1 /* 2 * Copyright 2017 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Rafał Miłecki <zajec5@gmail.com> 23 * Alex Deucher <alexdeucher@gmail.com> 24 */ 25 26 #include "amdgpu.h" 27 #include "amdgpu_drv.h" 28 #include "amdgpu_pm.h" 29 #include "amdgpu_dpm.h" 30 #include "atom.h" 31 #include <linux/pci.h> 32 #include <linux/hwmon.h> 33 #include <linux/hwmon-sysfs.h> 34 #include <linux/nospec.h> 35 #include <linux/pm_runtime.h> 36 #include <asm/processor.h> 37 38 static const struct cg_flag_name clocks[] = { 39 {AMD_CG_SUPPORT_GFX_FGCG, "Graphics Fine Grain Clock Gating"}, 40 {AMD_CG_SUPPORT_GFX_MGCG, "Graphics Medium Grain Clock Gating"}, 41 {AMD_CG_SUPPORT_GFX_MGLS, "Graphics Medium Grain memory Light Sleep"}, 42 {AMD_CG_SUPPORT_GFX_CGCG, "Graphics Coarse Grain Clock Gating"}, 43 {AMD_CG_SUPPORT_GFX_CGLS, "Graphics Coarse Grain memory Light Sleep"}, 44 {AMD_CG_SUPPORT_GFX_CGTS, "Graphics Coarse Grain Tree Shader Clock Gating"}, 45 {AMD_CG_SUPPORT_GFX_CGTS_LS, "Graphics Coarse Grain Tree Shader Light Sleep"}, 46 {AMD_CG_SUPPORT_GFX_CP_LS, "Graphics Command Processor Light Sleep"}, 47 {AMD_CG_SUPPORT_GFX_RLC_LS, "Graphics Run List Controller Light Sleep"}, 48 {AMD_CG_SUPPORT_GFX_3D_CGCG, "Graphics 3D Coarse Grain Clock Gating"}, 49 {AMD_CG_SUPPORT_GFX_3D_CGLS, "Graphics 3D Coarse Grain memory Light Sleep"}, 50 {AMD_CG_SUPPORT_MC_LS, "Memory Controller Light Sleep"}, 51 {AMD_CG_SUPPORT_MC_MGCG, "Memory Controller Medium Grain Clock Gating"}, 52 {AMD_CG_SUPPORT_SDMA_LS, "System Direct Memory Access Light Sleep"}, 53 {AMD_CG_SUPPORT_SDMA_MGCG, "System Direct Memory Access Medium Grain Clock Gating"}, 54 {AMD_CG_SUPPORT_BIF_MGCG, "Bus Interface Medium Grain Clock Gating"}, 55 {AMD_CG_SUPPORT_BIF_LS, "Bus Interface Light Sleep"}, 56 {AMD_CG_SUPPORT_UVD_MGCG, "Unified Video Decoder Medium Grain Clock Gating"}, 57 {AMD_CG_SUPPORT_VCE_MGCG, "Video Compression Engine Medium Grain Clock Gating"}, 58 {AMD_CG_SUPPORT_HDP_LS, "Host Data Path Light Sleep"}, 59 {AMD_CG_SUPPORT_HDP_MGCG, "Host Data Path Medium Grain Clock Gating"}, 60 {AMD_CG_SUPPORT_DRM_MGCG, "Digital Right Management Medium Grain Clock Gating"}, 61 {AMD_CG_SUPPORT_DRM_LS, "Digital Right Management Light Sleep"}, 62 {AMD_CG_SUPPORT_ROM_MGCG, "Rom Medium Grain Clock Gating"}, 63 {AMD_CG_SUPPORT_DF_MGCG, "Data Fabric Medium Grain Clock Gating"}, 64 {AMD_CG_SUPPORT_VCN_MGCG, "VCN Medium Grain Clock Gating"}, 65 {AMD_CG_SUPPORT_HDP_DS, "Host Data Path Deep Sleep"}, 66 {AMD_CG_SUPPORT_HDP_SD, "Host Data Path Shutdown"}, 67 {AMD_CG_SUPPORT_IH_CG, "Interrupt Handler Clock Gating"}, 68 {AMD_CG_SUPPORT_JPEG_MGCG, "JPEG Medium Grain Clock Gating"}, 69 {AMD_CG_SUPPORT_REPEATER_FGCG, "Repeater Fine Grain Clock Gating"}, 70 {AMD_CG_SUPPORT_GFX_PERF_CLK, "Perfmon Clock Gating"}, 71 {AMD_CG_SUPPORT_ATHUB_MGCG, "Address Translation Hub Medium Grain Clock Gating"}, 72 {AMD_CG_SUPPORT_ATHUB_LS, "Address Translation Hub Light Sleep"}, 73 {0, NULL}, 74 }; 75 76 static const struct hwmon_temp_label { 77 enum PP_HWMON_TEMP channel; 78 const char *label; 79 } temp_label[] = { 80 {PP_TEMP_EDGE, "edge"}, 81 {PP_TEMP_JUNCTION, "junction"}, 82 {PP_TEMP_MEM, "mem"}, 83 }; 84 85 const char * const amdgpu_pp_profile_name[] = { 86 "BOOTUP_DEFAULT", 87 "3D_FULL_SCREEN", 88 "POWER_SAVING", 89 "VIDEO", 90 "VR", 91 "COMPUTE", 92 "CUSTOM", 93 "WINDOW_3D", 94 "CAPPED", 95 "UNCAPPED", 96 }; 97 98 /** 99 * DOC: power_dpm_state 100 * 101 * The power_dpm_state file is a legacy interface and is only provided for 102 * backwards compatibility. The amdgpu driver provides a sysfs API for adjusting 103 * certain power related parameters. The file power_dpm_state is used for this. 104 * It accepts the following arguments: 105 * 106 * - battery 107 * 108 * - balanced 109 * 110 * - performance 111 * 112 * battery 113 * 114 * On older GPUs, the vbios provided a special power state for battery 115 * operation. Selecting battery switched to this state. This is no 116 * longer provided on newer GPUs so the option does nothing in that case. 117 * 118 * balanced 119 * 120 * On older GPUs, the vbios provided a special power state for balanced 121 * operation. Selecting balanced switched to this state. This is no 122 * longer provided on newer GPUs so the option does nothing in that case. 123 * 124 * performance 125 * 126 * On older GPUs, the vbios provided a special power state for performance 127 * operation. Selecting performance switched to this state. This is no 128 * longer provided on newer GPUs so the option does nothing in that case. 129 * 130 */ 131 132 static ssize_t amdgpu_get_power_dpm_state(struct device *dev, 133 struct device_attribute *attr, 134 char *buf) 135 { 136 struct drm_device *ddev = dev_get_drvdata(dev); 137 struct amdgpu_device *adev = drm_to_adev(ddev); 138 enum amd_pm_state_type pm; 139 int ret; 140 141 if (amdgpu_in_reset(adev)) 142 return -EPERM; 143 if (adev->in_suspend && !adev->in_runpm) 144 return -EPERM; 145 146 ret = pm_runtime_get_sync(ddev->dev); 147 if (ret < 0) { 148 pm_runtime_put_autosuspend(ddev->dev); 149 return ret; 150 } 151 152 amdgpu_dpm_get_current_power_state(adev, &pm); 153 154 pm_runtime_mark_last_busy(ddev->dev); 155 pm_runtime_put_autosuspend(ddev->dev); 156 157 return sysfs_emit(buf, "%s\n", 158 (pm == POWER_STATE_TYPE_BATTERY) ? "battery" : 159 (pm == POWER_STATE_TYPE_BALANCED) ? "balanced" : "performance"); 160 } 161 162 static ssize_t amdgpu_set_power_dpm_state(struct device *dev, 163 struct device_attribute *attr, 164 const char *buf, 165 size_t count) 166 { 167 struct drm_device *ddev = dev_get_drvdata(dev); 168 struct amdgpu_device *adev = drm_to_adev(ddev); 169 enum amd_pm_state_type state; 170 int ret; 171 172 if (amdgpu_in_reset(adev)) 173 return -EPERM; 174 if (adev->in_suspend && !adev->in_runpm) 175 return -EPERM; 176 177 if (strncmp("battery", buf, strlen("battery")) == 0) 178 state = POWER_STATE_TYPE_BATTERY; 179 else if (strncmp("balanced", buf, strlen("balanced")) == 0) 180 state = POWER_STATE_TYPE_BALANCED; 181 else if (strncmp("performance", buf, strlen("performance")) == 0) 182 state = POWER_STATE_TYPE_PERFORMANCE; 183 else 184 return -EINVAL; 185 186 ret = pm_runtime_get_sync(ddev->dev); 187 if (ret < 0) { 188 pm_runtime_put_autosuspend(ddev->dev); 189 return ret; 190 } 191 192 amdgpu_dpm_set_power_state(adev, state); 193 194 pm_runtime_mark_last_busy(ddev->dev); 195 pm_runtime_put_autosuspend(ddev->dev); 196 197 return count; 198 } 199 200 201 /** 202 * DOC: power_dpm_force_performance_level 203 * 204 * The amdgpu driver provides a sysfs API for adjusting certain power 205 * related parameters. The file power_dpm_force_performance_level is 206 * used for this. It accepts the following arguments: 207 * 208 * - auto 209 * 210 * - low 211 * 212 * - high 213 * 214 * - manual 215 * 216 * - profile_standard 217 * 218 * - profile_min_sclk 219 * 220 * - profile_min_mclk 221 * 222 * - profile_peak 223 * 224 * auto 225 * 226 * When auto is selected, the driver will attempt to dynamically select 227 * the optimal power profile for current conditions in the driver. 228 * 229 * low 230 * 231 * When low is selected, the clocks are forced to the lowest power state. 232 * 233 * high 234 * 235 * When high is selected, the clocks are forced to the highest power state. 236 * 237 * manual 238 * 239 * When manual is selected, the user can manually adjust which power states 240 * are enabled for each clock domain via the sysfs pp_dpm_mclk, pp_dpm_sclk, 241 * and pp_dpm_pcie files and adjust the power state transition heuristics 242 * via the pp_power_profile_mode sysfs file. 243 * 244 * profile_standard 245 * profile_min_sclk 246 * profile_min_mclk 247 * profile_peak 248 * 249 * When the profiling modes are selected, clock and power gating are 250 * disabled and the clocks are set for different profiling cases. This 251 * mode is recommended for profiling specific work loads where you do 252 * not want clock or power gating for clock fluctuation to interfere 253 * with your results. profile_standard sets the clocks to a fixed clock 254 * level which varies from asic to asic. profile_min_sclk forces the sclk 255 * to the lowest level. profile_min_mclk forces the mclk to the lowest level. 256 * profile_peak sets all clocks (mclk, sclk, pcie) to the highest levels. 257 * 258 */ 259 260 static ssize_t amdgpu_get_power_dpm_force_performance_level(struct device *dev, 261 struct device_attribute *attr, 262 char *buf) 263 { 264 struct drm_device *ddev = dev_get_drvdata(dev); 265 struct amdgpu_device *adev = drm_to_adev(ddev); 266 enum amd_dpm_forced_level level = 0xff; 267 int ret; 268 269 if (amdgpu_in_reset(adev)) 270 return -EPERM; 271 if (adev->in_suspend && !adev->in_runpm) 272 return -EPERM; 273 274 ret = pm_runtime_get_sync(ddev->dev); 275 if (ret < 0) { 276 pm_runtime_put_autosuspend(ddev->dev); 277 return ret; 278 } 279 280 level = amdgpu_dpm_get_performance_level(adev); 281 282 pm_runtime_mark_last_busy(ddev->dev); 283 pm_runtime_put_autosuspend(ddev->dev); 284 285 return sysfs_emit(buf, "%s\n", 286 (level == AMD_DPM_FORCED_LEVEL_AUTO) ? "auto" : 287 (level == AMD_DPM_FORCED_LEVEL_LOW) ? "low" : 288 (level == AMD_DPM_FORCED_LEVEL_HIGH) ? "high" : 289 (level == AMD_DPM_FORCED_LEVEL_MANUAL) ? "manual" : 290 (level == AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD) ? "profile_standard" : 291 (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) ? "profile_min_sclk" : 292 (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK) ? "profile_min_mclk" : 293 (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) ? "profile_peak" : 294 (level == AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM) ? "perf_determinism" : 295 "unknown"); 296 } 297 298 static ssize_t amdgpu_set_power_dpm_force_performance_level(struct device *dev, 299 struct device_attribute *attr, 300 const char *buf, 301 size_t count) 302 { 303 struct drm_device *ddev = dev_get_drvdata(dev); 304 struct amdgpu_device *adev = drm_to_adev(ddev); 305 enum amd_dpm_forced_level level; 306 int ret = 0; 307 308 if (amdgpu_in_reset(adev)) 309 return -EPERM; 310 if (adev->in_suspend && !adev->in_runpm) 311 return -EPERM; 312 313 if (strncmp("low", buf, strlen("low")) == 0) { 314 level = AMD_DPM_FORCED_LEVEL_LOW; 315 } else if (strncmp("high", buf, strlen("high")) == 0) { 316 level = AMD_DPM_FORCED_LEVEL_HIGH; 317 } else if (strncmp("auto", buf, strlen("auto")) == 0) { 318 level = AMD_DPM_FORCED_LEVEL_AUTO; 319 } else if (strncmp("manual", buf, strlen("manual")) == 0) { 320 level = AMD_DPM_FORCED_LEVEL_MANUAL; 321 } else if (strncmp("profile_exit", buf, strlen("profile_exit")) == 0) { 322 level = AMD_DPM_FORCED_LEVEL_PROFILE_EXIT; 323 } else if (strncmp("profile_standard", buf, strlen("profile_standard")) == 0) { 324 level = AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD; 325 } else if (strncmp("profile_min_sclk", buf, strlen("profile_min_sclk")) == 0) { 326 level = AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK; 327 } else if (strncmp("profile_min_mclk", buf, strlen("profile_min_mclk")) == 0) { 328 level = AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK; 329 } else if (strncmp("profile_peak", buf, strlen("profile_peak")) == 0) { 330 level = AMD_DPM_FORCED_LEVEL_PROFILE_PEAK; 331 } else if (strncmp("perf_determinism", buf, strlen("perf_determinism")) == 0) { 332 level = AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM; 333 } else { 334 return -EINVAL; 335 } 336 337 ret = pm_runtime_get_sync(ddev->dev); 338 if (ret < 0) { 339 pm_runtime_put_autosuspend(ddev->dev); 340 return ret; 341 } 342 343 mutex_lock(&adev->pm.stable_pstate_ctx_lock); 344 if (amdgpu_dpm_force_performance_level(adev, level)) { 345 pm_runtime_mark_last_busy(ddev->dev); 346 pm_runtime_put_autosuspend(ddev->dev); 347 mutex_unlock(&adev->pm.stable_pstate_ctx_lock); 348 return -EINVAL; 349 } 350 /* override whatever a user ctx may have set */ 351 adev->pm.stable_pstate_ctx = NULL; 352 mutex_unlock(&adev->pm.stable_pstate_ctx_lock); 353 354 pm_runtime_mark_last_busy(ddev->dev); 355 pm_runtime_put_autosuspend(ddev->dev); 356 357 return count; 358 } 359 360 static ssize_t amdgpu_get_pp_num_states(struct device *dev, 361 struct device_attribute *attr, 362 char *buf) 363 { 364 struct drm_device *ddev = dev_get_drvdata(dev); 365 struct amdgpu_device *adev = drm_to_adev(ddev); 366 struct pp_states_info data; 367 uint32_t i; 368 int buf_len, ret; 369 370 if (amdgpu_in_reset(adev)) 371 return -EPERM; 372 if (adev->in_suspend && !adev->in_runpm) 373 return -EPERM; 374 375 ret = pm_runtime_get_sync(ddev->dev); 376 if (ret < 0) { 377 pm_runtime_put_autosuspend(ddev->dev); 378 return ret; 379 } 380 381 if (amdgpu_dpm_get_pp_num_states(adev, &data)) 382 memset(&data, 0, sizeof(data)); 383 384 pm_runtime_mark_last_busy(ddev->dev); 385 pm_runtime_put_autosuspend(ddev->dev); 386 387 buf_len = sysfs_emit(buf, "states: %d\n", data.nums); 388 for (i = 0; i < data.nums; i++) 389 buf_len += sysfs_emit_at(buf, buf_len, "%d %s\n", i, 390 (data.states[i] == POWER_STATE_TYPE_INTERNAL_BOOT) ? "boot" : 391 (data.states[i] == POWER_STATE_TYPE_BATTERY) ? "battery" : 392 (data.states[i] == POWER_STATE_TYPE_BALANCED) ? "balanced" : 393 (data.states[i] == POWER_STATE_TYPE_PERFORMANCE) ? "performance" : "default"); 394 395 return buf_len; 396 } 397 398 static ssize_t amdgpu_get_pp_cur_state(struct device *dev, 399 struct device_attribute *attr, 400 char *buf) 401 { 402 struct drm_device *ddev = dev_get_drvdata(dev); 403 struct amdgpu_device *adev = drm_to_adev(ddev); 404 struct pp_states_info data = {0}; 405 enum amd_pm_state_type pm = 0; 406 int i = 0, ret = 0; 407 408 if (amdgpu_in_reset(adev)) 409 return -EPERM; 410 if (adev->in_suspend && !adev->in_runpm) 411 return -EPERM; 412 413 ret = pm_runtime_get_sync(ddev->dev); 414 if (ret < 0) { 415 pm_runtime_put_autosuspend(ddev->dev); 416 return ret; 417 } 418 419 amdgpu_dpm_get_current_power_state(adev, &pm); 420 421 ret = amdgpu_dpm_get_pp_num_states(adev, &data); 422 423 pm_runtime_mark_last_busy(ddev->dev); 424 pm_runtime_put_autosuspend(ddev->dev); 425 426 if (ret) 427 return ret; 428 429 for (i = 0; i < data.nums; i++) { 430 if (pm == data.states[i]) 431 break; 432 } 433 434 if (i == data.nums) 435 i = -EINVAL; 436 437 return sysfs_emit(buf, "%d\n", i); 438 } 439 440 static ssize_t amdgpu_get_pp_force_state(struct device *dev, 441 struct device_attribute *attr, 442 char *buf) 443 { 444 struct drm_device *ddev = dev_get_drvdata(dev); 445 struct amdgpu_device *adev = drm_to_adev(ddev); 446 447 if (amdgpu_in_reset(adev)) 448 return -EPERM; 449 if (adev->in_suspend && !adev->in_runpm) 450 return -EPERM; 451 452 if (adev->pm.pp_force_state_enabled) 453 return amdgpu_get_pp_cur_state(dev, attr, buf); 454 else 455 return sysfs_emit(buf, "\n"); 456 } 457 458 static ssize_t amdgpu_set_pp_force_state(struct device *dev, 459 struct device_attribute *attr, 460 const char *buf, 461 size_t count) 462 { 463 struct drm_device *ddev = dev_get_drvdata(dev); 464 struct amdgpu_device *adev = drm_to_adev(ddev); 465 enum amd_pm_state_type state = 0; 466 struct pp_states_info data; 467 unsigned long idx; 468 int ret; 469 470 if (amdgpu_in_reset(adev)) 471 return -EPERM; 472 if (adev->in_suspend && !adev->in_runpm) 473 return -EPERM; 474 475 adev->pm.pp_force_state_enabled = false; 476 477 if (strlen(buf) == 1) 478 return count; 479 480 ret = kstrtoul(buf, 0, &idx); 481 if (ret || idx >= ARRAY_SIZE(data.states)) 482 return -EINVAL; 483 484 idx = array_index_nospec(idx, ARRAY_SIZE(data.states)); 485 486 ret = pm_runtime_get_sync(ddev->dev); 487 if (ret < 0) { 488 pm_runtime_put_autosuspend(ddev->dev); 489 return ret; 490 } 491 492 ret = amdgpu_dpm_get_pp_num_states(adev, &data); 493 if (ret) 494 goto err_out; 495 496 state = data.states[idx]; 497 498 /* only set user selected power states */ 499 if (state != POWER_STATE_TYPE_INTERNAL_BOOT && 500 state != POWER_STATE_TYPE_DEFAULT) { 501 ret = amdgpu_dpm_dispatch_task(adev, 502 AMD_PP_TASK_ENABLE_USER_STATE, &state); 503 if (ret) 504 goto err_out; 505 506 adev->pm.pp_force_state_enabled = true; 507 } 508 509 pm_runtime_mark_last_busy(ddev->dev); 510 pm_runtime_put_autosuspend(ddev->dev); 511 512 return count; 513 514 err_out: 515 pm_runtime_mark_last_busy(ddev->dev); 516 pm_runtime_put_autosuspend(ddev->dev); 517 return ret; 518 } 519 520 /** 521 * DOC: pp_table 522 * 523 * The amdgpu driver provides a sysfs API for uploading new powerplay 524 * tables. The file pp_table is used for this. Reading the file 525 * will dump the current power play table. Writing to the file 526 * will attempt to upload a new powerplay table and re-initialize 527 * powerplay using that new table. 528 * 529 */ 530 531 static ssize_t amdgpu_get_pp_table(struct device *dev, 532 struct device_attribute *attr, 533 char *buf) 534 { 535 struct drm_device *ddev = dev_get_drvdata(dev); 536 struct amdgpu_device *adev = drm_to_adev(ddev); 537 char *table = NULL; 538 int size, ret; 539 540 if (amdgpu_in_reset(adev)) 541 return -EPERM; 542 if (adev->in_suspend && !adev->in_runpm) 543 return -EPERM; 544 545 ret = pm_runtime_get_sync(ddev->dev); 546 if (ret < 0) { 547 pm_runtime_put_autosuspend(ddev->dev); 548 return ret; 549 } 550 551 size = amdgpu_dpm_get_pp_table(adev, &table); 552 553 pm_runtime_mark_last_busy(ddev->dev); 554 pm_runtime_put_autosuspend(ddev->dev); 555 556 if (size <= 0) 557 return size; 558 559 if (size >= PAGE_SIZE) 560 size = PAGE_SIZE - 1; 561 562 memcpy(buf, table, size); 563 564 return size; 565 } 566 567 static ssize_t amdgpu_set_pp_table(struct device *dev, 568 struct device_attribute *attr, 569 const char *buf, 570 size_t count) 571 { 572 struct drm_device *ddev = dev_get_drvdata(dev); 573 struct amdgpu_device *adev = drm_to_adev(ddev); 574 int ret = 0; 575 576 if (amdgpu_in_reset(adev)) 577 return -EPERM; 578 if (adev->in_suspend && !adev->in_runpm) 579 return -EPERM; 580 581 ret = pm_runtime_get_sync(ddev->dev); 582 if (ret < 0) { 583 pm_runtime_put_autosuspend(ddev->dev); 584 return ret; 585 } 586 587 ret = amdgpu_dpm_set_pp_table(adev, buf, count); 588 589 pm_runtime_mark_last_busy(ddev->dev); 590 pm_runtime_put_autosuspend(ddev->dev); 591 592 if (ret) 593 return ret; 594 595 return count; 596 } 597 598 /** 599 * DOC: pp_od_clk_voltage 600 * 601 * The amdgpu driver provides a sysfs API for adjusting the clocks and voltages 602 * in each power level within a power state. The pp_od_clk_voltage is used for 603 * this. 604 * 605 * Note that the actual memory controller clock rate are exposed, not 606 * the effective memory clock of the DRAMs. To translate it, use the 607 * following formula: 608 * 609 * Clock conversion (Mhz): 610 * 611 * HBM: effective_memory_clock = memory_controller_clock * 1 612 * 613 * G5: effective_memory_clock = memory_controller_clock * 1 614 * 615 * G6: effective_memory_clock = memory_controller_clock * 2 616 * 617 * DRAM data rate (MT/s): 618 * 619 * HBM: effective_memory_clock * 2 = data_rate 620 * 621 * G5: effective_memory_clock * 4 = data_rate 622 * 623 * G6: effective_memory_clock * 8 = data_rate 624 * 625 * Bandwidth (MB/s): 626 * 627 * data_rate * vram_bit_width / 8 = memory_bandwidth 628 * 629 * Some examples: 630 * 631 * G5 on RX460: 632 * 633 * memory_controller_clock = 1750 Mhz 634 * 635 * effective_memory_clock = 1750 Mhz * 1 = 1750 Mhz 636 * 637 * data rate = 1750 * 4 = 7000 MT/s 638 * 639 * memory_bandwidth = 7000 * 128 bits / 8 = 112000 MB/s 640 * 641 * G6 on RX5700: 642 * 643 * memory_controller_clock = 875 Mhz 644 * 645 * effective_memory_clock = 875 Mhz * 2 = 1750 Mhz 646 * 647 * data rate = 1750 * 8 = 14000 MT/s 648 * 649 * memory_bandwidth = 14000 * 256 bits / 8 = 448000 MB/s 650 * 651 * < For Vega10 and previous ASICs > 652 * 653 * Reading the file will display: 654 * 655 * - a list of engine clock levels and voltages labeled OD_SCLK 656 * 657 * - a list of memory clock levels and voltages labeled OD_MCLK 658 * 659 * - a list of valid ranges for sclk, mclk, and voltage labeled OD_RANGE 660 * 661 * To manually adjust these settings, first select manual using 662 * power_dpm_force_performance_level. Enter a new value for each 663 * level by writing a string that contains "s/m level clock voltage" to 664 * the file. E.g., "s 1 500 820" will update sclk level 1 to be 500 MHz 665 * at 820 mV; "m 0 350 810" will update mclk level 0 to be 350 MHz at 666 * 810 mV. When you have edited all of the states as needed, write 667 * "c" (commit) to the file to commit your changes. If you want to reset to the 668 * default power levels, write "r" (reset) to the file to reset them. 669 * 670 * 671 * < For Vega20 and newer ASICs > 672 * 673 * Reading the file will display: 674 * 675 * - minimum and maximum engine clock labeled OD_SCLK 676 * 677 * - minimum(not available for Vega20 and Navi1x) and maximum memory 678 * clock labeled OD_MCLK 679 * 680 * - three <frequency, voltage> points labeled OD_VDDC_CURVE. 681 * They can be used to calibrate the sclk voltage curve. 682 * 683 * - voltage offset(in mV) applied on target voltage calculation. 684 * This is available for Sienna Cichlid, Navy Flounder and Dimgrey 685 * Cavefish. For these ASICs, the target voltage calculation can be 686 * illustrated by "voltage = voltage calculated from v/f curve + 687 * overdrive vddgfx offset" 688 * 689 * - a list of valid ranges for sclk, mclk, and voltage curve points 690 * labeled OD_RANGE 691 * 692 * < For APUs > 693 * 694 * Reading the file will display: 695 * 696 * - minimum and maximum engine clock labeled OD_SCLK 697 * 698 * - a list of valid ranges for sclk labeled OD_RANGE 699 * 700 * < For VanGogh > 701 * 702 * Reading the file will display: 703 * 704 * - minimum and maximum engine clock labeled OD_SCLK 705 * - minimum and maximum core clocks labeled OD_CCLK 706 * 707 * - a list of valid ranges for sclk and cclk labeled OD_RANGE 708 * 709 * To manually adjust these settings: 710 * 711 * - First select manual using power_dpm_force_performance_level 712 * 713 * - For clock frequency setting, enter a new value by writing a 714 * string that contains "s/m index clock" to the file. The index 715 * should be 0 if to set minimum clock. And 1 if to set maximum 716 * clock. E.g., "s 0 500" will update minimum sclk to be 500 MHz. 717 * "m 1 800" will update maximum mclk to be 800Mhz. For core 718 * clocks on VanGogh, the string contains "p core index clock". 719 * E.g., "p 2 0 800" would set the minimum core clock on core 720 * 2 to 800Mhz. 721 * 722 * For sclk voltage curve, enter the new values by writing a 723 * string that contains "vc point clock voltage" to the file. The 724 * points are indexed by 0, 1 and 2. E.g., "vc 0 300 600" will 725 * update point1 with clock set as 300Mhz and voltage as 726 * 600mV. "vc 2 1000 1000" will update point3 with clock set 727 * as 1000Mhz and voltage 1000mV. 728 * 729 * To update the voltage offset applied for gfxclk/voltage calculation, 730 * enter the new value by writing a string that contains "vo offset". 731 * This is supported by Sienna Cichlid, Navy Flounder and Dimgrey Cavefish. 732 * And the offset can be a positive or negative value. 733 * 734 * - When you have edited all of the states as needed, write "c" (commit) 735 * to the file to commit your changes 736 * 737 * - If you want to reset to the default power levels, write "r" (reset) 738 * to the file to reset them 739 * 740 */ 741 742 static ssize_t amdgpu_set_pp_od_clk_voltage(struct device *dev, 743 struct device_attribute *attr, 744 const char *buf, 745 size_t count) 746 { 747 struct drm_device *ddev = dev_get_drvdata(dev); 748 struct amdgpu_device *adev = drm_to_adev(ddev); 749 int ret; 750 uint32_t parameter_size = 0; 751 long parameter[64]; 752 char buf_cpy[128]; 753 char *tmp_str; 754 char *sub_str; 755 const char delimiter[3] = {' ', '\n', '\0'}; 756 uint32_t type; 757 758 if (amdgpu_in_reset(adev)) 759 return -EPERM; 760 if (adev->in_suspend && !adev->in_runpm) 761 return -EPERM; 762 763 if (count > 127) 764 return -EINVAL; 765 766 if (*buf == 's') 767 type = PP_OD_EDIT_SCLK_VDDC_TABLE; 768 else if (*buf == 'p') 769 type = PP_OD_EDIT_CCLK_VDDC_TABLE; 770 else if (*buf == 'm') 771 type = PP_OD_EDIT_MCLK_VDDC_TABLE; 772 else if(*buf == 'r') 773 type = PP_OD_RESTORE_DEFAULT_TABLE; 774 else if (*buf == 'c') 775 type = PP_OD_COMMIT_DPM_TABLE; 776 else if (!strncmp(buf, "vc", 2)) 777 type = PP_OD_EDIT_VDDC_CURVE; 778 else if (!strncmp(buf, "vo", 2)) 779 type = PP_OD_EDIT_VDDGFX_OFFSET; 780 else 781 return -EINVAL; 782 783 memcpy(buf_cpy, buf, count+1); 784 785 tmp_str = buf_cpy; 786 787 if ((type == PP_OD_EDIT_VDDC_CURVE) || 788 (type == PP_OD_EDIT_VDDGFX_OFFSET)) 789 tmp_str++; 790 while (isspace(*++tmp_str)); 791 792 while ((sub_str = strsep(&tmp_str, delimiter)) != NULL) { 793 if (strlen(sub_str) == 0) 794 continue; 795 ret = kstrtol(sub_str, 0, ¶meter[parameter_size]); 796 if (ret) 797 return -EINVAL; 798 parameter_size++; 799 800 while (isspace(*tmp_str)) 801 tmp_str++; 802 } 803 804 ret = pm_runtime_get_sync(ddev->dev); 805 if (ret < 0) { 806 pm_runtime_put_autosuspend(ddev->dev); 807 return ret; 808 } 809 810 if (amdgpu_dpm_set_fine_grain_clk_vol(adev, 811 type, 812 parameter, 813 parameter_size)) 814 goto err_out; 815 816 if (amdgpu_dpm_odn_edit_dpm_table(adev, type, 817 parameter, parameter_size)) 818 goto err_out; 819 820 if (type == PP_OD_COMMIT_DPM_TABLE) { 821 if (amdgpu_dpm_dispatch_task(adev, 822 AMD_PP_TASK_READJUST_POWER_STATE, 823 NULL)) 824 goto err_out; 825 } 826 827 pm_runtime_mark_last_busy(ddev->dev); 828 pm_runtime_put_autosuspend(ddev->dev); 829 830 return count; 831 832 err_out: 833 pm_runtime_mark_last_busy(ddev->dev); 834 pm_runtime_put_autosuspend(ddev->dev); 835 return -EINVAL; 836 } 837 838 static ssize_t amdgpu_get_pp_od_clk_voltage(struct device *dev, 839 struct device_attribute *attr, 840 char *buf) 841 { 842 struct drm_device *ddev = dev_get_drvdata(dev); 843 struct amdgpu_device *adev = drm_to_adev(ddev); 844 int size = 0; 845 int ret; 846 enum pp_clock_type od_clocks[6] = { 847 OD_SCLK, 848 OD_MCLK, 849 OD_VDDC_CURVE, 850 OD_RANGE, 851 OD_VDDGFX_OFFSET, 852 OD_CCLK, 853 }; 854 uint clk_index; 855 856 if (amdgpu_in_reset(adev)) 857 return -EPERM; 858 if (adev->in_suspend && !adev->in_runpm) 859 return -EPERM; 860 861 ret = pm_runtime_get_sync(ddev->dev); 862 if (ret < 0) { 863 pm_runtime_put_autosuspend(ddev->dev); 864 return ret; 865 } 866 867 for (clk_index = 0 ; clk_index < 6 ; clk_index++) { 868 ret = amdgpu_dpm_emit_clock_levels(adev, od_clocks[clk_index], buf, &size); 869 if (ret) 870 break; 871 } 872 if (ret == -ENOENT) { 873 size = amdgpu_dpm_print_clock_levels(adev, OD_SCLK, buf); 874 if (size > 0) { 875 size += amdgpu_dpm_print_clock_levels(adev, OD_MCLK, buf + size); 876 size += amdgpu_dpm_print_clock_levels(adev, OD_VDDC_CURVE, buf + size); 877 size += amdgpu_dpm_print_clock_levels(adev, OD_VDDGFX_OFFSET, buf + size); 878 size += amdgpu_dpm_print_clock_levels(adev, OD_RANGE, buf + size); 879 size += amdgpu_dpm_print_clock_levels(adev, OD_CCLK, buf + size); 880 } 881 } 882 883 if (size == 0) 884 size = sysfs_emit(buf, "\n"); 885 886 pm_runtime_mark_last_busy(ddev->dev); 887 pm_runtime_put_autosuspend(ddev->dev); 888 889 return size; 890 } 891 892 /** 893 * DOC: pp_features 894 * 895 * The amdgpu driver provides a sysfs API for adjusting what powerplay 896 * features to be enabled. The file pp_features is used for this. And 897 * this is only available for Vega10 and later dGPUs. 898 * 899 * Reading back the file will show you the followings: 900 * - Current ppfeature masks 901 * - List of the all supported powerplay features with their naming, 902 * bitmasks and enablement status('Y'/'N' means "enabled"/"disabled"). 903 * 904 * To manually enable or disable a specific feature, just set or clear 905 * the corresponding bit from original ppfeature masks and input the 906 * new ppfeature masks. 907 */ 908 static ssize_t amdgpu_set_pp_features(struct device *dev, 909 struct device_attribute *attr, 910 const char *buf, 911 size_t count) 912 { 913 struct drm_device *ddev = dev_get_drvdata(dev); 914 struct amdgpu_device *adev = drm_to_adev(ddev); 915 uint64_t featuremask; 916 int ret; 917 918 if (amdgpu_in_reset(adev)) 919 return -EPERM; 920 if (adev->in_suspend && !adev->in_runpm) 921 return -EPERM; 922 923 ret = kstrtou64(buf, 0, &featuremask); 924 if (ret) 925 return -EINVAL; 926 927 ret = pm_runtime_get_sync(ddev->dev); 928 if (ret < 0) { 929 pm_runtime_put_autosuspend(ddev->dev); 930 return ret; 931 } 932 933 ret = amdgpu_dpm_set_ppfeature_status(adev, featuremask); 934 935 pm_runtime_mark_last_busy(ddev->dev); 936 pm_runtime_put_autosuspend(ddev->dev); 937 938 if (ret) 939 return -EINVAL; 940 941 return count; 942 } 943 944 static ssize_t amdgpu_get_pp_features(struct device *dev, 945 struct device_attribute *attr, 946 char *buf) 947 { 948 struct drm_device *ddev = dev_get_drvdata(dev); 949 struct amdgpu_device *adev = drm_to_adev(ddev); 950 ssize_t size; 951 int ret; 952 953 if (amdgpu_in_reset(adev)) 954 return -EPERM; 955 if (adev->in_suspend && !adev->in_runpm) 956 return -EPERM; 957 958 ret = pm_runtime_get_sync(ddev->dev); 959 if (ret < 0) { 960 pm_runtime_put_autosuspend(ddev->dev); 961 return ret; 962 } 963 964 size = amdgpu_dpm_get_ppfeature_status(adev, buf); 965 if (size <= 0) 966 size = sysfs_emit(buf, "\n"); 967 968 pm_runtime_mark_last_busy(ddev->dev); 969 pm_runtime_put_autosuspend(ddev->dev); 970 971 return size; 972 } 973 974 /** 975 * DOC: pp_dpm_sclk pp_dpm_mclk pp_dpm_socclk pp_dpm_fclk pp_dpm_dcefclk pp_dpm_pcie 976 * 977 * The amdgpu driver provides a sysfs API for adjusting what power levels 978 * are enabled for a given power state. The files pp_dpm_sclk, pp_dpm_mclk, 979 * pp_dpm_socclk, pp_dpm_fclk, pp_dpm_dcefclk and pp_dpm_pcie are used for 980 * this. 981 * 982 * pp_dpm_socclk and pp_dpm_dcefclk interfaces are only available for 983 * Vega10 and later ASICs. 984 * pp_dpm_fclk interface is only available for Vega20 and later ASICs. 985 * 986 * Reading back the files will show you the available power levels within 987 * the power state and the clock information for those levels. 988 * 989 * To manually adjust these states, first select manual using 990 * power_dpm_force_performance_level. 991 * Secondly, enter a new value for each level by inputing a string that 992 * contains " echo xx xx xx > pp_dpm_sclk/mclk/pcie" 993 * E.g., 994 * 995 * .. code-block:: bash 996 * 997 * echo "4 5 6" > pp_dpm_sclk 998 * 999 * will enable sclk levels 4, 5, and 6. 1000 * 1001 * NOTE: change to the dcefclk max dpm level is not supported now 1002 */ 1003 1004 static ssize_t amdgpu_get_pp_dpm_clock(struct device *dev, 1005 enum pp_clock_type type, 1006 char *buf) 1007 { 1008 struct drm_device *ddev = dev_get_drvdata(dev); 1009 struct amdgpu_device *adev = drm_to_adev(ddev); 1010 int size = 0; 1011 int ret = 0; 1012 1013 if (amdgpu_in_reset(adev)) 1014 return -EPERM; 1015 if (adev->in_suspend && !adev->in_runpm) 1016 return -EPERM; 1017 1018 ret = pm_runtime_get_sync(ddev->dev); 1019 if (ret < 0) { 1020 pm_runtime_put_autosuspend(ddev->dev); 1021 return ret; 1022 } 1023 1024 ret = amdgpu_dpm_emit_clock_levels(adev, type, buf, &size); 1025 if (ret == -ENOENT) 1026 size = amdgpu_dpm_print_clock_levels(adev, type, buf); 1027 1028 if (size == 0) 1029 size = sysfs_emit(buf, "\n"); 1030 1031 pm_runtime_mark_last_busy(ddev->dev); 1032 pm_runtime_put_autosuspend(ddev->dev); 1033 1034 return size; 1035 } 1036 1037 /* 1038 * Worst case: 32 bits individually specified, in octal at 12 characters 1039 * per line (+1 for \n). 1040 */ 1041 #define AMDGPU_MASK_BUF_MAX (32 * 13) 1042 1043 static ssize_t amdgpu_read_mask(const char *buf, size_t count, uint32_t *mask) 1044 { 1045 int ret; 1046 unsigned long level; 1047 char *sub_str = NULL; 1048 char *tmp; 1049 char buf_cpy[AMDGPU_MASK_BUF_MAX + 1]; 1050 const char delimiter[3] = {' ', '\n', '\0'}; 1051 size_t bytes; 1052 1053 *mask = 0; 1054 1055 bytes = min(count, sizeof(buf_cpy) - 1); 1056 memcpy(buf_cpy, buf, bytes); 1057 buf_cpy[bytes] = '\0'; 1058 tmp = buf_cpy; 1059 while ((sub_str = strsep(&tmp, delimiter)) != NULL) { 1060 if (strlen(sub_str)) { 1061 ret = kstrtoul(sub_str, 0, &level); 1062 if (ret || level > 31) 1063 return -EINVAL; 1064 *mask |= 1 << level; 1065 } else 1066 break; 1067 } 1068 1069 return 0; 1070 } 1071 1072 static ssize_t amdgpu_set_pp_dpm_clock(struct device *dev, 1073 enum pp_clock_type type, 1074 const char *buf, 1075 size_t count) 1076 { 1077 struct drm_device *ddev = dev_get_drvdata(dev); 1078 struct amdgpu_device *adev = drm_to_adev(ddev); 1079 int ret; 1080 uint32_t mask = 0; 1081 1082 if (amdgpu_in_reset(adev)) 1083 return -EPERM; 1084 if (adev->in_suspend && !adev->in_runpm) 1085 return -EPERM; 1086 1087 ret = amdgpu_read_mask(buf, count, &mask); 1088 if (ret) 1089 return ret; 1090 1091 ret = pm_runtime_get_sync(ddev->dev); 1092 if (ret < 0) { 1093 pm_runtime_put_autosuspend(ddev->dev); 1094 return ret; 1095 } 1096 1097 ret = amdgpu_dpm_force_clock_level(adev, type, mask); 1098 1099 pm_runtime_mark_last_busy(ddev->dev); 1100 pm_runtime_put_autosuspend(ddev->dev); 1101 1102 if (ret) 1103 return -EINVAL; 1104 1105 return count; 1106 } 1107 1108 static ssize_t amdgpu_get_pp_dpm_sclk(struct device *dev, 1109 struct device_attribute *attr, 1110 char *buf) 1111 { 1112 return amdgpu_get_pp_dpm_clock(dev, PP_SCLK, buf); 1113 } 1114 1115 static ssize_t amdgpu_set_pp_dpm_sclk(struct device *dev, 1116 struct device_attribute *attr, 1117 const char *buf, 1118 size_t count) 1119 { 1120 return amdgpu_set_pp_dpm_clock(dev, PP_SCLK, buf, count); 1121 } 1122 1123 static ssize_t amdgpu_get_pp_dpm_mclk(struct device *dev, 1124 struct device_attribute *attr, 1125 char *buf) 1126 { 1127 return amdgpu_get_pp_dpm_clock(dev, PP_MCLK, buf); 1128 } 1129 1130 static ssize_t amdgpu_set_pp_dpm_mclk(struct device *dev, 1131 struct device_attribute *attr, 1132 const char *buf, 1133 size_t count) 1134 { 1135 return amdgpu_set_pp_dpm_clock(dev, PP_MCLK, buf, count); 1136 } 1137 1138 static ssize_t amdgpu_get_pp_dpm_socclk(struct device *dev, 1139 struct device_attribute *attr, 1140 char *buf) 1141 { 1142 return amdgpu_get_pp_dpm_clock(dev, PP_SOCCLK, buf); 1143 } 1144 1145 static ssize_t amdgpu_set_pp_dpm_socclk(struct device *dev, 1146 struct device_attribute *attr, 1147 const char *buf, 1148 size_t count) 1149 { 1150 return amdgpu_set_pp_dpm_clock(dev, PP_SOCCLK, buf, count); 1151 } 1152 1153 static ssize_t amdgpu_get_pp_dpm_fclk(struct device *dev, 1154 struct device_attribute *attr, 1155 char *buf) 1156 { 1157 return amdgpu_get_pp_dpm_clock(dev, PP_FCLK, buf); 1158 } 1159 1160 static ssize_t amdgpu_set_pp_dpm_fclk(struct device *dev, 1161 struct device_attribute *attr, 1162 const char *buf, 1163 size_t count) 1164 { 1165 return amdgpu_set_pp_dpm_clock(dev, PP_FCLK, buf, count); 1166 } 1167 1168 static ssize_t amdgpu_get_pp_dpm_vclk(struct device *dev, 1169 struct device_attribute *attr, 1170 char *buf) 1171 { 1172 return amdgpu_get_pp_dpm_clock(dev, PP_VCLK, buf); 1173 } 1174 1175 static ssize_t amdgpu_set_pp_dpm_vclk(struct device *dev, 1176 struct device_attribute *attr, 1177 const char *buf, 1178 size_t count) 1179 { 1180 return amdgpu_set_pp_dpm_clock(dev, PP_VCLK, buf, count); 1181 } 1182 1183 static ssize_t amdgpu_get_pp_dpm_vclk1(struct device *dev, 1184 struct device_attribute *attr, 1185 char *buf) 1186 { 1187 return amdgpu_get_pp_dpm_clock(dev, PP_VCLK1, buf); 1188 } 1189 1190 static ssize_t amdgpu_set_pp_dpm_vclk1(struct device *dev, 1191 struct device_attribute *attr, 1192 const char *buf, 1193 size_t count) 1194 { 1195 return amdgpu_set_pp_dpm_clock(dev, PP_VCLK1, buf, count); 1196 } 1197 1198 static ssize_t amdgpu_get_pp_dpm_dclk(struct device *dev, 1199 struct device_attribute *attr, 1200 char *buf) 1201 { 1202 return amdgpu_get_pp_dpm_clock(dev, PP_DCLK, buf); 1203 } 1204 1205 static ssize_t amdgpu_set_pp_dpm_dclk(struct device *dev, 1206 struct device_attribute *attr, 1207 const char *buf, 1208 size_t count) 1209 { 1210 return amdgpu_set_pp_dpm_clock(dev, PP_DCLK, buf, count); 1211 } 1212 1213 static ssize_t amdgpu_get_pp_dpm_dclk1(struct device *dev, 1214 struct device_attribute *attr, 1215 char *buf) 1216 { 1217 return amdgpu_get_pp_dpm_clock(dev, PP_DCLK1, buf); 1218 } 1219 1220 static ssize_t amdgpu_set_pp_dpm_dclk1(struct device *dev, 1221 struct device_attribute *attr, 1222 const char *buf, 1223 size_t count) 1224 { 1225 return amdgpu_set_pp_dpm_clock(dev, PP_DCLK1, buf, count); 1226 } 1227 1228 static ssize_t amdgpu_get_pp_dpm_dcefclk(struct device *dev, 1229 struct device_attribute *attr, 1230 char *buf) 1231 { 1232 return amdgpu_get_pp_dpm_clock(dev, PP_DCEFCLK, buf); 1233 } 1234 1235 static ssize_t amdgpu_set_pp_dpm_dcefclk(struct device *dev, 1236 struct device_attribute *attr, 1237 const char *buf, 1238 size_t count) 1239 { 1240 return amdgpu_set_pp_dpm_clock(dev, PP_DCEFCLK, buf, count); 1241 } 1242 1243 static ssize_t amdgpu_get_pp_dpm_pcie(struct device *dev, 1244 struct device_attribute *attr, 1245 char *buf) 1246 { 1247 return amdgpu_get_pp_dpm_clock(dev, PP_PCIE, buf); 1248 } 1249 1250 static ssize_t amdgpu_set_pp_dpm_pcie(struct device *dev, 1251 struct device_attribute *attr, 1252 const char *buf, 1253 size_t count) 1254 { 1255 return amdgpu_set_pp_dpm_clock(dev, PP_PCIE, buf, count); 1256 } 1257 1258 static ssize_t amdgpu_get_pp_sclk_od(struct device *dev, 1259 struct device_attribute *attr, 1260 char *buf) 1261 { 1262 struct drm_device *ddev = dev_get_drvdata(dev); 1263 struct amdgpu_device *adev = drm_to_adev(ddev); 1264 uint32_t value = 0; 1265 int ret; 1266 1267 if (amdgpu_in_reset(adev)) 1268 return -EPERM; 1269 if (adev->in_suspend && !adev->in_runpm) 1270 return -EPERM; 1271 1272 ret = pm_runtime_get_sync(ddev->dev); 1273 if (ret < 0) { 1274 pm_runtime_put_autosuspend(ddev->dev); 1275 return ret; 1276 } 1277 1278 value = amdgpu_dpm_get_sclk_od(adev); 1279 1280 pm_runtime_mark_last_busy(ddev->dev); 1281 pm_runtime_put_autosuspend(ddev->dev); 1282 1283 return sysfs_emit(buf, "%d\n", value); 1284 } 1285 1286 static ssize_t amdgpu_set_pp_sclk_od(struct device *dev, 1287 struct device_attribute *attr, 1288 const char *buf, 1289 size_t count) 1290 { 1291 struct drm_device *ddev = dev_get_drvdata(dev); 1292 struct amdgpu_device *adev = drm_to_adev(ddev); 1293 int ret; 1294 long int value; 1295 1296 if (amdgpu_in_reset(adev)) 1297 return -EPERM; 1298 if (adev->in_suspend && !adev->in_runpm) 1299 return -EPERM; 1300 1301 ret = kstrtol(buf, 0, &value); 1302 1303 if (ret) 1304 return -EINVAL; 1305 1306 ret = pm_runtime_get_sync(ddev->dev); 1307 if (ret < 0) { 1308 pm_runtime_put_autosuspend(ddev->dev); 1309 return ret; 1310 } 1311 1312 amdgpu_dpm_set_sclk_od(adev, (uint32_t)value); 1313 1314 pm_runtime_mark_last_busy(ddev->dev); 1315 pm_runtime_put_autosuspend(ddev->dev); 1316 1317 return count; 1318 } 1319 1320 static ssize_t amdgpu_get_pp_mclk_od(struct device *dev, 1321 struct device_attribute *attr, 1322 char *buf) 1323 { 1324 struct drm_device *ddev = dev_get_drvdata(dev); 1325 struct amdgpu_device *adev = drm_to_adev(ddev); 1326 uint32_t value = 0; 1327 int ret; 1328 1329 if (amdgpu_in_reset(adev)) 1330 return -EPERM; 1331 if (adev->in_suspend && !adev->in_runpm) 1332 return -EPERM; 1333 1334 ret = pm_runtime_get_sync(ddev->dev); 1335 if (ret < 0) { 1336 pm_runtime_put_autosuspend(ddev->dev); 1337 return ret; 1338 } 1339 1340 value = amdgpu_dpm_get_mclk_od(adev); 1341 1342 pm_runtime_mark_last_busy(ddev->dev); 1343 pm_runtime_put_autosuspend(ddev->dev); 1344 1345 return sysfs_emit(buf, "%d\n", value); 1346 } 1347 1348 static ssize_t amdgpu_set_pp_mclk_od(struct device *dev, 1349 struct device_attribute *attr, 1350 const char *buf, 1351 size_t count) 1352 { 1353 struct drm_device *ddev = dev_get_drvdata(dev); 1354 struct amdgpu_device *adev = drm_to_adev(ddev); 1355 int ret; 1356 long int value; 1357 1358 if (amdgpu_in_reset(adev)) 1359 return -EPERM; 1360 if (adev->in_suspend && !adev->in_runpm) 1361 return -EPERM; 1362 1363 ret = kstrtol(buf, 0, &value); 1364 1365 if (ret) 1366 return -EINVAL; 1367 1368 ret = pm_runtime_get_sync(ddev->dev); 1369 if (ret < 0) { 1370 pm_runtime_put_autosuspend(ddev->dev); 1371 return ret; 1372 } 1373 1374 amdgpu_dpm_set_mclk_od(adev, (uint32_t)value); 1375 1376 pm_runtime_mark_last_busy(ddev->dev); 1377 pm_runtime_put_autosuspend(ddev->dev); 1378 1379 return count; 1380 } 1381 1382 /** 1383 * DOC: pp_power_profile_mode 1384 * 1385 * The amdgpu driver provides a sysfs API for adjusting the heuristics 1386 * related to switching between power levels in a power state. The file 1387 * pp_power_profile_mode is used for this. 1388 * 1389 * Reading this file outputs a list of all of the predefined power profiles 1390 * and the relevant heuristics settings for that profile. 1391 * 1392 * To select a profile or create a custom profile, first select manual using 1393 * power_dpm_force_performance_level. Writing the number of a predefined 1394 * profile to pp_power_profile_mode will enable those heuristics. To 1395 * create a custom set of heuristics, write a string of numbers to the file 1396 * starting with the number of the custom profile along with a setting 1397 * for each heuristic parameter. Due to differences across asic families 1398 * the heuristic parameters vary from family to family. 1399 * 1400 */ 1401 1402 static ssize_t amdgpu_get_pp_power_profile_mode(struct device *dev, 1403 struct device_attribute *attr, 1404 char *buf) 1405 { 1406 struct drm_device *ddev = dev_get_drvdata(dev); 1407 struct amdgpu_device *adev = drm_to_adev(ddev); 1408 ssize_t size; 1409 int ret; 1410 1411 if (amdgpu_in_reset(adev)) 1412 return -EPERM; 1413 if (adev->in_suspend && !adev->in_runpm) 1414 return -EPERM; 1415 1416 ret = pm_runtime_get_sync(ddev->dev); 1417 if (ret < 0) { 1418 pm_runtime_put_autosuspend(ddev->dev); 1419 return ret; 1420 } 1421 1422 size = amdgpu_dpm_get_power_profile_mode(adev, buf); 1423 if (size <= 0) 1424 size = sysfs_emit(buf, "\n"); 1425 1426 pm_runtime_mark_last_busy(ddev->dev); 1427 pm_runtime_put_autosuspend(ddev->dev); 1428 1429 return size; 1430 } 1431 1432 1433 static ssize_t amdgpu_set_pp_power_profile_mode(struct device *dev, 1434 struct device_attribute *attr, 1435 const char *buf, 1436 size_t count) 1437 { 1438 int ret; 1439 struct drm_device *ddev = dev_get_drvdata(dev); 1440 struct amdgpu_device *adev = drm_to_adev(ddev); 1441 uint32_t parameter_size = 0; 1442 long parameter[64]; 1443 char *sub_str, buf_cpy[128]; 1444 char *tmp_str; 1445 uint32_t i = 0; 1446 char tmp[2]; 1447 long int profile_mode = 0; 1448 const char delimiter[3] = {' ', '\n', '\0'}; 1449 1450 if (amdgpu_in_reset(adev)) 1451 return -EPERM; 1452 if (adev->in_suspend && !adev->in_runpm) 1453 return -EPERM; 1454 1455 tmp[0] = *(buf); 1456 tmp[1] = '\0'; 1457 ret = kstrtol(tmp, 0, &profile_mode); 1458 if (ret) 1459 return -EINVAL; 1460 1461 if (profile_mode == PP_SMC_POWER_PROFILE_CUSTOM) { 1462 if (count < 2 || count > 127) 1463 return -EINVAL; 1464 while (isspace(*++buf)) 1465 i++; 1466 memcpy(buf_cpy, buf, count-i); 1467 tmp_str = buf_cpy; 1468 while ((sub_str = strsep(&tmp_str, delimiter)) != NULL) { 1469 if (strlen(sub_str) == 0) 1470 continue; 1471 ret = kstrtol(sub_str, 0, ¶meter[parameter_size]); 1472 if (ret) 1473 return -EINVAL; 1474 parameter_size++; 1475 while (isspace(*tmp_str)) 1476 tmp_str++; 1477 } 1478 } 1479 parameter[parameter_size] = profile_mode; 1480 1481 ret = pm_runtime_get_sync(ddev->dev); 1482 if (ret < 0) { 1483 pm_runtime_put_autosuspend(ddev->dev); 1484 return ret; 1485 } 1486 1487 ret = amdgpu_dpm_set_power_profile_mode(adev, parameter, parameter_size); 1488 1489 pm_runtime_mark_last_busy(ddev->dev); 1490 pm_runtime_put_autosuspend(ddev->dev); 1491 1492 if (!ret) 1493 return count; 1494 1495 return -EINVAL; 1496 } 1497 1498 /** 1499 * DOC: gpu_busy_percent 1500 * 1501 * The amdgpu driver provides a sysfs API for reading how busy the GPU 1502 * is as a percentage. The file gpu_busy_percent is used for this. 1503 * The SMU firmware computes a percentage of load based on the 1504 * aggregate activity level in the IP cores. 1505 */ 1506 static ssize_t amdgpu_get_gpu_busy_percent(struct device *dev, 1507 struct device_attribute *attr, 1508 char *buf) 1509 { 1510 struct drm_device *ddev = dev_get_drvdata(dev); 1511 struct amdgpu_device *adev = drm_to_adev(ddev); 1512 int r, value, size = sizeof(value); 1513 1514 if (amdgpu_in_reset(adev)) 1515 return -EPERM; 1516 if (adev->in_suspend && !adev->in_runpm) 1517 return -EPERM; 1518 1519 r = pm_runtime_get_sync(ddev->dev); 1520 if (r < 0) { 1521 pm_runtime_put_autosuspend(ddev->dev); 1522 return r; 1523 } 1524 1525 /* read the IP busy sensor */ 1526 r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_LOAD, 1527 (void *)&value, &size); 1528 1529 pm_runtime_mark_last_busy(ddev->dev); 1530 pm_runtime_put_autosuspend(ddev->dev); 1531 1532 if (r) 1533 return r; 1534 1535 return sysfs_emit(buf, "%d\n", value); 1536 } 1537 1538 /** 1539 * DOC: mem_busy_percent 1540 * 1541 * The amdgpu driver provides a sysfs API for reading how busy the VRAM 1542 * is as a percentage. The file mem_busy_percent is used for this. 1543 * The SMU firmware computes a percentage of load based on the 1544 * aggregate activity level in the IP cores. 1545 */ 1546 static ssize_t amdgpu_get_mem_busy_percent(struct device *dev, 1547 struct device_attribute *attr, 1548 char *buf) 1549 { 1550 struct drm_device *ddev = dev_get_drvdata(dev); 1551 struct amdgpu_device *adev = drm_to_adev(ddev); 1552 int r, value, size = sizeof(value); 1553 1554 if (amdgpu_in_reset(adev)) 1555 return -EPERM; 1556 if (adev->in_suspend && !adev->in_runpm) 1557 return -EPERM; 1558 1559 r = pm_runtime_get_sync(ddev->dev); 1560 if (r < 0) { 1561 pm_runtime_put_autosuspend(ddev->dev); 1562 return r; 1563 } 1564 1565 /* read the IP busy sensor */ 1566 r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_MEM_LOAD, 1567 (void *)&value, &size); 1568 1569 pm_runtime_mark_last_busy(ddev->dev); 1570 pm_runtime_put_autosuspend(ddev->dev); 1571 1572 if (r) 1573 return r; 1574 1575 return sysfs_emit(buf, "%d\n", value); 1576 } 1577 1578 /** 1579 * DOC: pcie_bw 1580 * 1581 * The amdgpu driver provides a sysfs API for estimating how much data 1582 * has been received and sent by the GPU in the last second through PCIe. 1583 * The file pcie_bw is used for this. 1584 * The Perf counters count the number of received and sent messages and return 1585 * those values, as well as the maximum payload size of a PCIe packet (mps). 1586 * Note that it is not possible to easily and quickly obtain the size of each 1587 * packet transmitted, so we output the max payload size (mps) to allow for 1588 * quick estimation of the PCIe bandwidth usage 1589 */ 1590 static ssize_t amdgpu_get_pcie_bw(struct device *dev, 1591 struct device_attribute *attr, 1592 char *buf) 1593 { 1594 struct drm_device *ddev = dev_get_drvdata(dev); 1595 struct amdgpu_device *adev = drm_to_adev(ddev); 1596 uint64_t count0 = 0, count1 = 0; 1597 int ret; 1598 1599 if (amdgpu_in_reset(adev)) 1600 return -EPERM; 1601 if (adev->in_suspend && !adev->in_runpm) 1602 return -EPERM; 1603 1604 if (adev->flags & AMD_IS_APU) 1605 return -ENODATA; 1606 1607 if (!adev->asic_funcs->get_pcie_usage) 1608 return -ENODATA; 1609 1610 ret = pm_runtime_get_sync(ddev->dev); 1611 if (ret < 0) { 1612 pm_runtime_put_autosuspend(ddev->dev); 1613 return ret; 1614 } 1615 1616 amdgpu_asic_get_pcie_usage(adev, &count0, &count1); 1617 1618 pm_runtime_mark_last_busy(ddev->dev); 1619 pm_runtime_put_autosuspend(ddev->dev); 1620 1621 return sysfs_emit(buf, "%llu %llu %i\n", 1622 count0, count1, pcie_get_mps(adev->pdev)); 1623 } 1624 1625 /** 1626 * DOC: unique_id 1627 * 1628 * The amdgpu driver provides a sysfs API for providing a unique ID for the GPU 1629 * The file unique_id is used for this. 1630 * This will provide a Unique ID that will persist from machine to machine 1631 * 1632 * NOTE: This will only work for GFX9 and newer. This file will be absent 1633 * on unsupported ASICs (GFX8 and older) 1634 */ 1635 static ssize_t amdgpu_get_unique_id(struct device *dev, 1636 struct device_attribute *attr, 1637 char *buf) 1638 { 1639 struct drm_device *ddev = dev_get_drvdata(dev); 1640 struct amdgpu_device *adev = drm_to_adev(ddev); 1641 1642 if (amdgpu_in_reset(adev)) 1643 return -EPERM; 1644 if (adev->in_suspend && !adev->in_runpm) 1645 return -EPERM; 1646 1647 if (adev->unique_id) 1648 return sysfs_emit(buf, "%016llx\n", adev->unique_id); 1649 1650 return 0; 1651 } 1652 1653 /** 1654 * DOC: thermal_throttling_logging 1655 * 1656 * Thermal throttling pulls down the clock frequency and thus the performance. 1657 * It's an useful mechanism to protect the chip from overheating. Since it 1658 * impacts performance, the user controls whether it is enabled and if so, 1659 * the log frequency. 1660 * 1661 * Reading back the file shows you the status(enabled or disabled) and 1662 * the interval(in seconds) between each thermal logging. 1663 * 1664 * Writing an integer to the file, sets a new logging interval, in seconds. 1665 * The value should be between 1 and 3600. If the value is less than 1, 1666 * thermal logging is disabled. Values greater than 3600 are ignored. 1667 */ 1668 static ssize_t amdgpu_get_thermal_throttling_logging(struct device *dev, 1669 struct device_attribute *attr, 1670 char *buf) 1671 { 1672 struct drm_device *ddev = dev_get_drvdata(dev); 1673 struct amdgpu_device *adev = drm_to_adev(ddev); 1674 1675 return sysfs_emit(buf, "%s: thermal throttling logging %s, with interval %d seconds\n", 1676 adev_to_drm(adev)->unique, 1677 atomic_read(&adev->throttling_logging_enabled) ? "enabled" : "disabled", 1678 adev->throttling_logging_rs.interval / HZ + 1); 1679 } 1680 1681 static ssize_t amdgpu_set_thermal_throttling_logging(struct device *dev, 1682 struct device_attribute *attr, 1683 const char *buf, 1684 size_t count) 1685 { 1686 struct drm_device *ddev = dev_get_drvdata(dev); 1687 struct amdgpu_device *adev = drm_to_adev(ddev); 1688 long throttling_logging_interval; 1689 unsigned long flags; 1690 int ret = 0; 1691 1692 ret = kstrtol(buf, 0, &throttling_logging_interval); 1693 if (ret) 1694 return ret; 1695 1696 if (throttling_logging_interval > 3600) 1697 return -EINVAL; 1698 1699 if (throttling_logging_interval > 0) { 1700 raw_spin_lock_irqsave(&adev->throttling_logging_rs.lock, flags); 1701 /* 1702 * Reset the ratelimit timer internals. 1703 * This can effectively restart the timer. 1704 */ 1705 adev->throttling_logging_rs.interval = 1706 (throttling_logging_interval - 1) * HZ; 1707 adev->throttling_logging_rs.begin = 0; 1708 adev->throttling_logging_rs.printed = 0; 1709 adev->throttling_logging_rs.missed = 0; 1710 raw_spin_unlock_irqrestore(&adev->throttling_logging_rs.lock, flags); 1711 1712 atomic_set(&adev->throttling_logging_enabled, 1); 1713 } else { 1714 atomic_set(&adev->throttling_logging_enabled, 0); 1715 } 1716 1717 return count; 1718 } 1719 1720 /** 1721 * DOC: apu_thermal_cap 1722 * 1723 * The amdgpu driver provides a sysfs API for retrieving/updating thermal 1724 * limit temperature in millidegrees Celsius 1725 * 1726 * Reading back the file shows you core limit value 1727 * 1728 * Writing an integer to the file, sets a new thermal limit. The value 1729 * should be between 0 and 100. If the value is less than 0 or greater 1730 * than 100, then the write request will be ignored. 1731 */ 1732 static ssize_t amdgpu_get_apu_thermal_cap(struct device *dev, 1733 struct device_attribute *attr, 1734 char *buf) 1735 { 1736 int ret, size; 1737 u32 limit; 1738 struct drm_device *ddev = dev_get_drvdata(dev); 1739 struct amdgpu_device *adev = drm_to_adev(ddev); 1740 1741 ret = pm_runtime_get_sync(ddev->dev); 1742 if (ret < 0) { 1743 pm_runtime_put_autosuspend(ddev->dev); 1744 return ret; 1745 } 1746 1747 ret = amdgpu_dpm_get_apu_thermal_limit(adev, &limit); 1748 if (!ret) 1749 size = sysfs_emit(buf, "%u\n", limit); 1750 else 1751 size = sysfs_emit(buf, "failed to get thermal limit\n"); 1752 1753 pm_runtime_mark_last_busy(ddev->dev); 1754 pm_runtime_put_autosuspend(ddev->dev); 1755 1756 return size; 1757 } 1758 1759 static ssize_t amdgpu_set_apu_thermal_cap(struct device *dev, 1760 struct device_attribute *attr, 1761 const char *buf, 1762 size_t count) 1763 { 1764 int ret; 1765 u32 value; 1766 struct drm_device *ddev = dev_get_drvdata(dev); 1767 struct amdgpu_device *adev = drm_to_adev(ddev); 1768 1769 ret = kstrtou32(buf, 10, &value); 1770 if (ret) 1771 return ret; 1772 1773 if (value > 100) { 1774 dev_err(dev, "Invalid argument !\n"); 1775 return -EINVAL; 1776 } 1777 1778 ret = pm_runtime_get_sync(ddev->dev); 1779 if (ret < 0) { 1780 pm_runtime_put_autosuspend(ddev->dev); 1781 return ret; 1782 } 1783 1784 ret = amdgpu_dpm_set_apu_thermal_limit(adev, value); 1785 if (ret) { 1786 dev_err(dev, "failed to update thermal limit\n"); 1787 return ret; 1788 } 1789 1790 pm_runtime_mark_last_busy(ddev->dev); 1791 pm_runtime_put_autosuspend(ddev->dev); 1792 1793 return count; 1794 } 1795 1796 /** 1797 * DOC: gpu_metrics 1798 * 1799 * The amdgpu driver provides a sysfs API for retrieving current gpu 1800 * metrics data. The file gpu_metrics is used for this. Reading the 1801 * file will dump all the current gpu metrics data. 1802 * 1803 * These data include temperature, frequency, engines utilization, 1804 * power consume, throttler status, fan speed and cpu core statistics( 1805 * available for APU only). That's it will give a snapshot of all sensors 1806 * at the same time. 1807 */ 1808 static ssize_t amdgpu_get_gpu_metrics(struct device *dev, 1809 struct device_attribute *attr, 1810 char *buf) 1811 { 1812 struct drm_device *ddev = dev_get_drvdata(dev); 1813 struct amdgpu_device *adev = drm_to_adev(ddev); 1814 void *gpu_metrics; 1815 ssize_t size = 0; 1816 int ret; 1817 1818 if (amdgpu_in_reset(adev)) 1819 return -EPERM; 1820 if (adev->in_suspend && !adev->in_runpm) 1821 return -EPERM; 1822 1823 ret = pm_runtime_get_sync(ddev->dev); 1824 if (ret < 0) { 1825 pm_runtime_put_autosuspend(ddev->dev); 1826 return ret; 1827 } 1828 1829 size = amdgpu_dpm_get_gpu_metrics(adev, &gpu_metrics); 1830 if (size <= 0) 1831 goto out; 1832 1833 if (size >= PAGE_SIZE) 1834 size = PAGE_SIZE - 1; 1835 1836 memcpy(buf, gpu_metrics, size); 1837 1838 out: 1839 pm_runtime_mark_last_busy(ddev->dev); 1840 pm_runtime_put_autosuspend(ddev->dev); 1841 1842 return size; 1843 } 1844 1845 static int amdgpu_device_read_powershift(struct amdgpu_device *adev, 1846 uint32_t *ss_power, bool dgpu_share) 1847 { 1848 struct drm_device *ddev = adev_to_drm(adev); 1849 uint32_t size; 1850 int r = 0; 1851 1852 if (amdgpu_in_reset(adev)) 1853 return -EPERM; 1854 if (adev->in_suspend && !adev->in_runpm) 1855 return -EPERM; 1856 1857 r = pm_runtime_get_sync(ddev->dev); 1858 if (r < 0) { 1859 pm_runtime_put_autosuspend(ddev->dev); 1860 return r; 1861 } 1862 1863 if (dgpu_share) 1864 r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_SS_DGPU_SHARE, 1865 (void *)ss_power, &size); 1866 else 1867 r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_SS_APU_SHARE, 1868 (void *)ss_power, &size); 1869 1870 pm_runtime_mark_last_busy(ddev->dev); 1871 pm_runtime_put_autosuspend(ddev->dev); 1872 return r; 1873 } 1874 1875 static int amdgpu_show_powershift_percent(struct device *dev, 1876 char *buf, bool dgpu_share) 1877 { 1878 struct drm_device *ddev = dev_get_drvdata(dev); 1879 struct amdgpu_device *adev = drm_to_adev(ddev); 1880 uint32_t ss_power; 1881 int r = 0, i; 1882 1883 r = amdgpu_device_read_powershift(adev, &ss_power, dgpu_share); 1884 if (r == -EOPNOTSUPP) { 1885 /* sensor not available on dGPU, try to read from APU */ 1886 adev = NULL; 1887 mutex_lock(&mgpu_info.mutex); 1888 for (i = 0; i < mgpu_info.num_gpu; i++) { 1889 if (mgpu_info.gpu_ins[i].adev->flags & AMD_IS_APU) { 1890 adev = mgpu_info.gpu_ins[i].adev; 1891 break; 1892 } 1893 } 1894 mutex_unlock(&mgpu_info.mutex); 1895 if (adev) 1896 r = amdgpu_device_read_powershift(adev, &ss_power, dgpu_share); 1897 } 1898 1899 if (!r) 1900 r = sysfs_emit(buf, "%u%%\n", ss_power); 1901 1902 return r; 1903 } 1904 /** 1905 * DOC: smartshift_apu_power 1906 * 1907 * The amdgpu driver provides a sysfs API for reporting APU power 1908 * shift in percentage if platform supports smartshift. Value 0 means that 1909 * there is no powershift and values between [1-100] means that the power 1910 * is shifted to APU, the percentage of boost is with respect to APU power 1911 * limit on the platform. 1912 */ 1913 1914 static ssize_t amdgpu_get_smartshift_apu_power(struct device *dev, struct device_attribute *attr, 1915 char *buf) 1916 { 1917 return amdgpu_show_powershift_percent(dev, buf, false); 1918 } 1919 1920 /** 1921 * DOC: smartshift_dgpu_power 1922 * 1923 * The amdgpu driver provides a sysfs API for reporting dGPU power 1924 * shift in percentage if platform supports smartshift. Value 0 means that 1925 * there is no powershift and values between [1-100] means that the power is 1926 * shifted to dGPU, the percentage of boost is with respect to dGPU power 1927 * limit on the platform. 1928 */ 1929 1930 static ssize_t amdgpu_get_smartshift_dgpu_power(struct device *dev, struct device_attribute *attr, 1931 char *buf) 1932 { 1933 return amdgpu_show_powershift_percent(dev, buf, true); 1934 } 1935 1936 /** 1937 * DOC: smartshift_bias 1938 * 1939 * The amdgpu driver provides a sysfs API for reporting the 1940 * smartshift(SS2.0) bias level. The value ranges from -100 to 100 1941 * and the default is 0. -100 sets maximum preference to APU 1942 * and 100 sets max perference to dGPU. 1943 */ 1944 1945 static ssize_t amdgpu_get_smartshift_bias(struct device *dev, 1946 struct device_attribute *attr, 1947 char *buf) 1948 { 1949 int r = 0; 1950 1951 r = sysfs_emit(buf, "%d\n", amdgpu_smartshift_bias); 1952 1953 return r; 1954 } 1955 1956 static ssize_t amdgpu_set_smartshift_bias(struct device *dev, 1957 struct device_attribute *attr, 1958 const char *buf, size_t count) 1959 { 1960 struct drm_device *ddev = dev_get_drvdata(dev); 1961 struct amdgpu_device *adev = drm_to_adev(ddev); 1962 int r = 0; 1963 int bias = 0; 1964 1965 if (amdgpu_in_reset(adev)) 1966 return -EPERM; 1967 if (adev->in_suspend && !adev->in_runpm) 1968 return -EPERM; 1969 1970 r = pm_runtime_get_sync(ddev->dev); 1971 if (r < 0) { 1972 pm_runtime_put_autosuspend(ddev->dev); 1973 return r; 1974 } 1975 1976 r = kstrtoint(buf, 10, &bias); 1977 if (r) 1978 goto out; 1979 1980 if (bias > AMDGPU_SMARTSHIFT_MAX_BIAS) 1981 bias = AMDGPU_SMARTSHIFT_MAX_BIAS; 1982 else if (bias < AMDGPU_SMARTSHIFT_MIN_BIAS) 1983 bias = AMDGPU_SMARTSHIFT_MIN_BIAS; 1984 1985 amdgpu_smartshift_bias = bias; 1986 r = count; 1987 1988 /* TODO: update bias level with SMU message */ 1989 1990 out: 1991 pm_runtime_mark_last_busy(ddev->dev); 1992 pm_runtime_put_autosuspend(ddev->dev); 1993 return r; 1994 } 1995 1996 1997 static int ss_power_attr_update(struct amdgpu_device *adev, struct amdgpu_device_attr *attr, 1998 uint32_t mask, enum amdgpu_device_attr_states *states) 1999 { 2000 if (!amdgpu_device_supports_smart_shift(adev_to_drm(adev))) 2001 *states = ATTR_STATE_UNSUPPORTED; 2002 2003 return 0; 2004 } 2005 2006 static int ss_bias_attr_update(struct amdgpu_device *adev, struct amdgpu_device_attr *attr, 2007 uint32_t mask, enum amdgpu_device_attr_states *states) 2008 { 2009 uint32_t ss_power, size; 2010 2011 if (!amdgpu_device_supports_smart_shift(adev_to_drm(adev))) 2012 *states = ATTR_STATE_UNSUPPORTED; 2013 else if (amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_SS_APU_SHARE, 2014 (void *)&ss_power, &size)) 2015 *states = ATTR_STATE_UNSUPPORTED; 2016 else if (amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_SS_DGPU_SHARE, 2017 (void *)&ss_power, &size)) 2018 *states = ATTR_STATE_UNSUPPORTED; 2019 2020 return 0; 2021 } 2022 2023 static struct amdgpu_device_attr amdgpu_device_attrs[] = { 2024 AMDGPU_DEVICE_ATTR_RW(power_dpm_state, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF), 2025 AMDGPU_DEVICE_ATTR_RW(power_dpm_force_performance_level, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF), 2026 AMDGPU_DEVICE_ATTR_RO(pp_num_states, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF), 2027 AMDGPU_DEVICE_ATTR_RO(pp_cur_state, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF), 2028 AMDGPU_DEVICE_ATTR_RW(pp_force_state, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF), 2029 AMDGPU_DEVICE_ATTR_RW(pp_table, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF), 2030 AMDGPU_DEVICE_ATTR_RW(pp_dpm_sclk, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF), 2031 AMDGPU_DEVICE_ATTR_RW(pp_dpm_mclk, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF), 2032 AMDGPU_DEVICE_ATTR_RW(pp_dpm_socclk, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF), 2033 AMDGPU_DEVICE_ATTR_RW(pp_dpm_fclk, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF), 2034 AMDGPU_DEVICE_ATTR_RW(pp_dpm_vclk, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF), 2035 AMDGPU_DEVICE_ATTR_RW(pp_dpm_vclk1, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF), 2036 AMDGPU_DEVICE_ATTR_RW(pp_dpm_dclk, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF), 2037 AMDGPU_DEVICE_ATTR_RW(pp_dpm_dclk1, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF), 2038 AMDGPU_DEVICE_ATTR_RW(pp_dpm_dcefclk, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF), 2039 AMDGPU_DEVICE_ATTR_RW(pp_dpm_pcie, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF), 2040 AMDGPU_DEVICE_ATTR_RW(pp_sclk_od, ATTR_FLAG_BASIC), 2041 AMDGPU_DEVICE_ATTR_RW(pp_mclk_od, ATTR_FLAG_BASIC), 2042 AMDGPU_DEVICE_ATTR_RW(pp_power_profile_mode, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF), 2043 AMDGPU_DEVICE_ATTR_RW(pp_od_clk_voltage, ATTR_FLAG_BASIC), 2044 AMDGPU_DEVICE_ATTR_RO(gpu_busy_percent, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF), 2045 AMDGPU_DEVICE_ATTR_RO(mem_busy_percent, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF), 2046 AMDGPU_DEVICE_ATTR_RO(pcie_bw, ATTR_FLAG_BASIC), 2047 AMDGPU_DEVICE_ATTR_RW(pp_features, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF), 2048 AMDGPU_DEVICE_ATTR_RO(unique_id, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF), 2049 AMDGPU_DEVICE_ATTR_RW(thermal_throttling_logging, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF), 2050 AMDGPU_DEVICE_ATTR_RW(apu_thermal_cap, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF), 2051 AMDGPU_DEVICE_ATTR_RO(gpu_metrics, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF), 2052 AMDGPU_DEVICE_ATTR_RO(smartshift_apu_power, ATTR_FLAG_BASIC, 2053 .attr_update = ss_power_attr_update), 2054 AMDGPU_DEVICE_ATTR_RO(smartshift_dgpu_power, ATTR_FLAG_BASIC, 2055 .attr_update = ss_power_attr_update), 2056 AMDGPU_DEVICE_ATTR_RW(smartshift_bias, ATTR_FLAG_BASIC, 2057 .attr_update = ss_bias_attr_update), 2058 }; 2059 2060 static int default_attr_update(struct amdgpu_device *adev, struct amdgpu_device_attr *attr, 2061 uint32_t mask, enum amdgpu_device_attr_states *states) 2062 { 2063 struct device_attribute *dev_attr = &attr->dev_attr; 2064 uint32_t mp1_ver = adev->ip_versions[MP1_HWIP][0]; 2065 uint32_t gc_ver = adev->ip_versions[GC_HWIP][0]; 2066 const char *attr_name = dev_attr->attr.name; 2067 2068 if (!(attr->flags & mask)) { 2069 *states = ATTR_STATE_UNSUPPORTED; 2070 return 0; 2071 } 2072 2073 #define DEVICE_ATTR_IS(_name) (!strcmp(attr_name, #_name)) 2074 2075 if (DEVICE_ATTR_IS(pp_dpm_socclk)) { 2076 if (gc_ver < IP_VERSION(9, 0, 0)) 2077 *states = ATTR_STATE_UNSUPPORTED; 2078 } else if (DEVICE_ATTR_IS(pp_dpm_dcefclk)) { 2079 if (gc_ver < IP_VERSION(9, 0, 0) || 2080 gc_ver == IP_VERSION(9, 4, 1) || 2081 gc_ver == IP_VERSION(9, 4, 2)) 2082 *states = ATTR_STATE_UNSUPPORTED; 2083 } else if (DEVICE_ATTR_IS(pp_dpm_fclk)) { 2084 if (mp1_ver < IP_VERSION(10, 0, 0)) 2085 *states = ATTR_STATE_UNSUPPORTED; 2086 } else if (DEVICE_ATTR_IS(pp_od_clk_voltage)) { 2087 *states = ATTR_STATE_UNSUPPORTED; 2088 if (amdgpu_dpm_is_overdrive_supported(adev)) 2089 *states = ATTR_STATE_SUPPORTED; 2090 } else if (DEVICE_ATTR_IS(mem_busy_percent)) { 2091 if (adev->flags & AMD_IS_APU || gc_ver == IP_VERSION(9, 0, 1)) 2092 *states = ATTR_STATE_UNSUPPORTED; 2093 } else if (DEVICE_ATTR_IS(pcie_bw)) { 2094 /* PCIe Perf counters won't work on APU nodes */ 2095 if (adev->flags & AMD_IS_APU) 2096 *states = ATTR_STATE_UNSUPPORTED; 2097 } else if (DEVICE_ATTR_IS(unique_id)) { 2098 switch (gc_ver) { 2099 case IP_VERSION(9, 0, 1): 2100 case IP_VERSION(9, 4, 0): 2101 case IP_VERSION(9, 4, 1): 2102 case IP_VERSION(9, 4, 2): 2103 case IP_VERSION(10, 3, 0): 2104 case IP_VERSION(11, 0, 0): 2105 case IP_VERSION(11, 0, 1): 2106 case IP_VERSION(11, 0, 2): 2107 *states = ATTR_STATE_SUPPORTED; 2108 break; 2109 default: 2110 *states = ATTR_STATE_UNSUPPORTED; 2111 } 2112 } else if (DEVICE_ATTR_IS(pp_features)) { 2113 if (adev->flags & AMD_IS_APU || gc_ver < IP_VERSION(9, 0, 0)) 2114 *states = ATTR_STATE_UNSUPPORTED; 2115 } else if (DEVICE_ATTR_IS(gpu_metrics)) { 2116 if (gc_ver < IP_VERSION(9, 1, 0)) 2117 *states = ATTR_STATE_UNSUPPORTED; 2118 } else if (DEVICE_ATTR_IS(pp_dpm_vclk)) { 2119 if (!(gc_ver == IP_VERSION(10, 3, 1) || 2120 gc_ver == IP_VERSION(10, 3, 0) || 2121 gc_ver == IP_VERSION(10, 1, 2) || 2122 gc_ver == IP_VERSION(11, 0, 0) || 2123 gc_ver == IP_VERSION(11, 0, 2) || 2124 gc_ver == IP_VERSION(11, 0, 3))) 2125 *states = ATTR_STATE_UNSUPPORTED; 2126 } else if (DEVICE_ATTR_IS(pp_dpm_vclk1)) { 2127 if (!((gc_ver == IP_VERSION(10, 3, 1) || 2128 gc_ver == IP_VERSION(10, 3, 0) || 2129 gc_ver == IP_VERSION(11, 0, 2) || 2130 gc_ver == IP_VERSION(11, 0, 3)) && adev->vcn.num_vcn_inst >= 2)) 2131 *states = ATTR_STATE_UNSUPPORTED; 2132 } else if (DEVICE_ATTR_IS(pp_dpm_dclk)) { 2133 if (!(gc_ver == IP_VERSION(10, 3, 1) || 2134 gc_ver == IP_VERSION(10, 3, 0) || 2135 gc_ver == IP_VERSION(10, 1, 2) || 2136 gc_ver == IP_VERSION(11, 0, 0) || 2137 gc_ver == IP_VERSION(11, 0, 2) || 2138 gc_ver == IP_VERSION(11, 0, 3))) 2139 *states = ATTR_STATE_UNSUPPORTED; 2140 } else if (DEVICE_ATTR_IS(pp_dpm_dclk1)) { 2141 if (!((gc_ver == IP_VERSION(10, 3, 1) || 2142 gc_ver == IP_VERSION(10, 3, 0) || 2143 gc_ver == IP_VERSION(11, 0, 2) || 2144 gc_ver == IP_VERSION(11, 0, 3)) && adev->vcn.num_vcn_inst >= 2)) 2145 *states = ATTR_STATE_UNSUPPORTED; 2146 } else if (DEVICE_ATTR_IS(pp_power_profile_mode)) { 2147 if (amdgpu_dpm_get_power_profile_mode(adev, NULL) == -EOPNOTSUPP) 2148 *states = ATTR_STATE_UNSUPPORTED; 2149 else if (gc_ver == IP_VERSION(10, 3, 0) && amdgpu_sriov_vf(adev)) 2150 *states = ATTR_STATE_UNSUPPORTED; 2151 } 2152 2153 switch (gc_ver) { 2154 case IP_VERSION(9, 4, 1): 2155 case IP_VERSION(9, 4, 2): 2156 /* the Mi series card does not support standalone mclk/socclk/fclk level setting */ 2157 if (DEVICE_ATTR_IS(pp_dpm_mclk) || 2158 DEVICE_ATTR_IS(pp_dpm_socclk) || 2159 DEVICE_ATTR_IS(pp_dpm_fclk)) { 2160 dev_attr->attr.mode &= ~S_IWUGO; 2161 dev_attr->store = NULL; 2162 } 2163 break; 2164 case IP_VERSION(10, 3, 0): 2165 if (DEVICE_ATTR_IS(power_dpm_force_performance_level) && 2166 amdgpu_sriov_vf(adev)) { 2167 dev_attr->attr.mode &= ~0222; 2168 dev_attr->store = NULL; 2169 } 2170 break; 2171 default: 2172 break; 2173 } 2174 2175 if (DEVICE_ATTR_IS(pp_dpm_dcefclk)) { 2176 /* SMU MP1 does not support dcefclk level setting */ 2177 if (gc_ver >= IP_VERSION(10, 0, 0)) { 2178 dev_attr->attr.mode &= ~S_IWUGO; 2179 dev_attr->store = NULL; 2180 } 2181 } 2182 2183 /* setting should not be allowed from VF if not in one VF mode */ 2184 if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev)) { 2185 dev_attr->attr.mode &= ~S_IWUGO; 2186 dev_attr->store = NULL; 2187 } 2188 2189 #undef DEVICE_ATTR_IS 2190 2191 return 0; 2192 } 2193 2194 2195 static int amdgpu_device_attr_create(struct amdgpu_device *adev, 2196 struct amdgpu_device_attr *attr, 2197 uint32_t mask, struct list_head *attr_list) 2198 { 2199 int ret = 0; 2200 struct device_attribute *dev_attr = &attr->dev_attr; 2201 const char *name = dev_attr->attr.name; 2202 enum amdgpu_device_attr_states attr_states = ATTR_STATE_SUPPORTED; 2203 struct amdgpu_device_attr_entry *attr_entry; 2204 2205 int (*attr_update)(struct amdgpu_device *adev, struct amdgpu_device_attr *attr, 2206 uint32_t mask, enum amdgpu_device_attr_states *states) = default_attr_update; 2207 2208 BUG_ON(!attr); 2209 2210 attr_update = attr->attr_update ? attr->attr_update : default_attr_update; 2211 2212 ret = attr_update(adev, attr, mask, &attr_states); 2213 if (ret) { 2214 dev_err(adev->dev, "failed to update device file %s, ret = %d\n", 2215 name, ret); 2216 return ret; 2217 } 2218 2219 if (attr_states == ATTR_STATE_UNSUPPORTED) 2220 return 0; 2221 2222 ret = device_create_file(adev->dev, dev_attr); 2223 if (ret) { 2224 dev_err(adev->dev, "failed to create device file %s, ret = %d\n", 2225 name, ret); 2226 } 2227 2228 attr_entry = kmalloc(sizeof(*attr_entry), GFP_KERNEL); 2229 if (!attr_entry) 2230 return -ENOMEM; 2231 2232 attr_entry->attr = attr; 2233 INIT_LIST_HEAD(&attr_entry->entry); 2234 2235 list_add_tail(&attr_entry->entry, attr_list); 2236 2237 return ret; 2238 } 2239 2240 static void amdgpu_device_attr_remove(struct amdgpu_device *adev, struct amdgpu_device_attr *attr) 2241 { 2242 struct device_attribute *dev_attr = &attr->dev_attr; 2243 2244 device_remove_file(adev->dev, dev_attr); 2245 } 2246 2247 static void amdgpu_device_attr_remove_groups(struct amdgpu_device *adev, 2248 struct list_head *attr_list); 2249 2250 static int amdgpu_device_attr_create_groups(struct amdgpu_device *adev, 2251 struct amdgpu_device_attr *attrs, 2252 uint32_t counts, 2253 uint32_t mask, 2254 struct list_head *attr_list) 2255 { 2256 int ret = 0; 2257 uint32_t i = 0; 2258 2259 for (i = 0; i < counts; i++) { 2260 ret = amdgpu_device_attr_create(adev, &attrs[i], mask, attr_list); 2261 if (ret) 2262 goto failed; 2263 } 2264 2265 return 0; 2266 2267 failed: 2268 amdgpu_device_attr_remove_groups(adev, attr_list); 2269 2270 return ret; 2271 } 2272 2273 static void amdgpu_device_attr_remove_groups(struct amdgpu_device *adev, 2274 struct list_head *attr_list) 2275 { 2276 struct amdgpu_device_attr_entry *entry, *entry_tmp; 2277 2278 if (list_empty(attr_list)) 2279 return ; 2280 2281 list_for_each_entry_safe(entry, entry_tmp, attr_list, entry) { 2282 amdgpu_device_attr_remove(adev, entry->attr); 2283 list_del(&entry->entry); 2284 kfree(entry); 2285 } 2286 } 2287 2288 static ssize_t amdgpu_hwmon_show_temp(struct device *dev, 2289 struct device_attribute *attr, 2290 char *buf) 2291 { 2292 struct amdgpu_device *adev = dev_get_drvdata(dev); 2293 int channel = to_sensor_dev_attr(attr)->index; 2294 int r, temp = 0, size = sizeof(temp); 2295 2296 if (amdgpu_in_reset(adev)) 2297 return -EPERM; 2298 if (adev->in_suspend && !adev->in_runpm) 2299 return -EPERM; 2300 2301 if (channel >= PP_TEMP_MAX) 2302 return -EINVAL; 2303 2304 r = pm_runtime_get_sync(adev_to_drm(adev)->dev); 2305 if (r < 0) { 2306 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 2307 return r; 2308 } 2309 2310 switch (channel) { 2311 case PP_TEMP_JUNCTION: 2312 /* get current junction temperature */ 2313 r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_HOTSPOT_TEMP, 2314 (void *)&temp, &size); 2315 break; 2316 case PP_TEMP_EDGE: 2317 /* get current edge temperature */ 2318 r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_EDGE_TEMP, 2319 (void *)&temp, &size); 2320 break; 2321 case PP_TEMP_MEM: 2322 /* get current memory temperature */ 2323 r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_MEM_TEMP, 2324 (void *)&temp, &size); 2325 break; 2326 default: 2327 r = -EINVAL; 2328 break; 2329 } 2330 2331 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev); 2332 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 2333 2334 if (r) 2335 return r; 2336 2337 return sysfs_emit(buf, "%d\n", temp); 2338 } 2339 2340 static ssize_t amdgpu_hwmon_show_temp_thresh(struct device *dev, 2341 struct device_attribute *attr, 2342 char *buf) 2343 { 2344 struct amdgpu_device *adev = dev_get_drvdata(dev); 2345 int hyst = to_sensor_dev_attr(attr)->index; 2346 int temp; 2347 2348 if (hyst) 2349 temp = adev->pm.dpm.thermal.min_temp; 2350 else 2351 temp = adev->pm.dpm.thermal.max_temp; 2352 2353 return sysfs_emit(buf, "%d\n", temp); 2354 } 2355 2356 static ssize_t amdgpu_hwmon_show_hotspot_temp_thresh(struct device *dev, 2357 struct device_attribute *attr, 2358 char *buf) 2359 { 2360 struct amdgpu_device *adev = dev_get_drvdata(dev); 2361 int hyst = to_sensor_dev_attr(attr)->index; 2362 int temp; 2363 2364 if (hyst) 2365 temp = adev->pm.dpm.thermal.min_hotspot_temp; 2366 else 2367 temp = adev->pm.dpm.thermal.max_hotspot_crit_temp; 2368 2369 return sysfs_emit(buf, "%d\n", temp); 2370 } 2371 2372 static ssize_t amdgpu_hwmon_show_mem_temp_thresh(struct device *dev, 2373 struct device_attribute *attr, 2374 char *buf) 2375 { 2376 struct amdgpu_device *adev = dev_get_drvdata(dev); 2377 int hyst = to_sensor_dev_attr(attr)->index; 2378 int temp; 2379 2380 if (hyst) 2381 temp = adev->pm.dpm.thermal.min_mem_temp; 2382 else 2383 temp = adev->pm.dpm.thermal.max_mem_crit_temp; 2384 2385 return sysfs_emit(buf, "%d\n", temp); 2386 } 2387 2388 static ssize_t amdgpu_hwmon_show_temp_label(struct device *dev, 2389 struct device_attribute *attr, 2390 char *buf) 2391 { 2392 int channel = to_sensor_dev_attr(attr)->index; 2393 2394 if (channel >= PP_TEMP_MAX) 2395 return -EINVAL; 2396 2397 return sysfs_emit(buf, "%s\n", temp_label[channel].label); 2398 } 2399 2400 static ssize_t amdgpu_hwmon_show_temp_emergency(struct device *dev, 2401 struct device_attribute *attr, 2402 char *buf) 2403 { 2404 struct amdgpu_device *adev = dev_get_drvdata(dev); 2405 int channel = to_sensor_dev_attr(attr)->index; 2406 int temp = 0; 2407 2408 if (channel >= PP_TEMP_MAX) 2409 return -EINVAL; 2410 2411 switch (channel) { 2412 case PP_TEMP_JUNCTION: 2413 temp = adev->pm.dpm.thermal.max_hotspot_emergency_temp; 2414 break; 2415 case PP_TEMP_EDGE: 2416 temp = adev->pm.dpm.thermal.max_edge_emergency_temp; 2417 break; 2418 case PP_TEMP_MEM: 2419 temp = adev->pm.dpm.thermal.max_mem_emergency_temp; 2420 break; 2421 } 2422 2423 return sysfs_emit(buf, "%d\n", temp); 2424 } 2425 2426 static ssize_t amdgpu_hwmon_get_pwm1_enable(struct device *dev, 2427 struct device_attribute *attr, 2428 char *buf) 2429 { 2430 struct amdgpu_device *adev = dev_get_drvdata(dev); 2431 u32 pwm_mode = 0; 2432 int ret; 2433 2434 if (amdgpu_in_reset(adev)) 2435 return -EPERM; 2436 if (adev->in_suspend && !adev->in_runpm) 2437 return -EPERM; 2438 2439 ret = pm_runtime_get_sync(adev_to_drm(adev)->dev); 2440 if (ret < 0) { 2441 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 2442 return ret; 2443 } 2444 2445 ret = amdgpu_dpm_get_fan_control_mode(adev, &pwm_mode); 2446 2447 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev); 2448 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 2449 2450 if (ret) 2451 return -EINVAL; 2452 2453 return sysfs_emit(buf, "%u\n", pwm_mode); 2454 } 2455 2456 static ssize_t amdgpu_hwmon_set_pwm1_enable(struct device *dev, 2457 struct device_attribute *attr, 2458 const char *buf, 2459 size_t count) 2460 { 2461 struct amdgpu_device *adev = dev_get_drvdata(dev); 2462 int err, ret; 2463 int value; 2464 2465 if (amdgpu_in_reset(adev)) 2466 return -EPERM; 2467 if (adev->in_suspend && !adev->in_runpm) 2468 return -EPERM; 2469 2470 err = kstrtoint(buf, 10, &value); 2471 if (err) 2472 return err; 2473 2474 ret = pm_runtime_get_sync(adev_to_drm(adev)->dev); 2475 if (ret < 0) { 2476 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 2477 return ret; 2478 } 2479 2480 ret = amdgpu_dpm_set_fan_control_mode(adev, value); 2481 2482 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev); 2483 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 2484 2485 if (ret) 2486 return -EINVAL; 2487 2488 return count; 2489 } 2490 2491 static ssize_t amdgpu_hwmon_get_pwm1_min(struct device *dev, 2492 struct device_attribute *attr, 2493 char *buf) 2494 { 2495 return sysfs_emit(buf, "%i\n", 0); 2496 } 2497 2498 static ssize_t amdgpu_hwmon_get_pwm1_max(struct device *dev, 2499 struct device_attribute *attr, 2500 char *buf) 2501 { 2502 return sysfs_emit(buf, "%i\n", 255); 2503 } 2504 2505 static ssize_t amdgpu_hwmon_set_pwm1(struct device *dev, 2506 struct device_attribute *attr, 2507 const char *buf, size_t count) 2508 { 2509 struct amdgpu_device *adev = dev_get_drvdata(dev); 2510 int err; 2511 u32 value; 2512 u32 pwm_mode; 2513 2514 if (amdgpu_in_reset(adev)) 2515 return -EPERM; 2516 if (adev->in_suspend && !adev->in_runpm) 2517 return -EPERM; 2518 2519 err = kstrtou32(buf, 10, &value); 2520 if (err) 2521 return err; 2522 2523 err = pm_runtime_get_sync(adev_to_drm(adev)->dev); 2524 if (err < 0) { 2525 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 2526 return err; 2527 } 2528 2529 err = amdgpu_dpm_get_fan_control_mode(adev, &pwm_mode); 2530 if (err) 2531 goto out; 2532 2533 if (pwm_mode != AMD_FAN_CTRL_MANUAL) { 2534 pr_info("manual fan speed control should be enabled first\n"); 2535 err = -EINVAL; 2536 goto out; 2537 } 2538 2539 err = amdgpu_dpm_set_fan_speed_pwm(adev, value); 2540 2541 out: 2542 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev); 2543 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 2544 2545 if (err) 2546 return err; 2547 2548 return count; 2549 } 2550 2551 static ssize_t amdgpu_hwmon_get_pwm1(struct device *dev, 2552 struct device_attribute *attr, 2553 char *buf) 2554 { 2555 struct amdgpu_device *adev = dev_get_drvdata(dev); 2556 int err; 2557 u32 speed = 0; 2558 2559 if (amdgpu_in_reset(adev)) 2560 return -EPERM; 2561 if (adev->in_suspend && !adev->in_runpm) 2562 return -EPERM; 2563 2564 err = pm_runtime_get_sync(adev_to_drm(adev)->dev); 2565 if (err < 0) { 2566 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 2567 return err; 2568 } 2569 2570 err = amdgpu_dpm_get_fan_speed_pwm(adev, &speed); 2571 2572 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev); 2573 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 2574 2575 if (err) 2576 return err; 2577 2578 return sysfs_emit(buf, "%i\n", speed); 2579 } 2580 2581 static ssize_t amdgpu_hwmon_get_fan1_input(struct device *dev, 2582 struct device_attribute *attr, 2583 char *buf) 2584 { 2585 struct amdgpu_device *adev = dev_get_drvdata(dev); 2586 int err; 2587 u32 speed = 0; 2588 2589 if (amdgpu_in_reset(adev)) 2590 return -EPERM; 2591 if (adev->in_suspend && !adev->in_runpm) 2592 return -EPERM; 2593 2594 err = pm_runtime_get_sync(adev_to_drm(adev)->dev); 2595 if (err < 0) { 2596 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 2597 return err; 2598 } 2599 2600 err = amdgpu_dpm_get_fan_speed_rpm(adev, &speed); 2601 2602 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev); 2603 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 2604 2605 if (err) 2606 return err; 2607 2608 return sysfs_emit(buf, "%i\n", speed); 2609 } 2610 2611 static ssize_t amdgpu_hwmon_get_fan1_min(struct device *dev, 2612 struct device_attribute *attr, 2613 char *buf) 2614 { 2615 struct amdgpu_device *adev = dev_get_drvdata(dev); 2616 u32 min_rpm = 0; 2617 u32 size = sizeof(min_rpm); 2618 int r; 2619 2620 if (amdgpu_in_reset(adev)) 2621 return -EPERM; 2622 if (adev->in_suspend && !adev->in_runpm) 2623 return -EPERM; 2624 2625 r = pm_runtime_get_sync(adev_to_drm(adev)->dev); 2626 if (r < 0) { 2627 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 2628 return r; 2629 } 2630 2631 r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_MIN_FAN_RPM, 2632 (void *)&min_rpm, &size); 2633 2634 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev); 2635 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 2636 2637 if (r) 2638 return r; 2639 2640 return sysfs_emit(buf, "%d\n", min_rpm); 2641 } 2642 2643 static ssize_t amdgpu_hwmon_get_fan1_max(struct device *dev, 2644 struct device_attribute *attr, 2645 char *buf) 2646 { 2647 struct amdgpu_device *adev = dev_get_drvdata(dev); 2648 u32 max_rpm = 0; 2649 u32 size = sizeof(max_rpm); 2650 int r; 2651 2652 if (amdgpu_in_reset(adev)) 2653 return -EPERM; 2654 if (adev->in_suspend && !adev->in_runpm) 2655 return -EPERM; 2656 2657 r = pm_runtime_get_sync(adev_to_drm(adev)->dev); 2658 if (r < 0) { 2659 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 2660 return r; 2661 } 2662 2663 r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_MAX_FAN_RPM, 2664 (void *)&max_rpm, &size); 2665 2666 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev); 2667 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 2668 2669 if (r) 2670 return r; 2671 2672 return sysfs_emit(buf, "%d\n", max_rpm); 2673 } 2674 2675 static ssize_t amdgpu_hwmon_get_fan1_target(struct device *dev, 2676 struct device_attribute *attr, 2677 char *buf) 2678 { 2679 struct amdgpu_device *adev = dev_get_drvdata(dev); 2680 int err; 2681 u32 rpm = 0; 2682 2683 if (amdgpu_in_reset(adev)) 2684 return -EPERM; 2685 if (adev->in_suspend && !adev->in_runpm) 2686 return -EPERM; 2687 2688 err = pm_runtime_get_sync(adev_to_drm(adev)->dev); 2689 if (err < 0) { 2690 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 2691 return err; 2692 } 2693 2694 err = amdgpu_dpm_get_fan_speed_rpm(adev, &rpm); 2695 2696 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev); 2697 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 2698 2699 if (err) 2700 return err; 2701 2702 return sysfs_emit(buf, "%i\n", rpm); 2703 } 2704 2705 static ssize_t amdgpu_hwmon_set_fan1_target(struct device *dev, 2706 struct device_attribute *attr, 2707 const char *buf, size_t count) 2708 { 2709 struct amdgpu_device *adev = dev_get_drvdata(dev); 2710 int err; 2711 u32 value; 2712 u32 pwm_mode; 2713 2714 if (amdgpu_in_reset(adev)) 2715 return -EPERM; 2716 if (adev->in_suspend && !adev->in_runpm) 2717 return -EPERM; 2718 2719 err = kstrtou32(buf, 10, &value); 2720 if (err) 2721 return err; 2722 2723 err = pm_runtime_get_sync(adev_to_drm(adev)->dev); 2724 if (err < 0) { 2725 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 2726 return err; 2727 } 2728 2729 err = amdgpu_dpm_get_fan_control_mode(adev, &pwm_mode); 2730 if (err) 2731 goto out; 2732 2733 if (pwm_mode != AMD_FAN_CTRL_MANUAL) { 2734 err = -ENODATA; 2735 goto out; 2736 } 2737 2738 err = amdgpu_dpm_set_fan_speed_rpm(adev, value); 2739 2740 out: 2741 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev); 2742 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 2743 2744 if (err) 2745 return err; 2746 2747 return count; 2748 } 2749 2750 static ssize_t amdgpu_hwmon_get_fan1_enable(struct device *dev, 2751 struct device_attribute *attr, 2752 char *buf) 2753 { 2754 struct amdgpu_device *adev = dev_get_drvdata(dev); 2755 u32 pwm_mode = 0; 2756 int ret; 2757 2758 if (amdgpu_in_reset(adev)) 2759 return -EPERM; 2760 if (adev->in_suspend && !adev->in_runpm) 2761 return -EPERM; 2762 2763 ret = pm_runtime_get_sync(adev_to_drm(adev)->dev); 2764 if (ret < 0) { 2765 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 2766 return ret; 2767 } 2768 2769 ret = amdgpu_dpm_get_fan_control_mode(adev, &pwm_mode); 2770 2771 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev); 2772 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 2773 2774 if (ret) 2775 return -EINVAL; 2776 2777 return sysfs_emit(buf, "%i\n", pwm_mode == AMD_FAN_CTRL_AUTO ? 0 : 1); 2778 } 2779 2780 static ssize_t amdgpu_hwmon_set_fan1_enable(struct device *dev, 2781 struct device_attribute *attr, 2782 const char *buf, 2783 size_t count) 2784 { 2785 struct amdgpu_device *adev = dev_get_drvdata(dev); 2786 int err; 2787 int value; 2788 u32 pwm_mode; 2789 2790 if (amdgpu_in_reset(adev)) 2791 return -EPERM; 2792 if (adev->in_suspend && !adev->in_runpm) 2793 return -EPERM; 2794 2795 err = kstrtoint(buf, 10, &value); 2796 if (err) 2797 return err; 2798 2799 if (value == 0) 2800 pwm_mode = AMD_FAN_CTRL_AUTO; 2801 else if (value == 1) 2802 pwm_mode = AMD_FAN_CTRL_MANUAL; 2803 else 2804 return -EINVAL; 2805 2806 err = pm_runtime_get_sync(adev_to_drm(adev)->dev); 2807 if (err < 0) { 2808 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 2809 return err; 2810 } 2811 2812 err = amdgpu_dpm_set_fan_control_mode(adev, pwm_mode); 2813 2814 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev); 2815 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 2816 2817 if (err) 2818 return -EINVAL; 2819 2820 return count; 2821 } 2822 2823 static ssize_t amdgpu_hwmon_show_vddgfx(struct device *dev, 2824 struct device_attribute *attr, 2825 char *buf) 2826 { 2827 struct amdgpu_device *adev = dev_get_drvdata(dev); 2828 u32 vddgfx; 2829 int r, size = sizeof(vddgfx); 2830 2831 if (amdgpu_in_reset(adev)) 2832 return -EPERM; 2833 if (adev->in_suspend && !adev->in_runpm) 2834 return -EPERM; 2835 2836 r = pm_runtime_get_sync(adev_to_drm(adev)->dev); 2837 if (r < 0) { 2838 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 2839 return r; 2840 } 2841 2842 /* get the voltage */ 2843 r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VDDGFX, 2844 (void *)&vddgfx, &size); 2845 2846 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev); 2847 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 2848 2849 if (r) 2850 return r; 2851 2852 return sysfs_emit(buf, "%d\n", vddgfx); 2853 } 2854 2855 static ssize_t amdgpu_hwmon_show_vddgfx_label(struct device *dev, 2856 struct device_attribute *attr, 2857 char *buf) 2858 { 2859 return sysfs_emit(buf, "vddgfx\n"); 2860 } 2861 2862 static ssize_t amdgpu_hwmon_show_vddnb(struct device *dev, 2863 struct device_attribute *attr, 2864 char *buf) 2865 { 2866 struct amdgpu_device *adev = dev_get_drvdata(dev); 2867 u32 vddnb; 2868 int r, size = sizeof(vddnb); 2869 2870 if (amdgpu_in_reset(adev)) 2871 return -EPERM; 2872 if (adev->in_suspend && !adev->in_runpm) 2873 return -EPERM; 2874 2875 /* only APUs have vddnb */ 2876 if (!(adev->flags & AMD_IS_APU)) 2877 return -EINVAL; 2878 2879 r = pm_runtime_get_sync(adev_to_drm(adev)->dev); 2880 if (r < 0) { 2881 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 2882 return r; 2883 } 2884 2885 /* get the voltage */ 2886 r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VDDNB, 2887 (void *)&vddnb, &size); 2888 2889 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev); 2890 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 2891 2892 if (r) 2893 return r; 2894 2895 return sysfs_emit(buf, "%d\n", vddnb); 2896 } 2897 2898 static ssize_t amdgpu_hwmon_show_vddnb_label(struct device *dev, 2899 struct device_attribute *attr, 2900 char *buf) 2901 { 2902 return sysfs_emit(buf, "vddnb\n"); 2903 } 2904 2905 static ssize_t amdgpu_hwmon_show_power_avg(struct device *dev, 2906 struct device_attribute *attr, 2907 char *buf) 2908 { 2909 struct amdgpu_device *adev = dev_get_drvdata(dev); 2910 u32 query = 0; 2911 int r, size = sizeof(u32); 2912 unsigned uw; 2913 2914 if (amdgpu_in_reset(adev)) 2915 return -EPERM; 2916 if (adev->in_suspend && !adev->in_runpm) 2917 return -EPERM; 2918 2919 r = pm_runtime_get_sync(adev_to_drm(adev)->dev); 2920 if (r < 0) { 2921 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 2922 return r; 2923 } 2924 2925 /* get the voltage */ 2926 r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_POWER, 2927 (void *)&query, &size); 2928 2929 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev); 2930 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 2931 2932 if (r) 2933 return r; 2934 2935 /* convert to microwatts */ 2936 uw = (query >> 8) * 1000000 + (query & 0xff) * 1000; 2937 2938 return sysfs_emit(buf, "%u\n", uw); 2939 } 2940 2941 static ssize_t amdgpu_hwmon_show_power_cap_min(struct device *dev, 2942 struct device_attribute *attr, 2943 char *buf) 2944 { 2945 return sysfs_emit(buf, "%i\n", 0); 2946 } 2947 2948 2949 static ssize_t amdgpu_hwmon_show_power_cap_generic(struct device *dev, 2950 struct device_attribute *attr, 2951 char *buf, 2952 enum pp_power_limit_level pp_limit_level) 2953 { 2954 struct amdgpu_device *adev = dev_get_drvdata(dev); 2955 enum pp_power_type power_type = to_sensor_dev_attr(attr)->index; 2956 uint32_t limit; 2957 ssize_t size; 2958 int r; 2959 2960 if (amdgpu_in_reset(adev)) 2961 return -EPERM; 2962 if (adev->in_suspend && !adev->in_runpm) 2963 return -EPERM; 2964 2965 r = pm_runtime_get_sync(adev_to_drm(adev)->dev); 2966 if (r < 0) { 2967 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 2968 return r; 2969 } 2970 2971 r = amdgpu_dpm_get_power_limit(adev, &limit, 2972 pp_limit_level, power_type); 2973 2974 if (!r) 2975 size = sysfs_emit(buf, "%u\n", limit * 1000000); 2976 else 2977 size = sysfs_emit(buf, "\n"); 2978 2979 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev); 2980 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 2981 2982 return size; 2983 } 2984 2985 2986 static ssize_t amdgpu_hwmon_show_power_cap_max(struct device *dev, 2987 struct device_attribute *attr, 2988 char *buf) 2989 { 2990 return amdgpu_hwmon_show_power_cap_generic(dev, attr, buf, PP_PWR_LIMIT_MAX); 2991 2992 } 2993 2994 static ssize_t amdgpu_hwmon_show_power_cap(struct device *dev, 2995 struct device_attribute *attr, 2996 char *buf) 2997 { 2998 return amdgpu_hwmon_show_power_cap_generic(dev, attr, buf, PP_PWR_LIMIT_CURRENT); 2999 3000 } 3001 3002 static ssize_t amdgpu_hwmon_show_power_cap_default(struct device *dev, 3003 struct device_attribute *attr, 3004 char *buf) 3005 { 3006 return amdgpu_hwmon_show_power_cap_generic(dev, attr, buf, PP_PWR_LIMIT_DEFAULT); 3007 3008 } 3009 3010 static ssize_t amdgpu_hwmon_show_power_label(struct device *dev, 3011 struct device_attribute *attr, 3012 char *buf) 3013 { 3014 struct amdgpu_device *adev = dev_get_drvdata(dev); 3015 uint32_t gc_ver = adev->ip_versions[GC_HWIP][0]; 3016 3017 if (gc_ver == IP_VERSION(10, 3, 1)) 3018 return sysfs_emit(buf, "%s\n", 3019 to_sensor_dev_attr(attr)->index == PP_PWR_TYPE_FAST ? 3020 "fastPPT" : "slowPPT"); 3021 else 3022 return sysfs_emit(buf, "PPT\n"); 3023 } 3024 3025 static ssize_t amdgpu_hwmon_set_power_cap(struct device *dev, 3026 struct device_attribute *attr, 3027 const char *buf, 3028 size_t count) 3029 { 3030 struct amdgpu_device *adev = dev_get_drvdata(dev); 3031 int limit_type = to_sensor_dev_attr(attr)->index; 3032 int err; 3033 u32 value; 3034 3035 if (amdgpu_in_reset(adev)) 3036 return -EPERM; 3037 if (adev->in_suspend && !adev->in_runpm) 3038 return -EPERM; 3039 3040 if (amdgpu_sriov_vf(adev)) 3041 return -EINVAL; 3042 3043 err = kstrtou32(buf, 10, &value); 3044 if (err) 3045 return err; 3046 3047 value = value / 1000000; /* convert to Watt */ 3048 value |= limit_type << 24; 3049 3050 err = pm_runtime_get_sync(adev_to_drm(adev)->dev); 3051 if (err < 0) { 3052 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 3053 return err; 3054 } 3055 3056 err = amdgpu_dpm_set_power_limit(adev, value); 3057 3058 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev); 3059 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 3060 3061 if (err) 3062 return err; 3063 3064 return count; 3065 } 3066 3067 static ssize_t amdgpu_hwmon_show_sclk(struct device *dev, 3068 struct device_attribute *attr, 3069 char *buf) 3070 { 3071 struct amdgpu_device *adev = dev_get_drvdata(dev); 3072 uint32_t sclk; 3073 int r, size = sizeof(sclk); 3074 3075 if (amdgpu_in_reset(adev)) 3076 return -EPERM; 3077 if (adev->in_suspend && !adev->in_runpm) 3078 return -EPERM; 3079 3080 r = pm_runtime_get_sync(adev_to_drm(adev)->dev); 3081 if (r < 0) { 3082 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 3083 return r; 3084 } 3085 3086 /* get the sclk */ 3087 r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GFX_SCLK, 3088 (void *)&sclk, &size); 3089 3090 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev); 3091 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 3092 3093 if (r) 3094 return r; 3095 3096 return sysfs_emit(buf, "%u\n", sclk * 10 * 1000); 3097 } 3098 3099 static ssize_t amdgpu_hwmon_show_sclk_label(struct device *dev, 3100 struct device_attribute *attr, 3101 char *buf) 3102 { 3103 return sysfs_emit(buf, "sclk\n"); 3104 } 3105 3106 static ssize_t amdgpu_hwmon_show_mclk(struct device *dev, 3107 struct device_attribute *attr, 3108 char *buf) 3109 { 3110 struct amdgpu_device *adev = dev_get_drvdata(dev); 3111 uint32_t mclk; 3112 int r, size = sizeof(mclk); 3113 3114 if (amdgpu_in_reset(adev)) 3115 return -EPERM; 3116 if (adev->in_suspend && !adev->in_runpm) 3117 return -EPERM; 3118 3119 r = pm_runtime_get_sync(adev_to_drm(adev)->dev); 3120 if (r < 0) { 3121 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 3122 return r; 3123 } 3124 3125 /* get the sclk */ 3126 r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GFX_MCLK, 3127 (void *)&mclk, &size); 3128 3129 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev); 3130 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 3131 3132 if (r) 3133 return r; 3134 3135 return sysfs_emit(buf, "%u\n", mclk * 10 * 1000); 3136 } 3137 3138 static ssize_t amdgpu_hwmon_show_mclk_label(struct device *dev, 3139 struct device_attribute *attr, 3140 char *buf) 3141 { 3142 return sysfs_emit(buf, "mclk\n"); 3143 } 3144 3145 /** 3146 * DOC: hwmon 3147 * 3148 * The amdgpu driver exposes the following sensor interfaces: 3149 * 3150 * - GPU temperature (via the on-die sensor) 3151 * 3152 * - GPU voltage 3153 * 3154 * - Northbridge voltage (APUs only) 3155 * 3156 * - GPU power 3157 * 3158 * - GPU fan 3159 * 3160 * - GPU gfx/compute engine clock 3161 * 3162 * - GPU memory clock (dGPU only) 3163 * 3164 * hwmon interfaces for GPU temperature: 3165 * 3166 * - temp[1-3]_input: the on die GPU temperature in millidegrees Celsius 3167 * - temp2_input and temp3_input are supported on SOC15 dGPUs only 3168 * 3169 * - temp[1-3]_label: temperature channel label 3170 * - temp2_label and temp3_label are supported on SOC15 dGPUs only 3171 * 3172 * - temp[1-3]_crit: temperature critical max value in millidegrees Celsius 3173 * - temp2_crit and temp3_crit are supported on SOC15 dGPUs only 3174 * 3175 * - temp[1-3]_crit_hyst: temperature hysteresis for critical limit in millidegrees Celsius 3176 * - temp2_crit_hyst and temp3_crit_hyst are supported on SOC15 dGPUs only 3177 * 3178 * - temp[1-3]_emergency: temperature emergency max value(asic shutdown) in millidegrees Celsius 3179 * - these are supported on SOC15 dGPUs only 3180 * 3181 * hwmon interfaces for GPU voltage: 3182 * 3183 * - in0_input: the voltage on the GPU in millivolts 3184 * 3185 * - in1_input: the voltage on the Northbridge in millivolts 3186 * 3187 * hwmon interfaces for GPU power: 3188 * 3189 * - power1_average: average power used by the SoC in microWatts. On APUs this includes the CPU. 3190 * 3191 * - power1_cap_min: minimum cap supported in microWatts 3192 * 3193 * - power1_cap_max: maximum cap supported in microWatts 3194 * 3195 * - power1_cap: selected power cap in microWatts 3196 * 3197 * hwmon interfaces for GPU fan: 3198 * 3199 * - pwm1: pulse width modulation fan level (0-255) 3200 * 3201 * - pwm1_enable: pulse width modulation fan control method (0: no fan speed control, 1: manual fan speed control using pwm interface, 2: automatic fan speed control) 3202 * 3203 * - pwm1_min: pulse width modulation fan control minimum level (0) 3204 * 3205 * - pwm1_max: pulse width modulation fan control maximum level (255) 3206 * 3207 * - fan1_min: a minimum value Unit: revolution/min (RPM) 3208 * 3209 * - fan1_max: a maximum value Unit: revolution/max (RPM) 3210 * 3211 * - fan1_input: fan speed in RPM 3212 * 3213 * - fan[1-\*]_target: Desired fan speed Unit: revolution/min (RPM) 3214 * 3215 * - fan[1-\*]_enable: Enable or disable the sensors.1: Enable 0: Disable 3216 * 3217 * NOTE: DO NOT set the fan speed via "pwm1" and "fan[1-\*]_target" interfaces at the same time. 3218 * That will get the former one overridden. 3219 * 3220 * hwmon interfaces for GPU clocks: 3221 * 3222 * - freq1_input: the gfx/compute clock in hertz 3223 * 3224 * - freq2_input: the memory clock in hertz 3225 * 3226 * You can use hwmon tools like sensors to view this information on your system. 3227 * 3228 */ 3229 3230 static SENSOR_DEVICE_ATTR(temp1_input, S_IRUGO, amdgpu_hwmon_show_temp, NULL, PP_TEMP_EDGE); 3231 static SENSOR_DEVICE_ATTR(temp1_crit, S_IRUGO, amdgpu_hwmon_show_temp_thresh, NULL, 0); 3232 static SENSOR_DEVICE_ATTR(temp1_crit_hyst, S_IRUGO, amdgpu_hwmon_show_temp_thresh, NULL, 1); 3233 static SENSOR_DEVICE_ATTR(temp1_emergency, S_IRUGO, amdgpu_hwmon_show_temp_emergency, NULL, PP_TEMP_EDGE); 3234 static SENSOR_DEVICE_ATTR(temp2_input, S_IRUGO, amdgpu_hwmon_show_temp, NULL, PP_TEMP_JUNCTION); 3235 static SENSOR_DEVICE_ATTR(temp2_crit, S_IRUGO, amdgpu_hwmon_show_hotspot_temp_thresh, NULL, 0); 3236 static SENSOR_DEVICE_ATTR(temp2_crit_hyst, S_IRUGO, amdgpu_hwmon_show_hotspot_temp_thresh, NULL, 1); 3237 static SENSOR_DEVICE_ATTR(temp2_emergency, S_IRUGO, amdgpu_hwmon_show_temp_emergency, NULL, PP_TEMP_JUNCTION); 3238 static SENSOR_DEVICE_ATTR(temp3_input, S_IRUGO, amdgpu_hwmon_show_temp, NULL, PP_TEMP_MEM); 3239 static SENSOR_DEVICE_ATTR(temp3_crit, S_IRUGO, amdgpu_hwmon_show_mem_temp_thresh, NULL, 0); 3240 static SENSOR_DEVICE_ATTR(temp3_crit_hyst, S_IRUGO, amdgpu_hwmon_show_mem_temp_thresh, NULL, 1); 3241 static SENSOR_DEVICE_ATTR(temp3_emergency, S_IRUGO, amdgpu_hwmon_show_temp_emergency, NULL, PP_TEMP_MEM); 3242 static SENSOR_DEVICE_ATTR(temp1_label, S_IRUGO, amdgpu_hwmon_show_temp_label, NULL, PP_TEMP_EDGE); 3243 static SENSOR_DEVICE_ATTR(temp2_label, S_IRUGO, amdgpu_hwmon_show_temp_label, NULL, PP_TEMP_JUNCTION); 3244 static SENSOR_DEVICE_ATTR(temp3_label, S_IRUGO, amdgpu_hwmon_show_temp_label, NULL, PP_TEMP_MEM); 3245 static SENSOR_DEVICE_ATTR(pwm1, S_IRUGO | S_IWUSR, amdgpu_hwmon_get_pwm1, amdgpu_hwmon_set_pwm1, 0); 3246 static SENSOR_DEVICE_ATTR(pwm1_enable, S_IRUGO | S_IWUSR, amdgpu_hwmon_get_pwm1_enable, amdgpu_hwmon_set_pwm1_enable, 0); 3247 static SENSOR_DEVICE_ATTR(pwm1_min, S_IRUGO, amdgpu_hwmon_get_pwm1_min, NULL, 0); 3248 static SENSOR_DEVICE_ATTR(pwm1_max, S_IRUGO, amdgpu_hwmon_get_pwm1_max, NULL, 0); 3249 static SENSOR_DEVICE_ATTR(fan1_input, S_IRUGO, amdgpu_hwmon_get_fan1_input, NULL, 0); 3250 static SENSOR_DEVICE_ATTR(fan1_min, S_IRUGO, amdgpu_hwmon_get_fan1_min, NULL, 0); 3251 static SENSOR_DEVICE_ATTR(fan1_max, S_IRUGO, amdgpu_hwmon_get_fan1_max, NULL, 0); 3252 static SENSOR_DEVICE_ATTR(fan1_target, S_IRUGO | S_IWUSR, amdgpu_hwmon_get_fan1_target, amdgpu_hwmon_set_fan1_target, 0); 3253 static SENSOR_DEVICE_ATTR(fan1_enable, S_IRUGO | S_IWUSR, amdgpu_hwmon_get_fan1_enable, amdgpu_hwmon_set_fan1_enable, 0); 3254 static SENSOR_DEVICE_ATTR(in0_input, S_IRUGO, amdgpu_hwmon_show_vddgfx, NULL, 0); 3255 static SENSOR_DEVICE_ATTR(in0_label, S_IRUGO, amdgpu_hwmon_show_vddgfx_label, NULL, 0); 3256 static SENSOR_DEVICE_ATTR(in1_input, S_IRUGO, amdgpu_hwmon_show_vddnb, NULL, 0); 3257 static SENSOR_DEVICE_ATTR(in1_label, S_IRUGO, amdgpu_hwmon_show_vddnb_label, NULL, 0); 3258 static SENSOR_DEVICE_ATTR(power1_average, S_IRUGO, amdgpu_hwmon_show_power_avg, NULL, 0); 3259 static SENSOR_DEVICE_ATTR(power1_cap_max, S_IRUGO, amdgpu_hwmon_show_power_cap_max, NULL, 0); 3260 static SENSOR_DEVICE_ATTR(power1_cap_min, S_IRUGO, amdgpu_hwmon_show_power_cap_min, NULL, 0); 3261 static SENSOR_DEVICE_ATTR(power1_cap, S_IRUGO | S_IWUSR, amdgpu_hwmon_show_power_cap, amdgpu_hwmon_set_power_cap, 0); 3262 static SENSOR_DEVICE_ATTR(power1_cap_default, S_IRUGO, amdgpu_hwmon_show_power_cap_default, NULL, 0); 3263 static SENSOR_DEVICE_ATTR(power1_label, S_IRUGO, amdgpu_hwmon_show_power_label, NULL, 0); 3264 static SENSOR_DEVICE_ATTR(power2_average, S_IRUGO, amdgpu_hwmon_show_power_avg, NULL, 1); 3265 static SENSOR_DEVICE_ATTR(power2_cap_max, S_IRUGO, amdgpu_hwmon_show_power_cap_max, NULL, 1); 3266 static SENSOR_DEVICE_ATTR(power2_cap_min, S_IRUGO, amdgpu_hwmon_show_power_cap_min, NULL, 1); 3267 static SENSOR_DEVICE_ATTR(power2_cap, S_IRUGO | S_IWUSR, amdgpu_hwmon_show_power_cap, amdgpu_hwmon_set_power_cap, 1); 3268 static SENSOR_DEVICE_ATTR(power2_cap_default, S_IRUGO, amdgpu_hwmon_show_power_cap_default, NULL, 1); 3269 static SENSOR_DEVICE_ATTR(power2_label, S_IRUGO, amdgpu_hwmon_show_power_label, NULL, 1); 3270 static SENSOR_DEVICE_ATTR(freq1_input, S_IRUGO, amdgpu_hwmon_show_sclk, NULL, 0); 3271 static SENSOR_DEVICE_ATTR(freq1_label, S_IRUGO, amdgpu_hwmon_show_sclk_label, NULL, 0); 3272 static SENSOR_DEVICE_ATTR(freq2_input, S_IRUGO, amdgpu_hwmon_show_mclk, NULL, 0); 3273 static SENSOR_DEVICE_ATTR(freq2_label, S_IRUGO, amdgpu_hwmon_show_mclk_label, NULL, 0); 3274 3275 static struct attribute *hwmon_attributes[] = { 3276 &sensor_dev_attr_temp1_input.dev_attr.attr, 3277 &sensor_dev_attr_temp1_crit.dev_attr.attr, 3278 &sensor_dev_attr_temp1_crit_hyst.dev_attr.attr, 3279 &sensor_dev_attr_temp2_input.dev_attr.attr, 3280 &sensor_dev_attr_temp2_crit.dev_attr.attr, 3281 &sensor_dev_attr_temp2_crit_hyst.dev_attr.attr, 3282 &sensor_dev_attr_temp3_input.dev_attr.attr, 3283 &sensor_dev_attr_temp3_crit.dev_attr.attr, 3284 &sensor_dev_attr_temp3_crit_hyst.dev_attr.attr, 3285 &sensor_dev_attr_temp1_emergency.dev_attr.attr, 3286 &sensor_dev_attr_temp2_emergency.dev_attr.attr, 3287 &sensor_dev_attr_temp3_emergency.dev_attr.attr, 3288 &sensor_dev_attr_temp1_label.dev_attr.attr, 3289 &sensor_dev_attr_temp2_label.dev_attr.attr, 3290 &sensor_dev_attr_temp3_label.dev_attr.attr, 3291 &sensor_dev_attr_pwm1.dev_attr.attr, 3292 &sensor_dev_attr_pwm1_enable.dev_attr.attr, 3293 &sensor_dev_attr_pwm1_min.dev_attr.attr, 3294 &sensor_dev_attr_pwm1_max.dev_attr.attr, 3295 &sensor_dev_attr_fan1_input.dev_attr.attr, 3296 &sensor_dev_attr_fan1_min.dev_attr.attr, 3297 &sensor_dev_attr_fan1_max.dev_attr.attr, 3298 &sensor_dev_attr_fan1_target.dev_attr.attr, 3299 &sensor_dev_attr_fan1_enable.dev_attr.attr, 3300 &sensor_dev_attr_in0_input.dev_attr.attr, 3301 &sensor_dev_attr_in0_label.dev_attr.attr, 3302 &sensor_dev_attr_in1_input.dev_attr.attr, 3303 &sensor_dev_attr_in1_label.dev_attr.attr, 3304 &sensor_dev_attr_power1_average.dev_attr.attr, 3305 &sensor_dev_attr_power1_cap_max.dev_attr.attr, 3306 &sensor_dev_attr_power1_cap_min.dev_attr.attr, 3307 &sensor_dev_attr_power1_cap.dev_attr.attr, 3308 &sensor_dev_attr_power1_cap_default.dev_attr.attr, 3309 &sensor_dev_attr_power1_label.dev_attr.attr, 3310 &sensor_dev_attr_power2_average.dev_attr.attr, 3311 &sensor_dev_attr_power2_cap_max.dev_attr.attr, 3312 &sensor_dev_attr_power2_cap_min.dev_attr.attr, 3313 &sensor_dev_attr_power2_cap.dev_attr.attr, 3314 &sensor_dev_attr_power2_cap_default.dev_attr.attr, 3315 &sensor_dev_attr_power2_label.dev_attr.attr, 3316 &sensor_dev_attr_freq1_input.dev_attr.attr, 3317 &sensor_dev_attr_freq1_label.dev_attr.attr, 3318 &sensor_dev_attr_freq2_input.dev_attr.attr, 3319 &sensor_dev_attr_freq2_label.dev_attr.attr, 3320 NULL 3321 }; 3322 3323 static umode_t hwmon_attributes_visible(struct kobject *kobj, 3324 struct attribute *attr, int index) 3325 { 3326 struct device *dev = kobj_to_dev(kobj); 3327 struct amdgpu_device *adev = dev_get_drvdata(dev); 3328 umode_t effective_mode = attr->mode; 3329 uint32_t gc_ver = adev->ip_versions[GC_HWIP][0]; 3330 3331 /* under multi-vf mode, the hwmon attributes are all not supported */ 3332 if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev)) 3333 return 0; 3334 3335 /* under pp one vf mode manage of hwmon attributes is not supported */ 3336 if (amdgpu_sriov_is_pp_one_vf(adev)) 3337 effective_mode &= ~S_IWUSR; 3338 3339 /* Skip fan attributes if fan is not present */ 3340 if (adev->pm.no_fan && (attr == &sensor_dev_attr_pwm1.dev_attr.attr || 3341 attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr || 3342 attr == &sensor_dev_attr_pwm1_max.dev_attr.attr || 3343 attr == &sensor_dev_attr_pwm1_min.dev_attr.attr || 3344 attr == &sensor_dev_attr_fan1_input.dev_attr.attr || 3345 attr == &sensor_dev_attr_fan1_min.dev_attr.attr || 3346 attr == &sensor_dev_attr_fan1_max.dev_attr.attr || 3347 attr == &sensor_dev_attr_fan1_target.dev_attr.attr || 3348 attr == &sensor_dev_attr_fan1_enable.dev_attr.attr)) 3349 return 0; 3350 3351 /* Skip fan attributes on APU */ 3352 if ((adev->flags & AMD_IS_APU) && 3353 (attr == &sensor_dev_attr_pwm1.dev_attr.attr || 3354 attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr || 3355 attr == &sensor_dev_attr_pwm1_max.dev_attr.attr || 3356 attr == &sensor_dev_attr_pwm1_min.dev_attr.attr || 3357 attr == &sensor_dev_attr_fan1_input.dev_attr.attr || 3358 attr == &sensor_dev_attr_fan1_min.dev_attr.attr || 3359 attr == &sensor_dev_attr_fan1_max.dev_attr.attr || 3360 attr == &sensor_dev_attr_fan1_target.dev_attr.attr || 3361 attr == &sensor_dev_attr_fan1_enable.dev_attr.attr)) 3362 return 0; 3363 3364 /* Skip crit temp on APU */ 3365 if ((adev->flags & AMD_IS_APU) && (adev->family >= AMDGPU_FAMILY_CZ) && 3366 (attr == &sensor_dev_attr_temp1_crit.dev_attr.attr || 3367 attr == &sensor_dev_attr_temp1_crit_hyst.dev_attr.attr)) 3368 return 0; 3369 3370 /* Skip limit attributes if DPM is not enabled */ 3371 if (!adev->pm.dpm_enabled && 3372 (attr == &sensor_dev_attr_temp1_crit.dev_attr.attr || 3373 attr == &sensor_dev_attr_temp1_crit_hyst.dev_attr.attr || 3374 attr == &sensor_dev_attr_pwm1.dev_attr.attr || 3375 attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr || 3376 attr == &sensor_dev_attr_pwm1_max.dev_attr.attr || 3377 attr == &sensor_dev_attr_pwm1_min.dev_attr.attr || 3378 attr == &sensor_dev_attr_fan1_input.dev_attr.attr || 3379 attr == &sensor_dev_attr_fan1_min.dev_attr.attr || 3380 attr == &sensor_dev_attr_fan1_max.dev_attr.attr || 3381 attr == &sensor_dev_attr_fan1_target.dev_attr.attr || 3382 attr == &sensor_dev_attr_fan1_enable.dev_attr.attr)) 3383 return 0; 3384 3385 /* mask fan attributes if we have no bindings for this asic to expose */ 3386 if (((amdgpu_dpm_get_fan_speed_pwm(adev, NULL) == -EOPNOTSUPP) && 3387 attr == &sensor_dev_attr_pwm1.dev_attr.attr) || /* can't query fan */ 3388 ((amdgpu_dpm_get_fan_control_mode(adev, NULL) == -EOPNOTSUPP) && 3389 attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr)) /* can't query state */ 3390 effective_mode &= ~S_IRUGO; 3391 3392 if (((amdgpu_dpm_set_fan_speed_pwm(adev, U32_MAX) == -EOPNOTSUPP) && 3393 attr == &sensor_dev_attr_pwm1.dev_attr.attr) || /* can't manage fan */ 3394 ((amdgpu_dpm_set_fan_control_mode(adev, U32_MAX) == -EOPNOTSUPP) && 3395 attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr)) /* can't manage state */ 3396 effective_mode &= ~S_IWUSR; 3397 3398 /* In the case of APUs, this is only implemented on Vangogh */ 3399 if (((adev->family == AMDGPU_FAMILY_SI) || 3400 ((adev->flags & AMD_IS_APU) && (gc_ver != IP_VERSION(10, 3, 1)))) && 3401 (attr == &sensor_dev_attr_power1_cap_max.dev_attr.attr || 3402 attr == &sensor_dev_attr_power1_cap_min.dev_attr.attr || 3403 attr == &sensor_dev_attr_power1_cap.dev_attr.attr || 3404 attr == &sensor_dev_attr_power1_cap_default.dev_attr.attr)) 3405 return 0; 3406 3407 /* not implemented yet for APUs having < GC 9.3.0 (Renoir) */ 3408 if (((adev->family == AMDGPU_FAMILY_SI) || 3409 ((adev->flags & AMD_IS_APU) && (gc_ver < IP_VERSION(9, 3, 0)))) && 3410 (attr == &sensor_dev_attr_power1_average.dev_attr.attr)) 3411 return 0; 3412 3413 /* hide max/min values if we can't both query and manage the fan */ 3414 if (((amdgpu_dpm_set_fan_speed_pwm(adev, U32_MAX) == -EOPNOTSUPP) && 3415 (amdgpu_dpm_get_fan_speed_pwm(adev, NULL) == -EOPNOTSUPP) && 3416 (amdgpu_dpm_set_fan_speed_rpm(adev, U32_MAX) == -EOPNOTSUPP) && 3417 (amdgpu_dpm_get_fan_speed_rpm(adev, NULL) == -EOPNOTSUPP)) && 3418 (attr == &sensor_dev_attr_pwm1_max.dev_attr.attr || 3419 attr == &sensor_dev_attr_pwm1_min.dev_attr.attr)) 3420 return 0; 3421 3422 if ((amdgpu_dpm_set_fan_speed_rpm(adev, U32_MAX) == -EOPNOTSUPP) && 3423 (amdgpu_dpm_get_fan_speed_rpm(adev, NULL) == -EOPNOTSUPP) && 3424 (attr == &sensor_dev_attr_fan1_max.dev_attr.attr || 3425 attr == &sensor_dev_attr_fan1_min.dev_attr.attr)) 3426 return 0; 3427 3428 if ((adev->family == AMDGPU_FAMILY_SI || /* not implemented yet */ 3429 adev->family == AMDGPU_FAMILY_KV) && /* not implemented yet */ 3430 (attr == &sensor_dev_attr_in0_input.dev_attr.attr || 3431 attr == &sensor_dev_attr_in0_label.dev_attr.attr)) 3432 return 0; 3433 3434 /* only APUs have vddnb */ 3435 if (!(adev->flags & AMD_IS_APU) && 3436 (attr == &sensor_dev_attr_in1_input.dev_attr.attr || 3437 attr == &sensor_dev_attr_in1_label.dev_attr.attr)) 3438 return 0; 3439 3440 /* no mclk on APUs */ 3441 if ((adev->flags & AMD_IS_APU) && 3442 (attr == &sensor_dev_attr_freq2_input.dev_attr.attr || 3443 attr == &sensor_dev_attr_freq2_label.dev_attr.attr)) 3444 return 0; 3445 3446 /* only SOC15 dGPUs support hotspot and mem temperatures */ 3447 if (((adev->flags & AMD_IS_APU) || gc_ver < IP_VERSION(9, 0, 0)) && 3448 (attr == &sensor_dev_attr_temp2_crit.dev_attr.attr || 3449 attr == &sensor_dev_attr_temp2_crit_hyst.dev_attr.attr || 3450 attr == &sensor_dev_attr_temp3_crit.dev_attr.attr || 3451 attr == &sensor_dev_attr_temp3_crit_hyst.dev_attr.attr || 3452 attr == &sensor_dev_attr_temp1_emergency.dev_attr.attr || 3453 attr == &sensor_dev_attr_temp2_emergency.dev_attr.attr || 3454 attr == &sensor_dev_attr_temp3_emergency.dev_attr.attr || 3455 attr == &sensor_dev_attr_temp2_input.dev_attr.attr || 3456 attr == &sensor_dev_attr_temp3_input.dev_attr.attr || 3457 attr == &sensor_dev_attr_temp2_label.dev_attr.attr || 3458 attr == &sensor_dev_attr_temp3_label.dev_attr.attr)) 3459 return 0; 3460 3461 /* only Vangogh has fast PPT limit and power labels */ 3462 if (!(gc_ver == IP_VERSION(10, 3, 1)) && 3463 (attr == &sensor_dev_attr_power2_average.dev_attr.attr || 3464 attr == &sensor_dev_attr_power2_cap_max.dev_attr.attr || 3465 attr == &sensor_dev_attr_power2_cap_min.dev_attr.attr || 3466 attr == &sensor_dev_attr_power2_cap.dev_attr.attr || 3467 attr == &sensor_dev_attr_power2_cap_default.dev_attr.attr || 3468 attr == &sensor_dev_attr_power2_label.dev_attr.attr)) 3469 return 0; 3470 3471 return effective_mode; 3472 } 3473 3474 static const struct attribute_group hwmon_attrgroup = { 3475 .attrs = hwmon_attributes, 3476 .is_visible = hwmon_attributes_visible, 3477 }; 3478 3479 static const struct attribute_group *hwmon_groups[] = { 3480 &hwmon_attrgroup, 3481 NULL 3482 }; 3483 3484 int amdgpu_pm_sysfs_init(struct amdgpu_device *adev) 3485 { 3486 int ret; 3487 uint32_t mask = 0; 3488 3489 if (adev->pm.sysfs_initialized) 3490 return 0; 3491 3492 INIT_LIST_HEAD(&adev->pm.pm_attr_list); 3493 3494 if (adev->pm.dpm_enabled == 0) 3495 return 0; 3496 3497 adev->pm.int_hwmon_dev = hwmon_device_register_with_groups(adev->dev, 3498 DRIVER_NAME, adev, 3499 hwmon_groups); 3500 if (IS_ERR(adev->pm.int_hwmon_dev)) { 3501 ret = PTR_ERR(adev->pm.int_hwmon_dev); 3502 dev_err(adev->dev, 3503 "Unable to register hwmon device: %d\n", ret); 3504 return ret; 3505 } 3506 3507 switch (amdgpu_virt_get_sriov_vf_mode(adev)) { 3508 case SRIOV_VF_MODE_ONE_VF: 3509 mask = ATTR_FLAG_ONEVF; 3510 break; 3511 case SRIOV_VF_MODE_MULTI_VF: 3512 mask = 0; 3513 break; 3514 case SRIOV_VF_MODE_BARE_METAL: 3515 default: 3516 mask = ATTR_FLAG_MASK_ALL; 3517 break; 3518 } 3519 3520 ret = amdgpu_device_attr_create_groups(adev, 3521 amdgpu_device_attrs, 3522 ARRAY_SIZE(amdgpu_device_attrs), 3523 mask, 3524 &adev->pm.pm_attr_list); 3525 if (ret) 3526 return ret; 3527 3528 adev->pm.sysfs_initialized = true; 3529 3530 return 0; 3531 } 3532 3533 void amdgpu_pm_sysfs_fini(struct amdgpu_device *adev) 3534 { 3535 if (adev->pm.int_hwmon_dev) 3536 hwmon_device_unregister(adev->pm.int_hwmon_dev); 3537 3538 amdgpu_device_attr_remove_groups(adev, &adev->pm.pm_attr_list); 3539 } 3540 3541 /* 3542 * Debugfs info 3543 */ 3544 #if defined(CONFIG_DEBUG_FS) 3545 3546 static void amdgpu_debugfs_prints_cpu_info(struct seq_file *m, 3547 struct amdgpu_device *adev) { 3548 uint16_t *p_val; 3549 uint32_t size; 3550 int i; 3551 uint32_t num_cpu_cores = amdgpu_dpm_get_num_cpu_cores(adev); 3552 3553 if (amdgpu_dpm_is_cclk_dpm_supported(adev)) { 3554 p_val = kcalloc(num_cpu_cores, sizeof(uint16_t), 3555 GFP_KERNEL); 3556 3557 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_CPU_CLK, 3558 (void *)p_val, &size)) { 3559 for (i = 0; i < num_cpu_cores; i++) 3560 seq_printf(m, "\t%u MHz (CPU%d)\n", 3561 *(p_val + i), i); 3562 } 3563 3564 kfree(p_val); 3565 } 3566 } 3567 3568 static int amdgpu_debugfs_pm_info_pp(struct seq_file *m, struct amdgpu_device *adev) 3569 { 3570 uint32_t mp1_ver = adev->ip_versions[MP1_HWIP][0]; 3571 uint32_t gc_ver = adev->ip_versions[GC_HWIP][0]; 3572 uint32_t value; 3573 uint64_t value64 = 0; 3574 uint32_t query = 0; 3575 int size; 3576 3577 /* GPU Clocks */ 3578 size = sizeof(value); 3579 seq_printf(m, "GFX Clocks and Power:\n"); 3580 3581 amdgpu_debugfs_prints_cpu_info(m, adev); 3582 3583 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GFX_MCLK, (void *)&value, &size)) 3584 seq_printf(m, "\t%u MHz (MCLK)\n", value/100); 3585 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GFX_SCLK, (void *)&value, &size)) 3586 seq_printf(m, "\t%u MHz (SCLK)\n", value/100); 3587 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK, (void *)&value, &size)) 3588 seq_printf(m, "\t%u MHz (PSTATE_SCLK)\n", value/100); 3589 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK, (void *)&value, &size)) 3590 seq_printf(m, "\t%u MHz (PSTATE_MCLK)\n", value/100); 3591 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VDDGFX, (void *)&value, &size)) 3592 seq_printf(m, "\t%u mV (VDDGFX)\n", value); 3593 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VDDNB, (void *)&value, &size)) 3594 seq_printf(m, "\t%u mV (VDDNB)\n", value); 3595 size = sizeof(uint32_t); 3596 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_POWER, (void *)&query, &size)) 3597 seq_printf(m, "\t%u.%u W (average GPU)\n", query >> 8, query & 0xff); 3598 size = sizeof(value); 3599 seq_printf(m, "\n"); 3600 3601 /* GPU Temp */ 3602 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_TEMP, (void *)&value, &size)) 3603 seq_printf(m, "GPU Temperature: %u C\n", value/1000); 3604 3605 /* GPU Load */ 3606 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_LOAD, (void *)&value, &size)) 3607 seq_printf(m, "GPU Load: %u %%\n", value); 3608 /* MEM Load */ 3609 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_MEM_LOAD, (void *)&value, &size)) 3610 seq_printf(m, "MEM Load: %u %%\n", value); 3611 3612 seq_printf(m, "\n"); 3613 3614 /* SMC feature mask */ 3615 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK, (void *)&value64, &size)) 3616 seq_printf(m, "SMC Feature Mask: 0x%016llx\n", value64); 3617 3618 /* ASICs greater than CHIP_VEGA20 supports these sensors */ 3619 if (gc_ver != IP_VERSION(9, 4, 0) && mp1_ver > IP_VERSION(9, 0, 0)) { 3620 /* VCN clocks */ 3621 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VCN_POWER_STATE, (void *)&value, &size)) { 3622 if (!value) { 3623 seq_printf(m, "VCN: Disabled\n"); 3624 } else { 3625 seq_printf(m, "VCN: Enabled\n"); 3626 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_DCLK, (void *)&value, &size)) 3627 seq_printf(m, "\t%u MHz (DCLK)\n", value/100); 3628 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_VCLK, (void *)&value, &size)) 3629 seq_printf(m, "\t%u MHz (VCLK)\n", value/100); 3630 } 3631 } 3632 seq_printf(m, "\n"); 3633 } else { 3634 /* UVD clocks */ 3635 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_POWER, (void *)&value, &size)) { 3636 if (!value) { 3637 seq_printf(m, "UVD: Disabled\n"); 3638 } else { 3639 seq_printf(m, "UVD: Enabled\n"); 3640 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_DCLK, (void *)&value, &size)) 3641 seq_printf(m, "\t%u MHz (DCLK)\n", value/100); 3642 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_VCLK, (void *)&value, &size)) 3643 seq_printf(m, "\t%u MHz (VCLK)\n", value/100); 3644 } 3645 } 3646 seq_printf(m, "\n"); 3647 3648 /* VCE clocks */ 3649 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VCE_POWER, (void *)&value, &size)) { 3650 if (!value) { 3651 seq_printf(m, "VCE: Disabled\n"); 3652 } else { 3653 seq_printf(m, "VCE: Enabled\n"); 3654 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VCE_ECCLK, (void *)&value, &size)) 3655 seq_printf(m, "\t%u MHz (ECCLK)\n", value/100); 3656 } 3657 } 3658 } 3659 3660 return 0; 3661 } 3662 3663 static void amdgpu_parse_cg_state(struct seq_file *m, u64 flags) 3664 { 3665 int i; 3666 3667 for (i = 0; clocks[i].flag; i++) 3668 seq_printf(m, "\t%s: %s\n", clocks[i].name, 3669 (flags & clocks[i].flag) ? "On" : "Off"); 3670 } 3671 3672 static int amdgpu_debugfs_pm_info_show(struct seq_file *m, void *unused) 3673 { 3674 struct amdgpu_device *adev = (struct amdgpu_device *)m->private; 3675 struct drm_device *dev = adev_to_drm(adev); 3676 u64 flags = 0; 3677 int r; 3678 3679 if (amdgpu_in_reset(adev)) 3680 return -EPERM; 3681 if (adev->in_suspend && !adev->in_runpm) 3682 return -EPERM; 3683 3684 r = pm_runtime_get_sync(dev->dev); 3685 if (r < 0) { 3686 pm_runtime_put_autosuspend(dev->dev); 3687 return r; 3688 } 3689 3690 if (amdgpu_dpm_debugfs_print_current_performance_level(adev, m)) { 3691 r = amdgpu_debugfs_pm_info_pp(m, adev); 3692 if (r) 3693 goto out; 3694 } 3695 3696 amdgpu_device_ip_get_clockgating_state(adev, &flags); 3697 3698 seq_printf(m, "Clock Gating Flags Mask: 0x%llx\n", flags); 3699 amdgpu_parse_cg_state(m, flags); 3700 seq_printf(m, "\n"); 3701 3702 out: 3703 pm_runtime_mark_last_busy(dev->dev); 3704 pm_runtime_put_autosuspend(dev->dev); 3705 3706 return r; 3707 } 3708 3709 DEFINE_SHOW_ATTRIBUTE(amdgpu_debugfs_pm_info); 3710 3711 /* 3712 * amdgpu_pm_priv_buffer_read - Read memory region allocated to FW 3713 * 3714 * Reads debug memory region allocated to PMFW 3715 */ 3716 static ssize_t amdgpu_pm_prv_buffer_read(struct file *f, char __user *buf, 3717 size_t size, loff_t *pos) 3718 { 3719 struct amdgpu_device *adev = file_inode(f)->i_private; 3720 size_t smu_prv_buf_size; 3721 void *smu_prv_buf; 3722 int ret = 0; 3723 3724 if (amdgpu_in_reset(adev)) 3725 return -EPERM; 3726 if (adev->in_suspend && !adev->in_runpm) 3727 return -EPERM; 3728 3729 ret = amdgpu_dpm_get_smu_prv_buf_details(adev, &smu_prv_buf, &smu_prv_buf_size); 3730 if (ret) 3731 return ret; 3732 3733 if (!smu_prv_buf || !smu_prv_buf_size) 3734 return -EINVAL; 3735 3736 return simple_read_from_buffer(buf, size, pos, smu_prv_buf, 3737 smu_prv_buf_size); 3738 } 3739 3740 static const struct file_operations amdgpu_debugfs_pm_prv_buffer_fops = { 3741 .owner = THIS_MODULE, 3742 .open = simple_open, 3743 .read = amdgpu_pm_prv_buffer_read, 3744 .llseek = default_llseek, 3745 }; 3746 3747 #endif 3748 3749 void amdgpu_debugfs_pm_init(struct amdgpu_device *adev) 3750 { 3751 #if defined(CONFIG_DEBUG_FS) 3752 struct drm_minor *minor = adev_to_drm(adev)->primary; 3753 struct dentry *root = minor->debugfs_root; 3754 3755 if (!adev->pm.dpm_enabled) 3756 return; 3757 3758 debugfs_create_file("amdgpu_pm_info", 0444, root, adev, 3759 &amdgpu_debugfs_pm_info_fops); 3760 3761 if (adev->pm.smu_prv_buffer_size > 0) 3762 debugfs_create_file_size("amdgpu_pm_prv_buffer", 0444, root, 3763 adev, 3764 &amdgpu_debugfs_pm_prv_buffer_fops, 3765 adev->pm.smu_prv_buffer_size); 3766 3767 amdgpu_dpm_stb_debug_fs_init(adev); 3768 #endif 3769 } 3770