1 /*
2  * Copyright 2021 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  */
23 
24 #include "amdgpu.h"
25 #include "amdgpu_display.h"
26 #include "hwmgr.h"
27 #include "amdgpu_smu.h"
28 
29 void amdgpu_dpm_get_active_displays(struct amdgpu_device *adev)
30 {
31 	struct drm_device *ddev = adev_to_drm(adev);
32 	struct drm_crtc *crtc;
33 	struct amdgpu_crtc *amdgpu_crtc;
34 
35 	adev->pm.dpm.new_active_crtcs = 0;
36 	adev->pm.dpm.new_active_crtc_count = 0;
37 	if (adev->mode_info.num_crtc && adev->mode_info.mode_config_initialized) {
38 		list_for_each_entry(crtc,
39 				    &ddev->mode_config.crtc_list, head) {
40 			amdgpu_crtc = to_amdgpu_crtc(crtc);
41 			if (amdgpu_crtc->enabled) {
42 				adev->pm.dpm.new_active_crtcs |= (1 << amdgpu_crtc->crtc_id);
43 				adev->pm.dpm.new_active_crtc_count++;
44 			}
45 		}
46 	}
47 }
48 
49 u32 amdgpu_dpm_get_vblank_time(struct amdgpu_device *adev)
50 {
51 	struct drm_device *dev = adev_to_drm(adev);
52 	struct drm_crtc *crtc;
53 	struct amdgpu_crtc *amdgpu_crtc;
54 	u32 vblank_in_pixels;
55 	u32 vblank_time_us = 0xffffffff; /* if the displays are off, vblank time is max */
56 
57 	if (adev->mode_info.num_crtc && adev->mode_info.mode_config_initialized) {
58 		list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
59 			amdgpu_crtc = to_amdgpu_crtc(crtc);
60 			if (crtc->enabled && amdgpu_crtc->enabled && amdgpu_crtc->hw_mode.clock) {
61 				vblank_in_pixels =
62 					amdgpu_crtc->hw_mode.crtc_htotal *
63 					(amdgpu_crtc->hw_mode.crtc_vblank_end -
64 					amdgpu_crtc->hw_mode.crtc_vdisplay +
65 					(amdgpu_crtc->v_border * 2));
66 
67 				vblank_time_us = vblank_in_pixels * 1000 / amdgpu_crtc->hw_mode.clock;
68 				break;
69 			}
70 		}
71 	}
72 
73 	return vblank_time_us;
74 }
75 
76 u32 amdgpu_dpm_get_vrefresh(struct amdgpu_device *adev)
77 {
78 	struct drm_device *dev = adev_to_drm(adev);
79 	struct drm_crtc *crtc;
80 	struct amdgpu_crtc *amdgpu_crtc;
81 	u32 vrefresh = 0;
82 
83 	if (adev->mode_info.num_crtc && adev->mode_info.mode_config_initialized) {
84 		list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
85 			amdgpu_crtc = to_amdgpu_crtc(crtc);
86 			if (crtc->enabled && amdgpu_crtc->enabled && amdgpu_crtc->hw_mode.clock) {
87 				vrefresh = drm_mode_vrefresh(&amdgpu_crtc->hw_mode);
88 				break;
89 			}
90 		}
91 	}
92 
93 	return vrefresh;
94 }
95