1 /* 2 * Copyright 2011 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Alex Deucher 23 */ 24 25 #include "amdgpu.h" 26 #include "amdgpu_atombios.h" 27 #include "amdgpu_i2c.h" 28 #include "amdgpu_dpm.h" 29 #include "atom.h" 30 #include "amd_pcie.h" 31 #include "amdgpu_display.h" 32 #include "hwmgr.h" 33 #include <linux/power_supply.h> 34 #include "amdgpu_smu.h" 35 36 #define amdgpu_dpm_enable_bapm(adev, e) \ 37 ((adev)->powerplay.pp_funcs->enable_bapm((adev)->powerplay.pp_handle, (e))) 38 39 int amdgpu_dpm_get_sclk(struct amdgpu_device *adev, bool low) 40 { 41 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 42 int ret = 0; 43 44 if (!pp_funcs->get_sclk) 45 return 0; 46 47 mutex_lock(&adev->pm.mutex); 48 ret = pp_funcs->get_sclk((adev)->powerplay.pp_handle, 49 low); 50 mutex_unlock(&adev->pm.mutex); 51 52 return ret; 53 } 54 55 int amdgpu_dpm_get_mclk(struct amdgpu_device *adev, bool low) 56 { 57 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 58 int ret = 0; 59 60 if (!pp_funcs->get_mclk) 61 return 0; 62 63 mutex_lock(&adev->pm.mutex); 64 ret = pp_funcs->get_mclk((adev)->powerplay.pp_handle, 65 low); 66 mutex_unlock(&adev->pm.mutex); 67 68 return ret; 69 } 70 71 int amdgpu_dpm_set_powergating_by_smu(struct amdgpu_device *adev, uint32_t block_type, bool gate) 72 { 73 int ret = 0; 74 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 75 enum ip_power_state pwr_state = gate ? POWER_STATE_OFF : POWER_STATE_ON; 76 77 if (atomic_read(&adev->pm.pwr_state[block_type]) == pwr_state) { 78 dev_dbg(adev->dev, "IP block%d already in the target %s state!", 79 block_type, gate ? "gate" : "ungate"); 80 return 0; 81 } 82 83 mutex_lock(&adev->pm.mutex); 84 85 switch (block_type) { 86 case AMD_IP_BLOCK_TYPE_UVD: 87 case AMD_IP_BLOCK_TYPE_VCE: 88 case AMD_IP_BLOCK_TYPE_GFX: 89 case AMD_IP_BLOCK_TYPE_VCN: 90 case AMD_IP_BLOCK_TYPE_SDMA: 91 case AMD_IP_BLOCK_TYPE_JPEG: 92 case AMD_IP_BLOCK_TYPE_GMC: 93 case AMD_IP_BLOCK_TYPE_ACP: 94 if (pp_funcs && pp_funcs->set_powergating_by_smu) 95 ret = (pp_funcs->set_powergating_by_smu( 96 (adev)->powerplay.pp_handle, block_type, gate)); 97 break; 98 default: 99 break; 100 } 101 102 if (!ret) 103 atomic_set(&adev->pm.pwr_state[block_type], pwr_state); 104 105 mutex_unlock(&adev->pm.mutex); 106 107 return ret; 108 } 109 110 int amdgpu_dpm_baco_enter(struct amdgpu_device *adev) 111 { 112 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 113 void *pp_handle = adev->powerplay.pp_handle; 114 int ret = 0; 115 116 if (!pp_funcs || !pp_funcs->set_asic_baco_state) 117 return -ENOENT; 118 119 mutex_lock(&adev->pm.mutex); 120 121 /* enter BACO state */ 122 ret = pp_funcs->set_asic_baco_state(pp_handle, 1); 123 124 mutex_unlock(&adev->pm.mutex); 125 126 return ret; 127 } 128 129 int amdgpu_dpm_baco_exit(struct amdgpu_device *adev) 130 { 131 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 132 void *pp_handle = adev->powerplay.pp_handle; 133 int ret = 0; 134 135 if (!pp_funcs || !pp_funcs->set_asic_baco_state) 136 return -ENOENT; 137 138 mutex_lock(&adev->pm.mutex); 139 140 /* exit BACO state */ 141 ret = pp_funcs->set_asic_baco_state(pp_handle, 0); 142 143 mutex_unlock(&adev->pm.mutex); 144 145 return ret; 146 } 147 148 int amdgpu_dpm_set_mp1_state(struct amdgpu_device *adev, 149 enum pp_mp1_state mp1_state) 150 { 151 int ret = 0; 152 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 153 154 if (pp_funcs && pp_funcs->set_mp1_state) { 155 mutex_lock(&adev->pm.mutex); 156 157 ret = pp_funcs->set_mp1_state( 158 adev->powerplay.pp_handle, 159 mp1_state); 160 161 mutex_unlock(&adev->pm.mutex); 162 } 163 164 return ret; 165 } 166 167 bool amdgpu_dpm_is_baco_supported(struct amdgpu_device *adev) 168 { 169 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 170 void *pp_handle = adev->powerplay.pp_handle; 171 bool baco_cap; 172 int ret = 0; 173 174 if (!pp_funcs || !pp_funcs->get_asic_baco_capability) 175 return false; 176 177 mutex_lock(&adev->pm.mutex); 178 179 ret = pp_funcs->get_asic_baco_capability(pp_handle, 180 &baco_cap); 181 182 mutex_unlock(&adev->pm.mutex); 183 184 return ret ? false : baco_cap; 185 } 186 187 int amdgpu_dpm_mode2_reset(struct amdgpu_device *adev) 188 { 189 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 190 void *pp_handle = adev->powerplay.pp_handle; 191 int ret = 0; 192 193 if (!pp_funcs || !pp_funcs->asic_reset_mode_2) 194 return -ENOENT; 195 196 mutex_lock(&adev->pm.mutex); 197 198 ret = pp_funcs->asic_reset_mode_2(pp_handle); 199 200 mutex_unlock(&adev->pm.mutex); 201 202 return ret; 203 } 204 205 int amdgpu_dpm_baco_reset(struct amdgpu_device *adev) 206 { 207 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 208 void *pp_handle = adev->powerplay.pp_handle; 209 int ret = 0; 210 211 if (!pp_funcs || !pp_funcs->set_asic_baco_state) 212 return -ENOENT; 213 214 mutex_lock(&adev->pm.mutex); 215 216 /* enter BACO state */ 217 ret = pp_funcs->set_asic_baco_state(pp_handle, 1); 218 if (ret) 219 goto out; 220 221 /* exit BACO state */ 222 ret = pp_funcs->set_asic_baco_state(pp_handle, 0); 223 224 out: 225 mutex_unlock(&adev->pm.mutex); 226 return ret; 227 } 228 229 bool amdgpu_dpm_is_mode1_reset_supported(struct amdgpu_device *adev) 230 { 231 struct smu_context *smu = adev->powerplay.pp_handle; 232 bool support_mode1_reset = false; 233 234 if (is_support_sw_smu(adev)) { 235 mutex_lock(&adev->pm.mutex); 236 support_mode1_reset = smu_mode1_reset_is_support(smu); 237 mutex_unlock(&adev->pm.mutex); 238 } 239 240 return support_mode1_reset; 241 } 242 243 int amdgpu_dpm_mode1_reset(struct amdgpu_device *adev) 244 { 245 struct smu_context *smu = adev->powerplay.pp_handle; 246 int ret = -EOPNOTSUPP; 247 248 if (is_support_sw_smu(adev)) { 249 mutex_lock(&adev->pm.mutex); 250 ret = smu_mode1_reset(smu); 251 mutex_unlock(&adev->pm.mutex); 252 } 253 254 return ret; 255 } 256 257 int amdgpu_dpm_switch_power_profile(struct amdgpu_device *adev, 258 enum PP_SMC_POWER_PROFILE type, 259 bool en) 260 { 261 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 262 int ret = 0; 263 264 if (amdgpu_sriov_vf(adev)) 265 return 0; 266 267 if (pp_funcs && pp_funcs->switch_power_profile) { 268 mutex_lock(&adev->pm.mutex); 269 ret = pp_funcs->switch_power_profile( 270 adev->powerplay.pp_handle, type, en); 271 mutex_unlock(&adev->pm.mutex); 272 } 273 274 return ret; 275 } 276 277 int amdgpu_dpm_set_xgmi_pstate(struct amdgpu_device *adev, 278 uint32_t pstate) 279 { 280 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 281 int ret = 0; 282 283 if (pp_funcs && pp_funcs->set_xgmi_pstate) { 284 mutex_lock(&adev->pm.mutex); 285 ret = pp_funcs->set_xgmi_pstate(adev->powerplay.pp_handle, 286 pstate); 287 mutex_unlock(&adev->pm.mutex); 288 } 289 290 return ret; 291 } 292 293 int amdgpu_dpm_set_df_cstate(struct amdgpu_device *adev, 294 uint32_t cstate) 295 { 296 int ret = 0; 297 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 298 void *pp_handle = adev->powerplay.pp_handle; 299 300 if (pp_funcs && pp_funcs->set_df_cstate) { 301 mutex_lock(&adev->pm.mutex); 302 ret = pp_funcs->set_df_cstate(pp_handle, cstate); 303 mutex_unlock(&adev->pm.mutex); 304 } 305 306 return ret; 307 } 308 309 int amdgpu_dpm_allow_xgmi_power_down(struct amdgpu_device *adev, bool en) 310 { 311 struct smu_context *smu = adev->powerplay.pp_handle; 312 int ret = 0; 313 314 if (is_support_sw_smu(adev)) { 315 mutex_lock(&adev->pm.mutex); 316 ret = smu_allow_xgmi_power_down(smu, en); 317 mutex_unlock(&adev->pm.mutex); 318 } 319 320 return ret; 321 } 322 323 int amdgpu_dpm_enable_mgpu_fan_boost(struct amdgpu_device *adev) 324 { 325 void *pp_handle = adev->powerplay.pp_handle; 326 const struct amd_pm_funcs *pp_funcs = 327 adev->powerplay.pp_funcs; 328 int ret = 0; 329 330 if (pp_funcs && pp_funcs->enable_mgpu_fan_boost) { 331 mutex_lock(&adev->pm.mutex); 332 ret = pp_funcs->enable_mgpu_fan_boost(pp_handle); 333 mutex_unlock(&adev->pm.mutex); 334 } 335 336 return ret; 337 } 338 339 int amdgpu_dpm_set_clockgating_by_smu(struct amdgpu_device *adev, 340 uint32_t msg_id) 341 { 342 void *pp_handle = adev->powerplay.pp_handle; 343 const struct amd_pm_funcs *pp_funcs = 344 adev->powerplay.pp_funcs; 345 int ret = 0; 346 347 if (pp_funcs && pp_funcs->set_clockgating_by_smu) { 348 mutex_lock(&adev->pm.mutex); 349 ret = pp_funcs->set_clockgating_by_smu(pp_handle, 350 msg_id); 351 mutex_unlock(&adev->pm.mutex); 352 } 353 354 return ret; 355 } 356 357 int amdgpu_dpm_smu_i2c_bus_access(struct amdgpu_device *adev, 358 bool acquire) 359 { 360 void *pp_handle = adev->powerplay.pp_handle; 361 const struct amd_pm_funcs *pp_funcs = 362 adev->powerplay.pp_funcs; 363 int ret = -EOPNOTSUPP; 364 365 if (pp_funcs && pp_funcs->smu_i2c_bus_access) { 366 mutex_lock(&adev->pm.mutex); 367 ret = pp_funcs->smu_i2c_bus_access(pp_handle, 368 acquire); 369 mutex_unlock(&adev->pm.mutex); 370 } 371 372 return ret; 373 } 374 375 void amdgpu_pm_acpi_event_handler(struct amdgpu_device *adev) 376 { 377 if (adev->pm.dpm_enabled) { 378 mutex_lock(&adev->pm.mutex); 379 if (power_supply_is_system_supplied() > 0) 380 adev->pm.ac_power = true; 381 else 382 adev->pm.ac_power = false; 383 384 if (adev->powerplay.pp_funcs && 385 adev->powerplay.pp_funcs->enable_bapm) 386 amdgpu_dpm_enable_bapm(adev, adev->pm.ac_power); 387 388 if (is_support_sw_smu(adev)) 389 smu_set_ac_dc(adev->powerplay.pp_handle); 390 391 mutex_unlock(&adev->pm.mutex); 392 } 393 } 394 395 int amdgpu_dpm_read_sensor(struct amdgpu_device *adev, enum amd_pp_sensors sensor, 396 void *data, uint32_t *size) 397 { 398 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 399 int ret = -EINVAL; 400 401 if (!data || !size) 402 return -EINVAL; 403 404 if (pp_funcs && pp_funcs->read_sensor) { 405 mutex_lock(&adev->pm.mutex); 406 ret = pp_funcs->read_sensor(adev->powerplay.pp_handle, 407 sensor, 408 data, 409 size); 410 mutex_unlock(&adev->pm.mutex); 411 } 412 413 return ret; 414 } 415 416 void amdgpu_dpm_compute_clocks(struct amdgpu_device *adev) 417 { 418 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 419 420 if (!adev->pm.dpm_enabled) 421 return; 422 423 if (!pp_funcs->pm_compute_clocks) 424 return; 425 426 mutex_lock(&adev->pm.mutex); 427 pp_funcs->pm_compute_clocks(adev->powerplay.pp_handle); 428 mutex_unlock(&adev->pm.mutex); 429 } 430 431 void amdgpu_dpm_enable_uvd(struct amdgpu_device *adev, bool enable) 432 { 433 int ret = 0; 434 435 ret = amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_UVD, !enable); 436 if (ret) 437 DRM_ERROR("Dpm %s uvd failed, ret = %d. \n", 438 enable ? "enable" : "disable", ret); 439 } 440 441 void amdgpu_dpm_enable_vce(struct amdgpu_device *adev, bool enable) 442 { 443 int ret = 0; 444 445 ret = amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_VCE, !enable); 446 if (ret) 447 DRM_ERROR("Dpm %s vce failed, ret = %d. \n", 448 enable ? "enable" : "disable", ret); 449 } 450 451 void amdgpu_dpm_enable_jpeg(struct amdgpu_device *adev, bool enable) 452 { 453 int ret = 0; 454 455 ret = amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_JPEG, !enable); 456 if (ret) 457 DRM_ERROR("Dpm %s jpeg failed, ret = %d. \n", 458 enable ? "enable" : "disable", ret); 459 } 460 461 int amdgpu_pm_load_smu_firmware(struct amdgpu_device *adev, uint32_t *smu_version) 462 { 463 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 464 int r = 0; 465 466 if (!pp_funcs || !pp_funcs->load_firmware) 467 return 0; 468 469 mutex_lock(&adev->pm.mutex); 470 r = pp_funcs->load_firmware(adev->powerplay.pp_handle); 471 if (r) { 472 pr_err("smu firmware loading failed\n"); 473 goto out; 474 } 475 476 if (smu_version) 477 *smu_version = adev->pm.fw_version; 478 479 out: 480 mutex_unlock(&adev->pm.mutex); 481 return r; 482 } 483 484 int amdgpu_dpm_handle_passthrough_sbr(struct amdgpu_device *adev, bool enable) 485 { 486 int ret = 0; 487 488 if (is_support_sw_smu(adev)) { 489 mutex_lock(&adev->pm.mutex); 490 ret = smu_handle_passthrough_sbr(adev->powerplay.pp_handle, 491 enable); 492 mutex_unlock(&adev->pm.mutex); 493 } 494 495 return ret; 496 } 497 498 int amdgpu_dpm_send_hbm_bad_pages_num(struct amdgpu_device *adev, uint32_t size) 499 { 500 struct smu_context *smu = adev->powerplay.pp_handle; 501 int ret = 0; 502 503 mutex_lock(&adev->pm.mutex); 504 ret = smu_send_hbm_bad_pages_num(smu, size); 505 mutex_unlock(&adev->pm.mutex); 506 507 return ret; 508 } 509 510 int amdgpu_dpm_send_hbm_bad_channel_flag(struct amdgpu_device *adev, uint32_t size) 511 { 512 struct smu_context *smu = adev->powerplay.pp_handle; 513 int ret = 0; 514 515 mutex_lock(&adev->pm.mutex); 516 ret = smu_send_hbm_bad_channel_flag(smu, size); 517 mutex_unlock(&adev->pm.mutex); 518 519 return ret; 520 } 521 522 int amdgpu_dpm_get_dpm_freq_range(struct amdgpu_device *adev, 523 enum pp_clock_type type, 524 uint32_t *min, 525 uint32_t *max) 526 { 527 int ret = 0; 528 529 if (type != PP_SCLK) 530 return -EINVAL; 531 532 if (!is_support_sw_smu(adev)) 533 return -EOPNOTSUPP; 534 535 mutex_lock(&adev->pm.mutex); 536 ret = smu_get_dpm_freq_range(adev->powerplay.pp_handle, 537 SMU_SCLK, 538 min, 539 max); 540 mutex_unlock(&adev->pm.mutex); 541 542 return ret; 543 } 544 545 int amdgpu_dpm_set_soft_freq_range(struct amdgpu_device *adev, 546 enum pp_clock_type type, 547 uint32_t min, 548 uint32_t max) 549 { 550 struct smu_context *smu = adev->powerplay.pp_handle; 551 int ret = 0; 552 553 if (type != PP_SCLK) 554 return -EINVAL; 555 556 if (!is_support_sw_smu(adev)) 557 return -EOPNOTSUPP; 558 559 mutex_lock(&adev->pm.mutex); 560 ret = smu_set_soft_freq_range(smu, 561 SMU_SCLK, 562 min, 563 max); 564 mutex_unlock(&adev->pm.mutex); 565 566 return ret; 567 } 568 569 int amdgpu_dpm_write_watermarks_table(struct amdgpu_device *adev) 570 { 571 struct smu_context *smu = adev->powerplay.pp_handle; 572 int ret = 0; 573 574 if (!is_support_sw_smu(adev)) 575 return 0; 576 577 mutex_lock(&adev->pm.mutex); 578 ret = smu_write_watermarks_table(smu); 579 mutex_unlock(&adev->pm.mutex); 580 581 return ret; 582 } 583 584 int amdgpu_dpm_wait_for_event(struct amdgpu_device *adev, 585 enum smu_event_type event, 586 uint64_t event_arg) 587 { 588 struct smu_context *smu = adev->powerplay.pp_handle; 589 int ret = 0; 590 591 if (!is_support_sw_smu(adev)) 592 return -EOPNOTSUPP; 593 594 mutex_lock(&adev->pm.mutex); 595 ret = smu_wait_for_event(smu, event, event_arg); 596 mutex_unlock(&adev->pm.mutex); 597 598 return ret; 599 } 600 601 int amdgpu_dpm_get_status_gfxoff(struct amdgpu_device *adev, uint32_t *value) 602 { 603 struct smu_context *smu = adev->powerplay.pp_handle; 604 int ret = 0; 605 606 if (!is_support_sw_smu(adev)) 607 return -EOPNOTSUPP; 608 609 mutex_lock(&adev->pm.mutex); 610 ret = smu_get_status_gfxoff(smu, value); 611 mutex_unlock(&adev->pm.mutex); 612 613 return ret; 614 } 615 616 uint64_t amdgpu_dpm_get_thermal_throttling_counter(struct amdgpu_device *adev) 617 { 618 struct smu_context *smu = adev->powerplay.pp_handle; 619 620 if (!is_support_sw_smu(adev)) 621 return 0; 622 623 return atomic64_read(&smu->throttle_int_counter); 624 } 625 626 /* amdgpu_dpm_gfx_state_change - Handle gfx power state change set 627 * @adev: amdgpu_device pointer 628 * @state: gfx power state(1 -sGpuChangeState_D0Entry and 2 -sGpuChangeState_D3Entry) 629 * 630 */ 631 void amdgpu_dpm_gfx_state_change(struct amdgpu_device *adev, 632 enum gfx_change_state state) 633 { 634 mutex_lock(&adev->pm.mutex); 635 if (adev->powerplay.pp_funcs && 636 adev->powerplay.pp_funcs->gfx_state_change_set) 637 ((adev)->powerplay.pp_funcs->gfx_state_change_set( 638 (adev)->powerplay.pp_handle, state)); 639 mutex_unlock(&adev->pm.mutex); 640 } 641 642 int amdgpu_dpm_get_ecc_info(struct amdgpu_device *adev, 643 void *umc_ecc) 644 { 645 struct smu_context *smu = adev->powerplay.pp_handle; 646 647 if (!is_support_sw_smu(adev)) 648 return -EOPNOTSUPP; 649 650 return smu_get_ecc_info(smu, umc_ecc); 651 } 652 653 struct amd_vce_state *amdgpu_dpm_get_vce_clock_state(struct amdgpu_device *adev, 654 uint32_t idx) 655 { 656 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 657 struct amd_vce_state *vstate = NULL; 658 659 if (!pp_funcs->get_vce_clock_state) 660 return NULL; 661 662 mutex_lock(&adev->pm.mutex); 663 vstate = pp_funcs->get_vce_clock_state(adev->powerplay.pp_handle, 664 idx); 665 mutex_unlock(&adev->pm.mutex); 666 667 return vstate; 668 } 669 670 void amdgpu_dpm_get_current_power_state(struct amdgpu_device *adev, 671 enum amd_pm_state_type *state) 672 { 673 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 674 675 mutex_lock(&adev->pm.mutex); 676 677 if (!pp_funcs->get_current_power_state) { 678 *state = adev->pm.dpm.user_state; 679 goto out; 680 } 681 682 *state = pp_funcs->get_current_power_state(adev->powerplay.pp_handle); 683 if (*state < POWER_STATE_TYPE_DEFAULT || 684 *state > POWER_STATE_TYPE_INTERNAL_3DPERF) 685 *state = adev->pm.dpm.user_state; 686 687 out: 688 mutex_unlock(&adev->pm.mutex); 689 } 690 691 void amdgpu_dpm_set_power_state(struct amdgpu_device *adev, 692 enum amd_pm_state_type state) 693 { 694 mutex_lock(&adev->pm.mutex); 695 adev->pm.dpm.user_state = state; 696 mutex_unlock(&adev->pm.mutex); 697 698 if (is_support_sw_smu(adev)) 699 return; 700 701 if (amdgpu_dpm_dispatch_task(adev, 702 AMD_PP_TASK_ENABLE_USER_STATE, 703 &state) == -EOPNOTSUPP) 704 amdgpu_dpm_compute_clocks(adev); 705 } 706 707 enum amd_dpm_forced_level amdgpu_dpm_get_performance_level(struct amdgpu_device *adev) 708 { 709 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 710 enum amd_dpm_forced_level level; 711 712 mutex_lock(&adev->pm.mutex); 713 if (pp_funcs->get_performance_level) 714 level = pp_funcs->get_performance_level(adev->powerplay.pp_handle); 715 else 716 level = adev->pm.dpm.forced_level; 717 mutex_unlock(&adev->pm.mutex); 718 719 return level; 720 } 721 722 int amdgpu_dpm_force_performance_level(struct amdgpu_device *adev, 723 enum amd_dpm_forced_level level) 724 { 725 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 726 enum amd_dpm_forced_level current_level; 727 uint32_t profile_mode_mask = AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD | 728 AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK | 729 AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK | 730 AMD_DPM_FORCED_LEVEL_PROFILE_PEAK; 731 732 if (!pp_funcs->force_performance_level) 733 return 0; 734 735 if (adev->pm.dpm.thermal_active) 736 return -EINVAL; 737 738 current_level = amdgpu_dpm_get_performance_level(adev); 739 if (current_level == level) 740 return 0; 741 742 if (adev->asic_type == CHIP_RAVEN) { 743 if (!(adev->apu_flags & AMD_APU_IS_RAVEN2)) { 744 if (current_level != AMD_DPM_FORCED_LEVEL_MANUAL && 745 level == AMD_DPM_FORCED_LEVEL_MANUAL) 746 amdgpu_gfx_off_ctrl(adev, false); 747 else if (current_level == AMD_DPM_FORCED_LEVEL_MANUAL && 748 level != AMD_DPM_FORCED_LEVEL_MANUAL) 749 amdgpu_gfx_off_ctrl(adev, true); 750 } 751 } 752 753 if (!(current_level & profile_mode_mask) && 754 (level == AMD_DPM_FORCED_LEVEL_PROFILE_EXIT)) 755 return -EINVAL; 756 757 if (!(current_level & profile_mode_mask) && 758 (level & profile_mode_mask)) { 759 /* enter UMD Pstate */ 760 amdgpu_device_ip_set_powergating_state(adev, 761 AMD_IP_BLOCK_TYPE_GFX, 762 AMD_PG_STATE_UNGATE); 763 amdgpu_device_ip_set_clockgating_state(adev, 764 AMD_IP_BLOCK_TYPE_GFX, 765 AMD_CG_STATE_UNGATE); 766 } else if ((current_level & profile_mode_mask) && 767 !(level & profile_mode_mask)) { 768 /* exit UMD Pstate */ 769 amdgpu_device_ip_set_clockgating_state(adev, 770 AMD_IP_BLOCK_TYPE_GFX, 771 AMD_CG_STATE_GATE); 772 amdgpu_device_ip_set_powergating_state(adev, 773 AMD_IP_BLOCK_TYPE_GFX, 774 AMD_PG_STATE_GATE); 775 } 776 777 mutex_lock(&adev->pm.mutex); 778 779 if (pp_funcs->force_performance_level(adev->powerplay.pp_handle, 780 level)) { 781 mutex_unlock(&adev->pm.mutex); 782 return -EINVAL; 783 } 784 785 adev->pm.dpm.forced_level = level; 786 787 mutex_unlock(&adev->pm.mutex); 788 789 return 0; 790 } 791 792 int amdgpu_dpm_get_pp_num_states(struct amdgpu_device *adev, 793 struct pp_states_info *states) 794 { 795 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 796 int ret = 0; 797 798 if (!pp_funcs->get_pp_num_states) 799 return -EOPNOTSUPP; 800 801 mutex_lock(&adev->pm.mutex); 802 ret = pp_funcs->get_pp_num_states(adev->powerplay.pp_handle, 803 states); 804 mutex_unlock(&adev->pm.mutex); 805 806 return ret; 807 } 808 809 int amdgpu_dpm_dispatch_task(struct amdgpu_device *adev, 810 enum amd_pp_task task_id, 811 enum amd_pm_state_type *user_state) 812 { 813 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 814 int ret = 0; 815 816 if (!pp_funcs->dispatch_tasks) 817 return -EOPNOTSUPP; 818 819 mutex_lock(&adev->pm.mutex); 820 ret = pp_funcs->dispatch_tasks(adev->powerplay.pp_handle, 821 task_id, 822 user_state); 823 mutex_unlock(&adev->pm.mutex); 824 825 return ret; 826 } 827 828 int amdgpu_dpm_get_pp_table(struct amdgpu_device *adev, char **table) 829 { 830 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 831 int ret = 0; 832 833 if (!pp_funcs->get_pp_table) 834 return 0; 835 836 mutex_lock(&adev->pm.mutex); 837 ret = pp_funcs->get_pp_table(adev->powerplay.pp_handle, 838 table); 839 mutex_unlock(&adev->pm.mutex); 840 841 return ret; 842 } 843 844 int amdgpu_dpm_set_fine_grain_clk_vol(struct amdgpu_device *adev, 845 uint32_t type, 846 long *input, 847 uint32_t size) 848 { 849 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 850 int ret = 0; 851 852 if (!pp_funcs->set_fine_grain_clk_vol) 853 return 0; 854 855 mutex_lock(&adev->pm.mutex); 856 ret = pp_funcs->set_fine_grain_clk_vol(adev->powerplay.pp_handle, 857 type, 858 input, 859 size); 860 mutex_unlock(&adev->pm.mutex); 861 862 return ret; 863 } 864 865 int amdgpu_dpm_odn_edit_dpm_table(struct amdgpu_device *adev, 866 uint32_t type, 867 long *input, 868 uint32_t size) 869 { 870 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 871 int ret = 0; 872 873 if (!pp_funcs->odn_edit_dpm_table) 874 return 0; 875 876 mutex_lock(&adev->pm.mutex); 877 ret = pp_funcs->odn_edit_dpm_table(adev->powerplay.pp_handle, 878 type, 879 input, 880 size); 881 mutex_unlock(&adev->pm.mutex); 882 883 return ret; 884 } 885 886 int amdgpu_dpm_print_clock_levels(struct amdgpu_device *adev, 887 enum pp_clock_type type, 888 char *buf) 889 { 890 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 891 int ret = 0; 892 893 if (!pp_funcs->print_clock_levels) 894 return 0; 895 896 mutex_lock(&adev->pm.mutex); 897 ret = pp_funcs->print_clock_levels(adev->powerplay.pp_handle, 898 type, 899 buf); 900 mutex_unlock(&adev->pm.mutex); 901 902 return ret; 903 } 904 905 int amdgpu_dpm_emit_clock_levels(struct amdgpu_device *adev, 906 enum pp_clock_type type, 907 char *buf, 908 int *offset) 909 { 910 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 911 int ret = 0; 912 913 if (!pp_funcs->emit_clock_levels) 914 return -ENOENT; 915 916 mutex_lock(&adev->pm.mutex); 917 ret = pp_funcs->emit_clock_levels(adev->powerplay.pp_handle, 918 type, 919 buf, 920 offset); 921 mutex_unlock(&adev->pm.mutex); 922 923 return ret; 924 } 925 926 int amdgpu_dpm_set_ppfeature_status(struct amdgpu_device *adev, 927 uint64_t ppfeature_masks) 928 { 929 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 930 int ret = 0; 931 932 if (!pp_funcs->set_ppfeature_status) 933 return 0; 934 935 mutex_lock(&adev->pm.mutex); 936 ret = pp_funcs->set_ppfeature_status(adev->powerplay.pp_handle, 937 ppfeature_masks); 938 mutex_unlock(&adev->pm.mutex); 939 940 return ret; 941 } 942 943 int amdgpu_dpm_get_ppfeature_status(struct amdgpu_device *adev, char *buf) 944 { 945 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 946 int ret = 0; 947 948 if (!pp_funcs->get_ppfeature_status) 949 return 0; 950 951 mutex_lock(&adev->pm.mutex); 952 ret = pp_funcs->get_ppfeature_status(adev->powerplay.pp_handle, 953 buf); 954 mutex_unlock(&adev->pm.mutex); 955 956 return ret; 957 } 958 959 int amdgpu_dpm_force_clock_level(struct amdgpu_device *adev, 960 enum pp_clock_type type, 961 uint32_t mask) 962 { 963 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 964 int ret = 0; 965 966 if (!pp_funcs->force_clock_level) 967 return 0; 968 969 mutex_lock(&adev->pm.mutex); 970 ret = pp_funcs->force_clock_level(adev->powerplay.pp_handle, 971 type, 972 mask); 973 mutex_unlock(&adev->pm.mutex); 974 975 return ret; 976 } 977 978 int amdgpu_dpm_get_sclk_od(struct amdgpu_device *adev) 979 { 980 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 981 int ret = 0; 982 983 if (!pp_funcs->get_sclk_od) 984 return 0; 985 986 mutex_lock(&adev->pm.mutex); 987 ret = pp_funcs->get_sclk_od(adev->powerplay.pp_handle); 988 mutex_unlock(&adev->pm.mutex); 989 990 return ret; 991 } 992 993 int amdgpu_dpm_set_sclk_od(struct amdgpu_device *adev, uint32_t value) 994 { 995 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 996 997 if (is_support_sw_smu(adev)) 998 return 0; 999 1000 mutex_lock(&adev->pm.mutex); 1001 if (pp_funcs->set_sclk_od) 1002 pp_funcs->set_sclk_od(adev->powerplay.pp_handle, value); 1003 mutex_unlock(&adev->pm.mutex); 1004 1005 if (amdgpu_dpm_dispatch_task(adev, 1006 AMD_PP_TASK_READJUST_POWER_STATE, 1007 NULL) == -EOPNOTSUPP) { 1008 adev->pm.dpm.current_ps = adev->pm.dpm.boot_ps; 1009 amdgpu_dpm_compute_clocks(adev); 1010 } 1011 1012 return 0; 1013 } 1014 1015 int amdgpu_dpm_get_mclk_od(struct amdgpu_device *adev) 1016 { 1017 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 1018 int ret = 0; 1019 1020 if (!pp_funcs->get_mclk_od) 1021 return 0; 1022 1023 mutex_lock(&adev->pm.mutex); 1024 ret = pp_funcs->get_mclk_od(adev->powerplay.pp_handle); 1025 mutex_unlock(&adev->pm.mutex); 1026 1027 return ret; 1028 } 1029 1030 int amdgpu_dpm_set_mclk_od(struct amdgpu_device *adev, uint32_t value) 1031 { 1032 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 1033 1034 if (is_support_sw_smu(adev)) 1035 return 0; 1036 1037 mutex_lock(&adev->pm.mutex); 1038 if (pp_funcs->set_mclk_od) 1039 pp_funcs->set_mclk_od(adev->powerplay.pp_handle, value); 1040 mutex_unlock(&adev->pm.mutex); 1041 1042 if (amdgpu_dpm_dispatch_task(adev, 1043 AMD_PP_TASK_READJUST_POWER_STATE, 1044 NULL) == -EOPNOTSUPP) { 1045 adev->pm.dpm.current_ps = adev->pm.dpm.boot_ps; 1046 amdgpu_dpm_compute_clocks(adev); 1047 } 1048 1049 return 0; 1050 } 1051 1052 int amdgpu_dpm_get_power_profile_mode(struct amdgpu_device *adev, 1053 char *buf) 1054 { 1055 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 1056 int ret = 0; 1057 1058 if (!pp_funcs->get_power_profile_mode) 1059 return -EOPNOTSUPP; 1060 1061 mutex_lock(&adev->pm.mutex); 1062 ret = pp_funcs->get_power_profile_mode(adev->powerplay.pp_handle, 1063 buf); 1064 mutex_unlock(&adev->pm.mutex); 1065 1066 return ret; 1067 } 1068 1069 int amdgpu_dpm_set_power_profile_mode(struct amdgpu_device *adev, 1070 long *input, uint32_t size) 1071 { 1072 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 1073 int ret = 0; 1074 1075 if (!pp_funcs->set_power_profile_mode) 1076 return 0; 1077 1078 mutex_lock(&adev->pm.mutex); 1079 ret = pp_funcs->set_power_profile_mode(adev->powerplay.pp_handle, 1080 input, 1081 size); 1082 mutex_unlock(&adev->pm.mutex); 1083 1084 return ret; 1085 } 1086 1087 int amdgpu_dpm_get_gpu_metrics(struct amdgpu_device *adev, void **table) 1088 { 1089 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 1090 int ret = 0; 1091 1092 if (!pp_funcs->get_gpu_metrics) 1093 return 0; 1094 1095 mutex_lock(&adev->pm.mutex); 1096 ret = pp_funcs->get_gpu_metrics(adev->powerplay.pp_handle, 1097 table); 1098 mutex_unlock(&adev->pm.mutex); 1099 1100 return ret; 1101 } 1102 1103 int amdgpu_dpm_get_fan_control_mode(struct amdgpu_device *adev, 1104 uint32_t *fan_mode) 1105 { 1106 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 1107 int ret = 0; 1108 1109 if (!pp_funcs->get_fan_control_mode) 1110 return -EOPNOTSUPP; 1111 1112 mutex_lock(&adev->pm.mutex); 1113 ret = pp_funcs->get_fan_control_mode(adev->powerplay.pp_handle, 1114 fan_mode); 1115 mutex_unlock(&adev->pm.mutex); 1116 1117 return ret; 1118 } 1119 1120 int amdgpu_dpm_set_fan_speed_pwm(struct amdgpu_device *adev, 1121 uint32_t speed) 1122 { 1123 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 1124 int ret = 0; 1125 1126 if (!pp_funcs->set_fan_speed_pwm) 1127 return -EOPNOTSUPP; 1128 1129 mutex_lock(&adev->pm.mutex); 1130 ret = pp_funcs->set_fan_speed_pwm(adev->powerplay.pp_handle, 1131 speed); 1132 mutex_unlock(&adev->pm.mutex); 1133 1134 return ret; 1135 } 1136 1137 int amdgpu_dpm_get_fan_speed_pwm(struct amdgpu_device *adev, 1138 uint32_t *speed) 1139 { 1140 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 1141 int ret = 0; 1142 1143 if (!pp_funcs->get_fan_speed_pwm) 1144 return -EOPNOTSUPP; 1145 1146 mutex_lock(&adev->pm.mutex); 1147 ret = pp_funcs->get_fan_speed_pwm(adev->powerplay.pp_handle, 1148 speed); 1149 mutex_unlock(&adev->pm.mutex); 1150 1151 return ret; 1152 } 1153 1154 int amdgpu_dpm_get_fan_speed_rpm(struct amdgpu_device *adev, 1155 uint32_t *speed) 1156 { 1157 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 1158 int ret = 0; 1159 1160 if (!pp_funcs->get_fan_speed_rpm) 1161 return -EOPNOTSUPP; 1162 1163 mutex_lock(&adev->pm.mutex); 1164 ret = pp_funcs->get_fan_speed_rpm(adev->powerplay.pp_handle, 1165 speed); 1166 mutex_unlock(&adev->pm.mutex); 1167 1168 return ret; 1169 } 1170 1171 int amdgpu_dpm_set_fan_speed_rpm(struct amdgpu_device *adev, 1172 uint32_t speed) 1173 { 1174 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 1175 int ret = 0; 1176 1177 if (!pp_funcs->set_fan_speed_rpm) 1178 return -EOPNOTSUPP; 1179 1180 mutex_lock(&adev->pm.mutex); 1181 ret = pp_funcs->set_fan_speed_rpm(adev->powerplay.pp_handle, 1182 speed); 1183 mutex_unlock(&adev->pm.mutex); 1184 1185 return ret; 1186 } 1187 1188 int amdgpu_dpm_set_fan_control_mode(struct amdgpu_device *adev, 1189 uint32_t mode) 1190 { 1191 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 1192 int ret = 0; 1193 1194 if (!pp_funcs->set_fan_control_mode) 1195 return -EOPNOTSUPP; 1196 1197 mutex_lock(&adev->pm.mutex); 1198 ret = pp_funcs->set_fan_control_mode(adev->powerplay.pp_handle, 1199 mode); 1200 mutex_unlock(&adev->pm.mutex); 1201 1202 return ret; 1203 } 1204 1205 int amdgpu_dpm_get_power_limit(struct amdgpu_device *adev, 1206 uint32_t *limit, 1207 enum pp_power_limit_level pp_limit_level, 1208 enum pp_power_type power_type) 1209 { 1210 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 1211 int ret = 0; 1212 1213 if (!pp_funcs->get_power_limit) 1214 return -ENODATA; 1215 1216 mutex_lock(&adev->pm.mutex); 1217 ret = pp_funcs->get_power_limit(adev->powerplay.pp_handle, 1218 limit, 1219 pp_limit_level, 1220 power_type); 1221 mutex_unlock(&adev->pm.mutex); 1222 1223 return ret; 1224 } 1225 1226 int amdgpu_dpm_set_power_limit(struct amdgpu_device *adev, 1227 uint32_t limit) 1228 { 1229 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 1230 int ret = 0; 1231 1232 if (!pp_funcs->set_power_limit) 1233 return -EINVAL; 1234 1235 mutex_lock(&adev->pm.mutex); 1236 ret = pp_funcs->set_power_limit(adev->powerplay.pp_handle, 1237 limit); 1238 mutex_unlock(&adev->pm.mutex); 1239 1240 return ret; 1241 } 1242 1243 int amdgpu_dpm_is_cclk_dpm_supported(struct amdgpu_device *adev) 1244 { 1245 bool cclk_dpm_supported = false; 1246 1247 if (!is_support_sw_smu(adev)) 1248 return false; 1249 1250 mutex_lock(&adev->pm.mutex); 1251 cclk_dpm_supported = is_support_cclk_dpm(adev); 1252 mutex_unlock(&adev->pm.mutex); 1253 1254 return (int)cclk_dpm_supported; 1255 } 1256 1257 int amdgpu_dpm_debugfs_print_current_performance_level(struct amdgpu_device *adev, 1258 struct seq_file *m) 1259 { 1260 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 1261 1262 if (!pp_funcs->debugfs_print_current_performance_level) 1263 return -EOPNOTSUPP; 1264 1265 mutex_lock(&adev->pm.mutex); 1266 pp_funcs->debugfs_print_current_performance_level(adev->powerplay.pp_handle, 1267 m); 1268 mutex_unlock(&adev->pm.mutex); 1269 1270 return 0; 1271 } 1272 1273 int amdgpu_dpm_get_smu_prv_buf_details(struct amdgpu_device *adev, 1274 void **addr, 1275 size_t *size) 1276 { 1277 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 1278 int ret = 0; 1279 1280 if (!pp_funcs->get_smu_prv_buf_details) 1281 return -ENOSYS; 1282 1283 mutex_lock(&adev->pm.mutex); 1284 ret = pp_funcs->get_smu_prv_buf_details(adev->powerplay.pp_handle, 1285 addr, 1286 size); 1287 mutex_unlock(&adev->pm.mutex); 1288 1289 return ret; 1290 } 1291 1292 int amdgpu_dpm_is_overdrive_supported(struct amdgpu_device *adev) 1293 { 1294 struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle; 1295 struct smu_context *smu = adev->powerplay.pp_handle; 1296 1297 if ((is_support_sw_smu(adev) && smu->od_enabled) || 1298 (is_support_sw_smu(adev) && smu->is_apu) || 1299 (!is_support_sw_smu(adev) && hwmgr->od_enabled)) 1300 return true; 1301 1302 return false; 1303 } 1304 1305 int amdgpu_dpm_set_pp_table(struct amdgpu_device *adev, 1306 const char *buf, 1307 size_t size) 1308 { 1309 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 1310 int ret = 0; 1311 1312 if (!pp_funcs->set_pp_table) 1313 return -EOPNOTSUPP; 1314 1315 mutex_lock(&adev->pm.mutex); 1316 ret = pp_funcs->set_pp_table(adev->powerplay.pp_handle, 1317 buf, 1318 size); 1319 mutex_unlock(&adev->pm.mutex); 1320 1321 return ret; 1322 } 1323 1324 int amdgpu_dpm_get_num_cpu_cores(struct amdgpu_device *adev) 1325 { 1326 struct smu_context *smu = adev->powerplay.pp_handle; 1327 1328 if (!is_support_sw_smu(adev)) 1329 return INT_MAX; 1330 1331 return smu->cpu_core_num; 1332 } 1333 1334 void amdgpu_dpm_stb_debug_fs_init(struct amdgpu_device *adev) 1335 { 1336 if (!is_support_sw_smu(adev)) 1337 return; 1338 1339 amdgpu_smu_stb_debug_fs_init(adev); 1340 } 1341 1342 int amdgpu_dpm_display_configuration_change(struct amdgpu_device *adev, 1343 const struct amd_pp_display_configuration *input) 1344 { 1345 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 1346 int ret = 0; 1347 1348 if (!pp_funcs->display_configuration_change) 1349 return 0; 1350 1351 mutex_lock(&adev->pm.mutex); 1352 ret = pp_funcs->display_configuration_change(adev->powerplay.pp_handle, 1353 input); 1354 mutex_unlock(&adev->pm.mutex); 1355 1356 return ret; 1357 } 1358 1359 int amdgpu_dpm_get_clock_by_type(struct amdgpu_device *adev, 1360 enum amd_pp_clock_type type, 1361 struct amd_pp_clocks *clocks) 1362 { 1363 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 1364 int ret = 0; 1365 1366 if (!pp_funcs->get_clock_by_type) 1367 return 0; 1368 1369 mutex_lock(&adev->pm.mutex); 1370 ret = pp_funcs->get_clock_by_type(adev->powerplay.pp_handle, 1371 type, 1372 clocks); 1373 mutex_unlock(&adev->pm.mutex); 1374 1375 return ret; 1376 } 1377 1378 int amdgpu_dpm_get_display_mode_validation_clks(struct amdgpu_device *adev, 1379 struct amd_pp_simple_clock_info *clocks) 1380 { 1381 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 1382 int ret = 0; 1383 1384 if (!pp_funcs->get_display_mode_validation_clocks) 1385 return 0; 1386 1387 mutex_lock(&adev->pm.mutex); 1388 ret = pp_funcs->get_display_mode_validation_clocks(adev->powerplay.pp_handle, 1389 clocks); 1390 mutex_unlock(&adev->pm.mutex); 1391 1392 return ret; 1393 } 1394 1395 int amdgpu_dpm_get_clock_by_type_with_latency(struct amdgpu_device *adev, 1396 enum amd_pp_clock_type type, 1397 struct pp_clock_levels_with_latency *clocks) 1398 { 1399 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 1400 int ret = 0; 1401 1402 if (!pp_funcs->get_clock_by_type_with_latency) 1403 return 0; 1404 1405 mutex_lock(&adev->pm.mutex); 1406 ret = pp_funcs->get_clock_by_type_with_latency(adev->powerplay.pp_handle, 1407 type, 1408 clocks); 1409 mutex_unlock(&adev->pm.mutex); 1410 1411 return ret; 1412 } 1413 1414 int amdgpu_dpm_get_clock_by_type_with_voltage(struct amdgpu_device *adev, 1415 enum amd_pp_clock_type type, 1416 struct pp_clock_levels_with_voltage *clocks) 1417 { 1418 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 1419 int ret = 0; 1420 1421 if (!pp_funcs->get_clock_by_type_with_voltage) 1422 return 0; 1423 1424 mutex_lock(&adev->pm.mutex); 1425 ret = pp_funcs->get_clock_by_type_with_voltage(adev->powerplay.pp_handle, 1426 type, 1427 clocks); 1428 mutex_unlock(&adev->pm.mutex); 1429 1430 return ret; 1431 } 1432 1433 int amdgpu_dpm_set_watermarks_for_clocks_ranges(struct amdgpu_device *adev, 1434 void *clock_ranges) 1435 { 1436 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 1437 int ret = 0; 1438 1439 if (!pp_funcs->set_watermarks_for_clocks_ranges) 1440 return -EOPNOTSUPP; 1441 1442 mutex_lock(&adev->pm.mutex); 1443 ret = pp_funcs->set_watermarks_for_clocks_ranges(adev->powerplay.pp_handle, 1444 clock_ranges); 1445 mutex_unlock(&adev->pm.mutex); 1446 1447 return ret; 1448 } 1449 1450 int amdgpu_dpm_display_clock_voltage_request(struct amdgpu_device *adev, 1451 struct pp_display_clock_request *clock) 1452 { 1453 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 1454 int ret = 0; 1455 1456 if (!pp_funcs->display_clock_voltage_request) 1457 return -EOPNOTSUPP; 1458 1459 mutex_lock(&adev->pm.mutex); 1460 ret = pp_funcs->display_clock_voltage_request(adev->powerplay.pp_handle, 1461 clock); 1462 mutex_unlock(&adev->pm.mutex); 1463 1464 return ret; 1465 } 1466 1467 int amdgpu_dpm_get_current_clocks(struct amdgpu_device *adev, 1468 struct amd_pp_clock_info *clocks) 1469 { 1470 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 1471 int ret = 0; 1472 1473 if (!pp_funcs->get_current_clocks) 1474 return -EOPNOTSUPP; 1475 1476 mutex_lock(&adev->pm.mutex); 1477 ret = pp_funcs->get_current_clocks(adev->powerplay.pp_handle, 1478 clocks); 1479 mutex_unlock(&adev->pm.mutex); 1480 1481 return ret; 1482 } 1483 1484 void amdgpu_dpm_notify_smu_enable_pwe(struct amdgpu_device *adev) 1485 { 1486 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 1487 1488 if (!pp_funcs->notify_smu_enable_pwe) 1489 return; 1490 1491 mutex_lock(&adev->pm.mutex); 1492 pp_funcs->notify_smu_enable_pwe(adev->powerplay.pp_handle); 1493 mutex_unlock(&adev->pm.mutex); 1494 } 1495 1496 int amdgpu_dpm_set_active_display_count(struct amdgpu_device *adev, 1497 uint32_t count) 1498 { 1499 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 1500 int ret = 0; 1501 1502 if (!pp_funcs->set_active_display_count) 1503 return -EOPNOTSUPP; 1504 1505 mutex_lock(&adev->pm.mutex); 1506 ret = pp_funcs->set_active_display_count(adev->powerplay.pp_handle, 1507 count); 1508 mutex_unlock(&adev->pm.mutex); 1509 1510 return ret; 1511 } 1512 1513 int amdgpu_dpm_set_min_deep_sleep_dcefclk(struct amdgpu_device *adev, 1514 uint32_t clock) 1515 { 1516 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 1517 int ret = 0; 1518 1519 if (!pp_funcs->set_min_deep_sleep_dcefclk) 1520 return -EOPNOTSUPP; 1521 1522 mutex_lock(&adev->pm.mutex); 1523 ret = pp_funcs->set_min_deep_sleep_dcefclk(adev->powerplay.pp_handle, 1524 clock); 1525 mutex_unlock(&adev->pm.mutex); 1526 1527 return ret; 1528 } 1529 1530 void amdgpu_dpm_set_hard_min_dcefclk_by_freq(struct amdgpu_device *adev, 1531 uint32_t clock) 1532 { 1533 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 1534 1535 if (!pp_funcs->set_hard_min_dcefclk_by_freq) 1536 return; 1537 1538 mutex_lock(&adev->pm.mutex); 1539 pp_funcs->set_hard_min_dcefclk_by_freq(adev->powerplay.pp_handle, 1540 clock); 1541 mutex_unlock(&adev->pm.mutex); 1542 } 1543 1544 void amdgpu_dpm_set_hard_min_fclk_by_freq(struct amdgpu_device *adev, 1545 uint32_t clock) 1546 { 1547 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 1548 1549 if (!pp_funcs->set_hard_min_fclk_by_freq) 1550 return; 1551 1552 mutex_lock(&adev->pm.mutex); 1553 pp_funcs->set_hard_min_fclk_by_freq(adev->powerplay.pp_handle, 1554 clock); 1555 mutex_unlock(&adev->pm.mutex); 1556 } 1557 1558 int amdgpu_dpm_display_disable_memory_clock_switch(struct amdgpu_device *adev, 1559 bool disable_memory_clock_switch) 1560 { 1561 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 1562 int ret = 0; 1563 1564 if (!pp_funcs->display_disable_memory_clock_switch) 1565 return 0; 1566 1567 mutex_lock(&adev->pm.mutex); 1568 ret = pp_funcs->display_disable_memory_clock_switch(adev->powerplay.pp_handle, 1569 disable_memory_clock_switch); 1570 mutex_unlock(&adev->pm.mutex); 1571 1572 return ret; 1573 } 1574 1575 int amdgpu_dpm_get_max_sustainable_clocks_by_dc(struct amdgpu_device *adev, 1576 struct pp_smu_nv_clock_table *max_clocks) 1577 { 1578 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 1579 int ret = 0; 1580 1581 if (!pp_funcs->get_max_sustainable_clocks_by_dc) 1582 return -EOPNOTSUPP; 1583 1584 mutex_lock(&adev->pm.mutex); 1585 ret = pp_funcs->get_max_sustainable_clocks_by_dc(adev->powerplay.pp_handle, 1586 max_clocks); 1587 mutex_unlock(&adev->pm.mutex); 1588 1589 return ret; 1590 } 1591 1592 enum pp_smu_status amdgpu_dpm_get_uclk_dpm_states(struct amdgpu_device *adev, 1593 unsigned int *clock_values_in_khz, 1594 unsigned int *num_states) 1595 { 1596 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 1597 int ret = 0; 1598 1599 if (!pp_funcs->get_uclk_dpm_states) 1600 return -EOPNOTSUPP; 1601 1602 mutex_lock(&adev->pm.mutex); 1603 ret = pp_funcs->get_uclk_dpm_states(adev->powerplay.pp_handle, 1604 clock_values_in_khz, 1605 num_states); 1606 mutex_unlock(&adev->pm.mutex); 1607 1608 return ret; 1609 } 1610 1611 int amdgpu_dpm_get_dpm_clock_table(struct amdgpu_device *adev, 1612 struct dpm_clocks *clock_table) 1613 { 1614 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 1615 int ret = 0; 1616 1617 if (!pp_funcs->get_dpm_clock_table) 1618 return -EOPNOTSUPP; 1619 1620 mutex_lock(&adev->pm.mutex); 1621 ret = pp_funcs->get_dpm_clock_table(adev->powerplay.pp_handle, 1622 clock_table); 1623 mutex_unlock(&adev->pm.mutex); 1624 1625 return ret; 1626 } 1627