1 /* 2 * Copyright 2011 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Alex Deucher 23 */ 24 25 #include "amdgpu.h" 26 #include "amdgpu_atombios.h" 27 #include "amdgpu_i2c.h" 28 #include "amdgpu_dpm.h" 29 #include "atom.h" 30 #include "amd_pcie.h" 31 #include "amdgpu_display.h" 32 #include "hwmgr.h" 33 #include <linux/power_supply.h> 34 #include "amdgpu_smu.h" 35 36 #define amdgpu_dpm_enable_bapm(adev, e) \ 37 ((adev)->powerplay.pp_funcs->enable_bapm((adev)->powerplay.pp_handle, (e))) 38 39 int amdgpu_dpm_get_sclk(struct amdgpu_device *adev, bool low) 40 { 41 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 42 int ret = 0; 43 44 if (!pp_funcs->get_sclk) 45 return 0; 46 47 mutex_lock(&adev->pm.mutex); 48 ret = pp_funcs->get_sclk((adev)->powerplay.pp_handle, 49 low); 50 mutex_unlock(&adev->pm.mutex); 51 52 return ret; 53 } 54 55 int amdgpu_dpm_get_mclk(struct amdgpu_device *adev, bool low) 56 { 57 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 58 int ret = 0; 59 60 if (!pp_funcs->get_mclk) 61 return 0; 62 63 mutex_lock(&adev->pm.mutex); 64 ret = pp_funcs->get_mclk((adev)->powerplay.pp_handle, 65 low); 66 mutex_unlock(&adev->pm.mutex); 67 68 return ret; 69 } 70 71 int amdgpu_dpm_set_powergating_by_smu(struct amdgpu_device *adev, uint32_t block_type, bool gate) 72 { 73 int ret = 0; 74 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 75 enum ip_power_state pwr_state = gate ? POWER_STATE_OFF : POWER_STATE_ON; 76 77 if (atomic_read(&adev->pm.pwr_state[block_type]) == pwr_state) { 78 dev_dbg(adev->dev, "IP block%d already in the target %s state!", 79 block_type, gate ? "gate" : "ungate"); 80 return 0; 81 } 82 83 mutex_lock(&adev->pm.mutex); 84 85 switch (block_type) { 86 case AMD_IP_BLOCK_TYPE_UVD: 87 case AMD_IP_BLOCK_TYPE_VCE: 88 case AMD_IP_BLOCK_TYPE_GFX: 89 case AMD_IP_BLOCK_TYPE_VCN: 90 case AMD_IP_BLOCK_TYPE_SDMA: 91 case AMD_IP_BLOCK_TYPE_JPEG: 92 case AMD_IP_BLOCK_TYPE_GMC: 93 case AMD_IP_BLOCK_TYPE_ACP: 94 if (pp_funcs && pp_funcs->set_powergating_by_smu) 95 ret = (pp_funcs->set_powergating_by_smu( 96 (adev)->powerplay.pp_handle, block_type, gate)); 97 break; 98 default: 99 break; 100 } 101 102 if (!ret) 103 atomic_set(&adev->pm.pwr_state[block_type], pwr_state); 104 105 mutex_unlock(&adev->pm.mutex); 106 107 return ret; 108 } 109 110 int amdgpu_dpm_baco_enter(struct amdgpu_device *adev) 111 { 112 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 113 void *pp_handle = adev->powerplay.pp_handle; 114 int ret = 0; 115 116 if (!pp_funcs || !pp_funcs->set_asic_baco_state) 117 return -ENOENT; 118 119 mutex_lock(&adev->pm.mutex); 120 121 /* enter BACO state */ 122 ret = pp_funcs->set_asic_baco_state(pp_handle, 1); 123 124 mutex_unlock(&adev->pm.mutex); 125 126 return ret; 127 } 128 129 int amdgpu_dpm_baco_exit(struct amdgpu_device *adev) 130 { 131 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 132 void *pp_handle = adev->powerplay.pp_handle; 133 int ret = 0; 134 135 if (!pp_funcs || !pp_funcs->set_asic_baco_state) 136 return -ENOENT; 137 138 mutex_lock(&adev->pm.mutex); 139 140 /* exit BACO state */ 141 ret = pp_funcs->set_asic_baco_state(pp_handle, 0); 142 143 mutex_unlock(&adev->pm.mutex); 144 145 return ret; 146 } 147 148 int amdgpu_dpm_set_mp1_state(struct amdgpu_device *adev, 149 enum pp_mp1_state mp1_state) 150 { 151 int ret = 0; 152 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 153 154 if (pp_funcs && pp_funcs->set_mp1_state) { 155 mutex_lock(&adev->pm.mutex); 156 157 ret = pp_funcs->set_mp1_state( 158 adev->powerplay.pp_handle, 159 mp1_state); 160 161 mutex_unlock(&adev->pm.mutex); 162 } 163 164 return ret; 165 } 166 167 bool amdgpu_dpm_is_baco_supported(struct amdgpu_device *adev) 168 { 169 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 170 void *pp_handle = adev->powerplay.pp_handle; 171 bool baco_cap; 172 int ret = 0; 173 174 if (!pp_funcs || !pp_funcs->get_asic_baco_capability) 175 return false; 176 177 mutex_lock(&adev->pm.mutex); 178 179 ret = pp_funcs->get_asic_baco_capability(pp_handle, 180 &baco_cap); 181 182 mutex_unlock(&adev->pm.mutex); 183 184 return ret ? false : baco_cap; 185 } 186 187 int amdgpu_dpm_mode2_reset(struct amdgpu_device *adev) 188 { 189 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 190 void *pp_handle = adev->powerplay.pp_handle; 191 int ret = 0; 192 193 if (!pp_funcs || !pp_funcs->asic_reset_mode_2) 194 return -ENOENT; 195 196 mutex_lock(&adev->pm.mutex); 197 198 ret = pp_funcs->asic_reset_mode_2(pp_handle); 199 200 mutex_unlock(&adev->pm.mutex); 201 202 return ret; 203 } 204 205 int amdgpu_dpm_baco_reset(struct amdgpu_device *adev) 206 { 207 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 208 void *pp_handle = adev->powerplay.pp_handle; 209 int ret = 0; 210 211 if (!pp_funcs || !pp_funcs->set_asic_baco_state) 212 return -ENOENT; 213 214 mutex_lock(&adev->pm.mutex); 215 216 /* enter BACO state */ 217 ret = pp_funcs->set_asic_baco_state(pp_handle, 1); 218 if (ret) 219 goto out; 220 221 /* exit BACO state */ 222 ret = pp_funcs->set_asic_baco_state(pp_handle, 0); 223 224 out: 225 mutex_unlock(&adev->pm.mutex); 226 return ret; 227 } 228 229 bool amdgpu_dpm_is_mode1_reset_supported(struct amdgpu_device *adev) 230 { 231 struct smu_context *smu = adev->powerplay.pp_handle; 232 bool support_mode1_reset = false; 233 234 if (is_support_sw_smu(adev)) { 235 mutex_lock(&adev->pm.mutex); 236 support_mode1_reset = smu_mode1_reset_is_support(smu); 237 mutex_unlock(&adev->pm.mutex); 238 } 239 240 return support_mode1_reset; 241 } 242 243 int amdgpu_dpm_mode1_reset(struct amdgpu_device *adev) 244 { 245 struct smu_context *smu = adev->powerplay.pp_handle; 246 int ret = -EOPNOTSUPP; 247 248 if (is_support_sw_smu(adev)) { 249 mutex_lock(&adev->pm.mutex); 250 ret = smu_mode1_reset(smu); 251 mutex_unlock(&adev->pm.mutex); 252 } 253 254 return ret; 255 } 256 257 int amdgpu_dpm_switch_power_profile(struct amdgpu_device *adev, 258 enum PP_SMC_POWER_PROFILE type, 259 bool en) 260 { 261 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 262 int ret = 0; 263 264 if (amdgpu_sriov_vf(adev)) 265 return 0; 266 267 if (pp_funcs && pp_funcs->switch_power_profile) { 268 mutex_lock(&adev->pm.mutex); 269 ret = pp_funcs->switch_power_profile( 270 adev->powerplay.pp_handle, type, en); 271 mutex_unlock(&adev->pm.mutex); 272 } 273 274 return ret; 275 } 276 277 int amdgpu_dpm_set_xgmi_pstate(struct amdgpu_device *adev, 278 uint32_t pstate) 279 { 280 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 281 int ret = 0; 282 283 if (pp_funcs && pp_funcs->set_xgmi_pstate) { 284 mutex_lock(&adev->pm.mutex); 285 ret = pp_funcs->set_xgmi_pstate(adev->powerplay.pp_handle, 286 pstate); 287 mutex_unlock(&adev->pm.mutex); 288 } 289 290 return ret; 291 } 292 293 int amdgpu_dpm_set_df_cstate(struct amdgpu_device *adev, 294 uint32_t cstate) 295 { 296 int ret = 0; 297 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 298 void *pp_handle = adev->powerplay.pp_handle; 299 300 if (pp_funcs && pp_funcs->set_df_cstate) { 301 mutex_lock(&adev->pm.mutex); 302 ret = pp_funcs->set_df_cstate(pp_handle, cstate); 303 mutex_unlock(&adev->pm.mutex); 304 } 305 306 return ret; 307 } 308 309 int amdgpu_dpm_allow_xgmi_power_down(struct amdgpu_device *adev, bool en) 310 { 311 struct smu_context *smu = adev->powerplay.pp_handle; 312 int ret = 0; 313 314 if (is_support_sw_smu(adev)) { 315 mutex_lock(&adev->pm.mutex); 316 ret = smu_allow_xgmi_power_down(smu, en); 317 mutex_unlock(&adev->pm.mutex); 318 } 319 320 return ret; 321 } 322 323 int amdgpu_dpm_enable_mgpu_fan_boost(struct amdgpu_device *adev) 324 { 325 void *pp_handle = adev->powerplay.pp_handle; 326 const struct amd_pm_funcs *pp_funcs = 327 adev->powerplay.pp_funcs; 328 int ret = 0; 329 330 if (pp_funcs && pp_funcs->enable_mgpu_fan_boost) { 331 mutex_lock(&adev->pm.mutex); 332 ret = pp_funcs->enable_mgpu_fan_boost(pp_handle); 333 mutex_unlock(&adev->pm.mutex); 334 } 335 336 return ret; 337 } 338 339 int amdgpu_dpm_set_clockgating_by_smu(struct amdgpu_device *adev, 340 uint32_t msg_id) 341 { 342 void *pp_handle = adev->powerplay.pp_handle; 343 const struct amd_pm_funcs *pp_funcs = 344 adev->powerplay.pp_funcs; 345 int ret = 0; 346 347 if (pp_funcs && pp_funcs->set_clockgating_by_smu) { 348 mutex_lock(&adev->pm.mutex); 349 ret = pp_funcs->set_clockgating_by_smu(pp_handle, 350 msg_id); 351 mutex_unlock(&adev->pm.mutex); 352 } 353 354 return ret; 355 } 356 357 int amdgpu_dpm_smu_i2c_bus_access(struct amdgpu_device *adev, 358 bool acquire) 359 { 360 void *pp_handle = adev->powerplay.pp_handle; 361 const struct amd_pm_funcs *pp_funcs = 362 adev->powerplay.pp_funcs; 363 int ret = -EOPNOTSUPP; 364 365 if (pp_funcs && pp_funcs->smu_i2c_bus_access) { 366 mutex_lock(&adev->pm.mutex); 367 ret = pp_funcs->smu_i2c_bus_access(pp_handle, 368 acquire); 369 mutex_unlock(&adev->pm.mutex); 370 } 371 372 return ret; 373 } 374 375 void amdgpu_pm_acpi_event_handler(struct amdgpu_device *adev) 376 { 377 if (adev->pm.dpm_enabled) { 378 mutex_lock(&adev->pm.mutex); 379 if (power_supply_is_system_supplied() > 0) 380 adev->pm.ac_power = true; 381 else 382 adev->pm.ac_power = false; 383 384 if (adev->powerplay.pp_funcs && 385 adev->powerplay.pp_funcs->enable_bapm) 386 amdgpu_dpm_enable_bapm(adev, adev->pm.ac_power); 387 388 if (is_support_sw_smu(adev)) 389 smu_set_ac_dc(adev->powerplay.pp_handle); 390 391 mutex_unlock(&adev->pm.mutex); 392 } 393 } 394 395 int amdgpu_dpm_read_sensor(struct amdgpu_device *adev, enum amd_pp_sensors sensor, 396 void *data, uint32_t *size) 397 { 398 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 399 int ret = -EINVAL; 400 401 if (!data || !size) 402 return -EINVAL; 403 404 if (pp_funcs && pp_funcs->read_sensor) { 405 mutex_lock(&adev->pm.mutex); 406 ret = pp_funcs->read_sensor(adev->powerplay.pp_handle, 407 sensor, 408 data, 409 size); 410 mutex_unlock(&adev->pm.mutex); 411 } 412 413 return ret; 414 } 415 416 void amdgpu_dpm_compute_clocks(struct amdgpu_device *adev) 417 { 418 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 419 420 if (!adev->pm.dpm_enabled) 421 return; 422 423 if (!pp_funcs->pm_compute_clocks) 424 return; 425 426 mutex_lock(&adev->pm.mutex); 427 pp_funcs->pm_compute_clocks(adev->powerplay.pp_handle); 428 mutex_unlock(&adev->pm.mutex); 429 } 430 431 void amdgpu_dpm_enable_uvd(struct amdgpu_device *adev, bool enable) 432 { 433 int ret = 0; 434 435 ret = amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_UVD, !enable); 436 if (ret) 437 DRM_ERROR("Dpm %s uvd failed, ret = %d. \n", 438 enable ? "enable" : "disable", ret); 439 } 440 441 void amdgpu_dpm_enable_vce(struct amdgpu_device *adev, bool enable) 442 { 443 int ret = 0; 444 445 ret = amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_VCE, !enable); 446 if (ret) 447 DRM_ERROR("Dpm %s vce failed, ret = %d. \n", 448 enable ? "enable" : "disable", ret); 449 } 450 451 void amdgpu_dpm_enable_jpeg(struct amdgpu_device *adev, bool enable) 452 { 453 int ret = 0; 454 455 ret = amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_JPEG, !enable); 456 if (ret) 457 DRM_ERROR("Dpm %s jpeg failed, ret = %d. \n", 458 enable ? "enable" : "disable", ret); 459 } 460 461 int amdgpu_pm_load_smu_firmware(struct amdgpu_device *adev, uint32_t *smu_version) 462 { 463 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 464 int r = 0; 465 466 if (!pp_funcs || !pp_funcs->load_firmware) 467 return 0; 468 469 mutex_lock(&adev->pm.mutex); 470 r = pp_funcs->load_firmware(adev->powerplay.pp_handle); 471 if (r) { 472 pr_err("smu firmware loading failed\n"); 473 goto out; 474 } 475 476 if (smu_version) 477 *smu_version = adev->pm.fw_version; 478 479 out: 480 mutex_unlock(&adev->pm.mutex); 481 return r; 482 } 483 484 int amdgpu_dpm_handle_passthrough_sbr(struct amdgpu_device *adev, bool enable) 485 { 486 int ret = 0; 487 488 if (is_support_sw_smu(adev)) { 489 mutex_lock(&adev->pm.mutex); 490 ret = smu_handle_passthrough_sbr(adev->powerplay.pp_handle, 491 enable); 492 mutex_unlock(&adev->pm.mutex); 493 } 494 495 return ret; 496 } 497 498 int amdgpu_dpm_send_hbm_bad_pages_num(struct amdgpu_device *adev, uint32_t size) 499 { 500 struct smu_context *smu = adev->powerplay.pp_handle; 501 int ret = 0; 502 503 mutex_lock(&adev->pm.mutex); 504 ret = smu_send_hbm_bad_pages_num(smu, size); 505 mutex_unlock(&adev->pm.mutex); 506 507 return ret; 508 } 509 510 int amdgpu_dpm_get_dpm_freq_range(struct amdgpu_device *adev, 511 enum pp_clock_type type, 512 uint32_t *min, 513 uint32_t *max) 514 { 515 int ret = 0; 516 517 if (type != PP_SCLK) 518 return -EINVAL; 519 520 if (!is_support_sw_smu(adev)) 521 return -EOPNOTSUPP; 522 523 mutex_lock(&adev->pm.mutex); 524 ret = smu_get_dpm_freq_range(adev->powerplay.pp_handle, 525 SMU_SCLK, 526 min, 527 max); 528 mutex_unlock(&adev->pm.mutex); 529 530 return ret; 531 } 532 533 int amdgpu_dpm_set_soft_freq_range(struct amdgpu_device *adev, 534 enum pp_clock_type type, 535 uint32_t min, 536 uint32_t max) 537 { 538 struct smu_context *smu = adev->powerplay.pp_handle; 539 int ret = 0; 540 541 if (type != PP_SCLK) 542 return -EINVAL; 543 544 if (!is_support_sw_smu(adev)) 545 return -EOPNOTSUPP; 546 547 mutex_lock(&adev->pm.mutex); 548 ret = smu_set_soft_freq_range(smu, 549 SMU_SCLK, 550 min, 551 max); 552 mutex_unlock(&adev->pm.mutex); 553 554 return ret; 555 } 556 557 int amdgpu_dpm_write_watermarks_table(struct amdgpu_device *adev) 558 { 559 struct smu_context *smu = adev->powerplay.pp_handle; 560 int ret = 0; 561 562 if (!is_support_sw_smu(adev)) 563 return 0; 564 565 mutex_lock(&adev->pm.mutex); 566 ret = smu_write_watermarks_table(smu); 567 mutex_unlock(&adev->pm.mutex); 568 569 return ret; 570 } 571 572 int amdgpu_dpm_wait_for_event(struct amdgpu_device *adev, 573 enum smu_event_type event, 574 uint64_t event_arg) 575 { 576 struct smu_context *smu = adev->powerplay.pp_handle; 577 int ret = 0; 578 579 if (!is_support_sw_smu(adev)) 580 return -EOPNOTSUPP; 581 582 mutex_lock(&adev->pm.mutex); 583 ret = smu_wait_for_event(smu, event, event_arg); 584 mutex_unlock(&adev->pm.mutex); 585 586 return ret; 587 } 588 589 int amdgpu_dpm_get_status_gfxoff(struct amdgpu_device *adev, uint32_t *value) 590 { 591 struct smu_context *smu = adev->powerplay.pp_handle; 592 int ret = 0; 593 594 if (!is_support_sw_smu(adev)) 595 return -EOPNOTSUPP; 596 597 mutex_lock(&adev->pm.mutex); 598 ret = smu_get_status_gfxoff(smu, value); 599 mutex_unlock(&adev->pm.mutex); 600 601 return ret; 602 } 603 604 uint64_t amdgpu_dpm_get_thermal_throttling_counter(struct amdgpu_device *adev) 605 { 606 struct smu_context *smu = adev->powerplay.pp_handle; 607 608 if (!is_support_sw_smu(adev)) 609 return 0; 610 611 return atomic64_read(&smu->throttle_int_counter); 612 } 613 614 /* amdgpu_dpm_gfx_state_change - Handle gfx power state change set 615 * @adev: amdgpu_device pointer 616 * @state: gfx power state(1 -sGpuChangeState_D0Entry and 2 -sGpuChangeState_D3Entry) 617 * 618 */ 619 void amdgpu_dpm_gfx_state_change(struct amdgpu_device *adev, 620 enum gfx_change_state state) 621 { 622 mutex_lock(&adev->pm.mutex); 623 if (adev->powerplay.pp_funcs && 624 adev->powerplay.pp_funcs->gfx_state_change_set) 625 ((adev)->powerplay.pp_funcs->gfx_state_change_set( 626 (adev)->powerplay.pp_handle, state)); 627 mutex_unlock(&adev->pm.mutex); 628 } 629 630 int amdgpu_dpm_get_ecc_info(struct amdgpu_device *adev, 631 void *umc_ecc) 632 { 633 struct smu_context *smu = adev->powerplay.pp_handle; 634 635 if (!is_support_sw_smu(adev)) 636 return -EOPNOTSUPP; 637 638 return smu_get_ecc_info(smu, umc_ecc); 639 } 640 641 struct amd_vce_state *amdgpu_dpm_get_vce_clock_state(struct amdgpu_device *adev, 642 uint32_t idx) 643 { 644 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 645 struct amd_vce_state *vstate = NULL; 646 647 if (!pp_funcs->get_vce_clock_state) 648 return NULL; 649 650 mutex_lock(&adev->pm.mutex); 651 vstate = pp_funcs->get_vce_clock_state(adev->powerplay.pp_handle, 652 idx); 653 mutex_unlock(&adev->pm.mutex); 654 655 return vstate; 656 } 657 658 void amdgpu_dpm_get_current_power_state(struct amdgpu_device *adev, 659 enum amd_pm_state_type *state) 660 { 661 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 662 663 mutex_lock(&adev->pm.mutex); 664 665 if (!pp_funcs->get_current_power_state) { 666 *state = adev->pm.dpm.user_state; 667 goto out; 668 } 669 670 *state = pp_funcs->get_current_power_state(adev->powerplay.pp_handle); 671 if (*state < POWER_STATE_TYPE_DEFAULT || 672 *state > POWER_STATE_TYPE_INTERNAL_3DPERF) 673 *state = adev->pm.dpm.user_state; 674 675 out: 676 mutex_unlock(&adev->pm.mutex); 677 } 678 679 void amdgpu_dpm_set_power_state(struct amdgpu_device *adev, 680 enum amd_pm_state_type state) 681 { 682 mutex_lock(&adev->pm.mutex); 683 adev->pm.dpm.user_state = state; 684 mutex_unlock(&adev->pm.mutex); 685 686 if (is_support_sw_smu(adev)) 687 return; 688 689 if (amdgpu_dpm_dispatch_task(adev, 690 AMD_PP_TASK_ENABLE_USER_STATE, 691 &state) == -EOPNOTSUPP) 692 amdgpu_dpm_compute_clocks(adev); 693 } 694 695 enum amd_dpm_forced_level amdgpu_dpm_get_performance_level(struct amdgpu_device *adev) 696 { 697 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 698 enum amd_dpm_forced_level level; 699 700 mutex_lock(&adev->pm.mutex); 701 if (pp_funcs->get_performance_level) 702 level = pp_funcs->get_performance_level(adev->powerplay.pp_handle); 703 else 704 level = adev->pm.dpm.forced_level; 705 mutex_unlock(&adev->pm.mutex); 706 707 return level; 708 } 709 710 int amdgpu_dpm_force_performance_level(struct amdgpu_device *adev, 711 enum amd_dpm_forced_level level) 712 { 713 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 714 enum amd_dpm_forced_level current_level; 715 uint32_t profile_mode_mask = AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD | 716 AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK | 717 AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK | 718 AMD_DPM_FORCED_LEVEL_PROFILE_PEAK; 719 720 if (!pp_funcs->force_performance_level) 721 return 0; 722 723 if (adev->pm.dpm.thermal_active) 724 return -EINVAL; 725 726 current_level = amdgpu_dpm_get_performance_level(adev); 727 if (current_level == level) 728 return 0; 729 730 if (adev->asic_type == CHIP_RAVEN) { 731 if (!(adev->apu_flags & AMD_APU_IS_RAVEN2)) { 732 if (current_level != AMD_DPM_FORCED_LEVEL_MANUAL && 733 level == AMD_DPM_FORCED_LEVEL_MANUAL) 734 amdgpu_gfx_off_ctrl(adev, false); 735 else if (current_level == AMD_DPM_FORCED_LEVEL_MANUAL && 736 level != AMD_DPM_FORCED_LEVEL_MANUAL) 737 amdgpu_gfx_off_ctrl(adev, true); 738 } 739 } 740 741 if (!(current_level & profile_mode_mask) && 742 (level == AMD_DPM_FORCED_LEVEL_PROFILE_EXIT)) 743 return -EINVAL; 744 745 if (!(current_level & profile_mode_mask) && 746 (level & profile_mode_mask)) { 747 /* enter UMD Pstate */ 748 amdgpu_device_ip_set_powergating_state(adev, 749 AMD_IP_BLOCK_TYPE_GFX, 750 AMD_PG_STATE_UNGATE); 751 amdgpu_device_ip_set_clockgating_state(adev, 752 AMD_IP_BLOCK_TYPE_GFX, 753 AMD_CG_STATE_UNGATE); 754 } else if ((current_level & profile_mode_mask) && 755 !(level & profile_mode_mask)) { 756 /* exit UMD Pstate */ 757 amdgpu_device_ip_set_clockgating_state(adev, 758 AMD_IP_BLOCK_TYPE_GFX, 759 AMD_CG_STATE_GATE); 760 amdgpu_device_ip_set_powergating_state(adev, 761 AMD_IP_BLOCK_TYPE_GFX, 762 AMD_PG_STATE_GATE); 763 } 764 765 mutex_lock(&adev->pm.mutex); 766 767 if (pp_funcs->force_performance_level(adev->powerplay.pp_handle, 768 level)) { 769 mutex_unlock(&adev->pm.mutex); 770 return -EINVAL; 771 } 772 773 adev->pm.dpm.forced_level = level; 774 775 mutex_unlock(&adev->pm.mutex); 776 777 return 0; 778 } 779 780 int amdgpu_dpm_get_pp_num_states(struct amdgpu_device *adev, 781 struct pp_states_info *states) 782 { 783 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 784 int ret = 0; 785 786 if (!pp_funcs->get_pp_num_states) 787 return -EOPNOTSUPP; 788 789 mutex_lock(&adev->pm.mutex); 790 ret = pp_funcs->get_pp_num_states(adev->powerplay.pp_handle, 791 states); 792 mutex_unlock(&adev->pm.mutex); 793 794 return ret; 795 } 796 797 int amdgpu_dpm_dispatch_task(struct amdgpu_device *adev, 798 enum amd_pp_task task_id, 799 enum amd_pm_state_type *user_state) 800 { 801 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 802 int ret = 0; 803 804 if (!pp_funcs->dispatch_tasks) 805 return -EOPNOTSUPP; 806 807 mutex_lock(&adev->pm.mutex); 808 ret = pp_funcs->dispatch_tasks(adev->powerplay.pp_handle, 809 task_id, 810 user_state); 811 mutex_unlock(&adev->pm.mutex); 812 813 return ret; 814 } 815 816 int amdgpu_dpm_get_pp_table(struct amdgpu_device *adev, char **table) 817 { 818 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 819 int ret = 0; 820 821 if (!pp_funcs->get_pp_table) 822 return 0; 823 824 mutex_lock(&adev->pm.mutex); 825 ret = pp_funcs->get_pp_table(adev->powerplay.pp_handle, 826 table); 827 mutex_unlock(&adev->pm.mutex); 828 829 return ret; 830 } 831 832 int amdgpu_dpm_set_fine_grain_clk_vol(struct amdgpu_device *adev, 833 uint32_t type, 834 long *input, 835 uint32_t size) 836 { 837 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 838 int ret = 0; 839 840 if (!pp_funcs->set_fine_grain_clk_vol) 841 return 0; 842 843 mutex_lock(&adev->pm.mutex); 844 ret = pp_funcs->set_fine_grain_clk_vol(adev->powerplay.pp_handle, 845 type, 846 input, 847 size); 848 mutex_unlock(&adev->pm.mutex); 849 850 return ret; 851 } 852 853 int amdgpu_dpm_odn_edit_dpm_table(struct amdgpu_device *adev, 854 uint32_t type, 855 long *input, 856 uint32_t size) 857 { 858 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 859 int ret = 0; 860 861 if (!pp_funcs->odn_edit_dpm_table) 862 return 0; 863 864 mutex_lock(&adev->pm.mutex); 865 ret = pp_funcs->odn_edit_dpm_table(adev->powerplay.pp_handle, 866 type, 867 input, 868 size); 869 mutex_unlock(&adev->pm.mutex); 870 871 return ret; 872 } 873 874 int amdgpu_dpm_print_clock_levels(struct amdgpu_device *adev, 875 enum pp_clock_type type, 876 char *buf) 877 { 878 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 879 int ret = 0; 880 881 if (!pp_funcs->print_clock_levels) 882 return 0; 883 884 mutex_lock(&adev->pm.mutex); 885 ret = pp_funcs->print_clock_levels(adev->powerplay.pp_handle, 886 type, 887 buf); 888 mutex_unlock(&adev->pm.mutex); 889 890 return ret; 891 } 892 893 int amdgpu_dpm_emit_clock_levels(struct amdgpu_device *adev, 894 enum pp_clock_type type, 895 char *buf, 896 int *offset) 897 { 898 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 899 int ret = 0; 900 901 if (!pp_funcs->emit_clock_levels) 902 return -ENOENT; 903 904 mutex_lock(&adev->pm.mutex); 905 ret = pp_funcs->emit_clock_levels(adev->powerplay.pp_handle, 906 type, 907 buf, 908 offset); 909 mutex_unlock(&adev->pm.mutex); 910 911 return ret; 912 } 913 914 int amdgpu_dpm_set_ppfeature_status(struct amdgpu_device *adev, 915 uint64_t ppfeature_masks) 916 { 917 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 918 int ret = 0; 919 920 if (!pp_funcs->set_ppfeature_status) 921 return 0; 922 923 mutex_lock(&adev->pm.mutex); 924 ret = pp_funcs->set_ppfeature_status(adev->powerplay.pp_handle, 925 ppfeature_masks); 926 mutex_unlock(&adev->pm.mutex); 927 928 return ret; 929 } 930 931 int amdgpu_dpm_get_ppfeature_status(struct amdgpu_device *adev, char *buf) 932 { 933 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 934 int ret = 0; 935 936 if (!pp_funcs->get_ppfeature_status) 937 return 0; 938 939 mutex_lock(&adev->pm.mutex); 940 ret = pp_funcs->get_ppfeature_status(adev->powerplay.pp_handle, 941 buf); 942 mutex_unlock(&adev->pm.mutex); 943 944 return ret; 945 } 946 947 int amdgpu_dpm_force_clock_level(struct amdgpu_device *adev, 948 enum pp_clock_type type, 949 uint32_t mask) 950 { 951 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 952 int ret = 0; 953 954 if (!pp_funcs->force_clock_level) 955 return 0; 956 957 mutex_lock(&adev->pm.mutex); 958 ret = pp_funcs->force_clock_level(adev->powerplay.pp_handle, 959 type, 960 mask); 961 mutex_unlock(&adev->pm.mutex); 962 963 return ret; 964 } 965 966 int amdgpu_dpm_get_sclk_od(struct amdgpu_device *adev) 967 { 968 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 969 int ret = 0; 970 971 if (!pp_funcs->get_sclk_od) 972 return 0; 973 974 mutex_lock(&adev->pm.mutex); 975 ret = pp_funcs->get_sclk_od(adev->powerplay.pp_handle); 976 mutex_unlock(&adev->pm.mutex); 977 978 return ret; 979 } 980 981 int amdgpu_dpm_set_sclk_od(struct amdgpu_device *adev, uint32_t value) 982 { 983 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 984 985 if (is_support_sw_smu(adev)) 986 return 0; 987 988 mutex_lock(&adev->pm.mutex); 989 if (pp_funcs->set_sclk_od) 990 pp_funcs->set_sclk_od(adev->powerplay.pp_handle, value); 991 mutex_unlock(&adev->pm.mutex); 992 993 if (amdgpu_dpm_dispatch_task(adev, 994 AMD_PP_TASK_READJUST_POWER_STATE, 995 NULL) == -EOPNOTSUPP) { 996 adev->pm.dpm.current_ps = adev->pm.dpm.boot_ps; 997 amdgpu_dpm_compute_clocks(adev); 998 } 999 1000 return 0; 1001 } 1002 1003 int amdgpu_dpm_get_mclk_od(struct amdgpu_device *adev) 1004 { 1005 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 1006 int ret = 0; 1007 1008 if (!pp_funcs->get_mclk_od) 1009 return 0; 1010 1011 mutex_lock(&adev->pm.mutex); 1012 ret = pp_funcs->get_mclk_od(adev->powerplay.pp_handle); 1013 mutex_unlock(&adev->pm.mutex); 1014 1015 return ret; 1016 } 1017 1018 int amdgpu_dpm_set_mclk_od(struct amdgpu_device *adev, uint32_t value) 1019 { 1020 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 1021 1022 if (is_support_sw_smu(adev)) 1023 return 0; 1024 1025 mutex_lock(&adev->pm.mutex); 1026 if (pp_funcs->set_mclk_od) 1027 pp_funcs->set_mclk_od(adev->powerplay.pp_handle, value); 1028 mutex_unlock(&adev->pm.mutex); 1029 1030 if (amdgpu_dpm_dispatch_task(adev, 1031 AMD_PP_TASK_READJUST_POWER_STATE, 1032 NULL) == -EOPNOTSUPP) { 1033 adev->pm.dpm.current_ps = adev->pm.dpm.boot_ps; 1034 amdgpu_dpm_compute_clocks(adev); 1035 } 1036 1037 return 0; 1038 } 1039 1040 int amdgpu_dpm_get_power_profile_mode(struct amdgpu_device *adev, 1041 char *buf) 1042 { 1043 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 1044 int ret = 0; 1045 1046 if (!pp_funcs->get_power_profile_mode) 1047 return -EOPNOTSUPP; 1048 1049 mutex_lock(&adev->pm.mutex); 1050 ret = pp_funcs->get_power_profile_mode(adev->powerplay.pp_handle, 1051 buf); 1052 mutex_unlock(&adev->pm.mutex); 1053 1054 return ret; 1055 } 1056 1057 int amdgpu_dpm_set_power_profile_mode(struct amdgpu_device *adev, 1058 long *input, uint32_t size) 1059 { 1060 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 1061 int ret = 0; 1062 1063 if (!pp_funcs->set_power_profile_mode) 1064 return 0; 1065 1066 mutex_lock(&adev->pm.mutex); 1067 ret = pp_funcs->set_power_profile_mode(adev->powerplay.pp_handle, 1068 input, 1069 size); 1070 mutex_unlock(&adev->pm.mutex); 1071 1072 return ret; 1073 } 1074 1075 int amdgpu_dpm_get_gpu_metrics(struct amdgpu_device *adev, void **table) 1076 { 1077 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 1078 int ret = 0; 1079 1080 if (!pp_funcs->get_gpu_metrics) 1081 return 0; 1082 1083 mutex_lock(&adev->pm.mutex); 1084 ret = pp_funcs->get_gpu_metrics(adev->powerplay.pp_handle, 1085 table); 1086 mutex_unlock(&adev->pm.mutex); 1087 1088 return ret; 1089 } 1090 1091 int amdgpu_dpm_get_fan_control_mode(struct amdgpu_device *adev, 1092 uint32_t *fan_mode) 1093 { 1094 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 1095 int ret = 0; 1096 1097 if (!pp_funcs->get_fan_control_mode) 1098 return -EOPNOTSUPP; 1099 1100 mutex_lock(&adev->pm.mutex); 1101 ret = pp_funcs->get_fan_control_mode(adev->powerplay.pp_handle, 1102 fan_mode); 1103 mutex_unlock(&adev->pm.mutex); 1104 1105 return ret; 1106 } 1107 1108 int amdgpu_dpm_set_fan_speed_pwm(struct amdgpu_device *adev, 1109 uint32_t speed) 1110 { 1111 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 1112 int ret = 0; 1113 1114 if (!pp_funcs->set_fan_speed_pwm) 1115 return -EOPNOTSUPP; 1116 1117 mutex_lock(&adev->pm.mutex); 1118 ret = pp_funcs->set_fan_speed_pwm(adev->powerplay.pp_handle, 1119 speed); 1120 mutex_unlock(&adev->pm.mutex); 1121 1122 return ret; 1123 } 1124 1125 int amdgpu_dpm_get_fan_speed_pwm(struct amdgpu_device *adev, 1126 uint32_t *speed) 1127 { 1128 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 1129 int ret = 0; 1130 1131 if (!pp_funcs->get_fan_speed_pwm) 1132 return -EOPNOTSUPP; 1133 1134 mutex_lock(&adev->pm.mutex); 1135 ret = pp_funcs->get_fan_speed_pwm(adev->powerplay.pp_handle, 1136 speed); 1137 mutex_unlock(&adev->pm.mutex); 1138 1139 return ret; 1140 } 1141 1142 int amdgpu_dpm_get_fan_speed_rpm(struct amdgpu_device *adev, 1143 uint32_t *speed) 1144 { 1145 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 1146 int ret = 0; 1147 1148 if (!pp_funcs->get_fan_speed_rpm) 1149 return -EOPNOTSUPP; 1150 1151 mutex_lock(&adev->pm.mutex); 1152 ret = pp_funcs->get_fan_speed_rpm(adev->powerplay.pp_handle, 1153 speed); 1154 mutex_unlock(&adev->pm.mutex); 1155 1156 return ret; 1157 } 1158 1159 int amdgpu_dpm_set_fan_speed_rpm(struct amdgpu_device *adev, 1160 uint32_t speed) 1161 { 1162 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 1163 int ret = 0; 1164 1165 if (!pp_funcs->set_fan_speed_rpm) 1166 return -EOPNOTSUPP; 1167 1168 mutex_lock(&adev->pm.mutex); 1169 ret = pp_funcs->set_fan_speed_rpm(adev->powerplay.pp_handle, 1170 speed); 1171 mutex_unlock(&adev->pm.mutex); 1172 1173 return ret; 1174 } 1175 1176 int amdgpu_dpm_set_fan_control_mode(struct amdgpu_device *adev, 1177 uint32_t mode) 1178 { 1179 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 1180 int ret = 0; 1181 1182 if (!pp_funcs->set_fan_control_mode) 1183 return -EOPNOTSUPP; 1184 1185 mutex_lock(&adev->pm.mutex); 1186 ret = pp_funcs->set_fan_control_mode(adev->powerplay.pp_handle, 1187 mode); 1188 mutex_unlock(&adev->pm.mutex); 1189 1190 return ret; 1191 } 1192 1193 int amdgpu_dpm_get_power_limit(struct amdgpu_device *adev, 1194 uint32_t *limit, 1195 enum pp_power_limit_level pp_limit_level, 1196 enum pp_power_type power_type) 1197 { 1198 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 1199 int ret = 0; 1200 1201 if (!pp_funcs->get_power_limit) 1202 return -ENODATA; 1203 1204 mutex_lock(&adev->pm.mutex); 1205 ret = pp_funcs->get_power_limit(adev->powerplay.pp_handle, 1206 limit, 1207 pp_limit_level, 1208 power_type); 1209 mutex_unlock(&adev->pm.mutex); 1210 1211 return ret; 1212 } 1213 1214 int amdgpu_dpm_set_power_limit(struct amdgpu_device *adev, 1215 uint32_t limit) 1216 { 1217 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 1218 int ret = 0; 1219 1220 if (!pp_funcs->set_power_limit) 1221 return -EINVAL; 1222 1223 mutex_lock(&adev->pm.mutex); 1224 ret = pp_funcs->set_power_limit(adev->powerplay.pp_handle, 1225 limit); 1226 mutex_unlock(&adev->pm.mutex); 1227 1228 return ret; 1229 } 1230 1231 int amdgpu_dpm_is_cclk_dpm_supported(struct amdgpu_device *adev) 1232 { 1233 bool cclk_dpm_supported = false; 1234 1235 if (!is_support_sw_smu(adev)) 1236 return false; 1237 1238 mutex_lock(&adev->pm.mutex); 1239 cclk_dpm_supported = is_support_cclk_dpm(adev); 1240 mutex_unlock(&adev->pm.mutex); 1241 1242 return (int)cclk_dpm_supported; 1243 } 1244 1245 int amdgpu_dpm_debugfs_print_current_performance_level(struct amdgpu_device *adev, 1246 struct seq_file *m) 1247 { 1248 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 1249 1250 if (!pp_funcs->debugfs_print_current_performance_level) 1251 return -EOPNOTSUPP; 1252 1253 mutex_lock(&adev->pm.mutex); 1254 pp_funcs->debugfs_print_current_performance_level(adev->powerplay.pp_handle, 1255 m); 1256 mutex_unlock(&adev->pm.mutex); 1257 1258 return 0; 1259 } 1260 1261 int amdgpu_dpm_get_smu_prv_buf_details(struct amdgpu_device *adev, 1262 void **addr, 1263 size_t *size) 1264 { 1265 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 1266 int ret = 0; 1267 1268 if (!pp_funcs->get_smu_prv_buf_details) 1269 return -ENOSYS; 1270 1271 mutex_lock(&adev->pm.mutex); 1272 ret = pp_funcs->get_smu_prv_buf_details(adev->powerplay.pp_handle, 1273 addr, 1274 size); 1275 mutex_unlock(&adev->pm.mutex); 1276 1277 return ret; 1278 } 1279 1280 int amdgpu_dpm_is_overdrive_supported(struct amdgpu_device *adev) 1281 { 1282 struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle; 1283 struct smu_context *smu = adev->powerplay.pp_handle; 1284 1285 if ((is_support_sw_smu(adev) && smu->od_enabled) || 1286 (is_support_sw_smu(adev) && smu->is_apu) || 1287 (!is_support_sw_smu(adev) && hwmgr->od_enabled)) 1288 return true; 1289 1290 return false; 1291 } 1292 1293 int amdgpu_dpm_set_pp_table(struct amdgpu_device *adev, 1294 const char *buf, 1295 size_t size) 1296 { 1297 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 1298 int ret = 0; 1299 1300 if (!pp_funcs->set_pp_table) 1301 return -EOPNOTSUPP; 1302 1303 mutex_lock(&adev->pm.mutex); 1304 ret = pp_funcs->set_pp_table(adev->powerplay.pp_handle, 1305 buf, 1306 size); 1307 mutex_unlock(&adev->pm.mutex); 1308 1309 return ret; 1310 } 1311 1312 int amdgpu_dpm_get_num_cpu_cores(struct amdgpu_device *adev) 1313 { 1314 struct smu_context *smu = adev->powerplay.pp_handle; 1315 1316 if (!is_support_sw_smu(adev)) 1317 return INT_MAX; 1318 1319 return smu->cpu_core_num; 1320 } 1321 1322 void amdgpu_dpm_stb_debug_fs_init(struct amdgpu_device *adev) 1323 { 1324 if (!is_support_sw_smu(adev)) 1325 return; 1326 1327 amdgpu_smu_stb_debug_fs_init(adev); 1328 } 1329 1330 int amdgpu_dpm_display_configuration_change(struct amdgpu_device *adev, 1331 const struct amd_pp_display_configuration *input) 1332 { 1333 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 1334 int ret = 0; 1335 1336 if (!pp_funcs->display_configuration_change) 1337 return 0; 1338 1339 mutex_lock(&adev->pm.mutex); 1340 ret = pp_funcs->display_configuration_change(adev->powerplay.pp_handle, 1341 input); 1342 mutex_unlock(&adev->pm.mutex); 1343 1344 return ret; 1345 } 1346 1347 int amdgpu_dpm_get_clock_by_type(struct amdgpu_device *adev, 1348 enum amd_pp_clock_type type, 1349 struct amd_pp_clocks *clocks) 1350 { 1351 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 1352 int ret = 0; 1353 1354 if (!pp_funcs->get_clock_by_type) 1355 return 0; 1356 1357 mutex_lock(&adev->pm.mutex); 1358 ret = pp_funcs->get_clock_by_type(adev->powerplay.pp_handle, 1359 type, 1360 clocks); 1361 mutex_unlock(&adev->pm.mutex); 1362 1363 return ret; 1364 } 1365 1366 int amdgpu_dpm_get_display_mode_validation_clks(struct amdgpu_device *adev, 1367 struct amd_pp_simple_clock_info *clocks) 1368 { 1369 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 1370 int ret = 0; 1371 1372 if (!pp_funcs->get_display_mode_validation_clocks) 1373 return 0; 1374 1375 mutex_lock(&adev->pm.mutex); 1376 ret = pp_funcs->get_display_mode_validation_clocks(adev->powerplay.pp_handle, 1377 clocks); 1378 mutex_unlock(&adev->pm.mutex); 1379 1380 return ret; 1381 } 1382 1383 int amdgpu_dpm_get_clock_by_type_with_latency(struct amdgpu_device *adev, 1384 enum amd_pp_clock_type type, 1385 struct pp_clock_levels_with_latency *clocks) 1386 { 1387 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 1388 int ret = 0; 1389 1390 if (!pp_funcs->get_clock_by_type_with_latency) 1391 return 0; 1392 1393 mutex_lock(&adev->pm.mutex); 1394 ret = pp_funcs->get_clock_by_type_with_latency(adev->powerplay.pp_handle, 1395 type, 1396 clocks); 1397 mutex_unlock(&adev->pm.mutex); 1398 1399 return ret; 1400 } 1401 1402 int amdgpu_dpm_get_clock_by_type_with_voltage(struct amdgpu_device *adev, 1403 enum amd_pp_clock_type type, 1404 struct pp_clock_levels_with_voltage *clocks) 1405 { 1406 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 1407 int ret = 0; 1408 1409 if (!pp_funcs->get_clock_by_type_with_voltage) 1410 return 0; 1411 1412 mutex_lock(&adev->pm.mutex); 1413 ret = pp_funcs->get_clock_by_type_with_voltage(adev->powerplay.pp_handle, 1414 type, 1415 clocks); 1416 mutex_unlock(&adev->pm.mutex); 1417 1418 return ret; 1419 } 1420 1421 int amdgpu_dpm_set_watermarks_for_clocks_ranges(struct amdgpu_device *adev, 1422 void *clock_ranges) 1423 { 1424 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 1425 int ret = 0; 1426 1427 if (!pp_funcs->set_watermarks_for_clocks_ranges) 1428 return -EOPNOTSUPP; 1429 1430 mutex_lock(&adev->pm.mutex); 1431 ret = pp_funcs->set_watermarks_for_clocks_ranges(adev->powerplay.pp_handle, 1432 clock_ranges); 1433 mutex_unlock(&adev->pm.mutex); 1434 1435 return ret; 1436 } 1437 1438 int amdgpu_dpm_display_clock_voltage_request(struct amdgpu_device *adev, 1439 struct pp_display_clock_request *clock) 1440 { 1441 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 1442 int ret = 0; 1443 1444 if (!pp_funcs->display_clock_voltage_request) 1445 return -EOPNOTSUPP; 1446 1447 mutex_lock(&adev->pm.mutex); 1448 ret = pp_funcs->display_clock_voltage_request(adev->powerplay.pp_handle, 1449 clock); 1450 mutex_unlock(&adev->pm.mutex); 1451 1452 return ret; 1453 } 1454 1455 int amdgpu_dpm_get_current_clocks(struct amdgpu_device *adev, 1456 struct amd_pp_clock_info *clocks) 1457 { 1458 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 1459 int ret = 0; 1460 1461 if (!pp_funcs->get_current_clocks) 1462 return -EOPNOTSUPP; 1463 1464 mutex_lock(&adev->pm.mutex); 1465 ret = pp_funcs->get_current_clocks(adev->powerplay.pp_handle, 1466 clocks); 1467 mutex_unlock(&adev->pm.mutex); 1468 1469 return ret; 1470 } 1471 1472 void amdgpu_dpm_notify_smu_enable_pwe(struct amdgpu_device *adev) 1473 { 1474 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 1475 1476 if (!pp_funcs->notify_smu_enable_pwe) 1477 return; 1478 1479 mutex_lock(&adev->pm.mutex); 1480 pp_funcs->notify_smu_enable_pwe(adev->powerplay.pp_handle); 1481 mutex_unlock(&adev->pm.mutex); 1482 } 1483 1484 int amdgpu_dpm_set_active_display_count(struct amdgpu_device *adev, 1485 uint32_t count) 1486 { 1487 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 1488 int ret = 0; 1489 1490 if (!pp_funcs->set_active_display_count) 1491 return -EOPNOTSUPP; 1492 1493 mutex_lock(&adev->pm.mutex); 1494 ret = pp_funcs->set_active_display_count(adev->powerplay.pp_handle, 1495 count); 1496 mutex_unlock(&adev->pm.mutex); 1497 1498 return ret; 1499 } 1500 1501 int amdgpu_dpm_set_min_deep_sleep_dcefclk(struct amdgpu_device *adev, 1502 uint32_t clock) 1503 { 1504 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 1505 int ret = 0; 1506 1507 if (!pp_funcs->set_min_deep_sleep_dcefclk) 1508 return -EOPNOTSUPP; 1509 1510 mutex_lock(&adev->pm.mutex); 1511 ret = pp_funcs->set_min_deep_sleep_dcefclk(adev->powerplay.pp_handle, 1512 clock); 1513 mutex_unlock(&adev->pm.mutex); 1514 1515 return ret; 1516 } 1517 1518 void amdgpu_dpm_set_hard_min_dcefclk_by_freq(struct amdgpu_device *adev, 1519 uint32_t clock) 1520 { 1521 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 1522 1523 if (!pp_funcs->set_hard_min_dcefclk_by_freq) 1524 return; 1525 1526 mutex_lock(&adev->pm.mutex); 1527 pp_funcs->set_hard_min_dcefclk_by_freq(adev->powerplay.pp_handle, 1528 clock); 1529 mutex_unlock(&adev->pm.mutex); 1530 } 1531 1532 void amdgpu_dpm_set_hard_min_fclk_by_freq(struct amdgpu_device *adev, 1533 uint32_t clock) 1534 { 1535 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 1536 1537 if (!pp_funcs->set_hard_min_fclk_by_freq) 1538 return; 1539 1540 mutex_lock(&adev->pm.mutex); 1541 pp_funcs->set_hard_min_fclk_by_freq(adev->powerplay.pp_handle, 1542 clock); 1543 mutex_unlock(&adev->pm.mutex); 1544 } 1545 1546 int amdgpu_dpm_display_disable_memory_clock_switch(struct amdgpu_device *adev, 1547 bool disable_memory_clock_switch) 1548 { 1549 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 1550 int ret = 0; 1551 1552 if (!pp_funcs->display_disable_memory_clock_switch) 1553 return 0; 1554 1555 mutex_lock(&adev->pm.mutex); 1556 ret = pp_funcs->display_disable_memory_clock_switch(adev->powerplay.pp_handle, 1557 disable_memory_clock_switch); 1558 mutex_unlock(&adev->pm.mutex); 1559 1560 return ret; 1561 } 1562 1563 int amdgpu_dpm_get_max_sustainable_clocks_by_dc(struct amdgpu_device *adev, 1564 struct pp_smu_nv_clock_table *max_clocks) 1565 { 1566 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 1567 int ret = 0; 1568 1569 if (!pp_funcs->get_max_sustainable_clocks_by_dc) 1570 return -EOPNOTSUPP; 1571 1572 mutex_lock(&adev->pm.mutex); 1573 ret = pp_funcs->get_max_sustainable_clocks_by_dc(adev->powerplay.pp_handle, 1574 max_clocks); 1575 mutex_unlock(&adev->pm.mutex); 1576 1577 return ret; 1578 } 1579 1580 enum pp_smu_status amdgpu_dpm_get_uclk_dpm_states(struct amdgpu_device *adev, 1581 unsigned int *clock_values_in_khz, 1582 unsigned int *num_states) 1583 { 1584 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 1585 int ret = 0; 1586 1587 if (!pp_funcs->get_uclk_dpm_states) 1588 return -EOPNOTSUPP; 1589 1590 mutex_lock(&adev->pm.mutex); 1591 ret = pp_funcs->get_uclk_dpm_states(adev->powerplay.pp_handle, 1592 clock_values_in_khz, 1593 num_states); 1594 mutex_unlock(&adev->pm.mutex); 1595 1596 return ret; 1597 } 1598 1599 int amdgpu_dpm_get_dpm_clock_table(struct amdgpu_device *adev, 1600 struct dpm_clocks *clock_table) 1601 { 1602 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 1603 int ret = 0; 1604 1605 if (!pp_funcs->get_dpm_clock_table) 1606 return -EOPNOTSUPP; 1607 1608 mutex_lock(&adev->pm.mutex); 1609 ret = pp_funcs->get_dpm_clock_table(adev->powerplay.pp_handle, 1610 clock_table); 1611 mutex_unlock(&adev->pm.mutex); 1612 1613 return ret; 1614 } 1615