1 /* 2 * Copyright 2011 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Alex Deucher 23 */ 24 25 #include "amdgpu.h" 26 #include "amdgpu_atombios.h" 27 #include "amdgpu_i2c.h" 28 #include "amdgpu_dpm.h" 29 #include "atom.h" 30 #include "amd_pcie.h" 31 #include "amdgpu_display.h" 32 #include "hwmgr.h" 33 #include <linux/power_supply.h> 34 #include "amdgpu_smu.h" 35 36 #define amdgpu_dpm_enable_bapm(adev, e) \ 37 ((adev)->powerplay.pp_funcs->enable_bapm((adev)->powerplay.pp_handle, (e))) 38 39 int amdgpu_dpm_get_sclk(struct amdgpu_device *adev, bool low) 40 { 41 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 42 int ret = 0; 43 44 if (!pp_funcs->get_sclk) 45 return 0; 46 47 mutex_lock(&adev->pm.mutex); 48 ret = pp_funcs->get_sclk((adev)->powerplay.pp_handle, 49 low); 50 mutex_unlock(&adev->pm.mutex); 51 52 return ret; 53 } 54 55 int amdgpu_dpm_get_mclk(struct amdgpu_device *adev, bool low) 56 { 57 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 58 int ret = 0; 59 60 if (!pp_funcs->get_mclk) 61 return 0; 62 63 mutex_lock(&adev->pm.mutex); 64 ret = pp_funcs->get_mclk((adev)->powerplay.pp_handle, 65 low); 66 mutex_unlock(&adev->pm.mutex); 67 68 return ret; 69 } 70 71 int amdgpu_dpm_set_powergating_by_smu(struct amdgpu_device *adev, uint32_t block_type, bool gate) 72 { 73 int ret = 0; 74 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 75 enum ip_power_state pwr_state = gate ? POWER_STATE_OFF : POWER_STATE_ON; 76 77 if (atomic_read(&adev->pm.pwr_state[block_type]) == pwr_state) { 78 dev_dbg(adev->dev, "IP block%d already in the target %s state!", 79 block_type, gate ? "gate" : "ungate"); 80 return 0; 81 } 82 83 mutex_lock(&adev->pm.mutex); 84 85 switch (block_type) { 86 case AMD_IP_BLOCK_TYPE_UVD: 87 case AMD_IP_BLOCK_TYPE_VCE: 88 case AMD_IP_BLOCK_TYPE_GFX: 89 case AMD_IP_BLOCK_TYPE_VCN: 90 case AMD_IP_BLOCK_TYPE_SDMA: 91 case AMD_IP_BLOCK_TYPE_JPEG: 92 case AMD_IP_BLOCK_TYPE_GMC: 93 case AMD_IP_BLOCK_TYPE_ACP: 94 if (pp_funcs && pp_funcs->set_powergating_by_smu) 95 ret = (pp_funcs->set_powergating_by_smu( 96 (adev)->powerplay.pp_handle, block_type, gate)); 97 break; 98 default: 99 break; 100 } 101 102 if (!ret) 103 atomic_set(&adev->pm.pwr_state[block_type], pwr_state); 104 105 mutex_unlock(&adev->pm.mutex); 106 107 return ret; 108 } 109 110 int amdgpu_dpm_baco_enter(struct amdgpu_device *adev) 111 { 112 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 113 void *pp_handle = adev->powerplay.pp_handle; 114 int ret = 0; 115 116 if (!pp_funcs || !pp_funcs->set_asic_baco_state) 117 return -ENOENT; 118 119 mutex_lock(&adev->pm.mutex); 120 121 /* enter BACO state */ 122 ret = pp_funcs->set_asic_baco_state(pp_handle, 1); 123 124 mutex_unlock(&adev->pm.mutex); 125 126 return ret; 127 } 128 129 int amdgpu_dpm_baco_exit(struct amdgpu_device *adev) 130 { 131 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 132 void *pp_handle = adev->powerplay.pp_handle; 133 int ret = 0; 134 135 if (!pp_funcs || !pp_funcs->set_asic_baco_state) 136 return -ENOENT; 137 138 mutex_lock(&adev->pm.mutex); 139 140 /* exit BACO state */ 141 ret = pp_funcs->set_asic_baco_state(pp_handle, 0); 142 143 mutex_unlock(&adev->pm.mutex); 144 145 return ret; 146 } 147 148 int amdgpu_dpm_set_mp1_state(struct amdgpu_device *adev, 149 enum pp_mp1_state mp1_state) 150 { 151 int ret = 0; 152 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 153 154 if (pp_funcs && pp_funcs->set_mp1_state) { 155 mutex_lock(&adev->pm.mutex); 156 157 ret = pp_funcs->set_mp1_state( 158 adev->powerplay.pp_handle, 159 mp1_state); 160 161 mutex_unlock(&adev->pm.mutex); 162 } 163 164 return ret; 165 } 166 167 bool amdgpu_dpm_is_baco_supported(struct amdgpu_device *adev) 168 { 169 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 170 void *pp_handle = adev->powerplay.pp_handle; 171 bool baco_cap; 172 int ret = 0; 173 174 if (!pp_funcs || !pp_funcs->get_asic_baco_capability) 175 return false; 176 177 mutex_lock(&adev->pm.mutex); 178 179 ret = pp_funcs->get_asic_baco_capability(pp_handle, 180 &baco_cap); 181 182 mutex_unlock(&adev->pm.mutex); 183 184 return ret ? false : baco_cap; 185 } 186 187 int amdgpu_dpm_mode2_reset(struct amdgpu_device *adev) 188 { 189 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 190 void *pp_handle = adev->powerplay.pp_handle; 191 int ret = 0; 192 193 if (!pp_funcs || !pp_funcs->asic_reset_mode_2) 194 return -ENOENT; 195 196 mutex_lock(&adev->pm.mutex); 197 198 ret = pp_funcs->asic_reset_mode_2(pp_handle); 199 200 mutex_unlock(&adev->pm.mutex); 201 202 return ret; 203 } 204 205 int amdgpu_dpm_baco_reset(struct amdgpu_device *adev) 206 { 207 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 208 void *pp_handle = adev->powerplay.pp_handle; 209 int ret = 0; 210 211 if (!pp_funcs || !pp_funcs->set_asic_baco_state) 212 return -ENOENT; 213 214 mutex_lock(&adev->pm.mutex); 215 216 /* enter BACO state */ 217 ret = pp_funcs->set_asic_baco_state(pp_handle, 1); 218 if (ret) 219 goto out; 220 221 /* exit BACO state */ 222 ret = pp_funcs->set_asic_baco_state(pp_handle, 0); 223 224 out: 225 mutex_unlock(&adev->pm.mutex); 226 return ret; 227 } 228 229 bool amdgpu_dpm_is_mode1_reset_supported(struct amdgpu_device *adev) 230 { 231 struct smu_context *smu = adev->powerplay.pp_handle; 232 bool support_mode1_reset = false; 233 234 if (is_support_sw_smu(adev)) { 235 mutex_lock(&adev->pm.mutex); 236 support_mode1_reset = smu_mode1_reset_is_support(smu); 237 mutex_unlock(&adev->pm.mutex); 238 } 239 240 return support_mode1_reset; 241 } 242 243 int amdgpu_dpm_mode1_reset(struct amdgpu_device *adev) 244 { 245 struct smu_context *smu = adev->powerplay.pp_handle; 246 int ret = -EOPNOTSUPP; 247 248 if (is_support_sw_smu(adev)) { 249 mutex_lock(&adev->pm.mutex); 250 ret = smu_mode1_reset(smu); 251 mutex_unlock(&adev->pm.mutex); 252 } 253 254 return ret; 255 } 256 257 int amdgpu_dpm_switch_power_profile(struct amdgpu_device *adev, 258 enum PP_SMC_POWER_PROFILE type, 259 bool en) 260 { 261 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 262 int ret = 0; 263 264 if (amdgpu_sriov_vf(adev)) 265 return 0; 266 267 if (pp_funcs && pp_funcs->switch_power_profile) { 268 mutex_lock(&adev->pm.mutex); 269 ret = pp_funcs->switch_power_profile( 270 adev->powerplay.pp_handle, type, en); 271 mutex_unlock(&adev->pm.mutex); 272 } 273 274 return ret; 275 } 276 277 int amdgpu_dpm_set_xgmi_pstate(struct amdgpu_device *adev, 278 uint32_t pstate) 279 { 280 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 281 int ret = 0; 282 283 if (pp_funcs && pp_funcs->set_xgmi_pstate) { 284 mutex_lock(&adev->pm.mutex); 285 ret = pp_funcs->set_xgmi_pstate(adev->powerplay.pp_handle, 286 pstate); 287 mutex_unlock(&adev->pm.mutex); 288 } 289 290 return ret; 291 } 292 293 int amdgpu_dpm_set_df_cstate(struct amdgpu_device *adev, 294 uint32_t cstate) 295 { 296 int ret = 0; 297 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 298 void *pp_handle = adev->powerplay.pp_handle; 299 300 if (pp_funcs && pp_funcs->set_df_cstate) { 301 mutex_lock(&adev->pm.mutex); 302 ret = pp_funcs->set_df_cstate(pp_handle, cstate); 303 mutex_unlock(&adev->pm.mutex); 304 } 305 306 return ret; 307 } 308 309 int amdgpu_dpm_allow_xgmi_power_down(struct amdgpu_device *adev, bool en) 310 { 311 struct smu_context *smu = adev->powerplay.pp_handle; 312 int ret = 0; 313 314 if (is_support_sw_smu(adev)) { 315 mutex_lock(&adev->pm.mutex); 316 ret = smu_allow_xgmi_power_down(smu, en); 317 mutex_unlock(&adev->pm.mutex); 318 } 319 320 return ret; 321 } 322 323 int amdgpu_dpm_enable_mgpu_fan_boost(struct amdgpu_device *adev) 324 { 325 void *pp_handle = adev->powerplay.pp_handle; 326 const struct amd_pm_funcs *pp_funcs = 327 adev->powerplay.pp_funcs; 328 int ret = 0; 329 330 if (pp_funcs && pp_funcs->enable_mgpu_fan_boost) { 331 mutex_lock(&adev->pm.mutex); 332 ret = pp_funcs->enable_mgpu_fan_boost(pp_handle); 333 mutex_unlock(&adev->pm.mutex); 334 } 335 336 return ret; 337 } 338 339 int amdgpu_dpm_set_clockgating_by_smu(struct amdgpu_device *adev, 340 uint32_t msg_id) 341 { 342 void *pp_handle = adev->powerplay.pp_handle; 343 const struct amd_pm_funcs *pp_funcs = 344 adev->powerplay.pp_funcs; 345 int ret = 0; 346 347 if (pp_funcs && pp_funcs->set_clockgating_by_smu) { 348 mutex_lock(&adev->pm.mutex); 349 ret = pp_funcs->set_clockgating_by_smu(pp_handle, 350 msg_id); 351 mutex_unlock(&adev->pm.mutex); 352 } 353 354 return ret; 355 } 356 357 int amdgpu_dpm_smu_i2c_bus_access(struct amdgpu_device *adev, 358 bool acquire) 359 { 360 void *pp_handle = adev->powerplay.pp_handle; 361 const struct amd_pm_funcs *pp_funcs = 362 adev->powerplay.pp_funcs; 363 int ret = -EOPNOTSUPP; 364 365 if (pp_funcs && pp_funcs->smu_i2c_bus_access) { 366 mutex_lock(&adev->pm.mutex); 367 ret = pp_funcs->smu_i2c_bus_access(pp_handle, 368 acquire); 369 mutex_unlock(&adev->pm.mutex); 370 } 371 372 return ret; 373 } 374 375 void amdgpu_pm_acpi_event_handler(struct amdgpu_device *adev) 376 { 377 if (adev->pm.dpm_enabled) { 378 mutex_lock(&adev->pm.mutex); 379 if (power_supply_is_system_supplied() > 0) 380 adev->pm.ac_power = true; 381 else 382 adev->pm.ac_power = false; 383 384 if (adev->powerplay.pp_funcs && 385 adev->powerplay.pp_funcs->enable_bapm) 386 amdgpu_dpm_enable_bapm(adev, adev->pm.ac_power); 387 388 if (is_support_sw_smu(adev)) 389 smu_set_ac_dc(adev->powerplay.pp_handle); 390 391 mutex_unlock(&adev->pm.mutex); 392 } 393 } 394 395 int amdgpu_dpm_read_sensor(struct amdgpu_device *adev, enum amd_pp_sensors sensor, 396 void *data, uint32_t *size) 397 { 398 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 399 int ret = -EINVAL; 400 401 if (!data || !size) 402 return -EINVAL; 403 404 if (pp_funcs && pp_funcs->read_sensor) { 405 mutex_lock(&adev->pm.mutex); 406 ret = pp_funcs->read_sensor(adev->powerplay.pp_handle, 407 sensor, 408 data, 409 size); 410 mutex_unlock(&adev->pm.mutex); 411 } 412 413 return ret; 414 } 415 416 void amdgpu_dpm_compute_clocks(struct amdgpu_device *adev) 417 { 418 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 419 420 if (!adev->pm.dpm_enabled) 421 return; 422 423 if (!pp_funcs->pm_compute_clocks) 424 return; 425 426 mutex_lock(&adev->pm.mutex); 427 pp_funcs->pm_compute_clocks(adev->powerplay.pp_handle); 428 mutex_unlock(&adev->pm.mutex); 429 } 430 431 void amdgpu_dpm_enable_uvd(struct amdgpu_device *adev, bool enable) 432 { 433 int ret = 0; 434 435 ret = amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_UVD, !enable); 436 if (ret) 437 DRM_ERROR("Dpm %s uvd failed, ret = %d. \n", 438 enable ? "enable" : "disable", ret); 439 } 440 441 void amdgpu_dpm_enable_vce(struct amdgpu_device *adev, bool enable) 442 { 443 int ret = 0; 444 445 ret = amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_VCE, !enable); 446 if (ret) 447 DRM_ERROR("Dpm %s vce failed, ret = %d. \n", 448 enable ? "enable" : "disable", ret); 449 } 450 451 void amdgpu_dpm_enable_jpeg(struct amdgpu_device *adev, bool enable) 452 { 453 int ret = 0; 454 455 ret = amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_JPEG, !enable); 456 if (ret) 457 DRM_ERROR("Dpm %s jpeg failed, ret = %d. \n", 458 enable ? "enable" : "disable", ret); 459 } 460 461 int amdgpu_pm_load_smu_firmware(struct amdgpu_device *adev, uint32_t *smu_version) 462 { 463 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 464 int r = 0; 465 466 if (!pp_funcs->load_firmware) 467 return 0; 468 469 mutex_lock(&adev->pm.mutex); 470 r = pp_funcs->load_firmware(adev->powerplay.pp_handle); 471 if (r) { 472 pr_err("smu firmware loading failed\n"); 473 goto out; 474 } 475 476 if (smu_version) 477 *smu_version = adev->pm.fw_version; 478 479 out: 480 mutex_unlock(&adev->pm.mutex); 481 return r; 482 } 483 484 int amdgpu_dpm_handle_passthrough_sbr(struct amdgpu_device *adev, bool enable) 485 { 486 int ret = 0; 487 488 if (is_support_sw_smu(adev)) { 489 mutex_lock(&adev->pm.mutex); 490 ret = smu_handle_passthrough_sbr(adev->powerplay.pp_handle, 491 enable); 492 mutex_unlock(&adev->pm.mutex); 493 } 494 495 return ret; 496 } 497 498 int amdgpu_dpm_send_hbm_bad_pages_num(struct amdgpu_device *adev, uint32_t size) 499 { 500 struct smu_context *smu = adev->powerplay.pp_handle; 501 int ret = 0; 502 503 mutex_lock(&adev->pm.mutex); 504 ret = smu_send_hbm_bad_pages_num(smu, size); 505 mutex_unlock(&adev->pm.mutex); 506 507 return ret; 508 } 509 510 int amdgpu_dpm_get_dpm_freq_range(struct amdgpu_device *adev, 511 enum pp_clock_type type, 512 uint32_t *min, 513 uint32_t *max) 514 { 515 int ret = 0; 516 517 if (type != PP_SCLK) 518 return -EINVAL; 519 520 if (!is_support_sw_smu(adev)) 521 return -EOPNOTSUPP; 522 523 mutex_lock(&adev->pm.mutex); 524 ret = smu_get_dpm_freq_range(adev->powerplay.pp_handle, 525 SMU_SCLK, 526 min, 527 max); 528 mutex_unlock(&adev->pm.mutex); 529 530 return ret; 531 } 532 533 int amdgpu_dpm_set_soft_freq_range(struct amdgpu_device *adev, 534 enum pp_clock_type type, 535 uint32_t min, 536 uint32_t max) 537 { 538 struct smu_context *smu = adev->powerplay.pp_handle; 539 int ret = 0; 540 541 if (type != PP_SCLK) 542 return -EINVAL; 543 544 if (!is_support_sw_smu(adev)) 545 return -EOPNOTSUPP; 546 547 mutex_lock(&adev->pm.mutex); 548 ret = smu_set_soft_freq_range(smu, 549 SMU_SCLK, 550 min, 551 max); 552 mutex_unlock(&adev->pm.mutex); 553 554 return ret; 555 } 556 557 int amdgpu_dpm_write_watermarks_table(struct amdgpu_device *adev) 558 { 559 struct smu_context *smu = adev->powerplay.pp_handle; 560 int ret = 0; 561 562 if (!is_support_sw_smu(adev)) 563 return 0; 564 565 mutex_lock(&adev->pm.mutex); 566 ret = smu_write_watermarks_table(smu); 567 mutex_unlock(&adev->pm.mutex); 568 569 return ret; 570 } 571 572 int amdgpu_dpm_wait_for_event(struct amdgpu_device *adev, 573 enum smu_event_type event, 574 uint64_t event_arg) 575 { 576 struct smu_context *smu = adev->powerplay.pp_handle; 577 int ret = 0; 578 579 if (!is_support_sw_smu(adev)) 580 return -EOPNOTSUPP; 581 582 mutex_lock(&adev->pm.mutex); 583 ret = smu_wait_for_event(smu, event, event_arg); 584 mutex_unlock(&adev->pm.mutex); 585 586 return ret; 587 } 588 589 int amdgpu_dpm_get_status_gfxoff(struct amdgpu_device *adev, uint32_t *value) 590 { 591 struct smu_context *smu = adev->powerplay.pp_handle; 592 int ret = 0; 593 594 if (!is_support_sw_smu(adev)) 595 return -EOPNOTSUPP; 596 597 mutex_lock(&adev->pm.mutex); 598 ret = smu_get_status_gfxoff(smu, value); 599 mutex_unlock(&adev->pm.mutex); 600 601 return ret; 602 } 603 604 uint64_t amdgpu_dpm_get_thermal_throttling_counter(struct amdgpu_device *adev) 605 { 606 struct smu_context *smu = adev->powerplay.pp_handle; 607 608 if (!is_support_sw_smu(adev)) 609 return 0; 610 611 return atomic64_read(&smu->throttle_int_counter); 612 } 613 614 /* amdgpu_dpm_gfx_state_change - Handle gfx power state change set 615 * @adev: amdgpu_device pointer 616 * @state: gfx power state(1 -sGpuChangeState_D0Entry and 2 -sGpuChangeState_D3Entry) 617 * 618 */ 619 void amdgpu_dpm_gfx_state_change(struct amdgpu_device *adev, 620 enum gfx_change_state state) 621 { 622 mutex_lock(&adev->pm.mutex); 623 if (adev->powerplay.pp_funcs && 624 adev->powerplay.pp_funcs->gfx_state_change_set) 625 ((adev)->powerplay.pp_funcs->gfx_state_change_set( 626 (adev)->powerplay.pp_handle, state)); 627 mutex_unlock(&adev->pm.mutex); 628 } 629 630 int amdgpu_dpm_get_ecc_info(struct amdgpu_device *adev, 631 void *umc_ecc) 632 { 633 struct smu_context *smu = adev->powerplay.pp_handle; 634 635 if (!is_support_sw_smu(adev)) 636 return -EOPNOTSUPP; 637 638 return smu_get_ecc_info(smu, umc_ecc); 639 } 640 641 struct amd_vce_state *amdgpu_dpm_get_vce_clock_state(struct amdgpu_device *adev, 642 uint32_t idx) 643 { 644 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 645 struct amd_vce_state *vstate = NULL; 646 647 if (!pp_funcs->get_vce_clock_state) 648 return NULL; 649 650 mutex_lock(&adev->pm.mutex); 651 vstate = pp_funcs->get_vce_clock_state(adev->powerplay.pp_handle, 652 idx); 653 mutex_unlock(&adev->pm.mutex); 654 655 return vstate; 656 } 657 658 void amdgpu_dpm_get_current_power_state(struct amdgpu_device *adev, 659 enum amd_pm_state_type *state) 660 { 661 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 662 663 mutex_lock(&adev->pm.mutex); 664 665 if (!pp_funcs->get_current_power_state) { 666 *state = adev->pm.dpm.user_state; 667 goto out; 668 } 669 670 *state = pp_funcs->get_current_power_state(adev->powerplay.pp_handle); 671 if (*state < POWER_STATE_TYPE_DEFAULT || 672 *state > POWER_STATE_TYPE_INTERNAL_3DPERF) 673 *state = adev->pm.dpm.user_state; 674 675 out: 676 mutex_unlock(&adev->pm.mutex); 677 } 678 679 void amdgpu_dpm_set_power_state(struct amdgpu_device *adev, 680 enum amd_pm_state_type state) 681 { 682 mutex_lock(&adev->pm.mutex); 683 adev->pm.dpm.user_state = state; 684 mutex_unlock(&adev->pm.mutex); 685 686 if (is_support_sw_smu(adev)) 687 return; 688 689 if (amdgpu_dpm_dispatch_task(adev, 690 AMD_PP_TASK_ENABLE_USER_STATE, 691 &state) == -EOPNOTSUPP) 692 amdgpu_dpm_compute_clocks(adev); 693 } 694 695 enum amd_dpm_forced_level amdgpu_dpm_get_performance_level(struct amdgpu_device *adev) 696 { 697 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 698 enum amd_dpm_forced_level level; 699 700 mutex_lock(&adev->pm.mutex); 701 if (pp_funcs->get_performance_level) 702 level = pp_funcs->get_performance_level(adev->powerplay.pp_handle); 703 else 704 level = adev->pm.dpm.forced_level; 705 mutex_unlock(&adev->pm.mutex); 706 707 return level; 708 } 709 710 int amdgpu_dpm_force_performance_level(struct amdgpu_device *adev, 711 enum amd_dpm_forced_level level) 712 { 713 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 714 int ret = 0; 715 716 if (!pp_funcs->force_performance_level) 717 return 0; 718 719 mutex_lock(&adev->pm.mutex); 720 721 if (adev->pm.dpm.thermal_active) { 722 ret = -EINVAL; 723 goto out; 724 } 725 726 if (pp_funcs->force_performance_level(adev->powerplay.pp_handle, 727 level)) 728 ret = -EINVAL; 729 730 if (!ret) 731 adev->pm.dpm.forced_level = level; 732 733 out: 734 mutex_unlock(&adev->pm.mutex); 735 736 return ret; 737 } 738 739 int amdgpu_dpm_get_pp_num_states(struct amdgpu_device *adev, 740 struct pp_states_info *states) 741 { 742 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 743 int ret = 0; 744 745 if (!pp_funcs->get_pp_num_states) 746 return -EOPNOTSUPP; 747 748 mutex_lock(&adev->pm.mutex); 749 ret = pp_funcs->get_pp_num_states(adev->powerplay.pp_handle, 750 states); 751 mutex_unlock(&adev->pm.mutex); 752 753 return ret; 754 } 755 756 int amdgpu_dpm_dispatch_task(struct amdgpu_device *adev, 757 enum amd_pp_task task_id, 758 enum amd_pm_state_type *user_state) 759 { 760 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 761 int ret = 0; 762 763 if (!pp_funcs->dispatch_tasks) 764 return -EOPNOTSUPP; 765 766 mutex_lock(&adev->pm.mutex); 767 ret = pp_funcs->dispatch_tasks(adev->powerplay.pp_handle, 768 task_id, 769 user_state); 770 mutex_unlock(&adev->pm.mutex); 771 772 return ret; 773 } 774 775 int amdgpu_dpm_get_pp_table(struct amdgpu_device *adev, char **table) 776 { 777 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 778 int ret = 0; 779 780 if (!pp_funcs->get_pp_table) 781 return 0; 782 783 mutex_lock(&adev->pm.mutex); 784 ret = pp_funcs->get_pp_table(adev->powerplay.pp_handle, 785 table); 786 mutex_unlock(&adev->pm.mutex); 787 788 return ret; 789 } 790 791 int amdgpu_dpm_set_fine_grain_clk_vol(struct amdgpu_device *adev, 792 uint32_t type, 793 long *input, 794 uint32_t size) 795 { 796 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 797 int ret = 0; 798 799 if (!pp_funcs->set_fine_grain_clk_vol) 800 return 0; 801 802 mutex_lock(&adev->pm.mutex); 803 ret = pp_funcs->set_fine_grain_clk_vol(adev->powerplay.pp_handle, 804 type, 805 input, 806 size); 807 mutex_unlock(&adev->pm.mutex); 808 809 return ret; 810 } 811 812 int amdgpu_dpm_odn_edit_dpm_table(struct amdgpu_device *adev, 813 uint32_t type, 814 long *input, 815 uint32_t size) 816 { 817 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 818 int ret = 0; 819 820 if (!pp_funcs->odn_edit_dpm_table) 821 return 0; 822 823 mutex_lock(&adev->pm.mutex); 824 ret = pp_funcs->odn_edit_dpm_table(adev->powerplay.pp_handle, 825 type, 826 input, 827 size); 828 mutex_unlock(&adev->pm.mutex); 829 830 return ret; 831 } 832 833 int amdgpu_dpm_print_clock_levels(struct amdgpu_device *adev, 834 enum pp_clock_type type, 835 char *buf) 836 { 837 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 838 int ret = 0; 839 840 if (!pp_funcs->print_clock_levels) 841 return 0; 842 843 mutex_lock(&adev->pm.mutex); 844 ret = pp_funcs->print_clock_levels(adev->powerplay.pp_handle, 845 type, 846 buf); 847 mutex_unlock(&adev->pm.mutex); 848 849 return ret; 850 } 851 852 int amdgpu_dpm_set_ppfeature_status(struct amdgpu_device *adev, 853 uint64_t ppfeature_masks) 854 { 855 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 856 int ret = 0; 857 858 if (!pp_funcs->set_ppfeature_status) 859 return 0; 860 861 mutex_lock(&adev->pm.mutex); 862 ret = pp_funcs->set_ppfeature_status(adev->powerplay.pp_handle, 863 ppfeature_masks); 864 mutex_unlock(&adev->pm.mutex); 865 866 return ret; 867 } 868 869 int amdgpu_dpm_get_ppfeature_status(struct amdgpu_device *adev, char *buf) 870 { 871 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 872 int ret = 0; 873 874 if (!pp_funcs->get_ppfeature_status) 875 return 0; 876 877 mutex_lock(&adev->pm.mutex); 878 ret = pp_funcs->get_ppfeature_status(adev->powerplay.pp_handle, 879 buf); 880 mutex_unlock(&adev->pm.mutex); 881 882 return ret; 883 } 884 885 int amdgpu_dpm_force_clock_level(struct amdgpu_device *adev, 886 enum pp_clock_type type, 887 uint32_t mask) 888 { 889 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 890 int ret = 0; 891 892 if (!pp_funcs->force_clock_level) 893 return 0; 894 895 mutex_lock(&adev->pm.mutex); 896 ret = pp_funcs->force_clock_level(adev->powerplay.pp_handle, 897 type, 898 mask); 899 mutex_unlock(&adev->pm.mutex); 900 901 return ret; 902 } 903 904 int amdgpu_dpm_get_sclk_od(struct amdgpu_device *adev) 905 { 906 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 907 int ret = 0; 908 909 if (!pp_funcs->get_sclk_od) 910 return 0; 911 912 mutex_lock(&adev->pm.mutex); 913 ret = pp_funcs->get_sclk_od(adev->powerplay.pp_handle); 914 mutex_unlock(&adev->pm.mutex); 915 916 return ret; 917 } 918 919 int amdgpu_dpm_set_sclk_od(struct amdgpu_device *adev, uint32_t value) 920 { 921 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 922 923 if (is_support_sw_smu(adev)) 924 return 0; 925 926 mutex_lock(&adev->pm.mutex); 927 if (pp_funcs->set_sclk_od) 928 pp_funcs->set_sclk_od(adev->powerplay.pp_handle, value); 929 mutex_unlock(&adev->pm.mutex); 930 931 if (amdgpu_dpm_dispatch_task(adev, 932 AMD_PP_TASK_READJUST_POWER_STATE, 933 NULL) == -EOPNOTSUPP) { 934 adev->pm.dpm.current_ps = adev->pm.dpm.boot_ps; 935 amdgpu_dpm_compute_clocks(adev); 936 } 937 938 return 0; 939 } 940 941 int amdgpu_dpm_get_mclk_od(struct amdgpu_device *adev) 942 { 943 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 944 int ret = 0; 945 946 if (!pp_funcs->get_mclk_od) 947 return 0; 948 949 mutex_lock(&adev->pm.mutex); 950 ret = pp_funcs->get_mclk_od(adev->powerplay.pp_handle); 951 mutex_unlock(&adev->pm.mutex); 952 953 return ret; 954 } 955 956 int amdgpu_dpm_set_mclk_od(struct amdgpu_device *adev, uint32_t value) 957 { 958 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 959 960 if (is_support_sw_smu(adev)) 961 return 0; 962 963 mutex_lock(&adev->pm.mutex); 964 if (pp_funcs->set_mclk_od) 965 pp_funcs->set_mclk_od(adev->powerplay.pp_handle, value); 966 mutex_unlock(&adev->pm.mutex); 967 968 if (amdgpu_dpm_dispatch_task(adev, 969 AMD_PP_TASK_READJUST_POWER_STATE, 970 NULL) == -EOPNOTSUPP) { 971 adev->pm.dpm.current_ps = adev->pm.dpm.boot_ps; 972 amdgpu_dpm_compute_clocks(adev); 973 } 974 975 return 0; 976 } 977 978 int amdgpu_dpm_get_power_profile_mode(struct amdgpu_device *adev, 979 char *buf) 980 { 981 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 982 int ret = 0; 983 984 if (!pp_funcs->get_power_profile_mode) 985 return -EOPNOTSUPP; 986 987 mutex_lock(&adev->pm.mutex); 988 ret = pp_funcs->get_power_profile_mode(adev->powerplay.pp_handle, 989 buf); 990 mutex_unlock(&adev->pm.mutex); 991 992 return ret; 993 } 994 995 int amdgpu_dpm_set_power_profile_mode(struct amdgpu_device *adev, 996 long *input, uint32_t size) 997 { 998 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 999 int ret = 0; 1000 1001 if (!pp_funcs->set_power_profile_mode) 1002 return 0; 1003 1004 mutex_lock(&adev->pm.mutex); 1005 ret = pp_funcs->set_power_profile_mode(adev->powerplay.pp_handle, 1006 input, 1007 size); 1008 mutex_unlock(&adev->pm.mutex); 1009 1010 return ret; 1011 } 1012 1013 int amdgpu_dpm_get_gpu_metrics(struct amdgpu_device *adev, void **table) 1014 { 1015 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 1016 int ret = 0; 1017 1018 if (!pp_funcs->get_gpu_metrics) 1019 return 0; 1020 1021 mutex_lock(&adev->pm.mutex); 1022 ret = pp_funcs->get_gpu_metrics(adev->powerplay.pp_handle, 1023 table); 1024 mutex_unlock(&adev->pm.mutex); 1025 1026 return ret; 1027 } 1028 1029 int amdgpu_dpm_get_fan_control_mode(struct amdgpu_device *adev, 1030 uint32_t *fan_mode) 1031 { 1032 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 1033 1034 if (!pp_funcs->get_fan_control_mode) 1035 return -EOPNOTSUPP; 1036 1037 mutex_lock(&adev->pm.mutex); 1038 *fan_mode = pp_funcs->get_fan_control_mode(adev->powerplay.pp_handle); 1039 mutex_unlock(&adev->pm.mutex); 1040 1041 return 0; 1042 } 1043 1044 int amdgpu_dpm_set_fan_speed_pwm(struct amdgpu_device *adev, 1045 uint32_t speed) 1046 { 1047 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 1048 int ret = 0; 1049 1050 if (!pp_funcs->set_fan_speed_pwm) 1051 return -EINVAL; 1052 1053 mutex_lock(&adev->pm.mutex); 1054 ret = pp_funcs->set_fan_speed_pwm(adev->powerplay.pp_handle, 1055 speed); 1056 mutex_unlock(&adev->pm.mutex); 1057 1058 return ret; 1059 } 1060 1061 int amdgpu_dpm_get_fan_speed_pwm(struct amdgpu_device *adev, 1062 uint32_t *speed) 1063 { 1064 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 1065 int ret = 0; 1066 1067 if (!pp_funcs->get_fan_speed_pwm) 1068 return -EINVAL; 1069 1070 mutex_lock(&adev->pm.mutex); 1071 ret = pp_funcs->get_fan_speed_pwm(adev->powerplay.pp_handle, 1072 speed); 1073 mutex_unlock(&adev->pm.mutex); 1074 1075 return ret; 1076 } 1077 1078 int amdgpu_dpm_get_fan_speed_rpm(struct amdgpu_device *adev, 1079 uint32_t *speed) 1080 { 1081 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 1082 int ret = 0; 1083 1084 if (!pp_funcs->get_fan_speed_rpm) 1085 return -EINVAL; 1086 1087 mutex_lock(&adev->pm.mutex); 1088 ret = pp_funcs->get_fan_speed_rpm(adev->powerplay.pp_handle, 1089 speed); 1090 mutex_unlock(&adev->pm.mutex); 1091 1092 return ret; 1093 } 1094 1095 int amdgpu_dpm_set_fan_speed_rpm(struct amdgpu_device *adev, 1096 uint32_t speed) 1097 { 1098 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 1099 int ret = 0; 1100 1101 if (!pp_funcs->set_fan_speed_rpm) 1102 return -EINVAL; 1103 1104 mutex_lock(&adev->pm.mutex); 1105 ret = pp_funcs->set_fan_speed_rpm(adev->powerplay.pp_handle, 1106 speed); 1107 mutex_unlock(&adev->pm.mutex); 1108 1109 return ret; 1110 } 1111 1112 int amdgpu_dpm_set_fan_control_mode(struct amdgpu_device *adev, 1113 uint32_t mode) 1114 { 1115 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 1116 1117 if (!pp_funcs->set_fan_control_mode) 1118 return -EOPNOTSUPP; 1119 1120 mutex_lock(&adev->pm.mutex); 1121 pp_funcs->set_fan_control_mode(adev->powerplay.pp_handle, 1122 mode); 1123 mutex_unlock(&adev->pm.mutex); 1124 1125 return 0; 1126 } 1127 1128 int amdgpu_dpm_get_power_limit(struct amdgpu_device *adev, 1129 uint32_t *limit, 1130 enum pp_power_limit_level pp_limit_level, 1131 enum pp_power_type power_type) 1132 { 1133 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 1134 int ret = 0; 1135 1136 if (!pp_funcs->get_power_limit) 1137 return -ENODATA; 1138 1139 mutex_lock(&adev->pm.mutex); 1140 ret = pp_funcs->get_power_limit(adev->powerplay.pp_handle, 1141 limit, 1142 pp_limit_level, 1143 power_type); 1144 mutex_unlock(&adev->pm.mutex); 1145 1146 return ret; 1147 } 1148 1149 int amdgpu_dpm_set_power_limit(struct amdgpu_device *adev, 1150 uint32_t limit) 1151 { 1152 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 1153 int ret = 0; 1154 1155 if (!pp_funcs->set_power_limit) 1156 return -EINVAL; 1157 1158 mutex_lock(&adev->pm.mutex); 1159 ret = pp_funcs->set_power_limit(adev->powerplay.pp_handle, 1160 limit); 1161 mutex_unlock(&adev->pm.mutex); 1162 1163 return ret; 1164 } 1165 1166 int amdgpu_dpm_is_cclk_dpm_supported(struct amdgpu_device *adev) 1167 { 1168 bool cclk_dpm_supported = false; 1169 1170 if (!is_support_sw_smu(adev)) 1171 return false; 1172 1173 mutex_lock(&adev->pm.mutex); 1174 cclk_dpm_supported = is_support_cclk_dpm(adev); 1175 mutex_unlock(&adev->pm.mutex); 1176 1177 return (int)cclk_dpm_supported; 1178 } 1179 1180 int amdgpu_dpm_debugfs_print_current_performance_level(struct amdgpu_device *adev, 1181 struct seq_file *m) 1182 { 1183 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 1184 1185 if (!pp_funcs->debugfs_print_current_performance_level) 1186 return -EOPNOTSUPP; 1187 1188 mutex_lock(&adev->pm.mutex); 1189 pp_funcs->debugfs_print_current_performance_level(adev->powerplay.pp_handle, 1190 m); 1191 mutex_unlock(&adev->pm.mutex); 1192 1193 return 0; 1194 } 1195 1196 int amdgpu_dpm_get_smu_prv_buf_details(struct amdgpu_device *adev, 1197 void **addr, 1198 size_t *size) 1199 { 1200 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 1201 int ret = 0; 1202 1203 if (!pp_funcs->get_smu_prv_buf_details) 1204 return -ENOSYS; 1205 1206 mutex_lock(&adev->pm.mutex); 1207 ret = pp_funcs->get_smu_prv_buf_details(adev->powerplay.pp_handle, 1208 addr, 1209 size); 1210 mutex_unlock(&adev->pm.mutex); 1211 1212 return ret; 1213 } 1214 1215 int amdgpu_dpm_is_overdrive_supported(struct amdgpu_device *adev) 1216 { 1217 struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle; 1218 struct smu_context *smu = adev->powerplay.pp_handle; 1219 1220 if ((is_support_sw_smu(adev) && smu->od_enabled) || 1221 (is_support_sw_smu(adev) && smu->is_apu) || 1222 (!is_support_sw_smu(adev) && hwmgr->od_enabled)) 1223 return true; 1224 1225 return false; 1226 } 1227 1228 int amdgpu_dpm_set_pp_table(struct amdgpu_device *adev, 1229 const char *buf, 1230 size_t size) 1231 { 1232 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 1233 int ret = 0; 1234 1235 if (!pp_funcs->set_pp_table) 1236 return -EOPNOTSUPP; 1237 1238 mutex_lock(&adev->pm.mutex); 1239 ret = pp_funcs->set_pp_table(adev->powerplay.pp_handle, 1240 buf, 1241 size); 1242 mutex_unlock(&adev->pm.mutex); 1243 1244 return ret; 1245 } 1246 1247 int amdgpu_dpm_get_num_cpu_cores(struct amdgpu_device *adev) 1248 { 1249 struct smu_context *smu = adev->powerplay.pp_handle; 1250 1251 if (!is_support_sw_smu(adev)) 1252 return INT_MAX; 1253 1254 return smu->cpu_core_num; 1255 } 1256 1257 void amdgpu_dpm_stb_debug_fs_init(struct amdgpu_device *adev) 1258 { 1259 if (!is_support_sw_smu(adev)) 1260 return; 1261 1262 amdgpu_smu_stb_debug_fs_init(adev); 1263 } 1264 1265 int amdgpu_dpm_display_configuration_change(struct amdgpu_device *adev, 1266 const struct amd_pp_display_configuration *input) 1267 { 1268 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 1269 int ret = 0; 1270 1271 if (!pp_funcs->display_configuration_change) 1272 return 0; 1273 1274 mutex_lock(&adev->pm.mutex); 1275 ret = pp_funcs->display_configuration_change(adev->powerplay.pp_handle, 1276 input); 1277 mutex_unlock(&adev->pm.mutex); 1278 1279 return ret; 1280 } 1281 1282 int amdgpu_dpm_get_clock_by_type(struct amdgpu_device *adev, 1283 enum amd_pp_clock_type type, 1284 struct amd_pp_clocks *clocks) 1285 { 1286 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 1287 int ret = 0; 1288 1289 if (!pp_funcs->get_clock_by_type) 1290 return 0; 1291 1292 mutex_lock(&adev->pm.mutex); 1293 ret = pp_funcs->get_clock_by_type(adev->powerplay.pp_handle, 1294 type, 1295 clocks); 1296 mutex_unlock(&adev->pm.mutex); 1297 1298 return ret; 1299 } 1300 1301 int amdgpu_dpm_get_display_mode_validation_clks(struct amdgpu_device *adev, 1302 struct amd_pp_simple_clock_info *clocks) 1303 { 1304 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 1305 int ret = 0; 1306 1307 if (!pp_funcs->get_display_mode_validation_clocks) 1308 return 0; 1309 1310 mutex_lock(&adev->pm.mutex); 1311 ret = pp_funcs->get_display_mode_validation_clocks(adev->powerplay.pp_handle, 1312 clocks); 1313 mutex_unlock(&adev->pm.mutex); 1314 1315 return ret; 1316 } 1317 1318 int amdgpu_dpm_get_clock_by_type_with_latency(struct amdgpu_device *adev, 1319 enum amd_pp_clock_type type, 1320 struct pp_clock_levels_with_latency *clocks) 1321 { 1322 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 1323 int ret = 0; 1324 1325 if (!pp_funcs->get_clock_by_type_with_latency) 1326 return 0; 1327 1328 mutex_lock(&adev->pm.mutex); 1329 ret = pp_funcs->get_clock_by_type_with_latency(adev->powerplay.pp_handle, 1330 type, 1331 clocks); 1332 mutex_unlock(&adev->pm.mutex); 1333 1334 return ret; 1335 } 1336 1337 int amdgpu_dpm_get_clock_by_type_with_voltage(struct amdgpu_device *adev, 1338 enum amd_pp_clock_type type, 1339 struct pp_clock_levels_with_voltage *clocks) 1340 { 1341 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 1342 int ret = 0; 1343 1344 if (!pp_funcs->get_clock_by_type_with_voltage) 1345 return 0; 1346 1347 mutex_lock(&adev->pm.mutex); 1348 ret = pp_funcs->get_clock_by_type_with_voltage(adev->powerplay.pp_handle, 1349 type, 1350 clocks); 1351 mutex_unlock(&adev->pm.mutex); 1352 1353 return ret; 1354 } 1355 1356 int amdgpu_dpm_set_watermarks_for_clocks_ranges(struct amdgpu_device *adev, 1357 void *clock_ranges) 1358 { 1359 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 1360 int ret = 0; 1361 1362 if (!pp_funcs->set_watermarks_for_clocks_ranges) 1363 return -EOPNOTSUPP; 1364 1365 mutex_lock(&adev->pm.mutex); 1366 ret = pp_funcs->set_watermarks_for_clocks_ranges(adev->powerplay.pp_handle, 1367 clock_ranges); 1368 mutex_unlock(&adev->pm.mutex); 1369 1370 return ret; 1371 } 1372 1373 int amdgpu_dpm_display_clock_voltage_request(struct amdgpu_device *adev, 1374 struct pp_display_clock_request *clock) 1375 { 1376 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 1377 int ret = 0; 1378 1379 if (!pp_funcs->display_clock_voltage_request) 1380 return -EOPNOTSUPP; 1381 1382 mutex_lock(&adev->pm.mutex); 1383 ret = pp_funcs->display_clock_voltage_request(adev->powerplay.pp_handle, 1384 clock); 1385 mutex_unlock(&adev->pm.mutex); 1386 1387 return ret; 1388 } 1389 1390 int amdgpu_dpm_get_current_clocks(struct amdgpu_device *adev, 1391 struct amd_pp_clock_info *clocks) 1392 { 1393 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 1394 int ret = 0; 1395 1396 if (!pp_funcs->get_current_clocks) 1397 return -EOPNOTSUPP; 1398 1399 mutex_lock(&adev->pm.mutex); 1400 ret = pp_funcs->get_current_clocks(adev->powerplay.pp_handle, 1401 clocks); 1402 mutex_unlock(&adev->pm.mutex); 1403 1404 return ret; 1405 } 1406 1407 void amdgpu_dpm_notify_smu_enable_pwe(struct amdgpu_device *adev) 1408 { 1409 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 1410 1411 if (!pp_funcs->notify_smu_enable_pwe) 1412 return; 1413 1414 mutex_lock(&adev->pm.mutex); 1415 pp_funcs->notify_smu_enable_pwe(adev->powerplay.pp_handle); 1416 mutex_unlock(&adev->pm.mutex); 1417 } 1418 1419 int amdgpu_dpm_set_active_display_count(struct amdgpu_device *adev, 1420 uint32_t count) 1421 { 1422 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 1423 int ret = 0; 1424 1425 if (!pp_funcs->set_active_display_count) 1426 return -EOPNOTSUPP; 1427 1428 mutex_lock(&adev->pm.mutex); 1429 ret = pp_funcs->set_active_display_count(adev->powerplay.pp_handle, 1430 count); 1431 mutex_unlock(&adev->pm.mutex); 1432 1433 return ret; 1434 } 1435 1436 int amdgpu_dpm_set_min_deep_sleep_dcefclk(struct amdgpu_device *adev, 1437 uint32_t clock) 1438 { 1439 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 1440 int ret = 0; 1441 1442 if (!pp_funcs->set_min_deep_sleep_dcefclk) 1443 return -EOPNOTSUPP; 1444 1445 mutex_lock(&adev->pm.mutex); 1446 ret = pp_funcs->set_min_deep_sleep_dcefclk(adev->powerplay.pp_handle, 1447 clock); 1448 mutex_unlock(&adev->pm.mutex); 1449 1450 return ret; 1451 } 1452 1453 void amdgpu_dpm_set_hard_min_dcefclk_by_freq(struct amdgpu_device *adev, 1454 uint32_t clock) 1455 { 1456 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 1457 1458 if (!pp_funcs->set_hard_min_dcefclk_by_freq) 1459 return; 1460 1461 mutex_lock(&adev->pm.mutex); 1462 pp_funcs->set_hard_min_dcefclk_by_freq(adev->powerplay.pp_handle, 1463 clock); 1464 mutex_unlock(&adev->pm.mutex); 1465 } 1466 1467 void amdgpu_dpm_set_hard_min_fclk_by_freq(struct amdgpu_device *adev, 1468 uint32_t clock) 1469 { 1470 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 1471 1472 if (!pp_funcs->set_hard_min_fclk_by_freq) 1473 return; 1474 1475 mutex_lock(&adev->pm.mutex); 1476 pp_funcs->set_hard_min_fclk_by_freq(adev->powerplay.pp_handle, 1477 clock); 1478 mutex_unlock(&adev->pm.mutex); 1479 } 1480 1481 int amdgpu_dpm_display_disable_memory_clock_switch(struct amdgpu_device *adev, 1482 bool disable_memory_clock_switch) 1483 { 1484 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 1485 int ret = 0; 1486 1487 if (!pp_funcs->display_disable_memory_clock_switch) 1488 return 0; 1489 1490 mutex_lock(&adev->pm.mutex); 1491 ret = pp_funcs->display_disable_memory_clock_switch(adev->powerplay.pp_handle, 1492 disable_memory_clock_switch); 1493 mutex_unlock(&adev->pm.mutex); 1494 1495 return ret; 1496 } 1497 1498 int amdgpu_dpm_get_max_sustainable_clocks_by_dc(struct amdgpu_device *adev, 1499 struct pp_smu_nv_clock_table *max_clocks) 1500 { 1501 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 1502 int ret = 0; 1503 1504 if (!pp_funcs->get_max_sustainable_clocks_by_dc) 1505 return -EOPNOTSUPP; 1506 1507 mutex_lock(&adev->pm.mutex); 1508 ret = pp_funcs->get_max_sustainable_clocks_by_dc(adev->powerplay.pp_handle, 1509 max_clocks); 1510 mutex_unlock(&adev->pm.mutex); 1511 1512 return ret; 1513 } 1514 1515 enum pp_smu_status amdgpu_dpm_get_uclk_dpm_states(struct amdgpu_device *adev, 1516 unsigned int *clock_values_in_khz, 1517 unsigned int *num_states) 1518 { 1519 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 1520 int ret = 0; 1521 1522 if (!pp_funcs->get_uclk_dpm_states) 1523 return -EOPNOTSUPP; 1524 1525 mutex_lock(&adev->pm.mutex); 1526 ret = pp_funcs->get_uclk_dpm_states(adev->powerplay.pp_handle, 1527 clock_values_in_khz, 1528 num_states); 1529 mutex_unlock(&adev->pm.mutex); 1530 1531 return ret; 1532 } 1533 1534 int amdgpu_dpm_get_dpm_clock_table(struct amdgpu_device *adev, 1535 struct dpm_clocks *clock_table) 1536 { 1537 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 1538 int ret = 0; 1539 1540 if (!pp_funcs->get_dpm_clock_table) 1541 return -EOPNOTSUPP; 1542 1543 mutex_lock(&adev->pm.mutex); 1544 ret = pp_funcs->get_dpm_clock_table(adev->powerplay.pp_handle, 1545 clock_table); 1546 mutex_unlock(&adev->pm.mutex); 1547 1548 return ret; 1549 } 1550