1e098bc96SEvan Quan /* 2e098bc96SEvan Quan * Copyright 2011 Advanced Micro Devices, Inc. 3e098bc96SEvan Quan * 4e098bc96SEvan Quan * Permission is hereby granted, free of charge, to any person obtaining a 5e098bc96SEvan Quan * copy of this software and associated documentation files (the "Software"), 6e098bc96SEvan Quan * to deal in the Software without restriction, including without limitation 7e098bc96SEvan Quan * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8e098bc96SEvan Quan * and/or sell copies of the Software, and to permit persons to whom the 9e098bc96SEvan Quan * Software is furnished to do so, subject to the following conditions: 10e098bc96SEvan Quan * 11e098bc96SEvan Quan * The above copyright notice and this permission notice shall be included in 12e098bc96SEvan Quan * all copies or substantial portions of the Software. 13e098bc96SEvan Quan * 14e098bc96SEvan Quan * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15e098bc96SEvan Quan * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16e098bc96SEvan Quan * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17e098bc96SEvan Quan * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18e098bc96SEvan Quan * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19e098bc96SEvan Quan * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20e098bc96SEvan Quan * OTHER DEALINGS IN THE SOFTWARE. 21e098bc96SEvan Quan * 22e098bc96SEvan Quan * Authors: Alex Deucher 23e098bc96SEvan Quan */ 24e098bc96SEvan Quan 25e098bc96SEvan Quan #include "amdgpu.h" 26e098bc96SEvan Quan #include "amdgpu_atombios.h" 27e098bc96SEvan Quan #include "amdgpu_i2c.h" 28e098bc96SEvan Quan #include "amdgpu_dpm.h" 29e098bc96SEvan Quan #include "atom.h" 30e098bc96SEvan Quan #include "amd_pcie.h" 31e098bc96SEvan Quan #include "amdgpu_display.h" 32e098bc96SEvan Quan #include "hwmgr.h" 33e098bc96SEvan Quan #include <linux/power_supply.h> 34ebfc2533SEvan Quan #include "amdgpu_smu.h" 35e098bc96SEvan Quan 36d4481576SEvan Quan #define amdgpu_dpm_enable_bapm(adev, e) \ 37d4481576SEvan Quan ((adev)->powerplay.pp_funcs->enable_bapm((adev)->powerplay.pp_handle, (e))) 38d4481576SEvan Quan 39e098bc96SEvan Quan int amdgpu_dpm_get_sclk(struct amdgpu_device *adev, bool low) 40e098bc96SEvan Quan { 41bc7d6c12SDarren Powell const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 423712e7a4SEvan Quan int ret = 0; 43e098bc96SEvan Quan 443712e7a4SEvan Quan if (!pp_funcs->get_sclk) 453712e7a4SEvan Quan return 0; 463712e7a4SEvan Quan 473712e7a4SEvan Quan mutex_lock(&adev->pm.mutex); 483712e7a4SEvan Quan ret = pp_funcs->get_sclk((adev)->powerplay.pp_handle, 493712e7a4SEvan Quan low); 503712e7a4SEvan Quan mutex_unlock(&adev->pm.mutex); 513712e7a4SEvan Quan 523712e7a4SEvan Quan return ret; 53e098bc96SEvan Quan } 54e098bc96SEvan Quan 55e098bc96SEvan Quan int amdgpu_dpm_get_mclk(struct amdgpu_device *adev, bool low) 56e098bc96SEvan Quan { 57bc7d6c12SDarren Powell const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 583712e7a4SEvan Quan int ret = 0; 59e098bc96SEvan Quan 603712e7a4SEvan Quan if (!pp_funcs->get_mclk) 613712e7a4SEvan Quan return 0; 623712e7a4SEvan Quan 633712e7a4SEvan Quan mutex_lock(&adev->pm.mutex); 643712e7a4SEvan Quan ret = pp_funcs->get_mclk((adev)->powerplay.pp_handle, 653712e7a4SEvan Quan low); 663712e7a4SEvan Quan mutex_unlock(&adev->pm.mutex); 673712e7a4SEvan Quan 683712e7a4SEvan Quan return ret; 69e098bc96SEvan Quan } 70e098bc96SEvan Quan 71e098bc96SEvan Quan int amdgpu_dpm_set_powergating_by_smu(struct amdgpu_device *adev, uint32_t block_type, bool gate) 72e098bc96SEvan Quan { 73e098bc96SEvan Quan int ret = 0; 74bc7d6c12SDarren Powell const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 756ee27ee2SEvan Quan enum ip_power_state pwr_state = gate ? POWER_STATE_OFF : POWER_STATE_ON; 766ee27ee2SEvan Quan 776ee27ee2SEvan Quan if (atomic_read(&adev->pm.pwr_state[block_type]) == pwr_state) { 786ee27ee2SEvan Quan dev_dbg(adev->dev, "IP block%d already in the target %s state!", 796ee27ee2SEvan Quan block_type, gate ? "gate" : "ungate"); 806ee27ee2SEvan Quan return 0; 816ee27ee2SEvan Quan } 82e098bc96SEvan Quan 833712e7a4SEvan Quan mutex_lock(&adev->pm.mutex); 843712e7a4SEvan Quan 85e098bc96SEvan Quan switch (block_type) { 86e098bc96SEvan Quan case AMD_IP_BLOCK_TYPE_UVD: 87e098bc96SEvan Quan case AMD_IP_BLOCK_TYPE_VCE: 88e098bc96SEvan Quan case AMD_IP_BLOCK_TYPE_GFX: 89e098bc96SEvan Quan case AMD_IP_BLOCK_TYPE_VCN: 90e098bc96SEvan Quan case AMD_IP_BLOCK_TYPE_SDMA: 91e098bc96SEvan Quan case AMD_IP_BLOCK_TYPE_JPEG: 92e098bc96SEvan Quan case AMD_IP_BLOCK_TYPE_GMC: 93e098bc96SEvan Quan case AMD_IP_BLOCK_TYPE_ACP: 943712e7a4SEvan Quan if (pp_funcs && pp_funcs->set_powergating_by_smu) 95bc7d6c12SDarren Powell ret = (pp_funcs->set_powergating_by_smu( 96e098bc96SEvan Quan (adev)->powerplay.pp_handle, block_type, gate)); 97e098bc96SEvan Quan break; 98e098bc96SEvan Quan default: 99e098bc96SEvan Quan break; 100e098bc96SEvan Quan } 101e098bc96SEvan Quan 1026ee27ee2SEvan Quan if (!ret) 1036ee27ee2SEvan Quan atomic_set(&adev->pm.pwr_state[block_type], pwr_state); 1046ee27ee2SEvan Quan 1053712e7a4SEvan Quan mutex_unlock(&adev->pm.mutex); 1063712e7a4SEvan Quan 107e098bc96SEvan Quan return ret; 108e098bc96SEvan Quan } 109e098bc96SEvan Quan 110e098bc96SEvan Quan int amdgpu_dpm_baco_enter(struct amdgpu_device *adev) 111e098bc96SEvan Quan { 112e098bc96SEvan Quan const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 113e098bc96SEvan Quan void *pp_handle = adev->powerplay.pp_handle; 114e098bc96SEvan Quan int ret = 0; 115e098bc96SEvan Quan 116e098bc96SEvan Quan if (!pp_funcs || !pp_funcs->set_asic_baco_state) 117e098bc96SEvan Quan return -ENOENT; 118e098bc96SEvan Quan 1193712e7a4SEvan Quan mutex_lock(&adev->pm.mutex); 1203712e7a4SEvan Quan 121e098bc96SEvan Quan /* enter BACO state */ 122e098bc96SEvan Quan ret = pp_funcs->set_asic_baco_state(pp_handle, 1); 123e098bc96SEvan Quan 1243712e7a4SEvan Quan mutex_unlock(&adev->pm.mutex); 1253712e7a4SEvan Quan 126e098bc96SEvan Quan return ret; 127e098bc96SEvan Quan } 128e098bc96SEvan Quan 129e098bc96SEvan Quan int amdgpu_dpm_baco_exit(struct amdgpu_device *adev) 130e098bc96SEvan Quan { 131e098bc96SEvan Quan const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 132e098bc96SEvan Quan void *pp_handle = adev->powerplay.pp_handle; 133e098bc96SEvan Quan int ret = 0; 134e098bc96SEvan Quan 135e098bc96SEvan Quan if (!pp_funcs || !pp_funcs->set_asic_baco_state) 136e098bc96SEvan Quan return -ENOENT; 137e098bc96SEvan Quan 1383712e7a4SEvan Quan mutex_lock(&adev->pm.mutex); 1393712e7a4SEvan Quan 140e098bc96SEvan Quan /* exit BACO state */ 141e098bc96SEvan Quan ret = pp_funcs->set_asic_baco_state(pp_handle, 0); 142e098bc96SEvan Quan 1433712e7a4SEvan Quan mutex_unlock(&adev->pm.mutex); 1443712e7a4SEvan Quan 145e098bc96SEvan Quan return ret; 146e098bc96SEvan Quan } 147e098bc96SEvan Quan 148e098bc96SEvan Quan int amdgpu_dpm_set_mp1_state(struct amdgpu_device *adev, 149e098bc96SEvan Quan enum pp_mp1_state mp1_state) 150e098bc96SEvan Quan { 151e098bc96SEvan Quan int ret = 0; 152bab0f602SDarren Powell const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 153e098bc96SEvan Quan 154bab0f602SDarren Powell if (pp_funcs && pp_funcs->set_mp1_state) { 1553712e7a4SEvan Quan mutex_lock(&adev->pm.mutex); 1563712e7a4SEvan Quan 157bab0f602SDarren Powell ret = pp_funcs->set_mp1_state( 158e098bc96SEvan Quan adev->powerplay.pp_handle, 159e098bc96SEvan Quan mp1_state); 1603712e7a4SEvan Quan 1613712e7a4SEvan Quan mutex_unlock(&adev->pm.mutex); 162e098bc96SEvan Quan } 163e098bc96SEvan Quan 164e098bc96SEvan Quan return ret; 165e098bc96SEvan Quan } 166e098bc96SEvan Quan 167e098bc96SEvan Quan bool amdgpu_dpm_is_baco_supported(struct amdgpu_device *adev) 168e098bc96SEvan Quan { 169e098bc96SEvan Quan const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 170e098bc96SEvan Quan void *pp_handle = adev->powerplay.pp_handle; 171e098bc96SEvan Quan bool baco_cap; 1723712e7a4SEvan Quan int ret = 0; 173e098bc96SEvan Quan 174e098bc96SEvan Quan if (!pp_funcs || !pp_funcs->get_asic_baco_capability) 175e098bc96SEvan Quan return false; 176e098bc96SEvan Quan 1773712e7a4SEvan Quan mutex_lock(&adev->pm.mutex); 178e098bc96SEvan Quan 1793712e7a4SEvan Quan ret = pp_funcs->get_asic_baco_capability(pp_handle, 1803712e7a4SEvan Quan &baco_cap); 1813712e7a4SEvan Quan 1823712e7a4SEvan Quan mutex_unlock(&adev->pm.mutex); 1833712e7a4SEvan Quan 1843712e7a4SEvan Quan return ret ? false : baco_cap; 185e098bc96SEvan Quan } 186e098bc96SEvan Quan 187e098bc96SEvan Quan int amdgpu_dpm_mode2_reset(struct amdgpu_device *adev) 188e098bc96SEvan Quan { 189e098bc96SEvan Quan const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 190e098bc96SEvan Quan void *pp_handle = adev->powerplay.pp_handle; 1913712e7a4SEvan Quan int ret = 0; 192e098bc96SEvan Quan 193e098bc96SEvan Quan if (!pp_funcs || !pp_funcs->asic_reset_mode_2) 194e098bc96SEvan Quan return -ENOENT; 195e098bc96SEvan Quan 1963712e7a4SEvan Quan mutex_lock(&adev->pm.mutex); 1973712e7a4SEvan Quan 1983712e7a4SEvan Quan ret = pp_funcs->asic_reset_mode_2(pp_handle); 1993712e7a4SEvan Quan 2003712e7a4SEvan Quan mutex_unlock(&adev->pm.mutex); 2013712e7a4SEvan Quan 2023712e7a4SEvan Quan return ret; 203e098bc96SEvan Quan } 204e098bc96SEvan Quan 205e098bc96SEvan Quan int amdgpu_dpm_baco_reset(struct amdgpu_device *adev) 206e098bc96SEvan Quan { 207e098bc96SEvan Quan const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 208e098bc96SEvan Quan void *pp_handle = adev->powerplay.pp_handle; 209e098bc96SEvan Quan int ret = 0; 210e098bc96SEvan Quan 2119ab5001aSDarren Powell if (!pp_funcs || !pp_funcs->set_asic_baco_state) 212e098bc96SEvan Quan return -ENOENT; 213e098bc96SEvan Quan 2143712e7a4SEvan Quan mutex_lock(&adev->pm.mutex); 2153712e7a4SEvan Quan 216e098bc96SEvan Quan /* enter BACO state */ 217e098bc96SEvan Quan ret = pp_funcs->set_asic_baco_state(pp_handle, 1); 218e098bc96SEvan Quan if (ret) 2193712e7a4SEvan Quan goto out; 220e098bc96SEvan Quan 221e098bc96SEvan Quan /* exit BACO state */ 222e098bc96SEvan Quan ret = pp_funcs->set_asic_baco_state(pp_handle, 0); 223e098bc96SEvan Quan 2243712e7a4SEvan Quan out: 2253712e7a4SEvan Quan mutex_unlock(&adev->pm.mutex); 2263712e7a4SEvan Quan return ret; 227e098bc96SEvan Quan } 228e098bc96SEvan Quan 229e098bc96SEvan Quan bool amdgpu_dpm_is_mode1_reset_supported(struct amdgpu_device *adev) 230e098bc96SEvan Quan { 231ebfc2533SEvan Quan struct smu_context *smu = adev->powerplay.pp_handle; 2323712e7a4SEvan Quan bool support_mode1_reset = false; 233e098bc96SEvan Quan 2343712e7a4SEvan Quan if (is_support_sw_smu(adev)) { 2353712e7a4SEvan Quan mutex_lock(&adev->pm.mutex); 2363712e7a4SEvan Quan support_mode1_reset = smu_mode1_reset_is_support(smu); 2373712e7a4SEvan Quan mutex_unlock(&adev->pm.mutex); 2383712e7a4SEvan Quan } 239e098bc96SEvan Quan 2403712e7a4SEvan Quan return support_mode1_reset; 241e098bc96SEvan Quan } 242e098bc96SEvan Quan 243e098bc96SEvan Quan int amdgpu_dpm_mode1_reset(struct amdgpu_device *adev) 244e098bc96SEvan Quan { 245ebfc2533SEvan Quan struct smu_context *smu = adev->powerplay.pp_handle; 2463712e7a4SEvan Quan int ret = -EOPNOTSUPP; 247e098bc96SEvan Quan 2483712e7a4SEvan Quan if (is_support_sw_smu(adev)) { 2493712e7a4SEvan Quan mutex_lock(&adev->pm.mutex); 2503712e7a4SEvan Quan ret = smu_mode1_reset(smu); 2513712e7a4SEvan Quan mutex_unlock(&adev->pm.mutex); 2523712e7a4SEvan Quan } 253e098bc96SEvan Quan 2543712e7a4SEvan Quan return ret; 255e098bc96SEvan Quan } 256e098bc96SEvan Quan 257e098bc96SEvan Quan int amdgpu_dpm_switch_power_profile(struct amdgpu_device *adev, 258e098bc96SEvan Quan enum PP_SMC_POWER_PROFILE type, 259e098bc96SEvan Quan bool en) 260e098bc96SEvan Quan { 261bab0f602SDarren Powell const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 262e098bc96SEvan Quan int ret = 0; 263e098bc96SEvan Quan 2647cf7a392SJingwen Chen if (amdgpu_sriov_vf(adev)) 2657cf7a392SJingwen Chen return 0; 2667cf7a392SJingwen Chen 2673712e7a4SEvan Quan if (pp_funcs && pp_funcs->switch_power_profile) { 2683712e7a4SEvan Quan mutex_lock(&adev->pm.mutex); 269bab0f602SDarren Powell ret = pp_funcs->switch_power_profile( 270e098bc96SEvan Quan adev->powerplay.pp_handle, type, en); 2713712e7a4SEvan Quan mutex_unlock(&adev->pm.mutex); 2723712e7a4SEvan Quan } 273e098bc96SEvan Quan 274e098bc96SEvan Quan return ret; 275e098bc96SEvan Quan } 276e098bc96SEvan Quan 277e098bc96SEvan Quan int amdgpu_dpm_set_xgmi_pstate(struct amdgpu_device *adev, 278e098bc96SEvan Quan uint32_t pstate) 279e098bc96SEvan Quan { 280bab0f602SDarren Powell const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 281e098bc96SEvan Quan int ret = 0; 282e098bc96SEvan Quan 2833712e7a4SEvan Quan if (pp_funcs && pp_funcs->set_xgmi_pstate) { 2843712e7a4SEvan Quan mutex_lock(&adev->pm.mutex); 285bab0f602SDarren Powell ret = pp_funcs->set_xgmi_pstate(adev->powerplay.pp_handle, 286e098bc96SEvan Quan pstate); 2873712e7a4SEvan Quan mutex_unlock(&adev->pm.mutex); 2883712e7a4SEvan Quan } 289e098bc96SEvan Quan 290e098bc96SEvan Quan return ret; 291e098bc96SEvan Quan } 292e098bc96SEvan Quan 293e098bc96SEvan Quan int amdgpu_dpm_set_df_cstate(struct amdgpu_device *adev, 294e098bc96SEvan Quan uint32_t cstate) 295e098bc96SEvan Quan { 296e098bc96SEvan Quan int ret = 0; 297e098bc96SEvan Quan const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 298e098bc96SEvan Quan void *pp_handle = adev->powerplay.pp_handle; 299e098bc96SEvan Quan 3003712e7a4SEvan Quan if (pp_funcs && pp_funcs->set_df_cstate) { 3013712e7a4SEvan Quan mutex_lock(&adev->pm.mutex); 302e098bc96SEvan Quan ret = pp_funcs->set_df_cstate(pp_handle, cstate); 3033712e7a4SEvan Quan mutex_unlock(&adev->pm.mutex); 3043712e7a4SEvan Quan } 305e098bc96SEvan Quan 306e098bc96SEvan Quan return ret; 307e098bc96SEvan Quan } 308e098bc96SEvan Quan 309e098bc96SEvan Quan int amdgpu_dpm_allow_xgmi_power_down(struct amdgpu_device *adev, bool en) 310e098bc96SEvan Quan { 311ebfc2533SEvan Quan struct smu_context *smu = adev->powerplay.pp_handle; 3123712e7a4SEvan Quan int ret = 0; 313e098bc96SEvan Quan 3143712e7a4SEvan Quan if (is_support_sw_smu(adev)) { 3153712e7a4SEvan Quan mutex_lock(&adev->pm.mutex); 3163712e7a4SEvan Quan ret = smu_allow_xgmi_power_down(smu, en); 3173712e7a4SEvan Quan mutex_unlock(&adev->pm.mutex); 3183712e7a4SEvan Quan } 319e098bc96SEvan Quan 3203712e7a4SEvan Quan return ret; 321e098bc96SEvan Quan } 322e098bc96SEvan Quan 323e098bc96SEvan Quan int amdgpu_dpm_enable_mgpu_fan_boost(struct amdgpu_device *adev) 324e098bc96SEvan Quan { 325e098bc96SEvan Quan void *pp_handle = adev->powerplay.pp_handle; 326e098bc96SEvan Quan const struct amd_pm_funcs *pp_funcs = 327e098bc96SEvan Quan adev->powerplay.pp_funcs; 328e098bc96SEvan Quan int ret = 0; 329e098bc96SEvan Quan 3303712e7a4SEvan Quan if (pp_funcs && pp_funcs->enable_mgpu_fan_boost) { 3313712e7a4SEvan Quan mutex_lock(&adev->pm.mutex); 332e098bc96SEvan Quan ret = pp_funcs->enable_mgpu_fan_boost(pp_handle); 3333712e7a4SEvan Quan mutex_unlock(&adev->pm.mutex); 3343712e7a4SEvan Quan } 335e098bc96SEvan Quan 336e098bc96SEvan Quan return ret; 337e098bc96SEvan Quan } 338e098bc96SEvan Quan 339e098bc96SEvan Quan int amdgpu_dpm_set_clockgating_by_smu(struct amdgpu_device *adev, 340e098bc96SEvan Quan uint32_t msg_id) 341e098bc96SEvan Quan { 342e098bc96SEvan Quan void *pp_handle = adev->powerplay.pp_handle; 343e098bc96SEvan Quan const struct amd_pm_funcs *pp_funcs = 344e098bc96SEvan Quan adev->powerplay.pp_funcs; 345e098bc96SEvan Quan int ret = 0; 346e098bc96SEvan Quan 3473712e7a4SEvan Quan if (pp_funcs && pp_funcs->set_clockgating_by_smu) { 3483712e7a4SEvan Quan mutex_lock(&adev->pm.mutex); 349e098bc96SEvan Quan ret = pp_funcs->set_clockgating_by_smu(pp_handle, 350e098bc96SEvan Quan msg_id); 3513712e7a4SEvan Quan mutex_unlock(&adev->pm.mutex); 3523712e7a4SEvan Quan } 353e098bc96SEvan Quan 354e098bc96SEvan Quan return ret; 355e098bc96SEvan Quan } 356e098bc96SEvan Quan 357e098bc96SEvan Quan int amdgpu_dpm_smu_i2c_bus_access(struct amdgpu_device *adev, 358e098bc96SEvan Quan bool acquire) 359e098bc96SEvan Quan { 360e098bc96SEvan Quan void *pp_handle = adev->powerplay.pp_handle; 361e098bc96SEvan Quan const struct amd_pm_funcs *pp_funcs = 362e098bc96SEvan Quan adev->powerplay.pp_funcs; 363e098bc96SEvan Quan int ret = -EOPNOTSUPP; 364e098bc96SEvan Quan 3653712e7a4SEvan Quan if (pp_funcs && pp_funcs->smu_i2c_bus_access) { 3663712e7a4SEvan Quan mutex_lock(&adev->pm.mutex); 367e098bc96SEvan Quan ret = pp_funcs->smu_i2c_bus_access(pp_handle, 368e098bc96SEvan Quan acquire); 3693712e7a4SEvan Quan mutex_unlock(&adev->pm.mutex); 3703712e7a4SEvan Quan } 371e098bc96SEvan Quan 372e098bc96SEvan Quan return ret; 373e098bc96SEvan Quan } 374e098bc96SEvan Quan 375e098bc96SEvan Quan void amdgpu_pm_acpi_event_handler(struct amdgpu_device *adev) 376e098bc96SEvan Quan { 377e098bc96SEvan Quan if (adev->pm.dpm_enabled) { 378e098bc96SEvan Quan mutex_lock(&adev->pm.mutex); 379e098bc96SEvan Quan if (power_supply_is_system_supplied() > 0) 380e098bc96SEvan Quan adev->pm.ac_power = true; 381e098bc96SEvan Quan else 382e098bc96SEvan Quan adev->pm.ac_power = false; 3833712e7a4SEvan Quan 384e098bc96SEvan Quan if (adev->powerplay.pp_funcs && 385e098bc96SEvan Quan adev->powerplay.pp_funcs->enable_bapm) 386e098bc96SEvan Quan amdgpu_dpm_enable_bapm(adev, adev->pm.ac_power); 387e098bc96SEvan Quan 388e098bc96SEvan Quan if (is_support_sw_smu(adev)) 389ebfc2533SEvan Quan smu_set_ac_dc(adev->powerplay.pp_handle); 3903712e7a4SEvan Quan 3913712e7a4SEvan Quan mutex_unlock(&adev->pm.mutex); 392e098bc96SEvan Quan } 393e098bc96SEvan Quan } 394e098bc96SEvan Quan 395e098bc96SEvan Quan int amdgpu_dpm_read_sensor(struct amdgpu_device *adev, enum amd_pp_sensors sensor, 396e098bc96SEvan Quan void *data, uint32_t *size) 397e098bc96SEvan Quan { 3989ab5001aSDarren Powell const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 3993712e7a4SEvan Quan int ret = -EINVAL; 400e098bc96SEvan Quan 401e098bc96SEvan Quan if (!data || !size) 402e098bc96SEvan Quan return -EINVAL; 403e098bc96SEvan Quan 4043712e7a4SEvan Quan if (pp_funcs && pp_funcs->read_sensor) { 4053712e7a4SEvan Quan mutex_lock(&adev->pm.mutex); 4063712e7a4SEvan Quan ret = pp_funcs->read_sensor(adev->powerplay.pp_handle, 4073712e7a4SEvan Quan sensor, 4083712e7a4SEvan Quan data, 4093712e7a4SEvan Quan size); 4103712e7a4SEvan Quan mutex_unlock(&adev->pm.mutex); 4113712e7a4SEvan Quan } 412e098bc96SEvan Quan 413e098bc96SEvan Quan return ret; 414e098bc96SEvan Quan } 415e098bc96SEvan Quan 41684176663SEvan Quan void amdgpu_dpm_compute_clocks(struct amdgpu_device *adev) 417e098bc96SEvan Quan { 4186ddbd37fSEvan Quan const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 419e098bc96SEvan Quan 420e098bc96SEvan Quan if (!adev->pm.dpm_enabled) 421e098bc96SEvan Quan return; 422e098bc96SEvan Quan 4236ddbd37fSEvan Quan if (!pp_funcs->pm_compute_clocks) 4246ddbd37fSEvan Quan return; 425e098bc96SEvan Quan 4263712e7a4SEvan Quan mutex_lock(&adev->pm.mutex); 4276ddbd37fSEvan Quan pp_funcs->pm_compute_clocks(adev->powerplay.pp_handle); 4283712e7a4SEvan Quan mutex_unlock(&adev->pm.mutex); 429e098bc96SEvan Quan } 430e098bc96SEvan Quan 431e098bc96SEvan Quan void amdgpu_dpm_enable_uvd(struct amdgpu_device *adev, bool enable) 432e098bc96SEvan Quan { 433e098bc96SEvan Quan int ret = 0; 434e098bc96SEvan Quan 435e098bc96SEvan Quan ret = amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_UVD, !enable); 436e098bc96SEvan Quan if (ret) 437e098bc96SEvan Quan DRM_ERROR("Dpm %s uvd failed, ret = %d. \n", 438e098bc96SEvan Quan enable ? "enable" : "disable", ret); 439e098bc96SEvan Quan } 440e098bc96SEvan Quan 441e098bc96SEvan Quan void amdgpu_dpm_enable_vce(struct amdgpu_device *adev, bool enable) 442e098bc96SEvan Quan { 443e098bc96SEvan Quan int ret = 0; 444e098bc96SEvan Quan 445e098bc96SEvan Quan ret = amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_VCE, !enable); 446e098bc96SEvan Quan if (ret) 447e098bc96SEvan Quan DRM_ERROR("Dpm %s vce failed, ret = %d. \n", 448e098bc96SEvan Quan enable ? "enable" : "disable", ret); 449e098bc96SEvan Quan } 450e098bc96SEvan Quan 451e098bc96SEvan Quan void amdgpu_dpm_enable_jpeg(struct amdgpu_device *adev, bool enable) 452e098bc96SEvan Quan { 453e098bc96SEvan Quan int ret = 0; 454e098bc96SEvan Quan 455e098bc96SEvan Quan ret = amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_JPEG, !enable); 456e098bc96SEvan Quan if (ret) 457e098bc96SEvan Quan DRM_ERROR("Dpm %s jpeg failed, ret = %d. \n", 458e098bc96SEvan Quan enable ? "enable" : "disable", ret); 459e098bc96SEvan Quan } 460e098bc96SEvan Quan 461e098bc96SEvan Quan int amdgpu_pm_load_smu_firmware(struct amdgpu_device *adev, uint32_t *smu_version) 462e098bc96SEvan Quan { 4633712e7a4SEvan Quan const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 4643712e7a4SEvan Quan int r = 0; 465e098bc96SEvan Quan 4661613f346SFlora Cui if (!pp_funcs || !pp_funcs->load_firmware) 4673712e7a4SEvan Quan return 0; 4683712e7a4SEvan Quan 4693712e7a4SEvan Quan mutex_lock(&adev->pm.mutex); 4703712e7a4SEvan Quan r = pp_funcs->load_firmware(adev->powerplay.pp_handle); 471e098bc96SEvan Quan if (r) { 472e098bc96SEvan Quan pr_err("smu firmware loading failed\n"); 4733712e7a4SEvan Quan goto out; 474e098bc96SEvan Quan } 4752e4b2f7bSEvan Quan 4762e4b2f7bSEvan Quan if (smu_version) 477e098bc96SEvan Quan *smu_version = adev->pm.fw_version; 4782e4b2f7bSEvan Quan 4793712e7a4SEvan Quan out: 4803712e7a4SEvan Quan mutex_unlock(&adev->pm.mutex); 4813712e7a4SEvan Quan return r; 482e098bc96SEvan Quan } 483bc143d8bSEvan Quan 484bc143d8bSEvan Quan int amdgpu_dpm_handle_passthrough_sbr(struct amdgpu_device *adev, bool enable) 485bc143d8bSEvan Quan { 4863712e7a4SEvan Quan int ret = 0; 4873712e7a4SEvan Quan 4883712e7a4SEvan Quan if (is_support_sw_smu(adev)) { 4893712e7a4SEvan Quan mutex_lock(&adev->pm.mutex); 4903712e7a4SEvan Quan ret = smu_handle_passthrough_sbr(adev->powerplay.pp_handle, 4913712e7a4SEvan Quan enable); 4923712e7a4SEvan Quan mutex_unlock(&adev->pm.mutex); 4933712e7a4SEvan Quan } 4943712e7a4SEvan Quan 4953712e7a4SEvan Quan return ret; 496bc143d8bSEvan Quan } 497bc143d8bSEvan Quan 498bc143d8bSEvan Quan int amdgpu_dpm_send_hbm_bad_pages_num(struct amdgpu_device *adev, uint32_t size) 499bc143d8bSEvan Quan { 500ebfc2533SEvan Quan struct smu_context *smu = adev->powerplay.pp_handle; 5013712e7a4SEvan Quan int ret = 0; 502ebfc2533SEvan Quan 5033712e7a4SEvan Quan mutex_lock(&adev->pm.mutex); 5043712e7a4SEvan Quan ret = smu_send_hbm_bad_pages_num(smu, size); 5053712e7a4SEvan Quan mutex_unlock(&adev->pm.mutex); 5063712e7a4SEvan Quan 5073712e7a4SEvan Quan return ret; 508bc143d8bSEvan Quan } 509bc143d8bSEvan Quan 510*d510eccfSStanley.Yang int amdgpu_dpm_send_hbm_bad_channel_flag(struct amdgpu_device *adev, uint32_t size) 511*d510eccfSStanley.Yang { 512*d510eccfSStanley.Yang struct smu_context *smu = adev->powerplay.pp_handle; 513*d510eccfSStanley.Yang int ret = 0; 514*d510eccfSStanley.Yang 515*d510eccfSStanley.Yang mutex_lock(&adev->pm.mutex); 516*d510eccfSStanley.Yang ret = smu_send_hbm_bad_channel_flag(smu, size); 517*d510eccfSStanley.Yang mutex_unlock(&adev->pm.mutex); 518*d510eccfSStanley.Yang 519*d510eccfSStanley.Yang return ret; 520*d510eccfSStanley.Yang } 521*d510eccfSStanley.Yang 522bc143d8bSEvan Quan int amdgpu_dpm_get_dpm_freq_range(struct amdgpu_device *adev, 523bc143d8bSEvan Quan enum pp_clock_type type, 524bc143d8bSEvan Quan uint32_t *min, 525bc143d8bSEvan Quan uint32_t *max) 526bc143d8bSEvan Quan { 5273712e7a4SEvan Quan int ret = 0; 5283712e7a4SEvan Quan 5293712e7a4SEvan Quan if (type != PP_SCLK) 5303712e7a4SEvan Quan return -EINVAL; 5313712e7a4SEvan Quan 532bc143d8bSEvan Quan if (!is_support_sw_smu(adev)) 533bc143d8bSEvan Quan return -EOPNOTSUPP; 534bc143d8bSEvan Quan 5353712e7a4SEvan Quan mutex_lock(&adev->pm.mutex); 5363712e7a4SEvan Quan ret = smu_get_dpm_freq_range(adev->powerplay.pp_handle, 5373712e7a4SEvan Quan SMU_SCLK, 5383712e7a4SEvan Quan min, 5393712e7a4SEvan Quan max); 5403712e7a4SEvan Quan mutex_unlock(&adev->pm.mutex); 5413712e7a4SEvan Quan 5423712e7a4SEvan Quan return ret; 543bc143d8bSEvan Quan } 544bc143d8bSEvan Quan 545bc143d8bSEvan Quan int amdgpu_dpm_set_soft_freq_range(struct amdgpu_device *adev, 546bc143d8bSEvan Quan enum pp_clock_type type, 547bc143d8bSEvan Quan uint32_t min, 548bc143d8bSEvan Quan uint32_t max) 549bc143d8bSEvan Quan { 550ebfc2533SEvan Quan struct smu_context *smu = adev->powerplay.pp_handle; 5513712e7a4SEvan Quan int ret = 0; 5523712e7a4SEvan Quan 5533712e7a4SEvan Quan if (type != PP_SCLK) 5543712e7a4SEvan Quan return -EINVAL; 555ebfc2533SEvan Quan 556bc143d8bSEvan Quan if (!is_support_sw_smu(adev)) 557bc143d8bSEvan Quan return -EOPNOTSUPP; 558bc143d8bSEvan Quan 5593712e7a4SEvan Quan mutex_lock(&adev->pm.mutex); 5603712e7a4SEvan Quan ret = smu_set_soft_freq_range(smu, 5613712e7a4SEvan Quan SMU_SCLK, 5623712e7a4SEvan Quan min, 5633712e7a4SEvan Quan max); 5643712e7a4SEvan Quan mutex_unlock(&adev->pm.mutex); 5653712e7a4SEvan Quan 5663712e7a4SEvan Quan return ret; 567bc143d8bSEvan Quan } 568bc143d8bSEvan Quan 56913f5dbd6SEvan Quan int amdgpu_dpm_write_watermarks_table(struct amdgpu_device *adev) 57013f5dbd6SEvan Quan { 571ebfc2533SEvan Quan struct smu_context *smu = adev->powerplay.pp_handle; 5723712e7a4SEvan Quan int ret = 0; 573ebfc2533SEvan Quan 57413f5dbd6SEvan Quan if (!is_support_sw_smu(adev)) 57513f5dbd6SEvan Quan return 0; 57613f5dbd6SEvan Quan 5773712e7a4SEvan Quan mutex_lock(&adev->pm.mutex); 5783712e7a4SEvan Quan ret = smu_write_watermarks_table(smu); 5793712e7a4SEvan Quan mutex_unlock(&adev->pm.mutex); 5803712e7a4SEvan Quan 5813712e7a4SEvan Quan return ret; 58213f5dbd6SEvan Quan } 58313f5dbd6SEvan Quan 584bc143d8bSEvan Quan int amdgpu_dpm_wait_for_event(struct amdgpu_device *adev, 585bc143d8bSEvan Quan enum smu_event_type event, 586bc143d8bSEvan Quan uint64_t event_arg) 587bc143d8bSEvan Quan { 588ebfc2533SEvan Quan struct smu_context *smu = adev->powerplay.pp_handle; 5893712e7a4SEvan Quan int ret = 0; 590ebfc2533SEvan Quan 591bc143d8bSEvan Quan if (!is_support_sw_smu(adev)) 592bc143d8bSEvan Quan return -EOPNOTSUPP; 593bc143d8bSEvan Quan 5943712e7a4SEvan Quan mutex_lock(&adev->pm.mutex); 5953712e7a4SEvan Quan ret = smu_wait_for_event(smu, event, event_arg); 5963712e7a4SEvan Quan mutex_unlock(&adev->pm.mutex); 5973712e7a4SEvan Quan 5983712e7a4SEvan Quan return ret; 599bc143d8bSEvan Quan } 600bc143d8bSEvan Quan 601bc143d8bSEvan Quan int amdgpu_dpm_get_status_gfxoff(struct amdgpu_device *adev, uint32_t *value) 602bc143d8bSEvan Quan { 603ebfc2533SEvan Quan struct smu_context *smu = adev->powerplay.pp_handle; 6043712e7a4SEvan Quan int ret = 0; 605ebfc2533SEvan Quan 606bc143d8bSEvan Quan if (!is_support_sw_smu(adev)) 607bc143d8bSEvan Quan return -EOPNOTSUPP; 608bc143d8bSEvan Quan 6093712e7a4SEvan Quan mutex_lock(&adev->pm.mutex); 6103712e7a4SEvan Quan ret = smu_get_status_gfxoff(smu, value); 6113712e7a4SEvan Quan mutex_unlock(&adev->pm.mutex); 6123712e7a4SEvan Quan 6133712e7a4SEvan Quan return ret; 614bc143d8bSEvan Quan } 615bc143d8bSEvan Quan 616bc143d8bSEvan Quan uint64_t amdgpu_dpm_get_thermal_throttling_counter(struct amdgpu_device *adev) 617bc143d8bSEvan Quan { 618ebfc2533SEvan Quan struct smu_context *smu = adev->powerplay.pp_handle; 619ebfc2533SEvan Quan 6203712e7a4SEvan Quan if (!is_support_sw_smu(adev)) 6213712e7a4SEvan Quan return 0; 6223712e7a4SEvan Quan 623ebfc2533SEvan Quan return atomic64_read(&smu->throttle_int_counter); 624bc143d8bSEvan Quan } 625bc143d8bSEvan Quan 626bc143d8bSEvan Quan /* amdgpu_dpm_gfx_state_change - Handle gfx power state change set 627bc143d8bSEvan Quan * @adev: amdgpu_device pointer 628bc143d8bSEvan Quan * @state: gfx power state(1 -sGpuChangeState_D0Entry and 2 -sGpuChangeState_D3Entry) 629bc143d8bSEvan Quan * 630bc143d8bSEvan Quan */ 631bc143d8bSEvan Quan void amdgpu_dpm_gfx_state_change(struct amdgpu_device *adev, 632bc143d8bSEvan Quan enum gfx_change_state state) 633bc143d8bSEvan Quan { 634bc143d8bSEvan Quan mutex_lock(&adev->pm.mutex); 635bc143d8bSEvan Quan if (adev->powerplay.pp_funcs && 636bc143d8bSEvan Quan adev->powerplay.pp_funcs->gfx_state_change_set) 637bc143d8bSEvan Quan ((adev)->powerplay.pp_funcs->gfx_state_change_set( 638bc143d8bSEvan Quan (adev)->powerplay.pp_handle, state)); 639bc143d8bSEvan Quan mutex_unlock(&adev->pm.mutex); 640bc143d8bSEvan Quan } 641bc143d8bSEvan Quan 642bc143d8bSEvan Quan int amdgpu_dpm_get_ecc_info(struct amdgpu_device *adev, 643bc143d8bSEvan Quan void *umc_ecc) 644bc143d8bSEvan Quan { 645ebfc2533SEvan Quan struct smu_context *smu = adev->powerplay.pp_handle; 646ebfc2533SEvan Quan 647bc143d8bSEvan Quan if (!is_support_sw_smu(adev)) 648bc143d8bSEvan Quan return -EOPNOTSUPP; 649bc143d8bSEvan Quan 650ebfc2533SEvan Quan return smu_get_ecc_info(smu, umc_ecc); 651bc143d8bSEvan Quan } 65279c65f3fSEvan Quan 65379c65f3fSEvan Quan struct amd_vce_state *amdgpu_dpm_get_vce_clock_state(struct amdgpu_device *adev, 65479c65f3fSEvan Quan uint32_t idx) 65579c65f3fSEvan Quan { 65679c65f3fSEvan Quan const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 6573712e7a4SEvan Quan struct amd_vce_state *vstate = NULL; 65879c65f3fSEvan Quan 65979c65f3fSEvan Quan if (!pp_funcs->get_vce_clock_state) 66079c65f3fSEvan Quan return NULL; 66179c65f3fSEvan Quan 6623712e7a4SEvan Quan mutex_lock(&adev->pm.mutex); 6633712e7a4SEvan Quan vstate = pp_funcs->get_vce_clock_state(adev->powerplay.pp_handle, 66479c65f3fSEvan Quan idx); 6653712e7a4SEvan Quan mutex_unlock(&adev->pm.mutex); 6663712e7a4SEvan Quan 6673712e7a4SEvan Quan return vstate; 66879c65f3fSEvan Quan } 66979c65f3fSEvan Quan 67079c65f3fSEvan Quan void amdgpu_dpm_get_current_power_state(struct amdgpu_device *adev, 67179c65f3fSEvan Quan enum amd_pm_state_type *state) 67279c65f3fSEvan Quan { 67379c65f3fSEvan Quan const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 67479c65f3fSEvan Quan 6753712e7a4SEvan Quan mutex_lock(&adev->pm.mutex); 6763712e7a4SEvan Quan 67779c65f3fSEvan Quan if (!pp_funcs->get_current_power_state) { 67879c65f3fSEvan Quan *state = adev->pm.dpm.user_state; 6793712e7a4SEvan Quan goto out; 68079c65f3fSEvan Quan } 68179c65f3fSEvan Quan 68279c65f3fSEvan Quan *state = pp_funcs->get_current_power_state(adev->powerplay.pp_handle); 68379c65f3fSEvan Quan if (*state < POWER_STATE_TYPE_DEFAULT || 68479c65f3fSEvan Quan *state > POWER_STATE_TYPE_INTERNAL_3DPERF) 68579c65f3fSEvan Quan *state = adev->pm.dpm.user_state; 6863712e7a4SEvan Quan 6873712e7a4SEvan Quan out: 6883712e7a4SEvan Quan mutex_unlock(&adev->pm.mutex); 68979c65f3fSEvan Quan } 69079c65f3fSEvan Quan 69179c65f3fSEvan Quan void amdgpu_dpm_set_power_state(struct amdgpu_device *adev, 69279c65f3fSEvan Quan enum amd_pm_state_type state) 69379c65f3fSEvan Quan { 6943712e7a4SEvan Quan mutex_lock(&adev->pm.mutex); 69579c65f3fSEvan Quan adev->pm.dpm.user_state = state; 6963712e7a4SEvan Quan mutex_unlock(&adev->pm.mutex); 69779c65f3fSEvan Quan 69879c65f3fSEvan Quan if (is_support_sw_smu(adev)) 69979c65f3fSEvan Quan return; 70079c65f3fSEvan Quan 70179c65f3fSEvan Quan if (amdgpu_dpm_dispatch_task(adev, 70279c65f3fSEvan Quan AMD_PP_TASK_ENABLE_USER_STATE, 70379c65f3fSEvan Quan &state) == -EOPNOTSUPP) 70484176663SEvan Quan amdgpu_dpm_compute_clocks(adev); 70579c65f3fSEvan Quan } 70679c65f3fSEvan Quan 70775513bf5SEvan Quan enum amd_dpm_forced_level amdgpu_dpm_get_performance_level(struct amdgpu_device *adev) 70879c65f3fSEvan Quan { 70979c65f3fSEvan Quan const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 71079c65f3fSEvan Quan enum amd_dpm_forced_level level; 71179c65f3fSEvan Quan 71275513bf5SEvan Quan mutex_lock(&adev->pm.mutex); 71379c65f3fSEvan Quan if (pp_funcs->get_performance_level) 71479c65f3fSEvan Quan level = pp_funcs->get_performance_level(adev->powerplay.pp_handle); 71579c65f3fSEvan Quan else 71679c65f3fSEvan Quan level = adev->pm.dpm.forced_level; 7173712e7a4SEvan Quan mutex_unlock(&adev->pm.mutex); 71879c65f3fSEvan Quan 71979c65f3fSEvan Quan return level; 72079c65f3fSEvan Quan } 72179c65f3fSEvan Quan 72279c65f3fSEvan Quan int amdgpu_dpm_force_performance_level(struct amdgpu_device *adev, 72379c65f3fSEvan Quan enum amd_dpm_forced_level level) 72479c65f3fSEvan Quan { 72579c65f3fSEvan Quan const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 72654c73b51SAlex Deucher enum amd_dpm_forced_level current_level; 72754c73b51SAlex Deucher uint32_t profile_mode_mask = AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD | 72854c73b51SAlex Deucher AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK | 72954c73b51SAlex Deucher AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK | 73054c73b51SAlex Deucher AMD_DPM_FORCED_LEVEL_PROFILE_PEAK; 73179c65f3fSEvan Quan 7323712e7a4SEvan Quan if (!pp_funcs->force_performance_level) 7333712e7a4SEvan Quan return 0; 7343712e7a4SEvan Quan 73575513bf5SEvan Quan if (adev->pm.dpm.thermal_active) 73675513bf5SEvan Quan return -EINVAL; 7373712e7a4SEvan Quan 73875513bf5SEvan Quan current_level = amdgpu_dpm_get_performance_level(adev); 73975513bf5SEvan Quan if (current_level == level) 74075513bf5SEvan Quan return 0; 74154c73b51SAlex Deucher 74254c73b51SAlex Deucher if (adev->asic_type == CHIP_RAVEN) { 74354c73b51SAlex Deucher if (!(adev->apu_flags & AMD_APU_IS_RAVEN2)) { 74454c73b51SAlex Deucher if (current_level != AMD_DPM_FORCED_LEVEL_MANUAL && 74554c73b51SAlex Deucher level == AMD_DPM_FORCED_LEVEL_MANUAL) 74654c73b51SAlex Deucher amdgpu_gfx_off_ctrl(adev, false); 74754c73b51SAlex Deucher else if (current_level == AMD_DPM_FORCED_LEVEL_MANUAL && 74854c73b51SAlex Deucher level != AMD_DPM_FORCED_LEVEL_MANUAL) 74954c73b51SAlex Deucher amdgpu_gfx_off_ctrl(adev, true); 75054c73b51SAlex Deucher } 75154c73b51SAlex Deucher } 75254c73b51SAlex Deucher 75354c73b51SAlex Deucher if (!(current_level & profile_mode_mask) && 75475513bf5SEvan Quan (level == AMD_DPM_FORCED_LEVEL_PROFILE_EXIT)) 75575513bf5SEvan Quan return -EINVAL; 75654c73b51SAlex Deucher 75754c73b51SAlex Deucher if (!(current_level & profile_mode_mask) && 75854c73b51SAlex Deucher (level & profile_mode_mask)) { 75954c73b51SAlex Deucher /* enter UMD Pstate */ 76054c73b51SAlex Deucher amdgpu_device_ip_set_powergating_state(adev, 76154c73b51SAlex Deucher AMD_IP_BLOCK_TYPE_GFX, 76254c73b51SAlex Deucher AMD_PG_STATE_UNGATE); 76354c73b51SAlex Deucher amdgpu_device_ip_set_clockgating_state(adev, 76454c73b51SAlex Deucher AMD_IP_BLOCK_TYPE_GFX, 76554c73b51SAlex Deucher AMD_CG_STATE_UNGATE); 76654c73b51SAlex Deucher } else if ((current_level & profile_mode_mask) && 76754c73b51SAlex Deucher !(level & profile_mode_mask)) { 76854c73b51SAlex Deucher /* exit UMD Pstate */ 76954c73b51SAlex Deucher amdgpu_device_ip_set_clockgating_state(adev, 77054c73b51SAlex Deucher AMD_IP_BLOCK_TYPE_GFX, 77154c73b51SAlex Deucher AMD_CG_STATE_GATE); 77254c73b51SAlex Deucher amdgpu_device_ip_set_powergating_state(adev, 77354c73b51SAlex Deucher AMD_IP_BLOCK_TYPE_GFX, 77454c73b51SAlex Deucher AMD_PG_STATE_GATE); 77554c73b51SAlex Deucher } 77654c73b51SAlex Deucher 77775513bf5SEvan Quan mutex_lock(&adev->pm.mutex); 77879c65f3fSEvan Quan 77975513bf5SEvan Quan if (pp_funcs->force_performance_level(adev->powerplay.pp_handle, 78075513bf5SEvan Quan level)) { 78175513bf5SEvan Quan mutex_unlock(&adev->pm.mutex); 78275513bf5SEvan Quan return -EINVAL; 78375513bf5SEvan Quan } 78475513bf5SEvan Quan 78579c65f3fSEvan Quan adev->pm.dpm.forced_level = level; 78679c65f3fSEvan Quan 7873712e7a4SEvan Quan mutex_unlock(&adev->pm.mutex); 7883712e7a4SEvan Quan 78975513bf5SEvan Quan return 0; 79079c65f3fSEvan Quan } 79179c65f3fSEvan Quan 79279c65f3fSEvan Quan int amdgpu_dpm_get_pp_num_states(struct amdgpu_device *adev, 79379c65f3fSEvan Quan struct pp_states_info *states) 79479c65f3fSEvan Quan { 79579c65f3fSEvan Quan const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 7963712e7a4SEvan Quan int ret = 0; 79779c65f3fSEvan Quan 79879c65f3fSEvan Quan if (!pp_funcs->get_pp_num_states) 79979c65f3fSEvan Quan return -EOPNOTSUPP; 80079c65f3fSEvan Quan 8013712e7a4SEvan Quan mutex_lock(&adev->pm.mutex); 8023712e7a4SEvan Quan ret = pp_funcs->get_pp_num_states(adev->powerplay.pp_handle, 8033712e7a4SEvan Quan states); 8043712e7a4SEvan Quan mutex_unlock(&adev->pm.mutex); 8053712e7a4SEvan Quan 8063712e7a4SEvan Quan return ret; 80779c65f3fSEvan Quan } 80879c65f3fSEvan Quan 80979c65f3fSEvan Quan int amdgpu_dpm_dispatch_task(struct amdgpu_device *adev, 81079c65f3fSEvan Quan enum amd_pp_task task_id, 81179c65f3fSEvan Quan enum amd_pm_state_type *user_state) 81279c65f3fSEvan Quan { 81379c65f3fSEvan Quan const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 8143712e7a4SEvan Quan int ret = 0; 81579c65f3fSEvan Quan 81679c65f3fSEvan Quan if (!pp_funcs->dispatch_tasks) 81779c65f3fSEvan Quan return -EOPNOTSUPP; 81879c65f3fSEvan Quan 8193712e7a4SEvan Quan mutex_lock(&adev->pm.mutex); 8203712e7a4SEvan Quan ret = pp_funcs->dispatch_tasks(adev->powerplay.pp_handle, 8213712e7a4SEvan Quan task_id, 8223712e7a4SEvan Quan user_state); 8233712e7a4SEvan Quan mutex_unlock(&adev->pm.mutex); 8243712e7a4SEvan Quan 8253712e7a4SEvan Quan return ret; 82679c65f3fSEvan Quan } 82779c65f3fSEvan Quan 82879c65f3fSEvan Quan int amdgpu_dpm_get_pp_table(struct amdgpu_device *adev, char **table) 82979c65f3fSEvan Quan { 83079c65f3fSEvan Quan const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 8313712e7a4SEvan Quan int ret = 0; 83279c65f3fSEvan Quan 83379c65f3fSEvan Quan if (!pp_funcs->get_pp_table) 83479c65f3fSEvan Quan return 0; 83579c65f3fSEvan Quan 8363712e7a4SEvan Quan mutex_lock(&adev->pm.mutex); 8373712e7a4SEvan Quan ret = pp_funcs->get_pp_table(adev->powerplay.pp_handle, 8383712e7a4SEvan Quan table); 8393712e7a4SEvan Quan mutex_unlock(&adev->pm.mutex); 8403712e7a4SEvan Quan 8413712e7a4SEvan Quan return ret; 84279c65f3fSEvan Quan } 84379c65f3fSEvan Quan 84479c65f3fSEvan Quan int amdgpu_dpm_set_fine_grain_clk_vol(struct amdgpu_device *adev, 84579c65f3fSEvan Quan uint32_t type, 84679c65f3fSEvan Quan long *input, 84779c65f3fSEvan Quan uint32_t size) 84879c65f3fSEvan Quan { 84979c65f3fSEvan Quan const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 8503712e7a4SEvan Quan int ret = 0; 85179c65f3fSEvan Quan 85279c65f3fSEvan Quan if (!pp_funcs->set_fine_grain_clk_vol) 85379c65f3fSEvan Quan return 0; 85479c65f3fSEvan Quan 8553712e7a4SEvan Quan mutex_lock(&adev->pm.mutex); 8563712e7a4SEvan Quan ret = pp_funcs->set_fine_grain_clk_vol(adev->powerplay.pp_handle, 85779c65f3fSEvan Quan type, 85879c65f3fSEvan Quan input, 85979c65f3fSEvan Quan size); 8603712e7a4SEvan Quan mutex_unlock(&adev->pm.mutex); 8613712e7a4SEvan Quan 8623712e7a4SEvan Quan return ret; 86379c65f3fSEvan Quan } 86479c65f3fSEvan Quan 86579c65f3fSEvan Quan int amdgpu_dpm_odn_edit_dpm_table(struct amdgpu_device *adev, 86679c65f3fSEvan Quan uint32_t type, 86779c65f3fSEvan Quan long *input, 86879c65f3fSEvan Quan uint32_t size) 86979c65f3fSEvan Quan { 87079c65f3fSEvan Quan const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 8713712e7a4SEvan Quan int ret = 0; 87279c65f3fSEvan Quan 87379c65f3fSEvan Quan if (!pp_funcs->odn_edit_dpm_table) 87479c65f3fSEvan Quan return 0; 87579c65f3fSEvan Quan 8763712e7a4SEvan Quan mutex_lock(&adev->pm.mutex); 8773712e7a4SEvan Quan ret = pp_funcs->odn_edit_dpm_table(adev->powerplay.pp_handle, 87879c65f3fSEvan Quan type, 87979c65f3fSEvan Quan input, 88079c65f3fSEvan Quan size); 8813712e7a4SEvan Quan mutex_unlock(&adev->pm.mutex); 8823712e7a4SEvan Quan 8833712e7a4SEvan Quan return ret; 88479c65f3fSEvan Quan } 88579c65f3fSEvan Quan 88679c65f3fSEvan Quan int amdgpu_dpm_print_clock_levels(struct amdgpu_device *adev, 88779c65f3fSEvan Quan enum pp_clock_type type, 88879c65f3fSEvan Quan char *buf) 88979c65f3fSEvan Quan { 89079c65f3fSEvan Quan const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 8913712e7a4SEvan Quan int ret = 0; 89279c65f3fSEvan Quan 89379c65f3fSEvan Quan if (!pp_funcs->print_clock_levels) 89479c65f3fSEvan Quan return 0; 89579c65f3fSEvan Quan 8963712e7a4SEvan Quan mutex_lock(&adev->pm.mutex); 8973712e7a4SEvan Quan ret = pp_funcs->print_clock_levels(adev->powerplay.pp_handle, 89879c65f3fSEvan Quan type, 89979c65f3fSEvan Quan buf); 9003712e7a4SEvan Quan mutex_unlock(&adev->pm.mutex); 9013712e7a4SEvan Quan 9023712e7a4SEvan Quan return ret; 90379c65f3fSEvan Quan } 90479c65f3fSEvan Quan 9055d64f9bbSDarren Powell int amdgpu_dpm_emit_clock_levels(struct amdgpu_device *adev, 9065d64f9bbSDarren Powell enum pp_clock_type type, 9075d64f9bbSDarren Powell char *buf, 9085d64f9bbSDarren Powell int *offset) 9095d64f9bbSDarren Powell { 9105d64f9bbSDarren Powell const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 9115d64f9bbSDarren Powell int ret = 0; 9125d64f9bbSDarren Powell 9135d64f9bbSDarren Powell if (!pp_funcs->emit_clock_levels) 9145d64f9bbSDarren Powell return -ENOENT; 9155d64f9bbSDarren Powell 9165d64f9bbSDarren Powell mutex_lock(&adev->pm.mutex); 9175d64f9bbSDarren Powell ret = pp_funcs->emit_clock_levels(adev->powerplay.pp_handle, 9185d64f9bbSDarren Powell type, 9195d64f9bbSDarren Powell buf, 9205d64f9bbSDarren Powell offset); 9215d64f9bbSDarren Powell mutex_unlock(&adev->pm.mutex); 9225d64f9bbSDarren Powell 9235d64f9bbSDarren Powell return ret; 9245d64f9bbSDarren Powell } 9255d64f9bbSDarren Powell 92679c65f3fSEvan Quan int amdgpu_dpm_set_ppfeature_status(struct amdgpu_device *adev, 92779c65f3fSEvan Quan uint64_t ppfeature_masks) 92879c65f3fSEvan Quan { 92979c65f3fSEvan Quan const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 9303712e7a4SEvan Quan int ret = 0; 93179c65f3fSEvan Quan 93279c65f3fSEvan Quan if (!pp_funcs->set_ppfeature_status) 93379c65f3fSEvan Quan return 0; 93479c65f3fSEvan Quan 9353712e7a4SEvan Quan mutex_lock(&adev->pm.mutex); 9363712e7a4SEvan Quan ret = pp_funcs->set_ppfeature_status(adev->powerplay.pp_handle, 93779c65f3fSEvan Quan ppfeature_masks); 9383712e7a4SEvan Quan mutex_unlock(&adev->pm.mutex); 9393712e7a4SEvan Quan 9403712e7a4SEvan Quan return ret; 94179c65f3fSEvan Quan } 94279c65f3fSEvan Quan 94379c65f3fSEvan Quan int amdgpu_dpm_get_ppfeature_status(struct amdgpu_device *adev, char *buf) 94479c65f3fSEvan Quan { 94579c65f3fSEvan Quan const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 9463712e7a4SEvan Quan int ret = 0; 94779c65f3fSEvan Quan 94879c65f3fSEvan Quan if (!pp_funcs->get_ppfeature_status) 94979c65f3fSEvan Quan return 0; 95079c65f3fSEvan Quan 9513712e7a4SEvan Quan mutex_lock(&adev->pm.mutex); 9523712e7a4SEvan Quan ret = pp_funcs->get_ppfeature_status(adev->powerplay.pp_handle, 95379c65f3fSEvan Quan buf); 9543712e7a4SEvan Quan mutex_unlock(&adev->pm.mutex); 9553712e7a4SEvan Quan 9563712e7a4SEvan Quan return ret; 95779c65f3fSEvan Quan } 95879c65f3fSEvan Quan 95979c65f3fSEvan Quan int amdgpu_dpm_force_clock_level(struct amdgpu_device *adev, 96079c65f3fSEvan Quan enum pp_clock_type type, 96179c65f3fSEvan Quan uint32_t mask) 96279c65f3fSEvan Quan { 96379c65f3fSEvan Quan const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 9643712e7a4SEvan Quan int ret = 0; 96579c65f3fSEvan Quan 96679c65f3fSEvan Quan if (!pp_funcs->force_clock_level) 96779c65f3fSEvan Quan return 0; 96879c65f3fSEvan Quan 9693712e7a4SEvan Quan mutex_lock(&adev->pm.mutex); 9703712e7a4SEvan Quan ret = pp_funcs->force_clock_level(adev->powerplay.pp_handle, 97179c65f3fSEvan Quan type, 97279c65f3fSEvan Quan mask); 9733712e7a4SEvan Quan mutex_unlock(&adev->pm.mutex); 9743712e7a4SEvan Quan 9753712e7a4SEvan Quan return ret; 97679c65f3fSEvan Quan } 97779c65f3fSEvan Quan 97879c65f3fSEvan Quan int amdgpu_dpm_get_sclk_od(struct amdgpu_device *adev) 97979c65f3fSEvan Quan { 98079c65f3fSEvan Quan const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 9813712e7a4SEvan Quan int ret = 0; 98279c65f3fSEvan Quan 98379c65f3fSEvan Quan if (!pp_funcs->get_sclk_od) 98479c65f3fSEvan Quan return 0; 98579c65f3fSEvan Quan 9863712e7a4SEvan Quan mutex_lock(&adev->pm.mutex); 9873712e7a4SEvan Quan ret = pp_funcs->get_sclk_od(adev->powerplay.pp_handle); 9883712e7a4SEvan Quan mutex_unlock(&adev->pm.mutex); 9893712e7a4SEvan Quan 9903712e7a4SEvan Quan return ret; 99179c65f3fSEvan Quan } 99279c65f3fSEvan Quan 99379c65f3fSEvan Quan int amdgpu_dpm_set_sclk_od(struct amdgpu_device *adev, uint32_t value) 99479c65f3fSEvan Quan { 99579c65f3fSEvan Quan const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 99679c65f3fSEvan Quan 99779c65f3fSEvan Quan if (is_support_sw_smu(adev)) 99879c65f3fSEvan Quan return 0; 99979c65f3fSEvan Quan 10003712e7a4SEvan Quan mutex_lock(&adev->pm.mutex); 100179c65f3fSEvan Quan if (pp_funcs->set_sclk_od) 100279c65f3fSEvan Quan pp_funcs->set_sclk_od(adev->powerplay.pp_handle, value); 10033712e7a4SEvan Quan mutex_unlock(&adev->pm.mutex); 100479c65f3fSEvan Quan 100579c65f3fSEvan Quan if (amdgpu_dpm_dispatch_task(adev, 100679c65f3fSEvan Quan AMD_PP_TASK_READJUST_POWER_STATE, 100779c65f3fSEvan Quan NULL) == -EOPNOTSUPP) { 100879c65f3fSEvan Quan adev->pm.dpm.current_ps = adev->pm.dpm.boot_ps; 100984176663SEvan Quan amdgpu_dpm_compute_clocks(adev); 101079c65f3fSEvan Quan } 101179c65f3fSEvan Quan 101279c65f3fSEvan Quan return 0; 101379c65f3fSEvan Quan } 101479c65f3fSEvan Quan 101579c65f3fSEvan Quan int amdgpu_dpm_get_mclk_od(struct amdgpu_device *adev) 101679c65f3fSEvan Quan { 101779c65f3fSEvan Quan const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 10183712e7a4SEvan Quan int ret = 0; 101979c65f3fSEvan Quan 102079c65f3fSEvan Quan if (!pp_funcs->get_mclk_od) 102179c65f3fSEvan Quan return 0; 102279c65f3fSEvan Quan 10233712e7a4SEvan Quan mutex_lock(&adev->pm.mutex); 10243712e7a4SEvan Quan ret = pp_funcs->get_mclk_od(adev->powerplay.pp_handle); 10253712e7a4SEvan Quan mutex_unlock(&adev->pm.mutex); 10263712e7a4SEvan Quan 10273712e7a4SEvan Quan return ret; 102879c65f3fSEvan Quan } 102979c65f3fSEvan Quan 103079c65f3fSEvan Quan int amdgpu_dpm_set_mclk_od(struct amdgpu_device *adev, uint32_t value) 103179c65f3fSEvan Quan { 103279c65f3fSEvan Quan const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 103379c65f3fSEvan Quan 103479c65f3fSEvan Quan if (is_support_sw_smu(adev)) 103579c65f3fSEvan Quan return 0; 103679c65f3fSEvan Quan 10373712e7a4SEvan Quan mutex_lock(&adev->pm.mutex); 103879c65f3fSEvan Quan if (pp_funcs->set_mclk_od) 103979c65f3fSEvan Quan pp_funcs->set_mclk_od(adev->powerplay.pp_handle, value); 10403712e7a4SEvan Quan mutex_unlock(&adev->pm.mutex); 104179c65f3fSEvan Quan 104279c65f3fSEvan Quan if (amdgpu_dpm_dispatch_task(adev, 104379c65f3fSEvan Quan AMD_PP_TASK_READJUST_POWER_STATE, 104479c65f3fSEvan Quan NULL) == -EOPNOTSUPP) { 104579c65f3fSEvan Quan adev->pm.dpm.current_ps = adev->pm.dpm.boot_ps; 104684176663SEvan Quan amdgpu_dpm_compute_clocks(adev); 104779c65f3fSEvan Quan } 104879c65f3fSEvan Quan 104979c65f3fSEvan Quan return 0; 105079c65f3fSEvan Quan } 105179c65f3fSEvan Quan 105279c65f3fSEvan Quan int amdgpu_dpm_get_power_profile_mode(struct amdgpu_device *adev, 105379c65f3fSEvan Quan char *buf) 105479c65f3fSEvan Quan { 105579c65f3fSEvan Quan const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 10563712e7a4SEvan Quan int ret = 0; 105779c65f3fSEvan Quan 105879c65f3fSEvan Quan if (!pp_funcs->get_power_profile_mode) 105979c65f3fSEvan Quan return -EOPNOTSUPP; 106079c65f3fSEvan Quan 10613712e7a4SEvan Quan mutex_lock(&adev->pm.mutex); 10623712e7a4SEvan Quan ret = pp_funcs->get_power_profile_mode(adev->powerplay.pp_handle, 106379c65f3fSEvan Quan buf); 10643712e7a4SEvan Quan mutex_unlock(&adev->pm.mutex); 10653712e7a4SEvan Quan 10663712e7a4SEvan Quan return ret; 106779c65f3fSEvan Quan } 106879c65f3fSEvan Quan 106979c65f3fSEvan Quan int amdgpu_dpm_set_power_profile_mode(struct amdgpu_device *adev, 107079c65f3fSEvan Quan long *input, uint32_t size) 107179c65f3fSEvan Quan { 107279c65f3fSEvan Quan const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 10733712e7a4SEvan Quan int ret = 0; 107479c65f3fSEvan Quan 107579c65f3fSEvan Quan if (!pp_funcs->set_power_profile_mode) 107679c65f3fSEvan Quan return 0; 107779c65f3fSEvan Quan 10783712e7a4SEvan Quan mutex_lock(&adev->pm.mutex); 10793712e7a4SEvan Quan ret = pp_funcs->set_power_profile_mode(adev->powerplay.pp_handle, 108079c65f3fSEvan Quan input, 108179c65f3fSEvan Quan size); 10823712e7a4SEvan Quan mutex_unlock(&adev->pm.mutex); 10833712e7a4SEvan Quan 10843712e7a4SEvan Quan return ret; 108579c65f3fSEvan Quan } 108679c65f3fSEvan Quan 108779c65f3fSEvan Quan int amdgpu_dpm_get_gpu_metrics(struct amdgpu_device *adev, void **table) 108879c65f3fSEvan Quan { 108979c65f3fSEvan Quan const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 10903712e7a4SEvan Quan int ret = 0; 109179c65f3fSEvan Quan 109279c65f3fSEvan Quan if (!pp_funcs->get_gpu_metrics) 109379c65f3fSEvan Quan return 0; 109479c65f3fSEvan Quan 10953712e7a4SEvan Quan mutex_lock(&adev->pm.mutex); 10963712e7a4SEvan Quan ret = pp_funcs->get_gpu_metrics(adev->powerplay.pp_handle, 10973712e7a4SEvan Quan table); 10983712e7a4SEvan Quan mutex_unlock(&adev->pm.mutex); 10993712e7a4SEvan Quan 11003712e7a4SEvan Quan return ret; 110179c65f3fSEvan Quan } 110279c65f3fSEvan Quan 110379c65f3fSEvan Quan int amdgpu_dpm_get_fan_control_mode(struct amdgpu_device *adev, 110479c65f3fSEvan Quan uint32_t *fan_mode) 110579c65f3fSEvan Quan { 110679c65f3fSEvan Quan const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 1107685fae24SEvan Quan int ret = 0; 110879c65f3fSEvan Quan 110979c65f3fSEvan Quan if (!pp_funcs->get_fan_control_mode) 111079c65f3fSEvan Quan return -EOPNOTSUPP; 111179c65f3fSEvan Quan 11123712e7a4SEvan Quan mutex_lock(&adev->pm.mutex); 1113685fae24SEvan Quan ret = pp_funcs->get_fan_control_mode(adev->powerplay.pp_handle, 1114685fae24SEvan Quan fan_mode); 11153712e7a4SEvan Quan mutex_unlock(&adev->pm.mutex); 111679c65f3fSEvan Quan 1117685fae24SEvan Quan return ret; 111879c65f3fSEvan Quan } 111979c65f3fSEvan Quan 112079c65f3fSEvan Quan int amdgpu_dpm_set_fan_speed_pwm(struct amdgpu_device *adev, 112179c65f3fSEvan Quan uint32_t speed) 112279c65f3fSEvan Quan { 112379c65f3fSEvan Quan const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 11243712e7a4SEvan Quan int ret = 0; 112579c65f3fSEvan Quan 112679c65f3fSEvan Quan if (!pp_funcs->set_fan_speed_pwm) 1127685fae24SEvan Quan return -EOPNOTSUPP; 112879c65f3fSEvan Quan 11293712e7a4SEvan Quan mutex_lock(&adev->pm.mutex); 11303712e7a4SEvan Quan ret = pp_funcs->set_fan_speed_pwm(adev->powerplay.pp_handle, 11313712e7a4SEvan Quan speed); 11323712e7a4SEvan Quan mutex_unlock(&adev->pm.mutex); 11333712e7a4SEvan Quan 11343712e7a4SEvan Quan return ret; 113579c65f3fSEvan Quan } 113679c65f3fSEvan Quan 113779c65f3fSEvan Quan int amdgpu_dpm_get_fan_speed_pwm(struct amdgpu_device *adev, 113879c65f3fSEvan Quan uint32_t *speed) 113979c65f3fSEvan Quan { 114079c65f3fSEvan Quan const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 11413712e7a4SEvan Quan int ret = 0; 114279c65f3fSEvan Quan 114379c65f3fSEvan Quan if (!pp_funcs->get_fan_speed_pwm) 1144685fae24SEvan Quan return -EOPNOTSUPP; 114579c65f3fSEvan Quan 11463712e7a4SEvan Quan mutex_lock(&adev->pm.mutex); 11473712e7a4SEvan Quan ret = pp_funcs->get_fan_speed_pwm(adev->powerplay.pp_handle, 11483712e7a4SEvan Quan speed); 11493712e7a4SEvan Quan mutex_unlock(&adev->pm.mutex); 11503712e7a4SEvan Quan 11513712e7a4SEvan Quan return ret; 115279c65f3fSEvan Quan } 115379c65f3fSEvan Quan 115479c65f3fSEvan Quan int amdgpu_dpm_get_fan_speed_rpm(struct amdgpu_device *adev, 115579c65f3fSEvan Quan uint32_t *speed) 115679c65f3fSEvan Quan { 115779c65f3fSEvan Quan const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 11583712e7a4SEvan Quan int ret = 0; 115979c65f3fSEvan Quan 116079c65f3fSEvan Quan if (!pp_funcs->get_fan_speed_rpm) 1161685fae24SEvan Quan return -EOPNOTSUPP; 116279c65f3fSEvan Quan 11633712e7a4SEvan Quan mutex_lock(&adev->pm.mutex); 11643712e7a4SEvan Quan ret = pp_funcs->get_fan_speed_rpm(adev->powerplay.pp_handle, 11653712e7a4SEvan Quan speed); 11663712e7a4SEvan Quan mutex_unlock(&adev->pm.mutex); 11673712e7a4SEvan Quan 11683712e7a4SEvan Quan return ret; 116979c65f3fSEvan Quan } 117079c65f3fSEvan Quan 117179c65f3fSEvan Quan int amdgpu_dpm_set_fan_speed_rpm(struct amdgpu_device *adev, 117279c65f3fSEvan Quan uint32_t speed) 117379c65f3fSEvan Quan { 117479c65f3fSEvan Quan const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 11753712e7a4SEvan Quan int ret = 0; 117679c65f3fSEvan Quan 117779c65f3fSEvan Quan if (!pp_funcs->set_fan_speed_rpm) 1178685fae24SEvan Quan return -EOPNOTSUPP; 117979c65f3fSEvan Quan 11803712e7a4SEvan Quan mutex_lock(&adev->pm.mutex); 11813712e7a4SEvan Quan ret = pp_funcs->set_fan_speed_rpm(adev->powerplay.pp_handle, 11823712e7a4SEvan Quan speed); 11833712e7a4SEvan Quan mutex_unlock(&adev->pm.mutex); 11843712e7a4SEvan Quan 11853712e7a4SEvan Quan return ret; 118679c65f3fSEvan Quan } 118779c65f3fSEvan Quan 118879c65f3fSEvan Quan int amdgpu_dpm_set_fan_control_mode(struct amdgpu_device *adev, 118979c65f3fSEvan Quan uint32_t mode) 119079c65f3fSEvan Quan { 119179c65f3fSEvan Quan const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 1192685fae24SEvan Quan int ret = 0; 119379c65f3fSEvan Quan 119479c65f3fSEvan Quan if (!pp_funcs->set_fan_control_mode) 119579c65f3fSEvan Quan return -EOPNOTSUPP; 119679c65f3fSEvan Quan 11973712e7a4SEvan Quan mutex_lock(&adev->pm.mutex); 1198685fae24SEvan Quan ret = pp_funcs->set_fan_control_mode(adev->powerplay.pp_handle, 11993712e7a4SEvan Quan mode); 12003712e7a4SEvan Quan mutex_unlock(&adev->pm.mutex); 120179c65f3fSEvan Quan 1202685fae24SEvan Quan return ret; 120379c65f3fSEvan Quan } 120479c65f3fSEvan Quan 120579c65f3fSEvan Quan int amdgpu_dpm_get_power_limit(struct amdgpu_device *adev, 120679c65f3fSEvan Quan uint32_t *limit, 120779c65f3fSEvan Quan enum pp_power_limit_level pp_limit_level, 120879c65f3fSEvan Quan enum pp_power_type power_type) 120979c65f3fSEvan Quan { 121079c65f3fSEvan Quan const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 12113712e7a4SEvan Quan int ret = 0; 121279c65f3fSEvan Quan 121379c65f3fSEvan Quan if (!pp_funcs->get_power_limit) 121479c65f3fSEvan Quan return -ENODATA; 121579c65f3fSEvan Quan 12163712e7a4SEvan Quan mutex_lock(&adev->pm.mutex); 12173712e7a4SEvan Quan ret = pp_funcs->get_power_limit(adev->powerplay.pp_handle, 121879c65f3fSEvan Quan limit, 121979c65f3fSEvan Quan pp_limit_level, 122079c65f3fSEvan Quan power_type); 12213712e7a4SEvan Quan mutex_unlock(&adev->pm.mutex); 12223712e7a4SEvan Quan 12233712e7a4SEvan Quan return ret; 122479c65f3fSEvan Quan } 122579c65f3fSEvan Quan 122679c65f3fSEvan Quan int amdgpu_dpm_set_power_limit(struct amdgpu_device *adev, 122779c65f3fSEvan Quan uint32_t limit) 122879c65f3fSEvan Quan { 122979c65f3fSEvan Quan const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 12303712e7a4SEvan Quan int ret = 0; 123179c65f3fSEvan Quan 123279c65f3fSEvan Quan if (!pp_funcs->set_power_limit) 123379c65f3fSEvan Quan return -EINVAL; 123479c65f3fSEvan Quan 12353712e7a4SEvan Quan mutex_lock(&adev->pm.mutex); 12363712e7a4SEvan Quan ret = pp_funcs->set_power_limit(adev->powerplay.pp_handle, 12373712e7a4SEvan Quan limit); 12383712e7a4SEvan Quan mutex_unlock(&adev->pm.mutex); 12393712e7a4SEvan Quan 12403712e7a4SEvan Quan return ret; 124179c65f3fSEvan Quan } 124279c65f3fSEvan Quan 124379c65f3fSEvan Quan int amdgpu_dpm_is_cclk_dpm_supported(struct amdgpu_device *adev) 124479c65f3fSEvan Quan { 12453712e7a4SEvan Quan bool cclk_dpm_supported = false; 12463712e7a4SEvan Quan 124779c65f3fSEvan Quan if (!is_support_sw_smu(adev)) 124879c65f3fSEvan Quan return false; 124979c65f3fSEvan Quan 12503712e7a4SEvan Quan mutex_lock(&adev->pm.mutex); 12513712e7a4SEvan Quan cclk_dpm_supported = is_support_cclk_dpm(adev); 12523712e7a4SEvan Quan mutex_unlock(&adev->pm.mutex); 12533712e7a4SEvan Quan 12543712e7a4SEvan Quan return (int)cclk_dpm_supported; 125579c65f3fSEvan Quan } 125679c65f3fSEvan Quan 125779c65f3fSEvan Quan int amdgpu_dpm_debugfs_print_current_performance_level(struct amdgpu_device *adev, 125879c65f3fSEvan Quan struct seq_file *m) 125979c65f3fSEvan Quan { 126079c65f3fSEvan Quan const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 126179c65f3fSEvan Quan 126279c65f3fSEvan Quan if (!pp_funcs->debugfs_print_current_performance_level) 126379c65f3fSEvan Quan return -EOPNOTSUPP; 126479c65f3fSEvan Quan 12653712e7a4SEvan Quan mutex_lock(&adev->pm.mutex); 126679c65f3fSEvan Quan pp_funcs->debugfs_print_current_performance_level(adev->powerplay.pp_handle, 126779c65f3fSEvan Quan m); 12683712e7a4SEvan Quan mutex_unlock(&adev->pm.mutex); 126979c65f3fSEvan Quan 127079c65f3fSEvan Quan return 0; 127179c65f3fSEvan Quan } 127279c65f3fSEvan Quan 127379c65f3fSEvan Quan int amdgpu_dpm_get_smu_prv_buf_details(struct amdgpu_device *adev, 127479c65f3fSEvan Quan void **addr, 127579c65f3fSEvan Quan size_t *size) 127679c65f3fSEvan Quan { 127779c65f3fSEvan Quan const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 12783712e7a4SEvan Quan int ret = 0; 127979c65f3fSEvan Quan 128079c65f3fSEvan Quan if (!pp_funcs->get_smu_prv_buf_details) 128179c65f3fSEvan Quan return -ENOSYS; 128279c65f3fSEvan Quan 12833712e7a4SEvan Quan mutex_lock(&adev->pm.mutex); 12843712e7a4SEvan Quan ret = pp_funcs->get_smu_prv_buf_details(adev->powerplay.pp_handle, 128579c65f3fSEvan Quan addr, 128679c65f3fSEvan Quan size); 12873712e7a4SEvan Quan mutex_unlock(&adev->pm.mutex); 12883712e7a4SEvan Quan 12893712e7a4SEvan Quan return ret; 129079c65f3fSEvan Quan } 129179c65f3fSEvan Quan 129279c65f3fSEvan Quan int amdgpu_dpm_is_overdrive_supported(struct amdgpu_device *adev) 129379c65f3fSEvan Quan { 129479c65f3fSEvan Quan struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle; 1295ebfc2533SEvan Quan struct smu_context *smu = adev->powerplay.pp_handle; 129679c65f3fSEvan Quan 1297ebfc2533SEvan Quan if ((is_support_sw_smu(adev) && smu->od_enabled) || 1298ebfc2533SEvan Quan (is_support_sw_smu(adev) && smu->is_apu) || 129979c65f3fSEvan Quan (!is_support_sw_smu(adev) && hwmgr->od_enabled)) 130079c65f3fSEvan Quan return true; 130179c65f3fSEvan Quan 130279c65f3fSEvan Quan return false; 130379c65f3fSEvan Quan } 130479c65f3fSEvan Quan 130579c65f3fSEvan Quan int amdgpu_dpm_set_pp_table(struct amdgpu_device *adev, 130679c65f3fSEvan Quan const char *buf, 130779c65f3fSEvan Quan size_t size) 130879c65f3fSEvan Quan { 130979c65f3fSEvan Quan const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 13103712e7a4SEvan Quan int ret = 0; 131179c65f3fSEvan Quan 131279c65f3fSEvan Quan if (!pp_funcs->set_pp_table) 131379c65f3fSEvan Quan return -EOPNOTSUPP; 131479c65f3fSEvan Quan 13153712e7a4SEvan Quan mutex_lock(&adev->pm.mutex); 13163712e7a4SEvan Quan ret = pp_funcs->set_pp_table(adev->powerplay.pp_handle, 131779c65f3fSEvan Quan buf, 131879c65f3fSEvan Quan size); 13193712e7a4SEvan Quan mutex_unlock(&adev->pm.mutex); 13203712e7a4SEvan Quan 13213712e7a4SEvan Quan return ret; 132279c65f3fSEvan Quan } 132379c65f3fSEvan Quan 132479c65f3fSEvan Quan int amdgpu_dpm_get_num_cpu_cores(struct amdgpu_device *adev) 132579c65f3fSEvan Quan { 1326ebfc2533SEvan Quan struct smu_context *smu = adev->powerplay.pp_handle; 1327ebfc2533SEvan Quan 13283712e7a4SEvan Quan if (!is_support_sw_smu(adev)) 13293712e7a4SEvan Quan return INT_MAX; 13303712e7a4SEvan Quan 1331ebfc2533SEvan Quan return smu->cpu_core_num; 133279c65f3fSEvan Quan } 133379c65f3fSEvan Quan 133479c65f3fSEvan Quan void amdgpu_dpm_stb_debug_fs_init(struct amdgpu_device *adev) 133579c65f3fSEvan Quan { 133679c65f3fSEvan Quan if (!is_support_sw_smu(adev)) 133779c65f3fSEvan Quan return; 133879c65f3fSEvan Quan 133979c65f3fSEvan Quan amdgpu_smu_stb_debug_fs_init(adev); 134079c65f3fSEvan Quan } 134113f5dbd6SEvan Quan 134213f5dbd6SEvan Quan int amdgpu_dpm_display_configuration_change(struct amdgpu_device *adev, 134313f5dbd6SEvan Quan const struct amd_pp_display_configuration *input) 134413f5dbd6SEvan Quan { 134513f5dbd6SEvan Quan const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 13463712e7a4SEvan Quan int ret = 0; 134713f5dbd6SEvan Quan 134813f5dbd6SEvan Quan if (!pp_funcs->display_configuration_change) 134913f5dbd6SEvan Quan return 0; 135013f5dbd6SEvan Quan 13513712e7a4SEvan Quan mutex_lock(&adev->pm.mutex); 13523712e7a4SEvan Quan ret = pp_funcs->display_configuration_change(adev->powerplay.pp_handle, 135313f5dbd6SEvan Quan input); 13543712e7a4SEvan Quan mutex_unlock(&adev->pm.mutex); 13553712e7a4SEvan Quan 13563712e7a4SEvan Quan return ret; 135713f5dbd6SEvan Quan } 135813f5dbd6SEvan Quan 135913f5dbd6SEvan Quan int amdgpu_dpm_get_clock_by_type(struct amdgpu_device *adev, 136013f5dbd6SEvan Quan enum amd_pp_clock_type type, 136113f5dbd6SEvan Quan struct amd_pp_clocks *clocks) 136213f5dbd6SEvan Quan { 136313f5dbd6SEvan Quan const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 13643712e7a4SEvan Quan int ret = 0; 136513f5dbd6SEvan Quan 136613f5dbd6SEvan Quan if (!pp_funcs->get_clock_by_type) 136713f5dbd6SEvan Quan return 0; 136813f5dbd6SEvan Quan 13693712e7a4SEvan Quan mutex_lock(&adev->pm.mutex); 13703712e7a4SEvan Quan ret = pp_funcs->get_clock_by_type(adev->powerplay.pp_handle, 137113f5dbd6SEvan Quan type, 137213f5dbd6SEvan Quan clocks); 13733712e7a4SEvan Quan mutex_unlock(&adev->pm.mutex); 13743712e7a4SEvan Quan 13753712e7a4SEvan Quan return ret; 137613f5dbd6SEvan Quan } 137713f5dbd6SEvan Quan 137813f5dbd6SEvan Quan int amdgpu_dpm_get_display_mode_validation_clks(struct amdgpu_device *adev, 137913f5dbd6SEvan Quan struct amd_pp_simple_clock_info *clocks) 138013f5dbd6SEvan Quan { 138113f5dbd6SEvan Quan const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 13823712e7a4SEvan Quan int ret = 0; 138313f5dbd6SEvan Quan 138413f5dbd6SEvan Quan if (!pp_funcs->get_display_mode_validation_clocks) 138513f5dbd6SEvan Quan return 0; 138613f5dbd6SEvan Quan 13873712e7a4SEvan Quan mutex_lock(&adev->pm.mutex); 13883712e7a4SEvan Quan ret = pp_funcs->get_display_mode_validation_clocks(adev->powerplay.pp_handle, 138913f5dbd6SEvan Quan clocks); 13903712e7a4SEvan Quan mutex_unlock(&adev->pm.mutex); 13913712e7a4SEvan Quan 13923712e7a4SEvan Quan return ret; 139313f5dbd6SEvan Quan } 139413f5dbd6SEvan Quan 139513f5dbd6SEvan Quan int amdgpu_dpm_get_clock_by_type_with_latency(struct amdgpu_device *adev, 139613f5dbd6SEvan Quan enum amd_pp_clock_type type, 139713f5dbd6SEvan Quan struct pp_clock_levels_with_latency *clocks) 139813f5dbd6SEvan Quan { 139913f5dbd6SEvan Quan const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 14003712e7a4SEvan Quan int ret = 0; 140113f5dbd6SEvan Quan 140213f5dbd6SEvan Quan if (!pp_funcs->get_clock_by_type_with_latency) 140313f5dbd6SEvan Quan return 0; 140413f5dbd6SEvan Quan 14053712e7a4SEvan Quan mutex_lock(&adev->pm.mutex); 14063712e7a4SEvan Quan ret = pp_funcs->get_clock_by_type_with_latency(adev->powerplay.pp_handle, 140713f5dbd6SEvan Quan type, 140813f5dbd6SEvan Quan clocks); 14093712e7a4SEvan Quan mutex_unlock(&adev->pm.mutex); 14103712e7a4SEvan Quan 14113712e7a4SEvan Quan return ret; 141213f5dbd6SEvan Quan } 141313f5dbd6SEvan Quan 141413f5dbd6SEvan Quan int amdgpu_dpm_get_clock_by_type_with_voltage(struct amdgpu_device *adev, 141513f5dbd6SEvan Quan enum amd_pp_clock_type type, 141613f5dbd6SEvan Quan struct pp_clock_levels_with_voltage *clocks) 141713f5dbd6SEvan Quan { 141813f5dbd6SEvan Quan const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 14193712e7a4SEvan Quan int ret = 0; 142013f5dbd6SEvan Quan 142113f5dbd6SEvan Quan if (!pp_funcs->get_clock_by_type_with_voltage) 142213f5dbd6SEvan Quan return 0; 142313f5dbd6SEvan Quan 14243712e7a4SEvan Quan mutex_lock(&adev->pm.mutex); 14253712e7a4SEvan Quan ret = pp_funcs->get_clock_by_type_with_voltage(adev->powerplay.pp_handle, 142613f5dbd6SEvan Quan type, 142713f5dbd6SEvan Quan clocks); 14283712e7a4SEvan Quan mutex_unlock(&adev->pm.mutex); 14293712e7a4SEvan Quan 14303712e7a4SEvan Quan return ret; 143113f5dbd6SEvan Quan } 143213f5dbd6SEvan Quan 143313f5dbd6SEvan Quan int amdgpu_dpm_set_watermarks_for_clocks_ranges(struct amdgpu_device *adev, 143413f5dbd6SEvan Quan void *clock_ranges) 143513f5dbd6SEvan Quan { 143613f5dbd6SEvan Quan const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 14373712e7a4SEvan Quan int ret = 0; 143813f5dbd6SEvan Quan 143913f5dbd6SEvan Quan if (!pp_funcs->set_watermarks_for_clocks_ranges) 144013f5dbd6SEvan Quan return -EOPNOTSUPP; 144113f5dbd6SEvan Quan 14423712e7a4SEvan Quan mutex_lock(&adev->pm.mutex); 14433712e7a4SEvan Quan ret = pp_funcs->set_watermarks_for_clocks_ranges(adev->powerplay.pp_handle, 144413f5dbd6SEvan Quan clock_ranges); 14453712e7a4SEvan Quan mutex_unlock(&adev->pm.mutex); 14463712e7a4SEvan Quan 14473712e7a4SEvan Quan return ret; 144813f5dbd6SEvan Quan } 144913f5dbd6SEvan Quan 145013f5dbd6SEvan Quan int amdgpu_dpm_display_clock_voltage_request(struct amdgpu_device *adev, 145113f5dbd6SEvan Quan struct pp_display_clock_request *clock) 145213f5dbd6SEvan Quan { 145313f5dbd6SEvan Quan const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 14543712e7a4SEvan Quan int ret = 0; 145513f5dbd6SEvan Quan 145613f5dbd6SEvan Quan if (!pp_funcs->display_clock_voltage_request) 145713f5dbd6SEvan Quan return -EOPNOTSUPP; 145813f5dbd6SEvan Quan 14593712e7a4SEvan Quan mutex_lock(&adev->pm.mutex); 14603712e7a4SEvan Quan ret = pp_funcs->display_clock_voltage_request(adev->powerplay.pp_handle, 146113f5dbd6SEvan Quan clock); 14623712e7a4SEvan Quan mutex_unlock(&adev->pm.mutex); 14633712e7a4SEvan Quan 14643712e7a4SEvan Quan return ret; 146513f5dbd6SEvan Quan } 146613f5dbd6SEvan Quan 146713f5dbd6SEvan Quan int amdgpu_dpm_get_current_clocks(struct amdgpu_device *adev, 146813f5dbd6SEvan Quan struct amd_pp_clock_info *clocks) 146913f5dbd6SEvan Quan { 147013f5dbd6SEvan Quan const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 14713712e7a4SEvan Quan int ret = 0; 147213f5dbd6SEvan Quan 147313f5dbd6SEvan Quan if (!pp_funcs->get_current_clocks) 147413f5dbd6SEvan Quan return -EOPNOTSUPP; 147513f5dbd6SEvan Quan 14763712e7a4SEvan Quan mutex_lock(&adev->pm.mutex); 14773712e7a4SEvan Quan ret = pp_funcs->get_current_clocks(adev->powerplay.pp_handle, 147813f5dbd6SEvan Quan clocks); 14793712e7a4SEvan Quan mutex_unlock(&adev->pm.mutex); 14803712e7a4SEvan Quan 14813712e7a4SEvan Quan return ret; 148213f5dbd6SEvan Quan } 148313f5dbd6SEvan Quan 148413f5dbd6SEvan Quan void amdgpu_dpm_notify_smu_enable_pwe(struct amdgpu_device *adev) 148513f5dbd6SEvan Quan { 148613f5dbd6SEvan Quan const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 148713f5dbd6SEvan Quan 148813f5dbd6SEvan Quan if (!pp_funcs->notify_smu_enable_pwe) 148913f5dbd6SEvan Quan return; 149013f5dbd6SEvan Quan 14913712e7a4SEvan Quan mutex_lock(&adev->pm.mutex); 149213f5dbd6SEvan Quan pp_funcs->notify_smu_enable_pwe(adev->powerplay.pp_handle); 14933712e7a4SEvan Quan mutex_unlock(&adev->pm.mutex); 149413f5dbd6SEvan Quan } 149513f5dbd6SEvan Quan 149613f5dbd6SEvan Quan int amdgpu_dpm_set_active_display_count(struct amdgpu_device *adev, 149713f5dbd6SEvan Quan uint32_t count) 149813f5dbd6SEvan Quan { 149913f5dbd6SEvan Quan const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 15003712e7a4SEvan Quan int ret = 0; 150113f5dbd6SEvan Quan 150213f5dbd6SEvan Quan if (!pp_funcs->set_active_display_count) 150313f5dbd6SEvan Quan return -EOPNOTSUPP; 150413f5dbd6SEvan Quan 15053712e7a4SEvan Quan mutex_lock(&adev->pm.mutex); 15063712e7a4SEvan Quan ret = pp_funcs->set_active_display_count(adev->powerplay.pp_handle, 150713f5dbd6SEvan Quan count); 15083712e7a4SEvan Quan mutex_unlock(&adev->pm.mutex); 15093712e7a4SEvan Quan 15103712e7a4SEvan Quan return ret; 151113f5dbd6SEvan Quan } 151213f5dbd6SEvan Quan 151313f5dbd6SEvan Quan int amdgpu_dpm_set_min_deep_sleep_dcefclk(struct amdgpu_device *adev, 151413f5dbd6SEvan Quan uint32_t clock) 151513f5dbd6SEvan Quan { 151613f5dbd6SEvan Quan const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 15173712e7a4SEvan Quan int ret = 0; 151813f5dbd6SEvan Quan 151913f5dbd6SEvan Quan if (!pp_funcs->set_min_deep_sleep_dcefclk) 152013f5dbd6SEvan Quan return -EOPNOTSUPP; 152113f5dbd6SEvan Quan 15223712e7a4SEvan Quan mutex_lock(&adev->pm.mutex); 15233712e7a4SEvan Quan ret = pp_funcs->set_min_deep_sleep_dcefclk(adev->powerplay.pp_handle, 152413f5dbd6SEvan Quan clock); 15253712e7a4SEvan Quan mutex_unlock(&adev->pm.mutex); 15263712e7a4SEvan Quan 15273712e7a4SEvan Quan return ret; 152813f5dbd6SEvan Quan } 152913f5dbd6SEvan Quan 153013f5dbd6SEvan Quan void amdgpu_dpm_set_hard_min_dcefclk_by_freq(struct amdgpu_device *adev, 153113f5dbd6SEvan Quan uint32_t clock) 153213f5dbd6SEvan Quan { 153313f5dbd6SEvan Quan const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 153413f5dbd6SEvan Quan 153513f5dbd6SEvan Quan if (!pp_funcs->set_hard_min_dcefclk_by_freq) 153613f5dbd6SEvan Quan return; 153713f5dbd6SEvan Quan 15383712e7a4SEvan Quan mutex_lock(&adev->pm.mutex); 153913f5dbd6SEvan Quan pp_funcs->set_hard_min_dcefclk_by_freq(adev->powerplay.pp_handle, 154013f5dbd6SEvan Quan clock); 15413712e7a4SEvan Quan mutex_unlock(&adev->pm.mutex); 154213f5dbd6SEvan Quan } 154313f5dbd6SEvan Quan 154413f5dbd6SEvan Quan void amdgpu_dpm_set_hard_min_fclk_by_freq(struct amdgpu_device *adev, 154513f5dbd6SEvan Quan uint32_t clock) 154613f5dbd6SEvan Quan { 154713f5dbd6SEvan Quan const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 154813f5dbd6SEvan Quan 154913f5dbd6SEvan Quan if (!pp_funcs->set_hard_min_fclk_by_freq) 155013f5dbd6SEvan Quan return; 155113f5dbd6SEvan Quan 15523712e7a4SEvan Quan mutex_lock(&adev->pm.mutex); 155313f5dbd6SEvan Quan pp_funcs->set_hard_min_fclk_by_freq(adev->powerplay.pp_handle, 155413f5dbd6SEvan Quan clock); 15553712e7a4SEvan Quan mutex_unlock(&adev->pm.mutex); 155613f5dbd6SEvan Quan } 155713f5dbd6SEvan Quan 155813f5dbd6SEvan Quan int amdgpu_dpm_display_disable_memory_clock_switch(struct amdgpu_device *adev, 155913f5dbd6SEvan Quan bool disable_memory_clock_switch) 156013f5dbd6SEvan Quan { 156113f5dbd6SEvan Quan const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 15623712e7a4SEvan Quan int ret = 0; 156313f5dbd6SEvan Quan 156413f5dbd6SEvan Quan if (!pp_funcs->display_disable_memory_clock_switch) 156513f5dbd6SEvan Quan return 0; 156613f5dbd6SEvan Quan 15673712e7a4SEvan Quan mutex_lock(&adev->pm.mutex); 15683712e7a4SEvan Quan ret = pp_funcs->display_disable_memory_clock_switch(adev->powerplay.pp_handle, 156913f5dbd6SEvan Quan disable_memory_clock_switch); 15703712e7a4SEvan Quan mutex_unlock(&adev->pm.mutex); 15713712e7a4SEvan Quan 15723712e7a4SEvan Quan return ret; 157313f5dbd6SEvan Quan } 157413f5dbd6SEvan Quan 157513f5dbd6SEvan Quan int amdgpu_dpm_get_max_sustainable_clocks_by_dc(struct amdgpu_device *adev, 157613f5dbd6SEvan Quan struct pp_smu_nv_clock_table *max_clocks) 157713f5dbd6SEvan Quan { 157813f5dbd6SEvan Quan const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 15793712e7a4SEvan Quan int ret = 0; 158013f5dbd6SEvan Quan 158113f5dbd6SEvan Quan if (!pp_funcs->get_max_sustainable_clocks_by_dc) 158213f5dbd6SEvan Quan return -EOPNOTSUPP; 158313f5dbd6SEvan Quan 15843712e7a4SEvan Quan mutex_lock(&adev->pm.mutex); 15853712e7a4SEvan Quan ret = pp_funcs->get_max_sustainable_clocks_by_dc(adev->powerplay.pp_handle, 158613f5dbd6SEvan Quan max_clocks); 15873712e7a4SEvan Quan mutex_unlock(&adev->pm.mutex); 15883712e7a4SEvan Quan 15893712e7a4SEvan Quan return ret; 159013f5dbd6SEvan Quan } 159113f5dbd6SEvan Quan 159213f5dbd6SEvan Quan enum pp_smu_status amdgpu_dpm_get_uclk_dpm_states(struct amdgpu_device *adev, 159313f5dbd6SEvan Quan unsigned int *clock_values_in_khz, 159413f5dbd6SEvan Quan unsigned int *num_states) 159513f5dbd6SEvan Quan { 159613f5dbd6SEvan Quan const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 15973712e7a4SEvan Quan int ret = 0; 159813f5dbd6SEvan Quan 159913f5dbd6SEvan Quan if (!pp_funcs->get_uclk_dpm_states) 160013f5dbd6SEvan Quan return -EOPNOTSUPP; 160113f5dbd6SEvan Quan 16023712e7a4SEvan Quan mutex_lock(&adev->pm.mutex); 16033712e7a4SEvan Quan ret = pp_funcs->get_uclk_dpm_states(adev->powerplay.pp_handle, 160413f5dbd6SEvan Quan clock_values_in_khz, 160513f5dbd6SEvan Quan num_states); 16063712e7a4SEvan Quan mutex_unlock(&adev->pm.mutex); 16073712e7a4SEvan Quan 16083712e7a4SEvan Quan return ret; 160913f5dbd6SEvan Quan } 161013f5dbd6SEvan Quan 161113f5dbd6SEvan Quan int amdgpu_dpm_get_dpm_clock_table(struct amdgpu_device *adev, 161213f5dbd6SEvan Quan struct dpm_clocks *clock_table) 161313f5dbd6SEvan Quan { 161413f5dbd6SEvan Quan const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 16153712e7a4SEvan Quan int ret = 0; 161613f5dbd6SEvan Quan 161713f5dbd6SEvan Quan if (!pp_funcs->get_dpm_clock_table) 161813f5dbd6SEvan Quan return -EOPNOTSUPP; 161913f5dbd6SEvan Quan 16203712e7a4SEvan Quan mutex_lock(&adev->pm.mutex); 16213712e7a4SEvan Quan ret = pp_funcs->get_dpm_clock_table(adev->powerplay.pp_handle, 162213f5dbd6SEvan Quan clock_table); 16233712e7a4SEvan Quan mutex_unlock(&adev->pm.mutex); 16243712e7a4SEvan Quan 16253712e7a4SEvan Quan return ret; 162613f5dbd6SEvan Quan } 1627