1e098bc96SEvan Quan /* 2e098bc96SEvan Quan * Copyright 2011 Advanced Micro Devices, Inc. 3e098bc96SEvan Quan * 4e098bc96SEvan Quan * Permission is hereby granted, free of charge, to any person obtaining a 5e098bc96SEvan Quan * copy of this software and associated documentation files (the "Software"), 6e098bc96SEvan Quan * to deal in the Software without restriction, including without limitation 7e098bc96SEvan Quan * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8e098bc96SEvan Quan * and/or sell copies of the Software, and to permit persons to whom the 9e098bc96SEvan Quan * Software is furnished to do so, subject to the following conditions: 10e098bc96SEvan Quan * 11e098bc96SEvan Quan * The above copyright notice and this permission notice shall be included in 12e098bc96SEvan Quan * all copies or substantial portions of the Software. 13e098bc96SEvan Quan * 14e098bc96SEvan Quan * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15e098bc96SEvan Quan * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16e098bc96SEvan Quan * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17e098bc96SEvan Quan * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18e098bc96SEvan Quan * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19e098bc96SEvan Quan * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20e098bc96SEvan Quan * OTHER DEALINGS IN THE SOFTWARE. 21e098bc96SEvan Quan * 22e098bc96SEvan Quan * Authors: Alex Deucher 23e098bc96SEvan Quan */ 24e098bc96SEvan Quan 25e098bc96SEvan Quan #include "amdgpu.h" 26e098bc96SEvan Quan #include "amdgpu_atombios.h" 27e098bc96SEvan Quan #include "amdgpu_i2c.h" 28e098bc96SEvan Quan #include "amdgpu_dpm.h" 29e098bc96SEvan Quan #include "atom.h" 30e098bc96SEvan Quan #include "amd_pcie.h" 31e098bc96SEvan Quan #include "amdgpu_display.h" 32e098bc96SEvan Quan #include "hwmgr.h" 33e098bc96SEvan Quan #include <linux/power_supply.h> 34ebfc2533SEvan Quan #include "amdgpu_smu.h" 35e098bc96SEvan Quan 36d4481576SEvan Quan #define amdgpu_dpm_enable_bapm(adev, e) \ 37d4481576SEvan Quan ((adev)->powerplay.pp_funcs->enable_bapm((adev)->powerplay.pp_handle, (e))) 38d4481576SEvan Quan 39e098bc96SEvan Quan int amdgpu_dpm_get_sclk(struct amdgpu_device *adev, bool low) 40e098bc96SEvan Quan { 41bc7d6c12SDarren Powell const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 423712e7a4SEvan Quan int ret = 0; 43e098bc96SEvan Quan 443712e7a4SEvan Quan if (!pp_funcs->get_sclk) 453712e7a4SEvan Quan return 0; 463712e7a4SEvan Quan 473712e7a4SEvan Quan mutex_lock(&adev->pm.mutex); 483712e7a4SEvan Quan ret = pp_funcs->get_sclk((adev)->powerplay.pp_handle, 493712e7a4SEvan Quan low); 503712e7a4SEvan Quan mutex_unlock(&adev->pm.mutex); 513712e7a4SEvan Quan 523712e7a4SEvan Quan return ret; 53e098bc96SEvan Quan } 54e098bc96SEvan Quan 55e098bc96SEvan Quan int amdgpu_dpm_get_mclk(struct amdgpu_device *adev, bool low) 56e098bc96SEvan Quan { 57bc7d6c12SDarren Powell const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 583712e7a4SEvan Quan int ret = 0; 59e098bc96SEvan Quan 603712e7a4SEvan Quan if (!pp_funcs->get_mclk) 613712e7a4SEvan Quan return 0; 623712e7a4SEvan Quan 633712e7a4SEvan Quan mutex_lock(&adev->pm.mutex); 643712e7a4SEvan Quan ret = pp_funcs->get_mclk((adev)->powerplay.pp_handle, 653712e7a4SEvan Quan low); 663712e7a4SEvan Quan mutex_unlock(&adev->pm.mutex); 673712e7a4SEvan Quan 683712e7a4SEvan Quan return ret; 69e098bc96SEvan Quan } 70e098bc96SEvan Quan 71e098bc96SEvan Quan int amdgpu_dpm_set_powergating_by_smu(struct amdgpu_device *adev, uint32_t block_type, bool gate) 72e098bc96SEvan Quan { 73e098bc96SEvan Quan int ret = 0; 74bc7d6c12SDarren Powell const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 756ee27ee2SEvan Quan enum ip_power_state pwr_state = gate ? POWER_STATE_OFF : POWER_STATE_ON; 766ee27ee2SEvan Quan 776ee27ee2SEvan Quan if (atomic_read(&adev->pm.pwr_state[block_type]) == pwr_state) { 786ee27ee2SEvan Quan dev_dbg(adev->dev, "IP block%d already in the target %s state!", 796ee27ee2SEvan Quan block_type, gate ? "gate" : "ungate"); 806ee27ee2SEvan Quan return 0; 816ee27ee2SEvan Quan } 82e098bc96SEvan Quan 833712e7a4SEvan Quan mutex_lock(&adev->pm.mutex); 843712e7a4SEvan Quan 85e098bc96SEvan Quan switch (block_type) { 86e098bc96SEvan Quan case AMD_IP_BLOCK_TYPE_UVD: 87e098bc96SEvan Quan case AMD_IP_BLOCK_TYPE_VCE: 88e098bc96SEvan Quan case AMD_IP_BLOCK_TYPE_GFX: 89e098bc96SEvan Quan case AMD_IP_BLOCK_TYPE_VCN: 90e098bc96SEvan Quan case AMD_IP_BLOCK_TYPE_SDMA: 91e098bc96SEvan Quan case AMD_IP_BLOCK_TYPE_JPEG: 92e098bc96SEvan Quan case AMD_IP_BLOCK_TYPE_GMC: 93e098bc96SEvan Quan case AMD_IP_BLOCK_TYPE_ACP: 943712e7a4SEvan Quan if (pp_funcs && pp_funcs->set_powergating_by_smu) 95bc7d6c12SDarren Powell ret = (pp_funcs->set_powergating_by_smu( 96e098bc96SEvan Quan (adev)->powerplay.pp_handle, block_type, gate)); 97e098bc96SEvan Quan break; 98e098bc96SEvan Quan default: 99e098bc96SEvan Quan break; 100e098bc96SEvan Quan } 101e098bc96SEvan Quan 1026ee27ee2SEvan Quan if (!ret) 1036ee27ee2SEvan Quan atomic_set(&adev->pm.pwr_state[block_type], pwr_state); 1046ee27ee2SEvan Quan 1053712e7a4SEvan Quan mutex_unlock(&adev->pm.mutex); 1063712e7a4SEvan Quan 107e098bc96SEvan Quan return ret; 108e098bc96SEvan Quan } 109e098bc96SEvan Quan 110e098bc96SEvan Quan int amdgpu_dpm_baco_enter(struct amdgpu_device *adev) 111e098bc96SEvan Quan { 112e098bc96SEvan Quan const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 113e098bc96SEvan Quan void *pp_handle = adev->powerplay.pp_handle; 114e098bc96SEvan Quan int ret = 0; 115e098bc96SEvan Quan 116e098bc96SEvan Quan if (!pp_funcs || !pp_funcs->set_asic_baco_state) 117e098bc96SEvan Quan return -ENOENT; 118e098bc96SEvan Quan 1193712e7a4SEvan Quan mutex_lock(&adev->pm.mutex); 1203712e7a4SEvan Quan 121e098bc96SEvan Quan /* enter BACO state */ 122e098bc96SEvan Quan ret = pp_funcs->set_asic_baco_state(pp_handle, 1); 123e098bc96SEvan Quan 1243712e7a4SEvan Quan mutex_unlock(&adev->pm.mutex); 1253712e7a4SEvan Quan 126e098bc96SEvan Quan return ret; 127e098bc96SEvan Quan } 128e098bc96SEvan Quan 129e098bc96SEvan Quan int amdgpu_dpm_baco_exit(struct amdgpu_device *adev) 130e098bc96SEvan Quan { 131e098bc96SEvan Quan const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 132e098bc96SEvan Quan void *pp_handle = adev->powerplay.pp_handle; 133e098bc96SEvan Quan int ret = 0; 134e098bc96SEvan Quan 135e098bc96SEvan Quan if (!pp_funcs || !pp_funcs->set_asic_baco_state) 136e098bc96SEvan Quan return -ENOENT; 137e098bc96SEvan Quan 1383712e7a4SEvan Quan mutex_lock(&adev->pm.mutex); 1393712e7a4SEvan Quan 140e098bc96SEvan Quan /* exit BACO state */ 141e098bc96SEvan Quan ret = pp_funcs->set_asic_baco_state(pp_handle, 0); 142e098bc96SEvan Quan 1433712e7a4SEvan Quan mutex_unlock(&adev->pm.mutex); 1443712e7a4SEvan Quan 145e098bc96SEvan Quan return ret; 146e098bc96SEvan Quan } 147e098bc96SEvan Quan 148e098bc96SEvan Quan int amdgpu_dpm_set_mp1_state(struct amdgpu_device *adev, 149e098bc96SEvan Quan enum pp_mp1_state mp1_state) 150e098bc96SEvan Quan { 151e098bc96SEvan Quan int ret = 0; 152bab0f602SDarren Powell const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 153e098bc96SEvan Quan 154bab0f602SDarren Powell if (pp_funcs && pp_funcs->set_mp1_state) { 1553712e7a4SEvan Quan mutex_lock(&adev->pm.mutex); 1563712e7a4SEvan Quan 157bab0f602SDarren Powell ret = pp_funcs->set_mp1_state( 158e098bc96SEvan Quan adev->powerplay.pp_handle, 159e098bc96SEvan Quan mp1_state); 1603712e7a4SEvan Quan 1613712e7a4SEvan Quan mutex_unlock(&adev->pm.mutex); 162e098bc96SEvan Quan } 163e098bc96SEvan Quan 164e098bc96SEvan Quan return ret; 165e098bc96SEvan Quan } 166e098bc96SEvan Quan 167e098bc96SEvan Quan bool amdgpu_dpm_is_baco_supported(struct amdgpu_device *adev) 168e098bc96SEvan Quan { 169e098bc96SEvan Quan const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 170e098bc96SEvan Quan void *pp_handle = adev->powerplay.pp_handle; 171e098bc96SEvan Quan bool baco_cap; 1723712e7a4SEvan Quan int ret = 0; 173e098bc96SEvan Quan 174e098bc96SEvan Quan if (!pp_funcs || !pp_funcs->get_asic_baco_capability) 175e098bc96SEvan Quan return false; 176e098bc96SEvan Quan 1773712e7a4SEvan Quan mutex_lock(&adev->pm.mutex); 178e098bc96SEvan Quan 1793712e7a4SEvan Quan ret = pp_funcs->get_asic_baco_capability(pp_handle, 1803712e7a4SEvan Quan &baco_cap); 1813712e7a4SEvan Quan 1823712e7a4SEvan Quan mutex_unlock(&adev->pm.mutex); 1833712e7a4SEvan Quan 1843712e7a4SEvan Quan return ret ? false : baco_cap; 185e098bc96SEvan Quan } 186e098bc96SEvan Quan 187e098bc96SEvan Quan int amdgpu_dpm_mode2_reset(struct amdgpu_device *adev) 188e098bc96SEvan Quan { 189e098bc96SEvan Quan const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 190e098bc96SEvan Quan void *pp_handle = adev->powerplay.pp_handle; 1913712e7a4SEvan Quan int ret = 0; 192e098bc96SEvan Quan 193e098bc96SEvan Quan if (!pp_funcs || !pp_funcs->asic_reset_mode_2) 194e098bc96SEvan Quan return -ENOENT; 195e098bc96SEvan Quan 1963712e7a4SEvan Quan mutex_lock(&adev->pm.mutex); 1973712e7a4SEvan Quan 1983712e7a4SEvan Quan ret = pp_funcs->asic_reset_mode_2(pp_handle); 1993712e7a4SEvan Quan 2003712e7a4SEvan Quan mutex_unlock(&adev->pm.mutex); 2013712e7a4SEvan Quan 2023712e7a4SEvan Quan return ret; 203e098bc96SEvan Quan } 204e098bc96SEvan Quan 205e098bc96SEvan Quan int amdgpu_dpm_baco_reset(struct amdgpu_device *adev) 206e098bc96SEvan Quan { 207e098bc96SEvan Quan const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 208e098bc96SEvan Quan void *pp_handle = adev->powerplay.pp_handle; 209e098bc96SEvan Quan int ret = 0; 210e098bc96SEvan Quan 2119ab5001aSDarren Powell if (!pp_funcs || !pp_funcs->set_asic_baco_state) 212e098bc96SEvan Quan return -ENOENT; 213e098bc96SEvan Quan 2143712e7a4SEvan Quan mutex_lock(&adev->pm.mutex); 2153712e7a4SEvan Quan 216e098bc96SEvan Quan /* enter BACO state */ 217e098bc96SEvan Quan ret = pp_funcs->set_asic_baco_state(pp_handle, 1); 218e098bc96SEvan Quan if (ret) 2193712e7a4SEvan Quan goto out; 220e098bc96SEvan Quan 221e098bc96SEvan Quan /* exit BACO state */ 222e098bc96SEvan Quan ret = pp_funcs->set_asic_baco_state(pp_handle, 0); 223e098bc96SEvan Quan 2243712e7a4SEvan Quan out: 2253712e7a4SEvan Quan mutex_unlock(&adev->pm.mutex); 2263712e7a4SEvan Quan return ret; 227e098bc96SEvan Quan } 228e098bc96SEvan Quan 229e098bc96SEvan Quan bool amdgpu_dpm_is_mode1_reset_supported(struct amdgpu_device *adev) 230e098bc96SEvan Quan { 231ebfc2533SEvan Quan struct smu_context *smu = adev->powerplay.pp_handle; 2323712e7a4SEvan Quan bool support_mode1_reset = false; 233e098bc96SEvan Quan 2343712e7a4SEvan Quan if (is_support_sw_smu(adev)) { 2353712e7a4SEvan Quan mutex_lock(&adev->pm.mutex); 2363712e7a4SEvan Quan support_mode1_reset = smu_mode1_reset_is_support(smu); 2373712e7a4SEvan Quan mutex_unlock(&adev->pm.mutex); 2383712e7a4SEvan Quan } 239e098bc96SEvan Quan 2403712e7a4SEvan Quan return support_mode1_reset; 241e098bc96SEvan Quan } 242e098bc96SEvan Quan 243e098bc96SEvan Quan int amdgpu_dpm_mode1_reset(struct amdgpu_device *adev) 244e098bc96SEvan Quan { 245ebfc2533SEvan Quan struct smu_context *smu = adev->powerplay.pp_handle; 2463712e7a4SEvan Quan int ret = -EOPNOTSUPP; 247e098bc96SEvan Quan 2483712e7a4SEvan Quan if (is_support_sw_smu(adev)) { 2493712e7a4SEvan Quan mutex_lock(&adev->pm.mutex); 2503712e7a4SEvan Quan ret = smu_mode1_reset(smu); 2513712e7a4SEvan Quan mutex_unlock(&adev->pm.mutex); 2523712e7a4SEvan Quan } 253e098bc96SEvan Quan 2543712e7a4SEvan Quan return ret; 255e098bc96SEvan Quan } 256e098bc96SEvan Quan 257e098bc96SEvan Quan int amdgpu_dpm_switch_power_profile(struct amdgpu_device *adev, 258e098bc96SEvan Quan enum PP_SMC_POWER_PROFILE type, 259e098bc96SEvan Quan bool en) 260e098bc96SEvan Quan { 261bab0f602SDarren Powell const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 262e098bc96SEvan Quan int ret = 0; 263e098bc96SEvan Quan 2647cf7a392SJingwen Chen if (amdgpu_sriov_vf(adev)) 2657cf7a392SJingwen Chen return 0; 2667cf7a392SJingwen Chen 2673712e7a4SEvan Quan if (pp_funcs && pp_funcs->switch_power_profile) { 2683712e7a4SEvan Quan mutex_lock(&adev->pm.mutex); 269bab0f602SDarren Powell ret = pp_funcs->switch_power_profile( 270e098bc96SEvan Quan adev->powerplay.pp_handle, type, en); 2713712e7a4SEvan Quan mutex_unlock(&adev->pm.mutex); 2723712e7a4SEvan Quan } 273e098bc96SEvan Quan 274e098bc96SEvan Quan return ret; 275e098bc96SEvan Quan } 276e098bc96SEvan Quan 277e098bc96SEvan Quan int amdgpu_dpm_set_xgmi_pstate(struct amdgpu_device *adev, 278e098bc96SEvan Quan uint32_t pstate) 279e098bc96SEvan Quan { 280bab0f602SDarren Powell const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 281e098bc96SEvan Quan int ret = 0; 282e098bc96SEvan Quan 2833712e7a4SEvan Quan if (pp_funcs && pp_funcs->set_xgmi_pstate) { 2843712e7a4SEvan Quan mutex_lock(&adev->pm.mutex); 285bab0f602SDarren Powell ret = pp_funcs->set_xgmi_pstate(adev->powerplay.pp_handle, 286e098bc96SEvan Quan pstate); 2873712e7a4SEvan Quan mutex_unlock(&adev->pm.mutex); 2883712e7a4SEvan Quan } 289e098bc96SEvan Quan 290e098bc96SEvan Quan return ret; 291e098bc96SEvan Quan } 292e098bc96SEvan Quan 293e098bc96SEvan Quan int amdgpu_dpm_set_df_cstate(struct amdgpu_device *adev, 294e098bc96SEvan Quan uint32_t cstate) 295e098bc96SEvan Quan { 296e098bc96SEvan Quan int ret = 0; 297e098bc96SEvan Quan const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 298e098bc96SEvan Quan void *pp_handle = adev->powerplay.pp_handle; 299e098bc96SEvan Quan 3003712e7a4SEvan Quan if (pp_funcs && pp_funcs->set_df_cstate) { 3013712e7a4SEvan Quan mutex_lock(&adev->pm.mutex); 302e098bc96SEvan Quan ret = pp_funcs->set_df_cstate(pp_handle, cstate); 3033712e7a4SEvan Quan mutex_unlock(&adev->pm.mutex); 3043712e7a4SEvan Quan } 305e098bc96SEvan Quan 306e098bc96SEvan Quan return ret; 307e098bc96SEvan Quan } 308e098bc96SEvan Quan 309e098bc96SEvan Quan int amdgpu_dpm_allow_xgmi_power_down(struct amdgpu_device *adev, bool en) 310e098bc96SEvan Quan { 311ebfc2533SEvan Quan struct smu_context *smu = adev->powerplay.pp_handle; 3123712e7a4SEvan Quan int ret = 0; 313e098bc96SEvan Quan 3143712e7a4SEvan Quan if (is_support_sw_smu(adev)) { 3153712e7a4SEvan Quan mutex_lock(&adev->pm.mutex); 3163712e7a4SEvan Quan ret = smu_allow_xgmi_power_down(smu, en); 3173712e7a4SEvan Quan mutex_unlock(&adev->pm.mutex); 3183712e7a4SEvan Quan } 319e098bc96SEvan Quan 3203712e7a4SEvan Quan return ret; 321e098bc96SEvan Quan } 322e098bc96SEvan Quan 323e098bc96SEvan Quan int amdgpu_dpm_enable_mgpu_fan_boost(struct amdgpu_device *adev) 324e098bc96SEvan Quan { 325e098bc96SEvan Quan void *pp_handle = adev->powerplay.pp_handle; 326e098bc96SEvan Quan const struct amd_pm_funcs *pp_funcs = 327e098bc96SEvan Quan adev->powerplay.pp_funcs; 328e098bc96SEvan Quan int ret = 0; 329e098bc96SEvan Quan 3303712e7a4SEvan Quan if (pp_funcs && pp_funcs->enable_mgpu_fan_boost) { 3313712e7a4SEvan Quan mutex_lock(&adev->pm.mutex); 332e098bc96SEvan Quan ret = pp_funcs->enable_mgpu_fan_boost(pp_handle); 3333712e7a4SEvan Quan mutex_unlock(&adev->pm.mutex); 3343712e7a4SEvan Quan } 335e098bc96SEvan Quan 336e098bc96SEvan Quan return ret; 337e098bc96SEvan Quan } 338e098bc96SEvan Quan 339e098bc96SEvan Quan int amdgpu_dpm_set_clockgating_by_smu(struct amdgpu_device *adev, 340e098bc96SEvan Quan uint32_t msg_id) 341e098bc96SEvan Quan { 342e098bc96SEvan Quan void *pp_handle = adev->powerplay.pp_handle; 343e098bc96SEvan Quan const struct amd_pm_funcs *pp_funcs = 344e098bc96SEvan Quan adev->powerplay.pp_funcs; 345e098bc96SEvan Quan int ret = 0; 346e098bc96SEvan Quan 3473712e7a4SEvan Quan if (pp_funcs && pp_funcs->set_clockgating_by_smu) { 3483712e7a4SEvan Quan mutex_lock(&adev->pm.mutex); 349e098bc96SEvan Quan ret = pp_funcs->set_clockgating_by_smu(pp_handle, 350e098bc96SEvan Quan msg_id); 3513712e7a4SEvan Quan mutex_unlock(&adev->pm.mutex); 3523712e7a4SEvan Quan } 353e098bc96SEvan Quan 354e098bc96SEvan Quan return ret; 355e098bc96SEvan Quan } 356e098bc96SEvan Quan 357e098bc96SEvan Quan int amdgpu_dpm_smu_i2c_bus_access(struct amdgpu_device *adev, 358e098bc96SEvan Quan bool acquire) 359e098bc96SEvan Quan { 360e098bc96SEvan Quan void *pp_handle = adev->powerplay.pp_handle; 361e098bc96SEvan Quan const struct amd_pm_funcs *pp_funcs = 362e098bc96SEvan Quan adev->powerplay.pp_funcs; 363e098bc96SEvan Quan int ret = -EOPNOTSUPP; 364e098bc96SEvan Quan 3653712e7a4SEvan Quan if (pp_funcs && pp_funcs->smu_i2c_bus_access) { 3663712e7a4SEvan Quan mutex_lock(&adev->pm.mutex); 367e098bc96SEvan Quan ret = pp_funcs->smu_i2c_bus_access(pp_handle, 368e098bc96SEvan Quan acquire); 3693712e7a4SEvan Quan mutex_unlock(&adev->pm.mutex); 3703712e7a4SEvan Quan } 371e098bc96SEvan Quan 372e098bc96SEvan Quan return ret; 373e098bc96SEvan Quan } 374e098bc96SEvan Quan 375e098bc96SEvan Quan void amdgpu_pm_acpi_event_handler(struct amdgpu_device *adev) 376e098bc96SEvan Quan { 377e098bc96SEvan Quan if (adev->pm.dpm_enabled) { 378e098bc96SEvan Quan mutex_lock(&adev->pm.mutex); 379e098bc96SEvan Quan if (power_supply_is_system_supplied() > 0) 380e098bc96SEvan Quan adev->pm.ac_power = true; 381e098bc96SEvan Quan else 382e098bc96SEvan Quan adev->pm.ac_power = false; 3833712e7a4SEvan Quan 384e098bc96SEvan Quan if (adev->powerplay.pp_funcs && 385e098bc96SEvan Quan adev->powerplay.pp_funcs->enable_bapm) 386e098bc96SEvan Quan amdgpu_dpm_enable_bapm(adev, adev->pm.ac_power); 387e098bc96SEvan Quan 388e098bc96SEvan Quan if (is_support_sw_smu(adev)) 389ebfc2533SEvan Quan smu_set_ac_dc(adev->powerplay.pp_handle); 3903712e7a4SEvan Quan 3913712e7a4SEvan Quan mutex_unlock(&adev->pm.mutex); 392e098bc96SEvan Quan } 393e098bc96SEvan Quan } 394e098bc96SEvan Quan 395e098bc96SEvan Quan int amdgpu_dpm_read_sensor(struct amdgpu_device *adev, enum amd_pp_sensors sensor, 396e098bc96SEvan Quan void *data, uint32_t *size) 397e098bc96SEvan Quan { 3989ab5001aSDarren Powell const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 3993712e7a4SEvan Quan int ret = -EINVAL; 400e098bc96SEvan Quan 401e098bc96SEvan Quan if (!data || !size) 402e098bc96SEvan Quan return -EINVAL; 403e098bc96SEvan Quan 4043712e7a4SEvan Quan if (pp_funcs && pp_funcs->read_sensor) { 4053712e7a4SEvan Quan mutex_lock(&adev->pm.mutex); 4063712e7a4SEvan Quan ret = pp_funcs->read_sensor(adev->powerplay.pp_handle, 4073712e7a4SEvan Quan sensor, 4083712e7a4SEvan Quan data, 4093712e7a4SEvan Quan size); 4103712e7a4SEvan Quan mutex_unlock(&adev->pm.mutex); 4113712e7a4SEvan Quan } 412e098bc96SEvan Quan 413e098bc96SEvan Quan return ret; 414e098bc96SEvan Quan } 415e098bc96SEvan Quan 41684176663SEvan Quan void amdgpu_dpm_compute_clocks(struct amdgpu_device *adev) 417e098bc96SEvan Quan { 4186ddbd37fSEvan Quan const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 419e098bc96SEvan Quan 420e098bc96SEvan Quan if (!adev->pm.dpm_enabled) 421e098bc96SEvan Quan return; 422e098bc96SEvan Quan 4236ddbd37fSEvan Quan if (!pp_funcs->pm_compute_clocks) 4246ddbd37fSEvan Quan return; 425e098bc96SEvan Quan 4263712e7a4SEvan Quan mutex_lock(&adev->pm.mutex); 4276ddbd37fSEvan Quan pp_funcs->pm_compute_clocks(adev->powerplay.pp_handle); 4283712e7a4SEvan Quan mutex_unlock(&adev->pm.mutex); 429e098bc96SEvan Quan } 430e098bc96SEvan Quan 431e098bc96SEvan Quan void amdgpu_dpm_enable_uvd(struct amdgpu_device *adev, bool enable) 432e098bc96SEvan Quan { 433e098bc96SEvan Quan int ret = 0; 434e098bc96SEvan Quan 435e098bc96SEvan Quan ret = amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_UVD, !enable); 436e098bc96SEvan Quan if (ret) 437e098bc96SEvan Quan DRM_ERROR("Dpm %s uvd failed, ret = %d. \n", 438e098bc96SEvan Quan enable ? "enable" : "disable", ret); 439e098bc96SEvan Quan } 440e098bc96SEvan Quan 441e098bc96SEvan Quan void amdgpu_dpm_enable_vce(struct amdgpu_device *adev, bool enable) 442e098bc96SEvan Quan { 443e098bc96SEvan Quan int ret = 0; 444e098bc96SEvan Quan 445e098bc96SEvan Quan ret = amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_VCE, !enable); 446e098bc96SEvan Quan if (ret) 447e098bc96SEvan Quan DRM_ERROR("Dpm %s vce failed, ret = %d. \n", 448e098bc96SEvan Quan enable ? "enable" : "disable", ret); 449e098bc96SEvan Quan } 450e098bc96SEvan Quan 451e098bc96SEvan Quan void amdgpu_dpm_enable_jpeg(struct amdgpu_device *adev, bool enable) 452e098bc96SEvan Quan { 453e098bc96SEvan Quan int ret = 0; 454e098bc96SEvan Quan 455e098bc96SEvan Quan ret = amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_JPEG, !enable); 456e098bc96SEvan Quan if (ret) 457e098bc96SEvan Quan DRM_ERROR("Dpm %s jpeg failed, ret = %d. \n", 458e098bc96SEvan Quan enable ? "enable" : "disable", ret); 459e098bc96SEvan Quan } 460e098bc96SEvan Quan 461e098bc96SEvan Quan int amdgpu_pm_load_smu_firmware(struct amdgpu_device *adev, uint32_t *smu_version) 462e098bc96SEvan Quan { 4633712e7a4SEvan Quan const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 4643712e7a4SEvan Quan int r = 0; 465e098bc96SEvan Quan 4661613f346SFlora Cui if (!pp_funcs || !pp_funcs->load_firmware) 4673712e7a4SEvan Quan return 0; 4683712e7a4SEvan Quan 4693712e7a4SEvan Quan mutex_lock(&adev->pm.mutex); 4703712e7a4SEvan Quan r = pp_funcs->load_firmware(adev->powerplay.pp_handle); 471e098bc96SEvan Quan if (r) { 472e098bc96SEvan Quan pr_err("smu firmware loading failed\n"); 4733712e7a4SEvan Quan goto out; 474e098bc96SEvan Quan } 4752e4b2f7bSEvan Quan 4762e4b2f7bSEvan Quan if (smu_version) 477e098bc96SEvan Quan *smu_version = adev->pm.fw_version; 4782e4b2f7bSEvan Quan 4793712e7a4SEvan Quan out: 4803712e7a4SEvan Quan mutex_unlock(&adev->pm.mutex); 4813712e7a4SEvan Quan return r; 482e098bc96SEvan Quan } 483bc143d8bSEvan Quan 484bc143d8bSEvan Quan int amdgpu_dpm_handle_passthrough_sbr(struct amdgpu_device *adev, bool enable) 485bc143d8bSEvan Quan { 4863712e7a4SEvan Quan int ret = 0; 4873712e7a4SEvan Quan 4883712e7a4SEvan Quan if (is_support_sw_smu(adev)) { 4893712e7a4SEvan Quan mutex_lock(&adev->pm.mutex); 4903712e7a4SEvan Quan ret = smu_handle_passthrough_sbr(adev->powerplay.pp_handle, 4913712e7a4SEvan Quan enable); 4923712e7a4SEvan Quan mutex_unlock(&adev->pm.mutex); 4933712e7a4SEvan Quan } 4943712e7a4SEvan Quan 4953712e7a4SEvan Quan return ret; 496bc143d8bSEvan Quan } 497bc143d8bSEvan Quan 498bc143d8bSEvan Quan int amdgpu_dpm_send_hbm_bad_pages_num(struct amdgpu_device *adev, uint32_t size) 499bc143d8bSEvan Quan { 500ebfc2533SEvan Quan struct smu_context *smu = adev->powerplay.pp_handle; 5013712e7a4SEvan Quan int ret = 0; 502ebfc2533SEvan Quan 5033712e7a4SEvan Quan mutex_lock(&adev->pm.mutex); 5043712e7a4SEvan Quan ret = smu_send_hbm_bad_pages_num(smu, size); 5053712e7a4SEvan Quan mutex_unlock(&adev->pm.mutex); 5063712e7a4SEvan Quan 5073712e7a4SEvan Quan return ret; 508bc143d8bSEvan Quan } 509bc143d8bSEvan Quan 510bc143d8bSEvan Quan int amdgpu_dpm_get_dpm_freq_range(struct amdgpu_device *adev, 511bc143d8bSEvan Quan enum pp_clock_type type, 512bc143d8bSEvan Quan uint32_t *min, 513bc143d8bSEvan Quan uint32_t *max) 514bc143d8bSEvan Quan { 5153712e7a4SEvan Quan int ret = 0; 5163712e7a4SEvan Quan 5173712e7a4SEvan Quan if (type != PP_SCLK) 5183712e7a4SEvan Quan return -EINVAL; 5193712e7a4SEvan Quan 520bc143d8bSEvan Quan if (!is_support_sw_smu(adev)) 521bc143d8bSEvan Quan return -EOPNOTSUPP; 522bc143d8bSEvan Quan 5233712e7a4SEvan Quan mutex_lock(&adev->pm.mutex); 5243712e7a4SEvan Quan ret = smu_get_dpm_freq_range(adev->powerplay.pp_handle, 5253712e7a4SEvan Quan SMU_SCLK, 5263712e7a4SEvan Quan min, 5273712e7a4SEvan Quan max); 5283712e7a4SEvan Quan mutex_unlock(&adev->pm.mutex); 5293712e7a4SEvan Quan 5303712e7a4SEvan Quan return ret; 531bc143d8bSEvan Quan } 532bc143d8bSEvan Quan 533bc143d8bSEvan Quan int amdgpu_dpm_set_soft_freq_range(struct amdgpu_device *adev, 534bc143d8bSEvan Quan enum pp_clock_type type, 535bc143d8bSEvan Quan uint32_t min, 536bc143d8bSEvan Quan uint32_t max) 537bc143d8bSEvan Quan { 538ebfc2533SEvan Quan struct smu_context *smu = adev->powerplay.pp_handle; 5393712e7a4SEvan Quan int ret = 0; 5403712e7a4SEvan Quan 5413712e7a4SEvan Quan if (type != PP_SCLK) 5423712e7a4SEvan Quan return -EINVAL; 543ebfc2533SEvan Quan 544bc143d8bSEvan Quan if (!is_support_sw_smu(adev)) 545bc143d8bSEvan Quan return -EOPNOTSUPP; 546bc143d8bSEvan Quan 5473712e7a4SEvan Quan mutex_lock(&adev->pm.mutex); 5483712e7a4SEvan Quan ret = smu_set_soft_freq_range(smu, 5493712e7a4SEvan Quan SMU_SCLK, 5503712e7a4SEvan Quan min, 5513712e7a4SEvan Quan max); 5523712e7a4SEvan Quan mutex_unlock(&adev->pm.mutex); 5533712e7a4SEvan Quan 5543712e7a4SEvan Quan return ret; 555bc143d8bSEvan Quan } 556bc143d8bSEvan Quan 55713f5dbd6SEvan Quan int amdgpu_dpm_write_watermarks_table(struct amdgpu_device *adev) 55813f5dbd6SEvan Quan { 559ebfc2533SEvan Quan struct smu_context *smu = adev->powerplay.pp_handle; 5603712e7a4SEvan Quan int ret = 0; 561ebfc2533SEvan Quan 56213f5dbd6SEvan Quan if (!is_support_sw_smu(adev)) 56313f5dbd6SEvan Quan return 0; 56413f5dbd6SEvan Quan 5653712e7a4SEvan Quan mutex_lock(&adev->pm.mutex); 5663712e7a4SEvan Quan ret = smu_write_watermarks_table(smu); 5673712e7a4SEvan Quan mutex_unlock(&adev->pm.mutex); 5683712e7a4SEvan Quan 5693712e7a4SEvan Quan return ret; 57013f5dbd6SEvan Quan } 57113f5dbd6SEvan Quan 572bc143d8bSEvan Quan int amdgpu_dpm_wait_for_event(struct amdgpu_device *adev, 573bc143d8bSEvan Quan enum smu_event_type event, 574bc143d8bSEvan Quan uint64_t event_arg) 575bc143d8bSEvan Quan { 576ebfc2533SEvan Quan struct smu_context *smu = adev->powerplay.pp_handle; 5773712e7a4SEvan Quan int ret = 0; 578ebfc2533SEvan Quan 579bc143d8bSEvan Quan if (!is_support_sw_smu(adev)) 580bc143d8bSEvan Quan return -EOPNOTSUPP; 581bc143d8bSEvan Quan 5823712e7a4SEvan Quan mutex_lock(&adev->pm.mutex); 5833712e7a4SEvan Quan ret = smu_wait_for_event(smu, event, event_arg); 5843712e7a4SEvan Quan mutex_unlock(&adev->pm.mutex); 5853712e7a4SEvan Quan 5863712e7a4SEvan Quan return ret; 587bc143d8bSEvan Quan } 588bc143d8bSEvan Quan 589bc143d8bSEvan Quan int amdgpu_dpm_get_status_gfxoff(struct amdgpu_device *adev, uint32_t *value) 590bc143d8bSEvan Quan { 591ebfc2533SEvan Quan struct smu_context *smu = adev->powerplay.pp_handle; 5923712e7a4SEvan Quan int ret = 0; 593ebfc2533SEvan Quan 594bc143d8bSEvan Quan if (!is_support_sw_smu(adev)) 595bc143d8bSEvan Quan return -EOPNOTSUPP; 596bc143d8bSEvan Quan 5973712e7a4SEvan Quan mutex_lock(&adev->pm.mutex); 5983712e7a4SEvan Quan ret = smu_get_status_gfxoff(smu, value); 5993712e7a4SEvan Quan mutex_unlock(&adev->pm.mutex); 6003712e7a4SEvan Quan 6013712e7a4SEvan Quan return ret; 602bc143d8bSEvan Quan } 603bc143d8bSEvan Quan 604bc143d8bSEvan Quan uint64_t amdgpu_dpm_get_thermal_throttling_counter(struct amdgpu_device *adev) 605bc143d8bSEvan Quan { 606ebfc2533SEvan Quan struct smu_context *smu = adev->powerplay.pp_handle; 607ebfc2533SEvan Quan 6083712e7a4SEvan Quan if (!is_support_sw_smu(adev)) 6093712e7a4SEvan Quan return 0; 6103712e7a4SEvan Quan 611ebfc2533SEvan Quan return atomic64_read(&smu->throttle_int_counter); 612bc143d8bSEvan Quan } 613bc143d8bSEvan Quan 614bc143d8bSEvan Quan /* amdgpu_dpm_gfx_state_change - Handle gfx power state change set 615bc143d8bSEvan Quan * @adev: amdgpu_device pointer 616bc143d8bSEvan Quan * @state: gfx power state(1 -sGpuChangeState_D0Entry and 2 -sGpuChangeState_D3Entry) 617bc143d8bSEvan Quan * 618bc143d8bSEvan Quan */ 619bc143d8bSEvan Quan void amdgpu_dpm_gfx_state_change(struct amdgpu_device *adev, 620bc143d8bSEvan Quan enum gfx_change_state state) 621bc143d8bSEvan Quan { 622bc143d8bSEvan Quan mutex_lock(&adev->pm.mutex); 623bc143d8bSEvan Quan if (adev->powerplay.pp_funcs && 624bc143d8bSEvan Quan adev->powerplay.pp_funcs->gfx_state_change_set) 625bc143d8bSEvan Quan ((adev)->powerplay.pp_funcs->gfx_state_change_set( 626bc143d8bSEvan Quan (adev)->powerplay.pp_handle, state)); 627bc143d8bSEvan Quan mutex_unlock(&adev->pm.mutex); 628bc143d8bSEvan Quan } 629bc143d8bSEvan Quan 630bc143d8bSEvan Quan int amdgpu_dpm_get_ecc_info(struct amdgpu_device *adev, 631bc143d8bSEvan Quan void *umc_ecc) 632bc143d8bSEvan Quan { 633ebfc2533SEvan Quan struct smu_context *smu = adev->powerplay.pp_handle; 634ebfc2533SEvan Quan 635bc143d8bSEvan Quan if (!is_support_sw_smu(adev)) 636bc143d8bSEvan Quan return -EOPNOTSUPP; 637bc143d8bSEvan Quan 638ebfc2533SEvan Quan return smu_get_ecc_info(smu, umc_ecc); 639bc143d8bSEvan Quan } 64079c65f3fSEvan Quan 64179c65f3fSEvan Quan struct amd_vce_state *amdgpu_dpm_get_vce_clock_state(struct amdgpu_device *adev, 64279c65f3fSEvan Quan uint32_t idx) 64379c65f3fSEvan Quan { 64479c65f3fSEvan Quan const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 6453712e7a4SEvan Quan struct amd_vce_state *vstate = NULL; 64679c65f3fSEvan Quan 64779c65f3fSEvan Quan if (!pp_funcs->get_vce_clock_state) 64879c65f3fSEvan Quan return NULL; 64979c65f3fSEvan Quan 6503712e7a4SEvan Quan mutex_lock(&adev->pm.mutex); 6513712e7a4SEvan Quan vstate = pp_funcs->get_vce_clock_state(adev->powerplay.pp_handle, 65279c65f3fSEvan Quan idx); 6533712e7a4SEvan Quan mutex_unlock(&adev->pm.mutex); 6543712e7a4SEvan Quan 6553712e7a4SEvan Quan return vstate; 65679c65f3fSEvan Quan } 65779c65f3fSEvan Quan 65879c65f3fSEvan Quan void amdgpu_dpm_get_current_power_state(struct amdgpu_device *adev, 65979c65f3fSEvan Quan enum amd_pm_state_type *state) 66079c65f3fSEvan Quan { 66179c65f3fSEvan Quan const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 66279c65f3fSEvan Quan 6633712e7a4SEvan Quan mutex_lock(&adev->pm.mutex); 6643712e7a4SEvan Quan 66579c65f3fSEvan Quan if (!pp_funcs->get_current_power_state) { 66679c65f3fSEvan Quan *state = adev->pm.dpm.user_state; 6673712e7a4SEvan Quan goto out; 66879c65f3fSEvan Quan } 66979c65f3fSEvan Quan 67079c65f3fSEvan Quan *state = pp_funcs->get_current_power_state(adev->powerplay.pp_handle); 67179c65f3fSEvan Quan if (*state < POWER_STATE_TYPE_DEFAULT || 67279c65f3fSEvan Quan *state > POWER_STATE_TYPE_INTERNAL_3DPERF) 67379c65f3fSEvan Quan *state = adev->pm.dpm.user_state; 6743712e7a4SEvan Quan 6753712e7a4SEvan Quan out: 6763712e7a4SEvan Quan mutex_unlock(&adev->pm.mutex); 67779c65f3fSEvan Quan } 67879c65f3fSEvan Quan 67979c65f3fSEvan Quan void amdgpu_dpm_set_power_state(struct amdgpu_device *adev, 68079c65f3fSEvan Quan enum amd_pm_state_type state) 68179c65f3fSEvan Quan { 6823712e7a4SEvan Quan mutex_lock(&adev->pm.mutex); 68379c65f3fSEvan Quan adev->pm.dpm.user_state = state; 6843712e7a4SEvan Quan mutex_unlock(&adev->pm.mutex); 68579c65f3fSEvan Quan 68679c65f3fSEvan Quan if (is_support_sw_smu(adev)) 68779c65f3fSEvan Quan return; 68879c65f3fSEvan Quan 68979c65f3fSEvan Quan if (amdgpu_dpm_dispatch_task(adev, 69079c65f3fSEvan Quan AMD_PP_TASK_ENABLE_USER_STATE, 69179c65f3fSEvan Quan &state) == -EOPNOTSUPP) 69284176663SEvan Quan amdgpu_dpm_compute_clocks(adev); 69379c65f3fSEvan Quan } 69479c65f3fSEvan Quan 69575513bf5SEvan Quan enum amd_dpm_forced_level amdgpu_dpm_get_performance_level(struct amdgpu_device *adev) 69679c65f3fSEvan Quan { 69779c65f3fSEvan Quan const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 69879c65f3fSEvan Quan enum amd_dpm_forced_level level; 69979c65f3fSEvan Quan 70075513bf5SEvan Quan mutex_lock(&adev->pm.mutex); 70179c65f3fSEvan Quan if (pp_funcs->get_performance_level) 70279c65f3fSEvan Quan level = pp_funcs->get_performance_level(adev->powerplay.pp_handle); 70379c65f3fSEvan Quan else 70479c65f3fSEvan Quan level = adev->pm.dpm.forced_level; 7053712e7a4SEvan Quan mutex_unlock(&adev->pm.mutex); 70679c65f3fSEvan Quan 70779c65f3fSEvan Quan return level; 70879c65f3fSEvan Quan } 70979c65f3fSEvan Quan 71079c65f3fSEvan Quan int amdgpu_dpm_force_performance_level(struct amdgpu_device *adev, 71179c65f3fSEvan Quan enum amd_dpm_forced_level level) 71279c65f3fSEvan Quan { 71379c65f3fSEvan Quan const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 71454c73b51SAlex Deucher enum amd_dpm_forced_level current_level; 71554c73b51SAlex Deucher uint32_t profile_mode_mask = AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD | 71654c73b51SAlex Deucher AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK | 71754c73b51SAlex Deucher AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK | 71854c73b51SAlex Deucher AMD_DPM_FORCED_LEVEL_PROFILE_PEAK; 71979c65f3fSEvan Quan 7203712e7a4SEvan Quan if (!pp_funcs->force_performance_level) 7213712e7a4SEvan Quan return 0; 7223712e7a4SEvan Quan 72375513bf5SEvan Quan if (adev->pm.dpm.thermal_active) 72475513bf5SEvan Quan return -EINVAL; 7253712e7a4SEvan Quan 72675513bf5SEvan Quan current_level = amdgpu_dpm_get_performance_level(adev); 72775513bf5SEvan Quan if (current_level == level) 72875513bf5SEvan Quan return 0; 72954c73b51SAlex Deucher 73054c73b51SAlex Deucher if (adev->asic_type == CHIP_RAVEN) { 73154c73b51SAlex Deucher if (!(adev->apu_flags & AMD_APU_IS_RAVEN2)) { 73254c73b51SAlex Deucher if (current_level != AMD_DPM_FORCED_LEVEL_MANUAL && 73354c73b51SAlex Deucher level == AMD_DPM_FORCED_LEVEL_MANUAL) 73454c73b51SAlex Deucher amdgpu_gfx_off_ctrl(adev, false); 73554c73b51SAlex Deucher else if (current_level == AMD_DPM_FORCED_LEVEL_MANUAL && 73654c73b51SAlex Deucher level != AMD_DPM_FORCED_LEVEL_MANUAL) 73754c73b51SAlex Deucher amdgpu_gfx_off_ctrl(adev, true); 73854c73b51SAlex Deucher } 73954c73b51SAlex Deucher } 74054c73b51SAlex Deucher 74154c73b51SAlex Deucher if (!(current_level & profile_mode_mask) && 74275513bf5SEvan Quan (level == AMD_DPM_FORCED_LEVEL_PROFILE_EXIT)) 74375513bf5SEvan Quan return -EINVAL; 74454c73b51SAlex Deucher 74554c73b51SAlex Deucher if (!(current_level & profile_mode_mask) && 74654c73b51SAlex Deucher (level & profile_mode_mask)) { 74754c73b51SAlex Deucher /* enter UMD Pstate */ 74854c73b51SAlex Deucher amdgpu_device_ip_set_powergating_state(adev, 74954c73b51SAlex Deucher AMD_IP_BLOCK_TYPE_GFX, 75054c73b51SAlex Deucher AMD_PG_STATE_UNGATE); 75154c73b51SAlex Deucher amdgpu_device_ip_set_clockgating_state(adev, 75254c73b51SAlex Deucher AMD_IP_BLOCK_TYPE_GFX, 75354c73b51SAlex Deucher AMD_CG_STATE_UNGATE); 75454c73b51SAlex Deucher } else if ((current_level & profile_mode_mask) && 75554c73b51SAlex Deucher !(level & profile_mode_mask)) { 75654c73b51SAlex Deucher /* exit UMD Pstate */ 75754c73b51SAlex Deucher amdgpu_device_ip_set_clockgating_state(adev, 75854c73b51SAlex Deucher AMD_IP_BLOCK_TYPE_GFX, 75954c73b51SAlex Deucher AMD_CG_STATE_GATE); 76054c73b51SAlex Deucher amdgpu_device_ip_set_powergating_state(adev, 76154c73b51SAlex Deucher AMD_IP_BLOCK_TYPE_GFX, 76254c73b51SAlex Deucher AMD_PG_STATE_GATE); 76354c73b51SAlex Deucher } 76454c73b51SAlex Deucher 76575513bf5SEvan Quan mutex_lock(&adev->pm.mutex); 76679c65f3fSEvan Quan 76775513bf5SEvan Quan if (pp_funcs->force_performance_level(adev->powerplay.pp_handle, 76875513bf5SEvan Quan level)) { 76975513bf5SEvan Quan mutex_unlock(&adev->pm.mutex); 77075513bf5SEvan Quan return -EINVAL; 77175513bf5SEvan Quan } 77275513bf5SEvan Quan 77379c65f3fSEvan Quan adev->pm.dpm.forced_level = level; 77479c65f3fSEvan Quan 7753712e7a4SEvan Quan mutex_unlock(&adev->pm.mutex); 7763712e7a4SEvan Quan 77775513bf5SEvan Quan return 0; 77879c65f3fSEvan Quan } 77979c65f3fSEvan Quan 78079c65f3fSEvan Quan int amdgpu_dpm_get_pp_num_states(struct amdgpu_device *adev, 78179c65f3fSEvan Quan struct pp_states_info *states) 78279c65f3fSEvan Quan { 78379c65f3fSEvan Quan const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 7843712e7a4SEvan Quan int ret = 0; 78579c65f3fSEvan Quan 78679c65f3fSEvan Quan if (!pp_funcs->get_pp_num_states) 78779c65f3fSEvan Quan return -EOPNOTSUPP; 78879c65f3fSEvan Quan 7893712e7a4SEvan Quan mutex_lock(&adev->pm.mutex); 7903712e7a4SEvan Quan ret = pp_funcs->get_pp_num_states(adev->powerplay.pp_handle, 7913712e7a4SEvan Quan states); 7923712e7a4SEvan Quan mutex_unlock(&adev->pm.mutex); 7933712e7a4SEvan Quan 7943712e7a4SEvan Quan return ret; 79579c65f3fSEvan Quan } 79679c65f3fSEvan Quan 79779c65f3fSEvan Quan int amdgpu_dpm_dispatch_task(struct amdgpu_device *adev, 79879c65f3fSEvan Quan enum amd_pp_task task_id, 79979c65f3fSEvan Quan enum amd_pm_state_type *user_state) 80079c65f3fSEvan Quan { 80179c65f3fSEvan Quan const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 8023712e7a4SEvan Quan int ret = 0; 80379c65f3fSEvan Quan 80479c65f3fSEvan Quan if (!pp_funcs->dispatch_tasks) 80579c65f3fSEvan Quan return -EOPNOTSUPP; 80679c65f3fSEvan Quan 8073712e7a4SEvan Quan mutex_lock(&adev->pm.mutex); 8083712e7a4SEvan Quan ret = pp_funcs->dispatch_tasks(adev->powerplay.pp_handle, 8093712e7a4SEvan Quan task_id, 8103712e7a4SEvan Quan user_state); 8113712e7a4SEvan Quan mutex_unlock(&adev->pm.mutex); 8123712e7a4SEvan Quan 8133712e7a4SEvan Quan return ret; 81479c65f3fSEvan Quan } 81579c65f3fSEvan Quan 81679c65f3fSEvan Quan int amdgpu_dpm_get_pp_table(struct amdgpu_device *adev, char **table) 81779c65f3fSEvan Quan { 81879c65f3fSEvan Quan const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 8193712e7a4SEvan Quan int ret = 0; 82079c65f3fSEvan Quan 82179c65f3fSEvan Quan if (!pp_funcs->get_pp_table) 82279c65f3fSEvan Quan return 0; 82379c65f3fSEvan Quan 8243712e7a4SEvan Quan mutex_lock(&adev->pm.mutex); 8253712e7a4SEvan Quan ret = pp_funcs->get_pp_table(adev->powerplay.pp_handle, 8263712e7a4SEvan Quan table); 8273712e7a4SEvan Quan mutex_unlock(&adev->pm.mutex); 8283712e7a4SEvan Quan 8293712e7a4SEvan Quan return ret; 83079c65f3fSEvan Quan } 83179c65f3fSEvan Quan 83279c65f3fSEvan Quan int amdgpu_dpm_set_fine_grain_clk_vol(struct amdgpu_device *adev, 83379c65f3fSEvan Quan uint32_t type, 83479c65f3fSEvan Quan long *input, 83579c65f3fSEvan Quan uint32_t size) 83679c65f3fSEvan Quan { 83779c65f3fSEvan Quan const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 8383712e7a4SEvan Quan int ret = 0; 83979c65f3fSEvan Quan 84079c65f3fSEvan Quan if (!pp_funcs->set_fine_grain_clk_vol) 84179c65f3fSEvan Quan return 0; 84279c65f3fSEvan Quan 8433712e7a4SEvan Quan mutex_lock(&adev->pm.mutex); 8443712e7a4SEvan Quan ret = pp_funcs->set_fine_grain_clk_vol(adev->powerplay.pp_handle, 84579c65f3fSEvan Quan type, 84679c65f3fSEvan Quan input, 84779c65f3fSEvan Quan size); 8483712e7a4SEvan Quan mutex_unlock(&adev->pm.mutex); 8493712e7a4SEvan Quan 8503712e7a4SEvan Quan return ret; 85179c65f3fSEvan Quan } 85279c65f3fSEvan Quan 85379c65f3fSEvan Quan int amdgpu_dpm_odn_edit_dpm_table(struct amdgpu_device *adev, 85479c65f3fSEvan Quan uint32_t type, 85579c65f3fSEvan Quan long *input, 85679c65f3fSEvan Quan uint32_t size) 85779c65f3fSEvan Quan { 85879c65f3fSEvan Quan const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 8593712e7a4SEvan Quan int ret = 0; 86079c65f3fSEvan Quan 86179c65f3fSEvan Quan if (!pp_funcs->odn_edit_dpm_table) 86279c65f3fSEvan Quan return 0; 86379c65f3fSEvan Quan 8643712e7a4SEvan Quan mutex_lock(&adev->pm.mutex); 8653712e7a4SEvan Quan ret = pp_funcs->odn_edit_dpm_table(adev->powerplay.pp_handle, 86679c65f3fSEvan Quan type, 86779c65f3fSEvan Quan input, 86879c65f3fSEvan Quan size); 8693712e7a4SEvan Quan mutex_unlock(&adev->pm.mutex); 8703712e7a4SEvan Quan 8713712e7a4SEvan Quan return ret; 87279c65f3fSEvan Quan } 87379c65f3fSEvan Quan 87479c65f3fSEvan Quan int amdgpu_dpm_print_clock_levels(struct amdgpu_device *adev, 87579c65f3fSEvan Quan enum pp_clock_type type, 87679c65f3fSEvan Quan char *buf) 87779c65f3fSEvan Quan { 87879c65f3fSEvan Quan const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 8793712e7a4SEvan Quan int ret = 0; 88079c65f3fSEvan Quan 88179c65f3fSEvan Quan if (!pp_funcs->print_clock_levels) 88279c65f3fSEvan Quan return 0; 88379c65f3fSEvan Quan 8843712e7a4SEvan Quan mutex_lock(&adev->pm.mutex); 8853712e7a4SEvan Quan ret = pp_funcs->print_clock_levels(adev->powerplay.pp_handle, 88679c65f3fSEvan Quan type, 88779c65f3fSEvan Quan buf); 8883712e7a4SEvan Quan mutex_unlock(&adev->pm.mutex); 8893712e7a4SEvan Quan 8903712e7a4SEvan Quan return ret; 89179c65f3fSEvan Quan } 89279c65f3fSEvan Quan 893*5d64f9bbSDarren Powell int amdgpu_dpm_emit_clock_levels(struct amdgpu_device *adev, 894*5d64f9bbSDarren Powell enum pp_clock_type type, 895*5d64f9bbSDarren Powell char *buf, 896*5d64f9bbSDarren Powell int *offset) 897*5d64f9bbSDarren Powell { 898*5d64f9bbSDarren Powell const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 899*5d64f9bbSDarren Powell int ret = 0; 900*5d64f9bbSDarren Powell 901*5d64f9bbSDarren Powell if (!pp_funcs->emit_clock_levels) 902*5d64f9bbSDarren Powell return -ENOENT; 903*5d64f9bbSDarren Powell 904*5d64f9bbSDarren Powell mutex_lock(&adev->pm.mutex); 905*5d64f9bbSDarren Powell ret = pp_funcs->emit_clock_levels(adev->powerplay.pp_handle, 906*5d64f9bbSDarren Powell type, 907*5d64f9bbSDarren Powell buf, 908*5d64f9bbSDarren Powell offset); 909*5d64f9bbSDarren Powell mutex_unlock(&adev->pm.mutex); 910*5d64f9bbSDarren Powell 911*5d64f9bbSDarren Powell return ret; 912*5d64f9bbSDarren Powell } 913*5d64f9bbSDarren Powell 91479c65f3fSEvan Quan int amdgpu_dpm_set_ppfeature_status(struct amdgpu_device *adev, 91579c65f3fSEvan Quan uint64_t ppfeature_masks) 91679c65f3fSEvan Quan { 91779c65f3fSEvan Quan const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 9183712e7a4SEvan Quan int ret = 0; 91979c65f3fSEvan Quan 92079c65f3fSEvan Quan if (!pp_funcs->set_ppfeature_status) 92179c65f3fSEvan Quan return 0; 92279c65f3fSEvan Quan 9233712e7a4SEvan Quan mutex_lock(&adev->pm.mutex); 9243712e7a4SEvan Quan ret = pp_funcs->set_ppfeature_status(adev->powerplay.pp_handle, 92579c65f3fSEvan Quan ppfeature_masks); 9263712e7a4SEvan Quan mutex_unlock(&adev->pm.mutex); 9273712e7a4SEvan Quan 9283712e7a4SEvan Quan return ret; 92979c65f3fSEvan Quan } 93079c65f3fSEvan Quan 93179c65f3fSEvan Quan int amdgpu_dpm_get_ppfeature_status(struct amdgpu_device *adev, char *buf) 93279c65f3fSEvan Quan { 93379c65f3fSEvan Quan const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 9343712e7a4SEvan Quan int ret = 0; 93579c65f3fSEvan Quan 93679c65f3fSEvan Quan if (!pp_funcs->get_ppfeature_status) 93779c65f3fSEvan Quan return 0; 93879c65f3fSEvan Quan 9393712e7a4SEvan Quan mutex_lock(&adev->pm.mutex); 9403712e7a4SEvan Quan ret = pp_funcs->get_ppfeature_status(adev->powerplay.pp_handle, 94179c65f3fSEvan Quan buf); 9423712e7a4SEvan Quan mutex_unlock(&adev->pm.mutex); 9433712e7a4SEvan Quan 9443712e7a4SEvan Quan return ret; 94579c65f3fSEvan Quan } 94679c65f3fSEvan Quan 94779c65f3fSEvan Quan int amdgpu_dpm_force_clock_level(struct amdgpu_device *adev, 94879c65f3fSEvan Quan enum pp_clock_type type, 94979c65f3fSEvan Quan uint32_t mask) 95079c65f3fSEvan Quan { 95179c65f3fSEvan Quan const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 9523712e7a4SEvan Quan int ret = 0; 95379c65f3fSEvan Quan 95479c65f3fSEvan Quan if (!pp_funcs->force_clock_level) 95579c65f3fSEvan Quan return 0; 95679c65f3fSEvan Quan 9573712e7a4SEvan Quan mutex_lock(&adev->pm.mutex); 9583712e7a4SEvan Quan ret = pp_funcs->force_clock_level(adev->powerplay.pp_handle, 95979c65f3fSEvan Quan type, 96079c65f3fSEvan Quan mask); 9613712e7a4SEvan Quan mutex_unlock(&adev->pm.mutex); 9623712e7a4SEvan Quan 9633712e7a4SEvan Quan return ret; 96479c65f3fSEvan Quan } 96579c65f3fSEvan Quan 96679c65f3fSEvan Quan int amdgpu_dpm_get_sclk_od(struct amdgpu_device *adev) 96779c65f3fSEvan Quan { 96879c65f3fSEvan Quan const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 9693712e7a4SEvan Quan int ret = 0; 97079c65f3fSEvan Quan 97179c65f3fSEvan Quan if (!pp_funcs->get_sclk_od) 97279c65f3fSEvan Quan return 0; 97379c65f3fSEvan Quan 9743712e7a4SEvan Quan mutex_lock(&adev->pm.mutex); 9753712e7a4SEvan Quan ret = pp_funcs->get_sclk_od(adev->powerplay.pp_handle); 9763712e7a4SEvan Quan mutex_unlock(&adev->pm.mutex); 9773712e7a4SEvan Quan 9783712e7a4SEvan Quan return ret; 97979c65f3fSEvan Quan } 98079c65f3fSEvan Quan 98179c65f3fSEvan Quan int amdgpu_dpm_set_sclk_od(struct amdgpu_device *adev, uint32_t value) 98279c65f3fSEvan Quan { 98379c65f3fSEvan Quan const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 98479c65f3fSEvan Quan 98579c65f3fSEvan Quan if (is_support_sw_smu(adev)) 98679c65f3fSEvan Quan return 0; 98779c65f3fSEvan Quan 9883712e7a4SEvan Quan mutex_lock(&adev->pm.mutex); 98979c65f3fSEvan Quan if (pp_funcs->set_sclk_od) 99079c65f3fSEvan Quan pp_funcs->set_sclk_od(adev->powerplay.pp_handle, value); 9913712e7a4SEvan Quan mutex_unlock(&adev->pm.mutex); 99279c65f3fSEvan Quan 99379c65f3fSEvan Quan if (amdgpu_dpm_dispatch_task(adev, 99479c65f3fSEvan Quan AMD_PP_TASK_READJUST_POWER_STATE, 99579c65f3fSEvan Quan NULL) == -EOPNOTSUPP) { 99679c65f3fSEvan Quan adev->pm.dpm.current_ps = adev->pm.dpm.boot_ps; 99784176663SEvan Quan amdgpu_dpm_compute_clocks(adev); 99879c65f3fSEvan Quan } 99979c65f3fSEvan Quan 100079c65f3fSEvan Quan return 0; 100179c65f3fSEvan Quan } 100279c65f3fSEvan Quan 100379c65f3fSEvan Quan int amdgpu_dpm_get_mclk_od(struct amdgpu_device *adev) 100479c65f3fSEvan Quan { 100579c65f3fSEvan Quan const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 10063712e7a4SEvan Quan int ret = 0; 100779c65f3fSEvan Quan 100879c65f3fSEvan Quan if (!pp_funcs->get_mclk_od) 100979c65f3fSEvan Quan return 0; 101079c65f3fSEvan Quan 10113712e7a4SEvan Quan mutex_lock(&adev->pm.mutex); 10123712e7a4SEvan Quan ret = pp_funcs->get_mclk_od(adev->powerplay.pp_handle); 10133712e7a4SEvan Quan mutex_unlock(&adev->pm.mutex); 10143712e7a4SEvan Quan 10153712e7a4SEvan Quan return ret; 101679c65f3fSEvan Quan } 101779c65f3fSEvan Quan 101879c65f3fSEvan Quan int amdgpu_dpm_set_mclk_od(struct amdgpu_device *adev, uint32_t value) 101979c65f3fSEvan Quan { 102079c65f3fSEvan Quan const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 102179c65f3fSEvan Quan 102279c65f3fSEvan Quan if (is_support_sw_smu(adev)) 102379c65f3fSEvan Quan return 0; 102479c65f3fSEvan Quan 10253712e7a4SEvan Quan mutex_lock(&adev->pm.mutex); 102679c65f3fSEvan Quan if (pp_funcs->set_mclk_od) 102779c65f3fSEvan Quan pp_funcs->set_mclk_od(adev->powerplay.pp_handle, value); 10283712e7a4SEvan Quan mutex_unlock(&adev->pm.mutex); 102979c65f3fSEvan Quan 103079c65f3fSEvan Quan if (amdgpu_dpm_dispatch_task(adev, 103179c65f3fSEvan Quan AMD_PP_TASK_READJUST_POWER_STATE, 103279c65f3fSEvan Quan NULL) == -EOPNOTSUPP) { 103379c65f3fSEvan Quan adev->pm.dpm.current_ps = adev->pm.dpm.boot_ps; 103484176663SEvan Quan amdgpu_dpm_compute_clocks(adev); 103579c65f3fSEvan Quan } 103679c65f3fSEvan Quan 103779c65f3fSEvan Quan return 0; 103879c65f3fSEvan Quan } 103979c65f3fSEvan Quan 104079c65f3fSEvan Quan int amdgpu_dpm_get_power_profile_mode(struct amdgpu_device *adev, 104179c65f3fSEvan Quan char *buf) 104279c65f3fSEvan Quan { 104379c65f3fSEvan Quan const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 10443712e7a4SEvan Quan int ret = 0; 104579c65f3fSEvan Quan 104679c65f3fSEvan Quan if (!pp_funcs->get_power_profile_mode) 104779c65f3fSEvan Quan return -EOPNOTSUPP; 104879c65f3fSEvan Quan 10493712e7a4SEvan Quan mutex_lock(&adev->pm.mutex); 10503712e7a4SEvan Quan ret = pp_funcs->get_power_profile_mode(adev->powerplay.pp_handle, 105179c65f3fSEvan Quan buf); 10523712e7a4SEvan Quan mutex_unlock(&adev->pm.mutex); 10533712e7a4SEvan Quan 10543712e7a4SEvan Quan return ret; 105579c65f3fSEvan Quan } 105679c65f3fSEvan Quan 105779c65f3fSEvan Quan int amdgpu_dpm_set_power_profile_mode(struct amdgpu_device *adev, 105879c65f3fSEvan Quan long *input, uint32_t size) 105979c65f3fSEvan Quan { 106079c65f3fSEvan Quan const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 10613712e7a4SEvan Quan int ret = 0; 106279c65f3fSEvan Quan 106379c65f3fSEvan Quan if (!pp_funcs->set_power_profile_mode) 106479c65f3fSEvan Quan return 0; 106579c65f3fSEvan Quan 10663712e7a4SEvan Quan mutex_lock(&adev->pm.mutex); 10673712e7a4SEvan Quan ret = pp_funcs->set_power_profile_mode(adev->powerplay.pp_handle, 106879c65f3fSEvan Quan input, 106979c65f3fSEvan Quan size); 10703712e7a4SEvan Quan mutex_unlock(&adev->pm.mutex); 10713712e7a4SEvan Quan 10723712e7a4SEvan Quan return ret; 107379c65f3fSEvan Quan } 107479c65f3fSEvan Quan 107579c65f3fSEvan Quan int amdgpu_dpm_get_gpu_metrics(struct amdgpu_device *adev, void **table) 107679c65f3fSEvan Quan { 107779c65f3fSEvan Quan const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 10783712e7a4SEvan Quan int ret = 0; 107979c65f3fSEvan Quan 108079c65f3fSEvan Quan if (!pp_funcs->get_gpu_metrics) 108179c65f3fSEvan Quan return 0; 108279c65f3fSEvan Quan 10833712e7a4SEvan Quan mutex_lock(&adev->pm.mutex); 10843712e7a4SEvan Quan ret = pp_funcs->get_gpu_metrics(adev->powerplay.pp_handle, 10853712e7a4SEvan Quan table); 10863712e7a4SEvan Quan mutex_unlock(&adev->pm.mutex); 10873712e7a4SEvan Quan 10883712e7a4SEvan Quan return ret; 108979c65f3fSEvan Quan } 109079c65f3fSEvan Quan 109179c65f3fSEvan Quan int amdgpu_dpm_get_fan_control_mode(struct amdgpu_device *adev, 109279c65f3fSEvan Quan uint32_t *fan_mode) 109379c65f3fSEvan Quan { 109479c65f3fSEvan Quan const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 1095685fae24SEvan Quan int ret = 0; 109679c65f3fSEvan Quan 109779c65f3fSEvan Quan if (!pp_funcs->get_fan_control_mode) 109879c65f3fSEvan Quan return -EOPNOTSUPP; 109979c65f3fSEvan Quan 11003712e7a4SEvan Quan mutex_lock(&adev->pm.mutex); 1101685fae24SEvan Quan ret = pp_funcs->get_fan_control_mode(adev->powerplay.pp_handle, 1102685fae24SEvan Quan fan_mode); 11033712e7a4SEvan Quan mutex_unlock(&adev->pm.mutex); 110479c65f3fSEvan Quan 1105685fae24SEvan Quan return ret; 110679c65f3fSEvan Quan } 110779c65f3fSEvan Quan 110879c65f3fSEvan Quan int amdgpu_dpm_set_fan_speed_pwm(struct amdgpu_device *adev, 110979c65f3fSEvan Quan uint32_t speed) 111079c65f3fSEvan Quan { 111179c65f3fSEvan Quan const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 11123712e7a4SEvan Quan int ret = 0; 111379c65f3fSEvan Quan 111479c65f3fSEvan Quan if (!pp_funcs->set_fan_speed_pwm) 1115685fae24SEvan Quan return -EOPNOTSUPP; 111679c65f3fSEvan Quan 11173712e7a4SEvan Quan mutex_lock(&adev->pm.mutex); 11183712e7a4SEvan Quan ret = pp_funcs->set_fan_speed_pwm(adev->powerplay.pp_handle, 11193712e7a4SEvan Quan speed); 11203712e7a4SEvan Quan mutex_unlock(&adev->pm.mutex); 11213712e7a4SEvan Quan 11223712e7a4SEvan Quan return ret; 112379c65f3fSEvan Quan } 112479c65f3fSEvan Quan 112579c65f3fSEvan Quan int amdgpu_dpm_get_fan_speed_pwm(struct amdgpu_device *adev, 112679c65f3fSEvan Quan uint32_t *speed) 112779c65f3fSEvan Quan { 112879c65f3fSEvan Quan const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 11293712e7a4SEvan Quan int ret = 0; 113079c65f3fSEvan Quan 113179c65f3fSEvan Quan if (!pp_funcs->get_fan_speed_pwm) 1132685fae24SEvan Quan return -EOPNOTSUPP; 113379c65f3fSEvan Quan 11343712e7a4SEvan Quan mutex_lock(&adev->pm.mutex); 11353712e7a4SEvan Quan ret = pp_funcs->get_fan_speed_pwm(adev->powerplay.pp_handle, 11363712e7a4SEvan Quan speed); 11373712e7a4SEvan Quan mutex_unlock(&adev->pm.mutex); 11383712e7a4SEvan Quan 11393712e7a4SEvan Quan return ret; 114079c65f3fSEvan Quan } 114179c65f3fSEvan Quan 114279c65f3fSEvan Quan int amdgpu_dpm_get_fan_speed_rpm(struct amdgpu_device *adev, 114379c65f3fSEvan Quan uint32_t *speed) 114479c65f3fSEvan Quan { 114579c65f3fSEvan Quan const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 11463712e7a4SEvan Quan int ret = 0; 114779c65f3fSEvan Quan 114879c65f3fSEvan Quan if (!pp_funcs->get_fan_speed_rpm) 1149685fae24SEvan Quan return -EOPNOTSUPP; 115079c65f3fSEvan Quan 11513712e7a4SEvan Quan mutex_lock(&adev->pm.mutex); 11523712e7a4SEvan Quan ret = pp_funcs->get_fan_speed_rpm(adev->powerplay.pp_handle, 11533712e7a4SEvan Quan speed); 11543712e7a4SEvan Quan mutex_unlock(&adev->pm.mutex); 11553712e7a4SEvan Quan 11563712e7a4SEvan Quan return ret; 115779c65f3fSEvan Quan } 115879c65f3fSEvan Quan 115979c65f3fSEvan Quan int amdgpu_dpm_set_fan_speed_rpm(struct amdgpu_device *adev, 116079c65f3fSEvan Quan uint32_t speed) 116179c65f3fSEvan Quan { 116279c65f3fSEvan Quan const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 11633712e7a4SEvan Quan int ret = 0; 116479c65f3fSEvan Quan 116579c65f3fSEvan Quan if (!pp_funcs->set_fan_speed_rpm) 1166685fae24SEvan Quan return -EOPNOTSUPP; 116779c65f3fSEvan Quan 11683712e7a4SEvan Quan mutex_lock(&adev->pm.mutex); 11693712e7a4SEvan Quan ret = pp_funcs->set_fan_speed_rpm(adev->powerplay.pp_handle, 11703712e7a4SEvan Quan speed); 11713712e7a4SEvan Quan mutex_unlock(&adev->pm.mutex); 11723712e7a4SEvan Quan 11733712e7a4SEvan Quan return ret; 117479c65f3fSEvan Quan } 117579c65f3fSEvan Quan 117679c65f3fSEvan Quan int amdgpu_dpm_set_fan_control_mode(struct amdgpu_device *adev, 117779c65f3fSEvan Quan uint32_t mode) 117879c65f3fSEvan Quan { 117979c65f3fSEvan Quan const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 1180685fae24SEvan Quan int ret = 0; 118179c65f3fSEvan Quan 118279c65f3fSEvan Quan if (!pp_funcs->set_fan_control_mode) 118379c65f3fSEvan Quan return -EOPNOTSUPP; 118479c65f3fSEvan Quan 11853712e7a4SEvan Quan mutex_lock(&adev->pm.mutex); 1186685fae24SEvan Quan ret = pp_funcs->set_fan_control_mode(adev->powerplay.pp_handle, 11873712e7a4SEvan Quan mode); 11883712e7a4SEvan Quan mutex_unlock(&adev->pm.mutex); 118979c65f3fSEvan Quan 1190685fae24SEvan Quan return ret; 119179c65f3fSEvan Quan } 119279c65f3fSEvan Quan 119379c65f3fSEvan Quan int amdgpu_dpm_get_power_limit(struct amdgpu_device *adev, 119479c65f3fSEvan Quan uint32_t *limit, 119579c65f3fSEvan Quan enum pp_power_limit_level pp_limit_level, 119679c65f3fSEvan Quan enum pp_power_type power_type) 119779c65f3fSEvan Quan { 119879c65f3fSEvan Quan const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 11993712e7a4SEvan Quan int ret = 0; 120079c65f3fSEvan Quan 120179c65f3fSEvan Quan if (!pp_funcs->get_power_limit) 120279c65f3fSEvan Quan return -ENODATA; 120379c65f3fSEvan Quan 12043712e7a4SEvan Quan mutex_lock(&adev->pm.mutex); 12053712e7a4SEvan Quan ret = pp_funcs->get_power_limit(adev->powerplay.pp_handle, 120679c65f3fSEvan Quan limit, 120779c65f3fSEvan Quan pp_limit_level, 120879c65f3fSEvan Quan power_type); 12093712e7a4SEvan Quan mutex_unlock(&adev->pm.mutex); 12103712e7a4SEvan Quan 12113712e7a4SEvan Quan return ret; 121279c65f3fSEvan Quan } 121379c65f3fSEvan Quan 121479c65f3fSEvan Quan int amdgpu_dpm_set_power_limit(struct amdgpu_device *adev, 121579c65f3fSEvan Quan uint32_t limit) 121679c65f3fSEvan Quan { 121779c65f3fSEvan Quan const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 12183712e7a4SEvan Quan int ret = 0; 121979c65f3fSEvan Quan 122079c65f3fSEvan Quan if (!pp_funcs->set_power_limit) 122179c65f3fSEvan Quan return -EINVAL; 122279c65f3fSEvan Quan 12233712e7a4SEvan Quan mutex_lock(&adev->pm.mutex); 12243712e7a4SEvan Quan ret = pp_funcs->set_power_limit(adev->powerplay.pp_handle, 12253712e7a4SEvan Quan limit); 12263712e7a4SEvan Quan mutex_unlock(&adev->pm.mutex); 12273712e7a4SEvan Quan 12283712e7a4SEvan Quan return ret; 122979c65f3fSEvan Quan } 123079c65f3fSEvan Quan 123179c65f3fSEvan Quan int amdgpu_dpm_is_cclk_dpm_supported(struct amdgpu_device *adev) 123279c65f3fSEvan Quan { 12333712e7a4SEvan Quan bool cclk_dpm_supported = false; 12343712e7a4SEvan Quan 123579c65f3fSEvan Quan if (!is_support_sw_smu(adev)) 123679c65f3fSEvan Quan return false; 123779c65f3fSEvan Quan 12383712e7a4SEvan Quan mutex_lock(&adev->pm.mutex); 12393712e7a4SEvan Quan cclk_dpm_supported = is_support_cclk_dpm(adev); 12403712e7a4SEvan Quan mutex_unlock(&adev->pm.mutex); 12413712e7a4SEvan Quan 12423712e7a4SEvan Quan return (int)cclk_dpm_supported; 124379c65f3fSEvan Quan } 124479c65f3fSEvan Quan 124579c65f3fSEvan Quan int amdgpu_dpm_debugfs_print_current_performance_level(struct amdgpu_device *adev, 124679c65f3fSEvan Quan struct seq_file *m) 124779c65f3fSEvan Quan { 124879c65f3fSEvan Quan const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 124979c65f3fSEvan Quan 125079c65f3fSEvan Quan if (!pp_funcs->debugfs_print_current_performance_level) 125179c65f3fSEvan Quan return -EOPNOTSUPP; 125279c65f3fSEvan Quan 12533712e7a4SEvan Quan mutex_lock(&adev->pm.mutex); 125479c65f3fSEvan Quan pp_funcs->debugfs_print_current_performance_level(adev->powerplay.pp_handle, 125579c65f3fSEvan Quan m); 12563712e7a4SEvan Quan mutex_unlock(&adev->pm.mutex); 125779c65f3fSEvan Quan 125879c65f3fSEvan Quan return 0; 125979c65f3fSEvan Quan } 126079c65f3fSEvan Quan 126179c65f3fSEvan Quan int amdgpu_dpm_get_smu_prv_buf_details(struct amdgpu_device *adev, 126279c65f3fSEvan Quan void **addr, 126379c65f3fSEvan Quan size_t *size) 126479c65f3fSEvan Quan { 126579c65f3fSEvan Quan const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 12663712e7a4SEvan Quan int ret = 0; 126779c65f3fSEvan Quan 126879c65f3fSEvan Quan if (!pp_funcs->get_smu_prv_buf_details) 126979c65f3fSEvan Quan return -ENOSYS; 127079c65f3fSEvan Quan 12713712e7a4SEvan Quan mutex_lock(&adev->pm.mutex); 12723712e7a4SEvan Quan ret = pp_funcs->get_smu_prv_buf_details(adev->powerplay.pp_handle, 127379c65f3fSEvan Quan addr, 127479c65f3fSEvan Quan size); 12753712e7a4SEvan Quan mutex_unlock(&adev->pm.mutex); 12763712e7a4SEvan Quan 12773712e7a4SEvan Quan return ret; 127879c65f3fSEvan Quan } 127979c65f3fSEvan Quan 128079c65f3fSEvan Quan int amdgpu_dpm_is_overdrive_supported(struct amdgpu_device *adev) 128179c65f3fSEvan Quan { 128279c65f3fSEvan Quan struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle; 1283ebfc2533SEvan Quan struct smu_context *smu = adev->powerplay.pp_handle; 128479c65f3fSEvan Quan 1285ebfc2533SEvan Quan if ((is_support_sw_smu(adev) && smu->od_enabled) || 1286ebfc2533SEvan Quan (is_support_sw_smu(adev) && smu->is_apu) || 128779c65f3fSEvan Quan (!is_support_sw_smu(adev) && hwmgr->od_enabled)) 128879c65f3fSEvan Quan return true; 128979c65f3fSEvan Quan 129079c65f3fSEvan Quan return false; 129179c65f3fSEvan Quan } 129279c65f3fSEvan Quan 129379c65f3fSEvan Quan int amdgpu_dpm_set_pp_table(struct amdgpu_device *adev, 129479c65f3fSEvan Quan const char *buf, 129579c65f3fSEvan Quan size_t size) 129679c65f3fSEvan Quan { 129779c65f3fSEvan Quan const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 12983712e7a4SEvan Quan int ret = 0; 129979c65f3fSEvan Quan 130079c65f3fSEvan Quan if (!pp_funcs->set_pp_table) 130179c65f3fSEvan Quan return -EOPNOTSUPP; 130279c65f3fSEvan Quan 13033712e7a4SEvan Quan mutex_lock(&adev->pm.mutex); 13043712e7a4SEvan Quan ret = pp_funcs->set_pp_table(adev->powerplay.pp_handle, 130579c65f3fSEvan Quan buf, 130679c65f3fSEvan Quan size); 13073712e7a4SEvan Quan mutex_unlock(&adev->pm.mutex); 13083712e7a4SEvan Quan 13093712e7a4SEvan Quan return ret; 131079c65f3fSEvan Quan } 131179c65f3fSEvan Quan 131279c65f3fSEvan Quan int amdgpu_dpm_get_num_cpu_cores(struct amdgpu_device *adev) 131379c65f3fSEvan Quan { 1314ebfc2533SEvan Quan struct smu_context *smu = adev->powerplay.pp_handle; 1315ebfc2533SEvan Quan 13163712e7a4SEvan Quan if (!is_support_sw_smu(adev)) 13173712e7a4SEvan Quan return INT_MAX; 13183712e7a4SEvan Quan 1319ebfc2533SEvan Quan return smu->cpu_core_num; 132079c65f3fSEvan Quan } 132179c65f3fSEvan Quan 132279c65f3fSEvan Quan void amdgpu_dpm_stb_debug_fs_init(struct amdgpu_device *adev) 132379c65f3fSEvan Quan { 132479c65f3fSEvan Quan if (!is_support_sw_smu(adev)) 132579c65f3fSEvan Quan return; 132679c65f3fSEvan Quan 132779c65f3fSEvan Quan amdgpu_smu_stb_debug_fs_init(adev); 132879c65f3fSEvan Quan } 132913f5dbd6SEvan Quan 133013f5dbd6SEvan Quan int amdgpu_dpm_display_configuration_change(struct amdgpu_device *adev, 133113f5dbd6SEvan Quan const struct amd_pp_display_configuration *input) 133213f5dbd6SEvan Quan { 133313f5dbd6SEvan Quan const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 13343712e7a4SEvan Quan int ret = 0; 133513f5dbd6SEvan Quan 133613f5dbd6SEvan Quan if (!pp_funcs->display_configuration_change) 133713f5dbd6SEvan Quan return 0; 133813f5dbd6SEvan Quan 13393712e7a4SEvan Quan mutex_lock(&adev->pm.mutex); 13403712e7a4SEvan Quan ret = pp_funcs->display_configuration_change(adev->powerplay.pp_handle, 134113f5dbd6SEvan Quan input); 13423712e7a4SEvan Quan mutex_unlock(&adev->pm.mutex); 13433712e7a4SEvan Quan 13443712e7a4SEvan Quan return ret; 134513f5dbd6SEvan Quan } 134613f5dbd6SEvan Quan 134713f5dbd6SEvan Quan int amdgpu_dpm_get_clock_by_type(struct amdgpu_device *adev, 134813f5dbd6SEvan Quan enum amd_pp_clock_type type, 134913f5dbd6SEvan Quan struct amd_pp_clocks *clocks) 135013f5dbd6SEvan Quan { 135113f5dbd6SEvan Quan const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 13523712e7a4SEvan Quan int ret = 0; 135313f5dbd6SEvan Quan 135413f5dbd6SEvan Quan if (!pp_funcs->get_clock_by_type) 135513f5dbd6SEvan Quan return 0; 135613f5dbd6SEvan Quan 13573712e7a4SEvan Quan mutex_lock(&adev->pm.mutex); 13583712e7a4SEvan Quan ret = pp_funcs->get_clock_by_type(adev->powerplay.pp_handle, 135913f5dbd6SEvan Quan type, 136013f5dbd6SEvan Quan clocks); 13613712e7a4SEvan Quan mutex_unlock(&adev->pm.mutex); 13623712e7a4SEvan Quan 13633712e7a4SEvan Quan return ret; 136413f5dbd6SEvan Quan } 136513f5dbd6SEvan Quan 136613f5dbd6SEvan Quan int amdgpu_dpm_get_display_mode_validation_clks(struct amdgpu_device *adev, 136713f5dbd6SEvan Quan struct amd_pp_simple_clock_info *clocks) 136813f5dbd6SEvan Quan { 136913f5dbd6SEvan Quan const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 13703712e7a4SEvan Quan int ret = 0; 137113f5dbd6SEvan Quan 137213f5dbd6SEvan Quan if (!pp_funcs->get_display_mode_validation_clocks) 137313f5dbd6SEvan Quan return 0; 137413f5dbd6SEvan Quan 13753712e7a4SEvan Quan mutex_lock(&adev->pm.mutex); 13763712e7a4SEvan Quan ret = pp_funcs->get_display_mode_validation_clocks(adev->powerplay.pp_handle, 137713f5dbd6SEvan Quan clocks); 13783712e7a4SEvan Quan mutex_unlock(&adev->pm.mutex); 13793712e7a4SEvan Quan 13803712e7a4SEvan Quan return ret; 138113f5dbd6SEvan Quan } 138213f5dbd6SEvan Quan 138313f5dbd6SEvan Quan int amdgpu_dpm_get_clock_by_type_with_latency(struct amdgpu_device *adev, 138413f5dbd6SEvan Quan enum amd_pp_clock_type type, 138513f5dbd6SEvan Quan struct pp_clock_levels_with_latency *clocks) 138613f5dbd6SEvan Quan { 138713f5dbd6SEvan Quan const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 13883712e7a4SEvan Quan int ret = 0; 138913f5dbd6SEvan Quan 139013f5dbd6SEvan Quan if (!pp_funcs->get_clock_by_type_with_latency) 139113f5dbd6SEvan Quan return 0; 139213f5dbd6SEvan Quan 13933712e7a4SEvan Quan mutex_lock(&adev->pm.mutex); 13943712e7a4SEvan Quan ret = pp_funcs->get_clock_by_type_with_latency(adev->powerplay.pp_handle, 139513f5dbd6SEvan Quan type, 139613f5dbd6SEvan Quan clocks); 13973712e7a4SEvan Quan mutex_unlock(&adev->pm.mutex); 13983712e7a4SEvan Quan 13993712e7a4SEvan Quan return ret; 140013f5dbd6SEvan Quan } 140113f5dbd6SEvan Quan 140213f5dbd6SEvan Quan int amdgpu_dpm_get_clock_by_type_with_voltage(struct amdgpu_device *adev, 140313f5dbd6SEvan Quan enum amd_pp_clock_type type, 140413f5dbd6SEvan Quan struct pp_clock_levels_with_voltage *clocks) 140513f5dbd6SEvan Quan { 140613f5dbd6SEvan Quan const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 14073712e7a4SEvan Quan int ret = 0; 140813f5dbd6SEvan Quan 140913f5dbd6SEvan Quan if (!pp_funcs->get_clock_by_type_with_voltage) 141013f5dbd6SEvan Quan return 0; 141113f5dbd6SEvan Quan 14123712e7a4SEvan Quan mutex_lock(&adev->pm.mutex); 14133712e7a4SEvan Quan ret = pp_funcs->get_clock_by_type_with_voltage(adev->powerplay.pp_handle, 141413f5dbd6SEvan Quan type, 141513f5dbd6SEvan Quan clocks); 14163712e7a4SEvan Quan mutex_unlock(&adev->pm.mutex); 14173712e7a4SEvan Quan 14183712e7a4SEvan Quan return ret; 141913f5dbd6SEvan Quan } 142013f5dbd6SEvan Quan 142113f5dbd6SEvan Quan int amdgpu_dpm_set_watermarks_for_clocks_ranges(struct amdgpu_device *adev, 142213f5dbd6SEvan Quan void *clock_ranges) 142313f5dbd6SEvan Quan { 142413f5dbd6SEvan Quan const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 14253712e7a4SEvan Quan int ret = 0; 142613f5dbd6SEvan Quan 142713f5dbd6SEvan Quan if (!pp_funcs->set_watermarks_for_clocks_ranges) 142813f5dbd6SEvan Quan return -EOPNOTSUPP; 142913f5dbd6SEvan Quan 14303712e7a4SEvan Quan mutex_lock(&adev->pm.mutex); 14313712e7a4SEvan Quan ret = pp_funcs->set_watermarks_for_clocks_ranges(adev->powerplay.pp_handle, 143213f5dbd6SEvan Quan clock_ranges); 14333712e7a4SEvan Quan mutex_unlock(&adev->pm.mutex); 14343712e7a4SEvan Quan 14353712e7a4SEvan Quan return ret; 143613f5dbd6SEvan Quan } 143713f5dbd6SEvan Quan 143813f5dbd6SEvan Quan int amdgpu_dpm_display_clock_voltage_request(struct amdgpu_device *adev, 143913f5dbd6SEvan Quan struct pp_display_clock_request *clock) 144013f5dbd6SEvan Quan { 144113f5dbd6SEvan Quan const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 14423712e7a4SEvan Quan int ret = 0; 144313f5dbd6SEvan Quan 144413f5dbd6SEvan Quan if (!pp_funcs->display_clock_voltage_request) 144513f5dbd6SEvan Quan return -EOPNOTSUPP; 144613f5dbd6SEvan Quan 14473712e7a4SEvan Quan mutex_lock(&adev->pm.mutex); 14483712e7a4SEvan Quan ret = pp_funcs->display_clock_voltage_request(adev->powerplay.pp_handle, 144913f5dbd6SEvan Quan clock); 14503712e7a4SEvan Quan mutex_unlock(&adev->pm.mutex); 14513712e7a4SEvan Quan 14523712e7a4SEvan Quan return ret; 145313f5dbd6SEvan Quan } 145413f5dbd6SEvan Quan 145513f5dbd6SEvan Quan int amdgpu_dpm_get_current_clocks(struct amdgpu_device *adev, 145613f5dbd6SEvan Quan struct amd_pp_clock_info *clocks) 145713f5dbd6SEvan Quan { 145813f5dbd6SEvan Quan const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 14593712e7a4SEvan Quan int ret = 0; 146013f5dbd6SEvan Quan 146113f5dbd6SEvan Quan if (!pp_funcs->get_current_clocks) 146213f5dbd6SEvan Quan return -EOPNOTSUPP; 146313f5dbd6SEvan Quan 14643712e7a4SEvan Quan mutex_lock(&adev->pm.mutex); 14653712e7a4SEvan Quan ret = pp_funcs->get_current_clocks(adev->powerplay.pp_handle, 146613f5dbd6SEvan Quan clocks); 14673712e7a4SEvan Quan mutex_unlock(&adev->pm.mutex); 14683712e7a4SEvan Quan 14693712e7a4SEvan Quan return ret; 147013f5dbd6SEvan Quan } 147113f5dbd6SEvan Quan 147213f5dbd6SEvan Quan void amdgpu_dpm_notify_smu_enable_pwe(struct amdgpu_device *adev) 147313f5dbd6SEvan Quan { 147413f5dbd6SEvan Quan const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 147513f5dbd6SEvan Quan 147613f5dbd6SEvan Quan if (!pp_funcs->notify_smu_enable_pwe) 147713f5dbd6SEvan Quan return; 147813f5dbd6SEvan Quan 14793712e7a4SEvan Quan mutex_lock(&adev->pm.mutex); 148013f5dbd6SEvan Quan pp_funcs->notify_smu_enable_pwe(adev->powerplay.pp_handle); 14813712e7a4SEvan Quan mutex_unlock(&adev->pm.mutex); 148213f5dbd6SEvan Quan } 148313f5dbd6SEvan Quan 148413f5dbd6SEvan Quan int amdgpu_dpm_set_active_display_count(struct amdgpu_device *adev, 148513f5dbd6SEvan Quan uint32_t count) 148613f5dbd6SEvan Quan { 148713f5dbd6SEvan Quan const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 14883712e7a4SEvan Quan int ret = 0; 148913f5dbd6SEvan Quan 149013f5dbd6SEvan Quan if (!pp_funcs->set_active_display_count) 149113f5dbd6SEvan Quan return -EOPNOTSUPP; 149213f5dbd6SEvan Quan 14933712e7a4SEvan Quan mutex_lock(&adev->pm.mutex); 14943712e7a4SEvan Quan ret = pp_funcs->set_active_display_count(adev->powerplay.pp_handle, 149513f5dbd6SEvan Quan count); 14963712e7a4SEvan Quan mutex_unlock(&adev->pm.mutex); 14973712e7a4SEvan Quan 14983712e7a4SEvan Quan return ret; 149913f5dbd6SEvan Quan } 150013f5dbd6SEvan Quan 150113f5dbd6SEvan Quan int amdgpu_dpm_set_min_deep_sleep_dcefclk(struct amdgpu_device *adev, 150213f5dbd6SEvan Quan uint32_t clock) 150313f5dbd6SEvan Quan { 150413f5dbd6SEvan Quan const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 15053712e7a4SEvan Quan int ret = 0; 150613f5dbd6SEvan Quan 150713f5dbd6SEvan Quan if (!pp_funcs->set_min_deep_sleep_dcefclk) 150813f5dbd6SEvan Quan return -EOPNOTSUPP; 150913f5dbd6SEvan Quan 15103712e7a4SEvan Quan mutex_lock(&adev->pm.mutex); 15113712e7a4SEvan Quan ret = pp_funcs->set_min_deep_sleep_dcefclk(adev->powerplay.pp_handle, 151213f5dbd6SEvan Quan clock); 15133712e7a4SEvan Quan mutex_unlock(&adev->pm.mutex); 15143712e7a4SEvan Quan 15153712e7a4SEvan Quan return ret; 151613f5dbd6SEvan Quan } 151713f5dbd6SEvan Quan 151813f5dbd6SEvan Quan void amdgpu_dpm_set_hard_min_dcefclk_by_freq(struct amdgpu_device *adev, 151913f5dbd6SEvan Quan uint32_t clock) 152013f5dbd6SEvan Quan { 152113f5dbd6SEvan Quan const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 152213f5dbd6SEvan Quan 152313f5dbd6SEvan Quan if (!pp_funcs->set_hard_min_dcefclk_by_freq) 152413f5dbd6SEvan Quan return; 152513f5dbd6SEvan Quan 15263712e7a4SEvan Quan mutex_lock(&adev->pm.mutex); 152713f5dbd6SEvan Quan pp_funcs->set_hard_min_dcefclk_by_freq(adev->powerplay.pp_handle, 152813f5dbd6SEvan Quan clock); 15293712e7a4SEvan Quan mutex_unlock(&adev->pm.mutex); 153013f5dbd6SEvan Quan } 153113f5dbd6SEvan Quan 153213f5dbd6SEvan Quan void amdgpu_dpm_set_hard_min_fclk_by_freq(struct amdgpu_device *adev, 153313f5dbd6SEvan Quan uint32_t clock) 153413f5dbd6SEvan Quan { 153513f5dbd6SEvan Quan const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 153613f5dbd6SEvan Quan 153713f5dbd6SEvan Quan if (!pp_funcs->set_hard_min_fclk_by_freq) 153813f5dbd6SEvan Quan return; 153913f5dbd6SEvan Quan 15403712e7a4SEvan Quan mutex_lock(&adev->pm.mutex); 154113f5dbd6SEvan Quan pp_funcs->set_hard_min_fclk_by_freq(adev->powerplay.pp_handle, 154213f5dbd6SEvan Quan clock); 15433712e7a4SEvan Quan mutex_unlock(&adev->pm.mutex); 154413f5dbd6SEvan Quan } 154513f5dbd6SEvan Quan 154613f5dbd6SEvan Quan int amdgpu_dpm_display_disable_memory_clock_switch(struct amdgpu_device *adev, 154713f5dbd6SEvan Quan bool disable_memory_clock_switch) 154813f5dbd6SEvan Quan { 154913f5dbd6SEvan Quan const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 15503712e7a4SEvan Quan int ret = 0; 155113f5dbd6SEvan Quan 155213f5dbd6SEvan Quan if (!pp_funcs->display_disable_memory_clock_switch) 155313f5dbd6SEvan Quan return 0; 155413f5dbd6SEvan Quan 15553712e7a4SEvan Quan mutex_lock(&adev->pm.mutex); 15563712e7a4SEvan Quan ret = pp_funcs->display_disable_memory_clock_switch(adev->powerplay.pp_handle, 155713f5dbd6SEvan Quan disable_memory_clock_switch); 15583712e7a4SEvan Quan mutex_unlock(&adev->pm.mutex); 15593712e7a4SEvan Quan 15603712e7a4SEvan Quan return ret; 156113f5dbd6SEvan Quan } 156213f5dbd6SEvan Quan 156313f5dbd6SEvan Quan int amdgpu_dpm_get_max_sustainable_clocks_by_dc(struct amdgpu_device *adev, 156413f5dbd6SEvan Quan struct pp_smu_nv_clock_table *max_clocks) 156513f5dbd6SEvan Quan { 156613f5dbd6SEvan Quan const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 15673712e7a4SEvan Quan int ret = 0; 156813f5dbd6SEvan Quan 156913f5dbd6SEvan Quan if (!pp_funcs->get_max_sustainable_clocks_by_dc) 157013f5dbd6SEvan Quan return -EOPNOTSUPP; 157113f5dbd6SEvan Quan 15723712e7a4SEvan Quan mutex_lock(&adev->pm.mutex); 15733712e7a4SEvan Quan ret = pp_funcs->get_max_sustainable_clocks_by_dc(adev->powerplay.pp_handle, 157413f5dbd6SEvan Quan max_clocks); 15753712e7a4SEvan Quan mutex_unlock(&adev->pm.mutex); 15763712e7a4SEvan Quan 15773712e7a4SEvan Quan return ret; 157813f5dbd6SEvan Quan } 157913f5dbd6SEvan Quan 158013f5dbd6SEvan Quan enum pp_smu_status amdgpu_dpm_get_uclk_dpm_states(struct amdgpu_device *adev, 158113f5dbd6SEvan Quan unsigned int *clock_values_in_khz, 158213f5dbd6SEvan Quan unsigned int *num_states) 158313f5dbd6SEvan Quan { 158413f5dbd6SEvan Quan const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 15853712e7a4SEvan Quan int ret = 0; 158613f5dbd6SEvan Quan 158713f5dbd6SEvan Quan if (!pp_funcs->get_uclk_dpm_states) 158813f5dbd6SEvan Quan return -EOPNOTSUPP; 158913f5dbd6SEvan Quan 15903712e7a4SEvan Quan mutex_lock(&adev->pm.mutex); 15913712e7a4SEvan Quan ret = pp_funcs->get_uclk_dpm_states(adev->powerplay.pp_handle, 159213f5dbd6SEvan Quan clock_values_in_khz, 159313f5dbd6SEvan Quan num_states); 15943712e7a4SEvan Quan mutex_unlock(&adev->pm.mutex); 15953712e7a4SEvan Quan 15963712e7a4SEvan Quan return ret; 159713f5dbd6SEvan Quan } 159813f5dbd6SEvan Quan 159913f5dbd6SEvan Quan int amdgpu_dpm_get_dpm_clock_table(struct amdgpu_device *adev, 160013f5dbd6SEvan Quan struct dpm_clocks *clock_table) 160113f5dbd6SEvan Quan { 160213f5dbd6SEvan Quan const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 16033712e7a4SEvan Quan int ret = 0; 160413f5dbd6SEvan Quan 160513f5dbd6SEvan Quan if (!pp_funcs->get_dpm_clock_table) 160613f5dbd6SEvan Quan return -EOPNOTSUPP; 160713f5dbd6SEvan Quan 16083712e7a4SEvan Quan mutex_lock(&adev->pm.mutex); 16093712e7a4SEvan Quan ret = pp_funcs->get_dpm_clock_table(adev->powerplay.pp_handle, 161013f5dbd6SEvan Quan clock_table); 16113712e7a4SEvan Quan mutex_unlock(&adev->pm.mutex); 16123712e7a4SEvan Quan 16133712e7a4SEvan Quan return ret; 161413f5dbd6SEvan Quan } 1615