1 /*
2  * Copyright 2012 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  */
23 
24 #ifndef VI_STRUCTS_H_
25 #define VI_STRUCTS_H_
26 
27 struct vi_sdma_mqd {
28 	uint32_t sdmax_rlcx_rb_cntl;
29 	uint32_t sdmax_rlcx_rb_base;
30 	uint32_t sdmax_rlcx_rb_base_hi;
31 	uint32_t sdmax_rlcx_rb_rptr;
32 	uint32_t sdmax_rlcx_rb_wptr;
33 	uint32_t sdmax_rlcx_rb_wptr_poll_cntl;
34 	uint32_t sdmax_rlcx_rb_wptr_poll_addr_hi;
35 	uint32_t sdmax_rlcx_rb_wptr_poll_addr_lo;
36 	uint32_t sdmax_rlcx_rb_rptr_addr_hi;
37 	uint32_t sdmax_rlcx_rb_rptr_addr_lo;
38 	uint32_t sdmax_rlcx_ib_cntl;
39 	uint32_t sdmax_rlcx_ib_rptr;
40 	uint32_t sdmax_rlcx_ib_offset;
41 	uint32_t sdmax_rlcx_ib_base_lo;
42 	uint32_t sdmax_rlcx_ib_base_hi;
43 	uint32_t sdmax_rlcx_ib_size;
44 	uint32_t sdmax_rlcx_skip_cntl;
45 	uint32_t sdmax_rlcx_context_status;
46 	uint32_t sdmax_rlcx_doorbell;
47 	uint32_t sdmax_rlcx_virtual_addr;
48 	uint32_t sdmax_rlcx_ape1_cntl;
49 	uint32_t sdmax_rlcx_doorbell_log;
50 	uint32_t reserved_22;
51 	uint32_t reserved_23;
52 	uint32_t reserved_24;
53 	uint32_t reserved_25;
54 	uint32_t reserved_26;
55 	uint32_t reserved_27;
56 	uint32_t reserved_28;
57 	uint32_t reserved_29;
58 	uint32_t reserved_30;
59 	uint32_t reserved_31;
60 	uint32_t reserved_32;
61 	uint32_t reserved_33;
62 	uint32_t reserved_34;
63 	uint32_t reserved_35;
64 	uint32_t reserved_36;
65 	uint32_t reserved_37;
66 	uint32_t reserved_38;
67 	uint32_t reserved_39;
68 	uint32_t reserved_40;
69 	uint32_t reserved_41;
70 	uint32_t reserved_42;
71 	uint32_t reserved_43;
72 	uint32_t reserved_44;
73 	uint32_t reserved_45;
74 	uint32_t reserved_46;
75 	uint32_t reserved_47;
76 	uint32_t reserved_48;
77 	uint32_t reserved_49;
78 	uint32_t reserved_50;
79 	uint32_t reserved_51;
80 	uint32_t reserved_52;
81 	uint32_t reserved_53;
82 	uint32_t reserved_54;
83 	uint32_t reserved_55;
84 	uint32_t reserved_56;
85 	uint32_t reserved_57;
86 	uint32_t reserved_58;
87 	uint32_t reserved_59;
88 	uint32_t reserved_60;
89 	uint32_t reserved_61;
90 	uint32_t reserved_62;
91 	uint32_t reserved_63;
92 	uint32_t reserved_64;
93 	uint32_t reserved_65;
94 	uint32_t reserved_66;
95 	uint32_t reserved_67;
96 	uint32_t reserved_68;
97 	uint32_t reserved_69;
98 	uint32_t reserved_70;
99 	uint32_t reserved_71;
100 	uint32_t reserved_72;
101 	uint32_t reserved_73;
102 	uint32_t reserved_74;
103 	uint32_t reserved_75;
104 	uint32_t reserved_76;
105 	uint32_t reserved_77;
106 	uint32_t reserved_78;
107 	uint32_t reserved_79;
108 	uint32_t reserved_80;
109 	uint32_t reserved_81;
110 	uint32_t reserved_82;
111 	uint32_t reserved_83;
112 	uint32_t reserved_84;
113 	uint32_t reserved_85;
114 	uint32_t reserved_86;
115 	uint32_t reserved_87;
116 	uint32_t reserved_88;
117 	uint32_t reserved_89;
118 	uint32_t reserved_90;
119 	uint32_t reserved_91;
120 	uint32_t reserved_92;
121 	uint32_t reserved_93;
122 	uint32_t reserved_94;
123 	uint32_t reserved_95;
124 	uint32_t reserved_96;
125 	uint32_t reserved_97;
126 	uint32_t reserved_98;
127 	uint32_t reserved_99;
128 	uint32_t reserved_100;
129 	uint32_t reserved_101;
130 	uint32_t reserved_102;
131 	uint32_t reserved_103;
132 	uint32_t reserved_104;
133 	uint32_t reserved_105;
134 	uint32_t reserved_106;
135 	uint32_t reserved_107;
136 	uint32_t reserved_108;
137 	uint32_t reserved_109;
138 	uint32_t reserved_110;
139 	uint32_t reserved_111;
140 	uint32_t reserved_112;
141 	uint32_t reserved_113;
142 	uint32_t reserved_114;
143 	uint32_t reserved_115;
144 	uint32_t reserved_116;
145 	uint32_t reserved_117;
146 	uint32_t reserved_118;
147 	uint32_t reserved_119;
148 	uint32_t reserved_120;
149 	uint32_t reserved_121;
150 	uint32_t reserved_122;
151 	uint32_t reserved_123;
152 	uint32_t reserved_124;
153 	uint32_t reserved_125;
154 	uint32_t reserved_126;
155 	uint32_t reserved_127;
156 	uint32_t sdma_engine_id;
157 	uint32_t sdma_queue_id;
158 };
159 
160 struct vi_mqd {
161 	uint32_t header;
162 	uint32_t compute_dispatch_initiator;
163 	uint32_t compute_dim_x;
164 	uint32_t compute_dim_y;
165 	uint32_t compute_dim_z;
166 	uint32_t compute_start_x;
167 	uint32_t compute_start_y;
168 	uint32_t compute_start_z;
169 	uint32_t compute_num_thread_x;
170 	uint32_t compute_num_thread_y;
171 	uint32_t compute_num_thread_z;
172 	uint32_t compute_pipelinestat_enable;
173 	uint32_t compute_perfcount_enable;
174 	uint32_t compute_pgm_lo;
175 	uint32_t compute_pgm_hi;
176 	uint32_t compute_tba_lo;
177 	uint32_t compute_tba_hi;
178 	uint32_t compute_tma_lo;
179 	uint32_t compute_tma_hi;
180 	uint32_t compute_pgm_rsrc1;
181 	uint32_t compute_pgm_rsrc2;
182 	uint32_t compute_vmid;
183 	uint32_t compute_resource_limits;
184 	uint32_t compute_static_thread_mgmt_se0;
185 	uint32_t compute_static_thread_mgmt_se1;
186 	uint32_t compute_tmpring_size;
187 	uint32_t compute_static_thread_mgmt_se2;
188 	uint32_t compute_static_thread_mgmt_se3;
189 	uint32_t compute_restart_x;
190 	uint32_t compute_restart_y;
191 	uint32_t compute_restart_z;
192 	uint32_t compute_thread_trace_enable;
193 	uint32_t compute_misc_reserved;
194 	uint32_t compute_dispatch_id;
195 	uint32_t compute_threadgroup_id;
196 	uint32_t compute_relaunch;
197 	uint32_t compute_wave_restore_addr_lo;
198 	uint32_t compute_wave_restore_addr_hi;
199 	uint32_t compute_wave_restore_control;
200 	uint32_t reserved9;
201 	uint32_t reserved10;
202 	uint32_t reserved11;
203 	uint32_t reserved12;
204 	uint32_t reserved13;
205 	uint32_t reserved14;
206 	uint32_t reserved15;
207 	uint32_t reserved16;
208 	uint32_t reserved17;
209 	uint32_t reserved18;
210 	uint32_t reserved19;
211 	uint32_t reserved20;
212 	uint32_t reserved21;
213 	uint32_t reserved22;
214 	uint32_t reserved23;
215 	uint32_t reserved24;
216 	uint32_t reserved25;
217 	uint32_t reserved26;
218 	uint32_t reserved27;
219 	uint32_t reserved28;
220 	uint32_t reserved29;
221 	uint32_t reserved30;
222 	uint32_t reserved31;
223 	uint32_t reserved32;
224 	uint32_t reserved33;
225 	uint32_t reserved34;
226 	uint32_t compute_user_data_0;
227 	uint32_t compute_user_data_1;
228 	uint32_t compute_user_data_2;
229 	uint32_t compute_user_data_3;
230 	uint32_t compute_user_data_4;
231 	uint32_t compute_user_data_5;
232 	uint32_t compute_user_data_6;
233 	uint32_t compute_user_data_7;
234 	uint32_t compute_user_data_8;
235 	uint32_t compute_user_data_9;
236 	uint32_t compute_user_data_10;
237 	uint32_t compute_user_data_11;
238 	uint32_t compute_user_data_12;
239 	uint32_t compute_user_data_13;
240 	uint32_t compute_user_data_14;
241 	uint32_t compute_user_data_15;
242 	uint32_t cp_compute_csinvoc_count_lo;
243 	uint32_t cp_compute_csinvoc_count_hi;
244 	uint32_t reserved35;
245 	uint32_t reserved36;
246 	uint32_t reserved37;
247 	uint32_t cp_mqd_query_time_lo;
248 	uint32_t cp_mqd_query_time_hi;
249 	uint32_t cp_mqd_connect_start_time_lo;
250 	uint32_t cp_mqd_connect_start_time_hi;
251 	uint32_t cp_mqd_connect_end_time_lo;
252 	uint32_t cp_mqd_connect_end_time_hi;
253 	uint32_t cp_mqd_connect_end_wf_count;
254 	uint32_t cp_mqd_connect_end_pq_rptr;
255 	uint32_t cp_mqd_connect_endvi_sdma_mqd_pq_wptr;
256 	uint32_t cp_mqd_connect_end_ib_rptr;
257 	uint32_t reserved38;
258 	uint32_t reserved39;
259 	uint32_t cp_mqd_save_start_time_lo;
260 	uint32_t cp_mqd_save_start_time_hi;
261 	uint32_t cp_mqd_save_end_time_lo;
262 	uint32_t cp_mqd_save_end_time_hi;
263 	uint32_t cp_mqd_restore_start_time_lo;
264 	uint32_t cp_mqd_restore_start_time_hi;
265 	uint32_t cp_mqd_restore_end_time_lo;
266 	uint32_t cp_mqd_restore_end_time_hi;
267 	uint32_t disable_queue;
268 	uint32_t reserved41;
269 	uint32_t gds_cs_ctxsw_cnt0;
270 	uint32_t gds_cs_ctxsw_cnt1;
271 	uint32_t gds_cs_ctxsw_cnt2;
272 	uint32_t gds_cs_ctxsw_cnt3;
273 	uint32_t reserved42;
274 	uint32_t reserved43;
275 	uint32_t cp_pq_exe_status_lo;
276 	uint32_t cp_pq_exe_status_hi;
277 	uint32_t cp_packet_id_lo;
278 	uint32_t cp_packet_id_hi;
279 	uint32_t cp_packet_exe_status_lo;
280 	uint32_t cp_packet_exe_status_hi;
281 	uint32_t gds_save_base_addr_lo;
282 	uint32_t gds_save_base_addr_hi;
283 	uint32_t gds_save_mask_lo;
284 	uint32_t gds_save_mask_hi;
285 	uint32_t ctx_save_base_addr_lo;
286 	uint32_t ctx_save_base_addr_hi;
287 	uint32_t dynamic_cu_mask_addr_lo;
288 	uint32_t dynamic_cu_mask_addr_hi;
289 	uint32_t cp_mqd_base_addr_lo;
290 	uint32_t cp_mqd_base_addr_hi;
291 	uint32_t cp_hqd_active;
292 	uint32_t cp_hqd_vmid;
293 	uint32_t cp_hqd_persistent_state;
294 	uint32_t cp_hqd_pipe_priority;
295 	uint32_t cp_hqd_queue_priority;
296 	uint32_t cp_hqd_quantum;
297 	uint32_t cp_hqd_pq_base_lo;
298 	uint32_t cp_hqd_pq_base_hi;
299 	uint32_t cp_hqd_pq_rptr;
300 	uint32_t cp_hqd_pq_rptr_report_addr_lo;
301 	uint32_t cp_hqd_pq_rptr_report_addr_hi;
302 	uint32_t cp_hqd_pq_wptr_poll_addr_lo;
303 	uint32_t cp_hqd_pq_wptr_poll_addr_hi;
304 	uint32_t cp_hqd_pq_doorbell_control;
305 	uint32_t cp_hqd_pq_wptr;
306 	uint32_t cp_hqd_pq_control;
307 	uint32_t cp_hqd_ib_base_addr_lo;
308 	uint32_t cp_hqd_ib_base_addr_hi;
309 	uint32_t cp_hqd_ib_rptr;
310 	uint32_t cp_hqd_ib_control;
311 	uint32_t cp_hqd_iq_timer;
312 	uint32_t cp_hqd_iq_rptr;
313 	uint32_t cp_hqd_dequeue_request;
314 	uint32_t cp_hqd_dma_offload;
315 	uint32_t cp_hqd_sema_cmd;
316 	uint32_t cp_hqd_msg_type;
317 	uint32_t cp_hqd_atomic0_preop_lo;
318 	uint32_t cp_hqd_atomic0_preop_hi;
319 	uint32_t cp_hqd_atomic1_preop_lo;
320 	uint32_t cp_hqd_atomic1_preop_hi;
321 	uint32_t cp_hqd_hq_status0;
322 	uint32_t cp_hqd_hq_control0;
323 	uint32_t cp_mqd_control;
324 	uint32_t cp_hqd_hq_status1;
325 	uint32_t cp_hqd_hq_control1;
326 	uint32_t cp_hqd_eop_base_addr_lo;
327 	uint32_t cp_hqd_eop_base_addr_hi;
328 	uint32_t cp_hqd_eop_control;
329 	uint32_t cp_hqd_eop_rptr;
330 	uint32_t cp_hqd_eop_wptr;
331 	uint32_t cp_hqd_eop_done_events;
332 	uint32_t cp_hqd_ctx_save_base_addr_lo;
333 	uint32_t cp_hqd_ctx_save_base_addr_hi;
334 	uint32_t cp_hqd_ctx_save_control;
335 	uint32_t cp_hqd_cntl_stack_offset;
336 	uint32_t cp_hqd_cntl_stack_size;
337 	uint32_t cp_hqd_wg_state_offset;
338 	uint32_t cp_hqd_ctx_save_size;
339 	uint32_t cp_hqd_gds_resource_state;
340 	uint32_t cp_hqd_error;
341 	uint32_t cp_hqd_eop_wptr_mem;
342 	uint32_t cp_hqd_eop_dones;
343 	uint32_t reserved46;
344 	uint32_t reserved47;
345 	uint32_t reserved48;
346 	uint32_t reserved49;
347 	uint32_t reserved50;
348 	uint32_t reserved51;
349 	uint32_t reserved52;
350 	uint32_t reserved53;
351 	uint32_t reserved54;
352 	uint32_t reserved55;
353 	uint32_t iqtimer_pkt_header;
354 	uint32_t iqtimer_pkt_dw0;
355 	uint32_t iqtimer_pkt_dw1;
356 	uint32_t iqtimer_pkt_dw2;
357 	uint32_t iqtimer_pkt_dw3;
358 	uint32_t iqtimer_pkt_dw4;
359 	uint32_t iqtimer_pkt_dw5;
360 	uint32_t iqtimer_pkt_dw6;
361 	uint32_t iqtimer_pkt_dw7;
362 	uint32_t iqtimer_pkt_dw8;
363 	uint32_t iqtimer_pkt_dw9;
364 	uint32_t iqtimer_pkt_dw10;
365 	uint32_t iqtimer_pkt_dw11;
366 	uint32_t iqtimer_pkt_dw12;
367 	uint32_t iqtimer_pkt_dw13;
368 	uint32_t iqtimer_pkt_dw14;
369 	uint32_t iqtimer_pkt_dw15;
370 	uint32_t iqtimer_pkt_dw16;
371 	uint32_t iqtimer_pkt_dw17;
372 	uint32_t iqtimer_pkt_dw18;
373 	uint32_t iqtimer_pkt_dw19;
374 	uint32_t iqtimer_pkt_dw20;
375 	uint32_t iqtimer_pkt_dw21;
376 	uint32_t iqtimer_pkt_dw22;
377 	uint32_t iqtimer_pkt_dw23;
378 	uint32_t iqtimer_pkt_dw24;
379 	uint32_t iqtimer_pkt_dw25;
380 	uint32_t iqtimer_pkt_dw26;
381 	uint32_t iqtimer_pkt_dw27;
382 	uint32_t iqtimer_pkt_dw28;
383 	uint32_t iqtimer_pkt_dw29;
384 	uint32_t iqtimer_pkt_dw30;
385 	uint32_t iqtimer_pkt_dw31;
386 	uint32_t reserved56;
387 	uint32_t reserved57;
388 	uint32_t reserved58;
389 	uint32_t set_resources_header;
390 	uint32_t set_resources_dw1;
391 	uint32_t set_resources_dw2;
392 	uint32_t set_resources_dw3;
393 	uint32_t set_resources_dw4;
394 	uint32_t set_resources_dw5;
395 	uint32_t set_resources_dw6;
396 	uint32_t set_resources_dw7;
397 	uint32_t reserved59;
398 	uint32_t reserved60;
399 	uint32_t reserved61;
400 	uint32_t reserved62;
401 	uint32_t reserved63;
402 	uint32_t reserved64;
403 	uint32_t reserved65;
404 	uint32_t reserved66;
405 	uint32_t reserved67;
406 	uint32_t reserved68;
407 	uint32_t reserved69;
408 	uint32_t reserved70;
409 	uint32_t reserved71;
410 	uint32_t reserved72;
411 	uint32_t reserved73;
412 	uint32_t reserved74;
413 	uint32_t reserved75;
414 	uint32_t reserved76;
415 	uint32_t reserved77;
416 	uint32_t reserved78;
417 	uint32_t reserved_t[256];
418 };
419 
420 struct vi_mqd_allocation {
421 	struct vi_mqd mqd;
422 	uint32_t wptr_poll_mem;
423 	uint32_t rptr_report_mem;
424 	uint32_t dynamic_cu_mask;
425 	uint32_t dynamic_rb_mask;
426 };
427 
428 struct vi_ce_ib_state {
429 	uint32_t    ce_ib_completion_status;
430 	uint32_t    ce_constegnine_count;
431 	uint32_t    ce_ibOffset_ib1;
432 	uint32_t    ce_ibOffset_ib2;
433 }; /* Total of 4 DWORD */
434 
435 struct vi_de_ib_state {
436 	uint32_t    ib_completion_status;
437 	uint32_t    de_constEngine_count;
438 	uint32_t    ib_offset_ib1;
439 	uint32_t    ib_offset_ib2;
440 	uint32_t    preamble_begin_ib1;
441 	uint32_t    preamble_begin_ib2;
442 	uint32_t    preamble_end_ib1;
443 	uint32_t    preamble_end_ib2;
444 	uint32_t    draw_indirect_baseLo;
445 	uint32_t    draw_indirect_baseHi;
446 	uint32_t    disp_indirect_baseLo;
447 	uint32_t    disp_indirect_baseHi;
448 	uint32_t    gds_backup_addrlo;
449 	uint32_t    gds_backup_addrhi;
450 	uint32_t    index_base_addrlo;
451 	uint32_t    index_base_addrhi;
452 	uint32_t    sample_cntl;
453 }; /* Total of 17 DWORD */
454 
455 struct vi_ce_ib_state_chained_ib {
456 	/* section of non chained ib part */
457 	uint32_t    ce_ib_completion_status;
458 	uint32_t    ce_constegnine_count;
459 	uint32_t    ce_ibOffset_ib1;
460 	uint32_t    ce_ibOffset_ib2;
461 
462 	/* section of chained ib */
463 	uint32_t    ce_chainib_addrlo_ib1;
464 	uint32_t    ce_chainib_addrlo_ib2;
465 	uint32_t    ce_chainib_addrhi_ib1;
466 	uint32_t    ce_chainib_addrhi_ib2;
467 	uint32_t    ce_chainib_size_ib1;
468 	uint32_t    ce_chainib_size_ib2;
469 }; /* total 10 DWORD */
470 
471 struct vi_de_ib_state_chained_ib {
472 	/* section of non chained ib part */
473 	uint32_t    ib_completion_status;
474 	uint32_t    de_constEngine_count;
475 	uint32_t    ib_offset_ib1;
476 	uint32_t    ib_offset_ib2;
477 
478 	/* section of chained ib */
479 	uint32_t    chain_ib_addrlo_ib1;
480 	uint32_t    chain_ib_addrlo_ib2;
481 	uint32_t    chain_ib_addrhi_ib1;
482 	uint32_t    chain_ib_addrhi_ib2;
483 	uint32_t    chain_ib_size_ib1;
484 	uint32_t    chain_ib_size_ib2;
485 
486 	/* section of non chained ib part */
487 	uint32_t    preamble_begin_ib1;
488 	uint32_t    preamble_begin_ib2;
489 	uint32_t    preamble_end_ib1;
490 	uint32_t    preamble_end_ib2;
491 
492 	/* section of chained ib */
493 	uint32_t    chain_ib_pream_addrlo_ib1;
494 	uint32_t    chain_ib_pream_addrlo_ib2;
495 	uint32_t    chain_ib_pream_addrhi_ib1;
496 	uint32_t    chain_ib_pream_addrhi_ib2;
497 
498 	/* section of non chained ib part */
499 	uint32_t    draw_indirect_baseLo;
500 	uint32_t    draw_indirect_baseHi;
501 	uint32_t    disp_indirect_baseLo;
502 	uint32_t    disp_indirect_baseHi;
503 	uint32_t    gds_backup_addrlo;
504 	uint32_t    gds_backup_addrhi;
505 	uint32_t    index_base_addrlo;
506 	uint32_t    index_base_addrhi;
507 	uint32_t    sample_cntl;
508 }; /* Total of 27 DWORD */
509 
510 struct vi_gfx_meta_data {
511 	/* 4 DWORD, address must be 4KB aligned */
512 	struct vi_ce_ib_state        ce_payload;
513 	uint32_t                     reserved1[60];
514 	/* 17 DWORD, address must be 64B aligned */
515 	struct vi_de_ib_state        de_payload;
516 	/* PFP IB base address which get pre-empted */
517 	uint32_t                     DeIbBaseAddrLo;
518 	uint32_t                     DeIbBaseAddrHi;
519 	uint32_t                     reserved2[941];
520 }; /* Total of 4K Bytes */
521 
522 struct vi_gfx_meta_data_chained_ib {
523 	/* 10 DWORD, address must be 4KB aligned */
524 	struct vi_ce_ib_state_chained_ib       ce_payload;
525 	uint32_t                               reserved1[54];
526 	/* 27 DWORD, address must be 64B aligned */
527 	struct vi_de_ib_state_chained_ib       de_payload;
528 	/* PFP IB base address which get pre-empted */
529 	uint32_t                               DeIbBaseAddrLo;
530 	uint32_t                               DeIbBaseAddrHi;
531 	uint32_t                               reserved2[931];
532 }; /* Total of 4K Bytes */
533 
534 #endif /* VI_STRUCTS_H_ */
535