1 /*
2  * Copyright (C) 2019  Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included
12  * in all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
15  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
18  * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
19  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
20  */
21 #ifndef _renoir_ip_offset_HEADER
22 #define _renoir_ip_offset_HEADER
23 
24 #define MAX_INSTANCE                                       7
25 #define MAX_SEGMENT                                        5
26 
27 
28 struct IP_BASE_INSTANCE
29 {
30     unsigned int segment[MAX_SEGMENT];
31 };
32 
33 struct IP_BASE
34 {
35     struct IP_BASE_INSTANCE instance[MAX_INSTANCE];
36 };
37 
38 
39 static const struct IP_BASE ACP_BASE ={ { { { 0x02403800, 0x00480000, 0, 0, 0 } },
40                                         { { 0, 0, 0, 0, 0 } },
41                                         { { 0, 0, 0, 0, 0 } },
42                                         { { 0, 0, 0, 0, 0 } },
43                                         { { 0, 0, 0, 0, 0 } },
44                                         { { 0, 0, 0, 0, 0 } },
45                                         { { 0, 0, 0, 0, 0 } } } };
46 static const struct IP_BASE ATHUB_BASE ={ { { { 0x00000C20, 0x02408C00, 0, 0, 0 } },
47                                         { { 0, 0, 0, 0, 0 } },
48                                         { { 0, 0, 0, 0, 0 } },
49                                         { { 0, 0, 0, 0, 0 } },
50                                         { { 0, 0, 0, 0, 0 } },
51                                         { { 0, 0, 0, 0, 0 } },
52                                         { { 0, 0, 0, 0, 0 } } } };
53 static const struct IP_BASE CLK_BASE ={ { { { 0x00016C00, 0x00016E00, 0x00017000, 0x00017E00, 0 } },
54                                         { { 0, 0, 0, 0, 0 } },
55                                         { { 0, 0, 0, 0, 0 } },
56                                         { { 0, 0, 0, 0, 0 } },
57                                         { { 0, 0, 0, 0, 0 } },
58                                         { { 0, 0, 0, 0, 0 } },
59                                         { { 0, 0, 0, 0, 0 } } } };
60 static const struct IP_BASE DBGU_IO0_BASE ={ { { { 0x000001E0, 0x0240B400, 0, 0, 0 } },
61                                         { { 0, 0, 0, 0, 0 } },
62                                         { { 0, 0, 0, 0, 0 } },
63                                         { { 0, 0, 0, 0, 0 } },
64                                         { { 0, 0, 0, 0, 0 } },
65                                         { { 0, 0, 0, 0, 0 } },
66                                         { { 0, 0, 0, 0, 0 } } } };
67 static const struct IP_BASE DF_BASE ={ { { { 0x00007000, 0x0240B800, 0, 0, 0 } },
68                                         { { 0, 0, 0, 0, 0 } },
69                                         { { 0, 0, 0, 0, 0 } },
70                                         { { 0, 0, 0, 0, 0 } },
71                                         { { 0, 0, 0, 0, 0 } },
72                                         { { 0, 0, 0, 0, 0 } },
73                                         { { 0, 0, 0, 0, 0 } } } };
74 static const struct IP_BASE DIO_BASE ={ { { { 0x02404000, 0, 0, 0, 0 } },
75                                         { { 0, 0, 0, 0, 0 } },
76                                         { { 0, 0, 0, 0, 0 } },
77                                         { { 0, 0, 0, 0, 0 } },
78                                         { { 0, 0, 0, 0, 0 } },
79                                         { { 0, 0, 0, 0, 0 } },
80                                         { { 0, 0, 0, 0, 0 } } } };
81 static const struct IP_BASE DMU_BASE ={ { { { 0x00000012, 0x000000C0, 0x000034C0, 0x00009000, 0x02403C00 } },
82                                         { { 0, 0, 0, 0, 0 } },
83                                         { { 0, 0, 0, 0, 0 } },
84                                         { { 0, 0, 0, 0, 0 } },
85                                         { { 0, 0, 0, 0, 0 } },
86                                         { { 0, 0, 0, 0, 0 } },
87                                         { { 0, 0, 0, 0, 0 } } } };
88 static const struct IP_BASE DPCS_BASE ={ { { { 0x00000012, 0x000000C0, 0x000034C0, 0x00009000, 0x02403C00 } },
89                                         { { 0, 0, 0, 0, 0 } },
90                                         { { 0, 0, 0, 0, 0 } },
91                                         { { 0, 0, 0, 0, 0 } },
92                                         { { 0, 0, 0, 0, 0 } },
93                                         { { 0, 0, 0, 0, 0 } },
94                                         { { 0, 0, 0, 0, 0 } } } };
95 static const struct IP_BASE FUSE_BASE ={ { { { 0x00017400, 0x02401400, 0, 0, 0 } },
96                                         { { 0, 0, 0, 0, 0 } },
97                                         { { 0, 0, 0, 0, 0 } },
98                                         { { 0, 0, 0, 0, 0 } },
99                                         { { 0, 0, 0, 0, 0 } },
100                                         { { 0, 0, 0, 0, 0 } },
101                                         { { 0, 0, 0, 0, 0 } } } };
102 static const struct IP_BASE GC_BASE ={ { { { 0x00002000, 0x0000A000, 0x02402C00, 0, 0 } },
103                                         { { 0, 0, 0, 0, 0 } },
104                                         { { 0, 0, 0, 0, 0 } },
105                                         { { 0, 0, 0, 0, 0 } },
106                                         { { 0, 0, 0, 0, 0 } },
107                                         { { 0, 0, 0, 0, 0 } },
108                                         { { 0, 0, 0, 0, 0 } } } };
109 static const struct IP_BASE HDA_BASE ={ { { { 0x02404800, 0x004C0000, 0, 0, 0 } },
110                                         { { 0, 0, 0, 0, 0 } },
111                                         { { 0, 0, 0, 0, 0 } },
112                                         { { 0, 0, 0, 0, 0 } },
113                                         { { 0, 0, 0, 0, 0 } },
114                                         { { 0, 0, 0, 0, 0 } },
115                                         { { 0, 0, 0, 0, 0 } } } };
116 static const struct IP_BASE HDP_BASE ={ { { { 0x00000F20, 0x0240A400, 0, 0, 0 } },
117                                         { { 0, 0, 0, 0, 0 } },
118                                         { { 0, 0, 0, 0, 0 } },
119                                         { { 0, 0, 0, 0, 0 } },
120                                         { { 0, 0, 0, 0, 0 } },
121                                         { { 0, 0, 0, 0, 0 } },
122                                         { { 0, 0, 0, 0, 0 } } } };
123 static const struct IP_BASE IOHC0_BASE ={ { { { 0x00010000, 0x02406000, 0x04EC0000, 0, 0 } },
124                                         { { 0, 0, 0, 0, 0 } },
125                                         { { 0, 0, 0, 0, 0 } },
126                                         { { 0, 0, 0, 0, 0 } },
127                                         { { 0, 0, 0, 0, 0 } },
128                                         { { 0, 0, 0, 0, 0 } },
129                                         { { 0, 0, 0, 0, 0 } } } };
130 static const struct IP_BASE ISP_BASE ={ { { { 0x00018000, 0x0240B000, 0, 0, 0 } },
131                                         { { 0, 0, 0, 0, 0 } },
132                                         { { 0, 0, 0, 0, 0 } },
133                                         { { 0, 0, 0, 0, 0 } },
134                                         { { 0, 0, 0, 0, 0 } },
135                                         { { 0, 0, 0, 0, 0 } },
136                                         { { 0, 0, 0, 0, 0 } } } };
137 static const struct IP_BASE L2IMU0_BASE ={ { { { 0x00007DC0, 0x02407000, 0x00900000, 0x04FC0000, 0x055C0000 } },
138                                         { { 0, 0, 0, 0, 0 } },
139                                         { { 0, 0, 0, 0, 0 } },
140                                         { { 0, 0, 0, 0, 0 } },
141                                         { { 0, 0, 0, 0, 0 } },
142                                         { { 0, 0, 0, 0, 0 } },
143                                         { { 0, 0, 0, 0, 0 } } } };
144 static const struct IP_BASE MMHUB_BASE ={ { { { 0x0001A000, 0x02408800, 0, 0, 0 } },
145                                         { { 0, 0, 0, 0, 0 } },
146                                         { { 0, 0, 0, 0, 0 } },
147                                         { { 0, 0, 0, 0, 0 } },
148                                         { { 0, 0, 0, 0, 0 } },
149                                         { { 0, 0, 0, 0, 0 } },
150                                         { { 0, 0, 0, 0, 0 } } } };
151 static const struct IP_BASE MP0_BASE ={ { { { 0x00016000, 0x0243FC00, 0x00DC0000, 0x00E00000, 0x00E40000 } },
152                                         { { 0, 0, 0, 0, 0 } },
153                                         { { 0, 0, 0, 0, 0 } },
154                                         { { 0, 0, 0, 0, 0 } },
155                                         { { 0, 0, 0, 0, 0 } },
156                                         { { 0, 0, 0, 0, 0 } },
157                                         { { 0, 0, 0, 0, 0 } } } };
158 static const struct IP_BASE MP1_BASE ={ { { { 0x00016000, 0x02400400, 0x00E80000, 0x00EC0000, 0x00F00000 } },
159                                         { { 0, 0, 0, 0, 0 } },
160                                         { { 0, 0, 0, 0, 0 } },
161                                         { { 0, 0, 0, 0, 0 } },
162                                         { { 0, 0, 0, 0, 0 } },
163                                         { { 0, 0, 0, 0, 0 } },
164                                         { { 0, 0, 0, 0, 0 } } } };
165 static const struct IP_BASE NBIF0_BASE ={ { { { 0x00000000, 0x00000014, 0x00000D20, 0x00010400, 0x0241B000 } },
166                                         { { 0, 0, 0, 0, 0 } },
167                                         { { 0, 0, 0, 0, 0 } },
168                                         { { 0, 0, 0, 0, 0 } },
169                                         { { 0, 0, 0, 0, 0 } },
170                                         { { 0, 0, 0, 0, 0 } },
171                                         { { 0, 0, 0, 0, 0 } } } };
172 static const struct IP_BASE OSSSYS_BASE ={ { { { 0x000010A0, 0x0240A000, 0, 0, 0 } },
173                                         { { 0, 0, 0, 0, 0 } },
174                                         { { 0, 0, 0, 0, 0 } },
175                                         { { 0, 0, 0, 0, 0 } },
176                                         { { 0, 0, 0, 0, 0 } },
177                                         { { 0, 0, 0, 0, 0 } },
178                                         { { 0, 0, 0, 0, 0 } } } };
179 static const struct IP_BASE PCIE0_BASE ={ { { { 0x02411800, 0x04440000, 0, 0, 0 } },
180                                         { { 0, 0, 0, 0, 0 } },
181                                         { { 0, 0, 0, 0, 0 } },
182                                         { { 0, 0, 0, 0, 0 } },
183                                         { { 0, 0, 0, 0, 0 } },
184                                         { { 0, 0, 0, 0, 0 } },
185                                         { { 0, 0, 0, 0, 0 } } } };
186 static const struct IP_BASE SDMA0_BASE ={ { { { 0x00001260, 0x0240A800, 0, 0, 0 } },
187                                         { { 0, 0, 0, 0, 0 } },
188                                         { { 0, 0, 0, 0, 0 } },
189                                         { { 0, 0, 0, 0, 0 } },
190                                         { { 0, 0, 0, 0, 0 } },
191                                         { { 0, 0, 0, 0, 0 } },
192                                         { { 0, 0, 0, 0, 0 } } } };
193 static const struct IP_BASE SMUIO_BASE ={ { { { 0x00016800, 0x00016A00, 0x02401000, 0x00440000, 0 } },
194                                         { { 0, 0, 0, 0, 0 } },
195                                         { { 0, 0, 0, 0, 0 } },
196                                         { { 0, 0, 0, 0, 0 } },
197                                         { { 0, 0, 0, 0, 0 } },
198                                         { { 0, 0, 0, 0, 0 } },
199                                         { { 0, 0, 0, 0, 0 } } } };
200 static const struct IP_BASE THM_BASE ={ { { { 0x00016600, 0x02400C00, 0, 0, 0 } },
201                                         { { 0, 0, 0, 0, 0 } },
202                                         { { 0, 0, 0, 0, 0 } },
203                                         { { 0, 0, 0, 0, 0 } },
204                                         { { 0, 0, 0, 0, 0 } },
205                                         { { 0, 0, 0, 0, 0 } },
206                                         { { 0, 0, 0, 0, 0 } } } };
207 static const struct IP_BASE UMC_BASE ={ { { { 0x00014000, 0x02425800, 0, 0, 0 } },
208                                         { { 0x00054000, 0x02425C00, 0, 0, 0 } },
209                                         { { 0, 0, 0, 0, 0 } },
210                                         { { 0, 0, 0, 0, 0 } },
211                                         { { 0, 0, 0, 0, 0 } },
212                                         { { 0, 0, 0, 0, 0 } },
213                                         { { 0, 0, 0, 0, 0 } } } };
214 static const struct IP_BASE USB0_BASE ={ { { { 0x0242A800, 0x05B00000, 0, 0, 0 } },
215                                         { { 0, 0, 0, 0, 0 } },
216                                         { { 0, 0, 0, 0, 0 } },
217                                         { { 0, 0, 0, 0, 0 } },
218                                         { { 0, 0, 0, 0, 0 } },
219                                         { { 0, 0, 0, 0, 0 } },
220                                         { { 0, 0, 0, 0, 0 } } } };
221 static const struct IP_BASE UVD0_BASE ={ { { { 0x00007800, 0x00007E00, 0x02403000, 0, 0 } },
222                                         { { 0, 0, 0, 0, 0 } },
223                                         { { 0, 0, 0, 0, 0 } },
224                                         { { 0, 0, 0, 0, 0 } },
225                                         { { 0, 0, 0, 0, 0 } },
226                                         { { 0, 0, 0, 0, 0 } },
227                                         { { 0, 0, 0, 0, 0 } } } };
228 
229 
230 #define ACP_BASE__INST0_SEG0                       0x02403800
231 #define ACP_BASE__INST0_SEG1                       0x00480000
232 #define ACP_BASE__INST0_SEG2                       0
233 #define ACP_BASE__INST0_SEG3                       0
234 #define ACP_BASE__INST0_SEG4                       0
235 
236 #define ACP_BASE__INST1_SEG0                       0
237 #define ACP_BASE__INST1_SEG1                       0
238 #define ACP_BASE__INST1_SEG2                       0
239 #define ACP_BASE__INST1_SEG3                       0
240 #define ACP_BASE__INST1_SEG4                       0
241 
242 #define ACP_BASE__INST2_SEG0                       0
243 #define ACP_BASE__INST2_SEG1                       0
244 #define ACP_BASE__INST2_SEG2                       0
245 #define ACP_BASE__INST2_SEG3                       0
246 #define ACP_BASE__INST2_SEG4                       0
247 
248 #define ACP_BASE__INST3_SEG0                       0
249 #define ACP_BASE__INST3_SEG1                       0
250 #define ACP_BASE__INST3_SEG2                       0
251 #define ACP_BASE__INST3_SEG3                       0
252 #define ACP_BASE__INST3_SEG4                       0
253 
254 #define ACP_BASE__INST4_SEG0                       0
255 #define ACP_BASE__INST4_SEG1                       0
256 #define ACP_BASE__INST4_SEG2                       0
257 #define ACP_BASE__INST4_SEG3                       0
258 #define ACP_BASE__INST4_SEG4                       0
259 
260 #define ACP_BASE__INST5_SEG0                       0
261 #define ACP_BASE__INST5_SEG1                       0
262 #define ACP_BASE__INST5_SEG2                       0
263 #define ACP_BASE__INST5_SEG3                       0
264 #define ACP_BASE__INST5_SEG4                       0
265 
266 #define ACP_BASE__INST6_SEG0                       0
267 #define ACP_BASE__INST6_SEG1                       0
268 #define ACP_BASE__INST6_SEG2                       0
269 #define ACP_BASE__INST6_SEG3                       0
270 #define ACP_BASE__INST6_SEG4                       0
271 
272 #define ATHUB_BASE__INST0_SEG0                     0x00000C20
273 #define ATHUB_BASE__INST0_SEG1                     0x02408C00
274 #define ATHUB_BASE__INST0_SEG2                     0
275 #define ATHUB_BASE__INST0_SEG3                     0
276 #define ATHUB_BASE__INST0_SEG4                     0
277 
278 #define ATHUB_BASE__INST1_SEG0                     0
279 #define ATHUB_BASE__INST1_SEG1                     0
280 #define ATHUB_BASE__INST1_SEG2                     0
281 #define ATHUB_BASE__INST1_SEG3                     0
282 #define ATHUB_BASE__INST1_SEG4                     0
283 
284 #define ATHUB_BASE__INST2_SEG0                     0
285 #define ATHUB_BASE__INST2_SEG1                     0
286 #define ATHUB_BASE__INST2_SEG2                     0
287 #define ATHUB_BASE__INST2_SEG3                     0
288 #define ATHUB_BASE__INST2_SEG4                     0
289 
290 #define ATHUB_BASE__INST3_SEG0                     0
291 #define ATHUB_BASE__INST3_SEG1                     0
292 #define ATHUB_BASE__INST3_SEG2                     0
293 #define ATHUB_BASE__INST3_SEG3                     0
294 #define ATHUB_BASE__INST3_SEG4                     0
295 
296 #define ATHUB_BASE__INST4_SEG0                     0
297 #define ATHUB_BASE__INST4_SEG1                     0
298 #define ATHUB_BASE__INST4_SEG2                     0
299 #define ATHUB_BASE__INST4_SEG3                     0
300 #define ATHUB_BASE__INST4_SEG4                     0
301 
302 #define ATHUB_BASE__INST5_SEG0                     0
303 #define ATHUB_BASE__INST5_SEG1                     0
304 #define ATHUB_BASE__INST5_SEG2                     0
305 #define ATHUB_BASE__INST5_SEG3                     0
306 #define ATHUB_BASE__INST5_SEG4                     0
307 
308 #define ATHUB_BASE__INST6_SEG0                     0
309 #define ATHUB_BASE__INST6_SEG1                     0
310 #define ATHUB_BASE__INST6_SEG2                     0
311 #define ATHUB_BASE__INST6_SEG3                     0
312 #define ATHUB_BASE__INST6_SEG4                     0
313 
314 #define CLK_BASE__INST0_SEG0                       0x00016C00
315 #define CLK_BASE__INST0_SEG1                       0x00016E00
316 #define CLK_BASE__INST0_SEG2                       0x00017000
317 #define CLK_BASE__INST0_SEG3                       0x00017E00
318 #define CLK_BASE__INST0_SEG4                       0
319 
320 #define CLK_BASE__INST1_SEG0                       0
321 #define CLK_BASE__INST1_SEG1                       0
322 #define CLK_BASE__INST1_SEG2                       0
323 #define CLK_BASE__INST1_SEG3                       0
324 #define CLK_BASE__INST1_SEG4                       0
325 
326 #define CLK_BASE__INST2_SEG0                       0
327 #define CLK_BASE__INST2_SEG1                       0
328 #define CLK_BASE__INST2_SEG2                       0
329 #define CLK_BASE__INST2_SEG3                       0
330 #define CLK_BASE__INST2_SEG4                       0
331 
332 #define CLK_BASE__INST3_SEG0                       0
333 #define CLK_BASE__INST3_SEG1                       0
334 #define CLK_BASE__INST3_SEG2                       0
335 #define CLK_BASE__INST3_SEG3                       0
336 #define CLK_BASE__INST3_SEG4                       0
337 
338 #define CLK_BASE__INST4_SEG0                       0
339 #define CLK_BASE__INST4_SEG1                       0
340 #define CLK_BASE__INST4_SEG2                       0
341 #define CLK_BASE__INST4_SEG3                       0
342 #define CLK_BASE__INST4_SEG4                       0
343 
344 #define CLK_BASE__INST5_SEG0                       0
345 #define CLK_BASE__INST5_SEG1                       0
346 #define CLK_BASE__INST5_SEG2                       0
347 #define CLK_BASE__INST5_SEG3                       0
348 #define CLK_BASE__INST5_SEG4                       0
349 
350 #define CLK_BASE__INST6_SEG0                       0
351 #define CLK_BASE__INST6_SEG1                       0
352 #define CLK_BASE__INST6_SEG2                       0
353 #define CLK_BASE__INST6_SEG3                       0
354 #define CLK_BASE__INST6_SEG4                       0
355 
356 #define DBGU_IO0_BASE__INST0_SEG0                  0x000001E0
357 #define DBGU_IO0_BASE__INST0_SEG1                  0x0240B400
358 #define DBGU_IO0_BASE__INST0_SEG2                  0
359 #define DBGU_IO0_BASE__INST0_SEG3                  0
360 #define DBGU_IO0_BASE__INST0_SEG4                  0
361 
362 #define DBGU_IO0_BASE__INST1_SEG0                  0
363 #define DBGU_IO0_BASE__INST1_SEG1                  0
364 #define DBGU_IO0_BASE__INST1_SEG2                  0
365 #define DBGU_IO0_BASE__INST1_SEG3                  0
366 #define DBGU_IO0_BASE__INST1_SEG4                  0
367 
368 #define DBGU_IO0_BASE__INST2_SEG0                  0
369 #define DBGU_IO0_BASE__INST2_SEG1                  0
370 #define DBGU_IO0_BASE__INST2_SEG2                  0
371 #define DBGU_IO0_BASE__INST2_SEG3                  0
372 #define DBGU_IO0_BASE__INST2_SEG4                  0
373 
374 #define DBGU_IO0_BASE__INST3_SEG0                  0
375 #define DBGU_IO0_BASE__INST3_SEG1                  0
376 #define DBGU_IO0_BASE__INST3_SEG2                  0
377 #define DBGU_IO0_BASE__INST3_SEG3                  0
378 #define DBGU_IO0_BASE__INST3_SEG4                  0
379 
380 #define DBGU_IO0_BASE__INST4_SEG0                  0
381 #define DBGU_IO0_BASE__INST4_SEG1                  0
382 #define DBGU_IO0_BASE__INST4_SEG2                  0
383 #define DBGU_IO0_BASE__INST4_SEG3                  0
384 #define DBGU_IO0_BASE__INST4_SEG4                  0
385 
386 #define DBGU_IO0_BASE__INST5_SEG0                  0
387 #define DBGU_IO0_BASE__INST5_SEG1                  0
388 #define DBGU_IO0_BASE__INST5_SEG2                  0
389 #define DBGU_IO0_BASE__INST5_SEG3                  0
390 #define DBGU_IO0_BASE__INST5_SEG4                  0
391 
392 #define DBGU_IO0_BASE__INST6_SEG0                  0
393 #define DBGU_IO0_BASE__INST6_SEG1                  0
394 #define DBGU_IO0_BASE__INST6_SEG2                  0
395 #define DBGU_IO0_BASE__INST6_SEG3                  0
396 #define DBGU_IO0_BASE__INST6_SEG4                  0
397 
398 #define DF_BASE__INST0_SEG0                        0x00007000
399 #define DF_BASE__INST0_SEG1                        0x0240B800
400 #define DF_BASE__INST0_SEG2                        0
401 #define DF_BASE__INST0_SEG3                        0
402 #define DF_BASE__INST0_SEG4                        0
403 
404 #define DF_BASE__INST1_SEG0                        0
405 #define DF_BASE__INST1_SEG1                        0
406 #define DF_BASE__INST1_SEG2                        0
407 #define DF_BASE__INST1_SEG3                        0
408 #define DF_BASE__INST1_SEG4                        0
409 
410 #define DF_BASE__INST2_SEG0                        0
411 #define DF_BASE__INST2_SEG1                        0
412 #define DF_BASE__INST2_SEG2                        0
413 #define DF_BASE__INST2_SEG3                        0
414 #define DF_BASE__INST2_SEG4                        0
415 
416 #define DF_BASE__INST3_SEG0                        0
417 #define DF_BASE__INST3_SEG1                        0
418 #define DF_BASE__INST3_SEG2                        0
419 #define DF_BASE__INST3_SEG3                        0
420 #define DF_BASE__INST3_SEG4                        0
421 
422 #define DF_BASE__INST4_SEG0                        0
423 #define DF_BASE__INST4_SEG1                        0
424 #define DF_BASE__INST4_SEG2                        0
425 #define DF_BASE__INST4_SEG3                        0
426 #define DF_BASE__INST4_SEG4                        0
427 
428 #define DF_BASE__INST5_SEG0                        0
429 #define DF_BASE__INST5_SEG1                        0
430 #define DF_BASE__INST5_SEG2                        0
431 #define DF_BASE__INST5_SEG3                        0
432 #define DF_BASE__INST5_SEG4                        0
433 
434 #define DF_BASE__INST6_SEG0                        0
435 #define DF_BASE__INST6_SEG1                        0
436 #define DF_BASE__INST6_SEG2                        0
437 #define DF_BASE__INST6_SEG3                        0
438 #define DF_BASE__INST6_SEG4                        0
439 
440 #define DIO_BASE__INST0_SEG0                       0x02404000
441 #define DIO_BASE__INST0_SEG1                       0
442 #define DIO_BASE__INST0_SEG2                       0
443 #define DIO_BASE__INST0_SEG3                       0
444 #define DIO_BASE__INST0_SEG4                       0
445 
446 #define DIO_BASE__INST1_SEG0                       0
447 #define DIO_BASE__INST1_SEG1                       0
448 #define DIO_BASE__INST1_SEG2                       0
449 #define DIO_BASE__INST1_SEG3                       0
450 #define DIO_BASE__INST1_SEG4                       0
451 
452 #define DIO_BASE__INST2_SEG0                       0
453 #define DIO_BASE__INST2_SEG1                       0
454 #define DIO_BASE__INST2_SEG2                       0
455 #define DIO_BASE__INST2_SEG3                       0
456 #define DIO_BASE__INST2_SEG4                       0
457 
458 #define DIO_BASE__INST3_SEG0                       0
459 #define DIO_BASE__INST3_SEG1                       0
460 #define DIO_BASE__INST3_SEG2                       0
461 #define DIO_BASE__INST3_SEG3                       0
462 #define DIO_BASE__INST3_SEG4                       0
463 
464 #define DIO_BASE__INST4_SEG0                       0
465 #define DIO_BASE__INST4_SEG1                       0
466 #define DIO_BASE__INST4_SEG2                       0
467 #define DIO_BASE__INST4_SEG3                       0
468 #define DIO_BASE__INST4_SEG4                       0
469 
470 #define DIO_BASE__INST5_SEG0                       0
471 #define DIO_BASE__INST5_SEG1                       0
472 #define DIO_BASE__INST5_SEG2                       0
473 #define DIO_BASE__INST5_SEG3                       0
474 #define DIO_BASE__INST5_SEG4                       0
475 
476 #define DIO_BASE__INST6_SEG0                       0
477 #define DIO_BASE__INST6_SEG1                       0
478 #define DIO_BASE__INST6_SEG2                       0
479 #define DIO_BASE__INST6_SEG3                       0
480 #define DIO_BASE__INST6_SEG4                       0
481 
482 #define DMU_BASE__INST0_SEG0                       0x00000012
483 #define DMU_BASE__INST0_SEG1                       0x000000C0
484 #define DMU_BASE__INST0_SEG2                       0x000034C0
485 #define DMU_BASE__INST0_SEG3                       0x00009000
486 #define DMU_BASE__INST0_SEG4                       0x02403C00
487 
488 #define DMU_BASE__INST1_SEG0                       0
489 #define DMU_BASE__INST1_SEG1                       0
490 #define DMU_BASE__INST1_SEG2                       0
491 #define DMU_BASE__INST1_SEG3                       0
492 #define DMU_BASE__INST1_SEG4                       0
493 
494 #define DMU_BASE__INST2_SEG0                       0
495 #define DMU_BASE__INST2_SEG1                       0
496 #define DMU_BASE__INST2_SEG2                       0
497 #define DMU_BASE__INST2_SEG3                       0
498 #define DMU_BASE__INST2_SEG4                       0
499 
500 #define DMU_BASE__INST3_SEG0                       0
501 #define DMU_BASE__INST3_SEG1                       0
502 #define DMU_BASE__INST3_SEG2                       0
503 #define DMU_BASE__INST3_SEG3                       0
504 #define DMU_BASE__INST3_SEG4                       0
505 
506 #define DMU_BASE__INST4_SEG0                       0
507 #define DMU_BASE__INST4_SEG1                       0
508 #define DMU_BASE__INST4_SEG2                       0
509 #define DMU_BASE__INST4_SEG3                       0
510 #define DMU_BASE__INST4_SEG4                       0
511 
512 #define DMU_BASE__INST5_SEG0                       0
513 #define DMU_BASE__INST5_SEG1                       0
514 #define DMU_BASE__INST5_SEG2                       0
515 #define DMU_BASE__INST5_SEG3                       0
516 #define DMU_BASE__INST5_SEG4                       0
517 
518 #define DMU_BASE__INST6_SEG0                       0
519 #define DMU_BASE__INST6_SEG1                       0
520 #define DMU_BASE__INST6_SEG2                       0
521 #define DMU_BASE__INST6_SEG3                       0
522 #define DMU_BASE__INST6_SEG4                       0
523 
524 #define DPCS_BASE__INST0_SEG0                      0x00000012
525 #define DPCS_BASE__INST0_SEG1                      0x000000C0
526 #define DPCS_BASE__INST0_SEG2                      0x000034C0
527 #define DPCS_BASE__INST0_SEG3                      0x00009000
528 #define DPCS_BASE__INST0_SEG4                      0x02403C00
529 
530 #define DPCS_BASE__INST1_SEG0                      0
531 #define DPCS_BASE__INST1_SEG1                      0
532 #define DPCS_BASE__INST1_SEG2                      0
533 #define DPCS_BASE__INST1_SEG3                      0
534 #define DPCS_BASE__INST1_SEG4                      0
535 
536 #define DPCS_BASE__INST2_SEG0                      0
537 #define DPCS_BASE__INST2_SEG1                      0
538 #define DPCS_BASE__INST2_SEG2                      0
539 #define DPCS_BASE__INST2_SEG3                      0
540 #define DPCS_BASE__INST2_SEG4                      0
541 
542 #define DPCS_BASE__INST3_SEG0                      0
543 #define DPCS_BASE__INST3_SEG1                      0
544 #define DPCS_BASE__INST3_SEG2                      0
545 #define DPCS_BASE__INST3_SEG3                      0
546 #define DPCS_BASE__INST3_SEG4                      0
547 
548 #define DPCS_BASE__INST4_SEG0                      0
549 #define DPCS_BASE__INST4_SEG1                      0
550 #define DPCS_BASE__INST4_SEG2                      0
551 #define DPCS_BASE__INST4_SEG3                      0
552 #define DPCS_BASE__INST4_SEG4                      0
553 
554 #define DPCS_BASE__INST5_SEG0                      0
555 #define DPCS_BASE__INST5_SEG1                      0
556 #define DPCS_BASE__INST5_SEG2                      0
557 #define DPCS_BASE__INST5_SEG3                      0
558 #define DPCS_BASE__INST5_SEG4                      0
559 
560 #define DPCS_BASE__INST6_SEG0                      0
561 #define DPCS_BASE__INST6_SEG1                      0
562 #define DPCS_BASE__INST6_SEG2                      0
563 #define DPCS_BASE__INST6_SEG3                      0
564 #define DPCS_BASE__INST6_SEG4                      0
565 
566 #define FUSE_BASE__INST0_SEG0                      0x00017400
567 #define FUSE_BASE__INST0_SEG1                      0x02401400
568 #define FUSE_BASE__INST0_SEG2                      0
569 #define FUSE_BASE__INST0_SEG3                      0
570 #define FUSE_BASE__INST0_SEG4                      0
571 
572 #define FUSE_BASE__INST1_SEG0                      0
573 #define FUSE_BASE__INST1_SEG1                      0
574 #define FUSE_BASE__INST1_SEG2                      0
575 #define FUSE_BASE__INST1_SEG3                      0
576 #define FUSE_BASE__INST1_SEG4                      0
577 
578 #define FUSE_BASE__INST2_SEG0                      0
579 #define FUSE_BASE__INST2_SEG1                      0
580 #define FUSE_BASE__INST2_SEG2                      0
581 #define FUSE_BASE__INST2_SEG3                      0
582 #define FUSE_BASE__INST2_SEG4                      0
583 
584 #define FUSE_BASE__INST3_SEG0                      0
585 #define FUSE_BASE__INST3_SEG1                      0
586 #define FUSE_BASE__INST3_SEG2                      0
587 #define FUSE_BASE__INST3_SEG3                      0
588 #define FUSE_BASE__INST3_SEG4                      0
589 
590 #define FUSE_BASE__INST4_SEG0                      0
591 #define FUSE_BASE__INST4_SEG1                      0
592 #define FUSE_BASE__INST4_SEG2                      0
593 #define FUSE_BASE__INST4_SEG3                      0
594 #define FUSE_BASE__INST4_SEG4                      0
595 
596 #define FUSE_BASE__INST5_SEG0                      0
597 #define FUSE_BASE__INST5_SEG1                      0
598 #define FUSE_BASE__INST5_SEG2                      0
599 #define FUSE_BASE__INST5_SEG3                      0
600 #define FUSE_BASE__INST5_SEG4                      0
601 
602 #define FUSE_BASE__INST6_SEG0                      0
603 #define FUSE_BASE__INST6_SEG1                      0
604 #define FUSE_BASE__INST6_SEG2                      0
605 #define FUSE_BASE__INST6_SEG3                      0
606 #define FUSE_BASE__INST6_SEG4                      0
607 
608 #define GC_BASE__INST0_SEG0                        0x00002000
609 #define GC_BASE__INST0_SEG1                        0x0000A000
610 #define GC_BASE__INST0_SEG2                        0x02402C00
611 #define GC_BASE__INST0_SEG3                        0
612 #define GC_BASE__INST0_SEG4                        0
613 
614 #define GC_BASE__INST1_SEG0                        0
615 #define GC_BASE__INST1_SEG1                        0
616 #define GC_BASE__INST1_SEG2                        0
617 #define GC_BASE__INST1_SEG3                        0
618 #define GC_BASE__INST1_SEG4                        0
619 
620 #define GC_BASE__INST2_SEG0                        0
621 #define GC_BASE__INST2_SEG1                        0
622 #define GC_BASE__INST2_SEG2                        0
623 #define GC_BASE__INST2_SEG3                        0
624 #define GC_BASE__INST2_SEG4                        0
625 
626 #define GC_BASE__INST3_SEG0                        0
627 #define GC_BASE__INST3_SEG1                        0
628 #define GC_BASE__INST3_SEG2                        0
629 #define GC_BASE__INST3_SEG3                        0
630 #define GC_BASE__INST3_SEG4                        0
631 
632 #define GC_BASE__INST4_SEG0                        0
633 #define GC_BASE__INST4_SEG1                        0
634 #define GC_BASE__INST4_SEG2                        0
635 #define GC_BASE__INST4_SEG3                        0
636 #define GC_BASE__INST4_SEG4                        0
637 
638 #define GC_BASE__INST5_SEG0                        0
639 #define GC_BASE__INST5_SEG1                        0
640 #define GC_BASE__INST5_SEG2                        0
641 #define GC_BASE__INST5_SEG3                        0
642 #define GC_BASE__INST5_SEG4                        0
643 
644 #define GC_BASE__INST6_SEG0                        0
645 #define GC_BASE__INST6_SEG1                        0
646 #define GC_BASE__INST6_SEG2                        0
647 #define GC_BASE__INST6_SEG3                        0
648 #define GC_BASE__INST6_SEG4                        0
649 
650 #define HDA_BASE__INST0_SEG0                       0x02404800
651 #define HDA_BASE__INST0_SEG1                       0x004C0000
652 #define HDA_BASE__INST0_SEG2                       0
653 #define HDA_BASE__INST0_SEG3                       0
654 #define HDA_BASE__INST0_SEG4                       0
655 
656 #define HDA_BASE__INST1_SEG0                       0
657 #define HDA_BASE__INST1_SEG1                       0
658 #define HDA_BASE__INST1_SEG2                       0
659 #define HDA_BASE__INST1_SEG3                       0
660 #define HDA_BASE__INST1_SEG4                       0
661 
662 #define HDA_BASE__INST2_SEG0                       0
663 #define HDA_BASE__INST2_SEG1                       0
664 #define HDA_BASE__INST2_SEG2                       0
665 #define HDA_BASE__INST2_SEG3                       0
666 #define HDA_BASE__INST2_SEG4                       0
667 
668 #define HDA_BASE__INST3_SEG0                       0
669 #define HDA_BASE__INST3_SEG1                       0
670 #define HDA_BASE__INST3_SEG2                       0
671 #define HDA_BASE__INST3_SEG3                       0
672 #define HDA_BASE__INST3_SEG4                       0
673 
674 #define HDA_BASE__INST4_SEG0                       0
675 #define HDA_BASE__INST4_SEG1                       0
676 #define HDA_BASE__INST4_SEG2                       0
677 #define HDA_BASE__INST4_SEG3                       0
678 #define HDA_BASE__INST4_SEG4                       0
679 
680 #define HDA_BASE__INST5_SEG0                       0
681 #define HDA_BASE__INST5_SEG1                       0
682 #define HDA_BASE__INST5_SEG2                       0
683 #define HDA_BASE__INST5_SEG3                       0
684 #define HDA_BASE__INST5_SEG4                       0
685 
686 #define HDA_BASE__INST6_SEG0                       0
687 #define HDA_BASE__INST6_SEG1                       0
688 #define HDA_BASE__INST6_SEG2                       0
689 #define HDA_BASE__INST6_SEG3                       0
690 #define HDA_BASE__INST6_SEG4                       0
691 
692 #define HDP_BASE__INST0_SEG0                       0x00000F20
693 #define HDP_BASE__INST0_SEG1                       0x0240A400
694 #define HDP_BASE__INST0_SEG2                       0
695 #define HDP_BASE__INST0_SEG3                       0
696 #define HDP_BASE__INST0_SEG4                       0
697 
698 #define HDP_BASE__INST1_SEG0                       0
699 #define HDP_BASE__INST1_SEG1                       0
700 #define HDP_BASE__INST1_SEG2                       0
701 #define HDP_BASE__INST1_SEG3                       0
702 #define HDP_BASE__INST1_SEG4                       0
703 
704 #define HDP_BASE__INST2_SEG0                       0
705 #define HDP_BASE__INST2_SEG1                       0
706 #define HDP_BASE__INST2_SEG2                       0
707 #define HDP_BASE__INST2_SEG3                       0
708 #define HDP_BASE__INST2_SEG4                       0
709 
710 #define HDP_BASE__INST3_SEG0                       0
711 #define HDP_BASE__INST3_SEG1                       0
712 #define HDP_BASE__INST3_SEG2                       0
713 #define HDP_BASE__INST3_SEG3                       0
714 #define HDP_BASE__INST3_SEG4                       0
715 
716 #define HDP_BASE__INST4_SEG0                       0
717 #define HDP_BASE__INST4_SEG1                       0
718 #define HDP_BASE__INST4_SEG2                       0
719 #define HDP_BASE__INST4_SEG3                       0
720 #define HDP_BASE__INST4_SEG4                       0
721 
722 #define HDP_BASE__INST5_SEG0                       0
723 #define HDP_BASE__INST5_SEG1                       0
724 #define HDP_BASE__INST5_SEG2                       0
725 #define HDP_BASE__INST5_SEG3                       0
726 #define HDP_BASE__INST5_SEG4                       0
727 
728 #define HDP_BASE__INST6_SEG0                       0
729 #define HDP_BASE__INST6_SEG1                       0
730 #define HDP_BASE__INST6_SEG2                       0
731 #define HDP_BASE__INST6_SEG3                       0
732 #define HDP_BASE__INST6_SEG4                       0
733 
734 #define IOHC0_BASE__INST0_SEG0                     0x00010000
735 #define IOHC0_BASE__INST0_SEG1                     0x02406000
736 #define IOHC0_BASE__INST0_SEG2                     0x04EC0000
737 #define IOHC0_BASE__INST0_SEG3                     0
738 #define IOHC0_BASE__INST0_SEG4                     0
739 
740 #define IOHC0_BASE__INST1_SEG0                     0
741 #define IOHC0_BASE__INST1_SEG1                     0
742 #define IOHC0_BASE__INST1_SEG2                     0
743 #define IOHC0_BASE__INST1_SEG3                     0
744 #define IOHC0_BASE__INST1_SEG4                     0
745 
746 #define IOHC0_BASE__INST2_SEG0                     0
747 #define IOHC0_BASE__INST2_SEG1                     0
748 #define IOHC0_BASE__INST2_SEG2                     0
749 #define IOHC0_BASE__INST2_SEG3                     0
750 #define IOHC0_BASE__INST2_SEG4                     0
751 
752 #define IOHC0_BASE__INST3_SEG0                     0
753 #define IOHC0_BASE__INST3_SEG1                     0
754 #define IOHC0_BASE__INST3_SEG2                     0
755 #define IOHC0_BASE__INST3_SEG3                     0
756 #define IOHC0_BASE__INST3_SEG4                     0
757 
758 #define IOHC0_BASE__INST4_SEG0                     0
759 #define IOHC0_BASE__INST4_SEG1                     0
760 #define IOHC0_BASE__INST4_SEG2                     0
761 #define IOHC0_BASE__INST4_SEG3                     0
762 #define IOHC0_BASE__INST4_SEG4                     0
763 
764 #define IOHC0_BASE__INST5_SEG0                     0
765 #define IOHC0_BASE__INST5_SEG1                     0
766 #define IOHC0_BASE__INST5_SEG2                     0
767 #define IOHC0_BASE__INST5_SEG3                     0
768 #define IOHC0_BASE__INST5_SEG4                     0
769 
770 #define IOHC0_BASE__INST6_SEG0                     0
771 #define IOHC0_BASE__INST6_SEG1                     0
772 #define IOHC0_BASE__INST6_SEG2                     0
773 #define IOHC0_BASE__INST6_SEG3                     0
774 #define IOHC0_BASE__INST6_SEG4                     0
775 
776 #define ISP_BASE__INST0_SEG0                       0x00018000
777 #define ISP_BASE__INST0_SEG1                       0x0240B000
778 #define ISP_BASE__INST0_SEG2                       0
779 #define ISP_BASE__INST0_SEG3                       0
780 #define ISP_BASE__INST0_SEG4                       0
781 
782 #define ISP_BASE__INST1_SEG0                       0
783 #define ISP_BASE__INST1_SEG1                       0
784 #define ISP_BASE__INST1_SEG2                       0
785 #define ISP_BASE__INST1_SEG3                       0
786 #define ISP_BASE__INST1_SEG4                       0
787 
788 #define ISP_BASE__INST2_SEG0                       0
789 #define ISP_BASE__INST2_SEG1                       0
790 #define ISP_BASE__INST2_SEG2                       0
791 #define ISP_BASE__INST2_SEG3                       0
792 #define ISP_BASE__INST2_SEG4                       0
793 
794 #define ISP_BASE__INST3_SEG0                       0
795 #define ISP_BASE__INST3_SEG1                       0
796 #define ISP_BASE__INST3_SEG2                       0
797 #define ISP_BASE__INST3_SEG3                       0
798 #define ISP_BASE__INST3_SEG4                       0
799 
800 #define ISP_BASE__INST4_SEG0                       0
801 #define ISP_BASE__INST4_SEG1                       0
802 #define ISP_BASE__INST4_SEG2                       0
803 #define ISP_BASE__INST4_SEG3                       0
804 #define ISP_BASE__INST4_SEG4                       0
805 
806 #define ISP_BASE__INST5_SEG0                       0
807 #define ISP_BASE__INST5_SEG1                       0
808 #define ISP_BASE__INST5_SEG2                       0
809 #define ISP_BASE__INST5_SEG3                       0
810 #define ISP_BASE__INST5_SEG4                       0
811 
812 #define ISP_BASE__INST6_SEG0                       0
813 #define ISP_BASE__INST6_SEG1                       0
814 #define ISP_BASE__INST6_SEG2                       0
815 #define ISP_BASE__INST6_SEG3                       0
816 #define ISP_BASE__INST6_SEG4                       0
817 
818 #define L2IMU0_BASE__INST0_SEG0                    0x00007DC0
819 #define L2IMU0_BASE__INST0_SEG1                    0x02407000
820 #define L2IMU0_BASE__INST0_SEG2                    0x00900000
821 #define L2IMU0_BASE__INST0_SEG3                    0x04FC0000
822 #define L2IMU0_BASE__INST0_SEG4                    0x055C0000
823 
824 #define L2IMU0_BASE__INST1_SEG0                    0
825 #define L2IMU0_BASE__INST1_SEG1                    0
826 #define L2IMU0_BASE__INST1_SEG2                    0
827 #define L2IMU0_BASE__INST1_SEG3                    0
828 #define L2IMU0_BASE__INST1_SEG4                    0
829 
830 #define L2IMU0_BASE__INST2_SEG0                    0
831 #define L2IMU0_BASE__INST2_SEG1                    0
832 #define L2IMU0_BASE__INST2_SEG2                    0
833 #define L2IMU0_BASE__INST2_SEG3                    0
834 #define L2IMU0_BASE__INST2_SEG4                    0
835 
836 #define L2IMU0_BASE__INST3_SEG0                    0
837 #define L2IMU0_BASE__INST3_SEG1                    0
838 #define L2IMU0_BASE__INST3_SEG2                    0
839 #define L2IMU0_BASE__INST3_SEG3                    0
840 #define L2IMU0_BASE__INST3_SEG4                    0
841 
842 #define L2IMU0_BASE__INST4_SEG0                    0
843 #define L2IMU0_BASE__INST4_SEG1                    0
844 #define L2IMU0_BASE__INST4_SEG2                    0
845 #define L2IMU0_BASE__INST4_SEG3                    0
846 #define L2IMU0_BASE__INST4_SEG4                    0
847 
848 #define L2IMU0_BASE__INST5_SEG0                    0
849 #define L2IMU0_BASE__INST5_SEG1                    0
850 #define L2IMU0_BASE__INST5_SEG2                    0
851 #define L2IMU0_BASE__INST5_SEG3                    0
852 #define L2IMU0_BASE__INST5_SEG4                    0
853 
854 #define L2IMU0_BASE__INST6_SEG0                    0
855 #define L2IMU0_BASE__INST6_SEG1                    0
856 #define L2IMU0_BASE__INST6_SEG2                    0
857 #define L2IMU0_BASE__INST6_SEG3                    0
858 #define L2IMU0_BASE__INST6_SEG4                    0
859 
860 #define MMHUB_BASE__INST0_SEG0                     0x0001A000
861 #define MMHUB_BASE__INST0_SEG1                     0x02408800
862 #define MMHUB_BASE__INST0_SEG2                     0
863 #define MMHUB_BASE__INST0_SEG3                     0
864 #define MMHUB_BASE__INST0_SEG4                     0
865 
866 #define MMHUB_BASE__INST1_SEG0                     0
867 #define MMHUB_BASE__INST1_SEG1                     0
868 #define MMHUB_BASE__INST1_SEG2                     0
869 #define MMHUB_BASE__INST1_SEG3                     0
870 #define MMHUB_BASE__INST1_SEG4                     0
871 
872 #define MMHUB_BASE__INST2_SEG0                     0
873 #define MMHUB_BASE__INST2_SEG1                     0
874 #define MMHUB_BASE__INST2_SEG2                     0
875 #define MMHUB_BASE__INST2_SEG3                     0
876 #define MMHUB_BASE__INST2_SEG4                     0
877 
878 #define MMHUB_BASE__INST3_SEG0                     0
879 #define MMHUB_BASE__INST3_SEG1                     0
880 #define MMHUB_BASE__INST3_SEG2                     0
881 #define MMHUB_BASE__INST3_SEG3                     0
882 #define MMHUB_BASE__INST3_SEG4                     0
883 
884 #define MMHUB_BASE__INST4_SEG0                     0
885 #define MMHUB_BASE__INST4_SEG1                     0
886 #define MMHUB_BASE__INST4_SEG2                     0
887 #define MMHUB_BASE__INST4_SEG3                     0
888 #define MMHUB_BASE__INST4_SEG4                     0
889 
890 #define MMHUB_BASE__INST5_SEG0                     0
891 #define MMHUB_BASE__INST5_SEG1                     0
892 #define MMHUB_BASE__INST5_SEG2                     0
893 #define MMHUB_BASE__INST5_SEG3                     0
894 #define MMHUB_BASE__INST5_SEG4                     0
895 
896 #define MMHUB_BASE__INST6_SEG0                     0
897 #define MMHUB_BASE__INST6_SEG1                     0
898 #define MMHUB_BASE__INST6_SEG2                     0
899 #define MMHUB_BASE__INST6_SEG3                     0
900 #define MMHUB_BASE__INST6_SEG4                     0
901 
902 #define MP0_BASE__INST0_SEG0                       0x00016000
903 #define MP0_BASE__INST0_SEG1                       0x0243FC00
904 #define MP0_BASE__INST0_SEG2                       0x00DC0000
905 #define MP0_BASE__INST0_SEG3                       0x00E00000
906 #define MP0_BASE__INST0_SEG4                       0x00E40000
907 
908 #define MP0_BASE__INST1_SEG0                       0
909 #define MP0_BASE__INST1_SEG1                       0
910 #define MP0_BASE__INST1_SEG2                       0
911 #define MP0_BASE__INST1_SEG3                       0
912 #define MP0_BASE__INST1_SEG4                       0
913 
914 #define MP0_BASE__INST2_SEG0                       0
915 #define MP0_BASE__INST2_SEG1                       0
916 #define MP0_BASE__INST2_SEG2                       0
917 #define MP0_BASE__INST2_SEG3                       0
918 #define MP0_BASE__INST2_SEG4                       0
919 
920 #define MP0_BASE__INST3_SEG0                       0
921 #define MP0_BASE__INST3_SEG1                       0
922 #define MP0_BASE__INST3_SEG2                       0
923 #define MP0_BASE__INST3_SEG3                       0
924 #define MP0_BASE__INST3_SEG4                       0
925 
926 #define MP0_BASE__INST4_SEG0                       0
927 #define MP0_BASE__INST4_SEG1                       0
928 #define MP0_BASE__INST4_SEG2                       0
929 #define MP0_BASE__INST4_SEG3                       0
930 #define MP0_BASE__INST4_SEG4                       0
931 
932 #define MP0_BASE__INST5_SEG0                       0
933 #define MP0_BASE__INST5_SEG1                       0
934 #define MP0_BASE__INST5_SEG2                       0
935 #define MP0_BASE__INST5_SEG3                       0
936 #define MP0_BASE__INST5_SEG4                       0
937 
938 #define MP0_BASE__INST6_SEG0                       0
939 #define MP0_BASE__INST6_SEG1                       0
940 #define MP0_BASE__INST6_SEG2                       0
941 #define MP0_BASE__INST6_SEG3                       0
942 #define MP0_BASE__INST6_SEG4                       0
943 
944 #define MP1_BASE__INST0_SEG0                       0x00016200
945 #define MP1_BASE__INST0_SEG1                       0x02400400
946 #define MP1_BASE__INST0_SEG2                       0x00E80000
947 #define MP1_BASE__INST0_SEG3                       0x00EC0000
948 #define MP1_BASE__INST0_SEG4                       0x00F00000
949 
950 #define MP1_BASE__INST1_SEG0                       0
951 #define MP1_BASE__INST1_SEG1                       0
952 #define MP1_BASE__INST1_SEG2                       0
953 #define MP1_BASE__INST1_SEG3                       0
954 #define MP1_BASE__INST1_SEG4                       0
955 
956 #define MP1_BASE__INST2_SEG0                       0
957 #define MP1_BASE__INST2_SEG1                       0
958 #define MP1_BASE__INST2_SEG2                       0
959 #define MP1_BASE__INST2_SEG3                       0
960 #define MP1_BASE__INST2_SEG4                       0
961 
962 #define MP1_BASE__INST3_SEG0                       0
963 #define MP1_BASE__INST3_SEG1                       0
964 #define MP1_BASE__INST3_SEG2                       0
965 #define MP1_BASE__INST3_SEG3                       0
966 #define MP1_BASE__INST3_SEG4                       0
967 
968 #define MP1_BASE__INST4_SEG0                       0
969 #define MP1_BASE__INST4_SEG1                       0
970 #define MP1_BASE__INST4_SEG2                       0
971 #define MP1_BASE__INST4_SEG3                       0
972 #define MP1_BASE__INST4_SEG4                       0
973 
974 #define MP1_BASE__INST5_SEG0                       0
975 #define MP1_BASE__INST5_SEG1                       0
976 #define MP1_BASE__INST5_SEG2                       0
977 #define MP1_BASE__INST5_SEG3                       0
978 #define MP1_BASE__INST5_SEG4                       0
979 
980 #define MP1_BASE__INST6_SEG0                       0
981 #define MP1_BASE__INST6_SEG1                       0
982 #define MP1_BASE__INST6_SEG2                       0
983 #define MP1_BASE__INST6_SEG3                       0
984 #define MP1_BASE__INST6_SEG4                       0
985 
986 #define NBIF0_BASE__INST0_SEG0                     0x00000000
987 #define NBIF0_BASE__INST0_SEG1                     0x00000014
988 #define NBIF0_BASE__INST0_SEG2                     0x00000D20
989 #define NBIF0_BASE__INST0_SEG3                     0x00010400
990 #define NBIF0_BASE__INST0_SEG4                     0x0241B000
991 
992 #define NBIF0_BASE__INST1_SEG0                     0
993 #define NBIF0_BASE__INST1_SEG1                     0
994 #define NBIF0_BASE__INST1_SEG2                     0
995 #define NBIF0_BASE__INST1_SEG3                     0
996 #define NBIF0_BASE__INST1_SEG4                     0
997 
998 #define NBIF0_BASE__INST2_SEG0                     0
999 #define NBIF0_BASE__INST2_SEG1                     0
1000 #define NBIF0_BASE__INST2_SEG2                     0
1001 #define NBIF0_BASE__INST2_SEG3                     0
1002 #define NBIF0_BASE__INST2_SEG4                     0
1003 
1004 #define NBIF0_BASE__INST3_SEG0                     0
1005 #define NBIF0_BASE__INST3_SEG1                     0
1006 #define NBIF0_BASE__INST3_SEG2                     0
1007 #define NBIF0_BASE__INST3_SEG3                     0
1008 #define NBIF0_BASE__INST3_SEG4                     0
1009 
1010 #define NBIF0_BASE__INST4_SEG0                     0
1011 #define NBIF0_BASE__INST4_SEG1                     0
1012 #define NBIF0_BASE__INST4_SEG2                     0
1013 #define NBIF0_BASE__INST4_SEG3                     0
1014 #define NBIF0_BASE__INST4_SEG4                     0
1015 
1016 #define NBIF0_BASE__INST5_SEG0                     0
1017 #define NBIF0_BASE__INST5_SEG1                     0
1018 #define NBIF0_BASE__INST5_SEG2                     0
1019 #define NBIF0_BASE__INST5_SEG3                     0
1020 #define NBIF0_BASE__INST5_SEG4                     0
1021 
1022 #define NBIF0_BASE__INST6_SEG0                     0
1023 #define NBIF0_BASE__INST6_SEG1                     0
1024 #define NBIF0_BASE__INST6_SEG2                     0
1025 #define NBIF0_BASE__INST6_SEG3                     0
1026 #define NBIF0_BASE__INST6_SEG4                     0
1027 
1028 #define OSSSYS_BASE__INST0_SEG0                    0x000010A0
1029 #define OSSSYS_BASE__INST0_SEG1                    0x0240A000
1030 #define OSSSYS_BASE__INST0_SEG2                    0
1031 #define OSSSYS_BASE__INST0_SEG3                    0
1032 #define OSSSYS_BASE__INST0_SEG4                    0
1033 
1034 #define OSSSYS_BASE__INST1_SEG0                    0
1035 #define OSSSYS_BASE__INST1_SEG1                    0
1036 #define OSSSYS_BASE__INST1_SEG2                    0
1037 #define OSSSYS_BASE__INST1_SEG3                    0
1038 #define OSSSYS_BASE__INST1_SEG4                    0
1039 
1040 #define OSSSYS_BASE__INST2_SEG0                    0
1041 #define OSSSYS_BASE__INST2_SEG1                    0
1042 #define OSSSYS_BASE__INST2_SEG2                    0
1043 #define OSSSYS_BASE__INST2_SEG3                    0
1044 #define OSSSYS_BASE__INST2_SEG4                    0
1045 
1046 #define OSSSYS_BASE__INST3_SEG0                    0
1047 #define OSSSYS_BASE__INST3_SEG1                    0
1048 #define OSSSYS_BASE__INST3_SEG2                    0
1049 #define OSSSYS_BASE__INST3_SEG3                    0
1050 #define OSSSYS_BASE__INST3_SEG4                    0
1051 
1052 #define OSSSYS_BASE__INST4_SEG0                    0
1053 #define OSSSYS_BASE__INST4_SEG1                    0
1054 #define OSSSYS_BASE__INST4_SEG2                    0
1055 #define OSSSYS_BASE__INST4_SEG3                    0
1056 #define OSSSYS_BASE__INST4_SEG4                    0
1057 
1058 #define OSSSYS_BASE__INST5_SEG0                    0
1059 #define OSSSYS_BASE__INST5_SEG1                    0
1060 #define OSSSYS_BASE__INST5_SEG2                    0
1061 #define OSSSYS_BASE__INST5_SEG3                    0
1062 #define OSSSYS_BASE__INST5_SEG4                    0
1063 
1064 #define OSSSYS_BASE__INST6_SEG0                    0
1065 #define OSSSYS_BASE__INST6_SEG1                    0
1066 #define OSSSYS_BASE__INST6_SEG2                    0
1067 #define OSSSYS_BASE__INST6_SEG3                    0
1068 #define OSSSYS_BASE__INST6_SEG4                    0
1069 
1070 #define PCIE0_BASE__INST0_SEG0                     0x02411800
1071 #define PCIE0_BASE__INST0_SEG1                     0x04440000
1072 #define PCIE0_BASE__INST0_SEG2                     0
1073 #define PCIE0_BASE__INST0_SEG3                     0
1074 #define PCIE0_BASE__INST0_SEG4                     0
1075 
1076 #define PCIE0_BASE__INST1_SEG0                     0
1077 #define PCIE0_BASE__INST1_SEG1                     0
1078 #define PCIE0_BASE__INST1_SEG2                     0
1079 #define PCIE0_BASE__INST1_SEG3                     0
1080 #define PCIE0_BASE__INST1_SEG4                     0
1081 
1082 #define PCIE0_BASE__INST2_SEG0                     0
1083 #define PCIE0_BASE__INST2_SEG1                     0
1084 #define PCIE0_BASE__INST2_SEG2                     0
1085 #define PCIE0_BASE__INST2_SEG3                     0
1086 #define PCIE0_BASE__INST2_SEG4                     0
1087 
1088 #define PCIE0_BASE__INST3_SEG0                     0
1089 #define PCIE0_BASE__INST3_SEG1                     0
1090 #define PCIE0_BASE__INST3_SEG2                     0
1091 #define PCIE0_BASE__INST3_SEG3                     0
1092 #define PCIE0_BASE__INST3_SEG4                     0
1093 
1094 #define PCIE0_BASE__INST4_SEG0                     0
1095 #define PCIE0_BASE__INST4_SEG1                     0
1096 #define PCIE0_BASE__INST4_SEG2                     0
1097 #define PCIE0_BASE__INST4_SEG3                     0
1098 #define PCIE0_BASE__INST4_SEG4                     0
1099 
1100 #define PCIE0_BASE__INST5_SEG0                     0
1101 #define PCIE0_BASE__INST5_SEG1                     0
1102 #define PCIE0_BASE__INST5_SEG2                     0
1103 #define PCIE0_BASE__INST5_SEG3                     0
1104 #define PCIE0_BASE__INST5_SEG4                     0
1105 
1106 #define PCIE0_BASE__INST6_SEG0                     0
1107 #define PCIE0_BASE__INST6_SEG1                     0
1108 #define PCIE0_BASE__INST6_SEG2                     0
1109 #define PCIE0_BASE__INST6_SEG3                     0
1110 #define PCIE0_BASE__INST6_SEG4                     0
1111 
1112 #define SDMA0_BASE__INST0_SEG0                     0x00001260
1113 #define SDMA0_BASE__INST0_SEG1                     0x0240A800
1114 #define SDMA0_BASE__INST0_SEG2                     0
1115 #define SDMA0_BASE__INST0_SEG3                     0
1116 #define SDMA0_BASE__INST0_SEG4                     0
1117 
1118 #define SDMA0_BASE__INST1_SEG0                     0
1119 #define SDMA0_BASE__INST1_SEG1                     0
1120 #define SDMA0_BASE__INST1_SEG2                     0
1121 #define SDMA0_BASE__INST1_SEG3                     0
1122 #define SDMA0_BASE__INST1_SEG4                     0
1123 
1124 #define SDMA0_BASE__INST2_SEG0                     0
1125 #define SDMA0_BASE__INST2_SEG1                     0
1126 #define SDMA0_BASE__INST2_SEG2                     0
1127 #define SDMA0_BASE__INST2_SEG3                     0
1128 #define SDMA0_BASE__INST2_SEG4                     0
1129 
1130 #define SDMA0_BASE__INST3_SEG0                     0
1131 #define SDMA0_BASE__INST3_SEG1                     0
1132 #define SDMA0_BASE__INST3_SEG2                     0
1133 #define SDMA0_BASE__INST3_SEG3                     0
1134 #define SDMA0_BASE__INST3_SEG4                     0
1135 
1136 #define SDMA0_BASE__INST4_SEG0                     0
1137 #define SDMA0_BASE__INST4_SEG1                     0
1138 #define SDMA0_BASE__INST4_SEG2                     0
1139 #define SDMA0_BASE__INST4_SEG3                     0
1140 #define SDMA0_BASE__INST4_SEG4                     0
1141 
1142 #define SDMA0_BASE__INST5_SEG0                     0
1143 #define SDMA0_BASE__INST5_SEG1                     0
1144 #define SDMA0_BASE__INST5_SEG2                     0
1145 #define SDMA0_BASE__INST5_SEG3                     0
1146 #define SDMA0_BASE__INST5_SEG4                     0
1147 
1148 #define SDMA0_BASE__INST6_SEG0                     0
1149 #define SDMA0_BASE__INST6_SEG1                     0
1150 #define SDMA0_BASE__INST6_SEG2                     0
1151 #define SDMA0_BASE__INST6_SEG3                     0
1152 #define SDMA0_BASE__INST6_SEG4                     0
1153 
1154 #define SMUIO_BASE__INST0_SEG0                     0x00016800
1155 #define SMUIO_BASE__INST0_SEG1                     0x00016A00
1156 #define SMUIO_BASE__INST0_SEG2                     0x02401000
1157 #define SMUIO_BASE__INST0_SEG3                     0x00440000
1158 #define SMUIO_BASE__INST0_SEG4                     0
1159 
1160 #define SMUIO_BASE__INST1_SEG0                     0
1161 #define SMUIO_BASE__INST1_SEG1                     0
1162 #define SMUIO_BASE__INST1_SEG2                     0
1163 #define SMUIO_BASE__INST1_SEG3                     0
1164 #define SMUIO_BASE__INST1_SEG4                     0
1165 
1166 #define SMUIO_BASE__INST2_SEG0                     0
1167 #define SMUIO_BASE__INST2_SEG1                     0
1168 #define SMUIO_BASE__INST2_SEG2                     0
1169 #define SMUIO_BASE__INST2_SEG3                     0
1170 #define SMUIO_BASE__INST2_SEG4                     0
1171 
1172 #define SMUIO_BASE__INST3_SEG0                     0
1173 #define SMUIO_BASE__INST3_SEG1                     0
1174 #define SMUIO_BASE__INST3_SEG2                     0
1175 #define SMUIO_BASE__INST3_SEG3                     0
1176 #define SMUIO_BASE__INST3_SEG4                     0
1177 
1178 #define SMUIO_BASE__INST4_SEG0                     0
1179 #define SMUIO_BASE__INST4_SEG1                     0
1180 #define SMUIO_BASE__INST4_SEG2                     0
1181 #define SMUIO_BASE__INST4_SEG3                     0
1182 #define SMUIO_BASE__INST4_SEG4                     0
1183 
1184 #define SMUIO_BASE__INST5_SEG0                     0
1185 #define SMUIO_BASE__INST5_SEG1                     0
1186 #define SMUIO_BASE__INST5_SEG2                     0
1187 #define SMUIO_BASE__INST5_SEG3                     0
1188 #define SMUIO_BASE__INST5_SEG4                     0
1189 
1190 #define SMUIO_BASE__INST6_SEG0                     0
1191 #define SMUIO_BASE__INST6_SEG1                     0
1192 #define SMUIO_BASE__INST6_SEG2                     0
1193 #define SMUIO_BASE__INST6_SEG3                     0
1194 #define SMUIO_BASE__INST6_SEG4                     0
1195 
1196 #define THM_BASE__INST0_SEG0                       0x00016600
1197 #define THM_BASE__INST0_SEG1                       0x02400C00
1198 #define THM_BASE__INST0_SEG2                       0
1199 #define THM_BASE__INST0_SEG3                       0
1200 #define THM_BASE__INST0_SEG4                       0
1201 
1202 #define THM_BASE__INST1_SEG0                       0
1203 #define THM_BASE__INST1_SEG1                       0
1204 #define THM_BASE__INST1_SEG2                       0
1205 #define THM_BASE__INST1_SEG3                       0
1206 #define THM_BASE__INST1_SEG4                       0
1207 
1208 #define THM_BASE__INST2_SEG0                       0
1209 #define THM_BASE__INST2_SEG1                       0
1210 #define THM_BASE__INST2_SEG2                       0
1211 #define THM_BASE__INST2_SEG3                       0
1212 #define THM_BASE__INST2_SEG4                       0
1213 
1214 #define THM_BASE__INST3_SEG0                       0
1215 #define THM_BASE__INST3_SEG1                       0
1216 #define THM_BASE__INST3_SEG2                       0
1217 #define THM_BASE__INST3_SEG3                       0
1218 #define THM_BASE__INST3_SEG4                       0
1219 
1220 #define THM_BASE__INST4_SEG0                       0
1221 #define THM_BASE__INST4_SEG1                       0
1222 #define THM_BASE__INST4_SEG2                       0
1223 #define THM_BASE__INST4_SEG3                       0
1224 #define THM_BASE__INST4_SEG4                       0
1225 
1226 #define THM_BASE__INST5_SEG0                       0
1227 #define THM_BASE__INST5_SEG1                       0
1228 #define THM_BASE__INST5_SEG2                       0
1229 #define THM_BASE__INST5_SEG3                       0
1230 #define THM_BASE__INST5_SEG4                       0
1231 
1232 #define THM_BASE__INST6_SEG0                       0
1233 #define THM_BASE__INST6_SEG1                       0
1234 #define THM_BASE__INST6_SEG2                       0
1235 #define THM_BASE__INST6_SEG3                       0
1236 #define THM_BASE__INST6_SEG4                       0
1237 
1238 #define UMC_BASE__INST0_SEG0                       0x00014000
1239 #define UMC_BASE__INST0_SEG1                       0x02425800
1240 #define UMC_BASE__INST0_SEG2                       0
1241 #define UMC_BASE__INST0_SEG3                       0
1242 #define UMC_BASE__INST0_SEG4                       0
1243 
1244 #define UMC_BASE__INST1_SEG0                       0x00054000
1245 #define UMC_BASE__INST1_SEG1                       0x02425C00
1246 #define UMC_BASE__INST1_SEG2                       0
1247 #define UMC_BASE__INST1_SEG3                       0
1248 #define UMC_BASE__INST1_SEG4                       0
1249 
1250 #define UMC_BASE__INST2_SEG0                       0
1251 #define UMC_BASE__INST2_SEG1                       0
1252 #define UMC_BASE__INST2_SEG2                       0
1253 #define UMC_BASE__INST2_SEG3                       0
1254 #define UMC_BASE__INST2_SEG4                       0
1255 
1256 #define UMC_BASE__INST3_SEG0                       0
1257 #define UMC_BASE__INST3_SEG1                       0
1258 #define UMC_BASE__INST3_SEG2                       0
1259 #define UMC_BASE__INST3_SEG3                       0
1260 #define UMC_BASE__INST3_SEG4                       0
1261 
1262 #define UMC_BASE__INST4_SEG0                       0
1263 #define UMC_BASE__INST4_SEG1                       0
1264 #define UMC_BASE__INST4_SEG2                       0
1265 #define UMC_BASE__INST4_SEG3                       0
1266 #define UMC_BASE__INST4_SEG4                       0
1267 
1268 #define UMC_BASE__INST5_SEG0                       0
1269 #define UMC_BASE__INST5_SEG1                       0
1270 #define UMC_BASE__INST5_SEG2                       0
1271 #define UMC_BASE__INST5_SEG3                       0
1272 #define UMC_BASE__INST5_SEG4                       0
1273 
1274 #define UMC_BASE__INST6_SEG0                       0
1275 #define UMC_BASE__INST6_SEG1                       0
1276 #define UMC_BASE__INST6_SEG2                       0
1277 #define UMC_BASE__INST6_SEG3                       0
1278 #define UMC_BASE__INST6_SEG4                       0
1279 
1280 #define USB0_BASE__INST0_SEG0                      0x0242A800
1281 #define USB0_BASE__INST0_SEG1                      0x05B00000
1282 #define USB0_BASE__INST0_SEG2                      0
1283 #define USB0_BASE__INST0_SEG3                      0
1284 #define USB0_BASE__INST0_SEG4                      0
1285 
1286 #define USB0_BASE__INST1_SEG0                      0
1287 #define USB0_BASE__INST1_SEG1                      0
1288 #define USB0_BASE__INST1_SEG2                      0
1289 #define USB0_BASE__INST1_SEG3                      0
1290 #define USB0_BASE__INST1_SEG4                      0
1291 
1292 #define USB0_BASE__INST2_SEG0                      0
1293 #define USB0_BASE__INST2_SEG1                      0
1294 #define USB0_BASE__INST2_SEG2                      0
1295 #define USB0_BASE__INST2_SEG3                      0
1296 #define USB0_BASE__INST2_SEG4                      0
1297 
1298 #define USB0_BASE__INST3_SEG0                      0
1299 #define USB0_BASE__INST3_SEG1                      0
1300 #define USB0_BASE__INST3_SEG2                      0
1301 #define USB0_BASE__INST3_SEG3                      0
1302 #define USB0_BASE__INST3_SEG4                      0
1303 
1304 #define USB0_BASE__INST4_SEG0                      0
1305 #define USB0_BASE__INST4_SEG1                      0
1306 #define USB0_BASE__INST4_SEG2                      0
1307 #define USB0_BASE__INST4_SEG3                      0
1308 #define USB0_BASE__INST4_SEG4                      0
1309 
1310 #define USB0_BASE__INST5_SEG0                      0
1311 #define USB0_BASE__INST5_SEG1                      0
1312 #define USB0_BASE__INST5_SEG2                      0
1313 #define USB0_BASE__INST5_SEG3                      0
1314 #define USB0_BASE__INST5_SEG4                      0
1315 
1316 #define USB0_BASE__INST6_SEG0                      0
1317 #define USB0_BASE__INST6_SEG1                      0
1318 #define USB0_BASE__INST6_SEG2                      0
1319 #define USB0_BASE__INST6_SEG3                      0
1320 #define USB0_BASE__INST6_SEG4                      0
1321 
1322 #define UVD0_BASE__INST0_SEG0                      0x00007800
1323 #define UVD0_BASE__INST0_SEG1                      0x00007E00
1324 #define UVD0_BASE__INST0_SEG2                      0x02403000
1325 #define UVD0_BASE__INST0_SEG3                      0
1326 #define UVD0_BASE__INST0_SEG4                      0
1327 
1328 #define UVD0_BASE__INST1_SEG0                      0
1329 #define UVD0_BASE__INST1_SEG1                      0
1330 #define UVD0_BASE__INST1_SEG2                      0
1331 #define UVD0_BASE__INST1_SEG3                      0
1332 #define UVD0_BASE__INST1_SEG4                      0
1333 
1334 #define UVD0_BASE__INST2_SEG0                      0
1335 #define UVD0_BASE__INST2_SEG1                      0
1336 #define UVD0_BASE__INST2_SEG2                      0
1337 #define UVD0_BASE__INST2_SEG3                      0
1338 #define UVD0_BASE__INST2_SEG4                      0
1339 
1340 #define UVD0_BASE__INST3_SEG0                      0
1341 #define UVD0_BASE__INST3_SEG1                      0
1342 #define UVD0_BASE__INST3_SEG2                      0
1343 #define UVD0_BASE__INST3_SEG3                      0
1344 #define UVD0_BASE__INST3_SEG4                      0
1345 
1346 #define UVD0_BASE__INST4_SEG0                      0
1347 #define UVD0_BASE__INST4_SEG1                      0
1348 #define UVD0_BASE__INST4_SEG2                      0
1349 #define UVD0_BASE__INST4_SEG3                      0
1350 #define UVD0_BASE__INST4_SEG4                      0
1351 
1352 #define UVD0_BASE__INST5_SEG0                      0
1353 #define UVD0_BASE__INST5_SEG1                      0
1354 #define UVD0_BASE__INST5_SEG2                      0
1355 #define UVD0_BASE__INST5_SEG3                      0
1356 #define UVD0_BASE__INST5_SEG4                      0
1357 
1358 #define UVD0_BASE__INST6_SEG0                      0
1359 #define UVD0_BASE__INST6_SEG1                      0
1360 #define UVD0_BASE__INST6_SEG2                      0
1361 #define UVD0_BASE__INST6_SEG3                      0
1362 #define UVD0_BASE__INST6_SEG4                      0
1363 
1364 #endif
1365