1 /* 2 * Copyright 2013 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 23 #ifndef _PPTABLE_H 24 #define _PPTABLE_H 25 26 #pragma pack(1) 27 28 typedef struct _ATOM_PPLIB_THERMALCONTROLLER 29 30 { 31 UCHAR ucType; // one of ATOM_PP_THERMALCONTROLLER_* 32 UCHAR ucI2cLine; // as interpreted by DAL I2C 33 UCHAR ucI2cAddress; 34 UCHAR ucFanParameters; // Fan Control Parameters. 35 UCHAR ucFanMinRPM; // Fan Minimum RPM (hundreds) -- for display purposes only. 36 UCHAR ucFanMaxRPM; // Fan Maximum RPM (hundreds) -- for display purposes only. 37 UCHAR ucReserved; // ---- 38 UCHAR ucFlags; // to be defined 39 } ATOM_PPLIB_THERMALCONTROLLER; 40 41 #define ATOM_PP_FANPARAMETERS_TACHOMETER_PULSES_PER_REVOLUTION_MASK 0x0f 42 #define ATOM_PP_FANPARAMETERS_NOFAN 0x80 // No fan is connected to this controller. 43 44 #define ATOM_PP_THERMALCONTROLLER_NONE 0 45 #define ATOM_PP_THERMALCONTROLLER_LM63 1 // Not used by PPLib 46 #define ATOM_PP_THERMALCONTROLLER_ADM1032 2 // Not used by PPLib 47 #define ATOM_PP_THERMALCONTROLLER_ADM1030 3 // Not used by PPLib 48 #define ATOM_PP_THERMALCONTROLLER_MUA6649 4 // Not used by PPLib 49 #define ATOM_PP_THERMALCONTROLLER_LM64 5 50 #define ATOM_PP_THERMALCONTROLLER_F75375 6 // Not used by PPLib 51 #define ATOM_PP_THERMALCONTROLLER_RV6xx 7 52 #define ATOM_PP_THERMALCONTROLLER_RV770 8 53 #define ATOM_PP_THERMALCONTROLLER_ADT7473 9 54 #define ATOM_PP_THERMALCONTROLLER_KONG 10 55 #define ATOM_PP_THERMALCONTROLLER_EXTERNAL_GPIO 11 56 #define ATOM_PP_THERMALCONTROLLER_EVERGREEN 12 57 #define ATOM_PP_THERMALCONTROLLER_EMC2103 13 /* 0x0D */ // Only fan control will be implemented, do NOT show this in PPGen. 58 #define ATOM_PP_THERMALCONTROLLER_SUMO 14 /* 0x0E */ // Sumo type, used internally 59 #define ATOM_PP_THERMALCONTROLLER_NISLANDS 15 60 #define ATOM_PP_THERMALCONTROLLER_SISLANDS 16 61 #define ATOM_PP_THERMALCONTROLLER_LM96163 17 62 #define ATOM_PP_THERMALCONTROLLER_CISLANDS 18 63 #define ATOM_PP_THERMALCONTROLLER_KAVERI 19 64 65 66 // Thermal controller 'combo type' to use an external controller for Fan control and an internal controller for thermal. 67 // We probably should reserve the bit 0x80 for this use. 68 // To keep the number of these types low we should also use the same code for all ASICs (i.e. do not distinguish RV6xx and RV7xx Internal here). 69 // The driver can pick the correct internal controller based on the ASIC. 70 71 #define ATOM_PP_THERMALCONTROLLER_ADT7473_WITH_INTERNAL 0x89 // ADT7473 Fan Control + Internal Thermal Controller 72 #define ATOM_PP_THERMALCONTROLLER_EMC2103_WITH_INTERNAL 0x8D // EMC2103 Fan Control + Internal Thermal Controller 73 74 typedef struct _ATOM_PPLIB_STATE 75 { 76 UCHAR ucNonClockStateIndex; 77 UCHAR ucClockStateIndices[1]; // variable-sized 78 } ATOM_PPLIB_STATE; 79 80 81 typedef struct _ATOM_PPLIB_FANTABLE 82 { 83 UCHAR ucFanTableFormat; // Change this if the table format changes or version changes so that the other fields are not the same. 84 UCHAR ucTHyst; // Temperature hysteresis. Integer. 85 USHORT usTMin; // The temperature, in 0.01 centigrades, below which we just run at a minimal PWM. 86 USHORT usTMed; // The middle temperature where we change slopes. 87 USHORT usTHigh; // The high point above TMed for adjusting the second slope. 88 USHORT usPWMMin; // The minimum PWM value in percent (0.01% increments). 89 USHORT usPWMMed; // The PWM value (in percent) at TMed. 90 USHORT usPWMHigh; // The PWM value at THigh. 91 } ATOM_PPLIB_FANTABLE; 92 93 typedef struct _ATOM_PPLIB_FANTABLE2 94 { 95 ATOM_PPLIB_FANTABLE basicTable; 96 USHORT usTMax; // The max temperature 97 } ATOM_PPLIB_FANTABLE2; 98 99 typedef struct _ATOM_PPLIB_FANTABLE3 100 { 101 ATOM_PPLIB_FANTABLE2 basicTable2; 102 UCHAR ucFanControlMode; 103 USHORT usFanPWMMax; 104 USHORT usFanOutputSensitivity; 105 } ATOM_PPLIB_FANTABLE3; 106 107 typedef struct _ATOM_PPLIB_EXTENDEDHEADER 108 { 109 USHORT usSize; 110 ULONG ulMaxEngineClock; // For Overdrive. 111 ULONG ulMaxMemoryClock; // For Overdrive. 112 // Add extra system parameters here, always adjust size to include all fields. 113 USHORT usVCETableOffset; //points to ATOM_PPLIB_VCE_Table 114 USHORT usUVDTableOffset; //points to ATOM_PPLIB_UVD_Table 115 USHORT usSAMUTableOffset; //points to ATOM_PPLIB_SAMU_Table 116 USHORT usPPMTableOffset; //points to ATOM_PPLIB_PPM_Table 117 USHORT usACPTableOffset; //points to ATOM_PPLIB_ACP_Table 118 /* points to ATOM_PPLIB_POWERTUNE_Table */ 119 USHORT usPowerTuneTableOffset; 120 /* points to ATOM_PPLIB_CLOCK_Voltage_Dependency_Table for sclkVddgfxTable */ 121 USHORT usSclkVddgfxTableOffset; 122 } ATOM_PPLIB_EXTENDEDHEADER; 123 124 //// ATOM_PPLIB_POWERPLAYTABLE::ulPlatformCaps 125 #define ATOM_PP_PLATFORM_CAP_BACKBIAS 1 126 #define ATOM_PP_PLATFORM_CAP_POWERPLAY 2 127 #define ATOM_PP_PLATFORM_CAP_SBIOSPOWERSOURCE 4 128 #define ATOM_PP_PLATFORM_CAP_ASPM_L0s 8 129 #define ATOM_PP_PLATFORM_CAP_ASPM_L1 16 130 #define ATOM_PP_PLATFORM_CAP_HARDWAREDC 32 131 #define ATOM_PP_PLATFORM_CAP_GEMINIPRIMARY 64 132 #define ATOM_PP_PLATFORM_CAP_STEPVDDC 128 133 #define ATOM_PP_PLATFORM_CAP_VOLTAGECONTROL 256 134 #define ATOM_PP_PLATFORM_CAP_SIDEPORTCONTROL 512 135 #define ATOM_PP_PLATFORM_CAP_TURNOFFPLL_ASPML1 1024 136 #define ATOM_PP_PLATFORM_CAP_HTLINKCONTROL 2048 137 #define ATOM_PP_PLATFORM_CAP_MVDDCONTROL 4096 138 #define ATOM_PP_PLATFORM_CAP_GOTO_BOOT_ON_ALERT 0x2000 // Go to boot state on alerts, e.g. on an AC->DC transition. 139 #define ATOM_PP_PLATFORM_CAP_DONT_WAIT_FOR_VBLANK_ON_ALERT 0x4000 // Do NOT wait for VBLANK during an alert (e.g. AC->DC transition). 140 #define ATOM_PP_PLATFORM_CAP_VDDCI_CONTROL 0x8000 // Does the driver control VDDCI independently from VDDC. 141 #define ATOM_PP_PLATFORM_CAP_REGULATOR_HOT 0x00010000 // Enable the 'regulator hot' feature. 142 #define ATOM_PP_PLATFORM_CAP_BACO 0x00020000 // Does the driver supports BACO state. 143 #define ATOM_PP_PLATFORM_CAP_NEW_CAC_VOLTAGE 0x00040000 // Does the driver supports new CAC voltage table. 144 #define ATOM_PP_PLATFORM_CAP_REVERT_GPIO5_POLARITY 0x00080000 // Does the driver supports revert GPIO5 polarity. 145 #define ATOM_PP_PLATFORM_CAP_OUTPUT_THERMAL2GPIO17 0x00100000 // Does the driver supports thermal2GPIO17. 146 #define ATOM_PP_PLATFORM_CAP_VRHOT_GPIO_CONFIGURABLE 0x00200000 // Does the driver supports VR HOT GPIO Configurable. 147 #define ATOM_PP_PLATFORM_CAP_TEMP_INVERSION 0x00400000 // Does the driver supports Temp Inversion feature. 148 #define ATOM_PP_PLATFORM_CAP_EVV 0x00800000 149 #define ATOM_PP_PLATFORM_COMBINE_PCC_WITH_THERMAL_SIGNAL 0x01000000 150 #define ATOM_PP_PLATFORM_LOAD_POST_PRODUCTION_FIRMWARE 0x02000000 151 #define ATOM_PP_PLATFORM_CAP_DISABLE_USING_ACTUAL_TEMPERATURE_FOR_POWER_CALC 0x04000000 152 153 typedef struct _ATOM_PPLIB_POWERPLAYTABLE 154 { 155 ATOM_COMMON_TABLE_HEADER sHeader; 156 157 UCHAR ucDataRevision; 158 159 UCHAR ucNumStates; 160 UCHAR ucStateEntrySize; 161 UCHAR ucClockInfoSize; 162 UCHAR ucNonClockSize; 163 164 // offset from start of this table to array of ucNumStates ATOM_PPLIB_STATE structures 165 USHORT usStateArrayOffset; 166 167 // offset from start of this table to array of ASIC-specific structures, 168 // currently ATOM_PPLIB_CLOCK_INFO. 169 USHORT usClockInfoArrayOffset; 170 171 // offset from start of this table to array of ATOM_PPLIB_NONCLOCK_INFO 172 USHORT usNonClockInfoArrayOffset; 173 174 USHORT usBackbiasTime; // in microseconds 175 USHORT usVoltageTime; // in microseconds 176 USHORT usTableSize; //the size of this structure, or the extended structure 177 178 ULONG ulPlatformCaps; // See ATOM_PPLIB_CAPS_* 179 180 ATOM_PPLIB_THERMALCONTROLLER sThermalController; 181 182 USHORT usBootClockInfoOffset; 183 USHORT usBootNonClockInfoOffset; 184 185 } ATOM_PPLIB_POWERPLAYTABLE; 186 187 typedef struct _ATOM_PPLIB_POWERPLAYTABLE2 188 { 189 ATOM_PPLIB_POWERPLAYTABLE basicTable; 190 UCHAR ucNumCustomThermalPolicy; 191 USHORT usCustomThermalPolicyArrayOffset; 192 }ATOM_PPLIB_POWERPLAYTABLE2, *LPATOM_PPLIB_POWERPLAYTABLE2; 193 194 typedef struct _ATOM_PPLIB_POWERPLAYTABLE3 195 { 196 ATOM_PPLIB_POWERPLAYTABLE2 basicTable2; 197 USHORT usFormatID; // To be used ONLY by PPGen. 198 USHORT usFanTableOffset; 199 USHORT usExtendendedHeaderOffset; 200 } ATOM_PPLIB_POWERPLAYTABLE3, *LPATOM_PPLIB_POWERPLAYTABLE3; 201 202 typedef struct _ATOM_PPLIB_POWERPLAYTABLE4 203 { 204 ATOM_PPLIB_POWERPLAYTABLE3 basicTable3; 205 ULONG ulGoldenPPID; // PPGen use only 206 ULONG ulGoldenRevision; // PPGen use only 207 USHORT usVddcDependencyOnSCLKOffset; 208 USHORT usVddciDependencyOnMCLKOffset; 209 USHORT usVddcDependencyOnMCLKOffset; 210 USHORT usMaxClockVoltageOnDCOffset; 211 USHORT usVddcPhaseShedLimitsTableOffset; // Points to ATOM_PPLIB_PhaseSheddingLimits_Table 212 USHORT usMvddDependencyOnMCLKOffset; 213 } ATOM_PPLIB_POWERPLAYTABLE4, *LPATOM_PPLIB_POWERPLAYTABLE4; 214 215 typedef struct _ATOM_PPLIB_POWERPLAYTABLE5 216 { 217 ATOM_PPLIB_POWERPLAYTABLE4 basicTable4; 218 ULONG ulTDPLimit; 219 ULONG ulNearTDPLimit; 220 ULONG ulSQRampingThreshold; 221 USHORT usCACLeakageTableOffset; // Points to ATOM_PPLIB_CAC_Leakage_Table 222 ULONG ulCACLeakage; // The iLeakage for driver calculated CAC leakage table 223 USHORT usTDPODLimit; 224 USHORT usLoadLineSlope; // in milliOhms * 100 225 } ATOM_PPLIB_POWERPLAYTABLE5, *LPATOM_PPLIB_POWERPLAYTABLE5; 226 227 //// ATOM_PPLIB_NONCLOCK_INFO::usClassification 228 #define ATOM_PPLIB_CLASSIFICATION_UI_MASK 0x0007 229 #define ATOM_PPLIB_CLASSIFICATION_UI_SHIFT 0 230 #define ATOM_PPLIB_CLASSIFICATION_UI_NONE 0 231 #define ATOM_PPLIB_CLASSIFICATION_UI_BATTERY 1 232 #define ATOM_PPLIB_CLASSIFICATION_UI_BALANCED 3 233 #define ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE 5 234 // 2, 4, 6, 7 are reserved 235 236 #define ATOM_PPLIB_CLASSIFICATION_BOOT 0x0008 237 #define ATOM_PPLIB_CLASSIFICATION_THERMAL 0x0010 238 #define ATOM_PPLIB_CLASSIFICATION_LIMITEDPOWERSOURCE 0x0020 239 #define ATOM_PPLIB_CLASSIFICATION_REST 0x0040 240 #define ATOM_PPLIB_CLASSIFICATION_FORCED 0x0080 241 #define ATOM_PPLIB_CLASSIFICATION_3DPERFORMANCE 0x0100 242 #define ATOM_PPLIB_CLASSIFICATION_OVERDRIVETEMPLATE 0x0200 243 #define ATOM_PPLIB_CLASSIFICATION_UVDSTATE 0x0400 244 #define ATOM_PPLIB_CLASSIFICATION_3DLOW 0x0800 245 #define ATOM_PPLIB_CLASSIFICATION_ACPI 0x1000 246 #define ATOM_PPLIB_CLASSIFICATION_HD2STATE 0x2000 247 #define ATOM_PPLIB_CLASSIFICATION_HDSTATE 0x4000 248 #define ATOM_PPLIB_CLASSIFICATION_SDSTATE 0x8000 249 250 //// ATOM_PPLIB_NONCLOCK_INFO::usClassification2 251 #define ATOM_PPLIB_CLASSIFICATION2_LIMITEDPOWERSOURCE_2 0x0001 252 #define ATOM_PPLIB_CLASSIFICATION2_ULV 0x0002 253 #define ATOM_PPLIB_CLASSIFICATION2_MVC 0x0004 //Multi-View Codec (BD-3D) 254 255 //// ATOM_PPLIB_NONCLOCK_INFO::ulCapsAndSettings 256 #define ATOM_PPLIB_SINGLE_DISPLAY_ONLY 0x00000001 257 #define ATOM_PPLIB_SUPPORTS_VIDEO_PLAYBACK 0x00000002 258 259 // 0 is 2.5Gb/s, 1 is 5Gb/s 260 #define ATOM_PPLIB_PCIE_LINK_SPEED_MASK 0x00000004 261 #define ATOM_PPLIB_PCIE_LINK_SPEED_SHIFT 2 262 263 // lanes - 1: 1, 2, 4, 8, 12, 16 permitted by PCIE spec 264 #define ATOM_PPLIB_PCIE_LINK_WIDTH_MASK 0x000000F8 265 #define ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT 3 266 267 // lookup into reduced refresh-rate table 268 #define ATOM_PPLIB_LIMITED_REFRESHRATE_VALUE_MASK 0x00000F00 269 #define ATOM_PPLIB_LIMITED_REFRESHRATE_VALUE_SHIFT 8 270 271 #define ATOM_PPLIB_LIMITED_REFRESHRATE_UNLIMITED 0 272 #define ATOM_PPLIB_LIMITED_REFRESHRATE_50HZ 1 273 // 2-15 TBD as needed. 274 275 #define ATOM_PPLIB_SOFTWARE_DISABLE_LOADBALANCING 0x00001000 276 #define ATOM_PPLIB_SOFTWARE_ENABLE_SLEEP_FOR_TIMESTAMPS 0x00002000 277 278 #define ATOM_PPLIB_DISALLOW_ON_DC 0x00004000 279 280 #define ATOM_PPLIB_ENABLE_VARIBRIGHT 0x00008000 281 282 //memory related flags 283 #define ATOM_PPLIB_SWSTATE_MEMORY_DLL_OFF 0x000010000 284 285 //M3 Arb //2bits, current 3 sets of parameters in total 286 #define ATOM_PPLIB_M3ARB_MASK 0x00060000 287 #define ATOM_PPLIB_M3ARB_SHIFT 17 288 289 #define ATOM_PPLIB_ENABLE_DRR 0x00080000 290 291 // remaining 16 bits are reserved 292 typedef struct _ATOM_PPLIB_THERMAL_STATE 293 { 294 UCHAR ucMinTemperature; 295 UCHAR ucMaxTemperature; 296 UCHAR ucThermalAction; 297 }ATOM_PPLIB_THERMAL_STATE, *LPATOM_PPLIB_THERMAL_STATE; 298 299 // Contained in an array starting at the offset 300 // in ATOM_PPLIB_POWERPLAYTABLE::usNonClockInfoArrayOffset. 301 // referenced from ATOM_PPLIB_STATE_INFO::ucNonClockStateIndex 302 #define ATOM_PPLIB_NONCLOCKINFO_VER1 12 303 #define ATOM_PPLIB_NONCLOCKINFO_VER2 24 304 typedef struct _ATOM_PPLIB_NONCLOCK_INFO 305 { 306 USHORT usClassification; 307 UCHAR ucMinTemperature; 308 UCHAR ucMaxTemperature; 309 ULONG ulCapsAndSettings; 310 UCHAR ucRequiredPower; 311 USHORT usClassification2; 312 ULONG ulVCLK; 313 ULONG ulDCLK; 314 UCHAR ucUnused[5]; 315 } ATOM_PPLIB_NONCLOCK_INFO; 316 317 // Contained in an array starting at the offset 318 // in ATOM_PPLIB_POWERPLAYTABLE::usClockInfoArrayOffset. 319 // referenced from ATOM_PPLIB_STATE::ucClockStateIndices 320 typedef struct _ATOM_PPLIB_R600_CLOCK_INFO 321 { 322 USHORT usEngineClockLow; 323 UCHAR ucEngineClockHigh; 324 325 USHORT usMemoryClockLow; 326 UCHAR ucMemoryClockHigh; 327 328 USHORT usVDDC; 329 USHORT usUnused1; 330 USHORT usUnused2; 331 332 ULONG ulFlags; // ATOM_PPLIB_R600_FLAGS_* 333 334 } ATOM_PPLIB_R600_CLOCK_INFO; 335 336 // ulFlags in ATOM_PPLIB_R600_CLOCK_INFO 337 #define ATOM_PPLIB_R600_FLAGS_PCIEGEN2 1 338 #define ATOM_PPLIB_R600_FLAGS_UVDSAFE 2 339 #define ATOM_PPLIB_R600_FLAGS_BACKBIASENABLE 4 340 #define ATOM_PPLIB_R600_FLAGS_MEMORY_ODT_OFF 8 341 #define ATOM_PPLIB_R600_FLAGS_MEMORY_DLL_OFF 16 342 #define ATOM_PPLIB_R600_FLAGS_LOWPOWER 32 // On the RV770 use 'low power' setting (sequencer S0). 343 344 typedef struct _ATOM_PPLIB_RS780_CLOCK_INFO 345 346 { 347 USHORT usLowEngineClockLow; // Low Engine clock in MHz (the same way as on the R600). 348 UCHAR ucLowEngineClockHigh; 349 USHORT usHighEngineClockLow; // High Engine clock in MHz. 350 UCHAR ucHighEngineClockHigh; 351 USHORT usMemoryClockLow; // For now one of the ATOM_PPLIB_RS780_SPMCLK_XXXX constants. 352 UCHAR ucMemoryClockHigh; // Currentyl unused. 353 UCHAR ucPadding; // For proper alignment and size. 354 USHORT usVDDC; // For the 780, use: None, Low, High, Variable 355 UCHAR ucMaxHTLinkWidth; // From SBIOS - {2, 4, 8, 16} 356 UCHAR ucMinHTLinkWidth; // From SBIOS - {2, 4, 8, 16}. Effective only if CDLW enabled. Minimum down stream width could 357 USHORT usHTLinkFreq; // See definition ATOM_PPLIB_RS780_HTLINKFREQ_xxx or in MHz(>=200). 358 ULONG ulFlags; 359 } ATOM_PPLIB_RS780_CLOCK_INFO; 360 361 #define ATOM_PPLIB_RS780_VOLTAGE_NONE 0 362 #define ATOM_PPLIB_RS780_VOLTAGE_LOW 1 363 #define ATOM_PPLIB_RS780_VOLTAGE_HIGH 2 364 #define ATOM_PPLIB_RS780_VOLTAGE_VARIABLE 3 365 366 #define ATOM_PPLIB_RS780_SPMCLK_NONE 0 // We cannot change the side port memory clock, leave it as it is. 367 #define ATOM_PPLIB_RS780_SPMCLK_LOW 1 368 #define ATOM_PPLIB_RS780_SPMCLK_HIGH 2 369 370 #define ATOM_PPLIB_RS780_HTLINKFREQ_NONE 0 371 #define ATOM_PPLIB_RS780_HTLINKFREQ_LOW 1 372 #define ATOM_PPLIB_RS780_HTLINKFREQ_HIGH 2 373 374 typedef struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO 375 { 376 USHORT usEngineClockLow; 377 UCHAR ucEngineClockHigh; 378 379 USHORT usMemoryClockLow; 380 UCHAR ucMemoryClockHigh; 381 382 USHORT usVDDC; 383 USHORT usVDDCI; 384 USHORT usUnused; 385 386 ULONG ulFlags; // ATOM_PPLIB_R600_FLAGS_* 387 388 } ATOM_PPLIB_EVERGREEN_CLOCK_INFO; 389 390 typedef struct _ATOM_PPLIB_SI_CLOCK_INFO 391 { 392 USHORT usEngineClockLow; 393 UCHAR ucEngineClockHigh; 394 395 USHORT usMemoryClockLow; 396 UCHAR ucMemoryClockHigh; 397 398 USHORT usVDDC; 399 USHORT usVDDCI; 400 UCHAR ucPCIEGen; 401 UCHAR ucUnused1; 402 403 ULONG ulFlags; // ATOM_PPLIB_SI_FLAGS_*, no flag is necessary for now 404 405 } ATOM_PPLIB_SI_CLOCK_INFO; 406 407 typedef struct _ATOM_PPLIB_CI_CLOCK_INFO 408 { 409 USHORT usEngineClockLow; 410 UCHAR ucEngineClockHigh; 411 412 USHORT usMemoryClockLow; 413 UCHAR ucMemoryClockHigh; 414 415 UCHAR ucPCIEGen; 416 USHORT usPCIELane; 417 } ATOM_PPLIB_CI_CLOCK_INFO; 418 419 typedef struct _ATOM_PPLIB_SUMO_CLOCK_INFO{ 420 USHORT usEngineClockLow; //clockfrequency & 0xFFFF. The unit is in 10khz 421 UCHAR ucEngineClockHigh; //clockfrequency >> 16. 422 UCHAR vddcIndex; //2-bit vddc index; 423 USHORT tdpLimit; 424 //please initalize to 0 425 USHORT rsv1; 426 //please initialize to 0s 427 ULONG rsv2[2]; 428 }ATOM_PPLIB_SUMO_CLOCK_INFO; 429 430 typedef struct _ATOM_PPLIB_CZ_CLOCK_INFO { 431 UCHAR index; 432 UCHAR rsv[3]; 433 } ATOM_PPLIB_CZ_CLOCK_INFO; 434 435 typedef struct _ATOM_PPLIB_STATE_V2 436 { 437 //number of valid dpm levels in this state; Driver uses it to calculate the whole 438 //size of the state: sizeof(ATOM_PPLIB_STATE_V2) + (ucNumDPMLevels - 1) * sizeof(UCHAR) 439 UCHAR ucNumDPMLevels; 440 441 //a index to the array of nonClockInfos 442 UCHAR nonClockInfoIndex; 443 /** 444 * Driver will read the first ucNumDPMLevels in this array 445 */ 446 UCHAR clockInfoIndex[1]; 447 } ATOM_PPLIB_STATE_V2; 448 449 typedef struct _StateArray{ 450 //how many states we have 451 UCHAR ucNumEntries; 452 453 ATOM_PPLIB_STATE_V2 states[1]; 454 }StateArray; 455 456 457 typedef struct _ClockInfoArray{ 458 //how many clock levels we have 459 UCHAR ucNumEntries; 460 461 //sizeof(ATOM_PPLIB_CLOCK_INFO) 462 UCHAR ucEntrySize; 463 464 UCHAR clockInfo[1]; 465 }ClockInfoArray; 466 467 typedef struct _NonClockInfoArray{ 468 469 //how many non-clock levels we have. normally should be same as number of states 470 UCHAR ucNumEntries; 471 //sizeof(ATOM_PPLIB_NONCLOCK_INFO) 472 UCHAR ucEntrySize; 473 474 ATOM_PPLIB_NONCLOCK_INFO nonClockInfo[1]; 475 }NonClockInfoArray; 476 477 typedef struct _ATOM_PPLIB_Clock_Voltage_Dependency_Record 478 { 479 USHORT usClockLow; 480 UCHAR ucClockHigh; 481 USHORT usVoltage; 482 }ATOM_PPLIB_Clock_Voltage_Dependency_Record; 483 484 typedef struct _ATOM_PPLIB_Clock_Voltage_Dependency_Table 485 { 486 UCHAR ucNumEntries; // Number of entries. 487 ATOM_PPLIB_Clock_Voltage_Dependency_Record entries[1]; // Dynamically allocate entries. 488 }ATOM_PPLIB_Clock_Voltage_Dependency_Table; 489 490 typedef struct _ATOM_PPLIB_Clock_Voltage_Limit_Record 491 { 492 USHORT usSclkLow; 493 UCHAR ucSclkHigh; 494 USHORT usMclkLow; 495 UCHAR ucMclkHigh; 496 USHORT usVddc; 497 USHORT usVddci; 498 }ATOM_PPLIB_Clock_Voltage_Limit_Record; 499 500 typedef struct _ATOM_PPLIB_Clock_Voltage_Limit_Table 501 { 502 UCHAR ucNumEntries; // Number of entries. 503 ATOM_PPLIB_Clock_Voltage_Limit_Record entries[1]; // Dynamically allocate entries. 504 }ATOM_PPLIB_Clock_Voltage_Limit_Table; 505 506 union _ATOM_PPLIB_CAC_Leakage_Record 507 { 508 struct 509 { 510 USHORT usVddc; // We use this field for the "fake" standardized VDDC for power calculations; For CI and newer, we use this as the real VDDC value. in CI we read it as StdVoltageHiSidd 511 ULONG ulLeakageValue; // For CI and newer we use this as the "fake" standar VDDC value. in CI we read it as StdVoltageLoSidd 512 513 }; 514 struct 515 { 516 USHORT usVddc1; 517 USHORT usVddc2; 518 USHORT usVddc3; 519 }; 520 }; 521 522 typedef union _ATOM_PPLIB_CAC_Leakage_Record ATOM_PPLIB_CAC_Leakage_Record; 523 524 typedef struct _ATOM_PPLIB_CAC_Leakage_Table 525 { 526 UCHAR ucNumEntries; // Number of entries. 527 ATOM_PPLIB_CAC_Leakage_Record entries[1]; // Dynamically allocate entries. 528 }ATOM_PPLIB_CAC_Leakage_Table; 529 530 typedef struct _ATOM_PPLIB_PhaseSheddingLimits_Record 531 { 532 USHORT usVoltage; 533 USHORT usSclkLow; 534 UCHAR ucSclkHigh; 535 USHORT usMclkLow; 536 UCHAR ucMclkHigh; 537 }ATOM_PPLIB_PhaseSheddingLimits_Record; 538 539 typedef struct _ATOM_PPLIB_PhaseSheddingLimits_Table 540 { 541 UCHAR ucNumEntries; // Number of entries. 542 ATOM_PPLIB_PhaseSheddingLimits_Record entries[1]; // Dynamically allocate entries. 543 }ATOM_PPLIB_PhaseSheddingLimits_Table; 544 545 typedef struct _VCEClockInfo{ 546 USHORT usEVClkLow; 547 UCHAR ucEVClkHigh; 548 USHORT usECClkLow; 549 UCHAR ucECClkHigh; 550 }VCEClockInfo; 551 552 typedef struct _VCEClockInfoArray{ 553 UCHAR ucNumEntries; 554 VCEClockInfo entries[1]; 555 }VCEClockInfoArray; 556 557 typedef struct _ATOM_PPLIB_VCE_Clock_Voltage_Limit_Record 558 { 559 USHORT usVoltage; 560 UCHAR ucVCEClockInfoIndex; 561 }ATOM_PPLIB_VCE_Clock_Voltage_Limit_Record; 562 563 typedef struct _ATOM_PPLIB_VCE_Clock_Voltage_Limit_Table 564 { 565 UCHAR numEntries; 566 ATOM_PPLIB_VCE_Clock_Voltage_Limit_Record entries[1]; 567 }ATOM_PPLIB_VCE_Clock_Voltage_Limit_Table; 568 569 typedef struct _ATOM_PPLIB_VCE_State_Record 570 { 571 UCHAR ucVCEClockInfoIndex; 572 UCHAR ucClockInfoIndex; //highest 2 bits indicates memory p-states, lower 6bits indicates index to ClockInfoArrary 573 }ATOM_PPLIB_VCE_State_Record; 574 575 typedef struct _ATOM_PPLIB_VCE_State_Table 576 { 577 UCHAR numEntries; 578 ATOM_PPLIB_VCE_State_Record entries[1]; 579 }ATOM_PPLIB_VCE_State_Table; 580 581 582 typedef struct _ATOM_PPLIB_VCE_Table 583 { 584 UCHAR revid; 585 // VCEClockInfoArray array; 586 // ATOM_PPLIB_VCE_Clock_Voltage_Limit_Table limits; 587 // ATOM_PPLIB_VCE_State_Table states; 588 }ATOM_PPLIB_VCE_Table; 589 590 591 typedef struct _UVDClockInfo{ 592 USHORT usVClkLow; 593 UCHAR ucVClkHigh; 594 USHORT usDClkLow; 595 UCHAR ucDClkHigh; 596 }UVDClockInfo; 597 598 typedef struct _UVDClockInfoArray{ 599 UCHAR ucNumEntries; 600 UVDClockInfo entries[1]; 601 }UVDClockInfoArray; 602 603 typedef struct _ATOM_PPLIB_UVD_Clock_Voltage_Limit_Record 604 { 605 USHORT usVoltage; 606 UCHAR ucUVDClockInfoIndex; 607 }ATOM_PPLIB_UVD_Clock_Voltage_Limit_Record; 608 609 typedef struct _ATOM_PPLIB_UVD_Clock_Voltage_Limit_Table 610 { 611 UCHAR numEntries; 612 ATOM_PPLIB_UVD_Clock_Voltage_Limit_Record entries[1]; 613 }ATOM_PPLIB_UVD_Clock_Voltage_Limit_Table; 614 615 typedef struct _ATOM_PPLIB_UVD_Table 616 { 617 UCHAR revid; 618 // UVDClockInfoArray array; 619 // ATOM_PPLIB_UVD_Clock_Voltage_Limit_Table limits; 620 }ATOM_PPLIB_UVD_Table; 621 622 typedef struct _ATOM_PPLIB_SAMClk_Voltage_Limit_Record 623 { 624 USHORT usVoltage; 625 USHORT usSAMClockLow; 626 UCHAR ucSAMClockHigh; 627 }ATOM_PPLIB_SAMClk_Voltage_Limit_Record; 628 629 typedef struct _ATOM_PPLIB_SAMClk_Voltage_Limit_Table{ 630 UCHAR numEntries; 631 ATOM_PPLIB_SAMClk_Voltage_Limit_Record entries[1]; 632 }ATOM_PPLIB_SAMClk_Voltage_Limit_Table; 633 634 typedef struct _ATOM_PPLIB_SAMU_Table 635 { 636 UCHAR revid; 637 ATOM_PPLIB_SAMClk_Voltage_Limit_Table limits; 638 }ATOM_PPLIB_SAMU_Table; 639 640 typedef struct _ATOM_PPLIB_ACPClk_Voltage_Limit_Record 641 { 642 USHORT usVoltage; 643 USHORT usACPClockLow; 644 UCHAR ucACPClockHigh; 645 }ATOM_PPLIB_ACPClk_Voltage_Limit_Record; 646 647 typedef struct _ATOM_PPLIB_ACPClk_Voltage_Limit_Table{ 648 UCHAR numEntries; 649 ATOM_PPLIB_ACPClk_Voltage_Limit_Record entries[1]; 650 }ATOM_PPLIB_ACPClk_Voltage_Limit_Table; 651 652 typedef struct _ATOM_PPLIB_ACP_Table 653 { 654 UCHAR revid; 655 ATOM_PPLIB_ACPClk_Voltage_Limit_Table limits; 656 }ATOM_PPLIB_ACP_Table; 657 658 typedef struct _ATOM_PowerTune_Table{ 659 USHORT usTDP; 660 USHORT usConfigurableTDP; 661 USHORT usTDC; 662 USHORT usBatteryPowerLimit; 663 USHORT usSmallPowerLimit; 664 USHORT usLowCACLeakage; 665 USHORT usHighCACLeakage; 666 }ATOM_PowerTune_Table; 667 668 typedef struct _ATOM_PPLIB_POWERTUNE_Table 669 { 670 UCHAR revid; 671 ATOM_PowerTune_Table power_tune_table; 672 }ATOM_PPLIB_POWERTUNE_Table; 673 674 typedef struct _ATOM_PPLIB_POWERTUNE_Table_V1 675 { 676 UCHAR revid; 677 ATOM_PowerTune_Table power_tune_table; 678 USHORT usMaximumPowerDeliveryLimit; 679 USHORT usTjMax; 680 USHORT usReserve[6]; 681 } ATOM_PPLIB_POWERTUNE_Table_V1; 682 683 #define ATOM_PPM_A_A 1 684 #define ATOM_PPM_A_I 2 685 typedef struct _ATOM_PPLIB_PPM_Table 686 { 687 UCHAR ucRevId; 688 UCHAR ucPpmDesign; //A+I or A+A 689 USHORT usCpuCoreNumber; 690 ULONG ulPlatformTDP; 691 ULONG ulSmallACPlatformTDP; 692 ULONG ulPlatformTDC; 693 ULONG ulSmallACPlatformTDC; 694 ULONG ulApuTDP; 695 ULONG ulDGpuTDP; 696 ULONG ulDGpuUlvPower; 697 ULONG ulTjmax; 698 } ATOM_PPLIB_PPM_Table; 699 700 #pragma pack() 701 702 #endif 703