1 /* 2 * Copyright 2022 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #ifndef __MES_API_DEF_H__ 25 #define __MES_API_DEF_H__ 26 27 #pragma pack(push, 4) 28 29 #define MES_API_VERSION 1 30 31 /* Driver submits one API(cmd) as a single Frame and this command size is same 32 * for all API to ease the debugging and parsing of ring buffer. 33 */ 34 enum { API_FRAME_SIZE_IN_DWORDS = 64 }; 35 36 /* To avoid command in scheduler context to be overwritten whenenver mutilple 37 * interrupts come in, this creates another queue. 38 */ 39 enum { API_NUMBER_OF_COMMAND_MAX = 32 }; 40 41 enum MES_API_TYPE { 42 MES_API_TYPE_SCHEDULER = 1, 43 MES_API_TYPE_MAX 44 }; 45 46 enum MES_SCH_API_OPCODE { 47 MES_SCH_API_SET_HW_RSRC = 0, 48 MES_SCH_API_SET_SCHEDULING_CONFIG = 1, /* agreegated db, quantums, etc */ 49 MES_SCH_API_ADD_QUEUE = 2, 50 MES_SCH_API_REMOVE_QUEUE = 3, 51 MES_SCH_API_PERFORM_YIELD = 4, 52 MES_SCH_API_SET_GANG_PRIORITY_LEVEL = 5, 53 MES_SCH_API_SUSPEND = 6, 54 MES_SCH_API_RESUME = 7, 55 MES_SCH_API_RESET = 8, 56 MES_SCH_API_SET_LOG_BUFFER = 9, 57 MES_SCH_API_CHANGE_GANG_PRORITY = 10, 58 MES_SCH_API_QUERY_SCHEDULER_STATUS = 11, 59 MES_SCH_API_PROGRAM_GDS = 12, 60 MES_SCH_API_SET_DEBUG_VMID = 13, 61 MES_SCH_API_MISC = 14, 62 MES_SCH_API_UPDATE_ROOT_PAGE_TABLE = 15, 63 MES_SCH_API_AMD_LOG = 16, 64 MES_SCH_API_MAX = 0xFF 65 }; 66 67 union MES_API_HEADER { 68 struct { 69 uint32_t type : 4; /* 0 - Invalid; 1 - Scheduling; 2 - TBD */ 70 uint32_t opcode : 8; 71 uint32_t dwsize : 8; /* including header */ 72 uint32_t reserved : 12; 73 }; 74 75 uint32_t u32All; 76 }; 77 78 enum MES_AMD_PRIORITY_LEVEL { 79 AMD_PRIORITY_LEVEL_LOW = 0, 80 AMD_PRIORITY_LEVEL_NORMAL = 1, 81 AMD_PRIORITY_LEVEL_MEDIUM = 2, 82 AMD_PRIORITY_LEVEL_HIGH = 3, 83 AMD_PRIORITY_LEVEL_REALTIME = 4, 84 AMD_PRIORITY_NUM_LEVELS 85 }; 86 87 enum MES_QUEUE_TYPE { 88 MES_QUEUE_TYPE_GFX, 89 MES_QUEUE_TYPE_COMPUTE, 90 MES_QUEUE_TYPE_SDMA, 91 MES_QUEUE_TYPE_MAX, 92 }; 93 94 struct MES_API_STATUS { 95 uint64_t api_completion_fence_addr; 96 uint64_t api_completion_fence_value; 97 }; 98 99 enum { MAX_COMPUTE_PIPES = 8 }; 100 enum { MAX_GFX_PIPES = 2 }; 101 enum { MAX_SDMA_PIPES = 2 }; 102 103 enum { MAX_COMPUTE_HQD_PER_PIPE = 8 }; 104 enum { MAX_GFX_HQD_PER_PIPE = 8 }; 105 enum { MAX_SDMA_HQD_PER_PIPE = 10 }; 106 enum { MAX_SDMA_HQD_PER_PIPE_11_0 = 8 }; 107 108 enum { MAX_QUEUES_IN_A_GANG = 8 }; 109 110 enum VM_HUB_TYPE { 111 VM_HUB_TYPE_GC = 0, 112 VM_HUB_TYPE_MM = 1, 113 VM_HUB_TYPE_MAX, 114 }; 115 116 enum { VMID_INVALID = 0xffff }; 117 118 enum { MAX_VMID_GCHUB = 16 }; 119 enum { MAX_VMID_MMHUB = 16 }; 120 121 enum SET_DEBUG_VMID_OPERATIONS { 122 DEBUG_VMID_OP_PROGRAM = 0, 123 DEBUG_VMID_OP_ALLOCATE = 1, 124 DEBUG_VMID_OP_RELEASE = 2 125 }; 126 127 enum MES_LOG_OPERATION { 128 MES_LOG_OPERATION_CONTEXT_STATE_CHANGE = 0, 129 MES_LOG_OPERATION_QUEUE_NEW_WORK = 1, 130 MES_LOG_OPERATION_QUEUE_UNWAIT_SYNC_OBJECT = 2, 131 MES_LOG_OPERATION_QUEUE_NO_MORE_WORK = 3, 132 MES_LOG_OPERATION_QUEUE_WAIT_SYNC_OBJECT = 4, 133 MES_LOG_OPERATION_QUEUE_INVALID = 0xF, 134 }; 135 136 enum MES_LOG_CONTEXT_STATE { 137 MES_LOG_CONTEXT_STATE_IDLE = 0, 138 MES_LOG_CONTEXT_STATE_RUNNING = 1, 139 MES_LOG_CONTEXT_STATE_READY = 2, 140 MES_LOG_CONTEXT_STATE_READY_STANDBY = 3, 141 MES_LOG_CONTEXT_STATE_INVALID = 0xF, 142 }; 143 144 struct MES_LOG_CONTEXT_STATE_CHANGE { 145 void *h_context; 146 enum MES_LOG_CONTEXT_STATE new_context_state; 147 }; 148 149 struct MES_LOG_QUEUE_NEW_WORK { 150 uint64_t h_queue; 151 uint64_t reserved; 152 }; 153 154 struct MES_LOG_QUEUE_UNWAIT_SYNC_OBJECT { 155 uint64_t h_queue; 156 uint64_t h_sync_object; 157 }; 158 159 struct MES_LOG_QUEUE_NO_MORE_WORK { 160 uint64_t h_queue; 161 uint64_t reserved; 162 }; 163 164 struct MES_LOG_QUEUE_WAIT_SYNC_OBJECT { 165 uint64_t h_queue; 166 uint64_t h_sync_object; 167 }; 168 169 struct MES_LOG_ENTRY_HEADER { 170 uint32_t first_free_entry_index; 171 uint32_t wraparound_count; 172 uint64_t number_of_entries; 173 uint64_t reserved[2]; 174 }; 175 176 struct MES_LOG_ENTRY_DATA { 177 uint64_t gpu_time_stamp; 178 uint32_t operation_type; /* operation_type is of MES_LOG_OPERATION type */ 179 uint32_t reserved_operation_type_bits; 180 union { 181 struct MES_LOG_CONTEXT_STATE_CHANGE context_state_change; 182 struct MES_LOG_QUEUE_NEW_WORK queue_new_work; 183 struct MES_LOG_QUEUE_UNWAIT_SYNC_OBJECT queue_unwait_sync_object; 184 struct MES_LOG_QUEUE_NO_MORE_WORK queue_no_more_work; 185 struct MES_LOG_QUEUE_WAIT_SYNC_OBJECT queue_wait_sync_object; 186 uint64_t all[2]; 187 }; 188 }; 189 190 struct MES_LOG_BUFFER { 191 struct MES_LOG_ENTRY_HEADER header; 192 struct MES_LOG_ENTRY_DATA entries[1]; 193 }; 194 195 enum MES_SWIP_TO_HWIP_DEF { 196 MES_MAX_HWIP_SEGMENT = 8, 197 }; 198 199 union MESAPI_SET_HW_RESOURCES { 200 struct { 201 union MES_API_HEADER header; 202 uint32_t vmid_mask_mmhub; 203 uint32_t vmid_mask_gfxhub; 204 uint32_t gds_size; 205 uint32_t paging_vmid; 206 uint32_t compute_hqd_mask[MAX_COMPUTE_PIPES]; 207 uint32_t gfx_hqd_mask[MAX_GFX_PIPES]; 208 uint32_t sdma_hqd_mask[MAX_SDMA_PIPES]; 209 uint32_t aggregated_doorbells[AMD_PRIORITY_NUM_LEVELS]; 210 uint64_t g_sch_ctx_gpu_mc_ptr; 211 uint64_t query_status_fence_gpu_mc_ptr; 212 uint32_t gc_base[MES_MAX_HWIP_SEGMENT]; 213 uint32_t mmhub_base[MES_MAX_HWIP_SEGMENT]; 214 uint32_t osssys_base[MES_MAX_HWIP_SEGMENT]; 215 struct MES_API_STATUS api_status; 216 union { 217 struct { 218 uint32_t disable_reset : 1; 219 uint32_t use_different_vmid_compute : 1; 220 uint32_t disable_mes_log : 1; 221 uint32_t apply_mmhub_pgvm_invalidate_ack_loss_wa : 1; 222 uint32_t apply_grbm_remote_register_dummy_read_wa : 1; 223 uint32_t second_gfx_pipe_enabled : 1; 224 uint32_t enable_level_process_quantum_check : 1; 225 uint32_t reserved : 25; 226 }; 227 uint32_t uint32_t_all; 228 }; 229 uint32_t oversubscription_timer; 230 uint64_t doorbell_info; 231 }; 232 233 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS]; 234 }; 235 236 union MESAPI__ADD_QUEUE { 237 struct { 238 union MES_API_HEADER header; 239 uint32_t process_id; 240 uint64_t page_table_base_addr; 241 uint64_t process_va_start; 242 uint64_t process_va_end; 243 uint64_t process_quantum; 244 uint64_t process_context_addr; 245 uint64_t gang_quantum; 246 uint64_t gang_context_addr; 247 uint32_t inprocess_gang_priority; 248 enum MES_AMD_PRIORITY_LEVEL gang_global_priority_level; 249 uint32_t doorbell_offset; 250 uint64_t mqd_addr; 251 uint64_t wptr_addr; 252 uint64_t h_context; 253 uint64_t h_queue; 254 enum MES_QUEUE_TYPE queue_type; 255 uint32_t gds_base; 256 uint32_t gds_size; 257 uint32_t gws_base; 258 uint32_t gws_size; 259 uint32_t oa_mask; 260 uint64_t trap_handler_addr; 261 uint32_t vm_context_cntl; 262 263 struct { 264 uint32_t paging : 1; 265 uint32_t debug_vmid : 4; 266 uint32_t program_gds : 1; 267 uint32_t is_gang_suspended : 1; 268 uint32_t is_tmz_queue : 1; 269 uint32_t map_kiq_utility_queue : 1; 270 uint32_t is_kfd_process : 1; 271 uint32_t trap_en : 1; 272 uint32_t is_aql_queue : 1; 273 uint32_t reserved : 20; 274 }; 275 struct MES_API_STATUS api_status; 276 uint64_t tma_addr; 277 }; 278 279 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS]; 280 }; 281 282 union MESAPI__REMOVE_QUEUE { 283 struct { 284 union MES_API_HEADER header; 285 uint32_t doorbell_offset; 286 uint64_t gang_context_addr; 287 288 struct { 289 uint32_t unmap_legacy_gfx_queue : 1; 290 uint32_t unmap_kiq_utility_queue : 1; 291 uint32_t preempt_legacy_gfx_queue : 1; 292 uint32_t unmap_legacy_queue : 1; 293 uint32_t reserved : 28; 294 }; 295 struct MES_API_STATUS api_status; 296 297 uint32_t pipe_id; 298 uint32_t queue_id; 299 300 uint64_t tf_addr; 301 uint32_t tf_data; 302 303 enum MES_QUEUE_TYPE queue_type; 304 }; 305 306 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS]; 307 }; 308 309 union MESAPI__SET_SCHEDULING_CONFIG { 310 struct { 311 union MES_API_HEADER header; 312 /* Grace period when preempting another priority band for this 313 * priority band. The value for idle priority band is ignored, 314 * as it never preempts other bands. 315 */ 316 uint64_t grace_period_other_levels[AMD_PRIORITY_NUM_LEVELS]; 317 /* Default quantum for scheduling across processes within 318 * a priority band. 319 */ 320 uint64_t process_quantum_for_level[AMD_PRIORITY_NUM_LEVELS]; 321 /* Default grace period for processes that preempt each other 322 * within a priority band. 323 */ 324 uint64_t process_grace_period_same_level[AMD_PRIORITY_NUM_LEVELS]; 325 /* For normal level this field specifies the target GPU 326 * percentage in situations when it's starved by the high level. 327 * Valid values are between 0 and 50, with the default being 10. 328 */ 329 uint32_t normal_yield_percent; 330 struct MES_API_STATUS api_status; 331 }; 332 333 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS]; 334 }; 335 336 union MESAPI__PERFORM_YIELD { 337 struct { 338 union MES_API_HEADER header; 339 uint32_t dummy; 340 struct MES_API_STATUS api_status; 341 }; 342 343 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS]; 344 }; 345 346 union MESAPI__CHANGE_GANG_PRIORITY_LEVEL { 347 struct { 348 union MES_API_HEADER header; 349 uint32_t inprocess_gang_priority; 350 enum MES_AMD_PRIORITY_LEVEL gang_global_priority_level; 351 uint64_t gang_quantum; 352 uint64_t gang_context_addr; 353 struct MES_API_STATUS api_status; 354 }; 355 356 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS]; 357 }; 358 359 union MESAPI__SUSPEND { 360 struct { 361 union MES_API_HEADER header; 362 /* false - suspend all gangs; true - specific gang */ 363 struct { 364 uint32_t suspend_all_gangs : 1; 365 uint32_t reserved : 31; 366 }; 367 /* gang_context_addr is valid only if suspend_all = false */ 368 uint64_t gang_context_addr; 369 370 uint64_t suspend_fence_addr; 371 uint32_t suspend_fence_value; 372 373 struct MES_API_STATUS api_status; 374 }; 375 376 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS]; 377 }; 378 379 union MESAPI__RESUME { 380 struct { 381 union MES_API_HEADER header; 382 /* false - resume all gangs; true - specified gang */ 383 struct { 384 uint32_t resume_all_gangs : 1; 385 uint32_t reserved : 31; 386 }; 387 /* valid only if resume_all_gangs = false */ 388 uint64_t gang_context_addr; 389 390 struct MES_API_STATUS api_status; 391 }; 392 393 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS]; 394 }; 395 396 union MESAPI__RESET { 397 struct { 398 union MES_API_HEADER header; 399 400 struct { 401 /* Only reset the queue given by doorbell_offset (not entire gang) */ 402 uint32_t reset_queue_only : 1; 403 /* Hang detection first then reset any queues that are hung */ 404 uint32_t hang_detect_then_reset : 1; 405 /* Only do hang detection (no reset) */ 406 uint32_t hang_detect_only : 1; 407 /* Rest HP and LP kernel queues not managed by MES */ 408 uint32_t reset_legacy_gfx : 1; 409 uint32_t reserved : 28; 410 }; 411 412 uint64_t gang_context_addr; 413 414 /* valid only if reset_queue_only = true */ 415 uint32_t doorbell_offset; 416 417 /* valid only if hang_detect_then_reset = true */ 418 uint64_t doorbell_offset_addr; 419 enum MES_QUEUE_TYPE queue_type; 420 421 /* valid only if reset_legacy_gfx = true */ 422 uint32_t pipe_id_lp; 423 uint32_t queue_id_lp; 424 uint32_t vmid_id_lp; 425 uint64_t mqd_mc_addr_lp; 426 uint32_t doorbell_offset_lp; 427 uint64_t wptr_addr_lp; 428 429 uint32_t pipe_id_hp; 430 uint32_t queue_id_hp; 431 uint32_t vmid_id_hp; 432 uint64_t mqd_mc_addr_hp; 433 uint32_t doorbell_offset_hp; 434 uint64_t wptr_addr_hp; 435 436 struct MES_API_STATUS api_status; 437 }; 438 439 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS]; 440 }; 441 442 union MESAPI__SET_LOGGING_BUFFER { 443 struct { 444 union MES_API_HEADER header; 445 /* There are separate log buffers for each queue type */ 446 enum MES_QUEUE_TYPE log_type; 447 /* Log buffer GPU Address */ 448 uint64_t logging_buffer_addr; 449 /* number of entries in the log buffer */ 450 uint32_t number_of_entries; 451 /* Entry index at which CPU interrupt needs to be signalled */ 452 uint32_t interrupt_entry; 453 454 struct MES_API_STATUS api_status; 455 }; 456 457 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS]; 458 }; 459 460 union MESAPI__QUERY_MES_STATUS { 461 struct { 462 union MES_API_HEADER header; 463 bool mes_healthy; /* 0 - not healthy, 1 - healthy */ 464 struct MES_API_STATUS api_status; 465 }; 466 467 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS]; 468 }; 469 470 union MESAPI__PROGRAM_GDS { 471 struct { 472 union MES_API_HEADER header; 473 uint64_t process_context_addr; 474 uint32_t gds_base; 475 uint32_t gds_size; 476 uint32_t gws_base; 477 uint32_t gws_size; 478 uint32_t oa_mask; 479 struct MES_API_STATUS api_status; 480 }; 481 482 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS]; 483 }; 484 485 union MESAPI__SET_DEBUG_VMID { 486 struct { 487 union MES_API_HEADER header; 488 struct MES_API_STATUS api_status; 489 union { 490 struct { 491 uint32_t use_gds : 1; 492 uint32_t operation : 2; 493 uint32_t reserved : 29; 494 } flags; 495 uint32_t u32All; 496 }; 497 uint32_t reserved; 498 uint32_t debug_vmid; 499 uint64_t process_context_addr; 500 uint64_t page_table_base_addr; 501 uint64_t process_va_start; 502 uint64_t process_va_end; 503 uint32_t gds_base; 504 uint32_t gds_size; 505 uint32_t gws_base; 506 uint32_t gws_size; 507 uint32_t oa_mask; 508 509 /* output addr of the acquired vmid value */ 510 uint64_t output_addr; 511 }; 512 513 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS]; 514 }; 515 516 enum MESAPI_MISC_OPCODE { 517 MESAPI_MISC__WRITE_REG, 518 MESAPI_MISC__INV_GART, 519 MESAPI_MISC__QUERY_STATUS, 520 MESAPI_MISC__READ_REG, 521 MESAPI_MISC__WAIT_REG_MEM, 522 MESAPI_MISC__MAX, 523 }; 524 525 enum { MISC_DATA_MAX_SIZE_IN_DWORDS = 20 }; 526 527 struct WRITE_REG { 528 uint32_t reg_offset; 529 uint32_t reg_value; 530 }; 531 532 struct READ_REG { 533 uint32_t reg_offset; 534 uint64_t buffer_addr; 535 }; 536 537 enum WRM_OPERATION { 538 WRM_OPERATION__WAIT_REG_MEM, 539 WRM_OPERATION__WR_WAIT_WR_REG, 540 WRM_OPERATION__MAX, 541 }; 542 543 struct WAIT_REG_MEM { 544 enum WRM_OPERATION op; 545 uint32_t reference; 546 uint32_t mask; 547 uint32_t reg_offset1; 548 uint32_t reg_offset2; 549 }; 550 551 struct INV_GART { 552 uint64_t inv_range_va_start; 553 uint64_t inv_range_size; 554 }; 555 556 struct QUERY_STATUS { 557 uint32_t context_id; 558 }; 559 560 union MESAPI__MISC { 561 struct { 562 union MES_API_HEADER header; 563 enum MESAPI_MISC_OPCODE opcode; 564 struct MES_API_STATUS api_status; 565 566 union { 567 struct WRITE_REG write_reg; 568 struct INV_GART inv_gart; 569 struct QUERY_STATUS query_status; 570 struct READ_REG read_reg; 571 struct WAIT_REG_MEM wait_reg_mem; 572 uint32_t data[MISC_DATA_MAX_SIZE_IN_DWORDS]; 573 }; 574 }; 575 576 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS]; 577 }; 578 579 union MESAPI__UPDATE_ROOT_PAGE_TABLE { 580 struct { 581 union MES_API_HEADER header; 582 uint64_t page_table_base_addr; 583 uint64_t process_context_addr; 584 struct MES_API_STATUS api_status; 585 }; 586 587 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS]; 588 }; 589 590 union MESAPI_AMD_LOG { 591 struct { 592 union MES_API_HEADER header; 593 uint64_t p_buffer_memory; 594 uint64_t p_buffer_size_used; 595 struct MES_API_STATUS api_status; 596 }; 597 598 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS]; 599 }; 600 601 #pragma pack(pop) 602 #endif 603