1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #ifndef _DM_PP_INTERFACE_ 24 #define _DM_PP_INTERFACE_ 25 26 #define PP_MAX_CLOCK_LEVELS 8 27 28 struct pp_clock_with_latency { 29 uint32_t clocks_in_khz; 30 uint32_t latency_in_us; 31 }; 32 33 struct pp_clock_levels_with_latency { 34 uint32_t num_levels; 35 struct pp_clock_with_latency data[PP_MAX_CLOCK_LEVELS]; 36 }; 37 38 struct pp_clock_with_voltage { 39 uint32_t clocks_in_khz; 40 uint32_t voltage_in_mv; 41 }; 42 43 struct pp_clock_levels_with_voltage { 44 uint32_t num_levels; 45 struct pp_clock_with_voltage data[PP_MAX_CLOCK_LEVELS]; 46 }; 47 48 #define PP_MAX_WM_SETS 4 49 50 enum pp_wm_set_id { 51 DC_WM_SET_A = 0, 52 DC_WM_SET_B, 53 DC_WM_SET_C, 54 DC_WM_SET_D, 55 DC_WM_SET_INVALID = 0xffff, 56 }; 57 58 struct pp_wm_set_with_dmif_clock_range_soc15 { 59 enum pp_wm_set_id wm_set_id; 60 uint32_t wm_min_dcefclk_in_khz; 61 uint32_t wm_max_dcefclk_in_khz; 62 uint32_t wm_min_memclk_in_khz; 63 uint32_t wm_max_memclk_in_khz; 64 }; 65 66 struct pp_wm_set_with_mcif_clock_range_soc15 { 67 enum pp_wm_set_id wm_set_id; 68 uint32_t wm_min_socclk_in_khz; 69 uint32_t wm_max_socclk_in_khz; 70 uint32_t wm_min_memclk_in_khz; 71 uint32_t wm_max_memclk_in_khz; 72 }; 73 74 struct pp_wm_sets_with_clock_ranges_soc15 { 75 uint32_t num_wm_sets_dmif; 76 uint32_t num_wm_sets_mcif; 77 struct pp_wm_set_with_dmif_clock_range_soc15 78 wm_sets_dmif[PP_MAX_WM_SETS]; 79 struct pp_wm_set_with_mcif_clock_range_soc15 80 wm_sets_mcif[PP_MAX_WM_SETS]; 81 }; 82 83 #endif /* _DM_PP_INTERFACE_ */ 84