1 /* 2 * Copyright 2015 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * 23 */ 24 #ifndef _CGS_COMMON_H 25 #define _CGS_COMMON_H 26 27 #include "amd_shared.h" 28 29 struct cgs_device; 30 31 /** 32 * enum cgs_gpu_mem_type - GPU memory types 33 */ 34 enum cgs_gpu_mem_type { 35 CGS_GPU_MEM_TYPE__VISIBLE_FB, 36 CGS_GPU_MEM_TYPE__INVISIBLE_FB, 37 CGS_GPU_MEM_TYPE__VISIBLE_CONTIG_FB, 38 CGS_GPU_MEM_TYPE__INVISIBLE_CONTIG_FB, 39 CGS_GPU_MEM_TYPE__GART_CACHEABLE, 40 CGS_GPU_MEM_TYPE__GART_WRITECOMBINE 41 }; 42 43 /** 44 * enum cgs_ind_reg - Indirect register spaces 45 */ 46 enum cgs_ind_reg { 47 CGS_IND_REG__MMIO, 48 CGS_IND_REG__PCIE, 49 CGS_IND_REG__SMC, 50 CGS_IND_REG__UVD_CTX, 51 CGS_IND_REG__DIDT, 52 CGS_IND_REG_GC_CAC, 53 CGS_IND_REG__AUDIO_ENDPT 54 }; 55 56 /** 57 * enum cgs_clock - Clocks controlled by the SMU 58 */ 59 enum cgs_clock { 60 CGS_CLOCK__SCLK, 61 CGS_CLOCK__MCLK, 62 CGS_CLOCK__VCLK, 63 CGS_CLOCK__DCLK, 64 CGS_CLOCK__ECLK, 65 CGS_CLOCK__ACLK, 66 CGS_CLOCK__ICLK, 67 /* ... */ 68 }; 69 70 /** 71 * enum cgs_engine - Engines that can be statically power-gated 72 */ 73 enum cgs_engine { 74 CGS_ENGINE__UVD, 75 CGS_ENGINE__VCE, 76 CGS_ENGINE__VP8, 77 CGS_ENGINE__ACP_DMA, 78 CGS_ENGINE__ACP_DSP0, 79 CGS_ENGINE__ACP_DSP1, 80 CGS_ENGINE__ISP, 81 /* ... */ 82 }; 83 84 /** 85 * enum cgs_voltage_planes - Voltage planes for external camera HW 86 */ 87 enum cgs_voltage_planes { 88 CGS_VOLTAGE_PLANE__SENSOR0, 89 CGS_VOLTAGE_PLANE__SENSOR1, 90 /* ... */ 91 }; 92 93 /* 94 * enum cgs_ucode_id - Firmware types for different IPs 95 */ 96 enum cgs_ucode_id { 97 CGS_UCODE_ID_SMU = 0, 98 CGS_UCODE_ID_SMU_SK, 99 CGS_UCODE_ID_SDMA0, 100 CGS_UCODE_ID_SDMA1, 101 CGS_UCODE_ID_CP_CE, 102 CGS_UCODE_ID_CP_PFP, 103 CGS_UCODE_ID_CP_ME, 104 CGS_UCODE_ID_CP_MEC, 105 CGS_UCODE_ID_CP_MEC_JT1, 106 CGS_UCODE_ID_CP_MEC_JT2, 107 CGS_UCODE_ID_GMCON_RENG, 108 CGS_UCODE_ID_RLC_G, 109 CGS_UCODE_ID_STORAGE, 110 CGS_UCODE_ID_MAXIMUM, 111 }; 112 113 enum cgs_system_info_id { 114 CGS_SYSTEM_INFO_ADAPTER_BDF_ID = 1, 115 CGS_SYSTEM_INFO_PCIE_GEN_INFO, 116 CGS_SYSTEM_INFO_PCIE_MLW, 117 CGS_SYSTEM_INFO_PCIE_DEV, 118 CGS_SYSTEM_INFO_PCIE_REV, 119 CGS_SYSTEM_INFO_CG_FLAGS, 120 CGS_SYSTEM_INFO_PG_FLAGS, 121 CGS_SYSTEM_INFO_GFX_CU_INFO, 122 CGS_SYSTEM_INFO_GFX_SE_INFO, 123 CGS_SYSTEM_INFO_PCIE_SUB_SYS_ID, 124 CGS_SYSTEM_INFO_PCIE_SUB_SYS_VENDOR_ID, 125 CGS_SYSTEM_INFO_ID_MAXIMUM, 126 }; 127 128 struct cgs_system_info { 129 uint64_t size; 130 enum cgs_system_info_id info_id; 131 union { 132 void *ptr; 133 uint64_t value; 134 }; 135 uint64_t padding[13]; 136 }; 137 138 /* 139 * enum cgs_resource_type - GPU resource type 140 */ 141 enum cgs_resource_type { 142 CGS_RESOURCE_TYPE_MMIO = 0, 143 CGS_RESOURCE_TYPE_FB, 144 CGS_RESOURCE_TYPE_IO, 145 CGS_RESOURCE_TYPE_DOORBELL, 146 CGS_RESOURCE_TYPE_ROM, 147 }; 148 149 /** 150 * struct cgs_clock_limits - Clock limits 151 * 152 * Clocks are specified in 10KHz units. 153 */ 154 struct cgs_clock_limits { 155 unsigned min; /**< Minimum supported frequency */ 156 unsigned max; /**< Maxumim supported frequency */ 157 unsigned sustainable; /**< Thermally sustainable frequency */ 158 }; 159 160 /** 161 * struct cgs_firmware_info - Firmware information 162 */ 163 struct cgs_firmware_info { 164 uint16_t version; 165 uint16_t fw_version; 166 uint16_t feature_version; 167 uint32_t image_size; 168 uint64_t mc_addr; 169 170 /* only for smc firmware */ 171 uint32_t ucode_start_address; 172 173 void *kptr; 174 bool is_kicker; 175 }; 176 177 struct cgs_mode_info { 178 uint32_t refresh_rate; 179 uint32_t ref_clock; 180 uint32_t vblank_time_us; 181 }; 182 183 struct cgs_display_info { 184 uint32_t display_count; 185 uint32_t active_display_mask; 186 struct cgs_mode_info *mode_info; 187 }; 188 189 typedef unsigned long cgs_handle_t; 190 191 #define CGS_ACPI_METHOD_ATCS 0x53435441 192 #define CGS_ACPI_METHOD_ATIF 0x46495441 193 #define CGS_ACPI_METHOD_ATPX 0x58505441 194 #define CGS_ACPI_FIELD_METHOD_NAME 0x00000001 195 #define CGS_ACPI_FIELD_INPUT_ARGUMENT_COUNT 0x00000002 196 #define CGS_ACPI_MAX_BUFFER_SIZE 256 197 #define CGS_ACPI_TYPE_ANY 0x00 198 #define CGS_ACPI_TYPE_INTEGER 0x01 199 #define CGS_ACPI_TYPE_STRING 0x02 200 #define CGS_ACPI_TYPE_BUFFER 0x03 201 #define CGS_ACPI_TYPE_PACKAGE 0x04 202 203 struct cgs_acpi_method_argument { 204 uint32_t type; 205 uint32_t data_length; 206 union{ 207 uint32_t value; 208 void *pointer; 209 }; 210 }; 211 212 struct cgs_acpi_method_info { 213 uint32_t size; 214 uint32_t field; 215 uint32_t input_count; 216 uint32_t name; 217 struct cgs_acpi_method_argument *pinput_argument; 218 uint32_t output_count; 219 struct cgs_acpi_method_argument *poutput_argument; 220 uint32_t padding[9]; 221 }; 222 223 /** 224 * cgs_gpu_mem_info() - Return information about memory heaps 225 * @cgs_device: opaque device handle 226 * @type: memory type 227 * @mc_start: Start MC address of the heap (output) 228 * @mc_size: MC address space size (output) 229 * @mem_size: maximum amount of memory available for allocation (output) 230 * 231 * This function returns information about memory heaps. The type 232 * parameter is used to select the memory heap. The mc_start and 233 * mc_size for GART heaps may be bigger than the memory available for 234 * allocation. 235 * 236 * mc_start and mc_size are undefined for non-contiguous FB memory 237 * types, since buffers allocated with these types may or may not be 238 * GART mapped. 239 * 240 * Return: 0 on success, -errno otherwise 241 */ 242 typedef int (*cgs_gpu_mem_info_t)(struct cgs_device *cgs_device, enum cgs_gpu_mem_type type, 243 uint64_t *mc_start, uint64_t *mc_size, 244 uint64_t *mem_size); 245 246 /** 247 * cgs_gmap_kmem() - map kernel memory to GART aperture 248 * @cgs_device: opaque device handle 249 * @kmem: pointer to kernel memory 250 * @size: size to map 251 * @min_offset: minimum offset from start of GART aperture 252 * @max_offset: maximum offset from start of GART aperture 253 * @kmem_handle: kernel memory handle (output) 254 * @mcaddr: MC address (output) 255 * 256 * Return: 0 on success, -errno otherwise 257 */ 258 typedef int (*cgs_gmap_kmem_t)(struct cgs_device *cgs_device, void *kmem, uint64_t size, 259 uint64_t min_offset, uint64_t max_offset, 260 cgs_handle_t *kmem_handle, uint64_t *mcaddr); 261 262 /** 263 * cgs_gunmap_kmem() - unmap kernel memory 264 * @cgs_device: opaque device handle 265 * @kmem_handle: kernel memory handle returned by gmap_kmem 266 * 267 * Return: 0 on success, -errno otherwise 268 */ 269 typedef int (*cgs_gunmap_kmem_t)(struct cgs_device *cgs_device, cgs_handle_t kmem_handle); 270 271 /** 272 * cgs_alloc_gpu_mem() - Allocate GPU memory 273 * @cgs_device: opaque device handle 274 * @type: memory type 275 * @size: size in bytes 276 * @align: alignment in bytes 277 * @min_offset: minimum offset from start of heap 278 * @max_offset: maximum offset from start of heap 279 * @handle: memory handle (output) 280 * 281 * The memory types CGS_GPU_MEM_TYPE_*_CONTIG_FB force contiguous 282 * memory allocation. This guarantees that the MC address returned by 283 * cgs_gmap_gpu_mem is not mapped through the GART. The non-contiguous 284 * FB memory types may be GART mapped depending on memory 285 * fragmentation and memory allocator policies. 286 * 287 * If min/max_offset are non-0, the allocation will be forced to 288 * reside between these offsets in its respective memory heap. The 289 * base address that the offset relates to, depends on the memory 290 * type. 291 * 292 * - CGS_GPU_MEM_TYPE__*_CONTIG_FB: FB MC base address 293 * - CGS_GPU_MEM_TYPE__GART_*: GART aperture base address 294 * - others: undefined, don't use with max_offset 295 * 296 * Return: 0 on success, -errno otherwise 297 */ 298 typedef int (*cgs_alloc_gpu_mem_t)(struct cgs_device *cgs_device, enum cgs_gpu_mem_type type, 299 uint64_t size, uint64_t align, 300 uint64_t min_offset, uint64_t max_offset, 301 cgs_handle_t *handle); 302 303 /** 304 * cgs_free_gpu_mem() - Free GPU memory 305 * @cgs_device: opaque device handle 306 * @handle: memory handle returned by alloc or import 307 * 308 * Return: 0 on success, -errno otherwise 309 */ 310 typedef int (*cgs_free_gpu_mem_t)(struct cgs_device *cgs_device, cgs_handle_t handle); 311 312 /** 313 * cgs_gmap_gpu_mem() - GPU-map GPU memory 314 * @cgs_device: opaque device handle 315 * @handle: memory handle returned by alloc or import 316 * @mcaddr: MC address (output) 317 * 318 * Ensures that a buffer is GPU accessible and returns its MC address. 319 * 320 * Return: 0 on success, -errno otherwise 321 */ 322 typedef int (*cgs_gmap_gpu_mem_t)(struct cgs_device *cgs_device, cgs_handle_t handle, 323 uint64_t *mcaddr); 324 325 /** 326 * cgs_gunmap_gpu_mem() - GPU-unmap GPU memory 327 * @cgs_device: opaque device handle 328 * @handle: memory handle returned by alloc or import 329 * 330 * Allows the buffer to be migrated while it's not used by the GPU. 331 * 332 * Return: 0 on success, -errno otherwise 333 */ 334 typedef int (*cgs_gunmap_gpu_mem_t)(struct cgs_device *cgs_device, cgs_handle_t handle); 335 336 /** 337 * cgs_kmap_gpu_mem() - Kernel-map GPU memory 338 * 339 * @cgs_device: opaque device handle 340 * @handle: memory handle returned by alloc or import 341 * @map: Kernel virtual address the memory was mapped to (output) 342 * 343 * Return: 0 on success, -errno otherwise 344 */ 345 typedef int (*cgs_kmap_gpu_mem_t)(struct cgs_device *cgs_device, cgs_handle_t handle, 346 void **map); 347 348 /** 349 * cgs_kunmap_gpu_mem() - Kernel-unmap GPU memory 350 * @cgs_device: opaque device handle 351 * @handle: memory handle returned by alloc or import 352 * 353 * Return: 0 on success, -errno otherwise 354 */ 355 typedef int (*cgs_kunmap_gpu_mem_t)(struct cgs_device *cgs_device, cgs_handle_t handle); 356 357 /** 358 * cgs_read_register() - Read an MMIO register 359 * @cgs_device: opaque device handle 360 * @offset: register offset 361 * 362 * Return: register value 363 */ 364 typedef uint32_t (*cgs_read_register_t)(struct cgs_device *cgs_device, unsigned offset); 365 366 /** 367 * cgs_write_register() - Write an MMIO register 368 * @cgs_device: opaque device handle 369 * @offset: register offset 370 * @value: register value 371 */ 372 typedef void (*cgs_write_register_t)(struct cgs_device *cgs_device, unsigned offset, 373 uint32_t value); 374 375 /** 376 * cgs_read_ind_register() - Read an indirect register 377 * @cgs_device: opaque device handle 378 * @offset: register offset 379 * 380 * Return: register value 381 */ 382 typedef uint32_t (*cgs_read_ind_register_t)(struct cgs_device *cgs_device, enum cgs_ind_reg space, 383 unsigned index); 384 385 /** 386 * cgs_write_ind_register() - Write an indirect register 387 * @cgs_device: opaque device handle 388 * @offset: register offset 389 * @value: register value 390 */ 391 typedef void (*cgs_write_ind_register_t)(struct cgs_device *cgs_device, enum cgs_ind_reg space, 392 unsigned index, uint32_t value); 393 394 /** 395 * cgs_read_pci_config_byte() - Read byte from PCI configuration space 396 * @cgs_device: opaque device handle 397 * @addr: address 398 * 399 * Return: Value read 400 */ 401 typedef uint8_t (*cgs_read_pci_config_byte_t)(struct cgs_device *cgs_device, unsigned addr); 402 403 /** 404 * cgs_read_pci_config_word() - Read word from PCI configuration space 405 * @cgs_device: opaque device handle 406 * @addr: address, must be word-aligned 407 * 408 * Return: Value read 409 */ 410 typedef uint16_t (*cgs_read_pci_config_word_t)(struct cgs_device *cgs_device, unsigned addr); 411 412 /** 413 * cgs_read_pci_config_dword() - Read dword from PCI configuration space 414 * @cgs_device: opaque device handle 415 * @addr: address, must be dword-aligned 416 * 417 * Return: Value read 418 */ 419 typedef uint32_t (*cgs_read_pci_config_dword_t)(struct cgs_device *cgs_device, 420 unsigned addr); 421 422 /** 423 * cgs_write_pci_config_byte() - Write byte to PCI configuration space 424 * @cgs_device: opaque device handle 425 * @addr: address 426 * @value: value to write 427 */ 428 typedef void (*cgs_write_pci_config_byte_t)(struct cgs_device *cgs_device, unsigned addr, 429 uint8_t value); 430 431 /** 432 * cgs_write_pci_config_word() - Write byte to PCI configuration space 433 * @cgs_device: opaque device handle 434 * @addr: address, must be word-aligned 435 * @value: value to write 436 */ 437 typedef void (*cgs_write_pci_config_word_t)(struct cgs_device *cgs_device, unsigned addr, 438 uint16_t value); 439 440 /** 441 * cgs_write_pci_config_dword() - Write byte to PCI configuration space 442 * @cgs_device: opaque device handle 443 * @addr: address, must be dword-aligned 444 * @value: value to write 445 */ 446 typedef void (*cgs_write_pci_config_dword_t)(struct cgs_device *cgs_device, unsigned addr, 447 uint32_t value); 448 449 450 /** 451 * cgs_get_pci_resource() - provide access to a device resource (PCI BAR) 452 * @cgs_device: opaque device handle 453 * @resource_type: Type of Resource (MMIO, IO, ROM, FB, DOORBELL) 454 * @size: size of the region 455 * @offset: offset from the start of the region 456 * @resource_base: base address (not including offset) returned 457 * 458 * Return: 0 on success, -errno otherwise 459 */ 460 typedef int (*cgs_get_pci_resource_t)(struct cgs_device *cgs_device, 461 enum cgs_resource_type resource_type, 462 uint64_t size, 463 uint64_t offset, 464 uint64_t *resource_base); 465 466 /** 467 * cgs_atom_get_data_table() - Get a pointer to an ATOM BIOS data table 468 * @cgs_device: opaque device handle 469 * @table: data table index 470 * @size: size of the table (output, may be NULL) 471 * @frev: table format revision (output, may be NULL) 472 * @crev: table content revision (output, may be NULL) 473 * 474 * Return: Pointer to start of the table, or NULL on failure 475 */ 476 typedef const void *(*cgs_atom_get_data_table_t)( 477 struct cgs_device *cgs_device, unsigned table, 478 uint16_t *size, uint8_t *frev, uint8_t *crev); 479 480 /** 481 * cgs_atom_get_cmd_table_revs() - Get ATOM BIOS command table revisions 482 * @cgs_device: opaque device handle 483 * @table: data table index 484 * @frev: table format revision (output, may be NULL) 485 * @crev: table content revision (output, may be NULL) 486 * 487 * Return: 0 on success, -errno otherwise 488 */ 489 typedef int (*cgs_atom_get_cmd_table_revs_t)(struct cgs_device *cgs_device, unsigned table, 490 uint8_t *frev, uint8_t *crev); 491 492 /** 493 * cgs_atom_exec_cmd_table() - Execute an ATOM BIOS command table 494 * @cgs_device: opaque device handle 495 * @table: command table index 496 * @args: arguments 497 * 498 * Return: 0 on success, -errno otherwise 499 */ 500 typedef int (*cgs_atom_exec_cmd_table_t)(struct cgs_device *cgs_device, 501 unsigned table, void *args); 502 503 /** 504 * cgs_create_pm_request() - Create a power management request 505 * @cgs_device: opaque device handle 506 * @request: handle of created PM request (output) 507 * 508 * Return: 0 on success, -errno otherwise 509 */ 510 typedef int (*cgs_create_pm_request_t)(struct cgs_device *cgs_device, cgs_handle_t *request); 511 512 /** 513 * cgs_destroy_pm_request() - Destroy a power management request 514 * @cgs_device: opaque device handle 515 * @request: handle of created PM request 516 * 517 * Return: 0 on success, -errno otherwise 518 */ 519 typedef int (*cgs_destroy_pm_request_t)(struct cgs_device *cgs_device, cgs_handle_t request); 520 521 /** 522 * cgs_set_pm_request() - Activate or deactiveate a PM request 523 * @cgs_device: opaque device handle 524 * @request: PM request handle 525 * @active: 0 = deactivate, non-0 = activate 526 * 527 * While a PM request is active, its minimum clock requests are taken 528 * into account as the requested engines are powered up. When the 529 * request is inactive, the engines may be powered down and clocks may 530 * be lower, depending on other PM requests by other driver 531 * components. 532 * 533 * Return: 0 on success, -errno otherwise 534 */ 535 typedef int (*cgs_set_pm_request_t)(struct cgs_device *cgs_device, cgs_handle_t request, 536 int active); 537 538 /** 539 * cgs_pm_request_clock() - Request a minimum frequency for a specific clock 540 * @cgs_device: opaque device handle 541 * @request: PM request handle 542 * @clock: which clock? 543 * @freq: requested min. frequency in 10KHz units (0 to clear request) 544 * 545 * Return: 0 on success, -errno otherwise 546 */ 547 typedef int (*cgs_pm_request_clock_t)(struct cgs_device *cgs_device, cgs_handle_t request, 548 enum cgs_clock clock, unsigned freq); 549 550 /** 551 * cgs_pm_request_engine() - Request an engine to be powered up 552 * @cgs_device: opaque device handle 553 * @request: PM request handle 554 * @engine: which engine? 555 * @powered: 0 = powered down, non-0 = powered up 556 * 557 * Return: 0 on success, -errno otherwise 558 */ 559 typedef int (*cgs_pm_request_engine_t)(struct cgs_device *cgs_device, cgs_handle_t request, 560 enum cgs_engine engine, int powered); 561 562 /** 563 * cgs_pm_query_clock_limits() - Query clock frequency limits 564 * @cgs_device: opaque device handle 565 * @clock: which clock? 566 * @limits: clock limits 567 * 568 * Return: 0 on success, -errno otherwise 569 */ 570 typedef int (*cgs_pm_query_clock_limits_t)(struct cgs_device *cgs_device, 571 enum cgs_clock clock, 572 struct cgs_clock_limits *limits); 573 574 /** 575 * cgs_set_camera_voltages() - Apply specific voltages to PMIC voltage planes 576 * @cgs_device: opaque device handle 577 * @mask: bitmask of voltages to change (1<<CGS_VOLTAGE_PLANE__xyz|...) 578 * @voltages: pointer to array of voltage values in 1mV units 579 * 580 * Return: 0 on success, -errno otherwise 581 */ 582 typedef int (*cgs_set_camera_voltages_t)(struct cgs_device *cgs_device, uint32_t mask, 583 const uint32_t *voltages); 584 /** 585 * cgs_get_firmware_info - Get the firmware information from core driver 586 * @cgs_device: opaque device handle 587 * @type: the firmware type 588 * @info: returend firmware information 589 * 590 * Return: 0 on success, -errno otherwise 591 */ 592 typedef int (*cgs_get_firmware_info)(struct cgs_device *cgs_device, 593 enum cgs_ucode_id type, 594 struct cgs_firmware_info *info); 595 596 typedef int (*cgs_rel_firmware)(struct cgs_device *cgs_device, 597 enum cgs_ucode_id type); 598 599 typedef int(*cgs_set_powergating_state)(struct cgs_device *cgs_device, 600 enum amd_ip_block_type block_type, 601 enum amd_powergating_state state); 602 603 typedef int(*cgs_set_clockgating_state)(struct cgs_device *cgs_device, 604 enum amd_ip_block_type block_type, 605 enum amd_clockgating_state state); 606 607 typedef int(*cgs_get_active_displays_info)( 608 struct cgs_device *cgs_device, 609 struct cgs_display_info *info); 610 611 typedef int (*cgs_notify_dpm_enabled)(struct cgs_device *cgs_device, bool enabled); 612 613 typedef int (*cgs_call_acpi_method)(struct cgs_device *cgs_device, 614 uint32_t acpi_method, 615 uint32_t acpi_function, 616 void *pinput, void *poutput, 617 uint32_t output_count, 618 uint32_t input_size, 619 uint32_t output_size); 620 621 typedef int (*cgs_query_system_info)(struct cgs_device *cgs_device, 622 struct cgs_system_info *sys_info); 623 624 typedef int (*cgs_is_virtualization_enabled_t)(void *cgs_device); 625 626 typedef int (*cgs_enter_safe_mode)(struct cgs_device *cgs_device, bool en); 627 628 struct cgs_ops { 629 /* memory management calls (similar to KFD interface) */ 630 cgs_gpu_mem_info_t gpu_mem_info; 631 cgs_gmap_kmem_t gmap_kmem; 632 cgs_gunmap_kmem_t gunmap_kmem; 633 cgs_alloc_gpu_mem_t alloc_gpu_mem; 634 cgs_free_gpu_mem_t free_gpu_mem; 635 cgs_gmap_gpu_mem_t gmap_gpu_mem; 636 cgs_gunmap_gpu_mem_t gunmap_gpu_mem; 637 cgs_kmap_gpu_mem_t kmap_gpu_mem; 638 cgs_kunmap_gpu_mem_t kunmap_gpu_mem; 639 /* MMIO access */ 640 cgs_read_register_t read_register; 641 cgs_write_register_t write_register; 642 cgs_read_ind_register_t read_ind_register; 643 cgs_write_ind_register_t write_ind_register; 644 /* PCI configuration space access */ 645 cgs_read_pci_config_byte_t read_pci_config_byte; 646 cgs_read_pci_config_word_t read_pci_config_word; 647 cgs_read_pci_config_dword_t read_pci_config_dword; 648 cgs_write_pci_config_byte_t write_pci_config_byte; 649 cgs_write_pci_config_word_t write_pci_config_word; 650 cgs_write_pci_config_dword_t write_pci_config_dword; 651 /* PCI resources */ 652 cgs_get_pci_resource_t get_pci_resource; 653 /* ATOM BIOS */ 654 cgs_atom_get_data_table_t atom_get_data_table; 655 cgs_atom_get_cmd_table_revs_t atom_get_cmd_table_revs; 656 cgs_atom_exec_cmd_table_t atom_exec_cmd_table; 657 /* Power management */ 658 cgs_create_pm_request_t create_pm_request; 659 cgs_destroy_pm_request_t destroy_pm_request; 660 cgs_set_pm_request_t set_pm_request; 661 cgs_pm_request_clock_t pm_request_clock; 662 cgs_pm_request_engine_t pm_request_engine; 663 cgs_pm_query_clock_limits_t pm_query_clock_limits; 664 cgs_set_camera_voltages_t set_camera_voltages; 665 /* Firmware Info */ 666 cgs_get_firmware_info get_firmware_info; 667 cgs_rel_firmware rel_firmware; 668 /* cg pg interface*/ 669 cgs_set_powergating_state set_powergating_state; 670 cgs_set_clockgating_state set_clockgating_state; 671 /* display manager */ 672 cgs_get_active_displays_info get_active_displays_info; 673 /* notify dpm enabled */ 674 cgs_notify_dpm_enabled notify_dpm_enabled; 675 /* ACPI */ 676 cgs_call_acpi_method call_acpi_method; 677 /* get system info */ 678 cgs_query_system_info query_system_info; 679 cgs_is_virtualization_enabled_t is_virtualization_enabled; 680 cgs_enter_safe_mode enter_safe_mode; 681 }; 682 683 struct cgs_os_ops; /* To be define in OS-specific CGS header */ 684 685 struct cgs_device 686 { 687 const struct cgs_ops *ops; 688 const struct cgs_os_ops *os_ops; 689 /* to be embedded at the start of driver private structure */ 690 }; 691 692 /* Convenience macros that make CGS indirect function calls look like 693 * normal function calls */ 694 #define CGS_CALL(func,dev,...) \ 695 (((struct cgs_device *)dev)->ops->func(dev, ##__VA_ARGS__)) 696 #define CGS_OS_CALL(func,dev,...) \ 697 (((struct cgs_device *)dev)->os_ops->func(dev, ##__VA_ARGS__)) 698 699 #define cgs_gpu_mem_info(dev,type,mc_start,mc_size,mem_size) \ 700 CGS_CALL(gpu_mem_info,dev,type,mc_start,mc_size,mem_size) 701 #define cgs_gmap_kmem(dev,kmem,size,min_off,max_off,kmem_handle,mcaddr) \ 702 CGS_CALL(gmap_kmem,dev,kmem,size,min_off,max_off,kmem_handle,mcaddr) 703 #define cgs_gunmap_kmem(dev,kmem_handle) \ 704 CGS_CALL(gunmap_kmem,dev,keme_handle) 705 #define cgs_alloc_gpu_mem(dev,type,size,align,min_off,max_off,handle) \ 706 CGS_CALL(alloc_gpu_mem,dev,type,size,align,min_off,max_off,handle) 707 #define cgs_free_gpu_mem(dev,handle) \ 708 CGS_CALL(free_gpu_mem,dev,handle) 709 #define cgs_gmap_gpu_mem(dev,handle,mcaddr) \ 710 CGS_CALL(gmap_gpu_mem,dev,handle,mcaddr) 711 #define cgs_gunmap_gpu_mem(dev,handle) \ 712 CGS_CALL(gunmap_gpu_mem,dev,handle) 713 #define cgs_kmap_gpu_mem(dev,handle,map) \ 714 CGS_CALL(kmap_gpu_mem,dev,handle,map) 715 #define cgs_kunmap_gpu_mem(dev,handle) \ 716 CGS_CALL(kunmap_gpu_mem,dev,handle) 717 718 #define cgs_read_register(dev,offset) \ 719 CGS_CALL(read_register,dev,offset) 720 #define cgs_write_register(dev,offset,value) \ 721 CGS_CALL(write_register,dev,offset,value) 722 #define cgs_read_ind_register(dev,space,index) \ 723 CGS_CALL(read_ind_register,dev,space,index) 724 #define cgs_write_ind_register(dev,space,index,value) \ 725 CGS_CALL(write_ind_register,dev,space,index,value) 726 727 #define cgs_read_pci_config_byte(dev,addr) \ 728 CGS_CALL(read_pci_config_byte,dev,addr) 729 #define cgs_read_pci_config_word(dev,addr) \ 730 CGS_CALL(read_pci_config_word,dev,addr) 731 #define cgs_read_pci_config_dword(dev,addr) \ 732 CGS_CALL(read_pci_config_dword,dev,addr) 733 #define cgs_write_pci_config_byte(dev,addr,value) \ 734 CGS_CALL(write_pci_config_byte,dev,addr,value) 735 #define cgs_write_pci_config_word(dev,addr,value) \ 736 CGS_CALL(write_pci_config_word,dev,addr,value) 737 #define cgs_write_pci_config_dword(dev,addr,value) \ 738 CGS_CALL(write_pci_config_dword,dev,addr,value) 739 740 #define cgs_atom_get_data_table(dev,table,size,frev,crev) \ 741 CGS_CALL(atom_get_data_table,dev,table,size,frev,crev) 742 #define cgs_atom_get_cmd_table_revs(dev,table,frev,crev) \ 743 CGS_CALL(atom_get_cmd_table_revs,dev,table,frev,crev) 744 #define cgs_atom_exec_cmd_table(dev,table,args) \ 745 CGS_CALL(atom_exec_cmd_table,dev,table,args) 746 747 #define cgs_create_pm_request(dev,request) \ 748 CGS_CALL(create_pm_request,dev,request) 749 #define cgs_destroy_pm_request(dev,request) \ 750 CGS_CALL(destroy_pm_request,dev,request) 751 #define cgs_set_pm_request(dev,request,active) \ 752 CGS_CALL(set_pm_request,dev,request,active) 753 #define cgs_pm_request_clock(dev,request,clock,freq) \ 754 CGS_CALL(pm_request_clock,dev,request,clock,freq) 755 #define cgs_pm_request_engine(dev,request,engine,powered) \ 756 CGS_CALL(pm_request_engine,dev,request,engine,powered) 757 #define cgs_pm_query_clock_limits(dev,clock,limits) \ 758 CGS_CALL(pm_query_clock_limits,dev,clock,limits) 759 #define cgs_set_camera_voltages(dev,mask,voltages) \ 760 CGS_CALL(set_camera_voltages,dev,mask,voltages) 761 #define cgs_get_firmware_info(dev, type, info) \ 762 CGS_CALL(get_firmware_info, dev, type, info) 763 #define cgs_rel_firmware(dev, type) \ 764 CGS_CALL(rel_firmware, dev, type) 765 #define cgs_set_powergating_state(dev, block_type, state) \ 766 CGS_CALL(set_powergating_state, dev, block_type, state) 767 #define cgs_set_clockgating_state(dev, block_type, state) \ 768 CGS_CALL(set_clockgating_state, dev, block_type, state) 769 #define cgs_notify_dpm_enabled(dev, enabled) \ 770 CGS_CALL(notify_dpm_enabled, dev, enabled) 771 772 #define cgs_get_active_displays_info(dev, info) \ 773 CGS_CALL(get_active_displays_info, dev, info) 774 775 #define cgs_call_acpi_method(dev, acpi_method, acpi_function, pintput, poutput, output_count, input_size, output_size) \ 776 CGS_CALL(call_acpi_method, dev, acpi_method, acpi_function, pintput, poutput, output_count, input_size, output_size) 777 #define cgs_query_system_info(dev, sys_info) \ 778 CGS_CALL(query_system_info, dev, sys_info) 779 #define cgs_get_pci_resource(cgs_device, resource_type, size, offset, \ 780 resource_base) \ 781 CGS_CALL(get_pci_resource, cgs_device, resource_type, size, offset, \ 782 resource_base) 783 784 #define cgs_is_virtualization_enabled(cgs_device) \ 785 CGS_CALL(is_virtualization_enabled, cgs_device) 786 787 #define cgs_enter_safe_mode(cgs_device, en) \ 788 CGS_CALL(enter_safe_mode, cgs_device, en) 789 790 #endif /* _CGS_COMMON_H */ 791