1 /* 2 * Copyright 2015 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * 23 */ 24 #ifndef _CGS_COMMON_H 25 #define _CGS_COMMON_H 26 27 #include "amd_shared.h" 28 29 struct cgs_device; 30 31 /** 32 * enum cgs_gpu_mem_type - GPU memory types 33 */ 34 enum cgs_gpu_mem_type { 35 CGS_GPU_MEM_TYPE__VISIBLE_FB, 36 CGS_GPU_MEM_TYPE__INVISIBLE_FB, 37 CGS_GPU_MEM_TYPE__VISIBLE_CONTIG_FB, 38 CGS_GPU_MEM_TYPE__INVISIBLE_CONTIG_FB, 39 CGS_GPU_MEM_TYPE__GART_CACHEABLE, 40 CGS_GPU_MEM_TYPE__GART_WRITECOMBINE 41 }; 42 43 /** 44 * enum cgs_ind_reg - Indirect register spaces 45 */ 46 enum cgs_ind_reg { 47 CGS_IND_REG__MMIO, 48 CGS_IND_REG__PCIE, 49 CGS_IND_REG__SMC, 50 CGS_IND_REG__UVD_CTX, 51 CGS_IND_REG__DIDT, 52 CGS_IND_REG_GC_CAC, 53 CGS_IND_REG__AUDIO_ENDPT 54 }; 55 56 /** 57 * enum cgs_clock - Clocks controlled by the SMU 58 */ 59 enum cgs_clock { 60 CGS_CLOCK__SCLK, 61 CGS_CLOCK__MCLK, 62 CGS_CLOCK__VCLK, 63 CGS_CLOCK__DCLK, 64 CGS_CLOCK__ECLK, 65 CGS_CLOCK__ACLK, 66 CGS_CLOCK__ICLK, 67 /* ... */ 68 }; 69 70 /** 71 * enum cgs_engine - Engines that can be statically power-gated 72 */ 73 enum cgs_engine { 74 CGS_ENGINE__UVD, 75 CGS_ENGINE__VCE, 76 CGS_ENGINE__VP8, 77 CGS_ENGINE__ACP_DMA, 78 CGS_ENGINE__ACP_DSP0, 79 CGS_ENGINE__ACP_DSP1, 80 CGS_ENGINE__ISP, 81 /* ... */ 82 }; 83 84 /** 85 * enum cgs_voltage_planes - Voltage planes for external camera HW 86 */ 87 enum cgs_voltage_planes { 88 CGS_VOLTAGE_PLANE__SENSOR0, 89 CGS_VOLTAGE_PLANE__SENSOR1, 90 /* ... */ 91 }; 92 93 /* 94 * enum cgs_ucode_id - Firmware types for different IPs 95 */ 96 enum cgs_ucode_id { 97 CGS_UCODE_ID_SMU = 0, 98 CGS_UCODE_ID_SMU_SK, 99 CGS_UCODE_ID_SDMA0, 100 CGS_UCODE_ID_SDMA1, 101 CGS_UCODE_ID_CP_CE, 102 CGS_UCODE_ID_CP_PFP, 103 CGS_UCODE_ID_CP_ME, 104 CGS_UCODE_ID_CP_MEC, 105 CGS_UCODE_ID_CP_MEC_JT1, 106 CGS_UCODE_ID_CP_MEC_JT2, 107 CGS_UCODE_ID_GMCON_RENG, 108 CGS_UCODE_ID_RLC_G, 109 CGS_UCODE_ID_STORAGE, 110 CGS_UCODE_ID_MAXIMUM, 111 }; 112 113 enum cgs_system_info_id { 114 CGS_SYSTEM_INFO_ADAPTER_BDF_ID = 1, 115 CGS_SYSTEM_INFO_PCIE_GEN_INFO, 116 CGS_SYSTEM_INFO_PCIE_MLW, 117 CGS_SYSTEM_INFO_PCIE_DEV, 118 CGS_SYSTEM_INFO_PCIE_REV, 119 CGS_SYSTEM_INFO_CG_FLAGS, 120 CGS_SYSTEM_INFO_PG_FLAGS, 121 CGS_SYSTEM_INFO_GFX_CU_INFO, 122 CGS_SYSTEM_INFO_GFX_SE_INFO, 123 CGS_SYSTEM_INFO_PCIE_SUB_SYS_ID, 124 CGS_SYSTEM_INFO_PCIE_SUB_SYS_VENDOR_ID, 125 CGS_SYSTEM_INFO_ID_MAXIMUM, 126 }; 127 128 struct cgs_system_info { 129 uint64_t size; 130 enum cgs_system_info_id info_id; 131 union { 132 void *ptr; 133 uint64_t value; 134 }; 135 uint64_t padding[13]; 136 }; 137 138 /* 139 * enum cgs_resource_type - GPU resource type 140 */ 141 enum cgs_resource_type { 142 CGS_RESOURCE_TYPE_MMIO = 0, 143 CGS_RESOURCE_TYPE_FB, 144 CGS_RESOURCE_TYPE_IO, 145 CGS_RESOURCE_TYPE_DOORBELL, 146 CGS_RESOURCE_TYPE_ROM, 147 }; 148 149 /** 150 * struct cgs_clock_limits - Clock limits 151 * 152 * Clocks are specified in 10KHz units. 153 */ 154 struct cgs_clock_limits { 155 unsigned min; /**< Minimum supported frequency */ 156 unsigned max; /**< Maxumim supported frequency */ 157 unsigned sustainable; /**< Thermally sustainable frequency */ 158 }; 159 160 /** 161 * struct cgs_firmware_info - Firmware information 162 */ 163 struct cgs_firmware_info { 164 uint16_t version; 165 uint16_t fw_version; 166 uint16_t feature_version; 167 uint32_t image_size; 168 uint64_t mc_addr; 169 170 /* only for smc firmware */ 171 uint32_t ucode_start_address; 172 173 void *kptr; 174 }; 175 176 struct cgs_mode_info { 177 uint32_t refresh_rate; 178 uint32_t ref_clock; 179 uint32_t vblank_time_us; 180 }; 181 182 struct cgs_display_info { 183 uint32_t display_count; 184 uint32_t active_display_mask; 185 struct cgs_mode_info *mode_info; 186 }; 187 188 typedef unsigned long cgs_handle_t; 189 190 #define CGS_ACPI_METHOD_ATCS 0x53435441 191 #define CGS_ACPI_METHOD_ATIF 0x46495441 192 #define CGS_ACPI_METHOD_ATPX 0x58505441 193 #define CGS_ACPI_FIELD_METHOD_NAME 0x00000001 194 #define CGS_ACPI_FIELD_INPUT_ARGUMENT_COUNT 0x00000002 195 #define CGS_ACPI_MAX_BUFFER_SIZE 256 196 #define CGS_ACPI_TYPE_ANY 0x00 197 #define CGS_ACPI_TYPE_INTEGER 0x01 198 #define CGS_ACPI_TYPE_STRING 0x02 199 #define CGS_ACPI_TYPE_BUFFER 0x03 200 #define CGS_ACPI_TYPE_PACKAGE 0x04 201 202 struct cgs_acpi_method_argument { 203 uint32_t type; 204 uint32_t data_length; 205 union{ 206 uint32_t value; 207 void *pointer; 208 }; 209 }; 210 211 struct cgs_acpi_method_info { 212 uint32_t size; 213 uint32_t field; 214 uint32_t input_count; 215 uint32_t name; 216 struct cgs_acpi_method_argument *pinput_argument; 217 uint32_t output_count; 218 struct cgs_acpi_method_argument *poutput_argument; 219 uint32_t padding[9]; 220 }; 221 222 /** 223 * cgs_gpu_mem_info() - Return information about memory heaps 224 * @cgs_device: opaque device handle 225 * @type: memory type 226 * @mc_start: Start MC address of the heap (output) 227 * @mc_size: MC address space size (output) 228 * @mem_size: maximum amount of memory available for allocation (output) 229 * 230 * This function returns information about memory heaps. The type 231 * parameter is used to select the memory heap. The mc_start and 232 * mc_size for GART heaps may be bigger than the memory available for 233 * allocation. 234 * 235 * mc_start and mc_size are undefined for non-contiguous FB memory 236 * types, since buffers allocated with these types may or may not be 237 * GART mapped. 238 * 239 * Return: 0 on success, -errno otherwise 240 */ 241 typedef int (*cgs_gpu_mem_info_t)(struct cgs_device *cgs_device, enum cgs_gpu_mem_type type, 242 uint64_t *mc_start, uint64_t *mc_size, 243 uint64_t *mem_size); 244 245 /** 246 * cgs_gmap_kmem() - map kernel memory to GART aperture 247 * @cgs_device: opaque device handle 248 * @kmem: pointer to kernel memory 249 * @size: size to map 250 * @min_offset: minimum offset from start of GART aperture 251 * @max_offset: maximum offset from start of GART aperture 252 * @kmem_handle: kernel memory handle (output) 253 * @mcaddr: MC address (output) 254 * 255 * Return: 0 on success, -errno otherwise 256 */ 257 typedef int (*cgs_gmap_kmem_t)(struct cgs_device *cgs_device, void *kmem, uint64_t size, 258 uint64_t min_offset, uint64_t max_offset, 259 cgs_handle_t *kmem_handle, uint64_t *mcaddr); 260 261 /** 262 * cgs_gunmap_kmem() - unmap kernel memory 263 * @cgs_device: opaque device handle 264 * @kmem_handle: kernel memory handle returned by gmap_kmem 265 * 266 * Return: 0 on success, -errno otherwise 267 */ 268 typedef int (*cgs_gunmap_kmem_t)(struct cgs_device *cgs_device, cgs_handle_t kmem_handle); 269 270 /** 271 * cgs_alloc_gpu_mem() - Allocate GPU memory 272 * @cgs_device: opaque device handle 273 * @type: memory type 274 * @size: size in bytes 275 * @align: alignment in bytes 276 * @min_offset: minimum offset from start of heap 277 * @max_offset: maximum offset from start of heap 278 * @handle: memory handle (output) 279 * 280 * The memory types CGS_GPU_MEM_TYPE_*_CONTIG_FB force contiguous 281 * memory allocation. This guarantees that the MC address returned by 282 * cgs_gmap_gpu_mem is not mapped through the GART. The non-contiguous 283 * FB memory types may be GART mapped depending on memory 284 * fragmentation and memory allocator policies. 285 * 286 * If min/max_offset are non-0, the allocation will be forced to 287 * reside between these offsets in its respective memory heap. The 288 * base address that the offset relates to, depends on the memory 289 * type. 290 * 291 * - CGS_GPU_MEM_TYPE__*_CONTIG_FB: FB MC base address 292 * - CGS_GPU_MEM_TYPE__GART_*: GART aperture base address 293 * - others: undefined, don't use with max_offset 294 * 295 * Return: 0 on success, -errno otherwise 296 */ 297 typedef int (*cgs_alloc_gpu_mem_t)(struct cgs_device *cgs_device, enum cgs_gpu_mem_type type, 298 uint64_t size, uint64_t align, 299 uint64_t min_offset, uint64_t max_offset, 300 cgs_handle_t *handle); 301 302 /** 303 * cgs_free_gpu_mem() - Free GPU memory 304 * @cgs_device: opaque device handle 305 * @handle: memory handle returned by alloc or import 306 * 307 * Return: 0 on success, -errno otherwise 308 */ 309 typedef int (*cgs_free_gpu_mem_t)(struct cgs_device *cgs_device, cgs_handle_t handle); 310 311 /** 312 * cgs_gmap_gpu_mem() - GPU-map GPU memory 313 * @cgs_device: opaque device handle 314 * @handle: memory handle returned by alloc or import 315 * @mcaddr: MC address (output) 316 * 317 * Ensures that a buffer is GPU accessible and returns its MC address. 318 * 319 * Return: 0 on success, -errno otherwise 320 */ 321 typedef int (*cgs_gmap_gpu_mem_t)(struct cgs_device *cgs_device, cgs_handle_t handle, 322 uint64_t *mcaddr); 323 324 /** 325 * cgs_gunmap_gpu_mem() - GPU-unmap GPU memory 326 * @cgs_device: opaque device handle 327 * @handle: memory handle returned by alloc or import 328 * 329 * Allows the buffer to be migrated while it's not used by the GPU. 330 * 331 * Return: 0 on success, -errno otherwise 332 */ 333 typedef int (*cgs_gunmap_gpu_mem_t)(struct cgs_device *cgs_device, cgs_handle_t handle); 334 335 /** 336 * cgs_kmap_gpu_mem() - Kernel-map GPU memory 337 * 338 * @cgs_device: opaque device handle 339 * @handle: memory handle returned by alloc or import 340 * @map: Kernel virtual address the memory was mapped to (output) 341 * 342 * Return: 0 on success, -errno otherwise 343 */ 344 typedef int (*cgs_kmap_gpu_mem_t)(struct cgs_device *cgs_device, cgs_handle_t handle, 345 void **map); 346 347 /** 348 * cgs_kunmap_gpu_mem() - Kernel-unmap GPU memory 349 * @cgs_device: opaque device handle 350 * @handle: memory handle returned by alloc or import 351 * 352 * Return: 0 on success, -errno otherwise 353 */ 354 typedef int (*cgs_kunmap_gpu_mem_t)(struct cgs_device *cgs_device, cgs_handle_t handle); 355 356 /** 357 * cgs_read_register() - Read an MMIO register 358 * @cgs_device: opaque device handle 359 * @offset: register offset 360 * 361 * Return: register value 362 */ 363 typedef uint32_t (*cgs_read_register_t)(struct cgs_device *cgs_device, unsigned offset); 364 365 /** 366 * cgs_write_register() - Write an MMIO register 367 * @cgs_device: opaque device handle 368 * @offset: register offset 369 * @value: register value 370 */ 371 typedef void (*cgs_write_register_t)(struct cgs_device *cgs_device, unsigned offset, 372 uint32_t value); 373 374 /** 375 * cgs_read_ind_register() - Read an indirect register 376 * @cgs_device: opaque device handle 377 * @offset: register offset 378 * 379 * Return: register value 380 */ 381 typedef uint32_t (*cgs_read_ind_register_t)(struct cgs_device *cgs_device, enum cgs_ind_reg space, 382 unsigned index); 383 384 /** 385 * cgs_write_ind_register() - Write an indirect register 386 * @cgs_device: opaque device handle 387 * @offset: register offset 388 * @value: register value 389 */ 390 typedef void (*cgs_write_ind_register_t)(struct cgs_device *cgs_device, enum cgs_ind_reg space, 391 unsigned index, uint32_t value); 392 393 /** 394 * cgs_read_pci_config_byte() - Read byte from PCI configuration space 395 * @cgs_device: opaque device handle 396 * @addr: address 397 * 398 * Return: Value read 399 */ 400 typedef uint8_t (*cgs_read_pci_config_byte_t)(struct cgs_device *cgs_device, unsigned addr); 401 402 /** 403 * cgs_read_pci_config_word() - Read word from PCI configuration space 404 * @cgs_device: opaque device handle 405 * @addr: address, must be word-aligned 406 * 407 * Return: Value read 408 */ 409 typedef uint16_t (*cgs_read_pci_config_word_t)(struct cgs_device *cgs_device, unsigned addr); 410 411 /** 412 * cgs_read_pci_config_dword() - Read dword from PCI configuration space 413 * @cgs_device: opaque device handle 414 * @addr: address, must be dword-aligned 415 * 416 * Return: Value read 417 */ 418 typedef uint32_t (*cgs_read_pci_config_dword_t)(struct cgs_device *cgs_device, 419 unsigned addr); 420 421 /** 422 * cgs_write_pci_config_byte() - Write byte to PCI configuration space 423 * @cgs_device: opaque device handle 424 * @addr: address 425 * @value: value to write 426 */ 427 typedef void (*cgs_write_pci_config_byte_t)(struct cgs_device *cgs_device, unsigned addr, 428 uint8_t value); 429 430 /** 431 * cgs_write_pci_config_word() - Write byte to PCI configuration space 432 * @cgs_device: opaque device handle 433 * @addr: address, must be word-aligned 434 * @value: value to write 435 */ 436 typedef void (*cgs_write_pci_config_word_t)(struct cgs_device *cgs_device, unsigned addr, 437 uint16_t value); 438 439 /** 440 * cgs_write_pci_config_dword() - Write byte to PCI configuration space 441 * @cgs_device: opaque device handle 442 * @addr: address, must be dword-aligned 443 * @value: value to write 444 */ 445 typedef void (*cgs_write_pci_config_dword_t)(struct cgs_device *cgs_device, unsigned addr, 446 uint32_t value); 447 448 449 /** 450 * cgs_get_pci_resource() - provide access to a device resource (PCI BAR) 451 * @cgs_device: opaque device handle 452 * @resource_type: Type of Resource (MMIO, IO, ROM, FB, DOORBELL) 453 * @size: size of the region 454 * @offset: offset from the start of the region 455 * @resource_base: base address (not including offset) returned 456 * 457 * Return: 0 on success, -errno otherwise 458 */ 459 typedef int (*cgs_get_pci_resource_t)(struct cgs_device *cgs_device, 460 enum cgs_resource_type resource_type, 461 uint64_t size, 462 uint64_t offset, 463 uint64_t *resource_base); 464 465 /** 466 * cgs_atom_get_data_table() - Get a pointer to an ATOM BIOS data table 467 * @cgs_device: opaque device handle 468 * @table: data table index 469 * @size: size of the table (output, may be NULL) 470 * @frev: table format revision (output, may be NULL) 471 * @crev: table content revision (output, may be NULL) 472 * 473 * Return: Pointer to start of the table, or NULL on failure 474 */ 475 typedef const void *(*cgs_atom_get_data_table_t)( 476 struct cgs_device *cgs_device, unsigned table, 477 uint16_t *size, uint8_t *frev, uint8_t *crev); 478 479 /** 480 * cgs_atom_get_cmd_table_revs() - Get ATOM BIOS command table revisions 481 * @cgs_device: opaque device handle 482 * @table: data table index 483 * @frev: table format revision (output, may be NULL) 484 * @crev: table content revision (output, may be NULL) 485 * 486 * Return: 0 on success, -errno otherwise 487 */ 488 typedef int (*cgs_atom_get_cmd_table_revs_t)(struct cgs_device *cgs_device, unsigned table, 489 uint8_t *frev, uint8_t *crev); 490 491 /** 492 * cgs_atom_exec_cmd_table() - Execute an ATOM BIOS command table 493 * @cgs_device: opaque device handle 494 * @table: command table index 495 * @args: arguments 496 * 497 * Return: 0 on success, -errno otherwise 498 */ 499 typedef int (*cgs_atom_exec_cmd_table_t)(struct cgs_device *cgs_device, 500 unsigned table, void *args); 501 502 /** 503 * cgs_create_pm_request() - Create a power management request 504 * @cgs_device: opaque device handle 505 * @request: handle of created PM request (output) 506 * 507 * Return: 0 on success, -errno otherwise 508 */ 509 typedef int (*cgs_create_pm_request_t)(struct cgs_device *cgs_device, cgs_handle_t *request); 510 511 /** 512 * cgs_destroy_pm_request() - Destroy a power management request 513 * @cgs_device: opaque device handle 514 * @request: handle of created PM request 515 * 516 * Return: 0 on success, -errno otherwise 517 */ 518 typedef int (*cgs_destroy_pm_request_t)(struct cgs_device *cgs_device, cgs_handle_t request); 519 520 /** 521 * cgs_set_pm_request() - Activate or deactiveate a PM request 522 * @cgs_device: opaque device handle 523 * @request: PM request handle 524 * @active: 0 = deactivate, non-0 = activate 525 * 526 * While a PM request is active, its minimum clock requests are taken 527 * into account as the requested engines are powered up. When the 528 * request is inactive, the engines may be powered down and clocks may 529 * be lower, depending on other PM requests by other driver 530 * components. 531 * 532 * Return: 0 on success, -errno otherwise 533 */ 534 typedef int (*cgs_set_pm_request_t)(struct cgs_device *cgs_device, cgs_handle_t request, 535 int active); 536 537 /** 538 * cgs_pm_request_clock() - Request a minimum frequency for a specific clock 539 * @cgs_device: opaque device handle 540 * @request: PM request handle 541 * @clock: which clock? 542 * @freq: requested min. frequency in 10KHz units (0 to clear request) 543 * 544 * Return: 0 on success, -errno otherwise 545 */ 546 typedef int (*cgs_pm_request_clock_t)(struct cgs_device *cgs_device, cgs_handle_t request, 547 enum cgs_clock clock, unsigned freq); 548 549 /** 550 * cgs_pm_request_engine() - Request an engine to be powered up 551 * @cgs_device: opaque device handle 552 * @request: PM request handle 553 * @engine: which engine? 554 * @powered: 0 = powered down, non-0 = powered up 555 * 556 * Return: 0 on success, -errno otherwise 557 */ 558 typedef int (*cgs_pm_request_engine_t)(struct cgs_device *cgs_device, cgs_handle_t request, 559 enum cgs_engine engine, int powered); 560 561 /** 562 * cgs_pm_query_clock_limits() - Query clock frequency limits 563 * @cgs_device: opaque device handle 564 * @clock: which clock? 565 * @limits: clock limits 566 * 567 * Return: 0 on success, -errno otherwise 568 */ 569 typedef int (*cgs_pm_query_clock_limits_t)(struct cgs_device *cgs_device, 570 enum cgs_clock clock, 571 struct cgs_clock_limits *limits); 572 573 /** 574 * cgs_set_camera_voltages() - Apply specific voltages to PMIC voltage planes 575 * @cgs_device: opaque device handle 576 * @mask: bitmask of voltages to change (1<<CGS_VOLTAGE_PLANE__xyz|...) 577 * @voltages: pointer to array of voltage values in 1mV units 578 * 579 * Return: 0 on success, -errno otherwise 580 */ 581 typedef int (*cgs_set_camera_voltages_t)(struct cgs_device *cgs_device, uint32_t mask, 582 const uint32_t *voltages); 583 /** 584 * cgs_get_firmware_info - Get the firmware information from core driver 585 * @cgs_device: opaque device handle 586 * @type: the firmware type 587 * @info: returend firmware information 588 * 589 * Return: 0 on success, -errno otherwise 590 */ 591 typedef int (*cgs_get_firmware_info)(struct cgs_device *cgs_device, 592 enum cgs_ucode_id type, 593 struct cgs_firmware_info *info); 594 595 typedef int (*cgs_rel_firmware)(struct cgs_device *cgs_device, 596 enum cgs_ucode_id type); 597 598 typedef int(*cgs_set_powergating_state)(struct cgs_device *cgs_device, 599 enum amd_ip_block_type block_type, 600 enum amd_powergating_state state); 601 602 typedef int(*cgs_set_clockgating_state)(struct cgs_device *cgs_device, 603 enum amd_ip_block_type block_type, 604 enum amd_clockgating_state state); 605 606 typedef int(*cgs_get_active_displays_info)( 607 struct cgs_device *cgs_device, 608 struct cgs_display_info *info); 609 610 typedef int (*cgs_notify_dpm_enabled)(struct cgs_device *cgs_device, bool enabled); 611 612 typedef int (*cgs_call_acpi_method)(struct cgs_device *cgs_device, 613 uint32_t acpi_method, 614 uint32_t acpi_function, 615 void *pinput, void *poutput, 616 uint32_t output_count, 617 uint32_t input_size, 618 uint32_t output_size); 619 620 typedef int (*cgs_query_system_info)(struct cgs_device *cgs_device, 621 struct cgs_system_info *sys_info); 622 623 typedef int (*cgs_is_virtualization_enabled_t)(void *cgs_device); 624 625 struct cgs_ops { 626 /* memory management calls (similar to KFD interface) */ 627 cgs_gpu_mem_info_t gpu_mem_info; 628 cgs_gmap_kmem_t gmap_kmem; 629 cgs_gunmap_kmem_t gunmap_kmem; 630 cgs_alloc_gpu_mem_t alloc_gpu_mem; 631 cgs_free_gpu_mem_t free_gpu_mem; 632 cgs_gmap_gpu_mem_t gmap_gpu_mem; 633 cgs_gunmap_gpu_mem_t gunmap_gpu_mem; 634 cgs_kmap_gpu_mem_t kmap_gpu_mem; 635 cgs_kunmap_gpu_mem_t kunmap_gpu_mem; 636 /* MMIO access */ 637 cgs_read_register_t read_register; 638 cgs_write_register_t write_register; 639 cgs_read_ind_register_t read_ind_register; 640 cgs_write_ind_register_t write_ind_register; 641 /* PCI configuration space access */ 642 cgs_read_pci_config_byte_t read_pci_config_byte; 643 cgs_read_pci_config_word_t read_pci_config_word; 644 cgs_read_pci_config_dword_t read_pci_config_dword; 645 cgs_write_pci_config_byte_t write_pci_config_byte; 646 cgs_write_pci_config_word_t write_pci_config_word; 647 cgs_write_pci_config_dword_t write_pci_config_dword; 648 /* PCI resources */ 649 cgs_get_pci_resource_t get_pci_resource; 650 /* ATOM BIOS */ 651 cgs_atom_get_data_table_t atom_get_data_table; 652 cgs_atom_get_cmd_table_revs_t atom_get_cmd_table_revs; 653 cgs_atom_exec_cmd_table_t atom_exec_cmd_table; 654 /* Power management */ 655 cgs_create_pm_request_t create_pm_request; 656 cgs_destroy_pm_request_t destroy_pm_request; 657 cgs_set_pm_request_t set_pm_request; 658 cgs_pm_request_clock_t pm_request_clock; 659 cgs_pm_request_engine_t pm_request_engine; 660 cgs_pm_query_clock_limits_t pm_query_clock_limits; 661 cgs_set_camera_voltages_t set_camera_voltages; 662 /* Firmware Info */ 663 cgs_get_firmware_info get_firmware_info; 664 cgs_rel_firmware rel_firmware; 665 /* cg pg interface*/ 666 cgs_set_powergating_state set_powergating_state; 667 cgs_set_clockgating_state set_clockgating_state; 668 /* display manager */ 669 cgs_get_active_displays_info get_active_displays_info; 670 /* notify dpm enabled */ 671 cgs_notify_dpm_enabled notify_dpm_enabled; 672 /* ACPI */ 673 cgs_call_acpi_method call_acpi_method; 674 /* get system info */ 675 cgs_query_system_info query_system_info; 676 cgs_is_virtualization_enabled_t is_virtualization_enabled; 677 }; 678 679 struct cgs_os_ops; /* To be define in OS-specific CGS header */ 680 681 struct cgs_device 682 { 683 const struct cgs_ops *ops; 684 const struct cgs_os_ops *os_ops; 685 /* to be embedded at the start of driver private structure */ 686 }; 687 688 /* Convenience macros that make CGS indirect function calls look like 689 * normal function calls */ 690 #define CGS_CALL(func,dev,...) \ 691 (((struct cgs_device *)dev)->ops->func(dev, ##__VA_ARGS__)) 692 #define CGS_OS_CALL(func,dev,...) \ 693 (((struct cgs_device *)dev)->os_ops->func(dev, ##__VA_ARGS__)) 694 695 #define cgs_gpu_mem_info(dev,type,mc_start,mc_size,mem_size) \ 696 CGS_CALL(gpu_mem_info,dev,type,mc_start,mc_size,mem_size) 697 #define cgs_gmap_kmem(dev,kmem,size,min_off,max_off,kmem_handle,mcaddr) \ 698 CGS_CALL(gmap_kmem,dev,kmem,size,min_off,max_off,kmem_handle,mcaddr) 699 #define cgs_gunmap_kmem(dev,kmem_handle) \ 700 CGS_CALL(gunmap_kmem,dev,keme_handle) 701 #define cgs_alloc_gpu_mem(dev,type,size,align,min_off,max_off,handle) \ 702 CGS_CALL(alloc_gpu_mem,dev,type,size,align,min_off,max_off,handle) 703 #define cgs_free_gpu_mem(dev,handle) \ 704 CGS_CALL(free_gpu_mem,dev,handle) 705 #define cgs_gmap_gpu_mem(dev,handle,mcaddr) \ 706 CGS_CALL(gmap_gpu_mem,dev,handle,mcaddr) 707 #define cgs_gunmap_gpu_mem(dev,handle) \ 708 CGS_CALL(gunmap_gpu_mem,dev,handle) 709 #define cgs_kmap_gpu_mem(dev,handle,map) \ 710 CGS_CALL(kmap_gpu_mem,dev,handle,map) 711 #define cgs_kunmap_gpu_mem(dev,handle) \ 712 CGS_CALL(kunmap_gpu_mem,dev,handle) 713 714 #define cgs_read_register(dev,offset) \ 715 CGS_CALL(read_register,dev,offset) 716 #define cgs_write_register(dev,offset,value) \ 717 CGS_CALL(write_register,dev,offset,value) 718 #define cgs_read_ind_register(dev,space,index) \ 719 CGS_CALL(read_ind_register,dev,space,index) 720 #define cgs_write_ind_register(dev,space,index,value) \ 721 CGS_CALL(write_ind_register,dev,space,index,value) 722 723 #define cgs_read_pci_config_byte(dev,addr) \ 724 CGS_CALL(read_pci_config_byte,dev,addr) 725 #define cgs_read_pci_config_word(dev,addr) \ 726 CGS_CALL(read_pci_config_word,dev,addr) 727 #define cgs_read_pci_config_dword(dev,addr) \ 728 CGS_CALL(read_pci_config_dword,dev,addr) 729 #define cgs_write_pci_config_byte(dev,addr,value) \ 730 CGS_CALL(write_pci_config_byte,dev,addr,value) 731 #define cgs_write_pci_config_word(dev,addr,value) \ 732 CGS_CALL(write_pci_config_word,dev,addr,value) 733 #define cgs_write_pci_config_dword(dev,addr,value) \ 734 CGS_CALL(write_pci_config_dword,dev,addr,value) 735 736 #define cgs_atom_get_data_table(dev,table,size,frev,crev) \ 737 CGS_CALL(atom_get_data_table,dev,table,size,frev,crev) 738 #define cgs_atom_get_cmd_table_revs(dev,table,frev,crev) \ 739 CGS_CALL(atom_get_cmd_table_revs,dev,table,frev,crev) 740 #define cgs_atom_exec_cmd_table(dev,table,args) \ 741 CGS_CALL(atom_exec_cmd_table,dev,table,args) 742 743 #define cgs_create_pm_request(dev,request) \ 744 CGS_CALL(create_pm_request,dev,request) 745 #define cgs_destroy_pm_request(dev,request) \ 746 CGS_CALL(destroy_pm_request,dev,request) 747 #define cgs_set_pm_request(dev,request,active) \ 748 CGS_CALL(set_pm_request,dev,request,active) 749 #define cgs_pm_request_clock(dev,request,clock,freq) \ 750 CGS_CALL(pm_request_clock,dev,request,clock,freq) 751 #define cgs_pm_request_engine(dev,request,engine,powered) \ 752 CGS_CALL(pm_request_engine,dev,request,engine,powered) 753 #define cgs_pm_query_clock_limits(dev,clock,limits) \ 754 CGS_CALL(pm_query_clock_limits,dev,clock,limits) 755 #define cgs_set_camera_voltages(dev,mask,voltages) \ 756 CGS_CALL(set_camera_voltages,dev,mask,voltages) 757 #define cgs_get_firmware_info(dev, type, info) \ 758 CGS_CALL(get_firmware_info, dev, type, info) 759 #define cgs_rel_firmware(dev, type) \ 760 CGS_CALL(rel_firmware, dev, type) 761 #define cgs_set_powergating_state(dev, block_type, state) \ 762 CGS_CALL(set_powergating_state, dev, block_type, state) 763 #define cgs_set_clockgating_state(dev, block_type, state) \ 764 CGS_CALL(set_clockgating_state, dev, block_type, state) 765 #define cgs_notify_dpm_enabled(dev, enabled) \ 766 CGS_CALL(notify_dpm_enabled, dev, enabled) 767 768 #define cgs_get_active_displays_info(dev, info) \ 769 CGS_CALL(get_active_displays_info, dev, info) 770 771 #define cgs_call_acpi_method(dev, acpi_method, acpi_function, pintput, poutput, output_count, input_size, output_size) \ 772 CGS_CALL(call_acpi_method, dev, acpi_method, acpi_function, pintput, poutput, output_count, input_size, output_size) 773 #define cgs_query_system_info(dev, sys_info) \ 774 CGS_CALL(query_system_info, dev, sys_info) 775 #define cgs_get_pci_resource(cgs_device, resource_type, size, offset, \ 776 resource_base) \ 777 CGS_CALL(get_pci_resource, cgs_device, resource_type, size, offset, \ 778 resource_base) 779 780 #define cgs_is_virtualization_enabled(cgs_device) \ 781 CGS_CALL(is_virtualization_enabled, cgs_device) 782 #endif /* _CGS_COMMON_H */ 783