1 /* 2 * Copyright 2015 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * 23 */ 24 #ifndef _CGS_COMMON_H 25 #define _CGS_COMMON_H 26 27 #include "amd_shared.h" 28 29 /** 30 * enum cgs_gpu_mem_type - GPU memory types 31 */ 32 enum cgs_gpu_mem_type { 33 CGS_GPU_MEM_TYPE__VISIBLE_FB, 34 CGS_GPU_MEM_TYPE__INVISIBLE_FB, 35 CGS_GPU_MEM_TYPE__VISIBLE_CONTIG_FB, 36 CGS_GPU_MEM_TYPE__INVISIBLE_CONTIG_FB, 37 CGS_GPU_MEM_TYPE__GART_CACHEABLE, 38 CGS_GPU_MEM_TYPE__GART_WRITECOMBINE 39 }; 40 41 /** 42 * enum cgs_ind_reg - Indirect register spaces 43 */ 44 enum cgs_ind_reg { 45 CGS_IND_REG__MMIO, 46 CGS_IND_REG__PCIE, 47 CGS_IND_REG__SMC, 48 CGS_IND_REG__UVD_CTX, 49 CGS_IND_REG__DIDT, 50 CGS_IND_REG__AUDIO_ENDPT 51 }; 52 53 /** 54 * enum cgs_clock - Clocks controlled by the SMU 55 */ 56 enum cgs_clock { 57 CGS_CLOCK__SCLK, 58 CGS_CLOCK__MCLK, 59 CGS_CLOCK__VCLK, 60 CGS_CLOCK__DCLK, 61 CGS_CLOCK__ECLK, 62 CGS_CLOCK__ACLK, 63 CGS_CLOCK__ICLK, 64 /* ... */ 65 }; 66 67 /** 68 * enum cgs_engine - Engines that can be statically power-gated 69 */ 70 enum cgs_engine { 71 CGS_ENGINE__UVD, 72 CGS_ENGINE__VCE, 73 CGS_ENGINE__VP8, 74 CGS_ENGINE__ACP_DMA, 75 CGS_ENGINE__ACP_DSP0, 76 CGS_ENGINE__ACP_DSP1, 77 CGS_ENGINE__ISP, 78 /* ... */ 79 }; 80 81 /** 82 * enum cgs_voltage_planes - Voltage planes for external camera HW 83 */ 84 enum cgs_voltage_planes { 85 CGS_VOLTAGE_PLANE__SENSOR0, 86 CGS_VOLTAGE_PLANE__SENSOR1, 87 /* ... */ 88 }; 89 90 /* 91 * enum cgs_ucode_id - Firmware types for different IPs 92 */ 93 enum cgs_ucode_id { 94 CGS_UCODE_ID_SMU = 0, 95 CGS_UCODE_ID_SDMA0, 96 CGS_UCODE_ID_SDMA1, 97 CGS_UCODE_ID_CP_CE, 98 CGS_UCODE_ID_CP_PFP, 99 CGS_UCODE_ID_CP_ME, 100 CGS_UCODE_ID_CP_MEC, 101 CGS_UCODE_ID_CP_MEC_JT1, 102 CGS_UCODE_ID_CP_MEC_JT2, 103 CGS_UCODE_ID_GMCON_RENG, 104 CGS_UCODE_ID_RLC_G, 105 CGS_UCODE_ID_MAXIMUM, 106 }; 107 108 enum cgs_system_info_id { 109 CGS_SYSTEM_INFO_ADAPTER_BDF_ID = 1, 110 CGS_SYSTEM_INFO_PCIE_GEN_INFO, 111 CGS_SYSTEM_INFO_PCIE_MLW, 112 CGS_SYSTEM_INFO_ID_MAXIMUM, 113 }; 114 115 struct cgs_system_info { 116 uint64_t size; 117 uint64_t info_id; 118 union { 119 void *ptr; 120 uint64_t value; 121 }; 122 uint64_t padding[13]; 123 }; 124 125 /* 126 * enum cgs_resource_type - GPU resource type 127 */ 128 enum cgs_resource_type { 129 CGS_RESOURCE_TYPE_MMIO = 0, 130 CGS_RESOURCE_TYPE_FB, 131 CGS_RESOURCE_TYPE_IO, 132 CGS_RESOURCE_TYPE_DOORBELL, 133 CGS_RESOURCE_TYPE_ROM, 134 }; 135 136 /** 137 * struct cgs_clock_limits - Clock limits 138 * 139 * Clocks are specified in 10KHz units. 140 */ 141 struct cgs_clock_limits { 142 unsigned min; /**< Minimum supported frequency */ 143 unsigned max; /**< Maxumim supported frequency */ 144 unsigned sustainable; /**< Thermally sustainable frequency */ 145 }; 146 147 /** 148 * struct cgs_firmware_info - Firmware information 149 */ 150 struct cgs_firmware_info { 151 uint16_t version; 152 uint16_t feature_version; 153 uint32_t image_size; 154 uint64_t mc_addr; 155 void *kptr; 156 }; 157 158 struct cgs_mode_info { 159 uint32_t refresh_rate; 160 uint32_t ref_clock; 161 uint32_t vblank_time_us; 162 }; 163 164 struct cgs_display_info { 165 uint32_t display_count; 166 uint32_t active_display_mask; 167 struct cgs_mode_info *mode_info; 168 }; 169 170 typedef unsigned long cgs_handle_t; 171 172 #define CGS_ACPI_METHOD_ATCS 0x53435441 173 #define CGS_ACPI_METHOD_ATIF 0x46495441 174 #define CGS_ACPI_METHOD_ATPX 0x58505441 175 #define CGS_ACPI_FIELD_METHOD_NAME 0x00000001 176 #define CGS_ACPI_FIELD_INPUT_ARGUMENT_COUNT 0x00000002 177 #define CGS_ACPI_MAX_BUFFER_SIZE 256 178 #define CGS_ACPI_TYPE_ANY 0x00 179 #define CGS_ACPI_TYPE_INTEGER 0x01 180 #define CGS_ACPI_TYPE_STRING 0x02 181 #define CGS_ACPI_TYPE_BUFFER 0x03 182 #define CGS_ACPI_TYPE_PACKAGE 0x04 183 184 struct cgs_acpi_method_argument { 185 uint32_t type; 186 uint32_t method_length; 187 uint32_t data_length; 188 union{ 189 uint32_t value; 190 void *pointer; 191 }; 192 }; 193 194 struct cgs_acpi_method_info { 195 uint32_t size; 196 uint32_t field; 197 uint32_t input_count; 198 uint32_t name; 199 struct cgs_acpi_method_argument *pinput_argument; 200 uint32_t output_count; 201 struct cgs_acpi_method_argument *poutput_argument; 202 uint32_t padding[9]; 203 }; 204 205 /** 206 * cgs_gpu_mem_info() - Return information about memory heaps 207 * @cgs_device: opaque device handle 208 * @type: memory type 209 * @mc_start: Start MC address of the heap (output) 210 * @mc_size: MC address space size (output) 211 * @mem_size: maximum amount of memory available for allocation (output) 212 * 213 * This function returns information about memory heaps. The type 214 * parameter is used to select the memory heap. The mc_start and 215 * mc_size for GART heaps may be bigger than the memory available for 216 * allocation. 217 * 218 * mc_start and mc_size are undefined for non-contiguous FB memory 219 * types, since buffers allocated with these types may or may not be 220 * GART mapped. 221 * 222 * Return: 0 on success, -errno otherwise 223 */ 224 typedef int (*cgs_gpu_mem_info_t)(void *cgs_device, enum cgs_gpu_mem_type type, 225 uint64_t *mc_start, uint64_t *mc_size, 226 uint64_t *mem_size); 227 228 /** 229 * cgs_gmap_kmem() - map kernel memory to GART aperture 230 * @cgs_device: opaque device handle 231 * @kmem: pointer to kernel memory 232 * @size: size to map 233 * @min_offset: minimum offset from start of GART aperture 234 * @max_offset: maximum offset from start of GART aperture 235 * @kmem_handle: kernel memory handle (output) 236 * @mcaddr: MC address (output) 237 * 238 * Return: 0 on success, -errno otherwise 239 */ 240 typedef int (*cgs_gmap_kmem_t)(void *cgs_device, void *kmem, uint64_t size, 241 uint64_t min_offset, uint64_t max_offset, 242 cgs_handle_t *kmem_handle, uint64_t *mcaddr); 243 244 /** 245 * cgs_gunmap_kmem() - unmap kernel memory 246 * @cgs_device: opaque device handle 247 * @kmem_handle: kernel memory handle returned by gmap_kmem 248 * 249 * Return: 0 on success, -errno otherwise 250 */ 251 typedef int (*cgs_gunmap_kmem_t)(void *cgs_device, cgs_handle_t kmem_handle); 252 253 /** 254 * cgs_alloc_gpu_mem() - Allocate GPU memory 255 * @cgs_device: opaque device handle 256 * @type: memory type 257 * @size: size in bytes 258 * @align: alignment in bytes 259 * @min_offset: minimum offset from start of heap 260 * @max_offset: maximum offset from start of heap 261 * @handle: memory handle (output) 262 * 263 * The memory types CGS_GPU_MEM_TYPE_*_CONTIG_FB force contiguous 264 * memory allocation. This guarantees that the MC address returned by 265 * cgs_gmap_gpu_mem is not mapped through the GART. The non-contiguous 266 * FB memory types may be GART mapped depending on memory 267 * fragmentation and memory allocator policies. 268 * 269 * If min/max_offset are non-0, the allocation will be forced to 270 * reside between these offsets in its respective memory heap. The 271 * base address that the offset relates to, depends on the memory 272 * type. 273 * 274 * - CGS_GPU_MEM_TYPE__*_CONTIG_FB: FB MC base address 275 * - CGS_GPU_MEM_TYPE__GART_*: GART aperture base address 276 * - others: undefined, don't use with max_offset 277 * 278 * Return: 0 on success, -errno otherwise 279 */ 280 typedef int (*cgs_alloc_gpu_mem_t)(void *cgs_device, enum cgs_gpu_mem_type type, 281 uint64_t size, uint64_t align, 282 uint64_t min_offset, uint64_t max_offset, 283 cgs_handle_t *handle); 284 285 /** 286 * cgs_free_gpu_mem() - Free GPU memory 287 * @cgs_device: opaque device handle 288 * @handle: memory handle returned by alloc or import 289 * 290 * Return: 0 on success, -errno otherwise 291 */ 292 typedef int (*cgs_free_gpu_mem_t)(void *cgs_device, cgs_handle_t handle); 293 294 /** 295 * cgs_gmap_gpu_mem() - GPU-map GPU memory 296 * @cgs_device: opaque device handle 297 * @handle: memory handle returned by alloc or import 298 * @mcaddr: MC address (output) 299 * 300 * Ensures that a buffer is GPU accessible and returns its MC address. 301 * 302 * Return: 0 on success, -errno otherwise 303 */ 304 typedef int (*cgs_gmap_gpu_mem_t)(void *cgs_device, cgs_handle_t handle, 305 uint64_t *mcaddr); 306 307 /** 308 * cgs_gunmap_gpu_mem() - GPU-unmap GPU memory 309 * @cgs_device: opaque device handle 310 * @handle: memory handle returned by alloc or import 311 * 312 * Allows the buffer to be migrated while it's not used by the GPU. 313 * 314 * Return: 0 on success, -errno otherwise 315 */ 316 typedef int (*cgs_gunmap_gpu_mem_t)(void *cgs_device, cgs_handle_t handle); 317 318 /** 319 * cgs_kmap_gpu_mem() - Kernel-map GPU memory 320 * 321 * @cgs_device: opaque device handle 322 * @handle: memory handle returned by alloc or import 323 * @map: Kernel virtual address the memory was mapped to (output) 324 * 325 * Return: 0 on success, -errno otherwise 326 */ 327 typedef int (*cgs_kmap_gpu_mem_t)(void *cgs_device, cgs_handle_t handle, 328 void **map); 329 330 /** 331 * cgs_kunmap_gpu_mem() - Kernel-unmap GPU memory 332 * @cgs_device: opaque device handle 333 * @handle: memory handle returned by alloc or import 334 * 335 * Return: 0 on success, -errno otherwise 336 */ 337 typedef int (*cgs_kunmap_gpu_mem_t)(void *cgs_device, cgs_handle_t handle); 338 339 /** 340 * cgs_read_register() - Read an MMIO register 341 * @cgs_device: opaque device handle 342 * @offset: register offset 343 * 344 * Return: register value 345 */ 346 typedef uint32_t (*cgs_read_register_t)(void *cgs_device, unsigned offset); 347 348 /** 349 * cgs_write_register() - Write an MMIO register 350 * @cgs_device: opaque device handle 351 * @offset: register offset 352 * @value: register value 353 */ 354 typedef void (*cgs_write_register_t)(void *cgs_device, unsigned offset, 355 uint32_t value); 356 357 /** 358 * cgs_read_ind_register() - Read an indirect register 359 * @cgs_device: opaque device handle 360 * @offset: register offset 361 * 362 * Return: register value 363 */ 364 typedef uint32_t (*cgs_read_ind_register_t)(void *cgs_device, enum cgs_ind_reg space, 365 unsigned index); 366 367 /** 368 * cgs_write_ind_register() - Write an indirect register 369 * @cgs_device: opaque device handle 370 * @offset: register offset 371 * @value: register value 372 */ 373 typedef void (*cgs_write_ind_register_t)(void *cgs_device, enum cgs_ind_reg space, 374 unsigned index, uint32_t value); 375 376 /** 377 * cgs_read_pci_config_byte() - Read byte from PCI configuration space 378 * @cgs_device: opaque device handle 379 * @addr: address 380 * 381 * Return: Value read 382 */ 383 typedef uint8_t (*cgs_read_pci_config_byte_t)(void *cgs_device, unsigned addr); 384 385 /** 386 * cgs_read_pci_config_word() - Read word from PCI configuration space 387 * @cgs_device: opaque device handle 388 * @addr: address, must be word-aligned 389 * 390 * Return: Value read 391 */ 392 typedef uint16_t (*cgs_read_pci_config_word_t)(void *cgs_device, unsigned addr); 393 394 /** 395 * cgs_read_pci_config_dword() - Read dword from PCI configuration space 396 * @cgs_device: opaque device handle 397 * @addr: address, must be dword-aligned 398 * 399 * Return: Value read 400 */ 401 typedef uint32_t (*cgs_read_pci_config_dword_t)(void *cgs_device, 402 unsigned addr); 403 404 /** 405 * cgs_write_pci_config_byte() - Write byte to PCI configuration space 406 * @cgs_device: opaque device handle 407 * @addr: address 408 * @value: value to write 409 */ 410 typedef void (*cgs_write_pci_config_byte_t)(void *cgs_device, unsigned addr, 411 uint8_t value); 412 413 /** 414 * cgs_write_pci_config_word() - Write byte to PCI configuration space 415 * @cgs_device: opaque device handle 416 * @addr: address, must be word-aligned 417 * @value: value to write 418 */ 419 typedef void (*cgs_write_pci_config_word_t)(void *cgs_device, unsigned addr, 420 uint16_t value); 421 422 /** 423 * cgs_write_pci_config_dword() - Write byte to PCI configuration space 424 * @cgs_device: opaque device handle 425 * @addr: address, must be dword-aligned 426 * @value: value to write 427 */ 428 typedef void (*cgs_write_pci_config_dword_t)(void *cgs_device, unsigned addr, 429 uint32_t value); 430 431 432 /** 433 * cgs_get_pci_resource() - provide access to a device resource (PCI BAR) 434 * @cgs_device: opaque device handle 435 * @resource_type: Type of Resource (MMIO, IO, ROM, FB, DOORBELL) 436 * @size: size of the region 437 * @offset: offset from the start of the region 438 * @resource_base: base address (not including offset) returned 439 * 440 * Return: 0 on success, -errno otherwise 441 */ 442 typedef int (*cgs_get_pci_resource_t)(void *cgs_device, 443 enum cgs_resource_type resource_type, 444 uint64_t size, 445 uint64_t offset, 446 uint64_t *resource_base); 447 448 /** 449 * cgs_atom_get_data_table() - Get a pointer to an ATOM BIOS data table 450 * @cgs_device: opaque device handle 451 * @table: data table index 452 * @size: size of the table (output, may be NULL) 453 * @frev: table format revision (output, may be NULL) 454 * @crev: table content revision (output, may be NULL) 455 * 456 * Return: Pointer to start of the table, or NULL on failure 457 */ 458 typedef const void *(*cgs_atom_get_data_table_t)( 459 void *cgs_device, unsigned table, 460 uint16_t *size, uint8_t *frev, uint8_t *crev); 461 462 /** 463 * cgs_atom_get_cmd_table_revs() - Get ATOM BIOS command table revisions 464 * @cgs_device: opaque device handle 465 * @table: data table index 466 * @frev: table format revision (output, may be NULL) 467 * @crev: table content revision (output, may be NULL) 468 * 469 * Return: 0 on success, -errno otherwise 470 */ 471 typedef int (*cgs_atom_get_cmd_table_revs_t)(void *cgs_device, unsigned table, 472 uint8_t *frev, uint8_t *crev); 473 474 /** 475 * cgs_atom_exec_cmd_table() - Execute an ATOM BIOS command table 476 * @cgs_device: opaque device handle 477 * @table: command table index 478 * @args: arguments 479 * 480 * Return: 0 on success, -errno otherwise 481 */ 482 typedef int (*cgs_atom_exec_cmd_table_t)(void *cgs_device, 483 unsigned table, void *args); 484 485 /** 486 * cgs_create_pm_request() - Create a power management request 487 * @cgs_device: opaque device handle 488 * @request: handle of created PM request (output) 489 * 490 * Return: 0 on success, -errno otherwise 491 */ 492 typedef int (*cgs_create_pm_request_t)(void *cgs_device, cgs_handle_t *request); 493 494 /** 495 * cgs_destroy_pm_request() - Destroy a power management request 496 * @cgs_device: opaque device handle 497 * @request: handle of created PM request 498 * 499 * Return: 0 on success, -errno otherwise 500 */ 501 typedef int (*cgs_destroy_pm_request_t)(void *cgs_device, cgs_handle_t request); 502 503 /** 504 * cgs_set_pm_request() - Activate or deactiveate a PM request 505 * @cgs_device: opaque device handle 506 * @request: PM request handle 507 * @active: 0 = deactivate, non-0 = activate 508 * 509 * While a PM request is active, its minimum clock requests are taken 510 * into account as the requested engines are powered up. When the 511 * request is inactive, the engines may be powered down and clocks may 512 * be lower, depending on other PM requests by other driver 513 * components. 514 * 515 * Return: 0 on success, -errno otherwise 516 */ 517 typedef int (*cgs_set_pm_request_t)(void *cgs_device, cgs_handle_t request, 518 int active); 519 520 /** 521 * cgs_pm_request_clock() - Request a minimum frequency for a specific clock 522 * @cgs_device: opaque device handle 523 * @request: PM request handle 524 * @clock: which clock? 525 * @freq: requested min. frequency in 10KHz units (0 to clear request) 526 * 527 * Return: 0 on success, -errno otherwise 528 */ 529 typedef int (*cgs_pm_request_clock_t)(void *cgs_device, cgs_handle_t request, 530 enum cgs_clock clock, unsigned freq); 531 532 /** 533 * cgs_pm_request_engine() - Request an engine to be powered up 534 * @cgs_device: opaque device handle 535 * @request: PM request handle 536 * @engine: which engine? 537 * @powered: 0 = powered down, non-0 = powered up 538 * 539 * Return: 0 on success, -errno otherwise 540 */ 541 typedef int (*cgs_pm_request_engine_t)(void *cgs_device, cgs_handle_t request, 542 enum cgs_engine engine, int powered); 543 544 /** 545 * cgs_pm_query_clock_limits() - Query clock frequency limits 546 * @cgs_device: opaque device handle 547 * @clock: which clock? 548 * @limits: clock limits 549 * 550 * Return: 0 on success, -errno otherwise 551 */ 552 typedef int (*cgs_pm_query_clock_limits_t)(void *cgs_device, 553 enum cgs_clock clock, 554 struct cgs_clock_limits *limits); 555 556 /** 557 * cgs_set_camera_voltages() - Apply specific voltages to PMIC voltage planes 558 * @cgs_device: opaque device handle 559 * @mask: bitmask of voltages to change (1<<CGS_VOLTAGE_PLANE__xyz|...) 560 * @voltages: pointer to array of voltage values in 1mV units 561 * 562 * Return: 0 on success, -errno otherwise 563 */ 564 typedef int (*cgs_set_camera_voltages_t)(void *cgs_device, uint32_t mask, 565 const uint32_t *voltages); 566 /** 567 * cgs_get_firmware_info - Get the firmware information from core driver 568 * @cgs_device: opaque device handle 569 * @type: the firmware type 570 * @info: returend firmware information 571 * 572 * Return: 0 on success, -errno otherwise 573 */ 574 typedef int (*cgs_get_firmware_info)(void *cgs_device, 575 enum cgs_ucode_id type, 576 struct cgs_firmware_info *info); 577 578 typedef int(*cgs_set_powergating_state)(void *cgs_device, 579 enum amd_ip_block_type block_type, 580 enum amd_powergating_state state); 581 582 typedef int(*cgs_set_clockgating_state)(void *cgs_device, 583 enum amd_ip_block_type block_type, 584 enum amd_clockgating_state state); 585 586 typedef int(*cgs_get_active_displays_info)( 587 void *cgs_device, 588 struct cgs_display_info *info); 589 590 typedef int (*cgs_call_acpi_method)(void *cgs_device, 591 uint32_t acpi_method, 592 uint32_t acpi_function, 593 void *pinput, void *poutput, 594 uint32_t output_count, 595 uint32_t input_size, 596 uint32_t output_size); 597 598 typedef int (*cgs_query_system_info)(void *cgs_device, 599 struct cgs_system_info *sys_info); 600 601 struct cgs_ops { 602 /* memory management calls (similar to KFD interface) */ 603 cgs_gpu_mem_info_t gpu_mem_info; 604 cgs_gmap_kmem_t gmap_kmem; 605 cgs_gunmap_kmem_t gunmap_kmem; 606 cgs_alloc_gpu_mem_t alloc_gpu_mem; 607 cgs_free_gpu_mem_t free_gpu_mem; 608 cgs_gmap_gpu_mem_t gmap_gpu_mem; 609 cgs_gunmap_gpu_mem_t gunmap_gpu_mem; 610 cgs_kmap_gpu_mem_t kmap_gpu_mem; 611 cgs_kunmap_gpu_mem_t kunmap_gpu_mem; 612 /* MMIO access */ 613 cgs_read_register_t read_register; 614 cgs_write_register_t write_register; 615 cgs_read_ind_register_t read_ind_register; 616 cgs_write_ind_register_t write_ind_register; 617 /* PCI configuration space access */ 618 cgs_read_pci_config_byte_t read_pci_config_byte; 619 cgs_read_pci_config_word_t read_pci_config_word; 620 cgs_read_pci_config_dword_t read_pci_config_dword; 621 cgs_write_pci_config_byte_t write_pci_config_byte; 622 cgs_write_pci_config_word_t write_pci_config_word; 623 cgs_write_pci_config_dword_t write_pci_config_dword; 624 /* PCI resources */ 625 cgs_get_pci_resource_t get_pci_resource; 626 /* ATOM BIOS */ 627 cgs_atom_get_data_table_t atom_get_data_table; 628 cgs_atom_get_cmd_table_revs_t atom_get_cmd_table_revs; 629 cgs_atom_exec_cmd_table_t atom_exec_cmd_table; 630 /* Power management */ 631 cgs_create_pm_request_t create_pm_request; 632 cgs_destroy_pm_request_t destroy_pm_request; 633 cgs_set_pm_request_t set_pm_request; 634 cgs_pm_request_clock_t pm_request_clock; 635 cgs_pm_request_engine_t pm_request_engine; 636 cgs_pm_query_clock_limits_t pm_query_clock_limits; 637 cgs_set_camera_voltages_t set_camera_voltages; 638 /* Firmware Info */ 639 cgs_get_firmware_info get_firmware_info; 640 /* cg pg interface*/ 641 cgs_set_powergating_state set_powergating_state; 642 cgs_set_clockgating_state set_clockgating_state; 643 /* display manager */ 644 cgs_get_active_displays_info get_active_displays_info; 645 /* ACPI */ 646 cgs_call_acpi_method call_acpi_method; 647 /* get system info */ 648 cgs_query_system_info query_system_info; 649 }; 650 651 struct cgs_os_ops; /* To be define in OS-specific CGS header */ 652 653 struct cgs_device 654 { 655 const struct cgs_ops *ops; 656 const struct cgs_os_ops *os_ops; 657 /* to be embedded at the start of driver private structure */ 658 }; 659 660 /* Convenience macros that make CGS indirect function calls look like 661 * normal function calls */ 662 #define CGS_CALL(func,dev,...) \ 663 (((struct cgs_device *)dev)->ops->func(dev, ##__VA_ARGS__)) 664 #define CGS_OS_CALL(func,dev,...) \ 665 (((struct cgs_device *)dev)->os_ops->func(dev, ##__VA_ARGS__)) 666 667 #define cgs_gpu_mem_info(dev,type,mc_start,mc_size,mem_size) \ 668 CGS_CALL(gpu_mem_info,dev,type,mc_start,mc_size,mem_size) 669 #define cgs_gmap_kmem(dev,kmem,size,min_off,max_off,kmem_handle,mcaddr) \ 670 CGS_CALL(gmap_kmem,dev,kmem,size,min_off,max_off,kmem_handle,mcaddr) 671 #define cgs_gunmap_kmem(dev,kmem_handle) \ 672 CGS_CALL(gunmap_kmem,dev,keme_handle) 673 #define cgs_alloc_gpu_mem(dev,type,size,align,min_off,max_off,handle) \ 674 CGS_CALL(alloc_gpu_mem,dev,type,size,align,min_off,max_off,handle) 675 #define cgs_free_gpu_mem(dev,handle) \ 676 CGS_CALL(free_gpu_mem,dev,handle) 677 #define cgs_gmap_gpu_mem(dev,handle,mcaddr) \ 678 CGS_CALL(gmap_gpu_mem,dev,handle,mcaddr) 679 #define cgs_gunmap_gpu_mem(dev,handle) \ 680 CGS_CALL(gunmap_gpu_mem,dev,handle) 681 #define cgs_kmap_gpu_mem(dev,handle,map) \ 682 CGS_CALL(kmap_gpu_mem,dev,handle,map) 683 #define cgs_kunmap_gpu_mem(dev,handle) \ 684 CGS_CALL(kunmap_gpu_mem,dev,handle) 685 686 #define cgs_read_register(dev,offset) \ 687 CGS_CALL(read_register,dev,offset) 688 #define cgs_write_register(dev,offset,value) \ 689 CGS_CALL(write_register,dev,offset,value) 690 #define cgs_read_ind_register(dev,space,index) \ 691 CGS_CALL(read_ind_register,dev,space,index) 692 #define cgs_write_ind_register(dev,space,index,value) \ 693 CGS_CALL(write_ind_register,dev,space,index,value) 694 695 #define cgs_read_pci_config_byte(dev,addr) \ 696 CGS_CALL(read_pci_config_byte,dev,addr) 697 #define cgs_read_pci_config_word(dev,addr) \ 698 CGS_CALL(read_pci_config_word,dev,addr) 699 #define cgs_read_pci_config_dword(dev,addr) \ 700 CGS_CALL(read_pci_config_dword,dev,addr) 701 #define cgs_write_pci_config_byte(dev,addr,value) \ 702 CGS_CALL(write_pci_config_byte,dev,addr,value) 703 #define cgs_write_pci_config_word(dev,addr,value) \ 704 CGS_CALL(write_pci_config_word,dev,addr,value) 705 #define cgs_write_pci_config_dword(dev,addr,value) \ 706 CGS_CALL(write_pci_config_dword,dev,addr,value) 707 708 #define cgs_atom_get_data_table(dev,table,size,frev,crev) \ 709 CGS_CALL(atom_get_data_table,dev,table,size,frev,crev) 710 #define cgs_atom_get_cmd_table_revs(dev,table,frev,crev) \ 711 CGS_CALL(atom_get_cmd_table_revs,dev,table,frev,crev) 712 #define cgs_atom_exec_cmd_table(dev,table,args) \ 713 CGS_CALL(atom_exec_cmd_table,dev,table,args) 714 715 #define cgs_create_pm_request(dev,request) \ 716 CGS_CALL(create_pm_request,dev,request) 717 #define cgs_destroy_pm_request(dev,request) \ 718 CGS_CALL(destroy_pm_request,dev,request) 719 #define cgs_set_pm_request(dev,request,active) \ 720 CGS_CALL(set_pm_request,dev,request,active) 721 #define cgs_pm_request_clock(dev,request,clock,freq) \ 722 CGS_CALL(pm_request_clock,dev,request,clock,freq) 723 #define cgs_pm_request_engine(dev,request,engine,powered) \ 724 CGS_CALL(pm_request_engine,dev,request,engine,powered) 725 #define cgs_pm_query_clock_limits(dev,clock,limits) \ 726 CGS_CALL(pm_query_clock_limits,dev,clock,limits) 727 #define cgs_set_camera_voltages(dev,mask,voltages) \ 728 CGS_CALL(set_camera_voltages,dev,mask,voltages) 729 #define cgs_get_firmware_info(dev, type, info) \ 730 CGS_CALL(get_firmware_info, dev, type, info) 731 #define cgs_set_powergating_state(dev, block_type, state) \ 732 CGS_CALL(set_powergating_state, dev, block_type, state) 733 #define cgs_set_clockgating_state(dev, block_type, state) \ 734 CGS_CALL(set_clockgating_state, dev, block_type, state) 735 #define cgs_get_active_displays_info(dev, info) \ 736 CGS_CALL(get_active_displays_info, dev, info) 737 #define cgs_call_acpi_method(dev, acpi_method, acpi_function, pintput, poutput, output_count, input_size, output_size) \ 738 CGS_CALL(call_acpi_method, dev, acpi_method, acpi_function, pintput, poutput, output_count, input_size, output_size) 739 #define cgs_query_system_info(dev, sys_info) \ 740 CGS_CALL(query_system_info, dev, sys_info) 741 #define cgs_get_pci_resource(cgs_device, resource_type, size, offset, \ 742 resource_base) \ 743 CGS_CALL(get_pci_resource, cgs_device, resource_type, size, offset, \ 744 resource_base) 745 746 #endif /* _CGS_COMMON_H */ 747