1 /* 2 * Copyright 2015 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * 23 */ 24 #ifndef _CGS_COMMON_H 25 #define _CGS_COMMON_H 26 27 #include "amd_shared.h" 28 29 struct cgs_device; 30 31 /** 32 * enum cgs_gpu_mem_type - GPU memory types 33 */ 34 enum cgs_gpu_mem_type { 35 CGS_GPU_MEM_TYPE__VISIBLE_FB, 36 CGS_GPU_MEM_TYPE__INVISIBLE_FB, 37 CGS_GPU_MEM_TYPE__VISIBLE_CONTIG_FB, 38 CGS_GPU_MEM_TYPE__INVISIBLE_CONTIG_FB, 39 CGS_GPU_MEM_TYPE__GART_CACHEABLE, 40 CGS_GPU_MEM_TYPE__GART_WRITECOMBINE 41 }; 42 43 /** 44 * enum cgs_ind_reg - Indirect register spaces 45 */ 46 enum cgs_ind_reg { 47 CGS_IND_REG__MMIO, 48 CGS_IND_REG__PCIE, 49 CGS_IND_REG__SMC, 50 CGS_IND_REG__UVD_CTX, 51 CGS_IND_REG__DIDT, 52 CGS_IND_REG_GC_CAC, 53 CGS_IND_REG__AUDIO_ENDPT 54 }; 55 56 /** 57 * enum cgs_clock - Clocks controlled by the SMU 58 */ 59 enum cgs_clock { 60 CGS_CLOCK__SCLK, 61 CGS_CLOCK__MCLK, 62 CGS_CLOCK__VCLK, 63 CGS_CLOCK__DCLK, 64 CGS_CLOCK__ECLK, 65 CGS_CLOCK__ACLK, 66 CGS_CLOCK__ICLK, 67 /* ... */ 68 }; 69 70 /** 71 * enum cgs_engine - Engines that can be statically power-gated 72 */ 73 enum cgs_engine { 74 CGS_ENGINE__UVD, 75 CGS_ENGINE__VCE, 76 CGS_ENGINE__VP8, 77 CGS_ENGINE__ACP_DMA, 78 CGS_ENGINE__ACP_DSP0, 79 CGS_ENGINE__ACP_DSP1, 80 CGS_ENGINE__ISP, 81 /* ... */ 82 }; 83 84 /** 85 * enum cgs_voltage_planes - Voltage planes for external camera HW 86 */ 87 enum cgs_voltage_planes { 88 CGS_VOLTAGE_PLANE__SENSOR0, 89 CGS_VOLTAGE_PLANE__SENSOR1, 90 /* ... */ 91 }; 92 93 /* 94 * enum cgs_ucode_id - Firmware types for different IPs 95 */ 96 enum cgs_ucode_id { 97 CGS_UCODE_ID_SMU = 0, 98 CGS_UCODE_ID_SMU_SK, 99 CGS_UCODE_ID_SDMA0, 100 CGS_UCODE_ID_SDMA1, 101 CGS_UCODE_ID_CP_CE, 102 CGS_UCODE_ID_CP_PFP, 103 CGS_UCODE_ID_CP_ME, 104 CGS_UCODE_ID_CP_MEC, 105 CGS_UCODE_ID_CP_MEC_JT1, 106 CGS_UCODE_ID_CP_MEC_JT2, 107 CGS_UCODE_ID_GMCON_RENG, 108 CGS_UCODE_ID_RLC_G, 109 CGS_UCODE_ID_MAXIMUM, 110 }; 111 112 enum cgs_system_info_id { 113 CGS_SYSTEM_INFO_ADAPTER_BDF_ID = 1, 114 CGS_SYSTEM_INFO_PCIE_GEN_INFO, 115 CGS_SYSTEM_INFO_PCIE_MLW, 116 CGS_SYSTEM_INFO_PCIE_DEV, 117 CGS_SYSTEM_INFO_PCIE_REV, 118 CGS_SYSTEM_INFO_CG_FLAGS, 119 CGS_SYSTEM_INFO_PG_FLAGS, 120 CGS_SYSTEM_INFO_GFX_CU_INFO, 121 CGS_SYSTEM_INFO_GFX_SE_INFO, 122 CGS_SYSTEM_INFO_PCIE_SUB_SYS_ID, 123 CGS_SYSTEM_INFO_PCIE_SUB_SYS_VENDOR_ID, 124 CGS_SYSTEM_INFO_ID_MAXIMUM, 125 }; 126 127 struct cgs_system_info { 128 uint64_t size; 129 enum cgs_system_info_id info_id; 130 union { 131 void *ptr; 132 uint64_t value; 133 }; 134 uint64_t padding[13]; 135 }; 136 137 /* 138 * enum cgs_resource_type - GPU resource type 139 */ 140 enum cgs_resource_type { 141 CGS_RESOURCE_TYPE_MMIO = 0, 142 CGS_RESOURCE_TYPE_FB, 143 CGS_RESOURCE_TYPE_IO, 144 CGS_RESOURCE_TYPE_DOORBELL, 145 CGS_RESOURCE_TYPE_ROM, 146 }; 147 148 /** 149 * struct cgs_clock_limits - Clock limits 150 * 151 * Clocks are specified in 10KHz units. 152 */ 153 struct cgs_clock_limits { 154 unsigned min; /**< Minimum supported frequency */ 155 unsigned max; /**< Maxumim supported frequency */ 156 unsigned sustainable; /**< Thermally sustainable frequency */ 157 }; 158 159 /** 160 * struct cgs_firmware_info - Firmware information 161 */ 162 struct cgs_firmware_info { 163 uint16_t version; 164 uint16_t fw_version; 165 uint16_t feature_version; 166 uint32_t image_size; 167 uint64_t mc_addr; 168 169 /* only for smc firmware */ 170 uint32_t ucode_start_address; 171 172 void *kptr; 173 }; 174 175 struct cgs_mode_info { 176 uint32_t refresh_rate; 177 uint32_t ref_clock; 178 uint32_t vblank_time_us; 179 }; 180 181 struct cgs_display_info { 182 uint32_t display_count; 183 uint32_t active_display_mask; 184 struct cgs_mode_info *mode_info; 185 }; 186 187 typedef unsigned long cgs_handle_t; 188 189 #define CGS_ACPI_METHOD_ATCS 0x53435441 190 #define CGS_ACPI_METHOD_ATIF 0x46495441 191 #define CGS_ACPI_METHOD_ATPX 0x58505441 192 #define CGS_ACPI_FIELD_METHOD_NAME 0x00000001 193 #define CGS_ACPI_FIELD_INPUT_ARGUMENT_COUNT 0x00000002 194 #define CGS_ACPI_MAX_BUFFER_SIZE 256 195 #define CGS_ACPI_TYPE_ANY 0x00 196 #define CGS_ACPI_TYPE_INTEGER 0x01 197 #define CGS_ACPI_TYPE_STRING 0x02 198 #define CGS_ACPI_TYPE_BUFFER 0x03 199 #define CGS_ACPI_TYPE_PACKAGE 0x04 200 201 struct cgs_acpi_method_argument { 202 uint32_t type; 203 uint32_t data_length; 204 union{ 205 uint32_t value; 206 void *pointer; 207 }; 208 }; 209 210 struct cgs_acpi_method_info { 211 uint32_t size; 212 uint32_t field; 213 uint32_t input_count; 214 uint32_t name; 215 struct cgs_acpi_method_argument *pinput_argument; 216 uint32_t output_count; 217 struct cgs_acpi_method_argument *poutput_argument; 218 uint32_t padding[9]; 219 }; 220 221 /** 222 * cgs_gpu_mem_info() - Return information about memory heaps 223 * @cgs_device: opaque device handle 224 * @type: memory type 225 * @mc_start: Start MC address of the heap (output) 226 * @mc_size: MC address space size (output) 227 * @mem_size: maximum amount of memory available for allocation (output) 228 * 229 * This function returns information about memory heaps. The type 230 * parameter is used to select the memory heap. The mc_start and 231 * mc_size for GART heaps may be bigger than the memory available for 232 * allocation. 233 * 234 * mc_start and mc_size are undefined for non-contiguous FB memory 235 * types, since buffers allocated with these types may or may not be 236 * GART mapped. 237 * 238 * Return: 0 on success, -errno otherwise 239 */ 240 typedef int (*cgs_gpu_mem_info_t)(struct cgs_device *cgs_device, enum cgs_gpu_mem_type type, 241 uint64_t *mc_start, uint64_t *mc_size, 242 uint64_t *mem_size); 243 244 /** 245 * cgs_gmap_kmem() - map kernel memory to GART aperture 246 * @cgs_device: opaque device handle 247 * @kmem: pointer to kernel memory 248 * @size: size to map 249 * @min_offset: minimum offset from start of GART aperture 250 * @max_offset: maximum offset from start of GART aperture 251 * @kmem_handle: kernel memory handle (output) 252 * @mcaddr: MC address (output) 253 * 254 * Return: 0 on success, -errno otherwise 255 */ 256 typedef int (*cgs_gmap_kmem_t)(struct cgs_device *cgs_device, void *kmem, uint64_t size, 257 uint64_t min_offset, uint64_t max_offset, 258 cgs_handle_t *kmem_handle, uint64_t *mcaddr); 259 260 /** 261 * cgs_gunmap_kmem() - unmap kernel memory 262 * @cgs_device: opaque device handle 263 * @kmem_handle: kernel memory handle returned by gmap_kmem 264 * 265 * Return: 0 on success, -errno otherwise 266 */ 267 typedef int (*cgs_gunmap_kmem_t)(struct cgs_device *cgs_device, cgs_handle_t kmem_handle); 268 269 /** 270 * cgs_alloc_gpu_mem() - Allocate GPU memory 271 * @cgs_device: opaque device handle 272 * @type: memory type 273 * @size: size in bytes 274 * @align: alignment in bytes 275 * @min_offset: minimum offset from start of heap 276 * @max_offset: maximum offset from start of heap 277 * @handle: memory handle (output) 278 * 279 * The memory types CGS_GPU_MEM_TYPE_*_CONTIG_FB force contiguous 280 * memory allocation. This guarantees that the MC address returned by 281 * cgs_gmap_gpu_mem is not mapped through the GART. The non-contiguous 282 * FB memory types may be GART mapped depending on memory 283 * fragmentation and memory allocator policies. 284 * 285 * If min/max_offset are non-0, the allocation will be forced to 286 * reside between these offsets in its respective memory heap. The 287 * base address that the offset relates to, depends on the memory 288 * type. 289 * 290 * - CGS_GPU_MEM_TYPE__*_CONTIG_FB: FB MC base address 291 * - CGS_GPU_MEM_TYPE__GART_*: GART aperture base address 292 * - others: undefined, don't use with max_offset 293 * 294 * Return: 0 on success, -errno otherwise 295 */ 296 typedef int (*cgs_alloc_gpu_mem_t)(struct cgs_device *cgs_device, enum cgs_gpu_mem_type type, 297 uint64_t size, uint64_t align, 298 uint64_t min_offset, uint64_t max_offset, 299 cgs_handle_t *handle); 300 301 /** 302 * cgs_free_gpu_mem() - Free GPU memory 303 * @cgs_device: opaque device handle 304 * @handle: memory handle returned by alloc or import 305 * 306 * Return: 0 on success, -errno otherwise 307 */ 308 typedef int (*cgs_free_gpu_mem_t)(struct cgs_device *cgs_device, cgs_handle_t handle); 309 310 /** 311 * cgs_gmap_gpu_mem() - GPU-map GPU memory 312 * @cgs_device: opaque device handle 313 * @handle: memory handle returned by alloc or import 314 * @mcaddr: MC address (output) 315 * 316 * Ensures that a buffer is GPU accessible and returns its MC address. 317 * 318 * Return: 0 on success, -errno otherwise 319 */ 320 typedef int (*cgs_gmap_gpu_mem_t)(struct cgs_device *cgs_device, cgs_handle_t handle, 321 uint64_t *mcaddr); 322 323 /** 324 * cgs_gunmap_gpu_mem() - GPU-unmap GPU memory 325 * @cgs_device: opaque device handle 326 * @handle: memory handle returned by alloc or import 327 * 328 * Allows the buffer to be migrated while it's not used by the GPU. 329 * 330 * Return: 0 on success, -errno otherwise 331 */ 332 typedef int (*cgs_gunmap_gpu_mem_t)(struct cgs_device *cgs_device, cgs_handle_t handle); 333 334 /** 335 * cgs_kmap_gpu_mem() - Kernel-map GPU memory 336 * 337 * @cgs_device: opaque device handle 338 * @handle: memory handle returned by alloc or import 339 * @map: Kernel virtual address the memory was mapped to (output) 340 * 341 * Return: 0 on success, -errno otherwise 342 */ 343 typedef int (*cgs_kmap_gpu_mem_t)(struct cgs_device *cgs_device, cgs_handle_t handle, 344 void **map); 345 346 /** 347 * cgs_kunmap_gpu_mem() - Kernel-unmap GPU memory 348 * @cgs_device: opaque device handle 349 * @handle: memory handle returned by alloc or import 350 * 351 * Return: 0 on success, -errno otherwise 352 */ 353 typedef int (*cgs_kunmap_gpu_mem_t)(struct cgs_device *cgs_device, cgs_handle_t handle); 354 355 /** 356 * cgs_read_register() - Read an MMIO register 357 * @cgs_device: opaque device handle 358 * @offset: register offset 359 * 360 * Return: register value 361 */ 362 typedef uint32_t (*cgs_read_register_t)(struct cgs_device *cgs_device, unsigned offset); 363 364 /** 365 * cgs_write_register() - Write an MMIO register 366 * @cgs_device: opaque device handle 367 * @offset: register offset 368 * @value: register value 369 */ 370 typedef void (*cgs_write_register_t)(struct cgs_device *cgs_device, unsigned offset, 371 uint32_t value); 372 373 /** 374 * cgs_read_ind_register() - Read an indirect register 375 * @cgs_device: opaque device handle 376 * @offset: register offset 377 * 378 * Return: register value 379 */ 380 typedef uint32_t (*cgs_read_ind_register_t)(struct cgs_device *cgs_device, enum cgs_ind_reg space, 381 unsigned index); 382 383 /** 384 * cgs_write_ind_register() - Write an indirect register 385 * @cgs_device: opaque device handle 386 * @offset: register offset 387 * @value: register value 388 */ 389 typedef void (*cgs_write_ind_register_t)(struct cgs_device *cgs_device, enum cgs_ind_reg space, 390 unsigned index, uint32_t value); 391 392 /** 393 * cgs_read_pci_config_byte() - Read byte from PCI configuration space 394 * @cgs_device: opaque device handle 395 * @addr: address 396 * 397 * Return: Value read 398 */ 399 typedef uint8_t (*cgs_read_pci_config_byte_t)(struct cgs_device *cgs_device, unsigned addr); 400 401 /** 402 * cgs_read_pci_config_word() - Read word from PCI configuration space 403 * @cgs_device: opaque device handle 404 * @addr: address, must be word-aligned 405 * 406 * Return: Value read 407 */ 408 typedef uint16_t (*cgs_read_pci_config_word_t)(struct cgs_device *cgs_device, unsigned addr); 409 410 /** 411 * cgs_read_pci_config_dword() - Read dword from PCI configuration space 412 * @cgs_device: opaque device handle 413 * @addr: address, must be dword-aligned 414 * 415 * Return: Value read 416 */ 417 typedef uint32_t (*cgs_read_pci_config_dword_t)(struct cgs_device *cgs_device, 418 unsigned addr); 419 420 /** 421 * cgs_write_pci_config_byte() - Write byte to PCI configuration space 422 * @cgs_device: opaque device handle 423 * @addr: address 424 * @value: value to write 425 */ 426 typedef void (*cgs_write_pci_config_byte_t)(struct cgs_device *cgs_device, unsigned addr, 427 uint8_t value); 428 429 /** 430 * cgs_write_pci_config_word() - Write byte to PCI configuration space 431 * @cgs_device: opaque device handle 432 * @addr: address, must be word-aligned 433 * @value: value to write 434 */ 435 typedef void (*cgs_write_pci_config_word_t)(struct cgs_device *cgs_device, unsigned addr, 436 uint16_t value); 437 438 /** 439 * cgs_write_pci_config_dword() - Write byte to PCI configuration space 440 * @cgs_device: opaque device handle 441 * @addr: address, must be dword-aligned 442 * @value: value to write 443 */ 444 typedef void (*cgs_write_pci_config_dword_t)(struct cgs_device *cgs_device, unsigned addr, 445 uint32_t value); 446 447 448 /** 449 * cgs_get_pci_resource() - provide access to a device resource (PCI BAR) 450 * @cgs_device: opaque device handle 451 * @resource_type: Type of Resource (MMIO, IO, ROM, FB, DOORBELL) 452 * @size: size of the region 453 * @offset: offset from the start of the region 454 * @resource_base: base address (not including offset) returned 455 * 456 * Return: 0 on success, -errno otherwise 457 */ 458 typedef int (*cgs_get_pci_resource_t)(struct cgs_device *cgs_device, 459 enum cgs_resource_type resource_type, 460 uint64_t size, 461 uint64_t offset, 462 uint64_t *resource_base); 463 464 /** 465 * cgs_atom_get_data_table() - Get a pointer to an ATOM BIOS data table 466 * @cgs_device: opaque device handle 467 * @table: data table index 468 * @size: size of the table (output, may be NULL) 469 * @frev: table format revision (output, may be NULL) 470 * @crev: table content revision (output, may be NULL) 471 * 472 * Return: Pointer to start of the table, or NULL on failure 473 */ 474 typedef const void *(*cgs_atom_get_data_table_t)( 475 struct cgs_device *cgs_device, unsigned table, 476 uint16_t *size, uint8_t *frev, uint8_t *crev); 477 478 /** 479 * cgs_atom_get_cmd_table_revs() - Get ATOM BIOS command table revisions 480 * @cgs_device: opaque device handle 481 * @table: data table index 482 * @frev: table format revision (output, may be NULL) 483 * @crev: table content revision (output, may be NULL) 484 * 485 * Return: 0 on success, -errno otherwise 486 */ 487 typedef int (*cgs_atom_get_cmd_table_revs_t)(struct cgs_device *cgs_device, unsigned table, 488 uint8_t *frev, uint8_t *crev); 489 490 /** 491 * cgs_atom_exec_cmd_table() - Execute an ATOM BIOS command table 492 * @cgs_device: opaque device handle 493 * @table: command table index 494 * @args: arguments 495 * 496 * Return: 0 on success, -errno otherwise 497 */ 498 typedef int (*cgs_atom_exec_cmd_table_t)(struct cgs_device *cgs_device, 499 unsigned table, void *args); 500 501 /** 502 * cgs_create_pm_request() - Create a power management request 503 * @cgs_device: opaque device handle 504 * @request: handle of created PM request (output) 505 * 506 * Return: 0 on success, -errno otherwise 507 */ 508 typedef int (*cgs_create_pm_request_t)(struct cgs_device *cgs_device, cgs_handle_t *request); 509 510 /** 511 * cgs_destroy_pm_request() - Destroy a power management request 512 * @cgs_device: opaque device handle 513 * @request: handle of created PM request 514 * 515 * Return: 0 on success, -errno otherwise 516 */ 517 typedef int (*cgs_destroy_pm_request_t)(struct cgs_device *cgs_device, cgs_handle_t request); 518 519 /** 520 * cgs_set_pm_request() - Activate or deactiveate a PM request 521 * @cgs_device: opaque device handle 522 * @request: PM request handle 523 * @active: 0 = deactivate, non-0 = activate 524 * 525 * While a PM request is active, its minimum clock requests are taken 526 * into account as the requested engines are powered up. When the 527 * request is inactive, the engines may be powered down and clocks may 528 * be lower, depending on other PM requests by other driver 529 * components. 530 * 531 * Return: 0 on success, -errno otherwise 532 */ 533 typedef int (*cgs_set_pm_request_t)(struct cgs_device *cgs_device, cgs_handle_t request, 534 int active); 535 536 /** 537 * cgs_pm_request_clock() - Request a minimum frequency for a specific clock 538 * @cgs_device: opaque device handle 539 * @request: PM request handle 540 * @clock: which clock? 541 * @freq: requested min. frequency in 10KHz units (0 to clear request) 542 * 543 * Return: 0 on success, -errno otherwise 544 */ 545 typedef int (*cgs_pm_request_clock_t)(struct cgs_device *cgs_device, cgs_handle_t request, 546 enum cgs_clock clock, unsigned freq); 547 548 /** 549 * cgs_pm_request_engine() - Request an engine to be powered up 550 * @cgs_device: opaque device handle 551 * @request: PM request handle 552 * @engine: which engine? 553 * @powered: 0 = powered down, non-0 = powered up 554 * 555 * Return: 0 on success, -errno otherwise 556 */ 557 typedef int (*cgs_pm_request_engine_t)(struct cgs_device *cgs_device, cgs_handle_t request, 558 enum cgs_engine engine, int powered); 559 560 /** 561 * cgs_pm_query_clock_limits() - Query clock frequency limits 562 * @cgs_device: opaque device handle 563 * @clock: which clock? 564 * @limits: clock limits 565 * 566 * Return: 0 on success, -errno otherwise 567 */ 568 typedef int (*cgs_pm_query_clock_limits_t)(struct cgs_device *cgs_device, 569 enum cgs_clock clock, 570 struct cgs_clock_limits *limits); 571 572 /** 573 * cgs_set_camera_voltages() - Apply specific voltages to PMIC voltage planes 574 * @cgs_device: opaque device handle 575 * @mask: bitmask of voltages to change (1<<CGS_VOLTAGE_PLANE__xyz|...) 576 * @voltages: pointer to array of voltage values in 1mV units 577 * 578 * Return: 0 on success, -errno otherwise 579 */ 580 typedef int (*cgs_set_camera_voltages_t)(struct cgs_device *cgs_device, uint32_t mask, 581 const uint32_t *voltages); 582 /** 583 * cgs_get_firmware_info - Get the firmware information from core driver 584 * @cgs_device: opaque device handle 585 * @type: the firmware type 586 * @info: returend firmware information 587 * 588 * Return: 0 on success, -errno otherwise 589 */ 590 typedef int (*cgs_get_firmware_info)(struct cgs_device *cgs_device, 591 enum cgs_ucode_id type, 592 struct cgs_firmware_info *info); 593 594 typedef int (*cgs_rel_firmware)(struct cgs_device *cgs_device, 595 enum cgs_ucode_id type); 596 597 typedef int(*cgs_set_powergating_state)(struct cgs_device *cgs_device, 598 enum amd_ip_block_type block_type, 599 enum amd_powergating_state state); 600 601 typedef int(*cgs_set_clockgating_state)(struct cgs_device *cgs_device, 602 enum amd_ip_block_type block_type, 603 enum amd_clockgating_state state); 604 605 typedef int(*cgs_get_active_displays_info)( 606 struct cgs_device *cgs_device, 607 struct cgs_display_info *info); 608 609 typedef int (*cgs_notify_dpm_enabled)(struct cgs_device *cgs_device, bool enabled); 610 611 typedef int (*cgs_call_acpi_method)(struct cgs_device *cgs_device, 612 uint32_t acpi_method, 613 uint32_t acpi_function, 614 void *pinput, void *poutput, 615 uint32_t output_count, 616 uint32_t input_size, 617 uint32_t output_size); 618 619 typedef int (*cgs_query_system_info)(struct cgs_device *cgs_device, 620 struct cgs_system_info *sys_info); 621 622 struct cgs_ops { 623 /* memory management calls (similar to KFD interface) */ 624 cgs_gpu_mem_info_t gpu_mem_info; 625 cgs_gmap_kmem_t gmap_kmem; 626 cgs_gunmap_kmem_t gunmap_kmem; 627 cgs_alloc_gpu_mem_t alloc_gpu_mem; 628 cgs_free_gpu_mem_t free_gpu_mem; 629 cgs_gmap_gpu_mem_t gmap_gpu_mem; 630 cgs_gunmap_gpu_mem_t gunmap_gpu_mem; 631 cgs_kmap_gpu_mem_t kmap_gpu_mem; 632 cgs_kunmap_gpu_mem_t kunmap_gpu_mem; 633 /* MMIO access */ 634 cgs_read_register_t read_register; 635 cgs_write_register_t write_register; 636 cgs_read_ind_register_t read_ind_register; 637 cgs_write_ind_register_t write_ind_register; 638 /* PCI configuration space access */ 639 cgs_read_pci_config_byte_t read_pci_config_byte; 640 cgs_read_pci_config_word_t read_pci_config_word; 641 cgs_read_pci_config_dword_t read_pci_config_dword; 642 cgs_write_pci_config_byte_t write_pci_config_byte; 643 cgs_write_pci_config_word_t write_pci_config_word; 644 cgs_write_pci_config_dword_t write_pci_config_dword; 645 /* PCI resources */ 646 cgs_get_pci_resource_t get_pci_resource; 647 /* ATOM BIOS */ 648 cgs_atom_get_data_table_t atom_get_data_table; 649 cgs_atom_get_cmd_table_revs_t atom_get_cmd_table_revs; 650 cgs_atom_exec_cmd_table_t atom_exec_cmd_table; 651 /* Power management */ 652 cgs_create_pm_request_t create_pm_request; 653 cgs_destroy_pm_request_t destroy_pm_request; 654 cgs_set_pm_request_t set_pm_request; 655 cgs_pm_request_clock_t pm_request_clock; 656 cgs_pm_request_engine_t pm_request_engine; 657 cgs_pm_query_clock_limits_t pm_query_clock_limits; 658 cgs_set_camera_voltages_t set_camera_voltages; 659 /* Firmware Info */ 660 cgs_get_firmware_info get_firmware_info; 661 cgs_rel_firmware rel_firmware; 662 /* cg pg interface*/ 663 cgs_set_powergating_state set_powergating_state; 664 cgs_set_clockgating_state set_clockgating_state; 665 /* display manager */ 666 cgs_get_active_displays_info get_active_displays_info; 667 /* notify dpm enabled */ 668 cgs_notify_dpm_enabled notify_dpm_enabled; 669 /* ACPI */ 670 cgs_call_acpi_method call_acpi_method; 671 /* get system info */ 672 cgs_query_system_info query_system_info; 673 }; 674 675 struct cgs_os_ops; /* To be define in OS-specific CGS header */ 676 677 struct cgs_device 678 { 679 const struct cgs_ops *ops; 680 const struct cgs_os_ops *os_ops; 681 /* to be embedded at the start of driver private structure */ 682 }; 683 684 /* Convenience macros that make CGS indirect function calls look like 685 * normal function calls */ 686 #define CGS_CALL(func,dev,...) \ 687 (((struct cgs_device *)dev)->ops->func(dev, ##__VA_ARGS__)) 688 #define CGS_OS_CALL(func,dev,...) \ 689 (((struct cgs_device *)dev)->os_ops->func(dev, ##__VA_ARGS__)) 690 691 #define cgs_gpu_mem_info(dev,type,mc_start,mc_size,mem_size) \ 692 CGS_CALL(gpu_mem_info,dev,type,mc_start,mc_size,mem_size) 693 #define cgs_gmap_kmem(dev,kmem,size,min_off,max_off,kmem_handle,mcaddr) \ 694 CGS_CALL(gmap_kmem,dev,kmem,size,min_off,max_off,kmem_handle,mcaddr) 695 #define cgs_gunmap_kmem(dev,kmem_handle) \ 696 CGS_CALL(gunmap_kmem,dev,keme_handle) 697 #define cgs_alloc_gpu_mem(dev,type,size,align,min_off,max_off,handle) \ 698 CGS_CALL(alloc_gpu_mem,dev,type,size,align,min_off,max_off,handle) 699 #define cgs_free_gpu_mem(dev,handle) \ 700 CGS_CALL(free_gpu_mem,dev,handle) 701 #define cgs_gmap_gpu_mem(dev,handle,mcaddr) \ 702 CGS_CALL(gmap_gpu_mem,dev,handle,mcaddr) 703 #define cgs_gunmap_gpu_mem(dev,handle) \ 704 CGS_CALL(gunmap_gpu_mem,dev,handle) 705 #define cgs_kmap_gpu_mem(dev,handle,map) \ 706 CGS_CALL(kmap_gpu_mem,dev,handle,map) 707 #define cgs_kunmap_gpu_mem(dev,handle) \ 708 CGS_CALL(kunmap_gpu_mem,dev,handle) 709 710 #define cgs_read_register(dev,offset) \ 711 CGS_CALL(read_register,dev,offset) 712 #define cgs_write_register(dev,offset,value) \ 713 CGS_CALL(write_register,dev,offset,value) 714 #define cgs_read_ind_register(dev,space,index) \ 715 CGS_CALL(read_ind_register,dev,space,index) 716 #define cgs_write_ind_register(dev,space,index,value) \ 717 CGS_CALL(write_ind_register,dev,space,index,value) 718 719 #define cgs_read_pci_config_byte(dev,addr) \ 720 CGS_CALL(read_pci_config_byte,dev,addr) 721 #define cgs_read_pci_config_word(dev,addr) \ 722 CGS_CALL(read_pci_config_word,dev,addr) 723 #define cgs_read_pci_config_dword(dev,addr) \ 724 CGS_CALL(read_pci_config_dword,dev,addr) 725 #define cgs_write_pci_config_byte(dev,addr,value) \ 726 CGS_CALL(write_pci_config_byte,dev,addr,value) 727 #define cgs_write_pci_config_word(dev,addr,value) \ 728 CGS_CALL(write_pci_config_word,dev,addr,value) 729 #define cgs_write_pci_config_dword(dev,addr,value) \ 730 CGS_CALL(write_pci_config_dword,dev,addr,value) 731 732 #define cgs_atom_get_data_table(dev,table,size,frev,crev) \ 733 CGS_CALL(atom_get_data_table,dev,table,size,frev,crev) 734 #define cgs_atom_get_cmd_table_revs(dev,table,frev,crev) \ 735 CGS_CALL(atom_get_cmd_table_revs,dev,table,frev,crev) 736 #define cgs_atom_exec_cmd_table(dev,table,args) \ 737 CGS_CALL(atom_exec_cmd_table,dev,table,args) 738 739 #define cgs_create_pm_request(dev,request) \ 740 CGS_CALL(create_pm_request,dev,request) 741 #define cgs_destroy_pm_request(dev,request) \ 742 CGS_CALL(destroy_pm_request,dev,request) 743 #define cgs_set_pm_request(dev,request,active) \ 744 CGS_CALL(set_pm_request,dev,request,active) 745 #define cgs_pm_request_clock(dev,request,clock,freq) \ 746 CGS_CALL(pm_request_clock,dev,request,clock,freq) 747 #define cgs_pm_request_engine(dev,request,engine,powered) \ 748 CGS_CALL(pm_request_engine,dev,request,engine,powered) 749 #define cgs_pm_query_clock_limits(dev,clock,limits) \ 750 CGS_CALL(pm_query_clock_limits,dev,clock,limits) 751 #define cgs_set_camera_voltages(dev,mask,voltages) \ 752 CGS_CALL(set_camera_voltages,dev,mask,voltages) 753 #define cgs_get_firmware_info(dev, type, info) \ 754 CGS_CALL(get_firmware_info, dev, type, info) 755 #define cgs_rel_firmware(dev, type) \ 756 CGS_CALL(rel_firmware, dev, type) 757 #define cgs_set_powergating_state(dev, block_type, state) \ 758 CGS_CALL(set_powergating_state, dev, block_type, state) 759 #define cgs_set_clockgating_state(dev, block_type, state) \ 760 CGS_CALL(set_clockgating_state, dev, block_type, state) 761 #define cgs_notify_dpm_enabled(dev, enabled) \ 762 CGS_CALL(notify_dpm_enabled, dev, enabled) 763 764 #define cgs_get_active_displays_info(dev, info) \ 765 CGS_CALL(get_active_displays_info, dev, info) 766 767 #define cgs_call_acpi_method(dev, acpi_method, acpi_function, pintput, poutput, output_count, input_size, output_size) \ 768 CGS_CALL(call_acpi_method, dev, acpi_method, acpi_function, pintput, poutput, output_count, input_size, output_size) 769 #define cgs_query_system_info(dev, sys_info) \ 770 CGS_CALL(query_system_info, dev, sys_info) 771 #define cgs_get_pci_resource(cgs_device, resource_type, size, offset, \ 772 resource_base) \ 773 CGS_CALL(get_pci_resource, cgs_device, resource_type, size, offset, \ 774 resource_base) 775 776 #endif /* _CGS_COMMON_H */ 777