1 /* 2 * Copyright 2015 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * 23 */ 24 #ifndef _CGS_COMMON_H 25 #define _CGS_COMMON_H 26 27 #include "amd_shared.h" 28 29 struct cgs_device; 30 31 /** 32 * enum cgs_gpu_mem_type - GPU memory types 33 */ 34 enum cgs_gpu_mem_type { 35 CGS_GPU_MEM_TYPE__VISIBLE_FB, 36 CGS_GPU_MEM_TYPE__INVISIBLE_FB, 37 CGS_GPU_MEM_TYPE__VISIBLE_CONTIG_FB, 38 CGS_GPU_MEM_TYPE__INVISIBLE_CONTIG_FB, 39 CGS_GPU_MEM_TYPE__GART_CACHEABLE, 40 CGS_GPU_MEM_TYPE__GART_WRITECOMBINE 41 }; 42 43 /** 44 * enum cgs_ind_reg - Indirect register spaces 45 */ 46 enum cgs_ind_reg { 47 CGS_IND_REG__MMIO, 48 CGS_IND_REG__PCIE, 49 CGS_IND_REG__SMC, 50 CGS_IND_REG__UVD_CTX, 51 CGS_IND_REG__DIDT, 52 CGS_IND_REG_GC_CAC, 53 CGS_IND_REG_SE_CAC, 54 CGS_IND_REG__AUDIO_ENDPT 55 }; 56 57 /** 58 * enum cgs_engine - Engines that can be statically power-gated 59 */ 60 enum cgs_engine { 61 CGS_ENGINE__UVD, 62 CGS_ENGINE__VCE, 63 CGS_ENGINE__VP8, 64 CGS_ENGINE__ACP_DMA, 65 CGS_ENGINE__ACP_DSP0, 66 CGS_ENGINE__ACP_DSP1, 67 CGS_ENGINE__ISP, 68 /* ... */ 69 }; 70 71 /* 72 * enum cgs_ucode_id - Firmware types for different IPs 73 */ 74 enum cgs_ucode_id { 75 CGS_UCODE_ID_SMU = 0, 76 CGS_UCODE_ID_SMU_SK, 77 CGS_UCODE_ID_SDMA0, 78 CGS_UCODE_ID_SDMA1, 79 CGS_UCODE_ID_CP_CE, 80 CGS_UCODE_ID_CP_PFP, 81 CGS_UCODE_ID_CP_ME, 82 CGS_UCODE_ID_CP_MEC, 83 CGS_UCODE_ID_CP_MEC_JT1, 84 CGS_UCODE_ID_CP_MEC_JT2, 85 CGS_UCODE_ID_GMCON_RENG, 86 CGS_UCODE_ID_RLC_G, 87 CGS_UCODE_ID_STORAGE, 88 CGS_UCODE_ID_MAXIMUM, 89 }; 90 91 enum cgs_system_info_id { 92 CGS_SYSTEM_INFO_ADAPTER_BDF_ID = 1, 93 CGS_SYSTEM_INFO_PCIE_GEN_INFO, 94 CGS_SYSTEM_INFO_PCIE_MLW, 95 CGS_SYSTEM_INFO_PCIE_DEV, 96 CGS_SYSTEM_INFO_PCIE_REV, 97 CGS_SYSTEM_INFO_CG_FLAGS, 98 CGS_SYSTEM_INFO_PG_FLAGS, 99 CGS_SYSTEM_INFO_GFX_CU_INFO, 100 CGS_SYSTEM_INFO_GFX_SE_INFO, 101 CGS_SYSTEM_INFO_PCIE_SUB_SYS_ID, 102 CGS_SYSTEM_INFO_PCIE_SUB_SYS_VENDOR_ID, 103 CGS_SYSTEM_INFO_ID_MAXIMUM, 104 }; 105 106 struct cgs_system_info { 107 uint64_t size; 108 enum cgs_system_info_id info_id; 109 union { 110 void *ptr; 111 uint64_t value; 112 }; 113 uint64_t padding[13]; 114 }; 115 116 /* 117 * enum cgs_resource_type - GPU resource type 118 */ 119 enum cgs_resource_type { 120 CGS_RESOURCE_TYPE_MMIO = 0, 121 CGS_RESOURCE_TYPE_FB, 122 CGS_RESOURCE_TYPE_IO, 123 CGS_RESOURCE_TYPE_DOORBELL, 124 CGS_RESOURCE_TYPE_ROM, 125 }; 126 127 /** 128 * struct cgs_firmware_info - Firmware information 129 */ 130 struct cgs_firmware_info { 131 uint16_t version; 132 uint16_t fw_version; 133 uint16_t feature_version; 134 uint32_t image_size; 135 uint64_t mc_addr; 136 137 /* only for smc firmware */ 138 uint32_t ucode_start_address; 139 140 void *kptr; 141 bool is_kicker; 142 }; 143 144 struct cgs_mode_info { 145 uint32_t refresh_rate; 146 uint32_t ref_clock; 147 uint32_t vblank_time_us; 148 }; 149 150 struct cgs_display_info { 151 uint32_t display_count; 152 uint32_t active_display_mask; 153 struct cgs_mode_info *mode_info; 154 }; 155 156 typedef unsigned long cgs_handle_t; 157 158 #define CGS_ACPI_METHOD_ATCS 0x53435441 159 #define CGS_ACPI_METHOD_ATIF 0x46495441 160 #define CGS_ACPI_METHOD_ATPX 0x58505441 161 #define CGS_ACPI_FIELD_METHOD_NAME 0x00000001 162 #define CGS_ACPI_FIELD_INPUT_ARGUMENT_COUNT 0x00000002 163 #define CGS_ACPI_MAX_BUFFER_SIZE 256 164 #define CGS_ACPI_TYPE_ANY 0x00 165 #define CGS_ACPI_TYPE_INTEGER 0x01 166 #define CGS_ACPI_TYPE_STRING 0x02 167 #define CGS_ACPI_TYPE_BUFFER 0x03 168 #define CGS_ACPI_TYPE_PACKAGE 0x04 169 170 struct cgs_acpi_method_argument { 171 uint32_t type; 172 uint32_t data_length; 173 union{ 174 uint32_t value; 175 void *pointer; 176 }; 177 }; 178 179 struct cgs_acpi_method_info { 180 uint32_t size; 181 uint32_t field; 182 uint32_t input_count; 183 uint32_t name; 184 struct cgs_acpi_method_argument *pinput_argument; 185 uint32_t output_count; 186 struct cgs_acpi_method_argument *poutput_argument; 187 uint32_t padding[9]; 188 }; 189 190 /** 191 * cgs_alloc_gpu_mem() - Allocate GPU memory 192 * @cgs_device: opaque device handle 193 * @type: memory type 194 * @size: size in bytes 195 * @align: alignment in bytes 196 * @min_offset: minimum offset from start of heap 197 * @max_offset: maximum offset from start of heap 198 * @handle: memory handle (output) 199 * 200 * The memory types CGS_GPU_MEM_TYPE_*_CONTIG_FB force contiguous 201 * memory allocation. This guarantees that the MC address returned by 202 * cgs_gmap_gpu_mem is not mapped through the GART. The non-contiguous 203 * FB memory types may be GART mapped depending on memory 204 * fragmentation and memory allocator policies. 205 * 206 * If min/max_offset are non-0, the allocation will be forced to 207 * reside between these offsets in its respective memory heap. The 208 * base address that the offset relates to, depends on the memory 209 * type. 210 * 211 * - CGS_GPU_MEM_TYPE__*_CONTIG_FB: FB MC base address 212 * - CGS_GPU_MEM_TYPE__GART_*: GART aperture base address 213 * - others: undefined, don't use with max_offset 214 * 215 * Return: 0 on success, -errno otherwise 216 */ 217 typedef int (*cgs_alloc_gpu_mem_t)(struct cgs_device *cgs_device, enum cgs_gpu_mem_type type, 218 uint64_t size, uint64_t align, 219 uint64_t min_offset, uint64_t max_offset, 220 cgs_handle_t *handle); 221 222 /** 223 * cgs_free_gpu_mem() - Free GPU memory 224 * @cgs_device: opaque device handle 225 * @handle: memory handle returned by alloc or import 226 * 227 * Return: 0 on success, -errno otherwise 228 */ 229 typedef int (*cgs_free_gpu_mem_t)(struct cgs_device *cgs_device, cgs_handle_t handle); 230 231 /** 232 * cgs_gmap_gpu_mem() - GPU-map GPU memory 233 * @cgs_device: opaque device handle 234 * @handle: memory handle returned by alloc or import 235 * @mcaddr: MC address (output) 236 * 237 * Ensures that a buffer is GPU accessible and returns its MC address. 238 * 239 * Return: 0 on success, -errno otherwise 240 */ 241 typedef int (*cgs_gmap_gpu_mem_t)(struct cgs_device *cgs_device, cgs_handle_t handle, 242 uint64_t *mcaddr); 243 244 /** 245 * cgs_gunmap_gpu_mem() - GPU-unmap GPU memory 246 * @cgs_device: opaque device handle 247 * @handle: memory handle returned by alloc or import 248 * 249 * Allows the buffer to be migrated while it's not used by the GPU. 250 * 251 * Return: 0 on success, -errno otherwise 252 */ 253 typedef int (*cgs_gunmap_gpu_mem_t)(struct cgs_device *cgs_device, cgs_handle_t handle); 254 255 /** 256 * cgs_kmap_gpu_mem() - Kernel-map GPU memory 257 * 258 * @cgs_device: opaque device handle 259 * @handle: memory handle returned by alloc or import 260 * @map: Kernel virtual address the memory was mapped to (output) 261 * 262 * Return: 0 on success, -errno otherwise 263 */ 264 typedef int (*cgs_kmap_gpu_mem_t)(struct cgs_device *cgs_device, cgs_handle_t handle, 265 void **map); 266 267 /** 268 * cgs_kunmap_gpu_mem() - Kernel-unmap GPU memory 269 * @cgs_device: opaque device handle 270 * @handle: memory handle returned by alloc or import 271 * 272 * Return: 0 on success, -errno otherwise 273 */ 274 typedef int (*cgs_kunmap_gpu_mem_t)(struct cgs_device *cgs_device, cgs_handle_t handle); 275 276 /** 277 * cgs_read_register() - Read an MMIO register 278 * @cgs_device: opaque device handle 279 * @offset: register offset 280 * 281 * Return: register value 282 */ 283 typedef uint32_t (*cgs_read_register_t)(struct cgs_device *cgs_device, unsigned offset); 284 285 /** 286 * cgs_write_register() - Write an MMIO register 287 * @cgs_device: opaque device handle 288 * @offset: register offset 289 * @value: register value 290 */ 291 typedef void (*cgs_write_register_t)(struct cgs_device *cgs_device, unsigned offset, 292 uint32_t value); 293 294 /** 295 * cgs_read_ind_register() - Read an indirect register 296 * @cgs_device: opaque device handle 297 * @offset: register offset 298 * 299 * Return: register value 300 */ 301 typedef uint32_t (*cgs_read_ind_register_t)(struct cgs_device *cgs_device, enum cgs_ind_reg space, 302 unsigned index); 303 304 /** 305 * cgs_write_ind_register() - Write an indirect register 306 * @cgs_device: opaque device handle 307 * @offset: register offset 308 * @value: register value 309 */ 310 typedef void (*cgs_write_ind_register_t)(struct cgs_device *cgs_device, enum cgs_ind_reg space, 311 unsigned index, uint32_t value); 312 313 /** 314 * cgs_get_pci_resource() - provide access to a device resource (PCI BAR) 315 * @cgs_device: opaque device handle 316 * @resource_type: Type of Resource (MMIO, IO, ROM, FB, DOORBELL) 317 * @size: size of the region 318 * @offset: offset from the start of the region 319 * @resource_base: base address (not including offset) returned 320 * 321 * Return: 0 on success, -errno otherwise 322 */ 323 typedef int (*cgs_get_pci_resource_t)(struct cgs_device *cgs_device, 324 enum cgs_resource_type resource_type, 325 uint64_t size, 326 uint64_t offset, 327 uint64_t *resource_base); 328 329 /** 330 * cgs_atom_get_data_table() - Get a pointer to an ATOM BIOS data table 331 * @cgs_device: opaque device handle 332 * @table: data table index 333 * @size: size of the table (output, may be NULL) 334 * @frev: table format revision (output, may be NULL) 335 * @crev: table content revision (output, may be NULL) 336 * 337 * Return: Pointer to start of the table, or NULL on failure 338 */ 339 typedef const void *(*cgs_atom_get_data_table_t)( 340 struct cgs_device *cgs_device, unsigned table, 341 uint16_t *size, uint8_t *frev, uint8_t *crev); 342 343 /** 344 * cgs_atom_get_cmd_table_revs() - Get ATOM BIOS command table revisions 345 * @cgs_device: opaque device handle 346 * @table: data table index 347 * @frev: table format revision (output, may be NULL) 348 * @crev: table content revision (output, may be NULL) 349 * 350 * Return: 0 on success, -errno otherwise 351 */ 352 typedef int (*cgs_atom_get_cmd_table_revs_t)(struct cgs_device *cgs_device, unsigned table, 353 uint8_t *frev, uint8_t *crev); 354 355 /** 356 * cgs_atom_exec_cmd_table() - Execute an ATOM BIOS command table 357 * @cgs_device: opaque device handle 358 * @table: command table index 359 * @args: arguments 360 * 361 * Return: 0 on success, -errno otherwise 362 */ 363 typedef int (*cgs_atom_exec_cmd_table_t)(struct cgs_device *cgs_device, 364 unsigned table, void *args); 365 366 /** 367 * cgs_get_firmware_info - Get the firmware information from core driver 368 * @cgs_device: opaque device handle 369 * @type: the firmware type 370 * @info: returend firmware information 371 * 372 * Return: 0 on success, -errno otherwise 373 */ 374 typedef int (*cgs_get_firmware_info)(struct cgs_device *cgs_device, 375 enum cgs_ucode_id type, 376 struct cgs_firmware_info *info); 377 378 typedef int (*cgs_rel_firmware)(struct cgs_device *cgs_device, 379 enum cgs_ucode_id type); 380 381 typedef int(*cgs_set_powergating_state)(struct cgs_device *cgs_device, 382 enum amd_ip_block_type block_type, 383 enum amd_powergating_state state); 384 385 typedef int(*cgs_set_clockgating_state)(struct cgs_device *cgs_device, 386 enum amd_ip_block_type block_type, 387 enum amd_clockgating_state state); 388 389 typedef int(*cgs_get_active_displays_info)( 390 struct cgs_device *cgs_device, 391 struct cgs_display_info *info); 392 393 typedef int (*cgs_notify_dpm_enabled)(struct cgs_device *cgs_device, bool enabled); 394 395 typedef int (*cgs_call_acpi_method)(struct cgs_device *cgs_device, 396 uint32_t acpi_method, 397 uint32_t acpi_function, 398 void *pinput, void *poutput, 399 uint32_t output_count, 400 uint32_t input_size, 401 uint32_t output_size); 402 403 typedef int (*cgs_query_system_info)(struct cgs_device *cgs_device, 404 struct cgs_system_info *sys_info); 405 406 typedef int (*cgs_is_virtualization_enabled_t)(void *cgs_device); 407 408 typedef int (*cgs_enter_safe_mode)(struct cgs_device *cgs_device, bool en); 409 410 typedef void (*cgs_lock_grbm_idx)(struct cgs_device *cgs_device, bool lock); 411 412 struct cgs_ops { 413 /* memory management calls (similar to KFD interface) */ 414 cgs_alloc_gpu_mem_t alloc_gpu_mem; 415 cgs_free_gpu_mem_t free_gpu_mem; 416 cgs_gmap_gpu_mem_t gmap_gpu_mem; 417 cgs_gunmap_gpu_mem_t gunmap_gpu_mem; 418 cgs_kmap_gpu_mem_t kmap_gpu_mem; 419 cgs_kunmap_gpu_mem_t kunmap_gpu_mem; 420 /* MMIO access */ 421 cgs_read_register_t read_register; 422 cgs_write_register_t write_register; 423 cgs_read_ind_register_t read_ind_register; 424 cgs_write_ind_register_t write_ind_register; 425 /* PCI resources */ 426 cgs_get_pci_resource_t get_pci_resource; 427 /* ATOM BIOS */ 428 cgs_atom_get_data_table_t atom_get_data_table; 429 cgs_atom_get_cmd_table_revs_t atom_get_cmd_table_revs; 430 cgs_atom_exec_cmd_table_t atom_exec_cmd_table; 431 /* Firmware Info */ 432 cgs_get_firmware_info get_firmware_info; 433 cgs_rel_firmware rel_firmware; 434 /* cg pg interface*/ 435 cgs_set_powergating_state set_powergating_state; 436 cgs_set_clockgating_state set_clockgating_state; 437 /* display manager */ 438 cgs_get_active_displays_info get_active_displays_info; 439 /* notify dpm enabled */ 440 cgs_notify_dpm_enabled notify_dpm_enabled; 441 /* ACPI */ 442 cgs_call_acpi_method call_acpi_method; 443 /* get system info */ 444 cgs_query_system_info query_system_info; 445 cgs_is_virtualization_enabled_t is_virtualization_enabled; 446 cgs_enter_safe_mode enter_safe_mode; 447 cgs_lock_grbm_idx lock_grbm_idx; 448 }; 449 450 struct cgs_os_ops; /* To be define in OS-specific CGS header */ 451 452 struct cgs_device 453 { 454 const struct cgs_ops *ops; 455 const struct cgs_os_ops *os_ops; 456 /* to be embedded at the start of driver private structure */ 457 }; 458 459 /* Convenience macros that make CGS indirect function calls look like 460 * normal function calls */ 461 #define CGS_CALL(func,dev,...) \ 462 (((struct cgs_device *)dev)->ops->func(dev, ##__VA_ARGS__)) 463 #define CGS_OS_CALL(func,dev,...) \ 464 (((struct cgs_device *)dev)->os_ops->func(dev, ##__VA_ARGS__)) 465 466 #define cgs_alloc_gpu_mem(dev,type,size,align,min_off,max_off,handle) \ 467 CGS_CALL(alloc_gpu_mem,dev,type,size,align,min_off,max_off,handle) 468 #define cgs_free_gpu_mem(dev,handle) \ 469 CGS_CALL(free_gpu_mem,dev,handle) 470 #define cgs_gmap_gpu_mem(dev,handle,mcaddr) \ 471 CGS_CALL(gmap_gpu_mem,dev,handle,mcaddr) 472 #define cgs_gunmap_gpu_mem(dev,handle) \ 473 CGS_CALL(gunmap_gpu_mem,dev,handle) 474 #define cgs_kmap_gpu_mem(dev,handle,map) \ 475 CGS_CALL(kmap_gpu_mem,dev,handle,map) 476 #define cgs_kunmap_gpu_mem(dev,handle) \ 477 CGS_CALL(kunmap_gpu_mem,dev,handle) 478 479 #define cgs_read_register(dev,offset) \ 480 CGS_CALL(read_register,dev,offset) 481 #define cgs_write_register(dev,offset,value) \ 482 CGS_CALL(write_register,dev,offset,value) 483 #define cgs_read_ind_register(dev,space,index) \ 484 CGS_CALL(read_ind_register,dev,space,index) 485 #define cgs_write_ind_register(dev,space,index,value) \ 486 CGS_CALL(write_ind_register,dev,space,index,value) 487 488 #define cgs_atom_get_data_table(dev,table,size,frev,crev) \ 489 CGS_CALL(atom_get_data_table,dev,table,size,frev,crev) 490 #define cgs_atom_get_cmd_table_revs(dev,table,frev,crev) \ 491 CGS_CALL(atom_get_cmd_table_revs,dev,table,frev,crev) 492 #define cgs_atom_exec_cmd_table(dev,table,args) \ 493 CGS_CALL(atom_exec_cmd_table,dev,table,args) 494 495 #define cgs_get_firmware_info(dev, type, info) \ 496 CGS_CALL(get_firmware_info, dev, type, info) 497 #define cgs_rel_firmware(dev, type) \ 498 CGS_CALL(rel_firmware, dev, type) 499 #define cgs_set_powergating_state(dev, block_type, state) \ 500 CGS_CALL(set_powergating_state, dev, block_type, state) 501 #define cgs_set_clockgating_state(dev, block_type, state) \ 502 CGS_CALL(set_clockgating_state, dev, block_type, state) 503 #define cgs_notify_dpm_enabled(dev, enabled) \ 504 CGS_CALL(notify_dpm_enabled, dev, enabled) 505 506 #define cgs_get_active_displays_info(dev, info) \ 507 CGS_CALL(get_active_displays_info, dev, info) 508 509 #define cgs_call_acpi_method(dev, acpi_method, acpi_function, pintput, poutput, output_count, input_size, output_size) \ 510 CGS_CALL(call_acpi_method, dev, acpi_method, acpi_function, pintput, poutput, output_count, input_size, output_size) 511 #define cgs_query_system_info(dev, sys_info) \ 512 CGS_CALL(query_system_info, dev, sys_info) 513 #define cgs_get_pci_resource(cgs_device, resource_type, size, offset, \ 514 resource_base) \ 515 CGS_CALL(get_pci_resource, cgs_device, resource_type, size, offset, \ 516 resource_base) 517 518 #define cgs_is_virtualization_enabled(cgs_device) \ 519 CGS_CALL(is_virtualization_enabled, cgs_device) 520 521 #define cgs_enter_safe_mode(cgs_device, en) \ 522 CGS_CALL(enter_safe_mode, cgs_device, en) 523 524 #define cgs_lock_grbm_idx(cgs_device, lock) \ 525 CGS_CALL(lock_grbm_idx, cgs_device, lock) 526 #endif /* _CGS_COMMON_H */ 527