1 /* 2 * Copyright 2015 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * 23 */ 24 #ifndef _CGS_COMMON_H 25 #define _CGS_COMMON_H 26 27 #include "amd_shared.h" 28 29 /** 30 * enum cgs_gpu_mem_type - GPU memory types 31 */ 32 enum cgs_gpu_mem_type { 33 CGS_GPU_MEM_TYPE__VISIBLE_FB, 34 CGS_GPU_MEM_TYPE__INVISIBLE_FB, 35 CGS_GPU_MEM_TYPE__VISIBLE_CONTIG_FB, 36 CGS_GPU_MEM_TYPE__INVISIBLE_CONTIG_FB, 37 CGS_GPU_MEM_TYPE__GART_CACHEABLE, 38 CGS_GPU_MEM_TYPE__GART_WRITECOMBINE 39 }; 40 41 /** 42 * enum cgs_ind_reg - Indirect register spaces 43 */ 44 enum cgs_ind_reg { 45 CGS_IND_REG__MMIO, 46 CGS_IND_REG__PCIE, 47 CGS_IND_REG__SMC, 48 CGS_IND_REG__UVD_CTX, 49 CGS_IND_REG__DIDT, 50 CGS_IND_REG__AUDIO_ENDPT 51 }; 52 53 /** 54 * enum cgs_clock - Clocks controlled by the SMU 55 */ 56 enum cgs_clock { 57 CGS_CLOCK__SCLK, 58 CGS_CLOCK__MCLK, 59 CGS_CLOCK__VCLK, 60 CGS_CLOCK__DCLK, 61 CGS_CLOCK__ECLK, 62 CGS_CLOCK__ACLK, 63 CGS_CLOCK__ICLK, 64 /* ... */ 65 }; 66 67 /** 68 * enum cgs_engine - Engines that can be statically power-gated 69 */ 70 enum cgs_engine { 71 CGS_ENGINE__UVD, 72 CGS_ENGINE__VCE, 73 CGS_ENGINE__VP8, 74 CGS_ENGINE__ACP_DMA, 75 CGS_ENGINE__ACP_DSP0, 76 CGS_ENGINE__ACP_DSP1, 77 CGS_ENGINE__ISP, 78 /* ... */ 79 }; 80 81 /** 82 * enum cgs_voltage_planes - Voltage planes for external camera HW 83 */ 84 enum cgs_voltage_planes { 85 CGS_VOLTAGE_PLANE__SENSOR0, 86 CGS_VOLTAGE_PLANE__SENSOR1, 87 /* ... */ 88 }; 89 90 /* 91 * enum cgs_ucode_id - Firmware types for different IPs 92 */ 93 enum cgs_ucode_id { 94 CGS_UCODE_ID_SMU = 0, 95 CGS_UCODE_ID_SDMA0, 96 CGS_UCODE_ID_SDMA1, 97 CGS_UCODE_ID_CP_CE, 98 CGS_UCODE_ID_CP_PFP, 99 CGS_UCODE_ID_CP_ME, 100 CGS_UCODE_ID_CP_MEC, 101 CGS_UCODE_ID_CP_MEC_JT1, 102 CGS_UCODE_ID_CP_MEC_JT2, 103 CGS_UCODE_ID_GMCON_RENG, 104 CGS_UCODE_ID_RLC_G, 105 CGS_UCODE_ID_MAXIMUM, 106 }; 107 108 enum cgs_system_info_id { 109 CGS_SYSTEM_INFO_ADAPTER_BDF_ID = 1, 110 CGS_SYSTEM_INFO_PCIE_GEN_INFO, 111 CGS_SYSTEM_INFO_PCIE_MLW, 112 CGS_SYSTEM_INFO_CG_FLAGS, 113 CGS_SYSTEM_INFO_PG_FLAGS, 114 CGS_SYSTEM_INFO_ID_MAXIMUM, 115 }; 116 117 struct cgs_system_info { 118 uint64_t size; 119 uint64_t info_id; 120 union { 121 void *ptr; 122 uint64_t value; 123 }; 124 uint64_t padding[13]; 125 }; 126 127 /* 128 * enum cgs_resource_type - GPU resource type 129 */ 130 enum cgs_resource_type { 131 CGS_RESOURCE_TYPE_MMIO = 0, 132 CGS_RESOURCE_TYPE_FB, 133 CGS_RESOURCE_TYPE_IO, 134 CGS_RESOURCE_TYPE_DOORBELL, 135 CGS_RESOURCE_TYPE_ROM, 136 }; 137 138 /** 139 * struct cgs_clock_limits - Clock limits 140 * 141 * Clocks are specified in 10KHz units. 142 */ 143 struct cgs_clock_limits { 144 unsigned min; /**< Minimum supported frequency */ 145 unsigned max; /**< Maxumim supported frequency */ 146 unsigned sustainable; /**< Thermally sustainable frequency */ 147 }; 148 149 /** 150 * struct cgs_firmware_info - Firmware information 151 */ 152 struct cgs_firmware_info { 153 uint16_t version; 154 uint16_t feature_version; 155 uint32_t image_size; 156 uint64_t mc_addr; 157 void *kptr; 158 }; 159 160 struct cgs_mode_info { 161 uint32_t refresh_rate; 162 uint32_t ref_clock; 163 uint32_t vblank_time_us; 164 }; 165 166 struct cgs_display_info { 167 uint32_t display_count; 168 uint32_t active_display_mask; 169 struct cgs_mode_info *mode_info; 170 }; 171 172 typedef unsigned long cgs_handle_t; 173 174 #define CGS_ACPI_METHOD_ATCS 0x53435441 175 #define CGS_ACPI_METHOD_ATIF 0x46495441 176 #define CGS_ACPI_METHOD_ATPX 0x58505441 177 #define CGS_ACPI_FIELD_METHOD_NAME 0x00000001 178 #define CGS_ACPI_FIELD_INPUT_ARGUMENT_COUNT 0x00000002 179 #define CGS_ACPI_MAX_BUFFER_SIZE 256 180 #define CGS_ACPI_TYPE_ANY 0x00 181 #define CGS_ACPI_TYPE_INTEGER 0x01 182 #define CGS_ACPI_TYPE_STRING 0x02 183 #define CGS_ACPI_TYPE_BUFFER 0x03 184 #define CGS_ACPI_TYPE_PACKAGE 0x04 185 186 struct cgs_acpi_method_argument { 187 uint32_t type; 188 uint32_t method_length; 189 uint32_t data_length; 190 union{ 191 uint32_t value; 192 void *pointer; 193 }; 194 }; 195 196 struct cgs_acpi_method_info { 197 uint32_t size; 198 uint32_t field; 199 uint32_t input_count; 200 uint32_t name; 201 struct cgs_acpi_method_argument *pinput_argument; 202 uint32_t output_count; 203 struct cgs_acpi_method_argument *poutput_argument; 204 uint32_t padding[9]; 205 }; 206 207 /** 208 * cgs_gpu_mem_info() - Return information about memory heaps 209 * @cgs_device: opaque device handle 210 * @type: memory type 211 * @mc_start: Start MC address of the heap (output) 212 * @mc_size: MC address space size (output) 213 * @mem_size: maximum amount of memory available for allocation (output) 214 * 215 * This function returns information about memory heaps. The type 216 * parameter is used to select the memory heap. The mc_start and 217 * mc_size for GART heaps may be bigger than the memory available for 218 * allocation. 219 * 220 * mc_start and mc_size are undefined for non-contiguous FB memory 221 * types, since buffers allocated with these types may or may not be 222 * GART mapped. 223 * 224 * Return: 0 on success, -errno otherwise 225 */ 226 typedef int (*cgs_gpu_mem_info_t)(void *cgs_device, enum cgs_gpu_mem_type type, 227 uint64_t *mc_start, uint64_t *mc_size, 228 uint64_t *mem_size); 229 230 /** 231 * cgs_gmap_kmem() - map kernel memory to GART aperture 232 * @cgs_device: opaque device handle 233 * @kmem: pointer to kernel memory 234 * @size: size to map 235 * @min_offset: minimum offset from start of GART aperture 236 * @max_offset: maximum offset from start of GART aperture 237 * @kmem_handle: kernel memory handle (output) 238 * @mcaddr: MC address (output) 239 * 240 * Return: 0 on success, -errno otherwise 241 */ 242 typedef int (*cgs_gmap_kmem_t)(void *cgs_device, void *kmem, uint64_t size, 243 uint64_t min_offset, uint64_t max_offset, 244 cgs_handle_t *kmem_handle, uint64_t *mcaddr); 245 246 /** 247 * cgs_gunmap_kmem() - unmap kernel memory 248 * @cgs_device: opaque device handle 249 * @kmem_handle: kernel memory handle returned by gmap_kmem 250 * 251 * Return: 0 on success, -errno otherwise 252 */ 253 typedef int (*cgs_gunmap_kmem_t)(void *cgs_device, cgs_handle_t kmem_handle); 254 255 /** 256 * cgs_alloc_gpu_mem() - Allocate GPU memory 257 * @cgs_device: opaque device handle 258 * @type: memory type 259 * @size: size in bytes 260 * @align: alignment in bytes 261 * @min_offset: minimum offset from start of heap 262 * @max_offset: maximum offset from start of heap 263 * @handle: memory handle (output) 264 * 265 * The memory types CGS_GPU_MEM_TYPE_*_CONTIG_FB force contiguous 266 * memory allocation. This guarantees that the MC address returned by 267 * cgs_gmap_gpu_mem is not mapped through the GART. The non-contiguous 268 * FB memory types may be GART mapped depending on memory 269 * fragmentation and memory allocator policies. 270 * 271 * If min/max_offset are non-0, the allocation will be forced to 272 * reside between these offsets in its respective memory heap. The 273 * base address that the offset relates to, depends on the memory 274 * type. 275 * 276 * - CGS_GPU_MEM_TYPE__*_CONTIG_FB: FB MC base address 277 * - CGS_GPU_MEM_TYPE__GART_*: GART aperture base address 278 * - others: undefined, don't use with max_offset 279 * 280 * Return: 0 on success, -errno otherwise 281 */ 282 typedef int (*cgs_alloc_gpu_mem_t)(void *cgs_device, enum cgs_gpu_mem_type type, 283 uint64_t size, uint64_t align, 284 uint64_t min_offset, uint64_t max_offset, 285 cgs_handle_t *handle); 286 287 /** 288 * cgs_free_gpu_mem() - Free GPU memory 289 * @cgs_device: opaque device handle 290 * @handle: memory handle returned by alloc or import 291 * 292 * Return: 0 on success, -errno otherwise 293 */ 294 typedef int (*cgs_free_gpu_mem_t)(void *cgs_device, cgs_handle_t handle); 295 296 /** 297 * cgs_gmap_gpu_mem() - GPU-map GPU memory 298 * @cgs_device: opaque device handle 299 * @handle: memory handle returned by alloc or import 300 * @mcaddr: MC address (output) 301 * 302 * Ensures that a buffer is GPU accessible and returns its MC address. 303 * 304 * Return: 0 on success, -errno otherwise 305 */ 306 typedef int (*cgs_gmap_gpu_mem_t)(void *cgs_device, cgs_handle_t handle, 307 uint64_t *mcaddr); 308 309 /** 310 * cgs_gunmap_gpu_mem() - GPU-unmap GPU memory 311 * @cgs_device: opaque device handle 312 * @handle: memory handle returned by alloc or import 313 * 314 * Allows the buffer to be migrated while it's not used by the GPU. 315 * 316 * Return: 0 on success, -errno otherwise 317 */ 318 typedef int (*cgs_gunmap_gpu_mem_t)(void *cgs_device, cgs_handle_t handle); 319 320 /** 321 * cgs_kmap_gpu_mem() - Kernel-map GPU memory 322 * 323 * @cgs_device: opaque device handle 324 * @handle: memory handle returned by alloc or import 325 * @map: Kernel virtual address the memory was mapped to (output) 326 * 327 * Return: 0 on success, -errno otherwise 328 */ 329 typedef int (*cgs_kmap_gpu_mem_t)(void *cgs_device, cgs_handle_t handle, 330 void **map); 331 332 /** 333 * cgs_kunmap_gpu_mem() - Kernel-unmap GPU memory 334 * @cgs_device: opaque device handle 335 * @handle: memory handle returned by alloc or import 336 * 337 * Return: 0 on success, -errno otherwise 338 */ 339 typedef int (*cgs_kunmap_gpu_mem_t)(void *cgs_device, cgs_handle_t handle); 340 341 /** 342 * cgs_read_register() - Read an MMIO register 343 * @cgs_device: opaque device handle 344 * @offset: register offset 345 * 346 * Return: register value 347 */ 348 typedef uint32_t (*cgs_read_register_t)(void *cgs_device, unsigned offset); 349 350 /** 351 * cgs_write_register() - Write an MMIO register 352 * @cgs_device: opaque device handle 353 * @offset: register offset 354 * @value: register value 355 */ 356 typedef void (*cgs_write_register_t)(void *cgs_device, unsigned offset, 357 uint32_t value); 358 359 /** 360 * cgs_read_ind_register() - Read an indirect register 361 * @cgs_device: opaque device handle 362 * @offset: register offset 363 * 364 * Return: register value 365 */ 366 typedef uint32_t (*cgs_read_ind_register_t)(void *cgs_device, enum cgs_ind_reg space, 367 unsigned index); 368 369 /** 370 * cgs_write_ind_register() - Write an indirect register 371 * @cgs_device: opaque device handle 372 * @offset: register offset 373 * @value: register value 374 */ 375 typedef void (*cgs_write_ind_register_t)(void *cgs_device, enum cgs_ind_reg space, 376 unsigned index, uint32_t value); 377 378 /** 379 * cgs_read_pci_config_byte() - Read byte from PCI configuration space 380 * @cgs_device: opaque device handle 381 * @addr: address 382 * 383 * Return: Value read 384 */ 385 typedef uint8_t (*cgs_read_pci_config_byte_t)(void *cgs_device, unsigned addr); 386 387 /** 388 * cgs_read_pci_config_word() - Read word from PCI configuration space 389 * @cgs_device: opaque device handle 390 * @addr: address, must be word-aligned 391 * 392 * Return: Value read 393 */ 394 typedef uint16_t (*cgs_read_pci_config_word_t)(void *cgs_device, unsigned addr); 395 396 /** 397 * cgs_read_pci_config_dword() - Read dword from PCI configuration space 398 * @cgs_device: opaque device handle 399 * @addr: address, must be dword-aligned 400 * 401 * Return: Value read 402 */ 403 typedef uint32_t (*cgs_read_pci_config_dword_t)(void *cgs_device, 404 unsigned addr); 405 406 /** 407 * cgs_write_pci_config_byte() - Write byte to PCI configuration space 408 * @cgs_device: opaque device handle 409 * @addr: address 410 * @value: value to write 411 */ 412 typedef void (*cgs_write_pci_config_byte_t)(void *cgs_device, unsigned addr, 413 uint8_t value); 414 415 /** 416 * cgs_write_pci_config_word() - Write byte to PCI configuration space 417 * @cgs_device: opaque device handle 418 * @addr: address, must be word-aligned 419 * @value: value to write 420 */ 421 typedef void (*cgs_write_pci_config_word_t)(void *cgs_device, unsigned addr, 422 uint16_t value); 423 424 /** 425 * cgs_write_pci_config_dword() - Write byte to PCI configuration space 426 * @cgs_device: opaque device handle 427 * @addr: address, must be dword-aligned 428 * @value: value to write 429 */ 430 typedef void (*cgs_write_pci_config_dword_t)(void *cgs_device, unsigned addr, 431 uint32_t value); 432 433 434 /** 435 * cgs_get_pci_resource() - provide access to a device resource (PCI BAR) 436 * @cgs_device: opaque device handle 437 * @resource_type: Type of Resource (MMIO, IO, ROM, FB, DOORBELL) 438 * @size: size of the region 439 * @offset: offset from the start of the region 440 * @resource_base: base address (not including offset) returned 441 * 442 * Return: 0 on success, -errno otherwise 443 */ 444 typedef int (*cgs_get_pci_resource_t)(void *cgs_device, 445 enum cgs_resource_type resource_type, 446 uint64_t size, 447 uint64_t offset, 448 uint64_t *resource_base); 449 450 /** 451 * cgs_atom_get_data_table() - Get a pointer to an ATOM BIOS data table 452 * @cgs_device: opaque device handle 453 * @table: data table index 454 * @size: size of the table (output, may be NULL) 455 * @frev: table format revision (output, may be NULL) 456 * @crev: table content revision (output, may be NULL) 457 * 458 * Return: Pointer to start of the table, or NULL on failure 459 */ 460 typedef const void *(*cgs_atom_get_data_table_t)( 461 void *cgs_device, unsigned table, 462 uint16_t *size, uint8_t *frev, uint8_t *crev); 463 464 /** 465 * cgs_atom_get_cmd_table_revs() - Get ATOM BIOS command table revisions 466 * @cgs_device: opaque device handle 467 * @table: data table index 468 * @frev: table format revision (output, may be NULL) 469 * @crev: table content revision (output, may be NULL) 470 * 471 * Return: 0 on success, -errno otherwise 472 */ 473 typedef int (*cgs_atom_get_cmd_table_revs_t)(void *cgs_device, unsigned table, 474 uint8_t *frev, uint8_t *crev); 475 476 /** 477 * cgs_atom_exec_cmd_table() - Execute an ATOM BIOS command table 478 * @cgs_device: opaque device handle 479 * @table: command table index 480 * @args: arguments 481 * 482 * Return: 0 on success, -errno otherwise 483 */ 484 typedef int (*cgs_atom_exec_cmd_table_t)(void *cgs_device, 485 unsigned table, void *args); 486 487 /** 488 * cgs_create_pm_request() - Create a power management request 489 * @cgs_device: opaque device handle 490 * @request: handle of created PM request (output) 491 * 492 * Return: 0 on success, -errno otherwise 493 */ 494 typedef int (*cgs_create_pm_request_t)(void *cgs_device, cgs_handle_t *request); 495 496 /** 497 * cgs_destroy_pm_request() - Destroy a power management request 498 * @cgs_device: opaque device handle 499 * @request: handle of created PM request 500 * 501 * Return: 0 on success, -errno otherwise 502 */ 503 typedef int (*cgs_destroy_pm_request_t)(void *cgs_device, cgs_handle_t request); 504 505 /** 506 * cgs_set_pm_request() - Activate or deactiveate a PM request 507 * @cgs_device: opaque device handle 508 * @request: PM request handle 509 * @active: 0 = deactivate, non-0 = activate 510 * 511 * While a PM request is active, its minimum clock requests are taken 512 * into account as the requested engines are powered up. When the 513 * request is inactive, the engines may be powered down and clocks may 514 * be lower, depending on other PM requests by other driver 515 * components. 516 * 517 * Return: 0 on success, -errno otherwise 518 */ 519 typedef int (*cgs_set_pm_request_t)(void *cgs_device, cgs_handle_t request, 520 int active); 521 522 /** 523 * cgs_pm_request_clock() - Request a minimum frequency for a specific clock 524 * @cgs_device: opaque device handle 525 * @request: PM request handle 526 * @clock: which clock? 527 * @freq: requested min. frequency in 10KHz units (0 to clear request) 528 * 529 * Return: 0 on success, -errno otherwise 530 */ 531 typedef int (*cgs_pm_request_clock_t)(void *cgs_device, cgs_handle_t request, 532 enum cgs_clock clock, unsigned freq); 533 534 /** 535 * cgs_pm_request_engine() - Request an engine to be powered up 536 * @cgs_device: opaque device handle 537 * @request: PM request handle 538 * @engine: which engine? 539 * @powered: 0 = powered down, non-0 = powered up 540 * 541 * Return: 0 on success, -errno otherwise 542 */ 543 typedef int (*cgs_pm_request_engine_t)(void *cgs_device, cgs_handle_t request, 544 enum cgs_engine engine, int powered); 545 546 /** 547 * cgs_pm_query_clock_limits() - Query clock frequency limits 548 * @cgs_device: opaque device handle 549 * @clock: which clock? 550 * @limits: clock limits 551 * 552 * Return: 0 on success, -errno otherwise 553 */ 554 typedef int (*cgs_pm_query_clock_limits_t)(void *cgs_device, 555 enum cgs_clock clock, 556 struct cgs_clock_limits *limits); 557 558 /** 559 * cgs_set_camera_voltages() - Apply specific voltages to PMIC voltage planes 560 * @cgs_device: opaque device handle 561 * @mask: bitmask of voltages to change (1<<CGS_VOLTAGE_PLANE__xyz|...) 562 * @voltages: pointer to array of voltage values in 1mV units 563 * 564 * Return: 0 on success, -errno otherwise 565 */ 566 typedef int (*cgs_set_camera_voltages_t)(void *cgs_device, uint32_t mask, 567 const uint32_t *voltages); 568 /** 569 * cgs_get_firmware_info - Get the firmware information from core driver 570 * @cgs_device: opaque device handle 571 * @type: the firmware type 572 * @info: returend firmware information 573 * 574 * Return: 0 on success, -errno otherwise 575 */ 576 typedef int (*cgs_get_firmware_info)(void *cgs_device, 577 enum cgs_ucode_id type, 578 struct cgs_firmware_info *info); 579 580 typedef int(*cgs_set_powergating_state)(void *cgs_device, 581 enum amd_ip_block_type block_type, 582 enum amd_powergating_state state); 583 584 typedef int(*cgs_set_clockgating_state)(void *cgs_device, 585 enum amd_ip_block_type block_type, 586 enum amd_clockgating_state state); 587 588 typedef int(*cgs_get_active_displays_info)( 589 void *cgs_device, 590 struct cgs_display_info *info); 591 592 typedef int (*cgs_notify_dpm_enabled)(void *cgs_device, bool enabled); 593 594 typedef int (*cgs_call_acpi_method)(void *cgs_device, 595 uint32_t acpi_method, 596 uint32_t acpi_function, 597 void *pinput, void *poutput, 598 uint32_t output_count, 599 uint32_t input_size, 600 uint32_t output_size); 601 602 typedef int (*cgs_query_system_info)(void *cgs_device, 603 struct cgs_system_info *sys_info); 604 605 struct cgs_ops { 606 /* memory management calls (similar to KFD interface) */ 607 cgs_gpu_mem_info_t gpu_mem_info; 608 cgs_gmap_kmem_t gmap_kmem; 609 cgs_gunmap_kmem_t gunmap_kmem; 610 cgs_alloc_gpu_mem_t alloc_gpu_mem; 611 cgs_free_gpu_mem_t free_gpu_mem; 612 cgs_gmap_gpu_mem_t gmap_gpu_mem; 613 cgs_gunmap_gpu_mem_t gunmap_gpu_mem; 614 cgs_kmap_gpu_mem_t kmap_gpu_mem; 615 cgs_kunmap_gpu_mem_t kunmap_gpu_mem; 616 /* MMIO access */ 617 cgs_read_register_t read_register; 618 cgs_write_register_t write_register; 619 cgs_read_ind_register_t read_ind_register; 620 cgs_write_ind_register_t write_ind_register; 621 /* PCI configuration space access */ 622 cgs_read_pci_config_byte_t read_pci_config_byte; 623 cgs_read_pci_config_word_t read_pci_config_word; 624 cgs_read_pci_config_dword_t read_pci_config_dword; 625 cgs_write_pci_config_byte_t write_pci_config_byte; 626 cgs_write_pci_config_word_t write_pci_config_word; 627 cgs_write_pci_config_dword_t write_pci_config_dword; 628 /* PCI resources */ 629 cgs_get_pci_resource_t get_pci_resource; 630 /* ATOM BIOS */ 631 cgs_atom_get_data_table_t atom_get_data_table; 632 cgs_atom_get_cmd_table_revs_t atom_get_cmd_table_revs; 633 cgs_atom_exec_cmd_table_t atom_exec_cmd_table; 634 /* Power management */ 635 cgs_create_pm_request_t create_pm_request; 636 cgs_destroy_pm_request_t destroy_pm_request; 637 cgs_set_pm_request_t set_pm_request; 638 cgs_pm_request_clock_t pm_request_clock; 639 cgs_pm_request_engine_t pm_request_engine; 640 cgs_pm_query_clock_limits_t pm_query_clock_limits; 641 cgs_set_camera_voltages_t set_camera_voltages; 642 /* Firmware Info */ 643 cgs_get_firmware_info get_firmware_info; 644 /* cg pg interface*/ 645 cgs_set_powergating_state set_powergating_state; 646 cgs_set_clockgating_state set_clockgating_state; 647 /* display manager */ 648 cgs_get_active_displays_info get_active_displays_info; 649 /* notify dpm enabled */ 650 cgs_notify_dpm_enabled notify_dpm_enabled; 651 /* ACPI */ 652 cgs_call_acpi_method call_acpi_method; 653 /* get system info */ 654 cgs_query_system_info query_system_info; 655 }; 656 657 struct cgs_os_ops; /* To be define in OS-specific CGS header */ 658 659 struct cgs_device 660 { 661 const struct cgs_ops *ops; 662 const struct cgs_os_ops *os_ops; 663 /* to be embedded at the start of driver private structure */ 664 }; 665 666 /* Convenience macros that make CGS indirect function calls look like 667 * normal function calls */ 668 #define CGS_CALL(func,dev,...) \ 669 (((struct cgs_device *)dev)->ops->func(dev, ##__VA_ARGS__)) 670 #define CGS_OS_CALL(func,dev,...) \ 671 (((struct cgs_device *)dev)->os_ops->func(dev, ##__VA_ARGS__)) 672 673 #define cgs_gpu_mem_info(dev,type,mc_start,mc_size,mem_size) \ 674 CGS_CALL(gpu_mem_info,dev,type,mc_start,mc_size,mem_size) 675 #define cgs_gmap_kmem(dev,kmem,size,min_off,max_off,kmem_handle,mcaddr) \ 676 CGS_CALL(gmap_kmem,dev,kmem,size,min_off,max_off,kmem_handle,mcaddr) 677 #define cgs_gunmap_kmem(dev,kmem_handle) \ 678 CGS_CALL(gunmap_kmem,dev,keme_handle) 679 #define cgs_alloc_gpu_mem(dev,type,size,align,min_off,max_off,handle) \ 680 CGS_CALL(alloc_gpu_mem,dev,type,size,align,min_off,max_off,handle) 681 #define cgs_free_gpu_mem(dev,handle) \ 682 CGS_CALL(free_gpu_mem,dev,handle) 683 #define cgs_gmap_gpu_mem(dev,handle,mcaddr) \ 684 CGS_CALL(gmap_gpu_mem,dev,handle,mcaddr) 685 #define cgs_gunmap_gpu_mem(dev,handle) \ 686 CGS_CALL(gunmap_gpu_mem,dev,handle) 687 #define cgs_kmap_gpu_mem(dev,handle,map) \ 688 CGS_CALL(kmap_gpu_mem,dev,handle,map) 689 #define cgs_kunmap_gpu_mem(dev,handle) \ 690 CGS_CALL(kunmap_gpu_mem,dev,handle) 691 692 #define cgs_read_register(dev,offset) \ 693 CGS_CALL(read_register,dev,offset) 694 #define cgs_write_register(dev,offset,value) \ 695 CGS_CALL(write_register,dev,offset,value) 696 #define cgs_read_ind_register(dev,space,index) \ 697 CGS_CALL(read_ind_register,dev,space,index) 698 #define cgs_write_ind_register(dev,space,index,value) \ 699 CGS_CALL(write_ind_register,dev,space,index,value) 700 701 #define cgs_read_pci_config_byte(dev,addr) \ 702 CGS_CALL(read_pci_config_byte,dev,addr) 703 #define cgs_read_pci_config_word(dev,addr) \ 704 CGS_CALL(read_pci_config_word,dev,addr) 705 #define cgs_read_pci_config_dword(dev,addr) \ 706 CGS_CALL(read_pci_config_dword,dev,addr) 707 #define cgs_write_pci_config_byte(dev,addr,value) \ 708 CGS_CALL(write_pci_config_byte,dev,addr,value) 709 #define cgs_write_pci_config_word(dev,addr,value) \ 710 CGS_CALL(write_pci_config_word,dev,addr,value) 711 #define cgs_write_pci_config_dword(dev,addr,value) \ 712 CGS_CALL(write_pci_config_dword,dev,addr,value) 713 714 #define cgs_atom_get_data_table(dev,table,size,frev,crev) \ 715 CGS_CALL(atom_get_data_table,dev,table,size,frev,crev) 716 #define cgs_atom_get_cmd_table_revs(dev,table,frev,crev) \ 717 CGS_CALL(atom_get_cmd_table_revs,dev,table,frev,crev) 718 #define cgs_atom_exec_cmd_table(dev,table,args) \ 719 CGS_CALL(atom_exec_cmd_table,dev,table,args) 720 721 #define cgs_create_pm_request(dev,request) \ 722 CGS_CALL(create_pm_request,dev,request) 723 #define cgs_destroy_pm_request(dev,request) \ 724 CGS_CALL(destroy_pm_request,dev,request) 725 #define cgs_set_pm_request(dev,request,active) \ 726 CGS_CALL(set_pm_request,dev,request,active) 727 #define cgs_pm_request_clock(dev,request,clock,freq) \ 728 CGS_CALL(pm_request_clock,dev,request,clock,freq) 729 #define cgs_pm_request_engine(dev,request,engine,powered) \ 730 CGS_CALL(pm_request_engine,dev,request,engine,powered) 731 #define cgs_pm_query_clock_limits(dev,clock,limits) \ 732 CGS_CALL(pm_query_clock_limits,dev,clock,limits) 733 #define cgs_set_camera_voltages(dev,mask,voltages) \ 734 CGS_CALL(set_camera_voltages,dev,mask,voltages) 735 #define cgs_get_firmware_info(dev, type, info) \ 736 CGS_CALL(get_firmware_info, dev, type, info) 737 #define cgs_set_powergating_state(dev, block_type, state) \ 738 CGS_CALL(set_powergating_state, dev, block_type, state) 739 #define cgs_set_clockgating_state(dev, block_type, state) \ 740 CGS_CALL(set_clockgating_state, dev, block_type, state) 741 #define cgs_notify_dpm_enabled(dev, enabled) \ 742 CGS_CALL(notify_dpm_enabled, dev, enabled) 743 744 #define cgs_get_active_displays_info(dev, info) \ 745 CGS_CALL(get_active_displays_info, dev, info) 746 747 #define cgs_call_acpi_method(dev, acpi_method, acpi_function, pintput, poutput, output_count, input_size, output_size) \ 748 CGS_CALL(call_acpi_method, dev, acpi_method, acpi_function, pintput, poutput, output_count, input_size, output_size) 749 #define cgs_query_system_info(dev, sys_info) \ 750 CGS_CALL(query_system_info, dev, sys_info) 751 #define cgs_get_pci_resource(cgs_device, resource_type, size, offset, \ 752 resource_base) \ 753 CGS_CALL(get_pci_resource, cgs_device, resource_type, size, offset, \ 754 resource_base) 755 756 #endif /* _CGS_COMMON_H */ 757