1 /****************************************************************************\ 2 * 3 * File Name atomfirmware.h 4 * Project This is an interface header file between atombios and OS GPU drivers for SoC15 products 5 * 6 * Description header file of general definitions for OS and pre-OS video drivers 7 * 8 * Copyright 2014 Advanced Micro Devices, Inc. 9 * 10 * Permission is hereby granted, free of charge, to any person obtaining a copy of this software 11 * and associated documentation files (the "Software"), to deal in the Software without restriction, 12 * including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, 13 * and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, 14 * subject to the following conditions: 15 * 16 * The above copyright notice and this permission notice shall be included in all copies or substantial 17 * portions of the Software. 18 * 19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 22 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 23 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 24 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 25 * OTHER DEALINGS IN THE SOFTWARE. 26 * 27 \****************************************************************************/ 28 29 /*IMPORTANT NOTES 30 * If a change in VBIOS/Driver/Tool's interface is only needed for SoC15 and forward products, then the change is only needed in this atomfirmware.h header file. 31 * If a change in VBIOS/Driver/Tool's interface is only needed for pre-SoC15 products, then the change is only needed in atombios.h header file. 32 * If a change is needed for both pre and post SoC15 products, then the change has to be made separately and might be differently in both atomfirmware.h and atombios.h. 33 */ 34 35 #ifndef _ATOMFIRMWARE_H_ 36 #define _ATOMFIRMWARE_H_ 37 38 enum atom_bios_header_version_def{ 39 ATOM_MAJOR_VERSION =0x0003, 40 ATOM_MINOR_VERSION =0x0003, 41 }; 42 43 #ifdef _H2INC 44 #ifndef uint32_t 45 typedef unsigned long uint32_t; 46 #endif 47 48 #ifndef uint16_t 49 typedef unsigned short uint16_t; 50 #endif 51 52 #ifndef uint8_t 53 typedef unsigned char uint8_t; 54 #endif 55 #endif 56 57 enum atom_crtc_def{ 58 ATOM_CRTC1 =0, 59 ATOM_CRTC2 =1, 60 ATOM_CRTC3 =2, 61 ATOM_CRTC4 =3, 62 ATOM_CRTC5 =4, 63 ATOM_CRTC6 =5, 64 ATOM_CRTC_INVALID =0xff, 65 }; 66 67 enum atom_ppll_def{ 68 ATOM_PPLL0 =2, 69 ATOM_GCK_DFS =8, 70 ATOM_FCH_CLK =9, 71 ATOM_DP_DTO =11, 72 ATOM_COMBOPHY_PLL0 =20, 73 ATOM_COMBOPHY_PLL1 =21, 74 ATOM_COMBOPHY_PLL2 =22, 75 ATOM_COMBOPHY_PLL3 =23, 76 ATOM_COMBOPHY_PLL4 =24, 77 ATOM_COMBOPHY_PLL5 =25, 78 ATOM_PPLL_INVALID =0xff, 79 }; 80 81 // define ASIC internal encoder id ( bit vector ), used for CRTC_SourceSel 82 enum atom_dig_def{ 83 ASIC_INT_DIG1_ENCODER_ID =0x03, 84 ASIC_INT_DIG2_ENCODER_ID =0x09, 85 ASIC_INT_DIG3_ENCODER_ID =0x0a, 86 ASIC_INT_DIG4_ENCODER_ID =0x0b, 87 ASIC_INT_DIG5_ENCODER_ID =0x0c, 88 ASIC_INT_DIG6_ENCODER_ID =0x0d, 89 ASIC_INT_DIG7_ENCODER_ID =0x0e, 90 }; 91 92 //ucEncoderMode 93 enum atom_encode_mode_def 94 { 95 ATOM_ENCODER_MODE_DP =0, 96 ATOM_ENCODER_MODE_DP_SST =0, 97 ATOM_ENCODER_MODE_LVDS =1, 98 ATOM_ENCODER_MODE_DVI =2, 99 ATOM_ENCODER_MODE_HDMI =3, 100 ATOM_ENCODER_MODE_DP_AUDIO =5, 101 ATOM_ENCODER_MODE_DP_MST =5, 102 ATOM_ENCODER_MODE_CRT =15, 103 ATOM_ENCODER_MODE_DVO =16, 104 }; 105 106 enum atom_encoder_refclk_src_def{ 107 ENCODER_REFCLK_SRC_P1PLL =0, 108 ENCODER_REFCLK_SRC_P2PLL =1, 109 ENCODER_REFCLK_SRC_P3PLL =2, 110 ENCODER_REFCLK_SRC_EXTCLK =3, 111 ENCODER_REFCLK_SRC_INVALID =0xff, 112 }; 113 114 enum atom_scaler_def{ 115 ATOM_SCALER_DISABLE =0, /*scaler bypass mode, auto-center & no replication*/ 116 ATOM_SCALER_CENTER =1, //For Fudo, it's bypass and auto-center & auto replication 117 ATOM_SCALER_EXPANSION =2, /*scaler expansion by 2 tap alpha blending mode*/ 118 }; 119 120 enum atom_operation_def{ 121 ATOM_DISABLE = 0, 122 ATOM_ENABLE = 1, 123 ATOM_INIT = 7, 124 ATOM_GET_STATUS = 8, 125 }; 126 127 enum atom_embedded_display_op_def{ 128 ATOM_LCD_BL_OFF = 2, 129 ATOM_LCD_BL_OM = 3, 130 ATOM_LCD_BL_BRIGHTNESS_CONTROL = 4, 131 ATOM_LCD_SELFTEST_START = 5, 132 ATOM_LCD_SELFTEST_STOP = 6, 133 }; 134 135 enum atom_spread_spectrum_mode{ 136 ATOM_SS_CENTER_OR_DOWN_MODE_MASK = 0x01, 137 ATOM_SS_DOWN_SPREAD_MODE = 0x00, 138 ATOM_SS_CENTRE_SPREAD_MODE = 0x01, 139 ATOM_INT_OR_EXT_SS_MASK = 0x02, 140 ATOM_INTERNAL_SS_MASK = 0x00, 141 ATOM_EXTERNAL_SS_MASK = 0x02, 142 }; 143 144 /* define panel bit per color */ 145 enum atom_panel_bit_per_color{ 146 PANEL_BPC_UNDEFINE =0x00, 147 PANEL_6BIT_PER_COLOR =0x01, 148 PANEL_8BIT_PER_COLOR =0x02, 149 PANEL_10BIT_PER_COLOR =0x03, 150 PANEL_12BIT_PER_COLOR =0x04, 151 PANEL_16BIT_PER_COLOR =0x05, 152 }; 153 154 //ucVoltageType 155 enum atom_voltage_type 156 { 157 VOLTAGE_TYPE_VDDC = 1, 158 VOLTAGE_TYPE_MVDDC = 2, 159 VOLTAGE_TYPE_MVDDQ = 3, 160 VOLTAGE_TYPE_VDDCI = 4, 161 VOLTAGE_TYPE_VDDGFX = 5, 162 VOLTAGE_TYPE_PCC = 6, 163 VOLTAGE_TYPE_MVPP = 7, 164 VOLTAGE_TYPE_LEDDPM = 8, 165 VOLTAGE_TYPE_PCC_MVDD = 9, 166 VOLTAGE_TYPE_PCIE_VDDC = 10, 167 VOLTAGE_TYPE_PCIE_VDDR = 11, 168 VOLTAGE_TYPE_GENERIC_I2C_1 = 0x11, 169 VOLTAGE_TYPE_GENERIC_I2C_2 = 0x12, 170 VOLTAGE_TYPE_GENERIC_I2C_3 = 0x13, 171 VOLTAGE_TYPE_GENERIC_I2C_4 = 0x14, 172 VOLTAGE_TYPE_GENERIC_I2C_5 = 0x15, 173 VOLTAGE_TYPE_GENERIC_I2C_6 = 0x16, 174 VOLTAGE_TYPE_GENERIC_I2C_7 = 0x17, 175 VOLTAGE_TYPE_GENERIC_I2C_8 = 0x18, 176 VOLTAGE_TYPE_GENERIC_I2C_9 = 0x19, 177 VOLTAGE_TYPE_GENERIC_I2C_10 = 0x1A, 178 }; 179 180 enum atom_dgpu_vram_type { 181 ATOM_DGPU_VRAM_TYPE_GDDR5 = 0x50, 182 ATOM_DGPU_VRAM_TYPE_HBM2 = 0x60, 183 ATOM_DGPU_VRAM_TYPE_HBM2E = 0x61, 184 ATOM_DGPU_VRAM_TYPE_GDDR6 = 0x70, 185 }; 186 187 enum atom_dp_vs_preemph_def{ 188 DP_VS_LEVEL0_PREEMPH_LEVEL0 = 0x00, 189 DP_VS_LEVEL1_PREEMPH_LEVEL0 = 0x01, 190 DP_VS_LEVEL2_PREEMPH_LEVEL0 = 0x02, 191 DP_VS_LEVEL3_PREEMPH_LEVEL0 = 0x03, 192 DP_VS_LEVEL0_PREEMPH_LEVEL1 = 0x08, 193 DP_VS_LEVEL1_PREEMPH_LEVEL1 = 0x09, 194 DP_VS_LEVEL2_PREEMPH_LEVEL1 = 0x0a, 195 DP_VS_LEVEL0_PREEMPH_LEVEL2 = 0x10, 196 DP_VS_LEVEL1_PREEMPH_LEVEL2 = 0x11, 197 DP_VS_LEVEL0_PREEMPH_LEVEL3 = 0x18, 198 }; 199 200 #define BIOS_ATOM_PREFIX "ATOMBIOS" 201 #define BIOS_VERSION_PREFIX "ATOMBIOSBK-AMD" 202 #define BIOS_STRING_LENGTH 43 203 204 /* 205 enum atom_string_def{ 206 asic_bus_type_pcie_string = "PCI_EXPRESS", 207 atom_fire_gl_string = "FGL", 208 atom_bios_string = "ATOM" 209 }; 210 */ 211 212 #pragma pack(1) /* BIOS data must use byte aligment*/ 213 214 enum atombios_image_offset{ 215 OFFSET_TO_ATOM_ROM_HEADER_POINTER = 0x00000048, 216 OFFSET_TO_ATOM_ROM_IMAGE_SIZE = 0x00000002, 217 OFFSET_TO_ATOMBIOS_ASIC_BUS_MEM_TYPE = 0x94, 218 MAXSIZE_OF_ATOMBIOS_ASIC_BUS_MEM_TYPE = 20, /*including the terminator 0x0!*/ 219 OFFSET_TO_GET_ATOMBIOS_NUMBER_OF_STRINGS = 0x2f, 220 OFFSET_TO_GET_ATOMBIOS_STRING_START = 0x6e, 221 OFFSET_TO_VBIOS_PART_NUMBER = 0x80, 222 OFFSET_TO_VBIOS_DATE = 0x50, 223 }; 224 225 /**************************************************************************** 226 * Common header for all tables (Data table, Command function). 227 * Every table pointed in _ATOM_MASTER_DATA_TABLE has this common header. 228 * And the pointer actually points to this header. 229 ****************************************************************************/ 230 231 struct atom_common_table_header 232 { 233 uint16_t structuresize; 234 uint8_t format_revision; //mainly used for a hw function, when the parser is not backward compatible 235 uint8_t content_revision; //change it when a data table has a structure change, or a hw function has a input/output parameter change 236 }; 237 238 /**************************************************************************** 239 * Structure stores the ROM header. 240 ****************************************************************************/ 241 struct atom_rom_header_v2_2 242 { 243 struct atom_common_table_header table_header; 244 uint8_t atom_bios_string[4]; //enum atom_string_def atom_bios_string; //Signature to distinguish between Atombios and non-atombios, 245 uint16_t bios_segment_address; 246 uint16_t protectedmodeoffset; 247 uint16_t configfilenameoffset; 248 uint16_t crc_block_offset; 249 uint16_t vbios_bootupmessageoffset; 250 uint16_t int10_offset; 251 uint16_t pcibusdevinitcode; 252 uint16_t iobaseaddress; 253 uint16_t subsystem_vendor_id; 254 uint16_t subsystem_id; 255 uint16_t pci_info_offset; 256 uint16_t masterhwfunction_offset; //Offest for SW to get all command function offsets, Don't change the position 257 uint16_t masterdatatable_offset; //Offest for SW to get all data table offsets, Don't change the position 258 uint16_t reserved; 259 uint32_t pspdirtableoffset; 260 }; 261 262 /*==============================hw function portion======================================================================*/ 263 264 265 /**************************************************************************** 266 * Structures used in Command.mtb, each function name is not given here since those function could change from time to time 267 * The real functionality of each function is associated with the parameter structure version when defined 268 * For all internal cmd function definitions, please reference to atomstruct.h 269 ****************************************************************************/ 270 struct atom_master_list_of_command_functions_v2_1{ 271 uint16_t asic_init; //Function 272 uint16_t cmd_function1; //used as an internal one 273 uint16_t cmd_function2; //used as an internal one 274 uint16_t cmd_function3; //used as an internal one 275 uint16_t digxencodercontrol; //Function 276 uint16_t cmd_function5; //used as an internal one 277 uint16_t cmd_function6; //used as an internal one 278 uint16_t cmd_function7; //used as an internal one 279 uint16_t cmd_function8; //used as an internal one 280 uint16_t cmd_function9; //used as an internal one 281 uint16_t setengineclock; //Function 282 uint16_t setmemoryclock; //Function 283 uint16_t setpixelclock; //Function 284 uint16_t enabledisppowergating; //Function 285 uint16_t cmd_function14; //used as an internal one 286 uint16_t cmd_function15; //used as an internal one 287 uint16_t cmd_function16; //used as an internal one 288 uint16_t cmd_function17; //used as an internal one 289 uint16_t cmd_function18; //used as an internal one 290 uint16_t cmd_function19; //used as an internal one 291 uint16_t cmd_function20; //used as an internal one 292 uint16_t cmd_function21; //used as an internal one 293 uint16_t cmd_function22; //used as an internal one 294 uint16_t cmd_function23; //used as an internal one 295 uint16_t cmd_function24; //used as an internal one 296 uint16_t cmd_function25; //used as an internal one 297 uint16_t cmd_function26; //used as an internal one 298 uint16_t cmd_function27; //used as an internal one 299 uint16_t cmd_function28; //used as an internal one 300 uint16_t cmd_function29; //used as an internal one 301 uint16_t cmd_function30; //used as an internal one 302 uint16_t cmd_function31; //used as an internal one 303 uint16_t cmd_function32; //used as an internal one 304 uint16_t cmd_function33; //used as an internal one 305 uint16_t blankcrtc; //Function 306 uint16_t enablecrtc; //Function 307 uint16_t cmd_function36; //used as an internal one 308 uint16_t cmd_function37; //used as an internal one 309 uint16_t cmd_function38; //used as an internal one 310 uint16_t cmd_function39; //used as an internal one 311 uint16_t cmd_function40; //used as an internal one 312 uint16_t getsmuclockinfo; //Function 313 uint16_t selectcrtc_source; //Function 314 uint16_t cmd_function43; //used as an internal one 315 uint16_t cmd_function44; //used as an internal one 316 uint16_t cmd_function45; //used as an internal one 317 uint16_t setdceclock; //Function 318 uint16_t getmemoryclock; //Function 319 uint16_t getengineclock; //Function 320 uint16_t setcrtc_usingdtdtiming; //Function 321 uint16_t externalencodercontrol; //Function 322 uint16_t cmd_function51; //used as an internal one 323 uint16_t cmd_function52; //used as an internal one 324 uint16_t cmd_function53; //used as an internal one 325 uint16_t processi2cchanneltransaction;//Function 326 uint16_t cmd_function55; //used as an internal one 327 uint16_t cmd_function56; //used as an internal one 328 uint16_t cmd_function57; //used as an internal one 329 uint16_t cmd_function58; //used as an internal one 330 uint16_t cmd_function59; //used as an internal one 331 uint16_t computegpuclockparam; //Function 332 uint16_t cmd_function61; //used as an internal one 333 uint16_t cmd_function62; //used as an internal one 334 uint16_t dynamicmemorysettings; //Function function 335 uint16_t memorytraining; //Function function 336 uint16_t cmd_function65; //used as an internal one 337 uint16_t cmd_function66; //used as an internal one 338 uint16_t setvoltage; //Function 339 uint16_t cmd_function68; //used as an internal one 340 uint16_t readefusevalue; //Function 341 uint16_t cmd_function70; //used as an internal one 342 uint16_t cmd_function71; //used as an internal one 343 uint16_t cmd_function72; //used as an internal one 344 uint16_t cmd_function73; //used as an internal one 345 uint16_t cmd_function74; //used as an internal one 346 uint16_t cmd_function75; //used as an internal one 347 uint16_t dig1transmittercontrol; //Function 348 uint16_t cmd_function77; //used as an internal one 349 uint16_t processauxchanneltransaction;//Function 350 uint16_t cmd_function79; //used as an internal one 351 uint16_t getvoltageinfo; //Function 352 }; 353 354 struct atom_master_command_function_v2_1 355 { 356 struct atom_common_table_header table_header; 357 struct atom_master_list_of_command_functions_v2_1 listofcmdfunctions; 358 }; 359 360 /**************************************************************************** 361 * Structures used in every command function 362 ****************************************************************************/ 363 struct atom_function_attribute 364 { 365 uint16_t ws_in_bytes:8; //[7:0]=Size of workspace in Bytes (in multiple of a dword), 366 uint16_t ps_in_bytes:7; //[14:8]=Size of parameter space in Bytes (multiple of a dword), 367 uint16_t updated_by_util:1; //[15]=flag to indicate the function is updated by util 368 }; 369 370 371 /**************************************************************************** 372 * Common header for all hw functions. 373 * Every function pointed by _master_list_of_hw_function has this common header. 374 * And the pointer actually points to this header. 375 ****************************************************************************/ 376 struct atom_rom_hw_function_header 377 { 378 struct atom_common_table_header func_header; 379 struct atom_function_attribute func_attrib; 380 }; 381 382 383 /*==============================sw data table portion======================================================================*/ 384 /**************************************************************************** 385 * Structures used in data.mtb, each data table name is not given here since those data table could change from time to time 386 * The real name of each table is given when its data structure version is defined 387 ****************************************************************************/ 388 struct atom_master_list_of_data_tables_v2_1{ 389 uint16_t utilitypipeline; /* Offest for the utility to get parser info,Don't change this position!*/ 390 uint16_t multimedia_info; 391 uint16_t smc_dpm_info; 392 uint16_t sw_datatable3; 393 uint16_t firmwareinfo; /* Shared by various SW components */ 394 uint16_t sw_datatable5; 395 uint16_t lcd_info; /* Shared by various SW components */ 396 uint16_t sw_datatable7; 397 uint16_t smu_info; 398 uint16_t sw_datatable9; 399 uint16_t sw_datatable10; 400 uint16_t vram_usagebyfirmware; /* Shared by various SW components */ 401 uint16_t gpio_pin_lut; /* Shared by various SW components */ 402 uint16_t sw_datatable13; 403 uint16_t gfx_info; 404 uint16_t powerplayinfo; /* Shared by various SW components */ 405 uint16_t sw_datatable16; 406 uint16_t sw_datatable17; 407 uint16_t sw_datatable18; 408 uint16_t sw_datatable19; 409 uint16_t sw_datatable20; 410 uint16_t sw_datatable21; 411 uint16_t displayobjectinfo; /* Shared by various SW components */ 412 uint16_t indirectioaccess; /* used as an internal one */ 413 uint16_t umc_info; /* Shared by various SW components */ 414 uint16_t sw_datatable25; 415 uint16_t sw_datatable26; 416 uint16_t dce_info; /* Shared by various SW components */ 417 uint16_t vram_info; /* Shared by various SW components */ 418 uint16_t sw_datatable29; 419 uint16_t integratedsysteminfo; /* Shared by various SW components */ 420 uint16_t asic_profiling_info; /* Shared by various SW components */ 421 uint16_t voltageobject_info; /* shared by various SW components */ 422 uint16_t sw_datatable33; 423 uint16_t sw_datatable34; 424 }; 425 426 427 struct atom_master_data_table_v2_1 428 { 429 struct atom_common_table_header table_header; 430 struct atom_master_list_of_data_tables_v2_1 listOfdatatables; 431 }; 432 433 434 struct atom_dtd_format 435 { 436 uint16_t pixclk; 437 uint16_t h_active; 438 uint16_t h_blanking_time; 439 uint16_t v_active; 440 uint16_t v_blanking_time; 441 uint16_t h_sync_offset; 442 uint16_t h_sync_width; 443 uint16_t v_sync_offset; 444 uint16_t v_syncwidth; 445 uint16_t reserved; 446 uint16_t reserved0; 447 uint8_t h_border; 448 uint8_t v_border; 449 uint16_t miscinfo; 450 uint8_t atom_mode_id; 451 uint8_t refreshrate; 452 }; 453 454 /* atom_dtd_format.modemiscinfo defintion */ 455 enum atom_dtd_format_modemiscinfo{ 456 ATOM_HSYNC_POLARITY = 0x0002, 457 ATOM_VSYNC_POLARITY = 0x0004, 458 ATOM_H_REPLICATIONBY2 = 0x0010, 459 ATOM_V_REPLICATIONBY2 = 0x0020, 460 ATOM_INTERLACE = 0x0080, 461 ATOM_COMPOSITESYNC = 0x0040, 462 }; 463 464 465 /* utilitypipeline 466 * when format_revision==1 && content_revision==1, then this an info table for atomworks to use during debug session, no structure is associated with it. 467 * the location of it can't change 468 */ 469 470 471 /* 472 *************************************************************************** 473 Data Table firmwareinfo structure 474 *************************************************************************** 475 */ 476 477 struct atom_firmware_info_v3_1 478 { 479 struct atom_common_table_header table_header; 480 uint32_t firmware_revision; 481 uint32_t bootup_sclk_in10khz; 482 uint32_t bootup_mclk_in10khz; 483 uint32_t firmware_capability; // enum atombios_firmware_capability 484 uint32_t main_call_parser_entry; /* direct address of main parser call in VBIOS binary. */ 485 uint32_t bios_scratch_reg_startaddr; // 1st bios scratch register dword address 486 uint16_t bootup_vddc_mv; 487 uint16_t bootup_vddci_mv; 488 uint16_t bootup_mvddc_mv; 489 uint16_t bootup_vddgfx_mv; 490 uint8_t mem_module_id; 491 uint8_t coolingsolution_id; /*0: Air cooling; 1: Liquid cooling ... */ 492 uint8_t reserved1[2]; 493 uint32_t mc_baseaddr_high; 494 uint32_t mc_baseaddr_low; 495 uint32_t reserved2[6]; 496 }; 497 498 /* Total 32bit cap indication */ 499 enum atombios_firmware_capability 500 { 501 ATOM_FIRMWARE_CAP_FIRMWARE_POSTED = 0x00000001, 502 ATOM_FIRMWARE_CAP_GPU_VIRTUALIZATION = 0x00000002, 503 ATOM_FIRMWARE_CAP_WMI_SUPPORT = 0x00000040, 504 ATOM_FIRMWARE_CAP_HWEMU_ENABLE = 0x00000080, 505 ATOM_FIRMWARE_CAP_HWEMU_UMC_CFG = 0x00000100, 506 ATOM_FIRMWARE_CAP_SRAM_ECC = 0x00000200, 507 ATOM_FIRMWARE_CAP_ENABLE_2STAGE_BIST_TRAINING = 0x00000400, 508 ATOM_FIRMWARE_CAP_ENABLE_2ND_USB20PORT = 0x0008000, 509 ATOM_FIRMWARE_CAP_DYNAMIC_BOOT_CFG_ENABLE = 0x0020000, 510 }; 511 512 enum atom_cooling_solution_id{ 513 AIR_COOLING = 0x00, 514 LIQUID_COOLING = 0x01 515 }; 516 517 struct atom_firmware_info_v3_2 { 518 struct atom_common_table_header table_header; 519 uint32_t firmware_revision; 520 uint32_t bootup_sclk_in10khz; 521 uint32_t bootup_mclk_in10khz; 522 uint32_t firmware_capability; // enum atombios_firmware_capability 523 uint32_t main_call_parser_entry; /* direct address of main parser call in VBIOS binary. */ 524 uint32_t bios_scratch_reg_startaddr; // 1st bios scratch register dword address 525 uint16_t bootup_vddc_mv; 526 uint16_t bootup_vddci_mv; 527 uint16_t bootup_mvddc_mv; 528 uint16_t bootup_vddgfx_mv; 529 uint8_t mem_module_id; 530 uint8_t coolingsolution_id; /*0: Air cooling; 1: Liquid cooling ... */ 531 uint8_t reserved1[2]; 532 uint32_t mc_baseaddr_high; 533 uint32_t mc_baseaddr_low; 534 uint8_t board_i2c_feature_id; // enum of atom_board_i2c_feature_id_def 535 uint8_t board_i2c_feature_gpio_id; // i2c id find in gpio_lut data table gpio_id 536 uint8_t board_i2c_feature_slave_addr; 537 uint8_t reserved3; 538 uint16_t bootup_mvddq_mv; 539 uint16_t bootup_mvpp_mv; 540 uint32_t zfbstartaddrin16mb; 541 uint32_t reserved2[3]; 542 }; 543 544 struct atom_firmware_info_v3_3 545 { 546 struct atom_common_table_header table_header; 547 uint32_t firmware_revision; 548 uint32_t bootup_sclk_in10khz; 549 uint32_t bootup_mclk_in10khz; 550 uint32_t firmware_capability; // enum atombios_firmware_capability 551 uint32_t main_call_parser_entry; /* direct address of main parser call in VBIOS binary. */ 552 uint32_t bios_scratch_reg_startaddr; // 1st bios scratch register dword address 553 uint16_t bootup_vddc_mv; 554 uint16_t bootup_vddci_mv; 555 uint16_t bootup_mvddc_mv; 556 uint16_t bootup_vddgfx_mv; 557 uint8_t mem_module_id; 558 uint8_t coolingsolution_id; /*0: Air cooling; 1: Liquid cooling ... */ 559 uint8_t reserved1[2]; 560 uint32_t mc_baseaddr_high; 561 uint32_t mc_baseaddr_low; 562 uint8_t board_i2c_feature_id; // enum of atom_board_i2c_feature_id_def 563 uint8_t board_i2c_feature_gpio_id; // i2c id find in gpio_lut data table gpio_id 564 uint8_t board_i2c_feature_slave_addr; 565 uint8_t reserved3; 566 uint16_t bootup_mvddq_mv; 567 uint16_t bootup_mvpp_mv; 568 uint32_t zfbstartaddrin16mb; 569 uint32_t pplib_pptable_id; // if pplib_pptable_id!=0, pplib get powerplay table inside driver instead of from VBIOS 570 uint32_t reserved2[2]; 571 }; 572 573 struct atom_firmware_info_v3_4 { 574 struct atom_common_table_header table_header; 575 uint32_t firmware_revision; 576 uint32_t bootup_sclk_in10khz; 577 uint32_t bootup_mclk_in10khz; 578 uint32_t firmware_capability; // enum atombios_firmware_capability 579 uint32_t main_call_parser_entry; /* direct address of main parser call in VBIOS binary. */ 580 uint32_t bios_scratch_reg_startaddr; // 1st bios scratch register dword address 581 uint16_t bootup_vddc_mv; 582 uint16_t bootup_vddci_mv; 583 uint16_t bootup_mvddc_mv; 584 uint16_t bootup_vddgfx_mv; 585 uint8_t mem_module_id; 586 uint8_t coolingsolution_id; /*0: Air cooling; 1: Liquid cooling ... */ 587 uint8_t reserved1[2]; 588 uint32_t mc_baseaddr_high; 589 uint32_t mc_baseaddr_low; 590 uint8_t board_i2c_feature_id; // enum of atom_board_i2c_feature_id_def 591 uint8_t board_i2c_feature_gpio_id; // i2c id find in gpio_lut data table gpio_id 592 uint8_t board_i2c_feature_slave_addr; 593 uint8_t ras_rom_i2c_slave_addr; 594 uint16_t bootup_mvddq_mv; 595 uint16_t bootup_mvpp_mv; 596 uint32_t zfbstartaddrin16mb; 597 uint32_t pplib_pptable_id; // if pplib_pptable_id!=0, pplib get powerplay table inside driver instead of from VBIOS 598 uint32_t mvdd_ratio; // mvdd_raio = (real mvdd in power rail)*1000/(mvdd_output_from_svi2) 599 uint16_t hw_bootup_vddgfx_mv; // hw default vddgfx voltage level decide by board strap 600 uint16_t hw_bootup_vddc_mv; // hw default vddc voltage level decide by board strap 601 uint16_t hw_bootup_mvddc_mv; // hw default mvddc voltage level decide by board strap 602 uint16_t hw_bootup_vddci_mv; // hw default vddci voltage level decide by board strap 603 uint32_t maco_pwrlimit_mw; // bomaco mode power limit in unit of m-watt 604 uint32_t usb_pwrlimit_mw; // power limit when USB is enable in unit of m-watt 605 uint32_t fw_reserved_size_in_kb; // VBIOS reserved extra fw size in unit of kb. 606 uint32_t pspbl_init_done_reg_addr; 607 uint32_t pspbl_init_done_value; 608 uint32_t pspbl_init_done_check_timeout; // time out in unit of us when polling pspbl init done 609 uint32_t reserved[2]; 610 }; 611 612 /* 613 *************************************************************************** 614 Data Table lcd_info structure 615 *************************************************************************** 616 */ 617 618 struct lcd_info_v2_1 619 { 620 struct atom_common_table_header table_header; 621 struct atom_dtd_format lcd_timing; 622 uint16_t backlight_pwm; 623 uint16_t special_handle_cap; 624 uint16_t panel_misc; 625 uint16_t lvds_max_slink_pclk; 626 uint16_t lvds_ss_percentage; 627 uint16_t lvds_ss_rate_10hz; 628 uint8_t pwr_on_digon_to_de; /*all pwr sequence numbers below are in uint of 4ms*/ 629 uint8_t pwr_on_de_to_vary_bl; 630 uint8_t pwr_down_vary_bloff_to_de; 631 uint8_t pwr_down_de_to_digoff; 632 uint8_t pwr_off_delay; 633 uint8_t pwr_on_vary_bl_to_blon; 634 uint8_t pwr_down_bloff_to_vary_bloff; 635 uint8_t panel_bpc; 636 uint8_t dpcd_edp_config_cap; 637 uint8_t dpcd_max_link_rate; 638 uint8_t dpcd_max_lane_count; 639 uint8_t dpcd_max_downspread; 640 uint8_t min_allowed_bl_level; 641 uint8_t max_allowed_bl_level; 642 uint8_t bootup_bl_level; 643 uint8_t dplvdsrxid; 644 uint32_t reserved1[8]; 645 }; 646 647 /* lcd_info_v2_1.panel_misc defintion */ 648 enum atom_lcd_info_panel_misc{ 649 ATOM_PANEL_MISC_FPDI =0x0002, 650 }; 651 652 //uceDPToLVDSRxId 653 enum atom_lcd_info_dptolvds_rx_id 654 { 655 eDP_TO_LVDS_RX_DISABLE = 0x00, // no eDP->LVDS translator chip 656 eDP_TO_LVDS_COMMON_ID = 0x01, // common eDP->LVDS translator chip without AMD SW init 657 eDP_TO_LVDS_REALTEK_ID = 0x02, // Realtek tansaltor which require AMD SW init 658 }; 659 660 661 /* 662 *************************************************************************** 663 Data Table gpio_pin_lut structure 664 *************************************************************************** 665 */ 666 667 struct atom_gpio_pin_assignment 668 { 669 uint32_t data_a_reg_index; 670 uint8_t gpio_bitshift; 671 uint8_t gpio_mask_bitshift; 672 uint8_t gpio_id; 673 uint8_t reserved; 674 }; 675 676 /* atom_gpio_pin_assignment.gpio_id definition */ 677 enum atom_gpio_pin_assignment_gpio_id { 678 I2C_HW_LANE_MUX =0x0f, /* only valid when bit7=1 */ 679 I2C_HW_ENGINE_ID_MASK =0x70, /* only valid when bit7=1 */ 680 I2C_HW_CAP =0x80, /*only when the I2C_HW_CAP is set, the pin ID is assigned to an I2C pin pair, otherwise, it's an generic GPIO pin */ 681 682 /* gpio_id pre-define id for multiple usage */ 683 /* GPIO use to control PCIE_VDDC in certain SLT board */ 684 PCIE_VDDC_CONTROL_GPIO_PINID = 56, 685 /* if PP_AC_DC_SWITCH_GPIO_PINID in Gpio_Pin_LutTable, AC/DC swithing feature is enable */ 686 PP_AC_DC_SWITCH_GPIO_PINID = 60, 687 /* VDDC_REGULATOR_VRHOT_GPIO_PINID in Gpio_Pin_LutTable, VRHot feature is enable */ 688 VDDC_VRHOT_GPIO_PINID = 61, 689 /*if VDDC_PCC_GPIO_PINID in GPIO_LUTable, Peak Current Control feature is enabled */ 690 VDDC_PCC_GPIO_PINID = 62, 691 /* Only used on certain SLT/PA board to allow utility to cut Efuse. */ 692 EFUSE_CUT_ENABLE_GPIO_PINID = 63, 693 /* ucGPIO=DRAM_SELF_REFRESH_GPIO_PIND uses for memory self refresh (ucGPIO=0, DRAM self-refresh; ucGPIO= */ 694 DRAM_SELF_REFRESH_GPIO_PINID = 64, 695 /* Thermal interrupt output->system thermal chip GPIO pin */ 696 THERMAL_INT_OUTPUT_GPIO_PINID =65, 697 }; 698 699 700 struct atom_gpio_pin_lut_v2_1 701 { 702 struct atom_common_table_header table_header; 703 /*the real number of this included in the structure is calcualted by using the (whole structure size - the header size)/size of atom_gpio_pin_lut */ 704 struct atom_gpio_pin_assignment gpio_pin[8]; 705 }; 706 707 708 /* 709 * VBIOS/PRE-OS always reserve a FB region at the top of frame buffer. driver should not write 710 * access that region. driver can allocate their own reservation region as long as it does not 711 * overlap firwmare's reservation region. 712 * if (pre-NV1X) atom data table firmwareInfoTable version < 3.3: 713 * in this case, atom data table vram_usagebyfirmwareTable version always <= 2.1 714 * if VBIOS/UEFI GOP is posted: 715 * VBIOS/UEFIGOP update used_by_firmware_in_kb = total reserved size by VBIOS 716 * update start_address_in_kb = total_mem_size_in_kb - used_by_firmware_in_kb; 717 * ( total_mem_size_in_kb = reg(CONFIG_MEMSIZE)<<10) 718 * driver can allocate driver reservation region under firmware reservation, 719 * used_by_driver_in_kb = driver reservation size 720 * driver reservation start address = (start_address_in_kb - used_by_driver_in_kb) 721 * Comment1[hchan]: There is only one reservation at the beginning of the FB reserved by 722 * host driver. Host driver would overwrite the table with the following 723 * used_by_firmware_in_kb = total reserved size for pf-vf info exchange and 724 * set SRIOV_MSG_SHARE_RESERVATION mask start_address_in_kb = 0 725 * else there is no VBIOS reservation region: 726 * driver must allocate driver reservation region at top of FB. 727 * driver set used_by_driver_in_kb = driver reservation size 728 * driver reservation start address = (total_mem_size_in_kb - used_by_driver_in_kb) 729 * same as Comment1 730 * else (NV1X and after): 731 * if VBIOS/UEFI GOP is posted: 732 * VBIOS/UEFIGOP update: 733 * used_by_firmware_in_kb = atom_firmware_Info_v3_3.fw_reserved_size_in_kb; 734 * start_address_in_kb = total_mem_size_in_kb - used_by_firmware_in_kb; 735 * (total_mem_size_in_kb = reg(CONFIG_MEMSIZE)<<10) 736 * if vram_usagebyfirmwareTable version <= 2.1: 737 * driver can allocate driver reservation region under firmware reservation, 738 * driver set used_by_driver_in_kb = driver reservation size 739 * driver reservation start address = start_address_in_kb - used_by_driver_in_kb 740 * same as Comment1 741 * else driver can: 742 * allocate it reservation any place as long as it does overlap pre-OS FW reservation area 743 * set used_by_driver_region0_in_kb = driver reservation size 744 * set driver_region0_start_address_in_kb = driver reservation region start address 745 * Comment2[hchan]: Host driver can set used_by_firmware_in_kb and start_address_in_kb to 746 * zero as the reservation for VF as it doesn’t exist. And Host driver should also 747 * update atom_firmware_Info table to remove the same VBIOS reservation as well. 748 */ 749 750 struct vram_usagebyfirmware_v2_1 751 { 752 struct atom_common_table_header table_header; 753 uint32_t start_address_in_kb; 754 uint16_t used_by_firmware_in_kb; 755 uint16_t used_by_driver_in_kb; 756 }; 757 758 struct vram_usagebyfirmware_v2_2 { 759 struct atom_common_table_header table_header; 760 uint32_t fw_region_start_address_in_kb; 761 uint16_t used_by_firmware_in_kb; 762 uint16_t reserved; 763 uint32_t driver_region0_start_address_in_kb; 764 uint32_t used_by_driver_region0_in_kb; 765 uint32_t reserved32[7]; 766 }; 767 768 /* 769 *************************************************************************** 770 Data Table displayobjectinfo structure 771 *************************************************************************** 772 */ 773 774 enum atom_object_record_type_id { 775 ATOM_I2C_RECORD_TYPE = 1, 776 ATOM_HPD_INT_RECORD_TYPE = 2, 777 ATOM_CONNECTOR_CAP_RECORD_TYPE = 3, 778 ATOM_CONNECTOR_SPEED_UPTO = 4, 779 ATOM_OBJECT_GPIO_CNTL_RECORD_TYPE = 9, 780 ATOM_CONNECTOR_HPDPIN_LUT_RECORD_TYPE = 16, 781 ATOM_CONNECTOR_AUXDDC_LUT_RECORD_TYPE = 17, 782 ATOM_ENCODER_CAP_RECORD_TYPE = 20, 783 ATOM_BRACKET_LAYOUT_RECORD_TYPE = 21, 784 ATOM_CONNECTOR_FORCED_TMDS_CAP_RECORD_TYPE = 22, 785 ATOM_DISP_CONNECTOR_CAPS_RECORD_TYPE = 23, 786 ATOM_BRACKET_LAYOUT_V2_RECORD_TYPE = 25, 787 ATOM_RECORD_END_TYPE = 0xFF, 788 }; 789 790 struct atom_common_record_header 791 { 792 uint8_t record_type; //An emun to indicate the record type 793 uint8_t record_size; //The size of the whole record in byte 794 }; 795 796 struct atom_i2c_record 797 { 798 struct atom_common_record_header record_header; //record_type = ATOM_I2C_RECORD_TYPE 799 uint8_t i2c_id; 800 uint8_t i2c_slave_addr; //The slave address, it's 0 when the record is attached to connector for DDC 801 }; 802 803 struct atom_hpd_int_record 804 { 805 struct atom_common_record_header record_header; //record_type = ATOM_HPD_INT_RECORD_TYPE 806 uint8_t pin_id; //Corresponding block in GPIO_PIN_INFO table gives the pin info 807 uint8_t plugin_pin_state; 808 }; 809 810 struct atom_connector_caps_record { 811 struct atom_common_record_header 812 record_header; //record_type = ATOM_CONN_CAP_RECORD_TYPE 813 uint16_t connector_caps; //01b if internal display is checked; 10b if internal BL is checked; 0 of Not 814 }; 815 816 struct atom_connector_speed_record { 817 struct atom_common_record_header 818 record_header; //record_type = ATOM_CONN_SPEED_UPTO 819 uint32_t connector_max_speed; // connector Max speed attribute, it sets 8100 in Mhz when DP connector @8.1Ghz. 820 uint16_t reserved; 821 }; 822 823 // Bit maps for ATOM_ENCODER_CAP_RECORD.usEncoderCap 824 enum atom_encoder_caps_def 825 { 826 ATOM_ENCODER_CAP_RECORD_HBR2 =0x01, // DP1.2 HBR2 is supported by HW encoder, it is retired in NI. the real meaning from SI is MST_EN 827 ATOM_ENCODER_CAP_RECORD_MST_EN =0x01, // from SI, this bit means DP MST is enable or not. 828 ATOM_ENCODER_CAP_RECORD_HBR2_EN =0x02, // DP1.2 HBR2 setting is qualified and HBR2 can be enabled 829 ATOM_ENCODER_CAP_RECORD_HDMI6Gbps_EN =0x04, // HDMI2.0 6Gbps enable or not. 830 ATOM_ENCODER_CAP_RECORD_HBR3_EN =0x08, // DP1.3 HBR3 is supported by board. 831 ATOM_ENCODER_CAP_RECORD_DP2 =0x10, // DP2 is supported by ASIC/board. 832 ATOM_ENCODER_CAP_RECORD_UHBR10_EN =0x20, // DP2.0 UHBR10 settings is supported by board 833 ATOM_ENCODER_CAP_RECORD_UHBR13_5_EN =0x40, // DP2.0 UHBR13.5 settings is supported by board 834 ATOM_ENCODER_CAP_RECORD_UHBR20_EN =0x80, // DP2.0 UHBR20 settings is supported by board 835 ATOM_ENCODER_CAP_RECORD_USB_C_TYPE =0x100, // the DP connector is a USB-C type. 836 }; 837 838 struct atom_encoder_caps_record 839 { 840 struct atom_common_record_header record_header; //record_type = ATOM_ENCODER_CAP_RECORD_TYPE 841 uint32_t encodercaps; 842 }; 843 844 enum atom_connector_caps_def 845 { 846 ATOM_CONNECTOR_CAP_INTERNAL_DISPLAY = 0x01, //a cap bit to indicate that this non-embedded display connector is an internal display 847 ATOM_CONNECTOR_CAP_INTERNAL_DISPLAY_BL = 0x02, //a cap bit to indicate that this internal display requires BL control from GPU, refers to lcd_info for BL PWM freq 848 }; 849 850 struct atom_disp_connector_caps_record 851 { 852 struct atom_common_record_header record_header; 853 uint32_t connectcaps; 854 }; 855 856 //The following generic object gpio pin control record type will replace JTAG_RECORD/FPGA_CONTROL_RECORD/DVI_EXT_INPUT_RECORD above gradually 857 struct atom_gpio_pin_control_pair 858 { 859 uint8_t gpio_id; // GPIO_ID, find the corresponding ID in GPIO_LUT table 860 uint8_t gpio_pinstate; // Pin state showing how to set-up the pin 861 }; 862 863 struct atom_object_gpio_cntl_record 864 { 865 struct atom_common_record_header record_header; 866 uint8_t flag; // Future expnadibility 867 uint8_t number_of_pins; // Number of GPIO pins used to control the object 868 struct atom_gpio_pin_control_pair gpio[1]; // the real gpio pin pair determined by number of pins ucNumberOfPins 869 }; 870 871 //Definitions for GPIO pin state 872 enum atom_gpio_pin_control_pinstate_def 873 { 874 GPIO_PIN_TYPE_INPUT = 0x00, 875 GPIO_PIN_TYPE_OUTPUT = 0x10, 876 GPIO_PIN_TYPE_HW_CONTROL = 0x20, 877 878 //For GPIO_PIN_TYPE_OUTPUT the following is defined 879 GPIO_PIN_OUTPUT_STATE_MASK = 0x01, 880 GPIO_PIN_OUTPUT_STATE_SHIFT = 0, 881 GPIO_PIN_STATE_ACTIVE_LOW = 0x0, 882 GPIO_PIN_STATE_ACTIVE_HIGH = 0x1, 883 }; 884 885 // Indexes to GPIO array in GLSync record 886 // GLSync record is for Frame Lock/Gen Lock feature. 887 enum atom_glsync_record_gpio_index_def 888 { 889 ATOM_GPIO_INDEX_GLSYNC_REFCLK = 0, 890 ATOM_GPIO_INDEX_GLSYNC_HSYNC = 1, 891 ATOM_GPIO_INDEX_GLSYNC_VSYNC = 2, 892 ATOM_GPIO_INDEX_GLSYNC_SWAP_REQ = 3, 893 ATOM_GPIO_INDEX_GLSYNC_SWAP_GNT = 4, 894 ATOM_GPIO_INDEX_GLSYNC_INTERRUPT = 5, 895 ATOM_GPIO_INDEX_GLSYNC_V_RESET = 6, 896 ATOM_GPIO_INDEX_GLSYNC_SWAP_CNTL = 7, 897 ATOM_GPIO_INDEX_GLSYNC_SWAP_SEL = 8, 898 ATOM_GPIO_INDEX_GLSYNC_MAX = 9, 899 }; 900 901 902 struct atom_connector_hpdpin_lut_record //record for ATOM_CONNECTOR_HPDPIN_LUT_RECORD_TYPE 903 { 904 struct atom_common_record_header record_header; 905 uint8_t hpd_pin_map[8]; 906 }; 907 908 struct atom_connector_auxddc_lut_record //record for ATOM_CONNECTOR_AUXDDC_LUT_RECORD_TYPE 909 { 910 struct atom_common_record_header record_header; 911 uint8_t aux_ddc_map[8]; 912 }; 913 914 struct atom_connector_forced_tmds_cap_record 915 { 916 struct atom_common_record_header record_header; 917 // override TMDS capability on this connector when it operate in TMDS mode. usMaxTmdsClkRate = max TMDS Clock in Mhz/2.5 918 uint8_t maxtmdsclkrate_in2_5mhz; 919 uint8_t reserved; 920 }; 921 922 struct atom_connector_layout_info 923 { 924 uint16_t connectorobjid; 925 uint8_t connector_type; 926 uint8_t position; 927 }; 928 929 // define ATOM_CONNECTOR_LAYOUT_INFO.ucConnectorType to describe the display connector size 930 enum atom_connector_layout_info_connector_type_def 931 { 932 CONNECTOR_TYPE_DVI_D = 1, 933 934 CONNECTOR_TYPE_HDMI = 4, 935 CONNECTOR_TYPE_DISPLAY_PORT = 5, 936 CONNECTOR_TYPE_MINI_DISPLAY_PORT = 6, 937 }; 938 939 struct atom_bracket_layout_record 940 { 941 struct atom_common_record_header record_header; 942 uint8_t bracketlen; 943 uint8_t bracketwidth; 944 uint8_t conn_num; 945 uint8_t reserved; 946 struct atom_connector_layout_info conn_info[1]; 947 }; 948 struct atom_bracket_layout_record_v2 { 949 struct atom_common_record_header 950 record_header; //record_type = ATOM_BRACKET_LAYOUT_RECORD_TYPE 951 uint8_t bracketlen; //Bracket Length in mm 952 uint8_t bracketwidth; //Bracket Width in mm 953 uint8_t conn_num; //Connector numbering 954 uint8_t mini_type; //Mini Type (0 = Normal; 1 = Mini) 955 uint8_t reserved1; 956 uint8_t reserved2; 957 }; 958 959 enum atom_connector_layout_info_mini_type_def { 960 MINI_TYPE_NORMAL = 0, 961 MINI_TYPE_MINI = 1, 962 }; 963 964 enum atom_display_device_tag_def{ 965 ATOM_DISPLAY_LCD1_SUPPORT = 0x0002, //an embedded display is either an LVDS or eDP signal type of display 966 ATOM_DISPLAY_LCD2_SUPPORT = 0x0020, //second edp device tag 0x0020 for backward compability 967 ATOM_DISPLAY_DFP1_SUPPORT = 0x0008, 968 ATOM_DISPLAY_DFP2_SUPPORT = 0x0080, 969 ATOM_DISPLAY_DFP3_SUPPORT = 0x0200, 970 ATOM_DISPLAY_DFP4_SUPPORT = 0x0400, 971 ATOM_DISPLAY_DFP5_SUPPORT = 0x0800, 972 ATOM_DISPLAY_DFP6_SUPPORT = 0x0040, 973 ATOM_DISPLAY_DFPx_SUPPORT = 0x0ec8, 974 }; 975 976 struct atom_display_object_path_v2 977 { 978 uint16_t display_objid; //Connector Object ID or Misc Object ID 979 uint16_t disp_recordoffset; 980 uint16_t encoderobjid; //first encoder closer to the connector, could be either an external or intenal encoder 981 uint16_t extencoderobjid; //2nd encoder after the first encoder, from the connector point of view; 982 uint16_t encoder_recordoffset; 983 uint16_t extencoder_recordoffset; 984 uint16_t device_tag; //a supported device vector, each display path starts with this.the paths are enumerated in the way of priority, a path appears first 985 uint8_t priority_id; 986 uint8_t reserved; 987 }; 988 989 struct atom_display_object_path_v3 { 990 uint16_t display_objid; //Connector Object ID or Misc Object ID 991 uint16_t disp_recordoffset; 992 uint16_t encoderobjid; //first encoder closer to the connector, could be either an external or intenal encoder 993 uint16_t reserved1; //only on USBC case, otherwise always = 0 994 uint16_t reserved2; //reserved and always = 0 995 uint16_t reserved3; //reserved and always = 0 996 //a supported device vector, each display path starts with this.the paths are enumerated in the way of priority, 997 //a path appears first 998 uint16_t device_tag; 999 uint16_t reserved4; //reserved and always = 0 1000 }; 1001 1002 struct display_object_info_table_v1_4 1003 { 1004 struct atom_common_table_header table_header; 1005 uint16_t supporteddevices; 1006 uint8_t number_of_path; 1007 uint8_t reserved; 1008 struct atom_display_object_path_v2 display_path[8]; //the real number of this included in the structure is calculated by using the (whole structure size - the header size- number_of_path)/size of atom_display_object_path 1009 }; 1010 1011 struct display_object_info_table_v1_5 { 1012 struct atom_common_table_header table_header; 1013 uint16_t supporteddevices; 1014 uint8_t number_of_path; 1015 uint8_t reserved; 1016 // the real number of this included in the structure is calculated by using the 1017 // (whole structure size - the header size- number_of_path)/size of atom_display_object_path 1018 struct atom_display_object_path_v3 display_path[8]; 1019 }; 1020 1021 /* 1022 *************************************************************************** 1023 Data Table dce_info structure 1024 *************************************************************************** 1025 */ 1026 struct atom_display_controller_info_v4_1 1027 { 1028 struct atom_common_table_header table_header; 1029 uint32_t display_caps; 1030 uint32_t bootup_dispclk_10khz; 1031 uint16_t dce_refclk_10khz; 1032 uint16_t i2c_engine_refclk_10khz; 1033 uint16_t dvi_ss_percentage; // in unit of 0.001% 1034 uint16_t dvi_ss_rate_10hz; 1035 uint16_t hdmi_ss_percentage; // in unit of 0.001% 1036 uint16_t hdmi_ss_rate_10hz; 1037 uint16_t dp_ss_percentage; // in unit of 0.001% 1038 uint16_t dp_ss_rate_10hz; 1039 uint8_t dvi_ss_mode; // enum of atom_spread_spectrum_mode 1040 uint8_t hdmi_ss_mode; // enum of atom_spread_spectrum_mode 1041 uint8_t dp_ss_mode; // enum of atom_spread_spectrum_mode 1042 uint8_t ss_reserved; 1043 uint8_t hardcode_mode_num; // a hardcode mode number defined in StandardVESA_TimingTable when a CRT or DFP EDID is not available 1044 uint8_t reserved1[3]; 1045 uint16_t dpphy_refclk_10khz; 1046 uint16_t reserved2; 1047 uint8_t dceip_min_ver; 1048 uint8_t dceip_max_ver; 1049 uint8_t max_disp_pipe_num; 1050 uint8_t max_vbios_active_disp_pipe_num; 1051 uint8_t max_ppll_num; 1052 uint8_t max_disp_phy_num; 1053 uint8_t max_aux_pairs; 1054 uint8_t remotedisplayconfig; 1055 uint8_t reserved3[8]; 1056 }; 1057 1058 struct atom_display_controller_info_v4_2 1059 { 1060 struct atom_common_table_header table_header; 1061 uint32_t display_caps; 1062 uint32_t bootup_dispclk_10khz; 1063 uint16_t dce_refclk_10khz; 1064 uint16_t i2c_engine_refclk_10khz; 1065 uint16_t dvi_ss_percentage; // in unit of 0.001% 1066 uint16_t dvi_ss_rate_10hz; 1067 uint16_t hdmi_ss_percentage; // in unit of 0.001% 1068 uint16_t hdmi_ss_rate_10hz; 1069 uint16_t dp_ss_percentage; // in unit of 0.001% 1070 uint16_t dp_ss_rate_10hz; 1071 uint8_t dvi_ss_mode; // enum of atom_spread_spectrum_mode 1072 uint8_t hdmi_ss_mode; // enum of atom_spread_spectrum_mode 1073 uint8_t dp_ss_mode; // enum of atom_spread_spectrum_mode 1074 uint8_t ss_reserved; 1075 uint8_t dfp_hardcode_mode_num; // DFP hardcode mode number defined in StandardVESA_TimingTable when EDID is not available 1076 uint8_t dfp_hardcode_refreshrate;// DFP hardcode mode refreshrate defined in StandardVESA_TimingTable when EDID is not available 1077 uint8_t vga_hardcode_mode_num; // VGA hardcode mode number defined in StandardVESA_TimingTable when EDID is not avablable 1078 uint8_t vga_hardcode_refreshrate;// VGA hardcode mode number defined in StandardVESA_TimingTable when EDID is not avablable 1079 uint16_t dpphy_refclk_10khz; 1080 uint16_t reserved2; 1081 uint8_t dcnip_min_ver; 1082 uint8_t dcnip_max_ver; 1083 uint8_t max_disp_pipe_num; 1084 uint8_t max_vbios_active_disp_pipe_num; 1085 uint8_t max_ppll_num; 1086 uint8_t max_disp_phy_num; 1087 uint8_t max_aux_pairs; 1088 uint8_t remotedisplayconfig; 1089 uint8_t reserved3[8]; 1090 }; 1091 1092 struct atom_display_controller_info_v4_3 1093 { 1094 struct atom_common_table_header table_header; 1095 uint32_t display_caps; 1096 uint32_t bootup_dispclk_10khz; 1097 uint16_t dce_refclk_10khz; 1098 uint16_t i2c_engine_refclk_10khz; 1099 uint16_t dvi_ss_percentage; // in unit of 0.001% 1100 uint16_t dvi_ss_rate_10hz; 1101 uint16_t hdmi_ss_percentage; // in unit of 0.001% 1102 uint16_t hdmi_ss_rate_10hz; 1103 uint16_t dp_ss_percentage; // in unit of 0.001% 1104 uint16_t dp_ss_rate_10hz; 1105 uint8_t dvi_ss_mode; // enum of atom_spread_spectrum_mode 1106 uint8_t hdmi_ss_mode; // enum of atom_spread_spectrum_mode 1107 uint8_t dp_ss_mode; // enum of atom_spread_spectrum_mode 1108 uint8_t ss_reserved; 1109 uint8_t dfp_hardcode_mode_num; // DFP hardcode mode number defined in StandardVESA_TimingTable when EDID is not available 1110 uint8_t dfp_hardcode_refreshrate;// DFP hardcode mode refreshrate defined in StandardVESA_TimingTable when EDID is not available 1111 uint8_t vga_hardcode_mode_num; // VGA hardcode mode number defined in StandardVESA_TimingTable when EDID is not avablable 1112 uint8_t vga_hardcode_refreshrate;// VGA hardcode mode number defined in StandardVESA_TimingTable when EDID is not avablable 1113 uint16_t dpphy_refclk_10khz; 1114 uint16_t reserved2; 1115 uint8_t dcnip_min_ver; 1116 uint8_t dcnip_max_ver; 1117 uint8_t max_disp_pipe_num; 1118 uint8_t max_vbios_active_disp_pipe_num; 1119 uint8_t max_ppll_num; 1120 uint8_t max_disp_phy_num; 1121 uint8_t max_aux_pairs; 1122 uint8_t remotedisplayconfig; 1123 uint8_t reserved3[8]; 1124 }; 1125 1126 struct atom_display_controller_info_v4_4 { 1127 struct atom_common_table_header table_header; 1128 uint32_t display_caps; 1129 uint32_t bootup_dispclk_10khz; 1130 uint16_t dce_refclk_10khz; 1131 uint16_t i2c_engine_refclk_10khz; 1132 uint16_t dvi_ss_percentage; // in unit of 0.001% 1133 uint16_t dvi_ss_rate_10hz; 1134 uint16_t hdmi_ss_percentage; // in unit of 0.001% 1135 uint16_t hdmi_ss_rate_10hz; 1136 uint16_t dp_ss_percentage; // in unit of 0.001% 1137 uint16_t dp_ss_rate_10hz; 1138 uint8_t dvi_ss_mode; // enum of atom_spread_spectrum_mode 1139 uint8_t hdmi_ss_mode; // enum of atom_spread_spectrum_mode 1140 uint8_t dp_ss_mode; // enum of atom_spread_spectrum_mode 1141 uint8_t ss_reserved; 1142 uint8_t dfp_hardcode_mode_num; // DFP hardcode mode number defined in StandardVESA_TimingTable when EDID is not available 1143 uint8_t dfp_hardcode_refreshrate;// DFP hardcode mode refreshrate defined in StandardVESA_TimingTable when EDID is not available 1144 uint8_t vga_hardcode_mode_num; // VGA hardcode mode number defined in StandardVESA_TimingTable when EDID is not avablable 1145 uint8_t vga_hardcode_refreshrate;// VGA hardcode mode number defined in StandardVESA_TimingTable when EDID is not avablable 1146 uint16_t dpphy_refclk_10khz; 1147 uint16_t hw_chip_id; 1148 uint8_t dcnip_min_ver; 1149 uint8_t dcnip_max_ver; 1150 uint8_t max_disp_pipe_num; 1151 uint8_t max_vbios_active_disp_pipum; 1152 uint8_t max_ppll_num; 1153 uint8_t max_disp_phy_num; 1154 uint8_t max_aux_pairs; 1155 uint8_t remotedisplayconfig; 1156 uint32_t dispclk_pll_vco_freq; 1157 uint32_t dp_ref_clk_freq; 1158 uint32_t max_mclk_chg_lat; // Worst case blackout duration for a memory clock frequency (p-state) change, units of 100s of ns (0.1 us) 1159 uint32_t max_sr_exit_lat; // Worst case memory self refresh exit time, units of 100ns of ns (0.1us) 1160 uint32_t max_sr_enter_exit_lat; // Worst case memory self refresh entry followed by immediate exit time, units of 100ns of ns (0.1us) 1161 uint16_t dc_golden_table_offset; // point of struct of atom_dc_golden_table_vxx 1162 uint16_t dc_golden_table_ver; 1163 uint32_t reserved3[3]; 1164 }; 1165 1166 struct atom_dc_golden_table_v1 1167 { 1168 uint32_t aux_dphy_rx_control0_val; 1169 uint32_t aux_dphy_tx_control_val; 1170 uint32_t aux_dphy_rx_control1_val; 1171 uint32_t dc_gpio_aux_ctrl_0_val; 1172 uint32_t dc_gpio_aux_ctrl_1_val; 1173 uint32_t dc_gpio_aux_ctrl_2_val; 1174 uint32_t dc_gpio_aux_ctrl_3_val; 1175 uint32_t dc_gpio_aux_ctrl_4_val; 1176 uint32_t dc_gpio_aux_ctrl_5_val; 1177 uint32_t reserved[23]; 1178 }; 1179 1180 enum dce_info_caps_def { 1181 // only for VBIOS 1182 DCE_INFO_CAPS_FORCE_DISPDEV_CONNECTED = 0x02, 1183 // only for VBIOS 1184 DCE_INFO_CAPS_DISABLE_DFP_DP_HBR2 = 0x04, 1185 // only for VBIOS 1186 DCE_INFO_CAPS_ENABLE_INTERLAC_TIMING = 0x08, 1187 // only for VBIOS 1188 DCE_INFO_CAPS_LTTPR_SUPPORT_ENABLE = 0x20, 1189 DCE_INFO_CAPS_VBIOS_LTTPR_TRANSPARENT_ENABLE = 0x40, 1190 }; 1191 1192 struct atom_display_controller_info_v4_5 1193 { 1194 struct atom_common_table_header table_header; 1195 uint32_t display_caps; 1196 uint32_t bootup_dispclk_10khz; 1197 uint16_t dce_refclk_10khz; 1198 uint16_t i2c_engine_refclk_10khz; 1199 uint16_t dvi_ss_percentage; // in unit of 0.001% 1200 uint16_t dvi_ss_rate_10hz; 1201 uint16_t hdmi_ss_percentage; // in unit of 0.001% 1202 uint16_t hdmi_ss_rate_10hz; 1203 uint16_t dp_ss_percentage; // in unit of 0.001% 1204 uint16_t dp_ss_rate_10hz; 1205 uint8_t dvi_ss_mode; // enum of atom_spread_spectrum_mode 1206 uint8_t hdmi_ss_mode; // enum of atom_spread_spectrum_mode 1207 uint8_t dp_ss_mode; // enum of atom_spread_spectrum_mode 1208 uint8_t ss_reserved; 1209 // DFP hardcode mode number defined in StandardVESA_TimingTable when EDID is not available 1210 uint8_t dfp_hardcode_mode_num; 1211 // DFP hardcode mode refreshrate defined in StandardVESA_TimingTable when EDID is not available 1212 uint8_t dfp_hardcode_refreshrate; 1213 // VGA hardcode mode number defined in StandardVESA_TimingTable when EDID is not avablable 1214 uint8_t vga_hardcode_mode_num; 1215 // VGA hardcode mode number defined in StandardVESA_TimingTable when EDID is not avablable 1216 uint8_t vga_hardcode_refreshrate; 1217 uint16_t dpphy_refclk_10khz; 1218 uint16_t hw_chip_id; 1219 uint8_t dcnip_min_ver; 1220 uint8_t dcnip_max_ver; 1221 uint8_t max_disp_pipe_num; 1222 uint8_t max_vbios_active_disp_pipe_num; 1223 uint8_t max_ppll_num; 1224 uint8_t max_disp_phy_num; 1225 uint8_t max_aux_pairs; 1226 uint8_t remotedisplayconfig; 1227 uint32_t dispclk_pll_vco_freq; 1228 uint32_t dp_ref_clk_freq; 1229 // Worst case blackout duration for a memory clock frequency (p-state) change, units of 100s of ns (0.1 us) 1230 uint32_t max_mclk_chg_lat; 1231 // Worst case memory self refresh exit time, units of 100ns of ns (0.1us) 1232 uint32_t max_sr_exit_lat; 1233 // Worst case memory self refresh entry followed by immediate exit time, units of 100ns of ns (0.1us) 1234 uint32_t max_sr_enter_exit_lat; 1235 uint16_t dc_golden_table_offset; // point of struct of atom_dc_golden_table_vxx 1236 uint16_t dc_golden_table_ver; 1237 uint32_t aux_dphy_rx_control0_val; 1238 uint32_t aux_dphy_tx_control_val; 1239 uint32_t aux_dphy_rx_control1_val; 1240 uint32_t dc_gpio_aux_ctrl_0_val; 1241 uint32_t dc_gpio_aux_ctrl_1_val; 1242 uint32_t dc_gpio_aux_ctrl_2_val; 1243 uint32_t dc_gpio_aux_ctrl_3_val; 1244 uint32_t dc_gpio_aux_ctrl_4_val; 1245 uint32_t dc_gpio_aux_ctrl_5_val; 1246 uint32_t reserved[26]; 1247 }; 1248 1249 /* 1250 *************************************************************************** 1251 Data Table ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO structure 1252 *************************************************************************** 1253 */ 1254 struct atom_ext_display_path 1255 { 1256 uint16_t device_tag; //A bit vector to show what devices are supported 1257 uint16_t device_acpi_enum; //16bit device ACPI id. 1258 uint16_t connectorobjid; //A physical connector for displays to plug in, using object connector definitions 1259 uint8_t auxddclut_index; //An index into external AUX/DDC channel LUT 1260 uint8_t hpdlut_index; //An index into external HPD pin LUT 1261 uint16_t ext_encoder_objid; //external encoder object id 1262 uint8_t channelmapping; // if ucChannelMapping=0, using default one to one mapping 1263 uint8_t chpninvert; // bit vector for up to 8 lanes, =0: P and N is not invert, =1 P and N is inverted 1264 uint16_t caps; 1265 uint16_t reserved; 1266 }; 1267 1268 //usCaps 1269 enum ext_display_path_cap_def { 1270 EXT_DISPLAY_PATH_CAPS__HBR2_DISABLE = 0x0001, 1271 EXT_DISPLAY_PATH_CAPS__DP_FIXED_VS_EN = 0x0002, 1272 EXT_DISPLAY_PATH_CAPS__EXT_CHIP_MASK = 0x007C, 1273 EXT_DISPLAY_PATH_CAPS__HDMI20_PI3EQX1204 = (0x01 << 2), //PI redriver chip 1274 EXT_DISPLAY_PATH_CAPS__HDMI20_TISN65DP159RSBT = (0x02 << 2), //TI retimer chip 1275 EXT_DISPLAY_PATH_CAPS__HDMI20_PARADE_PS175 = (0x03 << 2) //Parade DP->HDMI recoverter chip 1276 }; 1277 1278 struct atom_external_display_connection_info 1279 { 1280 struct atom_common_table_header table_header; 1281 uint8_t guid[16]; // a GUID is a 16 byte long string 1282 struct atom_ext_display_path path[7]; // total of fixed 7 entries. 1283 uint8_t checksum; // a simple Checksum of the sum of whole structure equal to 0x0. 1284 uint8_t stereopinid; // use for eDP panel 1285 uint8_t remotedisplayconfig; 1286 uint8_t edptolvdsrxid; 1287 uint8_t fixdpvoltageswing; // usCaps[1]=1, this indicate DP_LANE_SET value 1288 uint8_t reserved[3]; // for potential expansion 1289 }; 1290 1291 /* 1292 *************************************************************************** 1293 Data Table integratedsysteminfo structure 1294 *************************************************************************** 1295 */ 1296 1297 struct atom_camera_dphy_timing_param 1298 { 1299 uint8_t profile_id; // SENSOR_PROFILES 1300 uint32_t param; 1301 }; 1302 1303 struct atom_camera_dphy_elec_param 1304 { 1305 uint16_t param[3]; 1306 }; 1307 1308 struct atom_camera_module_info 1309 { 1310 uint8_t module_id; // 0: Rear, 1: Front right of user, 2: Front left of user 1311 uint8_t module_name[8]; 1312 struct atom_camera_dphy_timing_param timingparam[6]; // Exact number is under estimation and confirmation from sensor vendor 1313 }; 1314 1315 struct atom_camera_flashlight_info 1316 { 1317 uint8_t flashlight_id; // 0: Rear, 1: Front 1318 uint8_t name[8]; 1319 }; 1320 1321 struct atom_camera_data 1322 { 1323 uint32_t versionCode; 1324 struct atom_camera_module_info cameraInfo[3]; // Assuming 3 camera sensors max 1325 struct atom_camera_flashlight_info flashInfo; // Assuming 1 flashlight max 1326 struct atom_camera_dphy_elec_param dphy_param; 1327 uint32_t crc_val; // CRC 1328 }; 1329 1330 1331 struct atom_14nm_dpphy_dvihdmi_tuningset 1332 { 1333 uint32_t max_symclk_in10khz; 1334 uint8_t encoder_mode; //atom_encode_mode_def, =2: DVI, =3: HDMI mode 1335 uint8_t phy_sel; //bit vector of phy, bit0= phya, bit1=phyb, ....bit5 = phyf 1336 uint16_t margindeemph; //COMMON_MAR_DEEMPH_NOM[7:0]tx_margin_nom [15:8]deemph_gen1_nom 1337 uint8_t deemph_6db_4; //COMMON_SELDEEMPH60[31:24]deemph_6db_4 1338 uint8_t boostadj; //CMD_BUS_GLOBAL_FOR_TX_LANE0 [19:16]tx_boost_adj [20]tx_boost_en [23:22]tx_binary_ron_code_offset 1339 uint8_t tx_driver_fifty_ohms; //COMMON_ZCALCODE_CTRL[21].tx_driver_fifty_ohms 1340 uint8_t deemph_sel; //MARGIN_DEEMPH_LANE0.DEEMPH_SEL 1341 }; 1342 1343 struct atom_14nm_dpphy_dp_setting{ 1344 uint8_t dp_vs_pemph_level; //enum of atom_dp_vs_preemph_def 1345 uint16_t margindeemph; //COMMON_MAR_DEEMPH_NOM[7:0]tx_margin_nom [15:8]deemph_gen1_nom 1346 uint8_t deemph_6db_4; //COMMON_SELDEEMPH60[31:24]deemph_6db_4 1347 uint8_t boostadj; //CMD_BUS_GLOBAL_FOR_TX_LANE0 [19:16]tx_boost_adj [20]tx_boost_en [23:22]tx_binary_ron_code_offset 1348 }; 1349 1350 struct atom_14nm_dpphy_dp_tuningset{ 1351 uint8_t phy_sel; // bit vector of phy, bit0= phya, bit1=phyb, ....bit5 = phyf 1352 uint8_t version; 1353 uint16_t table_size; // size of atom_14nm_dpphy_dp_tuningset 1354 uint16_t reserved; 1355 struct atom_14nm_dpphy_dp_setting dptuning[10]; 1356 }; 1357 1358 struct atom_14nm_dig_transmitter_info_header_v4_0{ 1359 struct atom_common_table_header table_header; 1360 uint16_t pcie_phy_tmds_hdmi_macro_settings_offset; // offset of PCIEPhyTMDSHDMIMacroSettingsTbl 1361 uint16_t uniphy_vs_emph_lookup_table_offset; // offset of UniphyVSEmphLookUpTbl 1362 uint16_t uniphy_xbar_settings_table_offset; // offset of UniphyXbarSettingsTbl 1363 }; 1364 1365 struct atom_14nm_combphy_tmds_vs_set 1366 { 1367 uint8_t sym_clk; 1368 uint8_t dig_mode; 1369 uint8_t phy_sel; 1370 uint16_t common_mar_deemph_nom__margin_deemph_val; 1371 uint8_t common_seldeemph60__deemph_6db_4_val; 1372 uint8_t cmd_bus_global_for_tx_lane0__boostadj_val ; 1373 uint8_t common_zcalcode_ctrl__tx_driver_fifty_ohms_val; 1374 uint8_t margin_deemph_lane0__deemph_sel_val; 1375 }; 1376 1377 struct atom_DCN_dpphy_dvihdmi_tuningset 1378 { 1379 uint32_t max_symclk_in10khz; 1380 uint8_t encoder_mode; //atom_encode_mode_def, =2: DVI, =3: HDMI mode 1381 uint8_t phy_sel; //bit vector of phy, bit0= phya, bit1=phyb, ....bit5 = phyf 1382 uint8_t tx_eq_main; // map to RDPCSTX_PHY_FUSE0/1/2/3[5:0](EQ_MAIN) 1383 uint8_t tx_eq_pre; // map to RDPCSTX_PHY_FUSE0/1/2/3[11:6](EQ_PRE) 1384 uint8_t tx_eq_post; // map to RDPCSTX_PHY_FUSE0/1/2/3[17:12](EQ_POST) 1385 uint8_t reserved1; 1386 uint8_t tx_vboost_lvl; // tx_vboost_lvl, map to RDPCSTX_PHY_CNTL0.RDPCS_PHY_TX_VBOOST_LVL 1387 uint8_t reserved2; 1388 }; 1389 1390 struct atom_DCN_dpphy_dp_setting{ 1391 uint8_t dp_vs_pemph_level; //enum of atom_dp_vs_preemph_def 1392 uint8_t tx_eq_main; // map to RDPCSTX_PHY_FUSE0/1/2/3[5:0](EQ_MAIN) 1393 uint8_t tx_eq_pre; // map to RDPCSTX_PHY_FUSE0/1/2/3[11:6](EQ_PRE) 1394 uint8_t tx_eq_post; // map to RDPCSTX_PHY_FUSE0/1/2/3[17:12](EQ_POST) 1395 uint8_t tx_vboost_lvl; // tx_vboost_lvl, map to RDPCSTX_PHY_CNTL0.RDPCS_PHY_TX_VBOOST_LVL 1396 }; 1397 1398 struct atom_DCN_dpphy_dp_tuningset{ 1399 uint8_t phy_sel; // bit vector of phy, bit0= phya, bit1=phyb, ....bit5 = phyf 1400 uint8_t version; 1401 uint16_t table_size; // size of atom_14nm_dpphy_dp_setting 1402 uint16_t reserved; 1403 struct atom_DCN_dpphy_dp_setting dptunings[10]; 1404 }; 1405 1406 struct atom_i2c_reg_info { 1407 uint8_t ucI2cRegIndex; 1408 uint8_t ucI2cRegVal; 1409 }; 1410 1411 struct atom_hdmi_retimer_redriver_set { 1412 uint8_t HdmiSlvAddr; 1413 uint8_t HdmiRegNum; 1414 uint8_t Hdmi6GRegNum; 1415 struct atom_i2c_reg_info HdmiRegSetting[9]; //For non 6G Hz use 1416 struct atom_i2c_reg_info Hdmi6GhzRegSetting[3]; //For 6G Hz use. 1417 }; 1418 1419 struct atom_integrated_system_info_v1_11 1420 { 1421 struct atom_common_table_header table_header; 1422 uint32_t vbios_misc; //enum of atom_system_vbiosmisc_def 1423 uint32_t gpucapinfo; //enum of atom_system_gpucapinf_def 1424 uint32_t system_config; 1425 uint32_t cpucapinfo; 1426 uint16_t gpuclk_ss_percentage; //unit of 0.001%, 1000 mean 1% 1427 uint16_t gpuclk_ss_type; 1428 uint16_t lvds_ss_percentage; //unit of 0.001%, 1000 mean 1% 1429 uint16_t lvds_ss_rate_10hz; 1430 uint16_t hdmi_ss_percentage; //unit of 0.001%, 1000 mean 1% 1431 uint16_t hdmi_ss_rate_10hz; 1432 uint16_t dvi_ss_percentage; //unit of 0.001%, 1000 mean 1% 1433 uint16_t dvi_ss_rate_10hz; 1434 uint16_t dpphy_override; // bit vector, enum of atom_sysinfo_dpphy_override_def 1435 uint16_t lvds_misc; // enum of atom_sys_info_lvds_misc_def 1436 uint16_t backlight_pwm_hz; // pwm frequency in hz 1437 uint8_t memorytype; // enum of atom_dmi_t17_mem_type_def, APU memory type indication. 1438 uint8_t umachannelnumber; // number of memory channels 1439 uint8_t pwr_on_digon_to_de; /* all pwr sequence numbers below are in uint of 4ms */ 1440 uint8_t pwr_on_de_to_vary_bl; 1441 uint8_t pwr_down_vary_bloff_to_de; 1442 uint8_t pwr_down_de_to_digoff; 1443 uint8_t pwr_off_delay; 1444 uint8_t pwr_on_vary_bl_to_blon; 1445 uint8_t pwr_down_bloff_to_vary_bloff; 1446 uint8_t min_allowed_bl_level; 1447 uint8_t htc_hyst_limit; 1448 uint8_t htc_tmp_limit; 1449 uint8_t reserved1; 1450 uint8_t reserved2; 1451 struct atom_external_display_connection_info extdispconninfo; 1452 struct atom_14nm_dpphy_dvihdmi_tuningset dvi_tuningset; 1453 struct atom_14nm_dpphy_dvihdmi_tuningset hdmi_tuningset; 1454 struct atom_14nm_dpphy_dvihdmi_tuningset hdmi6g_tuningset; 1455 struct atom_14nm_dpphy_dp_tuningset dp_tuningset; // rbr 1.62G dp tuning set 1456 struct atom_14nm_dpphy_dp_tuningset dp_hbr3_tuningset; // HBR3 dp tuning set 1457 struct atom_camera_data camera_info; 1458 struct atom_hdmi_retimer_redriver_set dp0_retimer_set; //for DP0 1459 struct atom_hdmi_retimer_redriver_set dp1_retimer_set; //for DP1 1460 struct atom_hdmi_retimer_redriver_set dp2_retimer_set; //for DP2 1461 struct atom_hdmi_retimer_redriver_set dp3_retimer_set; //for DP3 1462 struct atom_14nm_dpphy_dp_tuningset dp_hbr_tuningset; //hbr 2.7G dp tuning set 1463 struct atom_14nm_dpphy_dp_tuningset dp_hbr2_tuningset; //hbr2 5.4G dp turnig set 1464 struct atom_14nm_dpphy_dp_tuningset edp_tuningset; //edp tuning set 1465 uint32_t reserved[66]; 1466 }; 1467 1468 struct atom_integrated_system_info_v1_12 1469 { 1470 struct atom_common_table_header table_header; 1471 uint32_t vbios_misc; //enum of atom_system_vbiosmisc_def 1472 uint32_t gpucapinfo; //enum of atom_system_gpucapinf_def 1473 uint32_t system_config; 1474 uint32_t cpucapinfo; 1475 uint16_t gpuclk_ss_percentage; //unit of 0.001%, 1000 mean 1% 1476 uint16_t gpuclk_ss_type; 1477 uint16_t lvds_ss_percentage; //unit of 0.001%, 1000 mean 1% 1478 uint16_t lvds_ss_rate_10hz; 1479 uint16_t hdmi_ss_percentage; //unit of 0.001%, 1000 mean 1% 1480 uint16_t hdmi_ss_rate_10hz; 1481 uint16_t dvi_ss_percentage; //unit of 0.001%, 1000 mean 1% 1482 uint16_t dvi_ss_rate_10hz; 1483 uint16_t dpphy_override; // bit vector, enum of atom_sysinfo_dpphy_override_def 1484 uint16_t lvds_misc; // enum of atom_sys_info_lvds_misc_def 1485 uint16_t backlight_pwm_hz; // pwm frequency in hz 1486 uint8_t memorytype; // enum of atom_dmi_t17_mem_type_def, APU memory type indication. 1487 uint8_t umachannelnumber; // number of memory channels 1488 uint8_t pwr_on_digon_to_de; // all pwr sequence numbers below are in uint of 4ms // 1489 uint8_t pwr_on_de_to_vary_bl; 1490 uint8_t pwr_down_vary_bloff_to_de; 1491 uint8_t pwr_down_de_to_digoff; 1492 uint8_t pwr_off_delay; 1493 uint8_t pwr_on_vary_bl_to_blon; 1494 uint8_t pwr_down_bloff_to_vary_bloff; 1495 uint8_t min_allowed_bl_level; 1496 uint8_t htc_hyst_limit; 1497 uint8_t htc_tmp_limit; 1498 uint8_t reserved1; 1499 uint8_t reserved2; 1500 struct atom_external_display_connection_info extdispconninfo; 1501 struct atom_DCN_dpphy_dvihdmi_tuningset TMDS_tuningset; 1502 struct atom_DCN_dpphy_dvihdmi_tuningset hdmiCLK5_tuningset; 1503 struct atom_DCN_dpphy_dvihdmi_tuningset hdmiCLK8_tuningset; 1504 struct atom_DCN_dpphy_dp_tuningset rbr_tuningset; // rbr 1.62G dp tuning set 1505 struct atom_DCN_dpphy_dp_tuningset hbr3_tuningset; // HBR3 dp tuning set 1506 struct atom_camera_data camera_info; 1507 struct atom_hdmi_retimer_redriver_set dp0_retimer_set; //for DP0 1508 struct atom_hdmi_retimer_redriver_set dp1_retimer_set; //for DP1 1509 struct atom_hdmi_retimer_redriver_set dp2_retimer_set; //for DP2 1510 struct atom_hdmi_retimer_redriver_set dp3_retimer_set; //for DP3 1511 struct atom_DCN_dpphy_dp_tuningset hbr_tuningset; //hbr 2.7G dp tuning set 1512 struct atom_DCN_dpphy_dp_tuningset hbr2_tuningset; //hbr2 5.4G dp turnig set 1513 struct atom_DCN_dpphy_dp_tuningset edp_tunings; //edp tuning set 1514 struct atom_DCN_dpphy_dvihdmi_tuningset hdmiCLK6_tuningset; 1515 uint32_t reserved[63]; 1516 }; 1517 1518 struct edp_info_table 1519 { 1520 uint16_t edp_backlight_pwm_hz; 1521 uint16_t edp_ss_percentage; 1522 uint16_t edp_ss_rate_10hz; 1523 uint16_t reserved1; 1524 uint32_t reserved2; 1525 uint8_t edp_pwr_on_off_delay; 1526 uint8_t edp_pwr_on_vary_bl_to_blon; 1527 uint8_t edp_pwr_down_bloff_to_vary_bloff; 1528 uint8_t edp_panel_bpc; 1529 uint8_t edp_bootup_bl_level; 1530 uint8_t reserved3[3]; 1531 uint32_t reserved4[3]; 1532 }; 1533 1534 struct atom_integrated_system_info_v2_1 1535 { 1536 struct atom_common_table_header table_header; 1537 uint32_t vbios_misc; //enum of atom_system_vbiosmisc_def 1538 uint32_t gpucapinfo; //enum of atom_system_gpucapinf_def 1539 uint32_t system_config; 1540 uint32_t cpucapinfo; 1541 uint16_t gpuclk_ss_percentage; //unit of 0.001%, 1000 mean 1% 1542 uint16_t gpuclk_ss_type; 1543 uint16_t dpphy_override; // bit vector, enum of atom_sysinfo_dpphy_override_def 1544 uint8_t memorytype; // enum of atom_dmi_t17_mem_type_def, APU memory type indication. 1545 uint8_t umachannelnumber; // number of memory channels 1546 uint8_t htc_hyst_limit; 1547 uint8_t htc_tmp_limit; 1548 uint8_t reserved1; 1549 uint8_t reserved2; 1550 struct edp_info_table edp1_info; 1551 struct edp_info_table edp2_info; 1552 uint32_t reserved3[8]; 1553 struct atom_external_display_connection_info extdispconninfo; 1554 struct atom_DCN_dpphy_dvihdmi_tuningset TMDS_tuningset; 1555 struct atom_DCN_dpphy_dvihdmi_tuningset hdmiCLK5_tuningset; //add clk6 1556 struct atom_DCN_dpphy_dvihdmi_tuningset hdmiCLK6_tuningset; 1557 struct atom_DCN_dpphy_dvihdmi_tuningset hdmiCLK8_tuningset; 1558 uint32_t reserved4[6];//reserve 2*sizeof(atom_DCN_dpphy_dvihdmi_tuningset) 1559 struct atom_DCN_dpphy_dp_tuningset rbr_tuningset; // rbr 1.62G dp tuning set 1560 struct atom_DCN_dpphy_dp_tuningset hbr_tuningset; //hbr 2.7G dp tuning set 1561 struct atom_DCN_dpphy_dp_tuningset hbr2_tuningset; //hbr2 5.4G dp turnig set 1562 struct atom_DCN_dpphy_dp_tuningset hbr3_tuningset; // HBR3 dp tuning set 1563 struct atom_DCN_dpphy_dp_tuningset edp_tunings; //edp tuning set 1564 uint32_t reserved5[28];//reserve 2*sizeof(atom_DCN_dpphy_dp_tuningset) 1565 struct atom_hdmi_retimer_redriver_set dp0_retimer_set; //for DP0 1566 struct atom_hdmi_retimer_redriver_set dp1_retimer_set; //for DP1 1567 struct atom_hdmi_retimer_redriver_set dp2_retimer_set; //for DP2 1568 struct atom_hdmi_retimer_redriver_set dp3_retimer_set; //for DP3 1569 uint32_t reserved6[30];// reserve size of(atom_camera_data) for camera_info 1570 uint32_t reserved7[32]; 1571 1572 }; 1573 1574 struct atom_n6_display_phy_tuning_set { 1575 uint8_t display_signal_type; 1576 uint8_t phy_sel; 1577 uint8_t preset_level; 1578 uint8_t reserved1; 1579 uint32_t reserved2; 1580 uint32_t speed_upto; 1581 uint8_t tx_vboost_level; 1582 uint8_t tx_vreg_v2i; 1583 uint8_t tx_vregdrv_byp; 1584 uint8_t tx_term_cntl; 1585 uint8_t tx_peak_level; 1586 uint8_t tx_slew_en; 1587 uint8_t tx_eq_pre; 1588 uint8_t tx_eq_main; 1589 uint8_t tx_eq_post; 1590 uint8_t tx_en_inv_pre; 1591 uint8_t tx_en_inv_post; 1592 uint8_t reserved3; 1593 uint32_t reserved4; 1594 uint32_t reserved5; 1595 uint32_t reserved6; 1596 }; 1597 1598 struct atom_display_phy_tuning_info { 1599 struct atom_common_table_header table_header; 1600 struct atom_n6_display_phy_tuning_set disp_phy_tuning[1]; 1601 }; 1602 1603 struct atom_integrated_system_info_v2_2 1604 { 1605 struct atom_common_table_header table_header; 1606 uint32_t vbios_misc; //enum of atom_system_vbiosmisc_def 1607 uint32_t gpucapinfo; //enum of atom_system_gpucapinf_def 1608 uint32_t system_config; 1609 uint32_t cpucapinfo; 1610 uint16_t gpuclk_ss_percentage; //unit of 0.001%, 1000 mean 1% 1611 uint16_t gpuclk_ss_type; 1612 uint16_t dpphy_override; // bit vector, enum of atom_sysinfo_dpphy_override_def 1613 uint8_t memorytype; // enum of atom_dmi_t17_mem_type_def, APU memory type indication. 1614 uint8_t umachannelnumber; // number of memory channels 1615 uint8_t htc_hyst_limit; 1616 uint8_t htc_tmp_limit; 1617 uint8_t reserved1; 1618 uint8_t reserved2; 1619 struct edp_info_table edp1_info; 1620 struct edp_info_table edp2_info; 1621 uint32_t reserved3[8]; 1622 struct atom_external_display_connection_info extdispconninfo; 1623 1624 uint32_t reserved4[189]; 1625 }; 1626 1627 // system_config 1628 enum atom_system_vbiosmisc_def{ 1629 INTEGRATED_SYSTEM_INFO__GET_EDID_CALLBACK_FUNC_SUPPORT = 0x01, 1630 }; 1631 1632 1633 // gpucapinfo 1634 enum atom_system_gpucapinf_def{ 1635 SYS_INFO_GPUCAPS__ENABEL_DFS_BYPASS = 0x10, 1636 }; 1637 1638 //dpphy_override 1639 enum atom_sysinfo_dpphy_override_def{ 1640 ATOM_ENABLE_DVI_TUNINGSET = 0x01, 1641 ATOM_ENABLE_HDMI_TUNINGSET = 0x02, 1642 ATOM_ENABLE_HDMI6G_TUNINGSET = 0x04, 1643 ATOM_ENABLE_DP_TUNINGSET = 0x08, 1644 ATOM_ENABLE_DP_HBR3_TUNINGSET = 0x10, 1645 }; 1646 1647 //lvds_misc 1648 enum atom_sys_info_lvds_misc_def 1649 { 1650 SYS_INFO_LVDS_MISC_888_FPDI_MODE =0x01, 1651 SYS_INFO_LVDS_MISC_888_BPC_MODE =0x04, 1652 SYS_INFO_LVDS_MISC_OVERRIDE_EN =0x08, 1653 }; 1654 1655 1656 //memorytype DMI Type 17 offset 12h - Memory Type 1657 enum atom_dmi_t17_mem_type_def{ 1658 OtherMemType = 0x01, ///< Assign 01 to Other 1659 UnknownMemType, ///< Assign 02 to Unknown 1660 DramMemType, ///< Assign 03 to DRAM 1661 EdramMemType, ///< Assign 04 to EDRAM 1662 VramMemType, ///< Assign 05 to VRAM 1663 SramMemType, ///< Assign 06 to SRAM 1664 RamMemType, ///< Assign 07 to RAM 1665 RomMemType, ///< Assign 08 to ROM 1666 FlashMemType, ///< Assign 09 to Flash 1667 EepromMemType, ///< Assign 10 to EEPROM 1668 FepromMemType, ///< Assign 11 to FEPROM 1669 EpromMemType, ///< Assign 12 to EPROM 1670 CdramMemType, ///< Assign 13 to CDRAM 1671 ThreeDramMemType, ///< Assign 14 to 3DRAM 1672 SdramMemType, ///< Assign 15 to SDRAM 1673 SgramMemType, ///< Assign 16 to SGRAM 1674 RdramMemType, ///< Assign 17 to RDRAM 1675 DdrMemType, ///< Assign 18 to DDR 1676 Ddr2MemType, ///< Assign 19 to DDR2 1677 Ddr2FbdimmMemType, ///< Assign 20 to DDR2 FB-DIMM 1678 Ddr3MemType = 0x18, ///< Assign 24 to DDR3 1679 Fbd2MemType, ///< Assign 25 to FBD2 1680 Ddr4MemType, ///< Assign 26 to DDR4 1681 LpDdrMemType, ///< Assign 27 to LPDDR 1682 LpDdr2MemType, ///< Assign 28 to LPDDR2 1683 LpDdr3MemType, ///< Assign 29 to LPDDR3 1684 LpDdr4MemType, ///< Assign 30 to LPDDR4 1685 GDdr6MemType, ///< Assign 31 to GDDR6 1686 HbmMemType, ///< Assign 32 to HBM 1687 Hbm2MemType, ///< Assign 33 to HBM2 1688 Ddr5MemType, ///< Assign 34 to DDR5 1689 LpDdr5MemType, ///< Assign 35 to LPDDR5 1690 }; 1691 1692 1693 // this Table is used starting from NL/AM, used by SBIOS and pass the IntegratedSystemInfoTable/PowerPlayInfoTable/SystemCameraInfoTable 1694 struct atom_fusion_system_info_v4 1695 { 1696 struct atom_integrated_system_info_v1_11 sysinfo; // refer to ATOM_INTEGRATED_SYSTEM_INFO_V1_8 definition 1697 uint32_t powerplayinfo[256]; // Reserve 1024 bytes space for PowerPlayInfoTable 1698 }; 1699 1700 1701 /* 1702 *************************************************************************** 1703 Data Table gfx_info structure 1704 *************************************************************************** 1705 */ 1706 1707 struct atom_gfx_info_v2_2 1708 { 1709 struct atom_common_table_header table_header; 1710 uint8_t gfxip_min_ver; 1711 uint8_t gfxip_max_ver; 1712 uint8_t max_shader_engines; 1713 uint8_t max_tile_pipes; 1714 uint8_t max_cu_per_sh; 1715 uint8_t max_sh_per_se; 1716 uint8_t max_backends_per_se; 1717 uint8_t max_texture_channel_caches; 1718 uint32_t regaddr_cp_dma_src_addr; 1719 uint32_t regaddr_cp_dma_src_addr_hi; 1720 uint32_t regaddr_cp_dma_dst_addr; 1721 uint32_t regaddr_cp_dma_dst_addr_hi; 1722 uint32_t regaddr_cp_dma_command; 1723 uint32_t regaddr_cp_status; 1724 uint32_t regaddr_rlc_gpu_clock_32; 1725 uint32_t rlc_gpu_timer_refclk; 1726 }; 1727 1728 struct atom_gfx_info_v2_3 { 1729 struct atom_common_table_header table_header; 1730 uint8_t gfxip_min_ver; 1731 uint8_t gfxip_max_ver; 1732 uint8_t max_shader_engines; 1733 uint8_t max_tile_pipes; 1734 uint8_t max_cu_per_sh; 1735 uint8_t max_sh_per_se; 1736 uint8_t max_backends_per_se; 1737 uint8_t max_texture_channel_caches; 1738 uint32_t regaddr_cp_dma_src_addr; 1739 uint32_t regaddr_cp_dma_src_addr_hi; 1740 uint32_t regaddr_cp_dma_dst_addr; 1741 uint32_t regaddr_cp_dma_dst_addr_hi; 1742 uint32_t regaddr_cp_dma_command; 1743 uint32_t regaddr_cp_status; 1744 uint32_t regaddr_rlc_gpu_clock_32; 1745 uint32_t rlc_gpu_timer_refclk; 1746 uint8_t active_cu_per_sh; 1747 uint8_t active_rb_per_se; 1748 uint16_t gcgoldenoffset; 1749 uint32_t rm21_sram_vmin_value; 1750 }; 1751 1752 struct atom_gfx_info_v2_4 1753 { 1754 struct atom_common_table_header table_header; 1755 uint8_t gfxip_min_ver; 1756 uint8_t gfxip_max_ver; 1757 uint8_t max_shader_engines; 1758 uint8_t reserved; 1759 uint8_t max_cu_per_sh; 1760 uint8_t max_sh_per_se; 1761 uint8_t max_backends_per_se; 1762 uint8_t max_texture_channel_caches; 1763 uint32_t regaddr_cp_dma_src_addr; 1764 uint32_t regaddr_cp_dma_src_addr_hi; 1765 uint32_t regaddr_cp_dma_dst_addr; 1766 uint32_t regaddr_cp_dma_dst_addr_hi; 1767 uint32_t regaddr_cp_dma_command; 1768 uint32_t regaddr_cp_status; 1769 uint32_t regaddr_rlc_gpu_clock_32; 1770 uint32_t rlc_gpu_timer_refclk; 1771 uint8_t active_cu_per_sh; 1772 uint8_t active_rb_per_se; 1773 uint16_t gcgoldenoffset; 1774 uint16_t gc_num_gprs; 1775 uint16_t gc_gsprim_buff_depth; 1776 uint16_t gc_parameter_cache_depth; 1777 uint16_t gc_wave_size; 1778 uint16_t gc_max_waves_per_simd; 1779 uint16_t gc_lds_size; 1780 uint8_t gc_num_max_gs_thds; 1781 uint8_t gc_gs_table_depth; 1782 uint8_t gc_double_offchip_lds_buffer; 1783 uint8_t gc_max_scratch_slots_per_cu; 1784 uint32_t sram_rm_fuses_val; 1785 uint32_t sram_custom_rm_fuses_val; 1786 }; 1787 1788 struct atom_gfx_info_v2_7 { 1789 struct atom_common_table_header table_header; 1790 uint8_t gfxip_min_ver; 1791 uint8_t gfxip_max_ver; 1792 uint8_t max_shader_engines; 1793 uint8_t reserved; 1794 uint8_t max_cu_per_sh; 1795 uint8_t max_sh_per_se; 1796 uint8_t max_backends_per_se; 1797 uint8_t max_texture_channel_caches; 1798 uint32_t regaddr_cp_dma_src_addr; 1799 uint32_t regaddr_cp_dma_src_addr_hi; 1800 uint32_t regaddr_cp_dma_dst_addr; 1801 uint32_t regaddr_cp_dma_dst_addr_hi; 1802 uint32_t regaddr_cp_dma_command; 1803 uint32_t regaddr_cp_status; 1804 uint32_t regaddr_rlc_gpu_clock_32; 1805 uint32_t rlc_gpu_timer_refclk; 1806 uint8_t active_cu_per_sh; 1807 uint8_t active_rb_per_se; 1808 uint16_t gcgoldenoffset; 1809 uint16_t gc_num_gprs; 1810 uint16_t gc_gsprim_buff_depth; 1811 uint16_t gc_parameter_cache_depth; 1812 uint16_t gc_wave_size; 1813 uint16_t gc_max_waves_per_simd; 1814 uint16_t gc_lds_size; 1815 uint8_t gc_num_max_gs_thds; 1816 uint8_t gc_gs_table_depth; 1817 uint8_t gc_double_offchip_lds_buffer; 1818 uint8_t gc_max_scratch_slots_per_cu; 1819 uint32_t sram_rm_fuses_val; 1820 uint32_t sram_custom_rm_fuses_val; 1821 uint8_t cut_cu; 1822 uint8_t active_cu_total; 1823 uint8_t cu_reserved[2]; 1824 uint32_t gc_config; 1825 uint8_t inactive_cu_per_se[8]; 1826 uint32_t reserved2[6]; 1827 }; 1828 1829 struct atom_gfx_info_v3_0 { 1830 struct atom_common_table_header table_header; 1831 uint8_t gfxip_min_ver; 1832 uint8_t gfxip_max_ver; 1833 uint8_t max_shader_engines; 1834 uint8_t max_tile_pipes; 1835 uint8_t max_cu_per_sh; 1836 uint8_t max_sh_per_se; 1837 uint8_t max_backends_per_se; 1838 uint8_t max_texture_channel_caches; 1839 uint32_t regaddr_lsdma_queue0_rb_rptr; 1840 uint32_t regaddr_lsdma_queue0_rb_rptr_hi; 1841 uint32_t regaddr_lsdma_queue0_rb_wptr; 1842 uint32_t regaddr_lsdma_queue0_rb_wptr_hi; 1843 uint32_t regaddr_lsdma_command; 1844 uint32_t regaddr_lsdma_status; 1845 uint32_t regaddr_golden_tsc_count_lower; 1846 uint32_t golden_tsc_count_lower_refclk; 1847 uint8_t active_wgp_per_se; 1848 uint8_t active_rb_per_se; 1849 uint8_t active_se; 1850 uint8_t reserved1; 1851 uint32_t sram_rm_fuses_val; 1852 uint32_t sram_custom_rm_fuses_val; 1853 uint32_t inactive_sa_mask; 1854 uint32_t gc_config; 1855 uint8_t inactive_wgp[16]; 1856 uint8_t inactive_rb[16]; 1857 uint32_t gdfll_as_wait_ctrl_val; 1858 uint32_t gdfll_as_step_ctrl_val; 1859 uint32_t reserved[8]; 1860 }; 1861 1862 /* 1863 *************************************************************************** 1864 Data Table smu_info structure 1865 *************************************************************************** 1866 */ 1867 struct atom_smu_info_v3_1 1868 { 1869 struct atom_common_table_header table_header; 1870 uint8_t smuip_min_ver; 1871 uint8_t smuip_max_ver; 1872 uint8_t smu_rsd1; 1873 uint8_t gpuclk_ss_mode; // enum of atom_spread_spectrum_mode 1874 uint16_t sclk_ss_percentage; 1875 uint16_t sclk_ss_rate_10hz; 1876 uint16_t gpuclk_ss_percentage; // in unit of 0.001% 1877 uint16_t gpuclk_ss_rate_10hz; 1878 uint32_t core_refclk_10khz; 1879 uint8_t ac_dc_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for AC/DC switching, =0xff means invalid 1880 uint8_t ac_dc_polarity; // GPIO polarity for AC/DC switching 1881 uint8_t vr0hot_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for VR0 HOT event, =0xff means invalid 1882 uint8_t vr0hot_polarity; // GPIO polarity for VR0 HOT event 1883 uint8_t vr1hot_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for VR1 HOT event , =0xff means invalid 1884 uint8_t vr1hot_polarity; // GPIO polarity for VR1 HOT event 1885 uint8_t fw_ctf_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for CTF, =0xff means invalid 1886 uint8_t fw_ctf_polarity; // GPIO polarity for CTF 1887 }; 1888 1889 struct atom_smu_info_v3_2 { 1890 struct atom_common_table_header table_header; 1891 uint8_t smuip_min_ver; 1892 uint8_t smuip_max_ver; 1893 uint8_t smu_rsd1; 1894 uint8_t gpuclk_ss_mode; 1895 uint16_t sclk_ss_percentage; 1896 uint16_t sclk_ss_rate_10hz; 1897 uint16_t gpuclk_ss_percentage; // in unit of 0.001% 1898 uint16_t gpuclk_ss_rate_10hz; 1899 uint32_t core_refclk_10khz; 1900 uint8_t ac_dc_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for AC/DC switching, =0xff means invalid 1901 uint8_t ac_dc_polarity; // GPIO polarity for AC/DC switching 1902 uint8_t vr0hot_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for VR0 HOT event, =0xff means invalid 1903 uint8_t vr0hot_polarity; // GPIO polarity for VR0 HOT event 1904 uint8_t vr1hot_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for VR1 HOT event , =0xff means invalid 1905 uint8_t vr1hot_polarity; // GPIO polarity for VR1 HOT event 1906 uint8_t fw_ctf_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for CTF, =0xff means invalid 1907 uint8_t fw_ctf_polarity; // GPIO polarity for CTF 1908 uint8_t pcc_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for PCC, =0xff means invalid 1909 uint8_t pcc_gpio_polarity; // GPIO polarity for CTF 1910 uint16_t smugoldenoffset; 1911 uint32_t gpupll_vco_freq_10khz; 1912 uint32_t bootup_smnclk_10khz; 1913 uint32_t bootup_socclk_10khz; 1914 uint32_t bootup_mp0clk_10khz; 1915 uint32_t bootup_mp1clk_10khz; 1916 uint32_t bootup_lclk_10khz; 1917 uint32_t bootup_dcefclk_10khz; 1918 uint32_t ctf_threshold_override_value; 1919 uint32_t reserved[5]; 1920 }; 1921 1922 struct atom_smu_info_v3_3 { 1923 struct atom_common_table_header table_header; 1924 uint8_t smuip_min_ver; 1925 uint8_t smuip_max_ver; 1926 uint8_t waflclk_ss_mode; 1927 uint8_t gpuclk_ss_mode; 1928 uint16_t sclk_ss_percentage; 1929 uint16_t sclk_ss_rate_10hz; 1930 uint16_t gpuclk_ss_percentage; // in unit of 0.001% 1931 uint16_t gpuclk_ss_rate_10hz; 1932 uint32_t core_refclk_10khz; 1933 uint8_t ac_dc_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for AC/DC switching, =0xff means invalid 1934 uint8_t ac_dc_polarity; // GPIO polarity for AC/DC switching 1935 uint8_t vr0hot_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for VR0 HOT event, =0xff means invalid 1936 uint8_t vr0hot_polarity; // GPIO polarity for VR0 HOT event 1937 uint8_t vr1hot_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for VR1 HOT event , =0xff means invalid 1938 uint8_t vr1hot_polarity; // GPIO polarity for VR1 HOT event 1939 uint8_t fw_ctf_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for CTF, =0xff means invalid 1940 uint8_t fw_ctf_polarity; // GPIO polarity for CTF 1941 uint8_t pcc_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for PCC, =0xff means invalid 1942 uint8_t pcc_gpio_polarity; // GPIO polarity for CTF 1943 uint16_t smugoldenoffset; 1944 uint32_t gpupll_vco_freq_10khz; 1945 uint32_t bootup_smnclk_10khz; 1946 uint32_t bootup_socclk_10khz; 1947 uint32_t bootup_mp0clk_10khz; 1948 uint32_t bootup_mp1clk_10khz; 1949 uint32_t bootup_lclk_10khz; 1950 uint32_t bootup_dcefclk_10khz; 1951 uint32_t ctf_threshold_override_value; 1952 uint32_t syspll3_0_vco_freq_10khz; 1953 uint32_t syspll3_1_vco_freq_10khz; 1954 uint32_t bootup_fclk_10khz; 1955 uint32_t bootup_waflclk_10khz; 1956 uint32_t smu_info_caps; 1957 uint16_t waflclk_ss_percentage; // in unit of 0.001% 1958 uint16_t smuinitoffset; 1959 uint32_t reserved; 1960 }; 1961 1962 struct atom_smu_info_v3_5 1963 { 1964 struct atom_common_table_header table_header; 1965 uint8_t smuip_min_ver; 1966 uint8_t smuip_max_ver; 1967 uint8_t waflclk_ss_mode; 1968 uint8_t gpuclk_ss_mode; 1969 uint16_t sclk_ss_percentage; 1970 uint16_t sclk_ss_rate_10hz; 1971 uint16_t gpuclk_ss_percentage; // in unit of 0.001% 1972 uint16_t gpuclk_ss_rate_10hz; 1973 uint32_t core_refclk_10khz; 1974 uint32_t syspll0_1_vco_freq_10khz; 1975 uint32_t syspll0_2_vco_freq_10khz; 1976 uint8_t pcc_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for PCC, =0xff means invalid 1977 uint8_t pcc_gpio_polarity; // GPIO polarity for CTF 1978 uint16_t smugoldenoffset; 1979 uint32_t syspll0_0_vco_freq_10khz; 1980 uint32_t bootup_smnclk_10khz; 1981 uint32_t bootup_socclk_10khz; 1982 uint32_t bootup_mp0clk_10khz; 1983 uint32_t bootup_mp1clk_10khz; 1984 uint32_t bootup_lclk_10khz; 1985 uint32_t bootup_dcefclk_10khz; 1986 uint32_t ctf_threshold_override_value; 1987 uint32_t syspll3_0_vco_freq_10khz; 1988 uint32_t syspll3_1_vco_freq_10khz; 1989 uint32_t bootup_fclk_10khz; 1990 uint32_t bootup_waflclk_10khz; 1991 uint32_t smu_info_caps; 1992 uint16_t waflclk_ss_percentage; // in unit of 0.001% 1993 uint16_t smuinitoffset; 1994 uint32_t bootup_dprefclk_10khz; 1995 uint32_t bootup_usbclk_10khz; 1996 uint32_t smb_slave_address; 1997 uint32_t cg_fdo_ctrl0_val; 1998 uint32_t cg_fdo_ctrl1_val; 1999 uint32_t cg_fdo_ctrl2_val; 2000 uint32_t gdfll_as_wait_ctrl_val; 2001 uint32_t gdfll_as_step_ctrl_val; 2002 uint32_t bootup_dtbclk_10khz; 2003 uint32_t fclk_syspll_refclk_10khz; 2004 uint32_t smusvi_svc0_val; 2005 uint32_t smusvi_svc1_val; 2006 uint32_t smusvi_svd0_val; 2007 uint32_t smusvi_svd1_val; 2008 uint32_t smusvi_svt0_val; 2009 uint32_t smusvi_svt1_val; 2010 uint32_t cg_tach_ctrl_val; 2011 uint32_t cg_pump_ctrl1_val; 2012 uint32_t cg_pump_tach_ctrl_val; 2013 uint32_t thm_ctf_delay_val; 2014 uint32_t thm_thermal_int_ctrl_val; 2015 uint32_t thm_tmon_config_val; 2016 uint32_t reserved[16]; 2017 }; 2018 2019 struct atom_smu_info_v3_6 2020 { 2021 struct atom_common_table_header table_header; 2022 uint8_t smuip_min_ver; 2023 uint8_t smuip_max_ver; 2024 uint8_t waflclk_ss_mode; 2025 uint8_t gpuclk_ss_mode; 2026 uint16_t sclk_ss_percentage; 2027 uint16_t sclk_ss_rate_10hz; 2028 uint16_t gpuclk_ss_percentage; 2029 uint16_t gpuclk_ss_rate_10hz; 2030 uint32_t core_refclk_10khz; 2031 uint32_t syspll0_1_vco_freq_10khz; 2032 uint32_t syspll0_2_vco_freq_10khz; 2033 uint8_t pcc_gpio_bit; 2034 uint8_t pcc_gpio_polarity; 2035 uint16_t smugoldenoffset; 2036 uint32_t syspll0_0_vco_freq_10khz; 2037 uint32_t bootup_smnclk_10khz; 2038 uint32_t bootup_socclk_10khz; 2039 uint32_t bootup_mp0clk_10khz; 2040 uint32_t bootup_mp1clk_10khz; 2041 uint32_t bootup_lclk_10khz; 2042 uint32_t bootup_dxioclk_10khz; 2043 uint32_t ctf_threshold_override_value; 2044 uint32_t syspll3_0_vco_freq_10khz; 2045 uint32_t syspll3_1_vco_freq_10khz; 2046 uint32_t bootup_fclk_10khz; 2047 uint32_t bootup_waflclk_10khz; 2048 uint32_t smu_info_caps; 2049 uint16_t waflclk_ss_percentage; 2050 uint16_t smuinitoffset; 2051 uint32_t bootup_gfxavsclk_10khz; 2052 uint32_t bootup_mpioclk_10khz; 2053 uint32_t smb_slave_address; 2054 uint32_t cg_fdo_ctrl0_val; 2055 uint32_t cg_fdo_ctrl1_val; 2056 uint32_t cg_fdo_ctrl2_val; 2057 uint32_t gdfll_as_wait_ctrl_val; 2058 uint32_t gdfll_as_step_ctrl_val; 2059 uint32_t reserved_clk; 2060 uint32_t fclk_syspll_refclk_10khz; 2061 uint32_t smusvi_svc0_val; 2062 uint32_t smusvi_svc1_val; 2063 uint32_t smusvi_svd0_val; 2064 uint32_t smusvi_svd1_val; 2065 uint32_t smusvi_svt0_val; 2066 uint32_t smusvi_svt1_val; 2067 uint32_t cg_tach_ctrl_val; 2068 uint32_t cg_pump_ctrl1_val; 2069 uint32_t cg_pump_tach_ctrl_val; 2070 uint32_t thm_ctf_delay_val; 2071 uint32_t thm_thermal_int_ctrl_val; 2072 uint32_t thm_tmon_config_val; 2073 uint32_t bootup_vclk_10khz; 2074 uint32_t bootup_dclk_10khz; 2075 uint32_t smu_gpiopad_pu_en_val; 2076 uint32_t smu_gpiopad_pd_en_val; 2077 uint32_t reserved[12]; 2078 }; 2079 2080 struct atom_smu_info_v4_0 { 2081 struct atom_common_table_header table_header; 2082 uint32_t bootup_gfxclk_bypass_10khz; 2083 uint32_t bootup_usrclk_10khz; 2084 uint32_t bootup_csrclk_10khz; 2085 uint32_t core_refclk_10khz; 2086 uint32_t syspll1_vco_freq_10khz; 2087 uint32_t syspll2_vco_freq_10khz; 2088 uint8_t pcc_gpio_bit; 2089 uint8_t pcc_gpio_polarity; 2090 uint16_t bootup_vddusr_mv; 2091 uint32_t syspll0_vco_freq_10khz; 2092 uint32_t bootup_smnclk_10khz; 2093 uint32_t bootup_socclk_10khz; 2094 uint32_t bootup_mp0clk_10khz; 2095 uint32_t bootup_mp1clk_10khz; 2096 uint32_t bootup_lclk_10khz; 2097 uint32_t bootup_dcefclk_10khz; 2098 uint32_t ctf_threshold_override_value; 2099 uint32_t syspll3_vco_freq_10khz; 2100 uint32_t mm_syspll_vco_freq_10khz; 2101 uint32_t bootup_fclk_10khz; 2102 uint32_t bootup_waflclk_10khz; 2103 uint32_t smu_info_caps; 2104 uint16_t waflclk_ss_percentage; 2105 uint16_t smuinitoffset; 2106 uint32_t bootup_dprefclk_10khz; 2107 uint32_t bootup_usbclk_10khz; 2108 uint32_t smb_slave_address; 2109 uint32_t cg_fdo_ctrl0_val; 2110 uint32_t cg_fdo_ctrl1_val; 2111 uint32_t cg_fdo_ctrl2_val; 2112 uint32_t gdfll_as_wait_ctrl_val; 2113 uint32_t gdfll_as_step_ctrl_val; 2114 uint32_t bootup_dtbclk_10khz; 2115 uint32_t fclk_syspll_refclk_10khz; 2116 uint32_t smusvi_svc0_val; 2117 uint32_t smusvi_svc1_val; 2118 uint32_t smusvi_svd0_val; 2119 uint32_t smusvi_svd1_val; 2120 uint32_t smusvi_svt0_val; 2121 uint32_t smusvi_svt1_val; 2122 uint32_t cg_tach_ctrl_val; 2123 uint32_t cg_pump_ctrl1_val; 2124 uint32_t cg_pump_tach_ctrl_val; 2125 uint32_t thm_ctf_delay_val; 2126 uint32_t thm_thermal_int_ctrl_val; 2127 uint32_t thm_tmon_config_val; 2128 uint32_t smbus_timing_cntrl0_val; 2129 uint32_t smbus_timing_cntrl1_val; 2130 uint32_t smbus_timing_cntrl2_val; 2131 uint32_t pwr_disp_timer_global_control_val; 2132 uint32_t bootup_mpioclk_10khz; 2133 uint32_t bootup_dclk0_10khz; 2134 uint32_t bootup_vclk0_10khz; 2135 uint32_t bootup_dclk1_10khz; 2136 uint32_t bootup_vclk1_10khz; 2137 uint32_t bootup_baco400clk_10khz; 2138 uint32_t bootup_baco1200clk_bypass_10khz; 2139 uint32_t bootup_baco700clk_bypass_10khz; 2140 uint32_t reserved[16]; 2141 }; 2142 2143 /* 2144 *************************************************************************** 2145 Data Table smc_dpm_info structure 2146 *************************************************************************** 2147 */ 2148 struct atom_smc_dpm_info_v4_1 2149 { 2150 struct atom_common_table_header table_header; 2151 uint8_t liquid1_i2c_address; 2152 uint8_t liquid2_i2c_address; 2153 uint8_t vr_i2c_address; 2154 uint8_t plx_i2c_address; 2155 2156 uint8_t liquid_i2c_linescl; 2157 uint8_t liquid_i2c_linesda; 2158 uint8_t vr_i2c_linescl; 2159 uint8_t vr_i2c_linesda; 2160 2161 uint8_t plx_i2c_linescl; 2162 uint8_t plx_i2c_linesda; 2163 uint8_t vrsensorpresent; 2164 uint8_t liquidsensorpresent; 2165 2166 uint16_t maxvoltagestepgfx; 2167 uint16_t maxvoltagestepsoc; 2168 2169 uint8_t vddgfxvrmapping; 2170 uint8_t vddsocvrmapping; 2171 uint8_t vddmem0vrmapping; 2172 uint8_t vddmem1vrmapping; 2173 2174 uint8_t gfxulvphasesheddingmask; 2175 uint8_t soculvphasesheddingmask; 2176 uint8_t padding8_v[2]; 2177 2178 uint16_t gfxmaxcurrent; 2179 uint8_t gfxoffset; 2180 uint8_t padding_telemetrygfx; 2181 2182 uint16_t socmaxcurrent; 2183 uint8_t socoffset; 2184 uint8_t padding_telemetrysoc; 2185 2186 uint16_t mem0maxcurrent; 2187 uint8_t mem0offset; 2188 uint8_t padding_telemetrymem0; 2189 2190 uint16_t mem1maxcurrent; 2191 uint8_t mem1offset; 2192 uint8_t padding_telemetrymem1; 2193 2194 uint8_t acdcgpio; 2195 uint8_t acdcpolarity; 2196 uint8_t vr0hotgpio; 2197 uint8_t vr0hotpolarity; 2198 2199 uint8_t vr1hotgpio; 2200 uint8_t vr1hotpolarity; 2201 uint8_t padding1; 2202 uint8_t padding2; 2203 2204 uint8_t ledpin0; 2205 uint8_t ledpin1; 2206 uint8_t ledpin2; 2207 uint8_t padding8_4; 2208 2209 uint8_t pllgfxclkspreadenabled; 2210 uint8_t pllgfxclkspreadpercent; 2211 uint16_t pllgfxclkspreadfreq; 2212 2213 uint8_t uclkspreadenabled; 2214 uint8_t uclkspreadpercent; 2215 uint16_t uclkspreadfreq; 2216 2217 uint8_t socclkspreadenabled; 2218 uint8_t socclkspreadpercent; 2219 uint16_t socclkspreadfreq; 2220 2221 uint8_t acggfxclkspreadenabled; 2222 uint8_t acggfxclkspreadpercent; 2223 uint16_t acggfxclkspreadfreq; 2224 2225 uint8_t Vr2_I2C_address; 2226 uint8_t padding_vr2[3]; 2227 2228 uint32_t boardreserved[9]; 2229 }; 2230 2231 /* 2232 *************************************************************************** 2233 Data Table smc_dpm_info structure 2234 *************************************************************************** 2235 */ 2236 struct atom_smc_dpm_info_v4_3 2237 { 2238 struct atom_common_table_header table_header; 2239 uint8_t liquid1_i2c_address; 2240 uint8_t liquid2_i2c_address; 2241 uint8_t vr_i2c_address; 2242 uint8_t plx_i2c_address; 2243 2244 uint8_t liquid_i2c_linescl; 2245 uint8_t liquid_i2c_linesda; 2246 uint8_t vr_i2c_linescl; 2247 uint8_t vr_i2c_linesda; 2248 2249 uint8_t plx_i2c_linescl; 2250 uint8_t plx_i2c_linesda; 2251 uint8_t vrsensorpresent; 2252 uint8_t liquidsensorpresent; 2253 2254 uint16_t maxvoltagestepgfx; 2255 uint16_t maxvoltagestepsoc; 2256 2257 uint8_t vddgfxvrmapping; 2258 uint8_t vddsocvrmapping; 2259 uint8_t vddmem0vrmapping; 2260 uint8_t vddmem1vrmapping; 2261 2262 uint8_t gfxulvphasesheddingmask; 2263 uint8_t soculvphasesheddingmask; 2264 uint8_t externalsensorpresent; 2265 uint8_t padding8_v; 2266 2267 uint16_t gfxmaxcurrent; 2268 uint8_t gfxoffset; 2269 uint8_t padding_telemetrygfx; 2270 2271 uint16_t socmaxcurrent; 2272 uint8_t socoffset; 2273 uint8_t padding_telemetrysoc; 2274 2275 uint16_t mem0maxcurrent; 2276 uint8_t mem0offset; 2277 uint8_t padding_telemetrymem0; 2278 2279 uint16_t mem1maxcurrent; 2280 uint8_t mem1offset; 2281 uint8_t padding_telemetrymem1; 2282 2283 uint8_t acdcgpio; 2284 uint8_t acdcpolarity; 2285 uint8_t vr0hotgpio; 2286 uint8_t vr0hotpolarity; 2287 2288 uint8_t vr1hotgpio; 2289 uint8_t vr1hotpolarity; 2290 uint8_t padding1; 2291 uint8_t padding2; 2292 2293 uint8_t ledpin0; 2294 uint8_t ledpin1; 2295 uint8_t ledpin2; 2296 uint8_t padding8_4; 2297 2298 uint8_t pllgfxclkspreadenabled; 2299 uint8_t pllgfxclkspreadpercent; 2300 uint16_t pllgfxclkspreadfreq; 2301 2302 uint8_t uclkspreadenabled; 2303 uint8_t uclkspreadpercent; 2304 uint16_t uclkspreadfreq; 2305 2306 uint8_t fclkspreadenabled; 2307 uint8_t fclkspreadpercent; 2308 uint16_t fclkspreadfreq; 2309 2310 uint8_t fllgfxclkspreadenabled; 2311 uint8_t fllgfxclkspreadpercent; 2312 uint16_t fllgfxclkspreadfreq; 2313 2314 uint32_t boardreserved[10]; 2315 }; 2316 2317 struct smudpm_i2ccontrollerconfig_t { 2318 uint32_t enabled; 2319 uint32_t slaveaddress; 2320 uint32_t controllerport; 2321 uint32_t controllername; 2322 uint32_t thermalthrottler; 2323 uint32_t i2cprotocol; 2324 uint32_t i2cspeed; 2325 }; 2326 2327 struct atom_smc_dpm_info_v4_4 2328 { 2329 struct atom_common_table_header table_header; 2330 uint32_t i2c_padding[3]; 2331 2332 uint16_t maxvoltagestepgfx; 2333 uint16_t maxvoltagestepsoc; 2334 2335 uint8_t vddgfxvrmapping; 2336 uint8_t vddsocvrmapping; 2337 uint8_t vddmem0vrmapping; 2338 uint8_t vddmem1vrmapping; 2339 2340 uint8_t gfxulvphasesheddingmask; 2341 uint8_t soculvphasesheddingmask; 2342 uint8_t externalsensorpresent; 2343 uint8_t padding8_v; 2344 2345 uint16_t gfxmaxcurrent; 2346 uint8_t gfxoffset; 2347 uint8_t padding_telemetrygfx; 2348 2349 uint16_t socmaxcurrent; 2350 uint8_t socoffset; 2351 uint8_t padding_telemetrysoc; 2352 2353 uint16_t mem0maxcurrent; 2354 uint8_t mem0offset; 2355 uint8_t padding_telemetrymem0; 2356 2357 uint16_t mem1maxcurrent; 2358 uint8_t mem1offset; 2359 uint8_t padding_telemetrymem1; 2360 2361 2362 uint8_t acdcgpio; 2363 uint8_t acdcpolarity; 2364 uint8_t vr0hotgpio; 2365 uint8_t vr0hotpolarity; 2366 2367 uint8_t vr1hotgpio; 2368 uint8_t vr1hotpolarity; 2369 uint8_t padding1; 2370 uint8_t padding2; 2371 2372 2373 uint8_t ledpin0; 2374 uint8_t ledpin1; 2375 uint8_t ledpin2; 2376 uint8_t padding8_4; 2377 2378 2379 uint8_t pllgfxclkspreadenabled; 2380 uint8_t pllgfxclkspreadpercent; 2381 uint16_t pllgfxclkspreadfreq; 2382 2383 2384 uint8_t uclkspreadenabled; 2385 uint8_t uclkspreadpercent; 2386 uint16_t uclkspreadfreq; 2387 2388 2389 uint8_t fclkspreadenabled; 2390 uint8_t fclkspreadpercent; 2391 uint16_t fclkspreadfreq; 2392 2393 2394 uint8_t fllgfxclkspreadenabled; 2395 uint8_t fllgfxclkspreadpercent; 2396 uint16_t fllgfxclkspreadfreq; 2397 2398 2399 struct smudpm_i2ccontrollerconfig_t i2ccontrollers[7]; 2400 2401 2402 uint32_t boardreserved[10]; 2403 }; 2404 2405 enum smudpm_v4_5_i2ccontrollername_e{ 2406 SMC_V4_5_I2C_CONTROLLER_NAME_VR_GFX = 0, 2407 SMC_V4_5_I2C_CONTROLLER_NAME_VR_SOC, 2408 SMC_V4_5_I2C_CONTROLLER_NAME_VR_VDDCI, 2409 SMC_V4_5_I2C_CONTROLLER_NAME_VR_MVDD, 2410 SMC_V4_5_I2C_CONTROLLER_NAME_LIQUID0, 2411 SMC_V4_5_I2C_CONTROLLER_NAME_LIQUID1, 2412 SMC_V4_5_I2C_CONTROLLER_NAME_PLX, 2413 SMC_V4_5_I2C_CONTROLLER_NAME_SPARE, 2414 SMC_V4_5_I2C_CONTROLLER_NAME_COUNT, 2415 }; 2416 2417 enum smudpm_v4_5_i2ccontrollerthrottler_e{ 2418 SMC_V4_5_I2C_CONTROLLER_THROTTLER_TYPE_NONE = 0, 2419 SMC_V4_5_I2C_CONTROLLER_THROTTLER_VR_GFX, 2420 SMC_V4_5_I2C_CONTROLLER_THROTTLER_VR_SOC, 2421 SMC_V4_5_I2C_CONTROLLER_THROTTLER_VR_VDDCI, 2422 SMC_V4_5_I2C_CONTROLLER_THROTTLER_VR_MVDD, 2423 SMC_V4_5_I2C_CONTROLLER_THROTTLER_LIQUID0, 2424 SMC_V4_5_I2C_CONTROLLER_THROTTLER_LIQUID1, 2425 SMC_V4_5_I2C_CONTROLLER_THROTTLER_PLX, 2426 SMC_V4_5_I2C_CONTROLLER_THROTTLER_COUNT, 2427 }; 2428 2429 enum smudpm_v4_5_i2ccontrollerprotocol_e{ 2430 SMC_V4_5_I2C_CONTROLLER_PROTOCOL_VR_0, 2431 SMC_V4_5_I2C_CONTROLLER_PROTOCOL_VR_1, 2432 SMC_V4_5_I2C_CONTROLLER_PROTOCOL_TMP_0, 2433 SMC_V4_5_I2C_CONTROLLER_PROTOCOL_TMP_1, 2434 SMC_V4_5_I2C_CONTROLLER_PROTOCOL_SPARE_0, 2435 SMC_V4_5_I2C_CONTROLLER_PROTOCOL_SPARE_1, 2436 SMC_V4_5_I2C_CONTROLLER_PROTOCOL_COUNT, 2437 }; 2438 2439 struct smudpm_i2c_controller_config_v2 2440 { 2441 uint8_t Enabled; 2442 uint8_t Speed; 2443 uint8_t Padding[2]; 2444 uint32_t SlaveAddress; 2445 uint8_t ControllerPort; 2446 uint8_t ControllerName; 2447 uint8_t ThermalThrotter; 2448 uint8_t I2cProtocol; 2449 }; 2450 2451 struct atom_smc_dpm_info_v4_5 2452 { 2453 struct atom_common_table_header table_header; 2454 // SECTION: BOARD PARAMETERS 2455 // I2C Control 2456 struct smudpm_i2c_controller_config_v2 I2cControllers[8]; 2457 2458 // SVI2 Board Parameters 2459 uint16_t MaxVoltageStepGfx; // In mV(Q2) Max voltage step that SMU will request. Multiple steps are taken if voltage change exceeds this value. 2460 uint16_t MaxVoltageStepSoc; // In mV(Q2) Max voltage step that SMU will request. Multiple steps are taken if voltage change exceeds this value. 2461 2462 uint8_t VddGfxVrMapping; // Use VR_MAPPING* bitfields 2463 uint8_t VddSocVrMapping; // Use VR_MAPPING* bitfields 2464 uint8_t VddMem0VrMapping; // Use VR_MAPPING* bitfields 2465 uint8_t VddMem1VrMapping; // Use VR_MAPPING* bitfields 2466 2467 uint8_t GfxUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode 2468 uint8_t SocUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode 2469 uint8_t ExternalSensorPresent; // External RDI connected to TMON (aka TEMP IN) 2470 uint8_t Padding8_V; 2471 2472 // Telemetry Settings 2473 uint16_t GfxMaxCurrent; // in Amps 2474 uint8_t GfxOffset; // in Amps 2475 uint8_t Padding_TelemetryGfx; 2476 uint16_t SocMaxCurrent; // in Amps 2477 uint8_t SocOffset; // in Amps 2478 uint8_t Padding_TelemetrySoc; 2479 2480 uint16_t Mem0MaxCurrent; // in Amps 2481 uint8_t Mem0Offset; // in Amps 2482 uint8_t Padding_TelemetryMem0; 2483 2484 uint16_t Mem1MaxCurrent; // in Amps 2485 uint8_t Mem1Offset; // in Amps 2486 uint8_t Padding_TelemetryMem1; 2487 2488 // GPIO Settings 2489 uint8_t AcDcGpio; // GPIO pin configured for AC/DC switching 2490 uint8_t AcDcPolarity; // GPIO polarity for AC/DC switching 2491 uint8_t VR0HotGpio; // GPIO pin configured for VR0 HOT event 2492 uint8_t VR0HotPolarity; // GPIO polarity for VR0 HOT event 2493 2494 uint8_t VR1HotGpio; // GPIO pin configured for VR1 HOT event 2495 uint8_t VR1HotPolarity; // GPIO polarity for VR1 HOT event 2496 uint8_t GthrGpio; // GPIO pin configured for GTHR Event 2497 uint8_t GthrPolarity; // replace GPIO polarity for GTHR 2498 2499 // LED Display Settings 2500 uint8_t LedPin0; // GPIO number for LedPin[0] 2501 uint8_t LedPin1; // GPIO number for LedPin[1] 2502 uint8_t LedPin2; // GPIO number for LedPin[2] 2503 uint8_t padding8_4; 2504 2505 // GFXCLK PLL Spread Spectrum 2506 uint8_t PllGfxclkSpreadEnabled; // on or off 2507 uint8_t PllGfxclkSpreadPercent; // Q4.4 2508 uint16_t PllGfxclkSpreadFreq; // kHz 2509 2510 // GFXCLK DFLL Spread Spectrum 2511 uint8_t DfllGfxclkSpreadEnabled; // on or off 2512 uint8_t DfllGfxclkSpreadPercent; // Q4.4 2513 uint16_t DfllGfxclkSpreadFreq; // kHz 2514 2515 // UCLK Spread Spectrum 2516 uint8_t UclkSpreadEnabled; // on or off 2517 uint8_t UclkSpreadPercent; // Q4.4 2518 uint16_t UclkSpreadFreq; // kHz 2519 2520 // SOCCLK Spread Spectrum 2521 uint8_t SoclkSpreadEnabled; // on or off 2522 uint8_t SocclkSpreadPercent; // Q4.4 2523 uint16_t SocclkSpreadFreq; // kHz 2524 2525 // Total board power 2526 uint16_t TotalBoardPower; //Only needed for TCP Estimated case, where TCP = TGP+Total Board Power 2527 uint16_t BoardPadding; 2528 2529 // Mvdd Svi2 Div Ratio Setting 2530 uint32_t MvddRatio; // This is used for MVDD Vid workaround. It has 16 fractional bits (Q16.16) 2531 2532 uint32_t BoardReserved[9]; 2533 2534 }; 2535 2536 struct atom_smc_dpm_info_v4_6 2537 { 2538 struct atom_common_table_header table_header; 2539 // section: board parameters 2540 uint32_t i2c_padding[3]; // old i2c control are moved to new area 2541 2542 uint16_t maxvoltagestepgfx; // in mv(q2) max voltage step that smu will request. multiple steps are taken if voltage change exceeds this value. 2543 uint16_t maxvoltagestepsoc; // in mv(q2) max voltage step that smu will request. multiple steps are taken if voltage change exceeds this value. 2544 2545 uint8_t vddgfxvrmapping; // use vr_mapping* bitfields 2546 uint8_t vddsocvrmapping; // use vr_mapping* bitfields 2547 uint8_t vddmemvrmapping; // use vr_mapping* bitfields 2548 uint8_t boardvrmapping; // use vr_mapping* bitfields 2549 2550 uint8_t gfxulvphasesheddingmask; // set this to 1 to set psi0/1 to 1 in ulv mode 2551 uint8_t externalsensorpresent; // external rdi connected to tmon (aka temp in) 2552 uint8_t padding8_v[2]; 2553 2554 // telemetry settings 2555 uint16_t gfxmaxcurrent; // in amps 2556 uint8_t gfxoffset; // in amps 2557 uint8_t padding_telemetrygfx; 2558 2559 uint16_t socmaxcurrent; // in amps 2560 uint8_t socoffset; // in amps 2561 uint8_t padding_telemetrysoc; 2562 2563 uint16_t memmaxcurrent; // in amps 2564 uint8_t memoffset; // in amps 2565 uint8_t padding_telemetrymem; 2566 2567 uint16_t boardmaxcurrent; // in amps 2568 uint8_t boardoffset; // in amps 2569 uint8_t padding_telemetryboardinput; 2570 2571 // gpio settings 2572 uint8_t vr0hotgpio; // gpio pin configured for vr0 hot event 2573 uint8_t vr0hotpolarity; // gpio polarity for vr0 hot event 2574 uint8_t vr1hotgpio; // gpio pin configured for vr1 hot event 2575 uint8_t vr1hotpolarity; // gpio polarity for vr1 hot event 2576 2577 // gfxclk pll spread spectrum 2578 uint8_t pllgfxclkspreadenabled; // on or off 2579 uint8_t pllgfxclkspreadpercent; // q4.4 2580 uint16_t pllgfxclkspreadfreq; // khz 2581 2582 // uclk spread spectrum 2583 uint8_t uclkspreadenabled; // on or off 2584 uint8_t uclkspreadpercent; // q4.4 2585 uint16_t uclkspreadfreq; // khz 2586 2587 // fclk spread spectrum 2588 uint8_t fclkspreadenabled; // on or off 2589 uint8_t fclkspreadpercent; // q4.4 2590 uint16_t fclkspreadfreq; // khz 2591 2592 2593 // gfxclk fll spread spectrum 2594 uint8_t fllgfxclkspreadenabled; // on or off 2595 uint8_t fllgfxclkspreadpercent; // q4.4 2596 uint16_t fllgfxclkspreadfreq; // khz 2597 2598 // i2c controller structure 2599 struct smudpm_i2c_controller_config_v2 i2ccontrollers[8]; 2600 2601 // memory section 2602 uint32_t memorychannelenabled; // for dram use only, max 32 channels enabled bit mask. 2603 2604 uint8_t drambitwidth; // for dram use only. see dram bit width type defines 2605 uint8_t paddingmem[3]; 2606 2607 // total board power 2608 uint16_t totalboardpower; //only needed for tcp estimated case, where tcp = tgp+total board power 2609 uint16_t boardpadding; 2610 2611 // section: xgmi training 2612 uint8_t xgmilinkspeed[4]; 2613 uint8_t xgmilinkwidth[4]; 2614 2615 uint16_t xgmifclkfreq[4]; 2616 uint16_t xgmisocvoltage[4]; 2617 2618 // reserved 2619 uint32_t boardreserved[10]; 2620 }; 2621 2622 struct atom_smc_dpm_info_v4_7 2623 { 2624 struct atom_common_table_header table_header; 2625 // SECTION: BOARD PARAMETERS 2626 // I2C Control 2627 struct smudpm_i2c_controller_config_v2 I2cControllers[8]; 2628 2629 // SVI2 Board Parameters 2630 uint16_t MaxVoltageStepGfx; // In mV(Q2) Max voltage step that SMU will request. Multiple steps are taken if voltage change exceeds this value. 2631 uint16_t MaxVoltageStepSoc; // In mV(Q2) Max voltage step that SMU will request. Multiple steps are taken if voltage change exceeds this value. 2632 2633 uint8_t VddGfxVrMapping; // Use VR_MAPPING* bitfields 2634 uint8_t VddSocVrMapping; // Use VR_MAPPING* bitfields 2635 uint8_t VddMem0VrMapping; // Use VR_MAPPING* bitfields 2636 uint8_t VddMem1VrMapping; // Use VR_MAPPING* bitfields 2637 2638 uint8_t GfxUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode 2639 uint8_t SocUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode 2640 uint8_t ExternalSensorPresent; // External RDI connected to TMON (aka TEMP IN) 2641 uint8_t Padding8_V; 2642 2643 // Telemetry Settings 2644 uint16_t GfxMaxCurrent; // in Amps 2645 uint8_t GfxOffset; // in Amps 2646 uint8_t Padding_TelemetryGfx; 2647 uint16_t SocMaxCurrent; // in Amps 2648 uint8_t SocOffset; // in Amps 2649 uint8_t Padding_TelemetrySoc; 2650 2651 uint16_t Mem0MaxCurrent; // in Amps 2652 uint8_t Mem0Offset; // in Amps 2653 uint8_t Padding_TelemetryMem0; 2654 2655 uint16_t Mem1MaxCurrent; // in Amps 2656 uint8_t Mem1Offset; // in Amps 2657 uint8_t Padding_TelemetryMem1; 2658 2659 // GPIO Settings 2660 uint8_t AcDcGpio; // GPIO pin configured for AC/DC switching 2661 uint8_t AcDcPolarity; // GPIO polarity for AC/DC switching 2662 uint8_t VR0HotGpio; // GPIO pin configured for VR0 HOT event 2663 uint8_t VR0HotPolarity; // GPIO polarity for VR0 HOT event 2664 2665 uint8_t VR1HotGpio; // GPIO pin configured for VR1 HOT event 2666 uint8_t VR1HotPolarity; // GPIO polarity for VR1 HOT event 2667 uint8_t GthrGpio; // GPIO pin configured for GTHR Event 2668 uint8_t GthrPolarity; // replace GPIO polarity for GTHR 2669 2670 // LED Display Settings 2671 uint8_t LedPin0; // GPIO number for LedPin[0] 2672 uint8_t LedPin1; // GPIO number for LedPin[1] 2673 uint8_t LedPin2; // GPIO number for LedPin[2] 2674 uint8_t padding8_4; 2675 2676 // GFXCLK PLL Spread Spectrum 2677 uint8_t PllGfxclkSpreadEnabled; // on or off 2678 uint8_t PllGfxclkSpreadPercent; // Q4.4 2679 uint16_t PllGfxclkSpreadFreq; // kHz 2680 2681 // GFXCLK DFLL Spread Spectrum 2682 uint8_t DfllGfxclkSpreadEnabled; // on or off 2683 uint8_t DfllGfxclkSpreadPercent; // Q4.4 2684 uint16_t DfllGfxclkSpreadFreq; // kHz 2685 2686 // UCLK Spread Spectrum 2687 uint8_t UclkSpreadEnabled; // on or off 2688 uint8_t UclkSpreadPercent; // Q4.4 2689 uint16_t UclkSpreadFreq; // kHz 2690 2691 // SOCCLK Spread Spectrum 2692 uint8_t SoclkSpreadEnabled; // on or off 2693 uint8_t SocclkSpreadPercent; // Q4.4 2694 uint16_t SocclkSpreadFreq; // kHz 2695 2696 // Total board power 2697 uint16_t TotalBoardPower; //Only needed for TCP Estimated case, where TCP = TGP+Total Board Power 2698 uint16_t BoardPadding; 2699 2700 // Mvdd Svi2 Div Ratio Setting 2701 uint32_t MvddRatio; // This is used for MVDD Vid workaround. It has 16 fractional bits (Q16.16) 2702 2703 // GPIO pins for I2C communications with 2nd controller for Input Telemetry Sequence 2704 uint8_t GpioI2cScl; // Serial Clock 2705 uint8_t GpioI2cSda; // Serial Data 2706 uint16_t GpioPadding; 2707 2708 // Additional LED Display Settings 2709 uint8_t LedPin3; // GPIO number for LedPin[3] - PCIE GEN Speed 2710 uint8_t LedPin4; // GPIO number for LedPin[4] - PMFW Error Status 2711 uint16_t LedEnableMask; 2712 2713 // Power Limit Scalars 2714 uint8_t PowerLimitScalar[4]; //[PPT_THROTTLER_COUNT] 2715 2716 uint8_t MvddUlvPhaseSheddingMask; 2717 uint8_t VddciUlvPhaseSheddingMask; 2718 uint8_t Padding8_Psi1; 2719 uint8_t Padding8_Psi2; 2720 2721 uint32_t BoardReserved[5]; 2722 }; 2723 2724 struct smudpm_i2c_controller_config_v3 2725 { 2726 uint8_t Enabled; 2727 uint8_t Speed; 2728 uint8_t SlaveAddress; 2729 uint8_t ControllerPort; 2730 uint8_t ControllerName; 2731 uint8_t ThermalThrotter; 2732 uint8_t I2cProtocol; 2733 uint8_t PaddingConfig; 2734 }; 2735 2736 struct atom_smc_dpm_info_v4_9 2737 { 2738 struct atom_common_table_header table_header; 2739 2740 //SECTION: Gaming Clocks 2741 //uint32_t GamingClk[6]; 2742 2743 // SECTION: I2C Control 2744 struct smudpm_i2c_controller_config_v3 I2cControllers[16]; 2745 2746 uint8_t GpioScl; // GPIO Number for SCL Line, used only for CKSVII2C1 2747 uint8_t GpioSda; // GPIO Number for SDA Line, used only for CKSVII2C1 2748 uint8_t FchUsbPdSlaveAddr; //For requesting USB PD controller S-states via FCH I2C when entering PME turn off 2749 uint8_t I2cSpare; 2750 2751 // SECTION: SVI2 Board Parameters 2752 uint8_t VddGfxVrMapping; // Use VR_MAPPING* bitfields 2753 uint8_t VddSocVrMapping; // Use VR_MAPPING* bitfields 2754 uint8_t VddMem0VrMapping; // Use VR_MAPPING* bitfields 2755 uint8_t VddMem1VrMapping; // Use VR_MAPPING* bitfields 2756 2757 uint8_t GfxUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode 2758 uint8_t SocUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode 2759 uint8_t VddciUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode 2760 uint8_t MvddUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode 2761 2762 // SECTION: Telemetry Settings 2763 uint16_t GfxMaxCurrent; // in Amps 2764 uint8_t GfxOffset; // in Amps 2765 uint8_t Padding_TelemetryGfx; 2766 2767 uint16_t SocMaxCurrent; // in Amps 2768 uint8_t SocOffset; // in Amps 2769 uint8_t Padding_TelemetrySoc; 2770 2771 uint16_t Mem0MaxCurrent; // in Amps 2772 uint8_t Mem0Offset; // in Amps 2773 uint8_t Padding_TelemetryMem0; 2774 2775 uint16_t Mem1MaxCurrent; // in Amps 2776 uint8_t Mem1Offset; // in Amps 2777 uint8_t Padding_TelemetryMem1; 2778 2779 uint32_t MvddRatio; // This is used for MVDD Svi2 Div Ratio workaround. It has 16 fractional bits (Q16.16) 2780 2781 // SECTION: GPIO Settings 2782 uint8_t AcDcGpio; // GPIO pin configured for AC/DC switching 2783 uint8_t AcDcPolarity; // GPIO polarity for AC/DC switching 2784 uint8_t VR0HotGpio; // GPIO pin configured for VR0 HOT event 2785 uint8_t VR0HotPolarity; // GPIO polarity for VR0 HOT event 2786 2787 uint8_t VR1HotGpio; // GPIO pin configured for VR1 HOT event 2788 uint8_t VR1HotPolarity; // GPIO polarity for VR1 HOT event 2789 uint8_t GthrGpio; // GPIO pin configured for GTHR Event 2790 uint8_t GthrPolarity; // replace GPIO polarity for GTHR 2791 2792 // LED Display Settings 2793 uint8_t LedPin0; // GPIO number for LedPin[0] 2794 uint8_t LedPin1; // GPIO number for LedPin[1] 2795 uint8_t LedPin2; // GPIO number for LedPin[2] 2796 uint8_t LedEnableMask; 2797 2798 uint8_t LedPcie; // GPIO number for PCIE results 2799 uint8_t LedError; // GPIO number for Error Cases 2800 uint8_t LedSpare1[2]; 2801 2802 // SECTION: Clock Spread Spectrum 2803 2804 // GFXCLK PLL Spread Spectrum 2805 uint8_t PllGfxclkSpreadEnabled; // on or off 2806 uint8_t PllGfxclkSpreadPercent; // Q4.4 2807 uint16_t PllGfxclkSpreadFreq; // kHz 2808 2809 // GFXCLK DFLL Spread Spectrum 2810 uint8_t DfllGfxclkSpreadEnabled; // on or off 2811 uint8_t DfllGfxclkSpreadPercent; // Q4.4 2812 uint16_t DfllGfxclkSpreadFreq; // kHz 2813 2814 // UCLK Spread Spectrum 2815 uint8_t UclkSpreadEnabled; // on or off 2816 uint8_t UclkSpreadPercent; // Q4.4 2817 uint16_t UclkSpreadFreq; // kHz 2818 2819 // FCLK Spread Spectrum 2820 uint8_t FclkSpreadEnabled; // on or off 2821 uint8_t FclkSpreadPercent; // Q4.4 2822 uint16_t FclkSpreadFreq; // kHz 2823 2824 // Section: Memory Config 2825 uint32_t MemoryChannelEnabled; // For DRAM use only, Max 32 channels enabled bit mask. 2826 2827 uint8_t DramBitWidth; // For DRAM use only. See Dram Bit width type defines 2828 uint8_t PaddingMem1[3]; 2829 2830 // Section: Total Board Power 2831 uint16_t TotalBoardPower; //Only needed for TCP Estimated case, where TCP = TGP+Total Board Power 2832 uint16_t BoardPowerPadding; 2833 2834 // SECTION: XGMI Training 2835 uint8_t XgmiLinkSpeed [4]; 2836 uint8_t XgmiLinkWidth [4]; 2837 2838 uint16_t XgmiFclkFreq [4]; 2839 uint16_t XgmiSocVoltage [4]; 2840 2841 // SECTION: Board Reserved 2842 2843 uint32_t BoardReserved[16]; 2844 2845 }; 2846 2847 struct atom_smc_dpm_info_v4_10 2848 { 2849 struct atom_common_table_header table_header; 2850 2851 // SECTION: BOARD PARAMETERS 2852 // Telemetry Settings 2853 uint16_t GfxMaxCurrent; // in Amps 2854 uint8_t GfxOffset; // in Amps 2855 uint8_t Padding_TelemetryGfx; 2856 2857 uint16_t SocMaxCurrent; // in Amps 2858 uint8_t SocOffset; // in Amps 2859 uint8_t Padding_TelemetrySoc; 2860 2861 uint16_t MemMaxCurrent; // in Amps 2862 uint8_t MemOffset; // in Amps 2863 uint8_t Padding_TelemetryMem; 2864 2865 uint16_t BoardMaxCurrent; // in Amps 2866 uint8_t BoardOffset; // in Amps 2867 uint8_t Padding_TelemetryBoardInput; 2868 2869 // Platform input telemetry voltage coefficient 2870 uint32_t BoardVoltageCoeffA; // decode by /1000 2871 uint32_t BoardVoltageCoeffB; // decode by /1000 2872 2873 // GPIO Settings 2874 uint8_t VR0HotGpio; // GPIO pin configured for VR0 HOT event 2875 uint8_t VR0HotPolarity; // GPIO polarity for VR0 HOT event 2876 uint8_t VR1HotGpio; // GPIO pin configured for VR1 HOT event 2877 uint8_t VR1HotPolarity; // GPIO polarity for VR1 HOT event 2878 2879 // UCLK Spread Spectrum 2880 uint8_t UclkSpreadEnabled; // on or off 2881 uint8_t UclkSpreadPercent; // Q4.4 2882 uint16_t UclkSpreadFreq; // kHz 2883 2884 // FCLK Spread Spectrum 2885 uint8_t FclkSpreadEnabled; // on or off 2886 uint8_t FclkSpreadPercent; // Q4.4 2887 uint16_t FclkSpreadFreq; // kHz 2888 2889 // I2C Controller Structure 2890 struct smudpm_i2c_controller_config_v3 I2cControllers[8]; 2891 2892 // GPIO pins for I2C communications with 2nd controller for Input Telemetry Sequence 2893 uint8_t GpioI2cScl; // Serial Clock 2894 uint8_t GpioI2cSda; // Serial Data 2895 uint16_t spare5; 2896 2897 uint32_t reserved[16]; 2898 }; 2899 2900 /* 2901 *************************************************************************** 2902 Data Table asic_profiling_info structure 2903 *************************************************************************** 2904 */ 2905 struct atom_asic_profiling_info_v4_1 2906 { 2907 struct atom_common_table_header table_header; 2908 uint32_t maxvddc; 2909 uint32_t minvddc; 2910 uint32_t avfs_meannsigma_acontant0; 2911 uint32_t avfs_meannsigma_acontant1; 2912 uint32_t avfs_meannsigma_acontant2; 2913 uint16_t avfs_meannsigma_dc_tol_sigma; 2914 uint16_t avfs_meannsigma_platform_mean; 2915 uint16_t avfs_meannsigma_platform_sigma; 2916 uint32_t gb_vdroop_table_cksoff_a0; 2917 uint32_t gb_vdroop_table_cksoff_a1; 2918 uint32_t gb_vdroop_table_cksoff_a2; 2919 uint32_t gb_vdroop_table_ckson_a0; 2920 uint32_t gb_vdroop_table_ckson_a1; 2921 uint32_t gb_vdroop_table_ckson_a2; 2922 uint32_t avfsgb_fuse_table_cksoff_m1; 2923 uint32_t avfsgb_fuse_table_cksoff_m2; 2924 uint32_t avfsgb_fuse_table_cksoff_b; 2925 uint32_t avfsgb_fuse_table_ckson_m1; 2926 uint32_t avfsgb_fuse_table_ckson_m2; 2927 uint32_t avfsgb_fuse_table_ckson_b; 2928 uint16_t max_voltage_0_25mv; 2929 uint8_t enable_gb_vdroop_table_cksoff; 2930 uint8_t enable_gb_vdroop_table_ckson; 2931 uint8_t enable_gb_fuse_table_cksoff; 2932 uint8_t enable_gb_fuse_table_ckson; 2933 uint16_t psm_age_comfactor; 2934 uint8_t enable_apply_avfs_cksoff_voltage; 2935 uint8_t reserved; 2936 uint32_t dispclk2gfxclk_a; 2937 uint32_t dispclk2gfxclk_b; 2938 uint32_t dispclk2gfxclk_c; 2939 uint32_t pixclk2gfxclk_a; 2940 uint32_t pixclk2gfxclk_b; 2941 uint32_t pixclk2gfxclk_c; 2942 uint32_t dcefclk2gfxclk_a; 2943 uint32_t dcefclk2gfxclk_b; 2944 uint32_t dcefclk2gfxclk_c; 2945 uint32_t phyclk2gfxclk_a; 2946 uint32_t phyclk2gfxclk_b; 2947 uint32_t phyclk2gfxclk_c; 2948 }; 2949 2950 struct atom_asic_profiling_info_v4_2 { 2951 struct atom_common_table_header table_header; 2952 uint32_t maxvddc; 2953 uint32_t minvddc; 2954 uint32_t avfs_meannsigma_acontant0; 2955 uint32_t avfs_meannsigma_acontant1; 2956 uint32_t avfs_meannsigma_acontant2; 2957 uint16_t avfs_meannsigma_dc_tol_sigma; 2958 uint16_t avfs_meannsigma_platform_mean; 2959 uint16_t avfs_meannsigma_platform_sigma; 2960 uint32_t gb_vdroop_table_cksoff_a0; 2961 uint32_t gb_vdroop_table_cksoff_a1; 2962 uint32_t gb_vdroop_table_cksoff_a2; 2963 uint32_t gb_vdroop_table_ckson_a0; 2964 uint32_t gb_vdroop_table_ckson_a1; 2965 uint32_t gb_vdroop_table_ckson_a2; 2966 uint32_t avfsgb_fuse_table_cksoff_m1; 2967 uint32_t avfsgb_fuse_table_cksoff_m2; 2968 uint32_t avfsgb_fuse_table_cksoff_b; 2969 uint32_t avfsgb_fuse_table_ckson_m1; 2970 uint32_t avfsgb_fuse_table_ckson_m2; 2971 uint32_t avfsgb_fuse_table_ckson_b; 2972 uint16_t max_voltage_0_25mv; 2973 uint8_t enable_gb_vdroop_table_cksoff; 2974 uint8_t enable_gb_vdroop_table_ckson; 2975 uint8_t enable_gb_fuse_table_cksoff; 2976 uint8_t enable_gb_fuse_table_ckson; 2977 uint16_t psm_age_comfactor; 2978 uint8_t enable_apply_avfs_cksoff_voltage; 2979 uint8_t reserved; 2980 uint32_t dispclk2gfxclk_a; 2981 uint32_t dispclk2gfxclk_b; 2982 uint32_t dispclk2gfxclk_c; 2983 uint32_t pixclk2gfxclk_a; 2984 uint32_t pixclk2gfxclk_b; 2985 uint32_t pixclk2gfxclk_c; 2986 uint32_t dcefclk2gfxclk_a; 2987 uint32_t dcefclk2gfxclk_b; 2988 uint32_t dcefclk2gfxclk_c; 2989 uint32_t phyclk2gfxclk_a; 2990 uint32_t phyclk2gfxclk_b; 2991 uint32_t phyclk2gfxclk_c; 2992 uint32_t acg_gb_vdroop_table_a0; 2993 uint32_t acg_gb_vdroop_table_a1; 2994 uint32_t acg_gb_vdroop_table_a2; 2995 uint32_t acg_avfsgb_fuse_table_m1; 2996 uint32_t acg_avfsgb_fuse_table_m2; 2997 uint32_t acg_avfsgb_fuse_table_b; 2998 uint8_t enable_acg_gb_vdroop_table; 2999 uint8_t enable_acg_gb_fuse_table; 3000 uint32_t acg_dispclk2gfxclk_a; 3001 uint32_t acg_dispclk2gfxclk_b; 3002 uint32_t acg_dispclk2gfxclk_c; 3003 uint32_t acg_pixclk2gfxclk_a; 3004 uint32_t acg_pixclk2gfxclk_b; 3005 uint32_t acg_pixclk2gfxclk_c; 3006 uint32_t acg_dcefclk2gfxclk_a; 3007 uint32_t acg_dcefclk2gfxclk_b; 3008 uint32_t acg_dcefclk2gfxclk_c; 3009 uint32_t acg_phyclk2gfxclk_a; 3010 uint32_t acg_phyclk2gfxclk_b; 3011 uint32_t acg_phyclk2gfxclk_c; 3012 }; 3013 3014 /* 3015 *************************************************************************** 3016 Data Table multimedia_info structure 3017 *************************************************************************** 3018 */ 3019 struct atom_multimedia_info_v2_1 3020 { 3021 struct atom_common_table_header table_header; 3022 uint8_t uvdip_min_ver; 3023 uint8_t uvdip_max_ver; 3024 uint8_t vceip_min_ver; 3025 uint8_t vceip_max_ver; 3026 uint16_t uvd_enc_max_input_width_pixels; 3027 uint16_t uvd_enc_max_input_height_pixels; 3028 uint16_t vce_enc_max_input_width_pixels; 3029 uint16_t vce_enc_max_input_height_pixels; 3030 uint32_t uvd_enc_max_bandwidth; // 16x16 pixels/sec, codec independent 3031 uint32_t vce_enc_max_bandwidth; // 16x16 pixels/sec, codec independent 3032 }; 3033 3034 3035 /* 3036 *************************************************************************** 3037 Data Table umc_info structure 3038 *************************************************************************** 3039 */ 3040 struct atom_umc_info_v3_1 3041 { 3042 struct atom_common_table_header table_header; 3043 uint32_t ucode_version; 3044 uint32_t ucode_rom_startaddr; 3045 uint32_t ucode_length; 3046 uint16_t umc_reg_init_offset; 3047 uint16_t customer_ucode_name_offset; 3048 uint16_t mclk_ss_percentage; 3049 uint16_t mclk_ss_rate_10hz; 3050 uint8_t umcip_min_ver; 3051 uint8_t umcip_max_ver; 3052 uint8_t vram_type; //enum of atom_dgpu_vram_type 3053 uint8_t umc_config; 3054 uint32_t mem_refclk_10khz; 3055 }; 3056 3057 // umc_info.umc_config 3058 enum atom_umc_config_def { 3059 UMC_CONFIG__ENABLE_1KB_INTERLEAVE_MODE = 0x00000001, 3060 UMC_CONFIG__DEFAULT_MEM_ECC_ENABLE = 0x00000002, 3061 UMC_CONFIG__ENABLE_HBM_LANE_REPAIR = 0x00000004, 3062 UMC_CONFIG__ENABLE_BANK_HARVESTING = 0x00000008, 3063 UMC_CONFIG__ENABLE_PHY_REINIT = 0x00000010, 3064 UMC_CONFIG__DISABLE_UCODE_CHKSTATUS = 0x00000020, 3065 }; 3066 3067 struct atom_umc_info_v3_2 3068 { 3069 struct atom_common_table_header table_header; 3070 uint32_t ucode_version; 3071 uint32_t ucode_rom_startaddr; 3072 uint32_t ucode_length; 3073 uint16_t umc_reg_init_offset; 3074 uint16_t customer_ucode_name_offset; 3075 uint16_t mclk_ss_percentage; 3076 uint16_t mclk_ss_rate_10hz; 3077 uint8_t umcip_min_ver; 3078 uint8_t umcip_max_ver; 3079 uint8_t vram_type; //enum of atom_dgpu_vram_type 3080 uint8_t umc_config; 3081 uint32_t mem_refclk_10khz; 3082 uint32_t pstate_uclk_10khz[4]; 3083 uint16_t umcgoldenoffset; 3084 uint16_t densitygoldenoffset; 3085 }; 3086 3087 struct atom_umc_info_v3_3 3088 { 3089 struct atom_common_table_header table_header; 3090 uint32_t ucode_reserved; 3091 uint32_t ucode_rom_startaddr; 3092 uint32_t ucode_length; 3093 uint16_t umc_reg_init_offset; 3094 uint16_t customer_ucode_name_offset; 3095 uint16_t mclk_ss_percentage; 3096 uint16_t mclk_ss_rate_10hz; 3097 uint8_t umcip_min_ver; 3098 uint8_t umcip_max_ver; 3099 uint8_t vram_type; //enum of atom_dgpu_vram_type 3100 uint8_t umc_config; 3101 uint32_t mem_refclk_10khz; 3102 uint32_t pstate_uclk_10khz[4]; 3103 uint16_t umcgoldenoffset; 3104 uint16_t densitygoldenoffset; 3105 uint32_t umc_config1; 3106 uint32_t bist_data_startaddr; 3107 uint32_t reserved[2]; 3108 }; 3109 3110 enum atom_umc_config1_def { 3111 UMC_CONFIG1__ENABLE_PSTATE_PHASE_STORE_TRAIN = 0x00000001, 3112 UMC_CONFIG1__ENABLE_AUTO_FRAMING = 0x00000002, 3113 UMC_CONFIG1__ENABLE_RESTORE_BIST_DATA = 0x00000004, 3114 UMC_CONFIG1__DISABLE_STROBE_MODE = 0x00000008, 3115 UMC_CONFIG1__DEBUG_DATA_PARITY_EN = 0x00000010, 3116 UMC_CONFIG1__ENABLE_ECC_CAPABLE = 0x00010000, 3117 }; 3118 3119 /* 3120 *************************************************************************** 3121 Data Table vram_info structure 3122 *************************************************************************** 3123 */ 3124 struct atom_vram_module_v9 { 3125 // Design Specific Values 3126 uint32_t memory_size; // Total memory size in unit of MB for CONFIG_MEMSIZE zeros 3127 uint32_t channel_enable; // bit vector, each bit indicate specific channel enable or not 3128 uint32_t max_mem_clk; // max memory clock of this memory in unit of 10kHz, =0 means it is not defined 3129 uint16_t reserved[3]; 3130 uint16_t mem_voltage; // mem_voltage 3131 uint16_t vram_module_size; // Size of atom_vram_module_v9 3132 uint8_t ext_memory_id; // Current memory module ID 3133 uint8_t memory_type; // enum of atom_dgpu_vram_type 3134 uint8_t channel_num; // Number of mem. channels supported in this module 3135 uint8_t channel_width; // CHANNEL_16BIT/CHANNEL_32BIT/CHANNEL_64BIT 3136 uint8_t density; // _8Mx32, _16Mx32, _16Mx16, _32Mx16 3137 uint8_t tunningset_id; // MC phy registers set per. 3138 uint8_t vender_rev_id; // [7:4] Revision, [3:0] Vendor code 3139 uint8_t refreshrate; // [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64ms) 3140 uint8_t hbm_ven_rev_id; // hbm_ven_rev_id 3141 uint8_t vram_rsd2; // reserved 3142 char dram_pnstring[20]; // part number end with '0'. 3143 }; 3144 3145 struct atom_vram_info_header_v2_3 { 3146 struct atom_common_table_header table_header; 3147 uint16_t mem_adjust_tbloffset; // offset of atom_umc_init_reg_block structure for memory vendor specific UMC adjust setting 3148 uint16_t mem_clk_patch_tbloffset; // offset of atom_umc_init_reg_block structure for memory clock specific UMC setting 3149 uint16_t mc_adjust_pertile_tbloffset; // offset of atom_umc_init_reg_block structure for Per Byte Offset Preset Settings 3150 uint16_t mc_phyinit_tbloffset; // offset of atom_umc_init_reg_block structure for MC phy init set 3151 uint16_t dram_data_remap_tbloffset; // reserved for now 3152 uint16_t tmrs_seq_offset; // offset of HBM tmrs 3153 uint16_t post_ucode_init_offset; // offset of atom_umc_init_reg_block structure for MC phy init after MC uCode complete umc init 3154 uint16_t vram_rsd2; 3155 uint8_t vram_module_num; // indicate number of VRAM module 3156 uint8_t umcip_min_ver; 3157 uint8_t umcip_max_ver; 3158 uint8_t mc_phy_tile_num; // indicate the MCD tile number which use in DramDataRemapTbl and usMcAdjustPerTileTblOffset 3159 struct atom_vram_module_v9 vram_module[16]; // just for allocation, real number of blocks is in ucNumOfVRAMModule; 3160 }; 3161 3162 /* 3163 *************************************************************************** 3164 Data Table vram_info v3.0 structure 3165 *************************************************************************** 3166 */ 3167 struct atom_vram_module_v3_0 { 3168 uint8_t density; 3169 uint8_t tunningset_id; 3170 uint8_t ext_memory_id; 3171 uint8_t dram_vendor_id; 3172 uint16_t dram_info_offset; 3173 uint16_t mem_tuning_offset; 3174 uint16_t tmrs_seq_offset; 3175 uint16_t reserved1; 3176 uint32_t dram_size_per_ch; 3177 uint32_t reserved[3]; 3178 char dram_pnstring[40]; 3179 }; 3180 3181 struct atom_vram_info_header_v3_0 { 3182 struct atom_common_table_header table_header; 3183 uint16_t mem_tuning_table_offset; 3184 uint16_t dram_info_table_offset; 3185 uint16_t tmrs_table_offset; 3186 uint16_t mc_init_table_offset; 3187 uint16_t dram_data_remap_table_offset; 3188 uint16_t umc_emuinittable_offset; 3189 uint16_t reserved_sub_table_offset[2]; 3190 uint8_t vram_module_num; 3191 uint8_t umcip_min_ver; 3192 uint8_t umcip_max_ver; 3193 uint8_t mc_phy_tile_num; 3194 uint8_t memory_type; 3195 uint8_t channel_num; 3196 uint8_t channel_width; 3197 uint8_t reserved1; 3198 uint32_t channel_enable; 3199 uint32_t channel1_enable; 3200 uint32_t feature_enable; 3201 uint32_t feature1_enable; 3202 uint32_t hardcode_mem_size; 3203 uint32_t reserved4[4]; 3204 struct atom_vram_module_v3_0 vram_module[8]; 3205 }; 3206 3207 struct atom_umc_register_addr_info{ 3208 uint32_t umc_register_addr:24; 3209 uint32_t umc_reg_type_ind:1; 3210 uint32_t umc_reg_rsvd:7; 3211 }; 3212 3213 //atom_umc_register_addr_info. 3214 enum atom_umc_register_addr_info_flag{ 3215 b3ATOM_UMC_REG_ADD_INFO_INDIRECT_ACCESS =0x01, 3216 }; 3217 3218 union atom_umc_register_addr_info_access 3219 { 3220 struct atom_umc_register_addr_info umc_reg_addr; 3221 uint32_t u32umc_reg_addr; 3222 }; 3223 3224 struct atom_umc_reg_setting_id_config{ 3225 uint32_t memclockrange:24; 3226 uint32_t mem_blk_id:8; 3227 }; 3228 3229 union atom_umc_reg_setting_id_config_access 3230 { 3231 struct atom_umc_reg_setting_id_config umc_id_access; 3232 uint32_t u32umc_id_access; 3233 }; 3234 3235 struct atom_umc_reg_setting_data_block{ 3236 union atom_umc_reg_setting_id_config_access block_id; 3237 uint32_t u32umc_reg_data[1]; 3238 }; 3239 3240 struct atom_umc_init_reg_block{ 3241 uint16_t umc_reg_num; 3242 uint16_t reserved; 3243 union atom_umc_register_addr_info_access umc_reg_list[1]; //for allocation purpose, the real number come from umc_reg_num; 3244 struct atom_umc_reg_setting_data_block umc_reg_setting_list[1]; 3245 }; 3246 3247 struct atom_vram_module_v10 { 3248 // Design Specific Values 3249 uint32_t memory_size; // Total memory size in unit of MB for CONFIG_MEMSIZE zeros 3250 uint32_t channel_enable; // bit vector, each bit indicate specific channel enable or not 3251 uint32_t max_mem_clk; // max memory clock of this memory in unit of 10kHz, =0 means it is not defined 3252 uint16_t reserved[3]; 3253 uint16_t mem_voltage; // mem_voltage 3254 uint16_t vram_module_size; // Size of atom_vram_module_v9 3255 uint8_t ext_memory_id; // Current memory module ID 3256 uint8_t memory_type; // enum of atom_dgpu_vram_type 3257 uint8_t channel_num; // Number of mem. channels supported in this module 3258 uint8_t channel_width; // CHANNEL_16BIT/CHANNEL_32BIT/CHANNEL_64BIT 3259 uint8_t density; // _8Mx32, _16Mx32, _16Mx16, _32Mx16 3260 uint8_t tunningset_id; // MC phy registers set per 3261 uint8_t vender_rev_id; // [7:4] Revision, [3:0] Vendor code 3262 uint8_t refreshrate; // [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64ms) 3263 uint8_t vram_flags; // bit0= bankgroup enable 3264 uint8_t vram_rsd2; // reserved 3265 uint16_t gddr6_mr10; // gddr6 mode register10 value 3266 uint16_t gddr6_mr1; // gddr6 mode register1 value 3267 uint16_t gddr6_mr2; // gddr6 mode register2 value 3268 uint16_t gddr6_mr7; // gddr6 mode register7 value 3269 char dram_pnstring[20]; // part number end with '0' 3270 }; 3271 3272 struct atom_vram_info_header_v2_4 { 3273 struct atom_common_table_header table_header; 3274 uint16_t mem_adjust_tbloffset; // offset of atom_umc_init_reg_block structure for memory vendor specific UMC adjust setting 3275 uint16_t mem_clk_patch_tbloffset; // offset of atom_umc_init_reg_block structure for memory clock specific UMC setting 3276 uint16_t mc_adjust_pertile_tbloffset; // offset of atom_umc_init_reg_block structure for Per Byte Offset Preset Settings 3277 uint16_t mc_phyinit_tbloffset; // offset of atom_umc_init_reg_block structure for MC phy init set 3278 uint16_t dram_data_remap_tbloffset; // reserved for now 3279 uint16_t reserved; // offset of reserved 3280 uint16_t post_ucode_init_offset; // offset of atom_umc_init_reg_block structure for MC phy init after MC uCode complete umc init 3281 uint16_t vram_rsd2; 3282 uint8_t vram_module_num; // indicate number of VRAM module 3283 uint8_t umcip_min_ver; 3284 uint8_t umcip_max_ver; 3285 uint8_t mc_phy_tile_num; // indicate the MCD tile number which use in DramDataRemapTbl and usMcAdjustPerTileTblOffset 3286 struct atom_vram_module_v10 vram_module[16]; // just for allocation, real number of blocks is in ucNumOfVRAMModule; 3287 }; 3288 3289 struct atom_vram_module_v11 { 3290 // Design Specific Values 3291 uint32_t memory_size; // Total memory size in unit of MB for CONFIG_MEMSIZE zeros 3292 uint32_t channel_enable; // bit vector, each bit indicate specific channel enable or not 3293 uint16_t mem_voltage; // mem_voltage 3294 uint16_t vram_module_size; // Size of atom_vram_module_v9 3295 uint8_t ext_memory_id; // Current memory module ID 3296 uint8_t memory_type; // enum of atom_dgpu_vram_type 3297 uint8_t channel_num; // Number of mem. channels supported in this module 3298 uint8_t channel_width; // CHANNEL_16BIT/CHANNEL_32BIT/CHANNEL_64BIT 3299 uint8_t density; // _8Mx32, _16Mx32, _16Mx16, _32Mx16 3300 uint8_t tunningset_id; // MC phy registers set per. 3301 uint16_t reserved[4]; // reserved 3302 uint8_t vender_rev_id; // [7:4] Revision, [3:0] Vendor code 3303 uint8_t refreshrate; // [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64ms) 3304 uint8_t vram_flags; // bit0= bankgroup enable 3305 uint8_t vram_rsd2; // reserved 3306 uint16_t gddr6_mr10; // gddr6 mode register10 value 3307 uint16_t gddr6_mr0; // gddr6 mode register0 value 3308 uint16_t gddr6_mr1; // gddr6 mode register1 value 3309 uint16_t gddr6_mr2; // gddr6 mode register2 value 3310 uint16_t gddr6_mr4; // gddr6 mode register4 value 3311 uint16_t gddr6_mr7; // gddr6 mode register7 value 3312 uint16_t gddr6_mr8; // gddr6 mode register8 value 3313 char dram_pnstring[40]; // part number end with '0'. 3314 }; 3315 3316 struct atom_gddr6_ac_timing_v2_5 { 3317 uint32_t u32umc_id_access; 3318 uint8_t RL; 3319 uint8_t WL; 3320 uint8_t tRAS; 3321 uint8_t tRC; 3322 3323 uint16_t tREFI; 3324 uint8_t tRFC; 3325 uint8_t tRFCpb; 3326 3327 uint8_t tRREFD; 3328 uint8_t tRCDRD; 3329 uint8_t tRCDWR; 3330 uint8_t tRP; 3331 3332 uint8_t tRRDS; 3333 uint8_t tRRDL; 3334 uint8_t tWR; 3335 uint8_t tWTRS; 3336 3337 uint8_t tWTRL; 3338 uint8_t tFAW; 3339 uint8_t tCCDS; 3340 uint8_t tCCDL; 3341 3342 uint8_t tCRCRL; 3343 uint8_t tCRCWL; 3344 uint8_t tCKE; 3345 uint8_t tCKSRE; 3346 3347 uint8_t tCKSRX; 3348 uint8_t tRTPS; 3349 uint8_t tRTPL; 3350 uint8_t tMRD; 3351 3352 uint8_t tMOD; 3353 uint8_t tXS; 3354 uint8_t tXHP; 3355 uint8_t tXSMRS; 3356 3357 uint32_t tXSH; 3358 3359 uint8_t tPD; 3360 uint8_t tXP; 3361 uint8_t tCPDED; 3362 uint8_t tACTPDE; 3363 3364 uint8_t tPREPDE; 3365 uint8_t tREFPDE; 3366 uint8_t tMRSPDEN; 3367 uint8_t tRDSRE; 3368 3369 uint8_t tWRSRE; 3370 uint8_t tPPD; 3371 uint8_t tCCDMW; 3372 uint8_t tWTRTR; 3373 3374 uint8_t tLTLTR; 3375 uint8_t tREFTR; 3376 uint8_t VNDR; 3377 uint8_t reserved[9]; 3378 }; 3379 3380 struct atom_gddr6_bit_byte_remap { 3381 uint32_t dphy_byteremap; //mmUMC_DPHY_ByteRemap 3382 uint32_t dphy_bitremap0; //mmUMC_DPHY_BitRemap0 3383 uint32_t dphy_bitremap1; //mmUMC_DPHY_BitRemap1 3384 uint32_t dphy_bitremap2; //mmUMC_DPHY_BitRemap2 3385 uint32_t aphy_bitremap0; //mmUMC_APHY_BitRemap0 3386 uint32_t aphy_bitremap1; //mmUMC_APHY_BitRemap1 3387 uint32_t phy_dram; //mmUMC_PHY_DRAM 3388 }; 3389 3390 struct atom_gddr6_dram_data_remap { 3391 uint32_t table_size; 3392 uint8_t phyintf_ck_inverted[8]; //UMC_PHY_PHYINTF_CNTL.INV_CK 3393 struct atom_gddr6_bit_byte_remap bit_byte_remap[16]; 3394 }; 3395 3396 struct atom_vram_info_header_v2_5 { 3397 struct atom_common_table_header table_header; 3398 uint16_t mem_adjust_tbloffset; // offset of atom_umc_init_reg_block structure for memory vendor specific UMC adjust settings 3399 uint16_t gddr6_ac_timing_offset; // offset of atom_gddr6_ac_timing_v2_5 structure for memory clock specific UMC settings 3400 uint16_t mc_adjust_pertile_tbloffset; // offset of atom_umc_init_reg_block structure for Per Byte Offset Preset Settings 3401 uint16_t mc_phyinit_tbloffset; // offset of atom_umc_init_reg_block structure for MC phy init set 3402 uint16_t dram_data_remap_tbloffset; // offset of atom_gddr6_dram_data_remap array to indicate DRAM data lane to GPU mapping 3403 uint16_t reserved; // offset of reserved 3404 uint16_t post_ucode_init_offset; // offset of atom_umc_init_reg_block structure for MC phy init after MC uCode complete umc init 3405 uint16_t strobe_mode_patch_tbloffset; // offset of atom_umc_init_reg_block structure for Strobe Mode memory clock specific UMC settings 3406 uint8_t vram_module_num; // indicate number of VRAM module 3407 uint8_t umcip_min_ver; 3408 uint8_t umcip_max_ver; 3409 uint8_t mc_phy_tile_num; // indicate the MCD tile number which use in DramDataRemapTbl and usMcAdjustPerTileTblOffset 3410 struct atom_vram_module_v11 vram_module[16]; // just for allocation, real number of blocks is in ucNumOfVRAMModule; 3411 }; 3412 3413 struct atom_vram_info_header_v2_6 { 3414 struct atom_common_table_header table_header; 3415 uint16_t mem_adjust_tbloffset; 3416 uint16_t mem_clk_patch_tbloffset; 3417 uint16_t mc_adjust_pertile_tbloffset; 3418 uint16_t mc_phyinit_tbloffset; 3419 uint16_t dram_data_remap_tbloffset; 3420 uint16_t tmrs_seq_offset; 3421 uint16_t post_ucode_init_offset; 3422 uint16_t vram_rsd2; 3423 uint8_t vram_module_num; 3424 uint8_t umcip_min_ver; 3425 uint8_t umcip_max_ver; 3426 uint8_t mc_phy_tile_num; 3427 struct atom_vram_module_v9 vram_module[16]; 3428 }; 3429 /* 3430 *************************************************************************** 3431 Data Table voltageobject_info structure 3432 *************************************************************************** 3433 */ 3434 struct atom_i2c_data_entry 3435 { 3436 uint16_t i2c_reg_index; // i2c register address, can be up to 16bit 3437 uint16_t i2c_reg_data; // i2c register data, can be up to 16bit 3438 }; 3439 3440 struct atom_voltage_object_header_v4{ 3441 uint8_t voltage_type; //enum atom_voltage_type 3442 uint8_t voltage_mode; //enum atom_voltage_object_mode 3443 uint16_t object_size; //Size of Object 3444 }; 3445 3446 // atom_voltage_object_header_v4.voltage_mode 3447 enum atom_voltage_object_mode 3448 { 3449 VOLTAGE_OBJ_GPIO_LUT = 0, //VOLTAGE and GPIO Lookup table ->atom_gpio_voltage_object_v4 3450 VOLTAGE_OBJ_VR_I2C_INIT_SEQ = 3, //VOLTAGE REGULATOR INIT sequece through I2C -> atom_i2c_voltage_object_v4 3451 VOLTAGE_OBJ_PHASE_LUT = 4, //Set Vregulator Phase lookup table ->atom_gpio_voltage_object_v4 3452 VOLTAGE_OBJ_SVID2 = 7, //Indicate voltage control by SVID2 ->atom_svid2_voltage_object_v4 3453 VOLTAGE_OBJ_EVV = 8, 3454 VOLTAGE_OBJ_MERGED_POWER = 9, 3455 }; 3456 3457 struct atom_i2c_voltage_object_v4 3458 { 3459 struct atom_voltage_object_header_v4 header; // voltage mode = VOLTAGE_OBJ_VR_I2C_INIT_SEQ 3460 uint8_t regulator_id; //Indicate Voltage Regulator Id 3461 uint8_t i2c_id; 3462 uint8_t i2c_slave_addr; 3463 uint8_t i2c_control_offset; 3464 uint8_t i2c_flag; // Bit0: 0 - One byte data; 1 - Two byte data 3465 uint8_t i2c_speed; // =0, use default i2c speed, otherwise use it in unit of kHz. 3466 uint8_t reserved[2]; 3467 struct atom_i2c_data_entry i2cdatalut[1]; // end with 0xff 3468 }; 3469 3470 // ATOM_I2C_VOLTAGE_OBJECT_V3.ucVoltageControlFlag 3471 enum atom_i2c_voltage_control_flag 3472 { 3473 VOLTAGE_DATA_ONE_BYTE = 0, 3474 VOLTAGE_DATA_TWO_BYTE = 1, 3475 }; 3476 3477 3478 struct atom_voltage_gpio_map_lut 3479 { 3480 uint32_t voltage_gpio_reg_val; // The Voltage ID which is used to program GPIO register 3481 uint16_t voltage_level_mv; // The corresponding Voltage Value, in mV 3482 }; 3483 3484 struct atom_gpio_voltage_object_v4 3485 { 3486 struct atom_voltage_object_header_v4 header; // voltage mode = VOLTAGE_OBJ_GPIO_LUT or VOLTAGE_OBJ_PHASE_LUT 3487 uint8_t gpio_control_id; // default is 0 which indicate control through CG VID mode 3488 uint8_t gpio_entry_num; // indiate the entry numbers of Votlage/Gpio value Look up table 3489 uint8_t phase_delay_us; // phase delay in unit of micro second 3490 uint8_t reserved; 3491 uint32_t gpio_mask_val; // GPIO Mask value 3492 struct atom_voltage_gpio_map_lut voltage_gpio_lut[1]; 3493 }; 3494 3495 struct atom_svid2_voltage_object_v4 3496 { 3497 struct atom_voltage_object_header_v4 header; // voltage mode = VOLTAGE_OBJ_SVID2 3498 uint8_t loadline_psi1; // bit4:0= loadline setting ( Core Loadline trim and offset trim ), bit5=0:PSI1_L disable =1: PSI1_L enable 3499 uint8_t psi0_l_vid_thresd; // VR PSI0_L VID threshold 3500 uint8_t psi0_enable; // 3501 uint8_t maxvstep; 3502 uint8_t telemetry_offset; 3503 uint8_t telemetry_gain; 3504 uint16_t reserved1; 3505 }; 3506 3507 struct atom_merged_voltage_object_v4 3508 { 3509 struct atom_voltage_object_header_v4 header; // voltage mode = VOLTAGE_OBJ_MERGED_POWER 3510 uint8_t merged_powerrail_type; //enum atom_voltage_type 3511 uint8_t reserved[3]; 3512 }; 3513 3514 union atom_voltage_object_v4{ 3515 struct atom_gpio_voltage_object_v4 gpio_voltage_obj; 3516 struct atom_i2c_voltage_object_v4 i2c_voltage_obj; 3517 struct atom_svid2_voltage_object_v4 svid2_voltage_obj; 3518 struct atom_merged_voltage_object_v4 merged_voltage_obj; 3519 }; 3520 3521 struct atom_voltage_objects_info_v4_1 3522 { 3523 struct atom_common_table_header table_header; 3524 union atom_voltage_object_v4 voltage_object[1]; //Info for Voltage control 3525 }; 3526 3527 3528 /* 3529 *************************************************************************** 3530 All Command Function structure definition 3531 *************************************************************************** 3532 */ 3533 3534 /* 3535 *************************************************************************** 3536 Structures used by asic_init 3537 *************************************************************************** 3538 */ 3539 3540 struct asic_init_engine_parameters 3541 { 3542 uint32_t sclkfreqin10khz:24; 3543 uint32_t engineflag:8; /* enum atom_asic_init_engine_flag */ 3544 }; 3545 3546 struct asic_init_mem_parameters 3547 { 3548 uint32_t mclkfreqin10khz:24; 3549 uint32_t memflag:8; /* enum atom_asic_init_mem_flag */ 3550 }; 3551 3552 struct asic_init_parameters_v2_1 3553 { 3554 struct asic_init_engine_parameters engineparam; 3555 struct asic_init_mem_parameters memparam; 3556 }; 3557 3558 struct asic_init_ps_allocation_v2_1 3559 { 3560 struct asic_init_parameters_v2_1 param; 3561 uint32_t reserved[16]; 3562 }; 3563 3564 3565 enum atom_asic_init_engine_flag 3566 { 3567 b3NORMAL_ENGINE_INIT = 0, 3568 b3SRIOV_SKIP_ASIC_INIT = 0x02, 3569 b3SRIOV_LOAD_UCODE = 0x40, 3570 }; 3571 3572 enum atom_asic_init_mem_flag 3573 { 3574 b3NORMAL_MEM_INIT = 0, 3575 b3DRAM_SELF_REFRESH_EXIT =0x20, 3576 }; 3577 3578 /* 3579 *************************************************************************** 3580 Structures used by setengineclock 3581 *************************************************************************** 3582 */ 3583 3584 struct set_engine_clock_parameters_v2_1 3585 { 3586 uint32_t sclkfreqin10khz:24; 3587 uint32_t sclkflag:8; /* enum atom_set_engine_mem_clock_flag, */ 3588 uint32_t reserved[10]; 3589 }; 3590 3591 struct set_engine_clock_ps_allocation_v2_1 3592 { 3593 struct set_engine_clock_parameters_v2_1 clockinfo; 3594 uint32_t reserved[10]; 3595 }; 3596 3597 3598 enum atom_set_engine_mem_clock_flag 3599 { 3600 b3NORMAL_CHANGE_CLOCK = 0, 3601 b3FIRST_TIME_CHANGE_CLOCK = 0x08, 3602 b3STORE_DPM_TRAINGING = 0x40, //Applicable to memory clock change,when set, it store specific DPM mode training result 3603 }; 3604 3605 /* 3606 *************************************************************************** 3607 Structures used by getengineclock 3608 *************************************************************************** 3609 */ 3610 struct get_engine_clock_parameter 3611 { 3612 uint32_t sclk_10khz; // current engine speed in 10KHz unit 3613 uint32_t reserved; 3614 }; 3615 3616 /* 3617 *************************************************************************** 3618 Structures used by setmemoryclock 3619 *************************************************************************** 3620 */ 3621 struct set_memory_clock_parameters_v2_1 3622 { 3623 uint32_t mclkfreqin10khz:24; 3624 uint32_t mclkflag:8; /* enum atom_set_engine_mem_clock_flag, */ 3625 uint32_t reserved[10]; 3626 }; 3627 3628 struct set_memory_clock_ps_allocation_v2_1 3629 { 3630 struct set_memory_clock_parameters_v2_1 clockinfo; 3631 uint32_t reserved[10]; 3632 }; 3633 3634 3635 /* 3636 *************************************************************************** 3637 Structures used by getmemoryclock 3638 *************************************************************************** 3639 */ 3640 struct get_memory_clock_parameter 3641 { 3642 uint32_t mclk_10khz; // current engine speed in 10KHz unit 3643 uint32_t reserved; 3644 }; 3645 3646 3647 3648 /* 3649 *************************************************************************** 3650 Structures used by setvoltage 3651 *************************************************************************** 3652 */ 3653 3654 struct set_voltage_parameters_v1_4 3655 { 3656 uint8_t voltagetype; /* enum atom_voltage_type */ 3657 uint8_t command; /* Indicate action: Set voltage level, enum atom_set_voltage_command */ 3658 uint16_t vlevel_mv; /* real voltage level in unit of mv or Voltage Phase (0, 1, 2, .. ) */ 3659 }; 3660 3661 //set_voltage_parameters_v2_1.voltagemode 3662 enum atom_set_voltage_command{ 3663 ATOM_SET_VOLTAGE = 0, 3664 ATOM_INIT_VOLTAGE_REGULATOR = 3, 3665 ATOM_SET_VOLTAGE_PHASE = 4, 3666 ATOM_GET_LEAKAGE_ID = 8, 3667 }; 3668 3669 struct set_voltage_ps_allocation_v1_4 3670 { 3671 struct set_voltage_parameters_v1_4 setvoltageparam; 3672 uint32_t reserved[10]; 3673 }; 3674 3675 3676 /* 3677 *************************************************************************** 3678 Structures used by computegpuclockparam 3679 *************************************************************************** 3680 */ 3681 3682 //ATOM_COMPUTE_CLOCK_FREQ.ulComputeClockFlag 3683 enum atom_gpu_clock_type 3684 { 3685 COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK =0x00, 3686 COMPUTE_GPUCLK_INPUT_FLAG_GFXCLK =0x01, 3687 COMPUTE_GPUCLK_INPUT_FLAG_UCLK =0x02, 3688 }; 3689 3690 struct compute_gpu_clock_input_parameter_v1_8 3691 { 3692 uint32_t gpuclock_10khz:24; //Input= target clock, output = actual clock 3693 uint32_t gpu_clock_type:8; //Input indicate clock type: enum atom_gpu_clock_type 3694 uint32_t reserved[5]; 3695 }; 3696 3697 3698 struct compute_gpu_clock_output_parameter_v1_8 3699 { 3700 uint32_t gpuclock_10khz:24; //Input= target clock, output = actual clock 3701 uint32_t dfs_did:8; //return parameter: DFS divider which is used to program to register directly 3702 uint32_t pll_fb_mult; //Feedback Multiplier, bit 8:0 int, bit 15:12 post_div, bit 31:16 frac 3703 uint32_t pll_ss_fbsmult; // Spread FB Mult: bit 8:0 int, bit 31:16 frac 3704 uint16_t pll_ss_slew_frac; 3705 uint8_t pll_ss_enable; 3706 uint8_t reserved; 3707 uint32_t reserved1[2]; 3708 }; 3709 3710 3711 3712 /* 3713 *************************************************************************** 3714 Structures used by ReadEfuseValue 3715 *************************************************************************** 3716 */ 3717 3718 struct read_efuse_input_parameters_v3_1 3719 { 3720 uint16_t efuse_start_index; 3721 uint8_t reserved; 3722 uint8_t bitslen; 3723 }; 3724 3725 // ReadEfuseValue input/output parameter 3726 union read_efuse_value_parameters_v3_1 3727 { 3728 struct read_efuse_input_parameters_v3_1 efuse_info; 3729 uint32_t efusevalue; 3730 }; 3731 3732 3733 /* 3734 *************************************************************************** 3735 Structures used by getsmuclockinfo 3736 *************************************************************************** 3737 */ 3738 struct atom_get_smu_clock_info_parameters_v3_1 3739 { 3740 uint8_t syspll_id; // 0= syspll0, 1=syspll1, 2=syspll2 3741 uint8_t clk_id; // atom_smu9_syspll0_clock_id (only valid when command == GET_SMU_CLOCK_INFO_V3_1_GET_CLOCK_FREQ ) 3742 uint8_t command; // enum of atom_get_smu_clock_info_command 3743 uint8_t dfsdid; // =0: get DFS DID from register, >0, give DFS divider, (only valid when command == GET_SMU_CLOCK_INFO_V3_1_GET_CLOCK_FREQ ) 3744 }; 3745 3746 enum atom_get_smu_clock_info_command 3747 { 3748 GET_SMU_CLOCK_INFO_V3_1_GET_CLOCK_FREQ = 0, 3749 GET_SMU_CLOCK_INFO_V3_1_GET_PLLVCO_FREQ = 1, 3750 GET_SMU_CLOCK_INFO_V3_1_GET_PLLREFCLK_FREQ = 2, 3751 }; 3752 3753 enum atom_smu9_syspll0_clock_id 3754 { 3755 SMU9_SYSPLL0_SMNCLK_ID = 0, // SMNCLK 3756 SMU9_SYSPLL0_SOCCLK_ID = 1, // SOCCLK (FCLK) 3757 SMU9_SYSPLL0_MP0CLK_ID = 2, // MP0CLK 3758 SMU9_SYSPLL0_MP1CLK_ID = 3, // MP1CLK 3759 SMU9_SYSPLL0_LCLK_ID = 4, // LCLK 3760 SMU9_SYSPLL0_DCLK_ID = 5, // DCLK 3761 SMU9_SYSPLL0_VCLK_ID = 6, // VCLK 3762 SMU9_SYSPLL0_ECLK_ID = 7, // ECLK 3763 SMU9_SYSPLL0_DCEFCLK_ID = 8, // DCEFCLK 3764 SMU9_SYSPLL0_DPREFCLK_ID = 10, // DPREFCLK 3765 SMU9_SYSPLL0_DISPCLK_ID = 11, // DISPCLK 3766 }; 3767 3768 enum atom_smu11_syspll_id { 3769 SMU11_SYSPLL0_ID = 0, 3770 SMU11_SYSPLL1_0_ID = 1, 3771 SMU11_SYSPLL1_1_ID = 2, 3772 SMU11_SYSPLL1_2_ID = 3, 3773 SMU11_SYSPLL2_ID = 4, 3774 SMU11_SYSPLL3_0_ID = 5, 3775 SMU11_SYSPLL3_1_ID = 6, 3776 }; 3777 3778 enum atom_smu11_syspll0_clock_id { 3779 SMU11_SYSPLL0_ECLK_ID = 0, // ECLK 3780 SMU11_SYSPLL0_SOCCLK_ID = 1, // SOCCLK 3781 SMU11_SYSPLL0_MP0CLK_ID = 2, // MP0CLK 3782 SMU11_SYSPLL0_DCLK_ID = 3, // DCLK 3783 SMU11_SYSPLL0_VCLK_ID = 4, // VCLK 3784 SMU11_SYSPLL0_DCEFCLK_ID = 5, // DCEFCLK 3785 }; 3786 3787 enum atom_smu11_syspll1_0_clock_id { 3788 SMU11_SYSPLL1_0_UCLKA_ID = 0, // UCLK_a 3789 }; 3790 3791 enum atom_smu11_syspll1_1_clock_id { 3792 SMU11_SYSPLL1_0_UCLKB_ID = 0, // UCLK_b 3793 }; 3794 3795 enum atom_smu11_syspll1_2_clock_id { 3796 SMU11_SYSPLL1_0_FCLK_ID = 0, // FCLK 3797 }; 3798 3799 enum atom_smu11_syspll2_clock_id { 3800 SMU11_SYSPLL2_GFXCLK_ID = 0, // GFXCLK 3801 }; 3802 3803 enum atom_smu11_syspll3_0_clock_id { 3804 SMU11_SYSPLL3_0_WAFCLK_ID = 0, // WAFCLK 3805 SMU11_SYSPLL3_0_DISPCLK_ID = 1, // DISPCLK 3806 SMU11_SYSPLL3_0_DPREFCLK_ID = 2, // DPREFCLK 3807 }; 3808 3809 enum atom_smu11_syspll3_1_clock_id { 3810 SMU11_SYSPLL3_1_MP1CLK_ID = 0, // MP1CLK 3811 SMU11_SYSPLL3_1_SMNCLK_ID = 1, // SMNCLK 3812 SMU11_SYSPLL3_1_LCLK_ID = 2, // LCLK 3813 }; 3814 3815 enum atom_smu12_syspll_id { 3816 SMU12_SYSPLL0_ID = 0, 3817 SMU12_SYSPLL1_ID = 1, 3818 SMU12_SYSPLL2_ID = 2, 3819 SMU12_SYSPLL3_0_ID = 3, 3820 SMU12_SYSPLL3_1_ID = 4, 3821 }; 3822 3823 enum atom_smu12_syspll0_clock_id { 3824 SMU12_SYSPLL0_SMNCLK_ID = 0, // SOCCLK 3825 SMU12_SYSPLL0_SOCCLK_ID = 1, // SOCCLK 3826 SMU12_SYSPLL0_MP0CLK_ID = 2, // MP0CLK 3827 SMU12_SYSPLL0_MP1CLK_ID = 3, // MP1CLK 3828 SMU12_SYSPLL0_MP2CLK_ID = 4, // MP2CLK 3829 SMU12_SYSPLL0_VCLK_ID = 5, // VCLK 3830 SMU12_SYSPLL0_LCLK_ID = 6, // LCLK 3831 SMU12_SYSPLL0_DCLK_ID = 7, // DCLK 3832 SMU12_SYSPLL0_ACLK_ID = 8, // ACLK 3833 SMU12_SYSPLL0_ISPCLK_ID = 9, // ISPCLK 3834 SMU12_SYSPLL0_SHUBCLK_ID = 10, // SHUBCLK 3835 }; 3836 3837 enum atom_smu12_syspll1_clock_id { 3838 SMU12_SYSPLL1_DISPCLK_ID = 0, // DISPCLK 3839 SMU12_SYSPLL1_DPPCLK_ID = 1, // DPPCLK 3840 SMU12_SYSPLL1_DPREFCLK_ID = 2, // DPREFCLK 3841 SMU12_SYSPLL1_DCFCLK_ID = 3, // DCFCLK 3842 }; 3843 3844 enum atom_smu12_syspll2_clock_id { 3845 SMU12_SYSPLL2_Pre_GFXCLK_ID = 0, // Pre_GFXCLK 3846 }; 3847 3848 enum atom_smu12_syspll3_0_clock_id { 3849 SMU12_SYSPLL3_0_FCLK_ID = 0, // FCLK 3850 }; 3851 3852 enum atom_smu12_syspll3_1_clock_id { 3853 SMU12_SYSPLL3_1_UMCCLK_ID = 0, // UMCCLK 3854 }; 3855 3856 struct atom_get_smu_clock_info_output_parameters_v3_1 3857 { 3858 union { 3859 uint32_t smu_clock_freq_hz; 3860 uint32_t syspllvcofreq_10khz; 3861 uint32_t sysspllrefclk_10khz; 3862 }atom_smu_outputclkfreq; 3863 }; 3864 3865 3866 3867 /* 3868 *************************************************************************** 3869 Structures used by dynamicmemorysettings 3870 *************************************************************************** 3871 */ 3872 3873 enum atom_dynamic_memory_setting_command 3874 { 3875 COMPUTE_MEMORY_PLL_PARAM = 1, 3876 COMPUTE_ENGINE_PLL_PARAM = 2, 3877 ADJUST_MC_SETTING_PARAM = 3, 3878 }; 3879 3880 /* when command = COMPUTE_MEMORY_PLL_PARAM or ADJUST_MC_SETTING_PARAM */ 3881 struct dynamic_mclk_settings_parameters_v2_1 3882 { 3883 uint32_t mclk_10khz:24; //Input= target mclk 3884 uint32_t command:8; //command enum of atom_dynamic_memory_setting_command 3885 uint32_t reserved; 3886 }; 3887 3888 /* when command = COMPUTE_ENGINE_PLL_PARAM */ 3889 struct dynamic_sclk_settings_parameters_v2_1 3890 { 3891 uint32_t sclk_10khz:24; //Input= target mclk 3892 uint32_t command:8; //command enum of atom_dynamic_memory_setting_command 3893 uint32_t mclk_10khz; 3894 uint32_t reserved; 3895 }; 3896 3897 union dynamic_memory_settings_parameters_v2_1 3898 { 3899 struct dynamic_mclk_settings_parameters_v2_1 mclk_setting; 3900 struct dynamic_sclk_settings_parameters_v2_1 sclk_setting; 3901 }; 3902 3903 3904 3905 /* 3906 *************************************************************************** 3907 Structures used by memorytraining 3908 *************************************************************************** 3909 */ 3910 3911 enum atom_umc6_0_ucode_function_call_enum_id 3912 { 3913 UMC60_UCODE_FUNC_ID_REINIT = 0, 3914 UMC60_UCODE_FUNC_ID_ENTER_SELFREFRESH = 1, 3915 UMC60_UCODE_FUNC_ID_EXIT_SELFREFRESH = 2, 3916 }; 3917 3918 3919 struct memory_training_parameters_v2_1 3920 { 3921 uint8_t ucode_func_id; 3922 uint8_t ucode_reserved[3]; 3923 uint32_t reserved[5]; 3924 }; 3925 3926 3927 /* 3928 *************************************************************************** 3929 Structures used by setpixelclock 3930 *************************************************************************** 3931 */ 3932 3933 struct set_pixel_clock_parameter_v1_7 3934 { 3935 uint32_t pixclk_100hz; // target the pixel clock to drive the CRTC timing in unit of 100Hz. 3936 3937 uint8_t pll_id; // ATOM_PHY_PLL0/ATOM_PHY_PLL1/ATOM_PPLL0 3938 uint8_t encoderobjid; // ASIC encoder id defined in objectId.h, 3939 // indicate which graphic encoder will be used. 3940 uint8_t encoder_mode; // Encoder mode: 3941 uint8_t miscinfo; // enum atom_set_pixel_clock_v1_7_misc_info 3942 uint8_t crtc_id; // enum of atom_crtc_def 3943 uint8_t deep_color_ratio; // HDMI panel bit depth: enum atom_set_pixel_clock_v1_7_deepcolor_ratio 3944 uint8_t reserved1[2]; 3945 uint32_t reserved2; 3946 }; 3947 3948 //ucMiscInfo 3949 enum atom_set_pixel_clock_v1_7_misc_info 3950 { 3951 PIXEL_CLOCK_V7_MISC_FORCE_PROG_PPLL = 0x01, 3952 PIXEL_CLOCK_V7_MISC_PROG_PHYPLL = 0x02, 3953 PIXEL_CLOCK_V7_MISC_YUV420_MODE = 0x04, 3954 PIXEL_CLOCK_V7_MISC_DVI_DUALLINK_EN = 0x08, 3955 PIXEL_CLOCK_V7_MISC_REF_DIV_SRC = 0x30, 3956 PIXEL_CLOCK_V7_MISC_REF_DIV_SRC_XTALIN = 0x00, 3957 PIXEL_CLOCK_V7_MISC_REF_DIV_SRC_PCIE = 0x10, 3958 PIXEL_CLOCK_V7_MISC_REF_DIV_SRC_GENLK = 0x20, 3959 PIXEL_CLOCK_V7_MISC_REF_DIV_SRC_REFPAD = 0x30, 3960 PIXEL_CLOCK_V7_MISC_ATOMIC_UPDATE = 0x40, 3961 PIXEL_CLOCK_V7_MISC_FORCE_SS_DIS = 0x80, 3962 }; 3963 3964 /* deep_color_ratio */ 3965 enum atom_set_pixel_clock_v1_7_deepcolor_ratio 3966 { 3967 PIXEL_CLOCK_V7_DEEPCOLOR_RATIO_DIS = 0x00, //00 - DCCG_DEEP_COLOR_DTO_DISABLE: Disable Deep Color DTO 3968 PIXEL_CLOCK_V7_DEEPCOLOR_RATIO_5_4 = 0x01, //01 - DCCG_DEEP_COLOR_DTO_5_4_RATIO: Set Deep Color DTO to 5:4 3969 PIXEL_CLOCK_V7_DEEPCOLOR_RATIO_3_2 = 0x02, //02 - DCCG_DEEP_COLOR_DTO_3_2_RATIO: Set Deep Color DTO to 3:2 3970 PIXEL_CLOCK_V7_DEEPCOLOR_RATIO_2_1 = 0x03, //03 - DCCG_DEEP_COLOR_DTO_2_1_RATIO: Set Deep Color DTO to 2:1 3971 }; 3972 3973 /* 3974 *************************************************************************** 3975 Structures used by setdceclock 3976 *************************************************************************** 3977 */ 3978 3979 // SetDCEClock input parameter for DCE11.2( ELM and BF ) and above 3980 struct set_dce_clock_parameters_v2_1 3981 { 3982 uint32_t dceclk_10khz; // target DCE frequency in unit of 10KHZ, return real DISPCLK/DPREFCLK frequency. 3983 uint8_t dceclktype; // =0: DISPCLK =1: DPREFCLK =2: PIXCLK 3984 uint8_t dceclksrc; // ATOM_PLL0 or ATOM_GCK_DFS or ATOM_FCH_CLK or ATOM_COMBOPHY_PLLx 3985 uint8_t dceclkflag; // Bit [1:0] = PPLL ref clock source ( when ucDCEClkSrc= ATOM_PPLL0 ) 3986 uint8_t crtc_id; // ucDisp Pipe Id, ATOM_CRTC0/1/2/..., use only when ucDCEClkType = PIXCLK 3987 }; 3988 3989 //ucDCEClkType 3990 enum atom_set_dce_clock_clock_type 3991 { 3992 DCE_CLOCK_TYPE_DISPCLK = 0, 3993 DCE_CLOCK_TYPE_DPREFCLK = 1, 3994 DCE_CLOCK_TYPE_PIXELCLK = 2, // used by VBIOS internally, called by SetPixelClock 3995 }; 3996 3997 //ucDCEClkFlag when ucDCEClkType == DPREFCLK 3998 enum atom_set_dce_clock_dprefclk_flag 3999 { 4000 DCE_CLOCK_FLAG_PLL_REFCLK_SRC_MASK = 0x03, 4001 DCE_CLOCK_FLAG_PLL_REFCLK_SRC_GENERICA = 0x00, 4002 DCE_CLOCK_FLAG_PLL_REFCLK_SRC_GENLK = 0x01, 4003 DCE_CLOCK_FLAG_PLL_REFCLK_SRC_PCIE = 0x02, 4004 DCE_CLOCK_FLAG_PLL_REFCLK_SRC_XTALIN = 0x03, 4005 }; 4006 4007 //ucDCEClkFlag when ucDCEClkType == PIXCLK 4008 enum atom_set_dce_clock_pixclk_flag 4009 { 4010 DCE_CLOCK_FLAG_PCLK_DEEPCOLOR_RATIO_MASK = 0x03, 4011 DCE_CLOCK_FLAG_PCLK_DEEPCOLOR_RATIO_DIS = 0x00, //00 - DCCG_DEEP_COLOR_DTO_DISABLE: Disable Deep Color DTO 4012 DCE_CLOCK_FLAG_PCLK_DEEPCOLOR_RATIO_5_4 = 0x01, //01 - DCCG_DEEP_COLOR_DTO_5_4_RATIO: Set Deep Color DTO to 5:4 4013 DCE_CLOCK_FLAG_PCLK_DEEPCOLOR_RATIO_3_2 = 0x02, //02 - DCCG_DEEP_COLOR_DTO_3_2_RATIO: Set Deep Color DTO to 3:2 4014 DCE_CLOCK_FLAG_PCLK_DEEPCOLOR_RATIO_2_1 = 0x03, //03 - DCCG_DEEP_COLOR_DTO_2_1_RATIO: Set Deep Color DTO to 2:1 4015 DCE_CLOCK_FLAG_PIXCLK_YUV420_MODE = 0x04, 4016 }; 4017 4018 struct set_dce_clock_ps_allocation_v2_1 4019 { 4020 struct set_dce_clock_parameters_v2_1 param; 4021 uint32_t ulReserved[2]; 4022 }; 4023 4024 4025 /****************************************************************************/ 4026 // Structures used by BlankCRTC 4027 /****************************************************************************/ 4028 struct blank_crtc_parameters 4029 { 4030 uint8_t crtc_id; // enum atom_crtc_def 4031 uint8_t blanking; // enum atom_blank_crtc_command 4032 uint16_t reserved; 4033 uint32_t reserved1; 4034 }; 4035 4036 enum atom_blank_crtc_command 4037 { 4038 ATOM_BLANKING = 1, 4039 ATOM_BLANKING_OFF = 0, 4040 }; 4041 4042 /****************************************************************************/ 4043 // Structures used by enablecrtc 4044 /****************************************************************************/ 4045 struct enable_crtc_parameters 4046 { 4047 uint8_t crtc_id; // enum atom_crtc_def 4048 uint8_t enable; // ATOM_ENABLE or ATOM_DISABLE 4049 uint8_t padding[2]; 4050 }; 4051 4052 4053 /****************************************************************************/ 4054 // Structure used by EnableDispPowerGating 4055 /****************************************************************************/ 4056 struct enable_disp_power_gating_parameters_v2_1 4057 { 4058 uint8_t disp_pipe_id; // ATOM_CRTC1, ATOM_CRTC2, ... 4059 uint8_t enable; // ATOM_ENABLE or ATOM_DISABLE 4060 uint8_t padding[2]; 4061 }; 4062 4063 struct enable_disp_power_gating_ps_allocation 4064 { 4065 struct enable_disp_power_gating_parameters_v2_1 param; 4066 uint32_t ulReserved[4]; 4067 }; 4068 4069 /****************************************************************************/ 4070 // Structure used in setcrtc_usingdtdtiming 4071 /****************************************************************************/ 4072 struct set_crtc_using_dtd_timing_parameters 4073 { 4074 uint16_t h_size; 4075 uint16_t h_blanking_time; 4076 uint16_t v_size; 4077 uint16_t v_blanking_time; 4078 uint16_t h_syncoffset; 4079 uint16_t h_syncwidth; 4080 uint16_t v_syncoffset; 4081 uint16_t v_syncwidth; 4082 uint16_t modemiscinfo; 4083 uint8_t h_border; 4084 uint8_t v_border; 4085 uint8_t crtc_id; // enum atom_crtc_def 4086 uint8_t encoder_mode; // atom_encode_mode_def 4087 uint8_t padding[2]; 4088 }; 4089 4090 4091 /****************************************************************************/ 4092 // Structures used by processi2cchanneltransaction 4093 /****************************************************************************/ 4094 struct process_i2c_channel_transaction_parameters 4095 { 4096 uint8_t i2cspeed_khz; 4097 union { 4098 uint8_t regindex; 4099 uint8_t status; /* enum atom_process_i2c_flag */ 4100 } regind_status; 4101 uint16_t i2c_data_out; 4102 uint8_t flag; /* enum atom_process_i2c_status */ 4103 uint8_t trans_bytes; 4104 uint8_t slave_addr; 4105 uint8_t i2c_id; 4106 }; 4107 4108 //ucFlag 4109 enum atom_process_i2c_flag 4110 { 4111 HW_I2C_WRITE = 1, 4112 HW_I2C_READ = 0, 4113 I2C_2BYTE_ADDR = 0x02, 4114 HW_I2C_SMBUS_BYTE_WR = 0x04, 4115 }; 4116 4117 //status 4118 enum atom_process_i2c_status 4119 { 4120 HW_ASSISTED_I2C_STATUS_FAILURE =2, 4121 HW_ASSISTED_I2C_STATUS_SUCCESS =1, 4122 }; 4123 4124 4125 /****************************************************************************/ 4126 // Structures used by processauxchanneltransaction 4127 /****************************************************************************/ 4128 4129 struct process_aux_channel_transaction_parameters_v1_2 4130 { 4131 uint16_t aux_request; 4132 uint16_t dataout; 4133 uint8_t channelid; 4134 union { 4135 uint8_t reply_status; 4136 uint8_t aux_delay; 4137 } aux_status_delay; 4138 uint8_t dataout_len; 4139 uint8_t hpd_id; //=0: HPD1, =1: HPD2, =2: HPD3, =3: HPD4, =4: HPD5, =5: HPD6 4140 }; 4141 4142 4143 /****************************************************************************/ 4144 // Structures used by selectcrtc_source 4145 /****************************************************************************/ 4146 4147 struct select_crtc_source_parameters_v2_3 4148 { 4149 uint8_t crtc_id; // enum atom_crtc_def 4150 uint8_t encoder_id; // enum atom_dig_def 4151 uint8_t encode_mode; // enum atom_encode_mode_def 4152 uint8_t dst_bpc; // enum atom_panel_bit_per_color 4153 }; 4154 4155 4156 /****************************************************************************/ 4157 // Structures used by digxencodercontrol 4158 /****************************************************************************/ 4159 4160 // ucAction: 4161 enum atom_dig_encoder_control_action 4162 { 4163 ATOM_ENCODER_CMD_DISABLE_DIG = 0, 4164 ATOM_ENCODER_CMD_ENABLE_DIG = 1, 4165 ATOM_ENCODER_CMD_DP_LINK_TRAINING_START = 0x08, 4166 ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN1 = 0x09, 4167 ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN2 = 0x0a, 4168 ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN3 = 0x13, 4169 ATOM_ENCODER_CMD_DP_LINK_TRAINING_COMPLETE = 0x0b, 4170 ATOM_ENCODER_CMD_DP_VIDEO_OFF = 0x0c, 4171 ATOM_ENCODER_CMD_DP_VIDEO_ON = 0x0d, 4172 ATOM_ENCODER_CMD_SETUP_PANEL_MODE = 0x10, 4173 ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN4 = 0x14, 4174 ATOM_ENCODER_CMD_STREAM_SETUP = 0x0F, 4175 ATOM_ENCODER_CMD_LINK_SETUP = 0x11, 4176 ATOM_ENCODER_CMD_ENCODER_BLANK = 0x12, 4177 }; 4178 4179 //define ucPanelMode 4180 enum atom_dig_encoder_control_panelmode 4181 { 4182 DP_PANEL_MODE_DISABLE = 0x00, 4183 DP_PANEL_MODE_ENABLE_eDP_MODE = 0x01, 4184 DP_PANEL_MODE_ENABLE_LVLINK_MODE = 0x11, 4185 }; 4186 4187 //ucDigId 4188 enum atom_dig_encoder_control_v5_digid 4189 { 4190 ATOM_ENCODER_CONFIG_V5_DIG0_ENCODER = 0x00, 4191 ATOM_ENCODER_CONFIG_V5_DIG1_ENCODER = 0x01, 4192 ATOM_ENCODER_CONFIG_V5_DIG2_ENCODER = 0x02, 4193 ATOM_ENCODER_CONFIG_V5_DIG3_ENCODER = 0x03, 4194 ATOM_ENCODER_CONFIG_V5_DIG4_ENCODER = 0x04, 4195 ATOM_ENCODER_CONFIG_V5_DIG5_ENCODER = 0x05, 4196 ATOM_ENCODER_CONFIG_V5_DIG6_ENCODER = 0x06, 4197 ATOM_ENCODER_CONFIG_V5_DIG7_ENCODER = 0x07, 4198 }; 4199 4200 struct dig_encoder_stream_setup_parameters_v1_5 4201 { 4202 uint8_t digid; // 0~6 map to DIG0~DIG6 enum atom_dig_encoder_control_v5_digid 4203 uint8_t action; // = ATOM_ENOCODER_CMD_STREAM_SETUP 4204 uint8_t digmode; // ATOM_ENCODER_MODE_DP/ATOM_ENCODER_MODE_DVI/ATOM_ENCODER_MODE_HDMI 4205 uint8_t lanenum; // Lane number 4206 uint32_t pclk_10khz; // Pixel Clock in 10Khz 4207 uint8_t bitpercolor; 4208 uint8_t dplinkrate_270mhz;//= DP link rate/270Mhz, =6: 1.62G = 10: 2.7G, =20: 5.4Ghz, =30: 8.1Ghz etc 4209 uint8_t reserved[2]; 4210 }; 4211 4212 struct dig_encoder_link_setup_parameters_v1_5 4213 { 4214 uint8_t digid; // 0~6 map to DIG0~DIG6 enum atom_dig_encoder_control_v5_digid 4215 uint8_t action; // = ATOM_ENOCODER_CMD_LINK_SETUP 4216 uint8_t digmode; // ATOM_ENCODER_MODE_DP/ATOM_ENCODER_MODE_DVI/ATOM_ENCODER_MODE_HDMI 4217 uint8_t lanenum; // Lane number 4218 uint8_t symclk_10khz; // Symbol Clock in 10Khz 4219 uint8_t hpd_sel; 4220 uint8_t digfe_sel; // DIG stream( front-end ) selection, bit0 means DIG0 FE is enable, 4221 uint8_t reserved[2]; 4222 }; 4223 4224 struct dp_panel_mode_set_parameters_v1_5 4225 { 4226 uint8_t digid; // 0~6 map to DIG0~DIG6 enum atom_dig_encoder_control_v5_digid 4227 uint8_t action; // = ATOM_ENCODER_CMD_DPLINK_SETUP 4228 uint8_t panelmode; // enum atom_dig_encoder_control_panelmode 4229 uint8_t reserved1; 4230 uint32_t reserved2[2]; 4231 }; 4232 4233 struct dig_encoder_generic_cmd_parameters_v1_5 4234 { 4235 uint8_t digid; // 0~6 map to DIG0~DIG6 enum atom_dig_encoder_control_v5_digid 4236 uint8_t action; // = rest of generic encoder command which does not carry any parameters 4237 uint8_t reserved1[2]; 4238 uint32_t reserved2[2]; 4239 }; 4240 4241 union dig_encoder_control_parameters_v1_5 4242 { 4243 struct dig_encoder_generic_cmd_parameters_v1_5 cmd_param; 4244 struct dig_encoder_stream_setup_parameters_v1_5 stream_param; 4245 struct dig_encoder_link_setup_parameters_v1_5 link_param; 4246 struct dp_panel_mode_set_parameters_v1_5 dppanel_param; 4247 }; 4248 4249 /* 4250 *************************************************************************** 4251 Structures used by dig1transmittercontrol 4252 *************************************************************************** 4253 */ 4254 struct dig_transmitter_control_parameters_v1_6 4255 { 4256 uint8_t phyid; // 0=UNIPHYA, 1=UNIPHYB, 2=UNIPHYC, 3=UNIPHYD, 4= UNIPHYE 5=UNIPHYF 4257 uint8_t action; // define as ATOM_TRANSMITER_ACTION_xxx 4258 union { 4259 uint8_t digmode; // enum atom_encode_mode_def 4260 uint8_t dplaneset; // DP voltage swing and pre-emphasis value defined in DPCD DP_LANE_SET, "DP_LANE_SET__xDB_y_zV" 4261 } mode_laneset; 4262 uint8_t lanenum; // Lane number 1, 2, 4, 8 4263 uint32_t symclk_10khz; // Symbol Clock in 10Khz 4264 uint8_t hpdsel; // =1: HPD1, =2: HPD2, .... =6: HPD6, =0: HPD is not assigned 4265 uint8_t digfe_sel; // DIG stream( front-end ) selection, bit0 means DIG0 FE is enable, 4266 uint8_t connobj_id; // Connector Object Id defined in ObjectId.h 4267 uint8_t reserved; 4268 uint32_t reserved1; 4269 }; 4270 4271 struct dig_transmitter_control_ps_allocation_v1_6 4272 { 4273 struct dig_transmitter_control_parameters_v1_6 param; 4274 uint32_t reserved[4]; 4275 }; 4276 4277 //ucAction 4278 enum atom_dig_transmitter_control_action 4279 { 4280 ATOM_TRANSMITTER_ACTION_DISABLE = 0, 4281 ATOM_TRANSMITTER_ACTION_ENABLE = 1, 4282 ATOM_TRANSMITTER_ACTION_LCD_BLOFF = 2, 4283 ATOM_TRANSMITTER_ACTION_LCD_BLON = 3, 4284 ATOM_TRANSMITTER_ACTION_BL_BRIGHTNESS_CONTROL = 4, 4285 ATOM_TRANSMITTER_ACTION_LCD_SELFTEST_START = 5, 4286 ATOM_TRANSMITTER_ACTION_LCD_SELFTEST_STOP = 6, 4287 ATOM_TRANSMITTER_ACTION_INIT = 7, 4288 ATOM_TRANSMITTER_ACTION_DISABLE_OUTPUT = 8, 4289 ATOM_TRANSMITTER_ACTION_ENABLE_OUTPUT = 9, 4290 ATOM_TRANSMITTER_ACTION_SETUP = 10, 4291 ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH = 11, 4292 ATOM_TRANSMITTER_ACTION_POWER_ON = 12, 4293 ATOM_TRANSMITTER_ACTION_POWER_OFF = 13, 4294 }; 4295 4296 // digfe_sel 4297 enum atom_dig_transmitter_control_digfe_sel 4298 { 4299 ATOM_TRANMSITTER_V6__DIGA_SEL = 0x01, 4300 ATOM_TRANMSITTER_V6__DIGB_SEL = 0x02, 4301 ATOM_TRANMSITTER_V6__DIGC_SEL = 0x04, 4302 ATOM_TRANMSITTER_V6__DIGD_SEL = 0x08, 4303 ATOM_TRANMSITTER_V6__DIGE_SEL = 0x10, 4304 ATOM_TRANMSITTER_V6__DIGF_SEL = 0x20, 4305 ATOM_TRANMSITTER_V6__DIGG_SEL = 0x40, 4306 }; 4307 4308 4309 //ucHPDSel 4310 enum atom_dig_transmitter_control_hpd_sel 4311 { 4312 ATOM_TRANSMITTER_V6_NO_HPD_SEL = 0x00, 4313 ATOM_TRANSMITTER_V6_HPD1_SEL = 0x01, 4314 ATOM_TRANSMITTER_V6_HPD2_SEL = 0x02, 4315 ATOM_TRANSMITTER_V6_HPD3_SEL = 0x03, 4316 ATOM_TRANSMITTER_V6_HPD4_SEL = 0x04, 4317 ATOM_TRANSMITTER_V6_HPD5_SEL = 0x05, 4318 ATOM_TRANSMITTER_V6_HPD6_SEL = 0x06, 4319 }; 4320 4321 // ucDPLaneSet 4322 enum atom_dig_transmitter_control_dplaneset 4323 { 4324 DP_LANE_SET__0DB_0_4V = 0x00, 4325 DP_LANE_SET__0DB_0_6V = 0x01, 4326 DP_LANE_SET__0DB_0_8V = 0x02, 4327 DP_LANE_SET__0DB_1_2V = 0x03, 4328 DP_LANE_SET__3_5DB_0_4V = 0x08, 4329 DP_LANE_SET__3_5DB_0_6V = 0x09, 4330 DP_LANE_SET__3_5DB_0_8V = 0x0a, 4331 DP_LANE_SET__6DB_0_4V = 0x10, 4332 DP_LANE_SET__6DB_0_6V = 0x11, 4333 DP_LANE_SET__9_5DB_0_4V = 0x18, 4334 }; 4335 4336 4337 4338 /****************************************************************************/ 4339 // Structures used by ExternalEncoderControl V2.4 4340 /****************************************************************************/ 4341 4342 struct external_encoder_control_parameters_v2_4 4343 { 4344 uint16_t pixelclock_10khz; // pixel clock in 10Khz, valid when ucAction=SETUP/ENABLE_OUTPUT 4345 uint8_t config; // indicate which encoder, and DP link rate when ucAction = SETUP/ENABLE_OUTPUT 4346 uint8_t action; // 4347 uint8_t encodermode; // encoder mode, only used when ucAction = SETUP/ENABLE_OUTPUT 4348 uint8_t lanenum; // lane number, only used when ucAction = SETUP/ENABLE_OUTPUT 4349 uint8_t bitpercolor; // output bit per color, only valid when ucAction = SETUP/ENABLE_OUTPUT and ucEncodeMode= DP 4350 uint8_t hpd_id; 4351 }; 4352 4353 4354 // ucAction 4355 enum external_encoder_control_action_def 4356 { 4357 EXTERNAL_ENCODER_ACTION_V3_DISABLE_OUTPUT = 0x00, 4358 EXTERNAL_ENCODER_ACTION_V3_ENABLE_OUTPUT = 0x01, 4359 EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT = 0x07, 4360 EXTERNAL_ENCODER_ACTION_V3_ENCODER_SETUP = 0x0f, 4361 EXTERNAL_ENCODER_ACTION_V3_ENCODER_BLANKING_OFF = 0x10, 4362 EXTERNAL_ENCODER_ACTION_V3_ENCODER_BLANKING = 0x11, 4363 EXTERNAL_ENCODER_ACTION_V3_DACLOAD_DETECTION = 0x12, 4364 EXTERNAL_ENCODER_ACTION_V3_DDC_SETUP = 0x14, 4365 }; 4366 4367 // ucConfig 4368 enum external_encoder_control_v2_4_config_def 4369 { 4370 EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_MASK = 0x03, 4371 EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_1_62GHZ = 0x00, 4372 EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ = 0x01, 4373 EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_5_40GHZ = 0x02, 4374 EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_3_24GHZ = 0x03, 4375 EXTERNAL_ENCODER_CONFIG_V3_ENCODER_SEL_MAKS = 0x70, 4376 EXTERNAL_ENCODER_CONFIG_V3_ENCODER1 = 0x00, 4377 EXTERNAL_ENCODER_CONFIG_V3_ENCODER2 = 0x10, 4378 EXTERNAL_ENCODER_CONFIG_V3_ENCODER3 = 0x20, 4379 }; 4380 4381 struct external_encoder_control_ps_allocation_v2_4 4382 { 4383 struct external_encoder_control_parameters_v2_4 sExtEncoder; 4384 uint32_t reserved[2]; 4385 }; 4386 4387 4388 /* 4389 *************************************************************************** 4390 AMD ACPI Table 4391 4392 *************************************************************************** 4393 */ 4394 4395 struct amd_acpi_description_header{ 4396 uint32_t signature; 4397 uint32_t tableLength; //Length 4398 uint8_t revision; 4399 uint8_t checksum; 4400 uint8_t oemId[6]; 4401 uint8_t oemTableId[8]; //UINT64 OemTableId; 4402 uint32_t oemRevision; 4403 uint32_t creatorId; 4404 uint32_t creatorRevision; 4405 }; 4406 4407 struct uefi_acpi_vfct{ 4408 struct amd_acpi_description_header sheader; 4409 uint8_t tableUUID[16]; //0x24 4410 uint32_t vbiosimageoffset; //0x34. Offset to the first GOP_VBIOS_CONTENT block from the beginning of the stucture. 4411 uint32_t lib1Imageoffset; //0x38. Offset to the first GOP_LIB1_CONTENT block from the beginning of the stucture. 4412 uint32_t reserved[4]; //0x3C 4413 }; 4414 4415 struct vfct_image_header{ 4416 uint32_t pcibus; //0x4C 4417 uint32_t pcidevice; //0x50 4418 uint32_t pcifunction; //0x54 4419 uint16_t vendorid; //0x58 4420 uint16_t deviceid; //0x5A 4421 uint16_t ssvid; //0x5C 4422 uint16_t ssid; //0x5E 4423 uint32_t revision; //0x60 4424 uint32_t imagelength; //0x64 4425 }; 4426 4427 4428 struct gop_vbios_content { 4429 struct vfct_image_header vbiosheader; 4430 uint8_t vbioscontent[1]; 4431 }; 4432 4433 struct gop_lib1_content { 4434 struct vfct_image_header lib1header; 4435 uint8_t lib1content[1]; 4436 }; 4437 4438 4439 4440 /* 4441 *************************************************************************** 4442 Scratch Register definitions 4443 Each number below indicates which scratch regiser request, Active and 4444 Connect all share the same definitions as display_device_tag defines 4445 *************************************************************************** 4446 */ 4447 4448 enum scratch_register_def{ 4449 ATOM_DEVICE_CONNECT_INFO_DEF = 0, 4450 ATOM_BL_BRI_LEVEL_INFO_DEF = 2, 4451 ATOM_ACTIVE_INFO_DEF = 3, 4452 ATOM_LCD_INFO_DEF = 4, 4453 ATOM_DEVICE_REQ_INFO_DEF = 5, 4454 ATOM_ACC_CHANGE_INFO_DEF = 6, 4455 ATOM_PRE_OS_MODE_INFO_DEF = 7, 4456 ATOM_PRE_OS_ASSERTION_DEF = 8, //For GOP to record a 32bit assertion code, this is enabled by default in prodution GOP drivers. 4457 ATOM_INTERNAL_TIMER_INFO_DEF = 10, 4458 }; 4459 4460 enum scratch_device_connect_info_bit_def{ 4461 ATOM_DISPLAY_LCD1_CONNECT =0x0002, 4462 ATOM_DISPLAY_DFP1_CONNECT =0x0008, 4463 ATOM_DISPLAY_DFP2_CONNECT =0x0080, 4464 ATOM_DISPLAY_DFP3_CONNECT =0x0200, 4465 ATOM_DISPLAY_DFP4_CONNECT =0x0400, 4466 ATOM_DISPLAY_DFP5_CONNECT =0x0800, 4467 ATOM_DISPLAY_DFP6_CONNECT =0x0040, 4468 ATOM_DISPLAY_DFPx_CONNECT =0x0ec8, 4469 ATOM_CONNECT_INFO_DEVICE_MASK =0x0fff, 4470 }; 4471 4472 enum scratch_bl_bri_level_info_bit_def{ 4473 ATOM_CURRENT_BL_LEVEL_SHIFT =0x8, 4474 #ifndef _H2INC 4475 ATOM_CURRENT_BL_LEVEL_MASK =0x0000ff00, 4476 ATOM_DEVICE_DPMS_STATE =0x00010000, 4477 #endif 4478 }; 4479 4480 enum scratch_active_info_bits_def{ 4481 ATOM_DISPLAY_LCD1_ACTIVE =0x0002, 4482 ATOM_DISPLAY_DFP1_ACTIVE =0x0008, 4483 ATOM_DISPLAY_DFP2_ACTIVE =0x0080, 4484 ATOM_DISPLAY_DFP3_ACTIVE =0x0200, 4485 ATOM_DISPLAY_DFP4_ACTIVE =0x0400, 4486 ATOM_DISPLAY_DFP5_ACTIVE =0x0800, 4487 ATOM_DISPLAY_DFP6_ACTIVE =0x0040, 4488 ATOM_ACTIVE_INFO_DEVICE_MASK =0x0fff, 4489 }; 4490 4491 enum scratch_device_req_info_bits_def{ 4492 ATOM_DISPLAY_LCD1_REQ =0x0002, 4493 ATOM_DISPLAY_DFP1_REQ =0x0008, 4494 ATOM_DISPLAY_DFP2_REQ =0x0080, 4495 ATOM_DISPLAY_DFP3_REQ =0x0200, 4496 ATOM_DISPLAY_DFP4_REQ =0x0400, 4497 ATOM_DISPLAY_DFP5_REQ =0x0800, 4498 ATOM_DISPLAY_DFP6_REQ =0x0040, 4499 ATOM_REQ_INFO_DEVICE_MASK =0x0fff, 4500 }; 4501 4502 enum scratch_acc_change_info_bitshift_def{ 4503 ATOM_ACC_CHANGE_ACC_MODE_SHIFT =4, 4504 ATOM_ACC_CHANGE_LID_STATUS_SHIFT =6, 4505 }; 4506 4507 enum scratch_acc_change_info_bits_def{ 4508 ATOM_ACC_CHANGE_ACC_MODE =0x00000010, 4509 ATOM_ACC_CHANGE_LID_STATUS =0x00000040, 4510 }; 4511 4512 enum scratch_pre_os_mode_info_bits_def{ 4513 ATOM_PRE_OS_MODE_MASK =0x00000003, 4514 ATOM_PRE_OS_MODE_VGA =0x00000000, 4515 ATOM_PRE_OS_MODE_VESA =0x00000001, 4516 ATOM_PRE_OS_MODE_GOP =0x00000002, 4517 ATOM_PRE_OS_MODE_PIXEL_DEPTH =0x0000000C, 4518 ATOM_PRE_OS_MODE_PIXEL_FORMAT_MASK=0x000000F0, 4519 ATOM_PRE_OS_MODE_8BIT_PAL_EN =0x00000100, 4520 ATOM_ASIC_INIT_COMPLETE =0x00000200, 4521 #ifndef _H2INC 4522 ATOM_PRE_OS_MODE_NUMBER_MASK =0xFFFF0000, 4523 #endif 4524 }; 4525 4526 4527 4528 /* 4529 *************************************************************************** 4530 ATOM firmware ID header file 4531 !! Please keep it at end of the atomfirmware.h !! 4532 *************************************************************************** 4533 */ 4534 #include "atomfirmwareid.h" 4535 #pragma pack() 4536 4537 #endif 4538 4539