1 /****************************************************************************\ 2 * 3 * File Name atomfirmware.h 4 * Project This is an interface header file between atombios and OS GPU drivers for SoC15 products 5 * 6 * Description header file of general definitions for OS nd pre-OS video drivers 7 * 8 * Copyright 2014 Advanced Micro Devices, Inc. 9 * 10 * Permission is hereby granted, free of charge, to any person obtaining a copy of this software 11 * and associated documentation files (the "Software"), to deal in the Software without restriction, 12 * including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, 13 * and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, 14 * subject to the following conditions: 15 * 16 * The above copyright notice and this permission notice shall be included in all copies or substantial 17 * portions of the Software. 18 * 19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 22 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 23 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 24 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 25 * OTHER DEALINGS IN THE SOFTWARE. 26 * 27 \****************************************************************************/ 28 29 /*IMPORTANT NOTES 30 * If a change in VBIOS/Driver/Tool's interface is only needed for SoC15 and forward products, then the change is only needed in this atomfirmware.h header file. 31 * If a change in VBIOS/Driver/Tool's interface is only needed for pre-SoC15 products, then the change is only needed in atombios.h header file. 32 * If a change is needed for both pre and post SoC15 products, then the change has to be made separately and might be differently in both atomfirmware.h and atombios.h. 33 */ 34 35 #ifndef _ATOMFIRMWARE_H_ 36 #define _ATOMFIRMWARE_H_ 37 38 enum atom_bios_header_version_def{ 39 ATOM_MAJOR_VERSION =0x0003, 40 ATOM_MINOR_VERSION =0x0003, 41 }; 42 43 #ifdef _H2INC 44 #ifndef uint32_t 45 typedef unsigned long uint32_t; 46 #endif 47 48 #ifndef uint16_t 49 typedef unsigned short uint16_t; 50 #endif 51 52 #ifndef uint8_t 53 typedef unsigned char uint8_t; 54 #endif 55 #endif 56 57 enum atom_crtc_def{ 58 ATOM_CRTC1 =0, 59 ATOM_CRTC2 =1, 60 ATOM_CRTC3 =2, 61 ATOM_CRTC4 =3, 62 ATOM_CRTC5 =4, 63 ATOM_CRTC6 =5, 64 ATOM_CRTC_INVALID =0xff, 65 }; 66 67 enum atom_ppll_def{ 68 ATOM_PPLL0 =2, 69 ATOM_GCK_DFS =8, 70 ATOM_FCH_CLK =9, 71 ATOM_DP_DTO =11, 72 ATOM_COMBOPHY_PLL0 =20, 73 ATOM_COMBOPHY_PLL1 =21, 74 ATOM_COMBOPHY_PLL2 =22, 75 ATOM_COMBOPHY_PLL3 =23, 76 ATOM_COMBOPHY_PLL4 =24, 77 ATOM_COMBOPHY_PLL5 =25, 78 ATOM_PPLL_INVALID =0xff, 79 }; 80 81 // define ASIC internal encoder id ( bit vector ), used for CRTC_SourceSel 82 enum atom_dig_def{ 83 ASIC_INT_DIG1_ENCODER_ID =0x03, 84 ASIC_INT_DIG2_ENCODER_ID =0x09, 85 ASIC_INT_DIG3_ENCODER_ID =0x0a, 86 ASIC_INT_DIG4_ENCODER_ID =0x0b, 87 ASIC_INT_DIG5_ENCODER_ID =0x0c, 88 ASIC_INT_DIG6_ENCODER_ID =0x0d, 89 ASIC_INT_DIG7_ENCODER_ID =0x0e, 90 }; 91 92 //ucEncoderMode 93 enum atom_encode_mode_def 94 { 95 ATOM_ENCODER_MODE_DP =0, 96 ATOM_ENCODER_MODE_DP_SST =0, 97 ATOM_ENCODER_MODE_LVDS =1, 98 ATOM_ENCODER_MODE_DVI =2, 99 ATOM_ENCODER_MODE_HDMI =3, 100 ATOM_ENCODER_MODE_DP_AUDIO =5, 101 ATOM_ENCODER_MODE_DP_MST =5, 102 ATOM_ENCODER_MODE_CRT =15, 103 ATOM_ENCODER_MODE_DVO =16, 104 }; 105 106 enum atom_encoder_refclk_src_def{ 107 ENCODER_REFCLK_SRC_P1PLL =0, 108 ENCODER_REFCLK_SRC_P2PLL =1, 109 ENCODER_REFCLK_SRC_P3PLL =2, 110 ENCODER_REFCLK_SRC_EXTCLK =3, 111 ENCODER_REFCLK_SRC_INVALID =0xff, 112 }; 113 114 enum atom_scaler_def{ 115 ATOM_SCALER_DISABLE =0, /*scaler bypass mode, auto-center & no replication*/ 116 ATOM_SCALER_CENTER =1, //For Fudo, it's bypass and auto-center & auto replication 117 ATOM_SCALER_EXPANSION =2, /*scaler expansion by 2 tap alpha blending mode*/ 118 }; 119 120 enum atom_operation_def{ 121 ATOM_DISABLE = 0, 122 ATOM_ENABLE = 1, 123 ATOM_INIT = 7, 124 ATOM_GET_STATUS = 8, 125 }; 126 127 enum atom_embedded_display_op_def{ 128 ATOM_LCD_BL_OFF = 2, 129 ATOM_LCD_BL_OM = 3, 130 ATOM_LCD_BL_BRIGHTNESS_CONTROL = 4, 131 ATOM_LCD_SELFTEST_START = 5, 132 ATOM_LCD_SELFTEST_STOP = 6, 133 }; 134 135 enum atom_spread_spectrum_mode{ 136 ATOM_SS_CENTER_OR_DOWN_MODE_MASK = 0x01, 137 ATOM_SS_DOWN_SPREAD_MODE = 0x00, 138 ATOM_SS_CENTRE_SPREAD_MODE = 0x01, 139 ATOM_INT_OR_EXT_SS_MASK = 0x02, 140 ATOM_INTERNAL_SS_MASK = 0x00, 141 ATOM_EXTERNAL_SS_MASK = 0x02, 142 }; 143 144 /* define panel bit per color */ 145 enum atom_panel_bit_per_color{ 146 PANEL_BPC_UNDEFINE =0x00, 147 PANEL_6BIT_PER_COLOR =0x01, 148 PANEL_8BIT_PER_COLOR =0x02, 149 PANEL_10BIT_PER_COLOR =0x03, 150 PANEL_12BIT_PER_COLOR =0x04, 151 PANEL_16BIT_PER_COLOR =0x05, 152 }; 153 154 //ucVoltageType 155 enum atom_voltage_type 156 { 157 VOLTAGE_TYPE_VDDC = 1, 158 VOLTAGE_TYPE_MVDDC = 2, 159 VOLTAGE_TYPE_MVDDQ = 3, 160 VOLTAGE_TYPE_VDDCI = 4, 161 VOLTAGE_TYPE_VDDGFX = 5, 162 VOLTAGE_TYPE_PCC = 6, 163 VOLTAGE_TYPE_MVPP = 7, 164 VOLTAGE_TYPE_LEDDPM = 8, 165 VOLTAGE_TYPE_PCC_MVDD = 9, 166 VOLTAGE_TYPE_PCIE_VDDC = 10, 167 VOLTAGE_TYPE_PCIE_VDDR = 11, 168 VOLTAGE_TYPE_GENERIC_I2C_1 = 0x11, 169 VOLTAGE_TYPE_GENERIC_I2C_2 = 0x12, 170 VOLTAGE_TYPE_GENERIC_I2C_3 = 0x13, 171 VOLTAGE_TYPE_GENERIC_I2C_4 = 0x14, 172 VOLTAGE_TYPE_GENERIC_I2C_5 = 0x15, 173 VOLTAGE_TYPE_GENERIC_I2C_6 = 0x16, 174 VOLTAGE_TYPE_GENERIC_I2C_7 = 0x17, 175 VOLTAGE_TYPE_GENERIC_I2C_8 = 0x18, 176 VOLTAGE_TYPE_GENERIC_I2C_9 = 0x19, 177 VOLTAGE_TYPE_GENERIC_I2C_10 = 0x1A, 178 }; 179 180 enum atom_dgpu_vram_type { 181 ATOM_DGPU_VRAM_TYPE_GDDR5 = 0x50, 182 ATOM_DGPU_VRAM_TYPE_HBM2 = 0x60, 183 ATOM_DGPU_VRAM_TYPE_HBM2E = 0x61, 184 ATOM_DGPU_VRAM_TYPE_GDDR6 = 0x70, 185 }; 186 187 enum atom_dp_vs_preemph_def{ 188 DP_VS_LEVEL0_PREEMPH_LEVEL0 = 0x00, 189 DP_VS_LEVEL1_PREEMPH_LEVEL0 = 0x01, 190 DP_VS_LEVEL2_PREEMPH_LEVEL0 = 0x02, 191 DP_VS_LEVEL3_PREEMPH_LEVEL0 = 0x03, 192 DP_VS_LEVEL0_PREEMPH_LEVEL1 = 0x08, 193 DP_VS_LEVEL1_PREEMPH_LEVEL1 = 0x09, 194 DP_VS_LEVEL2_PREEMPH_LEVEL1 = 0x0a, 195 DP_VS_LEVEL0_PREEMPH_LEVEL2 = 0x10, 196 DP_VS_LEVEL1_PREEMPH_LEVEL2 = 0x11, 197 DP_VS_LEVEL0_PREEMPH_LEVEL3 = 0x18, 198 }; 199 200 201 /* 202 enum atom_string_def{ 203 asic_bus_type_pcie_string = "PCI_EXPRESS", 204 atom_fire_gl_string = "FGL", 205 atom_bios_string = "ATOM" 206 }; 207 */ 208 209 #pragma pack(1) /* BIOS data must use byte aligment*/ 210 211 enum atombios_image_offset{ 212 OFFSET_TO_ATOM_ROM_HEADER_POINTER =0x00000048, 213 OFFSET_TO_ATOM_ROM_IMAGE_SIZE =0x00000002, 214 OFFSET_TO_ATOMBIOS_ASIC_BUS_MEM_TYPE =0x94, 215 MAXSIZE_OF_ATOMBIOS_ASIC_BUS_MEM_TYPE =20, /*including the terminator 0x0!*/ 216 OFFSET_TO_GET_ATOMBIOS_NUMBER_OF_STRINGS =0x2f, 217 OFFSET_TO_GET_ATOMBIOS_STRING_START =0x6e, 218 }; 219 220 /**************************************************************************** 221 * Common header for all tables (Data table, Command function). 222 * Every table pointed in _ATOM_MASTER_DATA_TABLE has this common header. 223 * And the pointer actually points to this header. 224 ****************************************************************************/ 225 226 struct atom_common_table_header 227 { 228 uint16_t structuresize; 229 uint8_t format_revision; //mainly used for a hw function, when the parser is not backward compatible 230 uint8_t content_revision; //change it when a data table has a structure change, or a hw function has a input/output parameter change 231 }; 232 233 /**************************************************************************** 234 * Structure stores the ROM header. 235 ****************************************************************************/ 236 struct atom_rom_header_v2_2 237 { 238 struct atom_common_table_header table_header; 239 uint8_t atom_bios_string[4]; //enum atom_string_def atom_bios_string; //Signature to distinguish between Atombios and non-atombios, 240 uint16_t bios_segment_address; 241 uint16_t protectedmodeoffset; 242 uint16_t configfilenameoffset; 243 uint16_t crc_block_offset; 244 uint16_t vbios_bootupmessageoffset; 245 uint16_t int10_offset; 246 uint16_t pcibusdevinitcode; 247 uint16_t iobaseaddress; 248 uint16_t subsystem_vendor_id; 249 uint16_t subsystem_id; 250 uint16_t pci_info_offset; 251 uint16_t masterhwfunction_offset; //Offest for SW to get all command function offsets, Don't change the position 252 uint16_t masterdatatable_offset; //Offest for SW to get all data table offsets, Don't change the position 253 uint16_t reserved; 254 uint32_t pspdirtableoffset; 255 }; 256 257 /*==============================hw function portion======================================================================*/ 258 259 260 /**************************************************************************** 261 * Structures used in Command.mtb, each function name is not given here since those function could change from time to time 262 * The real functionality of each function is associated with the parameter structure version when defined 263 * For all internal cmd function definitions, please reference to atomstruct.h 264 ****************************************************************************/ 265 struct atom_master_list_of_command_functions_v2_1{ 266 uint16_t asic_init; //Function 267 uint16_t cmd_function1; //used as an internal one 268 uint16_t cmd_function2; //used as an internal one 269 uint16_t cmd_function3; //used as an internal one 270 uint16_t digxencodercontrol; //Function 271 uint16_t cmd_function5; //used as an internal one 272 uint16_t cmd_function6; //used as an internal one 273 uint16_t cmd_function7; //used as an internal one 274 uint16_t cmd_function8; //used as an internal one 275 uint16_t cmd_function9; //used as an internal one 276 uint16_t setengineclock; //Function 277 uint16_t setmemoryclock; //Function 278 uint16_t setpixelclock; //Function 279 uint16_t enabledisppowergating; //Function 280 uint16_t cmd_function14; //used as an internal one 281 uint16_t cmd_function15; //used as an internal one 282 uint16_t cmd_function16; //used as an internal one 283 uint16_t cmd_function17; //used as an internal one 284 uint16_t cmd_function18; //used as an internal one 285 uint16_t cmd_function19; //used as an internal one 286 uint16_t cmd_function20; //used as an internal one 287 uint16_t cmd_function21; //used as an internal one 288 uint16_t cmd_function22; //used as an internal one 289 uint16_t cmd_function23; //used as an internal one 290 uint16_t cmd_function24; //used as an internal one 291 uint16_t cmd_function25; //used as an internal one 292 uint16_t cmd_function26; //used as an internal one 293 uint16_t cmd_function27; //used as an internal one 294 uint16_t cmd_function28; //used as an internal one 295 uint16_t cmd_function29; //used as an internal one 296 uint16_t cmd_function30; //used as an internal one 297 uint16_t cmd_function31; //used as an internal one 298 uint16_t cmd_function32; //used as an internal one 299 uint16_t cmd_function33; //used as an internal one 300 uint16_t blankcrtc; //Function 301 uint16_t enablecrtc; //Function 302 uint16_t cmd_function36; //used as an internal one 303 uint16_t cmd_function37; //used as an internal one 304 uint16_t cmd_function38; //used as an internal one 305 uint16_t cmd_function39; //used as an internal one 306 uint16_t cmd_function40; //used as an internal one 307 uint16_t getsmuclockinfo; //Function 308 uint16_t selectcrtc_source; //Function 309 uint16_t cmd_function43; //used as an internal one 310 uint16_t cmd_function44; //used as an internal one 311 uint16_t cmd_function45; //used as an internal one 312 uint16_t setdceclock; //Function 313 uint16_t getmemoryclock; //Function 314 uint16_t getengineclock; //Function 315 uint16_t setcrtc_usingdtdtiming; //Function 316 uint16_t externalencodercontrol; //Function 317 uint16_t cmd_function51; //used as an internal one 318 uint16_t cmd_function52; //used as an internal one 319 uint16_t cmd_function53; //used as an internal one 320 uint16_t processi2cchanneltransaction;//Function 321 uint16_t cmd_function55; //used as an internal one 322 uint16_t cmd_function56; //used as an internal one 323 uint16_t cmd_function57; //used as an internal one 324 uint16_t cmd_function58; //used as an internal one 325 uint16_t cmd_function59; //used as an internal one 326 uint16_t computegpuclockparam; //Function 327 uint16_t cmd_function61; //used as an internal one 328 uint16_t cmd_function62; //used as an internal one 329 uint16_t dynamicmemorysettings; //Function function 330 uint16_t memorytraining; //Function function 331 uint16_t cmd_function65; //used as an internal one 332 uint16_t cmd_function66; //used as an internal one 333 uint16_t setvoltage; //Function 334 uint16_t cmd_function68; //used as an internal one 335 uint16_t readefusevalue; //Function 336 uint16_t cmd_function70; //used as an internal one 337 uint16_t cmd_function71; //used as an internal one 338 uint16_t cmd_function72; //used as an internal one 339 uint16_t cmd_function73; //used as an internal one 340 uint16_t cmd_function74; //used as an internal one 341 uint16_t cmd_function75; //used as an internal one 342 uint16_t dig1transmittercontrol; //Function 343 uint16_t cmd_function77; //used as an internal one 344 uint16_t processauxchanneltransaction;//Function 345 uint16_t cmd_function79; //used as an internal one 346 uint16_t getvoltageinfo; //Function 347 }; 348 349 struct atom_master_command_function_v2_1 350 { 351 struct atom_common_table_header table_header; 352 struct atom_master_list_of_command_functions_v2_1 listofcmdfunctions; 353 }; 354 355 /**************************************************************************** 356 * Structures used in every command function 357 ****************************************************************************/ 358 struct atom_function_attribute 359 { 360 uint16_t ws_in_bytes:8; //[7:0]=Size of workspace in Bytes (in multiple of a dword), 361 uint16_t ps_in_bytes:7; //[14:8]=Size of parameter space in Bytes (multiple of a dword), 362 uint16_t updated_by_util:1; //[15]=flag to indicate the function is updated by util 363 }; 364 365 366 /**************************************************************************** 367 * Common header for all hw functions. 368 * Every function pointed by _master_list_of_hw_function has this common header. 369 * And the pointer actually points to this header. 370 ****************************************************************************/ 371 struct atom_rom_hw_function_header 372 { 373 struct atom_common_table_header func_header; 374 struct atom_function_attribute func_attrib; 375 }; 376 377 378 /*==============================sw data table portion======================================================================*/ 379 /**************************************************************************** 380 * Structures used in data.mtb, each data table name is not given here since those data table could change from time to time 381 * The real name of each table is given when its data structure version is defined 382 ****************************************************************************/ 383 struct atom_master_list_of_data_tables_v2_1{ 384 uint16_t utilitypipeline; /* Offest for the utility to get parser info,Don't change this position!*/ 385 uint16_t multimedia_info; 386 uint16_t smc_dpm_info; 387 uint16_t sw_datatable3; 388 uint16_t firmwareinfo; /* Shared by various SW components */ 389 uint16_t sw_datatable5; 390 uint16_t lcd_info; /* Shared by various SW components */ 391 uint16_t sw_datatable7; 392 uint16_t smu_info; 393 uint16_t sw_datatable9; 394 uint16_t sw_datatable10; 395 uint16_t vram_usagebyfirmware; /* Shared by various SW components */ 396 uint16_t gpio_pin_lut; /* Shared by various SW components */ 397 uint16_t sw_datatable13; 398 uint16_t gfx_info; 399 uint16_t powerplayinfo; /* Shared by various SW components */ 400 uint16_t sw_datatable16; 401 uint16_t sw_datatable17; 402 uint16_t sw_datatable18; 403 uint16_t sw_datatable19; 404 uint16_t sw_datatable20; 405 uint16_t sw_datatable21; 406 uint16_t displayobjectinfo; /* Shared by various SW components */ 407 uint16_t indirectioaccess; /* used as an internal one */ 408 uint16_t umc_info; /* Shared by various SW components */ 409 uint16_t sw_datatable25; 410 uint16_t sw_datatable26; 411 uint16_t dce_info; /* Shared by various SW components */ 412 uint16_t vram_info; /* Shared by various SW components */ 413 uint16_t sw_datatable29; 414 uint16_t integratedsysteminfo; /* Shared by various SW components */ 415 uint16_t asic_profiling_info; /* Shared by various SW components */ 416 uint16_t voltageobject_info; /* shared by various SW components */ 417 uint16_t sw_datatable33; 418 uint16_t sw_datatable34; 419 }; 420 421 422 struct atom_master_data_table_v2_1 423 { 424 struct atom_common_table_header table_header; 425 struct atom_master_list_of_data_tables_v2_1 listOfdatatables; 426 }; 427 428 429 struct atom_dtd_format 430 { 431 uint16_t pixclk; 432 uint16_t h_active; 433 uint16_t h_blanking_time; 434 uint16_t v_active; 435 uint16_t v_blanking_time; 436 uint16_t h_sync_offset; 437 uint16_t h_sync_width; 438 uint16_t v_sync_offset; 439 uint16_t v_syncwidth; 440 uint16_t reserved; 441 uint16_t reserved0; 442 uint8_t h_border; 443 uint8_t v_border; 444 uint16_t miscinfo; 445 uint8_t atom_mode_id; 446 uint8_t refreshrate; 447 }; 448 449 /* atom_dtd_format.modemiscinfo defintion */ 450 enum atom_dtd_format_modemiscinfo{ 451 ATOM_HSYNC_POLARITY = 0x0002, 452 ATOM_VSYNC_POLARITY = 0x0004, 453 ATOM_H_REPLICATIONBY2 = 0x0010, 454 ATOM_V_REPLICATIONBY2 = 0x0020, 455 ATOM_INTERLACE = 0x0080, 456 ATOM_COMPOSITESYNC = 0x0040, 457 }; 458 459 460 /* utilitypipeline 461 * when format_revision==1 && content_revision==1, then this an info table for atomworks to use during debug session, no structure is associated with it. 462 * the location of it can't change 463 */ 464 465 466 /* 467 *************************************************************************** 468 Data Table firmwareinfo structure 469 *************************************************************************** 470 */ 471 472 struct atom_firmware_info_v3_1 473 { 474 struct atom_common_table_header table_header; 475 uint32_t firmware_revision; 476 uint32_t bootup_sclk_in10khz; 477 uint32_t bootup_mclk_in10khz; 478 uint32_t firmware_capability; // enum atombios_firmware_capability 479 uint32_t main_call_parser_entry; /* direct address of main parser call in VBIOS binary. */ 480 uint32_t bios_scratch_reg_startaddr; // 1st bios scratch register dword address 481 uint16_t bootup_vddc_mv; 482 uint16_t bootup_vddci_mv; 483 uint16_t bootup_mvddc_mv; 484 uint16_t bootup_vddgfx_mv; 485 uint8_t mem_module_id; 486 uint8_t coolingsolution_id; /*0: Air cooling; 1: Liquid cooling ... */ 487 uint8_t reserved1[2]; 488 uint32_t mc_baseaddr_high; 489 uint32_t mc_baseaddr_low; 490 uint32_t reserved2[6]; 491 }; 492 493 /* Total 32bit cap indication */ 494 enum atombios_firmware_capability 495 { 496 ATOM_FIRMWARE_CAP_FIRMWARE_POSTED = 0x00000001, 497 ATOM_FIRMWARE_CAP_GPU_VIRTUALIZATION = 0x00000002, 498 ATOM_FIRMWARE_CAP_WMI_SUPPORT = 0x00000040, 499 ATOM_FIRMWARE_CAP_HWEMU_ENABLE = 0x00000080, 500 ATOM_FIRMWARE_CAP_HWEMU_UMC_CFG = 0x00000100, 501 ATOM_FIRMWARE_CAP_SRAM_ECC = 0x00000200, 502 ATOM_FIRMWARE_CAP_ENABLE_2STAGE_BIST_TRAINING = 0x00000400, 503 ATOM_FIRMWARE_CAP_ENABLE_2ND_USB20PORT = 0x0008000, 504 ATOM_FIRMWARE_CAP_DYNAMIC_BOOT_CFG_ENABLE = 0x0020000, 505 }; 506 507 enum atom_cooling_solution_id{ 508 AIR_COOLING = 0x00, 509 LIQUID_COOLING = 0x01 510 }; 511 512 struct atom_firmware_info_v3_2 { 513 struct atom_common_table_header table_header; 514 uint32_t firmware_revision; 515 uint32_t bootup_sclk_in10khz; 516 uint32_t bootup_mclk_in10khz; 517 uint32_t firmware_capability; // enum atombios_firmware_capability 518 uint32_t main_call_parser_entry; /* direct address of main parser call in VBIOS binary. */ 519 uint32_t bios_scratch_reg_startaddr; // 1st bios scratch register dword address 520 uint16_t bootup_vddc_mv; 521 uint16_t bootup_vddci_mv; 522 uint16_t bootup_mvddc_mv; 523 uint16_t bootup_vddgfx_mv; 524 uint8_t mem_module_id; 525 uint8_t coolingsolution_id; /*0: Air cooling; 1: Liquid cooling ... */ 526 uint8_t reserved1[2]; 527 uint32_t mc_baseaddr_high; 528 uint32_t mc_baseaddr_low; 529 uint8_t board_i2c_feature_id; // enum of atom_board_i2c_feature_id_def 530 uint8_t board_i2c_feature_gpio_id; // i2c id find in gpio_lut data table gpio_id 531 uint8_t board_i2c_feature_slave_addr; 532 uint8_t reserved3; 533 uint16_t bootup_mvddq_mv; 534 uint16_t bootup_mvpp_mv; 535 uint32_t zfbstartaddrin16mb; 536 uint32_t reserved2[3]; 537 }; 538 539 struct atom_firmware_info_v3_3 540 { 541 struct atom_common_table_header table_header; 542 uint32_t firmware_revision; 543 uint32_t bootup_sclk_in10khz; 544 uint32_t bootup_mclk_in10khz; 545 uint32_t firmware_capability; // enum atombios_firmware_capability 546 uint32_t main_call_parser_entry; /* direct address of main parser call in VBIOS binary. */ 547 uint32_t bios_scratch_reg_startaddr; // 1st bios scratch register dword address 548 uint16_t bootup_vddc_mv; 549 uint16_t bootup_vddci_mv; 550 uint16_t bootup_mvddc_mv; 551 uint16_t bootup_vddgfx_mv; 552 uint8_t mem_module_id; 553 uint8_t coolingsolution_id; /*0: Air cooling; 1: Liquid cooling ... */ 554 uint8_t reserved1[2]; 555 uint32_t mc_baseaddr_high; 556 uint32_t mc_baseaddr_low; 557 uint8_t board_i2c_feature_id; // enum of atom_board_i2c_feature_id_def 558 uint8_t board_i2c_feature_gpio_id; // i2c id find in gpio_lut data table gpio_id 559 uint8_t board_i2c_feature_slave_addr; 560 uint8_t reserved3; 561 uint16_t bootup_mvddq_mv; 562 uint16_t bootup_mvpp_mv; 563 uint32_t zfbstartaddrin16mb; 564 uint32_t pplib_pptable_id; // if pplib_pptable_id!=0, pplib get powerplay table inside driver instead of from VBIOS 565 uint32_t reserved2[2]; 566 }; 567 568 struct atom_firmware_info_v3_4 { 569 struct atom_common_table_header table_header; 570 uint32_t firmware_revision; 571 uint32_t bootup_sclk_in10khz; 572 uint32_t bootup_mclk_in10khz; 573 uint32_t firmware_capability; // enum atombios_firmware_capability 574 uint32_t main_call_parser_entry; /* direct address of main parser call in VBIOS binary. */ 575 uint32_t bios_scratch_reg_startaddr; // 1st bios scratch register dword address 576 uint16_t bootup_vddc_mv; 577 uint16_t bootup_vddci_mv; 578 uint16_t bootup_mvddc_mv; 579 uint16_t bootup_vddgfx_mv; 580 uint8_t mem_module_id; 581 uint8_t coolingsolution_id; /*0: Air cooling; 1: Liquid cooling ... */ 582 uint8_t reserved1[2]; 583 uint32_t mc_baseaddr_high; 584 uint32_t mc_baseaddr_low; 585 uint8_t board_i2c_feature_id; // enum of atom_board_i2c_feature_id_def 586 uint8_t board_i2c_feature_gpio_id; // i2c id find in gpio_lut data table gpio_id 587 uint8_t board_i2c_feature_slave_addr; 588 uint8_t reserved3; 589 uint16_t bootup_mvddq_mv; 590 uint16_t bootup_mvpp_mv; 591 uint32_t zfbstartaddrin16mb; 592 uint32_t pplib_pptable_id; // if pplib_pptable_id!=0, pplib get powerplay table inside driver instead of from VBIOS 593 uint32_t mvdd_ratio; // mvdd_raio = (real mvdd in power rail)*1000/(mvdd_output_from_svi2) 594 uint16_t hw_bootup_vddgfx_mv; // hw default vddgfx voltage level decide by board strap 595 uint16_t hw_bootup_vddc_mv; // hw default vddc voltage level decide by board strap 596 uint16_t hw_bootup_mvddc_mv; // hw default mvddc voltage level decide by board strap 597 uint16_t hw_bootup_vddci_mv; // hw default vddci voltage level decide by board strap 598 uint32_t maco_pwrlimit_mw; // bomaco mode power limit in unit of m-watt 599 uint32_t usb_pwrlimit_mw; // power limit when USB is enable in unit of m-watt 600 uint32_t fw_reserved_size_in_kb; // VBIOS reserved extra fw size in unit of kb. 601 uint32_t pspbl_init_done_reg_addr; 602 uint32_t pspbl_init_done_value; 603 uint32_t pspbl_init_done_check_timeout; // time out in unit of us when polling pspbl init done 604 uint32_t reserved[2]; 605 }; 606 607 /* 608 *************************************************************************** 609 Data Table lcd_info structure 610 *************************************************************************** 611 */ 612 613 struct lcd_info_v2_1 614 { 615 struct atom_common_table_header table_header; 616 struct atom_dtd_format lcd_timing; 617 uint16_t backlight_pwm; 618 uint16_t special_handle_cap; 619 uint16_t panel_misc; 620 uint16_t lvds_max_slink_pclk; 621 uint16_t lvds_ss_percentage; 622 uint16_t lvds_ss_rate_10hz; 623 uint8_t pwr_on_digon_to_de; /*all pwr sequence numbers below are in uint of 4ms*/ 624 uint8_t pwr_on_de_to_vary_bl; 625 uint8_t pwr_down_vary_bloff_to_de; 626 uint8_t pwr_down_de_to_digoff; 627 uint8_t pwr_off_delay; 628 uint8_t pwr_on_vary_bl_to_blon; 629 uint8_t pwr_down_bloff_to_vary_bloff; 630 uint8_t panel_bpc; 631 uint8_t dpcd_edp_config_cap; 632 uint8_t dpcd_max_link_rate; 633 uint8_t dpcd_max_lane_count; 634 uint8_t dpcd_max_downspread; 635 uint8_t min_allowed_bl_level; 636 uint8_t max_allowed_bl_level; 637 uint8_t bootup_bl_level; 638 uint8_t dplvdsrxid; 639 uint32_t reserved1[8]; 640 }; 641 642 /* lcd_info_v2_1.panel_misc defintion */ 643 enum atom_lcd_info_panel_misc{ 644 ATOM_PANEL_MISC_FPDI =0x0002, 645 }; 646 647 //uceDPToLVDSRxId 648 enum atom_lcd_info_dptolvds_rx_id 649 { 650 eDP_TO_LVDS_RX_DISABLE = 0x00, // no eDP->LVDS translator chip 651 eDP_TO_LVDS_COMMON_ID = 0x01, // common eDP->LVDS translator chip without AMD SW init 652 eDP_TO_LVDS_REALTEK_ID = 0x02, // Realtek tansaltor which require AMD SW init 653 }; 654 655 656 /* 657 *************************************************************************** 658 Data Table gpio_pin_lut structure 659 *************************************************************************** 660 */ 661 662 struct atom_gpio_pin_assignment 663 { 664 uint32_t data_a_reg_index; 665 uint8_t gpio_bitshift; 666 uint8_t gpio_mask_bitshift; 667 uint8_t gpio_id; 668 uint8_t reserved; 669 }; 670 671 /* atom_gpio_pin_assignment.gpio_id definition */ 672 enum atom_gpio_pin_assignment_gpio_id { 673 I2C_HW_LANE_MUX =0x0f, /* only valid when bit7=1 */ 674 I2C_HW_ENGINE_ID_MASK =0x70, /* only valid when bit7=1 */ 675 I2C_HW_CAP =0x80, /*only when the I2C_HW_CAP is set, the pin ID is assigned to an I2C pin pair, otherwise, it's an generic GPIO pin */ 676 677 /* gpio_id pre-define id for multiple usage */ 678 /* GPIO use to control PCIE_VDDC in certain SLT board */ 679 PCIE_VDDC_CONTROL_GPIO_PINID = 56, 680 /* if PP_AC_DC_SWITCH_GPIO_PINID in Gpio_Pin_LutTable, AC/DC swithing feature is enable */ 681 PP_AC_DC_SWITCH_GPIO_PINID = 60, 682 /* VDDC_REGULATOR_VRHOT_GPIO_PINID in Gpio_Pin_LutTable, VRHot feature is enable */ 683 VDDC_VRHOT_GPIO_PINID = 61, 684 /*if VDDC_PCC_GPIO_PINID in GPIO_LUTable, Peak Current Control feature is enabled */ 685 VDDC_PCC_GPIO_PINID = 62, 686 /* Only used on certain SLT/PA board to allow utility to cut Efuse. */ 687 EFUSE_CUT_ENABLE_GPIO_PINID = 63, 688 /* ucGPIO=DRAM_SELF_REFRESH_GPIO_PIND uses for memory self refresh (ucGPIO=0, DRAM self-refresh; ucGPIO= */ 689 DRAM_SELF_REFRESH_GPIO_PINID = 64, 690 /* Thermal interrupt output->system thermal chip GPIO pin */ 691 THERMAL_INT_OUTPUT_GPIO_PINID =65, 692 }; 693 694 695 struct atom_gpio_pin_lut_v2_1 696 { 697 struct atom_common_table_header table_header; 698 /*the real number of this included in the structure is calcualted by using the (whole structure size - the header size)/size of atom_gpio_pin_lut */ 699 struct atom_gpio_pin_assignment gpio_pin[8]; 700 }; 701 702 703 /* 704 *************************************************************************** 705 Data Table vram_usagebyfirmware structure 706 *************************************************************************** 707 */ 708 709 struct vram_usagebyfirmware_v2_1 710 { 711 struct atom_common_table_header table_header; 712 uint32_t start_address_in_kb; 713 uint16_t used_by_firmware_in_kb; 714 uint16_t used_by_driver_in_kb; 715 }; 716 717 718 /* 719 *************************************************************************** 720 Data Table displayobjectinfo structure 721 *************************************************************************** 722 */ 723 724 enum atom_object_record_type_id 725 { 726 ATOM_I2C_RECORD_TYPE =1, 727 ATOM_HPD_INT_RECORD_TYPE =2, 728 ATOM_OBJECT_GPIO_CNTL_RECORD_TYPE =9, 729 ATOM_CONNECTOR_HPDPIN_LUT_RECORD_TYPE =16, 730 ATOM_CONNECTOR_AUXDDC_LUT_RECORD_TYPE =17, 731 ATOM_ENCODER_CAP_RECORD_TYPE=20, 732 ATOM_BRACKET_LAYOUT_RECORD_TYPE=21, 733 ATOM_CONNECTOR_FORCED_TMDS_CAP_RECORD_TYPE=22, 734 ATOM_DISP_CONNECTOR_CAPS_RECORD_TYPE=23, 735 ATOM_RECORD_END_TYPE =0xFF, 736 }; 737 738 struct atom_common_record_header 739 { 740 uint8_t record_type; //An emun to indicate the record type 741 uint8_t record_size; //The size of the whole record in byte 742 }; 743 744 struct atom_i2c_record 745 { 746 struct atom_common_record_header record_header; //record_type = ATOM_I2C_RECORD_TYPE 747 uint8_t i2c_id; 748 uint8_t i2c_slave_addr; //The slave address, it's 0 when the record is attached to connector for DDC 749 }; 750 751 struct atom_hpd_int_record 752 { 753 struct atom_common_record_header record_header; //record_type = ATOM_HPD_INT_RECORD_TYPE 754 uint8_t pin_id; //Corresponding block in GPIO_PIN_INFO table gives the pin info 755 uint8_t plugin_pin_state; 756 }; 757 758 // Bit maps for ATOM_ENCODER_CAP_RECORD.usEncoderCap 759 enum atom_encoder_caps_def 760 { 761 ATOM_ENCODER_CAP_RECORD_HBR2 =0x01, // DP1.2 HBR2 is supported by HW encoder, it is retired in NI. the real meaning from SI is MST_EN 762 ATOM_ENCODER_CAP_RECORD_MST_EN =0x01, // from SI, this bit means DP MST is enable or not. 763 ATOM_ENCODER_CAP_RECORD_HBR2_EN =0x02, // DP1.2 HBR2 setting is qualified and HBR2 can be enabled 764 ATOM_ENCODER_CAP_RECORD_HDMI6Gbps_EN =0x04, // HDMI2.0 6Gbps enable or not. 765 ATOM_ENCODER_CAP_RECORD_HBR3_EN =0x08, // DP1.3 HBR3 is supported by board. 766 ATOM_ENCODER_CAP_RECORD_USB_C_TYPE =0x100, // the DP connector is a USB-C type. 767 }; 768 769 struct atom_encoder_caps_record 770 { 771 struct atom_common_record_header record_header; //record_type = ATOM_ENCODER_CAP_RECORD_TYPE 772 uint32_t encodercaps; 773 }; 774 775 enum atom_connector_caps_def 776 { 777 ATOM_CONNECTOR_CAP_INTERNAL_DISPLAY = 0x01, //a cap bit to indicate that this non-embedded display connector is an internal display 778 ATOM_CONNECTOR_CAP_INTERNAL_DISPLAY_BL = 0x02, //a cap bit to indicate that this internal display requires BL control from GPU, refers to lcd_info for BL PWM freq 779 }; 780 781 struct atom_disp_connector_caps_record 782 { 783 struct atom_common_record_header record_header; 784 uint32_t connectcaps; 785 }; 786 787 //The following generic object gpio pin control record type will replace JTAG_RECORD/FPGA_CONTROL_RECORD/DVI_EXT_INPUT_RECORD above gradually 788 struct atom_gpio_pin_control_pair 789 { 790 uint8_t gpio_id; // GPIO_ID, find the corresponding ID in GPIO_LUT table 791 uint8_t gpio_pinstate; // Pin state showing how to set-up the pin 792 }; 793 794 struct atom_object_gpio_cntl_record 795 { 796 struct atom_common_record_header record_header; 797 uint8_t flag; // Future expnadibility 798 uint8_t number_of_pins; // Number of GPIO pins used to control the object 799 struct atom_gpio_pin_control_pair gpio[1]; // the real gpio pin pair determined by number of pins ucNumberOfPins 800 }; 801 802 //Definitions for GPIO pin state 803 enum atom_gpio_pin_control_pinstate_def 804 { 805 GPIO_PIN_TYPE_INPUT = 0x00, 806 GPIO_PIN_TYPE_OUTPUT = 0x10, 807 GPIO_PIN_TYPE_HW_CONTROL = 0x20, 808 809 //For GPIO_PIN_TYPE_OUTPUT the following is defined 810 GPIO_PIN_OUTPUT_STATE_MASK = 0x01, 811 GPIO_PIN_OUTPUT_STATE_SHIFT = 0, 812 GPIO_PIN_STATE_ACTIVE_LOW = 0x0, 813 GPIO_PIN_STATE_ACTIVE_HIGH = 0x1, 814 }; 815 816 // Indexes to GPIO array in GLSync record 817 // GLSync record is for Frame Lock/Gen Lock feature. 818 enum atom_glsync_record_gpio_index_def 819 { 820 ATOM_GPIO_INDEX_GLSYNC_REFCLK = 0, 821 ATOM_GPIO_INDEX_GLSYNC_HSYNC = 1, 822 ATOM_GPIO_INDEX_GLSYNC_VSYNC = 2, 823 ATOM_GPIO_INDEX_GLSYNC_SWAP_REQ = 3, 824 ATOM_GPIO_INDEX_GLSYNC_SWAP_GNT = 4, 825 ATOM_GPIO_INDEX_GLSYNC_INTERRUPT = 5, 826 ATOM_GPIO_INDEX_GLSYNC_V_RESET = 6, 827 ATOM_GPIO_INDEX_GLSYNC_SWAP_CNTL = 7, 828 ATOM_GPIO_INDEX_GLSYNC_SWAP_SEL = 8, 829 ATOM_GPIO_INDEX_GLSYNC_MAX = 9, 830 }; 831 832 833 struct atom_connector_hpdpin_lut_record //record for ATOM_CONNECTOR_HPDPIN_LUT_RECORD_TYPE 834 { 835 struct atom_common_record_header record_header; 836 uint8_t hpd_pin_map[8]; 837 }; 838 839 struct atom_connector_auxddc_lut_record //record for ATOM_CONNECTOR_AUXDDC_LUT_RECORD_TYPE 840 { 841 struct atom_common_record_header record_header; 842 uint8_t aux_ddc_map[8]; 843 }; 844 845 struct atom_connector_forced_tmds_cap_record 846 { 847 struct atom_common_record_header record_header; 848 // override TMDS capability on this connector when it operate in TMDS mode. usMaxTmdsClkRate = max TMDS Clock in Mhz/2.5 849 uint8_t maxtmdsclkrate_in2_5mhz; 850 uint8_t reserved; 851 }; 852 853 struct atom_connector_layout_info 854 { 855 uint16_t connectorobjid; 856 uint8_t connector_type; 857 uint8_t position; 858 }; 859 860 // define ATOM_CONNECTOR_LAYOUT_INFO.ucConnectorType to describe the display connector size 861 enum atom_connector_layout_info_connector_type_def 862 { 863 CONNECTOR_TYPE_DVI_D = 1, 864 865 CONNECTOR_TYPE_HDMI = 4, 866 CONNECTOR_TYPE_DISPLAY_PORT = 5, 867 CONNECTOR_TYPE_MINI_DISPLAY_PORT = 6, 868 }; 869 870 struct atom_bracket_layout_record 871 { 872 struct atom_common_record_header record_header; 873 uint8_t bracketlen; 874 uint8_t bracketwidth; 875 uint8_t conn_num; 876 uint8_t reserved; 877 struct atom_connector_layout_info conn_info[1]; 878 }; 879 880 enum atom_display_device_tag_def{ 881 ATOM_DISPLAY_LCD1_SUPPORT = 0x0002, //an embedded display is either an LVDS or eDP signal type of display 882 ATOM_DISPLAY_DFP1_SUPPORT = 0x0008, 883 ATOM_DISPLAY_DFP2_SUPPORT = 0x0080, 884 ATOM_DISPLAY_DFP3_SUPPORT = 0x0200, 885 ATOM_DISPLAY_DFP4_SUPPORT = 0x0400, 886 ATOM_DISPLAY_DFP5_SUPPORT = 0x0800, 887 ATOM_DISPLAY_DFP6_SUPPORT = 0x0040, 888 ATOM_DISPLAY_DFPx_SUPPORT = 0x0ec8, 889 }; 890 891 struct atom_display_object_path_v2 892 { 893 uint16_t display_objid; //Connector Object ID or Misc Object ID 894 uint16_t disp_recordoffset; 895 uint16_t encoderobjid; //first encoder closer to the connector, could be either an external or intenal encoder 896 uint16_t extencoderobjid; //2nd encoder after the first encoder, from the connector point of view; 897 uint16_t encoder_recordoffset; 898 uint16_t extencoder_recordoffset; 899 uint16_t device_tag; //a supported device vector, each display path starts with this.the paths are enumerated in the way of priority, a path appears first 900 uint8_t priority_id; 901 uint8_t reserved; 902 }; 903 904 struct display_object_info_table_v1_4 905 { 906 struct atom_common_table_header table_header; 907 uint16_t supporteddevices; 908 uint8_t number_of_path; 909 uint8_t reserved; 910 struct atom_display_object_path_v2 display_path[8]; //the real number of this included in the structure is calculated by using the (whole structure size - the header size- number_of_path)/size of atom_display_object_path 911 }; 912 913 914 /* 915 *************************************************************************** 916 Data Table dce_info structure 917 *************************************************************************** 918 */ 919 struct atom_display_controller_info_v4_1 920 { 921 struct atom_common_table_header table_header; 922 uint32_t display_caps; 923 uint32_t bootup_dispclk_10khz; 924 uint16_t dce_refclk_10khz; 925 uint16_t i2c_engine_refclk_10khz; 926 uint16_t dvi_ss_percentage; // in unit of 0.001% 927 uint16_t dvi_ss_rate_10hz; 928 uint16_t hdmi_ss_percentage; // in unit of 0.001% 929 uint16_t hdmi_ss_rate_10hz; 930 uint16_t dp_ss_percentage; // in unit of 0.001% 931 uint16_t dp_ss_rate_10hz; 932 uint8_t dvi_ss_mode; // enum of atom_spread_spectrum_mode 933 uint8_t hdmi_ss_mode; // enum of atom_spread_spectrum_mode 934 uint8_t dp_ss_mode; // enum of atom_spread_spectrum_mode 935 uint8_t ss_reserved; 936 uint8_t hardcode_mode_num; // a hardcode mode number defined in StandardVESA_TimingTable when a CRT or DFP EDID is not available 937 uint8_t reserved1[3]; 938 uint16_t dpphy_refclk_10khz; 939 uint16_t reserved2; 940 uint8_t dceip_min_ver; 941 uint8_t dceip_max_ver; 942 uint8_t max_disp_pipe_num; 943 uint8_t max_vbios_active_disp_pipe_num; 944 uint8_t max_ppll_num; 945 uint8_t max_disp_phy_num; 946 uint8_t max_aux_pairs; 947 uint8_t remotedisplayconfig; 948 uint8_t reserved3[8]; 949 }; 950 951 struct atom_display_controller_info_v4_2 952 { 953 struct atom_common_table_header table_header; 954 uint32_t display_caps; 955 uint32_t bootup_dispclk_10khz; 956 uint16_t dce_refclk_10khz; 957 uint16_t i2c_engine_refclk_10khz; 958 uint16_t dvi_ss_percentage; // in unit of 0.001% 959 uint16_t dvi_ss_rate_10hz; 960 uint16_t hdmi_ss_percentage; // in unit of 0.001% 961 uint16_t hdmi_ss_rate_10hz; 962 uint16_t dp_ss_percentage; // in unit of 0.001% 963 uint16_t dp_ss_rate_10hz; 964 uint8_t dvi_ss_mode; // enum of atom_spread_spectrum_mode 965 uint8_t hdmi_ss_mode; // enum of atom_spread_spectrum_mode 966 uint8_t dp_ss_mode; // enum of atom_spread_spectrum_mode 967 uint8_t ss_reserved; 968 uint8_t dfp_hardcode_mode_num; // DFP hardcode mode number defined in StandardVESA_TimingTable when EDID is not available 969 uint8_t dfp_hardcode_refreshrate;// DFP hardcode mode refreshrate defined in StandardVESA_TimingTable when EDID is not available 970 uint8_t vga_hardcode_mode_num; // VGA hardcode mode number defined in StandardVESA_TimingTable when EDID is not avablable 971 uint8_t vga_hardcode_refreshrate;// VGA hardcode mode number defined in StandardVESA_TimingTable when EDID is not avablable 972 uint16_t dpphy_refclk_10khz; 973 uint16_t reserved2; 974 uint8_t dcnip_min_ver; 975 uint8_t dcnip_max_ver; 976 uint8_t max_disp_pipe_num; 977 uint8_t max_vbios_active_disp_pipe_num; 978 uint8_t max_ppll_num; 979 uint8_t max_disp_phy_num; 980 uint8_t max_aux_pairs; 981 uint8_t remotedisplayconfig; 982 uint8_t reserved3[8]; 983 }; 984 985 struct atom_display_controller_info_v4_3 986 { 987 struct atom_common_table_header table_header; 988 uint32_t display_caps; 989 uint32_t bootup_dispclk_10khz; 990 uint16_t dce_refclk_10khz; 991 uint16_t i2c_engine_refclk_10khz; 992 uint16_t dvi_ss_percentage; // in unit of 0.001% 993 uint16_t dvi_ss_rate_10hz; 994 uint16_t hdmi_ss_percentage; // in unit of 0.001% 995 uint16_t hdmi_ss_rate_10hz; 996 uint16_t dp_ss_percentage; // in unit of 0.001% 997 uint16_t dp_ss_rate_10hz; 998 uint8_t dvi_ss_mode; // enum of atom_spread_spectrum_mode 999 uint8_t hdmi_ss_mode; // enum of atom_spread_spectrum_mode 1000 uint8_t dp_ss_mode; // enum of atom_spread_spectrum_mode 1001 uint8_t ss_reserved; 1002 uint8_t dfp_hardcode_mode_num; // DFP hardcode mode number defined in StandardVESA_TimingTable when EDID is not available 1003 uint8_t dfp_hardcode_refreshrate;// DFP hardcode mode refreshrate defined in StandardVESA_TimingTable when EDID is not available 1004 uint8_t vga_hardcode_mode_num; // VGA hardcode mode number defined in StandardVESA_TimingTable when EDID is not avablable 1005 uint8_t vga_hardcode_refreshrate;// VGA hardcode mode number defined in StandardVESA_TimingTable when EDID is not avablable 1006 uint16_t dpphy_refclk_10khz; 1007 uint16_t reserved2; 1008 uint8_t dcnip_min_ver; 1009 uint8_t dcnip_max_ver; 1010 uint8_t max_disp_pipe_num; 1011 uint8_t max_vbios_active_disp_pipe_num; 1012 uint8_t max_ppll_num; 1013 uint8_t max_disp_phy_num; 1014 uint8_t max_aux_pairs; 1015 uint8_t remotedisplayconfig; 1016 uint8_t reserved3[8]; 1017 }; 1018 1019 struct atom_display_controller_info_v4_4 { 1020 struct atom_common_table_header table_header; 1021 uint32_t display_caps; 1022 uint32_t bootup_dispclk_10khz; 1023 uint16_t dce_refclk_10khz; 1024 uint16_t i2c_engine_refclk_10khz; 1025 uint16_t dvi_ss_percentage; // in unit of 0.001% 1026 uint16_t dvi_ss_rate_10hz; 1027 uint16_t hdmi_ss_percentage; // in unit of 0.001% 1028 uint16_t hdmi_ss_rate_10hz; 1029 uint16_t dp_ss_percentage; // in unit of 0.001% 1030 uint16_t dp_ss_rate_10hz; 1031 uint8_t dvi_ss_mode; // enum of atom_spread_spectrum_mode 1032 uint8_t hdmi_ss_mode; // enum of atom_spread_spectrum_mode 1033 uint8_t dp_ss_mode; // enum of atom_spread_spectrum_mode 1034 uint8_t ss_reserved; 1035 uint8_t dfp_hardcode_mode_num; // DFP hardcode mode number defined in StandardVESA_TimingTable when EDID is not available 1036 uint8_t dfp_hardcode_refreshrate;// DFP hardcode mode refreshrate defined in StandardVESA_TimingTable when EDID is not available 1037 uint8_t vga_hardcode_mode_num; // VGA hardcode mode number defined in StandardVESA_TimingTable when EDID is not avablable 1038 uint8_t vga_hardcode_refreshrate;// VGA hardcode mode number defined in StandardVESA_TimingTable when EDID is not avablable 1039 uint16_t dpphy_refclk_10khz; 1040 uint16_t hw_chip_id; 1041 uint8_t dcnip_min_ver; 1042 uint8_t dcnip_max_ver; 1043 uint8_t max_disp_pipe_num; 1044 uint8_t max_vbios_active_disp_pipum; 1045 uint8_t max_ppll_num; 1046 uint8_t max_disp_phy_num; 1047 uint8_t max_aux_pairs; 1048 uint8_t remotedisplayconfig; 1049 uint32_t dispclk_pll_vco_freq; 1050 uint32_t dp_ref_clk_freq; 1051 uint32_t max_mclk_chg_lat; // Worst case blackout duration for a memory clock frequency (p-state) change, units of 100s of ns (0.1 us) 1052 uint32_t max_sr_exit_lat; // Worst case memory self refresh exit time, units of 100ns of ns (0.1us) 1053 uint32_t max_sr_enter_exit_lat; // Worst case memory self refresh entry followed by immediate exit time, units of 100ns of ns (0.1us) 1054 uint16_t dc_golden_table_offset; // point of struct of atom_dc_golden_table_vxx 1055 uint16_t dc_golden_table_ver; 1056 uint32_t reserved3[3]; 1057 }; 1058 1059 struct atom_dc_golden_table_v1 1060 { 1061 uint32_t aux_dphy_rx_control0_val; 1062 uint32_t aux_dphy_tx_control_val; 1063 uint32_t aux_dphy_rx_control1_val; 1064 uint32_t dc_gpio_aux_ctrl_0_val; 1065 uint32_t dc_gpio_aux_ctrl_1_val; 1066 uint32_t dc_gpio_aux_ctrl_2_val; 1067 uint32_t dc_gpio_aux_ctrl_3_val; 1068 uint32_t dc_gpio_aux_ctrl_4_val; 1069 uint32_t dc_gpio_aux_ctrl_5_val; 1070 uint32_t reserved[23]; 1071 }; 1072 1073 enum dce_info_caps_def 1074 { 1075 // only for VBIOS 1076 DCE_INFO_CAPS_FORCE_DISPDEV_CONNECTED =0x02, 1077 // only for VBIOS 1078 DCE_INFO_CAPS_DISABLE_DFP_DP_HBR2 =0x04, 1079 // only for VBIOS 1080 DCE_INFO_CAPS_ENABLE_INTERLAC_TIMING =0x08, 1081 // only for VBIOS 1082 DCE_INFO_CAPS_LTTPR_SUPPORT_ENABLE =0x20, 1083 DCE_INFO_CAPS_VBIOS_LTTPR_TRANSPARENT_ENABLE = 0x40, 1084 }; 1085 1086 /* 1087 *************************************************************************** 1088 Data Table ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO structure 1089 *************************************************************************** 1090 */ 1091 struct atom_ext_display_path 1092 { 1093 uint16_t device_tag; //A bit vector to show what devices are supported 1094 uint16_t device_acpi_enum; //16bit device ACPI id. 1095 uint16_t connectorobjid; //A physical connector for displays to plug in, using object connector definitions 1096 uint8_t auxddclut_index; //An index into external AUX/DDC channel LUT 1097 uint8_t hpdlut_index; //An index into external HPD pin LUT 1098 uint16_t ext_encoder_objid; //external encoder object id 1099 uint8_t channelmapping; // if ucChannelMapping=0, using default one to one mapping 1100 uint8_t chpninvert; // bit vector for up to 8 lanes, =0: P and N is not invert, =1 P and N is inverted 1101 uint16_t caps; 1102 uint16_t reserved; 1103 }; 1104 1105 //usCaps 1106 enum ext_display_path_cap_def { 1107 EXT_DISPLAY_PATH_CAPS__HBR2_DISABLE = 0x0001, 1108 EXT_DISPLAY_PATH_CAPS__DP_FIXED_VS_EN = 0x0002, 1109 EXT_DISPLAY_PATH_CAPS__EXT_CHIP_MASK = 0x007C, 1110 EXT_DISPLAY_PATH_CAPS__HDMI20_PI3EQX1204 = (0x01 << 2), //PI redriver chip 1111 EXT_DISPLAY_PATH_CAPS__HDMI20_TISN65DP159RSBT = (0x02 << 2), //TI retimer chip 1112 EXT_DISPLAY_PATH_CAPS__HDMI20_PARADE_PS175 = (0x03 << 2) //Parade DP->HDMI recoverter chip 1113 }; 1114 1115 struct atom_external_display_connection_info 1116 { 1117 struct atom_common_table_header table_header; 1118 uint8_t guid[16]; // a GUID is a 16 byte long string 1119 struct atom_ext_display_path path[7]; // total of fixed 7 entries. 1120 uint8_t checksum; // a simple Checksum of the sum of whole structure equal to 0x0. 1121 uint8_t stereopinid; // use for eDP panel 1122 uint8_t remotedisplayconfig; 1123 uint8_t edptolvdsrxid; 1124 uint8_t fixdpvoltageswing; // usCaps[1]=1, this indicate DP_LANE_SET value 1125 uint8_t reserved[3]; // for potential expansion 1126 }; 1127 1128 /* 1129 *************************************************************************** 1130 Data Table integratedsysteminfo structure 1131 *************************************************************************** 1132 */ 1133 1134 struct atom_camera_dphy_timing_param 1135 { 1136 uint8_t profile_id; // SENSOR_PROFILES 1137 uint32_t param; 1138 }; 1139 1140 struct atom_camera_dphy_elec_param 1141 { 1142 uint16_t param[3]; 1143 }; 1144 1145 struct atom_camera_module_info 1146 { 1147 uint8_t module_id; // 0: Rear, 1: Front right of user, 2: Front left of user 1148 uint8_t module_name[8]; 1149 struct atom_camera_dphy_timing_param timingparam[6]; // Exact number is under estimation and confirmation from sensor vendor 1150 }; 1151 1152 struct atom_camera_flashlight_info 1153 { 1154 uint8_t flashlight_id; // 0: Rear, 1: Front 1155 uint8_t name[8]; 1156 }; 1157 1158 struct atom_camera_data 1159 { 1160 uint32_t versionCode; 1161 struct atom_camera_module_info cameraInfo[3]; // Assuming 3 camera sensors max 1162 struct atom_camera_flashlight_info flashInfo; // Assuming 1 flashlight max 1163 struct atom_camera_dphy_elec_param dphy_param; 1164 uint32_t crc_val; // CRC 1165 }; 1166 1167 1168 struct atom_14nm_dpphy_dvihdmi_tuningset 1169 { 1170 uint32_t max_symclk_in10khz; 1171 uint8_t encoder_mode; //atom_encode_mode_def, =2: DVI, =3: HDMI mode 1172 uint8_t phy_sel; //bit vector of phy, bit0= phya, bit1=phyb, ....bit5 = phyf 1173 uint16_t margindeemph; //COMMON_MAR_DEEMPH_NOM[7:0]tx_margin_nom [15:8]deemph_gen1_nom 1174 uint8_t deemph_6db_4; //COMMON_SELDEEMPH60[31:24]deemph_6db_4 1175 uint8_t boostadj; //CMD_BUS_GLOBAL_FOR_TX_LANE0 [19:16]tx_boost_adj [20]tx_boost_en [23:22]tx_binary_ron_code_offset 1176 uint8_t tx_driver_fifty_ohms; //COMMON_ZCALCODE_CTRL[21].tx_driver_fifty_ohms 1177 uint8_t deemph_sel; //MARGIN_DEEMPH_LANE0.DEEMPH_SEL 1178 }; 1179 1180 struct atom_14nm_dpphy_dp_setting{ 1181 uint8_t dp_vs_pemph_level; //enum of atom_dp_vs_preemph_def 1182 uint16_t margindeemph; //COMMON_MAR_DEEMPH_NOM[7:0]tx_margin_nom [15:8]deemph_gen1_nom 1183 uint8_t deemph_6db_4; //COMMON_SELDEEMPH60[31:24]deemph_6db_4 1184 uint8_t boostadj; //CMD_BUS_GLOBAL_FOR_TX_LANE0 [19:16]tx_boost_adj [20]tx_boost_en [23:22]tx_binary_ron_code_offset 1185 }; 1186 1187 struct atom_14nm_dpphy_dp_tuningset{ 1188 uint8_t phy_sel; // bit vector of phy, bit0= phya, bit1=phyb, ....bit5 = phyf 1189 uint8_t version; 1190 uint16_t table_size; // size of atom_14nm_dpphy_dp_tuningset 1191 uint16_t reserved; 1192 struct atom_14nm_dpphy_dp_setting dptuning[10]; 1193 }; 1194 1195 struct atom_14nm_dig_transmitter_info_header_v4_0{ 1196 struct atom_common_table_header table_header; 1197 uint16_t pcie_phy_tmds_hdmi_macro_settings_offset; // offset of PCIEPhyTMDSHDMIMacroSettingsTbl 1198 uint16_t uniphy_vs_emph_lookup_table_offset; // offset of UniphyVSEmphLookUpTbl 1199 uint16_t uniphy_xbar_settings_table_offset; // offset of UniphyXbarSettingsTbl 1200 }; 1201 1202 struct atom_14nm_combphy_tmds_vs_set 1203 { 1204 uint8_t sym_clk; 1205 uint8_t dig_mode; 1206 uint8_t phy_sel; 1207 uint16_t common_mar_deemph_nom__margin_deemph_val; 1208 uint8_t common_seldeemph60__deemph_6db_4_val; 1209 uint8_t cmd_bus_global_for_tx_lane0__boostadj_val ; 1210 uint8_t common_zcalcode_ctrl__tx_driver_fifty_ohms_val; 1211 uint8_t margin_deemph_lane0__deemph_sel_val; 1212 }; 1213 1214 struct atom_DCN_dpphy_dvihdmi_tuningset 1215 { 1216 uint32_t max_symclk_in10khz; 1217 uint8_t encoder_mode; //atom_encode_mode_def, =2: DVI, =3: HDMI mode 1218 uint8_t phy_sel; //bit vector of phy, bit0= phya, bit1=phyb, ....bit5 = phyf 1219 uint8_t tx_eq_main; // map to RDPCSTX_PHY_FUSE0/1/2/3[5:0](EQ_MAIN) 1220 uint8_t tx_eq_pre; // map to RDPCSTX_PHY_FUSE0/1/2/3[11:6](EQ_PRE) 1221 uint8_t tx_eq_post; // map to RDPCSTX_PHY_FUSE0/1/2/3[17:12](EQ_POST) 1222 uint8_t reserved1; 1223 uint8_t tx_vboost_lvl; // tx_vboost_lvl, map to RDPCSTX_PHY_CNTL0.RDPCS_PHY_TX_VBOOST_LVL 1224 uint8_t reserved2; 1225 }; 1226 1227 struct atom_DCN_dpphy_dp_setting{ 1228 uint8_t dp_vs_pemph_level; //enum of atom_dp_vs_preemph_def 1229 uint8_t tx_eq_main; // map to RDPCSTX_PHY_FUSE0/1/2/3[5:0](EQ_MAIN) 1230 uint8_t tx_eq_pre; // map to RDPCSTX_PHY_FUSE0/1/2/3[11:6](EQ_PRE) 1231 uint8_t tx_eq_post; // map to RDPCSTX_PHY_FUSE0/1/2/3[17:12](EQ_POST) 1232 uint8_t tx_vboost_lvl; // tx_vboost_lvl, map to RDPCSTX_PHY_CNTL0.RDPCS_PHY_TX_VBOOST_LVL 1233 }; 1234 1235 struct atom_DCN_dpphy_dp_tuningset{ 1236 uint8_t phy_sel; // bit vector of phy, bit0= phya, bit1=phyb, ....bit5 = phyf 1237 uint8_t version; 1238 uint16_t table_size; // size of atom_14nm_dpphy_dp_setting 1239 uint16_t reserved; 1240 struct atom_DCN_dpphy_dp_setting dptunings[10]; 1241 }; 1242 1243 struct atom_i2c_reg_info { 1244 uint8_t ucI2cRegIndex; 1245 uint8_t ucI2cRegVal; 1246 }; 1247 1248 struct atom_hdmi_retimer_redriver_set { 1249 uint8_t HdmiSlvAddr; 1250 uint8_t HdmiRegNum; 1251 uint8_t Hdmi6GRegNum; 1252 struct atom_i2c_reg_info HdmiRegSetting[9]; //For non 6G Hz use 1253 struct atom_i2c_reg_info Hdmi6GhzRegSetting[3]; //For 6G Hz use. 1254 }; 1255 1256 struct atom_integrated_system_info_v1_11 1257 { 1258 struct atom_common_table_header table_header; 1259 uint32_t vbios_misc; //enum of atom_system_vbiosmisc_def 1260 uint32_t gpucapinfo; //enum of atom_system_gpucapinf_def 1261 uint32_t system_config; 1262 uint32_t cpucapinfo; 1263 uint16_t gpuclk_ss_percentage; //unit of 0.001%, 1000 mean 1% 1264 uint16_t gpuclk_ss_type; 1265 uint16_t lvds_ss_percentage; //unit of 0.001%, 1000 mean 1% 1266 uint16_t lvds_ss_rate_10hz; 1267 uint16_t hdmi_ss_percentage; //unit of 0.001%, 1000 mean 1% 1268 uint16_t hdmi_ss_rate_10hz; 1269 uint16_t dvi_ss_percentage; //unit of 0.001%, 1000 mean 1% 1270 uint16_t dvi_ss_rate_10hz; 1271 uint16_t dpphy_override; // bit vector, enum of atom_sysinfo_dpphy_override_def 1272 uint16_t lvds_misc; // enum of atom_sys_info_lvds_misc_def 1273 uint16_t backlight_pwm_hz; // pwm frequency in hz 1274 uint8_t memorytype; // enum of atom_dmi_t17_mem_type_def, APU memory type indication. 1275 uint8_t umachannelnumber; // number of memory channels 1276 uint8_t pwr_on_digon_to_de; /* all pwr sequence numbers below are in uint of 4ms */ 1277 uint8_t pwr_on_de_to_vary_bl; 1278 uint8_t pwr_down_vary_bloff_to_de; 1279 uint8_t pwr_down_de_to_digoff; 1280 uint8_t pwr_off_delay; 1281 uint8_t pwr_on_vary_bl_to_blon; 1282 uint8_t pwr_down_bloff_to_vary_bloff; 1283 uint8_t min_allowed_bl_level; 1284 uint8_t htc_hyst_limit; 1285 uint8_t htc_tmp_limit; 1286 uint8_t reserved1; 1287 uint8_t reserved2; 1288 struct atom_external_display_connection_info extdispconninfo; 1289 struct atom_14nm_dpphy_dvihdmi_tuningset dvi_tuningset; 1290 struct atom_14nm_dpphy_dvihdmi_tuningset hdmi_tuningset; 1291 struct atom_14nm_dpphy_dvihdmi_tuningset hdmi6g_tuningset; 1292 struct atom_14nm_dpphy_dp_tuningset dp_tuningset; // rbr 1.62G dp tuning set 1293 struct atom_14nm_dpphy_dp_tuningset dp_hbr3_tuningset; // HBR3 dp tuning set 1294 struct atom_camera_data camera_info; 1295 struct atom_hdmi_retimer_redriver_set dp0_retimer_set; //for DP0 1296 struct atom_hdmi_retimer_redriver_set dp1_retimer_set; //for DP1 1297 struct atom_hdmi_retimer_redriver_set dp2_retimer_set; //for DP2 1298 struct atom_hdmi_retimer_redriver_set dp3_retimer_set; //for DP3 1299 struct atom_14nm_dpphy_dp_tuningset dp_hbr_tuningset; //hbr 2.7G dp tuning set 1300 struct atom_14nm_dpphy_dp_tuningset dp_hbr2_tuningset; //hbr2 5.4G dp turnig set 1301 struct atom_14nm_dpphy_dp_tuningset edp_tuningset; //edp tuning set 1302 uint32_t reserved[66]; 1303 }; 1304 1305 struct atom_integrated_system_info_v1_12 1306 { 1307 struct atom_common_table_header table_header; 1308 uint32_t vbios_misc; //enum of atom_system_vbiosmisc_def 1309 uint32_t gpucapinfo; //enum of atom_system_gpucapinf_def 1310 uint32_t system_config; 1311 uint32_t cpucapinfo; 1312 uint16_t gpuclk_ss_percentage; //unit of 0.001%, 1000 mean 1% 1313 uint16_t gpuclk_ss_type; 1314 uint16_t lvds_ss_percentage; //unit of 0.001%, 1000 mean 1% 1315 uint16_t lvds_ss_rate_10hz; 1316 uint16_t hdmi_ss_percentage; //unit of 0.001%, 1000 mean 1% 1317 uint16_t hdmi_ss_rate_10hz; 1318 uint16_t dvi_ss_percentage; //unit of 0.001%, 1000 mean 1% 1319 uint16_t dvi_ss_rate_10hz; 1320 uint16_t dpphy_override; // bit vector, enum of atom_sysinfo_dpphy_override_def 1321 uint16_t lvds_misc; // enum of atom_sys_info_lvds_misc_def 1322 uint16_t backlight_pwm_hz; // pwm frequency in hz 1323 uint8_t memorytype; // enum of atom_dmi_t17_mem_type_def, APU memory type indication. 1324 uint8_t umachannelnumber; // number of memory channels 1325 uint8_t pwr_on_digon_to_de; // all pwr sequence numbers below are in uint of 4ms // 1326 uint8_t pwr_on_de_to_vary_bl; 1327 uint8_t pwr_down_vary_bloff_to_de; 1328 uint8_t pwr_down_de_to_digoff; 1329 uint8_t pwr_off_delay; 1330 uint8_t pwr_on_vary_bl_to_blon; 1331 uint8_t pwr_down_bloff_to_vary_bloff; 1332 uint8_t min_allowed_bl_level; 1333 uint8_t htc_hyst_limit; 1334 uint8_t htc_tmp_limit; 1335 uint8_t reserved1; 1336 uint8_t reserved2; 1337 struct atom_external_display_connection_info extdispconninfo; 1338 struct atom_DCN_dpphy_dvihdmi_tuningset TMDS_tuningset; 1339 struct atom_DCN_dpphy_dvihdmi_tuningset hdmiCLK5_tuningset; 1340 struct atom_DCN_dpphy_dvihdmi_tuningset hdmiCLK8_tuningset; 1341 struct atom_DCN_dpphy_dp_tuningset rbr_tuningset; // rbr 1.62G dp tuning set 1342 struct atom_DCN_dpphy_dp_tuningset hbr3_tuningset; // HBR3 dp tuning set 1343 struct atom_camera_data camera_info; 1344 struct atom_hdmi_retimer_redriver_set dp0_retimer_set; //for DP0 1345 struct atom_hdmi_retimer_redriver_set dp1_retimer_set; //for DP1 1346 struct atom_hdmi_retimer_redriver_set dp2_retimer_set; //for DP2 1347 struct atom_hdmi_retimer_redriver_set dp3_retimer_set; //for DP3 1348 struct atom_DCN_dpphy_dp_tuningset hbr_tuningset; //hbr 2.7G dp tuning set 1349 struct atom_DCN_dpphy_dp_tuningset hbr2_tuningset; //hbr2 5.4G dp turnig set 1350 struct atom_DCN_dpphy_dp_tuningset edp_tunings; //edp tuning set 1351 struct atom_DCN_dpphy_dvihdmi_tuningset hdmiCLK6_tuningset; 1352 uint32_t reserved[63]; 1353 }; 1354 1355 struct edp_info_table 1356 { 1357 uint16_t edp_backlight_pwm_hz; 1358 uint16_t edp_ss_percentage; 1359 uint16_t edp_ss_rate_10hz; 1360 uint16_t reserved1; 1361 uint32_t reserved2; 1362 uint8_t edp_pwr_on_off_delay; 1363 uint8_t edp_pwr_on_vary_bl_to_blon; 1364 uint8_t edp_pwr_down_bloff_to_vary_bloff; 1365 uint8_t edp_panel_bpc; 1366 uint8_t edp_bootup_bl_level; 1367 uint8_t reserved3[3]; 1368 uint32_t reserved4[3]; 1369 }; 1370 1371 struct atom_integrated_system_info_v2_1 1372 { 1373 struct atom_common_table_header table_header; 1374 uint32_t vbios_misc; //enum of atom_system_vbiosmisc_def 1375 uint32_t gpucapinfo; //enum of atom_system_gpucapinf_def 1376 uint32_t system_config; 1377 uint32_t cpucapinfo; 1378 uint16_t gpuclk_ss_percentage; //unit of 0.001%, 1000 mean 1% 1379 uint16_t gpuclk_ss_type; 1380 uint16_t dpphy_override; // bit vector, enum of atom_sysinfo_dpphy_override_def 1381 uint8_t memorytype; // enum of atom_dmi_t17_mem_type_def, APU memory type indication. 1382 uint8_t umachannelnumber; // number of memory channels 1383 uint8_t htc_hyst_limit; 1384 uint8_t htc_tmp_limit; 1385 uint8_t reserved1; 1386 uint8_t reserved2; 1387 struct edp_info_table edp1_info; 1388 struct edp_info_table edp2_info; 1389 uint32_t reserved3[8]; 1390 struct atom_external_display_connection_info extdispconninfo; 1391 struct atom_DCN_dpphy_dvihdmi_tuningset TMDS_tuningset; 1392 struct atom_DCN_dpphy_dvihdmi_tuningset hdmiCLK5_tuningset; //add clk6 1393 struct atom_DCN_dpphy_dvihdmi_tuningset hdmiCLK6_tuningset; 1394 struct atom_DCN_dpphy_dvihdmi_tuningset hdmiCLK8_tuningset; 1395 uint32_t reserved4[6];//reserve 2*sizeof(atom_DCN_dpphy_dvihdmi_tuningset) 1396 struct atom_DCN_dpphy_dp_tuningset rbr_tuningset; // rbr 1.62G dp tuning set 1397 struct atom_DCN_dpphy_dp_tuningset hbr_tuningset; //hbr 2.7G dp tuning set 1398 struct atom_DCN_dpphy_dp_tuningset hbr2_tuningset; //hbr2 5.4G dp turnig set 1399 struct atom_DCN_dpphy_dp_tuningset hbr3_tuningset; // HBR3 dp tuning set 1400 struct atom_DCN_dpphy_dp_tuningset edp_tunings; //edp tuning set 1401 uint32_t reserved5[28];//reserve 2*sizeof(atom_DCN_dpphy_dp_tuningset) 1402 struct atom_hdmi_retimer_redriver_set dp0_retimer_set; //for DP0 1403 struct atom_hdmi_retimer_redriver_set dp1_retimer_set; //for DP1 1404 struct atom_hdmi_retimer_redriver_set dp2_retimer_set; //for DP2 1405 struct atom_hdmi_retimer_redriver_set dp3_retimer_set; //for DP3 1406 uint32_t reserved6[30];// reserve size of(atom_camera_data) for camera_info 1407 uint32_t reserved7[32]; 1408 1409 }; 1410 1411 // system_config 1412 enum atom_system_vbiosmisc_def{ 1413 INTEGRATED_SYSTEM_INFO__GET_EDID_CALLBACK_FUNC_SUPPORT = 0x01, 1414 }; 1415 1416 1417 // gpucapinfo 1418 enum atom_system_gpucapinf_def{ 1419 SYS_INFO_GPUCAPS__ENABEL_DFS_BYPASS = 0x10, 1420 }; 1421 1422 //dpphy_override 1423 enum atom_sysinfo_dpphy_override_def{ 1424 ATOM_ENABLE_DVI_TUNINGSET = 0x01, 1425 ATOM_ENABLE_HDMI_TUNINGSET = 0x02, 1426 ATOM_ENABLE_HDMI6G_TUNINGSET = 0x04, 1427 ATOM_ENABLE_DP_TUNINGSET = 0x08, 1428 ATOM_ENABLE_DP_HBR3_TUNINGSET = 0x10, 1429 }; 1430 1431 //lvds_misc 1432 enum atom_sys_info_lvds_misc_def 1433 { 1434 SYS_INFO_LVDS_MISC_888_FPDI_MODE =0x01, 1435 SYS_INFO_LVDS_MISC_888_BPC_MODE =0x04, 1436 SYS_INFO_LVDS_MISC_OVERRIDE_EN =0x08, 1437 }; 1438 1439 1440 //memorytype DMI Type 17 offset 12h - Memory Type 1441 enum atom_dmi_t17_mem_type_def{ 1442 OtherMemType = 0x01, ///< Assign 01 to Other 1443 UnknownMemType, ///< Assign 02 to Unknown 1444 DramMemType, ///< Assign 03 to DRAM 1445 EdramMemType, ///< Assign 04 to EDRAM 1446 VramMemType, ///< Assign 05 to VRAM 1447 SramMemType, ///< Assign 06 to SRAM 1448 RamMemType, ///< Assign 07 to RAM 1449 RomMemType, ///< Assign 08 to ROM 1450 FlashMemType, ///< Assign 09 to Flash 1451 EepromMemType, ///< Assign 10 to EEPROM 1452 FepromMemType, ///< Assign 11 to FEPROM 1453 EpromMemType, ///< Assign 12 to EPROM 1454 CdramMemType, ///< Assign 13 to CDRAM 1455 ThreeDramMemType, ///< Assign 14 to 3DRAM 1456 SdramMemType, ///< Assign 15 to SDRAM 1457 SgramMemType, ///< Assign 16 to SGRAM 1458 RdramMemType, ///< Assign 17 to RDRAM 1459 DdrMemType, ///< Assign 18 to DDR 1460 Ddr2MemType, ///< Assign 19 to DDR2 1461 Ddr2FbdimmMemType, ///< Assign 20 to DDR2 FB-DIMM 1462 Ddr3MemType = 0x18, ///< Assign 24 to DDR3 1463 Fbd2MemType, ///< Assign 25 to FBD2 1464 Ddr4MemType, ///< Assign 26 to DDR4 1465 LpDdrMemType, ///< Assign 27 to LPDDR 1466 LpDdr2MemType, ///< Assign 28 to LPDDR2 1467 LpDdr3MemType, ///< Assign 29 to LPDDR3 1468 LpDdr4MemType, ///< Assign 30 to LPDDR4 1469 GDdr6MemType, ///< Assign 31 to GDDR6 1470 HbmMemType, ///< Assign 32 to HBM 1471 Hbm2MemType, ///< Assign 33 to HBM2 1472 Ddr5MemType, ///< Assign 34 to DDR5 1473 LpDdr5MemType, ///< Assign 35 to LPDDR5 1474 }; 1475 1476 1477 // this Table is used starting from NL/AM, used by SBIOS and pass the IntegratedSystemInfoTable/PowerPlayInfoTable/SystemCameraInfoTable 1478 struct atom_fusion_system_info_v4 1479 { 1480 struct atom_integrated_system_info_v1_11 sysinfo; // refer to ATOM_INTEGRATED_SYSTEM_INFO_V1_8 definition 1481 uint32_t powerplayinfo[256]; // Reserve 1024 bytes space for PowerPlayInfoTable 1482 }; 1483 1484 1485 /* 1486 *************************************************************************** 1487 Data Table gfx_info structure 1488 *************************************************************************** 1489 */ 1490 1491 struct atom_gfx_info_v2_2 1492 { 1493 struct atom_common_table_header table_header; 1494 uint8_t gfxip_min_ver; 1495 uint8_t gfxip_max_ver; 1496 uint8_t max_shader_engines; 1497 uint8_t max_tile_pipes; 1498 uint8_t max_cu_per_sh; 1499 uint8_t max_sh_per_se; 1500 uint8_t max_backends_per_se; 1501 uint8_t max_texture_channel_caches; 1502 uint32_t regaddr_cp_dma_src_addr; 1503 uint32_t regaddr_cp_dma_src_addr_hi; 1504 uint32_t regaddr_cp_dma_dst_addr; 1505 uint32_t regaddr_cp_dma_dst_addr_hi; 1506 uint32_t regaddr_cp_dma_command; 1507 uint32_t regaddr_cp_status; 1508 uint32_t regaddr_rlc_gpu_clock_32; 1509 uint32_t rlc_gpu_timer_refclk; 1510 }; 1511 1512 struct atom_gfx_info_v2_3 { 1513 struct atom_common_table_header table_header; 1514 uint8_t gfxip_min_ver; 1515 uint8_t gfxip_max_ver; 1516 uint8_t max_shader_engines; 1517 uint8_t max_tile_pipes; 1518 uint8_t max_cu_per_sh; 1519 uint8_t max_sh_per_se; 1520 uint8_t max_backends_per_se; 1521 uint8_t max_texture_channel_caches; 1522 uint32_t regaddr_cp_dma_src_addr; 1523 uint32_t regaddr_cp_dma_src_addr_hi; 1524 uint32_t regaddr_cp_dma_dst_addr; 1525 uint32_t regaddr_cp_dma_dst_addr_hi; 1526 uint32_t regaddr_cp_dma_command; 1527 uint32_t regaddr_cp_status; 1528 uint32_t regaddr_rlc_gpu_clock_32; 1529 uint32_t rlc_gpu_timer_refclk; 1530 uint8_t active_cu_per_sh; 1531 uint8_t active_rb_per_se; 1532 uint16_t gcgoldenoffset; 1533 uint32_t rm21_sram_vmin_value; 1534 }; 1535 1536 struct atom_gfx_info_v2_4 1537 { 1538 struct atom_common_table_header table_header; 1539 uint8_t gfxip_min_ver; 1540 uint8_t gfxip_max_ver; 1541 uint8_t max_shader_engines; 1542 uint8_t reserved; 1543 uint8_t max_cu_per_sh; 1544 uint8_t max_sh_per_se; 1545 uint8_t max_backends_per_se; 1546 uint8_t max_texture_channel_caches; 1547 uint32_t regaddr_cp_dma_src_addr; 1548 uint32_t regaddr_cp_dma_src_addr_hi; 1549 uint32_t regaddr_cp_dma_dst_addr; 1550 uint32_t regaddr_cp_dma_dst_addr_hi; 1551 uint32_t regaddr_cp_dma_command; 1552 uint32_t regaddr_cp_status; 1553 uint32_t regaddr_rlc_gpu_clock_32; 1554 uint32_t rlc_gpu_timer_refclk; 1555 uint8_t active_cu_per_sh; 1556 uint8_t active_rb_per_se; 1557 uint16_t gcgoldenoffset; 1558 uint16_t gc_num_gprs; 1559 uint16_t gc_gsprim_buff_depth; 1560 uint16_t gc_parameter_cache_depth; 1561 uint16_t gc_wave_size; 1562 uint16_t gc_max_waves_per_simd; 1563 uint16_t gc_lds_size; 1564 uint8_t gc_num_max_gs_thds; 1565 uint8_t gc_gs_table_depth; 1566 uint8_t gc_double_offchip_lds_buffer; 1567 uint8_t gc_max_scratch_slots_per_cu; 1568 uint32_t sram_rm_fuses_val; 1569 uint32_t sram_custom_rm_fuses_val; 1570 }; 1571 1572 struct atom_gfx_info_v2_7 { 1573 struct atom_common_table_header table_header; 1574 uint8_t gfxip_min_ver; 1575 uint8_t gfxip_max_ver; 1576 uint8_t max_shader_engines; 1577 uint8_t reserved; 1578 uint8_t max_cu_per_sh; 1579 uint8_t max_sh_per_se; 1580 uint8_t max_backends_per_se; 1581 uint8_t max_texture_channel_caches; 1582 uint32_t regaddr_cp_dma_src_addr; 1583 uint32_t regaddr_cp_dma_src_addr_hi; 1584 uint32_t regaddr_cp_dma_dst_addr; 1585 uint32_t regaddr_cp_dma_dst_addr_hi; 1586 uint32_t regaddr_cp_dma_command; 1587 uint32_t regaddr_cp_status; 1588 uint32_t regaddr_rlc_gpu_clock_32; 1589 uint32_t rlc_gpu_timer_refclk; 1590 uint8_t active_cu_per_sh; 1591 uint8_t active_rb_per_se; 1592 uint16_t gcgoldenoffset; 1593 uint16_t gc_num_gprs; 1594 uint16_t gc_gsprim_buff_depth; 1595 uint16_t gc_parameter_cache_depth; 1596 uint16_t gc_wave_size; 1597 uint16_t gc_max_waves_per_simd; 1598 uint16_t gc_lds_size; 1599 uint8_t gc_num_max_gs_thds; 1600 uint8_t gc_gs_table_depth; 1601 uint8_t gc_double_offchip_lds_buffer; 1602 uint8_t gc_max_scratch_slots_per_cu; 1603 uint32_t sram_rm_fuses_val; 1604 uint32_t sram_custom_rm_fuses_val; 1605 uint8_t cut_cu; 1606 uint8_t active_cu_total; 1607 uint8_t cu_reserved[2]; 1608 uint32_t gc_config; 1609 uint8_t inactive_cu_per_se[8]; 1610 uint32_t reserved2[6]; 1611 }; 1612 1613 /* 1614 *************************************************************************** 1615 Data Table smu_info structure 1616 *************************************************************************** 1617 */ 1618 struct atom_smu_info_v3_1 1619 { 1620 struct atom_common_table_header table_header; 1621 uint8_t smuip_min_ver; 1622 uint8_t smuip_max_ver; 1623 uint8_t smu_rsd1; 1624 uint8_t gpuclk_ss_mode; // enum of atom_spread_spectrum_mode 1625 uint16_t sclk_ss_percentage; 1626 uint16_t sclk_ss_rate_10hz; 1627 uint16_t gpuclk_ss_percentage; // in unit of 0.001% 1628 uint16_t gpuclk_ss_rate_10hz; 1629 uint32_t core_refclk_10khz; 1630 uint8_t ac_dc_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for AC/DC switching, =0xff means invalid 1631 uint8_t ac_dc_polarity; // GPIO polarity for AC/DC switching 1632 uint8_t vr0hot_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for VR0 HOT event, =0xff means invalid 1633 uint8_t vr0hot_polarity; // GPIO polarity for VR0 HOT event 1634 uint8_t vr1hot_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for VR1 HOT event , =0xff means invalid 1635 uint8_t vr1hot_polarity; // GPIO polarity for VR1 HOT event 1636 uint8_t fw_ctf_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for CTF, =0xff means invalid 1637 uint8_t fw_ctf_polarity; // GPIO polarity for CTF 1638 }; 1639 1640 struct atom_smu_info_v3_2 { 1641 struct atom_common_table_header table_header; 1642 uint8_t smuip_min_ver; 1643 uint8_t smuip_max_ver; 1644 uint8_t smu_rsd1; 1645 uint8_t gpuclk_ss_mode; 1646 uint16_t sclk_ss_percentage; 1647 uint16_t sclk_ss_rate_10hz; 1648 uint16_t gpuclk_ss_percentage; // in unit of 0.001% 1649 uint16_t gpuclk_ss_rate_10hz; 1650 uint32_t core_refclk_10khz; 1651 uint8_t ac_dc_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for AC/DC switching, =0xff means invalid 1652 uint8_t ac_dc_polarity; // GPIO polarity for AC/DC switching 1653 uint8_t vr0hot_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for VR0 HOT event, =0xff means invalid 1654 uint8_t vr0hot_polarity; // GPIO polarity for VR0 HOT event 1655 uint8_t vr1hot_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for VR1 HOT event , =0xff means invalid 1656 uint8_t vr1hot_polarity; // GPIO polarity for VR1 HOT event 1657 uint8_t fw_ctf_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for CTF, =0xff means invalid 1658 uint8_t fw_ctf_polarity; // GPIO polarity for CTF 1659 uint8_t pcc_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for PCC, =0xff means invalid 1660 uint8_t pcc_gpio_polarity; // GPIO polarity for CTF 1661 uint16_t smugoldenoffset; 1662 uint32_t gpupll_vco_freq_10khz; 1663 uint32_t bootup_smnclk_10khz; 1664 uint32_t bootup_socclk_10khz; 1665 uint32_t bootup_mp0clk_10khz; 1666 uint32_t bootup_mp1clk_10khz; 1667 uint32_t bootup_lclk_10khz; 1668 uint32_t bootup_dcefclk_10khz; 1669 uint32_t ctf_threshold_override_value; 1670 uint32_t reserved[5]; 1671 }; 1672 1673 struct atom_smu_info_v3_3 { 1674 struct atom_common_table_header table_header; 1675 uint8_t smuip_min_ver; 1676 uint8_t smuip_max_ver; 1677 uint8_t waflclk_ss_mode; 1678 uint8_t gpuclk_ss_mode; 1679 uint16_t sclk_ss_percentage; 1680 uint16_t sclk_ss_rate_10hz; 1681 uint16_t gpuclk_ss_percentage; // in unit of 0.001% 1682 uint16_t gpuclk_ss_rate_10hz; 1683 uint32_t core_refclk_10khz; 1684 uint8_t ac_dc_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for AC/DC switching, =0xff means invalid 1685 uint8_t ac_dc_polarity; // GPIO polarity for AC/DC switching 1686 uint8_t vr0hot_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for VR0 HOT event, =0xff means invalid 1687 uint8_t vr0hot_polarity; // GPIO polarity for VR0 HOT event 1688 uint8_t vr1hot_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for VR1 HOT event , =0xff means invalid 1689 uint8_t vr1hot_polarity; // GPIO polarity for VR1 HOT event 1690 uint8_t fw_ctf_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for CTF, =0xff means invalid 1691 uint8_t fw_ctf_polarity; // GPIO polarity for CTF 1692 uint8_t pcc_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for PCC, =0xff means invalid 1693 uint8_t pcc_gpio_polarity; // GPIO polarity for CTF 1694 uint16_t smugoldenoffset; 1695 uint32_t gpupll_vco_freq_10khz; 1696 uint32_t bootup_smnclk_10khz; 1697 uint32_t bootup_socclk_10khz; 1698 uint32_t bootup_mp0clk_10khz; 1699 uint32_t bootup_mp1clk_10khz; 1700 uint32_t bootup_lclk_10khz; 1701 uint32_t bootup_dcefclk_10khz; 1702 uint32_t ctf_threshold_override_value; 1703 uint32_t syspll3_0_vco_freq_10khz; 1704 uint32_t syspll3_1_vco_freq_10khz; 1705 uint32_t bootup_fclk_10khz; 1706 uint32_t bootup_waflclk_10khz; 1707 uint32_t smu_info_caps; 1708 uint16_t waflclk_ss_percentage; // in unit of 0.001% 1709 uint16_t smuinitoffset; 1710 uint32_t reserved; 1711 }; 1712 1713 /* 1714 *************************************************************************** 1715 Data Table smc_dpm_info structure 1716 *************************************************************************** 1717 */ 1718 struct atom_smc_dpm_info_v4_1 1719 { 1720 struct atom_common_table_header table_header; 1721 uint8_t liquid1_i2c_address; 1722 uint8_t liquid2_i2c_address; 1723 uint8_t vr_i2c_address; 1724 uint8_t plx_i2c_address; 1725 1726 uint8_t liquid_i2c_linescl; 1727 uint8_t liquid_i2c_linesda; 1728 uint8_t vr_i2c_linescl; 1729 uint8_t vr_i2c_linesda; 1730 1731 uint8_t plx_i2c_linescl; 1732 uint8_t plx_i2c_linesda; 1733 uint8_t vrsensorpresent; 1734 uint8_t liquidsensorpresent; 1735 1736 uint16_t maxvoltagestepgfx; 1737 uint16_t maxvoltagestepsoc; 1738 1739 uint8_t vddgfxvrmapping; 1740 uint8_t vddsocvrmapping; 1741 uint8_t vddmem0vrmapping; 1742 uint8_t vddmem1vrmapping; 1743 1744 uint8_t gfxulvphasesheddingmask; 1745 uint8_t soculvphasesheddingmask; 1746 uint8_t padding8_v[2]; 1747 1748 uint16_t gfxmaxcurrent; 1749 uint8_t gfxoffset; 1750 uint8_t padding_telemetrygfx; 1751 1752 uint16_t socmaxcurrent; 1753 uint8_t socoffset; 1754 uint8_t padding_telemetrysoc; 1755 1756 uint16_t mem0maxcurrent; 1757 uint8_t mem0offset; 1758 uint8_t padding_telemetrymem0; 1759 1760 uint16_t mem1maxcurrent; 1761 uint8_t mem1offset; 1762 uint8_t padding_telemetrymem1; 1763 1764 uint8_t acdcgpio; 1765 uint8_t acdcpolarity; 1766 uint8_t vr0hotgpio; 1767 uint8_t vr0hotpolarity; 1768 1769 uint8_t vr1hotgpio; 1770 uint8_t vr1hotpolarity; 1771 uint8_t padding1; 1772 uint8_t padding2; 1773 1774 uint8_t ledpin0; 1775 uint8_t ledpin1; 1776 uint8_t ledpin2; 1777 uint8_t padding8_4; 1778 1779 uint8_t pllgfxclkspreadenabled; 1780 uint8_t pllgfxclkspreadpercent; 1781 uint16_t pllgfxclkspreadfreq; 1782 1783 uint8_t uclkspreadenabled; 1784 uint8_t uclkspreadpercent; 1785 uint16_t uclkspreadfreq; 1786 1787 uint8_t socclkspreadenabled; 1788 uint8_t socclkspreadpercent; 1789 uint16_t socclkspreadfreq; 1790 1791 uint8_t acggfxclkspreadenabled; 1792 uint8_t acggfxclkspreadpercent; 1793 uint16_t acggfxclkspreadfreq; 1794 1795 uint8_t Vr2_I2C_address; 1796 uint8_t padding_vr2[3]; 1797 1798 uint32_t boardreserved[9]; 1799 }; 1800 1801 /* 1802 *************************************************************************** 1803 Data Table smc_dpm_info structure 1804 *************************************************************************** 1805 */ 1806 struct atom_smc_dpm_info_v4_3 1807 { 1808 struct atom_common_table_header table_header; 1809 uint8_t liquid1_i2c_address; 1810 uint8_t liquid2_i2c_address; 1811 uint8_t vr_i2c_address; 1812 uint8_t plx_i2c_address; 1813 1814 uint8_t liquid_i2c_linescl; 1815 uint8_t liquid_i2c_linesda; 1816 uint8_t vr_i2c_linescl; 1817 uint8_t vr_i2c_linesda; 1818 1819 uint8_t plx_i2c_linescl; 1820 uint8_t plx_i2c_linesda; 1821 uint8_t vrsensorpresent; 1822 uint8_t liquidsensorpresent; 1823 1824 uint16_t maxvoltagestepgfx; 1825 uint16_t maxvoltagestepsoc; 1826 1827 uint8_t vddgfxvrmapping; 1828 uint8_t vddsocvrmapping; 1829 uint8_t vddmem0vrmapping; 1830 uint8_t vddmem1vrmapping; 1831 1832 uint8_t gfxulvphasesheddingmask; 1833 uint8_t soculvphasesheddingmask; 1834 uint8_t externalsensorpresent; 1835 uint8_t padding8_v; 1836 1837 uint16_t gfxmaxcurrent; 1838 uint8_t gfxoffset; 1839 uint8_t padding_telemetrygfx; 1840 1841 uint16_t socmaxcurrent; 1842 uint8_t socoffset; 1843 uint8_t padding_telemetrysoc; 1844 1845 uint16_t mem0maxcurrent; 1846 uint8_t mem0offset; 1847 uint8_t padding_telemetrymem0; 1848 1849 uint16_t mem1maxcurrent; 1850 uint8_t mem1offset; 1851 uint8_t padding_telemetrymem1; 1852 1853 uint8_t acdcgpio; 1854 uint8_t acdcpolarity; 1855 uint8_t vr0hotgpio; 1856 uint8_t vr0hotpolarity; 1857 1858 uint8_t vr1hotgpio; 1859 uint8_t vr1hotpolarity; 1860 uint8_t padding1; 1861 uint8_t padding2; 1862 1863 uint8_t ledpin0; 1864 uint8_t ledpin1; 1865 uint8_t ledpin2; 1866 uint8_t padding8_4; 1867 1868 uint8_t pllgfxclkspreadenabled; 1869 uint8_t pllgfxclkspreadpercent; 1870 uint16_t pllgfxclkspreadfreq; 1871 1872 uint8_t uclkspreadenabled; 1873 uint8_t uclkspreadpercent; 1874 uint16_t uclkspreadfreq; 1875 1876 uint8_t fclkspreadenabled; 1877 uint8_t fclkspreadpercent; 1878 uint16_t fclkspreadfreq; 1879 1880 uint8_t fllgfxclkspreadenabled; 1881 uint8_t fllgfxclkspreadpercent; 1882 uint16_t fllgfxclkspreadfreq; 1883 1884 uint32_t boardreserved[10]; 1885 }; 1886 1887 struct smudpm_i2ccontrollerconfig_t { 1888 uint32_t enabled; 1889 uint32_t slaveaddress; 1890 uint32_t controllerport; 1891 uint32_t controllername; 1892 uint32_t thermalthrottler; 1893 uint32_t i2cprotocol; 1894 uint32_t i2cspeed; 1895 }; 1896 1897 struct atom_smc_dpm_info_v4_4 1898 { 1899 struct atom_common_table_header table_header; 1900 uint32_t i2c_padding[3]; 1901 1902 uint16_t maxvoltagestepgfx; 1903 uint16_t maxvoltagestepsoc; 1904 1905 uint8_t vddgfxvrmapping; 1906 uint8_t vddsocvrmapping; 1907 uint8_t vddmem0vrmapping; 1908 uint8_t vddmem1vrmapping; 1909 1910 uint8_t gfxulvphasesheddingmask; 1911 uint8_t soculvphasesheddingmask; 1912 uint8_t externalsensorpresent; 1913 uint8_t padding8_v; 1914 1915 uint16_t gfxmaxcurrent; 1916 uint8_t gfxoffset; 1917 uint8_t padding_telemetrygfx; 1918 1919 uint16_t socmaxcurrent; 1920 uint8_t socoffset; 1921 uint8_t padding_telemetrysoc; 1922 1923 uint16_t mem0maxcurrent; 1924 uint8_t mem0offset; 1925 uint8_t padding_telemetrymem0; 1926 1927 uint16_t mem1maxcurrent; 1928 uint8_t mem1offset; 1929 uint8_t padding_telemetrymem1; 1930 1931 1932 uint8_t acdcgpio; 1933 uint8_t acdcpolarity; 1934 uint8_t vr0hotgpio; 1935 uint8_t vr0hotpolarity; 1936 1937 uint8_t vr1hotgpio; 1938 uint8_t vr1hotpolarity; 1939 uint8_t padding1; 1940 uint8_t padding2; 1941 1942 1943 uint8_t ledpin0; 1944 uint8_t ledpin1; 1945 uint8_t ledpin2; 1946 uint8_t padding8_4; 1947 1948 1949 uint8_t pllgfxclkspreadenabled; 1950 uint8_t pllgfxclkspreadpercent; 1951 uint16_t pllgfxclkspreadfreq; 1952 1953 1954 uint8_t uclkspreadenabled; 1955 uint8_t uclkspreadpercent; 1956 uint16_t uclkspreadfreq; 1957 1958 1959 uint8_t fclkspreadenabled; 1960 uint8_t fclkspreadpercent; 1961 uint16_t fclkspreadfreq; 1962 1963 1964 uint8_t fllgfxclkspreadenabled; 1965 uint8_t fllgfxclkspreadpercent; 1966 uint16_t fllgfxclkspreadfreq; 1967 1968 1969 struct smudpm_i2ccontrollerconfig_t i2ccontrollers[7]; 1970 1971 1972 uint32_t boardreserved[10]; 1973 }; 1974 1975 enum smudpm_v4_5_i2ccontrollername_e{ 1976 SMC_V4_5_I2C_CONTROLLER_NAME_VR_GFX = 0, 1977 SMC_V4_5_I2C_CONTROLLER_NAME_VR_SOC, 1978 SMC_V4_5_I2C_CONTROLLER_NAME_VR_VDDCI, 1979 SMC_V4_5_I2C_CONTROLLER_NAME_VR_MVDD, 1980 SMC_V4_5_I2C_CONTROLLER_NAME_LIQUID0, 1981 SMC_V4_5_I2C_CONTROLLER_NAME_LIQUID1, 1982 SMC_V4_5_I2C_CONTROLLER_NAME_PLX, 1983 SMC_V4_5_I2C_CONTROLLER_NAME_SPARE, 1984 SMC_V4_5_I2C_CONTROLLER_NAME_COUNT, 1985 }; 1986 1987 enum smudpm_v4_5_i2ccontrollerthrottler_e{ 1988 SMC_V4_5_I2C_CONTROLLER_THROTTLER_TYPE_NONE = 0, 1989 SMC_V4_5_I2C_CONTROLLER_THROTTLER_VR_GFX, 1990 SMC_V4_5_I2C_CONTROLLER_THROTTLER_VR_SOC, 1991 SMC_V4_5_I2C_CONTROLLER_THROTTLER_VR_VDDCI, 1992 SMC_V4_5_I2C_CONTROLLER_THROTTLER_VR_MVDD, 1993 SMC_V4_5_I2C_CONTROLLER_THROTTLER_LIQUID0, 1994 SMC_V4_5_I2C_CONTROLLER_THROTTLER_LIQUID1, 1995 SMC_V4_5_I2C_CONTROLLER_THROTTLER_PLX, 1996 SMC_V4_5_I2C_CONTROLLER_THROTTLER_COUNT, 1997 }; 1998 1999 enum smudpm_v4_5_i2ccontrollerprotocol_e{ 2000 SMC_V4_5_I2C_CONTROLLER_PROTOCOL_VR_0, 2001 SMC_V4_5_I2C_CONTROLLER_PROTOCOL_VR_1, 2002 SMC_V4_5_I2C_CONTROLLER_PROTOCOL_TMP_0, 2003 SMC_V4_5_I2C_CONTROLLER_PROTOCOL_TMP_1, 2004 SMC_V4_5_I2C_CONTROLLER_PROTOCOL_SPARE_0, 2005 SMC_V4_5_I2C_CONTROLLER_PROTOCOL_SPARE_1, 2006 SMC_V4_5_I2C_CONTROLLER_PROTOCOL_COUNT, 2007 }; 2008 2009 struct smudpm_i2c_controller_config_v2 2010 { 2011 uint8_t Enabled; 2012 uint8_t Speed; 2013 uint8_t Padding[2]; 2014 uint32_t SlaveAddress; 2015 uint8_t ControllerPort; 2016 uint8_t ControllerName; 2017 uint8_t ThermalThrotter; 2018 uint8_t I2cProtocol; 2019 }; 2020 2021 struct atom_smc_dpm_info_v4_5 2022 { 2023 struct atom_common_table_header table_header; 2024 // SECTION: BOARD PARAMETERS 2025 // I2C Control 2026 struct smudpm_i2c_controller_config_v2 I2cControllers[8]; 2027 2028 // SVI2 Board Parameters 2029 uint16_t MaxVoltageStepGfx; // In mV(Q2) Max voltage step that SMU will request. Multiple steps are taken if voltage change exceeds this value. 2030 uint16_t MaxVoltageStepSoc; // In mV(Q2) Max voltage step that SMU will request. Multiple steps are taken if voltage change exceeds this value. 2031 2032 uint8_t VddGfxVrMapping; // Use VR_MAPPING* bitfields 2033 uint8_t VddSocVrMapping; // Use VR_MAPPING* bitfields 2034 uint8_t VddMem0VrMapping; // Use VR_MAPPING* bitfields 2035 uint8_t VddMem1VrMapping; // Use VR_MAPPING* bitfields 2036 2037 uint8_t GfxUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode 2038 uint8_t SocUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode 2039 uint8_t ExternalSensorPresent; // External RDI connected to TMON (aka TEMP IN) 2040 uint8_t Padding8_V; 2041 2042 // Telemetry Settings 2043 uint16_t GfxMaxCurrent; // in Amps 2044 uint8_t GfxOffset; // in Amps 2045 uint8_t Padding_TelemetryGfx; 2046 uint16_t SocMaxCurrent; // in Amps 2047 uint8_t SocOffset; // in Amps 2048 uint8_t Padding_TelemetrySoc; 2049 2050 uint16_t Mem0MaxCurrent; // in Amps 2051 uint8_t Mem0Offset; // in Amps 2052 uint8_t Padding_TelemetryMem0; 2053 2054 uint16_t Mem1MaxCurrent; // in Amps 2055 uint8_t Mem1Offset; // in Amps 2056 uint8_t Padding_TelemetryMem1; 2057 2058 // GPIO Settings 2059 uint8_t AcDcGpio; // GPIO pin configured for AC/DC switching 2060 uint8_t AcDcPolarity; // GPIO polarity for AC/DC switching 2061 uint8_t VR0HotGpio; // GPIO pin configured for VR0 HOT event 2062 uint8_t VR0HotPolarity; // GPIO polarity for VR0 HOT event 2063 2064 uint8_t VR1HotGpio; // GPIO pin configured for VR1 HOT event 2065 uint8_t VR1HotPolarity; // GPIO polarity for VR1 HOT event 2066 uint8_t GthrGpio; // GPIO pin configured for GTHR Event 2067 uint8_t GthrPolarity; // replace GPIO polarity for GTHR 2068 2069 // LED Display Settings 2070 uint8_t LedPin0; // GPIO number for LedPin[0] 2071 uint8_t LedPin1; // GPIO number for LedPin[1] 2072 uint8_t LedPin2; // GPIO number for LedPin[2] 2073 uint8_t padding8_4; 2074 2075 // GFXCLK PLL Spread Spectrum 2076 uint8_t PllGfxclkSpreadEnabled; // on or off 2077 uint8_t PllGfxclkSpreadPercent; // Q4.4 2078 uint16_t PllGfxclkSpreadFreq; // kHz 2079 2080 // GFXCLK DFLL Spread Spectrum 2081 uint8_t DfllGfxclkSpreadEnabled; // on or off 2082 uint8_t DfllGfxclkSpreadPercent; // Q4.4 2083 uint16_t DfllGfxclkSpreadFreq; // kHz 2084 2085 // UCLK Spread Spectrum 2086 uint8_t UclkSpreadEnabled; // on or off 2087 uint8_t UclkSpreadPercent; // Q4.4 2088 uint16_t UclkSpreadFreq; // kHz 2089 2090 // SOCCLK Spread Spectrum 2091 uint8_t SoclkSpreadEnabled; // on or off 2092 uint8_t SocclkSpreadPercent; // Q4.4 2093 uint16_t SocclkSpreadFreq; // kHz 2094 2095 // Total board power 2096 uint16_t TotalBoardPower; //Only needed for TCP Estimated case, where TCP = TGP+Total Board Power 2097 uint16_t BoardPadding; 2098 2099 // Mvdd Svi2 Div Ratio Setting 2100 uint32_t MvddRatio; // This is used for MVDD Vid workaround. It has 16 fractional bits (Q16.16) 2101 2102 uint32_t BoardReserved[9]; 2103 2104 }; 2105 2106 struct atom_smc_dpm_info_v4_6 2107 { 2108 struct atom_common_table_header table_header; 2109 // section: board parameters 2110 uint32_t i2c_padding[3]; // old i2c control are moved to new area 2111 2112 uint16_t maxvoltagestepgfx; // in mv(q2) max voltage step that smu will request. multiple steps are taken if voltage change exceeds this value. 2113 uint16_t maxvoltagestepsoc; // in mv(q2) max voltage step that smu will request. multiple steps are taken if voltage change exceeds this value. 2114 2115 uint8_t vddgfxvrmapping; // use vr_mapping* bitfields 2116 uint8_t vddsocvrmapping; // use vr_mapping* bitfields 2117 uint8_t vddmemvrmapping; // use vr_mapping* bitfields 2118 uint8_t boardvrmapping; // use vr_mapping* bitfields 2119 2120 uint8_t gfxulvphasesheddingmask; // set this to 1 to set psi0/1 to 1 in ulv mode 2121 uint8_t externalsensorpresent; // external rdi connected to tmon (aka temp in) 2122 uint8_t padding8_v[2]; 2123 2124 // telemetry settings 2125 uint16_t gfxmaxcurrent; // in amps 2126 uint8_t gfxoffset; // in amps 2127 uint8_t padding_telemetrygfx; 2128 2129 uint16_t socmaxcurrent; // in amps 2130 uint8_t socoffset; // in amps 2131 uint8_t padding_telemetrysoc; 2132 2133 uint16_t memmaxcurrent; // in amps 2134 uint8_t memoffset; // in amps 2135 uint8_t padding_telemetrymem; 2136 2137 uint16_t boardmaxcurrent; // in amps 2138 uint8_t boardoffset; // in amps 2139 uint8_t padding_telemetryboardinput; 2140 2141 // gpio settings 2142 uint8_t vr0hotgpio; // gpio pin configured for vr0 hot event 2143 uint8_t vr0hotpolarity; // gpio polarity for vr0 hot event 2144 uint8_t vr1hotgpio; // gpio pin configured for vr1 hot event 2145 uint8_t vr1hotpolarity; // gpio polarity for vr1 hot event 2146 2147 // gfxclk pll spread spectrum 2148 uint8_t pllgfxclkspreadenabled; // on or off 2149 uint8_t pllgfxclkspreadpercent; // q4.4 2150 uint16_t pllgfxclkspreadfreq; // khz 2151 2152 // uclk spread spectrum 2153 uint8_t uclkspreadenabled; // on or off 2154 uint8_t uclkspreadpercent; // q4.4 2155 uint16_t uclkspreadfreq; // khz 2156 2157 // fclk spread spectrum 2158 uint8_t fclkspreadenabled; // on or off 2159 uint8_t fclkspreadpercent; // q4.4 2160 uint16_t fclkspreadfreq; // khz 2161 2162 2163 // gfxclk fll spread spectrum 2164 uint8_t fllgfxclkspreadenabled; // on or off 2165 uint8_t fllgfxclkspreadpercent; // q4.4 2166 uint16_t fllgfxclkspreadfreq; // khz 2167 2168 // i2c controller structure 2169 struct smudpm_i2c_controller_config_v2 i2ccontrollers[8]; 2170 2171 // memory section 2172 uint32_t memorychannelenabled; // for dram use only, max 32 channels enabled bit mask. 2173 2174 uint8_t drambitwidth; // for dram use only. see dram bit width type defines 2175 uint8_t paddingmem[3]; 2176 2177 // total board power 2178 uint16_t totalboardpower; //only needed for tcp estimated case, where tcp = tgp+total board power 2179 uint16_t boardpadding; 2180 2181 // section: xgmi training 2182 uint8_t xgmilinkspeed[4]; 2183 uint8_t xgmilinkwidth[4]; 2184 2185 uint16_t xgmifclkfreq[4]; 2186 uint16_t xgmisocvoltage[4]; 2187 2188 // reserved 2189 uint32_t boardreserved[10]; 2190 }; 2191 2192 struct atom_smc_dpm_info_v4_7 2193 { 2194 struct atom_common_table_header table_header; 2195 // SECTION: BOARD PARAMETERS 2196 // I2C Control 2197 struct smudpm_i2c_controller_config_v2 I2cControllers[8]; 2198 2199 // SVI2 Board Parameters 2200 uint16_t MaxVoltageStepGfx; // In mV(Q2) Max voltage step that SMU will request. Multiple steps are taken if voltage change exceeds this value. 2201 uint16_t MaxVoltageStepSoc; // In mV(Q2) Max voltage step that SMU will request. Multiple steps are taken if voltage change exceeds this value. 2202 2203 uint8_t VddGfxVrMapping; // Use VR_MAPPING* bitfields 2204 uint8_t VddSocVrMapping; // Use VR_MAPPING* bitfields 2205 uint8_t VddMem0VrMapping; // Use VR_MAPPING* bitfields 2206 uint8_t VddMem1VrMapping; // Use VR_MAPPING* bitfields 2207 2208 uint8_t GfxUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode 2209 uint8_t SocUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode 2210 uint8_t ExternalSensorPresent; // External RDI connected to TMON (aka TEMP IN) 2211 uint8_t Padding8_V; 2212 2213 // Telemetry Settings 2214 uint16_t GfxMaxCurrent; // in Amps 2215 uint8_t GfxOffset; // in Amps 2216 uint8_t Padding_TelemetryGfx; 2217 uint16_t SocMaxCurrent; // in Amps 2218 uint8_t SocOffset; // in Amps 2219 uint8_t Padding_TelemetrySoc; 2220 2221 uint16_t Mem0MaxCurrent; // in Amps 2222 uint8_t Mem0Offset; // in Amps 2223 uint8_t Padding_TelemetryMem0; 2224 2225 uint16_t Mem1MaxCurrent; // in Amps 2226 uint8_t Mem1Offset; // in Amps 2227 uint8_t Padding_TelemetryMem1; 2228 2229 // GPIO Settings 2230 uint8_t AcDcGpio; // GPIO pin configured for AC/DC switching 2231 uint8_t AcDcPolarity; // GPIO polarity for AC/DC switching 2232 uint8_t VR0HotGpio; // GPIO pin configured for VR0 HOT event 2233 uint8_t VR0HotPolarity; // GPIO polarity for VR0 HOT event 2234 2235 uint8_t VR1HotGpio; // GPIO pin configured for VR1 HOT event 2236 uint8_t VR1HotPolarity; // GPIO polarity for VR1 HOT event 2237 uint8_t GthrGpio; // GPIO pin configured for GTHR Event 2238 uint8_t GthrPolarity; // replace GPIO polarity for GTHR 2239 2240 // LED Display Settings 2241 uint8_t LedPin0; // GPIO number for LedPin[0] 2242 uint8_t LedPin1; // GPIO number for LedPin[1] 2243 uint8_t LedPin2; // GPIO number for LedPin[2] 2244 uint8_t padding8_4; 2245 2246 // GFXCLK PLL Spread Spectrum 2247 uint8_t PllGfxclkSpreadEnabled; // on or off 2248 uint8_t PllGfxclkSpreadPercent; // Q4.4 2249 uint16_t PllGfxclkSpreadFreq; // kHz 2250 2251 // GFXCLK DFLL Spread Spectrum 2252 uint8_t DfllGfxclkSpreadEnabled; // on or off 2253 uint8_t DfllGfxclkSpreadPercent; // Q4.4 2254 uint16_t DfllGfxclkSpreadFreq; // kHz 2255 2256 // UCLK Spread Spectrum 2257 uint8_t UclkSpreadEnabled; // on or off 2258 uint8_t UclkSpreadPercent; // Q4.4 2259 uint16_t UclkSpreadFreq; // kHz 2260 2261 // SOCCLK Spread Spectrum 2262 uint8_t SoclkSpreadEnabled; // on or off 2263 uint8_t SocclkSpreadPercent; // Q4.4 2264 uint16_t SocclkSpreadFreq; // kHz 2265 2266 // Total board power 2267 uint16_t TotalBoardPower; //Only needed for TCP Estimated case, where TCP = TGP+Total Board Power 2268 uint16_t BoardPadding; 2269 2270 // Mvdd Svi2 Div Ratio Setting 2271 uint32_t MvddRatio; // This is used for MVDD Vid workaround. It has 16 fractional bits (Q16.16) 2272 2273 // GPIO pins for I2C communications with 2nd controller for Input Telemetry Sequence 2274 uint8_t GpioI2cScl; // Serial Clock 2275 uint8_t GpioI2cSda; // Serial Data 2276 uint16_t GpioPadding; 2277 2278 // Additional LED Display Settings 2279 uint8_t LedPin3; // GPIO number for LedPin[3] - PCIE GEN Speed 2280 uint8_t LedPin4; // GPIO number for LedPin[4] - PMFW Error Status 2281 uint16_t LedEnableMask; 2282 2283 // Power Limit Scalars 2284 uint8_t PowerLimitScalar[4]; //[PPT_THROTTLER_COUNT] 2285 2286 uint8_t MvddUlvPhaseSheddingMask; 2287 uint8_t VddciUlvPhaseSheddingMask; 2288 uint8_t Padding8_Psi1; 2289 uint8_t Padding8_Psi2; 2290 2291 uint32_t BoardReserved[5]; 2292 }; 2293 2294 struct smudpm_i2c_controller_config_v3 2295 { 2296 uint8_t Enabled; 2297 uint8_t Speed; 2298 uint8_t SlaveAddress; 2299 uint8_t ControllerPort; 2300 uint8_t ControllerName; 2301 uint8_t ThermalThrotter; 2302 uint8_t I2cProtocol; 2303 uint8_t PaddingConfig; 2304 }; 2305 2306 struct atom_smc_dpm_info_v4_9 2307 { 2308 struct atom_common_table_header table_header; 2309 2310 //SECTION: Gaming Clocks 2311 //uint32_t GamingClk[6]; 2312 2313 // SECTION: I2C Control 2314 struct smudpm_i2c_controller_config_v3 I2cControllers[16]; 2315 2316 uint8_t GpioScl; // GPIO Number for SCL Line, used only for CKSVII2C1 2317 uint8_t GpioSda; // GPIO Number for SDA Line, used only for CKSVII2C1 2318 uint8_t FchUsbPdSlaveAddr; //For requesting USB PD controller S-states via FCH I2C when entering PME turn off 2319 uint8_t I2cSpare; 2320 2321 // SECTION: SVI2 Board Parameters 2322 uint8_t VddGfxVrMapping; // Use VR_MAPPING* bitfields 2323 uint8_t VddSocVrMapping; // Use VR_MAPPING* bitfields 2324 uint8_t VddMem0VrMapping; // Use VR_MAPPING* bitfields 2325 uint8_t VddMem1VrMapping; // Use VR_MAPPING* bitfields 2326 2327 uint8_t GfxUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode 2328 uint8_t SocUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode 2329 uint8_t VddciUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode 2330 uint8_t MvddUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode 2331 2332 // SECTION: Telemetry Settings 2333 uint16_t GfxMaxCurrent; // in Amps 2334 uint8_t GfxOffset; // in Amps 2335 uint8_t Padding_TelemetryGfx; 2336 2337 uint16_t SocMaxCurrent; // in Amps 2338 uint8_t SocOffset; // in Amps 2339 uint8_t Padding_TelemetrySoc; 2340 2341 uint16_t Mem0MaxCurrent; // in Amps 2342 uint8_t Mem0Offset; // in Amps 2343 uint8_t Padding_TelemetryMem0; 2344 2345 uint16_t Mem1MaxCurrent; // in Amps 2346 uint8_t Mem1Offset; // in Amps 2347 uint8_t Padding_TelemetryMem1; 2348 2349 uint32_t MvddRatio; // This is used for MVDD Svi2 Div Ratio workaround. It has 16 fractional bits (Q16.16) 2350 2351 // SECTION: GPIO Settings 2352 uint8_t AcDcGpio; // GPIO pin configured for AC/DC switching 2353 uint8_t AcDcPolarity; // GPIO polarity for AC/DC switching 2354 uint8_t VR0HotGpio; // GPIO pin configured for VR0 HOT event 2355 uint8_t VR0HotPolarity; // GPIO polarity for VR0 HOT event 2356 2357 uint8_t VR1HotGpio; // GPIO pin configured for VR1 HOT event 2358 uint8_t VR1HotPolarity; // GPIO polarity for VR1 HOT event 2359 uint8_t GthrGpio; // GPIO pin configured for GTHR Event 2360 uint8_t GthrPolarity; // replace GPIO polarity for GTHR 2361 2362 // LED Display Settings 2363 uint8_t LedPin0; // GPIO number for LedPin[0] 2364 uint8_t LedPin1; // GPIO number for LedPin[1] 2365 uint8_t LedPin2; // GPIO number for LedPin[2] 2366 uint8_t LedEnableMask; 2367 2368 uint8_t LedPcie; // GPIO number for PCIE results 2369 uint8_t LedError; // GPIO number for Error Cases 2370 uint8_t LedSpare1[2]; 2371 2372 // SECTION: Clock Spread Spectrum 2373 2374 // GFXCLK PLL Spread Spectrum 2375 uint8_t PllGfxclkSpreadEnabled; // on or off 2376 uint8_t PllGfxclkSpreadPercent; // Q4.4 2377 uint16_t PllGfxclkSpreadFreq; // kHz 2378 2379 // GFXCLK DFLL Spread Spectrum 2380 uint8_t DfllGfxclkSpreadEnabled; // on or off 2381 uint8_t DfllGfxclkSpreadPercent; // Q4.4 2382 uint16_t DfllGfxclkSpreadFreq; // kHz 2383 2384 // UCLK Spread Spectrum 2385 uint8_t UclkSpreadEnabled; // on or off 2386 uint8_t UclkSpreadPercent; // Q4.4 2387 uint16_t UclkSpreadFreq; // kHz 2388 2389 // FCLK Spread Spectrum 2390 uint8_t FclkSpreadEnabled; // on or off 2391 uint8_t FclkSpreadPercent; // Q4.4 2392 uint16_t FclkSpreadFreq; // kHz 2393 2394 // Section: Memory Config 2395 uint32_t MemoryChannelEnabled; // For DRAM use only, Max 32 channels enabled bit mask. 2396 2397 uint8_t DramBitWidth; // For DRAM use only. See Dram Bit width type defines 2398 uint8_t PaddingMem1[3]; 2399 2400 // Section: Total Board Power 2401 uint16_t TotalBoardPower; //Only needed for TCP Estimated case, where TCP = TGP+Total Board Power 2402 uint16_t BoardPowerPadding; 2403 2404 // SECTION: XGMI Training 2405 uint8_t XgmiLinkSpeed [4]; 2406 uint8_t XgmiLinkWidth [4]; 2407 2408 uint16_t XgmiFclkFreq [4]; 2409 uint16_t XgmiSocVoltage [4]; 2410 2411 // SECTION: Board Reserved 2412 2413 uint32_t BoardReserved[16]; 2414 2415 }; 2416 2417 struct atom_smc_dpm_info_v4_10 2418 { 2419 struct atom_common_table_header table_header; 2420 2421 // SECTION: BOARD PARAMETERS 2422 // Telemetry Settings 2423 uint16_t GfxMaxCurrent; // in Amps 2424 uint8_t GfxOffset; // in Amps 2425 uint8_t Padding_TelemetryGfx; 2426 2427 uint16_t SocMaxCurrent; // in Amps 2428 uint8_t SocOffset; // in Amps 2429 uint8_t Padding_TelemetrySoc; 2430 2431 uint16_t MemMaxCurrent; // in Amps 2432 uint8_t MemOffset; // in Amps 2433 uint8_t Padding_TelemetryMem; 2434 2435 uint16_t BoardMaxCurrent; // in Amps 2436 uint8_t BoardOffset; // in Amps 2437 uint8_t Padding_TelemetryBoardInput; 2438 2439 // Platform input telemetry voltage coefficient 2440 uint32_t BoardVoltageCoeffA; // decode by /1000 2441 uint32_t BoardVoltageCoeffB; // decode by /1000 2442 2443 // GPIO Settings 2444 uint8_t VR0HotGpio; // GPIO pin configured for VR0 HOT event 2445 uint8_t VR0HotPolarity; // GPIO polarity for VR0 HOT event 2446 uint8_t VR1HotGpio; // GPIO pin configured for VR1 HOT event 2447 uint8_t VR1HotPolarity; // GPIO polarity for VR1 HOT event 2448 2449 // UCLK Spread Spectrum 2450 uint8_t UclkSpreadEnabled; // on or off 2451 uint8_t UclkSpreadPercent; // Q4.4 2452 uint16_t UclkSpreadFreq; // kHz 2453 2454 // FCLK Spread Spectrum 2455 uint8_t FclkSpreadEnabled; // on or off 2456 uint8_t FclkSpreadPercent; // Q4.4 2457 uint16_t FclkSpreadFreq; // kHz 2458 2459 // I2C Controller Structure 2460 struct smudpm_i2c_controller_config_v3 I2cControllers[8]; 2461 2462 // GPIO pins for I2C communications with 2nd controller for Input Telemetry Sequence 2463 uint8_t GpioI2cScl; // Serial Clock 2464 uint8_t GpioI2cSda; // Serial Data 2465 uint16_t spare5; 2466 2467 uint32_t reserved[16]; 2468 }; 2469 2470 /* 2471 *************************************************************************** 2472 Data Table asic_profiling_info structure 2473 *************************************************************************** 2474 */ 2475 struct atom_asic_profiling_info_v4_1 2476 { 2477 struct atom_common_table_header table_header; 2478 uint32_t maxvddc; 2479 uint32_t minvddc; 2480 uint32_t avfs_meannsigma_acontant0; 2481 uint32_t avfs_meannsigma_acontant1; 2482 uint32_t avfs_meannsigma_acontant2; 2483 uint16_t avfs_meannsigma_dc_tol_sigma; 2484 uint16_t avfs_meannsigma_platform_mean; 2485 uint16_t avfs_meannsigma_platform_sigma; 2486 uint32_t gb_vdroop_table_cksoff_a0; 2487 uint32_t gb_vdroop_table_cksoff_a1; 2488 uint32_t gb_vdroop_table_cksoff_a2; 2489 uint32_t gb_vdroop_table_ckson_a0; 2490 uint32_t gb_vdroop_table_ckson_a1; 2491 uint32_t gb_vdroop_table_ckson_a2; 2492 uint32_t avfsgb_fuse_table_cksoff_m1; 2493 uint32_t avfsgb_fuse_table_cksoff_m2; 2494 uint32_t avfsgb_fuse_table_cksoff_b; 2495 uint32_t avfsgb_fuse_table_ckson_m1; 2496 uint32_t avfsgb_fuse_table_ckson_m2; 2497 uint32_t avfsgb_fuse_table_ckson_b; 2498 uint16_t max_voltage_0_25mv; 2499 uint8_t enable_gb_vdroop_table_cksoff; 2500 uint8_t enable_gb_vdroop_table_ckson; 2501 uint8_t enable_gb_fuse_table_cksoff; 2502 uint8_t enable_gb_fuse_table_ckson; 2503 uint16_t psm_age_comfactor; 2504 uint8_t enable_apply_avfs_cksoff_voltage; 2505 uint8_t reserved; 2506 uint32_t dispclk2gfxclk_a; 2507 uint32_t dispclk2gfxclk_b; 2508 uint32_t dispclk2gfxclk_c; 2509 uint32_t pixclk2gfxclk_a; 2510 uint32_t pixclk2gfxclk_b; 2511 uint32_t pixclk2gfxclk_c; 2512 uint32_t dcefclk2gfxclk_a; 2513 uint32_t dcefclk2gfxclk_b; 2514 uint32_t dcefclk2gfxclk_c; 2515 uint32_t phyclk2gfxclk_a; 2516 uint32_t phyclk2gfxclk_b; 2517 uint32_t phyclk2gfxclk_c; 2518 }; 2519 2520 struct atom_asic_profiling_info_v4_2 { 2521 struct atom_common_table_header table_header; 2522 uint32_t maxvddc; 2523 uint32_t minvddc; 2524 uint32_t avfs_meannsigma_acontant0; 2525 uint32_t avfs_meannsigma_acontant1; 2526 uint32_t avfs_meannsigma_acontant2; 2527 uint16_t avfs_meannsigma_dc_tol_sigma; 2528 uint16_t avfs_meannsigma_platform_mean; 2529 uint16_t avfs_meannsigma_platform_sigma; 2530 uint32_t gb_vdroop_table_cksoff_a0; 2531 uint32_t gb_vdroop_table_cksoff_a1; 2532 uint32_t gb_vdroop_table_cksoff_a2; 2533 uint32_t gb_vdroop_table_ckson_a0; 2534 uint32_t gb_vdroop_table_ckson_a1; 2535 uint32_t gb_vdroop_table_ckson_a2; 2536 uint32_t avfsgb_fuse_table_cksoff_m1; 2537 uint32_t avfsgb_fuse_table_cksoff_m2; 2538 uint32_t avfsgb_fuse_table_cksoff_b; 2539 uint32_t avfsgb_fuse_table_ckson_m1; 2540 uint32_t avfsgb_fuse_table_ckson_m2; 2541 uint32_t avfsgb_fuse_table_ckson_b; 2542 uint16_t max_voltage_0_25mv; 2543 uint8_t enable_gb_vdroop_table_cksoff; 2544 uint8_t enable_gb_vdroop_table_ckson; 2545 uint8_t enable_gb_fuse_table_cksoff; 2546 uint8_t enable_gb_fuse_table_ckson; 2547 uint16_t psm_age_comfactor; 2548 uint8_t enable_apply_avfs_cksoff_voltage; 2549 uint8_t reserved; 2550 uint32_t dispclk2gfxclk_a; 2551 uint32_t dispclk2gfxclk_b; 2552 uint32_t dispclk2gfxclk_c; 2553 uint32_t pixclk2gfxclk_a; 2554 uint32_t pixclk2gfxclk_b; 2555 uint32_t pixclk2gfxclk_c; 2556 uint32_t dcefclk2gfxclk_a; 2557 uint32_t dcefclk2gfxclk_b; 2558 uint32_t dcefclk2gfxclk_c; 2559 uint32_t phyclk2gfxclk_a; 2560 uint32_t phyclk2gfxclk_b; 2561 uint32_t phyclk2gfxclk_c; 2562 uint32_t acg_gb_vdroop_table_a0; 2563 uint32_t acg_gb_vdroop_table_a1; 2564 uint32_t acg_gb_vdroop_table_a2; 2565 uint32_t acg_avfsgb_fuse_table_m1; 2566 uint32_t acg_avfsgb_fuse_table_m2; 2567 uint32_t acg_avfsgb_fuse_table_b; 2568 uint8_t enable_acg_gb_vdroop_table; 2569 uint8_t enable_acg_gb_fuse_table; 2570 uint32_t acg_dispclk2gfxclk_a; 2571 uint32_t acg_dispclk2gfxclk_b; 2572 uint32_t acg_dispclk2gfxclk_c; 2573 uint32_t acg_pixclk2gfxclk_a; 2574 uint32_t acg_pixclk2gfxclk_b; 2575 uint32_t acg_pixclk2gfxclk_c; 2576 uint32_t acg_dcefclk2gfxclk_a; 2577 uint32_t acg_dcefclk2gfxclk_b; 2578 uint32_t acg_dcefclk2gfxclk_c; 2579 uint32_t acg_phyclk2gfxclk_a; 2580 uint32_t acg_phyclk2gfxclk_b; 2581 uint32_t acg_phyclk2gfxclk_c; 2582 }; 2583 2584 /* 2585 *************************************************************************** 2586 Data Table multimedia_info structure 2587 *************************************************************************** 2588 */ 2589 struct atom_multimedia_info_v2_1 2590 { 2591 struct atom_common_table_header table_header; 2592 uint8_t uvdip_min_ver; 2593 uint8_t uvdip_max_ver; 2594 uint8_t vceip_min_ver; 2595 uint8_t vceip_max_ver; 2596 uint16_t uvd_enc_max_input_width_pixels; 2597 uint16_t uvd_enc_max_input_height_pixels; 2598 uint16_t vce_enc_max_input_width_pixels; 2599 uint16_t vce_enc_max_input_height_pixels; 2600 uint32_t uvd_enc_max_bandwidth; // 16x16 pixels/sec, codec independent 2601 uint32_t vce_enc_max_bandwidth; // 16x16 pixels/sec, codec independent 2602 }; 2603 2604 2605 /* 2606 *************************************************************************** 2607 Data Table umc_info structure 2608 *************************************************************************** 2609 */ 2610 struct atom_umc_info_v3_1 2611 { 2612 struct atom_common_table_header table_header; 2613 uint32_t ucode_version; 2614 uint32_t ucode_rom_startaddr; 2615 uint32_t ucode_length; 2616 uint16_t umc_reg_init_offset; 2617 uint16_t customer_ucode_name_offset; 2618 uint16_t mclk_ss_percentage; 2619 uint16_t mclk_ss_rate_10hz; 2620 uint8_t umcip_min_ver; 2621 uint8_t umcip_max_ver; 2622 uint8_t vram_type; //enum of atom_dgpu_vram_type 2623 uint8_t umc_config; 2624 uint32_t mem_refclk_10khz; 2625 }; 2626 2627 // umc_info.umc_config 2628 enum atom_umc_config_def { 2629 UMC_CONFIG__ENABLE_1KB_INTERLEAVE_MODE = 0x00000001, 2630 UMC_CONFIG__DEFAULT_MEM_ECC_ENABLE = 0x00000002, 2631 UMC_CONFIG__ENABLE_HBM_LANE_REPAIR = 0x00000004, 2632 UMC_CONFIG__ENABLE_BANK_HARVESTING = 0x00000008, 2633 UMC_CONFIG__ENABLE_PHY_REINIT = 0x00000010, 2634 UMC_CONFIG__DISABLE_UCODE_CHKSTATUS = 0x00000020, 2635 }; 2636 2637 struct atom_umc_info_v3_2 2638 { 2639 struct atom_common_table_header table_header; 2640 uint32_t ucode_version; 2641 uint32_t ucode_rom_startaddr; 2642 uint32_t ucode_length; 2643 uint16_t umc_reg_init_offset; 2644 uint16_t customer_ucode_name_offset; 2645 uint16_t mclk_ss_percentage; 2646 uint16_t mclk_ss_rate_10hz; 2647 uint8_t umcip_min_ver; 2648 uint8_t umcip_max_ver; 2649 uint8_t vram_type; //enum of atom_dgpu_vram_type 2650 uint8_t umc_config; 2651 uint32_t mem_refclk_10khz; 2652 uint32_t pstate_uclk_10khz[4]; 2653 uint16_t umcgoldenoffset; 2654 uint16_t densitygoldenoffset; 2655 }; 2656 2657 struct atom_umc_info_v3_3 2658 { 2659 struct atom_common_table_header table_header; 2660 uint32_t ucode_reserved; 2661 uint32_t ucode_rom_startaddr; 2662 uint32_t ucode_length; 2663 uint16_t umc_reg_init_offset; 2664 uint16_t customer_ucode_name_offset; 2665 uint16_t mclk_ss_percentage; 2666 uint16_t mclk_ss_rate_10hz; 2667 uint8_t umcip_min_ver; 2668 uint8_t umcip_max_ver; 2669 uint8_t vram_type; //enum of atom_dgpu_vram_type 2670 uint8_t umc_config; 2671 uint32_t mem_refclk_10khz; 2672 uint32_t pstate_uclk_10khz[4]; 2673 uint16_t umcgoldenoffset; 2674 uint16_t densitygoldenoffset; 2675 uint32_t umc_config1; 2676 uint32_t bist_data_startaddr; 2677 uint32_t reserved[2]; 2678 }; 2679 2680 enum atom_umc_config1_def { 2681 UMC_CONFIG1__ENABLE_PSTATE_PHASE_STORE_TRAIN = 0x00000001, 2682 UMC_CONFIG1__ENABLE_AUTO_FRAMING = 0x00000002, 2683 UMC_CONFIG1__ENABLE_RESTORE_BIST_DATA = 0x00000004, 2684 UMC_CONFIG1__DISABLE_STROBE_MODE = 0x00000008, 2685 UMC_CONFIG1__DEBUG_DATA_PARITY_EN = 0x00000010, 2686 UMC_CONFIG1__ENABLE_ECC_CAPABLE = 0x00010000, 2687 }; 2688 2689 /* 2690 *************************************************************************** 2691 Data Table vram_info structure 2692 *************************************************************************** 2693 */ 2694 struct atom_vram_module_v9 { 2695 // Design Specific Values 2696 uint32_t memory_size; // Total memory size in unit of MB for CONFIG_MEMSIZE zeros 2697 uint32_t channel_enable; // bit vector, each bit indicate specific channel enable or not 2698 uint32_t max_mem_clk; // max memory clock of this memory in unit of 10kHz, =0 means it is not defined 2699 uint16_t reserved[3]; 2700 uint16_t mem_voltage; // mem_voltage 2701 uint16_t vram_module_size; // Size of atom_vram_module_v9 2702 uint8_t ext_memory_id; // Current memory module ID 2703 uint8_t memory_type; // enum of atom_dgpu_vram_type 2704 uint8_t channel_num; // Number of mem. channels supported in this module 2705 uint8_t channel_width; // CHANNEL_16BIT/CHANNEL_32BIT/CHANNEL_64BIT 2706 uint8_t density; // _8Mx32, _16Mx32, _16Mx16, _32Mx16 2707 uint8_t tunningset_id; // MC phy registers set per. 2708 uint8_t vender_rev_id; // [7:4] Revision, [3:0] Vendor code 2709 uint8_t refreshrate; // [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64ms) 2710 uint8_t hbm_ven_rev_id; // hbm_ven_rev_id 2711 uint8_t vram_rsd2; // reserved 2712 char dram_pnstring[20]; // part number end with '0'. 2713 }; 2714 2715 struct atom_vram_info_header_v2_3 { 2716 struct atom_common_table_header table_header; 2717 uint16_t mem_adjust_tbloffset; // offset of atom_umc_init_reg_block structure for memory vendor specific UMC adjust setting 2718 uint16_t mem_clk_patch_tbloffset; // offset of atom_umc_init_reg_block structure for memory clock specific UMC setting 2719 uint16_t mc_adjust_pertile_tbloffset; // offset of atom_umc_init_reg_block structure for Per Byte Offset Preset Settings 2720 uint16_t mc_phyinit_tbloffset; // offset of atom_umc_init_reg_block structure for MC phy init set 2721 uint16_t dram_data_remap_tbloffset; // reserved for now 2722 uint16_t tmrs_seq_offset; // offset of HBM tmrs 2723 uint16_t post_ucode_init_offset; // offset of atom_umc_init_reg_block structure for MC phy init after MC uCode complete umc init 2724 uint16_t vram_rsd2; 2725 uint8_t vram_module_num; // indicate number of VRAM module 2726 uint8_t umcip_min_ver; 2727 uint8_t umcip_max_ver; 2728 uint8_t mc_phy_tile_num; // indicate the MCD tile number which use in DramDataRemapTbl and usMcAdjustPerTileTblOffset 2729 struct atom_vram_module_v9 vram_module[16]; // just for allocation, real number of blocks is in ucNumOfVRAMModule; 2730 }; 2731 2732 struct atom_umc_register_addr_info{ 2733 uint32_t umc_register_addr:24; 2734 uint32_t umc_reg_type_ind:1; 2735 uint32_t umc_reg_rsvd:7; 2736 }; 2737 2738 //atom_umc_register_addr_info. 2739 enum atom_umc_register_addr_info_flag{ 2740 b3ATOM_UMC_REG_ADD_INFO_INDIRECT_ACCESS =0x01, 2741 }; 2742 2743 union atom_umc_register_addr_info_access 2744 { 2745 struct atom_umc_register_addr_info umc_reg_addr; 2746 uint32_t u32umc_reg_addr; 2747 }; 2748 2749 struct atom_umc_reg_setting_id_config{ 2750 uint32_t memclockrange:24; 2751 uint32_t mem_blk_id:8; 2752 }; 2753 2754 union atom_umc_reg_setting_id_config_access 2755 { 2756 struct atom_umc_reg_setting_id_config umc_id_access; 2757 uint32_t u32umc_id_access; 2758 }; 2759 2760 struct atom_umc_reg_setting_data_block{ 2761 union atom_umc_reg_setting_id_config_access block_id; 2762 uint32_t u32umc_reg_data[1]; 2763 }; 2764 2765 struct atom_umc_init_reg_block{ 2766 uint16_t umc_reg_num; 2767 uint16_t reserved; 2768 union atom_umc_register_addr_info_access umc_reg_list[1]; //for allocation purpose, the real number come from umc_reg_num; 2769 struct atom_umc_reg_setting_data_block umc_reg_setting_list[1]; 2770 }; 2771 2772 struct atom_vram_module_v10 { 2773 // Design Specific Values 2774 uint32_t memory_size; // Total memory size in unit of MB for CONFIG_MEMSIZE zeros 2775 uint32_t channel_enable; // bit vector, each bit indicate specific channel enable or not 2776 uint32_t max_mem_clk; // max memory clock of this memory in unit of 10kHz, =0 means it is not defined 2777 uint16_t reserved[3]; 2778 uint16_t mem_voltage; // mem_voltage 2779 uint16_t vram_module_size; // Size of atom_vram_module_v9 2780 uint8_t ext_memory_id; // Current memory module ID 2781 uint8_t memory_type; // enum of atom_dgpu_vram_type 2782 uint8_t channel_num; // Number of mem. channels supported in this module 2783 uint8_t channel_width; // CHANNEL_16BIT/CHANNEL_32BIT/CHANNEL_64BIT 2784 uint8_t density; // _8Mx32, _16Mx32, _16Mx16, _32Mx16 2785 uint8_t tunningset_id; // MC phy registers set per 2786 uint8_t vender_rev_id; // [7:4] Revision, [3:0] Vendor code 2787 uint8_t refreshrate; // [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64ms) 2788 uint8_t vram_flags; // bit0= bankgroup enable 2789 uint8_t vram_rsd2; // reserved 2790 uint16_t gddr6_mr10; // gddr6 mode register10 value 2791 uint16_t gddr6_mr1; // gddr6 mode register1 value 2792 uint16_t gddr6_mr2; // gddr6 mode register2 value 2793 uint16_t gddr6_mr7; // gddr6 mode register7 value 2794 char dram_pnstring[20]; // part number end with '0' 2795 }; 2796 2797 struct atom_vram_info_header_v2_4 { 2798 struct atom_common_table_header table_header; 2799 uint16_t mem_adjust_tbloffset; // offset of atom_umc_init_reg_block structure for memory vendor specific UMC adjust setting 2800 uint16_t mem_clk_patch_tbloffset; // offset of atom_umc_init_reg_block structure for memory clock specific UMC setting 2801 uint16_t mc_adjust_pertile_tbloffset; // offset of atom_umc_init_reg_block structure for Per Byte Offset Preset Settings 2802 uint16_t mc_phyinit_tbloffset; // offset of atom_umc_init_reg_block structure for MC phy init set 2803 uint16_t dram_data_remap_tbloffset; // reserved for now 2804 uint16_t reserved; // offset of reserved 2805 uint16_t post_ucode_init_offset; // offset of atom_umc_init_reg_block structure for MC phy init after MC uCode complete umc init 2806 uint16_t vram_rsd2; 2807 uint8_t vram_module_num; // indicate number of VRAM module 2808 uint8_t umcip_min_ver; 2809 uint8_t umcip_max_ver; 2810 uint8_t mc_phy_tile_num; // indicate the MCD tile number which use in DramDataRemapTbl and usMcAdjustPerTileTblOffset 2811 struct atom_vram_module_v10 vram_module[16]; // just for allocation, real number of blocks is in ucNumOfVRAMModule; 2812 }; 2813 2814 struct atom_vram_module_v11 { 2815 // Design Specific Values 2816 uint32_t memory_size; // Total memory size in unit of MB for CONFIG_MEMSIZE zeros 2817 uint32_t channel_enable; // bit vector, each bit indicate specific channel enable or not 2818 uint16_t mem_voltage; // mem_voltage 2819 uint16_t vram_module_size; // Size of atom_vram_module_v9 2820 uint8_t ext_memory_id; // Current memory module ID 2821 uint8_t memory_type; // enum of atom_dgpu_vram_type 2822 uint8_t channel_num; // Number of mem. channels supported in this module 2823 uint8_t channel_width; // CHANNEL_16BIT/CHANNEL_32BIT/CHANNEL_64BIT 2824 uint8_t density; // _8Mx32, _16Mx32, _16Mx16, _32Mx16 2825 uint8_t tunningset_id; // MC phy registers set per. 2826 uint16_t reserved[4]; // reserved 2827 uint8_t vender_rev_id; // [7:4] Revision, [3:0] Vendor code 2828 uint8_t refreshrate; // [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64ms) 2829 uint8_t vram_flags; // bit0= bankgroup enable 2830 uint8_t vram_rsd2; // reserved 2831 uint16_t gddr6_mr10; // gddr6 mode register10 value 2832 uint16_t gddr6_mr0; // gddr6 mode register0 value 2833 uint16_t gddr6_mr1; // gddr6 mode register1 value 2834 uint16_t gddr6_mr2; // gddr6 mode register2 value 2835 uint16_t gddr6_mr4; // gddr6 mode register4 value 2836 uint16_t gddr6_mr7; // gddr6 mode register7 value 2837 uint16_t gddr6_mr8; // gddr6 mode register8 value 2838 char dram_pnstring[40]; // part number end with '0'. 2839 }; 2840 2841 struct atom_gddr6_ac_timing_v2_5 { 2842 uint32_t u32umc_id_access; 2843 uint8_t RL; 2844 uint8_t WL; 2845 uint8_t tRAS; 2846 uint8_t tRC; 2847 2848 uint16_t tREFI; 2849 uint8_t tRFC; 2850 uint8_t tRFCpb; 2851 2852 uint8_t tRREFD; 2853 uint8_t tRCDRD; 2854 uint8_t tRCDWR; 2855 uint8_t tRP; 2856 2857 uint8_t tRRDS; 2858 uint8_t tRRDL; 2859 uint8_t tWR; 2860 uint8_t tWTRS; 2861 2862 uint8_t tWTRL; 2863 uint8_t tFAW; 2864 uint8_t tCCDS; 2865 uint8_t tCCDL; 2866 2867 uint8_t tCRCRL; 2868 uint8_t tCRCWL; 2869 uint8_t tCKE; 2870 uint8_t tCKSRE; 2871 2872 uint8_t tCKSRX; 2873 uint8_t tRTPS; 2874 uint8_t tRTPL; 2875 uint8_t tMRD; 2876 2877 uint8_t tMOD; 2878 uint8_t tXS; 2879 uint8_t tXHP; 2880 uint8_t tXSMRS; 2881 2882 uint32_t tXSH; 2883 2884 uint8_t tPD; 2885 uint8_t tXP; 2886 uint8_t tCPDED; 2887 uint8_t tACTPDE; 2888 2889 uint8_t tPREPDE; 2890 uint8_t tREFPDE; 2891 uint8_t tMRSPDEN; 2892 uint8_t tRDSRE; 2893 2894 uint8_t tWRSRE; 2895 uint8_t tPPD; 2896 uint8_t tCCDMW; 2897 uint8_t tWTRTR; 2898 2899 uint8_t tLTLTR; 2900 uint8_t tREFTR; 2901 uint8_t VNDR; 2902 uint8_t reserved[9]; 2903 }; 2904 2905 struct atom_gddr6_bit_byte_remap { 2906 uint32_t dphy_byteremap; //mmUMC_DPHY_ByteRemap 2907 uint32_t dphy_bitremap0; //mmUMC_DPHY_BitRemap0 2908 uint32_t dphy_bitremap1; //mmUMC_DPHY_BitRemap1 2909 uint32_t dphy_bitremap2; //mmUMC_DPHY_BitRemap2 2910 uint32_t aphy_bitremap0; //mmUMC_APHY_BitRemap0 2911 uint32_t aphy_bitremap1; //mmUMC_APHY_BitRemap1 2912 uint32_t phy_dram; //mmUMC_PHY_DRAM 2913 }; 2914 2915 struct atom_gddr6_dram_data_remap { 2916 uint32_t table_size; 2917 uint8_t phyintf_ck_inverted[8]; //UMC_PHY_PHYINTF_CNTL.INV_CK 2918 struct atom_gddr6_bit_byte_remap bit_byte_remap[16]; 2919 }; 2920 2921 struct atom_vram_info_header_v2_5 { 2922 struct atom_common_table_header table_header; 2923 uint16_t mem_adjust_tbloffset; // offset of atom_umc_init_reg_block structure for memory vendor specific UMC adjust settings 2924 uint16_t gddr6_ac_timing_offset; // offset of atom_gddr6_ac_timing_v2_5 structure for memory clock specific UMC settings 2925 uint16_t mc_adjust_pertile_tbloffset; // offset of atom_umc_init_reg_block structure for Per Byte Offset Preset Settings 2926 uint16_t mc_phyinit_tbloffset; // offset of atom_umc_init_reg_block structure for MC phy init set 2927 uint16_t dram_data_remap_tbloffset; // offset of atom_gddr6_dram_data_remap array to indicate DRAM data lane to GPU mapping 2928 uint16_t reserved; // offset of reserved 2929 uint16_t post_ucode_init_offset; // offset of atom_umc_init_reg_block structure for MC phy init after MC uCode complete umc init 2930 uint16_t strobe_mode_patch_tbloffset; // offset of atom_umc_init_reg_block structure for Strobe Mode memory clock specific UMC settings 2931 uint8_t vram_module_num; // indicate number of VRAM module 2932 uint8_t umcip_min_ver; 2933 uint8_t umcip_max_ver; 2934 uint8_t mc_phy_tile_num; // indicate the MCD tile number which use in DramDataRemapTbl and usMcAdjustPerTileTblOffset 2935 struct atom_vram_module_v11 vram_module[16]; // just for allocation, real number of blocks is in ucNumOfVRAMModule; 2936 }; 2937 2938 struct atom_vram_info_header_v2_6 { 2939 struct atom_common_table_header table_header; 2940 uint16_t mem_adjust_tbloffset; 2941 uint16_t mem_clk_patch_tbloffset; 2942 uint16_t mc_adjust_pertile_tbloffset; 2943 uint16_t mc_phyinit_tbloffset; 2944 uint16_t dram_data_remap_tbloffset; 2945 uint16_t tmrs_seq_offset; 2946 uint16_t post_ucode_init_offset; 2947 uint16_t vram_rsd2; 2948 uint8_t vram_module_num; 2949 uint8_t umcip_min_ver; 2950 uint8_t umcip_max_ver; 2951 uint8_t mc_phy_tile_num; 2952 struct atom_vram_module_v9 vram_module[16]; 2953 }; 2954 /* 2955 *************************************************************************** 2956 Data Table voltageobject_info structure 2957 *************************************************************************** 2958 */ 2959 struct atom_i2c_data_entry 2960 { 2961 uint16_t i2c_reg_index; // i2c register address, can be up to 16bit 2962 uint16_t i2c_reg_data; // i2c register data, can be up to 16bit 2963 }; 2964 2965 struct atom_voltage_object_header_v4{ 2966 uint8_t voltage_type; //enum atom_voltage_type 2967 uint8_t voltage_mode; //enum atom_voltage_object_mode 2968 uint16_t object_size; //Size of Object 2969 }; 2970 2971 // atom_voltage_object_header_v4.voltage_mode 2972 enum atom_voltage_object_mode 2973 { 2974 VOLTAGE_OBJ_GPIO_LUT = 0, //VOLTAGE and GPIO Lookup table ->atom_gpio_voltage_object_v4 2975 VOLTAGE_OBJ_VR_I2C_INIT_SEQ = 3, //VOLTAGE REGULATOR INIT sequece through I2C -> atom_i2c_voltage_object_v4 2976 VOLTAGE_OBJ_PHASE_LUT = 4, //Set Vregulator Phase lookup table ->atom_gpio_voltage_object_v4 2977 VOLTAGE_OBJ_SVID2 = 7, //Indicate voltage control by SVID2 ->atom_svid2_voltage_object_v4 2978 VOLTAGE_OBJ_EVV = 8, 2979 VOLTAGE_OBJ_MERGED_POWER = 9, 2980 }; 2981 2982 struct atom_i2c_voltage_object_v4 2983 { 2984 struct atom_voltage_object_header_v4 header; // voltage mode = VOLTAGE_OBJ_VR_I2C_INIT_SEQ 2985 uint8_t regulator_id; //Indicate Voltage Regulator Id 2986 uint8_t i2c_id; 2987 uint8_t i2c_slave_addr; 2988 uint8_t i2c_control_offset; 2989 uint8_t i2c_flag; // Bit0: 0 - One byte data; 1 - Two byte data 2990 uint8_t i2c_speed; // =0, use default i2c speed, otherwise use it in unit of kHz. 2991 uint8_t reserved[2]; 2992 struct atom_i2c_data_entry i2cdatalut[1]; // end with 0xff 2993 }; 2994 2995 // ATOM_I2C_VOLTAGE_OBJECT_V3.ucVoltageControlFlag 2996 enum atom_i2c_voltage_control_flag 2997 { 2998 VOLTAGE_DATA_ONE_BYTE = 0, 2999 VOLTAGE_DATA_TWO_BYTE = 1, 3000 }; 3001 3002 3003 struct atom_voltage_gpio_map_lut 3004 { 3005 uint32_t voltage_gpio_reg_val; // The Voltage ID which is used to program GPIO register 3006 uint16_t voltage_level_mv; // The corresponding Voltage Value, in mV 3007 }; 3008 3009 struct atom_gpio_voltage_object_v4 3010 { 3011 struct atom_voltage_object_header_v4 header; // voltage mode = VOLTAGE_OBJ_GPIO_LUT or VOLTAGE_OBJ_PHASE_LUT 3012 uint8_t gpio_control_id; // default is 0 which indicate control through CG VID mode 3013 uint8_t gpio_entry_num; // indiate the entry numbers of Votlage/Gpio value Look up table 3014 uint8_t phase_delay_us; // phase delay in unit of micro second 3015 uint8_t reserved; 3016 uint32_t gpio_mask_val; // GPIO Mask value 3017 struct atom_voltage_gpio_map_lut voltage_gpio_lut[1]; 3018 }; 3019 3020 struct atom_svid2_voltage_object_v4 3021 { 3022 struct atom_voltage_object_header_v4 header; // voltage mode = VOLTAGE_OBJ_SVID2 3023 uint8_t loadline_psi1; // bit4:0= loadline setting ( Core Loadline trim and offset trim ), bit5=0:PSI1_L disable =1: PSI1_L enable 3024 uint8_t psi0_l_vid_thresd; // VR PSI0_L VID threshold 3025 uint8_t psi0_enable; // 3026 uint8_t maxvstep; 3027 uint8_t telemetry_offset; 3028 uint8_t telemetry_gain; 3029 uint16_t reserved1; 3030 }; 3031 3032 struct atom_merged_voltage_object_v4 3033 { 3034 struct atom_voltage_object_header_v4 header; // voltage mode = VOLTAGE_OBJ_MERGED_POWER 3035 uint8_t merged_powerrail_type; //enum atom_voltage_type 3036 uint8_t reserved[3]; 3037 }; 3038 3039 union atom_voltage_object_v4{ 3040 struct atom_gpio_voltage_object_v4 gpio_voltage_obj; 3041 struct atom_i2c_voltage_object_v4 i2c_voltage_obj; 3042 struct atom_svid2_voltage_object_v4 svid2_voltage_obj; 3043 struct atom_merged_voltage_object_v4 merged_voltage_obj; 3044 }; 3045 3046 struct atom_voltage_objects_info_v4_1 3047 { 3048 struct atom_common_table_header table_header; 3049 union atom_voltage_object_v4 voltage_object[1]; //Info for Voltage control 3050 }; 3051 3052 3053 /* 3054 *************************************************************************** 3055 All Command Function structure definition 3056 *************************************************************************** 3057 */ 3058 3059 /* 3060 *************************************************************************** 3061 Structures used by asic_init 3062 *************************************************************************** 3063 */ 3064 3065 struct asic_init_engine_parameters 3066 { 3067 uint32_t sclkfreqin10khz:24; 3068 uint32_t engineflag:8; /* enum atom_asic_init_engine_flag */ 3069 }; 3070 3071 struct asic_init_mem_parameters 3072 { 3073 uint32_t mclkfreqin10khz:24; 3074 uint32_t memflag:8; /* enum atom_asic_init_mem_flag */ 3075 }; 3076 3077 struct asic_init_parameters_v2_1 3078 { 3079 struct asic_init_engine_parameters engineparam; 3080 struct asic_init_mem_parameters memparam; 3081 }; 3082 3083 struct asic_init_ps_allocation_v2_1 3084 { 3085 struct asic_init_parameters_v2_1 param; 3086 uint32_t reserved[16]; 3087 }; 3088 3089 3090 enum atom_asic_init_engine_flag 3091 { 3092 b3NORMAL_ENGINE_INIT = 0, 3093 b3SRIOV_SKIP_ASIC_INIT = 0x02, 3094 b3SRIOV_LOAD_UCODE = 0x40, 3095 }; 3096 3097 enum atom_asic_init_mem_flag 3098 { 3099 b3NORMAL_MEM_INIT = 0, 3100 b3DRAM_SELF_REFRESH_EXIT =0x20, 3101 }; 3102 3103 /* 3104 *************************************************************************** 3105 Structures used by setengineclock 3106 *************************************************************************** 3107 */ 3108 3109 struct set_engine_clock_parameters_v2_1 3110 { 3111 uint32_t sclkfreqin10khz:24; 3112 uint32_t sclkflag:8; /* enum atom_set_engine_mem_clock_flag, */ 3113 uint32_t reserved[10]; 3114 }; 3115 3116 struct set_engine_clock_ps_allocation_v2_1 3117 { 3118 struct set_engine_clock_parameters_v2_1 clockinfo; 3119 uint32_t reserved[10]; 3120 }; 3121 3122 3123 enum atom_set_engine_mem_clock_flag 3124 { 3125 b3NORMAL_CHANGE_CLOCK = 0, 3126 b3FIRST_TIME_CHANGE_CLOCK = 0x08, 3127 b3STORE_DPM_TRAINGING = 0x40, //Applicable to memory clock change,when set, it store specific DPM mode training result 3128 }; 3129 3130 /* 3131 *************************************************************************** 3132 Structures used by getengineclock 3133 *************************************************************************** 3134 */ 3135 struct get_engine_clock_parameter 3136 { 3137 uint32_t sclk_10khz; // current engine speed in 10KHz unit 3138 uint32_t reserved; 3139 }; 3140 3141 /* 3142 *************************************************************************** 3143 Structures used by setmemoryclock 3144 *************************************************************************** 3145 */ 3146 struct set_memory_clock_parameters_v2_1 3147 { 3148 uint32_t mclkfreqin10khz:24; 3149 uint32_t mclkflag:8; /* enum atom_set_engine_mem_clock_flag, */ 3150 uint32_t reserved[10]; 3151 }; 3152 3153 struct set_memory_clock_ps_allocation_v2_1 3154 { 3155 struct set_memory_clock_parameters_v2_1 clockinfo; 3156 uint32_t reserved[10]; 3157 }; 3158 3159 3160 /* 3161 *************************************************************************** 3162 Structures used by getmemoryclock 3163 *************************************************************************** 3164 */ 3165 struct get_memory_clock_parameter 3166 { 3167 uint32_t mclk_10khz; // current engine speed in 10KHz unit 3168 uint32_t reserved; 3169 }; 3170 3171 3172 3173 /* 3174 *************************************************************************** 3175 Structures used by setvoltage 3176 *************************************************************************** 3177 */ 3178 3179 struct set_voltage_parameters_v1_4 3180 { 3181 uint8_t voltagetype; /* enum atom_voltage_type */ 3182 uint8_t command; /* Indicate action: Set voltage level, enum atom_set_voltage_command */ 3183 uint16_t vlevel_mv; /* real voltage level in unit of mv or Voltage Phase (0, 1, 2, .. ) */ 3184 }; 3185 3186 //set_voltage_parameters_v2_1.voltagemode 3187 enum atom_set_voltage_command{ 3188 ATOM_SET_VOLTAGE = 0, 3189 ATOM_INIT_VOLTAGE_REGULATOR = 3, 3190 ATOM_SET_VOLTAGE_PHASE = 4, 3191 ATOM_GET_LEAKAGE_ID = 8, 3192 }; 3193 3194 struct set_voltage_ps_allocation_v1_4 3195 { 3196 struct set_voltage_parameters_v1_4 setvoltageparam; 3197 uint32_t reserved[10]; 3198 }; 3199 3200 3201 /* 3202 *************************************************************************** 3203 Structures used by computegpuclockparam 3204 *************************************************************************** 3205 */ 3206 3207 //ATOM_COMPUTE_CLOCK_FREQ.ulComputeClockFlag 3208 enum atom_gpu_clock_type 3209 { 3210 COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK =0x00, 3211 COMPUTE_GPUCLK_INPUT_FLAG_GFXCLK =0x01, 3212 COMPUTE_GPUCLK_INPUT_FLAG_UCLK =0x02, 3213 }; 3214 3215 struct compute_gpu_clock_input_parameter_v1_8 3216 { 3217 uint32_t gpuclock_10khz:24; //Input= target clock, output = actual clock 3218 uint32_t gpu_clock_type:8; //Input indicate clock type: enum atom_gpu_clock_type 3219 uint32_t reserved[5]; 3220 }; 3221 3222 3223 struct compute_gpu_clock_output_parameter_v1_8 3224 { 3225 uint32_t gpuclock_10khz:24; //Input= target clock, output = actual clock 3226 uint32_t dfs_did:8; //return parameter: DFS divider which is used to program to register directly 3227 uint32_t pll_fb_mult; //Feedback Multiplier, bit 8:0 int, bit 15:12 post_div, bit 31:16 frac 3228 uint32_t pll_ss_fbsmult; // Spread FB Mult: bit 8:0 int, bit 31:16 frac 3229 uint16_t pll_ss_slew_frac; 3230 uint8_t pll_ss_enable; 3231 uint8_t reserved; 3232 uint32_t reserved1[2]; 3233 }; 3234 3235 3236 3237 /* 3238 *************************************************************************** 3239 Structures used by ReadEfuseValue 3240 *************************************************************************** 3241 */ 3242 3243 struct read_efuse_input_parameters_v3_1 3244 { 3245 uint16_t efuse_start_index; 3246 uint8_t reserved; 3247 uint8_t bitslen; 3248 }; 3249 3250 // ReadEfuseValue input/output parameter 3251 union read_efuse_value_parameters_v3_1 3252 { 3253 struct read_efuse_input_parameters_v3_1 efuse_info; 3254 uint32_t efusevalue; 3255 }; 3256 3257 3258 /* 3259 *************************************************************************** 3260 Structures used by getsmuclockinfo 3261 *************************************************************************** 3262 */ 3263 struct atom_get_smu_clock_info_parameters_v3_1 3264 { 3265 uint8_t syspll_id; // 0= syspll0, 1=syspll1, 2=syspll2 3266 uint8_t clk_id; // atom_smu9_syspll0_clock_id (only valid when command == GET_SMU_CLOCK_INFO_V3_1_GET_CLOCK_FREQ ) 3267 uint8_t command; // enum of atom_get_smu_clock_info_command 3268 uint8_t dfsdid; // =0: get DFS DID from register, >0, give DFS divider, (only valid when command == GET_SMU_CLOCK_INFO_V3_1_GET_CLOCK_FREQ ) 3269 }; 3270 3271 enum atom_get_smu_clock_info_command 3272 { 3273 GET_SMU_CLOCK_INFO_V3_1_GET_CLOCK_FREQ = 0, 3274 GET_SMU_CLOCK_INFO_V3_1_GET_PLLVCO_FREQ = 1, 3275 GET_SMU_CLOCK_INFO_V3_1_GET_PLLREFCLK_FREQ = 2, 3276 }; 3277 3278 enum atom_smu9_syspll0_clock_id 3279 { 3280 SMU9_SYSPLL0_SMNCLK_ID = 0, // SMNCLK 3281 SMU9_SYSPLL0_SOCCLK_ID = 1, // SOCCLK (FCLK) 3282 SMU9_SYSPLL0_MP0CLK_ID = 2, // MP0CLK 3283 SMU9_SYSPLL0_MP1CLK_ID = 3, // MP1CLK 3284 SMU9_SYSPLL0_LCLK_ID = 4, // LCLK 3285 SMU9_SYSPLL0_DCLK_ID = 5, // DCLK 3286 SMU9_SYSPLL0_VCLK_ID = 6, // VCLK 3287 SMU9_SYSPLL0_ECLK_ID = 7, // ECLK 3288 SMU9_SYSPLL0_DCEFCLK_ID = 8, // DCEFCLK 3289 SMU9_SYSPLL0_DPREFCLK_ID = 10, // DPREFCLK 3290 SMU9_SYSPLL0_DISPCLK_ID = 11, // DISPCLK 3291 }; 3292 3293 enum atom_smu11_syspll_id { 3294 SMU11_SYSPLL0_ID = 0, 3295 SMU11_SYSPLL1_0_ID = 1, 3296 SMU11_SYSPLL1_1_ID = 2, 3297 SMU11_SYSPLL1_2_ID = 3, 3298 SMU11_SYSPLL2_ID = 4, 3299 SMU11_SYSPLL3_0_ID = 5, 3300 SMU11_SYSPLL3_1_ID = 6, 3301 }; 3302 3303 enum atom_smu11_syspll0_clock_id { 3304 SMU11_SYSPLL0_ECLK_ID = 0, // ECLK 3305 SMU11_SYSPLL0_SOCCLK_ID = 1, // SOCCLK 3306 SMU11_SYSPLL0_MP0CLK_ID = 2, // MP0CLK 3307 SMU11_SYSPLL0_DCLK_ID = 3, // DCLK 3308 SMU11_SYSPLL0_VCLK_ID = 4, // VCLK 3309 SMU11_SYSPLL0_DCEFCLK_ID = 5, // DCEFCLK 3310 }; 3311 3312 enum atom_smu11_syspll1_0_clock_id { 3313 SMU11_SYSPLL1_0_UCLKA_ID = 0, // UCLK_a 3314 }; 3315 3316 enum atom_smu11_syspll1_1_clock_id { 3317 SMU11_SYSPLL1_0_UCLKB_ID = 0, // UCLK_b 3318 }; 3319 3320 enum atom_smu11_syspll1_2_clock_id { 3321 SMU11_SYSPLL1_0_FCLK_ID = 0, // FCLK 3322 }; 3323 3324 enum atom_smu11_syspll2_clock_id { 3325 SMU11_SYSPLL2_GFXCLK_ID = 0, // GFXCLK 3326 }; 3327 3328 enum atom_smu11_syspll3_0_clock_id { 3329 SMU11_SYSPLL3_0_WAFCLK_ID = 0, // WAFCLK 3330 SMU11_SYSPLL3_0_DISPCLK_ID = 1, // DISPCLK 3331 SMU11_SYSPLL3_0_DPREFCLK_ID = 2, // DPREFCLK 3332 }; 3333 3334 enum atom_smu11_syspll3_1_clock_id { 3335 SMU11_SYSPLL3_1_MP1CLK_ID = 0, // MP1CLK 3336 SMU11_SYSPLL3_1_SMNCLK_ID = 1, // SMNCLK 3337 SMU11_SYSPLL3_1_LCLK_ID = 2, // LCLK 3338 }; 3339 3340 enum atom_smu12_syspll_id { 3341 SMU12_SYSPLL0_ID = 0, 3342 SMU12_SYSPLL1_ID = 1, 3343 SMU12_SYSPLL2_ID = 2, 3344 SMU12_SYSPLL3_0_ID = 3, 3345 SMU12_SYSPLL3_1_ID = 4, 3346 }; 3347 3348 enum atom_smu12_syspll0_clock_id { 3349 SMU12_SYSPLL0_SMNCLK_ID = 0, // SOCCLK 3350 SMU12_SYSPLL0_SOCCLK_ID = 1, // SOCCLK 3351 SMU12_SYSPLL0_MP0CLK_ID = 2, // MP0CLK 3352 SMU12_SYSPLL0_MP1CLK_ID = 3, // MP1CLK 3353 SMU12_SYSPLL0_MP2CLK_ID = 4, // MP2CLK 3354 SMU12_SYSPLL0_VCLK_ID = 5, // VCLK 3355 SMU12_SYSPLL0_LCLK_ID = 6, // LCLK 3356 SMU12_SYSPLL0_DCLK_ID = 7, // DCLK 3357 SMU12_SYSPLL0_ACLK_ID = 8, // ACLK 3358 SMU12_SYSPLL0_ISPCLK_ID = 9, // ISPCLK 3359 SMU12_SYSPLL0_SHUBCLK_ID = 10, // SHUBCLK 3360 }; 3361 3362 enum atom_smu12_syspll1_clock_id { 3363 SMU12_SYSPLL1_DISPCLK_ID = 0, // DISPCLK 3364 SMU12_SYSPLL1_DPPCLK_ID = 1, // DPPCLK 3365 SMU12_SYSPLL1_DPREFCLK_ID = 2, // DPREFCLK 3366 SMU12_SYSPLL1_DCFCLK_ID = 3, // DCFCLK 3367 }; 3368 3369 enum atom_smu12_syspll2_clock_id { 3370 SMU12_SYSPLL2_Pre_GFXCLK_ID = 0, // Pre_GFXCLK 3371 }; 3372 3373 enum atom_smu12_syspll3_0_clock_id { 3374 SMU12_SYSPLL3_0_FCLK_ID = 0, // FCLK 3375 }; 3376 3377 enum atom_smu12_syspll3_1_clock_id { 3378 SMU12_SYSPLL3_1_UMCCLK_ID = 0, // UMCCLK 3379 }; 3380 3381 struct atom_get_smu_clock_info_output_parameters_v3_1 3382 { 3383 union { 3384 uint32_t smu_clock_freq_hz; 3385 uint32_t syspllvcofreq_10khz; 3386 uint32_t sysspllrefclk_10khz; 3387 }atom_smu_outputclkfreq; 3388 }; 3389 3390 3391 3392 /* 3393 *************************************************************************** 3394 Structures used by dynamicmemorysettings 3395 *************************************************************************** 3396 */ 3397 3398 enum atom_dynamic_memory_setting_command 3399 { 3400 COMPUTE_MEMORY_PLL_PARAM = 1, 3401 COMPUTE_ENGINE_PLL_PARAM = 2, 3402 ADJUST_MC_SETTING_PARAM = 3, 3403 }; 3404 3405 /* when command = COMPUTE_MEMORY_PLL_PARAM or ADJUST_MC_SETTING_PARAM */ 3406 struct dynamic_mclk_settings_parameters_v2_1 3407 { 3408 uint32_t mclk_10khz:24; //Input= target mclk 3409 uint32_t command:8; //command enum of atom_dynamic_memory_setting_command 3410 uint32_t reserved; 3411 }; 3412 3413 /* when command = COMPUTE_ENGINE_PLL_PARAM */ 3414 struct dynamic_sclk_settings_parameters_v2_1 3415 { 3416 uint32_t sclk_10khz:24; //Input= target mclk 3417 uint32_t command:8; //command enum of atom_dynamic_memory_setting_command 3418 uint32_t mclk_10khz; 3419 uint32_t reserved; 3420 }; 3421 3422 union dynamic_memory_settings_parameters_v2_1 3423 { 3424 struct dynamic_mclk_settings_parameters_v2_1 mclk_setting; 3425 struct dynamic_sclk_settings_parameters_v2_1 sclk_setting; 3426 }; 3427 3428 3429 3430 /* 3431 *************************************************************************** 3432 Structures used by memorytraining 3433 *************************************************************************** 3434 */ 3435 3436 enum atom_umc6_0_ucode_function_call_enum_id 3437 { 3438 UMC60_UCODE_FUNC_ID_REINIT = 0, 3439 UMC60_UCODE_FUNC_ID_ENTER_SELFREFRESH = 1, 3440 UMC60_UCODE_FUNC_ID_EXIT_SELFREFRESH = 2, 3441 }; 3442 3443 3444 struct memory_training_parameters_v2_1 3445 { 3446 uint8_t ucode_func_id; 3447 uint8_t ucode_reserved[3]; 3448 uint32_t reserved[5]; 3449 }; 3450 3451 3452 /* 3453 *************************************************************************** 3454 Structures used by setpixelclock 3455 *************************************************************************** 3456 */ 3457 3458 struct set_pixel_clock_parameter_v1_7 3459 { 3460 uint32_t pixclk_100hz; // target the pixel clock to drive the CRTC timing in unit of 100Hz. 3461 3462 uint8_t pll_id; // ATOM_PHY_PLL0/ATOM_PHY_PLL1/ATOM_PPLL0 3463 uint8_t encoderobjid; // ASIC encoder id defined in objectId.h, 3464 // indicate which graphic encoder will be used. 3465 uint8_t encoder_mode; // Encoder mode: 3466 uint8_t miscinfo; // enum atom_set_pixel_clock_v1_7_misc_info 3467 uint8_t crtc_id; // enum of atom_crtc_def 3468 uint8_t deep_color_ratio; // HDMI panel bit depth: enum atom_set_pixel_clock_v1_7_deepcolor_ratio 3469 uint8_t reserved1[2]; 3470 uint32_t reserved2; 3471 }; 3472 3473 //ucMiscInfo 3474 enum atom_set_pixel_clock_v1_7_misc_info 3475 { 3476 PIXEL_CLOCK_V7_MISC_FORCE_PROG_PPLL = 0x01, 3477 PIXEL_CLOCK_V7_MISC_PROG_PHYPLL = 0x02, 3478 PIXEL_CLOCK_V7_MISC_YUV420_MODE = 0x04, 3479 PIXEL_CLOCK_V7_MISC_DVI_DUALLINK_EN = 0x08, 3480 PIXEL_CLOCK_V7_MISC_REF_DIV_SRC = 0x30, 3481 PIXEL_CLOCK_V7_MISC_REF_DIV_SRC_XTALIN = 0x00, 3482 PIXEL_CLOCK_V7_MISC_REF_DIV_SRC_PCIE = 0x10, 3483 PIXEL_CLOCK_V7_MISC_REF_DIV_SRC_GENLK = 0x20, 3484 PIXEL_CLOCK_V7_MISC_REF_DIV_SRC_REFPAD = 0x30, 3485 PIXEL_CLOCK_V7_MISC_ATOMIC_UPDATE = 0x40, 3486 PIXEL_CLOCK_V7_MISC_FORCE_SS_DIS = 0x80, 3487 }; 3488 3489 /* deep_color_ratio */ 3490 enum atom_set_pixel_clock_v1_7_deepcolor_ratio 3491 { 3492 PIXEL_CLOCK_V7_DEEPCOLOR_RATIO_DIS = 0x00, //00 - DCCG_DEEP_COLOR_DTO_DISABLE: Disable Deep Color DTO 3493 PIXEL_CLOCK_V7_DEEPCOLOR_RATIO_5_4 = 0x01, //01 - DCCG_DEEP_COLOR_DTO_5_4_RATIO: Set Deep Color DTO to 5:4 3494 PIXEL_CLOCK_V7_DEEPCOLOR_RATIO_3_2 = 0x02, //02 - DCCG_DEEP_COLOR_DTO_3_2_RATIO: Set Deep Color DTO to 3:2 3495 PIXEL_CLOCK_V7_DEEPCOLOR_RATIO_2_1 = 0x03, //03 - DCCG_DEEP_COLOR_DTO_2_1_RATIO: Set Deep Color DTO to 2:1 3496 }; 3497 3498 /* 3499 *************************************************************************** 3500 Structures used by setdceclock 3501 *************************************************************************** 3502 */ 3503 3504 // SetDCEClock input parameter for DCE11.2( ELM and BF ) and above 3505 struct set_dce_clock_parameters_v2_1 3506 { 3507 uint32_t dceclk_10khz; // target DCE frequency in unit of 10KHZ, return real DISPCLK/DPREFCLK frequency. 3508 uint8_t dceclktype; // =0: DISPCLK =1: DPREFCLK =2: PIXCLK 3509 uint8_t dceclksrc; // ATOM_PLL0 or ATOM_GCK_DFS or ATOM_FCH_CLK or ATOM_COMBOPHY_PLLx 3510 uint8_t dceclkflag; // Bit [1:0] = PPLL ref clock source ( when ucDCEClkSrc= ATOM_PPLL0 ) 3511 uint8_t crtc_id; // ucDisp Pipe Id, ATOM_CRTC0/1/2/..., use only when ucDCEClkType = PIXCLK 3512 }; 3513 3514 //ucDCEClkType 3515 enum atom_set_dce_clock_clock_type 3516 { 3517 DCE_CLOCK_TYPE_DISPCLK = 0, 3518 DCE_CLOCK_TYPE_DPREFCLK = 1, 3519 DCE_CLOCK_TYPE_PIXELCLK = 2, // used by VBIOS internally, called by SetPixelClock 3520 }; 3521 3522 //ucDCEClkFlag when ucDCEClkType == DPREFCLK 3523 enum atom_set_dce_clock_dprefclk_flag 3524 { 3525 DCE_CLOCK_FLAG_PLL_REFCLK_SRC_MASK = 0x03, 3526 DCE_CLOCK_FLAG_PLL_REFCLK_SRC_GENERICA = 0x00, 3527 DCE_CLOCK_FLAG_PLL_REFCLK_SRC_GENLK = 0x01, 3528 DCE_CLOCK_FLAG_PLL_REFCLK_SRC_PCIE = 0x02, 3529 DCE_CLOCK_FLAG_PLL_REFCLK_SRC_XTALIN = 0x03, 3530 }; 3531 3532 //ucDCEClkFlag when ucDCEClkType == PIXCLK 3533 enum atom_set_dce_clock_pixclk_flag 3534 { 3535 DCE_CLOCK_FLAG_PCLK_DEEPCOLOR_RATIO_MASK = 0x03, 3536 DCE_CLOCK_FLAG_PCLK_DEEPCOLOR_RATIO_DIS = 0x00, //00 - DCCG_DEEP_COLOR_DTO_DISABLE: Disable Deep Color DTO 3537 DCE_CLOCK_FLAG_PCLK_DEEPCOLOR_RATIO_5_4 = 0x01, //01 - DCCG_DEEP_COLOR_DTO_5_4_RATIO: Set Deep Color DTO to 5:4 3538 DCE_CLOCK_FLAG_PCLK_DEEPCOLOR_RATIO_3_2 = 0x02, //02 - DCCG_DEEP_COLOR_DTO_3_2_RATIO: Set Deep Color DTO to 3:2 3539 DCE_CLOCK_FLAG_PCLK_DEEPCOLOR_RATIO_2_1 = 0x03, //03 - DCCG_DEEP_COLOR_DTO_2_1_RATIO: Set Deep Color DTO to 2:1 3540 DCE_CLOCK_FLAG_PIXCLK_YUV420_MODE = 0x04, 3541 }; 3542 3543 struct set_dce_clock_ps_allocation_v2_1 3544 { 3545 struct set_dce_clock_parameters_v2_1 param; 3546 uint32_t ulReserved[2]; 3547 }; 3548 3549 3550 /****************************************************************************/ 3551 // Structures used by BlankCRTC 3552 /****************************************************************************/ 3553 struct blank_crtc_parameters 3554 { 3555 uint8_t crtc_id; // enum atom_crtc_def 3556 uint8_t blanking; // enum atom_blank_crtc_command 3557 uint16_t reserved; 3558 uint32_t reserved1; 3559 }; 3560 3561 enum atom_blank_crtc_command 3562 { 3563 ATOM_BLANKING = 1, 3564 ATOM_BLANKING_OFF = 0, 3565 }; 3566 3567 /****************************************************************************/ 3568 // Structures used by enablecrtc 3569 /****************************************************************************/ 3570 struct enable_crtc_parameters 3571 { 3572 uint8_t crtc_id; // enum atom_crtc_def 3573 uint8_t enable; // ATOM_ENABLE or ATOM_DISABLE 3574 uint8_t padding[2]; 3575 }; 3576 3577 3578 /****************************************************************************/ 3579 // Structure used by EnableDispPowerGating 3580 /****************************************************************************/ 3581 struct enable_disp_power_gating_parameters_v2_1 3582 { 3583 uint8_t disp_pipe_id; // ATOM_CRTC1, ATOM_CRTC2, ... 3584 uint8_t enable; // ATOM_ENABLE or ATOM_DISABLE 3585 uint8_t padding[2]; 3586 }; 3587 3588 struct enable_disp_power_gating_ps_allocation 3589 { 3590 struct enable_disp_power_gating_parameters_v2_1 param; 3591 uint32_t ulReserved[4]; 3592 }; 3593 3594 /****************************************************************************/ 3595 // Structure used in setcrtc_usingdtdtiming 3596 /****************************************************************************/ 3597 struct set_crtc_using_dtd_timing_parameters 3598 { 3599 uint16_t h_size; 3600 uint16_t h_blanking_time; 3601 uint16_t v_size; 3602 uint16_t v_blanking_time; 3603 uint16_t h_syncoffset; 3604 uint16_t h_syncwidth; 3605 uint16_t v_syncoffset; 3606 uint16_t v_syncwidth; 3607 uint16_t modemiscinfo; 3608 uint8_t h_border; 3609 uint8_t v_border; 3610 uint8_t crtc_id; // enum atom_crtc_def 3611 uint8_t encoder_mode; // atom_encode_mode_def 3612 uint8_t padding[2]; 3613 }; 3614 3615 3616 /****************************************************************************/ 3617 // Structures used by processi2cchanneltransaction 3618 /****************************************************************************/ 3619 struct process_i2c_channel_transaction_parameters 3620 { 3621 uint8_t i2cspeed_khz; 3622 union { 3623 uint8_t regindex; 3624 uint8_t status; /* enum atom_process_i2c_flag */ 3625 } regind_status; 3626 uint16_t i2c_data_out; 3627 uint8_t flag; /* enum atom_process_i2c_status */ 3628 uint8_t trans_bytes; 3629 uint8_t slave_addr; 3630 uint8_t i2c_id; 3631 }; 3632 3633 //ucFlag 3634 enum atom_process_i2c_flag 3635 { 3636 HW_I2C_WRITE = 1, 3637 HW_I2C_READ = 0, 3638 I2C_2BYTE_ADDR = 0x02, 3639 HW_I2C_SMBUS_BYTE_WR = 0x04, 3640 }; 3641 3642 //status 3643 enum atom_process_i2c_status 3644 { 3645 HW_ASSISTED_I2C_STATUS_FAILURE =2, 3646 HW_ASSISTED_I2C_STATUS_SUCCESS =1, 3647 }; 3648 3649 3650 /****************************************************************************/ 3651 // Structures used by processauxchanneltransaction 3652 /****************************************************************************/ 3653 3654 struct process_aux_channel_transaction_parameters_v1_2 3655 { 3656 uint16_t aux_request; 3657 uint16_t dataout; 3658 uint8_t channelid; 3659 union { 3660 uint8_t reply_status; 3661 uint8_t aux_delay; 3662 } aux_status_delay; 3663 uint8_t dataout_len; 3664 uint8_t hpd_id; //=0: HPD1, =1: HPD2, =2: HPD3, =3: HPD4, =4: HPD5, =5: HPD6 3665 }; 3666 3667 3668 /****************************************************************************/ 3669 // Structures used by selectcrtc_source 3670 /****************************************************************************/ 3671 3672 struct select_crtc_source_parameters_v2_3 3673 { 3674 uint8_t crtc_id; // enum atom_crtc_def 3675 uint8_t encoder_id; // enum atom_dig_def 3676 uint8_t encode_mode; // enum atom_encode_mode_def 3677 uint8_t dst_bpc; // enum atom_panel_bit_per_color 3678 }; 3679 3680 3681 /****************************************************************************/ 3682 // Structures used by digxencodercontrol 3683 /****************************************************************************/ 3684 3685 // ucAction: 3686 enum atom_dig_encoder_control_action 3687 { 3688 ATOM_ENCODER_CMD_DISABLE_DIG = 0, 3689 ATOM_ENCODER_CMD_ENABLE_DIG = 1, 3690 ATOM_ENCODER_CMD_DP_LINK_TRAINING_START = 0x08, 3691 ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN1 = 0x09, 3692 ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN2 = 0x0a, 3693 ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN3 = 0x13, 3694 ATOM_ENCODER_CMD_DP_LINK_TRAINING_COMPLETE = 0x0b, 3695 ATOM_ENCODER_CMD_DP_VIDEO_OFF = 0x0c, 3696 ATOM_ENCODER_CMD_DP_VIDEO_ON = 0x0d, 3697 ATOM_ENCODER_CMD_SETUP_PANEL_MODE = 0x10, 3698 ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN4 = 0x14, 3699 ATOM_ENCODER_CMD_STREAM_SETUP = 0x0F, 3700 ATOM_ENCODER_CMD_LINK_SETUP = 0x11, 3701 ATOM_ENCODER_CMD_ENCODER_BLANK = 0x12, 3702 }; 3703 3704 //define ucPanelMode 3705 enum atom_dig_encoder_control_panelmode 3706 { 3707 DP_PANEL_MODE_DISABLE = 0x00, 3708 DP_PANEL_MODE_ENABLE_eDP_MODE = 0x01, 3709 DP_PANEL_MODE_ENABLE_LVLINK_MODE = 0x11, 3710 }; 3711 3712 //ucDigId 3713 enum atom_dig_encoder_control_v5_digid 3714 { 3715 ATOM_ENCODER_CONFIG_V5_DIG0_ENCODER = 0x00, 3716 ATOM_ENCODER_CONFIG_V5_DIG1_ENCODER = 0x01, 3717 ATOM_ENCODER_CONFIG_V5_DIG2_ENCODER = 0x02, 3718 ATOM_ENCODER_CONFIG_V5_DIG3_ENCODER = 0x03, 3719 ATOM_ENCODER_CONFIG_V5_DIG4_ENCODER = 0x04, 3720 ATOM_ENCODER_CONFIG_V5_DIG5_ENCODER = 0x05, 3721 ATOM_ENCODER_CONFIG_V5_DIG6_ENCODER = 0x06, 3722 ATOM_ENCODER_CONFIG_V5_DIG7_ENCODER = 0x07, 3723 }; 3724 3725 struct dig_encoder_stream_setup_parameters_v1_5 3726 { 3727 uint8_t digid; // 0~6 map to DIG0~DIG6 enum atom_dig_encoder_control_v5_digid 3728 uint8_t action; // = ATOM_ENOCODER_CMD_STREAM_SETUP 3729 uint8_t digmode; // ATOM_ENCODER_MODE_DP/ATOM_ENCODER_MODE_DVI/ATOM_ENCODER_MODE_HDMI 3730 uint8_t lanenum; // Lane number 3731 uint32_t pclk_10khz; // Pixel Clock in 10Khz 3732 uint8_t bitpercolor; 3733 uint8_t dplinkrate_270mhz;//= DP link rate/270Mhz, =6: 1.62G = 10: 2.7G, =20: 5.4Ghz, =30: 8.1Ghz etc 3734 uint8_t reserved[2]; 3735 }; 3736 3737 struct dig_encoder_link_setup_parameters_v1_5 3738 { 3739 uint8_t digid; // 0~6 map to DIG0~DIG6 enum atom_dig_encoder_control_v5_digid 3740 uint8_t action; // = ATOM_ENOCODER_CMD_LINK_SETUP 3741 uint8_t digmode; // ATOM_ENCODER_MODE_DP/ATOM_ENCODER_MODE_DVI/ATOM_ENCODER_MODE_HDMI 3742 uint8_t lanenum; // Lane number 3743 uint8_t symclk_10khz; // Symbol Clock in 10Khz 3744 uint8_t hpd_sel; 3745 uint8_t digfe_sel; // DIG stream( front-end ) selection, bit0 means DIG0 FE is enable, 3746 uint8_t reserved[2]; 3747 }; 3748 3749 struct dp_panel_mode_set_parameters_v1_5 3750 { 3751 uint8_t digid; // 0~6 map to DIG0~DIG6 enum atom_dig_encoder_control_v5_digid 3752 uint8_t action; // = ATOM_ENCODER_CMD_DPLINK_SETUP 3753 uint8_t panelmode; // enum atom_dig_encoder_control_panelmode 3754 uint8_t reserved1; 3755 uint32_t reserved2[2]; 3756 }; 3757 3758 struct dig_encoder_generic_cmd_parameters_v1_5 3759 { 3760 uint8_t digid; // 0~6 map to DIG0~DIG6 enum atom_dig_encoder_control_v5_digid 3761 uint8_t action; // = rest of generic encoder command which does not carry any parameters 3762 uint8_t reserved1[2]; 3763 uint32_t reserved2[2]; 3764 }; 3765 3766 union dig_encoder_control_parameters_v1_5 3767 { 3768 struct dig_encoder_generic_cmd_parameters_v1_5 cmd_param; 3769 struct dig_encoder_stream_setup_parameters_v1_5 stream_param; 3770 struct dig_encoder_link_setup_parameters_v1_5 link_param; 3771 struct dp_panel_mode_set_parameters_v1_5 dppanel_param; 3772 }; 3773 3774 /* 3775 *************************************************************************** 3776 Structures used by dig1transmittercontrol 3777 *************************************************************************** 3778 */ 3779 struct dig_transmitter_control_parameters_v1_6 3780 { 3781 uint8_t phyid; // 0=UNIPHYA, 1=UNIPHYB, 2=UNIPHYC, 3=UNIPHYD, 4= UNIPHYE 5=UNIPHYF 3782 uint8_t action; // define as ATOM_TRANSMITER_ACTION_xxx 3783 union { 3784 uint8_t digmode; // enum atom_encode_mode_def 3785 uint8_t dplaneset; // DP voltage swing and pre-emphasis value defined in DPCD DP_LANE_SET, "DP_LANE_SET__xDB_y_zV" 3786 } mode_laneset; 3787 uint8_t lanenum; // Lane number 1, 2, 4, 8 3788 uint32_t symclk_10khz; // Symbol Clock in 10Khz 3789 uint8_t hpdsel; // =1: HPD1, =2: HPD2, .... =6: HPD6, =0: HPD is not assigned 3790 uint8_t digfe_sel; // DIG stream( front-end ) selection, bit0 means DIG0 FE is enable, 3791 uint8_t connobj_id; // Connector Object Id defined in ObjectId.h 3792 uint8_t reserved; 3793 uint32_t reserved1; 3794 }; 3795 3796 struct dig_transmitter_control_ps_allocation_v1_6 3797 { 3798 struct dig_transmitter_control_parameters_v1_6 param; 3799 uint32_t reserved[4]; 3800 }; 3801 3802 //ucAction 3803 enum atom_dig_transmitter_control_action 3804 { 3805 ATOM_TRANSMITTER_ACTION_DISABLE = 0, 3806 ATOM_TRANSMITTER_ACTION_ENABLE = 1, 3807 ATOM_TRANSMITTER_ACTION_LCD_BLOFF = 2, 3808 ATOM_TRANSMITTER_ACTION_LCD_BLON = 3, 3809 ATOM_TRANSMITTER_ACTION_BL_BRIGHTNESS_CONTROL = 4, 3810 ATOM_TRANSMITTER_ACTION_LCD_SELFTEST_START = 5, 3811 ATOM_TRANSMITTER_ACTION_LCD_SELFTEST_STOP = 6, 3812 ATOM_TRANSMITTER_ACTION_INIT = 7, 3813 ATOM_TRANSMITTER_ACTION_DISABLE_OUTPUT = 8, 3814 ATOM_TRANSMITTER_ACTION_ENABLE_OUTPUT = 9, 3815 ATOM_TRANSMITTER_ACTION_SETUP = 10, 3816 ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH = 11, 3817 ATOM_TRANSMITTER_ACTION_POWER_ON = 12, 3818 ATOM_TRANSMITTER_ACTION_POWER_OFF = 13, 3819 }; 3820 3821 // digfe_sel 3822 enum atom_dig_transmitter_control_digfe_sel 3823 { 3824 ATOM_TRANMSITTER_V6__DIGA_SEL = 0x01, 3825 ATOM_TRANMSITTER_V6__DIGB_SEL = 0x02, 3826 ATOM_TRANMSITTER_V6__DIGC_SEL = 0x04, 3827 ATOM_TRANMSITTER_V6__DIGD_SEL = 0x08, 3828 ATOM_TRANMSITTER_V6__DIGE_SEL = 0x10, 3829 ATOM_TRANMSITTER_V6__DIGF_SEL = 0x20, 3830 ATOM_TRANMSITTER_V6__DIGG_SEL = 0x40, 3831 }; 3832 3833 3834 //ucHPDSel 3835 enum atom_dig_transmitter_control_hpd_sel 3836 { 3837 ATOM_TRANSMITTER_V6_NO_HPD_SEL = 0x00, 3838 ATOM_TRANSMITTER_V6_HPD1_SEL = 0x01, 3839 ATOM_TRANSMITTER_V6_HPD2_SEL = 0x02, 3840 ATOM_TRANSMITTER_V6_HPD3_SEL = 0x03, 3841 ATOM_TRANSMITTER_V6_HPD4_SEL = 0x04, 3842 ATOM_TRANSMITTER_V6_HPD5_SEL = 0x05, 3843 ATOM_TRANSMITTER_V6_HPD6_SEL = 0x06, 3844 }; 3845 3846 // ucDPLaneSet 3847 enum atom_dig_transmitter_control_dplaneset 3848 { 3849 DP_LANE_SET__0DB_0_4V = 0x00, 3850 DP_LANE_SET__0DB_0_6V = 0x01, 3851 DP_LANE_SET__0DB_0_8V = 0x02, 3852 DP_LANE_SET__0DB_1_2V = 0x03, 3853 DP_LANE_SET__3_5DB_0_4V = 0x08, 3854 DP_LANE_SET__3_5DB_0_6V = 0x09, 3855 DP_LANE_SET__3_5DB_0_8V = 0x0a, 3856 DP_LANE_SET__6DB_0_4V = 0x10, 3857 DP_LANE_SET__6DB_0_6V = 0x11, 3858 DP_LANE_SET__9_5DB_0_4V = 0x18, 3859 }; 3860 3861 3862 3863 /****************************************************************************/ 3864 // Structures used by ExternalEncoderControl V2.4 3865 /****************************************************************************/ 3866 3867 struct external_encoder_control_parameters_v2_4 3868 { 3869 uint16_t pixelclock_10khz; // pixel clock in 10Khz, valid when ucAction=SETUP/ENABLE_OUTPUT 3870 uint8_t config; // indicate which encoder, and DP link rate when ucAction = SETUP/ENABLE_OUTPUT 3871 uint8_t action; // 3872 uint8_t encodermode; // encoder mode, only used when ucAction = SETUP/ENABLE_OUTPUT 3873 uint8_t lanenum; // lane number, only used when ucAction = SETUP/ENABLE_OUTPUT 3874 uint8_t bitpercolor; // output bit per color, only valid when ucAction = SETUP/ENABLE_OUTPUT and ucEncodeMode= DP 3875 uint8_t hpd_id; 3876 }; 3877 3878 3879 // ucAction 3880 enum external_encoder_control_action_def 3881 { 3882 EXTERNAL_ENCODER_ACTION_V3_DISABLE_OUTPUT = 0x00, 3883 EXTERNAL_ENCODER_ACTION_V3_ENABLE_OUTPUT = 0x01, 3884 EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT = 0x07, 3885 EXTERNAL_ENCODER_ACTION_V3_ENCODER_SETUP = 0x0f, 3886 EXTERNAL_ENCODER_ACTION_V3_ENCODER_BLANKING_OFF = 0x10, 3887 EXTERNAL_ENCODER_ACTION_V3_ENCODER_BLANKING = 0x11, 3888 EXTERNAL_ENCODER_ACTION_V3_DACLOAD_DETECTION = 0x12, 3889 EXTERNAL_ENCODER_ACTION_V3_DDC_SETUP = 0x14, 3890 }; 3891 3892 // ucConfig 3893 enum external_encoder_control_v2_4_config_def 3894 { 3895 EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_MASK = 0x03, 3896 EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_1_62GHZ = 0x00, 3897 EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ = 0x01, 3898 EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_5_40GHZ = 0x02, 3899 EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_3_24GHZ = 0x03, 3900 EXTERNAL_ENCODER_CONFIG_V3_ENCODER_SEL_MAKS = 0x70, 3901 EXTERNAL_ENCODER_CONFIG_V3_ENCODER1 = 0x00, 3902 EXTERNAL_ENCODER_CONFIG_V3_ENCODER2 = 0x10, 3903 EXTERNAL_ENCODER_CONFIG_V3_ENCODER3 = 0x20, 3904 }; 3905 3906 struct external_encoder_control_ps_allocation_v2_4 3907 { 3908 struct external_encoder_control_parameters_v2_4 sExtEncoder; 3909 uint32_t reserved[2]; 3910 }; 3911 3912 3913 /* 3914 *************************************************************************** 3915 AMD ACPI Table 3916 3917 *************************************************************************** 3918 */ 3919 3920 struct amd_acpi_description_header{ 3921 uint32_t signature; 3922 uint32_t tableLength; //Length 3923 uint8_t revision; 3924 uint8_t checksum; 3925 uint8_t oemId[6]; 3926 uint8_t oemTableId[8]; //UINT64 OemTableId; 3927 uint32_t oemRevision; 3928 uint32_t creatorId; 3929 uint32_t creatorRevision; 3930 }; 3931 3932 struct uefi_acpi_vfct{ 3933 struct amd_acpi_description_header sheader; 3934 uint8_t tableUUID[16]; //0x24 3935 uint32_t vbiosimageoffset; //0x34. Offset to the first GOP_VBIOS_CONTENT block from the beginning of the stucture. 3936 uint32_t lib1Imageoffset; //0x38. Offset to the first GOP_LIB1_CONTENT block from the beginning of the stucture. 3937 uint32_t reserved[4]; //0x3C 3938 }; 3939 3940 struct vfct_image_header{ 3941 uint32_t pcibus; //0x4C 3942 uint32_t pcidevice; //0x50 3943 uint32_t pcifunction; //0x54 3944 uint16_t vendorid; //0x58 3945 uint16_t deviceid; //0x5A 3946 uint16_t ssvid; //0x5C 3947 uint16_t ssid; //0x5E 3948 uint32_t revision; //0x60 3949 uint32_t imagelength; //0x64 3950 }; 3951 3952 3953 struct gop_vbios_content { 3954 struct vfct_image_header vbiosheader; 3955 uint8_t vbioscontent[1]; 3956 }; 3957 3958 struct gop_lib1_content { 3959 struct vfct_image_header lib1header; 3960 uint8_t lib1content[1]; 3961 }; 3962 3963 3964 3965 /* 3966 *************************************************************************** 3967 Scratch Register definitions 3968 Each number below indicates which scratch regiser request, Active and 3969 Connect all share the same definitions as display_device_tag defines 3970 *************************************************************************** 3971 */ 3972 3973 enum scratch_register_def{ 3974 ATOM_DEVICE_CONNECT_INFO_DEF = 0, 3975 ATOM_BL_BRI_LEVEL_INFO_DEF = 2, 3976 ATOM_ACTIVE_INFO_DEF = 3, 3977 ATOM_LCD_INFO_DEF = 4, 3978 ATOM_DEVICE_REQ_INFO_DEF = 5, 3979 ATOM_ACC_CHANGE_INFO_DEF = 6, 3980 ATOM_PRE_OS_MODE_INFO_DEF = 7, 3981 ATOM_PRE_OS_ASSERTION_DEF = 8, //For GOP to record a 32bit assertion code, this is enabled by default in prodution GOP drivers. 3982 ATOM_INTERNAL_TIMER_INFO_DEF = 10, 3983 }; 3984 3985 enum scratch_device_connect_info_bit_def{ 3986 ATOM_DISPLAY_LCD1_CONNECT =0x0002, 3987 ATOM_DISPLAY_DFP1_CONNECT =0x0008, 3988 ATOM_DISPLAY_DFP2_CONNECT =0x0080, 3989 ATOM_DISPLAY_DFP3_CONNECT =0x0200, 3990 ATOM_DISPLAY_DFP4_CONNECT =0x0400, 3991 ATOM_DISPLAY_DFP5_CONNECT =0x0800, 3992 ATOM_DISPLAY_DFP6_CONNECT =0x0040, 3993 ATOM_DISPLAY_DFPx_CONNECT =0x0ec8, 3994 ATOM_CONNECT_INFO_DEVICE_MASK =0x0fff, 3995 }; 3996 3997 enum scratch_bl_bri_level_info_bit_def{ 3998 ATOM_CURRENT_BL_LEVEL_SHIFT =0x8, 3999 #ifndef _H2INC 4000 ATOM_CURRENT_BL_LEVEL_MASK =0x0000ff00, 4001 ATOM_DEVICE_DPMS_STATE =0x00010000, 4002 #endif 4003 }; 4004 4005 enum scratch_active_info_bits_def{ 4006 ATOM_DISPLAY_LCD1_ACTIVE =0x0002, 4007 ATOM_DISPLAY_DFP1_ACTIVE =0x0008, 4008 ATOM_DISPLAY_DFP2_ACTIVE =0x0080, 4009 ATOM_DISPLAY_DFP3_ACTIVE =0x0200, 4010 ATOM_DISPLAY_DFP4_ACTIVE =0x0400, 4011 ATOM_DISPLAY_DFP5_ACTIVE =0x0800, 4012 ATOM_DISPLAY_DFP6_ACTIVE =0x0040, 4013 ATOM_ACTIVE_INFO_DEVICE_MASK =0x0fff, 4014 }; 4015 4016 enum scratch_device_req_info_bits_def{ 4017 ATOM_DISPLAY_LCD1_REQ =0x0002, 4018 ATOM_DISPLAY_DFP1_REQ =0x0008, 4019 ATOM_DISPLAY_DFP2_REQ =0x0080, 4020 ATOM_DISPLAY_DFP3_REQ =0x0200, 4021 ATOM_DISPLAY_DFP4_REQ =0x0400, 4022 ATOM_DISPLAY_DFP5_REQ =0x0800, 4023 ATOM_DISPLAY_DFP6_REQ =0x0040, 4024 ATOM_REQ_INFO_DEVICE_MASK =0x0fff, 4025 }; 4026 4027 enum scratch_acc_change_info_bitshift_def{ 4028 ATOM_ACC_CHANGE_ACC_MODE_SHIFT =4, 4029 ATOM_ACC_CHANGE_LID_STATUS_SHIFT =6, 4030 }; 4031 4032 enum scratch_acc_change_info_bits_def{ 4033 ATOM_ACC_CHANGE_ACC_MODE =0x00000010, 4034 ATOM_ACC_CHANGE_LID_STATUS =0x00000040, 4035 }; 4036 4037 enum scratch_pre_os_mode_info_bits_def{ 4038 ATOM_PRE_OS_MODE_MASK =0x00000003, 4039 ATOM_PRE_OS_MODE_VGA =0x00000000, 4040 ATOM_PRE_OS_MODE_VESA =0x00000001, 4041 ATOM_PRE_OS_MODE_GOP =0x00000002, 4042 ATOM_PRE_OS_MODE_PIXEL_DEPTH =0x0000000C, 4043 ATOM_PRE_OS_MODE_PIXEL_FORMAT_MASK=0x000000F0, 4044 ATOM_PRE_OS_MODE_8BIT_PAL_EN =0x00000100, 4045 ATOM_ASIC_INIT_COMPLETE =0x00000200, 4046 #ifndef _H2INC 4047 ATOM_PRE_OS_MODE_NUMBER_MASK =0xFFFF0000, 4048 #endif 4049 }; 4050 4051 4052 4053 /* 4054 *************************************************************************** 4055 ATOM firmware ID header file 4056 !! Please keep it at end of the atomfirmware.h !! 4057 *************************************************************************** 4058 */ 4059 #include "atomfirmwareid.h" 4060 #pragma pack() 4061 4062 #endif 4063 4064