1 /****************************************************************************\ 2 * 3 * File Name atomfirmware.h 4 * Project This is an interface header file between atombios and OS GPU drivers for SoC15 products 5 * 6 * Description header file of general definitions for OS nd pre-OS video drivers 7 * 8 * Copyright 2014 Advanced Micro Devices, Inc. 9 * 10 * Permission is hereby granted, free of charge, to any person obtaining a copy of this software 11 * and associated documentation files (the "Software"), to deal in the Software without restriction, 12 * including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, 13 * and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, 14 * subject to the following conditions: 15 * 16 * The above copyright notice and this permission notice shall be included in all copies or substantial 17 * portions of the Software. 18 * 19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 22 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 23 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 24 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 25 * OTHER DEALINGS IN THE SOFTWARE. 26 * 27 \****************************************************************************/ 28 29 /*IMPORTANT NOTES 30 * If a change in VBIOS/Driver/Tool's interface is only needed for SoC15 and forward products, then the change is only needed in this atomfirmware.h header file. 31 * If a change in VBIOS/Driver/Tool's interface is only needed for pre-SoC15 products, then the change is only needed in atombios.h header file. 32 * If a change is needed for both pre and post SoC15 products, then the change has to be made separately and might be differently in both atomfirmware.h and atombios.h. 33 */ 34 35 #ifndef _ATOMFIRMWARE_H_ 36 #define _ATOMFIRMWARE_H_ 37 38 enum atom_bios_header_version_def{ 39 ATOM_MAJOR_VERSION =0x0003, 40 ATOM_MINOR_VERSION =0x0003, 41 }; 42 43 #ifdef _H2INC 44 #ifndef uint32_t 45 typedef unsigned long uint32_t; 46 #endif 47 48 #ifndef uint16_t 49 typedef unsigned short uint16_t; 50 #endif 51 52 #ifndef uint8_t 53 typedef unsigned char uint8_t; 54 #endif 55 #endif 56 57 enum atom_crtc_def{ 58 ATOM_CRTC1 =0, 59 ATOM_CRTC2 =1, 60 ATOM_CRTC3 =2, 61 ATOM_CRTC4 =3, 62 ATOM_CRTC5 =4, 63 ATOM_CRTC6 =5, 64 ATOM_CRTC_INVALID =0xff, 65 }; 66 67 enum atom_ppll_def{ 68 ATOM_PPLL0 =2, 69 ATOM_GCK_DFS =8, 70 ATOM_FCH_CLK =9, 71 ATOM_DP_DTO =11, 72 ATOM_COMBOPHY_PLL0 =20, 73 ATOM_COMBOPHY_PLL1 =21, 74 ATOM_COMBOPHY_PLL2 =22, 75 ATOM_COMBOPHY_PLL3 =23, 76 ATOM_COMBOPHY_PLL4 =24, 77 ATOM_COMBOPHY_PLL5 =25, 78 ATOM_PPLL_INVALID =0xff, 79 }; 80 81 // define ASIC internal encoder id ( bit vector ), used for CRTC_SourceSel 82 enum atom_dig_def{ 83 ASIC_INT_DIG1_ENCODER_ID =0x03, 84 ASIC_INT_DIG2_ENCODER_ID =0x09, 85 ASIC_INT_DIG3_ENCODER_ID =0x0a, 86 ASIC_INT_DIG4_ENCODER_ID =0x0b, 87 ASIC_INT_DIG5_ENCODER_ID =0x0c, 88 ASIC_INT_DIG6_ENCODER_ID =0x0d, 89 ASIC_INT_DIG7_ENCODER_ID =0x0e, 90 }; 91 92 //ucEncoderMode 93 enum atom_encode_mode_def 94 { 95 ATOM_ENCODER_MODE_DP =0, 96 ATOM_ENCODER_MODE_DP_SST =0, 97 ATOM_ENCODER_MODE_LVDS =1, 98 ATOM_ENCODER_MODE_DVI =2, 99 ATOM_ENCODER_MODE_HDMI =3, 100 ATOM_ENCODER_MODE_DP_AUDIO =5, 101 ATOM_ENCODER_MODE_DP_MST =5, 102 ATOM_ENCODER_MODE_CRT =15, 103 ATOM_ENCODER_MODE_DVO =16, 104 }; 105 106 enum atom_encoder_refclk_src_def{ 107 ENCODER_REFCLK_SRC_P1PLL =0, 108 ENCODER_REFCLK_SRC_P2PLL =1, 109 ENCODER_REFCLK_SRC_P3PLL =2, 110 ENCODER_REFCLK_SRC_EXTCLK =3, 111 ENCODER_REFCLK_SRC_INVALID =0xff, 112 }; 113 114 enum atom_scaler_def{ 115 ATOM_SCALER_DISABLE =0, /*scaler bypass mode, auto-center & no replication*/ 116 ATOM_SCALER_CENTER =1, //For Fudo, it's bypass and auto-center & auto replication 117 ATOM_SCALER_EXPANSION =2, /*scaler expansion by 2 tap alpha blending mode*/ 118 }; 119 120 enum atom_operation_def{ 121 ATOM_DISABLE = 0, 122 ATOM_ENABLE = 1, 123 ATOM_INIT = 7, 124 ATOM_GET_STATUS = 8, 125 }; 126 127 enum atom_embedded_display_op_def{ 128 ATOM_LCD_BL_OFF = 2, 129 ATOM_LCD_BL_OM = 3, 130 ATOM_LCD_BL_BRIGHTNESS_CONTROL = 4, 131 ATOM_LCD_SELFTEST_START = 5, 132 ATOM_LCD_SELFTEST_STOP = 6, 133 }; 134 135 enum atom_spread_spectrum_mode{ 136 ATOM_SS_CENTER_OR_DOWN_MODE_MASK = 0x01, 137 ATOM_SS_DOWN_SPREAD_MODE = 0x00, 138 ATOM_SS_CENTRE_SPREAD_MODE = 0x01, 139 ATOM_INT_OR_EXT_SS_MASK = 0x02, 140 ATOM_INTERNAL_SS_MASK = 0x00, 141 ATOM_EXTERNAL_SS_MASK = 0x02, 142 }; 143 144 /* define panel bit per color */ 145 enum atom_panel_bit_per_color{ 146 PANEL_BPC_UNDEFINE =0x00, 147 PANEL_6BIT_PER_COLOR =0x01, 148 PANEL_8BIT_PER_COLOR =0x02, 149 PANEL_10BIT_PER_COLOR =0x03, 150 PANEL_12BIT_PER_COLOR =0x04, 151 PANEL_16BIT_PER_COLOR =0x05, 152 }; 153 154 //ucVoltageType 155 enum atom_voltage_type 156 { 157 VOLTAGE_TYPE_VDDC = 1, 158 VOLTAGE_TYPE_MVDDC = 2, 159 VOLTAGE_TYPE_MVDDQ = 3, 160 VOLTAGE_TYPE_VDDCI = 4, 161 VOLTAGE_TYPE_VDDGFX = 5, 162 VOLTAGE_TYPE_PCC = 6, 163 VOLTAGE_TYPE_MVPP = 7, 164 VOLTAGE_TYPE_LEDDPM = 8, 165 VOLTAGE_TYPE_PCC_MVDD = 9, 166 VOLTAGE_TYPE_PCIE_VDDC = 10, 167 VOLTAGE_TYPE_PCIE_VDDR = 11, 168 VOLTAGE_TYPE_GENERIC_I2C_1 = 0x11, 169 VOLTAGE_TYPE_GENERIC_I2C_2 = 0x12, 170 VOLTAGE_TYPE_GENERIC_I2C_3 = 0x13, 171 VOLTAGE_TYPE_GENERIC_I2C_4 = 0x14, 172 VOLTAGE_TYPE_GENERIC_I2C_5 = 0x15, 173 VOLTAGE_TYPE_GENERIC_I2C_6 = 0x16, 174 VOLTAGE_TYPE_GENERIC_I2C_7 = 0x17, 175 VOLTAGE_TYPE_GENERIC_I2C_8 = 0x18, 176 VOLTAGE_TYPE_GENERIC_I2C_9 = 0x19, 177 VOLTAGE_TYPE_GENERIC_I2C_10 = 0x1A, 178 }; 179 180 enum atom_dgpu_vram_type{ 181 ATOM_DGPU_VRAM_TYPE_GDDR5 = 0x50, 182 ATOM_DGPU_VRAM_TYPE_HBM = 0x60, 183 }; 184 185 enum atom_dp_vs_preemph_def{ 186 DP_VS_LEVEL0_PREEMPH_LEVEL0 = 0x00, 187 DP_VS_LEVEL1_PREEMPH_LEVEL0 = 0x01, 188 DP_VS_LEVEL2_PREEMPH_LEVEL0 = 0x02, 189 DP_VS_LEVEL3_PREEMPH_LEVEL0 = 0x03, 190 DP_VS_LEVEL0_PREEMPH_LEVEL1 = 0x08, 191 DP_VS_LEVEL1_PREEMPH_LEVEL1 = 0x09, 192 DP_VS_LEVEL2_PREEMPH_LEVEL1 = 0x0a, 193 DP_VS_LEVEL0_PREEMPH_LEVEL2 = 0x10, 194 DP_VS_LEVEL1_PREEMPH_LEVEL2 = 0x11, 195 DP_VS_LEVEL0_PREEMPH_LEVEL3 = 0x18, 196 }; 197 198 199 /* 200 enum atom_string_def{ 201 asic_bus_type_pcie_string = "PCI_EXPRESS", 202 atom_fire_gl_string = "FGL", 203 atom_bios_string = "ATOM" 204 }; 205 */ 206 207 #pragma pack(1) /* BIOS data must use byte aligment*/ 208 209 enum atombios_image_offset{ 210 OFFSET_TO_ATOM_ROM_HEADER_POINTER =0x00000048, 211 OFFSET_TO_ATOM_ROM_IMAGE_SIZE =0x00000002, 212 OFFSET_TO_ATOMBIOS_ASIC_BUS_MEM_TYPE =0x94, 213 MAXSIZE_OF_ATOMBIOS_ASIC_BUS_MEM_TYPE =20, /*including the terminator 0x0!*/ 214 OFFSET_TO_GET_ATOMBIOS_NUMBER_OF_STRINGS =0x2f, 215 OFFSET_TO_GET_ATOMBIOS_STRING_START =0x6e, 216 }; 217 218 /**************************************************************************** 219 * Common header for all tables (Data table, Command function). 220 * Every table pointed in _ATOM_MASTER_DATA_TABLE has this common header. 221 * And the pointer actually points to this header. 222 ****************************************************************************/ 223 224 struct atom_common_table_header 225 { 226 uint16_t structuresize; 227 uint8_t format_revision; //mainly used for a hw function, when the parser is not backward compatible 228 uint8_t content_revision; //change it when a data table has a structure change, or a hw function has a input/output parameter change 229 }; 230 231 /**************************************************************************** 232 * Structure stores the ROM header. 233 ****************************************************************************/ 234 struct atom_rom_header_v2_2 235 { 236 struct atom_common_table_header table_header; 237 uint8_t atom_bios_string[4]; //enum atom_string_def atom_bios_string; //Signature to distinguish between Atombios and non-atombios, 238 uint16_t bios_segment_address; 239 uint16_t protectedmodeoffset; 240 uint16_t configfilenameoffset; 241 uint16_t crc_block_offset; 242 uint16_t vbios_bootupmessageoffset; 243 uint16_t int10_offset; 244 uint16_t pcibusdevinitcode; 245 uint16_t iobaseaddress; 246 uint16_t subsystem_vendor_id; 247 uint16_t subsystem_id; 248 uint16_t pci_info_offset; 249 uint16_t masterhwfunction_offset; //Offest for SW to get all command function offsets, Don't change the position 250 uint16_t masterdatatable_offset; //Offest for SW to get all data table offsets, Don't change the position 251 uint16_t reserved; 252 uint32_t pspdirtableoffset; 253 }; 254 255 /*==============================hw function portion======================================================================*/ 256 257 258 /**************************************************************************** 259 * Structures used in Command.mtb, each function name is not given here since those function could change from time to time 260 * The real functionality of each function is associated with the parameter structure version when defined 261 * For all internal cmd function definitions, please reference to atomstruct.h 262 ****************************************************************************/ 263 struct atom_master_list_of_command_functions_v2_1{ 264 uint16_t asic_init; //Function 265 uint16_t cmd_function1; //used as an internal one 266 uint16_t cmd_function2; //used as an internal one 267 uint16_t cmd_function3; //used as an internal one 268 uint16_t digxencodercontrol; //Function 269 uint16_t cmd_function5; //used as an internal one 270 uint16_t cmd_function6; //used as an internal one 271 uint16_t cmd_function7; //used as an internal one 272 uint16_t cmd_function8; //used as an internal one 273 uint16_t cmd_function9; //used as an internal one 274 uint16_t setengineclock; //Function 275 uint16_t setmemoryclock; //Function 276 uint16_t setpixelclock; //Function 277 uint16_t enabledisppowergating; //Function 278 uint16_t cmd_function14; //used as an internal one 279 uint16_t cmd_function15; //used as an internal one 280 uint16_t cmd_function16; //used as an internal one 281 uint16_t cmd_function17; //used as an internal one 282 uint16_t cmd_function18; //used as an internal one 283 uint16_t cmd_function19; //used as an internal one 284 uint16_t cmd_function20; //used as an internal one 285 uint16_t cmd_function21; //used as an internal one 286 uint16_t cmd_function22; //used as an internal one 287 uint16_t cmd_function23; //used as an internal one 288 uint16_t cmd_function24; //used as an internal one 289 uint16_t cmd_function25; //used as an internal one 290 uint16_t cmd_function26; //used as an internal one 291 uint16_t cmd_function27; //used as an internal one 292 uint16_t cmd_function28; //used as an internal one 293 uint16_t cmd_function29; //used as an internal one 294 uint16_t cmd_function30; //used as an internal one 295 uint16_t cmd_function31; //used as an internal one 296 uint16_t cmd_function32; //used as an internal one 297 uint16_t cmd_function33; //used as an internal one 298 uint16_t blankcrtc; //Function 299 uint16_t enablecrtc; //Function 300 uint16_t cmd_function36; //used as an internal one 301 uint16_t cmd_function37; //used as an internal one 302 uint16_t cmd_function38; //used as an internal one 303 uint16_t cmd_function39; //used as an internal one 304 uint16_t cmd_function40; //used as an internal one 305 uint16_t getsmuclockinfo; //Function 306 uint16_t selectcrtc_source; //Function 307 uint16_t cmd_function43; //used as an internal one 308 uint16_t cmd_function44; //used as an internal one 309 uint16_t cmd_function45; //used as an internal one 310 uint16_t setdceclock; //Function 311 uint16_t getmemoryclock; //Function 312 uint16_t getengineclock; //Function 313 uint16_t setcrtc_usingdtdtiming; //Function 314 uint16_t externalencodercontrol; //Function 315 uint16_t cmd_function51; //used as an internal one 316 uint16_t cmd_function52; //used as an internal one 317 uint16_t cmd_function53; //used as an internal one 318 uint16_t processi2cchanneltransaction;//Function 319 uint16_t cmd_function55; //used as an internal one 320 uint16_t cmd_function56; //used as an internal one 321 uint16_t cmd_function57; //used as an internal one 322 uint16_t cmd_function58; //used as an internal one 323 uint16_t cmd_function59; //used as an internal one 324 uint16_t computegpuclockparam; //Function 325 uint16_t cmd_function61; //used as an internal one 326 uint16_t cmd_function62; //used as an internal one 327 uint16_t dynamicmemorysettings; //Function function 328 uint16_t memorytraining; //Function function 329 uint16_t cmd_function65; //used as an internal one 330 uint16_t cmd_function66; //used as an internal one 331 uint16_t setvoltage; //Function 332 uint16_t cmd_function68; //used as an internal one 333 uint16_t readefusevalue; //Function 334 uint16_t cmd_function70; //used as an internal one 335 uint16_t cmd_function71; //used as an internal one 336 uint16_t cmd_function72; //used as an internal one 337 uint16_t cmd_function73; //used as an internal one 338 uint16_t cmd_function74; //used as an internal one 339 uint16_t cmd_function75; //used as an internal one 340 uint16_t dig1transmittercontrol; //Function 341 uint16_t cmd_function77; //used as an internal one 342 uint16_t processauxchanneltransaction;//Function 343 uint16_t cmd_function79; //used as an internal one 344 uint16_t getvoltageinfo; //Function 345 }; 346 347 struct atom_master_command_function_v2_1 348 { 349 struct atom_common_table_header table_header; 350 struct atom_master_list_of_command_functions_v2_1 listofcmdfunctions; 351 }; 352 353 /**************************************************************************** 354 * Structures used in every command function 355 ****************************************************************************/ 356 struct atom_function_attribute 357 { 358 uint16_t ws_in_bytes:8; //[7:0]=Size of workspace in Bytes (in multiple of a dword), 359 uint16_t ps_in_bytes:7; //[14:8]=Size of parameter space in Bytes (multiple of a dword), 360 uint16_t updated_by_util:1; //[15]=flag to indicate the function is updated by util 361 }; 362 363 364 /**************************************************************************** 365 * Common header for all hw functions. 366 * Every function pointed by _master_list_of_hw_function has this common header. 367 * And the pointer actually points to this header. 368 ****************************************************************************/ 369 struct atom_rom_hw_function_header 370 { 371 struct atom_common_table_header func_header; 372 struct atom_function_attribute func_attrib; 373 }; 374 375 376 /*==============================sw data table portion======================================================================*/ 377 /**************************************************************************** 378 * Structures used in data.mtb, each data table name is not given here since those data table could change from time to time 379 * The real name of each table is given when its data structure version is defined 380 ****************************************************************************/ 381 struct atom_master_list_of_data_tables_v2_1{ 382 uint16_t utilitypipeline; /* Offest for the utility to get parser info,Don't change this position!*/ 383 uint16_t multimedia_info; 384 uint16_t sw_datatable2; 385 uint16_t sw_datatable3; 386 uint16_t firmwareinfo; /* Shared by various SW components */ 387 uint16_t sw_datatable5; 388 uint16_t lcd_info; /* Shared by various SW components */ 389 uint16_t sw_datatable7; 390 uint16_t smu_info; 391 uint16_t sw_datatable9; 392 uint16_t sw_datatable10; 393 uint16_t vram_usagebyfirmware; /* Shared by various SW components */ 394 uint16_t gpio_pin_lut; /* Shared by various SW components */ 395 uint16_t sw_datatable13; 396 uint16_t gfx_info; 397 uint16_t powerplayinfo; /* Shared by various SW components */ 398 uint16_t sw_datatable16; 399 uint16_t sw_datatable17; 400 uint16_t sw_datatable18; 401 uint16_t sw_datatable19; 402 uint16_t sw_datatable20; 403 uint16_t sw_datatable21; 404 uint16_t displayobjectinfo; /* Shared by various SW components */ 405 uint16_t indirectioaccess; /* used as an internal one */ 406 uint16_t umc_info; /* Shared by various SW components */ 407 uint16_t sw_datatable25; 408 uint16_t sw_datatable26; 409 uint16_t dce_info; /* Shared by various SW components */ 410 uint16_t vram_info; /* Shared by various SW components */ 411 uint16_t sw_datatable29; 412 uint16_t integratedsysteminfo; /* Shared by various SW components */ 413 uint16_t asic_profiling_info; /* Shared by various SW components */ 414 uint16_t voltageobject_info; /* shared by various SW components */ 415 uint16_t sw_datatable33; 416 uint16_t sw_datatable34; 417 }; 418 419 420 struct atom_master_data_table_v2_1 421 { 422 struct atom_common_table_header table_header; 423 struct atom_master_list_of_data_tables_v2_1 listOfdatatables; 424 }; 425 426 427 struct atom_dtd_format 428 { 429 uint16_t pixclk; 430 uint16_t h_active; 431 uint16_t h_blanking_time; 432 uint16_t v_active; 433 uint16_t v_blanking_time; 434 uint16_t h_sync_offset; 435 uint16_t h_sync_width; 436 uint16_t v_sync_offset; 437 uint16_t v_syncwidth; 438 uint16_t reserved; 439 uint16_t reserved0; 440 uint8_t h_border; 441 uint8_t v_border; 442 uint16_t miscinfo; 443 uint8_t atom_mode_id; 444 uint8_t refreshrate; 445 }; 446 447 /* atom_dtd_format.modemiscinfo defintion */ 448 enum atom_dtd_format_modemiscinfo{ 449 ATOM_HSYNC_POLARITY = 0x0002, 450 ATOM_VSYNC_POLARITY = 0x0004, 451 ATOM_H_REPLICATIONBY2 = 0x0010, 452 ATOM_V_REPLICATIONBY2 = 0x0020, 453 ATOM_INTERLACE = 0x0080, 454 ATOM_COMPOSITESYNC = 0x0040, 455 }; 456 457 458 /* utilitypipeline 459 * when format_revision==1 && content_revision==1, then this an info table for atomworks to use during debug session, no structure is associated with it. 460 * the location of it can't change 461 */ 462 463 464 /* 465 *************************************************************************** 466 Data Table firmwareinfo structure 467 *************************************************************************** 468 */ 469 470 struct atom_firmware_info_v3_1 471 { 472 struct atom_common_table_header table_header; 473 uint32_t firmware_revision; 474 uint32_t bootup_sclk_in10khz; 475 uint32_t bootup_mclk_in10khz; 476 uint32_t firmware_capability; // enum atombios_firmware_capability 477 uint32_t main_call_parser_entry; /* direct address of main parser call in VBIOS binary. */ 478 uint32_t bios_scratch_reg_startaddr; // 1st bios scratch register dword address 479 uint16_t bootup_vddc_mv; 480 uint16_t bootup_vddci_mv; 481 uint16_t bootup_mvddc_mv; 482 uint16_t bootup_vddgfx_mv; 483 uint8_t mem_module_id; 484 uint8_t coolingsolution_id; /*0: Air cooling; 1: Liquid cooling ... */ 485 uint8_t reserved1[2]; 486 uint32_t mc_baseaddr_high; 487 uint32_t mc_baseaddr_low; 488 uint32_t reserved2[6]; 489 }; 490 491 /* Total 32bit cap indication */ 492 enum atombios_firmware_capability 493 { 494 ATOM_FIRMWARE_CAP_FIRMWARE_POSTED = 0x00000001, 495 ATOM_FIRMWARE_CAP_GPU_VIRTUALIZATION = 0x00000002, 496 ATOM_FIRMWARE_CAP_WMI_SUPPORT = 0x00000040, 497 }; 498 499 enum atom_cooling_solution_id{ 500 AIR_COOLING = 0x00, 501 LIQUID_COOLING = 0x01 502 }; 503 504 505 /* 506 *************************************************************************** 507 Data Table lcd_info structure 508 *************************************************************************** 509 */ 510 511 struct lcd_info_v2_1 512 { 513 struct atom_common_table_header table_header; 514 struct atom_dtd_format lcd_timing; 515 uint16_t backlight_pwm; 516 uint16_t special_handle_cap; 517 uint16_t panel_misc; 518 uint16_t lvds_max_slink_pclk; 519 uint16_t lvds_ss_percentage; 520 uint16_t lvds_ss_rate_10hz; 521 uint8_t pwr_on_digon_to_de; /*all pwr sequence numbers below are in uint of 4ms*/ 522 uint8_t pwr_on_de_to_vary_bl; 523 uint8_t pwr_down_vary_bloff_to_de; 524 uint8_t pwr_down_de_to_digoff; 525 uint8_t pwr_off_delay; 526 uint8_t pwr_on_vary_bl_to_blon; 527 uint8_t pwr_down_bloff_to_vary_bloff; 528 uint8_t panel_bpc; 529 uint8_t dpcd_edp_config_cap; 530 uint8_t dpcd_max_link_rate; 531 uint8_t dpcd_max_lane_count; 532 uint8_t dpcd_max_downspread; 533 uint8_t min_allowed_bl_level; 534 uint8_t max_allowed_bl_level; 535 uint8_t bootup_bl_level; 536 uint8_t dplvdsrxid; 537 uint32_t reserved1[8]; 538 }; 539 540 /* lcd_info_v2_1.panel_misc defintion */ 541 enum atom_lcd_info_panel_misc{ 542 ATOM_PANEL_MISC_FPDI =0x0002, 543 }; 544 545 //uceDPToLVDSRxId 546 enum atom_lcd_info_dptolvds_rx_id 547 { 548 eDP_TO_LVDS_RX_DISABLE = 0x00, // no eDP->LVDS translator chip 549 eDP_TO_LVDS_COMMON_ID = 0x01, // common eDP->LVDS translator chip without AMD SW init 550 eDP_TO_LVDS_REALTEK_ID = 0x02, // Realtek tansaltor which require AMD SW init 551 }; 552 553 554 /* 555 *************************************************************************** 556 Data Table gpio_pin_lut structure 557 *************************************************************************** 558 */ 559 560 struct atom_gpio_pin_assignment 561 { 562 uint32_t data_a_reg_index; 563 uint8_t gpio_bitshift; 564 uint8_t gpio_mask_bitshift; 565 uint8_t gpio_id; 566 uint8_t reserved; 567 }; 568 569 /* atom_gpio_pin_assignment.gpio_id definition */ 570 enum atom_gpio_pin_assignment_gpio_id { 571 I2C_HW_LANE_MUX =0x0f, /* only valid when bit7=1 */ 572 I2C_HW_ENGINE_ID_MASK =0x70, /* only valid when bit7=1 */ 573 I2C_HW_CAP =0x80, /*only when the I2C_HW_CAP is set, the pin ID is assigned to an I2C pin pair, otherwise, it's an generic GPIO pin */ 574 575 /* gpio_id pre-define id for multiple usage */ 576 /* GPIO use to control PCIE_VDDC in certain SLT board */ 577 PCIE_VDDC_CONTROL_GPIO_PINID = 56, 578 /* if PP_AC_DC_SWITCH_GPIO_PINID in Gpio_Pin_LutTable, AC/DC swithing feature is enable */ 579 PP_AC_DC_SWITCH_GPIO_PINID = 60, 580 /* VDDC_REGULATOR_VRHOT_GPIO_PINID in Gpio_Pin_LutTable, VRHot feature is enable */ 581 VDDC_VRHOT_GPIO_PINID = 61, 582 /*if VDDC_PCC_GPIO_PINID in GPIO_LUTable, Peak Current Control feature is enabled */ 583 VDDC_PCC_GPIO_PINID = 62, 584 /* Only used on certain SLT/PA board to allow utility to cut Efuse. */ 585 EFUSE_CUT_ENABLE_GPIO_PINID = 63, 586 /* ucGPIO=DRAM_SELF_REFRESH_GPIO_PIND uses for memory self refresh (ucGPIO=0, DRAM self-refresh; ucGPIO= */ 587 DRAM_SELF_REFRESH_GPIO_PINID = 64, 588 /* Thermal interrupt output->system thermal chip GPIO pin */ 589 THERMAL_INT_OUTPUT_GPIO_PINID =65, 590 }; 591 592 593 struct atom_gpio_pin_lut_v2_1 594 { 595 struct atom_common_table_header table_header; 596 /*the real number of this included in the structure is calcualted by using the (whole structure size - the header size)/size of atom_gpio_pin_lut */ 597 struct atom_gpio_pin_assignment gpio_pin[8]; 598 }; 599 600 601 /* 602 *************************************************************************** 603 Data Table vram_usagebyfirmware structure 604 *************************************************************************** 605 */ 606 607 struct vram_usagebyfirmware_v2_1 608 { 609 struct atom_common_table_header table_header; 610 uint32_t start_address_in_kb; 611 uint16_t used_by_firmware_in_kb; 612 uint16_t used_by_driver_in_kb; 613 }; 614 615 616 /* 617 *************************************************************************** 618 Data Table displayobjectinfo structure 619 *************************************************************************** 620 */ 621 622 enum atom_object_record_type_id 623 { 624 ATOM_I2C_RECORD_TYPE =1, 625 ATOM_HPD_INT_RECORD_TYPE =2, 626 ATOM_OBJECT_GPIO_CNTL_RECORD_TYPE =9, 627 ATOM_CONNECTOR_HPDPIN_LUT_RECORD_TYPE =16, 628 ATOM_CONNECTOR_AUXDDC_LUT_RECORD_TYPE =17, 629 ATOM_ENCODER_CAP_RECORD_TYPE=20, 630 ATOM_BRACKET_LAYOUT_RECORD_TYPE=21, 631 ATOM_CONNECTOR_FORCED_TMDS_CAP_RECORD_TYPE=22, 632 ATOM_RECORD_END_TYPE =0xFF, 633 }; 634 635 struct atom_common_record_header 636 { 637 uint8_t record_type; //An emun to indicate the record type 638 uint8_t record_size; //The size of the whole record in byte 639 }; 640 641 struct atom_i2c_record 642 { 643 struct atom_common_record_header record_header; //record_type = ATOM_I2C_RECORD_TYPE 644 uint8_t i2c_id; 645 uint8_t i2c_slave_addr; //The slave address, it's 0 when the record is attached to connector for DDC 646 }; 647 648 struct atom_hpd_int_record 649 { 650 struct atom_common_record_header record_header; //record_type = ATOM_HPD_INT_RECORD_TYPE 651 uint8_t pin_id; //Corresponding block in GPIO_PIN_INFO table gives the pin info 652 uint8_t plugin_pin_state; 653 }; 654 655 // Bit maps for ATOM_ENCODER_CAP_RECORD.usEncoderCap 656 enum atom_encoder_caps_def 657 { 658 ATOM_ENCODER_CAP_RECORD_HBR2 =0x01, // DP1.2 HBR2 is supported by HW encoder, it is retired in NI. the real meaning from SI is MST_EN 659 ATOM_ENCODER_CAP_RECORD_MST_EN =0x01, // from SI, this bit means DP MST is enable or not. 660 ATOM_ENCODER_CAP_RECORD_HBR2_EN =0x02, // DP1.2 HBR2 setting is qualified and HBR2 can be enabled 661 ATOM_ENCODER_CAP_RECORD_HDMI6Gbps_EN =0x04, // HDMI2.0 6Gbps enable or not. 662 ATOM_ENCODER_CAP_RECORD_HBR3_EN =0x08, // DP1.3 HBR3 is supported by board. 663 }; 664 665 struct atom_encoder_caps_record 666 { 667 struct atom_common_record_header record_header; //record_type = ATOM_ENCODER_CAP_RECORD_TYPE 668 uint32_t encodercaps; 669 }; 670 671 enum atom_connector_caps_def 672 { 673 ATOM_CONNECTOR_CAP_INTERNAL_DISPLAY = 0x01, //a cap bit to indicate that this non-embedded display connector is an internal display 674 ATOM_CONNECTOR_CAP_INTERNAL_DISPLAY_BL = 0x02, //a cap bit to indicate that this internal display requires BL control from GPU, refers to lcd_info for BL PWM freq 675 }; 676 677 struct atom_disp_connector_caps_record 678 { 679 struct atom_common_record_header record_header; 680 uint32_t connectcaps; 681 }; 682 683 //The following generic object gpio pin control record type will replace JTAG_RECORD/FPGA_CONTROL_RECORD/DVI_EXT_INPUT_RECORD above gradually 684 struct atom_gpio_pin_control_pair 685 { 686 uint8_t gpio_id; // GPIO_ID, find the corresponding ID in GPIO_LUT table 687 uint8_t gpio_pinstate; // Pin state showing how to set-up the pin 688 }; 689 690 struct atom_object_gpio_cntl_record 691 { 692 struct atom_common_record_header record_header; 693 uint8_t flag; // Future expnadibility 694 uint8_t number_of_pins; // Number of GPIO pins used to control the object 695 struct atom_gpio_pin_control_pair gpio[1]; // the real gpio pin pair determined by number of pins ucNumberOfPins 696 }; 697 698 //Definitions for GPIO pin state 699 enum atom_gpio_pin_control_pinstate_def 700 { 701 GPIO_PIN_TYPE_INPUT = 0x00, 702 GPIO_PIN_TYPE_OUTPUT = 0x10, 703 GPIO_PIN_TYPE_HW_CONTROL = 0x20, 704 705 //For GPIO_PIN_TYPE_OUTPUT the following is defined 706 GPIO_PIN_OUTPUT_STATE_MASK = 0x01, 707 GPIO_PIN_OUTPUT_STATE_SHIFT = 0, 708 GPIO_PIN_STATE_ACTIVE_LOW = 0x0, 709 GPIO_PIN_STATE_ACTIVE_HIGH = 0x1, 710 }; 711 712 // Indexes to GPIO array in GLSync record 713 // GLSync record is for Frame Lock/Gen Lock feature. 714 enum atom_glsync_record_gpio_index_def 715 { 716 ATOM_GPIO_INDEX_GLSYNC_REFCLK = 0, 717 ATOM_GPIO_INDEX_GLSYNC_HSYNC = 1, 718 ATOM_GPIO_INDEX_GLSYNC_VSYNC = 2, 719 ATOM_GPIO_INDEX_GLSYNC_SWAP_REQ = 3, 720 ATOM_GPIO_INDEX_GLSYNC_SWAP_GNT = 4, 721 ATOM_GPIO_INDEX_GLSYNC_INTERRUPT = 5, 722 ATOM_GPIO_INDEX_GLSYNC_V_RESET = 6, 723 ATOM_GPIO_INDEX_GLSYNC_SWAP_CNTL = 7, 724 ATOM_GPIO_INDEX_GLSYNC_SWAP_SEL = 8, 725 ATOM_GPIO_INDEX_GLSYNC_MAX = 9, 726 }; 727 728 729 struct atom_connector_hpdpin_lut_record //record for ATOM_CONNECTOR_HPDPIN_LUT_RECORD_TYPE 730 { 731 struct atom_common_record_header record_header; 732 uint8_t hpd_pin_map[8]; 733 }; 734 735 struct atom_connector_auxddc_lut_record //record for ATOM_CONNECTOR_AUXDDC_LUT_RECORD_TYPE 736 { 737 struct atom_common_record_header record_header; 738 uint8_t aux_ddc_map[8]; 739 }; 740 741 struct atom_connector_forced_tmds_cap_record 742 { 743 struct atom_common_record_header record_header; 744 // override TMDS capability on this connector when it operate in TMDS mode. usMaxTmdsClkRate = max TMDS Clock in Mhz/2.5 745 uint8_t maxtmdsclkrate_in2_5mhz; 746 uint8_t reserved; 747 }; 748 749 struct atom_connector_layout_info 750 { 751 uint16_t connectorobjid; 752 uint8_t connector_type; 753 uint8_t position; 754 }; 755 756 // define ATOM_CONNECTOR_LAYOUT_INFO.ucConnectorType to describe the display connector size 757 enum atom_connector_layout_info_connector_type_def 758 { 759 CONNECTOR_TYPE_DVI_D = 1, 760 761 CONNECTOR_TYPE_HDMI = 4, 762 CONNECTOR_TYPE_DISPLAY_PORT = 5, 763 CONNECTOR_TYPE_MINI_DISPLAY_PORT = 6, 764 }; 765 766 struct atom_bracket_layout_record 767 { 768 struct atom_common_record_header record_header; 769 uint8_t bracketlen; 770 uint8_t bracketwidth; 771 uint8_t conn_num; 772 uint8_t reserved; 773 struct atom_connector_layout_info conn_info[1]; 774 }; 775 776 enum atom_display_device_tag_def{ 777 ATOM_DISPLAY_LCD1_SUPPORT = 0x0002, //an embedded display is either an LVDS or eDP signal type of display 778 ATOM_DISPLAY_DFP1_SUPPORT = 0x0008, 779 ATOM_DISPLAY_DFP2_SUPPORT = 0x0080, 780 ATOM_DISPLAY_DFP3_SUPPORT = 0x0200, 781 ATOM_DISPLAY_DFP4_SUPPORT = 0x0400, 782 ATOM_DISPLAY_DFP5_SUPPORT = 0x0800, 783 ATOM_DISPLAY_DFP6_SUPPORT = 0x0040, 784 ATOM_DISPLAY_DFPx_SUPPORT = 0x0ec8, 785 }; 786 787 struct atom_display_object_path_v2 788 { 789 uint16_t display_objid; //Connector Object ID or Misc Object ID 790 uint16_t disp_recordoffset; 791 uint16_t encoderobjid; //first encoder closer to the connector, could be either an external or intenal encoder 792 uint16_t extencoderobjid; //2nd encoder after the first encoder, from the connector point of view; 793 uint16_t encoder_recordoffset; 794 uint16_t extencoder_recordoffset; 795 uint16_t device_tag; //a supported device vector, each display path starts with this.the paths are enumerated in the way of priority, a path appears first 796 uint8_t priority_id; 797 uint8_t reserved; 798 }; 799 800 struct display_object_info_table_v1_4 801 { 802 struct atom_common_table_header table_header; 803 uint16_t supporteddevices; 804 uint8_t number_of_path; 805 uint8_t reserved; 806 struct atom_display_object_path_v2 display_path[8]; //the real number of this included in the structure is calculated by using the (whole structure size - the header size- number_of_path)/size of atom_display_object_path 807 }; 808 809 810 /* 811 *************************************************************************** 812 Data Table dce_info structure 813 *************************************************************************** 814 */ 815 struct atom_display_controller_info_v4_1 816 { 817 struct atom_common_table_header table_header; 818 uint32_t display_caps; 819 uint32_t bootup_dispclk_10khz; 820 uint16_t dce_refclk_10khz; 821 uint16_t i2c_engine_refclk_10khz; 822 uint16_t dvi_ss_percentage; // in unit of 0.001% 823 uint16_t dvi_ss_rate_10hz; 824 uint16_t hdmi_ss_percentage; // in unit of 0.001% 825 uint16_t hdmi_ss_rate_10hz; 826 uint16_t dp_ss_percentage; // in unit of 0.001% 827 uint16_t dp_ss_rate_10hz; 828 uint8_t dvi_ss_mode; // enum of atom_spread_spectrum_mode 829 uint8_t hdmi_ss_mode; // enum of atom_spread_spectrum_mode 830 uint8_t dp_ss_mode; // enum of atom_spread_spectrum_mode 831 uint8_t ss_reserved; 832 uint8_t hardcode_mode_num; // a hardcode mode number defined in StandardVESA_TimingTable when a CRT or DFP EDID is not available 833 uint8_t reserved1[3]; 834 uint16_t dpphy_refclk_10khz; 835 uint16_t reserved2; 836 uint8_t dceip_min_ver; 837 uint8_t dceip_max_ver; 838 uint8_t max_disp_pipe_num; 839 uint8_t max_vbios_active_disp_pipe_num; 840 uint8_t max_ppll_num; 841 uint8_t max_disp_phy_num; 842 uint8_t max_aux_pairs; 843 uint8_t remotedisplayconfig; 844 uint8_t reserved3[8]; 845 }; 846 847 848 struct atom_display_controller_info_v4_2 849 { 850 struct atom_common_table_header table_header; 851 uint32_t display_caps; 852 uint32_t bootup_dispclk_10khz; 853 uint16_t dce_refclk_10khz; 854 uint16_t i2c_engine_refclk_10khz; 855 uint16_t dvi_ss_percentage; // in unit of 0.001% 856 uint16_t dvi_ss_rate_10hz; 857 uint16_t hdmi_ss_percentage; // in unit of 0.001% 858 uint16_t hdmi_ss_rate_10hz; 859 uint16_t dp_ss_percentage; // in unit of 0.001% 860 uint16_t dp_ss_rate_10hz; 861 uint8_t dvi_ss_mode; // enum of atom_spread_spectrum_mode 862 uint8_t hdmi_ss_mode; // enum of atom_spread_spectrum_mode 863 uint8_t dp_ss_mode; // enum of atom_spread_spectrum_mode 864 uint8_t ss_reserved; 865 uint8_t dfp_hardcode_mode_num; // DFP hardcode mode number defined in StandardVESA_TimingTable when EDID is not available 866 uint8_t dfp_hardcode_refreshrate;// DFP hardcode mode refreshrate defined in StandardVESA_TimingTable when EDID is not available 867 uint8_t vga_hardcode_mode_num; // VGA hardcode mode number defined in StandardVESA_TimingTable when EDID is not avablable 868 uint8_t vga_hardcode_refreshrate;// VGA hardcode mode number defined in StandardVESA_TimingTable when EDID is not avablable 869 uint16_t dpphy_refclk_10khz; 870 uint16_t reserved2; 871 uint8_t dcnip_min_ver; 872 uint8_t dcnip_max_ver; 873 uint8_t max_disp_pipe_num; 874 uint8_t max_vbios_active_disp_pipe_num; 875 uint8_t max_ppll_num; 876 uint8_t max_disp_phy_num; 877 uint8_t max_aux_pairs; 878 uint8_t remotedisplayconfig; 879 uint8_t reserved3[8]; 880 }; 881 882 883 enum dce_info_caps_def 884 { 885 // only for VBIOS 886 DCE_INFO_CAPS_FORCE_DISPDEV_CONNECTED =0x02, 887 // only for VBIOS 888 DCE_INFO_CAPS_DISABLE_DFP_DP_HBR2 =0x04, 889 // only for VBIOS 890 DCE_INFO_CAPS_ENABLE_INTERLAC_TIMING =0x08, 891 892 }; 893 894 /* 895 *************************************************************************** 896 Data Table ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO structure 897 *************************************************************************** 898 */ 899 struct atom_ext_display_path 900 { 901 uint16_t device_tag; //A bit vector to show what devices are supported 902 uint16_t device_acpi_enum; //16bit device ACPI id. 903 uint16_t connectorobjid; //A physical connector for displays to plug in, using object connector definitions 904 uint8_t auxddclut_index; //An index into external AUX/DDC channel LUT 905 uint8_t hpdlut_index; //An index into external HPD pin LUT 906 uint16_t ext_encoder_objid; //external encoder object id 907 uint8_t channelmapping; // if ucChannelMapping=0, using default one to one mapping 908 uint8_t chpninvert; // bit vector for up to 8 lanes, =0: P and N is not invert, =1 P and N is inverted 909 uint16_t caps; 910 uint16_t reserved; 911 }; 912 913 //usCaps 914 enum ext_display_path_cap_def 915 { 916 EXT_DISPLAY_PATH_CAPS__HBR2_DISABLE =0x0001, 917 EXT_DISPLAY_PATH_CAPS__DP_FIXED_VS_EN =0x0002, 918 EXT_DISPLAY_PATH_CAPS__EXT_CHIP_MASK =0x007C, 919 }; 920 921 struct atom_external_display_connection_info 922 { 923 struct atom_common_table_header table_header; 924 uint8_t guid[16]; // a GUID is a 16 byte long string 925 struct atom_ext_display_path path[7]; // total of fixed 7 entries. 926 uint8_t checksum; // a simple Checksum of the sum of whole structure equal to 0x0. 927 uint8_t stereopinid; // use for eDP panel 928 uint8_t remotedisplayconfig; 929 uint8_t edptolvdsrxid; 930 uint8_t fixdpvoltageswing; // usCaps[1]=1, this indicate DP_LANE_SET value 931 uint8_t reserved[3]; // for potential expansion 932 }; 933 934 /* 935 *************************************************************************** 936 Data Table integratedsysteminfo structure 937 *************************************************************************** 938 */ 939 940 struct atom_camera_dphy_timing_param 941 { 942 uint8_t profile_id; // SENSOR_PROFILES 943 uint32_t param; 944 }; 945 946 struct atom_camera_dphy_elec_param 947 { 948 uint16_t param[3]; 949 }; 950 951 struct atom_camera_module_info 952 { 953 uint8_t module_id; // 0: Rear, 1: Front right of user, 2: Front left of user 954 uint8_t module_name[8]; 955 struct atom_camera_dphy_timing_param timingparam[6]; // Exact number is under estimation and confirmation from sensor vendor 956 }; 957 958 struct atom_camera_flashlight_info 959 { 960 uint8_t flashlight_id; // 0: Rear, 1: Front 961 uint8_t name[8]; 962 }; 963 964 struct atom_camera_data 965 { 966 uint32_t versionCode; 967 struct atom_camera_module_info cameraInfo[3]; // Assuming 3 camera sensors max 968 struct atom_camera_flashlight_info flashInfo; // Assuming 1 flashlight max 969 struct atom_camera_dphy_elec_param dphy_param; 970 uint32_t crc_val; // CRC 971 }; 972 973 974 struct atom_14nm_dpphy_dvihdmi_tuningset 975 { 976 uint32_t max_symclk_in10khz; 977 uint8_t encoder_mode; //atom_encode_mode_def, =2: DVI, =3: HDMI mode 978 uint8_t phy_sel; //bit vector of phy, bit0= phya, bit1=phyb, ....bit5 = phyf 979 uint16_t margindeemph; //COMMON_MAR_DEEMPH_NOM[7:0]tx_margin_nom [15:8]deemph_gen1_nom 980 uint8_t deemph_6db_4; //COMMON_SELDEEMPH60[31:24]deemph_6db_4 981 uint8_t boostadj; //CMD_BUS_GLOBAL_FOR_TX_LANE0 [19:16]tx_boost_adj [20]tx_boost_en [23:22]tx_binary_ron_code_offset 982 uint8_t tx_driver_fifty_ohms; //COMMON_ZCALCODE_CTRL[21].tx_driver_fifty_ohms 983 uint8_t deemph_sel; //MARGIN_DEEMPH_LANE0.DEEMPH_SEL 984 }; 985 986 struct atom_14nm_dpphy_dp_setting{ 987 uint8_t dp_vs_pemph_level; //enum of atom_dp_vs_preemph_def 988 uint16_t margindeemph; //COMMON_MAR_DEEMPH_NOM[7:0]tx_margin_nom [15:8]deemph_gen1_nom 989 uint8_t deemph_6db_4; //COMMON_SELDEEMPH60[31:24]deemph_6db_4 990 uint8_t boostadj; //CMD_BUS_GLOBAL_FOR_TX_LANE0 [19:16]tx_boost_adj [20]tx_boost_en [23:22]tx_binary_ron_code_offset 991 }; 992 993 struct atom_14nm_dpphy_dp_tuningset{ 994 uint8_t phy_sel; // bit vector of phy, bit0= phya, bit1=phyb, ....bit5 = phyf 995 uint8_t version; 996 uint16_t table_size; // size of atom_14nm_dpphy_dp_tuningset 997 uint16_t reserved; 998 struct atom_14nm_dpphy_dp_setting dptuning[10]; 999 }; 1000 1001 struct atom_14nm_dig_transmitter_info_header_v4_0{ 1002 struct atom_common_table_header table_header; 1003 uint16_t pcie_phy_tmds_hdmi_macro_settings_offset; // offset of PCIEPhyTMDSHDMIMacroSettingsTbl 1004 uint16_t uniphy_vs_emph_lookup_table_offset; // offset of UniphyVSEmphLookUpTbl 1005 uint16_t uniphy_xbar_settings_table_offset; // offset of UniphyXbarSettingsTbl 1006 }; 1007 1008 struct atom_14nm_combphy_tmds_vs_set 1009 { 1010 uint8_t sym_clk; 1011 uint8_t dig_mode; 1012 uint8_t phy_sel; 1013 uint16_t common_mar_deemph_nom__margin_deemph_val; 1014 uint8_t common_seldeemph60__deemph_6db_4_val; 1015 uint8_t cmd_bus_global_for_tx_lane0__boostadj_val ; 1016 uint8_t common_zcalcode_ctrl__tx_driver_fifty_ohms_val; 1017 uint8_t margin_deemph_lane0__deemph_sel_val; 1018 }; 1019 1020 struct atom_integrated_system_info_v1_11 1021 { 1022 struct atom_common_table_header table_header; 1023 uint32_t vbios_misc; //enum of atom_system_vbiosmisc_def 1024 uint32_t gpucapinfo; //enum of atom_system_gpucapinf_def 1025 uint32_t system_config; 1026 uint32_t cpucapinfo; 1027 uint16_t gpuclk_ss_percentage; //unit of 0.001%, 1000 mean 1% 1028 uint16_t gpuclk_ss_type; 1029 uint16_t lvds_ss_percentage; //unit of 0.001%, 1000 mean 1% 1030 uint16_t lvds_ss_rate_10hz; 1031 uint16_t hdmi_ss_percentage; //unit of 0.001%, 1000 mean 1% 1032 uint16_t hdmi_ss_rate_10hz; 1033 uint16_t dvi_ss_percentage; //unit of 0.001%, 1000 mean 1% 1034 uint16_t dvi_ss_rate_10hz; 1035 uint16_t dpphy_override; // bit vector, enum of atom_sysinfo_dpphy_override_def 1036 uint16_t lvds_misc; // enum of atom_sys_info_lvds_misc_def 1037 uint16_t backlight_pwm_hz; // pwm frequency in hz 1038 uint8_t memorytype; // enum of atom_sys_mem_type 1039 uint8_t umachannelnumber; // number of memory channels 1040 uint8_t pwr_on_digon_to_de; /* all pwr sequence numbers below are in uint of 4ms */ 1041 uint8_t pwr_on_de_to_vary_bl; 1042 uint8_t pwr_down_vary_bloff_to_de; 1043 uint8_t pwr_down_de_to_digoff; 1044 uint8_t pwr_off_delay; 1045 uint8_t pwr_on_vary_bl_to_blon; 1046 uint8_t pwr_down_bloff_to_vary_bloff; 1047 uint8_t min_allowed_bl_level; 1048 struct atom_external_display_connection_info extdispconninfo; 1049 struct atom_14nm_dpphy_dvihdmi_tuningset dvi_tuningset; 1050 struct atom_14nm_dpphy_dvihdmi_tuningset hdmi_tuningset; 1051 struct atom_14nm_dpphy_dvihdmi_tuningset hdmi6g_tuningset; 1052 struct atom_14nm_dpphy_dp_tuningset dp_tuningset; 1053 struct atom_14nm_dpphy_dp_tuningset dp_hbr3_tuningset; 1054 struct atom_camera_data camera_info; 1055 uint32_t reserved[138]; 1056 }; 1057 1058 1059 // system_config 1060 enum atom_system_vbiosmisc_def{ 1061 INTEGRATED_SYSTEM_INFO__GET_EDID_CALLBACK_FUNC_SUPPORT = 0x01, 1062 }; 1063 1064 1065 // gpucapinfo 1066 enum atom_system_gpucapinf_def{ 1067 SYS_INFO_GPUCAPS__ENABEL_DFS_BYPASS = 0x10, 1068 }; 1069 1070 //dpphy_override 1071 enum atom_sysinfo_dpphy_override_def{ 1072 ATOM_ENABLE_DVI_TUNINGSET = 0x01, 1073 ATOM_ENABLE_HDMI_TUNINGSET = 0x02, 1074 ATOM_ENABLE_HDMI6G_TUNINGSET = 0x04, 1075 ATOM_ENABLE_DP_TUNINGSET = 0x08, 1076 ATOM_ENABLE_DP_HBR3_TUNINGSET = 0x10, 1077 }; 1078 1079 //lvds_misc 1080 enum atom_sys_info_lvds_misc_def 1081 { 1082 SYS_INFO_LVDS_MISC_888_FPDI_MODE =0x01, 1083 SYS_INFO_LVDS_MISC_888_BPC_MODE =0x04, 1084 SYS_INFO_LVDS_MISC_OVERRIDE_EN =0x08, 1085 }; 1086 1087 1088 //memorytype DMI Type 17 offset 12h - Memory Type 1089 enum atom_dmi_t17_mem_type_def{ 1090 OtherMemType = 0x01, ///< Assign 01 to Other 1091 UnknownMemType, ///< Assign 02 to Unknown 1092 DramMemType, ///< Assign 03 to DRAM 1093 EdramMemType, ///< Assign 04 to EDRAM 1094 VramMemType, ///< Assign 05 to VRAM 1095 SramMemType, ///< Assign 06 to SRAM 1096 RamMemType, ///< Assign 07 to RAM 1097 RomMemType, ///< Assign 08 to ROM 1098 FlashMemType, ///< Assign 09 to Flash 1099 EepromMemType, ///< Assign 10 to EEPROM 1100 FepromMemType, ///< Assign 11 to FEPROM 1101 EpromMemType, ///< Assign 12 to EPROM 1102 CdramMemType, ///< Assign 13 to CDRAM 1103 ThreeDramMemType, ///< Assign 14 to 3DRAM 1104 SdramMemType, ///< Assign 15 to SDRAM 1105 SgramMemType, ///< Assign 16 to SGRAM 1106 RdramMemType, ///< Assign 17 to RDRAM 1107 DdrMemType, ///< Assign 18 to DDR 1108 Ddr2MemType, ///< Assign 19 to DDR2 1109 Ddr2FbdimmMemType, ///< Assign 20 to DDR2 FB-DIMM 1110 Ddr3MemType = 0x18, ///< Assign 24 to DDR3 1111 Fbd2MemType, ///< Assign 25 to FBD2 1112 Ddr4MemType, ///< Assign 26 to DDR4 1113 LpDdrMemType, ///< Assign 27 to LPDDR 1114 LpDdr2MemType, ///< Assign 28 to LPDDR2 1115 LpDdr3MemType, ///< Assign 29 to LPDDR3 1116 LpDdr4MemType, ///< Assign 30 to LPDDR4 1117 }; 1118 1119 1120 // this Table is used starting from NL/AM, used by SBIOS and pass the IntegratedSystemInfoTable/PowerPlayInfoTable/SystemCameraInfoTable 1121 struct atom_fusion_system_info_v4 1122 { 1123 struct atom_integrated_system_info_v1_11 sysinfo; // refer to ATOM_INTEGRATED_SYSTEM_INFO_V1_8 definition 1124 uint32_t powerplayinfo[256]; // Reserve 1024 bytes space for PowerPlayInfoTable 1125 }; 1126 1127 1128 /* 1129 *************************************************************************** 1130 Data Table gfx_info structure 1131 *************************************************************************** 1132 */ 1133 1134 struct atom_gfx_info_v2_2 1135 { 1136 struct atom_common_table_header table_header; 1137 uint8_t gfxip_min_ver; 1138 uint8_t gfxip_max_ver; 1139 uint8_t max_shader_engines; 1140 uint8_t max_tile_pipes; 1141 uint8_t max_cu_per_sh; 1142 uint8_t max_sh_per_se; 1143 uint8_t max_backends_per_se; 1144 uint8_t max_texture_channel_caches; 1145 uint32_t regaddr_cp_dma_src_addr; 1146 uint32_t regaddr_cp_dma_src_addr_hi; 1147 uint32_t regaddr_cp_dma_dst_addr; 1148 uint32_t regaddr_cp_dma_dst_addr_hi; 1149 uint32_t regaddr_cp_dma_command; 1150 uint32_t regaddr_cp_status; 1151 uint32_t regaddr_rlc_gpu_clock_32; 1152 uint32_t rlc_gpu_timer_refclk; 1153 }; 1154 1155 1156 1157 /* 1158 *************************************************************************** 1159 Data Table smu_info structure 1160 *************************************************************************** 1161 */ 1162 struct atom_smu_info_v3_1 1163 { 1164 struct atom_common_table_header table_header; 1165 uint8_t smuip_min_ver; 1166 uint8_t smuip_max_ver; 1167 uint8_t smu_rsd1; 1168 uint8_t gpuclk_ss_mode; // enum of atom_spread_spectrum_mode 1169 uint16_t sclk_ss_percentage; 1170 uint16_t sclk_ss_rate_10hz; 1171 uint16_t gpuclk_ss_percentage; // in unit of 0.001% 1172 uint16_t gpuclk_ss_rate_10hz; 1173 uint32_t core_refclk_10khz; 1174 uint8_t ac_dc_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for AC/DC switching, =0xff means invalid 1175 uint8_t ac_dc_polarity; // GPIO polarity for AC/DC switching 1176 uint8_t vr0hot_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for VR0 HOT event, =0xff means invalid 1177 uint8_t vr0hot_polarity; // GPIO polarity for VR0 HOT event 1178 uint8_t vr1hot_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for VR1 HOT event , =0xff means invalid 1179 uint8_t vr1hot_polarity; // GPIO polarity for VR1 HOT event 1180 uint8_t fw_ctf_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for CTF, =0xff means invalid 1181 uint8_t fw_ctf_polarity; // GPIO polarity for CTF 1182 }; 1183 1184 1185 1186 /* 1187 *************************************************************************** 1188 Data Table asic_profiling_info structure 1189 *************************************************************************** 1190 */ 1191 struct atom_asic_profiling_info_v4_1 1192 { 1193 struct atom_common_table_header table_header; 1194 uint32_t maxvddc; 1195 uint32_t minvddc; 1196 uint32_t avfs_meannsigma_acontant0; 1197 uint32_t avfs_meannsigma_acontant1; 1198 uint32_t avfs_meannsigma_acontant2; 1199 uint16_t avfs_meannsigma_dc_tol_sigma; 1200 uint16_t avfs_meannsigma_platform_mean; 1201 uint16_t avfs_meannsigma_platform_sigma; 1202 uint32_t gb_vdroop_table_cksoff_a0; 1203 uint32_t gb_vdroop_table_cksoff_a1; 1204 uint32_t gb_vdroop_table_cksoff_a2; 1205 uint32_t gb_vdroop_table_ckson_a0; 1206 uint32_t gb_vdroop_table_ckson_a1; 1207 uint32_t gb_vdroop_table_ckson_a2; 1208 uint32_t avfsgb_fuse_table_cksoff_m1; 1209 uint32_t avfsgb_fuse_table_cksoff_m2; 1210 uint32_t avfsgb_fuse_table_cksoff_b; 1211 uint32_t avfsgb_fuse_table_ckson_m1; 1212 uint32_t avfsgb_fuse_table_ckson_m2; 1213 uint32_t avfsgb_fuse_table_ckson_b; 1214 uint16_t max_voltage_0_25mv; 1215 uint8_t enable_gb_vdroop_table_cksoff; 1216 uint8_t enable_gb_vdroop_table_ckson; 1217 uint8_t enable_gb_fuse_table_cksoff; 1218 uint8_t enable_gb_fuse_table_ckson; 1219 uint16_t psm_age_comfactor; 1220 uint8_t enable_apply_avfs_cksoff_voltage; 1221 uint8_t reserved; 1222 uint32_t dispclk2gfxclk_a; 1223 uint32_t dispclk2gfxclk_b; 1224 uint32_t dispclk2gfxclk_c; 1225 uint32_t pixclk2gfxclk_a; 1226 uint32_t pixclk2gfxclk_b; 1227 uint32_t pixclk2gfxclk_c; 1228 uint32_t dcefclk2gfxclk_a; 1229 uint32_t dcefclk2gfxclk_b; 1230 uint32_t dcefclk2gfxclk_c; 1231 uint32_t phyclk2gfxclk_a; 1232 uint32_t phyclk2gfxclk_b; 1233 uint32_t phyclk2gfxclk_c; 1234 }; 1235 1236 1237 /* 1238 *************************************************************************** 1239 Data Table multimedia_info structure 1240 *************************************************************************** 1241 */ 1242 struct atom_multimedia_info_v2_1 1243 { 1244 struct atom_common_table_header table_header; 1245 uint8_t uvdip_min_ver; 1246 uint8_t uvdip_max_ver; 1247 uint8_t vceip_min_ver; 1248 uint8_t vceip_max_ver; 1249 uint16_t uvd_enc_max_input_width_pixels; 1250 uint16_t uvd_enc_max_input_height_pixels; 1251 uint16_t vce_enc_max_input_width_pixels; 1252 uint16_t vce_enc_max_input_height_pixels; 1253 uint32_t uvd_enc_max_bandwidth; // 16x16 pixels/sec, codec independent 1254 uint32_t vce_enc_max_bandwidth; // 16x16 pixels/sec, codec independent 1255 }; 1256 1257 1258 /* 1259 *************************************************************************** 1260 Data Table umc_info structure 1261 *************************************************************************** 1262 */ 1263 struct atom_umc_info_v3_1 1264 { 1265 struct atom_common_table_header table_header; 1266 uint32_t ucode_version; 1267 uint32_t ucode_rom_startaddr; 1268 uint32_t ucode_length; 1269 uint16_t umc_reg_init_offset; 1270 uint16_t customer_ucode_name_offset; 1271 uint16_t mclk_ss_percentage; 1272 uint16_t mclk_ss_rate_10hz; 1273 uint8_t umcip_min_ver; 1274 uint8_t umcip_max_ver; 1275 uint8_t vram_type; //enum of atom_dgpu_vram_type 1276 uint8_t umc_config; 1277 uint32_t mem_refclk_10khz; 1278 }; 1279 1280 1281 /* 1282 *************************************************************************** 1283 Data Table vram_info structure 1284 *************************************************************************** 1285 */ 1286 struct atom_vram_module_v9 1287 { 1288 // Design Specific Values 1289 uint32_t memory_size; // Total memory size in unit of MB for CONFIG_MEMSIZE zeros 1290 uint32_t channel_enable; // for 32 channel ASIC usage 1291 uint32_t umcch_addrcfg; 1292 uint32_t umcch_addrsel; 1293 uint32_t umcch_colsel; 1294 uint16_t vram_module_size; // Size of atom_vram_module_v9 1295 uint8_t ext_memory_id; // Current memory module ID 1296 uint8_t memory_type; // enum of atom_dgpu_vram_type 1297 uint8_t channel_num; // Number of mem. channels supported in this module 1298 uint8_t channel_width; // CHANNEL_16BIT/CHANNEL_32BIT/CHANNEL_64BIT 1299 uint8_t density; // _8Mx32, _16Mx32, _16Mx16, _32Mx16 1300 uint8_t tunningset_id; // MC phy registers set per. 1301 uint8_t vender_rev_id; // [7:4] Revision, [3:0] Vendor code 1302 uint8_t refreshrate; // [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64ms) 1303 uint16_t vram_rsd2; // reserved 1304 char dram_pnstring[20]; // part number end with '0'. 1305 }; 1306 1307 1308 struct atom_vram_info_header_v2_3 1309 { 1310 struct atom_common_table_header table_header; 1311 uint16_t mem_adjust_tbloffset; // offset of atom_umc_init_reg_block structure for memory vendor specific UMC adjust setting 1312 uint16_t mem_clk_patch_tbloffset; // offset of atom_umc_init_reg_block structure for memory clock specific UMC setting 1313 uint16_t mc_adjust_pertile_tbloffset; // offset of atom_umc_init_reg_block structure for Per Byte Offset Preset Settings 1314 uint16_t mc_phyinit_tbloffset; // offset of atom_umc_init_reg_block structure for MC phy init set 1315 uint16_t dram_data_remap_tbloffset; // reserved for now 1316 uint16_t vram_rsd2[3]; 1317 uint8_t vram_module_num; // indicate number of VRAM module 1318 uint8_t vram_rsd1[2]; 1319 uint8_t mc_phy_tile_num; // indicate the MCD tile number which use in DramDataRemapTbl and usMcAdjustPerTileTblOffset 1320 struct atom_vram_module_v9 vram_module[16]; // just for allocation, real number of blocks is in ucNumOfVRAMModule; 1321 }; 1322 1323 struct atom_umc_register_addr_info{ 1324 uint32_t umc_register_addr:24; 1325 uint32_t umc_reg_type_ind:1; 1326 uint32_t umc_reg_rsvd:7; 1327 }; 1328 1329 //atom_umc_register_addr_info. 1330 enum atom_umc_register_addr_info_flag{ 1331 b3ATOM_UMC_REG_ADD_INFO_INDIRECT_ACCESS =0x01, 1332 }; 1333 1334 union atom_umc_register_addr_info_access 1335 { 1336 struct atom_umc_register_addr_info umc_reg_addr; 1337 uint32_t u32umc_reg_addr; 1338 }; 1339 1340 struct atom_umc_reg_setting_id_config{ 1341 uint32_t memclockrange:24; 1342 uint32_t mem_blk_id:8; 1343 }; 1344 1345 union atom_umc_reg_setting_id_config_access 1346 { 1347 struct atom_umc_reg_setting_id_config umc_id_access; 1348 uint32_t u32umc_id_access; 1349 }; 1350 1351 struct atom_umc_reg_setting_data_block{ 1352 union atom_umc_reg_setting_id_config_access block_id; 1353 uint32_t u32umc_reg_data[1]; 1354 }; 1355 1356 struct atom_umc_init_reg_block{ 1357 uint16_t umc_reg_num; 1358 uint16_t reserved; 1359 union atom_umc_register_addr_info_access umc_reg_list[1]; //for allocation purpose, the real number come from umc_reg_num; 1360 struct atom_umc_reg_setting_data_block umc_reg_setting_list[1]; 1361 }; 1362 1363 1364 /* 1365 *************************************************************************** 1366 Data Table voltageobject_info structure 1367 *************************************************************************** 1368 */ 1369 struct atom_i2c_data_entry 1370 { 1371 uint16_t i2c_reg_index; // i2c register address, can be up to 16bit 1372 uint16_t i2c_reg_data; // i2c register data, can be up to 16bit 1373 }; 1374 1375 struct atom_voltage_object_header_v4{ 1376 uint8_t voltage_type; //enum atom_voltage_type 1377 uint8_t voltage_mode; //enum atom_voltage_object_mode 1378 uint16_t object_size; //Size of Object 1379 }; 1380 1381 // atom_voltage_object_header_v4.voltage_mode 1382 enum atom_voltage_object_mode 1383 { 1384 VOLTAGE_OBJ_GPIO_LUT = 0, //VOLTAGE and GPIO Lookup table ->atom_gpio_voltage_object_v4 1385 VOLTAGE_OBJ_VR_I2C_INIT_SEQ = 3, //VOLTAGE REGULATOR INIT sequece through I2C -> atom_i2c_voltage_object_v4 1386 VOLTAGE_OBJ_PHASE_LUT = 4, //Set Vregulator Phase lookup table ->atom_gpio_voltage_object_v4 1387 VOLTAGE_OBJ_SVID2 = 7, //Indicate voltage control by SVID2 ->atom_svid2_voltage_object_v4 1388 VOLTAGE_OBJ_EVV = 8, 1389 VOLTAGE_OBJ_MERGED_POWER = 9, 1390 }; 1391 1392 struct atom_i2c_voltage_object_v4 1393 { 1394 struct atom_voltage_object_header_v4 header; // voltage mode = VOLTAGE_OBJ_VR_I2C_INIT_SEQ 1395 uint8_t regulator_id; //Indicate Voltage Regulator Id 1396 uint8_t i2c_id; 1397 uint8_t i2c_slave_addr; 1398 uint8_t i2c_control_offset; 1399 uint8_t i2c_flag; // Bit0: 0 - One byte data; 1 - Two byte data 1400 uint8_t i2c_speed; // =0, use default i2c speed, otherwise use it in unit of kHz. 1401 uint8_t reserved[2]; 1402 struct atom_i2c_data_entry i2cdatalut[1]; // end with 0xff 1403 }; 1404 1405 // ATOM_I2C_VOLTAGE_OBJECT_V3.ucVoltageControlFlag 1406 enum atom_i2c_voltage_control_flag 1407 { 1408 VOLTAGE_DATA_ONE_BYTE = 0, 1409 VOLTAGE_DATA_TWO_BYTE = 1, 1410 }; 1411 1412 1413 struct atom_voltage_gpio_map_lut 1414 { 1415 uint32_t voltage_gpio_reg_val; // The Voltage ID which is used to program GPIO register 1416 uint16_t voltage_level_mv; // The corresponding Voltage Value, in mV 1417 }; 1418 1419 struct atom_gpio_voltage_object_v4 1420 { 1421 struct atom_voltage_object_header_v4 header; // voltage mode = VOLTAGE_OBJ_GPIO_LUT or VOLTAGE_OBJ_PHASE_LUT 1422 uint8_t gpio_control_id; // default is 0 which indicate control through CG VID mode 1423 uint8_t gpio_entry_num; // indiate the entry numbers of Votlage/Gpio value Look up table 1424 uint8_t phase_delay_us; // phase delay in unit of micro second 1425 uint8_t reserved; 1426 uint32_t gpio_mask_val; // GPIO Mask value 1427 struct atom_voltage_gpio_map_lut voltage_gpio_lut[1]; 1428 }; 1429 1430 struct atom_svid2_voltage_object_v4 1431 { 1432 struct atom_voltage_object_header_v4 header; // voltage mode = VOLTAGE_OBJ_SVID2 1433 uint8_t loadline_psi1; // bit4:0= loadline setting ( Core Loadline trim and offset trim ), bit5=0:PSI1_L disable =1: PSI1_L enable 1434 uint8_t psi0_l_vid_thresd; // VR PSI0_L VID threshold 1435 uint8_t psi0_enable; // 1436 uint8_t maxvstep; 1437 uint8_t telemetry_offset; 1438 uint8_t telemetry_gain; 1439 uint16_t reserved1; 1440 }; 1441 1442 struct atom_merged_voltage_object_v4 1443 { 1444 struct atom_voltage_object_header_v4 header; // voltage mode = VOLTAGE_OBJ_MERGED_POWER 1445 uint8_t merged_powerrail_type; //enum atom_voltage_type 1446 uint8_t reserved[3]; 1447 }; 1448 1449 union atom_voltage_object_v4{ 1450 struct atom_gpio_voltage_object_v4 gpio_voltage_obj; 1451 struct atom_i2c_voltage_object_v4 i2c_voltage_obj; 1452 struct atom_svid2_voltage_object_v4 svid2_voltage_obj; 1453 struct atom_merged_voltage_object_v4 merged_voltage_obj; 1454 }; 1455 1456 struct atom_voltage_objects_info_v4_1 1457 { 1458 struct atom_common_table_header table_header; 1459 union atom_voltage_object_v4 voltage_object[1]; //Info for Voltage control 1460 }; 1461 1462 1463 /* 1464 *************************************************************************** 1465 All Command Function structure definition 1466 *************************************************************************** 1467 */ 1468 1469 /* 1470 *************************************************************************** 1471 Structures used by asic_init 1472 *************************************************************************** 1473 */ 1474 1475 struct asic_init_engine_parameters 1476 { 1477 uint32_t sclkfreqin10khz:24; 1478 uint32_t engineflag:8; /* enum atom_asic_init_engine_flag */ 1479 }; 1480 1481 struct asic_init_mem_parameters 1482 { 1483 uint32_t mclkfreqin10khz:24; 1484 uint32_t memflag:8; /* enum atom_asic_init_mem_flag */ 1485 }; 1486 1487 struct asic_init_parameters_v2_1 1488 { 1489 struct asic_init_engine_parameters engineparam; 1490 struct asic_init_mem_parameters memparam; 1491 }; 1492 1493 struct asic_init_ps_allocation_v2_1 1494 { 1495 struct asic_init_parameters_v2_1 param; 1496 uint32_t reserved[16]; 1497 }; 1498 1499 1500 enum atom_asic_init_engine_flag 1501 { 1502 b3NORMAL_ENGINE_INIT = 0, 1503 b3SRIOV_SKIP_ASIC_INIT = 0x02, 1504 b3SRIOV_LOAD_UCODE = 0x40, 1505 }; 1506 1507 enum atom_asic_init_mem_flag 1508 { 1509 b3NORMAL_MEM_INIT = 0, 1510 b3DRAM_SELF_REFRESH_EXIT =0x20, 1511 }; 1512 1513 /* 1514 *************************************************************************** 1515 Structures used by setengineclock 1516 *************************************************************************** 1517 */ 1518 1519 struct set_engine_clock_parameters_v2_1 1520 { 1521 uint32_t sclkfreqin10khz:24; 1522 uint32_t sclkflag:8; /* enum atom_set_engine_mem_clock_flag, */ 1523 uint32_t reserved[10]; 1524 }; 1525 1526 struct set_engine_clock_ps_allocation_v2_1 1527 { 1528 struct set_engine_clock_parameters_v2_1 clockinfo; 1529 uint32_t reserved[10]; 1530 }; 1531 1532 1533 enum atom_set_engine_mem_clock_flag 1534 { 1535 b3NORMAL_CHANGE_CLOCK = 0, 1536 b3FIRST_TIME_CHANGE_CLOCK = 0x08, 1537 b3STORE_DPM_TRAINGING = 0x40, //Applicable to memory clock change,when set, it store specific DPM mode training result 1538 }; 1539 1540 /* 1541 *************************************************************************** 1542 Structures used by getengineclock 1543 *************************************************************************** 1544 */ 1545 struct get_engine_clock_parameter 1546 { 1547 uint32_t sclk_10khz; // current engine speed in 10KHz unit 1548 uint32_t reserved; 1549 }; 1550 1551 /* 1552 *************************************************************************** 1553 Structures used by setmemoryclock 1554 *************************************************************************** 1555 */ 1556 struct set_memory_clock_parameters_v2_1 1557 { 1558 uint32_t mclkfreqin10khz:24; 1559 uint32_t mclkflag:8; /* enum atom_set_engine_mem_clock_flag, */ 1560 uint32_t reserved[10]; 1561 }; 1562 1563 struct set_memory_clock_ps_allocation_v2_1 1564 { 1565 struct set_memory_clock_parameters_v2_1 clockinfo; 1566 uint32_t reserved[10]; 1567 }; 1568 1569 1570 /* 1571 *************************************************************************** 1572 Structures used by getmemoryclock 1573 *************************************************************************** 1574 */ 1575 struct get_memory_clock_parameter 1576 { 1577 uint32_t mclk_10khz; // current engine speed in 10KHz unit 1578 uint32_t reserved; 1579 }; 1580 1581 1582 1583 /* 1584 *************************************************************************** 1585 Structures used by setvoltage 1586 *************************************************************************** 1587 */ 1588 1589 struct set_voltage_parameters_v1_4 1590 { 1591 uint8_t voltagetype; /* enum atom_voltage_type */ 1592 uint8_t command; /* Indicate action: Set voltage level, enum atom_set_voltage_command */ 1593 uint16_t vlevel_mv; /* real voltage level in unit of mv or Voltage Phase (0, 1, 2, .. ) */ 1594 }; 1595 1596 //set_voltage_parameters_v2_1.voltagemode 1597 enum atom_set_voltage_command{ 1598 ATOM_SET_VOLTAGE = 0, 1599 ATOM_INIT_VOLTAGE_REGULATOR = 3, 1600 ATOM_SET_VOLTAGE_PHASE = 4, 1601 ATOM_GET_LEAKAGE_ID = 8, 1602 }; 1603 1604 struct set_voltage_ps_allocation_v1_4 1605 { 1606 struct set_voltage_parameters_v1_4 setvoltageparam; 1607 uint32_t reserved[10]; 1608 }; 1609 1610 1611 /* 1612 *************************************************************************** 1613 Structures used by computegpuclockparam 1614 *************************************************************************** 1615 */ 1616 1617 //ATOM_COMPUTE_CLOCK_FREQ.ulComputeClockFlag 1618 enum atom_gpu_clock_type 1619 { 1620 COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK =0x00, 1621 COMPUTE_GPUCLK_INPUT_FLAG_GFXCLK =0x01, 1622 COMPUTE_GPUCLK_INPUT_FLAG_UCLK =0x02, 1623 }; 1624 1625 struct compute_gpu_clock_input_parameter_v1_8 1626 { 1627 uint32_t gpuclock_10khz:24; //Input= target clock, output = actual clock 1628 uint32_t gpu_clock_type:8; //Input indicate clock type: enum atom_gpu_clock_type 1629 uint32_t reserved[5]; 1630 }; 1631 1632 1633 struct compute_gpu_clock_output_parameter_v1_8 1634 { 1635 uint32_t gpuclock_10khz:24; //Input= target clock, output = actual clock 1636 uint32_t dfs_did:8; //return parameter: DFS divider which is used to program to register directly 1637 uint32_t pll_fb_mult; //Feedback Multiplier, bit 8:0 int, bit 15:12 post_div, bit 31:16 frac 1638 uint32_t pll_ss_fbsmult; // Spread FB Mult: bit 8:0 int, bit 31:16 frac 1639 uint16_t pll_ss_slew_frac; 1640 uint8_t pll_ss_enable; 1641 uint8_t reserved; 1642 uint32_t reserved1[2]; 1643 }; 1644 1645 1646 1647 /* 1648 *************************************************************************** 1649 Structures used by ReadEfuseValue 1650 *************************************************************************** 1651 */ 1652 1653 struct read_efuse_input_parameters_v3_1 1654 { 1655 uint16_t efuse_start_index; 1656 uint8_t reserved; 1657 uint8_t bitslen; 1658 }; 1659 1660 // ReadEfuseValue input/output parameter 1661 union read_efuse_value_parameters_v3_1 1662 { 1663 struct read_efuse_input_parameters_v3_1 efuse_info; 1664 uint32_t efusevalue; 1665 }; 1666 1667 1668 /* 1669 *************************************************************************** 1670 Structures used by getsmuclockinfo 1671 *************************************************************************** 1672 */ 1673 struct atom_get_smu_clock_info_parameters_v3_1 1674 { 1675 uint8_t syspll_id; // 0= syspll0, 1=syspll1, 2=syspll2 1676 uint8_t clk_id; // atom_smu9_syspll0_clock_id (only valid when command == GET_SMU_CLOCK_INFO_V3_1_GET_CLOCK_FREQ ) 1677 uint8_t command; // enum of atom_get_smu_clock_info_command 1678 uint8_t dfsdid; // =0: get DFS DID from register, >0, give DFS divider, (only valid when command == GET_SMU_CLOCK_INFO_V3_1_GET_CLOCK_FREQ ) 1679 }; 1680 1681 enum atom_get_smu_clock_info_command 1682 { 1683 GET_SMU_CLOCK_INFO_V3_1_GET_CLOCK_FREQ = 0, 1684 GET_SMU_CLOCK_INFO_V3_1_GET_PLLVCO_FREQ = 1, 1685 GET_SMU_CLOCK_INFO_V3_1_GET_PLLREFCLK_FREQ = 2, 1686 }; 1687 1688 enum atom_smu9_syspll0_clock_id 1689 { 1690 SMU9_SYSPLL0_SMNCLK_ID = 0, // SMNCLK 1691 SMU9_SYSPLL0_SOCCLK_ID = 1, // SOCCLK (FCLK) 1692 SMU9_SYSPLL0_MP0CLK_ID = 2, // MP0CLK 1693 SMU9_SYSPLL0_MP1CLK_ID = 3, // MP1CLK 1694 SMU9_SYSPLL0_LCLK_ID = 4, // LCLK 1695 SMU9_SYSPLL0_DCLK_ID = 5, // DCLK 1696 SMU9_SYSPLL0_VCLK_ID = 6, // VCLK 1697 SMU9_SYSPLL0_ECLK_ID = 7, // ECLK 1698 SMU9_SYSPLL0_DCEFCLK_ID = 8, // DCEFCLK 1699 SMU9_SYSPLL0_DPREFCLK_ID = 10, // DPREFCLK 1700 SMU9_SYSPLL0_DISPCLK_ID = 11, // DISPCLK 1701 }; 1702 1703 struct atom_get_smu_clock_info_output_parameters_v3_1 1704 { 1705 union { 1706 uint32_t smu_clock_freq_hz; 1707 uint32_t syspllvcofreq_10khz; 1708 uint32_t sysspllrefclk_10khz; 1709 }atom_smu_outputclkfreq; 1710 }; 1711 1712 1713 1714 /* 1715 *************************************************************************** 1716 Structures used by dynamicmemorysettings 1717 *************************************************************************** 1718 */ 1719 1720 enum atom_dynamic_memory_setting_command 1721 { 1722 COMPUTE_MEMORY_PLL_PARAM = 1, 1723 COMPUTE_ENGINE_PLL_PARAM = 2, 1724 ADJUST_MC_SETTING_PARAM = 3, 1725 }; 1726 1727 /* when command = COMPUTE_MEMORY_PLL_PARAM or ADJUST_MC_SETTING_PARAM */ 1728 struct dynamic_mclk_settings_parameters_v2_1 1729 { 1730 uint32_t mclk_10khz:24; //Input= target mclk 1731 uint32_t command:8; //command enum of atom_dynamic_memory_setting_command 1732 uint32_t reserved; 1733 }; 1734 1735 /* when command = COMPUTE_ENGINE_PLL_PARAM */ 1736 struct dynamic_sclk_settings_parameters_v2_1 1737 { 1738 uint32_t sclk_10khz:24; //Input= target mclk 1739 uint32_t command:8; //command enum of atom_dynamic_memory_setting_command 1740 uint32_t mclk_10khz; 1741 uint32_t reserved; 1742 }; 1743 1744 union dynamic_memory_settings_parameters_v2_1 1745 { 1746 struct dynamic_mclk_settings_parameters_v2_1 mclk_setting; 1747 struct dynamic_sclk_settings_parameters_v2_1 sclk_setting; 1748 }; 1749 1750 1751 1752 /* 1753 *************************************************************************** 1754 Structures used by memorytraining 1755 *************************************************************************** 1756 */ 1757 1758 enum atom_umc6_0_ucode_function_call_enum_id 1759 { 1760 UMC60_UCODE_FUNC_ID_REINIT = 0, 1761 UMC60_UCODE_FUNC_ID_ENTER_SELFREFRESH = 1, 1762 UMC60_UCODE_FUNC_ID_EXIT_SELFREFRESH = 2, 1763 }; 1764 1765 1766 struct memory_training_parameters_v2_1 1767 { 1768 uint8_t ucode_func_id; 1769 uint8_t ucode_reserved[3]; 1770 uint32_t reserved[5]; 1771 }; 1772 1773 1774 /* 1775 *************************************************************************** 1776 Structures used by setpixelclock 1777 *************************************************************************** 1778 */ 1779 1780 struct set_pixel_clock_parameter_v1_7 1781 { 1782 uint32_t pixclk_100hz; // target the pixel clock to drive the CRTC timing in unit of 100Hz. 1783 1784 uint8_t pll_id; // ATOM_PHY_PLL0/ATOM_PHY_PLL1/ATOM_PPLL0 1785 uint8_t encoderobjid; // ASIC encoder id defined in objectId.h, 1786 // indicate which graphic encoder will be used. 1787 uint8_t encoder_mode; // Encoder mode: 1788 uint8_t miscinfo; // enum atom_set_pixel_clock_v1_7_misc_info 1789 uint8_t crtc_id; // enum of atom_crtc_def 1790 uint8_t deep_color_ratio; // HDMI panel bit depth: enum atom_set_pixel_clock_v1_7_deepcolor_ratio 1791 uint8_t reserved1[2]; 1792 uint32_t reserved2; 1793 }; 1794 1795 //ucMiscInfo 1796 enum atom_set_pixel_clock_v1_7_misc_info 1797 { 1798 PIXEL_CLOCK_V7_MISC_FORCE_PROG_PPLL = 0x01, 1799 PIXEL_CLOCK_V7_MISC_PROG_PHYPLL = 0x02, 1800 PIXEL_CLOCK_V7_MISC_YUV420_MODE = 0x04, 1801 PIXEL_CLOCK_V7_MISC_DVI_DUALLINK_EN = 0x08, 1802 PIXEL_CLOCK_V7_MISC_REF_DIV_SRC = 0x30, 1803 PIXEL_CLOCK_V7_MISC_REF_DIV_SRC_XTALIN = 0x00, 1804 PIXEL_CLOCK_V7_MISC_REF_DIV_SRC_PCIE = 0x10, 1805 PIXEL_CLOCK_V7_MISC_REF_DIV_SRC_GENLK = 0x20, 1806 PIXEL_CLOCK_V7_MISC_REF_DIV_SRC_REFPAD = 0x30, 1807 PIXEL_CLOCK_V7_MISC_ATOMIC_UPDATE = 0x40, 1808 PIXEL_CLOCK_V7_MISC_FORCE_SS_DIS = 0x80, 1809 }; 1810 1811 /* deep_color_ratio */ 1812 enum atom_set_pixel_clock_v1_7_deepcolor_ratio 1813 { 1814 PIXEL_CLOCK_V7_DEEPCOLOR_RATIO_DIS = 0x00, //00 - DCCG_DEEP_COLOR_DTO_DISABLE: Disable Deep Color DTO 1815 PIXEL_CLOCK_V7_DEEPCOLOR_RATIO_5_4 = 0x01, //01 - DCCG_DEEP_COLOR_DTO_5_4_RATIO: Set Deep Color DTO to 5:4 1816 PIXEL_CLOCK_V7_DEEPCOLOR_RATIO_3_2 = 0x02, //02 - DCCG_DEEP_COLOR_DTO_3_2_RATIO: Set Deep Color DTO to 3:2 1817 PIXEL_CLOCK_V7_DEEPCOLOR_RATIO_2_1 = 0x03, //03 - DCCG_DEEP_COLOR_DTO_2_1_RATIO: Set Deep Color DTO to 2:1 1818 }; 1819 1820 /* 1821 *************************************************************************** 1822 Structures used by setdceclock 1823 *************************************************************************** 1824 */ 1825 1826 // SetDCEClock input parameter for DCE11.2( ELM and BF ) and above 1827 struct set_dce_clock_parameters_v2_1 1828 { 1829 uint32_t dceclk_10khz; // target DCE frequency in unit of 10KHZ, return real DISPCLK/DPREFCLK frequency. 1830 uint8_t dceclktype; // =0: DISPCLK =1: DPREFCLK =2: PIXCLK 1831 uint8_t dceclksrc; // ATOM_PLL0 or ATOM_GCK_DFS or ATOM_FCH_CLK or ATOM_COMBOPHY_PLLx 1832 uint8_t dceclkflag; // Bit [1:0] = PPLL ref clock source ( when ucDCEClkSrc= ATOM_PPLL0 ) 1833 uint8_t crtc_id; // ucDisp Pipe Id, ATOM_CRTC0/1/2/..., use only when ucDCEClkType = PIXCLK 1834 }; 1835 1836 //ucDCEClkType 1837 enum atom_set_dce_clock_clock_type 1838 { 1839 DCE_CLOCK_TYPE_DISPCLK = 0, 1840 DCE_CLOCK_TYPE_DPREFCLK = 1, 1841 DCE_CLOCK_TYPE_PIXELCLK = 2, // used by VBIOS internally, called by SetPixelClock 1842 }; 1843 1844 //ucDCEClkFlag when ucDCEClkType == DPREFCLK 1845 enum atom_set_dce_clock_dprefclk_flag 1846 { 1847 DCE_CLOCK_FLAG_PLL_REFCLK_SRC_MASK = 0x03, 1848 DCE_CLOCK_FLAG_PLL_REFCLK_SRC_GENERICA = 0x00, 1849 DCE_CLOCK_FLAG_PLL_REFCLK_SRC_GENLK = 0x01, 1850 DCE_CLOCK_FLAG_PLL_REFCLK_SRC_PCIE = 0x02, 1851 DCE_CLOCK_FLAG_PLL_REFCLK_SRC_XTALIN = 0x03, 1852 }; 1853 1854 //ucDCEClkFlag when ucDCEClkType == PIXCLK 1855 enum atom_set_dce_clock_pixclk_flag 1856 { 1857 DCE_CLOCK_FLAG_PCLK_DEEPCOLOR_RATIO_MASK = 0x03, 1858 DCE_CLOCK_FLAG_PCLK_DEEPCOLOR_RATIO_DIS = 0x00, //00 - DCCG_DEEP_COLOR_DTO_DISABLE: Disable Deep Color DTO 1859 DCE_CLOCK_FLAG_PCLK_DEEPCOLOR_RATIO_5_4 = 0x01, //01 - DCCG_DEEP_COLOR_DTO_5_4_RATIO: Set Deep Color DTO to 5:4 1860 DCE_CLOCK_FLAG_PCLK_DEEPCOLOR_RATIO_3_2 = 0x02, //02 - DCCG_DEEP_COLOR_DTO_3_2_RATIO: Set Deep Color DTO to 3:2 1861 DCE_CLOCK_FLAG_PCLK_DEEPCOLOR_RATIO_2_1 = 0x03, //03 - DCCG_DEEP_COLOR_DTO_2_1_RATIO: Set Deep Color DTO to 2:1 1862 DCE_CLOCK_FLAG_PIXCLK_YUV420_MODE = 0x04, 1863 }; 1864 1865 struct set_dce_clock_ps_allocation_v2_1 1866 { 1867 struct set_dce_clock_parameters_v2_1 param; 1868 uint32_t ulReserved[2]; 1869 }; 1870 1871 1872 /****************************************************************************/ 1873 // Structures used by BlankCRTC 1874 /****************************************************************************/ 1875 struct blank_crtc_parameters 1876 { 1877 uint8_t crtc_id; // enum atom_crtc_def 1878 uint8_t blanking; // enum atom_blank_crtc_command 1879 uint16_t reserved; 1880 uint32_t reserved1; 1881 }; 1882 1883 enum atom_blank_crtc_command 1884 { 1885 ATOM_BLANKING = 1, 1886 ATOM_BLANKING_OFF = 0, 1887 }; 1888 1889 /****************************************************************************/ 1890 // Structures used by enablecrtc 1891 /****************************************************************************/ 1892 struct enable_crtc_parameters 1893 { 1894 uint8_t crtc_id; // enum atom_crtc_def 1895 uint8_t enable; // ATOM_ENABLE or ATOM_DISABLE 1896 uint8_t padding[2]; 1897 }; 1898 1899 1900 /****************************************************************************/ 1901 // Structure used by EnableDispPowerGating 1902 /****************************************************************************/ 1903 struct enable_disp_power_gating_parameters_v2_1 1904 { 1905 uint8_t disp_pipe_id; // ATOM_CRTC1, ATOM_CRTC2, ... 1906 uint8_t enable; // ATOM_ENABLE or ATOM_DISABLE 1907 uint8_t padding[2]; 1908 }; 1909 1910 struct enable_disp_power_gating_ps_allocation 1911 { 1912 struct enable_disp_power_gating_parameters_v2_1 param; 1913 uint32_t ulReserved[4]; 1914 }; 1915 1916 /****************************************************************************/ 1917 // Structure used in setcrtc_usingdtdtiming 1918 /****************************************************************************/ 1919 struct set_crtc_using_dtd_timing_parameters 1920 { 1921 uint16_t h_size; 1922 uint16_t h_blanking_time; 1923 uint16_t v_size; 1924 uint16_t v_blanking_time; 1925 uint16_t h_syncoffset; 1926 uint16_t h_syncwidth; 1927 uint16_t v_syncoffset; 1928 uint16_t v_syncwidth; 1929 uint16_t modemiscinfo; 1930 uint8_t h_border; 1931 uint8_t v_border; 1932 uint8_t crtc_id; // enum atom_crtc_def 1933 uint8_t encoder_mode; // atom_encode_mode_def 1934 uint8_t padding[2]; 1935 }; 1936 1937 1938 /****************************************************************************/ 1939 // Structures used by processi2cchanneltransaction 1940 /****************************************************************************/ 1941 struct process_i2c_channel_transaction_parameters 1942 { 1943 uint8_t i2cspeed_khz; 1944 union { 1945 uint8_t regindex; 1946 uint8_t status; /* enum atom_process_i2c_flag */ 1947 } regind_status; 1948 uint16_t i2c_data_out; 1949 uint8_t flag; /* enum atom_process_i2c_status */ 1950 uint8_t trans_bytes; 1951 uint8_t slave_addr; 1952 uint8_t i2c_id; 1953 }; 1954 1955 //ucFlag 1956 enum atom_process_i2c_flag 1957 { 1958 HW_I2C_WRITE = 1, 1959 HW_I2C_READ = 0, 1960 I2C_2BYTE_ADDR = 0x02, 1961 HW_I2C_SMBUS_BYTE_WR = 0x04, 1962 }; 1963 1964 //status 1965 enum atom_process_i2c_status 1966 { 1967 HW_ASSISTED_I2C_STATUS_FAILURE =2, 1968 HW_ASSISTED_I2C_STATUS_SUCCESS =1, 1969 }; 1970 1971 1972 /****************************************************************************/ 1973 // Structures used by processauxchanneltransaction 1974 /****************************************************************************/ 1975 1976 struct process_aux_channel_transaction_parameters_v1_2 1977 { 1978 uint16_t aux_request; 1979 uint16_t dataout; 1980 uint8_t channelid; 1981 union { 1982 uint8_t reply_status; 1983 uint8_t aux_delay; 1984 } aux_status_delay; 1985 uint8_t dataout_len; 1986 uint8_t hpd_id; //=0: HPD1, =1: HPD2, =2: HPD3, =3: HPD4, =4: HPD5, =5: HPD6 1987 }; 1988 1989 1990 /****************************************************************************/ 1991 // Structures used by selectcrtc_source 1992 /****************************************************************************/ 1993 1994 struct select_crtc_source_parameters_v2_3 1995 { 1996 uint8_t crtc_id; // enum atom_crtc_def 1997 uint8_t encoder_id; // enum atom_dig_def 1998 uint8_t encode_mode; // enum atom_encode_mode_def 1999 uint8_t dst_bpc; // enum atom_panel_bit_per_color 2000 }; 2001 2002 2003 /****************************************************************************/ 2004 // Structures used by digxencodercontrol 2005 /****************************************************************************/ 2006 2007 // ucAction: 2008 enum atom_dig_encoder_control_action 2009 { 2010 ATOM_ENCODER_CMD_DISABLE_DIG = 0, 2011 ATOM_ENCODER_CMD_ENABLE_DIG = 1, 2012 ATOM_ENCODER_CMD_DP_LINK_TRAINING_START = 0x08, 2013 ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN1 = 0x09, 2014 ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN2 = 0x0a, 2015 ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN3 = 0x13, 2016 ATOM_ENCODER_CMD_DP_LINK_TRAINING_COMPLETE = 0x0b, 2017 ATOM_ENCODER_CMD_DP_VIDEO_OFF = 0x0c, 2018 ATOM_ENCODER_CMD_DP_VIDEO_ON = 0x0d, 2019 ATOM_ENCODER_CMD_SETUP_PANEL_MODE = 0x10, 2020 ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN4 = 0x14, 2021 ATOM_ENCODER_CMD_STREAM_SETUP = 0x0F, 2022 ATOM_ENCODER_CMD_LINK_SETUP = 0x11, 2023 ATOM_ENCODER_CMD_ENCODER_BLANK = 0x12, 2024 }; 2025 2026 //define ucPanelMode 2027 enum atom_dig_encoder_control_panelmode 2028 { 2029 DP_PANEL_MODE_DISABLE = 0x00, 2030 DP_PANEL_MODE_ENABLE_eDP_MODE = 0x01, 2031 DP_PANEL_MODE_ENABLE_LVLINK_MODE = 0x11, 2032 }; 2033 2034 //ucDigId 2035 enum atom_dig_encoder_control_v5_digid 2036 { 2037 ATOM_ENCODER_CONFIG_V5_DIG0_ENCODER = 0x00, 2038 ATOM_ENCODER_CONFIG_V5_DIG1_ENCODER = 0x01, 2039 ATOM_ENCODER_CONFIG_V5_DIG2_ENCODER = 0x02, 2040 ATOM_ENCODER_CONFIG_V5_DIG3_ENCODER = 0x03, 2041 ATOM_ENCODER_CONFIG_V5_DIG4_ENCODER = 0x04, 2042 ATOM_ENCODER_CONFIG_V5_DIG5_ENCODER = 0x05, 2043 ATOM_ENCODER_CONFIG_V5_DIG6_ENCODER = 0x06, 2044 ATOM_ENCODER_CONFIG_V5_DIG7_ENCODER = 0x07, 2045 }; 2046 2047 struct dig_encoder_stream_setup_parameters_v1_5 2048 { 2049 uint8_t digid; // 0~6 map to DIG0~DIG6 enum atom_dig_encoder_control_v5_digid 2050 uint8_t action; // = ATOM_ENOCODER_CMD_STREAM_SETUP 2051 uint8_t digmode; // ATOM_ENCODER_MODE_DP/ATOM_ENCODER_MODE_DVI/ATOM_ENCODER_MODE_HDMI 2052 uint8_t lanenum; // Lane number 2053 uint32_t pclk_10khz; // Pixel Clock in 10Khz 2054 uint8_t bitpercolor; 2055 uint8_t dplinkrate_270mhz;//= DP link rate/270Mhz, =6: 1.62G = 10: 2.7G, =20: 5.4Ghz, =30: 8.1Ghz etc 2056 uint8_t reserved[2]; 2057 }; 2058 2059 struct dig_encoder_link_setup_parameters_v1_5 2060 { 2061 uint8_t digid; // 0~6 map to DIG0~DIG6 enum atom_dig_encoder_control_v5_digid 2062 uint8_t action; // = ATOM_ENOCODER_CMD_LINK_SETUP 2063 uint8_t digmode; // ATOM_ENCODER_MODE_DP/ATOM_ENCODER_MODE_DVI/ATOM_ENCODER_MODE_HDMI 2064 uint8_t lanenum; // Lane number 2065 uint8_t symclk_10khz; // Symbol Clock in 10Khz 2066 uint8_t hpd_sel; 2067 uint8_t digfe_sel; // DIG stream( front-end ) selection, bit0 means DIG0 FE is enable, 2068 uint8_t reserved[2]; 2069 }; 2070 2071 struct dp_panel_mode_set_parameters_v1_5 2072 { 2073 uint8_t digid; // 0~6 map to DIG0~DIG6 enum atom_dig_encoder_control_v5_digid 2074 uint8_t action; // = ATOM_ENCODER_CMD_DPLINK_SETUP 2075 uint8_t panelmode; // enum atom_dig_encoder_control_panelmode 2076 uint8_t reserved1; 2077 uint32_t reserved2[2]; 2078 }; 2079 2080 struct dig_encoder_generic_cmd_parameters_v1_5 2081 { 2082 uint8_t digid; // 0~6 map to DIG0~DIG6 enum atom_dig_encoder_control_v5_digid 2083 uint8_t action; // = rest of generic encoder command which does not carry any parameters 2084 uint8_t reserved1[2]; 2085 uint32_t reserved2[2]; 2086 }; 2087 2088 union dig_encoder_control_parameters_v1_5 2089 { 2090 struct dig_encoder_generic_cmd_parameters_v1_5 cmd_param; 2091 struct dig_encoder_stream_setup_parameters_v1_5 stream_param; 2092 struct dig_encoder_link_setup_parameters_v1_5 link_param; 2093 struct dp_panel_mode_set_parameters_v1_5 dppanel_param; 2094 }; 2095 2096 /* 2097 *************************************************************************** 2098 Structures used by dig1transmittercontrol 2099 *************************************************************************** 2100 */ 2101 struct dig_transmitter_control_parameters_v1_6 2102 { 2103 uint8_t phyid; // 0=UNIPHYA, 1=UNIPHYB, 2=UNIPHYC, 3=UNIPHYD, 4= UNIPHYE 5=UNIPHYF 2104 uint8_t action; // define as ATOM_TRANSMITER_ACTION_xxx 2105 union { 2106 uint8_t digmode; // enum atom_encode_mode_def 2107 uint8_t dplaneset; // DP voltage swing and pre-emphasis value defined in DPCD DP_LANE_SET, "DP_LANE_SET__xDB_y_zV" 2108 } mode_laneset; 2109 uint8_t lanenum; // Lane number 1, 2, 4, 8 2110 uint32_t symclk_10khz; // Symbol Clock in 10Khz 2111 uint8_t hpdsel; // =1: HPD1, =2: HPD2, .... =6: HPD6, =0: HPD is not assigned 2112 uint8_t digfe_sel; // DIG stream( front-end ) selection, bit0 means DIG0 FE is enable, 2113 uint8_t connobj_id; // Connector Object Id defined in ObjectId.h 2114 uint8_t reserved; 2115 uint32_t reserved1; 2116 }; 2117 2118 struct dig_transmitter_control_ps_allocation_v1_6 2119 { 2120 struct dig_transmitter_control_parameters_v1_6 param; 2121 uint32_t reserved[4]; 2122 }; 2123 2124 //ucAction 2125 enum atom_dig_transmitter_control_action 2126 { 2127 ATOM_TRANSMITTER_ACTION_DISABLE = 0, 2128 ATOM_TRANSMITTER_ACTION_ENABLE = 1, 2129 ATOM_TRANSMITTER_ACTION_LCD_BLOFF = 2, 2130 ATOM_TRANSMITTER_ACTION_LCD_BLON = 3, 2131 ATOM_TRANSMITTER_ACTION_BL_BRIGHTNESS_CONTROL = 4, 2132 ATOM_TRANSMITTER_ACTION_LCD_SELFTEST_START = 5, 2133 ATOM_TRANSMITTER_ACTION_LCD_SELFTEST_STOP = 6, 2134 ATOM_TRANSMITTER_ACTION_INIT = 7, 2135 ATOM_TRANSMITTER_ACTION_DISABLE_OUTPUT = 8, 2136 ATOM_TRANSMITTER_ACTION_ENABLE_OUTPUT = 9, 2137 ATOM_TRANSMITTER_ACTION_SETUP = 10, 2138 ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH = 11, 2139 ATOM_TRANSMITTER_ACTION_POWER_ON = 12, 2140 ATOM_TRANSMITTER_ACTION_POWER_OFF = 13, 2141 }; 2142 2143 // digfe_sel 2144 enum atom_dig_transmitter_control_digfe_sel 2145 { 2146 ATOM_TRANMSITTER_V6__DIGA_SEL = 0x01, 2147 ATOM_TRANMSITTER_V6__DIGB_SEL = 0x02, 2148 ATOM_TRANMSITTER_V6__DIGC_SEL = 0x04, 2149 ATOM_TRANMSITTER_V6__DIGD_SEL = 0x08, 2150 ATOM_TRANMSITTER_V6__DIGE_SEL = 0x10, 2151 ATOM_TRANMSITTER_V6__DIGF_SEL = 0x20, 2152 ATOM_TRANMSITTER_V6__DIGG_SEL = 0x40, 2153 }; 2154 2155 2156 //ucHPDSel 2157 enum atom_dig_transmitter_control_hpd_sel 2158 { 2159 ATOM_TRANSMITTER_V6_NO_HPD_SEL = 0x00, 2160 ATOM_TRANSMITTER_V6_HPD1_SEL = 0x01, 2161 ATOM_TRANSMITTER_V6_HPD2_SEL = 0x02, 2162 ATOM_TRANSMITTER_V6_HPD3_SEL = 0x03, 2163 ATOM_TRANSMITTER_V6_HPD4_SEL = 0x04, 2164 ATOM_TRANSMITTER_V6_HPD5_SEL = 0x05, 2165 ATOM_TRANSMITTER_V6_HPD6_SEL = 0x06, 2166 }; 2167 2168 // ucDPLaneSet 2169 enum atom_dig_transmitter_control_dplaneset 2170 { 2171 DP_LANE_SET__0DB_0_4V = 0x00, 2172 DP_LANE_SET__0DB_0_6V = 0x01, 2173 DP_LANE_SET__0DB_0_8V = 0x02, 2174 DP_LANE_SET__0DB_1_2V = 0x03, 2175 DP_LANE_SET__3_5DB_0_4V = 0x08, 2176 DP_LANE_SET__3_5DB_0_6V = 0x09, 2177 DP_LANE_SET__3_5DB_0_8V = 0x0a, 2178 DP_LANE_SET__6DB_0_4V = 0x10, 2179 DP_LANE_SET__6DB_0_6V = 0x11, 2180 DP_LANE_SET__9_5DB_0_4V = 0x18, 2181 }; 2182 2183 2184 2185 /****************************************************************************/ 2186 // Structures used by ExternalEncoderControl V2.4 2187 /****************************************************************************/ 2188 2189 struct external_encoder_control_parameters_v2_4 2190 { 2191 uint16_t pixelclock_10khz; // pixel clock in 10Khz, valid when ucAction=SETUP/ENABLE_OUTPUT 2192 uint8_t config; // indicate which encoder, and DP link rate when ucAction = SETUP/ENABLE_OUTPUT 2193 uint8_t action; // 2194 uint8_t encodermode; // encoder mode, only used when ucAction = SETUP/ENABLE_OUTPUT 2195 uint8_t lanenum; // lane number, only used when ucAction = SETUP/ENABLE_OUTPUT 2196 uint8_t bitpercolor; // output bit per color, only valid when ucAction = SETUP/ENABLE_OUTPUT and ucEncodeMode= DP 2197 uint8_t hpd_id; 2198 }; 2199 2200 2201 // ucAction 2202 enum external_encoder_control_action_def 2203 { 2204 EXTERNAL_ENCODER_ACTION_V3_DISABLE_OUTPUT = 0x00, 2205 EXTERNAL_ENCODER_ACTION_V3_ENABLE_OUTPUT = 0x01, 2206 EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT = 0x07, 2207 EXTERNAL_ENCODER_ACTION_V3_ENCODER_SETUP = 0x0f, 2208 EXTERNAL_ENCODER_ACTION_V3_ENCODER_BLANKING_OFF = 0x10, 2209 EXTERNAL_ENCODER_ACTION_V3_ENCODER_BLANKING = 0x11, 2210 EXTERNAL_ENCODER_ACTION_V3_DACLOAD_DETECTION = 0x12, 2211 EXTERNAL_ENCODER_ACTION_V3_DDC_SETUP = 0x14, 2212 }; 2213 2214 // ucConfig 2215 enum external_encoder_control_v2_4_config_def 2216 { 2217 EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_MASK = 0x03, 2218 EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_1_62GHZ = 0x00, 2219 EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ = 0x01, 2220 EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_5_40GHZ = 0x02, 2221 EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_3_24GHZ = 0x03, 2222 EXTERNAL_ENCODER_CONFIG_V3_ENCODER_SEL_MAKS = 0x70, 2223 EXTERNAL_ENCODER_CONFIG_V3_ENCODER1 = 0x00, 2224 EXTERNAL_ENCODER_CONFIG_V3_ENCODER2 = 0x10, 2225 EXTERNAL_ENCODER_CONFIG_V3_ENCODER3 = 0x20, 2226 }; 2227 2228 struct external_encoder_control_ps_allocation_v2_4 2229 { 2230 struct external_encoder_control_parameters_v2_4 sExtEncoder; 2231 uint32_t reserved[2]; 2232 }; 2233 2234 2235 /* 2236 *************************************************************************** 2237 AMD ACPI Table 2238 2239 *************************************************************************** 2240 */ 2241 2242 struct amd_acpi_description_header{ 2243 uint32_t signature; 2244 uint32_t tableLength; //Length 2245 uint8_t revision; 2246 uint8_t checksum; 2247 uint8_t oemId[6]; 2248 uint8_t oemTableId[8]; //UINT64 OemTableId; 2249 uint32_t oemRevision; 2250 uint32_t creatorId; 2251 uint32_t creatorRevision; 2252 }; 2253 2254 struct uefi_acpi_vfct{ 2255 struct amd_acpi_description_header sheader; 2256 uint8_t tableUUID[16]; //0x24 2257 uint32_t vbiosimageoffset; //0x34. Offset to the first GOP_VBIOS_CONTENT block from the beginning of the stucture. 2258 uint32_t lib1Imageoffset; //0x38. Offset to the first GOP_LIB1_CONTENT block from the beginning of the stucture. 2259 uint32_t reserved[4]; //0x3C 2260 }; 2261 2262 struct vfct_image_header{ 2263 uint32_t pcibus; //0x4C 2264 uint32_t pcidevice; //0x50 2265 uint32_t pcifunction; //0x54 2266 uint16_t vendorid; //0x58 2267 uint16_t deviceid; //0x5A 2268 uint16_t ssvid; //0x5C 2269 uint16_t ssid; //0x5E 2270 uint32_t revision; //0x60 2271 uint32_t imagelength; //0x64 2272 }; 2273 2274 2275 struct gop_vbios_content { 2276 struct vfct_image_header vbiosheader; 2277 uint8_t vbioscontent[1]; 2278 }; 2279 2280 struct gop_lib1_content { 2281 struct vfct_image_header lib1header; 2282 uint8_t lib1content[1]; 2283 }; 2284 2285 2286 2287 /* 2288 *************************************************************************** 2289 Scratch Register definitions 2290 Each number below indicates which scratch regiser request, Active and 2291 Connect all share the same definitions as display_device_tag defines 2292 *************************************************************************** 2293 */ 2294 2295 enum scratch_register_def{ 2296 ATOM_DEVICE_CONNECT_INFO_DEF = 0, 2297 ATOM_BL_BRI_LEVEL_INFO_DEF = 2, 2298 ATOM_ACTIVE_INFO_DEF = 3, 2299 ATOM_LCD_INFO_DEF = 4, 2300 ATOM_DEVICE_REQ_INFO_DEF = 5, 2301 ATOM_ACC_CHANGE_INFO_DEF = 6, 2302 ATOM_PRE_OS_MODE_INFO_DEF = 7, 2303 ATOM_PRE_OS_ASSERTION_DEF = 8, //For GOP to record a 32bit assertion code, this is enabled by default in prodution GOP drivers. 2304 ATOM_INTERNAL_TIMER_INFO_DEF = 10, 2305 }; 2306 2307 enum scratch_device_connect_info_bit_def{ 2308 ATOM_DISPLAY_LCD1_CONNECT =0x0002, 2309 ATOM_DISPLAY_DFP1_CONNECT =0x0008, 2310 ATOM_DISPLAY_DFP2_CONNECT =0x0080, 2311 ATOM_DISPLAY_DFP3_CONNECT =0x0200, 2312 ATOM_DISPLAY_DFP4_CONNECT =0x0400, 2313 ATOM_DISPLAY_DFP5_CONNECT =0x0800, 2314 ATOM_DISPLAY_DFP6_CONNECT =0x0040, 2315 ATOM_DISPLAY_DFPx_CONNECT =0x0ec8, 2316 ATOM_CONNECT_INFO_DEVICE_MASK =0x0fff, 2317 }; 2318 2319 enum scratch_bl_bri_level_info_bit_def{ 2320 ATOM_CURRENT_BL_LEVEL_SHIFT =0x8, 2321 #ifndef _H2INC 2322 ATOM_CURRENT_BL_LEVEL_MASK =0x0000ff00, 2323 ATOM_DEVICE_DPMS_STATE =0x00010000, 2324 #endif 2325 }; 2326 2327 enum scratch_active_info_bits_def{ 2328 ATOM_DISPLAY_LCD1_ACTIVE =0x0002, 2329 ATOM_DISPLAY_DFP1_ACTIVE =0x0008, 2330 ATOM_DISPLAY_DFP2_ACTIVE =0x0080, 2331 ATOM_DISPLAY_DFP3_ACTIVE =0x0200, 2332 ATOM_DISPLAY_DFP4_ACTIVE =0x0400, 2333 ATOM_DISPLAY_DFP5_ACTIVE =0x0800, 2334 ATOM_DISPLAY_DFP6_ACTIVE =0x0040, 2335 ATOM_ACTIVE_INFO_DEVICE_MASK =0x0fff, 2336 }; 2337 2338 enum scratch_device_req_info_bits_def{ 2339 ATOM_DISPLAY_LCD1_REQ =0x0002, 2340 ATOM_DISPLAY_DFP1_REQ =0x0008, 2341 ATOM_DISPLAY_DFP2_REQ =0x0080, 2342 ATOM_DISPLAY_DFP3_REQ =0x0200, 2343 ATOM_DISPLAY_DFP4_REQ =0x0400, 2344 ATOM_DISPLAY_DFP5_REQ =0x0800, 2345 ATOM_DISPLAY_DFP6_REQ =0x0040, 2346 ATOM_REQ_INFO_DEVICE_MASK =0x0fff, 2347 }; 2348 2349 enum scratch_acc_change_info_bitshift_def{ 2350 ATOM_ACC_CHANGE_ACC_MODE_SHIFT =4, 2351 ATOM_ACC_CHANGE_LID_STATUS_SHIFT =6, 2352 }; 2353 2354 enum scratch_acc_change_info_bits_def{ 2355 ATOM_ACC_CHANGE_ACC_MODE =0x00000010, 2356 ATOM_ACC_CHANGE_LID_STATUS =0x00000040, 2357 }; 2358 2359 enum scratch_pre_os_mode_info_bits_def{ 2360 ATOM_PRE_OS_MODE_MASK =0x00000003, 2361 ATOM_PRE_OS_MODE_VGA =0x00000000, 2362 ATOM_PRE_OS_MODE_VESA =0x00000001, 2363 ATOM_PRE_OS_MODE_GOP =0x00000002, 2364 ATOM_PRE_OS_MODE_PIXEL_DEPTH =0x0000000C, 2365 ATOM_PRE_OS_MODE_PIXEL_FORMAT_MASK=0x000000F0, 2366 ATOM_PRE_OS_MODE_8BIT_PAL_EN =0x00000100, 2367 ATOM_ASIC_INIT_COMPLETE =0x00000200, 2368 #ifndef _H2INC 2369 ATOM_PRE_OS_MODE_NUMBER_MASK =0xFFFF0000, 2370 #endif 2371 }; 2372 2373 2374 2375 /* 2376 *************************************************************************** 2377 ATOM firmware ID header file 2378 !! Please keep it at end of the atomfirmware.h !! 2379 *************************************************************************** 2380 */ 2381 #include "atomfirmwareid.h" 2382 #pragma pack() 2383 2384 #endif 2385 2386