1 /****************************************************************************\
2 *
3 *  File Name      atomfirmware.h
4 *  Project        This is an interface header file between atombios and OS GPU drivers for SoC15 products
5 *
6 *  Description    header file of general definitions for OS and pre-OS video drivers
7 *
8 *  Copyright 2014 Advanced Micro Devices, Inc.
9 *
10 * Permission is hereby granted, free of charge, to any person obtaining a copy of this software
11 * and associated documentation files (the "Software"), to deal in the Software without restriction,
12 * including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense,
13 * and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so,
14 * subject to the following conditions:
15 *
16 * The above copyright notice and this permission notice shall be included in all copies or substantial
17 * portions of the Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
22 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
23 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
24 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
25 * OTHER DEALINGS IN THE SOFTWARE.
26 *
27 \****************************************************************************/
28 
29 /*IMPORTANT NOTES
30 * If a change in VBIOS/Driver/Tool's interface is only needed for SoC15 and forward products, then the change is only needed in this atomfirmware.h header file.
31 * If a change in VBIOS/Driver/Tool's interface is only needed for pre-SoC15 products, then the change is only needed in atombios.h header file.
32 * If a change is needed for both pre and post SoC15 products, then the change has to be made separately and might be differently in both atomfirmware.h and atombios.h.
33 */
34 
35 #ifndef _ATOMFIRMWARE_H_
36 #define _ATOMFIRMWARE_H_
37 
38 enum  atom_bios_header_version_def{
39   ATOM_MAJOR_VERSION        =0x0003,
40   ATOM_MINOR_VERSION        =0x0003,
41 };
42 
43 #ifdef _H2INC
44   #ifndef uint32_t
45     typedef unsigned long uint32_t;
46   #endif
47 
48   #ifndef uint16_t
49     typedef unsigned short uint16_t;
50   #endif
51 
52   #ifndef uint8_t
53     typedef unsigned char uint8_t;
54   #endif
55 #endif
56 
57 enum atom_crtc_def{
58   ATOM_CRTC1      =0,
59   ATOM_CRTC2      =1,
60   ATOM_CRTC3      =2,
61   ATOM_CRTC4      =3,
62   ATOM_CRTC5      =4,
63   ATOM_CRTC6      =5,
64   ATOM_CRTC_INVALID  =0xff,
65 };
66 
67 enum atom_ppll_def{
68   ATOM_PPLL0          =2,
69   ATOM_GCK_DFS        =8,
70   ATOM_FCH_CLK        =9,
71   ATOM_DP_DTO         =11,
72   ATOM_COMBOPHY_PLL0  =20,
73   ATOM_COMBOPHY_PLL1  =21,
74   ATOM_COMBOPHY_PLL2  =22,
75   ATOM_COMBOPHY_PLL3  =23,
76   ATOM_COMBOPHY_PLL4  =24,
77   ATOM_COMBOPHY_PLL5  =25,
78   ATOM_PPLL_INVALID   =0xff,
79 };
80 
81 // define ASIC internal encoder id ( bit vector ), used for CRTC_SourceSel
82 enum atom_dig_def{
83   ASIC_INT_DIG1_ENCODER_ID  =0x03,
84   ASIC_INT_DIG2_ENCODER_ID  =0x09,
85   ASIC_INT_DIG3_ENCODER_ID  =0x0a,
86   ASIC_INT_DIG4_ENCODER_ID  =0x0b,
87   ASIC_INT_DIG5_ENCODER_ID  =0x0c,
88   ASIC_INT_DIG6_ENCODER_ID  =0x0d,
89   ASIC_INT_DIG7_ENCODER_ID  =0x0e,
90 };
91 
92 //ucEncoderMode
93 enum atom_encode_mode_def
94 {
95   ATOM_ENCODER_MODE_DP          =0,
96   ATOM_ENCODER_MODE_DP_SST      =0,
97   ATOM_ENCODER_MODE_LVDS        =1,
98   ATOM_ENCODER_MODE_DVI         =2,
99   ATOM_ENCODER_MODE_HDMI        =3,
100   ATOM_ENCODER_MODE_DP_AUDIO    =5,
101   ATOM_ENCODER_MODE_DP_MST      =5,
102   ATOM_ENCODER_MODE_CRT         =15,
103   ATOM_ENCODER_MODE_DVO         =16,
104 };
105 
106 enum atom_encoder_refclk_src_def{
107   ENCODER_REFCLK_SRC_P1PLL      =0,
108   ENCODER_REFCLK_SRC_P2PLL      =1,
109   ENCODER_REFCLK_SRC_P3PLL      =2,
110   ENCODER_REFCLK_SRC_EXTCLK     =3,
111   ENCODER_REFCLK_SRC_INVALID    =0xff,
112 };
113 
114 enum atom_scaler_def{
115   ATOM_SCALER_DISABLE          =0,  /*scaler bypass mode, auto-center & no replication*/
116   ATOM_SCALER_CENTER           =1,  //For Fudo, it's bypass and auto-center & auto replication
117   ATOM_SCALER_EXPANSION        =2,  /*scaler expansion by 2 tap alpha blending mode*/
118 };
119 
120 enum atom_operation_def{
121   ATOM_DISABLE             = 0,
122   ATOM_ENABLE              = 1,
123   ATOM_INIT                = 7,
124   ATOM_GET_STATUS          = 8,
125 };
126 
127 enum atom_embedded_display_op_def{
128   ATOM_LCD_BL_OFF                = 2,
129   ATOM_LCD_BL_OM                 = 3,
130   ATOM_LCD_BL_BRIGHTNESS_CONTROL = 4,
131   ATOM_LCD_SELFTEST_START        = 5,
132   ATOM_LCD_SELFTEST_STOP         = 6,
133 };
134 
135 enum atom_spread_spectrum_mode{
136   ATOM_SS_CENTER_OR_DOWN_MODE_MASK  = 0x01,
137   ATOM_SS_DOWN_SPREAD_MODE          = 0x00,
138   ATOM_SS_CENTRE_SPREAD_MODE        = 0x01,
139   ATOM_INT_OR_EXT_SS_MASK           = 0x02,
140   ATOM_INTERNAL_SS_MASK             = 0x00,
141   ATOM_EXTERNAL_SS_MASK             = 0x02,
142 };
143 
144 /* define panel bit per color  */
145 enum atom_panel_bit_per_color{
146   PANEL_BPC_UNDEFINE     =0x00,
147   PANEL_6BIT_PER_COLOR   =0x01,
148   PANEL_8BIT_PER_COLOR   =0x02,
149   PANEL_10BIT_PER_COLOR  =0x03,
150   PANEL_12BIT_PER_COLOR  =0x04,
151   PANEL_16BIT_PER_COLOR  =0x05,
152 };
153 
154 //ucVoltageType
155 enum atom_voltage_type
156 {
157   VOLTAGE_TYPE_VDDC = 1,
158   VOLTAGE_TYPE_MVDDC = 2,
159   VOLTAGE_TYPE_MVDDQ = 3,
160   VOLTAGE_TYPE_VDDCI = 4,
161   VOLTAGE_TYPE_VDDGFX = 5,
162   VOLTAGE_TYPE_PCC = 6,
163   VOLTAGE_TYPE_MVPP = 7,
164   VOLTAGE_TYPE_LEDDPM = 8,
165   VOLTAGE_TYPE_PCC_MVDD = 9,
166   VOLTAGE_TYPE_PCIE_VDDC = 10,
167   VOLTAGE_TYPE_PCIE_VDDR = 11,
168   VOLTAGE_TYPE_GENERIC_I2C_1 = 0x11,
169   VOLTAGE_TYPE_GENERIC_I2C_2 = 0x12,
170   VOLTAGE_TYPE_GENERIC_I2C_3 = 0x13,
171   VOLTAGE_TYPE_GENERIC_I2C_4 = 0x14,
172   VOLTAGE_TYPE_GENERIC_I2C_5 = 0x15,
173   VOLTAGE_TYPE_GENERIC_I2C_6 = 0x16,
174   VOLTAGE_TYPE_GENERIC_I2C_7 = 0x17,
175   VOLTAGE_TYPE_GENERIC_I2C_8 = 0x18,
176   VOLTAGE_TYPE_GENERIC_I2C_9 = 0x19,
177   VOLTAGE_TYPE_GENERIC_I2C_10 = 0x1A,
178 };
179 
180 enum atom_dgpu_vram_type {
181   ATOM_DGPU_VRAM_TYPE_GDDR5 = 0x50,
182   ATOM_DGPU_VRAM_TYPE_HBM2  = 0x60,
183   ATOM_DGPU_VRAM_TYPE_HBM2E = 0x61,
184   ATOM_DGPU_VRAM_TYPE_GDDR6 = 0x70,
185 };
186 
187 enum atom_dp_vs_preemph_def{
188   DP_VS_LEVEL0_PREEMPH_LEVEL0 = 0x00,
189   DP_VS_LEVEL1_PREEMPH_LEVEL0 = 0x01,
190   DP_VS_LEVEL2_PREEMPH_LEVEL0 = 0x02,
191   DP_VS_LEVEL3_PREEMPH_LEVEL0 = 0x03,
192   DP_VS_LEVEL0_PREEMPH_LEVEL1 = 0x08,
193   DP_VS_LEVEL1_PREEMPH_LEVEL1 = 0x09,
194   DP_VS_LEVEL2_PREEMPH_LEVEL1 = 0x0a,
195   DP_VS_LEVEL0_PREEMPH_LEVEL2 = 0x10,
196   DP_VS_LEVEL1_PREEMPH_LEVEL2 = 0x11,
197   DP_VS_LEVEL0_PREEMPH_LEVEL3 = 0x18,
198 };
199 
200 #define BIOS_ATOM_PREFIX   "ATOMBIOS"
201 #define BIOS_VERSION_PREFIX  "ATOMBIOSBK-AMD"
202 #define BIOS_STRING_LENGTH 43
203 
204 /*
205 enum atom_string_def{
206 asic_bus_type_pcie_string = "PCI_EXPRESS",
207 atom_fire_gl_string       = "FGL",
208 atom_bios_string          = "ATOM"
209 };
210 */
211 
212 #pragma pack(1)                          /* BIOS data must use byte aligment*/
213 
214 enum atombios_image_offset{
215   OFFSET_TO_ATOM_ROM_HEADER_POINTER          = 0x00000048,
216   OFFSET_TO_ATOM_ROM_IMAGE_SIZE              = 0x00000002,
217   OFFSET_TO_ATOMBIOS_ASIC_BUS_MEM_TYPE       = 0x94,
218   MAXSIZE_OF_ATOMBIOS_ASIC_BUS_MEM_TYPE      = 20,  /*including the terminator 0x0!*/
219   OFFSET_TO_GET_ATOMBIOS_NUMBER_OF_STRINGS   = 0x2f,
220   OFFSET_TO_GET_ATOMBIOS_STRING_START        = 0x6e,
221   OFFSET_TO_VBIOS_PART_NUMBER                = 0x80,
222   OFFSET_TO_VBIOS_DATE                       = 0x50,
223 };
224 
225 /****************************************************************************
226 * Common header for all tables (Data table, Command function).
227 * Every table pointed in _ATOM_MASTER_DATA_TABLE has this common header.
228 * And the pointer actually points to this header.
229 ****************************************************************************/
230 
231 struct atom_common_table_header
232 {
233   uint16_t structuresize;
234   uint8_t  format_revision;   //mainly used for a hw function, when the parser is not backward compatible
235   uint8_t  content_revision;  //change it when a data table has a structure change, or a hw function has a input/output parameter change
236 };
237 
238 /****************************************************************************
239 * Structure stores the ROM header.
240 ****************************************************************************/
241 struct atom_rom_header_v2_2
242 {
243   struct atom_common_table_header table_header;
244   uint8_t  atom_bios_string[4];        //enum atom_string_def atom_bios_string;     //Signature to distinguish between Atombios and non-atombios,
245   uint16_t bios_segment_address;
246   uint16_t protectedmodeoffset;
247   uint16_t configfilenameoffset;
248   uint16_t crc_block_offset;
249   uint16_t vbios_bootupmessageoffset;
250   uint16_t int10_offset;
251   uint16_t pcibusdevinitcode;
252   uint16_t iobaseaddress;
253   uint16_t subsystem_vendor_id;
254   uint16_t subsystem_id;
255   uint16_t pci_info_offset;
256   uint16_t masterhwfunction_offset;      //Offest for SW to get all command function offsets, Don't change the position
257   uint16_t masterdatatable_offset;       //Offest for SW to get all data table offsets, Don't change the position
258   uint16_t reserved;
259   uint32_t pspdirtableoffset;
260 };
261 
262 /*==============================hw function portion======================================================================*/
263 
264 
265 /****************************************************************************
266 * Structures used in Command.mtb, each function name is not given here since those function could change from time to time
267 * The real functionality of each function is associated with the parameter structure version when defined
268 * For all internal cmd function definitions, please reference to atomstruct.h
269 ****************************************************************************/
270 struct atom_master_list_of_command_functions_v2_1{
271   uint16_t asic_init;                   //Function
272   uint16_t cmd_function1;               //used as an internal one
273   uint16_t cmd_function2;               //used as an internal one
274   uint16_t cmd_function3;               //used as an internal one
275   uint16_t digxencodercontrol;          //Function
276   uint16_t cmd_function5;               //used as an internal one
277   uint16_t cmd_function6;               //used as an internal one
278   uint16_t cmd_function7;               //used as an internal one
279   uint16_t cmd_function8;               //used as an internal one
280   uint16_t cmd_function9;               //used as an internal one
281   uint16_t setengineclock;              //Function
282   uint16_t setmemoryclock;              //Function
283   uint16_t setpixelclock;               //Function
284   uint16_t enabledisppowergating;       //Function
285   uint16_t cmd_function14;              //used as an internal one
286   uint16_t cmd_function15;              //used as an internal one
287   uint16_t cmd_function16;              //used as an internal one
288   uint16_t cmd_function17;              //used as an internal one
289   uint16_t cmd_function18;              //used as an internal one
290   uint16_t cmd_function19;              //used as an internal one
291   uint16_t cmd_function20;              //used as an internal one
292   uint16_t cmd_function21;              //used as an internal one
293   uint16_t cmd_function22;              //used as an internal one
294   uint16_t cmd_function23;              //used as an internal one
295   uint16_t cmd_function24;              //used as an internal one
296   uint16_t cmd_function25;              //used as an internal one
297   uint16_t cmd_function26;              //used as an internal one
298   uint16_t cmd_function27;              //used as an internal one
299   uint16_t cmd_function28;              //used as an internal one
300   uint16_t cmd_function29;              //used as an internal one
301   uint16_t cmd_function30;              //used as an internal one
302   uint16_t cmd_function31;              //used as an internal one
303   uint16_t cmd_function32;              //used as an internal one
304   uint16_t cmd_function33;              //used as an internal one
305   uint16_t blankcrtc;                   //Function
306   uint16_t enablecrtc;                  //Function
307   uint16_t cmd_function36;              //used as an internal one
308   uint16_t cmd_function37;              //used as an internal one
309   uint16_t cmd_function38;              //used as an internal one
310   uint16_t cmd_function39;              //used as an internal one
311   uint16_t cmd_function40;              //used as an internal one
312   uint16_t getsmuclockinfo;             //Function
313   uint16_t selectcrtc_source;           //Function
314   uint16_t cmd_function43;              //used as an internal one
315   uint16_t cmd_function44;              //used as an internal one
316   uint16_t cmd_function45;              //used as an internal one
317   uint16_t setdceclock;                 //Function
318   uint16_t getmemoryclock;              //Function
319   uint16_t getengineclock;              //Function
320   uint16_t setcrtc_usingdtdtiming;      //Function
321   uint16_t externalencodercontrol;      //Function
322   uint16_t cmd_function51;              //used as an internal one
323   uint16_t cmd_function52;              //used as an internal one
324   uint16_t cmd_function53;              //used as an internal one
325   uint16_t processi2cchanneltransaction;//Function
326   uint16_t cmd_function55;              //used as an internal one
327   uint16_t cmd_function56;              //used as an internal one
328   uint16_t cmd_function57;              //used as an internal one
329   uint16_t cmd_function58;              //used as an internal one
330   uint16_t cmd_function59;              //used as an internal one
331   uint16_t computegpuclockparam;        //Function
332   uint16_t cmd_function61;              //used as an internal one
333   uint16_t cmd_function62;              //used as an internal one
334   uint16_t dynamicmemorysettings;       //Function function
335   uint16_t memorytraining;              //Function function
336   uint16_t cmd_function65;              //used as an internal one
337   uint16_t cmd_function66;              //used as an internal one
338   uint16_t setvoltage;                  //Function
339   uint16_t cmd_function68;              //used as an internal one
340   uint16_t readefusevalue;              //Function
341   uint16_t cmd_function70;              //used as an internal one
342   uint16_t cmd_function71;              //used as an internal one
343   uint16_t cmd_function72;              //used as an internal one
344   uint16_t cmd_function73;              //used as an internal one
345   uint16_t cmd_function74;              //used as an internal one
346   uint16_t cmd_function75;              //used as an internal one
347   uint16_t dig1transmittercontrol;      //Function
348   uint16_t cmd_function77;              //used as an internal one
349   uint16_t processauxchanneltransaction;//Function
350   uint16_t cmd_function79;              //used as an internal one
351   uint16_t getvoltageinfo;              //Function
352 };
353 
354 struct atom_master_command_function_v2_1
355 {
356   struct atom_common_table_header  table_header;
357   struct atom_master_list_of_command_functions_v2_1 listofcmdfunctions;
358 };
359 
360 /****************************************************************************
361 * Structures used in every command function
362 ****************************************************************************/
363 struct atom_function_attribute
364 {
365   uint16_t  ws_in_bytes:8;            //[7:0]=Size of workspace in Bytes (in multiple of a dword),
366   uint16_t  ps_in_bytes:7;            //[14:8]=Size of parameter space in Bytes (multiple of a dword),
367   uint16_t  updated_by_util:1;        //[15]=flag to indicate the function is updated by util
368 };
369 
370 
371 /****************************************************************************
372 * Common header for all hw functions.
373 * Every function pointed by _master_list_of_hw_function has this common header.
374 * And the pointer actually points to this header.
375 ****************************************************************************/
376 struct atom_rom_hw_function_header
377 {
378   struct atom_common_table_header func_header;
379   struct atom_function_attribute func_attrib;
380 };
381 
382 
383 /*==============================sw data table portion======================================================================*/
384 /****************************************************************************
385 * Structures used in data.mtb, each data table name is not given here since those data table could change from time to time
386 * The real name of each table is given when its data structure version is defined
387 ****************************************************************************/
388 struct atom_master_list_of_data_tables_v2_1{
389   uint16_t utilitypipeline;               /* Offest for the utility to get parser info,Don't change this position!*/
390   uint16_t multimedia_info;
391   uint16_t smc_dpm_info;
392   uint16_t sw_datatable3;
393   uint16_t firmwareinfo;                  /* Shared by various SW components */
394   uint16_t sw_datatable5;
395   uint16_t lcd_info;                      /* Shared by various SW components */
396   uint16_t sw_datatable7;
397   uint16_t smu_info;
398   uint16_t sw_datatable9;
399   uint16_t sw_datatable10;
400   uint16_t vram_usagebyfirmware;          /* Shared by various SW components */
401   uint16_t gpio_pin_lut;                  /* Shared by various SW components */
402   uint16_t sw_datatable13;
403   uint16_t gfx_info;
404   uint16_t powerplayinfo;                 /* Shared by various SW components */
405   uint16_t sw_datatable16;
406   uint16_t sw_datatable17;
407   uint16_t sw_datatable18;
408   uint16_t sw_datatable19;
409   uint16_t sw_datatable20;
410   uint16_t sw_datatable21;
411   uint16_t displayobjectinfo;             /* Shared by various SW components */
412   uint16_t indirectioaccess;			  /* used as an internal one */
413   uint16_t umc_info;                      /* Shared by various SW components */
414   uint16_t sw_datatable25;
415   uint16_t sw_datatable26;
416   uint16_t dce_info;                      /* Shared by various SW components */
417   uint16_t vram_info;                     /* Shared by various SW components */
418   uint16_t sw_datatable29;
419   uint16_t integratedsysteminfo;          /* Shared by various SW components */
420   uint16_t asic_profiling_info;           /* Shared by various SW components */
421   uint16_t voltageobject_info;            /* shared by various SW components */
422   uint16_t sw_datatable33;
423   uint16_t sw_datatable34;
424 };
425 
426 
427 struct atom_master_data_table_v2_1
428 {
429   struct atom_common_table_header table_header;
430   struct atom_master_list_of_data_tables_v2_1 listOfdatatables;
431 };
432 
433 
434 struct atom_dtd_format
435 {
436   uint16_t  pixclk;
437   uint16_t  h_active;
438   uint16_t  h_blanking_time;
439   uint16_t  v_active;
440   uint16_t  v_blanking_time;
441   uint16_t  h_sync_offset;
442   uint16_t  h_sync_width;
443   uint16_t  v_sync_offset;
444   uint16_t  v_syncwidth;
445   uint16_t  reserved;
446   uint16_t  reserved0;
447   uint8_t   h_border;
448   uint8_t   v_border;
449   uint16_t  miscinfo;
450   uint8_t   atom_mode_id;
451   uint8_t   refreshrate;
452 };
453 
454 /* atom_dtd_format.modemiscinfo defintion */
455 enum atom_dtd_format_modemiscinfo{
456   ATOM_HSYNC_POLARITY    = 0x0002,
457   ATOM_VSYNC_POLARITY    = 0x0004,
458   ATOM_H_REPLICATIONBY2  = 0x0010,
459   ATOM_V_REPLICATIONBY2  = 0x0020,
460   ATOM_INTERLACE         = 0x0080,
461   ATOM_COMPOSITESYNC     = 0x0040,
462 };
463 
464 
465 /* utilitypipeline
466  * when format_revision==1 && content_revision==1, then this an info table for atomworks to use during debug session, no structure is associated with it.
467  * the location of it can't change
468 */
469 
470 
471 /*
472   ***************************************************************************
473     Data Table firmwareinfo  structure
474   ***************************************************************************
475 */
476 
477 struct atom_firmware_info_v3_1
478 {
479   struct atom_common_table_header table_header;
480   uint32_t firmware_revision;
481   uint32_t bootup_sclk_in10khz;
482   uint32_t bootup_mclk_in10khz;
483   uint32_t firmware_capability;             // enum atombios_firmware_capability
484   uint32_t main_call_parser_entry;          /* direct address of main parser call in VBIOS binary. */
485   uint32_t bios_scratch_reg_startaddr;      // 1st bios scratch register dword address
486   uint16_t bootup_vddc_mv;
487   uint16_t bootup_vddci_mv;
488   uint16_t bootup_mvddc_mv;
489   uint16_t bootup_vddgfx_mv;
490   uint8_t  mem_module_id;
491   uint8_t  coolingsolution_id;              /*0: Air cooling; 1: Liquid cooling ... */
492   uint8_t  reserved1[2];
493   uint32_t mc_baseaddr_high;
494   uint32_t mc_baseaddr_low;
495   uint32_t reserved2[6];
496 };
497 
498 /* Total 32bit cap indication */
499 enum atombios_firmware_capability
500 {
501 	ATOM_FIRMWARE_CAP_FIRMWARE_POSTED = 0x00000001,
502 	ATOM_FIRMWARE_CAP_GPU_VIRTUALIZATION  = 0x00000002,
503 	ATOM_FIRMWARE_CAP_WMI_SUPPORT  = 0x00000040,
504 	ATOM_FIRMWARE_CAP_HWEMU_ENABLE  = 0x00000080,
505 	ATOM_FIRMWARE_CAP_HWEMU_UMC_CFG = 0x00000100,
506 	ATOM_FIRMWARE_CAP_SRAM_ECC      = 0x00000200,
507 	ATOM_FIRMWARE_CAP_ENABLE_2STAGE_BIST_TRAINING  = 0x00000400,
508 	ATOM_FIRMWARE_CAP_ENABLE_2ND_USB20PORT = 0x0008000,
509 	ATOM_FIRMWARE_CAP_DYNAMIC_BOOT_CFG_ENABLE = 0x0020000,
510 };
511 
512 enum atom_cooling_solution_id{
513   AIR_COOLING    = 0x00,
514   LIQUID_COOLING = 0x01
515 };
516 
517 struct atom_firmware_info_v3_2 {
518   struct atom_common_table_header table_header;
519   uint32_t firmware_revision;
520   uint32_t bootup_sclk_in10khz;
521   uint32_t bootup_mclk_in10khz;
522   uint32_t firmware_capability;             // enum atombios_firmware_capability
523   uint32_t main_call_parser_entry;          /* direct address of main parser call in VBIOS binary. */
524   uint32_t bios_scratch_reg_startaddr;      // 1st bios scratch register dword address
525   uint16_t bootup_vddc_mv;
526   uint16_t bootup_vddci_mv;
527   uint16_t bootup_mvddc_mv;
528   uint16_t bootup_vddgfx_mv;
529   uint8_t  mem_module_id;
530   uint8_t  coolingsolution_id;              /*0: Air cooling; 1: Liquid cooling ... */
531   uint8_t  reserved1[2];
532   uint32_t mc_baseaddr_high;
533   uint32_t mc_baseaddr_low;
534   uint8_t  board_i2c_feature_id;            // enum of atom_board_i2c_feature_id_def
535   uint8_t  board_i2c_feature_gpio_id;       // i2c id find in gpio_lut data table gpio_id
536   uint8_t  board_i2c_feature_slave_addr;
537   uint8_t  reserved3;
538   uint16_t bootup_mvddq_mv;
539   uint16_t bootup_mvpp_mv;
540   uint32_t zfbstartaddrin16mb;
541   uint32_t reserved2[3];
542 };
543 
544 struct atom_firmware_info_v3_3
545 {
546   struct atom_common_table_header table_header;
547   uint32_t firmware_revision;
548   uint32_t bootup_sclk_in10khz;
549   uint32_t bootup_mclk_in10khz;
550   uint32_t firmware_capability;             // enum atombios_firmware_capability
551   uint32_t main_call_parser_entry;          /* direct address of main parser call in VBIOS binary. */
552   uint32_t bios_scratch_reg_startaddr;      // 1st bios scratch register dword address
553   uint16_t bootup_vddc_mv;
554   uint16_t bootup_vddci_mv;
555   uint16_t bootup_mvddc_mv;
556   uint16_t bootup_vddgfx_mv;
557   uint8_t  mem_module_id;
558   uint8_t  coolingsolution_id;              /*0: Air cooling; 1: Liquid cooling ... */
559   uint8_t  reserved1[2];
560   uint32_t mc_baseaddr_high;
561   uint32_t mc_baseaddr_low;
562   uint8_t  board_i2c_feature_id;            // enum of atom_board_i2c_feature_id_def
563   uint8_t  board_i2c_feature_gpio_id;       // i2c id find in gpio_lut data table gpio_id
564   uint8_t  board_i2c_feature_slave_addr;
565   uint8_t  reserved3;
566   uint16_t bootup_mvddq_mv;
567   uint16_t bootup_mvpp_mv;
568   uint32_t zfbstartaddrin16mb;
569   uint32_t pplib_pptable_id;                // if pplib_pptable_id!=0, pplib get powerplay table inside driver instead of from VBIOS
570   uint32_t reserved2[2];
571 };
572 
573 struct atom_firmware_info_v3_4 {
574 	struct atom_common_table_header table_header;
575 	uint32_t firmware_revision;
576 	uint32_t bootup_sclk_in10khz;
577 	uint32_t bootup_mclk_in10khz;
578 	uint32_t firmware_capability;             // enum atombios_firmware_capability
579 	uint32_t main_call_parser_entry;          /* direct address of main parser call in VBIOS binary. */
580 	uint32_t bios_scratch_reg_startaddr;      // 1st bios scratch register dword address
581 	uint16_t bootup_vddc_mv;
582 	uint16_t bootup_vddci_mv;
583 	uint16_t bootup_mvddc_mv;
584 	uint16_t bootup_vddgfx_mv;
585 	uint8_t  mem_module_id;
586 	uint8_t  coolingsolution_id;              /*0: Air cooling; 1: Liquid cooling ... */
587 	uint8_t  reserved1[2];
588 	uint32_t mc_baseaddr_high;
589 	uint32_t mc_baseaddr_low;
590 	uint8_t  board_i2c_feature_id;            // enum of atom_board_i2c_feature_id_def
591 	uint8_t  board_i2c_feature_gpio_id;       // i2c id find in gpio_lut data table gpio_id
592 	uint8_t  board_i2c_feature_slave_addr;
593 	uint8_t  ras_rom_i2c_slave_addr;
594 	uint16_t bootup_mvddq_mv;
595 	uint16_t bootup_mvpp_mv;
596 	uint32_t zfbstartaddrin16mb;
597 	uint32_t pplib_pptable_id;                // if pplib_pptable_id!=0, pplib get powerplay table inside driver instead of from VBIOS
598 	uint32_t mvdd_ratio;                      // mvdd_raio = (real mvdd in power rail)*1000/(mvdd_output_from_svi2)
599 	uint16_t hw_bootup_vddgfx_mv;             // hw default vddgfx voltage level decide by board strap
600 	uint16_t hw_bootup_vddc_mv;               // hw default vddc voltage level decide by board strap
601 	uint16_t hw_bootup_mvddc_mv;              // hw default mvddc voltage level decide by board strap
602 	uint16_t hw_bootup_vddci_mv;              // hw default vddci voltage level decide by board strap
603 	uint32_t maco_pwrlimit_mw;                // bomaco mode power limit in unit of m-watt
604 	uint32_t usb_pwrlimit_mw;                 // power limit when USB is enable in unit of m-watt
605 	uint32_t fw_reserved_size_in_kb;          // VBIOS reserved extra fw size in unit of kb.
606         uint32_t pspbl_init_done_reg_addr;
607         uint32_t pspbl_init_done_value;
608         uint32_t pspbl_init_done_check_timeout;   // time out in unit of us when polling pspbl init done
609         uint32_t reserved[2];
610 };
611 
612 /*
613   ***************************************************************************
614     Data Table lcd_info  structure
615   ***************************************************************************
616 */
617 
618 struct lcd_info_v2_1
619 {
620   struct  atom_common_table_header table_header;
621   struct  atom_dtd_format  lcd_timing;
622   uint16_t backlight_pwm;
623   uint16_t special_handle_cap;
624   uint16_t panel_misc;
625   uint16_t lvds_max_slink_pclk;
626   uint16_t lvds_ss_percentage;
627   uint16_t lvds_ss_rate_10hz;
628   uint8_t  pwr_on_digon_to_de;          /*all pwr sequence numbers below are in uint of 4ms*/
629   uint8_t  pwr_on_de_to_vary_bl;
630   uint8_t  pwr_down_vary_bloff_to_de;
631   uint8_t  pwr_down_de_to_digoff;
632   uint8_t  pwr_off_delay;
633   uint8_t  pwr_on_vary_bl_to_blon;
634   uint8_t  pwr_down_bloff_to_vary_bloff;
635   uint8_t  panel_bpc;
636   uint8_t  dpcd_edp_config_cap;
637   uint8_t  dpcd_max_link_rate;
638   uint8_t  dpcd_max_lane_count;
639   uint8_t  dpcd_max_downspread;
640   uint8_t  min_allowed_bl_level;
641   uint8_t  max_allowed_bl_level;
642   uint8_t  bootup_bl_level;
643   uint8_t  dplvdsrxid;
644   uint32_t reserved1[8];
645 };
646 
647 /* lcd_info_v2_1.panel_misc defintion */
648 enum atom_lcd_info_panel_misc{
649   ATOM_PANEL_MISC_FPDI            =0x0002,
650 };
651 
652 //uceDPToLVDSRxId
653 enum atom_lcd_info_dptolvds_rx_id
654 {
655   eDP_TO_LVDS_RX_DISABLE                 = 0x00,       // no eDP->LVDS translator chip
656   eDP_TO_LVDS_COMMON_ID                  = 0x01,       // common eDP->LVDS translator chip without AMD SW init
657   eDP_TO_LVDS_REALTEK_ID                 = 0x02,       // Realtek tansaltor which require AMD SW init
658 };
659 
660 
661 /*
662   ***************************************************************************
663     Data Table gpio_pin_lut  structure
664   ***************************************************************************
665 */
666 
667 struct atom_gpio_pin_assignment
668 {
669   uint32_t data_a_reg_index;
670   uint8_t  gpio_bitshift;
671   uint8_t  gpio_mask_bitshift;
672   uint8_t  gpio_id;
673   uint8_t  reserved;
674 };
675 
676 /* atom_gpio_pin_assignment.gpio_id definition */
677 enum atom_gpio_pin_assignment_gpio_id {
678   I2C_HW_LANE_MUX        =0x0f, /* only valid when bit7=1 */
679   I2C_HW_ENGINE_ID_MASK  =0x70, /* only valid when bit7=1 */
680   I2C_HW_CAP             =0x80, /*only when the I2C_HW_CAP is set, the pin ID is assigned to an I2C pin pair, otherwise, it's an generic GPIO pin */
681 
682   /* gpio_id pre-define id for multiple usage */
683   /* GPIO use to control PCIE_VDDC in certain SLT board */
684   PCIE_VDDC_CONTROL_GPIO_PINID = 56,
685   /* if PP_AC_DC_SWITCH_GPIO_PINID in Gpio_Pin_LutTable, AC/DC swithing feature is enable */
686   PP_AC_DC_SWITCH_GPIO_PINID = 60,
687   /* VDDC_REGULATOR_VRHOT_GPIO_PINID in Gpio_Pin_LutTable, VRHot feature is enable */
688   VDDC_VRHOT_GPIO_PINID = 61,
689   /*if VDDC_PCC_GPIO_PINID in GPIO_LUTable, Peak Current Control feature is enabled */
690   VDDC_PCC_GPIO_PINID = 62,
691   /* Only used on certain SLT/PA board to allow utility to cut Efuse. */
692   EFUSE_CUT_ENABLE_GPIO_PINID = 63,
693   /* ucGPIO=DRAM_SELF_REFRESH_GPIO_PIND uses  for memory self refresh (ucGPIO=0, DRAM self-refresh; ucGPIO= */
694   DRAM_SELF_REFRESH_GPIO_PINID = 64,
695   /* Thermal interrupt output->system thermal chip GPIO pin */
696   THERMAL_INT_OUTPUT_GPIO_PINID =65,
697 };
698 
699 
700 struct atom_gpio_pin_lut_v2_1
701 {
702   struct  atom_common_table_header  table_header;
703   /*the real number of this included in the structure is calcualted by using the (whole structure size - the header size)/size of atom_gpio_pin_lut  */
704   struct  atom_gpio_pin_assignment  gpio_pin[8];
705 };
706 
707 
708 /*
709   ***************************************************************************
710     Data Table vram_usagebyfirmware  structure
711   ***************************************************************************
712 */
713 
714 struct vram_usagebyfirmware_v2_1
715 {
716   struct  atom_common_table_header  table_header;
717   uint32_t  start_address_in_kb;
718   uint16_t  used_by_firmware_in_kb;
719   uint16_t  used_by_driver_in_kb;
720 };
721 
722 
723 /*
724   ***************************************************************************
725     Data Table displayobjectinfo  structure
726   ***************************************************************************
727 */
728 
729 enum atom_object_record_type_id {
730 	ATOM_I2C_RECORD_TYPE = 1,
731 	ATOM_HPD_INT_RECORD_TYPE = 2,
732 	ATOM_CONNECTOR_CAP_RECORD_TYPE = 3,
733 	ATOM_CONNECTOR_SPEED_UPTO = 4,
734 	ATOM_OBJECT_GPIO_CNTL_RECORD_TYPE = 9,
735 	ATOM_CONNECTOR_HPDPIN_LUT_RECORD_TYPE = 16,
736 	ATOM_CONNECTOR_AUXDDC_LUT_RECORD_TYPE = 17,
737 	ATOM_ENCODER_CAP_RECORD_TYPE = 20,
738 	ATOM_BRACKET_LAYOUT_RECORD_TYPE = 21,
739 	ATOM_CONNECTOR_FORCED_TMDS_CAP_RECORD_TYPE = 22,
740 	ATOM_DISP_CONNECTOR_CAPS_RECORD_TYPE = 23,
741 	ATOM_BRACKET_LAYOUT_V2_RECORD_TYPE = 25,
742 	ATOM_RECORD_END_TYPE = 0xFF,
743 };
744 
745 struct atom_common_record_header
746 {
747   uint8_t record_type;                      //An emun to indicate the record type
748   uint8_t record_size;                      //The size of the whole record in byte
749 };
750 
751 struct atom_i2c_record
752 {
753   struct atom_common_record_header record_header;   //record_type = ATOM_I2C_RECORD_TYPE
754   uint8_t i2c_id;
755   uint8_t i2c_slave_addr;                   //The slave address, it's 0 when the record is attached to connector for DDC
756 };
757 
758 struct atom_hpd_int_record
759 {
760   struct atom_common_record_header record_header;  //record_type = ATOM_HPD_INT_RECORD_TYPE
761   uint8_t  pin_id;              //Corresponding block in GPIO_PIN_INFO table gives the pin info
762   uint8_t  plugin_pin_state;
763 };
764 
765 struct atom_connector_caps_record {
766 	struct atom_common_record_header
767 		record_header; //record_type = ATOM_CONN_CAP_RECORD_TYPE
768 	uint16_t connector_caps; //01b if internal display is checked; 10b if internal BL is checked; 0 of Not
769 };
770 
771 struct atom_connector_speed_record {
772 	struct atom_common_record_header
773 		record_header; //record_type = ATOM_CONN_SPEED_UPTO
774 	uint32_t connector_max_speed; // connector Max speed attribute, it sets 8100 in Mhz when DP connector @8.1Ghz.
775 	uint16_t reserved;
776 };
777 
778 // Bit maps for ATOM_ENCODER_CAP_RECORD.usEncoderCap
779 enum atom_encoder_caps_def
780 {
781   ATOM_ENCODER_CAP_RECORD_HBR2                  =0x01,         // DP1.2 HBR2 is supported by HW encoder, it is retired in NI. the real meaning from SI is MST_EN
782   ATOM_ENCODER_CAP_RECORD_MST_EN                =0x01,         // from SI, this bit means DP MST is enable or not.
783   ATOM_ENCODER_CAP_RECORD_HBR2_EN               =0x02,         // DP1.2 HBR2 setting is qualified and HBR2 can be enabled
784   ATOM_ENCODER_CAP_RECORD_HDMI6Gbps_EN          =0x04,         // HDMI2.0 6Gbps enable or not.
785   ATOM_ENCODER_CAP_RECORD_HBR3_EN               =0x08,         // DP1.3 HBR3 is supported by board.
786   ATOM_ENCODER_CAP_RECORD_DP2                   =0x10,         // DP2 is supported by ASIC/board.
787   ATOM_ENCODER_CAP_RECORD_UHBR10_EN             =0x20,         // DP2.0 UHBR10 settings is supported by board
788   ATOM_ENCODER_CAP_RECORD_UHBR13_5_EN           =0x40,         // DP2.0 UHBR13.5 settings is supported by board
789   ATOM_ENCODER_CAP_RECORD_UHBR20_EN             =0x80,         // DP2.0 UHBR20 settings is supported by board
790   ATOM_ENCODER_CAP_RECORD_USB_C_TYPE            =0x100,        // the DP connector is a USB-C type.
791 };
792 
793 struct  atom_encoder_caps_record
794 {
795   struct atom_common_record_header record_header;  //record_type = ATOM_ENCODER_CAP_RECORD_TYPE
796   uint32_t  encodercaps;
797 };
798 
799 enum atom_connector_caps_def
800 {
801   ATOM_CONNECTOR_CAP_INTERNAL_DISPLAY         = 0x01,        //a cap bit to indicate that this non-embedded display connector is an internal display
802   ATOM_CONNECTOR_CAP_INTERNAL_DISPLAY_BL      = 0x02,        //a cap bit to indicate that this internal display requires BL control from GPU, refers to lcd_info for BL PWM freq
803 };
804 
805 struct atom_disp_connector_caps_record
806 {
807   struct atom_common_record_header record_header;
808   uint32_t connectcaps;
809 };
810 
811 //The following generic object gpio pin control record type will replace JTAG_RECORD/FPGA_CONTROL_RECORD/DVI_EXT_INPUT_RECORD above gradually
812 struct atom_gpio_pin_control_pair
813 {
814   uint8_t gpio_id;               // GPIO_ID, find the corresponding ID in GPIO_LUT table
815   uint8_t gpio_pinstate;         // Pin state showing how to set-up the pin
816 };
817 
818 struct atom_object_gpio_cntl_record
819 {
820   struct atom_common_record_header record_header;
821   uint8_t flag;                   // Future expnadibility
822   uint8_t number_of_pins;         // Number of GPIO pins used to control the object
823   struct atom_gpio_pin_control_pair gpio[1];              // the real gpio pin pair determined by number of pins ucNumberOfPins
824 };
825 
826 //Definitions for GPIO pin state
827 enum atom_gpio_pin_control_pinstate_def
828 {
829   GPIO_PIN_TYPE_INPUT             = 0x00,
830   GPIO_PIN_TYPE_OUTPUT            = 0x10,
831   GPIO_PIN_TYPE_HW_CONTROL        = 0x20,
832 
833 //For GPIO_PIN_TYPE_OUTPUT the following is defined
834   GPIO_PIN_OUTPUT_STATE_MASK      = 0x01,
835   GPIO_PIN_OUTPUT_STATE_SHIFT     = 0,
836   GPIO_PIN_STATE_ACTIVE_LOW       = 0x0,
837   GPIO_PIN_STATE_ACTIVE_HIGH      = 0x1,
838 };
839 
840 // Indexes to GPIO array in GLSync record
841 // GLSync record is for Frame Lock/Gen Lock feature.
842 enum atom_glsync_record_gpio_index_def
843 {
844   ATOM_GPIO_INDEX_GLSYNC_REFCLK    = 0,
845   ATOM_GPIO_INDEX_GLSYNC_HSYNC     = 1,
846   ATOM_GPIO_INDEX_GLSYNC_VSYNC     = 2,
847   ATOM_GPIO_INDEX_GLSYNC_SWAP_REQ  = 3,
848   ATOM_GPIO_INDEX_GLSYNC_SWAP_GNT  = 4,
849   ATOM_GPIO_INDEX_GLSYNC_INTERRUPT = 5,
850   ATOM_GPIO_INDEX_GLSYNC_V_RESET   = 6,
851   ATOM_GPIO_INDEX_GLSYNC_SWAP_CNTL = 7,
852   ATOM_GPIO_INDEX_GLSYNC_SWAP_SEL  = 8,
853   ATOM_GPIO_INDEX_GLSYNC_MAX       = 9,
854 };
855 
856 
857 struct atom_connector_hpdpin_lut_record     //record for ATOM_CONNECTOR_HPDPIN_LUT_RECORD_TYPE
858 {
859   struct atom_common_record_header record_header;
860   uint8_t hpd_pin_map[8];
861 };
862 
863 struct atom_connector_auxddc_lut_record     //record for ATOM_CONNECTOR_AUXDDC_LUT_RECORD_TYPE
864 {
865   struct atom_common_record_header record_header;
866   uint8_t aux_ddc_map[8];
867 };
868 
869 struct atom_connector_forced_tmds_cap_record
870 {
871   struct atom_common_record_header record_header;
872   // override TMDS capability on this connector when it operate in TMDS mode.  usMaxTmdsClkRate = max TMDS Clock in Mhz/2.5
873   uint8_t  maxtmdsclkrate_in2_5mhz;
874   uint8_t  reserved;
875 };
876 
877 struct atom_connector_layout_info
878 {
879   uint16_t connectorobjid;
880   uint8_t  connector_type;
881   uint8_t  position;
882 };
883 
884 // define ATOM_CONNECTOR_LAYOUT_INFO.ucConnectorType to describe the display connector size
885 enum atom_connector_layout_info_connector_type_def
886 {
887   CONNECTOR_TYPE_DVI_D                 = 1,
888 
889   CONNECTOR_TYPE_HDMI                  = 4,
890   CONNECTOR_TYPE_DISPLAY_PORT          = 5,
891   CONNECTOR_TYPE_MINI_DISPLAY_PORT     = 6,
892 };
893 
894 struct  atom_bracket_layout_record
895 {
896   struct atom_common_record_header record_header;
897   uint8_t bracketlen;
898   uint8_t bracketwidth;
899   uint8_t conn_num;
900   uint8_t reserved;
901   struct atom_connector_layout_info  conn_info[1];
902 };
903 struct atom_bracket_layout_record_v2 {
904 	struct atom_common_record_header
905 		record_header; //record_type =  ATOM_BRACKET_LAYOUT_RECORD_TYPE
906 	uint8_t bracketlen; //Bracket Length in mm
907 	uint8_t bracketwidth; //Bracket Width in mm
908 	uint8_t conn_num; //Connector numbering
909 	uint8_t mini_type; //Mini Type (0 = Normal; 1 = Mini)
910 	uint8_t reserved1;
911 	uint8_t reserved2;
912 };
913 
914 enum atom_connector_layout_info_mini_type_def {
915 	MINI_TYPE_NORMAL = 0,
916 	MINI_TYPE_MINI = 1,
917 };
918 
919 enum atom_display_device_tag_def{
920   ATOM_DISPLAY_LCD1_SUPPORT            = 0x0002, //an embedded display is either an LVDS or eDP signal type of display
921   ATOM_DISPLAY_LCD2_SUPPORT			       = 0x0020, //second edp device tag 0x0020 for backward compability
922   ATOM_DISPLAY_DFP1_SUPPORT            = 0x0008,
923   ATOM_DISPLAY_DFP2_SUPPORT            = 0x0080,
924   ATOM_DISPLAY_DFP3_SUPPORT            = 0x0200,
925   ATOM_DISPLAY_DFP4_SUPPORT            = 0x0400,
926   ATOM_DISPLAY_DFP5_SUPPORT            = 0x0800,
927   ATOM_DISPLAY_DFP6_SUPPORT            = 0x0040,
928   ATOM_DISPLAY_DFPx_SUPPORT            = 0x0ec8,
929 };
930 
931 struct atom_display_object_path_v2
932 {
933   uint16_t display_objid;                  //Connector Object ID or Misc Object ID
934   uint16_t disp_recordoffset;
935   uint16_t encoderobjid;                   //first encoder closer to the connector, could be either an external or intenal encoder
936   uint16_t extencoderobjid;                //2nd encoder after the first encoder, from the connector point of view;
937   uint16_t encoder_recordoffset;
938   uint16_t extencoder_recordoffset;
939   uint16_t device_tag;                     //a supported device vector, each display path starts with this.the paths are enumerated in the way of priority, a path appears first
940   uint8_t  priority_id;
941   uint8_t  reserved;
942 };
943 
944 struct atom_display_object_path_v3 {
945 	uint16_t display_objid; //Connector Object ID or Misc Object ID
946 	uint16_t disp_recordoffset;
947 	uint16_t encoderobjid; //first encoder closer to the connector, could be either an external or intenal encoder
948 	uint16_t reserved1; //only on USBC case, otherwise always = 0
949 	uint16_t reserved2; //reserved and always = 0
950 	uint16_t reserved3; //reserved and always = 0
951 	//a supported device vector, each display path starts with this.the paths are enumerated in the way of priority,
952 	//a path appears first
953 	uint16_t device_tag;
954 	uint16_t reserved4; //reserved and always = 0
955 };
956 
957 struct display_object_info_table_v1_4
958 {
959   struct    atom_common_table_header  table_header;
960   uint16_t  supporteddevices;
961   uint8_t   number_of_path;
962   uint8_t   reserved;
963   struct    atom_display_object_path_v2 display_path[8];   //the real number of this included in the structure is calculated by using the (whole structure size - the header size- number_of_path)/size of atom_display_object_path
964 };
965 
966 struct display_object_info_table_v1_5 {
967 	struct atom_common_table_header table_header;
968 	uint16_t supporteddevices;
969 	uint8_t number_of_path;
970 	uint8_t reserved;
971 	// the real number of this included in the structure is calculated by using the
972 	// (whole structure size - the header size- number_of_path)/size of atom_display_object_path
973 	struct atom_display_object_path_v3 display_path[8];
974 };
975 
976 /*
977   ***************************************************************************
978     Data Table dce_info  structure
979   ***************************************************************************
980 */
981 struct atom_display_controller_info_v4_1
982 {
983   struct  atom_common_table_header  table_header;
984   uint32_t display_caps;
985   uint32_t bootup_dispclk_10khz;
986   uint16_t dce_refclk_10khz;
987   uint16_t i2c_engine_refclk_10khz;
988   uint16_t dvi_ss_percentage;       // in unit of 0.001%
989   uint16_t dvi_ss_rate_10hz;
990   uint16_t hdmi_ss_percentage;      // in unit of 0.001%
991   uint16_t hdmi_ss_rate_10hz;
992   uint16_t dp_ss_percentage;        // in unit of 0.001%
993   uint16_t dp_ss_rate_10hz;
994   uint8_t  dvi_ss_mode;             // enum of atom_spread_spectrum_mode
995   uint8_t  hdmi_ss_mode;            // enum of atom_spread_spectrum_mode
996   uint8_t  dp_ss_mode;              // enum of atom_spread_spectrum_mode
997   uint8_t  ss_reserved;
998   uint8_t  hardcode_mode_num;       // a hardcode mode number defined in StandardVESA_TimingTable when a CRT or DFP EDID is not available
999   uint8_t  reserved1[3];
1000   uint16_t dpphy_refclk_10khz;
1001   uint16_t reserved2;
1002   uint8_t  dceip_min_ver;
1003   uint8_t  dceip_max_ver;
1004   uint8_t  max_disp_pipe_num;
1005   uint8_t  max_vbios_active_disp_pipe_num;
1006   uint8_t  max_ppll_num;
1007   uint8_t  max_disp_phy_num;
1008   uint8_t  max_aux_pairs;
1009   uint8_t  remotedisplayconfig;
1010   uint8_t  reserved3[8];
1011 };
1012 
1013 struct atom_display_controller_info_v4_2
1014 {
1015   struct  atom_common_table_header  table_header;
1016   uint32_t display_caps;
1017   uint32_t bootup_dispclk_10khz;
1018   uint16_t dce_refclk_10khz;
1019   uint16_t i2c_engine_refclk_10khz;
1020   uint16_t dvi_ss_percentage;       // in unit of 0.001%
1021   uint16_t dvi_ss_rate_10hz;
1022   uint16_t hdmi_ss_percentage;      // in unit of 0.001%
1023   uint16_t hdmi_ss_rate_10hz;
1024   uint16_t dp_ss_percentage;        // in unit of 0.001%
1025   uint16_t dp_ss_rate_10hz;
1026   uint8_t  dvi_ss_mode;             // enum of atom_spread_spectrum_mode
1027   uint8_t  hdmi_ss_mode;            // enum of atom_spread_spectrum_mode
1028   uint8_t  dp_ss_mode;              // enum of atom_spread_spectrum_mode
1029   uint8_t  ss_reserved;
1030   uint8_t  dfp_hardcode_mode_num;   // DFP hardcode mode number defined in StandardVESA_TimingTable when EDID is not available
1031   uint8_t  dfp_hardcode_refreshrate;// DFP hardcode mode refreshrate defined in StandardVESA_TimingTable when EDID is not available
1032   uint8_t  vga_hardcode_mode_num;   // VGA hardcode mode number defined in StandardVESA_TimingTable when EDID is not avablable
1033   uint8_t  vga_hardcode_refreshrate;// VGA hardcode mode number defined in StandardVESA_TimingTable when EDID is not avablable
1034   uint16_t dpphy_refclk_10khz;
1035   uint16_t reserved2;
1036   uint8_t  dcnip_min_ver;
1037   uint8_t  dcnip_max_ver;
1038   uint8_t  max_disp_pipe_num;
1039   uint8_t  max_vbios_active_disp_pipe_num;
1040   uint8_t  max_ppll_num;
1041   uint8_t  max_disp_phy_num;
1042   uint8_t  max_aux_pairs;
1043   uint8_t  remotedisplayconfig;
1044   uint8_t  reserved3[8];
1045 };
1046 
1047 struct atom_display_controller_info_v4_3
1048 {
1049   struct  atom_common_table_header  table_header;
1050   uint32_t display_caps;
1051   uint32_t bootup_dispclk_10khz;
1052   uint16_t dce_refclk_10khz;
1053   uint16_t i2c_engine_refclk_10khz;
1054   uint16_t dvi_ss_percentage;       // in unit of 0.001%
1055   uint16_t dvi_ss_rate_10hz;
1056   uint16_t hdmi_ss_percentage;      // in unit of 0.001%
1057   uint16_t hdmi_ss_rate_10hz;
1058   uint16_t dp_ss_percentage;        // in unit of 0.001%
1059   uint16_t dp_ss_rate_10hz;
1060   uint8_t  dvi_ss_mode;             // enum of atom_spread_spectrum_mode
1061   uint8_t  hdmi_ss_mode;            // enum of atom_spread_spectrum_mode
1062   uint8_t  dp_ss_mode;              // enum of atom_spread_spectrum_mode
1063   uint8_t  ss_reserved;
1064   uint8_t  dfp_hardcode_mode_num;   // DFP hardcode mode number defined in StandardVESA_TimingTable when EDID is not available
1065   uint8_t  dfp_hardcode_refreshrate;// DFP hardcode mode refreshrate defined in StandardVESA_TimingTable when EDID is not available
1066   uint8_t  vga_hardcode_mode_num;   // VGA hardcode mode number defined in StandardVESA_TimingTable when EDID is not avablable
1067   uint8_t  vga_hardcode_refreshrate;// VGA hardcode mode number defined in StandardVESA_TimingTable when EDID is not avablable
1068   uint16_t dpphy_refclk_10khz;
1069   uint16_t reserved2;
1070   uint8_t  dcnip_min_ver;
1071   uint8_t  dcnip_max_ver;
1072   uint8_t  max_disp_pipe_num;
1073   uint8_t  max_vbios_active_disp_pipe_num;
1074   uint8_t  max_ppll_num;
1075   uint8_t  max_disp_phy_num;
1076   uint8_t  max_aux_pairs;
1077   uint8_t  remotedisplayconfig;
1078   uint8_t  reserved3[8];
1079 };
1080 
1081 struct atom_display_controller_info_v4_4 {
1082 	struct atom_common_table_header table_header;
1083 	uint32_t display_caps;
1084 	uint32_t bootup_dispclk_10khz;
1085 	uint16_t dce_refclk_10khz;
1086 	uint16_t i2c_engine_refclk_10khz;
1087 	uint16_t dvi_ss_percentage;	 // in unit of 0.001%
1088 	uint16_t dvi_ss_rate_10hz;
1089 	uint16_t hdmi_ss_percentage;	 // in unit of 0.001%
1090 	uint16_t hdmi_ss_rate_10hz;
1091 	uint16_t dp_ss_percentage;	 // in unit of 0.001%
1092 	uint16_t dp_ss_rate_10hz;
1093 	uint8_t dvi_ss_mode;		 // enum of atom_spread_spectrum_mode
1094 	uint8_t hdmi_ss_mode;		 // enum of atom_spread_spectrum_mode
1095 	uint8_t dp_ss_mode;		 // enum of atom_spread_spectrum_mode
1096 	uint8_t ss_reserved;
1097 	uint8_t dfp_hardcode_mode_num;	 // DFP hardcode mode number defined in StandardVESA_TimingTable when EDID is not available
1098 	uint8_t dfp_hardcode_refreshrate;// DFP hardcode mode refreshrate defined in StandardVESA_TimingTable when EDID is not available
1099 	uint8_t vga_hardcode_mode_num;	 // VGA hardcode mode number defined in StandardVESA_TimingTable when EDID is not avablable
1100 	uint8_t vga_hardcode_refreshrate;// VGA hardcode mode number defined in StandardVESA_TimingTable when EDID is not avablable
1101 	uint16_t dpphy_refclk_10khz;
1102 	uint16_t hw_chip_id;
1103 	uint8_t dcnip_min_ver;
1104 	uint8_t dcnip_max_ver;
1105 	uint8_t max_disp_pipe_num;
1106 	uint8_t max_vbios_active_disp_pipum;
1107 	uint8_t max_ppll_num;
1108 	uint8_t max_disp_phy_num;
1109 	uint8_t max_aux_pairs;
1110 	uint8_t remotedisplayconfig;
1111 	uint32_t dispclk_pll_vco_freq;
1112 	uint32_t dp_ref_clk_freq;
1113 	uint32_t max_mclk_chg_lat;	 // Worst case blackout duration for a memory clock frequency (p-state) change, units of 100s of ns (0.1 us)
1114 	uint32_t max_sr_exit_lat;	 // Worst case memory self refresh exit time, units of 100ns of ns (0.1us)
1115 	uint32_t max_sr_enter_exit_lat;	 // Worst case memory self refresh entry followed by immediate exit time, units of 100ns of ns (0.1us)
1116 	uint16_t dc_golden_table_offset; // point of struct of atom_dc_golden_table_vxx
1117 	uint16_t dc_golden_table_ver;
1118 	uint32_t reserved3[3];
1119 };
1120 
1121 struct atom_dc_golden_table_v1
1122 {
1123 	uint32_t aux_dphy_rx_control0_val;
1124 	uint32_t aux_dphy_tx_control_val;
1125 	uint32_t aux_dphy_rx_control1_val;
1126 	uint32_t dc_gpio_aux_ctrl_0_val;
1127 	uint32_t dc_gpio_aux_ctrl_1_val;
1128 	uint32_t dc_gpio_aux_ctrl_2_val;
1129 	uint32_t dc_gpio_aux_ctrl_3_val;
1130 	uint32_t dc_gpio_aux_ctrl_4_val;
1131 	uint32_t dc_gpio_aux_ctrl_5_val;
1132 	uint32_t reserved[23];
1133 };
1134 
1135 enum dce_info_caps_def {
1136 	// only for VBIOS
1137 	DCE_INFO_CAPS_FORCE_DISPDEV_CONNECTED = 0x02,
1138 	// only for VBIOS
1139 	DCE_INFO_CAPS_DISABLE_DFP_DP_HBR2 = 0x04,
1140 	// only for VBIOS
1141 	DCE_INFO_CAPS_ENABLE_INTERLAC_TIMING = 0x08,
1142 	// only for VBIOS
1143 	DCE_INFO_CAPS_LTTPR_SUPPORT_ENABLE = 0x20,
1144 	DCE_INFO_CAPS_VBIOS_LTTPR_TRANSPARENT_ENABLE = 0x40,
1145 };
1146 
1147 struct atom_display_controller_info_v4_5
1148 {
1149   struct  atom_common_table_header  table_header;
1150   uint32_t display_caps;
1151   uint32_t bootup_dispclk_10khz;
1152   uint16_t dce_refclk_10khz;
1153   uint16_t i2c_engine_refclk_10khz;
1154   uint16_t dvi_ss_percentage;       // in unit of 0.001%
1155   uint16_t dvi_ss_rate_10hz;
1156   uint16_t hdmi_ss_percentage;      // in unit of 0.001%
1157   uint16_t hdmi_ss_rate_10hz;
1158   uint16_t dp_ss_percentage;        // in unit of 0.001%
1159   uint16_t dp_ss_rate_10hz;
1160   uint8_t  dvi_ss_mode;             // enum of atom_spread_spectrum_mode
1161   uint8_t  hdmi_ss_mode;            // enum of atom_spread_spectrum_mode
1162   uint8_t  dp_ss_mode;              // enum of atom_spread_spectrum_mode
1163   uint8_t  ss_reserved;
1164   // DFP hardcode mode number defined in StandardVESA_TimingTable when EDID is not available
1165   uint8_t  dfp_hardcode_mode_num;
1166   // DFP hardcode mode refreshrate defined in StandardVESA_TimingTable when EDID is not available
1167   uint8_t  dfp_hardcode_refreshrate;
1168   // VGA hardcode mode number defined in StandardVESA_TimingTable when EDID is not avablable
1169   uint8_t  vga_hardcode_mode_num;
1170   // VGA hardcode mode number defined in StandardVESA_TimingTable when EDID is not avablable
1171   uint8_t  vga_hardcode_refreshrate;
1172   uint16_t dpphy_refclk_10khz;
1173   uint16_t hw_chip_id;
1174   uint8_t  dcnip_min_ver;
1175   uint8_t  dcnip_max_ver;
1176   uint8_t  max_disp_pipe_num;
1177   uint8_t  max_vbios_active_disp_pipe_num;
1178   uint8_t  max_ppll_num;
1179   uint8_t  max_disp_phy_num;
1180   uint8_t  max_aux_pairs;
1181   uint8_t  remotedisplayconfig;
1182   uint32_t dispclk_pll_vco_freq;
1183   uint32_t dp_ref_clk_freq;
1184   // Worst case blackout duration for a memory clock frequency (p-state) change, units of 100s of ns (0.1 us)
1185   uint32_t max_mclk_chg_lat;
1186   // Worst case memory self refresh exit time, units of 100ns of ns (0.1us)
1187   uint32_t max_sr_exit_lat;
1188   // Worst case memory self refresh entry followed by immediate exit time, units of 100ns of ns (0.1us)
1189   uint32_t max_sr_enter_exit_lat;
1190   uint16_t dc_golden_table_offset;  // point of struct of atom_dc_golden_table_vxx
1191   uint16_t dc_golden_table_ver;
1192   uint32_t aux_dphy_rx_control0_val;
1193   uint32_t aux_dphy_tx_control_val;
1194   uint32_t aux_dphy_rx_control1_val;
1195   uint32_t dc_gpio_aux_ctrl_0_val;
1196   uint32_t dc_gpio_aux_ctrl_1_val;
1197   uint32_t dc_gpio_aux_ctrl_2_val;
1198   uint32_t dc_gpio_aux_ctrl_3_val;
1199   uint32_t dc_gpio_aux_ctrl_4_val;
1200   uint32_t dc_gpio_aux_ctrl_5_val;
1201   uint32_t reserved[26];
1202 };
1203 
1204 /*
1205   ***************************************************************************
1206     Data Table ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO  structure
1207   ***************************************************************************
1208 */
1209 struct atom_ext_display_path
1210 {
1211   uint16_t  device_tag;                      //A bit vector to show what devices are supported
1212   uint16_t  device_acpi_enum;                //16bit device ACPI id.
1213   uint16_t  connectorobjid;                  //A physical connector for displays to plug in, using object connector definitions
1214   uint8_t   auxddclut_index;                 //An index into external AUX/DDC channel LUT
1215   uint8_t   hpdlut_index;                    //An index into external HPD pin LUT
1216   uint16_t  ext_encoder_objid;               //external encoder object id
1217   uint8_t   channelmapping;                  // if ucChannelMapping=0, using default one to one mapping
1218   uint8_t   chpninvert;                      // bit vector for up to 8 lanes, =0: P and N is not invert, =1 P and N is inverted
1219   uint16_t  caps;
1220   uint16_t  reserved;
1221 };
1222 
1223 //usCaps
1224 enum ext_display_path_cap_def {
1225 	EXT_DISPLAY_PATH_CAPS__HBR2_DISABLE =           0x0001,
1226 	EXT_DISPLAY_PATH_CAPS__DP_FIXED_VS_EN =         0x0002,
1227 	EXT_DISPLAY_PATH_CAPS__EXT_CHIP_MASK =          0x007C,
1228 	EXT_DISPLAY_PATH_CAPS__HDMI20_PI3EQX1204 =      (0x01 << 2), //PI redriver chip
1229 	EXT_DISPLAY_PATH_CAPS__HDMI20_TISN65DP159RSBT = (0x02 << 2), //TI retimer chip
1230 	EXT_DISPLAY_PATH_CAPS__HDMI20_PARADE_PS175 =    (0x03 << 2)  //Parade DP->HDMI recoverter chip
1231 };
1232 
1233 struct atom_external_display_connection_info
1234 {
1235   struct  atom_common_table_header  table_header;
1236   uint8_t                  guid[16];                                  // a GUID is a 16 byte long string
1237   struct atom_ext_display_path path[7];                               // total of fixed 7 entries.
1238   uint8_t                  checksum;                                  // a simple Checksum of the sum of whole structure equal to 0x0.
1239   uint8_t                  stereopinid;                               // use for eDP panel
1240   uint8_t                  remotedisplayconfig;
1241   uint8_t                  edptolvdsrxid;
1242   uint8_t                  fixdpvoltageswing;                         // usCaps[1]=1, this indicate DP_LANE_SET value
1243   uint8_t                  reserved[3];                               // for potential expansion
1244 };
1245 
1246 /*
1247   ***************************************************************************
1248     Data Table integratedsysteminfo  structure
1249   ***************************************************************************
1250 */
1251 
1252 struct atom_camera_dphy_timing_param
1253 {
1254   uint8_t  profile_id;       // SENSOR_PROFILES
1255   uint32_t param;
1256 };
1257 
1258 struct atom_camera_dphy_elec_param
1259 {
1260   uint16_t param[3];
1261 };
1262 
1263 struct atom_camera_module_info
1264 {
1265   uint8_t module_id;                    // 0: Rear, 1: Front right of user, 2: Front left of user
1266   uint8_t module_name[8];
1267   struct atom_camera_dphy_timing_param timingparam[6]; // Exact number is under estimation and confirmation from sensor vendor
1268 };
1269 
1270 struct atom_camera_flashlight_info
1271 {
1272   uint8_t flashlight_id;                // 0: Rear, 1: Front
1273   uint8_t name[8];
1274 };
1275 
1276 struct atom_camera_data
1277 {
1278   uint32_t versionCode;
1279   struct atom_camera_module_info cameraInfo[3];      // Assuming 3 camera sensors max
1280   struct atom_camera_flashlight_info flashInfo;      // Assuming 1 flashlight max
1281   struct atom_camera_dphy_elec_param dphy_param;
1282   uint32_t crc_val;         // CRC
1283 };
1284 
1285 
1286 struct atom_14nm_dpphy_dvihdmi_tuningset
1287 {
1288   uint32_t max_symclk_in10khz;
1289   uint8_t encoder_mode;            //atom_encode_mode_def, =2: DVI, =3: HDMI mode
1290   uint8_t phy_sel;                 //bit vector of phy, bit0= phya, bit1=phyb, ....bit5 = phyf
1291   uint16_t margindeemph;           //COMMON_MAR_DEEMPH_NOM[7:0]tx_margin_nom [15:8]deemph_gen1_nom
1292   uint8_t deemph_6db_4;            //COMMON_SELDEEMPH60[31:24]deemph_6db_4
1293   uint8_t boostadj;                //CMD_BUS_GLOBAL_FOR_TX_LANE0 [19:16]tx_boost_adj  [20]tx_boost_en  [23:22]tx_binary_ron_code_offset
1294   uint8_t tx_driver_fifty_ohms;    //COMMON_ZCALCODE_CTRL[21].tx_driver_fifty_ohms
1295   uint8_t deemph_sel;              //MARGIN_DEEMPH_LANE0.DEEMPH_SEL
1296 };
1297 
1298 struct atom_14nm_dpphy_dp_setting{
1299   uint8_t dp_vs_pemph_level;       //enum of atom_dp_vs_preemph_def
1300   uint16_t margindeemph;           //COMMON_MAR_DEEMPH_NOM[7:0]tx_margin_nom [15:8]deemph_gen1_nom
1301   uint8_t deemph_6db_4;            //COMMON_SELDEEMPH60[31:24]deemph_6db_4
1302   uint8_t boostadj;                //CMD_BUS_GLOBAL_FOR_TX_LANE0 [19:16]tx_boost_adj  [20]tx_boost_en  [23:22]tx_binary_ron_code_offset
1303 };
1304 
1305 struct atom_14nm_dpphy_dp_tuningset{
1306   uint8_t phy_sel;                 // bit vector of phy, bit0= phya, bit1=phyb, ....bit5 = phyf
1307   uint8_t version;
1308   uint16_t table_size;             // size of atom_14nm_dpphy_dp_tuningset
1309   uint16_t reserved;
1310   struct atom_14nm_dpphy_dp_setting dptuning[10];
1311 };
1312 
1313 struct atom_14nm_dig_transmitter_info_header_v4_0{
1314   struct  atom_common_table_header  table_header;
1315   uint16_t pcie_phy_tmds_hdmi_macro_settings_offset;     // offset of PCIEPhyTMDSHDMIMacroSettingsTbl
1316   uint16_t uniphy_vs_emph_lookup_table_offset;           // offset of UniphyVSEmphLookUpTbl
1317   uint16_t uniphy_xbar_settings_table_offset;            // offset of UniphyXbarSettingsTbl
1318 };
1319 
1320 struct atom_14nm_combphy_tmds_vs_set
1321 {
1322   uint8_t sym_clk;
1323   uint8_t dig_mode;
1324   uint8_t phy_sel;
1325   uint16_t common_mar_deemph_nom__margin_deemph_val;
1326   uint8_t common_seldeemph60__deemph_6db_4_val;
1327   uint8_t cmd_bus_global_for_tx_lane0__boostadj_val ;
1328   uint8_t common_zcalcode_ctrl__tx_driver_fifty_ohms_val;
1329   uint8_t margin_deemph_lane0__deemph_sel_val;
1330 };
1331 
1332 struct atom_DCN_dpphy_dvihdmi_tuningset
1333 {
1334   uint32_t max_symclk_in10khz;
1335   uint8_t  encoder_mode;           //atom_encode_mode_def, =2: DVI, =3: HDMI mode
1336   uint8_t  phy_sel;                //bit vector of phy, bit0= phya, bit1=phyb, ....bit5 = phyf
1337   uint8_t  tx_eq_main;             // map to RDPCSTX_PHY_FUSE0/1/2/3[5:0](EQ_MAIN)
1338   uint8_t  tx_eq_pre;              // map to RDPCSTX_PHY_FUSE0/1/2/3[11:6](EQ_PRE)
1339   uint8_t  tx_eq_post;             // map to RDPCSTX_PHY_FUSE0/1/2/3[17:12](EQ_POST)
1340   uint8_t  reserved1;
1341   uint8_t  tx_vboost_lvl;          // tx_vboost_lvl, map to RDPCSTX_PHY_CNTL0.RDPCS_PHY_TX_VBOOST_LVL
1342   uint8_t  reserved2;
1343 };
1344 
1345 struct atom_DCN_dpphy_dp_setting{
1346   uint8_t dp_vs_pemph_level;       //enum of atom_dp_vs_preemph_def
1347   uint8_t tx_eq_main;             // map to RDPCSTX_PHY_FUSE0/1/2/3[5:0](EQ_MAIN)
1348   uint8_t tx_eq_pre;              // map to RDPCSTX_PHY_FUSE0/1/2/3[11:6](EQ_PRE)
1349   uint8_t tx_eq_post;             // map to RDPCSTX_PHY_FUSE0/1/2/3[17:12](EQ_POST)
1350   uint8_t tx_vboost_lvl;          // tx_vboost_lvl, map to RDPCSTX_PHY_CNTL0.RDPCS_PHY_TX_VBOOST_LVL
1351 };
1352 
1353 struct atom_DCN_dpphy_dp_tuningset{
1354   uint8_t phy_sel;                 // bit vector of phy, bit0= phya, bit1=phyb, ....bit5 = phyf
1355   uint8_t version;
1356   uint16_t table_size;             // size of atom_14nm_dpphy_dp_setting
1357   uint16_t reserved;
1358   struct atom_DCN_dpphy_dp_setting dptunings[10];
1359 };
1360 
1361 struct atom_i2c_reg_info {
1362   uint8_t ucI2cRegIndex;
1363   uint8_t ucI2cRegVal;
1364 };
1365 
1366 struct atom_hdmi_retimer_redriver_set {
1367   uint8_t HdmiSlvAddr;
1368   uint8_t HdmiRegNum;
1369   uint8_t Hdmi6GRegNum;
1370   struct atom_i2c_reg_info HdmiRegSetting[9];        //For non 6G Hz use
1371   struct atom_i2c_reg_info Hdmi6GhzRegSetting[3];    //For 6G Hz use.
1372 };
1373 
1374 struct atom_integrated_system_info_v1_11
1375 {
1376   struct  atom_common_table_header  table_header;
1377   uint32_t  vbios_misc;                       //enum of atom_system_vbiosmisc_def
1378   uint32_t  gpucapinfo;                       //enum of atom_system_gpucapinf_def
1379   uint32_t  system_config;
1380   uint32_t  cpucapinfo;
1381   uint16_t  gpuclk_ss_percentage;             //unit of 0.001%,   1000 mean 1%
1382   uint16_t  gpuclk_ss_type;
1383   uint16_t  lvds_ss_percentage;               //unit of 0.001%,   1000 mean 1%
1384   uint16_t  lvds_ss_rate_10hz;
1385   uint16_t  hdmi_ss_percentage;               //unit of 0.001%,   1000 mean 1%
1386   uint16_t  hdmi_ss_rate_10hz;
1387   uint16_t  dvi_ss_percentage;                //unit of 0.001%,   1000 mean 1%
1388   uint16_t  dvi_ss_rate_10hz;
1389   uint16_t  dpphy_override;                   // bit vector, enum of atom_sysinfo_dpphy_override_def
1390   uint16_t  lvds_misc;                        // enum of atom_sys_info_lvds_misc_def
1391   uint16_t  backlight_pwm_hz;                 // pwm frequency in hz
1392   uint8_t   memorytype;                       // enum of atom_dmi_t17_mem_type_def, APU memory type indication.
1393   uint8_t   umachannelnumber;                 // number of memory channels
1394   uint8_t   pwr_on_digon_to_de;               /* all pwr sequence numbers below are in uint of 4ms */
1395   uint8_t   pwr_on_de_to_vary_bl;
1396   uint8_t   pwr_down_vary_bloff_to_de;
1397   uint8_t   pwr_down_de_to_digoff;
1398   uint8_t   pwr_off_delay;
1399   uint8_t   pwr_on_vary_bl_to_blon;
1400   uint8_t   pwr_down_bloff_to_vary_bloff;
1401   uint8_t   min_allowed_bl_level;
1402   uint8_t   htc_hyst_limit;
1403   uint8_t   htc_tmp_limit;
1404   uint8_t   reserved1;
1405   uint8_t   reserved2;
1406   struct atom_external_display_connection_info extdispconninfo;
1407   struct atom_14nm_dpphy_dvihdmi_tuningset dvi_tuningset;
1408   struct atom_14nm_dpphy_dvihdmi_tuningset hdmi_tuningset;
1409   struct atom_14nm_dpphy_dvihdmi_tuningset hdmi6g_tuningset;
1410   struct atom_14nm_dpphy_dp_tuningset dp_tuningset;        // rbr 1.62G dp tuning set
1411   struct atom_14nm_dpphy_dp_tuningset dp_hbr3_tuningset;   // HBR3 dp tuning set
1412   struct atom_camera_data  camera_info;
1413   struct atom_hdmi_retimer_redriver_set dp0_retimer_set;   //for DP0
1414   struct atom_hdmi_retimer_redriver_set dp1_retimer_set;   //for DP1
1415   struct atom_hdmi_retimer_redriver_set dp2_retimer_set;   //for DP2
1416   struct atom_hdmi_retimer_redriver_set dp3_retimer_set;   //for DP3
1417   struct atom_14nm_dpphy_dp_tuningset dp_hbr_tuningset;    //hbr 2.7G dp tuning set
1418   struct atom_14nm_dpphy_dp_tuningset dp_hbr2_tuningset;   //hbr2 5.4G dp turnig set
1419   struct atom_14nm_dpphy_dp_tuningset edp_tuningset;       //edp tuning set
1420   uint32_t  reserved[66];
1421 };
1422 
1423 struct atom_integrated_system_info_v1_12
1424 {
1425   struct  atom_common_table_header  table_header;
1426   uint32_t  vbios_misc;                       //enum of atom_system_vbiosmisc_def
1427   uint32_t  gpucapinfo;                       //enum of atom_system_gpucapinf_def
1428   uint32_t  system_config;
1429   uint32_t  cpucapinfo;
1430   uint16_t  gpuclk_ss_percentage;             //unit of 0.001%,   1000 mean 1%
1431   uint16_t  gpuclk_ss_type;
1432   uint16_t  lvds_ss_percentage;               //unit of 0.001%,   1000 mean 1%
1433   uint16_t  lvds_ss_rate_10hz;
1434   uint16_t  hdmi_ss_percentage;               //unit of 0.001%,   1000 mean 1%
1435   uint16_t  hdmi_ss_rate_10hz;
1436   uint16_t  dvi_ss_percentage;                //unit of 0.001%,   1000 mean 1%
1437   uint16_t  dvi_ss_rate_10hz;
1438   uint16_t  dpphy_override;                   // bit vector, enum of atom_sysinfo_dpphy_override_def
1439   uint16_t  lvds_misc;                        // enum of atom_sys_info_lvds_misc_def
1440   uint16_t  backlight_pwm_hz;                 // pwm frequency in hz
1441   uint8_t   memorytype;                       // enum of atom_dmi_t17_mem_type_def, APU memory type indication.
1442   uint8_t   umachannelnumber;                 // number of memory channels
1443   uint8_t   pwr_on_digon_to_de;               // all pwr sequence numbers below are in uint of 4ms //
1444   uint8_t   pwr_on_de_to_vary_bl;
1445   uint8_t   pwr_down_vary_bloff_to_de;
1446   uint8_t   pwr_down_de_to_digoff;
1447   uint8_t   pwr_off_delay;
1448   uint8_t   pwr_on_vary_bl_to_blon;
1449   uint8_t   pwr_down_bloff_to_vary_bloff;
1450   uint8_t   min_allowed_bl_level;
1451   uint8_t   htc_hyst_limit;
1452   uint8_t   htc_tmp_limit;
1453   uint8_t   reserved1;
1454   uint8_t   reserved2;
1455   struct atom_external_display_connection_info extdispconninfo;
1456   struct atom_DCN_dpphy_dvihdmi_tuningset  TMDS_tuningset;
1457   struct atom_DCN_dpphy_dvihdmi_tuningset  hdmiCLK5_tuningset;
1458   struct atom_DCN_dpphy_dvihdmi_tuningset  hdmiCLK8_tuningset;
1459   struct atom_DCN_dpphy_dp_tuningset rbr_tuningset;        // rbr 1.62G dp tuning set
1460   struct atom_DCN_dpphy_dp_tuningset hbr3_tuningset;   // HBR3 dp tuning set
1461   struct atom_camera_data  camera_info;
1462   struct atom_hdmi_retimer_redriver_set dp0_retimer_set;   //for DP0
1463   struct atom_hdmi_retimer_redriver_set dp1_retimer_set;   //for DP1
1464   struct atom_hdmi_retimer_redriver_set dp2_retimer_set;   //for DP2
1465   struct atom_hdmi_retimer_redriver_set dp3_retimer_set;   //for DP3
1466   struct atom_DCN_dpphy_dp_tuningset hbr_tuningset;    //hbr 2.7G dp tuning set
1467   struct atom_DCN_dpphy_dp_tuningset hbr2_tuningset;   //hbr2 5.4G dp turnig set
1468   struct atom_DCN_dpphy_dp_tuningset edp_tunings;       //edp tuning set
1469   struct atom_DCN_dpphy_dvihdmi_tuningset  hdmiCLK6_tuningset;
1470   uint32_t  reserved[63];
1471 };
1472 
1473 struct edp_info_table
1474 {
1475         uint16_t edp_backlight_pwm_hz;
1476         uint16_t edp_ss_percentage;
1477         uint16_t edp_ss_rate_10hz;
1478         uint16_t reserved1;
1479         uint32_t reserved2;
1480         uint8_t  edp_pwr_on_off_delay;
1481         uint8_t  edp_pwr_on_vary_bl_to_blon;
1482         uint8_t  edp_pwr_down_bloff_to_vary_bloff;
1483         uint8_t  edp_panel_bpc;
1484         uint8_t  edp_bootup_bl_level;
1485         uint8_t  reserved3[3];
1486         uint32_t reserved4[3];
1487 };
1488 
1489 struct atom_integrated_system_info_v2_1
1490 {
1491         struct  atom_common_table_header  table_header;
1492         uint32_t  vbios_misc;                       //enum of atom_system_vbiosmisc_def
1493         uint32_t  gpucapinfo;                       //enum of atom_system_gpucapinf_def
1494         uint32_t  system_config;
1495         uint32_t  cpucapinfo;
1496         uint16_t  gpuclk_ss_percentage;             //unit of 0.001%,   1000 mean 1%
1497         uint16_t  gpuclk_ss_type;
1498         uint16_t  dpphy_override;                   // bit vector, enum of atom_sysinfo_dpphy_override_def
1499         uint8_t   memorytype;                       // enum of atom_dmi_t17_mem_type_def, APU memory type indication.
1500         uint8_t   umachannelnumber;                 // number of memory channels
1501         uint8_t   htc_hyst_limit;
1502         uint8_t   htc_tmp_limit;
1503         uint8_t   reserved1;
1504         uint8_t   reserved2;
1505         struct edp_info_table edp1_info;
1506         struct edp_info_table edp2_info;
1507         uint32_t  reserved3[8];
1508         struct atom_external_display_connection_info extdispconninfo;
1509         struct atom_DCN_dpphy_dvihdmi_tuningset  TMDS_tuningset;
1510         struct atom_DCN_dpphy_dvihdmi_tuningset  hdmiCLK5_tuningset; //add clk6
1511         struct atom_DCN_dpphy_dvihdmi_tuningset  hdmiCLK6_tuningset;
1512         struct atom_DCN_dpphy_dvihdmi_tuningset  hdmiCLK8_tuningset;
1513         uint32_t reserved4[6];//reserve 2*sizeof(atom_DCN_dpphy_dvihdmi_tuningset)
1514         struct atom_DCN_dpphy_dp_tuningset rbr_tuningset;        // rbr 1.62G dp tuning set
1515         struct atom_DCN_dpphy_dp_tuningset hbr_tuningset;    //hbr 2.7G dp tuning set
1516         struct atom_DCN_dpphy_dp_tuningset hbr2_tuningset;   //hbr2 5.4G dp turnig set
1517         struct atom_DCN_dpphy_dp_tuningset hbr3_tuningset;   // HBR3 dp tuning set
1518         struct atom_DCN_dpphy_dp_tuningset edp_tunings;       //edp tuning set
1519         uint32_t reserved5[28];//reserve 2*sizeof(atom_DCN_dpphy_dp_tuningset)
1520         struct atom_hdmi_retimer_redriver_set dp0_retimer_set;   //for DP0
1521         struct atom_hdmi_retimer_redriver_set dp1_retimer_set;   //for DP1
1522         struct atom_hdmi_retimer_redriver_set dp2_retimer_set;   //for DP2
1523         struct atom_hdmi_retimer_redriver_set dp3_retimer_set;   //for DP3
1524         uint32_t reserved6[30];// reserve size of(atom_camera_data) for camera_info
1525         uint32_t reserved7[32];
1526 
1527 };
1528 
1529 struct atom_n6_display_phy_tuning_set {
1530 	uint8_t display_signal_type;
1531 	uint8_t phy_sel;
1532 	uint8_t preset_level;
1533 	uint8_t reserved1;
1534 	uint32_t reserved2;
1535 	uint32_t speed_upto;
1536 	uint8_t tx_vboost_level;
1537 	uint8_t tx_vreg_v2i;
1538 	uint8_t tx_vregdrv_byp;
1539 	uint8_t tx_term_cntl;
1540 	uint8_t tx_peak_level;
1541 	uint8_t tx_slew_en;
1542 	uint8_t tx_eq_pre;
1543 	uint8_t tx_eq_main;
1544 	uint8_t tx_eq_post;
1545 	uint8_t tx_en_inv_pre;
1546 	uint8_t tx_en_inv_post;
1547 	uint8_t reserved3;
1548 	uint32_t reserved4;
1549 	uint32_t reserved5;
1550 	uint32_t reserved6;
1551 };
1552 
1553 struct atom_display_phy_tuning_info {
1554 	struct atom_common_table_header table_header;
1555 	struct atom_n6_display_phy_tuning_set disp_phy_tuning[1];
1556 };
1557 
1558 struct atom_integrated_system_info_v2_2
1559 {
1560 	struct  atom_common_table_header  table_header;
1561 	uint32_t  vbios_misc;                       //enum of atom_system_vbiosmisc_def
1562 	uint32_t  gpucapinfo;                       //enum of atom_system_gpucapinf_def
1563 	uint32_t  system_config;
1564 	uint32_t  cpucapinfo;
1565 	uint16_t  gpuclk_ss_percentage;             //unit of 0.001%,   1000 mean 1%
1566 	uint16_t  gpuclk_ss_type;
1567 	uint16_t  dpphy_override;                   // bit vector, enum of atom_sysinfo_dpphy_override_def
1568 	uint8_t   memorytype;                       // enum of atom_dmi_t17_mem_type_def, APU memory type indication.
1569 	uint8_t   umachannelnumber;                 // number of memory channels
1570 	uint8_t   htc_hyst_limit;
1571 	uint8_t   htc_tmp_limit;
1572 	uint8_t   reserved1;
1573 	uint8_t   reserved2;
1574 	struct edp_info_table edp1_info;
1575 	struct edp_info_table edp2_info;
1576 	uint32_t  reserved3[8];
1577 	struct atom_external_display_connection_info extdispconninfo;
1578 
1579 	uint32_t  reserved4[189];
1580 };
1581 
1582 // system_config
1583 enum atom_system_vbiosmisc_def{
1584   INTEGRATED_SYSTEM_INFO__GET_EDID_CALLBACK_FUNC_SUPPORT = 0x01,
1585 };
1586 
1587 
1588 // gpucapinfo
1589 enum atom_system_gpucapinf_def{
1590   SYS_INFO_GPUCAPS__ENABEL_DFS_BYPASS  = 0x10,
1591 };
1592 
1593 //dpphy_override
1594 enum atom_sysinfo_dpphy_override_def{
1595   ATOM_ENABLE_DVI_TUNINGSET   = 0x01,
1596   ATOM_ENABLE_HDMI_TUNINGSET  = 0x02,
1597   ATOM_ENABLE_HDMI6G_TUNINGSET  = 0x04,
1598   ATOM_ENABLE_DP_TUNINGSET  = 0x08,
1599   ATOM_ENABLE_DP_HBR3_TUNINGSET  = 0x10,
1600 };
1601 
1602 //lvds_misc
1603 enum atom_sys_info_lvds_misc_def
1604 {
1605   SYS_INFO_LVDS_MISC_888_FPDI_MODE                 =0x01,
1606   SYS_INFO_LVDS_MISC_888_BPC_MODE                  =0x04,
1607   SYS_INFO_LVDS_MISC_OVERRIDE_EN                   =0x08,
1608 };
1609 
1610 
1611 //memorytype  DMI Type 17 offset 12h - Memory Type
1612 enum atom_dmi_t17_mem_type_def{
1613   OtherMemType = 0x01,                                  ///< Assign 01 to Other
1614   UnknownMemType,                                       ///< Assign 02 to Unknown
1615   DramMemType,                                          ///< Assign 03 to DRAM
1616   EdramMemType,                                         ///< Assign 04 to EDRAM
1617   VramMemType,                                          ///< Assign 05 to VRAM
1618   SramMemType,                                          ///< Assign 06 to SRAM
1619   RamMemType,                                           ///< Assign 07 to RAM
1620   RomMemType,                                           ///< Assign 08 to ROM
1621   FlashMemType,                                         ///< Assign 09 to Flash
1622   EepromMemType,                                        ///< Assign 10 to EEPROM
1623   FepromMemType,                                        ///< Assign 11 to FEPROM
1624   EpromMemType,                                         ///< Assign 12 to EPROM
1625   CdramMemType,                                         ///< Assign 13 to CDRAM
1626   ThreeDramMemType,                                     ///< Assign 14 to 3DRAM
1627   SdramMemType,                                         ///< Assign 15 to SDRAM
1628   SgramMemType,                                         ///< Assign 16 to SGRAM
1629   RdramMemType,                                         ///< Assign 17 to RDRAM
1630   DdrMemType,                                           ///< Assign 18 to DDR
1631   Ddr2MemType,                                          ///< Assign 19 to DDR2
1632   Ddr2FbdimmMemType,                                    ///< Assign 20 to DDR2 FB-DIMM
1633   Ddr3MemType = 0x18,                                   ///< Assign 24 to DDR3
1634   Fbd2MemType,                                          ///< Assign 25 to FBD2
1635   Ddr4MemType,                                          ///< Assign 26 to DDR4
1636   LpDdrMemType,                                         ///< Assign 27 to LPDDR
1637   LpDdr2MemType,                                        ///< Assign 28 to LPDDR2
1638   LpDdr3MemType,                                        ///< Assign 29 to LPDDR3
1639   LpDdr4MemType,                                        ///< Assign 30 to LPDDR4
1640   GDdr6MemType,                                         ///< Assign 31 to GDDR6
1641   HbmMemType,                                           ///< Assign 32 to HBM
1642   Hbm2MemType,                                          ///< Assign 33 to HBM2
1643   Ddr5MemType,                                          ///< Assign 34 to DDR5
1644   LpDdr5MemType,                                        ///< Assign 35 to LPDDR5
1645 };
1646 
1647 
1648 // this Table is used starting from NL/AM, used by SBIOS and pass the IntegratedSystemInfoTable/PowerPlayInfoTable/SystemCameraInfoTable
1649 struct atom_fusion_system_info_v4
1650 {
1651   struct atom_integrated_system_info_v1_11   sysinfo;           // refer to ATOM_INTEGRATED_SYSTEM_INFO_V1_8 definition
1652   uint32_t   powerplayinfo[256];                                // Reserve 1024 bytes space for PowerPlayInfoTable
1653 };
1654 
1655 
1656 /*
1657   ***************************************************************************
1658     Data Table gfx_info  structure
1659   ***************************************************************************
1660 */
1661 
1662 struct  atom_gfx_info_v2_2
1663 {
1664   struct  atom_common_table_header  table_header;
1665   uint8_t gfxip_min_ver;
1666   uint8_t gfxip_max_ver;
1667   uint8_t max_shader_engines;
1668   uint8_t max_tile_pipes;
1669   uint8_t max_cu_per_sh;
1670   uint8_t max_sh_per_se;
1671   uint8_t max_backends_per_se;
1672   uint8_t max_texture_channel_caches;
1673   uint32_t regaddr_cp_dma_src_addr;
1674   uint32_t regaddr_cp_dma_src_addr_hi;
1675   uint32_t regaddr_cp_dma_dst_addr;
1676   uint32_t regaddr_cp_dma_dst_addr_hi;
1677   uint32_t regaddr_cp_dma_command;
1678   uint32_t regaddr_cp_status;
1679   uint32_t regaddr_rlc_gpu_clock_32;
1680   uint32_t rlc_gpu_timer_refclk;
1681 };
1682 
1683 struct  atom_gfx_info_v2_3 {
1684   struct  atom_common_table_header  table_header;
1685   uint8_t gfxip_min_ver;
1686   uint8_t gfxip_max_ver;
1687   uint8_t max_shader_engines;
1688   uint8_t max_tile_pipes;
1689   uint8_t max_cu_per_sh;
1690   uint8_t max_sh_per_se;
1691   uint8_t max_backends_per_se;
1692   uint8_t max_texture_channel_caches;
1693   uint32_t regaddr_cp_dma_src_addr;
1694   uint32_t regaddr_cp_dma_src_addr_hi;
1695   uint32_t regaddr_cp_dma_dst_addr;
1696   uint32_t regaddr_cp_dma_dst_addr_hi;
1697   uint32_t regaddr_cp_dma_command;
1698   uint32_t regaddr_cp_status;
1699   uint32_t regaddr_rlc_gpu_clock_32;
1700   uint32_t rlc_gpu_timer_refclk;
1701   uint8_t active_cu_per_sh;
1702   uint8_t active_rb_per_se;
1703   uint16_t gcgoldenoffset;
1704   uint32_t rm21_sram_vmin_value;
1705 };
1706 
1707 struct  atom_gfx_info_v2_4
1708 {
1709   struct  atom_common_table_header  table_header;
1710   uint8_t gfxip_min_ver;
1711   uint8_t gfxip_max_ver;
1712   uint8_t max_shader_engines;
1713   uint8_t reserved;
1714   uint8_t max_cu_per_sh;
1715   uint8_t max_sh_per_se;
1716   uint8_t max_backends_per_se;
1717   uint8_t max_texture_channel_caches;
1718   uint32_t regaddr_cp_dma_src_addr;
1719   uint32_t regaddr_cp_dma_src_addr_hi;
1720   uint32_t regaddr_cp_dma_dst_addr;
1721   uint32_t regaddr_cp_dma_dst_addr_hi;
1722   uint32_t regaddr_cp_dma_command;
1723   uint32_t regaddr_cp_status;
1724   uint32_t regaddr_rlc_gpu_clock_32;
1725   uint32_t rlc_gpu_timer_refclk;
1726   uint8_t active_cu_per_sh;
1727   uint8_t active_rb_per_se;
1728   uint16_t gcgoldenoffset;
1729   uint16_t gc_num_gprs;
1730   uint16_t gc_gsprim_buff_depth;
1731   uint16_t gc_parameter_cache_depth;
1732   uint16_t gc_wave_size;
1733   uint16_t gc_max_waves_per_simd;
1734   uint16_t gc_lds_size;
1735   uint8_t gc_num_max_gs_thds;
1736   uint8_t gc_gs_table_depth;
1737   uint8_t gc_double_offchip_lds_buffer;
1738   uint8_t gc_max_scratch_slots_per_cu;
1739   uint32_t sram_rm_fuses_val;
1740   uint32_t sram_custom_rm_fuses_val;
1741 };
1742 
1743 struct atom_gfx_info_v2_7 {
1744 	struct atom_common_table_header table_header;
1745 	uint8_t gfxip_min_ver;
1746 	uint8_t gfxip_max_ver;
1747 	uint8_t max_shader_engines;
1748 	uint8_t reserved;
1749 	uint8_t max_cu_per_sh;
1750 	uint8_t max_sh_per_se;
1751 	uint8_t max_backends_per_se;
1752 	uint8_t max_texture_channel_caches;
1753 	uint32_t regaddr_cp_dma_src_addr;
1754 	uint32_t regaddr_cp_dma_src_addr_hi;
1755 	uint32_t regaddr_cp_dma_dst_addr;
1756 	uint32_t regaddr_cp_dma_dst_addr_hi;
1757 	uint32_t regaddr_cp_dma_command;
1758 	uint32_t regaddr_cp_status;
1759 	uint32_t regaddr_rlc_gpu_clock_32;
1760 	uint32_t rlc_gpu_timer_refclk;
1761 	uint8_t active_cu_per_sh;
1762 	uint8_t active_rb_per_se;
1763 	uint16_t gcgoldenoffset;
1764 	uint16_t gc_num_gprs;
1765 	uint16_t gc_gsprim_buff_depth;
1766 	uint16_t gc_parameter_cache_depth;
1767 	uint16_t gc_wave_size;
1768 	uint16_t gc_max_waves_per_simd;
1769 	uint16_t gc_lds_size;
1770 	uint8_t gc_num_max_gs_thds;
1771 	uint8_t gc_gs_table_depth;
1772 	uint8_t gc_double_offchip_lds_buffer;
1773 	uint8_t gc_max_scratch_slots_per_cu;
1774 	uint32_t sram_rm_fuses_val;
1775 	uint32_t sram_custom_rm_fuses_val;
1776 	uint8_t cut_cu;
1777 	uint8_t active_cu_total;
1778 	uint8_t cu_reserved[2];
1779 	uint32_t gc_config;
1780 	uint8_t inactive_cu_per_se[8];
1781 	uint32_t reserved2[6];
1782 };
1783 
1784 struct atom_gfx_info_v3_0 {
1785 	struct atom_common_table_header table_header;
1786 	uint8_t gfxip_min_ver;
1787 	uint8_t gfxip_max_ver;
1788 	uint8_t max_shader_engines;
1789 	uint8_t max_tile_pipes;
1790 	uint8_t max_cu_per_sh;
1791 	uint8_t max_sh_per_se;
1792 	uint8_t max_backends_per_se;
1793 	uint8_t max_texture_channel_caches;
1794 	uint32_t regaddr_lsdma_queue0_rb_rptr;
1795 	uint32_t regaddr_lsdma_queue0_rb_rptr_hi;
1796 	uint32_t regaddr_lsdma_queue0_rb_wptr;
1797 	uint32_t regaddr_lsdma_queue0_rb_wptr_hi;
1798 	uint32_t regaddr_lsdma_command;
1799 	uint32_t regaddr_lsdma_status;
1800 	uint32_t regaddr_golden_tsc_count_lower;
1801 	uint32_t golden_tsc_count_lower_refclk;
1802 	uint8_t active_wgp_per_se;
1803 	uint8_t active_rb_per_se;
1804 	uint8_t active_se;
1805 	uint8_t reserved1;
1806 	uint32_t sram_rm_fuses_val;
1807 	uint32_t sram_custom_rm_fuses_val;
1808 	uint32_t inactive_sa_mask;
1809 	uint32_t gc_config;
1810 	uint8_t inactive_wgp[16];
1811 	uint8_t inactive_rb[16];
1812 	uint32_t gdfll_as_wait_ctrl_val;
1813 	uint32_t gdfll_as_step_ctrl_val;
1814 	uint32_t reserved[8];
1815 };
1816 
1817 /*
1818   ***************************************************************************
1819     Data Table smu_info  structure
1820   ***************************************************************************
1821 */
1822 struct atom_smu_info_v3_1
1823 {
1824   struct  atom_common_table_header  table_header;
1825   uint8_t smuip_min_ver;
1826   uint8_t smuip_max_ver;
1827   uint8_t smu_rsd1;
1828   uint8_t gpuclk_ss_mode;           // enum of atom_spread_spectrum_mode
1829   uint16_t sclk_ss_percentage;
1830   uint16_t sclk_ss_rate_10hz;
1831   uint16_t gpuclk_ss_percentage;    // in unit of 0.001%
1832   uint16_t gpuclk_ss_rate_10hz;
1833   uint32_t core_refclk_10khz;
1834   uint8_t  ac_dc_gpio_bit;          // GPIO bit shift in SMU_GPIOPAD_A  configured for AC/DC switching, =0xff means invalid
1835   uint8_t  ac_dc_polarity;          // GPIO polarity for AC/DC switching
1836   uint8_t  vr0hot_gpio_bit;         // GPIO bit shift in SMU_GPIOPAD_A  configured for VR0 HOT event, =0xff means invalid
1837   uint8_t  vr0hot_polarity;         // GPIO polarity for VR0 HOT event
1838   uint8_t  vr1hot_gpio_bit;         // GPIO bit shift in SMU_GPIOPAD_A configured for VR1 HOT event , =0xff means invalid
1839   uint8_t  vr1hot_polarity;         // GPIO polarity for VR1 HOT event
1840   uint8_t  fw_ctf_gpio_bit;         // GPIO bit shift in SMU_GPIOPAD_A configured for CTF, =0xff means invalid
1841   uint8_t  fw_ctf_polarity;         // GPIO polarity for CTF
1842 };
1843 
1844 struct atom_smu_info_v3_2 {
1845   struct   atom_common_table_header  table_header;
1846   uint8_t  smuip_min_ver;
1847   uint8_t  smuip_max_ver;
1848   uint8_t  smu_rsd1;
1849   uint8_t  gpuclk_ss_mode;
1850   uint16_t sclk_ss_percentage;
1851   uint16_t sclk_ss_rate_10hz;
1852   uint16_t gpuclk_ss_percentage;    // in unit of 0.001%
1853   uint16_t gpuclk_ss_rate_10hz;
1854   uint32_t core_refclk_10khz;
1855   uint8_t  ac_dc_gpio_bit;          // GPIO bit shift in SMU_GPIOPAD_A  configured for AC/DC switching, =0xff means invalid
1856   uint8_t  ac_dc_polarity;          // GPIO polarity for AC/DC switching
1857   uint8_t  vr0hot_gpio_bit;         // GPIO bit shift in SMU_GPIOPAD_A  configured for VR0 HOT event, =0xff means invalid
1858   uint8_t  vr0hot_polarity;         // GPIO polarity for VR0 HOT event
1859   uint8_t  vr1hot_gpio_bit;         // GPIO bit shift in SMU_GPIOPAD_A configured for VR1 HOT event , =0xff means invalid
1860   uint8_t  vr1hot_polarity;         // GPIO polarity for VR1 HOT event
1861   uint8_t  fw_ctf_gpio_bit;         // GPIO bit shift in SMU_GPIOPAD_A configured for CTF, =0xff means invalid
1862   uint8_t  fw_ctf_polarity;         // GPIO polarity for CTF
1863   uint8_t  pcc_gpio_bit;            // GPIO bit shift in SMU_GPIOPAD_A configured for PCC, =0xff means invalid
1864   uint8_t  pcc_gpio_polarity;       // GPIO polarity for CTF
1865   uint16_t smugoldenoffset;
1866   uint32_t gpupll_vco_freq_10khz;
1867   uint32_t bootup_smnclk_10khz;
1868   uint32_t bootup_socclk_10khz;
1869   uint32_t bootup_mp0clk_10khz;
1870   uint32_t bootup_mp1clk_10khz;
1871   uint32_t bootup_lclk_10khz;
1872   uint32_t bootup_dcefclk_10khz;
1873   uint32_t ctf_threshold_override_value;
1874   uint32_t reserved[5];
1875 };
1876 
1877 struct atom_smu_info_v3_3 {
1878   struct   atom_common_table_header  table_header;
1879   uint8_t  smuip_min_ver;
1880   uint8_t  smuip_max_ver;
1881   uint8_t  waflclk_ss_mode;
1882   uint8_t  gpuclk_ss_mode;
1883   uint16_t sclk_ss_percentage;
1884   uint16_t sclk_ss_rate_10hz;
1885   uint16_t gpuclk_ss_percentage;    // in unit of 0.001%
1886   uint16_t gpuclk_ss_rate_10hz;
1887   uint32_t core_refclk_10khz;
1888   uint8_t  ac_dc_gpio_bit;          // GPIO bit shift in SMU_GPIOPAD_A  configured for AC/DC switching, =0xff means invalid
1889   uint8_t  ac_dc_polarity;          // GPIO polarity for AC/DC switching
1890   uint8_t  vr0hot_gpio_bit;         // GPIO bit shift in SMU_GPIOPAD_A  configured for VR0 HOT event, =0xff means invalid
1891   uint8_t  vr0hot_polarity;         // GPIO polarity for VR0 HOT event
1892   uint8_t  vr1hot_gpio_bit;         // GPIO bit shift in SMU_GPIOPAD_A configured for VR1 HOT event , =0xff means invalid
1893   uint8_t  vr1hot_polarity;         // GPIO polarity for VR1 HOT event
1894   uint8_t  fw_ctf_gpio_bit;         // GPIO bit shift in SMU_GPIOPAD_A configured for CTF, =0xff means invalid
1895   uint8_t  fw_ctf_polarity;         // GPIO polarity for CTF
1896   uint8_t  pcc_gpio_bit;            // GPIO bit shift in SMU_GPIOPAD_A configured for PCC, =0xff means invalid
1897   uint8_t  pcc_gpio_polarity;       // GPIO polarity for CTF
1898   uint16_t smugoldenoffset;
1899   uint32_t gpupll_vco_freq_10khz;
1900   uint32_t bootup_smnclk_10khz;
1901   uint32_t bootup_socclk_10khz;
1902   uint32_t bootup_mp0clk_10khz;
1903   uint32_t bootup_mp1clk_10khz;
1904   uint32_t bootup_lclk_10khz;
1905   uint32_t bootup_dcefclk_10khz;
1906   uint32_t ctf_threshold_override_value;
1907   uint32_t syspll3_0_vco_freq_10khz;
1908   uint32_t syspll3_1_vco_freq_10khz;
1909   uint32_t bootup_fclk_10khz;
1910   uint32_t bootup_waflclk_10khz;
1911   uint32_t smu_info_caps;
1912   uint16_t waflclk_ss_percentage;    // in unit of 0.001%
1913   uint16_t smuinitoffset;
1914   uint32_t reserved;
1915 };
1916 
1917 struct atom_smu_info_v3_5
1918 {
1919   struct   atom_common_table_header  table_header;
1920   uint8_t  smuip_min_ver;
1921   uint8_t  smuip_max_ver;
1922   uint8_t  waflclk_ss_mode;
1923   uint8_t  gpuclk_ss_mode;
1924   uint16_t sclk_ss_percentage;
1925   uint16_t sclk_ss_rate_10hz;
1926   uint16_t gpuclk_ss_percentage;    // in unit of 0.001%
1927   uint16_t gpuclk_ss_rate_10hz;
1928   uint32_t core_refclk_10khz;
1929   uint32_t syspll0_1_vco_freq_10khz;
1930   uint32_t syspll0_2_vco_freq_10khz;
1931   uint8_t  pcc_gpio_bit;            // GPIO bit shift in SMU_GPIOPAD_A configured for PCC, =0xff means invalid
1932   uint8_t  pcc_gpio_polarity;       // GPIO polarity for CTF
1933   uint16_t smugoldenoffset;
1934   uint32_t syspll0_0_vco_freq_10khz;
1935   uint32_t bootup_smnclk_10khz;
1936   uint32_t bootup_socclk_10khz;
1937   uint32_t bootup_mp0clk_10khz;
1938   uint32_t bootup_mp1clk_10khz;
1939   uint32_t bootup_lclk_10khz;
1940   uint32_t bootup_dcefclk_10khz;
1941   uint32_t ctf_threshold_override_value;
1942   uint32_t syspll3_0_vco_freq_10khz;
1943   uint32_t syspll3_1_vco_freq_10khz;
1944   uint32_t bootup_fclk_10khz;
1945   uint32_t bootup_waflclk_10khz;
1946   uint32_t smu_info_caps;
1947   uint16_t waflclk_ss_percentage;    // in unit of 0.001%
1948   uint16_t smuinitoffset;
1949   uint32_t bootup_dprefclk_10khz;
1950   uint32_t bootup_usbclk_10khz;
1951   uint32_t smb_slave_address;
1952   uint32_t cg_fdo_ctrl0_val;
1953   uint32_t cg_fdo_ctrl1_val;
1954   uint32_t cg_fdo_ctrl2_val;
1955   uint32_t gdfll_as_wait_ctrl_val;
1956   uint32_t gdfll_as_step_ctrl_val;
1957   uint32_t bootup_dtbclk_10khz;
1958   uint32_t fclk_syspll_refclk_10khz;
1959   uint32_t smusvi_svc0_val;
1960   uint32_t smusvi_svc1_val;
1961   uint32_t smusvi_svd0_val;
1962   uint32_t smusvi_svd1_val;
1963   uint32_t smusvi_svt0_val;
1964   uint32_t smusvi_svt1_val;
1965   uint32_t cg_tach_ctrl_val;
1966   uint32_t cg_pump_ctrl1_val;
1967   uint32_t cg_pump_tach_ctrl_val;
1968   uint32_t thm_ctf_delay_val;
1969   uint32_t thm_thermal_int_ctrl_val;
1970   uint32_t thm_tmon_config_val;
1971   uint32_t reserved[16];
1972 };
1973 
1974 struct atom_smu_info_v3_6
1975 {
1976 	struct   atom_common_table_header  table_header;
1977 	uint8_t  smuip_min_ver;
1978 	uint8_t  smuip_max_ver;
1979 	uint8_t  waflclk_ss_mode;
1980 	uint8_t  gpuclk_ss_mode;
1981 	uint16_t sclk_ss_percentage;
1982 	uint16_t sclk_ss_rate_10hz;
1983 	uint16_t gpuclk_ss_percentage;
1984 	uint16_t gpuclk_ss_rate_10hz;
1985 	uint32_t core_refclk_10khz;
1986 	uint32_t syspll0_1_vco_freq_10khz;
1987 	uint32_t syspll0_2_vco_freq_10khz;
1988 	uint8_t  pcc_gpio_bit;
1989 	uint8_t  pcc_gpio_polarity;
1990 	uint16_t smugoldenoffset;
1991 	uint32_t syspll0_0_vco_freq_10khz;
1992 	uint32_t bootup_smnclk_10khz;
1993 	uint32_t bootup_socclk_10khz;
1994 	uint32_t bootup_mp0clk_10khz;
1995 	uint32_t bootup_mp1clk_10khz;
1996 	uint32_t bootup_lclk_10khz;
1997 	uint32_t bootup_dxioclk_10khz;
1998 	uint32_t ctf_threshold_override_value;
1999 	uint32_t syspll3_0_vco_freq_10khz;
2000 	uint32_t syspll3_1_vco_freq_10khz;
2001 	uint32_t bootup_fclk_10khz;
2002 	uint32_t bootup_waflclk_10khz;
2003 	uint32_t smu_info_caps;
2004 	uint16_t waflclk_ss_percentage;
2005 	uint16_t smuinitoffset;
2006 	uint32_t bootup_gfxavsclk_10khz;
2007 	uint32_t bootup_mpioclk_10khz;
2008 	uint32_t smb_slave_address;
2009 	uint32_t cg_fdo_ctrl0_val;
2010 	uint32_t cg_fdo_ctrl1_val;
2011 	uint32_t cg_fdo_ctrl2_val;
2012 	uint32_t gdfll_as_wait_ctrl_val;
2013 	uint32_t gdfll_as_step_ctrl_val;
2014 	uint32_t reserved_clk;
2015 	uint32_t fclk_syspll_refclk_10khz;
2016 	uint32_t smusvi_svc0_val;
2017 	uint32_t smusvi_svc1_val;
2018 	uint32_t smusvi_svd0_val;
2019 	uint32_t smusvi_svd1_val;
2020 	uint32_t smusvi_svt0_val;
2021 	uint32_t smusvi_svt1_val;
2022 	uint32_t cg_tach_ctrl_val;
2023 	uint32_t cg_pump_ctrl1_val;
2024 	uint32_t cg_pump_tach_ctrl_val;
2025 	uint32_t thm_ctf_delay_val;
2026 	uint32_t thm_thermal_int_ctrl_val;
2027 	uint32_t thm_tmon_config_val;
2028 	uint32_t bootup_vclk_10khz;
2029 	uint32_t bootup_dclk_10khz;
2030 	uint32_t smu_gpiopad_pu_en_val;
2031 	uint32_t smu_gpiopad_pd_en_val;
2032 	uint32_t reserved[12];
2033 };
2034 
2035 struct atom_smu_info_v4_0 {
2036 	struct atom_common_table_header table_header;
2037 	uint32_t bootup_gfxclk_bypass_10khz;
2038 	uint32_t bootup_usrclk_10khz;
2039 	uint32_t bootup_csrclk_10khz;
2040 	uint32_t core_refclk_10khz;
2041 	uint32_t syspll1_vco_freq_10khz;
2042 	uint32_t syspll2_vco_freq_10khz;
2043 	uint8_t pcc_gpio_bit;
2044 	uint8_t pcc_gpio_polarity;
2045 	uint16_t bootup_vddusr_mv;
2046 	uint32_t syspll0_vco_freq_10khz;
2047 	uint32_t bootup_smnclk_10khz;
2048 	uint32_t bootup_socclk_10khz;
2049 	uint32_t bootup_mp0clk_10khz;
2050 	uint32_t bootup_mp1clk_10khz;
2051 	uint32_t bootup_lclk_10khz;
2052 	uint32_t bootup_dcefclk_10khz;
2053 	uint32_t ctf_threshold_override_value;
2054 	uint32_t syspll3_vco_freq_10khz;
2055 	uint32_t mm_syspll_vco_freq_10khz;
2056 	uint32_t bootup_fclk_10khz;
2057 	uint32_t bootup_waflclk_10khz;
2058 	uint32_t smu_info_caps;
2059 	uint16_t waflclk_ss_percentage;
2060 	uint16_t smuinitoffset;
2061 	uint32_t bootup_dprefclk_10khz;
2062 	uint32_t bootup_usbclk_10khz;
2063 	uint32_t smb_slave_address;
2064 	uint32_t cg_fdo_ctrl0_val;
2065 	uint32_t cg_fdo_ctrl1_val;
2066 	uint32_t cg_fdo_ctrl2_val;
2067 	uint32_t gdfll_as_wait_ctrl_val;
2068 	uint32_t gdfll_as_step_ctrl_val;
2069 	uint32_t bootup_dtbclk_10khz;
2070 	uint32_t fclk_syspll_refclk_10khz;
2071 	uint32_t smusvi_svc0_val;
2072 	uint32_t smusvi_svc1_val;
2073 	uint32_t smusvi_svd0_val;
2074 	uint32_t smusvi_svd1_val;
2075 	uint32_t smusvi_svt0_val;
2076 	uint32_t smusvi_svt1_val;
2077 	uint32_t cg_tach_ctrl_val;
2078 	uint32_t cg_pump_ctrl1_val;
2079 	uint32_t cg_pump_tach_ctrl_val;
2080 	uint32_t thm_ctf_delay_val;
2081 	uint32_t thm_thermal_int_ctrl_val;
2082 	uint32_t thm_tmon_config_val;
2083 	uint32_t smbus_timing_cntrl0_val;
2084 	uint32_t smbus_timing_cntrl1_val;
2085 	uint32_t smbus_timing_cntrl2_val;
2086 	uint32_t pwr_disp_timer_global_control_val;
2087 	uint32_t bootup_mpioclk_10khz;
2088 	uint32_t bootup_dclk0_10khz;
2089 	uint32_t bootup_vclk0_10khz;
2090 	uint32_t bootup_dclk1_10khz;
2091 	uint32_t bootup_vclk1_10khz;
2092 	uint32_t bootup_baco400clk_10khz;
2093 	uint32_t bootup_baco1200clk_bypass_10khz;
2094 	uint32_t bootup_baco700clk_bypass_10khz;
2095 	uint32_t reserved[16];
2096 };
2097 
2098 /*
2099  ***************************************************************************
2100    Data Table smc_dpm_info  structure
2101  ***************************************************************************
2102  */
2103 struct atom_smc_dpm_info_v4_1
2104 {
2105   struct   atom_common_table_header  table_header;
2106   uint8_t  liquid1_i2c_address;
2107   uint8_t  liquid2_i2c_address;
2108   uint8_t  vr_i2c_address;
2109   uint8_t  plx_i2c_address;
2110 
2111   uint8_t  liquid_i2c_linescl;
2112   uint8_t  liquid_i2c_linesda;
2113   uint8_t  vr_i2c_linescl;
2114   uint8_t  vr_i2c_linesda;
2115 
2116   uint8_t  plx_i2c_linescl;
2117   uint8_t  plx_i2c_linesda;
2118   uint8_t  vrsensorpresent;
2119   uint8_t  liquidsensorpresent;
2120 
2121   uint16_t maxvoltagestepgfx;
2122   uint16_t maxvoltagestepsoc;
2123 
2124   uint8_t  vddgfxvrmapping;
2125   uint8_t  vddsocvrmapping;
2126   uint8_t  vddmem0vrmapping;
2127   uint8_t  vddmem1vrmapping;
2128 
2129   uint8_t  gfxulvphasesheddingmask;
2130   uint8_t  soculvphasesheddingmask;
2131   uint8_t  padding8_v[2];
2132 
2133   uint16_t gfxmaxcurrent;
2134   uint8_t  gfxoffset;
2135   uint8_t  padding_telemetrygfx;
2136 
2137   uint16_t socmaxcurrent;
2138   uint8_t  socoffset;
2139   uint8_t  padding_telemetrysoc;
2140 
2141   uint16_t mem0maxcurrent;
2142   uint8_t  mem0offset;
2143   uint8_t  padding_telemetrymem0;
2144 
2145   uint16_t mem1maxcurrent;
2146   uint8_t  mem1offset;
2147   uint8_t  padding_telemetrymem1;
2148 
2149   uint8_t  acdcgpio;
2150   uint8_t  acdcpolarity;
2151   uint8_t  vr0hotgpio;
2152   uint8_t  vr0hotpolarity;
2153 
2154   uint8_t  vr1hotgpio;
2155   uint8_t  vr1hotpolarity;
2156   uint8_t  padding1;
2157   uint8_t  padding2;
2158 
2159   uint8_t  ledpin0;
2160   uint8_t  ledpin1;
2161   uint8_t  ledpin2;
2162   uint8_t  padding8_4;
2163 
2164 	uint8_t  pllgfxclkspreadenabled;
2165 	uint8_t  pllgfxclkspreadpercent;
2166 	uint16_t pllgfxclkspreadfreq;
2167 
2168   uint8_t uclkspreadenabled;
2169   uint8_t uclkspreadpercent;
2170   uint16_t uclkspreadfreq;
2171 
2172   uint8_t socclkspreadenabled;
2173   uint8_t socclkspreadpercent;
2174   uint16_t socclkspreadfreq;
2175 
2176 	uint8_t  acggfxclkspreadenabled;
2177 	uint8_t  acggfxclkspreadpercent;
2178 	uint16_t acggfxclkspreadfreq;
2179 
2180 	uint8_t Vr2_I2C_address;
2181 	uint8_t padding_vr2[3];
2182 
2183 	uint32_t boardreserved[9];
2184 };
2185 
2186 /*
2187  ***************************************************************************
2188    Data Table smc_dpm_info  structure
2189  ***************************************************************************
2190  */
2191 struct atom_smc_dpm_info_v4_3
2192 {
2193   struct   atom_common_table_header  table_header;
2194   uint8_t  liquid1_i2c_address;
2195   uint8_t  liquid2_i2c_address;
2196   uint8_t  vr_i2c_address;
2197   uint8_t  plx_i2c_address;
2198 
2199   uint8_t  liquid_i2c_linescl;
2200   uint8_t  liquid_i2c_linesda;
2201   uint8_t  vr_i2c_linescl;
2202   uint8_t  vr_i2c_linesda;
2203 
2204   uint8_t  plx_i2c_linescl;
2205   uint8_t  plx_i2c_linesda;
2206   uint8_t  vrsensorpresent;
2207   uint8_t  liquidsensorpresent;
2208 
2209   uint16_t maxvoltagestepgfx;
2210   uint16_t maxvoltagestepsoc;
2211 
2212   uint8_t  vddgfxvrmapping;
2213   uint8_t  vddsocvrmapping;
2214   uint8_t  vddmem0vrmapping;
2215   uint8_t  vddmem1vrmapping;
2216 
2217   uint8_t  gfxulvphasesheddingmask;
2218   uint8_t  soculvphasesheddingmask;
2219   uint8_t  externalsensorpresent;
2220   uint8_t  padding8_v;
2221 
2222   uint16_t gfxmaxcurrent;
2223   uint8_t  gfxoffset;
2224   uint8_t  padding_telemetrygfx;
2225 
2226   uint16_t socmaxcurrent;
2227   uint8_t  socoffset;
2228   uint8_t  padding_telemetrysoc;
2229 
2230   uint16_t mem0maxcurrent;
2231   uint8_t  mem0offset;
2232   uint8_t  padding_telemetrymem0;
2233 
2234   uint16_t mem1maxcurrent;
2235   uint8_t  mem1offset;
2236   uint8_t  padding_telemetrymem1;
2237 
2238   uint8_t  acdcgpio;
2239   uint8_t  acdcpolarity;
2240   uint8_t  vr0hotgpio;
2241   uint8_t  vr0hotpolarity;
2242 
2243   uint8_t  vr1hotgpio;
2244   uint8_t  vr1hotpolarity;
2245   uint8_t  padding1;
2246   uint8_t  padding2;
2247 
2248   uint8_t  ledpin0;
2249   uint8_t  ledpin1;
2250   uint8_t  ledpin2;
2251   uint8_t  padding8_4;
2252 
2253   uint8_t  pllgfxclkspreadenabled;
2254   uint8_t  pllgfxclkspreadpercent;
2255   uint16_t pllgfxclkspreadfreq;
2256 
2257   uint8_t uclkspreadenabled;
2258   uint8_t uclkspreadpercent;
2259   uint16_t uclkspreadfreq;
2260 
2261   uint8_t fclkspreadenabled;
2262   uint8_t fclkspreadpercent;
2263   uint16_t fclkspreadfreq;
2264 
2265   uint8_t fllgfxclkspreadenabled;
2266   uint8_t fllgfxclkspreadpercent;
2267   uint16_t fllgfxclkspreadfreq;
2268 
2269   uint32_t boardreserved[10];
2270 };
2271 
2272 struct smudpm_i2ccontrollerconfig_t {
2273   uint32_t  enabled;
2274   uint32_t  slaveaddress;
2275   uint32_t  controllerport;
2276   uint32_t  controllername;
2277   uint32_t  thermalthrottler;
2278   uint32_t  i2cprotocol;
2279   uint32_t  i2cspeed;
2280 };
2281 
2282 struct atom_smc_dpm_info_v4_4
2283 {
2284   struct   atom_common_table_header  table_header;
2285   uint32_t  i2c_padding[3];
2286 
2287   uint16_t maxvoltagestepgfx;
2288   uint16_t maxvoltagestepsoc;
2289 
2290   uint8_t  vddgfxvrmapping;
2291   uint8_t  vddsocvrmapping;
2292   uint8_t  vddmem0vrmapping;
2293   uint8_t  vddmem1vrmapping;
2294 
2295   uint8_t  gfxulvphasesheddingmask;
2296   uint8_t  soculvphasesheddingmask;
2297   uint8_t  externalsensorpresent;
2298   uint8_t  padding8_v;
2299 
2300   uint16_t gfxmaxcurrent;
2301   uint8_t  gfxoffset;
2302   uint8_t  padding_telemetrygfx;
2303 
2304   uint16_t socmaxcurrent;
2305   uint8_t  socoffset;
2306   uint8_t  padding_telemetrysoc;
2307 
2308   uint16_t mem0maxcurrent;
2309   uint8_t  mem0offset;
2310   uint8_t  padding_telemetrymem0;
2311 
2312   uint16_t mem1maxcurrent;
2313   uint8_t  mem1offset;
2314   uint8_t  padding_telemetrymem1;
2315 
2316 
2317   uint8_t  acdcgpio;
2318   uint8_t  acdcpolarity;
2319   uint8_t  vr0hotgpio;
2320   uint8_t  vr0hotpolarity;
2321 
2322   uint8_t  vr1hotgpio;
2323   uint8_t  vr1hotpolarity;
2324   uint8_t  padding1;
2325   uint8_t  padding2;
2326 
2327 
2328   uint8_t  ledpin0;
2329   uint8_t  ledpin1;
2330   uint8_t  ledpin2;
2331   uint8_t  padding8_4;
2332 
2333 
2334   uint8_t  pllgfxclkspreadenabled;
2335   uint8_t  pllgfxclkspreadpercent;
2336   uint16_t pllgfxclkspreadfreq;
2337 
2338 
2339   uint8_t  uclkspreadenabled;
2340   uint8_t  uclkspreadpercent;
2341   uint16_t uclkspreadfreq;
2342 
2343 
2344   uint8_t  fclkspreadenabled;
2345   uint8_t  fclkspreadpercent;
2346   uint16_t fclkspreadfreq;
2347 
2348 
2349   uint8_t  fllgfxclkspreadenabled;
2350   uint8_t  fllgfxclkspreadpercent;
2351   uint16_t fllgfxclkspreadfreq;
2352 
2353 
2354   struct smudpm_i2ccontrollerconfig_t  i2ccontrollers[7];
2355 
2356 
2357   uint32_t boardreserved[10];
2358 };
2359 
2360 enum smudpm_v4_5_i2ccontrollername_e{
2361     SMC_V4_5_I2C_CONTROLLER_NAME_VR_GFX = 0,
2362     SMC_V4_5_I2C_CONTROLLER_NAME_VR_SOC,
2363     SMC_V4_5_I2C_CONTROLLER_NAME_VR_VDDCI,
2364     SMC_V4_5_I2C_CONTROLLER_NAME_VR_MVDD,
2365     SMC_V4_5_I2C_CONTROLLER_NAME_LIQUID0,
2366     SMC_V4_5_I2C_CONTROLLER_NAME_LIQUID1,
2367     SMC_V4_5_I2C_CONTROLLER_NAME_PLX,
2368     SMC_V4_5_I2C_CONTROLLER_NAME_SPARE,
2369     SMC_V4_5_I2C_CONTROLLER_NAME_COUNT,
2370 };
2371 
2372 enum smudpm_v4_5_i2ccontrollerthrottler_e{
2373     SMC_V4_5_I2C_CONTROLLER_THROTTLER_TYPE_NONE = 0,
2374     SMC_V4_5_I2C_CONTROLLER_THROTTLER_VR_GFX,
2375     SMC_V4_5_I2C_CONTROLLER_THROTTLER_VR_SOC,
2376     SMC_V4_5_I2C_CONTROLLER_THROTTLER_VR_VDDCI,
2377     SMC_V4_5_I2C_CONTROLLER_THROTTLER_VR_MVDD,
2378     SMC_V4_5_I2C_CONTROLLER_THROTTLER_LIQUID0,
2379     SMC_V4_5_I2C_CONTROLLER_THROTTLER_LIQUID1,
2380     SMC_V4_5_I2C_CONTROLLER_THROTTLER_PLX,
2381     SMC_V4_5_I2C_CONTROLLER_THROTTLER_COUNT,
2382 };
2383 
2384 enum smudpm_v4_5_i2ccontrollerprotocol_e{
2385     SMC_V4_5_I2C_CONTROLLER_PROTOCOL_VR_0,
2386     SMC_V4_5_I2C_CONTROLLER_PROTOCOL_VR_1,
2387     SMC_V4_5_I2C_CONTROLLER_PROTOCOL_TMP_0,
2388     SMC_V4_5_I2C_CONTROLLER_PROTOCOL_TMP_1,
2389     SMC_V4_5_I2C_CONTROLLER_PROTOCOL_SPARE_0,
2390     SMC_V4_5_I2C_CONTROLLER_PROTOCOL_SPARE_1,
2391     SMC_V4_5_I2C_CONTROLLER_PROTOCOL_COUNT,
2392 };
2393 
2394 struct smudpm_i2c_controller_config_v2
2395 {
2396     uint8_t   Enabled;
2397     uint8_t   Speed;
2398     uint8_t   Padding[2];
2399     uint32_t  SlaveAddress;
2400     uint8_t   ControllerPort;
2401     uint8_t   ControllerName;
2402     uint8_t   ThermalThrotter;
2403     uint8_t   I2cProtocol;
2404 };
2405 
2406 struct atom_smc_dpm_info_v4_5
2407 {
2408   struct   atom_common_table_header  table_header;
2409     // SECTION: BOARD PARAMETERS
2410     // I2C Control
2411   struct smudpm_i2c_controller_config_v2  I2cControllers[8];
2412 
2413   // SVI2 Board Parameters
2414   uint16_t     MaxVoltageStepGfx; // In mV(Q2) Max voltage step that SMU will request. Multiple steps are taken if voltage change exceeds this value.
2415   uint16_t     MaxVoltageStepSoc; // In mV(Q2) Max voltage step that SMU will request. Multiple steps are taken if voltage change exceeds this value.
2416 
2417   uint8_t      VddGfxVrMapping;   // Use VR_MAPPING* bitfields
2418   uint8_t      VddSocVrMapping;   // Use VR_MAPPING* bitfields
2419   uint8_t      VddMem0VrMapping;  // Use VR_MAPPING* bitfields
2420   uint8_t      VddMem1VrMapping;  // Use VR_MAPPING* bitfields
2421 
2422   uint8_t      GfxUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode
2423   uint8_t      SocUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode
2424   uint8_t      ExternalSensorPresent; // External RDI connected to TMON (aka TEMP IN)
2425   uint8_t      Padding8_V;
2426 
2427   // Telemetry Settings
2428   uint16_t     GfxMaxCurrent;   // in Amps
2429   uint8_t      GfxOffset;       // in Amps
2430   uint8_t      Padding_TelemetryGfx;
2431   uint16_t     SocMaxCurrent;   // in Amps
2432   uint8_t      SocOffset;       // in Amps
2433   uint8_t      Padding_TelemetrySoc;
2434 
2435   uint16_t     Mem0MaxCurrent;   // in Amps
2436   uint8_t      Mem0Offset;       // in Amps
2437   uint8_t      Padding_TelemetryMem0;
2438 
2439   uint16_t     Mem1MaxCurrent;   // in Amps
2440   uint8_t      Mem1Offset;       // in Amps
2441   uint8_t      Padding_TelemetryMem1;
2442 
2443   // GPIO Settings
2444   uint8_t      AcDcGpio;        // GPIO pin configured for AC/DC switching
2445   uint8_t      AcDcPolarity;    // GPIO polarity for AC/DC switching
2446   uint8_t      VR0HotGpio;      // GPIO pin configured for VR0 HOT event
2447   uint8_t      VR0HotPolarity;  // GPIO polarity for VR0 HOT event
2448 
2449   uint8_t      VR1HotGpio;      // GPIO pin configured for VR1 HOT event
2450   uint8_t      VR1HotPolarity;  // GPIO polarity for VR1 HOT event
2451   uint8_t      GthrGpio;        // GPIO pin configured for GTHR Event
2452   uint8_t      GthrPolarity;    // replace GPIO polarity for GTHR
2453 
2454   // LED Display Settings
2455   uint8_t      LedPin0;         // GPIO number for LedPin[0]
2456   uint8_t      LedPin1;         // GPIO number for LedPin[1]
2457   uint8_t      LedPin2;         // GPIO number for LedPin[2]
2458   uint8_t      padding8_4;
2459 
2460   // GFXCLK PLL Spread Spectrum
2461   uint8_t      PllGfxclkSpreadEnabled;   // on or off
2462   uint8_t      PllGfxclkSpreadPercent;   // Q4.4
2463   uint16_t     PllGfxclkSpreadFreq;      // kHz
2464 
2465   // GFXCLK DFLL Spread Spectrum
2466   uint8_t      DfllGfxclkSpreadEnabled;   // on or off
2467   uint8_t      DfllGfxclkSpreadPercent;   // Q4.4
2468   uint16_t     DfllGfxclkSpreadFreq;      // kHz
2469 
2470   // UCLK Spread Spectrum
2471   uint8_t      UclkSpreadEnabled;   // on or off
2472   uint8_t      UclkSpreadPercent;   // Q4.4
2473   uint16_t     UclkSpreadFreq;      // kHz
2474 
2475   // SOCCLK Spread Spectrum
2476   uint8_t      SoclkSpreadEnabled;   // on or off
2477   uint8_t      SocclkSpreadPercent;   // Q4.4
2478   uint16_t     SocclkSpreadFreq;      // kHz
2479 
2480   // Total board power
2481   uint16_t     TotalBoardPower;     //Only needed for TCP Estimated case, where TCP = TGP+Total Board Power
2482   uint16_t     BoardPadding;
2483 
2484   // Mvdd Svi2 Div Ratio Setting
2485   uint32_t MvddRatio; // This is used for MVDD Vid workaround. It has 16 fractional bits (Q16.16)
2486 
2487   uint32_t     BoardReserved[9];
2488 
2489 };
2490 
2491 struct atom_smc_dpm_info_v4_6
2492 {
2493   struct   atom_common_table_header  table_header;
2494   // section: board parameters
2495   uint32_t     i2c_padding[3];   // old i2c control are moved to new area
2496 
2497   uint16_t     maxvoltagestepgfx; // in mv(q2) max voltage step that smu will request. multiple steps are taken if voltage change exceeds this value.
2498   uint16_t     maxvoltagestepsoc; // in mv(q2) max voltage step that smu will request. multiple steps are taken if voltage change exceeds this value.
2499 
2500   uint8_t      vddgfxvrmapping;     // use vr_mapping* bitfields
2501   uint8_t      vddsocvrmapping;     // use vr_mapping* bitfields
2502   uint8_t      vddmemvrmapping;     // use vr_mapping* bitfields
2503   uint8_t      boardvrmapping;      // use vr_mapping* bitfields
2504 
2505   uint8_t      gfxulvphasesheddingmask; // set this to 1 to set psi0/1 to 1 in ulv mode
2506   uint8_t      externalsensorpresent; // external rdi connected to tmon (aka temp in)
2507   uint8_t      padding8_v[2];
2508 
2509   // telemetry settings
2510   uint16_t     gfxmaxcurrent;   // in amps
2511   uint8_t      gfxoffset;       // in amps
2512   uint8_t      padding_telemetrygfx;
2513 
2514   uint16_t     socmaxcurrent;   // in amps
2515   uint8_t      socoffset;       // in amps
2516   uint8_t      padding_telemetrysoc;
2517 
2518   uint16_t     memmaxcurrent;   // in amps
2519   uint8_t      memoffset;       // in amps
2520   uint8_t      padding_telemetrymem;
2521 
2522   uint16_t     boardmaxcurrent;   // in amps
2523   uint8_t      boardoffset;       // in amps
2524   uint8_t      padding_telemetryboardinput;
2525 
2526   // gpio settings
2527   uint8_t      vr0hotgpio;      // gpio pin configured for vr0 hot event
2528   uint8_t      vr0hotpolarity;  // gpio polarity for vr0 hot event
2529   uint8_t      vr1hotgpio;      // gpio pin configured for vr1 hot event
2530   uint8_t      vr1hotpolarity;  // gpio polarity for vr1 hot event
2531 
2532  // gfxclk pll spread spectrum
2533   uint8_t	   pllgfxclkspreadenabled;	// on or off
2534   uint8_t	   pllgfxclkspreadpercent;	// q4.4
2535   uint16_t	   pllgfxclkspreadfreq;		// khz
2536 
2537  // uclk spread spectrum
2538   uint8_t	   uclkspreadenabled;   // on or off
2539   uint8_t	   uclkspreadpercent;   // q4.4
2540   uint16_t	   uclkspreadfreq;	   // khz
2541 
2542  // fclk spread spectrum
2543   uint8_t	   fclkspreadenabled;   // on or off
2544   uint8_t	   fclkspreadpercent;   // q4.4
2545   uint16_t	   fclkspreadfreq;	   // khz
2546 
2547 
2548   // gfxclk fll spread spectrum
2549   uint8_t      fllgfxclkspreadenabled;   // on or off
2550   uint8_t      fllgfxclkspreadpercent;   // q4.4
2551   uint16_t     fllgfxclkspreadfreq;      // khz
2552 
2553   // i2c controller structure
2554   struct smudpm_i2c_controller_config_v2 i2ccontrollers[8];
2555 
2556   // memory section
2557   uint32_t	 memorychannelenabled; // for dram use only, max 32 channels enabled bit mask.
2558 
2559   uint8_t 	 drambitwidth; // for dram use only.  see dram bit width type defines
2560   uint8_t 	 paddingmem[3];
2561 
2562 	// total board power
2563   uint16_t	 totalboardpower;	  //only needed for tcp estimated case, where tcp = tgp+total board power
2564   uint16_t	 boardpadding;
2565 
2566 	// section: xgmi training
2567   uint8_t 	 xgmilinkspeed[4];
2568   uint8_t 	 xgmilinkwidth[4];
2569 
2570   uint16_t	 xgmifclkfreq[4];
2571   uint16_t	 xgmisocvoltage[4];
2572 
2573   // reserved
2574   uint32_t   boardreserved[10];
2575 };
2576 
2577 struct atom_smc_dpm_info_v4_7
2578 {
2579   struct   atom_common_table_header  table_header;
2580     // SECTION: BOARD PARAMETERS
2581     // I2C Control
2582   struct smudpm_i2c_controller_config_v2  I2cControllers[8];
2583 
2584   // SVI2 Board Parameters
2585   uint16_t     MaxVoltageStepGfx; // In mV(Q2) Max voltage step that SMU will request. Multiple steps are taken if voltage change exceeds this value.
2586   uint16_t     MaxVoltageStepSoc; // In mV(Q2) Max voltage step that SMU will request. Multiple steps are taken if voltage change exceeds this value.
2587 
2588   uint8_t      VddGfxVrMapping;   // Use VR_MAPPING* bitfields
2589   uint8_t      VddSocVrMapping;   // Use VR_MAPPING* bitfields
2590   uint8_t      VddMem0VrMapping;  // Use VR_MAPPING* bitfields
2591   uint8_t      VddMem1VrMapping;  // Use VR_MAPPING* bitfields
2592 
2593   uint8_t      GfxUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode
2594   uint8_t      SocUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode
2595   uint8_t      ExternalSensorPresent; // External RDI connected to TMON (aka TEMP IN)
2596   uint8_t      Padding8_V;
2597 
2598   // Telemetry Settings
2599   uint16_t     GfxMaxCurrent;   // in Amps
2600   uint8_t      GfxOffset;       // in Amps
2601   uint8_t      Padding_TelemetryGfx;
2602   uint16_t     SocMaxCurrent;   // in Amps
2603   uint8_t      SocOffset;       // in Amps
2604   uint8_t      Padding_TelemetrySoc;
2605 
2606   uint16_t     Mem0MaxCurrent;   // in Amps
2607   uint8_t      Mem0Offset;       // in Amps
2608   uint8_t      Padding_TelemetryMem0;
2609 
2610   uint16_t     Mem1MaxCurrent;   // in Amps
2611   uint8_t      Mem1Offset;       // in Amps
2612   uint8_t      Padding_TelemetryMem1;
2613 
2614   // GPIO Settings
2615   uint8_t      AcDcGpio;        // GPIO pin configured for AC/DC switching
2616   uint8_t      AcDcPolarity;    // GPIO polarity for AC/DC switching
2617   uint8_t      VR0HotGpio;      // GPIO pin configured for VR0 HOT event
2618   uint8_t      VR0HotPolarity;  // GPIO polarity for VR0 HOT event
2619 
2620   uint8_t      VR1HotGpio;      // GPIO pin configured for VR1 HOT event
2621   uint8_t      VR1HotPolarity;  // GPIO polarity for VR1 HOT event
2622   uint8_t      GthrGpio;        // GPIO pin configured for GTHR Event
2623   uint8_t      GthrPolarity;    // replace GPIO polarity for GTHR
2624 
2625   // LED Display Settings
2626   uint8_t      LedPin0;         // GPIO number for LedPin[0]
2627   uint8_t      LedPin1;         // GPIO number for LedPin[1]
2628   uint8_t      LedPin2;         // GPIO number for LedPin[2]
2629   uint8_t      padding8_4;
2630 
2631   // GFXCLK PLL Spread Spectrum
2632   uint8_t      PllGfxclkSpreadEnabled;   // on or off
2633   uint8_t      PllGfxclkSpreadPercent;   // Q4.4
2634   uint16_t     PllGfxclkSpreadFreq;      // kHz
2635 
2636   // GFXCLK DFLL Spread Spectrum
2637   uint8_t      DfllGfxclkSpreadEnabled;   // on or off
2638   uint8_t      DfllGfxclkSpreadPercent;   // Q4.4
2639   uint16_t     DfllGfxclkSpreadFreq;      // kHz
2640 
2641   // UCLK Spread Spectrum
2642   uint8_t      UclkSpreadEnabled;   // on or off
2643   uint8_t      UclkSpreadPercent;   // Q4.4
2644   uint16_t     UclkSpreadFreq;      // kHz
2645 
2646   // SOCCLK Spread Spectrum
2647   uint8_t      SoclkSpreadEnabled;   // on or off
2648   uint8_t      SocclkSpreadPercent;   // Q4.4
2649   uint16_t     SocclkSpreadFreq;      // kHz
2650 
2651   // Total board power
2652   uint16_t     TotalBoardPower;     //Only needed for TCP Estimated case, where TCP = TGP+Total Board Power
2653   uint16_t     BoardPadding;
2654 
2655   // Mvdd Svi2 Div Ratio Setting
2656   uint32_t     MvddRatio; // This is used for MVDD Vid workaround. It has 16 fractional bits (Q16.16)
2657 
2658   // GPIO pins for I2C communications with 2nd controller for Input Telemetry Sequence
2659   uint8_t      GpioI2cScl;          // Serial Clock
2660   uint8_t      GpioI2cSda;          // Serial Data
2661   uint16_t     GpioPadding;
2662 
2663   // Additional LED Display Settings
2664   uint8_t      LedPin3;         // GPIO number for LedPin[3] - PCIE GEN Speed
2665   uint8_t      LedPin4;         // GPIO number for LedPin[4] - PMFW Error Status
2666   uint16_t     LedEnableMask;
2667 
2668   // Power Limit Scalars
2669   uint8_t      PowerLimitScalar[4];    //[PPT_THROTTLER_COUNT]
2670 
2671   uint8_t      MvddUlvPhaseSheddingMask;
2672   uint8_t      VddciUlvPhaseSheddingMask;
2673   uint8_t      Padding8_Psi1;
2674   uint8_t      Padding8_Psi2;
2675 
2676   uint32_t     BoardReserved[5];
2677 };
2678 
2679 struct smudpm_i2c_controller_config_v3
2680 {
2681   uint8_t   Enabled;
2682   uint8_t   Speed;
2683   uint8_t   SlaveAddress;
2684   uint8_t   ControllerPort;
2685   uint8_t   ControllerName;
2686   uint8_t   ThermalThrotter;
2687   uint8_t   I2cProtocol;
2688   uint8_t   PaddingConfig;
2689 };
2690 
2691 struct atom_smc_dpm_info_v4_9
2692 {
2693   struct   atom_common_table_header  table_header;
2694 
2695   //SECTION: Gaming Clocks
2696   //uint32_t     GamingClk[6];
2697 
2698   // SECTION: I2C Control
2699   struct smudpm_i2c_controller_config_v3  I2cControllers[16];
2700 
2701   uint8_t      GpioScl;  // GPIO Number for SCL Line, used only for CKSVII2C1
2702   uint8_t      GpioSda;  // GPIO Number for SDA Line, used only for CKSVII2C1
2703   uint8_t      FchUsbPdSlaveAddr; //For requesting USB PD controller S-states via FCH I2C when entering PME turn off
2704   uint8_t      I2cSpare;
2705 
2706   // SECTION: SVI2 Board Parameters
2707   uint8_t      VddGfxVrMapping;   // Use VR_MAPPING* bitfields
2708   uint8_t      VddSocVrMapping;   // Use VR_MAPPING* bitfields
2709   uint8_t      VddMem0VrMapping;  // Use VR_MAPPING* bitfields
2710   uint8_t      VddMem1VrMapping;  // Use VR_MAPPING* bitfields
2711 
2712   uint8_t      GfxUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode
2713   uint8_t      SocUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode
2714   uint8_t      VddciUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode
2715   uint8_t      MvddUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode
2716 
2717   // SECTION: Telemetry Settings
2718   uint16_t     GfxMaxCurrent;   // in Amps
2719   uint8_t      GfxOffset;       // in Amps
2720   uint8_t      Padding_TelemetryGfx;
2721 
2722   uint16_t     SocMaxCurrent;   // in Amps
2723   uint8_t      SocOffset;       // in Amps
2724   uint8_t      Padding_TelemetrySoc;
2725 
2726   uint16_t     Mem0MaxCurrent;   // in Amps
2727   uint8_t      Mem0Offset;       // in Amps
2728   uint8_t      Padding_TelemetryMem0;
2729 
2730   uint16_t     Mem1MaxCurrent;   // in Amps
2731   uint8_t      Mem1Offset;       // in Amps
2732   uint8_t      Padding_TelemetryMem1;
2733 
2734   uint32_t     MvddRatio; // This is used for MVDD  Svi2 Div Ratio workaround. It has 16 fractional bits (Q16.16)
2735 
2736   // SECTION: GPIO Settings
2737   uint8_t      AcDcGpio;        // GPIO pin configured for AC/DC switching
2738   uint8_t      AcDcPolarity;    // GPIO polarity for AC/DC switching
2739   uint8_t      VR0HotGpio;      // GPIO pin configured for VR0 HOT event
2740   uint8_t      VR0HotPolarity;  // GPIO polarity for VR0 HOT event
2741 
2742   uint8_t      VR1HotGpio;      // GPIO pin configured for VR1 HOT event
2743   uint8_t      VR1HotPolarity;  // GPIO polarity for VR1 HOT event
2744   uint8_t      GthrGpio;        // GPIO pin configured for GTHR Event
2745   uint8_t      GthrPolarity;    // replace GPIO polarity for GTHR
2746 
2747   // LED Display Settings
2748   uint8_t      LedPin0;         // GPIO number for LedPin[0]
2749   uint8_t      LedPin1;         // GPIO number for LedPin[1]
2750   uint8_t      LedPin2;         // GPIO number for LedPin[2]
2751   uint8_t      LedEnableMask;
2752 
2753   uint8_t      LedPcie;        // GPIO number for PCIE results
2754   uint8_t      LedError;       // GPIO number for Error Cases
2755   uint8_t      LedSpare1[2];
2756 
2757   // SECTION: Clock Spread Spectrum
2758 
2759   // GFXCLK PLL Spread Spectrum
2760   uint8_t      PllGfxclkSpreadEnabled;   // on or off
2761   uint8_t      PllGfxclkSpreadPercent;   // Q4.4
2762   uint16_t     PllGfxclkSpreadFreq;      // kHz
2763 
2764   // GFXCLK DFLL Spread Spectrum
2765   uint8_t      DfllGfxclkSpreadEnabled;   // on or off
2766   uint8_t      DfllGfxclkSpreadPercent;   // Q4.4
2767   uint16_t     DfllGfxclkSpreadFreq;      // kHz
2768 
2769   // UCLK Spread Spectrum
2770   uint8_t      UclkSpreadEnabled;   // on or off
2771   uint8_t      UclkSpreadPercent;   // Q4.4
2772   uint16_t     UclkSpreadFreq;      // kHz
2773 
2774   // FCLK Spread Spectrum
2775   uint8_t      FclkSpreadEnabled;   // on or off
2776   uint8_t      FclkSpreadPercent;   // Q4.4
2777   uint16_t     FclkSpreadFreq;      // kHz
2778 
2779   // Section: Memory Config
2780   uint32_t     MemoryChannelEnabled; // For DRAM use only, Max 32 channels enabled bit mask.
2781 
2782   uint8_t      DramBitWidth; // For DRAM use only.  See Dram Bit width type defines
2783   uint8_t      PaddingMem1[3];
2784 
2785   // Section: Total Board Power
2786   uint16_t     TotalBoardPower;     //Only needed for TCP Estimated case, where TCP = TGP+Total Board Power
2787   uint16_t     BoardPowerPadding;
2788 
2789   // SECTION: XGMI Training
2790   uint8_t      XgmiLinkSpeed   [4];
2791   uint8_t      XgmiLinkWidth   [4];
2792 
2793   uint16_t     XgmiFclkFreq    [4];
2794   uint16_t     XgmiSocVoltage  [4];
2795 
2796   // SECTION: Board Reserved
2797 
2798   uint32_t     BoardReserved[16];
2799 
2800 };
2801 
2802 struct atom_smc_dpm_info_v4_10
2803 {
2804   struct   atom_common_table_header  table_header;
2805 
2806   // SECTION: BOARD PARAMETERS
2807   // Telemetry Settings
2808   uint16_t GfxMaxCurrent; // in Amps
2809   uint8_t   GfxOffset;     // in Amps
2810   uint8_t  Padding_TelemetryGfx;
2811 
2812   uint16_t SocMaxCurrent; // in Amps
2813   uint8_t   SocOffset;     // in Amps
2814   uint8_t  Padding_TelemetrySoc;
2815 
2816   uint16_t MemMaxCurrent; // in Amps
2817   uint8_t   MemOffset;     // in Amps
2818   uint8_t  Padding_TelemetryMem;
2819 
2820   uint16_t BoardMaxCurrent; // in Amps
2821   uint8_t   BoardOffset;     // in Amps
2822   uint8_t  Padding_TelemetryBoardInput;
2823 
2824   // Platform input telemetry voltage coefficient
2825   uint32_t BoardVoltageCoeffA; // decode by /1000
2826   uint32_t BoardVoltageCoeffB; // decode by /1000
2827 
2828   // GPIO Settings
2829   uint8_t  VR0HotGpio;     // GPIO pin configured for VR0 HOT event
2830   uint8_t  VR0HotPolarity; // GPIO polarity for VR0 HOT event
2831   uint8_t  VR1HotGpio;     // GPIO pin configured for VR1 HOT event
2832   uint8_t  VR1HotPolarity; // GPIO polarity for VR1 HOT event
2833 
2834   // UCLK Spread Spectrum
2835   uint8_t  UclkSpreadEnabled; // on or off
2836   uint8_t  UclkSpreadPercent; // Q4.4
2837   uint16_t UclkSpreadFreq;    // kHz
2838 
2839   // FCLK Spread Spectrum
2840   uint8_t  FclkSpreadEnabled; // on or off
2841   uint8_t  FclkSpreadPercent; // Q4.4
2842   uint16_t FclkSpreadFreq;    // kHz
2843 
2844   // I2C Controller Structure
2845   struct smudpm_i2c_controller_config_v3  I2cControllers[8];
2846 
2847   // GPIO pins for I2C communications with 2nd controller for Input Telemetry Sequence
2848   uint8_t  GpioI2cScl; // Serial Clock
2849   uint8_t  GpioI2cSda; // Serial Data
2850   uint16_t spare5;
2851 
2852   uint32_t reserved[16];
2853 };
2854 
2855 /*
2856   ***************************************************************************
2857     Data Table asic_profiling_info  structure
2858   ***************************************************************************
2859 */
2860 struct  atom_asic_profiling_info_v4_1
2861 {
2862   struct  atom_common_table_header  table_header;
2863   uint32_t  maxvddc;
2864   uint32_t  minvddc;
2865   uint32_t  avfs_meannsigma_acontant0;
2866   uint32_t  avfs_meannsigma_acontant1;
2867   uint32_t  avfs_meannsigma_acontant2;
2868   uint16_t  avfs_meannsigma_dc_tol_sigma;
2869   uint16_t  avfs_meannsigma_platform_mean;
2870   uint16_t  avfs_meannsigma_platform_sigma;
2871   uint32_t  gb_vdroop_table_cksoff_a0;
2872   uint32_t  gb_vdroop_table_cksoff_a1;
2873   uint32_t  gb_vdroop_table_cksoff_a2;
2874   uint32_t  gb_vdroop_table_ckson_a0;
2875   uint32_t  gb_vdroop_table_ckson_a1;
2876   uint32_t  gb_vdroop_table_ckson_a2;
2877   uint32_t  avfsgb_fuse_table_cksoff_m1;
2878   uint32_t  avfsgb_fuse_table_cksoff_m2;
2879   uint32_t  avfsgb_fuse_table_cksoff_b;
2880   uint32_t  avfsgb_fuse_table_ckson_m1;
2881   uint32_t  avfsgb_fuse_table_ckson_m2;
2882   uint32_t  avfsgb_fuse_table_ckson_b;
2883   uint16_t  max_voltage_0_25mv;
2884   uint8_t   enable_gb_vdroop_table_cksoff;
2885   uint8_t   enable_gb_vdroop_table_ckson;
2886   uint8_t   enable_gb_fuse_table_cksoff;
2887   uint8_t   enable_gb_fuse_table_ckson;
2888   uint16_t  psm_age_comfactor;
2889   uint8_t   enable_apply_avfs_cksoff_voltage;
2890   uint8_t   reserved;
2891   uint32_t  dispclk2gfxclk_a;
2892   uint32_t  dispclk2gfxclk_b;
2893   uint32_t  dispclk2gfxclk_c;
2894   uint32_t  pixclk2gfxclk_a;
2895   uint32_t  pixclk2gfxclk_b;
2896   uint32_t  pixclk2gfxclk_c;
2897   uint32_t  dcefclk2gfxclk_a;
2898   uint32_t  dcefclk2gfxclk_b;
2899   uint32_t  dcefclk2gfxclk_c;
2900   uint32_t  phyclk2gfxclk_a;
2901   uint32_t  phyclk2gfxclk_b;
2902   uint32_t  phyclk2gfxclk_c;
2903 };
2904 
2905 struct  atom_asic_profiling_info_v4_2 {
2906 	struct  atom_common_table_header  table_header;
2907 	uint32_t  maxvddc;
2908 	uint32_t  minvddc;
2909 	uint32_t  avfs_meannsigma_acontant0;
2910 	uint32_t  avfs_meannsigma_acontant1;
2911 	uint32_t  avfs_meannsigma_acontant2;
2912 	uint16_t  avfs_meannsigma_dc_tol_sigma;
2913 	uint16_t  avfs_meannsigma_platform_mean;
2914 	uint16_t  avfs_meannsigma_platform_sigma;
2915 	uint32_t  gb_vdroop_table_cksoff_a0;
2916 	uint32_t  gb_vdroop_table_cksoff_a1;
2917 	uint32_t  gb_vdroop_table_cksoff_a2;
2918 	uint32_t  gb_vdroop_table_ckson_a0;
2919 	uint32_t  gb_vdroop_table_ckson_a1;
2920 	uint32_t  gb_vdroop_table_ckson_a2;
2921 	uint32_t  avfsgb_fuse_table_cksoff_m1;
2922 	uint32_t  avfsgb_fuse_table_cksoff_m2;
2923 	uint32_t  avfsgb_fuse_table_cksoff_b;
2924 	uint32_t  avfsgb_fuse_table_ckson_m1;
2925 	uint32_t  avfsgb_fuse_table_ckson_m2;
2926 	uint32_t  avfsgb_fuse_table_ckson_b;
2927 	uint16_t  max_voltage_0_25mv;
2928 	uint8_t   enable_gb_vdroop_table_cksoff;
2929 	uint8_t   enable_gb_vdroop_table_ckson;
2930 	uint8_t   enable_gb_fuse_table_cksoff;
2931 	uint8_t   enable_gb_fuse_table_ckson;
2932 	uint16_t  psm_age_comfactor;
2933 	uint8_t   enable_apply_avfs_cksoff_voltage;
2934 	uint8_t   reserved;
2935 	uint32_t  dispclk2gfxclk_a;
2936 	uint32_t  dispclk2gfxclk_b;
2937 	uint32_t  dispclk2gfxclk_c;
2938 	uint32_t  pixclk2gfxclk_a;
2939 	uint32_t  pixclk2gfxclk_b;
2940 	uint32_t  pixclk2gfxclk_c;
2941 	uint32_t  dcefclk2gfxclk_a;
2942 	uint32_t  dcefclk2gfxclk_b;
2943 	uint32_t  dcefclk2gfxclk_c;
2944 	uint32_t  phyclk2gfxclk_a;
2945 	uint32_t  phyclk2gfxclk_b;
2946 	uint32_t  phyclk2gfxclk_c;
2947 	uint32_t  acg_gb_vdroop_table_a0;
2948 	uint32_t  acg_gb_vdroop_table_a1;
2949 	uint32_t  acg_gb_vdroop_table_a2;
2950 	uint32_t  acg_avfsgb_fuse_table_m1;
2951 	uint32_t  acg_avfsgb_fuse_table_m2;
2952 	uint32_t  acg_avfsgb_fuse_table_b;
2953 	uint8_t   enable_acg_gb_vdroop_table;
2954 	uint8_t   enable_acg_gb_fuse_table;
2955 	uint32_t  acg_dispclk2gfxclk_a;
2956 	uint32_t  acg_dispclk2gfxclk_b;
2957 	uint32_t  acg_dispclk2gfxclk_c;
2958 	uint32_t  acg_pixclk2gfxclk_a;
2959 	uint32_t  acg_pixclk2gfxclk_b;
2960 	uint32_t  acg_pixclk2gfxclk_c;
2961 	uint32_t  acg_dcefclk2gfxclk_a;
2962 	uint32_t  acg_dcefclk2gfxclk_b;
2963 	uint32_t  acg_dcefclk2gfxclk_c;
2964 	uint32_t  acg_phyclk2gfxclk_a;
2965 	uint32_t  acg_phyclk2gfxclk_b;
2966 	uint32_t  acg_phyclk2gfxclk_c;
2967 };
2968 
2969 /*
2970   ***************************************************************************
2971     Data Table multimedia_info  structure
2972   ***************************************************************************
2973 */
2974 struct atom_multimedia_info_v2_1
2975 {
2976   struct  atom_common_table_header  table_header;
2977   uint8_t uvdip_min_ver;
2978   uint8_t uvdip_max_ver;
2979   uint8_t vceip_min_ver;
2980   uint8_t vceip_max_ver;
2981   uint16_t uvd_enc_max_input_width_pixels;
2982   uint16_t uvd_enc_max_input_height_pixels;
2983   uint16_t vce_enc_max_input_width_pixels;
2984   uint16_t vce_enc_max_input_height_pixels;
2985   uint32_t uvd_enc_max_bandwidth;           // 16x16 pixels/sec, codec independent
2986   uint32_t vce_enc_max_bandwidth;           // 16x16 pixels/sec, codec independent
2987 };
2988 
2989 
2990 /*
2991   ***************************************************************************
2992     Data Table umc_info  structure
2993   ***************************************************************************
2994 */
2995 struct atom_umc_info_v3_1
2996 {
2997   struct  atom_common_table_header  table_header;
2998   uint32_t ucode_version;
2999   uint32_t ucode_rom_startaddr;
3000   uint32_t ucode_length;
3001   uint16_t umc_reg_init_offset;
3002   uint16_t customer_ucode_name_offset;
3003   uint16_t mclk_ss_percentage;
3004   uint16_t mclk_ss_rate_10hz;
3005   uint8_t umcip_min_ver;
3006   uint8_t umcip_max_ver;
3007   uint8_t vram_type;              //enum of atom_dgpu_vram_type
3008   uint8_t umc_config;
3009   uint32_t mem_refclk_10khz;
3010 };
3011 
3012 // umc_info.umc_config
3013 enum atom_umc_config_def {
3014   UMC_CONFIG__ENABLE_1KB_INTERLEAVE_MODE  =   0x00000001,
3015   UMC_CONFIG__DEFAULT_MEM_ECC_ENABLE      =   0x00000002,
3016   UMC_CONFIG__ENABLE_HBM_LANE_REPAIR      =   0x00000004,
3017   UMC_CONFIG__ENABLE_BANK_HARVESTING      =   0x00000008,
3018   UMC_CONFIG__ENABLE_PHY_REINIT           =   0x00000010,
3019   UMC_CONFIG__DISABLE_UCODE_CHKSTATUS     =   0x00000020,
3020 };
3021 
3022 struct atom_umc_info_v3_2
3023 {
3024   struct  atom_common_table_header  table_header;
3025   uint32_t ucode_version;
3026   uint32_t ucode_rom_startaddr;
3027   uint32_t ucode_length;
3028   uint16_t umc_reg_init_offset;
3029   uint16_t customer_ucode_name_offset;
3030   uint16_t mclk_ss_percentage;
3031   uint16_t mclk_ss_rate_10hz;
3032   uint8_t umcip_min_ver;
3033   uint8_t umcip_max_ver;
3034   uint8_t vram_type;              //enum of atom_dgpu_vram_type
3035   uint8_t umc_config;
3036   uint32_t mem_refclk_10khz;
3037   uint32_t pstate_uclk_10khz[4];
3038   uint16_t umcgoldenoffset;
3039   uint16_t densitygoldenoffset;
3040 };
3041 
3042 struct atom_umc_info_v3_3
3043 {
3044   struct  atom_common_table_header  table_header;
3045   uint32_t ucode_reserved;
3046   uint32_t ucode_rom_startaddr;
3047   uint32_t ucode_length;
3048   uint16_t umc_reg_init_offset;
3049   uint16_t customer_ucode_name_offset;
3050   uint16_t mclk_ss_percentage;
3051   uint16_t mclk_ss_rate_10hz;
3052   uint8_t umcip_min_ver;
3053   uint8_t umcip_max_ver;
3054   uint8_t vram_type;              //enum of atom_dgpu_vram_type
3055   uint8_t umc_config;
3056   uint32_t mem_refclk_10khz;
3057   uint32_t pstate_uclk_10khz[4];
3058   uint16_t umcgoldenoffset;
3059   uint16_t densitygoldenoffset;
3060   uint32_t umc_config1;
3061   uint32_t bist_data_startaddr;
3062   uint32_t reserved[2];
3063 };
3064 
3065 enum atom_umc_config1_def {
3066 	UMC_CONFIG1__ENABLE_PSTATE_PHASE_STORE_TRAIN = 0x00000001,
3067 	UMC_CONFIG1__ENABLE_AUTO_FRAMING = 0x00000002,
3068 	UMC_CONFIG1__ENABLE_RESTORE_BIST_DATA = 0x00000004,
3069 	UMC_CONFIG1__DISABLE_STROBE_MODE = 0x00000008,
3070 	UMC_CONFIG1__DEBUG_DATA_PARITY_EN = 0x00000010,
3071 	UMC_CONFIG1__ENABLE_ECC_CAPABLE = 0x00010000,
3072 };
3073 
3074 /*
3075   ***************************************************************************
3076     Data Table vram_info  structure
3077   ***************************************************************************
3078 */
3079 struct atom_vram_module_v9 {
3080   // Design Specific Values
3081   uint32_t  memory_size;                   // Total memory size in unit of MB for CONFIG_MEMSIZE zeros
3082   uint32_t  channel_enable;                // bit vector, each bit indicate specific channel enable or not
3083   uint32_t  max_mem_clk;                   // max memory clock of this memory in unit of 10kHz, =0 means it is not defined
3084   uint16_t  reserved[3];
3085   uint16_t  mem_voltage;                   // mem_voltage
3086   uint16_t  vram_module_size;              // Size of atom_vram_module_v9
3087   uint8_t   ext_memory_id;                 // Current memory module ID
3088   uint8_t   memory_type;                   // enum of atom_dgpu_vram_type
3089   uint8_t   channel_num;                   // Number of mem. channels supported in this module
3090   uint8_t   channel_width;                 // CHANNEL_16BIT/CHANNEL_32BIT/CHANNEL_64BIT
3091   uint8_t   density;                       // _8Mx32, _16Mx32, _16Mx16, _32Mx16
3092   uint8_t   tunningset_id;                 // MC phy registers set per.
3093   uint8_t   vender_rev_id;                 // [7:4] Revision, [3:0] Vendor code
3094   uint8_t   refreshrate;                   // [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64ms)
3095   uint8_t   hbm_ven_rev_id;		   // hbm_ven_rev_id
3096   uint8_t   vram_rsd2;			   // reserved
3097   char    dram_pnstring[20];               // part number end with '0'.
3098 };
3099 
3100 struct atom_vram_info_header_v2_3 {
3101   struct   atom_common_table_header table_header;
3102   uint16_t mem_adjust_tbloffset;                         // offset of atom_umc_init_reg_block structure for memory vendor specific UMC adjust setting
3103   uint16_t mem_clk_patch_tbloffset;                      // offset of atom_umc_init_reg_block structure for memory clock specific UMC setting
3104   uint16_t mc_adjust_pertile_tbloffset;                  // offset of atom_umc_init_reg_block structure for Per Byte Offset Preset Settings
3105   uint16_t mc_phyinit_tbloffset;                         // offset of atom_umc_init_reg_block structure for MC phy init set
3106   uint16_t dram_data_remap_tbloffset;                    // reserved for now
3107   uint16_t tmrs_seq_offset;                              // offset of HBM tmrs
3108   uint16_t post_ucode_init_offset;                       // offset of atom_umc_init_reg_block structure for MC phy init after MC uCode complete umc init
3109   uint16_t vram_rsd2;
3110   uint8_t  vram_module_num;                              // indicate number of VRAM module
3111   uint8_t  umcip_min_ver;
3112   uint8_t  umcip_max_ver;
3113   uint8_t  mc_phy_tile_num;                              // indicate the MCD tile number which use in DramDataRemapTbl and usMcAdjustPerTileTblOffset
3114   struct   atom_vram_module_v9  vram_module[16];         // just for allocation, real number of blocks is in ucNumOfVRAMModule;
3115 };
3116 
3117 /*
3118   ***************************************************************************
3119     Data Table vram_info v3.0  structure
3120   ***************************************************************************
3121 */
3122 struct atom_vram_module_v3_0 {
3123 	uint8_t density;
3124 	uint8_t tunningset_id;
3125 	uint8_t ext_memory_id;
3126 	uint8_t dram_vendor_id;
3127 	uint16_t dram_info_offset;
3128 	uint16_t mem_tuning_offset;
3129 	uint16_t tmrs_seq_offset;
3130 	uint16_t reserved1;
3131 	uint32_t dram_size_per_ch;
3132 	uint32_t reserved[3];
3133 	char dram_pnstring[40];
3134 };
3135 
3136 struct atom_vram_info_header_v3_0 {
3137 	struct atom_common_table_header table_header;
3138 	uint16_t mem_tuning_table_offset;
3139 	uint16_t dram_info_table_offset;
3140 	uint16_t tmrs_table_offset;
3141 	uint16_t mc_init_table_offset;
3142 	uint16_t dram_data_remap_table_offset;
3143 	uint16_t umc_emuinittable_offset;
3144 	uint16_t reserved_sub_table_offset[2];
3145 	uint8_t vram_module_num;
3146 	uint8_t umcip_min_ver;
3147 	uint8_t umcip_max_ver;
3148 	uint8_t mc_phy_tile_num;
3149 	uint8_t memory_type;
3150 	uint8_t channel_num;
3151 	uint8_t channel_width;
3152 	uint8_t reserved1;
3153 	uint32_t channel_enable;
3154 	uint32_t channel1_enable;
3155 	uint32_t feature_enable;
3156 	uint32_t feature1_enable;
3157 	uint32_t hardcode_mem_size;
3158 	uint32_t reserved4[4];
3159 	struct atom_vram_module_v3_0 vram_module[8];
3160 };
3161 
3162 struct atom_umc_register_addr_info{
3163   uint32_t  umc_register_addr:24;
3164   uint32_t  umc_reg_type_ind:1;
3165   uint32_t  umc_reg_rsvd:7;
3166 };
3167 
3168 //atom_umc_register_addr_info.
3169 enum atom_umc_register_addr_info_flag{
3170   b3ATOM_UMC_REG_ADD_INFO_INDIRECT_ACCESS  =0x01,
3171 };
3172 
3173 union atom_umc_register_addr_info_access
3174 {
3175   struct atom_umc_register_addr_info umc_reg_addr;
3176   uint32_t u32umc_reg_addr;
3177 };
3178 
3179 struct atom_umc_reg_setting_id_config{
3180   uint32_t memclockrange:24;
3181   uint32_t mem_blk_id:8;
3182 };
3183 
3184 union atom_umc_reg_setting_id_config_access
3185 {
3186   struct atom_umc_reg_setting_id_config umc_id_access;
3187   uint32_t  u32umc_id_access;
3188 };
3189 
3190 struct atom_umc_reg_setting_data_block{
3191   union atom_umc_reg_setting_id_config_access  block_id;
3192   uint32_t u32umc_reg_data[1];
3193 };
3194 
3195 struct atom_umc_init_reg_block{
3196   uint16_t umc_reg_num;
3197   uint16_t reserved;
3198   union atom_umc_register_addr_info_access umc_reg_list[1];     //for allocation purpose, the real number come from umc_reg_num;
3199   struct atom_umc_reg_setting_data_block umc_reg_setting_list[1];
3200 };
3201 
3202 struct atom_vram_module_v10 {
3203   // Design Specific Values
3204   uint32_t  memory_size;                   // Total memory size in unit of MB for CONFIG_MEMSIZE zeros
3205   uint32_t  channel_enable;                // bit vector, each bit indicate specific channel enable or not
3206   uint32_t  max_mem_clk;                   // max memory clock of this memory in unit of 10kHz, =0 means it is not defined
3207   uint16_t  reserved[3];
3208   uint16_t  mem_voltage;                   // mem_voltage
3209   uint16_t  vram_module_size;              // Size of atom_vram_module_v9
3210   uint8_t   ext_memory_id;                 // Current memory module ID
3211   uint8_t   memory_type;                   // enum of atom_dgpu_vram_type
3212   uint8_t   channel_num;                   // Number of mem. channels supported in this module
3213   uint8_t   channel_width;                 // CHANNEL_16BIT/CHANNEL_32BIT/CHANNEL_64BIT
3214   uint8_t   density;                       // _8Mx32, _16Mx32, _16Mx16, _32Mx16
3215   uint8_t   tunningset_id;                 // MC phy registers set per
3216   uint8_t   vender_rev_id;                 // [7:4] Revision, [3:0] Vendor code
3217   uint8_t   refreshrate;                   // [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64ms)
3218   uint8_t   vram_flags;			   // bit0= bankgroup enable
3219   uint8_t   vram_rsd2;			   // reserved
3220   uint16_t  gddr6_mr10;                    // gddr6 mode register10 value
3221   uint16_t  gddr6_mr1;                     // gddr6 mode register1 value
3222   uint16_t  gddr6_mr2;                     // gddr6 mode register2 value
3223   uint16_t  gddr6_mr7;                     // gddr6 mode register7 value
3224   char    dram_pnstring[20];               // part number end with '0'
3225 };
3226 
3227 struct atom_vram_info_header_v2_4 {
3228   struct   atom_common_table_header table_header;
3229   uint16_t mem_adjust_tbloffset;                         // offset of atom_umc_init_reg_block structure for memory vendor specific UMC adjust setting
3230   uint16_t mem_clk_patch_tbloffset;                      // offset of atom_umc_init_reg_block structure for memory clock specific UMC setting
3231   uint16_t mc_adjust_pertile_tbloffset;                  // offset of atom_umc_init_reg_block structure for Per Byte Offset Preset Settings
3232   uint16_t mc_phyinit_tbloffset;                         // offset of atom_umc_init_reg_block structure for MC phy init set
3233   uint16_t dram_data_remap_tbloffset;                    // reserved for now
3234   uint16_t reserved;                                     // offset of reserved
3235   uint16_t post_ucode_init_offset;                       // offset of atom_umc_init_reg_block structure for MC phy init after MC uCode complete umc init
3236   uint16_t vram_rsd2;
3237   uint8_t  vram_module_num;                              // indicate number of VRAM module
3238   uint8_t  umcip_min_ver;
3239   uint8_t  umcip_max_ver;
3240   uint8_t  mc_phy_tile_num;                              // indicate the MCD tile number which use in DramDataRemapTbl and usMcAdjustPerTileTblOffset
3241   struct   atom_vram_module_v10  vram_module[16];        // just for allocation, real number of blocks is in ucNumOfVRAMModule;
3242 };
3243 
3244 struct atom_vram_module_v11 {
3245 	// Design Specific Values
3246 	uint32_t  memory_size;                   // Total memory size in unit of MB for CONFIG_MEMSIZE zeros
3247 	uint32_t  channel_enable;                // bit vector, each bit indicate specific channel enable or not
3248 	uint16_t  mem_voltage;                   // mem_voltage
3249 	uint16_t  vram_module_size;              // Size of atom_vram_module_v9
3250 	uint8_t   ext_memory_id;                 // Current memory module ID
3251 	uint8_t   memory_type;                   // enum of atom_dgpu_vram_type
3252 	uint8_t   channel_num;                   // Number of mem. channels supported in this module
3253 	uint8_t   channel_width;                 // CHANNEL_16BIT/CHANNEL_32BIT/CHANNEL_64BIT
3254 	uint8_t   density;                       // _8Mx32, _16Mx32, _16Mx16, _32Mx16
3255 	uint8_t   tunningset_id;                 // MC phy registers set per.
3256 	uint16_t  reserved[4];                   // reserved
3257 	uint8_t   vender_rev_id;                 // [7:4] Revision, [3:0] Vendor code
3258 	uint8_t   refreshrate;			 // [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64ms)
3259 	uint8_t   vram_flags;			 // bit0= bankgroup enable
3260 	uint8_t   vram_rsd2;			 // reserved
3261 	uint16_t  gddr6_mr10;                    // gddr6 mode register10 value
3262 	uint16_t  gddr6_mr0;                     // gddr6 mode register0 value
3263 	uint16_t  gddr6_mr1;                     // gddr6 mode register1 value
3264 	uint16_t  gddr6_mr2;                     // gddr6 mode register2 value
3265 	uint16_t  gddr6_mr4;                     // gddr6 mode register4 value
3266 	uint16_t  gddr6_mr7;                     // gddr6 mode register7 value
3267 	uint16_t  gddr6_mr8;                     // gddr6 mode register8 value
3268 	char    dram_pnstring[40];               // part number end with '0'.
3269 };
3270 
3271 struct atom_gddr6_ac_timing_v2_5 {
3272 	uint32_t  u32umc_id_access;
3273 	uint8_t  RL;
3274 	uint8_t  WL;
3275 	uint8_t  tRAS;
3276 	uint8_t  tRC;
3277 
3278 	uint16_t  tREFI;
3279 	uint8_t  tRFC;
3280 	uint8_t  tRFCpb;
3281 
3282 	uint8_t  tRREFD;
3283 	uint8_t  tRCDRD;
3284 	uint8_t  tRCDWR;
3285 	uint8_t  tRP;
3286 
3287 	uint8_t  tRRDS;
3288 	uint8_t  tRRDL;
3289 	uint8_t  tWR;
3290 	uint8_t  tWTRS;
3291 
3292 	uint8_t  tWTRL;
3293 	uint8_t  tFAW;
3294 	uint8_t  tCCDS;
3295 	uint8_t  tCCDL;
3296 
3297 	uint8_t  tCRCRL;
3298 	uint8_t  tCRCWL;
3299 	uint8_t  tCKE;
3300 	uint8_t  tCKSRE;
3301 
3302 	uint8_t  tCKSRX;
3303 	uint8_t  tRTPS;
3304 	uint8_t  tRTPL;
3305 	uint8_t  tMRD;
3306 
3307 	uint8_t  tMOD;
3308 	uint8_t  tXS;
3309 	uint8_t  tXHP;
3310 	uint8_t  tXSMRS;
3311 
3312 	uint32_t  tXSH;
3313 
3314 	uint8_t  tPD;
3315 	uint8_t  tXP;
3316 	uint8_t  tCPDED;
3317 	uint8_t  tACTPDE;
3318 
3319 	uint8_t  tPREPDE;
3320 	uint8_t  tREFPDE;
3321 	uint8_t  tMRSPDEN;
3322 	uint8_t  tRDSRE;
3323 
3324 	uint8_t  tWRSRE;
3325 	uint8_t  tPPD;
3326 	uint8_t  tCCDMW;
3327 	uint8_t  tWTRTR;
3328 
3329 	uint8_t  tLTLTR;
3330 	uint8_t  tREFTR;
3331 	uint8_t  VNDR;
3332 	uint8_t  reserved[9];
3333 };
3334 
3335 struct atom_gddr6_bit_byte_remap {
3336 	uint32_t dphy_byteremap;    //mmUMC_DPHY_ByteRemap
3337 	uint32_t dphy_bitremap0;    //mmUMC_DPHY_BitRemap0
3338 	uint32_t dphy_bitremap1;    //mmUMC_DPHY_BitRemap1
3339 	uint32_t dphy_bitremap2;    //mmUMC_DPHY_BitRemap2
3340 	uint32_t aphy_bitremap0;    //mmUMC_APHY_BitRemap0
3341 	uint32_t aphy_bitremap1;    //mmUMC_APHY_BitRemap1
3342 	uint32_t phy_dram;          //mmUMC_PHY_DRAM
3343 };
3344 
3345 struct atom_gddr6_dram_data_remap {
3346 	uint32_t table_size;
3347 	uint8_t phyintf_ck_inverted[8];     //UMC_PHY_PHYINTF_CNTL.INV_CK
3348 	struct atom_gddr6_bit_byte_remap bit_byte_remap[16];
3349 };
3350 
3351 struct atom_vram_info_header_v2_5 {
3352 	struct   atom_common_table_header table_header;
3353 	uint16_t mem_adjust_tbloffset;                         // offset of atom_umc_init_reg_block structure for memory vendor specific UMC adjust settings
3354 	uint16_t gddr6_ac_timing_offset;                     // offset of atom_gddr6_ac_timing_v2_5 structure for memory clock specific UMC settings
3355 	uint16_t mc_adjust_pertile_tbloffset;                  // offset of atom_umc_init_reg_block structure for Per Byte Offset Preset Settings
3356 	uint16_t mc_phyinit_tbloffset;                         // offset of atom_umc_init_reg_block structure for MC phy init set
3357 	uint16_t dram_data_remap_tbloffset;                    // offset of atom_gddr6_dram_data_remap array to indicate DRAM data lane to GPU mapping
3358 	uint16_t reserved;                                     // offset of reserved
3359 	uint16_t post_ucode_init_offset;                       // offset of atom_umc_init_reg_block structure for MC phy init after MC uCode complete umc init
3360 	uint16_t strobe_mode_patch_tbloffset;                  // offset of atom_umc_init_reg_block structure for Strobe Mode memory clock specific UMC settings
3361 	uint8_t  vram_module_num;                              // indicate number of VRAM module
3362 	uint8_t  umcip_min_ver;
3363 	uint8_t  umcip_max_ver;
3364 	uint8_t  mc_phy_tile_num;                              // indicate the MCD tile number which use in DramDataRemapTbl and usMcAdjustPerTileTblOffset
3365 	struct   atom_vram_module_v11  vram_module[16];        // just for allocation, real number of blocks is in ucNumOfVRAMModule;
3366 };
3367 
3368 struct atom_vram_info_header_v2_6 {
3369 	struct atom_common_table_header table_header;
3370 	uint16_t mem_adjust_tbloffset;
3371 	uint16_t mem_clk_patch_tbloffset;
3372 	uint16_t mc_adjust_pertile_tbloffset;
3373 	uint16_t mc_phyinit_tbloffset;
3374 	uint16_t dram_data_remap_tbloffset;
3375 	uint16_t tmrs_seq_offset;
3376 	uint16_t post_ucode_init_offset;
3377 	uint16_t vram_rsd2;
3378 	uint8_t  vram_module_num;
3379 	uint8_t  umcip_min_ver;
3380 	uint8_t  umcip_max_ver;
3381 	uint8_t  mc_phy_tile_num;
3382 	struct atom_vram_module_v9 vram_module[16];
3383 };
3384 /*
3385   ***************************************************************************
3386     Data Table voltageobject_info  structure
3387   ***************************************************************************
3388 */
3389 struct  atom_i2c_data_entry
3390 {
3391   uint16_t  i2c_reg_index;               // i2c register address, can be up to 16bit
3392   uint16_t  i2c_reg_data;                // i2c register data, can be up to 16bit
3393 };
3394 
3395 struct atom_voltage_object_header_v4{
3396   uint8_t    voltage_type;                           //enum atom_voltage_type
3397   uint8_t    voltage_mode;                           //enum atom_voltage_object_mode
3398   uint16_t   object_size;                            //Size of Object
3399 };
3400 
3401 // atom_voltage_object_header_v4.voltage_mode
3402 enum atom_voltage_object_mode
3403 {
3404    VOLTAGE_OBJ_GPIO_LUT              =  0,        //VOLTAGE and GPIO Lookup table ->atom_gpio_voltage_object_v4
3405    VOLTAGE_OBJ_VR_I2C_INIT_SEQ       =  3,        //VOLTAGE REGULATOR INIT sequece through I2C -> atom_i2c_voltage_object_v4
3406    VOLTAGE_OBJ_PHASE_LUT             =  4,        //Set Vregulator Phase lookup table ->atom_gpio_voltage_object_v4
3407    VOLTAGE_OBJ_SVID2                 =  7,        //Indicate voltage control by SVID2 ->atom_svid2_voltage_object_v4
3408    VOLTAGE_OBJ_EVV                   =  8,
3409    VOLTAGE_OBJ_MERGED_POWER          =  9,
3410 };
3411 
3412 struct  atom_i2c_voltage_object_v4
3413 {
3414    struct atom_voltage_object_header_v4 header;  // voltage mode = VOLTAGE_OBJ_VR_I2C_INIT_SEQ
3415    uint8_t  regulator_id;                        //Indicate Voltage Regulator Id
3416    uint8_t  i2c_id;
3417    uint8_t  i2c_slave_addr;
3418    uint8_t  i2c_control_offset;
3419    uint8_t  i2c_flag;                            // Bit0: 0 - One byte data; 1 - Two byte data
3420    uint8_t  i2c_speed;                           // =0, use default i2c speed, otherwise use it in unit of kHz.
3421    uint8_t  reserved[2];
3422    struct atom_i2c_data_entry i2cdatalut[1];     // end with 0xff
3423 };
3424 
3425 // ATOM_I2C_VOLTAGE_OBJECT_V3.ucVoltageControlFlag
3426 enum atom_i2c_voltage_control_flag
3427 {
3428    VOLTAGE_DATA_ONE_BYTE = 0,
3429    VOLTAGE_DATA_TWO_BYTE = 1,
3430 };
3431 
3432 
3433 struct atom_voltage_gpio_map_lut
3434 {
3435   uint32_t  voltage_gpio_reg_val;              // The Voltage ID which is used to program GPIO register
3436   uint16_t  voltage_level_mv;                  // The corresponding Voltage Value, in mV
3437 };
3438 
3439 struct atom_gpio_voltage_object_v4
3440 {
3441    struct atom_voltage_object_header_v4 header;  // voltage mode = VOLTAGE_OBJ_GPIO_LUT or VOLTAGE_OBJ_PHASE_LUT
3442    uint8_t  gpio_control_id;                     // default is 0 which indicate control through CG VID mode
3443    uint8_t  gpio_entry_num;                      // indiate the entry numbers of Votlage/Gpio value Look up table
3444    uint8_t  phase_delay_us;                      // phase delay in unit of micro second
3445    uint8_t  reserved;
3446    uint32_t gpio_mask_val;                         // GPIO Mask value
3447    struct atom_voltage_gpio_map_lut voltage_gpio_lut[1];
3448 };
3449 
3450 struct  atom_svid2_voltage_object_v4
3451 {
3452    struct atom_voltage_object_header_v4 header;  // voltage mode = VOLTAGE_OBJ_SVID2
3453    uint8_t loadline_psi1;                        // bit4:0= loadline setting ( Core Loadline trim and offset trim ), bit5=0:PSI1_L disable =1: PSI1_L enable
3454    uint8_t psi0_l_vid_thresd;                    // VR PSI0_L VID threshold
3455    uint8_t psi0_enable;                          //
3456    uint8_t maxvstep;
3457    uint8_t telemetry_offset;
3458    uint8_t telemetry_gain;
3459    uint16_t reserved1;
3460 };
3461 
3462 struct atom_merged_voltage_object_v4
3463 {
3464   struct atom_voltage_object_header_v4 header;  // voltage mode = VOLTAGE_OBJ_MERGED_POWER
3465   uint8_t  merged_powerrail_type;               //enum atom_voltage_type
3466   uint8_t  reserved[3];
3467 };
3468 
3469 union atom_voltage_object_v4{
3470   struct atom_gpio_voltage_object_v4 gpio_voltage_obj;
3471   struct atom_i2c_voltage_object_v4 i2c_voltage_obj;
3472   struct atom_svid2_voltage_object_v4 svid2_voltage_obj;
3473   struct atom_merged_voltage_object_v4 merged_voltage_obj;
3474 };
3475 
3476 struct  atom_voltage_objects_info_v4_1
3477 {
3478   struct atom_common_table_header table_header;
3479   union atom_voltage_object_v4 voltage_object[1];   //Info for Voltage control
3480 };
3481 
3482 
3483 /*
3484   ***************************************************************************
3485               All Command Function structure definition
3486   ***************************************************************************
3487 */
3488 
3489 /*
3490   ***************************************************************************
3491               Structures used by asic_init
3492   ***************************************************************************
3493 */
3494 
3495 struct asic_init_engine_parameters
3496 {
3497   uint32_t sclkfreqin10khz:24;
3498   uint32_t engineflag:8;              /* enum atom_asic_init_engine_flag  */
3499 };
3500 
3501 struct asic_init_mem_parameters
3502 {
3503   uint32_t mclkfreqin10khz:24;
3504   uint32_t memflag:8;                 /* enum atom_asic_init_mem_flag  */
3505 };
3506 
3507 struct asic_init_parameters_v2_1
3508 {
3509   struct asic_init_engine_parameters engineparam;
3510   struct asic_init_mem_parameters memparam;
3511 };
3512 
3513 struct asic_init_ps_allocation_v2_1
3514 {
3515   struct asic_init_parameters_v2_1 param;
3516   uint32_t reserved[16];
3517 };
3518 
3519 
3520 enum atom_asic_init_engine_flag
3521 {
3522   b3NORMAL_ENGINE_INIT = 0,
3523   b3SRIOV_SKIP_ASIC_INIT = 0x02,
3524   b3SRIOV_LOAD_UCODE = 0x40,
3525 };
3526 
3527 enum atom_asic_init_mem_flag
3528 {
3529   b3NORMAL_MEM_INIT = 0,
3530   b3DRAM_SELF_REFRESH_EXIT =0x20,
3531 };
3532 
3533 /*
3534   ***************************************************************************
3535               Structures used by setengineclock
3536   ***************************************************************************
3537 */
3538 
3539 struct set_engine_clock_parameters_v2_1
3540 {
3541   uint32_t sclkfreqin10khz:24;
3542   uint32_t sclkflag:8;              /* enum atom_set_engine_mem_clock_flag,  */
3543   uint32_t reserved[10];
3544 };
3545 
3546 struct set_engine_clock_ps_allocation_v2_1
3547 {
3548   struct set_engine_clock_parameters_v2_1 clockinfo;
3549   uint32_t reserved[10];
3550 };
3551 
3552 
3553 enum atom_set_engine_mem_clock_flag
3554 {
3555   b3NORMAL_CHANGE_CLOCK = 0,
3556   b3FIRST_TIME_CHANGE_CLOCK = 0x08,
3557   b3STORE_DPM_TRAINGING = 0x40,         //Applicable to memory clock change,when set, it store specific DPM mode training result
3558 };
3559 
3560 /*
3561   ***************************************************************************
3562               Structures used by getengineclock
3563   ***************************************************************************
3564 */
3565 struct get_engine_clock_parameter
3566 {
3567   uint32_t sclk_10khz;          // current engine speed in 10KHz unit
3568   uint32_t reserved;
3569 };
3570 
3571 /*
3572   ***************************************************************************
3573               Structures used by setmemoryclock
3574   ***************************************************************************
3575 */
3576 struct set_memory_clock_parameters_v2_1
3577 {
3578   uint32_t mclkfreqin10khz:24;
3579   uint32_t mclkflag:8;              /* enum atom_set_engine_mem_clock_flag,  */
3580   uint32_t reserved[10];
3581 };
3582 
3583 struct set_memory_clock_ps_allocation_v2_1
3584 {
3585   struct set_memory_clock_parameters_v2_1 clockinfo;
3586   uint32_t reserved[10];
3587 };
3588 
3589 
3590 /*
3591   ***************************************************************************
3592               Structures used by getmemoryclock
3593   ***************************************************************************
3594 */
3595 struct get_memory_clock_parameter
3596 {
3597   uint32_t mclk_10khz;          // current engine speed in 10KHz unit
3598   uint32_t reserved;
3599 };
3600 
3601 
3602 
3603 /*
3604   ***************************************************************************
3605               Structures used by setvoltage
3606   ***************************************************************************
3607 */
3608 
3609 struct set_voltage_parameters_v1_4
3610 {
3611   uint8_t  voltagetype;                /* enum atom_voltage_type */
3612   uint8_t  command;                    /* Indicate action: Set voltage level, enum atom_set_voltage_command */
3613   uint16_t vlevel_mv;                  /* real voltage level in unit of mv or Voltage Phase (0, 1, 2, .. ) */
3614 };
3615 
3616 //set_voltage_parameters_v2_1.voltagemode
3617 enum atom_set_voltage_command{
3618   ATOM_SET_VOLTAGE  = 0,
3619   ATOM_INIT_VOLTAGE_REGULATOR = 3,
3620   ATOM_SET_VOLTAGE_PHASE = 4,
3621   ATOM_GET_LEAKAGE_ID    = 8,
3622 };
3623 
3624 struct set_voltage_ps_allocation_v1_4
3625 {
3626   struct set_voltage_parameters_v1_4 setvoltageparam;
3627   uint32_t reserved[10];
3628 };
3629 
3630 
3631 /*
3632   ***************************************************************************
3633               Structures used by computegpuclockparam
3634   ***************************************************************************
3635 */
3636 
3637 //ATOM_COMPUTE_CLOCK_FREQ.ulComputeClockFlag
3638 enum atom_gpu_clock_type
3639 {
3640   COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK =0x00,
3641   COMPUTE_GPUCLK_INPUT_FLAG_GFXCLK =0x01,
3642   COMPUTE_GPUCLK_INPUT_FLAG_UCLK =0x02,
3643 };
3644 
3645 struct compute_gpu_clock_input_parameter_v1_8
3646 {
3647   uint32_t  gpuclock_10khz:24;         //Input= target clock, output = actual clock
3648   uint32_t  gpu_clock_type:8;          //Input indicate clock type: enum atom_gpu_clock_type
3649   uint32_t  reserved[5];
3650 };
3651 
3652 
3653 struct compute_gpu_clock_output_parameter_v1_8
3654 {
3655   uint32_t  gpuclock_10khz:24;              //Input= target clock, output = actual clock
3656   uint32_t  dfs_did:8;                      //return parameter: DFS divider which is used to program to register directly
3657   uint32_t  pll_fb_mult;                    //Feedback Multiplier, bit 8:0 int, bit 15:12 post_div, bit 31:16 frac
3658   uint32_t  pll_ss_fbsmult;                 // Spread FB Mult: bit 8:0 int, bit 31:16 frac
3659   uint16_t  pll_ss_slew_frac;
3660   uint8_t   pll_ss_enable;
3661   uint8_t   reserved;
3662   uint32_t  reserved1[2];
3663 };
3664 
3665 
3666 
3667 /*
3668   ***************************************************************************
3669               Structures used by ReadEfuseValue
3670   ***************************************************************************
3671 */
3672 
3673 struct read_efuse_input_parameters_v3_1
3674 {
3675   uint16_t efuse_start_index;
3676   uint8_t  reserved;
3677   uint8_t  bitslen;
3678 };
3679 
3680 // ReadEfuseValue input/output parameter
3681 union read_efuse_value_parameters_v3_1
3682 {
3683   struct read_efuse_input_parameters_v3_1 efuse_info;
3684   uint32_t efusevalue;
3685 };
3686 
3687 
3688 /*
3689   ***************************************************************************
3690               Structures used by getsmuclockinfo
3691   ***************************************************************************
3692 */
3693 struct atom_get_smu_clock_info_parameters_v3_1
3694 {
3695   uint8_t syspll_id;          // 0= syspll0, 1=syspll1, 2=syspll2
3696   uint8_t clk_id;             // atom_smu9_syspll0_clock_id  (only valid when command == GET_SMU_CLOCK_INFO_V3_1_GET_CLOCK_FREQ )
3697   uint8_t command;            // enum of atom_get_smu_clock_info_command
3698   uint8_t dfsdid;             // =0: get DFS DID from register, >0, give DFS divider, (only valid when command == GET_SMU_CLOCK_INFO_V3_1_GET_CLOCK_FREQ )
3699 };
3700 
3701 enum atom_get_smu_clock_info_command
3702 {
3703   GET_SMU_CLOCK_INFO_V3_1_GET_CLOCK_FREQ       = 0,
3704   GET_SMU_CLOCK_INFO_V3_1_GET_PLLVCO_FREQ      = 1,
3705   GET_SMU_CLOCK_INFO_V3_1_GET_PLLREFCLK_FREQ   = 2,
3706 };
3707 
3708 enum atom_smu9_syspll0_clock_id
3709 {
3710   SMU9_SYSPLL0_SMNCLK_ID   = 0,       //  SMNCLK
3711   SMU9_SYSPLL0_SOCCLK_ID   = 1,       //	SOCCLK (FCLK)
3712   SMU9_SYSPLL0_MP0CLK_ID   = 2,       //	MP0CLK
3713   SMU9_SYSPLL0_MP1CLK_ID   = 3,       //	MP1CLK
3714   SMU9_SYSPLL0_LCLK_ID     = 4,       //	LCLK
3715   SMU9_SYSPLL0_DCLK_ID     = 5,       //	DCLK
3716   SMU9_SYSPLL0_VCLK_ID     = 6,       //	VCLK
3717   SMU9_SYSPLL0_ECLK_ID     = 7,       //	ECLK
3718   SMU9_SYSPLL0_DCEFCLK_ID  = 8,       //	DCEFCLK
3719   SMU9_SYSPLL0_DPREFCLK_ID = 10,      //	DPREFCLK
3720   SMU9_SYSPLL0_DISPCLK_ID  = 11,      //	DISPCLK
3721 };
3722 
3723 enum atom_smu11_syspll_id {
3724   SMU11_SYSPLL0_ID            = 0,
3725   SMU11_SYSPLL1_0_ID          = 1,
3726   SMU11_SYSPLL1_1_ID          = 2,
3727   SMU11_SYSPLL1_2_ID          = 3,
3728   SMU11_SYSPLL2_ID            = 4,
3729   SMU11_SYSPLL3_0_ID          = 5,
3730   SMU11_SYSPLL3_1_ID          = 6,
3731 };
3732 
3733 enum atom_smu11_syspll0_clock_id {
3734   SMU11_SYSPLL0_ECLK_ID     = 0,       //	ECLK
3735   SMU11_SYSPLL0_SOCCLK_ID   = 1,       //	SOCCLK
3736   SMU11_SYSPLL0_MP0CLK_ID   = 2,       //	MP0CLK
3737   SMU11_SYSPLL0_DCLK_ID     = 3,       //	DCLK
3738   SMU11_SYSPLL0_VCLK_ID     = 4,       //	VCLK
3739   SMU11_SYSPLL0_DCEFCLK_ID  = 5,       //	DCEFCLK
3740 };
3741 
3742 enum atom_smu11_syspll1_0_clock_id {
3743   SMU11_SYSPLL1_0_UCLKA_ID   = 0,       // UCLK_a
3744 };
3745 
3746 enum atom_smu11_syspll1_1_clock_id {
3747   SMU11_SYSPLL1_0_UCLKB_ID   = 0,       // UCLK_b
3748 };
3749 
3750 enum atom_smu11_syspll1_2_clock_id {
3751   SMU11_SYSPLL1_0_FCLK_ID   = 0,        // FCLK
3752 };
3753 
3754 enum atom_smu11_syspll2_clock_id {
3755   SMU11_SYSPLL2_GFXCLK_ID   = 0,        // GFXCLK
3756 };
3757 
3758 enum atom_smu11_syspll3_0_clock_id {
3759   SMU11_SYSPLL3_0_WAFCLK_ID = 0,       //	WAFCLK
3760   SMU11_SYSPLL3_0_DISPCLK_ID = 1,      //	DISPCLK
3761   SMU11_SYSPLL3_0_DPREFCLK_ID = 2,     //	DPREFCLK
3762 };
3763 
3764 enum atom_smu11_syspll3_1_clock_id {
3765   SMU11_SYSPLL3_1_MP1CLK_ID = 0,       //	MP1CLK
3766   SMU11_SYSPLL3_1_SMNCLK_ID = 1,       //	SMNCLK
3767   SMU11_SYSPLL3_1_LCLK_ID = 2,         //	LCLK
3768 };
3769 
3770 enum atom_smu12_syspll_id {
3771   SMU12_SYSPLL0_ID          = 0,
3772   SMU12_SYSPLL1_ID          = 1,
3773   SMU12_SYSPLL2_ID          = 2,
3774   SMU12_SYSPLL3_0_ID        = 3,
3775   SMU12_SYSPLL3_1_ID        = 4,
3776 };
3777 
3778 enum atom_smu12_syspll0_clock_id {
3779   SMU12_SYSPLL0_SMNCLK_ID   = 0,			//	SOCCLK
3780   SMU12_SYSPLL0_SOCCLK_ID   = 1,			//	SOCCLK
3781   SMU12_SYSPLL0_MP0CLK_ID   = 2,			//	MP0CLK
3782   SMU12_SYSPLL0_MP1CLK_ID   = 3,			//	MP1CLK
3783   SMU12_SYSPLL0_MP2CLK_ID   = 4,			//	MP2CLK
3784   SMU12_SYSPLL0_VCLK_ID     = 5,			//	VCLK
3785   SMU12_SYSPLL0_LCLK_ID     = 6,			//	LCLK
3786   SMU12_SYSPLL0_DCLK_ID     = 7,			//	DCLK
3787   SMU12_SYSPLL0_ACLK_ID     = 8,			//	ACLK
3788   SMU12_SYSPLL0_ISPCLK_ID   = 9,			//	ISPCLK
3789   SMU12_SYSPLL0_SHUBCLK_ID  = 10,			//	SHUBCLK
3790 };
3791 
3792 enum atom_smu12_syspll1_clock_id {
3793   SMU12_SYSPLL1_DISPCLK_ID  = 0,      //	DISPCLK
3794   SMU12_SYSPLL1_DPPCLK_ID   = 1,      //	DPPCLK
3795   SMU12_SYSPLL1_DPREFCLK_ID = 2,      //	DPREFCLK
3796   SMU12_SYSPLL1_DCFCLK_ID   = 3,      //	DCFCLK
3797 };
3798 
3799 enum atom_smu12_syspll2_clock_id {
3800   SMU12_SYSPLL2_Pre_GFXCLK_ID = 0,   // Pre_GFXCLK
3801 };
3802 
3803 enum atom_smu12_syspll3_0_clock_id {
3804   SMU12_SYSPLL3_0_FCLK_ID = 0,      //	FCLK
3805 };
3806 
3807 enum atom_smu12_syspll3_1_clock_id {
3808   SMU12_SYSPLL3_1_UMCCLK_ID = 0,    //	UMCCLK
3809 };
3810 
3811 struct  atom_get_smu_clock_info_output_parameters_v3_1
3812 {
3813   union {
3814     uint32_t smu_clock_freq_hz;
3815     uint32_t syspllvcofreq_10khz;
3816     uint32_t sysspllrefclk_10khz;
3817   }atom_smu_outputclkfreq;
3818 };
3819 
3820 
3821 
3822 /*
3823   ***************************************************************************
3824               Structures used by dynamicmemorysettings
3825   ***************************************************************************
3826 */
3827 
3828 enum atom_dynamic_memory_setting_command
3829 {
3830   COMPUTE_MEMORY_PLL_PARAM = 1,
3831   COMPUTE_ENGINE_PLL_PARAM = 2,
3832   ADJUST_MC_SETTING_PARAM = 3,
3833 };
3834 
3835 /* when command = COMPUTE_MEMORY_PLL_PARAM or ADJUST_MC_SETTING_PARAM */
3836 struct dynamic_mclk_settings_parameters_v2_1
3837 {
3838   uint32_t  mclk_10khz:24;         //Input= target mclk
3839   uint32_t  command:8;             //command enum of atom_dynamic_memory_setting_command
3840   uint32_t  reserved;
3841 };
3842 
3843 /* when command = COMPUTE_ENGINE_PLL_PARAM */
3844 struct dynamic_sclk_settings_parameters_v2_1
3845 {
3846   uint32_t  sclk_10khz:24;         //Input= target mclk
3847   uint32_t  command:8;             //command enum of atom_dynamic_memory_setting_command
3848   uint32_t  mclk_10khz;
3849   uint32_t  reserved;
3850 };
3851 
3852 union dynamic_memory_settings_parameters_v2_1
3853 {
3854   struct dynamic_mclk_settings_parameters_v2_1 mclk_setting;
3855   struct dynamic_sclk_settings_parameters_v2_1 sclk_setting;
3856 };
3857 
3858 
3859 
3860 /*
3861   ***************************************************************************
3862               Structures used by memorytraining
3863   ***************************************************************************
3864 */
3865 
3866 enum atom_umc6_0_ucode_function_call_enum_id
3867 {
3868   UMC60_UCODE_FUNC_ID_REINIT                 = 0,
3869   UMC60_UCODE_FUNC_ID_ENTER_SELFREFRESH      = 1,
3870   UMC60_UCODE_FUNC_ID_EXIT_SELFREFRESH       = 2,
3871 };
3872 
3873 
3874 struct memory_training_parameters_v2_1
3875 {
3876   uint8_t ucode_func_id;
3877   uint8_t ucode_reserved[3];
3878   uint32_t reserved[5];
3879 };
3880 
3881 
3882 /*
3883   ***************************************************************************
3884               Structures used by setpixelclock
3885   ***************************************************************************
3886 */
3887 
3888 struct set_pixel_clock_parameter_v1_7
3889 {
3890     uint32_t pixclk_100hz;               // target the pixel clock to drive the CRTC timing in unit of 100Hz.
3891 
3892     uint8_t  pll_id;                     // ATOM_PHY_PLL0/ATOM_PHY_PLL1/ATOM_PPLL0
3893     uint8_t  encoderobjid;               // ASIC encoder id defined in objectId.h,
3894                                          // indicate which graphic encoder will be used.
3895     uint8_t  encoder_mode;               // Encoder mode:
3896     uint8_t  miscinfo;                   // enum atom_set_pixel_clock_v1_7_misc_info
3897     uint8_t  crtc_id;                    // enum of atom_crtc_def
3898     uint8_t  deep_color_ratio;           // HDMI panel bit depth: enum atom_set_pixel_clock_v1_7_deepcolor_ratio
3899     uint8_t  reserved1[2];
3900     uint32_t reserved2;
3901 };
3902 
3903 //ucMiscInfo
3904 enum atom_set_pixel_clock_v1_7_misc_info
3905 {
3906   PIXEL_CLOCK_V7_MISC_FORCE_PROG_PPLL         = 0x01,
3907   PIXEL_CLOCK_V7_MISC_PROG_PHYPLL             = 0x02,
3908   PIXEL_CLOCK_V7_MISC_YUV420_MODE             = 0x04,
3909   PIXEL_CLOCK_V7_MISC_DVI_DUALLINK_EN         = 0x08,
3910   PIXEL_CLOCK_V7_MISC_REF_DIV_SRC             = 0x30,
3911   PIXEL_CLOCK_V7_MISC_REF_DIV_SRC_XTALIN      = 0x00,
3912   PIXEL_CLOCK_V7_MISC_REF_DIV_SRC_PCIE        = 0x10,
3913   PIXEL_CLOCK_V7_MISC_REF_DIV_SRC_GENLK       = 0x20,
3914   PIXEL_CLOCK_V7_MISC_REF_DIV_SRC_REFPAD      = 0x30,
3915   PIXEL_CLOCK_V7_MISC_ATOMIC_UPDATE           = 0x40,
3916   PIXEL_CLOCK_V7_MISC_FORCE_SS_DIS            = 0x80,
3917 };
3918 
3919 /* deep_color_ratio */
3920 enum atom_set_pixel_clock_v1_7_deepcolor_ratio
3921 {
3922   PIXEL_CLOCK_V7_DEEPCOLOR_RATIO_DIS          = 0x00,      //00 - DCCG_DEEP_COLOR_DTO_DISABLE: Disable Deep Color DTO
3923   PIXEL_CLOCK_V7_DEEPCOLOR_RATIO_5_4          = 0x01,      //01 - DCCG_DEEP_COLOR_DTO_5_4_RATIO: Set Deep Color DTO to 5:4
3924   PIXEL_CLOCK_V7_DEEPCOLOR_RATIO_3_2          = 0x02,      //02 - DCCG_DEEP_COLOR_DTO_3_2_RATIO: Set Deep Color DTO to 3:2
3925   PIXEL_CLOCK_V7_DEEPCOLOR_RATIO_2_1          = 0x03,      //03 - DCCG_DEEP_COLOR_DTO_2_1_RATIO: Set Deep Color DTO to 2:1
3926 };
3927 
3928 /*
3929   ***************************************************************************
3930               Structures used by setdceclock
3931   ***************************************************************************
3932 */
3933 
3934 // SetDCEClock input parameter for DCE11.2( ELM and BF ) and above
3935 struct set_dce_clock_parameters_v2_1
3936 {
3937   uint32_t dceclk_10khz;                               // target DCE frequency in unit of 10KHZ, return real DISPCLK/DPREFCLK frequency.
3938   uint8_t  dceclktype;                                 // =0: DISPCLK  =1: DPREFCLK  =2: PIXCLK
3939   uint8_t  dceclksrc;                                  // ATOM_PLL0 or ATOM_GCK_DFS or ATOM_FCH_CLK or ATOM_COMBOPHY_PLLx
3940   uint8_t  dceclkflag;                                 // Bit [1:0] = PPLL ref clock source ( when ucDCEClkSrc= ATOM_PPLL0 )
3941   uint8_t  crtc_id;                                    // ucDisp Pipe Id, ATOM_CRTC0/1/2/..., use only when ucDCEClkType = PIXCLK
3942 };
3943 
3944 //ucDCEClkType
3945 enum atom_set_dce_clock_clock_type
3946 {
3947   DCE_CLOCK_TYPE_DISPCLK                      = 0,
3948   DCE_CLOCK_TYPE_DPREFCLK                     = 1,
3949   DCE_CLOCK_TYPE_PIXELCLK                     = 2,        // used by VBIOS internally, called by SetPixelClock
3950 };
3951 
3952 //ucDCEClkFlag when ucDCEClkType == DPREFCLK
3953 enum atom_set_dce_clock_dprefclk_flag
3954 {
3955   DCE_CLOCK_FLAG_PLL_REFCLK_SRC_MASK          = 0x03,
3956   DCE_CLOCK_FLAG_PLL_REFCLK_SRC_GENERICA      = 0x00,
3957   DCE_CLOCK_FLAG_PLL_REFCLK_SRC_GENLK         = 0x01,
3958   DCE_CLOCK_FLAG_PLL_REFCLK_SRC_PCIE          = 0x02,
3959   DCE_CLOCK_FLAG_PLL_REFCLK_SRC_XTALIN        = 0x03,
3960 };
3961 
3962 //ucDCEClkFlag when ucDCEClkType == PIXCLK
3963 enum atom_set_dce_clock_pixclk_flag
3964 {
3965   DCE_CLOCK_FLAG_PCLK_DEEPCOLOR_RATIO_MASK    = 0x03,
3966   DCE_CLOCK_FLAG_PCLK_DEEPCOLOR_RATIO_DIS     = 0x00,      //00 - DCCG_DEEP_COLOR_DTO_DISABLE: Disable Deep Color DTO
3967   DCE_CLOCK_FLAG_PCLK_DEEPCOLOR_RATIO_5_4     = 0x01,      //01 - DCCG_DEEP_COLOR_DTO_5_4_RATIO: Set Deep Color DTO to 5:4
3968   DCE_CLOCK_FLAG_PCLK_DEEPCOLOR_RATIO_3_2     = 0x02,      //02 - DCCG_DEEP_COLOR_DTO_3_2_RATIO: Set Deep Color DTO to 3:2
3969   DCE_CLOCK_FLAG_PCLK_DEEPCOLOR_RATIO_2_1     = 0x03,      //03 - DCCG_DEEP_COLOR_DTO_2_1_RATIO: Set Deep Color DTO to 2:1
3970   DCE_CLOCK_FLAG_PIXCLK_YUV420_MODE           = 0x04,
3971 };
3972 
3973 struct set_dce_clock_ps_allocation_v2_1
3974 {
3975   struct set_dce_clock_parameters_v2_1 param;
3976   uint32_t ulReserved[2];
3977 };
3978 
3979 
3980 /****************************************************************************/
3981 // Structures used by BlankCRTC
3982 /****************************************************************************/
3983 struct blank_crtc_parameters
3984 {
3985   uint8_t  crtc_id;                   // enum atom_crtc_def
3986   uint8_t  blanking;                  // enum atom_blank_crtc_command
3987   uint16_t reserved;
3988   uint32_t reserved1;
3989 };
3990 
3991 enum atom_blank_crtc_command
3992 {
3993   ATOM_BLANKING         = 1,
3994   ATOM_BLANKING_OFF     = 0,
3995 };
3996 
3997 /****************************************************************************/
3998 // Structures used by enablecrtc
3999 /****************************************************************************/
4000 struct enable_crtc_parameters
4001 {
4002   uint8_t crtc_id;                    // enum atom_crtc_def
4003   uint8_t enable;                     // ATOM_ENABLE or ATOM_DISABLE
4004   uint8_t padding[2];
4005 };
4006 
4007 
4008 /****************************************************************************/
4009 // Structure used by EnableDispPowerGating
4010 /****************************************************************************/
4011 struct enable_disp_power_gating_parameters_v2_1
4012 {
4013   uint8_t disp_pipe_id;                // ATOM_CRTC1, ATOM_CRTC2, ...
4014   uint8_t enable;                     // ATOM_ENABLE or ATOM_DISABLE
4015   uint8_t padding[2];
4016 };
4017 
4018 struct enable_disp_power_gating_ps_allocation
4019 {
4020   struct enable_disp_power_gating_parameters_v2_1 param;
4021   uint32_t ulReserved[4];
4022 };
4023 
4024 /****************************************************************************/
4025 // Structure used in setcrtc_usingdtdtiming
4026 /****************************************************************************/
4027 struct set_crtc_using_dtd_timing_parameters
4028 {
4029   uint16_t  h_size;
4030   uint16_t  h_blanking_time;
4031   uint16_t  v_size;
4032   uint16_t  v_blanking_time;
4033   uint16_t  h_syncoffset;
4034   uint16_t  h_syncwidth;
4035   uint16_t  v_syncoffset;
4036   uint16_t  v_syncwidth;
4037   uint16_t  modemiscinfo;
4038   uint8_t   h_border;
4039   uint8_t   v_border;
4040   uint8_t   crtc_id;                   // enum atom_crtc_def
4041   uint8_t   encoder_mode;			   // atom_encode_mode_def
4042   uint8_t   padding[2];
4043 };
4044 
4045 
4046 /****************************************************************************/
4047 // Structures used by processi2cchanneltransaction
4048 /****************************************************************************/
4049 struct process_i2c_channel_transaction_parameters
4050 {
4051   uint8_t i2cspeed_khz;
4052   union {
4053     uint8_t regindex;
4054     uint8_t status;                  /* enum atom_process_i2c_flag */
4055   } regind_status;
4056   uint16_t  i2c_data_out;
4057   uint8_t   flag;                    /* enum atom_process_i2c_status */
4058   uint8_t   trans_bytes;
4059   uint8_t   slave_addr;
4060   uint8_t   i2c_id;
4061 };
4062 
4063 //ucFlag
4064 enum atom_process_i2c_flag
4065 {
4066   HW_I2C_WRITE          = 1,
4067   HW_I2C_READ           = 0,
4068   I2C_2BYTE_ADDR        = 0x02,
4069   HW_I2C_SMBUS_BYTE_WR  = 0x04,
4070 };
4071 
4072 //status
4073 enum atom_process_i2c_status
4074 {
4075   HW_ASSISTED_I2C_STATUS_FAILURE     =2,
4076   HW_ASSISTED_I2C_STATUS_SUCCESS     =1,
4077 };
4078 
4079 
4080 /****************************************************************************/
4081 // Structures used by processauxchanneltransaction
4082 /****************************************************************************/
4083 
4084 struct process_aux_channel_transaction_parameters_v1_2
4085 {
4086   uint16_t aux_request;
4087   uint16_t dataout;
4088   uint8_t  channelid;
4089   union {
4090     uint8_t   reply_status;
4091     uint8_t   aux_delay;
4092   } aux_status_delay;
4093   uint8_t   dataout_len;
4094   uint8_t   hpd_id;                                       //=0: HPD1, =1: HPD2, =2: HPD3, =3: HPD4, =4: HPD5, =5: HPD6
4095 };
4096 
4097 
4098 /****************************************************************************/
4099 // Structures used by selectcrtc_source
4100 /****************************************************************************/
4101 
4102 struct select_crtc_source_parameters_v2_3
4103 {
4104   uint8_t crtc_id;                        // enum atom_crtc_def
4105   uint8_t encoder_id;                     // enum atom_dig_def
4106   uint8_t encode_mode;                    // enum atom_encode_mode_def
4107   uint8_t dst_bpc;                        // enum atom_panel_bit_per_color
4108 };
4109 
4110 
4111 /****************************************************************************/
4112 // Structures used by digxencodercontrol
4113 /****************************************************************************/
4114 
4115 // ucAction:
4116 enum atom_dig_encoder_control_action
4117 {
4118   ATOM_ENCODER_CMD_DISABLE_DIG                  = 0,
4119   ATOM_ENCODER_CMD_ENABLE_DIG                   = 1,
4120   ATOM_ENCODER_CMD_DP_LINK_TRAINING_START       = 0x08,
4121   ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN1    = 0x09,
4122   ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN2    = 0x0a,
4123   ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN3    = 0x13,
4124   ATOM_ENCODER_CMD_DP_LINK_TRAINING_COMPLETE    = 0x0b,
4125   ATOM_ENCODER_CMD_DP_VIDEO_OFF                 = 0x0c,
4126   ATOM_ENCODER_CMD_DP_VIDEO_ON                  = 0x0d,
4127   ATOM_ENCODER_CMD_SETUP_PANEL_MODE             = 0x10,
4128   ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN4    = 0x14,
4129   ATOM_ENCODER_CMD_STREAM_SETUP                 = 0x0F,
4130   ATOM_ENCODER_CMD_LINK_SETUP                   = 0x11,
4131   ATOM_ENCODER_CMD_ENCODER_BLANK                = 0x12,
4132 };
4133 
4134 //define ucPanelMode
4135 enum atom_dig_encoder_control_panelmode
4136 {
4137   DP_PANEL_MODE_DISABLE                        = 0x00,
4138   DP_PANEL_MODE_ENABLE_eDP_MODE                = 0x01,
4139   DP_PANEL_MODE_ENABLE_LVLINK_MODE             = 0x11,
4140 };
4141 
4142 //ucDigId
4143 enum atom_dig_encoder_control_v5_digid
4144 {
4145   ATOM_ENCODER_CONFIG_V5_DIG0_ENCODER           = 0x00,
4146   ATOM_ENCODER_CONFIG_V5_DIG1_ENCODER           = 0x01,
4147   ATOM_ENCODER_CONFIG_V5_DIG2_ENCODER           = 0x02,
4148   ATOM_ENCODER_CONFIG_V5_DIG3_ENCODER           = 0x03,
4149   ATOM_ENCODER_CONFIG_V5_DIG4_ENCODER           = 0x04,
4150   ATOM_ENCODER_CONFIG_V5_DIG5_ENCODER           = 0x05,
4151   ATOM_ENCODER_CONFIG_V5_DIG6_ENCODER           = 0x06,
4152   ATOM_ENCODER_CONFIG_V5_DIG7_ENCODER           = 0x07,
4153 };
4154 
4155 struct dig_encoder_stream_setup_parameters_v1_5
4156 {
4157   uint8_t digid;            // 0~6 map to DIG0~DIG6 enum atom_dig_encoder_control_v5_digid
4158   uint8_t action;           // =  ATOM_ENOCODER_CMD_STREAM_SETUP
4159   uint8_t digmode;          // ATOM_ENCODER_MODE_DP/ATOM_ENCODER_MODE_DVI/ATOM_ENCODER_MODE_HDMI
4160   uint8_t lanenum;          // Lane number
4161   uint32_t pclk_10khz;      // Pixel Clock in 10Khz
4162   uint8_t bitpercolor;
4163   uint8_t dplinkrate_270mhz;//= DP link rate/270Mhz, =6: 1.62G  = 10: 2.7G, =20: 5.4Ghz, =30: 8.1Ghz etc
4164   uint8_t reserved[2];
4165 };
4166 
4167 struct dig_encoder_link_setup_parameters_v1_5
4168 {
4169   uint8_t digid;           // 0~6 map to DIG0~DIG6 enum atom_dig_encoder_control_v5_digid
4170   uint8_t action;          // =  ATOM_ENOCODER_CMD_LINK_SETUP
4171   uint8_t digmode;         // ATOM_ENCODER_MODE_DP/ATOM_ENCODER_MODE_DVI/ATOM_ENCODER_MODE_HDMI
4172   uint8_t lanenum;         // Lane number
4173   uint8_t symclk_10khz;    // Symbol Clock in 10Khz
4174   uint8_t hpd_sel;
4175   uint8_t digfe_sel;       // DIG stream( front-end ) selection, bit0 means DIG0 FE is enable,
4176   uint8_t reserved[2];
4177 };
4178 
4179 struct dp_panel_mode_set_parameters_v1_5
4180 {
4181   uint8_t digid;              // 0~6 map to DIG0~DIG6 enum atom_dig_encoder_control_v5_digid
4182   uint8_t action;             // = ATOM_ENCODER_CMD_DPLINK_SETUP
4183   uint8_t panelmode;      // enum atom_dig_encoder_control_panelmode
4184   uint8_t reserved1;
4185   uint32_t reserved2[2];
4186 };
4187 
4188 struct dig_encoder_generic_cmd_parameters_v1_5
4189 {
4190   uint8_t digid;           // 0~6 map to DIG0~DIG6 enum atom_dig_encoder_control_v5_digid
4191   uint8_t action;          // = rest of generic encoder command which does not carry any parameters
4192   uint8_t reserved1[2];
4193   uint32_t reserved2[2];
4194 };
4195 
4196 union dig_encoder_control_parameters_v1_5
4197 {
4198   struct dig_encoder_generic_cmd_parameters_v1_5  cmd_param;
4199   struct dig_encoder_stream_setup_parameters_v1_5 stream_param;
4200   struct dig_encoder_link_setup_parameters_v1_5   link_param;
4201   struct dp_panel_mode_set_parameters_v1_5 dppanel_param;
4202 };
4203 
4204 /*
4205   ***************************************************************************
4206               Structures used by dig1transmittercontrol
4207   ***************************************************************************
4208 */
4209 struct dig_transmitter_control_parameters_v1_6
4210 {
4211   uint8_t phyid;           // 0=UNIPHYA, 1=UNIPHYB, 2=UNIPHYC, 3=UNIPHYD, 4= UNIPHYE 5=UNIPHYF
4212   uint8_t action;          // define as ATOM_TRANSMITER_ACTION_xxx
4213   union {
4214     uint8_t digmode;        // enum atom_encode_mode_def
4215     uint8_t dplaneset;      // DP voltage swing and pre-emphasis value defined in DPCD DP_LANE_SET, "DP_LANE_SET__xDB_y_zV"
4216   } mode_laneset;
4217   uint8_t  lanenum;        // Lane number 1, 2, 4, 8
4218   uint32_t symclk_10khz;   // Symbol Clock in 10Khz
4219   uint8_t  hpdsel;         // =1: HPD1, =2: HPD2, .... =6: HPD6, =0: HPD is not assigned
4220   uint8_t  digfe_sel;      // DIG stream( front-end ) selection, bit0 means DIG0 FE is enable,
4221   uint8_t  connobj_id;     // Connector Object Id defined in ObjectId.h
4222   uint8_t  reserved;
4223   uint32_t reserved1;
4224 };
4225 
4226 struct dig_transmitter_control_ps_allocation_v1_6
4227 {
4228   struct dig_transmitter_control_parameters_v1_6 param;
4229   uint32_t reserved[4];
4230 };
4231 
4232 //ucAction
4233 enum atom_dig_transmitter_control_action
4234 {
4235   ATOM_TRANSMITTER_ACTION_DISABLE                 = 0,
4236   ATOM_TRANSMITTER_ACTION_ENABLE                  = 1,
4237   ATOM_TRANSMITTER_ACTION_LCD_BLOFF               = 2,
4238   ATOM_TRANSMITTER_ACTION_LCD_BLON                = 3,
4239   ATOM_TRANSMITTER_ACTION_BL_BRIGHTNESS_CONTROL   = 4,
4240   ATOM_TRANSMITTER_ACTION_LCD_SELFTEST_START      = 5,
4241   ATOM_TRANSMITTER_ACTION_LCD_SELFTEST_STOP       = 6,
4242   ATOM_TRANSMITTER_ACTION_INIT                    = 7,
4243   ATOM_TRANSMITTER_ACTION_DISABLE_OUTPUT          = 8,
4244   ATOM_TRANSMITTER_ACTION_ENABLE_OUTPUT           = 9,
4245   ATOM_TRANSMITTER_ACTION_SETUP                   = 10,
4246   ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH            = 11,
4247   ATOM_TRANSMITTER_ACTION_POWER_ON                = 12,
4248   ATOM_TRANSMITTER_ACTION_POWER_OFF               = 13,
4249 };
4250 
4251 // digfe_sel
4252 enum atom_dig_transmitter_control_digfe_sel
4253 {
4254   ATOM_TRANMSITTER_V6__DIGA_SEL                   = 0x01,
4255   ATOM_TRANMSITTER_V6__DIGB_SEL                   = 0x02,
4256   ATOM_TRANMSITTER_V6__DIGC_SEL                   = 0x04,
4257   ATOM_TRANMSITTER_V6__DIGD_SEL                   = 0x08,
4258   ATOM_TRANMSITTER_V6__DIGE_SEL                   = 0x10,
4259   ATOM_TRANMSITTER_V6__DIGF_SEL                   = 0x20,
4260   ATOM_TRANMSITTER_V6__DIGG_SEL                   = 0x40,
4261 };
4262 
4263 
4264 //ucHPDSel
4265 enum atom_dig_transmitter_control_hpd_sel
4266 {
4267   ATOM_TRANSMITTER_V6_NO_HPD_SEL                  = 0x00,
4268   ATOM_TRANSMITTER_V6_HPD1_SEL                    = 0x01,
4269   ATOM_TRANSMITTER_V6_HPD2_SEL                    = 0x02,
4270   ATOM_TRANSMITTER_V6_HPD3_SEL                    = 0x03,
4271   ATOM_TRANSMITTER_V6_HPD4_SEL                    = 0x04,
4272   ATOM_TRANSMITTER_V6_HPD5_SEL                    = 0x05,
4273   ATOM_TRANSMITTER_V6_HPD6_SEL                    = 0x06,
4274 };
4275 
4276 // ucDPLaneSet
4277 enum atom_dig_transmitter_control_dplaneset
4278 {
4279   DP_LANE_SET__0DB_0_4V                           = 0x00,
4280   DP_LANE_SET__0DB_0_6V                           = 0x01,
4281   DP_LANE_SET__0DB_0_8V                           = 0x02,
4282   DP_LANE_SET__0DB_1_2V                           = 0x03,
4283   DP_LANE_SET__3_5DB_0_4V                         = 0x08,
4284   DP_LANE_SET__3_5DB_0_6V                         = 0x09,
4285   DP_LANE_SET__3_5DB_0_8V                         = 0x0a,
4286   DP_LANE_SET__6DB_0_4V                           = 0x10,
4287   DP_LANE_SET__6DB_0_6V                           = 0x11,
4288   DP_LANE_SET__9_5DB_0_4V                         = 0x18,
4289 };
4290 
4291 
4292 
4293 /****************************************************************************/
4294 // Structures used by ExternalEncoderControl V2.4
4295 /****************************************************************************/
4296 
4297 struct external_encoder_control_parameters_v2_4
4298 {
4299   uint16_t pixelclock_10khz;  // pixel clock in 10Khz, valid when ucAction=SETUP/ENABLE_OUTPUT
4300   uint8_t  config;            // indicate which encoder, and DP link rate when ucAction = SETUP/ENABLE_OUTPUT
4301   uint8_t  action;            //
4302   uint8_t  encodermode;       // encoder mode, only used when ucAction = SETUP/ENABLE_OUTPUT
4303   uint8_t  lanenum;           // lane number, only used when ucAction = SETUP/ENABLE_OUTPUT
4304   uint8_t  bitpercolor;       // output bit per color, only valid when ucAction = SETUP/ENABLE_OUTPUT and ucEncodeMode= DP
4305   uint8_t  hpd_id;
4306 };
4307 
4308 
4309 // ucAction
4310 enum external_encoder_control_action_def
4311 {
4312   EXTERNAL_ENCODER_ACTION_V3_DISABLE_OUTPUT           = 0x00,
4313   EXTERNAL_ENCODER_ACTION_V3_ENABLE_OUTPUT            = 0x01,
4314   EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT             = 0x07,
4315   EXTERNAL_ENCODER_ACTION_V3_ENCODER_SETUP            = 0x0f,
4316   EXTERNAL_ENCODER_ACTION_V3_ENCODER_BLANKING_OFF     = 0x10,
4317   EXTERNAL_ENCODER_ACTION_V3_ENCODER_BLANKING         = 0x11,
4318   EXTERNAL_ENCODER_ACTION_V3_DACLOAD_DETECTION        = 0x12,
4319   EXTERNAL_ENCODER_ACTION_V3_DDC_SETUP                = 0x14,
4320 };
4321 
4322 // ucConfig
4323 enum external_encoder_control_v2_4_config_def
4324 {
4325   EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_MASK          = 0x03,
4326   EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_1_62GHZ       = 0x00,
4327   EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ       = 0x01,
4328   EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_5_40GHZ       = 0x02,
4329   EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_3_24GHZ       = 0x03,
4330   EXTERNAL_ENCODER_CONFIG_V3_ENCODER_SEL_MAKS         = 0x70,
4331   EXTERNAL_ENCODER_CONFIG_V3_ENCODER1                 = 0x00,
4332   EXTERNAL_ENCODER_CONFIG_V3_ENCODER2                 = 0x10,
4333   EXTERNAL_ENCODER_CONFIG_V3_ENCODER3                 = 0x20,
4334 };
4335 
4336 struct external_encoder_control_ps_allocation_v2_4
4337 {
4338   struct external_encoder_control_parameters_v2_4 sExtEncoder;
4339   uint32_t reserved[2];
4340 };
4341 
4342 
4343 /*
4344   ***************************************************************************
4345                            AMD ACPI Table
4346 
4347   ***************************************************************************
4348 */
4349 
4350 struct amd_acpi_description_header{
4351   uint32_t signature;
4352   uint32_t tableLength;      //Length
4353   uint8_t  revision;
4354   uint8_t  checksum;
4355   uint8_t  oemId[6];
4356   uint8_t  oemTableId[8];    //UINT64  OemTableId;
4357   uint32_t oemRevision;
4358   uint32_t creatorId;
4359   uint32_t creatorRevision;
4360 };
4361 
4362 struct uefi_acpi_vfct{
4363   struct   amd_acpi_description_header sheader;
4364   uint8_t  tableUUID[16];    //0x24
4365   uint32_t vbiosimageoffset; //0x34. Offset to the first GOP_VBIOS_CONTENT block from the beginning of the stucture.
4366   uint32_t lib1Imageoffset;  //0x38. Offset to the first GOP_LIB1_CONTENT block from the beginning of the stucture.
4367   uint32_t reserved[4];      //0x3C
4368 };
4369 
4370 struct vfct_image_header{
4371   uint32_t  pcibus;          //0x4C
4372   uint32_t  pcidevice;       //0x50
4373   uint32_t  pcifunction;     //0x54
4374   uint16_t  vendorid;        //0x58
4375   uint16_t  deviceid;        //0x5A
4376   uint16_t  ssvid;           //0x5C
4377   uint16_t  ssid;            //0x5E
4378   uint32_t  revision;        //0x60
4379   uint32_t  imagelength;     //0x64
4380 };
4381 
4382 
4383 struct gop_vbios_content {
4384   struct vfct_image_header vbiosheader;
4385   uint8_t                  vbioscontent[1];
4386 };
4387 
4388 struct gop_lib1_content {
4389   struct vfct_image_header lib1header;
4390   uint8_t                  lib1content[1];
4391 };
4392 
4393 
4394 
4395 /*
4396   ***************************************************************************
4397                    Scratch Register definitions
4398   Each number below indicates which scratch regiser request, Active and
4399   Connect all share the same definitions as display_device_tag defines
4400   ***************************************************************************
4401 */
4402 
4403 enum scratch_register_def{
4404   ATOM_DEVICE_CONNECT_INFO_DEF      = 0,
4405   ATOM_BL_BRI_LEVEL_INFO_DEF        = 2,
4406   ATOM_ACTIVE_INFO_DEF              = 3,
4407   ATOM_LCD_INFO_DEF                 = 4,
4408   ATOM_DEVICE_REQ_INFO_DEF          = 5,
4409   ATOM_ACC_CHANGE_INFO_DEF          = 6,
4410   ATOM_PRE_OS_MODE_INFO_DEF         = 7,
4411   ATOM_PRE_OS_ASSERTION_DEF      = 8,    //For GOP to record a 32bit assertion code, this is enabled by default in prodution GOP drivers.
4412   ATOM_INTERNAL_TIMER_INFO_DEF      = 10,
4413 };
4414 
4415 enum scratch_device_connect_info_bit_def{
4416   ATOM_DISPLAY_LCD1_CONNECT           =0x0002,
4417   ATOM_DISPLAY_DFP1_CONNECT           =0x0008,
4418   ATOM_DISPLAY_DFP2_CONNECT           =0x0080,
4419   ATOM_DISPLAY_DFP3_CONNECT           =0x0200,
4420   ATOM_DISPLAY_DFP4_CONNECT           =0x0400,
4421   ATOM_DISPLAY_DFP5_CONNECT           =0x0800,
4422   ATOM_DISPLAY_DFP6_CONNECT           =0x0040,
4423   ATOM_DISPLAY_DFPx_CONNECT           =0x0ec8,
4424   ATOM_CONNECT_INFO_DEVICE_MASK       =0x0fff,
4425 };
4426 
4427 enum scratch_bl_bri_level_info_bit_def{
4428   ATOM_CURRENT_BL_LEVEL_SHIFT         =0x8,
4429 #ifndef _H2INC
4430   ATOM_CURRENT_BL_LEVEL_MASK          =0x0000ff00,
4431   ATOM_DEVICE_DPMS_STATE              =0x00010000,
4432 #endif
4433 };
4434 
4435 enum scratch_active_info_bits_def{
4436   ATOM_DISPLAY_LCD1_ACTIVE            =0x0002,
4437   ATOM_DISPLAY_DFP1_ACTIVE            =0x0008,
4438   ATOM_DISPLAY_DFP2_ACTIVE            =0x0080,
4439   ATOM_DISPLAY_DFP3_ACTIVE            =0x0200,
4440   ATOM_DISPLAY_DFP4_ACTIVE            =0x0400,
4441   ATOM_DISPLAY_DFP5_ACTIVE            =0x0800,
4442   ATOM_DISPLAY_DFP6_ACTIVE            =0x0040,
4443   ATOM_ACTIVE_INFO_DEVICE_MASK        =0x0fff,
4444 };
4445 
4446 enum scratch_device_req_info_bits_def{
4447   ATOM_DISPLAY_LCD1_REQ               =0x0002,
4448   ATOM_DISPLAY_DFP1_REQ               =0x0008,
4449   ATOM_DISPLAY_DFP2_REQ               =0x0080,
4450   ATOM_DISPLAY_DFP3_REQ               =0x0200,
4451   ATOM_DISPLAY_DFP4_REQ               =0x0400,
4452   ATOM_DISPLAY_DFP5_REQ               =0x0800,
4453   ATOM_DISPLAY_DFP6_REQ               =0x0040,
4454   ATOM_REQ_INFO_DEVICE_MASK           =0x0fff,
4455 };
4456 
4457 enum scratch_acc_change_info_bitshift_def{
4458   ATOM_ACC_CHANGE_ACC_MODE_SHIFT    =4,
4459   ATOM_ACC_CHANGE_LID_STATUS_SHIFT  =6,
4460 };
4461 
4462 enum scratch_acc_change_info_bits_def{
4463   ATOM_ACC_CHANGE_ACC_MODE          =0x00000010,
4464   ATOM_ACC_CHANGE_LID_STATUS        =0x00000040,
4465 };
4466 
4467 enum scratch_pre_os_mode_info_bits_def{
4468   ATOM_PRE_OS_MODE_MASK             =0x00000003,
4469   ATOM_PRE_OS_MODE_VGA              =0x00000000,
4470   ATOM_PRE_OS_MODE_VESA             =0x00000001,
4471   ATOM_PRE_OS_MODE_GOP              =0x00000002,
4472   ATOM_PRE_OS_MODE_PIXEL_DEPTH      =0x0000000C,
4473   ATOM_PRE_OS_MODE_PIXEL_FORMAT_MASK=0x000000F0,
4474   ATOM_PRE_OS_MODE_8BIT_PAL_EN      =0x00000100,
4475   ATOM_ASIC_INIT_COMPLETE           =0x00000200,
4476 #ifndef _H2INC
4477   ATOM_PRE_OS_MODE_NUMBER_MASK      =0xFFFF0000,
4478 #endif
4479 };
4480 
4481 
4482 
4483 /*
4484   ***************************************************************************
4485                        ATOM firmware ID header file
4486               !! Please keep it at end of the atomfirmware.h !!
4487   ***************************************************************************
4488 */
4489 #include "atomfirmwareid.h"
4490 #pragma pack()
4491 
4492 #endif
4493 
4494