1 /****************************************************************************\ 2 * 3 * File Name atomfirmware.h 4 * Project This is an interface header file between atombios and OS GPU drivers for SoC15 products 5 * 6 * Description header file of general definitions for OS nd pre-OS video drivers 7 * 8 * Copyright 2014 Advanced Micro Devices, Inc. 9 * 10 * Permission is hereby granted, free of charge, to any person obtaining a copy of this software 11 * and associated documentation files (the "Software"), to deal in the Software without restriction, 12 * including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, 13 * and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, 14 * subject to the following conditions: 15 * 16 * The above copyright notice and this permission notice shall be included in all copies or substantial 17 * portions of the Software. 18 * 19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 22 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 23 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 24 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 25 * OTHER DEALINGS IN THE SOFTWARE. 26 * 27 \****************************************************************************/ 28 29 /*IMPORTANT NOTES 30 * If a change in VBIOS/Driver/Tool's interface is only needed for SoC15 and forward products, then the change is only needed in this atomfirmware.h header file. 31 * If a change in VBIOS/Driver/Tool's interface is only needed for pre-SoC15 products, then the change is only needed in atombios.h header file. 32 * If a change is needed for both pre and post SoC15 products, then the change has to be made separately and might be differently in both atomfirmware.h and atombios.h. 33 */ 34 35 #ifndef _ATOMFIRMWARE_H_ 36 #define _ATOMFIRMWARE_H_ 37 38 enum atom_bios_header_version_def{ 39 ATOM_MAJOR_VERSION =0x0003, 40 ATOM_MINOR_VERSION =0x0003, 41 }; 42 43 #ifdef _H2INC 44 #ifndef uint32_t 45 typedef unsigned long uint32_t; 46 #endif 47 48 #ifndef uint16_t 49 typedef unsigned short uint16_t; 50 #endif 51 52 #ifndef uint8_t 53 typedef unsigned char uint8_t; 54 #endif 55 #endif 56 57 enum atom_crtc_def{ 58 ATOM_CRTC1 =0, 59 ATOM_CRTC2 =1, 60 ATOM_CRTC3 =2, 61 ATOM_CRTC4 =3, 62 ATOM_CRTC5 =4, 63 ATOM_CRTC6 =5, 64 ATOM_CRTC_INVALID =0xff, 65 }; 66 67 enum atom_ppll_def{ 68 ATOM_PPLL0 =2, 69 ATOM_GCK_DFS =8, 70 ATOM_FCH_CLK =9, 71 ATOM_DP_DTO =11, 72 ATOM_COMBOPHY_PLL0 =20, 73 ATOM_COMBOPHY_PLL1 =21, 74 ATOM_COMBOPHY_PLL2 =22, 75 ATOM_COMBOPHY_PLL3 =23, 76 ATOM_COMBOPHY_PLL4 =24, 77 ATOM_COMBOPHY_PLL5 =25, 78 ATOM_PPLL_INVALID =0xff, 79 }; 80 81 // define ASIC internal encoder id ( bit vector ), used for CRTC_SourceSel 82 enum atom_dig_def{ 83 ASIC_INT_DIG1_ENCODER_ID =0x03, 84 ASIC_INT_DIG2_ENCODER_ID =0x09, 85 ASIC_INT_DIG3_ENCODER_ID =0x0a, 86 ASIC_INT_DIG4_ENCODER_ID =0x0b, 87 ASIC_INT_DIG5_ENCODER_ID =0x0c, 88 ASIC_INT_DIG6_ENCODER_ID =0x0d, 89 ASIC_INT_DIG7_ENCODER_ID =0x0e, 90 }; 91 92 //ucEncoderMode 93 enum atom_encode_mode_def 94 { 95 ATOM_ENCODER_MODE_DP =0, 96 ATOM_ENCODER_MODE_DP_SST =0, 97 ATOM_ENCODER_MODE_LVDS =1, 98 ATOM_ENCODER_MODE_DVI =2, 99 ATOM_ENCODER_MODE_HDMI =3, 100 ATOM_ENCODER_MODE_DP_AUDIO =5, 101 ATOM_ENCODER_MODE_DP_MST =5, 102 ATOM_ENCODER_MODE_CRT =15, 103 ATOM_ENCODER_MODE_DVO =16, 104 }; 105 106 enum atom_encoder_refclk_src_def{ 107 ENCODER_REFCLK_SRC_P1PLL =0, 108 ENCODER_REFCLK_SRC_P2PLL =1, 109 ENCODER_REFCLK_SRC_P3PLL =2, 110 ENCODER_REFCLK_SRC_EXTCLK =3, 111 ENCODER_REFCLK_SRC_INVALID =0xff, 112 }; 113 114 enum atom_scaler_def{ 115 ATOM_SCALER_DISABLE =0, /*scaler bypass mode, auto-center & no replication*/ 116 ATOM_SCALER_CENTER =1, //For Fudo, it's bypass and auto-center & auto replication 117 ATOM_SCALER_EXPANSION =2, /*scaler expansion by 2 tap alpha blending mode*/ 118 }; 119 120 enum atom_operation_def{ 121 ATOM_DISABLE = 0, 122 ATOM_ENABLE = 1, 123 ATOM_INIT = 7, 124 ATOM_GET_STATUS = 8, 125 }; 126 127 enum atom_embedded_display_op_def{ 128 ATOM_LCD_BL_OFF = 2, 129 ATOM_LCD_BL_OM = 3, 130 ATOM_LCD_BL_BRIGHTNESS_CONTROL = 4, 131 ATOM_LCD_SELFTEST_START = 5, 132 ATOM_LCD_SELFTEST_STOP = 6, 133 }; 134 135 enum atom_spread_spectrum_mode{ 136 ATOM_SS_CENTER_OR_DOWN_MODE_MASK = 0x01, 137 ATOM_SS_DOWN_SPREAD_MODE = 0x00, 138 ATOM_SS_CENTRE_SPREAD_MODE = 0x01, 139 ATOM_INT_OR_EXT_SS_MASK = 0x02, 140 ATOM_INTERNAL_SS_MASK = 0x00, 141 ATOM_EXTERNAL_SS_MASK = 0x02, 142 }; 143 144 /* define panel bit per color */ 145 enum atom_panel_bit_per_color{ 146 PANEL_BPC_UNDEFINE =0x00, 147 PANEL_6BIT_PER_COLOR =0x01, 148 PANEL_8BIT_PER_COLOR =0x02, 149 PANEL_10BIT_PER_COLOR =0x03, 150 PANEL_12BIT_PER_COLOR =0x04, 151 PANEL_16BIT_PER_COLOR =0x05, 152 }; 153 154 //ucVoltageType 155 enum atom_voltage_type 156 { 157 VOLTAGE_TYPE_VDDC = 1, 158 VOLTAGE_TYPE_MVDDC = 2, 159 VOLTAGE_TYPE_MVDDQ = 3, 160 VOLTAGE_TYPE_VDDCI = 4, 161 VOLTAGE_TYPE_VDDGFX = 5, 162 VOLTAGE_TYPE_PCC = 6, 163 VOLTAGE_TYPE_MVPP = 7, 164 VOLTAGE_TYPE_LEDDPM = 8, 165 VOLTAGE_TYPE_PCC_MVDD = 9, 166 VOLTAGE_TYPE_PCIE_VDDC = 10, 167 VOLTAGE_TYPE_PCIE_VDDR = 11, 168 VOLTAGE_TYPE_GENERIC_I2C_1 = 0x11, 169 VOLTAGE_TYPE_GENERIC_I2C_2 = 0x12, 170 VOLTAGE_TYPE_GENERIC_I2C_3 = 0x13, 171 VOLTAGE_TYPE_GENERIC_I2C_4 = 0x14, 172 VOLTAGE_TYPE_GENERIC_I2C_5 = 0x15, 173 VOLTAGE_TYPE_GENERIC_I2C_6 = 0x16, 174 VOLTAGE_TYPE_GENERIC_I2C_7 = 0x17, 175 VOLTAGE_TYPE_GENERIC_I2C_8 = 0x18, 176 VOLTAGE_TYPE_GENERIC_I2C_9 = 0x19, 177 VOLTAGE_TYPE_GENERIC_I2C_10 = 0x1A, 178 }; 179 180 enum atom_dgpu_vram_type { 181 ATOM_DGPU_VRAM_TYPE_GDDR5 = 0x50, 182 ATOM_DGPU_VRAM_TYPE_HBM2 = 0x60, 183 ATOM_DGPU_VRAM_TYPE_HBM2E = 0x61, 184 ATOM_DGPU_VRAM_TYPE_GDDR6 = 0x70, 185 }; 186 187 enum atom_dp_vs_preemph_def{ 188 DP_VS_LEVEL0_PREEMPH_LEVEL0 = 0x00, 189 DP_VS_LEVEL1_PREEMPH_LEVEL0 = 0x01, 190 DP_VS_LEVEL2_PREEMPH_LEVEL0 = 0x02, 191 DP_VS_LEVEL3_PREEMPH_LEVEL0 = 0x03, 192 DP_VS_LEVEL0_PREEMPH_LEVEL1 = 0x08, 193 DP_VS_LEVEL1_PREEMPH_LEVEL1 = 0x09, 194 DP_VS_LEVEL2_PREEMPH_LEVEL1 = 0x0a, 195 DP_VS_LEVEL0_PREEMPH_LEVEL2 = 0x10, 196 DP_VS_LEVEL1_PREEMPH_LEVEL2 = 0x11, 197 DP_VS_LEVEL0_PREEMPH_LEVEL3 = 0x18, 198 }; 199 200 201 /* 202 enum atom_string_def{ 203 asic_bus_type_pcie_string = "PCI_EXPRESS", 204 atom_fire_gl_string = "FGL", 205 atom_bios_string = "ATOM" 206 }; 207 */ 208 209 #pragma pack(1) /* BIOS data must use byte aligment*/ 210 211 enum atombios_image_offset{ 212 OFFSET_TO_ATOM_ROM_HEADER_POINTER =0x00000048, 213 OFFSET_TO_ATOM_ROM_IMAGE_SIZE =0x00000002, 214 OFFSET_TO_ATOMBIOS_ASIC_BUS_MEM_TYPE =0x94, 215 MAXSIZE_OF_ATOMBIOS_ASIC_BUS_MEM_TYPE =20, /*including the terminator 0x0!*/ 216 OFFSET_TO_GET_ATOMBIOS_NUMBER_OF_STRINGS =0x2f, 217 OFFSET_TO_GET_ATOMBIOS_STRING_START =0x6e, 218 }; 219 220 /**************************************************************************** 221 * Common header for all tables (Data table, Command function). 222 * Every table pointed in _ATOM_MASTER_DATA_TABLE has this common header. 223 * And the pointer actually points to this header. 224 ****************************************************************************/ 225 226 struct atom_common_table_header 227 { 228 uint16_t structuresize; 229 uint8_t format_revision; //mainly used for a hw function, when the parser is not backward compatible 230 uint8_t content_revision; //change it when a data table has a structure change, or a hw function has a input/output parameter change 231 }; 232 233 /**************************************************************************** 234 * Structure stores the ROM header. 235 ****************************************************************************/ 236 struct atom_rom_header_v2_2 237 { 238 struct atom_common_table_header table_header; 239 uint8_t atom_bios_string[4]; //enum atom_string_def atom_bios_string; //Signature to distinguish between Atombios and non-atombios, 240 uint16_t bios_segment_address; 241 uint16_t protectedmodeoffset; 242 uint16_t configfilenameoffset; 243 uint16_t crc_block_offset; 244 uint16_t vbios_bootupmessageoffset; 245 uint16_t int10_offset; 246 uint16_t pcibusdevinitcode; 247 uint16_t iobaseaddress; 248 uint16_t subsystem_vendor_id; 249 uint16_t subsystem_id; 250 uint16_t pci_info_offset; 251 uint16_t masterhwfunction_offset; //Offest for SW to get all command function offsets, Don't change the position 252 uint16_t masterdatatable_offset; //Offest for SW to get all data table offsets, Don't change the position 253 uint16_t reserved; 254 uint32_t pspdirtableoffset; 255 }; 256 257 /*==============================hw function portion======================================================================*/ 258 259 260 /**************************************************************************** 261 * Structures used in Command.mtb, each function name is not given here since those function could change from time to time 262 * The real functionality of each function is associated with the parameter structure version when defined 263 * For all internal cmd function definitions, please reference to atomstruct.h 264 ****************************************************************************/ 265 struct atom_master_list_of_command_functions_v2_1{ 266 uint16_t asic_init; //Function 267 uint16_t cmd_function1; //used as an internal one 268 uint16_t cmd_function2; //used as an internal one 269 uint16_t cmd_function3; //used as an internal one 270 uint16_t digxencodercontrol; //Function 271 uint16_t cmd_function5; //used as an internal one 272 uint16_t cmd_function6; //used as an internal one 273 uint16_t cmd_function7; //used as an internal one 274 uint16_t cmd_function8; //used as an internal one 275 uint16_t cmd_function9; //used as an internal one 276 uint16_t setengineclock; //Function 277 uint16_t setmemoryclock; //Function 278 uint16_t setpixelclock; //Function 279 uint16_t enabledisppowergating; //Function 280 uint16_t cmd_function14; //used as an internal one 281 uint16_t cmd_function15; //used as an internal one 282 uint16_t cmd_function16; //used as an internal one 283 uint16_t cmd_function17; //used as an internal one 284 uint16_t cmd_function18; //used as an internal one 285 uint16_t cmd_function19; //used as an internal one 286 uint16_t cmd_function20; //used as an internal one 287 uint16_t cmd_function21; //used as an internal one 288 uint16_t cmd_function22; //used as an internal one 289 uint16_t cmd_function23; //used as an internal one 290 uint16_t cmd_function24; //used as an internal one 291 uint16_t cmd_function25; //used as an internal one 292 uint16_t cmd_function26; //used as an internal one 293 uint16_t cmd_function27; //used as an internal one 294 uint16_t cmd_function28; //used as an internal one 295 uint16_t cmd_function29; //used as an internal one 296 uint16_t cmd_function30; //used as an internal one 297 uint16_t cmd_function31; //used as an internal one 298 uint16_t cmd_function32; //used as an internal one 299 uint16_t cmd_function33; //used as an internal one 300 uint16_t blankcrtc; //Function 301 uint16_t enablecrtc; //Function 302 uint16_t cmd_function36; //used as an internal one 303 uint16_t cmd_function37; //used as an internal one 304 uint16_t cmd_function38; //used as an internal one 305 uint16_t cmd_function39; //used as an internal one 306 uint16_t cmd_function40; //used as an internal one 307 uint16_t getsmuclockinfo; //Function 308 uint16_t selectcrtc_source; //Function 309 uint16_t cmd_function43; //used as an internal one 310 uint16_t cmd_function44; //used as an internal one 311 uint16_t cmd_function45; //used as an internal one 312 uint16_t setdceclock; //Function 313 uint16_t getmemoryclock; //Function 314 uint16_t getengineclock; //Function 315 uint16_t setcrtc_usingdtdtiming; //Function 316 uint16_t externalencodercontrol; //Function 317 uint16_t cmd_function51; //used as an internal one 318 uint16_t cmd_function52; //used as an internal one 319 uint16_t cmd_function53; //used as an internal one 320 uint16_t processi2cchanneltransaction;//Function 321 uint16_t cmd_function55; //used as an internal one 322 uint16_t cmd_function56; //used as an internal one 323 uint16_t cmd_function57; //used as an internal one 324 uint16_t cmd_function58; //used as an internal one 325 uint16_t cmd_function59; //used as an internal one 326 uint16_t computegpuclockparam; //Function 327 uint16_t cmd_function61; //used as an internal one 328 uint16_t cmd_function62; //used as an internal one 329 uint16_t dynamicmemorysettings; //Function function 330 uint16_t memorytraining; //Function function 331 uint16_t cmd_function65; //used as an internal one 332 uint16_t cmd_function66; //used as an internal one 333 uint16_t setvoltage; //Function 334 uint16_t cmd_function68; //used as an internal one 335 uint16_t readefusevalue; //Function 336 uint16_t cmd_function70; //used as an internal one 337 uint16_t cmd_function71; //used as an internal one 338 uint16_t cmd_function72; //used as an internal one 339 uint16_t cmd_function73; //used as an internal one 340 uint16_t cmd_function74; //used as an internal one 341 uint16_t cmd_function75; //used as an internal one 342 uint16_t dig1transmittercontrol; //Function 343 uint16_t cmd_function77; //used as an internal one 344 uint16_t processauxchanneltransaction;//Function 345 uint16_t cmd_function79; //used as an internal one 346 uint16_t getvoltageinfo; //Function 347 }; 348 349 struct atom_master_command_function_v2_1 350 { 351 struct atom_common_table_header table_header; 352 struct atom_master_list_of_command_functions_v2_1 listofcmdfunctions; 353 }; 354 355 /**************************************************************************** 356 * Structures used in every command function 357 ****************************************************************************/ 358 struct atom_function_attribute 359 { 360 uint16_t ws_in_bytes:8; //[7:0]=Size of workspace in Bytes (in multiple of a dword), 361 uint16_t ps_in_bytes:7; //[14:8]=Size of parameter space in Bytes (multiple of a dword), 362 uint16_t updated_by_util:1; //[15]=flag to indicate the function is updated by util 363 }; 364 365 366 /**************************************************************************** 367 * Common header for all hw functions. 368 * Every function pointed by _master_list_of_hw_function has this common header. 369 * And the pointer actually points to this header. 370 ****************************************************************************/ 371 struct atom_rom_hw_function_header 372 { 373 struct atom_common_table_header func_header; 374 struct atom_function_attribute func_attrib; 375 }; 376 377 378 /*==============================sw data table portion======================================================================*/ 379 /**************************************************************************** 380 * Structures used in data.mtb, each data table name is not given here since those data table could change from time to time 381 * The real name of each table is given when its data structure version is defined 382 ****************************************************************************/ 383 struct atom_master_list_of_data_tables_v2_1{ 384 uint16_t utilitypipeline; /* Offest for the utility to get parser info,Don't change this position!*/ 385 uint16_t multimedia_info; 386 uint16_t smc_dpm_info; 387 uint16_t sw_datatable3; 388 uint16_t firmwareinfo; /* Shared by various SW components */ 389 uint16_t sw_datatable5; 390 uint16_t lcd_info; /* Shared by various SW components */ 391 uint16_t sw_datatable7; 392 uint16_t smu_info; 393 uint16_t sw_datatable9; 394 uint16_t sw_datatable10; 395 uint16_t vram_usagebyfirmware; /* Shared by various SW components */ 396 uint16_t gpio_pin_lut; /* Shared by various SW components */ 397 uint16_t sw_datatable13; 398 uint16_t gfx_info; 399 uint16_t powerplayinfo; /* Shared by various SW components */ 400 uint16_t sw_datatable16; 401 uint16_t sw_datatable17; 402 uint16_t sw_datatable18; 403 uint16_t sw_datatable19; 404 uint16_t sw_datatable20; 405 uint16_t sw_datatable21; 406 uint16_t displayobjectinfo; /* Shared by various SW components */ 407 uint16_t indirectioaccess; /* used as an internal one */ 408 uint16_t umc_info; /* Shared by various SW components */ 409 uint16_t sw_datatable25; 410 uint16_t sw_datatable26; 411 uint16_t dce_info; /* Shared by various SW components */ 412 uint16_t vram_info; /* Shared by various SW components */ 413 uint16_t sw_datatable29; 414 uint16_t integratedsysteminfo; /* Shared by various SW components */ 415 uint16_t asic_profiling_info; /* Shared by various SW components */ 416 uint16_t voltageobject_info; /* shared by various SW components */ 417 uint16_t sw_datatable33; 418 uint16_t sw_datatable34; 419 }; 420 421 422 struct atom_master_data_table_v2_1 423 { 424 struct atom_common_table_header table_header; 425 struct atom_master_list_of_data_tables_v2_1 listOfdatatables; 426 }; 427 428 429 struct atom_dtd_format 430 { 431 uint16_t pixclk; 432 uint16_t h_active; 433 uint16_t h_blanking_time; 434 uint16_t v_active; 435 uint16_t v_blanking_time; 436 uint16_t h_sync_offset; 437 uint16_t h_sync_width; 438 uint16_t v_sync_offset; 439 uint16_t v_syncwidth; 440 uint16_t reserved; 441 uint16_t reserved0; 442 uint8_t h_border; 443 uint8_t v_border; 444 uint16_t miscinfo; 445 uint8_t atom_mode_id; 446 uint8_t refreshrate; 447 }; 448 449 /* atom_dtd_format.modemiscinfo defintion */ 450 enum atom_dtd_format_modemiscinfo{ 451 ATOM_HSYNC_POLARITY = 0x0002, 452 ATOM_VSYNC_POLARITY = 0x0004, 453 ATOM_H_REPLICATIONBY2 = 0x0010, 454 ATOM_V_REPLICATIONBY2 = 0x0020, 455 ATOM_INTERLACE = 0x0080, 456 ATOM_COMPOSITESYNC = 0x0040, 457 }; 458 459 460 /* utilitypipeline 461 * when format_revision==1 && content_revision==1, then this an info table for atomworks to use during debug session, no structure is associated with it. 462 * the location of it can't change 463 */ 464 465 466 /* 467 *************************************************************************** 468 Data Table firmwareinfo structure 469 *************************************************************************** 470 */ 471 472 struct atom_firmware_info_v3_1 473 { 474 struct atom_common_table_header table_header; 475 uint32_t firmware_revision; 476 uint32_t bootup_sclk_in10khz; 477 uint32_t bootup_mclk_in10khz; 478 uint32_t firmware_capability; // enum atombios_firmware_capability 479 uint32_t main_call_parser_entry; /* direct address of main parser call in VBIOS binary. */ 480 uint32_t bios_scratch_reg_startaddr; // 1st bios scratch register dword address 481 uint16_t bootup_vddc_mv; 482 uint16_t bootup_vddci_mv; 483 uint16_t bootup_mvddc_mv; 484 uint16_t bootup_vddgfx_mv; 485 uint8_t mem_module_id; 486 uint8_t coolingsolution_id; /*0: Air cooling; 1: Liquid cooling ... */ 487 uint8_t reserved1[2]; 488 uint32_t mc_baseaddr_high; 489 uint32_t mc_baseaddr_low; 490 uint32_t reserved2[6]; 491 }; 492 493 /* Total 32bit cap indication */ 494 enum atombios_firmware_capability 495 { 496 ATOM_FIRMWARE_CAP_FIRMWARE_POSTED = 0x00000001, 497 ATOM_FIRMWARE_CAP_GPU_VIRTUALIZATION = 0x00000002, 498 ATOM_FIRMWARE_CAP_WMI_SUPPORT = 0x00000040, 499 ATOM_FIRMWARE_CAP_HWEMU_ENABLE = 0x00000080, 500 ATOM_FIRMWARE_CAP_HWEMU_UMC_CFG = 0x00000100, 501 ATOM_FIRMWARE_CAP_SRAM_ECC = 0x00000200, 502 ATOM_FIRMWARE_CAP_ENABLE_2STAGE_BIST_TRAINING = 0x00000400, 503 ATOM_FIRMWARE_CAP_ENABLE_2ND_USB20PORT = 0x0008000, 504 }; 505 506 enum atom_cooling_solution_id{ 507 AIR_COOLING = 0x00, 508 LIQUID_COOLING = 0x01 509 }; 510 511 struct atom_firmware_info_v3_2 { 512 struct atom_common_table_header table_header; 513 uint32_t firmware_revision; 514 uint32_t bootup_sclk_in10khz; 515 uint32_t bootup_mclk_in10khz; 516 uint32_t firmware_capability; // enum atombios_firmware_capability 517 uint32_t main_call_parser_entry; /* direct address of main parser call in VBIOS binary. */ 518 uint32_t bios_scratch_reg_startaddr; // 1st bios scratch register dword address 519 uint16_t bootup_vddc_mv; 520 uint16_t bootup_vddci_mv; 521 uint16_t bootup_mvddc_mv; 522 uint16_t bootup_vddgfx_mv; 523 uint8_t mem_module_id; 524 uint8_t coolingsolution_id; /*0: Air cooling; 1: Liquid cooling ... */ 525 uint8_t reserved1[2]; 526 uint32_t mc_baseaddr_high; 527 uint32_t mc_baseaddr_low; 528 uint8_t board_i2c_feature_id; // enum of atom_board_i2c_feature_id_def 529 uint8_t board_i2c_feature_gpio_id; // i2c id find in gpio_lut data table gpio_id 530 uint8_t board_i2c_feature_slave_addr; 531 uint8_t reserved3; 532 uint16_t bootup_mvddq_mv; 533 uint16_t bootup_mvpp_mv; 534 uint32_t zfbstartaddrin16mb; 535 uint32_t reserved2[3]; 536 }; 537 538 struct atom_firmware_info_v3_3 539 { 540 struct atom_common_table_header table_header; 541 uint32_t firmware_revision; 542 uint32_t bootup_sclk_in10khz; 543 uint32_t bootup_mclk_in10khz; 544 uint32_t firmware_capability; // enum atombios_firmware_capability 545 uint32_t main_call_parser_entry; /* direct address of main parser call in VBIOS binary. */ 546 uint32_t bios_scratch_reg_startaddr; // 1st bios scratch register dword address 547 uint16_t bootup_vddc_mv; 548 uint16_t bootup_vddci_mv; 549 uint16_t bootup_mvddc_mv; 550 uint16_t bootup_vddgfx_mv; 551 uint8_t mem_module_id; 552 uint8_t coolingsolution_id; /*0: Air cooling; 1: Liquid cooling ... */ 553 uint8_t reserved1[2]; 554 uint32_t mc_baseaddr_high; 555 uint32_t mc_baseaddr_low; 556 uint8_t board_i2c_feature_id; // enum of atom_board_i2c_feature_id_def 557 uint8_t board_i2c_feature_gpio_id; // i2c id find in gpio_lut data table gpio_id 558 uint8_t board_i2c_feature_slave_addr; 559 uint8_t reserved3; 560 uint16_t bootup_mvddq_mv; 561 uint16_t bootup_mvpp_mv; 562 uint32_t zfbstartaddrin16mb; 563 uint32_t pplib_pptable_id; // if pplib_pptable_id!=0, pplib get powerplay table inside driver instead of from VBIOS 564 uint32_t reserved2[2]; 565 }; 566 567 struct atom_firmware_info_v3_4 { 568 struct atom_common_table_header table_header; 569 uint32_t firmware_revision; 570 uint32_t bootup_sclk_in10khz; 571 uint32_t bootup_mclk_in10khz; 572 uint32_t firmware_capability; // enum atombios_firmware_capability 573 uint32_t main_call_parser_entry; /* direct address of main parser call in VBIOS binary. */ 574 uint32_t bios_scratch_reg_startaddr; // 1st bios scratch register dword address 575 uint16_t bootup_vddc_mv; 576 uint16_t bootup_vddci_mv; 577 uint16_t bootup_mvddc_mv; 578 uint16_t bootup_vddgfx_mv; 579 uint8_t mem_module_id; 580 uint8_t coolingsolution_id; /*0: Air cooling; 1: Liquid cooling ... */ 581 uint8_t reserved1[2]; 582 uint32_t mc_baseaddr_high; 583 uint32_t mc_baseaddr_low; 584 uint8_t board_i2c_feature_id; // enum of atom_board_i2c_feature_id_def 585 uint8_t board_i2c_feature_gpio_id; // i2c id find in gpio_lut data table gpio_id 586 uint8_t board_i2c_feature_slave_addr; 587 uint8_t reserved3; 588 uint16_t bootup_mvddq_mv; 589 uint16_t bootup_mvpp_mv; 590 uint32_t zfbstartaddrin16mb; 591 uint32_t pplib_pptable_id; // if pplib_pptable_id!=0, pplib get powerplay table inside driver instead of from VBIOS 592 uint32_t mvdd_ratio; // mvdd_raio = (real mvdd in power rail)*1000/(mvdd_output_from_svi2) 593 uint16_t hw_bootup_vddgfx_mv; // hw default vddgfx voltage level decide by board strap 594 uint16_t hw_bootup_vddc_mv; // hw default vddc voltage level decide by board strap 595 uint16_t hw_bootup_mvddc_mv; // hw default mvddc voltage level decide by board strap 596 uint16_t hw_bootup_vddci_mv; // hw default vddci voltage level decide by board strap 597 uint32_t maco_pwrlimit_mw; // bomaco mode power limit in unit of m-watt 598 uint32_t usb_pwrlimit_mw; // power limit when USB is enable in unit of m-watt 599 uint32_t fw_reserved_size_in_kb; // VBIOS reserved extra fw size in unit of kb. 600 uint32_t pspbl_init_done_reg_addr; 601 uint32_t pspbl_init_done_value; 602 uint32_t pspbl_init_done_check_timeout; // time out in unit of us when polling pspbl init done 603 uint32_t reserved[2]; 604 }; 605 606 /* 607 *************************************************************************** 608 Data Table lcd_info structure 609 *************************************************************************** 610 */ 611 612 struct lcd_info_v2_1 613 { 614 struct atom_common_table_header table_header; 615 struct atom_dtd_format lcd_timing; 616 uint16_t backlight_pwm; 617 uint16_t special_handle_cap; 618 uint16_t panel_misc; 619 uint16_t lvds_max_slink_pclk; 620 uint16_t lvds_ss_percentage; 621 uint16_t lvds_ss_rate_10hz; 622 uint8_t pwr_on_digon_to_de; /*all pwr sequence numbers below are in uint of 4ms*/ 623 uint8_t pwr_on_de_to_vary_bl; 624 uint8_t pwr_down_vary_bloff_to_de; 625 uint8_t pwr_down_de_to_digoff; 626 uint8_t pwr_off_delay; 627 uint8_t pwr_on_vary_bl_to_blon; 628 uint8_t pwr_down_bloff_to_vary_bloff; 629 uint8_t panel_bpc; 630 uint8_t dpcd_edp_config_cap; 631 uint8_t dpcd_max_link_rate; 632 uint8_t dpcd_max_lane_count; 633 uint8_t dpcd_max_downspread; 634 uint8_t min_allowed_bl_level; 635 uint8_t max_allowed_bl_level; 636 uint8_t bootup_bl_level; 637 uint8_t dplvdsrxid; 638 uint32_t reserved1[8]; 639 }; 640 641 /* lcd_info_v2_1.panel_misc defintion */ 642 enum atom_lcd_info_panel_misc{ 643 ATOM_PANEL_MISC_FPDI =0x0002, 644 }; 645 646 //uceDPToLVDSRxId 647 enum atom_lcd_info_dptolvds_rx_id 648 { 649 eDP_TO_LVDS_RX_DISABLE = 0x00, // no eDP->LVDS translator chip 650 eDP_TO_LVDS_COMMON_ID = 0x01, // common eDP->LVDS translator chip without AMD SW init 651 eDP_TO_LVDS_REALTEK_ID = 0x02, // Realtek tansaltor which require AMD SW init 652 }; 653 654 655 /* 656 *************************************************************************** 657 Data Table gpio_pin_lut structure 658 *************************************************************************** 659 */ 660 661 struct atom_gpio_pin_assignment 662 { 663 uint32_t data_a_reg_index; 664 uint8_t gpio_bitshift; 665 uint8_t gpio_mask_bitshift; 666 uint8_t gpio_id; 667 uint8_t reserved; 668 }; 669 670 /* atom_gpio_pin_assignment.gpio_id definition */ 671 enum atom_gpio_pin_assignment_gpio_id { 672 I2C_HW_LANE_MUX =0x0f, /* only valid when bit7=1 */ 673 I2C_HW_ENGINE_ID_MASK =0x70, /* only valid when bit7=1 */ 674 I2C_HW_CAP =0x80, /*only when the I2C_HW_CAP is set, the pin ID is assigned to an I2C pin pair, otherwise, it's an generic GPIO pin */ 675 676 /* gpio_id pre-define id for multiple usage */ 677 /* GPIO use to control PCIE_VDDC in certain SLT board */ 678 PCIE_VDDC_CONTROL_GPIO_PINID = 56, 679 /* if PP_AC_DC_SWITCH_GPIO_PINID in Gpio_Pin_LutTable, AC/DC swithing feature is enable */ 680 PP_AC_DC_SWITCH_GPIO_PINID = 60, 681 /* VDDC_REGULATOR_VRHOT_GPIO_PINID in Gpio_Pin_LutTable, VRHot feature is enable */ 682 VDDC_VRHOT_GPIO_PINID = 61, 683 /*if VDDC_PCC_GPIO_PINID in GPIO_LUTable, Peak Current Control feature is enabled */ 684 VDDC_PCC_GPIO_PINID = 62, 685 /* Only used on certain SLT/PA board to allow utility to cut Efuse. */ 686 EFUSE_CUT_ENABLE_GPIO_PINID = 63, 687 /* ucGPIO=DRAM_SELF_REFRESH_GPIO_PIND uses for memory self refresh (ucGPIO=0, DRAM self-refresh; ucGPIO= */ 688 DRAM_SELF_REFRESH_GPIO_PINID = 64, 689 /* Thermal interrupt output->system thermal chip GPIO pin */ 690 THERMAL_INT_OUTPUT_GPIO_PINID =65, 691 }; 692 693 694 struct atom_gpio_pin_lut_v2_1 695 { 696 struct atom_common_table_header table_header; 697 /*the real number of this included in the structure is calcualted by using the (whole structure size - the header size)/size of atom_gpio_pin_lut */ 698 struct atom_gpio_pin_assignment gpio_pin[8]; 699 }; 700 701 702 /* 703 *************************************************************************** 704 Data Table vram_usagebyfirmware structure 705 *************************************************************************** 706 */ 707 708 struct vram_usagebyfirmware_v2_1 709 { 710 struct atom_common_table_header table_header; 711 uint32_t start_address_in_kb; 712 uint16_t used_by_firmware_in_kb; 713 uint16_t used_by_driver_in_kb; 714 }; 715 716 717 /* 718 *************************************************************************** 719 Data Table displayobjectinfo structure 720 *************************************************************************** 721 */ 722 723 enum atom_object_record_type_id 724 { 725 ATOM_I2C_RECORD_TYPE =1, 726 ATOM_HPD_INT_RECORD_TYPE =2, 727 ATOM_OBJECT_GPIO_CNTL_RECORD_TYPE =9, 728 ATOM_CONNECTOR_HPDPIN_LUT_RECORD_TYPE =16, 729 ATOM_CONNECTOR_AUXDDC_LUT_RECORD_TYPE =17, 730 ATOM_ENCODER_CAP_RECORD_TYPE=20, 731 ATOM_BRACKET_LAYOUT_RECORD_TYPE=21, 732 ATOM_CONNECTOR_FORCED_TMDS_CAP_RECORD_TYPE=22, 733 ATOM_DISP_CONNECTOR_CAPS_RECORD_TYPE=23, 734 ATOM_RECORD_END_TYPE =0xFF, 735 }; 736 737 struct atom_common_record_header 738 { 739 uint8_t record_type; //An emun to indicate the record type 740 uint8_t record_size; //The size of the whole record in byte 741 }; 742 743 struct atom_i2c_record 744 { 745 struct atom_common_record_header record_header; //record_type = ATOM_I2C_RECORD_TYPE 746 uint8_t i2c_id; 747 uint8_t i2c_slave_addr; //The slave address, it's 0 when the record is attached to connector for DDC 748 }; 749 750 struct atom_hpd_int_record 751 { 752 struct atom_common_record_header record_header; //record_type = ATOM_HPD_INT_RECORD_TYPE 753 uint8_t pin_id; //Corresponding block in GPIO_PIN_INFO table gives the pin info 754 uint8_t plugin_pin_state; 755 }; 756 757 // Bit maps for ATOM_ENCODER_CAP_RECORD.usEncoderCap 758 enum atom_encoder_caps_def 759 { 760 ATOM_ENCODER_CAP_RECORD_HBR2 =0x01, // DP1.2 HBR2 is supported by HW encoder, it is retired in NI. the real meaning from SI is MST_EN 761 ATOM_ENCODER_CAP_RECORD_MST_EN =0x01, // from SI, this bit means DP MST is enable or not. 762 ATOM_ENCODER_CAP_RECORD_HBR2_EN =0x02, // DP1.2 HBR2 setting is qualified and HBR2 can be enabled 763 ATOM_ENCODER_CAP_RECORD_HDMI6Gbps_EN =0x04, // HDMI2.0 6Gbps enable or not. 764 ATOM_ENCODER_CAP_RECORD_HBR3_EN =0x08, // DP1.3 HBR3 is supported by board. 765 ATOM_ENCODER_CAP_RECORD_USB_C_TYPE =0x100, // the DP connector is a USB-C type. 766 }; 767 768 struct atom_encoder_caps_record 769 { 770 struct atom_common_record_header record_header; //record_type = ATOM_ENCODER_CAP_RECORD_TYPE 771 uint32_t encodercaps; 772 }; 773 774 enum atom_connector_caps_def 775 { 776 ATOM_CONNECTOR_CAP_INTERNAL_DISPLAY = 0x01, //a cap bit to indicate that this non-embedded display connector is an internal display 777 ATOM_CONNECTOR_CAP_INTERNAL_DISPLAY_BL = 0x02, //a cap bit to indicate that this internal display requires BL control from GPU, refers to lcd_info for BL PWM freq 778 }; 779 780 struct atom_disp_connector_caps_record 781 { 782 struct atom_common_record_header record_header; 783 uint32_t connectcaps; 784 }; 785 786 //The following generic object gpio pin control record type will replace JTAG_RECORD/FPGA_CONTROL_RECORD/DVI_EXT_INPUT_RECORD above gradually 787 struct atom_gpio_pin_control_pair 788 { 789 uint8_t gpio_id; // GPIO_ID, find the corresponding ID in GPIO_LUT table 790 uint8_t gpio_pinstate; // Pin state showing how to set-up the pin 791 }; 792 793 struct atom_object_gpio_cntl_record 794 { 795 struct atom_common_record_header record_header; 796 uint8_t flag; // Future expnadibility 797 uint8_t number_of_pins; // Number of GPIO pins used to control the object 798 struct atom_gpio_pin_control_pair gpio[1]; // the real gpio pin pair determined by number of pins ucNumberOfPins 799 }; 800 801 //Definitions for GPIO pin state 802 enum atom_gpio_pin_control_pinstate_def 803 { 804 GPIO_PIN_TYPE_INPUT = 0x00, 805 GPIO_PIN_TYPE_OUTPUT = 0x10, 806 GPIO_PIN_TYPE_HW_CONTROL = 0x20, 807 808 //For GPIO_PIN_TYPE_OUTPUT the following is defined 809 GPIO_PIN_OUTPUT_STATE_MASK = 0x01, 810 GPIO_PIN_OUTPUT_STATE_SHIFT = 0, 811 GPIO_PIN_STATE_ACTIVE_LOW = 0x0, 812 GPIO_PIN_STATE_ACTIVE_HIGH = 0x1, 813 }; 814 815 // Indexes to GPIO array in GLSync record 816 // GLSync record is for Frame Lock/Gen Lock feature. 817 enum atom_glsync_record_gpio_index_def 818 { 819 ATOM_GPIO_INDEX_GLSYNC_REFCLK = 0, 820 ATOM_GPIO_INDEX_GLSYNC_HSYNC = 1, 821 ATOM_GPIO_INDEX_GLSYNC_VSYNC = 2, 822 ATOM_GPIO_INDEX_GLSYNC_SWAP_REQ = 3, 823 ATOM_GPIO_INDEX_GLSYNC_SWAP_GNT = 4, 824 ATOM_GPIO_INDEX_GLSYNC_INTERRUPT = 5, 825 ATOM_GPIO_INDEX_GLSYNC_V_RESET = 6, 826 ATOM_GPIO_INDEX_GLSYNC_SWAP_CNTL = 7, 827 ATOM_GPIO_INDEX_GLSYNC_SWAP_SEL = 8, 828 ATOM_GPIO_INDEX_GLSYNC_MAX = 9, 829 }; 830 831 832 struct atom_connector_hpdpin_lut_record //record for ATOM_CONNECTOR_HPDPIN_LUT_RECORD_TYPE 833 { 834 struct atom_common_record_header record_header; 835 uint8_t hpd_pin_map[8]; 836 }; 837 838 struct atom_connector_auxddc_lut_record //record for ATOM_CONNECTOR_AUXDDC_LUT_RECORD_TYPE 839 { 840 struct atom_common_record_header record_header; 841 uint8_t aux_ddc_map[8]; 842 }; 843 844 struct atom_connector_forced_tmds_cap_record 845 { 846 struct atom_common_record_header record_header; 847 // override TMDS capability on this connector when it operate in TMDS mode. usMaxTmdsClkRate = max TMDS Clock in Mhz/2.5 848 uint8_t maxtmdsclkrate_in2_5mhz; 849 uint8_t reserved; 850 }; 851 852 struct atom_connector_layout_info 853 { 854 uint16_t connectorobjid; 855 uint8_t connector_type; 856 uint8_t position; 857 }; 858 859 // define ATOM_CONNECTOR_LAYOUT_INFO.ucConnectorType to describe the display connector size 860 enum atom_connector_layout_info_connector_type_def 861 { 862 CONNECTOR_TYPE_DVI_D = 1, 863 864 CONNECTOR_TYPE_HDMI = 4, 865 CONNECTOR_TYPE_DISPLAY_PORT = 5, 866 CONNECTOR_TYPE_MINI_DISPLAY_PORT = 6, 867 }; 868 869 struct atom_bracket_layout_record 870 { 871 struct atom_common_record_header record_header; 872 uint8_t bracketlen; 873 uint8_t bracketwidth; 874 uint8_t conn_num; 875 uint8_t reserved; 876 struct atom_connector_layout_info conn_info[1]; 877 }; 878 879 enum atom_display_device_tag_def{ 880 ATOM_DISPLAY_LCD1_SUPPORT = 0x0002, //an embedded display is either an LVDS or eDP signal type of display 881 ATOM_DISPLAY_DFP1_SUPPORT = 0x0008, 882 ATOM_DISPLAY_DFP2_SUPPORT = 0x0080, 883 ATOM_DISPLAY_DFP3_SUPPORT = 0x0200, 884 ATOM_DISPLAY_DFP4_SUPPORT = 0x0400, 885 ATOM_DISPLAY_DFP5_SUPPORT = 0x0800, 886 ATOM_DISPLAY_DFP6_SUPPORT = 0x0040, 887 ATOM_DISPLAY_DFPx_SUPPORT = 0x0ec8, 888 }; 889 890 struct atom_display_object_path_v2 891 { 892 uint16_t display_objid; //Connector Object ID or Misc Object ID 893 uint16_t disp_recordoffset; 894 uint16_t encoderobjid; //first encoder closer to the connector, could be either an external or intenal encoder 895 uint16_t extencoderobjid; //2nd encoder after the first encoder, from the connector point of view; 896 uint16_t encoder_recordoffset; 897 uint16_t extencoder_recordoffset; 898 uint16_t device_tag; //a supported device vector, each display path starts with this.the paths are enumerated in the way of priority, a path appears first 899 uint8_t priority_id; 900 uint8_t reserved; 901 }; 902 903 struct display_object_info_table_v1_4 904 { 905 struct atom_common_table_header table_header; 906 uint16_t supporteddevices; 907 uint8_t number_of_path; 908 uint8_t reserved; 909 struct atom_display_object_path_v2 display_path[8]; //the real number of this included in the structure is calculated by using the (whole structure size - the header size- number_of_path)/size of atom_display_object_path 910 }; 911 912 913 /* 914 *************************************************************************** 915 Data Table dce_info structure 916 *************************************************************************** 917 */ 918 struct atom_display_controller_info_v4_1 919 { 920 struct atom_common_table_header table_header; 921 uint32_t display_caps; 922 uint32_t bootup_dispclk_10khz; 923 uint16_t dce_refclk_10khz; 924 uint16_t i2c_engine_refclk_10khz; 925 uint16_t dvi_ss_percentage; // in unit of 0.001% 926 uint16_t dvi_ss_rate_10hz; 927 uint16_t hdmi_ss_percentage; // in unit of 0.001% 928 uint16_t hdmi_ss_rate_10hz; 929 uint16_t dp_ss_percentage; // in unit of 0.001% 930 uint16_t dp_ss_rate_10hz; 931 uint8_t dvi_ss_mode; // enum of atom_spread_spectrum_mode 932 uint8_t hdmi_ss_mode; // enum of atom_spread_spectrum_mode 933 uint8_t dp_ss_mode; // enum of atom_spread_spectrum_mode 934 uint8_t ss_reserved; 935 uint8_t hardcode_mode_num; // a hardcode mode number defined in StandardVESA_TimingTable when a CRT or DFP EDID is not available 936 uint8_t reserved1[3]; 937 uint16_t dpphy_refclk_10khz; 938 uint16_t reserved2; 939 uint8_t dceip_min_ver; 940 uint8_t dceip_max_ver; 941 uint8_t max_disp_pipe_num; 942 uint8_t max_vbios_active_disp_pipe_num; 943 uint8_t max_ppll_num; 944 uint8_t max_disp_phy_num; 945 uint8_t max_aux_pairs; 946 uint8_t remotedisplayconfig; 947 uint8_t reserved3[8]; 948 }; 949 950 struct atom_display_controller_info_v4_2 951 { 952 struct atom_common_table_header table_header; 953 uint32_t display_caps; 954 uint32_t bootup_dispclk_10khz; 955 uint16_t dce_refclk_10khz; 956 uint16_t i2c_engine_refclk_10khz; 957 uint16_t dvi_ss_percentage; // in unit of 0.001% 958 uint16_t dvi_ss_rate_10hz; 959 uint16_t hdmi_ss_percentage; // in unit of 0.001% 960 uint16_t hdmi_ss_rate_10hz; 961 uint16_t dp_ss_percentage; // in unit of 0.001% 962 uint16_t dp_ss_rate_10hz; 963 uint8_t dvi_ss_mode; // enum of atom_spread_spectrum_mode 964 uint8_t hdmi_ss_mode; // enum of atom_spread_spectrum_mode 965 uint8_t dp_ss_mode; // enum of atom_spread_spectrum_mode 966 uint8_t ss_reserved; 967 uint8_t dfp_hardcode_mode_num; // DFP hardcode mode number defined in StandardVESA_TimingTable when EDID is not available 968 uint8_t dfp_hardcode_refreshrate;// DFP hardcode mode refreshrate defined in StandardVESA_TimingTable when EDID is not available 969 uint8_t vga_hardcode_mode_num; // VGA hardcode mode number defined in StandardVESA_TimingTable when EDID is not avablable 970 uint8_t vga_hardcode_refreshrate;// VGA hardcode mode number defined in StandardVESA_TimingTable when EDID is not avablable 971 uint16_t dpphy_refclk_10khz; 972 uint16_t reserved2; 973 uint8_t dcnip_min_ver; 974 uint8_t dcnip_max_ver; 975 uint8_t max_disp_pipe_num; 976 uint8_t max_vbios_active_disp_pipe_num; 977 uint8_t max_ppll_num; 978 uint8_t max_disp_phy_num; 979 uint8_t max_aux_pairs; 980 uint8_t remotedisplayconfig; 981 uint8_t reserved3[8]; 982 }; 983 984 struct atom_display_controller_info_v4_4 { 985 struct atom_common_table_header table_header; 986 uint32_t display_caps; 987 uint32_t bootup_dispclk_10khz; 988 uint16_t dce_refclk_10khz; 989 uint16_t i2c_engine_refclk_10khz; 990 uint16_t dvi_ss_percentage; // in unit of 0.001% 991 uint16_t dvi_ss_rate_10hz; 992 uint16_t hdmi_ss_percentage; // in unit of 0.001% 993 uint16_t hdmi_ss_rate_10hz; 994 uint16_t dp_ss_percentage; // in unit of 0.001% 995 uint16_t dp_ss_rate_10hz; 996 uint8_t dvi_ss_mode; // enum of atom_spread_spectrum_mode 997 uint8_t hdmi_ss_mode; // enum of atom_spread_spectrum_mode 998 uint8_t dp_ss_mode; // enum of atom_spread_spectrum_mode 999 uint8_t ss_reserved; 1000 uint8_t dfp_hardcode_mode_num; // DFP hardcode mode number defined in StandardVESA_TimingTable when EDID is not available 1001 uint8_t dfp_hardcode_refreshrate;// DFP hardcode mode refreshrate defined in StandardVESA_TimingTable when EDID is not available 1002 uint8_t vga_hardcode_mode_num; // VGA hardcode mode number defined in StandardVESA_TimingTable when EDID is not avablable 1003 uint8_t vga_hardcode_refreshrate;// VGA hardcode mode number defined in StandardVESA_TimingTable when EDID is not avablable 1004 uint16_t dpphy_refclk_10khz; 1005 uint16_t hw_chip_id; 1006 uint8_t dcnip_min_ver; 1007 uint8_t dcnip_max_ver; 1008 uint8_t max_disp_pipe_num; 1009 uint8_t max_vbios_active_disp_pipum; 1010 uint8_t max_ppll_num; 1011 uint8_t max_disp_phy_num; 1012 uint8_t max_aux_pairs; 1013 uint8_t remotedisplayconfig; 1014 uint32_t dispclk_pll_vco_freq; 1015 uint32_t dp_ref_clk_freq; 1016 uint32_t max_mclk_chg_lat; // Worst case blackout duration for a memory clock frequency (p-state) change, units of 100s of ns (0.1 us) 1017 uint32_t max_sr_exit_lat; // Worst case memory self refresh exit time, units of 100ns of ns (0.1us) 1018 uint32_t max_sr_enter_exit_lat; // Worst case memory self refresh entry followed by immediate exit time, units of 100ns of ns (0.1us) 1019 uint16_t dc_golden_table_offset; // point of struct of atom_dc_golden_table_vxx 1020 uint16_t dc_golden_table_ver; 1021 uint32_t reserved3[3]; 1022 }; 1023 1024 struct atom_dc_golden_table_v1 1025 { 1026 uint32_t aux_dphy_rx_control0_val; 1027 uint32_t aux_dphy_tx_control_val; 1028 uint32_t aux_dphy_rx_control1_val; 1029 uint32_t dc_gpio_aux_ctrl_0_val; 1030 uint32_t dc_gpio_aux_ctrl_1_val; 1031 uint32_t dc_gpio_aux_ctrl_2_val; 1032 uint32_t dc_gpio_aux_ctrl_3_val; 1033 uint32_t dc_gpio_aux_ctrl_4_val; 1034 uint32_t dc_gpio_aux_ctrl_5_val; 1035 uint32_t reserved[23]; 1036 }; 1037 1038 enum dce_info_caps_def 1039 { 1040 // only for VBIOS 1041 DCE_INFO_CAPS_FORCE_DISPDEV_CONNECTED =0x02, 1042 // only for VBIOS 1043 DCE_INFO_CAPS_DISABLE_DFP_DP_HBR2 =0x04, 1044 // only for VBIOS 1045 DCE_INFO_CAPS_ENABLE_INTERLAC_TIMING =0x08, 1046 1047 }; 1048 1049 /* 1050 *************************************************************************** 1051 Data Table ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO structure 1052 *************************************************************************** 1053 */ 1054 struct atom_ext_display_path 1055 { 1056 uint16_t device_tag; //A bit vector to show what devices are supported 1057 uint16_t device_acpi_enum; //16bit device ACPI id. 1058 uint16_t connectorobjid; //A physical connector for displays to plug in, using object connector definitions 1059 uint8_t auxddclut_index; //An index into external AUX/DDC channel LUT 1060 uint8_t hpdlut_index; //An index into external HPD pin LUT 1061 uint16_t ext_encoder_objid; //external encoder object id 1062 uint8_t channelmapping; // if ucChannelMapping=0, using default one to one mapping 1063 uint8_t chpninvert; // bit vector for up to 8 lanes, =0: P and N is not invert, =1 P and N is inverted 1064 uint16_t caps; 1065 uint16_t reserved; 1066 }; 1067 1068 //usCaps 1069 enum ext_display_path_cap_def { 1070 EXT_DISPLAY_PATH_CAPS__HBR2_DISABLE = 0x0001, 1071 EXT_DISPLAY_PATH_CAPS__DP_FIXED_VS_EN = 0x0002, 1072 EXT_DISPLAY_PATH_CAPS__EXT_CHIP_MASK = 0x007C, 1073 EXT_DISPLAY_PATH_CAPS__HDMI20_PI3EQX1204 = (0x01 << 2), //PI redriver chip 1074 EXT_DISPLAY_PATH_CAPS__HDMI20_TISN65DP159RSBT = (0x02 << 2), //TI retimer chip 1075 EXT_DISPLAY_PATH_CAPS__HDMI20_PARADE_PS175 = (0x03 << 2) //Parade DP->HDMI recoverter chip 1076 }; 1077 1078 struct atom_external_display_connection_info 1079 { 1080 struct atom_common_table_header table_header; 1081 uint8_t guid[16]; // a GUID is a 16 byte long string 1082 struct atom_ext_display_path path[7]; // total of fixed 7 entries. 1083 uint8_t checksum; // a simple Checksum of the sum of whole structure equal to 0x0. 1084 uint8_t stereopinid; // use for eDP panel 1085 uint8_t remotedisplayconfig; 1086 uint8_t edptolvdsrxid; 1087 uint8_t fixdpvoltageswing; // usCaps[1]=1, this indicate DP_LANE_SET value 1088 uint8_t reserved[3]; // for potential expansion 1089 }; 1090 1091 /* 1092 *************************************************************************** 1093 Data Table integratedsysteminfo structure 1094 *************************************************************************** 1095 */ 1096 1097 struct atom_camera_dphy_timing_param 1098 { 1099 uint8_t profile_id; // SENSOR_PROFILES 1100 uint32_t param; 1101 }; 1102 1103 struct atom_camera_dphy_elec_param 1104 { 1105 uint16_t param[3]; 1106 }; 1107 1108 struct atom_camera_module_info 1109 { 1110 uint8_t module_id; // 0: Rear, 1: Front right of user, 2: Front left of user 1111 uint8_t module_name[8]; 1112 struct atom_camera_dphy_timing_param timingparam[6]; // Exact number is under estimation and confirmation from sensor vendor 1113 }; 1114 1115 struct atom_camera_flashlight_info 1116 { 1117 uint8_t flashlight_id; // 0: Rear, 1: Front 1118 uint8_t name[8]; 1119 }; 1120 1121 struct atom_camera_data 1122 { 1123 uint32_t versionCode; 1124 struct atom_camera_module_info cameraInfo[3]; // Assuming 3 camera sensors max 1125 struct atom_camera_flashlight_info flashInfo; // Assuming 1 flashlight max 1126 struct atom_camera_dphy_elec_param dphy_param; 1127 uint32_t crc_val; // CRC 1128 }; 1129 1130 1131 struct atom_14nm_dpphy_dvihdmi_tuningset 1132 { 1133 uint32_t max_symclk_in10khz; 1134 uint8_t encoder_mode; //atom_encode_mode_def, =2: DVI, =3: HDMI mode 1135 uint8_t phy_sel; //bit vector of phy, bit0= phya, bit1=phyb, ....bit5 = phyf 1136 uint16_t margindeemph; //COMMON_MAR_DEEMPH_NOM[7:0]tx_margin_nom [15:8]deemph_gen1_nom 1137 uint8_t deemph_6db_4; //COMMON_SELDEEMPH60[31:24]deemph_6db_4 1138 uint8_t boostadj; //CMD_BUS_GLOBAL_FOR_TX_LANE0 [19:16]tx_boost_adj [20]tx_boost_en [23:22]tx_binary_ron_code_offset 1139 uint8_t tx_driver_fifty_ohms; //COMMON_ZCALCODE_CTRL[21].tx_driver_fifty_ohms 1140 uint8_t deemph_sel; //MARGIN_DEEMPH_LANE0.DEEMPH_SEL 1141 }; 1142 1143 struct atom_14nm_dpphy_dp_setting{ 1144 uint8_t dp_vs_pemph_level; //enum of atom_dp_vs_preemph_def 1145 uint16_t margindeemph; //COMMON_MAR_DEEMPH_NOM[7:0]tx_margin_nom [15:8]deemph_gen1_nom 1146 uint8_t deemph_6db_4; //COMMON_SELDEEMPH60[31:24]deemph_6db_4 1147 uint8_t boostadj; //CMD_BUS_GLOBAL_FOR_TX_LANE0 [19:16]tx_boost_adj [20]tx_boost_en [23:22]tx_binary_ron_code_offset 1148 }; 1149 1150 struct atom_14nm_dpphy_dp_tuningset{ 1151 uint8_t phy_sel; // bit vector of phy, bit0= phya, bit1=phyb, ....bit5 = phyf 1152 uint8_t version; 1153 uint16_t table_size; // size of atom_14nm_dpphy_dp_tuningset 1154 uint16_t reserved; 1155 struct atom_14nm_dpphy_dp_setting dptuning[10]; 1156 }; 1157 1158 struct atom_14nm_dig_transmitter_info_header_v4_0{ 1159 struct atom_common_table_header table_header; 1160 uint16_t pcie_phy_tmds_hdmi_macro_settings_offset; // offset of PCIEPhyTMDSHDMIMacroSettingsTbl 1161 uint16_t uniphy_vs_emph_lookup_table_offset; // offset of UniphyVSEmphLookUpTbl 1162 uint16_t uniphy_xbar_settings_table_offset; // offset of UniphyXbarSettingsTbl 1163 }; 1164 1165 struct atom_14nm_combphy_tmds_vs_set 1166 { 1167 uint8_t sym_clk; 1168 uint8_t dig_mode; 1169 uint8_t phy_sel; 1170 uint16_t common_mar_deemph_nom__margin_deemph_val; 1171 uint8_t common_seldeemph60__deemph_6db_4_val; 1172 uint8_t cmd_bus_global_for_tx_lane0__boostadj_val ; 1173 uint8_t common_zcalcode_ctrl__tx_driver_fifty_ohms_val; 1174 uint8_t margin_deemph_lane0__deemph_sel_val; 1175 }; 1176 1177 struct atom_DCN_dpphy_dvihdmi_tuningset 1178 { 1179 uint32_t max_symclk_in10khz; 1180 uint8_t encoder_mode; //atom_encode_mode_def, =2: DVI, =3: HDMI mode 1181 uint8_t phy_sel; //bit vector of phy, bit0= phya, bit1=phyb, ....bit5 = phyf 1182 uint8_t tx_eq_main; // map to RDPCSTX_PHY_FUSE0/1/2/3[5:0](EQ_MAIN) 1183 uint8_t tx_eq_pre; // map to RDPCSTX_PHY_FUSE0/1/2/3[11:6](EQ_PRE) 1184 uint8_t tx_eq_post; // map to RDPCSTX_PHY_FUSE0/1/2/3[17:12](EQ_POST) 1185 uint8_t reserved1; 1186 uint8_t tx_vboost_lvl; // tx_vboost_lvl, map to RDPCSTX_PHY_CNTL0.RDPCS_PHY_TX_VBOOST_LVL 1187 uint8_t reserved2; 1188 }; 1189 1190 struct atom_DCN_dpphy_dp_setting{ 1191 uint8_t dp_vs_pemph_level; //enum of atom_dp_vs_preemph_def 1192 uint8_t tx_eq_main; // map to RDPCSTX_PHY_FUSE0/1/2/3[5:0](EQ_MAIN) 1193 uint8_t tx_eq_pre; // map to RDPCSTX_PHY_FUSE0/1/2/3[11:6](EQ_PRE) 1194 uint8_t tx_eq_post; // map to RDPCSTX_PHY_FUSE0/1/2/3[17:12](EQ_POST) 1195 uint8_t tx_vboost_lvl; // tx_vboost_lvl, map to RDPCSTX_PHY_CNTL0.RDPCS_PHY_TX_VBOOST_LVL 1196 }; 1197 1198 struct atom_DCN_dpphy_dp_tuningset{ 1199 uint8_t phy_sel; // bit vector of phy, bit0= phya, bit1=phyb, ....bit5 = phyf 1200 uint8_t version; 1201 uint16_t table_size; // size of atom_14nm_dpphy_dp_setting 1202 uint16_t reserved; 1203 struct atom_DCN_dpphy_dp_setting dptunings[10]; 1204 }; 1205 1206 struct atom_i2c_reg_info { 1207 uint8_t ucI2cRegIndex; 1208 uint8_t ucI2cRegVal; 1209 }; 1210 1211 struct atom_hdmi_retimer_redriver_set { 1212 uint8_t HdmiSlvAddr; 1213 uint8_t HdmiRegNum; 1214 uint8_t Hdmi6GRegNum; 1215 struct atom_i2c_reg_info HdmiRegSetting[9]; //For non 6G Hz use 1216 struct atom_i2c_reg_info Hdmi6GhzRegSetting[3]; //For 6G Hz use. 1217 }; 1218 1219 struct atom_integrated_system_info_v1_11 1220 { 1221 struct atom_common_table_header table_header; 1222 uint32_t vbios_misc; //enum of atom_system_vbiosmisc_def 1223 uint32_t gpucapinfo; //enum of atom_system_gpucapinf_def 1224 uint32_t system_config; 1225 uint32_t cpucapinfo; 1226 uint16_t gpuclk_ss_percentage; //unit of 0.001%, 1000 mean 1% 1227 uint16_t gpuclk_ss_type; 1228 uint16_t lvds_ss_percentage; //unit of 0.001%, 1000 mean 1% 1229 uint16_t lvds_ss_rate_10hz; 1230 uint16_t hdmi_ss_percentage; //unit of 0.001%, 1000 mean 1% 1231 uint16_t hdmi_ss_rate_10hz; 1232 uint16_t dvi_ss_percentage; //unit of 0.001%, 1000 mean 1% 1233 uint16_t dvi_ss_rate_10hz; 1234 uint16_t dpphy_override; // bit vector, enum of atom_sysinfo_dpphy_override_def 1235 uint16_t lvds_misc; // enum of atom_sys_info_lvds_misc_def 1236 uint16_t backlight_pwm_hz; // pwm frequency in hz 1237 uint8_t memorytype; // enum of atom_dmi_t17_mem_type_def, APU memory type indication. 1238 uint8_t umachannelnumber; // number of memory channels 1239 uint8_t pwr_on_digon_to_de; /* all pwr sequence numbers below are in uint of 4ms */ 1240 uint8_t pwr_on_de_to_vary_bl; 1241 uint8_t pwr_down_vary_bloff_to_de; 1242 uint8_t pwr_down_de_to_digoff; 1243 uint8_t pwr_off_delay; 1244 uint8_t pwr_on_vary_bl_to_blon; 1245 uint8_t pwr_down_bloff_to_vary_bloff; 1246 uint8_t min_allowed_bl_level; 1247 uint8_t htc_hyst_limit; 1248 uint8_t htc_tmp_limit; 1249 uint8_t reserved1; 1250 uint8_t reserved2; 1251 struct atom_external_display_connection_info extdispconninfo; 1252 struct atom_14nm_dpphy_dvihdmi_tuningset dvi_tuningset; 1253 struct atom_14nm_dpphy_dvihdmi_tuningset hdmi_tuningset; 1254 struct atom_14nm_dpphy_dvihdmi_tuningset hdmi6g_tuningset; 1255 struct atom_14nm_dpphy_dp_tuningset dp_tuningset; // rbr 1.62G dp tuning set 1256 struct atom_14nm_dpphy_dp_tuningset dp_hbr3_tuningset; // HBR3 dp tuning set 1257 struct atom_camera_data camera_info; 1258 struct atom_hdmi_retimer_redriver_set dp0_retimer_set; //for DP0 1259 struct atom_hdmi_retimer_redriver_set dp1_retimer_set; //for DP1 1260 struct atom_hdmi_retimer_redriver_set dp2_retimer_set; //for DP2 1261 struct atom_hdmi_retimer_redriver_set dp3_retimer_set; //for DP3 1262 struct atom_14nm_dpphy_dp_tuningset dp_hbr_tuningset; //hbr 2.7G dp tuning set 1263 struct atom_14nm_dpphy_dp_tuningset dp_hbr2_tuningset; //hbr2 5.4G dp turnig set 1264 struct atom_14nm_dpphy_dp_tuningset edp_tuningset; //edp tuning set 1265 uint32_t reserved[66]; 1266 }; 1267 1268 struct atom_integrated_system_info_v1_12 1269 { 1270 struct atom_common_table_header table_header; 1271 uint32_t vbios_misc; //enum of atom_system_vbiosmisc_def 1272 uint32_t gpucapinfo; //enum of atom_system_gpucapinf_def 1273 uint32_t system_config; 1274 uint32_t cpucapinfo; 1275 uint16_t gpuclk_ss_percentage; //unit of 0.001%, 1000 mean 1% 1276 uint16_t gpuclk_ss_type; 1277 uint16_t lvds_ss_percentage; //unit of 0.001%, 1000 mean 1% 1278 uint16_t lvds_ss_rate_10hz; 1279 uint16_t hdmi_ss_percentage; //unit of 0.001%, 1000 mean 1% 1280 uint16_t hdmi_ss_rate_10hz; 1281 uint16_t dvi_ss_percentage; //unit of 0.001%, 1000 mean 1% 1282 uint16_t dvi_ss_rate_10hz; 1283 uint16_t dpphy_override; // bit vector, enum of atom_sysinfo_dpphy_override_def 1284 uint16_t lvds_misc; // enum of atom_sys_info_lvds_misc_def 1285 uint16_t backlight_pwm_hz; // pwm frequency in hz 1286 uint8_t memorytype; // enum of atom_dmi_t17_mem_type_def, APU memory type indication. 1287 uint8_t umachannelnumber; // number of memory channels 1288 uint8_t pwr_on_digon_to_de; // all pwr sequence numbers below are in uint of 4ms // 1289 uint8_t pwr_on_de_to_vary_bl; 1290 uint8_t pwr_down_vary_bloff_to_de; 1291 uint8_t pwr_down_de_to_digoff; 1292 uint8_t pwr_off_delay; 1293 uint8_t pwr_on_vary_bl_to_blon; 1294 uint8_t pwr_down_bloff_to_vary_bloff; 1295 uint8_t min_allowed_bl_level; 1296 uint8_t htc_hyst_limit; 1297 uint8_t htc_tmp_limit; 1298 uint8_t reserved1; 1299 uint8_t reserved2; 1300 struct atom_external_display_connection_info extdispconninfo; 1301 struct atom_DCN_dpphy_dvihdmi_tuningset TMDS_tuningset; 1302 struct atom_DCN_dpphy_dvihdmi_tuningset hdmiCLK5_tuningset; 1303 struct atom_DCN_dpphy_dvihdmi_tuningset hdmiCLK8_tuningset; 1304 struct atom_DCN_dpphy_dp_tuningset rbr_tuningset; // rbr 1.62G dp tuning set 1305 struct atom_DCN_dpphy_dp_tuningset hbr3_tuningset; // HBR3 dp tuning set 1306 struct atom_camera_data camera_info; 1307 struct atom_hdmi_retimer_redriver_set dp0_retimer_set; //for DP0 1308 struct atom_hdmi_retimer_redriver_set dp1_retimer_set; //for DP1 1309 struct atom_hdmi_retimer_redriver_set dp2_retimer_set; //for DP2 1310 struct atom_hdmi_retimer_redriver_set dp3_retimer_set; //for DP3 1311 struct atom_DCN_dpphy_dp_tuningset hbr_tuningset; //hbr 2.7G dp tuning set 1312 struct atom_DCN_dpphy_dp_tuningset hbr2_tuningset; //hbr2 5.4G dp turnig set 1313 struct atom_DCN_dpphy_dp_tuningset edp_tunings; //edp tuning set 1314 struct atom_DCN_dpphy_dvihdmi_tuningset hdmiCLK6_tuningset; 1315 uint32_t reserved[63]; 1316 }; 1317 1318 struct edp_info_table 1319 { 1320 uint16_t edp_backlight_pwm_hz; 1321 uint16_t edp_ss_percentage; 1322 uint16_t edp_ss_rate_10hz; 1323 uint16_t reserved1; 1324 uint32_t reserved2; 1325 uint8_t edp_pwr_on_off_delay; 1326 uint8_t edp_pwr_on_vary_bl_to_blon; 1327 uint8_t edp_pwr_down_bloff_to_vary_bloff; 1328 uint8_t edp_panel_bpc; 1329 uint8_t edp_bootup_bl_level; 1330 uint8_t reserved3[3]; 1331 uint32_t reserved4[3]; 1332 }; 1333 1334 struct atom_integrated_system_info_v2_1 1335 { 1336 struct atom_common_table_header table_header; 1337 uint32_t vbios_misc; //enum of atom_system_vbiosmisc_def 1338 uint32_t gpucapinfo; //enum of atom_system_gpucapinf_def 1339 uint32_t system_config; 1340 uint32_t cpucapinfo; 1341 uint16_t gpuclk_ss_percentage; //unit of 0.001%, 1000 mean 1% 1342 uint16_t gpuclk_ss_type; 1343 uint16_t dpphy_override; // bit vector, enum of atom_sysinfo_dpphy_override_def 1344 uint8_t memorytype; // enum of atom_dmi_t17_mem_type_def, APU memory type indication. 1345 uint8_t umachannelnumber; // number of memory channels 1346 uint8_t htc_hyst_limit; 1347 uint8_t htc_tmp_limit; 1348 uint8_t reserved1; 1349 uint8_t reserved2; 1350 struct edp_info_table edp1_info; 1351 struct edp_info_table edp2_info; 1352 uint32_t reserved3[8]; 1353 struct atom_external_display_connection_info extdispconninfo; 1354 struct atom_DCN_dpphy_dvihdmi_tuningset TMDS_tuningset; 1355 struct atom_DCN_dpphy_dvihdmi_tuningset hdmiCLK5_tuningset; //add clk6 1356 struct atom_DCN_dpphy_dvihdmi_tuningset hdmiCLK6_tuningset; 1357 struct atom_DCN_dpphy_dvihdmi_tuningset hdmiCLK8_tuningset; 1358 uint32_t reserved4[6];//reserve 2*sizeof(atom_DCN_dpphy_dvihdmi_tuningset) 1359 struct atom_DCN_dpphy_dp_tuningset rbr_tuningset; // rbr 1.62G dp tuning set 1360 struct atom_DCN_dpphy_dp_tuningset hbr_tuningset; //hbr 2.7G dp tuning set 1361 struct atom_DCN_dpphy_dp_tuningset hbr2_tuningset; //hbr2 5.4G dp turnig set 1362 struct atom_DCN_dpphy_dp_tuningset hbr3_tuningset; // HBR3 dp tuning set 1363 struct atom_DCN_dpphy_dp_tuningset edp_tunings; //edp tuning set 1364 uint32_t reserved5[28];//reserve 2*sizeof(atom_DCN_dpphy_dp_tuningset) 1365 struct atom_hdmi_retimer_redriver_set dp0_retimer_set; //for DP0 1366 struct atom_hdmi_retimer_redriver_set dp1_retimer_set; //for DP1 1367 struct atom_hdmi_retimer_redriver_set dp2_retimer_set; //for DP2 1368 struct atom_hdmi_retimer_redriver_set dp3_retimer_set; //for DP3 1369 uint32_t reserved6[30];// reserve size of(atom_camera_data) for camera_info 1370 uint32_t reserved7[32]; 1371 1372 }; 1373 1374 // system_config 1375 enum atom_system_vbiosmisc_def{ 1376 INTEGRATED_SYSTEM_INFO__GET_EDID_CALLBACK_FUNC_SUPPORT = 0x01, 1377 }; 1378 1379 1380 // gpucapinfo 1381 enum atom_system_gpucapinf_def{ 1382 SYS_INFO_GPUCAPS__ENABEL_DFS_BYPASS = 0x10, 1383 }; 1384 1385 //dpphy_override 1386 enum atom_sysinfo_dpphy_override_def{ 1387 ATOM_ENABLE_DVI_TUNINGSET = 0x01, 1388 ATOM_ENABLE_HDMI_TUNINGSET = 0x02, 1389 ATOM_ENABLE_HDMI6G_TUNINGSET = 0x04, 1390 ATOM_ENABLE_DP_TUNINGSET = 0x08, 1391 ATOM_ENABLE_DP_HBR3_TUNINGSET = 0x10, 1392 }; 1393 1394 //lvds_misc 1395 enum atom_sys_info_lvds_misc_def 1396 { 1397 SYS_INFO_LVDS_MISC_888_FPDI_MODE =0x01, 1398 SYS_INFO_LVDS_MISC_888_BPC_MODE =0x04, 1399 SYS_INFO_LVDS_MISC_OVERRIDE_EN =0x08, 1400 }; 1401 1402 1403 //memorytype DMI Type 17 offset 12h - Memory Type 1404 enum atom_dmi_t17_mem_type_def{ 1405 OtherMemType = 0x01, ///< Assign 01 to Other 1406 UnknownMemType, ///< Assign 02 to Unknown 1407 DramMemType, ///< Assign 03 to DRAM 1408 EdramMemType, ///< Assign 04 to EDRAM 1409 VramMemType, ///< Assign 05 to VRAM 1410 SramMemType, ///< Assign 06 to SRAM 1411 RamMemType, ///< Assign 07 to RAM 1412 RomMemType, ///< Assign 08 to ROM 1413 FlashMemType, ///< Assign 09 to Flash 1414 EepromMemType, ///< Assign 10 to EEPROM 1415 FepromMemType, ///< Assign 11 to FEPROM 1416 EpromMemType, ///< Assign 12 to EPROM 1417 CdramMemType, ///< Assign 13 to CDRAM 1418 ThreeDramMemType, ///< Assign 14 to 3DRAM 1419 SdramMemType, ///< Assign 15 to SDRAM 1420 SgramMemType, ///< Assign 16 to SGRAM 1421 RdramMemType, ///< Assign 17 to RDRAM 1422 DdrMemType, ///< Assign 18 to DDR 1423 Ddr2MemType, ///< Assign 19 to DDR2 1424 Ddr2FbdimmMemType, ///< Assign 20 to DDR2 FB-DIMM 1425 Ddr3MemType = 0x18, ///< Assign 24 to DDR3 1426 Fbd2MemType, ///< Assign 25 to FBD2 1427 Ddr4MemType, ///< Assign 26 to DDR4 1428 LpDdrMemType, ///< Assign 27 to LPDDR 1429 LpDdr2MemType, ///< Assign 28 to LPDDR2 1430 LpDdr3MemType, ///< Assign 29 to LPDDR3 1431 LpDdr4MemType, ///< Assign 30 to LPDDR4 1432 GDdr6MemType, ///< Assign 31 to GDDR6 1433 HbmMemType, ///< Assign 32 to HBM 1434 Hbm2MemType, ///< Assign 33 to HBM2 1435 Ddr5MemType, ///< Assign 34 to DDR5 1436 LpDdr5MemType, ///< Assign 35 to LPDDR5 1437 }; 1438 1439 1440 // this Table is used starting from NL/AM, used by SBIOS and pass the IntegratedSystemInfoTable/PowerPlayInfoTable/SystemCameraInfoTable 1441 struct atom_fusion_system_info_v4 1442 { 1443 struct atom_integrated_system_info_v1_11 sysinfo; // refer to ATOM_INTEGRATED_SYSTEM_INFO_V1_8 definition 1444 uint32_t powerplayinfo[256]; // Reserve 1024 bytes space for PowerPlayInfoTable 1445 }; 1446 1447 1448 /* 1449 *************************************************************************** 1450 Data Table gfx_info structure 1451 *************************************************************************** 1452 */ 1453 1454 struct atom_gfx_info_v2_2 1455 { 1456 struct atom_common_table_header table_header; 1457 uint8_t gfxip_min_ver; 1458 uint8_t gfxip_max_ver; 1459 uint8_t max_shader_engines; 1460 uint8_t max_tile_pipes; 1461 uint8_t max_cu_per_sh; 1462 uint8_t max_sh_per_se; 1463 uint8_t max_backends_per_se; 1464 uint8_t max_texture_channel_caches; 1465 uint32_t regaddr_cp_dma_src_addr; 1466 uint32_t regaddr_cp_dma_src_addr_hi; 1467 uint32_t regaddr_cp_dma_dst_addr; 1468 uint32_t regaddr_cp_dma_dst_addr_hi; 1469 uint32_t regaddr_cp_dma_command; 1470 uint32_t regaddr_cp_status; 1471 uint32_t regaddr_rlc_gpu_clock_32; 1472 uint32_t rlc_gpu_timer_refclk; 1473 }; 1474 1475 struct atom_gfx_info_v2_3 { 1476 struct atom_common_table_header table_header; 1477 uint8_t gfxip_min_ver; 1478 uint8_t gfxip_max_ver; 1479 uint8_t max_shader_engines; 1480 uint8_t max_tile_pipes; 1481 uint8_t max_cu_per_sh; 1482 uint8_t max_sh_per_se; 1483 uint8_t max_backends_per_se; 1484 uint8_t max_texture_channel_caches; 1485 uint32_t regaddr_cp_dma_src_addr; 1486 uint32_t regaddr_cp_dma_src_addr_hi; 1487 uint32_t regaddr_cp_dma_dst_addr; 1488 uint32_t regaddr_cp_dma_dst_addr_hi; 1489 uint32_t regaddr_cp_dma_command; 1490 uint32_t regaddr_cp_status; 1491 uint32_t regaddr_rlc_gpu_clock_32; 1492 uint32_t rlc_gpu_timer_refclk; 1493 uint8_t active_cu_per_sh; 1494 uint8_t active_rb_per_se; 1495 uint16_t gcgoldenoffset; 1496 uint32_t rm21_sram_vmin_value; 1497 }; 1498 1499 struct atom_gfx_info_v2_4 1500 { 1501 struct atom_common_table_header table_header; 1502 uint8_t gfxip_min_ver; 1503 uint8_t gfxip_max_ver; 1504 uint8_t max_shader_engines; 1505 uint8_t reserved; 1506 uint8_t max_cu_per_sh; 1507 uint8_t max_sh_per_se; 1508 uint8_t max_backends_per_se; 1509 uint8_t max_texture_channel_caches; 1510 uint32_t regaddr_cp_dma_src_addr; 1511 uint32_t regaddr_cp_dma_src_addr_hi; 1512 uint32_t regaddr_cp_dma_dst_addr; 1513 uint32_t regaddr_cp_dma_dst_addr_hi; 1514 uint32_t regaddr_cp_dma_command; 1515 uint32_t regaddr_cp_status; 1516 uint32_t regaddr_rlc_gpu_clock_32; 1517 uint32_t rlc_gpu_timer_refclk; 1518 uint8_t active_cu_per_sh; 1519 uint8_t active_rb_per_se; 1520 uint16_t gcgoldenoffset; 1521 uint16_t gc_num_gprs; 1522 uint16_t gc_gsprim_buff_depth; 1523 uint16_t gc_parameter_cache_depth; 1524 uint16_t gc_wave_size; 1525 uint16_t gc_max_waves_per_simd; 1526 uint16_t gc_lds_size; 1527 uint8_t gc_num_max_gs_thds; 1528 uint8_t gc_gs_table_depth; 1529 uint8_t gc_double_offchip_lds_buffer; 1530 uint8_t gc_max_scratch_slots_per_cu; 1531 uint32_t sram_rm_fuses_val; 1532 uint32_t sram_custom_rm_fuses_val; 1533 }; 1534 1535 struct atom_gfx_info_v2_7 { 1536 struct atom_common_table_header table_header; 1537 uint8_t gfxip_min_ver; 1538 uint8_t gfxip_max_ver; 1539 uint8_t max_shader_engines; 1540 uint8_t reserved; 1541 uint8_t max_cu_per_sh; 1542 uint8_t max_sh_per_se; 1543 uint8_t max_backends_per_se; 1544 uint8_t max_texture_channel_caches; 1545 uint32_t regaddr_cp_dma_src_addr; 1546 uint32_t regaddr_cp_dma_src_addr_hi; 1547 uint32_t regaddr_cp_dma_dst_addr; 1548 uint32_t regaddr_cp_dma_dst_addr_hi; 1549 uint32_t regaddr_cp_dma_command; 1550 uint32_t regaddr_cp_status; 1551 uint32_t regaddr_rlc_gpu_clock_32; 1552 uint32_t rlc_gpu_timer_refclk; 1553 uint8_t active_cu_per_sh; 1554 uint8_t active_rb_per_se; 1555 uint16_t gcgoldenoffset; 1556 uint16_t gc_num_gprs; 1557 uint16_t gc_gsprim_buff_depth; 1558 uint16_t gc_parameter_cache_depth; 1559 uint16_t gc_wave_size; 1560 uint16_t gc_max_waves_per_simd; 1561 uint16_t gc_lds_size; 1562 uint8_t gc_num_max_gs_thds; 1563 uint8_t gc_gs_table_depth; 1564 uint8_t gc_double_offchip_lds_buffer; 1565 uint8_t gc_max_scratch_slots_per_cu; 1566 uint32_t sram_rm_fuses_val; 1567 uint32_t sram_custom_rm_fuses_val; 1568 uint8_t cut_cu; 1569 uint8_t active_cu_total; 1570 uint8_t cu_reserved[2]; 1571 uint32_t gc_config; 1572 uint8_t inactive_cu_per_se[8]; 1573 uint32_t reserved2[6]; 1574 }; 1575 1576 /* 1577 *************************************************************************** 1578 Data Table smu_info structure 1579 *************************************************************************** 1580 */ 1581 struct atom_smu_info_v3_1 1582 { 1583 struct atom_common_table_header table_header; 1584 uint8_t smuip_min_ver; 1585 uint8_t smuip_max_ver; 1586 uint8_t smu_rsd1; 1587 uint8_t gpuclk_ss_mode; // enum of atom_spread_spectrum_mode 1588 uint16_t sclk_ss_percentage; 1589 uint16_t sclk_ss_rate_10hz; 1590 uint16_t gpuclk_ss_percentage; // in unit of 0.001% 1591 uint16_t gpuclk_ss_rate_10hz; 1592 uint32_t core_refclk_10khz; 1593 uint8_t ac_dc_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for AC/DC switching, =0xff means invalid 1594 uint8_t ac_dc_polarity; // GPIO polarity for AC/DC switching 1595 uint8_t vr0hot_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for VR0 HOT event, =0xff means invalid 1596 uint8_t vr0hot_polarity; // GPIO polarity for VR0 HOT event 1597 uint8_t vr1hot_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for VR1 HOT event , =0xff means invalid 1598 uint8_t vr1hot_polarity; // GPIO polarity for VR1 HOT event 1599 uint8_t fw_ctf_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for CTF, =0xff means invalid 1600 uint8_t fw_ctf_polarity; // GPIO polarity for CTF 1601 }; 1602 1603 struct atom_smu_info_v3_2 { 1604 struct atom_common_table_header table_header; 1605 uint8_t smuip_min_ver; 1606 uint8_t smuip_max_ver; 1607 uint8_t smu_rsd1; 1608 uint8_t gpuclk_ss_mode; 1609 uint16_t sclk_ss_percentage; 1610 uint16_t sclk_ss_rate_10hz; 1611 uint16_t gpuclk_ss_percentage; // in unit of 0.001% 1612 uint16_t gpuclk_ss_rate_10hz; 1613 uint32_t core_refclk_10khz; 1614 uint8_t ac_dc_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for AC/DC switching, =0xff means invalid 1615 uint8_t ac_dc_polarity; // GPIO polarity for AC/DC switching 1616 uint8_t vr0hot_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for VR0 HOT event, =0xff means invalid 1617 uint8_t vr0hot_polarity; // GPIO polarity for VR0 HOT event 1618 uint8_t vr1hot_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for VR1 HOT event , =0xff means invalid 1619 uint8_t vr1hot_polarity; // GPIO polarity for VR1 HOT event 1620 uint8_t fw_ctf_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for CTF, =0xff means invalid 1621 uint8_t fw_ctf_polarity; // GPIO polarity for CTF 1622 uint8_t pcc_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for PCC, =0xff means invalid 1623 uint8_t pcc_gpio_polarity; // GPIO polarity for CTF 1624 uint16_t smugoldenoffset; 1625 uint32_t gpupll_vco_freq_10khz; 1626 uint32_t bootup_smnclk_10khz; 1627 uint32_t bootup_socclk_10khz; 1628 uint32_t bootup_mp0clk_10khz; 1629 uint32_t bootup_mp1clk_10khz; 1630 uint32_t bootup_lclk_10khz; 1631 uint32_t bootup_dcefclk_10khz; 1632 uint32_t ctf_threshold_override_value; 1633 uint32_t reserved[5]; 1634 }; 1635 1636 struct atom_smu_info_v3_3 { 1637 struct atom_common_table_header table_header; 1638 uint8_t smuip_min_ver; 1639 uint8_t smuip_max_ver; 1640 uint8_t waflclk_ss_mode; 1641 uint8_t gpuclk_ss_mode; 1642 uint16_t sclk_ss_percentage; 1643 uint16_t sclk_ss_rate_10hz; 1644 uint16_t gpuclk_ss_percentage; // in unit of 0.001% 1645 uint16_t gpuclk_ss_rate_10hz; 1646 uint32_t core_refclk_10khz; 1647 uint8_t ac_dc_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for AC/DC switching, =0xff means invalid 1648 uint8_t ac_dc_polarity; // GPIO polarity for AC/DC switching 1649 uint8_t vr0hot_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for VR0 HOT event, =0xff means invalid 1650 uint8_t vr0hot_polarity; // GPIO polarity for VR0 HOT event 1651 uint8_t vr1hot_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for VR1 HOT event , =0xff means invalid 1652 uint8_t vr1hot_polarity; // GPIO polarity for VR1 HOT event 1653 uint8_t fw_ctf_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for CTF, =0xff means invalid 1654 uint8_t fw_ctf_polarity; // GPIO polarity for CTF 1655 uint8_t pcc_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for PCC, =0xff means invalid 1656 uint8_t pcc_gpio_polarity; // GPIO polarity for CTF 1657 uint16_t smugoldenoffset; 1658 uint32_t gpupll_vco_freq_10khz; 1659 uint32_t bootup_smnclk_10khz; 1660 uint32_t bootup_socclk_10khz; 1661 uint32_t bootup_mp0clk_10khz; 1662 uint32_t bootup_mp1clk_10khz; 1663 uint32_t bootup_lclk_10khz; 1664 uint32_t bootup_dcefclk_10khz; 1665 uint32_t ctf_threshold_override_value; 1666 uint32_t syspll3_0_vco_freq_10khz; 1667 uint32_t syspll3_1_vco_freq_10khz; 1668 uint32_t bootup_fclk_10khz; 1669 uint32_t bootup_waflclk_10khz; 1670 uint32_t smu_info_caps; 1671 uint16_t waflclk_ss_percentage; // in unit of 0.001% 1672 uint16_t smuinitoffset; 1673 uint32_t reserved; 1674 }; 1675 1676 /* 1677 *************************************************************************** 1678 Data Table smc_dpm_info structure 1679 *************************************************************************** 1680 */ 1681 struct atom_smc_dpm_info_v4_1 1682 { 1683 struct atom_common_table_header table_header; 1684 uint8_t liquid1_i2c_address; 1685 uint8_t liquid2_i2c_address; 1686 uint8_t vr_i2c_address; 1687 uint8_t plx_i2c_address; 1688 1689 uint8_t liquid_i2c_linescl; 1690 uint8_t liquid_i2c_linesda; 1691 uint8_t vr_i2c_linescl; 1692 uint8_t vr_i2c_linesda; 1693 1694 uint8_t plx_i2c_linescl; 1695 uint8_t plx_i2c_linesda; 1696 uint8_t vrsensorpresent; 1697 uint8_t liquidsensorpresent; 1698 1699 uint16_t maxvoltagestepgfx; 1700 uint16_t maxvoltagestepsoc; 1701 1702 uint8_t vddgfxvrmapping; 1703 uint8_t vddsocvrmapping; 1704 uint8_t vddmem0vrmapping; 1705 uint8_t vddmem1vrmapping; 1706 1707 uint8_t gfxulvphasesheddingmask; 1708 uint8_t soculvphasesheddingmask; 1709 uint8_t padding8_v[2]; 1710 1711 uint16_t gfxmaxcurrent; 1712 uint8_t gfxoffset; 1713 uint8_t padding_telemetrygfx; 1714 1715 uint16_t socmaxcurrent; 1716 uint8_t socoffset; 1717 uint8_t padding_telemetrysoc; 1718 1719 uint16_t mem0maxcurrent; 1720 uint8_t mem0offset; 1721 uint8_t padding_telemetrymem0; 1722 1723 uint16_t mem1maxcurrent; 1724 uint8_t mem1offset; 1725 uint8_t padding_telemetrymem1; 1726 1727 uint8_t acdcgpio; 1728 uint8_t acdcpolarity; 1729 uint8_t vr0hotgpio; 1730 uint8_t vr0hotpolarity; 1731 1732 uint8_t vr1hotgpio; 1733 uint8_t vr1hotpolarity; 1734 uint8_t padding1; 1735 uint8_t padding2; 1736 1737 uint8_t ledpin0; 1738 uint8_t ledpin1; 1739 uint8_t ledpin2; 1740 uint8_t padding8_4; 1741 1742 uint8_t pllgfxclkspreadenabled; 1743 uint8_t pllgfxclkspreadpercent; 1744 uint16_t pllgfxclkspreadfreq; 1745 1746 uint8_t uclkspreadenabled; 1747 uint8_t uclkspreadpercent; 1748 uint16_t uclkspreadfreq; 1749 1750 uint8_t socclkspreadenabled; 1751 uint8_t socclkspreadpercent; 1752 uint16_t socclkspreadfreq; 1753 1754 uint8_t acggfxclkspreadenabled; 1755 uint8_t acggfxclkspreadpercent; 1756 uint16_t acggfxclkspreadfreq; 1757 1758 uint8_t Vr2_I2C_address; 1759 uint8_t padding_vr2[3]; 1760 1761 uint32_t boardreserved[9]; 1762 }; 1763 1764 /* 1765 *************************************************************************** 1766 Data Table smc_dpm_info structure 1767 *************************************************************************** 1768 */ 1769 struct atom_smc_dpm_info_v4_3 1770 { 1771 struct atom_common_table_header table_header; 1772 uint8_t liquid1_i2c_address; 1773 uint8_t liquid2_i2c_address; 1774 uint8_t vr_i2c_address; 1775 uint8_t plx_i2c_address; 1776 1777 uint8_t liquid_i2c_linescl; 1778 uint8_t liquid_i2c_linesda; 1779 uint8_t vr_i2c_linescl; 1780 uint8_t vr_i2c_linesda; 1781 1782 uint8_t plx_i2c_linescl; 1783 uint8_t plx_i2c_linesda; 1784 uint8_t vrsensorpresent; 1785 uint8_t liquidsensorpresent; 1786 1787 uint16_t maxvoltagestepgfx; 1788 uint16_t maxvoltagestepsoc; 1789 1790 uint8_t vddgfxvrmapping; 1791 uint8_t vddsocvrmapping; 1792 uint8_t vddmem0vrmapping; 1793 uint8_t vddmem1vrmapping; 1794 1795 uint8_t gfxulvphasesheddingmask; 1796 uint8_t soculvphasesheddingmask; 1797 uint8_t externalsensorpresent; 1798 uint8_t padding8_v; 1799 1800 uint16_t gfxmaxcurrent; 1801 uint8_t gfxoffset; 1802 uint8_t padding_telemetrygfx; 1803 1804 uint16_t socmaxcurrent; 1805 uint8_t socoffset; 1806 uint8_t padding_telemetrysoc; 1807 1808 uint16_t mem0maxcurrent; 1809 uint8_t mem0offset; 1810 uint8_t padding_telemetrymem0; 1811 1812 uint16_t mem1maxcurrent; 1813 uint8_t mem1offset; 1814 uint8_t padding_telemetrymem1; 1815 1816 uint8_t acdcgpio; 1817 uint8_t acdcpolarity; 1818 uint8_t vr0hotgpio; 1819 uint8_t vr0hotpolarity; 1820 1821 uint8_t vr1hotgpio; 1822 uint8_t vr1hotpolarity; 1823 uint8_t padding1; 1824 uint8_t padding2; 1825 1826 uint8_t ledpin0; 1827 uint8_t ledpin1; 1828 uint8_t ledpin2; 1829 uint8_t padding8_4; 1830 1831 uint8_t pllgfxclkspreadenabled; 1832 uint8_t pllgfxclkspreadpercent; 1833 uint16_t pllgfxclkspreadfreq; 1834 1835 uint8_t uclkspreadenabled; 1836 uint8_t uclkspreadpercent; 1837 uint16_t uclkspreadfreq; 1838 1839 uint8_t fclkspreadenabled; 1840 uint8_t fclkspreadpercent; 1841 uint16_t fclkspreadfreq; 1842 1843 uint8_t fllgfxclkspreadenabled; 1844 uint8_t fllgfxclkspreadpercent; 1845 uint16_t fllgfxclkspreadfreq; 1846 1847 uint32_t boardreserved[10]; 1848 }; 1849 1850 struct smudpm_i2ccontrollerconfig_t { 1851 uint32_t enabled; 1852 uint32_t slaveaddress; 1853 uint32_t controllerport; 1854 uint32_t controllername; 1855 uint32_t thermalthrottler; 1856 uint32_t i2cprotocol; 1857 uint32_t i2cspeed; 1858 }; 1859 1860 struct atom_smc_dpm_info_v4_4 1861 { 1862 struct atom_common_table_header table_header; 1863 uint32_t i2c_padding[3]; 1864 1865 uint16_t maxvoltagestepgfx; 1866 uint16_t maxvoltagestepsoc; 1867 1868 uint8_t vddgfxvrmapping; 1869 uint8_t vddsocvrmapping; 1870 uint8_t vddmem0vrmapping; 1871 uint8_t vddmem1vrmapping; 1872 1873 uint8_t gfxulvphasesheddingmask; 1874 uint8_t soculvphasesheddingmask; 1875 uint8_t externalsensorpresent; 1876 uint8_t padding8_v; 1877 1878 uint16_t gfxmaxcurrent; 1879 uint8_t gfxoffset; 1880 uint8_t padding_telemetrygfx; 1881 1882 uint16_t socmaxcurrent; 1883 uint8_t socoffset; 1884 uint8_t padding_telemetrysoc; 1885 1886 uint16_t mem0maxcurrent; 1887 uint8_t mem0offset; 1888 uint8_t padding_telemetrymem0; 1889 1890 uint16_t mem1maxcurrent; 1891 uint8_t mem1offset; 1892 uint8_t padding_telemetrymem1; 1893 1894 1895 uint8_t acdcgpio; 1896 uint8_t acdcpolarity; 1897 uint8_t vr0hotgpio; 1898 uint8_t vr0hotpolarity; 1899 1900 uint8_t vr1hotgpio; 1901 uint8_t vr1hotpolarity; 1902 uint8_t padding1; 1903 uint8_t padding2; 1904 1905 1906 uint8_t ledpin0; 1907 uint8_t ledpin1; 1908 uint8_t ledpin2; 1909 uint8_t padding8_4; 1910 1911 1912 uint8_t pllgfxclkspreadenabled; 1913 uint8_t pllgfxclkspreadpercent; 1914 uint16_t pllgfxclkspreadfreq; 1915 1916 1917 uint8_t uclkspreadenabled; 1918 uint8_t uclkspreadpercent; 1919 uint16_t uclkspreadfreq; 1920 1921 1922 uint8_t fclkspreadenabled; 1923 uint8_t fclkspreadpercent; 1924 uint16_t fclkspreadfreq; 1925 1926 1927 uint8_t fllgfxclkspreadenabled; 1928 uint8_t fllgfxclkspreadpercent; 1929 uint16_t fllgfxclkspreadfreq; 1930 1931 1932 struct smudpm_i2ccontrollerconfig_t i2ccontrollers[7]; 1933 1934 1935 uint32_t boardreserved[10]; 1936 }; 1937 1938 enum smudpm_v4_5_i2ccontrollername_e{ 1939 SMC_V4_5_I2C_CONTROLLER_NAME_VR_GFX = 0, 1940 SMC_V4_5_I2C_CONTROLLER_NAME_VR_SOC, 1941 SMC_V4_5_I2C_CONTROLLER_NAME_VR_VDDCI, 1942 SMC_V4_5_I2C_CONTROLLER_NAME_VR_MVDD, 1943 SMC_V4_5_I2C_CONTROLLER_NAME_LIQUID0, 1944 SMC_V4_5_I2C_CONTROLLER_NAME_LIQUID1, 1945 SMC_V4_5_I2C_CONTROLLER_NAME_PLX, 1946 SMC_V4_5_I2C_CONTROLLER_NAME_SPARE, 1947 SMC_V4_5_I2C_CONTROLLER_NAME_COUNT, 1948 }; 1949 1950 enum smudpm_v4_5_i2ccontrollerthrottler_e{ 1951 SMC_V4_5_I2C_CONTROLLER_THROTTLER_TYPE_NONE = 0, 1952 SMC_V4_5_I2C_CONTROLLER_THROTTLER_VR_GFX, 1953 SMC_V4_5_I2C_CONTROLLER_THROTTLER_VR_SOC, 1954 SMC_V4_5_I2C_CONTROLLER_THROTTLER_VR_VDDCI, 1955 SMC_V4_5_I2C_CONTROLLER_THROTTLER_VR_MVDD, 1956 SMC_V4_5_I2C_CONTROLLER_THROTTLER_LIQUID0, 1957 SMC_V4_5_I2C_CONTROLLER_THROTTLER_LIQUID1, 1958 SMC_V4_5_I2C_CONTROLLER_THROTTLER_PLX, 1959 SMC_V4_5_I2C_CONTROLLER_THROTTLER_COUNT, 1960 }; 1961 1962 enum smudpm_v4_5_i2ccontrollerprotocol_e{ 1963 SMC_V4_5_I2C_CONTROLLER_PROTOCOL_VR_0, 1964 SMC_V4_5_I2C_CONTROLLER_PROTOCOL_VR_1, 1965 SMC_V4_5_I2C_CONTROLLER_PROTOCOL_TMP_0, 1966 SMC_V4_5_I2C_CONTROLLER_PROTOCOL_TMP_1, 1967 SMC_V4_5_I2C_CONTROLLER_PROTOCOL_SPARE_0, 1968 SMC_V4_5_I2C_CONTROLLER_PROTOCOL_SPARE_1, 1969 SMC_V4_5_I2C_CONTROLLER_PROTOCOL_COUNT, 1970 }; 1971 1972 struct smudpm_i2c_controller_config_v2 1973 { 1974 uint8_t Enabled; 1975 uint8_t Speed; 1976 uint8_t Padding[2]; 1977 uint32_t SlaveAddress; 1978 uint8_t ControllerPort; 1979 uint8_t ControllerName; 1980 uint8_t ThermalThrotter; 1981 uint8_t I2cProtocol; 1982 }; 1983 1984 struct atom_smc_dpm_info_v4_5 1985 { 1986 struct atom_common_table_header table_header; 1987 // SECTION: BOARD PARAMETERS 1988 // I2C Control 1989 struct smudpm_i2c_controller_config_v2 I2cControllers[8]; 1990 1991 // SVI2 Board Parameters 1992 uint16_t MaxVoltageStepGfx; // In mV(Q2) Max voltage step that SMU will request. Multiple steps are taken if voltage change exceeds this value. 1993 uint16_t MaxVoltageStepSoc; // In mV(Q2) Max voltage step that SMU will request. Multiple steps are taken if voltage change exceeds this value. 1994 1995 uint8_t VddGfxVrMapping; // Use VR_MAPPING* bitfields 1996 uint8_t VddSocVrMapping; // Use VR_MAPPING* bitfields 1997 uint8_t VddMem0VrMapping; // Use VR_MAPPING* bitfields 1998 uint8_t VddMem1VrMapping; // Use VR_MAPPING* bitfields 1999 2000 uint8_t GfxUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode 2001 uint8_t SocUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode 2002 uint8_t ExternalSensorPresent; // External RDI connected to TMON (aka TEMP IN) 2003 uint8_t Padding8_V; 2004 2005 // Telemetry Settings 2006 uint16_t GfxMaxCurrent; // in Amps 2007 uint8_t GfxOffset; // in Amps 2008 uint8_t Padding_TelemetryGfx; 2009 uint16_t SocMaxCurrent; // in Amps 2010 uint8_t SocOffset; // in Amps 2011 uint8_t Padding_TelemetrySoc; 2012 2013 uint16_t Mem0MaxCurrent; // in Amps 2014 uint8_t Mem0Offset; // in Amps 2015 uint8_t Padding_TelemetryMem0; 2016 2017 uint16_t Mem1MaxCurrent; // in Amps 2018 uint8_t Mem1Offset; // in Amps 2019 uint8_t Padding_TelemetryMem1; 2020 2021 // GPIO Settings 2022 uint8_t AcDcGpio; // GPIO pin configured for AC/DC switching 2023 uint8_t AcDcPolarity; // GPIO polarity for AC/DC switching 2024 uint8_t VR0HotGpio; // GPIO pin configured for VR0 HOT event 2025 uint8_t VR0HotPolarity; // GPIO polarity for VR0 HOT event 2026 2027 uint8_t VR1HotGpio; // GPIO pin configured for VR1 HOT event 2028 uint8_t VR1HotPolarity; // GPIO polarity for VR1 HOT event 2029 uint8_t GthrGpio; // GPIO pin configured for GTHR Event 2030 uint8_t GthrPolarity; // replace GPIO polarity for GTHR 2031 2032 // LED Display Settings 2033 uint8_t LedPin0; // GPIO number for LedPin[0] 2034 uint8_t LedPin1; // GPIO number for LedPin[1] 2035 uint8_t LedPin2; // GPIO number for LedPin[2] 2036 uint8_t padding8_4; 2037 2038 // GFXCLK PLL Spread Spectrum 2039 uint8_t PllGfxclkSpreadEnabled; // on or off 2040 uint8_t PllGfxclkSpreadPercent; // Q4.4 2041 uint16_t PllGfxclkSpreadFreq; // kHz 2042 2043 // GFXCLK DFLL Spread Spectrum 2044 uint8_t DfllGfxclkSpreadEnabled; // on or off 2045 uint8_t DfllGfxclkSpreadPercent; // Q4.4 2046 uint16_t DfllGfxclkSpreadFreq; // kHz 2047 2048 // UCLK Spread Spectrum 2049 uint8_t UclkSpreadEnabled; // on or off 2050 uint8_t UclkSpreadPercent; // Q4.4 2051 uint16_t UclkSpreadFreq; // kHz 2052 2053 // SOCCLK Spread Spectrum 2054 uint8_t SoclkSpreadEnabled; // on or off 2055 uint8_t SocclkSpreadPercent; // Q4.4 2056 uint16_t SocclkSpreadFreq; // kHz 2057 2058 // Total board power 2059 uint16_t TotalBoardPower; //Only needed for TCP Estimated case, where TCP = TGP+Total Board Power 2060 uint16_t BoardPadding; 2061 2062 // Mvdd Svi2 Div Ratio Setting 2063 uint32_t MvddRatio; // This is used for MVDD Vid workaround. It has 16 fractional bits (Q16.16) 2064 2065 uint32_t BoardReserved[9]; 2066 2067 }; 2068 2069 struct atom_smc_dpm_info_v4_6 2070 { 2071 struct atom_common_table_header table_header; 2072 // section: board parameters 2073 uint32_t i2c_padding[3]; // old i2c control are moved to new area 2074 2075 uint16_t maxvoltagestepgfx; // in mv(q2) max voltage step that smu will request. multiple steps are taken if voltage change exceeds this value. 2076 uint16_t maxvoltagestepsoc; // in mv(q2) max voltage step that smu will request. multiple steps are taken if voltage change exceeds this value. 2077 2078 uint8_t vddgfxvrmapping; // use vr_mapping* bitfields 2079 uint8_t vddsocvrmapping; // use vr_mapping* bitfields 2080 uint8_t vddmemvrmapping; // use vr_mapping* bitfields 2081 uint8_t boardvrmapping; // use vr_mapping* bitfields 2082 2083 uint8_t gfxulvphasesheddingmask; // set this to 1 to set psi0/1 to 1 in ulv mode 2084 uint8_t externalsensorpresent; // external rdi connected to tmon (aka temp in) 2085 uint8_t padding8_v[2]; 2086 2087 // telemetry settings 2088 uint16_t gfxmaxcurrent; // in amps 2089 uint8_t gfxoffset; // in amps 2090 uint8_t padding_telemetrygfx; 2091 2092 uint16_t socmaxcurrent; // in amps 2093 uint8_t socoffset; // in amps 2094 uint8_t padding_telemetrysoc; 2095 2096 uint16_t memmaxcurrent; // in amps 2097 uint8_t memoffset; // in amps 2098 uint8_t padding_telemetrymem; 2099 2100 uint16_t boardmaxcurrent; // in amps 2101 uint8_t boardoffset; // in amps 2102 uint8_t padding_telemetryboardinput; 2103 2104 // gpio settings 2105 uint8_t vr0hotgpio; // gpio pin configured for vr0 hot event 2106 uint8_t vr0hotpolarity; // gpio polarity for vr0 hot event 2107 uint8_t vr1hotgpio; // gpio pin configured for vr1 hot event 2108 uint8_t vr1hotpolarity; // gpio polarity for vr1 hot event 2109 2110 // gfxclk pll spread spectrum 2111 uint8_t pllgfxclkspreadenabled; // on or off 2112 uint8_t pllgfxclkspreadpercent; // q4.4 2113 uint16_t pllgfxclkspreadfreq; // khz 2114 2115 // uclk spread spectrum 2116 uint8_t uclkspreadenabled; // on or off 2117 uint8_t uclkspreadpercent; // q4.4 2118 uint16_t uclkspreadfreq; // khz 2119 2120 // fclk spread spectrum 2121 uint8_t fclkspreadenabled; // on or off 2122 uint8_t fclkspreadpercent; // q4.4 2123 uint16_t fclkspreadfreq; // khz 2124 2125 2126 // gfxclk fll spread spectrum 2127 uint8_t fllgfxclkspreadenabled; // on or off 2128 uint8_t fllgfxclkspreadpercent; // q4.4 2129 uint16_t fllgfxclkspreadfreq; // khz 2130 2131 // i2c controller structure 2132 struct smudpm_i2c_controller_config_v2 i2ccontrollers[8]; 2133 2134 // memory section 2135 uint32_t memorychannelenabled; // for dram use only, max 32 channels enabled bit mask. 2136 2137 uint8_t drambitwidth; // for dram use only. see dram bit width type defines 2138 uint8_t paddingmem[3]; 2139 2140 // total board power 2141 uint16_t totalboardpower; //only needed for tcp estimated case, where tcp = tgp+total board power 2142 uint16_t boardpadding; 2143 2144 // section: xgmi training 2145 uint8_t xgmilinkspeed[4]; 2146 uint8_t xgmilinkwidth[4]; 2147 2148 uint16_t xgmifclkfreq[4]; 2149 uint16_t xgmisocvoltage[4]; 2150 2151 // reserved 2152 uint32_t boardreserved[10]; 2153 }; 2154 2155 struct atom_smc_dpm_info_v4_7 2156 { 2157 struct atom_common_table_header table_header; 2158 // SECTION: BOARD PARAMETERS 2159 // I2C Control 2160 struct smudpm_i2c_controller_config_v2 I2cControllers[8]; 2161 2162 // SVI2 Board Parameters 2163 uint16_t MaxVoltageStepGfx; // In mV(Q2) Max voltage step that SMU will request. Multiple steps are taken if voltage change exceeds this value. 2164 uint16_t MaxVoltageStepSoc; // In mV(Q2) Max voltage step that SMU will request. Multiple steps are taken if voltage change exceeds this value. 2165 2166 uint8_t VddGfxVrMapping; // Use VR_MAPPING* bitfields 2167 uint8_t VddSocVrMapping; // Use VR_MAPPING* bitfields 2168 uint8_t VddMem0VrMapping; // Use VR_MAPPING* bitfields 2169 uint8_t VddMem1VrMapping; // Use VR_MAPPING* bitfields 2170 2171 uint8_t GfxUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode 2172 uint8_t SocUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode 2173 uint8_t ExternalSensorPresent; // External RDI connected to TMON (aka TEMP IN) 2174 uint8_t Padding8_V; 2175 2176 // Telemetry Settings 2177 uint16_t GfxMaxCurrent; // in Amps 2178 uint8_t GfxOffset; // in Amps 2179 uint8_t Padding_TelemetryGfx; 2180 uint16_t SocMaxCurrent; // in Amps 2181 uint8_t SocOffset; // in Amps 2182 uint8_t Padding_TelemetrySoc; 2183 2184 uint16_t Mem0MaxCurrent; // in Amps 2185 uint8_t Mem0Offset; // in Amps 2186 uint8_t Padding_TelemetryMem0; 2187 2188 uint16_t Mem1MaxCurrent; // in Amps 2189 uint8_t Mem1Offset; // in Amps 2190 uint8_t Padding_TelemetryMem1; 2191 2192 // GPIO Settings 2193 uint8_t AcDcGpio; // GPIO pin configured for AC/DC switching 2194 uint8_t AcDcPolarity; // GPIO polarity for AC/DC switching 2195 uint8_t VR0HotGpio; // GPIO pin configured for VR0 HOT event 2196 uint8_t VR0HotPolarity; // GPIO polarity for VR0 HOT event 2197 2198 uint8_t VR1HotGpio; // GPIO pin configured for VR1 HOT event 2199 uint8_t VR1HotPolarity; // GPIO polarity for VR1 HOT event 2200 uint8_t GthrGpio; // GPIO pin configured for GTHR Event 2201 uint8_t GthrPolarity; // replace GPIO polarity for GTHR 2202 2203 // LED Display Settings 2204 uint8_t LedPin0; // GPIO number for LedPin[0] 2205 uint8_t LedPin1; // GPIO number for LedPin[1] 2206 uint8_t LedPin2; // GPIO number for LedPin[2] 2207 uint8_t padding8_4; 2208 2209 // GFXCLK PLL Spread Spectrum 2210 uint8_t PllGfxclkSpreadEnabled; // on or off 2211 uint8_t PllGfxclkSpreadPercent; // Q4.4 2212 uint16_t PllGfxclkSpreadFreq; // kHz 2213 2214 // GFXCLK DFLL Spread Spectrum 2215 uint8_t DfllGfxclkSpreadEnabled; // on or off 2216 uint8_t DfllGfxclkSpreadPercent; // Q4.4 2217 uint16_t DfllGfxclkSpreadFreq; // kHz 2218 2219 // UCLK Spread Spectrum 2220 uint8_t UclkSpreadEnabled; // on or off 2221 uint8_t UclkSpreadPercent; // Q4.4 2222 uint16_t UclkSpreadFreq; // kHz 2223 2224 // SOCCLK Spread Spectrum 2225 uint8_t SoclkSpreadEnabled; // on or off 2226 uint8_t SocclkSpreadPercent; // Q4.4 2227 uint16_t SocclkSpreadFreq; // kHz 2228 2229 // Total board power 2230 uint16_t TotalBoardPower; //Only needed for TCP Estimated case, where TCP = TGP+Total Board Power 2231 uint16_t BoardPadding; 2232 2233 // Mvdd Svi2 Div Ratio Setting 2234 uint32_t MvddRatio; // This is used for MVDD Vid workaround. It has 16 fractional bits (Q16.16) 2235 2236 // GPIO pins for I2C communications with 2nd controller for Input Telemetry Sequence 2237 uint8_t GpioI2cScl; // Serial Clock 2238 uint8_t GpioI2cSda; // Serial Data 2239 uint16_t GpioPadding; 2240 2241 // Additional LED Display Settings 2242 uint8_t LedPin3; // GPIO number for LedPin[3] - PCIE GEN Speed 2243 uint8_t LedPin4; // GPIO number for LedPin[4] - PMFW Error Status 2244 uint16_t LedEnableMask; 2245 2246 // Power Limit Scalars 2247 uint8_t PowerLimitScalar[4]; //[PPT_THROTTLER_COUNT] 2248 2249 uint8_t MvddUlvPhaseSheddingMask; 2250 uint8_t VddciUlvPhaseSheddingMask; 2251 uint8_t Padding8_Psi1; 2252 uint8_t Padding8_Psi2; 2253 2254 uint32_t BoardReserved[5]; 2255 }; 2256 2257 struct smudpm_i2c_controller_config_v3 2258 { 2259 uint8_t Enabled; 2260 uint8_t Speed; 2261 uint8_t SlaveAddress; 2262 uint8_t ControllerPort; 2263 uint8_t ControllerName; 2264 uint8_t ThermalThrotter; 2265 uint8_t I2cProtocol; 2266 uint8_t PaddingConfig; 2267 }; 2268 2269 struct atom_smc_dpm_info_v4_9 2270 { 2271 struct atom_common_table_header table_header; 2272 2273 //SECTION: Gaming Clocks 2274 //uint32_t GamingClk[6]; 2275 2276 // SECTION: I2C Control 2277 struct smudpm_i2c_controller_config_v3 I2cControllers[16]; 2278 2279 uint8_t GpioScl; // GPIO Number for SCL Line, used only for CKSVII2C1 2280 uint8_t GpioSda; // GPIO Number for SDA Line, used only for CKSVII2C1 2281 uint8_t FchUsbPdSlaveAddr; //For requesting USB PD controller S-states via FCH I2C when entering PME turn off 2282 uint8_t I2cSpare; 2283 2284 // SECTION: SVI2 Board Parameters 2285 uint8_t VddGfxVrMapping; // Use VR_MAPPING* bitfields 2286 uint8_t VddSocVrMapping; // Use VR_MAPPING* bitfields 2287 uint8_t VddMem0VrMapping; // Use VR_MAPPING* bitfields 2288 uint8_t VddMem1VrMapping; // Use VR_MAPPING* bitfields 2289 2290 uint8_t GfxUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode 2291 uint8_t SocUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode 2292 uint8_t VddciUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode 2293 uint8_t MvddUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode 2294 2295 // SECTION: Telemetry Settings 2296 uint16_t GfxMaxCurrent; // in Amps 2297 uint8_t GfxOffset; // in Amps 2298 uint8_t Padding_TelemetryGfx; 2299 2300 uint16_t SocMaxCurrent; // in Amps 2301 uint8_t SocOffset; // in Amps 2302 uint8_t Padding_TelemetrySoc; 2303 2304 uint16_t Mem0MaxCurrent; // in Amps 2305 uint8_t Mem0Offset; // in Amps 2306 uint8_t Padding_TelemetryMem0; 2307 2308 uint16_t Mem1MaxCurrent; // in Amps 2309 uint8_t Mem1Offset; // in Amps 2310 uint8_t Padding_TelemetryMem1; 2311 2312 uint32_t MvddRatio; // This is used for MVDD Svi2 Div Ratio workaround. It has 16 fractional bits (Q16.16) 2313 2314 // SECTION: GPIO Settings 2315 uint8_t AcDcGpio; // GPIO pin configured for AC/DC switching 2316 uint8_t AcDcPolarity; // GPIO polarity for AC/DC switching 2317 uint8_t VR0HotGpio; // GPIO pin configured for VR0 HOT event 2318 uint8_t VR0HotPolarity; // GPIO polarity for VR0 HOT event 2319 2320 uint8_t VR1HotGpio; // GPIO pin configured for VR1 HOT event 2321 uint8_t VR1HotPolarity; // GPIO polarity for VR1 HOT event 2322 uint8_t GthrGpio; // GPIO pin configured for GTHR Event 2323 uint8_t GthrPolarity; // replace GPIO polarity for GTHR 2324 2325 // LED Display Settings 2326 uint8_t LedPin0; // GPIO number for LedPin[0] 2327 uint8_t LedPin1; // GPIO number for LedPin[1] 2328 uint8_t LedPin2; // GPIO number for LedPin[2] 2329 uint8_t LedEnableMask; 2330 2331 uint8_t LedPcie; // GPIO number for PCIE results 2332 uint8_t LedError; // GPIO number for Error Cases 2333 uint8_t LedSpare1[2]; 2334 2335 // SECTION: Clock Spread Spectrum 2336 2337 // GFXCLK PLL Spread Spectrum 2338 uint8_t PllGfxclkSpreadEnabled; // on or off 2339 uint8_t PllGfxclkSpreadPercent; // Q4.4 2340 uint16_t PllGfxclkSpreadFreq; // kHz 2341 2342 // GFXCLK DFLL Spread Spectrum 2343 uint8_t DfllGfxclkSpreadEnabled; // on or off 2344 uint8_t DfllGfxclkSpreadPercent; // Q4.4 2345 uint16_t DfllGfxclkSpreadFreq; // kHz 2346 2347 // UCLK Spread Spectrum 2348 uint8_t UclkSpreadEnabled; // on or off 2349 uint8_t UclkSpreadPercent; // Q4.4 2350 uint16_t UclkSpreadFreq; // kHz 2351 2352 // FCLK Spread Spectrum 2353 uint8_t FclkSpreadEnabled; // on or off 2354 uint8_t FclkSpreadPercent; // Q4.4 2355 uint16_t FclkSpreadFreq; // kHz 2356 2357 // Section: Memory Config 2358 uint32_t MemoryChannelEnabled; // For DRAM use only, Max 32 channels enabled bit mask. 2359 2360 uint8_t DramBitWidth; // For DRAM use only. See Dram Bit width type defines 2361 uint8_t PaddingMem1[3]; 2362 2363 // Section: Total Board Power 2364 uint16_t TotalBoardPower; //Only needed for TCP Estimated case, where TCP = TGP+Total Board Power 2365 uint16_t BoardPowerPadding; 2366 2367 // SECTION: XGMI Training 2368 uint8_t XgmiLinkSpeed [4]; 2369 uint8_t XgmiLinkWidth [4]; 2370 2371 uint16_t XgmiFclkFreq [4]; 2372 uint16_t XgmiSocVoltage [4]; 2373 2374 // SECTION: Board Reserved 2375 2376 uint32_t BoardReserved[16]; 2377 2378 }; 2379 2380 struct atom_smc_dpm_info_v4_10 2381 { 2382 struct atom_common_table_header table_header; 2383 2384 // SECTION: BOARD PARAMETERS 2385 // Telemetry Settings 2386 uint16_t GfxMaxCurrent; // in Amps 2387 uint8_t GfxOffset; // in Amps 2388 uint8_t Padding_TelemetryGfx; 2389 2390 uint16_t SocMaxCurrent; // in Amps 2391 uint8_t SocOffset; // in Amps 2392 uint8_t Padding_TelemetrySoc; 2393 2394 uint16_t MemMaxCurrent; // in Amps 2395 uint8_t MemOffset; // in Amps 2396 uint8_t Padding_TelemetryMem; 2397 2398 uint16_t BoardMaxCurrent; // in Amps 2399 uint8_t BoardOffset; // in Amps 2400 uint8_t Padding_TelemetryBoardInput; 2401 2402 // Platform input telemetry voltage coefficient 2403 uint32_t BoardVoltageCoeffA; // decode by /1000 2404 uint32_t BoardVoltageCoeffB; // decode by /1000 2405 2406 // GPIO Settings 2407 uint8_t VR0HotGpio; // GPIO pin configured for VR0 HOT event 2408 uint8_t VR0HotPolarity; // GPIO polarity for VR0 HOT event 2409 uint8_t VR1HotGpio; // GPIO pin configured for VR1 HOT event 2410 uint8_t VR1HotPolarity; // GPIO polarity for VR1 HOT event 2411 2412 // UCLK Spread Spectrum 2413 uint8_t UclkSpreadEnabled; // on or off 2414 uint8_t UclkSpreadPercent; // Q4.4 2415 uint16_t UclkSpreadFreq; // kHz 2416 2417 // FCLK Spread Spectrum 2418 uint8_t FclkSpreadEnabled; // on or off 2419 uint8_t FclkSpreadPercent; // Q4.4 2420 uint16_t FclkSpreadFreq; // kHz 2421 2422 // I2C Controller Structure 2423 struct smudpm_i2c_controller_config_v3 I2cControllers[8]; 2424 2425 // GPIO pins for I2C communications with 2nd controller for Input Telemetry Sequence 2426 uint8_t GpioI2cScl; // Serial Clock 2427 uint8_t GpioI2cSda; // Serial Data 2428 uint16_t spare5; 2429 2430 uint32_t reserved[16]; 2431 }; 2432 2433 /* 2434 *************************************************************************** 2435 Data Table asic_profiling_info structure 2436 *************************************************************************** 2437 */ 2438 struct atom_asic_profiling_info_v4_1 2439 { 2440 struct atom_common_table_header table_header; 2441 uint32_t maxvddc; 2442 uint32_t minvddc; 2443 uint32_t avfs_meannsigma_acontant0; 2444 uint32_t avfs_meannsigma_acontant1; 2445 uint32_t avfs_meannsigma_acontant2; 2446 uint16_t avfs_meannsigma_dc_tol_sigma; 2447 uint16_t avfs_meannsigma_platform_mean; 2448 uint16_t avfs_meannsigma_platform_sigma; 2449 uint32_t gb_vdroop_table_cksoff_a0; 2450 uint32_t gb_vdroop_table_cksoff_a1; 2451 uint32_t gb_vdroop_table_cksoff_a2; 2452 uint32_t gb_vdroop_table_ckson_a0; 2453 uint32_t gb_vdroop_table_ckson_a1; 2454 uint32_t gb_vdroop_table_ckson_a2; 2455 uint32_t avfsgb_fuse_table_cksoff_m1; 2456 uint32_t avfsgb_fuse_table_cksoff_m2; 2457 uint32_t avfsgb_fuse_table_cksoff_b; 2458 uint32_t avfsgb_fuse_table_ckson_m1; 2459 uint32_t avfsgb_fuse_table_ckson_m2; 2460 uint32_t avfsgb_fuse_table_ckson_b; 2461 uint16_t max_voltage_0_25mv; 2462 uint8_t enable_gb_vdroop_table_cksoff; 2463 uint8_t enable_gb_vdroop_table_ckson; 2464 uint8_t enable_gb_fuse_table_cksoff; 2465 uint8_t enable_gb_fuse_table_ckson; 2466 uint16_t psm_age_comfactor; 2467 uint8_t enable_apply_avfs_cksoff_voltage; 2468 uint8_t reserved; 2469 uint32_t dispclk2gfxclk_a; 2470 uint32_t dispclk2gfxclk_b; 2471 uint32_t dispclk2gfxclk_c; 2472 uint32_t pixclk2gfxclk_a; 2473 uint32_t pixclk2gfxclk_b; 2474 uint32_t pixclk2gfxclk_c; 2475 uint32_t dcefclk2gfxclk_a; 2476 uint32_t dcefclk2gfxclk_b; 2477 uint32_t dcefclk2gfxclk_c; 2478 uint32_t phyclk2gfxclk_a; 2479 uint32_t phyclk2gfxclk_b; 2480 uint32_t phyclk2gfxclk_c; 2481 }; 2482 2483 struct atom_asic_profiling_info_v4_2 { 2484 struct atom_common_table_header table_header; 2485 uint32_t maxvddc; 2486 uint32_t minvddc; 2487 uint32_t avfs_meannsigma_acontant0; 2488 uint32_t avfs_meannsigma_acontant1; 2489 uint32_t avfs_meannsigma_acontant2; 2490 uint16_t avfs_meannsigma_dc_tol_sigma; 2491 uint16_t avfs_meannsigma_platform_mean; 2492 uint16_t avfs_meannsigma_platform_sigma; 2493 uint32_t gb_vdroop_table_cksoff_a0; 2494 uint32_t gb_vdroop_table_cksoff_a1; 2495 uint32_t gb_vdroop_table_cksoff_a2; 2496 uint32_t gb_vdroop_table_ckson_a0; 2497 uint32_t gb_vdroop_table_ckson_a1; 2498 uint32_t gb_vdroop_table_ckson_a2; 2499 uint32_t avfsgb_fuse_table_cksoff_m1; 2500 uint32_t avfsgb_fuse_table_cksoff_m2; 2501 uint32_t avfsgb_fuse_table_cksoff_b; 2502 uint32_t avfsgb_fuse_table_ckson_m1; 2503 uint32_t avfsgb_fuse_table_ckson_m2; 2504 uint32_t avfsgb_fuse_table_ckson_b; 2505 uint16_t max_voltage_0_25mv; 2506 uint8_t enable_gb_vdroop_table_cksoff; 2507 uint8_t enable_gb_vdroop_table_ckson; 2508 uint8_t enable_gb_fuse_table_cksoff; 2509 uint8_t enable_gb_fuse_table_ckson; 2510 uint16_t psm_age_comfactor; 2511 uint8_t enable_apply_avfs_cksoff_voltage; 2512 uint8_t reserved; 2513 uint32_t dispclk2gfxclk_a; 2514 uint32_t dispclk2gfxclk_b; 2515 uint32_t dispclk2gfxclk_c; 2516 uint32_t pixclk2gfxclk_a; 2517 uint32_t pixclk2gfxclk_b; 2518 uint32_t pixclk2gfxclk_c; 2519 uint32_t dcefclk2gfxclk_a; 2520 uint32_t dcefclk2gfxclk_b; 2521 uint32_t dcefclk2gfxclk_c; 2522 uint32_t phyclk2gfxclk_a; 2523 uint32_t phyclk2gfxclk_b; 2524 uint32_t phyclk2gfxclk_c; 2525 uint32_t acg_gb_vdroop_table_a0; 2526 uint32_t acg_gb_vdroop_table_a1; 2527 uint32_t acg_gb_vdroop_table_a2; 2528 uint32_t acg_avfsgb_fuse_table_m1; 2529 uint32_t acg_avfsgb_fuse_table_m2; 2530 uint32_t acg_avfsgb_fuse_table_b; 2531 uint8_t enable_acg_gb_vdroop_table; 2532 uint8_t enable_acg_gb_fuse_table; 2533 uint32_t acg_dispclk2gfxclk_a; 2534 uint32_t acg_dispclk2gfxclk_b; 2535 uint32_t acg_dispclk2gfxclk_c; 2536 uint32_t acg_pixclk2gfxclk_a; 2537 uint32_t acg_pixclk2gfxclk_b; 2538 uint32_t acg_pixclk2gfxclk_c; 2539 uint32_t acg_dcefclk2gfxclk_a; 2540 uint32_t acg_dcefclk2gfxclk_b; 2541 uint32_t acg_dcefclk2gfxclk_c; 2542 uint32_t acg_phyclk2gfxclk_a; 2543 uint32_t acg_phyclk2gfxclk_b; 2544 uint32_t acg_phyclk2gfxclk_c; 2545 }; 2546 2547 /* 2548 *************************************************************************** 2549 Data Table multimedia_info structure 2550 *************************************************************************** 2551 */ 2552 struct atom_multimedia_info_v2_1 2553 { 2554 struct atom_common_table_header table_header; 2555 uint8_t uvdip_min_ver; 2556 uint8_t uvdip_max_ver; 2557 uint8_t vceip_min_ver; 2558 uint8_t vceip_max_ver; 2559 uint16_t uvd_enc_max_input_width_pixels; 2560 uint16_t uvd_enc_max_input_height_pixels; 2561 uint16_t vce_enc_max_input_width_pixels; 2562 uint16_t vce_enc_max_input_height_pixels; 2563 uint32_t uvd_enc_max_bandwidth; // 16x16 pixels/sec, codec independent 2564 uint32_t vce_enc_max_bandwidth; // 16x16 pixels/sec, codec independent 2565 }; 2566 2567 2568 /* 2569 *************************************************************************** 2570 Data Table umc_info structure 2571 *************************************************************************** 2572 */ 2573 struct atom_umc_info_v3_1 2574 { 2575 struct atom_common_table_header table_header; 2576 uint32_t ucode_version; 2577 uint32_t ucode_rom_startaddr; 2578 uint32_t ucode_length; 2579 uint16_t umc_reg_init_offset; 2580 uint16_t customer_ucode_name_offset; 2581 uint16_t mclk_ss_percentage; 2582 uint16_t mclk_ss_rate_10hz; 2583 uint8_t umcip_min_ver; 2584 uint8_t umcip_max_ver; 2585 uint8_t vram_type; //enum of atom_dgpu_vram_type 2586 uint8_t umc_config; 2587 uint32_t mem_refclk_10khz; 2588 }; 2589 2590 // umc_info.umc_config 2591 enum atom_umc_config_def { 2592 UMC_CONFIG__ENABLE_1KB_INTERLEAVE_MODE = 0x00000001, 2593 UMC_CONFIG__DEFAULT_MEM_ECC_ENABLE = 0x00000002, 2594 UMC_CONFIG__ENABLE_HBM_LANE_REPAIR = 0x00000004, 2595 UMC_CONFIG__ENABLE_BANK_HARVESTING = 0x00000008, 2596 UMC_CONFIG__ENABLE_PHY_REINIT = 0x00000010, 2597 UMC_CONFIG__DISABLE_UCODE_CHKSTATUS = 0x00000020, 2598 }; 2599 2600 struct atom_umc_info_v3_2 2601 { 2602 struct atom_common_table_header table_header; 2603 uint32_t ucode_version; 2604 uint32_t ucode_rom_startaddr; 2605 uint32_t ucode_length; 2606 uint16_t umc_reg_init_offset; 2607 uint16_t customer_ucode_name_offset; 2608 uint16_t mclk_ss_percentage; 2609 uint16_t mclk_ss_rate_10hz; 2610 uint8_t umcip_min_ver; 2611 uint8_t umcip_max_ver; 2612 uint8_t vram_type; //enum of atom_dgpu_vram_type 2613 uint8_t umc_config; 2614 uint32_t mem_refclk_10khz; 2615 uint32_t pstate_uclk_10khz[4]; 2616 uint16_t umcgoldenoffset; 2617 uint16_t densitygoldenoffset; 2618 }; 2619 2620 struct atom_umc_info_v3_3 2621 { 2622 struct atom_common_table_header table_header; 2623 uint32_t ucode_reserved; 2624 uint32_t ucode_rom_startaddr; 2625 uint32_t ucode_length; 2626 uint16_t umc_reg_init_offset; 2627 uint16_t customer_ucode_name_offset; 2628 uint16_t mclk_ss_percentage; 2629 uint16_t mclk_ss_rate_10hz; 2630 uint8_t umcip_min_ver; 2631 uint8_t umcip_max_ver; 2632 uint8_t vram_type; //enum of atom_dgpu_vram_type 2633 uint8_t umc_config; 2634 uint32_t mem_refclk_10khz; 2635 uint32_t pstate_uclk_10khz[4]; 2636 uint16_t umcgoldenoffset; 2637 uint16_t densitygoldenoffset; 2638 uint32_t umc_config1; 2639 uint32_t bist_data_startaddr; 2640 uint32_t reserved[2]; 2641 }; 2642 2643 enum atom_umc_config1_def { 2644 UMC_CONFIG1__ENABLE_PSTATE_PHASE_STORE_TRAIN = 0x00000001, 2645 UMC_CONFIG1__ENABLE_AUTO_FRAMING = 0x00000002, 2646 UMC_CONFIG1__ENABLE_RESTORE_BIST_DATA = 0x00000004, 2647 UMC_CONFIG1__DISABLE_STROBE_MODE = 0x00000008, 2648 UMC_CONFIG1__DEBUG_DATA_PARITY_EN = 0x00000010, 2649 UMC_CONFIG1__ENABLE_ECC_CAPABLE = 0x00010000, 2650 }; 2651 2652 /* 2653 *************************************************************************** 2654 Data Table vram_info structure 2655 *************************************************************************** 2656 */ 2657 struct atom_vram_module_v9 { 2658 // Design Specific Values 2659 uint32_t memory_size; // Total memory size in unit of MB for CONFIG_MEMSIZE zeros 2660 uint32_t channel_enable; // bit vector, each bit indicate specific channel enable or not 2661 uint32_t max_mem_clk; // max memory clock of this memory in unit of 10kHz, =0 means it is not defined 2662 uint16_t reserved[3]; 2663 uint16_t mem_voltage; // mem_voltage 2664 uint16_t vram_module_size; // Size of atom_vram_module_v9 2665 uint8_t ext_memory_id; // Current memory module ID 2666 uint8_t memory_type; // enum of atom_dgpu_vram_type 2667 uint8_t channel_num; // Number of mem. channels supported in this module 2668 uint8_t channel_width; // CHANNEL_16BIT/CHANNEL_32BIT/CHANNEL_64BIT 2669 uint8_t density; // _8Mx32, _16Mx32, _16Mx16, _32Mx16 2670 uint8_t tunningset_id; // MC phy registers set per. 2671 uint8_t vender_rev_id; // [7:4] Revision, [3:0] Vendor code 2672 uint8_t refreshrate; // [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64ms) 2673 uint8_t hbm_ven_rev_id; // hbm_ven_rev_id 2674 uint8_t vram_rsd2; // reserved 2675 char dram_pnstring[20]; // part number end with '0'. 2676 }; 2677 2678 struct atom_vram_info_header_v2_3 { 2679 struct atom_common_table_header table_header; 2680 uint16_t mem_adjust_tbloffset; // offset of atom_umc_init_reg_block structure for memory vendor specific UMC adjust setting 2681 uint16_t mem_clk_patch_tbloffset; // offset of atom_umc_init_reg_block structure for memory clock specific UMC setting 2682 uint16_t mc_adjust_pertile_tbloffset; // offset of atom_umc_init_reg_block structure for Per Byte Offset Preset Settings 2683 uint16_t mc_phyinit_tbloffset; // offset of atom_umc_init_reg_block structure for MC phy init set 2684 uint16_t dram_data_remap_tbloffset; // reserved for now 2685 uint16_t tmrs_seq_offset; // offset of HBM tmrs 2686 uint16_t post_ucode_init_offset; // offset of atom_umc_init_reg_block structure for MC phy init after MC uCode complete umc init 2687 uint16_t vram_rsd2; 2688 uint8_t vram_module_num; // indicate number of VRAM module 2689 uint8_t umcip_min_ver; 2690 uint8_t umcip_max_ver; 2691 uint8_t mc_phy_tile_num; // indicate the MCD tile number which use in DramDataRemapTbl and usMcAdjustPerTileTblOffset 2692 struct atom_vram_module_v9 vram_module[16]; // just for allocation, real number of blocks is in ucNumOfVRAMModule; 2693 }; 2694 2695 struct atom_umc_register_addr_info{ 2696 uint32_t umc_register_addr:24; 2697 uint32_t umc_reg_type_ind:1; 2698 uint32_t umc_reg_rsvd:7; 2699 }; 2700 2701 //atom_umc_register_addr_info. 2702 enum atom_umc_register_addr_info_flag{ 2703 b3ATOM_UMC_REG_ADD_INFO_INDIRECT_ACCESS =0x01, 2704 }; 2705 2706 union atom_umc_register_addr_info_access 2707 { 2708 struct atom_umc_register_addr_info umc_reg_addr; 2709 uint32_t u32umc_reg_addr; 2710 }; 2711 2712 struct atom_umc_reg_setting_id_config{ 2713 uint32_t memclockrange:24; 2714 uint32_t mem_blk_id:8; 2715 }; 2716 2717 union atom_umc_reg_setting_id_config_access 2718 { 2719 struct atom_umc_reg_setting_id_config umc_id_access; 2720 uint32_t u32umc_id_access; 2721 }; 2722 2723 struct atom_umc_reg_setting_data_block{ 2724 union atom_umc_reg_setting_id_config_access block_id; 2725 uint32_t u32umc_reg_data[1]; 2726 }; 2727 2728 struct atom_umc_init_reg_block{ 2729 uint16_t umc_reg_num; 2730 uint16_t reserved; 2731 union atom_umc_register_addr_info_access umc_reg_list[1]; //for allocation purpose, the real number come from umc_reg_num; 2732 struct atom_umc_reg_setting_data_block umc_reg_setting_list[1]; 2733 }; 2734 2735 struct atom_vram_module_v10 { 2736 // Design Specific Values 2737 uint32_t memory_size; // Total memory size in unit of MB for CONFIG_MEMSIZE zeros 2738 uint32_t channel_enable; // bit vector, each bit indicate specific channel enable or not 2739 uint32_t max_mem_clk; // max memory clock of this memory in unit of 10kHz, =0 means it is not defined 2740 uint16_t reserved[3]; 2741 uint16_t mem_voltage; // mem_voltage 2742 uint16_t vram_module_size; // Size of atom_vram_module_v9 2743 uint8_t ext_memory_id; // Current memory module ID 2744 uint8_t memory_type; // enum of atom_dgpu_vram_type 2745 uint8_t channel_num; // Number of mem. channels supported in this module 2746 uint8_t channel_width; // CHANNEL_16BIT/CHANNEL_32BIT/CHANNEL_64BIT 2747 uint8_t density; // _8Mx32, _16Mx32, _16Mx16, _32Mx16 2748 uint8_t tunningset_id; // MC phy registers set per 2749 uint8_t vender_rev_id; // [7:4] Revision, [3:0] Vendor code 2750 uint8_t refreshrate; // [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64ms) 2751 uint8_t vram_flags; // bit0= bankgroup enable 2752 uint8_t vram_rsd2; // reserved 2753 uint16_t gddr6_mr10; // gddr6 mode register10 value 2754 uint16_t gddr6_mr1; // gddr6 mode register1 value 2755 uint16_t gddr6_mr2; // gddr6 mode register2 value 2756 uint16_t gddr6_mr7; // gddr6 mode register7 value 2757 char dram_pnstring[20]; // part number end with '0' 2758 }; 2759 2760 struct atom_vram_info_header_v2_4 { 2761 struct atom_common_table_header table_header; 2762 uint16_t mem_adjust_tbloffset; // offset of atom_umc_init_reg_block structure for memory vendor specific UMC adjust setting 2763 uint16_t mem_clk_patch_tbloffset; // offset of atom_umc_init_reg_block structure for memory clock specific UMC setting 2764 uint16_t mc_adjust_pertile_tbloffset; // offset of atom_umc_init_reg_block structure for Per Byte Offset Preset Settings 2765 uint16_t mc_phyinit_tbloffset; // offset of atom_umc_init_reg_block structure for MC phy init set 2766 uint16_t dram_data_remap_tbloffset; // reserved for now 2767 uint16_t reserved; // offset of reserved 2768 uint16_t post_ucode_init_offset; // offset of atom_umc_init_reg_block structure for MC phy init after MC uCode complete umc init 2769 uint16_t vram_rsd2; 2770 uint8_t vram_module_num; // indicate number of VRAM module 2771 uint8_t umcip_min_ver; 2772 uint8_t umcip_max_ver; 2773 uint8_t mc_phy_tile_num; // indicate the MCD tile number which use in DramDataRemapTbl and usMcAdjustPerTileTblOffset 2774 struct atom_vram_module_v10 vram_module[16]; // just for allocation, real number of blocks is in ucNumOfVRAMModule; 2775 }; 2776 2777 struct atom_vram_module_v11 { 2778 // Design Specific Values 2779 uint32_t memory_size; // Total memory size in unit of MB for CONFIG_MEMSIZE zeros 2780 uint32_t channel_enable; // bit vector, each bit indicate specific channel enable or not 2781 uint16_t mem_voltage; // mem_voltage 2782 uint16_t vram_module_size; // Size of atom_vram_module_v9 2783 uint8_t ext_memory_id; // Current memory module ID 2784 uint8_t memory_type; // enum of atom_dgpu_vram_type 2785 uint8_t channel_num; // Number of mem. channels supported in this module 2786 uint8_t channel_width; // CHANNEL_16BIT/CHANNEL_32BIT/CHANNEL_64BIT 2787 uint8_t density; // _8Mx32, _16Mx32, _16Mx16, _32Mx16 2788 uint8_t tunningset_id; // MC phy registers set per. 2789 uint16_t reserved[4]; // reserved 2790 uint8_t vender_rev_id; // [7:4] Revision, [3:0] Vendor code 2791 uint8_t refreshrate; // [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64ms) 2792 uint8_t vram_flags; // bit0= bankgroup enable 2793 uint8_t vram_rsd2; // reserved 2794 uint16_t gddr6_mr10; // gddr6 mode register10 value 2795 uint16_t gddr6_mr0; // gddr6 mode register0 value 2796 uint16_t gddr6_mr1; // gddr6 mode register1 value 2797 uint16_t gddr6_mr2; // gddr6 mode register2 value 2798 uint16_t gddr6_mr4; // gddr6 mode register4 value 2799 uint16_t gddr6_mr7; // gddr6 mode register7 value 2800 uint16_t gddr6_mr8; // gddr6 mode register8 value 2801 char dram_pnstring[40]; // part number end with '0'. 2802 }; 2803 2804 struct atom_gddr6_ac_timing_v2_5 { 2805 uint32_t u32umc_id_access; 2806 uint8_t RL; 2807 uint8_t WL; 2808 uint8_t tRAS; 2809 uint8_t tRC; 2810 2811 uint16_t tREFI; 2812 uint8_t tRFC; 2813 uint8_t tRFCpb; 2814 2815 uint8_t tRREFD; 2816 uint8_t tRCDRD; 2817 uint8_t tRCDWR; 2818 uint8_t tRP; 2819 2820 uint8_t tRRDS; 2821 uint8_t tRRDL; 2822 uint8_t tWR; 2823 uint8_t tWTRS; 2824 2825 uint8_t tWTRL; 2826 uint8_t tFAW; 2827 uint8_t tCCDS; 2828 uint8_t tCCDL; 2829 2830 uint8_t tCRCRL; 2831 uint8_t tCRCWL; 2832 uint8_t tCKE; 2833 uint8_t tCKSRE; 2834 2835 uint8_t tCKSRX; 2836 uint8_t tRTPS; 2837 uint8_t tRTPL; 2838 uint8_t tMRD; 2839 2840 uint8_t tMOD; 2841 uint8_t tXS; 2842 uint8_t tXHP; 2843 uint8_t tXSMRS; 2844 2845 uint32_t tXSH; 2846 2847 uint8_t tPD; 2848 uint8_t tXP; 2849 uint8_t tCPDED; 2850 uint8_t tACTPDE; 2851 2852 uint8_t tPREPDE; 2853 uint8_t tREFPDE; 2854 uint8_t tMRSPDEN; 2855 uint8_t tRDSRE; 2856 2857 uint8_t tWRSRE; 2858 uint8_t tPPD; 2859 uint8_t tCCDMW; 2860 uint8_t tWTRTR; 2861 2862 uint8_t tLTLTR; 2863 uint8_t tREFTR; 2864 uint8_t VNDR; 2865 uint8_t reserved[9]; 2866 }; 2867 2868 struct atom_gddr6_bit_byte_remap { 2869 uint32_t dphy_byteremap; //mmUMC_DPHY_ByteRemap 2870 uint32_t dphy_bitremap0; //mmUMC_DPHY_BitRemap0 2871 uint32_t dphy_bitremap1; //mmUMC_DPHY_BitRemap1 2872 uint32_t dphy_bitremap2; //mmUMC_DPHY_BitRemap2 2873 uint32_t aphy_bitremap0; //mmUMC_APHY_BitRemap0 2874 uint32_t aphy_bitremap1; //mmUMC_APHY_BitRemap1 2875 uint32_t phy_dram; //mmUMC_PHY_DRAM 2876 }; 2877 2878 struct atom_gddr6_dram_data_remap { 2879 uint32_t table_size; 2880 uint8_t phyintf_ck_inverted[8]; //UMC_PHY_PHYINTF_CNTL.INV_CK 2881 struct atom_gddr6_bit_byte_remap bit_byte_remap[16]; 2882 }; 2883 2884 struct atom_vram_info_header_v2_5 { 2885 struct atom_common_table_header table_header; 2886 uint16_t mem_adjust_tbloffset; // offset of atom_umc_init_reg_block structure for memory vendor specific UMC adjust settings 2887 uint16_t gddr6_ac_timing_offset; // offset of atom_gddr6_ac_timing_v2_5 structure for memory clock specific UMC settings 2888 uint16_t mc_adjust_pertile_tbloffset; // offset of atom_umc_init_reg_block structure for Per Byte Offset Preset Settings 2889 uint16_t mc_phyinit_tbloffset; // offset of atom_umc_init_reg_block structure for MC phy init set 2890 uint16_t dram_data_remap_tbloffset; // offset of atom_gddr6_dram_data_remap array to indicate DRAM data lane to GPU mapping 2891 uint16_t reserved; // offset of reserved 2892 uint16_t post_ucode_init_offset; // offset of atom_umc_init_reg_block structure for MC phy init after MC uCode complete umc init 2893 uint16_t strobe_mode_patch_tbloffset; // offset of atom_umc_init_reg_block structure for Strobe Mode memory clock specific UMC settings 2894 uint8_t vram_module_num; // indicate number of VRAM module 2895 uint8_t umcip_min_ver; 2896 uint8_t umcip_max_ver; 2897 uint8_t mc_phy_tile_num; // indicate the MCD tile number which use in DramDataRemapTbl and usMcAdjustPerTileTblOffset 2898 struct atom_vram_module_v11 vram_module[16]; // just for allocation, real number of blocks is in ucNumOfVRAMModule; 2899 }; 2900 2901 struct atom_vram_info_header_v2_6 { 2902 struct atom_common_table_header table_header; 2903 uint16_t mem_adjust_tbloffset; 2904 uint16_t mem_clk_patch_tbloffset; 2905 uint16_t mc_adjust_pertile_tbloffset; 2906 uint16_t mc_phyinit_tbloffset; 2907 uint16_t dram_data_remap_tbloffset; 2908 uint16_t tmrs_seq_offset; 2909 uint16_t post_ucode_init_offset; 2910 uint16_t vram_rsd2; 2911 uint8_t vram_module_num; 2912 uint8_t umcip_min_ver; 2913 uint8_t umcip_max_ver; 2914 uint8_t mc_phy_tile_num; 2915 struct atom_vram_module_v9 vram_module[16]; 2916 }; 2917 /* 2918 *************************************************************************** 2919 Data Table voltageobject_info structure 2920 *************************************************************************** 2921 */ 2922 struct atom_i2c_data_entry 2923 { 2924 uint16_t i2c_reg_index; // i2c register address, can be up to 16bit 2925 uint16_t i2c_reg_data; // i2c register data, can be up to 16bit 2926 }; 2927 2928 struct atom_voltage_object_header_v4{ 2929 uint8_t voltage_type; //enum atom_voltage_type 2930 uint8_t voltage_mode; //enum atom_voltage_object_mode 2931 uint16_t object_size; //Size of Object 2932 }; 2933 2934 // atom_voltage_object_header_v4.voltage_mode 2935 enum atom_voltage_object_mode 2936 { 2937 VOLTAGE_OBJ_GPIO_LUT = 0, //VOLTAGE and GPIO Lookup table ->atom_gpio_voltage_object_v4 2938 VOLTAGE_OBJ_VR_I2C_INIT_SEQ = 3, //VOLTAGE REGULATOR INIT sequece through I2C -> atom_i2c_voltage_object_v4 2939 VOLTAGE_OBJ_PHASE_LUT = 4, //Set Vregulator Phase lookup table ->atom_gpio_voltage_object_v4 2940 VOLTAGE_OBJ_SVID2 = 7, //Indicate voltage control by SVID2 ->atom_svid2_voltage_object_v4 2941 VOLTAGE_OBJ_EVV = 8, 2942 VOLTAGE_OBJ_MERGED_POWER = 9, 2943 }; 2944 2945 struct atom_i2c_voltage_object_v4 2946 { 2947 struct atom_voltage_object_header_v4 header; // voltage mode = VOLTAGE_OBJ_VR_I2C_INIT_SEQ 2948 uint8_t regulator_id; //Indicate Voltage Regulator Id 2949 uint8_t i2c_id; 2950 uint8_t i2c_slave_addr; 2951 uint8_t i2c_control_offset; 2952 uint8_t i2c_flag; // Bit0: 0 - One byte data; 1 - Two byte data 2953 uint8_t i2c_speed; // =0, use default i2c speed, otherwise use it in unit of kHz. 2954 uint8_t reserved[2]; 2955 struct atom_i2c_data_entry i2cdatalut[1]; // end with 0xff 2956 }; 2957 2958 // ATOM_I2C_VOLTAGE_OBJECT_V3.ucVoltageControlFlag 2959 enum atom_i2c_voltage_control_flag 2960 { 2961 VOLTAGE_DATA_ONE_BYTE = 0, 2962 VOLTAGE_DATA_TWO_BYTE = 1, 2963 }; 2964 2965 2966 struct atom_voltage_gpio_map_lut 2967 { 2968 uint32_t voltage_gpio_reg_val; // The Voltage ID which is used to program GPIO register 2969 uint16_t voltage_level_mv; // The corresponding Voltage Value, in mV 2970 }; 2971 2972 struct atom_gpio_voltage_object_v4 2973 { 2974 struct atom_voltage_object_header_v4 header; // voltage mode = VOLTAGE_OBJ_GPIO_LUT or VOLTAGE_OBJ_PHASE_LUT 2975 uint8_t gpio_control_id; // default is 0 which indicate control through CG VID mode 2976 uint8_t gpio_entry_num; // indiate the entry numbers of Votlage/Gpio value Look up table 2977 uint8_t phase_delay_us; // phase delay in unit of micro second 2978 uint8_t reserved; 2979 uint32_t gpio_mask_val; // GPIO Mask value 2980 struct atom_voltage_gpio_map_lut voltage_gpio_lut[1]; 2981 }; 2982 2983 struct atom_svid2_voltage_object_v4 2984 { 2985 struct atom_voltage_object_header_v4 header; // voltage mode = VOLTAGE_OBJ_SVID2 2986 uint8_t loadline_psi1; // bit4:0= loadline setting ( Core Loadline trim and offset trim ), bit5=0:PSI1_L disable =1: PSI1_L enable 2987 uint8_t psi0_l_vid_thresd; // VR PSI0_L VID threshold 2988 uint8_t psi0_enable; // 2989 uint8_t maxvstep; 2990 uint8_t telemetry_offset; 2991 uint8_t telemetry_gain; 2992 uint16_t reserved1; 2993 }; 2994 2995 struct atom_merged_voltage_object_v4 2996 { 2997 struct atom_voltage_object_header_v4 header; // voltage mode = VOLTAGE_OBJ_MERGED_POWER 2998 uint8_t merged_powerrail_type; //enum atom_voltage_type 2999 uint8_t reserved[3]; 3000 }; 3001 3002 union atom_voltage_object_v4{ 3003 struct atom_gpio_voltage_object_v4 gpio_voltage_obj; 3004 struct atom_i2c_voltage_object_v4 i2c_voltage_obj; 3005 struct atom_svid2_voltage_object_v4 svid2_voltage_obj; 3006 struct atom_merged_voltage_object_v4 merged_voltage_obj; 3007 }; 3008 3009 struct atom_voltage_objects_info_v4_1 3010 { 3011 struct atom_common_table_header table_header; 3012 union atom_voltage_object_v4 voltage_object[1]; //Info for Voltage control 3013 }; 3014 3015 3016 /* 3017 *************************************************************************** 3018 All Command Function structure definition 3019 *************************************************************************** 3020 */ 3021 3022 /* 3023 *************************************************************************** 3024 Structures used by asic_init 3025 *************************************************************************** 3026 */ 3027 3028 struct asic_init_engine_parameters 3029 { 3030 uint32_t sclkfreqin10khz:24; 3031 uint32_t engineflag:8; /* enum atom_asic_init_engine_flag */ 3032 }; 3033 3034 struct asic_init_mem_parameters 3035 { 3036 uint32_t mclkfreqin10khz:24; 3037 uint32_t memflag:8; /* enum atom_asic_init_mem_flag */ 3038 }; 3039 3040 struct asic_init_parameters_v2_1 3041 { 3042 struct asic_init_engine_parameters engineparam; 3043 struct asic_init_mem_parameters memparam; 3044 }; 3045 3046 struct asic_init_ps_allocation_v2_1 3047 { 3048 struct asic_init_parameters_v2_1 param; 3049 uint32_t reserved[16]; 3050 }; 3051 3052 3053 enum atom_asic_init_engine_flag 3054 { 3055 b3NORMAL_ENGINE_INIT = 0, 3056 b3SRIOV_SKIP_ASIC_INIT = 0x02, 3057 b3SRIOV_LOAD_UCODE = 0x40, 3058 }; 3059 3060 enum atom_asic_init_mem_flag 3061 { 3062 b3NORMAL_MEM_INIT = 0, 3063 b3DRAM_SELF_REFRESH_EXIT =0x20, 3064 }; 3065 3066 /* 3067 *************************************************************************** 3068 Structures used by setengineclock 3069 *************************************************************************** 3070 */ 3071 3072 struct set_engine_clock_parameters_v2_1 3073 { 3074 uint32_t sclkfreqin10khz:24; 3075 uint32_t sclkflag:8; /* enum atom_set_engine_mem_clock_flag, */ 3076 uint32_t reserved[10]; 3077 }; 3078 3079 struct set_engine_clock_ps_allocation_v2_1 3080 { 3081 struct set_engine_clock_parameters_v2_1 clockinfo; 3082 uint32_t reserved[10]; 3083 }; 3084 3085 3086 enum atom_set_engine_mem_clock_flag 3087 { 3088 b3NORMAL_CHANGE_CLOCK = 0, 3089 b3FIRST_TIME_CHANGE_CLOCK = 0x08, 3090 b3STORE_DPM_TRAINGING = 0x40, //Applicable to memory clock change,when set, it store specific DPM mode training result 3091 }; 3092 3093 /* 3094 *************************************************************************** 3095 Structures used by getengineclock 3096 *************************************************************************** 3097 */ 3098 struct get_engine_clock_parameter 3099 { 3100 uint32_t sclk_10khz; // current engine speed in 10KHz unit 3101 uint32_t reserved; 3102 }; 3103 3104 /* 3105 *************************************************************************** 3106 Structures used by setmemoryclock 3107 *************************************************************************** 3108 */ 3109 struct set_memory_clock_parameters_v2_1 3110 { 3111 uint32_t mclkfreqin10khz:24; 3112 uint32_t mclkflag:8; /* enum atom_set_engine_mem_clock_flag, */ 3113 uint32_t reserved[10]; 3114 }; 3115 3116 struct set_memory_clock_ps_allocation_v2_1 3117 { 3118 struct set_memory_clock_parameters_v2_1 clockinfo; 3119 uint32_t reserved[10]; 3120 }; 3121 3122 3123 /* 3124 *************************************************************************** 3125 Structures used by getmemoryclock 3126 *************************************************************************** 3127 */ 3128 struct get_memory_clock_parameter 3129 { 3130 uint32_t mclk_10khz; // current engine speed in 10KHz unit 3131 uint32_t reserved; 3132 }; 3133 3134 3135 3136 /* 3137 *************************************************************************** 3138 Structures used by setvoltage 3139 *************************************************************************** 3140 */ 3141 3142 struct set_voltage_parameters_v1_4 3143 { 3144 uint8_t voltagetype; /* enum atom_voltage_type */ 3145 uint8_t command; /* Indicate action: Set voltage level, enum atom_set_voltage_command */ 3146 uint16_t vlevel_mv; /* real voltage level in unit of mv or Voltage Phase (0, 1, 2, .. ) */ 3147 }; 3148 3149 //set_voltage_parameters_v2_1.voltagemode 3150 enum atom_set_voltage_command{ 3151 ATOM_SET_VOLTAGE = 0, 3152 ATOM_INIT_VOLTAGE_REGULATOR = 3, 3153 ATOM_SET_VOLTAGE_PHASE = 4, 3154 ATOM_GET_LEAKAGE_ID = 8, 3155 }; 3156 3157 struct set_voltage_ps_allocation_v1_4 3158 { 3159 struct set_voltage_parameters_v1_4 setvoltageparam; 3160 uint32_t reserved[10]; 3161 }; 3162 3163 3164 /* 3165 *************************************************************************** 3166 Structures used by computegpuclockparam 3167 *************************************************************************** 3168 */ 3169 3170 //ATOM_COMPUTE_CLOCK_FREQ.ulComputeClockFlag 3171 enum atom_gpu_clock_type 3172 { 3173 COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK =0x00, 3174 COMPUTE_GPUCLK_INPUT_FLAG_GFXCLK =0x01, 3175 COMPUTE_GPUCLK_INPUT_FLAG_UCLK =0x02, 3176 }; 3177 3178 struct compute_gpu_clock_input_parameter_v1_8 3179 { 3180 uint32_t gpuclock_10khz:24; //Input= target clock, output = actual clock 3181 uint32_t gpu_clock_type:8; //Input indicate clock type: enum atom_gpu_clock_type 3182 uint32_t reserved[5]; 3183 }; 3184 3185 3186 struct compute_gpu_clock_output_parameter_v1_8 3187 { 3188 uint32_t gpuclock_10khz:24; //Input= target clock, output = actual clock 3189 uint32_t dfs_did:8; //return parameter: DFS divider which is used to program to register directly 3190 uint32_t pll_fb_mult; //Feedback Multiplier, bit 8:0 int, bit 15:12 post_div, bit 31:16 frac 3191 uint32_t pll_ss_fbsmult; // Spread FB Mult: bit 8:0 int, bit 31:16 frac 3192 uint16_t pll_ss_slew_frac; 3193 uint8_t pll_ss_enable; 3194 uint8_t reserved; 3195 uint32_t reserved1[2]; 3196 }; 3197 3198 3199 3200 /* 3201 *************************************************************************** 3202 Structures used by ReadEfuseValue 3203 *************************************************************************** 3204 */ 3205 3206 struct read_efuse_input_parameters_v3_1 3207 { 3208 uint16_t efuse_start_index; 3209 uint8_t reserved; 3210 uint8_t bitslen; 3211 }; 3212 3213 // ReadEfuseValue input/output parameter 3214 union read_efuse_value_parameters_v3_1 3215 { 3216 struct read_efuse_input_parameters_v3_1 efuse_info; 3217 uint32_t efusevalue; 3218 }; 3219 3220 3221 /* 3222 *************************************************************************** 3223 Structures used by getsmuclockinfo 3224 *************************************************************************** 3225 */ 3226 struct atom_get_smu_clock_info_parameters_v3_1 3227 { 3228 uint8_t syspll_id; // 0= syspll0, 1=syspll1, 2=syspll2 3229 uint8_t clk_id; // atom_smu9_syspll0_clock_id (only valid when command == GET_SMU_CLOCK_INFO_V3_1_GET_CLOCK_FREQ ) 3230 uint8_t command; // enum of atom_get_smu_clock_info_command 3231 uint8_t dfsdid; // =0: get DFS DID from register, >0, give DFS divider, (only valid when command == GET_SMU_CLOCK_INFO_V3_1_GET_CLOCK_FREQ ) 3232 }; 3233 3234 enum atom_get_smu_clock_info_command 3235 { 3236 GET_SMU_CLOCK_INFO_V3_1_GET_CLOCK_FREQ = 0, 3237 GET_SMU_CLOCK_INFO_V3_1_GET_PLLVCO_FREQ = 1, 3238 GET_SMU_CLOCK_INFO_V3_1_GET_PLLREFCLK_FREQ = 2, 3239 }; 3240 3241 enum atom_smu9_syspll0_clock_id 3242 { 3243 SMU9_SYSPLL0_SMNCLK_ID = 0, // SMNCLK 3244 SMU9_SYSPLL0_SOCCLK_ID = 1, // SOCCLK (FCLK) 3245 SMU9_SYSPLL0_MP0CLK_ID = 2, // MP0CLK 3246 SMU9_SYSPLL0_MP1CLK_ID = 3, // MP1CLK 3247 SMU9_SYSPLL0_LCLK_ID = 4, // LCLK 3248 SMU9_SYSPLL0_DCLK_ID = 5, // DCLK 3249 SMU9_SYSPLL0_VCLK_ID = 6, // VCLK 3250 SMU9_SYSPLL0_ECLK_ID = 7, // ECLK 3251 SMU9_SYSPLL0_DCEFCLK_ID = 8, // DCEFCLK 3252 SMU9_SYSPLL0_DPREFCLK_ID = 10, // DPREFCLK 3253 SMU9_SYSPLL0_DISPCLK_ID = 11, // DISPCLK 3254 }; 3255 3256 enum atom_smu11_syspll_id { 3257 SMU11_SYSPLL0_ID = 0, 3258 SMU11_SYSPLL1_0_ID = 1, 3259 SMU11_SYSPLL1_1_ID = 2, 3260 SMU11_SYSPLL1_2_ID = 3, 3261 SMU11_SYSPLL2_ID = 4, 3262 SMU11_SYSPLL3_0_ID = 5, 3263 SMU11_SYSPLL3_1_ID = 6, 3264 }; 3265 3266 enum atom_smu11_syspll0_clock_id { 3267 SMU11_SYSPLL0_ECLK_ID = 0, // ECLK 3268 SMU11_SYSPLL0_SOCCLK_ID = 1, // SOCCLK 3269 SMU11_SYSPLL0_MP0CLK_ID = 2, // MP0CLK 3270 SMU11_SYSPLL0_DCLK_ID = 3, // DCLK 3271 SMU11_SYSPLL0_VCLK_ID = 4, // VCLK 3272 SMU11_SYSPLL0_DCEFCLK_ID = 5, // DCEFCLK 3273 }; 3274 3275 enum atom_smu11_syspll1_0_clock_id { 3276 SMU11_SYSPLL1_0_UCLKA_ID = 0, // UCLK_a 3277 }; 3278 3279 enum atom_smu11_syspll1_1_clock_id { 3280 SMU11_SYSPLL1_0_UCLKB_ID = 0, // UCLK_b 3281 }; 3282 3283 enum atom_smu11_syspll1_2_clock_id { 3284 SMU11_SYSPLL1_0_FCLK_ID = 0, // FCLK 3285 }; 3286 3287 enum atom_smu11_syspll2_clock_id { 3288 SMU11_SYSPLL2_GFXCLK_ID = 0, // GFXCLK 3289 }; 3290 3291 enum atom_smu11_syspll3_0_clock_id { 3292 SMU11_SYSPLL3_0_WAFCLK_ID = 0, // WAFCLK 3293 SMU11_SYSPLL3_0_DISPCLK_ID = 1, // DISPCLK 3294 SMU11_SYSPLL3_0_DPREFCLK_ID = 2, // DPREFCLK 3295 }; 3296 3297 enum atom_smu11_syspll3_1_clock_id { 3298 SMU11_SYSPLL3_1_MP1CLK_ID = 0, // MP1CLK 3299 SMU11_SYSPLL3_1_SMNCLK_ID = 1, // SMNCLK 3300 SMU11_SYSPLL3_1_LCLK_ID = 2, // LCLK 3301 }; 3302 3303 struct atom_get_smu_clock_info_output_parameters_v3_1 3304 { 3305 union { 3306 uint32_t smu_clock_freq_hz; 3307 uint32_t syspllvcofreq_10khz; 3308 uint32_t sysspllrefclk_10khz; 3309 }atom_smu_outputclkfreq; 3310 }; 3311 3312 3313 3314 /* 3315 *************************************************************************** 3316 Structures used by dynamicmemorysettings 3317 *************************************************************************** 3318 */ 3319 3320 enum atom_dynamic_memory_setting_command 3321 { 3322 COMPUTE_MEMORY_PLL_PARAM = 1, 3323 COMPUTE_ENGINE_PLL_PARAM = 2, 3324 ADJUST_MC_SETTING_PARAM = 3, 3325 }; 3326 3327 /* when command = COMPUTE_MEMORY_PLL_PARAM or ADJUST_MC_SETTING_PARAM */ 3328 struct dynamic_mclk_settings_parameters_v2_1 3329 { 3330 uint32_t mclk_10khz:24; //Input= target mclk 3331 uint32_t command:8; //command enum of atom_dynamic_memory_setting_command 3332 uint32_t reserved; 3333 }; 3334 3335 /* when command = COMPUTE_ENGINE_PLL_PARAM */ 3336 struct dynamic_sclk_settings_parameters_v2_1 3337 { 3338 uint32_t sclk_10khz:24; //Input= target mclk 3339 uint32_t command:8; //command enum of atom_dynamic_memory_setting_command 3340 uint32_t mclk_10khz; 3341 uint32_t reserved; 3342 }; 3343 3344 union dynamic_memory_settings_parameters_v2_1 3345 { 3346 struct dynamic_mclk_settings_parameters_v2_1 mclk_setting; 3347 struct dynamic_sclk_settings_parameters_v2_1 sclk_setting; 3348 }; 3349 3350 3351 3352 /* 3353 *************************************************************************** 3354 Structures used by memorytraining 3355 *************************************************************************** 3356 */ 3357 3358 enum atom_umc6_0_ucode_function_call_enum_id 3359 { 3360 UMC60_UCODE_FUNC_ID_REINIT = 0, 3361 UMC60_UCODE_FUNC_ID_ENTER_SELFREFRESH = 1, 3362 UMC60_UCODE_FUNC_ID_EXIT_SELFREFRESH = 2, 3363 }; 3364 3365 3366 struct memory_training_parameters_v2_1 3367 { 3368 uint8_t ucode_func_id; 3369 uint8_t ucode_reserved[3]; 3370 uint32_t reserved[5]; 3371 }; 3372 3373 3374 /* 3375 *************************************************************************** 3376 Structures used by setpixelclock 3377 *************************************************************************** 3378 */ 3379 3380 struct set_pixel_clock_parameter_v1_7 3381 { 3382 uint32_t pixclk_100hz; // target the pixel clock to drive the CRTC timing in unit of 100Hz. 3383 3384 uint8_t pll_id; // ATOM_PHY_PLL0/ATOM_PHY_PLL1/ATOM_PPLL0 3385 uint8_t encoderobjid; // ASIC encoder id defined in objectId.h, 3386 // indicate which graphic encoder will be used. 3387 uint8_t encoder_mode; // Encoder mode: 3388 uint8_t miscinfo; // enum atom_set_pixel_clock_v1_7_misc_info 3389 uint8_t crtc_id; // enum of atom_crtc_def 3390 uint8_t deep_color_ratio; // HDMI panel bit depth: enum atom_set_pixel_clock_v1_7_deepcolor_ratio 3391 uint8_t reserved1[2]; 3392 uint32_t reserved2; 3393 }; 3394 3395 //ucMiscInfo 3396 enum atom_set_pixel_clock_v1_7_misc_info 3397 { 3398 PIXEL_CLOCK_V7_MISC_FORCE_PROG_PPLL = 0x01, 3399 PIXEL_CLOCK_V7_MISC_PROG_PHYPLL = 0x02, 3400 PIXEL_CLOCK_V7_MISC_YUV420_MODE = 0x04, 3401 PIXEL_CLOCK_V7_MISC_DVI_DUALLINK_EN = 0x08, 3402 PIXEL_CLOCK_V7_MISC_REF_DIV_SRC = 0x30, 3403 PIXEL_CLOCK_V7_MISC_REF_DIV_SRC_XTALIN = 0x00, 3404 PIXEL_CLOCK_V7_MISC_REF_DIV_SRC_PCIE = 0x10, 3405 PIXEL_CLOCK_V7_MISC_REF_DIV_SRC_GENLK = 0x20, 3406 PIXEL_CLOCK_V7_MISC_REF_DIV_SRC_REFPAD = 0x30, 3407 PIXEL_CLOCK_V7_MISC_ATOMIC_UPDATE = 0x40, 3408 PIXEL_CLOCK_V7_MISC_FORCE_SS_DIS = 0x80, 3409 }; 3410 3411 /* deep_color_ratio */ 3412 enum atom_set_pixel_clock_v1_7_deepcolor_ratio 3413 { 3414 PIXEL_CLOCK_V7_DEEPCOLOR_RATIO_DIS = 0x00, //00 - DCCG_DEEP_COLOR_DTO_DISABLE: Disable Deep Color DTO 3415 PIXEL_CLOCK_V7_DEEPCOLOR_RATIO_5_4 = 0x01, //01 - DCCG_DEEP_COLOR_DTO_5_4_RATIO: Set Deep Color DTO to 5:4 3416 PIXEL_CLOCK_V7_DEEPCOLOR_RATIO_3_2 = 0x02, //02 - DCCG_DEEP_COLOR_DTO_3_2_RATIO: Set Deep Color DTO to 3:2 3417 PIXEL_CLOCK_V7_DEEPCOLOR_RATIO_2_1 = 0x03, //03 - DCCG_DEEP_COLOR_DTO_2_1_RATIO: Set Deep Color DTO to 2:1 3418 }; 3419 3420 /* 3421 *************************************************************************** 3422 Structures used by setdceclock 3423 *************************************************************************** 3424 */ 3425 3426 // SetDCEClock input parameter for DCE11.2( ELM and BF ) and above 3427 struct set_dce_clock_parameters_v2_1 3428 { 3429 uint32_t dceclk_10khz; // target DCE frequency in unit of 10KHZ, return real DISPCLK/DPREFCLK frequency. 3430 uint8_t dceclktype; // =0: DISPCLK =1: DPREFCLK =2: PIXCLK 3431 uint8_t dceclksrc; // ATOM_PLL0 or ATOM_GCK_DFS or ATOM_FCH_CLK or ATOM_COMBOPHY_PLLx 3432 uint8_t dceclkflag; // Bit [1:0] = PPLL ref clock source ( when ucDCEClkSrc= ATOM_PPLL0 ) 3433 uint8_t crtc_id; // ucDisp Pipe Id, ATOM_CRTC0/1/2/..., use only when ucDCEClkType = PIXCLK 3434 }; 3435 3436 //ucDCEClkType 3437 enum atom_set_dce_clock_clock_type 3438 { 3439 DCE_CLOCK_TYPE_DISPCLK = 0, 3440 DCE_CLOCK_TYPE_DPREFCLK = 1, 3441 DCE_CLOCK_TYPE_PIXELCLK = 2, // used by VBIOS internally, called by SetPixelClock 3442 }; 3443 3444 //ucDCEClkFlag when ucDCEClkType == DPREFCLK 3445 enum atom_set_dce_clock_dprefclk_flag 3446 { 3447 DCE_CLOCK_FLAG_PLL_REFCLK_SRC_MASK = 0x03, 3448 DCE_CLOCK_FLAG_PLL_REFCLK_SRC_GENERICA = 0x00, 3449 DCE_CLOCK_FLAG_PLL_REFCLK_SRC_GENLK = 0x01, 3450 DCE_CLOCK_FLAG_PLL_REFCLK_SRC_PCIE = 0x02, 3451 DCE_CLOCK_FLAG_PLL_REFCLK_SRC_XTALIN = 0x03, 3452 }; 3453 3454 //ucDCEClkFlag when ucDCEClkType == PIXCLK 3455 enum atom_set_dce_clock_pixclk_flag 3456 { 3457 DCE_CLOCK_FLAG_PCLK_DEEPCOLOR_RATIO_MASK = 0x03, 3458 DCE_CLOCK_FLAG_PCLK_DEEPCOLOR_RATIO_DIS = 0x00, //00 - DCCG_DEEP_COLOR_DTO_DISABLE: Disable Deep Color DTO 3459 DCE_CLOCK_FLAG_PCLK_DEEPCOLOR_RATIO_5_4 = 0x01, //01 - DCCG_DEEP_COLOR_DTO_5_4_RATIO: Set Deep Color DTO to 5:4 3460 DCE_CLOCK_FLAG_PCLK_DEEPCOLOR_RATIO_3_2 = 0x02, //02 - DCCG_DEEP_COLOR_DTO_3_2_RATIO: Set Deep Color DTO to 3:2 3461 DCE_CLOCK_FLAG_PCLK_DEEPCOLOR_RATIO_2_1 = 0x03, //03 - DCCG_DEEP_COLOR_DTO_2_1_RATIO: Set Deep Color DTO to 2:1 3462 DCE_CLOCK_FLAG_PIXCLK_YUV420_MODE = 0x04, 3463 }; 3464 3465 struct set_dce_clock_ps_allocation_v2_1 3466 { 3467 struct set_dce_clock_parameters_v2_1 param; 3468 uint32_t ulReserved[2]; 3469 }; 3470 3471 3472 /****************************************************************************/ 3473 // Structures used by BlankCRTC 3474 /****************************************************************************/ 3475 struct blank_crtc_parameters 3476 { 3477 uint8_t crtc_id; // enum atom_crtc_def 3478 uint8_t blanking; // enum atom_blank_crtc_command 3479 uint16_t reserved; 3480 uint32_t reserved1; 3481 }; 3482 3483 enum atom_blank_crtc_command 3484 { 3485 ATOM_BLANKING = 1, 3486 ATOM_BLANKING_OFF = 0, 3487 }; 3488 3489 /****************************************************************************/ 3490 // Structures used by enablecrtc 3491 /****************************************************************************/ 3492 struct enable_crtc_parameters 3493 { 3494 uint8_t crtc_id; // enum atom_crtc_def 3495 uint8_t enable; // ATOM_ENABLE or ATOM_DISABLE 3496 uint8_t padding[2]; 3497 }; 3498 3499 3500 /****************************************************************************/ 3501 // Structure used by EnableDispPowerGating 3502 /****************************************************************************/ 3503 struct enable_disp_power_gating_parameters_v2_1 3504 { 3505 uint8_t disp_pipe_id; // ATOM_CRTC1, ATOM_CRTC2, ... 3506 uint8_t enable; // ATOM_ENABLE or ATOM_DISABLE 3507 uint8_t padding[2]; 3508 }; 3509 3510 struct enable_disp_power_gating_ps_allocation 3511 { 3512 struct enable_disp_power_gating_parameters_v2_1 param; 3513 uint32_t ulReserved[4]; 3514 }; 3515 3516 /****************************************************************************/ 3517 // Structure used in setcrtc_usingdtdtiming 3518 /****************************************************************************/ 3519 struct set_crtc_using_dtd_timing_parameters 3520 { 3521 uint16_t h_size; 3522 uint16_t h_blanking_time; 3523 uint16_t v_size; 3524 uint16_t v_blanking_time; 3525 uint16_t h_syncoffset; 3526 uint16_t h_syncwidth; 3527 uint16_t v_syncoffset; 3528 uint16_t v_syncwidth; 3529 uint16_t modemiscinfo; 3530 uint8_t h_border; 3531 uint8_t v_border; 3532 uint8_t crtc_id; // enum atom_crtc_def 3533 uint8_t encoder_mode; // atom_encode_mode_def 3534 uint8_t padding[2]; 3535 }; 3536 3537 3538 /****************************************************************************/ 3539 // Structures used by processi2cchanneltransaction 3540 /****************************************************************************/ 3541 struct process_i2c_channel_transaction_parameters 3542 { 3543 uint8_t i2cspeed_khz; 3544 union { 3545 uint8_t regindex; 3546 uint8_t status; /* enum atom_process_i2c_flag */ 3547 } regind_status; 3548 uint16_t i2c_data_out; 3549 uint8_t flag; /* enum atom_process_i2c_status */ 3550 uint8_t trans_bytes; 3551 uint8_t slave_addr; 3552 uint8_t i2c_id; 3553 }; 3554 3555 //ucFlag 3556 enum atom_process_i2c_flag 3557 { 3558 HW_I2C_WRITE = 1, 3559 HW_I2C_READ = 0, 3560 I2C_2BYTE_ADDR = 0x02, 3561 HW_I2C_SMBUS_BYTE_WR = 0x04, 3562 }; 3563 3564 //status 3565 enum atom_process_i2c_status 3566 { 3567 HW_ASSISTED_I2C_STATUS_FAILURE =2, 3568 HW_ASSISTED_I2C_STATUS_SUCCESS =1, 3569 }; 3570 3571 3572 /****************************************************************************/ 3573 // Structures used by processauxchanneltransaction 3574 /****************************************************************************/ 3575 3576 struct process_aux_channel_transaction_parameters_v1_2 3577 { 3578 uint16_t aux_request; 3579 uint16_t dataout; 3580 uint8_t channelid; 3581 union { 3582 uint8_t reply_status; 3583 uint8_t aux_delay; 3584 } aux_status_delay; 3585 uint8_t dataout_len; 3586 uint8_t hpd_id; //=0: HPD1, =1: HPD2, =2: HPD3, =3: HPD4, =4: HPD5, =5: HPD6 3587 }; 3588 3589 3590 /****************************************************************************/ 3591 // Structures used by selectcrtc_source 3592 /****************************************************************************/ 3593 3594 struct select_crtc_source_parameters_v2_3 3595 { 3596 uint8_t crtc_id; // enum atom_crtc_def 3597 uint8_t encoder_id; // enum atom_dig_def 3598 uint8_t encode_mode; // enum atom_encode_mode_def 3599 uint8_t dst_bpc; // enum atom_panel_bit_per_color 3600 }; 3601 3602 3603 /****************************************************************************/ 3604 // Structures used by digxencodercontrol 3605 /****************************************************************************/ 3606 3607 // ucAction: 3608 enum atom_dig_encoder_control_action 3609 { 3610 ATOM_ENCODER_CMD_DISABLE_DIG = 0, 3611 ATOM_ENCODER_CMD_ENABLE_DIG = 1, 3612 ATOM_ENCODER_CMD_DP_LINK_TRAINING_START = 0x08, 3613 ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN1 = 0x09, 3614 ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN2 = 0x0a, 3615 ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN3 = 0x13, 3616 ATOM_ENCODER_CMD_DP_LINK_TRAINING_COMPLETE = 0x0b, 3617 ATOM_ENCODER_CMD_DP_VIDEO_OFF = 0x0c, 3618 ATOM_ENCODER_CMD_DP_VIDEO_ON = 0x0d, 3619 ATOM_ENCODER_CMD_SETUP_PANEL_MODE = 0x10, 3620 ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN4 = 0x14, 3621 ATOM_ENCODER_CMD_STREAM_SETUP = 0x0F, 3622 ATOM_ENCODER_CMD_LINK_SETUP = 0x11, 3623 ATOM_ENCODER_CMD_ENCODER_BLANK = 0x12, 3624 }; 3625 3626 //define ucPanelMode 3627 enum atom_dig_encoder_control_panelmode 3628 { 3629 DP_PANEL_MODE_DISABLE = 0x00, 3630 DP_PANEL_MODE_ENABLE_eDP_MODE = 0x01, 3631 DP_PANEL_MODE_ENABLE_LVLINK_MODE = 0x11, 3632 }; 3633 3634 //ucDigId 3635 enum atom_dig_encoder_control_v5_digid 3636 { 3637 ATOM_ENCODER_CONFIG_V5_DIG0_ENCODER = 0x00, 3638 ATOM_ENCODER_CONFIG_V5_DIG1_ENCODER = 0x01, 3639 ATOM_ENCODER_CONFIG_V5_DIG2_ENCODER = 0x02, 3640 ATOM_ENCODER_CONFIG_V5_DIG3_ENCODER = 0x03, 3641 ATOM_ENCODER_CONFIG_V5_DIG4_ENCODER = 0x04, 3642 ATOM_ENCODER_CONFIG_V5_DIG5_ENCODER = 0x05, 3643 ATOM_ENCODER_CONFIG_V5_DIG6_ENCODER = 0x06, 3644 ATOM_ENCODER_CONFIG_V5_DIG7_ENCODER = 0x07, 3645 }; 3646 3647 struct dig_encoder_stream_setup_parameters_v1_5 3648 { 3649 uint8_t digid; // 0~6 map to DIG0~DIG6 enum atom_dig_encoder_control_v5_digid 3650 uint8_t action; // = ATOM_ENOCODER_CMD_STREAM_SETUP 3651 uint8_t digmode; // ATOM_ENCODER_MODE_DP/ATOM_ENCODER_MODE_DVI/ATOM_ENCODER_MODE_HDMI 3652 uint8_t lanenum; // Lane number 3653 uint32_t pclk_10khz; // Pixel Clock in 10Khz 3654 uint8_t bitpercolor; 3655 uint8_t dplinkrate_270mhz;//= DP link rate/270Mhz, =6: 1.62G = 10: 2.7G, =20: 5.4Ghz, =30: 8.1Ghz etc 3656 uint8_t reserved[2]; 3657 }; 3658 3659 struct dig_encoder_link_setup_parameters_v1_5 3660 { 3661 uint8_t digid; // 0~6 map to DIG0~DIG6 enum atom_dig_encoder_control_v5_digid 3662 uint8_t action; // = ATOM_ENOCODER_CMD_LINK_SETUP 3663 uint8_t digmode; // ATOM_ENCODER_MODE_DP/ATOM_ENCODER_MODE_DVI/ATOM_ENCODER_MODE_HDMI 3664 uint8_t lanenum; // Lane number 3665 uint8_t symclk_10khz; // Symbol Clock in 10Khz 3666 uint8_t hpd_sel; 3667 uint8_t digfe_sel; // DIG stream( front-end ) selection, bit0 means DIG0 FE is enable, 3668 uint8_t reserved[2]; 3669 }; 3670 3671 struct dp_panel_mode_set_parameters_v1_5 3672 { 3673 uint8_t digid; // 0~6 map to DIG0~DIG6 enum atom_dig_encoder_control_v5_digid 3674 uint8_t action; // = ATOM_ENCODER_CMD_DPLINK_SETUP 3675 uint8_t panelmode; // enum atom_dig_encoder_control_panelmode 3676 uint8_t reserved1; 3677 uint32_t reserved2[2]; 3678 }; 3679 3680 struct dig_encoder_generic_cmd_parameters_v1_5 3681 { 3682 uint8_t digid; // 0~6 map to DIG0~DIG6 enum atom_dig_encoder_control_v5_digid 3683 uint8_t action; // = rest of generic encoder command which does not carry any parameters 3684 uint8_t reserved1[2]; 3685 uint32_t reserved2[2]; 3686 }; 3687 3688 union dig_encoder_control_parameters_v1_5 3689 { 3690 struct dig_encoder_generic_cmd_parameters_v1_5 cmd_param; 3691 struct dig_encoder_stream_setup_parameters_v1_5 stream_param; 3692 struct dig_encoder_link_setup_parameters_v1_5 link_param; 3693 struct dp_panel_mode_set_parameters_v1_5 dppanel_param; 3694 }; 3695 3696 /* 3697 *************************************************************************** 3698 Structures used by dig1transmittercontrol 3699 *************************************************************************** 3700 */ 3701 struct dig_transmitter_control_parameters_v1_6 3702 { 3703 uint8_t phyid; // 0=UNIPHYA, 1=UNIPHYB, 2=UNIPHYC, 3=UNIPHYD, 4= UNIPHYE 5=UNIPHYF 3704 uint8_t action; // define as ATOM_TRANSMITER_ACTION_xxx 3705 union { 3706 uint8_t digmode; // enum atom_encode_mode_def 3707 uint8_t dplaneset; // DP voltage swing and pre-emphasis value defined in DPCD DP_LANE_SET, "DP_LANE_SET__xDB_y_zV" 3708 } mode_laneset; 3709 uint8_t lanenum; // Lane number 1, 2, 4, 8 3710 uint32_t symclk_10khz; // Symbol Clock in 10Khz 3711 uint8_t hpdsel; // =1: HPD1, =2: HPD2, .... =6: HPD6, =0: HPD is not assigned 3712 uint8_t digfe_sel; // DIG stream( front-end ) selection, bit0 means DIG0 FE is enable, 3713 uint8_t connobj_id; // Connector Object Id defined in ObjectId.h 3714 uint8_t reserved; 3715 uint32_t reserved1; 3716 }; 3717 3718 struct dig_transmitter_control_ps_allocation_v1_6 3719 { 3720 struct dig_transmitter_control_parameters_v1_6 param; 3721 uint32_t reserved[4]; 3722 }; 3723 3724 //ucAction 3725 enum atom_dig_transmitter_control_action 3726 { 3727 ATOM_TRANSMITTER_ACTION_DISABLE = 0, 3728 ATOM_TRANSMITTER_ACTION_ENABLE = 1, 3729 ATOM_TRANSMITTER_ACTION_LCD_BLOFF = 2, 3730 ATOM_TRANSMITTER_ACTION_LCD_BLON = 3, 3731 ATOM_TRANSMITTER_ACTION_BL_BRIGHTNESS_CONTROL = 4, 3732 ATOM_TRANSMITTER_ACTION_LCD_SELFTEST_START = 5, 3733 ATOM_TRANSMITTER_ACTION_LCD_SELFTEST_STOP = 6, 3734 ATOM_TRANSMITTER_ACTION_INIT = 7, 3735 ATOM_TRANSMITTER_ACTION_DISABLE_OUTPUT = 8, 3736 ATOM_TRANSMITTER_ACTION_ENABLE_OUTPUT = 9, 3737 ATOM_TRANSMITTER_ACTION_SETUP = 10, 3738 ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH = 11, 3739 ATOM_TRANSMITTER_ACTION_POWER_ON = 12, 3740 ATOM_TRANSMITTER_ACTION_POWER_OFF = 13, 3741 }; 3742 3743 // digfe_sel 3744 enum atom_dig_transmitter_control_digfe_sel 3745 { 3746 ATOM_TRANMSITTER_V6__DIGA_SEL = 0x01, 3747 ATOM_TRANMSITTER_V6__DIGB_SEL = 0x02, 3748 ATOM_TRANMSITTER_V6__DIGC_SEL = 0x04, 3749 ATOM_TRANMSITTER_V6__DIGD_SEL = 0x08, 3750 ATOM_TRANMSITTER_V6__DIGE_SEL = 0x10, 3751 ATOM_TRANMSITTER_V6__DIGF_SEL = 0x20, 3752 ATOM_TRANMSITTER_V6__DIGG_SEL = 0x40, 3753 }; 3754 3755 3756 //ucHPDSel 3757 enum atom_dig_transmitter_control_hpd_sel 3758 { 3759 ATOM_TRANSMITTER_V6_NO_HPD_SEL = 0x00, 3760 ATOM_TRANSMITTER_V6_HPD1_SEL = 0x01, 3761 ATOM_TRANSMITTER_V6_HPD2_SEL = 0x02, 3762 ATOM_TRANSMITTER_V6_HPD3_SEL = 0x03, 3763 ATOM_TRANSMITTER_V6_HPD4_SEL = 0x04, 3764 ATOM_TRANSMITTER_V6_HPD5_SEL = 0x05, 3765 ATOM_TRANSMITTER_V6_HPD6_SEL = 0x06, 3766 }; 3767 3768 // ucDPLaneSet 3769 enum atom_dig_transmitter_control_dplaneset 3770 { 3771 DP_LANE_SET__0DB_0_4V = 0x00, 3772 DP_LANE_SET__0DB_0_6V = 0x01, 3773 DP_LANE_SET__0DB_0_8V = 0x02, 3774 DP_LANE_SET__0DB_1_2V = 0x03, 3775 DP_LANE_SET__3_5DB_0_4V = 0x08, 3776 DP_LANE_SET__3_5DB_0_6V = 0x09, 3777 DP_LANE_SET__3_5DB_0_8V = 0x0a, 3778 DP_LANE_SET__6DB_0_4V = 0x10, 3779 DP_LANE_SET__6DB_0_6V = 0x11, 3780 DP_LANE_SET__9_5DB_0_4V = 0x18, 3781 }; 3782 3783 3784 3785 /****************************************************************************/ 3786 // Structures used by ExternalEncoderControl V2.4 3787 /****************************************************************************/ 3788 3789 struct external_encoder_control_parameters_v2_4 3790 { 3791 uint16_t pixelclock_10khz; // pixel clock in 10Khz, valid when ucAction=SETUP/ENABLE_OUTPUT 3792 uint8_t config; // indicate which encoder, and DP link rate when ucAction = SETUP/ENABLE_OUTPUT 3793 uint8_t action; // 3794 uint8_t encodermode; // encoder mode, only used when ucAction = SETUP/ENABLE_OUTPUT 3795 uint8_t lanenum; // lane number, only used when ucAction = SETUP/ENABLE_OUTPUT 3796 uint8_t bitpercolor; // output bit per color, only valid when ucAction = SETUP/ENABLE_OUTPUT and ucEncodeMode= DP 3797 uint8_t hpd_id; 3798 }; 3799 3800 3801 // ucAction 3802 enum external_encoder_control_action_def 3803 { 3804 EXTERNAL_ENCODER_ACTION_V3_DISABLE_OUTPUT = 0x00, 3805 EXTERNAL_ENCODER_ACTION_V3_ENABLE_OUTPUT = 0x01, 3806 EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT = 0x07, 3807 EXTERNAL_ENCODER_ACTION_V3_ENCODER_SETUP = 0x0f, 3808 EXTERNAL_ENCODER_ACTION_V3_ENCODER_BLANKING_OFF = 0x10, 3809 EXTERNAL_ENCODER_ACTION_V3_ENCODER_BLANKING = 0x11, 3810 EXTERNAL_ENCODER_ACTION_V3_DACLOAD_DETECTION = 0x12, 3811 EXTERNAL_ENCODER_ACTION_V3_DDC_SETUP = 0x14, 3812 }; 3813 3814 // ucConfig 3815 enum external_encoder_control_v2_4_config_def 3816 { 3817 EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_MASK = 0x03, 3818 EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_1_62GHZ = 0x00, 3819 EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ = 0x01, 3820 EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_5_40GHZ = 0x02, 3821 EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_3_24GHZ = 0x03, 3822 EXTERNAL_ENCODER_CONFIG_V3_ENCODER_SEL_MAKS = 0x70, 3823 EXTERNAL_ENCODER_CONFIG_V3_ENCODER1 = 0x00, 3824 EXTERNAL_ENCODER_CONFIG_V3_ENCODER2 = 0x10, 3825 EXTERNAL_ENCODER_CONFIG_V3_ENCODER3 = 0x20, 3826 }; 3827 3828 struct external_encoder_control_ps_allocation_v2_4 3829 { 3830 struct external_encoder_control_parameters_v2_4 sExtEncoder; 3831 uint32_t reserved[2]; 3832 }; 3833 3834 3835 /* 3836 *************************************************************************** 3837 AMD ACPI Table 3838 3839 *************************************************************************** 3840 */ 3841 3842 struct amd_acpi_description_header{ 3843 uint32_t signature; 3844 uint32_t tableLength; //Length 3845 uint8_t revision; 3846 uint8_t checksum; 3847 uint8_t oemId[6]; 3848 uint8_t oemTableId[8]; //UINT64 OemTableId; 3849 uint32_t oemRevision; 3850 uint32_t creatorId; 3851 uint32_t creatorRevision; 3852 }; 3853 3854 struct uefi_acpi_vfct{ 3855 struct amd_acpi_description_header sheader; 3856 uint8_t tableUUID[16]; //0x24 3857 uint32_t vbiosimageoffset; //0x34. Offset to the first GOP_VBIOS_CONTENT block from the beginning of the stucture. 3858 uint32_t lib1Imageoffset; //0x38. Offset to the first GOP_LIB1_CONTENT block from the beginning of the stucture. 3859 uint32_t reserved[4]; //0x3C 3860 }; 3861 3862 struct vfct_image_header{ 3863 uint32_t pcibus; //0x4C 3864 uint32_t pcidevice; //0x50 3865 uint32_t pcifunction; //0x54 3866 uint16_t vendorid; //0x58 3867 uint16_t deviceid; //0x5A 3868 uint16_t ssvid; //0x5C 3869 uint16_t ssid; //0x5E 3870 uint32_t revision; //0x60 3871 uint32_t imagelength; //0x64 3872 }; 3873 3874 3875 struct gop_vbios_content { 3876 struct vfct_image_header vbiosheader; 3877 uint8_t vbioscontent[1]; 3878 }; 3879 3880 struct gop_lib1_content { 3881 struct vfct_image_header lib1header; 3882 uint8_t lib1content[1]; 3883 }; 3884 3885 3886 3887 /* 3888 *************************************************************************** 3889 Scratch Register definitions 3890 Each number below indicates which scratch regiser request, Active and 3891 Connect all share the same definitions as display_device_tag defines 3892 *************************************************************************** 3893 */ 3894 3895 enum scratch_register_def{ 3896 ATOM_DEVICE_CONNECT_INFO_DEF = 0, 3897 ATOM_BL_BRI_LEVEL_INFO_DEF = 2, 3898 ATOM_ACTIVE_INFO_DEF = 3, 3899 ATOM_LCD_INFO_DEF = 4, 3900 ATOM_DEVICE_REQ_INFO_DEF = 5, 3901 ATOM_ACC_CHANGE_INFO_DEF = 6, 3902 ATOM_PRE_OS_MODE_INFO_DEF = 7, 3903 ATOM_PRE_OS_ASSERTION_DEF = 8, //For GOP to record a 32bit assertion code, this is enabled by default in prodution GOP drivers. 3904 ATOM_INTERNAL_TIMER_INFO_DEF = 10, 3905 }; 3906 3907 enum scratch_device_connect_info_bit_def{ 3908 ATOM_DISPLAY_LCD1_CONNECT =0x0002, 3909 ATOM_DISPLAY_DFP1_CONNECT =0x0008, 3910 ATOM_DISPLAY_DFP2_CONNECT =0x0080, 3911 ATOM_DISPLAY_DFP3_CONNECT =0x0200, 3912 ATOM_DISPLAY_DFP4_CONNECT =0x0400, 3913 ATOM_DISPLAY_DFP5_CONNECT =0x0800, 3914 ATOM_DISPLAY_DFP6_CONNECT =0x0040, 3915 ATOM_DISPLAY_DFPx_CONNECT =0x0ec8, 3916 ATOM_CONNECT_INFO_DEVICE_MASK =0x0fff, 3917 }; 3918 3919 enum scratch_bl_bri_level_info_bit_def{ 3920 ATOM_CURRENT_BL_LEVEL_SHIFT =0x8, 3921 #ifndef _H2INC 3922 ATOM_CURRENT_BL_LEVEL_MASK =0x0000ff00, 3923 ATOM_DEVICE_DPMS_STATE =0x00010000, 3924 #endif 3925 }; 3926 3927 enum scratch_active_info_bits_def{ 3928 ATOM_DISPLAY_LCD1_ACTIVE =0x0002, 3929 ATOM_DISPLAY_DFP1_ACTIVE =0x0008, 3930 ATOM_DISPLAY_DFP2_ACTIVE =0x0080, 3931 ATOM_DISPLAY_DFP3_ACTIVE =0x0200, 3932 ATOM_DISPLAY_DFP4_ACTIVE =0x0400, 3933 ATOM_DISPLAY_DFP5_ACTIVE =0x0800, 3934 ATOM_DISPLAY_DFP6_ACTIVE =0x0040, 3935 ATOM_ACTIVE_INFO_DEVICE_MASK =0x0fff, 3936 }; 3937 3938 enum scratch_device_req_info_bits_def{ 3939 ATOM_DISPLAY_LCD1_REQ =0x0002, 3940 ATOM_DISPLAY_DFP1_REQ =0x0008, 3941 ATOM_DISPLAY_DFP2_REQ =0x0080, 3942 ATOM_DISPLAY_DFP3_REQ =0x0200, 3943 ATOM_DISPLAY_DFP4_REQ =0x0400, 3944 ATOM_DISPLAY_DFP5_REQ =0x0800, 3945 ATOM_DISPLAY_DFP6_REQ =0x0040, 3946 ATOM_REQ_INFO_DEVICE_MASK =0x0fff, 3947 }; 3948 3949 enum scratch_acc_change_info_bitshift_def{ 3950 ATOM_ACC_CHANGE_ACC_MODE_SHIFT =4, 3951 ATOM_ACC_CHANGE_LID_STATUS_SHIFT =6, 3952 }; 3953 3954 enum scratch_acc_change_info_bits_def{ 3955 ATOM_ACC_CHANGE_ACC_MODE =0x00000010, 3956 ATOM_ACC_CHANGE_LID_STATUS =0x00000040, 3957 }; 3958 3959 enum scratch_pre_os_mode_info_bits_def{ 3960 ATOM_PRE_OS_MODE_MASK =0x00000003, 3961 ATOM_PRE_OS_MODE_VGA =0x00000000, 3962 ATOM_PRE_OS_MODE_VESA =0x00000001, 3963 ATOM_PRE_OS_MODE_GOP =0x00000002, 3964 ATOM_PRE_OS_MODE_PIXEL_DEPTH =0x0000000C, 3965 ATOM_PRE_OS_MODE_PIXEL_FORMAT_MASK=0x000000F0, 3966 ATOM_PRE_OS_MODE_8BIT_PAL_EN =0x00000100, 3967 ATOM_ASIC_INIT_COMPLETE =0x00000200, 3968 #ifndef _H2INC 3969 ATOM_PRE_OS_MODE_NUMBER_MASK =0xFFFF0000, 3970 #endif 3971 }; 3972 3973 3974 3975 /* 3976 *************************************************************************** 3977 ATOM firmware ID header file 3978 !! Please keep it at end of the atomfirmware.h !! 3979 *************************************************************************** 3980 */ 3981 #include "atomfirmwareid.h" 3982 #pragma pack() 3983 3984 #endif 3985 3986