1 /****************************************************************************\ 2 * 3 * File Name atomfirmware.h 4 * Project This is an interface header file between atombios and OS GPU drivers for SoC15 products 5 * 6 * Description header file of general definitions for OS and pre-OS video drivers 7 * 8 * Copyright 2014 Advanced Micro Devices, Inc. 9 * 10 * Permission is hereby granted, free of charge, to any person obtaining a copy of this software 11 * and associated documentation files (the "Software"), to deal in the Software without restriction, 12 * including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, 13 * and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, 14 * subject to the following conditions: 15 * 16 * The above copyright notice and this permission notice shall be included in all copies or substantial 17 * portions of the Software. 18 * 19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 22 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 23 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 24 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 25 * OTHER DEALINGS IN THE SOFTWARE. 26 * 27 \****************************************************************************/ 28 29 /*IMPORTANT NOTES 30 * If a change in VBIOS/Driver/Tool's interface is only needed for SoC15 and forward products, then the change is only needed in this atomfirmware.h header file. 31 * If a change in VBIOS/Driver/Tool's interface is only needed for pre-SoC15 products, then the change is only needed in atombios.h header file. 32 * If a change is needed for both pre and post SoC15 products, then the change has to be made separately and might be differently in both atomfirmware.h and atombios.h. 33 */ 34 35 #ifndef _ATOMFIRMWARE_H_ 36 #define _ATOMFIRMWARE_H_ 37 38 enum atom_bios_header_version_def{ 39 ATOM_MAJOR_VERSION =0x0003, 40 ATOM_MINOR_VERSION =0x0003, 41 }; 42 43 #ifdef _H2INC 44 #ifndef uint32_t 45 typedef unsigned long uint32_t; 46 #endif 47 48 #ifndef uint16_t 49 typedef unsigned short uint16_t; 50 #endif 51 52 #ifndef uint8_t 53 typedef unsigned char uint8_t; 54 #endif 55 #endif 56 57 enum atom_crtc_def{ 58 ATOM_CRTC1 =0, 59 ATOM_CRTC2 =1, 60 ATOM_CRTC3 =2, 61 ATOM_CRTC4 =3, 62 ATOM_CRTC5 =4, 63 ATOM_CRTC6 =5, 64 ATOM_CRTC_INVALID =0xff, 65 }; 66 67 enum atom_ppll_def{ 68 ATOM_PPLL0 =2, 69 ATOM_GCK_DFS =8, 70 ATOM_FCH_CLK =9, 71 ATOM_DP_DTO =11, 72 ATOM_COMBOPHY_PLL0 =20, 73 ATOM_COMBOPHY_PLL1 =21, 74 ATOM_COMBOPHY_PLL2 =22, 75 ATOM_COMBOPHY_PLL3 =23, 76 ATOM_COMBOPHY_PLL4 =24, 77 ATOM_COMBOPHY_PLL5 =25, 78 ATOM_PPLL_INVALID =0xff, 79 }; 80 81 // define ASIC internal encoder id ( bit vector ), used for CRTC_SourceSel 82 enum atom_dig_def{ 83 ASIC_INT_DIG1_ENCODER_ID =0x03, 84 ASIC_INT_DIG2_ENCODER_ID =0x09, 85 ASIC_INT_DIG3_ENCODER_ID =0x0a, 86 ASIC_INT_DIG4_ENCODER_ID =0x0b, 87 ASIC_INT_DIG5_ENCODER_ID =0x0c, 88 ASIC_INT_DIG6_ENCODER_ID =0x0d, 89 ASIC_INT_DIG7_ENCODER_ID =0x0e, 90 }; 91 92 //ucEncoderMode 93 enum atom_encode_mode_def 94 { 95 ATOM_ENCODER_MODE_DP =0, 96 ATOM_ENCODER_MODE_DP_SST =0, 97 ATOM_ENCODER_MODE_LVDS =1, 98 ATOM_ENCODER_MODE_DVI =2, 99 ATOM_ENCODER_MODE_HDMI =3, 100 ATOM_ENCODER_MODE_DP_AUDIO =5, 101 ATOM_ENCODER_MODE_DP_MST =5, 102 ATOM_ENCODER_MODE_CRT =15, 103 ATOM_ENCODER_MODE_DVO =16, 104 }; 105 106 enum atom_encoder_refclk_src_def{ 107 ENCODER_REFCLK_SRC_P1PLL =0, 108 ENCODER_REFCLK_SRC_P2PLL =1, 109 ENCODER_REFCLK_SRC_P3PLL =2, 110 ENCODER_REFCLK_SRC_EXTCLK =3, 111 ENCODER_REFCLK_SRC_INVALID =0xff, 112 }; 113 114 enum atom_scaler_def{ 115 ATOM_SCALER_DISABLE =0, /*scaler bypass mode, auto-center & no replication*/ 116 ATOM_SCALER_CENTER =1, //For Fudo, it's bypass and auto-center & auto replication 117 ATOM_SCALER_EXPANSION =2, /*scaler expansion by 2 tap alpha blending mode*/ 118 }; 119 120 enum atom_operation_def{ 121 ATOM_DISABLE = 0, 122 ATOM_ENABLE = 1, 123 ATOM_INIT = 7, 124 ATOM_GET_STATUS = 8, 125 }; 126 127 enum atom_embedded_display_op_def{ 128 ATOM_LCD_BL_OFF = 2, 129 ATOM_LCD_BL_OM = 3, 130 ATOM_LCD_BL_BRIGHTNESS_CONTROL = 4, 131 ATOM_LCD_SELFTEST_START = 5, 132 ATOM_LCD_SELFTEST_STOP = 6, 133 }; 134 135 enum atom_spread_spectrum_mode{ 136 ATOM_SS_CENTER_OR_DOWN_MODE_MASK = 0x01, 137 ATOM_SS_DOWN_SPREAD_MODE = 0x00, 138 ATOM_SS_CENTRE_SPREAD_MODE = 0x01, 139 ATOM_INT_OR_EXT_SS_MASK = 0x02, 140 ATOM_INTERNAL_SS_MASK = 0x00, 141 ATOM_EXTERNAL_SS_MASK = 0x02, 142 }; 143 144 /* define panel bit per color */ 145 enum atom_panel_bit_per_color{ 146 PANEL_BPC_UNDEFINE =0x00, 147 PANEL_6BIT_PER_COLOR =0x01, 148 PANEL_8BIT_PER_COLOR =0x02, 149 PANEL_10BIT_PER_COLOR =0x03, 150 PANEL_12BIT_PER_COLOR =0x04, 151 PANEL_16BIT_PER_COLOR =0x05, 152 }; 153 154 //ucVoltageType 155 enum atom_voltage_type 156 { 157 VOLTAGE_TYPE_VDDC = 1, 158 VOLTAGE_TYPE_MVDDC = 2, 159 VOLTAGE_TYPE_MVDDQ = 3, 160 VOLTAGE_TYPE_VDDCI = 4, 161 VOLTAGE_TYPE_VDDGFX = 5, 162 VOLTAGE_TYPE_PCC = 6, 163 VOLTAGE_TYPE_MVPP = 7, 164 VOLTAGE_TYPE_LEDDPM = 8, 165 VOLTAGE_TYPE_PCC_MVDD = 9, 166 VOLTAGE_TYPE_PCIE_VDDC = 10, 167 VOLTAGE_TYPE_PCIE_VDDR = 11, 168 VOLTAGE_TYPE_GENERIC_I2C_1 = 0x11, 169 VOLTAGE_TYPE_GENERIC_I2C_2 = 0x12, 170 VOLTAGE_TYPE_GENERIC_I2C_3 = 0x13, 171 VOLTAGE_TYPE_GENERIC_I2C_4 = 0x14, 172 VOLTAGE_TYPE_GENERIC_I2C_5 = 0x15, 173 VOLTAGE_TYPE_GENERIC_I2C_6 = 0x16, 174 VOLTAGE_TYPE_GENERIC_I2C_7 = 0x17, 175 VOLTAGE_TYPE_GENERIC_I2C_8 = 0x18, 176 VOLTAGE_TYPE_GENERIC_I2C_9 = 0x19, 177 VOLTAGE_TYPE_GENERIC_I2C_10 = 0x1A, 178 }; 179 180 enum atom_dgpu_vram_type { 181 ATOM_DGPU_VRAM_TYPE_GDDR5 = 0x50, 182 ATOM_DGPU_VRAM_TYPE_HBM2 = 0x60, 183 ATOM_DGPU_VRAM_TYPE_HBM2E = 0x61, 184 ATOM_DGPU_VRAM_TYPE_GDDR6 = 0x70, 185 ATOM_DGPU_VRAM_TYPE_HBM3 = 0x80, 186 }; 187 188 enum atom_dp_vs_preemph_def{ 189 DP_VS_LEVEL0_PREEMPH_LEVEL0 = 0x00, 190 DP_VS_LEVEL1_PREEMPH_LEVEL0 = 0x01, 191 DP_VS_LEVEL2_PREEMPH_LEVEL0 = 0x02, 192 DP_VS_LEVEL3_PREEMPH_LEVEL0 = 0x03, 193 DP_VS_LEVEL0_PREEMPH_LEVEL1 = 0x08, 194 DP_VS_LEVEL1_PREEMPH_LEVEL1 = 0x09, 195 DP_VS_LEVEL2_PREEMPH_LEVEL1 = 0x0a, 196 DP_VS_LEVEL0_PREEMPH_LEVEL2 = 0x10, 197 DP_VS_LEVEL1_PREEMPH_LEVEL2 = 0x11, 198 DP_VS_LEVEL0_PREEMPH_LEVEL3 = 0x18, 199 }; 200 201 #define BIOS_ATOM_PREFIX "ATOMBIOS" 202 #define BIOS_VERSION_PREFIX "ATOMBIOSBK-AMD" 203 #define BIOS_STRING_LENGTH 43 204 205 /* 206 enum atom_string_def{ 207 asic_bus_type_pcie_string = "PCI_EXPRESS", 208 atom_fire_gl_string = "FGL", 209 atom_bios_string = "ATOM" 210 }; 211 */ 212 213 #pragma pack(1) /* BIOS data must use byte aligment*/ 214 215 enum atombios_image_offset{ 216 OFFSET_TO_ATOM_ROM_HEADER_POINTER = 0x00000048, 217 OFFSET_TO_ATOM_ROM_IMAGE_SIZE = 0x00000002, 218 OFFSET_TO_ATOMBIOS_ASIC_BUS_MEM_TYPE = 0x94, 219 MAXSIZE_OF_ATOMBIOS_ASIC_BUS_MEM_TYPE = 20, /*including the terminator 0x0!*/ 220 OFFSET_TO_GET_ATOMBIOS_NUMBER_OF_STRINGS = 0x2f, 221 OFFSET_TO_GET_ATOMBIOS_STRING_START = 0x6e, 222 OFFSET_TO_VBIOS_PART_NUMBER = 0x80, 223 OFFSET_TO_VBIOS_DATE = 0x50, 224 }; 225 226 /**************************************************************************** 227 * Common header for all tables (Data table, Command function). 228 * Every table pointed in _ATOM_MASTER_DATA_TABLE has this common header. 229 * And the pointer actually points to this header. 230 ****************************************************************************/ 231 232 struct atom_common_table_header 233 { 234 uint16_t structuresize; 235 uint8_t format_revision; //mainly used for a hw function, when the parser is not backward compatible 236 uint8_t content_revision; //change it when a data table has a structure change, or a hw function has a input/output parameter change 237 }; 238 239 /**************************************************************************** 240 * Structure stores the ROM header. 241 ****************************************************************************/ 242 struct atom_rom_header_v2_2 243 { 244 struct atom_common_table_header table_header; 245 uint8_t atom_bios_string[4]; //enum atom_string_def atom_bios_string; //Signature to distinguish between Atombios and non-atombios, 246 uint16_t bios_segment_address; 247 uint16_t protectedmodeoffset; 248 uint16_t configfilenameoffset; 249 uint16_t crc_block_offset; 250 uint16_t vbios_bootupmessageoffset; 251 uint16_t int10_offset; 252 uint16_t pcibusdevinitcode; 253 uint16_t iobaseaddress; 254 uint16_t subsystem_vendor_id; 255 uint16_t subsystem_id; 256 uint16_t pci_info_offset; 257 uint16_t masterhwfunction_offset; //Offest for SW to get all command function offsets, Don't change the position 258 uint16_t masterdatatable_offset; //Offest for SW to get all data table offsets, Don't change the position 259 uint16_t reserved; 260 uint32_t pspdirtableoffset; 261 }; 262 263 /*==============================hw function portion======================================================================*/ 264 265 266 /**************************************************************************** 267 * Structures used in Command.mtb, each function name is not given here since those function could change from time to time 268 * The real functionality of each function is associated with the parameter structure version when defined 269 * For all internal cmd function definitions, please reference to atomstruct.h 270 ****************************************************************************/ 271 struct atom_master_list_of_command_functions_v2_1{ 272 uint16_t asic_init; //Function 273 uint16_t cmd_function1; //used as an internal one 274 uint16_t cmd_function2; //used as an internal one 275 uint16_t cmd_function3; //used as an internal one 276 uint16_t digxencodercontrol; //Function 277 uint16_t cmd_function5; //used as an internal one 278 uint16_t cmd_function6; //used as an internal one 279 uint16_t cmd_function7; //used as an internal one 280 uint16_t cmd_function8; //used as an internal one 281 uint16_t cmd_function9; //used as an internal one 282 uint16_t setengineclock; //Function 283 uint16_t setmemoryclock; //Function 284 uint16_t setpixelclock; //Function 285 uint16_t enabledisppowergating; //Function 286 uint16_t cmd_function14; //used as an internal one 287 uint16_t cmd_function15; //used as an internal one 288 uint16_t cmd_function16; //used as an internal one 289 uint16_t cmd_function17; //used as an internal one 290 uint16_t cmd_function18; //used as an internal one 291 uint16_t cmd_function19; //used as an internal one 292 uint16_t cmd_function20; //used as an internal one 293 uint16_t cmd_function21; //used as an internal one 294 uint16_t cmd_function22; //used as an internal one 295 uint16_t cmd_function23; //used as an internal one 296 uint16_t cmd_function24; //used as an internal one 297 uint16_t cmd_function25; //used as an internal one 298 uint16_t cmd_function26; //used as an internal one 299 uint16_t cmd_function27; //used as an internal one 300 uint16_t cmd_function28; //used as an internal one 301 uint16_t cmd_function29; //used as an internal one 302 uint16_t cmd_function30; //used as an internal one 303 uint16_t cmd_function31; //used as an internal one 304 uint16_t cmd_function32; //used as an internal one 305 uint16_t cmd_function33; //used as an internal one 306 uint16_t blankcrtc; //Function 307 uint16_t enablecrtc; //Function 308 uint16_t cmd_function36; //used as an internal one 309 uint16_t cmd_function37; //used as an internal one 310 uint16_t cmd_function38; //used as an internal one 311 uint16_t cmd_function39; //used as an internal one 312 uint16_t cmd_function40; //used as an internal one 313 uint16_t getsmuclockinfo; //Function 314 uint16_t selectcrtc_source; //Function 315 uint16_t cmd_function43; //used as an internal one 316 uint16_t cmd_function44; //used as an internal one 317 uint16_t cmd_function45; //used as an internal one 318 uint16_t setdceclock; //Function 319 uint16_t getmemoryclock; //Function 320 uint16_t getengineclock; //Function 321 uint16_t setcrtc_usingdtdtiming; //Function 322 uint16_t externalencodercontrol; //Function 323 uint16_t cmd_function51; //used as an internal one 324 uint16_t cmd_function52; //used as an internal one 325 uint16_t cmd_function53; //used as an internal one 326 uint16_t processi2cchanneltransaction;//Function 327 uint16_t cmd_function55; //used as an internal one 328 uint16_t cmd_function56; //used as an internal one 329 uint16_t cmd_function57; //used as an internal one 330 uint16_t cmd_function58; //used as an internal one 331 uint16_t cmd_function59; //used as an internal one 332 uint16_t computegpuclockparam; //Function 333 uint16_t cmd_function61; //used as an internal one 334 uint16_t cmd_function62; //used as an internal one 335 uint16_t dynamicmemorysettings; //Function function 336 uint16_t memorytraining; //Function function 337 uint16_t cmd_function65; //used as an internal one 338 uint16_t cmd_function66; //used as an internal one 339 uint16_t setvoltage; //Function 340 uint16_t cmd_function68; //used as an internal one 341 uint16_t readefusevalue; //Function 342 uint16_t cmd_function70; //used as an internal one 343 uint16_t cmd_function71; //used as an internal one 344 uint16_t cmd_function72; //used as an internal one 345 uint16_t cmd_function73; //used as an internal one 346 uint16_t cmd_function74; //used as an internal one 347 uint16_t cmd_function75; //used as an internal one 348 uint16_t dig1transmittercontrol; //Function 349 uint16_t cmd_function77; //used as an internal one 350 uint16_t processauxchanneltransaction;//Function 351 uint16_t cmd_function79; //used as an internal one 352 uint16_t getvoltageinfo; //Function 353 }; 354 355 struct atom_master_command_function_v2_1 356 { 357 struct atom_common_table_header table_header; 358 struct atom_master_list_of_command_functions_v2_1 listofcmdfunctions; 359 }; 360 361 /**************************************************************************** 362 * Structures used in every command function 363 ****************************************************************************/ 364 struct atom_function_attribute 365 { 366 uint16_t ws_in_bytes:8; //[7:0]=Size of workspace in Bytes (in multiple of a dword), 367 uint16_t ps_in_bytes:7; //[14:8]=Size of parameter space in Bytes (multiple of a dword), 368 uint16_t updated_by_util:1; //[15]=flag to indicate the function is updated by util 369 }; 370 371 372 /**************************************************************************** 373 * Common header for all hw functions. 374 * Every function pointed by _master_list_of_hw_function has this common header. 375 * And the pointer actually points to this header. 376 ****************************************************************************/ 377 struct atom_rom_hw_function_header 378 { 379 struct atom_common_table_header func_header; 380 struct atom_function_attribute func_attrib; 381 }; 382 383 384 /*==============================sw data table portion======================================================================*/ 385 /**************************************************************************** 386 * Structures used in data.mtb, each data table name is not given here since those data table could change from time to time 387 * The real name of each table is given when its data structure version is defined 388 ****************************************************************************/ 389 struct atom_master_list_of_data_tables_v2_1{ 390 uint16_t utilitypipeline; /* Offest for the utility to get parser info,Don't change this position!*/ 391 uint16_t multimedia_info; 392 uint16_t smc_dpm_info; 393 uint16_t sw_datatable3; 394 uint16_t firmwareinfo; /* Shared by various SW components */ 395 uint16_t sw_datatable5; 396 uint16_t lcd_info; /* Shared by various SW components */ 397 uint16_t sw_datatable7; 398 uint16_t smu_info; 399 uint16_t sw_datatable9; 400 uint16_t sw_datatable10; 401 uint16_t vram_usagebyfirmware; /* Shared by various SW components */ 402 uint16_t gpio_pin_lut; /* Shared by various SW components */ 403 uint16_t sw_datatable13; 404 uint16_t gfx_info; 405 uint16_t powerplayinfo; /* Shared by various SW components */ 406 uint16_t sw_datatable16; 407 uint16_t sw_datatable17; 408 uint16_t sw_datatable18; 409 uint16_t sw_datatable19; 410 uint16_t sw_datatable20; 411 uint16_t sw_datatable21; 412 uint16_t displayobjectinfo; /* Shared by various SW components */ 413 uint16_t indirectioaccess; /* used as an internal one */ 414 uint16_t umc_info; /* Shared by various SW components */ 415 uint16_t sw_datatable25; 416 uint16_t sw_datatable26; 417 uint16_t dce_info; /* Shared by various SW components */ 418 uint16_t vram_info; /* Shared by various SW components */ 419 uint16_t sw_datatable29; 420 uint16_t integratedsysteminfo; /* Shared by various SW components */ 421 uint16_t asic_profiling_info; /* Shared by various SW components */ 422 uint16_t voltageobject_info; /* shared by various SW components */ 423 uint16_t sw_datatable33; 424 uint16_t sw_datatable34; 425 }; 426 427 428 struct atom_master_data_table_v2_1 429 { 430 struct atom_common_table_header table_header; 431 struct atom_master_list_of_data_tables_v2_1 listOfdatatables; 432 }; 433 434 435 struct atom_dtd_format 436 { 437 uint16_t pixclk; 438 uint16_t h_active; 439 uint16_t h_blanking_time; 440 uint16_t v_active; 441 uint16_t v_blanking_time; 442 uint16_t h_sync_offset; 443 uint16_t h_sync_width; 444 uint16_t v_sync_offset; 445 uint16_t v_syncwidth; 446 uint16_t reserved; 447 uint16_t reserved0; 448 uint8_t h_border; 449 uint8_t v_border; 450 uint16_t miscinfo; 451 uint8_t atom_mode_id; 452 uint8_t refreshrate; 453 }; 454 455 /* atom_dtd_format.modemiscinfo defintion */ 456 enum atom_dtd_format_modemiscinfo{ 457 ATOM_HSYNC_POLARITY = 0x0002, 458 ATOM_VSYNC_POLARITY = 0x0004, 459 ATOM_H_REPLICATIONBY2 = 0x0010, 460 ATOM_V_REPLICATIONBY2 = 0x0020, 461 ATOM_INTERLACE = 0x0080, 462 ATOM_COMPOSITESYNC = 0x0040, 463 }; 464 465 466 /* utilitypipeline 467 * when format_revision==1 && content_revision==1, then this an info table for atomworks to use during debug session, no structure is associated with it. 468 * the location of it can't change 469 */ 470 471 472 /* 473 *************************************************************************** 474 Data Table firmwareinfo structure 475 *************************************************************************** 476 */ 477 478 struct atom_firmware_info_v3_1 479 { 480 struct atom_common_table_header table_header; 481 uint32_t firmware_revision; 482 uint32_t bootup_sclk_in10khz; 483 uint32_t bootup_mclk_in10khz; 484 uint32_t firmware_capability; // enum atombios_firmware_capability 485 uint32_t main_call_parser_entry; /* direct address of main parser call in VBIOS binary. */ 486 uint32_t bios_scratch_reg_startaddr; // 1st bios scratch register dword address 487 uint16_t bootup_vddc_mv; 488 uint16_t bootup_vddci_mv; 489 uint16_t bootup_mvddc_mv; 490 uint16_t bootup_vddgfx_mv; 491 uint8_t mem_module_id; 492 uint8_t coolingsolution_id; /*0: Air cooling; 1: Liquid cooling ... */ 493 uint8_t reserved1[2]; 494 uint32_t mc_baseaddr_high; 495 uint32_t mc_baseaddr_low; 496 uint32_t reserved2[6]; 497 }; 498 499 /* Total 32bit cap indication */ 500 enum atombios_firmware_capability 501 { 502 ATOM_FIRMWARE_CAP_FIRMWARE_POSTED = 0x00000001, 503 ATOM_FIRMWARE_CAP_GPU_VIRTUALIZATION = 0x00000002, 504 ATOM_FIRMWARE_CAP_WMI_SUPPORT = 0x00000040, 505 ATOM_FIRMWARE_CAP_HWEMU_ENABLE = 0x00000080, 506 ATOM_FIRMWARE_CAP_HWEMU_UMC_CFG = 0x00000100, 507 ATOM_FIRMWARE_CAP_SRAM_ECC = 0x00000200, 508 ATOM_FIRMWARE_CAP_ENABLE_2STAGE_BIST_TRAINING = 0x00000400, 509 ATOM_FIRMWARE_CAP_ENABLE_2ND_USB20PORT = 0x0008000, 510 ATOM_FIRMWARE_CAP_DYNAMIC_BOOT_CFG_ENABLE = 0x0020000, 511 }; 512 513 enum atom_cooling_solution_id{ 514 AIR_COOLING = 0x00, 515 LIQUID_COOLING = 0x01 516 }; 517 518 struct atom_firmware_info_v3_2 { 519 struct atom_common_table_header table_header; 520 uint32_t firmware_revision; 521 uint32_t bootup_sclk_in10khz; 522 uint32_t bootup_mclk_in10khz; 523 uint32_t firmware_capability; // enum atombios_firmware_capability 524 uint32_t main_call_parser_entry; /* direct address of main parser call in VBIOS binary. */ 525 uint32_t bios_scratch_reg_startaddr; // 1st bios scratch register dword address 526 uint16_t bootup_vddc_mv; 527 uint16_t bootup_vddci_mv; 528 uint16_t bootup_mvddc_mv; 529 uint16_t bootup_vddgfx_mv; 530 uint8_t mem_module_id; 531 uint8_t coolingsolution_id; /*0: Air cooling; 1: Liquid cooling ... */ 532 uint8_t reserved1[2]; 533 uint32_t mc_baseaddr_high; 534 uint32_t mc_baseaddr_low; 535 uint8_t board_i2c_feature_id; // enum of atom_board_i2c_feature_id_def 536 uint8_t board_i2c_feature_gpio_id; // i2c id find in gpio_lut data table gpio_id 537 uint8_t board_i2c_feature_slave_addr; 538 uint8_t reserved3; 539 uint16_t bootup_mvddq_mv; 540 uint16_t bootup_mvpp_mv; 541 uint32_t zfbstartaddrin16mb; 542 uint32_t reserved2[3]; 543 }; 544 545 struct atom_firmware_info_v3_3 546 { 547 struct atom_common_table_header table_header; 548 uint32_t firmware_revision; 549 uint32_t bootup_sclk_in10khz; 550 uint32_t bootup_mclk_in10khz; 551 uint32_t firmware_capability; // enum atombios_firmware_capability 552 uint32_t main_call_parser_entry; /* direct address of main parser call in VBIOS binary. */ 553 uint32_t bios_scratch_reg_startaddr; // 1st bios scratch register dword address 554 uint16_t bootup_vddc_mv; 555 uint16_t bootup_vddci_mv; 556 uint16_t bootup_mvddc_mv; 557 uint16_t bootup_vddgfx_mv; 558 uint8_t mem_module_id; 559 uint8_t coolingsolution_id; /*0: Air cooling; 1: Liquid cooling ... */ 560 uint8_t reserved1[2]; 561 uint32_t mc_baseaddr_high; 562 uint32_t mc_baseaddr_low; 563 uint8_t board_i2c_feature_id; // enum of atom_board_i2c_feature_id_def 564 uint8_t board_i2c_feature_gpio_id; // i2c id find in gpio_lut data table gpio_id 565 uint8_t board_i2c_feature_slave_addr; 566 uint8_t reserved3; 567 uint16_t bootup_mvddq_mv; 568 uint16_t bootup_mvpp_mv; 569 uint32_t zfbstartaddrin16mb; 570 uint32_t pplib_pptable_id; // if pplib_pptable_id!=0, pplib get powerplay table inside driver instead of from VBIOS 571 uint32_t reserved2[2]; 572 }; 573 574 struct atom_firmware_info_v3_4 { 575 struct atom_common_table_header table_header; 576 uint32_t firmware_revision; 577 uint32_t bootup_sclk_in10khz; 578 uint32_t bootup_mclk_in10khz; 579 uint32_t firmware_capability; // enum atombios_firmware_capability 580 uint32_t main_call_parser_entry; /* direct address of main parser call in VBIOS binary. */ 581 uint32_t bios_scratch_reg_startaddr; // 1st bios scratch register dword address 582 uint16_t bootup_vddc_mv; 583 uint16_t bootup_vddci_mv; 584 uint16_t bootup_mvddc_mv; 585 uint16_t bootup_vddgfx_mv; 586 uint8_t mem_module_id; 587 uint8_t coolingsolution_id; /*0: Air cooling; 1: Liquid cooling ... */ 588 uint8_t reserved1[2]; 589 uint32_t mc_baseaddr_high; 590 uint32_t mc_baseaddr_low; 591 uint8_t board_i2c_feature_id; // enum of atom_board_i2c_feature_id_def 592 uint8_t board_i2c_feature_gpio_id; // i2c id find in gpio_lut data table gpio_id 593 uint8_t board_i2c_feature_slave_addr; 594 uint8_t ras_rom_i2c_slave_addr; 595 uint16_t bootup_mvddq_mv; 596 uint16_t bootup_mvpp_mv; 597 uint32_t zfbstartaddrin16mb; 598 uint32_t pplib_pptable_id; // if pplib_pptable_id!=0, pplib get powerplay table inside driver instead of from VBIOS 599 uint32_t mvdd_ratio; // mvdd_raio = (real mvdd in power rail)*1000/(mvdd_output_from_svi2) 600 uint16_t hw_bootup_vddgfx_mv; // hw default vddgfx voltage level decide by board strap 601 uint16_t hw_bootup_vddc_mv; // hw default vddc voltage level decide by board strap 602 uint16_t hw_bootup_mvddc_mv; // hw default mvddc voltage level decide by board strap 603 uint16_t hw_bootup_vddci_mv; // hw default vddci voltage level decide by board strap 604 uint32_t maco_pwrlimit_mw; // bomaco mode power limit in unit of m-watt 605 uint32_t usb_pwrlimit_mw; // power limit when USB is enable in unit of m-watt 606 uint32_t fw_reserved_size_in_kb; // VBIOS reserved extra fw size in unit of kb. 607 uint32_t pspbl_init_done_reg_addr; 608 uint32_t pspbl_init_done_value; 609 uint32_t pspbl_init_done_check_timeout; // time out in unit of us when polling pspbl init done 610 uint32_t reserved[2]; 611 }; 612 613 /* 614 *************************************************************************** 615 Data Table lcd_info structure 616 *************************************************************************** 617 */ 618 619 struct lcd_info_v2_1 620 { 621 struct atom_common_table_header table_header; 622 struct atom_dtd_format lcd_timing; 623 uint16_t backlight_pwm; 624 uint16_t special_handle_cap; 625 uint16_t panel_misc; 626 uint16_t lvds_max_slink_pclk; 627 uint16_t lvds_ss_percentage; 628 uint16_t lvds_ss_rate_10hz; 629 uint8_t pwr_on_digon_to_de; /*all pwr sequence numbers below are in uint of 4ms*/ 630 uint8_t pwr_on_de_to_vary_bl; 631 uint8_t pwr_down_vary_bloff_to_de; 632 uint8_t pwr_down_de_to_digoff; 633 uint8_t pwr_off_delay; 634 uint8_t pwr_on_vary_bl_to_blon; 635 uint8_t pwr_down_bloff_to_vary_bloff; 636 uint8_t panel_bpc; 637 uint8_t dpcd_edp_config_cap; 638 uint8_t dpcd_max_link_rate; 639 uint8_t dpcd_max_lane_count; 640 uint8_t dpcd_max_downspread; 641 uint8_t min_allowed_bl_level; 642 uint8_t max_allowed_bl_level; 643 uint8_t bootup_bl_level; 644 uint8_t dplvdsrxid; 645 uint32_t reserved1[8]; 646 }; 647 648 /* lcd_info_v2_1.panel_misc defintion */ 649 enum atom_lcd_info_panel_misc{ 650 ATOM_PANEL_MISC_FPDI =0x0002, 651 }; 652 653 //uceDPToLVDSRxId 654 enum atom_lcd_info_dptolvds_rx_id 655 { 656 eDP_TO_LVDS_RX_DISABLE = 0x00, // no eDP->LVDS translator chip 657 eDP_TO_LVDS_COMMON_ID = 0x01, // common eDP->LVDS translator chip without AMD SW init 658 eDP_TO_LVDS_REALTEK_ID = 0x02, // Realtek tansaltor which require AMD SW init 659 }; 660 661 662 /* 663 *************************************************************************** 664 Data Table gpio_pin_lut structure 665 *************************************************************************** 666 */ 667 668 struct atom_gpio_pin_assignment 669 { 670 uint32_t data_a_reg_index; 671 uint8_t gpio_bitshift; 672 uint8_t gpio_mask_bitshift; 673 uint8_t gpio_id; 674 uint8_t reserved; 675 }; 676 677 /* atom_gpio_pin_assignment.gpio_id definition */ 678 enum atom_gpio_pin_assignment_gpio_id { 679 I2C_HW_LANE_MUX =0x0f, /* only valid when bit7=1 */ 680 I2C_HW_ENGINE_ID_MASK =0x70, /* only valid when bit7=1 */ 681 I2C_HW_CAP =0x80, /*only when the I2C_HW_CAP is set, the pin ID is assigned to an I2C pin pair, otherwise, it's an generic GPIO pin */ 682 683 /* gpio_id pre-define id for multiple usage */ 684 /* GPIO use to control PCIE_VDDC in certain SLT board */ 685 PCIE_VDDC_CONTROL_GPIO_PINID = 56, 686 /* if PP_AC_DC_SWITCH_GPIO_PINID in Gpio_Pin_LutTable, AC/DC swithing feature is enable */ 687 PP_AC_DC_SWITCH_GPIO_PINID = 60, 688 /* VDDC_REGULATOR_VRHOT_GPIO_PINID in Gpio_Pin_LutTable, VRHot feature is enable */ 689 VDDC_VRHOT_GPIO_PINID = 61, 690 /*if VDDC_PCC_GPIO_PINID in GPIO_LUTable, Peak Current Control feature is enabled */ 691 VDDC_PCC_GPIO_PINID = 62, 692 /* Only used on certain SLT/PA board to allow utility to cut Efuse. */ 693 EFUSE_CUT_ENABLE_GPIO_PINID = 63, 694 /* ucGPIO=DRAM_SELF_REFRESH_GPIO_PIND uses for memory self refresh (ucGPIO=0, DRAM self-refresh; ucGPIO= */ 695 DRAM_SELF_REFRESH_GPIO_PINID = 64, 696 /* Thermal interrupt output->system thermal chip GPIO pin */ 697 THERMAL_INT_OUTPUT_GPIO_PINID =65, 698 }; 699 700 701 struct atom_gpio_pin_lut_v2_1 702 { 703 struct atom_common_table_header table_header; 704 /*the real number of this included in the structure is calcualted by using the (whole structure size - the header size)/size of atom_gpio_pin_lut */ 705 struct atom_gpio_pin_assignment gpio_pin[8]; 706 }; 707 708 709 /* 710 * VBIOS/PRE-OS always reserve a FB region at the top of frame buffer. driver should not write 711 * access that region. driver can allocate their own reservation region as long as it does not 712 * overlap firwmare's reservation region. 713 * if (pre-NV1X) atom data table firmwareInfoTable version < 3.3: 714 * in this case, atom data table vram_usagebyfirmwareTable version always <= 2.1 715 * if VBIOS/UEFI GOP is posted: 716 * VBIOS/UEFIGOP update used_by_firmware_in_kb = total reserved size by VBIOS 717 * update start_address_in_kb = total_mem_size_in_kb - used_by_firmware_in_kb; 718 * ( total_mem_size_in_kb = reg(CONFIG_MEMSIZE)<<10) 719 * driver can allocate driver reservation region under firmware reservation, 720 * used_by_driver_in_kb = driver reservation size 721 * driver reservation start address = (start_address_in_kb - used_by_driver_in_kb) 722 * Comment1[hchan]: There is only one reservation at the beginning of the FB reserved by 723 * host driver. Host driver would overwrite the table with the following 724 * used_by_firmware_in_kb = total reserved size for pf-vf info exchange and 725 * set SRIOV_MSG_SHARE_RESERVATION mask start_address_in_kb = 0 726 * else there is no VBIOS reservation region: 727 * driver must allocate driver reservation region at top of FB. 728 * driver set used_by_driver_in_kb = driver reservation size 729 * driver reservation start address = (total_mem_size_in_kb - used_by_driver_in_kb) 730 * same as Comment1 731 * else (NV1X and after): 732 * if VBIOS/UEFI GOP is posted: 733 * VBIOS/UEFIGOP update: 734 * used_by_firmware_in_kb = atom_firmware_Info_v3_3.fw_reserved_size_in_kb; 735 * start_address_in_kb = total_mem_size_in_kb - used_by_firmware_in_kb; 736 * (total_mem_size_in_kb = reg(CONFIG_MEMSIZE)<<10) 737 * if vram_usagebyfirmwareTable version <= 2.1: 738 * driver can allocate driver reservation region under firmware reservation, 739 * driver set used_by_driver_in_kb = driver reservation size 740 * driver reservation start address = start_address_in_kb - used_by_driver_in_kb 741 * same as Comment1 742 * else driver can: 743 * allocate it reservation any place as long as it does overlap pre-OS FW reservation area 744 * set used_by_driver_region0_in_kb = driver reservation size 745 * set driver_region0_start_address_in_kb = driver reservation region start address 746 * Comment2[hchan]: Host driver can set used_by_firmware_in_kb and start_address_in_kb to 747 * zero as the reservation for VF as it doesn’t exist. And Host driver should also 748 * update atom_firmware_Info table to remove the same VBIOS reservation as well. 749 */ 750 751 struct vram_usagebyfirmware_v2_1 752 { 753 struct atom_common_table_header table_header; 754 uint32_t start_address_in_kb; 755 uint16_t used_by_firmware_in_kb; 756 uint16_t used_by_driver_in_kb; 757 }; 758 759 struct vram_usagebyfirmware_v2_2 { 760 struct atom_common_table_header table_header; 761 uint32_t fw_region_start_address_in_kb; 762 uint16_t used_by_firmware_in_kb; 763 uint16_t reserved; 764 uint32_t driver_region0_start_address_in_kb; 765 uint32_t used_by_driver_region0_in_kb; 766 uint32_t reserved32[7]; 767 }; 768 769 /* 770 *************************************************************************** 771 Data Table displayobjectinfo structure 772 *************************************************************************** 773 */ 774 775 enum atom_object_record_type_id { 776 ATOM_I2C_RECORD_TYPE = 1, 777 ATOM_HPD_INT_RECORD_TYPE = 2, 778 ATOM_CONNECTOR_CAP_RECORD_TYPE = 3, 779 ATOM_CONNECTOR_SPEED_UPTO = 4, 780 ATOM_OBJECT_GPIO_CNTL_RECORD_TYPE = 9, 781 ATOM_CONNECTOR_HPDPIN_LUT_RECORD_TYPE = 16, 782 ATOM_CONNECTOR_AUXDDC_LUT_RECORD_TYPE = 17, 783 ATOM_ENCODER_CAP_RECORD_TYPE = 20, 784 ATOM_BRACKET_LAYOUT_RECORD_TYPE = 21, 785 ATOM_CONNECTOR_FORCED_TMDS_CAP_RECORD_TYPE = 22, 786 ATOM_DISP_CONNECTOR_CAPS_RECORD_TYPE = 23, 787 ATOM_BRACKET_LAYOUT_V2_RECORD_TYPE = 25, 788 ATOM_RECORD_END_TYPE = 0xFF, 789 }; 790 791 struct atom_common_record_header 792 { 793 uint8_t record_type; //An emun to indicate the record type 794 uint8_t record_size; //The size of the whole record in byte 795 }; 796 797 struct atom_i2c_record 798 { 799 struct atom_common_record_header record_header; //record_type = ATOM_I2C_RECORD_TYPE 800 uint8_t i2c_id; 801 uint8_t i2c_slave_addr; //The slave address, it's 0 when the record is attached to connector for DDC 802 }; 803 804 struct atom_hpd_int_record 805 { 806 struct atom_common_record_header record_header; //record_type = ATOM_HPD_INT_RECORD_TYPE 807 uint8_t pin_id; //Corresponding block in GPIO_PIN_INFO table gives the pin info 808 uint8_t plugin_pin_state; 809 }; 810 811 struct atom_connector_caps_record { 812 struct atom_common_record_header 813 record_header; //record_type = ATOM_CONN_CAP_RECORD_TYPE 814 uint16_t connector_caps; //01b if internal display is checked; 10b if internal BL is checked; 0 of Not 815 }; 816 817 struct atom_connector_speed_record { 818 struct atom_common_record_header 819 record_header; //record_type = ATOM_CONN_SPEED_UPTO 820 uint32_t connector_max_speed; // connector Max speed attribute, it sets 8100 in Mhz when DP connector @8.1Ghz. 821 uint16_t reserved; 822 }; 823 824 // Bit maps for ATOM_ENCODER_CAP_RECORD.usEncoderCap 825 enum atom_encoder_caps_def 826 { 827 ATOM_ENCODER_CAP_RECORD_HBR2 =0x01, // DP1.2 HBR2 is supported by HW encoder, it is retired in NI. the real meaning from SI is MST_EN 828 ATOM_ENCODER_CAP_RECORD_MST_EN =0x01, // from SI, this bit means DP MST is enable or not. 829 ATOM_ENCODER_CAP_RECORD_HBR2_EN =0x02, // DP1.2 HBR2 setting is qualified and HBR2 can be enabled 830 ATOM_ENCODER_CAP_RECORD_HDMI6Gbps_EN =0x04, // HDMI2.0 6Gbps enable or not. 831 ATOM_ENCODER_CAP_RECORD_HBR3_EN =0x08, // DP1.3 HBR3 is supported by board. 832 ATOM_ENCODER_CAP_RECORD_DP2 =0x10, // DP2 is supported by ASIC/board. 833 ATOM_ENCODER_CAP_RECORD_UHBR10_EN =0x20, // DP2.0 UHBR10 settings is supported by board 834 ATOM_ENCODER_CAP_RECORD_UHBR13_5_EN =0x40, // DP2.0 UHBR13.5 settings is supported by board 835 ATOM_ENCODER_CAP_RECORD_UHBR20_EN =0x80, // DP2.0 UHBR20 settings is supported by board 836 ATOM_ENCODER_CAP_RECORD_USB_C_TYPE =0x100, // the DP connector is a USB-C type. 837 }; 838 839 struct atom_encoder_caps_record 840 { 841 struct atom_common_record_header record_header; //record_type = ATOM_ENCODER_CAP_RECORD_TYPE 842 uint32_t encodercaps; 843 }; 844 845 enum atom_connector_caps_def 846 { 847 ATOM_CONNECTOR_CAP_INTERNAL_DISPLAY = 0x01, //a cap bit to indicate that this non-embedded display connector is an internal display 848 ATOM_CONNECTOR_CAP_INTERNAL_DISPLAY_BL = 0x02, //a cap bit to indicate that this internal display requires BL control from GPU, refers to lcd_info for BL PWM freq 849 }; 850 851 struct atom_disp_connector_caps_record 852 { 853 struct atom_common_record_header record_header; 854 uint32_t connectcaps; 855 }; 856 857 //The following generic object gpio pin control record type will replace JTAG_RECORD/FPGA_CONTROL_RECORD/DVI_EXT_INPUT_RECORD above gradually 858 struct atom_gpio_pin_control_pair 859 { 860 uint8_t gpio_id; // GPIO_ID, find the corresponding ID in GPIO_LUT table 861 uint8_t gpio_pinstate; // Pin state showing how to set-up the pin 862 }; 863 864 struct atom_object_gpio_cntl_record 865 { 866 struct atom_common_record_header record_header; 867 uint8_t flag; // Future expnadibility 868 uint8_t number_of_pins; // Number of GPIO pins used to control the object 869 struct atom_gpio_pin_control_pair gpio[1]; // the real gpio pin pair determined by number of pins ucNumberOfPins 870 }; 871 872 //Definitions for GPIO pin state 873 enum atom_gpio_pin_control_pinstate_def 874 { 875 GPIO_PIN_TYPE_INPUT = 0x00, 876 GPIO_PIN_TYPE_OUTPUT = 0x10, 877 GPIO_PIN_TYPE_HW_CONTROL = 0x20, 878 879 //For GPIO_PIN_TYPE_OUTPUT the following is defined 880 GPIO_PIN_OUTPUT_STATE_MASK = 0x01, 881 GPIO_PIN_OUTPUT_STATE_SHIFT = 0, 882 GPIO_PIN_STATE_ACTIVE_LOW = 0x0, 883 GPIO_PIN_STATE_ACTIVE_HIGH = 0x1, 884 }; 885 886 // Indexes to GPIO array in GLSync record 887 // GLSync record is for Frame Lock/Gen Lock feature. 888 enum atom_glsync_record_gpio_index_def 889 { 890 ATOM_GPIO_INDEX_GLSYNC_REFCLK = 0, 891 ATOM_GPIO_INDEX_GLSYNC_HSYNC = 1, 892 ATOM_GPIO_INDEX_GLSYNC_VSYNC = 2, 893 ATOM_GPIO_INDEX_GLSYNC_SWAP_REQ = 3, 894 ATOM_GPIO_INDEX_GLSYNC_SWAP_GNT = 4, 895 ATOM_GPIO_INDEX_GLSYNC_INTERRUPT = 5, 896 ATOM_GPIO_INDEX_GLSYNC_V_RESET = 6, 897 ATOM_GPIO_INDEX_GLSYNC_SWAP_CNTL = 7, 898 ATOM_GPIO_INDEX_GLSYNC_SWAP_SEL = 8, 899 ATOM_GPIO_INDEX_GLSYNC_MAX = 9, 900 }; 901 902 903 struct atom_connector_hpdpin_lut_record //record for ATOM_CONNECTOR_HPDPIN_LUT_RECORD_TYPE 904 { 905 struct atom_common_record_header record_header; 906 uint8_t hpd_pin_map[8]; 907 }; 908 909 struct atom_connector_auxddc_lut_record //record for ATOM_CONNECTOR_AUXDDC_LUT_RECORD_TYPE 910 { 911 struct atom_common_record_header record_header; 912 uint8_t aux_ddc_map[8]; 913 }; 914 915 struct atom_connector_forced_tmds_cap_record 916 { 917 struct atom_common_record_header record_header; 918 // override TMDS capability on this connector when it operate in TMDS mode. usMaxTmdsClkRate = max TMDS Clock in Mhz/2.5 919 uint8_t maxtmdsclkrate_in2_5mhz; 920 uint8_t reserved; 921 }; 922 923 struct atom_connector_layout_info 924 { 925 uint16_t connectorobjid; 926 uint8_t connector_type; 927 uint8_t position; 928 }; 929 930 // define ATOM_CONNECTOR_LAYOUT_INFO.ucConnectorType to describe the display connector size 931 enum atom_connector_layout_info_connector_type_def 932 { 933 CONNECTOR_TYPE_DVI_D = 1, 934 935 CONNECTOR_TYPE_HDMI = 4, 936 CONNECTOR_TYPE_DISPLAY_PORT = 5, 937 CONNECTOR_TYPE_MINI_DISPLAY_PORT = 6, 938 }; 939 940 struct atom_bracket_layout_record 941 { 942 struct atom_common_record_header record_header; 943 uint8_t bracketlen; 944 uint8_t bracketwidth; 945 uint8_t conn_num; 946 uint8_t reserved; 947 struct atom_connector_layout_info conn_info[1]; 948 }; 949 struct atom_bracket_layout_record_v2 { 950 struct atom_common_record_header 951 record_header; //record_type = ATOM_BRACKET_LAYOUT_RECORD_TYPE 952 uint8_t bracketlen; //Bracket Length in mm 953 uint8_t bracketwidth; //Bracket Width in mm 954 uint8_t conn_num; //Connector numbering 955 uint8_t mini_type; //Mini Type (0 = Normal; 1 = Mini) 956 uint8_t reserved1; 957 uint8_t reserved2; 958 }; 959 960 enum atom_connector_layout_info_mini_type_def { 961 MINI_TYPE_NORMAL = 0, 962 MINI_TYPE_MINI = 1, 963 }; 964 965 enum atom_display_device_tag_def{ 966 ATOM_DISPLAY_LCD1_SUPPORT = 0x0002, //an embedded display is either an LVDS or eDP signal type of display 967 ATOM_DISPLAY_LCD2_SUPPORT = 0x0020, //second edp device tag 0x0020 for backward compability 968 ATOM_DISPLAY_DFP1_SUPPORT = 0x0008, 969 ATOM_DISPLAY_DFP2_SUPPORT = 0x0080, 970 ATOM_DISPLAY_DFP3_SUPPORT = 0x0200, 971 ATOM_DISPLAY_DFP4_SUPPORT = 0x0400, 972 ATOM_DISPLAY_DFP5_SUPPORT = 0x0800, 973 ATOM_DISPLAY_DFP6_SUPPORT = 0x0040, 974 ATOM_DISPLAY_DFPx_SUPPORT = 0x0ec8, 975 }; 976 977 struct atom_display_object_path_v2 978 { 979 uint16_t display_objid; //Connector Object ID or Misc Object ID 980 uint16_t disp_recordoffset; 981 uint16_t encoderobjid; //first encoder closer to the connector, could be either an external or intenal encoder 982 uint16_t extencoderobjid; //2nd encoder after the first encoder, from the connector point of view; 983 uint16_t encoder_recordoffset; 984 uint16_t extencoder_recordoffset; 985 uint16_t device_tag; //a supported device vector, each display path starts with this.the paths are enumerated in the way of priority, a path appears first 986 uint8_t priority_id; 987 uint8_t reserved; 988 }; 989 990 struct atom_display_object_path_v3 { 991 uint16_t display_objid; //Connector Object ID or Misc Object ID 992 uint16_t disp_recordoffset; 993 uint16_t encoderobjid; //first encoder closer to the connector, could be either an external or intenal encoder 994 uint16_t reserved1; //only on USBC case, otherwise always = 0 995 uint16_t reserved2; //reserved and always = 0 996 uint16_t reserved3; //reserved and always = 0 997 //a supported device vector, each display path starts with this.the paths are enumerated in the way of priority, 998 //a path appears first 999 uint16_t device_tag; 1000 uint16_t reserved4; //reserved and always = 0 1001 }; 1002 1003 struct display_object_info_table_v1_4 1004 { 1005 struct atom_common_table_header table_header; 1006 uint16_t supporteddevices; 1007 uint8_t number_of_path; 1008 uint8_t reserved; 1009 struct atom_display_object_path_v2 display_path[8]; //the real number of this included in the structure is calculated by using the (whole structure size - the header size- number_of_path)/size of atom_display_object_path 1010 }; 1011 1012 struct display_object_info_table_v1_5 { 1013 struct atom_common_table_header table_header; 1014 uint16_t supporteddevices; 1015 uint8_t number_of_path; 1016 uint8_t reserved; 1017 // the real number of this included in the structure is calculated by using the 1018 // (whole structure size - the header size- number_of_path)/size of atom_display_object_path 1019 struct atom_display_object_path_v3 display_path[8]; 1020 }; 1021 1022 /* 1023 *************************************************************************** 1024 Data Table dce_info structure 1025 *************************************************************************** 1026 */ 1027 struct atom_display_controller_info_v4_1 1028 { 1029 struct atom_common_table_header table_header; 1030 uint32_t display_caps; 1031 uint32_t bootup_dispclk_10khz; 1032 uint16_t dce_refclk_10khz; 1033 uint16_t i2c_engine_refclk_10khz; 1034 uint16_t dvi_ss_percentage; // in unit of 0.001% 1035 uint16_t dvi_ss_rate_10hz; 1036 uint16_t hdmi_ss_percentage; // in unit of 0.001% 1037 uint16_t hdmi_ss_rate_10hz; 1038 uint16_t dp_ss_percentage; // in unit of 0.001% 1039 uint16_t dp_ss_rate_10hz; 1040 uint8_t dvi_ss_mode; // enum of atom_spread_spectrum_mode 1041 uint8_t hdmi_ss_mode; // enum of atom_spread_spectrum_mode 1042 uint8_t dp_ss_mode; // enum of atom_spread_spectrum_mode 1043 uint8_t ss_reserved; 1044 uint8_t hardcode_mode_num; // a hardcode mode number defined in StandardVESA_TimingTable when a CRT or DFP EDID is not available 1045 uint8_t reserved1[3]; 1046 uint16_t dpphy_refclk_10khz; 1047 uint16_t reserved2; 1048 uint8_t dceip_min_ver; 1049 uint8_t dceip_max_ver; 1050 uint8_t max_disp_pipe_num; 1051 uint8_t max_vbios_active_disp_pipe_num; 1052 uint8_t max_ppll_num; 1053 uint8_t max_disp_phy_num; 1054 uint8_t max_aux_pairs; 1055 uint8_t remotedisplayconfig; 1056 uint8_t reserved3[8]; 1057 }; 1058 1059 struct atom_display_controller_info_v4_2 1060 { 1061 struct atom_common_table_header table_header; 1062 uint32_t display_caps; 1063 uint32_t bootup_dispclk_10khz; 1064 uint16_t dce_refclk_10khz; 1065 uint16_t i2c_engine_refclk_10khz; 1066 uint16_t dvi_ss_percentage; // in unit of 0.001% 1067 uint16_t dvi_ss_rate_10hz; 1068 uint16_t hdmi_ss_percentage; // in unit of 0.001% 1069 uint16_t hdmi_ss_rate_10hz; 1070 uint16_t dp_ss_percentage; // in unit of 0.001% 1071 uint16_t dp_ss_rate_10hz; 1072 uint8_t dvi_ss_mode; // enum of atom_spread_spectrum_mode 1073 uint8_t hdmi_ss_mode; // enum of atom_spread_spectrum_mode 1074 uint8_t dp_ss_mode; // enum of atom_spread_spectrum_mode 1075 uint8_t ss_reserved; 1076 uint8_t dfp_hardcode_mode_num; // DFP hardcode mode number defined in StandardVESA_TimingTable when EDID is not available 1077 uint8_t dfp_hardcode_refreshrate;// DFP hardcode mode refreshrate defined in StandardVESA_TimingTable when EDID is not available 1078 uint8_t vga_hardcode_mode_num; // VGA hardcode mode number defined in StandardVESA_TimingTable when EDID is not avablable 1079 uint8_t vga_hardcode_refreshrate;// VGA hardcode mode number defined in StandardVESA_TimingTable when EDID is not avablable 1080 uint16_t dpphy_refclk_10khz; 1081 uint16_t reserved2; 1082 uint8_t dcnip_min_ver; 1083 uint8_t dcnip_max_ver; 1084 uint8_t max_disp_pipe_num; 1085 uint8_t max_vbios_active_disp_pipe_num; 1086 uint8_t max_ppll_num; 1087 uint8_t max_disp_phy_num; 1088 uint8_t max_aux_pairs; 1089 uint8_t remotedisplayconfig; 1090 uint8_t reserved3[8]; 1091 }; 1092 1093 struct atom_display_controller_info_v4_3 1094 { 1095 struct atom_common_table_header table_header; 1096 uint32_t display_caps; 1097 uint32_t bootup_dispclk_10khz; 1098 uint16_t dce_refclk_10khz; 1099 uint16_t i2c_engine_refclk_10khz; 1100 uint16_t dvi_ss_percentage; // in unit of 0.001% 1101 uint16_t dvi_ss_rate_10hz; 1102 uint16_t hdmi_ss_percentage; // in unit of 0.001% 1103 uint16_t hdmi_ss_rate_10hz; 1104 uint16_t dp_ss_percentage; // in unit of 0.001% 1105 uint16_t dp_ss_rate_10hz; 1106 uint8_t dvi_ss_mode; // enum of atom_spread_spectrum_mode 1107 uint8_t hdmi_ss_mode; // enum of atom_spread_spectrum_mode 1108 uint8_t dp_ss_mode; // enum of atom_spread_spectrum_mode 1109 uint8_t ss_reserved; 1110 uint8_t dfp_hardcode_mode_num; // DFP hardcode mode number defined in StandardVESA_TimingTable when EDID is not available 1111 uint8_t dfp_hardcode_refreshrate;// DFP hardcode mode refreshrate defined in StandardVESA_TimingTable when EDID is not available 1112 uint8_t vga_hardcode_mode_num; // VGA hardcode mode number defined in StandardVESA_TimingTable when EDID is not avablable 1113 uint8_t vga_hardcode_refreshrate;// VGA hardcode mode number defined in StandardVESA_TimingTable when EDID is not avablable 1114 uint16_t dpphy_refclk_10khz; 1115 uint16_t reserved2; 1116 uint8_t dcnip_min_ver; 1117 uint8_t dcnip_max_ver; 1118 uint8_t max_disp_pipe_num; 1119 uint8_t max_vbios_active_disp_pipe_num; 1120 uint8_t max_ppll_num; 1121 uint8_t max_disp_phy_num; 1122 uint8_t max_aux_pairs; 1123 uint8_t remotedisplayconfig; 1124 uint8_t reserved3[8]; 1125 }; 1126 1127 struct atom_display_controller_info_v4_4 { 1128 struct atom_common_table_header table_header; 1129 uint32_t display_caps; 1130 uint32_t bootup_dispclk_10khz; 1131 uint16_t dce_refclk_10khz; 1132 uint16_t i2c_engine_refclk_10khz; 1133 uint16_t dvi_ss_percentage; // in unit of 0.001% 1134 uint16_t dvi_ss_rate_10hz; 1135 uint16_t hdmi_ss_percentage; // in unit of 0.001% 1136 uint16_t hdmi_ss_rate_10hz; 1137 uint16_t dp_ss_percentage; // in unit of 0.001% 1138 uint16_t dp_ss_rate_10hz; 1139 uint8_t dvi_ss_mode; // enum of atom_spread_spectrum_mode 1140 uint8_t hdmi_ss_mode; // enum of atom_spread_spectrum_mode 1141 uint8_t dp_ss_mode; // enum of atom_spread_spectrum_mode 1142 uint8_t ss_reserved; 1143 uint8_t dfp_hardcode_mode_num; // DFP hardcode mode number defined in StandardVESA_TimingTable when EDID is not available 1144 uint8_t dfp_hardcode_refreshrate;// DFP hardcode mode refreshrate defined in StandardVESA_TimingTable when EDID is not available 1145 uint8_t vga_hardcode_mode_num; // VGA hardcode mode number defined in StandardVESA_TimingTable when EDID is not avablable 1146 uint8_t vga_hardcode_refreshrate;// VGA hardcode mode number defined in StandardVESA_TimingTable when EDID is not avablable 1147 uint16_t dpphy_refclk_10khz; 1148 uint16_t hw_chip_id; 1149 uint8_t dcnip_min_ver; 1150 uint8_t dcnip_max_ver; 1151 uint8_t max_disp_pipe_num; 1152 uint8_t max_vbios_active_disp_pipum; 1153 uint8_t max_ppll_num; 1154 uint8_t max_disp_phy_num; 1155 uint8_t max_aux_pairs; 1156 uint8_t remotedisplayconfig; 1157 uint32_t dispclk_pll_vco_freq; 1158 uint32_t dp_ref_clk_freq; 1159 uint32_t max_mclk_chg_lat; // Worst case blackout duration for a memory clock frequency (p-state) change, units of 100s of ns (0.1 us) 1160 uint32_t max_sr_exit_lat; // Worst case memory self refresh exit time, units of 100ns of ns (0.1us) 1161 uint32_t max_sr_enter_exit_lat; // Worst case memory self refresh entry followed by immediate exit time, units of 100ns of ns (0.1us) 1162 uint16_t dc_golden_table_offset; // point of struct of atom_dc_golden_table_vxx 1163 uint16_t dc_golden_table_ver; 1164 uint32_t reserved3[3]; 1165 }; 1166 1167 struct atom_dc_golden_table_v1 1168 { 1169 uint32_t aux_dphy_rx_control0_val; 1170 uint32_t aux_dphy_tx_control_val; 1171 uint32_t aux_dphy_rx_control1_val; 1172 uint32_t dc_gpio_aux_ctrl_0_val; 1173 uint32_t dc_gpio_aux_ctrl_1_val; 1174 uint32_t dc_gpio_aux_ctrl_2_val; 1175 uint32_t dc_gpio_aux_ctrl_3_val; 1176 uint32_t dc_gpio_aux_ctrl_4_val; 1177 uint32_t dc_gpio_aux_ctrl_5_val; 1178 uint32_t reserved[23]; 1179 }; 1180 1181 enum dce_info_caps_def { 1182 // only for VBIOS 1183 DCE_INFO_CAPS_FORCE_DISPDEV_CONNECTED = 0x02, 1184 // only for VBIOS 1185 DCE_INFO_CAPS_DISABLE_DFP_DP_HBR2 = 0x04, 1186 // only for VBIOS 1187 DCE_INFO_CAPS_ENABLE_INTERLAC_TIMING = 0x08, 1188 // only for VBIOS 1189 DCE_INFO_CAPS_LTTPR_SUPPORT_ENABLE = 0x20, 1190 DCE_INFO_CAPS_VBIOS_LTTPR_TRANSPARENT_ENABLE = 0x40, 1191 }; 1192 1193 struct atom_display_controller_info_v4_5 1194 { 1195 struct atom_common_table_header table_header; 1196 uint32_t display_caps; 1197 uint32_t bootup_dispclk_10khz; 1198 uint16_t dce_refclk_10khz; 1199 uint16_t i2c_engine_refclk_10khz; 1200 uint16_t dvi_ss_percentage; // in unit of 0.001% 1201 uint16_t dvi_ss_rate_10hz; 1202 uint16_t hdmi_ss_percentage; // in unit of 0.001% 1203 uint16_t hdmi_ss_rate_10hz; 1204 uint16_t dp_ss_percentage; // in unit of 0.001% 1205 uint16_t dp_ss_rate_10hz; 1206 uint8_t dvi_ss_mode; // enum of atom_spread_spectrum_mode 1207 uint8_t hdmi_ss_mode; // enum of atom_spread_spectrum_mode 1208 uint8_t dp_ss_mode; // enum of atom_spread_spectrum_mode 1209 uint8_t ss_reserved; 1210 // DFP hardcode mode number defined in StandardVESA_TimingTable when EDID is not available 1211 uint8_t dfp_hardcode_mode_num; 1212 // DFP hardcode mode refreshrate defined in StandardVESA_TimingTable when EDID is not available 1213 uint8_t dfp_hardcode_refreshrate; 1214 // VGA hardcode mode number defined in StandardVESA_TimingTable when EDID is not avablable 1215 uint8_t vga_hardcode_mode_num; 1216 // VGA hardcode mode number defined in StandardVESA_TimingTable when EDID is not avablable 1217 uint8_t vga_hardcode_refreshrate; 1218 uint16_t dpphy_refclk_10khz; 1219 uint16_t hw_chip_id; 1220 uint8_t dcnip_min_ver; 1221 uint8_t dcnip_max_ver; 1222 uint8_t max_disp_pipe_num; 1223 uint8_t max_vbios_active_disp_pipe_num; 1224 uint8_t max_ppll_num; 1225 uint8_t max_disp_phy_num; 1226 uint8_t max_aux_pairs; 1227 uint8_t remotedisplayconfig; 1228 uint32_t dispclk_pll_vco_freq; 1229 uint32_t dp_ref_clk_freq; 1230 // Worst case blackout duration for a memory clock frequency (p-state) change, units of 100s of ns (0.1 us) 1231 uint32_t max_mclk_chg_lat; 1232 // Worst case memory self refresh exit time, units of 100ns of ns (0.1us) 1233 uint32_t max_sr_exit_lat; 1234 // Worst case memory self refresh entry followed by immediate exit time, units of 100ns of ns (0.1us) 1235 uint32_t max_sr_enter_exit_lat; 1236 uint16_t dc_golden_table_offset; // point of struct of atom_dc_golden_table_vxx 1237 uint16_t dc_golden_table_ver; 1238 uint32_t aux_dphy_rx_control0_val; 1239 uint32_t aux_dphy_tx_control_val; 1240 uint32_t aux_dphy_rx_control1_val; 1241 uint32_t dc_gpio_aux_ctrl_0_val; 1242 uint32_t dc_gpio_aux_ctrl_1_val; 1243 uint32_t dc_gpio_aux_ctrl_2_val; 1244 uint32_t dc_gpio_aux_ctrl_3_val; 1245 uint32_t dc_gpio_aux_ctrl_4_val; 1246 uint32_t dc_gpio_aux_ctrl_5_val; 1247 uint32_t reserved[26]; 1248 }; 1249 1250 /* 1251 *************************************************************************** 1252 Data Table ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO structure 1253 *************************************************************************** 1254 */ 1255 struct atom_ext_display_path 1256 { 1257 uint16_t device_tag; //A bit vector to show what devices are supported 1258 uint16_t device_acpi_enum; //16bit device ACPI id. 1259 uint16_t connectorobjid; //A physical connector for displays to plug in, using object connector definitions 1260 uint8_t auxddclut_index; //An index into external AUX/DDC channel LUT 1261 uint8_t hpdlut_index; //An index into external HPD pin LUT 1262 uint16_t ext_encoder_objid; //external encoder object id 1263 uint8_t channelmapping; // if ucChannelMapping=0, using default one to one mapping 1264 uint8_t chpninvert; // bit vector for up to 8 lanes, =0: P and N is not invert, =1 P and N is inverted 1265 uint16_t caps; 1266 uint16_t reserved; 1267 }; 1268 1269 //usCaps 1270 enum ext_display_path_cap_def { 1271 EXT_DISPLAY_PATH_CAPS__HBR2_DISABLE = 0x0001, 1272 EXT_DISPLAY_PATH_CAPS__DP_FIXED_VS_EN = 0x0002, 1273 EXT_DISPLAY_PATH_CAPS__EXT_CHIP_MASK = 0x007C, 1274 EXT_DISPLAY_PATH_CAPS__HDMI20_PI3EQX1204 = (0x01 << 2), //PI redriver chip 1275 EXT_DISPLAY_PATH_CAPS__HDMI20_TISN65DP159RSBT = (0x02 << 2), //TI retimer chip 1276 EXT_DISPLAY_PATH_CAPS__HDMI20_PARADE_PS175 = (0x03 << 2) //Parade DP->HDMI recoverter chip 1277 }; 1278 1279 struct atom_external_display_connection_info 1280 { 1281 struct atom_common_table_header table_header; 1282 uint8_t guid[16]; // a GUID is a 16 byte long string 1283 struct atom_ext_display_path path[7]; // total of fixed 7 entries. 1284 uint8_t checksum; // a simple Checksum of the sum of whole structure equal to 0x0. 1285 uint8_t stereopinid; // use for eDP panel 1286 uint8_t remotedisplayconfig; 1287 uint8_t edptolvdsrxid; 1288 uint8_t fixdpvoltageswing; // usCaps[1]=1, this indicate DP_LANE_SET value 1289 uint8_t reserved[3]; // for potential expansion 1290 }; 1291 1292 /* 1293 *************************************************************************** 1294 Data Table integratedsysteminfo structure 1295 *************************************************************************** 1296 */ 1297 1298 struct atom_camera_dphy_timing_param 1299 { 1300 uint8_t profile_id; // SENSOR_PROFILES 1301 uint32_t param; 1302 }; 1303 1304 struct atom_camera_dphy_elec_param 1305 { 1306 uint16_t param[3]; 1307 }; 1308 1309 struct atom_camera_module_info 1310 { 1311 uint8_t module_id; // 0: Rear, 1: Front right of user, 2: Front left of user 1312 uint8_t module_name[8]; 1313 struct atom_camera_dphy_timing_param timingparam[6]; // Exact number is under estimation and confirmation from sensor vendor 1314 }; 1315 1316 struct atom_camera_flashlight_info 1317 { 1318 uint8_t flashlight_id; // 0: Rear, 1: Front 1319 uint8_t name[8]; 1320 }; 1321 1322 struct atom_camera_data 1323 { 1324 uint32_t versionCode; 1325 struct atom_camera_module_info cameraInfo[3]; // Assuming 3 camera sensors max 1326 struct atom_camera_flashlight_info flashInfo; // Assuming 1 flashlight max 1327 struct atom_camera_dphy_elec_param dphy_param; 1328 uint32_t crc_val; // CRC 1329 }; 1330 1331 1332 struct atom_14nm_dpphy_dvihdmi_tuningset 1333 { 1334 uint32_t max_symclk_in10khz; 1335 uint8_t encoder_mode; //atom_encode_mode_def, =2: DVI, =3: HDMI mode 1336 uint8_t phy_sel; //bit vector of phy, bit0= phya, bit1=phyb, ....bit5 = phyf 1337 uint16_t margindeemph; //COMMON_MAR_DEEMPH_NOM[7:0]tx_margin_nom [15:8]deemph_gen1_nom 1338 uint8_t deemph_6db_4; //COMMON_SELDEEMPH60[31:24]deemph_6db_4 1339 uint8_t boostadj; //CMD_BUS_GLOBAL_FOR_TX_LANE0 [19:16]tx_boost_adj [20]tx_boost_en [23:22]tx_binary_ron_code_offset 1340 uint8_t tx_driver_fifty_ohms; //COMMON_ZCALCODE_CTRL[21].tx_driver_fifty_ohms 1341 uint8_t deemph_sel; //MARGIN_DEEMPH_LANE0.DEEMPH_SEL 1342 }; 1343 1344 struct atom_14nm_dpphy_dp_setting{ 1345 uint8_t dp_vs_pemph_level; //enum of atom_dp_vs_preemph_def 1346 uint16_t margindeemph; //COMMON_MAR_DEEMPH_NOM[7:0]tx_margin_nom [15:8]deemph_gen1_nom 1347 uint8_t deemph_6db_4; //COMMON_SELDEEMPH60[31:24]deemph_6db_4 1348 uint8_t boostadj; //CMD_BUS_GLOBAL_FOR_TX_LANE0 [19:16]tx_boost_adj [20]tx_boost_en [23:22]tx_binary_ron_code_offset 1349 }; 1350 1351 struct atom_14nm_dpphy_dp_tuningset{ 1352 uint8_t phy_sel; // bit vector of phy, bit0= phya, bit1=phyb, ....bit5 = phyf 1353 uint8_t version; 1354 uint16_t table_size; // size of atom_14nm_dpphy_dp_tuningset 1355 uint16_t reserved; 1356 struct atom_14nm_dpphy_dp_setting dptuning[10]; 1357 }; 1358 1359 struct atom_14nm_dig_transmitter_info_header_v4_0{ 1360 struct atom_common_table_header table_header; 1361 uint16_t pcie_phy_tmds_hdmi_macro_settings_offset; // offset of PCIEPhyTMDSHDMIMacroSettingsTbl 1362 uint16_t uniphy_vs_emph_lookup_table_offset; // offset of UniphyVSEmphLookUpTbl 1363 uint16_t uniphy_xbar_settings_table_offset; // offset of UniphyXbarSettingsTbl 1364 }; 1365 1366 struct atom_14nm_combphy_tmds_vs_set 1367 { 1368 uint8_t sym_clk; 1369 uint8_t dig_mode; 1370 uint8_t phy_sel; 1371 uint16_t common_mar_deemph_nom__margin_deemph_val; 1372 uint8_t common_seldeemph60__deemph_6db_4_val; 1373 uint8_t cmd_bus_global_for_tx_lane0__boostadj_val ; 1374 uint8_t common_zcalcode_ctrl__tx_driver_fifty_ohms_val; 1375 uint8_t margin_deemph_lane0__deemph_sel_val; 1376 }; 1377 1378 struct atom_DCN_dpphy_dvihdmi_tuningset 1379 { 1380 uint32_t max_symclk_in10khz; 1381 uint8_t encoder_mode; //atom_encode_mode_def, =2: DVI, =3: HDMI mode 1382 uint8_t phy_sel; //bit vector of phy, bit0= phya, bit1=phyb, ....bit5 = phyf 1383 uint8_t tx_eq_main; // map to RDPCSTX_PHY_FUSE0/1/2/3[5:0](EQ_MAIN) 1384 uint8_t tx_eq_pre; // map to RDPCSTX_PHY_FUSE0/1/2/3[11:6](EQ_PRE) 1385 uint8_t tx_eq_post; // map to RDPCSTX_PHY_FUSE0/1/2/3[17:12](EQ_POST) 1386 uint8_t reserved1; 1387 uint8_t tx_vboost_lvl; // tx_vboost_lvl, map to RDPCSTX_PHY_CNTL0.RDPCS_PHY_TX_VBOOST_LVL 1388 uint8_t reserved2; 1389 }; 1390 1391 struct atom_DCN_dpphy_dp_setting{ 1392 uint8_t dp_vs_pemph_level; //enum of atom_dp_vs_preemph_def 1393 uint8_t tx_eq_main; // map to RDPCSTX_PHY_FUSE0/1/2/3[5:0](EQ_MAIN) 1394 uint8_t tx_eq_pre; // map to RDPCSTX_PHY_FUSE0/1/2/3[11:6](EQ_PRE) 1395 uint8_t tx_eq_post; // map to RDPCSTX_PHY_FUSE0/1/2/3[17:12](EQ_POST) 1396 uint8_t tx_vboost_lvl; // tx_vboost_lvl, map to RDPCSTX_PHY_CNTL0.RDPCS_PHY_TX_VBOOST_LVL 1397 }; 1398 1399 struct atom_DCN_dpphy_dp_tuningset{ 1400 uint8_t phy_sel; // bit vector of phy, bit0= phya, bit1=phyb, ....bit5 = phyf 1401 uint8_t version; 1402 uint16_t table_size; // size of atom_14nm_dpphy_dp_setting 1403 uint16_t reserved; 1404 struct atom_DCN_dpphy_dp_setting dptunings[10]; 1405 }; 1406 1407 struct atom_i2c_reg_info { 1408 uint8_t ucI2cRegIndex; 1409 uint8_t ucI2cRegVal; 1410 }; 1411 1412 struct atom_hdmi_retimer_redriver_set { 1413 uint8_t HdmiSlvAddr; 1414 uint8_t HdmiRegNum; 1415 uint8_t Hdmi6GRegNum; 1416 struct atom_i2c_reg_info HdmiRegSetting[9]; //For non 6G Hz use 1417 struct atom_i2c_reg_info Hdmi6GhzRegSetting[3]; //For 6G Hz use. 1418 }; 1419 1420 struct atom_integrated_system_info_v1_11 1421 { 1422 struct atom_common_table_header table_header; 1423 uint32_t vbios_misc; //enum of atom_system_vbiosmisc_def 1424 uint32_t gpucapinfo; //enum of atom_system_gpucapinf_def 1425 uint32_t system_config; 1426 uint32_t cpucapinfo; 1427 uint16_t gpuclk_ss_percentage; //unit of 0.001%, 1000 mean 1% 1428 uint16_t gpuclk_ss_type; 1429 uint16_t lvds_ss_percentage; //unit of 0.001%, 1000 mean 1% 1430 uint16_t lvds_ss_rate_10hz; 1431 uint16_t hdmi_ss_percentage; //unit of 0.001%, 1000 mean 1% 1432 uint16_t hdmi_ss_rate_10hz; 1433 uint16_t dvi_ss_percentage; //unit of 0.001%, 1000 mean 1% 1434 uint16_t dvi_ss_rate_10hz; 1435 uint16_t dpphy_override; // bit vector, enum of atom_sysinfo_dpphy_override_def 1436 uint16_t lvds_misc; // enum of atom_sys_info_lvds_misc_def 1437 uint16_t backlight_pwm_hz; // pwm frequency in hz 1438 uint8_t memorytype; // enum of atom_dmi_t17_mem_type_def, APU memory type indication. 1439 uint8_t umachannelnumber; // number of memory channels 1440 uint8_t pwr_on_digon_to_de; /* all pwr sequence numbers below are in uint of 4ms */ 1441 uint8_t pwr_on_de_to_vary_bl; 1442 uint8_t pwr_down_vary_bloff_to_de; 1443 uint8_t pwr_down_de_to_digoff; 1444 uint8_t pwr_off_delay; 1445 uint8_t pwr_on_vary_bl_to_blon; 1446 uint8_t pwr_down_bloff_to_vary_bloff; 1447 uint8_t min_allowed_bl_level; 1448 uint8_t htc_hyst_limit; 1449 uint8_t htc_tmp_limit; 1450 uint8_t reserved1; 1451 uint8_t reserved2; 1452 struct atom_external_display_connection_info extdispconninfo; 1453 struct atom_14nm_dpphy_dvihdmi_tuningset dvi_tuningset; 1454 struct atom_14nm_dpphy_dvihdmi_tuningset hdmi_tuningset; 1455 struct atom_14nm_dpphy_dvihdmi_tuningset hdmi6g_tuningset; 1456 struct atom_14nm_dpphy_dp_tuningset dp_tuningset; // rbr 1.62G dp tuning set 1457 struct atom_14nm_dpphy_dp_tuningset dp_hbr3_tuningset; // HBR3 dp tuning set 1458 struct atom_camera_data camera_info; 1459 struct atom_hdmi_retimer_redriver_set dp0_retimer_set; //for DP0 1460 struct atom_hdmi_retimer_redriver_set dp1_retimer_set; //for DP1 1461 struct atom_hdmi_retimer_redriver_set dp2_retimer_set; //for DP2 1462 struct atom_hdmi_retimer_redriver_set dp3_retimer_set; //for DP3 1463 struct atom_14nm_dpphy_dp_tuningset dp_hbr_tuningset; //hbr 2.7G dp tuning set 1464 struct atom_14nm_dpphy_dp_tuningset dp_hbr2_tuningset; //hbr2 5.4G dp turnig set 1465 struct atom_14nm_dpphy_dp_tuningset edp_tuningset; //edp tuning set 1466 uint32_t reserved[66]; 1467 }; 1468 1469 struct atom_integrated_system_info_v1_12 1470 { 1471 struct atom_common_table_header table_header; 1472 uint32_t vbios_misc; //enum of atom_system_vbiosmisc_def 1473 uint32_t gpucapinfo; //enum of atom_system_gpucapinf_def 1474 uint32_t system_config; 1475 uint32_t cpucapinfo; 1476 uint16_t gpuclk_ss_percentage; //unit of 0.001%, 1000 mean 1% 1477 uint16_t gpuclk_ss_type; 1478 uint16_t lvds_ss_percentage; //unit of 0.001%, 1000 mean 1% 1479 uint16_t lvds_ss_rate_10hz; 1480 uint16_t hdmi_ss_percentage; //unit of 0.001%, 1000 mean 1% 1481 uint16_t hdmi_ss_rate_10hz; 1482 uint16_t dvi_ss_percentage; //unit of 0.001%, 1000 mean 1% 1483 uint16_t dvi_ss_rate_10hz; 1484 uint16_t dpphy_override; // bit vector, enum of atom_sysinfo_dpphy_override_def 1485 uint16_t lvds_misc; // enum of atom_sys_info_lvds_misc_def 1486 uint16_t backlight_pwm_hz; // pwm frequency in hz 1487 uint8_t memorytype; // enum of atom_dmi_t17_mem_type_def, APU memory type indication. 1488 uint8_t umachannelnumber; // number of memory channels 1489 uint8_t pwr_on_digon_to_de; // all pwr sequence numbers below are in uint of 4ms // 1490 uint8_t pwr_on_de_to_vary_bl; 1491 uint8_t pwr_down_vary_bloff_to_de; 1492 uint8_t pwr_down_de_to_digoff; 1493 uint8_t pwr_off_delay; 1494 uint8_t pwr_on_vary_bl_to_blon; 1495 uint8_t pwr_down_bloff_to_vary_bloff; 1496 uint8_t min_allowed_bl_level; 1497 uint8_t htc_hyst_limit; 1498 uint8_t htc_tmp_limit; 1499 uint8_t reserved1; 1500 uint8_t reserved2; 1501 struct atom_external_display_connection_info extdispconninfo; 1502 struct atom_DCN_dpphy_dvihdmi_tuningset TMDS_tuningset; 1503 struct atom_DCN_dpphy_dvihdmi_tuningset hdmiCLK5_tuningset; 1504 struct atom_DCN_dpphy_dvihdmi_tuningset hdmiCLK8_tuningset; 1505 struct atom_DCN_dpphy_dp_tuningset rbr_tuningset; // rbr 1.62G dp tuning set 1506 struct atom_DCN_dpphy_dp_tuningset hbr3_tuningset; // HBR3 dp tuning set 1507 struct atom_camera_data camera_info; 1508 struct atom_hdmi_retimer_redriver_set dp0_retimer_set; //for DP0 1509 struct atom_hdmi_retimer_redriver_set dp1_retimer_set; //for DP1 1510 struct atom_hdmi_retimer_redriver_set dp2_retimer_set; //for DP2 1511 struct atom_hdmi_retimer_redriver_set dp3_retimer_set; //for DP3 1512 struct atom_DCN_dpphy_dp_tuningset hbr_tuningset; //hbr 2.7G dp tuning set 1513 struct atom_DCN_dpphy_dp_tuningset hbr2_tuningset; //hbr2 5.4G dp turnig set 1514 struct atom_DCN_dpphy_dp_tuningset edp_tunings; //edp tuning set 1515 struct atom_DCN_dpphy_dvihdmi_tuningset hdmiCLK6_tuningset; 1516 uint32_t reserved[63]; 1517 }; 1518 1519 struct edp_info_table 1520 { 1521 uint16_t edp_backlight_pwm_hz; 1522 uint16_t edp_ss_percentage; 1523 uint16_t edp_ss_rate_10hz; 1524 uint16_t reserved1; 1525 uint32_t reserved2; 1526 uint8_t edp_pwr_on_off_delay; 1527 uint8_t edp_pwr_on_vary_bl_to_blon; 1528 uint8_t edp_pwr_down_bloff_to_vary_bloff; 1529 uint8_t edp_panel_bpc; 1530 uint8_t edp_bootup_bl_level; 1531 uint8_t reserved3[3]; 1532 uint32_t reserved4[3]; 1533 }; 1534 1535 struct atom_integrated_system_info_v2_1 1536 { 1537 struct atom_common_table_header table_header; 1538 uint32_t vbios_misc; //enum of atom_system_vbiosmisc_def 1539 uint32_t gpucapinfo; //enum of atom_system_gpucapinf_def 1540 uint32_t system_config; 1541 uint32_t cpucapinfo; 1542 uint16_t gpuclk_ss_percentage; //unit of 0.001%, 1000 mean 1% 1543 uint16_t gpuclk_ss_type; 1544 uint16_t dpphy_override; // bit vector, enum of atom_sysinfo_dpphy_override_def 1545 uint8_t memorytype; // enum of atom_dmi_t17_mem_type_def, APU memory type indication. 1546 uint8_t umachannelnumber; // number of memory channels 1547 uint8_t htc_hyst_limit; 1548 uint8_t htc_tmp_limit; 1549 uint8_t reserved1; 1550 uint8_t reserved2; 1551 struct edp_info_table edp1_info; 1552 struct edp_info_table edp2_info; 1553 uint32_t reserved3[8]; 1554 struct atom_external_display_connection_info extdispconninfo; 1555 struct atom_DCN_dpphy_dvihdmi_tuningset TMDS_tuningset; 1556 struct atom_DCN_dpphy_dvihdmi_tuningset hdmiCLK5_tuningset; //add clk6 1557 struct atom_DCN_dpphy_dvihdmi_tuningset hdmiCLK6_tuningset; 1558 struct atom_DCN_dpphy_dvihdmi_tuningset hdmiCLK8_tuningset; 1559 uint32_t reserved4[6];//reserve 2*sizeof(atom_DCN_dpphy_dvihdmi_tuningset) 1560 struct atom_DCN_dpphy_dp_tuningset rbr_tuningset; // rbr 1.62G dp tuning set 1561 struct atom_DCN_dpphy_dp_tuningset hbr_tuningset; //hbr 2.7G dp tuning set 1562 struct atom_DCN_dpphy_dp_tuningset hbr2_tuningset; //hbr2 5.4G dp turnig set 1563 struct atom_DCN_dpphy_dp_tuningset hbr3_tuningset; // HBR3 dp tuning set 1564 struct atom_DCN_dpphy_dp_tuningset edp_tunings; //edp tuning set 1565 uint32_t reserved5[28];//reserve 2*sizeof(atom_DCN_dpphy_dp_tuningset) 1566 struct atom_hdmi_retimer_redriver_set dp0_retimer_set; //for DP0 1567 struct atom_hdmi_retimer_redriver_set dp1_retimer_set; //for DP1 1568 struct atom_hdmi_retimer_redriver_set dp2_retimer_set; //for DP2 1569 struct atom_hdmi_retimer_redriver_set dp3_retimer_set; //for DP3 1570 uint32_t reserved6[30];// reserve size of(atom_camera_data) for camera_info 1571 uint32_t reserved7[32]; 1572 1573 }; 1574 1575 struct atom_n6_display_phy_tuning_set { 1576 uint8_t display_signal_type; 1577 uint8_t phy_sel; 1578 uint8_t preset_level; 1579 uint8_t reserved1; 1580 uint32_t reserved2; 1581 uint32_t speed_upto; 1582 uint8_t tx_vboost_level; 1583 uint8_t tx_vreg_v2i; 1584 uint8_t tx_vregdrv_byp; 1585 uint8_t tx_term_cntl; 1586 uint8_t tx_peak_level; 1587 uint8_t tx_slew_en; 1588 uint8_t tx_eq_pre; 1589 uint8_t tx_eq_main; 1590 uint8_t tx_eq_post; 1591 uint8_t tx_en_inv_pre; 1592 uint8_t tx_en_inv_post; 1593 uint8_t reserved3; 1594 uint32_t reserved4; 1595 uint32_t reserved5; 1596 uint32_t reserved6; 1597 }; 1598 1599 struct atom_display_phy_tuning_info { 1600 struct atom_common_table_header table_header; 1601 struct atom_n6_display_phy_tuning_set disp_phy_tuning[1]; 1602 }; 1603 1604 struct atom_integrated_system_info_v2_2 1605 { 1606 struct atom_common_table_header table_header; 1607 uint32_t vbios_misc; //enum of atom_system_vbiosmisc_def 1608 uint32_t gpucapinfo; //enum of atom_system_gpucapinf_def 1609 uint32_t system_config; 1610 uint32_t cpucapinfo; 1611 uint16_t gpuclk_ss_percentage; //unit of 0.001%, 1000 mean 1% 1612 uint16_t gpuclk_ss_type; 1613 uint16_t dpphy_override; // bit vector, enum of atom_sysinfo_dpphy_override_def 1614 uint8_t memorytype; // enum of atom_dmi_t17_mem_type_def, APU memory type indication. 1615 uint8_t umachannelnumber; // number of memory channels 1616 uint8_t htc_hyst_limit; 1617 uint8_t htc_tmp_limit; 1618 uint8_t reserved1; 1619 uint8_t reserved2; 1620 struct edp_info_table edp1_info; 1621 struct edp_info_table edp2_info; 1622 uint32_t reserved3[8]; 1623 struct atom_external_display_connection_info extdispconninfo; 1624 1625 uint32_t reserved4[189]; 1626 }; 1627 1628 // system_config 1629 enum atom_system_vbiosmisc_def{ 1630 INTEGRATED_SYSTEM_INFO__GET_EDID_CALLBACK_FUNC_SUPPORT = 0x01, 1631 }; 1632 1633 1634 // gpucapinfo 1635 enum atom_system_gpucapinf_def{ 1636 SYS_INFO_GPUCAPS__ENABEL_DFS_BYPASS = 0x10, 1637 }; 1638 1639 //dpphy_override 1640 enum atom_sysinfo_dpphy_override_def{ 1641 ATOM_ENABLE_DVI_TUNINGSET = 0x01, 1642 ATOM_ENABLE_HDMI_TUNINGSET = 0x02, 1643 ATOM_ENABLE_HDMI6G_TUNINGSET = 0x04, 1644 ATOM_ENABLE_DP_TUNINGSET = 0x08, 1645 ATOM_ENABLE_DP_HBR3_TUNINGSET = 0x10, 1646 }; 1647 1648 //lvds_misc 1649 enum atom_sys_info_lvds_misc_def 1650 { 1651 SYS_INFO_LVDS_MISC_888_FPDI_MODE =0x01, 1652 SYS_INFO_LVDS_MISC_888_BPC_MODE =0x04, 1653 SYS_INFO_LVDS_MISC_OVERRIDE_EN =0x08, 1654 }; 1655 1656 1657 //memorytype DMI Type 17 offset 12h - Memory Type 1658 enum atom_dmi_t17_mem_type_def{ 1659 OtherMemType = 0x01, ///< Assign 01 to Other 1660 UnknownMemType, ///< Assign 02 to Unknown 1661 DramMemType, ///< Assign 03 to DRAM 1662 EdramMemType, ///< Assign 04 to EDRAM 1663 VramMemType, ///< Assign 05 to VRAM 1664 SramMemType, ///< Assign 06 to SRAM 1665 RamMemType, ///< Assign 07 to RAM 1666 RomMemType, ///< Assign 08 to ROM 1667 FlashMemType, ///< Assign 09 to Flash 1668 EepromMemType, ///< Assign 10 to EEPROM 1669 FepromMemType, ///< Assign 11 to FEPROM 1670 EpromMemType, ///< Assign 12 to EPROM 1671 CdramMemType, ///< Assign 13 to CDRAM 1672 ThreeDramMemType, ///< Assign 14 to 3DRAM 1673 SdramMemType, ///< Assign 15 to SDRAM 1674 SgramMemType, ///< Assign 16 to SGRAM 1675 RdramMemType, ///< Assign 17 to RDRAM 1676 DdrMemType, ///< Assign 18 to DDR 1677 Ddr2MemType, ///< Assign 19 to DDR2 1678 Ddr2FbdimmMemType, ///< Assign 20 to DDR2 FB-DIMM 1679 Ddr3MemType = 0x18, ///< Assign 24 to DDR3 1680 Fbd2MemType, ///< Assign 25 to FBD2 1681 Ddr4MemType, ///< Assign 26 to DDR4 1682 LpDdrMemType, ///< Assign 27 to LPDDR 1683 LpDdr2MemType, ///< Assign 28 to LPDDR2 1684 LpDdr3MemType, ///< Assign 29 to LPDDR3 1685 LpDdr4MemType, ///< Assign 30 to LPDDR4 1686 GDdr6MemType, ///< Assign 31 to GDDR6 1687 HbmMemType, ///< Assign 32 to HBM 1688 Hbm2MemType, ///< Assign 33 to HBM2 1689 Ddr5MemType, ///< Assign 34 to DDR5 1690 LpDdr5MemType, ///< Assign 35 to LPDDR5 1691 }; 1692 1693 1694 // this Table is used starting from NL/AM, used by SBIOS and pass the IntegratedSystemInfoTable/PowerPlayInfoTable/SystemCameraInfoTable 1695 struct atom_fusion_system_info_v4 1696 { 1697 struct atom_integrated_system_info_v1_11 sysinfo; // refer to ATOM_INTEGRATED_SYSTEM_INFO_V1_8 definition 1698 uint32_t powerplayinfo[256]; // Reserve 1024 bytes space for PowerPlayInfoTable 1699 }; 1700 1701 1702 /* 1703 *************************************************************************** 1704 Data Table gfx_info structure 1705 *************************************************************************** 1706 */ 1707 1708 struct atom_gfx_info_v2_2 1709 { 1710 struct atom_common_table_header table_header; 1711 uint8_t gfxip_min_ver; 1712 uint8_t gfxip_max_ver; 1713 uint8_t max_shader_engines; 1714 uint8_t max_tile_pipes; 1715 uint8_t max_cu_per_sh; 1716 uint8_t max_sh_per_se; 1717 uint8_t max_backends_per_se; 1718 uint8_t max_texture_channel_caches; 1719 uint32_t regaddr_cp_dma_src_addr; 1720 uint32_t regaddr_cp_dma_src_addr_hi; 1721 uint32_t regaddr_cp_dma_dst_addr; 1722 uint32_t regaddr_cp_dma_dst_addr_hi; 1723 uint32_t regaddr_cp_dma_command; 1724 uint32_t regaddr_cp_status; 1725 uint32_t regaddr_rlc_gpu_clock_32; 1726 uint32_t rlc_gpu_timer_refclk; 1727 }; 1728 1729 struct atom_gfx_info_v2_3 { 1730 struct atom_common_table_header table_header; 1731 uint8_t gfxip_min_ver; 1732 uint8_t gfxip_max_ver; 1733 uint8_t max_shader_engines; 1734 uint8_t max_tile_pipes; 1735 uint8_t max_cu_per_sh; 1736 uint8_t max_sh_per_se; 1737 uint8_t max_backends_per_se; 1738 uint8_t max_texture_channel_caches; 1739 uint32_t regaddr_cp_dma_src_addr; 1740 uint32_t regaddr_cp_dma_src_addr_hi; 1741 uint32_t regaddr_cp_dma_dst_addr; 1742 uint32_t regaddr_cp_dma_dst_addr_hi; 1743 uint32_t regaddr_cp_dma_command; 1744 uint32_t regaddr_cp_status; 1745 uint32_t regaddr_rlc_gpu_clock_32; 1746 uint32_t rlc_gpu_timer_refclk; 1747 uint8_t active_cu_per_sh; 1748 uint8_t active_rb_per_se; 1749 uint16_t gcgoldenoffset; 1750 uint32_t rm21_sram_vmin_value; 1751 }; 1752 1753 struct atom_gfx_info_v2_4 1754 { 1755 struct atom_common_table_header table_header; 1756 uint8_t gfxip_min_ver; 1757 uint8_t gfxip_max_ver; 1758 uint8_t max_shader_engines; 1759 uint8_t reserved; 1760 uint8_t max_cu_per_sh; 1761 uint8_t max_sh_per_se; 1762 uint8_t max_backends_per_se; 1763 uint8_t max_texture_channel_caches; 1764 uint32_t regaddr_cp_dma_src_addr; 1765 uint32_t regaddr_cp_dma_src_addr_hi; 1766 uint32_t regaddr_cp_dma_dst_addr; 1767 uint32_t regaddr_cp_dma_dst_addr_hi; 1768 uint32_t regaddr_cp_dma_command; 1769 uint32_t regaddr_cp_status; 1770 uint32_t regaddr_rlc_gpu_clock_32; 1771 uint32_t rlc_gpu_timer_refclk; 1772 uint8_t active_cu_per_sh; 1773 uint8_t active_rb_per_se; 1774 uint16_t gcgoldenoffset; 1775 uint16_t gc_num_gprs; 1776 uint16_t gc_gsprim_buff_depth; 1777 uint16_t gc_parameter_cache_depth; 1778 uint16_t gc_wave_size; 1779 uint16_t gc_max_waves_per_simd; 1780 uint16_t gc_lds_size; 1781 uint8_t gc_num_max_gs_thds; 1782 uint8_t gc_gs_table_depth; 1783 uint8_t gc_double_offchip_lds_buffer; 1784 uint8_t gc_max_scratch_slots_per_cu; 1785 uint32_t sram_rm_fuses_val; 1786 uint32_t sram_custom_rm_fuses_val; 1787 }; 1788 1789 struct atom_gfx_info_v2_7 { 1790 struct atom_common_table_header table_header; 1791 uint8_t gfxip_min_ver; 1792 uint8_t gfxip_max_ver; 1793 uint8_t max_shader_engines; 1794 uint8_t reserved; 1795 uint8_t max_cu_per_sh; 1796 uint8_t max_sh_per_se; 1797 uint8_t max_backends_per_se; 1798 uint8_t max_texture_channel_caches; 1799 uint32_t regaddr_cp_dma_src_addr; 1800 uint32_t regaddr_cp_dma_src_addr_hi; 1801 uint32_t regaddr_cp_dma_dst_addr; 1802 uint32_t regaddr_cp_dma_dst_addr_hi; 1803 uint32_t regaddr_cp_dma_command; 1804 uint32_t regaddr_cp_status; 1805 uint32_t regaddr_rlc_gpu_clock_32; 1806 uint32_t rlc_gpu_timer_refclk; 1807 uint8_t active_cu_per_sh; 1808 uint8_t active_rb_per_se; 1809 uint16_t gcgoldenoffset; 1810 uint16_t gc_num_gprs; 1811 uint16_t gc_gsprim_buff_depth; 1812 uint16_t gc_parameter_cache_depth; 1813 uint16_t gc_wave_size; 1814 uint16_t gc_max_waves_per_simd; 1815 uint16_t gc_lds_size; 1816 uint8_t gc_num_max_gs_thds; 1817 uint8_t gc_gs_table_depth; 1818 uint8_t gc_double_offchip_lds_buffer; 1819 uint8_t gc_max_scratch_slots_per_cu; 1820 uint32_t sram_rm_fuses_val; 1821 uint32_t sram_custom_rm_fuses_val; 1822 uint8_t cut_cu; 1823 uint8_t active_cu_total; 1824 uint8_t cu_reserved[2]; 1825 uint32_t gc_config; 1826 uint8_t inactive_cu_per_se[8]; 1827 uint32_t reserved2[6]; 1828 }; 1829 1830 struct atom_gfx_info_v3_0 { 1831 struct atom_common_table_header table_header; 1832 uint8_t gfxip_min_ver; 1833 uint8_t gfxip_max_ver; 1834 uint8_t max_shader_engines; 1835 uint8_t max_tile_pipes; 1836 uint8_t max_cu_per_sh; 1837 uint8_t max_sh_per_se; 1838 uint8_t max_backends_per_se; 1839 uint8_t max_texture_channel_caches; 1840 uint32_t regaddr_lsdma_queue0_rb_rptr; 1841 uint32_t regaddr_lsdma_queue0_rb_rptr_hi; 1842 uint32_t regaddr_lsdma_queue0_rb_wptr; 1843 uint32_t regaddr_lsdma_queue0_rb_wptr_hi; 1844 uint32_t regaddr_lsdma_command; 1845 uint32_t regaddr_lsdma_status; 1846 uint32_t regaddr_golden_tsc_count_lower; 1847 uint32_t golden_tsc_count_lower_refclk; 1848 uint8_t active_wgp_per_se; 1849 uint8_t active_rb_per_se; 1850 uint8_t active_se; 1851 uint8_t reserved1; 1852 uint32_t sram_rm_fuses_val; 1853 uint32_t sram_custom_rm_fuses_val; 1854 uint32_t inactive_sa_mask; 1855 uint32_t gc_config; 1856 uint8_t inactive_wgp[16]; 1857 uint8_t inactive_rb[16]; 1858 uint32_t gdfll_as_wait_ctrl_val; 1859 uint32_t gdfll_as_step_ctrl_val; 1860 uint32_t reserved[8]; 1861 }; 1862 1863 /* 1864 *************************************************************************** 1865 Data Table smu_info structure 1866 *************************************************************************** 1867 */ 1868 struct atom_smu_info_v3_1 1869 { 1870 struct atom_common_table_header table_header; 1871 uint8_t smuip_min_ver; 1872 uint8_t smuip_max_ver; 1873 uint8_t smu_rsd1; 1874 uint8_t gpuclk_ss_mode; // enum of atom_spread_spectrum_mode 1875 uint16_t sclk_ss_percentage; 1876 uint16_t sclk_ss_rate_10hz; 1877 uint16_t gpuclk_ss_percentage; // in unit of 0.001% 1878 uint16_t gpuclk_ss_rate_10hz; 1879 uint32_t core_refclk_10khz; 1880 uint8_t ac_dc_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for AC/DC switching, =0xff means invalid 1881 uint8_t ac_dc_polarity; // GPIO polarity for AC/DC switching 1882 uint8_t vr0hot_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for VR0 HOT event, =0xff means invalid 1883 uint8_t vr0hot_polarity; // GPIO polarity for VR0 HOT event 1884 uint8_t vr1hot_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for VR1 HOT event , =0xff means invalid 1885 uint8_t vr1hot_polarity; // GPIO polarity for VR1 HOT event 1886 uint8_t fw_ctf_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for CTF, =0xff means invalid 1887 uint8_t fw_ctf_polarity; // GPIO polarity for CTF 1888 }; 1889 1890 struct atom_smu_info_v3_2 { 1891 struct atom_common_table_header table_header; 1892 uint8_t smuip_min_ver; 1893 uint8_t smuip_max_ver; 1894 uint8_t smu_rsd1; 1895 uint8_t gpuclk_ss_mode; 1896 uint16_t sclk_ss_percentage; 1897 uint16_t sclk_ss_rate_10hz; 1898 uint16_t gpuclk_ss_percentage; // in unit of 0.001% 1899 uint16_t gpuclk_ss_rate_10hz; 1900 uint32_t core_refclk_10khz; 1901 uint8_t ac_dc_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for AC/DC switching, =0xff means invalid 1902 uint8_t ac_dc_polarity; // GPIO polarity for AC/DC switching 1903 uint8_t vr0hot_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for VR0 HOT event, =0xff means invalid 1904 uint8_t vr0hot_polarity; // GPIO polarity for VR0 HOT event 1905 uint8_t vr1hot_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for VR1 HOT event , =0xff means invalid 1906 uint8_t vr1hot_polarity; // GPIO polarity for VR1 HOT event 1907 uint8_t fw_ctf_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for CTF, =0xff means invalid 1908 uint8_t fw_ctf_polarity; // GPIO polarity for CTF 1909 uint8_t pcc_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for PCC, =0xff means invalid 1910 uint8_t pcc_gpio_polarity; // GPIO polarity for CTF 1911 uint16_t smugoldenoffset; 1912 uint32_t gpupll_vco_freq_10khz; 1913 uint32_t bootup_smnclk_10khz; 1914 uint32_t bootup_socclk_10khz; 1915 uint32_t bootup_mp0clk_10khz; 1916 uint32_t bootup_mp1clk_10khz; 1917 uint32_t bootup_lclk_10khz; 1918 uint32_t bootup_dcefclk_10khz; 1919 uint32_t ctf_threshold_override_value; 1920 uint32_t reserved[5]; 1921 }; 1922 1923 struct atom_smu_info_v3_3 { 1924 struct atom_common_table_header table_header; 1925 uint8_t smuip_min_ver; 1926 uint8_t smuip_max_ver; 1927 uint8_t waflclk_ss_mode; 1928 uint8_t gpuclk_ss_mode; 1929 uint16_t sclk_ss_percentage; 1930 uint16_t sclk_ss_rate_10hz; 1931 uint16_t gpuclk_ss_percentage; // in unit of 0.001% 1932 uint16_t gpuclk_ss_rate_10hz; 1933 uint32_t core_refclk_10khz; 1934 uint8_t ac_dc_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for AC/DC switching, =0xff means invalid 1935 uint8_t ac_dc_polarity; // GPIO polarity for AC/DC switching 1936 uint8_t vr0hot_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for VR0 HOT event, =0xff means invalid 1937 uint8_t vr0hot_polarity; // GPIO polarity for VR0 HOT event 1938 uint8_t vr1hot_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for VR1 HOT event , =0xff means invalid 1939 uint8_t vr1hot_polarity; // GPIO polarity for VR1 HOT event 1940 uint8_t fw_ctf_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for CTF, =0xff means invalid 1941 uint8_t fw_ctf_polarity; // GPIO polarity for CTF 1942 uint8_t pcc_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for PCC, =0xff means invalid 1943 uint8_t pcc_gpio_polarity; // GPIO polarity for CTF 1944 uint16_t smugoldenoffset; 1945 uint32_t gpupll_vco_freq_10khz; 1946 uint32_t bootup_smnclk_10khz; 1947 uint32_t bootup_socclk_10khz; 1948 uint32_t bootup_mp0clk_10khz; 1949 uint32_t bootup_mp1clk_10khz; 1950 uint32_t bootup_lclk_10khz; 1951 uint32_t bootup_dcefclk_10khz; 1952 uint32_t ctf_threshold_override_value; 1953 uint32_t syspll3_0_vco_freq_10khz; 1954 uint32_t syspll3_1_vco_freq_10khz; 1955 uint32_t bootup_fclk_10khz; 1956 uint32_t bootup_waflclk_10khz; 1957 uint32_t smu_info_caps; 1958 uint16_t waflclk_ss_percentage; // in unit of 0.001% 1959 uint16_t smuinitoffset; 1960 uint32_t reserved; 1961 }; 1962 1963 struct atom_smu_info_v3_5 1964 { 1965 struct atom_common_table_header table_header; 1966 uint8_t smuip_min_ver; 1967 uint8_t smuip_max_ver; 1968 uint8_t waflclk_ss_mode; 1969 uint8_t gpuclk_ss_mode; 1970 uint16_t sclk_ss_percentage; 1971 uint16_t sclk_ss_rate_10hz; 1972 uint16_t gpuclk_ss_percentage; // in unit of 0.001% 1973 uint16_t gpuclk_ss_rate_10hz; 1974 uint32_t core_refclk_10khz; 1975 uint32_t syspll0_1_vco_freq_10khz; 1976 uint32_t syspll0_2_vco_freq_10khz; 1977 uint8_t pcc_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for PCC, =0xff means invalid 1978 uint8_t pcc_gpio_polarity; // GPIO polarity for CTF 1979 uint16_t smugoldenoffset; 1980 uint32_t syspll0_0_vco_freq_10khz; 1981 uint32_t bootup_smnclk_10khz; 1982 uint32_t bootup_socclk_10khz; 1983 uint32_t bootup_mp0clk_10khz; 1984 uint32_t bootup_mp1clk_10khz; 1985 uint32_t bootup_lclk_10khz; 1986 uint32_t bootup_dcefclk_10khz; 1987 uint32_t ctf_threshold_override_value; 1988 uint32_t syspll3_0_vco_freq_10khz; 1989 uint32_t syspll3_1_vco_freq_10khz; 1990 uint32_t bootup_fclk_10khz; 1991 uint32_t bootup_waflclk_10khz; 1992 uint32_t smu_info_caps; 1993 uint16_t waflclk_ss_percentage; // in unit of 0.001% 1994 uint16_t smuinitoffset; 1995 uint32_t bootup_dprefclk_10khz; 1996 uint32_t bootup_usbclk_10khz; 1997 uint32_t smb_slave_address; 1998 uint32_t cg_fdo_ctrl0_val; 1999 uint32_t cg_fdo_ctrl1_val; 2000 uint32_t cg_fdo_ctrl2_val; 2001 uint32_t gdfll_as_wait_ctrl_val; 2002 uint32_t gdfll_as_step_ctrl_val; 2003 uint32_t bootup_dtbclk_10khz; 2004 uint32_t fclk_syspll_refclk_10khz; 2005 uint32_t smusvi_svc0_val; 2006 uint32_t smusvi_svc1_val; 2007 uint32_t smusvi_svd0_val; 2008 uint32_t smusvi_svd1_val; 2009 uint32_t smusvi_svt0_val; 2010 uint32_t smusvi_svt1_val; 2011 uint32_t cg_tach_ctrl_val; 2012 uint32_t cg_pump_ctrl1_val; 2013 uint32_t cg_pump_tach_ctrl_val; 2014 uint32_t thm_ctf_delay_val; 2015 uint32_t thm_thermal_int_ctrl_val; 2016 uint32_t thm_tmon_config_val; 2017 uint32_t reserved[16]; 2018 }; 2019 2020 struct atom_smu_info_v3_6 2021 { 2022 struct atom_common_table_header table_header; 2023 uint8_t smuip_min_ver; 2024 uint8_t smuip_max_ver; 2025 uint8_t waflclk_ss_mode; 2026 uint8_t gpuclk_ss_mode; 2027 uint16_t sclk_ss_percentage; 2028 uint16_t sclk_ss_rate_10hz; 2029 uint16_t gpuclk_ss_percentage; 2030 uint16_t gpuclk_ss_rate_10hz; 2031 uint32_t core_refclk_10khz; 2032 uint32_t syspll0_1_vco_freq_10khz; 2033 uint32_t syspll0_2_vco_freq_10khz; 2034 uint8_t pcc_gpio_bit; 2035 uint8_t pcc_gpio_polarity; 2036 uint16_t smugoldenoffset; 2037 uint32_t syspll0_0_vco_freq_10khz; 2038 uint32_t bootup_smnclk_10khz; 2039 uint32_t bootup_socclk_10khz; 2040 uint32_t bootup_mp0clk_10khz; 2041 uint32_t bootup_mp1clk_10khz; 2042 uint32_t bootup_lclk_10khz; 2043 uint32_t bootup_dxioclk_10khz; 2044 uint32_t ctf_threshold_override_value; 2045 uint32_t syspll3_0_vco_freq_10khz; 2046 uint32_t syspll3_1_vco_freq_10khz; 2047 uint32_t bootup_fclk_10khz; 2048 uint32_t bootup_waflclk_10khz; 2049 uint32_t smu_info_caps; 2050 uint16_t waflclk_ss_percentage; 2051 uint16_t smuinitoffset; 2052 uint32_t bootup_gfxavsclk_10khz; 2053 uint32_t bootup_mpioclk_10khz; 2054 uint32_t smb_slave_address; 2055 uint32_t cg_fdo_ctrl0_val; 2056 uint32_t cg_fdo_ctrl1_val; 2057 uint32_t cg_fdo_ctrl2_val; 2058 uint32_t gdfll_as_wait_ctrl_val; 2059 uint32_t gdfll_as_step_ctrl_val; 2060 uint32_t reserved_clk; 2061 uint32_t fclk_syspll_refclk_10khz; 2062 uint32_t smusvi_svc0_val; 2063 uint32_t smusvi_svc1_val; 2064 uint32_t smusvi_svd0_val; 2065 uint32_t smusvi_svd1_val; 2066 uint32_t smusvi_svt0_val; 2067 uint32_t smusvi_svt1_val; 2068 uint32_t cg_tach_ctrl_val; 2069 uint32_t cg_pump_ctrl1_val; 2070 uint32_t cg_pump_tach_ctrl_val; 2071 uint32_t thm_ctf_delay_val; 2072 uint32_t thm_thermal_int_ctrl_val; 2073 uint32_t thm_tmon_config_val; 2074 uint32_t bootup_vclk_10khz; 2075 uint32_t bootup_dclk_10khz; 2076 uint32_t smu_gpiopad_pu_en_val; 2077 uint32_t smu_gpiopad_pd_en_val; 2078 uint32_t reserved[12]; 2079 }; 2080 2081 struct atom_smu_info_v4_0 { 2082 struct atom_common_table_header table_header; 2083 uint32_t bootup_gfxclk_bypass_10khz; 2084 uint32_t bootup_usrclk_10khz; 2085 uint32_t bootup_csrclk_10khz; 2086 uint32_t core_refclk_10khz; 2087 uint32_t syspll1_vco_freq_10khz; 2088 uint32_t syspll2_vco_freq_10khz; 2089 uint8_t pcc_gpio_bit; 2090 uint8_t pcc_gpio_polarity; 2091 uint16_t bootup_vddusr_mv; 2092 uint32_t syspll0_vco_freq_10khz; 2093 uint32_t bootup_smnclk_10khz; 2094 uint32_t bootup_socclk_10khz; 2095 uint32_t bootup_mp0clk_10khz; 2096 uint32_t bootup_mp1clk_10khz; 2097 uint32_t bootup_lclk_10khz; 2098 uint32_t bootup_dcefclk_10khz; 2099 uint32_t ctf_threshold_override_value; 2100 uint32_t syspll3_vco_freq_10khz; 2101 uint32_t mm_syspll_vco_freq_10khz; 2102 uint32_t bootup_fclk_10khz; 2103 uint32_t bootup_waflclk_10khz; 2104 uint32_t smu_info_caps; 2105 uint16_t waflclk_ss_percentage; 2106 uint16_t smuinitoffset; 2107 uint32_t bootup_dprefclk_10khz; 2108 uint32_t bootup_usbclk_10khz; 2109 uint32_t smb_slave_address; 2110 uint32_t cg_fdo_ctrl0_val; 2111 uint32_t cg_fdo_ctrl1_val; 2112 uint32_t cg_fdo_ctrl2_val; 2113 uint32_t gdfll_as_wait_ctrl_val; 2114 uint32_t gdfll_as_step_ctrl_val; 2115 uint32_t bootup_dtbclk_10khz; 2116 uint32_t fclk_syspll_refclk_10khz; 2117 uint32_t smusvi_svc0_val; 2118 uint32_t smusvi_svc1_val; 2119 uint32_t smusvi_svd0_val; 2120 uint32_t smusvi_svd1_val; 2121 uint32_t smusvi_svt0_val; 2122 uint32_t smusvi_svt1_val; 2123 uint32_t cg_tach_ctrl_val; 2124 uint32_t cg_pump_ctrl1_val; 2125 uint32_t cg_pump_tach_ctrl_val; 2126 uint32_t thm_ctf_delay_val; 2127 uint32_t thm_thermal_int_ctrl_val; 2128 uint32_t thm_tmon_config_val; 2129 uint32_t smbus_timing_cntrl0_val; 2130 uint32_t smbus_timing_cntrl1_val; 2131 uint32_t smbus_timing_cntrl2_val; 2132 uint32_t pwr_disp_timer_global_control_val; 2133 uint32_t bootup_mpioclk_10khz; 2134 uint32_t bootup_dclk0_10khz; 2135 uint32_t bootup_vclk0_10khz; 2136 uint32_t bootup_dclk1_10khz; 2137 uint32_t bootup_vclk1_10khz; 2138 uint32_t bootup_baco400clk_10khz; 2139 uint32_t bootup_baco1200clk_bypass_10khz; 2140 uint32_t bootup_baco700clk_bypass_10khz; 2141 uint32_t reserved[16]; 2142 }; 2143 2144 /* 2145 *************************************************************************** 2146 Data Table smc_dpm_info structure 2147 *************************************************************************** 2148 */ 2149 struct atom_smc_dpm_info_v4_1 2150 { 2151 struct atom_common_table_header table_header; 2152 uint8_t liquid1_i2c_address; 2153 uint8_t liquid2_i2c_address; 2154 uint8_t vr_i2c_address; 2155 uint8_t plx_i2c_address; 2156 2157 uint8_t liquid_i2c_linescl; 2158 uint8_t liquid_i2c_linesda; 2159 uint8_t vr_i2c_linescl; 2160 uint8_t vr_i2c_linesda; 2161 2162 uint8_t plx_i2c_linescl; 2163 uint8_t plx_i2c_linesda; 2164 uint8_t vrsensorpresent; 2165 uint8_t liquidsensorpresent; 2166 2167 uint16_t maxvoltagestepgfx; 2168 uint16_t maxvoltagestepsoc; 2169 2170 uint8_t vddgfxvrmapping; 2171 uint8_t vddsocvrmapping; 2172 uint8_t vddmem0vrmapping; 2173 uint8_t vddmem1vrmapping; 2174 2175 uint8_t gfxulvphasesheddingmask; 2176 uint8_t soculvphasesheddingmask; 2177 uint8_t padding8_v[2]; 2178 2179 uint16_t gfxmaxcurrent; 2180 uint8_t gfxoffset; 2181 uint8_t padding_telemetrygfx; 2182 2183 uint16_t socmaxcurrent; 2184 uint8_t socoffset; 2185 uint8_t padding_telemetrysoc; 2186 2187 uint16_t mem0maxcurrent; 2188 uint8_t mem0offset; 2189 uint8_t padding_telemetrymem0; 2190 2191 uint16_t mem1maxcurrent; 2192 uint8_t mem1offset; 2193 uint8_t padding_telemetrymem1; 2194 2195 uint8_t acdcgpio; 2196 uint8_t acdcpolarity; 2197 uint8_t vr0hotgpio; 2198 uint8_t vr0hotpolarity; 2199 2200 uint8_t vr1hotgpio; 2201 uint8_t vr1hotpolarity; 2202 uint8_t padding1; 2203 uint8_t padding2; 2204 2205 uint8_t ledpin0; 2206 uint8_t ledpin1; 2207 uint8_t ledpin2; 2208 uint8_t padding8_4; 2209 2210 uint8_t pllgfxclkspreadenabled; 2211 uint8_t pllgfxclkspreadpercent; 2212 uint16_t pllgfxclkspreadfreq; 2213 2214 uint8_t uclkspreadenabled; 2215 uint8_t uclkspreadpercent; 2216 uint16_t uclkspreadfreq; 2217 2218 uint8_t socclkspreadenabled; 2219 uint8_t socclkspreadpercent; 2220 uint16_t socclkspreadfreq; 2221 2222 uint8_t acggfxclkspreadenabled; 2223 uint8_t acggfxclkspreadpercent; 2224 uint16_t acggfxclkspreadfreq; 2225 2226 uint8_t Vr2_I2C_address; 2227 uint8_t padding_vr2[3]; 2228 2229 uint32_t boardreserved[9]; 2230 }; 2231 2232 /* 2233 *************************************************************************** 2234 Data Table smc_dpm_info structure 2235 *************************************************************************** 2236 */ 2237 struct atom_smc_dpm_info_v4_3 2238 { 2239 struct atom_common_table_header table_header; 2240 uint8_t liquid1_i2c_address; 2241 uint8_t liquid2_i2c_address; 2242 uint8_t vr_i2c_address; 2243 uint8_t plx_i2c_address; 2244 2245 uint8_t liquid_i2c_linescl; 2246 uint8_t liquid_i2c_linesda; 2247 uint8_t vr_i2c_linescl; 2248 uint8_t vr_i2c_linesda; 2249 2250 uint8_t plx_i2c_linescl; 2251 uint8_t plx_i2c_linesda; 2252 uint8_t vrsensorpresent; 2253 uint8_t liquidsensorpresent; 2254 2255 uint16_t maxvoltagestepgfx; 2256 uint16_t maxvoltagestepsoc; 2257 2258 uint8_t vddgfxvrmapping; 2259 uint8_t vddsocvrmapping; 2260 uint8_t vddmem0vrmapping; 2261 uint8_t vddmem1vrmapping; 2262 2263 uint8_t gfxulvphasesheddingmask; 2264 uint8_t soculvphasesheddingmask; 2265 uint8_t externalsensorpresent; 2266 uint8_t padding8_v; 2267 2268 uint16_t gfxmaxcurrent; 2269 uint8_t gfxoffset; 2270 uint8_t padding_telemetrygfx; 2271 2272 uint16_t socmaxcurrent; 2273 uint8_t socoffset; 2274 uint8_t padding_telemetrysoc; 2275 2276 uint16_t mem0maxcurrent; 2277 uint8_t mem0offset; 2278 uint8_t padding_telemetrymem0; 2279 2280 uint16_t mem1maxcurrent; 2281 uint8_t mem1offset; 2282 uint8_t padding_telemetrymem1; 2283 2284 uint8_t acdcgpio; 2285 uint8_t acdcpolarity; 2286 uint8_t vr0hotgpio; 2287 uint8_t vr0hotpolarity; 2288 2289 uint8_t vr1hotgpio; 2290 uint8_t vr1hotpolarity; 2291 uint8_t padding1; 2292 uint8_t padding2; 2293 2294 uint8_t ledpin0; 2295 uint8_t ledpin1; 2296 uint8_t ledpin2; 2297 uint8_t padding8_4; 2298 2299 uint8_t pllgfxclkspreadenabled; 2300 uint8_t pllgfxclkspreadpercent; 2301 uint16_t pllgfxclkspreadfreq; 2302 2303 uint8_t uclkspreadenabled; 2304 uint8_t uclkspreadpercent; 2305 uint16_t uclkspreadfreq; 2306 2307 uint8_t fclkspreadenabled; 2308 uint8_t fclkspreadpercent; 2309 uint16_t fclkspreadfreq; 2310 2311 uint8_t fllgfxclkspreadenabled; 2312 uint8_t fllgfxclkspreadpercent; 2313 uint16_t fllgfxclkspreadfreq; 2314 2315 uint32_t boardreserved[10]; 2316 }; 2317 2318 struct smudpm_i2ccontrollerconfig_t { 2319 uint32_t enabled; 2320 uint32_t slaveaddress; 2321 uint32_t controllerport; 2322 uint32_t controllername; 2323 uint32_t thermalthrottler; 2324 uint32_t i2cprotocol; 2325 uint32_t i2cspeed; 2326 }; 2327 2328 struct atom_smc_dpm_info_v4_4 2329 { 2330 struct atom_common_table_header table_header; 2331 uint32_t i2c_padding[3]; 2332 2333 uint16_t maxvoltagestepgfx; 2334 uint16_t maxvoltagestepsoc; 2335 2336 uint8_t vddgfxvrmapping; 2337 uint8_t vddsocvrmapping; 2338 uint8_t vddmem0vrmapping; 2339 uint8_t vddmem1vrmapping; 2340 2341 uint8_t gfxulvphasesheddingmask; 2342 uint8_t soculvphasesheddingmask; 2343 uint8_t externalsensorpresent; 2344 uint8_t padding8_v; 2345 2346 uint16_t gfxmaxcurrent; 2347 uint8_t gfxoffset; 2348 uint8_t padding_telemetrygfx; 2349 2350 uint16_t socmaxcurrent; 2351 uint8_t socoffset; 2352 uint8_t padding_telemetrysoc; 2353 2354 uint16_t mem0maxcurrent; 2355 uint8_t mem0offset; 2356 uint8_t padding_telemetrymem0; 2357 2358 uint16_t mem1maxcurrent; 2359 uint8_t mem1offset; 2360 uint8_t padding_telemetrymem1; 2361 2362 2363 uint8_t acdcgpio; 2364 uint8_t acdcpolarity; 2365 uint8_t vr0hotgpio; 2366 uint8_t vr0hotpolarity; 2367 2368 uint8_t vr1hotgpio; 2369 uint8_t vr1hotpolarity; 2370 uint8_t padding1; 2371 uint8_t padding2; 2372 2373 2374 uint8_t ledpin0; 2375 uint8_t ledpin1; 2376 uint8_t ledpin2; 2377 uint8_t padding8_4; 2378 2379 2380 uint8_t pllgfxclkspreadenabled; 2381 uint8_t pllgfxclkspreadpercent; 2382 uint16_t pllgfxclkspreadfreq; 2383 2384 2385 uint8_t uclkspreadenabled; 2386 uint8_t uclkspreadpercent; 2387 uint16_t uclkspreadfreq; 2388 2389 2390 uint8_t fclkspreadenabled; 2391 uint8_t fclkspreadpercent; 2392 uint16_t fclkspreadfreq; 2393 2394 2395 uint8_t fllgfxclkspreadenabled; 2396 uint8_t fllgfxclkspreadpercent; 2397 uint16_t fllgfxclkspreadfreq; 2398 2399 2400 struct smudpm_i2ccontrollerconfig_t i2ccontrollers[7]; 2401 2402 2403 uint32_t boardreserved[10]; 2404 }; 2405 2406 enum smudpm_v4_5_i2ccontrollername_e{ 2407 SMC_V4_5_I2C_CONTROLLER_NAME_VR_GFX = 0, 2408 SMC_V4_5_I2C_CONTROLLER_NAME_VR_SOC, 2409 SMC_V4_5_I2C_CONTROLLER_NAME_VR_VDDCI, 2410 SMC_V4_5_I2C_CONTROLLER_NAME_VR_MVDD, 2411 SMC_V4_5_I2C_CONTROLLER_NAME_LIQUID0, 2412 SMC_V4_5_I2C_CONTROLLER_NAME_LIQUID1, 2413 SMC_V4_5_I2C_CONTROLLER_NAME_PLX, 2414 SMC_V4_5_I2C_CONTROLLER_NAME_SPARE, 2415 SMC_V4_5_I2C_CONTROLLER_NAME_COUNT, 2416 }; 2417 2418 enum smudpm_v4_5_i2ccontrollerthrottler_e{ 2419 SMC_V4_5_I2C_CONTROLLER_THROTTLER_TYPE_NONE = 0, 2420 SMC_V4_5_I2C_CONTROLLER_THROTTLER_VR_GFX, 2421 SMC_V4_5_I2C_CONTROLLER_THROTTLER_VR_SOC, 2422 SMC_V4_5_I2C_CONTROLLER_THROTTLER_VR_VDDCI, 2423 SMC_V4_5_I2C_CONTROLLER_THROTTLER_VR_MVDD, 2424 SMC_V4_5_I2C_CONTROLLER_THROTTLER_LIQUID0, 2425 SMC_V4_5_I2C_CONTROLLER_THROTTLER_LIQUID1, 2426 SMC_V4_5_I2C_CONTROLLER_THROTTLER_PLX, 2427 SMC_V4_5_I2C_CONTROLLER_THROTTLER_COUNT, 2428 }; 2429 2430 enum smudpm_v4_5_i2ccontrollerprotocol_e{ 2431 SMC_V4_5_I2C_CONTROLLER_PROTOCOL_VR_0, 2432 SMC_V4_5_I2C_CONTROLLER_PROTOCOL_VR_1, 2433 SMC_V4_5_I2C_CONTROLLER_PROTOCOL_TMP_0, 2434 SMC_V4_5_I2C_CONTROLLER_PROTOCOL_TMP_1, 2435 SMC_V4_5_I2C_CONTROLLER_PROTOCOL_SPARE_0, 2436 SMC_V4_5_I2C_CONTROLLER_PROTOCOL_SPARE_1, 2437 SMC_V4_5_I2C_CONTROLLER_PROTOCOL_COUNT, 2438 }; 2439 2440 struct smudpm_i2c_controller_config_v2 2441 { 2442 uint8_t Enabled; 2443 uint8_t Speed; 2444 uint8_t Padding[2]; 2445 uint32_t SlaveAddress; 2446 uint8_t ControllerPort; 2447 uint8_t ControllerName; 2448 uint8_t ThermalThrotter; 2449 uint8_t I2cProtocol; 2450 }; 2451 2452 struct atom_smc_dpm_info_v4_5 2453 { 2454 struct atom_common_table_header table_header; 2455 // SECTION: BOARD PARAMETERS 2456 // I2C Control 2457 struct smudpm_i2c_controller_config_v2 I2cControllers[8]; 2458 2459 // SVI2 Board Parameters 2460 uint16_t MaxVoltageStepGfx; // In mV(Q2) Max voltage step that SMU will request. Multiple steps are taken if voltage change exceeds this value. 2461 uint16_t MaxVoltageStepSoc; // In mV(Q2) Max voltage step that SMU will request. Multiple steps are taken if voltage change exceeds this value. 2462 2463 uint8_t VddGfxVrMapping; // Use VR_MAPPING* bitfields 2464 uint8_t VddSocVrMapping; // Use VR_MAPPING* bitfields 2465 uint8_t VddMem0VrMapping; // Use VR_MAPPING* bitfields 2466 uint8_t VddMem1VrMapping; // Use VR_MAPPING* bitfields 2467 2468 uint8_t GfxUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode 2469 uint8_t SocUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode 2470 uint8_t ExternalSensorPresent; // External RDI connected to TMON (aka TEMP IN) 2471 uint8_t Padding8_V; 2472 2473 // Telemetry Settings 2474 uint16_t GfxMaxCurrent; // in Amps 2475 uint8_t GfxOffset; // in Amps 2476 uint8_t Padding_TelemetryGfx; 2477 uint16_t SocMaxCurrent; // in Amps 2478 uint8_t SocOffset; // in Amps 2479 uint8_t Padding_TelemetrySoc; 2480 2481 uint16_t Mem0MaxCurrent; // in Amps 2482 uint8_t Mem0Offset; // in Amps 2483 uint8_t Padding_TelemetryMem0; 2484 2485 uint16_t Mem1MaxCurrent; // in Amps 2486 uint8_t Mem1Offset; // in Amps 2487 uint8_t Padding_TelemetryMem1; 2488 2489 // GPIO Settings 2490 uint8_t AcDcGpio; // GPIO pin configured for AC/DC switching 2491 uint8_t AcDcPolarity; // GPIO polarity for AC/DC switching 2492 uint8_t VR0HotGpio; // GPIO pin configured for VR0 HOT event 2493 uint8_t VR0HotPolarity; // GPIO polarity for VR0 HOT event 2494 2495 uint8_t VR1HotGpio; // GPIO pin configured for VR1 HOT event 2496 uint8_t VR1HotPolarity; // GPIO polarity for VR1 HOT event 2497 uint8_t GthrGpio; // GPIO pin configured for GTHR Event 2498 uint8_t GthrPolarity; // replace GPIO polarity for GTHR 2499 2500 // LED Display Settings 2501 uint8_t LedPin0; // GPIO number for LedPin[0] 2502 uint8_t LedPin1; // GPIO number for LedPin[1] 2503 uint8_t LedPin2; // GPIO number for LedPin[2] 2504 uint8_t padding8_4; 2505 2506 // GFXCLK PLL Spread Spectrum 2507 uint8_t PllGfxclkSpreadEnabled; // on or off 2508 uint8_t PllGfxclkSpreadPercent; // Q4.4 2509 uint16_t PllGfxclkSpreadFreq; // kHz 2510 2511 // GFXCLK DFLL Spread Spectrum 2512 uint8_t DfllGfxclkSpreadEnabled; // on or off 2513 uint8_t DfllGfxclkSpreadPercent; // Q4.4 2514 uint16_t DfllGfxclkSpreadFreq; // kHz 2515 2516 // UCLK Spread Spectrum 2517 uint8_t UclkSpreadEnabled; // on or off 2518 uint8_t UclkSpreadPercent; // Q4.4 2519 uint16_t UclkSpreadFreq; // kHz 2520 2521 // SOCCLK Spread Spectrum 2522 uint8_t SoclkSpreadEnabled; // on or off 2523 uint8_t SocclkSpreadPercent; // Q4.4 2524 uint16_t SocclkSpreadFreq; // kHz 2525 2526 // Total board power 2527 uint16_t TotalBoardPower; //Only needed for TCP Estimated case, where TCP = TGP+Total Board Power 2528 uint16_t BoardPadding; 2529 2530 // Mvdd Svi2 Div Ratio Setting 2531 uint32_t MvddRatio; // This is used for MVDD Vid workaround. It has 16 fractional bits (Q16.16) 2532 2533 uint32_t BoardReserved[9]; 2534 2535 }; 2536 2537 struct atom_smc_dpm_info_v4_6 2538 { 2539 struct atom_common_table_header table_header; 2540 // section: board parameters 2541 uint32_t i2c_padding[3]; // old i2c control are moved to new area 2542 2543 uint16_t maxvoltagestepgfx; // in mv(q2) max voltage step that smu will request. multiple steps are taken if voltage change exceeds this value. 2544 uint16_t maxvoltagestepsoc; // in mv(q2) max voltage step that smu will request. multiple steps are taken if voltage change exceeds this value. 2545 2546 uint8_t vddgfxvrmapping; // use vr_mapping* bitfields 2547 uint8_t vddsocvrmapping; // use vr_mapping* bitfields 2548 uint8_t vddmemvrmapping; // use vr_mapping* bitfields 2549 uint8_t boardvrmapping; // use vr_mapping* bitfields 2550 2551 uint8_t gfxulvphasesheddingmask; // set this to 1 to set psi0/1 to 1 in ulv mode 2552 uint8_t externalsensorpresent; // external rdi connected to tmon (aka temp in) 2553 uint8_t padding8_v[2]; 2554 2555 // telemetry settings 2556 uint16_t gfxmaxcurrent; // in amps 2557 uint8_t gfxoffset; // in amps 2558 uint8_t padding_telemetrygfx; 2559 2560 uint16_t socmaxcurrent; // in amps 2561 uint8_t socoffset; // in amps 2562 uint8_t padding_telemetrysoc; 2563 2564 uint16_t memmaxcurrent; // in amps 2565 uint8_t memoffset; // in amps 2566 uint8_t padding_telemetrymem; 2567 2568 uint16_t boardmaxcurrent; // in amps 2569 uint8_t boardoffset; // in amps 2570 uint8_t padding_telemetryboardinput; 2571 2572 // gpio settings 2573 uint8_t vr0hotgpio; // gpio pin configured for vr0 hot event 2574 uint8_t vr0hotpolarity; // gpio polarity for vr0 hot event 2575 uint8_t vr1hotgpio; // gpio pin configured for vr1 hot event 2576 uint8_t vr1hotpolarity; // gpio polarity for vr1 hot event 2577 2578 // gfxclk pll spread spectrum 2579 uint8_t pllgfxclkspreadenabled; // on or off 2580 uint8_t pllgfxclkspreadpercent; // q4.4 2581 uint16_t pllgfxclkspreadfreq; // khz 2582 2583 // uclk spread spectrum 2584 uint8_t uclkspreadenabled; // on or off 2585 uint8_t uclkspreadpercent; // q4.4 2586 uint16_t uclkspreadfreq; // khz 2587 2588 // fclk spread spectrum 2589 uint8_t fclkspreadenabled; // on or off 2590 uint8_t fclkspreadpercent; // q4.4 2591 uint16_t fclkspreadfreq; // khz 2592 2593 2594 // gfxclk fll spread spectrum 2595 uint8_t fllgfxclkspreadenabled; // on or off 2596 uint8_t fllgfxclkspreadpercent; // q4.4 2597 uint16_t fllgfxclkspreadfreq; // khz 2598 2599 // i2c controller structure 2600 struct smudpm_i2c_controller_config_v2 i2ccontrollers[8]; 2601 2602 // memory section 2603 uint32_t memorychannelenabled; // for dram use only, max 32 channels enabled bit mask. 2604 2605 uint8_t drambitwidth; // for dram use only. see dram bit width type defines 2606 uint8_t paddingmem[3]; 2607 2608 // total board power 2609 uint16_t totalboardpower; //only needed for tcp estimated case, where tcp = tgp+total board power 2610 uint16_t boardpadding; 2611 2612 // section: xgmi training 2613 uint8_t xgmilinkspeed[4]; 2614 uint8_t xgmilinkwidth[4]; 2615 2616 uint16_t xgmifclkfreq[4]; 2617 uint16_t xgmisocvoltage[4]; 2618 2619 // reserved 2620 uint32_t boardreserved[10]; 2621 }; 2622 2623 struct atom_smc_dpm_info_v4_7 2624 { 2625 struct atom_common_table_header table_header; 2626 // SECTION: BOARD PARAMETERS 2627 // I2C Control 2628 struct smudpm_i2c_controller_config_v2 I2cControllers[8]; 2629 2630 // SVI2 Board Parameters 2631 uint16_t MaxVoltageStepGfx; // In mV(Q2) Max voltage step that SMU will request. Multiple steps are taken if voltage change exceeds this value. 2632 uint16_t MaxVoltageStepSoc; // In mV(Q2) Max voltage step that SMU will request. Multiple steps are taken if voltage change exceeds this value. 2633 2634 uint8_t VddGfxVrMapping; // Use VR_MAPPING* bitfields 2635 uint8_t VddSocVrMapping; // Use VR_MAPPING* bitfields 2636 uint8_t VddMem0VrMapping; // Use VR_MAPPING* bitfields 2637 uint8_t VddMem1VrMapping; // Use VR_MAPPING* bitfields 2638 2639 uint8_t GfxUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode 2640 uint8_t SocUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode 2641 uint8_t ExternalSensorPresent; // External RDI connected to TMON (aka TEMP IN) 2642 uint8_t Padding8_V; 2643 2644 // Telemetry Settings 2645 uint16_t GfxMaxCurrent; // in Amps 2646 uint8_t GfxOffset; // in Amps 2647 uint8_t Padding_TelemetryGfx; 2648 uint16_t SocMaxCurrent; // in Amps 2649 uint8_t SocOffset; // in Amps 2650 uint8_t Padding_TelemetrySoc; 2651 2652 uint16_t Mem0MaxCurrent; // in Amps 2653 uint8_t Mem0Offset; // in Amps 2654 uint8_t Padding_TelemetryMem0; 2655 2656 uint16_t Mem1MaxCurrent; // in Amps 2657 uint8_t Mem1Offset; // in Amps 2658 uint8_t Padding_TelemetryMem1; 2659 2660 // GPIO Settings 2661 uint8_t AcDcGpio; // GPIO pin configured for AC/DC switching 2662 uint8_t AcDcPolarity; // GPIO polarity for AC/DC switching 2663 uint8_t VR0HotGpio; // GPIO pin configured for VR0 HOT event 2664 uint8_t VR0HotPolarity; // GPIO polarity for VR0 HOT event 2665 2666 uint8_t VR1HotGpio; // GPIO pin configured for VR1 HOT event 2667 uint8_t VR1HotPolarity; // GPIO polarity for VR1 HOT event 2668 uint8_t GthrGpio; // GPIO pin configured for GTHR Event 2669 uint8_t GthrPolarity; // replace GPIO polarity for GTHR 2670 2671 // LED Display Settings 2672 uint8_t LedPin0; // GPIO number for LedPin[0] 2673 uint8_t LedPin1; // GPIO number for LedPin[1] 2674 uint8_t LedPin2; // GPIO number for LedPin[2] 2675 uint8_t padding8_4; 2676 2677 // GFXCLK PLL Spread Spectrum 2678 uint8_t PllGfxclkSpreadEnabled; // on or off 2679 uint8_t PllGfxclkSpreadPercent; // Q4.4 2680 uint16_t PllGfxclkSpreadFreq; // kHz 2681 2682 // GFXCLK DFLL Spread Spectrum 2683 uint8_t DfllGfxclkSpreadEnabled; // on or off 2684 uint8_t DfllGfxclkSpreadPercent; // Q4.4 2685 uint16_t DfllGfxclkSpreadFreq; // kHz 2686 2687 // UCLK Spread Spectrum 2688 uint8_t UclkSpreadEnabled; // on or off 2689 uint8_t UclkSpreadPercent; // Q4.4 2690 uint16_t UclkSpreadFreq; // kHz 2691 2692 // SOCCLK Spread Spectrum 2693 uint8_t SoclkSpreadEnabled; // on or off 2694 uint8_t SocclkSpreadPercent; // Q4.4 2695 uint16_t SocclkSpreadFreq; // kHz 2696 2697 // Total board power 2698 uint16_t TotalBoardPower; //Only needed for TCP Estimated case, where TCP = TGP+Total Board Power 2699 uint16_t BoardPadding; 2700 2701 // Mvdd Svi2 Div Ratio Setting 2702 uint32_t MvddRatio; // This is used for MVDD Vid workaround. It has 16 fractional bits (Q16.16) 2703 2704 // GPIO pins for I2C communications with 2nd controller for Input Telemetry Sequence 2705 uint8_t GpioI2cScl; // Serial Clock 2706 uint8_t GpioI2cSda; // Serial Data 2707 uint16_t GpioPadding; 2708 2709 // Additional LED Display Settings 2710 uint8_t LedPin3; // GPIO number for LedPin[3] - PCIE GEN Speed 2711 uint8_t LedPin4; // GPIO number for LedPin[4] - PMFW Error Status 2712 uint16_t LedEnableMask; 2713 2714 // Power Limit Scalars 2715 uint8_t PowerLimitScalar[4]; //[PPT_THROTTLER_COUNT] 2716 2717 uint8_t MvddUlvPhaseSheddingMask; 2718 uint8_t VddciUlvPhaseSheddingMask; 2719 uint8_t Padding8_Psi1; 2720 uint8_t Padding8_Psi2; 2721 2722 uint32_t BoardReserved[5]; 2723 }; 2724 2725 struct smudpm_i2c_controller_config_v3 2726 { 2727 uint8_t Enabled; 2728 uint8_t Speed; 2729 uint8_t SlaveAddress; 2730 uint8_t ControllerPort; 2731 uint8_t ControllerName; 2732 uint8_t ThermalThrotter; 2733 uint8_t I2cProtocol; 2734 uint8_t PaddingConfig; 2735 }; 2736 2737 struct atom_smc_dpm_info_v4_9 2738 { 2739 struct atom_common_table_header table_header; 2740 2741 //SECTION: Gaming Clocks 2742 //uint32_t GamingClk[6]; 2743 2744 // SECTION: I2C Control 2745 struct smudpm_i2c_controller_config_v3 I2cControllers[16]; 2746 2747 uint8_t GpioScl; // GPIO Number for SCL Line, used only for CKSVII2C1 2748 uint8_t GpioSda; // GPIO Number for SDA Line, used only for CKSVII2C1 2749 uint8_t FchUsbPdSlaveAddr; //For requesting USB PD controller S-states via FCH I2C when entering PME turn off 2750 uint8_t I2cSpare; 2751 2752 // SECTION: SVI2 Board Parameters 2753 uint8_t VddGfxVrMapping; // Use VR_MAPPING* bitfields 2754 uint8_t VddSocVrMapping; // Use VR_MAPPING* bitfields 2755 uint8_t VddMem0VrMapping; // Use VR_MAPPING* bitfields 2756 uint8_t VddMem1VrMapping; // Use VR_MAPPING* bitfields 2757 2758 uint8_t GfxUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode 2759 uint8_t SocUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode 2760 uint8_t VddciUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode 2761 uint8_t MvddUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode 2762 2763 // SECTION: Telemetry Settings 2764 uint16_t GfxMaxCurrent; // in Amps 2765 uint8_t GfxOffset; // in Amps 2766 uint8_t Padding_TelemetryGfx; 2767 2768 uint16_t SocMaxCurrent; // in Amps 2769 uint8_t SocOffset; // in Amps 2770 uint8_t Padding_TelemetrySoc; 2771 2772 uint16_t Mem0MaxCurrent; // in Amps 2773 uint8_t Mem0Offset; // in Amps 2774 uint8_t Padding_TelemetryMem0; 2775 2776 uint16_t Mem1MaxCurrent; // in Amps 2777 uint8_t Mem1Offset; // in Amps 2778 uint8_t Padding_TelemetryMem1; 2779 2780 uint32_t MvddRatio; // This is used for MVDD Svi2 Div Ratio workaround. It has 16 fractional bits (Q16.16) 2781 2782 // SECTION: GPIO Settings 2783 uint8_t AcDcGpio; // GPIO pin configured for AC/DC switching 2784 uint8_t AcDcPolarity; // GPIO polarity for AC/DC switching 2785 uint8_t VR0HotGpio; // GPIO pin configured for VR0 HOT event 2786 uint8_t VR0HotPolarity; // GPIO polarity for VR0 HOT event 2787 2788 uint8_t VR1HotGpio; // GPIO pin configured for VR1 HOT event 2789 uint8_t VR1HotPolarity; // GPIO polarity for VR1 HOT event 2790 uint8_t GthrGpio; // GPIO pin configured for GTHR Event 2791 uint8_t GthrPolarity; // replace GPIO polarity for GTHR 2792 2793 // LED Display Settings 2794 uint8_t LedPin0; // GPIO number for LedPin[0] 2795 uint8_t LedPin1; // GPIO number for LedPin[1] 2796 uint8_t LedPin2; // GPIO number for LedPin[2] 2797 uint8_t LedEnableMask; 2798 2799 uint8_t LedPcie; // GPIO number for PCIE results 2800 uint8_t LedError; // GPIO number for Error Cases 2801 uint8_t LedSpare1[2]; 2802 2803 // SECTION: Clock Spread Spectrum 2804 2805 // GFXCLK PLL Spread Spectrum 2806 uint8_t PllGfxclkSpreadEnabled; // on or off 2807 uint8_t PllGfxclkSpreadPercent; // Q4.4 2808 uint16_t PllGfxclkSpreadFreq; // kHz 2809 2810 // GFXCLK DFLL Spread Spectrum 2811 uint8_t DfllGfxclkSpreadEnabled; // on or off 2812 uint8_t DfllGfxclkSpreadPercent; // Q4.4 2813 uint16_t DfllGfxclkSpreadFreq; // kHz 2814 2815 // UCLK Spread Spectrum 2816 uint8_t UclkSpreadEnabled; // on or off 2817 uint8_t UclkSpreadPercent; // Q4.4 2818 uint16_t UclkSpreadFreq; // kHz 2819 2820 // FCLK Spread Spectrum 2821 uint8_t FclkSpreadEnabled; // on or off 2822 uint8_t FclkSpreadPercent; // Q4.4 2823 uint16_t FclkSpreadFreq; // kHz 2824 2825 // Section: Memory Config 2826 uint32_t MemoryChannelEnabled; // For DRAM use only, Max 32 channels enabled bit mask. 2827 2828 uint8_t DramBitWidth; // For DRAM use only. See Dram Bit width type defines 2829 uint8_t PaddingMem1[3]; 2830 2831 // Section: Total Board Power 2832 uint16_t TotalBoardPower; //Only needed for TCP Estimated case, where TCP = TGP+Total Board Power 2833 uint16_t BoardPowerPadding; 2834 2835 // SECTION: XGMI Training 2836 uint8_t XgmiLinkSpeed [4]; 2837 uint8_t XgmiLinkWidth [4]; 2838 2839 uint16_t XgmiFclkFreq [4]; 2840 uint16_t XgmiSocVoltage [4]; 2841 2842 // SECTION: Board Reserved 2843 2844 uint32_t BoardReserved[16]; 2845 2846 }; 2847 2848 struct atom_smc_dpm_info_v4_10 2849 { 2850 struct atom_common_table_header table_header; 2851 2852 // SECTION: BOARD PARAMETERS 2853 // Telemetry Settings 2854 uint16_t GfxMaxCurrent; // in Amps 2855 uint8_t GfxOffset; // in Amps 2856 uint8_t Padding_TelemetryGfx; 2857 2858 uint16_t SocMaxCurrent; // in Amps 2859 uint8_t SocOffset; // in Amps 2860 uint8_t Padding_TelemetrySoc; 2861 2862 uint16_t MemMaxCurrent; // in Amps 2863 uint8_t MemOffset; // in Amps 2864 uint8_t Padding_TelemetryMem; 2865 2866 uint16_t BoardMaxCurrent; // in Amps 2867 uint8_t BoardOffset; // in Amps 2868 uint8_t Padding_TelemetryBoardInput; 2869 2870 // Platform input telemetry voltage coefficient 2871 uint32_t BoardVoltageCoeffA; // decode by /1000 2872 uint32_t BoardVoltageCoeffB; // decode by /1000 2873 2874 // GPIO Settings 2875 uint8_t VR0HotGpio; // GPIO pin configured for VR0 HOT event 2876 uint8_t VR0HotPolarity; // GPIO polarity for VR0 HOT event 2877 uint8_t VR1HotGpio; // GPIO pin configured for VR1 HOT event 2878 uint8_t VR1HotPolarity; // GPIO polarity for VR1 HOT event 2879 2880 // UCLK Spread Spectrum 2881 uint8_t UclkSpreadEnabled; // on or off 2882 uint8_t UclkSpreadPercent; // Q4.4 2883 uint16_t UclkSpreadFreq; // kHz 2884 2885 // FCLK Spread Spectrum 2886 uint8_t FclkSpreadEnabled; // on or off 2887 uint8_t FclkSpreadPercent; // Q4.4 2888 uint16_t FclkSpreadFreq; // kHz 2889 2890 // I2C Controller Structure 2891 struct smudpm_i2c_controller_config_v3 I2cControllers[8]; 2892 2893 // GPIO pins for I2C communications with 2nd controller for Input Telemetry Sequence 2894 uint8_t GpioI2cScl; // Serial Clock 2895 uint8_t GpioI2cSda; // Serial Data 2896 uint16_t spare5; 2897 2898 uint32_t reserved[16]; 2899 }; 2900 2901 /* 2902 *************************************************************************** 2903 Data Table asic_profiling_info structure 2904 *************************************************************************** 2905 */ 2906 struct atom_asic_profiling_info_v4_1 2907 { 2908 struct atom_common_table_header table_header; 2909 uint32_t maxvddc; 2910 uint32_t minvddc; 2911 uint32_t avfs_meannsigma_acontant0; 2912 uint32_t avfs_meannsigma_acontant1; 2913 uint32_t avfs_meannsigma_acontant2; 2914 uint16_t avfs_meannsigma_dc_tol_sigma; 2915 uint16_t avfs_meannsigma_platform_mean; 2916 uint16_t avfs_meannsigma_platform_sigma; 2917 uint32_t gb_vdroop_table_cksoff_a0; 2918 uint32_t gb_vdroop_table_cksoff_a1; 2919 uint32_t gb_vdroop_table_cksoff_a2; 2920 uint32_t gb_vdroop_table_ckson_a0; 2921 uint32_t gb_vdroop_table_ckson_a1; 2922 uint32_t gb_vdroop_table_ckson_a2; 2923 uint32_t avfsgb_fuse_table_cksoff_m1; 2924 uint32_t avfsgb_fuse_table_cksoff_m2; 2925 uint32_t avfsgb_fuse_table_cksoff_b; 2926 uint32_t avfsgb_fuse_table_ckson_m1; 2927 uint32_t avfsgb_fuse_table_ckson_m2; 2928 uint32_t avfsgb_fuse_table_ckson_b; 2929 uint16_t max_voltage_0_25mv; 2930 uint8_t enable_gb_vdroop_table_cksoff; 2931 uint8_t enable_gb_vdroop_table_ckson; 2932 uint8_t enable_gb_fuse_table_cksoff; 2933 uint8_t enable_gb_fuse_table_ckson; 2934 uint16_t psm_age_comfactor; 2935 uint8_t enable_apply_avfs_cksoff_voltage; 2936 uint8_t reserved; 2937 uint32_t dispclk2gfxclk_a; 2938 uint32_t dispclk2gfxclk_b; 2939 uint32_t dispclk2gfxclk_c; 2940 uint32_t pixclk2gfxclk_a; 2941 uint32_t pixclk2gfxclk_b; 2942 uint32_t pixclk2gfxclk_c; 2943 uint32_t dcefclk2gfxclk_a; 2944 uint32_t dcefclk2gfxclk_b; 2945 uint32_t dcefclk2gfxclk_c; 2946 uint32_t phyclk2gfxclk_a; 2947 uint32_t phyclk2gfxclk_b; 2948 uint32_t phyclk2gfxclk_c; 2949 }; 2950 2951 struct atom_asic_profiling_info_v4_2 { 2952 struct atom_common_table_header table_header; 2953 uint32_t maxvddc; 2954 uint32_t minvddc; 2955 uint32_t avfs_meannsigma_acontant0; 2956 uint32_t avfs_meannsigma_acontant1; 2957 uint32_t avfs_meannsigma_acontant2; 2958 uint16_t avfs_meannsigma_dc_tol_sigma; 2959 uint16_t avfs_meannsigma_platform_mean; 2960 uint16_t avfs_meannsigma_platform_sigma; 2961 uint32_t gb_vdroop_table_cksoff_a0; 2962 uint32_t gb_vdroop_table_cksoff_a1; 2963 uint32_t gb_vdroop_table_cksoff_a2; 2964 uint32_t gb_vdroop_table_ckson_a0; 2965 uint32_t gb_vdroop_table_ckson_a1; 2966 uint32_t gb_vdroop_table_ckson_a2; 2967 uint32_t avfsgb_fuse_table_cksoff_m1; 2968 uint32_t avfsgb_fuse_table_cksoff_m2; 2969 uint32_t avfsgb_fuse_table_cksoff_b; 2970 uint32_t avfsgb_fuse_table_ckson_m1; 2971 uint32_t avfsgb_fuse_table_ckson_m2; 2972 uint32_t avfsgb_fuse_table_ckson_b; 2973 uint16_t max_voltage_0_25mv; 2974 uint8_t enable_gb_vdroop_table_cksoff; 2975 uint8_t enable_gb_vdroop_table_ckson; 2976 uint8_t enable_gb_fuse_table_cksoff; 2977 uint8_t enable_gb_fuse_table_ckson; 2978 uint16_t psm_age_comfactor; 2979 uint8_t enable_apply_avfs_cksoff_voltage; 2980 uint8_t reserved; 2981 uint32_t dispclk2gfxclk_a; 2982 uint32_t dispclk2gfxclk_b; 2983 uint32_t dispclk2gfxclk_c; 2984 uint32_t pixclk2gfxclk_a; 2985 uint32_t pixclk2gfxclk_b; 2986 uint32_t pixclk2gfxclk_c; 2987 uint32_t dcefclk2gfxclk_a; 2988 uint32_t dcefclk2gfxclk_b; 2989 uint32_t dcefclk2gfxclk_c; 2990 uint32_t phyclk2gfxclk_a; 2991 uint32_t phyclk2gfxclk_b; 2992 uint32_t phyclk2gfxclk_c; 2993 uint32_t acg_gb_vdroop_table_a0; 2994 uint32_t acg_gb_vdroop_table_a1; 2995 uint32_t acg_gb_vdroop_table_a2; 2996 uint32_t acg_avfsgb_fuse_table_m1; 2997 uint32_t acg_avfsgb_fuse_table_m2; 2998 uint32_t acg_avfsgb_fuse_table_b; 2999 uint8_t enable_acg_gb_vdroop_table; 3000 uint8_t enable_acg_gb_fuse_table; 3001 uint32_t acg_dispclk2gfxclk_a; 3002 uint32_t acg_dispclk2gfxclk_b; 3003 uint32_t acg_dispclk2gfxclk_c; 3004 uint32_t acg_pixclk2gfxclk_a; 3005 uint32_t acg_pixclk2gfxclk_b; 3006 uint32_t acg_pixclk2gfxclk_c; 3007 uint32_t acg_dcefclk2gfxclk_a; 3008 uint32_t acg_dcefclk2gfxclk_b; 3009 uint32_t acg_dcefclk2gfxclk_c; 3010 uint32_t acg_phyclk2gfxclk_a; 3011 uint32_t acg_phyclk2gfxclk_b; 3012 uint32_t acg_phyclk2gfxclk_c; 3013 }; 3014 3015 /* 3016 *************************************************************************** 3017 Data Table multimedia_info structure 3018 *************************************************************************** 3019 */ 3020 struct atom_multimedia_info_v2_1 3021 { 3022 struct atom_common_table_header table_header; 3023 uint8_t uvdip_min_ver; 3024 uint8_t uvdip_max_ver; 3025 uint8_t vceip_min_ver; 3026 uint8_t vceip_max_ver; 3027 uint16_t uvd_enc_max_input_width_pixels; 3028 uint16_t uvd_enc_max_input_height_pixels; 3029 uint16_t vce_enc_max_input_width_pixels; 3030 uint16_t vce_enc_max_input_height_pixels; 3031 uint32_t uvd_enc_max_bandwidth; // 16x16 pixels/sec, codec independent 3032 uint32_t vce_enc_max_bandwidth; // 16x16 pixels/sec, codec independent 3033 }; 3034 3035 3036 /* 3037 *************************************************************************** 3038 Data Table umc_info structure 3039 *************************************************************************** 3040 */ 3041 struct atom_umc_info_v3_1 3042 { 3043 struct atom_common_table_header table_header; 3044 uint32_t ucode_version; 3045 uint32_t ucode_rom_startaddr; 3046 uint32_t ucode_length; 3047 uint16_t umc_reg_init_offset; 3048 uint16_t customer_ucode_name_offset; 3049 uint16_t mclk_ss_percentage; 3050 uint16_t mclk_ss_rate_10hz; 3051 uint8_t umcip_min_ver; 3052 uint8_t umcip_max_ver; 3053 uint8_t vram_type; //enum of atom_dgpu_vram_type 3054 uint8_t umc_config; 3055 uint32_t mem_refclk_10khz; 3056 }; 3057 3058 // umc_info.umc_config 3059 enum atom_umc_config_def { 3060 UMC_CONFIG__ENABLE_1KB_INTERLEAVE_MODE = 0x00000001, 3061 UMC_CONFIG__DEFAULT_MEM_ECC_ENABLE = 0x00000002, 3062 UMC_CONFIG__ENABLE_HBM_LANE_REPAIR = 0x00000004, 3063 UMC_CONFIG__ENABLE_BANK_HARVESTING = 0x00000008, 3064 UMC_CONFIG__ENABLE_PHY_REINIT = 0x00000010, 3065 UMC_CONFIG__DISABLE_UCODE_CHKSTATUS = 0x00000020, 3066 }; 3067 3068 struct atom_umc_info_v3_2 3069 { 3070 struct atom_common_table_header table_header; 3071 uint32_t ucode_version; 3072 uint32_t ucode_rom_startaddr; 3073 uint32_t ucode_length; 3074 uint16_t umc_reg_init_offset; 3075 uint16_t customer_ucode_name_offset; 3076 uint16_t mclk_ss_percentage; 3077 uint16_t mclk_ss_rate_10hz; 3078 uint8_t umcip_min_ver; 3079 uint8_t umcip_max_ver; 3080 uint8_t vram_type; //enum of atom_dgpu_vram_type 3081 uint8_t umc_config; 3082 uint32_t mem_refclk_10khz; 3083 uint32_t pstate_uclk_10khz[4]; 3084 uint16_t umcgoldenoffset; 3085 uint16_t densitygoldenoffset; 3086 }; 3087 3088 struct atom_umc_info_v3_3 3089 { 3090 struct atom_common_table_header table_header; 3091 uint32_t ucode_reserved; 3092 uint32_t ucode_rom_startaddr; 3093 uint32_t ucode_length; 3094 uint16_t umc_reg_init_offset; 3095 uint16_t customer_ucode_name_offset; 3096 uint16_t mclk_ss_percentage; 3097 uint16_t mclk_ss_rate_10hz; 3098 uint8_t umcip_min_ver; 3099 uint8_t umcip_max_ver; 3100 uint8_t vram_type; //enum of atom_dgpu_vram_type 3101 uint8_t umc_config; 3102 uint32_t mem_refclk_10khz; 3103 uint32_t pstate_uclk_10khz[4]; 3104 uint16_t umcgoldenoffset; 3105 uint16_t densitygoldenoffset; 3106 uint32_t umc_config1; 3107 uint32_t bist_data_startaddr; 3108 uint32_t reserved[2]; 3109 }; 3110 3111 enum atom_umc_config1_def { 3112 UMC_CONFIG1__ENABLE_PSTATE_PHASE_STORE_TRAIN = 0x00000001, 3113 UMC_CONFIG1__ENABLE_AUTO_FRAMING = 0x00000002, 3114 UMC_CONFIG1__ENABLE_RESTORE_BIST_DATA = 0x00000004, 3115 UMC_CONFIG1__DISABLE_STROBE_MODE = 0x00000008, 3116 UMC_CONFIG1__DEBUG_DATA_PARITY_EN = 0x00000010, 3117 UMC_CONFIG1__ENABLE_ECC_CAPABLE = 0x00010000, 3118 }; 3119 3120 /* 3121 *************************************************************************** 3122 Data Table vram_info structure 3123 *************************************************************************** 3124 */ 3125 struct atom_vram_module_v9 { 3126 // Design Specific Values 3127 uint32_t memory_size; // Total memory size in unit of MB for CONFIG_MEMSIZE zeros 3128 uint32_t channel_enable; // bit vector, each bit indicate specific channel enable or not 3129 uint32_t max_mem_clk; // max memory clock of this memory in unit of 10kHz, =0 means it is not defined 3130 uint16_t reserved[3]; 3131 uint16_t mem_voltage; // mem_voltage 3132 uint16_t vram_module_size; // Size of atom_vram_module_v9 3133 uint8_t ext_memory_id; // Current memory module ID 3134 uint8_t memory_type; // enum of atom_dgpu_vram_type 3135 uint8_t channel_num; // Number of mem. channels supported in this module 3136 uint8_t channel_width; // CHANNEL_16BIT/CHANNEL_32BIT/CHANNEL_64BIT 3137 uint8_t density; // _8Mx32, _16Mx32, _16Mx16, _32Mx16 3138 uint8_t tunningset_id; // MC phy registers set per. 3139 uint8_t vender_rev_id; // [7:4] Revision, [3:0] Vendor code 3140 uint8_t refreshrate; // [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64ms) 3141 uint8_t hbm_ven_rev_id; // hbm_ven_rev_id 3142 uint8_t vram_rsd2; // reserved 3143 char dram_pnstring[20]; // part number end with '0'. 3144 }; 3145 3146 struct atom_vram_info_header_v2_3 { 3147 struct atom_common_table_header table_header; 3148 uint16_t mem_adjust_tbloffset; // offset of atom_umc_init_reg_block structure for memory vendor specific UMC adjust setting 3149 uint16_t mem_clk_patch_tbloffset; // offset of atom_umc_init_reg_block structure for memory clock specific UMC setting 3150 uint16_t mc_adjust_pertile_tbloffset; // offset of atom_umc_init_reg_block structure for Per Byte Offset Preset Settings 3151 uint16_t mc_phyinit_tbloffset; // offset of atom_umc_init_reg_block structure for MC phy init set 3152 uint16_t dram_data_remap_tbloffset; // reserved for now 3153 uint16_t tmrs_seq_offset; // offset of HBM tmrs 3154 uint16_t post_ucode_init_offset; // offset of atom_umc_init_reg_block structure for MC phy init after MC uCode complete umc init 3155 uint16_t vram_rsd2; 3156 uint8_t vram_module_num; // indicate number of VRAM module 3157 uint8_t umcip_min_ver; 3158 uint8_t umcip_max_ver; 3159 uint8_t mc_phy_tile_num; // indicate the MCD tile number which use in DramDataRemapTbl and usMcAdjustPerTileTblOffset 3160 struct atom_vram_module_v9 vram_module[16]; // just for allocation, real number of blocks is in ucNumOfVRAMModule; 3161 }; 3162 3163 /* 3164 *************************************************************************** 3165 Data Table vram_info v3.0 structure 3166 *************************************************************************** 3167 */ 3168 struct atom_vram_module_v3_0 { 3169 uint8_t density; 3170 uint8_t tunningset_id; 3171 uint8_t ext_memory_id; 3172 uint8_t dram_vendor_id; 3173 uint16_t dram_info_offset; 3174 uint16_t mem_tuning_offset; 3175 uint16_t tmrs_seq_offset; 3176 uint16_t reserved1; 3177 uint32_t dram_size_per_ch; 3178 uint32_t reserved[3]; 3179 char dram_pnstring[40]; 3180 }; 3181 3182 struct atom_vram_info_header_v3_0 { 3183 struct atom_common_table_header table_header; 3184 uint16_t mem_tuning_table_offset; 3185 uint16_t dram_info_table_offset; 3186 uint16_t tmrs_table_offset; 3187 uint16_t mc_init_table_offset; 3188 uint16_t dram_data_remap_table_offset; 3189 uint16_t umc_emuinittable_offset; 3190 uint16_t reserved_sub_table_offset[2]; 3191 uint8_t vram_module_num; 3192 uint8_t umcip_min_ver; 3193 uint8_t umcip_max_ver; 3194 uint8_t mc_phy_tile_num; 3195 uint8_t memory_type; 3196 uint8_t channel_num; 3197 uint8_t channel_width; 3198 uint8_t reserved1; 3199 uint32_t channel_enable; 3200 uint32_t channel1_enable; 3201 uint32_t feature_enable; 3202 uint32_t feature1_enable; 3203 uint32_t hardcode_mem_size; 3204 uint32_t reserved4[4]; 3205 struct atom_vram_module_v3_0 vram_module[8]; 3206 }; 3207 3208 struct atom_umc_register_addr_info{ 3209 uint32_t umc_register_addr:24; 3210 uint32_t umc_reg_type_ind:1; 3211 uint32_t umc_reg_rsvd:7; 3212 }; 3213 3214 //atom_umc_register_addr_info. 3215 enum atom_umc_register_addr_info_flag{ 3216 b3ATOM_UMC_REG_ADD_INFO_INDIRECT_ACCESS =0x01, 3217 }; 3218 3219 union atom_umc_register_addr_info_access 3220 { 3221 struct atom_umc_register_addr_info umc_reg_addr; 3222 uint32_t u32umc_reg_addr; 3223 }; 3224 3225 struct atom_umc_reg_setting_id_config{ 3226 uint32_t memclockrange:24; 3227 uint32_t mem_blk_id:8; 3228 }; 3229 3230 union atom_umc_reg_setting_id_config_access 3231 { 3232 struct atom_umc_reg_setting_id_config umc_id_access; 3233 uint32_t u32umc_id_access; 3234 }; 3235 3236 struct atom_umc_reg_setting_data_block{ 3237 union atom_umc_reg_setting_id_config_access block_id; 3238 uint32_t u32umc_reg_data[1]; 3239 }; 3240 3241 struct atom_umc_init_reg_block{ 3242 uint16_t umc_reg_num; 3243 uint16_t reserved; 3244 union atom_umc_register_addr_info_access umc_reg_list[1]; //for allocation purpose, the real number come from umc_reg_num; 3245 struct atom_umc_reg_setting_data_block umc_reg_setting_list[1]; 3246 }; 3247 3248 struct atom_vram_module_v10 { 3249 // Design Specific Values 3250 uint32_t memory_size; // Total memory size in unit of MB for CONFIG_MEMSIZE zeros 3251 uint32_t channel_enable; // bit vector, each bit indicate specific channel enable or not 3252 uint32_t max_mem_clk; // max memory clock of this memory in unit of 10kHz, =0 means it is not defined 3253 uint16_t reserved[3]; 3254 uint16_t mem_voltage; // mem_voltage 3255 uint16_t vram_module_size; // Size of atom_vram_module_v9 3256 uint8_t ext_memory_id; // Current memory module ID 3257 uint8_t memory_type; // enum of atom_dgpu_vram_type 3258 uint8_t channel_num; // Number of mem. channels supported in this module 3259 uint8_t channel_width; // CHANNEL_16BIT/CHANNEL_32BIT/CHANNEL_64BIT 3260 uint8_t density; // _8Mx32, _16Mx32, _16Mx16, _32Mx16 3261 uint8_t tunningset_id; // MC phy registers set per 3262 uint8_t vender_rev_id; // [7:4] Revision, [3:0] Vendor code 3263 uint8_t refreshrate; // [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64ms) 3264 uint8_t vram_flags; // bit0= bankgroup enable 3265 uint8_t vram_rsd2; // reserved 3266 uint16_t gddr6_mr10; // gddr6 mode register10 value 3267 uint16_t gddr6_mr1; // gddr6 mode register1 value 3268 uint16_t gddr6_mr2; // gddr6 mode register2 value 3269 uint16_t gddr6_mr7; // gddr6 mode register7 value 3270 char dram_pnstring[20]; // part number end with '0' 3271 }; 3272 3273 struct atom_vram_info_header_v2_4 { 3274 struct atom_common_table_header table_header; 3275 uint16_t mem_adjust_tbloffset; // offset of atom_umc_init_reg_block structure for memory vendor specific UMC adjust setting 3276 uint16_t mem_clk_patch_tbloffset; // offset of atom_umc_init_reg_block structure for memory clock specific UMC setting 3277 uint16_t mc_adjust_pertile_tbloffset; // offset of atom_umc_init_reg_block structure for Per Byte Offset Preset Settings 3278 uint16_t mc_phyinit_tbloffset; // offset of atom_umc_init_reg_block structure for MC phy init set 3279 uint16_t dram_data_remap_tbloffset; // reserved for now 3280 uint16_t reserved; // offset of reserved 3281 uint16_t post_ucode_init_offset; // offset of atom_umc_init_reg_block structure for MC phy init after MC uCode complete umc init 3282 uint16_t vram_rsd2; 3283 uint8_t vram_module_num; // indicate number of VRAM module 3284 uint8_t umcip_min_ver; 3285 uint8_t umcip_max_ver; 3286 uint8_t mc_phy_tile_num; // indicate the MCD tile number which use in DramDataRemapTbl and usMcAdjustPerTileTblOffset 3287 struct atom_vram_module_v10 vram_module[16]; // just for allocation, real number of blocks is in ucNumOfVRAMModule; 3288 }; 3289 3290 struct atom_vram_module_v11 { 3291 // Design Specific Values 3292 uint32_t memory_size; // Total memory size in unit of MB for CONFIG_MEMSIZE zeros 3293 uint32_t channel_enable; // bit vector, each bit indicate specific channel enable or not 3294 uint16_t mem_voltage; // mem_voltage 3295 uint16_t vram_module_size; // Size of atom_vram_module_v9 3296 uint8_t ext_memory_id; // Current memory module ID 3297 uint8_t memory_type; // enum of atom_dgpu_vram_type 3298 uint8_t channel_num; // Number of mem. channels supported in this module 3299 uint8_t channel_width; // CHANNEL_16BIT/CHANNEL_32BIT/CHANNEL_64BIT 3300 uint8_t density; // _8Mx32, _16Mx32, _16Mx16, _32Mx16 3301 uint8_t tunningset_id; // MC phy registers set per. 3302 uint16_t reserved[4]; // reserved 3303 uint8_t vender_rev_id; // [7:4] Revision, [3:0] Vendor code 3304 uint8_t refreshrate; // [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64ms) 3305 uint8_t vram_flags; // bit0= bankgroup enable 3306 uint8_t vram_rsd2; // reserved 3307 uint16_t gddr6_mr10; // gddr6 mode register10 value 3308 uint16_t gddr6_mr0; // gddr6 mode register0 value 3309 uint16_t gddr6_mr1; // gddr6 mode register1 value 3310 uint16_t gddr6_mr2; // gddr6 mode register2 value 3311 uint16_t gddr6_mr4; // gddr6 mode register4 value 3312 uint16_t gddr6_mr7; // gddr6 mode register7 value 3313 uint16_t gddr6_mr8; // gddr6 mode register8 value 3314 char dram_pnstring[40]; // part number end with '0'. 3315 }; 3316 3317 struct atom_gddr6_ac_timing_v2_5 { 3318 uint32_t u32umc_id_access; 3319 uint8_t RL; 3320 uint8_t WL; 3321 uint8_t tRAS; 3322 uint8_t tRC; 3323 3324 uint16_t tREFI; 3325 uint8_t tRFC; 3326 uint8_t tRFCpb; 3327 3328 uint8_t tRREFD; 3329 uint8_t tRCDRD; 3330 uint8_t tRCDWR; 3331 uint8_t tRP; 3332 3333 uint8_t tRRDS; 3334 uint8_t tRRDL; 3335 uint8_t tWR; 3336 uint8_t tWTRS; 3337 3338 uint8_t tWTRL; 3339 uint8_t tFAW; 3340 uint8_t tCCDS; 3341 uint8_t tCCDL; 3342 3343 uint8_t tCRCRL; 3344 uint8_t tCRCWL; 3345 uint8_t tCKE; 3346 uint8_t tCKSRE; 3347 3348 uint8_t tCKSRX; 3349 uint8_t tRTPS; 3350 uint8_t tRTPL; 3351 uint8_t tMRD; 3352 3353 uint8_t tMOD; 3354 uint8_t tXS; 3355 uint8_t tXHP; 3356 uint8_t tXSMRS; 3357 3358 uint32_t tXSH; 3359 3360 uint8_t tPD; 3361 uint8_t tXP; 3362 uint8_t tCPDED; 3363 uint8_t tACTPDE; 3364 3365 uint8_t tPREPDE; 3366 uint8_t tREFPDE; 3367 uint8_t tMRSPDEN; 3368 uint8_t tRDSRE; 3369 3370 uint8_t tWRSRE; 3371 uint8_t tPPD; 3372 uint8_t tCCDMW; 3373 uint8_t tWTRTR; 3374 3375 uint8_t tLTLTR; 3376 uint8_t tREFTR; 3377 uint8_t VNDR; 3378 uint8_t reserved[9]; 3379 }; 3380 3381 struct atom_gddr6_bit_byte_remap { 3382 uint32_t dphy_byteremap; //mmUMC_DPHY_ByteRemap 3383 uint32_t dphy_bitremap0; //mmUMC_DPHY_BitRemap0 3384 uint32_t dphy_bitremap1; //mmUMC_DPHY_BitRemap1 3385 uint32_t dphy_bitremap2; //mmUMC_DPHY_BitRemap2 3386 uint32_t aphy_bitremap0; //mmUMC_APHY_BitRemap0 3387 uint32_t aphy_bitremap1; //mmUMC_APHY_BitRemap1 3388 uint32_t phy_dram; //mmUMC_PHY_DRAM 3389 }; 3390 3391 struct atom_gddr6_dram_data_remap { 3392 uint32_t table_size; 3393 uint8_t phyintf_ck_inverted[8]; //UMC_PHY_PHYINTF_CNTL.INV_CK 3394 struct atom_gddr6_bit_byte_remap bit_byte_remap[16]; 3395 }; 3396 3397 struct atom_vram_info_header_v2_5 { 3398 struct atom_common_table_header table_header; 3399 uint16_t mem_adjust_tbloffset; // offset of atom_umc_init_reg_block structure for memory vendor specific UMC adjust settings 3400 uint16_t gddr6_ac_timing_offset; // offset of atom_gddr6_ac_timing_v2_5 structure for memory clock specific UMC settings 3401 uint16_t mc_adjust_pertile_tbloffset; // offset of atom_umc_init_reg_block structure for Per Byte Offset Preset Settings 3402 uint16_t mc_phyinit_tbloffset; // offset of atom_umc_init_reg_block structure for MC phy init set 3403 uint16_t dram_data_remap_tbloffset; // offset of atom_gddr6_dram_data_remap array to indicate DRAM data lane to GPU mapping 3404 uint16_t reserved; // offset of reserved 3405 uint16_t post_ucode_init_offset; // offset of atom_umc_init_reg_block structure for MC phy init after MC uCode complete umc init 3406 uint16_t strobe_mode_patch_tbloffset; // offset of atom_umc_init_reg_block structure for Strobe Mode memory clock specific UMC settings 3407 uint8_t vram_module_num; // indicate number of VRAM module 3408 uint8_t umcip_min_ver; 3409 uint8_t umcip_max_ver; 3410 uint8_t mc_phy_tile_num; // indicate the MCD tile number which use in DramDataRemapTbl and usMcAdjustPerTileTblOffset 3411 struct atom_vram_module_v11 vram_module[16]; // just for allocation, real number of blocks is in ucNumOfVRAMModule; 3412 }; 3413 3414 struct atom_vram_info_header_v2_6 { 3415 struct atom_common_table_header table_header; 3416 uint16_t mem_adjust_tbloffset; 3417 uint16_t mem_clk_patch_tbloffset; 3418 uint16_t mc_adjust_pertile_tbloffset; 3419 uint16_t mc_phyinit_tbloffset; 3420 uint16_t dram_data_remap_tbloffset; 3421 uint16_t tmrs_seq_offset; 3422 uint16_t post_ucode_init_offset; 3423 uint16_t vram_rsd2; 3424 uint8_t vram_module_num; 3425 uint8_t umcip_min_ver; 3426 uint8_t umcip_max_ver; 3427 uint8_t mc_phy_tile_num; 3428 struct atom_vram_module_v9 vram_module[16]; 3429 }; 3430 /* 3431 *************************************************************************** 3432 Data Table voltageobject_info structure 3433 *************************************************************************** 3434 */ 3435 struct atom_i2c_data_entry 3436 { 3437 uint16_t i2c_reg_index; // i2c register address, can be up to 16bit 3438 uint16_t i2c_reg_data; // i2c register data, can be up to 16bit 3439 }; 3440 3441 struct atom_voltage_object_header_v4{ 3442 uint8_t voltage_type; //enum atom_voltage_type 3443 uint8_t voltage_mode; //enum atom_voltage_object_mode 3444 uint16_t object_size; //Size of Object 3445 }; 3446 3447 // atom_voltage_object_header_v4.voltage_mode 3448 enum atom_voltage_object_mode 3449 { 3450 VOLTAGE_OBJ_GPIO_LUT = 0, //VOLTAGE and GPIO Lookup table ->atom_gpio_voltage_object_v4 3451 VOLTAGE_OBJ_VR_I2C_INIT_SEQ = 3, //VOLTAGE REGULATOR INIT sequece through I2C -> atom_i2c_voltage_object_v4 3452 VOLTAGE_OBJ_PHASE_LUT = 4, //Set Vregulator Phase lookup table ->atom_gpio_voltage_object_v4 3453 VOLTAGE_OBJ_SVID2 = 7, //Indicate voltage control by SVID2 ->atom_svid2_voltage_object_v4 3454 VOLTAGE_OBJ_EVV = 8, 3455 VOLTAGE_OBJ_MERGED_POWER = 9, 3456 }; 3457 3458 struct atom_i2c_voltage_object_v4 3459 { 3460 struct atom_voltage_object_header_v4 header; // voltage mode = VOLTAGE_OBJ_VR_I2C_INIT_SEQ 3461 uint8_t regulator_id; //Indicate Voltage Regulator Id 3462 uint8_t i2c_id; 3463 uint8_t i2c_slave_addr; 3464 uint8_t i2c_control_offset; 3465 uint8_t i2c_flag; // Bit0: 0 - One byte data; 1 - Two byte data 3466 uint8_t i2c_speed; // =0, use default i2c speed, otherwise use it in unit of kHz. 3467 uint8_t reserved[2]; 3468 struct atom_i2c_data_entry i2cdatalut[1]; // end with 0xff 3469 }; 3470 3471 // ATOM_I2C_VOLTAGE_OBJECT_V3.ucVoltageControlFlag 3472 enum atom_i2c_voltage_control_flag 3473 { 3474 VOLTAGE_DATA_ONE_BYTE = 0, 3475 VOLTAGE_DATA_TWO_BYTE = 1, 3476 }; 3477 3478 3479 struct atom_voltage_gpio_map_lut 3480 { 3481 uint32_t voltage_gpio_reg_val; // The Voltage ID which is used to program GPIO register 3482 uint16_t voltage_level_mv; // The corresponding Voltage Value, in mV 3483 }; 3484 3485 struct atom_gpio_voltage_object_v4 3486 { 3487 struct atom_voltage_object_header_v4 header; // voltage mode = VOLTAGE_OBJ_GPIO_LUT or VOLTAGE_OBJ_PHASE_LUT 3488 uint8_t gpio_control_id; // default is 0 which indicate control through CG VID mode 3489 uint8_t gpio_entry_num; // indiate the entry numbers of Votlage/Gpio value Look up table 3490 uint8_t phase_delay_us; // phase delay in unit of micro second 3491 uint8_t reserved; 3492 uint32_t gpio_mask_val; // GPIO Mask value 3493 struct atom_voltage_gpio_map_lut voltage_gpio_lut[1]; 3494 }; 3495 3496 struct atom_svid2_voltage_object_v4 3497 { 3498 struct atom_voltage_object_header_v4 header; // voltage mode = VOLTAGE_OBJ_SVID2 3499 uint8_t loadline_psi1; // bit4:0= loadline setting ( Core Loadline trim and offset trim ), bit5=0:PSI1_L disable =1: PSI1_L enable 3500 uint8_t psi0_l_vid_thresd; // VR PSI0_L VID threshold 3501 uint8_t psi0_enable; // 3502 uint8_t maxvstep; 3503 uint8_t telemetry_offset; 3504 uint8_t telemetry_gain; 3505 uint16_t reserved1; 3506 }; 3507 3508 struct atom_merged_voltage_object_v4 3509 { 3510 struct atom_voltage_object_header_v4 header; // voltage mode = VOLTAGE_OBJ_MERGED_POWER 3511 uint8_t merged_powerrail_type; //enum atom_voltage_type 3512 uint8_t reserved[3]; 3513 }; 3514 3515 union atom_voltage_object_v4{ 3516 struct atom_gpio_voltage_object_v4 gpio_voltage_obj; 3517 struct atom_i2c_voltage_object_v4 i2c_voltage_obj; 3518 struct atom_svid2_voltage_object_v4 svid2_voltage_obj; 3519 struct atom_merged_voltage_object_v4 merged_voltage_obj; 3520 }; 3521 3522 struct atom_voltage_objects_info_v4_1 3523 { 3524 struct atom_common_table_header table_header; 3525 union atom_voltage_object_v4 voltage_object[1]; //Info for Voltage control 3526 }; 3527 3528 3529 /* 3530 *************************************************************************** 3531 All Command Function structure definition 3532 *************************************************************************** 3533 */ 3534 3535 /* 3536 *************************************************************************** 3537 Structures used by asic_init 3538 *************************************************************************** 3539 */ 3540 3541 struct asic_init_engine_parameters 3542 { 3543 uint32_t sclkfreqin10khz:24; 3544 uint32_t engineflag:8; /* enum atom_asic_init_engine_flag */ 3545 }; 3546 3547 struct asic_init_mem_parameters 3548 { 3549 uint32_t mclkfreqin10khz:24; 3550 uint32_t memflag:8; /* enum atom_asic_init_mem_flag */ 3551 }; 3552 3553 struct asic_init_parameters_v2_1 3554 { 3555 struct asic_init_engine_parameters engineparam; 3556 struct asic_init_mem_parameters memparam; 3557 }; 3558 3559 struct asic_init_ps_allocation_v2_1 3560 { 3561 struct asic_init_parameters_v2_1 param; 3562 uint32_t reserved[16]; 3563 }; 3564 3565 3566 enum atom_asic_init_engine_flag 3567 { 3568 b3NORMAL_ENGINE_INIT = 0, 3569 b3SRIOV_SKIP_ASIC_INIT = 0x02, 3570 b3SRIOV_LOAD_UCODE = 0x40, 3571 }; 3572 3573 enum atom_asic_init_mem_flag 3574 { 3575 b3NORMAL_MEM_INIT = 0, 3576 b3DRAM_SELF_REFRESH_EXIT =0x20, 3577 }; 3578 3579 /* 3580 *************************************************************************** 3581 Structures used by setengineclock 3582 *************************************************************************** 3583 */ 3584 3585 struct set_engine_clock_parameters_v2_1 3586 { 3587 uint32_t sclkfreqin10khz:24; 3588 uint32_t sclkflag:8; /* enum atom_set_engine_mem_clock_flag, */ 3589 uint32_t reserved[10]; 3590 }; 3591 3592 struct set_engine_clock_ps_allocation_v2_1 3593 { 3594 struct set_engine_clock_parameters_v2_1 clockinfo; 3595 uint32_t reserved[10]; 3596 }; 3597 3598 3599 enum atom_set_engine_mem_clock_flag 3600 { 3601 b3NORMAL_CHANGE_CLOCK = 0, 3602 b3FIRST_TIME_CHANGE_CLOCK = 0x08, 3603 b3STORE_DPM_TRAINGING = 0x40, //Applicable to memory clock change,when set, it store specific DPM mode training result 3604 }; 3605 3606 /* 3607 *************************************************************************** 3608 Structures used by getengineclock 3609 *************************************************************************** 3610 */ 3611 struct get_engine_clock_parameter 3612 { 3613 uint32_t sclk_10khz; // current engine speed in 10KHz unit 3614 uint32_t reserved; 3615 }; 3616 3617 /* 3618 *************************************************************************** 3619 Structures used by setmemoryclock 3620 *************************************************************************** 3621 */ 3622 struct set_memory_clock_parameters_v2_1 3623 { 3624 uint32_t mclkfreqin10khz:24; 3625 uint32_t mclkflag:8; /* enum atom_set_engine_mem_clock_flag, */ 3626 uint32_t reserved[10]; 3627 }; 3628 3629 struct set_memory_clock_ps_allocation_v2_1 3630 { 3631 struct set_memory_clock_parameters_v2_1 clockinfo; 3632 uint32_t reserved[10]; 3633 }; 3634 3635 3636 /* 3637 *************************************************************************** 3638 Structures used by getmemoryclock 3639 *************************************************************************** 3640 */ 3641 struct get_memory_clock_parameter 3642 { 3643 uint32_t mclk_10khz; // current engine speed in 10KHz unit 3644 uint32_t reserved; 3645 }; 3646 3647 3648 3649 /* 3650 *************************************************************************** 3651 Structures used by setvoltage 3652 *************************************************************************** 3653 */ 3654 3655 struct set_voltage_parameters_v1_4 3656 { 3657 uint8_t voltagetype; /* enum atom_voltage_type */ 3658 uint8_t command; /* Indicate action: Set voltage level, enum atom_set_voltage_command */ 3659 uint16_t vlevel_mv; /* real voltage level in unit of mv or Voltage Phase (0, 1, 2, .. ) */ 3660 }; 3661 3662 //set_voltage_parameters_v2_1.voltagemode 3663 enum atom_set_voltage_command{ 3664 ATOM_SET_VOLTAGE = 0, 3665 ATOM_INIT_VOLTAGE_REGULATOR = 3, 3666 ATOM_SET_VOLTAGE_PHASE = 4, 3667 ATOM_GET_LEAKAGE_ID = 8, 3668 }; 3669 3670 struct set_voltage_ps_allocation_v1_4 3671 { 3672 struct set_voltage_parameters_v1_4 setvoltageparam; 3673 uint32_t reserved[10]; 3674 }; 3675 3676 3677 /* 3678 *************************************************************************** 3679 Structures used by computegpuclockparam 3680 *************************************************************************** 3681 */ 3682 3683 //ATOM_COMPUTE_CLOCK_FREQ.ulComputeClockFlag 3684 enum atom_gpu_clock_type 3685 { 3686 COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK =0x00, 3687 COMPUTE_GPUCLK_INPUT_FLAG_GFXCLK =0x01, 3688 COMPUTE_GPUCLK_INPUT_FLAG_UCLK =0x02, 3689 }; 3690 3691 struct compute_gpu_clock_input_parameter_v1_8 3692 { 3693 uint32_t gpuclock_10khz:24; //Input= target clock, output = actual clock 3694 uint32_t gpu_clock_type:8; //Input indicate clock type: enum atom_gpu_clock_type 3695 uint32_t reserved[5]; 3696 }; 3697 3698 3699 struct compute_gpu_clock_output_parameter_v1_8 3700 { 3701 uint32_t gpuclock_10khz:24; //Input= target clock, output = actual clock 3702 uint32_t dfs_did:8; //return parameter: DFS divider which is used to program to register directly 3703 uint32_t pll_fb_mult; //Feedback Multiplier, bit 8:0 int, bit 15:12 post_div, bit 31:16 frac 3704 uint32_t pll_ss_fbsmult; // Spread FB Mult: bit 8:0 int, bit 31:16 frac 3705 uint16_t pll_ss_slew_frac; 3706 uint8_t pll_ss_enable; 3707 uint8_t reserved; 3708 uint32_t reserved1[2]; 3709 }; 3710 3711 3712 3713 /* 3714 *************************************************************************** 3715 Structures used by ReadEfuseValue 3716 *************************************************************************** 3717 */ 3718 3719 struct read_efuse_input_parameters_v3_1 3720 { 3721 uint16_t efuse_start_index; 3722 uint8_t reserved; 3723 uint8_t bitslen; 3724 }; 3725 3726 // ReadEfuseValue input/output parameter 3727 union read_efuse_value_parameters_v3_1 3728 { 3729 struct read_efuse_input_parameters_v3_1 efuse_info; 3730 uint32_t efusevalue; 3731 }; 3732 3733 3734 /* 3735 *************************************************************************** 3736 Structures used by getsmuclockinfo 3737 *************************************************************************** 3738 */ 3739 struct atom_get_smu_clock_info_parameters_v3_1 3740 { 3741 uint8_t syspll_id; // 0= syspll0, 1=syspll1, 2=syspll2 3742 uint8_t clk_id; // atom_smu9_syspll0_clock_id (only valid when command == GET_SMU_CLOCK_INFO_V3_1_GET_CLOCK_FREQ ) 3743 uint8_t command; // enum of atom_get_smu_clock_info_command 3744 uint8_t dfsdid; // =0: get DFS DID from register, >0, give DFS divider, (only valid when command == GET_SMU_CLOCK_INFO_V3_1_GET_CLOCK_FREQ ) 3745 }; 3746 3747 enum atom_get_smu_clock_info_command 3748 { 3749 GET_SMU_CLOCK_INFO_V3_1_GET_CLOCK_FREQ = 0, 3750 GET_SMU_CLOCK_INFO_V3_1_GET_PLLVCO_FREQ = 1, 3751 GET_SMU_CLOCK_INFO_V3_1_GET_PLLREFCLK_FREQ = 2, 3752 }; 3753 3754 enum atom_smu9_syspll0_clock_id 3755 { 3756 SMU9_SYSPLL0_SMNCLK_ID = 0, // SMNCLK 3757 SMU9_SYSPLL0_SOCCLK_ID = 1, // SOCCLK (FCLK) 3758 SMU9_SYSPLL0_MP0CLK_ID = 2, // MP0CLK 3759 SMU9_SYSPLL0_MP1CLK_ID = 3, // MP1CLK 3760 SMU9_SYSPLL0_LCLK_ID = 4, // LCLK 3761 SMU9_SYSPLL0_DCLK_ID = 5, // DCLK 3762 SMU9_SYSPLL0_VCLK_ID = 6, // VCLK 3763 SMU9_SYSPLL0_ECLK_ID = 7, // ECLK 3764 SMU9_SYSPLL0_DCEFCLK_ID = 8, // DCEFCLK 3765 SMU9_SYSPLL0_DPREFCLK_ID = 10, // DPREFCLK 3766 SMU9_SYSPLL0_DISPCLK_ID = 11, // DISPCLK 3767 }; 3768 3769 enum atom_smu11_syspll_id { 3770 SMU11_SYSPLL0_ID = 0, 3771 SMU11_SYSPLL1_0_ID = 1, 3772 SMU11_SYSPLL1_1_ID = 2, 3773 SMU11_SYSPLL1_2_ID = 3, 3774 SMU11_SYSPLL2_ID = 4, 3775 SMU11_SYSPLL3_0_ID = 5, 3776 SMU11_SYSPLL3_1_ID = 6, 3777 }; 3778 3779 enum atom_smu11_syspll0_clock_id { 3780 SMU11_SYSPLL0_ECLK_ID = 0, // ECLK 3781 SMU11_SYSPLL0_SOCCLK_ID = 1, // SOCCLK 3782 SMU11_SYSPLL0_MP0CLK_ID = 2, // MP0CLK 3783 SMU11_SYSPLL0_DCLK_ID = 3, // DCLK 3784 SMU11_SYSPLL0_VCLK_ID = 4, // VCLK 3785 SMU11_SYSPLL0_DCEFCLK_ID = 5, // DCEFCLK 3786 }; 3787 3788 enum atom_smu11_syspll1_0_clock_id { 3789 SMU11_SYSPLL1_0_UCLKA_ID = 0, // UCLK_a 3790 }; 3791 3792 enum atom_smu11_syspll1_1_clock_id { 3793 SMU11_SYSPLL1_0_UCLKB_ID = 0, // UCLK_b 3794 }; 3795 3796 enum atom_smu11_syspll1_2_clock_id { 3797 SMU11_SYSPLL1_0_FCLK_ID = 0, // FCLK 3798 }; 3799 3800 enum atom_smu11_syspll2_clock_id { 3801 SMU11_SYSPLL2_GFXCLK_ID = 0, // GFXCLK 3802 }; 3803 3804 enum atom_smu11_syspll3_0_clock_id { 3805 SMU11_SYSPLL3_0_WAFCLK_ID = 0, // WAFCLK 3806 SMU11_SYSPLL3_0_DISPCLK_ID = 1, // DISPCLK 3807 SMU11_SYSPLL3_0_DPREFCLK_ID = 2, // DPREFCLK 3808 }; 3809 3810 enum atom_smu11_syspll3_1_clock_id { 3811 SMU11_SYSPLL3_1_MP1CLK_ID = 0, // MP1CLK 3812 SMU11_SYSPLL3_1_SMNCLK_ID = 1, // SMNCLK 3813 SMU11_SYSPLL3_1_LCLK_ID = 2, // LCLK 3814 }; 3815 3816 enum atom_smu12_syspll_id { 3817 SMU12_SYSPLL0_ID = 0, 3818 SMU12_SYSPLL1_ID = 1, 3819 SMU12_SYSPLL2_ID = 2, 3820 SMU12_SYSPLL3_0_ID = 3, 3821 SMU12_SYSPLL3_1_ID = 4, 3822 }; 3823 3824 enum atom_smu12_syspll0_clock_id { 3825 SMU12_SYSPLL0_SMNCLK_ID = 0, // SOCCLK 3826 SMU12_SYSPLL0_SOCCLK_ID = 1, // SOCCLK 3827 SMU12_SYSPLL0_MP0CLK_ID = 2, // MP0CLK 3828 SMU12_SYSPLL0_MP1CLK_ID = 3, // MP1CLK 3829 SMU12_SYSPLL0_MP2CLK_ID = 4, // MP2CLK 3830 SMU12_SYSPLL0_VCLK_ID = 5, // VCLK 3831 SMU12_SYSPLL0_LCLK_ID = 6, // LCLK 3832 SMU12_SYSPLL0_DCLK_ID = 7, // DCLK 3833 SMU12_SYSPLL0_ACLK_ID = 8, // ACLK 3834 SMU12_SYSPLL0_ISPCLK_ID = 9, // ISPCLK 3835 SMU12_SYSPLL0_SHUBCLK_ID = 10, // SHUBCLK 3836 }; 3837 3838 enum atom_smu12_syspll1_clock_id { 3839 SMU12_SYSPLL1_DISPCLK_ID = 0, // DISPCLK 3840 SMU12_SYSPLL1_DPPCLK_ID = 1, // DPPCLK 3841 SMU12_SYSPLL1_DPREFCLK_ID = 2, // DPREFCLK 3842 SMU12_SYSPLL1_DCFCLK_ID = 3, // DCFCLK 3843 }; 3844 3845 enum atom_smu12_syspll2_clock_id { 3846 SMU12_SYSPLL2_Pre_GFXCLK_ID = 0, // Pre_GFXCLK 3847 }; 3848 3849 enum atom_smu12_syspll3_0_clock_id { 3850 SMU12_SYSPLL3_0_FCLK_ID = 0, // FCLK 3851 }; 3852 3853 enum atom_smu12_syspll3_1_clock_id { 3854 SMU12_SYSPLL3_1_UMCCLK_ID = 0, // UMCCLK 3855 }; 3856 3857 struct atom_get_smu_clock_info_output_parameters_v3_1 3858 { 3859 union { 3860 uint32_t smu_clock_freq_hz; 3861 uint32_t syspllvcofreq_10khz; 3862 uint32_t sysspllrefclk_10khz; 3863 }atom_smu_outputclkfreq; 3864 }; 3865 3866 3867 3868 /* 3869 *************************************************************************** 3870 Structures used by dynamicmemorysettings 3871 *************************************************************************** 3872 */ 3873 3874 enum atom_dynamic_memory_setting_command 3875 { 3876 COMPUTE_MEMORY_PLL_PARAM = 1, 3877 COMPUTE_ENGINE_PLL_PARAM = 2, 3878 ADJUST_MC_SETTING_PARAM = 3, 3879 }; 3880 3881 /* when command = COMPUTE_MEMORY_PLL_PARAM or ADJUST_MC_SETTING_PARAM */ 3882 struct dynamic_mclk_settings_parameters_v2_1 3883 { 3884 uint32_t mclk_10khz:24; //Input= target mclk 3885 uint32_t command:8; //command enum of atom_dynamic_memory_setting_command 3886 uint32_t reserved; 3887 }; 3888 3889 /* when command = COMPUTE_ENGINE_PLL_PARAM */ 3890 struct dynamic_sclk_settings_parameters_v2_1 3891 { 3892 uint32_t sclk_10khz:24; //Input= target mclk 3893 uint32_t command:8; //command enum of atom_dynamic_memory_setting_command 3894 uint32_t mclk_10khz; 3895 uint32_t reserved; 3896 }; 3897 3898 union dynamic_memory_settings_parameters_v2_1 3899 { 3900 struct dynamic_mclk_settings_parameters_v2_1 mclk_setting; 3901 struct dynamic_sclk_settings_parameters_v2_1 sclk_setting; 3902 }; 3903 3904 3905 3906 /* 3907 *************************************************************************** 3908 Structures used by memorytraining 3909 *************************************************************************** 3910 */ 3911 3912 enum atom_umc6_0_ucode_function_call_enum_id 3913 { 3914 UMC60_UCODE_FUNC_ID_REINIT = 0, 3915 UMC60_UCODE_FUNC_ID_ENTER_SELFREFRESH = 1, 3916 UMC60_UCODE_FUNC_ID_EXIT_SELFREFRESH = 2, 3917 }; 3918 3919 3920 struct memory_training_parameters_v2_1 3921 { 3922 uint8_t ucode_func_id; 3923 uint8_t ucode_reserved[3]; 3924 uint32_t reserved[5]; 3925 }; 3926 3927 3928 /* 3929 *************************************************************************** 3930 Structures used by setpixelclock 3931 *************************************************************************** 3932 */ 3933 3934 struct set_pixel_clock_parameter_v1_7 3935 { 3936 uint32_t pixclk_100hz; // target the pixel clock to drive the CRTC timing in unit of 100Hz. 3937 3938 uint8_t pll_id; // ATOM_PHY_PLL0/ATOM_PHY_PLL1/ATOM_PPLL0 3939 uint8_t encoderobjid; // ASIC encoder id defined in objectId.h, 3940 // indicate which graphic encoder will be used. 3941 uint8_t encoder_mode; // Encoder mode: 3942 uint8_t miscinfo; // enum atom_set_pixel_clock_v1_7_misc_info 3943 uint8_t crtc_id; // enum of atom_crtc_def 3944 uint8_t deep_color_ratio; // HDMI panel bit depth: enum atom_set_pixel_clock_v1_7_deepcolor_ratio 3945 uint8_t reserved1[2]; 3946 uint32_t reserved2; 3947 }; 3948 3949 //ucMiscInfo 3950 enum atom_set_pixel_clock_v1_7_misc_info 3951 { 3952 PIXEL_CLOCK_V7_MISC_FORCE_PROG_PPLL = 0x01, 3953 PIXEL_CLOCK_V7_MISC_PROG_PHYPLL = 0x02, 3954 PIXEL_CLOCK_V7_MISC_YUV420_MODE = 0x04, 3955 PIXEL_CLOCK_V7_MISC_DVI_DUALLINK_EN = 0x08, 3956 PIXEL_CLOCK_V7_MISC_REF_DIV_SRC = 0x30, 3957 PIXEL_CLOCK_V7_MISC_REF_DIV_SRC_XTALIN = 0x00, 3958 PIXEL_CLOCK_V7_MISC_REF_DIV_SRC_PCIE = 0x10, 3959 PIXEL_CLOCK_V7_MISC_REF_DIV_SRC_GENLK = 0x20, 3960 PIXEL_CLOCK_V7_MISC_REF_DIV_SRC_REFPAD = 0x30, 3961 PIXEL_CLOCK_V7_MISC_ATOMIC_UPDATE = 0x40, 3962 PIXEL_CLOCK_V7_MISC_FORCE_SS_DIS = 0x80, 3963 }; 3964 3965 /* deep_color_ratio */ 3966 enum atom_set_pixel_clock_v1_7_deepcolor_ratio 3967 { 3968 PIXEL_CLOCK_V7_DEEPCOLOR_RATIO_DIS = 0x00, //00 - DCCG_DEEP_COLOR_DTO_DISABLE: Disable Deep Color DTO 3969 PIXEL_CLOCK_V7_DEEPCOLOR_RATIO_5_4 = 0x01, //01 - DCCG_DEEP_COLOR_DTO_5_4_RATIO: Set Deep Color DTO to 5:4 3970 PIXEL_CLOCK_V7_DEEPCOLOR_RATIO_3_2 = 0x02, //02 - DCCG_DEEP_COLOR_DTO_3_2_RATIO: Set Deep Color DTO to 3:2 3971 PIXEL_CLOCK_V7_DEEPCOLOR_RATIO_2_1 = 0x03, //03 - DCCG_DEEP_COLOR_DTO_2_1_RATIO: Set Deep Color DTO to 2:1 3972 }; 3973 3974 /* 3975 *************************************************************************** 3976 Structures used by setdceclock 3977 *************************************************************************** 3978 */ 3979 3980 // SetDCEClock input parameter for DCE11.2( ELM and BF ) and above 3981 struct set_dce_clock_parameters_v2_1 3982 { 3983 uint32_t dceclk_10khz; // target DCE frequency in unit of 10KHZ, return real DISPCLK/DPREFCLK frequency. 3984 uint8_t dceclktype; // =0: DISPCLK =1: DPREFCLK =2: PIXCLK 3985 uint8_t dceclksrc; // ATOM_PLL0 or ATOM_GCK_DFS or ATOM_FCH_CLK or ATOM_COMBOPHY_PLLx 3986 uint8_t dceclkflag; // Bit [1:0] = PPLL ref clock source ( when ucDCEClkSrc= ATOM_PPLL0 ) 3987 uint8_t crtc_id; // ucDisp Pipe Id, ATOM_CRTC0/1/2/..., use only when ucDCEClkType = PIXCLK 3988 }; 3989 3990 //ucDCEClkType 3991 enum atom_set_dce_clock_clock_type 3992 { 3993 DCE_CLOCK_TYPE_DISPCLK = 0, 3994 DCE_CLOCK_TYPE_DPREFCLK = 1, 3995 DCE_CLOCK_TYPE_PIXELCLK = 2, // used by VBIOS internally, called by SetPixelClock 3996 }; 3997 3998 //ucDCEClkFlag when ucDCEClkType == DPREFCLK 3999 enum atom_set_dce_clock_dprefclk_flag 4000 { 4001 DCE_CLOCK_FLAG_PLL_REFCLK_SRC_MASK = 0x03, 4002 DCE_CLOCK_FLAG_PLL_REFCLK_SRC_GENERICA = 0x00, 4003 DCE_CLOCK_FLAG_PLL_REFCLK_SRC_GENLK = 0x01, 4004 DCE_CLOCK_FLAG_PLL_REFCLK_SRC_PCIE = 0x02, 4005 DCE_CLOCK_FLAG_PLL_REFCLK_SRC_XTALIN = 0x03, 4006 }; 4007 4008 //ucDCEClkFlag when ucDCEClkType == PIXCLK 4009 enum atom_set_dce_clock_pixclk_flag 4010 { 4011 DCE_CLOCK_FLAG_PCLK_DEEPCOLOR_RATIO_MASK = 0x03, 4012 DCE_CLOCK_FLAG_PCLK_DEEPCOLOR_RATIO_DIS = 0x00, //00 - DCCG_DEEP_COLOR_DTO_DISABLE: Disable Deep Color DTO 4013 DCE_CLOCK_FLAG_PCLK_DEEPCOLOR_RATIO_5_4 = 0x01, //01 - DCCG_DEEP_COLOR_DTO_5_4_RATIO: Set Deep Color DTO to 5:4 4014 DCE_CLOCK_FLAG_PCLK_DEEPCOLOR_RATIO_3_2 = 0x02, //02 - DCCG_DEEP_COLOR_DTO_3_2_RATIO: Set Deep Color DTO to 3:2 4015 DCE_CLOCK_FLAG_PCLK_DEEPCOLOR_RATIO_2_1 = 0x03, //03 - DCCG_DEEP_COLOR_DTO_2_1_RATIO: Set Deep Color DTO to 2:1 4016 DCE_CLOCK_FLAG_PIXCLK_YUV420_MODE = 0x04, 4017 }; 4018 4019 struct set_dce_clock_ps_allocation_v2_1 4020 { 4021 struct set_dce_clock_parameters_v2_1 param; 4022 uint32_t ulReserved[2]; 4023 }; 4024 4025 4026 /****************************************************************************/ 4027 // Structures used by BlankCRTC 4028 /****************************************************************************/ 4029 struct blank_crtc_parameters 4030 { 4031 uint8_t crtc_id; // enum atom_crtc_def 4032 uint8_t blanking; // enum atom_blank_crtc_command 4033 uint16_t reserved; 4034 uint32_t reserved1; 4035 }; 4036 4037 enum atom_blank_crtc_command 4038 { 4039 ATOM_BLANKING = 1, 4040 ATOM_BLANKING_OFF = 0, 4041 }; 4042 4043 /****************************************************************************/ 4044 // Structures used by enablecrtc 4045 /****************************************************************************/ 4046 struct enable_crtc_parameters 4047 { 4048 uint8_t crtc_id; // enum atom_crtc_def 4049 uint8_t enable; // ATOM_ENABLE or ATOM_DISABLE 4050 uint8_t padding[2]; 4051 }; 4052 4053 4054 /****************************************************************************/ 4055 // Structure used by EnableDispPowerGating 4056 /****************************************************************************/ 4057 struct enable_disp_power_gating_parameters_v2_1 4058 { 4059 uint8_t disp_pipe_id; // ATOM_CRTC1, ATOM_CRTC2, ... 4060 uint8_t enable; // ATOM_ENABLE or ATOM_DISABLE 4061 uint8_t padding[2]; 4062 }; 4063 4064 struct enable_disp_power_gating_ps_allocation 4065 { 4066 struct enable_disp_power_gating_parameters_v2_1 param; 4067 uint32_t ulReserved[4]; 4068 }; 4069 4070 /****************************************************************************/ 4071 // Structure used in setcrtc_usingdtdtiming 4072 /****************************************************************************/ 4073 struct set_crtc_using_dtd_timing_parameters 4074 { 4075 uint16_t h_size; 4076 uint16_t h_blanking_time; 4077 uint16_t v_size; 4078 uint16_t v_blanking_time; 4079 uint16_t h_syncoffset; 4080 uint16_t h_syncwidth; 4081 uint16_t v_syncoffset; 4082 uint16_t v_syncwidth; 4083 uint16_t modemiscinfo; 4084 uint8_t h_border; 4085 uint8_t v_border; 4086 uint8_t crtc_id; // enum atom_crtc_def 4087 uint8_t encoder_mode; // atom_encode_mode_def 4088 uint8_t padding[2]; 4089 }; 4090 4091 4092 /****************************************************************************/ 4093 // Structures used by processi2cchanneltransaction 4094 /****************************************************************************/ 4095 struct process_i2c_channel_transaction_parameters 4096 { 4097 uint8_t i2cspeed_khz; 4098 union { 4099 uint8_t regindex; 4100 uint8_t status; /* enum atom_process_i2c_flag */ 4101 } regind_status; 4102 uint16_t i2c_data_out; 4103 uint8_t flag; /* enum atom_process_i2c_status */ 4104 uint8_t trans_bytes; 4105 uint8_t slave_addr; 4106 uint8_t i2c_id; 4107 }; 4108 4109 //ucFlag 4110 enum atom_process_i2c_flag 4111 { 4112 HW_I2C_WRITE = 1, 4113 HW_I2C_READ = 0, 4114 I2C_2BYTE_ADDR = 0x02, 4115 HW_I2C_SMBUS_BYTE_WR = 0x04, 4116 }; 4117 4118 //status 4119 enum atom_process_i2c_status 4120 { 4121 HW_ASSISTED_I2C_STATUS_FAILURE =2, 4122 HW_ASSISTED_I2C_STATUS_SUCCESS =1, 4123 }; 4124 4125 4126 /****************************************************************************/ 4127 // Structures used by processauxchanneltransaction 4128 /****************************************************************************/ 4129 4130 struct process_aux_channel_transaction_parameters_v1_2 4131 { 4132 uint16_t aux_request; 4133 uint16_t dataout; 4134 uint8_t channelid; 4135 union { 4136 uint8_t reply_status; 4137 uint8_t aux_delay; 4138 } aux_status_delay; 4139 uint8_t dataout_len; 4140 uint8_t hpd_id; //=0: HPD1, =1: HPD2, =2: HPD3, =3: HPD4, =4: HPD5, =5: HPD6 4141 }; 4142 4143 4144 /****************************************************************************/ 4145 // Structures used by selectcrtc_source 4146 /****************************************************************************/ 4147 4148 struct select_crtc_source_parameters_v2_3 4149 { 4150 uint8_t crtc_id; // enum atom_crtc_def 4151 uint8_t encoder_id; // enum atom_dig_def 4152 uint8_t encode_mode; // enum atom_encode_mode_def 4153 uint8_t dst_bpc; // enum atom_panel_bit_per_color 4154 }; 4155 4156 4157 /****************************************************************************/ 4158 // Structures used by digxencodercontrol 4159 /****************************************************************************/ 4160 4161 // ucAction: 4162 enum atom_dig_encoder_control_action 4163 { 4164 ATOM_ENCODER_CMD_DISABLE_DIG = 0, 4165 ATOM_ENCODER_CMD_ENABLE_DIG = 1, 4166 ATOM_ENCODER_CMD_DP_LINK_TRAINING_START = 0x08, 4167 ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN1 = 0x09, 4168 ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN2 = 0x0a, 4169 ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN3 = 0x13, 4170 ATOM_ENCODER_CMD_DP_LINK_TRAINING_COMPLETE = 0x0b, 4171 ATOM_ENCODER_CMD_DP_VIDEO_OFF = 0x0c, 4172 ATOM_ENCODER_CMD_DP_VIDEO_ON = 0x0d, 4173 ATOM_ENCODER_CMD_SETUP_PANEL_MODE = 0x10, 4174 ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN4 = 0x14, 4175 ATOM_ENCODER_CMD_STREAM_SETUP = 0x0F, 4176 ATOM_ENCODER_CMD_LINK_SETUP = 0x11, 4177 ATOM_ENCODER_CMD_ENCODER_BLANK = 0x12, 4178 }; 4179 4180 //define ucPanelMode 4181 enum atom_dig_encoder_control_panelmode 4182 { 4183 DP_PANEL_MODE_DISABLE = 0x00, 4184 DP_PANEL_MODE_ENABLE_eDP_MODE = 0x01, 4185 DP_PANEL_MODE_ENABLE_LVLINK_MODE = 0x11, 4186 }; 4187 4188 //ucDigId 4189 enum atom_dig_encoder_control_v5_digid 4190 { 4191 ATOM_ENCODER_CONFIG_V5_DIG0_ENCODER = 0x00, 4192 ATOM_ENCODER_CONFIG_V5_DIG1_ENCODER = 0x01, 4193 ATOM_ENCODER_CONFIG_V5_DIG2_ENCODER = 0x02, 4194 ATOM_ENCODER_CONFIG_V5_DIG3_ENCODER = 0x03, 4195 ATOM_ENCODER_CONFIG_V5_DIG4_ENCODER = 0x04, 4196 ATOM_ENCODER_CONFIG_V5_DIG5_ENCODER = 0x05, 4197 ATOM_ENCODER_CONFIG_V5_DIG6_ENCODER = 0x06, 4198 ATOM_ENCODER_CONFIG_V5_DIG7_ENCODER = 0x07, 4199 }; 4200 4201 struct dig_encoder_stream_setup_parameters_v1_5 4202 { 4203 uint8_t digid; // 0~6 map to DIG0~DIG6 enum atom_dig_encoder_control_v5_digid 4204 uint8_t action; // = ATOM_ENOCODER_CMD_STREAM_SETUP 4205 uint8_t digmode; // ATOM_ENCODER_MODE_DP/ATOM_ENCODER_MODE_DVI/ATOM_ENCODER_MODE_HDMI 4206 uint8_t lanenum; // Lane number 4207 uint32_t pclk_10khz; // Pixel Clock in 10Khz 4208 uint8_t bitpercolor; 4209 uint8_t dplinkrate_270mhz;//= DP link rate/270Mhz, =6: 1.62G = 10: 2.7G, =20: 5.4Ghz, =30: 8.1Ghz etc 4210 uint8_t reserved[2]; 4211 }; 4212 4213 struct dig_encoder_link_setup_parameters_v1_5 4214 { 4215 uint8_t digid; // 0~6 map to DIG0~DIG6 enum atom_dig_encoder_control_v5_digid 4216 uint8_t action; // = ATOM_ENOCODER_CMD_LINK_SETUP 4217 uint8_t digmode; // ATOM_ENCODER_MODE_DP/ATOM_ENCODER_MODE_DVI/ATOM_ENCODER_MODE_HDMI 4218 uint8_t lanenum; // Lane number 4219 uint8_t symclk_10khz; // Symbol Clock in 10Khz 4220 uint8_t hpd_sel; 4221 uint8_t digfe_sel; // DIG stream( front-end ) selection, bit0 means DIG0 FE is enable, 4222 uint8_t reserved[2]; 4223 }; 4224 4225 struct dp_panel_mode_set_parameters_v1_5 4226 { 4227 uint8_t digid; // 0~6 map to DIG0~DIG6 enum atom_dig_encoder_control_v5_digid 4228 uint8_t action; // = ATOM_ENCODER_CMD_DPLINK_SETUP 4229 uint8_t panelmode; // enum atom_dig_encoder_control_panelmode 4230 uint8_t reserved1; 4231 uint32_t reserved2[2]; 4232 }; 4233 4234 struct dig_encoder_generic_cmd_parameters_v1_5 4235 { 4236 uint8_t digid; // 0~6 map to DIG0~DIG6 enum atom_dig_encoder_control_v5_digid 4237 uint8_t action; // = rest of generic encoder command which does not carry any parameters 4238 uint8_t reserved1[2]; 4239 uint32_t reserved2[2]; 4240 }; 4241 4242 union dig_encoder_control_parameters_v1_5 4243 { 4244 struct dig_encoder_generic_cmd_parameters_v1_5 cmd_param; 4245 struct dig_encoder_stream_setup_parameters_v1_5 stream_param; 4246 struct dig_encoder_link_setup_parameters_v1_5 link_param; 4247 struct dp_panel_mode_set_parameters_v1_5 dppanel_param; 4248 }; 4249 4250 /* 4251 *************************************************************************** 4252 Structures used by dig1transmittercontrol 4253 *************************************************************************** 4254 */ 4255 struct dig_transmitter_control_parameters_v1_6 4256 { 4257 uint8_t phyid; // 0=UNIPHYA, 1=UNIPHYB, 2=UNIPHYC, 3=UNIPHYD, 4= UNIPHYE 5=UNIPHYF 4258 uint8_t action; // define as ATOM_TRANSMITER_ACTION_xxx 4259 union { 4260 uint8_t digmode; // enum atom_encode_mode_def 4261 uint8_t dplaneset; // DP voltage swing and pre-emphasis value defined in DPCD DP_LANE_SET, "DP_LANE_SET__xDB_y_zV" 4262 } mode_laneset; 4263 uint8_t lanenum; // Lane number 1, 2, 4, 8 4264 uint32_t symclk_10khz; // Symbol Clock in 10Khz 4265 uint8_t hpdsel; // =1: HPD1, =2: HPD2, .... =6: HPD6, =0: HPD is not assigned 4266 uint8_t digfe_sel; // DIG stream( front-end ) selection, bit0 means DIG0 FE is enable, 4267 uint8_t connobj_id; // Connector Object Id defined in ObjectId.h 4268 uint8_t reserved; 4269 uint32_t reserved1; 4270 }; 4271 4272 struct dig_transmitter_control_ps_allocation_v1_6 4273 { 4274 struct dig_transmitter_control_parameters_v1_6 param; 4275 uint32_t reserved[4]; 4276 }; 4277 4278 //ucAction 4279 enum atom_dig_transmitter_control_action 4280 { 4281 ATOM_TRANSMITTER_ACTION_DISABLE = 0, 4282 ATOM_TRANSMITTER_ACTION_ENABLE = 1, 4283 ATOM_TRANSMITTER_ACTION_LCD_BLOFF = 2, 4284 ATOM_TRANSMITTER_ACTION_LCD_BLON = 3, 4285 ATOM_TRANSMITTER_ACTION_BL_BRIGHTNESS_CONTROL = 4, 4286 ATOM_TRANSMITTER_ACTION_LCD_SELFTEST_START = 5, 4287 ATOM_TRANSMITTER_ACTION_LCD_SELFTEST_STOP = 6, 4288 ATOM_TRANSMITTER_ACTION_INIT = 7, 4289 ATOM_TRANSMITTER_ACTION_DISABLE_OUTPUT = 8, 4290 ATOM_TRANSMITTER_ACTION_ENABLE_OUTPUT = 9, 4291 ATOM_TRANSMITTER_ACTION_SETUP = 10, 4292 ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH = 11, 4293 ATOM_TRANSMITTER_ACTION_POWER_ON = 12, 4294 ATOM_TRANSMITTER_ACTION_POWER_OFF = 13, 4295 }; 4296 4297 // digfe_sel 4298 enum atom_dig_transmitter_control_digfe_sel 4299 { 4300 ATOM_TRANMSITTER_V6__DIGA_SEL = 0x01, 4301 ATOM_TRANMSITTER_V6__DIGB_SEL = 0x02, 4302 ATOM_TRANMSITTER_V6__DIGC_SEL = 0x04, 4303 ATOM_TRANMSITTER_V6__DIGD_SEL = 0x08, 4304 ATOM_TRANMSITTER_V6__DIGE_SEL = 0x10, 4305 ATOM_TRANMSITTER_V6__DIGF_SEL = 0x20, 4306 ATOM_TRANMSITTER_V6__DIGG_SEL = 0x40, 4307 }; 4308 4309 4310 //ucHPDSel 4311 enum atom_dig_transmitter_control_hpd_sel 4312 { 4313 ATOM_TRANSMITTER_V6_NO_HPD_SEL = 0x00, 4314 ATOM_TRANSMITTER_V6_HPD1_SEL = 0x01, 4315 ATOM_TRANSMITTER_V6_HPD2_SEL = 0x02, 4316 ATOM_TRANSMITTER_V6_HPD3_SEL = 0x03, 4317 ATOM_TRANSMITTER_V6_HPD4_SEL = 0x04, 4318 ATOM_TRANSMITTER_V6_HPD5_SEL = 0x05, 4319 ATOM_TRANSMITTER_V6_HPD6_SEL = 0x06, 4320 }; 4321 4322 // ucDPLaneSet 4323 enum atom_dig_transmitter_control_dplaneset 4324 { 4325 DP_LANE_SET__0DB_0_4V = 0x00, 4326 DP_LANE_SET__0DB_0_6V = 0x01, 4327 DP_LANE_SET__0DB_0_8V = 0x02, 4328 DP_LANE_SET__0DB_1_2V = 0x03, 4329 DP_LANE_SET__3_5DB_0_4V = 0x08, 4330 DP_LANE_SET__3_5DB_0_6V = 0x09, 4331 DP_LANE_SET__3_5DB_0_8V = 0x0a, 4332 DP_LANE_SET__6DB_0_4V = 0x10, 4333 DP_LANE_SET__6DB_0_6V = 0x11, 4334 DP_LANE_SET__9_5DB_0_4V = 0x18, 4335 }; 4336 4337 4338 4339 /****************************************************************************/ 4340 // Structures used by ExternalEncoderControl V2.4 4341 /****************************************************************************/ 4342 4343 struct external_encoder_control_parameters_v2_4 4344 { 4345 uint16_t pixelclock_10khz; // pixel clock in 10Khz, valid when ucAction=SETUP/ENABLE_OUTPUT 4346 uint8_t config; // indicate which encoder, and DP link rate when ucAction = SETUP/ENABLE_OUTPUT 4347 uint8_t action; // 4348 uint8_t encodermode; // encoder mode, only used when ucAction = SETUP/ENABLE_OUTPUT 4349 uint8_t lanenum; // lane number, only used when ucAction = SETUP/ENABLE_OUTPUT 4350 uint8_t bitpercolor; // output bit per color, only valid when ucAction = SETUP/ENABLE_OUTPUT and ucEncodeMode= DP 4351 uint8_t hpd_id; 4352 }; 4353 4354 4355 // ucAction 4356 enum external_encoder_control_action_def 4357 { 4358 EXTERNAL_ENCODER_ACTION_V3_DISABLE_OUTPUT = 0x00, 4359 EXTERNAL_ENCODER_ACTION_V3_ENABLE_OUTPUT = 0x01, 4360 EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT = 0x07, 4361 EXTERNAL_ENCODER_ACTION_V3_ENCODER_SETUP = 0x0f, 4362 EXTERNAL_ENCODER_ACTION_V3_ENCODER_BLANKING_OFF = 0x10, 4363 EXTERNAL_ENCODER_ACTION_V3_ENCODER_BLANKING = 0x11, 4364 EXTERNAL_ENCODER_ACTION_V3_DACLOAD_DETECTION = 0x12, 4365 EXTERNAL_ENCODER_ACTION_V3_DDC_SETUP = 0x14, 4366 }; 4367 4368 // ucConfig 4369 enum external_encoder_control_v2_4_config_def 4370 { 4371 EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_MASK = 0x03, 4372 EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_1_62GHZ = 0x00, 4373 EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ = 0x01, 4374 EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_5_40GHZ = 0x02, 4375 EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_3_24GHZ = 0x03, 4376 EXTERNAL_ENCODER_CONFIG_V3_ENCODER_SEL_MAKS = 0x70, 4377 EXTERNAL_ENCODER_CONFIG_V3_ENCODER1 = 0x00, 4378 EXTERNAL_ENCODER_CONFIG_V3_ENCODER2 = 0x10, 4379 EXTERNAL_ENCODER_CONFIG_V3_ENCODER3 = 0x20, 4380 }; 4381 4382 struct external_encoder_control_ps_allocation_v2_4 4383 { 4384 struct external_encoder_control_parameters_v2_4 sExtEncoder; 4385 uint32_t reserved[2]; 4386 }; 4387 4388 4389 /* 4390 *************************************************************************** 4391 AMD ACPI Table 4392 4393 *************************************************************************** 4394 */ 4395 4396 struct amd_acpi_description_header{ 4397 uint32_t signature; 4398 uint32_t tableLength; //Length 4399 uint8_t revision; 4400 uint8_t checksum; 4401 uint8_t oemId[6]; 4402 uint8_t oemTableId[8]; //UINT64 OemTableId; 4403 uint32_t oemRevision; 4404 uint32_t creatorId; 4405 uint32_t creatorRevision; 4406 }; 4407 4408 struct uefi_acpi_vfct{ 4409 struct amd_acpi_description_header sheader; 4410 uint8_t tableUUID[16]; //0x24 4411 uint32_t vbiosimageoffset; //0x34. Offset to the first GOP_VBIOS_CONTENT block from the beginning of the stucture. 4412 uint32_t lib1Imageoffset; //0x38. Offset to the first GOP_LIB1_CONTENT block from the beginning of the stucture. 4413 uint32_t reserved[4]; //0x3C 4414 }; 4415 4416 struct vfct_image_header{ 4417 uint32_t pcibus; //0x4C 4418 uint32_t pcidevice; //0x50 4419 uint32_t pcifunction; //0x54 4420 uint16_t vendorid; //0x58 4421 uint16_t deviceid; //0x5A 4422 uint16_t ssvid; //0x5C 4423 uint16_t ssid; //0x5E 4424 uint32_t revision; //0x60 4425 uint32_t imagelength; //0x64 4426 }; 4427 4428 4429 struct gop_vbios_content { 4430 struct vfct_image_header vbiosheader; 4431 uint8_t vbioscontent[1]; 4432 }; 4433 4434 struct gop_lib1_content { 4435 struct vfct_image_header lib1header; 4436 uint8_t lib1content[1]; 4437 }; 4438 4439 4440 4441 /* 4442 *************************************************************************** 4443 Scratch Register definitions 4444 Each number below indicates which scratch regiser request, Active and 4445 Connect all share the same definitions as display_device_tag defines 4446 *************************************************************************** 4447 */ 4448 4449 enum scratch_register_def{ 4450 ATOM_DEVICE_CONNECT_INFO_DEF = 0, 4451 ATOM_BL_BRI_LEVEL_INFO_DEF = 2, 4452 ATOM_ACTIVE_INFO_DEF = 3, 4453 ATOM_LCD_INFO_DEF = 4, 4454 ATOM_DEVICE_REQ_INFO_DEF = 5, 4455 ATOM_ACC_CHANGE_INFO_DEF = 6, 4456 ATOM_PRE_OS_MODE_INFO_DEF = 7, 4457 ATOM_PRE_OS_ASSERTION_DEF = 8, //For GOP to record a 32bit assertion code, this is enabled by default in prodution GOP drivers. 4458 ATOM_INTERNAL_TIMER_INFO_DEF = 10, 4459 }; 4460 4461 enum scratch_device_connect_info_bit_def{ 4462 ATOM_DISPLAY_LCD1_CONNECT =0x0002, 4463 ATOM_DISPLAY_DFP1_CONNECT =0x0008, 4464 ATOM_DISPLAY_DFP2_CONNECT =0x0080, 4465 ATOM_DISPLAY_DFP3_CONNECT =0x0200, 4466 ATOM_DISPLAY_DFP4_CONNECT =0x0400, 4467 ATOM_DISPLAY_DFP5_CONNECT =0x0800, 4468 ATOM_DISPLAY_DFP6_CONNECT =0x0040, 4469 ATOM_DISPLAY_DFPx_CONNECT =0x0ec8, 4470 ATOM_CONNECT_INFO_DEVICE_MASK =0x0fff, 4471 }; 4472 4473 enum scratch_bl_bri_level_info_bit_def{ 4474 ATOM_CURRENT_BL_LEVEL_SHIFT =0x8, 4475 #ifndef _H2INC 4476 ATOM_CURRENT_BL_LEVEL_MASK =0x0000ff00, 4477 ATOM_DEVICE_DPMS_STATE =0x00010000, 4478 #endif 4479 }; 4480 4481 enum scratch_active_info_bits_def{ 4482 ATOM_DISPLAY_LCD1_ACTIVE =0x0002, 4483 ATOM_DISPLAY_DFP1_ACTIVE =0x0008, 4484 ATOM_DISPLAY_DFP2_ACTIVE =0x0080, 4485 ATOM_DISPLAY_DFP3_ACTIVE =0x0200, 4486 ATOM_DISPLAY_DFP4_ACTIVE =0x0400, 4487 ATOM_DISPLAY_DFP5_ACTIVE =0x0800, 4488 ATOM_DISPLAY_DFP6_ACTIVE =0x0040, 4489 ATOM_ACTIVE_INFO_DEVICE_MASK =0x0fff, 4490 }; 4491 4492 enum scratch_device_req_info_bits_def{ 4493 ATOM_DISPLAY_LCD1_REQ =0x0002, 4494 ATOM_DISPLAY_DFP1_REQ =0x0008, 4495 ATOM_DISPLAY_DFP2_REQ =0x0080, 4496 ATOM_DISPLAY_DFP3_REQ =0x0200, 4497 ATOM_DISPLAY_DFP4_REQ =0x0400, 4498 ATOM_DISPLAY_DFP5_REQ =0x0800, 4499 ATOM_DISPLAY_DFP6_REQ =0x0040, 4500 ATOM_REQ_INFO_DEVICE_MASK =0x0fff, 4501 }; 4502 4503 enum scratch_acc_change_info_bitshift_def{ 4504 ATOM_ACC_CHANGE_ACC_MODE_SHIFT =4, 4505 ATOM_ACC_CHANGE_LID_STATUS_SHIFT =6, 4506 }; 4507 4508 enum scratch_acc_change_info_bits_def{ 4509 ATOM_ACC_CHANGE_ACC_MODE =0x00000010, 4510 ATOM_ACC_CHANGE_LID_STATUS =0x00000040, 4511 }; 4512 4513 enum scratch_pre_os_mode_info_bits_def{ 4514 ATOM_PRE_OS_MODE_MASK =0x00000003, 4515 ATOM_PRE_OS_MODE_VGA =0x00000000, 4516 ATOM_PRE_OS_MODE_VESA =0x00000001, 4517 ATOM_PRE_OS_MODE_GOP =0x00000002, 4518 ATOM_PRE_OS_MODE_PIXEL_DEPTH =0x0000000C, 4519 ATOM_PRE_OS_MODE_PIXEL_FORMAT_MASK=0x000000F0, 4520 ATOM_PRE_OS_MODE_8BIT_PAL_EN =0x00000100, 4521 ATOM_ASIC_INIT_COMPLETE =0x00000200, 4522 #ifndef _H2INC 4523 ATOM_PRE_OS_MODE_NUMBER_MASK =0xFFFF0000, 4524 #endif 4525 }; 4526 4527 4528 4529 /* 4530 *************************************************************************** 4531 ATOM firmware ID header file 4532 !! Please keep it at end of the atomfirmware.h !! 4533 *************************************************************************** 4534 */ 4535 #include "atomfirmwareid.h" 4536 #pragma pack() 4537 4538 #endif 4539 4540