1 /* 2 * Copyright 2006-2007 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 23 24 /****************************************************************************/ 25 /*Portion I: Definitions shared between VBIOS and Driver */ 26 /****************************************************************************/ 27 28 #ifndef _ATOMBIOS_H 29 #define _ATOMBIOS_H 30 31 #define ATOM_VERSION_MAJOR 0x00020000 32 #define ATOM_VERSION_MINOR 0x00000002 33 34 #define ATOM_HEADER_VERSION (ATOM_VERSION_MAJOR | ATOM_VERSION_MINOR) 35 36 /* Endianness should be specified before inclusion, 37 * default to little endian 38 */ 39 #ifndef ATOM_BIG_ENDIAN 40 #error Endian not specified 41 #endif 42 43 #ifdef _H2INC 44 #ifndef ULONG 45 typedef unsigned long ULONG; 46 #endif 47 48 #ifndef UCHAR 49 typedef unsigned char UCHAR; 50 #endif 51 52 #ifndef USHORT 53 typedef unsigned short USHORT; 54 #endif 55 #endif 56 57 #define ATOM_DAC_A 0 58 #define ATOM_DAC_B 1 59 #define ATOM_EXT_DAC 2 60 61 #define ATOM_CRTC1 0 62 #define ATOM_CRTC2 1 63 #define ATOM_CRTC3 2 64 #define ATOM_CRTC4 3 65 #define ATOM_CRTC5 4 66 #define ATOM_CRTC6 5 67 68 #define ATOM_UNDERLAY_PIPE0 16 69 #define ATOM_UNDERLAY_PIPE1 17 70 71 #define ATOM_CRTC_INVALID 0xFF 72 73 #define ATOM_DIGA 0 74 #define ATOM_DIGB 1 75 76 #define ATOM_PPLL1 0 77 #define ATOM_PPLL2 1 78 #define ATOM_DCPLL 2 79 #define ATOM_PPLL0 2 80 #define ATOM_PPLL3 3 81 82 #define ATOM_EXT_PLL1 8 83 #define ATOM_EXT_PLL2 9 84 #define ATOM_EXT_CLOCK 10 85 #define ATOM_PPLL_INVALID 0xFF 86 87 #define ENCODER_REFCLK_SRC_P1PLL 0 88 #define ENCODER_REFCLK_SRC_P2PLL 1 89 #define ENCODER_REFCLK_SRC_DCPLL 2 90 #define ENCODER_REFCLK_SRC_EXTCLK 3 91 #define ENCODER_REFCLK_SRC_INVALID 0xFF 92 93 #define ATOM_SCALER_DISABLE 0 //For Fudo, it's bypass and auto-cengter & no replication 94 #define ATOM_SCALER_CENTER 1 //For Fudo, it's bypass and auto-center & auto replication 95 #define ATOM_SCALER_EXPANSION 2 //For Fudo, it's 2 Tap alpha blending mode 96 #define ATOM_SCALER_MULTI_EX 3 //For Fudo only, it's multi-tap mode only used to drive TV or CV, only used by Bios 97 98 #define ATOM_DISABLE 0 99 #define ATOM_ENABLE 1 100 #define ATOM_LCD_BLOFF (ATOM_DISABLE+2) 101 #define ATOM_LCD_BLON (ATOM_ENABLE+2) 102 #define ATOM_LCD_BL_BRIGHTNESS_CONTROL (ATOM_ENABLE+3) 103 #define ATOM_LCD_SELFTEST_START (ATOM_DISABLE+5) 104 #define ATOM_LCD_SELFTEST_STOP (ATOM_ENABLE+5) 105 #define ATOM_ENCODER_INIT (ATOM_DISABLE+7) 106 #define ATOM_INIT (ATOM_DISABLE+7) 107 #define ATOM_GET_STATUS (ATOM_DISABLE+8) 108 109 #define ATOM_BLANKING 1 110 #define ATOM_BLANKING_OFF 0 111 112 113 #define ATOM_CRT1 0 114 #define ATOM_CRT2 1 115 116 #define ATOM_TV_NTSC 1 117 #define ATOM_TV_NTSCJ 2 118 #define ATOM_TV_PAL 3 119 #define ATOM_TV_PALM 4 120 #define ATOM_TV_PALCN 5 121 #define ATOM_TV_PALN 6 122 #define ATOM_TV_PAL60 7 123 #define ATOM_TV_SECAM 8 124 #define ATOM_TV_CV 16 125 126 #define ATOM_DAC1_PS2 1 127 #define ATOM_DAC1_CV 2 128 #define ATOM_DAC1_NTSC 3 129 #define ATOM_DAC1_PAL 4 130 131 #define ATOM_DAC2_PS2 ATOM_DAC1_PS2 132 #define ATOM_DAC2_CV ATOM_DAC1_CV 133 #define ATOM_DAC2_NTSC ATOM_DAC1_NTSC 134 #define ATOM_DAC2_PAL ATOM_DAC1_PAL 135 136 #define ATOM_PM_ON 0 137 #define ATOM_PM_STANDBY 1 138 #define ATOM_PM_SUSPEND 2 139 #define ATOM_PM_OFF 3 140 141 // For ATOM_LVDS_INFO_V12 142 // Bit0:{=0:single, =1:dual}, 143 // Bit1 {=0:666RGB, =1:888RGB}, 144 // Bit2:3:{Grey level} 145 // Bit4:{=0:LDI format for RGB888, =1 FPDI format for RGB888} 146 #define ATOM_PANEL_MISC_DUAL 0x00000001 147 #define ATOM_PANEL_MISC_888RGB 0x00000002 148 #define ATOM_PANEL_MISC_GREY_LEVEL 0x0000000C 149 #define ATOM_PANEL_MISC_FPDI 0x00000010 150 #define ATOM_PANEL_MISC_GREY_LEVEL_SHIFT 2 151 #define ATOM_PANEL_MISC_SPATIAL 0x00000020 152 #define ATOM_PANEL_MISC_TEMPORAL 0x00000040 153 #define ATOM_PANEL_MISC_API_ENABLED 0x00000080 154 155 #define MEMTYPE_DDR1 "DDR1" 156 #define MEMTYPE_DDR2 "DDR2" 157 #define MEMTYPE_DDR3 "DDR3" 158 #define MEMTYPE_DDR4 "DDR4" 159 160 #define ASIC_BUS_TYPE_PCI "PCI" 161 #define ASIC_BUS_TYPE_AGP "AGP" 162 #define ASIC_BUS_TYPE_PCIE "PCI_EXPRESS" 163 164 //Maximum size of that FireGL flag string 165 #define ATOM_FIREGL_FLAG_STRING "FGL" //Flag used to enable FireGL Support 166 #define ATOM_MAX_SIZE_OF_FIREGL_FLAG_STRING 3 //sizeof( ATOM_FIREGL_FLAG_STRING ) 167 168 #define ATOM_FAKE_DESKTOP_STRING "DSK" //Flag used to enable mobile ASIC on Desktop 169 #define ATOM_MAX_SIZE_OF_FAKE_DESKTOP_STRING ATOM_MAX_SIZE_OF_FIREGL_FLAG_STRING 170 171 #define ATOM_M54T_FLAG_STRING "M54T" //Flag used to enable M54T Support 172 #define ATOM_MAX_SIZE_OF_M54T_FLAG_STRING 4 //sizeof( ATOM_M54T_FLAG_STRING ) 173 174 #define HW_ASSISTED_I2C_STATUS_FAILURE 2 175 #define HW_ASSISTED_I2C_STATUS_SUCCESS 1 176 177 #pragma pack(1) // BIOS data must use byte aligment 178 179 // Define offset to location of ROM header. 180 #define OFFSET_TO_POINTER_TO_ATOM_ROM_HEADER 0x00000048L 181 #define OFFSET_TO_ATOM_ROM_IMAGE_SIZE 0x00000002L 182 183 #define OFFSET_TO_ATOMBIOS_ASIC_BUS_MEM_TYPE 0x94 184 #define MAXSIZE_OF_ATOMBIOS_ASIC_BUS_MEM_TYPE 20 //including the terminator 0x0! 185 #define OFFSET_TO_GET_ATOMBIOS_STRINGS_NUMBER 0x002f 186 #define OFFSET_TO_GET_ATOMBIOS_STRINGS_START 0x006e 187 188 /****************************************************************************/ 189 // Common header for all tables (Data table, Command table). 190 // Every table pointed _ATOM_MASTER_DATA_TABLE has this common header. 191 // And the pointer actually points to this header. 192 /****************************************************************************/ 193 194 typedef struct _ATOM_COMMON_TABLE_HEADER 195 { 196 USHORT usStructureSize; 197 UCHAR ucTableFormatRevision; //Change it when the Parser is not backward compatible 198 UCHAR ucTableContentRevision; //Change it only when the table needs to change but the firmware 199 //Image can't be updated, while Driver needs to carry the new table! 200 }ATOM_COMMON_TABLE_HEADER; 201 202 /****************************************************************************/ 203 // Structure stores the ROM header. 204 /****************************************************************************/ 205 typedef struct _ATOM_ROM_HEADER 206 { 207 ATOM_COMMON_TABLE_HEADER sHeader; 208 UCHAR uaFirmWareSignature[4]; //Signature to distinguish between Atombios and non-atombios, 209 //atombios should init it as "ATOM", don't change the position 210 USHORT usBiosRuntimeSegmentAddress; 211 USHORT usProtectedModeInfoOffset; 212 USHORT usConfigFilenameOffset; 213 USHORT usCRC_BlockOffset; 214 USHORT usBIOS_BootupMessageOffset; 215 USHORT usInt10Offset; 216 USHORT usPciBusDevInitCode; 217 USHORT usIoBaseAddress; 218 USHORT usSubsystemVendorID; 219 USHORT usSubsystemID; 220 USHORT usPCI_InfoOffset; 221 USHORT usMasterCommandTableOffset;//Offest for SW to get all command table offsets, Don't change the position 222 USHORT usMasterDataTableOffset; //Offest for SW to get all data table offsets, Don't change the position 223 UCHAR ucExtendedFunctionCode; 224 UCHAR ucReserved; 225 }ATOM_ROM_HEADER; 226 227 //==============================Command Table Portion==================================== 228 229 230 /****************************************************************************/ 231 // Structures used in Command.mtb 232 /****************************************************************************/ 233 typedef struct _ATOM_MASTER_LIST_OF_COMMAND_TABLES{ 234 USHORT ASIC_Init; //Function Table, used by various SW components,latest version 1.1 235 USHORT GetDisplaySurfaceSize; //Atomic Table, Used by Bios when enabling HW ICON 236 USHORT ASIC_RegistersInit; //Atomic Table, indirectly used by various SW components,called from ASIC_Init 237 USHORT VRAM_BlockVenderDetection; //Atomic Table, used only by Bios 238 USHORT DIGxEncoderControl; //Only used by Bios 239 USHORT MemoryControllerInit; //Atomic Table, indirectly used by various SW components,called from ASIC_Init 240 USHORT EnableCRTCMemReq; //Function Table,directly used by various SW components,latest version 2.1 241 USHORT MemoryParamAdjust; //Atomic Table, indirectly used by various SW components,called from SetMemoryClock if needed 242 USHORT DVOEncoderControl; //Function Table,directly used by various SW components,latest version 1.2 243 USHORT GPIOPinControl; //Atomic Table, only used by Bios 244 USHORT SetEngineClock; //Function Table,directly used by various SW components,latest version 1.1 245 USHORT SetMemoryClock; //Function Table,directly used by various SW components,latest version 1.1 246 USHORT SetPixelClock; //Function Table,directly used by various SW components,latest version 1.2 247 USHORT EnableDispPowerGating; //Atomic Table, indirectly used by various SW components,called from ASIC_Init 248 USHORT ResetMemoryDLL; //Atomic Table, indirectly used by various SW components,called from SetMemoryClock 249 USHORT ResetMemoryDevice; //Atomic Table, indirectly used by various SW components,called from SetMemoryClock 250 USHORT MemoryPLLInit; //Atomic Table, used only by Bios 251 USHORT AdjustDisplayPll; //Atomic Table, used by various SW componentes. 252 USHORT AdjustMemoryController; //Atomic Table, indirectly used by various SW components,called from SetMemoryClock 253 USHORT EnableASIC_StaticPwrMgt; //Atomic Table, only used by Bios 254 USHORT SetUniphyInstance; //Atomic Table, only used by Bios 255 USHORT DAC_LoadDetection; //Atomic Table, directly used by various SW components,latest version 1.2 256 USHORT LVTMAEncoderControl; //Atomic Table,directly used by various SW components,latest version 1.3 257 USHORT HW_Misc_Operation; //Atomic Table, directly used by various SW components,latest version 1.1 258 USHORT DAC1EncoderControl; //Atomic Table, directly used by various SW components,latest version 1.1 259 USHORT DAC2EncoderControl; //Atomic Table, directly used by various SW components,latest version 1.1 260 USHORT DVOOutputControl; //Atomic Table, directly used by various SW components,latest version 1.1 261 USHORT CV1OutputControl; //Atomic Table, Atomic Table, Obsolete from Ry6xx, use DAC2 Output instead 262 USHORT GetConditionalGoldenSetting; //Only used by Bios 263 USHORT SMC_Init; //Function Table,directly used by various SW components,latest version 1.1 264 USHORT PatchMCSetting; //only used by BIOS 265 USHORT MC_SEQ_Control; //only used by BIOS 266 USHORT Gfx_Harvesting; //Atomic Table, Obsolete from Ry6xx, Now only used by BIOS for GFX harvesting 267 USHORT EnableScaler; //Atomic Table, used only by Bios 268 USHORT BlankCRTC; //Atomic Table, directly used by various SW components,latest version 1.1 269 USHORT EnableCRTC; //Atomic Table, directly used by various SW components,latest version 1.1 270 USHORT GetPixelClock; //Atomic Table, directly used by various SW components,latest version 1.1 271 USHORT EnableVGA_Render; //Function Table,directly used by various SW components,latest version 1.1 272 USHORT GetSCLKOverMCLKRatio; //Atomic Table, only used by Bios 273 USHORT SetCRTC_Timing; //Atomic Table, directly used by various SW components,latest version 1.1 274 USHORT SetCRTC_OverScan; //Atomic Table, used by various SW components,latest version 1.1 275 USHORT SetCRTC_Replication; //Atomic Table, used only by Bios 276 USHORT SelectCRTC_Source; //Atomic Table, directly used by various SW components,latest version 1.1 277 USHORT EnableGraphSurfaces; //Atomic Table, used only by Bios 278 USHORT UpdateCRTC_DoubleBufferRegisters; //Atomic Table, used only by Bios 279 USHORT LUT_AutoFill; //Atomic Table, only used by Bios 280 USHORT EnableHW_IconCursor; //Atomic Table, only used by Bios 281 USHORT GetMemoryClock; //Atomic Table, directly used by various SW components,latest version 1.1 282 USHORT GetEngineClock; //Atomic Table, directly used by various SW components,latest version 1.1 283 USHORT SetCRTC_UsingDTDTiming; //Atomic Table, directly used by various SW components,latest version 1.1 284 USHORT ExternalEncoderControl; //Atomic Table, directly used by various SW components,latest version 2.1 285 USHORT LVTMAOutputControl; //Atomic Table, directly used by various SW components,latest version 1.1 286 USHORT VRAM_BlockDetectionByStrap; //Atomic Table, used only by Bios 287 USHORT MemoryCleanUp; //Atomic Table, only used by Bios 288 USHORT ProcessI2cChannelTransaction; //Function Table,only used by Bios 289 USHORT WriteOneByteToHWAssistedI2C; //Function Table,indirectly used by various SW components 290 USHORT ReadHWAssistedI2CStatus; //Atomic Table, indirectly used by various SW components 291 USHORT SpeedFanControl; //Function Table,indirectly used by various SW components,called from ASIC_Init 292 USHORT PowerConnectorDetection; //Atomic Table, directly used by various SW components,latest version 1.1 293 USHORT MC_Synchronization; //Atomic Table, indirectly used by various SW components,called from SetMemoryClock 294 USHORT ComputeMemoryEnginePLL; //Atomic Table, indirectly used by various SW components,called from SetMemory/EngineClock 295 USHORT MemoryRefreshConversion; //Atomic Table, indirectly used by various SW components,called from SetMemory or SetEngineClock 296 USHORT VRAM_GetCurrentInfoBlock; //Atomic Table, used only by Bios 297 USHORT DynamicMemorySettings; //Atomic Table, indirectly used by various SW components,called from SetMemoryClock 298 USHORT MemoryTraining; //Atomic Table, used only by Bios 299 USHORT EnableSpreadSpectrumOnPPLL; //Atomic Table, directly used by various SW components,latest version 1.2 300 USHORT TMDSAOutputControl; //Atomic Table, directly used by various SW components,latest version 1.1 301 USHORT SetVoltage; //Function Table,directly and/or indirectly used by various SW components,latest version 1.1 302 USHORT DAC1OutputControl; //Atomic Table, directly used by various SW components,latest version 1.1 303 USHORT ReadEfuseValue; //Atomic Table, directly used by various SW components,latest version 1.1 304 USHORT ComputeMemoryClockParam; //Function Table,only used by Bios, obsolete soon.Switch to use "ReadEDIDFromHWAssistedI2C" 305 USHORT ClockSource; //Atomic Table, indirectly used by various SW components,called from ASIC_Init 306 USHORT MemoryDeviceInit; //Atomic Table, indirectly used by various SW components,called from SetMemoryClock 307 USHORT GetDispObjectInfo; //Atomic Table, indirectly used by various SW components,called from EnableVGARender 308 USHORT DIG1EncoderControl; //Atomic Table,directly used by various SW components,latest version 1.1 309 USHORT DIG2EncoderControl; //Atomic Table,directly used by various SW components,latest version 1.1 310 USHORT DIG1TransmitterControl; //Atomic Table,directly used by various SW components,latest version 1.1 311 USHORT DIG2TransmitterControl; //Atomic Table,directly used by various SW components,latest version 1.1 312 USHORT ProcessAuxChannelTransaction; //Function Table,only used by Bios 313 USHORT DPEncoderService; //Function Table,only used by Bios 314 USHORT GetVoltageInfo; //Function Table,only used by Bios since SI 315 }ATOM_MASTER_LIST_OF_COMMAND_TABLES; 316 317 // For backward compatible 318 #define ReadEDIDFromHWAssistedI2C ProcessI2cChannelTransaction 319 #define DPTranslatorControl DIG2EncoderControl 320 #define UNIPHYTransmitterControl DIG1TransmitterControl 321 #define LVTMATransmitterControl DIG2TransmitterControl 322 #define SetCRTC_DPM_State GetConditionalGoldenSetting 323 #define ASIC_StaticPwrMgtStatusChange SetUniphyInstance 324 #define HPDInterruptService ReadHWAssistedI2CStatus 325 #define EnableVGA_Access GetSCLKOverMCLKRatio 326 #define EnableYUV GetDispObjectInfo 327 #define DynamicClockGating EnableDispPowerGating 328 #define SetupHWAssistedI2CStatus ComputeMemoryClockParam 329 #define DAC2OutputControl ReadEfuseValue 330 331 #define TMDSAEncoderControl PatchMCSetting 332 #define LVDSEncoderControl MC_SEQ_Control 333 #define LCD1OutputControl HW_Misc_Operation 334 #define TV1OutputControl Gfx_Harvesting 335 #define TVEncoderControl SMC_Init 336 337 typedef struct _ATOM_MASTER_COMMAND_TABLE 338 { 339 ATOM_COMMON_TABLE_HEADER sHeader; 340 ATOM_MASTER_LIST_OF_COMMAND_TABLES ListOfCommandTables; 341 }ATOM_MASTER_COMMAND_TABLE; 342 343 /****************************************************************************/ 344 // Structures used in every command table 345 /****************************************************************************/ 346 typedef struct _ATOM_TABLE_ATTRIBUTE 347 { 348 #if ATOM_BIG_ENDIAN 349 USHORT UpdatedByUtility:1; //[15]=Table updated by utility flag 350 USHORT PS_SizeInBytes:7; //[14:8]=Size of parameter space in Bytes (multiple of a dword), 351 USHORT WS_SizeInBytes:8; //[7:0]=Size of workspace in Bytes (in multiple of a dword), 352 #else 353 USHORT WS_SizeInBytes:8; //[7:0]=Size of workspace in Bytes (in multiple of a dword), 354 USHORT PS_SizeInBytes:7; //[14:8]=Size of parameter space in Bytes (multiple of a dword), 355 USHORT UpdatedByUtility:1; //[15]=Table updated by utility flag 356 #endif 357 }ATOM_TABLE_ATTRIBUTE; 358 359 /****************************************************************************/ 360 // Common header for all command tables. 361 // Every table pointed by _ATOM_MASTER_COMMAND_TABLE has this common header. 362 // And the pointer actually points to this header. 363 /****************************************************************************/ 364 typedef struct _ATOM_COMMON_ROM_COMMAND_TABLE_HEADER 365 { 366 ATOM_COMMON_TABLE_HEADER CommonHeader; 367 ATOM_TABLE_ATTRIBUTE TableAttribute; 368 }ATOM_COMMON_ROM_COMMAND_TABLE_HEADER; 369 370 /****************************************************************************/ 371 // Structures used by ComputeMemoryEnginePLLTable 372 /****************************************************************************/ 373 374 #define COMPUTE_MEMORY_PLL_PARAM 1 375 #define COMPUTE_ENGINE_PLL_PARAM 2 376 #define ADJUST_MC_SETTING_PARAM 3 377 378 /****************************************************************************/ 379 // Structures used by AdjustMemoryControllerTable 380 /****************************************************************************/ 381 typedef struct _ATOM_ADJUST_MEMORY_CLOCK_FREQ 382 { 383 #if ATOM_BIG_ENDIAN 384 ULONG ulPointerReturnFlag:1; // BYTE_3[7]=1 - Return the pointer to the right Data Block; BYTE_3[7]=0 - Program the right Data Block 385 ULONG ulMemoryModuleNumber:7; // BYTE_3[6:0] 386 ULONG ulClockFreq:24; 387 #else 388 ULONG ulClockFreq:24; 389 ULONG ulMemoryModuleNumber:7; // BYTE_3[6:0] 390 ULONG ulPointerReturnFlag:1; // BYTE_3[7]=1 - Return the pointer to the right Data Block; BYTE_3[7]=0 - Program the right Data Block 391 #endif 392 }ATOM_ADJUST_MEMORY_CLOCK_FREQ; 393 #define POINTER_RETURN_FLAG 0x80 394 395 typedef struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS 396 { 397 ULONG ulClock; //When returen, it's the re-calculated clock based on given Fb_div Post_Div and ref_div 398 UCHAR ucAction; //0:reserved //1:Memory //2:Engine 399 UCHAR ucReserved; //may expand to return larger Fbdiv later 400 UCHAR ucFbDiv; //return value 401 UCHAR ucPostDiv; //return value 402 }COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS; 403 404 typedef struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V2 405 { 406 ULONG ulClock; //When return, [23:0] return real clock 407 UCHAR ucAction; //0:reserved;COMPUTE_MEMORY_PLL_PARAM:Memory;COMPUTE_ENGINE_PLL_PARAM:Engine. it return ref_div to be written to register 408 USHORT usFbDiv; //return Feedback value to be written to register 409 UCHAR ucPostDiv; //return post div to be written to register 410 }COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V2; 411 412 #define COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_PS_ALLOCATION COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS 413 414 #define SET_CLOCK_FREQ_MASK 0x00FFFFFF //Clock change tables only take bit [23:0] as the requested clock value 415 #define USE_NON_BUS_CLOCK_MASK 0x01000000 //Applicable to both memory and engine clock change, when set, it uses another clock as the temporary clock (engine uses memory and vice versa) 416 #define USE_MEMORY_SELF_REFRESH_MASK 0x02000000 //Only applicable to memory clock change, when set, using memory self refresh during clock transition 417 #define SKIP_INTERNAL_MEMORY_PARAMETER_CHANGE 0x04000000 //Only applicable to memory clock change, when set, the table will skip predefined internal memory parameter change 418 #define FIRST_TIME_CHANGE_CLOCK 0x08000000 //Applicable to both memory and engine clock change,when set, it means this is 1st time to change clock after ASIC bootup 419 #define SKIP_SW_PROGRAM_PLL 0x10000000 //Applicable to both memory and engine clock change, when set, it means the table will not program SPLL/MPLL 420 #define USE_SS_ENABLED_PIXEL_CLOCK USE_NON_BUS_CLOCK_MASK 421 422 #define b3USE_NON_BUS_CLOCK_MASK 0x01 //Applicable to both memory and engine clock change, when set, it uses another clock as the temporary clock (engine uses memory and vice versa) 423 #define b3USE_MEMORY_SELF_REFRESH 0x02 //Only applicable to memory clock change, when set, using memory self refresh during clock transition 424 #define b3SKIP_INTERNAL_MEMORY_PARAMETER_CHANGE 0x04 //Only applicable to memory clock change, when set, the table will skip predefined internal memory parameter change 425 #define b3FIRST_TIME_CHANGE_CLOCK 0x08 //Applicable to both memory and engine clock change,when set, it means this is 1st time to change clock after ASIC bootup 426 #define b3SKIP_SW_PROGRAM_PLL 0x10 //Applicable to both memory and engine clock change, when set, it means the table will not program SPLL/MPLL 427 #define b3DRAM_SELF_REFRESH_EXIT 0x20 //Applicable to DRAM self refresh exit only. when set, it means it will go to program DRAM self refresh exit path 428 429 typedef struct _ATOM_COMPUTE_CLOCK_FREQ 430 { 431 #if ATOM_BIG_ENDIAN 432 ULONG ulComputeClockFlag:8; // =1: COMPUTE_MEMORY_PLL_PARAM, =2: COMPUTE_ENGINE_PLL_PARAM 433 ULONG ulClockFreq:24; // in unit of 10kHz 434 #else 435 ULONG ulClockFreq:24; // in unit of 10kHz 436 ULONG ulComputeClockFlag:8; // =1: COMPUTE_MEMORY_PLL_PARAM, =2: COMPUTE_ENGINE_PLL_PARAM 437 #endif 438 }ATOM_COMPUTE_CLOCK_FREQ; 439 440 typedef struct _ATOM_S_MPLL_FB_DIVIDER 441 { 442 USHORT usFbDivFrac; 443 USHORT usFbDiv; 444 }ATOM_S_MPLL_FB_DIVIDER; 445 446 typedef struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V3 447 { 448 union 449 { 450 ATOM_COMPUTE_CLOCK_FREQ ulClock; //Input Parameter 451 ATOM_S_MPLL_FB_DIVIDER ulFbDiv; //Output Parameter 452 }; 453 UCHAR ucRefDiv; //Output Parameter 454 UCHAR ucPostDiv; //Output Parameter 455 UCHAR ucCntlFlag; //Output Parameter 456 UCHAR ucReserved; 457 }COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V3; 458 459 // ucCntlFlag 460 #define ATOM_PLL_CNTL_FLAG_PLL_POST_DIV_EN 1 461 #define ATOM_PLL_CNTL_FLAG_MPLL_VCO_MODE 2 462 #define ATOM_PLL_CNTL_FLAG_FRACTION_DISABLE 4 463 #define ATOM_PLL_CNTL_FLAG_SPLL_ISPARE_9 8 464 465 466 // V4 are only used for APU which PLL outside GPU 467 typedef struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V4 468 { 469 #if ATOM_BIG_ENDIAN 470 ULONG ucPostDiv:8; //return parameter: post divider which is used to program to register directly 471 ULONG ulClock:24; //Input= target clock, output = actual clock 472 #else 473 ULONG ulClock:24; //Input= target clock, output = actual clock 474 ULONG ucPostDiv:8; //return parameter: post divider which is used to program to register directly 475 #endif 476 }COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V4; 477 478 typedef struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V5 479 { 480 union 481 { 482 ATOM_COMPUTE_CLOCK_FREQ ulClock; //Input Parameter 483 ATOM_S_MPLL_FB_DIVIDER ulFbDiv; //Output Parameter 484 }; 485 UCHAR ucRefDiv; //Output Parameter 486 UCHAR ucPostDiv; //Output Parameter 487 union 488 { 489 UCHAR ucCntlFlag; //Output Flags 490 UCHAR ucInputFlag; //Input Flags. ucInputFlag[0] - Strobe(1)/Performance(0) mode 491 }; 492 UCHAR ucReserved; 493 }COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V5; 494 495 496 typedef struct _COMPUTE_GPU_CLOCK_INPUT_PARAMETERS_V1_6 497 { 498 ATOM_COMPUTE_CLOCK_FREQ ulClock; //Input Parameter 499 ULONG ulReserved[2]; 500 }COMPUTE_GPU_CLOCK_INPUT_PARAMETERS_V1_6; 501 502 //ATOM_COMPUTE_CLOCK_FREQ.ulComputeClockFlag 503 #define COMPUTE_GPUCLK_INPUT_FLAG_CLK_TYPE_MASK 0x0f 504 #define COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK 0x00 505 #define COMPUTE_GPUCLK_INPUT_FLAG_SCLK 0x01 506 507 508 typedef struct _COMPUTE_GPU_CLOCK_OUTPUT_PARAMETERS_V1_6 509 { 510 COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V4 ulClock; //Output Parameter: ucPostDiv=DFS divider 511 ATOM_S_MPLL_FB_DIVIDER ulFbDiv; //Output Parameter: PLL FB divider 512 UCHAR ucPllRefDiv; //Output Parameter: PLL ref divider 513 UCHAR ucPllPostDiv; //Output Parameter: PLL post divider 514 UCHAR ucPllCntlFlag; //Output Flags: control flag 515 UCHAR ucReserved; 516 }COMPUTE_GPU_CLOCK_OUTPUT_PARAMETERS_V1_6; 517 518 //ucPllCntlFlag 519 #define SPLL_CNTL_FLAG_VCO_MODE_MASK 0x03 520 521 522 // ucInputFlag 523 #define ATOM_PLL_INPUT_FLAG_PLL_STROBE_MODE_EN 1 // 1-StrobeMode, 0-PerformanceMode 524 525 // use for ComputeMemoryClockParamTable 526 typedef struct _COMPUTE_MEMORY_CLOCK_PARAM_PARAMETERS_V2_1 527 { 528 union 529 { 530 ULONG ulClock; 531 ATOM_S_MPLL_FB_DIVIDER ulFbDiv; //Output:UPPER_WORD=FB_DIV_INTEGER, LOWER_WORD=FB_DIV_FRAC shl (16-FB_FRACTION_BITS) 532 }; 533 UCHAR ucDllSpeed; //Output 534 UCHAR ucPostDiv; //Output 535 union{ 536 UCHAR ucInputFlag; //Input : ATOM_PLL_INPUT_FLAG_PLL_STROBE_MODE_EN: 1-StrobeMode, 0-PerformanceMode 537 UCHAR ucPllCntlFlag; //Output: 538 }; 539 UCHAR ucBWCntl; 540 }COMPUTE_MEMORY_CLOCK_PARAM_PARAMETERS_V2_1; 541 542 // definition of ucInputFlag 543 #define MPLL_INPUT_FLAG_STROBE_MODE_EN 0x01 544 // definition of ucPllCntlFlag 545 #define MPLL_CNTL_FLAG_VCO_MODE_MASK 0x03 546 #define MPLL_CNTL_FLAG_BYPASS_DQ_PLL 0x04 547 #define MPLL_CNTL_FLAG_QDR_ENABLE 0x08 548 #define MPLL_CNTL_FLAG_AD_HALF_RATE 0x10 549 550 //MPLL_CNTL_FLAG_BYPASS_AD_PLL has a wrong name, should be BYPASS_DQ_PLL 551 #define MPLL_CNTL_FLAG_BYPASS_AD_PLL 0x04 552 553 // use for ComputeMemoryClockParamTable 554 typedef struct _COMPUTE_MEMORY_CLOCK_PARAM_PARAMETERS_V2_2 555 { 556 COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V4 ulClock; 557 ULONG ulReserved; 558 }COMPUTE_MEMORY_CLOCK_PARAM_PARAMETERS_V2_2; 559 560 typedef struct _DYNAMICE_MEMORY_SETTINGS_PARAMETER 561 { 562 ATOM_COMPUTE_CLOCK_FREQ ulClock; 563 ULONG ulReserved[2]; 564 }DYNAMICE_MEMORY_SETTINGS_PARAMETER; 565 566 typedef struct _DYNAMICE_ENGINE_SETTINGS_PARAMETER 567 { 568 ATOM_COMPUTE_CLOCK_FREQ ulClock; 569 ULONG ulMemoryClock; 570 ULONG ulReserved; 571 }DYNAMICE_ENGINE_SETTINGS_PARAMETER; 572 573 /****************************************************************************/ 574 // Structures used by SetEngineClockTable 575 /****************************************************************************/ 576 typedef struct _SET_ENGINE_CLOCK_PARAMETERS 577 { 578 ULONG ulTargetEngineClock; //In 10Khz unit 579 }SET_ENGINE_CLOCK_PARAMETERS; 580 581 typedef struct _SET_ENGINE_CLOCK_PS_ALLOCATION 582 { 583 ULONG ulTargetEngineClock; //In 10Khz unit 584 COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_PS_ALLOCATION sReserved; 585 }SET_ENGINE_CLOCK_PS_ALLOCATION; 586 587 /****************************************************************************/ 588 // Structures used by SetMemoryClockTable 589 /****************************************************************************/ 590 typedef struct _SET_MEMORY_CLOCK_PARAMETERS 591 { 592 ULONG ulTargetMemoryClock; //In 10Khz unit 593 }SET_MEMORY_CLOCK_PARAMETERS; 594 595 typedef struct _SET_MEMORY_CLOCK_PS_ALLOCATION 596 { 597 ULONG ulTargetMemoryClock; //In 10Khz unit 598 COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_PS_ALLOCATION sReserved; 599 }SET_MEMORY_CLOCK_PS_ALLOCATION; 600 601 /****************************************************************************/ 602 // Structures used by ASIC_Init.ctb 603 /****************************************************************************/ 604 typedef struct _ASIC_INIT_PARAMETERS 605 { 606 ULONG ulDefaultEngineClock; //In 10Khz unit 607 ULONG ulDefaultMemoryClock; //In 10Khz unit 608 }ASIC_INIT_PARAMETERS; 609 610 typedef struct _ASIC_INIT_PS_ALLOCATION 611 { 612 ASIC_INIT_PARAMETERS sASICInitClocks; 613 SET_ENGINE_CLOCK_PS_ALLOCATION sReserved; //Caller doesn't need to init this structure 614 }ASIC_INIT_PS_ALLOCATION; 615 616 typedef struct _ASIC_INIT_CLOCK_PARAMETERS 617 { 618 ULONG ulClkFreqIn10Khz:24; 619 ULONG ucClkFlag:8; 620 }ASIC_INIT_CLOCK_PARAMETERS; 621 622 typedef struct _ASIC_INIT_PARAMETERS_V1_2 623 { 624 ASIC_INIT_CLOCK_PARAMETERS asSclkClock; //In 10Khz unit 625 ASIC_INIT_CLOCK_PARAMETERS asMemClock; //In 10Khz unit 626 }ASIC_INIT_PARAMETERS_V1_2; 627 628 typedef struct _ASIC_INIT_PS_ALLOCATION_V1_2 629 { 630 ASIC_INIT_PARAMETERS_V1_2 sASICInitClocks; 631 ULONG ulReserved[8]; 632 }ASIC_INIT_PS_ALLOCATION_V1_2; 633 634 /****************************************************************************/ 635 // Structure used by DynamicClockGatingTable.ctb 636 /****************************************************************************/ 637 typedef struct _DYNAMIC_CLOCK_GATING_PARAMETERS 638 { 639 UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE 640 UCHAR ucPadding[3]; 641 }DYNAMIC_CLOCK_GATING_PARAMETERS; 642 #define DYNAMIC_CLOCK_GATING_PS_ALLOCATION DYNAMIC_CLOCK_GATING_PARAMETERS 643 644 /****************************************************************************/ 645 // Structure used by EnableDispPowerGatingTable.ctb 646 /****************************************************************************/ 647 typedef struct _ENABLE_DISP_POWER_GATING_PARAMETERS_V2_1 648 { 649 UCHAR ucDispPipeId; // ATOM_CRTC1, ATOM_CRTC2, ... 650 UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE 651 UCHAR ucPadding[2]; 652 }ENABLE_DISP_POWER_GATING_PARAMETERS_V2_1; 653 654 typedef struct _ENABLE_DISP_POWER_GATING_PS_ALLOCATION 655 { 656 UCHAR ucDispPipeId; // ATOM_CRTC1, ATOM_CRTC2, ... 657 UCHAR ucEnable; // ATOM_ENABLE/ATOM_DISABLE/ATOM_INIT 658 UCHAR ucPadding[2]; 659 ULONG ulReserved[4]; 660 }ENABLE_DISP_POWER_GATING_PS_ALLOCATION; 661 662 /****************************************************************************/ 663 // Structure used by EnableASIC_StaticPwrMgtTable.ctb 664 /****************************************************************************/ 665 typedef struct _ENABLE_ASIC_STATIC_PWR_MGT_PARAMETERS 666 { 667 UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE 668 UCHAR ucPadding[3]; 669 }ENABLE_ASIC_STATIC_PWR_MGT_PARAMETERS; 670 #define ENABLE_ASIC_STATIC_PWR_MGT_PS_ALLOCATION ENABLE_ASIC_STATIC_PWR_MGT_PARAMETERS 671 672 /****************************************************************************/ 673 // Structures used by DAC_LoadDetectionTable.ctb 674 /****************************************************************************/ 675 typedef struct _DAC_LOAD_DETECTION_PARAMETERS 676 { 677 USHORT usDeviceID; //{ATOM_DEVICE_CRTx_SUPPORT,ATOM_DEVICE_TVx_SUPPORT,ATOM_DEVICE_CVx_SUPPORT} 678 UCHAR ucDacType; //{ATOM_DAC_A,ATOM_DAC_B, ATOM_EXT_DAC} 679 UCHAR ucMisc; //Valid only when table revision =1.3 and above 680 }DAC_LOAD_DETECTION_PARAMETERS; 681 682 // DAC_LOAD_DETECTION_PARAMETERS.ucMisc 683 #define DAC_LOAD_MISC_YPrPb 0x01 684 685 typedef struct _DAC_LOAD_DETECTION_PS_ALLOCATION 686 { 687 DAC_LOAD_DETECTION_PARAMETERS sDacload; 688 ULONG Reserved[2];// Don't set this one, allocation for EXT DAC 689 }DAC_LOAD_DETECTION_PS_ALLOCATION; 690 691 /****************************************************************************/ 692 // Structures used by DAC1EncoderControlTable.ctb and DAC2EncoderControlTable.ctb 693 /****************************************************************************/ 694 typedef struct _DAC_ENCODER_CONTROL_PARAMETERS 695 { 696 USHORT usPixelClock; // in 10KHz; for bios convenient 697 UCHAR ucDacStandard; // See definition of ATOM_DACx_xxx, For DEC3.0, bit 7 used as internal flag to indicate DAC2 (==1) or DAC1 (==0) 698 UCHAR ucAction; // 0: turn off encoder 699 // 1: setup and turn on encoder 700 // 7: ATOM_ENCODER_INIT Initialize DAC 701 }DAC_ENCODER_CONTROL_PARAMETERS; 702 703 #define DAC_ENCODER_CONTROL_PS_ALLOCATION DAC_ENCODER_CONTROL_PARAMETERS 704 705 /****************************************************************************/ 706 // Structures used by DIG1EncoderControlTable 707 // DIG2EncoderControlTable 708 // ExternalEncoderControlTable 709 /****************************************************************************/ 710 typedef struct _DIG_ENCODER_CONTROL_PARAMETERS 711 { 712 USHORT usPixelClock; // in 10KHz; for bios convenient 713 UCHAR ucConfig; 714 // [2] Link Select: 715 // =0: PHY linkA if bfLane<3 716 // =1: PHY linkB if bfLanes<3 717 // =0: PHY linkA+B if bfLanes=3 718 // [3] Transmitter Sel 719 // =0: UNIPHY or PCIEPHY 720 // =1: LVTMA 721 UCHAR ucAction; // =0: turn off encoder 722 // =1: turn on encoder 723 UCHAR ucEncoderMode; 724 // =0: DP encoder 725 // =1: LVDS encoder 726 // =2: DVI encoder 727 // =3: HDMI encoder 728 // =4: SDVO encoder 729 UCHAR ucLaneNum; // how many lanes to enable 730 UCHAR ucReserved[2]; 731 }DIG_ENCODER_CONTROL_PARAMETERS; 732 #define DIG_ENCODER_CONTROL_PS_ALLOCATION DIG_ENCODER_CONTROL_PARAMETERS 733 #define EXTERNAL_ENCODER_CONTROL_PARAMETER DIG_ENCODER_CONTROL_PARAMETERS 734 735 //ucConfig 736 #define ATOM_ENCODER_CONFIG_DPLINKRATE_MASK 0x01 737 #define ATOM_ENCODER_CONFIG_DPLINKRATE_1_62GHZ 0x00 738 #define ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ 0x01 739 #define ATOM_ENCODER_CONFIG_DPLINKRATE_5_40GHZ 0x02 740 #define ATOM_ENCODER_CONFIG_LINK_SEL_MASK 0x04 741 #define ATOM_ENCODER_CONFIG_LINKA 0x00 742 #define ATOM_ENCODER_CONFIG_LINKB 0x04 743 #define ATOM_ENCODER_CONFIG_LINKA_B ATOM_TRANSMITTER_CONFIG_LINKA 744 #define ATOM_ENCODER_CONFIG_LINKB_A ATOM_ENCODER_CONFIG_LINKB 745 #define ATOM_ENCODER_CONFIG_TRANSMITTER_SEL_MASK 0x08 746 #define ATOM_ENCODER_CONFIG_UNIPHY 0x00 747 #define ATOM_ENCODER_CONFIG_LVTMA 0x08 748 #define ATOM_ENCODER_CONFIG_TRANSMITTER1 0x00 749 #define ATOM_ENCODER_CONFIG_TRANSMITTER2 0x08 750 #define ATOM_ENCODER_CONFIG_DIGB 0x80 // VBIOS Internal use, outside SW should set this bit=0 751 // ucAction 752 // ATOM_ENABLE: Enable Encoder 753 // ATOM_DISABLE: Disable Encoder 754 755 //ucEncoderMode 756 #define ATOM_ENCODER_MODE_DP 0 757 #define ATOM_ENCODER_MODE_LVDS 1 758 #define ATOM_ENCODER_MODE_DVI 2 759 #define ATOM_ENCODER_MODE_HDMI 3 760 #define ATOM_ENCODER_MODE_SDVO 4 761 #define ATOM_ENCODER_MODE_DP_AUDIO 5 762 #define ATOM_ENCODER_MODE_TV 13 763 #define ATOM_ENCODER_MODE_CV 14 764 #define ATOM_ENCODER_MODE_CRT 15 765 #define ATOM_ENCODER_MODE_DVO 16 766 #define ATOM_ENCODER_MODE_DP_SST ATOM_ENCODER_MODE_DP // For DP1.2 767 #define ATOM_ENCODER_MODE_DP_MST 5 // For DP1.2 768 769 770 typedef struct _ATOM_DIG_ENCODER_CONFIG_V2 771 { 772 #if ATOM_BIG_ENDIAN 773 UCHAR ucReserved1:2; 774 UCHAR ucTransmitterSel:2; // =0: UniphyAB, =1: UniphyCD =2: UniphyEF 775 UCHAR ucLinkSel:1; // =0: linkA/C/E =1: linkB/D/F 776 UCHAR ucReserved:1; 777 UCHAR ucDPLinkRate:1; // =0: 1.62Ghz, =1: 2.7Ghz 778 #else 779 UCHAR ucDPLinkRate:1; // =0: 1.62Ghz, =1: 2.7Ghz 780 UCHAR ucReserved:1; 781 UCHAR ucLinkSel:1; // =0: linkA/C/E =1: linkB/D/F 782 UCHAR ucTransmitterSel:2; // =0: UniphyAB, =1: UniphyCD =2: UniphyEF 783 UCHAR ucReserved1:2; 784 #endif 785 }ATOM_DIG_ENCODER_CONFIG_V2; 786 787 788 typedef struct _DIG_ENCODER_CONTROL_PARAMETERS_V2 789 { 790 USHORT usPixelClock; // in 10KHz; for bios convenient 791 ATOM_DIG_ENCODER_CONFIG_V2 acConfig; 792 UCHAR ucAction; 793 UCHAR ucEncoderMode; 794 // =0: DP encoder 795 // =1: LVDS encoder 796 // =2: DVI encoder 797 // =3: HDMI encoder 798 // =4: SDVO encoder 799 UCHAR ucLaneNum; // how many lanes to enable 800 UCHAR ucStatus; // = DP_LINK_TRAINING_COMPLETE or DP_LINK_TRAINING_INCOMPLETE, only used by VBIOS with command ATOM_ENCODER_CMD_QUERY_DP_LINK_TRAINING_STATUS 801 UCHAR ucReserved; 802 }DIG_ENCODER_CONTROL_PARAMETERS_V2; 803 804 //ucConfig 805 #define ATOM_ENCODER_CONFIG_V2_DPLINKRATE_MASK 0x01 806 #define ATOM_ENCODER_CONFIG_V2_DPLINKRATE_1_62GHZ 0x00 807 #define ATOM_ENCODER_CONFIG_V2_DPLINKRATE_2_70GHZ 0x01 808 #define ATOM_ENCODER_CONFIG_V2_LINK_SEL_MASK 0x04 809 #define ATOM_ENCODER_CONFIG_V2_LINKA 0x00 810 #define ATOM_ENCODER_CONFIG_V2_LINKB 0x04 811 #define ATOM_ENCODER_CONFIG_V2_TRANSMITTER_SEL_MASK 0x18 812 #define ATOM_ENCODER_CONFIG_V2_TRANSMITTER1 0x00 813 #define ATOM_ENCODER_CONFIG_V2_TRANSMITTER2 0x08 814 #define ATOM_ENCODER_CONFIG_V2_TRANSMITTER3 0x10 815 816 // ucAction: 817 // ATOM_DISABLE 818 // ATOM_ENABLE 819 #define ATOM_ENCODER_CMD_DP_LINK_TRAINING_START 0x08 820 #define ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN1 0x09 821 #define ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN2 0x0a 822 #define ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN3 0x13 823 #define ATOM_ENCODER_CMD_DP_LINK_TRAINING_COMPLETE 0x0b 824 #define ATOM_ENCODER_CMD_DP_VIDEO_OFF 0x0c 825 #define ATOM_ENCODER_CMD_DP_VIDEO_ON 0x0d 826 #define ATOM_ENCODER_CMD_QUERY_DP_LINK_TRAINING_STATUS 0x0e 827 #define ATOM_ENCODER_CMD_SETUP 0x0f 828 #define ATOM_ENCODER_CMD_SETUP_PANEL_MODE 0x10 829 830 // ucStatus 831 #define ATOM_ENCODER_STATUS_LINK_TRAINING_COMPLETE 0x10 832 #define ATOM_ENCODER_STATUS_LINK_TRAINING_INCOMPLETE 0x00 833 834 //ucTableFormatRevision=1 835 //ucTableContentRevision=3 836 // Following function ENABLE sub-function will be used by driver when TMDS/HDMI/LVDS is used, disable function will be used by driver 837 typedef struct _ATOM_DIG_ENCODER_CONFIG_V3 838 { 839 #if ATOM_BIG_ENDIAN 840 UCHAR ucReserved1:1; 841 UCHAR ucDigSel:3; // =0/1/2/3/4/5: DIG0/1/2/3/4/5 (In register spec also referred as DIGA/B/C/D/E/F) 842 UCHAR ucReserved:3; 843 UCHAR ucDPLinkRate:1; // =0: 1.62Ghz, =1: 2.7Ghz 844 #else 845 UCHAR ucDPLinkRate:1; // =0: 1.62Ghz, =1: 2.7Ghz 846 UCHAR ucReserved:3; 847 UCHAR ucDigSel:3; // =0/1/2/3/4/5: DIG0/1/2/3/4/5 (In register spec also referred as DIGA/B/C/D/E/F) 848 UCHAR ucReserved1:1; 849 #endif 850 }ATOM_DIG_ENCODER_CONFIG_V3; 851 852 #define ATOM_ENCODER_CONFIG_V3_DPLINKRATE_MASK 0x03 853 #define ATOM_ENCODER_CONFIG_V3_DPLINKRATE_1_62GHZ 0x00 854 #define ATOM_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ 0x01 855 #define ATOM_ENCODER_CONFIG_V3_ENCODER_SEL 0x70 856 #define ATOM_ENCODER_CONFIG_V3_DIG0_ENCODER 0x00 857 #define ATOM_ENCODER_CONFIG_V3_DIG1_ENCODER 0x10 858 #define ATOM_ENCODER_CONFIG_V3_DIG2_ENCODER 0x20 859 #define ATOM_ENCODER_CONFIG_V3_DIG3_ENCODER 0x30 860 #define ATOM_ENCODER_CONFIG_V3_DIG4_ENCODER 0x40 861 #define ATOM_ENCODER_CONFIG_V3_DIG5_ENCODER 0x50 862 863 typedef struct _DIG_ENCODER_CONTROL_PARAMETERS_V3 864 { 865 USHORT usPixelClock; // in 10KHz; for bios convenient 866 ATOM_DIG_ENCODER_CONFIG_V3 acConfig; 867 UCHAR ucAction; 868 union{ 869 UCHAR ucEncoderMode; 870 // =0: DP encoder 871 // =1: LVDS encoder 872 // =2: DVI encoder 873 // =3: HDMI encoder 874 // =4: SDVO encoder 875 // =5: DP audio 876 UCHAR ucPanelMode; // only valid when ucAction == ATOM_ENCODER_CMD_SETUP_PANEL_MODE 877 // =0: external DP 878 // =0x1: internal DP2 879 // =0x11: internal DP1 for NutMeg/Travis DP translator 880 }; 881 UCHAR ucLaneNum; // how many lanes to enable 882 UCHAR ucBitPerColor; // only valid for DP mode when ucAction = ATOM_ENCODER_CMD_SETUP 883 UCHAR ucReserved; 884 }DIG_ENCODER_CONTROL_PARAMETERS_V3; 885 886 //ucTableFormatRevision=1 887 //ucTableContentRevision=4 888 // start from NI 889 // Following function ENABLE sub-function will be used by driver when TMDS/HDMI/LVDS is used, disable function will be used by driver 890 typedef struct _ATOM_DIG_ENCODER_CONFIG_V4 891 { 892 #if ATOM_BIG_ENDIAN 893 UCHAR ucReserved1:1; 894 UCHAR ucDigSel:3; // =0/1/2/3/4/5: DIG0/1/2/3/4/5 (In register spec also referred as DIGA/B/C/D/E/F) 895 UCHAR ucReserved:2; 896 UCHAR ucDPLinkRate:2; // =0: 1.62Ghz, =1: 2.7Ghz, 2=5.4Ghz <= Changed comparing to previous version 897 #else 898 UCHAR ucDPLinkRate:2; // =0: 1.62Ghz, =1: 2.7Ghz, 2=5.4Ghz <= Changed comparing to previous version 899 UCHAR ucReserved:2; 900 UCHAR ucDigSel:3; // =0/1/2/3/4/5: DIG0/1/2/3/4/5 (In register spec also referred as DIGA/B/C/D/E/F) 901 UCHAR ucReserved1:1; 902 #endif 903 }ATOM_DIG_ENCODER_CONFIG_V4; 904 905 #define ATOM_ENCODER_CONFIG_V4_DPLINKRATE_MASK 0x03 906 #define ATOM_ENCODER_CONFIG_V4_DPLINKRATE_1_62GHZ 0x00 907 #define ATOM_ENCODER_CONFIG_V4_DPLINKRATE_2_70GHZ 0x01 908 #define ATOM_ENCODER_CONFIG_V4_DPLINKRATE_5_40GHZ 0x02 909 #define ATOM_ENCODER_CONFIG_V4_DPLINKRATE_3_24GHZ 0x03 910 #define ATOM_ENCODER_CONFIG_V4_ENCODER_SEL 0x70 911 #define ATOM_ENCODER_CONFIG_V4_DIG0_ENCODER 0x00 912 #define ATOM_ENCODER_CONFIG_V4_DIG1_ENCODER 0x10 913 #define ATOM_ENCODER_CONFIG_V4_DIG2_ENCODER 0x20 914 #define ATOM_ENCODER_CONFIG_V4_DIG3_ENCODER 0x30 915 #define ATOM_ENCODER_CONFIG_V4_DIG4_ENCODER 0x40 916 #define ATOM_ENCODER_CONFIG_V4_DIG5_ENCODER 0x50 917 #define ATOM_ENCODER_CONFIG_V4_DIG6_ENCODER 0x60 918 919 typedef struct _DIG_ENCODER_CONTROL_PARAMETERS_V4 920 { 921 USHORT usPixelClock; // in 10KHz; for bios convenient 922 union{ 923 ATOM_DIG_ENCODER_CONFIG_V4 acConfig; 924 UCHAR ucConfig; 925 }; 926 UCHAR ucAction; 927 union{ 928 UCHAR ucEncoderMode; 929 // =0: DP encoder 930 // =1: LVDS encoder 931 // =2: DVI encoder 932 // =3: HDMI encoder 933 // =4: SDVO encoder 934 // =5: DP audio 935 UCHAR ucPanelMode; // only valid when ucAction == ATOM_ENCODER_CMD_SETUP_PANEL_MODE 936 // =0: external DP 937 // =0x1: internal DP2 938 // =0x11: internal DP1 for NutMeg/Travis DP translator 939 }; 940 UCHAR ucLaneNum; // how many lanes to enable 941 UCHAR ucBitPerColor; // only valid for DP mode when ucAction = ATOM_ENCODER_CMD_SETUP 942 UCHAR ucHPD_ID; // HPD ID (1-6). =0 means to skip HDP programming. New comparing to previous version 943 }DIG_ENCODER_CONTROL_PARAMETERS_V4; 944 945 // define ucBitPerColor: 946 #define PANEL_BPC_UNDEFINE 0x00 947 #define PANEL_6BIT_PER_COLOR 0x01 948 #define PANEL_8BIT_PER_COLOR 0x02 949 #define PANEL_10BIT_PER_COLOR 0x03 950 #define PANEL_12BIT_PER_COLOR 0x04 951 #define PANEL_16BIT_PER_COLOR 0x05 952 953 //define ucPanelMode 954 #define DP_PANEL_MODE_EXTERNAL_DP_MODE 0x00 955 #define DP_PANEL_MODE_INTERNAL_DP2_MODE 0x01 956 #define DP_PANEL_MODE_INTERNAL_DP1_MODE 0x11 957 958 /****************************************************************************/ 959 // Structures used by UNIPHYTransmitterControlTable 960 // LVTMATransmitterControlTable 961 // DVOOutputControlTable 962 /****************************************************************************/ 963 typedef struct _ATOM_DP_VS_MODE 964 { 965 UCHAR ucLaneSel; 966 UCHAR ucLaneSet; 967 }ATOM_DP_VS_MODE; 968 969 typedef struct _DIG_TRANSMITTER_CONTROL_PARAMETERS 970 { 971 union 972 { 973 USHORT usPixelClock; // in 10KHz; for bios convenient 974 USHORT usInitInfo; // when init uniphy,lower 8bit is used for connector type defined in objectid.h 975 ATOM_DP_VS_MODE asMode; // DP Voltage swing mode 976 }; 977 UCHAR ucConfig; 978 // [0]=0: 4 lane Link, 979 // =1: 8 lane Link ( Dual Links TMDS ) 980 // [1]=0: InCoherent mode 981 // =1: Coherent Mode 982 // [2] Link Select: 983 // =0: PHY linkA if bfLane<3 984 // =1: PHY linkB if bfLanes<3 985 // =0: PHY linkA+B if bfLanes=3 986 // [5:4]PCIE lane Sel 987 // =0: lane 0~3 or 0~7 988 // =1: lane 4~7 989 // =2: lane 8~11 or 8~15 990 // =3: lane 12~15 991 UCHAR ucAction; // =0: turn off encoder 992 // =1: turn on encoder 993 UCHAR ucReserved[4]; 994 }DIG_TRANSMITTER_CONTROL_PARAMETERS; 995 996 #define DIG_TRANSMITTER_CONTROL_PS_ALLOCATION DIG_TRANSMITTER_CONTROL_PARAMETERS 997 998 //ucInitInfo 999 #define ATOM_TRAMITTER_INITINFO_CONNECTOR_MASK 0x00ff 1000 1001 //ucConfig 1002 #define ATOM_TRANSMITTER_CONFIG_8LANE_LINK 0x01 1003 #define ATOM_TRANSMITTER_CONFIG_COHERENT 0x02 1004 #define ATOM_TRANSMITTER_CONFIG_LINK_SEL_MASK 0x04 1005 #define ATOM_TRANSMITTER_CONFIG_LINKA 0x00 1006 #define ATOM_TRANSMITTER_CONFIG_LINKB 0x04 1007 #define ATOM_TRANSMITTER_CONFIG_LINKA_B 0x00 1008 #define ATOM_TRANSMITTER_CONFIG_LINKB_A 0x04 1009 1010 #define ATOM_TRANSMITTER_CONFIG_ENCODER_SEL_MASK 0x08 // only used when ATOM_TRANSMITTER_ACTION_ENABLE 1011 #define ATOM_TRANSMITTER_CONFIG_DIG1_ENCODER 0x00 // only used when ATOM_TRANSMITTER_ACTION_ENABLE 1012 #define ATOM_TRANSMITTER_CONFIG_DIG2_ENCODER 0x08 // only used when ATOM_TRANSMITTER_ACTION_ENABLE 1013 1014 #define ATOM_TRANSMITTER_CONFIG_CLKSRC_MASK 0x30 1015 #define ATOM_TRANSMITTER_CONFIG_CLKSRC_PPLL 0x00 1016 #define ATOM_TRANSMITTER_CONFIG_CLKSRC_PCIE 0x20 1017 #define ATOM_TRANSMITTER_CONFIG_CLKSRC_XTALIN 0x30 1018 #define ATOM_TRANSMITTER_CONFIG_LANE_SEL_MASK 0xc0 1019 #define ATOM_TRANSMITTER_CONFIG_LANE_0_3 0x00 1020 #define ATOM_TRANSMITTER_CONFIG_LANE_0_7 0x00 1021 #define ATOM_TRANSMITTER_CONFIG_LANE_4_7 0x40 1022 #define ATOM_TRANSMITTER_CONFIG_LANE_8_11 0x80 1023 #define ATOM_TRANSMITTER_CONFIG_LANE_8_15 0x80 1024 #define ATOM_TRANSMITTER_CONFIG_LANE_12_15 0xc0 1025 1026 //ucAction 1027 #define ATOM_TRANSMITTER_ACTION_DISABLE 0 1028 #define ATOM_TRANSMITTER_ACTION_ENABLE 1 1029 #define ATOM_TRANSMITTER_ACTION_LCD_BLOFF 2 1030 #define ATOM_TRANSMITTER_ACTION_LCD_BLON 3 1031 #define ATOM_TRANSMITTER_ACTION_BL_BRIGHTNESS_CONTROL 4 1032 #define ATOM_TRANSMITTER_ACTION_LCD_SELFTEST_START 5 1033 #define ATOM_TRANSMITTER_ACTION_LCD_SELFTEST_STOP 6 1034 #define ATOM_TRANSMITTER_ACTION_INIT 7 1035 #define ATOM_TRANSMITTER_ACTION_DISABLE_OUTPUT 8 1036 #define ATOM_TRANSMITTER_ACTION_ENABLE_OUTPUT 9 1037 #define ATOM_TRANSMITTER_ACTION_SETUP 10 1038 #define ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH 11 1039 #define ATOM_TRANSMITTER_ACTION_POWER_ON 12 1040 #define ATOM_TRANSMITTER_ACTION_POWER_OFF 13 1041 1042 // Following are used for DigTransmitterControlTable ver1.2 1043 typedef struct _ATOM_DIG_TRANSMITTER_CONFIG_V2 1044 { 1045 #if ATOM_BIG_ENDIAN 1046 UCHAR ucTransmitterSel:2; //bit7:6: =0 Dig Transmitter 1 ( Uniphy AB ) 1047 // =1 Dig Transmitter 2 ( Uniphy CD ) 1048 // =2 Dig Transmitter 3 ( Uniphy EF ) 1049 UCHAR ucReserved:1; 1050 UCHAR fDPConnector:1; //bit4=0: DP connector =1: None DP connector 1051 UCHAR ucEncoderSel:1; //bit3=0: Data/Clk path source from DIGA( DIG inst0 ). =1: Data/clk path source from DIGB ( DIG inst1 ) 1052 UCHAR ucLinkSel:1; //bit2=0: Uniphy LINKA or C or E when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is A or C or E 1053 // =1: Uniphy LINKB or D or F when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is B or D or F 1054 1055 UCHAR fCoherentMode:1; //bit1=1: Coherent Mode ( for DVI/HDMI mode ) 1056 UCHAR fDualLinkConnector:1; //bit0=1: Dual Link DVI connector 1057 #else 1058 UCHAR fDualLinkConnector:1; //bit0=1: Dual Link DVI connector 1059 UCHAR fCoherentMode:1; //bit1=1: Coherent Mode ( for DVI/HDMI mode ) 1060 UCHAR ucLinkSel:1; //bit2=0: Uniphy LINKA or C or E when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is A or C or E 1061 // =1: Uniphy LINKB or D or F when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is B or D or F 1062 UCHAR ucEncoderSel:1; //bit3=0: Data/Clk path source from DIGA( DIG inst0 ). =1: Data/clk path source from DIGB ( DIG inst1 ) 1063 UCHAR fDPConnector:1; //bit4=0: DP connector =1: None DP connector 1064 UCHAR ucReserved:1; 1065 UCHAR ucTransmitterSel:2; //bit7:6: =0 Dig Transmitter 1 ( Uniphy AB ) 1066 // =1 Dig Transmitter 2 ( Uniphy CD ) 1067 // =2 Dig Transmitter 3 ( Uniphy EF ) 1068 #endif 1069 }ATOM_DIG_TRANSMITTER_CONFIG_V2; 1070 1071 //ucConfig 1072 //Bit0 1073 #define ATOM_TRANSMITTER_CONFIG_V2_DUAL_LINK_CONNECTOR 0x01 1074 1075 //Bit1 1076 #define ATOM_TRANSMITTER_CONFIG_V2_COHERENT 0x02 1077 1078 //Bit2 1079 #define ATOM_TRANSMITTER_CONFIG_V2_LINK_SEL_MASK 0x04 1080 #define ATOM_TRANSMITTER_CONFIG_V2_LINKA 0x00 1081 #define ATOM_TRANSMITTER_CONFIG_V2_LINKB 0x04 1082 1083 // Bit3 1084 #define ATOM_TRANSMITTER_CONFIG_V2_ENCODER_SEL_MASK 0x08 1085 #define ATOM_TRANSMITTER_CONFIG_V2_DIG1_ENCODER 0x00 // only used when ucAction == ATOM_TRANSMITTER_ACTION_ENABLE or ATOM_TRANSMITTER_ACTION_SETUP 1086 #define ATOM_TRANSMITTER_CONFIG_V2_DIG2_ENCODER 0x08 // only used when ucAction == ATOM_TRANSMITTER_ACTION_ENABLE or ATOM_TRANSMITTER_ACTION_SETUP 1087 1088 // Bit4 1089 #define ATOM_TRASMITTER_CONFIG_V2_DP_CONNECTOR 0x10 1090 1091 // Bit7:6 1092 #define ATOM_TRANSMITTER_CONFIG_V2_TRANSMITTER_SEL_MASK 0xC0 1093 #define ATOM_TRANSMITTER_CONFIG_V2_TRANSMITTER1 0x00 //AB 1094 #define ATOM_TRANSMITTER_CONFIG_V2_TRANSMITTER2 0x40 //CD 1095 #define ATOM_TRANSMITTER_CONFIG_V2_TRANSMITTER3 0x80 //EF 1096 1097 typedef struct _DIG_TRANSMITTER_CONTROL_PARAMETERS_V2 1098 { 1099 union 1100 { 1101 USHORT usPixelClock; // in 10KHz; for bios convenient 1102 USHORT usInitInfo; // when init uniphy,lower 8bit is used for connector type defined in objectid.h 1103 ATOM_DP_VS_MODE asMode; // DP Voltage swing mode 1104 }; 1105 ATOM_DIG_TRANSMITTER_CONFIG_V2 acConfig; 1106 UCHAR ucAction; // define as ATOM_TRANSMITER_ACTION_XXX 1107 UCHAR ucReserved[4]; 1108 }DIG_TRANSMITTER_CONTROL_PARAMETERS_V2; 1109 1110 typedef struct _ATOM_DIG_TRANSMITTER_CONFIG_V3 1111 { 1112 #if ATOM_BIG_ENDIAN 1113 UCHAR ucTransmitterSel:2; //bit7:6: =0 Dig Transmitter 1 ( Uniphy AB ) 1114 // =1 Dig Transmitter 2 ( Uniphy CD ) 1115 // =2 Dig Transmitter 3 ( Uniphy EF ) 1116 UCHAR ucRefClkSource:2; //bit5:4: PPLL1 =0, PPLL2=1, EXT_CLK=2 1117 UCHAR ucEncoderSel:1; //bit3=0: Data/Clk path source from DIGA/C/E. =1: Data/clk path source from DIGB/D/F 1118 UCHAR ucLinkSel:1; //bit2=0: Uniphy LINKA or C or E when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is A or C or E 1119 // =1: Uniphy LINKB or D or F when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is B or D or F 1120 UCHAR fCoherentMode:1; //bit1=1: Coherent Mode ( for DVI/HDMI mode ) 1121 UCHAR fDualLinkConnector:1; //bit0=1: Dual Link DVI connector 1122 #else 1123 UCHAR fDualLinkConnector:1; //bit0=1: Dual Link DVI connector 1124 UCHAR fCoherentMode:1; //bit1=1: Coherent Mode ( for DVI/HDMI mode ) 1125 UCHAR ucLinkSel:1; //bit2=0: Uniphy LINKA or C or E when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is A or C or E 1126 // =1: Uniphy LINKB or D or F when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is B or D or F 1127 UCHAR ucEncoderSel:1; //bit3=0: Data/Clk path source from DIGA/C/E. =1: Data/clk path source from DIGB/D/F 1128 UCHAR ucRefClkSource:2; //bit5:4: PPLL1 =0, PPLL2=1, EXT_CLK=2 1129 UCHAR ucTransmitterSel:2; //bit7:6: =0 Dig Transmitter 1 ( Uniphy AB ) 1130 // =1 Dig Transmitter 2 ( Uniphy CD ) 1131 // =2 Dig Transmitter 3 ( Uniphy EF ) 1132 #endif 1133 }ATOM_DIG_TRANSMITTER_CONFIG_V3; 1134 1135 1136 typedef struct _DIG_TRANSMITTER_CONTROL_PARAMETERS_V3 1137 { 1138 union 1139 { 1140 USHORT usPixelClock; // in 10KHz; for bios convenient 1141 USHORT usInitInfo; // when init uniphy,lower 8bit is used for connector type defined in objectid.h 1142 ATOM_DP_VS_MODE asMode; // DP Voltage swing mode 1143 }; 1144 ATOM_DIG_TRANSMITTER_CONFIG_V3 acConfig; 1145 UCHAR ucAction; // define as ATOM_TRANSMITER_ACTION_XXX 1146 UCHAR ucLaneNum; 1147 UCHAR ucReserved[3]; 1148 }DIG_TRANSMITTER_CONTROL_PARAMETERS_V3; 1149 1150 //ucConfig 1151 //Bit0 1152 #define ATOM_TRANSMITTER_CONFIG_V3_DUAL_LINK_CONNECTOR 0x01 1153 1154 //Bit1 1155 #define ATOM_TRANSMITTER_CONFIG_V3_COHERENT 0x02 1156 1157 //Bit2 1158 #define ATOM_TRANSMITTER_CONFIG_V3_LINK_SEL_MASK 0x04 1159 #define ATOM_TRANSMITTER_CONFIG_V3_LINKA 0x00 1160 #define ATOM_TRANSMITTER_CONFIG_V3_LINKB 0x04 1161 1162 // Bit3 1163 #define ATOM_TRANSMITTER_CONFIG_V3_ENCODER_SEL_MASK 0x08 1164 #define ATOM_TRANSMITTER_CONFIG_V3_DIG1_ENCODER 0x00 1165 #define ATOM_TRANSMITTER_CONFIG_V3_DIG2_ENCODER 0x08 1166 1167 // Bit5:4 1168 #define ATOM_TRASMITTER_CONFIG_V3_REFCLK_SEL_MASK 0x30 1169 #define ATOM_TRASMITTER_CONFIG_V3_P1PLL 0x00 1170 #define ATOM_TRASMITTER_CONFIG_V3_P2PLL 0x10 1171 #define ATOM_TRASMITTER_CONFIG_V3_REFCLK_SRC_EXT 0x20 1172 1173 // Bit7:6 1174 #define ATOM_TRANSMITTER_CONFIG_V3_TRANSMITTER_SEL_MASK 0xC0 1175 #define ATOM_TRANSMITTER_CONFIG_V3_TRANSMITTER1 0x00 //AB 1176 #define ATOM_TRANSMITTER_CONFIG_V3_TRANSMITTER2 0x40 //CD 1177 #define ATOM_TRANSMITTER_CONFIG_V3_TRANSMITTER3 0x80 //EF 1178 1179 1180 /****************************************************************************/ 1181 // Structures used by UNIPHYTransmitterControlTable V1.4 1182 // ASIC Families: NI 1183 // ucTableFormatRevision=1 1184 // ucTableContentRevision=4 1185 /****************************************************************************/ 1186 typedef struct _ATOM_DP_VS_MODE_V4 1187 { 1188 UCHAR ucLaneSel; 1189 union 1190 { 1191 UCHAR ucLaneSet; 1192 struct { 1193 #if ATOM_BIG_ENDIAN 1194 UCHAR ucPOST_CURSOR2:2; //Bit[7:6] Post Cursor2 Level <= New in V4 1195 UCHAR ucPRE_EMPHASIS:3; //Bit[5:3] Pre-emphasis Level 1196 UCHAR ucVOLTAGE_SWING:3; //Bit[2:0] Voltage Swing Level 1197 #else 1198 UCHAR ucVOLTAGE_SWING:3; //Bit[2:0] Voltage Swing Level 1199 UCHAR ucPRE_EMPHASIS:3; //Bit[5:3] Pre-emphasis Level 1200 UCHAR ucPOST_CURSOR2:2; //Bit[7:6] Post Cursor2 Level <= New in V4 1201 #endif 1202 }; 1203 }; 1204 }ATOM_DP_VS_MODE_V4; 1205 1206 typedef struct _ATOM_DIG_TRANSMITTER_CONFIG_V4 1207 { 1208 #if ATOM_BIG_ENDIAN 1209 UCHAR ucTransmitterSel:2; //bit7:6: =0 Dig Transmitter 1 ( Uniphy AB ) 1210 // =1 Dig Transmitter 2 ( Uniphy CD ) 1211 // =2 Dig Transmitter 3 ( Uniphy EF ) 1212 UCHAR ucRefClkSource:2; //bit5:4: PPLL1 =0, PPLL2=1, DCPLL=2, EXT_CLK=3 <= New 1213 UCHAR ucEncoderSel:1; //bit3=0: Data/Clk path source from DIGA/C/E. =1: Data/clk path source from DIGB/D/F 1214 UCHAR ucLinkSel:1; //bit2=0: Uniphy LINKA or C or E when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is A or C or E 1215 // =1: Uniphy LINKB or D or F when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is B or D or F 1216 UCHAR fCoherentMode:1; //bit1=1: Coherent Mode ( for DVI/HDMI mode ) 1217 UCHAR fDualLinkConnector:1; //bit0=1: Dual Link DVI connector 1218 #else 1219 UCHAR fDualLinkConnector:1; //bit0=1: Dual Link DVI connector 1220 UCHAR fCoherentMode:1; //bit1=1: Coherent Mode ( for DVI/HDMI mode ) 1221 UCHAR ucLinkSel:1; //bit2=0: Uniphy LINKA or C or E when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is A or C or E 1222 // =1: Uniphy LINKB or D or F when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is B or D or F 1223 UCHAR ucEncoderSel:1; //bit3=0: Data/Clk path source from DIGA/C/E. =1: Data/clk path source from DIGB/D/F 1224 UCHAR ucRefClkSource:2; //bit5:4: PPLL1 =0, PPLL2=1, DCPLL=2, EXT_CLK=3 <= New 1225 UCHAR ucTransmitterSel:2; //bit7:6: =0 Dig Transmitter 1 ( Uniphy AB ) 1226 // =1 Dig Transmitter 2 ( Uniphy CD ) 1227 // =2 Dig Transmitter 3 ( Uniphy EF ) 1228 #endif 1229 }ATOM_DIG_TRANSMITTER_CONFIG_V4; 1230 1231 typedef struct _DIG_TRANSMITTER_CONTROL_PARAMETERS_V4 1232 { 1233 union 1234 { 1235 USHORT usPixelClock; // in 10KHz; for bios convenient 1236 USHORT usInitInfo; // when init uniphy,lower 8bit is used for connector type defined in objectid.h 1237 ATOM_DP_VS_MODE_V4 asMode; // DP Voltage swing mode Redefined comparing to previous version 1238 }; 1239 union 1240 { 1241 ATOM_DIG_TRANSMITTER_CONFIG_V4 acConfig; 1242 UCHAR ucConfig; 1243 }; 1244 UCHAR ucAction; // define as ATOM_TRANSMITER_ACTION_XXX 1245 UCHAR ucLaneNum; 1246 UCHAR ucReserved[3]; 1247 }DIG_TRANSMITTER_CONTROL_PARAMETERS_V4; 1248 1249 //ucConfig 1250 //Bit0 1251 #define ATOM_TRANSMITTER_CONFIG_V4_DUAL_LINK_CONNECTOR 0x01 1252 //Bit1 1253 #define ATOM_TRANSMITTER_CONFIG_V4_COHERENT 0x02 1254 //Bit2 1255 #define ATOM_TRANSMITTER_CONFIG_V4_LINK_SEL_MASK 0x04 1256 #define ATOM_TRANSMITTER_CONFIG_V4_LINKA 0x00 1257 #define ATOM_TRANSMITTER_CONFIG_V4_LINKB 0x04 1258 // Bit3 1259 #define ATOM_TRANSMITTER_CONFIG_V4_ENCODER_SEL_MASK 0x08 1260 #define ATOM_TRANSMITTER_CONFIG_V4_DIG1_ENCODER 0x00 1261 #define ATOM_TRANSMITTER_CONFIG_V4_DIG2_ENCODER 0x08 1262 // Bit5:4 1263 #define ATOM_TRANSMITTER_CONFIG_V4_REFCLK_SEL_MASK 0x30 1264 #define ATOM_TRANSMITTER_CONFIG_V4_P1PLL 0x00 1265 #define ATOM_TRANSMITTER_CONFIG_V4_P2PLL 0x10 1266 #define ATOM_TRANSMITTER_CONFIG_V4_DCPLL 0x20 // New in _V4 1267 #define ATOM_TRANSMITTER_CONFIG_V4_REFCLK_SRC_EXT 0x30 // Changed comparing to V3 1268 // Bit7:6 1269 #define ATOM_TRANSMITTER_CONFIG_V4_TRANSMITTER_SEL_MASK 0xC0 1270 #define ATOM_TRANSMITTER_CONFIG_V4_TRANSMITTER1 0x00 //AB 1271 #define ATOM_TRANSMITTER_CONFIG_V4_TRANSMITTER2 0x40 //CD 1272 #define ATOM_TRANSMITTER_CONFIG_V4_TRANSMITTER3 0x80 //EF 1273 1274 1275 typedef struct _ATOM_DIG_TRANSMITTER_CONFIG_V5 1276 { 1277 #if ATOM_BIG_ENDIAN 1278 UCHAR ucReservd1:1; 1279 UCHAR ucHPDSel:3; 1280 UCHAR ucPhyClkSrcId:2; 1281 UCHAR ucCoherentMode:1; 1282 UCHAR ucReserved:1; 1283 #else 1284 UCHAR ucReserved:1; 1285 UCHAR ucCoherentMode:1; 1286 UCHAR ucPhyClkSrcId:2; 1287 UCHAR ucHPDSel:3; 1288 UCHAR ucReservd1:1; 1289 #endif 1290 }ATOM_DIG_TRANSMITTER_CONFIG_V5; 1291 1292 typedef struct _DIG_TRANSMITTER_CONTROL_PARAMETERS_V1_5 1293 { 1294 USHORT usSymClock; // Encoder Clock in 10kHz,(DP mode)= linkclock/10, (TMDS/LVDS/HDMI)= pixel clock, (HDMI deep color), =pixel clock * deep_color_ratio 1295 UCHAR ucPhyId; // 0=UNIPHYA, 1=UNIPHYB, 2=UNIPHYC, 3=UNIPHYD, 4= UNIPHYE 5=UNIPHYF 1296 UCHAR ucAction; // define as ATOM_TRANSMITER_ACTION_xxx 1297 UCHAR ucLaneNum; // indicate lane number 1-8 1298 UCHAR ucConnObjId; // Connector Object Id defined in ObjectId.h 1299 UCHAR ucDigMode; // indicate DIG mode 1300 union{ 1301 ATOM_DIG_TRANSMITTER_CONFIG_V5 asConfig; 1302 UCHAR ucConfig; 1303 }; 1304 UCHAR ucDigEncoderSel; // indicate DIG front end encoder 1305 UCHAR ucDPLaneSet; 1306 UCHAR ucReserved; 1307 UCHAR ucReserved1; 1308 }DIG_TRANSMITTER_CONTROL_PARAMETERS_V1_5; 1309 1310 //ucPhyId 1311 #define ATOM_PHY_ID_UNIPHYA 0 1312 #define ATOM_PHY_ID_UNIPHYB 1 1313 #define ATOM_PHY_ID_UNIPHYC 2 1314 #define ATOM_PHY_ID_UNIPHYD 3 1315 #define ATOM_PHY_ID_UNIPHYE 4 1316 #define ATOM_PHY_ID_UNIPHYF 5 1317 #define ATOM_PHY_ID_UNIPHYG 6 1318 1319 // ucDigEncoderSel 1320 #define ATOM_TRANMSITTER_V5__DIGA_SEL 0x01 1321 #define ATOM_TRANMSITTER_V5__DIGB_SEL 0x02 1322 #define ATOM_TRANMSITTER_V5__DIGC_SEL 0x04 1323 #define ATOM_TRANMSITTER_V5__DIGD_SEL 0x08 1324 #define ATOM_TRANMSITTER_V5__DIGE_SEL 0x10 1325 #define ATOM_TRANMSITTER_V5__DIGF_SEL 0x20 1326 #define ATOM_TRANMSITTER_V5__DIGG_SEL 0x40 1327 1328 // ucDigMode 1329 #define ATOM_TRANSMITTER_DIGMODE_V5_DP 0 1330 #define ATOM_TRANSMITTER_DIGMODE_V5_LVDS 1 1331 #define ATOM_TRANSMITTER_DIGMODE_V5_DVI 2 1332 #define ATOM_TRANSMITTER_DIGMODE_V5_HDMI 3 1333 #define ATOM_TRANSMITTER_DIGMODE_V5_SDVO 4 1334 #define ATOM_TRANSMITTER_DIGMODE_V5_DP_MST 5 1335 1336 // ucDPLaneSet 1337 #define DP_LANE_SET__0DB_0_4V 0x00 1338 #define DP_LANE_SET__0DB_0_6V 0x01 1339 #define DP_LANE_SET__0DB_0_8V 0x02 1340 #define DP_LANE_SET__0DB_1_2V 0x03 1341 #define DP_LANE_SET__3_5DB_0_4V 0x08 1342 #define DP_LANE_SET__3_5DB_0_6V 0x09 1343 #define DP_LANE_SET__3_5DB_0_8V 0x0a 1344 #define DP_LANE_SET__6DB_0_4V 0x10 1345 #define DP_LANE_SET__6DB_0_6V 0x11 1346 #define DP_LANE_SET__9_5DB_0_4V 0x18 1347 1348 // ATOM_DIG_TRANSMITTER_CONFIG_V5 asConfig; 1349 // Bit1 1350 #define ATOM_TRANSMITTER_CONFIG_V5_COHERENT 0x02 1351 1352 // Bit3:2 1353 #define ATOM_TRANSMITTER_CONFIG_V5_REFCLK_SEL_MASK 0x0c 1354 #define ATOM_TRANSMITTER_CONFIG_V5_REFCLK_SEL_SHIFT 0x02 1355 1356 #define ATOM_TRANSMITTER_CONFIG_V5_P1PLL 0x00 1357 #define ATOM_TRANSMITTER_CONFIG_V5_P2PLL 0x04 1358 #define ATOM_TRANSMITTER_CONFIG_V5_P0PLL 0x08 1359 #define ATOM_TRANSMITTER_CONFIG_V5_REFCLK_SRC_EXT 0x0c 1360 // Bit6:4 1361 #define ATOM_TRANSMITTER_CONFIG_V5_HPD_SEL_MASK 0x70 1362 #define ATOM_TRANSMITTER_CONFIG_V5_HPD_SEL_SHIFT 0x04 1363 1364 #define ATOM_TRANSMITTER_CONFIG_V5_NO_HPD_SEL 0x00 1365 #define ATOM_TRANSMITTER_CONFIG_V5_HPD1_SEL 0x10 1366 #define ATOM_TRANSMITTER_CONFIG_V5_HPD2_SEL 0x20 1367 #define ATOM_TRANSMITTER_CONFIG_V5_HPD3_SEL 0x30 1368 #define ATOM_TRANSMITTER_CONFIG_V5_HPD4_SEL 0x40 1369 #define ATOM_TRANSMITTER_CONFIG_V5_HPD5_SEL 0x50 1370 #define ATOM_TRANSMITTER_CONFIG_V5_HPD6_SEL 0x60 1371 1372 #define DIG_TRANSMITTER_CONTROL_PS_ALLOCATION_V1_5 DIG_TRANSMITTER_CONTROL_PARAMETERS_V1_5 1373 1374 1375 /****************************************************************************/ 1376 // Structures used by ExternalEncoderControlTable V1.3 1377 // ASIC Families: Evergreen, Llano, NI 1378 // ucTableFormatRevision=1 1379 // ucTableContentRevision=3 1380 /****************************************************************************/ 1381 1382 typedef struct _EXTERNAL_ENCODER_CONTROL_PARAMETERS_V3 1383 { 1384 union{ 1385 USHORT usPixelClock; // pixel clock in 10Khz, valid when ucAction=SETUP/ENABLE_OUTPUT 1386 USHORT usConnectorId; // connector id, valid when ucAction = INIT 1387 }; 1388 UCHAR ucConfig; // indicate which encoder, and DP link rate when ucAction = SETUP/ENABLE_OUTPUT 1389 UCHAR ucAction; // 1390 UCHAR ucEncoderMode; // encoder mode, only used when ucAction = SETUP/ENABLE_OUTPUT 1391 UCHAR ucLaneNum; // lane number, only used when ucAction = SETUP/ENABLE_OUTPUT 1392 UCHAR ucBitPerColor; // output bit per color, only valid when ucAction = SETUP/ENABLE_OUTPUT and ucEncodeMode= DP 1393 UCHAR ucReserved; 1394 }EXTERNAL_ENCODER_CONTROL_PARAMETERS_V3; 1395 1396 // ucAction 1397 #define EXTERANL_ENCODER_ACTION_V3_DISABLE_OUTPUT 0x00 1398 #define EXTERANL_ENCODER_ACTION_V3_ENABLE_OUTPUT 0x01 1399 #define EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT 0x07 1400 #define EXTERNAL_ENCODER_ACTION_V3_ENCODER_SETUP 0x0f 1401 #define EXTERNAL_ENCODER_ACTION_V3_ENCODER_BLANKING_OFF 0x10 1402 #define EXTERNAL_ENCODER_ACTION_V3_ENCODER_BLANKING 0x11 1403 #define EXTERNAL_ENCODER_ACTION_V3_DACLOAD_DETECTION 0x12 1404 #define EXTERNAL_ENCODER_ACTION_V3_DDC_SETUP 0x14 1405 1406 // ucConfig 1407 #define EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_MASK 0x03 1408 #define EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_1_62GHZ 0x00 1409 #define EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ 0x01 1410 #define EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_5_40GHZ 0x02 1411 #define EXTERNAL_ENCODER_CONFIG_V3_ENCODER_SEL_MAKS 0x70 1412 #define EXTERNAL_ENCODER_CONFIG_V3_ENCODER1 0x00 1413 #define EXTERNAL_ENCODER_CONFIG_V3_ENCODER2 0x10 1414 #define EXTERNAL_ENCODER_CONFIG_V3_ENCODER3 0x20 1415 1416 typedef struct _EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION_V3 1417 { 1418 EXTERNAL_ENCODER_CONTROL_PARAMETERS_V3 sExtEncoder; 1419 ULONG ulReserved[2]; 1420 }EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION_V3; 1421 1422 1423 /****************************************************************************/ 1424 // Structures used by DAC1OuputControlTable 1425 // DAC2OuputControlTable 1426 // LVTMAOutputControlTable (Before DEC30) 1427 // TMDSAOutputControlTable (Before DEC30) 1428 /****************************************************************************/ 1429 typedef struct _DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS 1430 { 1431 UCHAR ucAction; // Possible input:ATOM_ENABLE||ATOMDISABLE 1432 // When the display is LCD, in addition to above: 1433 // ATOM_LCD_BLOFF|| ATOM_LCD_BLON ||ATOM_LCD_BL_BRIGHTNESS_CONTROL||ATOM_LCD_SELFTEST_START|| 1434 // ATOM_LCD_SELFTEST_STOP 1435 1436 UCHAR aucPadding[3]; // padding to DWORD aligned 1437 }DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS; 1438 1439 #define DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS 1440 1441 1442 #define CRT1_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS 1443 #define CRT1_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION 1444 1445 #define CRT2_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS 1446 #define CRT2_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION 1447 1448 #define CV1_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS 1449 #define CV1_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION 1450 1451 #define TV1_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS 1452 #define TV1_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION 1453 1454 #define DFP1_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS 1455 #define DFP1_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION 1456 1457 #define DFP2_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS 1458 #define DFP2_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION 1459 1460 #define LCD1_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS 1461 #define LCD1_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION 1462 1463 #define DVO_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS 1464 #define DVO_OUTPUT_CONTROL_PS_ALLOCATION DIG_TRANSMITTER_CONTROL_PS_ALLOCATION 1465 #define DVO_OUTPUT_CONTROL_PARAMETERS_V3 DIG_TRANSMITTER_CONTROL_PARAMETERS 1466 1467 1468 typedef struct _LVTMA_OUTPUT_CONTROL_PARAMETERS_V2 1469 { 1470 // Possible value of ucAction 1471 // ATOM_TRANSMITTER_ACTION_LCD_BLON 1472 // ATOM_TRANSMITTER_ACTION_LCD_BLOFF 1473 // ATOM_TRANSMITTER_ACTION_BL_BRIGHTNESS_CONTROL 1474 // ATOM_TRANSMITTER_ACTION_POWER_ON 1475 // ATOM_TRANSMITTER_ACTION_POWER_OFF 1476 UCHAR ucAction; 1477 UCHAR ucBriLevel; 1478 USHORT usPwmFreq; // in unit of Hz, 200 means 200Hz 1479 }LVTMA_OUTPUT_CONTROL_PARAMETERS_V2; 1480 1481 1482 1483 /****************************************************************************/ 1484 // Structures used by BlankCRTCTable 1485 /****************************************************************************/ 1486 typedef struct _BLANK_CRTC_PARAMETERS 1487 { 1488 UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC2 1489 UCHAR ucBlanking; // ATOM_BLANKING or ATOM_BLANKINGOFF 1490 USHORT usBlackColorRCr; 1491 USHORT usBlackColorGY; 1492 USHORT usBlackColorBCb; 1493 }BLANK_CRTC_PARAMETERS; 1494 #define BLANK_CRTC_PS_ALLOCATION BLANK_CRTC_PARAMETERS 1495 1496 /****************************************************************************/ 1497 // Structures used by EnableCRTCTable 1498 // EnableCRTCMemReqTable 1499 // UpdateCRTC_DoubleBufferRegistersTable 1500 /****************************************************************************/ 1501 typedef struct _ENABLE_CRTC_PARAMETERS 1502 { 1503 UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC2 1504 UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE 1505 UCHAR ucPadding[2]; 1506 }ENABLE_CRTC_PARAMETERS; 1507 #define ENABLE_CRTC_PS_ALLOCATION ENABLE_CRTC_PARAMETERS 1508 1509 /****************************************************************************/ 1510 // Structures used by SetCRTC_OverScanTable 1511 /****************************************************************************/ 1512 typedef struct _SET_CRTC_OVERSCAN_PARAMETERS 1513 { 1514 USHORT usOverscanRight; // right 1515 USHORT usOverscanLeft; // left 1516 USHORT usOverscanBottom; // bottom 1517 USHORT usOverscanTop; // top 1518 UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC2 1519 UCHAR ucPadding[3]; 1520 }SET_CRTC_OVERSCAN_PARAMETERS; 1521 #define SET_CRTC_OVERSCAN_PS_ALLOCATION SET_CRTC_OVERSCAN_PARAMETERS 1522 1523 /****************************************************************************/ 1524 // Structures used by SetCRTC_ReplicationTable 1525 /****************************************************************************/ 1526 typedef struct _SET_CRTC_REPLICATION_PARAMETERS 1527 { 1528 UCHAR ucH_Replication; // horizontal replication 1529 UCHAR ucV_Replication; // vertical replication 1530 UCHAR usCRTC; // ATOM_CRTC1 or ATOM_CRTC2 1531 UCHAR ucPadding; 1532 }SET_CRTC_REPLICATION_PARAMETERS; 1533 #define SET_CRTC_REPLICATION_PS_ALLOCATION SET_CRTC_REPLICATION_PARAMETERS 1534 1535 /****************************************************************************/ 1536 // Structures used by SelectCRTC_SourceTable 1537 /****************************************************************************/ 1538 typedef struct _SELECT_CRTC_SOURCE_PARAMETERS 1539 { 1540 UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC2 1541 UCHAR ucDevice; // ATOM_DEVICE_CRT1|ATOM_DEVICE_CRT2|.... 1542 UCHAR ucPadding[2]; 1543 }SELECT_CRTC_SOURCE_PARAMETERS; 1544 #define SELECT_CRTC_SOURCE_PS_ALLOCATION SELECT_CRTC_SOURCE_PARAMETERS 1545 1546 typedef struct _SELECT_CRTC_SOURCE_PARAMETERS_V2 1547 { 1548 UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC2 1549 UCHAR ucEncoderID; // DAC1/DAC2/TVOUT/DIG1/DIG2/DVO 1550 UCHAR ucEncodeMode; // Encoding mode, only valid when using DIG1/DIG2/DVO 1551 UCHAR ucPadding; 1552 }SELECT_CRTC_SOURCE_PARAMETERS_V2; 1553 1554 //ucEncoderID 1555 //#define ASIC_INT_DAC1_ENCODER_ID 0x00 1556 //#define ASIC_INT_TV_ENCODER_ID 0x02 1557 //#define ASIC_INT_DIG1_ENCODER_ID 0x03 1558 //#define ASIC_INT_DAC2_ENCODER_ID 0x04 1559 //#define ASIC_EXT_TV_ENCODER_ID 0x06 1560 //#define ASIC_INT_DVO_ENCODER_ID 0x07 1561 //#define ASIC_INT_DIG2_ENCODER_ID 0x09 1562 //#define ASIC_EXT_DIG_ENCODER_ID 0x05 1563 1564 //ucEncodeMode 1565 //#define ATOM_ENCODER_MODE_DP 0 1566 //#define ATOM_ENCODER_MODE_LVDS 1 1567 //#define ATOM_ENCODER_MODE_DVI 2 1568 //#define ATOM_ENCODER_MODE_HDMI 3 1569 //#define ATOM_ENCODER_MODE_SDVO 4 1570 //#define ATOM_ENCODER_MODE_TV 13 1571 //#define ATOM_ENCODER_MODE_CV 14 1572 //#define ATOM_ENCODER_MODE_CRT 15 1573 1574 1575 typedef struct _SELECT_CRTC_SOURCE_PARAMETERS_V3 1576 { 1577 UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC2 1578 UCHAR ucEncoderID; // DAC1/DAC2/TVOUT/DIG1/DIG2/DVO 1579 UCHAR ucEncodeMode; // Encoding mode, only valid when using DIG1/DIG2/DVO 1580 UCHAR ucDstBpc; // PANEL_6/8/10/12BIT_PER_COLOR 1581 }SELECT_CRTC_SOURCE_PARAMETERS_V3; 1582 1583 1584 /****************************************************************************/ 1585 // Structures used by SetPixelClockTable 1586 // GetPixelClockTable 1587 /****************************************************************************/ 1588 //Major revision=1., Minor revision=1 1589 typedef struct _PIXEL_CLOCK_PARAMETERS 1590 { 1591 USHORT usPixelClock; // in 10kHz unit; for bios convenient = (RefClk*FB_Div)/(Ref_Div*Post_Div) 1592 // 0 means disable PPLL 1593 USHORT usRefDiv; // Reference divider 1594 USHORT usFbDiv; // feedback divider 1595 UCHAR ucPostDiv; // post divider 1596 UCHAR ucFracFbDiv; // fractional feedback divider 1597 UCHAR ucPpll; // ATOM_PPLL1 or ATOM_PPL2 1598 UCHAR ucRefDivSrc; // ATOM_PJITTER or ATO_NONPJITTER 1599 UCHAR ucCRTC; // Which CRTC uses this Ppll 1600 UCHAR ucPadding; 1601 }PIXEL_CLOCK_PARAMETERS; 1602 1603 //Major revision=1., Minor revision=2, add ucMiscIfno 1604 //ucMiscInfo: 1605 #define MISC_FORCE_REPROG_PIXEL_CLOCK 0x1 1606 #define MISC_DEVICE_INDEX_MASK 0xF0 1607 #define MISC_DEVICE_INDEX_SHIFT 4 1608 1609 typedef struct _PIXEL_CLOCK_PARAMETERS_V2 1610 { 1611 USHORT usPixelClock; // in 10kHz unit; for bios convenient = (RefClk*FB_Div)/(Ref_Div*Post_Div) 1612 // 0 means disable PPLL 1613 USHORT usRefDiv; // Reference divider 1614 USHORT usFbDiv; // feedback divider 1615 UCHAR ucPostDiv; // post divider 1616 UCHAR ucFracFbDiv; // fractional feedback divider 1617 UCHAR ucPpll; // ATOM_PPLL1 or ATOM_PPL2 1618 UCHAR ucRefDivSrc; // ATOM_PJITTER or ATO_NONPJITTER 1619 UCHAR ucCRTC; // Which CRTC uses this Ppll 1620 UCHAR ucMiscInfo; // Different bits for different purpose, bit [7:4] as device index, bit[0]=Force prog 1621 }PIXEL_CLOCK_PARAMETERS_V2; 1622 1623 //Major revision=1., Minor revision=3, structure/definition change 1624 //ucEncoderMode: 1625 //ATOM_ENCODER_MODE_DP 1626 //ATOM_ENOCDER_MODE_LVDS 1627 //ATOM_ENOCDER_MODE_DVI 1628 //ATOM_ENOCDER_MODE_HDMI 1629 //ATOM_ENOCDER_MODE_SDVO 1630 //ATOM_ENCODER_MODE_TV 13 1631 //ATOM_ENCODER_MODE_CV 14 1632 //ATOM_ENCODER_MODE_CRT 15 1633 1634 //ucDVOConfig 1635 //#define DVO_ENCODER_CONFIG_RATE_SEL 0x01 1636 //#define DVO_ENCODER_CONFIG_DDR_SPEED 0x00 1637 //#define DVO_ENCODER_CONFIG_SDR_SPEED 0x01 1638 //#define DVO_ENCODER_CONFIG_OUTPUT_SEL 0x0c 1639 //#define DVO_ENCODER_CONFIG_LOW12BIT 0x00 1640 //#define DVO_ENCODER_CONFIG_UPPER12BIT 0x04 1641 //#define DVO_ENCODER_CONFIG_24BIT 0x08 1642 1643 //ucMiscInfo: also changed, see below 1644 #define PIXEL_CLOCK_MISC_FORCE_PROG_PPLL 0x01 1645 #define PIXEL_CLOCK_MISC_VGA_MODE 0x02 1646 #define PIXEL_CLOCK_MISC_CRTC_SEL_MASK 0x04 1647 #define PIXEL_CLOCK_MISC_CRTC_SEL_CRTC1 0x00 1648 #define PIXEL_CLOCK_MISC_CRTC_SEL_CRTC2 0x04 1649 #define PIXEL_CLOCK_MISC_USE_ENGINE_FOR_DISPCLK 0x08 1650 #define PIXEL_CLOCK_MISC_REF_DIV_SRC 0x10 1651 // V1.4 for RoadRunner 1652 #define PIXEL_CLOCK_V4_MISC_SS_ENABLE 0x10 1653 #define PIXEL_CLOCK_V4_MISC_COHERENT_MODE 0x20 1654 1655 1656 typedef struct _PIXEL_CLOCK_PARAMETERS_V3 1657 { 1658 USHORT usPixelClock; // in 10kHz unit; for bios convenient = (RefClk*FB_Div)/(Ref_Div*Post_Div) 1659 // 0 means disable PPLL. For VGA PPLL,make sure this value is not 0. 1660 USHORT usRefDiv; // Reference divider 1661 USHORT usFbDiv; // feedback divider 1662 UCHAR ucPostDiv; // post divider 1663 UCHAR ucFracFbDiv; // fractional feedback divider 1664 UCHAR ucPpll; // ATOM_PPLL1 or ATOM_PPL2 1665 UCHAR ucTransmitterId; // graphic encoder id defined in objectId.h 1666 union 1667 { 1668 UCHAR ucEncoderMode; // encoder type defined as ATOM_ENCODER_MODE_DP/DVI/HDMI/ 1669 UCHAR ucDVOConfig; // when use DVO, need to know SDR/DDR, 12bit or 24bit 1670 }; 1671 UCHAR ucMiscInfo; // bit[0]=Force program, bit[1]= set pclk for VGA, b[2]= CRTC sel 1672 // bit[3]=0:use PPLL for dispclk source, =1: use engine clock for dispclock source 1673 // bit[4]=0:use XTALIN as the source of reference divider,=1 use the pre-defined clock as the source of reference divider 1674 }PIXEL_CLOCK_PARAMETERS_V3; 1675 1676 #define PIXEL_CLOCK_PARAMETERS_LAST PIXEL_CLOCK_PARAMETERS_V2 1677 #define GET_PIXEL_CLOCK_PS_ALLOCATION PIXEL_CLOCK_PARAMETERS_LAST 1678 1679 1680 typedef struct _PIXEL_CLOCK_PARAMETERS_V5 1681 { 1682 UCHAR ucCRTC; // ATOM_CRTC1~6, indicate the CRTC controller to 1683 // drive the pixel clock. not used for DCPLL case. 1684 union{ 1685 UCHAR ucReserved; 1686 UCHAR ucFracFbDiv; // [gphan] temporary to prevent build problem. remove it after driver code is changed. 1687 }; 1688 USHORT usPixelClock; // target the pixel clock to drive the CRTC timing 1689 // 0 means disable PPLL/DCPLL. 1690 USHORT usFbDiv; // feedback divider integer part. 1691 UCHAR ucPostDiv; // post divider. 1692 UCHAR ucRefDiv; // Reference divider 1693 UCHAR ucPpll; // ATOM_PPLL1/ATOM_PPLL2/ATOM_DCPLL 1694 UCHAR ucTransmitterID; // ASIC encoder id defined in objectId.h, 1695 // indicate which graphic encoder will be used. 1696 UCHAR ucEncoderMode; // Encoder mode: 1697 UCHAR ucMiscInfo; // bit[0]= Force program PPLL 1698 // bit[1]= when VGA timing is used. 1699 // bit[3:2]= HDMI panel bit depth: =0: 24bpp =1:30bpp, =2:32bpp 1700 // bit[4]= RefClock source for PPLL. 1701 // =0: XTLAIN( default mode ) 1702 // =1: other external clock source, which is pre-defined 1703 // by VBIOS depend on the feature required. 1704 // bit[7:5]: reserved. 1705 ULONG ulFbDivDecFrac; // 20 bit feedback divider decimal fraction part, range from 1~999999 ( 0.000001 to 0.999999 ) 1706 1707 }PIXEL_CLOCK_PARAMETERS_V5; 1708 1709 #define PIXEL_CLOCK_V5_MISC_FORCE_PROG_PPLL 0x01 1710 #define PIXEL_CLOCK_V5_MISC_VGA_MODE 0x02 1711 #define PIXEL_CLOCK_V5_MISC_HDMI_BPP_MASK 0x0c 1712 #define PIXEL_CLOCK_V5_MISC_HDMI_24BPP 0x00 1713 #define PIXEL_CLOCK_V5_MISC_HDMI_30BPP 0x04 1714 #define PIXEL_CLOCK_V5_MISC_HDMI_32BPP 0x08 1715 #define PIXEL_CLOCK_V5_MISC_REF_DIV_SRC 0x10 1716 1717 typedef struct _CRTC_PIXEL_CLOCK_FREQ 1718 { 1719 #if ATOM_BIG_ENDIAN 1720 ULONG ucCRTC:8; // ATOM_CRTC1~6, indicate the CRTC controller to 1721 // drive the pixel clock. not used for DCPLL case. 1722 ULONG ulPixelClock:24; // target the pixel clock to drive the CRTC timing. 1723 // 0 means disable PPLL/DCPLL. Expanded to 24 bits comparing to previous version. 1724 #else 1725 ULONG ulPixelClock:24; // target the pixel clock to drive the CRTC timing. 1726 // 0 means disable PPLL/DCPLL. Expanded to 24 bits comparing to previous version. 1727 ULONG ucCRTC:8; // ATOM_CRTC1~6, indicate the CRTC controller to 1728 // drive the pixel clock. not used for DCPLL case. 1729 #endif 1730 }CRTC_PIXEL_CLOCK_FREQ; 1731 1732 typedef struct _PIXEL_CLOCK_PARAMETERS_V6 1733 { 1734 union{ 1735 CRTC_PIXEL_CLOCK_FREQ ulCrtcPclkFreq; // pixel clock and CRTC id frequency 1736 ULONG ulDispEngClkFreq; // dispclk frequency 1737 }; 1738 USHORT usFbDiv; // feedback divider integer part. 1739 UCHAR ucPostDiv; // post divider. 1740 UCHAR ucRefDiv; // Reference divider 1741 UCHAR ucPpll; // ATOM_PPLL1/ATOM_PPLL2/ATOM_DCPLL 1742 UCHAR ucTransmitterID; // ASIC encoder id defined in objectId.h, 1743 // indicate which graphic encoder will be used. 1744 UCHAR ucEncoderMode; // Encoder mode: 1745 UCHAR ucMiscInfo; // bit[0]= Force program PPLL 1746 // bit[1]= when VGA timing is used. 1747 // bit[3:2]= HDMI panel bit depth: =0: 24bpp =1:30bpp, =2:32bpp 1748 // bit[4]= RefClock source for PPLL. 1749 // =0: XTLAIN( default mode ) 1750 // =1: other external clock source, which is pre-defined 1751 // by VBIOS depend on the feature required. 1752 // bit[7:5]: reserved. 1753 ULONG ulFbDivDecFrac; // 20 bit feedback divider decimal fraction part, range from 1~999999 ( 0.000001 to 0.999999 ) 1754 1755 }PIXEL_CLOCK_PARAMETERS_V6; 1756 1757 #define PIXEL_CLOCK_V6_MISC_FORCE_PROG_PPLL 0x01 1758 #define PIXEL_CLOCK_V6_MISC_VGA_MODE 0x02 1759 #define PIXEL_CLOCK_V6_MISC_HDMI_BPP_MASK 0x0c 1760 #define PIXEL_CLOCK_V6_MISC_HDMI_24BPP 0x00 1761 #define PIXEL_CLOCK_V6_MISC_HDMI_36BPP 0x04 1762 #define PIXEL_CLOCK_V6_MISC_HDMI_36BPP_V6 0x08 //for V6, the correct defintion for 36bpp should be 2 for 36bpp(2:1) 1763 #define PIXEL_CLOCK_V6_MISC_HDMI_30BPP 0x08 1764 #define PIXEL_CLOCK_V6_MISC_HDMI_30BPP_V6 0x04 //for V6, the correct defintion for 30bpp should be 1 for 36bpp(5:4) 1765 #define PIXEL_CLOCK_V6_MISC_HDMI_48BPP 0x0c 1766 #define PIXEL_CLOCK_V6_MISC_REF_DIV_SRC 0x10 1767 #define PIXEL_CLOCK_V6_MISC_GEN_DPREFCLK 0x40 1768 #define PIXEL_CLOCK_V6_MISC_DPREFCLK_BYPASS 0x40 1769 1770 typedef struct _GET_DISP_PLL_STATUS_INPUT_PARAMETERS_V2 1771 { 1772 PIXEL_CLOCK_PARAMETERS_V3 sDispClkInput; 1773 }GET_DISP_PLL_STATUS_INPUT_PARAMETERS_V2; 1774 1775 typedef struct _GET_DISP_PLL_STATUS_OUTPUT_PARAMETERS_V2 1776 { 1777 UCHAR ucStatus; 1778 UCHAR ucRefDivSrc; // =1: reference clock source from XTALIN, =0: source from PCIE ref clock 1779 UCHAR ucReserved[2]; 1780 }GET_DISP_PLL_STATUS_OUTPUT_PARAMETERS_V2; 1781 1782 typedef struct _GET_DISP_PLL_STATUS_INPUT_PARAMETERS_V3 1783 { 1784 PIXEL_CLOCK_PARAMETERS_V5 sDispClkInput; 1785 }GET_DISP_PLL_STATUS_INPUT_PARAMETERS_V3; 1786 1787 1788 /****************************************************************************/ 1789 // Structures used by AdjustDisplayPllTable 1790 /****************************************************************************/ 1791 typedef struct _ADJUST_DISPLAY_PLL_PARAMETERS 1792 { 1793 USHORT usPixelClock; 1794 UCHAR ucTransmitterID; 1795 UCHAR ucEncodeMode; 1796 union 1797 { 1798 UCHAR ucDVOConfig; //if DVO, need passing link rate and output 12bitlow or 24bit 1799 UCHAR ucConfig; //if none DVO, not defined yet 1800 }; 1801 UCHAR ucReserved[3]; 1802 }ADJUST_DISPLAY_PLL_PARAMETERS; 1803 1804 #define ADJUST_DISPLAY_CONFIG_SS_ENABLE 0x10 1805 #define ADJUST_DISPLAY_PLL_PS_ALLOCATION ADJUST_DISPLAY_PLL_PARAMETERS 1806 1807 typedef struct _ADJUST_DISPLAY_PLL_INPUT_PARAMETERS_V3 1808 { 1809 USHORT usPixelClock; // target pixel clock 1810 UCHAR ucTransmitterID; // GPU transmitter id defined in objectid.h 1811 UCHAR ucEncodeMode; // encoder mode: CRT, LVDS, DP, TMDS or HDMI 1812 UCHAR ucDispPllConfig; // display pll configure parameter defined as following DISPPLL_CONFIG_XXXX 1813 UCHAR ucExtTransmitterID; // external encoder id. 1814 UCHAR ucReserved[2]; 1815 }ADJUST_DISPLAY_PLL_INPUT_PARAMETERS_V3; 1816 1817 // usDispPllConfig v1.2 for RoadRunner 1818 #define DISPPLL_CONFIG_DVO_RATE_SEL 0x0001 // need only when ucTransmitterID = DVO 1819 #define DISPPLL_CONFIG_DVO_DDR_SPEED 0x0000 // need only when ucTransmitterID = DVO 1820 #define DISPPLL_CONFIG_DVO_SDR_SPEED 0x0001 // need only when ucTransmitterID = DVO 1821 #define DISPPLL_CONFIG_DVO_OUTPUT_SEL 0x000c // need only when ucTransmitterID = DVO 1822 #define DISPPLL_CONFIG_DVO_LOW12BIT 0x0000 // need only when ucTransmitterID = DVO 1823 #define DISPPLL_CONFIG_DVO_UPPER12BIT 0x0004 // need only when ucTransmitterID = DVO 1824 #define DISPPLL_CONFIG_DVO_24BIT 0x0008 // need only when ucTransmitterID = DVO 1825 #define DISPPLL_CONFIG_SS_ENABLE 0x0010 // Only used when ucEncoderMode = DP or LVDS 1826 #define DISPPLL_CONFIG_COHERENT_MODE 0x0020 // Only used when ucEncoderMode = TMDS or HDMI 1827 #define DISPPLL_CONFIG_DUAL_LINK 0x0040 // Only used when ucEncoderMode = TMDS or LVDS 1828 1829 1830 typedef struct _ADJUST_DISPLAY_PLL_OUTPUT_PARAMETERS_V3 1831 { 1832 ULONG ulDispPllFreq; // return display PPLL freq which is used to generate the pixclock, and related idclk, symclk etc 1833 UCHAR ucRefDiv; // if it is none-zero, it is used to be calculated the other ppll parameter fb_divider and post_div ( if it is not given ) 1834 UCHAR ucPostDiv; // if it is none-zero, it is used to be calculated the other ppll parameter fb_divider 1835 UCHAR ucReserved[2]; 1836 }ADJUST_DISPLAY_PLL_OUTPUT_PARAMETERS_V3; 1837 1838 typedef struct _ADJUST_DISPLAY_PLL_PS_ALLOCATION_V3 1839 { 1840 union 1841 { 1842 ADJUST_DISPLAY_PLL_INPUT_PARAMETERS_V3 sInput; 1843 ADJUST_DISPLAY_PLL_OUTPUT_PARAMETERS_V3 sOutput; 1844 }; 1845 } ADJUST_DISPLAY_PLL_PS_ALLOCATION_V3; 1846 1847 /****************************************************************************/ 1848 // Structures used by EnableYUVTable 1849 /****************************************************************************/ 1850 typedef struct _ENABLE_YUV_PARAMETERS 1851 { 1852 UCHAR ucEnable; // ATOM_ENABLE:Enable YUV or ATOM_DISABLE:Disable YUV (RGB) 1853 UCHAR ucCRTC; // Which CRTC needs this YUV or RGB format 1854 UCHAR ucPadding[2]; 1855 }ENABLE_YUV_PARAMETERS; 1856 #define ENABLE_YUV_PS_ALLOCATION ENABLE_YUV_PARAMETERS 1857 1858 /****************************************************************************/ 1859 // Structures used by GetMemoryClockTable 1860 /****************************************************************************/ 1861 typedef struct _GET_MEMORY_CLOCK_PARAMETERS 1862 { 1863 ULONG ulReturnMemoryClock; // current memory speed in 10KHz unit 1864 } GET_MEMORY_CLOCK_PARAMETERS; 1865 #define GET_MEMORY_CLOCK_PS_ALLOCATION GET_MEMORY_CLOCK_PARAMETERS 1866 1867 /****************************************************************************/ 1868 // Structures used by GetEngineClockTable 1869 /****************************************************************************/ 1870 typedef struct _GET_ENGINE_CLOCK_PARAMETERS 1871 { 1872 ULONG ulReturnEngineClock; // current engine speed in 10KHz unit 1873 } GET_ENGINE_CLOCK_PARAMETERS; 1874 #define GET_ENGINE_CLOCK_PS_ALLOCATION GET_ENGINE_CLOCK_PARAMETERS 1875 1876 /****************************************************************************/ 1877 // Following Structures and constant may be obsolete 1878 /****************************************************************************/ 1879 //Maxium 8 bytes,the data read in will be placed in the parameter space. 1880 //Read operaion successeful when the paramter space is non-zero, otherwise read operation failed 1881 typedef struct _READ_EDID_FROM_HW_I2C_DATA_PARAMETERS 1882 { 1883 USHORT usPrescale; //Ratio between Engine clock and I2C clock 1884 USHORT usVRAMAddress; //Adress in Frame Buffer where to pace raw EDID 1885 USHORT usStatus; //When use output: lower byte EDID checksum, high byte hardware status 1886 //WHen use input: lower byte as 'byte to read':currently limited to 128byte or 1byte 1887 UCHAR ucSlaveAddr; //Read from which slave 1888 UCHAR ucLineNumber; //Read from which HW assisted line 1889 }READ_EDID_FROM_HW_I2C_DATA_PARAMETERS; 1890 #define READ_EDID_FROM_HW_I2C_DATA_PS_ALLOCATION READ_EDID_FROM_HW_I2C_DATA_PARAMETERS 1891 1892 1893 #define ATOM_WRITE_I2C_FORMAT_PSOFFSET_PSDATABYTE 0 1894 #define ATOM_WRITE_I2C_FORMAT_PSOFFSET_PSTWODATABYTES 1 1895 #define ATOM_WRITE_I2C_FORMAT_PSCOUNTER_PSOFFSET_IDDATABLOCK 2 1896 #define ATOM_WRITE_I2C_FORMAT_PSCOUNTER_IDOFFSET_PLUS_IDDATABLOCK 3 1897 #define ATOM_WRITE_I2C_FORMAT_IDCOUNTER_IDOFFSET_IDDATABLOCK 4 1898 1899 typedef struct _WRITE_ONE_BYTE_HW_I2C_DATA_PARAMETERS 1900 { 1901 USHORT usPrescale; //Ratio between Engine clock and I2C clock 1902 USHORT usByteOffset; //Write to which byte 1903 //Upper portion of usByteOffset is Format of data 1904 //1bytePS+offsetPS 1905 //2bytesPS+offsetPS 1906 //blockID+offsetPS 1907 //blockID+offsetID 1908 //blockID+counterID+offsetID 1909 UCHAR ucData; //PS data1 1910 UCHAR ucStatus; //Status byte 1=success, 2=failure, Also is used as PS data2 1911 UCHAR ucSlaveAddr; //Write to which slave 1912 UCHAR ucLineNumber; //Write from which HW assisted line 1913 }WRITE_ONE_BYTE_HW_I2C_DATA_PARAMETERS; 1914 1915 #define WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION WRITE_ONE_BYTE_HW_I2C_DATA_PARAMETERS 1916 1917 typedef struct _SET_UP_HW_I2C_DATA_PARAMETERS 1918 { 1919 USHORT usPrescale; //Ratio between Engine clock and I2C clock 1920 UCHAR ucSlaveAddr; //Write to which slave 1921 UCHAR ucLineNumber; //Write from which HW assisted line 1922 }SET_UP_HW_I2C_DATA_PARAMETERS; 1923 1924 /**************************************************************************/ 1925 #define SPEED_FAN_CONTROL_PS_ALLOCATION WRITE_ONE_BYTE_HW_I2C_DATA_PARAMETERS 1926 1927 1928 /****************************************************************************/ 1929 // Structures used by PowerConnectorDetectionTable 1930 /****************************************************************************/ 1931 typedef struct _POWER_CONNECTOR_DETECTION_PARAMETERS 1932 { 1933 UCHAR ucPowerConnectorStatus; //Used for return value 0: detected, 1:not detected 1934 UCHAR ucPwrBehaviorId; 1935 USHORT usPwrBudget; //how much power currently boot to in unit of watt 1936 }POWER_CONNECTOR_DETECTION_PARAMETERS; 1937 1938 typedef struct POWER_CONNECTOR_DETECTION_PS_ALLOCATION 1939 { 1940 UCHAR ucPowerConnectorStatus; //Used for return value 0: detected, 1:not detected 1941 UCHAR ucReserved; 1942 USHORT usPwrBudget; //how much power currently boot to in unit of watt 1943 WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved; 1944 }POWER_CONNECTOR_DETECTION_PS_ALLOCATION; 1945 1946 1947 /****************************LVDS SS Command Table Definitions**********************/ 1948 1949 /****************************************************************************/ 1950 // Structures used by EnableSpreadSpectrumOnPPLLTable 1951 /****************************************************************************/ 1952 typedef struct _ENABLE_LVDS_SS_PARAMETERS 1953 { 1954 USHORT usSpreadSpectrumPercentage; 1955 UCHAR ucSpreadSpectrumType; //Bit1=0 Down Spread,=1 Center Spread. Bit1=1 Ext. =0 Int. Others:TBD 1956 UCHAR ucSpreadSpectrumStepSize_Delay; //bits3:2 SS_STEP_SIZE; bit 6:4 SS_DELAY 1957 UCHAR ucEnable; //ATOM_ENABLE or ATOM_DISABLE 1958 UCHAR ucPadding[3]; 1959 }ENABLE_LVDS_SS_PARAMETERS; 1960 1961 //ucTableFormatRevision=1,ucTableContentRevision=2 1962 typedef struct _ENABLE_LVDS_SS_PARAMETERS_V2 1963 { 1964 USHORT usSpreadSpectrumPercentage; 1965 UCHAR ucSpreadSpectrumType; //Bit1=0 Down Spread,=1 Center Spread. Bit1=1 Ext. =0 Int. Others:TBD 1966 UCHAR ucSpreadSpectrumStep; // 1967 UCHAR ucEnable; //ATOM_ENABLE or ATOM_DISABLE 1968 UCHAR ucSpreadSpectrumDelay; 1969 UCHAR ucSpreadSpectrumRange; 1970 UCHAR ucPadding; 1971 }ENABLE_LVDS_SS_PARAMETERS_V2; 1972 1973 //This new structure is based on ENABLE_LVDS_SS_PARAMETERS but expands to SS on PPLL, so other devices can use SS. 1974 typedef struct _ENABLE_SPREAD_SPECTRUM_ON_PPLL 1975 { 1976 USHORT usSpreadSpectrumPercentage; 1977 UCHAR ucSpreadSpectrumType; // Bit1=0 Down Spread,=1 Center Spread. Bit1=1 Ext. =0 Int. Others:TBD 1978 UCHAR ucSpreadSpectrumStep; // 1979 UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE 1980 UCHAR ucSpreadSpectrumDelay; 1981 UCHAR ucSpreadSpectrumRange; 1982 UCHAR ucPpll; // ATOM_PPLL1/ATOM_PPLL2 1983 }ENABLE_SPREAD_SPECTRUM_ON_PPLL; 1984 1985 typedef struct _ENABLE_SPREAD_SPECTRUM_ON_PPLL_V2 1986 { 1987 USHORT usSpreadSpectrumPercentage; 1988 UCHAR ucSpreadSpectrumType; // Bit[0]: 0-Down Spread,1-Center Spread. 1989 // Bit[1]: 1-Ext. 0-Int. 1990 // Bit[3:2]: =0 P1PLL =1 P2PLL =2 DCPLL 1991 // Bits[7:4] reserved 1992 UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE 1993 USHORT usSpreadSpectrumAmount; // Includes SS_AMOUNT_FBDIV[7:0] and SS_AMOUNT_NFRAC_SLIP[11:8] 1994 USHORT usSpreadSpectrumStep; // SS_STEP_SIZE_DSFRAC 1995 }ENABLE_SPREAD_SPECTRUM_ON_PPLL_V2; 1996 1997 #define ATOM_PPLL_SS_TYPE_V2_DOWN_SPREAD 0x00 1998 #define ATOM_PPLL_SS_TYPE_V2_CENTRE_SPREAD 0x01 1999 #define ATOM_PPLL_SS_TYPE_V2_EXT_SPREAD 0x02 2000 #define ATOM_PPLL_SS_TYPE_V2_PPLL_SEL_MASK 0x0c 2001 #define ATOM_PPLL_SS_TYPE_V2_P1PLL 0x00 2002 #define ATOM_PPLL_SS_TYPE_V2_P2PLL 0x04 2003 #define ATOM_PPLL_SS_TYPE_V2_DCPLL 0x08 2004 #define ATOM_PPLL_SS_AMOUNT_V2_FBDIV_MASK 0x00FF 2005 #define ATOM_PPLL_SS_AMOUNT_V2_FBDIV_SHIFT 0 2006 #define ATOM_PPLL_SS_AMOUNT_V2_NFRAC_MASK 0x0F00 2007 #define ATOM_PPLL_SS_AMOUNT_V2_NFRAC_SHIFT 8 2008 2009 // Used by DCE5.0 2010 typedef struct _ENABLE_SPREAD_SPECTRUM_ON_PPLL_V3 2011 { 2012 USHORT usSpreadSpectrumAmountFrac; // SS_AMOUNT_DSFRAC New in DCE5.0 2013 UCHAR ucSpreadSpectrumType; // Bit[0]: 0-Down Spread,1-Center Spread. 2014 // Bit[1]: 1-Ext. 0-Int. 2015 // Bit[3:2]: =0 P1PLL =1 P2PLL =2 DCPLL 2016 // Bits[7:4] reserved 2017 UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE 2018 USHORT usSpreadSpectrumAmount; // Includes SS_AMOUNT_FBDIV[7:0] and SS_AMOUNT_NFRAC_SLIP[11:8] 2019 USHORT usSpreadSpectrumStep; // SS_STEP_SIZE_DSFRAC 2020 }ENABLE_SPREAD_SPECTRUM_ON_PPLL_V3; 2021 2022 2023 #define ATOM_PPLL_SS_TYPE_V3_DOWN_SPREAD 0x00 2024 #define ATOM_PPLL_SS_TYPE_V3_CENTRE_SPREAD 0x01 2025 #define ATOM_PPLL_SS_TYPE_V3_EXT_SPREAD 0x02 2026 #define ATOM_PPLL_SS_TYPE_V3_PPLL_SEL_MASK 0x0c 2027 #define ATOM_PPLL_SS_TYPE_V3_P1PLL 0x00 2028 #define ATOM_PPLL_SS_TYPE_V3_P2PLL 0x04 2029 #define ATOM_PPLL_SS_TYPE_V3_DCPLL 0x08 2030 #define ATOM_PPLL_SS_TYPE_V3_P0PLL ATOM_PPLL_SS_TYPE_V3_DCPLL 2031 #define ATOM_PPLL_SS_AMOUNT_V3_FBDIV_MASK 0x00FF 2032 #define ATOM_PPLL_SS_AMOUNT_V3_FBDIV_SHIFT 0 2033 #define ATOM_PPLL_SS_AMOUNT_V3_NFRAC_MASK 0x0F00 2034 #define ATOM_PPLL_SS_AMOUNT_V3_NFRAC_SHIFT 8 2035 2036 #define ENABLE_SPREAD_SPECTRUM_ON_PPLL_PS_ALLOCATION ENABLE_SPREAD_SPECTRUM_ON_PPLL 2037 2038 typedef struct _SET_PIXEL_CLOCK_PS_ALLOCATION 2039 { 2040 PIXEL_CLOCK_PARAMETERS sPCLKInput; 2041 ENABLE_SPREAD_SPECTRUM_ON_PPLL sReserved;//Caller doesn't need to init this portion 2042 }SET_PIXEL_CLOCK_PS_ALLOCATION; 2043 2044 2045 2046 #define ENABLE_VGA_RENDER_PS_ALLOCATION SET_PIXEL_CLOCK_PS_ALLOCATION 2047 2048 /****************************************************************************/ 2049 // Structures used by ### 2050 /****************************************************************************/ 2051 typedef struct _MEMORY_TRAINING_PARAMETERS 2052 { 2053 ULONG ulTargetMemoryClock; //In 10Khz unit 2054 }MEMORY_TRAINING_PARAMETERS; 2055 #define MEMORY_TRAINING_PS_ALLOCATION MEMORY_TRAINING_PARAMETERS 2056 2057 2058 typedef struct _MEMORY_TRAINING_PARAMETERS_V1_2 2059 { 2060 USHORT usMemTrainingMode; 2061 USHORT usReserved; 2062 }MEMORY_TRAINING_PARAMETERS_V1_2; 2063 2064 //usMemTrainingMode 2065 #define NORMAL_MEMORY_TRAINING_MODE 0 2066 #define ENTER_DRAM_SELFREFRESH_MODE 1 2067 #define EXIT_DRAM_SELFRESH_MODE 2 2068 2069 /****************************LVDS and other encoder command table definitions **********************/ 2070 2071 2072 /****************************************************************************/ 2073 // Structures used by LVDSEncoderControlTable (Before DEC30) 2074 // LVTMAEncoderControlTable (Before DEC30) 2075 // TMDSAEncoderControlTable (Before DEC30) 2076 /****************************************************************************/ 2077 typedef struct _LVDS_ENCODER_CONTROL_PARAMETERS 2078 { 2079 USHORT usPixelClock; // in 10KHz; for bios convenient 2080 UCHAR ucMisc; // bit0=0: Enable single link 2081 // =1: Enable dual link 2082 // Bit1=0: 666RGB 2083 // =1: 888RGB 2084 UCHAR ucAction; // 0: turn off encoder 2085 // 1: setup and turn on encoder 2086 }LVDS_ENCODER_CONTROL_PARAMETERS; 2087 2088 #define LVDS_ENCODER_CONTROL_PS_ALLOCATION LVDS_ENCODER_CONTROL_PARAMETERS 2089 2090 #define TMDS1_ENCODER_CONTROL_PARAMETERS LVDS_ENCODER_CONTROL_PARAMETERS 2091 #define TMDS1_ENCODER_CONTROL_PS_ALLOCATION TMDS1_ENCODER_CONTROL_PARAMETERS 2092 2093 #define TMDS2_ENCODER_CONTROL_PARAMETERS TMDS1_ENCODER_CONTROL_PARAMETERS 2094 #define TMDS2_ENCODER_CONTROL_PS_ALLOCATION TMDS2_ENCODER_CONTROL_PARAMETERS 2095 2096 //ucTableFormatRevision=1,ucTableContentRevision=2 2097 typedef struct _LVDS_ENCODER_CONTROL_PARAMETERS_V2 2098 { 2099 USHORT usPixelClock; // in 10KHz; for bios convenient 2100 UCHAR ucMisc; // see PANEL_ENCODER_MISC_xx defintions below 2101 UCHAR ucAction; // 0: turn off encoder 2102 // 1: setup and turn on encoder 2103 UCHAR ucTruncate; // bit0=0: Disable truncate 2104 // =1: Enable truncate 2105 // bit4=0: 666RGB 2106 // =1: 888RGB 2107 UCHAR ucSpatial; // bit0=0: Disable spatial dithering 2108 // =1: Enable spatial dithering 2109 // bit4=0: 666RGB 2110 // =1: 888RGB 2111 UCHAR ucTemporal; // bit0=0: Disable temporal dithering 2112 // =1: Enable temporal dithering 2113 // bit4=0: 666RGB 2114 // =1: 888RGB 2115 // bit5=0: Gray level 2 2116 // =1: Gray level 4 2117 UCHAR ucFRC; // bit4=0: 25FRC_SEL pattern E 2118 // =1: 25FRC_SEL pattern F 2119 // bit6:5=0: 50FRC_SEL pattern A 2120 // =1: 50FRC_SEL pattern B 2121 // =2: 50FRC_SEL pattern C 2122 // =3: 50FRC_SEL pattern D 2123 // bit7=0: 75FRC_SEL pattern E 2124 // =1: 75FRC_SEL pattern F 2125 }LVDS_ENCODER_CONTROL_PARAMETERS_V2; 2126 2127 #define LVDS_ENCODER_CONTROL_PS_ALLOCATION_V2 LVDS_ENCODER_CONTROL_PARAMETERS_V2 2128 2129 #define TMDS1_ENCODER_CONTROL_PARAMETERS_V2 LVDS_ENCODER_CONTROL_PARAMETERS_V2 2130 #define TMDS1_ENCODER_CONTROL_PS_ALLOCATION_V2 TMDS1_ENCODER_CONTROL_PARAMETERS_V2 2131 2132 #define TMDS2_ENCODER_CONTROL_PARAMETERS_V2 TMDS1_ENCODER_CONTROL_PARAMETERS_V2 2133 #define TMDS2_ENCODER_CONTROL_PS_ALLOCATION_V2 TMDS2_ENCODER_CONTROL_PARAMETERS_V2 2134 2135 2136 #define LVDS_ENCODER_CONTROL_PARAMETERS_V3 LVDS_ENCODER_CONTROL_PARAMETERS_V2 2137 #define LVDS_ENCODER_CONTROL_PS_ALLOCATION_V3 LVDS_ENCODER_CONTROL_PARAMETERS_V3 2138 2139 #define TMDS1_ENCODER_CONTROL_PARAMETERS_V3 LVDS_ENCODER_CONTROL_PARAMETERS_V3 2140 #define TMDS1_ENCODER_CONTROL_PS_ALLOCATION_V3 TMDS1_ENCODER_CONTROL_PARAMETERS_V3 2141 2142 #define TMDS2_ENCODER_CONTROL_PARAMETERS_V3 LVDS_ENCODER_CONTROL_PARAMETERS_V3 2143 #define TMDS2_ENCODER_CONTROL_PS_ALLOCATION_V3 TMDS2_ENCODER_CONTROL_PARAMETERS_V3 2144 2145 /****************************************************************************/ 2146 // Structures used by ### 2147 /****************************************************************************/ 2148 typedef struct _ENABLE_EXTERNAL_TMDS_ENCODER_PARAMETERS 2149 { 2150 UCHAR ucEnable; // Enable or Disable External TMDS encoder 2151 UCHAR ucMisc; // Bit0=0:Enable Single link;=1:Enable Dual link;Bit1 {=0:666RGB, =1:888RGB} 2152 UCHAR ucPadding[2]; 2153 }ENABLE_EXTERNAL_TMDS_ENCODER_PARAMETERS; 2154 2155 typedef struct _ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION 2156 { 2157 ENABLE_EXTERNAL_TMDS_ENCODER_PARAMETERS sXTmdsEncoder; 2158 WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved; //Caller doesn't need to init this portion 2159 }ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION; 2160 2161 #define ENABLE_EXTERNAL_TMDS_ENCODER_PARAMETERS_V2 LVDS_ENCODER_CONTROL_PARAMETERS_V2 2162 typedef struct _ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION_V2 2163 { 2164 ENABLE_EXTERNAL_TMDS_ENCODER_PARAMETERS_V2 sXTmdsEncoder; 2165 WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved; //Caller doesn't need to init this portion 2166 }ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION_V2; 2167 2168 typedef struct _EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION 2169 { 2170 DIG_ENCODER_CONTROL_PARAMETERS sDigEncoder; 2171 WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved; 2172 }EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION; 2173 2174 /****************************************************************************/ 2175 // Structures used by DVOEncoderControlTable 2176 /****************************************************************************/ 2177 //ucTableFormatRevision=1,ucTableContentRevision=3 2178 //ucDVOConfig: 2179 #define DVO_ENCODER_CONFIG_RATE_SEL 0x01 2180 #define DVO_ENCODER_CONFIG_DDR_SPEED 0x00 2181 #define DVO_ENCODER_CONFIG_SDR_SPEED 0x01 2182 #define DVO_ENCODER_CONFIG_OUTPUT_SEL 0x0c 2183 #define DVO_ENCODER_CONFIG_LOW12BIT 0x00 2184 #define DVO_ENCODER_CONFIG_UPPER12BIT 0x04 2185 #define DVO_ENCODER_CONFIG_24BIT 0x08 2186 2187 typedef struct _DVO_ENCODER_CONTROL_PARAMETERS_V3 2188 { 2189 USHORT usPixelClock; 2190 UCHAR ucDVOConfig; 2191 UCHAR ucAction; //ATOM_ENABLE/ATOM_DISABLE/ATOM_HPD_INIT 2192 UCHAR ucReseved[4]; 2193 }DVO_ENCODER_CONTROL_PARAMETERS_V3; 2194 #define DVO_ENCODER_CONTROL_PS_ALLOCATION_V3 DVO_ENCODER_CONTROL_PARAMETERS_V3 2195 2196 typedef struct _DVO_ENCODER_CONTROL_PARAMETERS_V1_4 2197 { 2198 USHORT usPixelClock; 2199 UCHAR ucDVOConfig; 2200 UCHAR ucAction; //ATOM_ENABLE/ATOM_DISABLE/ATOM_HPD_INIT 2201 UCHAR ucBitPerColor; //please refer to definition of PANEL_xBIT_PER_COLOR 2202 UCHAR ucReseved[3]; 2203 }DVO_ENCODER_CONTROL_PARAMETERS_V1_4; 2204 #define DVO_ENCODER_CONTROL_PS_ALLOCATION_V1_4 DVO_ENCODER_CONTROL_PARAMETERS_V1_4 2205 2206 2207 //ucTableFormatRevision=1 2208 //ucTableContentRevision=3 structure is not changed but usMisc add bit 1 as another input for 2209 // bit1=0: non-coherent mode 2210 // =1: coherent mode 2211 2212 //========================================================================================== 2213 //Only change is here next time when changing encoder parameter definitions again! 2214 #define LVDS_ENCODER_CONTROL_PARAMETERS_LAST LVDS_ENCODER_CONTROL_PARAMETERS_V3 2215 #define LVDS_ENCODER_CONTROL_PS_ALLOCATION_LAST LVDS_ENCODER_CONTROL_PARAMETERS_LAST 2216 2217 #define TMDS1_ENCODER_CONTROL_PARAMETERS_LAST LVDS_ENCODER_CONTROL_PARAMETERS_V3 2218 #define TMDS1_ENCODER_CONTROL_PS_ALLOCATION_LAST TMDS1_ENCODER_CONTROL_PARAMETERS_LAST 2219 2220 #define TMDS2_ENCODER_CONTROL_PARAMETERS_LAST LVDS_ENCODER_CONTROL_PARAMETERS_V3 2221 #define TMDS2_ENCODER_CONTROL_PS_ALLOCATION_LAST TMDS2_ENCODER_CONTROL_PARAMETERS_LAST 2222 2223 #define DVO_ENCODER_CONTROL_PARAMETERS_LAST DVO_ENCODER_CONTROL_PARAMETERS 2224 #define DVO_ENCODER_CONTROL_PS_ALLOCATION_LAST DVO_ENCODER_CONTROL_PS_ALLOCATION 2225 2226 //========================================================================================== 2227 #define PANEL_ENCODER_MISC_DUAL 0x01 2228 #define PANEL_ENCODER_MISC_COHERENT 0x02 2229 #define PANEL_ENCODER_MISC_TMDS_LINKB 0x04 2230 #define PANEL_ENCODER_MISC_HDMI_TYPE 0x08 2231 2232 #define PANEL_ENCODER_ACTION_DISABLE ATOM_DISABLE 2233 #define PANEL_ENCODER_ACTION_ENABLE ATOM_ENABLE 2234 #define PANEL_ENCODER_ACTION_COHERENTSEQ (ATOM_ENABLE+1) 2235 2236 #define PANEL_ENCODER_TRUNCATE_EN 0x01 2237 #define PANEL_ENCODER_TRUNCATE_DEPTH 0x10 2238 #define PANEL_ENCODER_SPATIAL_DITHER_EN 0x01 2239 #define PANEL_ENCODER_SPATIAL_DITHER_DEPTH 0x10 2240 #define PANEL_ENCODER_TEMPORAL_DITHER_EN 0x01 2241 #define PANEL_ENCODER_TEMPORAL_DITHER_DEPTH 0x10 2242 #define PANEL_ENCODER_TEMPORAL_LEVEL_4 0x20 2243 #define PANEL_ENCODER_25FRC_MASK 0x10 2244 #define PANEL_ENCODER_25FRC_E 0x00 2245 #define PANEL_ENCODER_25FRC_F 0x10 2246 #define PANEL_ENCODER_50FRC_MASK 0x60 2247 #define PANEL_ENCODER_50FRC_A 0x00 2248 #define PANEL_ENCODER_50FRC_B 0x20 2249 #define PANEL_ENCODER_50FRC_C 0x40 2250 #define PANEL_ENCODER_50FRC_D 0x60 2251 #define PANEL_ENCODER_75FRC_MASK 0x80 2252 #define PANEL_ENCODER_75FRC_E 0x00 2253 #define PANEL_ENCODER_75FRC_F 0x80 2254 2255 /****************************************************************************/ 2256 // Structures used by SetVoltageTable 2257 /****************************************************************************/ 2258 #define SET_VOLTAGE_TYPE_ASIC_VDDC 1 2259 #define SET_VOLTAGE_TYPE_ASIC_MVDDC 2 2260 #define SET_VOLTAGE_TYPE_ASIC_MVDDQ 3 2261 #define SET_VOLTAGE_TYPE_ASIC_VDDCI 4 2262 #define SET_VOLTAGE_INIT_MODE 5 2263 #define SET_VOLTAGE_GET_MAX_VOLTAGE 6 //Gets the Max. voltage for the soldered Asic 2264 2265 #define SET_ASIC_VOLTAGE_MODE_ALL_SOURCE 0x1 2266 #define SET_ASIC_VOLTAGE_MODE_SOURCE_A 0x2 2267 #define SET_ASIC_VOLTAGE_MODE_SOURCE_B 0x4 2268 2269 #define SET_ASIC_VOLTAGE_MODE_SET_VOLTAGE 0x0 2270 #define SET_ASIC_VOLTAGE_MODE_GET_GPIOVAL 0x1 2271 #define SET_ASIC_VOLTAGE_MODE_GET_GPIOMASK 0x2 2272 2273 typedef struct _SET_VOLTAGE_PARAMETERS 2274 { 2275 UCHAR ucVoltageType; // To tell which voltage to set up, VDDC/MVDDC/MVDDQ 2276 UCHAR ucVoltageMode; // To set all, to set source A or source B or ... 2277 UCHAR ucVoltageIndex; // An index to tell which voltage level 2278 UCHAR ucReserved; 2279 }SET_VOLTAGE_PARAMETERS; 2280 2281 typedef struct _SET_VOLTAGE_PARAMETERS_V2 2282 { 2283 UCHAR ucVoltageType; // To tell which voltage to set up, VDDC/MVDDC/MVDDQ 2284 UCHAR ucVoltageMode; // Not used, maybe use for state machine for differen power mode 2285 USHORT usVoltageLevel; // real voltage level 2286 }SET_VOLTAGE_PARAMETERS_V2; 2287 2288 // used by both SetVoltageTable v1.3 and v1.4 2289 typedef struct _SET_VOLTAGE_PARAMETERS_V1_3 2290 { 2291 UCHAR ucVoltageType; // To tell which voltage to set up, VDDC/MVDDC/MVDDQ/VDDCI 2292 UCHAR ucVoltageMode; // Indicate action: Set voltage level 2293 USHORT usVoltageLevel; // real voltage level in unit of mv or Voltage Phase (0, 1, 2, .. ) 2294 }SET_VOLTAGE_PARAMETERS_V1_3; 2295 2296 //ucVoltageType 2297 #define VOLTAGE_TYPE_VDDC 1 2298 #define VOLTAGE_TYPE_MVDDC 2 2299 #define VOLTAGE_TYPE_MVDDQ 3 2300 #define VOLTAGE_TYPE_VDDCI 4 2301 #define VOLTAGE_TYPE_VDDGFX 5 2302 #define VOLTAGE_TYPE_PCC 6 2303 2304 #define VOLTAGE_TYPE_GENERIC_I2C_1 0x11 2305 #define VOLTAGE_TYPE_GENERIC_I2C_2 0x12 2306 #define VOLTAGE_TYPE_GENERIC_I2C_3 0x13 2307 #define VOLTAGE_TYPE_GENERIC_I2C_4 0x14 2308 #define VOLTAGE_TYPE_GENERIC_I2C_5 0x15 2309 #define VOLTAGE_TYPE_GENERIC_I2C_6 0x16 2310 #define VOLTAGE_TYPE_GENERIC_I2C_7 0x17 2311 #define VOLTAGE_TYPE_GENERIC_I2C_8 0x18 2312 #define VOLTAGE_TYPE_GENERIC_I2C_9 0x19 2313 #define VOLTAGE_TYPE_GENERIC_I2C_10 0x1A 2314 2315 //SET_VOLTAGE_PARAMETERS_V3.ucVoltageMode 2316 #define ATOM_SET_VOLTAGE 0 //Set voltage Level 2317 #define ATOM_INIT_VOLTAGE_REGULATOR 3 //Init Regulator 2318 #define ATOM_SET_VOLTAGE_PHASE 4 //Set Vregulator Phase, only for SVID/PVID regulator 2319 #define ATOM_GET_MAX_VOLTAGE 6 //Get Max Voltage, not used from SetVoltageTable v1.3 2320 #define ATOM_GET_VOLTAGE_LEVEL 6 //Get Voltage level from vitual voltage ID, not used for SetVoltage v1.4 2321 #define ATOM_GET_LEAKAGE_ID 8 //Get Leakage Voltage Id ( starting from SMU7x IP ), SetVoltage v1.4 2322 2323 // define vitual voltage id in usVoltageLevel 2324 #define ATOM_VIRTUAL_VOLTAGE_ID0 0xff01 2325 #define ATOM_VIRTUAL_VOLTAGE_ID1 0xff02 2326 #define ATOM_VIRTUAL_VOLTAGE_ID2 0xff03 2327 #define ATOM_VIRTUAL_VOLTAGE_ID3 0xff04 2328 #define ATOM_VIRTUAL_VOLTAGE_ID4 0xff05 2329 #define ATOM_VIRTUAL_VOLTAGE_ID5 0xff06 2330 #define ATOM_VIRTUAL_VOLTAGE_ID6 0xff07 2331 #define ATOM_VIRTUAL_VOLTAGE_ID7 0xff08 2332 2333 typedef struct _SET_VOLTAGE_PS_ALLOCATION 2334 { 2335 SET_VOLTAGE_PARAMETERS sASICSetVoltage; 2336 WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved; 2337 }SET_VOLTAGE_PS_ALLOCATION; 2338 2339 // New Added from SI for GetVoltageInfoTable, input parameter structure 2340 typedef struct _GET_VOLTAGE_INFO_INPUT_PARAMETER_V1_1 2341 { 2342 UCHAR ucVoltageType; // Input: To tell which voltage to set up, VDDC/MVDDC/MVDDQ/VDDCI 2343 UCHAR ucVoltageMode; // Input: Indicate action: Get voltage info 2344 USHORT usVoltageLevel; // Input: real voltage level in unit of mv or Voltage Phase (0, 1, 2, .. ) or Leakage Id 2345 ULONG ulReserved; 2346 }GET_VOLTAGE_INFO_INPUT_PARAMETER_V1_1; 2347 2348 // New Added from SI for GetVoltageInfoTable, output parameter structure when ucVotlageMode == ATOM_GET_VOLTAGE_VID 2349 typedef struct _GET_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_1 2350 { 2351 ULONG ulVotlageGpioState; 2352 ULONG ulVoltageGPioMask; 2353 }GET_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_1; 2354 2355 // New Added from SI for GetVoltageInfoTable, output parameter structure when ucVotlageMode == ATOM_GET_VOLTAGE_STATEx_LEAKAGE_VID 2356 typedef struct _GET_LEAKAGE_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_1 2357 { 2358 USHORT usVoltageLevel; 2359 USHORT usVoltageId; // Voltage Id programmed in Voltage Regulator 2360 ULONG ulReseved; 2361 }GET_LEAKAGE_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_1; 2362 2363 // GetVoltageInfo v1.1 ucVoltageMode 2364 #define ATOM_GET_VOLTAGE_VID 0x00 2365 #define ATOM_GET_VOTLAGE_INIT_SEQ 0x03 2366 #define ATOM_GET_VOLTTAGE_PHASE_PHASE_VID 0x04 2367 #define ATOM_GET_VOLTAGE_SVID2 0x07 //Get SVI2 Regulator Info 2368 2369 // for SI, this state map to 0xff02 voltage state in Power Play table, which is power boost state 2370 #define ATOM_GET_VOLTAGE_STATE0_LEAKAGE_VID 0x10 2371 // for SI, this state map to 0xff01 voltage state in Power Play table, which is performance state 2372 #define ATOM_GET_VOLTAGE_STATE1_LEAKAGE_VID 0x11 2373 2374 #define ATOM_GET_VOLTAGE_STATE2_LEAKAGE_VID 0x12 2375 #define ATOM_GET_VOLTAGE_STATE3_LEAKAGE_VID 0x13 2376 2377 2378 // New Added from CI Hawaii for GetVoltageInfoTable, input parameter structure 2379 typedef struct _GET_VOLTAGE_INFO_INPUT_PARAMETER_V1_2 2380 { 2381 UCHAR ucVoltageType; // Input: To tell which voltage to set up, VDDC/MVDDC/MVDDQ/VDDCI 2382 UCHAR ucVoltageMode; // Input: Indicate action: Get voltage info 2383 USHORT usVoltageLevel; // Input: real voltage level in unit of mv or Voltage Phase (0, 1, 2, .. ) or Leakage Id 2384 ULONG ulSCLKFreq; // Input: when ucVoltageMode= ATOM_GET_VOLTAGE_EVV_VOLTAGE, DPM state SCLK frequency, Define in PPTable SCLK/Voltage dependence table 2385 }GET_VOLTAGE_INFO_INPUT_PARAMETER_V1_2; 2386 2387 // New in GetVoltageInfo v1.2 ucVoltageMode 2388 #define ATOM_GET_VOLTAGE_EVV_VOLTAGE 0x09 2389 2390 // New Added from CI Hawaii for EVV feature 2391 typedef struct _GET_EVV_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_2 2392 { 2393 USHORT usVoltageLevel; // real voltage level in unit of mv 2394 USHORT usVoltageId; // Voltage Id programmed in Voltage Regulator 2395 USHORT usTDP_Current; // TDP_Current in unit of 0.01A 2396 USHORT usTDP_Power; // TDP_Current in unit of 0.1W 2397 }GET_EVV_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_2; 2398 2399 /****************************************************************************/ 2400 // Structures used by TVEncoderControlTable 2401 /****************************************************************************/ 2402 typedef struct _TV_ENCODER_CONTROL_PARAMETERS 2403 { 2404 USHORT usPixelClock; // in 10KHz; for bios convenient 2405 UCHAR ucTvStandard; // See definition "ATOM_TV_NTSC ..." 2406 UCHAR ucAction; // 0: turn off encoder 2407 // 1: setup and turn on encoder 2408 }TV_ENCODER_CONTROL_PARAMETERS; 2409 2410 typedef struct _TV_ENCODER_CONTROL_PS_ALLOCATION 2411 { 2412 TV_ENCODER_CONTROL_PARAMETERS sTVEncoder; 2413 WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved; // Don't set this one 2414 }TV_ENCODER_CONTROL_PS_ALLOCATION; 2415 2416 //==============================Data Table Portion==================================== 2417 2418 2419 /****************************************************************************/ 2420 // Structure used in Data.mtb 2421 /****************************************************************************/ 2422 typedef struct _ATOM_MASTER_LIST_OF_DATA_TABLES 2423 { 2424 USHORT UtilityPipeLine; // Offest for the utility to get parser info,Don't change this position! 2425 USHORT MultimediaCapabilityInfo; // Only used by MM Lib,latest version 1.1, not configuable from Bios, need to include the table to build Bios 2426 USHORT MultimediaConfigInfo; // Only used by MM Lib,latest version 2.1, not configuable from Bios, need to include the table to build Bios 2427 USHORT StandardVESA_Timing; // Only used by Bios 2428 USHORT FirmwareInfo; // Shared by various SW components,latest version 1.4 2429 USHORT PaletteData; // Only used by BIOS 2430 USHORT LCD_Info; // Shared by various SW components,latest version 1.3, was called LVDS_Info 2431 USHORT DIGTransmitterInfo; // Internal used by VBIOS only version 3.1 2432 USHORT AnalogTV_Info; // Shared by various SW components,latest version 1.1 2433 USHORT SupportedDevicesInfo; // Will be obsolete from R600 2434 USHORT GPIO_I2C_Info; // Shared by various SW components,latest version 1.2 will be used from R600 2435 USHORT VRAM_UsageByFirmware; // Shared by various SW components,latest version 1.3 will be used from R600 2436 USHORT GPIO_Pin_LUT; // Shared by various SW components,latest version 1.1 2437 USHORT VESA_ToInternalModeLUT; // Only used by Bios 2438 USHORT ComponentVideoInfo; // Shared by various SW components,latest version 2.1 will be used from R600 2439 USHORT PowerPlayInfo; // Shared by various SW components,latest version 2.1,new design from R600 2440 USHORT GPUVirtualizationInfo; // Will be obsolete from R600 2441 USHORT SaveRestoreInfo; // Only used by Bios 2442 USHORT PPLL_SS_Info; // Shared by various SW components,latest version 1.2, used to call SS_Info, change to new name because of int ASIC SS info 2443 USHORT OemInfo; // Defined and used by external SW, should be obsolete soon 2444 USHORT XTMDS_Info; // Will be obsolete from R600 2445 USHORT MclkSS_Info; // Shared by various SW components,latest version 1.1, only enabled when ext SS chip is used 2446 USHORT Object_Header; // Shared by various SW components,latest version 1.1 2447 USHORT IndirectIOAccess; // Only used by Bios,this table position can't change at all!! 2448 USHORT MC_InitParameter; // Only used by command table 2449 USHORT ASIC_VDDC_Info; // Will be obsolete from R600 2450 USHORT ASIC_InternalSS_Info; // New tabel name from R600, used to be called "ASIC_MVDDC_Info" 2451 USHORT TV_VideoMode; // Only used by command table 2452 USHORT VRAM_Info; // Only used by command table, latest version 1.3 2453 USHORT MemoryTrainingInfo; // Used for VBIOS and Diag utility for memory training purpose since R600. the new table rev start from 2.1 2454 USHORT IntegratedSystemInfo; // Shared by various SW components 2455 USHORT ASIC_ProfilingInfo; // New table name from R600, used to be called "ASIC_VDDCI_Info" for pre-R600 2456 USHORT VoltageObjectInfo; // Shared by various SW components, latest version 1.1 2457 USHORT PowerSourceInfo; // Shared by various SW components, latest versoin 1.1 2458 USHORT ServiceInfo; 2459 }ATOM_MASTER_LIST_OF_DATA_TABLES; 2460 2461 typedef struct _ATOM_MASTER_DATA_TABLE 2462 { 2463 ATOM_COMMON_TABLE_HEADER sHeader; 2464 ATOM_MASTER_LIST_OF_DATA_TABLES ListOfDataTables; 2465 }ATOM_MASTER_DATA_TABLE; 2466 2467 // For backward compatible 2468 #define LVDS_Info LCD_Info 2469 #define DAC_Info PaletteData 2470 #define TMDS_Info DIGTransmitterInfo 2471 #define CompassionateData GPUVirtualizationInfo 2472 2473 /****************************************************************************/ 2474 // Structure used in MultimediaCapabilityInfoTable 2475 /****************************************************************************/ 2476 typedef struct _ATOM_MULTIMEDIA_CAPABILITY_INFO 2477 { 2478 ATOM_COMMON_TABLE_HEADER sHeader; 2479 ULONG ulSignature; // HW info table signature string "$ATI" 2480 UCHAR ucI2C_Type; // I2C type (normal GP_IO, ImpactTV GP_IO, Dedicated I2C pin, etc) 2481 UCHAR ucTV_OutInfo; // Type of TV out supported (3:0) and video out crystal frequency (6:4) and TV data port (7) 2482 UCHAR ucVideoPortInfo; // Provides the video port capabilities 2483 UCHAR ucHostPortInfo; // Provides host port configuration information 2484 }ATOM_MULTIMEDIA_CAPABILITY_INFO; 2485 2486 2487 /****************************************************************************/ 2488 // Structure used in MultimediaConfigInfoTable 2489 /****************************************************************************/ 2490 typedef struct _ATOM_MULTIMEDIA_CONFIG_INFO 2491 { 2492 ATOM_COMMON_TABLE_HEADER sHeader; 2493 ULONG ulSignature; // MM info table signature sting "$MMT" 2494 UCHAR ucTunerInfo; // Type of tuner installed on the adapter (4:0) and video input for tuner (7:5) 2495 UCHAR ucAudioChipInfo; // List the audio chip type (3:0) product type (4) and OEM revision (7:5) 2496 UCHAR ucProductID; // Defines as OEM ID or ATI board ID dependent on product type setting 2497 UCHAR ucMiscInfo1; // Tuner voltage (1:0) HW teletext support (3:2) FM audio decoder (5:4) reserved (6) audio scrambling (7) 2498 UCHAR ucMiscInfo2; // I2S input config (0) I2S output config (1) I2S Audio Chip (4:2) SPDIF Output Config (5) reserved (7:6) 2499 UCHAR ucMiscInfo3; // Video Decoder Type (3:0) Video In Standard/Crystal (7:4) 2500 UCHAR ucMiscInfo4; // Video Decoder Host Config (2:0) reserved (7:3) 2501 UCHAR ucVideoInput0Info;// Video Input 0 Type (1:0) F/B setting (2) physical connector ID (5:3) reserved (7:6) 2502 UCHAR ucVideoInput1Info;// Video Input 1 Type (1:0) F/B setting (2) physical connector ID (5:3) reserved (7:6) 2503 UCHAR ucVideoInput2Info;// Video Input 2 Type (1:0) F/B setting (2) physical connector ID (5:3) reserved (7:6) 2504 UCHAR ucVideoInput3Info;// Video Input 3 Type (1:0) F/B setting (2) physical connector ID (5:3) reserved (7:6) 2505 UCHAR ucVideoInput4Info;// Video Input 4 Type (1:0) F/B setting (2) physical connector ID (5:3) reserved (7:6) 2506 }ATOM_MULTIMEDIA_CONFIG_INFO; 2507 2508 2509 /****************************************************************************/ 2510 // Structures used in FirmwareInfoTable 2511 /****************************************************************************/ 2512 2513 // usBIOSCapability Defintion: 2514 // Bit 0 = 0: Bios image is not Posted, =1:Bios image is Posted; 2515 // Bit 1 = 0: Dual CRTC is not supported, =1: Dual CRTC is supported; 2516 // Bit 2 = 0: Extended Desktop is not supported, =1: Extended Desktop is supported; 2517 // Others: Reserved 2518 #define ATOM_BIOS_INFO_ATOM_FIRMWARE_POSTED 0x0001 2519 #define ATOM_BIOS_INFO_DUAL_CRTC_SUPPORT 0x0002 2520 #define ATOM_BIOS_INFO_EXTENDED_DESKTOP_SUPPORT 0x0004 2521 #define ATOM_BIOS_INFO_MEMORY_CLOCK_SS_SUPPORT 0x0008 // (valid from v1.1 ~v1.4):=1: memclk SS enable, =0 memclk SS disable. 2522 #define ATOM_BIOS_INFO_ENGINE_CLOCK_SS_SUPPORT 0x0010 // (valid from v1.1 ~v1.4):=1: engclk SS enable, =0 engclk SS disable. 2523 #define ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU 0x0020 2524 #define ATOM_BIOS_INFO_WMI_SUPPORT 0x0040 2525 #define ATOM_BIOS_INFO_PPMODE_ASSIGNGED_BY_SYSTEM 0x0080 2526 #define ATOM_BIOS_INFO_HYPERMEMORY_SUPPORT 0x0100 2527 #define ATOM_BIOS_INFO_HYPERMEMORY_SIZE_MASK 0x1E00 2528 #define ATOM_BIOS_INFO_VPOST_WITHOUT_FIRST_MODE_SET 0x2000 2529 #define ATOM_BIOS_INFO_BIOS_SCRATCH6_SCL2_REDEFINE 0x4000 2530 #define ATOM_BIOS_INFO_MEMORY_CLOCK_EXT_SS_SUPPORT 0x0008 // (valid from v2.1 ): =1: memclk ss enable with external ss chip 2531 #define ATOM_BIOS_INFO_ENGINE_CLOCK_EXT_SS_SUPPORT 0x0010 // (valid from v2.1 ): =1: engclk ss enable with external ss chip 2532 2533 2534 #ifndef _H2INC 2535 2536 //Please don't add or expand this bitfield structure below, this one will retire soon.! 2537 typedef struct _ATOM_FIRMWARE_CAPABILITY 2538 { 2539 #if ATOM_BIG_ENDIAN 2540 USHORT Reserved:1; 2541 USHORT SCL2Redefined:1; 2542 USHORT PostWithoutModeSet:1; 2543 USHORT HyperMemory_Size:4; 2544 USHORT HyperMemory_Support:1; 2545 USHORT PPMode_Assigned:1; 2546 USHORT WMI_SUPPORT:1; 2547 USHORT GPUControlsBL:1; 2548 USHORT EngineClockSS_Support:1; 2549 USHORT MemoryClockSS_Support:1; 2550 USHORT ExtendedDesktopSupport:1; 2551 USHORT DualCRTC_Support:1; 2552 USHORT FirmwarePosted:1; 2553 #else 2554 USHORT FirmwarePosted:1; 2555 USHORT DualCRTC_Support:1; 2556 USHORT ExtendedDesktopSupport:1; 2557 USHORT MemoryClockSS_Support:1; 2558 USHORT EngineClockSS_Support:1; 2559 USHORT GPUControlsBL:1; 2560 USHORT WMI_SUPPORT:1; 2561 USHORT PPMode_Assigned:1; 2562 USHORT HyperMemory_Support:1; 2563 USHORT HyperMemory_Size:4; 2564 USHORT PostWithoutModeSet:1; 2565 USHORT SCL2Redefined:1; 2566 USHORT Reserved:1; 2567 #endif 2568 }ATOM_FIRMWARE_CAPABILITY; 2569 2570 typedef union _ATOM_FIRMWARE_CAPABILITY_ACCESS 2571 { 2572 ATOM_FIRMWARE_CAPABILITY sbfAccess; 2573 USHORT susAccess; 2574 }ATOM_FIRMWARE_CAPABILITY_ACCESS; 2575 2576 #else 2577 2578 typedef union _ATOM_FIRMWARE_CAPABILITY_ACCESS 2579 { 2580 USHORT susAccess; 2581 }ATOM_FIRMWARE_CAPABILITY_ACCESS; 2582 2583 #endif 2584 2585 typedef struct _ATOM_FIRMWARE_INFO 2586 { 2587 ATOM_COMMON_TABLE_HEADER sHeader; 2588 ULONG ulFirmwareRevision; 2589 ULONG ulDefaultEngineClock; //In 10Khz unit 2590 ULONG ulDefaultMemoryClock; //In 10Khz unit 2591 ULONG ulDriverTargetEngineClock; //In 10Khz unit 2592 ULONG ulDriverTargetMemoryClock; //In 10Khz unit 2593 ULONG ulMaxEngineClockPLL_Output; //In 10Khz unit 2594 ULONG ulMaxMemoryClockPLL_Output; //In 10Khz unit 2595 ULONG ulMaxPixelClockPLL_Output; //In 10Khz unit 2596 ULONG ulASICMaxEngineClock; //In 10Khz unit 2597 ULONG ulASICMaxMemoryClock; //In 10Khz unit 2598 UCHAR ucASICMaxTemperature; 2599 UCHAR ucPadding[3]; //Don't use them 2600 ULONG aulReservedForBIOS[3]; //Don't use them 2601 USHORT usMinEngineClockPLL_Input; //In 10Khz unit 2602 USHORT usMaxEngineClockPLL_Input; //In 10Khz unit 2603 USHORT usMinEngineClockPLL_Output; //In 10Khz unit 2604 USHORT usMinMemoryClockPLL_Input; //In 10Khz unit 2605 USHORT usMaxMemoryClockPLL_Input; //In 10Khz unit 2606 USHORT usMinMemoryClockPLL_Output; //In 10Khz unit 2607 USHORT usMaxPixelClock; //In 10Khz unit, Max. Pclk 2608 USHORT usMinPixelClockPLL_Input; //In 10Khz unit 2609 USHORT usMaxPixelClockPLL_Input; //In 10Khz unit 2610 USHORT usMinPixelClockPLL_Output; //In 10Khz unit, the definitions above can't change!!! 2611 ATOM_FIRMWARE_CAPABILITY_ACCESS usFirmwareCapability; 2612 USHORT usReferenceClock; //In 10Khz unit 2613 USHORT usPM_RTS_Location; //RTS PM4 starting location in ROM in 1Kb unit 2614 UCHAR ucPM_RTS_StreamSize; //RTS PM4 packets in Kb unit 2615 UCHAR ucDesign_ID; //Indicate what is the board design 2616 UCHAR ucMemoryModule_ID; //Indicate what is the board design 2617 }ATOM_FIRMWARE_INFO; 2618 2619 typedef struct _ATOM_FIRMWARE_INFO_V1_2 2620 { 2621 ATOM_COMMON_TABLE_HEADER sHeader; 2622 ULONG ulFirmwareRevision; 2623 ULONG ulDefaultEngineClock; //In 10Khz unit 2624 ULONG ulDefaultMemoryClock; //In 10Khz unit 2625 ULONG ulDriverTargetEngineClock; //In 10Khz unit 2626 ULONG ulDriverTargetMemoryClock; //In 10Khz unit 2627 ULONG ulMaxEngineClockPLL_Output; //In 10Khz unit 2628 ULONG ulMaxMemoryClockPLL_Output; //In 10Khz unit 2629 ULONG ulMaxPixelClockPLL_Output; //In 10Khz unit 2630 ULONG ulASICMaxEngineClock; //In 10Khz unit 2631 ULONG ulASICMaxMemoryClock; //In 10Khz unit 2632 UCHAR ucASICMaxTemperature; 2633 UCHAR ucMinAllowedBL_Level; 2634 UCHAR ucPadding[2]; //Don't use them 2635 ULONG aulReservedForBIOS[2]; //Don't use them 2636 ULONG ulMinPixelClockPLL_Output; //In 10Khz unit 2637 USHORT usMinEngineClockPLL_Input; //In 10Khz unit 2638 USHORT usMaxEngineClockPLL_Input; //In 10Khz unit 2639 USHORT usMinEngineClockPLL_Output; //In 10Khz unit 2640 USHORT usMinMemoryClockPLL_Input; //In 10Khz unit 2641 USHORT usMaxMemoryClockPLL_Input; //In 10Khz unit 2642 USHORT usMinMemoryClockPLL_Output; //In 10Khz unit 2643 USHORT usMaxPixelClock; //In 10Khz unit, Max. Pclk 2644 USHORT usMinPixelClockPLL_Input; //In 10Khz unit 2645 USHORT usMaxPixelClockPLL_Input; //In 10Khz unit 2646 USHORT usMinPixelClockPLL_Output; //In 10Khz unit - lower 16bit of ulMinPixelClockPLL_Output 2647 ATOM_FIRMWARE_CAPABILITY_ACCESS usFirmwareCapability; 2648 USHORT usReferenceClock; //In 10Khz unit 2649 USHORT usPM_RTS_Location; //RTS PM4 starting location in ROM in 1Kb unit 2650 UCHAR ucPM_RTS_StreamSize; //RTS PM4 packets in Kb unit 2651 UCHAR ucDesign_ID; //Indicate what is the board design 2652 UCHAR ucMemoryModule_ID; //Indicate what is the board design 2653 }ATOM_FIRMWARE_INFO_V1_2; 2654 2655 typedef struct _ATOM_FIRMWARE_INFO_V1_3 2656 { 2657 ATOM_COMMON_TABLE_HEADER sHeader; 2658 ULONG ulFirmwareRevision; 2659 ULONG ulDefaultEngineClock; //In 10Khz unit 2660 ULONG ulDefaultMemoryClock; //In 10Khz unit 2661 ULONG ulDriverTargetEngineClock; //In 10Khz unit 2662 ULONG ulDriverTargetMemoryClock; //In 10Khz unit 2663 ULONG ulMaxEngineClockPLL_Output; //In 10Khz unit 2664 ULONG ulMaxMemoryClockPLL_Output; //In 10Khz unit 2665 ULONG ulMaxPixelClockPLL_Output; //In 10Khz unit 2666 ULONG ulASICMaxEngineClock; //In 10Khz unit 2667 ULONG ulASICMaxMemoryClock; //In 10Khz unit 2668 UCHAR ucASICMaxTemperature; 2669 UCHAR ucMinAllowedBL_Level; 2670 UCHAR ucPadding[2]; //Don't use them 2671 ULONG aulReservedForBIOS; //Don't use them 2672 ULONG ul3DAccelerationEngineClock;//In 10Khz unit 2673 ULONG ulMinPixelClockPLL_Output; //In 10Khz unit 2674 USHORT usMinEngineClockPLL_Input; //In 10Khz unit 2675 USHORT usMaxEngineClockPLL_Input; //In 10Khz unit 2676 USHORT usMinEngineClockPLL_Output; //In 10Khz unit 2677 USHORT usMinMemoryClockPLL_Input; //In 10Khz unit 2678 USHORT usMaxMemoryClockPLL_Input; //In 10Khz unit 2679 USHORT usMinMemoryClockPLL_Output; //In 10Khz unit 2680 USHORT usMaxPixelClock; //In 10Khz unit, Max. Pclk 2681 USHORT usMinPixelClockPLL_Input; //In 10Khz unit 2682 USHORT usMaxPixelClockPLL_Input; //In 10Khz unit 2683 USHORT usMinPixelClockPLL_Output; //In 10Khz unit - lower 16bit of ulMinPixelClockPLL_Output 2684 ATOM_FIRMWARE_CAPABILITY_ACCESS usFirmwareCapability; 2685 USHORT usReferenceClock; //In 10Khz unit 2686 USHORT usPM_RTS_Location; //RTS PM4 starting location in ROM in 1Kb unit 2687 UCHAR ucPM_RTS_StreamSize; //RTS PM4 packets in Kb unit 2688 UCHAR ucDesign_ID; //Indicate what is the board design 2689 UCHAR ucMemoryModule_ID; //Indicate what is the board design 2690 }ATOM_FIRMWARE_INFO_V1_3; 2691 2692 typedef struct _ATOM_FIRMWARE_INFO_V1_4 2693 { 2694 ATOM_COMMON_TABLE_HEADER sHeader; 2695 ULONG ulFirmwareRevision; 2696 ULONG ulDefaultEngineClock; //In 10Khz unit 2697 ULONG ulDefaultMemoryClock; //In 10Khz unit 2698 ULONG ulDriverTargetEngineClock; //In 10Khz unit 2699 ULONG ulDriverTargetMemoryClock; //In 10Khz unit 2700 ULONG ulMaxEngineClockPLL_Output; //In 10Khz unit 2701 ULONG ulMaxMemoryClockPLL_Output; //In 10Khz unit 2702 ULONG ulMaxPixelClockPLL_Output; //In 10Khz unit 2703 ULONG ulASICMaxEngineClock; //In 10Khz unit 2704 ULONG ulASICMaxMemoryClock; //In 10Khz unit 2705 UCHAR ucASICMaxTemperature; 2706 UCHAR ucMinAllowedBL_Level; 2707 USHORT usBootUpVDDCVoltage; //In MV unit 2708 USHORT usLcdMinPixelClockPLL_Output; // In MHz unit 2709 USHORT usLcdMaxPixelClockPLL_Output; // In MHz unit 2710 ULONG ul3DAccelerationEngineClock;//In 10Khz unit 2711 ULONG ulMinPixelClockPLL_Output; //In 10Khz unit 2712 USHORT usMinEngineClockPLL_Input; //In 10Khz unit 2713 USHORT usMaxEngineClockPLL_Input; //In 10Khz unit 2714 USHORT usMinEngineClockPLL_Output; //In 10Khz unit 2715 USHORT usMinMemoryClockPLL_Input; //In 10Khz unit 2716 USHORT usMaxMemoryClockPLL_Input; //In 10Khz unit 2717 USHORT usMinMemoryClockPLL_Output; //In 10Khz unit 2718 USHORT usMaxPixelClock; //In 10Khz unit, Max. Pclk 2719 USHORT usMinPixelClockPLL_Input; //In 10Khz unit 2720 USHORT usMaxPixelClockPLL_Input; //In 10Khz unit 2721 USHORT usMinPixelClockPLL_Output; //In 10Khz unit - lower 16bit of ulMinPixelClockPLL_Output 2722 ATOM_FIRMWARE_CAPABILITY_ACCESS usFirmwareCapability; 2723 USHORT usReferenceClock; //In 10Khz unit 2724 USHORT usPM_RTS_Location; //RTS PM4 starting location in ROM in 1Kb unit 2725 UCHAR ucPM_RTS_StreamSize; //RTS PM4 packets in Kb unit 2726 UCHAR ucDesign_ID; //Indicate what is the board design 2727 UCHAR ucMemoryModule_ID; //Indicate what is the board design 2728 }ATOM_FIRMWARE_INFO_V1_4; 2729 2730 //the structure below to be used from Cypress 2731 typedef struct _ATOM_FIRMWARE_INFO_V2_1 2732 { 2733 ATOM_COMMON_TABLE_HEADER sHeader; 2734 ULONG ulFirmwareRevision; 2735 ULONG ulDefaultEngineClock; //In 10Khz unit 2736 ULONG ulDefaultMemoryClock; //In 10Khz unit 2737 ULONG ulReserved1; 2738 ULONG ulReserved2; 2739 ULONG ulMaxEngineClockPLL_Output; //In 10Khz unit 2740 ULONG ulMaxMemoryClockPLL_Output; //In 10Khz unit 2741 ULONG ulMaxPixelClockPLL_Output; //In 10Khz unit 2742 ULONG ulBinaryAlteredInfo; //Was ulASICMaxEngineClock 2743 ULONG ulDefaultDispEngineClkFreq; //In 10Khz unit 2744 UCHAR ucReserved1; //Was ucASICMaxTemperature; 2745 UCHAR ucMinAllowedBL_Level; 2746 USHORT usBootUpVDDCVoltage; //In MV unit 2747 USHORT usLcdMinPixelClockPLL_Output; // In MHz unit 2748 USHORT usLcdMaxPixelClockPLL_Output; // In MHz unit 2749 ULONG ulReserved4; //Was ulAsicMaximumVoltage 2750 ULONG ulMinPixelClockPLL_Output; //In 10Khz unit 2751 USHORT usMinEngineClockPLL_Input; //In 10Khz unit 2752 USHORT usMaxEngineClockPLL_Input; //In 10Khz unit 2753 USHORT usMinEngineClockPLL_Output; //In 10Khz unit 2754 USHORT usMinMemoryClockPLL_Input; //In 10Khz unit 2755 USHORT usMaxMemoryClockPLL_Input; //In 10Khz unit 2756 USHORT usMinMemoryClockPLL_Output; //In 10Khz unit 2757 USHORT usMaxPixelClock; //In 10Khz unit, Max. Pclk 2758 USHORT usMinPixelClockPLL_Input; //In 10Khz unit 2759 USHORT usMaxPixelClockPLL_Input; //In 10Khz unit 2760 USHORT usMinPixelClockPLL_Output; //In 10Khz unit - lower 16bit of ulMinPixelClockPLL_Output 2761 ATOM_FIRMWARE_CAPABILITY_ACCESS usFirmwareCapability; 2762 USHORT usCoreReferenceClock; //In 10Khz unit 2763 USHORT usMemoryReferenceClock; //In 10Khz unit 2764 USHORT usUniphyDPModeExtClkFreq; //In 10Khz unit, if it is 0, In DP Mode Uniphy Input clock from internal PPLL, otherwise Input clock from external Spread clock 2765 UCHAR ucMemoryModule_ID; //Indicate what is the board design 2766 UCHAR ucReserved4[3]; 2767 2768 }ATOM_FIRMWARE_INFO_V2_1; 2769 2770 //the structure below to be used from NI 2771 //ucTableFormatRevision=2 2772 //ucTableContentRevision=2 2773 2774 typedef struct _PRODUCT_BRANDING 2775 { 2776 UCHAR ucEMBEDDED_CAP:2; // Bit[1:0] Embedded feature level 2777 UCHAR ucReserved:2; // Bit[3:2] Reserved 2778 UCHAR ucBRANDING_ID:4; // Bit[7:4] Branding ID 2779 }PRODUCT_BRANDING; 2780 2781 typedef struct _ATOM_FIRMWARE_INFO_V2_2 2782 { 2783 ATOM_COMMON_TABLE_HEADER sHeader; 2784 ULONG ulFirmwareRevision; 2785 ULONG ulDefaultEngineClock; //In 10Khz unit 2786 ULONG ulDefaultMemoryClock; //In 10Khz unit 2787 ULONG ulSPLL_OutputFreq; //In 10Khz unit 2788 ULONG ulGPUPLL_OutputFreq; //In 10Khz unit 2789 ULONG ulReserved1; //Was ulMaxEngineClockPLL_Output; //In 10Khz unit* 2790 ULONG ulReserved2; //Was ulMaxMemoryClockPLL_Output; //In 10Khz unit* 2791 ULONG ulMaxPixelClockPLL_Output; //In 10Khz unit 2792 ULONG ulBinaryAlteredInfo; //Was ulASICMaxEngineClock ? 2793 ULONG ulDefaultDispEngineClkFreq; //In 10Khz unit. This is the frequency before DCDTO, corresponding to usBootUpVDDCVoltage. 2794 UCHAR ucReserved3; //Was ucASICMaxTemperature; 2795 UCHAR ucMinAllowedBL_Level; 2796 USHORT usBootUpVDDCVoltage; //In MV unit 2797 USHORT usLcdMinPixelClockPLL_Output; // In MHz unit 2798 USHORT usLcdMaxPixelClockPLL_Output; // In MHz unit 2799 ULONG ulReserved4; //Was ulAsicMaximumVoltage 2800 ULONG ulMinPixelClockPLL_Output; //In 10Khz unit 2801 UCHAR ucRemoteDisplayConfig; 2802 UCHAR ucReserved5[3]; //Was usMinEngineClockPLL_Input and usMaxEngineClockPLL_Input 2803 ULONG ulReserved6; //Was usMinEngineClockPLL_Output and usMinMemoryClockPLL_Input 2804 ULONG ulReserved7; //Was usMaxMemoryClockPLL_Input and usMinMemoryClockPLL_Output 2805 USHORT usReserved11; //Was usMaxPixelClock; //In 10Khz unit, Max. Pclk used only for DAC 2806 USHORT usMinPixelClockPLL_Input; //In 10Khz unit 2807 USHORT usMaxPixelClockPLL_Input; //In 10Khz unit 2808 USHORT usBootUpVDDCIVoltage; //In unit of mv; Was usMinPixelClockPLL_Output; 2809 ATOM_FIRMWARE_CAPABILITY_ACCESS usFirmwareCapability; 2810 USHORT usCoreReferenceClock; //In 10Khz unit 2811 USHORT usMemoryReferenceClock; //In 10Khz unit 2812 USHORT usUniphyDPModeExtClkFreq; //In 10Khz unit, if it is 0, In DP Mode Uniphy Input clock from internal PPLL, otherwise Input clock from external Spread clock 2813 UCHAR ucMemoryModule_ID; //Indicate what is the board design 2814 UCHAR ucCoolingSolution_ID; //0: Air cooling; 1: Liquid cooling ... [COOLING_SOLUTION] 2815 PRODUCT_BRANDING ucProductBranding; // Bit[7:4]ucBRANDING_ID: Branding ID, Bit[3:2]ucReserved: Reserved, Bit[1:0]ucEMBEDDED_CAP: Embedded feature level. 2816 UCHAR ucReserved9; 2817 USHORT usBootUpMVDDCVoltage; //In unit of mv; Was usMinPixelClockPLL_Output; 2818 USHORT usBootUpVDDGFXVoltage; //In unit of mv; 2819 ULONG ulReserved10[3]; // New added comparing to previous version 2820 }ATOM_FIRMWARE_INFO_V2_2; 2821 2822 #define ATOM_FIRMWARE_INFO_LAST ATOM_FIRMWARE_INFO_V2_2 2823 2824 2825 // definition of ucRemoteDisplayConfig 2826 #define REMOTE_DISPLAY_DISABLE 0x00 2827 #define REMOTE_DISPLAY_ENABLE 0x01 2828 2829 /****************************************************************************/ 2830 // Structures used in IntegratedSystemInfoTable 2831 /****************************************************************************/ 2832 #define IGP_CAP_FLAG_DYNAMIC_CLOCK_EN 0x2 2833 #define IGP_CAP_FLAG_AC_CARD 0x4 2834 #define IGP_CAP_FLAG_SDVO_CARD 0x8 2835 #define IGP_CAP_FLAG_POSTDIV_BY_2_MODE 0x10 2836 2837 typedef struct _ATOM_INTEGRATED_SYSTEM_INFO 2838 { 2839 ATOM_COMMON_TABLE_HEADER sHeader; 2840 ULONG ulBootUpEngineClock; //in 10kHz unit 2841 ULONG ulBootUpMemoryClock; //in 10kHz unit 2842 ULONG ulMaxSystemMemoryClock; //in 10kHz unit 2843 ULONG ulMinSystemMemoryClock; //in 10kHz unit 2844 UCHAR ucNumberOfCyclesInPeriodHi; 2845 UCHAR ucLCDTimingSel; //=0:not valid.!=0 sel this timing descriptor from LCD EDID. 2846 USHORT usReserved1; 2847 USHORT usInterNBVoltageLow; //An intermidiate PMW value to set the voltage 2848 USHORT usInterNBVoltageHigh; //Another intermidiate PMW value to set the voltage 2849 ULONG ulReserved[2]; 2850 2851 USHORT usFSBClock; //In MHz unit 2852 USHORT usCapabilityFlag; //Bit0=1 indicates the fake HDMI support,Bit1=0/1 for Dynamic clocking dis/enable 2853 //Bit[3:2]== 0:No PCIE card, 1:AC card, 2:SDVO card 2854 //Bit[4]==1: P/2 mode, ==0: P/1 mode 2855 USHORT usPCIENBCfgReg7; //bit[7:0]=MUX_Sel, bit[9:8]=MUX_SEL_LEVEL2, bit[10]=Lane_Reversal 2856 USHORT usK8MemoryClock; //in MHz unit 2857 USHORT usK8SyncStartDelay; //in 0.01 us unit 2858 USHORT usK8DataReturnTime; //in 0.01 us unit 2859 UCHAR ucMaxNBVoltage; 2860 UCHAR ucMinNBVoltage; 2861 UCHAR ucMemoryType; //[7:4]=1:DDR1;=2:DDR2;=3:DDR3.[3:0] is reserved 2862 UCHAR ucNumberOfCyclesInPeriod; //CG.FVTHROT_PWM_CTRL_REG0.NumberOfCyclesInPeriod 2863 UCHAR ucStartingPWM_HighTime; //CG.FVTHROT_PWM_CTRL_REG0.StartingPWM_HighTime 2864 UCHAR ucHTLinkWidth; //16 bit vs. 8 bit 2865 UCHAR ucMaxNBVoltageHigh; 2866 UCHAR ucMinNBVoltageHigh; 2867 }ATOM_INTEGRATED_SYSTEM_INFO; 2868 2869 /* Explanation on entries in ATOM_INTEGRATED_SYSTEM_INFO 2870 ulBootUpMemoryClock: For Intel IGP,it's the UMA system memory clock 2871 For AMD IGP,it's 0 if no SidePort memory installed or it's the boot-up SidePort memory clock 2872 ulMaxSystemMemoryClock: For Intel IGP,it's the Max freq from memory SPD if memory runs in ASYNC mode or otherwise (SYNC mode) it's 0 2873 For AMD IGP,for now this can be 0 2874 ulMinSystemMemoryClock: For Intel IGP,it's 133MHz if memory runs in ASYNC mode or otherwise (SYNC mode) it's 0 2875 For AMD IGP,for now this can be 0 2876 2877 usFSBClock: For Intel IGP,it's FSB Freq 2878 For AMD IGP,it's HT Link Speed 2879 2880 usK8MemoryClock: For AMD IGP only. For RevF CPU, set it to 200 2881 usK8SyncStartDelay: For AMD IGP only. Memory access latency in K8, required for watermark calculation 2882 usK8DataReturnTime: For AMD IGP only. Memory access latency in K8, required for watermark calculation 2883 2884 VC:Voltage Control 2885 ucMaxNBVoltage: Voltage regulator dependent PWM value. Low 8 bits of the value for the max voltage.Set this one to 0xFF if VC without PWM. Set this to 0x0 if no VC at all. 2886 ucMinNBVoltage: Voltage regulator dependent PWM value. Low 8 bits of the value for the min voltage.Set this one to 0x00 if VC without PWM or no VC at all. 2887 2888 ucNumberOfCyclesInPeriod: Indicate how many cycles when PWM duty is 100%. low 8 bits of the value. 2889 ucNumberOfCyclesInPeriodHi: Indicate how many cycles when PWM duty is 100%. high 8 bits of the value.If the PWM has an inverter,set bit [7]==1,otherwise set it 0 2890 2891 ucMaxNBVoltageHigh: Voltage regulator dependent PWM value. High 8 bits of the value for the max voltage.Set this one to 0xFF if VC without PWM. Set this to 0x0 if no VC at all. 2892 ucMinNBVoltageHigh: Voltage regulator dependent PWM value. High 8 bits of the value for the min voltage.Set this one to 0x00 if VC without PWM or no VC at all. 2893 2894 2895 usInterNBVoltageLow: Voltage regulator dependent PWM value. The value makes the the voltage >=Min NB voltage but <=InterNBVoltageHigh. Set this to 0x0000 if VC without PWM or no VC at all. 2896 usInterNBVoltageHigh: Voltage regulator dependent PWM value. The value makes the the voltage >=InterNBVoltageLow but <=Max NB voltage.Set this to 0x0000 if VC without PWM or no VC at all. 2897 */ 2898 2899 2900 /* 2901 The following IGP table is introduced from RS780, which is supposed to be put by SBIOS in FB before IGP VBIOS starts VPOST; 2902 Then VBIOS will copy the whole structure to its image so all GPU SW components can access this data structure to get whatever they need. 2903 The enough reservation should allow us to never change table revisions. Whenever needed, a GPU SW component can use reserved portion for new data entries. 2904 2905 SW components can access the IGP system infor structure in the same way as before 2906 */ 2907 2908 2909 typedef struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 2910 { 2911 ATOM_COMMON_TABLE_HEADER sHeader; 2912 ULONG ulBootUpEngineClock; //in 10kHz unit 2913 ULONG ulReserved1[2]; //must be 0x0 for the reserved 2914 ULONG ulBootUpUMAClock; //in 10kHz unit 2915 ULONG ulBootUpSidePortClock; //in 10kHz unit 2916 ULONG ulMinSidePortClock; //in 10kHz unit 2917 ULONG ulReserved2[6]; //must be 0x0 for the reserved 2918 ULONG ulSystemConfig; //see explanation below 2919 ULONG ulBootUpReqDisplayVector; 2920 ULONG ulOtherDisplayMisc; 2921 ULONG ulDDISlot1Config; 2922 ULONG ulDDISlot2Config; 2923 UCHAR ucMemoryType; //[3:0]=1:DDR1;=2:DDR2;=3:DDR3.[7:4] is reserved 2924 UCHAR ucUMAChannelNumber; 2925 UCHAR ucDockingPinBit; 2926 UCHAR ucDockingPinPolarity; 2927 ULONG ulDockingPinCFGInfo; 2928 ULONG ulCPUCapInfo; 2929 USHORT usNumberOfCyclesInPeriod; 2930 USHORT usMaxNBVoltage; 2931 USHORT usMinNBVoltage; 2932 USHORT usBootUpNBVoltage; 2933 ULONG ulHTLinkFreq; //in 10Khz 2934 USHORT usMinHTLinkWidth; 2935 USHORT usMaxHTLinkWidth; 2936 USHORT usUMASyncStartDelay; 2937 USHORT usUMADataReturnTime; 2938 USHORT usLinkStatusZeroTime; 2939 USHORT usDACEfuse; //for storing badgap value (for RS880 only) 2940 ULONG ulHighVoltageHTLinkFreq; // in 10Khz 2941 ULONG ulLowVoltageHTLinkFreq; // in 10Khz 2942 USHORT usMaxUpStreamHTLinkWidth; 2943 USHORT usMaxDownStreamHTLinkWidth; 2944 USHORT usMinUpStreamHTLinkWidth; 2945 USHORT usMinDownStreamHTLinkWidth; 2946 USHORT usFirmwareVersion; //0 means FW is not supported. Otherwise it's the FW version loaded by SBIOS and driver should enable FW. 2947 USHORT usFullT0Time; // Input to calculate minimum HT link change time required by NB P-State. Unit is 0.01us. 2948 ULONG ulReserved3[96]; //must be 0x0 2949 }ATOM_INTEGRATED_SYSTEM_INFO_V2; 2950 2951 /* 2952 ulBootUpEngineClock: Boot-up Engine Clock in 10Khz; 2953 ulBootUpUMAClock: Boot-up UMA Clock in 10Khz; it must be 0x0 when UMA is not present 2954 ulBootUpSidePortClock: Boot-up SidePort Clock in 10Khz; it must be 0x0 when SidePort Memory is not present,this could be equal to or less than maximum supported Sideport memory clock 2955 2956 ulSystemConfig: 2957 Bit[0]=1: PowerExpress mode =0 Non-PowerExpress mode; 2958 Bit[1]=1: system boots up at AMD overdrived state or user customized mode. In this case, driver will just stick to this boot-up mode. No other PowerPlay state 2959 =0: system boots up at driver control state. Power state depends on PowerPlay table. 2960 Bit[2]=1: PWM method is used on NB voltage control. =0: GPIO method is used. 2961 Bit[3]=1: Only one power state(Performance) will be supported. 2962 =0: Multiple power states supported from PowerPlay table. 2963 Bit[4]=1: CLMC is supported and enabled on current system. 2964 =0: CLMC is not supported or enabled on current system. SBIOS need to support HT link/freq change through ATIF interface. 2965 Bit[5]=1: Enable CDLW for all driver control power states. Max HT width is from SBIOS, while Min HT width is determined by display requirement. 2966 =0: CDLW is disabled. If CLMC is enabled case, Min HT width will be set equal to Max HT width. If CLMC disabled case, Max HT width will be applied. 2967 Bit[6]=1: High Voltage requested for all power states. In this case, voltage will be forced at 1.1v and powerplay table voltage drop/throttling request will be ignored. 2968 =0: Voltage settings is determined by powerplay table. 2969 Bit[7]=1: Enable CLMC as hybrid Mode. CDLD and CILR will be disabled in this case and we're using legacy C1E. This is workaround for CPU(Griffin) performance issue. 2970 =0: Enable CLMC as regular mode, CDLD and CILR will be enabled. 2971 Bit[8]=1: CDLF is supported and enabled on current system. 2972 =0: CDLF is not supported or enabled on current system. 2973 Bit[9]=1: DLL Shut Down feature is enabled on current system. 2974 =0: DLL Shut Down feature is not enabled or supported on current system. 2975 2976 ulBootUpReqDisplayVector: This dword is a bit vector indicates what display devices are requested during boot-up. Refer to ATOM_DEVICE_xxx_SUPPORT for the bit vector definitions. 2977 2978 ulOtherDisplayMisc: [15:8]- Bootup LCD Expansion selection; 0-center, 1-full panel size expansion; 2979 [7:0] - BootupTV standard selection; This is a bit vector to indicate what TV standards are supported by the system. Refer to ucTVSuppportedStd definition; 2980 2981 ulDDISlot1Config: Describes the PCIE lane configuration on this DDI PCIE slot (ADD2 card) or connector (Mobile design). 2982 [3:0] - Bit vector to indicate PCIE lane config of the DDI slot/connector on chassis (bit 0=1 lane 3:0; bit 1=1 lane 7:4; bit 2=1 lane 11:8; bit 3=1 lane 15:12) 2983 [7:4] - Bit vector to indicate PCIE lane config of the same DDI slot/connector on docking station (bit 4=1 lane 3:0; bit 5=1 lane 7:4; bit 6=1 lane 11:8; bit 7=1 lane 15:12) 2984 When a DDI connector is not "paired" (meaming two connections mutualexclusive on chassis or docking, only one of them can be connected at one time. 2985 in both chassis and docking, SBIOS has to duplicate the same PCIE lane info from chassis to docking or vice versa. For example: 2986 one DDI connector is only populated in docking with PCIE lane 8-11, but there is no paired connection on chassis, SBIOS has to copy bit 6 to bit 2. 2987 2988 [15:8] - Lane configuration attribute; 2989 [23:16]- Connector type, possible value: 2990 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D 2991 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D 2992 CONNECTOR_OBJECT_ID_HDMI_TYPE_A 2993 CONNECTOR_OBJECT_ID_DISPLAYPORT 2994 CONNECTOR_OBJECT_ID_eDP 2995 [31:24]- Reserved 2996 2997 ulDDISlot2Config: Same as Slot1. 2998 ucMemoryType: SidePort memory type, set it to 0x0 when Sideport memory is not installed. Driver needs this info to change sideport memory clock. Not for display in CCC. 2999 For IGP, Hypermemory is the only memory type showed in CCC. 3000 3001 ucUMAChannelNumber: how many channels for the UMA; 3002 3003 ulDockingPinCFGInfo: [15:0]-Bus/Device/Function # to CFG to read this Docking Pin; [31:16]-reg offset in CFG to read this pin 3004 ucDockingPinBit: which bit in this register to read the pin status; 3005 ucDockingPinPolarity:Polarity of the pin when docked; 3006 3007 ulCPUCapInfo: [7:0]=1:Griffin;[7:0]=2:Greyhound;[7:0]=3:K8, [7:0]=4:Pharaoh, other bits reserved for now and must be 0x0 3008 3009 usNumberOfCyclesInPeriod:Indicate how many cycles when PWM duty is 100%. 3010 3011 usMaxNBVoltage:Max. voltage control value in either PWM or GPIO mode. 3012 usMinNBVoltage:Min. voltage control value in either PWM or GPIO mode. 3013 GPIO mode: both usMaxNBVoltage & usMinNBVoltage have a valid value ulSystemConfig.SYSTEM_CONFIG_USE_PWM_ON_VOLTAGE=0 3014 PWM mode: both usMaxNBVoltage & usMinNBVoltage have a valid value ulSystemConfig.SYSTEM_CONFIG_USE_PWM_ON_VOLTAGE=1 3015 GPU SW don't control mode: usMaxNBVoltage & usMinNBVoltage=0 and no care about ulSystemConfig.SYSTEM_CONFIG_USE_PWM_ON_VOLTAGE 3016 3017 usBootUpNBVoltage:Boot-up voltage regulator dependent PWM value. 3018 3019 3020 ulHTLinkFreq: Bootup HT link Frequency in 10Khz. 3021 usMinHTLinkWidth: Bootup minimum HT link width. If CDLW disabled, this is equal to usMaxHTLinkWidth. 3022 If CDLW enabled, both upstream and downstream width should be the same during bootup. 3023 usMaxHTLinkWidth: Bootup maximum HT link width. If CDLW disabled, this is equal to usMinHTLinkWidth. 3024 If CDLW enabled, both upstream and downstream width should be the same during bootup. 3025 3026 usUMASyncStartDelay: Memory access latency, required for watermark calculation 3027 usUMADataReturnTime: Memory access latency, required for watermark calculation 3028 usLinkStatusZeroTime:Memory access latency required for watermark calculation, set this to 0x0 for K8 CPU, set a proper value in 0.01 the unit of us 3029 for Griffin or Greyhound. SBIOS needs to convert to actual time by: 3030 if T0Ttime [5:4]=00b, then usLinkStatusZeroTime=T0Ttime [3:0]*0.1us (0.0 to 1.5us) 3031 if T0Ttime [5:4]=01b, then usLinkStatusZeroTime=T0Ttime [3:0]*0.5us (0.0 to 7.5us) 3032 if T0Ttime [5:4]=10b, then usLinkStatusZeroTime=T0Ttime [3:0]*2.0us (0.0 to 30us) 3033 if T0Ttime [5:4]=11b, and T0Ttime [3:0]=0x0 to 0xa, then usLinkStatusZeroTime=T0Ttime [3:0]*20us (0.0 to 200us) 3034 3035 ulHighVoltageHTLinkFreq: HT link frequency for power state with low voltage. If boot up runs in HT1, this must be 0. 3036 This must be less than or equal to ulHTLinkFreq(bootup frequency). 3037 ulLowVoltageHTLinkFreq: HT link frequency for power state with low voltage or voltage scaling 1.0v~1.1v. If boot up runs in HT1, this must be 0. 3038 This must be less than or equal to ulHighVoltageHTLinkFreq. 3039 3040 usMaxUpStreamHTLinkWidth: Asymmetric link width support in the future, to replace usMaxHTLinkWidth. Not used for now. 3041 usMaxDownStreamHTLinkWidth: same as above. 3042 usMinUpStreamHTLinkWidth: Asymmetric link width support in the future, to replace usMinHTLinkWidth. Not used for now. 3043 usMinDownStreamHTLinkWidth: same as above. 3044 */ 3045 3046 // ATOM_INTEGRATED_SYSTEM_INFO::ulCPUCapInfo - CPU type definition 3047 #define INTEGRATED_SYSTEM_INFO__UNKNOWN_CPU 0 3048 #define INTEGRATED_SYSTEM_INFO__AMD_CPU__GRIFFIN 1 3049 #define INTEGRATED_SYSTEM_INFO__AMD_CPU__GREYHOUND 2 3050 #define INTEGRATED_SYSTEM_INFO__AMD_CPU__K8 3 3051 #define INTEGRATED_SYSTEM_INFO__AMD_CPU__PHARAOH 4 3052 #define INTEGRATED_SYSTEM_INFO__AMD_CPU__OROCHI 5 3053 3054 #define INTEGRATED_SYSTEM_INFO__AMD_CPU__MAX_CODE INTEGRATED_SYSTEM_INFO__AMD_CPU__OROCHI // this deff reflects max defined CPU code 3055 3056 #define SYSTEM_CONFIG_POWEREXPRESS_ENABLE 0x00000001 3057 #define SYSTEM_CONFIG_RUN_AT_OVERDRIVE_ENGINE 0x00000002 3058 #define SYSTEM_CONFIG_USE_PWM_ON_VOLTAGE 0x00000004 3059 #define SYSTEM_CONFIG_PERFORMANCE_POWERSTATE_ONLY 0x00000008 3060 #define SYSTEM_CONFIG_CLMC_ENABLED 0x00000010 3061 #define SYSTEM_CONFIG_CDLW_ENABLED 0x00000020 3062 #define SYSTEM_CONFIG_HIGH_VOLTAGE_REQUESTED 0x00000040 3063 #define SYSTEM_CONFIG_CLMC_HYBRID_MODE_ENABLED 0x00000080 3064 #define SYSTEM_CONFIG_CDLF_ENABLED 0x00000100 3065 #define SYSTEM_CONFIG_DLL_SHUTDOWN_ENABLED 0x00000200 3066 3067 #define IGP_DDI_SLOT_LANE_CONFIG_MASK 0x000000FF 3068 3069 #define b0IGP_DDI_SLOT_LANE_MAP_MASK 0x0F 3070 #define b0IGP_DDI_SLOT_DOCKING_LANE_MAP_MASK 0xF0 3071 #define b0IGP_DDI_SLOT_CONFIG_LANE_0_3 0x01 3072 #define b0IGP_DDI_SLOT_CONFIG_LANE_4_7 0x02 3073 #define b0IGP_DDI_SLOT_CONFIG_LANE_8_11 0x04 3074 #define b0IGP_DDI_SLOT_CONFIG_LANE_12_15 0x08 3075 3076 #define IGP_DDI_SLOT_ATTRIBUTE_MASK 0x0000FF00 3077 #define IGP_DDI_SLOT_CONFIG_REVERSED 0x00000100 3078 #define b1IGP_DDI_SLOT_CONFIG_REVERSED 0x01 3079 3080 #define IGP_DDI_SLOT_CONNECTOR_TYPE_MASK 0x00FF0000 3081 3082 // IntegratedSystemInfoTable new Rev is V5 after V2, because of the real rev of V2 is v1.4. This rev is used for RR 3083 typedef struct _ATOM_INTEGRATED_SYSTEM_INFO_V5 3084 { 3085 ATOM_COMMON_TABLE_HEADER sHeader; 3086 ULONG ulBootUpEngineClock; //in 10kHz unit 3087 ULONG ulDentistVCOFreq; //Dentist VCO clock in 10kHz unit, the source of GPU SCLK, LCLK, UCLK and VCLK. 3088 ULONG ulLClockFreq; //GPU Lclk freq in 10kHz unit, have relationship with NCLK in NorthBridge 3089 ULONG ulBootUpUMAClock; //in 10kHz unit 3090 ULONG ulReserved1[8]; //must be 0x0 for the reserved 3091 ULONG ulBootUpReqDisplayVector; 3092 ULONG ulOtherDisplayMisc; 3093 ULONG ulReserved2[4]; //must be 0x0 for the reserved 3094 ULONG ulSystemConfig; //TBD 3095 ULONG ulCPUCapInfo; //TBD 3096 USHORT usMaxNBVoltage; //high NB voltage, calculated using current VDDNB (D24F2xDC) and VDDNB offset fuse; 3097 USHORT usMinNBVoltage; //low NB voltage, calculated using current VDDNB (D24F2xDC) and VDDNB offset fuse; 3098 USHORT usBootUpNBVoltage; //boot up NB voltage 3099 UCHAR ucHtcTmpLmt; //bit [22:16] of D24F3x64 Hardware Thermal Control (HTC) Register, may not be needed, TBD 3100 UCHAR ucTjOffset; //bit [28:22] of D24F3xE4 Thermtrip Status Register,may not be needed, TBD 3101 ULONG ulReserved3[4]; //must be 0x0 for the reserved 3102 ULONG ulDDISlot1Config; //see above ulDDISlot1Config definition 3103 ULONG ulDDISlot2Config; 3104 ULONG ulDDISlot3Config; 3105 ULONG ulDDISlot4Config; 3106 ULONG ulReserved4[4]; //must be 0x0 for the reserved 3107 UCHAR ucMemoryType; //[3:0]=1:DDR1;=2:DDR2;=3:DDR3.[7:4] is reserved 3108 UCHAR ucUMAChannelNumber; 3109 USHORT usReserved; 3110 ULONG ulReserved5[4]; //must be 0x0 for the reserved 3111 ULONG ulCSR_M3_ARB_CNTL_DEFAULT[10];//arrays with values for CSR M3 arbiter for default 3112 ULONG ulCSR_M3_ARB_CNTL_UVD[10]; //arrays with values for CSR M3 arbiter for UVD playback 3113 ULONG ulCSR_M3_ARB_CNTL_FS3D[10];//arrays with values for CSR M3 arbiter for Full Screen 3D applications 3114 ULONG ulReserved6[61]; //must be 0x0 3115 }ATOM_INTEGRATED_SYSTEM_INFO_V5; 3116 3117 3118 3119 /****************************************************************************/ 3120 // Structure used in GPUVirtualizationInfoTable 3121 /****************************************************************************/ 3122 typedef struct _ATOM_GPU_VIRTUALIZATION_INFO_V2_1 3123 { 3124 ATOM_COMMON_TABLE_HEADER sHeader; 3125 ULONG ulMCUcodeRomStartAddr; 3126 ULONG ulMCUcodeLength; 3127 ULONG ulSMCUcodeRomStartAddr; 3128 ULONG ulSMCUcodeLength; 3129 ULONG ulRLCVUcodeRomStartAddr; 3130 ULONG ulRLCVUcodeLength; 3131 ULONG ulTOCUcodeStartAddr; 3132 ULONG ulTOCUcodeLength; 3133 ULONG ulSMCPatchTableStartAddr; 3134 ULONG ulSmcPatchTableLength; 3135 ULONG ulSystemFlag; 3136 }ATOM_GPU_VIRTUALIZATION_INFO_V2_1; 3137 3138 3139 #define ATOM_CRT_INT_ENCODER1_INDEX 0x00000000 3140 #define ATOM_LCD_INT_ENCODER1_INDEX 0x00000001 3141 #define ATOM_TV_INT_ENCODER1_INDEX 0x00000002 3142 #define ATOM_DFP_INT_ENCODER1_INDEX 0x00000003 3143 #define ATOM_CRT_INT_ENCODER2_INDEX 0x00000004 3144 #define ATOM_LCD_EXT_ENCODER1_INDEX 0x00000005 3145 #define ATOM_TV_EXT_ENCODER1_INDEX 0x00000006 3146 #define ATOM_DFP_EXT_ENCODER1_INDEX 0x00000007 3147 #define ATOM_CV_INT_ENCODER1_INDEX 0x00000008 3148 #define ATOM_DFP_INT_ENCODER2_INDEX 0x00000009 3149 #define ATOM_CRT_EXT_ENCODER1_INDEX 0x0000000A 3150 #define ATOM_CV_EXT_ENCODER1_INDEX 0x0000000B 3151 #define ATOM_DFP_INT_ENCODER3_INDEX 0x0000000C 3152 #define ATOM_DFP_INT_ENCODER4_INDEX 0x0000000D 3153 3154 // define ASIC internal encoder id ( bit vector ), used for CRTC_SourceSelTable 3155 #define ASIC_INT_DAC1_ENCODER_ID 0x00 3156 #define ASIC_INT_TV_ENCODER_ID 0x02 3157 #define ASIC_INT_DIG1_ENCODER_ID 0x03 3158 #define ASIC_INT_DAC2_ENCODER_ID 0x04 3159 #define ASIC_EXT_TV_ENCODER_ID 0x06 3160 #define ASIC_INT_DVO_ENCODER_ID 0x07 3161 #define ASIC_INT_DIG2_ENCODER_ID 0x09 3162 #define ASIC_EXT_DIG_ENCODER_ID 0x05 3163 #define ASIC_EXT_DIG2_ENCODER_ID 0x08 3164 #define ASIC_INT_DIG3_ENCODER_ID 0x0a 3165 #define ASIC_INT_DIG4_ENCODER_ID 0x0b 3166 #define ASIC_INT_DIG5_ENCODER_ID 0x0c 3167 #define ASIC_INT_DIG6_ENCODER_ID 0x0d 3168 #define ASIC_INT_DIG7_ENCODER_ID 0x0e 3169 3170 //define Encoder attribute 3171 #define ATOM_ANALOG_ENCODER 0 3172 #define ATOM_DIGITAL_ENCODER 1 3173 #define ATOM_DP_ENCODER 2 3174 3175 #define ATOM_ENCODER_ENUM_MASK 0x70 3176 #define ATOM_ENCODER_ENUM_ID1 0x00 3177 #define ATOM_ENCODER_ENUM_ID2 0x10 3178 #define ATOM_ENCODER_ENUM_ID3 0x20 3179 #define ATOM_ENCODER_ENUM_ID4 0x30 3180 #define ATOM_ENCODER_ENUM_ID5 0x40 3181 #define ATOM_ENCODER_ENUM_ID6 0x50 3182 3183 #define ATOM_DEVICE_CRT1_INDEX 0x00000000 3184 #define ATOM_DEVICE_LCD1_INDEX 0x00000001 3185 #define ATOM_DEVICE_TV1_INDEX 0x00000002 3186 #define ATOM_DEVICE_DFP1_INDEX 0x00000003 3187 #define ATOM_DEVICE_CRT2_INDEX 0x00000004 3188 #define ATOM_DEVICE_LCD2_INDEX 0x00000005 3189 #define ATOM_DEVICE_DFP6_INDEX 0x00000006 3190 #define ATOM_DEVICE_DFP2_INDEX 0x00000007 3191 #define ATOM_DEVICE_CV_INDEX 0x00000008 3192 #define ATOM_DEVICE_DFP3_INDEX 0x00000009 3193 #define ATOM_DEVICE_DFP4_INDEX 0x0000000A 3194 #define ATOM_DEVICE_DFP5_INDEX 0x0000000B 3195 3196 #define ATOM_DEVICE_RESERVEDC_INDEX 0x0000000C 3197 #define ATOM_DEVICE_RESERVEDD_INDEX 0x0000000D 3198 #define ATOM_DEVICE_RESERVEDE_INDEX 0x0000000E 3199 #define ATOM_DEVICE_RESERVEDF_INDEX 0x0000000F 3200 #define ATOM_MAX_SUPPORTED_DEVICE_INFO (ATOM_DEVICE_DFP3_INDEX+1) 3201 #define ATOM_MAX_SUPPORTED_DEVICE_INFO_2 ATOM_MAX_SUPPORTED_DEVICE_INFO 3202 #define ATOM_MAX_SUPPORTED_DEVICE_INFO_3 (ATOM_DEVICE_DFP5_INDEX + 1 ) 3203 3204 #define ATOM_MAX_SUPPORTED_DEVICE (ATOM_DEVICE_RESERVEDF_INDEX+1) 3205 3206 #define ATOM_DEVICE_CRT1_SUPPORT (0x1L << ATOM_DEVICE_CRT1_INDEX ) 3207 #define ATOM_DEVICE_LCD1_SUPPORT (0x1L << ATOM_DEVICE_LCD1_INDEX ) 3208 #define ATOM_DEVICE_TV1_SUPPORT (0x1L << ATOM_DEVICE_TV1_INDEX ) 3209 #define ATOM_DEVICE_DFP1_SUPPORT (0x1L << ATOM_DEVICE_DFP1_INDEX ) 3210 #define ATOM_DEVICE_CRT2_SUPPORT (0x1L << ATOM_DEVICE_CRT2_INDEX ) 3211 #define ATOM_DEVICE_LCD2_SUPPORT (0x1L << ATOM_DEVICE_LCD2_INDEX ) 3212 #define ATOM_DEVICE_DFP6_SUPPORT (0x1L << ATOM_DEVICE_DFP6_INDEX ) 3213 #define ATOM_DEVICE_DFP2_SUPPORT (0x1L << ATOM_DEVICE_DFP2_INDEX ) 3214 #define ATOM_DEVICE_CV_SUPPORT (0x1L << ATOM_DEVICE_CV_INDEX ) 3215 #define ATOM_DEVICE_DFP3_SUPPORT (0x1L << ATOM_DEVICE_DFP3_INDEX ) 3216 #define ATOM_DEVICE_DFP4_SUPPORT (0x1L << ATOM_DEVICE_DFP4_INDEX ) 3217 #define ATOM_DEVICE_DFP5_SUPPORT (0x1L << ATOM_DEVICE_DFP5_INDEX ) 3218 3219 3220 #define ATOM_DEVICE_CRT_SUPPORT (ATOM_DEVICE_CRT1_SUPPORT | ATOM_DEVICE_CRT2_SUPPORT) 3221 #define ATOM_DEVICE_DFP_SUPPORT (ATOM_DEVICE_DFP1_SUPPORT | ATOM_DEVICE_DFP2_SUPPORT | ATOM_DEVICE_DFP3_SUPPORT | ATOM_DEVICE_DFP4_SUPPORT | ATOM_DEVICE_DFP5_SUPPORT | ATOM_DEVICE_DFP6_SUPPORT) 3222 #define ATOM_DEVICE_TV_SUPPORT ATOM_DEVICE_TV1_SUPPORT 3223 #define ATOM_DEVICE_LCD_SUPPORT (ATOM_DEVICE_LCD1_SUPPORT | ATOM_DEVICE_LCD2_SUPPORT) 3224 3225 #define ATOM_DEVICE_CONNECTOR_TYPE_MASK 0x000000F0 3226 #define ATOM_DEVICE_CONNECTOR_TYPE_SHIFT 0x00000004 3227 #define ATOM_DEVICE_CONNECTOR_VGA 0x00000001 3228 #define ATOM_DEVICE_CONNECTOR_DVI_I 0x00000002 3229 #define ATOM_DEVICE_CONNECTOR_DVI_D 0x00000003 3230 #define ATOM_DEVICE_CONNECTOR_DVI_A 0x00000004 3231 #define ATOM_DEVICE_CONNECTOR_SVIDEO 0x00000005 3232 #define ATOM_DEVICE_CONNECTOR_COMPOSITE 0x00000006 3233 #define ATOM_DEVICE_CONNECTOR_LVDS 0x00000007 3234 #define ATOM_DEVICE_CONNECTOR_DIGI_LINK 0x00000008 3235 #define ATOM_DEVICE_CONNECTOR_SCART 0x00000009 3236 #define ATOM_DEVICE_CONNECTOR_HDMI_TYPE_A 0x0000000A 3237 #define ATOM_DEVICE_CONNECTOR_HDMI_TYPE_B 0x0000000B 3238 #define ATOM_DEVICE_CONNECTOR_CASE_1 0x0000000E 3239 #define ATOM_DEVICE_CONNECTOR_DISPLAYPORT 0x0000000F 3240 3241 3242 #define ATOM_DEVICE_DAC_INFO_MASK 0x0000000F 3243 #define ATOM_DEVICE_DAC_INFO_SHIFT 0x00000000 3244 #define ATOM_DEVICE_DAC_INFO_NODAC 0x00000000 3245 #define ATOM_DEVICE_DAC_INFO_DACA 0x00000001 3246 #define ATOM_DEVICE_DAC_INFO_DACB 0x00000002 3247 #define ATOM_DEVICE_DAC_INFO_EXDAC 0x00000003 3248 3249 #define ATOM_DEVICE_I2C_ID_NOI2C 0x00000000 3250 3251 #define ATOM_DEVICE_I2C_LINEMUX_MASK 0x0000000F 3252 #define ATOM_DEVICE_I2C_LINEMUX_SHIFT 0x00000000 3253 3254 #define ATOM_DEVICE_I2C_ID_MASK 0x00000070 3255 #define ATOM_DEVICE_I2C_ID_SHIFT 0x00000004 3256 #define ATOM_DEVICE_I2C_ID_IS_FOR_NON_MM_USE 0x00000001 3257 #define ATOM_DEVICE_I2C_ID_IS_FOR_MM_USE 0x00000002 3258 #define ATOM_DEVICE_I2C_ID_IS_FOR_SDVO_USE 0x00000003 //For IGP RS600 3259 #define ATOM_DEVICE_I2C_ID_IS_FOR_DAC_SCL 0x00000004 //For IGP RS690 3260 3261 #define ATOM_DEVICE_I2C_HARDWARE_CAP_MASK 0x00000080 3262 #define ATOM_DEVICE_I2C_HARDWARE_CAP_SHIFT 0x00000007 3263 #define ATOM_DEVICE_USES_SOFTWARE_ASSISTED_I2C 0x00000000 3264 #define ATOM_DEVICE_USES_HARDWARE_ASSISTED_I2C 0x00000001 3265 3266 // usDeviceSupport: 3267 // Bits0 = 0 - no CRT1 support= 1- CRT1 is supported 3268 // Bit 1 = 0 - no LCD1 support= 1- LCD1 is supported 3269 // Bit 2 = 0 - no TV1 support= 1- TV1 is supported 3270 // Bit 3 = 0 - no DFP1 support= 1- DFP1 is supported 3271 // Bit 4 = 0 - no CRT2 support= 1- CRT2 is supported 3272 // Bit 5 = 0 - no LCD2 support= 1- LCD2 is supported 3273 // Bit 6 = 0 - no DFP6 support= 1- DFP6 is supported 3274 // Bit 7 = 0 - no DFP2 support= 1- DFP2 is supported 3275 // Bit 8 = 0 - no CV support= 1- CV is supported 3276 // Bit 9 = 0 - no DFP3 support= 1- DFP3 is supported 3277 // Bit 10= 0 - no DFP4 support= 1- DFP4 is supported 3278 // Bit 11= 0 - no DFP5 support= 1- DFP5 is supported 3279 // 3280 // 3281 3282 /****************************************************************************/ 3283 // Structure used in MclkSS_InfoTable 3284 /****************************************************************************/ 3285 // ucI2C_ConfigID 3286 // [7:0] - I2C LINE Associate ID 3287 // = 0 - no I2C 3288 // [7] - HW_Cap = 1, [6:0]=HW assisted I2C ID(HW line selection) 3289 // = 0, [6:0]=SW assisted I2C ID 3290 // [6-4] - HW_ENGINE_ID = 1, HW engine for NON multimedia use 3291 // = 2, HW engine for Multimedia use 3292 // = 3-7 Reserved for future I2C engines 3293 // [3-0] - I2C_LINE_MUX = A Mux number when it's HW assisted I2C or GPIO ID when it's SW I2C 3294 3295 typedef struct _ATOM_I2C_ID_CONFIG 3296 { 3297 #if ATOM_BIG_ENDIAN 3298 UCHAR bfHW_Capable:1; 3299 UCHAR bfHW_EngineID:3; 3300 UCHAR bfI2C_LineMux:4; 3301 #else 3302 UCHAR bfI2C_LineMux:4; 3303 UCHAR bfHW_EngineID:3; 3304 UCHAR bfHW_Capable:1; 3305 #endif 3306 }ATOM_I2C_ID_CONFIG; 3307 3308 typedef union _ATOM_I2C_ID_CONFIG_ACCESS 3309 { 3310 ATOM_I2C_ID_CONFIG sbfAccess; 3311 UCHAR ucAccess; 3312 }ATOM_I2C_ID_CONFIG_ACCESS; 3313 3314 3315 /****************************************************************************/ 3316 // Structure used in GPIO_I2C_InfoTable 3317 /****************************************************************************/ 3318 typedef struct _ATOM_GPIO_I2C_ASSIGMENT 3319 { 3320 USHORT usClkMaskRegisterIndex; 3321 USHORT usClkEnRegisterIndex; 3322 USHORT usClkY_RegisterIndex; 3323 USHORT usClkA_RegisterIndex; 3324 USHORT usDataMaskRegisterIndex; 3325 USHORT usDataEnRegisterIndex; 3326 USHORT usDataY_RegisterIndex; 3327 USHORT usDataA_RegisterIndex; 3328 ATOM_I2C_ID_CONFIG_ACCESS sucI2cId; 3329 UCHAR ucClkMaskShift; 3330 UCHAR ucClkEnShift; 3331 UCHAR ucClkY_Shift; 3332 UCHAR ucClkA_Shift; 3333 UCHAR ucDataMaskShift; 3334 UCHAR ucDataEnShift; 3335 UCHAR ucDataY_Shift; 3336 UCHAR ucDataA_Shift; 3337 UCHAR ucReserved1; 3338 UCHAR ucReserved2; 3339 }ATOM_GPIO_I2C_ASSIGMENT; 3340 3341 typedef struct _ATOM_GPIO_I2C_INFO 3342 { 3343 ATOM_COMMON_TABLE_HEADER sHeader; 3344 ATOM_GPIO_I2C_ASSIGMENT asGPIO_Info[ATOM_MAX_SUPPORTED_DEVICE]; 3345 }ATOM_GPIO_I2C_INFO; 3346 3347 /****************************************************************************/ 3348 // Common Structure used in other structures 3349 /****************************************************************************/ 3350 3351 #ifndef _H2INC 3352 3353 //Please don't add or expand this bitfield structure below, this one will retire soon.! 3354 typedef struct _ATOM_MODE_MISC_INFO 3355 { 3356 #if ATOM_BIG_ENDIAN 3357 USHORT Reserved:6; 3358 USHORT RGB888:1; 3359 USHORT DoubleClock:1; 3360 USHORT Interlace:1; 3361 USHORT CompositeSync:1; 3362 USHORT V_ReplicationBy2:1; 3363 USHORT H_ReplicationBy2:1; 3364 USHORT VerticalCutOff:1; 3365 USHORT VSyncPolarity:1; //0=Active High, 1=Active Low 3366 USHORT HSyncPolarity:1; //0=Active High, 1=Active Low 3367 USHORT HorizontalCutOff:1; 3368 #else 3369 USHORT HorizontalCutOff:1; 3370 USHORT HSyncPolarity:1; //0=Active High, 1=Active Low 3371 USHORT VSyncPolarity:1; //0=Active High, 1=Active Low 3372 USHORT VerticalCutOff:1; 3373 USHORT H_ReplicationBy2:1; 3374 USHORT V_ReplicationBy2:1; 3375 USHORT CompositeSync:1; 3376 USHORT Interlace:1; 3377 USHORT DoubleClock:1; 3378 USHORT RGB888:1; 3379 USHORT Reserved:6; 3380 #endif 3381 }ATOM_MODE_MISC_INFO; 3382 3383 typedef union _ATOM_MODE_MISC_INFO_ACCESS 3384 { 3385 ATOM_MODE_MISC_INFO sbfAccess; 3386 USHORT usAccess; 3387 }ATOM_MODE_MISC_INFO_ACCESS; 3388 3389 #else 3390 3391 typedef union _ATOM_MODE_MISC_INFO_ACCESS 3392 { 3393 USHORT usAccess; 3394 }ATOM_MODE_MISC_INFO_ACCESS; 3395 3396 #endif 3397 3398 // usModeMiscInfo- 3399 #define ATOM_H_CUTOFF 0x01 3400 #define ATOM_HSYNC_POLARITY 0x02 //0=Active High, 1=Active Low 3401 #define ATOM_VSYNC_POLARITY 0x04 //0=Active High, 1=Active Low 3402 #define ATOM_V_CUTOFF 0x08 3403 #define ATOM_H_REPLICATIONBY2 0x10 3404 #define ATOM_V_REPLICATIONBY2 0x20 3405 #define ATOM_COMPOSITESYNC 0x40 3406 #define ATOM_INTERLACE 0x80 3407 #define ATOM_DOUBLE_CLOCK_MODE 0x100 3408 #define ATOM_RGB888_MODE 0x200 3409 3410 //usRefreshRate- 3411 #define ATOM_REFRESH_43 43 3412 #define ATOM_REFRESH_47 47 3413 #define ATOM_REFRESH_56 56 3414 #define ATOM_REFRESH_60 60 3415 #define ATOM_REFRESH_65 65 3416 #define ATOM_REFRESH_70 70 3417 #define ATOM_REFRESH_72 72 3418 #define ATOM_REFRESH_75 75 3419 #define ATOM_REFRESH_85 85 3420 3421 // ATOM_MODE_TIMING data are exactly the same as VESA timing data. 3422 // Translation from EDID to ATOM_MODE_TIMING, use the following formula. 3423 // 3424 // VESA_HTOTAL = VESA_ACTIVE + 2* VESA_BORDER + VESA_BLANK 3425 // = EDID_HA + EDID_HBL 3426 // VESA_HDISP = VESA_ACTIVE = EDID_HA 3427 // VESA_HSYNC_START = VESA_ACTIVE + VESA_BORDER + VESA_FRONT_PORCH 3428 // = EDID_HA + EDID_HSO 3429 // VESA_HSYNC_WIDTH = VESA_HSYNC_TIME = EDID_HSPW 3430 // VESA_BORDER = EDID_BORDER 3431 3432 3433 /****************************************************************************/ 3434 // Structure used in SetCRTC_UsingDTDTimingTable 3435 /****************************************************************************/ 3436 typedef struct _SET_CRTC_USING_DTD_TIMING_PARAMETERS 3437 { 3438 USHORT usH_Size; 3439 USHORT usH_Blanking_Time; 3440 USHORT usV_Size; 3441 USHORT usV_Blanking_Time; 3442 USHORT usH_SyncOffset; 3443 USHORT usH_SyncWidth; 3444 USHORT usV_SyncOffset; 3445 USHORT usV_SyncWidth; 3446 ATOM_MODE_MISC_INFO_ACCESS susModeMiscInfo; 3447 UCHAR ucH_Border; // From DFP EDID 3448 UCHAR ucV_Border; 3449 UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC2 3450 UCHAR ucPadding[3]; 3451 }SET_CRTC_USING_DTD_TIMING_PARAMETERS; 3452 3453 /****************************************************************************/ 3454 // Structure used in SetCRTC_TimingTable 3455 /****************************************************************************/ 3456 typedef struct _SET_CRTC_TIMING_PARAMETERS 3457 { 3458 USHORT usH_Total; // horizontal total 3459 USHORT usH_Disp; // horizontal display 3460 USHORT usH_SyncStart; // horozontal Sync start 3461 USHORT usH_SyncWidth; // horizontal Sync width 3462 USHORT usV_Total; // vertical total 3463 USHORT usV_Disp; // vertical display 3464 USHORT usV_SyncStart; // vertical Sync start 3465 USHORT usV_SyncWidth; // vertical Sync width 3466 ATOM_MODE_MISC_INFO_ACCESS susModeMiscInfo; 3467 UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC2 3468 UCHAR ucOverscanRight; // right 3469 UCHAR ucOverscanLeft; // left 3470 UCHAR ucOverscanBottom; // bottom 3471 UCHAR ucOverscanTop; // top 3472 UCHAR ucReserved; 3473 }SET_CRTC_TIMING_PARAMETERS; 3474 #define SET_CRTC_TIMING_PARAMETERS_PS_ALLOCATION SET_CRTC_TIMING_PARAMETERS 3475 3476 3477 /****************************************************************************/ 3478 // Structure used in StandardVESA_TimingTable 3479 // AnalogTV_InfoTable 3480 // ComponentVideoInfoTable 3481 /****************************************************************************/ 3482 typedef struct _ATOM_MODE_TIMING 3483 { 3484 USHORT usCRTC_H_Total; 3485 USHORT usCRTC_H_Disp; 3486 USHORT usCRTC_H_SyncStart; 3487 USHORT usCRTC_H_SyncWidth; 3488 USHORT usCRTC_V_Total; 3489 USHORT usCRTC_V_Disp; 3490 USHORT usCRTC_V_SyncStart; 3491 USHORT usCRTC_V_SyncWidth; 3492 USHORT usPixelClock; //in 10Khz unit 3493 ATOM_MODE_MISC_INFO_ACCESS susModeMiscInfo; 3494 USHORT usCRTC_OverscanRight; 3495 USHORT usCRTC_OverscanLeft; 3496 USHORT usCRTC_OverscanBottom; 3497 USHORT usCRTC_OverscanTop; 3498 USHORT usReserve; 3499 UCHAR ucInternalModeNumber; 3500 UCHAR ucRefreshRate; 3501 }ATOM_MODE_TIMING; 3502 3503 typedef struct _ATOM_DTD_FORMAT 3504 { 3505 USHORT usPixClk; 3506 USHORT usHActive; 3507 USHORT usHBlanking_Time; 3508 USHORT usVActive; 3509 USHORT usVBlanking_Time; 3510 USHORT usHSyncOffset; 3511 USHORT usHSyncWidth; 3512 USHORT usVSyncOffset; 3513 USHORT usVSyncWidth; 3514 USHORT usImageHSize; 3515 USHORT usImageVSize; 3516 UCHAR ucHBorder; 3517 UCHAR ucVBorder; 3518 ATOM_MODE_MISC_INFO_ACCESS susModeMiscInfo; 3519 UCHAR ucInternalModeNumber; 3520 UCHAR ucRefreshRate; 3521 }ATOM_DTD_FORMAT; 3522 3523 /****************************************************************************/ 3524 // Structure used in LVDS_InfoTable 3525 // * Need a document to describe this table 3526 /****************************************************************************/ 3527 #define SUPPORTED_LCD_REFRESHRATE_30Hz 0x0004 3528 #define SUPPORTED_LCD_REFRESHRATE_40Hz 0x0008 3529 #define SUPPORTED_LCD_REFRESHRATE_50Hz 0x0010 3530 #define SUPPORTED_LCD_REFRESHRATE_60Hz 0x0020 3531 #define SUPPORTED_LCD_REFRESHRATE_48Hz 0x0040 3532 3533 //ucTableFormatRevision=1 3534 //ucTableContentRevision=1 3535 typedef struct _ATOM_LVDS_INFO 3536 { 3537 ATOM_COMMON_TABLE_HEADER sHeader; 3538 ATOM_DTD_FORMAT sLCDTiming; 3539 USHORT usModePatchTableOffset; 3540 USHORT usSupportedRefreshRate; //Refer to panel info table in ATOMBIOS extension Spec. 3541 USHORT usOffDelayInMs; 3542 UCHAR ucPowerSequenceDigOntoDEin10Ms; 3543 UCHAR ucPowerSequenceDEtoBLOnin10Ms; 3544 UCHAR ucLVDS_Misc; // Bit0:{=0:single, =1:dual},Bit1 {=0:666RGB, =1:888RGB},Bit2:3:{Grey level} 3545 // Bit4:{=0:LDI format for RGB888, =1 FPDI format for RGB888} 3546 // Bit5:{=0:Spatial Dithering disabled;1 Spatial Dithering enabled} 3547 // Bit6:{=0:Temporal Dithering disabled;1 Temporal Dithering enabled} 3548 UCHAR ucPanelDefaultRefreshRate; 3549 UCHAR ucPanelIdentification; 3550 UCHAR ucSS_Id; 3551 }ATOM_LVDS_INFO; 3552 3553 //ucTableFormatRevision=1 3554 //ucTableContentRevision=2 3555 typedef struct _ATOM_LVDS_INFO_V12 3556 { 3557 ATOM_COMMON_TABLE_HEADER sHeader; 3558 ATOM_DTD_FORMAT sLCDTiming; 3559 USHORT usExtInfoTableOffset; 3560 USHORT usSupportedRefreshRate; //Refer to panel info table in ATOMBIOS extension Spec. 3561 USHORT usOffDelayInMs; 3562 UCHAR ucPowerSequenceDigOntoDEin10Ms; 3563 UCHAR ucPowerSequenceDEtoBLOnin10Ms; 3564 UCHAR ucLVDS_Misc; // Bit0:{=0:single, =1:dual},Bit1 {=0:666RGB, =1:888RGB},Bit2:3:{Grey level} 3565 // Bit4:{=0:LDI format for RGB888, =1 FPDI format for RGB888} 3566 // Bit5:{=0:Spatial Dithering disabled;1 Spatial Dithering enabled} 3567 // Bit6:{=0:Temporal Dithering disabled;1 Temporal Dithering enabled} 3568 UCHAR ucPanelDefaultRefreshRate; 3569 UCHAR ucPanelIdentification; 3570 UCHAR ucSS_Id; 3571 USHORT usLCDVenderID; 3572 USHORT usLCDProductID; 3573 UCHAR ucLCDPanel_SpecialHandlingCap; 3574 UCHAR ucPanelInfoSize; // start from ATOM_DTD_FORMAT to end of panel info, include ExtInfoTable 3575 UCHAR ucReserved[2]; 3576 }ATOM_LVDS_INFO_V12; 3577 3578 //Definitions for ucLCDPanel_SpecialHandlingCap: 3579 3580 //Once DAL sees this CAP is set, it will read EDID from LCD on its own instead of using sLCDTiming in ATOM_LVDS_INFO_V12. 3581 //Other entries in ATOM_LVDS_INFO_V12 are still valid/useful to DAL 3582 #define LCDPANEL_CAP_READ_EDID 0x1 3583 3584 //If a design supports DRR (dynamic refresh rate) on internal panels (LVDS or EDP), this cap is set in ucLCDPanel_SpecialHandlingCap together 3585 //with multiple supported refresh rates@usSupportedRefreshRate. This cap should not be set when only slow refresh rate is supported (static 3586 //refresh rate switch by SW. This is only valid from ATOM_LVDS_INFO_V12 3587 #define LCDPANEL_CAP_DRR_SUPPORTED 0x2 3588 3589 //Use this cap bit for a quick reference whether an embadded panel (LCD1 ) is LVDS or eDP. 3590 #define LCDPANEL_CAP_eDP 0x4 3591 3592 3593 //Color Bit Depth definition in EDID V1.4 @BYTE 14h 3594 //Bit 6 5 4 3595 // 0 0 0 - Color bit depth is undefined 3596 // 0 0 1 - 6 Bits per Primary Color 3597 // 0 1 0 - 8 Bits per Primary Color 3598 // 0 1 1 - 10 Bits per Primary Color 3599 // 1 0 0 - 12 Bits per Primary Color 3600 // 1 0 1 - 14 Bits per Primary Color 3601 // 1 1 0 - 16 Bits per Primary Color 3602 // 1 1 1 - Reserved 3603 3604 #define PANEL_COLOR_BIT_DEPTH_MASK 0x70 3605 3606 // Bit7:{=0:Random Dithering disabled;1 Random Dithering enabled} 3607 #define PANEL_RANDOM_DITHER 0x80 3608 #define PANEL_RANDOM_DITHER_MASK 0x80 3609 3610 #define ATOM_LVDS_INFO_LAST ATOM_LVDS_INFO_V12 // no need to change this 3611 3612 3613 typedef struct _ATOM_LCD_REFRESH_RATE_SUPPORT 3614 { 3615 UCHAR ucSupportedRefreshRate; 3616 UCHAR ucMinRefreshRateForDRR; 3617 }ATOM_LCD_REFRESH_RATE_SUPPORT; 3618 3619 /****************************************************************************/ 3620 // Structures used by LCD_InfoTable V1.3 Note: previous version was called ATOM_LVDS_INFO_V12 3621 // ASIC Families: NI 3622 // ucTableFormatRevision=1 3623 // ucTableContentRevision=3 3624 /****************************************************************************/ 3625 typedef struct _ATOM_LCD_INFO_V13 3626 { 3627 ATOM_COMMON_TABLE_HEADER sHeader; 3628 ATOM_DTD_FORMAT sLCDTiming; 3629 USHORT usExtInfoTableOffset; 3630 union 3631 { 3632 USHORT usSupportedRefreshRate; 3633 ATOM_LCD_REFRESH_RATE_SUPPORT sRefreshRateSupport; 3634 }; 3635 ULONG ulReserved0; 3636 UCHAR ucLCD_Misc; // Reorganized in V13 3637 // Bit0: {=0:single, =1:dual}, 3638 // Bit1: {=0:LDI format for RGB888, =1 FPDI format for RGB888} // was {=0:666RGB, =1:888RGB}, 3639 // Bit3:2: {Grey level} 3640 // Bit6:4 Color Bit Depth definition (see below definition in EDID V1.4 @BYTE 14h) 3641 // Bit7 Reserved. was for ATOM_PANEL_MISC_API_ENABLED, still need it? 3642 UCHAR ucPanelDefaultRefreshRate; 3643 UCHAR ucPanelIdentification; 3644 UCHAR ucSS_Id; 3645 USHORT usLCDVenderID; 3646 USHORT usLCDProductID; 3647 UCHAR ucLCDPanel_SpecialHandlingCap; // Reorganized in V13 3648 // Bit0: Once DAL sees this CAP is set, it will read EDID from LCD on its own 3649 // Bit1: See LCDPANEL_CAP_DRR_SUPPORTED 3650 // Bit2: a quick reference whether an embadded panel (LCD1 ) is LVDS (0) or eDP (1) 3651 // Bit7-3: Reserved 3652 UCHAR ucPanelInfoSize; // start from ATOM_DTD_FORMAT to end of panel info, include ExtInfoTable 3653 USHORT usBacklightPWM; // Backlight PWM in Hz. New in _V13 3654 3655 UCHAR ucPowerSequenceDIGONtoDE_in4Ms; 3656 UCHAR ucPowerSequenceDEtoVARY_BL_in4Ms; 3657 UCHAR ucPowerSequenceVARY_BLtoDE_in4Ms; 3658 UCHAR ucPowerSequenceDEtoDIGON_in4Ms; 3659 3660 UCHAR ucOffDelay_in4Ms; 3661 UCHAR ucPowerSequenceVARY_BLtoBLON_in4Ms; 3662 UCHAR ucPowerSequenceBLONtoVARY_BL_in4Ms; 3663 UCHAR ucReserved1; 3664 3665 UCHAR ucDPCD_eDP_CONFIGURATION_CAP; // dpcd 0dh 3666 UCHAR ucDPCD_MAX_LINK_RATE; // dpcd 01h 3667 UCHAR ucDPCD_MAX_LANE_COUNT; // dpcd 02h 3668 UCHAR ucDPCD_MAX_DOWNSPREAD; // dpcd 03h 3669 3670 USHORT usMaxPclkFreqInSingleLink; // Max PixelClock frequency in single link mode. 3671 UCHAR uceDPToLVDSRxId; 3672 UCHAR ucLcdReservd; 3673 ULONG ulReserved[2]; 3674 }ATOM_LCD_INFO_V13; 3675 3676 #define ATOM_LCD_INFO_LAST ATOM_LCD_INFO_V13 3677 3678 //Definitions for ucLCD_Misc 3679 #define ATOM_PANEL_MISC_V13_DUAL 0x00000001 3680 #define ATOM_PANEL_MISC_V13_FPDI 0x00000002 3681 #define ATOM_PANEL_MISC_V13_GREY_LEVEL 0x0000000C 3682 #define ATOM_PANEL_MISC_V13_GREY_LEVEL_SHIFT 2 3683 #define ATOM_PANEL_MISC_V13_COLOR_BIT_DEPTH_MASK 0x70 3684 #define ATOM_PANEL_MISC_V13_6BIT_PER_COLOR 0x10 3685 #define ATOM_PANEL_MISC_V13_8BIT_PER_COLOR 0x20 3686 3687 //Color Bit Depth definition in EDID V1.4 @BYTE 14h 3688 //Bit 6 5 4 3689 // 0 0 0 - Color bit depth is undefined 3690 // 0 0 1 - 6 Bits per Primary Color 3691 // 0 1 0 - 8 Bits per Primary Color 3692 // 0 1 1 - 10 Bits per Primary Color 3693 // 1 0 0 - 12 Bits per Primary Color 3694 // 1 0 1 - 14 Bits per Primary Color 3695 // 1 1 0 - 16 Bits per Primary Color 3696 // 1 1 1 - Reserved 3697 3698 //Definitions for ucLCDPanel_SpecialHandlingCap: 3699 3700 //Once DAL sees this CAP is set, it will read EDID from LCD on its own instead of using sLCDTiming in ATOM_LVDS_INFO_V12. 3701 //Other entries in ATOM_LVDS_INFO_V12 are still valid/useful to DAL 3702 #define LCDPANEL_CAP_V13_READ_EDID 0x1 // = LCDPANEL_CAP_READ_EDID no change comparing to previous version 3703 3704 //If a design supports DRR (dynamic refresh rate) on internal panels (LVDS or EDP), this cap is set in ucLCDPanel_SpecialHandlingCap together 3705 //with multiple supported refresh rates@usSupportedRefreshRate. This cap should not be set when only slow refresh rate is supported (static 3706 //refresh rate switch by SW. This is only valid from ATOM_LVDS_INFO_V12 3707 #define LCDPANEL_CAP_V13_DRR_SUPPORTED 0x2 // = LCDPANEL_CAP_DRR_SUPPORTED no change comparing to previous version 3708 3709 //Use this cap bit for a quick reference whether an embadded panel (LCD1 ) is LVDS or eDP. 3710 #define LCDPANEL_CAP_V13_eDP 0x4 // = LCDPANEL_CAP_eDP no change comparing to previous version 3711 3712 //uceDPToLVDSRxId 3713 #define eDP_TO_LVDS_RX_DISABLE 0x00 // no eDP->LVDS translator chip 3714 #define eDP_TO_LVDS_COMMON_ID 0x01 // common eDP->LVDS translator chip without AMD SW init 3715 #define eDP_TO_LVDS_RT_ID 0x02 // RT tansaltor which require AMD SW init 3716 3717 typedef struct _ATOM_PATCH_RECORD_MODE 3718 { 3719 UCHAR ucRecordType; 3720 USHORT usHDisp; 3721 USHORT usVDisp; 3722 }ATOM_PATCH_RECORD_MODE; 3723 3724 typedef struct _ATOM_LCD_RTS_RECORD 3725 { 3726 UCHAR ucRecordType; 3727 UCHAR ucRTSValue; 3728 }ATOM_LCD_RTS_RECORD; 3729 3730 //!! If the record below exits, it shoud always be the first record for easy use in command table!!! 3731 // The record below is only used when LVDS_Info is present. From ATOM_LVDS_INFO_V12, use ucLCDPanel_SpecialHandlingCap instead. 3732 typedef struct _ATOM_LCD_MODE_CONTROL_CAP 3733 { 3734 UCHAR ucRecordType; 3735 USHORT usLCDCap; 3736 }ATOM_LCD_MODE_CONTROL_CAP; 3737 3738 #define LCD_MODE_CAP_BL_OFF 1 3739 #define LCD_MODE_CAP_CRTC_OFF 2 3740 #define LCD_MODE_CAP_PANEL_OFF 4 3741 3742 3743 typedef struct _ATOM_FAKE_EDID_PATCH_RECORD 3744 { 3745 UCHAR ucRecordType; 3746 UCHAR ucFakeEDIDLength; // = 128 means EDID lenght is 128 bytes, otherwise the EDID length = ucFakeEDIDLength*128 3747 UCHAR ucFakeEDIDString[1]; // This actually has ucFakeEdidLength elements. 3748 } ATOM_FAKE_EDID_PATCH_RECORD; 3749 3750 typedef struct _ATOM_PANEL_RESOLUTION_PATCH_RECORD 3751 { 3752 UCHAR ucRecordType; 3753 USHORT usHSize; 3754 USHORT usVSize; 3755 }ATOM_PANEL_RESOLUTION_PATCH_RECORD; 3756 3757 #define LCD_MODE_PATCH_RECORD_MODE_TYPE 1 3758 #define LCD_RTS_RECORD_TYPE 2 3759 #define LCD_CAP_RECORD_TYPE 3 3760 #define LCD_FAKE_EDID_PATCH_RECORD_TYPE 4 3761 #define LCD_PANEL_RESOLUTION_RECORD_TYPE 5 3762 #define LCD_EDID_OFFSET_PATCH_RECORD_TYPE 6 3763 #define ATOM_RECORD_END_TYPE 0xFF 3764 3765 /****************************Spread Spectrum Info Table Definitions **********************/ 3766 3767 //ucTableFormatRevision=1 3768 //ucTableContentRevision=2 3769 typedef struct _ATOM_SPREAD_SPECTRUM_ASSIGNMENT 3770 { 3771 USHORT usSpreadSpectrumPercentage; 3772 UCHAR ucSpreadSpectrumType; //Bit1=0 Down Spread,=1 Center Spread. Bit1=1 Ext. =0 Int. Bit2=1: PCIE REFCLK SS =0 iternal PPLL SS Others:TBD 3773 UCHAR ucSS_Step; 3774 UCHAR ucSS_Delay; 3775 UCHAR ucSS_Id; 3776 UCHAR ucRecommendedRef_Div; 3777 UCHAR ucSS_Range; //it was reserved for V11 3778 }ATOM_SPREAD_SPECTRUM_ASSIGNMENT; 3779 3780 #define ATOM_MAX_SS_ENTRY 16 3781 #define ATOM_DP_SS_ID1 0x0f1 // SS ID for internal DP stream at 2.7Ghz. if ATOM_DP_SS_ID2 does not exist in SS_InfoTable, it is used for internal DP stream at 1.62Ghz as well. 3782 #define ATOM_DP_SS_ID2 0x0f2 // SS ID for internal DP stream at 1.62Ghz, if it exists in SS_InfoTable. 3783 #define ATOM_LVLINK_2700MHz_SS_ID 0x0f3 // SS ID for LV link translator chip at 2.7Ghz 3784 #define ATOM_LVLINK_1620MHz_SS_ID 0x0f4 // SS ID for LV link translator chip at 1.62Ghz 3785 3786 3787 3788 #define ATOM_SS_DOWN_SPREAD_MODE_MASK 0x00000000 3789 #define ATOM_SS_DOWN_SPREAD_MODE 0x00000000 3790 #define ATOM_SS_CENTRE_SPREAD_MODE_MASK 0x00000001 3791 #define ATOM_SS_CENTRE_SPREAD_MODE 0x00000001 3792 #define ATOM_INTERNAL_SS_MASK 0x00000000 3793 #define ATOM_EXTERNAL_SS_MASK 0x00000002 3794 #define EXEC_SS_STEP_SIZE_SHIFT 2 3795 #define EXEC_SS_DELAY_SHIFT 4 3796 #define ACTIVEDATA_TO_BLON_DELAY_SHIFT 4 3797 3798 typedef struct _ATOM_SPREAD_SPECTRUM_INFO 3799 { 3800 ATOM_COMMON_TABLE_HEADER sHeader; 3801 ATOM_SPREAD_SPECTRUM_ASSIGNMENT asSS_Info[ATOM_MAX_SS_ENTRY]; 3802 }ATOM_SPREAD_SPECTRUM_INFO; 3803 3804 3805 /****************************************************************************/ 3806 // Structure used in AnalogTV_InfoTable (Top level) 3807 /****************************************************************************/ 3808 //ucTVBootUpDefaultStd definiton: 3809 3810 //ATOM_TV_NTSC 1 3811 //ATOM_TV_NTSCJ 2 3812 //ATOM_TV_PAL 3 3813 //ATOM_TV_PALM 4 3814 //ATOM_TV_PALCN 5 3815 //ATOM_TV_PALN 6 3816 //ATOM_TV_PAL60 7 3817 //ATOM_TV_SECAM 8 3818 3819 //ucTVSuppportedStd definition: 3820 #define NTSC_SUPPORT 0x1 3821 #define NTSCJ_SUPPORT 0x2 3822 3823 #define PAL_SUPPORT 0x4 3824 #define PALM_SUPPORT 0x8 3825 #define PALCN_SUPPORT 0x10 3826 #define PALN_SUPPORT 0x20 3827 #define PAL60_SUPPORT 0x40 3828 #define SECAM_SUPPORT 0x80 3829 3830 #define MAX_SUPPORTED_TV_TIMING 2 3831 3832 typedef struct _ATOM_ANALOG_TV_INFO 3833 { 3834 ATOM_COMMON_TABLE_HEADER sHeader; 3835 UCHAR ucTV_SuppportedStandard; 3836 UCHAR ucTV_BootUpDefaultStandard; 3837 UCHAR ucExt_TV_ASIC_ID; 3838 UCHAR ucExt_TV_ASIC_SlaveAddr; 3839 ATOM_DTD_FORMAT aModeTimings[MAX_SUPPORTED_TV_TIMING]; 3840 }ATOM_ANALOG_TV_INFO; 3841 3842 typedef struct _ATOM_DPCD_INFO 3843 { 3844 UCHAR ucRevisionNumber; //10h : Revision 1.0; 11h : Revision 1.1 3845 UCHAR ucMaxLinkRate; //06h : 1.62Gbps per lane; 0Ah = 2.7Gbps per lane 3846 UCHAR ucMaxLane; //Bits 4:0 = MAX_LANE_COUNT (1/2/4). Bit 7 = ENHANCED_FRAME_CAP 3847 UCHAR ucMaxDownSpread; //Bit0 = 0: No Down spread; Bit0 = 1: 0.5% (Subject to change according to DP spec) 3848 }ATOM_DPCD_INFO; 3849 3850 #define ATOM_DPCD_MAX_LANE_MASK 0x1F 3851 3852 /**************************************************************************/ 3853 // VRAM usage and their defintions 3854 3855 // One chunk of VRAM used by Bios are for HWICON surfaces,EDID data. 3856 // Current Mode timing and Dail Timing and/or STD timing data EACH device. They can be broken down as below. 3857 // All the addresses below are the offsets from the frame buffer start.They all MUST be Dword aligned! 3858 // To driver: The physical address of this memory portion=mmFB_START(4K aligned)+ATOMBIOS_VRAM_USAGE_START_ADDR+ATOM_x_ADDR 3859 // To Bios: ATOMBIOS_VRAM_USAGE_START_ADDR+ATOM_x_ADDR->MM_INDEX 3860 3861 // Moved VESA_MEMORY_IN_64K_BLOCK definition to "AtomConfig.h" so that it can be redefined in design (SKU). 3862 //#ifndef VESA_MEMORY_IN_64K_BLOCK 3863 //#define VESA_MEMORY_IN_64K_BLOCK 0x100 //256*64K=16Mb (Max. VESA memory is 16Mb!) 3864 //#endif 3865 3866 #define ATOM_EDID_RAW_DATASIZE 256 //In Bytes 3867 #define ATOM_HWICON_SURFACE_SIZE 4096 //In Bytes 3868 #define ATOM_HWICON_INFOTABLE_SIZE 32 3869 #define MAX_DTD_MODE_IN_VRAM 6 3870 #define ATOM_DTD_MODE_SUPPORT_TBL_SIZE (MAX_DTD_MODE_IN_VRAM*28) //28= (SIZEOF ATOM_DTD_FORMAT) 3871 #define ATOM_STD_MODE_SUPPORT_TBL_SIZE 32*8 //32 is a predefined number,8= (SIZEOF ATOM_STD_FORMAT) 3872 //20 bytes for Encoder Type and DPCD in STD EDID area 3873 #define DFP_ENCODER_TYPE_OFFSET (ATOM_EDID_RAW_DATASIZE + ATOM_DTD_MODE_SUPPORT_TBL_SIZE + ATOM_STD_MODE_SUPPORT_TBL_SIZE - 20) 3874 #define ATOM_DP_DPCD_OFFSET (DFP_ENCODER_TYPE_OFFSET + 4 ) 3875 3876 #define ATOM_HWICON1_SURFACE_ADDR 0 3877 #define ATOM_HWICON2_SURFACE_ADDR (ATOM_HWICON1_SURFACE_ADDR + ATOM_HWICON_SURFACE_SIZE) 3878 #define ATOM_HWICON_INFOTABLE_ADDR (ATOM_HWICON2_SURFACE_ADDR + ATOM_HWICON_SURFACE_SIZE) 3879 #define ATOM_CRT1_EDID_ADDR (ATOM_HWICON_INFOTABLE_ADDR + ATOM_HWICON_INFOTABLE_SIZE) 3880 #define ATOM_CRT1_DTD_MODE_TBL_ADDR (ATOM_CRT1_EDID_ADDR + ATOM_EDID_RAW_DATASIZE) 3881 #define ATOM_CRT1_STD_MODE_TBL_ADDR (ATOM_CRT1_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE) 3882 3883 #define ATOM_LCD1_EDID_ADDR (ATOM_CRT1_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE) 3884 #define ATOM_LCD1_DTD_MODE_TBL_ADDR (ATOM_LCD1_EDID_ADDR + ATOM_EDID_RAW_DATASIZE) 3885 #define ATOM_LCD1_STD_MODE_TBL_ADDR (ATOM_LCD1_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE) 3886 3887 #define ATOM_TV1_DTD_MODE_TBL_ADDR (ATOM_LCD1_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE) 3888 3889 #define ATOM_DFP1_EDID_ADDR (ATOM_TV1_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE) 3890 #define ATOM_DFP1_DTD_MODE_TBL_ADDR (ATOM_DFP1_EDID_ADDR + ATOM_EDID_RAW_DATASIZE) 3891 #define ATOM_DFP1_STD_MODE_TBL_ADDR (ATOM_DFP1_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE) 3892 3893 #define ATOM_CRT2_EDID_ADDR (ATOM_DFP1_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE) 3894 #define ATOM_CRT2_DTD_MODE_TBL_ADDR (ATOM_CRT2_EDID_ADDR + ATOM_EDID_RAW_DATASIZE) 3895 #define ATOM_CRT2_STD_MODE_TBL_ADDR (ATOM_CRT2_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE) 3896 3897 #define ATOM_LCD2_EDID_ADDR (ATOM_CRT2_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE) 3898 #define ATOM_LCD2_DTD_MODE_TBL_ADDR (ATOM_LCD2_EDID_ADDR + ATOM_EDID_RAW_DATASIZE) 3899 #define ATOM_LCD2_STD_MODE_TBL_ADDR (ATOM_LCD2_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE) 3900 3901 #define ATOM_DFP6_EDID_ADDR (ATOM_LCD2_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE) 3902 #define ATOM_DFP6_DTD_MODE_TBL_ADDR (ATOM_DFP6_EDID_ADDR + ATOM_EDID_RAW_DATASIZE) 3903 #define ATOM_DFP6_STD_MODE_TBL_ADDR (ATOM_DFP6_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE) 3904 3905 #define ATOM_DFP2_EDID_ADDR (ATOM_DFP6_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE) 3906 #define ATOM_DFP2_DTD_MODE_TBL_ADDR (ATOM_DFP2_EDID_ADDR + ATOM_EDID_RAW_DATASIZE) 3907 #define ATOM_DFP2_STD_MODE_TBL_ADDR (ATOM_DFP2_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE) 3908 3909 #define ATOM_CV_EDID_ADDR (ATOM_DFP2_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE) 3910 #define ATOM_CV_DTD_MODE_TBL_ADDR (ATOM_CV_EDID_ADDR + ATOM_EDID_RAW_DATASIZE) 3911 #define ATOM_CV_STD_MODE_TBL_ADDR (ATOM_CV_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE) 3912 3913 #define ATOM_DFP3_EDID_ADDR (ATOM_CV_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE) 3914 #define ATOM_DFP3_DTD_MODE_TBL_ADDR (ATOM_DFP3_EDID_ADDR + ATOM_EDID_RAW_DATASIZE) 3915 #define ATOM_DFP3_STD_MODE_TBL_ADDR (ATOM_DFP3_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE) 3916 3917 #define ATOM_DFP4_EDID_ADDR (ATOM_DFP3_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE) 3918 #define ATOM_DFP4_DTD_MODE_TBL_ADDR (ATOM_DFP4_EDID_ADDR + ATOM_EDID_RAW_DATASIZE) 3919 #define ATOM_DFP4_STD_MODE_TBL_ADDR (ATOM_DFP4_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE) 3920 3921 #define ATOM_DFP5_EDID_ADDR (ATOM_DFP4_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE) 3922 #define ATOM_DFP5_DTD_MODE_TBL_ADDR (ATOM_DFP5_EDID_ADDR + ATOM_EDID_RAW_DATASIZE) 3923 #define ATOM_DFP5_STD_MODE_TBL_ADDR (ATOM_DFP5_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE) 3924 3925 #define ATOM_DP_TRAINING_TBL_ADDR (ATOM_DFP5_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE) 3926 3927 #define ATOM_STACK_STORAGE_START (ATOM_DP_TRAINING_TBL_ADDR + 1024) 3928 #define ATOM_STACK_STORAGE_END ATOM_STACK_STORAGE_START + 512 3929 3930 //The size below is in Kb! 3931 #define ATOM_VRAM_RESERVE_SIZE ((((ATOM_STACK_STORAGE_END - ATOM_HWICON1_SURFACE_ADDR)>>10)+4)&0xFFFC) 3932 3933 #define ATOM_VRAM_RESERVE_V2_SIZE 32 3934 3935 #define ATOM_VRAM_OPERATION_FLAGS_MASK 0xC0000000L 3936 #define ATOM_VRAM_OPERATION_FLAGS_SHIFT 30 3937 #define ATOM_VRAM_BLOCK_NEEDS_NO_RESERVATION 0x1 3938 #define ATOM_VRAM_BLOCK_NEEDS_RESERVATION 0x0 3939 3940 /***********************************************************************************/ 3941 // Structure used in VRAM_UsageByFirmwareTable 3942 // Note1: This table is filled by SetBiosReservationStartInFB in CoreCommSubs.asm 3943 // at running time. 3944 // note2: From RV770, the memory is more than 32bit addressable, so we will change 3945 // ucTableFormatRevision=1,ucTableContentRevision=4, the strcuture remains 3946 // exactly same as 1.1 and 1.2 (1.3 is never in use), but ulStartAddrUsedByFirmware 3947 // (in offset to start of memory address) is KB aligned instead of byte aligend. 3948 // Note3: 3949 /* If we change usReserved to "usFBUsedbyDrvInKB", then to VBIOS this usFBUsedbyDrvInKB is a predefined, unchanged 3950 constant across VGA or non VGA adapter, 3951 for CAIL, The size of FB access area is known, only thing missing is the Offset of FB Access area, so we can have: 3952 3953 If (ulStartAddrUsedByFirmware!=0) 3954 FBAccessAreaOffset= ulStartAddrUsedByFirmware - usFBUsedbyDrvInKB; 3955 Reserved area has been claimed by VBIOS including this FB access area; CAIL doesn't need to reserve any extra area for this purpose 3956 else //Non VGA case 3957 if (FB_Size<=2Gb) 3958 FBAccessAreaOffset= FB_Size - usFBUsedbyDrvInKB; 3959 else 3960 FBAccessAreaOffset= Aper_Size - usFBUsedbyDrvInKB 3961 3962 CAIL needs to claim an reserved area defined by FBAccessAreaOffset and usFBUsedbyDrvInKB in non VGA case.*/ 3963 3964 /***********************************************************************************/ 3965 #define ATOM_MAX_FIRMWARE_VRAM_USAGE_INFO 1 3966 3967 typedef struct _ATOM_FIRMWARE_VRAM_RESERVE_INFO 3968 { 3969 ULONG ulStartAddrUsedByFirmware; 3970 USHORT usFirmwareUseInKb; 3971 USHORT usReserved; 3972 }ATOM_FIRMWARE_VRAM_RESERVE_INFO; 3973 3974 typedef struct _ATOM_VRAM_USAGE_BY_FIRMWARE 3975 { 3976 ATOM_COMMON_TABLE_HEADER sHeader; 3977 ATOM_FIRMWARE_VRAM_RESERVE_INFO asFirmwareVramReserveInfo[ATOM_MAX_FIRMWARE_VRAM_USAGE_INFO]; 3978 }ATOM_VRAM_USAGE_BY_FIRMWARE; 3979 3980 // change verion to 1.5, when allow driver to allocate the vram area for command table access. 3981 typedef struct _ATOM_FIRMWARE_VRAM_RESERVE_INFO_V1_5 3982 { 3983 ULONG ulStartAddrUsedByFirmware; 3984 USHORT usFirmwareUseInKb; 3985 USHORT usFBUsedByDrvInKb; 3986 }ATOM_FIRMWARE_VRAM_RESERVE_INFO_V1_5; 3987 3988 typedef struct _ATOM_VRAM_USAGE_BY_FIRMWARE_V1_5 3989 { 3990 ATOM_COMMON_TABLE_HEADER sHeader; 3991 ATOM_FIRMWARE_VRAM_RESERVE_INFO_V1_5 asFirmwareVramReserveInfo[ATOM_MAX_FIRMWARE_VRAM_USAGE_INFO]; 3992 }ATOM_VRAM_USAGE_BY_FIRMWARE_V1_5; 3993 3994 /****************************************************************************/ 3995 // Structure used in GPIO_Pin_LUTTable 3996 /****************************************************************************/ 3997 typedef struct _ATOM_GPIO_PIN_ASSIGNMENT 3998 { 3999 USHORT usGpioPin_AIndex; 4000 UCHAR ucGpioPinBitShift; 4001 UCHAR ucGPIO_ID; 4002 }ATOM_GPIO_PIN_ASSIGNMENT; 4003 4004 //ucGPIO_ID pre-define id for multiple usage 4005 // GPIO use to control PCIE_VDDC in certain SLT board 4006 #define PCIE_VDDC_CONTROL_GPIO_PINID 56 4007 4008 //from SMU7.x, if ucGPIO_ID=PP_AC_DC_SWITCH_GPIO_PINID in GPIO_LUTTable, AC/DC swithing feature is enable 4009 #define PP_AC_DC_SWITCH_GPIO_PINID 60 4010 //from SMU7.x, if ucGPIO_ID=VDDC_REGULATOR_VRHOT_GPIO_PINID in GPIO_LUTable, VRHot feature is enable 4011 #define VDDC_VRHOT_GPIO_PINID 61 4012 //if ucGPIO_ID=VDDC_PCC_GPIO_PINID in GPIO_LUTable, Peak Current Control feature is enabled 4013 #define VDDC_PCC_GPIO_PINID 62 4014 // Only used on certain SLT/PA board to allow utility to cut Efuse. 4015 #define EFUSE_CUT_ENABLE_GPIO_PINID 63 4016 // ucGPIO=DRAM_SELF_REFRESH_GPIO_PIND uses for memory self refresh (ucGPIO=0, DRAM self-refresh; ucGPIO= 4017 #define DRAM_SELF_REFRESH_GPIO_PINID 64 4018 // Thermal interrupt output->system thermal chip GPIO pin 4019 #define THERMAL_INT_OUTPUT_GPIO_PINID 65 4020 4021 4022 typedef struct _ATOM_GPIO_PIN_LUT 4023 { 4024 ATOM_COMMON_TABLE_HEADER sHeader; 4025 ATOM_GPIO_PIN_ASSIGNMENT asGPIO_Pin[1]; 4026 }ATOM_GPIO_PIN_LUT; 4027 4028 /****************************************************************************/ 4029 // Structure used in ComponentVideoInfoTable 4030 /****************************************************************************/ 4031 #define GPIO_PIN_ACTIVE_HIGH 0x1 4032 #define MAX_SUPPORTED_CV_STANDARDS 5 4033 4034 // definitions for ATOM_D_INFO.ucSettings 4035 #define ATOM_GPIO_SETTINGS_BITSHIFT_MASK 0x1F // [4:0] 4036 #define ATOM_GPIO_SETTINGS_RESERVED_MASK 0x60 // [6:5] = must be zeroed out 4037 #define ATOM_GPIO_SETTINGS_ACTIVE_MASK 0x80 // [7] 4038 4039 typedef struct _ATOM_GPIO_INFO 4040 { 4041 USHORT usAOffset; 4042 UCHAR ucSettings; 4043 UCHAR ucReserved; 4044 }ATOM_GPIO_INFO; 4045 4046 // definitions for ATOM_COMPONENT_VIDEO_INFO.ucMiscInfo (bit vector) 4047 #define ATOM_CV_RESTRICT_FORMAT_SELECTION 0x2 4048 4049 // definitions for ATOM_COMPONENT_VIDEO_INFO.uc480i/uc480p/uc720p/uc1080i 4050 #define ATOM_GPIO_DEFAULT_MODE_EN 0x80 //[7]; 4051 #define ATOM_GPIO_SETTING_PERMODE_MASK 0x7F //[6:0] 4052 4053 // definitions for ATOM_COMPONENT_VIDEO_INFO.ucLetterBoxMode 4054 //Line 3 out put 5V. 4055 #define ATOM_CV_LINE3_ASPECTRATIO_16_9_GPIO_A 0x01 //represent gpio 3 state for 16:9 4056 #define ATOM_CV_LINE3_ASPECTRATIO_16_9_GPIO_B 0x02 //represent gpio 4 state for 16:9 4057 #define ATOM_CV_LINE3_ASPECTRATIO_16_9_GPIO_SHIFT 0x0 4058 4059 //Line 3 out put 2.2V 4060 #define ATOM_CV_LINE3_ASPECTRATIO_4_3_LETBOX_GPIO_A 0x04 //represent gpio 3 state for 4:3 Letter box 4061 #define ATOM_CV_LINE3_ASPECTRATIO_4_3_LETBOX_GPIO_B 0x08 //represent gpio 4 state for 4:3 Letter box 4062 #define ATOM_CV_LINE3_ASPECTRATIO_4_3_LETBOX_GPIO_SHIFT 0x2 4063 4064 //Line 3 out put 0V 4065 #define ATOM_CV_LINE3_ASPECTRATIO_4_3_GPIO_A 0x10 //represent gpio 3 state for 4:3 4066 #define ATOM_CV_LINE3_ASPECTRATIO_4_3_GPIO_B 0x20 //represent gpio 4 state for 4:3 4067 #define ATOM_CV_LINE3_ASPECTRATIO_4_3_GPIO_SHIFT 0x4 4068 4069 #define ATOM_CV_LINE3_ASPECTRATIO_MASK 0x3F // bit [5:0] 4070 4071 #define ATOM_CV_LINE3_ASPECTRATIO_EXIST 0x80 //bit 7 4072 4073 //GPIO bit index in gpio setting per mode value, also represend the block no. in gpio blocks. 4074 #define ATOM_GPIO_INDEX_LINE3_ASPECRATIO_GPIO_A 3 //bit 3 in uc480i/uc480p/uc720p/uc1080i, which represend the default gpio bit setting for the mode. 4075 #define ATOM_GPIO_INDEX_LINE3_ASPECRATIO_GPIO_B 4 //bit 4 in uc480i/uc480p/uc720p/uc1080i, which represend the default gpio bit setting for the mode. 4076 4077 4078 typedef struct _ATOM_COMPONENT_VIDEO_INFO 4079 { 4080 ATOM_COMMON_TABLE_HEADER sHeader; 4081 USHORT usMask_PinRegisterIndex; 4082 USHORT usEN_PinRegisterIndex; 4083 USHORT usY_PinRegisterIndex; 4084 USHORT usA_PinRegisterIndex; 4085 UCHAR ucBitShift; 4086 UCHAR ucPinActiveState; //ucPinActiveState: Bit0=1 active high, =0 active low 4087 ATOM_DTD_FORMAT sReserved; // must be zeroed out 4088 UCHAR ucMiscInfo; 4089 UCHAR uc480i; 4090 UCHAR uc480p; 4091 UCHAR uc720p; 4092 UCHAR uc1080i; 4093 UCHAR ucLetterBoxMode; 4094 UCHAR ucReserved[3]; 4095 UCHAR ucNumOfWbGpioBlocks; //For Component video D-Connector support. If zere, NTSC type connector 4096 ATOM_GPIO_INFO aWbGpioStateBlock[MAX_SUPPORTED_CV_STANDARDS]; 4097 ATOM_DTD_FORMAT aModeTimings[MAX_SUPPORTED_CV_STANDARDS]; 4098 }ATOM_COMPONENT_VIDEO_INFO; 4099 4100 //ucTableFormatRevision=2 4101 //ucTableContentRevision=1 4102 typedef struct _ATOM_COMPONENT_VIDEO_INFO_V21 4103 { 4104 ATOM_COMMON_TABLE_HEADER sHeader; 4105 UCHAR ucMiscInfo; 4106 UCHAR uc480i; 4107 UCHAR uc480p; 4108 UCHAR uc720p; 4109 UCHAR uc1080i; 4110 UCHAR ucReserved; 4111 UCHAR ucLetterBoxMode; 4112 UCHAR ucNumOfWbGpioBlocks; //For Component video D-Connector support. If zere, NTSC type connector 4113 ATOM_GPIO_INFO aWbGpioStateBlock[MAX_SUPPORTED_CV_STANDARDS]; 4114 ATOM_DTD_FORMAT aModeTimings[MAX_SUPPORTED_CV_STANDARDS]; 4115 }ATOM_COMPONENT_VIDEO_INFO_V21; 4116 4117 #define ATOM_COMPONENT_VIDEO_INFO_LAST ATOM_COMPONENT_VIDEO_INFO_V21 4118 4119 /****************************************************************************/ 4120 // Structure used in object_InfoTable 4121 /****************************************************************************/ 4122 typedef struct _ATOM_OBJECT_HEADER 4123 { 4124 ATOM_COMMON_TABLE_HEADER sHeader; 4125 USHORT usDeviceSupport; 4126 USHORT usConnectorObjectTableOffset; 4127 USHORT usRouterObjectTableOffset; 4128 USHORT usEncoderObjectTableOffset; 4129 USHORT usProtectionObjectTableOffset; //only available when Protection block is independent. 4130 USHORT usDisplayPathTableOffset; 4131 }ATOM_OBJECT_HEADER; 4132 4133 typedef struct _ATOM_OBJECT_HEADER_V3 4134 { 4135 ATOM_COMMON_TABLE_HEADER sHeader; 4136 USHORT usDeviceSupport; 4137 USHORT usConnectorObjectTableOffset; 4138 USHORT usRouterObjectTableOffset; 4139 USHORT usEncoderObjectTableOffset; 4140 USHORT usProtectionObjectTableOffset; //only available when Protection block is independent. 4141 USHORT usDisplayPathTableOffset; 4142 USHORT usMiscObjectTableOffset; 4143 }ATOM_OBJECT_HEADER_V3; 4144 4145 4146 typedef struct _ATOM_DISPLAY_OBJECT_PATH 4147 { 4148 USHORT usDeviceTag; //supported device 4149 USHORT usSize; //the size of ATOM_DISPLAY_OBJECT_PATH 4150 USHORT usConnObjectId; //Connector Object ID 4151 USHORT usGPUObjectId; //GPU ID 4152 USHORT usGraphicObjIds[1]; //1st Encoder Obj source from GPU to last Graphic Obj destinate to connector. 4153 }ATOM_DISPLAY_OBJECT_PATH; 4154 4155 typedef struct _ATOM_DISPLAY_EXTERNAL_OBJECT_PATH 4156 { 4157 USHORT usDeviceTag; //supported device 4158 USHORT usSize; //the size of ATOM_DISPLAY_OBJECT_PATH 4159 USHORT usConnObjectId; //Connector Object ID 4160 USHORT usGPUObjectId; //GPU ID 4161 USHORT usGraphicObjIds[2]; //usGraphicObjIds[0]= GPU internal encoder, usGraphicObjIds[1]= external encoder 4162 }ATOM_DISPLAY_EXTERNAL_OBJECT_PATH; 4163 4164 typedef struct _ATOM_DISPLAY_OBJECT_PATH_TABLE 4165 { 4166 UCHAR ucNumOfDispPath; 4167 UCHAR ucVersion; 4168 UCHAR ucPadding[2]; 4169 ATOM_DISPLAY_OBJECT_PATH asDispPath[1]; 4170 }ATOM_DISPLAY_OBJECT_PATH_TABLE; 4171 4172 typedef struct _ATOM_OBJECT //each object has this structure 4173 { 4174 USHORT usObjectID; 4175 USHORT usSrcDstTableOffset; 4176 USHORT usRecordOffset; //this pointing to a bunch of records defined below 4177 USHORT usReserved; 4178 }ATOM_OBJECT; 4179 4180 typedef struct _ATOM_OBJECT_TABLE //Above 4 object table offset pointing to a bunch of objects all have this structure 4181 { 4182 UCHAR ucNumberOfObjects; 4183 UCHAR ucPadding[3]; 4184 ATOM_OBJECT asObjects[1]; 4185 }ATOM_OBJECT_TABLE; 4186 4187 typedef struct _ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT //usSrcDstTableOffset pointing to this structure 4188 { 4189 UCHAR ucNumberOfSrc; 4190 USHORT usSrcObjectID[1]; 4191 UCHAR ucNumberOfDst; 4192 USHORT usDstObjectID[1]; 4193 }ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT; 4194 4195 4196 //Two definitions below are for OPM on MXM module designs 4197 4198 #define EXT_HPDPIN_LUTINDEX_0 0 4199 #define EXT_HPDPIN_LUTINDEX_1 1 4200 #define EXT_HPDPIN_LUTINDEX_2 2 4201 #define EXT_HPDPIN_LUTINDEX_3 3 4202 #define EXT_HPDPIN_LUTINDEX_4 4 4203 #define EXT_HPDPIN_LUTINDEX_5 5 4204 #define EXT_HPDPIN_LUTINDEX_6 6 4205 #define EXT_HPDPIN_LUTINDEX_7 7 4206 #define MAX_NUMBER_OF_EXT_HPDPIN_LUT_ENTRIES (EXT_HPDPIN_LUTINDEX_7+1) 4207 4208 #define EXT_AUXDDC_LUTINDEX_0 0 4209 #define EXT_AUXDDC_LUTINDEX_1 1 4210 #define EXT_AUXDDC_LUTINDEX_2 2 4211 #define EXT_AUXDDC_LUTINDEX_3 3 4212 #define EXT_AUXDDC_LUTINDEX_4 4 4213 #define EXT_AUXDDC_LUTINDEX_5 5 4214 #define EXT_AUXDDC_LUTINDEX_6 6 4215 #define EXT_AUXDDC_LUTINDEX_7 7 4216 #define MAX_NUMBER_OF_EXT_AUXDDC_LUT_ENTRIES (EXT_AUXDDC_LUTINDEX_7+1) 4217 4218 //ucChannelMapping are defined as following 4219 //for DP connector, eDP, DP to VGA/LVDS 4220 //Bit[1:0]: Define which pin connect to DP connector DP_Lane0, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3 4221 //Bit[3:2]: Define which pin connect to DP connector DP_Lane1, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3 4222 //Bit[5:4]: Define which pin connect to DP connector DP_Lane2, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3 4223 //Bit[7:6]: Define which pin connect to DP connector DP_Lane3, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3 4224 typedef struct _ATOM_DP_CONN_CHANNEL_MAPPING 4225 { 4226 #if ATOM_BIG_ENDIAN 4227 UCHAR ucDP_Lane3_Source:2; 4228 UCHAR ucDP_Lane2_Source:2; 4229 UCHAR ucDP_Lane1_Source:2; 4230 UCHAR ucDP_Lane0_Source:2; 4231 #else 4232 UCHAR ucDP_Lane0_Source:2; 4233 UCHAR ucDP_Lane1_Source:2; 4234 UCHAR ucDP_Lane2_Source:2; 4235 UCHAR ucDP_Lane3_Source:2; 4236 #endif 4237 }ATOM_DP_CONN_CHANNEL_MAPPING; 4238 4239 //for DVI/HDMI, in dual link case, both links have to have same mapping. 4240 //Bit[1:0]: Define which pin connect to DVI connector data Lane2, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3 4241 //Bit[3:2]: Define which pin connect to DVI connector data Lane1, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3 4242 //Bit[5:4]: Define which pin connect to DVI connector data Lane0, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3 4243 //Bit[7:6]: Define which pin connect to DVI connector clock lane, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3 4244 typedef struct _ATOM_DVI_CONN_CHANNEL_MAPPING 4245 { 4246 #if ATOM_BIG_ENDIAN 4247 UCHAR ucDVI_CLK_Source:2; 4248 UCHAR ucDVI_DATA0_Source:2; 4249 UCHAR ucDVI_DATA1_Source:2; 4250 UCHAR ucDVI_DATA2_Source:2; 4251 #else 4252 UCHAR ucDVI_DATA2_Source:2; 4253 UCHAR ucDVI_DATA1_Source:2; 4254 UCHAR ucDVI_DATA0_Source:2; 4255 UCHAR ucDVI_CLK_Source:2; 4256 #endif 4257 }ATOM_DVI_CONN_CHANNEL_MAPPING; 4258 4259 typedef struct _EXT_DISPLAY_PATH 4260 { 4261 USHORT usDeviceTag; //A bit vector to show what devices are supported 4262 USHORT usDeviceACPIEnum; //16bit device ACPI id. 4263 USHORT usDeviceConnector; //A physical connector for displays to plug in, using object connector definitions 4264 UCHAR ucExtAUXDDCLutIndex; //An index into external AUX/DDC channel LUT 4265 UCHAR ucExtHPDPINLutIndex; //An index into external HPD pin LUT 4266 USHORT usExtEncoderObjId; //external encoder object id 4267 union{ 4268 UCHAR ucChannelMapping; // if ucChannelMapping=0, using default one to one mapping 4269 ATOM_DP_CONN_CHANNEL_MAPPING asDPMapping; 4270 ATOM_DVI_CONN_CHANNEL_MAPPING asDVIMapping; 4271 }; 4272 UCHAR ucChPNInvert; // bit vector for up to 8 lanes, =0: P and N is not invert, =1 P and N is inverted 4273 USHORT usCaps; 4274 USHORT usReserved; 4275 }EXT_DISPLAY_PATH; 4276 4277 #define NUMBER_OF_UCHAR_FOR_GUID 16 4278 #define MAX_NUMBER_OF_EXT_DISPLAY_PATH 7 4279 4280 //usCaps 4281 #define EXT_DISPLAY_PATH_CAPS__HBR2_DISABLE 0x01 4282 #define EXT_DISPLAY_PATH_CAPS__DP_FIXED_VS_EN 0x02 4283 #define EXT_DISPLAY_PATH_CAPS__HDMI20_PI3EQX1204 0x04 4284 #define EXT_DISPLAY_PATH_CAPS__HDMI20_TISN65DP159RSBT 0x08 4285 4286 typedef struct _ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO 4287 { 4288 ATOM_COMMON_TABLE_HEADER sHeader; 4289 UCHAR ucGuid [NUMBER_OF_UCHAR_FOR_GUID]; // a GUID is a 16 byte long string 4290 EXT_DISPLAY_PATH sPath[MAX_NUMBER_OF_EXT_DISPLAY_PATH]; // total of fixed 7 entries. 4291 UCHAR ucChecksum; // a simple Checksum of the sum of whole structure equal to 0x0. 4292 UCHAR uc3DStereoPinId; // use for eDP panel 4293 UCHAR ucRemoteDisplayConfig; 4294 UCHAR uceDPToLVDSRxId; 4295 UCHAR ucFixDPVoltageSwing; // usCaps[1]=1, this indicate DP_LANE_SET value 4296 UCHAR Reserved[3]; // for potential expansion 4297 }ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO; 4298 4299 //Related definitions, all records are differnt but they have a commond header 4300 typedef struct _ATOM_COMMON_RECORD_HEADER 4301 { 4302 UCHAR ucRecordType; //An emun to indicate the record type 4303 UCHAR ucRecordSize; //The size of the whole record in byte 4304 }ATOM_COMMON_RECORD_HEADER; 4305 4306 4307 #define ATOM_I2C_RECORD_TYPE 1 4308 #define ATOM_HPD_INT_RECORD_TYPE 2 4309 #define ATOM_OUTPUT_PROTECTION_RECORD_TYPE 3 4310 #define ATOM_CONNECTOR_DEVICE_TAG_RECORD_TYPE 4 4311 #define ATOM_CONNECTOR_DVI_EXT_INPUT_RECORD_TYPE 5 //Obsolete, switch to use GPIO_CNTL_RECORD_TYPE 4312 #define ATOM_ENCODER_FPGA_CONTROL_RECORD_TYPE 6 //Obsolete, switch to use GPIO_CNTL_RECORD_TYPE 4313 #define ATOM_CONNECTOR_CVTV_SHARE_DIN_RECORD_TYPE 7 4314 #define ATOM_JTAG_RECORD_TYPE 8 //Obsolete, switch to use GPIO_CNTL_RECORD_TYPE 4315 #define ATOM_OBJECT_GPIO_CNTL_RECORD_TYPE 9 4316 #define ATOM_ENCODER_DVO_CF_RECORD_TYPE 10 4317 #define ATOM_CONNECTOR_CF_RECORD_TYPE 11 4318 #define ATOM_CONNECTOR_HARDCODE_DTD_RECORD_TYPE 12 4319 #define ATOM_CONNECTOR_PCIE_SUBCONNECTOR_RECORD_TYPE 13 4320 #define ATOM_ROUTER_DDC_PATH_SELECT_RECORD_TYPE 14 4321 #define ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD_TYPE 15 4322 #define ATOM_CONNECTOR_HPDPIN_LUT_RECORD_TYPE 16 //This is for the case when connectors are not known to object table 4323 #define ATOM_CONNECTOR_AUXDDC_LUT_RECORD_TYPE 17 //This is for the case when connectors are not known to object table 4324 #define ATOM_OBJECT_LINK_RECORD_TYPE 18 //Once this record is present under one object, it indicats the oobject is linked to another obj described by the record 4325 #define ATOM_CONNECTOR_REMOTE_CAP_RECORD_TYPE 19 4326 #define ATOM_ENCODER_CAP_RECORD_TYPE 20 4327 #define ATOM_BRACKET_LAYOUT_RECORD_TYPE 21 4328 4329 4330 //Must be updated when new record type is added,equal to that record definition! 4331 #define ATOM_MAX_OBJECT_RECORD_NUMBER ATOM_ENCODER_CAP_RECORD_TYPE 4332 4333 typedef struct _ATOM_I2C_RECORD 4334 { 4335 ATOM_COMMON_RECORD_HEADER sheader; 4336 ATOM_I2C_ID_CONFIG sucI2cId; 4337 UCHAR ucI2CAddr; //The slave address, it's 0 when the record is attached to connector for DDC 4338 }ATOM_I2C_RECORD; 4339 4340 typedef struct _ATOM_HPD_INT_RECORD 4341 { 4342 ATOM_COMMON_RECORD_HEADER sheader; 4343 UCHAR ucHPDIntGPIOID; //Corresponding block in GPIO_PIN_INFO table gives the pin info 4344 UCHAR ucPlugged_PinState; 4345 }ATOM_HPD_INT_RECORD; 4346 4347 4348 typedef struct _ATOM_OUTPUT_PROTECTION_RECORD 4349 { 4350 ATOM_COMMON_RECORD_HEADER sheader; 4351 UCHAR ucProtectionFlag; 4352 UCHAR ucReserved; 4353 }ATOM_OUTPUT_PROTECTION_RECORD; 4354 4355 typedef struct _ATOM_CONNECTOR_DEVICE_TAG 4356 { 4357 ULONG ulACPIDeviceEnum; //Reserved for now 4358 USHORT usDeviceID; //This Id is same as "ATOM_DEVICE_XXX_SUPPORT" 4359 USHORT usPadding; 4360 }ATOM_CONNECTOR_DEVICE_TAG; 4361 4362 typedef struct _ATOM_CONNECTOR_DEVICE_TAG_RECORD 4363 { 4364 ATOM_COMMON_RECORD_HEADER sheader; 4365 UCHAR ucNumberOfDevice; 4366 UCHAR ucReserved; 4367 ATOM_CONNECTOR_DEVICE_TAG asDeviceTag[1]; //This Id is same as "ATOM_DEVICE_XXX_SUPPORT", 1 is only for allocation 4368 }ATOM_CONNECTOR_DEVICE_TAG_RECORD; 4369 4370 4371 typedef struct _ATOM_CONNECTOR_DVI_EXT_INPUT_RECORD 4372 { 4373 ATOM_COMMON_RECORD_HEADER sheader; 4374 UCHAR ucConfigGPIOID; 4375 UCHAR ucConfigGPIOState; //Set to 1 when it's active high to enable external flow in 4376 UCHAR ucFlowinGPIPID; 4377 UCHAR ucExtInGPIPID; 4378 }ATOM_CONNECTOR_DVI_EXT_INPUT_RECORD; 4379 4380 typedef struct _ATOM_ENCODER_FPGA_CONTROL_RECORD 4381 { 4382 ATOM_COMMON_RECORD_HEADER sheader; 4383 UCHAR ucCTL1GPIO_ID; 4384 UCHAR ucCTL1GPIOState; //Set to 1 when it's active high 4385 UCHAR ucCTL2GPIO_ID; 4386 UCHAR ucCTL2GPIOState; //Set to 1 when it's active high 4387 UCHAR ucCTL3GPIO_ID; 4388 UCHAR ucCTL3GPIOState; //Set to 1 when it's active high 4389 UCHAR ucCTLFPGA_IN_ID; 4390 UCHAR ucPadding[3]; 4391 }ATOM_ENCODER_FPGA_CONTROL_RECORD; 4392 4393 typedef struct _ATOM_CONNECTOR_CVTV_SHARE_DIN_RECORD 4394 { 4395 ATOM_COMMON_RECORD_HEADER sheader; 4396 UCHAR ucGPIOID; //Corresponding block in GPIO_PIN_INFO table gives the pin info 4397 UCHAR ucTVActiveState; //Indicating when the pin==0 or 1 when TV is connected 4398 }ATOM_CONNECTOR_CVTV_SHARE_DIN_RECORD; 4399 4400 typedef struct _ATOM_JTAG_RECORD 4401 { 4402 ATOM_COMMON_RECORD_HEADER sheader; 4403 UCHAR ucTMSGPIO_ID; 4404 UCHAR ucTMSGPIOState; //Set to 1 when it's active high 4405 UCHAR ucTCKGPIO_ID; 4406 UCHAR ucTCKGPIOState; //Set to 1 when it's active high 4407 UCHAR ucTDOGPIO_ID; 4408 UCHAR ucTDOGPIOState; //Set to 1 when it's active high 4409 UCHAR ucTDIGPIO_ID; 4410 UCHAR ucTDIGPIOState; //Set to 1 when it's active high 4411 UCHAR ucPadding[2]; 4412 }ATOM_JTAG_RECORD; 4413 4414 4415 //The following generic object gpio pin control record type will replace JTAG_RECORD/FPGA_CONTROL_RECORD/DVI_EXT_INPUT_RECORD above gradually 4416 typedef struct _ATOM_GPIO_PIN_CONTROL_PAIR 4417 { 4418 UCHAR ucGPIOID; // GPIO_ID, find the corresponding ID in GPIO_LUT table 4419 UCHAR ucGPIO_PinState; // Pin state showing how to set-up the pin 4420 }ATOM_GPIO_PIN_CONTROL_PAIR; 4421 4422 typedef struct _ATOM_OBJECT_GPIO_CNTL_RECORD 4423 { 4424 ATOM_COMMON_RECORD_HEADER sheader; 4425 UCHAR ucFlags; // Future expnadibility 4426 UCHAR ucNumberOfPins; // Number of GPIO pins used to control the object 4427 ATOM_GPIO_PIN_CONTROL_PAIR asGpio[1]; // the real gpio pin pair determined by number of pins ucNumberOfPins 4428 }ATOM_OBJECT_GPIO_CNTL_RECORD; 4429 4430 //Definitions for GPIO pin state 4431 #define GPIO_PIN_TYPE_INPUT 0x00 4432 #define GPIO_PIN_TYPE_OUTPUT 0x10 4433 #define GPIO_PIN_TYPE_HW_CONTROL 0x20 4434 4435 //For GPIO_PIN_TYPE_OUTPUT the following is defined 4436 #define GPIO_PIN_OUTPUT_STATE_MASK 0x01 4437 #define GPIO_PIN_OUTPUT_STATE_SHIFT 0 4438 #define GPIO_PIN_STATE_ACTIVE_LOW 0x0 4439 #define GPIO_PIN_STATE_ACTIVE_HIGH 0x1 4440 4441 // Indexes to GPIO array in GLSync record 4442 // GLSync record is for Frame Lock/Gen Lock feature. 4443 #define ATOM_GPIO_INDEX_GLSYNC_REFCLK 0 4444 #define ATOM_GPIO_INDEX_GLSYNC_HSYNC 1 4445 #define ATOM_GPIO_INDEX_GLSYNC_VSYNC 2 4446 #define ATOM_GPIO_INDEX_GLSYNC_SWAP_REQ 3 4447 #define ATOM_GPIO_INDEX_GLSYNC_SWAP_GNT 4 4448 #define ATOM_GPIO_INDEX_GLSYNC_INTERRUPT 5 4449 #define ATOM_GPIO_INDEX_GLSYNC_V_RESET 6 4450 #define ATOM_GPIO_INDEX_GLSYNC_SWAP_CNTL 7 4451 #define ATOM_GPIO_INDEX_GLSYNC_SWAP_SEL 8 4452 #define ATOM_GPIO_INDEX_GLSYNC_MAX 9 4453 4454 typedef struct _ATOM_ENCODER_DVO_CF_RECORD 4455 { 4456 ATOM_COMMON_RECORD_HEADER sheader; 4457 ULONG ulStrengthControl; // DVOA strength control for CF 4458 UCHAR ucPadding[2]; 4459 }ATOM_ENCODER_DVO_CF_RECORD; 4460 4461 // Bit maps for ATOM_ENCODER_CAP_RECORD.ucEncoderCap 4462 #define ATOM_ENCODER_CAP_RECORD_HBR2 0x01 // DP1.2 HBR2 is supported by HW encoder 4463 #define ATOM_ENCODER_CAP_RECORD_HBR2_EN 0x02 // DP1.2 HBR2 setting is qualified and HBR2 can be enabled 4464 #define ATOM_ENCODER_CAP_RECORD_HDMI6Gbps_EN 0x04 // HDMI2.0 6Gbps enable or not. 4465 4466 typedef struct _ATOM_ENCODER_CAP_RECORD 4467 { 4468 ATOM_COMMON_RECORD_HEADER sheader; 4469 union { 4470 USHORT usEncoderCap; 4471 struct { 4472 #if ATOM_BIG_ENDIAN 4473 USHORT usReserved:14; // Bit1-15 may be defined for other capability in future 4474 USHORT usHBR2En:1; // Bit1 is for DP1.2 HBR2 enable 4475 USHORT usHBR2Cap:1; // Bit0 is for DP1.2 HBR2 capability. 4476 #else 4477 USHORT usHBR2Cap:1; // Bit0 is for DP1.2 HBR2 capability. 4478 USHORT usHBR2En:1; // Bit1 is for DP1.2 HBR2 enable 4479 USHORT usReserved:14; // Bit1-15 may be defined for other capability in future 4480 #endif 4481 }; 4482 }; 4483 }ATOM_ENCODER_CAP_RECORD; 4484 4485 // value for ATOM_CONNECTOR_CF_RECORD.ucConnectedDvoBundle 4486 #define ATOM_CONNECTOR_CF_RECORD_CONNECTED_UPPER12BITBUNDLEA 1 4487 #define ATOM_CONNECTOR_CF_RECORD_CONNECTED_LOWER12BITBUNDLEB 2 4488 4489 typedef struct _ATOM_CONNECTOR_CF_RECORD 4490 { 4491 ATOM_COMMON_RECORD_HEADER sheader; 4492 USHORT usMaxPixClk; 4493 UCHAR ucFlowCntlGpioId; 4494 UCHAR ucSwapCntlGpioId; 4495 UCHAR ucConnectedDvoBundle; 4496 UCHAR ucPadding; 4497 }ATOM_CONNECTOR_CF_RECORD; 4498 4499 typedef struct _ATOM_CONNECTOR_HARDCODE_DTD_RECORD 4500 { 4501 ATOM_COMMON_RECORD_HEADER sheader; 4502 ATOM_DTD_FORMAT asTiming; 4503 }ATOM_CONNECTOR_HARDCODE_DTD_RECORD; 4504 4505 typedef struct _ATOM_CONNECTOR_PCIE_SUBCONNECTOR_RECORD 4506 { 4507 ATOM_COMMON_RECORD_HEADER sheader; //ATOM_CONNECTOR_PCIE_SUBCONNECTOR_RECORD_TYPE 4508 UCHAR ucSubConnectorType; //CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D|X_ID_DUAL_LINK_DVI_D|HDMI_TYPE_A 4509 UCHAR ucReserved; 4510 }ATOM_CONNECTOR_PCIE_SUBCONNECTOR_RECORD; 4511 4512 4513 typedef struct _ATOM_ROUTER_DDC_PATH_SELECT_RECORD 4514 { 4515 ATOM_COMMON_RECORD_HEADER sheader; 4516 UCHAR ucMuxType; //decide the number of ucMuxState, =0, no pin state, =1: single state with complement, >1: multiple state 4517 UCHAR ucMuxControlPin; 4518 UCHAR ucMuxState[2]; //for alligment purpose 4519 }ATOM_ROUTER_DDC_PATH_SELECT_RECORD; 4520 4521 typedef struct _ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD 4522 { 4523 ATOM_COMMON_RECORD_HEADER sheader; 4524 UCHAR ucMuxType; 4525 UCHAR ucMuxControlPin; 4526 UCHAR ucMuxState[2]; //for alligment purpose 4527 }ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD; 4528 4529 // define ucMuxType 4530 #define ATOM_ROUTER_MUX_PIN_STATE_MASK 0x0f 4531 #define ATOM_ROUTER_MUX_PIN_SINGLE_STATE_COMPLEMENT 0x01 4532 4533 typedef struct _ATOM_CONNECTOR_HPDPIN_LUT_RECORD //record for ATOM_CONNECTOR_HPDPIN_LUT_RECORD_TYPE 4534 { 4535 ATOM_COMMON_RECORD_HEADER sheader; 4536 UCHAR ucHPDPINMap[MAX_NUMBER_OF_EXT_HPDPIN_LUT_ENTRIES]; //An fixed size array which maps external pins to internal GPIO_PIN_INFO table 4537 }ATOM_CONNECTOR_HPDPIN_LUT_RECORD; 4538 4539 typedef struct _ATOM_CONNECTOR_AUXDDC_LUT_RECORD //record for ATOM_CONNECTOR_AUXDDC_LUT_RECORD_TYPE 4540 { 4541 ATOM_COMMON_RECORD_HEADER sheader; 4542 ATOM_I2C_ID_CONFIG ucAUXDDCMap[MAX_NUMBER_OF_EXT_AUXDDC_LUT_ENTRIES]; //An fixed size array which maps external pins to internal DDC ID 4543 }ATOM_CONNECTOR_AUXDDC_LUT_RECORD; 4544 4545 typedef struct _ATOM_OBJECT_LINK_RECORD 4546 { 4547 ATOM_COMMON_RECORD_HEADER sheader; 4548 USHORT usObjectID; //could be connector, encorder or other object in object.h 4549 }ATOM_OBJECT_LINK_RECORD; 4550 4551 typedef struct _ATOM_CONNECTOR_REMOTE_CAP_RECORD 4552 { 4553 ATOM_COMMON_RECORD_HEADER sheader; 4554 USHORT usReserved; 4555 }ATOM_CONNECTOR_REMOTE_CAP_RECORD; 4556 4557 typedef struct _ATOM_CONNECTOR_LAYOUT_INFO 4558 { 4559 USHORT usConnectorObjectId; 4560 UCHAR ucConnectorType; 4561 UCHAR ucPosition; 4562 }ATOM_CONNECTOR_LAYOUT_INFO; 4563 4564 // define ATOM_CONNECTOR_LAYOUT_INFO.ucConnectorType to describe the display connector size 4565 #define CONNECTOR_TYPE_DVI_D 1 4566 #define CONNECTOR_TYPE_DVI_I 2 4567 #define CONNECTOR_TYPE_VGA 3 4568 #define CONNECTOR_TYPE_HDMI 4 4569 #define CONNECTOR_TYPE_DISPLAY_PORT 5 4570 #define CONNECTOR_TYPE_MINI_DISPLAY_PORT 6 4571 4572 typedef struct _ATOM_BRACKET_LAYOUT_RECORD 4573 { 4574 ATOM_COMMON_RECORD_HEADER sheader; 4575 UCHAR ucLength; 4576 UCHAR ucWidth; 4577 UCHAR ucConnNum; 4578 UCHAR ucReserved; 4579 ATOM_CONNECTOR_LAYOUT_INFO asConnInfo[1]; 4580 }ATOM_BRACKET_LAYOUT_RECORD; 4581 4582 4583 /****************************************************************************/ 4584 // Structure used in XXXX 4585 /****************************************************************************/ 4586 typedef struct _ATOM_VOLTAGE_INFO_HEADER 4587 { 4588 USHORT usVDDCBaseLevel; //In number of 50mv unit 4589 USHORT usReserved; //For possible extension table offset 4590 UCHAR ucNumOfVoltageEntries; 4591 UCHAR ucBytesPerVoltageEntry; 4592 UCHAR ucVoltageStep; //Indicating in how many mv increament is one step, 0.5mv unit 4593 UCHAR ucDefaultVoltageEntry; 4594 UCHAR ucVoltageControlI2cLine; 4595 UCHAR ucVoltageControlAddress; 4596 UCHAR ucVoltageControlOffset; 4597 }ATOM_VOLTAGE_INFO_HEADER; 4598 4599 typedef struct _ATOM_VOLTAGE_INFO 4600 { 4601 ATOM_COMMON_TABLE_HEADER sHeader; 4602 ATOM_VOLTAGE_INFO_HEADER viHeader; 4603 UCHAR ucVoltageEntries[64]; //64 is for allocation, the actual number of entry is present at ucNumOfVoltageEntries*ucBytesPerVoltageEntry 4604 }ATOM_VOLTAGE_INFO; 4605 4606 4607 typedef struct _ATOM_VOLTAGE_FORMULA 4608 { 4609 USHORT usVoltageBaseLevel; // In number of 1mv unit 4610 USHORT usVoltageStep; // Indicating in how many mv increament is one step, 1mv unit 4611 UCHAR ucNumOfVoltageEntries; // Number of Voltage Entry, which indicate max Voltage 4612 UCHAR ucFlag; // bit0=0 :step is 1mv =1 0.5mv 4613 UCHAR ucBaseVID; // if there is no lookup table, VID= BaseVID + ( Vol - BaseLevle ) /VoltageStep 4614 UCHAR ucReserved; 4615 UCHAR ucVIDAdjustEntries[32]; // 32 is for allocation, the actual number of entry is present at ucNumOfVoltageEntries 4616 }ATOM_VOLTAGE_FORMULA; 4617 4618 typedef struct _VOLTAGE_LUT_ENTRY 4619 { 4620 USHORT usVoltageCode; // The Voltage ID, either GPIO or I2C code 4621 USHORT usVoltageValue; // The corresponding Voltage Value, in mV 4622 }VOLTAGE_LUT_ENTRY; 4623 4624 typedef struct _ATOM_VOLTAGE_FORMULA_V2 4625 { 4626 UCHAR ucNumOfVoltageEntries; // Number of Voltage Entry, which indicate max Voltage 4627 UCHAR ucReserved[3]; 4628 VOLTAGE_LUT_ENTRY asVIDAdjustEntries[32];// 32 is for allocation, the actual number of entries is in ucNumOfVoltageEntries 4629 }ATOM_VOLTAGE_FORMULA_V2; 4630 4631 typedef struct _ATOM_VOLTAGE_CONTROL 4632 { 4633 UCHAR ucVoltageControlId; //Indicate it is controlled by I2C or GPIO or HW state machine 4634 UCHAR ucVoltageControlI2cLine; 4635 UCHAR ucVoltageControlAddress; 4636 UCHAR ucVoltageControlOffset; 4637 USHORT usGpioPin_AIndex; //GPIO_PAD register index 4638 UCHAR ucGpioPinBitShift[9]; //at most 8 pin support 255 VIDs, termintate with 0xff 4639 UCHAR ucReserved; 4640 }ATOM_VOLTAGE_CONTROL; 4641 4642 // Define ucVoltageControlId 4643 #define VOLTAGE_CONTROLLED_BY_HW 0x00 4644 #define VOLTAGE_CONTROLLED_BY_I2C_MASK 0x7F 4645 #define VOLTAGE_CONTROLLED_BY_GPIO 0x80 4646 #define VOLTAGE_CONTROL_ID_LM64 0x01 //I2C control, used for R5xx Core Voltage 4647 #define VOLTAGE_CONTROL_ID_DAC 0x02 //I2C control, used for R5xx/R6xx MVDDC,MVDDQ or VDDCI 4648 #define VOLTAGE_CONTROL_ID_VT116xM 0x03 //I2C control, used for R6xx Core Voltage 4649 #define VOLTAGE_CONTROL_ID_DS4402 0x04 4650 #define VOLTAGE_CONTROL_ID_UP6266 0x05 4651 #define VOLTAGE_CONTROL_ID_SCORPIO 0x06 4652 #define VOLTAGE_CONTROL_ID_VT1556M 0x07 4653 #define VOLTAGE_CONTROL_ID_CHL822x 0x08 4654 #define VOLTAGE_CONTROL_ID_VT1586M 0x09 4655 #define VOLTAGE_CONTROL_ID_UP1637 0x0A 4656 #define VOLTAGE_CONTROL_ID_CHL8214 0x0B 4657 #define VOLTAGE_CONTROL_ID_UP1801 0x0C 4658 #define VOLTAGE_CONTROL_ID_ST6788A 0x0D 4659 #define VOLTAGE_CONTROL_ID_CHLIR3564SVI2 0x0E 4660 #define VOLTAGE_CONTROL_ID_AD527x 0x0F 4661 #define VOLTAGE_CONTROL_ID_NCP81022 0x10 4662 #define VOLTAGE_CONTROL_ID_LTC2635 0x11 4663 #define VOLTAGE_CONTROL_ID_NCP4208 0x12 4664 #define VOLTAGE_CONTROL_ID_IR35xx 0x13 4665 #define VOLTAGE_CONTROL_ID_RT9403 0x14 4666 4667 #define VOLTAGE_CONTROL_ID_GENERIC_I2C 0x40 4668 4669 typedef struct _ATOM_VOLTAGE_OBJECT 4670 { 4671 UCHAR ucVoltageType; //Indicate Voltage Source: VDDC, MVDDC, MVDDQ or MVDDCI 4672 UCHAR ucSize; //Size of Object 4673 ATOM_VOLTAGE_CONTROL asControl; //describ how to control 4674 ATOM_VOLTAGE_FORMULA asFormula; //Indicate How to convert real Voltage to VID 4675 }ATOM_VOLTAGE_OBJECT; 4676 4677 typedef struct _ATOM_VOLTAGE_OBJECT_V2 4678 { 4679 UCHAR ucVoltageType; //Indicate Voltage Source: VDDC, MVDDC, MVDDQ or MVDDCI 4680 UCHAR ucSize; //Size of Object 4681 ATOM_VOLTAGE_CONTROL asControl; //describ how to control 4682 ATOM_VOLTAGE_FORMULA_V2 asFormula; //Indicate How to convert real Voltage to VID 4683 }ATOM_VOLTAGE_OBJECT_V2; 4684 4685 typedef struct _ATOM_VOLTAGE_OBJECT_INFO 4686 { 4687 ATOM_COMMON_TABLE_HEADER sHeader; 4688 ATOM_VOLTAGE_OBJECT asVoltageObj[3]; //Info for Voltage control 4689 }ATOM_VOLTAGE_OBJECT_INFO; 4690 4691 typedef struct _ATOM_VOLTAGE_OBJECT_INFO_V2 4692 { 4693 ATOM_COMMON_TABLE_HEADER sHeader; 4694 ATOM_VOLTAGE_OBJECT_V2 asVoltageObj[3]; //Info for Voltage control 4695 }ATOM_VOLTAGE_OBJECT_INFO_V2; 4696 4697 typedef struct _ATOM_LEAKID_VOLTAGE 4698 { 4699 UCHAR ucLeakageId; 4700 UCHAR ucReserved; 4701 USHORT usVoltage; 4702 }ATOM_LEAKID_VOLTAGE; 4703 4704 typedef struct _ATOM_VOLTAGE_OBJECT_HEADER_V3{ 4705 UCHAR ucVoltageType; //Indicate Voltage Source: VDDC, MVDDC, MVDDQ or MVDDCI 4706 UCHAR ucVoltageMode; //Indicate voltage control mode: Init/Set/Leakage/Set phase 4707 USHORT usSize; //Size of Object 4708 }ATOM_VOLTAGE_OBJECT_HEADER_V3; 4709 4710 // ATOM_VOLTAGE_OBJECT_HEADER_V3.ucVoltageMode 4711 #define VOLTAGE_OBJ_GPIO_LUT 0 //VOLTAGE and GPIO Lookup table ->ATOM_GPIO_VOLTAGE_OBJECT_V3 4712 #define VOLTAGE_OBJ_VR_I2C_INIT_SEQ 3 //VOLTAGE REGULATOR INIT sequece through I2C -> ATOM_I2C_VOLTAGE_OBJECT_V3 4713 #define VOLTAGE_OBJ_PHASE_LUT 4 //Set Vregulator Phase lookup table ->ATOM_GPIO_VOLTAGE_OBJECT_V3 4714 #define VOLTAGE_OBJ_SVID2 7 //Indicate voltage control by SVID2 ->ATOM_SVID2_VOLTAGE_OBJECT_V3 4715 #define VOLTAGE_OBJ_EVV 8 4716 #define VOLTAGE_OBJ_PWRBOOST_LEAKAGE_LUT 0x10 //Powerboost Voltage and LeakageId lookup table->ATOM_LEAKAGE_VOLTAGE_OBJECT_V3 4717 #define VOLTAGE_OBJ_HIGH_STATE_LEAKAGE_LUT 0x11 //High voltage state Voltage and LeakageId lookup table->ATOM_LEAKAGE_VOLTAGE_OBJECT_V3 4718 #define VOLTAGE_OBJ_HIGH1_STATE_LEAKAGE_LUT 0x12 //High1 voltage state Voltage and LeakageId lookup table->ATOM_LEAKAGE_VOLTAGE_OBJECT_V3 4719 4720 typedef struct _VOLTAGE_LUT_ENTRY_V2 4721 { 4722 ULONG ulVoltageId; // The Voltage ID which is used to program GPIO register 4723 USHORT usVoltageValue; // The corresponding Voltage Value, in mV 4724 }VOLTAGE_LUT_ENTRY_V2; 4725 4726 typedef struct _LEAKAGE_VOLTAGE_LUT_ENTRY_V2 4727 { 4728 USHORT usVoltageLevel; // The Voltage ID which is used to program GPIO register 4729 USHORT usVoltageId; 4730 USHORT usLeakageId; // The corresponding Voltage Value, in mV 4731 }LEAKAGE_VOLTAGE_LUT_ENTRY_V2; 4732 4733 4734 typedef struct _ATOM_I2C_VOLTAGE_OBJECT_V3 4735 { 4736 ATOM_VOLTAGE_OBJECT_HEADER_V3 sHeader; // voltage mode = VOLTAGE_OBJ_VR_I2C_INIT_SEQ 4737 UCHAR ucVoltageRegulatorId; //Indicate Voltage Regulator Id 4738 UCHAR ucVoltageControlI2cLine; 4739 UCHAR ucVoltageControlAddress; 4740 UCHAR ucVoltageControlOffset; 4741 UCHAR ucVoltageControlFlag; // Bit0: 0 - One byte data; 1 - Two byte data 4742 UCHAR ulReserved[3]; 4743 VOLTAGE_LUT_ENTRY asVolI2cLut[1]; // end with 0xff 4744 }ATOM_I2C_VOLTAGE_OBJECT_V3; 4745 4746 // ATOM_I2C_VOLTAGE_OBJECT_V3.ucVoltageControlFlag 4747 #define VOLTAGE_DATA_ONE_BYTE 0 4748 #define VOLTAGE_DATA_TWO_BYTE 1 4749 4750 typedef struct _ATOM_GPIO_VOLTAGE_OBJECT_V3 4751 { 4752 ATOM_VOLTAGE_OBJECT_HEADER_V3 sHeader; // voltage mode = VOLTAGE_OBJ_GPIO_LUT or VOLTAGE_OBJ_PHASE_LUT 4753 UCHAR ucVoltageGpioCntlId; // default is 0 which indicate control through CG VID mode 4754 UCHAR ucGpioEntryNum; // indiate the entry numbers of Votlage/Gpio value Look up table 4755 UCHAR ucPhaseDelay; // phase delay in unit of micro second 4756 UCHAR ucReserved; 4757 ULONG ulGpioMaskVal; // GPIO Mask value 4758 VOLTAGE_LUT_ENTRY_V2 asVolGpioLut[1]; 4759 }ATOM_GPIO_VOLTAGE_OBJECT_V3; 4760 4761 typedef struct _ATOM_LEAKAGE_VOLTAGE_OBJECT_V3 4762 { 4763 ATOM_VOLTAGE_OBJECT_HEADER_V3 sHeader; // voltage mode = 0x10/0x11/0x12 4764 UCHAR ucLeakageCntlId; // default is 0 4765 UCHAR ucLeakageEntryNum; // indicate the entry number of LeakageId/Voltage Lut table 4766 UCHAR ucReserved[2]; 4767 ULONG ulMaxVoltageLevel; 4768 LEAKAGE_VOLTAGE_LUT_ENTRY_V2 asLeakageIdLut[1]; 4769 }ATOM_LEAKAGE_VOLTAGE_OBJECT_V3; 4770 4771 4772 typedef struct _ATOM_SVID2_VOLTAGE_OBJECT_V3 4773 { 4774 ATOM_VOLTAGE_OBJECT_HEADER_V3 sHeader; // voltage mode = VOLTAGE_OBJ_SVID2 4775 // 14:7 � PSI0_VID 4776 // 6 � PSI0_EN 4777 // 5 � PSI1 4778 // 4:2 � load line slope trim. 4779 // 1:0 � offset trim, 4780 USHORT usLoadLine_PSI; 4781 // GPU GPIO pin Id to SVID2 regulator VRHot pin. possible value 0~31. 0 means GPIO0, 31 means GPIO31 4782 UCHAR ucSVDGpioId; //0~31 indicate GPIO0~31 4783 UCHAR ucSVCGpioId; //0~31 indicate GPIO0~31 4784 ULONG ulReserved; 4785 }ATOM_SVID2_VOLTAGE_OBJECT_V3; 4786 4787 typedef union _ATOM_VOLTAGE_OBJECT_V3{ 4788 ATOM_GPIO_VOLTAGE_OBJECT_V3 asGpioVoltageObj; 4789 ATOM_I2C_VOLTAGE_OBJECT_V3 asI2cVoltageObj; 4790 ATOM_LEAKAGE_VOLTAGE_OBJECT_V3 asLeakageObj; 4791 ATOM_SVID2_VOLTAGE_OBJECT_V3 asSVID2Obj; 4792 }ATOM_VOLTAGE_OBJECT_V3; 4793 4794 typedef struct _ATOM_VOLTAGE_OBJECT_INFO_V3_1 4795 { 4796 ATOM_COMMON_TABLE_HEADER sHeader; 4797 ATOM_VOLTAGE_OBJECT_V3 asVoltageObj[3]; //Info for Voltage control 4798 }ATOM_VOLTAGE_OBJECT_INFO_V3_1; 4799 4800 4801 typedef struct _ATOM_ASIC_PROFILE_VOLTAGE 4802 { 4803 UCHAR ucProfileId; 4804 UCHAR ucReserved; 4805 USHORT usSize; 4806 USHORT usEfuseSpareStartAddr; 4807 USHORT usFuseIndex[8]; //from LSB to MSB, Max 8bit,end of 0xffff if less than 8 efuse id, 4808 ATOM_LEAKID_VOLTAGE asLeakVol[2]; //Leakid and relatd voltage 4809 }ATOM_ASIC_PROFILE_VOLTAGE; 4810 4811 //ucProfileId 4812 #define ATOM_ASIC_PROFILE_ID_EFUSE_VOLTAGE 1 4813 #define ATOM_ASIC_PROFILE_ID_EFUSE_PERFORMANCE_VOLTAGE 1 4814 #define ATOM_ASIC_PROFILE_ID_EFUSE_THERMAL_VOLTAGE 2 4815 4816 typedef struct _ATOM_ASIC_PROFILING_INFO 4817 { 4818 ATOM_COMMON_TABLE_HEADER asHeader; 4819 ATOM_ASIC_PROFILE_VOLTAGE asVoltage; 4820 }ATOM_ASIC_PROFILING_INFO; 4821 4822 typedef struct _ATOM_ASIC_PROFILING_INFO_V2_1 4823 { 4824 ATOM_COMMON_TABLE_HEADER asHeader; 4825 UCHAR ucLeakageBinNum; // indicate the entry number of LeakageId/Voltage Lut table 4826 USHORT usLeakageBinArrayOffset; // offset of USHORT Leakage Bin list array ( from lower LeakageId to higher) 4827 4828 UCHAR ucElbVDDC_Num; 4829 USHORT usElbVDDC_IdArrayOffset; // offset of USHORT virtual VDDC voltage id ( 0xff01~0xff08 ) 4830 USHORT usElbVDDC_LevelArrayOffset; // offset of 2 dimension voltage level USHORT array 4831 4832 UCHAR ucElbVDDCI_Num; 4833 USHORT usElbVDDCI_IdArrayOffset; // offset of USHORT virtual VDDCI voltage id ( 0xff01~0xff08 ) 4834 USHORT usElbVDDCI_LevelArrayOffset; // offset of 2 dimension voltage level USHORT array 4835 }ATOM_ASIC_PROFILING_INFO_V2_1; 4836 4837 4838 //Here is parameter to convert Efuse value to Measure value 4839 //Measured = LN((2^Bitsize-1)/EFUSE-1)*(Range)/(-alpha)+(Max+Min)/2 4840 typedef struct _EFUSE_LOGISTIC_FUNC_PARAM 4841 { 4842 USHORT usEfuseIndex; // Efuse Index in DWORD address, for example Index 911, usEuseIndex=112 4843 UCHAR ucEfuseBitLSB; // Efuse bit LSB in DWORD address, for example Index 911, usEfuseBitLSB= 911-112*8=15 4844 UCHAR ucEfuseLength; // Efuse bits length, 4845 ULONG ulEfuseEncodeRange; // Range = Max - Min, bit31 indicate the efuse is negative number 4846 ULONG ulEfuseEncodeAverage; // Average = ( Max + Min )/2 4847 }EFUSE_LOGISTIC_FUNC_PARAM; 4848 4849 //Linear Function: Measured = Round ( Efuse * ( Max-Min )/(2^BitSize -1 ) + Min ) 4850 typedef struct _EFUSE_LINEAR_FUNC_PARAM 4851 { 4852 USHORT usEfuseIndex; // Efuse Index in DWORD address, for example Index 911, usEuseIndex=112 4853 UCHAR ucEfuseBitLSB; // Efuse bit LSB in DWORD address, for example Index 911, usEfuseBitLSB= 911-112*8=15 4854 UCHAR ucEfuseLength; // Efuse bits length, 4855 ULONG ulEfuseEncodeRange; // Range = Max - Min, bit31 indicate the efuse is negative number 4856 ULONG ulEfuseMin; // Min 4857 }EFUSE_LINEAR_FUNC_PARAM; 4858 4859 4860 typedef struct _ATOM_ASIC_PROFILING_INFO_V3_1 4861 { 4862 ATOM_COMMON_TABLE_HEADER asHeader; 4863 ULONG ulEvvDerateTdp; 4864 ULONG ulEvvDerateTdc; 4865 ULONG ulBoardCoreTemp; 4866 ULONG ulMaxVddc; 4867 ULONG ulMinVddc; 4868 ULONG ulLoadLineSlop; 4869 ULONG ulLeakageTemp; 4870 ULONG ulLeakageVoltage; 4871 EFUSE_LINEAR_FUNC_PARAM sCACm; 4872 EFUSE_LINEAR_FUNC_PARAM sCACb; 4873 EFUSE_LOGISTIC_FUNC_PARAM sKt_b; 4874 EFUSE_LOGISTIC_FUNC_PARAM sKv_m; 4875 EFUSE_LOGISTIC_FUNC_PARAM sKv_b; 4876 USHORT usLkgEuseIndex; 4877 UCHAR ucLkgEfuseBitLSB; 4878 UCHAR ucLkgEfuseLength; 4879 ULONG ulLkgEncodeLn_MaxDivMin; 4880 ULONG ulLkgEncodeMax; 4881 ULONG ulLkgEncodeMin; 4882 ULONG ulEfuseLogisticAlpha; 4883 USHORT usPowerDpm0; 4884 USHORT usCurrentDpm0; 4885 USHORT usPowerDpm1; 4886 USHORT usCurrentDpm1; 4887 USHORT usPowerDpm2; 4888 USHORT usCurrentDpm2; 4889 USHORT usPowerDpm3; 4890 USHORT usCurrentDpm3; 4891 USHORT usPowerDpm4; 4892 USHORT usCurrentDpm4; 4893 USHORT usPowerDpm5; 4894 USHORT usCurrentDpm5; 4895 USHORT usPowerDpm6; 4896 USHORT usCurrentDpm6; 4897 USHORT usPowerDpm7; 4898 USHORT usCurrentDpm7; 4899 }ATOM_ASIC_PROFILING_INFO_V3_1; 4900 4901 4902 typedef struct _ATOM_ASIC_PROFILING_INFO_V3_2 4903 { 4904 ATOM_COMMON_TABLE_HEADER asHeader; 4905 ULONG ulEvvLkgFactor; 4906 ULONG ulBoardCoreTemp; 4907 ULONG ulMaxVddc; 4908 ULONG ulMinVddc; 4909 ULONG ulLoadLineSlop; 4910 ULONG ulLeakageTemp; 4911 ULONG ulLeakageVoltage; 4912 EFUSE_LINEAR_FUNC_PARAM sCACm; 4913 EFUSE_LINEAR_FUNC_PARAM sCACb; 4914 EFUSE_LOGISTIC_FUNC_PARAM sKt_b; 4915 EFUSE_LOGISTIC_FUNC_PARAM sKv_m; 4916 EFUSE_LOGISTIC_FUNC_PARAM sKv_b; 4917 USHORT usLkgEuseIndex; 4918 UCHAR ucLkgEfuseBitLSB; 4919 UCHAR ucLkgEfuseLength; 4920 ULONG ulLkgEncodeLn_MaxDivMin; 4921 ULONG ulLkgEncodeMax; 4922 ULONG ulLkgEncodeMin; 4923 ULONG ulEfuseLogisticAlpha; 4924 USHORT usPowerDpm0; 4925 USHORT usPowerDpm1; 4926 USHORT usPowerDpm2; 4927 USHORT usPowerDpm3; 4928 USHORT usPowerDpm4; 4929 USHORT usPowerDpm5; 4930 USHORT usPowerDpm6; 4931 USHORT usPowerDpm7; 4932 ULONG ulTdpDerateDPM0; 4933 ULONG ulTdpDerateDPM1; 4934 ULONG ulTdpDerateDPM2; 4935 ULONG ulTdpDerateDPM3; 4936 ULONG ulTdpDerateDPM4; 4937 ULONG ulTdpDerateDPM5; 4938 ULONG ulTdpDerateDPM6; 4939 ULONG ulTdpDerateDPM7; 4940 }ATOM_ASIC_PROFILING_INFO_V3_2; 4941 4942 4943 // for Tonga/Fiji speed EVV algorithm 4944 typedef struct _ATOM_ASIC_PROFILING_INFO_V3_3 4945 { 4946 ATOM_COMMON_TABLE_HEADER asHeader; 4947 ULONG ulEvvLkgFactor; 4948 ULONG ulBoardCoreTemp; 4949 ULONG ulMaxVddc; 4950 ULONG ulMinVddc; 4951 ULONG ulLoadLineSlop; 4952 ULONG ulLeakageTemp; 4953 ULONG ulLeakageVoltage; 4954 EFUSE_LINEAR_FUNC_PARAM sCACm; 4955 EFUSE_LINEAR_FUNC_PARAM sCACb; 4956 EFUSE_LOGISTIC_FUNC_PARAM sKt_b; 4957 EFUSE_LOGISTIC_FUNC_PARAM sKv_m; 4958 EFUSE_LOGISTIC_FUNC_PARAM sKv_b; 4959 USHORT usLkgEuseIndex; 4960 UCHAR ucLkgEfuseBitLSB; 4961 UCHAR ucLkgEfuseLength; 4962 ULONG ulLkgEncodeLn_MaxDivMin; 4963 ULONG ulLkgEncodeMax; 4964 ULONG ulLkgEncodeMin; 4965 ULONG ulEfuseLogisticAlpha; 4966 USHORT usPowerDpm0; 4967 USHORT usPowerDpm1; 4968 USHORT usPowerDpm2; 4969 USHORT usPowerDpm3; 4970 USHORT usPowerDpm4; 4971 USHORT usPowerDpm5; 4972 USHORT usPowerDpm6; 4973 USHORT usPowerDpm7; 4974 ULONG ulTdpDerateDPM0; 4975 ULONG ulTdpDerateDPM1; 4976 ULONG ulTdpDerateDPM2; 4977 ULONG ulTdpDerateDPM3; 4978 ULONG ulTdpDerateDPM4; 4979 ULONG ulTdpDerateDPM5; 4980 ULONG ulTdpDerateDPM6; 4981 ULONG ulTdpDerateDPM7; 4982 EFUSE_LINEAR_FUNC_PARAM sRoFuse; 4983 ULONG ulRoAlpha; 4984 ULONG ulRoBeta; 4985 ULONG ulRoGamma; 4986 ULONG ulRoEpsilon; 4987 ULONG ulATermRo; 4988 ULONG ulBTermRo; 4989 ULONG ulCTermRo; 4990 ULONG ulSclkMargin; 4991 ULONG ulFmaxPercent; 4992 ULONG ulCRPercent; 4993 ULONG ulSFmaxPercent; 4994 ULONG ulSCRPercent; 4995 ULONG ulSDCMargine; 4996 }ATOM_ASIC_PROFILING_INFO_V3_3; 4997 4998 // for Fiji speed EVV algorithm 4999 typedef struct _ATOM_ASIC_PROFILING_INFO_V3_4 5000 { 5001 ATOM_COMMON_TABLE_HEADER asHeader; 5002 ULONG ulEvvLkgFactor; 5003 ULONG ulBoardCoreTemp; 5004 ULONG ulMaxVddc; 5005 ULONG ulMinVddc; 5006 ULONG ulLoadLineSlop; 5007 ULONG ulLeakageTemp; 5008 ULONG ulLeakageVoltage; 5009 EFUSE_LINEAR_FUNC_PARAM sCACm; 5010 EFUSE_LINEAR_FUNC_PARAM sCACb; 5011 EFUSE_LOGISTIC_FUNC_PARAM sKt_b; 5012 EFUSE_LOGISTIC_FUNC_PARAM sKv_m; 5013 EFUSE_LOGISTIC_FUNC_PARAM sKv_b; 5014 USHORT usLkgEuseIndex; 5015 UCHAR ucLkgEfuseBitLSB; 5016 UCHAR ucLkgEfuseLength; 5017 ULONG ulLkgEncodeLn_MaxDivMin; 5018 ULONG ulLkgEncodeMax; 5019 ULONG ulLkgEncodeMin; 5020 ULONG ulEfuseLogisticAlpha; 5021 USHORT usPowerDpm0; 5022 USHORT usPowerDpm1; 5023 USHORT usPowerDpm2; 5024 USHORT usPowerDpm3; 5025 USHORT usPowerDpm4; 5026 USHORT usPowerDpm5; 5027 USHORT usPowerDpm6; 5028 USHORT usPowerDpm7; 5029 ULONG ulTdpDerateDPM0; 5030 ULONG ulTdpDerateDPM1; 5031 ULONG ulTdpDerateDPM2; 5032 ULONG ulTdpDerateDPM3; 5033 ULONG ulTdpDerateDPM4; 5034 ULONG ulTdpDerateDPM5; 5035 ULONG ulTdpDerateDPM6; 5036 ULONG ulTdpDerateDPM7; 5037 EFUSE_LINEAR_FUNC_PARAM sRoFuse; 5038 ULONG ulEvvDefaultVddc; 5039 ULONG ulEvvNoCalcVddc; 5040 USHORT usParamNegFlag; 5041 USHORT usSpeed_Model; 5042 ULONG ulSM_A0; 5043 ULONG ulSM_A1; 5044 ULONG ulSM_A2; 5045 ULONG ulSM_A3; 5046 ULONG ulSM_A4; 5047 ULONG ulSM_A5; 5048 ULONG ulSM_A6; 5049 ULONG ulSM_A7; 5050 UCHAR ucSM_A0_sign; 5051 UCHAR ucSM_A1_sign; 5052 UCHAR ucSM_A2_sign; 5053 UCHAR ucSM_A3_sign; 5054 UCHAR ucSM_A4_sign; 5055 UCHAR ucSM_A5_sign; 5056 UCHAR ucSM_A6_sign; 5057 UCHAR ucSM_A7_sign; 5058 ULONG ulMargin_RO_a; 5059 ULONG ulMargin_RO_b; 5060 ULONG ulMargin_RO_c; 5061 ULONG ulMargin_fixed; 5062 ULONG ulMargin_Fmax_mean; 5063 ULONG ulMargin_plat_mean; 5064 ULONG ulMargin_Fmax_sigma; 5065 ULONG ulMargin_plat_sigma; 5066 ULONG ulMargin_DC_sigma; 5067 ULONG ulReserved[8]; // Reserved for future ASIC 5068 }ATOM_ASIC_PROFILING_INFO_V3_4; 5069 5070 typedef struct _ATOM_POWER_SOURCE_OBJECT 5071 { 5072 UCHAR ucPwrSrcId; // Power source 5073 UCHAR ucPwrSensorType; // GPIO, I2C or none 5074 UCHAR ucPwrSensId; // if GPIO detect, it is GPIO id, if I2C detect, it is I2C id 5075 UCHAR ucPwrSensSlaveAddr; // Slave address if I2C detect 5076 UCHAR ucPwrSensRegIndex; // I2C register Index if I2C detect 5077 UCHAR ucPwrSensRegBitMask; // detect which bit is used if I2C detect 5078 UCHAR ucPwrSensActiveState; // high active or low active 5079 UCHAR ucReserve[3]; // reserve 5080 USHORT usSensPwr; // in unit of watt 5081 }ATOM_POWER_SOURCE_OBJECT; 5082 5083 typedef struct _ATOM_POWER_SOURCE_INFO 5084 { 5085 ATOM_COMMON_TABLE_HEADER asHeader; 5086 UCHAR asPwrbehave[16]; 5087 ATOM_POWER_SOURCE_OBJECT asPwrObj[1]; 5088 }ATOM_POWER_SOURCE_INFO; 5089 5090 5091 //Define ucPwrSrcId 5092 #define POWERSOURCE_PCIE_ID1 0x00 5093 #define POWERSOURCE_6PIN_CONNECTOR_ID1 0x01 5094 #define POWERSOURCE_8PIN_CONNECTOR_ID1 0x02 5095 #define POWERSOURCE_6PIN_CONNECTOR_ID2 0x04 5096 #define POWERSOURCE_8PIN_CONNECTOR_ID2 0x08 5097 5098 //define ucPwrSensorId 5099 #define POWER_SENSOR_ALWAYS 0x00 5100 #define POWER_SENSOR_GPIO 0x01 5101 #define POWER_SENSOR_I2C 0x02 5102 5103 typedef struct _ATOM_CLK_VOLT_CAPABILITY 5104 { 5105 ULONG ulVoltageIndex; // The Voltage Index indicated by FUSE, same voltage index shared with SCLK DPM fuse table 5106 ULONG ulMaximumSupportedCLK; // Maximum clock supported with specified voltage index, unit in 10kHz 5107 }ATOM_CLK_VOLT_CAPABILITY; 5108 5109 5110 typedef struct _ATOM_CLK_VOLT_CAPABILITY_V2 5111 { 5112 USHORT usVoltageLevel; // The real Voltage Level round up value in unit of mv, 5113 ULONG ulMaximumSupportedCLK; // Maximum clock supported with specified voltage index, unit in 10kHz 5114 }ATOM_CLK_VOLT_CAPABILITY_V2; 5115 5116 typedef struct _ATOM_AVAILABLE_SCLK_LIST 5117 { 5118 ULONG ulSupportedSCLK; // Maximum clock supported with specified voltage index, unit in 10kHz 5119 USHORT usVoltageIndex; // The Voltage Index indicated by FUSE for specified SCLK 5120 USHORT usVoltageID; // The Voltage ID indicated by FUSE for specified SCLK 5121 }ATOM_AVAILABLE_SCLK_LIST; 5122 5123 // ATOM_INTEGRATED_SYSTEM_INFO_V6 ulSystemConfig cap definition 5124 #define ATOM_IGP_INFO_V6_SYSTEM_CONFIG__PCIE_POWER_GATING_ENABLE 1 // refer to ulSystemConfig bit[0] 5125 5126 // this IntegrateSystemInfoTable is used for Liano/Ontario APU 5127 typedef struct _ATOM_INTEGRATED_SYSTEM_INFO_V6 5128 { 5129 ATOM_COMMON_TABLE_HEADER sHeader; 5130 ULONG ulBootUpEngineClock; 5131 ULONG ulDentistVCOFreq; 5132 ULONG ulBootUpUMAClock; 5133 ATOM_CLK_VOLT_CAPABILITY sDISPCLK_Voltage[4]; 5134 ULONG ulBootUpReqDisplayVector; 5135 ULONG ulOtherDisplayMisc; 5136 ULONG ulGPUCapInfo; 5137 ULONG ulSB_MMIO_Base_Addr; 5138 USHORT usRequestedPWMFreqInHz; 5139 UCHAR ucHtcTmpLmt; 5140 UCHAR ucHtcHystLmt; 5141 ULONG ulMinEngineClock; 5142 ULONG ulSystemConfig; 5143 ULONG ulCPUCapInfo; 5144 USHORT usNBP0Voltage; 5145 USHORT usNBP1Voltage; 5146 USHORT usBootUpNBVoltage; 5147 USHORT usExtDispConnInfoOffset; 5148 USHORT usPanelRefreshRateRange; 5149 UCHAR ucMemoryType; 5150 UCHAR ucUMAChannelNumber; 5151 ULONG ulCSR_M3_ARB_CNTL_DEFAULT[10]; 5152 ULONG ulCSR_M3_ARB_CNTL_UVD[10]; 5153 ULONG ulCSR_M3_ARB_CNTL_FS3D[10]; 5154 ATOM_AVAILABLE_SCLK_LIST sAvail_SCLK[5]; 5155 ULONG ulGMCRestoreResetTime; 5156 ULONG ulMinimumNClk; 5157 ULONG ulIdleNClk; 5158 ULONG ulDDR_DLL_PowerUpTime; 5159 ULONG ulDDR_PLL_PowerUpTime; 5160 USHORT usPCIEClkSSPercentage; 5161 USHORT usPCIEClkSSType; 5162 USHORT usLvdsSSPercentage; 5163 USHORT usLvdsSSpreadRateIn10Hz; 5164 USHORT usHDMISSPercentage; 5165 USHORT usHDMISSpreadRateIn10Hz; 5166 USHORT usDVISSPercentage; 5167 USHORT usDVISSpreadRateIn10Hz; 5168 ULONG SclkDpmBoostMargin; 5169 ULONG SclkDpmThrottleMargin; 5170 USHORT SclkDpmTdpLimitPG; 5171 USHORT SclkDpmTdpLimitBoost; 5172 ULONG ulBoostEngineCLock; 5173 UCHAR ulBoostVid_2bit; 5174 UCHAR EnableBoost; 5175 USHORT GnbTdpLimit; 5176 USHORT usMaxLVDSPclkFreqInSingleLink; 5177 UCHAR ucLvdsMisc; 5178 UCHAR ucLVDSReserved; 5179 ULONG ulReserved3[15]; 5180 ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO sExtDispConnInfo; 5181 }ATOM_INTEGRATED_SYSTEM_INFO_V6; 5182 5183 // ulGPUCapInfo 5184 #define INTEGRATED_SYSTEM_INFO_V6_GPUCAPINFO__TMDSHDMI_COHERENT_SINGLEPLL_MODE 0x01 5185 #define INTEGRATED_SYSTEM_INFO_V6_GPUCAPINFO__DISABLE_AUX_HW_MODE_DETECTION 0x08 5186 5187 //ucLVDSMisc: 5188 #define SYS_INFO_LVDSMISC__888_FPDI_MODE 0x01 5189 #define SYS_INFO_LVDSMISC__DL_CH_SWAP 0x02 5190 #define SYS_INFO_LVDSMISC__888_BPC 0x04 5191 #define SYS_INFO_LVDSMISC__OVERRIDE_EN 0x08 5192 #define SYS_INFO_LVDSMISC__BLON_ACTIVE_LOW 0x10 5193 // new since Trinity 5194 #define SYS_INFO_LVDSMISC__TRAVIS_LVDS_VOL_OVERRIDE_EN 0x20 5195 5196 // not used any more 5197 #define SYS_INFO_LVDSMISC__VSYNC_ACTIVE_LOW 0x04 5198 #define SYS_INFO_LVDSMISC__HSYNC_ACTIVE_LOW 0x08 5199 5200 /********************************************************************************************************************** 5201 ATOM_INTEGRATED_SYSTEM_INFO_V6 Description 5202 ulBootUpEngineClock: VBIOS bootup Engine clock frequency, in 10kHz unit. if it is equal 0, then VBIOS use pre-defined bootup engine clock 5203 ulDentistVCOFreq: Dentist VCO clock in 10kHz unit. 5204 ulBootUpUMAClock: System memory boot up clock frequency in 10Khz unit. 5205 sDISPCLK_Voltage: Report Display clock voltage requirement. 5206 5207 ulBootUpReqDisplayVector: VBIOS boot up display IDs, following are supported devices in Liano/Ontaio projects: 5208 ATOM_DEVICE_CRT1_SUPPORT 0x0001 5209 ATOM_DEVICE_CRT2_SUPPORT 0x0010 5210 ATOM_DEVICE_DFP1_SUPPORT 0x0008 5211 ATOM_DEVICE_DFP6_SUPPORT 0x0040 5212 ATOM_DEVICE_DFP2_SUPPORT 0x0080 5213 ATOM_DEVICE_DFP3_SUPPORT 0x0200 5214 ATOM_DEVICE_DFP4_SUPPORT 0x0400 5215 ATOM_DEVICE_DFP5_SUPPORT 0x0800 5216 ATOM_DEVICE_LCD1_SUPPORT 0x0002 5217 ulOtherDisplayMisc: Other display related flags, not defined yet. 5218 ulGPUCapInfo: bit[0]=0: TMDS/HDMI Coherent Mode use cascade PLL mode. 5219 =1: TMDS/HDMI Coherent Mode use signel PLL mode. 5220 bit[3]=0: Enable HW AUX mode detection logic 5221 =1: Disable HW AUX mode dettion logic 5222 ulSB_MMIO_Base_Addr: Physical Base address to SB MMIO space. Driver needs to initialize it for SMU usage. 5223 5224 usRequestedPWMFreqInHz: When it's set to 0x0 by SBIOS: the LCD BackLight is not controlled by GPU(SW). 5225 Any attempt to change BL using VBIOS function or enable VariBri from PP table is not effective since ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU==0; 5226 5227 When it's set to a non-zero frequency, the BackLight is controlled by GPU (SW) in one of two ways below: 5228 1. SW uses the GPU BL PWM output to control the BL, in chis case, this non-zero frequency determines what freq GPU should use; 5229 VBIOS will set up proper PWM frequency and ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU==1,as the result, 5230 Changing BL using VBIOS function is functional in both driver and non-driver present environment; 5231 and enabling VariBri under the driver environment from PP table is optional. 5232 5233 2. SW uses other means to control BL (like DPCD),this non-zero frequency serves as a flag only indicating 5234 that BL control from GPU is expected. 5235 VBIOS will NOT set up PWM frequency but make ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU==1 5236 Changing BL using VBIOS function could be functional in both driver and non-driver present environment,but 5237 it's per platform 5238 and enabling VariBri under the driver environment from PP table is optional. 5239 5240 ucHtcTmpLmt: Refer to D18F3x64 bit[22:16], HtcTmpLmt. 5241 Threshold on value to enter HTC_active state. 5242 ucHtcHystLmt: Refer to D18F3x64 bit[27:24], HtcHystLmt. 5243 To calculate threshold off value to exit HTC_active state, which is Threshold on vlaue minus ucHtcHystLmt. 5244 ulMinEngineClock: Minimum SCLK allowed in 10kHz unit. This is calculated based on WRCK Fuse settings. 5245 ulSystemConfig: Bit[0]=0: PCIE Power Gating Disabled 5246 =1: PCIE Power Gating Enabled 5247 Bit[1]=0: DDR-DLL shut-down feature disabled. 5248 1: DDR-DLL shut-down feature enabled. 5249 Bit[2]=0: DDR-PLL Power down feature disabled. 5250 1: DDR-PLL Power down feature enabled. 5251 ulCPUCapInfo: TBD 5252 usNBP0Voltage: VID for voltage on NB P0 State 5253 usNBP1Voltage: VID for voltage on NB P1 State 5254 usBootUpNBVoltage: Voltage Index of GNB voltage configured by SBIOS, which is suffcient to support VBIOS DISPCLK requirement. 5255 usExtDispConnInfoOffset: Offset to sExtDispConnInfo inside the structure 5256 usPanelRefreshRateRange: Bit vector for LCD supported refresh rate range. If DRR is requestd by the platform, at least two bits need to be set 5257 to indicate a range. 5258 SUPPORTED_LCD_REFRESHRATE_30Hz 0x0004 5259 SUPPORTED_LCD_REFRESHRATE_40Hz 0x0008 5260 SUPPORTED_LCD_REFRESHRATE_50Hz 0x0010 5261 SUPPORTED_LCD_REFRESHRATE_60Hz 0x0020 5262 ucMemoryType: [3:0]=1:DDR1;=2:DDR2;=3:DDR3.[7:4] is reserved. 5263 ucUMAChannelNumber: System memory channel numbers. 5264 ulCSR_M3_ARB_CNTL_DEFAULT[10]: Arrays with values for CSR M3 arbiter for default 5265 ulCSR_M3_ARB_CNTL_UVD[10]: Arrays with values for CSR M3 arbiter for UVD playback. 5266 ulCSR_M3_ARB_CNTL_FS3D[10]: Arrays with values for CSR M3 arbiter for Full Screen 3D applications. 5267 sAvail_SCLK[5]: Arrays to provide availabe list of SLCK and corresponding voltage, order from low to high 5268 ulGMCRestoreResetTime: GMC power restore and GMC reset time to calculate data reconnection latency. Unit in ns. 5269 ulMinimumNClk: Minimum NCLK speed among all NB-Pstates to calcualte data reconnection latency. Unit in 10kHz. 5270 ulIdleNClk: NCLK speed while memory runs in self-refresh state. Unit in 10kHz. 5271 ulDDR_DLL_PowerUpTime: DDR PHY DLL power up time. Unit in ns. 5272 ulDDR_PLL_PowerUpTime: DDR PHY PLL power up time. Unit in ns. 5273 usPCIEClkSSPercentage: PCIE Clock Spred Spectrum Percentage in unit 0.01%; 100 mean 1%. 5274 usPCIEClkSSType: PCIE Clock Spred Spectrum Type. 0 for Down spread(default); 1 for Center spread. 5275 usLvdsSSPercentage: LVDS panel ( not include eDP ) Spread Spectrum Percentage in unit of 0.01%, =0, use VBIOS default setting. 5276 usLvdsSSpreadRateIn10Hz: LVDS panel ( not include eDP ) Spread Spectrum frequency in unit of 10Hz, =0, use VBIOS default setting. 5277 usHDMISSPercentage: HDMI Spread Spectrum Percentage in unit 0.01%; 100 mean 1%, =0, use VBIOS default setting. 5278 usHDMISSpreadRateIn10Hz: HDMI Spread Spectrum frequency in unit of 10Hz, =0, use VBIOS default setting. 5279 usDVISSPercentage: DVI Spread Spectrum Percentage in unit 0.01%; 100 mean 1%, =0, use VBIOS default setting. 5280 usDVISSpreadRateIn10Hz: DVI Spread Spectrum frequency in unit of 10Hz, =0, use VBIOS default setting. 5281 usMaxLVDSPclkFreqInSingleLink: Max pixel clock LVDS panel single link, if=0 means VBIOS use default threhold, right now it is 85Mhz 5282 ucLVDSMisc: [bit0] LVDS 888bit panel mode =0: LVDS 888 panel in LDI mode, =1: LVDS 888 panel in FPDI mode 5283 [bit1] LVDS panel lower and upper link mapping =0: lower link and upper link not swap, =1: lower link and upper link are swapped 5284 [bit2] LVDS 888bit per color mode =0: 666 bit per color =1:888 bit per color 5285 [bit3] LVDS parameter override enable =0: ucLvdsMisc parameter are not used =1: ucLvdsMisc parameter should be used 5286 [bit4] Polarity of signal sent to digital BLON output pin. =0: not inverted(active high) =1: inverted ( active low ) 5287 **********************************************************************************************************************/ 5288 5289 // this Table is used for Liano/Ontario APU 5290 typedef struct _ATOM_FUSION_SYSTEM_INFO_V1 5291 { 5292 ATOM_INTEGRATED_SYSTEM_INFO_V6 sIntegratedSysInfo; 5293 ULONG ulPowerplayTable[128]; 5294 }ATOM_FUSION_SYSTEM_INFO_V1; 5295 5296 5297 typedef struct _ATOM_TDP_CONFIG_BITS 5298 { 5299 #if ATOM_BIG_ENDIAN 5300 ULONG uReserved:2; 5301 ULONG uTDP_Value:14; // Original TDP value in tens of milli watts 5302 ULONG uCTDP_Value:14; // Override value in tens of milli watts 5303 ULONG uCTDP_Enable:2; // = (uCTDP_Value > uTDP_Value? 2: (uCTDP_Value < uTDP_Value)) 5304 #else 5305 ULONG uCTDP_Enable:2; // = (uCTDP_Value > uTDP_Value? 2: (uCTDP_Value < uTDP_Value)) 5306 ULONG uCTDP_Value:14; // Override value in tens of milli watts 5307 ULONG uTDP_Value:14; // Original TDP value in tens of milli watts 5308 ULONG uReserved:2; 5309 #endif 5310 }ATOM_TDP_CONFIG_BITS; 5311 5312 typedef union _ATOM_TDP_CONFIG 5313 { 5314 ATOM_TDP_CONFIG_BITS TDP_config; 5315 ULONG TDP_config_all; 5316 }ATOM_TDP_CONFIG; 5317 5318 /********************************************************************************************************************** 5319 ATOM_FUSION_SYSTEM_INFO_V1 Description 5320 sIntegratedSysInfo: refer to ATOM_INTEGRATED_SYSTEM_INFO_V6 definition. 5321 ulPowerplayTable[128]: This 512 bytes memory is used to save ATOM_PPLIB_POWERPLAYTABLE3, starting form ulPowerplayTable[0] 5322 **********************************************************************************************************************/ 5323 5324 // this IntegrateSystemInfoTable is used for Trinity APU 5325 typedef struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_7 5326 { 5327 ATOM_COMMON_TABLE_HEADER sHeader; 5328 ULONG ulBootUpEngineClock; 5329 ULONG ulDentistVCOFreq; 5330 ULONG ulBootUpUMAClock; 5331 ATOM_CLK_VOLT_CAPABILITY sDISPCLK_Voltage[4]; 5332 ULONG ulBootUpReqDisplayVector; 5333 ULONG ulOtherDisplayMisc; 5334 ULONG ulGPUCapInfo; 5335 ULONG ulSB_MMIO_Base_Addr; 5336 USHORT usRequestedPWMFreqInHz; 5337 UCHAR ucHtcTmpLmt; 5338 UCHAR ucHtcHystLmt; 5339 ULONG ulMinEngineClock; 5340 ULONG ulSystemConfig; 5341 ULONG ulCPUCapInfo; 5342 USHORT usNBP0Voltage; 5343 USHORT usNBP1Voltage; 5344 USHORT usBootUpNBVoltage; 5345 USHORT usExtDispConnInfoOffset; 5346 USHORT usPanelRefreshRateRange; 5347 UCHAR ucMemoryType; 5348 UCHAR ucUMAChannelNumber; 5349 UCHAR strVBIOSMsg[40]; 5350 ATOM_TDP_CONFIG asTdpConfig; 5351 ULONG ulReserved[19]; 5352 ATOM_AVAILABLE_SCLK_LIST sAvail_SCLK[5]; 5353 ULONG ulGMCRestoreResetTime; 5354 ULONG ulMinimumNClk; 5355 ULONG ulIdleNClk; 5356 ULONG ulDDR_DLL_PowerUpTime; 5357 ULONG ulDDR_PLL_PowerUpTime; 5358 USHORT usPCIEClkSSPercentage; 5359 USHORT usPCIEClkSSType; 5360 USHORT usLvdsSSPercentage; 5361 USHORT usLvdsSSpreadRateIn10Hz; 5362 USHORT usHDMISSPercentage; 5363 USHORT usHDMISSpreadRateIn10Hz; 5364 USHORT usDVISSPercentage; 5365 USHORT usDVISSpreadRateIn10Hz; 5366 ULONG SclkDpmBoostMargin; 5367 ULONG SclkDpmThrottleMargin; 5368 USHORT SclkDpmTdpLimitPG; 5369 USHORT SclkDpmTdpLimitBoost; 5370 ULONG ulBoostEngineCLock; 5371 UCHAR ulBoostVid_2bit; 5372 UCHAR EnableBoost; 5373 USHORT GnbTdpLimit; 5374 USHORT usMaxLVDSPclkFreqInSingleLink; 5375 UCHAR ucLvdsMisc; 5376 UCHAR ucTravisLVDSVolAdjust; 5377 UCHAR ucLVDSPwrOnSeqDIGONtoDE_in4Ms; 5378 UCHAR ucLVDSPwrOnSeqDEtoVARY_BL_in4Ms; 5379 UCHAR ucLVDSPwrOffSeqVARY_BLtoDE_in4Ms; 5380 UCHAR ucLVDSPwrOffSeqDEtoDIGON_in4Ms; 5381 UCHAR ucLVDSOffToOnDelay_in4Ms; 5382 UCHAR ucLVDSPwrOnSeqVARY_BLtoBLON_in4Ms; 5383 UCHAR ucLVDSPwrOffSeqBLONtoVARY_BL_in4Ms; 5384 UCHAR ucMinAllowedBL_Level; 5385 ULONG ulLCDBitDepthControlVal; 5386 ULONG ulNbpStateMemclkFreq[4]; 5387 USHORT usNBP2Voltage; 5388 USHORT usNBP3Voltage; 5389 ULONG ulNbpStateNClkFreq[4]; 5390 UCHAR ucNBDPMEnable; 5391 UCHAR ucReserved[3]; 5392 UCHAR ucDPMState0VclkFid; 5393 UCHAR ucDPMState0DclkFid; 5394 UCHAR ucDPMState1VclkFid; 5395 UCHAR ucDPMState1DclkFid; 5396 UCHAR ucDPMState2VclkFid; 5397 UCHAR ucDPMState2DclkFid; 5398 UCHAR ucDPMState3VclkFid; 5399 UCHAR ucDPMState3DclkFid; 5400 ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO sExtDispConnInfo; 5401 }ATOM_INTEGRATED_SYSTEM_INFO_V1_7; 5402 5403 // ulOtherDisplayMisc 5404 #define INTEGRATED_SYSTEM_INFO__GET_EDID_CALLBACK_FUNC_SUPPORT 0x01 5405 #define INTEGRATED_SYSTEM_INFO__GET_BOOTUP_DISPLAY_CALLBACK_FUNC_SUPPORT 0x02 5406 #define INTEGRATED_SYSTEM_INFO__GET_EXPANSION_CALLBACK_FUNC_SUPPORT 0x04 5407 #define INTEGRATED_SYSTEM_INFO__FAST_BOOT_SUPPORT 0x08 5408 5409 // ulGPUCapInfo 5410 #define SYS_INFO_GPUCAPS__TMDSHDMI_COHERENT_SINGLEPLL_MODE 0x01 5411 #define SYS_INFO_GPUCAPS__DP_SINGLEPLL_MODE 0x02 5412 #define SYS_INFO_GPUCAPS__DISABLE_AUX_MODE_DETECT 0x08 5413 #define SYS_INFO_GPUCAPS__ENABEL_DFS_BYPASS 0x10 5414 //ulGPUCapInfo[16]=1 indicate SMC firmware is able to support GNB fast resume function, so that driver can call SMC to program most of GNB register during resuming, from ML 5415 #define SYS_INFO_GPUCAPS__GNB_FAST_RESUME_CAPABLE 0x00010000 5416 5417 //ulGPUCapInfo[17]=1 indicate battery boost feature is enable, from ML 5418 #define SYS_INFO_GPUCAPS__BATTERY_BOOST_ENABLE 0x00020000 5419 5420 /********************************************************************************************************************** 5421 ATOM_INTEGRATED_SYSTEM_INFO_V1_7 Description 5422 ulBootUpEngineClock: VBIOS bootup Engine clock frequency, in 10kHz unit. if it is equal 0, then VBIOS use pre-defined bootup engine clock 5423 ulDentistVCOFreq: Dentist VCO clock in 10kHz unit. 5424 ulBootUpUMAClock: System memory boot up clock frequency in 10Khz unit. 5425 sDISPCLK_Voltage: Report Display clock voltage requirement. 5426 5427 ulBootUpReqDisplayVector: VBIOS boot up display IDs, following are supported devices in Trinity projects: 5428 ATOM_DEVICE_CRT1_SUPPORT 0x0001 5429 ATOM_DEVICE_DFP1_SUPPORT 0x0008 5430 ATOM_DEVICE_DFP6_SUPPORT 0x0040 5431 ATOM_DEVICE_DFP2_SUPPORT 0x0080 5432 ATOM_DEVICE_DFP3_SUPPORT 0x0200 5433 ATOM_DEVICE_DFP4_SUPPORT 0x0400 5434 ATOM_DEVICE_DFP5_SUPPORT 0x0800 5435 ATOM_DEVICE_LCD1_SUPPORT 0x0002 5436 ulOtherDisplayMisc: bit[0]=0: INT15 callback function Get LCD EDID ( ax=4e08, bl=1b ) is not supported by SBIOS. 5437 =1: INT15 callback function Get LCD EDID ( ax=4e08, bl=1b ) is supported by SBIOS. 5438 bit[1]=0: INT15 callback function Get boot display( ax=4e08, bl=01h) is not supported by SBIOS 5439 =1: INT15 callback function Get boot display( ax=4e08, bl=01h) is supported by SBIOS 5440 bit[2]=0: INT15 callback function Get panel Expansion ( ax=4e08, bl=02h) is not supported by SBIOS 5441 =1: INT15 callback function Get panel Expansion ( ax=4e08, bl=02h) is supported by SBIOS 5442 bit[3]=0: VBIOS fast boot is disable 5443 =1: VBIOS fast boot is enable. ( VBIOS skip display device detection in every set mode if LCD panel is connect and LID is open) 5444 ulGPUCapInfo: bit[0]=0: TMDS/HDMI Coherent Mode use cascade PLL mode. 5445 =1: TMDS/HDMI Coherent Mode use signel PLL mode. 5446 bit[1]=0: DP mode use cascade PLL mode ( New for Trinity ) 5447 =1: DP mode use single PLL mode 5448 bit[3]=0: Enable AUX HW mode detection logic 5449 =1: Disable AUX HW mode detection logic 5450 5451 ulSB_MMIO_Base_Addr: Physical Base address to SB MMIO space. Driver needs to initialize it for SMU usage. 5452 5453 usRequestedPWMFreqInHz: When it's set to 0x0 by SBIOS: the LCD BackLight is not controlled by GPU(SW). 5454 Any attempt to change BL using VBIOS function or enable VariBri from PP table is not effective since ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU==0; 5455 5456 When it's set to a non-zero frequency, the BackLight is controlled by GPU (SW) in one of two ways below: 5457 1. SW uses the GPU BL PWM output to control the BL, in chis case, this non-zero frequency determines what freq GPU should use; 5458 VBIOS will set up proper PWM frequency and ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU==1,as the result, 5459 Changing BL using VBIOS function is functional in both driver and non-driver present environment; 5460 and enabling VariBri under the driver environment from PP table is optional. 5461 5462 2. SW uses other means to control BL (like DPCD),this non-zero frequency serves as a flag only indicating 5463 that BL control from GPU is expected. 5464 VBIOS will NOT set up PWM frequency but make ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU==1 5465 Changing BL using VBIOS function could be functional in both driver and non-driver present environment,but 5466 it's per platform 5467 and enabling VariBri under the driver environment from PP table is optional. 5468 5469 ucHtcTmpLmt: Refer to D18F3x64 bit[22:16], HtcTmpLmt. 5470 Threshold on value to enter HTC_active state. 5471 ucHtcHystLmt: Refer to D18F3x64 bit[27:24], HtcHystLmt. 5472 To calculate threshold off value to exit HTC_active state, which is Threshold on vlaue minus ucHtcHystLmt. 5473 ulMinEngineClock: Minimum SCLK allowed in 10kHz unit. This is calculated based on WRCK Fuse settings. 5474 ulSystemConfig: Bit[0]=0: PCIE Power Gating Disabled 5475 =1: PCIE Power Gating Enabled 5476 Bit[1]=0: DDR-DLL shut-down feature disabled. 5477 1: DDR-DLL shut-down feature enabled. 5478 Bit[2]=0: DDR-PLL Power down feature disabled. 5479 1: DDR-PLL Power down feature enabled. 5480 ulCPUCapInfo: TBD 5481 usNBP0Voltage: VID for voltage on NB P0 State 5482 usNBP1Voltage: VID for voltage on NB P1 State 5483 usNBP2Voltage: VID for voltage on NB P2 State 5484 usNBP3Voltage: VID for voltage on NB P3 State 5485 usBootUpNBVoltage: Voltage Index of GNB voltage configured by SBIOS, which is suffcient to support VBIOS DISPCLK requirement. 5486 usExtDispConnInfoOffset: Offset to sExtDispConnInfo inside the structure 5487 usPanelRefreshRateRange: Bit vector for LCD supported refresh rate range. If DRR is requestd by the platform, at least two bits need to be set 5488 to indicate a range. 5489 SUPPORTED_LCD_REFRESHRATE_30Hz 0x0004 5490 SUPPORTED_LCD_REFRESHRATE_40Hz 0x0008 5491 SUPPORTED_LCD_REFRESHRATE_50Hz 0x0010 5492 SUPPORTED_LCD_REFRESHRATE_60Hz 0x0020 5493 ucMemoryType: [3:0]=1:DDR1;=2:DDR2;=3:DDR3.[7:4] is reserved. 5494 ucUMAChannelNumber: System memory channel numbers. 5495 ulCSR_M3_ARB_CNTL_DEFAULT[10]: Arrays with values for CSR M3 arbiter for default 5496 ulCSR_M3_ARB_CNTL_UVD[10]: Arrays with values for CSR M3 arbiter for UVD playback. 5497 ulCSR_M3_ARB_CNTL_FS3D[10]: Arrays with values for CSR M3 arbiter for Full Screen 3D applications. 5498 sAvail_SCLK[5]: Arrays to provide availabe list of SLCK and corresponding voltage, order from low to high 5499 ulGMCRestoreResetTime: GMC power restore and GMC reset time to calculate data reconnection latency. Unit in ns. 5500 ulMinimumNClk: Minimum NCLK speed among all NB-Pstates to calcualte data reconnection latency. Unit in 10kHz. 5501 ulIdleNClk: NCLK speed while memory runs in self-refresh state. Unit in 10kHz. 5502 ulDDR_DLL_PowerUpTime: DDR PHY DLL power up time. Unit in ns. 5503 ulDDR_PLL_PowerUpTime: DDR PHY PLL power up time. Unit in ns. 5504 usPCIEClkSSPercentage: PCIE Clock Spread Spectrum Percentage in unit 0.01%; 100 mean 1%. 5505 usPCIEClkSSType: PCIE Clock Spread Spectrum Type. 0 for Down spread(default); 1 for Center spread. 5506 usLvdsSSPercentage: LVDS panel ( not include eDP ) Spread Spectrum Percentage in unit of 0.01%, =0, use VBIOS default setting. 5507 usLvdsSSpreadRateIn10Hz: LVDS panel ( not include eDP ) Spread Spectrum frequency in unit of 10Hz, =0, use VBIOS default setting. 5508 usHDMISSPercentage: HDMI Spread Spectrum Percentage in unit 0.01%; 100 mean 1%, =0, use VBIOS default setting. 5509 usHDMISSpreadRateIn10Hz: HDMI Spread Spectrum frequency in unit of 10Hz, =0, use VBIOS default setting. 5510 usDVISSPercentage: DVI Spread Spectrum Percentage in unit 0.01%; 100 mean 1%, =0, use VBIOS default setting. 5511 usDVISSpreadRateIn10Hz: DVI Spread Spectrum frequency in unit of 10Hz, =0, use VBIOS default setting. 5512 usMaxLVDSPclkFreqInSingleLink: Max pixel clock LVDS panel single link, if=0 means VBIOS use default threhold, right now it is 85Mhz 5513 ucLVDSMisc: [bit0] LVDS 888bit panel mode =0: LVDS 888 panel in LDI mode, =1: LVDS 888 panel in FPDI mode 5514 [bit1] LVDS panel lower and upper link mapping =0: lower link and upper link not swap, =1: lower link and upper link are swapped 5515 [bit2] LVDS 888bit per color mode =0: 666 bit per color =1:888 bit per color 5516 [bit3] LVDS parameter override enable =0: ucLvdsMisc parameter are not used =1: ucLvdsMisc parameter should be used 5517 [bit4] Polarity of signal sent to digital BLON output pin. =0: not inverted(active high) =1: inverted ( active low ) 5518 [bit5] Travid LVDS output voltage override enable, when =1, use ucTravisLVDSVolAdjust value to overwrite Traivs register LVDS_CTRL_4 5519 ucTravisLVDSVolAdjust When ucLVDSMisc[5]=1,it means platform SBIOS want to overwrite TravisLVDSVoltage. Then VBIOS will use ucTravisLVDSVolAdjust 5520 value to program Travis register LVDS_CTRL_4 5521 ucLVDSPwrOnSeqDIGONtoDE_in4Ms: LVDS power up sequence time in unit of 4ms, time delay from DIGON signal active to data enable signal active( DE ). 5522 =0 mean use VBIOS default which is 8 ( 32ms ). The LVDS power up sequence is as following: DIGON->DE->VARY_BL->BLON. 5523 This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable. 5524 ucLVDSPwrOnDEtoVARY_BL_in4Ms: LVDS power up sequence time in unit of 4ms., time delay from DE( data enable ) active to Vary Brightness enable signal active( VARY_BL ). 5525 =0 mean use VBIOS default which is 90 ( 360ms ). The LVDS power up sequence is as following: DIGON->DE->VARY_BL->BLON. 5526 This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable. 5527 5528 ucLVDSPwrOffVARY_BLtoDE_in4Ms: LVDS power down sequence time in unit of 4ms, time delay from data enable ( DE ) signal off to LCDVCC (DIGON) off. 5529 =0 mean use VBIOS default delay which is 8 ( 32ms ). The LVDS power down sequence is as following: BLON->VARY_BL->DE->DIGON 5530 This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable. 5531 5532 ucLVDSPwrOffDEtoDIGON_in4Ms: LVDS power down sequence time in unit of 4ms, time delay from vary brightness enable signal( VARY_BL) off to data enable ( DE ) signal off. 5533 =0 mean use VBIOS default which is 90 ( 360ms ). The LVDS power down sequence is as following: BLON->VARY_BL->DE->DIGON 5534 This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable. 5535 5536 ucLVDSOffToOnDelay_in4Ms: LVDS power down sequence time in unit of 4ms. Time delay from DIGON signal off to DIGON signal active. 5537 =0 means to use VBIOS default delay which is 125 ( 500ms ). 5538 This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable. 5539 5540 ucLVDSPwrOnSeqVARY_BLtoBLON_in4Ms: 5541 LVDS power up sequence time in unit of 4ms. Time delay from VARY_BL signal on to DLON signal active. 5542 =0 means to use VBIOS default delay which is 0 ( 0ms ). 5543 This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable. 5544 5545 ucLVDSPwrOffSeqBLONtoVARY_BL_in4Ms: 5546 LVDS power down sequence time in unit of 4ms. Time delay from BLON signal off to VARY_BL signal off. 5547 =0 means to use VBIOS default delay which is 0 ( 0ms ). 5548 This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable. 5549 5550 ucMinAllowedBL_Level: Lowest LCD backlight PWM level. This is customer platform specific parameters. By default it is 0. 5551 5552 ulNbpStateMemclkFreq[4]: system memory clock frequncey in unit of 10Khz in different NB pstate. 5553 5554 **********************************************************************************************************************/ 5555 5556 // this IntegrateSystemInfoTable is used for Kaveri & Kabini APU 5557 typedef struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_8 5558 { 5559 ATOM_COMMON_TABLE_HEADER sHeader; 5560 ULONG ulBootUpEngineClock; 5561 ULONG ulDentistVCOFreq; 5562 ULONG ulBootUpUMAClock; 5563 ATOM_CLK_VOLT_CAPABILITY sDISPCLK_Voltage[4]; 5564 ULONG ulBootUpReqDisplayVector; 5565 ULONG ulVBIOSMisc; 5566 ULONG ulGPUCapInfo; 5567 ULONG ulDISP_CLK2Freq; 5568 USHORT usRequestedPWMFreqInHz; 5569 UCHAR ucHtcTmpLmt; 5570 UCHAR ucHtcHystLmt; 5571 ULONG ulReserved2; 5572 ULONG ulSystemConfig; 5573 ULONG ulCPUCapInfo; 5574 ULONG ulReserved3; 5575 USHORT usGPUReservedSysMemSize; 5576 USHORT usExtDispConnInfoOffset; 5577 USHORT usPanelRefreshRateRange; 5578 UCHAR ucMemoryType; 5579 UCHAR ucUMAChannelNumber; 5580 UCHAR strVBIOSMsg[40]; 5581 ATOM_TDP_CONFIG asTdpConfig; 5582 ULONG ulReserved[19]; 5583 ATOM_AVAILABLE_SCLK_LIST sAvail_SCLK[5]; 5584 ULONG ulGMCRestoreResetTime; 5585 ULONG ulReserved4; 5586 ULONG ulIdleNClk; 5587 ULONG ulDDR_DLL_PowerUpTime; 5588 ULONG ulDDR_PLL_PowerUpTime; 5589 USHORT usPCIEClkSSPercentage; 5590 USHORT usPCIEClkSSType; 5591 USHORT usLvdsSSPercentage; 5592 USHORT usLvdsSSpreadRateIn10Hz; 5593 USHORT usHDMISSPercentage; 5594 USHORT usHDMISSpreadRateIn10Hz; 5595 USHORT usDVISSPercentage; 5596 USHORT usDVISSpreadRateIn10Hz; 5597 ULONG ulGPUReservedSysMemBaseAddrLo; 5598 ULONG ulGPUReservedSysMemBaseAddrHi; 5599 ATOM_CLK_VOLT_CAPABILITY s5thDISPCLK_Voltage; 5600 ULONG ulReserved5; 5601 USHORT usMaxLVDSPclkFreqInSingleLink; 5602 UCHAR ucLvdsMisc; 5603 UCHAR ucTravisLVDSVolAdjust; 5604 UCHAR ucLVDSPwrOnSeqDIGONtoDE_in4Ms; 5605 UCHAR ucLVDSPwrOnSeqDEtoVARY_BL_in4Ms; 5606 UCHAR ucLVDSPwrOffSeqVARY_BLtoDE_in4Ms; 5607 UCHAR ucLVDSPwrOffSeqDEtoDIGON_in4Ms; 5608 UCHAR ucLVDSOffToOnDelay_in4Ms; 5609 UCHAR ucLVDSPwrOnSeqVARY_BLtoBLON_in4Ms; 5610 UCHAR ucLVDSPwrOffSeqBLONtoVARY_BL_in4Ms; 5611 UCHAR ucMinAllowedBL_Level; 5612 ULONG ulLCDBitDepthControlVal; 5613 ULONG ulNbpStateMemclkFreq[4]; 5614 ULONG ulPSPVersion; 5615 ULONG ulNbpStateNClkFreq[4]; 5616 USHORT usNBPStateVoltage[4]; 5617 USHORT usBootUpNBVoltage; 5618 USHORT usReserved2; 5619 ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO sExtDispConnInfo; 5620 }ATOM_INTEGRATED_SYSTEM_INFO_V1_8; 5621 5622 /********************************************************************************************************************** 5623 ATOM_INTEGRATED_SYSTEM_INFO_V1_8 Description 5624 ulBootUpEngineClock: VBIOS bootup Engine clock frequency, in 10kHz unit. if it is equal 0, then VBIOS use pre-defined bootup engine clock 5625 ulDentistVCOFreq: Dentist VCO clock in 10kHz unit. 5626 ulBootUpUMAClock: System memory boot up clock frequency in 10Khz unit. 5627 sDISPCLK_Voltage: Report Display clock frequency requirement on GNB voltage(up to 4 voltage levels). 5628 5629 ulBootUpReqDisplayVector: VBIOS boot up display IDs, following are supported devices in Trinity projects: 5630 ATOM_DEVICE_CRT1_SUPPORT 0x0001 5631 ATOM_DEVICE_DFP1_SUPPORT 0x0008 5632 ATOM_DEVICE_DFP6_SUPPORT 0x0040 5633 ATOM_DEVICE_DFP2_SUPPORT 0x0080 5634 ATOM_DEVICE_DFP3_SUPPORT 0x0200 5635 ATOM_DEVICE_DFP4_SUPPORT 0x0400 5636 ATOM_DEVICE_DFP5_SUPPORT 0x0800 5637 ATOM_DEVICE_LCD1_SUPPORT 0x0002 5638 5639 ulVBIOSMisc: Miscellenous flags for VBIOS requirement and interface 5640 bit[0]=0: INT15 callback function Get LCD EDID ( ax=4e08, bl=1b ) is not supported by SBIOS. 5641 =1: INT15 callback function Get LCD EDID ( ax=4e08, bl=1b ) is supported by SBIOS. 5642 bit[1]=0: INT15 callback function Get boot display( ax=4e08, bl=01h) is not supported by SBIOS 5643 =1: INT15 callback function Get boot display( ax=4e08, bl=01h) is supported by SBIOS 5644 bit[2]=0: INT15 callback function Get panel Expansion ( ax=4e08, bl=02h) is not supported by SBIOS 5645 =1: INT15 callback function Get panel Expansion ( ax=4e08, bl=02h) is supported by SBIOS 5646 bit[3]=0: VBIOS fast boot is disable 5647 =1: VBIOS fast boot is enable. ( VBIOS skip display device detection in every set mode if LCD panel is connect and LID is open) 5648 5649 ulGPUCapInfo: bit[0~2]= Reserved 5650 bit[3]=0: Enable AUX HW mode detection logic 5651 =1: Disable AUX HW mode detection logic 5652 bit[4]=0: Disable DFS bypass feature 5653 =1: Enable DFS bypass feature 5654 5655 usRequestedPWMFreqInHz: When it's set to 0x0 by SBIOS: the LCD BackLight is not controlled by GPU(SW). 5656 Any attempt to change BL using VBIOS function or enable VariBri from PP table is not effective since ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU==0; 5657 5658 When it's set to a non-zero frequency, the BackLight is controlled by GPU (SW) in one of two ways below: 5659 1. SW uses the GPU BL PWM output to control the BL, in chis case, this non-zero frequency determines what freq GPU should use; 5660 VBIOS will set up proper PWM frequency and ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU==1,as the result, 5661 Changing BL using VBIOS function is functional in both driver and non-driver present environment; 5662 and enabling VariBri under the driver environment from PP table is optional. 5663 5664 2. SW uses other means to control BL (like DPCD),this non-zero frequency serves as a flag only indicating 5665 that BL control from GPU is expected. 5666 VBIOS will NOT set up PWM frequency but make ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU==1 5667 Changing BL using VBIOS function could be functional in both driver and non-driver present environment,but 5668 it's per platform 5669 and enabling VariBri under the driver environment from PP table is optional. 5670 5671 ucHtcTmpLmt: Refer to D18F3x64 bit[22:16], HtcTmpLmt. Threshold on value to enter HTC_active state. 5672 ucHtcHystLmt: Refer to D18F3x64 bit[27:24], HtcHystLmt. 5673 To calculate threshold off value to exit HTC_active state, which is Threshold on vlaue minus ucHtcHystLmt. 5674 5675 ulSystemConfig: Bit[0]=0: PCIE Power Gating Disabled 5676 =1: PCIE Power Gating Enabled 5677 Bit[1]=0: DDR-DLL shut-down feature disabled. 5678 1: DDR-DLL shut-down feature enabled. 5679 Bit[2]=0: DDR-PLL Power down feature disabled. 5680 1: DDR-PLL Power down feature enabled. 5681 Bit[3]=0: GNB DPM is disabled 5682 =1: GNB DPM is enabled 5683 ulCPUCapInfo: TBD 5684 5685 usExtDispConnInfoOffset: Offset to sExtDispConnInfo inside the structure 5686 usPanelRefreshRateRange: Bit vector for LCD supported refresh rate range. If DRR is requestd by the platform, at least two bits need to be set 5687 to indicate a range. 5688 SUPPORTED_LCD_REFRESHRATE_30Hz 0x0004 5689 SUPPORTED_LCD_REFRESHRATE_40Hz 0x0008 5690 SUPPORTED_LCD_REFRESHRATE_50Hz 0x0010 5691 SUPPORTED_LCD_REFRESHRATE_60Hz 0x0020 5692 5693 ucMemoryType: [3:0]=1:DDR1;=2:DDR2;=3:DDR3;=5:GDDR5; [7:4] is reserved. 5694 ucUMAChannelNumber: System memory channel numbers. 5695 5696 strVBIOSMsg[40]: VBIOS boot up customized message string 5697 5698 sAvail_SCLK[5]: Arrays to provide availabe list of SLCK and corresponding voltage, order from low to high 5699 5700 ulGMCRestoreResetTime: GMC power restore and GMC reset time to calculate data reconnection latency. Unit in ns. 5701 ulIdleNClk: NCLK speed while memory runs in self-refresh state, used to calculate self-refresh latency. Unit in 10kHz. 5702 ulDDR_DLL_PowerUpTime: DDR PHY DLL power up time. Unit in ns. 5703 ulDDR_PLL_PowerUpTime: DDR PHY PLL power up time. Unit in ns. 5704 5705 usPCIEClkSSPercentage: PCIE Clock Spread Spectrum Percentage in unit 0.01%; 100 mean 1%. 5706 usPCIEClkSSType: PCIE Clock Spread Spectrum Type. 0 for Down spread(default); 1 for Center spread. 5707 usLvdsSSPercentage: LVDS panel ( not include eDP ) Spread Spectrum Percentage in unit of 0.01%, =0, use VBIOS default setting. 5708 usLvdsSSpreadRateIn10Hz: LVDS panel ( not include eDP ) Spread Spectrum frequency in unit of 10Hz, =0, use VBIOS default setting. 5709 usHDMISSPercentage: HDMI Spread Spectrum Percentage in unit 0.01%; 100 mean 1%, =0, use VBIOS default setting. 5710 usHDMISSpreadRateIn10Hz: HDMI Spread Spectrum frequency in unit of 10Hz, =0, use VBIOS default setting. 5711 usDVISSPercentage: DVI Spread Spectrum Percentage in unit 0.01%; 100 mean 1%, =0, use VBIOS default setting. 5712 usDVISSpreadRateIn10Hz: DVI Spread Spectrum frequency in unit of 10Hz, =0, use VBIOS default setting. 5713 5714 usGPUReservedSysMemSize: Reserved system memory size for ACP engine in APU GNB, units in MB. 0/2/4MB based on CMOS options, current default could be 0MB. KV only, not on KB. 5715 ulGPUReservedSysMemBaseAddrLo: Low 32 bits base address to the reserved system memory. 5716 ulGPUReservedSysMemBaseAddrHi: High 32 bits base address to the reserved system memory. 5717 5718 usMaxLVDSPclkFreqInSingleLink: Max pixel clock LVDS panel single link, if=0 means VBIOS use default threhold, right now it is 85Mhz 5719 ucLVDSMisc: [bit0] LVDS 888bit panel mode =0: LVDS 888 panel in LDI mode, =1: LVDS 888 panel in FPDI mode 5720 [bit1] LVDS panel lower and upper link mapping =0: lower link and upper link not swap, =1: lower link and upper link are swapped 5721 [bit2] LVDS 888bit per color mode =0: 666 bit per color =1:888 bit per color 5722 [bit3] LVDS parameter override enable =0: ucLvdsMisc parameter are not used =1: ucLvdsMisc parameter should be used 5723 [bit4] Polarity of signal sent to digital BLON output pin. =0: not inverted(active high) =1: inverted ( active low ) 5724 [bit5] Travid LVDS output voltage override enable, when =1, use ucTravisLVDSVolAdjust value to overwrite Traivs register LVDS_CTRL_4 5725 ucTravisLVDSVolAdjust When ucLVDSMisc[5]=1,it means platform SBIOS want to overwrite TravisLVDSVoltage. Then VBIOS will use ucTravisLVDSVolAdjust 5726 value to program Travis register LVDS_CTRL_4 5727 ucLVDSPwrOnSeqDIGONtoDE_in4Ms: 5728 LVDS power up sequence time in unit of 4ms, time delay from DIGON signal active to data enable signal active( DE ). 5729 =0 mean use VBIOS default which is 8 ( 32ms ). The LVDS power up sequence is as following: DIGON->DE->VARY_BL->BLON. 5730 This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable. 5731 ucLVDSPwrOnDEtoVARY_BL_in4Ms: 5732 LVDS power up sequence time in unit of 4ms., time delay from DE( data enable ) active to Vary Brightness enable signal active( VARY_BL ). 5733 =0 mean use VBIOS default which is 90 ( 360ms ). The LVDS power up sequence is as following: DIGON->DE->VARY_BL->BLON. 5734 This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable. 5735 ucLVDSPwrOffVARY_BLtoDE_in4Ms: 5736 LVDS power down sequence time in unit of 4ms, time delay from data enable ( DE ) signal off to LCDVCC (DIGON) off. 5737 =0 mean use VBIOS default delay which is 8 ( 32ms ). The LVDS power down sequence is as following: BLON->VARY_BL->DE->DIGON 5738 This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable. 5739 ucLVDSPwrOffDEtoDIGON_in4Ms: 5740 LVDS power down sequence time in unit of 4ms, time delay from vary brightness enable signal( VARY_BL) off to data enable ( DE ) signal off. 5741 =0 mean use VBIOS default which is 90 ( 360ms ). The LVDS power down sequence is as following: BLON->VARY_BL->DE->DIGON 5742 This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable. 5743 ucLVDSOffToOnDelay_in4Ms: 5744 LVDS power down sequence time in unit of 4ms. Time delay from DIGON signal off to DIGON signal active. 5745 =0 means to use VBIOS default delay which is 125 ( 500ms ). 5746 This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable. 5747 ucLVDSPwrOnSeqVARY_BLtoBLON_in4Ms: 5748 LVDS power up sequence time in unit of 4ms. Time delay from VARY_BL signal on to DLON signal active. 5749 =0 means to use VBIOS default delay which is 0 ( 0ms ). 5750 This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable. 5751 5752 ucLVDSPwrOffSeqBLONtoVARY_BL_in4Ms: 5753 LVDS power down sequence time in unit of 4ms. Time delay from BLON signal off to VARY_BL signal off. 5754 =0 means to use VBIOS default delay which is 0 ( 0ms ). 5755 This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable. 5756 ucMinAllowedBL_Level: Lowest LCD backlight PWM level. This is customer platform specific parameters. By default it is 0. 5757 5758 ulLCDBitDepthControlVal: GPU display control encoder bit dither control setting, used to program register mmFMT_BIT_DEPTH_CONTROL 5759 5760 ulNbpStateMemclkFreq[4]: system memory clock frequncey in unit of 10Khz in different NB P-State(P0, P1, P2 & P3). 5761 ulNbpStateNClkFreq[4]: NB P-State NClk frequency in different NB P-State 5762 usNBPStateVoltage[4]: NB P-State (P0/P1 & P2/P3) voltage; NBP3 refers to lowes voltage 5763 usBootUpNBVoltage: NB P-State voltage during boot up before driver loaded 5764 sExtDispConnInfo: Display connector information table provided to VBIOS 5765 5766 **********************************************************************************************************************/ 5767 5768 // this Table is used for Kaveri/Kabini APU 5769 typedef struct _ATOM_FUSION_SYSTEM_INFO_V2 5770 { 5771 ATOM_INTEGRATED_SYSTEM_INFO_V1_8 sIntegratedSysInfo; // refer to ATOM_INTEGRATED_SYSTEM_INFO_V1_8 definition 5772 ULONG ulPowerplayTable[128]; // Update comments here to link new powerplay table definition structure 5773 }ATOM_FUSION_SYSTEM_INFO_V2; 5774 5775 5776 typedef struct _ATOM_I2C_REG_INFO 5777 { 5778 UCHAR ucI2cRegIndex; 5779 UCHAR ucI2cRegVal; 5780 }ATOM_I2C_REG_INFO; 5781 5782 // this IntegrateSystemInfoTable is used for Carrizo 5783 typedef struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_9 5784 { 5785 ATOM_COMMON_TABLE_HEADER sHeader; 5786 ULONG ulBootUpEngineClock; 5787 ULONG ulDentistVCOFreq; 5788 ULONG ulBootUpUMAClock; 5789 ATOM_CLK_VOLT_CAPABILITY sDISPCLK_Voltage[4]; // no longer used, keep it as is to avoid driver compiling error 5790 ULONG ulBootUpReqDisplayVector; 5791 ULONG ulVBIOSMisc; 5792 ULONG ulGPUCapInfo; 5793 ULONG ulDISP_CLK2Freq; 5794 USHORT usRequestedPWMFreqInHz; 5795 UCHAR ucHtcTmpLmt; 5796 UCHAR ucHtcHystLmt; 5797 ULONG ulReserved2; 5798 ULONG ulSystemConfig; 5799 ULONG ulCPUCapInfo; 5800 ULONG ulReserved3; 5801 USHORT usGPUReservedSysMemSize; 5802 USHORT usExtDispConnInfoOffset; 5803 USHORT usPanelRefreshRateRange; 5804 UCHAR ucMemoryType; 5805 UCHAR ucUMAChannelNumber; 5806 UCHAR strVBIOSMsg[40]; 5807 ATOM_TDP_CONFIG asTdpConfig; 5808 UCHAR ucExtHDMIReDrvSlvAddr; 5809 UCHAR ucExtHDMIReDrvRegNum; 5810 ATOM_I2C_REG_INFO asExtHDMIRegSetting[9]; 5811 ULONG ulReserved[2]; 5812 ATOM_CLK_VOLT_CAPABILITY_V2 sDispClkVoltageMapping[8]; 5813 ATOM_AVAILABLE_SCLK_LIST sAvail_SCLK[5]; // no longer used, keep it as is to avoid driver compiling error 5814 ULONG ulGMCRestoreResetTime; 5815 ULONG ulReserved4; 5816 ULONG ulIdleNClk; 5817 ULONG ulDDR_DLL_PowerUpTime; 5818 ULONG ulDDR_PLL_PowerUpTime; 5819 USHORT usPCIEClkSSPercentage; 5820 USHORT usPCIEClkSSType; 5821 USHORT usLvdsSSPercentage; 5822 USHORT usLvdsSSpreadRateIn10Hz; 5823 USHORT usHDMISSPercentage; 5824 USHORT usHDMISSpreadRateIn10Hz; 5825 USHORT usDVISSPercentage; 5826 USHORT usDVISSpreadRateIn10Hz; 5827 ULONG ulGPUReservedSysMemBaseAddrLo; 5828 ULONG ulGPUReservedSysMemBaseAddrHi; 5829 ULONG ulReserved5[3]; 5830 USHORT usMaxLVDSPclkFreqInSingleLink; 5831 UCHAR ucLvdsMisc; 5832 UCHAR ucTravisLVDSVolAdjust; 5833 UCHAR ucLVDSPwrOnSeqDIGONtoDE_in4Ms; 5834 UCHAR ucLVDSPwrOnSeqDEtoVARY_BL_in4Ms; 5835 UCHAR ucLVDSPwrOffSeqVARY_BLtoDE_in4Ms; 5836 UCHAR ucLVDSPwrOffSeqDEtoDIGON_in4Ms; 5837 UCHAR ucLVDSOffToOnDelay_in4Ms; 5838 UCHAR ucLVDSPwrOnSeqVARY_BLtoBLON_in4Ms; 5839 UCHAR ucLVDSPwrOffSeqBLONtoVARY_BL_in4Ms; 5840 UCHAR ucMinAllowedBL_Level; 5841 ULONG ulLCDBitDepthControlVal; 5842 ULONG ulNbpStateMemclkFreq[4]; // only 2 level is changed. 5843 ULONG ulPSPVersion; 5844 ULONG ulNbpStateNClkFreq[4]; 5845 USHORT usNBPStateVoltage[4]; 5846 USHORT usBootUpNBVoltage; 5847 UCHAR ucEDPv1_4VSMode; 5848 UCHAR ucReserved2; 5849 ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO sExtDispConnInfo; 5850 }ATOM_INTEGRATED_SYSTEM_INFO_V1_9; 5851 5852 5853 // definition for ucEDPv1_4VSMode 5854 #define EDP_VS_LEGACY_MODE 0 5855 #define EDP_VS_LOW_VDIFF_MODE 1 5856 #define EDP_VS_HIGH_VDIFF_MODE 2 5857 #define EDP_VS_STRETCH_MODE 3 5858 #define EDP_VS_SINGLE_VDIFF_MODE 4 5859 #define EDP_VS_VARIABLE_PREM_MODE 5 5860 5861 5862 // this IntegrateSystemInfoTable is used for Carrizo 5863 typedef struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_10 5864 { 5865 ATOM_COMMON_TABLE_HEADER sHeader; 5866 ULONG ulBootUpEngineClock; 5867 ULONG ulDentistVCOFreq; 5868 ULONG ulBootUpUMAClock; 5869 ULONG ulReserved0[8]; 5870 ULONG ulBootUpReqDisplayVector; 5871 ULONG ulVBIOSMisc; 5872 ULONG ulGPUCapInfo; 5873 ULONG ulReserved1; 5874 USHORT usRequestedPWMFreqInHz; 5875 UCHAR ucHtcTmpLmt; 5876 UCHAR ucHtcHystLmt; 5877 ULONG ulReserved2; 5878 ULONG ulSystemConfig; 5879 ULONG ulCPUCapInfo; 5880 ULONG ulReserved3; 5881 USHORT usGPUReservedSysMemSize; 5882 USHORT usExtDispConnInfoOffset; 5883 USHORT usPanelRefreshRateRange; 5884 UCHAR ucMemoryType; 5885 UCHAR ucUMAChannelNumber; 5886 UCHAR strVBIOSMsg[40]; 5887 ATOM_TDP_CONFIG asTdpConfig; 5888 ULONG ulReserved[7]; 5889 ATOM_CLK_VOLT_CAPABILITY_V2 sDispClkVoltageMapping[8]; 5890 ULONG ulReserved6[10]; 5891 ULONG ulGMCRestoreResetTime; 5892 ULONG ulReserved4; 5893 ULONG ulIdleNClk; 5894 ULONG ulDDR_DLL_PowerUpTime; 5895 ULONG ulDDR_PLL_PowerUpTime; 5896 USHORT usPCIEClkSSPercentage; 5897 USHORT usPCIEClkSSType; 5898 USHORT usLvdsSSPercentage; 5899 USHORT usLvdsSSpreadRateIn10Hz; 5900 USHORT usHDMISSPercentage; 5901 USHORT usHDMISSpreadRateIn10Hz; 5902 USHORT usDVISSPercentage; 5903 USHORT usDVISSpreadRateIn10Hz; 5904 ULONG ulGPUReservedSysMemBaseAddrLo; 5905 ULONG ulGPUReservedSysMemBaseAddrHi; 5906 ULONG ulReserved5[3]; 5907 USHORT usMaxLVDSPclkFreqInSingleLink; 5908 UCHAR ucLvdsMisc; 5909 UCHAR ucTravisLVDSVolAdjust; 5910 UCHAR ucLVDSPwrOnSeqDIGONtoDE_in4Ms; 5911 UCHAR ucLVDSPwrOnSeqDEtoVARY_BL_in4Ms; 5912 UCHAR ucLVDSPwrOffSeqVARY_BLtoDE_in4Ms; 5913 UCHAR ucLVDSPwrOffSeqDEtoDIGON_in4Ms; 5914 UCHAR ucLVDSOffToOnDelay_in4Ms; 5915 UCHAR ucLVDSPwrOnSeqVARY_BLtoBLON_in4Ms; 5916 UCHAR ucLVDSPwrOffSeqBLONtoVARY_BL_in4Ms; 5917 UCHAR ucMinAllowedBL_Level; 5918 ULONG ulLCDBitDepthControlVal; 5919 ULONG ulNbpStateMemclkFreq[2]; 5920 ULONG ulReserved7[2]; 5921 ULONG ulPSPVersion; 5922 ULONG ulNbpStateNClkFreq[4]; 5923 USHORT usNBPStateVoltage[4]; 5924 USHORT usBootUpNBVoltage; 5925 UCHAR ucEDPv1_4VSMode; 5926 UCHAR ucReserved2; 5927 ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO sExtDispConnInfo; 5928 }ATOM_INTEGRATED_SYSTEM_INFO_V1_10; 5929 5930 /**************************************************************************/ 5931 // This portion is only used when ext thermal chip or engine/memory clock SS chip is populated on a design 5932 //Memory SS Info Table 5933 //Define Memory Clock SS chip ID 5934 #define ICS91719 1 5935 #define ICS91720 2 5936 5937 //Define one structure to inform SW a "block of data" writing to external SS chip via I2C protocol 5938 typedef struct _ATOM_I2C_DATA_RECORD 5939 { 5940 UCHAR ucNunberOfBytes; //Indicates how many bytes SW needs to write to the external ASIC for one block, besides to "Start" and "Stop" 5941 UCHAR ucI2CData[1]; //I2C data in bytes, should be less than 16 bytes usually 5942 }ATOM_I2C_DATA_RECORD; 5943 5944 5945 //Define one structure to inform SW how many blocks of data writing to external SS chip via I2C protocol, in addition to other information 5946 typedef struct _ATOM_I2C_DEVICE_SETUP_INFO 5947 { 5948 ATOM_I2C_ID_CONFIG_ACCESS sucI2cId; //I2C line and HW/SW assisted cap. 5949 UCHAR ucSSChipID; //SS chip being used 5950 UCHAR ucSSChipSlaveAddr; //Slave Address to set up this SS chip 5951 UCHAR ucNumOfI2CDataRecords; //number of data block 5952 ATOM_I2C_DATA_RECORD asI2CData[1]; 5953 }ATOM_I2C_DEVICE_SETUP_INFO; 5954 5955 //========================================================================================== 5956 typedef struct _ATOM_ASIC_MVDD_INFO 5957 { 5958 ATOM_COMMON_TABLE_HEADER sHeader; 5959 ATOM_I2C_DEVICE_SETUP_INFO asI2CSetup[1]; 5960 }ATOM_ASIC_MVDD_INFO; 5961 5962 //========================================================================================== 5963 #define ATOM_MCLK_SS_INFO ATOM_ASIC_MVDD_INFO 5964 5965 //========================================================================================== 5966 /**************************************************************************/ 5967 5968 typedef struct _ATOM_ASIC_SS_ASSIGNMENT 5969 { 5970 ULONG ulTargetClockRange; //Clock Out frequence (VCO ), in unit of 10Khz 5971 USHORT usSpreadSpectrumPercentage; //in unit of 0.01% 5972 USHORT usSpreadRateInKhz; //in unit of kHz, modulation freq 5973 UCHAR ucClockIndication; //Indicate which clock source needs SS 5974 UCHAR ucSpreadSpectrumMode; //Bit1=0 Down Spread,=1 Center Spread. 5975 UCHAR ucReserved[2]; 5976 }ATOM_ASIC_SS_ASSIGNMENT; 5977 5978 //Define ucClockIndication, SW uses the IDs below to search if the SS is requried/enabled on a clock branch/signal type. 5979 //SS is not required or enabled if a match is not found. 5980 #define ASIC_INTERNAL_MEMORY_SS 1 5981 #define ASIC_INTERNAL_ENGINE_SS 2 5982 #define ASIC_INTERNAL_UVD_SS 3 5983 #define ASIC_INTERNAL_SS_ON_TMDS 4 5984 #define ASIC_INTERNAL_SS_ON_HDMI 5 5985 #define ASIC_INTERNAL_SS_ON_LVDS 6 5986 #define ASIC_INTERNAL_SS_ON_DP 7 5987 #define ASIC_INTERNAL_SS_ON_DCPLL 8 5988 #define ASIC_EXTERNAL_SS_ON_DP_CLOCK 9 5989 #define ASIC_INTERNAL_VCE_SS 10 5990 #define ASIC_INTERNAL_GPUPLL_SS 11 5991 5992 5993 typedef struct _ATOM_ASIC_SS_ASSIGNMENT_V2 5994 { 5995 ULONG ulTargetClockRange; //For mem/engine/uvd, Clock Out frequence (VCO ), in unit of 10Khz 5996 //For TMDS/HDMI/LVDS, it is pixel clock , for DP, it is link clock ( 27000 or 16200 ) 5997 USHORT usSpreadSpectrumPercentage; //in unit of 0.01% 5998 USHORT usSpreadRateIn10Hz; //in unit of 10Hz, modulation freq 5999 UCHAR ucClockIndication; //Indicate which clock source needs SS 6000 UCHAR ucSpreadSpectrumMode; //Bit0=0 Down Spread,=1 Center Spread, bit1=0: internal SS bit1=1: external SS 6001 UCHAR ucReserved[2]; 6002 }ATOM_ASIC_SS_ASSIGNMENT_V2; 6003 6004 //ucSpreadSpectrumMode 6005 //#define ATOM_SS_DOWN_SPREAD_MODE_MASK 0x00000000 6006 //#define ATOM_SS_DOWN_SPREAD_MODE 0x00000000 6007 //#define ATOM_SS_CENTRE_SPREAD_MODE_MASK 0x00000001 6008 //#define ATOM_SS_CENTRE_SPREAD_MODE 0x00000001 6009 //#define ATOM_INTERNAL_SS_MASK 0x00000000 6010 //#define ATOM_EXTERNAL_SS_MASK 0x00000002 6011 6012 typedef struct _ATOM_ASIC_INTERNAL_SS_INFO 6013 { 6014 ATOM_COMMON_TABLE_HEADER sHeader; 6015 ATOM_ASIC_SS_ASSIGNMENT asSpreadSpectrum[4]; 6016 }ATOM_ASIC_INTERNAL_SS_INFO; 6017 6018 typedef struct _ATOM_ASIC_INTERNAL_SS_INFO_V2 6019 { 6020 ATOM_COMMON_TABLE_HEADER sHeader; 6021 ATOM_ASIC_SS_ASSIGNMENT_V2 asSpreadSpectrum[1]; //this is point only. 6022 }ATOM_ASIC_INTERNAL_SS_INFO_V2; 6023 6024 typedef struct _ATOM_ASIC_SS_ASSIGNMENT_V3 6025 { 6026 ULONG ulTargetClockRange; //For mem/engine/uvd, Clock Out frequence (VCO ), in unit of 10Khz 6027 //For TMDS/HDMI/LVDS, it is pixel clock , for DP, it is link clock ( 27000 or 16200 ) 6028 USHORT usSpreadSpectrumPercentage; //in unit of 0.01% or 0.001%, decided by ucSpreadSpectrumMode bit4 6029 USHORT usSpreadRateIn10Hz; //in unit of 10Hz, modulation freq 6030 UCHAR ucClockIndication; //Indicate which clock source needs SS 6031 UCHAR ucSpreadSpectrumMode; //Bit0=0 Down Spread,=1 Center Spread, bit1=0: internal SS bit1=1: external SS 6032 UCHAR ucReserved[2]; 6033 }ATOM_ASIC_SS_ASSIGNMENT_V3; 6034 6035 //ATOM_ASIC_SS_ASSIGNMENT_V3.ucSpreadSpectrumMode 6036 #define SS_MODE_V3_CENTRE_SPREAD_MASK 0x01 6037 #define SS_MODE_V3_EXTERNAL_SS_MASK 0x02 6038 #define SS_MODE_V3_PERCENTAGE_DIV_BY_1000_MASK 0x10 6039 6040 typedef struct _ATOM_ASIC_INTERNAL_SS_INFO_V3 6041 { 6042 ATOM_COMMON_TABLE_HEADER sHeader; 6043 ATOM_ASIC_SS_ASSIGNMENT_V3 asSpreadSpectrum[1]; //this is pointer only. 6044 }ATOM_ASIC_INTERNAL_SS_INFO_V3; 6045 6046 6047 //==============================Scratch Pad Definition Portion=============================== 6048 #define ATOM_DEVICE_CONNECT_INFO_DEF 0 6049 #define ATOM_ROM_LOCATION_DEF 1 6050 #define ATOM_TV_STANDARD_DEF 2 6051 #define ATOM_ACTIVE_INFO_DEF 3 6052 #define ATOM_LCD_INFO_DEF 4 6053 #define ATOM_DOS_REQ_INFO_DEF 5 6054 #define ATOM_ACC_CHANGE_INFO_DEF 6 6055 #define ATOM_DOS_MODE_INFO_DEF 7 6056 #define ATOM_I2C_CHANNEL_STATUS_DEF 8 6057 #define ATOM_I2C_CHANNEL_STATUS1_DEF 9 6058 #define ATOM_INTERNAL_TIMER_DEF 10 6059 6060 // BIOS_0_SCRATCH Definition 6061 #define ATOM_S0_CRT1_MONO 0x00000001L 6062 #define ATOM_S0_CRT1_COLOR 0x00000002L 6063 #define ATOM_S0_CRT1_MASK (ATOM_S0_CRT1_MONO+ATOM_S0_CRT1_COLOR) 6064 6065 #define ATOM_S0_TV1_COMPOSITE_A 0x00000004L 6066 #define ATOM_S0_TV1_SVIDEO_A 0x00000008L 6067 #define ATOM_S0_TV1_MASK_A (ATOM_S0_TV1_COMPOSITE_A+ATOM_S0_TV1_SVIDEO_A) 6068 6069 #define ATOM_S0_CV_A 0x00000010L 6070 #define ATOM_S0_CV_DIN_A 0x00000020L 6071 #define ATOM_S0_CV_MASK_A (ATOM_S0_CV_A+ATOM_S0_CV_DIN_A) 6072 6073 6074 #define ATOM_S0_CRT2_MONO 0x00000100L 6075 #define ATOM_S0_CRT2_COLOR 0x00000200L 6076 #define ATOM_S0_CRT2_MASK (ATOM_S0_CRT2_MONO+ATOM_S0_CRT2_COLOR) 6077 6078 #define ATOM_S0_TV1_COMPOSITE 0x00000400L 6079 #define ATOM_S0_TV1_SVIDEO 0x00000800L 6080 #define ATOM_S0_TV1_SCART 0x00004000L 6081 #define ATOM_S0_TV1_MASK (ATOM_S0_TV1_COMPOSITE+ATOM_S0_TV1_SVIDEO+ATOM_S0_TV1_SCART) 6082 6083 #define ATOM_S0_CV 0x00001000L 6084 #define ATOM_S0_CV_DIN 0x00002000L 6085 #define ATOM_S0_CV_MASK (ATOM_S0_CV+ATOM_S0_CV_DIN) 6086 6087 #define ATOM_S0_DFP1 0x00010000L 6088 #define ATOM_S0_DFP2 0x00020000L 6089 #define ATOM_S0_LCD1 0x00040000L 6090 #define ATOM_S0_LCD2 0x00080000L 6091 #define ATOM_S0_DFP6 0x00100000L 6092 #define ATOM_S0_DFP3 0x00200000L 6093 #define ATOM_S0_DFP4 0x00400000L 6094 #define ATOM_S0_DFP5 0x00800000L 6095 6096 6097 #define ATOM_S0_DFP_MASK ATOM_S0_DFP1 | ATOM_S0_DFP2 | ATOM_S0_DFP3 | ATOM_S0_DFP4 | ATOM_S0_DFP5 | ATOM_S0_DFP6 6098 6099 #define ATOM_S0_FAD_REGISTER_BUG 0x02000000L // If set, indicates we are running a PCIE asic with 6100 // the FAD/HDP reg access bug. Bit is read by DAL, this is obsolete from RV5xx 6101 6102 #define ATOM_S0_THERMAL_STATE_MASK 0x1C000000L 6103 #define ATOM_S0_THERMAL_STATE_SHIFT 26 6104 6105 #define ATOM_S0_SYSTEM_POWER_STATE_MASK 0xE0000000L 6106 #define ATOM_S0_SYSTEM_POWER_STATE_SHIFT 29 6107 6108 #define ATOM_S0_SYSTEM_POWER_STATE_VALUE_AC 1 6109 #define ATOM_S0_SYSTEM_POWER_STATE_VALUE_DC 2 6110 #define ATOM_S0_SYSTEM_POWER_STATE_VALUE_LITEAC 3 6111 #define ATOM_S0_SYSTEM_POWER_STATE_VALUE_LIT2AC 4 6112 6113 //Byte aligned defintion for BIOS usage 6114 #define ATOM_S0_CRT1_MONOb0 0x01 6115 #define ATOM_S0_CRT1_COLORb0 0x02 6116 #define ATOM_S0_CRT1_MASKb0 (ATOM_S0_CRT1_MONOb0+ATOM_S0_CRT1_COLORb0) 6117 6118 #define ATOM_S0_TV1_COMPOSITEb0 0x04 6119 #define ATOM_S0_TV1_SVIDEOb0 0x08 6120 #define ATOM_S0_TV1_MASKb0 (ATOM_S0_TV1_COMPOSITEb0+ATOM_S0_TV1_SVIDEOb0) 6121 6122 #define ATOM_S0_CVb0 0x10 6123 #define ATOM_S0_CV_DINb0 0x20 6124 #define ATOM_S0_CV_MASKb0 (ATOM_S0_CVb0+ATOM_S0_CV_DINb0) 6125 6126 #define ATOM_S0_CRT2_MONOb1 0x01 6127 #define ATOM_S0_CRT2_COLORb1 0x02 6128 #define ATOM_S0_CRT2_MASKb1 (ATOM_S0_CRT2_MONOb1+ATOM_S0_CRT2_COLORb1) 6129 6130 #define ATOM_S0_TV1_COMPOSITEb1 0x04 6131 #define ATOM_S0_TV1_SVIDEOb1 0x08 6132 #define ATOM_S0_TV1_SCARTb1 0x40 6133 #define ATOM_S0_TV1_MASKb1 (ATOM_S0_TV1_COMPOSITEb1+ATOM_S0_TV1_SVIDEOb1+ATOM_S0_TV1_SCARTb1) 6134 6135 #define ATOM_S0_CVb1 0x10 6136 #define ATOM_S0_CV_DINb1 0x20 6137 #define ATOM_S0_CV_MASKb1 (ATOM_S0_CVb1+ATOM_S0_CV_DINb1) 6138 6139 #define ATOM_S0_DFP1b2 0x01 6140 #define ATOM_S0_DFP2b2 0x02 6141 #define ATOM_S0_LCD1b2 0x04 6142 #define ATOM_S0_LCD2b2 0x08 6143 #define ATOM_S0_DFP6b2 0x10 6144 #define ATOM_S0_DFP3b2 0x20 6145 #define ATOM_S0_DFP4b2 0x40 6146 #define ATOM_S0_DFP5b2 0x80 6147 6148 6149 #define ATOM_S0_THERMAL_STATE_MASKb3 0x1C 6150 #define ATOM_S0_THERMAL_STATE_SHIFTb3 2 6151 6152 #define ATOM_S0_SYSTEM_POWER_STATE_MASKb3 0xE0 6153 #define ATOM_S0_LCD1_SHIFT 18 6154 6155 // BIOS_1_SCRATCH Definition 6156 #define ATOM_S1_ROM_LOCATION_MASK 0x0000FFFFL 6157 #define ATOM_S1_PCI_BUS_DEV_MASK 0xFFFF0000L 6158 6159 // BIOS_2_SCRATCH Definition 6160 #define ATOM_S2_TV1_STANDARD_MASK 0x0000000FL 6161 #define ATOM_S2_CURRENT_BL_LEVEL_MASK 0x0000FF00L 6162 #define ATOM_S2_CURRENT_BL_LEVEL_SHIFT 8 6163 6164 #define ATOM_S2_FORCEDLOWPWRMODE_STATE_MASK 0x0C000000L 6165 #define ATOM_S2_FORCEDLOWPWRMODE_STATE_MASK_SHIFT 26 6166 #define ATOM_S2_FORCEDLOWPWRMODE_STATE_CHANGE 0x10000000L 6167 6168 #define ATOM_S2_DEVICE_DPMS_STATE 0x00010000L 6169 #define ATOM_S2_VRI_BRIGHT_ENABLE 0x20000000L 6170 6171 #define ATOM_S2_DISPLAY_ROTATION_0_DEGREE 0x0 6172 #define ATOM_S2_DISPLAY_ROTATION_90_DEGREE 0x1 6173 #define ATOM_S2_DISPLAY_ROTATION_180_DEGREE 0x2 6174 #define ATOM_S2_DISPLAY_ROTATION_270_DEGREE 0x3 6175 #define ATOM_S2_DISPLAY_ROTATION_DEGREE_SHIFT 30 6176 #define ATOM_S2_DISPLAY_ROTATION_ANGLE_MASK 0xC0000000L 6177 6178 6179 //Byte aligned defintion for BIOS usage 6180 #define ATOM_S2_TV1_STANDARD_MASKb0 0x0F 6181 #define ATOM_S2_CURRENT_BL_LEVEL_MASKb1 0xFF 6182 #define ATOM_S2_DEVICE_DPMS_STATEb2 0x01 6183 6184 #define ATOM_S2_TMDS_COHERENT_MODEb3 0x10 // used by VBIOS code only, use coherent mode for TMDS/HDMI mode 6185 #define ATOM_S2_VRI_BRIGHT_ENABLEb3 0x20 6186 #define ATOM_S2_ROTATION_STATE_MASKb3 0xC0 6187 6188 6189 // BIOS_3_SCRATCH Definition 6190 #define ATOM_S3_CRT1_ACTIVE 0x00000001L 6191 #define ATOM_S3_LCD1_ACTIVE 0x00000002L 6192 #define ATOM_S3_TV1_ACTIVE 0x00000004L 6193 #define ATOM_S3_DFP1_ACTIVE 0x00000008L 6194 #define ATOM_S3_CRT2_ACTIVE 0x00000010L 6195 #define ATOM_S3_LCD2_ACTIVE 0x00000020L 6196 #define ATOM_S3_DFP6_ACTIVE 0x00000040L 6197 #define ATOM_S3_DFP2_ACTIVE 0x00000080L 6198 #define ATOM_S3_CV_ACTIVE 0x00000100L 6199 #define ATOM_S3_DFP3_ACTIVE 0x00000200L 6200 #define ATOM_S3_DFP4_ACTIVE 0x00000400L 6201 #define ATOM_S3_DFP5_ACTIVE 0x00000800L 6202 6203 6204 #define ATOM_S3_DEVICE_ACTIVE_MASK 0x00000FFFL 6205 6206 #define ATOM_S3_LCD_FULLEXPANSION_ACTIVE 0x00001000L 6207 #define ATOM_S3_LCD_EXPANSION_ASPEC_RATIO_ACTIVE 0x00002000L 6208 6209 #define ATOM_S3_CRT1_CRTC_ACTIVE 0x00010000L 6210 #define ATOM_S3_LCD1_CRTC_ACTIVE 0x00020000L 6211 #define ATOM_S3_TV1_CRTC_ACTIVE 0x00040000L 6212 #define ATOM_S3_DFP1_CRTC_ACTIVE 0x00080000L 6213 #define ATOM_S3_CRT2_CRTC_ACTIVE 0x00100000L 6214 #define ATOM_S3_LCD2_CRTC_ACTIVE 0x00200000L 6215 #define ATOM_S3_DFP6_CRTC_ACTIVE 0x00400000L 6216 #define ATOM_S3_DFP2_CRTC_ACTIVE 0x00800000L 6217 #define ATOM_S3_CV_CRTC_ACTIVE 0x01000000L 6218 #define ATOM_S3_DFP3_CRTC_ACTIVE 0x02000000L 6219 #define ATOM_S3_DFP4_CRTC_ACTIVE 0x04000000L 6220 #define ATOM_S3_DFP5_CRTC_ACTIVE 0x08000000L 6221 6222 6223 #define ATOM_S3_DEVICE_CRTC_ACTIVE_MASK 0x0FFF0000L 6224 #define ATOM_S3_ASIC_GUI_ENGINE_HUNG 0x20000000L 6225 //Below two definitions are not supported in pplib, but in the old powerplay in DAL 6226 #define ATOM_S3_ALLOW_FAST_PWR_SWITCH 0x40000000L 6227 #define ATOM_S3_RQST_GPU_USE_MIN_PWR 0x80000000L 6228 6229 6230 6231 //Byte aligned defintion for BIOS usage 6232 #define ATOM_S3_CRT1_ACTIVEb0 0x01 6233 #define ATOM_S3_LCD1_ACTIVEb0 0x02 6234 #define ATOM_S3_TV1_ACTIVEb0 0x04 6235 #define ATOM_S3_DFP1_ACTIVEb0 0x08 6236 #define ATOM_S3_CRT2_ACTIVEb0 0x10 6237 #define ATOM_S3_LCD2_ACTIVEb0 0x20 6238 #define ATOM_S3_DFP6_ACTIVEb0 0x40 6239 #define ATOM_S3_DFP2_ACTIVEb0 0x80 6240 #define ATOM_S3_CV_ACTIVEb1 0x01 6241 #define ATOM_S3_DFP3_ACTIVEb1 0x02 6242 #define ATOM_S3_DFP4_ACTIVEb1 0x04 6243 #define ATOM_S3_DFP5_ACTIVEb1 0x08 6244 6245 6246 #define ATOM_S3_ACTIVE_CRTC1w0 0xFFF 6247 6248 #define ATOM_S3_CRT1_CRTC_ACTIVEb2 0x01 6249 #define ATOM_S3_LCD1_CRTC_ACTIVEb2 0x02 6250 #define ATOM_S3_TV1_CRTC_ACTIVEb2 0x04 6251 #define ATOM_S3_DFP1_CRTC_ACTIVEb2 0x08 6252 #define ATOM_S3_CRT2_CRTC_ACTIVEb2 0x10 6253 #define ATOM_S3_LCD2_CRTC_ACTIVEb2 0x20 6254 #define ATOM_S3_DFP6_CRTC_ACTIVEb2 0x40 6255 #define ATOM_S3_DFP2_CRTC_ACTIVEb2 0x80 6256 #define ATOM_S3_CV_CRTC_ACTIVEb3 0x01 6257 #define ATOM_S3_DFP3_CRTC_ACTIVEb3 0x02 6258 #define ATOM_S3_DFP4_CRTC_ACTIVEb3 0x04 6259 #define ATOM_S3_DFP5_CRTC_ACTIVEb3 0x08 6260 6261 6262 #define ATOM_S3_ACTIVE_CRTC2w1 0xFFF 6263 6264 6265 // BIOS_4_SCRATCH Definition 6266 #define ATOM_S4_LCD1_PANEL_ID_MASK 0x000000FFL 6267 #define ATOM_S4_LCD1_REFRESH_MASK 0x0000FF00L 6268 #define ATOM_S4_LCD1_REFRESH_SHIFT 8 6269 6270 //Byte aligned defintion for BIOS usage 6271 #define ATOM_S4_LCD1_PANEL_ID_MASKb0 0x0FF 6272 #define ATOM_S4_LCD1_REFRESH_MASKb1 ATOM_S4_LCD1_PANEL_ID_MASKb0 6273 #define ATOM_S4_VRAM_INFO_MASKb2 ATOM_S4_LCD1_PANEL_ID_MASKb0 6274 6275 // BIOS_5_SCRATCH Definition, BIOS_5_SCRATCH is used by Firmware only !!!! 6276 #define ATOM_S5_DOS_REQ_CRT1b0 0x01 6277 #define ATOM_S5_DOS_REQ_LCD1b0 0x02 6278 #define ATOM_S5_DOS_REQ_TV1b0 0x04 6279 #define ATOM_S5_DOS_REQ_DFP1b0 0x08 6280 #define ATOM_S5_DOS_REQ_CRT2b0 0x10 6281 #define ATOM_S5_DOS_REQ_LCD2b0 0x20 6282 #define ATOM_S5_DOS_REQ_DFP6b0 0x40 6283 #define ATOM_S5_DOS_REQ_DFP2b0 0x80 6284 #define ATOM_S5_DOS_REQ_CVb1 0x01 6285 #define ATOM_S5_DOS_REQ_DFP3b1 0x02 6286 #define ATOM_S5_DOS_REQ_DFP4b1 0x04 6287 #define ATOM_S5_DOS_REQ_DFP5b1 0x08 6288 6289 6290 #define ATOM_S5_DOS_REQ_DEVICEw0 0x0FFF 6291 6292 #define ATOM_S5_DOS_REQ_CRT1 0x0001 6293 #define ATOM_S5_DOS_REQ_LCD1 0x0002 6294 #define ATOM_S5_DOS_REQ_TV1 0x0004 6295 #define ATOM_S5_DOS_REQ_DFP1 0x0008 6296 #define ATOM_S5_DOS_REQ_CRT2 0x0010 6297 #define ATOM_S5_DOS_REQ_LCD2 0x0020 6298 #define ATOM_S5_DOS_REQ_DFP6 0x0040 6299 #define ATOM_S5_DOS_REQ_DFP2 0x0080 6300 #define ATOM_S5_DOS_REQ_CV 0x0100 6301 #define ATOM_S5_DOS_REQ_DFP3 0x0200 6302 #define ATOM_S5_DOS_REQ_DFP4 0x0400 6303 #define ATOM_S5_DOS_REQ_DFP5 0x0800 6304 6305 #define ATOM_S5_DOS_FORCE_CRT1b2 ATOM_S5_DOS_REQ_CRT1b0 6306 #define ATOM_S5_DOS_FORCE_TV1b2 ATOM_S5_DOS_REQ_TV1b0 6307 #define ATOM_S5_DOS_FORCE_CRT2b2 ATOM_S5_DOS_REQ_CRT2b0 6308 #define ATOM_S5_DOS_FORCE_CVb3 ATOM_S5_DOS_REQ_CVb1 6309 #define ATOM_S5_DOS_FORCE_DEVICEw1 (ATOM_S5_DOS_FORCE_CRT1b2+ATOM_S5_DOS_FORCE_TV1b2+ATOM_S5_DOS_FORCE_CRT2b2+\ 6310 (ATOM_S5_DOS_FORCE_CVb3<<8)) 6311 // BIOS_6_SCRATCH Definition 6312 #define ATOM_S6_DEVICE_CHANGE 0x00000001L 6313 #define ATOM_S6_SCALER_CHANGE 0x00000002L 6314 #define ATOM_S6_LID_CHANGE 0x00000004L 6315 #define ATOM_S6_DOCKING_CHANGE 0x00000008L 6316 #define ATOM_S6_ACC_MODE 0x00000010L 6317 #define ATOM_S6_EXT_DESKTOP_MODE 0x00000020L 6318 #define ATOM_S6_LID_STATE 0x00000040L 6319 #define ATOM_S6_DOCK_STATE 0x00000080L 6320 #define ATOM_S6_CRITICAL_STATE 0x00000100L 6321 #define ATOM_S6_HW_I2C_BUSY_STATE 0x00000200L 6322 #define ATOM_S6_THERMAL_STATE_CHANGE 0x00000400L 6323 #define ATOM_S6_INTERRUPT_SET_BY_BIOS 0x00000800L 6324 #define ATOM_S6_REQ_LCD_EXPANSION_FULL 0x00001000L //Normal expansion Request bit for LCD 6325 #define ATOM_S6_REQ_LCD_EXPANSION_ASPEC_RATIO 0x00002000L //Aspect ratio expansion Request bit for LCD 6326 6327 #define ATOM_S6_DISPLAY_STATE_CHANGE 0x00004000L //This bit is recycled when ATOM_BIOS_INFO_BIOS_SCRATCH6_SCL2_REDEFINE is set,previously it's SCL2_H_expansion 6328 #define ATOM_S6_I2C_STATE_CHANGE 0x00008000L //This bit is recycled,when ATOM_BIOS_INFO_BIOS_SCRATCH6_SCL2_REDEFINE is set,previously it's SCL2_V_expansion 6329 6330 #define ATOM_S6_ACC_REQ_CRT1 0x00010000L 6331 #define ATOM_S6_ACC_REQ_LCD1 0x00020000L 6332 #define ATOM_S6_ACC_REQ_TV1 0x00040000L 6333 #define ATOM_S6_ACC_REQ_DFP1 0x00080000L 6334 #define ATOM_S6_ACC_REQ_CRT2 0x00100000L 6335 #define ATOM_S6_ACC_REQ_LCD2 0x00200000L 6336 #define ATOM_S6_ACC_REQ_DFP6 0x00400000L 6337 #define ATOM_S6_ACC_REQ_DFP2 0x00800000L 6338 #define ATOM_S6_ACC_REQ_CV 0x01000000L 6339 #define ATOM_S6_ACC_REQ_DFP3 0x02000000L 6340 #define ATOM_S6_ACC_REQ_DFP4 0x04000000L 6341 #define ATOM_S6_ACC_REQ_DFP5 0x08000000L 6342 6343 #define ATOM_S6_ACC_REQ_MASK 0x0FFF0000L 6344 #define ATOM_S6_SYSTEM_POWER_MODE_CHANGE 0x10000000L 6345 #define ATOM_S6_ACC_BLOCK_DISPLAY_SWITCH 0x20000000L 6346 #define ATOM_S6_VRI_BRIGHTNESS_CHANGE 0x40000000L 6347 #define ATOM_S6_CONFIG_DISPLAY_CHANGE_MASK 0x80000000L 6348 6349 //Byte aligned defintion for BIOS usage 6350 #define ATOM_S6_DEVICE_CHANGEb0 0x01 6351 #define ATOM_S6_SCALER_CHANGEb0 0x02 6352 #define ATOM_S6_LID_CHANGEb0 0x04 6353 #define ATOM_S6_DOCKING_CHANGEb0 0x08 6354 #define ATOM_S6_ACC_MODEb0 0x10 6355 #define ATOM_S6_EXT_DESKTOP_MODEb0 0x20 6356 #define ATOM_S6_LID_STATEb0 0x40 6357 #define ATOM_S6_DOCK_STATEb0 0x80 6358 #define ATOM_S6_CRITICAL_STATEb1 0x01 6359 #define ATOM_S6_HW_I2C_BUSY_STATEb1 0x02 6360 #define ATOM_S6_THERMAL_STATE_CHANGEb1 0x04 6361 #define ATOM_S6_INTERRUPT_SET_BY_BIOSb1 0x08 6362 #define ATOM_S6_REQ_LCD_EXPANSION_FULLb1 0x10 6363 #define ATOM_S6_REQ_LCD_EXPANSION_ASPEC_RATIOb1 0x20 6364 6365 #define ATOM_S6_ACC_REQ_CRT1b2 0x01 6366 #define ATOM_S6_ACC_REQ_LCD1b2 0x02 6367 #define ATOM_S6_ACC_REQ_TV1b2 0x04 6368 #define ATOM_S6_ACC_REQ_DFP1b2 0x08 6369 #define ATOM_S6_ACC_REQ_CRT2b2 0x10 6370 #define ATOM_S6_ACC_REQ_LCD2b2 0x20 6371 #define ATOM_S6_ACC_REQ_DFP6b2 0x40 6372 #define ATOM_S6_ACC_REQ_DFP2b2 0x80 6373 #define ATOM_S6_ACC_REQ_CVb3 0x01 6374 #define ATOM_S6_ACC_REQ_DFP3b3 0x02 6375 #define ATOM_S6_ACC_REQ_DFP4b3 0x04 6376 #define ATOM_S6_ACC_REQ_DFP5b3 0x08 6377 6378 #define ATOM_S6_ACC_REQ_DEVICEw1 ATOM_S5_DOS_REQ_DEVICEw0 6379 #define ATOM_S6_SYSTEM_POWER_MODE_CHANGEb3 0x10 6380 #define ATOM_S6_ACC_BLOCK_DISPLAY_SWITCHb3 0x20 6381 #define ATOM_S6_VRI_BRIGHTNESS_CHANGEb3 0x40 6382 #define ATOM_S6_CONFIG_DISPLAY_CHANGEb3 0x80 6383 6384 #define ATOM_S6_DEVICE_CHANGE_SHIFT 0 6385 #define ATOM_S6_SCALER_CHANGE_SHIFT 1 6386 #define ATOM_S6_LID_CHANGE_SHIFT 2 6387 #define ATOM_S6_DOCKING_CHANGE_SHIFT 3 6388 #define ATOM_S6_ACC_MODE_SHIFT 4 6389 #define ATOM_S6_EXT_DESKTOP_MODE_SHIFT 5 6390 #define ATOM_S6_LID_STATE_SHIFT 6 6391 #define ATOM_S6_DOCK_STATE_SHIFT 7 6392 #define ATOM_S6_CRITICAL_STATE_SHIFT 8 6393 #define ATOM_S6_HW_I2C_BUSY_STATE_SHIFT 9 6394 #define ATOM_S6_THERMAL_STATE_CHANGE_SHIFT 10 6395 #define ATOM_S6_INTERRUPT_SET_BY_BIOS_SHIFT 11 6396 #define ATOM_S6_REQ_SCALER_SHIFT 12 6397 #define ATOM_S6_REQ_SCALER_ARATIO_SHIFT 13 6398 #define ATOM_S6_DISPLAY_STATE_CHANGE_SHIFT 14 6399 #define ATOM_S6_I2C_STATE_CHANGE_SHIFT 15 6400 #define ATOM_S6_SYSTEM_POWER_MODE_CHANGE_SHIFT 28 6401 #define ATOM_S6_ACC_BLOCK_DISPLAY_SWITCH_SHIFT 29 6402 #define ATOM_S6_VRI_BRIGHTNESS_CHANGE_SHIFT 30 6403 #define ATOM_S6_CONFIG_DISPLAY_CHANGE_SHIFT 31 6404 6405 // BIOS_7_SCRATCH Definition, BIOS_7_SCRATCH is used by Firmware only !!!! 6406 #define ATOM_S7_DOS_MODE_TYPEb0 0x03 6407 #define ATOM_S7_DOS_MODE_VGAb0 0x00 6408 #define ATOM_S7_DOS_MODE_VESAb0 0x01 6409 #define ATOM_S7_DOS_MODE_EXTb0 0x02 6410 #define ATOM_S7_DOS_MODE_PIXEL_DEPTHb0 0x0C 6411 #define ATOM_S7_DOS_MODE_PIXEL_FORMATb0 0xF0 6412 #define ATOM_S7_DOS_8BIT_DAC_ENb1 0x01 6413 #define ATOM_S7_ASIC_INIT_COMPLETEb1 0x02 6414 #define ATOM_S7_ASIC_INIT_COMPLETE_MASK 0x00000200 6415 #define ATOM_S7_DOS_MODE_NUMBERw1 0x0FFFF 6416 6417 #define ATOM_S7_DOS_8BIT_DAC_EN_SHIFT 8 6418 6419 // BIOS_8_SCRATCH Definition 6420 #define ATOM_S8_I2C_CHANNEL_BUSY_MASK 0x00000FFFF 6421 #define ATOM_S8_I2C_HW_ENGINE_BUSY_MASK 0x0FFFF0000 6422 6423 #define ATOM_S8_I2C_CHANNEL_BUSY_SHIFT 0 6424 #define ATOM_S8_I2C_ENGINE_BUSY_SHIFT 16 6425 6426 // BIOS_9_SCRATCH Definition 6427 #ifndef ATOM_S9_I2C_CHANNEL_COMPLETED_MASK 6428 #define ATOM_S9_I2C_CHANNEL_COMPLETED_MASK 0x0000FFFF 6429 #endif 6430 #ifndef ATOM_S9_I2C_CHANNEL_ABORTED_MASK 6431 #define ATOM_S9_I2C_CHANNEL_ABORTED_MASK 0xFFFF0000 6432 #endif 6433 #ifndef ATOM_S9_I2C_CHANNEL_COMPLETED_SHIFT 6434 #define ATOM_S9_I2C_CHANNEL_COMPLETED_SHIFT 0 6435 #endif 6436 #ifndef ATOM_S9_I2C_CHANNEL_ABORTED_SHIFT 6437 #define ATOM_S9_I2C_CHANNEL_ABORTED_SHIFT 16 6438 #endif 6439 6440 6441 #define ATOM_FLAG_SET 0x20 6442 #define ATOM_FLAG_CLEAR 0 6443 #define CLEAR_ATOM_S6_ACC_MODE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_ACC_MODE_SHIFT | ATOM_FLAG_CLEAR) 6444 #define SET_ATOM_S6_DEVICE_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_DEVICE_CHANGE_SHIFT | ATOM_FLAG_SET) 6445 #define SET_ATOM_S6_VRI_BRIGHTNESS_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_VRI_BRIGHTNESS_CHANGE_SHIFT | ATOM_FLAG_SET) 6446 #define SET_ATOM_S6_SCALER_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_SCALER_CHANGE_SHIFT | ATOM_FLAG_SET) 6447 #define SET_ATOM_S6_LID_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_LID_CHANGE_SHIFT | ATOM_FLAG_SET) 6448 6449 #define SET_ATOM_S6_LID_STATE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_LID_STATE_SHIFT | ATOM_FLAG_SET) 6450 #define CLEAR_ATOM_S6_LID_STATE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_LID_STATE_SHIFT | ATOM_FLAG_CLEAR) 6451 6452 #define SET_ATOM_S6_DOCK_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_DOCKING_CHANGE_SHIFT | ATOM_FLAG_SET) 6453 #define SET_ATOM_S6_DOCK_STATE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_DOCK_STATE_SHIFT | ATOM_FLAG_SET) 6454 #define CLEAR_ATOM_S6_DOCK_STATE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_DOCK_STATE_SHIFT | ATOM_FLAG_CLEAR) 6455 6456 #define SET_ATOM_S6_THERMAL_STATE_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_THERMAL_STATE_CHANGE_SHIFT | ATOM_FLAG_SET) 6457 #define SET_ATOM_S6_SYSTEM_POWER_MODE_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_SYSTEM_POWER_MODE_CHANGE_SHIFT | ATOM_FLAG_SET) 6458 #define SET_ATOM_S6_INTERRUPT_SET_BY_BIOS ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_INTERRUPT_SET_BY_BIOS_SHIFT | ATOM_FLAG_SET) 6459 6460 #define SET_ATOM_S6_CRITICAL_STATE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_CRITICAL_STATE_SHIFT | ATOM_FLAG_SET) 6461 #define CLEAR_ATOM_S6_CRITICAL_STATE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_CRITICAL_STATE_SHIFT | ATOM_FLAG_CLEAR) 6462 6463 #define SET_ATOM_S6_REQ_SCALER ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_REQ_SCALER_SHIFT | ATOM_FLAG_SET) 6464 #define CLEAR_ATOM_S6_REQ_SCALER ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_REQ_SCALER_SHIFT | ATOM_FLAG_CLEAR ) 6465 6466 #define SET_ATOM_S6_REQ_SCALER_ARATIO ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_REQ_SCALER_ARATIO_SHIFT | ATOM_FLAG_SET ) 6467 #define CLEAR_ATOM_S6_REQ_SCALER_ARATIO ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_REQ_SCALER_ARATIO_SHIFT | ATOM_FLAG_CLEAR ) 6468 6469 #define SET_ATOM_S6_I2C_STATE_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_I2C_STATE_CHANGE_SHIFT | ATOM_FLAG_SET ) 6470 6471 #define SET_ATOM_S6_DISPLAY_STATE_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_DISPLAY_STATE_CHANGE_SHIFT | ATOM_FLAG_SET ) 6472 6473 #define SET_ATOM_S6_DEVICE_RECONFIG ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_CONFIG_DISPLAY_CHANGE_SHIFT | ATOM_FLAG_SET) 6474 #define CLEAR_ATOM_S0_LCD1 ((ATOM_DEVICE_CONNECT_INFO_DEF << 8 )| ATOM_S0_LCD1_SHIFT | ATOM_FLAG_CLEAR ) 6475 #define SET_ATOM_S7_DOS_8BIT_DAC_EN ((ATOM_DOS_MODE_INFO_DEF << 8 )|ATOM_S7_DOS_8BIT_DAC_EN_SHIFT | ATOM_FLAG_SET ) 6476 #define CLEAR_ATOM_S7_DOS_8BIT_DAC_EN ((ATOM_DOS_MODE_INFO_DEF << 8 )|ATOM_S7_DOS_8BIT_DAC_EN_SHIFT | ATOM_FLAG_CLEAR ) 6477 6478 /****************************************************************************/ 6479 //Portion II: Definitinos only used in Driver 6480 /****************************************************************************/ 6481 6482 // Macros used by driver 6483 6484 #ifdef __cplusplus 6485 #define GetIndexIntoMasterTable(MasterOrData, FieldName) ((reinterpret_cast<char*>(&(static_cast<ATOM_MASTER_LIST_OF_##MasterOrData##_TABLES*>(0))->FieldName)-static_cast<char*>(0))/sizeof(USHORT)) 6486 6487 #define GET_COMMAND_TABLE_COMMANDSET_REVISION(TABLE_HEADER_OFFSET) (((static_cast<ATOM_COMMON_TABLE_HEADER*>(TABLE_HEADER_OFFSET))->ucTableFormatRevision )&0x3F) 6488 #define GET_COMMAND_TABLE_PARAMETER_REVISION(TABLE_HEADER_OFFSET) (((static_cast<ATOM_COMMON_TABLE_HEADER*>(TABLE_HEADER_OFFSET))->ucTableContentRevision)&0x3F) 6489 #else // not __cplusplus 6490 #define GetIndexIntoMasterTable(MasterOrData, FieldName) (((char*)(&((ATOM_MASTER_LIST_OF_##MasterOrData##_TABLES*)0)->FieldName)-(char*)0)/sizeof(USHORT)) 6491 6492 #define GET_COMMAND_TABLE_COMMANDSET_REVISION(TABLE_HEADER_OFFSET) ((((ATOM_COMMON_TABLE_HEADER*)TABLE_HEADER_OFFSET)->ucTableFormatRevision)&0x3F) 6493 #define GET_COMMAND_TABLE_PARAMETER_REVISION(TABLE_HEADER_OFFSET) ((((ATOM_COMMON_TABLE_HEADER*)TABLE_HEADER_OFFSET)->ucTableContentRevision)&0x3F) 6494 #endif // __cplusplus 6495 6496 #define GET_DATA_TABLE_MAJOR_REVISION GET_COMMAND_TABLE_COMMANDSET_REVISION 6497 #define GET_DATA_TABLE_MINOR_REVISION GET_COMMAND_TABLE_PARAMETER_REVISION 6498 6499 /****************************************************************************/ 6500 //Portion III: Definitinos only used in VBIOS 6501 /****************************************************************************/ 6502 #define ATOM_DAC_SRC 0x80 6503 #define ATOM_SRC_DAC1 0 6504 #define ATOM_SRC_DAC2 0x80 6505 6506 6507 6508 typedef struct _MEMORY_PLLINIT_PARAMETERS 6509 { 6510 ULONG ulTargetMemoryClock; //In 10Khz unit 6511 UCHAR ucAction; //not define yet 6512 UCHAR ucFbDiv_Hi; //Fbdiv Hi byte 6513 UCHAR ucFbDiv; //FB value 6514 UCHAR ucPostDiv; //Post div 6515 }MEMORY_PLLINIT_PARAMETERS; 6516 6517 #define MEMORY_PLLINIT_PS_ALLOCATION MEMORY_PLLINIT_PARAMETERS 6518 6519 6520 #define GPIO_PIN_WRITE 0x01 6521 #define GPIO_PIN_READ 0x00 6522 6523 typedef struct _GPIO_PIN_CONTROL_PARAMETERS 6524 { 6525 UCHAR ucGPIO_ID; //return value, read from GPIO pins 6526 UCHAR ucGPIOBitShift; //define which bit in uGPIOBitVal need to be update 6527 UCHAR ucGPIOBitVal; //Set/Reset corresponding bit defined in ucGPIOBitMask 6528 UCHAR ucAction; //=GPIO_PIN_WRITE: Read; =GPIO_PIN_READ: Write 6529 }GPIO_PIN_CONTROL_PARAMETERS; 6530 6531 typedef struct _ENABLE_SCALER_PARAMETERS 6532 { 6533 UCHAR ucScaler; // ATOM_SCALER1, ATOM_SCALER2 6534 UCHAR ucEnable; // ATOM_SCALER_DISABLE or ATOM_SCALER_CENTER or ATOM_SCALER_EXPANSION 6535 UCHAR ucTVStandard; // 6536 UCHAR ucPadding[1]; 6537 }ENABLE_SCALER_PARAMETERS; 6538 #define ENABLE_SCALER_PS_ALLOCATION ENABLE_SCALER_PARAMETERS 6539 6540 //ucEnable: 6541 #define SCALER_BYPASS_AUTO_CENTER_NO_REPLICATION 0 6542 #define SCALER_BYPASS_AUTO_CENTER_AUTO_REPLICATION 1 6543 #define SCALER_ENABLE_2TAP_ALPHA_MODE 2 6544 #define SCALER_ENABLE_MULTITAP_MODE 3 6545 6546 typedef struct _ENABLE_HARDWARE_ICON_CURSOR_PARAMETERS 6547 { 6548 ULONG usHWIconHorzVertPosn; // Hardware Icon Vertical position 6549 UCHAR ucHWIconVertOffset; // Hardware Icon Vertical offset 6550 UCHAR ucHWIconHorzOffset; // Hardware Icon Horizontal offset 6551 UCHAR ucSelection; // ATOM_CURSOR1 or ATOM_ICON1 or ATOM_CURSOR2 or ATOM_ICON2 6552 UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE 6553 }ENABLE_HARDWARE_ICON_CURSOR_PARAMETERS; 6554 6555 typedef struct _ENABLE_HARDWARE_ICON_CURSOR_PS_ALLOCATION 6556 { 6557 ENABLE_HARDWARE_ICON_CURSOR_PARAMETERS sEnableIcon; 6558 ENABLE_CRTC_PARAMETERS sReserved; 6559 }ENABLE_HARDWARE_ICON_CURSOR_PS_ALLOCATION; 6560 6561 typedef struct _ENABLE_GRAPH_SURFACE_PARAMETERS 6562 { 6563 USHORT usHight; // Image Hight 6564 USHORT usWidth; // Image Width 6565 UCHAR ucSurface; // Surface 1 or 2 6566 UCHAR ucPadding[3]; 6567 }ENABLE_GRAPH_SURFACE_PARAMETERS; 6568 6569 typedef struct _ENABLE_GRAPH_SURFACE_PARAMETERS_V1_2 6570 { 6571 USHORT usHight; // Image Hight 6572 USHORT usWidth; // Image Width 6573 UCHAR ucSurface; // Surface 1 or 2 6574 UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE 6575 UCHAR ucPadding[2]; 6576 }ENABLE_GRAPH_SURFACE_PARAMETERS_V1_2; 6577 6578 typedef struct _ENABLE_GRAPH_SURFACE_PARAMETERS_V1_3 6579 { 6580 USHORT usHight; // Image Hight 6581 USHORT usWidth; // Image Width 6582 UCHAR ucSurface; // Surface 1 or 2 6583 UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE 6584 USHORT usDeviceId; // Active Device Id for this surface. If no device, set to 0. 6585 }ENABLE_GRAPH_SURFACE_PARAMETERS_V1_3; 6586 6587 typedef struct _ENABLE_GRAPH_SURFACE_PARAMETERS_V1_4 6588 { 6589 USHORT usHight; // Image Hight 6590 USHORT usWidth; // Image Width 6591 USHORT usGraphPitch; 6592 UCHAR ucColorDepth; 6593 UCHAR ucPixelFormat; 6594 UCHAR ucSurface; // Surface 1 or 2 6595 UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE 6596 UCHAR ucModeType; 6597 UCHAR ucReserved; 6598 }ENABLE_GRAPH_SURFACE_PARAMETERS_V1_4; 6599 6600 // ucEnable 6601 #define ATOM_GRAPH_CONTROL_SET_PITCH 0x0f 6602 #define ATOM_GRAPH_CONTROL_SET_DISP_START 0x10 6603 6604 typedef struct _ENABLE_GRAPH_SURFACE_PS_ALLOCATION 6605 { 6606 ENABLE_GRAPH_SURFACE_PARAMETERS sSetSurface; 6607 ENABLE_YUV_PS_ALLOCATION sReserved; // Don't set this one 6608 }ENABLE_GRAPH_SURFACE_PS_ALLOCATION; 6609 6610 typedef struct _MEMORY_CLEAN_UP_PARAMETERS 6611 { 6612 USHORT usMemoryStart; //in 8Kb boundry, offset from memory base address 6613 USHORT usMemorySize; //8Kb blocks aligned 6614 }MEMORY_CLEAN_UP_PARAMETERS; 6615 6616 #define MEMORY_CLEAN_UP_PS_ALLOCATION MEMORY_CLEAN_UP_PARAMETERS 6617 6618 typedef struct _GET_DISPLAY_SURFACE_SIZE_PARAMETERS 6619 { 6620 USHORT usX_Size; //When use as input parameter, usX_Size indicates which CRTC 6621 USHORT usY_Size; 6622 }GET_DISPLAY_SURFACE_SIZE_PARAMETERS; 6623 6624 typedef struct _GET_DISPLAY_SURFACE_SIZE_PARAMETERS_V2 6625 { 6626 union{ 6627 USHORT usX_Size; //When use as input parameter, usX_Size indicates which CRTC 6628 USHORT usSurface; 6629 }; 6630 USHORT usY_Size; 6631 USHORT usDispXStart; 6632 USHORT usDispYStart; 6633 }GET_DISPLAY_SURFACE_SIZE_PARAMETERS_V2; 6634 6635 6636 typedef struct _PALETTE_DATA_CONTROL_PARAMETERS_V3 6637 { 6638 UCHAR ucLutId; 6639 UCHAR ucAction; 6640 USHORT usLutStartIndex; 6641 USHORT usLutLength; 6642 USHORT usLutOffsetInVram; 6643 }PALETTE_DATA_CONTROL_PARAMETERS_V3; 6644 6645 // ucAction: 6646 #define PALETTE_DATA_AUTO_FILL 1 6647 #define PALETTE_DATA_READ 2 6648 #define PALETTE_DATA_WRITE 3 6649 6650 6651 typedef struct _INTERRUPT_SERVICE_PARAMETERS_V2 6652 { 6653 UCHAR ucInterruptId; 6654 UCHAR ucServiceId; 6655 UCHAR ucStatus; 6656 UCHAR ucReserved; 6657 }INTERRUPT_SERVICE_PARAMETER_V2; 6658 6659 // ucInterruptId 6660 #define HDP1_INTERRUPT_ID 1 6661 #define HDP2_INTERRUPT_ID 2 6662 #define HDP3_INTERRUPT_ID 3 6663 #define HDP4_INTERRUPT_ID 4 6664 #define HDP5_INTERRUPT_ID 5 6665 #define HDP6_INTERRUPT_ID 6 6666 #define SW_INTERRUPT_ID 11 6667 6668 // ucAction 6669 #define INTERRUPT_SERVICE_GEN_SW_INT 1 6670 #define INTERRUPT_SERVICE_GET_STATUS 2 6671 6672 // ucStatus 6673 #define INTERRUPT_STATUS__INT_TRIGGER 1 6674 #define INTERRUPT_STATUS__HPD_HIGH 2 6675 6676 typedef struct _EFUSE_INPUT_PARAMETER 6677 { 6678 USHORT usEfuseIndex; 6679 UCHAR ucBitShift; 6680 UCHAR ucBitLength; 6681 }EFUSE_INPUT_PARAMETER; 6682 6683 // ReadEfuseValue command table input/output parameter 6684 typedef union _READ_EFUSE_VALUE_PARAMETER 6685 { 6686 EFUSE_INPUT_PARAMETER sEfuse; 6687 ULONG ulEfuseValue; 6688 }READ_EFUSE_VALUE_PARAMETER; 6689 6690 typedef struct _INDIRECT_IO_ACCESS 6691 { 6692 ATOM_COMMON_TABLE_HEADER sHeader; 6693 UCHAR IOAccessSequence[256]; 6694 } INDIRECT_IO_ACCESS; 6695 6696 #define INDIRECT_READ 0x00 6697 #define INDIRECT_WRITE 0x80 6698 6699 #define INDIRECT_IO_MM 0 6700 #define INDIRECT_IO_PLL 1 6701 #define INDIRECT_IO_MC 2 6702 #define INDIRECT_IO_PCIE 3 6703 #define INDIRECT_IO_PCIEP 4 6704 #define INDIRECT_IO_NBMISC 5 6705 #define INDIRECT_IO_SMU 5 6706 6707 #define INDIRECT_IO_PLL_READ INDIRECT_IO_PLL | INDIRECT_READ 6708 #define INDIRECT_IO_PLL_WRITE INDIRECT_IO_PLL | INDIRECT_WRITE 6709 #define INDIRECT_IO_MC_READ INDIRECT_IO_MC | INDIRECT_READ 6710 #define INDIRECT_IO_MC_WRITE INDIRECT_IO_MC | INDIRECT_WRITE 6711 #define INDIRECT_IO_PCIE_READ INDIRECT_IO_PCIE | INDIRECT_READ 6712 #define INDIRECT_IO_PCIE_WRITE INDIRECT_IO_PCIE | INDIRECT_WRITE 6713 #define INDIRECT_IO_PCIEP_READ INDIRECT_IO_PCIEP | INDIRECT_READ 6714 #define INDIRECT_IO_PCIEP_WRITE INDIRECT_IO_PCIEP | INDIRECT_WRITE 6715 #define INDIRECT_IO_NBMISC_READ INDIRECT_IO_NBMISC | INDIRECT_READ 6716 #define INDIRECT_IO_NBMISC_WRITE INDIRECT_IO_NBMISC | INDIRECT_WRITE 6717 #define INDIRECT_IO_SMU_READ INDIRECT_IO_SMU | INDIRECT_READ 6718 #define INDIRECT_IO_SMU_WRITE INDIRECT_IO_SMU | INDIRECT_WRITE 6719 6720 6721 typedef struct _ATOM_OEM_INFO 6722 { 6723 ATOM_COMMON_TABLE_HEADER sHeader; 6724 ATOM_I2C_ID_CONFIG_ACCESS sucI2cId; 6725 }ATOM_OEM_INFO; 6726 6727 typedef struct _ATOM_TV_MODE 6728 { 6729 UCHAR ucVMode_Num; //Video mode number 6730 UCHAR ucTV_Mode_Num; //Internal TV mode number 6731 }ATOM_TV_MODE; 6732 6733 typedef struct _ATOM_BIOS_INT_TVSTD_MODE 6734 { 6735 ATOM_COMMON_TABLE_HEADER sHeader; 6736 USHORT usTV_Mode_LUT_Offset; // Pointer to standard to internal number conversion table 6737 USHORT usTV_FIFO_Offset; // Pointer to FIFO entry table 6738 USHORT usNTSC_Tbl_Offset; // Pointer to SDTV_Mode_NTSC table 6739 USHORT usPAL_Tbl_Offset; // Pointer to SDTV_Mode_PAL table 6740 USHORT usCV_Tbl_Offset; // Pointer to SDTV_Mode_PAL table 6741 }ATOM_BIOS_INT_TVSTD_MODE; 6742 6743 6744 typedef struct _ATOM_TV_MODE_SCALER_PTR 6745 { 6746 USHORT ucFilter0_Offset; //Pointer to filter format 0 coefficients 6747 USHORT usFilter1_Offset; //Pointer to filter format 0 coefficients 6748 UCHAR ucTV_Mode_Num; 6749 }ATOM_TV_MODE_SCALER_PTR; 6750 6751 typedef struct _ATOM_STANDARD_VESA_TIMING 6752 { 6753 ATOM_COMMON_TABLE_HEADER sHeader; 6754 ATOM_DTD_FORMAT aModeTimings[16]; // 16 is not the real array number, just for initial allocation 6755 }ATOM_STANDARD_VESA_TIMING; 6756 6757 6758 typedef struct _ATOM_STD_FORMAT 6759 { 6760 USHORT usSTD_HDisp; 6761 USHORT usSTD_VDisp; 6762 USHORT usSTD_RefreshRate; 6763 USHORT usReserved; 6764 }ATOM_STD_FORMAT; 6765 6766 typedef struct _ATOM_VESA_TO_EXTENDED_MODE 6767 { 6768 USHORT usVESA_ModeNumber; 6769 USHORT usExtendedModeNumber; 6770 }ATOM_VESA_TO_EXTENDED_MODE; 6771 6772 typedef struct _ATOM_VESA_TO_INTENAL_MODE_LUT 6773 { 6774 ATOM_COMMON_TABLE_HEADER sHeader; 6775 ATOM_VESA_TO_EXTENDED_MODE asVESA_ToExtendedModeInfo[76]; 6776 }ATOM_VESA_TO_INTENAL_MODE_LUT; 6777 6778 /*************** ATOM Memory Related Data Structure ***********************/ 6779 typedef struct _ATOM_MEMORY_VENDOR_BLOCK{ 6780 UCHAR ucMemoryType; 6781 UCHAR ucMemoryVendor; 6782 UCHAR ucAdjMCId; 6783 UCHAR ucDynClkId; 6784 ULONG ulDllResetClkRange; 6785 }ATOM_MEMORY_VENDOR_BLOCK; 6786 6787 6788 typedef struct _ATOM_MEMORY_SETTING_ID_CONFIG{ 6789 #if ATOM_BIG_ENDIAN 6790 ULONG ucMemBlkId:8; 6791 ULONG ulMemClockRange:24; 6792 #else 6793 ULONG ulMemClockRange:24; 6794 ULONG ucMemBlkId:8; 6795 #endif 6796 }ATOM_MEMORY_SETTING_ID_CONFIG; 6797 6798 typedef union _ATOM_MEMORY_SETTING_ID_CONFIG_ACCESS 6799 { 6800 ATOM_MEMORY_SETTING_ID_CONFIG slAccess; 6801 ULONG ulAccess; 6802 }ATOM_MEMORY_SETTING_ID_CONFIG_ACCESS; 6803 6804 6805 typedef struct _ATOM_MEMORY_SETTING_DATA_BLOCK{ 6806 ATOM_MEMORY_SETTING_ID_CONFIG_ACCESS ulMemoryID; 6807 ULONG aulMemData[1]; 6808 }ATOM_MEMORY_SETTING_DATA_BLOCK; 6809 6810 6811 typedef struct _ATOM_INIT_REG_INDEX_FORMAT{ 6812 USHORT usRegIndex; // MC register index 6813 UCHAR ucPreRegDataLength; // offset in ATOM_INIT_REG_DATA_BLOCK.saRegDataBuf 6814 }ATOM_INIT_REG_INDEX_FORMAT; 6815 6816 6817 typedef struct _ATOM_INIT_REG_BLOCK{ 6818 USHORT usRegIndexTblSize; //size of asRegIndexBuf 6819 USHORT usRegDataBlkSize; //size of ATOM_MEMORY_SETTING_DATA_BLOCK 6820 ATOM_INIT_REG_INDEX_FORMAT asRegIndexBuf[1]; 6821 ATOM_MEMORY_SETTING_DATA_BLOCK asRegDataBuf[1]; 6822 }ATOM_INIT_REG_BLOCK; 6823 6824 #define END_OF_REG_INDEX_BLOCK 0x0ffff 6825 #define END_OF_REG_DATA_BLOCK 0x00000000 6826 #define ATOM_INIT_REG_MASK_FLAG 0x80 //Not used in BIOS 6827 #define CLOCK_RANGE_HIGHEST 0x00ffffff 6828 6829 #define VALUE_DWORD SIZEOF ULONG 6830 #define VALUE_SAME_AS_ABOVE 0 6831 #define VALUE_MASK_DWORD 0x84 6832 6833 #define INDEX_ACCESS_RANGE_BEGIN (VALUE_DWORD + 1) 6834 #define INDEX_ACCESS_RANGE_END (INDEX_ACCESS_RANGE_BEGIN + 1) 6835 #define VALUE_INDEX_ACCESS_SINGLE (INDEX_ACCESS_RANGE_END + 1) 6836 //#define ACCESS_MCIODEBUGIND 0x40 //defined in BIOS code 6837 #define ACCESS_PLACEHOLDER 0x80 6838 6839 6840 typedef struct _ATOM_MC_INIT_PARAM_TABLE 6841 { 6842 ATOM_COMMON_TABLE_HEADER sHeader; 6843 USHORT usAdjustARB_SEQDataOffset; 6844 USHORT usMCInitMemTypeTblOffset; 6845 USHORT usMCInitCommonTblOffset; 6846 USHORT usMCInitPowerDownTblOffset; 6847 ULONG ulARB_SEQDataBuf[32]; 6848 ATOM_INIT_REG_BLOCK asMCInitMemType; 6849 ATOM_INIT_REG_BLOCK asMCInitCommon; 6850 }ATOM_MC_INIT_PARAM_TABLE; 6851 6852 6853 typedef struct _ATOM_REG_INIT_SETTING 6854 { 6855 USHORT usRegIndex; 6856 ULONG ulRegValue; 6857 }ATOM_REG_INIT_SETTING; 6858 6859 typedef struct _ATOM_MC_INIT_PARAM_TABLE_V2_1 6860 { 6861 ATOM_COMMON_TABLE_HEADER sHeader; 6862 ULONG ulMCUcodeVersion; 6863 ULONG ulMCUcodeRomStartAddr; 6864 ULONG ulMCUcodeLength; 6865 USHORT usMcRegInitTableOffset; // offset of ATOM_REG_INIT_SETTING array for MC core register settings. 6866 USHORT usReserved; // offset of ATOM_INIT_REG_BLOCK for MC SEQ/PHY register setting 6867 }ATOM_MC_INIT_PARAM_TABLE_V2_1; 6868 6869 6870 #define _4Mx16 0x2 6871 #define _4Mx32 0x3 6872 #define _8Mx16 0x12 6873 #define _8Mx32 0x13 6874 #define _8Mx128 0x15 6875 #define _16Mx16 0x22 6876 #define _16Mx32 0x23 6877 #define _16Mx128 0x25 6878 #define _32Mx16 0x32 6879 #define _32Mx32 0x33 6880 #define _32Mx128 0x35 6881 #define _64Mx32 0x43 6882 #define _64Mx8 0x41 6883 #define _64Mx16 0x42 6884 #define _128Mx8 0x51 6885 #define _128Mx16 0x52 6886 #define _128Mx32 0x53 6887 #define _256Mx8 0x61 6888 #define _256Mx16 0x62 6889 #define _512Mx8 0x71 6890 6891 6892 #define SAMSUNG 0x1 6893 #define INFINEON 0x2 6894 #define ELPIDA 0x3 6895 #define ETRON 0x4 6896 #define NANYA 0x5 6897 #define HYNIX 0x6 6898 #define MOSEL 0x7 6899 #define WINBOND 0x8 6900 #define ESMT 0x9 6901 #define MICRON 0xF 6902 6903 #define QIMONDA INFINEON 6904 #define PROMOS MOSEL 6905 #define KRETON INFINEON 6906 #define ELIXIR NANYA 6907 #define MEZZA ELPIDA 6908 6909 6910 /////////////Support for GDDR5 MC uCode to reside in upper 64K of ROM///////////// 6911 6912 #define UCODE_ROM_START_ADDRESS 0x1b800 6913 #define UCODE_SIGNATURE 0x4375434d // 'MCuC' - MC uCode 6914 6915 //uCode block header for reference 6916 6917 typedef struct _MCuCodeHeader 6918 { 6919 ULONG ulSignature; 6920 UCHAR ucRevision; 6921 UCHAR ucChecksum; 6922 UCHAR ucReserved1; 6923 UCHAR ucReserved2; 6924 USHORT usParametersLength; 6925 USHORT usUCodeLength; 6926 USHORT usReserved1; 6927 USHORT usReserved2; 6928 } MCuCodeHeader; 6929 6930 ////////////////////////////////////////////////////////////////////////////////// 6931 6932 #define ATOM_MAX_NUMBER_OF_VRAM_MODULE 16 6933 6934 #define ATOM_VRAM_MODULE_MEMORY_VENDOR_ID_MASK 0xF 6935 typedef struct _ATOM_VRAM_MODULE_V1 6936 { 6937 ULONG ulReserved; 6938 USHORT usEMRSValue; 6939 USHORT usMRSValue; 6940 USHORT usReserved; 6941 UCHAR ucExtMemoryID; // An external indicator (by hardcode, callback or pin) to tell what is the current memory module 6942 UCHAR ucMemoryType; // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4;[3:0] reserved; 6943 UCHAR ucMemoryVenderID; // Predefined,never change across designs or memory type/vender 6944 UCHAR ucMemoryDeviceCfg; // [7:4]=0x0:4M;=0x1:8M;=0x2:16M;0x3:32M....[3:0]=0x0:x4;=0x1:x8;=0x2:x16;=0x3:x32... 6945 UCHAR ucRow; // Number of Row,in power of 2; 6946 UCHAR ucColumn; // Number of Column,in power of 2; 6947 UCHAR ucBank; // Nunber of Bank; 6948 UCHAR ucRank; // Number of Rank, in power of 2 6949 UCHAR ucChannelNum; // Number of channel; 6950 UCHAR ucChannelConfig; // [3:0]=Indication of what channel combination;[4:7]=Channel bit width, in number of 2 6951 UCHAR ucDefaultMVDDQ_ID; // Default MVDDQ setting for this memory block, ID linking to MVDDQ info table to find real set-up data; 6952 UCHAR ucDefaultMVDDC_ID; // Default MVDDC setting for this memory block, ID linking to MVDDC info table to find real set-up data; 6953 UCHAR ucReserved[2]; 6954 }ATOM_VRAM_MODULE_V1; 6955 6956 6957 typedef struct _ATOM_VRAM_MODULE_V2 6958 { 6959 ULONG ulReserved; 6960 ULONG ulFlags; // To enable/disable functionalities based on memory type 6961 ULONG ulEngineClock; // Override of default engine clock for particular memory type 6962 ULONG ulMemoryClock; // Override of default memory clock for particular memory type 6963 USHORT usEMRS2Value; // EMRS2 Value is used for GDDR2 and GDDR4 memory type 6964 USHORT usEMRS3Value; // EMRS3 Value is used for GDDR2 and GDDR4 memory type 6965 USHORT usEMRSValue; 6966 USHORT usMRSValue; 6967 USHORT usReserved; 6968 UCHAR ucExtMemoryID; // An external indicator (by hardcode, callback or pin) to tell what is the current memory module 6969 UCHAR ucMemoryType; // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4;[3:0] - must not be used for now; 6970 UCHAR ucMemoryVenderID; // Predefined,never change across designs or memory type/vender. If not predefined, vendor detection table gets executed 6971 UCHAR ucMemoryDeviceCfg; // [7:4]=0x0:4M;=0x1:8M;=0x2:16M;0x3:32M....[3:0]=0x0:x4;=0x1:x8;=0x2:x16;=0x3:x32... 6972 UCHAR ucRow; // Number of Row,in power of 2; 6973 UCHAR ucColumn; // Number of Column,in power of 2; 6974 UCHAR ucBank; // Nunber of Bank; 6975 UCHAR ucRank; // Number of Rank, in power of 2 6976 UCHAR ucChannelNum; // Number of channel; 6977 UCHAR ucChannelConfig; // [3:0]=Indication of what channel combination;[4:7]=Channel bit width, in number of 2 6978 UCHAR ucDefaultMVDDQ_ID; // Default MVDDQ setting for this memory block, ID linking to MVDDQ info table to find real set-up data; 6979 UCHAR ucDefaultMVDDC_ID; // Default MVDDC setting for this memory block, ID linking to MVDDC info table to find real set-up data; 6980 UCHAR ucRefreshRateFactor; 6981 UCHAR ucReserved[3]; 6982 }ATOM_VRAM_MODULE_V2; 6983 6984 6985 typedef struct _ATOM_MEMORY_TIMING_FORMAT 6986 { 6987 ULONG ulClkRange; // memory clock in 10kHz unit, when target memory clock is below this clock, use this memory timing 6988 union{ 6989 USHORT usMRS; // mode register 6990 USHORT usDDR3_MR0; 6991 }; 6992 union{ 6993 USHORT usEMRS; // extended mode register 6994 USHORT usDDR3_MR1; 6995 }; 6996 UCHAR ucCL; // CAS latency 6997 UCHAR ucWL; // WRITE Latency 6998 UCHAR uctRAS; // tRAS 6999 UCHAR uctRC; // tRC 7000 UCHAR uctRFC; // tRFC 7001 UCHAR uctRCDR; // tRCDR 7002 UCHAR uctRCDW; // tRCDW 7003 UCHAR uctRP; // tRP 7004 UCHAR uctRRD; // tRRD 7005 UCHAR uctWR; // tWR 7006 UCHAR uctWTR; // tWTR 7007 UCHAR uctPDIX; // tPDIX 7008 UCHAR uctFAW; // tFAW 7009 UCHAR uctAOND; // tAOND 7010 union 7011 { 7012 struct { 7013 UCHAR ucflag; // flag to control memory timing calculation. bit0= control EMRS2 Infineon 7014 UCHAR ucReserved; 7015 }; 7016 USHORT usDDR3_MR2; 7017 }; 7018 }ATOM_MEMORY_TIMING_FORMAT; 7019 7020 7021 typedef struct _ATOM_MEMORY_TIMING_FORMAT_V1 7022 { 7023 ULONG ulClkRange; // memory clock in 10kHz unit, when target memory clock is below this clock, use this memory timing 7024 USHORT usMRS; // mode register 7025 USHORT usEMRS; // extended mode register 7026 UCHAR ucCL; // CAS latency 7027 UCHAR ucWL; // WRITE Latency 7028 UCHAR uctRAS; // tRAS 7029 UCHAR uctRC; // tRC 7030 UCHAR uctRFC; // tRFC 7031 UCHAR uctRCDR; // tRCDR 7032 UCHAR uctRCDW; // tRCDW 7033 UCHAR uctRP; // tRP 7034 UCHAR uctRRD; // tRRD 7035 UCHAR uctWR; // tWR 7036 UCHAR uctWTR; // tWTR 7037 UCHAR uctPDIX; // tPDIX 7038 UCHAR uctFAW; // tFAW 7039 UCHAR uctAOND; // tAOND 7040 UCHAR ucflag; // flag to control memory timing calculation. bit0= control EMRS2 Infineon 7041 ////////////////////////////////////GDDR parameters/////////////////////////////////// 7042 UCHAR uctCCDL; // 7043 UCHAR uctCRCRL; // 7044 UCHAR uctCRCWL; // 7045 UCHAR uctCKE; // 7046 UCHAR uctCKRSE; // 7047 UCHAR uctCKRSX; // 7048 UCHAR uctFAW32; // 7049 UCHAR ucMR5lo; // 7050 UCHAR ucMR5hi; // 7051 UCHAR ucTerminator; 7052 }ATOM_MEMORY_TIMING_FORMAT_V1; 7053 7054 7055 7056 7057 typedef struct _ATOM_MEMORY_TIMING_FORMAT_V2 7058 { 7059 ULONG ulClkRange; // memory clock in 10kHz unit, when target memory clock is below this clock, use this memory timing 7060 USHORT usMRS; // mode register 7061 USHORT usEMRS; // extended mode register 7062 UCHAR ucCL; // CAS latency 7063 UCHAR ucWL; // WRITE Latency 7064 UCHAR uctRAS; // tRAS 7065 UCHAR uctRC; // tRC 7066 UCHAR uctRFC; // tRFC 7067 UCHAR uctRCDR; // tRCDR 7068 UCHAR uctRCDW; // tRCDW 7069 UCHAR uctRP; // tRP 7070 UCHAR uctRRD; // tRRD 7071 UCHAR uctWR; // tWR 7072 UCHAR uctWTR; // tWTR 7073 UCHAR uctPDIX; // tPDIX 7074 UCHAR uctFAW; // tFAW 7075 UCHAR uctAOND; // tAOND 7076 UCHAR ucflag; // flag to control memory timing calculation. bit0= control EMRS2 Infineon 7077 ////////////////////////////////////GDDR parameters/////////////////////////////////// 7078 UCHAR uctCCDL; // 7079 UCHAR uctCRCRL; // 7080 UCHAR uctCRCWL; // 7081 UCHAR uctCKE; // 7082 UCHAR uctCKRSE; // 7083 UCHAR uctCKRSX; // 7084 UCHAR uctFAW32; // 7085 UCHAR ucMR4lo; // 7086 UCHAR ucMR4hi; // 7087 UCHAR ucMR5lo; // 7088 UCHAR ucMR5hi; // 7089 UCHAR ucTerminator; 7090 UCHAR ucReserved; 7091 }ATOM_MEMORY_TIMING_FORMAT_V2; 7092 7093 7094 typedef struct _ATOM_MEMORY_FORMAT 7095 { 7096 ULONG ulDllDisClock; // memory DLL will be disable when target memory clock is below this clock 7097 union{ 7098 USHORT usEMRS2Value; // EMRS2 Value is used for GDDR2 and GDDR4 memory type 7099 USHORT usDDR3_Reserved; // Not used for DDR3 memory 7100 }; 7101 union{ 7102 USHORT usEMRS3Value; // EMRS3 Value is used for GDDR2 and GDDR4 memory type 7103 USHORT usDDR3_MR3; // Used for DDR3 memory 7104 }; 7105 UCHAR ucMemoryType; // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4;[3:0] - must not be used for now; 7106 UCHAR ucMemoryVenderID; // Predefined,never change across designs or memory type/vender. If not predefined, vendor detection table gets executed 7107 UCHAR ucRow; // Number of Row,in power of 2; 7108 UCHAR ucColumn; // Number of Column,in power of 2; 7109 UCHAR ucBank; // Nunber of Bank; 7110 UCHAR ucRank; // Number of Rank, in power of 2 7111 UCHAR ucBurstSize; // burst size, 0= burst size=4 1= burst size=8 7112 UCHAR ucDllDisBit; // position of DLL Enable/Disable bit in EMRS ( Extended Mode Register ) 7113 UCHAR ucRefreshRateFactor; // memory refresh rate in unit of ms 7114 UCHAR ucDensity; // _8Mx32, _16Mx32, _16Mx16, _32Mx16 7115 UCHAR ucPreamble; // [7:4] Write Preamble, [3:0] Read Preamble 7116 UCHAR ucMemAttrib; // Memory Device Addribute, like RDBI/WDBI etc 7117 ATOM_MEMORY_TIMING_FORMAT asMemTiming[5]; // Memory Timing block sort from lower clock to higher clock 7118 }ATOM_MEMORY_FORMAT; 7119 7120 7121 typedef struct _ATOM_VRAM_MODULE_V3 7122 { 7123 ULONG ulChannelMapCfg; // board dependent paramenter:Channel combination 7124 USHORT usSize; // size of ATOM_VRAM_MODULE_V3 7125 USHORT usDefaultMVDDQ; // board dependent parameter:Default Memory Core Voltage 7126 USHORT usDefaultMVDDC; // board dependent parameter:Default Memory IO Voltage 7127 UCHAR ucExtMemoryID; // An external indicator (by hardcode, callback or pin) to tell what is the current memory module 7128 UCHAR ucChannelNum; // board dependent parameter:Number of channel; 7129 UCHAR ucChannelSize; // board dependent parameter:32bit or 64bit 7130 UCHAR ucVREFI; // board dependnt parameter: EXT or INT +160mv to -140mv 7131 UCHAR ucNPL_RT; // board dependent parameter:NPL round trip delay, used for calculate memory timing parameters 7132 UCHAR ucFlag; // To enable/disable functionalities based on memory type 7133 ATOM_MEMORY_FORMAT asMemory; // describ all of video memory parameters from memory spec 7134 }ATOM_VRAM_MODULE_V3; 7135 7136 7137 //ATOM_VRAM_MODULE_V3.ucNPL_RT 7138 #define NPL_RT_MASK 0x0f 7139 #define BATTERY_ODT_MASK 0xc0 7140 7141 #define ATOM_VRAM_MODULE ATOM_VRAM_MODULE_V3 7142 7143 typedef struct _ATOM_VRAM_MODULE_V4 7144 { 7145 ULONG ulChannelMapCfg; // board dependent parameter: Channel combination 7146 USHORT usModuleSize; // size of ATOM_VRAM_MODULE_V4, make it easy for VBIOS to look for next entry of VRAM_MODULE 7147 USHORT usPrivateReserved; // BIOS internal reserved space to optimize code size, updated by the compiler, shouldn't be modified manually!! 7148 // MC_ARB_RAMCFG (includes NOOFBANK,NOOFRANKS,NOOFROWS,NOOFCOLS) 7149 USHORT usReserved; 7150 UCHAR ucExtMemoryID; // An external indicator (by hardcode, callback or pin) to tell what is the current memory module 7151 UCHAR ucMemoryType; // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4; 0x5:DDR5 [3:0] - Must be 0x0 for now; 7152 UCHAR ucChannelNum; // Number of channels present in this module config 7153 UCHAR ucChannelWidth; // 0 - 32 bits; 1 - 64 bits 7154 UCHAR ucDensity; // _8Mx32, _16Mx32, _16Mx16, _32Mx16 7155 UCHAR ucFlag; // To enable/disable functionalities based on memory type 7156 UCHAR ucMisc; // bit0: 0 - single rank; 1 - dual rank; bit2: 0 - burstlength 4, 1 - burstlength 8 7157 UCHAR ucVREFI; // board dependent parameter 7158 UCHAR ucNPL_RT; // board dependent parameter:NPL round trip delay, used for calculate memory timing parameters 7159 UCHAR ucPreamble; // [7:4] Write Preamble, [3:0] Read Preamble 7160 UCHAR ucMemorySize; // BIOS internal reserved space to optimize code size, updated by the compiler, shouldn't be modified manually!! 7161 // Total memory size in unit of 16MB for CONFIG_MEMSIZE - bit[23:0] zeros 7162 UCHAR ucReserved[3]; 7163 7164 //compare with V3, we flat the struct by merging ATOM_MEMORY_FORMAT (as is) into V4 as the same level 7165 union{ 7166 USHORT usEMRS2Value; // EMRS2 Value is used for GDDR2 and GDDR4 memory type 7167 USHORT usDDR3_Reserved; 7168 }; 7169 union{ 7170 USHORT usEMRS3Value; // EMRS3 Value is used for GDDR2 and GDDR4 memory type 7171 USHORT usDDR3_MR3; // Used for DDR3 memory 7172 }; 7173 UCHAR ucMemoryVenderID; // Predefined, If not predefined, vendor detection table gets executed 7174 UCHAR ucRefreshRateFactor; // [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64ms) 7175 UCHAR ucReserved2[2]; 7176 ATOM_MEMORY_TIMING_FORMAT asMemTiming[5];//Memory Timing block sort from lower clock to higher clock 7177 }ATOM_VRAM_MODULE_V4; 7178 7179 #define VRAM_MODULE_V4_MISC_RANK_MASK 0x3 7180 #define VRAM_MODULE_V4_MISC_DUAL_RANK 0x1 7181 #define VRAM_MODULE_V4_MISC_BL_MASK 0x4 7182 #define VRAM_MODULE_V4_MISC_BL8 0x4 7183 #define VRAM_MODULE_V4_MISC_DUAL_CS 0x10 7184 7185 typedef struct _ATOM_VRAM_MODULE_V5 7186 { 7187 ULONG ulChannelMapCfg; // board dependent parameter: Channel combination 7188 USHORT usModuleSize; // size of ATOM_VRAM_MODULE_V4, make it easy for VBIOS to look for next entry of VRAM_MODULE 7189 USHORT usPrivateReserved; // BIOS internal reserved space to optimize code size, updated by the compiler, shouldn't be modified manually!! 7190 // MC_ARB_RAMCFG (includes NOOFBANK,NOOFRANKS,NOOFROWS,NOOFCOLS) 7191 USHORT usReserved; 7192 UCHAR ucExtMemoryID; // An external indicator (by hardcode, callback or pin) to tell what is the current memory module 7193 UCHAR ucMemoryType; // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4; 0x5:DDR5 [3:0] - Must be 0x0 for now; 7194 UCHAR ucChannelNum; // Number of channels present in this module config 7195 UCHAR ucChannelWidth; // 0 - 32 bits; 1 - 64 bits 7196 UCHAR ucDensity; // _8Mx32, _16Mx32, _16Mx16, _32Mx16 7197 UCHAR ucFlag; // To enable/disable functionalities based on memory type 7198 UCHAR ucMisc; // bit0: 0 - single rank; 1 - dual rank; bit2: 0 - burstlength 4, 1 - burstlength 8 7199 UCHAR ucVREFI; // board dependent parameter 7200 UCHAR ucNPL_RT; // board dependent parameter:NPL round trip delay, used for calculate memory timing parameters 7201 UCHAR ucPreamble; // [7:4] Write Preamble, [3:0] Read Preamble 7202 UCHAR ucMemorySize; // BIOS internal reserved space to optimize code size, updated by the compiler, shouldn't be modified manually!! 7203 // Total memory size in unit of 16MB for CONFIG_MEMSIZE - bit[23:0] zeros 7204 UCHAR ucReserved[3]; 7205 7206 //compare with V3, we flat the struct by merging ATOM_MEMORY_FORMAT (as is) into V4 as the same level 7207 USHORT usEMRS2Value; // EMRS2 Value is used for GDDR2 and GDDR4 memory type 7208 USHORT usEMRS3Value; // EMRS3 Value is used for GDDR2 and GDDR4 memory type 7209 UCHAR ucMemoryVenderID; // Predefined, If not predefined, vendor detection table gets executed 7210 UCHAR ucRefreshRateFactor; // [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64ms) 7211 UCHAR ucFIFODepth; // FIFO depth supposes to be detected during vendor detection, but if we dont do vendor detection we have to hardcode FIFO Depth 7212 UCHAR ucCDR_Bandwidth; // [0:3]=Read CDR bandwidth, [4:7] - Write CDR Bandwidth 7213 ATOM_MEMORY_TIMING_FORMAT_V1 asMemTiming[5];//Memory Timing block sort from lower clock to higher clock 7214 }ATOM_VRAM_MODULE_V5; 7215 7216 7217 typedef struct _ATOM_VRAM_MODULE_V6 7218 { 7219 ULONG ulChannelMapCfg; // board dependent parameter: Channel combination 7220 USHORT usModuleSize; // size of ATOM_VRAM_MODULE_V4, make it easy for VBIOS to look for next entry of VRAM_MODULE 7221 USHORT usPrivateReserved; // BIOS internal reserved space to optimize code size, updated by the compiler, shouldn't be modified manually!! 7222 // MC_ARB_RAMCFG (includes NOOFBANK,NOOFRANKS,NOOFROWS,NOOFCOLS) 7223 USHORT usReserved; 7224 UCHAR ucExtMemoryID; // An external indicator (by hardcode, callback or pin) to tell what is the current memory module 7225 UCHAR ucMemoryType; // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4; 0x5:DDR5 [3:0] - Must be 0x0 for now; 7226 UCHAR ucChannelNum; // Number of channels present in this module config 7227 UCHAR ucChannelWidth; // 0 - 32 bits; 1 - 64 bits 7228 UCHAR ucDensity; // _8Mx32, _16Mx32, _16Mx16, _32Mx16 7229 UCHAR ucFlag; // To enable/disable functionalities based on memory type 7230 UCHAR ucMisc; // bit0: 0 - single rank; 1 - dual rank; bit2: 0 - burstlength 4, 1 - burstlength 8 7231 UCHAR ucVREFI; // board dependent parameter 7232 UCHAR ucNPL_RT; // board dependent parameter:NPL round trip delay, used for calculate memory timing parameters 7233 UCHAR ucPreamble; // [7:4] Write Preamble, [3:0] Read Preamble 7234 UCHAR ucMemorySize; // BIOS internal reserved space to optimize code size, updated by the compiler, shouldn't be modified manually!! 7235 // Total memory size in unit of 16MB for CONFIG_MEMSIZE - bit[23:0] zeros 7236 UCHAR ucReserved[3]; 7237 7238 //compare with V3, we flat the struct by merging ATOM_MEMORY_FORMAT (as is) into V4 as the same level 7239 USHORT usEMRS2Value; // EMRS2 Value is used for GDDR2 and GDDR4 memory type 7240 USHORT usEMRS3Value; // EMRS3 Value is used for GDDR2 and GDDR4 memory type 7241 UCHAR ucMemoryVenderID; // Predefined, If not predefined, vendor detection table gets executed 7242 UCHAR ucRefreshRateFactor; // [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64ms) 7243 UCHAR ucFIFODepth; // FIFO depth supposes to be detected during vendor detection, but if we dont do vendor detection we have to hardcode FIFO Depth 7244 UCHAR ucCDR_Bandwidth; // [0:3]=Read CDR bandwidth, [4:7] - Write CDR Bandwidth 7245 ATOM_MEMORY_TIMING_FORMAT_V2 asMemTiming[5];//Memory Timing block sort from lower clock to higher clock 7246 }ATOM_VRAM_MODULE_V6; 7247 7248 typedef struct _ATOM_VRAM_MODULE_V7 7249 { 7250 // Design Specific Values 7251 ULONG ulChannelMapCfg; // mmMC_SHARED_CHREMAP 7252 USHORT usModuleSize; // Size of ATOM_VRAM_MODULE_V7 7253 USHORT usPrivateReserved; // MC_ARB_RAMCFG (includes NOOFBANK,NOOFRANKS,NOOFROWS,NOOFCOLS) 7254 USHORT usEnableChannels; // bit vector which indicate which channels are enabled 7255 UCHAR ucExtMemoryID; // Current memory module ID 7256 UCHAR ucMemoryType; // MEM_TYPE_DDR2/DDR3/GDDR3/GDDR5 7257 UCHAR ucChannelNum; // Number of mem. channels supported in this module 7258 UCHAR ucChannelWidth; // CHANNEL_16BIT/CHANNEL_32BIT/CHANNEL_64BIT 7259 UCHAR ucDensity; // _8Mx32, _16Mx32, _16Mx16, _32Mx16 7260 UCHAR ucReserve; // In MC7x, the lower 4 bits are used as bit8-11 of memory size. In other MC code, it's not used. 7261 UCHAR ucMisc; // RANK_OF_THISMEMORY etc. 7262 UCHAR ucVREFI; // Not used. 7263 UCHAR ucNPL_RT; // Round trip delay (MC_SEQ_CAS_TIMING [28:24]:TCL=CL+NPL_RT-2). Always 2. 7264 UCHAR ucPreamble; // [7:4] Write Preamble, [3:0] Read Preamble 7265 UCHAR ucMemorySize; // Total memory size in unit of 16MB for CONFIG_MEMSIZE - bit[23:0] zeros 7266 USHORT usSEQSettingOffset; 7267 UCHAR ucReserved; 7268 // Memory Module specific values 7269 USHORT usEMRS2Value; // EMRS2/MR2 Value. 7270 USHORT usEMRS3Value; // EMRS3/MR3 Value. 7271 UCHAR ucMemoryVenderID; // [7:4] Revision, [3:0] Vendor code 7272 UCHAR ucRefreshRateFactor; // [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64ms) 7273 UCHAR ucFIFODepth; // FIFO depth can be detected during vendor detection, here is hardcoded per memory 7274 UCHAR ucCDR_Bandwidth; // [0:3]=Read CDR bandwidth, [4:7] - Write CDR Bandwidth 7275 char strMemPNString[20]; // part number end with '0'. 7276 }ATOM_VRAM_MODULE_V7; 7277 7278 7279 typedef struct _ATOM_VRAM_MODULE_V8 7280 { 7281 // Design Specific Values 7282 ULONG ulChannelMapCfg; // mmMC_SHARED_CHREMAP 7283 USHORT usModuleSize; // Size of ATOM_VRAM_MODULE_V7 7284 USHORT usMcRamCfg; // MC_ARB_RAMCFG (includes NOOFBANK,NOOFRANKS,NOOFROWS,NOOFCOLS) 7285 USHORT usEnableChannels; // bit vector which indicate which channels are enabled 7286 UCHAR ucExtMemoryID; // Current memory module ID 7287 UCHAR ucMemoryType; // MEM_TYPE_DDR2/DDR3/GDDR3/GDDR5 7288 UCHAR ucChannelNum; // Number of mem. channels supported in this module 7289 UCHAR ucChannelWidth; // CHANNEL_16BIT/CHANNEL_32BIT/CHANNEL_64BIT 7290 UCHAR ucDensity; // _8Mx32, _16Mx32, _16Mx16, _32Mx16 7291 UCHAR ucBankCol; // bit[3:2]= BANK ( =2:16bank, =1:8bank, =0:4bank ) bit[1:0]=Col ( =2: 10 bit, =1:9bit, =0:8bit ) 7292 UCHAR ucMisc; // RANK_OF_THISMEMORY etc. 7293 UCHAR ucVREFI; // Not used. 7294 USHORT usReserved; // Not used 7295 USHORT usMemorySize; // Total memory size in unit of MB for CONFIG_MEMSIZE zeros 7296 UCHAR ucMcTunningSetId; // MC phy registers set per. 7297 UCHAR ucRowNum; 7298 // Memory Module specific values 7299 USHORT usEMRS2Value; // EMRS2/MR2 Value. 7300 USHORT usEMRS3Value; // EMRS3/MR3 Value. 7301 UCHAR ucMemoryVenderID; // [7:4] Revision, [3:0] Vendor code 7302 UCHAR ucRefreshRateFactor; // [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64ms) 7303 UCHAR ucFIFODepth; // FIFO depth can be detected during vendor detection, here is hardcoded per memory 7304 UCHAR ucCDR_Bandwidth; // [0:3]=Read CDR bandwidth, [4:7] - Write CDR Bandwidth 7305 7306 ULONG ulChannelMapCfg1; // channel mapping for channel8~15 7307 ULONG ulBankMapCfg; 7308 ULONG ulReserved; 7309 char strMemPNString[20]; // part number end with '0'. 7310 }ATOM_VRAM_MODULE_V8; 7311 7312 7313 typedef struct _ATOM_VRAM_INFO_V2 7314 { 7315 ATOM_COMMON_TABLE_HEADER sHeader; 7316 UCHAR ucNumOfVRAMModule; 7317 ATOM_VRAM_MODULE aVramInfo[ATOM_MAX_NUMBER_OF_VRAM_MODULE]; // just for allocation, real number of blocks is in ucNumOfVRAMModule; 7318 }ATOM_VRAM_INFO_V2; 7319 7320 typedef struct _ATOM_VRAM_INFO_V3 7321 { 7322 ATOM_COMMON_TABLE_HEADER sHeader; 7323 USHORT usMemAdjustTblOffset; // offset of ATOM_INIT_REG_BLOCK structure for memory vendor specific MC adjust setting 7324 USHORT usMemClkPatchTblOffset; // offset of ATOM_INIT_REG_BLOCK structure for memory clock specific MC setting 7325 USHORT usRerseved; 7326 UCHAR aVID_PinsShift[9]; // 8 bit strap maximum+terminator 7327 UCHAR ucNumOfVRAMModule; 7328 ATOM_VRAM_MODULE aVramInfo[ATOM_MAX_NUMBER_OF_VRAM_MODULE]; // just for allocation, real number of blocks is in ucNumOfVRAMModule; 7329 ATOM_INIT_REG_BLOCK asMemPatch; // for allocation 7330 7331 }ATOM_VRAM_INFO_V3; 7332 7333 #define ATOM_VRAM_INFO_LAST ATOM_VRAM_INFO_V3 7334 7335 typedef struct _ATOM_VRAM_INFO_V4 7336 { 7337 ATOM_COMMON_TABLE_HEADER sHeader; 7338 USHORT usMemAdjustTblOffset; // offset of ATOM_INIT_REG_BLOCK structure for memory vendor specific MC adjust setting 7339 USHORT usMemClkPatchTblOffset; // offset of ATOM_INIT_REG_BLOCK structure for memory clock specific MC setting 7340 USHORT usRerseved; 7341 UCHAR ucMemDQ7_0ByteRemap; // DQ line byte remap, =0: Memory Data line BYTE0, =1: BYTE1, =2: BYTE2, =3: BYTE3 7342 ULONG ulMemDQ7_0BitRemap; // each DQ line ( 7~0) use 3bits, like: DQ0=Bit[2:0], DQ1:[5:3], ... DQ7:[23:21] 7343 UCHAR ucReservde[4]; 7344 UCHAR ucNumOfVRAMModule; 7345 ATOM_VRAM_MODULE_V4 aVramInfo[ATOM_MAX_NUMBER_OF_VRAM_MODULE]; // just for allocation, real number of blocks is in ucNumOfVRAMModule; 7346 ATOM_INIT_REG_BLOCK asMemPatch; // for allocation 7347 }ATOM_VRAM_INFO_V4; 7348 7349 typedef struct _ATOM_VRAM_INFO_HEADER_V2_1 7350 { 7351 ATOM_COMMON_TABLE_HEADER sHeader; 7352 USHORT usMemAdjustTblOffset; // offset of ATOM_INIT_REG_BLOCK structure for memory vendor specific MC adjust setting 7353 USHORT usMemClkPatchTblOffset; // offset of ATOM_INIT_REG_BLOCK structure for memory clock specific MC setting 7354 USHORT usPerBytePresetOffset; // offset of ATOM_INIT_REG_BLOCK structure for Per Byte Offset Preset Settings 7355 USHORT usReserved[3]; 7356 UCHAR ucNumOfVRAMModule; // indicate number of VRAM module 7357 UCHAR ucMemoryClkPatchTblVer; // version of memory AC timing register list 7358 UCHAR ucVramModuleVer; // indicate ATOM_VRAM_MODUE version 7359 UCHAR ucReserved; 7360 ATOM_VRAM_MODULE_V7 aVramInfo[ATOM_MAX_NUMBER_OF_VRAM_MODULE]; // just for allocation, real number of blocks is in ucNumOfVRAMModule; 7361 }ATOM_VRAM_INFO_HEADER_V2_1; 7362 7363 typedef struct _ATOM_VRAM_INFO_HEADER_V2_2 7364 { 7365 ATOM_COMMON_TABLE_HEADER sHeader; 7366 USHORT usMemAdjustTblOffset; // offset of ATOM_INIT_REG_BLOCK structure for memory vendor specific MC adjust setting 7367 USHORT usMemClkPatchTblOffset; // offset of ATOM_INIT_REG_BLOCK structure for memory clock specific MC setting 7368 USHORT usMcAdjustPerTileTblOffset; // offset of ATOM_INIT_REG_BLOCK structure for Per Byte Offset Preset Settings 7369 USHORT usMcPhyInitTableOffset; // offset of ATOM_INIT_REG_BLOCK structure for MC phy init set 7370 USHORT usDramDataRemapTblOffset; // offset of ATOM_DRAM_DATA_REMAP array to indicate DRAM data lane to GPU mapping 7371 USHORT usReserved1; 7372 UCHAR ucNumOfVRAMModule; // indicate number of VRAM module 7373 UCHAR ucMemoryClkPatchTblVer; // version of memory AC timing register list 7374 UCHAR ucVramModuleVer; // indicate ATOM_VRAM_MODUE version 7375 UCHAR ucMcPhyTileNum; // indicate the MCD tile number which use in DramDataRemapTbl and usMcAdjustPerTileTblOffset 7376 ATOM_VRAM_MODULE_V8 aVramInfo[ATOM_MAX_NUMBER_OF_VRAM_MODULE]; // just for allocation, real number of blocks is in ucNumOfVRAMModule; 7377 }ATOM_VRAM_INFO_HEADER_V2_2; 7378 7379 7380 typedef struct _ATOM_DRAM_DATA_REMAP 7381 { 7382 UCHAR ucByteRemapCh0; 7383 UCHAR ucByteRemapCh1; 7384 ULONG ulByte0BitRemapCh0; 7385 ULONG ulByte1BitRemapCh0; 7386 ULONG ulByte2BitRemapCh0; 7387 ULONG ulByte3BitRemapCh0; 7388 ULONG ulByte0BitRemapCh1; 7389 ULONG ulByte1BitRemapCh1; 7390 ULONG ulByte2BitRemapCh1; 7391 ULONG ulByte3BitRemapCh1; 7392 }ATOM_DRAM_DATA_REMAP; 7393 7394 typedef struct _ATOM_VRAM_GPIO_DETECTION_INFO 7395 { 7396 ATOM_COMMON_TABLE_HEADER sHeader; 7397 UCHAR aVID_PinsShift[9]; // 8 bit strap maximum+terminator 7398 }ATOM_VRAM_GPIO_DETECTION_INFO; 7399 7400 7401 typedef struct _ATOM_MEMORY_TRAINING_INFO 7402 { 7403 ATOM_COMMON_TABLE_HEADER sHeader; 7404 UCHAR ucTrainingLoop; 7405 UCHAR ucReserved[3]; 7406 ATOM_INIT_REG_BLOCK asMemTrainingSetting; 7407 }ATOM_MEMORY_TRAINING_INFO; 7408 7409 7410 typedef struct SW_I2C_CNTL_DATA_PARAMETERS 7411 { 7412 UCHAR ucControl; 7413 UCHAR ucData; 7414 UCHAR ucSatus; 7415 UCHAR ucTemp; 7416 } SW_I2C_CNTL_DATA_PARAMETERS; 7417 7418 #define SW_I2C_CNTL_DATA_PS_ALLOCATION SW_I2C_CNTL_DATA_PARAMETERS 7419 7420 typedef struct _SW_I2C_IO_DATA_PARAMETERS 7421 { 7422 USHORT GPIO_Info; 7423 UCHAR ucAct; 7424 UCHAR ucData; 7425 } SW_I2C_IO_DATA_PARAMETERS; 7426 7427 #define SW_I2C_IO_DATA_PS_ALLOCATION SW_I2C_IO_DATA_PARAMETERS 7428 7429 /****************************SW I2C CNTL DEFINITIONS**********************/ 7430 #define SW_I2C_IO_RESET 0 7431 #define SW_I2C_IO_GET 1 7432 #define SW_I2C_IO_DRIVE 2 7433 #define SW_I2C_IO_SET 3 7434 #define SW_I2C_IO_START 4 7435 7436 #define SW_I2C_IO_CLOCK 0 7437 #define SW_I2C_IO_DATA 0x80 7438 7439 #define SW_I2C_IO_ZERO 0 7440 #define SW_I2C_IO_ONE 0x100 7441 7442 #define SW_I2C_CNTL_READ 0 7443 #define SW_I2C_CNTL_WRITE 1 7444 #define SW_I2C_CNTL_START 2 7445 #define SW_I2C_CNTL_STOP 3 7446 #define SW_I2C_CNTL_OPEN 4 7447 #define SW_I2C_CNTL_CLOSE 5 7448 #define SW_I2C_CNTL_WRITE1BIT 6 7449 7450 //==============================VESA definition Portion=============================== 7451 #define VESA_OEM_PRODUCT_REV '01.00' 7452 #define VESA_MODE_ATTRIBUTE_MODE_SUPPORT 0xBB //refer to VBE spec p.32, no TTY support 7453 #define VESA_MODE_WIN_ATTRIBUTE 7 7454 #define VESA_WIN_SIZE 64 7455 7456 typedef struct _PTR_32_BIT_STRUCTURE 7457 { 7458 USHORT Offset16; 7459 USHORT Segment16; 7460 } PTR_32_BIT_STRUCTURE; 7461 7462 typedef union _PTR_32_BIT_UNION 7463 { 7464 PTR_32_BIT_STRUCTURE SegmentOffset; 7465 ULONG Ptr32_Bit; 7466 } PTR_32_BIT_UNION; 7467 7468 typedef struct _VBE_1_2_INFO_BLOCK_UPDATABLE 7469 { 7470 UCHAR VbeSignature[4]; 7471 USHORT VbeVersion; 7472 PTR_32_BIT_UNION OemStringPtr; 7473 UCHAR Capabilities[4]; 7474 PTR_32_BIT_UNION VideoModePtr; 7475 USHORT TotalMemory; 7476 } VBE_1_2_INFO_BLOCK_UPDATABLE; 7477 7478 7479 typedef struct _VBE_2_0_INFO_BLOCK_UPDATABLE 7480 { 7481 VBE_1_2_INFO_BLOCK_UPDATABLE CommonBlock; 7482 USHORT OemSoftRev; 7483 PTR_32_BIT_UNION OemVendorNamePtr; 7484 PTR_32_BIT_UNION OemProductNamePtr; 7485 PTR_32_BIT_UNION OemProductRevPtr; 7486 } VBE_2_0_INFO_BLOCK_UPDATABLE; 7487 7488 typedef union _VBE_VERSION_UNION 7489 { 7490 VBE_2_0_INFO_BLOCK_UPDATABLE VBE_2_0_InfoBlock; 7491 VBE_1_2_INFO_BLOCK_UPDATABLE VBE_1_2_InfoBlock; 7492 } VBE_VERSION_UNION; 7493 7494 typedef struct _VBE_INFO_BLOCK 7495 { 7496 VBE_VERSION_UNION UpdatableVBE_Info; 7497 UCHAR Reserved[222]; 7498 UCHAR OemData[256]; 7499 } VBE_INFO_BLOCK; 7500 7501 typedef struct _VBE_FP_INFO 7502 { 7503 USHORT HSize; 7504 USHORT VSize; 7505 USHORT FPType; 7506 UCHAR RedBPP; 7507 UCHAR GreenBPP; 7508 UCHAR BlueBPP; 7509 UCHAR ReservedBPP; 7510 ULONG RsvdOffScrnMemSize; 7511 ULONG RsvdOffScrnMEmPtr; 7512 UCHAR Reserved[14]; 7513 } VBE_FP_INFO; 7514 7515 typedef struct _VESA_MODE_INFO_BLOCK 7516 { 7517 // Mandatory information for all VBE revisions 7518 USHORT ModeAttributes; // dw ? ; mode attributes 7519 UCHAR WinAAttributes; // db ? ; window A attributes 7520 UCHAR WinBAttributes; // db ? ; window B attributes 7521 USHORT WinGranularity; // dw ? ; window granularity 7522 USHORT WinSize; // dw ? ; window size 7523 USHORT WinASegment; // dw ? ; window A start segment 7524 USHORT WinBSegment; // dw ? ; window B start segment 7525 ULONG WinFuncPtr; // dd ? ; real mode pointer to window function 7526 USHORT BytesPerScanLine;// dw ? ; bytes per scan line 7527 7528 //; Mandatory information for VBE 1.2 and above 7529 USHORT XResolution; // dw ? ; horizontal resolution in pixels or characters 7530 USHORT YResolution; // dw ? ; vertical resolution in pixels or characters 7531 UCHAR XCharSize; // db ? ; character cell width in pixels 7532 UCHAR YCharSize; // db ? ; character cell height in pixels 7533 UCHAR NumberOfPlanes; // db ? ; number of memory planes 7534 UCHAR BitsPerPixel; // db ? ; bits per pixel 7535 UCHAR NumberOfBanks; // db ? ; number of banks 7536 UCHAR MemoryModel; // db ? ; memory model type 7537 UCHAR BankSize; // db ? ; bank size in KB 7538 UCHAR NumberOfImagePages;// db ? ; number of images 7539 UCHAR ReservedForPageFunction;//db 1 ; reserved for page function 7540 7541 //; Direct Color fields(required for direct/6 and YUV/7 memory models) 7542 UCHAR RedMaskSize; // db ? ; size of direct color red mask in bits 7543 UCHAR RedFieldPosition; // db ? ; bit position of lsb of red mask 7544 UCHAR GreenMaskSize; // db ? ; size of direct color green mask in bits 7545 UCHAR GreenFieldPosition; // db ? ; bit position of lsb of green mask 7546 UCHAR BlueMaskSize; // db ? ; size of direct color blue mask in bits 7547 UCHAR BlueFieldPosition; // db ? ; bit position of lsb of blue mask 7548 UCHAR RsvdMaskSize; // db ? ; size of direct color reserved mask in bits 7549 UCHAR RsvdFieldPosition; // db ? ; bit position of lsb of reserved mask 7550 UCHAR DirectColorModeInfo;// db ? ; direct color mode attributes 7551 7552 //; Mandatory information for VBE 2.0 and above 7553 ULONG PhysBasePtr; // dd ? ; physical address for flat memory frame buffer 7554 ULONG Reserved_1; // dd 0 ; reserved - always set to 0 7555 USHORT Reserved_2; // dw 0 ; reserved - always set to 0 7556 7557 //; Mandatory information for VBE 3.0 and above 7558 USHORT LinBytesPerScanLine; // dw ? ; bytes per scan line for linear modes 7559 UCHAR BnkNumberOfImagePages;// db ? ; number of images for banked modes 7560 UCHAR LinNumberOfImagPages; // db ? ; number of images for linear modes 7561 UCHAR LinRedMaskSize; // db ? ; size of direct color red mask(linear modes) 7562 UCHAR LinRedFieldPosition; // db ? ; bit position of lsb of red mask(linear modes) 7563 UCHAR LinGreenMaskSize; // db ? ; size of direct color green mask(linear modes) 7564 UCHAR LinGreenFieldPosition;// db ? ; bit position of lsb of green mask(linear modes) 7565 UCHAR LinBlueMaskSize; // db ? ; size of direct color blue mask(linear modes) 7566 UCHAR LinBlueFieldPosition; // db ? ; bit position of lsb of blue mask(linear modes) 7567 UCHAR LinRsvdMaskSize; // db ? ; size of direct color reserved mask(linear modes) 7568 UCHAR LinRsvdFieldPosition; // db ? ; bit position of lsb of reserved mask(linear modes) 7569 ULONG MaxPixelClock; // dd ? ; maximum pixel clock(in Hz) for graphics mode 7570 UCHAR Reserved; // db 190 dup (0) 7571 } VESA_MODE_INFO_BLOCK; 7572 7573 // BIOS function CALLS 7574 #define ATOM_BIOS_EXTENDED_FUNCTION_CODE 0xA0 // ATI Extended Function code 7575 #define ATOM_BIOS_FUNCTION_COP_MODE 0x00 7576 #define ATOM_BIOS_FUNCTION_SHORT_QUERY1 0x04 7577 #define ATOM_BIOS_FUNCTION_SHORT_QUERY2 0x05 7578 #define ATOM_BIOS_FUNCTION_SHORT_QUERY3 0x06 7579 #define ATOM_BIOS_FUNCTION_GET_DDC 0x0B 7580 #define ATOM_BIOS_FUNCTION_ASIC_DSTATE 0x0E 7581 #define ATOM_BIOS_FUNCTION_DEBUG_PLAY 0x0F 7582 #define ATOM_BIOS_FUNCTION_STV_STD 0x16 7583 #define ATOM_BIOS_FUNCTION_DEVICE_DET 0x17 7584 #define ATOM_BIOS_FUNCTION_DEVICE_SWITCH 0x18 7585 7586 #define ATOM_BIOS_FUNCTION_PANEL_CONTROL 0x82 7587 #define ATOM_BIOS_FUNCTION_OLD_DEVICE_DET 0x83 7588 #define ATOM_BIOS_FUNCTION_OLD_DEVICE_SWITCH 0x84 7589 #define ATOM_BIOS_FUNCTION_HW_ICON 0x8A 7590 #define ATOM_BIOS_FUNCTION_SET_CMOS 0x8B 7591 #define SUB_FUNCTION_UPDATE_DISPLAY_INFO 0x8000 // Sub function 80 7592 #define SUB_FUNCTION_UPDATE_EXPANSION_INFO 0x8100 // Sub function 80 7593 7594 #define ATOM_BIOS_FUNCTION_DISPLAY_INFO 0x8D 7595 #define ATOM_BIOS_FUNCTION_DEVICE_ON_OFF 0x8E 7596 #define ATOM_BIOS_FUNCTION_VIDEO_STATE 0x8F 7597 #define ATOM_SUB_FUNCTION_GET_CRITICAL_STATE 0x0300 // Sub function 03 7598 #define ATOM_SUB_FUNCTION_GET_LIDSTATE 0x0700 // Sub function 7 7599 #define ATOM_SUB_FUNCTION_THERMAL_STATE_NOTICE 0x1400 // Notify caller the current thermal state 7600 #define ATOM_SUB_FUNCTION_CRITICAL_STATE_NOTICE 0x8300 // Notify caller the current critical state 7601 #define ATOM_SUB_FUNCTION_SET_LIDSTATE 0x8500 // Sub function 85 7602 #define ATOM_SUB_FUNCTION_GET_REQ_DISPLAY_FROM_SBIOS_MODE 0x8900// Sub function 89 7603 #define ATOM_SUB_FUNCTION_INFORM_ADC_SUPPORT 0x9400 // Notify caller that ADC is supported 7604 7605 7606 #define ATOM_BIOS_FUNCTION_VESA_DPMS 0x4F10 // Set DPMS 7607 #define ATOM_SUB_FUNCTION_SET_DPMS 0x0001 // BL: Sub function 01 7608 #define ATOM_SUB_FUNCTION_GET_DPMS 0x0002 // BL: Sub function 02 7609 #define ATOM_PARAMETER_VESA_DPMS_ON 0x0000 // BH Parameter for DPMS ON. 7610 #define ATOM_PARAMETER_VESA_DPMS_STANDBY 0x0100 // BH Parameter for DPMS STANDBY 7611 #define ATOM_PARAMETER_VESA_DPMS_SUSPEND 0x0200 // BH Parameter for DPMS SUSPEND 7612 #define ATOM_PARAMETER_VESA_DPMS_OFF 0x0400 // BH Parameter for DPMS OFF 7613 #define ATOM_PARAMETER_VESA_DPMS_REDUCE_ON 0x0800 // BH Parameter for DPMS REDUCE ON (NOT SUPPORTED) 7614 7615 #define ATOM_BIOS_RETURN_CODE_MASK 0x0000FF00L 7616 #define ATOM_BIOS_REG_HIGH_MASK 0x0000FF00L 7617 #define ATOM_BIOS_REG_LOW_MASK 0x000000FFL 7618 7619 // structure used for VBIOS only 7620 7621 //DispOutInfoTable 7622 typedef struct _ASIC_TRANSMITTER_INFO 7623 { 7624 USHORT usTransmitterObjId; 7625 USHORT usSupportDevice; 7626 UCHAR ucTransmitterCmdTblId; 7627 UCHAR ucConfig; 7628 UCHAR ucEncoderID; //available 1st encoder ( default ) 7629 UCHAR ucOptionEncoderID; //available 2nd encoder ( optional ) 7630 UCHAR uc2ndEncoderID; 7631 UCHAR ucReserved; 7632 }ASIC_TRANSMITTER_INFO; 7633 7634 #define ASIC_TRANSMITTER_INFO_CONFIG__DVO_SDR_MODE 0x01 7635 #define ASIC_TRANSMITTER_INFO_CONFIG__COHERENT_MODE 0x02 7636 #define ASIC_TRANSMITTER_INFO_CONFIG__ENCODEROBJ_ID_MASK 0xc4 7637 #define ASIC_TRANSMITTER_INFO_CONFIG__ENCODER_A 0x00 7638 #define ASIC_TRANSMITTER_INFO_CONFIG__ENCODER_B 0x04 7639 #define ASIC_TRANSMITTER_INFO_CONFIG__ENCODER_C 0x40 7640 #define ASIC_TRANSMITTER_INFO_CONFIG__ENCODER_D 0x44 7641 #define ASIC_TRANSMITTER_INFO_CONFIG__ENCODER_E 0x80 7642 #define ASIC_TRANSMITTER_INFO_CONFIG__ENCODER_F 0x84 7643 7644 typedef struct _ASIC_ENCODER_INFO 7645 { 7646 UCHAR ucEncoderID; 7647 UCHAR ucEncoderConfig; 7648 USHORT usEncoderCmdTblId; 7649 }ASIC_ENCODER_INFO; 7650 7651 typedef struct _ATOM_DISP_OUT_INFO 7652 { 7653 ATOM_COMMON_TABLE_HEADER sHeader; 7654 USHORT ptrTransmitterInfo; 7655 USHORT ptrEncoderInfo; 7656 ASIC_TRANSMITTER_INFO asTransmitterInfo[1]; 7657 ASIC_ENCODER_INFO asEncoderInfo[1]; 7658 }ATOM_DISP_OUT_INFO; 7659 7660 7661 typedef struct _ATOM_DISP_OUT_INFO_V2 7662 { 7663 ATOM_COMMON_TABLE_HEADER sHeader; 7664 USHORT ptrTransmitterInfo; 7665 USHORT ptrEncoderInfo; 7666 USHORT ptrMainCallParserFar; // direct address of main parser call in VBIOS binary. 7667 ASIC_TRANSMITTER_INFO asTransmitterInfo[1]; 7668 ASIC_ENCODER_INFO asEncoderInfo[1]; 7669 }ATOM_DISP_OUT_INFO_V2; 7670 7671 7672 typedef struct _ATOM_DISP_CLOCK_ID { 7673 UCHAR ucPpllId; 7674 UCHAR ucPpllAttribute; 7675 }ATOM_DISP_CLOCK_ID; 7676 7677 // ucPpllAttribute 7678 #define CLOCK_SOURCE_SHAREABLE 0x01 7679 #define CLOCK_SOURCE_DP_MODE 0x02 7680 #define CLOCK_SOURCE_NONE_DP_MODE 0x04 7681 7682 //DispOutInfoTable 7683 typedef struct _ASIC_TRANSMITTER_INFO_V2 7684 { 7685 USHORT usTransmitterObjId; 7686 USHORT usDispClkIdOffset; // point to clock source id list supported by Encoder Object 7687 UCHAR ucTransmitterCmdTblId; 7688 UCHAR ucConfig; 7689 UCHAR ucEncoderID; // available 1st encoder ( default ) 7690 UCHAR ucOptionEncoderID; // available 2nd encoder ( optional ) 7691 UCHAR uc2ndEncoderID; 7692 UCHAR ucReserved; 7693 }ASIC_TRANSMITTER_INFO_V2; 7694 7695 typedef struct _ATOM_DISP_OUT_INFO_V3 7696 { 7697 ATOM_COMMON_TABLE_HEADER sHeader; 7698 USHORT ptrTransmitterInfo; 7699 USHORT ptrEncoderInfo; 7700 USHORT ptrMainCallParserFar; // direct address of main parser call in VBIOS binary. 7701 USHORT usReserved; 7702 UCHAR ucDCERevision; 7703 UCHAR ucMaxDispEngineNum; 7704 UCHAR ucMaxActiveDispEngineNum; 7705 UCHAR ucMaxPPLLNum; 7706 UCHAR ucCoreRefClkSource; // value of CORE_REF_CLK_SOURCE 7707 UCHAR ucDispCaps; 7708 UCHAR ucReserved[2]; 7709 ASIC_TRANSMITTER_INFO_V2 asTransmitterInfo[1]; // for alligment only 7710 }ATOM_DISP_OUT_INFO_V3; 7711 7712 //ucDispCaps 7713 #define DISPLAY_CAPS__DP_PCLK_FROM_PPLL 0x01 7714 #define DISPLAY_CAPS__FORCE_DISPDEV_CONNECTED 0x02 7715 7716 typedef enum CORE_REF_CLK_SOURCE{ 7717 CLOCK_SRC_XTALIN=0, 7718 CLOCK_SRC_XO_IN=1, 7719 CLOCK_SRC_XO_IN2=2, 7720 }CORE_REF_CLK_SOURCE; 7721 7722 // DispDevicePriorityInfo 7723 typedef struct _ATOM_DISPLAY_DEVICE_PRIORITY_INFO 7724 { 7725 ATOM_COMMON_TABLE_HEADER sHeader; 7726 USHORT asDevicePriority[16]; 7727 }ATOM_DISPLAY_DEVICE_PRIORITY_INFO; 7728 7729 //ProcessAuxChannelTransactionTable 7730 typedef struct _PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS 7731 { 7732 USHORT lpAuxRequest; 7733 USHORT lpDataOut; 7734 UCHAR ucChannelID; 7735 union 7736 { 7737 UCHAR ucReplyStatus; 7738 UCHAR ucDelay; 7739 }; 7740 UCHAR ucDataOutLen; 7741 UCHAR ucReserved; 7742 }PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS; 7743 7744 //ProcessAuxChannelTransactionTable 7745 typedef struct _PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS_V2 7746 { 7747 USHORT lpAuxRequest; 7748 USHORT lpDataOut; 7749 UCHAR ucChannelID; 7750 union 7751 { 7752 UCHAR ucReplyStatus; 7753 UCHAR ucDelay; 7754 }; 7755 UCHAR ucDataOutLen; 7756 UCHAR ucHPD_ID; //=0: HPD1, =1: HPD2, =2: HPD3, =3: HPD4, =4: HPD5, =5: HPD6 7757 }PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS_V2; 7758 7759 #define PROCESS_AUX_CHANNEL_TRANSACTION_PS_ALLOCATION PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS 7760 7761 //GetSinkType 7762 7763 typedef struct _DP_ENCODER_SERVICE_PARAMETERS 7764 { 7765 USHORT ucLinkClock; 7766 union 7767 { 7768 UCHAR ucConfig; // for DP training command 7769 UCHAR ucI2cId; // use for GET_SINK_TYPE command 7770 }; 7771 UCHAR ucAction; 7772 UCHAR ucStatus; 7773 UCHAR ucLaneNum; 7774 UCHAR ucReserved[2]; 7775 }DP_ENCODER_SERVICE_PARAMETERS; 7776 7777 // ucAction 7778 #define ATOM_DP_ACTION_GET_SINK_TYPE 0x01 7779 7780 #define DP_ENCODER_SERVICE_PS_ALLOCATION WRITE_ONE_BYTE_HW_I2C_DATA_PARAMETERS 7781 7782 7783 typedef struct _DP_ENCODER_SERVICE_PARAMETERS_V2 7784 { 7785 USHORT usExtEncoderObjId; // External Encoder Object Id, output parameter only, use when ucAction = DP_SERVICE_V2_ACTION_DET_EXT_CONNECTION 7786 UCHAR ucAuxId; 7787 UCHAR ucAction; 7788 UCHAR ucSinkType; // Iput and Output parameters. 7789 UCHAR ucHPDId; // Input parameter, used when ucAction = DP_SERVICE_V2_ACTION_DET_EXT_CONNECTION 7790 UCHAR ucReserved[2]; 7791 }DP_ENCODER_SERVICE_PARAMETERS_V2; 7792 7793 typedef struct _DP_ENCODER_SERVICE_PS_ALLOCATION_V2 7794 { 7795 DP_ENCODER_SERVICE_PARAMETERS_V2 asDPServiceParam; 7796 PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS_V2 asAuxParam; 7797 }DP_ENCODER_SERVICE_PS_ALLOCATION_V2; 7798 7799 // ucAction 7800 #define DP_SERVICE_V2_ACTION_GET_SINK_TYPE 0x01 7801 #define DP_SERVICE_V2_ACTION_DET_LCD_CONNECTION 0x02 7802 7803 7804 // DP_TRAINING_TABLE 7805 #define DPCD_SET_LINKRATE_LANENUM_PATTERN1_TBL_ADDR ATOM_DP_TRAINING_TBL_ADDR 7806 #define DPCD_SET_SS_CNTL_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 8 ) 7807 #define DPCD_SET_LANE_VSWING_PREEMP_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 16 ) 7808 #define DPCD_SET_TRAINING_PATTERN0_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 24 ) 7809 #define DPCD_SET_TRAINING_PATTERN2_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 32) 7810 #define DPCD_GET_LINKRATE_LANENUM_SS_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 40) 7811 #define DPCD_GET_LANE_STATUS_ADJUST_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 48) 7812 #define DP_I2C_AUX_DDC_WRITE_START_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 60) 7813 #define DP_I2C_AUX_DDC_WRITE_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 64) 7814 #define DP_I2C_AUX_DDC_READ_START_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 72) 7815 #define DP_I2C_AUX_DDC_READ_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 76) 7816 #define DP_I2C_AUX_DDC_WRITE_END_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 80) 7817 #define DP_I2C_AUX_DDC_READ_END_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 84) 7818 7819 7820 typedef struct _PROCESS_I2C_CHANNEL_TRANSACTION_PARAMETERS 7821 { 7822 UCHAR ucI2CSpeed; 7823 union 7824 { 7825 UCHAR ucRegIndex; 7826 UCHAR ucStatus; 7827 }; 7828 USHORT lpI2CDataOut; 7829 UCHAR ucFlag; 7830 UCHAR ucTransBytes; 7831 UCHAR ucSlaveAddr; 7832 UCHAR ucLineNumber; 7833 }PROCESS_I2C_CHANNEL_TRANSACTION_PARAMETERS; 7834 7835 #define PROCESS_I2C_CHANNEL_TRANSACTION_PS_ALLOCATION PROCESS_I2C_CHANNEL_TRANSACTION_PARAMETERS 7836 7837 //ucFlag 7838 #define HW_I2C_WRITE 1 7839 #define HW_I2C_READ 0 7840 #define I2C_2BYTE_ADDR 0x02 7841 7842 /****************************************************************************/ 7843 // Structures used by HW_Misc_OperationTable 7844 /****************************************************************************/ 7845 typedef struct _ATOM_HW_MISC_OPERATION_INPUT_PARAMETER_V1_1 7846 { 7847 UCHAR ucCmd; // Input: To tell which action to take 7848 UCHAR ucReserved[3]; 7849 ULONG ulReserved; 7850 }ATOM_HW_MISC_OPERATION_INPUT_PARAMETER_V1_1; 7851 7852 typedef struct _ATOM_HW_MISC_OPERATION_OUTPUT_PARAMETER_V1_1 7853 { 7854 UCHAR ucReturnCode; // Output: Return value base on action was taken 7855 UCHAR ucReserved[3]; 7856 ULONG ulReserved; 7857 }ATOM_HW_MISC_OPERATION_OUTPUT_PARAMETER_V1_1; 7858 7859 // Actions code 7860 #define ATOM_GET_SDI_SUPPORT 0xF0 7861 7862 // Return code 7863 #define ATOM_UNKNOWN_CMD 0 7864 #define ATOM_FEATURE_NOT_SUPPORTED 1 7865 #define ATOM_FEATURE_SUPPORTED 2 7866 7867 typedef struct _ATOM_HW_MISC_OPERATION_PS_ALLOCATION 7868 { 7869 ATOM_HW_MISC_OPERATION_INPUT_PARAMETER_V1_1 sInput_Output; 7870 PROCESS_I2C_CHANNEL_TRANSACTION_PARAMETERS sReserved; 7871 }ATOM_HW_MISC_OPERATION_PS_ALLOCATION; 7872 7873 /****************************************************************************/ 7874 7875 typedef struct _SET_HWBLOCK_INSTANCE_PARAMETER_V2 7876 { 7877 UCHAR ucHWBlkInst; // HW block instance, 0, 1, 2, ... 7878 UCHAR ucReserved[3]; 7879 }SET_HWBLOCK_INSTANCE_PARAMETER_V2; 7880 7881 #define HWBLKINST_INSTANCE_MASK 0x07 7882 #define HWBLKINST_HWBLK_MASK 0xF0 7883 #define HWBLKINST_HWBLK_SHIFT 0x04 7884 7885 //ucHWBlock 7886 #define SELECT_DISP_ENGINE 0 7887 #define SELECT_DISP_PLL 1 7888 #define SELECT_DCIO_UNIPHY_LINK0 2 7889 #define SELECT_DCIO_UNIPHY_LINK1 3 7890 #define SELECT_DCIO_IMPCAL 4 7891 #define SELECT_DCIO_DIG 6 7892 #define SELECT_CRTC_PIXEL_RATE 7 7893 #define SELECT_VGA_BLK 8 7894 7895 // DIGTransmitterInfoTable structure used to program UNIPHY settings 7896 typedef struct _DIG_TRANSMITTER_INFO_HEADER_V3_1{ 7897 ATOM_COMMON_TABLE_HEADER sHeader; 7898 USHORT usDPVsPreEmphSettingOffset; // offset of PHY_ANALOG_SETTING_INFO * with DP Voltage Swing and Pre-Emphasis for each Link clock 7899 USHORT usPhyAnalogRegListOffset; // offset of CLOCK_CONDITION_REGESTER_INFO* with None-DP mode Analog Setting's register Info 7900 USHORT usPhyAnalogSettingOffset; // offset of CLOCK_CONDITION_SETTING_ENTRY* with None-DP mode Analog Setting for each link clock range 7901 USHORT usPhyPllRegListOffset; // offset of CLOCK_CONDITION_REGESTER_INFO* with Phy Pll register Info 7902 USHORT usPhyPllSettingOffset; // offset of CLOCK_CONDITION_SETTING_ENTRY* with Phy Pll Settings 7903 }DIG_TRANSMITTER_INFO_HEADER_V3_1; 7904 7905 typedef struct _DIG_TRANSMITTER_INFO_HEADER_V3_2{ 7906 ATOM_COMMON_TABLE_HEADER sHeader; 7907 USHORT usDPVsPreEmphSettingOffset; // offset of PHY_ANALOG_SETTING_INFO * with DP Voltage Swing and Pre-Emphasis for each Link clock 7908 USHORT usPhyAnalogRegListOffset; // offset of CLOCK_CONDITION_REGESTER_INFO* with None-DP mode Analog Setting's register Info 7909 USHORT usPhyAnalogSettingOffset; // offset of CLOCK_CONDITION_SETTING_ENTRY* with None-DP mode Analog Setting for each link clock range 7910 USHORT usPhyPllRegListOffset; // offset of CLOCK_CONDITION_REGESTER_INFO* with Phy Pll register Info 7911 USHORT usPhyPllSettingOffset; // offset of CLOCK_CONDITION_SETTING_ENTRY* with Phy Pll Settings 7912 USHORT usDPSSRegListOffset; // offset of CLOCK_CONDITION_REGESTER_INFO* with Phy SS Pll register Info 7913 USHORT usDPSSSettingOffset; // offset of CLOCK_CONDITION_SETTING_ENTRY* with Phy SS Pll Settings 7914 }DIG_TRANSMITTER_INFO_HEADER_V3_2; 7915 7916 7917 typedef struct _DIG_TRANSMITTER_INFO_HEADER_V3_3{ 7918 ATOM_COMMON_TABLE_HEADER sHeader; 7919 USHORT usDPVsPreEmphSettingOffset; // offset of PHY_ANALOG_SETTING_INFO * with DP Voltage Swing and Pre-Emphasis for each Link clock 7920 USHORT usPhyAnalogRegListOffset; // offset of CLOCK_CONDITION_REGESTER_INFO* with None-DP mode Analog Setting's register Info 7921 USHORT usPhyAnalogSettingOffset; // offset of CLOCK_CONDITION_SETTING_ENTRY* with None-DP mode Analog Setting for each link clock range 7922 USHORT usPhyPllRegListOffset; // offset of CLOCK_CONDITION_REGESTER_INFO* with Phy Pll register Info 7923 USHORT usPhyPllSettingOffset; // offset of CLOCK_CONDITION_SETTING_ENTRY* with Phy Pll Settings 7924 USHORT usDPSSRegListOffset; // offset of CLOCK_CONDITION_REGESTER_INFO* with Phy SS Pll register Info 7925 USHORT usDPSSSettingOffset; // offset of CLOCK_CONDITION_SETTING_ENTRY* with Phy SS Pll Settings 7926 USHORT usEDPVsLegacyModeOffset; // offset of PHY_ANALOG_SETTING_INFO * with eDP Legacy Mode Voltage Swing and Pre-Emphasis for each Link clock 7927 USHORT useDPVsLowVdiffModeOffset; // offset of PHY_ANALOG_SETTING_INFO * with eDP Low VDiff Mode Voltage Swing and Pre-Emphasis for each Link clock 7928 USHORT useDPVsHighVdiffModeOffset; // offset of PHY_ANALOG_SETTING_INFO * with eDP High VDiff Mode Voltage Swing and Pre-Emphasis for each Link clock 7929 USHORT useDPVsStretchModeOffset; // offset of PHY_ANALOG_SETTING_INFO * with eDP Stretch Mode Voltage Swing and Pre-Emphasis for each Link clock 7930 USHORT useDPVsSingleVdiffModeOffset; // offset of PHY_ANALOG_SETTING_INFO * with eDP Single Vdiff Mode Voltage Swing and Pre-Emphasis for each Link clock 7931 USHORT useDPVsVariablePremModeOffset; // offset of PHY_ANALOG_SETTING_INFO * with eDP Single Vidff+Variable PreEmphasis Voltage Swing and Pre-Emphasis for each Link clock 7932 }DIG_TRANSMITTER_INFO_HEADER_V3_3; 7933 7934 7935 typedef struct _CLOCK_CONDITION_REGESTER_INFO{ 7936 USHORT usRegisterIndex; 7937 UCHAR ucStartBit; 7938 UCHAR ucEndBit; 7939 }CLOCK_CONDITION_REGESTER_INFO; 7940 7941 typedef struct _CLOCK_CONDITION_SETTING_ENTRY{ 7942 USHORT usMaxClockFreq; 7943 UCHAR ucEncodeMode; 7944 UCHAR ucPhySel; 7945 ULONG ulAnalogSetting[1]; 7946 }CLOCK_CONDITION_SETTING_ENTRY; 7947 7948 typedef struct _CLOCK_CONDITION_SETTING_INFO{ 7949 USHORT usEntrySize; 7950 CLOCK_CONDITION_SETTING_ENTRY asClkCondSettingEntry[1]; 7951 }CLOCK_CONDITION_SETTING_INFO; 7952 7953 typedef struct _PHY_CONDITION_REG_VAL{ 7954 ULONG ulCondition; 7955 ULONG ulRegVal; 7956 }PHY_CONDITION_REG_VAL; 7957 7958 typedef struct _PHY_CONDITION_REG_VAL_V2{ 7959 ULONG ulCondition; 7960 UCHAR ucCondition2; 7961 ULONG ulRegVal; 7962 }PHY_CONDITION_REG_VAL_V2; 7963 7964 typedef struct _PHY_CONDITION_REG_INFO{ 7965 USHORT usRegIndex; 7966 USHORT usSize; 7967 PHY_CONDITION_REG_VAL asRegVal[1]; 7968 }PHY_CONDITION_REG_INFO; 7969 7970 typedef struct _PHY_CONDITION_REG_INFO_V2{ 7971 USHORT usRegIndex; 7972 USHORT usSize; 7973 PHY_CONDITION_REG_VAL_V2 asRegVal[1]; 7974 }PHY_CONDITION_REG_INFO_V2; 7975 7976 typedef struct _PHY_ANALOG_SETTING_INFO{ 7977 UCHAR ucEncodeMode; 7978 UCHAR ucPhySel; 7979 USHORT usSize; 7980 PHY_CONDITION_REG_INFO asAnalogSetting[1]; 7981 }PHY_ANALOG_SETTING_INFO; 7982 7983 typedef struct _PHY_ANALOG_SETTING_INFO_V2{ 7984 UCHAR ucEncodeMode; 7985 UCHAR ucPhySel; 7986 USHORT usSize; 7987 PHY_CONDITION_REG_INFO_V2 asAnalogSetting[1]; 7988 }PHY_ANALOG_SETTING_INFO_V2; 7989 7990 7991 typedef struct _GFX_HAVESTING_PARAMETERS { 7992 UCHAR ucGfxBlkId; //GFX blk id to be harvested, like CU, RB or PRIM 7993 UCHAR ucReserved; //reserved 7994 UCHAR ucActiveUnitNumPerSH; //requested active CU/RB/PRIM number per shader array 7995 UCHAR ucMaxUnitNumPerSH; //max CU/RB/PRIM number per shader array 7996 } GFX_HAVESTING_PARAMETERS; 7997 7998 //ucGfxBlkId 7999 #define GFX_HARVESTING_CU_ID 0 8000 #define GFX_HARVESTING_RB_ID 1 8001 #define GFX_HARVESTING_PRIM_ID 2 8002 8003 8004 typedef struct _VBIOS_ROM_HEADER{ 8005 UCHAR PciRomSignature[2]; 8006 UCHAR ucPciRomSizeIn512bytes; 8007 UCHAR ucJumpCoreMainInitBIOS; 8008 USHORT usLabelCoreMainInitBIOS; 8009 UCHAR PciReservedSpace[18]; 8010 USHORT usPciDataStructureOffset; 8011 UCHAR Rsvd1d_1a[4]; 8012 char strIbm[3]; 8013 UCHAR CheckSum[14]; 8014 UCHAR ucBiosMsgNumber; 8015 char str761295520[16]; 8016 USHORT usLabelCoreVPOSTNoMode; 8017 USHORT usSpecialPostOffset; 8018 UCHAR ucSpeicalPostImageSizeIn512Bytes; 8019 UCHAR Rsved47_45[3]; 8020 USHORT usROM_HeaderInformationTableOffset; 8021 UCHAR Rsved4f_4a[6]; 8022 char strBuildTimeStamp[20]; 8023 UCHAR ucJumpCoreXFuncFarHandler; 8024 USHORT usCoreXFuncFarHandlerOffset; 8025 UCHAR ucRsved67; 8026 UCHAR ucJumpCoreVFuncFarHandler; 8027 USHORT usCoreVFuncFarHandlerOffset; 8028 UCHAR Rsved6d_6b[3]; 8029 USHORT usATOM_BIOS_MESSAGE_Offset; 8030 }VBIOS_ROM_HEADER; 8031 8032 /****************************************************************************/ 8033 //Portion VI: Definitinos for vbios MC scratch registers that driver used 8034 /****************************************************************************/ 8035 8036 #define MC_MISC0__MEMORY_TYPE_MASK 0xF0000000 8037 #define MC_MISC0__MEMORY_TYPE__GDDR1 0x10000000 8038 #define MC_MISC0__MEMORY_TYPE__DDR2 0x20000000 8039 #define MC_MISC0__MEMORY_TYPE__GDDR3 0x30000000 8040 #define MC_MISC0__MEMORY_TYPE__GDDR4 0x40000000 8041 #define MC_MISC0__MEMORY_TYPE__GDDR5 0x50000000 8042 #define MC_MISC0__MEMORY_TYPE__HBM 0x60000000 8043 #define MC_MISC0__MEMORY_TYPE__DDR3 0xB0000000 8044 8045 #define ATOM_MEM_TYPE_DDR_STRING "DDR" 8046 #define ATOM_MEM_TYPE_DDR2_STRING "DDR2" 8047 #define ATOM_MEM_TYPE_GDDR3_STRING "GDDR3" 8048 #define ATOM_MEM_TYPE_GDDR4_STRING "GDDR4" 8049 #define ATOM_MEM_TYPE_GDDR5_STRING "GDDR5" 8050 #define ATOM_MEM_TYPE_HBM_STRING "HBM" 8051 #define ATOM_MEM_TYPE_DDR3_STRING "DDR3" 8052 8053 /****************************************************************************/ 8054 //Portion VII: Definitinos being oboselete 8055 /****************************************************************************/ 8056 8057 //========================================================================================== 8058 //Remove the definitions below when driver is ready! 8059 typedef struct _ATOM_DAC_INFO 8060 { 8061 ATOM_COMMON_TABLE_HEADER sHeader; 8062 USHORT usMaxFrequency; // in 10kHz unit 8063 USHORT usReserved; 8064 }ATOM_DAC_INFO; 8065 8066 8067 typedef struct _COMPASSIONATE_DATA 8068 { 8069 ATOM_COMMON_TABLE_HEADER sHeader; 8070 8071 //============================== DAC1 portion 8072 UCHAR ucDAC1_BG_Adjustment; 8073 UCHAR ucDAC1_DAC_Adjustment; 8074 USHORT usDAC1_FORCE_Data; 8075 //============================== DAC2 portion 8076 UCHAR ucDAC2_CRT2_BG_Adjustment; 8077 UCHAR ucDAC2_CRT2_DAC_Adjustment; 8078 USHORT usDAC2_CRT2_FORCE_Data; 8079 USHORT usDAC2_CRT2_MUX_RegisterIndex; 8080 UCHAR ucDAC2_CRT2_MUX_RegisterInfo; //Bit[4:0]=Bit position,Bit[7]=1:Active High;=0 Active Low 8081 UCHAR ucDAC2_NTSC_BG_Adjustment; 8082 UCHAR ucDAC2_NTSC_DAC_Adjustment; 8083 USHORT usDAC2_TV1_FORCE_Data; 8084 USHORT usDAC2_TV1_MUX_RegisterIndex; 8085 UCHAR ucDAC2_TV1_MUX_RegisterInfo; //Bit[4:0]=Bit position,Bit[7]=1:Active High;=0 Active Low 8086 UCHAR ucDAC2_CV_BG_Adjustment; 8087 UCHAR ucDAC2_CV_DAC_Adjustment; 8088 USHORT usDAC2_CV_FORCE_Data; 8089 USHORT usDAC2_CV_MUX_RegisterIndex; 8090 UCHAR ucDAC2_CV_MUX_RegisterInfo; //Bit[4:0]=Bit position,Bit[7]=1:Active High;=0 Active Low 8091 UCHAR ucDAC2_PAL_BG_Adjustment; 8092 UCHAR ucDAC2_PAL_DAC_Adjustment; 8093 USHORT usDAC2_TV2_FORCE_Data; 8094 }COMPASSIONATE_DATA; 8095 8096 /****************************Supported Device Info Table Definitions**********************/ 8097 // ucConnectInfo: 8098 // [7:4] - connector type 8099 // = 1 - VGA connector 8100 // = 2 - DVI-I 8101 // = 3 - DVI-D 8102 // = 4 - DVI-A 8103 // = 5 - SVIDEO 8104 // = 6 - COMPOSITE 8105 // = 7 - LVDS 8106 // = 8 - DIGITAL LINK 8107 // = 9 - SCART 8108 // = 0xA - HDMI_type A 8109 // = 0xB - HDMI_type B 8110 // = 0xE - Special case1 (DVI+DIN) 8111 // Others=TBD 8112 // [3:0] - DAC Associated 8113 // = 0 - no DAC 8114 // = 1 - DACA 8115 // = 2 - DACB 8116 // = 3 - External DAC 8117 // Others=TBD 8118 // 8119 8120 typedef struct _ATOM_CONNECTOR_INFO 8121 { 8122 #if ATOM_BIG_ENDIAN 8123 UCHAR bfConnectorType:4; 8124 UCHAR bfAssociatedDAC:4; 8125 #else 8126 UCHAR bfAssociatedDAC:4; 8127 UCHAR bfConnectorType:4; 8128 #endif 8129 }ATOM_CONNECTOR_INFO; 8130 8131 typedef union _ATOM_CONNECTOR_INFO_ACCESS 8132 { 8133 ATOM_CONNECTOR_INFO sbfAccess; 8134 UCHAR ucAccess; 8135 }ATOM_CONNECTOR_INFO_ACCESS; 8136 8137 typedef struct _ATOM_CONNECTOR_INFO_I2C 8138 { 8139 ATOM_CONNECTOR_INFO_ACCESS sucConnectorInfo; 8140 ATOM_I2C_ID_CONFIG_ACCESS sucI2cId; 8141 }ATOM_CONNECTOR_INFO_I2C; 8142 8143 8144 typedef struct _ATOM_SUPPORTED_DEVICES_INFO 8145 { 8146 ATOM_COMMON_TABLE_HEADER sHeader; 8147 USHORT usDeviceSupport; 8148 ATOM_CONNECTOR_INFO_I2C asConnInfo[ATOM_MAX_SUPPORTED_DEVICE_INFO]; 8149 }ATOM_SUPPORTED_DEVICES_INFO; 8150 8151 #define NO_INT_SRC_MAPPED 0xFF 8152 8153 typedef struct _ATOM_CONNECTOR_INC_SRC_BITMAP 8154 { 8155 UCHAR ucIntSrcBitmap; 8156 }ATOM_CONNECTOR_INC_SRC_BITMAP; 8157 8158 typedef struct _ATOM_SUPPORTED_DEVICES_INFO_2 8159 { 8160 ATOM_COMMON_TABLE_HEADER sHeader; 8161 USHORT usDeviceSupport; 8162 ATOM_CONNECTOR_INFO_I2C asConnInfo[ATOM_MAX_SUPPORTED_DEVICE_INFO_2]; 8163 ATOM_CONNECTOR_INC_SRC_BITMAP asIntSrcInfo[ATOM_MAX_SUPPORTED_DEVICE_INFO_2]; 8164 }ATOM_SUPPORTED_DEVICES_INFO_2; 8165 8166 typedef struct _ATOM_SUPPORTED_DEVICES_INFO_2d1 8167 { 8168 ATOM_COMMON_TABLE_HEADER sHeader; 8169 USHORT usDeviceSupport; 8170 ATOM_CONNECTOR_INFO_I2C asConnInfo[ATOM_MAX_SUPPORTED_DEVICE]; 8171 ATOM_CONNECTOR_INC_SRC_BITMAP asIntSrcInfo[ATOM_MAX_SUPPORTED_DEVICE]; 8172 }ATOM_SUPPORTED_DEVICES_INFO_2d1; 8173 8174 #define ATOM_SUPPORTED_DEVICES_INFO_LAST ATOM_SUPPORTED_DEVICES_INFO_2d1 8175 8176 8177 8178 typedef struct _ATOM_MISC_CONTROL_INFO 8179 { 8180 USHORT usFrequency; 8181 UCHAR ucPLL_ChargePump; // PLL charge-pump gain control 8182 UCHAR ucPLL_DutyCycle; // PLL duty cycle control 8183 UCHAR ucPLL_VCO_Gain; // PLL VCO gain control 8184 UCHAR ucPLL_VoltageSwing; // PLL driver voltage swing control 8185 }ATOM_MISC_CONTROL_INFO; 8186 8187 8188 #define ATOM_MAX_MISC_INFO 4 8189 8190 typedef struct _ATOM_TMDS_INFO 8191 { 8192 ATOM_COMMON_TABLE_HEADER sHeader; 8193 USHORT usMaxFrequency; // in 10Khz 8194 ATOM_MISC_CONTROL_INFO asMiscInfo[ATOM_MAX_MISC_INFO]; 8195 }ATOM_TMDS_INFO; 8196 8197 8198 typedef struct _ATOM_ENCODER_ANALOG_ATTRIBUTE 8199 { 8200 UCHAR ucTVStandard; //Same as TV standards defined above, 8201 UCHAR ucPadding[1]; 8202 }ATOM_ENCODER_ANALOG_ATTRIBUTE; 8203 8204 typedef struct _ATOM_ENCODER_DIGITAL_ATTRIBUTE 8205 { 8206 UCHAR ucAttribute; //Same as other digital encoder attributes defined above 8207 UCHAR ucPadding[1]; 8208 }ATOM_ENCODER_DIGITAL_ATTRIBUTE; 8209 8210 typedef union _ATOM_ENCODER_ATTRIBUTE 8211 { 8212 ATOM_ENCODER_ANALOG_ATTRIBUTE sAlgAttrib; 8213 ATOM_ENCODER_DIGITAL_ATTRIBUTE sDigAttrib; 8214 }ATOM_ENCODER_ATTRIBUTE; 8215 8216 8217 typedef struct _DVO_ENCODER_CONTROL_PARAMETERS 8218 { 8219 USHORT usPixelClock; 8220 USHORT usEncoderID; 8221 UCHAR ucDeviceType; //Use ATOM_DEVICE_xxx1_Index to indicate device type only. 8222 UCHAR ucAction; //ATOM_ENABLE/ATOM_DISABLE/ATOM_HPD_INIT 8223 ATOM_ENCODER_ATTRIBUTE usDevAttr; 8224 }DVO_ENCODER_CONTROL_PARAMETERS; 8225 8226 typedef struct _DVO_ENCODER_CONTROL_PS_ALLOCATION 8227 { 8228 DVO_ENCODER_CONTROL_PARAMETERS sDVOEncoder; 8229 WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved; //Caller doesn't need to init this portion 8230 }DVO_ENCODER_CONTROL_PS_ALLOCATION; 8231 8232 8233 #define ATOM_XTMDS_ASIC_SI164_ID 1 8234 #define ATOM_XTMDS_ASIC_SI178_ID 2 8235 #define ATOM_XTMDS_ASIC_TFP513_ID 3 8236 #define ATOM_XTMDS_SUPPORTED_SINGLELINK 0x00000001 8237 #define ATOM_XTMDS_SUPPORTED_DUALLINK 0x00000002 8238 #define ATOM_XTMDS_MVPU_FPGA 0x00000004 8239 8240 8241 typedef struct _ATOM_XTMDS_INFO 8242 { 8243 ATOM_COMMON_TABLE_HEADER sHeader; 8244 USHORT usSingleLinkMaxFrequency; 8245 ATOM_I2C_ID_CONFIG_ACCESS sucI2cId; //Point the ID on which I2C is used to control external chip 8246 UCHAR ucXtransimitterID; 8247 UCHAR ucSupportedLink; // Bit field, bit0=1, single link supported;bit1=1,dual link supported 8248 UCHAR ucSequnceAlterID; // Even with the same external TMDS asic, it's possible that the program seqence alters 8249 // due to design. This ID is used to alert driver that the sequence is not "standard"! 8250 UCHAR ucMasterAddress; // Address to control Master xTMDS Chip 8251 UCHAR ucSlaveAddress; // Address to control Slave xTMDS Chip 8252 }ATOM_XTMDS_INFO; 8253 8254 typedef struct _DFP_DPMS_STATUS_CHANGE_PARAMETERS 8255 { 8256 UCHAR ucEnable; // ATOM_ENABLE=On or ATOM_DISABLE=Off 8257 UCHAR ucDevice; // ATOM_DEVICE_DFP1_INDEX.... 8258 UCHAR ucPadding[2]; 8259 }DFP_DPMS_STATUS_CHANGE_PARAMETERS; 8260 8261 /****************************Legacy Power Play Table Definitions **********************/ 8262 8263 //Definitions for ulPowerPlayMiscInfo 8264 #define ATOM_PM_MISCINFO_SPLIT_CLOCK 0x00000000L 8265 #define ATOM_PM_MISCINFO_USING_MCLK_SRC 0x00000001L 8266 #define ATOM_PM_MISCINFO_USING_SCLK_SRC 0x00000002L 8267 8268 #define ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT 0x00000004L 8269 #define ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH 0x00000008L 8270 8271 #define ATOM_PM_MISCINFO_LOAD_PERFORMANCE_EN 0x00000010L 8272 8273 #define ATOM_PM_MISCINFO_ENGINE_CLOCK_CONTRL_EN 0x00000020L 8274 #define ATOM_PM_MISCINFO_MEMORY_CLOCK_CONTRL_EN 0x00000040L 8275 #define ATOM_PM_MISCINFO_PROGRAM_VOLTAGE 0x00000080L //When this bit set, ucVoltageDropIndex is not an index for GPIO pin, but a voltage ID that SW needs program 8276 8277 #define ATOM_PM_MISCINFO_ASIC_REDUCED_SPEED_SCLK_EN 0x00000100L 8278 #define ATOM_PM_MISCINFO_ASIC_DYNAMIC_VOLTAGE_EN 0x00000200L 8279 #define ATOM_PM_MISCINFO_ASIC_SLEEP_MODE_EN 0x00000400L 8280 #define ATOM_PM_MISCINFO_LOAD_BALANCE_EN 0x00000800L 8281 #define ATOM_PM_MISCINFO_DEFAULT_DC_STATE_ENTRY_TRUE 0x00001000L 8282 #define ATOM_PM_MISCINFO_DEFAULT_LOW_DC_STATE_ENTRY_TRUE 0x00002000L 8283 #define ATOM_PM_MISCINFO_LOW_LCD_REFRESH_RATE 0x00004000L 8284 8285 #define ATOM_PM_MISCINFO_DRIVER_DEFAULT_MODE 0x00008000L 8286 #define ATOM_PM_MISCINFO_OVER_CLOCK_MODE 0x00010000L 8287 #define ATOM_PM_MISCINFO_OVER_DRIVE_MODE 0x00020000L 8288 #define ATOM_PM_MISCINFO_POWER_SAVING_MODE 0x00040000L 8289 #define ATOM_PM_MISCINFO_THERMAL_DIODE_MODE 0x00080000L 8290 8291 #define ATOM_PM_MISCINFO_FRAME_MODULATION_MASK 0x00300000L //0-FM Disable, 1-2 level FM, 2-4 level FM, 3-Reserved 8292 #define ATOM_PM_MISCINFO_FRAME_MODULATION_SHIFT 20 8293 8294 #define ATOM_PM_MISCINFO_DYN_CLK_3D_IDLE 0x00400000L 8295 #define ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_2 0x00800000L 8296 #define ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_4 0x01000000L 8297 #define ATOM_PM_MISCINFO_DYNAMIC_HDP_BLOCK_EN 0x02000000L //When set, Dynamic 8298 #define ATOM_PM_MISCINFO_DYNAMIC_MC_HOST_BLOCK_EN 0x04000000L //When set, Dynamic 8299 #define ATOM_PM_MISCINFO_3D_ACCELERATION_EN 0x08000000L //When set, This mode is for acceleated 3D mode 8300 8301 #define ATOM_PM_MISCINFO_POWERPLAY_SETTINGS_GROUP_MASK 0x70000000L //1-Optimal Battery Life Group, 2-High Battery, 3-Balanced, 4-High Performance, 5- Optimal Performance (Default state with Default clocks) 8302 #define ATOM_PM_MISCINFO_POWERPLAY_SETTINGS_GROUP_SHIFT 28 8303 #define ATOM_PM_MISCINFO_ENABLE_BACK_BIAS 0x80000000L 8304 8305 #define ATOM_PM_MISCINFO2_SYSTEM_AC_LITE_MODE 0x00000001L 8306 #define ATOM_PM_MISCINFO2_MULTI_DISPLAY_SUPPORT 0x00000002L 8307 #define ATOM_PM_MISCINFO2_DYNAMIC_BACK_BIAS_EN 0x00000004L 8308 #define ATOM_PM_MISCINFO2_FS3D_OVERDRIVE_INFO 0x00000008L 8309 #define ATOM_PM_MISCINFO2_FORCEDLOWPWR_MODE 0x00000010L 8310 #define ATOM_PM_MISCINFO2_VDDCI_DYNAMIC_VOLTAGE_EN 0x00000020L 8311 #define ATOM_PM_MISCINFO2_VIDEO_PLAYBACK_CAPABLE 0x00000040L //If this bit is set in multi-pp mode, then driver will pack up one with the minior power consumption. 8312 //If it's not set in any pp mode, driver will use its default logic to pick a pp mode in video playback 8313 #define ATOM_PM_MISCINFO2_NOT_VALID_ON_DC 0x00000080L 8314 #define ATOM_PM_MISCINFO2_STUTTER_MODE_EN 0x00000100L 8315 #define ATOM_PM_MISCINFO2_UVD_SUPPORT_MODE 0x00000200L 8316 8317 //ucTableFormatRevision=1 8318 //ucTableContentRevision=1 8319 typedef struct _ATOM_POWERMODE_INFO 8320 { 8321 ULONG ulMiscInfo; //The power level should be arranged in ascending order 8322 ULONG ulReserved1; // must set to 0 8323 ULONG ulReserved2; // must set to 0 8324 USHORT usEngineClock; 8325 USHORT usMemoryClock; 8326 UCHAR ucVoltageDropIndex; // index to GPIO table 8327 UCHAR ucSelectedPanel_RefreshRate;// panel refresh rate 8328 UCHAR ucMinTemperature; 8329 UCHAR ucMaxTemperature; 8330 UCHAR ucNumPciELanes; // number of PCIE lanes 8331 }ATOM_POWERMODE_INFO; 8332 8333 //ucTableFormatRevision=2 8334 //ucTableContentRevision=1 8335 typedef struct _ATOM_POWERMODE_INFO_V2 8336 { 8337 ULONG ulMiscInfo; //The power level should be arranged in ascending order 8338 ULONG ulMiscInfo2; 8339 ULONG ulEngineClock; 8340 ULONG ulMemoryClock; 8341 UCHAR ucVoltageDropIndex; // index to GPIO table 8342 UCHAR ucSelectedPanel_RefreshRate;// panel refresh rate 8343 UCHAR ucMinTemperature; 8344 UCHAR ucMaxTemperature; 8345 UCHAR ucNumPciELanes; // number of PCIE lanes 8346 }ATOM_POWERMODE_INFO_V2; 8347 8348 //ucTableFormatRevision=2 8349 //ucTableContentRevision=2 8350 typedef struct _ATOM_POWERMODE_INFO_V3 8351 { 8352 ULONG ulMiscInfo; //The power level should be arranged in ascending order 8353 ULONG ulMiscInfo2; 8354 ULONG ulEngineClock; 8355 ULONG ulMemoryClock; 8356 UCHAR ucVoltageDropIndex; // index to Core (VDDC) votage table 8357 UCHAR ucSelectedPanel_RefreshRate;// panel refresh rate 8358 UCHAR ucMinTemperature; 8359 UCHAR ucMaxTemperature; 8360 UCHAR ucNumPciELanes; // number of PCIE lanes 8361 UCHAR ucVDDCI_VoltageDropIndex; // index to VDDCI votage table 8362 }ATOM_POWERMODE_INFO_V3; 8363 8364 8365 #define ATOM_MAX_NUMBEROF_POWER_BLOCK 8 8366 8367 #define ATOM_PP_OVERDRIVE_INTBITMAP_AUXWIN 0x01 8368 #define ATOM_PP_OVERDRIVE_INTBITMAP_OVERDRIVE 0x02 8369 8370 #define ATOM_PP_OVERDRIVE_THERMALCONTROLLER_LM63 0x01 8371 #define ATOM_PP_OVERDRIVE_THERMALCONTROLLER_ADM1032 0x02 8372 #define ATOM_PP_OVERDRIVE_THERMALCONTROLLER_ADM1030 0x03 8373 #define ATOM_PP_OVERDRIVE_THERMALCONTROLLER_MUA6649 0x04 8374 #define ATOM_PP_OVERDRIVE_THERMALCONTROLLER_LM64 0x05 8375 #define ATOM_PP_OVERDRIVE_THERMALCONTROLLER_F75375 0x06 8376 #define ATOM_PP_OVERDRIVE_THERMALCONTROLLER_ASC7512 0x07 // Andigilog 8377 8378 8379 typedef struct _ATOM_POWERPLAY_INFO 8380 { 8381 ATOM_COMMON_TABLE_HEADER sHeader; 8382 UCHAR ucOverdriveThermalController; 8383 UCHAR ucOverdriveI2cLine; 8384 UCHAR ucOverdriveIntBitmap; 8385 UCHAR ucOverdriveControllerAddress; 8386 UCHAR ucSizeOfPowerModeEntry; 8387 UCHAR ucNumOfPowerModeEntries; 8388 ATOM_POWERMODE_INFO asPowerPlayInfo[ATOM_MAX_NUMBEROF_POWER_BLOCK]; 8389 }ATOM_POWERPLAY_INFO; 8390 8391 typedef struct _ATOM_POWERPLAY_INFO_V2 8392 { 8393 ATOM_COMMON_TABLE_HEADER sHeader; 8394 UCHAR ucOverdriveThermalController; 8395 UCHAR ucOverdriveI2cLine; 8396 UCHAR ucOverdriveIntBitmap; 8397 UCHAR ucOverdriveControllerAddress; 8398 UCHAR ucSizeOfPowerModeEntry; 8399 UCHAR ucNumOfPowerModeEntries; 8400 ATOM_POWERMODE_INFO_V2 asPowerPlayInfo[ATOM_MAX_NUMBEROF_POWER_BLOCK]; 8401 }ATOM_POWERPLAY_INFO_V2; 8402 8403 typedef struct _ATOM_POWERPLAY_INFO_V3 8404 { 8405 ATOM_COMMON_TABLE_HEADER sHeader; 8406 UCHAR ucOverdriveThermalController; 8407 UCHAR ucOverdriveI2cLine; 8408 UCHAR ucOverdriveIntBitmap; 8409 UCHAR ucOverdriveControllerAddress; 8410 UCHAR ucSizeOfPowerModeEntry; 8411 UCHAR ucNumOfPowerModeEntries; 8412 ATOM_POWERMODE_INFO_V3 asPowerPlayInfo[ATOM_MAX_NUMBEROF_POWER_BLOCK]; 8413 }ATOM_POWERPLAY_INFO_V3; 8414 8415 8416 8417 /**************************************************************************/ 8418 8419 8420 // Following definitions are for compatiblity issue in different SW components. 8421 #define ATOM_MASTER_DATA_TABLE_REVISION 0x01 8422 #define Object_Info Object_Header 8423 #define AdjustARB_SEQ MC_InitParameter 8424 #define VRAM_GPIO_DetectionInfo VoltageObjectInfo 8425 #define ASIC_VDDCI_Info ASIC_ProfilingInfo 8426 #define ASIC_MVDDQ_Info MemoryTrainingInfo 8427 #define SS_Info PPLL_SS_Info 8428 #define ASIC_MVDDC_Info ASIC_InternalSS_Info 8429 #define DispDevicePriorityInfo SaveRestoreInfo 8430 #define DispOutInfo TV_VideoMode 8431 8432 8433 #define ATOM_ENCODER_OBJECT_TABLE ATOM_OBJECT_TABLE 8434 #define ATOM_CONNECTOR_OBJECT_TABLE ATOM_OBJECT_TABLE 8435 8436 //New device naming, remove them when both DAL/VBIOS is ready 8437 #define DFP2I_OUTPUT_CONTROL_PARAMETERS CRT1_OUTPUT_CONTROL_PARAMETERS 8438 #define DFP2I_OUTPUT_CONTROL_PS_ALLOCATION DFP2I_OUTPUT_CONTROL_PARAMETERS 8439 8440 #define DFP1X_OUTPUT_CONTROL_PARAMETERS CRT1_OUTPUT_CONTROL_PARAMETERS 8441 #define DFP1X_OUTPUT_CONTROL_PS_ALLOCATION DFP1X_OUTPUT_CONTROL_PARAMETERS 8442 8443 #define DFP1I_OUTPUT_CONTROL_PARAMETERS DFP1_OUTPUT_CONTROL_PARAMETERS 8444 #define DFP1I_OUTPUT_CONTROL_PS_ALLOCATION DFP1_OUTPUT_CONTROL_PS_ALLOCATION 8445 8446 #define ATOM_DEVICE_DFP1I_SUPPORT ATOM_DEVICE_DFP1_SUPPORT 8447 #define ATOM_DEVICE_DFP1X_SUPPORT ATOM_DEVICE_DFP2_SUPPORT 8448 8449 #define ATOM_DEVICE_DFP1I_INDEX ATOM_DEVICE_DFP1_INDEX 8450 #define ATOM_DEVICE_DFP1X_INDEX ATOM_DEVICE_DFP2_INDEX 8451 8452 #define ATOM_DEVICE_DFP2I_INDEX 0x00000009 8453 #define ATOM_DEVICE_DFP2I_SUPPORT (0x1L << ATOM_DEVICE_DFP2I_INDEX) 8454 8455 #define ATOM_S0_DFP1I ATOM_S0_DFP1 8456 #define ATOM_S0_DFP1X ATOM_S0_DFP2 8457 8458 #define ATOM_S0_DFP2I 0x00200000L 8459 #define ATOM_S0_DFP2Ib2 0x20 8460 8461 #define ATOM_S2_DFP1I_DPMS_STATE ATOM_S2_DFP1_DPMS_STATE 8462 #define ATOM_S2_DFP1X_DPMS_STATE ATOM_S2_DFP2_DPMS_STATE 8463 8464 #define ATOM_S2_DFP2I_DPMS_STATE 0x02000000L 8465 #define ATOM_S2_DFP2I_DPMS_STATEb3 0x02 8466 8467 #define ATOM_S3_DFP2I_ACTIVEb1 0x02 8468 8469 #define ATOM_S3_DFP1I_ACTIVE ATOM_S3_DFP1_ACTIVE 8470 #define ATOM_S3_DFP1X_ACTIVE ATOM_S3_DFP2_ACTIVE 8471 8472 #define ATOM_S3_DFP2I_ACTIVE 0x00000200L 8473 8474 #define ATOM_S3_DFP1I_CRTC_ACTIVE ATOM_S3_DFP1_CRTC_ACTIVE 8475 #define ATOM_S3_DFP1X_CRTC_ACTIVE ATOM_S3_DFP2_CRTC_ACTIVE 8476 #define ATOM_S3_DFP2I_CRTC_ACTIVE 0x02000000L 8477 8478 8479 #define ATOM_S3_DFP2I_CRTC_ACTIVEb3 0x02 8480 #define ATOM_S5_DOS_REQ_DFP2Ib1 0x02 8481 8482 #define ATOM_S5_DOS_REQ_DFP2I 0x0200 8483 #define ATOM_S6_ACC_REQ_DFP1I ATOM_S6_ACC_REQ_DFP1 8484 #define ATOM_S6_ACC_REQ_DFP1X ATOM_S6_ACC_REQ_DFP2 8485 8486 #define ATOM_S6_ACC_REQ_DFP2Ib3 0x02 8487 #define ATOM_S6_ACC_REQ_DFP2I 0x02000000L 8488 8489 #define TMDS1XEncoderControl DVOEncoderControl 8490 #define DFP1XOutputControl DVOOutputControl 8491 8492 #define ExternalDFPOutputControl DFP1XOutputControl 8493 #define EnableExternalTMDS_Encoder TMDS1XEncoderControl 8494 8495 #define DFP1IOutputControl TMDSAOutputControl 8496 #define DFP2IOutputControl LVTMAOutputControl 8497 8498 #define DAC1_ENCODER_CONTROL_PARAMETERS DAC_ENCODER_CONTROL_PARAMETERS 8499 #define DAC1_ENCODER_CONTROL_PS_ALLOCATION DAC_ENCODER_CONTROL_PS_ALLOCATION 8500 8501 #define DAC2_ENCODER_CONTROL_PARAMETERS DAC_ENCODER_CONTROL_PARAMETERS 8502 #define DAC2_ENCODER_CONTROL_PS_ALLOCATION DAC_ENCODER_CONTROL_PS_ALLOCATION 8503 8504 #define ucDac1Standard ucDacStandard 8505 #define ucDac2Standard ucDacStandard 8506 8507 #define TMDS1EncoderControl TMDSAEncoderControl 8508 #define TMDS2EncoderControl LVTMAEncoderControl 8509 8510 #define DFP1OutputControl TMDSAOutputControl 8511 #define DFP2OutputControl LVTMAOutputControl 8512 #define CRT1OutputControl DAC1OutputControl 8513 #define CRT2OutputControl DAC2OutputControl 8514 8515 //These two lines will be removed for sure in a few days, will follow up with Michael V. 8516 #define EnableLVDS_SS EnableSpreadSpectrumOnPPLL 8517 #define ENABLE_LVDS_SS_PARAMETERS_V3 ENABLE_SPREAD_SPECTRUM_ON_PPLL 8518 8519 #define ATOM_S2_CRT1_DPMS_STATE 0x00010000L 8520 #define ATOM_S2_LCD1_DPMS_STATE ATOM_S2_CRT1_DPMS_STATE 8521 #define ATOM_S2_TV1_DPMS_STATE ATOM_S2_CRT1_DPMS_STATE 8522 #define ATOM_S2_DFP1_DPMS_STATE ATOM_S2_CRT1_DPMS_STATE 8523 #define ATOM_S2_CRT2_DPMS_STATE ATOM_S2_CRT1_DPMS_STATE 8524 8525 #define ATOM_S6_ACC_REQ_TV2 0x00400000L 8526 #define ATOM_DEVICE_TV2_INDEX 0x00000006 8527 #define ATOM_DEVICE_TV2_SUPPORT (0x1L << ATOM_DEVICE_TV2_INDEX) 8528 #define ATOM_S0_TV2 0x00100000L 8529 #define ATOM_S3_TV2_ACTIVE ATOM_S3_DFP6_ACTIVE 8530 #define ATOM_S3_TV2_CRTC_ACTIVE ATOM_S3_DFP6_CRTC_ACTIVE 8531 8532 /*********************************************************************************/ 8533 8534 #pragma pack() // BIOS data must use byte aligment 8535 8536 #pragma pack(1) 8537 8538 typedef struct _ATOM_HOLE_INFO 8539 { 8540 USHORT usOffset; // offset of the hole ( from the start of the binary ) 8541 USHORT usLength; // length of the hole ( in bytes ) 8542 }ATOM_HOLE_INFO; 8543 8544 typedef struct _ATOM_SERVICE_DESCRIPTION 8545 { 8546 UCHAR ucRevision; // Holes set revision 8547 UCHAR ucAlgorithm; // Hash algorithm 8548 UCHAR ucSignatureType; // Signature type ( 0 - no signature, 1 - test, 2 - production ) 8549 UCHAR ucReserved; 8550 USHORT usSigOffset; // Signature offset ( from the start of the binary ) 8551 USHORT usSigLength; // Signature length 8552 }ATOM_SERVICE_DESCRIPTION; 8553 8554 8555 typedef struct _ATOM_SERVICE_INFO 8556 { 8557 ATOM_COMMON_TABLE_HEADER asHeader; 8558 ATOM_SERVICE_DESCRIPTION asDescr; 8559 UCHAR ucholesNo; // number of holes that follow 8560 ATOM_HOLE_INFO holes[1]; // array of hole descriptions 8561 }ATOM_SERVICE_INFO; 8562 8563 8564 8565 #pragma pack() // BIOS data must use byte aligment 8566 8567 // 8568 // AMD ACPI Table 8569 // 8570 #pragma pack(1) 8571 8572 typedef struct { 8573 ULONG Signature; 8574 ULONG TableLength; //Length 8575 UCHAR Revision; 8576 UCHAR Checksum; 8577 UCHAR OemId[6]; 8578 UCHAR OemTableId[8]; //UINT64 OemTableId; 8579 ULONG OemRevision; 8580 ULONG CreatorId; 8581 ULONG CreatorRevision; 8582 } AMD_ACPI_DESCRIPTION_HEADER; 8583 /* 8584 //EFI_ACPI_DESCRIPTION_HEADER from AcpiCommon.h 8585 typedef struct { 8586 UINT32 Signature; //0x0 8587 UINT32 Length; //0x4 8588 UINT8 Revision; //0x8 8589 UINT8 Checksum; //0x9 8590 UINT8 OemId[6]; //0xA 8591 UINT64 OemTableId; //0x10 8592 UINT32 OemRevision; //0x18 8593 UINT32 CreatorId; //0x1C 8594 UINT32 CreatorRevision; //0x20 8595 }EFI_ACPI_DESCRIPTION_HEADER; 8596 */ 8597 typedef struct { 8598 AMD_ACPI_DESCRIPTION_HEADER SHeader; 8599 UCHAR TableUUID[16]; //0x24 8600 ULONG VBIOSImageOffset; //0x34. Offset to the first GOP_VBIOS_CONTENT block from the beginning of the stucture. 8601 ULONG Lib1ImageOffset; //0x38. Offset to the first GOP_LIB1_CONTENT block from the beginning of the stucture. 8602 ULONG Reserved[4]; //0x3C 8603 }UEFI_ACPI_VFCT; 8604 8605 typedef struct { 8606 ULONG PCIBus; //0x4C 8607 ULONG PCIDevice; //0x50 8608 ULONG PCIFunction; //0x54 8609 USHORT VendorID; //0x58 8610 USHORT DeviceID; //0x5A 8611 USHORT SSVID; //0x5C 8612 USHORT SSID; //0x5E 8613 ULONG Revision; //0x60 8614 ULONG ImageLength; //0x64 8615 }VFCT_IMAGE_HEADER; 8616 8617 8618 typedef struct { 8619 VFCT_IMAGE_HEADER VbiosHeader; 8620 UCHAR VbiosContent[1]; 8621 }GOP_VBIOS_CONTENT; 8622 8623 typedef struct { 8624 VFCT_IMAGE_HEADER Lib1Header; 8625 UCHAR Lib1Content[1]; 8626 }GOP_LIB1_CONTENT; 8627 8628 #pragma pack() 8629 8630 8631 #endif /* _ATOMBIOS_H */ 8632 8633 #include "pptable.h" 8634 8635