1c54a60dbSLeo Liu /* 2c54a60dbSLeo Liu * Copyright (C) 2019 Advanced Micro Devices, Inc. 3c54a60dbSLeo Liu * 4c54a60dbSLeo Liu * Permission is hereby granted, free of charge, to any person obtaining a 5c54a60dbSLeo Liu * copy of this software and associated documentation files (the "Software"), 6c54a60dbSLeo Liu * to deal in the Software without restriction, including without limitation 7c54a60dbSLeo Liu * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8c54a60dbSLeo Liu * and/or sell copies of the Software, and to permit persons to whom the 9c54a60dbSLeo Liu * Software is furnished to do so, subject to the following conditions: 10c54a60dbSLeo Liu * 11c54a60dbSLeo Liu * The above copyright notice and this permission notice shall be included 12c54a60dbSLeo Liu * in all copies or substantial portions of the Software. 13c54a60dbSLeo Liu * 14c54a60dbSLeo Liu * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 15c54a60dbSLeo Liu * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16c54a60dbSLeo Liu * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17c54a60dbSLeo Liu * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN 18c54a60dbSLeo Liu * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 19c54a60dbSLeo Liu * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 20c54a60dbSLeo Liu */ 21c54a60dbSLeo Liu 22c54a60dbSLeo Liu #ifndef _vcn_2_5_OFFSET_HEADER 23c54a60dbSLeo Liu #define _vcn_2_5_OFFSET_HEADER 24c54a60dbSLeo Liu 25c54a60dbSLeo Liu // addressBlock: uvd0_mmsch_dec 26c54a60dbSLeo Liu // base address: 0x1e000 27c54a60dbSLeo Liu 28c54a60dbSLeo Liu 29c54a60dbSLeo Liu // addressBlock: uvd0_jpegnpdec 30c54a60dbSLeo Liu // base address: 0x1e200 31c54a60dbSLeo Liu #define mmUVD_JPEG_CNTL 0x0080 32c54a60dbSLeo Liu #define mmUVD_JPEG_CNTL_BASE_IDX 0 33c54a60dbSLeo Liu #define mmUVD_JPEG_RB_BASE 0x0081 34c54a60dbSLeo Liu #define mmUVD_JPEG_RB_BASE_BASE_IDX 0 35c54a60dbSLeo Liu #define mmUVD_JPEG_RB_WPTR 0x0082 36c54a60dbSLeo Liu #define mmUVD_JPEG_RB_WPTR_BASE_IDX 0 37c54a60dbSLeo Liu #define mmUVD_JPEG_RB_RPTR 0x0083 38c54a60dbSLeo Liu #define mmUVD_JPEG_RB_RPTR_BASE_IDX 0 39c54a60dbSLeo Liu #define mmUVD_JPEG_RB_SIZE 0x0084 40c54a60dbSLeo Liu #define mmUVD_JPEG_RB_SIZE_BASE_IDX 0 41c54a60dbSLeo Liu #define mmUVD_JPEG_DEC_SCRATCH0 0x0089 42c54a60dbSLeo Liu #define mmUVD_JPEG_DEC_SCRATCH0_BASE_IDX 0 43c54a60dbSLeo Liu #define mmUVD_JPEG_INT_EN 0x008a 44c54a60dbSLeo Liu #define mmUVD_JPEG_INT_EN_BASE_IDX 0 45c54a60dbSLeo Liu #define mmUVD_JPEG_INT_STAT 0x008b 46c54a60dbSLeo Liu #define mmUVD_JPEG_INT_STAT_BASE_IDX 0 47c54a60dbSLeo Liu #define mmUVD_JPEG_PITCH 0x009f 48c54a60dbSLeo Liu #define mmUVD_JPEG_PITCH_BASE_IDX 0 49c54a60dbSLeo Liu #define mmUVD_JPEG_UV_PITCH 0x00a0 50c54a60dbSLeo Liu #define mmUVD_JPEG_UV_PITCH_BASE_IDX 0 51c54a60dbSLeo Liu #define mmJPEG_DEC_Y_GFX8_TILING_SURFACE 0x00a1 52c54a60dbSLeo Liu #define mmJPEG_DEC_Y_GFX8_TILING_SURFACE_BASE_IDX 0 53c54a60dbSLeo Liu #define mmJPEG_DEC_UV_GFX8_TILING_SURFACE 0x00a2 54c54a60dbSLeo Liu #define mmJPEG_DEC_UV_GFX8_TILING_SURFACE_BASE_IDX 0 55c54a60dbSLeo Liu #define mmJPEG_DEC_GFX8_ADDR_CONFIG 0x00a3 56c54a60dbSLeo Liu #define mmJPEG_DEC_GFX8_ADDR_CONFIG_BASE_IDX 0 57c54a60dbSLeo Liu #define mmJPEG_DEC_Y_GFX10_TILING_SURFACE 0x00a4 58c54a60dbSLeo Liu #define mmJPEG_DEC_Y_GFX10_TILING_SURFACE_BASE_IDX 0 59c54a60dbSLeo Liu #define mmJPEG_DEC_UV_GFX10_TILING_SURFACE 0x00a5 60c54a60dbSLeo Liu #define mmJPEG_DEC_UV_GFX10_TILING_SURFACE_BASE_IDX 0 61c54a60dbSLeo Liu #define mmJPEG_DEC_GFX10_ADDR_CONFIG 0x00a6 62c54a60dbSLeo Liu #define mmJPEG_DEC_GFX10_ADDR_CONFIG_BASE_IDX 0 63c54a60dbSLeo Liu #define mmJPEG_DEC_ADDR_MODE 0x00a7 64c54a60dbSLeo Liu #define mmJPEG_DEC_ADDR_MODE_BASE_IDX 0 65c54a60dbSLeo Liu #define mmUVD_JPEG_GPCOM_CMD 0x00a9 66c54a60dbSLeo Liu #define mmUVD_JPEG_GPCOM_CMD_BASE_IDX 0 67c54a60dbSLeo Liu #define mmUVD_JPEG_GPCOM_DATA0 0x00aa 68c54a60dbSLeo Liu #define mmUVD_JPEG_GPCOM_DATA0_BASE_IDX 0 69c54a60dbSLeo Liu #define mmUVD_JPEG_GPCOM_DATA1 0x00ab 70c54a60dbSLeo Liu #define mmUVD_JPEG_GPCOM_DATA1_BASE_IDX 0 71c54a60dbSLeo Liu #define mmUVD_JPEG_SCRATCH1 0x00ae 72c54a60dbSLeo Liu #define mmUVD_JPEG_SCRATCH1_BASE_IDX 0 73c54a60dbSLeo Liu #define mmUVD_JPEG_DEC_SOFT_RST 0x00af 74c54a60dbSLeo Liu #define mmUVD_JPEG_DEC_SOFT_RST_BASE_IDX 0 75c54a60dbSLeo Liu 76c54a60dbSLeo Liu 77c54a60dbSLeo Liu // addressBlock: uvd0_uvd_jpeg_enc_dec 78c54a60dbSLeo Liu // base address: 0x1e300 79c54a60dbSLeo Liu #define mmUVD_JPEG_ENC_INT_EN 0x00c1 80c54a60dbSLeo Liu #define mmUVD_JPEG_ENC_INT_EN_BASE_IDX 0 81c54a60dbSLeo Liu #define mmUVD_JPEG_ENC_INT_STATUS 0x00c2 82c54a60dbSLeo Liu #define mmUVD_JPEG_ENC_INT_STATUS_BASE_IDX 0 83c54a60dbSLeo Liu #define mmUVD_JPEG_ENC_ENGINE_CNTL 0x00c5 84c54a60dbSLeo Liu #define mmUVD_JPEG_ENC_ENGINE_CNTL_BASE_IDX 0 85c54a60dbSLeo Liu #define mmUVD_JPEG_ENC_SCRATCH1 0x00ce 86c54a60dbSLeo Liu #define mmUVD_JPEG_ENC_SCRATCH1_BASE_IDX 0 87c54a60dbSLeo Liu 88c54a60dbSLeo Liu 89c54a60dbSLeo Liu // addressBlock: uvd0_uvd_jpeg_enc_sclk_dec 90c54a60dbSLeo Liu // base address: 0x1e380 91c54a60dbSLeo Liu #define mmUVD_JPEG_ENC_STATUS 0x00e5 92c54a60dbSLeo Liu #define mmUVD_JPEG_ENC_STATUS_BASE_IDX 0 93c54a60dbSLeo Liu #define mmUVD_JPEG_ENC_PITCH 0x00e6 94c54a60dbSLeo Liu #define mmUVD_JPEG_ENC_PITCH_BASE_IDX 0 95c54a60dbSLeo Liu #define mmUVD_JPEG_ENC_LUMA_BASE 0x00e7 96c54a60dbSLeo Liu #define mmUVD_JPEG_ENC_LUMA_BASE_BASE_IDX 0 97c54a60dbSLeo Liu #define mmUVD_JPEG_ENC_CHROMAU_BASE 0x00e8 98c54a60dbSLeo Liu #define mmUVD_JPEG_ENC_CHROMAU_BASE_BASE_IDX 0 99c54a60dbSLeo Liu #define mmUVD_JPEG_ENC_CHROMAV_BASE 0x00e9 100c54a60dbSLeo Liu #define mmUVD_JPEG_ENC_CHROMAV_BASE_BASE_IDX 0 101c54a60dbSLeo Liu #define mmJPEG_ENC_Y_GFX10_TILING_SURFACE 0x00ea 102c54a60dbSLeo Liu #define mmJPEG_ENC_Y_GFX10_TILING_SURFACE_BASE_IDX 0 103c54a60dbSLeo Liu #define mmJPEG_ENC_UV_GFX10_TILING_SURFACE 0x00eb 104c54a60dbSLeo Liu #define mmJPEG_ENC_UV_GFX10_TILING_SURFACE_BASE_IDX 0 105c54a60dbSLeo Liu #define mmJPEG_ENC_GFX10_ADDR_CONFIG 0x00ec 106c54a60dbSLeo Liu #define mmJPEG_ENC_GFX10_ADDR_CONFIG_BASE_IDX 0 107c54a60dbSLeo Liu #define mmJPEG_ENC_ADDR_MODE 0x00ed 108c54a60dbSLeo Liu #define mmJPEG_ENC_ADDR_MODE_BASE_IDX 0 109c54a60dbSLeo Liu #define mmUVD_JPEG_ENC_GPCOM_CMD 0x00ee 110c54a60dbSLeo Liu #define mmUVD_JPEG_ENC_GPCOM_CMD_BASE_IDX 0 111c54a60dbSLeo Liu #define mmUVD_JPEG_ENC_GPCOM_DATA0 0x00ef 112c54a60dbSLeo Liu #define mmUVD_JPEG_ENC_GPCOM_DATA0_BASE_IDX 0 113c54a60dbSLeo Liu #define mmUVD_JPEG_ENC_GPCOM_DATA1 0x00f0 114c54a60dbSLeo Liu #define mmUVD_JPEG_ENC_GPCOM_DATA1_BASE_IDX 0 115c54a60dbSLeo Liu #define mmUVD_JPEG_ENC_CGC_CNTL 0x00f5 116c54a60dbSLeo Liu #define mmUVD_JPEG_ENC_CGC_CNTL_BASE_IDX 0 117c54a60dbSLeo Liu #define mmUVD_JPEG_ENC_SCRATCH0 0x00f6 118c54a60dbSLeo Liu #define mmUVD_JPEG_ENC_SCRATCH0_BASE_IDX 0 119c54a60dbSLeo Liu #define mmUVD_JPEG_ENC_SOFT_RST 0x00f7 120c54a60dbSLeo Liu #define mmUVD_JPEG_ENC_SOFT_RST_BASE_IDX 0 121c54a60dbSLeo Liu 122c54a60dbSLeo Liu 123c54a60dbSLeo Liu // addressBlock: uvd0_uvd_jrbc_dec 124c54a60dbSLeo Liu // base address: 0x1e400 125c54a60dbSLeo Liu #define mmUVD_JRBC_RB_WPTR 0x0100 126c54a60dbSLeo Liu #define mmUVD_JRBC_RB_WPTR_BASE_IDX 0 127c54a60dbSLeo Liu #define mmUVD_JRBC_RB_CNTL 0x0101 128c54a60dbSLeo Liu #define mmUVD_JRBC_RB_CNTL_BASE_IDX 0 129c54a60dbSLeo Liu #define mmUVD_JRBC_IB_SIZE 0x0102 130c54a60dbSLeo Liu #define mmUVD_JRBC_IB_SIZE_BASE_IDX 0 131c54a60dbSLeo Liu #define mmUVD_JRBC_URGENT_CNTL 0x0103 132c54a60dbSLeo Liu #define mmUVD_JRBC_URGENT_CNTL_BASE_IDX 0 133c54a60dbSLeo Liu #define mmUVD_JRBC_RB_REF_DATA 0x0104 134c54a60dbSLeo Liu #define mmUVD_JRBC_RB_REF_DATA_BASE_IDX 0 135c54a60dbSLeo Liu #define mmUVD_JRBC_RB_COND_RD_TIMER 0x0105 136c54a60dbSLeo Liu #define mmUVD_JRBC_RB_COND_RD_TIMER_BASE_IDX 0 137c54a60dbSLeo Liu #define mmUVD_JRBC_SOFT_RESET 0x0108 138c54a60dbSLeo Liu #define mmUVD_JRBC_SOFT_RESET_BASE_IDX 0 139c54a60dbSLeo Liu #define mmUVD_JRBC_STATUS 0x0109 140c54a60dbSLeo Liu #define mmUVD_JRBC_STATUS_BASE_IDX 0 141c54a60dbSLeo Liu #define mmUVD_JRBC_RB_RPTR 0x010a 142c54a60dbSLeo Liu #define mmUVD_JRBC_RB_RPTR_BASE_IDX 0 143c54a60dbSLeo Liu #define mmUVD_JRBC_RB_BUF_STATUS 0x010b 144c54a60dbSLeo Liu #define mmUVD_JRBC_RB_BUF_STATUS_BASE_IDX 0 145c54a60dbSLeo Liu #define mmUVD_JRBC_IB_BUF_STATUS 0x010c 146c54a60dbSLeo Liu #define mmUVD_JRBC_IB_BUF_STATUS_BASE_IDX 0 147c54a60dbSLeo Liu #define mmUVD_JRBC_IB_SIZE_UPDATE 0x010d 148c54a60dbSLeo Liu #define mmUVD_JRBC_IB_SIZE_UPDATE_BASE_IDX 0 149c54a60dbSLeo Liu #define mmUVD_JRBC_IB_COND_RD_TIMER 0x010e 150c54a60dbSLeo Liu #define mmUVD_JRBC_IB_COND_RD_TIMER_BASE_IDX 0 151c54a60dbSLeo Liu #define mmUVD_JRBC_IB_REF_DATA 0x010f 152c54a60dbSLeo Liu #define mmUVD_JRBC_IB_REF_DATA_BASE_IDX 0 153c54a60dbSLeo Liu #define mmUVD_JPEG_PREEMPT_CMD 0x0110 154c54a60dbSLeo Liu #define mmUVD_JPEG_PREEMPT_CMD_BASE_IDX 0 155c54a60dbSLeo Liu #define mmUVD_JPEG_PREEMPT_FENCE_DATA0 0x0111 156c54a60dbSLeo Liu #define mmUVD_JPEG_PREEMPT_FENCE_DATA0_BASE_IDX 0 157c54a60dbSLeo Liu #define mmUVD_JPEG_PREEMPT_FENCE_DATA1 0x0112 158c54a60dbSLeo Liu #define mmUVD_JPEG_PREEMPT_FENCE_DATA1_BASE_IDX 0 159c54a60dbSLeo Liu #define mmUVD_JRBC_RB_SIZE 0x0113 160c54a60dbSLeo Liu #define mmUVD_JRBC_RB_SIZE_BASE_IDX 0 161c54a60dbSLeo Liu #define mmUVD_JRBC_SCRATCH0 0x0114 162c54a60dbSLeo Liu #define mmUVD_JRBC_SCRATCH0_BASE_IDX 0 163c54a60dbSLeo Liu 164c54a60dbSLeo Liu 165c54a60dbSLeo Liu // addressBlock: uvd0_uvd_jrbc_enc_dec 166c54a60dbSLeo Liu // base address: 0x1e480 167c54a60dbSLeo Liu #define mmUVD_JRBC_ENC_RB_WPTR 0x0120 168c54a60dbSLeo Liu #define mmUVD_JRBC_ENC_RB_WPTR_BASE_IDX 0 169c54a60dbSLeo Liu #define mmUVD_JRBC_ENC_RB_CNTL 0x0121 170c54a60dbSLeo Liu #define mmUVD_JRBC_ENC_RB_CNTL_BASE_IDX 0 171c54a60dbSLeo Liu #define mmUVD_JRBC_ENC_IB_SIZE 0x0122 172c54a60dbSLeo Liu #define mmUVD_JRBC_ENC_IB_SIZE_BASE_IDX 0 173c54a60dbSLeo Liu #define mmUVD_JRBC_ENC_URGENT_CNTL 0x0123 174c54a60dbSLeo Liu #define mmUVD_JRBC_ENC_URGENT_CNTL_BASE_IDX 0 175c54a60dbSLeo Liu #define mmUVD_JRBC_ENC_RB_REF_DATA 0x0124 176c54a60dbSLeo Liu #define mmUVD_JRBC_ENC_RB_REF_DATA_BASE_IDX 0 177c54a60dbSLeo Liu #define mmUVD_JRBC_ENC_RB_COND_RD_TIMER 0x0125 178c54a60dbSLeo Liu #define mmUVD_JRBC_ENC_RB_COND_RD_TIMER_BASE_IDX 0 179c54a60dbSLeo Liu #define mmUVD_JRBC_ENC_SOFT_RESET 0x0128 180c54a60dbSLeo Liu #define mmUVD_JRBC_ENC_SOFT_RESET_BASE_IDX 0 181c54a60dbSLeo Liu #define mmUVD_JRBC_ENC_STATUS 0x0129 182c54a60dbSLeo Liu #define mmUVD_JRBC_ENC_STATUS_BASE_IDX 0 183c54a60dbSLeo Liu #define mmUVD_JRBC_ENC_RB_RPTR 0x012a 184c54a60dbSLeo Liu #define mmUVD_JRBC_ENC_RB_RPTR_BASE_IDX 0 185c54a60dbSLeo Liu #define mmUVD_JRBC_ENC_RB_BUF_STATUS 0x012b 186c54a60dbSLeo Liu #define mmUVD_JRBC_ENC_RB_BUF_STATUS_BASE_IDX 0 187c54a60dbSLeo Liu #define mmUVD_JRBC_ENC_IB_BUF_STATUS 0x012c 188c54a60dbSLeo Liu #define mmUVD_JRBC_ENC_IB_BUF_STATUS_BASE_IDX 0 189c54a60dbSLeo Liu #define mmUVD_JRBC_ENC_IB_SIZE_UPDATE 0x012d 190c54a60dbSLeo Liu #define mmUVD_JRBC_ENC_IB_SIZE_UPDATE_BASE_IDX 0 191c54a60dbSLeo Liu #define mmUVD_JRBC_ENC_IB_COND_RD_TIMER 0x012e 192c54a60dbSLeo Liu #define mmUVD_JRBC_ENC_IB_COND_RD_TIMER_BASE_IDX 0 193c54a60dbSLeo Liu #define mmUVD_JRBC_ENC_IB_REF_DATA 0x012f 194c54a60dbSLeo Liu #define mmUVD_JRBC_ENC_IB_REF_DATA_BASE_IDX 0 195c54a60dbSLeo Liu #define mmUVD_JPEG_ENC_PREEMPT_CMD 0x0130 196c54a60dbSLeo Liu #define mmUVD_JPEG_ENC_PREEMPT_CMD_BASE_IDX 0 197c54a60dbSLeo Liu #define mmUVD_JPEG_ENC_PREEMPT_FENCE_DATA0 0x0131 198c54a60dbSLeo Liu #define mmUVD_JPEG_ENC_PREEMPT_FENCE_DATA0_BASE_IDX 0 199c54a60dbSLeo Liu #define mmUVD_JPEG_ENC_PREEMPT_FENCE_DATA1 0x0132 200c54a60dbSLeo Liu #define mmUVD_JPEG_ENC_PREEMPT_FENCE_DATA1_BASE_IDX 0 201c54a60dbSLeo Liu #define mmUVD_JRBC_ENC_RB_SIZE 0x0133 202c54a60dbSLeo Liu #define mmUVD_JRBC_ENC_RB_SIZE_BASE_IDX 0 203c54a60dbSLeo Liu #define mmUVD_JRBC_ENC_SCRATCH0 0x0134 204c54a60dbSLeo Liu #define mmUVD_JRBC_ENC_SCRATCH0_BASE_IDX 0 205c54a60dbSLeo Liu 206c54a60dbSLeo Liu 207c54a60dbSLeo Liu // addressBlock: uvd0_uvd_jmi_dec 208c54a60dbSLeo Liu // base address: 0x1e500 209c54a60dbSLeo Liu #define mmUVD_JMI_CTRL 0x0145 210c54a60dbSLeo Liu #define mmUVD_JMI_CTRL_BASE_IDX 0 211c54a60dbSLeo Liu #define mmUVD_LMI_JRBC_CTRL 0x0146 212c54a60dbSLeo Liu #define mmUVD_LMI_JRBC_CTRL_BASE_IDX 0 213c54a60dbSLeo Liu #define mmUVD_LMI_JPEG_CTRL 0x0147 214c54a60dbSLeo Liu #define mmUVD_LMI_JPEG_CTRL_BASE_IDX 0 215c54a60dbSLeo Liu #define mmUVD_JMI_EJRBC_CTRL 0x0148 216c54a60dbSLeo Liu #define mmUVD_JMI_EJRBC_CTRL_BASE_IDX 0 217c54a60dbSLeo Liu #define mmUVD_LMI_EJPEG_CTRL 0x0149 218c54a60dbSLeo Liu #define mmUVD_LMI_EJPEG_CTRL_BASE_IDX 0 219c54a60dbSLeo Liu #define mmUVD_LMI_JRBC_IB_VMID 0x014f 220c54a60dbSLeo Liu #define mmUVD_LMI_JRBC_IB_VMID_BASE_IDX 0 221c54a60dbSLeo Liu #define mmUVD_LMI_JRBC_RB_VMID 0x0150 222c54a60dbSLeo Liu #define mmUVD_LMI_JRBC_RB_VMID_BASE_IDX 0 223c54a60dbSLeo Liu #define mmUVD_LMI_JPEG_VMID 0x0151 224c54a60dbSLeo Liu #define mmUVD_LMI_JPEG_VMID_BASE_IDX 0 225c54a60dbSLeo Liu #define mmUVD_JMI_ENC_JRBC_IB_VMID 0x0152 226c54a60dbSLeo Liu #define mmUVD_JMI_ENC_JRBC_IB_VMID_BASE_IDX 0 227c54a60dbSLeo Liu #define mmUVD_JMI_ENC_JRBC_RB_VMID 0x0153 228c54a60dbSLeo Liu #define mmUVD_JMI_ENC_JRBC_RB_VMID_BASE_IDX 0 229c54a60dbSLeo Liu #define mmUVD_JMI_ENC_JPEG_VMID 0x0154 230c54a60dbSLeo Liu #define mmUVD_JMI_ENC_JPEG_VMID_BASE_IDX 0 231c54a60dbSLeo Liu #define mmUVD_JMI_PERFMON_CTRL 0x015c 232c54a60dbSLeo Liu #define mmUVD_JMI_PERFMON_CTRL_BASE_IDX 0 233c54a60dbSLeo Liu #define mmUVD_JMI_PERFMON_COUNT_LO 0x015d 234c54a60dbSLeo Liu #define mmUVD_JMI_PERFMON_COUNT_LO_BASE_IDX 0 235c54a60dbSLeo Liu #define mmUVD_JMI_PERFMON_COUNT_HI 0x015e 236c54a60dbSLeo Liu #define mmUVD_JMI_PERFMON_COUNT_HI_BASE_IDX 0 237c54a60dbSLeo Liu #define mmUVD_LMI_JPEG_READ_64BIT_BAR_LOW 0x0160 238c54a60dbSLeo Liu #define mmUVD_LMI_JPEG_READ_64BIT_BAR_LOW_BASE_IDX 0 239c54a60dbSLeo Liu #define mmUVD_LMI_JPEG_READ_64BIT_BAR_HIGH 0x0161 240c54a60dbSLeo Liu #define mmUVD_LMI_JPEG_READ_64BIT_BAR_HIGH_BASE_IDX 0 241c54a60dbSLeo Liu #define mmUVD_LMI_JPEG_WRITE_64BIT_BAR_LOW 0x0162 242c54a60dbSLeo Liu #define mmUVD_LMI_JPEG_WRITE_64BIT_BAR_LOW_BASE_IDX 0 243c54a60dbSLeo Liu #define mmUVD_LMI_JPEG_WRITE_64BIT_BAR_HIGH 0x0163 244c54a60dbSLeo Liu #define mmUVD_LMI_JPEG_WRITE_64BIT_BAR_HIGH_BASE_IDX 0 245c54a60dbSLeo Liu #define mmUVD_LMI_JPEG_PREEMPT_FENCE_64BIT_BAR_LOW 0x0164 246c54a60dbSLeo Liu #define mmUVD_LMI_JPEG_PREEMPT_FENCE_64BIT_BAR_LOW_BASE_IDX 0 247c54a60dbSLeo Liu #define mmUVD_LMI_JPEG_PREEMPT_FENCE_64BIT_BAR_HIGH 0x0165 248c54a60dbSLeo Liu #define mmUVD_LMI_JPEG_PREEMPT_FENCE_64BIT_BAR_HIGH_BASE_IDX 0 249c54a60dbSLeo Liu #define mmUVD_LMI_JRBC_RB_64BIT_BAR_LOW 0x0166 250c54a60dbSLeo Liu #define mmUVD_LMI_JRBC_RB_64BIT_BAR_LOW_BASE_IDX 0 251c54a60dbSLeo Liu #define mmUVD_LMI_JRBC_RB_64BIT_BAR_HIGH 0x0167 252c54a60dbSLeo Liu #define mmUVD_LMI_JRBC_RB_64BIT_BAR_HIGH_BASE_IDX 0 253c54a60dbSLeo Liu #define mmUVD_LMI_JRBC_IB_64BIT_BAR_LOW 0x0168 254c54a60dbSLeo Liu #define mmUVD_LMI_JRBC_IB_64BIT_BAR_LOW_BASE_IDX 0 255c54a60dbSLeo Liu #define mmUVD_LMI_JRBC_IB_64BIT_BAR_HIGH 0x0169 256c54a60dbSLeo Liu #define mmUVD_LMI_JRBC_IB_64BIT_BAR_HIGH_BASE_IDX 0 257c54a60dbSLeo Liu #define mmUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_LOW 0x016a 258c54a60dbSLeo Liu #define mmUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_LOW_BASE_IDX 0 259c54a60dbSLeo Liu #define mmUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_HIGH 0x016b 260c54a60dbSLeo Liu #define mmUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_HIGH_BASE_IDX 0 261c54a60dbSLeo Liu #define mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_LOW 0x016c 262c54a60dbSLeo Liu #define mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_LOW_BASE_IDX 0 263c54a60dbSLeo Liu #define mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_HIGH 0x016d 264c54a60dbSLeo Liu #define mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_HIGH_BASE_IDX 0 265c54a60dbSLeo Liu #define mmUVD_LMI_JRBC_IB_MEM_WR_64BIT_BAR_LOW 0x016e 266c54a60dbSLeo Liu #define mmUVD_LMI_JRBC_IB_MEM_WR_64BIT_BAR_LOW_BASE_IDX 0 267c54a60dbSLeo Liu #define mmUVD_LMI_JRBC_IB_MEM_WR_64BIT_BAR_HIGH 0x016f 268c54a60dbSLeo Liu #define mmUVD_LMI_JRBC_IB_MEM_WR_64BIT_BAR_HIGH_BASE_IDX 0 269c54a60dbSLeo Liu #define mmUVD_LMI_JRBC_IB_MEM_RD_64BIT_BAR_LOW 0x0170 270c54a60dbSLeo Liu #define mmUVD_LMI_JRBC_IB_MEM_RD_64BIT_BAR_LOW_BASE_IDX 0 271c54a60dbSLeo Liu #define mmUVD_LMI_JRBC_IB_MEM_RD_64BIT_BAR_HIGH 0x0171 272c54a60dbSLeo Liu #define mmUVD_LMI_JRBC_IB_MEM_RD_64BIT_BAR_HIGH_BASE_IDX 0 273c54a60dbSLeo Liu #define mmUVD_LMI_EJPEG_PREEMPT_FENCE_64BIT_BAR_LOW 0x017a 274c54a60dbSLeo Liu #define mmUVD_LMI_EJPEG_PREEMPT_FENCE_64BIT_BAR_LOW_BASE_IDX 0 275c54a60dbSLeo Liu #define mmUVD_LMI_EJPEG_PREEMPT_FENCE_64BIT_BAR_HIGH 0x017b 276c54a60dbSLeo Liu #define mmUVD_LMI_EJPEG_PREEMPT_FENCE_64BIT_BAR_HIGH_BASE_IDX 0 277c54a60dbSLeo Liu #define mmUVD_LMI_EJRBC_RB_64BIT_BAR_LOW 0x017c 278c54a60dbSLeo Liu #define mmUVD_LMI_EJRBC_RB_64BIT_BAR_LOW_BASE_IDX 0 279c54a60dbSLeo Liu #define mmUVD_LMI_EJRBC_RB_64BIT_BAR_HIGH 0x017d 280c54a60dbSLeo Liu #define mmUVD_LMI_EJRBC_RB_64BIT_BAR_HIGH_BASE_IDX 0 281c54a60dbSLeo Liu #define mmUVD_LMI_EJRBC_IB_64BIT_BAR_LOW 0x017e 282c54a60dbSLeo Liu #define mmUVD_LMI_EJRBC_IB_64BIT_BAR_LOW_BASE_IDX 0 283c54a60dbSLeo Liu #define mmUVD_LMI_EJRBC_IB_64BIT_BAR_HIGH 0x017f 284c54a60dbSLeo Liu #define mmUVD_LMI_EJRBC_IB_64BIT_BAR_HIGH_BASE_IDX 0 285c54a60dbSLeo Liu #define mmUVD_LMI_EJRBC_RB_MEM_WR_64BIT_BAR_LOW 0x0180 286c54a60dbSLeo Liu #define mmUVD_LMI_EJRBC_RB_MEM_WR_64BIT_BAR_LOW_BASE_IDX 0 287c54a60dbSLeo Liu #define mmUVD_LMI_EJRBC_RB_MEM_WR_64BIT_BAR_HIGH 0x0181 288c54a60dbSLeo Liu #define mmUVD_LMI_EJRBC_RB_MEM_WR_64BIT_BAR_HIGH_BASE_IDX 0 289c54a60dbSLeo Liu #define mmUVD_LMI_EJRBC_RB_MEM_RD_64BIT_BAR_LOW 0x0182 290c54a60dbSLeo Liu #define mmUVD_LMI_EJRBC_RB_MEM_RD_64BIT_BAR_LOW_BASE_IDX 0 291c54a60dbSLeo Liu #define mmUVD_LMI_EJRBC_RB_MEM_RD_64BIT_BAR_HIGH 0x0183 292c54a60dbSLeo Liu #define mmUVD_LMI_EJRBC_RB_MEM_RD_64BIT_BAR_HIGH_BASE_IDX 0 293c54a60dbSLeo Liu #define mmUVD_LMI_EJRBC_IB_MEM_WR_64BIT_BAR_LOW 0x0184 294c54a60dbSLeo Liu #define mmUVD_LMI_EJRBC_IB_MEM_WR_64BIT_BAR_LOW_BASE_IDX 0 295c54a60dbSLeo Liu #define mmUVD_LMI_EJRBC_IB_MEM_WR_64BIT_BAR_HIGH 0x0185 296c54a60dbSLeo Liu #define mmUVD_LMI_EJRBC_IB_MEM_WR_64BIT_BAR_HIGH_BASE_IDX 0 297c54a60dbSLeo Liu #define mmUVD_LMI_EJRBC_IB_MEM_RD_64BIT_BAR_LOW 0x0186 298c54a60dbSLeo Liu #define mmUVD_LMI_EJRBC_IB_MEM_RD_64BIT_BAR_LOW_BASE_IDX 0 299c54a60dbSLeo Liu #define mmUVD_LMI_EJRBC_IB_MEM_RD_64BIT_BAR_HIGH 0x0187 300c54a60dbSLeo Liu #define mmUVD_LMI_EJRBC_IB_MEM_RD_64BIT_BAR_HIGH_BASE_IDX 0 301c54a60dbSLeo Liu #define mmUVD_LMI_JPEG_PREEMPT_VMID 0x0188 302c54a60dbSLeo Liu #define mmUVD_LMI_JPEG_PREEMPT_VMID_BASE_IDX 0 303c54a60dbSLeo Liu #define mmUVD_LMI_ENC_JPEG_PREEMPT_VMID 0x0189 304c54a60dbSLeo Liu #define mmUVD_LMI_ENC_JPEG_PREEMPT_VMID_BASE_IDX 0 305c54a60dbSLeo Liu #define mmUVD_LMI_JPEG2_VMID 0x018a 306c54a60dbSLeo Liu #define mmUVD_LMI_JPEG2_VMID_BASE_IDX 0 307c54a60dbSLeo Liu #define mmUVD_LMI_JPEG2_READ_64BIT_BAR_LOW 0x018b 308c54a60dbSLeo Liu #define mmUVD_LMI_JPEG2_READ_64BIT_BAR_LOW_BASE_IDX 0 309c54a60dbSLeo Liu #define mmUVD_LMI_JPEG2_READ_64BIT_BAR_HIGH 0x018c 310c54a60dbSLeo Liu #define mmUVD_LMI_JPEG2_READ_64BIT_BAR_HIGH_BASE_IDX 0 311c54a60dbSLeo Liu #define mmUVD_LMI_JPEG2_WRITE_64BIT_BAR_LOW 0x018d 312c54a60dbSLeo Liu #define mmUVD_LMI_JPEG2_WRITE_64BIT_BAR_LOW_BASE_IDX 0 313c54a60dbSLeo Liu #define mmUVD_LMI_JPEG2_WRITE_64BIT_BAR_HIGH 0x018e 314c54a60dbSLeo Liu #define mmUVD_LMI_JPEG2_WRITE_64BIT_BAR_HIGH_BASE_IDX 0 315c54a60dbSLeo Liu #define mmUVD_LMI_JPEG_CTRL2 0x018f 316c54a60dbSLeo Liu #define mmUVD_LMI_JPEG_CTRL2_BASE_IDX 0 317c54a60dbSLeo Liu #define mmUVD_JMI_DEC_SWAP_CNTL 0x0190 318c54a60dbSLeo Liu #define mmUVD_JMI_DEC_SWAP_CNTL_BASE_IDX 0 319c54a60dbSLeo Liu #define mmUVD_JMI_ENC_SWAP_CNTL 0x0191 320c54a60dbSLeo Liu #define mmUVD_JMI_ENC_SWAP_CNTL_BASE_IDX 0 321c54a60dbSLeo Liu #define mmUVD_JMI_CNTL 0x0192 322c54a60dbSLeo Liu #define mmUVD_JMI_CNTL_BASE_IDX 0 323c54a60dbSLeo Liu #define mmUVD_JMI_HUFF_FENCE_64BIT_BAR_LOW 0x019a 324c54a60dbSLeo Liu #define mmUVD_JMI_HUFF_FENCE_64BIT_BAR_LOW_BASE_IDX 0 325c54a60dbSLeo Liu #define mmUVD_JMI_HUFF_FENCE_64BIT_BAR_HIGH 0x019b 326c54a60dbSLeo Liu #define mmUVD_JMI_HUFF_FENCE_64BIT_BAR_HIGH_BASE_IDX 0 327c54a60dbSLeo Liu #define mmUVD_JMI_DEC_SWAP_CNTL2 0x019c 328c54a60dbSLeo Liu #define mmUVD_JMI_DEC_SWAP_CNTL2_BASE_IDX 0 329c54a60dbSLeo Liu 330c54a60dbSLeo Liu 331c54a60dbSLeo Liu // addressBlock: uvd0_uvd_jpeg_common_dec 332c54a60dbSLeo Liu // base address: 0x1e700 333c54a60dbSLeo Liu #define mmJPEG_SOFT_RESET_STATUS 0x01c0 334c54a60dbSLeo Liu #define mmJPEG_SOFT_RESET_STATUS_BASE_IDX 0 335c54a60dbSLeo Liu #define mmJPEG_SYS_INT_EN 0x01c1 336c54a60dbSLeo Liu #define mmJPEG_SYS_INT_EN_BASE_IDX 0 337c54a60dbSLeo Liu #define mmJPEG_SYS_INT_STATUS 0x01c2 338c54a60dbSLeo Liu #define mmJPEG_SYS_INT_STATUS_BASE_IDX 0 339c54a60dbSLeo Liu #define mmJPEG_SYS_INT_ACK 0x01c3 340c54a60dbSLeo Liu #define mmJPEG_SYS_INT_ACK_BASE_IDX 0 341c54a60dbSLeo Liu #define mmJPEG_MASTINT_EN 0x01c8 342c54a60dbSLeo Liu #define mmJPEG_MASTINT_EN_BASE_IDX 0 343c54a60dbSLeo Liu #define mmJPEG_IH_CTRL 0x01c9 344c54a60dbSLeo Liu #define mmJPEG_IH_CTRL_BASE_IDX 0 345c54a60dbSLeo Liu #define mmJRBBM_ARB_CTRL 0x01cb 346c54a60dbSLeo Liu #define mmJRBBM_ARB_CTRL_BASE_IDX 0 347c54a60dbSLeo Liu 348c54a60dbSLeo Liu 349c54a60dbSLeo Liu // addressBlock: uvd0_uvd_jpeg_common_sclk_dec 350c54a60dbSLeo Liu // base address: 0x1e780 351c54a60dbSLeo Liu #define mmJPEG_CGC_GATE 0x01e0 352c54a60dbSLeo Liu #define mmJPEG_CGC_GATE_BASE_IDX 0 353c54a60dbSLeo Liu #define mmJPEG_CGC_CTRL 0x01e1 354c54a60dbSLeo Liu #define mmJPEG_CGC_CTRL_BASE_IDX 0 355c54a60dbSLeo Liu #define mmJPEG_CGC_STATUS 0x01e2 356c54a60dbSLeo Liu #define mmJPEG_CGC_STATUS_BASE_IDX 0 357c54a60dbSLeo Liu #define mmJPEG_COMN_CGC_MEM_CTRL 0x01e3 358c54a60dbSLeo Liu #define mmJPEG_COMN_CGC_MEM_CTRL_BASE_IDX 0 359c54a60dbSLeo Liu #define mmJPEG_DEC_CGC_MEM_CTRL 0x01e4 360c54a60dbSLeo Liu #define mmJPEG_DEC_CGC_MEM_CTRL_BASE_IDX 0 361c54a60dbSLeo Liu #define mmJPEG2_DEC_CGC_MEM_CTRL 0x01e5 362c54a60dbSLeo Liu #define mmJPEG2_DEC_CGC_MEM_CTRL_BASE_IDX 0 363c54a60dbSLeo Liu #define mmJPEG_ENC_CGC_MEM_CTRL 0x01e6 364c54a60dbSLeo Liu #define mmJPEG_ENC_CGC_MEM_CTRL_BASE_IDX 0 365c54a60dbSLeo Liu #define mmJPEG_SOFT_RESET2 0x01e7 366c54a60dbSLeo Liu #define mmJPEG_SOFT_RESET2_BASE_IDX 0 367c54a60dbSLeo Liu #define mmJPEG_PERF_BANK_CONF 0x01e8 368c54a60dbSLeo Liu #define mmJPEG_PERF_BANK_CONF_BASE_IDX 0 369c54a60dbSLeo Liu #define mmJPEG_PERF_BANK_EVENT_SEL 0x01e9 370c54a60dbSLeo Liu #define mmJPEG_PERF_BANK_EVENT_SEL_BASE_IDX 0 371c54a60dbSLeo Liu #define mmJPEG_PERF_BANK_COUNT0 0x01ea 372c54a60dbSLeo Liu #define mmJPEG_PERF_BANK_COUNT0_BASE_IDX 0 373c54a60dbSLeo Liu #define mmJPEG_PERF_BANK_COUNT1 0x01eb 374c54a60dbSLeo Liu #define mmJPEG_PERF_BANK_COUNT1_BASE_IDX 0 375c54a60dbSLeo Liu #define mmJPEG_PERF_BANK_COUNT2 0x01ec 376c54a60dbSLeo Liu #define mmJPEG_PERF_BANK_COUNT2_BASE_IDX 0 377c54a60dbSLeo Liu #define mmJPEG_PERF_BANK_COUNT3 0x01ed 378c54a60dbSLeo Liu #define mmJPEG_PERF_BANK_COUNT3_BASE_IDX 0 379c54a60dbSLeo Liu 380c54a60dbSLeo Liu 381c54a60dbSLeo Liu // addressBlock: uvd0_uvd_pg_dec 382c54a60dbSLeo Liu // base address: 0x1f800 383c54a60dbSLeo Liu #define mmUVD_PGFSM_CONFIG 0x0000 384c54a60dbSLeo Liu #define mmUVD_PGFSM_CONFIG_BASE_IDX 1 385c54a60dbSLeo Liu #define mmUVD_PGFSM_STATUS 0x0001 386c54a60dbSLeo Liu #define mmUVD_PGFSM_STATUS_BASE_IDX 1 387c54a60dbSLeo Liu #define mmUVD_POWER_STATUS 0x0004 388c54a60dbSLeo Liu #define mmUVD_POWER_STATUS_BASE_IDX 1 389c54a60dbSLeo Liu #define mmUVD_PG_IND_INDEX 0x0005 390c54a60dbSLeo Liu #define mmUVD_PG_IND_INDEX_BASE_IDX 1 391c54a60dbSLeo Liu #define mmUVD_PG_IND_DATA 0x0006 392c54a60dbSLeo Liu #define mmUVD_PG_IND_DATA_BASE_IDX 1 393c54a60dbSLeo Liu #define mmCC_UVD_HARVESTING 0x0007 394c54a60dbSLeo Liu #define mmCC_UVD_HARVESTING_BASE_IDX 1 395c54a60dbSLeo Liu #define mmUVD_JPEG_POWER_STATUS 0x000a 396c54a60dbSLeo Liu #define mmUVD_JPEG_POWER_STATUS_BASE_IDX 1 397c54a60dbSLeo Liu #define mmUVD_DPG_LMA_CTL 0x0011 398c54a60dbSLeo Liu #define mmUVD_DPG_LMA_CTL_BASE_IDX 1 399c54a60dbSLeo Liu #define mmUVD_DPG_LMA_DATA 0x0012 400c54a60dbSLeo Liu #define mmUVD_DPG_LMA_DATA_BASE_IDX 1 401c54a60dbSLeo Liu #define mmUVD_DPG_LMA_MASK 0x0013 402c54a60dbSLeo Liu #define mmUVD_DPG_LMA_MASK_BASE_IDX 1 403c54a60dbSLeo Liu #define mmUVD_DPG_PAUSE 0x0014 404c54a60dbSLeo Liu #define mmUVD_DPG_PAUSE_BASE_IDX 1 405c54a60dbSLeo Liu #define mmUVD_SCRATCH1 0x0015 406c54a60dbSLeo Liu #define mmUVD_SCRATCH1_BASE_IDX 1 407c54a60dbSLeo Liu #define mmUVD_SCRATCH2 0x0016 408c54a60dbSLeo Liu #define mmUVD_SCRATCH2_BASE_IDX 1 409c54a60dbSLeo Liu #define mmUVD_SCRATCH3 0x0017 410c54a60dbSLeo Liu #define mmUVD_SCRATCH3_BASE_IDX 1 411c54a60dbSLeo Liu #define mmUVD_SCRATCH4 0x0018 412c54a60dbSLeo Liu #define mmUVD_SCRATCH4_BASE_IDX 1 413c54a60dbSLeo Liu #define mmUVD_SCRATCH5 0x0019 414c54a60dbSLeo Liu #define mmUVD_SCRATCH5_BASE_IDX 1 415c54a60dbSLeo Liu #define mmUVD_SCRATCH6 0x001a 416c54a60dbSLeo Liu #define mmUVD_SCRATCH6_BASE_IDX 1 417c54a60dbSLeo Liu #define mmUVD_SCRATCH7 0x001b 418c54a60dbSLeo Liu #define mmUVD_SCRATCH7_BASE_IDX 1 419c54a60dbSLeo Liu #define mmUVD_SCRATCH8 0x001c 420c54a60dbSLeo Liu #define mmUVD_SCRATCH8_BASE_IDX 1 421c54a60dbSLeo Liu #define mmUVD_SCRATCH9 0x001d 422c54a60dbSLeo Liu #define mmUVD_SCRATCH9_BASE_IDX 1 423c54a60dbSLeo Liu #define mmUVD_SCRATCH10 0x001e 424c54a60dbSLeo Liu #define mmUVD_SCRATCH10_BASE_IDX 1 425c54a60dbSLeo Liu #define mmUVD_SCRATCH11 0x001f 426c54a60dbSLeo Liu #define mmUVD_SCRATCH11_BASE_IDX 1 427c54a60dbSLeo Liu #define mmUVD_SCRATCH12 0x0020 428c54a60dbSLeo Liu #define mmUVD_SCRATCH12_BASE_IDX 1 429c54a60dbSLeo Liu #define mmUVD_SCRATCH13 0x0021 430c54a60dbSLeo Liu #define mmUVD_SCRATCH13_BASE_IDX 1 431c54a60dbSLeo Liu #define mmUVD_SCRATCH14 0x0022 432c54a60dbSLeo Liu #define mmUVD_SCRATCH14_BASE_IDX 1 433c54a60dbSLeo Liu #define mmUVD_FREE_COUNTER_REG 0x0024 434c54a60dbSLeo Liu #define mmUVD_FREE_COUNTER_REG_BASE_IDX 1 435c54a60dbSLeo Liu #define mmUVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_LOW 0x0025 436c54a60dbSLeo Liu #define mmUVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_LOW_BASE_IDX 1 437c54a60dbSLeo Liu #define mmUVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_HIGH 0x0026 438c54a60dbSLeo Liu #define mmUVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_HIGH_BASE_IDX 1 439c54a60dbSLeo Liu #define mmUVD_DPG_VCPU_CACHE_OFFSET0 0x0027 440c54a60dbSLeo Liu #define mmUVD_DPG_VCPU_CACHE_OFFSET0_BASE_IDX 1 441c54a60dbSLeo Liu #define mmUVD_DPG_LMI_VCPU_CACHE_VMID 0x0028 442c54a60dbSLeo Liu #define mmUVD_DPG_LMI_VCPU_CACHE_VMID_BASE_IDX 1 443c54a60dbSLeo Liu #define mmUVD_PF_STATUS 0x0039 444c54a60dbSLeo Liu #define mmUVD_PF_STATUS_BASE_IDX 1 445c54a60dbSLeo Liu #define mmUVD_DPG_CLK_EN_VCPU_REPORT 0x003c 446c54a60dbSLeo Liu #define mmUVD_DPG_CLK_EN_VCPU_REPORT_BASE_IDX 1 447c54a60dbSLeo Liu #define mmUVD_GFX8_ADDR_CONFIG 0x0049 448c54a60dbSLeo Liu #define mmUVD_GFX8_ADDR_CONFIG_BASE_IDX 1 449c54a60dbSLeo Liu #define mmUVD_GFX10_ADDR_CONFIG 0x004a 450c54a60dbSLeo Liu #define mmUVD_GFX10_ADDR_CONFIG_BASE_IDX 1 451c54a60dbSLeo Liu #define mmUVD_GPCNT2_CNTL 0x004b 452c54a60dbSLeo Liu #define mmUVD_GPCNT2_CNTL_BASE_IDX 1 453c54a60dbSLeo Liu #define mmUVD_GPCNT2_TARGET_LOWER 0x004c 454c54a60dbSLeo Liu #define mmUVD_GPCNT2_TARGET_LOWER_BASE_IDX 1 455c54a60dbSLeo Liu #define mmUVD_GPCNT2_STATUS_LOWER 0x004d 456c54a60dbSLeo Liu #define mmUVD_GPCNT2_STATUS_LOWER_BASE_IDX 1 457c54a60dbSLeo Liu #define mmUVD_GPCNT2_TARGET_UPPER 0x004e 458c54a60dbSLeo Liu #define mmUVD_GPCNT2_TARGET_UPPER_BASE_IDX 1 459c54a60dbSLeo Liu #define mmUVD_GPCNT2_STATUS_UPPER 0x004f 460c54a60dbSLeo Liu #define mmUVD_GPCNT2_STATUS_UPPER_BASE_IDX 1 461c54a60dbSLeo Liu #define mmUVD_GPCNT3_CNTL 0x0050 462c54a60dbSLeo Liu #define mmUVD_GPCNT3_CNTL_BASE_IDX 1 463c54a60dbSLeo Liu #define mmUVD_GPCNT3_TARGET_LOWER 0x0051 464c54a60dbSLeo Liu #define mmUVD_GPCNT3_TARGET_LOWER_BASE_IDX 1 465c54a60dbSLeo Liu #define mmUVD_GPCNT3_STATUS_LOWER 0x0052 466c54a60dbSLeo Liu #define mmUVD_GPCNT3_STATUS_LOWER_BASE_IDX 1 467c54a60dbSLeo Liu #define mmUVD_GPCNT3_TARGET_UPPER 0x0053 468c54a60dbSLeo Liu #define mmUVD_GPCNT3_TARGET_UPPER_BASE_IDX 1 469c54a60dbSLeo Liu #define mmUVD_GPCNT3_STATUS_UPPER 0x0054 470c54a60dbSLeo Liu #define mmUVD_GPCNT3_STATUS_UPPER_BASE_IDX 1 471c54a60dbSLeo Liu 472c54a60dbSLeo Liu 473c54a60dbSLeo Liu // addressBlock: uvd0_uvddec 474c54a60dbSLeo Liu // base address: 0x1fa00 475c54a60dbSLeo Liu #define mmUVD_STATUS 0x0080 476c54a60dbSLeo Liu #define mmUVD_STATUS_BASE_IDX 1 477c54a60dbSLeo Liu #define mmUVD_ENC_PIPE_BUSY 0x0081 478c54a60dbSLeo Liu #define mmUVD_ENC_PIPE_BUSY_BASE_IDX 1 479c54a60dbSLeo Liu #define mmUVD_SOFT_RESET 0x0084 480c54a60dbSLeo Liu #define mmUVD_SOFT_RESET_BASE_IDX 1 481c54a60dbSLeo Liu #define mmUVD_SOFT_RESET2 0x0085 482c54a60dbSLeo Liu #define mmUVD_SOFT_RESET2_BASE_IDX 1 483c54a60dbSLeo Liu #define mmUVD_MMSCH_SOFT_RESET 0x0086 484c54a60dbSLeo Liu #define mmUVD_MMSCH_SOFT_RESET_BASE_IDX 1 485c54a60dbSLeo Liu #define mmUVD_CGC_GATE 0x0088 486c54a60dbSLeo Liu #define mmUVD_CGC_GATE_BASE_IDX 1 487c54a60dbSLeo Liu #define mmUVD_CGC_STATUS 0x0089 488c54a60dbSLeo Liu #define mmUVD_CGC_STATUS_BASE_IDX 1 489c54a60dbSLeo Liu #define mmUVD_CGC_CTRL 0x008a 490c54a60dbSLeo Liu #define mmUVD_CGC_CTRL_BASE_IDX 1 491c54a60dbSLeo Liu #define mmUVD_CGC_UDEC_STATUS 0x008b 492c54a60dbSLeo Liu #define mmUVD_CGC_UDEC_STATUS_BASE_IDX 1 493c54a60dbSLeo Liu #define mmUVD_SUVD_CGC_GATE 0x008c 494c54a60dbSLeo Liu #define mmUVD_SUVD_CGC_GATE_BASE_IDX 1 495c54a60dbSLeo Liu #define mmUVD_SUVD_CGC_STATUS 0x008d 496c54a60dbSLeo Liu #define mmUVD_SUVD_CGC_STATUS_BASE_IDX 1 497c54a60dbSLeo Liu #define mmUVD_SUVD_CGC_CTRL 0x008e 498c54a60dbSLeo Liu #define mmUVD_SUVD_CGC_CTRL_BASE_IDX 1 499c54a60dbSLeo Liu #define mmUVD_GPCOM_VCPU_CMD 0x008f 500c54a60dbSLeo Liu #define mmUVD_GPCOM_VCPU_CMD_BASE_IDX 1 501c54a60dbSLeo Liu #define mmUVD_GPCOM_VCPU_DATA0 0x0090 502c54a60dbSLeo Liu #define mmUVD_GPCOM_VCPU_DATA0_BASE_IDX 1 503c54a60dbSLeo Liu #define mmUVD_GPCOM_VCPU_DATA1 0x0091 504c54a60dbSLeo Liu #define mmUVD_GPCOM_VCPU_DATA1_BASE_IDX 1 505c54a60dbSLeo Liu #define mmUVD_GPCOM_SYS_CMD 0x0092 506c54a60dbSLeo Liu #define mmUVD_GPCOM_SYS_CMD_BASE_IDX 1 507c54a60dbSLeo Liu #define mmUVD_GPCOM_SYS_DATA0 0x0093 508c54a60dbSLeo Liu #define mmUVD_GPCOM_SYS_DATA0_BASE_IDX 1 509c54a60dbSLeo Liu #define mmUVD_GPCOM_SYS_DATA1 0x0094 510c54a60dbSLeo Liu #define mmUVD_GPCOM_SYS_DATA1_BASE_IDX 1 511c54a60dbSLeo Liu #define mmUVD_VCPU_INT_EN 0x0095 512c54a60dbSLeo Liu #define mmUVD_VCPU_INT_EN_BASE_IDX 1 513c54a60dbSLeo Liu #define mmUVD_VCPU_INT_ACK 0x0097 514c54a60dbSLeo Liu #define mmUVD_VCPU_INT_ACK_BASE_IDX 1 515c54a60dbSLeo Liu #define mmUVD_VCPU_INT_ROUTE 0x0098 516c54a60dbSLeo Liu #define mmUVD_VCPU_INT_ROUTE_BASE_IDX 1 517c54a60dbSLeo Liu #define mmUVD_ENC_VCPU_INT_EN 0x009e 518c54a60dbSLeo Liu #define mmUVD_ENC_VCPU_INT_EN_BASE_IDX 1 519c54a60dbSLeo Liu #define mmUVD_ENC_VCPU_INT_ACK 0x00a0 520c54a60dbSLeo Liu #define mmUVD_ENC_VCPU_INT_ACK_BASE_IDX 1 521c54a60dbSLeo Liu #define mmUVD_MASTINT_EN 0x00a1 522c54a60dbSLeo Liu #define mmUVD_MASTINT_EN_BASE_IDX 1 523c54a60dbSLeo Liu #define mmUVD_SYS_INT_EN 0x00a2 524c54a60dbSLeo Liu #define mmUVD_SYS_INT_EN_BASE_IDX 1 525c54a60dbSLeo Liu #define mmUVD_SYS_INT_STATUS 0x00a3 526c54a60dbSLeo Liu #define mmUVD_SYS_INT_STATUS_BASE_IDX 1 527c54a60dbSLeo Liu #define mmUVD_SYS_INT_ACK 0x00a4 528c54a60dbSLeo Liu #define mmUVD_SYS_INT_ACK_BASE_IDX 1 529c54a60dbSLeo Liu #define mmUVD_JOB_DONE 0x00a5 530c54a60dbSLeo Liu #define mmUVD_JOB_DONE_BASE_IDX 1 531c54a60dbSLeo Liu #define mmUVD_CBUF_ID 0x00a6 532c54a60dbSLeo Liu #define mmUVD_CBUF_ID_BASE_IDX 1 533c54a60dbSLeo Liu #define mmUVD_CONTEXT_ID 0x00a7 534c54a60dbSLeo Liu #define mmUVD_CONTEXT_ID_BASE_IDX 1 535c54a60dbSLeo Liu #define mmUVD_CONTEXT_ID2 0x00a8 536c54a60dbSLeo Liu #define mmUVD_CONTEXT_ID2_BASE_IDX 1 537c54a60dbSLeo Liu #define mmUVD_NO_OP 0x00a9 538c54a60dbSLeo Liu #define mmUVD_NO_OP_BASE_IDX 1 539c54a60dbSLeo Liu #define mmUVD_RB_BASE_LO 0x00aa 540c54a60dbSLeo Liu #define mmUVD_RB_BASE_LO_BASE_IDX 1 541c54a60dbSLeo Liu #define mmUVD_RB_BASE_HI 0x00ab 542c54a60dbSLeo Liu #define mmUVD_RB_BASE_HI_BASE_IDX 1 543c54a60dbSLeo Liu #define mmUVD_RB_SIZE 0x00ac 544c54a60dbSLeo Liu #define mmUVD_RB_SIZE_BASE_IDX 1 545c54a60dbSLeo Liu #define mmUVD_RB_RPTR 0x00ad 546c54a60dbSLeo Liu #define mmUVD_RB_RPTR_BASE_IDX 1 547c54a60dbSLeo Liu #define mmUVD_RB_WPTR 0x00ae 548c54a60dbSLeo Liu #define mmUVD_RB_WPTR_BASE_IDX 1 549c54a60dbSLeo Liu #define mmUVD_RB_BASE_LO2 0x00af 550c54a60dbSLeo Liu #define mmUVD_RB_BASE_LO2_BASE_IDX 1 551c54a60dbSLeo Liu #define mmUVD_RB_BASE_HI2 0x00b0 552c54a60dbSLeo Liu #define mmUVD_RB_BASE_HI2_BASE_IDX 1 553c54a60dbSLeo Liu #define mmUVD_RB_SIZE2 0x00b1 554c54a60dbSLeo Liu #define mmUVD_RB_SIZE2_BASE_IDX 1 555c54a60dbSLeo Liu #define mmUVD_RB_RPTR2 0x00b2 556c54a60dbSLeo Liu #define mmUVD_RB_RPTR2_BASE_IDX 1 557c54a60dbSLeo Liu #define mmUVD_RB_WPTR2 0x00b3 558c54a60dbSLeo Liu #define mmUVD_RB_WPTR2_BASE_IDX 1 559c54a60dbSLeo Liu #define mmUVD_RB_BASE_LO3 0x00b4 560c54a60dbSLeo Liu #define mmUVD_RB_BASE_LO3_BASE_IDX 1 561c54a60dbSLeo Liu #define mmUVD_RB_BASE_HI3 0x00b5 562c54a60dbSLeo Liu #define mmUVD_RB_BASE_HI3_BASE_IDX 1 563c54a60dbSLeo Liu #define mmUVD_RB_SIZE3 0x00b6 564c54a60dbSLeo Liu #define mmUVD_RB_SIZE3_BASE_IDX 1 565c54a60dbSLeo Liu #define mmUVD_RB_RPTR3 0x00b7 566c54a60dbSLeo Liu #define mmUVD_RB_RPTR3_BASE_IDX 1 567c54a60dbSLeo Liu #define mmUVD_RB_WPTR3 0x00b8 568c54a60dbSLeo Liu #define mmUVD_RB_WPTR3_BASE_IDX 1 569c54a60dbSLeo Liu #define mmUVD_RB_BASE_LO4 0x00b9 570c54a60dbSLeo Liu #define mmUVD_RB_BASE_LO4_BASE_IDX 1 571c54a60dbSLeo Liu #define mmUVD_RB_BASE_HI4 0x00ba 572c54a60dbSLeo Liu #define mmUVD_RB_BASE_HI4_BASE_IDX 1 573c54a60dbSLeo Liu #define mmUVD_RB_SIZE4 0x00bb 574c54a60dbSLeo Liu #define mmUVD_RB_SIZE4_BASE_IDX 1 575c54a60dbSLeo Liu #define mmUVD_RB_RPTR4 0x00bc 576c54a60dbSLeo Liu #define mmUVD_RB_RPTR4_BASE_IDX 1 577c54a60dbSLeo Liu #define mmUVD_RB_WPTR4 0x00bd 578c54a60dbSLeo Liu #define mmUVD_RB_WPTR4_BASE_IDX 1 579c54a60dbSLeo Liu #define mmUVD_OUT_RB_BASE_LO 0x00be 580c54a60dbSLeo Liu #define mmUVD_OUT_RB_BASE_LO_BASE_IDX 1 581c54a60dbSLeo Liu #define mmUVD_OUT_RB_BASE_HI 0x00bf 582c54a60dbSLeo Liu #define mmUVD_OUT_RB_BASE_HI_BASE_IDX 1 583c54a60dbSLeo Liu #define mmUVD_OUT_RB_SIZE 0x00c0 584c54a60dbSLeo Liu #define mmUVD_OUT_RB_SIZE_BASE_IDX 1 585c54a60dbSLeo Liu #define mmUVD_OUT_RB_RPTR 0x00c1 586c54a60dbSLeo Liu #define mmUVD_OUT_RB_RPTR_BASE_IDX 1 587c54a60dbSLeo Liu #define mmUVD_OUT_RB_WPTR 0x00c2 588c54a60dbSLeo Liu #define mmUVD_OUT_RB_WPTR_BASE_IDX 1 589c54a60dbSLeo Liu #define mmUVD_RB_ARB_CTRL 0x00c6 590c54a60dbSLeo Liu #define mmUVD_RB_ARB_CTRL_BASE_IDX 1 591c54a60dbSLeo Liu #define mmUVD_CTX_INDEX 0x00c7 592c54a60dbSLeo Liu #define mmUVD_CTX_INDEX_BASE_IDX 1 593c54a60dbSLeo Liu #define mmUVD_CTX_DATA 0x00c8 594c54a60dbSLeo Liu #define mmUVD_CTX_DATA_BASE_IDX 1 595c54a60dbSLeo Liu #define mmUVD_CXW_WR 0x00c9 596c54a60dbSLeo Liu #define mmUVD_CXW_WR_BASE_IDX 1 597c54a60dbSLeo Liu #define mmUVD_CXW_WR_INT_ID 0x00ca 598c54a60dbSLeo Liu #define mmUVD_CXW_WR_INT_ID_BASE_IDX 1 599c54a60dbSLeo Liu #define mmUVD_CXW_WR_INT_CTX_ID 0x00cb 600c54a60dbSLeo Liu #define mmUVD_CXW_WR_INT_CTX_ID_BASE_IDX 1 601c54a60dbSLeo Liu #define mmUVD_CXW_INT_ID 0x00cc 602c54a60dbSLeo Liu #define mmUVD_CXW_INT_ID_BASE_IDX 1 603c54a60dbSLeo Liu #define mmUVD_TOP_CTRL 0x00cf 604c54a60dbSLeo Liu #define mmUVD_TOP_CTRL_BASE_IDX 1 605c54a60dbSLeo Liu #define mmUVD_YBASE 0x00d0 606c54a60dbSLeo Liu #define mmUVD_YBASE_BASE_IDX 1 607c54a60dbSLeo Liu #define mmUVD_UVBASE 0x00d1 608c54a60dbSLeo Liu #define mmUVD_UVBASE_BASE_IDX 1 609c54a60dbSLeo Liu #define mmUVD_PITCH 0x00d2 610c54a60dbSLeo Liu #define mmUVD_PITCH_BASE_IDX 1 611c54a60dbSLeo Liu #define mmUVD_WIDTH 0x00d3 612c54a60dbSLeo Liu #define mmUVD_WIDTH_BASE_IDX 1 613c54a60dbSLeo Liu #define mmUVD_HEIGHT 0x00d4 614c54a60dbSLeo Liu #define mmUVD_HEIGHT_BASE_IDX 1 615c54a60dbSLeo Liu #define mmUVD_PICCOUNT 0x00d5 616c54a60dbSLeo Liu #define mmUVD_PICCOUNT_BASE_IDX 1 617c54a60dbSLeo Liu #define mmUVD_SCRATCH_NP 0x00db 618c54a60dbSLeo Liu #define mmUVD_SCRATCH_NP_BASE_IDX 1 619c54a60dbSLeo Liu #define mmUVD_VERSION 0x00dd 620c54a60dbSLeo Liu #define mmUVD_VERSION_BASE_IDX 1 621c54a60dbSLeo Liu #define mmUVD_GP_SCRATCH0 0x00de 622c54a60dbSLeo Liu #define mmUVD_GP_SCRATCH0_BASE_IDX 1 623c54a60dbSLeo Liu #define mmUVD_GP_SCRATCH1 0x00df 624c54a60dbSLeo Liu #define mmUVD_GP_SCRATCH1_BASE_IDX 1 625c54a60dbSLeo Liu #define mmUVD_GP_SCRATCH2 0x00e0 626c54a60dbSLeo Liu #define mmUVD_GP_SCRATCH2_BASE_IDX 1 627c54a60dbSLeo Liu #define mmUVD_GP_SCRATCH3 0x00e1 628c54a60dbSLeo Liu #define mmUVD_GP_SCRATCH3_BASE_IDX 1 629c54a60dbSLeo Liu #define mmUVD_GP_SCRATCH4 0x00e2 630c54a60dbSLeo Liu #define mmUVD_GP_SCRATCH4_BASE_IDX 1 631c54a60dbSLeo Liu #define mmUVD_GP_SCRATCH5 0x00e3 632c54a60dbSLeo Liu #define mmUVD_GP_SCRATCH5_BASE_IDX 1 633c54a60dbSLeo Liu #define mmUVD_GP_SCRATCH6 0x00e4 634c54a60dbSLeo Liu #define mmUVD_GP_SCRATCH6_BASE_IDX 1 635c54a60dbSLeo Liu #define mmUVD_GP_SCRATCH7 0x00e5 636c54a60dbSLeo Liu #define mmUVD_GP_SCRATCH7_BASE_IDX 1 637c54a60dbSLeo Liu #define mmUVD_GP_SCRATCH8 0x00e6 638c54a60dbSLeo Liu #define mmUVD_GP_SCRATCH8_BASE_IDX 1 639c54a60dbSLeo Liu #define mmUVD_GP_SCRATCH9 0x00e7 640c54a60dbSLeo Liu #define mmUVD_GP_SCRATCH9_BASE_IDX 1 641c54a60dbSLeo Liu #define mmUVD_GP_SCRATCH10 0x00e8 642c54a60dbSLeo Liu #define mmUVD_GP_SCRATCH10_BASE_IDX 1 643c54a60dbSLeo Liu #define mmUVD_GP_SCRATCH11 0x00e9 644c54a60dbSLeo Liu #define mmUVD_GP_SCRATCH11_BASE_IDX 1 645c54a60dbSLeo Liu #define mmUVD_GP_SCRATCH12 0x00ea 646c54a60dbSLeo Liu #define mmUVD_GP_SCRATCH12_BASE_IDX 1 647c54a60dbSLeo Liu #define mmUVD_GP_SCRATCH13 0x00eb 648c54a60dbSLeo Liu #define mmUVD_GP_SCRATCH13_BASE_IDX 1 649c54a60dbSLeo Liu #define mmUVD_GP_SCRATCH14 0x00ec 650c54a60dbSLeo Liu #define mmUVD_GP_SCRATCH14_BASE_IDX 1 651c54a60dbSLeo Liu #define mmUVD_GP_SCRATCH15 0x00ed 652c54a60dbSLeo Liu #define mmUVD_GP_SCRATCH15_BASE_IDX 1 653c54a60dbSLeo Liu #define mmUVD_GP_SCRATCH16 0x00ee 654c54a60dbSLeo Liu #define mmUVD_GP_SCRATCH16_BASE_IDX 1 655c54a60dbSLeo Liu #define mmUVD_GP_SCRATCH17 0x00ef 656c54a60dbSLeo Liu #define mmUVD_GP_SCRATCH17_BASE_IDX 1 657c54a60dbSLeo Liu #define mmUVD_GP_SCRATCH18 0x00f0 658c54a60dbSLeo Liu #define mmUVD_GP_SCRATCH18_BASE_IDX 1 659c54a60dbSLeo Liu #define mmUVD_GP_SCRATCH19 0x00f1 660c54a60dbSLeo Liu #define mmUVD_GP_SCRATCH19_BASE_IDX 1 661c54a60dbSLeo Liu #define mmUVD_GP_SCRATCH20 0x00f2 662c54a60dbSLeo Liu #define mmUVD_GP_SCRATCH20_BASE_IDX 1 663c54a60dbSLeo Liu #define mmUVD_GP_SCRATCH21 0x00f3 664c54a60dbSLeo Liu #define mmUVD_GP_SCRATCH21_BASE_IDX 1 665c54a60dbSLeo Liu #define mmUVD_GP_SCRATCH22 0x00f4 666c54a60dbSLeo Liu #define mmUVD_GP_SCRATCH22_BASE_IDX 1 667c54a60dbSLeo Liu #define mmUVD_GP_SCRATCH23 0x00f5 668c54a60dbSLeo Liu #define mmUVD_GP_SCRATCH23_BASE_IDX 1 669c54a60dbSLeo Liu 670c54a60dbSLeo Liu 671c54a60dbSLeo Liu // addressBlock: uvd0_ecpudec 672c54a60dbSLeo Liu // base address: 0x1fd00 673c54a60dbSLeo Liu #define mmUVD_VCPU_CACHE_OFFSET0 0x0140 674c54a60dbSLeo Liu #define mmUVD_VCPU_CACHE_OFFSET0_BASE_IDX 1 675c54a60dbSLeo Liu #define mmUVD_VCPU_CACHE_SIZE0 0x0141 676c54a60dbSLeo Liu #define mmUVD_VCPU_CACHE_SIZE0_BASE_IDX 1 677c54a60dbSLeo Liu #define mmUVD_VCPU_CACHE_OFFSET1 0x0142 678c54a60dbSLeo Liu #define mmUVD_VCPU_CACHE_OFFSET1_BASE_IDX 1 679c54a60dbSLeo Liu #define mmUVD_VCPU_CACHE_SIZE1 0x0143 680c54a60dbSLeo Liu #define mmUVD_VCPU_CACHE_SIZE1_BASE_IDX 1 681c54a60dbSLeo Liu #define mmUVD_VCPU_CACHE_OFFSET2 0x0144 682c54a60dbSLeo Liu #define mmUVD_VCPU_CACHE_OFFSET2_BASE_IDX 1 683c54a60dbSLeo Liu #define mmUVD_VCPU_CACHE_SIZE2 0x0145 684c54a60dbSLeo Liu #define mmUVD_VCPU_CACHE_SIZE2_BASE_IDX 1 685c54a60dbSLeo Liu #define mmUVD_VCPU_CACHE_OFFSET3 0x0146 686c54a60dbSLeo Liu #define mmUVD_VCPU_CACHE_OFFSET3_BASE_IDX 1 687c54a60dbSLeo Liu #define mmUVD_VCPU_CACHE_SIZE3 0x0147 688c54a60dbSLeo Liu #define mmUVD_VCPU_CACHE_SIZE3_BASE_IDX 1 689c54a60dbSLeo Liu #define mmUVD_VCPU_CACHE_OFFSET4 0x0148 690c54a60dbSLeo Liu #define mmUVD_VCPU_CACHE_OFFSET4_BASE_IDX 1 691c54a60dbSLeo Liu #define mmUVD_VCPU_CACHE_SIZE4 0x0149 692c54a60dbSLeo Liu #define mmUVD_VCPU_CACHE_SIZE4_BASE_IDX 1 693c54a60dbSLeo Liu #define mmUVD_VCPU_CACHE_OFFSET5 0x014a 694c54a60dbSLeo Liu #define mmUVD_VCPU_CACHE_OFFSET5_BASE_IDX 1 695c54a60dbSLeo Liu #define mmUVD_VCPU_CACHE_SIZE5 0x014b 696c54a60dbSLeo Liu #define mmUVD_VCPU_CACHE_SIZE5_BASE_IDX 1 697c54a60dbSLeo Liu #define mmUVD_VCPU_CACHE_OFFSET6 0x014c 698c54a60dbSLeo Liu #define mmUVD_VCPU_CACHE_OFFSET6_BASE_IDX 1 699c54a60dbSLeo Liu #define mmUVD_VCPU_CACHE_SIZE6 0x014d 700c54a60dbSLeo Liu #define mmUVD_VCPU_CACHE_SIZE6_BASE_IDX 1 701c54a60dbSLeo Liu #define mmUVD_VCPU_CACHE_OFFSET7 0x014e 702c54a60dbSLeo Liu #define mmUVD_VCPU_CACHE_OFFSET7_BASE_IDX 1 703c54a60dbSLeo Liu #define mmUVD_VCPU_CACHE_SIZE7 0x014f 704c54a60dbSLeo Liu #define mmUVD_VCPU_CACHE_SIZE7_BASE_IDX 1 705c54a60dbSLeo Liu #define mmUVD_VCPU_CACHE_OFFSET8 0x0150 706c54a60dbSLeo Liu #define mmUVD_VCPU_CACHE_OFFSET8_BASE_IDX 1 707c54a60dbSLeo Liu #define mmUVD_VCPU_CACHE_SIZE8 0x0151 708c54a60dbSLeo Liu #define mmUVD_VCPU_CACHE_SIZE8_BASE_IDX 1 709c54a60dbSLeo Liu #define mmUVD_VCPU_NONCACHE_OFFSET0 0x0152 710c54a60dbSLeo Liu #define mmUVD_VCPU_NONCACHE_OFFSET0_BASE_IDX 1 711c54a60dbSLeo Liu #define mmUVD_VCPU_NONCACHE_SIZE0 0x0153 712c54a60dbSLeo Liu #define mmUVD_VCPU_NONCACHE_SIZE0_BASE_IDX 1 713c54a60dbSLeo Liu #define mmUVD_VCPU_NONCACHE_OFFSET1 0x0154 714c54a60dbSLeo Liu #define mmUVD_VCPU_NONCACHE_OFFSET1_BASE_IDX 1 715c54a60dbSLeo Liu #define mmUVD_VCPU_NONCACHE_SIZE1 0x0155 716c54a60dbSLeo Liu #define mmUVD_VCPU_NONCACHE_SIZE1_BASE_IDX 1 717c54a60dbSLeo Liu #define mmUVD_VCPU_CNTL 0x0156 718c54a60dbSLeo Liu #define mmUVD_VCPU_CNTL_BASE_IDX 1 719c54a60dbSLeo Liu #define mmUVD_VCPU_PRID 0x0157 720c54a60dbSLeo Liu #define mmUVD_VCPU_PRID_BASE_IDX 1 721c54a60dbSLeo Liu #define mmUVD_VCPU_TRCE 0x0158 722c54a60dbSLeo Liu #define mmUVD_VCPU_TRCE_BASE_IDX 1 723c54a60dbSLeo Liu #define mmUVD_VCPU_TRCE_RD 0x0159 724c54a60dbSLeo Liu #define mmUVD_VCPU_TRCE_RD_BASE_IDX 1 725c54a60dbSLeo Liu 726c54a60dbSLeo Liu 727c54a60dbSLeo Liu // addressBlock: uvd0_uvd_mpcdec 728c54a60dbSLeo Liu // base address: 0x20310 729c54a60dbSLeo Liu #define mmUVD_MP_SWAP_CNTL 0x02c4 730c54a60dbSLeo Liu #define mmUVD_MP_SWAP_CNTL_BASE_IDX 1 731c54a60dbSLeo Liu #define mmUVD_MP_SWAP_CNTL2 0x02c5 732c54a60dbSLeo Liu #define mmUVD_MP_SWAP_CNTL2_BASE_IDX 1 733c54a60dbSLeo Liu #define mmUVD_MPC_LUMA_SRCH 0x02c6 734c54a60dbSLeo Liu #define mmUVD_MPC_LUMA_SRCH_BASE_IDX 1 735c54a60dbSLeo Liu #define mmUVD_MPC_LUMA_HIT 0x02c7 736c54a60dbSLeo Liu #define mmUVD_MPC_LUMA_HIT_BASE_IDX 1 737c54a60dbSLeo Liu #define mmUVD_MPC_LUMA_HITPEND 0x02c8 738c54a60dbSLeo Liu #define mmUVD_MPC_LUMA_HITPEND_BASE_IDX 1 739c54a60dbSLeo Liu #define mmUVD_MPC_CHROMA_SRCH 0x02c9 740c54a60dbSLeo Liu #define mmUVD_MPC_CHROMA_SRCH_BASE_IDX 1 741c54a60dbSLeo Liu #define mmUVD_MPC_CHROMA_HIT 0x02ca 742c54a60dbSLeo Liu #define mmUVD_MPC_CHROMA_HIT_BASE_IDX 1 743c54a60dbSLeo Liu #define mmUVD_MPC_CHROMA_HITPEND 0x02cb 744c54a60dbSLeo Liu #define mmUVD_MPC_CHROMA_HITPEND_BASE_IDX 1 745c54a60dbSLeo Liu #define mmUVD_MPC_CNTL 0x02cc 746c54a60dbSLeo Liu #define mmUVD_MPC_CNTL_BASE_IDX 1 747c54a60dbSLeo Liu #define mmUVD_MPC_PITCH 0x02cd 748c54a60dbSLeo Liu #define mmUVD_MPC_PITCH_BASE_IDX 1 749c54a60dbSLeo Liu #define mmUVD_MPC_SET_MUXA0 0x02ce 750c54a60dbSLeo Liu #define mmUVD_MPC_SET_MUXA0_BASE_IDX 1 751c54a60dbSLeo Liu #define mmUVD_MPC_SET_MUXA1 0x02cf 752c54a60dbSLeo Liu #define mmUVD_MPC_SET_MUXA1_BASE_IDX 1 753c54a60dbSLeo Liu #define mmUVD_MPC_SET_MUXB0 0x02d0 754c54a60dbSLeo Liu #define mmUVD_MPC_SET_MUXB0_BASE_IDX 1 755c54a60dbSLeo Liu #define mmUVD_MPC_SET_MUXB1 0x02d1 756c54a60dbSLeo Liu #define mmUVD_MPC_SET_MUXB1_BASE_IDX 1 757c54a60dbSLeo Liu #define mmUVD_MPC_SET_MUX 0x02d2 758c54a60dbSLeo Liu #define mmUVD_MPC_SET_MUX_BASE_IDX 1 759c54a60dbSLeo Liu #define mmUVD_MPC_SET_ALU 0x02d3 760c54a60dbSLeo Liu #define mmUVD_MPC_SET_ALU_BASE_IDX 1 761c54a60dbSLeo Liu #define mmUVD_MPC_PERF0 0x02d4 762c54a60dbSLeo Liu #define mmUVD_MPC_PERF0_BASE_IDX 1 763c54a60dbSLeo Liu #define mmUVD_MPC_PERF1 0x02d5 764c54a60dbSLeo Liu #define mmUVD_MPC_PERF1_BASE_IDX 1 765c54a60dbSLeo Liu 766c54a60dbSLeo Liu 767c54a60dbSLeo Liu // addressBlock: uvd0_uvd_rbcdec 768c54a60dbSLeo Liu // base address: 0x20370 769c54a60dbSLeo Liu #define mmUVD_RBC_IB_SIZE 0x02dc 770c54a60dbSLeo Liu #define mmUVD_RBC_IB_SIZE_BASE_IDX 1 771c54a60dbSLeo Liu #define mmUVD_RBC_IB_SIZE_UPDATE 0x02dd 772c54a60dbSLeo Liu #define mmUVD_RBC_IB_SIZE_UPDATE_BASE_IDX 1 773c54a60dbSLeo Liu #define mmUVD_RBC_RB_CNTL 0x02de 774c54a60dbSLeo Liu #define mmUVD_RBC_RB_CNTL_BASE_IDX 1 775c54a60dbSLeo Liu #define mmUVD_RBC_RB_RPTR_ADDR 0x02df 776c54a60dbSLeo Liu #define mmUVD_RBC_RB_RPTR_ADDR_BASE_IDX 1 777c54a60dbSLeo Liu #define mmUVD_RBC_RB_RPTR 0x02e0 778c54a60dbSLeo Liu #define mmUVD_RBC_RB_RPTR_BASE_IDX 1 779c54a60dbSLeo Liu #define mmUVD_RBC_RB_WPTR 0x02e1 780c54a60dbSLeo Liu #define mmUVD_RBC_RB_WPTR_BASE_IDX 1 781c54a60dbSLeo Liu #define mmUVD_RBC_VCPU_ACCESS 0x02e2 782c54a60dbSLeo Liu #define mmUVD_RBC_VCPU_ACCESS_BASE_IDX 1 783c54a60dbSLeo Liu #define mmUVD_RBC_READ_REQ_URGENT_CNTL 0x02e5 784c54a60dbSLeo Liu #define mmUVD_RBC_READ_REQ_URGENT_CNTL_BASE_IDX 1 785c54a60dbSLeo Liu #define mmUVD_RBC_RB_WPTR_CNTL 0x02e6 786c54a60dbSLeo Liu #define mmUVD_RBC_RB_WPTR_CNTL_BASE_IDX 1 787c54a60dbSLeo Liu #define mmUVD_RBC_WPTR_STATUS 0x02e7 788c54a60dbSLeo Liu #define mmUVD_RBC_WPTR_STATUS_BASE_IDX 1 789c54a60dbSLeo Liu #define mmUVD_RBC_WPTR_POLL_CNTL 0x02e8 790c54a60dbSLeo Liu #define mmUVD_RBC_WPTR_POLL_CNTL_BASE_IDX 1 791c54a60dbSLeo Liu #define mmUVD_RBC_WPTR_POLL_ADDR 0x02e9 792c54a60dbSLeo Liu #define mmUVD_RBC_WPTR_POLL_ADDR_BASE_IDX 1 793c54a60dbSLeo Liu #define mmUVD_SEMA_CMD 0x02ea 794c54a60dbSLeo Liu #define mmUVD_SEMA_CMD_BASE_IDX 1 795c54a60dbSLeo Liu #define mmUVD_SEMA_ADDR_LOW 0x02eb 796c54a60dbSLeo Liu #define mmUVD_SEMA_ADDR_LOW_BASE_IDX 1 797c54a60dbSLeo Liu #define mmUVD_SEMA_ADDR_HIGH 0x02ec 798c54a60dbSLeo Liu #define mmUVD_SEMA_ADDR_HIGH_BASE_IDX 1 799c54a60dbSLeo Liu #define mmUVD_ENGINE_CNTL 0x02ed 800c54a60dbSLeo Liu #define mmUVD_ENGINE_CNTL_BASE_IDX 1 801c54a60dbSLeo Liu #define mmUVD_SEMA_TIMEOUT_STATUS 0x02ee 802c54a60dbSLeo Liu #define mmUVD_SEMA_TIMEOUT_STATUS_BASE_IDX 1 803c54a60dbSLeo Liu #define mmUVD_SEMA_CNTL 0x02ef 804c54a60dbSLeo Liu #define mmUVD_SEMA_CNTL_BASE_IDX 1 805c54a60dbSLeo Liu #define mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL 0x02f0 806c54a60dbSLeo Liu #define mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL_BASE_IDX 1 807c54a60dbSLeo Liu #define mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL 0x02f1 808c54a60dbSLeo Liu #define mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL_BASE_IDX 1 809c54a60dbSLeo Liu #define mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL 0x02f2 810c54a60dbSLeo Liu #define mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL_BASE_IDX 1 811c54a60dbSLeo Liu #define mmUVD_JOB_START 0x02f3 812c54a60dbSLeo Liu #define mmUVD_JOB_START_BASE_IDX 1 813c54a60dbSLeo Liu #define mmUVD_RBC_BUF_STATUS 0x02f4 814c54a60dbSLeo Liu #define mmUVD_RBC_BUF_STATUS_BASE_IDX 1 815c54a60dbSLeo Liu 816c54a60dbSLeo Liu 817c54a60dbSLeo Liu // addressBlock: uvd0_uvdgendec 818c54a60dbSLeo Liu // base address: 0x20470 819c54a60dbSLeo Liu #define mmUVD_LCM_CGC_CNTRL 0x033f 820c54a60dbSLeo Liu #define mmUVD_LCM_CGC_CNTRL_BASE_IDX 1 821c54a60dbSLeo Liu #define mmUVD_MIF_CURR_UV_ADDR_CONFIG 0x03a0 822c54a60dbSLeo Liu #define mmUVD_MIF_CURR_UV_ADDR_CONFIG_BASE_IDX 1 823c54a60dbSLeo Liu #define mmUVD_MIF_REF_UV_ADDR_CONFIG 0x03a1 824c54a60dbSLeo Liu #define mmUVD_MIF_REF_UV_ADDR_CONFIG_BASE_IDX 1 825c54a60dbSLeo Liu #define mmUVD_MIF_RECON1_UV_ADDR_CONFIG 0x03a2 826c54a60dbSLeo Liu #define mmUVD_MIF_RECON1_UV_ADDR_CONFIG_BASE_IDX 1 827c54a60dbSLeo Liu #define mmUVD_MIF_CURR_ADDR_CONFIG 0x03ae 828c54a60dbSLeo Liu #define mmUVD_MIF_CURR_ADDR_CONFIG_BASE_IDX 1 829c54a60dbSLeo Liu #define mmUVD_MIF_REF_ADDR_CONFIG 0x03af 830c54a60dbSLeo Liu #define mmUVD_MIF_REF_ADDR_CONFIG_BASE_IDX 1 831c54a60dbSLeo Liu #define mmUVD_MIF_RECON1_ADDR_CONFIG 0x03e1 832c54a60dbSLeo Liu #define mmUVD_MIF_RECON1_ADDR_CONFIG_BASE_IDX 1 833c54a60dbSLeo Liu 834c54a60dbSLeo Liu 835c54a60dbSLeo Liu // addressBlock: uvd0_lmi_adpdec 836c54a60dbSLeo Liu // base address: 0x20870 837c54a60dbSLeo Liu #define mmUVD_LMI_RBC_RB_64BIT_BAR_LOW 0x0432 838c54a60dbSLeo Liu #define mmUVD_LMI_RBC_RB_64BIT_BAR_LOW_BASE_IDX 1 839c54a60dbSLeo Liu #define mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH 0x0433 840c54a60dbSLeo Liu #define mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH_BASE_IDX 1 841c54a60dbSLeo Liu #define mmUVD_LMI_RBC_IB_64BIT_BAR_LOW 0x0434 842c54a60dbSLeo Liu #define mmUVD_LMI_RBC_IB_64BIT_BAR_LOW_BASE_IDX 1 843c54a60dbSLeo Liu #define mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH 0x0435 844c54a60dbSLeo Liu #define mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH_BASE_IDX 1 845c54a60dbSLeo Liu #define mmUVD_LMI_VCPU_NC0_64BIT_BAR_LOW 0x0438 846c54a60dbSLeo Liu #define mmUVD_LMI_VCPU_NC0_64BIT_BAR_LOW_BASE_IDX 1 847c54a60dbSLeo Liu #define mmUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH 0x0439 848c54a60dbSLeo Liu #define mmUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH_BASE_IDX 1 849c54a60dbSLeo Liu #define mmUVD_LMI_VCPU_NC1_64BIT_BAR_LOW 0x043a 850c54a60dbSLeo Liu #define mmUVD_LMI_VCPU_NC1_64BIT_BAR_LOW_BASE_IDX 1 851c54a60dbSLeo Liu #define mmUVD_LMI_VCPU_NC1_64BIT_BAR_HIGH 0x043b 852c54a60dbSLeo Liu #define mmUVD_LMI_VCPU_NC1_64BIT_BAR_HIGH_BASE_IDX 1 853c54a60dbSLeo Liu #define mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW 0x043c 854c54a60dbSLeo Liu #define mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW_BASE_IDX 1 855c54a60dbSLeo Liu #define mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH 0x043d 856c54a60dbSLeo Liu #define mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH_BASE_IDX 1 857c54a60dbSLeo Liu #define mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW 0x0468 858c54a60dbSLeo Liu #define mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW_BASE_IDX 1 859c54a60dbSLeo Liu #define mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH 0x0469 860c54a60dbSLeo Liu #define mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH_BASE_IDX 1 861c54a60dbSLeo Liu #define mmUVD_LMI_VCPU_CACHE8_64BIT_BAR_LOW 0x046a 862c54a60dbSLeo Liu #define mmUVD_LMI_VCPU_CACHE8_64BIT_BAR_LOW_BASE_IDX 1 863c54a60dbSLeo Liu #define mmUVD_LMI_VCPU_CACHE8_64BIT_BAR_HIGH 0x046b 864c54a60dbSLeo Liu #define mmUVD_LMI_VCPU_CACHE8_64BIT_BAR_HIGH_BASE_IDX 1 865c54a60dbSLeo Liu #define mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW 0x046c 866c54a60dbSLeo Liu #define mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW_BASE_IDX 1 867c54a60dbSLeo Liu #define mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH 0x046d 868c54a60dbSLeo Liu #define mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH_BASE_IDX 1 869c54a60dbSLeo Liu #define mmUVD_LMI_VCPU_CACHE3_64BIT_BAR_LOW 0x046e 870c54a60dbSLeo Liu #define mmUVD_LMI_VCPU_CACHE3_64BIT_BAR_LOW_BASE_IDX 1 871c54a60dbSLeo Liu #define mmUVD_LMI_VCPU_CACHE3_64BIT_BAR_HIGH 0x046f 872c54a60dbSLeo Liu #define mmUVD_LMI_VCPU_CACHE3_64BIT_BAR_HIGH_BASE_IDX 1 873c54a60dbSLeo Liu #define mmUVD_LMI_VCPU_CACHE4_64BIT_BAR_LOW 0x0470 874c54a60dbSLeo Liu #define mmUVD_LMI_VCPU_CACHE4_64BIT_BAR_LOW_BASE_IDX 1 875c54a60dbSLeo Liu #define mmUVD_LMI_VCPU_CACHE4_64BIT_BAR_HIGH 0x0471 876c54a60dbSLeo Liu #define mmUVD_LMI_VCPU_CACHE4_64BIT_BAR_HIGH_BASE_IDX 1 877c54a60dbSLeo Liu #define mmUVD_LMI_VCPU_CACHE5_64BIT_BAR_LOW 0x0472 878c54a60dbSLeo Liu #define mmUVD_LMI_VCPU_CACHE5_64BIT_BAR_LOW_BASE_IDX 1 879c54a60dbSLeo Liu #define mmUVD_LMI_VCPU_CACHE5_64BIT_BAR_HIGH 0x0473 880c54a60dbSLeo Liu #define mmUVD_LMI_VCPU_CACHE5_64BIT_BAR_HIGH_BASE_IDX 1 881c54a60dbSLeo Liu #define mmUVD_LMI_VCPU_CACHE6_64BIT_BAR_LOW 0x0474 882c54a60dbSLeo Liu #define mmUVD_LMI_VCPU_CACHE6_64BIT_BAR_LOW_BASE_IDX 1 883c54a60dbSLeo Liu #define mmUVD_LMI_VCPU_CACHE6_64BIT_BAR_HIGH 0x0475 884c54a60dbSLeo Liu #define mmUVD_LMI_VCPU_CACHE6_64BIT_BAR_HIGH_BASE_IDX 1 885c54a60dbSLeo Liu #define mmUVD_LMI_VCPU_CACHE7_64BIT_BAR_LOW 0x0476 886c54a60dbSLeo Liu #define mmUVD_LMI_VCPU_CACHE7_64BIT_BAR_LOW_BASE_IDX 1 887c54a60dbSLeo Liu #define mmUVD_LMI_VCPU_CACHE7_64BIT_BAR_HIGH 0x0477 888c54a60dbSLeo Liu #define mmUVD_LMI_VCPU_CACHE7_64BIT_BAR_HIGH_BASE_IDX 1 889c54a60dbSLeo Liu #define mmUVD_LMI_SPH_64BIT_BAR_HIGH 0x047c 890c54a60dbSLeo Liu #define mmUVD_LMI_SPH_64BIT_BAR_HIGH_BASE_IDX 1 891c54a60dbSLeo Liu #define mmUVD_LMI_MMSCH_NC0_64BIT_BAR_LOW 0x047d 892c54a60dbSLeo Liu #define mmUVD_LMI_MMSCH_NC0_64BIT_BAR_LOW_BASE_IDX 1 893c54a60dbSLeo Liu #define mmUVD_LMI_MMSCH_NC0_64BIT_BAR_HIGH 0x047e 894c54a60dbSLeo Liu #define mmUVD_LMI_MMSCH_NC0_64BIT_BAR_HIGH_BASE_IDX 1 895c54a60dbSLeo Liu #define mmUVD_LMI_MMSCH_NC1_64BIT_BAR_LOW 0x047f 896c54a60dbSLeo Liu #define mmUVD_LMI_MMSCH_NC1_64BIT_BAR_LOW_BASE_IDX 1 897c54a60dbSLeo Liu #define mmUVD_LMI_MMSCH_NC1_64BIT_BAR_HIGH 0x0480 898c54a60dbSLeo Liu #define mmUVD_LMI_MMSCH_NC1_64BIT_BAR_HIGH_BASE_IDX 1 899c54a60dbSLeo Liu #define mmUVD_LMI_MMSCH_NC2_64BIT_BAR_LOW 0x0481 900c54a60dbSLeo Liu #define mmUVD_LMI_MMSCH_NC2_64BIT_BAR_LOW_BASE_IDX 1 901c54a60dbSLeo Liu #define mmUVD_LMI_MMSCH_NC2_64BIT_BAR_HIGH 0x0482 902c54a60dbSLeo Liu #define mmUVD_LMI_MMSCH_NC2_64BIT_BAR_HIGH_BASE_IDX 1 903c54a60dbSLeo Liu #define mmUVD_LMI_MMSCH_NC3_64BIT_BAR_LOW 0x0483 904c54a60dbSLeo Liu #define mmUVD_LMI_MMSCH_NC3_64BIT_BAR_LOW_BASE_IDX 1 905c54a60dbSLeo Liu #define mmUVD_LMI_MMSCH_NC3_64BIT_BAR_HIGH 0x0484 906c54a60dbSLeo Liu #define mmUVD_LMI_MMSCH_NC3_64BIT_BAR_HIGH_BASE_IDX 1 907c54a60dbSLeo Liu #define mmUVD_LMI_MMSCH_NC4_64BIT_BAR_LOW 0x0485 908c54a60dbSLeo Liu #define mmUVD_LMI_MMSCH_NC4_64BIT_BAR_LOW_BASE_IDX 1 909c54a60dbSLeo Liu #define mmUVD_LMI_MMSCH_NC4_64BIT_BAR_HIGH 0x0486 910c54a60dbSLeo Liu #define mmUVD_LMI_MMSCH_NC4_64BIT_BAR_HIGH_BASE_IDX 1 911c54a60dbSLeo Liu #define mmUVD_LMI_MMSCH_NC5_64BIT_BAR_LOW 0x0487 912c54a60dbSLeo Liu #define mmUVD_LMI_MMSCH_NC5_64BIT_BAR_LOW_BASE_IDX 1 913c54a60dbSLeo Liu #define mmUVD_LMI_MMSCH_NC5_64BIT_BAR_HIGH 0x0488 914c54a60dbSLeo Liu #define mmUVD_LMI_MMSCH_NC5_64BIT_BAR_HIGH_BASE_IDX 1 915c54a60dbSLeo Liu #define mmUVD_LMI_MMSCH_NC6_64BIT_BAR_LOW 0x0489 916c54a60dbSLeo Liu #define mmUVD_LMI_MMSCH_NC6_64BIT_BAR_LOW_BASE_IDX 1 917c54a60dbSLeo Liu #define mmUVD_LMI_MMSCH_NC6_64BIT_BAR_HIGH 0x048a 918c54a60dbSLeo Liu #define mmUVD_LMI_MMSCH_NC6_64BIT_BAR_HIGH_BASE_IDX 1 919c54a60dbSLeo Liu #define mmUVD_LMI_MMSCH_NC7_64BIT_BAR_LOW 0x048b 920c54a60dbSLeo Liu #define mmUVD_LMI_MMSCH_NC7_64BIT_BAR_LOW_BASE_IDX 1 921c54a60dbSLeo Liu #define mmUVD_LMI_MMSCH_NC7_64BIT_BAR_HIGH 0x048c 922c54a60dbSLeo Liu #define mmUVD_LMI_MMSCH_NC7_64BIT_BAR_HIGH_BASE_IDX 1 923c54a60dbSLeo Liu #define mmUVD_LMI_MMSCH_NC_VMID 0x048d 924c54a60dbSLeo Liu #define mmUVD_LMI_MMSCH_NC_VMID_BASE_IDX 1 925c54a60dbSLeo Liu #define mmUVD_LMI_MMSCH_CTRL 0x048e 926c54a60dbSLeo Liu #define mmUVD_LMI_MMSCH_CTRL_BASE_IDX 1 927c54a60dbSLeo Liu #define mmUVD_LMI_ARB_CTRL2 0x049a 928c54a60dbSLeo Liu #define mmUVD_LMI_ARB_CTRL2_BASE_IDX 1 929c54a60dbSLeo Liu #define mmUVD_LMI_VCPU_CACHE_VMIDS_MULTI 0x049f 930c54a60dbSLeo Liu #define mmUVD_LMI_VCPU_CACHE_VMIDS_MULTI_BASE_IDX 1 931c54a60dbSLeo Liu #define mmUVD_LMI_VCPU_NC_VMIDS_MULTI 0x04a0 932c54a60dbSLeo Liu #define mmUVD_LMI_VCPU_NC_VMIDS_MULTI_BASE_IDX 1 933c54a60dbSLeo Liu #define mmUVD_LMI_LAT_CTRL 0x04a1 934c54a60dbSLeo Liu #define mmUVD_LMI_LAT_CTRL_BASE_IDX 1 935c54a60dbSLeo Liu #define mmUVD_LMI_LAT_CNTR 0x04a2 936c54a60dbSLeo Liu #define mmUVD_LMI_LAT_CNTR_BASE_IDX 1 937c54a60dbSLeo Liu #define mmUVD_LMI_AVG_LAT_CNTR 0x04a3 938c54a60dbSLeo Liu #define mmUVD_LMI_AVG_LAT_CNTR_BASE_IDX 1 939c54a60dbSLeo Liu #define mmUVD_LMI_SPH 0x04a4 940c54a60dbSLeo Liu #define mmUVD_LMI_SPH_BASE_IDX 1 941c54a60dbSLeo Liu #define mmUVD_LMI_VCPU_CACHE_VMID 0x04a5 942c54a60dbSLeo Liu #define mmUVD_LMI_VCPU_CACHE_VMID_BASE_IDX 1 943c54a60dbSLeo Liu #define mmUVD_LMI_CTRL2 0x04a6 944c54a60dbSLeo Liu #define mmUVD_LMI_CTRL2_BASE_IDX 1 945c54a60dbSLeo Liu #define mmUVD_LMI_URGENT_CTRL 0x04a7 946c54a60dbSLeo Liu #define mmUVD_LMI_URGENT_CTRL_BASE_IDX 1 947c54a60dbSLeo Liu #define mmUVD_LMI_CTRL 0x04a8 948c54a60dbSLeo Liu #define mmUVD_LMI_CTRL_BASE_IDX 1 949c54a60dbSLeo Liu #define mmUVD_LMI_STATUS 0x04a9 950c54a60dbSLeo Liu #define mmUVD_LMI_STATUS_BASE_IDX 1 951c54a60dbSLeo Liu #define mmUVD_LMI_PERFMON_CTRL 0x04ac 952c54a60dbSLeo Liu #define mmUVD_LMI_PERFMON_CTRL_BASE_IDX 1 953c54a60dbSLeo Liu #define mmUVD_LMI_PERFMON_COUNT_LO 0x04ad 954c54a60dbSLeo Liu #define mmUVD_LMI_PERFMON_COUNT_LO_BASE_IDX 1 955c54a60dbSLeo Liu #define mmUVD_LMI_PERFMON_COUNT_HI 0x04ae 956c54a60dbSLeo Liu #define mmUVD_LMI_PERFMON_COUNT_HI_BASE_IDX 1 957c54a60dbSLeo Liu #define mmUVD_LMI_RBC_RB_VMID 0x04b0 958c54a60dbSLeo Liu #define mmUVD_LMI_RBC_RB_VMID_BASE_IDX 1 959c54a60dbSLeo Liu #define mmUVD_LMI_RBC_IB_VMID 0x04b1 960c54a60dbSLeo Liu #define mmUVD_LMI_RBC_IB_VMID_BASE_IDX 1 961c54a60dbSLeo Liu #define mmUVD_LMI_MC_CREDITS 0x04b2 962c54a60dbSLeo Liu #define mmUVD_LMI_MC_CREDITS_BASE_IDX 1 963c54a60dbSLeo Liu 964c54a60dbSLeo Liu 965c54a60dbSLeo Liu // addressBlock: uvd0_uvdnpdec 966c54a60dbSLeo Liu // base address: 0x20bd0 967c54a60dbSLeo Liu #define mmMDM_DMA_CMD 0x06f4 968c54a60dbSLeo Liu #define mmMDM_DMA_CMD_BASE_IDX 1 969c54a60dbSLeo Liu #define mmMDM_DMA_STATUS 0x06f5 970c54a60dbSLeo Liu #define mmMDM_DMA_STATUS_BASE_IDX 1 971c54a60dbSLeo Liu #define mmMDM_DMA_CTL 0x06f6 972c54a60dbSLeo Liu #define mmMDM_DMA_CTL_BASE_IDX 1 973c54a60dbSLeo Liu #define mmMDM_ENC_PIPE_BUSY 0x06f7 974c54a60dbSLeo Liu #define mmMDM_ENC_PIPE_BUSY_BASE_IDX 1 975c54a60dbSLeo Liu #define mmMDM_WIG_PIPE_BUSY 0x06f9 976c54a60dbSLeo Liu #define mmMDM_WIG_PIPE_BUSY_BASE_IDX 1 977c54a60dbSLeo Liu 978c54a60dbSLeo Liu 979c54a60dbSLeo Liu #endif 980