1 #ifndef _umc_8_7_0_SH_MASK_HEADER
2 #define _umc_8_7_0_SH_MASK_HEADER
3 
4 //UMCCH0_0_GeccErrCntSel
5 #define UMCCH0_0_GeccErrCntSel__GeccErrCntCsSel__SHIFT                                                        0x0
6 #define UMCCH0_0_GeccErrCntSel__GeccErrInt__SHIFT                                                             0xc
7 #define UMCCH0_0_GeccErrCntSel__GeccErrCntEn__SHIFT                                                           0xf
8 #define UMCCH0_0_GeccErrCntSel__PoisonCntEn__SHIFT                                                            0x10
9 #define UMCCH0_0_GeccErrCntSel__GeccErrCntCsSel_MASK                                                          0x0000000FL
10 #define UMCCH0_0_GeccErrCntSel__GeccErrInt_MASK                                                               0x00003000L
11 #define UMCCH0_0_GeccErrCntSel__GeccErrCntEn_MASK                                                             0x00008000L
12 #define UMCCH0_0_GeccErrCntSel__PoisonCntEn_MASK                                                              0x00030000L
13 //UMCCH0_0_GeccErrCnt
14 #define UMCCH0_0_GeccErrCnt__GeccErrCnt__SHIFT                                                                0x0
15 #define UMCCH0_0_GeccErrCnt__GeccUnCorrErrCnt__SHIFT                                                          0x10
16 #define UMCCH0_0_GeccErrCnt__GeccErrCnt_MASK                                                                  0x0000FFFFL
17 #define UMCCH0_0_GeccErrCnt__GeccUnCorrErrCnt_MASK                                                            0xFFFF0000L
18 //MCA_UMC_UMC0_MCUMC_STATUST0
19 #define MCA_UMC_UMC0_MCUMC_STATUST0__ErrorCode__SHIFT                                                         0x0
20 #define MCA_UMC_UMC0_MCUMC_STATUST0__ErrorCodeExt__SHIFT                                                      0x10
21 #define MCA_UMC_UMC0_MCUMC_STATUST0__RESERV22__SHIFT                                                          0x16
22 #define MCA_UMC_UMC0_MCUMC_STATUST0__AddrLsb__SHIFT                                                           0x18
23 #define MCA_UMC_UMC0_MCUMC_STATUST0__RESERV30__SHIFT                                                          0x1e
24 #define MCA_UMC_UMC0_MCUMC_STATUST0__ErrCoreId__SHIFT                                                         0x20
25 #define MCA_UMC_UMC0_MCUMC_STATUST0__RESERV38__SHIFT                                                          0x26
26 #define MCA_UMC_UMC0_MCUMC_STATUST0__Scrub__SHIFT                                                             0x28
27 #define MCA_UMC_UMC0_MCUMC_STATUST0__RESERV41__SHIFT                                                          0x29
28 #define MCA_UMC_UMC0_MCUMC_STATUST0__Poison__SHIFT                                                            0x2b
29 #define MCA_UMC_UMC0_MCUMC_STATUST0__Deferred__SHIFT                                                          0x2c
30 #define MCA_UMC_UMC0_MCUMC_STATUST0__UECC__SHIFT                                                              0x2d
31 #define MCA_UMC_UMC0_MCUMC_STATUST0__CECC__SHIFT                                                              0x2e
32 #define MCA_UMC_UMC0_MCUMC_STATUST0__RESERV47__SHIFT                                                          0x2f
33 #define MCA_UMC_UMC0_MCUMC_STATUST0__Transparent__SHIFT                                                       0x34
34 #define MCA_UMC_UMC0_MCUMC_STATUST0__SyndV__SHIFT                                                             0x35
35 #define MCA_UMC_UMC0_MCUMC_STATUST0__RESERV54__SHIFT                                                          0x36
36 #define MCA_UMC_UMC0_MCUMC_STATUST0__TCC__SHIFT                                                               0x37
37 #define MCA_UMC_UMC0_MCUMC_STATUST0__ErrCoreIdVal__SHIFT                                                      0x38
38 #define MCA_UMC_UMC0_MCUMC_STATUST0__PCC__SHIFT                                                               0x39
39 #define MCA_UMC_UMC0_MCUMC_STATUST0__AddrV__SHIFT                                                             0x3a
40 #define MCA_UMC_UMC0_MCUMC_STATUST0__MiscV__SHIFT                                                             0x3b
41 #define MCA_UMC_UMC0_MCUMC_STATUST0__En__SHIFT                                                                0x3c
42 #define MCA_UMC_UMC0_MCUMC_STATUST0__UC__SHIFT                                                                0x3d
43 #define MCA_UMC_UMC0_MCUMC_STATUST0__Overflow__SHIFT                                                          0x3e
44 #define MCA_UMC_UMC0_MCUMC_STATUST0__Val__SHIFT                                                               0x3f
45 #define MCA_UMC_UMC0_MCUMC_STATUST0__ErrorCode_MASK                                                           0x000000000000FFFFL
46 #define MCA_UMC_UMC0_MCUMC_STATUST0__ErrorCodeExt_MASK                                                        0x00000000003F0000L
47 #define MCA_UMC_UMC0_MCUMC_STATUST0__RESERV22_MASK                                                            0x0000000000C00000L
48 #define MCA_UMC_UMC0_MCUMC_STATUST0__AddrLsb_MASK                                                             0x000000003F000000L
49 #define MCA_UMC_UMC0_MCUMC_STATUST0__RESERV30_MASK                                                            0x00000000C0000000L
50 #define MCA_UMC_UMC0_MCUMC_STATUST0__ErrCoreId_MASK                                                           0x0000003F00000000L
51 #define MCA_UMC_UMC0_MCUMC_STATUST0__RESERV38_MASK                                                            0x000000C000000000L
52 #define MCA_UMC_UMC0_MCUMC_STATUST0__Scrub_MASK                                                               0x0000010000000000L
53 #define MCA_UMC_UMC0_MCUMC_STATUST0__RESERV41_MASK                                                            0x0000060000000000L
54 #define MCA_UMC_UMC0_MCUMC_STATUST0__Poison_MASK                                                              0x0000080000000000L
55 #define MCA_UMC_UMC0_MCUMC_STATUST0__Deferred_MASK                                                            0x0000100000000000L
56 #define MCA_UMC_UMC0_MCUMC_STATUST0__UECC_MASK                                                                0x0000200000000000L
57 #define MCA_UMC_UMC0_MCUMC_STATUST0__CECC_MASK                                                                0x0000400000000000L
58 #define MCA_UMC_UMC0_MCUMC_STATUST0__RESERV47_MASK                                                            0x000F800000000000L
59 #define MCA_UMC_UMC0_MCUMC_STATUST0__Transparent_MASK                                                         0x0010000000000000L
60 #define MCA_UMC_UMC0_MCUMC_STATUST0__SyndV_MASK                                                               0x0020000000000000L
61 #define MCA_UMC_UMC0_MCUMC_STATUST0__RESERV54_MASK                                                            0x0040000000000000L
62 #define MCA_UMC_UMC0_MCUMC_STATUST0__TCC_MASK                                                                 0x0080000000000000L
63 #define MCA_UMC_UMC0_MCUMC_STATUST0__ErrCoreIdVal_MASK                                                        0x0100000000000000L
64 #define MCA_UMC_UMC0_MCUMC_STATUST0__PCC_MASK                                                                 0x0200000000000000L
65 #define MCA_UMC_UMC0_MCUMC_STATUST0__AddrV_MASK                                                               0x0400000000000000L
66 #define MCA_UMC_UMC0_MCUMC_STATUST0__MiscV_MASK                                                               0x0800000000000000L
67 #define MCA_UMC_UMC0_MCUMC_STATUST0__En_MASK                                                                  0x1000000000000000L
68 #define MCA_UMC_UMC0_MCUMC_STATUST0__UC_MASK                                                                  0x2000000000000000L
69 #define MCA_UMC_UMC0_MCUMC_STATUST0__Overflow_MASK                                                            0x4000000000000000L
70 #define MCA_UMC_UMC0_MCUMC_STATUST0__Val_MASK                                                                 0x8000000000000000L
71 //MCA_UMC_UMC0_MCUMC_ADDRT0
72 #define MCA_UMC_UMC0_MCUMC_ADDRT0__ErrorAddr__SHIFT                                                           0x0
73 #define MCA_UMC_UMC0_MCUMC_ADDRT0__LSB__SHIFT                                                                 0x38
74 #define MCA_UMC_UMC0_MCUMC_ADDRT0__Reserved__SHIFT                                                            0x3e
75 #define MCA_UMC_UMC0_MCUMC_ADDRT0__ErrorAddr_MASK                                                             0x00FFFFFFFFFFFFFFL
76 #define MCA_UMC_UMC0_MCUMC_ADDRT0__LSB_MASK                                                                   0x3F00000000000000L
77 #define MCA_UMC_UMC0_MCUMC_ADDRT0__Reserved_MASK                                                              0xC000000000000000L
78 
79 #endif
80