14f727eceSLe Ma /* 24f727eceSLe Ma * Copyright (C) 2018 Advanced Micro Devices, Inc. 34f727eceSLe Ma * 44f727eceSLe Ma * Permission is hereby granted, free of charge, to any person obtaining a 54f727eceSLe Ma * copy of this software and associated documentation files (the "Software"), 64f727eceSLe Ma * to deal in the Software without restriction, including without limitation 74f727eceSLe Ma * the rights to use, copy, modify, merge, publish, distribute, sublicense, 84f727eceSLe Ma * and/or sell copies of the Software, and to permit persons to whom the 94f727eceSLe Ma * Software is furnished to do so, subject to the following conditions: 104f727eceSLe Ma * 114f727eceSLe Ma * The above copyright notice and this permission notice shall be included 124f727eceSLe Ma * in all copies or substantial portions of the Software. 134f727eceSLe Ma * 144f727eceSLe Ma * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 154f727eceSLe Ma * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 164f727eceSLe Ma * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 174f727eceSLe Ma * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN 184f727eceSLe Ma * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 194f727eceSLe Ma * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 204f727eceSLe Ma */ 214f727eceSLe Ma #ifndef _sdma7_4_2_2_SH_MASK_HEADER 224f727eceSLe Ma #define _sdma7_4_2_2_SH_MASK_HEADER 234f727eceSLe Ma 244f727eceSLe Ma 254f727eceSLe Ma // addressBlock: sdma7_sdma7dec 264f727eceSLe Ma //SDMA7_UCODE_ADDR 274f727eceSLe Ma #define SDMA7_UCODE_ADDR__VALUE__SHIFT 0x0 284f727eceSLe Ma #define SDMA7_UCODE_ADDR__VALUE_MASK 0x00001FFFL 294f727eceSLe Ma //SDMA7_UCODE_DATA 304f727eceSLe Ma #define SDMA7_UCODE_DATA__VALUE__SHIFT 0x0 314f727eceSLe Ma #define SDMA7_UCODE_DATA__VALUE_MASK 0xFFFFFFFFL 324f727eceSLe Ma //SDMA7_VM_CNTL 334f727eceSLe Ma #define SDMA7_VM_CNTL__CMD__SHIFT 0x0 344f727eceSLe Ma #define SDMA7_VM_CNTL__CMD_MASK 0x0000000FL 354f727eceSLe Ma //SDMA7_VM_CTX_LO 364f727eceSLe Ma #define SDMA7_VM_CTX_LO__ADDR__SHIFT 0x2 374f727eceSLe Ma #define SDMA7_VM_CTX_LO__ADDR_MASK 0xFFFFFFFCL 384f727eceSLe Ma //SDMA7_VM_CTX_HI 394f727eceSLe Ma #define SDMA7_VM_CTX_HI__ADDR__SHIFT 0x0 404f727eceSLe Ma #define SDMA7_VM_CTX_HI__ADDR_MASK 0xFFFFFFFFL 414f727eceSLe Ma //SDMA7_ACTIVE_FCN_ID 424f727eceSLe Ma #define SDMA7_ACTIVE_FCN_ID__VFID__SHIFT 0x0 434f727eceSLe Ma #define SDMA7_ACTIVE_FCN_ID__RESERVED__SHIFT 0x4 444f727eceSLe Ma #define SDMA7_ACTIVE_FCN_ID__VF__SHIFT 0x1f 454f727eceSLe Ma #define SDMA7_ACTIVE_FCN_ID__VFID_MASK 0x0000000FL 464f727eceSLe Ma #define SDMA7_ACTIVE_FCN_ID__RESERVED_MASK 0x7FFFFFF0L 474f727eceSLe Ma #define SDMA7_ACTIVE_FCN_ID__VF_MASK 0x80000000L 484f727eceSLe Ma //SDMA7_VM_CTX_CNTL 494f727eceSLe Ma #define SDMA7_VM_CTX_CNTL__PRIV__SHIFT 0x0 504f727eceSLe Ma #define SDMA7_VM_CTX_CNTL__VMID__SHIFT 0x4 514f727eceSLe Ma #define SDMA7_VM_CTX_CNTL__PRIV_MASK 0x00000001L 524f727eceSLe Ma #define SDMA7_VM_CTX_CNTL__VMID_MASK 0x000000F0L 534f727eceSLe Ma //SDMA7_VIRT_RESET_REQ 544f727eceSLe Ma #define SDMA7_VIRT_RESET_REQ__VF__SHIFT 0x0 554f727eceSLe Ma #define SDMA7_VIRT_RESET_REQ__PF__SHIFT 0x1f 564f727eceSLe Ma #define SDMA7_VIRT_RESET_REQ__VF_MASK 0x0000FFFFL 574f727eceSLe Ma #define SDMA7_VIRT_RESET_REQ__PF_MASK 0x80000000L 584f727eceSLe Ma //SDMA7_VF_ENABLE 594f727eceSLe Ma #define SDMA7_VF_ENABLE__VF_ENABLE__SHIFT 0x0 604f727eceSLe Ma #define SDMA7_VF_ENABLE__VF_ENABLE_MASK 0x00000001L 614f727eceSLe Ma //SDMA7_CONTEXT_REG_TYPE0 624f727eceSLe Ma #define SDMA7_CONTEXT_REG_TYPE0__SDMA7_GFX_RB_CNTL__SHIFT 0x0 634f727eceSLe Ma #define SDMA7_CONTEXT_REG_TYPE0__SDMA7_GFX_RB_BASE__SHIFT 0x1 644f727eceSLe Ma #define SDMA7_CONTEXT_REG_TYPE0__SDMA7_GFX_RB_BASE_HI__SHIFT 0x2 654f727eceSLe Ma #define SDMA7_CONTEXT_REG_TYPE0__SDMA7_GFX_RB_RPTR__SHIFT 0x3 664f727eceSLe Ma #define SDMA7_CONTEXT_REG_TYPE0__SDMA7_GFX_RB_RPTR_HI__SHIFT 0x4 674f727eceSLe Ma #define SDMA7_CONTEXT_REG_TYPE0__SDMA7_GFX_RB_WPTR__SHIFT 0x5 684f727eceSLe Ma #define SDMA7_CONTEXT_REG_TYPE0__SDMA7_GFX_RB_WPTR_HI__SHIFT 0x6 694f727eceSLe Ma #define SDMA7_CONTEXT_REG_TYPE0__SDMA7_GFX_RB_WPTR_POLL_CNTL__SHIFT 0x7 704f727eceSLe Ma #define SDMA7_CONTEXT_REG_TYPE0__SDMA7_GFX_RB_RPTR_ADDR_HI__SHIFT 0x8 714f727eceSLe Ma #define SDMA7_CONTEXT_REG_TYPE0__SDMA7_GFX_RB_RPTR_ADDR_LO__SHIFT 0x9 724f727eceSLe Ma #define SDMA7_CONTEXT_REG_TYPE0__SDMA7_GFX_IB_CNTL__SHIFT 0xa 734f727eceSLe Ma #define SDMA7_CONTEXT_REG_TYPE0__SDMA7_GFX_IB_RPTR__SHIFT 0xb 744f727eceSLe Ma #define SDMA7_CONTEXT_REG_TYPE0__SDMA7_GFX_IB_OFFSET__SHIFT 0xc 754f727eceSLe Ma #define SDMA7_CONTEXT_REG_TYPE0__SDMA7_GFX_IB_BASE_LO__SHIFT 0xd 764f727eceSLe Ma #define SDMA7_CONTEXT_REG_TYPE0__SDMA7_GFX_IB_BASE_HI__SHIFT 0xe 774f727eceSLe Ma #define SDMA7_CONTEXT_REG_TYPE0__SDMA7_GFX_IB_SIZE__SHIFT 0xf 784f727eceSLe Ma #define SDMA7_CONTEXT_REG_TYPE0__SDMA7_GFX_SKIP_CNTL__SHIFT 0x10 794f727eceSLe Ma #define SDMA7_CONTEXT_REG_TYPE0__SDMA7_GFX_CONTEXT_STATUS__SHIFT 0x11 804f727eceSLe Ma #define SDMA7_CONTEXT_REG_TYPE0__SDMA7_GFX_DOORBELL__SHIFT 0x12 814f727eceSLe Ma #define SDMA7_CONTEXT_REG_TYPE0__SDMA7_GFX_CONTEXT_CNTL__SHIFT 0x13 824f727eceSLe Ma #define SDMA7_CONTEXT_REG_TYPE0__SDMA7_GFX_RB_CNTL_MASK 0x00000001L 834f727eceSLe Ma #define SDMA7_CONTEXT_REG_TYPE0__SDMA7_GFX_RB_BASE_MASK 0x00000002L 844f727eceSLe Ma #define SDMA7_CONTEXT_REG_TYPE0__SDMA7_GFX_RB_BASE_HI_MASK 0x00000004L 854f727eceSLe Ma #define SDMA7_CONTEXT_REG_TYPE0__SDMA7_GFX_RB_RPTR_MASK 0x00000008L 864f727eceSLe Ma #define SDMA7_CONTEXT_REG_TYPE0__SDMA7_GFX_RB_RPTR_HI_MASK 0x00000010L 874f727eceSLe Ma #define SDMA7_CONTEXT_REG_TYPE0__SDMA7_GFX_RB_WPTR_MASK 0x00000020L 884f727eceSLe Ma #define SDMA7_CONTEXT_REG_TYPE0__SDMA7_GFX_RB_WPTR_HI_MASK 0x00000040L 894f727eceSLe Ma #define SDMA7_CONTEXT_REG_TYPE0__SDMA7_GFX_RB_WPTR_POLL_CNTL_MASK 0x00000080L 904f727eceSLe Ma #define SDMA7_CONTEXT_REG_TYPE0__SDMA7_GFX_RB_RPTR_ADDR_HI_MASK 0x00000100L 914f727eceSLe Ma #define SDMA7_CONTEXT_REG_TYPE0__SDMA7_GFX_RB_RPTR_ADDR_LO_MASK 0x00000200L 924f727eceSLe Ma #define SDMA7_CONTEXT_REG_TYPE0__SDMA7_GFX_IB_CNTL_MASK 0x00000400L 934f727eceSLe Ma #define SDMA7_CONTEXT_REG_TYPE0__SDMA7_GFX_IB_RPTR_MASK 0x00000800L 944f727eceSLe Ma #define SDMA7_CONTEXT_REG_TYPE0__SDMA7_GFX_IB_OFFSET_MASK 0x00001000L 954f727eceSLe Ma #define SDMA7_CONTEXT_REG_TYPE0__SDMA7_GFX_IB_BASE_LO_MASK 0x00002000L 964f727eceSLe Ma #define SDMA7_CONTEXT_REG_TYPE0__SDMA7_GFX_IB_BASE_HI_MASK 0x00004000L 974f727eceSLe Ma #define SDMA7_CONTEXT_REG_TYPE0__SDMA7_GFX_IB_SIZE_MASK 0x00008000L 984f727eceSLe Ma #define SDMA7_CONTEXT_REG_TYPE0__SDMA7_GFX_SKIP_CNTL_MASK 0x00010000L 994f727eceSLe Ma #define SDMA7_CONTEXT_REG_TYPE0__SDMA7_GFX_CONTEXT_STATUS_MASK 0x00020000L 1004f727eceSLe Ma #define SDMA7_CONTEXT_REG_TYPE0__SDMA7_GFX_DOORBELL_MASK 0x00040000L 1014f727eceSLe Ma #define SDMA7_CONTEXT_REG_TYPE0__SDMA7_GFX_CONTEXT_CNTL_MASK 0x00080000L 1024f727eceSLe Ma //SDMA7_CONTEXT_REG_TYPE1 1034f727eceSLe Ma #define SDMA7_CONTEXT_REG_TYPE1__SDMA7_GFX_STATUS__SHIFT 0x8 1044f727eceSLe Ma #define SDMA7_CONTEXT_REG_TYPE1__SDMA7_GFX_DOORBELL_LOG__SHIFT 0x9 1054f727eceSLe Ma #define SDMA7_CONTEXT_REG_TYPE1__SDMA7_GFX_WATERMARK__SHIFT 0xa 1064f727eceSLe Ma #define SDMA7_CONTEXT_REG_TYPE1__SDMA7_GFX_DOORBELL_OFFSET__SHIFT 0xb 1074f727eceSLe Ma #define SDMA7_CONTEXT_REG_TYPE1__SDMA7_GFX_CSA_ADDR_LO__SHIFT 0xc 1084f727eceSLe Ma #define SDMA7_CONTEXT_REG_TYPE1__SDMA7_GFX_CSA_ADDR_HI__SHIFT 0xd 1094f727eceSLe Ma #define SDMA7_CONTEXT_REG_TYPE1__VOID_REG2__SHIFT 0xe 1104f727eceSLe Ma #define SDMA7_CONTEXT_REG_TYPE1__SDMA7_GFX_IB_SUB_REMAIN__SHIFT 0xf 1114f727eceSLe Ma #define SDMA7_CONTEXT_REG_TYPE1__SDMA7_GFX_PREEMPT__SHIFT 0x10 1124f727eceSLe Ma #define SDMA7_CONTEXT_REG_TYPE1__SDMA7_GFX_DUMMY_REG__SHIFT 0x11 1134f727eceSLe Ma #define SDMA7_CONTEXT_REG_TYPE1__SDMA7_GFX_RB_WPTR_POLL_ADDR_HI__SHIFT 0x12 1144f727eceSLe Ma #define SDMA7_CONTEXT_REG_TYPE1__SDMA7_GFX_RB_WPTR_POLL_ADDR_LO__SHIFT 0x13 1154f727eceSLe Ma #define SDMA7_CONTEXT_REG_TYPE1__SDMA7_GFX_RB_AQL_CNTL__SHIFT 0x14 1164f727eceSLe Ma #define SDMA7_CONTEXT_REG_TYPE1__SDMA7_GFX_MINOR_PTR_UPDATE__SHIFT 0x15 1174f727eceSLe Ma #define SDMA7_CONTEXT_REG_TYPE1__RESERVED__SHIFT 0x16 1184f727eceSLe Ma #define SDMA7_CONTEXT_REG_TYPE1__SDMA7_GFX_STATUS_MASK 0x00000100L 1194f727eceSLe Ma #define SDMA7_CONTEXT_REG_TYPE1__SDMA7_GFX_DOORBELL_LOG_MASK 0x00000200L 1204f727eceSLe Ma #define SDMA7_CONTEXT_REG_TYPE1__SDMA7_GFX_WATERMARK_MASK 0x00000400L 1214f727eceSLe Ma #define SDMA7_CONTEXT_REG_TYPE1__SDMA7_GFX_DOORBELL_OFFSET_MASK 0x00000800L 1224f727eceSLe Ma #define SDMA7_CONTEXT_REG_TYPE1__SDMA7_GFX_CSA_ADDR_LO_MASK 0x00001000L 1234f727eceSLe Ma #define SDMA7_CONTEXT_REG_TYPE1__SDMA7_GFX_CSA_ADDR_HI_MASK 0x00002000L 1244f727eceSLe Ma #define SDMA7_CONTEXT_REG_TYPE1__VOID_REG2_MASK 0x00004000L 1254f727eceSLe Ma #define SDMA7_CONTEXT_REG_TYPE1__SDMA7_GFX_IB_SUB_REMAIN_MASK 0x00008000L 1264f727eceSLe Ma #define SDMA7_CONTEXT_REG_TYPE1__SDMA7_GFX_PREEMPT_MASK 0x00010000L 1274f727eceSLe Ma #define SDMA7_CONTEXT_REG_TYPE1__SDMA7_GFX_DUMMY_REG_MASK 0x00020000L 1284f727eceSLe Ma #define SDMA7_CONTEXT_REG_TYPE1__SDMA7_GFX_RB_WPTR_POLL_ADDR_HI_MASK 0x00040000L 1294f727eceSLe Ma #define SDMA7_CONTEXT_REG_TYPE1__SDMA7_GFX_RB_WPTR_POLL_ADDR_LO_MASK 0x00080000L 1304f727eceSLe Ma #define SDMA7_CONTEXT_REG_TYPE1__SDMA7_GFX_RB_AQL_CNTL_MASK 0x00100000L 1314f727eceSLe Ma #define SDMA7_CONTEXT_REG_TYPE1__SDMA7_GFX_MINOR_PTR_UPDATE_MASK 0x00200000L 1324f727eceSLe Ma #define SDMA7_CONTEXT_REG_TYPE1__RESERVED_MASK 0xFFC00000L 1334f727eceSLe Ma //SDMA7_CONTEXT_REG_TYPE2 1344f727eceSLe Ma #define SDMA7_CONTEXT_REG_TYPE2__SDMA7_GFX_MIDCMD_DATA0__SHIFT 0x0 1354f727eceSLe Ma #define SDMA7_CONTEXT_REG_TYPE2__SDMA7_GFX_MIDCMD_DATA1__SHIFT 0x1 1364f727eceSLe Ma #define SDMA7_CONTEXT_REG_TYPE2__SDMA7_GFX_MIDCMD_DATA2__SHIFT 0x2 1374f727eceSLe Ma #define SDMA7_CONTEXT_REG_TYPE2__SDMA7_GFX_MIDCMD_DATA3__SHIFT 0x3 1384f727eceSLe Ma #define SDMA7_CONTEXT_REG_TYPE2__SDMA7_GFX_MIDCMD_DATA4__SHIFT 0x4 1394f727eceSLe Ma #define SDMA7_CONTEXT_REG_TYPE2__SDMA7_GFX_MIDCMD_DATA5__SHIFT 0x5 1404f727eceSLe Ma #define SDMA7_CONTEXT_REG_TYPE2__SDMA7_GFX_MIDCMD_DATA6__SHIFT 0x6 1414f727eceSLe Ma #define SDMA7_CONTEXT_REG_TYPE2__SDMA7_GFX_MIDCMD_DATA7__SHIFT 0x7 1424f727eceSLe Ma #define SDMA7_CONTEXT_REG_TYPE2__SDMA7_GFX_MIDCMD_DATA8__SHIFT 0x8 1434f727eceSLe Ma #define SDMA7_CONTEXT_REG_TYPE2__SDMA7_GFX_MIDCMD_CNTL__SHIFT 0x9 1444f727eceSLe Ma #define SDMA7_CONTEXT_REG_TYPE2__RESERVED__SHIFT 0xa 1454f727eceSLe Ma #define SDMA7_CONTEXT_REG_TYPE2__SDMA7_GFX_MIDCMD_DATA0_MASK 0x00000001L 1464f727eceSLe Ma #define SDMA7_CONTEXT_REG_TYPE2__SDMA7_GFX_MIDCMD_DATA1_MASK 0x00000002L 1474f727eceSLe Ma #define SDMA7_CONTEXT_REG_TYPE2__SDMA7_GFX_MIDCMD_DATA2_MASK 0x00000004L 1484f727eceSLe Ma #define SDMA7_CONTEXT_REG_TYPE2__SDMA7_GFX_MIDCMD_DATA3_MASK 0x00000008L 1494f727eceSLe Ma #define SDMA7_CONTEXT_REG_TYPE2__SDMA7_GFX_MIDCMD_DATA4_MASK 0x00000010L 1504f727eceSLe Ma #define SDMA7_CONTEXT_REG_TYPE2__SDMA7_GFX_MIDCMD_DATA5_MASK 0x00000020L 1514f727eceSLe Ma #define SDMA7_CONTEXT_REG_TYPE2__SDMA7_GFX_MIDCMD_DATA6_MASK 0x00000040L 1524f727eceSLe Ma #define SDMA7_CONTEXT_REG_TYPE2__SDMA7_GFX_MIDCMD_DATA7_MASK 0x00000080L 1534f727eceSLe Ma #define SDMA7_CONTEXT_REG_TYPE2__SDMA7_GFX_MIDCMD_DATA8_MASK 0x00000100L 1544f727eceSLe Ma #define SDMA7_CONTEXT_REG_TYPE2__SDMA7_GFX_MIDCMD_CNTL_MASK 0x00000200L 1554f727eceSLe Ma #define SDMA7_CONTEXT_REG_TYPE2__RESERVED_MASK 0xFFFFFC00L 1564f727eceSLe Ma //SDMA7_CONTEXT_REG_TYPE3 1574f727eceSLe Ma #define SDMA7_CONTEXT_REG_TYPE3__RESERVED__SHIFT 0x0 1584f727eceSLe Ma #define SDMA7_CONTEXT_REG_TYPE3__RESERVED_MASK 0xFFFFFFFFL 1594f727eceSLe Ma //SDMA7_PUB_REG_TYPE0 1604f727eceSLe Ma #define SDMA7_PUB_REG_TYPE0__SDMA7_UCODE_ADDR__SHIFT 0x0 1614f727eceSLe Ma #define SDMA7_PUB_REG_TYPE0__SDMA7_UCODE_DATA__SHIFT 0x1 1624f727eceSLe Ma #define SDMA7_PUB_REG_TYPE0__RESERVED3__SHIFT 0x3 1634f727eceSLe Ma #define SDMA7_PUB_REG_TYPE0__SDMA7_VM_CNTL__SHIFT 0x4 1644f727eceSLe Ma #define SDMA7_PUB_REG_TYPE0__SDMA7_VM_CTX_LO__SHIFT 0x5 1654f727eceSLe Ma #define SDMA7_PUB_REG_TYPE0__SDMA7_VM_CTX_HI__SHIFT 0x6 1664f727eceSLe Ma #define SDMA7_PUB_REG_TYPE0__SDMA7_ACTIVE_FCN_ID__SHIFT 0x7 1674f727eceSLe Ma #define SDMA7_PUB_REG_TYPE0__SDMA7_VM_CTX_CNTL__SHIFT 0x8 1684f727eceSLe Ma #define SDMA7_PUB_REG_TYPE0__SDMA7_VIRT_RESET_REQ__SHIFT 0x9 1694f727eceSLe Ma #define SDMA7_PUB_REG_TYPE0__RESERVED10__SHIFT 0xa 1704f727eceSLe Ma #define SDMA7_PUB_REG_TYPE0__SDMA7_CONTEXT_REG_TYPE0__SHIFT 0xb 1714f727eceSLe Ma #define SDMA7_PUB_REG_TYPE0__SDMA7_CONTEXT_REG_TYPE1__SHIFT 0xc 1724f727eceSLe Ma #define SDMA7_PUB_REG_TYPE0__SDMA7_CONTEXT_REG_TYPE2__SHIFT 0xd 1734f727eceSLe Ma #define SDMA7_PUB_REG_TYPE0__SDMA7_CONTEXT_REG_TYPE3__SHIFT 0xe 1744f727eceSLe Ma #define SDMA7_PUB_REG_TYPE0__SDMA7_PUB_REG_TYPE0__SHIFT 0xf 1754f727eceSLe Ma #define SDMA7_PUB_REG_TYPE0__SDMA7_PUB_REG_TYPE1__SHIFT 0x10 1764f727eceSLe Ma #define SDMA7_PUB_REG_TYPE0__SDMA7_PUB_REG_TYPE2__SHIFT 0x11 1774f727eceSLe Ma #define SDMA7_PUB_REG_TYPE0__SDMA7_PUB_REG_TYPE3__SHIFT 0x12 1784f727eceSLe Ma #define SDMA7_PUB_REG_TYPE0__SDMA7_MMHUB_CNTL__SHIFT 0x13 1794f727eceSLe Ma #define SDMA7_PUB_REG_TYPE0__RESERVED_FOR_PSPSMU_ACCESS_ONLY__SHIFT 0x15 1804f727eceSLe Ma #define SDMA7_PUB_REG_TYPE0__SDMA7_CONTEXT_GROUP_BOUNDARY__SHIFT 0x19 1814f727eceSLe Ma #define SDMA7_PUB_REG_TYPE0__SDMA7_POWER_CNTL__SHIFT 0x1a 1824f727eceSLe Ma #define SDMA7_PUB_REG_TYPE0__SDMA7_CLK_CTRL__SHIFT 0x1b 1834f727eceSLe Ma #define SDMA7_PUB_REG_TYPE0__SDMA7_CNTL__SHIFT 0x1c 1844f727eceSLe Ma #define SDMA7_PUB_REG_TYPE0__SDMA7_CHICKEN_BITS__SHIFT 0x1d 1854f727eceSLe Ma #define SDMA7_PUB_REG_TYPE0__SDMA7_GB_ADDR_CONFIG__SHIFT 0x1e 1864f727eceSLe Ma #define SDMA7_PUB_REG_TYPE0__SDMA7_GB_ADDR_CONFIG_READ__SHIFT 0x1f 1874f727eceSLe Ma #define SDMA7_PUB_REG_TYPE0__SDMA7_UCODE_ADDR_MASK 0x00000001L 1884f727eceSLe Ma #define SDMA7_PUB_REG_TYPE0__SDMA7_UCODE_DATA_MASK 0x00000002L 1894f727eceSLe Ma #define SDMA7_PUB_REG_TYPE0__RESERVED3_MASK 0x00000008L 1904f727eceSLe Ma #define SDMA7_PUB_REG_TYPE0__SDMA7_VM_CNTL_MASK 0x00000010L 1914f727eceSLe Ma #define SDMA7_PUB_REG_TYPE0__SDMA7_VM_CTX_LO_MASK 0x00000020L 1924f727eceSLe Ma #define SDMA7_PUB_REG_TYPE0__SDMA7_VM_CTX_HI_MASK 0x00000040L 1934f727eceSLe Ma #define SDMA7_PUB_REG_TYPE0__SDMA7_ACTIVE_FCN_ID_MASK 0x00000080L 1944f727eceSLe Ma #define SDMA7_PUB_REG_TYPE0__SDMA7_VM_CTX_CNTL_MASK 0x00000100L 1954f727eceSLe Ma #define SDMA7_PUB_REG_TYPE0__SDMA7_VIRT_RESET_REQ_MASK 0x00000200L 1964f727eceSLe Ma #define SDMA7_PUB_REG_TYPE0__RESERVED10_MASK 0x00000400L 1974f727eceSLe Ma #define SDMA7_PUB_REG_TYPE0__SDMA7_CONTEXT_REG_TYPE0_MASK 0x00000800L 1984f727eceSLe Ma #define SDMA7_PUB_REG_TYPE0__SDMA7_CONTEXT_REG_TYPE1_MASK 0x00001000L 1994f727eceSLe Ma #define SDMA7_PUB_REG_TYPE0__SDMA7_CONTEXT_REG_TYPE2_MASK 0x00002000L 2004f727eceSLe Ma #define SDMA7_PUB_REG_TYPE0__SDMA7_CONTEXT_REG_TYPE3_MASK 0x00004000L 2014f727eceSLe Ma #define SDMA7_PUB_REG_TYPE0__SDMA7_PUB_REG_TYPE0_MASK 0x00008000L 2024f727eceSLe Ma #define SDMA7_PUB_REG_TYPE0__SDMA7_PUB_REG_TYPE1_MASK 0x00010000L 2034f727eceSLe Ma #define SDMA7_PUB_REG_TYPE0__SDMA7_PUB_REG_TYPE2_MASK 0x00020000L 2044f727eceSLe Ma #define SDMA7_PUB_REG_TYPE0__SDMA7_PUB_REG_TYPE3_MASK 0x00040000L 2054f727eceSLe Ma #define SDMA7_PUB_REG_TYPE0__SDMA7_MMHUB_CNTL_MASK 0x00080000L 2064f727eceSLe Ma #define SDMA7_PUB_REG_TYPE0__RESERVED_FOR_PSPSMU_ACCESS_ONLY_MASK 0x01E00000L 2074f727eceSLe Ma #define SDMA7_PUB_REG_TYPE0__SDMA7_CONTEXT_GROUP_BOUNDARY_MASK 0x02000000L 2084f727eceSLe Ma #define SDMA7_PUB_REG_TYPE0__SDMA7_POWER_CNTL_MASK 0x04000000L 2094f727eceSLe Ma #define SDMA7_PUB_REG_TYPE0__SDMA7_CLK_CTRL_MASK 0x08000000L 2104f727eceSLe Ma #define SDMA7_PUB_REG_TYPE0__SDMA7_CNTL_MASK 0x10000000L 2114f727eceSLe Ma #define SDMA7_PUB_REG_TYPE0__SDMA7_CHICKEN_BITS_MASK 0x20000000L 2124f727eceSLe Ma #define SDMA7_PUB_REG_TYPE0__SDMA7_GB_ADDR_CONFIG_MASK 0x40000000L 2134f727eceSLe Ma #define SDMA7_PUB_REG_TYPE0__SDMA7_GB_ADDR_CONFIG_READ_MASK 0x80000000L 2144f727eceSLe Ma //SDMA7_PUB_REG_TYPE1 2154f727eceSLe Ma #define SDMA7_PUB_REG_TYPE1__SDMA7_RB_RPTR_FETCH_HI__SHIFT 0x0 2164f727eceSLe Ma #define SDMA7_PUB_REG_TYPE1__SDMA7_SEM_WAIT_FAIL_TIMER_CNTL__SHIFT 0x1 2174f727eceSLe Ma #define SDMA7_PUB_REG_TYPE1__SDMA7_RB_RPTR_FETCH__SHIFT 0x2 2184f727eceSLe Ma #define SDMA7_PUB_REG_TYPE1__SDMA7_IB_OFFSET_FETCH__SHIFT 0x3 2194f727eceSLe Ma #define SDMA7_PUB_REG_TYPE1__SDMA7_PROGRAM__SHIFT 0x4 2204f727eceSLe Ma #define SDMA7_PUB_REG_TYPE1__SDMA7_STATUS_REG__SHIFT 0x5 2214f727eceSLe Ma #define SDMA7_PUB_REG_TYPE1__SDMA7_STATUS1_REG__SHIFT 0x6 2224f727eceSLe Ma #define SDMA7_PUB_REG_TYPE1__SDMA7_RD_BURST_CNTL__SHIFT 0x7 2234f727eceSLe Ma #define SDMA7_PUB_REG_TYPE1__SDMA7_HBM_PAGE_CONFIG__SHIFT 0x8 2244f727eceSLe Ma #define SDMA7_PUB_REG_TYPE1__SDMA7_UCODE_CHECKSUM__SHIFT 0x9 2254f727eceSLe Ma #define SDMA7_PUB_REG_TYPE1__SDMA7_F32_CNTL__SHIFT 0xa 2264f727eceSLe Ma #define SDMA7_PUB_REG_TYPE1__SDMA7_FREEZE__SHIFT 0xb 2274f727eceSLe Ma #define SDMA7_PUB_REG_TYPE1__SDMA7_PHASE0_QUANTUM__SHIFT 0xc 2284f727eceSLe Ma #define SDMA7_PUB_REG_TYPE1__SDMA7_PHASE1_QUANTUM__SHIFT 0xd 2294f727eceSLe Ma #define SDMA7_PUB_REG_TYPE1__SDMA_POWER_GATING__SHIFT 0xe 2304f727eceSLe Ma #define SDMA7_PUB_REG_TYPE1__SDMA_PGFSM_CONFIG__SHIFT 0xf 2314f727eceSLe Ma #define SDMA7_PUB_REG_TYPE1__SDMA_PGFSM_WRITE__SHIFT 0x10 2324f727eceSLe Ma #define SDMA7_PUB_REG_TYPE1__SDMA_PGFSM_READ__SHIFT 0x11 2334f727eceSLe Ma #define SDMA7_PUB_REG_TYPE1__SDMA7_EDC_CONFIG__SHIFT 0x12 2344f727eceSLe Ma #define SDMA7_PUB_REG_TYPE1__SDMA7_BA_THRESHOLD__SHIFT 0x13 2354f727eceSLe Ma #define SDMA7_PUB_REG_TYPE1__SDMA7_ID__SHIFT 0x14 2364f727eceSLe Ma #define SDMA7_PUB_REG_TYPE1__SDMA7_VERSION__SHIFT 0x15 2374f727eceSLe Ma #define SDMA7_PUB_REG_TYPE1__SDMA7_EDC_COUNTER__SHIFT 0x16 2384f727eceSLe Ma #define SDMA7_PUB_REG_TYPE1__SDMA7_EDC_COUNTER_CLEAR__SHIFT 0x17 2394f727eceSLe Ma #define SDMA7_PUB_REG_TYPE1__SDMA7_STATUS2_REG__SHIFT 0x18 2404f727eceSLe Ma #define SDMA7_PUB_REG_TYPE1__SDMA7_ATOMIC_CNTL__SHIFT 0x19 2414f727eceSLe Ma #define SDMA7_PUB_REG_TYPE1__SDMA7_ATOMIC_PREOP_LO__SHIFT 0x1a 2424f727eceSLe Ma #define SDMA7_PUB_REG_TYPE1__SDMA7_ATOMIC_PREOP_HI__SHIFT 0x1b 2434f727eceSLe Ma #define SDMA7_PUB_REG_TYPE1__SDMA7_UTCL1_CNTL__SHIFT 0x1c 2444f727eceSLe Ma #define SDMA7_PUB_REG_TYPE1__SDMA7_UTCL1_WATERMK__SHIFT 0x1d 2454f727eceSLe Ma #define SDMA7_PUB_REG_TYPE1__SDMA7_UTCL1_RD_STATUS__SHIFT 0x1e 2464f727eceSLe Ma #define SDMA7_PUB_REG_TYPE1__SDMA7_UTCL1_WR_STATUS__SHIFT 0x1f 2474f727eceSLe Ma #define SDMA7_PUB_REG_TYPE1__SDMA7_RB_RPTR_FETCH_HI_MASK 0x00000001L 2484f727eceSLe Ma #define SDMA7_PUB_REG_TYPE1__SDMA7_SEM_WAIT_FAIL_TIMER_CNTL_MASK 0x00000002L 2494f727eceSLe Ma #define SDMA7_PUB_REG_TYPE1__SDMA7_RB_RPTR_FETCH_MASK 0x00000004L 2504f727eceSLe Ma #define SDMA7_PUB_REG_TYPE1__SDMA7_IB_OFFSET_FETCH_MASK 0x00000008L 2514f727eceSLe Ma #define SDMA7_PUB_REG_TYPE1__SDMA7_PROGRAM_MASK 0x00000010L 2524f727eceSLe Ma #define SDMA7_PUB_REG_TYPE1__SDMA7_STATUS_REG_MASK 0x00000020L 2534f727eceSLe Ma #define SDMA7_PUB_REG_TYPE1__SDMA7_STATUS1_REG_MASK 0x00000040L 2544f727eceSLe Ma #define SDMA7_PUB_REG_TYPE1__SDMA7_RD_BURST_CNTL_MASK 0x00000080L 2554f727eceSLe Ma #define SDMA7_PUB_REG_TYPE1__SDMA7_HBM_PAGE_CONFIG_MASK 0x00000100L 2564f727eceSLe Ma #define SDMA7_PUB_REG_TYPE1__SDMA7_UCODE_CHECKSUM_MASK 0x00000200L 2574f727eceSLe Ma #define SDMA7_PUB_REG_TYPE1__SDMA7_F32_CNTL_MASK 0x00000400L 2584f727eceSLe Ma #define SDMA7_PUB_REG_TYPE1__SDMA7_FREEZE_MASK 0x00000800L 2594f727eceSLe Ma #define SDMA7_PUB_REG_TYPE1__SDMA7_PHASE0_QUANTUM_MASK 0x00001000L 2604f727eceSLe Ma #define SDMA7_PUB_REG_TYPE1__SDMA7_PHASE1_QUANTUM_MASK 0x00002000L 2614f727eceSLe Ma #define SDMA7_PUB_REG_TYPE1__SDMA_POWER_GATING_MASK 0x00004000L 2624f727eceSLe Ma #define SDMA7_PUB_REG_TYPE1__SDMA_PGFSM_CONFIG_MASK 0x00008000L 2634f727eceSLe Ma #define SDMA7_PUB_REG_TYPE1__SDMA_PGFSM_WRITE_MASK 0x00010000L 2644f727eceSLe Ma #define SDMA7_PUB_REG_TYPE1__SDMA_PGFSM_READ_MASK 0x00020000L 2654f727eceSLe Ma #define SDMA7_PUB_REG_TYPE1__SDMA7_EDC_CONFIG_MASK 0x00040000L 2664f727eceSLe Ma #define SDMA7_PUB_REG_TYPE1__SDMA7_BA_THRESHOLD_MASK 0x00080000L 2674f727eceSLe Ma #define SDMA7_PUB_REG_TYPE1__SDMA7_ID_MASK 0x00100000L 2684f727eceSLe Ma #define SDMA7_PUB_REG_TYPE1__SDMA7_VERSION_MASK 0x00200000L 2694f727eceSLe Ma #define SDMA7_PUB_REG_TYPE1__SDMA7_EDC_COUNTER_MASK 0x00400000L 2704f727eceSLe Ma #define SDMA7_PUB_REG_TYPE1__SDMA7_EDC_COUNTER_CLEAR_MASK 0x00800000L 2714f727eceSLe Ma #define SDMA7_PUB_REG_TYPE1__SDMA7_STATUS2_REG_MASK 0x01000000L 2724f727eceSLe Ma #define SDMA7_PUB_REG_TYPE1__SDMA7_ATOMIC_CNTL_MASK 0x02000000L 2734f727eceSLe Ma #define SDMA7_PUB_REG_TYPE1__SDMA7_ATOMIC_PREOP_LO_MASK 0x04000000L 2744f727eceSLe Ma #define SDMA7_PUB_REG_TYPE1__SDMA7_ATOMIC_PREOP_HI_MASK 0x08000000L 2754f727eceSLe Ma #define SDMA7_PUB_REG_TYPE1__SDMA7_UTCL1_CNTL_MASK 0x10000000L 2764f727eceSLe Ma #define SDMA7_PUB_REG_TYPE1__SDMA7_UTCL1_WATERMK_MASK 0x20000000L 2774f727eceSLe Ma #define SDMA7_PUB_REG_TYPE1__SDMA7_UTCL1_RD_STATUS_MASK 0x40000000L 2784f727eceSLe Ma #define SDMA7_PUB_REG_TYPE1__SDMA7_UTCL1_WR_STATUS_MASK 0x80000000L 2794f727eceSLe Ma //SDMA7_PUB_REG_TYPE2 2804f727eceSLe Ma #define SDMA7_PUB_REG_TYPE2__SDMA7_UTCL1_INV0__SHIFT 0x0 2814f727eceSLe Ma #define SDMA7_PUB_REG_TYPE2__SDMA7_UTCL1_INV1__SHIFT 0x1 2824f727eceSLe Ma #define SDMA7_PUB_REG_TYPE2__SDMA7_UTCL1_INV2__SHIFT 0x2 2834f727eceSLe Ma #define SDMA7_PUB_REG_TYPE2__SDMA7_UTCL1_RD_XNACK0__SHIFT 0x3 2844f727eceSLe Ma #define SDMA7_PUB_REG_TYPE2__SDMA7_UTCL1_RD_XNACK1__SHIFT 0x4 2854f727eceSLe Ma #define SDMA7_PUB_REG_TYPE2__SDMA7_UTCL1_WR_XNACK0__SHIFT 0x5 2864f727eceSLe Ma #define SDMA7_PUB_REG_TYPE2__SDMA7_UTCL1_WR_XNACK1__SHIFT 0x6 2874f727eceSLe Ma #define SDMA7_PUB_REG_TYPE2__SDMA7_UTCL1_TIMEOUT__SHIFT 0x7 2884f727eceSLe Ma #define SDMA7_PUB_REG_TYPE2__SDMA7_UTCL1_PAGE__SHIFT 0x8 2894f727eceSLe Ma #define SDMA7_PUB_REG_TYPE2__SDMA7_POWER_CNTL_IDLE__SHIFT 0x9 2904f727eceSLe Ma #define SDMA7_PUB_REG_TYPE2__SDMA7_RELAX_ORDERING_LUT__SHIFT 0xa 2914f727eceSLe Ma #define SDMA7_PUB_REG_TYPE2__SDMA7_CHICKEN_BITS_2__SHIFT 0xb 2924f727eceSLe Ma #define SDMA7_PUB_REG_TYPE2__SDMA7_STATUS3_REG__SHIFT 0xc 2934f727eceSLe Ma #define SDMA7_PUB_REG_TYPE2__SDMA7_PHYSICAL_ADDR_LO__SHIFT 0xd 2944f727eceSLe Ma #define SDMA7_PUB_REG_TYPE2__SDMA7_PHYSICAL_ADDR_HI__SHIFT 0xe 2954f727eceSLe Ma #define SDMA7_PUB_REG_TYPE2__SDMA7_PHASE2_QUANTUM__SHIFT 0xf 2964f727eceSLe Ma #define SDMA7_PUB_REG_TYPE2__SDMA7_ERROR_LOG__SHIFT 0x10 2974f727eceSLe Ma #define SDMA7_PUB_REG_TYPE2__SDMA7_PUB_DUMMY_REG0__SHIFT 0x11 2984f727eceSLe Ma #define SDMA7_PUB_REG_TYPE2__SDMA7_PUB_DUMMY_REG1__SHIFT 0x12 2994f727eceSLe Ma #define SDMA7_PUB_REG_TYPE2__SDMA7_PUB_DUMMY_REG2__SHIFT 0x13 3004f727eceSLe Ma #define SDMA7_PUB_REG_TYPE2__SDMA7_PUB_DUMMY_REG3__SHIFT 0x14 3014f727eceSLe Ma #define SDMA7_PUB_REG_TYPE2__SDMA7_F32_COUNTER__SHIFT 0x15 3024f727eceSLe Ma #define SDMA7_PUB_REG_TYPE2__SDMA7_UNBREAKABLE__SHIFT 0x16 3034f727eceSLe Ma #define SDMA7_PUB_REG_TYPE2__SDMA7_PERFMON_CNTL__SHIFT 0x17 3044f727eceSLe Ma #define SDMA7_PUB_REG_TYPE2__SDMA7_PERFCOUNTER0_RESULT__SHIFT 0x18 3054f727eceSLe Ma #define SDMA7_PUB_REG_TYPE2__SDMA7_PERFCOUNTER1_RESULT__SHIFT 0x19 3064f727eceSLe Ma #define SDMA7_PUB_REG_TYPE2__SDMA7_PERFCOUNTER_TAG_DELAY_RANGE__SHIFT 0x1a 3074f727eceSLe Ma #define SDMA7_PUB_REG_TYPE2__SDMA7_CRD_CNTL__SHIFT 0x1b 3084f727eceSLe Ma #define SDMA7_PUB_REG_TYPE2__RESERVED28__SHIFT 0x1c 3094f727eceSLe Ma #define SDMA7_PUB_REG_TYPE2__SDMA7_GPU_IOV_VIOLATION_LOG__SHIFT 0x1d 3104f727eceSLe Ma #define SDMA7_PUB_REG_TYPE2__SDMA7_ULV_CNTL__SHIFT 0x1e 3114f727eceSLe Ma #define SDMA7_PUB_REG_TYPE2__RESERVED__SHIFT 0x1f 3124f727eceSLe Ma #define SDMA7_PUB_REG_TYPE2__SDMA7_UTCL1_INV0_MASK 0x00000001L 3134f727eceSLe Ma #define SDMA7_PUB_REG_TYPE2__SDMA7_UTCL1_INV1_MASK 0x00000002L 3144f727eceSLe Ma #define SDMA7_PUB_REG_TYPE2__SDMA7_UTCL1_INV2_MASK 0x00000004L 3154f727eceSLe Ma #define SDMA7_PUB_REG_TYPE2__SDMA7_UTCL1_RD_XNACK0_MASK 0x00000008L 3164f727eceSLe Ma #define SDMA7_PUB_REG_TYPE2__SDMA7_UTCL1_RD_XNACK1_MASK 0x00000010L 3174f727eceSLe Ma #define SDMA7_PUB_REG_TYPE2__SDMA7_UTCL1_WR_XNACK0_MASK 0x00000020L 3184f727eceSLe Ma #define SDMA7_PUB_REG_TYPE2__SDMA7_UTCL1_WR_XNACK1_MASK 0x00000040L 3194f727eceSLe Ma #define SDMA7_PUB_REG_TYPE2__SDMA7_UTCL1_TIMEOUT_MASK 0x00000080L 3204f727eceSLe Ma #define SDMA7_PUB_REG_TYPE2__SDMA7_UTCL1_PAGE_MASK 0x00000100L 3214f727eceSLe Ma #define SDMA7_PUB_REG_TYPE2__SDMA7_POWER_CNTL_IDLE_MASK 0x00000200L 3224f727eceSLe Ma #define SDMA7_PUB_REG_TYPE2__SDMA7_RELAX_ORDERING_LUT_MASK 0x00000400L 3234f727eceSLe Ma #define SDMA7_PUB_REG_TYPE2__SDMA7_CHICKEN_BITS_2_MASK 0x00000800L 3244f727eceSLe Ma #define SDMA7_PUB_REG_TYPE2__SDMA7_STATUS3_REG_MASK 0x00001000L 3254f727eceSLe Ma #define SDMA7_PUB_REG_TYPE2__SDMA7_PHYSICAL_ADDR_LO_MASK 0x00002000L 3264f727eceSLe Ma #define SDMA7_PUB_REG_TYPE2__SDMA7_PHYSICAL_ADDR_HI_MASK 0x00004000L 3274f727eceSLe Ma #define SDMA7_PUB_REG_TYPE2__SDMA7_PHASE2_QUANTUM_MASK 0x00008000L 3284f727eceSLe Ma #define SDMA7_PUB_REG_TYPE2__SDMA7_ERROR_LOG_MASK 0x00010000L 3294f727eceSLe Ma #define SDMA7_PUB_REG_TYPE2__SDMA7_PUB_DUMMY_REG0_MASK 0x00020000L 3304f727eceSLe Ma #define SDMA7_PUB_REG_TYPE2__SDMA7_PUB_DUMMY_REG1_MASK 0x00040000L 3314f727eceSLe Ma #define SDMA7_PUB_REG_TYPE2__SDMA7_PUB_DUMMY_REG2_MASK 0x00080000L 3324f727eceSLe Ma #define SDMA7_PUB_REG_TYPE2__SDMA7_PUB_DUMMY_REG3_MASK 0x00100000L 3334f727eceSLe Ma #define SDMA7_PUB_REG_TYPE2__SDMA7_F32_COUNTER_MASK 0x00200000L 3344f727eceSLe Ma #define SDMA7_PUB_REG_TYPE2__SDMA7_UNBREAKABLE_MASK 0x00400000L 3354f727eceSLe Ma #define SDMA7_PUB_REG_TYPE2__SDMA7_PERFMON_CNTL_MASK 0x00800000L 3364f727eceSLe Ma #define SDMA7_PUB_REG_TYPE2__SDMA7_PERFCOUNTER0_RESULT_MASK 0x01000000L 3374f727eceSLe Ma #define SDMA7_PUB_REG_TYPE2__SDMA7_PERFCOUNTER1_RESULT_MASK 0x02000000L 3384f727eceSLe Ma #define SDMA7_PUB_REG_TYPE2__SDMA7_PERFCOUNTER_TAG_DELAY_RANGE_MASK 0x04000000L 3394f727eceSLe Ma #define SDMA7_PUB_REG_TYPE2__SDMA7_CRD_CNTL_MASK 0x08000000L 3404f727eceSLe Ma #define SDMA7_PUB_REG_TYPE2__RESERVED28_MASK 0x10000000L 3414f727eceSLe Ma #define SDMA7_PUB_REG_TYPE2__SDMA7_GPU_IOV_VIOLATION_LOG_MASK 0x20000000L 3424f727eceSLe Ma #define SDMA7_PUB_REG_TYPE2__SDMA7_ULV_CNTL_MASK 0x40000000L 3434f727eceSLe Ma #define SDMA7_PUB_REG_TYPE2__RESERVED_MASK 0x80000000L 3444f727eceSLe Ma //SDMA7_PUB_REG_TYPE3 3454f727eceSLe Ma #define SDMA7_PUB_REG_TYPE3__SDMA7_EA_DBIT_ADDR_DATA__SHIFT 0x0 3464f727eceSLe Ma #define SDMA7_PUB_REG_TYPE3__SDMA7_EA_DBIT_ADDR_INDEX__SHIFT 0x1 3474f727eceSLe Ma #define SDMA7_PUB_REG_TYPE3__SDMA7_GPU_IOV_VIOLATION_LOG2__SHIFT 0x2 3484f727eceSLe Ma #define SDMA7_PUB_REG_TYPE3__RESERVED__SHIFT 0x3 3494f727eceSLe Ma #define SDMA7_PUB_REG_TYPE3__SDMA7_EA_DBIT_ADDR_DATA_MASK 0x00000001L 3504f727eceSLe Ma #define SDMA7_PUB_REG_TYPE3__SDMA7_EA_DBIT_ADDR_INDEX_MASK 0x00000002L 3514f727eceSLe Ma #define SDMA7_PUB_REG_TYPE3__SDMA7_GPU_IOV_VIOLATION_LOG2_MASK 0x00000004L 3524f727eceSLe Ma #define SDMA7_PUB_REG_TYPE3__RESERVED_MASK 0xFFFFFFF8L 3534f727eceSLe Ma //SDMA7_MMHUB_CNTL 3544f727eceSLe Ma #define SDMA7_MMHUB_CNTL__UNIT_ID__SHIFT 0x0 3554f727eceSLe Ma #define SDMA7_MMHUB_CNTL__UNIT_ID_MASK 0x0000003FL 3564f727eceSLe Ma //SDMA7_CONTEXT_GROUP_BOUNDARY 3574f727eceSLe Ma #define SDMA7_CONTEXT_GROUP_BOUNDARY__RESERVED__SHIFT 0x0 3584f727eceSLe Ma #define SDMA7_CONTEXT_GROUP_BOUNDARY__RESERVED_MASK 0xFFFFFFFFL 3594f727eceSLe Ma //SDMA7_POWER_CNTL 3604f727eceSLe Ma #define SDMA7_POWER_CNTL__MEM_POWER_OVERRIDE__SHIFT 0x8 3614f727eceSLe Ma #define SDMA7_POWER_CNTL__MEM_POWER_LS_EN__SHIFT 0x9 3624f727eceSLe Ma #define SDMA7_POWER_CNTL__MEM_POWER_DS_EN__SHIFT 0xa 3634f727eceSLe Ma #define SDMA7_POWER_CNTL__MEM_POWER_SD_EN__SHIFT 0xb 3644f727eceSLe Ma #define SDMA7_POWER_CNTL__MEM_POWER_DELAY__SHIFT 0xc 3654f727eceSLe Ma #define SDMA7_POWER_CNTL__MEM_POWER_OVERRIDE_MASK 0x00000100L 3664f727eceSLe Ma #define SDMA7_POWER_CNTL__MEM_POWER_LS_EN_MASK 0x00000200L 3674f727eceSLe Ma #define SDMA7_POWER_CNTL__MEM_POWER_DS_EN_MASK 0x00000400L 3684f727eceSLe Ma #define SDMA7_POWER_CNTL__MEM_POWER_SD_EN_MASK 0x00000800L 3694f727eceSLe Ma #define SDMA7_POWER_CNTL__MEM_POWER_DELAY_MASK 0x003FF000L 3704f727eceSLe Ma //SDMA7_CLK_CTRL 3714f727eceSLe Ma #define SDMA7_CLK_CTRL__ON_DELAY__SHIFT 0x0 3724f727eceSLe Ma #define SDMA7_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 3734f727eceSLe Ma #define SDMA7_CLK_CTRL__RESERVED__SHIFT 0xc 3744f727eceSLe Ma #define SDMA7_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18 3754f727eceSLe Ma #define SDMA7_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19 3764f727eceSLe Ma #define SDMA7_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a 3774f727eceSLe Ma #define SDMA7_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b 3784f727eceSLe Ma #define SDMA7_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c 3794f727eceSLe Ma #define SDMA7_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d 3804f727eceSLe Ma #define SDMA7_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e 3814f727eceSLe Ma #define SDMA7_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f 3824f727eceSLe Ma #define SDMA7_CLK_CTRL__ON_DELAY_MASK 0x0000000FL 3834f727eceSLe Ma #define SDMA7_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L 3844f727eceSLe Ma #define SDMA7_CLK_CTRL__RESERVED_MASK 0x00FFF000L 3854f727eceSLe Ma #define SDMA7_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L 3864f727eceSLe Ma #define SDMA7_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L 3874f727eceSLe Ma #define SDMA7_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L 3884f727eceSLe Ma #define SDMA7_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L 3894f727eceSLe Ma #define SDMA7_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L 3904f727eceSLe Ma #define SDMA7_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L 3914f727eceSLe Ma #define SDMA7_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L 3924f727eceSLe Ma #define SDMA7_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L 3934f727eceSLe Ma //SDMA7_CNTL 3944f727eceSLe Ma #define SDMA7_CNTL__TRAP_ENABLE__SHIFT 0x0 3954f727eceSLe Ma #define SDMA7_CNTL__UTC_L1_ENABLE__SHIFT 0x1 3964f727eceSLe Ma #define SDMA7_CNTL__SEM_WAIT_INT_ENABLE__SHIFT 0x2 3974f727eceSLe Ma #define SDMA7_CNTL__DATA_SWAP_ENABLE__SHIFT 0x3 3984f727eceSLe Ma #define SDMA7_CNTL__FENCE_SWAP_ENABLE__SHIFT 0x4 3994f727eceSLe Ma #define SDMA7_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x5 4004f727eceSLe Ma #define SDMA7_CNTL__MIDCMD_WORLDSWITCH_ENABLE__SHIFT 0x11 4014f727eceSLe Ma #define SDMA7_CNTL__AUTO_CTXSW_ENABLE__SHIFT 0x12 4024f727eceSLe Ma #define SDMA7_CNTL__CTXEMPTY_INT_ENABLE__SHIFT 0x1c 4034f727eceSLe Ma #define SDMA7_CNTL__FROZEN_INT_ENABLE__SHIFT 0x1d 4044f727eceSLe Ma #define SDMA7_CNTL__IB_PREEMPT_INT_ENABLE__SHIFT 0x1e 4054f727eceSLe Ma #define SDMA7_CNTL__TRAP_ENABLE_MASK 0x00000001L 4064f727eceSLe Ma #define SDMA7_CNTL__UTC_L1_ENABLE_MASK 0x00000002L 4074f727eceSLe Ma #define SDMA7_CNTL__SEM_WAIT_INT_ENABLE_MASK 0x00000004L 4084f727eceSLe Ma #define SDMA7_CNTL__DATA_SWAP_ENABLE_MASK 0x00000008L 4094f727eceSLe Ma #define SDMA7_CNTL__FENCE_SWAP_ENABLE_MASK 0x00000010L 4104f727eceSLe Ma #define SDMA7_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00000020L 4114f727eceSLe Ma #define SDMA7_CNTL__MIDCMD_WORLDSWITCH_ENABLE_MASK 0x00020000L 4124f727eceSLe Ma #define SDMA7_CNTL__AUTO_CTXSW_ENABLE_MASK 0x00040000L 4134f727eceSLe Ma #define SDMA7_CNTL__CTXEMPTY_INT_ENABLE_MASK 0x10000000L 4144f727eceSLe Ma #define SDMA7_CNTL__FROZEN_INT_ENABLE_MASK 0x20000000L 4154f727eceSLe Ma #define SDMA7_CNTL__IB_PREEMPT_INT_ENABLE_MASK 0x40000000L 4164f727eceSLe Ma //SDMA7_CHICKEN_BITS 4174f727eceSLe Ma #define SDMA7_CHICKEN_BITS__COPY_EFFICIENCY_ENABLE__SHIFT 0x0 4184f727eceSLe Ma #define SDMA7_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE__SHIFT 0x1 4194f727eceSLe Ma #define SDMA7_CHICKEN_BITS__STALL_ON_NO_FREE_DATA_BUFFER_ENABLE__SHIFT 0x2 4204f727eceSLe Ma #define SDMA7_CHICKEN_BITS__WRITE_BURST_LENGTH__SHIFT 0x8 4214f727eceSLe Ma #define SDMA7_CHICKEN_BITS__WRITE_BURST_WAIT_CYCLE__SHIFT 0xa 4224f727eceSLe Ma #define SDMA7_CHICKEN_BITS__COPY_OVERLAP_ENABLE__SHIFT 0x10 4234f727eceSLe Ma #define SDMA7_CHICKEN_BITS__RAW_CHECK_ENABLE__SHIFT 0x11 4244f727eceSLe Ma #define SDMA7_CHICKEN_BITS__SRBM_POLL_RETRYING__SHIFT 0x14 4254f727eceSLe Ma #define SDMA7_CHICKEN_BITS__CG_STATUS_OUTPUT__SHIFT 0x17 4264f727eceSLe Ma #define SDMA7_CHICKEN_BITS__TIME_BASED_QOS__SHIFT 0x19 4274f727eceSLe Ma #define SDMA7_CHICKEN_BITS__CE_AFIFO_WATERMARK__SHIFT 0x1a 4284f727eceSLe Ma #define SDMA7_CHICKEN_BITS__CE_DFIFO_WATERMARK__SHIFT 0x1c 4294f727eceSLe Ma #define SDMA7_CHICKEN_BITS__CE_LFIFO_WATERMARK__SHIFT 0x1e 4304f727eceSLe Ma #define SDMA7_CHICKEN_BITS__COPY_EFFICIENCY_ENABLE_MASK 0x00000001L 4314f727eceSLe Ma #define SDMA7_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE_MASK 0x00000002L 4324f727eceSLe Ma #define SDMA7_CHICKEN_BITS__STALL_ON_NO_FREE_DATA_BUFFER_ENABLE_MASK 0x00000004L 4334f727eceSLe Ma #define SDMA7_CHICKEN_BITS__WRITE_BURST_LENGTH_MASK 0x00000300L 4344f727eceSLe Ma #define SDMA7_CHICKEN_BITS__WRITE_BURST_WAIT_CYCLE_MASK 0x00001C00L 4354f727eceSLe Ma #define SDMA7_CHICKEN_BITS__COPY_OVERLAP_ENABLE_MASK 0x00010000L 4364f727eceSLe Ma #define SDMA7_CHICKEN_BITS__RAW_CHECK_ENABLE_MASK 0x00020000L 4374f727eceSLe Ma #define SDMA7_CHICKEN_BITS__SRBM_POLL_RETRYING_MASK 0x00100000L 4384f727eceSLe Ma #define SDMA7_CHICKEN_BITS__CG_STATUS_OUTPUT_MASK 0x00800000L 4394f727eceSLe Ma #define SDMA7_CHICKEN_BITS__TIME_BASED_QOS_MASK 0x02000000L 4404f727eceSLe Ma #define SDMA7_CHICKEN_BITS__CE_AFIFO_WATERMARK_MASK 0x0C000000L 4414f727eceSLe Ma #define SDMA7_CHICKEN_BITS__CE_DFIFO_WATERMARK_MASK 0x30000000L 4424f727eceSLe Ma #define SDMA7_CHICKEN_BITS__CE_LFIFO_WATERMARK_MASK 0xC0000000L 4434f727eceSLe Ma //SDMA7_GB_ADDR_CONFIG 4444f727eceSLe Ma #define SDMA7_GB_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 4454f727eceSLe Ma #define SDMA7_GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x3 4464f727eceSLe Ma #define SDMA7_GB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8 4474f727eceSLe Ma #define SDMA7_GB_ADDR_CONFIG__NUM_BANKS__SHIFT 0xc 4484f727eceSLe Ma #define SDMA7_GB_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0x13 4494f727eceSLe Ma #define SDMA7_GB_ADDR_CONFIG__NUM_PIPES_MASK 0x00000007L 4504f727eceSLe Ma #define SDMA7_GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L 4514f727eceSLe Ma #define SDMA7_GB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x00000700L 4524f727eceSLe Ma #define SDMA7_GB_ADDR_CONFIG__NUM_BANKS_MASK 0x00007000L 4534f727eceSLe Ma #define SDMA7_GB_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x00180000L 4544f727eceSLe Ma //SDMA7_GB_ADDR_CONFIG_READ 4554f727eceSLe Ma #define SDMA7_GB_ADDR_CONFIG_READ__NUM_PIPES__SHIFT 0x0 4564f727eceSLe Ma #define SDMA7_GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE__SHIFT 0x3 4574f727eceSLe Ma #define SDMA7_GB_ADDR_CONFIG_READ__BANK_INTERLEAVE_SIZE__SHIFT 0x8 4584f727eceSLe Ma #define SDMA7_GB_ADDR_CONFIG_READ__NUM_BANKS__SHIFT 0xc 4594f727eceSLe Ma #define SDMA7_GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES__SHIFT 0x13 4604f727eceSLe Ma #define SDMA7_GB_ADDR_CONFIG_READ__NUM_PIPES_MASK 0x00000007L 4614f727eceSLe Ma #define SDMA7_GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L 4624f727eceSLe Ma #define SDMA7_GB_ADDR_CONFIG_READ__BANK_INTERLEAVE_SIZE_MASK 0x00000700L 4634f727eceSLe Ma #define SDMA7_GB_ADDR_CONFIG_READ__NUM_BANKS_MASK 0x00007000L 4644f727eceSLe Ma #define SDMA7_GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES_MASK 0x00180000L 4654f727eceSLe Ma //SDMA7_RB_RPTR_FETCH_HI 4664f727eceSLe Ma #define SDMA7_RB_RPTR_FETCH_HI__OFFSET__SHIFT 0x0 4674f727eceSLe Ma #define SDMA7_RB_RPTR_FETCH_HI__OFFSET_MASK 0xFFFFFFFFL 4684f727eceSLe Ma //SDMA7_SEM_WAIT_FAIL_TIMER_CNTL 4694f727eceSLe Ma #define SDMA7_SEM_WAIT_FAIL_TIMER_CNTL__TIMER__SHIFT 0x0 4704f727eceSLe Ma #define SDMA7_SEM_WAIT_FAIL_TIMER_CNTL__TIMER_MASK 0xFFFFFFFFL 4714f727eceSLe Ma //SDMA7_RB_RPTR_FETCH 4724f727eceSLe Ma #define SDMA7_RB_RPTR_FETCH__OFFSET__SHIFT 0x2 4734f727eceSLe Ma #define SDMA7_RB_RPTR_FETCH__OFFSET_MASK 0xFFFFFFFCL 4744f727eceSLe Ma //SDMA7_IB_OFFSET_FETCH 4754f727eceSLe Ma #define SDMA7_IB_OFFSET_FETCH__OFFSET__SHIFT 0x2 4764f727eceSLe Ma #define SDMA7_IB_OFFSET_FETCH__OFFSET_MASK 0x003FFFFCL 4774f727eceSLe Ma //SDMA7_PROGRAM 4784f727eceSLe Ma #define SDMA7_PROGRAM__STREAM__SHIFT 0x0 4794f727eceSLe Ma #define SDMA7_PROGRAM__STREAM_MASK 0xFFFFFFFFL 4804f727eceSLe Ma //SDMA7_STATUS_REG 4814f727eceSLe Ma #define SDMA7_STATUS_REG__IDLE__SHIFT 0x0 4824f727eceSLe Ma #define SDMA7_STATUS_REG__REG_IDLE__SHIFT 0x1 4834f727eceSLe Ma #define SDMA7_STATUS_REG__RB_EMPTY__SHIFT 0x2 4844f727eceSLe Ma #define SDMA7_STATUS_REG__RB_FULL__SHIFT 0x3 4854f727eceSLe Ma #define SDMA7_STATUS_REG__RB_CMD_IDLE__SHIFT 0x4 4864f727eceSLe Ma #define SDMA7_STATUS_REG__RB_CMD_FULL__SHIFT 0x5 4874f727eceSLe Ma #define SDMA7_STATUS_REG__IB_CMD_IDLE__SHIFT 0x6 4884f727eceSLe Ma #define SDMA7_STATUS_REG__IB_CMD_FULL__SHIFT 0x7 4894f727eceSLe Ma #define SDMA7_STATUS_REG__BLOCK_IDLE__SHIFT 0x8 4904f727eceSLe Ma #define SDMA7_STATUS_REG__INSIDE_IB__SHIFT 0x9 4914f727eceSLe Ma #define SDMA7_STATUS_REG__EX_IDLE__SHIFT 0xa 4924f727eceSLe Ma #define SDMA7_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE__SHIFT 0xb 4934f727eceSLe Ma #define SDMA7_STATUS_REG__PACKET_READY__SHIFT 0xc 4944f727eceSLe Ma #define SDMA7_STATUS_REG__MC_WR_IDLE__SHIFT 0xd 4954f727eceSLe Ma #define SDMA7_STATUS_REG__SRBM_IDLE__SHIFT 0xe 4964f727eceSLe Ma #define SDMA7_STATUS_REG__CONTEXT_EMPTY__SHIFT 0xf 4974f727eceSLe Ma #define SDMA7_STATUS_REG__DELTA_RPTR_FULL__SHIFT 0x10 4984f727eceSLe Ma #define SDMA7_STATUS_REG__RB_MC_RREQ_IDLE__SHIFT 0x11 4994f727eceSLe Ma #define SDMA7_STATUS_REG__IB_MC_RREQ_IDLE__SHIFT 0x12 5004f727eceSLe Ma #define SDMA7_STATUS_REG__MC_RD_IDLE__SHIFT 0x13 5014f727eceSLe Ma #define SDMA7_STATUS_REG__DELTA_RPTR_EMPTY__SHIFT 0x14 5024f727eceSLe Ma #define SDMA7_STATUS_REG__MC_RD_RET_STALL__SHIFT 0x15 5034f727eceSLe Ma #define SDMA7_STATUS_REG__MC_RD_NO_POLL_IDLE__SHIFT 0x16 5044f727eceSLe Ma #define SDMA7_STATUS_REG__PREV_CMD_IDLE__SHIFT 0x19 5054f727eceSLe Ma #define SDMA7_STATUS_REG__SEM_IDLE__SHIFT 0x1a 5064f727eceSLe Ma #define SDMA7_STATUS_REG__SEM_REQ_STALL__SHIFT 0x1b 5074f727eceSLe Ma #define SDMA7_STATUS_REG__SEM_RESP_STATE__SHIFT 0x1c 5084f727eceSLe Ma #define SDMA7_STATUS_REG__INT_IDLE__SHIFT 0x1e 5094f727eceSLe Ma #define SDMA7_STATUS_REG__INT_REQ_STALL__SHIFT 0x1f 5104f727eceSLe Ma #define SDMA7_STATUS_REG__IDLE_MASK 0x00000001L 5114f727eceSLe Ma #define SDMA7_STATUS_REG__REG_IDLE_MASK 0x00000002L 5124f727eceSLe Ma #define SDMA7_STATUS_REG__RB_EMPTY_MASK 0x00000004L 5134f727eceSLe Ma #define SDMA7_STATUS_REG__RB_FULL_MASK 0x00000008L 5144f727eceSLe Ma #define SDMA7_STATUS_REG__RB_CMD_IDLE_MASK 0x00000010L 5154f727eceSLe Ma #define SDMA7_STATUS_REG__RB_CMD_FULL_MASK 0x00000020L 5164f727eceSLe Ma #define SDMA7_STATUS_REG__IB_CMD_IDLE_MASK 0x00000040L 5174f727eceSLe Ma #define SDMA7_STATUS_REG__IB_CMD_FULL_MASK 0x00000080L 5184f727eceSLe Ma #define SDMA7_STATUS_REG__BLOCK_IDLE_MASK 0x00000100L 5194f727eceSLe Ma #define SDMA7_STATUS_REG__INSIDE_IB_MASK 0x00000200L 5204f727eceSLe Ma #define SDMA7_STATUS_REG__EX_IDLE_MASK 0x00000400L 5214f727eceSLe Ma #define SDMA7_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE_MASK 0x00000800L 5224f727eceSLe Ma #define SDMA7_STATUS_REG__PACKET_READY_MASK 0x00001000L 5234f727eceSLe Ma #define SDMA7_STATUS_REG__MC_WR_IDLE_MASK 0x00002000L 5244f727eceSLe Ma #define SDMA7_STATUS_REG__SRBM_IDLE_MASK 0x00004000L 5254f727eceSLe Ma #define SDMA7_STATUS_REG__CONTEXT_EMPTY_MASK 0x00008000L 5264f727eceSLe Ma #define SDMA7_STATUS_REG__DELTA_RPTR_FULL_MASK 0x00010000L 5274f727eceSLe Ma #define SDMA7_STATUS_REG__RB_MC_RREQ_IDLE_MASK 0x00020000L 5284f727eceSLe Ma #define SDMA7_STATUS_REG__IB_MC_RREQ_IDLE_MASK 0x00040000L 5294f727eceSLe Ma #define SDMA7_STATUS_REG__MC_RD_IDLE_MASK 0x00080000L 5304f727eceSLe Ma #define SDMA7_STATUS_REG__DELTA_RPTR_EMPTY_MASK 0x00100000L 5314f727eceSLe Ma #define SDMA7_STATUS_REG__MC_RD_RET_STALL_MASK 0x00200000L 5324f727eceSLe Ma #define SDMA7_STATUS_REG__MC_RD_NO_POLL_IDLE_MASK 0x00400000L 5334f727eceSLe Ma #define SDMA7_STATUS_REG__PREV_CMD_IDLE_MASK 0x02000000L 5344f727eceSLe Ma #define SDMA7_STATUS_REG__SEM_IDLE_MASK 0x04000000L 5354f727eceSLe Ma #define SDMA7_STATUS_REG__SEM_REQ_STALL_MASK 0x08000000L 5364f727eceSLe Ma #define SDMA7_STATUS_REG__SEM_RESP_STATE_MASK 0x30000000L 5374f727eceSLe Ma #define SDMA7_STATUS_REG__INT_IDLE_MASK 0x40000000L 5384f727eceSLe Ma #define SDMA7_STATUS_REG__INT_REQ_STALL_MASK 0x80000000L 5394f727eceSLe Ma //SDMA7_STATUS1_REG 5404f727eceSLe Ma #define SDMA7_STATUS1_REG__CE_WREQ_IDLE__SHIFT 0x0 5414f727eceSLe Ma #define SDMA7_STATUS1_REG__CE_WR_IDLE__SHIFT 0x1 5424f727eceSLe Ma #define SDMA7_STATUS1_REG__CE_SPLIT_IDLE__SHIFT 0x2 5434f727eceSLe Ma #define SDMA7_STATUS1_REG__CE_RREQ_IDLE__SHIFT 0x3 5444f727eceSLe Ma #define SDMA7_STATUS1_REG__CE_OUT_IDLE__SHIFT 0x4 5454f727eceSLe Ma #define SDMA7_STATUS1_REG__CE_IN_IDLE__SHIFT 0x5 5464f727eceSLe Ma #define SDMA7_STATUS1_REG__CE_DST_IDLE__SHIFT 0x6 5474f727eceSLe Ma #define SDMA7_STATUS1_REG__CE_CMD_IDLE__SHIFT 0x9 5484f727eceSLe Ma #define SDMA7_STATUS1_REG__CE_AFIFO_FULL__SHIFT 0xa 5494f727eceSLe Ma #define SDMA7_STATUS1_REG__CE_INFO_FULL__SHIFT 0xd 5504f727eceSLe Ma #define SDMA7_STATUS1_REG__CE_INFO1_FULL__SHIFT 0xe 5514f727eceSLe Ma #define SDMA7_STATUS1_REG__EX_START__SHIFT 0xf 5524f727eceSLe Ma #define SDMA7_STATUS1_REG__CE_RD_STALL__SHIFT 0x11 5534f727eceSLe Ma #define SDMA7_STATUS1_REG__CE_WR_STALL__SHIFT 0x12 5544f727eceSLe Ma #define SDMA7_STATUS1_REG__CE_WREQ_IDLE_MASK 0x00000001L 5554f727eceSLe Ma #define SDMA7_STATUS1_REG__CE_WR_IDLE_MASK 0x00000002L 5564f727eceSLe Ma #define SDMA7_STATUS1_REG__CE_SPLIT_IDLE_MASK 0x00000004L 5574f727eceSLe Ma #define SDMA7_STATUS1_REG__CE_RREQ_IDLE_MASK 0x00000008L 5584f727eceSLe Ma #define SDMA7_STATUS1_REG__CE_OUT_IDLE_MASK 0x00000010L 5594f727eceSLe Ma #define SDMA7_STATUS1_REG__CE_IN_IDLE_MASK 0x00000020L 5604f727eceSLe Ma #define SDMA7_STATUS1_REG__CE_DST_IDLE_MASK 0x00000040L 5614f727eceSLe Ma #define SDMA7_STATUS1_REG__CE_CMD_IDLE_MASK 0x00000200L 5624f727eceSLe Ma #define SDMA7_STATUS1_REG__CE_AFIFO_FULL_MASK 0x00000400L 5634f727eceSLe Ma #define SDMA7_STATUS1_REG__CE_INFO_FULL_MASK 0x00002000L 5644f727eceSLe Ma #define SDMA7_STATUS1_REG__CE_INFO1_FULL_MASK 0x00004000L 5654f727eceSLe Ma #define SDMA7_STATUS1_REG__EX_START_MASK 0x00008000L 5664f727eceSLe Ma #define SDMA7_STATUS1_REG__CE_RD_STALL_MASK 0x00020000L 5674f727eceSLe Ma #define SDMA7_STATUS1_REG__CE_WR_STALL_MASK 0x00040000L 5684f727eceSLe Ma //SDMA7_RD_BURST_CNTL 5694f727eceSLe Ma #define SDMA7_RD_BURST_CNTL__RD_BURST__SHIFT 0x0 5704f727eceSLe Ma #define SDMA7_RD_BURST_CNTL__CMD_BUFFER_RD_BURST__SHIFT 0x2 5714f727eceSLe Ma #define SDMA7_RD_BURST_CNTL__RD_BURST_MASK 0x00000003L 5724f727eceSLe Ma #define SDMA7_RD_BURST_CNTL__CMD_BUFFER_RD_BURST_MASK 0x0000000CL 5734f727eceSLe Ma //SDMA7_HBM_PAGE_CONFIG 5744f727eceSLe Ma #define SDMA7_HBM_PAGE_CONFIG__PAGE_SIZE_EXPONENT__SHIFT 0x0 5754f727eceSLe Ma #define SDMA7_HBM_PAGE_CONFIG__PAGE_SIZE_EXPONENT_MASK 0x00000001L 5764f727eceSLe Ma //SDMA7_UCODE_CHECKSUM 5774f727eceSLe Ma #define SDMA7_UCODE_CHECKSUM__DATA__SHIFT 0x0 5784f727eceSLe Ma #define SDMA7_UCODE_CHECKSUM__DATA_MASK 0xFFFFFFFFL 5794f727eceSLe Ma //SDMA7_F32_CNTL 5804f727eceSLe Ma #define SDMA7_F32_CNTL__HALT__SHIFT 0x0 5814f727eceSLe Ma #define SDMA7_F32_CNTL__STEP__SHIFT 0x1 5824f727eceSLe Ma #define SDMA7_F32_CNTL__HALT_MASK 0x00000001L 5834f727eceSLe Ma #define SDMA7_F32_CNTL__STEP_MASK 0x00000002L 5844f727eceSLe Ma //SDMA7_FREEZE 5854f727eceSLe Ma #define SDMA7_FREEZE__PREEMPT__SHIFT 0x0 5864f727eceSLe Ma #define SDMA7_FREEZE__FREEZE__SHIFT 0x4 5874f727eceSLe Ma #define SDMA7_FREEZE__FROZEN__SHIFT 0x5 5884f727eceSLe Ma #define SDMA7_FREEZE__F32_FREEZE__SHIFT 0x6 5894f727eceSLe Ma #define SDMA7_FREEZE__PREEMPT_MASK 0x00000001L 5904f727eceSLe Ma #define SDMA7_FREEZE__FREEZE_MASK 0x00000010L 5914f727eceSLe Ma #define SDMA7_FREEZE__FROZEN_MASK 0x00000020L 5924f727eceSLe Ma #define SDMA7_FREEZE__F32_FREEZE_MASK 0x00000040L 5934f727eceSLe Ma //SDMA7_PHASE0_QUANTUM 5944f727eceSLe Ma #define SDMA7_PHASE0_QUANTUM__UNIT__SHIFT 0x0 5954f727eceSLe Ma #define SDMA7_PHASE0_QUANTUM__VALUE__SHIFT 0x8 5964f727eceSLe Ma #define SDMA7_PHASE0_QUANTUM__PREFER__SHIFT 0x1e 5974f727eceSLe Ma #define SDMA7_PHASE0_QUANTUM__UNIT_MASK 0x0000000FL 5984f727eceSLe Ma #define SDMA7_PHASE0_QUANTUM__VALUE_MASK 0x00FFFF00L 5994f727eceSLe Ma #define SDMA7_PHASE0_QUANTUM__PREFER_MASK 0x40000000L 6004f727eceSLe Ma //SDMA7_PHASE1_QUANTUM 6014f727eceSLe Ma #define SDMA7_PHASE1_QUANTUM__UNIT__SHIFT 0x0 6024f727eceSLe Ma #define SDMA7_PHASE1_QUANTUM__VALUE__SHIFT 0x8 6034f727eceSLe Ma #define SDMA7_PHASE1_QUANTUM__PREFER__SHIFT 0x1e 6044f727eceSLe Ma #define SDMA7_PHASE1_QUANTUM__UNIT_MASK 0x0000000FL 6054f727eceSLe Ma #define SDMA7_PHASE1_QUANTUM__VALUE_MASK 0x00FFFF00L 6064f727eceSLe Ma #define SDMA7_PHASE1_QUANTUM__PREFER_MASK 0x40000000L 6074f727eceSLe Ma //SDMA7_EDC_CONFIG 6084f727eceSLe Ma #define SDMA7_EDC_CONFIG__DIS_EDC__SHIFT 0x1 6094f727eceSLe Ma #define SDMA7_EDC_CONFIG__ECC_INT_ENABLE__SHIFT 0x2 6104f727eceSLe Ma #define SDMA7_EDC_CONFIG__DIS_EDC_MASK 0x00000002L 6114f727eceSLe Ma #define SDMA7_EDC_CONFIG__ECC_INT_ENABLE_MASK 0x00000004L 6124f727eceSLe Ma //SDMA7_BA_THRESHOLD 6134f727eceSLe Ma #define SDMA7_BA_THRESHOLD__READ_THRES__SHIFT 0x0 6144f727eceSLe Ma #define SDMA7_BA_THRESHOLD__WRITE_THRES__SHIFT 0x10 6154f727eceSLe Ma #define SDMA7_BA_THRESHOLD__READ_THRES_MASK 0x000003FFL 6164f727eceSLe Ma #define SDMA7_BA_THRESHOLD__WRITE_THRES_MASK 0x03FF0000L 6174f727eceSLe Ma //SDMA7_ID 6184f727eceSLe Ma #define SDMA7_ID__DEVICE_ID__SHIFT 0x0 6194f727eceSLe Ma #define SDMA7_ID__DEVICE_ID_MASK 0x000000FFL 6204f727eceSLe Ma //SDMA7_VERSION 6214f727eceSLe Ma #define SDMA7_VERSION__MINVER__SHIFT 0x0 6224f727eceSLe Ma #define SDMA7_VERSION__MAJVER__SHIFT 0x8 6234f727eceSLe Ma #define SDMA7_VERSION__REV__SHIFT 0x10 6244f727eceSLe Ma #define SDMA7_VERSION__MINVER_MASK 0x0000007FL 6254f727eceSLe Ma #define SDMA7_VERSION__MAJVER_MASK 0x00007F00L 6264f727eceSLe Ma #define SDMA7_VERSION__REV_MASK 0x003F0000L 6274f727eceSLe Ma //SDMA7_EDC_COUNTER 6284f727eceSLe Ma #define SDMA7_EDC_COUNTER__SDMA_UCODE_BUF_SED__SHIFT 0x0 6294f727eceSLe Ma #define SDMA7_EDC_COUNTER__SDMA_RB_CMD_BUF_SED__SHIFT 0x2 6304f727eceSLe Ma #define SDMA7_EDC_COUNTER__SDMA_IB_CMD_BUF_SED__SHIFT 0x3 6314f727eceSLe Ma #define SDMA7_EDC_COUNTER__SDMA_UTCL1_RD_FIFO_SED__SHIFT 0x4 6324f727eceSLe Ma #define SDMA7_EDC_COUNTER__SDMA_UTCL1_RDBST_FIFO_SED__SHIFT 0x5 6334f727eceSLe Ma #define SDMA7_EDC_COUNTER__SDMA_DATA_LUT_FIFO_SED__SHIFT 0x6 6344f727eceSLe Ma #define SDMA7_EDC_COUNTER__SDMA_MBANK_DATA_BUF0_SED__SHIFT 0x7 6354f727eceSLe Ma #define SDMA7_EDC_COUNTER__SDMA_MBANK_DATA_BUF1_SED__SHIFT 0x8 6364f727eceSLe Ma #define SDMA7_EDC_COUNTER__SDMA_MBANK_DATA_BUF2_SED__SHIFT 0x9 6374f727eceSLe Ma #define SDMA7_EDC_COUNTER__SDMA_MBANK_DATA_BUF3_SED__SHIFT 0xa 6384f727eceSLe Ma #define SDMA7_EDC_COUNTER__SDMA_MBANK_DATA_BUF4_SED__SHIFT 0xb 6394f727eceSLe Ma #define SDMA7_EDC_COUNTER__SDMA_MBANK_DATA_BUF5_SED__SHIFT 0xc 6404f727eceSLe Ma #define SDMA7_EDC_COUNTER__SDMA_MBANK_DATA_BUF6_SED__SHIFT 0xd 6414f727eceSLe Ma #define SDMA7_EDC_COUNTER__SDMA_MBANK_DATA_BUF7_SED__SHIFT 0xe 6424f727eceSLe Ma #define SDMA7_EDC_COUNTER__SDMA_MBANK_DATA_BUF8_SED__SHIFT 0xf 6434f727eceSLe Ma #define SDMA7_EDC_COUNTER__SDMA_MBANK_DATA_BUF9_SED__SHIFT 0x10 6444f727eceSLe Ma #define SDMA7_EDC_COUNTER__SDMA_MBANK_DATA_BUF10_SED__SHIFT 0x11 6454f727eceSLe Ma #define SDMA7_EDC_COUNTER__SDMA_MBANK_DATA_BUF11_SED__SHIFT 0x12 6464f727eceSLe Ma #define SDMA7_EDC_COUNTER__SDMA_MBANK_DATA_BUF12_SED__SHIFT 0x13 6474f727eceSLe Ma #define SDMA7_EDC_COUNTER__SDMA_MBANK_DATA_BUF13_SED__SHIFT 0x14 6484f727eceSLe Ma #define SDMA7_EDC_COUNTER__SDMA_MBANK_DATA_BUF14_SED__SHIFT 0x15 6494f727eceSLe Ma #define SDMA7_EDC_COUNTER__SDMA_MBANK_DATA_BUF15_SED__SHIFT 0x16 6504f727eceSLe Ma #define SDMA7_EDC_COUNTER__SDMA_SPLIT_DAT_BUF_SED__SHIFT 0x17 6514f727eceSLe Ma #define SDMA7_EDC_COUNTER__SDMA_MC_WR_ADDR_FIFO_SED__SHIFT 0x18 6524f727eceSLe Ma #define SDMA7_EDC_COUNTER__SDMA_UCODE_BUF_SED_MASK 0x00000001L 6534f727eceSLe Ma #define SDMA7_EDC_COUNTER__SDMA_RB_CMD_BUF_SED_MASK 0x00000004L 6544f727eceSLe Ma #define SDMA7_EDC_COUNTER__SDMA_IB_CMD_BUF_SED_MASK 0x00000008L 6554f727eceSLe Ma #define SDMA7_EDC_COUNTER__SDMA_UTCL1_RD_FIFO_SED_MASK 0x00000010L 6564f727eceSLe Ma #define SDMA7_EDC_COUNTER__SDMA_UTCL1_RDBST_FIFO_SED_MASK 0x00000020L 6574f727eceSLe Ma #define SDMA7_EDC_COUNTER__SDMA_DATA_LUT_FIFO_SED_MASK 0x00000040L 6584f727eceSLe Ma #define SDMA7_EDC_COUNTER__SDMA_MBANK_DATA_BUF0_SED_MASK 0x00000080L 6594f727eceSLe Ma #define SDMA7_EDC_COUNTER__SDMA_MBANK_DATA_BUF1_SED_MASK 0x00000100L 6604f727eceSLe Ma #define SDMA7_EDC_COUNTER__SDMA_MBANK_DATA_BUF2_SED_MASK 0x00000200L 6614f727eceSLe Ma #define SDMA7_EDC_COUNTER__SDMA_MBANK_DATA_BUF3_SED_MASK 0x00000400L 6624f727eceSLe Ma #define SDMA7_EDC_COUNTER__SDMA_MBANK_DATA_BUF4_SED_MASK 0x00000800L 6634f727eceSLe Ma #define SDMA7_EDC_COUNTER__SDMA_MBANK_DATA_BUF5_SED_MASK 0x00001000L 6644f727eceSLe Ma #define SDMA7_EDC_COUNTER__SDMA_MBANK_DATA_BUF6_SED_MASK 0x00002000L 6654f727eceSLe Ma #define SDMA7_EDC_COUNTER__SDMA_MBANK_DATA_BUF7_SED_MASK 0x00004000L 6664f727eceSLe Ma #define SDMA7_EDC_COUNTER__SDMA_MBANK_DATA_BUF8_SED_MASK 0x00008000L 6674f727eceSLe Ma #define SDMA7_EDC_COUNTER__SDMA_MBANK_DATA_BUF9_SED_MASK 0x00010000L 6684f727eceSLe Ma #define SDMA7_EDC_COUNTER__SDMA_MBANK_DATA_BUF10_SED_MASK 0x00020000L 6694f727eceSLe Ma #define SDMA7_EDC_COUNTER__SDMA_MBANK_DATA_BUF11_SED_MASK 0x00040000L 6704f727eceSLe Ma #define SDMA7_EDC_COUNTER__SDMA_MBANK_DATA_BUF12_SED_MASK 0x00080000L 6714f727eceSLe Ma #define SDMA7_EDC_COUNTER__SDMA_MBANK_DATA_BUF13_SED_MASK 0x00100000L 6724f727eceSLe Ma #define SDMA7_EDC_COUNTER__SDMA_MBANK_DATA_BUF14_SED_MASK 0x00200000L 6734f727eceSLe Ma #define SDMA7_EDC_COUNTER__SDMA_MBANK_DATA_BUF15_SED_MASK 0x00400000L 6744f727eceSLe Ma #define SDMA7_EDC_COUNTER__SDMA_SPLIT_DAT_BUF_SED_MASK 0x00800000L 6754f727eceSLe Ma #define SDMA7_EDC_COUNTER__SDMA_MC_WR_ADDR_FIFO_SED_MASK 0x01000000L 6764f727eceSLe Ma //SDMA7_EDC_COUNTER_CLEAR 6774f727eceSLe Ma #define SDMA7_EDC_COUNTER_CLEAR__DUMMY__SHIFT 0x0 6784f727eceSLe Ma #define SDMA7_EDC_COUNTER_CLEAR__DUMMY_MASK 0x00000001L 6794f727eceSLe Ma //SDMA7_STATUS2_REG 6804f727eceSLe Ma #define SDMA7_STATUS2_REG__ID__SHIFT 0x0 6814f727eceSLe Ma #define SDMA7_STATUS2_REG__F32_INSTR_PTR__SHIFT 0x3 6824f727eceSLe Ma #define SDMA7_STATUS2_REG__CMD_OP__SHIFT 0x10 6834f727eceSLe Ma #define SDMA7_STATUS2_REG__ID_MASK 0x00000007L 6844f727eceSLe Ma #define SDMA7_STATUS2_REG__F32_INSTR_PTR_MASK 0x0000FFF8L 6854f727eceSLe Ma #define SDMA7_STATUS2_REG__CMD_OP_MASK 0xFFFF0000L 6864f727eceSLe Ma //SDMA7_ATOMIC_CNTL 6874f727eceSLe Ma #define SDMA7_ATOMIC_CNTL__LOOP_TIMER__SHIFT 0x0 6884f727eceSLe Ma #define SDMA7_ATOMIC_CNTL__ATOMIC_RTN_INT_ENABLE__SHIFT 0x1f 6894f727eceSLe Ma #define SDMA7_ATOMIC_CNTL__LOOP_TIMER_MASK 0x7FFFFFFFL 6904f727eceSLe Ma #define SDMA7_ATOMIC_CNTL__ATOMIC_RTN_INT_ENABLE_MASK 0x80000000L 6914f727eceSLe Ma //SDMA7_ATOMIC_PREOP_LO 6924f727eceSLe Ma #define SDMA7_ATOMIC_PREOP_LO__DATA__SHIFT 0x0 6934f727eceSLe Ma #define SDMA7_ATOMIC_PREOP_LO__DATA_MASK 0xFFFFFFFFL 6944f727eceSLe Ma //SDMA7_ATOMIC_PREOP_HI 6954f727eceSLe Ma #define SDMA7_ATOMIC_PREOP_HI__DATA__SHIFT 0x0 6964f727eceSLe Ma #define SDMA7_ATOMIC_PREOP_HI__DATA_MASK 0xFFFFFFFFL 6974f727eceSLe Ma //SDMA7_UTCL1_CNTL 6984f727eceSLe Ma #define SDMA7_UTCL1_CNTL__REDO_ENABLE__SHIFT 0x0 6994f727eceSLe Ma #define SDMA7_UTCL1_CNTL__REDO_DELAY__SHIFT 0x1 7004f727eceSLe Ma #define SDMA7_UTCL1_CNTL__REDO_WATERMK__SHIFT 0xb 7014f727eceSLe Ma #define SDMA7_UTCL1_CNTL__INVACK_DELAY__SHIFT 0xe 7024f727eceSLe Ma #define SDMA7_UTCL1_CNTL__REQL2_CREDIT__SHIFT 0x18 7034f727eceSLe Ma #define SDMA7_UTCL1_CNTL__VADDR_WATERMK__SHIFT 0x1d 7044f727eceSLe Ma #define SDMA7_UTCL1_CNTL__REDO_ENABLE_MASK 0x00000001L 7054f727eceSLe Ma #define SDMA7_UTCL1_CNTL__REDO_DELAY_MASK 0x000007FEL 7064f727eceSLe Ma #define SDMA7_UTCL1_CNTL__REDO_WATERMK_MASK 0x00003800L 7074f727eceSLe Ma #define SDMA7_UTCL1_CNTL__INVACK_DELAY_MASK 0x00FFC000L 7084f727eceSLe Ma #define SDMA7_UTCL1_CNTL__REQL2_CREDIT_MASK 0x1F000000L 7094f727eceSLe Ma #define SDMA7_UTCL1_CNTL__VADDR_WATERMK_MASK 0xE0000000L 7104f727eceSLe Ma //SDMA7_UTCL1_WATERMK 7114f727eceSLe Ma #define SDMA7_UTCL1_WATERMK__REQMC_WATERMK__SHIFT 0x0 7124f727eceSLe Ma #define SDMA7_UTCL1_WATERMK__REQPG_WATERMK__SHIFT 0x9 7134f727eceSLe Ma #define SDMA7_UTCL1_WATERMK__INVREQ_WATERMK__SHIFT 0x11 7144f727eceSLe Ma #define SDMA7_UTCL1_WATERMK__XNACK_WATERMK__SHIFT 0x19 7154f727eceSLe Ma #define SDMA7_UTCL1_WATERMK__REQMC_WATERMK_MASK 0x000001FFL 7164f727eceSLe Ma #define SDMA7_UTCL1_WATERMK__REQPG_WATERMK_MASK 0x0001FE00L 7174f727eceSLe Ma #define SDMA7_UTCL1_WATERMK__INVREQ_WATERMK_MASK 0x01FE0000L 7184f727eceSLe Ma #define SDMA7_UTCL1_WATERMK__XNACK_WATERMK_MASK 0xFE000000L 7194f727eceSLe Ma //SDMA7_UTCL1_RD_STATUS 7204f727eceSLe Ma #define SDMA7_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_EMPTY__SHIFT 0x0 7214f727eceSLe Ma #define SDMA7_UTCL1_RD_STATUS__RQMC_REQ_FIFO_EMPTY__SHIFT 0x1 7224f727eceSLe Ma #define SDMA7_UTCL1_RD_STATUS__RTPG_RET_BUF_EMPTY__SHIFT 0x2 7234f727eceSLe Ma #define SDMA7_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_EMPTY__SHIFT 0x3 7244f727eceSLe Ma #define SDMA7_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY__SHIFT 0x4 7254f727eceSLe Ma #define SDMA7_UTCL1_RD_STATUS__RQPG_REDO_FIFO_EMPTY__SHIFT 0x5 7264f727eceSLe Ma #define SDMA7_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_EMPTY__SHIFT 0x6 7274f727eceSLe Ma #define SDMA7_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_EMPTY__SHIFT 0x7 7284f727eceSLe Ma #define SDMA7_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_EMPTY__SHIFT 0x8 7294f727eceSLe Ma #define SDMA7_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_FULL__SHIFT 0x9 7304f727eceSLe Ma #define SDMA7_UTCL1_RD_STATUS__RQMC_REQ_FIFO_FULL__SHIFT 0xa 7314f727eceSLe Ma #define SDMA7_UTCL1_RD_STATUS__RTPG_RET_BUF_FULL__SHIFT 0xb 7324f727eceSLe Ma #define SDMA7_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_FULL__SHIFT 0xc 7334f727eceSLe Ma #define SDMA7_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_FULL__SHIFT 0xd 7344f727eceSLe Ma #define SDMA7_UTCL1_RD_STATUS__RQPG_REDO_FIFO_FULL__SHIFT 0xe 7354f727eceSLe Ma #define SDMA7_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_FULL__SHIFT 0xf 7364f727eceSLe Ma #define SDMA7_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_FULL__SHIFT 0x10 7374f727eceSLe Ma #define SDMA7_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_FULL__SHIFT 0x11 7384f727eceSLe Ma #define SDMA7_UTCL1_RD_STATUS__PAGE_FAULT__SHIFT 0x12 7394f727eceSLe Ma #define SDMA7_UTCL1_RD_STATUS__PAGE_NULL__SHIFT 0x13 7404f727eceSLe Ma #define SDMA7_UTCL1_RD_STATUS__REQL2_IDLE__SHIFT 0x14 7414f727eceSLe Ma #define SDMA7_UTCL1_RD_STATUS__CE_L1_STALL__SHIFT 0x15 7424f727eceSLe Ma #define SDMA7_UTCL1_RD_STATUS__NEXT_RD_VECTOR__SHIFT 0x16 7434f727eceSLe Ma #define SDMA7_UTCL1_RD_STATUS__MERGE_STATE__SHIFT 0x1a 7444f727eceSLe Ma #define SDMA7_UTCL1_RD_STATUS__ADDR_RD_RTR__SHIFT 0x1d 7454f727eceSLe Ma #define SDMA7_UTCL1_RD_STATUS__WPTR_POLLING__SHIFT 0x1e 7464f727eceSLe Ma #define SDMA7_UTCL1_RD_STATUS__INVREQ_SIZE__SHIFT 0x1f 7474f727eceSLe Ma #define SDMA7_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_EMPTY_MASK 0x00000001L 7484f727eceSLe Ma #define SDMA7_UTCL1_RD_STATUS__RQMC_REQ_FIFO_EMPTY_MASK 0x00000002L 7494f727eceSLe Ma #define SDMA7_UTCL1_RD_STATUS__RTPG_RET_BUF_EMPTY_MASK 0x00000004L 7504f727eceSLe Ma #define SDMA7_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_EMPTY_MASK 0x00000008L 7514f727eceSLe Ma #define SDMA7_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY_MASK 0x00000010L 7524f727eceSLe Ma #define SDMA7_UTCL1_RD_STATUS__RQPG_REDO_FIFO_EMPTY_MASK 0x00000020L 7534f727eceSLe Ma #define SDMA7_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_EMPTY_MASK 0x00000040L 7544f727eceSLe Ma #define SDMA7_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_EMPTY_MASK 0x00000080L 7554f727eceSLe Ma #define SDMA7_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_EMPTY_MASK 0x00000100L 7564f727eceSLe Ma #define SDMA7_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_FULL_MASK 0x00000200L 7574f727eceSLe Ma #define SDMA7_UTCL1_RD_STATUS__RQMC_REQ_FIFO_FULL_MASK 0x00000400L 7584f727eceSLe Ma #define SDMA7_UTCL1_RD_STATUS__RTPG_RET_BUF_FULL_MASK 0x00000800L 7594f727eceSLe Ma #define SDMA7_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_FULL_MASK 0x00001000L 7604f727eceSLe Ma #define SDMA7_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_FULL_MASK 0x00002000L 7614f727eceSLe Ma #define SDMA7_UTCL1_RD_STATUS__RQPG_REDO_FIFO_FULL_MASK 0x00004000L 7624f727eceSLe Ma #define SDMA7_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_FULL_MASK 0x00008000L 7634f727eceSLe Ma #define SDMA7_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_FULL_MASK 0x00010000L 7644f727eceSLe Ma #define SDMA7_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_FULL_MASK 0x00020000L 7654f727eceSLe Ma #define SDMA7_UTCL1_RD_STATUS__PAGE_FAULT_MASK 0x00040000L 7664f727eceSLe Ma #define SDMA7_UTCL1_RD_STATUS__PAGE_NULL_MASK 0x00080000L 7674f727eceSLe Ma #define SDMA7_UTCL1_RD_STATUS__REQL2_IDLE_MASK 0x00100000L 7684f727eceSLe Ma #define SDMA7_UTCL1_RD_STATUS__CE_L1_STALL_MASK 0x00200000L 7694f727eceSLe Ma #define SDMA7_UTCL1_RD_STATUS__NEXT_RD_VECTOR_MASK 0x03C00000L 7704f727eceSLe Ma #define SDMA7_UTCL1_RD_STATUS__MERGE_STATE_MASK 0x1C000000L 7714f727eceSLe Ma #define SDMA7_UTCL1_RD_STATUS__ADDR_RD_RTR_MASK 0x20000000L 7724f727eceSLe Ma #define SDMA7_UTCL1_RD_STATUS__WPTR_POLLING_MASK 0x40000000L 7734f727eceSLe Ma #define SDMA7_UTCL1_RD_STATUS__INVREQ_SIZE_MASK 0x80000000L 7744f727eceSLe Ma //SDMA7_UTCL1_WR_STATUS 7754f727eceSLe Ma #define SDMA7_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_EMPTY__SHIFT 0x0 7764f727eceSLe Ma #define SDMA7_UTCL1_WR_STATUS__RQMC_REQ_FIFO_EMPTY__SHIFT 0x1 7774f727eceSLe Ma #define SDMA7_UTCL1_WR_STATUS__RTPG_RET_BUF_EMPTY__SHIFT 0x2 7784f727eceSLe Ma #define SDMA7_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_EMPTY__SHIFT 0x3 7794f727eceSLe Ma #define SDMA7_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY__SHIFT 0x4 7804f727eceSLe Ma #define SDMA7_UTCL1_WR_STATUS__RQPG_REDO_FIFO_EMPTY__SHIFT 0x5 7814f727eceSLe Ma #define SDMA7_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_EMPTY__SHIFT 0x6 7824f727eceSLe Ma #define SDMA7_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_EMPTY__SHIFT 0x7 7834f727eceSLe Ma #define SDMA7_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_EMPTY__SHIFT 0x8 7844f727eceSLe Ma #define SDMA7_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_FULL__SHIFT 0x9 7854f727eceSLe Ma #define SDMA7_UTCL1_WR_STATUS__RQMC_REQ_FIFO_FULL__SHIFT 0xa 7864f727eceSLe Ma #define SDMA7_UTCL1_WR_STATUS__RTPG_RET_BUF_FULL__SHIFT 0xb 7874f727eceSLe Ma #define SDMA7_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_FULL__SHIFT 0xc 7884f727eceSLe Ma #define SDMA7_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_FULL__SHIFT 0xd 7894f727eceSLe Ma #define SDMA7_UTCL1_WR_STATUS__RQPG_REDO_FIFO_FULL__SHIFT 0xe 7904f727eceSLe Ma #define SDMA7_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_FULL__SHIFT 0xf 7914f727eceSLe Ma #define SDMA7_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_FULL__SHIFT 0x10 7924f727eceSLe Ma #define SDMA7_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_FULL__SHIFT 0x11 7934f727eceSLe Ma #define SDMA7_UTCL1_WR_STATUS__PAGE_FAULT__SHIFT 0x12 7944f727eceSLe Ma #define SDMA7_UTCL1_WR_STATUS__PAGE_NULL__SHIFT 0x13 7954f727eceSLe Ma #define SDMA7_UTCL1_WR_STATUS__REQL2_IDLE__SHIFT 0x14 7964f727eceSLe Ma #define SDMA7_UTCL1_WR_STATUS__F32_WR_RTR__SHIFT 0x15 7974f727eceSLe Ma #define SDMA7_UTCL1_WR_STATUS__NEXT_WR_VECTOR__SHIFT 0x16 7984f727eceSLe Ma #define SDMA7_UTCL1_WR_STATUS__MERGE_STATE__SHIFT 0x19 7994f727eceSLe Ma #define SDMA7_UTCL1_WR_STATUS__RPTR_DATA_FIFO_EMPTY__SHIFT 0x1c 8004f727eceSLe Ma #define SDMA7_UTCL1_WR_STATUS__RPTR_DATA_FIFO_FULL__SHIFT 0x1d 8014f727eceSLe Ma #define SDMA7_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_EMPTY__SHIFT 0x1e 8024f727eceSLe Ma #define SDMA7_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_FULL__SHIFT 0x1f 8034f727eceSLe Ma #define SDMA7_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_EMPTY_MASK 0x00000001L 8044f727eceSLe Ma #define SDMA7_UTCL1_WR_STATUS__RQMC_REQ_FIFO_EMPTY_MASK 0x00000002L 8054f727eceSLe Ma #define SDMA7_UTCL1_WR_STATUS__RTPG_RET_BUF_EMPTY_MASK 0x00000004L 8064f727eceSLe Ma #define SDMA7_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_EMPTY_MASK 0x00000008L 8074f727eceSLe Ma #define SDMA7_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY_MASK 0x00000010L 8084f727eceSLe Ma #define SDMA7_UTCL1_WR_STATUS__RQPG_REDO_FIFO_EMPTY_MASK 0x00000020L 8094f727eceSLe Ma #define SDMA7_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_EMPTY_MASK 0x00000040L 8104f727eceSLe Ma #define SDMA7_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_EMPTY_MASK 0x00000080L 8114f727eceSLe Ma #define SDMA7_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_EMPTY_MASK 0x00000100L 8124f727eceSLe Ma #define SDMA7_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_FULL_MASK 0x00000200L 8134f727eceSLe Ma #define SDMA7_UTCL1_WR_STATUS__RQMC_REQ_FIFO_FULL_MASK 0x00000400L 8144f727eceSLe Ma #define SDMA7_UTCL1_WR_STATUS__RTPG_RET_BUF_FULL_MASK 0x00000800L 8154f727eceSLe Ma #define SDMA7_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_FULL_MASK 0x00001000L 8164f727eceSLe Ma #define SDMA7_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_FULL_MASK 0x00002000L 8174f727eceSLe Ma #define SDMA7_UTCL1_WR_STATUS__RQPG_REDO_FIFO_FULL_MASK 0x00004000L 8184f727eceSLe Ma #define SDMA7_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_FULL_MASK 0x00008000L 8194f727eceSLe Ma #define SDMA7_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_FULL_MASK 0x00010000L 8204f727eceSLe Ma #define SDMA7_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_FULL_MASK 0x00020000L 8214f727eceSLe Ma #define SDMA7_UTCL1_WR_STATUS__PAGE_FAULT_MASK 0x00040000L 8224f727eceSLe Ma #define SDMA7_UTCL1_WR_STATUS__PAGE_NULL_MASK 0x00080000L 8234f727eceSLe Ma #define SDMA7_UTCL1_WR_STATUS__REQL2_IDLE_MASK 0x00100000L 8244f727eceSLe Ma #define SDMA7_UTCL1_WR_STATUS__F32_WR_RTR_MASK 0x00200000L 8254f727eceSLe Ma #define SDMA7_UTCL1_WR_STATUS__NEXT_WR_VECTOR_MASK 0x01C00000L 8264f727eceSLe Ma #define SDMA7_UTCL1_WR_STATUS__MERGE_STATE_MASK 0x0E000000L 8274f727eceSLe Ma #define SDMA7_UTCL1_WR_STATUS__RPTR_DATA_FIFO_EMPTY_MASK 0x10000000L 8284f727eceSLe Ma #define SDMA7_UTCL1_WR_STATUS__RPTR_DATA_FIFO_FULL_MASK 0x20000000L 8294f727eceSLe Ma #define SDMA7_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_EMPTY_MASK 0x40000000L 8304f727eceSLe Ma #define SDMA7_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_FULL_MASK 0x80000000L 8314f727eceSLe Ma //SDMA7_UTCL1_INV0 8324f727eceSLe Ma #define SDMA7_UTCL1_INV0__INV_MIDDLE__SHIFT 0x0 8334f727eceSLe Ma #define SDMA7_UTCL1_INV0__RD_TIMEOUT__SHIFT 0x1 8344f727eceSLe Ma #define SDMA7_UTCL1_INV0__WR_TIMEOUT__SHIFT 0x2 8354f727eceSLe Ma #define SDMA7_UTCL1_INV0__RD_IN_INVADR__SHIFT 0x3 8364f727eceSLe Ma #define SDMA7_UTCL1_INV0__WR_IN_INVADR__SHIFT 0x4 8374f727eceSLe Ma #define SDMA7_UTCL1_INV0__PAGE_NULL_SW__SHIFT 0x5 8384f727eceSLe Ma #define SDMA7_UTCL1_INV0__XNACK_IS_INVADR__SHIFT 0x6 8394f727eceSLe Ma #define SDMA7_UTCL1_INV0__INVREQ_ENABLE__SHIFT 0x7 8404f727eceSLe Ma #define SDMA7_UTCL1_INV0__NACK_TIMEOUT_SW__SHIFT 0x8 8414f727eceSLe Ma #define SDMA7_UTCL1_INV0__NFLUSH_INV_IDLE__SHIFT 0x9 8424f727eceSLe Ma #define SDMA7_UTCL1_INV0__FLUSH_INV_IDLE__SHIFT 0xa 8434f727eceSLe Ma #define SDMA7_UTCL1_INV0__INV_FLUSHTYPE__SHIFT 0xb 8444f727eceSLe Ma #define SDMA7_UTCL1_INV0__INV_VMID_VEC__SHIFT 0xc 8454f727eceSLe Ma #define SDMA7_UTCL1_INV0__INV_ADDR_HI__SHIFT 0x1c 8464f727eceSLe Ma #define SDMA7_UTCL1_INV0__INV_MIDDLE_MASK 0x00000001L 8474f727eceSLe Ma #define SDMA7_UTCL1_INV0__RD_TIMEOUT_MASK 0x00000002L 8484f727eceSLe Ma #define SDMA7_UTCL1_INV0__WR_TIMEOUT_MASK 0x00000004L 8494f727eceSLe Ma #define SDMA7_UTCL1_INV0__RD_IN_INVADR_MASK 0x00000008L 8504f727eceSLe Ma #define SDMA7_UTCL1_INV0__WR_IN_INVADR_MASK 0x00000010L 8514f727eceSLe Ma #define SDMA7_UTCL1_INV0__PAGE_NULL_SW_MASK 0x00000020L 8524f727eceSLe Ma #define SDMA7_UTCL1_INV0__XNACK_IS_INVADR_MASK 0x00000040L 8534f727eceSLe Ma #define SDMA7_UTCL1_INV0__INVREQ_ENABLE_MASK 0x00000080L 8544f727eceSLe Ma #define SDMA7_UTCL1_INV0__NACK_TIMEOUT_SW_MASK 0x00000100L 8554f727eceSLe Ma #define SDMA7_UTCL1_INV0__NFLUSH_INV_IDLE_MASK 0x00000200L 8564f727eceSLe Ma #define SDMA7_UTCL1_INV0__FLUSH_INV_IDLE_MASK 0x00000400L 8574f727eceSLe Ma #define SDMA7_UTCL1_INV0__INV_FLUSHTYPE_MASK 0x00000800L 8584f727eceSLe Ma #define SDMA7_UTCL1_INV0__INV_VMID_VEC_MASK 0x0FFFF000L 8594f727eceSLe Ma #define SDMA7_UTCL1_INV0__INV_ADDR_HI_MASK 0xF0000000L 8604f727eceSLe Ma //SDMA7_UTCL1_INV1 8614f727eceSLe Ma #define SDMA7_UTCL1_INV1__INV_ADDR_LO__SHIFT 0x0 8624f727eceSLe Ma #define SDMA7_UTCL1_INV1__INV_ADDR_LO_MASK 0xFFFFFFFFL 8634f727eceSLe Ma //SDMA7_UTCL1_INV2 8644f727eceSLe Ma #define SDMA7_UTCL1_INV2__INV_NFLUSH_VMID_VEC__SHIFT 0x0 8654f727eceSLe Ma #define SDMA7_UTCL1_INV2__INV_NFLUSH_VMID_VEC_MASK 0xFFFFFFFFL 8664f727eceSLe Ma //SDMA7_UTCL1_RD_XNACK0 8674f727eceSLe Ma #define SDMA7_UTCL1_RD_XNACK0__XNACK_ADDR_LO__SHIFT 0x0 8684f727eceSLe Ma #define SDMA7_UTCL1_RD_XNACK0__XNACK_ADDR_LO_MASK 0xFFFFFFFFL 8694f727eceSLe Ma //SDMA7_UTCL1_RD_XNACK1 8704f727eceSLe Ma #define SDMA7_UTCL1_RD_XNACK1__XNACK_ADDR_HI__SHIFT 0x0 8714f727eceSLe Ma #define SDMA7_UTCL1_RD_XNACK1__XNACK_VMID__SHIFT 0x4 8724f727eceSLe Ma #define SDMA7_UTCL1_RD_XNACK1__XNACK_VECTOR__SHIFT 0x8 8734f727eceSLe Ma #define SDMA7_UTCL1_RD_XNACK1__IS_XNACK__SHIFT 0x1a 8744f727eceSLe Ma #define SDMA7_UTCL1_RD_XNACK1__XNACK_ADDR_HI_MASK 0x0000000FL 8754f727eceSLe Ma #define SDMA7_UTCL1_RD_XNACK1__XNACK_VMID_MASK 0x000000F0L 8764f727eceSLe Ma #define SDMA7_UTCL1_RD_XNACK1__XNACK_VECTOR_MASK 0x03FFFF00L 8774f727eceSLe Ma #define SDMA7_UTCL1_RD_XNACK1__IS_XNACK_MASK 0x0C000000L 8784f727eceSLe Ma //SDMA7_UTCL1_WR_XNACK0 8794f727eceSLe Ma #define SDMA7_UTCL1_WR_XNACK0__XNACK_ADDR_LO__SHIFT 0x0 8804f727eceSLe Ma #define SDMA7_UTCL1_WR_XNACK0__XNACK_ADDR_LO_MASK 0xFFFFFFFFL 8814f727eceSLe Ma //SDMA7_UTCL1_WR_XNACK1 8824f727eceSLe Ma #define SDMA7_UTCL1_WR_XNACK1__XNACK_ADDR_HI__SHIFT 0x0 8834f727eceSLe Ma #define SDMA7_UTCL1_WR_XNACK1__XNACK_VMID__SHIFT 0x4 8844f727eceSLe Ma #define SDMA7_UTCL1_WR_XNACK1__XNACK_VECTOR__SHIFT 0x8 8854f727eceSLe Ma #define SDMA7_UTCL1_WR_XNACK1__IS_XNACK__SHIFT 0x1a 8864f727eceSLe Ma #define SDMA7_UTCL1_WR_XNACK1__XNACK_ADDR_HI_MASK 0x0000000FL 8874f727eceSLe Ma #define SDMA7_UTCL1_WR_XNACK1__XNACK_VMID_MASK 0x000000F0L 8884f727eceSLe Ma #define SDMA7_UTCL1_WR_XNACK1__XNACK_VECTOR_MASK 0x03FFFF00L 8894f727eceSLe Ma #define SDMA7_UTCL1_WR_XNACK1__IS_XNACK_MASK 0x0C000000L 8904f727eceSLe Ma //SDMA7_UTCL1_TIMEOUT 8914f727eceSLe Ma #define SDMA7_UTCL1_TIMEOUT__RD_XNACK_LIMIT__SHIFT 0x0 8924f727eceSLe Ma #define SDMA7_UTCL1_TIMEOUT__WR_XNACK_LIMIT__SHIFT 0x10 8934f727eceSLe Ma #define SDMA7_UTCL1_TIMEOUT__RD_XNACK_LIMIT_MASK 0x0000FFFFL 8944f727eceSLe Ma #define SDMA7_UTCL1_TIMEOUT__WR_XNACK_LIMIT_MASK 0xFFFF0000L 8954f727eceSLe Ma //SDMA7_UTCL1_PAGE 8964f727eceSLe Ma #define SDMA7_UTCL1_PAGE__VM_HOLE__SHIFT 0x0 8974f727eceSLe Ma #define SDMA7_UTCL1_PAGE__REQ_TYPE__SHIFT 0x1 8984f727eceSLe Ma #define SDMA7_UTCL1_PAGE__USE_MTYPE__SHIFT 0x6 8994f727eceSLe Ma #define SDMA7_UTCL1_PAGE__USE_PT_SNOOP__SHIFT 0x9 9004f727eceSLe Ma #define SDMA7_UTCL1_PAGE__VM_HOLE_MASK 0x00000001L 9014f727eceSLe Ma #define SDMA7_UTCL1_PAGE__REQ_TYPE_MASK 0x0000001EL 9024f727eceSLe Ma #define SDMA7_UTCL1_PAGE__USE_MTYPE_MASK 0x000001C0L 9034f727eceSLe Ma #define SDMA7_UTCL1_PAGE__USE_PT_SNOOP_MASK 0x00000200L 9044f727eceSLe Ma //SDMA7_POWER_CNTL_IDLE 9054f727eceSLe Ma #define SDMA7_POWER_CNTL_IDLE__DELAY0__SHIFT 0x0 9064f727eceSLe Ma #define SDMA7_POWER_CNTL_IDLE__DELAY1__SHIFT 0x10 9074f727eceSLe Ma #define SDMA7_POWER_CNTL_IDLE__DELAY2__SHIFT 0x18 9084f727eceSLe Ma #define SDMA7_POWER_CNTL_IDLE__DELAY0_MASK 0x0000FFFFL 9094f727eceSLe Ma #define SDMA7_POWER_CNTL_IDLE__DELAY1_MASK 0x00FF0000L 9104f727eceSLe Ma #define SDMA7_POWER_CNTL_IDLE__DELAY2_MASK 0xFF000000L 9114f727eceSLe Ma //SDMA7_RELAX_ORDERING_LUT 9124f727eceSLe Ma #define SDMA7_RELAX_ORDERING_LUT__RESERVED0__SHIFT 0x0 9134f727eceSLe Ma #define SDMA7_RELAX_ORDERING_LUT__COPY__SHIFT 0x1 9144f727eceSLe Ma #define SDMA7_RELAX_ORDERING_LUT__WRITE__SHIFT 0x2 9154f727eceSLe Ma #define SDMA7_RELAX_ORDERING_LUT__RESERVED3__SHIFT 0x3 9164f727eceSLe Ma #define SDMA7_RELAX_ORDERING_LUT__RESERVED4__SHIFT 0x4 9174f727eceSLe Ma #define SDMA7_RELAX_ORDERING_LUT__FENCE__SHIFT 0x5 9184f727eceSLe Ma #define SDMA7_RELAX_ORDERING_LUT__RESERVED76__SHIFT 0x6 9194f727eceSLe Ma #define SDMA7_RELAX_ORDERING_LUT__POLL_MEM__SHIFT 0x8 9204f727eceSLe Ma #define SDMA7_RELAX_ORDERING_LUT__COND_EXE__SHIFT 0x9 9214f727eceSLe Ma #define SDMA7_RELAX_ORDERING_LUT__ATOMIC__SHIFT 0xa 9224f727eceSLe Ma #define SDMA7_RELAX_ORDERING_LUT__CONST_FILL__SHIFT 0xb 9234f727eceSLe Ma #define SDMA7_RELAX_ORDERING_LUT__PTEPDE__SHIFT 0xc 9244f727eceSLe Ma #define SDMA7_RELAX_ORDERING_LUT__TIMESTAMP__SHIFT 0xd 9254f727eceSLe Ma #define SDMA7_RELAX_ORDERING_LUT__RESERVED__SHIFT 0xe 9264f727eceSLe Ma #define SDMA7_RELAX_ORDERING_LUT__WORLD_SWITCH__SHIFT 0x1b 9274f727eceSLe Ma #define SDMA7_RELAX_ORDERING_LUT__RPTR_WRB__SHIFT 0x1c 9284f727eceSLe Ma #define SDMA7_RELAX_ORDERING_LUT__WPTR_POLL__SHIFT 0x1d 9294f727eceSLe Ma #define SDMA7_RELAX_ORDERING_LUT__IB_FETCH__SHIFT 0x1e 9304f727eceSLe Ma #define SDMA7_RELAX_ORDERING_LUT__RB_FETCH__SHIFT 0x1f 9314f727eceSLe Ma #define SDMA7_RELAX_ORDERING_LUT__RESERVED0_MASK 0x00000001L 9324f727eceSLe Ma #define SDMA7_RELAX_ORDERING_LUT__COPY_MASK 0x00000002L 9334f727eceSLe Ma #define SDMA7_RELAX_ORDERING_LUT__WRITE_MASK 0x00000004L 9344f727eceSLe Ma #define SDMA7_RELAX_ORDERING_LUT__RESERVED3_MASK 0x00000008L 9354f727eceSLe Ma #define SDMA7_RELAX_ORDERING_LUT__RESERVED4_MASK 0x00000010L 9364f727eceSLe Ma #define SDMA7_RELAX_ORDERING_LUT__FENCE_MASK 0x00000020L 9374f727eceSLe Ma #define SDMA7_RELAX_ORDERING_LUT__RESERVED76_MASK 0x000000C0L 9384f727eceSLe Ma #define SDMA7_RELAX_ORDERING_LUT__POLL_MEM_MASK 0x00000100L 9394f727eceSLe Ma #define SDMA7_RELAX_ORDERING_LUT__COND_EXE_MASK 0x00000200L 9404f727eceSLe Ma #define SDMA7_RELAX_ORDERING_LUT__ATOMIC_MASK 0x00000400L 9414f727eceSLe Ma #define SDMA7_RELAX_ORDERING_LUT__CONST_FILL_MASK 0x00000800L 9424f727eceSLe Ma #define SDMA7_RELAX_ORDERING_LUT__PTEPDE_MASK 0x00001000L 9434f727eceSLe Ma #define SDMA7_RELAX_ORDERING_LUT__TIMESTAMP_MASK 0x00002000L 9444f727eceSLe Ma #define SDMA7_RELAX_ORDERING_LUT__RESERVED_MASK 0x07FFC000L 9454f727eceSLe Ma #define SDMA7_RELAX_ORDERING_LUT__WORLD_SWITCH_MASK 0x08000000L 9464f727eceSLe Ma #define SDMA7_RELAX_ORDERING_LUT__RPTR_WRB_MASK 0x10000000L 9474f727eceSLe Ma #define SDMA7_RELAX_ORDERING_LUT__WPTR_POLL_MASK 0x20000000L 9484f727eceSLe Ma #define SDMA7_RELAX_ORDERING_LUT__IB_FETCH_MASK 0x40000000L 9494f727eceSLe Ma #define SDMA7_RELAX_ORDERING_LUT__RB_FETCH_MASK 0x80000000L 9504f727eceSLe Ma //SDMA7_CHICKEN_BITS_2 9514f727eceSLe Ma #define SDMA7_CHICKEN_BITS_2__F32_CMD_PROC_DELAY__SHIFT 0x0 9524f727eceSLe Ma #define SDMA7_CHICKEN_BITS_2__F32_CMD_PROC_DELAY_MASK 0x0000000FL 9534f727eceSLe Ma //SDMA7_STATUS3_REG 9544f727eceSLe Ma #define SDMA7_STATUS3_REG__CMD_OP_STATUS__SHIFT 0x0 9554f727eceSLe Ma #define SDMA7_STATUS3_REG__PREV_VM_CMD__SHIFT 0x10 9564f727eceSLe Ma #define SDMA7_STATUS3_REG__EXCEPTION_IDLE__SHIFT 0x14 9574f727eceSLe Ma #define SDMA7_STATUS3_REG__QUEUE_ID_MATCH__SHIFT 0x15 9584f727eceSLe Ma #define SDMA7_STATUS3_REG__INT_QUEUE_ID__SHIFT 0x16 9594f727eceSLe Ma #define SDMA7_STATUS3_REG__CMD_OP_STATUS_MASK 0x0000FFFFL 9604f727eceSLe Ma #define SDMA7_STATUS3_REG__PREV_VM_CMD_MASK 0x000F0000L 9614f727eceSLe Ma #define SDMA7_STATUS3_REG__EXCEPTION_IDLE_MASK 0x00100000L 9624f727eceSLe Ma #define SDMA7_STATUS3_REG__QUEUE_ID_MATCH_MASK 0x00200000L 9634f727eceSLe Ma #define SDMA7_STATUS3_REG__INT_QUEUE_ID_MASK 0x03C00000L 9644f727eceSLe Ma //SDMA7_PHYSICAL_ADDR_LO 9654f727eceSLe Ma #define SDMA7_PHYSICAL_ADDR_LO__D_VALID__SHIFT 0x0 9664f727eceSLe Ma #define SDMA7_PHYSICAL_ADDR_LO__DIRTY__SHIFT 0x1 9674f727eceSLe Ma #define SDMA7_PHYSICAL_ADDR_LO__PHY_VALID__SHIFT 0x2 9684f727eceSLe Ma #define SDMA7_PHYSICAL_ADDR_LO__ADDR__SHIFT 0xc 9694f727eceSLe Ma #define SDMA7_PHYSICAL_ADDR_LO__D_VALID_MASK 0x00000001L 9704f727eceSLe Ma #define SDMA7_PHYSICAL_ADDR_LO__DIRTY_MASK 0x00000002L 9714f727eceSLe Ma #define SDMA7_PHYSICAL_ADDR_LO__PHY_VALID_MASK 0x00000004L 9724f727eceSLe Ma #define SDMA7_PHYSICAL_ADDR_LO__ADDR_MASK 0xFFFFF000L 9734f727eceSLe Ma //SDMA7_PHYSICAL_ADDR_HI 9744f727eceSLe Ma #define SDMA7_PHYSICAL_ADDR_HI__ADDR__SHIFT 0x0 9754f727eceSLe Ma #define SDMA7_PHYSICAL_ADDR_HI__ADDR_MASK 0x0000FFFFL 9764f727eceSLe Ma //SDMA7_PHASE2_QUANTUM 9774f727eceSLe Ma #define SDMA7_PHASE2_QUANTUM__UNIT__SHIFT 0x0 9784f727eceSLe Ma #define SDMA7_PHASE2_QUANTUM__VALUE__SHIFT 0x8 9794f727eceSLe Ma #define SDMA7_PHASE2_QUANTUM__PREFER__SHIFT 0x1e 9804f727eceSLe Ma #define SDMA7_PHASE2_QUANTUM__UNIT_MASK 0x0000000FL 9814f727eceSLe Ma #define SDMA7_PHASE2_QUANTUM__VALUE_MASK 0x00FFFF00L 9824f727eceSLe Ma #define SDMA7_PHASE2_QUANTUM__PREFER_MASK 0x40000000L 9834f727eceSLe Ma //SDMA7_ERROR_LOG 9844f727eceSLe Ma #define SDMA7_ERROR_LOG__OVERRIDE__SHIFT 0x0 9854f727eceSLe Ma #define SDMA7_ERROR_LOG__STATUS__SHIFT 0x10 9864f727eceSLe Ma #define SDMA7_ERROR_LOG__OVERRIDE_MASK 0x0000FFFFL 9874f727eceSLe Ma #define SDMA7_ERROR_LOG__STATUS_MASK 0xFFFF0000L 9884f727eceSLe Ma //SDMA7_PUB_DUMMY_REG0 9894f727eceSLe Ma #define SDMA7_PUB_DUMMY_REG0__VALUE__SHIFT 0x0 9904f727eceSLe Ma #define SDMA7_PUB_DUMMY_REG0__VALUE_MASK 0xFFFFFFFFL 9914f727eceSLe Ma //SDMA7_PUB_DUMMY_REG1 9924f727eceSLe Ma #define SDMA7_PUB_DUMMY_REG1__VALUE__SHIFT 0x0 9934f727eceSLe Ma #define SDMA7_PUB_DUMMY_REG1__VALUE_MASK 0xFFFFFFFFL 9944f727eceSLe Ma //SDMA7_PUB_DUMMY_REG2 9954f727eceSLe Ma #define SDMA7_PUB_DUMMY_REG2__VALUE__SHIFT 0x0 9964f727eceSLe Ma #define SDMA7_PUB_DUMMY_REG2__VALUE_MASK 0xFFFFFFFFL 9974f727eceSLe Ma //SDMA7_PUB_DUMMY_REG3 9984f727eceSLe Ma #define SDMA7_PUB_DUMMY_REG3__VALUE__SHIFT 0x0 9994f727eceSLe Ma #define SDMA7_PUB_DUMMY_REG3__VALUE_MASK 0xFFFFFFFFL 10004f727eceSLe Ma //SDMA7_F32_COUNTER 10014f727eceSLe Ma #define SDMA7_F32_COUNTER__VALUE__SHIFT 0x0 10024f727eceSLe Ma #define SDMA7_F32_COUNTER__VALUE_MASK 0xFFFFFFFFL 10034f727eceSLe Ma //SDMA7_UNBREAKABLE 10044f727eceSLe Ma #define SDMA7_UNBREAKABLE__VALUE__SHIFT 0x0 10054f727eceSLe Ma #define SDMA7_UNBREAKABLE__VALUE_MASK 0x00000001L 10064f727eceSLe Ma //SDMA7_PERFMON_CNTL 10074f727eceSLe Ma #define SDMA7_PERFMON_CNTL__PERF_ENABLE0__SHIFT 0x0 10084f727eceSLe Ma #define SDMA7_PERFMON_CNTL__PERF_CLEAR0__SHIFT 0x1 10094f727eceSLe Ma #define SDMA7_PERFMON_CNTL__PERF_SEL0__SHIFT 0x2 10104f727eceSLe Ma #define SDMA7_PERFMON_CNTL__PERF_ENABLE1__SHIFT 0xa 10114f727eceSLe Ma #define SDMA7_PERFMON_CNTL__PERF_CLEAR1__SHIFT 0xb 10124f727eceSLe Ma #define SDMA7_PERFMON_CNTL__PERF_SEL1__SHIFT 0xc 10134f727eceSLe Ma #define SDMA7_PERFMON_CNTL__PERF_ENABLE0_MASK 0x00000001L 10144f727eceSLe Ma #define SDMA7_PERFMON_CNTL__PERF_CLEAR0_MASK 0x00000002L 10154f727eceSLe Ma #define SDMA7_PERFMON_CNTL__PERF_SEL0_MASK 0x000003FCL 10164f727eceSLe Ma #define SDMA7_PERFMON_CNTL__PERF_ENABLE1_MASK 0x00000400L 10174f727eceSLe Ma #define SDMA7_PERFMON_CNTL__PERF_CLEAR1_MASK 0x00000800L 10184f727eceSLe Ma #define SDMA7_PERFMON_CNTL__PERF_SEL1_MASK 0x000FF000L 10194f727eceSLe Ma //SDMA7_PERFCOUNTER0_RESULT 10204f727eceSLe Ma #define SDMA7_PERFCOUNTER0_RESULT__PERF_COUNT__SHIFT 0x0 10214f727eceSLe Ma #define SDMA7_PERFCOUNTER0_RESULT__PERF_COUNT_MASK 0xFFFFFFFFL 10224f727eceSLe Ma //SDMA7_PERFCOUNTER1_RESULT 10234f727eceSLe Ma #define SDMA7_PERFCOUNTER1_RESULT__PERF_COUNT__SHIFT 0x0 10244f727eceSLe Ma #define SDMA7_PERFCOUNTER1_RESULT__PERF_COUNT_MASK 0xFFFFFFFFL 10254f727eceSLe Ma //SDMA7_PERFCOUNTER_TAG_DELAY_RANGE 10264f727eceSLe Ma #define SDMA7_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_LOW__SHIFT 0x0 10274f727eceSLe Ma #define SDMA7_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_HIGH__SHIFT 0xe 10284f727eceSLe Ma #define SDMA7_PERFCOUNTER_TAG_DELAY_RANGE__SELECT_RW__SHIFT 0x1c 10294f727eceSLe Ma #define SDMA7_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_LOW_MASK 0x00003FFFL 10304f727eceSLe Ma #define SDMA7_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_HIGH_MASK 0x0FFFC000L 10314f727eceSLe Ma #define SDMA7_PERFCOUNTER_TAG_DELAY_RANGE__SELECT_RW_MASK 0x10000000L 10324f727eceSLe Ma //SDMA7_CRD_CNTL 10334f727eceSLe Ma #define SDMA7_CRD_CNTL__MC_WRREQ_CREDIT__SHIFT 0x7 10344f727eceSLe Ma #define SDMA7_CRD_CNTL__MC_RDREQ_CREDIT__SHIFT 0xd 10354f727eceSLe Ma #define SDMA7_CRD_CNTL__MC_WRREQ_CREDIT_MASK 0x00001F80L 10364f727eceSLe Ma #define SDMA7_CRD_CNTL__MC_RDREQ_CREDIT_MASK 0x0007E000L 10374f727eceSLe Ma //SDMA7_GPU_IOV_VIOLATION_LOG 10384f727eceSLe Ma #define SDMA7_GPU_IOV_VIOLATION_LOG__VIOLATION_STATUS__SHIFT 0x0 10394f727eceSLe Ma #define SDMA7_GPU_IOV_VIOLATION_LOG__MULTIPLE_VIOLATION_STATUS__SHIFT 0x1 10404f727eceSLe Ma #define SDMA7_GPU_IOV_VIOLATION_LOG__ADDRESS__SHIFT 0x2 10414f727eceSLe Ma #define SDMA7_GPU_IOV_VIOLATION_LOG__WRITE_OPERATION__SHIFT 0x14 10424f727eceSLe Ma #define SDMA7_GPU_IOV_VIOLATION_LOG__VF__SHIFT 0x15 10434f727eceSLe Ma #define SDMA7_GPU_IOV_VIOLATION_LOG__VFID__SHIFT 0x16 10444f727eceSLe Ma #define SDMA7_GPU_IOV_VIOLATION_LOG__VIOLATION_STATUS_MASK 0x00000001L 10454f727eceSLe Ma #define SDMA7_GPU_IOV_VIOLATION_LOG__MULTIPLE_VIOLATION_STATUS_MASK 0x00000002L 10464f727eceSLe Ma #define SDMA7_GPU_IOV_VIOLATION_LOG__ADDRESS_MASK 0x000FFFFCL 10474f727eceSLe Ma #define SDMA7_GPU_IOV_VIOLATION_LOG__WRITE_OPERATION_MASK 0x00100000L 10484f727eceSLe Ma #define SDMA7_GPU_IOV_VIOLATION_LOG__VF_MASK 0x00200000L 10494f727eceSLe Ma #define SDMA7_GPU_IOV_VIOLATION_LOG__VFID_MASK 0x03C00000L 10504f727eceSLe Ma //SDMA7_ULV_CNTL 10514f727eceSLe Ma #define SDMA7_ULV_CNTL__HYSTERESIS__SHIFT 0x0 10524f727eceSLe Ma #define SDMA7_ULV_CNTL__ENTER_ULV_INT_CLR__SHIFT 0x1b 10534f727eceSLe Ma #define SDMA7_ULV_CNTL__EXIT_ULV_INT_CLR__SHIFT 0x1c 10544f727eceSLe Ma #define SDMA7_ULV_CNTL__ENTER_ULV_INT__SHIFT 0x1d 10554f727eceSLe Ma #define SDMA7_ULV_CNTL__EXIT_ULV_INT__SHIFT 0x1e 10564f727eceSLe Ma #define SDMA7_ULV_CNTL__ULV_STATUS__SHIFT 0x1f 10574f727eceSLe Ma #define SDMA7_ULV_CNTL__HYSTERESIS_MASK 0x0000001FL 10584f727eceSLe Ma #define SDMA7_ULV_CNTL__ENTER_ULV_INT_CLR_MASK 0x08000000L 10594f727eceSLe Ma #define SDMA7_ULV_CNTL__EXIT_ULV_INT_CLR_MASK 0x10000000L 10604f727eceSLe Ma #define SDMA7_ULV_CNTL__ENTER_ULV_INT_MASK 0x20000000L 10614f727eceSLe Ma #define SDMA7_ULV_CNTL__EXIT_ULV_INT_MASK 0x40000000L 10624f727eceSLe Ma #define SDMA7_ULV_CNTL__ULV_STATUS_MASK 0x80000000L 10634f727eceSLe Ma //SDMA7_EA_DBIT_ADDR_DATA 10644f727eceSLe Ma #define SDMA7_EA_DBIT_ADDR_DATA__VALUE__SHIFT 0x0 10654f727eceSLe Ma #define SDMA7_EA_DBIT_ADDR_DATA__VALUE_MASK 0xFFFFFFFFL 10664f727eceSLe Ma //SDMA7_EA_DBIT_ADDR_INDEX 10674f727eceSLe Ma #define SDMA7_EA_DBIT_ADDR_INDEX__VALUE__SHIFT 0x0 10684f727eceSLe Ma #define SDMA7_EA_DBIT_ADDR_INDEX__VALUE_MASK 0x00000007L 10694f727eceSLe Ma //SDMA7_GPU_IOV_VIOLATION_LOG2 10704f727eceSLe Ma #define SDMA7_GPU_IOV_VIOLATION_LOG2__INITIATOR_ID__SHIFT 0x0 10714f727eceSLe Ma #define SDMA7_GPU_IOV_VIOLATION_LOG2__INITIATOR_ID_MASK 0x000000FFL 10724f727eceSLe Ma //SDMA7_GFX_RB_CNTL 10734f727eceSLe Ma #define SDMA7_GFX_RB_CNTL__RB_ENABLE__SHIFT 0x0 10744f727eceSLe Ma #define SDMA7_GFX_RB_CNTL__RB_SIZE__SHIFT 0x1 10754f727eceSLe Ma #define SDMA7_GFX_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 10764f727eceSLe Ma #define SDMA7_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc 10774f727eceSLe Ma #define SDMA7_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd 10784f727eceSLe Ma #define SDMA7_GFX_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 10794f727eceSLe Ma #define SDMA7_GFX_RB_CNTL__RB_PRIV__SHIFT 0x17 10804f727eceSLe Ma #define SDMA7_GFX_RB_CNTL__RB_VMID__SHIFT 0x18 10814f727eceSLe Ma #define SDMA7_GFX_RB_CNTL__RB_ENABLE_MASK 0x00000001L 10824f727eceSLe Ma #define SDMA7_GFX_RB_CNTL__RB_SIZE_MASK 0x0000003EL 10834f727eceSLe Ma #define SDMA7_GFX_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L 10844f727eceSLe Ma #define SDMA7_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L 10854f727eceSLe Ma #define SDMA7_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L 10864f727eceSLe Ma #define SDMA7_GFX_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L 10874f727eceSLe Ma #define SDMA7_GFX_RB_CNTL__RB_PRIV_MASK 0x00800000L 10884f727eceSLe Ma #define SDMA7_GFX_RB_CNTL__RB_VMID_MASK 0x0F000000L 10894f727eceSLe Ma //SDMA7_GFX_RB_BASE 10904f727eceSLe Ma #define SDMA7_GFX_RB_BASE__ADDR__SHIFT 0x0 10914f727eceSLe Ma #define SDMA7_GFX_RB_BASE__ADDR_MASK 0xFFFFFFFFL 10924f727eceSLe Ma //SDMA7_GFX_RB_BASE_HI 10934f727eceSLe Ma #define SDMA7_GFX_RB_BASE_HI__ADDR__SHIFT 0x0 10944f727eceSLe Ma #define SDMA7_GFX_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL 10954f727eceSLe Ma //SDMA7_GFX_RB_RPTR 10964f727eceSLe Ma #define SDMA7_GFX_RB_RPTR__OFFSET__SHIFT 0x0 10974f727eceSLe Ma #define SDMA7_GFX_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL 10984f727eceSLe Ma //SDMA7_GFX_RB_RPTR_HI 10994f727eceSLe Ma #define SDMA7_GFX_RB_RPTR_HI__OFFSET__SHIFT 0x0 11004f727eceSLe Ma #define SDMA7_GFX_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL 11014f727eceSLe Ma //SDMA7_GFX_RB_WPTR 11024f727eceSLe Ma #define SDMA7_GFX_RB_WPTR__OFFSET__SHIFT 0x0 11034f727eceSLe Ma #define SDMA7_GFX_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL 11044f727eceSLe Ma //SDMA7_GFX_RB_WPTR_HI 11054f727eceSLe Ma #define SDMA7_GFX_RB_WPTR_HI__OFFSET__SHIFT 0x0 11064f727eceSLe Ma #define SDMA7_GFX_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL 11074f727eceSLe Ma //SDMA7_GFX_RB_WPTR_POLL_CNTL 11084f727eceSLe Ma #define SDMA7_GFX_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 11094f727eceSLe Ma #define SDMA7_GFX_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 11104f727eceSLe Ma #define SDMA7_GFX_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 11114f727eceSLe Ma #define SDMA7_GFX_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 11124f727eceSLe Ma #define SDMA7_GFX_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 11134f727eceSLe Ma #define SDMA7_GFX_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L 11144f727eceSLe Ma #define SDMA7_GFX_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L 11154f727eceSLe Ma #define SDMA7_GFX_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L 11164f727eceSLe Ma #define SDMA7_GFX_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L 11174f727eceSLe Ma #define SDMA7_GFX_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L 11184f727eceSLe Ma //SDMA7_GFX_RB_RPTR_ADDR_HI 11194f727eceSLe Ma #define SDMA7_GFX_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 11204f727eceSLe Ma #define SDMA7_GFX_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 11214f727eceSLe Ma //SDMA7_GFX_RB_RPTR_ADDR_LO 11224f727eceSLe Ma #define SDMA7_GFX_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 11234f727eceSLe Ma #define SDMA7_GFX_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 11244f727eceSLe Ma #define SDMA7_GFX_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L 11254f727eceSLe Ma #define SDMA7_GFX_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 11264f727eceSLe Ma //SDMA7_GFX_IB_CNTL 11274f727eceSLe Ma #define SDMA7_GFX_IB_CNTL__IB_ENABLE__SHIFT 0x0 11284f727eceSLe Ma #define SDMA7_GFX_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 11294f727eceSLe Ma #define SDMA7_GFX_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 11304f727eceSLe Ma #define SDMA7_GFX_IB_CNTL__CMD_VMID__SHIFT 0x10 11314f727eceSLe Ma #define SDMA7_GFX_IB_CNTL__IB_ENABLE_MASK 0x00000001L 11324f727eceSLe Ma #define SDMA7_GFX_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L 11334f727eceSLe Ma #define SDMA7_GFX_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L 11344f727eceSLe Ma #define SDMA7_GFX_IB_CNTL__CMD_VMID_MASK 0x000F0000L 11354f727eceSLe Ma //SDMA7_GFX_IB_RPTR 11364f727eceSLe Ma #define SDMA7_GFX_IB_RPTR__OFFSET__SHIFT 0x2 11374f727eceSLe Ma #define SDMA7_GFX_IB_RPTR__OFFSET_MASK 0x003FFFFCL 11384f727eceSLe Ma //SDMA7_GFX_IB_OFFSET 11394f727eceSLe Ma #define SDMA7_GFX_IB_OFFSET__OFFSET__SHIFT 0x2 11404f727eceSLe Ma #define SDMA7_GFX_IB_OFFSET__OFFSET_MASK 0x003FFFFCL 11414f727eceSLe Ma //SDMA7_GFX_IB_BASE_LO 11424f727eceSLe Ma #define SDMA7_GFX_IB_BASE_LO__ADDR__SHIFT 0x5 11434f727eceSLe Ma #define SDMA7_GFX_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L 11444f727eceSLe Ma //SDMA7_GFX_IB_BASE_HI 11454f727eceSLe Ma #define SDMA7_GFX_IB_BASE_HI__ADDR__SHIFT 0x0 11464f727eceSLe Ma #define SDMA7_GFX_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL 11474f727eceSLe Ma //SDMA7_GFX_IB_SIZE 11484f727eceSLe Ma #define SDMA7_GFX_IB_SIZE__SIZE__SHIFT 0x0 11494f727eceSLe Ma #define SDMA7_GFX_IB_SIZE__SIZE_MASK 0x000FFFFFL 11504f727eceSLe Ma //SDMA7_GFX_SKIP_CNTL 11514f727eceSLe Ma #define SDMA7_GFX_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 11524f727eceSLe Ma #define SDMA7_GFX_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL 11534f727eceSLe Ma //SDMA7_GFX_CONTEXT_STATUS 11544f727eceSLe Ma #define SDMA7_GFX_CONTEXT_STATUS__SELECTED__SHIFT 0x0 11554f727eceSLe Ma #define SDMA7_GFX_CONTEXT_STATUS__IDLE__SHIFT 0x2 11564f727eceSLe Ma #define SDMA7_GFX_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 11574f727eceSLe Ma #define SDMA7_GFX_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 11584f727eceSLe Ma #define SDMA7_GFX_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 11594f727eceSLe Ma #define SDMA7_GFX_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 11604f727eceSLe Ma #define SDMA7_GFX_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 11614f727eceSLe Ma #define SDMA7_GFX_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa 11624f727eceSLe Ma #define SDMA7_GFX_CONTEXT_STATUS__SELECTED_MASK 0x00000001L 11634f727eceSLe Ma #define SDMA7_GFX_CONTEXT_STATUS__IDLE_MASK 0x00000004L 11644f727eceSLe Ma #define SDMA7_GFX_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L 11654f727eceSLe Ma #define SDMA7_GFX_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L 11664f727eceSLe Ma #define SDMA7_GFX_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L 11674f727eceSLe Ma #define SDMA7_GFX_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L 11684f727eceSLe Ma #define SDMA7_GFX_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L 11694f727eceSLe Ma #define SDMA7_GFX_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L 11704f727eceSLe Ma //SDMA7_GFX_DOORBELL 11714f727eceSLe Ma #define SDMA7_GFX_DOORBELL__ENABLE__SHIFT 0x1c 11724f727eceSLe Ma #define SDMA7_GFX_DOORBELL__CAPTURED__SHIFT 0x1e 11734f727eceSLe Ma #define SDMA7_GFX_DOORBELL__ENABLE_MASK 0x10000000L 11744f727eceSLe Ma #define SDMA7_GFX_DOORBELL__CAPTURED_MASK 0x40000000L 11754f727eceSLe Ma //SDMA7_GFX_CONTEXT_CNTL 11764f727eceSLe Ma #define SDMA7_GFX_CONTEXT_CNTL__RESUME_CTX__SHIFT 0x10 11774f727eceSLe Ma #define SDMA7_GFX_CONTEXT_CNTL__RESUME_CTX_MASK 0x00010000L 11784f727eceSLe Ma //SDMA7_GFX_STATUS 11794f727eceSLe Ma #define SDMA7_GFX_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 11804f727eceSLe Ma #define SDMA7_GFX_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 11814f727eceSLe Ma #define SDMA7_GFX_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL 11824f727eceSLe Ma #define SDMA7_GFX_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L 11834f727eceSLe Ma //SDMA7_GFX_DOORBELL_LOG 11844f727eceSLe Ma #define SDMA7_GFX_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 11854f727eceSLe Ma #define SDMA7_GFX_DOORBELL_LOG__DATA__SHIFT 0x2 11864f727eceSLe Ma #define SDMA7_GFX_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L 11874f727eceSLe Ma #define SDMA7_GFX_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL 11884f727eceSLe Ma //SDMA7_GFX_WATERMARK 11894f727eceSLe Ma #define SDMA7_GFX_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 11904f727eceSLe Ma #define SDMA7_GFX_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 11914f727eceSLe Ma #define SDMA7_GFX_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL 11924f727eceSLe Ma #define SDMA7_GFX_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L 11934f727eceSLe Ma //SDMA7_GFX_DOORBELL_OFFSET 11944f727eceSLe Ma #define SDMA7_GFX_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 11954f727eceSLe Ma #define SDMA7_GFX_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL 11964f727eceSLe Ma //SDMA7_GFX_CSA_ADDR_LO 11974f727eceSLe Ma #define SDMA7_GFX_CSA_ADDR_LO__ADDR__SHIFT 0x2 11984f727eceSLe Ma #define SDMA7_GFX_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 11994f727eceSLe Ma //SDMA7_GFX_CSA_ADDR_HI 12004f727eceSLe Ma #define SDMA7_GFX_CSA_ADDR_HI__ADDR__SHIFT 0x0 12014f727eceSLe Ma #define SDMA7_GFX_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 12024f727eceSLe Ma //SDMA7_GFX_IB_SUB_REMAIN 12034f727eceSLe Ma #define SDMA7_GFX_IB_SUB_REMAIN__SIZE__SHIFT 0x0 12044f727eceSLe Ma #define SDMA7_GFX_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL 12054f727eceSLe Ma //SDMA7_GFX_PREEMPT 12064f727eceSLe Ma #define SDMA7_GFX_PREEMPT__IB_PREEMPT__SHIFT 0x0 12074f727eceSLe Ma #define SDMA7_GFX_PREEMPT__IB_PREEMPT_MASK 0x00000001L 12084f727eceSLe Ma //SDMA7_GFX_DUMMY_REG 12094f727eceSLe Ma #define SDMA7_GFX_DUMMY_REG__DUMMY__SHIFT 0x0 12104f727eceSLe Ma #define SDMA7_GFX_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL 12114f727eceSLe Ma //SDMA7_GFX_RB_WPTR_POLL_ADDR_HI 12124f727eceSLe Ma #define SDMA7_GFX_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 12134f727eceSLe Ma #define SDMA7_GFX_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 12144f727eceSLe Ma //SDMA7_GFX_RB_WPTR_POLL_ADDR_LO 12154f727eceSLe Ma #define SDMA7_GFX_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 12164f727eceSLe Ma #define SDMA7_GFX_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 12174f727eceSLe Ma //SDMA7_GFX_RB_AQL_CNTL 12184f727eceSLe Ma #define SDMA7_GFX_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 12194f727eceSLe Ma #define SDMA7_GFX_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 12204f727eceSLe Ma #define SDMA7_GFX_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 12214f727eceSLe Ma #define SDMA7_GFX_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L 12224f727eceSLe Ma #define SDMA7_GFX_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL 12234f727eceSLe Ma #define SDMA7_GFX_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L 12244f727eceSLe Ma //SDMA7_GFX_MINOR_PTR_UPDATE 12254f727eceSLe Ma #define SDMA7_GFX_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 12264f727eceSLe Ma #define SDMA7_GFX_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L 12274f727eceSLe Ma //SDMA7_GFX_MIDCMD_DATA0 12284f727eceSLe Ma #define SDMA7_GFX_MIDCMD_DATA0__DATA0__SHIFT 0x0 12294f727eceSLe Ma #define SDMA7_GFX_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL 12304f727eceSLe Ma //SDMA7_GFX_MIDCMD_DATA1 12314f727eceSLe Ma #define SDMA7_GFX_MIDCMD_DATA1__DATA1__SHIFT 0x0 12324f727eceSLe Ma #define SDMA7_GFX_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL 12334f727eceSLe Ma //SDMA7_GFX_MIDCMD_DATA2 12344f727eceSLe Ma #define SDMA7_GFX_MIDCMD_DATA2__DATA2__SHIFT 0x0 12354f727eceSLe Ma #define SDMA7_GFX_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL 12364f727eceSLe Ma //SDMA7_GFX_MIDCMD_DATA3 12374f727eceSLe Ma #define SDMA7_GFX_MIDCMD_DATA3__DATA3__SHIFT 0x0 12384f727eceSLe Ma #define SDMA7_GFX_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL 12394f727eceSLe Ma //SDMA7_GFX_MIDCMD_DATA4 12404f727eceSLe Ma #define SDMA7_GFX_MIDCMD_DATA4__DATA4__SHIFT 0x0 12414f727eceSLe Ma #define SDMA7_GFX_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL 12424f727eceSLe Ma //SDMA7_GFX_MIDCMD_DATA5 12434f727eceSLe Ma #define SDMA7_GFX_MIDCMD_DATA5__DATA5__SHIFT 0x0 12444f727eceSLe Ma #define SDMA7_GFX_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL 12454f727eceSLe Ma //SDMA7_GFX_MIDCMD_DATA6 12464f727eceSLe Ma #define SDMA7_GFX_MIDCMD_DATA6__DATA6__SHIFT 0x0 12474f727eceSLe Ma #define SDMA7_GFX_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL 12484f727eceSLe Ma //SDMA7_GFX_MIDCMD_DATA7 12494f727eceSLe Ma #define SDMA7_GFX_MIDCMD_DATA7__DATA7__SHIFT 0x0 12504f727eceSLe Ma #define SDMA7_GFX_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL 12514f727eceSLe Ma //SDMA7_GFX_MIDCMD_DATA8 12524f727eceSLe Ma #define SDMA7_GFX_MIDCMD_DATA8__DATA8__SHIFT 0x0 12534f727eceSLe Ma #define SDMA7_GFX_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL 12544f727eceSLe Ma //SDMA7_GFX_MIDCMD_CNTL 12554f727eceSLe Ma #define SDMA7_GFX_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 12564f727eceSLe Ma #define SDMA7_GFX_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 12574f727eceSLe Ma #define SDMA7_GFX_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 12584f727eceSLe Ma #define SDMA7_GFX_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 12594f727eceSLe Ma #define SDMA7_GFX_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L 12604f727eceSLe Ma #define SDMA7_GFX_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L 12614f727eceSLe Ma #define SDMA7_GFX_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L 12624f727eceSLe Ma #define SDMA7_GFX_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L 12634f727eceSLe Ma //SDMA7_PAGE_RB_CNTL 12644f727eceSLe Ma #define SDMA7_PAGE_RB_CNTL__RB_ENABLE__SHIFT 0x0 12654f727eceSLe Ma #define SDMA7_PAGE_RB_CNTL__RB_SIZE__SHIFT 0x1 12664f727eceSLe Ma #define SDMA7_PAGE_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 12674f727eceSLe Ma #define SDMA7_PAGE_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc 12684f727eceSLe Ma #define SDMA7_PAGE_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd 12694f727eceSLe Ma #define SDMA7_PAGE_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 12704f727eceSLe Ma #define SDMA7_PAGE_RB_CNTL__RB_PRIV__SHIFT 0x17 12714f727eceSLe Ma #define SDMA7_PAGE_RB_CNTL__RB_VMID__SHIFT 0x18 12724f727eceSLe Ma #define SDMA7_PAGE_RB_CNTL__RB_ENABLE_MASK 0x00000001L 12734f727eceSLe Ma #define SDMA7_PAGE_RB_CNTL__RB_SIZE_MASK 0x0000003EL 12744f727eceSLe Ma #define SDMA7_PAGE_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L 12754f727eceSLe Ma #define SDMA7_PAGE_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L 12764f727eceSLe Ma #define SDMA7_PAGE_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L 12774f727eceSLe Ma #define SDMA7_PAGE_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L 12784f727eceSLe Ma #define SDMA7_PAGE_RB_CNTL__RB_PRIV_MASK 0x00800000L 12794f727eceSLe Ma #define SDMA7_PAGE_RB_CNTL__RB_VMID_MASK 0x0F000000L 12804f727eceSLe Ma //SDMA7_PAGE_RB_BASE 12814f727eceSLe Ma #define SDMA7_PAGE_RB_BASE__ADDR__SHIFT 0x0 12824f727eceSLe Ma #define SDMA7_PAGE_RB_BASE__ADDR_MASK 0xFFFFFFFFL 12834f727eceSLe Ma //SDMA7_PAGE_RB_BASE_HI 12844f727eceSLe Ma #define SDMA7_PAGE_RB_BASE_HI__ADDR__SHIFT 0x0 12854f727eceSLe Ma #define SDMA7_PAGE_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL 12864f727eceSLe Ma //SDMA7_PAGE_RB_RPTR 12874f727eceSLe Ma #define SDMA7_PAGE_RB_RPTR__OFFSET__SHIFT 0x0 12884f727eceSLe Ma #define SDMA7_PAGE_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL 12894f727eceSLe Ma //SDMA7_PAGE_RB_RPTR_HI 12904f727eceSLe Ma #define SDMA7_PAGE_RB_RPTR_HI__OFFSET__SHIFT 0x0 12914f727eceSLe Ma #define SDMA7_PAGE_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL 12924f727eceSLe Ma //SDMA7_PAGE_RB_WPTR 12934f727eceSLe Ma #define SDMA7_PAGE_RB_WPTR__OFFSET__SHIFT 0x0 12944f727eceSLe Ma #define SDMA7_PAGE_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL 12954f727eceSLe Ma //SDMA7_PAGE_RB_WPTR_HI 12964f727eceSLe Ma #define SDMA7_PAGE_RB_WPTR_HI__OFFSET__SHIFT 0x0 12974f727eceSLe Ma #define SDMA7_PAGE_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL 12984f727eceSLe Ma //SDMA7_PAGE_RB_WPTR_POLL_CNTL 12994f727eceSLe Ma #define SDMA7_PAGE_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 13004f727eceSLe Ma #define SDMA7_PAGE_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 13014f727eceSLe Ma #define SDMA7_PAGE_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 13024f727eceSLe Ma #define SDMA7_PAGE_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 13034f727eceSLe Ma #define SDMA7_PAGE_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 13044f727eceSLe Ma #define SDMA7_PAGE_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L 13054f727eceSLe Ma #define SDMA7_PAGE_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L 13064f727eceSLe Ma #define SDMA7_PAGE_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L 13074f727eceSLe Ma #define SDMA7_PAGE_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L 13084f727eceSLe Ma #define SDMA7_PAGE_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L 13094f727eceSLe Ma //SDMA7_PAGE_RB_RPTR_ADDR_HI 13104f727eceSLe Ma #define SDMA7_PAGE_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 13114f727eceSLe Ma #define SDMA7_PAGE_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 13124f727eceSLe Ma //SDMA7_PAGE_RB_RPTR_ADDR_LO 13134f727eceSLe Ma #define SDMA7_PAGE_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 13144f727eceSLe Ma #define SDMA7_PAGE_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 13154f727eceSLe Ma #define SDMA7_PAGE_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L 13164f727eceSLe Ma #define SDMA7_PAGE_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 13174f727eceSLe Ma //SDMA7_PAGE_IB_CNTL 13184f727eceSLe Ma #define SDMA7_PAGE_IB_CNTL__IB_ENABLE__SHIFT 0x0 13194f727eceSLe Ma #define SDMA7_PAGE_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 13204f727eceSLe Ma #define SDMA7_PAGE_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 13214f727eceSLe Ma #define SDMA7_PAGE_IB_CNTL__CMD_VMID__SHIFT 0x10 13224f727eceSLe Ma #define SDMA7_PAGE_IB_CNTL__IB_ENABLE_MASK 0x00000001L 13234f727eceSLe Ma #define SDMA7_PAGE_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L 13244f727eceSLe Ma #define SDMA7_PAGE_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L 13254f727eceSLe Ma #define SDMA7_PAGE_IB_CNTL__CMD_VMID_MASK 0x000F0000L 13264f727eceSLe Ma //SDMA7_PAGE_IB_RPTR 13274f727eceSLe Ma #define SDMA7_PAGE_IB_RPTR__OFFSET__SHIFT 0x2 13284f727eceSLe Ma #define SDMA7_PAGE_IB_RPTR__OFFSET_MASK 0x003FFFFCL 13294f727eceSLe Ma //SDMA7_PAGE_IB_OFFSET 13304f727eceSLe Ma #define SDMA7_PAGE_IB_OFFSET__OFFSET__SHIFT 0x2 13314f727eceSLe Ma #define SDMA7_PAGE_IB_OFFSET__OFFSET_MASK 0x003FFFFCL 13324f727eceSLe Ma //SDMA7_PAGE_IB_BASE_LO 13334f727eceSLe Ma #define SDMA7_PAGE_IB_BASE_LO__ADDR__SHIFT 0x5 13344f727eceSLe Ma #define SDMA7_PAGE_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L 13354f727eceSLe Ma //SDMA7_PAGE_IB_BASE_HI 13364f727eceSLe Ma #define SDMA7_PAGE_IB_BASE_HI__ADDR__SHIFT 0x0 13374f727eceSLe Ma #define SDMA7_PAGE_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL 13384f727eceSLe Ma //SDMA7_PAGE_IB_SIZE 13394f727eceSLe Ma #define SDMA7_PAGE_IB_SIZE__SIZE__SHIFT 0x0 13404f727eceSLe Ma #define SDMA7_PAGE_IB_SIZE__SIZE_MASK 0x000FFFFFL 13414f727eceSLe Ma //SDMA7_PAGE_SKIP_CNTL 13424f727eceSLe Ma #define SDMA7_PAGE_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 13434f727eceSLe Ma #define SDMA7_PAGE_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL 13444f727eceSLe Ma //SDMA7_PAGE_CONTEXT_STATUS 13454f727eceSLe Ma #define SDMA7_PAGE_CONTEXT_STATUS__SELECTED__SHIFT 0x0 13464f727eceSLe Ma #define SDMA7_PAGE_CONTEXT_STATUS__IDLE__SHIFT 0x2 13474f727eceSLe Ma #define SDMA7_PAGE_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 13484f727eceSLe Ma #define SDMA7_PAGE_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 13494f727eceSLe Ma #define SDMA7_PAGE_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 13504f727eceSLe Ma #define SDMA7_PAGE_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 13514f727eceSLe Ma #define SDMA7_PAGE_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 13524f727eceSLe Ma #define SDMA7_PAGE_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa 13534f727eceSLe Ma #define SDMA7_PAGE_CONTEXT_STATUS__SELECTED_MASK 0x00000001L 13544f727eceSLe Ma #define SDMA7_PAGE_CONTEXT_STATUS__IDLE_MASK 0x00000004L 13554f727eceSLe Ma #define SDMA7_PAGE_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L 13564f727eceSLe Ma #define SDMA7_PAGE_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L 13574f727eceSLe Ma #define SDMA7_PAGE_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L 13584f727eceSLe Ma #define SDMA7_PAGE_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L 13594f727eceSLe Ma #define SDMA7_PAGE_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L 13604f727eceSLe Ma #define SDMA7_PAGE_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L 13614f727eceSLe Ma //SDMA7_PAGE_DOORBELL 13624f727eceSLe Ma #define SDMA7_PAGE_DOORBELL__ENABLE__SHIFT 0x1c 13634f727eceSLe Ma #define SDMA7_PAGE_DOORBELL__CAPTURED__SHIFT 0x1e 13644f727eceSLe Ma #define SDMA7_PAGE_DOORBELL__ENABLE_MASK 0x10000000L 13654f727eceSLe Ma #define SDMA7_PAGE_DOORBELL__CAPTURED_MASK 0x40000000L 13664f727eceSLe Ma //SDMA7_PAGE_STATUS 13674f727eceSLe Ma #define SDMA7_PAGE_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 13684f727eceSLe Ma #define SDMA7_PAGE_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 13694f727eceSLe Ma #define SDMA7_PAGE_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL 13704f727eceSLe Ma #define SDMA7_PAGE_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L 13714f727eceSLe Ma //SDMA7_PAGE_DOORBELL_LOG 13724f727eceSLe Ma #define SDMA7_PAGE_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 13734f727eceSLe Ma #define SDMA7_PAGE_DOORBELL_LOG__DATA__SHIFT 0x2 13744f727eceSLe Ma #define SDMA7_PAGE_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L 13754f727eceSLe Ma #define SDMA7_PAGE_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL 13764f727eceSLe Ma //SDMA7_PAGE_WATERMARK 13774f727eceSLe Ma #define SDMA7_PAGE_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 13784f727eceSLe Ma #define SDMA7_PAGE_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 13794f727eceSLe Ma #define SDMA7_PAGE_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL 13804f727eceSLe Ma #define SDMA7_PAGE_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L 13814f727eceSLe Ma //SDMA7_PAGE_DOORBELL_OFFSET 13824f727eceSLe Ma #define SDMA7_PAGE_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 13834f727eceSLe Ma #define SDMA7_PAGE_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL 13844f727eceSLe Ma //SDMA7_PAGE_CSA_ADDR_LO 13854f727eceSLe Ma #define SDMA7_PAGE_CSA_ADDR_LO__ADDR__SHIFT 0x2 13864f727eceSLe Ma #define SDMA7_PAGE_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 13874f727eceSLe Ma //SDMA7_PAGE_CSA_ADDR_HI 13884f727eceSLe Ma #define SDMA7_PAGE_CSA_ADDR_HI__ADDR__SHIFT 0x0 13894f727eceSLe Ma #define SDMA7_PAGE_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 13904f727eceSLe Ma //SDMA7_PAGE_IB_SUB_REMAIN 13914f727eceSLe Ma #define SDMA7_PAGE_IB_SUB_REMAIN__SIZE__SHIFT 0x0 13924f727eceSLe Ma #define SDMA7_PAGE_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL 13934f727eceSLe Ma //SDMA7_PAGE_PREEMPT 13944f727eceSLe Ma #define SDMA7_PAGE_PREEMPT__IB_PREEMPT__SHIFT 0x0 13954f727eceSLe Ma #define SDMA7_PAGE_PREEMPT__IB_PREEMPT_MASK 0x00000001L 13964f727eceSLe Ma //SDMA7_PAGE_DUMMY_REG 13974f727eceSLe Ma #define SDMA7_PAGE_DUMMY_REG__DUMMY__SHIFT 0x0 13984f727eceSLe Ma #define SDMA7_PAGE_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL 13994f727eceSLe Ma //SDMA7_PAGE_RB_WPTR_POLL_ADDR_HI 14004f727eceSLe Ma #define SDMA7_PAGE_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 14014f727eceSLe Ma #define SDMA7_PAGE_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 14024f727eceSLe Ma //SDMA7_PAGE_RB_WPTR_POLL_ADDR_LO 14034f727eceSLe Ma #define SDMA7_PAGE_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 14044f727eceSLe Ma #define SDMA7_PAGE_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 14054f727eceSLe Ma //SDMA7_PAGE_RB_AQL_CNTL 14064f727eceSLe Ma #define SDMA7_PAGE_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 14074f727eceSLe Ma #define SDMA7_PAGE_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 14084f727eceSLe Ma #define SDMA7_PAGE_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 14094f727eceSLe Ma #define SDMA7_PAGE_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L 14104f727eceSLe Ma #define SDMA7_PAGE_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL 14114f727eceSLe Ma #define SDMA7_PAGE_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L 14124f727eceSLe Ma //SDMA7_PAGE_MINOR_PTR_UPDATE 14134f727eceSLe Ma #define SDMA7_PAGE_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 14144f727eceSLe Ma #define SDMA7_PAGE_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L 14154f727eceSLe Ma //SDMA7_PAGE_MIDCMD_DATA0 14164f727eceSLe Ma #define SDMA7_PAGE_MIDCMD_DATA0__DATA0__SHIFT 0x0 14174f727eceSLe Ma #define SDMA7_PAGE_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL 14184f727eceSLe Ma //SDMA7_PAGE_MIDCMD_DATA1 14194f727eceSLe Ma #define SDMA7_PAGE_MIDCMD_DATA1__DATA1__SHIFT 0x0 14204f727eceSLe Ma #define SDMA7_PAGE_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL 14214f727eceSLe Ma //SDMA7_PAGE_MIDCMD_DATA2 14224f727eceSLe Ma #define SDMA7_PAGE_MIDCMD_DATA2__DATA2__SHIFT 0x0 14234f727eceSLe Ma #define SDMA7_PAGE_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL 14244f727eceSLe Ma //SDMA7_PAGE_MIDCMD_DATA3 14254f727eceSLe Ma #define SDMA7_PAGE_MIDCMD_DATA3__DATA3__SHIFT 0x0 14264f727eceSLe Ma #define SDMA7_PAGE_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL 14274f727eceSLe Ma //SDMA7_PAGE_MIDCMD_DATA4 14284f727eceSLe Ma #define SDMA7_PAGE_MIDCMD_DATA4__DATA4__SHIFT 0x0 14294f727eceSLe Ma #define SDMA7_PAGE_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL 14304f727eceSLe Ma //SDMA7_PAGE_MIDCMD_DATA5 14314f727eceSLe Ma #define SDMA7_PAGE_MIDCMD_DATA5__DATA5__SHIFT 0x0 14324f727eceSLe Ma #define SDMA7_PAGE_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL 14334f727eceSLe Ma //SDMA7_PAGE_MIDCMD_DATA6 14344f727eceSLe Ma #define SDMA7_PAGE_MIDCMD_DATA6__DATA6__SHIFT 0x0 14354f727eceSLe Ma #define SDMA7_PAGE_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL 14364f727eceSLe Ma //SDMA7_PAGE_MIDCMD_DATA7 14374f727eceSLe Ma #define SDMA7_PAGE_MIDCMD_DATA7__DATA7__SHIFT 0x0 14384f727eceSLe Ma #define SDMA7_PAGE_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL 14394f727eceSLe Ma //SDMA7_PAGE_MIDCMD_DATA8 14404f727eceSLe Ma #define SDMA7_PAGE_MIDCMD_DATA8__DATA8__SHIFT 0x0 14414f727eceSLe Ma #define SDMA7_PAGE_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL 14424f727eceSLe Ma //SDMA7_PAGE_MIDCMD_CNTL 14434f727eceSLe Ma #define SDMA7_PAGE_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 14444f727eceSLe Ma #define SDMA7_PAGE_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 14454f727eceSLe Ma #define SDMA7_PAGE_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 14464f727eceSLe Ma #define SDMA7_PAGE_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 14474f727eceSLe Ma #define SDMA7_PAGE_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L 14484f727eceSLe Ma #define SDMA7_PAGE_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L 14494f727eceSLe Ma #define SDMA7_PAGE_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L 14504f727eceSLe Ma #define SDMA7_PAGE_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L 14514f727eceSLe Ma //SDMA7_RLC0_RB_CNTL 14524f727eceSLe Ma #define SDMA7_RLC0_RB_CNTL__RB_ENABLE__SHIFT 0x0 14534f727eceSLe Ma #define SDMA7_RLC0_RB_CNTL__RB_SIZE__SHIFT 0x1 14544f727eceSLe Ma #define SDMA7_RLC0_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 14554f727eceSLe Ma #define SDMA7_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc 14564f727eceSLe Ma #define SDMA7_RLC0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd 14574f727eceSLe Ma #define SDMA7_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 14584f727eceSLe Ma #define SDMA7_RLC0_RB_CNTL__RB_PRIV__SHIFT 0x17 14594f727eceSLe Ma #define SDMA7_RLC0_RB_CNTL__RB_VMID__SHIFT 0x18 14604f727eceSLe Ma #define SDMA7_RLC0_RB_CNTL__RB_ENABLE_MASK 0x00000001L 14614f727eceSLe Ma #define SDMA7_RLC0_RB_CNTL__RB_SIZE_MASK 0x0000003EL 14624f727eceSLe Ma #define SDMA7_RLC0_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L 14634f727eceSLe Ma #define SDMA7_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L 14644f727eceSLe Ma #define SDMA7_RLC0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L 14654f727eceSLe Ma #define SDMA7_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L 14664f727eceSLe Ma #define SDMA7_RLC0_RB_CNTL__RB_PRIV_MASK 0x00800000L 14674f727eceSLe Ma #define SDMA7_RLC0_RB_CNTL__RB_VMID_MASK 0x0F000000L 14684f727eceSLe Ma //SDMA7_RLC0_RB_BASE 14694f727eceSLe Ma #define SDMA7_RLC0_RB_BASE__ADDR__SHIFT 0x0 14704f727eceSLe Ma #define SDMA7_RLC0_RB_BASE__ADDR_MASK 0xFFFFFFFFL 14714f727eceSLe Ma //SDMA7_RLC0_RB_BASE_HI 14724f727eceSLe Ma #define SDMA7_RLC0_RB_BASE_HI__ADDR__SHIFT 0x0 14734f727eceSLe Ma #define SDMA7_RLC0_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL 14744f727eceSLe Ma //SDMA7_RLC0_RB_RPTR 14754f727eceSLe Ma #define SDMA7_RLC0_RB_RPTR__OFFSET__SHIFT 0x0 14764f727eceSLe Ma #define SDMA7_RLC0_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL 14774f727eceSLe Ma //SDMA7_RLC0_RB_RPTR_HI 14784f727eceSLe Ma #define SDMA7_RLC0_RB_RPTR_HI__OFFSET__SHIFT 0x0 14794f727eceSLe Ma #define SDMA7_RLC0_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL 14804f727eceSLe Ma //SDMA7_RLC0_RB_WPTR 14814f727eceSLe Ma #define SDMA7_RLC0_RB_WPTR__OFFSET__SHIFT 0x0 14824f727eceSLe Ma #define SDMA7_RLC0_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL 14834f727eceSLe Ma //SDMA7_RLC0_RB_WPTR_HI 14844f727eceSLe Ma #define SDMA7_RLC0_RB_WPTR_HI__OFFSET__SHIFT 0x0 14854f727eceSLe Ma #define SDMA7_RLC0_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL 14864f727eceSLe Ma //SDMA7_RLC0_RB_WPTR_POLL_CNTL 14874f727eceSLe Ma #define SDMA7_RLC0_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 14884f727eceSLe Ma #define SDMA7_RLC0_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 14894f727eceSLe Ma #define SDMA7_RLC0_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 14904f727eceSLe Ma #define SDMA7_RLC0_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 14914f727eceSLe Ma #define SDMA7_RLC0_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 14924f727eceSLe Ma #define SDMA7_RLC0_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L 14934f727eceSLe Ma #define SDMA7_RLC0_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L 14944f727eceSLe Ma #define SDMA7_RLC0_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L 14954f727eceSLe Ma #define SDMA7_RLC0_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L 14964f727eceSLe Ma #define SDMA7_RLC0_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L 14974f727eceSLe Ma //SDMA7_RLC0_RB_RPTR_ADDR_HI 14984f727eceSLe Ma #define SDMA7_RLC0_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 14994f727eceSLe Ma #define SDMA7_RLC0_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 15004f727eceSLe Ma //SDMA7_RLC0_RB_RPTR_ADDR_LO 15014f727eceSLe Ma #define SDMA7_RLC0_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 15024f727eceSLe Ma #define SDMA7_RLC0_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 15034f727eceSLe Ma #define SDMA7_RLC0_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L 15044f727eceSLe Ma #define SDMA7_RLC0_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 15054f727eceSLe Ma //SDMA7_RLC0_IB_CNTL 15064f727eceSLe Ma #define SDMA7_RLC0_IB_CNTL__IB_ENABLE__SHIFT 0x0 15074f727eceSLe Ma #define SDMA7_RLC0_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 15084f727eceSLe Ma #define SDMA7_RLC0_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 15094f727eceSLe Ma #define SDMA7_RLC0_IB_CNTL__CMD_VMID__SHIFT 0x10 15104f727eceSLe Ma #define SDMA7_RLC0_IB_CNTL__IB_ENABLE_MASK 0x00000001L 15114f727eceSLe Ma #define SDMA7_RLC0_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L 15124f727eceSLe Ma #define SDMA7_RLC0_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L 15134f727eceSLe Ma #define SDMA7_RLC0_IB_CNTL__CMD_VMID_MASK 0x000F0000L 15144f727eceSLe Ma //SDMA7_RLC0_IB_RPTR 15154f727eceSLe Ma #define SDMA7_RLC0_IB_RPTR__OFFSET__SHIFT 0x2 15164f727eceSLe Ma #define SDMA7_RLC0_IB_RPTR__OFFSET_MASK 0x003FFFFCL 15174f727eceSLe Ma //SDMA7_RLC0_IB_OFFSET 15184f727eceSLe Ma #define SDMA7_RLC0_IB_OFFSET__OFFSET__SHIFT 0x2 15194f727eceSLe Ma #define SDMA7_RLC0_IB_OFFSET__OFFSET_MASK 0x003FFFFCL 15204f727eceSLe Ma //SDMA7_RLC0_IB_BASE_LO 15214f727eceSLe Ma #define SDMA7_RLC0_IB_BASE_LO__ADDR__SHIFT 0x5 15224f727eceSLe Ma #define SDMA7_RLC0_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L 15234f727eceSLe Ma //SDMA7_RLC0_IB_BASE_HI 15244f727eceSLe Ma #define SDMA7_RLC0_IB_BASE_HI__ADDR__SHIFT 0x0 15254f727eceSLe Ma #define SDMA7_RLC0_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL 15264f727eceSLe Ma //SDMA7_RLC0_IB_SIZE 15274f727eceSLe Ma #define SDMA7_RLC0_IB_SIZE__SIZE__SHIFT 0x0 15284f727eceSLe Ma #define SDMA7_RLC0_IB_SIZE__SIZE_MASK 0x000FFFFFL 15294f727eceSLe Ma //SDMA7_RLC0_SKIP_CNTL 15304f727eceSLe Ma #define SDMA7_RLC0_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 15314f727eceSLe Ma #define SDMA7_RLC0_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL 15324f727eceSLe Ma //SDMA7_RLC0_CONTEXT_STATUS 15334f727eceSLe Ma #define SDMA7_RLC0_CONTEXT_STATUS__SELECTED__SHIFT 0x0 15344f727eceSLe Ma #define SDMA7_RLC0_CONTEXT_STATUS__IDLE__SHIFT 0x2 15354f727eceSLe Ma #define SDMA7_RLC0_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 15364f727eceSLe Ma #define SDMA7_RLC0_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 15374f727eceSLe Ma #define SDMA7_RLC0_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 15384f727eceSLe Ma #define SDMA7_RLC0_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 15394f727eceSLe Ma #define SDMA7_RLC0_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 15404f727eceSLe Ma #define SDMA7_RLC0_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa 15414f727eceSLe Ma #define SDMA7_RLC0_CONTEXT_STATUS__SELECTED_MASK 0x00000001L 15424f727eceSLe Ma #define SDMA7_RLC0_CONTEXT_STATUS__IDLE_MASK 0x00000004L 15434f727eceSLe Ma #define SDMA7_RLC0_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L 15444f727eceSLe Ma #define SDMA7_RLC0_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L 15454f727eceSLe Ma #define SDMA7_RLC0_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L 15464f727eceSLe Ma #define SDMA7_RLC0_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L 15474f727eceSLe Ma #define SDMA7_RLC0_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L 15484f727eceSLe Ma #define SDMA7_RLC0_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L 15494f727eceSLe Ma //SDMA7_RLC0_DOORBELL 15504f727eceSLe Ma #define SDMA7_RLC0_DOORBELL__ENABLE__SHIFT 0x1c 15514f727eceSLe Ma #define SDMA7_RLC0_DOORBELL__CAPTURED__SHIFT 0x1e 15524f727eceSLe Ma #define SDMA7_RLC0_DOORBELL__ENABLE_MASK 0x10000000L 15534f727eceSLe Ma #define SDMA7_RLC0_DOORBELL__CAPTURED_MASK 0x40000000L 15544f727eceSLe Ma //SDMA7_RLC0_STATUS 15554f727eceSLe Ma #define SDMA7_RLC0_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 15564f727eceSLe Ma #define SDMA7_RLC0_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 15574f727eceSLe Ma #define SDMA7_RLC0_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL 15584f727eceSLe Ma #define SDMA7_RLC0_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L 15594f727eceSLe Ma //SDMA7_RLC0_DOORBELL_LOG 15604f727eceSLe Ma #define SDMA7_RLC0_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 15614f727eceSLe Ma #define SDMA7_RLC0_DOORBELL_LOG__DATA__SHIFT 0x2 15624f727eceSLe Ma #define SDMA7_RLC0_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L 15634f727eceSLe Ma #define SDMA7_RLC0_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL 15644f727eceSLe Ma //SDMA7_RLC0_WATERMARK 15654f727eceSLe Ma #define SDMA7_RLC0_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 15664f727eceSLe Ma #define SDMA7_RLC0_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 15674f727eceSLe Ma #define SDMA7_RLC0_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL 15684f727eceSLe Ma #define SDMA7_RLC0_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L 15694f727eceSLe Ma //SDMA7_RLC0_DOORBELL_OFFSET 15704f727eceSLe Ma #define SDMA7_RLC0_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 15714f727eceSLe Ma #define SDMA7_RLC0_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL 15724f727eceSLe Ma //SDMA7_RLC0_CSA_ADDR_LO 15734f727eceSLe Ma #define SDMA7_RLC0_CSA_ADDR_LO__ADDR__SHIFT 0x2 15744f727eceSLe Ma #define SDMA7_RLC0_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 15754f727eceSLe Ma //SDMA7_RLC0_CSA_ADDR_HI 15764f727eceSLe Ma #define SDMA7_RLC0_CSA_ADDR_HI__ADDR__SHIFT 0x0 15774f727eceSLe Ma #define SDMA7_RLC0_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 15784f727eceSLe Ma //SDMA7_RLC0_IB_SUB_REMAIN 15794f727eceSLe Ma #define SDMA7_RLC0_IB_SUB_REMAIN__SIZE__SHIFT 0x0 15804f727eceSLe Ma #define SDMA7_RLC0_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL 15814f727eceSLe Ma //SDMA7_RLC0_PREEMPT 15824f727eceSLe Ma #define SDMA7_RLC0_PREEMPT__IB_PREEMPT__SHIFT 0x0 15834f727eceSLe Ma #define SDMA7_RLC0_PREEMPT__IB_PREEMPT_MASK 0x00000001L 15844f727eceSLe Ma //SDMA7_RLC0_DUMMY_REG 15854f727eceSLe Ma #define SDMA7_RLC0_DUMMY_REG__DUMMY__SHIFT 0x0 15864f727eceSLe Ma #define SDMA7_RLC0_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL 15874f727eceSLe Ma //SDMA7_RLC0_RB_WPTR_POLL_ADDR_HI 15884f727eceSLe Ma #define SDMA7_RLC0_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 15894f727eceSLe Ma #define SDMA7_RLC0_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 15904f727eceSLe Ma //SDMA7_RLC0_RB_WPTR_POLL_ADDR_LO 15914f727eceSLe Ma #define SDMA7_RLC0_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 15924f727eceSLe Ma #define SDMA7_RLC0_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 15934f727eceSLe Ma //SDMA7_RLC0_RB_AQL_CNTL 15944f727eceSLe Ma #define SDMA7_RLC0_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 15954f727eceSLe Ma #define SDMA7_RLC0_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 15964f727eceSLe Ma #define SDMA7_RLC0_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 15974f727eceSLe Ma #define SDMA7_RLC0_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L 15984f727eceSLe Ma #define SDMA7_RLC0_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL 15994f727eceSLe Ma #define SDMA7_RLC0_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L 16004f727eceSLe Ma //SDMA7_RLC0_MINOR_PTR_UPDATE 16014f727eceSLe Ma #define SDMA7_RLC0_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 16024f727eceSLe Ma #define SDMA7_RLC0_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L 16034f727eceSLe Ma //SDMA7_RLC0_MIDCMD_DATA0 16044f727eceSLe Ma #define SDMA7_RLC0_MIDCMD_DATA0__DATA0__SHIFT 0x0 16054f727eceSLe Ma #define SDMA7_RLC0_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL 16064f727eceSLe Ma //SDMA7_RLC0_MIDCMD_DATA1 16074f727eceSLe Ma #define SDMA7_RLC0_MIDCMD_DATA1__DATA1__SHIFT 0x0 16084f727eceSLe Ma #define SDMA7_RLC0_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL 16094f727eceSLe Ma //SDMA7_RLC0_MIDCMD_DATA2 16104f727eceSLe Ma #define SDMA7_RLC0_MIDCMD_DATA2__DATA2__SHIFT 0x0 16114f727eceSLe Ma #define SDMA7_RLC0_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL 16124f727eceSLe Ma //SDMA7_RLC0_MIDCMD_DATA3 16134f727eceSLe Ma #define SDMA7_RLC0_MIDCMD_DATA3__DATA3__SHIFT 0x0 16144f727eceSLe Ma #define SDMA7_RLC0_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL 16154f727eceSLe Ma //SDMA7_RLC0_MIDCMD_DATA4 16164f727eceSLe Ma #define SDMA7_RLC0_MIDCMD_DATA4__DATA4__SHIFT 0x0 16174f727eceSLe Ma #define SDMA7_RLC0_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL 16184f727eceSLe Ma //SDMA7_RLC0_MIDCMD_DATA5 16194f727eceSLe Ma #define SDMA7_RLC0_MIDCMD_DATA5__DATA5__SHIFT 0x0 16204f727eceSLe Ma #define SDMA7_RLC0_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL 16214f727eceSLe Ma //SDMA7_RLC0_MIDCMD_DATA6 16224f727eceSLe Ma #define SDMA7_RLC0_MIDCMD_DATA6__DATA6__SHIFT 0x0 16234f727eceSLe Ma #define SDMA7_RLC0_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL 16244f727eceSLe Ma //SDMA7_RLC0_MIDCMD_DATA7 16254f727eceSLe Ma #define SDMA7_RLC0_MIDCMD_DATA7__DATA7__SHIFT 0x0 16264f727eceSLe Ma #define SDMA7_RLC0_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL 16274f727eceSLe Ma //SDMA7_RLC0_MIDCMD_DATA8 16284f727eceSLe Ma #define SDMA7_RLC0_MIDCMD_DATA8__DATA8__SHIFT 0x0 16294f727eceSLe Ma #define SDMA7_RLC0_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL 16304f727eceSLe Ma //SDMA7_RLC0_MIDCMD_CNTL 16314f727eceSLe Ma #define SDMA7_RLC0_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 16324f727eceSLe Ma #define SDMA7_RLC0_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 16334f727eceSLe Ma #define SDMA7_RLC0_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 16344f727eceSLe Ma #define SDMA7_RLC0_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 16354f727eceSLe Ma #define SDMA7_RLC0_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L 16364f727eceSLe Ma #define SDMA7_RLC0_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L 16374f727eceSLe Ma #define SDMA7_RLC0_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L 16384f727eceSLe Ma #define SDMA7_RLC0_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L 16394f727eceSLe Ma //SDMA7_RLC1_RB_CNTL 16404f727eceSLe Ma #define SDMA7_RLC1_RB_CNTL__RB_ENABLE__SHIFT 0x0 16414f727eceSLe Ma #define SDMA7_RLC1_RB_CNTL__RB_SIZE__SHIFT 0x1 16424f727eceSLe Ma #define SDMA7_RLC1_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 16434f727eceSLe Ma #define SDMA7_RLC1_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc 16444f727eceSLe Ma #define SDMA7_RLC1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd 16454f727eceSLe Ma #define SDMA7_RLC1_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 16464f727eceSLe Ma #define SDMA7_RLC1_RB_CNTL__RB_PRIV__SHIFT 0x17 16474f727eceSLe Ma #define SDMA7_RLC1_RB_CNTL__RB_VMID__SHIFT 0x18 16484f727eceSLe Ma #define SDMA7_RLC1_RB_CNTL__RB_ENABLE_MASK 0x00000001L 16494f727eceSLe Ma #define SDMA7_RLC1_RB_CNTL__RB_SIZE_MASK 0x0000003EL 16504f727eceSLe Ma #define SDMA7_RLC1_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L 16514f727eceSLe Ma #define SDMA7_RLC1_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L 16524f727eceSLe Ma #define SDMA7_RLC1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L 16534f727eceSLe Ma #define SDMA7_RLC1_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L 16544f727eceSLe Ma #define SDMA7_RLC1_RB_CNTL__RB_PRIV_MASK 0x00800000L 16554f727eceSLe Ma #define SDMA7_RLC1_RB_CNTL__RB_VMID_MASK 0x0F000000L 16564f727eceSLe Ma //SDMA7_RLC1_RB_BASE 16574f727eceSLe Ma #define SDMA7_RLC1_RB_BASE__ADDR__SHIFT 0x0 16584f727eceSLe Ma #define SDMA7_RLC1_RB_BASE__ADDR_MASK 0xFFFFFFFFL 16594f727eceSLe Ma //SDMA7_RLC1_RB_BASE_HI 16604f727eceSLe Ma #define SDMA7_RLC1_RB_BASE_HI__ADDR__SHIFT 0x0 16614f727eceSLe Ma #define SDMA7_RLC1_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL 16624f727eceSLe Ma //SDMA7_RLC1_RB_RPTR 16634f727eceSLe Ma #define SDMA7_RLC1_RB_RPTR__OFFSET__SHIFT 0x0 16644f727eceSLe Ma #define SDMA7_RLC1_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL 16654f727eceSLe Ma //SDMA7_RLC1_RB_RPTR_HI 16664f727eceSLe Ma #define SDMA7_RLC1_RB_RPTR_HI__OFFSET__SHIFT 0x0 16674f727eceSLe Ma #define SDMA7_RLC1_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL 16684f727eceSLe Ma //SDMA7_RLC1_RB_WPTR 16694f727eceSLe Ma #define SDMA7_RLC1_RB_WPTR__OFFSET__SHIFT 0x0 16704f727eceSLe Ma #define SDMA7_RLC1_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL 16714f727eceSLe Ma //SDMA7_RLC1_RB_WPTR_HI 16724f727eceSLe Ma #define SDMA7_RLC1_RB_WPTR_HI__OFFSET__SHIFT 0x0 16734f727eceSLe Ma #define SDMA7_RLC1_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL 16744f727eceSLe Ma //SDMA7_RLC1_RB_WPTR_POLL_CNTL 16754f727eceSLe Ma #define SDMA7_RLC1_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 16764f727eceSLe Ma #define SDMA7_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 16774f727eceSLe Ma #define SDMA7_RLC1_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 16784f727eceSLe Ma #define SDMA7_RLC1_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 16794f727eceSLe Ma #define SDMA7_RLC1_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 16804f727eceSLe Ma #define SDMA7_RLC1_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L 16814f727eceSLe Ma #define SDMA7_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L 16824f727eceSLe Ma #define SDMA7_RLC1_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L 16834f727eceSLe Ma #define SDMA7_RLC1_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L 16844f727eceSLe Ma #define SDMA7_RLC1_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L 16854f727eceSLe Ma //SDMA7_RLC1_RB_RPTR_ADDR_HI 16864f727eceSLe Ma #define SDMA7_RLC1_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 16874f727eceSLe Ma #define SDMA7_RLC1_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 16884f727eceSLe Ma //SDMA7_RLC1_RB_RPTR_ADDR_LO 16894f727eceSLe Ma #define SDMA7_RLC1_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 16904f727eceSLe Ma #define SDMA7_RLC1_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 16914f727eceSLe Ma #define SDMA7_RLC1_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L 16924f727eceSLe Ma #define SDMA7_RLC1_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 16934f727eceSLe Ma //SDMA7_RLC1_IB_CNTL 16944f727eceSLe Ma #define SDMA7_RLC1_IB_CNTL__IB_ENABLE__SHIFT 0x0 16954f727eceSLe Ma #define SDMA7_RLC1_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 16964f727eceSLe Ma #define SDMA7_RLC1_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 16974f727eceSLe Ma #define SDMA7_RLC1_IB_CNTL__CMD_VMID__SHIFT 0x10 16984f727eceSLe Ma #define SDMA7_RLC1_IB_CNTL__IB_ENABLE_MASK 0x00000001L 16994f727eceSLe Ma #define SDMA7_RLC1_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L 17004f727eceSLe Ma #define SDMA7_RLC1_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L 17014f727eceSLe Ma #define SDMA7_RLC1_IB_CNTL__CMD_VMID_MASK 0x000F0000L 17024f727eceSLe Ma //SDMA7_RLC1_IB_RPTR 17034f727eceSLe Ma #define SDMA7_RLC1_IB_RPTR__OFFSET__SHIFT 0x2 17044f727eceSLe Ma #define SDMA7_RLC1_IB_RPTR__OFFSET_MASK 0x003FFFFCL 17054f727eceSLe Ma //SDMA7_RLC1_IB_OFFSET 17064f727eceSLe Ma #define SDMA7_RLC1_IB_OFFSET__OFFSET__SHIFT 0x2 17074f727eceSLe Ma #define SDMA7_RLC1_IB_OFFSET__OFFSET_MASK 0x003FFFFCL 17084f727eceSLe Ma //SDMA7_RLC1_IB_BASE_LO 17094f727eceSLe Ma #define SDMA7_RLC1_IB_BASE_LO__ADDR__SHIFT 0x5 17104f727eceSLe Ma #define SDMA7_RLC1_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L 17114f727eceSLe Ma //SDMA7_RLC1_IB_BASE_HI 17124f727eceSLe Ma #define SDMA7_RLC1_IB_BASE_HI__ADDR__SHIFT 0x0 17134f727eceSLe Ma #define SDMA7_RLC1_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL 17144f727eceSLe Ma //SDMA7_RLC1_IB_SIZE 17154f727eceSLe Ma #define SDMA7_RLC1_IB_SIZE__SIZE__SHIFT 0x0 17164f727eceSLe Ma #define SDMA7_RLC1_IB_SIZE__SIZE_MASK 0x000FFFFFL 17174f727eceSLe Ma //SDMA7_RLC1_SKIP_CNTL 17184f727eceSLe Ma #define SDMA7_RLC1_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 17194f727eceSLe Ma #define SDMA7_RLC1_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL 17204f727eceSLe Ma //SDMA7_RLC1_CONTEXT_STATUS 17214f727eceSLe Ma #define SDMA7_RLC1_CONTEXT_STATUS__SELECTED__SHIFT 0x0 17224f727eceSLe Ma #define SDMA7_RLC1_CONTEXT_STATUS__IDLE__SHIFT 0x2 17234f727eceSLe Ma #define SDMA7_RLC1_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 17244f727eceSLe Ma #define SDMA7_RLC1_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 17254f727eceSLe Ma #define SDMA7_RLC1_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 17264f727eceSLe Ma #define SDMA7_RLC1_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 17274f727eceSLe Ma #define SDMA7_RLC1_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 17284f727eceSLe Ma #define SDMA7_RLC1_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa 17294f727eceSLe Ma #define SDMA7_RLC1_CONTEXT_STATUS__SELECTED_MASK 0x00000001L 17304f727eceSLe Ma #define SDMA7_RLC1_CONTEXT_STATUS__IDLE_MASK 0x00000004L 17314f727eceSLe Ma #define SDMA7_RLC1_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L 17324f727eceSLe Ma #define SDMA7_RLC1_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L 17334f727eceSLe Ma #define SDMA7_RLC1_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L 17344f727eceSLe Ma #define SDMA7_RLC1_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L 17354f727eceSLe Ma #define SDMA7_RLC1_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L 17364f727eceSLe Ma #define SDMA7_RLC1_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L 17374f727eceSLe Ma //SDMA7_RLC1_DOORBELL 17384f727eceSLe Ma #define SDMA7_RLC1_DOORBELL__ENABLE__SHIFT 0x1c 17394f727eceSLe Ma #define SDMA7_RLC1_DOORBELL__CAPTURED__SHIFT 0x1e 17404f727eceSLe Ma #define SDMA7_RLC1_DOORBELL__ENABLE_MASK 0x10000000L 17414f727eceSLe Ma #define SDMA7_RLC1_DOORBELL__CAPTURED_MASK 0x40000000L 17424f727eceSLe Ma //SDMA7_RLC1_STATUS 17434f727eceSLe Ma #define SDMA7_RLC1_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 17444f727eceSLe Ma #define SDMA7_RLC1_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 17454f727eceSLe Ma #define SDMA7_RLC1_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL 17464f727eceSLe Ma #define SDMA7_RLC1_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L 17474f727eceSLe Ma //SDMA7_RLC1_DOORBELL_LOG 17484f727eceSLe Ma #define SDMA7_RLC1_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 17494f727eceSLe Ma #define SDMA7_RLC1_DOORBELL_LOG__DATA__SHIFT 0x2 17504f727eceSLe Ma #define SDMA7_RLC1_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L 17514f727eceSLe Ma #define SDMA7_RLC1_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL 17524f727eceSLe Ma //SDMA7_RLC1_WATERMARK 17534f727eceSLe Ma #define SDMA7_RLC1_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 17544f727eceSLe Ma #define SDMA7_RLC1_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 17554f727eceSLe Ma #define SDMA7_RLC1_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL 17564f727eceSLe Ma #define SDMA7_RLC1_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L 17574f727eceSLe Ma //SDMA7_RLC1_DOORBELL_OFFSET 17584f727eceSLe Ma #define SDMA7_RLC1_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 17594f727eceSLe Ma #define SDMA7_RLC1_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL 17604f727eceSLe Ma //SDMA7_RLC1_CSA_ADDR_LO 17614f727eceSLe Ma #define SDMA7_RLC1_CSA_ADDR_LO__ADDR__SHIFT 0x2 17624f727eceSLe Ma #define SDMA7_RLC1_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 17634f727eceSLe Ma //SDMA7_RLC1_CSA_ADDR_HI 17644f727eceSLe Ma #define SDMA7_RLC1_CSA_ADDR_HI__ADDR__SHIFT 0x0 17654f727eceSLe Ma #define SDMA7_RLC1_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 17664f727eceSLe Ma //SDMA7_RLC1_IB_SUB_REMAIN 17674f727eceSLe Ma #define SDMA7_RLC1_IB_SUB_REMAIN__SIZE__SHIFT 0x0 17684f727eceSLe Ma #define SDMA7_RLC1_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL 17694f727eceSLe Ma //SDMA7_RLC1_PREEMPT 17704f727eceSLe Ma #define SDMA7_RLC1_PREEMPT__IB_PREEMPT__SHIFT 0x0 17714f727eceSLe Ma #define SDMA7_RLC1_PREEMPT__IB_PREEMPT_MASK 0x00000001L 17724f727eceSLe Ma //SDMA7_RLC1_DUMMY_REG 17734f727eceSLe Ma #define SDMA7_RLC1_DUMMY_REG__DUMMY__SHIFT 0x0 17744f727eceSLe Ma #define SDMA7_RLC1_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL 17754f727eceSLe Ma //SDMA7_RLC1_RB_WPTR_POLL_ADDR_HI 17764f727eceSLe Ma #define SDMA7_RLC1_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 17774f727eceSLe Ma #define SDMA7_RLC1_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 17784f727eceSLe Ma //SDMA7_RLC1_RB_WPTR_POLL_ADDR_LO 17794f727eceSLe Ma #define SDMA7_RLC1_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 17804f727eceSLe Ma #define SDMA7_RLC1_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 17814f727eceSLe Ma //SDMA7_RLC1_RB_AQL_CNTL 17824f727eceSLe Ma #define SDMA7_RLC1_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 17834f727eceSLe Ma #define SDMA7_RLC1_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 17844f727eceSLe Ma #define SDMA7_RLC1_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 17854f727eceSLe Ma #define SDMA7_RLC1_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L 17864f727eceSLe Ma #define SDMA7_RLC1_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL 17874f727eceSLe Ma #define SDMA7_RLC1_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L 17884f727eceSLe Ma //SDMA7_RLC1_MINOR_PTR_UPDATE 17894f727eceSLe Ma #define SDMA7_RLC1_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 17904f727eceSLe Ma #define SDMA7_RLC1_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L 17914f727eceSLe Ma //SDMA7_RLC1_MIDCMD_DATA0 17924f727eceSLe Ma #define SDMA7_RLC1_MIDCMD_DATA0__DATA0__SHIFT 0x0 17934f727eceSLe Ma #define SDMA7_RLC1_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL 17944f727eceSLe Ma //SDMA7_RLC1_MIDCMD_DATA1 17954f727eceSLe Ma #define SDMA7_RLC1_MIDCMD_DATA1__DATA1__SHIFT 0x0 17964f727eceSLe Ma #define SDMA7_RLC1_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL 17974f727eceSLe Ma //SDMA7_RLC1_MIDCMD_DATA2 17984f727eceSLe Ma #define SDMA7_RLC1_MIDCMD_DATA2__DATA2__SHIFT 0x0 17994f727eceSLe Ma #define SDMA7_RLC1_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL 18004f727eceSLe Ma //SDMA7_RLC1_MIDCMD_DATA3 18014f727eceSLe Ma #define SDMA7_RLC1_MIDCMD_DATA3__DATA3__SHIFT 0x0 18024f727eceSLe Ma #define SDMA7_RLC1_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL 18034f727eceSLe Ma //SDMA7_RLC1_MIDCMD_DATA4 18044f727eceSLe Ma #define SDMA7_RLC1_MIDCMD_DATA4__DATA4__SHIFT 0x0 18054f727eceSLe Ma #define SDMA7_RLC1_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL 18064f727eceSLe Ma //SDMA7_RLC1_MIDCMD_DATA5 18074f727eceSLe Ma #define SDMA7_RLC1_MIDCMD_DATA5__DATA5__SHIFT 0x0 18084f727eceSLe Ma #define SDMA7_RLC1_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL 18094f727eceSLe Ma //SDMA7_RLC1_MIDCMD_DATA6 18104f727eceSLe Ma #define SDMA7_RLC1_MIDCMD_DATA6__DATA6__SHIFT 0x0 18114f727eceSLe Ma #define SDMA7_RLC1_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL 18124f727eceSLe Ma //SDMA7_RLC1_MIDCMD_DATA7 18134f727eceSLe Ma #define SDMA7_RLC1_MIDCMD_DATA7__DATA7__SHIFT 0x0 18144f727eceSLe Ma #define SDMA7_RLC1_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL 18154f727eceSLe Ma //SDMA7_RLC1_MIDCMD_DATA8 18164f727eceSLe Ma #define SDMA7_RLC1_MIDCMD_DATA8__DATA8__SHIFT 0x0 18174f727eceSLe Ma #define SDMA7_RLC1_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL 18184f727eceSLe Ma //SDMA7_RLC1_MIDCMD_CNTL 18194f727eceSLe Ma #define SDMA7_RLC1_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 18204f727eceSLe Ma #define SDMA7_RLC1_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 18214f727eceSLe Ma #define SDMA7_RLC1_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 18224f727eceSLe Ma #define SDMA7_RLC1_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 18234f727eceSLe Ma #define SDMA7_RLC1_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L 18244f727eceSLe Ma #define SDMA7_RLC1_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L 18254f727eceSLe Ma #define SDMA7_RLC1_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L 18264f727eceSLe Ma #define SDMA7_RLC1_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L 18274f727eceSLe Ma //SDMA7_RLC2_RB_CNTL 18284f727eceSLe Ma #define SDMA7_RLC2_RB_CNTL__RB_ENABLE__SHIFT 0x0 18294f727eceSLe Ma #define SDMA7_RLC2_RB_CNTL__RB_SIZE__SHIFT 0x1 18304f727eceSLe Ma #define SDMA7_RLC2_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 18314f727eceSLe Ma #define SDMA7_RLC2_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc 18324f727eceSLe Ma #define SDMA7_RLC2_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd 18334f727eceSLe Ma #define SDMA7_RLC2_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 18344f727eceSLe Ma #define SDMA7_RLC2_RB_CNTL__RB_PRIV__SHIFT 0x17 18354f727eceSLe Ma #define SDMA7_RLC2_RB_CNTL__RB_VMID__SHIFT 0x18 18364f727eceSLe Ma #define SDMA7_RLC2_RB_CNTL__RB_ENABLE_MASK 0x00000001L 18374f727eceSLe Ma #define SDMA7_RLC2_RB_CNTL__RB_SIZE_MASK 0x0000003EL 18384f727eceSLe Ma #define SDMA7_RLC2_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L 18394f727eceSLe Ma #define SDMA7_RLC2_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L 18404f727eceSLe Ma #define SDMA7_RLC2_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L 18414f727eceSLe Ma #define SDMA7_RLC2_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L 18424f727eceSLe Ma #define SDMA7_RLC2_RB_CNTL__RB_PRIV_MASK 0x00800000L 18434f727eceSLe Ma #define SDMA7_RLC2_RB_CNTL__RB_VMID_MASK 0x0F000000L 18444f727eceSLe Ma //SDMA7_RLC2_RB_BASE 18454f727eceSLe Ma #define SDMA7_RLC2_RB_BASE__ADDR__SHIFT 0x0 18464f727eceSLe Ma #define SDMA7_RLC2_RB_BASE__ADDR_MASK 0xFFFFFFFFL 18474f727eceSLe Ma //SDMA7_RLC2_RB_BASE_HI 18484f727eceSLe Ma #define SDMA7_RLC2_RB_BASE_HI__ADDR__SHIFT 0x0 18494f727eceSLe Ma #define SDMA7_RLC2_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL 18504f727eceSLe Ma //SDMA7_RLC2_RB_RPTR 18514f727eceSLe Ma #define SDMA7_RLC2_RB_RPTR__OFFSET__SHIFT 0x0 18524f727eceSLe Ma #define SDMA7_RLC2_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL 18534f727eceSLe Ma //SDMA7_RLC2_RB_RPTR_HI 18544f727eceSLe Ma #define SDMA7_RLC2_RB_RPTR_HI__OFFSET__SHIFT 0x0 18554f727eceSLe Ma #define SDMA7_RLC2_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL 18564f727eceSLe Ma //SDMA7_RLC2_RB_WPTR 18574f727eceSLe Ma #define SDMA7_RLC2_RB_WPTR__OFFSET__SHIFT 0x0 18584f727eceSLe Ma #define SDMA7_RLC2_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL 18594f727eceSLe Ma //SDMA7_RLC2_RB_WPTR_HI 18604f727eceSLe Ma #define SDMA7_RLC2_RB_WPTR_HI__OFFSET__SHIFT 0x0 18614f727eceSLe Ma #define SDMA7_RLC2_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL 18624f727eceSLe Ma //SDMA7_RLC2_RB_WPTR_POLL_CNTL 18634f727eceSLe Ma #define SDMA7_RLC2_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 18644f727eceSLe Ma #define SDMA7_RLC2_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 18654f727eceSLe Ma #define SDMA7_RLC2_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 18664f727eceSLe Ma #define SDMA7_RLC2_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 18674f727eceSLe Ma #define SDMA7_RLC2_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 18684f727eceSLe Ma #define SDMA7_RLC2_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L 18694f727eceSLe Ma #define SDMA7_RLC2_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L 18704f727eceSLe Ma #define SDMA7_RLC2_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L 18714f727eceSLe Ma #define SDMA7_RLC2_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L 18724f727eceSLe Ma #define SDMA7_RLC2_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L 18734f727eceSLe Ma //SDMA7_RLC2_RB_RPTR_ADDR_HI 18744f727eceSLe Ma #define SDMA7_RLC2_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 18754f727eceSLe Ma #define SDMA7_RLC2_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 18764f727eceSLe Ma //SDMA7_RLC2_RB_RPTR_ADDR_LO 18774f727eceSLe Ma #define SDMA7_RLC2_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 18784f727eceSLe Ma #define SDMA7_RLC2_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 18794f727eceSLe Ma #define SDMA7_RLC2_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L 18804f727eceSLe Ma #define SDMA7_RLC2_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 18814f727eceSLe Ma //SDMA7_RLC2_IB_CNTL 18824f727eceSLe Ma #define SDMA7_RLC2_IB_CNTL__IB_ENABLE__SHIFT 0x0 18834f727eceSLe Ma #define SDMA7_RLC2_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 18844f727eceSLe Ma #define SDMA7_RLC2_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 18854f727eceSLe Ma #define SDMA7_RLC2_IB_CNTL__CMD_VMID__SHIFT 0x10 18864f727eceSLe Ma #define SDMA7_RLC2_IB_CNTL__IB_ENABLE_MASK 0x00000001L 18874f727eceSLe Ma #define SDMA7_RLC2_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L 18884f727eceSLe Ma #define SDMA7_RLC2_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L 18894f727eceSLe Ma #define SDMA7_RLC2_IB_CNTL__CMD_VMID_MASK 0x000F0000L 18904f727eceSLe Ma //SDMA7_RLC2_IB_RPTR 18914f727eceSLe Ma #define SDMA7_RLC2_IB_RPTR__OFFSET__SHIFT 0x2 18924f727eceSLe Ma #define SDMA7_RLC2_IB_RPTR__OFFSET_MASK 0x003FFFFCL 18934f727eceSLe Ma //SDMA7_RLC2_IB_OFFSET 18944f727eceSLe Ma #define SDMA7_RLC2_IB_OFFSET__OFFSET__SHIFT 0x2 18954f727eceSLe Ma #define SDMA7_RLC2_IB_OFFSET__OFFSET_MASK 0x003FFFFCL 18964f727eceSLe Ma //SDMA7_RLC2_IB_BASE_LO 18974f727eceSLe Ma #define SDMA7_RLC2_IB_BASE_LO__ADDR__SHIFT 0x5 18984f727eceSLe Ma #define SDMA7_RLC2_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L 18994f727eceSLe Ma //SDMA7_RLC2_IB_BASE_HI 19004f727eceSLe Ma #define SDMA7_RLC2_IB_BASE_HI__ADDR__SHIFT 0x0 19014f727eceSLe Ma #define SDMA7_RLC2_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL 19024f727eceSLe Ma //SDMA7_RLC2_IB_SIZE 19034f727eceSLe Ma #define SDMA7_RLC2_IB_SIZE__SIZE__SHIFT 0x0 19044f727eceSLe Ma #define SDMA7_RLC2_IB_SIZE__SIZE_MASK 0x000FFFFFL 19054f727eceSLe Ma //SDMA7_RLC2_SKIP_CNTL 19064f727eceSLe Ma #define SDMA7_RLC2_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 19074f727eceSLe Ma #define SDMA7_RLC2_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL 19084f727eceSLe Ma //SDMA7_RLC2_CONTEXT_STATUS 19094f727eceSLe Ma #define SDMA7_RLC2_CONTEXT_STATUS__SELECTED__SHIFT 0x0 19104f727eceSLe Ma #define SDMA7_RLC2_CONTEXT_STATUS__IDLE__SHIFT 0x2 19114f727eceSLe Ma #define SDMA7_RLC2_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 19124f727eceSLe Ma #define SDMA7_RLC2_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 19134f727eceSLe Ma #define SDMA7_RLC2_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 19144f727eceSLe Ma #define SDMA7_RLC2_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 19154f727eceSLe Ma #define SDMA7_RLC2_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 19164f727eceSLe Ma #define SDMA7_RLC2_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa 19174f727eceSLe Ma #define SDMA7_RLC2_CONTEXT_STATUS__SELECTED_MASK 0x00000001L 19184f727eceSLe Ma #define SDMA7_RLC2_CONTEXT_STATUS__IDLE_MASK 0x00000004L 19194f727eceSLe Ma #define SDMA7_RLC2_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L 19204f727eceSLe Ma #define SDMA7_RLC2_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L 19214f727eceSLe Ma #define SDMA7_RLC2_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L 19224f727eceSLe Ma #define SDMA7_RLC2_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L 19234f727eceSLe Ma #define SDMA7_RLC2_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L 19244f727eceSLe Ma #define SDMA7_RLC2_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L 19254f727eceSLe Ma //SDMA7_RLC2_DOORBELL 19264f727eceSLe Ma #define SDMA7_RLC2_DOORBELL__ENABLE__SHIFT 0x1c 19274f727eceSLe Ma #define SDMA7_RLC2_DOORBELL__CAPTURED__SHIFT 0x1e 19284f727eceSLe Ma #define SDMA7_RLC2_DOORBELL__ENABLE_MASK 0x10000000L 19294f727eceSLe Ma #define SDMA7_RLC2_DOORBELL__CAPTURED_MASK 0x40000000L 19304f727eceSLe Ma //SDMA7_RLC2_STATUS 19314f727eceSLe Ma #define SDMA7_RLC2_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 19324f727eceSLe Ma #define SDMA7_RLC2_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 19334f727eceSLe Ma #define SDMA7_RLC2_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL 19344f727eceSLe Ma #define SDMA7_RLC2_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L 19354f727eceSLe Ma //SDMA7_RLC2_DOORBELL_LOG 19364f727eceSLe Ma #define SDMA7_RLC2_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 19374f727eceSLe Ma #define SDMA7_RLC2_DOORBELL_LOG__DATA__SHIFT 0x2 19384f727eceSLe Ma #define SDMA7_RLC2_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L 19394f727eceSLe Ma #define SDMA7_RLC2_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL 19404f727eceSLe Ma //SDMA7_RLC2_WATERMARK 19414f727eceSLe Ma #define SDMA7_RLC2_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 19424f727eceSLe Ma #define SDMA7_RLC2_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 19434f727eceSLe Ma #define SDMA7_RLC2_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL 19444f727eceSLe Ma #define SDMA7_RLC2_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L 19454f727eceSLe Ma //SDMA7_RLC2_DOORBELL_OFFSET 19464f727eceSLe Ma #define SDMA7_RLC2_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 19474f727eceSLe Ma #define SDMA7_RLC2_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL 19484f727eceSLe Ma //SDMA7_RLC2_CSA_ADDR_LO 19494f727eceSLe Ma #define SDMA7_RLC2_CSA_ADDR_LO__ADDR__SHIFT 0x2 19504f727eceSLe Ma #define SDMA7_RLC2_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 19514f727eceSLe Ma //SDMA7_RLC2_CSA_ADDR_HI 19524f727eceSLe Ma #define SDMA7_RLC2_CSA_ADDR_HI__ADDR__SHIFT 0x0 19534f727eceSLe Ma #define SDMA7_RLC2_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 19544f727eceSLe Ma //SDMA7_RLC2_IB_SUB_REMAIN 19554f727eceSLe Ma #define SDMA7_RLC2_IB_SUB_REMAIN__SIZE__SHIFT 0x0 19564f727eceSLe Ma #define SDMA7_RLC2_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL 19574f727eceSLe Ma //SDMA7_RLC2_PREEMPT 19584f727eceSLe Ma #define SDMA7_RLC2_PREEMPT__IB_PREEMPT__SHIFT 0x0 19594f727eceSLe Ma #define SDMA7_RLC2_PREEMPT__IB_PREEMPT_MASK 0x00000001L 19604f727eceSLe Ma //SDMA7_RLC2_DUMMY_REG 19614f727eceSLe Ma #define SDMA7_RLC2_DUMMY_REG__DUMMY__SHIFT 0x0 19624f727eceSLe Ma #define SDMA7_RLC2_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL 19634f727eceSLe Ma //SDMA7_RLC2_RB_WPTR_POLL_ADDR_HI 19644f727eceSLe Ma #define SDMA7_RLC2_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 19654f727eceSLe Ma #define SDMA7_RLC2_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 19664f727eceSLe Ma //SDMA7_RLC2_RB_WPTR_POLL_ADDR_LO 19674f727eceSLe Ma #define SDMA7_RLC2_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 19684f727eceSLe Ma #define SDMA7_RLC2_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 19694f727eceSLe Ma //SDMA7_RLC2_RB_AQL_CNTL 19704f727eceSLe Ma #define SDMA7_RLC2_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 19714f727eceSLe Ma #define SDMA7_RLC2_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 19724f727eceSLe Ma #define SDMA7_RLC2_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 19734f727eceSLe Ma #define SDMA7_RLC2_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L 19744f727eceSLe Ma #define SDMA7_RLC2_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL 19754f727eceSLe Ma #define SDMA7_RLC2_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L 19764f727eceSLe Ma //SDMA7_RLC2_MINOR_PTR_UPDATE 19774f727eceSLe Ma #define SDMA7_RLC2_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 19784f727eceSLe Ma #define SDMA7_RLC2_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L 19794f727eceSLe Ma //SDMA7_RLC2_MIDCMD_DATA0 19804f727eceSLe Ma #define SDMA7_RLC2_MIDCMD_DATA0__DATA0__SHIFT 0x0 19814f727eceSLe Ma #define SDMA7_RLC2_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL 19824f727eceSLe Ma //SDMA7_RLC2_MIDCMD_DATA1 19834f727eceSLe Ma #define SDMA7_RLC2_MIDCMD_DATA1__DATA1__SHIFT 0x0 19844f727eceSLe Ma #define SDMA7_RLC2_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL 19854f727eceSLe Ma //SDMA7_RLC2_MIDCMD_DATA2 19864f727eceSLe Ma #define SDMA7_RLC2_MIDCMD_DATA2__DATA2__SHIFT 0x0 19874f727eceSLe Ma #define SDMA7_RLC2_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL 19884f727eceSLe Ma //SDMA7_RLC2_MIDCMD_DATA3 19894f727eceSLe Ma #define SDMA7_RLC2_MIDCMD_DATA3__DATA3__SHIFT 0x0 19904f727eceSLe Ma #define SDMA7_RLC2_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL 19914f727eceSLe Ma //SDMA7_RLC2_MIDCMD_DATA4 19924f727eceSLe Ma #define SDMA7_RLC2_MIDCMD_DATA4__DATA4__SHIFT 0x0 19934f727eceSLe Ma #define SDMA7_RLC2_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL 19944f727eceSLe Ma //SDMA7_RLC2_MIDCMD_DATA5 19954f727eceSLe Ma #define SDMA7_RLC2_MIDCMD_DATA5__DATA5__SHIFT 0x0 19964f727eceSLe Ma #define SDMA7_RLC2_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL 19974f727eceSLe Ma //SDMA7_RLC2_MIDCMD_DATA6 19984f727eceSLe Ma #define SDMA7_RLC2_MIDCMD_DATA6__DATA6__SHIFT 0x0 19994f727eceSLe Ma #define SDMA7_RLC2_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL 20004f727eceSLe Ma //SDMA7_RLC2_MIDCMD_DATA7 20014f727eceSLe Ma #define SDMA7_RLC2_MIDCMD_DATA7__DATA7__SHIFT 0x0 20024f727eceSLe Ma #define SDMA7_RLC2_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL 20034f727eceSLe Ma //SDMA7_RLC2_MIDCMD_DATA8 20044f727eceSLe Ma #define SDMA7_RLC2_MIDCMD_DATA8__DATA8__SHIFT 0x0 20054f727eceSLe Ma #define SDMA7_RLC2_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL 20064f727eceSLe Ma //SDMA7_RLC2_MIDCMD_CNTL 20074f727eceSLe Ma #define SDMA7_RLC2_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 20084f727eceSLe Ma #define SDMA7_RLC2_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 20094f727eceSLe Ma #define SDMA7_RLC2_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 20104f727eceSLe Ma #define SDMA7_RLC2_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 20114f727eceSLe Ma #define SDMA7_RLC2_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L 20124f727eceSLe Ma #define SDMA7_RLC2_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L 20134f727eceSLe Ma #define SDMA7_RLC2_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L 20144f727eceSLe Ma #define SDMA7_RLC2_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L 20154f727eceSLe Ma //SDMA7_RLC3_RB_CNTL 20164f727eceSLe Ma #define SDMA7_RLC3_RB_CNTL__RB_ENABLE__SHIFT 0x0 20174f727eceSLe Ma #define SDMA7_RLC3_RB_CNTL__RB_SIZE__SHIFT 0x1 20184f727eceSLe Ma #define SDMA7_RLC3_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 20194f727eceSLe Ma #define SDMA7_RLC3_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc 20204f727eceSLe Ma #define SDMA7_RLC3_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd 20214f727eceSLe Ma #define SDMA7_RLC3_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 20224f727eceSLe Ma #define SDMA7_RLC3_RB_CNTL__RB_PRIV__SHIFT 0x17 20234f727eceSLe Ma #define SDMA7_RLC3_RB_CNTL__RB_VMID__SHIFT 0x18 20244f727eceSLe Ma #define SDMA7_RLC3_RB_CNTL__RB_ENABLE_MASK 0x00000001L 20254f727eceSLe Ma #define SDMA7_RLC3_RB_CNTL__RB_SIZE_MASK 0x0000003EL 20264f727eceSLe Ma #define SDMA7_RLC3_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L 20274f727eceSLe Ma #define SDMA7_RLC3_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L 20284f727eceSLe Ma #define SDMA7_RLC3_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L 20294f727eceSLe Ma #define SDMA7_RLC3_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L 20304f727eceSLe Ma #define SDMA7_RLC3_RB_CNTL__RB_PRIV_MASK 0x00800000L 20314f727eceSLe Ma #define SDMA7_RLC3_RB_CNTL__RB_VMID_MASK 0x0F000000L 20324f727eceSLe Ma //SDMA7_RLC3_RB_BASE 20334f727eceSLe Ma #define SDMA7_RLC3_RB_BASE__ADDR__SHIFT 0x0 20344f727eceSLe Ma #define SDMA7_RLC3_RB_BASE__ADDR_MASK 0xFFFFFFFFL 20354f727eceSLe Ma //SDMA7_RLC3_RB_BASE_HI 20364f727eceSLe Ma #define SDMA7_RLC3_RB_BASE_HI__ADDR__SHIFT 0x0 20374f727eceSLe Ma #define SDMA7_RLC3_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL 20384f727eceSLe Ma //SDMA7_RLC3_RB_RPTR 20394f727eceSLe Ma #define SDMA7_RLC3_RB_RPTR__OFFSET__SHIFT 0x0 20404f727eceSLe Ma #define SDMA7_RLC3_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL 20414f727eceSLe Ma //SDMA7_RLC3_RB_RPTR_HI 20424f727eceSLe Ma #define SDMA7_RLC3_RB_RPTR_HI__OFFSET__SHIFT 0x0 20434f727eceSLe Ma #define SDMA7_RLC3_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL 20444f727eceSLe Ma //SDMA7_RLC3_RB_WPTR 20454f727eceSLe Ma #define SDMA7_RLC3_RB_WPTR__OFFSET__SHIFT 0x0 20464f727eceSLe Ma #define SDMA7_RLC3_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL 20474f727eceSLe Ma //SDMA7_RLC3_RB_WPTR_HI 20484f727eceSLe Ma #define SDMA7_RLC3_RB_WPTR_HI__OFFSET__SHIFT 0x0 20494f727eceSLe Ma #define SDMA7_RLC3_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL 20504f727eceSLe Ma //SDMA7_RLC3_RB_WPTR_POLL_CNTL 20514f727eceSLe Ma #define SDMA7_RLC3_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 20524f727eceSLe Ma #define SDMA7_RLC3_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 20534f727eceSLe Ma #define SDMA7_RLC3_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 20544f727eceSLe Ma #define SDMA7_RLC3_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 20554f727eceSLe Ma #define SDMA7_RLC3_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 20564f727eceSLe Ma #define SDMA7_RLC3_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L 20574f727eceSLe Ma #define SDMA7_RLC3_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L 20584f727eceSLe Ma #define SDMA7_RLC3_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L 20594f727eceSLe Ma #define SDMA7_RLC3_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L 20604f727eceSLe Ma #define SDMA7_RLC3_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L 20614f727eceSLe Ma //SDMA7_RLC3_RB_RPTR_ADDR_HI 20624f727eceSLe Ma #define SDMA7_RLC3_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 20634f727eceSLe Ma #define SDMA7_RLC3_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 20644f727eceSLe Ma //SDMA7_RLC3_RB_RPTR_ADDR_LO 20654f727eceSLe Ma #define SDMA7_RLC3_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 20664f727eceSLe Ma #define SDMA7_RLC3_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 20674f727eceSLe Ma #define SDMA7_RLC3_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L 20684f727eceSLe Ma #define SDMA7_RLC3_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 20694f727eceSLe Ma //SDMA7_RLC3_IB_CNTL 20704f727eceSLe Ma #define SDMA7_RLC3_IB_CNTL__IB_ENABLE__SHIFT 0x0 20714f727eceSLe Ma #define SDMA7_RLC3_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 20724f727eceSLe Ma #define SDMA7_RLC3_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 20734f727eceSLe Ma #define SDMA7_RLC3_IB_CNTL__CMD_VMID__SHIFT 0x10 20744f727eceSLe Ma #define SDMA7_RLC3_IB_CNTL__IB_ENABLE_MASK 0x00000001L 20754f727eceSLe Ma #define SDMA7_RLC3_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L 20764f727eceSLe Ma #define SDMA7_RLC3_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L 20774f727eceSLe Ma #define SDMA7_RLC3_IB_CNTL__CMD_VMID_MASK 0x000F0000L 20784f727eceSLe Ma //SDMA7_RLC3_IB_RPTR 20794f727eceSLe Ma #define SDMA7_RLC3_IB_RPTR__OFFSET__SHIFT 0x2 20804f727eceSLe Ma #define SDMA7_RLC3_IB_RPTR__OFFSET_MASK 0x003FFFFCL 20814f727eceSLe Ma //SDMA7_RLC3_IB_OFFSET 20824f727eceSLe Ma #define SDMA7_RLC3_IB_OFFSET__OFFSET__SHIFT 0x2 20834f727eceSLe Ma #define SDMA7_RLC3_IB_OFFSET__OFFSET_MASK 0x003FFFFCL 20844f727eceSLe Ma //SDMA7_RLC3_IB_BASE_LO 20854f727eceSLe Ma #define SDMA7_RLC3_IB_BASE_LO__ADDR__SHIFT 0x5 20864f727eceSLe Ma #define SDMA7_RLC3_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L 20874f727eceSLe Ma //SDMA7_RLC3_IB_BASE_HI 20884f727eceSLe Ma #define SDMA7_RLC3_IB_BASE_HI__ADDR__SHIFT 0x0 20894f727eceSLe Ma #define SDMA7_RLC3_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL 20904f727eceSLe Ma //SDMA7_RLC3_IB_SIZE 20914f727eceSLe Ma #define SDMA7_RLC3_IB_SIZE__SIZE__SHIFT 0x0 20924f727eceSLe Ma #define SDMA7_RLC3_IB_SIZE__SIZE_MASK 0x000FFFFFL 20934f727eceSLe Ma //SDMA7_RLC3_SKIP_CNTL 20944f727eceSLe Ma #define SDMA7_RLC3_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 20954f727eceSLe Ma #define SDMA7_RLC3_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL 20964f727eceSLe Ma //SDMA7_RLC3_CONTEXT_STATUS 20974f727eceSLe Ma #define SDMA7_RLC3_CONTEXT_STATUS__SELECTED__SHIFT 0x0 20984f727eceSLe Ma #define SDMA7_RLC3_CONTEXT_STATUS__IDLE__SHIFT 0x2 20994f727eceSLe Ma #define SDMA7_RLC3_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 21004f727eceSLe Ma #define SDMA7_RLC3_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 21014f727eceSLe Ma #define SDMA7_RLC3_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 21024f727eceSLe Ma #define SDMA7_RLC3_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 21034f727eceSLe Ma #define SDMA7_RLC3_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 21044f727eceSLe Ma #define SDMA7_RLC3_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa 21054f727eceSLe Ma #define SDMA7_RLC3_CONTEXT_STATUS__SELECTED_MASK 0x00000001L 21064f727eceSLe Ma #define SDMA7_RLC3_CONTEXT_STATUS__IDLE_MASK 0x00000004L 21074f727eceSLe Ma #define SDMA7_RLC3_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L 21084f727eceSLe Ma #define SDMA7_RLC3_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L 21094f727eceSLe Ma #define SDMA7_RLC3_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L 21104f727eceSLe Ma #define SDMA7_RLC3_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L 21114f727eceSLe Ma #define SDMA7_RLC3_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L 21124f727eceSLe Ma #define SDMA7_RLC3_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L 21134f727eceSLe Ma //SDMA7_RLC3_DOORBELL 21144f727eceSLe Ma #define SDMA7_RLC3_DOORBELL__ENABLE__SHIFT 0x1c 21154f727eceSLe Ma #define SDMA7_RLC3_DOORBELL__CAPTURED__SHIFT 0x1e 21164f727eceSLe Ma #define SDMA7_RLC3_DOORBELL__ENABLE_MASK 0x10000000L 21174f727eceSLe Ma #define SDMA7_RLC3_DOORBELL__CAPTURED_MASK 0x40000000L 21184f727eceSLe Ma //SDMA7_RLC3_STATUS 21194f727eceSLe Ma #define SDMA7_RLC3_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 21204f727eceSLe Ma #define SDMA7_RLC3_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 21214f727eceSLe Ma #define SDMA7_RLC3_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL 21224f727eceSLe Ma #define SDMA7_RLC3_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L 21234f727eceSLe Ma //SDMA7_RLC3_DOORBELL_LOG 21244f727eceSLe Ma #define SDMA7_RLC3_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 21254f727eceSLe Ma #define SDMA7_RLC3_DOORBELL_LOG__DATA__SHIFT 0x2 21264f727eceSLe Ma #define SDMA7_RLC3_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L 21274f727eceSLe Ma #define SDMA7_RLC3_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL 21284f727eceSLe Ma //SDMA7_RLC3_WATERMARK 21294f727eceSLe Ma #define SDMA7_RLC3_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 21304f727eceSLe Ma #define SDMA7_RLC3_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 21314f727eceSLe Ma #define SDMA7_RLC3_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL 21324f727eceSLe Ma #define SDMA7_RLC3_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L 21334f727eceSLe Ma //SDMA7_RLC3_DOORBELL_OFFSET 21344f727eceSLe Ma #define SDMA7_RLC3_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 21354f727eceSLe Ma #define SDMA7_RLC3_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL 21364f727eceSLe Ma //SDMA7_RLC3_CSA_ADDR_LO 21374f727eceSLe Ma #define SDMA7_RLC3_CSA_ADDR_LO__ADDR__SHIFT 0x2 21384f727eceSLe Ma #define SDMA7_RLC3_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 21394f727eceSLe Ma //SDMA7_RLC3_CSA_ADDR_HI 21404f727eceSLe Ma #define SDMA7_RLC3_CSA_ADDR_HI__ADDR__SHIFT 0x0 21414f727eceSLe Ma #define SDMA7_RLC3_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 21424f727eceSLe Ma //SDMA7_RLC3_IB_SUB_REMAIN 21434f727eceSLe Ma #define SDMA7_RLC3_IB_SUB_REMAIN__SIZE__SHIFT 0x0 21444f727eceSLe Ma #define SDMA7_RLC3_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL 21454f727eceSLe Ma //SDMA7_RLC3_PREEMPT 21464f727eceSLe Ma #define SDMA7_RLC3_PREEMPT__IB_PREEMPT__SHIFT 0x0 21474f727eceSLe Ma #define SDMA7_RLC3_PREEMPT__IB_PREEMPT_MASK 0x00000001L 21484f727eceSLe Ma //SDMA7_RLC3_DUMMY_REG 21494f727eceSLe Ma #define SDMA7_RLC3_DUMMY_REG__DUMMY__SHIFT 0x0 21504f727eceSLe Ma #define SDMA7_RLC3_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL 21514f727eceSLe Ma //SDMA7_RLC3_RB_WPTR_POLL_ADDR_HI 21524f727eceSLe Ma #define SDMA7_RLC3_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 21534f727eceSLe Ma #define SDMA7_RLC3_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 21544f727eceSLe Ma //SDMA7_RLC3_RB_WPTR_POLL_ADDR_LO 21554f727eceSLe Ma #define SDMA7_RLC3_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 21564f727eceSLe Ma #define SDMA7_RLC3_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 21574f727eceSLe Ma //SDMA7_RLC3_RB_AQL_CNTL 21584f727eceSLe Ma #define SDMA7_RLC3_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 21594f727eceSLe Ma #define SDMA7_RLC3_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 21604f727eceSLe Ma #define SDMA7_RLC3_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 21614f727eceSLe Ma #define SDMA7_RLC3_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L 21624f727eceSLe Ma #define SDMA7_RLC3_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL 21634f727eceSLe Ma #define SDMA7_RLC3_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L 21644f727eceSLe Ma //SDMA7_RLC3_MINOR_PTR_UPDATE 21654f727eceSLe Ma #define SDMA7_RLC3_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 21664f727eceSLe Ma #define SDMA7_RLC3_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L 21674f727eceSLe Ma //SDMA7_RLC3_MIDCMD_DATA0 21684f727eceSLe Ma #define SDMA7_RLC3_MIDCMD_DATA0__DATA0__SHIFT 0x0 21694f727eceSLe Ma #define SDMA7_RLC3_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL 21704f727eceSLe Ma //SDMA7_RLC3_MIDCMD_DATA1 21714f727eceSLe Ma #define SDMA7_RLC3_MIDCMD_DATA1__DATA1__SHIFT 0x0 21724f727eceSLe Ma #define SDMA7_RLC3_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL 21734f727eceSLe Ma //SDMA7_RLC3_MIDCMD_DATA2 21744f727eceSLe Ma #define SDMA7_RLC3_MIDCMD_DATA2__DATA2__SHIFT 0x0 21754f727eceSLe Ma #define SDMA7_RLC3_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL 21764f727eceSLe Ma //SDMA7_RLC3_MIDCMD_DATA3 21774f727eceSLe Ma #define SDMA7_RLC3_MIDCMD_DATA3__DATA3__SHIFT 0x0 21784f727eceSLe Ma #define SDMA7_RLC3_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL 21794f727eceSLe Ma //SDMA7_RLC3_MIDCMD_DATA4 21804f727eceSLe Ma #define SDMA7_RLC3_MIDCMD_DATA4__DATA4__SHIFT 0x0 21814f727eceSLe Ma #define SDMA7_RLC3_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL 21824f727eceSLe Ma //SDMA7_RLC3_MIDCMD_DATA5 21834f727eceSLe Ma #define SDMA7_RLC3_MIDCMD_DATA5__DATA5__SHIFT 0x0 21844f727eceSLe Ma #define SDMA7_RLC3_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL 21854f727eceSLe Ma //SDMA7_RLC3_MIDCMD_DATA6 21864f727eceSLe Ma #define SDMA7_RLC3_MIDCMD_DATA6__DATA6__SHIFT 0x0 21874f727eceSLe Ma #define SDMA7_RLC3_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL 21884f727eceSLe Ma //SDMA7_RLC3_MIDCMD_DATA7 21894f727eceSLe Ma #define SDMA7_RLC3_MIDCMD_DATA7__DATA7__SHIFT 0x0 21904f727eceSLe Ma #define SDMA7_RLC3_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL 21914f727eceSLe Ma //SDMA7_RLC3_MIDCMD_DATA8 21924f727eceSLe Ma #define SDMA7_RLC3_MIDCMD_DATA8__DATA8__SHIFT 0x0 21934f727eceSLe Ma #define SDMA7_RLC3_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL 21944f727eceSLe Ma //SDMA7_RLC3_MIDCMD_CNTL 21954f727eceSLe Ma #define SDMA7_RLC3_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 21964f727eceSLe Ma #define SDMA7_RLC3_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 21974f727eceSLe Ma #define SDMA7_RLC3_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 21984f727eceSLe Ma #define SDMA7_RLC3_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 21994f727eceSLe Ma #define SDMA7_RLC3_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L 22004f727eceSLe Ma #define SDMA7_RLC3_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L 22014f727eceSLe Ma #define SDMA7_RLC3_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L 22024f727eceSLe Ma #define SDMA7_RLC3_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L 22034f727eceSLe Ma //SDMA7_RLC4_RB_CNTL 22044f727eceSLe Ma #define SDMA7_RLC4_RB_CNTL__RB_ENABLE__SHIFT 0x0 22054f727eceSLe Ma #define SDMA7_RLC4_RB_CNTL__RB_SIZE__SHIFT 0x1 22064f727eceSLe Ma #define SDMA7_RLC4_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 22074f727eceSLe Ma #define SDMA7_RLC4_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc 22084f727eceSLe Ma #define SDMA7_RLC4_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd 22094f727eceSLe Ma #define SDMA7_RLC4_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 22104f727eceSLe Ma #define SDMA7_RLC4_RB_CNTL__RB_PRIV__SHIFT 0x17 22114f727eceSLe Ma #define SDMA7_RLC4_RB_CNTL__RB_VMID__SHIFT 0x18 22124f727eceSLe Ma #define SDMA7_RLC4_RB_CNTL__RB_ENABLE_MASK 0x00000001L 22134f727eceSLe Ma #define SDMA7_RLC4_RB_CNTL__RB_SIZE_MASK 0x0000003EL 22144f727eceSLe Ma #define SDMA7_RLC4_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L 22154f727eceSLe Ma #define SDMA7_RLC4_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L 22164f727eceSLe Ma #define SDMA7_RLC4_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L 22174f727eceSLe Ma #define SDMA7_RLC4_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L 22184f727eceSLe Ma #define SDMA7_RLC4_RB_CNTL__RB_PRIV_MASK 0x00800000L 22194f727eceSLe Ma #define SDMA7_RLC4_RB_CNTL__RB_VMID_MASK 0x0F000000L 22204f727eceSLe Ma //SDMA7_RLC4_RB_BASE 22214f727eceSLe Ma #define SDMA7_RLC4_RB_BASE__ADDR__SHIFT 0x0 22224f727eceSLe Ma #define SDMA7_RLC4_RB_BASE__ADDR_MASK 0xFFFFFFFFL 22234f727eceSLe Ma //SDMA7_RLC4_RB_BASE_HI 22244f727eceSLe Ma #define SDMA7_RLC4_RB_BASE_HI__ADDR__SHIFT 0x0 22254f727eceSLe Ma #define SDMA7_RLC4_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL 22264f727eceSLe Ma //SDMA7_RLC4_RB_RPTR 22274f727eceSLe Ma #define SDMA7_RLC4_RB_RPTR__OFFSET__SHIFT 0x0 22284f727eceSLe Ma #define SDMA7_RLC4_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL 22294f727eceSLe Ma //SDMA7_RLC4_RB_RPTR_HI 22304f727eceSLe Ma #define SDMA7_RLC4_RB_RPTR_HI__OFFSET__SHIFT 0x0 22314f727eceSLe Ma #define SDMA7_RLC4_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL 22324f727eceSLe Ma //SDMA7_RLC4_RB_WPTR 22334f727eceSLe Ma #define SDMA7_RLC4_RB_WPTR__OFFSET__SHIFT 0x0 22344f727eceSLe Ma #define SDMA7_RLC4_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL 22354f727eceSLe Ma //SDMA7_RLC4_RB_WPTR_HI 22364f727eceSLe Ma #define SDMA7_RLC4_RB_WPTR_HI__OFFSET__SHIFT 0x0 22374f727eceSLe Ma #define SDMA7_RLC4_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL 22384f727eceSLe Ma //SDMA7_RLC4_RB_WPTR_POLL_CNTL 22394f727eceSLe Ma #define SDMA7_RLC4_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 22404f727eceSLe Ma #define SDMA7_RLC4_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 22414f727eceSLe Ma #define SDMA7_RLC4_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 22424f727eceSLe Ma #define SDMA7_RLC4_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 22434f727eceSLe Ma #define SDMA7_RLC4_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 22444f727eceSLe Ma #define SDMA7_RLC4_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L 22454f727eceSLe Ma #define SDMA7_RLC4_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L 22464f727eceSLe Ma #define SDMA7_RLC4_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L 22474f727eceSLe Ma #define SDMA7_RLC4_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L 22484f727eceSLe Ma #define SDMA7_RLC4_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L 22494f727eceSLe Ma //SDMA7_RLC4_RB_RPTR_ADDR_HI 22504f727eceSLe Ma #define SDMA7_RLC4_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 22514f727eceSLe Ma #define SDMA7_RLC4_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 22524f727eceSLe Ma //SDMA7_RLC4_RB_RPTR_ADDR_LO 22534f727eceSLe Ma #define SDMA7_RLC4_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 22544f727eceSLe Ma #define SDMA7_RLC4_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 22554f727eceSLe Ma #define SDMA7_RLC4_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L 22564f727eceSLe Ma #define SDMA7_RLC4_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 22574f727eceSLe Ma //SDMA7_RLC4_IB_CNTL 22584f727eceSLe Ma #define SDMA7_RLC4_IB_CNTL__IB_ENABLE__SHIFT 0x0 22594f727eceSLe Ma #define SDMA7_RLC4_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 22604f727eceSLe Ma #define SDMA7_RLC4_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 22614f727eceSLe Ma #define SDMA7_RLC4_IB_CNTL__CMD_VMID__SHIFT 0x10 22624f727eceSLe Ma #define SDMA7_RLC4_IB_CNTL__IB_ENABLE_MASK 0x00000001L 22634f727eceSLe Ma #define SDMA7_RLC4_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L 22644f727eceSLe Ma #define SDMA7_RLC4_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L 22654f727eceSLe Ma #define SDMA7_RLC4_IB_CNTL__CMD_VMID_MASK 0x000F0000L 22664f727eceSLe Ma //SDMA7_RLC4_IB_RPTR 22674f727eceSLe Ma #define SDMA7_RLC4_IB_RPTR__OFFSET__SHIFT 0x2 22684f727eceSLe Ma #define SDMA7_RLC4_IB_RPTR__OFFSET_MASK 0x003FFFFCL 22694f727eceSLe Ma //SDMA7_RLC4_IB_OFFSET 22704f727eceSLe Ma #define SDMA7_RLC4_IB_OFFSET__OFFSET__SHIFT 0x2 22714f727eceSLe Ma #define SDMA7_RLC4_IB_OFFSET__OFFSET_MASK 0x003FFFFCL 22724f727eceSLe Ma //SDMA7_RLC4_IB_BASE_LO 22734f727eceSLe Ma #define SDMA7_RLC4_IB_BASE_LO__ADDR__SHIFT 0x5 22744f727eceSLe Ma #define SDMA7_RLC4_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L 22754f727eceSLe Ma //SDMA7_RLC4_IB_BASE_HI 22764f727eceSLe Ma #define SDMA7_RLC4_IB_BASE_HI__ADDR__SHIFT 0x0 22774f727eceSLe Ma #define SDMA7_RLC4_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL 22784f727eceSLe Ma //SDMA7_RLC4_IB_SIZE 22794f727eceSLe Ma #define SDMA7_RLC4_IB_SIZE__SIZE__SHIFT 0x0 22804f727eceSLe Ma #define SDMA7_RLC4_IB_SIZE__SIZE_MASK 0x000FFFFFL 22814f727eceSLe Ma //SDMA7_RLC4_SKIP_CNTL 22824f727eceSLe Ma #define SDMA7_RLC4_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 22834f727eceSLe Ma #define SDMA7_RLC4_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL 22844f727eceSLe Ma //SDMA7_RLC4_CONTEXT_STATUS 22854f727eceSLe Ma #define SDMA7_RLC4_CONTEXT_STATUS__SELECTED__SHIFT 0x0 22864f727eceSLe Ma #define SDMA7_RLC4_CONTEXT_STATUS__IDLE__SHIFT 0x2 22874f727eceSLe Ma #define SDMA7_RLC4_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 22884f727eceSLe Ma #define SDMA7_RLC4_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 22894f727eceSLe Ma #define SDMA7_RLC4_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 22904f727eceSLe Ma #define SDMA7_RLC4_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 22914f727eceSLe Ma #define SDMA7_RLC4_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 22924f727eceSLe Ma #define SDMA7_RLC4_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa 22934f727eceSLe Ma #define SDMA7_RLC4_CONTEXT_STATUS__SELECTED_MASK 0x00000001L 22944f727eceSLe Ma #define SDMA7_RLC4_CONTEXT_STATUS__IDLE_MASK 0x00000004L 22954f727eceSLe Ma #define SDMA7_RLC4_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L 22964f727eceSLe Ma #define SDMA7_RLC4_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L 22974f727eceSLe Ma #define SDMA7_RLC4_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L 22984f727eceSLe Ma #define SDMA7_RLC4_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L 22994f727eceSLe Ma #define SDMA7_RLC4_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L 23004f727eceSLe Ma #define SDMA7_RLC4_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L 23014f727eceSLe Ma //SDMA7_RLC4_DOORBELL 23024f727eceSLe Ma #define SDMA7_RLC4_DOORBELL__ENABLE__SHIFT 0x1c 23034f727eceSLe Ma #define SDMA7_RLC4_DOORBELL__CAPTURED__SHIFT 0x1e 23044f727eceSLe Ma #define SDMA7_RLC4_DOORBELL__ENABLE_MASK 0x10000000L 23054f727eceSLe Ma #define SDMA7_RLC4_DOORBELL__CAPTURED_MASK 0x40000000L 23064f727eceSLe Ma //SDMA7_RLC4_STATUS 23074f727eceSLe Ma #define SDMA7_RLC4_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 23084f727eceSLe Ma #define SDMA7_RLC4_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 23094f727eceSLe Ma #define SDMA7_RLC4_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL 23104f727eceSLe Ma #define SDMA7_RLC4_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L 23114f727eceSLe Ma //SDMA7_RLC4_DOORBELL_LOG 23124f727eceSLe Ma #define SDMA7_RLC4_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 23134f727eceSLe Ma #define SDMA7_RLC4_DOORBELL_LOG__DATA__SHIFT 0x2 23144f727eceSLe Ma #define SDMA7_RLC4_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L 23154f727eceSLe Ma #define SDMA7_RLC4_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL 23164f727eceSLe Ma //SDMA7_RLC4_WATERMARK 23174f727eceSLe Ma #define SDMA7_RLC4_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 23184f727eceSLe Ma #define SDMA7_RLC4_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 23194f727eceSLe Ma #define SDMA7_RLC4_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL 23204f727eceSLe Ma #define SDMA7_RLC4_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L 23214f727eceSLe Ma //SDMA7_RLC4_DOORBELL_OFFSET 23224f727eceSLe Ma #define SDMA7_RLC4_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 23234f727eceSLe Ma #define SDMA7_RLC4_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL 23244f727eceSLe Ma //SDMA7_RLC4_CSA_ADDR_LO 23254f727eceSLe Ma #define SDMA7_RLC4_CSA_ADDR_LO__ADDR__SHIFT 0x2 23264f727eceSLe Ma #define SDMA7_RLC4_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 23274f727eceSLe Ma //SDMA7_RLC4_CSA_ADDR_HI 23284f727eceSLe Ma #define SDMA7_RLC4_CSA_ADDR_HI__ADDR__SHIFT 0x0 23294f727eceSLe Ma #define SDMA7_RLC4_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 23304f727eceSLe Ma //SDMA7_RLC4_IB_SUB_REMAIN 23314f727eceSLe Ma #define SDMA7_RLC4_IB_SUB_REMAIN__SIZE__SHIFT 0x0 23324f727eceSLe Ma #define SDMA7_RLC4_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL 23334f727eceSLe Ma //SDMA7_RLC4_PREEMPT 23344f727eceSLe Ma #define SDMA7_RLC4_PREEMPT__IB_PREEMPT__SHIFT 0x0 23354f727eceSLe Ma #define SDMA7_RLC4_PREEMPT__IB_PREEMPT_MASK 0x00000001L 23364f727eceSLe Ma //SDMA7_RLC4_DUMMY_REG 23374f727eceSLe Ma #define SDMA7_RLC4_DUMMY_REG__DUMMY__SHIFT 0x0 23384f727eceSLe Ma #define SDMA7_RLC4_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL 23394f727eceSLe Ma //SDMA7_RLC4_RB_WPTR_POLL_ADDR_HI 23404f727eceSLe Ma #define SDMA7_RLC4_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 23414f727eceSLe Ma #define SDMA7_RLC4_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 23424f727eceSLe Ma //SDMA7_RLC4_RB_WPTR_POLL_ADDR_LO 23434f727eceSLe Ma #define SDMA7_RLC4_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 23444f727eceSLe Ma #define SDMA7_RLC4_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 23454f727eceSLe Ma //SDMA7_RLC4_RB_AQL_CNTL 23464f727eceSLe Ma #define SDMA7_RLC4_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 23474f727eceSLe Ma #define SDMA7_RLC4_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 23484f727eceSLe Ma #define SDMA7_RLC4_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 23494f727eceSLe Ma #define SDMA7_RLC4_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L 23504f727eceSLe Ma #define SDMA7_RLC4_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL 23514f727eceSLe Ma #define SDMA7_RLC4_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L 23524f727eceSLe Ma //SDMA7_RLC4_MINOR_PTR_UPDATE 23534f727eceSLe Ma #define SDMA7_RLC4_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 23544f727eceSLe Ma #define SDMA7_RLC4_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L 23554f727eceSLe Ma //SDMA7_RLC4_MIDCMD_DATA0 23564f727eceSLe Ma #define SDMA7_RLC4_MIDCMD_DATA0__DATA0__SHIFT 0x0 23574f727eceSLe Ma #define SDMA7_RLC4_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL 23584f727eceSLe Ma //SDMA7_RLC4_MIDCMD_DATA1 23594f727eceSLe Ma #define SDMA7_RLC4_MIDCMD_DATA1__DATA1__SHIFT 0x0 23604f727eceSLe Ma #define SDMA7_RLC4_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL 23614f727eceSLe Ma //SDMA7_RLC4_MIDCMD_DATA2 23624f727eceSLe Ma #define SDMA7_RLC4_MIDCMD_DATA2__DATA2__SHIFT 0x0 23634f727eceSLe Ma #define SDMA7_RLC4_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL 23644f727eceSLe Ma //SDMA7_RLC4_MIDCMD_DATA3 23654f727eceSLe Ma #define SDMA7_RLC4_MIDCMD_DATA3__DATA3__SHIFT 0x0 23664f727eceSLe Ma #define SDMA7_RLC4_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL 23674f727eceSLe Ma //SDMA7_RLC4_MIDCMD_DATA4 23684f727eceSLe Ma #define SDMA7_RLC4_MIDCMD_DATA4__DATA4__SHIFT 0x0 23694f727eceSLe Ma #define SDMA7_RLC4_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL 23704f727eceSLe Ma //SDMA7_RLC4_MIDCMD_DATA5 23714f727eceSLe Ma #define SDMA7_RLC4_MIDCMD_DATA5__DATA5__SHIFT 0x0 23724f727eceSLe Ma #define SDMA7_RLC4_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL 23734f727eceSLe Ma //SDMA7_RLC4_MIDCMD_DATA6 23744f727eceSLe Ma #define SDMA7_RLC4_MIDCMD_DATA6__DATA6__SHIFT 0x0 23754f727eceSLe Ma #define SDMA7_RLC4_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL 23764f727eceSLe Ma //SDMA7_RLC4_MIDCMD_DATA7 23774f727eceSLe Ma #define SDMA7_RLC4_MIDCMD_DATA7__DATA7__SHIFT 0x0 23784f727eceSLe Ma #define SDMA7_RLC4_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL 23794f727eceSLe Ma //SDMA7_RLC4_MIDCMD_DATA8 23804f727eceSLe Ma #define SDMA7_RLC4_MIDCMD_DATA8__DATA8__SHIFT 0x0 23814f727eceSLe Ma #define SDMA7_RLC4_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL 23824f727eceSLe Ma //SDMA7_RLC4_MIDCMD_CNTL 23834f727eceSLe Ma #define SDMA7_RLC4_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 23844f727eceSLe Ma #define SDMA7_RLC4_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 23854f727eceSLe Ma #define SDMA7_RLC4_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 23864f727eceSLe Ma #define SDMA7_RLC4_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 23874f727eceSLe Ma #define SDMA7_RLC4_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L 23884f727eceSLe Ma #define SDMA7_RLC4_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L 23894f727eceSLe Ma #define SDMA7_RLC4_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L 23904f727eceSLe Ma #define SDMA7_RLC4_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L 23914f727eceSLe Ma //SDMA7_RLC5_RB_CNTL 23924f727eceSLe Ma #define SDMA7_RLC5_RB_CNTL__RB_ENABLE__SHIFT 0x0 23934f727eceSLe Ma #define SDMA7_RLC5_RB_CNTL__RB_SIZE__SHIFT 0x1 23944f727eceSLe Ma #define SDMA7_RLC5_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 23954f727eceSLe Ma #define SDMA7_RLC5_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc 23964f727eceSLe Ma #define SDMA7_RLC5_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd 23974f727eceSLe Ma #define SDMA7_RLC5_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 23984f727eceSLe Ma #define SDMA7_RLC5_RB_CNTL__RB_PRIV__SHIFT 0x17 23994f727eceSLe Ma #define SDMA7_RLC5_RB_CNTL__RB_VMID__SHIFT 0x18 24004f727eceSLe Ma #define SDMA7_RLC5_RB_CNTL__RB_ENABLE_MASK 0x00000001L 24014f727eceSLe Ma #define SDMA7_RLC5_RB_CNTL__RB_SIZE_MASK 0x0000003EL 24024f727eceSLe Ma #define SDMA7_RLC5_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L 24034f727eceSLe Ma #define SDMA7_RLC5_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L 24044f727eceSLe Ma #define SDMA7_RLC5_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L 24054f727eceSLe Ma #define SDMA7_RLC5_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L 24064f727eceSLe Ma #define SDMA7_RLC5_RB_CNTL__RB_PRIV_MASK 0x00800000L 24074f727eceSLe Ma #define SDMA7_RLC5_RB_CNTL__RB_VMID_MASK 0x0F000000L 24084f727eceSLe Ma //SDMA7_RLC5_RB_BASE 24094f727eceSLe Ma #define SDMA7_RLC5_RB_BASE__ADDR__SHIFT 0x0 24104f727eceSLe Ma #define SDMA7_RLC5_RB_BASE__ADDR_MASK 0xFFFFFFFFL 24114f727eceSLe Ma //SDMA7_RLC5_RB_BASE_HI 24124f727eceSLe Ma #define SDMA7_RLC5_RB_BASE_HI__ADDR__SHIFT 0x0 24134f727eceSLe Ma #define SDMA7_RLC5_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL 24144f727eceSLe Ma //SDMA7_RLC5_RB_RPTR 24154f727eceSLe Ma #define SDMA7_RLC5_RB_RPTR__OFFSET__SHIFT 0x0 24164f727eceSLe Ma #define SDMA7_RLC5_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL 24174f727eceSLe Ma //SDMA7_RLC5_RB_RPTR_HI 24184f727eceSLe Ma #define SDMA7_RLC5_RB_RPTR_HI__OFFSET__SHIFT 0x0 24194f727eceSLe Ma #define SDMA7_RLC5_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL 24204f727eceSLe Ma //SDMA7_RLC5_RB_WPTR 24214f727eceSLe Ma #define SDMA7_RLC5_RB_WPTR__OFFSET__SHIFT 0x0 24224f727eceSLe Ma #define SDMA7_RLC5_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL 24234f727eceSLe Ma //SDMA7_RLC5_RB_WPTR_HI 24244f727eceSLe Ma #define SDMA7_RLC5_RB_WPTR_HI__OFFSET__SHIFT 0x0 24254f727eceSLe Ma #define SDMA7_RLC5_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL 24264f727eceSLe Ma //SDMA7_RLC5_RB_WPTR_POLL_CNTL 24274f727eceSLe Ma #define SDMA7_RLC5_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 24284f727eceSLe Ma #define SDMA7_RLC5_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 24294f727eceSLe Ma #define SDMA7_RLC5_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 24304f727eceSLe Ma #define SDMA7_RLC5_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 24314f727eceSLe Ma #define SDMA7_RLC5_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 24324f727eceSLe Ma #define SDMA7_RLC5_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L 24334f727eceSLe Ma #define SDMA7_RLC5_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L 24344f727eceSLe Ma #define SDMA7_RLC5_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L 24354f727eceSLe Ma #define SDMA7_RLC5_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L 24364f727eceSLe Ma #define SDMA7_RLC5_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L 24374f727eceSLe Ma //SDMA7_RLC5_RB_RPTR_ADDR_HI 24384f727eceSLe Ma #define SDMA7_RLC5_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 24394f727eceSLe Ma #define SDMA7_RLC5_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 24404f727eceSLe Ma //SDMA7_RLC5_RB_RPTR_ADDR_LO 24414f727eceSLe Ma #define SDMA7_RLC5_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 24424f727eceSLe Ma #define SDMA7_RLC5_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 24434f727eceSLe Ma #define SDMA7_RLC5_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L 24444f727eceSLe Ma #define SDMA7_RLC5_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 24454f727eceSLe Ma //SDMA7_RLC5_IB_CNTL 24464f727eceSLe Ma #define SDMA7_RLC5_IB_CNTL__IB_ENABLE__SHIFT 0x0 24474f727eceSLe Ma #define SDMA7_RLC5_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 24484f727eceSLe Ma #define SDMA7_RLC5_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 24494f727eceSLe Ma #define SDMA7_RLC5_IB_CNTL__CMD_VMID__SHIFT 0x10 24504f727eceSLe Ma #define SDMA7_RLC5_IB_CNTL__IB_ENABLE_MASK 0x00000001L 24514f727eceSLe Ma #define SDMA7_RLC5_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L 24524f727eceSLe Ma #define SDMA7_RLC5_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L 24534f727eceSLe Ma #define SDMA7_RLC5_IB_CNTL__CMD_VMID_MASK 0x000F0000L 24544f727eceSLe Ma //SDMA7_RLC5_IB_RPTR 24554f727eceSLe Ma #define SDMA7_RLC5_IB_RPTR__OFFSET__SHIFT 0x2 24564f727eceSLe Ma #define SDMA7_RLC5_IB_RPTR__OFFSET_MASK 0x003FFFFCL 24574f727eceSLe Ma //SDMA7_RLC5_IB_OFFSET 24584f727eceSLe Ma #define SDMA7_RLC5_IB_OFFSET__OFFSET__SHIFT 0x2 24594f727eceSLe Ma #define SDMA7_RLC5_IB_OFFSET__OFFSET_MASK 0x003FFFFCL 24604f727eceSLe Ma //SDMA7_RLC5_IB_BASE_LO 24614f727eceSLe Ma #define SDMA7_RLC5_IB_BASE_LO__ADDR__SHIFT 0x5 24624f727eceSLe Ma #define SDMA7_RLC5_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L 24634f727eceSLe Ma //SDMA7_RLC5_IB_BASE_HI 24644f727eceSLe Ma #define SDMA7_RLC5_IB_BASE_HI__ADDR__SHIFT 0x0 24654f727eceSLe Ma #define SDMA7_RLC5_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL 24664f727eceSLe Ma //SDMA7_RLC5_IB_SIZE 24674f727eceSLe Ma #define SDMA7_RLC5_IB_SIZE__SIZE__SHIFT 0x0 24684f727eceSLe Ma #define SDMA7_RLC5_IB_SIZE__SIZE_MASK 0x000FFFFFL 24694f727eceSLe Ma //SDMA7_RLC5_SKIP_CNTL 24704f727eceSLe Ma #define SDMA7_RLC5_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 24714f727eceSLe Ma #define SDMA7_RLC5_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL 24724f727eceSLe Ma //SDMA7_RLC5_CONTEXT_STATUS 24734f727eceSLe Ma #define SDMA7_RLC5_CONTEXT_STATUS__SELECTED__SHIFT 0x0 24744f727eceSLe Ma #define SDMA7_RLC5_CONTEXT_STATUS__IDLE__SHIFT 0x2 24754f727eceSLe Ma #define SDMA7_RLC5_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 24764f727eceSLe Ma #define SDMA7_RLC5_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 24774f727eceSLe Ma #define SDMA7_RLC5_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 24784f727eceSLe Ma #define SDMA7_RLC5_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 24794f727eceSLe Ma #define SDMA7_RLC5_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 24804f727eceSLe Ma #define SDMA7_RLC5_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa 24814f727eceSLe Ma #define SDMA7_RLC5_CONTEXT_STATUS__SELECTED_MASK 0x00000001L 24824f727eceSLe Ma #define SDMA7_RLC5_CONTEXT_STATUS__IDLE_MASK 0x00000004L 24834f727eceSLe Ma #define SDMA7_RLC5_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L 24844f727eceSLe Ma #define SDMA7_RLC5_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L 24854f727eceSLe Ma #define SDMA7_RLC5_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L 24864f727eceSLe Ma #define SDMA7_RLC5_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L 24874f727eceSLe Ma #define SDMA7_RLC5_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L 24884f727eceSLe Ma #define SDMA7_RLC5_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L 24894f727eceSLe Ma //SDMA7_RLC5_DOORBELL 24904f727eceSLe Ma #define SDMA7_RLC5_DOORBELL__ENABLE__SHIFT 0x1c 24914f727eceSLe Ma #define SDMA7_RLC5_DOORBELL__CAPTURED__SHIFT 0x1e 24924f727eceSLe Ma #define SDMA7_RLC5_DOORBELL__ENABLE_MASK 0x10000000L 24934f727eceSLe Ma #define SDMA7_RLC5_DOORBELL__CAPTURED_MASK 0x40000000L 24944f727eceSLe Ma //SDMA7_RLC5_STATUS 24954f727eceSLe Ma #define SDMA7_RLC5_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 24964f727eceSLe Ma #define SDMA7_RLC5_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 24974f727eceSLe Ma #define SDMA7_RLC5_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL 24984f727eceSLe Ma #define SDMA7_RLC5_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L 24994f727eceSLe Ma //SDMA7_RLC5_DOORBELL_LOG 25004f727eceSLe Ma #define SDMA7_RLC5_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 25014f727eceSLe Ma #define SDMA7_RLC5_DOORBELL_LOG__DATA__SHIFT 0x2 25024f727eceSLe Ma #define SDMA7_RLC5_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L 25034f727eceSLe Ma #define SDMA7_RLC5_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL 25044f727eceSLe Ma //SDMA7_RLC5_WATERMARK 25054f727eceSLe Ma #define SDMA7_RLC5_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 25064f727eceSLe Ma #define SDMA7_RLC5_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 25074f727eceSLe Ma #define SDMA7_RLC5_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL 25084f727eceSLe Ma #define SDMA7_RLC5_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L 25094f727eceSLe Ma //SDMA7_RLC5_DOORBELL_OFFSET 25104f727eceSLe Ma #define SDMA7_RLC5_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 25114f727eceSLe Ma #define SDMA7_RLC5_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL 25124f727eceSLe Ma //SDMA7_RLC5_CSA_ADDR_LO 25134f727eceSLe Ma #define SDMA7_RLC5_CSA_ADDR_LO__ADDR__SHIFT 0x2 25144f727eceSLe Ma #define SDMA7_RLC5_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 25154f727eceSLe Ma //SDMA7_RLC5_CSA_ADDR_HI 25164f727eceSLe Ma #define SDMA7_RLC5_CSA_ADDR_HI__ADDR__SHIFT 0x0 25174f727eceSLe Ma #define SDMA7_RLC5_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 25184f727eceSLe Ma //SDMA7_RLC5_IB_SUB_REMAIN 25194f727eceSLe Ma #define SDMA7_RLC5_IB_SUB_REMAIN__SIZE__SHIFT 0x0 25204f727eceSLe Ma #define SDMA7_RLC5_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL 25214f727eceSLe Ma //SDMA7_RLC5_PREEMPT 25224f727eceSLe Ma #define SDMA7_RLC5_PREEMPT__IB_PREEMPT__SHIFT 0x0 25234f727eceSLe Ma #define SDMA7_RLC5_PREEMPT__IB_PREEMPT_MASK 0x00000001L 25244f727eceSLe Ma //SDMA7_RLC5_DUMMY_REG 25254f727eceSLe Ma #define SDMA7_RLC5_DUMMY_REG__DUMMY__SHIFT 0x0 25264f727eceSLe Ma #define SDMA7_RLC5_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL 25274f727eceSLe Ma //SDMA7_RLC5_RB_WPTR_POLL_ADDR_HI 25284f727eceSLe Ma #define SDMA7_RLC5_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 25294f727eceSLe Ma #define SDMA7_RLC5_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 25304f727eceSLe Ma //SDMA7_RLC5_RB_WPTR_POLL_ADDR_LO 25314f727eceSLe Ma #define SDMA7_RLC5_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 25324f727eceSLe Ma #define SDMA7_RLC5_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 25334f727eceSLe Ma //SDMA7_RLC5_RB_AQL_CNTL 25344f727eceSLe Ma #define SDMA7_RLC5_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 25354f727eceSLe Ma #define SDMA7_RLC5_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 25364f727eceSLe Ma #define SDMA7_RLC5_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 25374f727eceSLe Ma #define SDMA7_RLC5_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L 25384f727eceSLe Ma #define SDMA7_RLC5_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL 25394f727eceSLe Ma #define SDMA7_RLC5_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L 25404f727eceSLe Ma //SDMA7_RLC5_MINOR_PTR_UPDATE 25414f727eceSLe Ma #define SDMA7_RLC5_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 25424f727eceSLe Ma #define SDMA7_RLC5_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L 25434f727eceSLe Ma //SDMA7_RLC5_MIDCMD_DATA0 25444f727eceSLe Ma #define SDMA7_RLC5_MIDCMD_DATA0__DATA0__SHIFT 0x0 25454f727eceSLe Ma #define SDMA7_RLC5_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL 25464f727eceSLe Ma //SDMA7_RLC5_MIDCMD_DATA1 25474f727eceSLe Ma #define SDMA7_RLC5_MIDCMD_DATA1__DATA1__SHIFT 0x0 25484f727eceSLe Ma #define SDMA7_RLC5_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL 25494f727eceSLe Ma //SDMA7_RLC5_MIDCMD_DATA2 25504f727eceSLe Ma #define SDMA7_RLC5_MIDCMD_DATA2__DATA2__SHIFT 0x0 25514f727eceSLe Ma #define SDMA7_RLC5_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL 25524f727eceSLe Ma //SDMA7_RLC5_MIDCMD_DATA3 25534f727eceSLe Ma #define SDMA7_RLC5_MIDCMD_DATA3__DATA3__SHIFT 0x0 25544f727eceSLe Ma #define SDMA7_RLC5_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL 25554f727eceSLe Ma //SDMA7_RLC5_MIDCMD_DATA4 25564f727eceSLe Ma #define SDMA7_RLC5_MIDCMD_DATA4__DATA4__SHIFT 0x0 25574f727eceSLe Ma #define SDMA7_RLC5_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL 25584f727eceSLe Ma //SDMA7_RLC5_MIDCMD_DATA5 25594f727eceSLe Ma #define SDMA7_RLC5_MIDCMD_DATA5__DATA5__SHIFT 0x0 25604f727eceSLe Ma #define SDMA7_RLC5_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL 25614f727eceSLe Ma //SDMA7_RLC5_MIDCMD_DATA6 25624f727eceSLe Ma #define SDMA7_RLC5_MIDCMD_DATA6__DATA6__SHIFT 0x0 25634f727eceSLe Ma #define SDMA7_RLC5_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL 25644f727eceSLe Ma //SDMA7_RLC5_MIDCMD_DATA7 25654f727eceSLe Ma #define SDMA7_RLC5_MIDCMD_DATA7__DATA7__SHIFT 0x0 25664f727eceSLe Ma #define SDMA7_RLC5_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL 25674f727eceSLe Ma //SDMA7_RLC5_MIDCMD_DATA8 25684f727eceSLe Ma #define SDMA7_RLC5_MIDCMD_DATA8__DATA8__SHIFT 0x0 25694f727eceSLe Ma #define SDMA7_RLC5_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL 25704f727eceSLe Ma //SDMA7_RLC5_MIDCMD_CNTL 25714f727eceSLe Ma #define SDMA7_RLC5_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 25724f727eceSLe Ma #define SDMA7_RLC5_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 25734f727eceSLe Ma #define SDMA7_RLC5_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 25744f727eceSLe Ma #define SDMA7_RLC5_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 25754f727eceSLe Ma #define SDMA7_RLC5_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L 25764f727eceSLe Ma #define SDMA7_RLC5_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L 25774f727eceSLe Ma #define SDMA7_RLC5_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L 25784f727eceSLe Ma #define SDMA7_RLC5_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L 25794f727eceSLe Ma //SDMA7_RLC6_RB_CNTL 25804f727eceSLe Ma #define SDMA7_RLC6_RB_CNTL__RB_ENABLE__SHIFT 0x0 25814f727eceSLe Ma #define SDMA7_RLC6_RB_CNTL__RB_SIZE__SHIFT 0x1 25824f727eceSLe Ma #define SDMA7_RLC6_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 25834f727eceSLe Ma #define SDMA7_RLC6_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc 25844f727eceSLe Ma #define SDMA7_RLC6_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd 25854f727eceSLe Ma #define SDMA7_RLC6_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 25864f727eceSLe Ma #define SDMA7_RLC6_RB_CNTL__RB_PRIV__SHIFT 0x17 25874f727eceSLe Ma #define SDMA7_RLC6_RB_CNTL__RB_VMID__SHIFT 0x18 25884f727eceSLe Ma #define SDMA7_RLC6_RB_CNTL__RB_ENABLE_MASK 0x00000001L 25894f727eceSLe Ma #define SDMA7_RLC6_RB_CNTL__RB_SIZE_MASK 0x0000003EL 25904f727eceSLe Ma #define SDMA7_RLC6_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L 25914f727eceSLe Ma #define SDMA7_RLC6_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L 25924f727eceSLe Ma #define SDMA7_RLC6_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L 25934f727eceSLe Ma #define SDMA7_RLC6_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L 25944f727eceSLe Ma #define SDMA7_RLC6_RB_CNTL__RB_PRIV_MASK 0x00800000L 25954f727eceSLe Ma #define SDMA7_RLC6_RB_CNTL__RB_VMID_MASK 0x0F000000L 25964f727eceSLe Ma //SDMA7_RLC6_RB_BASE 25974f727eceSLe Ma #define SDMA7_RLC6_RB_BASE__ADDR__SHIFT 0x0 25984f727eceSLe Ma #define SDMA7_RLC6_RB_BASE__ADDR_MASK 0xFFFFFFFFL 25994f727eceSLe Ma //SDMA7_RLC6_RB_BASE_HI 26004f727eceSLe Ma #define SDMA7_RLC6_RB_BASE_HI__ADDR__SHIFT 0x0 26014f727eceSLe Ma #define SDMA7_RLC6_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL 26024f727eceSLe Ma //SDMA7_RLC6_RB_RPTR 26034f727eceSLe Ma #define SDMA7_RLC6_RB_RPTR__OFFSET__SHIFT 0x0 26044f727eceSLe Ma #define SDMA7_RLC6_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL 26054f727eceSLe Ma //SDMA7_RLC6_RB_RPTR_HI 26064f727eceSLe Ma #define SDMA7_RLC6_RB_RPTR_HI__OFFSET__SHIFT 0x0 26074f727eceSLe Ma #define SDMA7_RLC6_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL 26084f727eceSLe Ma //SDMA7_RLC6_RB_WPTR 26094f727eceSLe Ma #define SDMA7_RLC6_RB_WPTR__OFFSET__SHIFT 0x0 26104f727eceSLe Ma #define SDMA7_RLC6_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL 26114f727eceSLe Ma //SDMA7_RLC6_RB_WPTR_HI 26124f727eceSLe Ma #define SDMA7_RLC6_RB_WPTR_HI__OFFSET__SHIFT 0x0 26134f727eceSLe Ma #define SDMA7_RLC6_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL 26144f727eceSLe Ma //SDMA7_RLC6_RB_WPTR_POLL_CNTL 26154f727eceSLe Ma #define SDMA7_RLC6_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 26164f727eceSLe Ma #define SDMA7_RLC6_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 26174f727eceSLe Ma #define SDMA7_RLC6_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 26184f727eceSLe Ma #define SDMA7_RLC6_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 26194f727eceSLe Ma #define SDMA7_RLC6_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 26204f727eceSLe Ma #define SDMA7_RLC6_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L 26214f727eceSLe Ma #define SDMA7_RLC6_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L 26224f727eceSLe Ma #define SDMA7_RLC6_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L 26234f727eceSLe Ma #define SDMA7_RLC6_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L 26244f727eceSLe Ma #define SDMA7_RLC6_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L 26254f727eceSLe Ma //SDMA7_RLC6_RB_RPTR_ADDR_HI 26264f727eceSLe Ma #define SDMA7_RLC6_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 26274f727eceSLe Ma #define SDMA7_RLC6_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 26284f727eceSLe Ma //SDMA7_RLC6_RB_RPTR_ADDR_LO 26294f727eceSLe Ma #define SDMA7_RLC6_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 26304f727eceSLe Ma #define SDMA7_RLC6_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 26314f727eceSLe Ma #define SDMA7_RLC6_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L 26324f727eceSLe Ma #define SDMA7_RLC6_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 26334f727eceSLe Ma //SDMA7_RLC6_IB_CNTL 26344f727eceSLe Ma #define SDMA7_RLC6_IB_CNTL__IB_ENABLE__SHIFT 0x0 26354f727eceSLe Ma #define SDMA7_RLC6_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 26364f727eceSLe Ma #define SDMA7_RLC6_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 26374f727eceSLe Ma #define SDMA7_RLC6_IB_CNTL__CMD_VMID__SHIFT 0x10 26384f727eceSLe Ma #define SDMA7_RLC6_IB_CNTL__IB_ENABLE_MASK 0x00000001L 26394f727eceSLe Ma #define SDMA7_RLC6_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L 26404f727eceSLe Ma #define SDMA7_RLC6_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L 26414f727eceSLe Ma #define SDMA7_RLC6_IB_CNTL__CMD_VMID_MASK 0x000F0000L 26424f727eceSLe Ma //SDMA7_RLC6_IB_RPTR 26434f727eceSLe Ma #define SDMA7_RLC6_IB_RPTR__OFFSET__SHIFT 0x2 26444f727eceSLe Ma #define SDMA7_RLC6_IB_RPTR__OFFSET_MASK 0x003FFFFCL 26454f727eceSLe Ma //SDMA7_RLC6_IB_OFFSET 26464f727eceSLe Ma #define SDMA7_RLC6_IB_OFFSET__OFFSET__SHIFT 0x2 26474f727eceSLe Ma #define SDMA7_RLC6_IB_OFFSET__OFFSET_MASK 0x003FFFFCL 26484f727eceSLe Ma //SDMA7_RLC6_IB_BASE_LO 26494f727eceSLe Ma #define SDMA7_RLC6_IB_BASE_LO__ADDR__SHIFT 0x5 26504f727eceSLe Ma #define SDMA7_RLC6_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L 26514f727eceSLe Ma //SDMA7_RLC6_IB_BASE_HI 26524f727eceSLe Ma #define SDMA7_RLC6_IB_BASE_HI__ADDR__SHIFT 0x0 26534f727eceSLe Ma #define SDMA7_RLC6_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL 26544f727eceSLe Ma //SDMA7_RLC6_IB_SIZE 26554f727eceSLe Ma #define SDMA7_RLC6_IB_SIZE__SIZE__SHIFT 0x0 26564f727eceSLe Ma #define SDMA7_RLC6_IB_SIZE__SIZE_MASK 0x000FFFFFL 26574f727eceSLe Ma //SDMA7_RLC6_SKIP_CNTL 26584f727eceSLe Ma #define SDMA7_RLC6_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 26594f727eceSLe Ma #define SDMA7_RLC6_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL 26604f727eceSLe Ma //SDMA7_RLC6_CONTEXT_STATUS 26614f727eceSLe Ma #define SDMA7_RLC6_CONTEXT_STATUS__SELECTED__SHIFT 0x0 26624f727eceSLe Ma #define SDMA7_RLC6_CONTEXT_STATUS__IDLE__SHIFT 0x2 26634f727eceSLe Ma #define SDMA7_RLC6_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 26644f727eceSLe Ma #define SDMA7_RLC6_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 26654f727eceSLe Ma #define SDMA7_RLC6_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 26664f727eceSLe Ma #define SDMA7_RLC6_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 26674f727eceSLe Ma #define SDMA7_RLC6_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 26684f727eceSLe Ma #define SDMA7_RLC6_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa 26694f727eceSLe Ma #define SDMA7_RLC6_CONTEXT_STATUS__SELECTED_MASK 0x00000001L 26704f727eceSLe Ma #define SDMA7_RLC6_CONTEXT_STATUS__IDLE_MASK 0x00000004L 26714f727eceSLe Ma #define SDMA7_RLC6_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L 26724f727eceSLe Ma #define SDMA7_RLC6_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L 26734f727eceSLe Ma #define SDMA7_RLC6_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L 26744f727eceSLe Ma #define SDMA7_RLC6_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L 26754f727eceSLe Ma #define SDMA7_RLC6_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L 26764f727eceSLe Ma #define SDMA7_RLC6_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L 26774f727eceSLe Ma //SDMA7_RLC6_DOORBELL 26784f727eceSLe Ma #define SDMA7_RLC6_DOORBELL__ENABLE__SHIFT 0x1c 26794f727eceSLe Ma #define SDMA7_RLC6_DOORBELL__CAPTURED__SHIFT 0x1e 26804f727eceSLe Ma #define SDMA7_RLC6_DOORBELL__ENABLE_MASK 0x10000000L 26814f727eceSLe Ma #define SDMA7_RLC6_DOORBELL__CAPTURED_MASK 0x40000000L 26824f727eceSLe Ma //SDMA7_RLC6_STATUS 26834f727eceSLe Ma #define SDMA7_RLC6_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 26844f727eceSLe Ma #define SDMA7_RLC6_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 26854f727eceSLe Ma #define SDMA7_RLC6_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL 26864f727eceSLe Ma #define SDMA7_RLC6_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L 26874f727eceSLe Ma //SDMA7_RLC6_DOORBELL_LOG 26884f727eceSLe Ma #define SDMA7_RLC6_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 26894f727eceSLe Ma #define SDMA7_RLC6_DOORBELL_LOG__DATA__SHIFT 0x2 26904f727eceSLe Ma #define SDMA7_RLC6_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L 26914f727eceSLe Ma #define SDMA7_RLC6_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL 26924f727eceSLe Ma //SDMA7_RLC6_WATERMARK 26934f727eceSLe Ma #define SDMA7_RLC6_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 26944f727eceSLe Ma #define SDMA7_RLC6_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 26954f727eceSLe Ma #define SDMA7_RLC6_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL 26964f727eceSLe Ma #define SDMA7_RLC6_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L 26974f727eceSLe Ma //SDMA7_RLC6_DOORBELL_OFFSET 26984f727eceSLe Ma #define SDMA7_RLC6_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 26994f727eceSLe Ma #define SDMA7_RLC6_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL 27004f727eceSLe Ma //SDMA7_RLC6_CSA_ADDR_LO 27014f727eceSLe Ma #define SDMA7_RLC6_CSA_ADDR_LO__ADDR__SHIFT 0x2 27024f727eceSLe Ma #define SDMA7_RLC6_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 27034f727eceSLe Ma //SDMA7_RLC6_CSA_ADDR_HI 27044f727eceSLe Ma #define SDMA7_RLC6_CSA_ADDR_HI__ADDR__SHIFT 0x0 27054f727eceSLe Ma #define SDMA7_RLC6_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 27064f727eceSLe Ma //SDMA7_RLC6_IB_SUB_REMAIN 27074f727eceSLe Ma #define SDMA7_RLC6_IB_SUB_REMAIN__SIZE__SHIFT 0x0 27084f727eceSLe Ma #define SDMA7_RLC6_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL 27094f727eceSLe Ma //SDMA7_RLC6_PREEMPT 27104f727eceSLe Ma #define SDMA7_RLC6_PREEMPT__IB_PREEMPT__SHIFT 0x0 27114f727eceSLe Ma #define SDMA7_RLC6_PREEMPT__IB_PREEMPT_MASK 0x00000001L 27124f727eceSLe Ma //SDMA7_RLC6_DUMMY_REG 27134f727eceSLe Ma #define SDMA7_RLC6_DUMMY_REG__DUMMY__SHIFT 0x0 27144f727eceSLe Ma #define SDMA7_RLC6_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL 27154f727eceSLe Ma //SDMA7_RLC6_RB_WPTR_POLL_ADDR_HI 27164f727eceSLe Ma #define SDMA7_RLC6_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 27174f727eceSLe Ma #define SDMA7_RLC6_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 27184f727eceSLe Ma //SDMA7_RLC6_RB_WPTR_POLL_ADDR_LO 27194f727eceSLe Ma #define SDMA7_RLC6_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 27204f727eceSLe Ma #define SDMA7_RLC6_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 27214f727eceSLe Ma //SDMA7_RLC6_RB_AQL_CNTL 27224f727eceSLe Ma #define SDMA7_RLC6_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 27234f727eceSLe Ma #define SDMA7_RLC6_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 27244f727eceSLe Ma #define SDMA7_RLC6_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 27254f727eceSLe Ma #define SDMA7_RLC6_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L 27264f727eceSLe Ma #define SDMA7_RLC6_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL 27274f727eceSLe Ma #define SDMA7_RLC6_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L 27284f727eceSLe Ma //SDMA7_RLC6_MINOR_PTR_UPDATE 27294f727eceSLe Ma #define SDMA7_RLC6_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 27304f727eceSLe Ma #define SDMA7_RLC6_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L 27314f727eceSLe Ma //SDMA7_RLC6_MIDCMD_DATA0 27324f727eceSLe Ma #define SDMA7_RLC6_MIDCMD_DATA0__DATA0__SHIFT 0x0 27334f727eceSLe Ma #define SDMA7_RLC6_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL 27344f727eceSLe Ma //SDMA7_RLC6_MIDCMD_DATA1 27354f727eceSLe Ma #define SDMA7_RLC6_MIDCMD_DATA1__DATA1__SHIFT 0x0 27364f727eceSLe Ma #define SDMA7_RLC6_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL 27374f727eceSLe Ma //SDMA7_RLC6_MIDCMD_DATA2 27384f727eceSLe Ma #define SDMA7_RLC6_MIDCMD_DATA2__DATA2__SHIFT 0x0 27394f727eceSLe Ma #define SDMA7_RLC6_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL 27404f727eceSLe Ma //SDMA7_RLC6_MIDCMD_DATA3 27414f727eceSLe Ma #define SDMA7_RLC6_MIDCMD_DATA3__DATA3__SHIFT 0x0 27424f727eceSLe Ma #define SDMA7_RLC6_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL 27434f727eceSLe Ma //SDMA7_RLC6_MIDCMD_DATA4 27444f727eceSLe Ma #define SDMA7_RLC6_MIDCMD_DATA4__DATA4__SHIFT 0x0 27454f727eceSLe Ma #define SDMA7_RLC6_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL 27464f727eceSLe Ma //SDMA7_RLC6_MIDCMD_DATA5 27474f727eceSLe Ma #define SDMA7_RLC6_MIDCMD_DATA5__DATA5__SHIFT 0x0 27484f727eceSLe Ma #define SDMA7_RLC6_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL 27494f727eceSLe Ma //SDMA7_RLC6_MIDCMD_DATA6 27504f727eceSLe Ma #define SDMA7_RLC6_MIDCMD_DATA6__DATA6__SHIFT 0x0 27514f727eceSLe Ma #define SDMA7_RLC6_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL 27524f727eceSLe Ma //SDMA7_RLC6_MIDCMD_DATA7 27534f727eceSLe Ma #define SDMA7_RLC6_MIDCMD_DATA7__DATA7__SHIFT 0x0 27544f727eceSLe Ma #define SDMA7_RLC6_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL 27554f727eceSLe Ma //SDMA7_RLC6_MIDCMD_DATA8 27564f727eceSLe Ma #define SDMA7_RLC6_MIDCMD_DATA8__DATA8__SHIFT 0x0 27574f727eceSLe Ma #define SDMA7_RLC6_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL 27584f727eceSLe Ma //SDMA7_RLC6_MIDCMD_CNTL 27594f727eceSLe Ma #define SDMA7_RLC6_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 27604f727eceSLe Ma #define SDMA7_RLC6_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 27614f727eceSLe Ma #define SDMA7_RLC6_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 27624f727eceSLe Ma #define SDMA7_RLC6_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 27634f727eceSLe Ma #define SDMA7_RLC6_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L 27644f727eceSLe Ma #define SDMA7_RLC6_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L 27654f727eceSLe Ma #define SDMA7_RLC6_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L 27664f727eceSLe Ma #define SDMA7_RLC6_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L 27674f727eceSLe Ma //SDMA7_RLC7_RB_CNTL 27684f727eceSLe Ma #define SDMA7_RLC7_RB_CNTL__RB_ENABLE__SHIFT 0x0 27694f727eceSLe Ma #define SDMA7_RLC7_RB_CNTL__RB_SIZE__SHIFT 0x1 27704f727eceSLe Ma #define SDMA7_RLC7_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 27714f727eceSLe Ma #define SDMA7_RLC7_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc 27724f727eceSLe Ma #define SDMA7_RLC7_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd 27734f727eceSLe Ma #define SDMA7_RLC7_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 27744f727eceSLe Ma #define SDMA7_RLC7_RB_CNTL__RB_PRIV__SHIFT 0x17 27754f727eceSLe Ma #define SDMA7_RLC7_RB_CNTL__RB_VMID__SHIFT 0x18 27764f727eceSLe Ma #define SDMA7_RLC7_RB_CNTL__RB_ENABLE_MASK 0x00000001L 27774f727eceSLe Ma #define SDMA7_RLC7_RB_CNTL__RB_SIZE_MASK 0x0000003EL 27784f727eceSLe Ma #define SDMA7_RLC7_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L 27794f727eceSLe Ma #define SDMA7_RLC7_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L 27804f727eceSLe Ma #define SDMA7_RLC7_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L 27814f727eceSLe Ma #define SDMA7_RLC7_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L 27824f727eceSLe Ma #define SDMA7_RLC7_RB_CNTL__RB_PRIV_MASK 0x00800000L 27834f727eceSLe Ma #define SDMA7_RLC7_RB_CNTL__RB_VMID_MASK 0x0F000000L 27844f727eceSLe Ma //SDMA7_RLC7_RB_BASE 27854f727eceSLe Ma #define SDMA7_RLC7_RB_BASE__ADDR__SHIFT 0x0 27864f727eceSLe Ma #define SDMA7_RLC7_RB_BASE__ADDR_MASK 0xFFFFFFFFL 27874f727eceSLe Ma //SDMA7_RLC7_RB_BASE_HI 27884f727eceSLe Ma #define SDMA7_RLC7_RB_BASE_HI__ADDR__SHIFT 0x0 27894f727eceSLe Ma #define SDMA7_RLC7_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL 27904f727eceSLe Ma //SDMA7_RLC7_RB_RPTR 27914f727eceSLe Ma #define SDMA7_RLC7_RB_RPTR__OFFSET__SHIFT 0x0 27924f727eceSLe Ma #define SDMA7_RLC7_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL 27934f727eceSLe Ma //SDMA7_RLC7_RB_RPTR_HI 27944f727eceSLe Ma #define SDMA7_RLC7_RB_RPTR_HI__OFFSET__SHIFT 0x0 27954f727eceSLe Ma #define SDMA7_RLC7_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL 27964f727eceSLe Ma //SDMA7_RLC7_RB_WPTR 27974f727eceSLe Ma #define SDMA7_RLC7_RB_WPTR__OFFSET__SHIFT 0x0 27984f727eceSLe Ma #define SDMA7_RLC7_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL 27994f727eceSLe Ma //SDMA7_RLC7_RB_WPTR_HI 28004f727eceSLe Ma #define SDMA7_RLC7_RB_WPTR_HI__OFFSET__SHIFT 0x0 28014f727eceSLe Ma #define SDMA7_RLC7_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL 28024f727eceSLe Ma //SDMA7_RLC7_RB_WPTR_POLL_CNTL 28034f727eceSLe Ma #define SDMA7_RLC7_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 28044f727eceSLe Ma #define SDMA7_RLC7_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 28054f727eceSLe Ma #define SDMA7_RLC7_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 28064f727eceSLe Ma #define SDMA7_RLC7_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 28074f727eceSLe Ma #define SDMA7_RLC7_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 28084f727eceSLe Ma #define SDMA7_RLC7_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L 28094f727eceSLe Ma #define SDMA7_RLC7_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L 28104f727eceSLe Ma #define SDMA7_RLC7_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L 28114f727eceSLe Ma #define SDMA7_RLC7_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L 28124f727eceSLe Ma #define SDMA7_RLC7_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L 28134f727eceSLe Ma //SDMA7_RLC7_RB_RPTR_ADDR_HI 28144f727eceSLe Ma #define SDMA7_RLC7_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 28154f727eceSLe Ma #define SDMA7_RLC7_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 28164f727eceSLe Ma //SDMA7_RLC7_RB_RPTR_ADDR_LO 28174f727eceSLe Ma #define SDMA7_RLC7_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 28184f727eceSLe Ma #define SDMA7_RLC7_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 28194f727eceSLe Ma #define SDMA7_RLC7_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L 28204f727eceSLe Ma #define SDMA7_RLC7_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 28214f727eceSLe Ma //SDMA7_RLC7_IB_CNTL 28224f727eceSLe Ma #define SDMA7_RLC7_IB_CNTL__IB_ENABLE__SHIFT 0x0 28234f727eceSLe Ma #define SDMA7_RLC7_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 28244f727eceSLe Ma #define SDMA7_RLC7_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 28254f727eceSLe Ma #define SDMA7_RLC7_IB_CNTL__CMD_VMID__SHIFT 0x10 28264f727eceSLe Ma #define SDMA7_RLC7_IB_CNTL__IB_ENABLE_MASK 0x00000001L 28274f727eceSLe Ma #define SDMA7_RLC7_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L 28284f727eceSLe Ma #define SDMA7_RLC7_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L 28294f727eceSLe Ma #define SDMA7_RLC7_IB_CNTL__CMD_VMID_MASK 0x000F0000L 28304f727eceSLe Ma //SDMA7_RLC7_IB_RPTR 28314f727eceSLe Ma #define SDMA7_RLC7_IB_RPTR__OFFSET__SHIFT 0x2 28324f727eceSLe Ma #define SDMA7_RLC7_IB_RPTR__OFFSET_MASK 0x003FFFFCL 28334f727eceSLe Ma //SDMA7_RLC7_IB_OFFSET 28344f727eceSLe Ma #define SDMA7_RLC7_IB_OFFSET__OFFSET__SHIFT 0x2 28354f727eceSLe Ma #define SDMA7_RLC7_IB_OFFSET__OFFSET_MASK 0x003FFFFCL 28364f727eceSLe Ma //SDMA7_RLC7_IB_BASE_LO 28374f727eceSLe Ma #define SDMA7_RLC7_IB_BASE_LO__ADDR__SHIFT 0x5 28384f727eceSLe Ma #define SDMA7_RLC7_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L 28394f727eceSLe Ma //SDMA7_RLC7_IB_BASE_HI 28404f727eceSLe Ma #define SDMA7_RLC7_IB_BASE_HI__ADDR__SHIFT 0x0 28414f727eceSLe Ma #define SDMA7_RLC7_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL 28424f727eceSLe Ma //SDMA7_RLC7_IB_SIZE 28434f727eceSLe Ma #define SDMA7_RLC7_IB_SIZE__SIZE__SHIFT 0x0 28444f727eceSLe Ma #define SDMA7_RLC7_IB_SIZE__SIZE_MASK 0x000FFFFFL 28454f727eceSLe Ma //SDMA7_RLC7_SKIP_CNTL 28464f727eceSLe Ma #define SDMA7_RLC7_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 28474f727eceSLe Ma #define SDMA7_RLC7_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL 28484f727eceSLe Ma //SDMA7_RLC7_CONTEXT_STATUS 28494f727eceSLe Ma #define SDMA7_RLC7_CONTEXT_STATUS__SELECTED__SHIFT 0x0 28504f727eceSLe Ma #define SDMA7_RLC7_CONTEXT_STATUS__IDLE__SHIFT 0x2 28514f727eceSLe Ma #define SDMA7_RLC7_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 28524f727eceSLe Ma #define SDMA7_RLC7_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 28534f727eceSLe Ma #define SDMA7_RLC7_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 28544f727eceSLe Ma #define SDMA7_RLC7_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 28554f727eceSLe Ma #define SDMA7_RLC7_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 28564f727eceSLe Ma #define SDMA7_RLC7_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa 28574f727eceSLe Ma #define SDMA7_RLC7_CONTEXT_STATUS__SELECTED_MASK 0x00000001L 28584f727eceSLe Ma #define SDMA7_RLC7_CONTEXT_STATUS__IDLE_MASK 0x00000004L 28594f727eceSLe Ma #define SDMA7_RLC7_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L 28604f727eceSLe Ma #define SDMA7_RLC7_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L 28614f727eceSLe Ma #define SDMA7_RLC7_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L 28624f727eceSLe Ma #define SDMA7_RLC7_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L 28634f727eceSLe Ma #define SDMA7_RLC7_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L 28644f727eceSLe Ma #define SDMA7_RLC7_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L 28654f727eceSLe Ma //SDMA7_RLC7_DOORBELL 28664f727eceSLe Ma #define SDMA7_RLC7_DOORBELL__ENABLE__SHIFT 0x1c 28674f727eceSLe Ma #define SDMA7_RLC7_DOORBELL__CAPTURED__SHIFT 0x1e 28684f727eceSLe Ma #define SDMA7_RLC7_DOORBELL__ENABLE_MASK 0x10000000L 28694f727eceSLe Ma #define SDMA7_RLC7_DOORBELL__CAPTURED_MASK 0x40000000L 28704f727eceSLe Ma //SDMA7_RLC7_STATUS 28714f727eceSLe Ma #define SDMA7_RLC7_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 28724f727eceSLe Ma #define SDMA7_RLC7_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 28734f727eceSLe Ma #define SDMA7_RLC7_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL 28744f727eceSLe Ma #define SDMA7_RLC7_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L 28754f727eceSLe Ma //SDMA7_RLC7_DOORBELL_LOG 28764f727eceSLe Ma #define SDMA7_RLC7_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 28774f727eceSLe Ma #define SDMA7_RLC7_DOORBELL_LOG__DATA__SHIFT 0x2 28784f727eceSLe Ma #define SDMA7_RLC7_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L 28794f727eceSLe Ma #define SDMA7_RLC7_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL 28804f727eceSLe Ma //SDMA7_RLC7_WATERMARK 28814f727eceSLe Ma #define SDMA7_RLC7_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 28824f727eceSLe Ma #define SDMA7_RLC7_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 28834f727eceSLe Ma #define SDMA7_RLC7_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL 28844f727eceSLe Ma #define SDMA7_RLC7_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L 28854f727eceSLe Ma //SDMA7_RLC7_DOORBELL_OFFSET 28864f727eceSLe Ma #define SDMA7_RLC7_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 28874f727eceSLe Ma #define SDMA7_RLC7_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL 28884f727eceSLe Ma //SDMA7_RLC7_CSA_ADDR_LO 28894f727eceSLe Ma #define SDMA7_RLC7_CSA_ADDR_LO__ADDR__SHIFT 0x2 28904f727eceSLe Ma #define SDMA7_RLC7_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 28914f727eceSLe Ma //SDMA7_RLC7_CSA_ADDR_HI 28924f727eceSLe Ma #define SDMA7_RLC7_CSA_ADDR_HI__ADDR__SHIFT 0x0 28934f727eceSLe Ma #define SDMA7_RLC7_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 28944f727eceSLe Ma //SDMA7_RLC7_IB_SUB_REMAIN 28954f727eceSLe Ma #define SDMA7_RLC7_IB_SUB_REMAIN__SIZE__SHIFT 0x0 28964f727eceSLe Ma #define SDMA7_RLC7_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL 28974f727eceSLe Ma //SDMA7_RLC7_PREEMPT 28984f727eceSLe Ma #define SDMA7_RLC7_PREEMPT__IB_PREEMPT__SHIFT 0x0 28994f727eceSLe Ma #define SDMA7_RLC7_PREEMPT__IB_PREEMPT_MASK 0x00000001L 29004f727eceSLe Ma //SDMA7_RLC7_DUMMY_REG 29014f727eceSLe Ma #define SDMA7_RLC7_DUMMY_REG__DUMMY__SHIFT 0x0 29024f727eceSLe Ma #define SDMA7_RLC7_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL 29034f727eceSLe Ma //SDMA7_RLC7_RB_WPTR_POLL_ADDR_HI 29044f727eceSLe Ma #define SDMA7_RLC7_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 29054f727eceSLe Ma #define SDMA7_RLC7_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 29064f727eceSLe Ma //SDMA7_RLC7_RB_WPTR_POLL_ADDR_LO 29074f727eceSLe Ma #define SDMA7_RLC7_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 29084f727eceSLe Ma #define SDMA7_RLC7_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 29094f727eceSLe Ma //SDMA7_RLC7_RB_AQL_CNTL 29104f727eceSLe Ma #define SDMA7_RLC7_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 29114f727eceSLe Ma #define SDMA7_RLC7_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 29124f727eceSLe Ma #define SDMA7_RLC7_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 29134f727eceSLe Ma #define SDMA7_RLC7_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L 29144f727eceSLe Ma #define SDMA7_RLC7_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL 29154f727eceSLe Ma #define SDMA7_RLC7_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L 29164f727eceSLe Ma //SDMA7_RLC7_MINOR_PTR_UPDATE 29174f727eceSLe Ma #define SDMA7_RLC7_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 29184f727eceSLe Ma #define SDMA7_RLC7_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L 29194f727eceSLe Ma //SDMA7_RLC7_MIDCMD_DATA0 29204f727eceSLe Ma #define SDMA7_RLC7_MIDCMD_DATA0__DATA0__SHIFT 0x0 29214f727eceSLe Ma #define SDMA7_RLC7_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL 29224f727eceSLe Ma //SDMA7_RLC7_MIDCMD_DATA1 29234f727eceSLe Ma #define SDMA7_RLC7_MIDCMD_DATA1__DATA1__SHIFT 0x0 29244f727eceSLe Ma #define SDMA7_RLC7_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL 29254f727eceSLe Ma //SDMA7_RLC7_MIDCMD_DATA2 29264f727eceSLe Ma #define SDMA7_RLC7_MIDCMD_DATA2__DATA2__SHIFT 0x0 29274f727eceSLe Ma #define SDMA7_RLC7_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL 29284f727eceSLe Ma //SDMA7_RLC7_MIDCMD_DATA3 29294f727eceSLe Ma #define SDMA7_RLC7_MIDCMD_DATA3__DATA3__SHIFT 0x0 29304f727eceSLe Ma #define SDMA7_RLC7_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL 29314f727eceSLe Ma //SDMA7_RLC7_MIDCMD_DATA4 29324f727eceSLe Ma #define SDMA7_RLC7_MIDCMD_DATA4__DATA4__SHIFT 0x0 29334f727eceSLe Ma #define SDMA7_RLC7_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL 29344f727eceSLe Ma //SDMA7_RLC7_MIDCMD_DATA5 29354f727eceSLe Ma #define SDMA7_RLC7_MIDCMD_DATA5__DATA5__SHIFT 0x0 29364f727eceSLe Ma #define SDMA7_RLC7_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL 29374f727eceSLe Ma //SDMA7_RLC7_MIDCMD_DATA6 29384f727eceSLe Ma #define SDMA7_RLC7_MIDCMD_DATA6__DATA6__SHIFT 0x0 29394f727eceSLe Ma #define SDMA7_RLC7_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL 29404f727eceSLe Ma //SDMA7_RLC7_MIDCMD_DATA7 29414f727eceSLe Ma #define SDMA7_RLC7_MIDCMD_DATA7__DATA7__SHIFT 0x0 29424f727eceSLe Ma #define SDMA7_RLC7_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL 29434f727eceSLe Ma //SDMA7_RLC7_MIDCMD_DATA8 29444f727eceSLe Ma #define SDMA7_RLC7_MIDCMD_DATA8__DATA8__SHIFT 0x0 29454f727eceSLe Ma #define SDMA7_RLC7_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL 29464f727eceSLe Ma //SDMA7_RLC7_MIDCMD_CNTL 29474f727eceSLe Ma #define SDMA7_RLC7_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 29484f727eceSLe Ma #define SDMA7_RLC7_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 29494f727eceSLe Ma #define SDMA7_RLC7_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 29504f727eceSLe Ma #define SDMA7_RLC7_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 29514f727eceSLe Ma #define SDMA7_RLC7_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L 29524f727eceSLe Ma #define SDMA7_RLC7_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L 29534f727eceSLe Ma #define SDMA7_RLC7_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L 29544f727eceSLe Ma #define SDMA7_RLC7_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L 29554f727eceSLe Ma 29564f727eceSLe Ma #endif 2957