14f727eceSLe Ma /* 24f727eceSLe Ma * Copyright (C) 2018 Advanced Micro Devices, Inc. 34f727eceSLe Ma * 44f727eceSLe Ma * Permission is hereby granted, free of charge, to any person obtaining a 54f727eceSLe Ma * copy of this software and associated documentation files (the "Software"), 64f727eceSLe Ma * to deal in the Software without restriction, including without limitation 74f727eceSLe Ma * the rights to use, copy, modify, merge, publish, distribute, sublicense, 84f727eceSLe Ma * and/or sell copies of the Software, and to permit persons to whom the 94f727eceSLe Ma * Software is furnished to do so, subject to the following conditions: 104f727eceSLe Ma * 114f727eceSLe Ma * The above copyright notice and this permission notice shall be included 124f727eceSLe Ma * in all copies or substantial portions of the Software. 134f727eceSLe Ma * 144f727eceSLe Ma * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 154f727eceSLe Ma * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 164f727eceSLe Ma * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 174f727eceSLe Ma * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN 184f727eceSLe Ma * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 194f727eceSLe Ma * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 204f727eceSLe Ma */ 214f727eceSLe Ma #ifndef _sdma5_4_2_2_OFFSET_HEADER 224f727eceSLe Ma #define _sdma5_4_2_2_OFFSET_HEADER 234f727eceSLe Ma 244f727eceSLe Ma 254f727eceSLe Ma 264f727eceSLe Ma // addressBlock: sdma5_sdma5dec 274f727eceSLe Ma // base address: 0x7b000 284f727eceSLe Ma #define mmSDMA5_UCODE_ADDR 0x0000 294f727eceSLe Ma #define mmSDMA5_UCODE_ADDR_BASE_IDX 1 304f727eceSLe Ma #define mmSDMA5_UCODE_DATA 0x0001 314f727eceSLe Ma #define mmSDMA5_UCODE_DATA_BASE_IDX 1 324f727eceSLe Ma #define mmSDMA5_VM_CNTL 0x0004 334f727eceSLe Ma #define mmSDMA5_VM_CNTL_BASE_IDX 1 344f727eceSLe Ma #define mmSDMA5_VM_CTX_LO 0x0005 354f727eceSLe Ma #define mmSDMA5_VM_CTX_LO_BASE_IDX 1 364f727eceSLe Ma #define mmSDMA5_VM_CTX_HI 0x0006 374f727eceSLe Ma #define mmSDMA5_VM_CTX_HI_BASE_IDX 1 384f727eceSLe Ma #define mmSDMA5_ACTIVE_FCN_ID 0x0007 394f727eceSLe Ma #define mmSDMA5_ACTIVE_FCN_ID_BASE_IDX 1 404f727eceSLe Ma #define mmSDMA5_VM_CTX_CNTL 0x0008 414f727eceSLe Ma #define mmSDMA5_VM_CTX_CNTL_BASE_IDX 1 424f727eceSLe Ma #define mmSDMA5_VIRT_RESET_REQ 0x0009 434f727eceSLe Ma #define mmSDMA5_VIRT_RESET_REQ_BASE_IDX 1 444f727eceSLe Ma #define mmSDMA5_VF_ENABLE 0x000a 454f727eceSLe Ma #define mmSDMA5_VF_ENABLE_BASE_IDX 1 464f727eceSLe Ma #define mmSDMA5_CONTEXT_REG_TYPE0 0x000b 474f727eceSLe Ma #define mmSDMA5_CONTEXT_REG_TYPE0_BASE_IDX 1 484f727eceSLe Ma #define mmSDMA5_CONTEXT_REG_TYPE1 0x000c 494f727eceSLe Ma #define mmSDMA5_CONTEXT_REG_TYPE1_BASE_IDX 1 504f727eceSLe Ma #define mmSDMA5_CONTEXT_REG_TYPE2 0x000d 514f727eceSLe Ma #define mmSDMA5_CONTEXT_REG_TYPE2_BASE_IDX 1 524f727eceSLe Ma #define mmSDMA5_CONTEXT_REG_TYPE3 0x000e 534f727eceSLe Ma #define mmSDMA5_CONTEXT_REG_TYPE3_BASE_IDX 1 544f727eceSLe Ma #define mmSDMA5_PUB_REG_TYPE0 0x000f 554f727eceSLe Ma #define mmSDMA5_PUB_REG_TYPE0_BASE_IDX 1 564f727eceSLe Ma #define mmSDMA5_PUB_REG_TYPE1 0x0010 574f727eceSLe Ma #define mmSDMA5_PUB_REG_TYPE1_BASE_IDX 1 584f727eceSLe Ma #define mmSDMA5_PUB_REG_TYPE2 0x0011 594f727eceSLe Ma #define mmSDMA5_PUB_REG_TYPE2_BASE_IDX 1 604f727eceSLe Ma #define mmSDMA5_PUB_REG_TYPE3 0x0012 614f727eceSLe Ma #define mmSDMA5_PUB_REG_TYPE3_BASE_IDX 1 624f727eceSLe Ma #define mmSDMA5_MMHUB_CNTL 0x0013 634f727eceSLe Ma #define mmSDMA5_MMHUB_CNTL_BASE_IDX 1 644f727eceSLe Ma #define mmSDMA5_CONTEXT_GROUP_BOUNDARY 0x0019 654f727eceSLe Ma #define mmSDMA5_CONTEXT_GROUP_BOUNDARY_BASE_IDX 1 664f727eceSLe Ma #define mmSDMA5_POWER_CNTL 0x001a 674f727eceSLe Ma #define mmSDMA5_POWER_CNTL_BASE_IDX 1 684f727eceSLe Ma #define mmSDMA5_CLK_CTRL 0x001b 694f727eceSLe Ma #define mmSDMA5_CLK_CTRL_BASE_IDX 1 704f727eceSLe Ma #define mmSDMA5_CNTL 0x001c 714f727eceSLe Ma #define mmSDMA5_CNTL_BASE_IDX 1 724f727eceSLe Ma #define mmSDMA5_CHICKEN_BITS 0x001d 734f727eceSLe Ma #define mmSDMA5_CHICKEN_BITS_BASE_IDX 1 744f727eceSLe Ma #define mmSDMA5_GB_ADDR_CONFIG 0x001e 754f727eceSLe Ma #define mmSDMA5_GB_ADDR_CONFIG_BASE_IDX 1 764f727eceSLe Ma #define mmSDMA5_GB_ADDR_CONFIG_READ 0x001f 774f727eceSLe Ma #define mmSDMA5_GB_ADDR_CONFIG_READ_BASE_IDX 1 784f727eceSLe Ma #define mmSDMA5_RB_RPTR_FETCH_HI 0x0020 794f727eceSLe Ma #define mmSDMA5_RB_RPTR_FETCH_HI_BASE_IDX 1 804f727eceSLe Ma #define mmSDMA5_SEM_WAIT_FAIL_TIMER_CNTL 0x0021 814f727eceSLe Ma #define mmSDMA5_SEM_WAIT_FAIL_TIMER_CNTL_BASE_IDX 1 824f727eceSLe Ma #define mmSDMA5_RB_RPTR_FETCH 0x0022 834f727eceSLe Ma #define mmSDMA5_RB_RPTR_FETCH_BASE_IDX 1 844f727eceSLe Ma #define mmSDMA5_IB_OFFSET_FETCH 0x0023 854f727eceSLe Ma #define mmSDMA5_IB_OFFSET_FETCH_BASE_IDX 1 864f727eceSLe Ma #define mmSDMA5_PROGRAM 0x0024 874f727eceSLe Ma #define mmSDMA5_PROGRAM_BASE_IDX 1 884f727eceSLe Ma #define mmSDMA5_STATUS_REG 0x0025 894f727eceSLe Ma #define mmSDMA5_STATUS_REG_BASE_IDX 1 904f727eceSLe Ma #define mmSDMA5_STATUS1_REG 0x0026 914f727eceSLe Ma #define mmSDMA5_STATUS1_REG_BASE_IDX 1 924f727eceSLe Ma #define mmSDMA5_RD_BURST_CNTL 0x0027 934f727eceSLe Ma #define mmSDMA5_RD_BURST_CNTL_BASE_IDX 1 944f727eceSLe Ma #define mmSDMA5_HBM_PAGE_CONFIG 0x0028 954f727eceSLe Ma #define mmSDMA5_HBM_PAGE_CONFIG_BASE_IDX 1 964f727eceSLe Ma #define mmSDMA5_UCODE_CHECKSUM 0x0029 974f727eceSLe Ma #define mmSDMA5_UCODE_CHECKSUM_BASE_IDX 1 984f727eceSLe Ma #define mmSDMA5_F32_CNTL 0x002a 994f727eceSLe Ma #define mmSDMA5_F32_CNTL_BASE_IDX 1 1004f727eceSLe Ma #define mmSDMA5_FREEZE 0x002b 1014f727eceSLe Ma #define mmSDMA5_FREEZE_BASE_IDX 1 1024f727eceSLe Ma #define mmSDMA5_PHASE0_QUANTUM 0x002c 1034f727eceSLe Ma #define mmSDMA5_PHASE0_QUANTUM_BASE_IDX 1 1044f727eceSLe Ma #define mmSDMA5_PHASE1_QUANTUM 0x002d 1054f727eceSLe Ma #define mmSDMA5_PHASE1_QUANTUM_BASE_IDX 1 1064f727eceSLe Ma #define mmSDMA5_EDC_CONFIG 0x0032 1074f727eceSLe Ma #define mmSDMA5_EDC_CONFIG_BASE_IDX 1 1084f727eceSLe Ma #define mmSDMA5_BA_THRESHOLD 0x0033 1094f727eceSLe Ma #define mmSDMA5_BA_THRESHOLD_BASE_IDX 1 1104f727eceSLe Ma #define mmSDMA5_ID 0x0034 1114f727eceSLe Ma #define mmSDMA5_ID_BASE_IDX 1 1124f727eceSLe Ma #define mmSDMA5_VERSION 0x0035 1134f727eceSLe Ma #define mmSDMA5_VERSION_BASE_IDX 1 1144f727eceSLe Ma #define mmSDMA5_EDC_COUNTER 0x0036 1154f727eceSLe Ma #define mmSDMA5_EDC_COUNTER_BASE_IDX 1 1164f727eceSLe Ma #define mmSDMA5_EDC_COUNTER_CLEAR 0x0037 1174f727eceSLe Ma #define mmSDMA5_EDC_COUNTER_CLEAR_BASE_IDX 1 1184f727eceSLe Ma #define mmSDMA5_STATUS2_REG 0x0038 1194f727eceSLe Ma #define mmSDMA5_STATUS2_REG_BASE_IDX 1 1204f727eceSLe Ma #define mmSDMA5_ATOMIC_CNTL 0x0039 1214f727eceSLe Ma #define mmSDMA5_ATOMIC_CNTL_BASE_IDX 1 1224f727eceSLe Ma #define mmSDMA5_ATOMIC_PREOP_LO 0x003a 1234f727eceSLe Ma #define mmSDMA5_ATOMIC_PREOP_LO_BASE_IDX 1 1244f727eceSLe Ma #define mmSDMA5_ATOMIC_PREOP_HI 0x003b 1254f727eceSLe Ma #define mmSDMA5_ATOMIC_PREOP_HI_BASE_IDX 1 1264f727eceSLe Ma #define mmSDMA5_UTCL1_CNTL 0x003c 1274f727eceSLe Ma #define mmSDMA5_UTCL1_CNTL_BASE_IDX 1 1284f727eceSLe Ma #define mmSDMA5_UTCL1_WATERMK 0x003d 1294f727eceSLe Ma #define mmSDMA5_UTCL1_WATERMK_BASE_IDX 1 1304f727eceSLe Ma #define mmSDMA5_UTCL1_RD_STATUS 0x003e 1314f727eceSLe Ma #define mmSDMA5_UTCL1_RD_STATUS_BASE_IDX 1 1324f727eceSLe Ma #define mmSDMA5_UTCL1_WR_STATUS 0x003f 1334f727eceSLe Ma #define mmSDMA5_UTCL1_WR_STATUS_BASE_IDX 1 1344f727eceSLe Ma #define mmSDMA5_UTCL1_INV0 0x0040 1354f727eceSLe Ma #define mmSDMA5_UTCL1_INV0_BASE_IDX 1 1364f727eceSLe Ma #define mmSDMA5_UTCL1_INV1 0x0041 1374f727eceSLe Ma #define mmSDMA5_UTCL1_INV1_BASE_IDX 1 1384f727eceSLe Ma #define mmSDMA5_UTCL1_INV2 0x0042 1394f727eceSLe Ma #define mmSDMA5_UTCL1_INV2_BASE_IDX 1 1404f727eceSLe Ma #define mmSDMA5_UTCL1_RD_XNACK0 0x0043 1414f727eceSLe Ma #define mmSDMA5_UTCL1_RD_XNACK0_BASE_IDX 1 1424f727eceSLe Ma #define mmSDMA5_UTCL1_RD_XNACK1 0x0044 1434f727eceSLe Ma #define mmSDMA5_UTCL1_RD_XNACK1_BASE_IDX 1 1444f727eceSLe Ma #define mmSDMA5_UTCL1_WR_XNACK0 0x0045 1454f727eceSLe Ma #define mmSDMA5_UTCL1_WR_XNACK0_BASE_IDX 1 1464f727eceSLe Ma #define mmSDMA5_UTCL1_WR_XNACK1 0x0046 1474f727eceSLe Ma #define mmSDMA5_UTCL1_WR_XNACK1_BASE_IDX 1 1484f727eceSLe Ma #define mmSDMA5_UTCL1_TIMEOUT 0x0047 1494f727eceSLe Ma #define mmSDMA5_UTCL1_TIMEOUT_BASE_IDX 1 1504f727eceSLe Ma #define mmSDMA5_UTCL1_PAGE 0x0048 1514f727eceSLe Ma #define mmSDMA5_UTCL1_PAGE_BASE_IDX 1 1524f727eceSLe Ma #define mmSDMA5_POWER_CNTL_IDLE 0x0049 1534f727eceSLe Ma #define mmSDMA5_POWER_CNTL_IDLE_BASE_IDX 1 1544f727eceSLe Ma #define mmSDMA5_RELAX_ORDERING_LUT 0x004a 1554f727eceSLe Ma #define mmSDMA5_RELAX_ORDERING_LUT_BASE_IDX 1 1564f727eceSLe Ma #define mmSDMA5_CHICKEN_BITS_2 0x004b 1574f727eceSLe Ma #define mmSDMA5_CHICKEN_BITS_2_BASE_IDX 1 1584f727eceSLe Ma #define mmSDMA5_STATUS3_REG 0x004c 1594f727eceSLe Ma #define mmSDMA5_STATUS3_REG_BASE_IDX 1 1604f727eceSLe Ma #define mmSDMA5_PHYSICAL_ADDR_LO 0x004d 1614f727eceSLe Ma #define mmSDMA5_PHYSICAL_ADDR_LO_BASE_IDX 1 1624f727eceSLe Ma #define mmSDMA5_PHYSICAL_ADDR_HI 0x004e 1634f727eceSLe Ma #define mmSDMA5_PHYSICAL_ADDR_HI_BASE_IDX 1 1644f727eceSLe Ma #define mmSDMA5_PHASE2_QUANTUM 0x004f 1654f727eceSLe Ma #define mmSDMA5_PHASE2_QUANTUM_BASE_IDX 1 1664f727eceSLe Ma #define mmSDMA5_ERROR_LOG 0x0050 1674f727eceSLe Ma #define mmSDMA5_ERROR_LOG_BASE_IDX 1 1684f727eceSLe Ma #define mmSDMA5_PUB_DUMMY_REG0 0x0051 1694f727eceSLe Ma #define mmSDMA5_PUB_DUMMY_REG0_BASE_IDX 1 1704f727eceSLe Ma #define mmSDMA5_PUB_DUMMY_REG1 0x0052 1714f727eceSLe Ma #define mmSDMA5_PUB_DUMMY_REG1_BASE_IDX 1 1724f727eceSLe Ma #define mmSDMA5_PUB_DUMMY_REG2 0x0053 1734f727eceSLe Ma #define mmSDMA5_PUB_DUMMY_REG2_BASE_IDX 1 1744f727eceSLe Ma #define mmSDMA5_PUB_DUMMY_REG3 0x0054 1754f727eceSLe Ma #define mmSDMA5_PUB_DUMMY_REG3_BASE_IDX 1 1764f727eceSLe Ma #define mmSDMA5_F32_COUNTER 0x0055 1774f727eceSLe Ma #define mmSDMA5_F32_COUNTER_BASE_IDX 1 1784f727eceSLe Ma #define mmSDMA5_UNBREAKABLE 0x0056 1794f727eceSLe Ma #define mmSDMA5_UNBREAKABLE_BASE_IDX 1 1804f727eceSLe Ma #define mmSDMA5_PERFMON_CNTL 0x0057 1814f727eceSLe Ma #define mmSDMA5_PERFMON_CNTL_BASE_IDX 1 1824f727eceSLe Ma #define mmSDMA5_PERFCOUNTER0_RESULT 0x0058 1834f727eceSLe Ma #define mmSDMA5_PERFCOUNTER0_RESULT_BASE_IDX 1 1844f727eceSLe Ma #define mmSDMA5_PERFCOUNTER1_RESULT 0x0059 1854f727eceSLe Ma #define mmSDMA5_PERFCOUNTER1_RESULT_BASE_IDX 1 1864f727eceSLe Ma #define mmSDMA5_PERFCOUNTER_TAG_DELAY_RANGE 0x005a 1874f727eceSLe Ma #define mmSDMA5_PERFCOUNTER_TAG_DELAY_RANGE_BASE_IDX 1 1884f727eceSLe Ma #define mmSDMA5_CRD_CNTL 0x005b 1894f727eceSLe Ma #define mmSDMA5_CRD_CNTL_BASE_IDX 1 1904f727eceSLe Ma #define mmSDMA5_GPU_IOV_VIOLATION_LOG 0x005d 1914f727eceSLe Ma #define mmSDMA5_GPU_IOV_VIOLATION_LOG_BASE_IDX 1 1924f727eceSLe Ma #define mmSDMA5_ULV_CNTL 0x005e 1934f727eceSLe Ma #define mmSDMA5_ULV_CNTL_BASE_IDX 1 1944f727eceSLe Ma #define mmSDMA5_EA_DBIT_ADDR_DATA 0x0060 1954f727eceSLe Ma #define mmSDMA5_EA_DBIT_ADDR_DATA_BASE_IDX 1 1964f727eceSLe Ma #define mmSDMA5_EA_DBIT_ADDR_INDEX 0x0061 1974f727eceSLe Ma #define mmSDMA5_EA_DBIT_ADDR_INDEX_BASE_IDX 1 1984f727eceSLe Ma #define mmSDMA5_GPU_IOV_VIOLATION_LOG2 0x0062 1994f727eceSLe Ma #define mmSDMA5_GPU_IOV_VIOLATION_LOG2_BASE_IDX 1 2004f727eceSLe Ma #define mmSDMA5_GFX_RB_CNTL 0x0080 2014f727eceSLe Ma #define mmSDMA5_GFX_RB_CNTL_BASE_IDX 1 2024f727eceSLe Ma #define mmSDMA5_GFX_RB_BASE 0x0081 2034f727eceSLe Ma #define mmSDMA5_GFX_RB_BASE_BASE_IDX 1 2044f727eceSLe Ma #define mmSDMA5_GFX_RB_BASE_HI 0x0082 2054f727eceSLe Ma #define mmSDMA5_GFX_RB_BASE_HI_BASE_IDX 1 2064f727eceSLe Ma #define mmSDMA5_GFX_RB_RPTR 0x0083 2074f727eceSLe Ma #define mmSDMA5_GFX_RB_RPTR_BASE_IDX 1 2084f727eceSLe Ma #define mmSDMA5_GFX_RB_RPTR_HI 0x0084 2094f727eceSLe Ma #define mmSDMA5_GFX_RB_RPTR_HI_BASE_IDX 1 2104f727eceSLe Ma #define mmSDMA5_GFX_RB_WPTR 0x0085 2114f727eceSLe Ma #define mmSDMA5_GFX_RB_WPTR_BASE_IDX 1 2124f727eceSLe Ma #define mmSDMA5_GFX_RB_WPTR_HI 0x0086 2134f727eceSLe Ma #define mmSDMA5_GFX_RB_WPTR_HI_BASE_IDX 1 2144f727eceSLe Ma #define mmSDMA5_GFX_RB_WPTR_POLL_CNTL 0x0087 2154f727eceSLe Ma #define mmSDMA5_GFX_RB_WPTR_POLL_CNTL_BASE_IDX 1 2164f727eceSLe Ma #define mmSDMA5_GFX_RB_RPTR_ADDR_HI 0x0088 2174f727eceSLe Ma #define mmSDMA5_GFX_RB_RPTR_ADDR_HI_BASE_IDX 1 2184f727eceSLe Ma #define mmSDMA5_GFX_RB_RPTR_ADDR_LO 0x0089 2194f727eceSLe Ma #define mmSDMA5_GFX_RB_RPTR_ADDR_LO_BASE_IDX 1 2204f727eceSLe Ma #define mmSDMA5_GFX_IB_CNTL 0x008a 2214f727eceSLe Ma #define mmSDMA5_GFX_IB_CNTL_BASE_IDX 1 2224f727eceSLe Ma #define mmSDMA5_GFX_IB_RPTR 0x008b 2234f727eceSLe Ma #define mmSDMA5_GFX_IB_RPTR_BASE_IDX 1 2244f727eceSLe Ma #define mmSDMA5_GFX_IB_OFFSET 0x008c 2254f727eceSLe Ma #define mmSDMA5_GFX_IB_OFFSET_BASE_IDX 1 2264f727eceSLe Ma #define mmSDMA5_GFX_IB_BASE_LO 0x008d 2274f727eceSLe Ma #define mmSDMA5_GFX_IB_BASE_LO_BASE_IDX 1 2284f727eceSLe Ma #define mmSDMA5_GFX_IB_BASE_HI 0x008e 2294f727eceSLe Ma #define mmSDMA5_GFX_IB_BASE_HI_BASE_IDX 1 2304f727eceSLe Ma #define mmSDMA5_GFX_IB_SIZE 0x008f 2314f727eceSLe Ma #define mmSDMA5_GFX_IB_SIZE_BASE_IDX 1 2324f727eceSLe Ma #define mmSDMA5_GFX_SKIP_CNTL 0x0090 2334f727eceSLe Ma #define mmSDMA5_GFX_SKIP_CNTL_BASE_IDX 1 2344f727eceSLe Ma #define mmSDMA5_GFX_CONTEXT_STATUS 0x0091 2354f727eceSLe Ma #define mmSDMA5_GFX_CONTEXT_STATUS_BASE_IDX 1 2364f727eceSLe Ma #define mmSDMA5_GFX_DOORBELL 0x0092 2374f727eceSLe Ma #define mmSDMA5_GFX_DOORBELL_BASE_IDX 1 2384f727eceSLe Ma #define mmSDMA5_GFX_CONTEXT_CNTL 0x0093 2394f727eceSLe Ma #define mmSDMA5_GFX_CONTEXT_CNTL_BASE_IDX 1 2404f727eceSLe Ma #define mmSDMA5_GFX_STATUS 0x00a8 2414f727eceSLe Ma #define mmSDMA5_GFX_STATUS_BASE_IDX 1 2424f727eceSLe Ma #define mmSDMA5_GFX_DOORBELL_LOG 0x00a9 2434f727eceSLe Ma #define mmSDMA5_GFX_DOORBELL_LOG_BASE_IDX 1 2444f727eceSLe Ma #define mmSDMA5_GFX_WATERMARK 0x00aa 2454f727eceSLe Ma #define mmSDMA5_GFX_WATERMARK_BASE_IDX 1 2464f727eceSLe Ma #define mmSDMA5_GFX_DOORBELL_OFFSET 0x00ab 2474f727eceSLe Ma #define mmSDMA5_GFX_DOORBELL_OFFSET_BASE_IDX 1 2484f727eceSLe Ma #define mmSDMA5_GFX_CSA_ADDR_LO 0x00ac 2494f727eceSLe Ma #define mmSDMA5_GFX_CSA_ADDR_LO_BASE_IDX 1 2504f727eceSLe Ma #define mmSDMA5_GFX_CSA_ADDR_HI 0x00ad 2514f727eceSLe Ma #define mmSDMA5_GFX_CSA_ADDR_HI_BASE_IDX 1 2524f727eceSLe Ma #define mmSDMA5_GFX_IB_SUB_REMAIN 0x00af 2534f727eceSLe Ma #define mmSDMA5_GFX_IB_SUB_REMAIN_BASE_IDX 1 2544f727eceSLe Ma #define mmSDMA5_GFX_PREEMPT 0x00b0 2554f727eceSLe Ma #define mmSDMA5_GFX_PREEMPT_BASE_IDX 1 2564f727eceSLe Ma #define mmSDMA5_GFX_DUMMY_REG 0x00b1 2574f727eceSLe Ma #define mmSDMA5_GFX_DUMMY_REG_BASE_IDX 1 2584f727eceSLe Ma #define mmSDMA5_GFX_RB_WPTR_POLL_ADDR_HI 0x00b2 2594f727eceSLe Ma #define mmSDMA5_GFX_RB_WPTR_POLL_ADDR_HI_BASE_IDX 1 2604f727eceSLe Ma #define mmSDMA5_GFX_RB_WPTR_POLL_ADDR_LO 0x00b3 2614f727eceSLe Ma #define mmSDMA5_GFX_RB_WPTR_POLL_ADDR_LO_BASE_IDX 1 2624f727eceSLe Ma #define mmSDMA5_GFX_RB_AQL_CNTL 0x00b4 2634f727eceSLe Ma #define mmSDMA5_GFX_RB_AQL_CNTL_BASE_IDX 1 2644f727eceSLe Ma #define mmSDMA5_GFX_MINOR_PTR_UPDATE 0x00b5 2654f727eceSLe Ma #define mmSDMA5_GFX_MINOR_PTR_UPDATE_BASE_IDX 1 2664f727eceSLe Ma #define mmSDMA5_GFX_MIDCMD_DATA0 0x00c0 2674f727eceSLe Ma #define mmSDMA5_GFX_MIDCMD_DATA0_BASE_IDX 1 2684f727eceSLe Ma #define mmSDMA5_GFX_MIDCMD_DATA1 0x00c1 2694f727eceSLe Ma #define mmSDMA5_GFX_MIDCMD_DATA1_BASE_IDX 1 2704f727eceSLe Ma #define mmSDMA5_GFX_MIDCMD_DATA2 0x00c2 2714f727eceSLe Ma #define mmSDMA5_GFX_MIDCMD_DATA2_BASE_IDX 1 2724f727eceSLe Ma #define mmSDMA5_GFX_MIDCMD_DATA3 0x00c3 2734f727eceSLe Ma #define mmSDMA5_GFX_MIDCMD_DATA3_BASE_IDX 1 2744f727eceSLe Ma #define mmSDMA5_GFX_MIDCMD_DATA4 0x00c4 2754f727eceSLe Ma #define mmSDMA5_GFX_MIDCMD_DATA4_BASE_IDX 1 2764f727eceSLe Ma #define mmSDMA5_GFX_MIDCMD_DATA5 0x00c5 2774f727eceSLe Ma #define mmSDMA5_GFX_MIDCMD_DATA5_BASE_IDX 1 2784f727eceSLe Ma #define mmSDMA5_GFX_MIDCMD_DATA6 0x00c6 2794f727eceSLe Ma #define mmSDMA5_GFX_MIDCMD_DATA6_BASE_IDX 1 2804f727eceSLe Ma #define mmSDMA5_GFX_MIDCMD_DATA7 0x00c7 2814f727eceSLe Ma #define mmSDMA5_GFX_MIDCMD_DATA7_BASE_IDX 1 2824f727eceSLe Ma #define mmSDMA5_GFX_MIDCMD_DATA8 0x00c8 2834f727eceSLe Ma #define mmSDMA5_GFX_MIDCMD_DATA8_BASE_IDX 1 2844f727eceSLe Ma #define mmSDMA5_GFX_MIDCMD_CNTL 0x00c9 2854f727eceSLe Ma #define mmSDMA5_GFX_MIDCMD_CNTL_BASE_IDX 1 2864f727eceSLe Ma #define mmSDMA5_PAGE_RB_CNTL 0x00d8 2874f727eceSLe Ma #define mmSDMA5_PAGE_RB_CNTL_BASE_IDX 1 2884f727eceSLe Ma #define mmSDMA5_PAGE_RB_BASE 0x00d9 2894f727eceSLe Ma #define mmSDMA5_PAGE_RB_BASE_BASE_IDX 1 2904f727eceSLe Ma #define mmSDMA5_PAGE_RB_BASE_HI 0x00da 2914f727eceSLe Ma #define mmSDMA5_PAGE_RB_BASE_HI_BASE_IDX 1 2924f727eceSLe Ma #define mmSDMA5_PAGE_RB_RPTR 0x00db 2934f727eceSLe Ma #define mmSDMA5_PAGE_RB_RPTR_BASE_IDX 1 2944f727eceSLe Ma #define mmSDMA5_PAGE_RB_RPTR_HI 0x00dc 2954f727eceSLe Ma #define mmSDMA5_PAGE_RB_RPTR_HI_BASE_IDX 1 2964f727eceSLe Ma #define mmSDMA5_PAGE_RB_WPTR 0x00dd 2974f727eceSLe Ma #define mmSDMA5_PAGE_RB_WPTR_BASE_IDX 1 2984f727eceSLe Ma #define mmSDMA5_PAGE_RB_WPTR_HI 0x00de 2994f727eceSLe Ma #define mmSDMA5_PAGE_RB_WPTR_HI_BASE_IDX 1 3004f727eceSLe Ma #define mmSDMA5_PAGE_RB_WPTR_POLL_CNTL 0x00df 3014f727eceSLe Ma #define mmSDMA5_PAGE_RB_WPTR_POLL_CNTL_BASE_IDX 1 3024f727eceSLe Ma #define mmSDMA5_PAGE_RB_RPTR_ADDR_HI 0x00e0 3034f727eceSLe Ma #define mmSDMA5_PAGE_RB_RPTR_ADDR_HI_BASE_IDX 1 3044f727eceSLe Ma #define mmSDMA5_PAGE_RB_RPTR_ADDR_LO 0x00e1 3054f727eceSLe Ma #define mmSDMA5_PAGE_RB_RPTR_ADDR_LO_BASE_IDX 1 3064f727eceSLe Ma #define mmSDMA5_PAGE_IB_CNTL 0x00e2 3074f727eceSLe Ma #define mmSDMA5_PAGE_IB_CNTL_BASE_IDX 1 3084f727eceSLe Ma #define mmSDMA5_PAGE_IB_RPTR 0x00e3 3094f727eceSLe Ma #define mmSDMA5_PAGE_IB_RPTR_BASE_IDX 1 3104f727eceSLe Ma #define mmSDMA5_PAGE_IB_OFFSET 0x00e4 3114f727eceSLe Ma #define mmSDMA5_PAGE_IB_OFFSET_BASE_IDX 1 3124f727eceSLe Ma #define mmSDMA5_PAGE_IB_BASE_LO 0x00e5 3134f727eceSLe Ma #define mmSDMA5_PAGE_IB_BASE_LO_BASE_IDX 1 3144f727eceSLe Ma #define mmSDMA5_PAGE_IB_BASE_HI 0x00e6 3154f727eceSLe Ma #define mmSDMA5_PAGE_IB_BASE_HI_BASE_IDX 1 3164f727eceSLe Ma #define mmSDMA5_PAGE_IB_SIZE 0x00e7 3174f727eceSLe Ma #define mmSDMA5_PAGE_IB_SIZE_BASE_IDX 1 3184f727eceSLe Ma #define mmSDMA5_PAGE_SKIP_CNTL 0x00e8 3194f727eceSLe Ma #define mmSDMA5_PAGE_SKIP_CNTL_BASE_IDX 1 3204f727eceSLe Ma #define mmSDMA5_PAGE_CONTEXT_STATUS 0x00e9 3214f727eceSLe Ma #define mmSDMA5_PAGE_CONTEXT_STATUS_BASE_IDX 1 3224f727eceSLe Ma #define mmSDMA5_PAGE_DOORBELL 0x00ea 3234f727eceSLe Ma #define mmSDMA5_PAGE_DOORBELL_BASE_IDX 1 3244f727eceSLe Ma #define mmSDMA5_PAGE_STATUS 0x0100 3254f727eceSLe Ma #define mmSDMA5_PAGE_STATUS_BASE_IDX 1 3264f727eceSLe Ma #define mmSDMA5_PAGE_DOORBELL_LOG 0x0101 3274f727eceSLe Ma #define mmSDMA5_PAGE_DOORBELL_LOG_BASE_IDX 1 3284f727eceSLe Ma #define mmSDMA5_PAGE_WATERMARK 0x0102 3294f727eceSLe Ma #define mmSDMA5_PAGE_WATERMARK_BASE_IDX 1 3304f727eceSLe Ma #define mmSDMA5_PAGE_DOORBELL_OFFSET 0x0103 3314f727eceSLe Ma #define mmSDMA5_PAGE_DOORBELL_OFFSET_BASE_IDX 1 3324f727eceSLe Ma #define mmSDMA5_PAGE_CSA_ADDR_LO 0x0104 3334f727eceSLe Ma #define mmSDMA5_PAGE_CSA_ADDR_LO_BASE_IDX 1 3344f727eceSLe Ma #define mmSDMA5_PAGE_CSA_ADDR_HI 0x0105 3354f727eceSLe Ma #define mmSDMA5_PAGE_CSA_ADDR_HI_BASE_IDX 1 3364f727eceSLe Ma #define mmSDMA5_PAGE_IB_SUB_REMAIN 0x0107 3374f727eceSLe Ma #define mmSDMA5_PAGE_IB_SUB_REMAIN_BASE_IDX 1 3384f727eceSLe Ma #define mmSDMA5_PAGE_PREEMPT 0x0108 3394f727eceSLe Ma #define mmSDMA5_PAGE_PREEMPT_BASE_IDX 1 3404f727eceSLe Ma #define mmSDMA5_PAGE_DUMMY_REG 0x0109 3414f727eceSLe Ma #define mmSDMA5_PAGE_DUMMY_REG_BASE_IDX 1 3424f727eceSLe Ma #define mmSDMA5_PAGE_RB_WPTR_POLL_ADDR_HI 0x010a 3434f727eceSLe Ma #define mmSDMA5_PAGE_RB_WPTR_POLL_ADDR_HI_BASE_IDX 1 3444f727eceSLe Ma #define mmSDMA5_PAGE_RB_WPTR_POLL_ADDR_LO 0x010b 3454f727eceSLe Ma #define mmSDMA5_PAGE_RB_WPTR_POLL_ADDR_LO_BASE_IDX 1 3464f727eceSLe Ma #define mmSDMA5_PAGE_RB_AQL_CNTL 0x010c 3474f727eceSLe Ma #define mmSDMA5_PAGE_RB_AQL_CNTL_BASE_IDX 1 3484f727eceSLe Ma #define mmSDMA5_PAGE_MINOR_PTR_UPDATE 0x010d 3494f727eceSLe Ma #define mmSDMA5_PAGE_MINOR_PTR_UPDATE_BASE_IDX 1 3504f727eceSLe Ma #define mmSDMA5_PAGE_MIDCMD_DATA0 0x0118 3514f727eceSLe Ma #define mmSDMA5_PAGE_MIDCMD_DATA0_BASE_IDX 1 3524f727eceSLe Ma #define mmSDMA5_PAGE_MIDCMD_DATA1 0x0119 3534f727eceSLe Ma #define mmSDMA5_PAGE_MIDCMD_DATA1_BASE_IDX 1 3544f727eceSLe Ma #define mmSDMA5_PAGE_MIDCMD_DATA2 0x011a 3554f727eceSLe Ma #define mmSDMA5_PAGE_MIDCMD_DATA2_BASE_IDX 1 3564f727eceSLe Ma #define mmSDMA5_PAGE_MIDCMD_DATA3 0x011b 3574f727eceSLe Ma #define mmSDMA5_PAGE_MIDCMD_DATA3_BASE_IDX 1 3584f727eceSLe Ma #define mmSDMA5_PAGE_MIDCMD_DATA4 0x011c 3594f727eceSLe Ma #define mmSDMA5_PAGE_MIDCMD_DATA4_BASE_IDX 1 3604f727eceSLe Ma #define mmSDMA5_PAGE_MIDCMD_DATA5 0x011d 3614f727eceSLe Ma #define mmSDMA5_PAGE_MIDCMD_DATA5_BASE_IDX 1 3624f727eceSLe Ma #define mmSDMA5_PAGE_MIDCMD_DATA6 0x011e 3634f727eceSLe Ma #define mmSDMA5_PAGE_MIDCMD_DATA6_BASE_IDX 1 3644f727eceSLe Ma #define mmSDMA5_PAGE_MIDCMD_DATA7 0x011f 3654f727eceSLe Ma #define mmSDMA5_PAGE_MIDCMD_DATA7_BASE_IDX 1 3664f727eceSLe Ma #define mmSDMA5_PAGE_MIDCMD_DATA8 0x0120 3674f727eceSLe Ma #define mmSDMA5_PAGE_MIDCMD_DATA8_BASE_IDX 1 3684f727eceSLe Ma #define mmSDMA5_PAGE_MIDCMD_CNTL 0x0121 3694f727eceSLe Ma #define mmSDMA5_PAGE_MIDCMD_CNTL_BASE_IDX 1 3704f727eceSLe Ma #define mmSDMA5_RLC0_RB_CNTL 0x0130 3714f727eceSLe Ma #define mmSDMA5_RLC0_RB_CNTL_BASE_IDX 1 3724f727eceSLe Ma #define mmSDMA5_RLC0_RB_BASE 0x0131 3734f727eceSLe Ma #define mmSDMA5_RLC0_RB_BASE_BASE_IDX 1 3744f727eceSLe Ma #define mmSDMA5_RLC0_RB_BASE_HI 0x0132 3754f727eceSLe Ma #define mmSDMA5_RLC0_RB_BASE_HI_BASE_IDX 1 3764f727eceSLe Ma #define mmSDMA5_RLC0_RB_RPTR 0x0133 3774f727eceSLe Ma #define mmSDMA5_RLC0_RB_RPTR_BASE_IDX 1 3784f727eceSLe Ma #define mmSDMA5_RLC0_RB_RPTR_HI 0x0134 3794f727eceSLe Ma #define mmSDMA5_RLC0_RB_RPTR_HI_BASE_IDX 1 3804f727eceSLe Ma #define mmSDMA5_RLC0_RB_WPTR 0x0135 3814f727eceSLe Ma #define mmSDMA5_RLC0_RB_WPTR_BASE_IDX 1 3824f727eceSLe Ma #define mmSDMA5_RLC0_RB_WPTR_HI 0x0136 3834f727eceSLe Ma #define mmSDMA5_RLC0_RB_WPTR_HI_BASE_IDX 1 3844f727eceSLe Ma #define mmSDMA5_RLC0_RB_WPTR_POLL_CNTL 0x0137 3854f727eceSLe Ma #define mmSDMA5_RLC0_RB_WPTR_POLL_CNTL_BASE_IDX 1 3864f727eceSLe Ma #define mmSDMA5_RLC0_RB_RPTR_ADDR_HI 0x0138 3874f727eceSLe Ma #define mmSDMA5_RLC0_RB_RPTR_ADDR_HI_BASE_IDX 1 3884f727eceSLe Ma #define mmSDMA5_RLC0_RB_RPTR_ADDR_LO 0x0139 3894f727eceSLe Ma #define mmSDMA5_RLC0_RB_RPTR_ADDR_LO_BASE_IDX 1 3904f727eceSLe Ma #define mmSDMA5_RLC0_IB_CNTL 0x013a 3914f727eceSLe Ma #define mmSDMA5_RLC0_IB_CNTL_BASE_IDX 1 3924f727eceSLe Ma #define mmSDMA5_RLC0_IB_RPTR 0x013b 3934f727eceSLe Ma #define mmSDMA5_RLC0_IB_RPTR_BASE_IDX 1 3944f727eceSLe Ma #define mmSDMA5_RLC0_IB_OFFSET 0x013c 3954f727eceSLe Ma #define mmSDMA5_RLC0_IB_OFFSET_BASE_IDX 1 3964f727eceSLe Ma #define mmSDMA5_RLC0_IB_BASE_LO 0x013d 3974f727eceSLe Ma #define mmSDMA5_RLC0_IB_BASE_LO_BASE_IDX 1 3984f727eceSLe Ma #define mmSDMA5_RLC0_IB_BASE_HI 0x013e 3994f727eceSLe Ma #define mmSDMA5_RLC0_IB_BASE_HI_BASE_IDX 1 4004f727eceSLe Ma #define mmSDMA5_RLC0_IB_SIZE 0x013f 4014f727eceSLe Ma #define mmSDMA5_RLC0_IB_SIZE_BASE_IDX 1 4024f727eceSLe Ma #define mmSDMA5_RLC0_SKIP_CNTL 0x0140 4034f727eceSLe Ma #define mmSDMA5_RLC0_SKIP_CNTL_BASE_IDX 1 4044f727eceSLe Ma #define mmSDMA5_RLC0_CONTEXT_STATUS 0x0141 4054f727eceSLe Ma #define mmSDMA5_RLC0_CONTEXT_STATUS_BASE_IDX 1 4064f727eceSLe Ma #define mmSDMA5_RLC0_DOORBELL 0x0142 4074f727eceSLe Ma #define mmSDMA5_RLC0_DOORBELL_BASE_IDX 1 4084f727eceSLe Ma #define mmSDMA5_RLC0_STATUS 0x0158 4094f727eceSLe Ma #define mmSDMA5_RLC0_STATUS_BASE_IDX 1 4104f727eceSLe Ma #define mmSDMA5_RLC0_DOORBELL_LOG 0x0159 4114f727eceSLe Ma #define mmSDMA5_RLC0_DOORBELL_LOG_BASE_IDX 1 4124f727eceSLe Ma #define mmSDMA5_RLC0_WATERMARK 0x015a 4134f727eceSLe Ma #define mmSDMA5_RLC0_WATERMARK_BASE_IDX 1 4144f727eceSLe Ma #define mmSDMA5_RLC0_DOORBELL_OFFSET 0x015b 4154f727eceSLe Ma #define mmSDMA5_RLC0_DOORBELL_OFFSET_BASE_IDX 1 4164f727eceSLe Ma #define mmSDMA5_RLC0_CSA_ADDR_LO 0x015c 4174f727eceSLe Ma #define mmSDMA5_RLC0_CSA_ADDR_LO_BASE_IDX 1 4184f727eceSLe Ma #define mmSDMA5_RLC0_CSA_ADDR_HI 0x015d 4194f727eceSLe Ma #define mmSDMA5_RLC0_CSA_ADDR_HI_BASE_IDX 1 4204f727eceSLe Ma #define mmSDMA5_RLC0_IB_SUB_REMAIN 0x015f 4214f727eceSLe Ma #define mmSDMA5_RLC0_IB_SUB_REMAIN_BASE_IDX 1 4224f727eceSLe Ma #define mmSDMA5_RLC0_PREEMPT 0x0160 4234f727eceSLe Ma #define mmSDMA5_RLC0_PREEMPT_BASE_IDX 1 4244f727eceSLe Ma #define mmSDMA5_RLC0_DUMMY_REG 0x0161 4254f727eceSLe Ma #define mmSDMA5_RLC0_DUMMY_REG_BASE_IDX 1 4264f727eceSLe Ma #define mmSDMA5_RLC0_RB_WPTR_POLL_ADDR_HI 0x0162 4274f727eceSLe Ma #define mmSDMA5_RLC0_RB_WPTR_POLL_ADDR_HI_BASE_IDX 1 4284f727eceSLe Ma #define mmSDMA5_RLC0_RB_WPTR_POLL_ADDR_LO 0x0163 4294f727eceSLe Ma #define mmSDMA5_RLC0_RB_WPTR_POLL_ADDR_LO_BASE_IDX 1 4304f727eceSLe Ma #define mmSDMA5_RLC0_RB_AQL_CNTL 0x0164 4314f727eceSLe Ma #define mmSDMA5_RLC0_RB_AQL_CNTL_BASE_IDX 1 4324f727eceSLe Ma #define mmSDMA5_RLC0_MINOR_PTR_UPDATE 0x0165 4334f727eceSLe Ma #define mmSDMA5_RLC0_MINOR_PTR_UPDATE_BASE_IDX 1 4344f727eceSLe Ma #define mmSDMA5_RLC0_MIDCMD_DATA0 0x0170 4354f727eceSLe Ma #define mmSDMA5_RLC0_MIDCMD_DATA0_BASE_IDX 1 4364f727eceSLe Ma #define mmSDMA5_RLC0_MIDCMD_DATA1 0x0171 4374f727eceSLe Ma #define mmSDMA5_RLC0_MIDCMD_DATA1_BASE_IDX 1 4384f727eceSLe Ma #define mmSDMA5_RLC0_MIDCMD_DATA2 0x0172 4394f727eceSLe Ma #define mmSDMA5_RLC0_MIDCMD_DATA2_BASE_IDX 1 4404f727eceSLe Ma #define mmSDMA5_RLC0_MIDCMD_DATA3 0x0173 4414f727eceSLe Ma #define mmSDMA5_RLC0_MIDCMD_DATA3_BASE_IDX 1 4424f727eceSLe Ma #define mmSDMA5_RLC0_MIDCMD_DATA4 0x0174 4434f727eceSLe Ma #define mmSDMA5_RLC0_MIDCMD_DATA4_BASE_IDX 1 4444f727eceSLe Ma #define mmSDMA5_RLC0_MIDCMD_DATA5 0x0175 4454f727eceSLe Ma #define mmSDMA5_RLC0_MIDCMD_DATA5_BASE_IDX 1 4464f727eceSLe Ma #define mmSDMA5_RLC0_MIDCMD_DATA6 0x0176 4474f727eceSLe Ma #define mmSDMA5_RLC0_MIDCMD_DATA6_BASE_IDX 1 4484f727eceSLe Ma #define mmSDMA5_RLC0_MIDCMD_DATA7 0x0177 4494f727eceSLe Ma #define mmSDMA5_RLC0_MIDCMD_DATA7_BASE_IDX 1 4504f727eceSLe Ma #define mmSDMA5_RLC0_MIDCMD_DATA8 0x0178 4514f727eceSLe Ma #define mmSDMA5_RLC0_MIDCMD_DATA8_BASE_IDX 1 4524f727eceSLe Ma #define mmSDMA5_RLC0_MIDCMD_CNTL 0x0179 4534f727eceSLe Ma #define mmSDMA5_RLC0_MIDCMD_CNTL_BASE_IDX 1 4544f727eceSLe Ma #define mmSDMA5_RLC1_RB_CNTL 0x0188 4554f727eceSLe Ma #define mmSDMA5_RLC1_RB_CNTL_BASE_IDX 1 4564f727eceSLe Ma #define mmSDMA5_RLC1_RB_BASE 0x0189 4574f727eceSLe Ma #define mmSDMA5_RLC1_RB_BASE_BASE_IDX 1 4584f727eceSLe Ma #define mmSDMA5_RLC1_RB_BASE_HI 0x018a 4594f727eceSLe Ma #define mmSDMA5_RLC1_RB_BASE_HI_BASE_IDX 1 4604f727eceSLe Ma #define mmSDMA5_RLC1_RB_RPTR 0x018b 4614f727eceSLe Ma #define mmSDMA5_RLC1_RB_RPTR_BASE_IDX 1 4624f727eceSLe Ma #define mmSDMA5_RLC1_RB_RPTR_HI 0x018c 4634f727eceSLe Ma #define mmSDMA5_RLC1_RB_RPTR_HI_BASE_IDX 1 4644f727eceSLe Ma #define mmSDMA5_RLC1_RB_WPTR 0x018d 4654f727eceSLe Ma #define mmSDMA5_RLC1_RB_WPTR_BASE_IDX 1 4664f727eceSLe Ma #define mmSDMA5_RLC1_RB_WPTR_HI 0x018e 4674f727eceSLe Ma #define mmSDMA5_RLC1_RB_WPTR_HI_BASE_IDX 1 4684f727eceSLe Ma #define mmSDMA5_RLC1_RB_WPTR_POLL_CNTL 0x018f 4694f727eceSLe Ma #define mmSDMA5_RLC1_RB_WPTR_POLL_CNTL_BASE_IDX 1 4704f727eceSLe Ma #define mmSDMA5_RLC1_RB_RPTR_ADDR_HI 0x0190 4714f727eceSLe Ma #define mmSDMA5_RLC1_RB_RPTR_ADDR_HI_BASE_IDX 1 4724f727eceSLe Ma #define mmSDMA5_RLC1_RB_RPTR_ADDR_LO 0x0191 4734f727eceSLe Ma #define mmSDMA5_RLC1_RB_RPTR_ADDR_LO_BASE_IDX 1 4744f727eceSLe Ma #define mmSDMA5_RLC1_IB_CNTL 0x0192 4754f727eceSLe Ma #define mmSDMA5_RLC1_IB_CNTL_BASE_IDX 1 4764f727eceSLe Ma #define mmSDMA5_RLC1_IB_RPTR 0x0193 4774f727eceSLe Ma #define mmSDMA5_RLC1_IB_RPTR_BASE_IDX 1 4784f727eceSLe Ma #define mmSDMA5_RLC1_IB_OFFSET 0x0194 4794f727eceSLe Ma #define mmSDMA5_RLC1_IB_OFFSET_BASE_IDX 1 4804f727eceSLe Ma #define mmSDMA5_RLC1_IB_BASE_LO 0x0195 4814f727eceSLe Ma #define mmSDMA5_RLC1_IB_BASE_LO_BASE_IDX 1 4824f727eceSLe Ma #define mmSDMA5_RLC1_IB_BASE_HI 0x0196 4834f727eceSLe Ma #define mmSDMA5_RLC1_IB_BASE_HI_BASE_IDX 1 4844f727eceSLe Ma #define mmSDMA5_RLC1_IB_SIZE 0x0197 4854f727eceSLe Ma #define mmSDMA5_RLC1_IB_SIZE_BASE_IDX 1 4864f727eceSLe Ma #define mmSDMA5_RLC1_SKIP_CNTL 0x0198 4874f727eceSLe Ma #define mmSDMA5_RLC1_SKIP_CNTL_BASE_IDX 1 4884f727eceSLe Ma #define mmSDMA5_RLC1_CONTEXT_STATUS 0x0199 4894f727eceSLe Ma #define mmSDMA5_RLC1_CONTEXT_STATUS_BASE_IDX 1 4904f727eceSLe Ma #define mmSDMA5_RLC1_DOORBELL 0x019a 4914f727eceSLe Ma #define mmSDMA5_RLC1_DOORBELL_BASE_IDX 1 4924f727eceSLe Ma #define mmSDMA5_RLC1_STATUS 0x01b0 4934f727eceSLe Ma #define mmSDMA5_RLC1_STATUS_BASE_IDX 1 4944f727eceSLe Ma #define mmSDMA5_RLC1_DOORBELL_LOG 0x01b1 4954f727eceSLe Ma #define mmSDMA5_RLC1_DOORBELL_LOG_BASE_IDX 1 4964f727eceSLe Ma #define mmSDMA5_RLC1_WATERMARK 0x01b2 4974f727eceSLe Ma #define mmSDMA5_RLC1_WATERMARK_BASE_IDX 1 4984f727eceSLe Ma #define mmSDMA5_RLC1_DOORBELL_OFFSET 0x01b3 4994f727eceSLe Ma #define mmSDMA5_RLC1_DOORBELL_OFFSET_BASE_IDX 1 5004f727eceSLe Ma #define mmSDMA5_RLC1_CSA_ADDR_LO 0x01b4 5014f727eceSLe Ma #define mmSDMA5_RLC1_CSA_ADDR_LO_BASE_IDX 1 5024f727eceSLe Ma #define mmSDMA5_RLC1_CSA_ADDR_HI 0x01b5 5034f727eceSLe Ma #define mmSDMA5_RLC1_CSA_ADDR_HI_BASE_IDX 1 5044f727eceSLe Ma #define mmSDMA5_RLC1_IB_SUB_REMAIN 0x01b7 5054f727eceSLe Ma #define mmSDMA5_RLC1_IB_SUB_REMAIN_BASE_IDX 1 5064f727eceSLe Ma #define mmSDMA5_RLC1_PREEMPT 0x01b8 5074f727eceSLe Ma #define mmSDMA5_RLC1_PREEMPT_BASE_IDX 1 5084f727eceSLe Ma #define mmSDMA5_RLC1_DUMMY_REG 0x01b9 5094f727eceSLe Ma #define mmSDMA5_RLC1_DUMMY_REG_BASE_IDX 1 5104f727eceSLe Ma #define mmSDMA5_RLC1_RB_WPTR_POLL_ADDR_HI 0x01ba 5114f727eceSLe Ma #define mmSDMA5_RLC1_RB_WPTR_POLL_ADDR_HI_BASE_IDX 1 5124f727eceSLe Ma #define mmSDMA5_RLC1_RB_WPTR_POLL_ADDR_LO 0x01bb 5134f727eceSLe Ma #define mmSDMA5_RLC1_RB_WPTR_POLL_ADDR_LO_BASE_IDX 1 5144f727eceSLe Ma #define mmSDMA5_RLC1_RB_AQL_CNTL 0x01bc 5154f727eceSLe Ma #define mmSDMA5_RLC1_RB_AQL_CNTL_BASE_IDX 1 5164f727eceSLe Ma #define mmSDMA5_RLC1_MINOR_PTR_UPDATE 0x01bd 5174f727eceSLe Ma #define mmSDMA5_RLC1_MINOR_PTR_UPDATE_BASE_IDX 1 5184f727eceSLe Ma #define mmSDMA5_RLC1_MIDCMD_DATA0 0x01c8 5194f727eceSLe Ma #define mmSDMA5_RLC1_MIDCMD_DATA0_BASE_IDX 1 5204f727eceSLe Ma #define mmSDMA5_RLC1_MIDCMD_DATA1 0x01c9 5214f727eceSLe Ma #define mmSDMA5_RLC1_MIDCMD_DATA1_BASE_IDX 1 5224f727eceSLe Ma #define mmSDMA5_RLC1_MIDCMD_DATA2 0x01ca 5234f727eceSLe Ma #define mmSDMA5_RLC1_MIDCMD_DATA2_BASE_IDX 1 5244f727eceSLe Ma #define mmSDMA5_RLC1_MIDCMD_DATA3 0x01cb 5254f727eceSLe Ma #define mmSDMA5_RLC1_MIDCMD_DATA3_BASE_IDX 1 5264f727eceSLe Ma #define mmSDMA5_RLC1_MIDCMD_DATA4 0x01cc 5274f727eceSLe Ma #define mmSDMA5_RLC1_MIDCMD_DATA4_BASE_IDX 1 5284f727eceSLe Ma #define mmSDMA5_RLC1_MIDCMD_DATA5 0x01cd 5294f727eceSLe Ma #define mmSDMA5_RLC1_MIDCMD_DATA5_BASE_IDX 1 5304f727eceSLe Ma #define mmSDMA5_RLC1_MIDCMD_DATA6 0x01ce 5314f727eceSLe Ma #define mmSDMA5_RLC1_MIDCMD_DATA6_BASE_IDX 1 5324f727eceSLe Ma #define mmSDMA5_RLC1_MIDCMD_DATA7 0x01cf 5334f727eceSLe Ma #define mmSDMA5_RLC1_MIDCMD_DATA7_BASE_IDX 1 5344f727eceSLe Ma #define mmSDMA5_RLC1_MIDCMD_DATA8 0x01d0 5354f727eceSLe Ma #define mmSDMA5_RLC1_MIDCMD_DATA8_BASE_IDX 1 5364f727eceSLe Ma #define mmSDMA5_RLC1_MIDCMD_CNTL 0x01d1 5374f727eceSLe Ma #define mmSDMA5_RLC1_MIDCMD_CNTL_BASE_IDX 1 5384f727eceSLe Ma #define mmSDMA5_RLC2_RB_CNTL 0x01e0 5394f727eceSLe Ma #define mmSDMA5_RLC2_RB_CNTL_BASE_IDX 1 5404f727eceSLe Ma #define mmSDMA5_RLC2_RB_BASE 0x01e1 5414f727eceSLe Ma #define mmSDMA5_RLC2_RB_BASE_BASE_IDX 1 5424f727eceSLe Ma #define mmSDMA5_RLC2_RB_BASE_HI 0x01e2 5434f727eceSLe Ma #define mmSDMA5_RLC2_RB_BASE_HI_BASE_IDX 1 5444f727eceSLe Ma #define mmSDMA5_RLC2_RB_RPTR 0x01e3 5454f727eceSLe Ma #define mmSDMA5_RLC2_RB_RPTR_BASE_IDX 1 5464f727eceSLe Ma #define mmSDMA5_RLC2_RB_RPTR_HI 0x01e4 5474f727eceSLe Ma #define mmSDMA5_RLC2_RB_RPTR_HI_BASE_IDX 1 5484f727eceSLe Ma #define mmSDMA5_RLC2_RB_WPTR 0x01e5 5494f727eceSLe Ma #define mmSDMA5_RLC2_RB_WPTR_BASE_IDX 1 5504f727eceSLe Ma #define mmSDMA5_RLC2_RB_WPTR_HI 0x01e6 5514f727eceSLe Ma #define mmSDMA5_RLC2_RB_WPTR_HI_BASE_IDX 1 5524f727eceSLe Ma #define mmSDMA5_RLC2_RB_WPTR_POLL_CNTL 0x01e7 5534f727eceSLe Ma #define mmSDMA5_RLC2_RB_WPTR_POLL_CNTL_BASE_IDX 1 5544f727eceSLe Ma #define mmSDMA5_RLC2_RB_RPTR_ADDR_HI 0x01e8 5554f727eceSLe Ma #define mmSDMA5_RLC2_RB_RPTR_ADDR_HI_BASE_IDX 1 5564f727eceSLe Ma #define mmSDMA5_RLC2_RB_RPTR_ADDR_LO 0x01e9 5574f727eceSLe Ma #define mmSDMA5_RLC2_RB_RPTR_ADDR_LO_BASE_IDX 1 5584f727eceSLe Ma #define mmSDMA5_RLC2_IB_CNTL 0x01ea 5594f727eceSLe Ma #define mmSDMA5_RLC2_IB_CNTL_BASE_IDX 1 5604f727eceSLe Ma #define mmSDMA5_RLC2_IB_RPTR 0x01eb 5614f727eceSLe Ma #define mmSDMA5_RLC2_IB_RPTR_BASE_IDX 1 5624f727eceSLe Ma #define mmSDMA5_RLC2_IB_OFFSET 0x01ec 5634f727eceSLe Ma #define mmSDMA5_RLC2_IB_OFFSET_BASE_IDX 1 5644f727eceSLe Ma #define mmSDMA5_RLC2_IB_BASE_LO 0x01ed 5654f727eceSLe Ma #define mmSDMA5_RLC2_IB_BASE_LO_BASE_IDX 1 5664f727eceSLe Ma #define mmSDMA5_RLC2_IB_BASE_HI 0x01ee 5674f727eceSLe Ma #define mmSDMA5_RLC2_IB_BASE_HI_BASE_IDX 1 5684f727eceSLe Ma #define mmSDMA5_RLC2_IB_SIZE 0x01ef 5694f727eceSLe Ma #define mmSDMA5_RLC2_IB_SIZE_BASE_IDX 1 5704f727eceSLe Ma #define mmSDMA5_RLC2_SKIP_CNTL 0x01f0 5714f727eceSLe Ma #define mmSDMA5_RLC2_SKIP_CNTL_BASE_IDX 1 5724f727eceSLe Ma #define mmSDMA5_RLC2_CONTEXT_STATUS 0x01f1 5734f727eceSLe Ma #define mmSDMA5_RLC2_CONTEXT_STATUS_BASE_IDX 1 5744f727eceSLe Ma #define mmSDMA5_RLC2_DOORBELL 0x01f2 5754f727eceSLe Ma #define mmSDMA5_RLC2_DOORBELL_BASE_IDX 1 5764f727eceSLe Ma #define mmSDMA5_RLC2_STATUS 0x0208 5774f727eceSLe Ma #define mmSDMA5_RLC2_STATUS_BASE_IDX 1 5784f727eceSLe Ma #define mmSDMA5_RLC2_DOORBELL_LOG 0x0209 5794f727eceSLe Ma #define mmSDMA5_RLC2_DOORBELL_LOG_BASE_IDX 1 5804f727eceSLe Ma #define mmSDMA5_RLC2_WATERMARK 0x020a 5814f727eceSLe Ma #define mmSDMA5_RLC2_WATERMARK_BASE_IDX 1 5824f727eceSLe Ma #define mmSDMA5_RLC2_DOORBELL_OFFSET 0x020b 5834f727eceSLe Ma #define mmSDMA5_RLC2_DOORBELL_OFFSET_BASE_IDX 1 5844f727eceSLe Ma #define mmSDMA5_RLC2_CSA_ADDR_LO 0x020c 5854f727eceSLe Ma #define mmSDMA5_RLC2_CSA_ADDR_LO_BASE_IDX 1 5864f727eceSLe Ma #define mmSDMA5_RLC2_CSA_ADDR_HI 0x020d 5874f727eceSLe Ma #define mmSDMA5_RLC2_CSA_ADDR_HI_BASE_IDX 1 5884f727eceSLe Ma #define mmSDMA5_RLC2_IB_SUB_REMAIN 0x020f 5894f727eceSLe Ma #define mmSDMA5_RLC2_IB_SUB_REMAIN_BASE_IDX 1 5904f727eceSLe Ma #define mmSDMA5_RLC2_PREEMPT 0x0210 5914f727eceSLe Ma #define mmSDMA5_RLC2_PREEMPT_BASE_IDX 1 5924f727eceSLe Ma #define mmSDMA5_RLC2_DUMMY_REG 0x0211 5934f727eceSLe Ma #define mmSDMA5_RLC2_DUMMY_REG_BASE_IDX 1 5944f727eceSLe Ma #define mmSDMA5_RLC2_RB_WPTR_POLL_ADDR_HI 0x0212 5954f727eceSLe Ma #define mmSDMA5_RLC2_RB_WPTR_POLL_ADDR_HI_BASE_IDX 1 5964f727eceSLe Ma #define mmSDMA5_RLC2_RB_WPTR_POLL_ADDR_LO 0x0213 5974f727eceSLe Ma #define mmSDMA5_RLC2_RB_WPTR_POLL_ADDR_LO_BASE_IDX 1 5984f727eceSLe Ma #define mmSDMA5_RLC2_RB_AQL_CNTL 0x0214 5994f727eceSLe Ma #define mmSDMA5_RLC2_RB_AQL_CNTL_BASE_IDX 1 6004f727eceSLe Ma #define mmSDMA5_RLC2_MINOR_PTR_UPDATE 0x0215 6014f727eceSLe Ma #define mmSDMA5_RLC2_MINOR_PTR_UPDATE_BASE_IDX 1 6024f727eceSLe Ma #define mmSDMA5_RLC2_MIDCMD_DATA0 0x0220 6034f727eceSLe Ma #define mmSDMA5_RLC2_MIDCMD_DATA0_BASE_IDX 1 6044f727eceSLe Ma #define mmSDMA5_RLC2_MIDCMD_DATA1 0x0221 6054f727eceSLe Ma #define mmSDMA5_RLC2_MIDCMD_DATA1_BASE_IDX 1 6064f727eceSLe Ma #define mmSDMA5_RLC2_MIDCMD_DATA2 0x0222 6074f727eceSLe Ma #define mmSDMA5_RLC2_MIDCMD_DATA2_BASE_IDX 1 6084f727eceSLe Ma #define mmSDMA5_RLC2_MIDCMD_DATA3 0x0223 6094f727eceSLe Ma #define mmSDMA5_RLC2_MIDCMD_DATA3_BASE_IDX 1 6104f727eceSLe Ma #define mmSDMA5_RLC2_MIDCMD_DATA4 0x0224 6114f727eceSLe Ma #define mmSDMA5_RLC2_MIDCMD_DATA4_BASE_IDX 1 6124f727eceSLe Ma #define mmSDMA5_RLC2_MIDCMD_DATA5 0x0225 6134f727eceSLe Ma #define mmSDMA5_RLC2_MIDCMD_DATA5_BASE_IDX 1 6144f727eceSLe Ma #define mmSDMA5_RLC2_MIDCMD_DATA6 0x0226 6154f727eceSLe Ma #define mmSDMA5_RLC2_MIDCMD_DATA6_BASE_IDX 1 6164f727eceSLe Ma #define mmSDMA5_RLC2_MIDCMD_DATA7 0x0227 6174f727eceSLe Ma #define mmSDMA5_RLC2_MIDCMD_DATA7_BASE_IDX 1 6184f727eceSLe Ma #define mmSDMA5_RLC2_MIDCMD_DATA8 0x0228 6194f727eceSLe Ma #define mmSDMA5_RLC2_MIDCMD_DATA8_BASE_IDX 1 6204f727eceSLe Ma #define mmSDMA5_RLC2_MIDCMD_CNTL 0x0229 6214f727eceSLe Ma #define mmSDMA5_RLC2_MIDCMD_CNTL_BASE_IDX 1 6224f727eceSLe Ma #define mmSDMA5_RLC3_RB_CNTL 0x0238 6234f727eceSLe Ma #define mmSDMA5_RLC3_RB_CNTL_BASE_IDX 1 6244f727eceSLe Ma #define mmSDMA5_RLC3_RB_BASE 0x0239 6254f727eceSLe Ma #define mmSDMA5_RLC3_RB_BASE_BASE_IDX 1 6264f727eceSLe Ma #define mmSDMA5_RLC3_RB_BASE_HI 0x023a 6274f727eceSLe Ma #define mmSDMA5_RLC3_RB_BASE_HI_BASE_IDX 1 6284f727eceSLe Ma #define mmSDMA5_RLC3_RB_RPTR 0x023b 6294f727eceSLe Ma #define mmSDMA5_RLC3_RB_RPTR_BASE_IDX 1 6304f727eceSLe Ma #define mmSDMA5_RLC3_RB_RPTR_HI 0x023c 6314f727eceSLe Ma #define mmSDMA5_RLC3_RB_RPTR_HI_BASE_IDX 1 6324f727eceSLe Ma #define mmSDMA5_RLC3_RB_WPTR 0x023d 6334f727eceSLe Ma #define mmSDMA5_RLC3_RB_WPTR_BASE_IDX 1 6344f727eceSLe Ma #define mmSDMA5_RLC3_RB_WPTR_HI 0x023e 6354f727eceSLe Ma #define mmSDMA5_RLC3_RB_WPTR_HI_BASE_IDX 1 6364f727eceSLe Ma #define mmSDMA5_RLC3_RB_WPTR_POLL_CNTL 0x023f 6374f727eceSLe Ma #define mmSDMA5_RLC3_RB_WPTR_POLL_CNTL_BASE_IDX 1 6384f727eceSLe Ma #define mmSDMA5_RLC3_RB_RPTR_ADDR_HI 0x0240 6394f727eceSLe Ma #define mmSDMA5_RLC3_RB_RPTR_ADDR_HI_BASE_IDX 1 6404f727eceSLe Ma #define mmSDMA5_RLC3_RB_RPTR_ADDR_LO 0x0241 6414f727eceSLe Ma #define mmSDMA5_RLC3_RB_RPTR_ADDR_LO_BASE_IDX 1 6424f727eceSLe Ma #define mmSDMA5_RLC3_IB_CNTL 0x0242 6434f727eceSLe Ma #define mmSDMA5_RLC3_IB_CNTL_BASE_IDX 1 6444f727eceSLe Ma #define mmSDMA5_RLC3_IB_RPTR 0x0243 6454f727eceSLe Ma #define mmSDMA5_RLC3_IB_RPTR_BASE_IDX 1 6464f727eceSLe Ma #define mmSDMA5_RLC3_IB_OFFSET 0x0244 6474f727eceSLe Ma #define mmSDMA5_RLC3_IB_OFFSET_BASE_IDX 1 6484f727eceSLe Ma #define mmSDMA5_RLC3_IB_BASE_LO 0x0245 6494f727eceSLe Ma #define mmSDMA5_RLC3_IB_BASE_LO_BASE_IDX 1 6504f727eceSLe Ma #define mmSDMA5_RLC3_IB_BASE_HI 0x0246 6514f727eceSLe Ma #define mmSDMA5_RLC3_IB_BASE_HI_BASE_IDX 1 6524f727eceSLe Ma #define mmSDMA5_RLC3_IB_SIZE 0x0247 6534f727eceSLe Ma #define mmSDMA5_RLC3_IB_SIZE_BASE_IDX 1 6544f727eceSLe Ma #define mmSDMA5_RLC3_SKIP_CNTL 0x0248 6554f727eceSLe Ma #define mmSDMA5_RLC3_SKIP_CNTL_BASE_IDX 1 6564f727eceSLe Ma #define mmSDMA5_RLC3_CONTEXT_STATUS 0x0249 6574f727eceSLe Ma #define mmSDMA5_RLC3_CONTEXT_STATUS_BASE_IDX 1 6584f727eceSLe Ma #define mmSDMA5_RLC3_DOORBELL 0x024a 6594f727eceSLe Ma #define mmSDMA5_RLC3_DOORBELL_BASE_IDX 1 6604f727eceSLe Ma #define mmSDMA5_RLC3_STATUS 0x0260 6614f727eceSLe Ma #define mmSDMA5_RLC3_STATUS_BASE_IDX 1 6624f727eceSLe Ma #define mmSDMA5_RLC3_DOORBELL_LOG 0x0261 6634f727eceSLe Ma #define mmSDMA5_RLC3_DOORBELL_LOG_BASE_IDX 1 6644f727eceSLe Ma #define mmSDMA5_RLC3_WATERMARK 0x0262 6654f727eceSLe Ma #define mmSDMA5_RLC3_WATERMARK_BASE_IDX 1 6664f727eceSLe Ma #define mmSDMA5_RLC3_DOORBELL_OFFSET 0x0263 6674f727eceSLe Ma #define mmSDMA5_RLC3_DOORBELL_OFFSET_BASE_IDX 1 6684f727eceSLe Ma #define mmSDMA5_RLC3_CSA_ADDR_LO 0x0264 6694f727eceSLe Ma #define mmSDMA5_RLC3_CSA_ADDR_LO_BASE_IDX 1 6704f727eceSLe Ma #define mmSDMA5_RLC3_CSA_ADDR_HI 0x0265 6714f727eceSLe Ma #define mmSDMA5_RLC3_CSA_ADDR_HI_BASE_IDX 1 6724f727eceSLe Ma #define mmSDMA5_RLC3_IB_SUB_REMAIN 0x0267 6734f727eceSLe Ma #define mmSDMA5_RLC3_IB_SUB_REMAIN_BASE_IDX 1 6744f727eceSLe Ma #define mmSDMA5_RLC3_PREEMPT 0x0268 6754f727eceSLe Ma #define mmSDMA5_RLC3_PREEMPT_BASE_IDX 1 6764f727eceSLe Ma #define mmSDMA5_RLC3_DUMMY_REG 0x0269 6774f727eceSLe Ma #define mmSDMA5_RLC3_DUMMY_REG_BASE_IDX 1 6784f727eceSLe Ma #define mmSDMA5_RLC3_RB_WPTR_POLL_ADDR_HI 0x026a 6794f727eceSLe Ma #define mmSDMA5_RLC3_RB_WPTR_POLL_ADDR_HI_BASE_IDX 1 6804f727eceSLe Ma #define mmSDMA5_RLC3_RB_WPTR_POLL_ADDR_LO 0x026b 6814f727eceSLe Ma #define mmSDMA5_RLC3_RB_WPTR_POLL_ADDR_LO_BASE_IDX 1 6824f727eceSLe Ma #define mmSDMA5_RLC3_RB_AQL_CNTL 0x026c 6834f727eceSLe Ma #define mmSDMA5_RLC3_RB_AQL_CNTL_BASE_IDX 1 6844f727eceSLe Ma #define mmSDMA5_RLC3_MINOR_PTR_UPDATE 0x026d 6854f727eceSLe Ma #define mmSDMA5_RLC3_MINOR_PTR_UPDATE_BASE_IDX 1 6864f727eceSLe Ma #define mmSDMA5_RLC3_MIDCMD_DATA0 0x0278 6874f727eceSLe Ma #define mmSDMA5_RLC3_MIDCMD_DATA0_BASE_IDX 1 6884f727eceSLe Ma #define mmSDMA5_RLC3_MIDCMD_DATA1 0x0279 6894f727eceSLe Ma #define mmSDMA5_RLC3_MIDCMD_DATA1_BASE_IDX 1 6904f727eceSLe Ma #define mmSDMA5_RLC3_MIDCMD_DATA2 0x027a 6914f727eceSLe Ma #define mmSDMA5_RLC3_MIDCMD_DATA2_BASE_IDX 1 6924f727eceSLe Ma #define mmSDMA5_RLC3_MIDCMD_DATA3 0x027b 6934f727eceSLe Ma #define mmSDMA5_RLC3_MIDCMD_DATA3_BASE_IDX 1 6944f727eceSLe Ma #define mmSDMA5_RLC3_MIDCMD_DATA4 0x027c 6954f727eceSLe Ma #define mmSDMA5_RLC3_MIDCMD_DATA4_BASE_IDX 1 6964f727eceSLe Ma #define mmSDMA5_RLC3_MIDCMD_DATA5 0x027d 6974f727eceSLe Ma #define mmSDMA5_RLC3_MIDCMD_DATA5_BASE_IDX 1 6984f727eceSLe Ma #define mmSDMA5_RLC3_MIDCMD_DATA6 0x027e 6994f727eceSLe Ma #define mmSDMA5_RLC3_MIDCMD_DATA6_BASE_IDX 1 7004f727eceSLe Ma #define mmSDMA5_RLC3_MIDCMD_DATA7 0x027f 7014f727eceSLe Ma #define mmSDMA5_RLC3_MIDCMD_DATA7_BASE_IDX 1 7024f727eceSLe Ma #define mmSDMA5_RLC3_MIDCMD_DATA8 0x0280 7034f727eceSLe Ma #define mmSDMA5_RLC3_MIDCMD_DATA8_BASE_IDX 1 7044f727eceSLe Ma #define mmSDMA5_RLC3_MIDCMD_CNTL 0x0281 7054f727eceSLe Ma #define mmSDMA5_RLC3_MIDCMD_CNTL_BASE_IDX 1 7064f727eceSLe Ma #define mmSDMA5_RLC4_RB_CNTL 0x0290 7074f727eceSLe Ma #define mmSDMA5_RLC4_RB_CNTL_BASE_IDX 1 7084f727eceSLe Ma #define mmSDMA5_RLC4_RB_BASE 0x0291 7094f727eceSLe Ma #define mmSDMA5_RLC4_RB_BASE_BASE_IDX 1 7104f727eceSLe Ma #define mmSDMA5_RLC4_RB_BASE_HI 0x0292 7114f727eceSLe Ma #define mmSDMA5_RLC4_RB_BASE_HI_BASE_IDX 1 7124f727eceSLe Ma #define mmSDMA5_RLC4_RB_RPTR 0x0293 7134f727eceSLe Ma #define mmSDMA5_RLC4_RB_RPTR_BASE_IDX 1 7144f727eceSLe Ma #define mmSDMA5_RLC4_RB_RPTR_HI 0x0294 7154f727eceSLe Ma #define mmSDMA5_RLC4_RB_RPTR_HI_BASE_IDX 1 7164f727eceSLe Ma #define mmSDMA5_RLC4_RB_WPTR 0x0295 7174f727eceSLe Ma #define mmSDMA5_RLC4_RB_WPTR_BASE_IDX 1 7184f727eceSLe Ma #define mmSDMA5_RLC4_RB_WPTR_HI 0x0296 7194f727eceSLe Ma #define mmSDMA5_RLC4_RB_WPTR_HI_BASE_IDX 1 7204f727eceSLe Ma #define mmSDMA5_RLC4_RB_WPTR_POLL_CNTL 0x0297 7214f727eceSLe Ma #define mmSDMA5_RLC4_RB_WPTR_POLL_CNTL_BASE_IDX 1 7224f727eceSLe Ma #define mmSDMA5_RLC4_RB_RPTR_ADDR_HI 0x0298 7234f727eceSLe Ma #define mmSDMA5_RLC4_RB_RPTR_ADDR_HI_BASE_IDX 1 7244f727eceSLe Ma #define mmSDMA5_RLC4_RB_RPTR_ADDR_LO 0x0299 7254f727eceSLe Ma #define mmSDMA5_RLC4_RB_RPTR_ADDR_LO_BASE_IDX 1 7264f727eceSLe Ma #define mmSDMA5_RLC4_IB_CNTL 0x029a 7274f727eceSLe Ma #define mmSDMA5_RLC4_IB_CNTL_BASE_IDX 1 7284f727eceSLe Ma #define mmSDMA5_RLC4_IB_RPTR 0x029b 7294f727eceSLe Ma #define mmSDMA5_RLC4_IB_RPTR_BASE_IDX 1 7304f727eceSLe Ma #define mmSDMA5_RLC4_IB_OFFSET 0x029c 7314f727eceSLe Ma #define mmSDMA5_RLC4_IB_OFFSET_BASE_IDX 1 7324f727eceSLe Ma #define mmSDMA5_RLC4_IB_BASE_LO 0x029d 7334f727eceSLe Ma #define mmSDMA5_RLC4_IB_BASE_LO_BASE_IDX 1 7344f727eceSLe Ma #define mmSDMA5_RLC4_IB_BASE_HI 0x029e 7354f727eceSLe Ma #define mmSDMA5_RLC4_IB_BASE_HI_BASE_IDX 1 7364f727eceSLe Ma #define mmSDMA5_RLC4_IB_SIZE 0x029f 7374f727eceSLe Ma #define mmSDMA5_RLC4_IB_SIZE_BASE_IDX 1 7384f727eceSLe Ma #define mmSDMA5_RLC4_SKIP_CNTL 0x02a0 7394f727eceSLe Ma #define mmSDMA5_RLC4_SKIP_CNTL_BASE_IDX 1 7404f727eceSLe Ma #define mmSDMA5_RLC4_CONTEXT_STATUS 0x02a1 7414f727eceSLe Ma #define mmSDMA5_RLC4_CONTEXT_STATUS_BASE_IDX 1 7424f727eceSLe Ma #define mmSDMA5_RLC4_DOORBELL 0x02a2 7434f727eceSLe Ma #define mmSDMA5_RLC4_DOORBELL_BASE_IDX 1 7444f727eceSLe Ma #define mmSDMA5_RLC4_STATUS 0x02b8 7454f727eceSLe Ma #define mmSDMA5_RLC4_STATUS_BASE_IDX 1 7464f727eceSLe Ma #define mmSDMA5_RLC4_DOORBELL_LOG 0x02b9 7474f727eceSLe Ma #define mmSDMA5_RLC4_DOORBELL_LOG_BASE_IDX 1 7484f727eceSLe Ma #define mmSDMA5_RLC4_WATERMARK 0x02ba 7494f727eceSLe Ma #define mmSDMA5_RLC4_WATERMARK_BASE_IDX 1 7504f727eceSLe Ma #define mmSDMA5_RLC4_DOORBELL_OFFSET 0x02bb 7514f727eceSLe Ma #define mmSDMA5_RLC4_DOORBELL_OFFSET_BASE_IDX 1 7524f727eceSLe Ma #define mmSDMA5_RLC4_CSA_ADDR_LO 0x02bc 7534f727eceSLe Ma #define mmSDMA5_RLC4_CSA_ADDR_LO_BASE_IDX 1 7544f727eceSLe Ma #define mmSDMA5_RLC4_CSA_ADDR_HI 0x02bd 7554f727eceSLe Ma #define mmSDMA5_RLC4_CSA_ADDR_HI_BASE_IDX 1 7564f727eceSLe Ma #define mmSDMA5_RLC4_IB_SUB_REMAIN 0x02bf 7574f727eceSLe Ma #define mmSDMA5_RLC4_IB_SUB_REMAIN_BASE_IDX 1 7584f727eceSLe Ma #define mmSDMA5_RLC4_PREEMPT 0x02c0 7594f727eceSLe Ma #define mmSDMA5_RLC4_PREEMPT_BASE_IDX 1 7604f727eceSLe Ma #define mmSDMA5_RLC4_DUMMY_REG 0x02c1 7614f727eceSLe Ma #define mmSDMA5_RLC4_DUMMY_REG_BASE_IDX 1 7624f727eceSLe Ma #define mmSDMA5_RLC4_RB_WPTR_POLL_ADDR_HI 0x02c2 7634f727eceSLe Ma #define mmSDMA5_RLC4_RB_WPTR_POLL_ADDR_HI_BASE_IDX 1 7644f727eceSLe Ma #define mmSDMA5_RLC4_RB_WPTR_POLL_ADDR_LO 0x02c3 7654f727eceSLe Ma #define mmSDMA5_RLC4_RB_WPTR_POLL_ADDR_LO_BASE_IDX 1 7664f727eceSLe Ma #define mmSDMA5_RLC4_RB_AQL_CNTL 0x02c4 7674f727eceSLe Ma #define mmSDMA5_RLC4_RB_AQL_CNTL_BASE_IDX 1 7684f727eceSLe Ma #define mmSDMA5_RLC4_MINOR_PTR_UPDATE 0x02c5 7694f727eceSLe Ma #define mmSDMA5_RLC4_MINOR_PTR_UPDATE_BASE_IDX 1 7704f727eceSLe Ma #define mmSDMA5_RLC4_MIDCMD_DATA0 0x02d0 7714f727eceSLe Ma #define mmSDMA5_RLC4_MIDCMD_DATA0_BASE_IDX 1 7724f727eceSLe Ma #define mmSDMA5_RLC4_MIDCMD_DATA1 0x02d1 7734f727eceSLe Ma #define mmSDMA5_RLC4_MIDCMD_DATA1_BASE_IDX 1 7744f727eceSLe Ma #define mmSDMA5_RLC4_MIDCMD_DATA2 0x02d2 7754f727eceSLe Ma #define mmSDMA5_RLC4_MIDCMD_DATA2_BASE_IDX 1 7764f727eceSLe Ma #define mmSDMA5_RLC4_MIDCMD_DATA3 0x02d3 7774f727eceSLe Ma #define mmSDMA5_RLC4_MIDCMD_DATA3_BASE_IDX 1 7784f727eceSLe Ma #define mmSDMA5_RLC4_MIDCMD_DATA4 0x02d4 7794f727eceSLe Ma #define mmSDMA5_RLC4_MIDCMD_DATA4_BASE_IDX 1 7804f727eceSLe Ma #define mmSDMA5_RLC4_MIDCMD_DATA5 0x02d5 7814f727eceSLe Ma #define mmSDMA5_RLC4_MIDCMD_DATA5_BASE_IDX 1 7824f727eceSLe Ma #define mmSDMA5_RLC4_MIDCMD_DATA6 0x02d6 7834f727eceSLe Ma #define mmSDMA5_RLC4_MIDCMD_DATA6_BASE_IDX 1 7844f727eceSLe Ma #define mmSDMA5_RLC4_MIDCMD_DATA7 0x02d7 7854f727eceSLe Ma #define mmSDMA5_RLC4_MIDCMD_DATA7_BASE_IDX 1 7864f727eceSLe Ma #define mmSDMA5_RLC4_MIDCMD_DATA8 0x02d8 7874f727eceSLe Ma #define mmSDMA5_RLC4_MIDCMD_DATA8_BASE_IDX 1 7884f727eceSLe Ma #define mmSDMA5_RLC4_MIDCMD_CNTL 0x02d9 7894f727eceSLe Ma #define mmSDMA5_RLC4_MIDCMD_CNTL_BASE_IDX 1 7904f727eceSLe Ma #define mmSDMA5_RLC5_RB_CNTL 0x02e8 7914f727eceSLe Ma #define mmSDMA5_RLC5_RB_CNTL_BASE_IDX 1 7924f727eceSLe Ma #define mmSDMA5_RLC5_RB_BASE 0x02e9 7934f727eceSLe Ma #define mmSDMA5_RLC5_RB_BASE_BASE_IDX 1 7944f727eceSLe Ma #define mmSDMA5_RLC5_RB_BASE_HI 0x02ea 7954f727eceSLe Ma #define mmSDMA5_RLC5_RB_BASE_HI_BASE_IDX 1 7964f727eceSLe Ma #define mmSDMA5_RLC5_RB_RPTR 0x02eb 7974f727eceSLe Ma #define mmSDMA5_RLC5_RB_RPTR_BASE_IDX 1 7984f727eceSLe Ma #define mmSDMA5_RLC5_RB_RPTR_HI 0x02ec 7994f727eceSLe Ma #define mmSDMA5_RLC5_RB_RPTR_HI_BASE_IDX 1 8004f727eceSLe Ma #define mmSDMA5_RLC5_RB_WPTR 0x02ed 8014f727eceSLe Ma #define mmSDMA5_RLC5_RB_WPTR_BASE_IDX 1 8024f727eceSLe Ma #define mmSDMA5_RLC5_RB_WPTR_HI 0x02ee 8034f727eceSLe Ma #define mmSDMA5_RLC5_RB_WPTR_HI_BASE_IDX 1 8044f727eceSLe Ma #define mmSDMA5_RLC5_RB_WPTR_POLL_CNTL 0x02ef 8054f727eceSLe Ma #define mmSDMA5_RLC5_RB_WPTR_POLL_CNTL_BASE_IDX 1 8064f727eceSLe Ma #define mmSDMA5_RLC5_RB_RPTR_ADDR_HI 0x02f0 8074f727eceSLe Ma #define mmSDMA5_RLC5_RB_RPTR_ADDR_HI_BASE_IDX 1 8084f727eceSLe Ma #define mmSDMA5_RLC5_RB_RPTR_ADDR_LO 0x02f1 8094f727eceSLe Ma #define mmSDMA5_RLC5_RB_RPTR_ADDR_LO_BASE_IDX 1 8104f727eceSLe Ma #define mmSDMA5_RLC5_IB_CNTL 0x02f2 8114f727eceSLe Ma #define mmSDMA5_RLC5_IB_CNTL_BASE_IDX 1 8124f727eceSLe Ma #define mmSDMA5_RLC5_IB_RPTR 0x02f3 8134f727eceSLe Ma #define mmSDMA5_RLC5_IB_RPTR_BASE_IDX 1 8144f727eceSLe Ma #define mmSDMA5_RLC5_IB_OFFSET 0x02f4 8154f727eceSLe Ma #define mmSDMA5_RLC5_IB_OFFSET_BASE_IDX 1 8164f727eceSLe Ma #define mmSDMA5_RLC5_IB_BASE_LO 0x02f5 8174f727eceSLe Ma #define mmSDMA5_RLC5_IB_BASE_LO_BASE_IDX 1 8184f727eceSLe Ma #define mmSDMA5_RLC5_IB_BASE_HI 0x02f6 8194f727eceSLe Ma #define mmSDMA5_RLC5_IB_BASE_HI_BASE_IDX 1 8204f727eceSLe Ma #define mmSDMA5_RLC5_IB_SIZE 0x02f7 8214f727eceSLe Ma #define mmSDMA5_RLC5_IB_SIZE_BASE_IDX 1 8224f727eceSLe Ma #define mmSDMA5_RLC5_SKIP_CNTL 0x02f8 8234f727eceSLe Ma #define mmSDMA5_RLC5_SKIP_CNTL_BASE_IDX 1 8244f727eceSLe Ma #define mmSDMA5_RLC5_CONTEXT_STATUS 0x02f9 8254f727eceSLe Ma #define mmSDMA5_RLC5_CONTEXT_STATUS_BASE_IDX 1 8264f727eceSLe Ma #define mmSDMA5_RLC5_DOORBELL 0x02fa 8274f727eceSLe Ma #define mmSDMA5_RLC5_DOORBELL_BASE_IDX 1 8284f727eceSLe Ma #define mmSDMA5_RLC5_STATUS 0x0310 8294f727eceSLe Ma #define mmSDMA5_RLC5_STATUS_BASE_IDX 1 8304f727eceSLe Ma #define mmSDMA5_RLC5_DOORBELL_LOG 0x0311 8314f727eceSLe Ma #define mmSDMA5_RLC5_DOORBELL_LOG_BASE_IDX 1 8324f727eceSLe Ma #define mmSDMA5_RLC5_WATERMARK 0x0312 8334f727eceSLe Ma #define mmSDMA5_RLC5_WATERMARK_BASE_IDX 1 8344f727eceSLe Ma #define mmSDMA5_RLC5_DOORBELL_OFFSET 0x0313 8354f727eceSLe Ma #define mmSDMA5_RLC5_DOORBELL_OFFSET_BASE_IDX 1 8364f727eceSLe Ma #define mmSDMA5_RLC5_CSA_ADDR_LO 0x0314 8374f727eceSLe Ma #define mmSDMA5_RLC5_CSA_ADDR_LO_BASE_IDX 1 8384f727eceSLe Ma #define mmSDMA5_RLC5_CSA_ADDR_HI 0x0315 8394f727eceSLe Ma #define mmSDMA5_RLC5_CSA_ADDR_HI_BASE_IDX 1 8404f727eceSLe Ma #define mmSDMA5_RLC5_IB_SUB_REMAIN 0x0317 8414f727eceSLe Ma #define mmSDMA5_RLC5_IB_SUB_REMAIN_BASE_IDX 1 8424f727eceSLe Ma #define mmSDMA5_RLC5_PREEMPT 0x0318 8434f727eceSLe Ma #define mmSDMA5_RLC5_PREEMPT_BASE_IDX 1 8444f727eceSLe Ma #define mmSDMA5_RLC5_DUMMY_REG 0x0319 8454f727eceSLe Ma #define mmSDMA5_RLC5_DUMMY_REG_BASE_IDX 1 8464f727eceSLe Ma #define mmSDMA5_RLC5_RB_WPTR_POLL_ADDR_HI 0x031a 8474f727eceSLe Ma #define mmSDMA5_RLC5_RB_WPTR_POLL_ADDR_HI_BASE_IDX 1 8484f727eceSLe Ma #define mmSDMA5_RLC5_RB_WPTR_POLL_ADDR_LO 0x031b 8494f727eceSLe Ma #define mmSDMA5_RLC5_RB_WPTR_POLL_ADDR_LO_BASE_IDX 1 8504f727eceSLe Ma #define mmSDMA5_RLC5_RB_AQL_CNTL 0x031c 8514f727eceSLe Ma #define mmSDMA5_RLC5_RB_AQL_CNTL_BASE_IDX 1 8524f727eceSLe Ma #define mmSDMA5_RLC5_MINOR_PTR_UPDATE 0x031d 8534f727eceSLe Ma #define mmSDMA5_RLC5_MINOR_PTR_UPDATE_BASE_IDX 1 8544f727eceSLe Ma #define mmSDMA5_RLC5_MIDCMD_DATA0 0x0328 8554f727eceSLe Ma #define mmSDMA5_RLC5_MIDCMD_DATA0_BASE_IDX 1 8564f727eceSLe Ma #define mmSDMA5_RLC5_MIDCMD_DATA1 0x0329 8574f727eceSLe Ma #define mmSDMA5_RLC5_MIDCMD_DATA1_BASE_IDX 1 8584f727eceSLe Ma #define mmSDMA5_RLC5_MIDCMD_DATA2 0x032a 8594f727eceSLe Ma #define mmSDMA5_RLC5_MIDCMD_DATA2_BASE_IDX 1 8604f727eceSLe Ma #define mmSDMA5_RLC5_MIDCMD_DATA3 0x032b 8614f727eceSLe Ma #define mmSDMA5_RLC5_MIDCMD_DATA3_BASE_IDX 1 8624f727eceSLe Ma #define mmSDMA5_RLC5_MIDCMD_DATA4 0x032c 8634f727eceSLe Ma #define mmSDMA5_RLC5_MIDCMD_DATA4_BASE_IDX 1 8644f727eceSLe Ma #define mmSDMA5_RLC5_MIDCMD_DATA5 0x032d 8654f727eceSLe Ma #define mmSDMA5_RLC5_MIDCMD_DATA5_BASE_IDX 1 8664f727eceSLe Ma #define mmSDMA5_RLC5_MIDCMD_DATA6 0x032e 8674f727eceSLe Ma #define mmSDMA5_RLC5_MIDCMD_DATA6_BASE_IDX 1 8684f727eceSLe Ma #define mmSDMA5_RLC5_MIDCMD_DATA7 0x032f 8694f727eceSLe Ma #define mmSDMA5_RLC5_MIDCMD_DATA7_BASE_IDX 1 8704f727eceSLe Ma #define mmSDMA5_RLC5_MIDCMD_DATA8 0x0330 8714f727eceSLe Ma #define mmSDMA5_RLC5_MIDCMD_DATA8_BASE_IDX 1 8724f727eceSLe Ma #define mmSDMA5_RLC5_MIDCMD_CNTL 0x0331 8734f727eceSLe Ma #define mmSDMA5_RLC5_MIDCMD_CNTL_BASE_IDX 1 8744f727eceSLe Ma #define mmSDMA5_RLC6_RB_CNTL 0x0340 8754f727eceSLe Ma #define mmSDMA5_RLC6_RB_CNTL_BASE_IDX 1 8764f727eceSLe Ma #define mmSDMA5_RLC6_RB_BASE 0x0341 8774f727eceSLe Ma #define mmSDMA5_RLC6_RB_BASE_BASE_IDX 1 8784f727eceSLe Ma #define mmSDMA5_RLC6_RB_BASE_HI 0x0342 8794f727eceSLe Ma #define mmSDMA5_RLC6_RB_BASE_HI_BASE_IDX 1 8804f727eceSLe Ma #define mmSDMA5_RLC6_RB_RPTR 0x0343 8814f727eceSLe Ma #define mmSDMA5_RLC6_RB_RPTR_BASE_IDX 1 8824f727eceSLe Ma #define mmSDMA5_RLC6_RB_RPTR_HI 0x0344 8834f727eceSLe Ma #define mmSDMA5_RLC6_RB_RPTR_HI_BASE_IDX 1 8844f727eceSLe Ma #define mmSDMA5_RLC6_RB_WPTR 0x0345 8854f727eceSLe Ma #define mmSDMA5_RLC6_RB_WPTR_BASE_IDX 1 8864f727eceSLe Ma #define mmSDMA5_RLC6_RB_WPTR_HI 0x0346 8874f727eceSLe Ma #define mmSDMA5_RLC6_RB_WPTR_HI_BASE_IDX 1 8884f727eceSLe Ma #define mmSDMA5_RLC6_RB_WPTR_POLL_CNTL 0x0347 8894f727eceSLe Ma #define mmSDMA5_RLC6_RB_WPTR_POLL_CNTL_BASE_IDX 1 8904f727eceSLe Ma #define mmSDMA5_RLC6_RB_RPTR_ADDR_HI 0x0348 8914f727eceSLe Ma #define mmSDMA5_RLC6_RB_RPTR_ADDR_HI_BASE_IDX 1 8924f727eceSLe Ma #define mmSDMA5_RLC6_RB_RPTR_ADDR_LO 0x0349 8934f727eceSLe Ma #define mmSDMA5_RLC6_RB_RPTR_ADDR_LO_BASE_IDX 1 8944f727eceSLe Ma #define mmSDMA5_RLC6_IB_CNTL 0x034a 8954f727eceSLe Ma #define mmSDMA5_RLC6_IB_CNTL_BASE_IDX 1 8964f727eceSLe Ma #define mmSDMA5_RLC6_IB_RPTR 0x034b 8974f727eceSLe Ma #define mmSDMA5_RLC6_IB_RPTR_BASE_IDX 1 8984f727eceSLe Ma #define mmSDMA5_RLC6_IB_OFFSET 0x034c 8994f727eceSLe Ma #define mmSDMA5_RLC6_IB_OFFSET_BASE_IDX 1 9004f727eceSLe Ma #define mmSDMA5_RLC6_IB_BASE_LO 0x034d 9014f727eceSLe Ma #define mmSDMA5_RLC6_IB_BASE_LO_BASE_IDX 1 9024f727eceSLe Ma #define mmSDMA5_RLC6_IB_BASE_HI 0x034e 9034f727eceSLe Ma #define mmSDMA5_RLC6_IB_BASE_HI_BASE_IDX 1 9044f727eceSLe Ma #define mmSDMA5_RLC6_IB_SIZE 0x034f 9054f727eceSLe Ma #define mmSDMA5_RLC6_IB_SIZE_BASE_IDX 1 9064f727eceSLe Ma #define mmSDMA5_RLC6_SKIP_CNTL 0x0350 9074f727eceSLe Ma #define mmSDMA5_RLC6_SKIP_CNTL_BASE_IDX 1 9084f727eceSLe Ma #define mmSDMA5_RLC6_CONTEXT_STATUS 0x0351 9094f727eceSLe Ma #define mmSDMA5_RLC6_CONTEXT_STATUS_BASE_IDX 1 9104f727eceSLe Ma #define mmSDMA5_RLC6_DOORBELL 0x0352 9114f727eceSLe Ma #define mmSDMA5_RLC6_DOORBELL_BASE_IDX 1 9124f727eceSLe Ma #define mmSDMA5_RLC6_STATUS 0x0368 9134f727eceSLe Ma #define mmSDMA5_RLC6_STATUS_BASE_IDX 1 9144f727eceSLe Ma #define mmSDMA5_RLC6_DOORBELL_LOG 0x0369 9154f727eceSLe Ma #define mmSDMA5_RLC6_DOORBELL_LOG_BASE_IDX 1 9164f727eceSLe Ma #define mmSDMA5_RLC6_WATERMARK 0x036a 9174f727eceSLe Ma #define mmSDMA5_RLC6_WATERMARK_BASE_IDX 1 9184f727eceSLe Ma #define mmSDMA5_RLC6_DOORBELL_OFFSET 0x036b 9194f727eceSLe Ma #define mmSDMA5_RLC6_DOORBELL_OFFSET_BASE_IDX 1 9204f727eceSLe Ma #define mmSDMA5_RLC6_CSA_ADDR_LO 0x036c 9214f727eceSLe Ma #define mmSDMA5_RLC6_CSA_ADDR_LO_BASE_IDX 1 9224f727eceSLe Ma #define mmSDMA5_RLC6_CSA_ADDR_HI 0x036d 9234f727eceSLe Ma #define mmSDMA5_RLC6_CSA_ADDR_HI_BASE_IDX 1 9244f727eceSLe Ma #define mmSDMA5_RLC6_IB_SUB_REMAIN 0x036f 9254f727eceSLe Ma #define mmSDMA5_RLC6_IB_SUB_REMAIN_BASE_IDX 1 9264f727eceSLe Ma #define mmSDMA5_RLC6_PREEMPT 0x0370 9274f727eceSLe Ma #define mmSDMA5_RLC6_PREEMPT_BASE_IDX 1 9284f727eceSLe Ma #define mmSDMA5_RLC6_DUMMY_REG 0x0371 9294f727eceSLe Ma #define mmSDMA5_RLC6_DUMMY_REG_BASE_IDX 1 9304f727eceSLe Ma #define mmSDMA5_RLC6_RB_WPTR_POLL_ADDR_HI 0x0372 9314f727eceSLe Ma #define mmSDMA5_RLC6_RB_WPTR_POLL_ADDR_HI_BASE_IDX 1 9324f727eceSLe Ma #define mmSDMA5_RLC6_RB_WPTR_POLL_ADDR_LO 0x0373 9334f727eceSLe Ma #define mmSDMA5_RLC6_RB_WPTR_POLL_ADDR_LO_BASE_IDX 1 9344f727eceSLe Ma #define mmSDMA5_RLC6_RB_AQL_CNTL 0x0374 9354f727eceSLe Ma #define mmSDMA5_RLC6_RB_AQL_CNTL_BASE_IDX 1 9364f727eceSLe Ma #define mmSDMA5_RLC6_MINOR_PTR_UPDATE 0x0375 9374f727eceSLe Ma #define mmSDMA5_RLC6_MINOR_PTR_UPDATE_BASE_IDX 1 9384f727eceSLe Ma #define mmSDMA5_RLC6_MIDCMD_DATA0 0x0380 9394f727eceSLe Ma #define mmSDMA5_RLC6_MIDCMD_DATA0_BASE_IDX 1 9404f727eceSLe Ma #define mmSDMA5_RLC6_MIDCMD_DATA1 0x0381 9414f727eceSLe Ma #define mmSDMA5_RLC6_MIDCMD_DATA1_BASE_IDX 1 9424f727eceSLe Ma #define mmSDMA5_RLC6_MIDCMD_DATA2 0x0382 9434f727eceSLe Ma #define mmSDMA5_RLC6_MIDCMD_DATA2_BASE_IDX 1 9444f727eceSLe Ma #define mmSDMA5_RLC6_MIDCMD_DATA3 0x0383 9454f727eceSLe Ma #define mmSDMA5_RLC6_MIDCMD_DATA3_BASE_IDX 1 9464f727eceSLe Ma #define mmSDMA5_RLC6_MIDCMD_DATA4 0x0384 9474f727eceSLe Ma #define mmSDMA5_RLC6_MIDCMD_DATA4_BASE_IDX 1 9484f727eceSLe Ma #define mmSDMA5_RLC6_MIDCMD_DATA5 0x0385 9494f727eceSLe Ma #define mmSDMA5_RLC6_MIDCMD_DATA5_BASE_IDX 1 9504f727eceSLe Ma #define mmSDMA5_RLC6_MIDCMD_DATA6 0x0386 9514f727eceSLe Ma #define mmSDMA5_RLC6_MIDCMD_DATA6_BASE_IDX 1 9524f727eceSLe Ma #define mmSDMA5_RLC6_MIDCMD_DATA7 0x0387 9534f727eceSLe Ma #define mmSDMA5_RLC6_MIDCMD_DATA7_BASE_IDX 1 9544f727eceSLe Ma #define mmSDMA5_RLC6_MIDCMD_DATA8 0x0388 9554f727eceSLe Ma #define mmSDMA5_RLC6_MIDCMD_DATA8_BASE_IDX 1 9564f727eceSLe Ma #define mmSDMA5_RLC6_MIDCMD_CNTL 0x0389 9574f727eceSLe Ma #define mmSDMA5_RLC6_MIDCMD_CNTL_BASE_IDX 1 9584f727eceSLe Ma #define mmSDMA5_RLC7_RB_CNTL 0x0398 9594f727eceSLe Ma #define mmSDMA5_RLC7_RB_CNTL_BASE_IDX 1 9604f727eceSLe Ma #define mmSDMA5_RLC7_RB_BASE 0x0399 9614f727eceSLe Ma #define mmSDMA5_RLC7_RB_BASE_BASE_IDX 1 9624f727eceSLe Ma #define mmSDMA5_RLC7_RB_BASE_HI 0x039a 9634f727eceSLe Ma #define mmSDMA5_RLC7_RB_BASE_HI_BASE_IDX 1 9644f727eceSLe Ma #define mmSDMA5_RLC7_RB_RPTR 0x039b 9654f727eceSLe Ma #define mmSDMA5_RLC7_RB_RPTR_BASE_IDX 1 9664f727eceSLe Ma #define mmSDMA5_RLC7_RB_RPTR_HI 0x039c 9674f727eceSLe Ma #define mmSDMA5_RLC7_RB_RPTR_HI_BASE_IDX 1 9684f727eceSLe Ma #define mmSDMA5_RLC7_RB_WPTR 0x039d 9694f727eceSLe Ma #define mmSDMA5_RLC7_RB_WPTR_BASE_IDX 1 9704f727eceSLe Ma #define mmSDMA5_RLC7_RB_WPTR_HI 0x039e 9714f727eceSLe Ma #define mmSDMA5_RLC7_RB_WPTR_HI_BASE_IDX 1 9724f727eceSLe Ma #define mmSDMA5_RLC7_RB_WPTR_POLL_CNTL 0x039f 9734f727eceSLe Ma #define mmSDMA5_RLC7_RB_WPTR_POLL_CNTL_BASE_IDX 1 9744f727eceSLe Ma #define mmSDMA5_RLC7_RB_RPTR_ADDR_HI 0x03a0 9754f727eceSLe Ma #define mmSDMA5_RLC7_RB_RPTR_ADDR_HI_BASE_IDX 1 9764f727eceSLe Ma #define mmSDMA5_RLC7_RB_RPTR_ADDR_LO 0x03a1 9774f727eceSLe Ma #define mmSDMA5_RLC7_RB_RPTR_ADDR_LO_BASE_IDX 1 9784f727eceSLe Ma #define mmSDMA5_RLC7_IB_CNTL 0x03a2 9794f727eceSLe Ma #define mmSDMA5_RLC7_IB_CNTL_BASE_IDX 1 9804f727eceSLe Ma #define mmSDMA5_RLC7_IB_RPTR 0x03a3 9814f727eceSLe Ma #define mmSDMA5_RLC7_IB_RPTR_BASE_IDX 1 9824f727eceSLe Ma #define mmSDMA5_RLC7_IB_OFFSET 0x03a4 9834f727eceSLe Ma #define mmSDMA5_RLC7_IB_OFFSET_BASE_IDX 1 9844f727eceSLe Ma #define mmSDMA5_RLC7_IB_BASE_LO 0x03a5 9854f727eceSLe Ma #define mmSDMA5_RLC7_IB_BASE_LO_BASE_IDX 1 9864f727eceSLe Ma #define mmSDMA5_RLC7_IB_BASE_HI 0x03a6 9874f727eceSLe Ma #define mmSDMA5_RLC7_IB_BASE_HI_BASE_IDX 1 9884f727eceSLe Ma #define mmSDMA5_RLC7_IB_SIZE 0x03a7 9894f727eceSLe Ma #define mmSDMA5_RLC7_IB_SIZE_BASE_IDX 1 9904f727eceSLe Ma #define mmSDMA5_RLC7_SKIP_CNTL 0x03a8 9914f727eceSLe Ma #define mmSDMA5_RLC7_SKIP_CNTL_BASE_IDX 1 9924f727eceSLe Ma #define mmSDMA5_RLC7_CONTEXT_STATUS 0x03a9 9934f727eceSLe Ma #define mmSDMA5_RLC7_CONTEXT_STATUS_BASE_IDX 1 9944f727eceSLe Ma #define mmSDMA5_RLC7_DOORBELL 0x03aa 9954f727eceSLe Ma #define mmSDMA5_RLC7_DOORBELL_BASE_IDX 1 9964f727eceSLe Ma #define mmSDMA5_RLC7_STATUS 0x03c0 9974f727eceSLe Ma #define mmSDMA5_RLC7_STATUS_BASE_IDX 1 9984f727eceSLe Ma #define mmSDMA5_RLC7_DOORBELL_LOG 0x03c1 9994f727eceSLe Ma #define mmSDMA5_RLC7_DOORBELL_LOG_BASE_IDX 1 10004f727eceSLe Ma #define mmSDMA5_RLC7_WATERMARK 0x03c2 10014f727eceSLe Ma #define mmSDMA5_RLC7_WATERMARK_BASE_IDX 1 10024f727eceSLe Ma #define mmSDMA5_RLC7_DOORBELL_OFFSET 0x03c3 10034f727eceSLe Ma #define mmSDMA5_RLC7_DOORBELL_OFFSET_BASE_IDX 1 10044f727eceSLe Ma #define mmSDMA5_RLC7_CSA_ADDR_LO 0x03c4 10054f727eceSLe Ma #define mmSDMA5_RLC7_CSA_ADDR_LO_BASE_IDX 1 10064f727eceSLe Ma #define mmSDMA5_RLC7_CSA_ADDR_HI 0x03c5 10074f727eceSLe Ma #define mmSDMA5_RLC7_CSA_ADDR_HI_BASE_IDX 1 10084f727eceSLe Ma #define mmSDMA5_RLC7_IB_SUB_REMAIN 0x03c7 10094f727eceSLe Ma #define mmSDMA5_RLC7_IB_SUB_REMAIN_BASE_IDX 1 10104f727eceSLe Ma #define mmSDMA5_RLC7_PREEMPT 0x03c8 10114f727eceSLe Ma #define mmSDMA5_RLC7_PREEMPT_BASE_IDX 1 10124f727eceSLe Ma #define mmSDMA5_RLC7_DUMMY_REG 0x03c9 10134f727eceSLe Ma #define mmSDMA5_RLC7_DUMMY_REG_BASE_IDX 1 10144f727eceSLe Ma #define mmSDMA5_RLC7_RB_WPTR_POLL_ADDR_HI 0x03ca 10154f727eceSLe Ma #define mmSDMA5_RLC7_RB_WPTR_POLL_ADDR_HI_BASE_IDX 1 10164f727eceSLe Ma #define mmSDMA5_RLC7_RB_WPTR_POLL_ADDR_LO 0x03cb 10174f727eceSLe Ma #define mmSDMA5_RLC7_RB_WPTR_POLL_ADDR_LO_BASE_IDX 1 10184f727eceSLe Ma #define mmSDMA5_RLC7_RB_AQL_CNTL 0x03cc 10194f727eceSLe Ma #define mmSDMA5_RLC7_RB_AQL_CNTL_BASE_IDX 1 10204f727eceSLe Ma #define mmSDMA5_RLC7_MINOR_PTR_UPDATE 0x03cd 10214f727eceSLe Ma #define mmSDMA5_RLC7_MINOR_PTR_UPDATE_BASE_IDX 1 10224f727eceSLe Ma #define mmSDMA5_RLC7_MIDCMD_DATA0 0x03d8 10234f727eceSLe Ma #define mmSDMA5_RLC7_MIDCMD_DATA0_BASE_IDX 1 10244f727eceSLe Ma #define mmSDMA5_RLC7_MIDCMD_DATA1 0x03d9 10254f727eceSLe Ma #define mmSDMA5_RLC7_MIDCMD_DATA1_BASE_IDX 1 10264f727eceSLe Ma #define mmSDMA5_RLC7_MIDCMD_DATA2 0x03da 10274f727eceSLe Ma #define mmSDMA5_RLC7_MIDCMD_DATA2_BASE_IDX 1 10284f727eceSLe Ma #define mmSDMA5_RLC7_MIDCMD_DATA3 0x03db 10294f727eceSLe Ma #define mmSDMA5_RLC7_MIDCMD_DATA3_BASE_IDX 1 10304f727eceSLe Ma #define mmSDMA5_RLC7_MIDCMD_DATA4 0x03dc 10314f727eceSLe Ma #define mmSDMA5_RLC7_MIDCMD_DATA4_BASE_IDX 1 10324f727eceSLe Ma #define mmSDMA5_RLC7_MIDCMD_DATA5 0x03dd 10334f727eceSLe Ma #define mmSDMA5_RLC7_MIDCMD_DATA5_BASE_IDX 1 10344f727eceSLe Ma #define mmSDMA5_RLC7_MIDCMD_DATA6 0x03de 10354f727eceSLe Ma #define mmSDMA5_RLC7_MIDCMD_DATA6_BASE_IDX 1 10364f727eceSLe Ma #define mmSDMA5_RLC7_MIDCMD_DATA7 0x03df 10374f727eceSLe Ma #define mmSDMA5_RLC7_MIDCMD_DATA7_BASE_IDX 1 10384f727eceSLe Ma #define mmSDMA5_RLC7_MIDCMD_DATA8 0x03e0 10394f727eceSLe Ma #define mmSDMA5_RLC7_MIDCMD_DATA8_BASE_IDX 1 10404f727eceSLe Ma #define mmSDMA5_RLC7_MIDCMD_CNTL 0x03e1 10414f727eceSLe Ma #define mmSDMA5_RLC7_MIDCMD_CNTL_BASE_IDX 1 10424f727eceSLe Ma 10434f727eceSLe Ma #endif 1044