1 /*
2  * Copyright (C) 2018  Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included
12  * in all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
15  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
18  * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
19  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
20  */
21 #ifndef _sdma1_4_2_0_OFFSET_HEADER
22 #define _sdma1_4_2_0_OFFSET_HEADER
23 
24 
25 
26 // addressBlock: sdma1_sdma1dec
27 // base address: 0x6180
28 #define mmSDMA1_UCODE_ADDR                                                                             0x0000
29 #define mmSDMA1_UCODE_ADDR_BASE_IDX                                                                    0
30 #define mmSDMA1_UCODE_DATA                                                                             0x0001
31 #define mmSDMA1_UCODE_DATA_BASE_IDX                                                                    0
32 #define mmSDMA1_VM_CNTL                                                                                0x0004
33 #define mmSDMA1_VM_CNTL_BASE_IDX                                                                       0
34 #define mmSDMA1_VM_CTX_LO                                                                              0x0005
35 #define mmSDMA1_VM_CTX_LO_BASE_IDX                                                                     0
36 #define mmSDMA1_VM_CTX_HI                                                                              0x0006
37 #define mmSDMA1_VM_CTX_HI_BASE_IDX                                                                     0
38 #define mmSDMA1_ACTIVE_FCN_ID                                                                          0x0007
39 #define mmSDMA1_ACTIVE_FCN_ID_BASE_IDX                                                                 0
40 #define mmSDMA1_VM_CTX_CNTL                                                                            0x0008
41 #define mmSDMA1_VM_CTX_CNTL_BASE_IDX                                                                   0
42 #define mmSDMA1_VIRT_RESET_REQ                                                                         0x0009
43 #define mmSDMA1_VIRT_RESET_REQ_BASE_IDX                                                                0
44 #define mmSDMA1_VF_ENABLE                                                                              0x000a
45 #define mmSDMA1_VF_ENABLE_BASE_IDX                                                                     0
46 #define mmSDMA1_CONTEXT_REG_TYPE0                                                                      0x000b
47 #define mmSDMA1_CONTEXT_REG_TYPE0_BASE_IDX                                                             0
48 #define mmSDMA1_CONTEXT_REG_TYPE1                                                                      0x000c
49 #define mmSDMA1_CONTEXT_REG_TYPE1_BASE_IDX                                                             0
50 #define mmSDMA1_CONTEXT_REG_TYPE2                                                                      0x000d
51 #define mmSDMA1_CONTEXT_REG_TYPE2_BASE_IDX                                                             0
52 #define mmSDMA1_CONTEXT_REG_TYPE3                                                                      0x000e
53 #define mmSDMA1_CONTEXT_REG_TYPE3_BASE_IDX                                                             0
54 #define mmSDMA1_PUB_REG_TYPE0                                                                          0x000f
55 #define mmSDMA1_PUB_REG_TYPE0_BASE_IDX                                                                 0
56 #define mmSDMA1_PUB_REG_TYPE1                                                                          0x0010
57 #define mmSDMA1_PUB_REG_TYPE1_BASE_IDX                                                                 0
58 #define mmSDMA1_PUB_REG_TYPE2                                                                          0x0011
59 #define mmSDMA1_PUB_REG_TYPE2_BASE_IDX                                                                 0
60 #define mmSDMA1_PUB_REG_TYPE3                                                                          0x0012
61 #define mmSDMA1_PUB_REG_TYPE3_BASE_IDX                                                                 0
62 #define mmSDMA1_MMHUB_CNTL                                                                             0x0013
63 #define mmSDMA1_MMHUB_CNTL_BASE_IDX                                                                    0
64 #define mmSDMA1_CONTEXT_GROUP_BOUNDARY                                                                 0x0019
65 #define mmSDMA1_CONTEXT_GROUP_BOUNDARY_BASE_IDX                                                        0
66 #define mmSDMA1_POWER_CNTL                                                                             0x001a
67 #define mmSDMA1_POWER_CNTL_BASE_IDX                                                                    0
68 #define mmSDMA1_CLK_CTRL                                                                               0x001b
69 #define mmSDMA1_CLK_CTRL_BASE_IDX                                                                      0
70 #define mmSDMA1_CNTL                                                                                   0x001c
71 #define mmSDMA1_CNTL_BASE_IDX                                                                          0
72 #define mmSDMA1_CHICKEN_BITS                                                                           0x001d
73 #define mmSDMA1_CHICKEN_BITS_BASE_IDX                                                                  0
74 #define mmSDMA1_GB_ADDR_CONFIG                                                                         0x001e
75 #define mmSDMA1_GB_ADDR_CONFIG_BASE_IDX                                                                0
76 #define mmSDMA1_GB_ADDR_CONFIG_READ                                                                    0x001f
77 #define mmSDMA1_GB_ADDR_CONFIG_READ_BASE_IDX                                                           0
78 #define mmSDMA1_RB_RPTR_FETCH_HI                                                                       0x0020
79 #define mmSDMA1_RB_RPTR_FETCH_HI_BASE_IDX                                                              0
80 #define mmSDMA1_SEM_WAIT_FAIL_TIMER_CNTL                                                               0x0021
81 #define mmSDMA1_SEM_WAIT_FAIL_TIMER_CNTL_BASE_IDX                                                      0
82 #define mmSDMA1_RB_RPTR_FETCH                                                                          0x0022
83 #define mmSDMA1_RB_RPTR_FETCH_BASE_IDX                                                                 0
84 #define mmSDMA1_IB_OFFSET_FETCH                                                                        0x0023
85 #define mmSDMA1_IB_OFFSET_FETCH_BASE_IDX                                                               0
86 #define mmSDMA1_PROGRAM                                                                                0x0024
87 #define mmSDMA1_PROGRAM_BASE_IDX                                                                       0
88 #define mmSDMA1_STATUS_REG                                                                             0x0025
89 #define mmSDMA1_STATUS_REG_BASE_IDX                                                                    0
90 #define mmSDMA1_STATUS1_REG                                                                            0x0026
91 #define mmSDMA1_STATUS1_REG_BASE_IDX                                                                   0
92 #define mmSDMA1_RD_BURST_CNTL                                                                          0x0027
93 #define mmSDMA1_RD_BURST_CNTL_BASE_IDX                                                                 0
94 #define mmSDMA1_HBM_PAGE_CONFIG                                                                        0x0028
95 #define mmSDMA1_HBM_PAGE_CONFIG_BASE_IDX                                                               0
96 #define mmSDMA1_UCODE_CHECKSUM                                                                         0x0029
97 #define mmSDMA1_UCODE_CHECKSUM_BASE_IDX                                                                0
98 #define mmSDMA1_F32_CNTL                                                                               0x002a
99 #define mmSDMA1_F32_CNTL_BASE_IDX                                                                      0
100 #define mmSDMA1_FREEZE                                                                                 0x002b
101 #define mmSDMA1_FREEZE_BASE_IDX                                                                        0
102 #define mmSDMA1_PHASE0_QUANTUM                                                                         0x002c
103 #define mmSDMA1_PHASE0_QUANTUM_BASE_IDX                                                                0
104 #define mmSDMA1_PHASE1_QUANTUM                                                                         0x002d
105 #define mmSDMA1_PHASE1_QUANTUM_BASE_IDX                                                                0
106 #define mmSDMA1_EDC_CONFIG                                                                             0x0032
107 #define mmSDMA1_EDC_CONFIG_BASE_IDX                                                                    0
108 #define mmSDMA1_BA_THRESHOLD                                                                           0x0033
109 #define mmSDMA1_BA_THRESHOLD_BASE_IDX                                                                  0
110 #define mmSDMA1_ID                                                                                     0x0034
111 #define mmSDMA1_ID_BASE_IDX                                                                            0
112 #define mmSDMA1_VERSION                                                                                0x0035
113 #define mmSDMA1_VERSION_BASE_IDX                                                                       0
114 #define mmSDMA1_EDC_COUNTER                                                                            0x0036
115 #define mmSDMA1_EDC_COUNTER_BASE_IDX                                                                   0
116 #define mmSDMA1_EDC_COUNTER_CLEAR                                                                      0x0037
117 #define mmSDMA1_EDC_COUNTER_CLEAR_BASE_IDX                                                             0
118 #define mmSDMA1_STATUS2_REG                                                                            0x0038
119 #define mmSDMA1_STATUS2_REG_BASE_IDX                                                                   0
120 #define mmSDMA1_ATOMIC_CNTL                                                                            0x0039
121 #define mmSDMA1_ATOMIC_CNTL_BASE_IDX                                                                   0
122 #define mmSDMA1_ATOMIC_PREOP_LO                                                                        0x003a
123 #define mmSDMA1_ATOMIC_PREOP_LO_BASE_IDX                                                               0
124 #define mmSDMA1_ATOMIC_PREOP_HI                                                                        0x003b
125 #define mmSDMA1_ATOMIC_PREOP_HI_BASE_IDX                                                               0
126 #define mmSDMA1_UTCL1_CNTL                                                                             0x003c
127 #define mmSDMA1_UTCL1_CNTL_BASE_IDX                                                                    0
128 #define mmSDMA1_UTCL1_WATERMK                                                                          0x003d
129 #define mmSDMA1_UTCL1_WATERMK_BASE_IDX                                                                 0
130 #define mmSDMA1_UTCL1_RD_STATUS                                                                        0x003e
131 #define mmSDMA1_UTCL1_RD_STATUS_BASE_IDX                                                               0
132 #define mmSDMA1_UTCL1_WR_STATUS                                                                        0x003f
133 #define mmSDMA1_UTCL1_WR_STATUS_BASE_IDX                                                               0
134 #define mmSDMA1_UTCL1_INV0                                                                             0x0040
135 #define mmSDMA1_UTCL1_INV0_BASE_IDX                                                                    0
136 #define mmSDMA1_UTCL1_INV1                                                                             0x0041
137 #define mmSDMA1_UTCL1_INV1_BASE_IDX                                                                    0
138 #define mmSDMA1_UTCL1_INV2                                                                             0x0042
139 #define mmSDMA1_UTCL1_INV2_BASE_IDX                                                                    0
140 #define mmSDMA1_UTCL1_RD_XNACK0                                                                        0x0043
141 #define mmSDMA1_UTCL1_RD_XNACK0_BASE_IDX                                                               0
142 #define mmSDMA1_UTCL1_RD_XNACK1                                                                        0x0044
143 #define mmSDMA1_UTCL1_RD_XNACK1_BASE_IDX                                                               0
144 #define mmSDMA1_UTCL1_WR_XNACK0                                                                        0x0045
145 #define mmSDMA1_UTCL1_WR_XNACK0_BASE_IDX                                                               0
146 #define mmSDMA1_UTCL1_WR_XNACK1                                                                        0x0046
147 #define mmSDMA1_UTCL1_WR_XNACK1_BASE_IDX                                                               0
148 #define mmSDMA1_UTCL1_TIMEOUT                                                                          0x0047
149 #define mmSDMA1_UTCL1_TIMEOUT_BASE_IDX                                                                 0
150 #define mmSDMA1_UTCL1_PAGE                                                                             0x0048
151 #define mmSDMA1_UTCL1_PAGE_BASE_IDX                                                                    0
152 #define mmSDMA1_POWER_CNTL_IDLE                                                                        0x0049
153 #define mmSDMA1_POWER_CNTL_IDLE_BASE_IDX                                                               0
154 #define mmSDMA1_RELAX_ORDERING_LUT                                                                     0x004a
155 #define mmSDMA1_RELAX_ORDERING_LUT_BASE_IDX                                                            0
156 #define mmSDMA1_CHICKEN_BITS_2                                                                         0x004b
157 #define mmSDMA1_CHICKEN_BITS_2_BASE_IDX                                                                0
158 #define mmSDMA1_STATUS3_REG                                                                            0x004c
159 #define mmSDMA1_STATUS3_REG_BASE_IDX                                                                   0
160 #define mmSDMA1_PHYSICAL_ADDR_LO                                                                       0x004d
161 #define mmSDMA1_PHYSICAL_ADDR_LO_BASE_IDX                                                              0
162 #define mmSDMA1_PHYSICAL_ADDR_HI                                                                       0x004e
163 #define mmSDMA1_PHYSICAL_ADDR_HI_BASE_IDX                                                              0
164 #define mmSDMA1_PHASE2_QUANTUM                                                                         0x004f
165 #define mmSDMA1_PHASE2_QUANTUM_BASE_IDX                                                                0
166 #define mmSDMA1_ERROR_LOG                                                                              0x0050
167 #define mmSDMA1_ERROR_LOG_BASE_IDX                                                                     0
168 #define mmSDMA1_PUB_DUMMY_REG0                                                                         0x0051
169 #define mmSDMA1_PUB_DUMMY_REG0_BASE_IDX                                                                0
170 #define mmSDMA1_PUB_DUMMY_REG1                                                                         0x0052
171 #define mmSDMA1_PUB_DUMMY_REG1_BASE_IDX                                                                0
172 #define mmSDMA1_PUB_DUMMY_REG2                                                                         0x0053
173 #define mmSDMA1_PUB_DUMMY_REG2_BASE_IDX                                                                0
174 #define mmSDMA1_PUB_DUMMY_REG3                                                                         0x0054
175 #define mmSDMA1_PUB_DUMMY_REG3_BASE_IDX                                                                0
176 #define mmSDMA1_F32_COUNTER                                                                            0x0055
177 #define mmSDMA1_F32_COUNTER_BASE_IDX                                                                   0
178 #define mmSDMA1_PERFMON_CNTL                                                                           0x0057
179 #define mmSDMA1_PERFMON_CNTL_BASE_IDX                                                                  0
180 #define mmSDMA1_PERFCOUNTER0_RESULT                                                                    0x0058
181 #define mmSDMA1_PERFCOUNTER0_RESULT_BASE_IDX                                                           0
182 #define mmSDMA1_PERFCOUNTER1_RESULT                                                                    0x0059
183 #define mmSDMA1_PERFCOUNTER1_RESULT_BASE_IDX                                                           0
184 #define mmSDMA1_PERFCOUNTER_TAG_DELAY_RANGE                                                            0x005a
185 #define mmSDMA1_PERFCOUNTER_TAG_DELAY_RANGE_BASE_IDX                                                   0
186 #define mmSDMA1_CRD_CNTL                                                                               0x005b
187 #define mmSDMA1_CRD_CNTL_BASE_IDX                                                                      0
188 #define mmSDMA1_GPU_IOV_VIOLATION_LOG                                                                  0x005d
189 #define mmSDMA1_GPU_IOV_VIOLATION_LOG_BASE_IDX                                                         0
190 #define mmSDMA1_ULV_CNTL                                                                               0x005e
191 #define mmSDMA1_ULV_CNTL_BASE_IDX                                                                      0
192 #define mmSDMA1_EA_DBIT_ADDR_DATA                                                                      0x0060
193 #define mmSDMA1_EA_DBIT_ADDR_DATA_BASE_IDX                                                             0
194 #define mmSDMA1_EA_DBIT_ADDR_INDEX                                                                     0x0061
195 #define mmSDMA1_EA_DBIT_ADDR_INDEX_BASE_IDX                                                            0
196 #define mmSDMA1_GFX_RB_CNTL                                                                            0x0080
197 #define mmSDMA1_GFX_RB_CNTL_BASE_IDX                                                                   0
198 #define mmSDMA1_GFX_RB_BASE                                                                            0x0081
199 #define mmSDMA1_GFX_RB_BASE_BASE_IDX                                                                   0
200 #define mmSDMA1_GFX_RB_BASE_HI                                                                         0x0082
201 #define mmSDMA1_GFX_RB_BASE_HI_BASE_IDX                                                                0
202 #define mmSDMA1_GFX_RB_RPTR                                                                            0x0083
203 #define mmSDMA1_GFX_RB_RPTR_BASE_IDX                                                                   0
204 #define mmSDMA1_GFX_RB_RPTR_HI                                                                         0x0084
205 #define mmSDMA1_GFX_RB_RPTR_HI_BASE_IDX                                                                0
206 #define mmSDMA1_GFX_RB_WPTR                                                                            0x0085
207 #define mmSDMA1_GFX_RB_WPTR_BASE_IDX                                                                   0
208 #define mmSDMA1_GFX_RB_WPTR_HI                                                                         0x0086
209 #define mmSDMA1_GFX_RB_WPTR_HI_BASE_IDX                                                                0
210 #define mmSDMA1_GFX_RB_WPTR_POLL_CNTL                                                                  0x0087
211 #define mmSDMA1_GFX_RB_WPTR_POLL_CNTL_BASE_IDX                                                         0
212 #define mmSDMA1_GFX_RB_RPTR_ADDR_HI                                                                    0x0088
213 #define mmSDMA1_GFX_RB_RPTR_ADDR_HI_BASE_IDX                                                           0
214 #define mmSDMA1_GFX_RB_RPTR_ADDR_LO                                                                    0x0089
215 #define mmSDMA1_GFX_RB_RPTR_ADDR_LO_BASE_IDX                                                           0
216 #define mmSDMA1_GFX_IB_CNTL                                                                            0x008a
217 #define mmSDMA1_GFX_IB_CNTL_BASE_IDX                                                                   0
218 #define mmSDMA1_GFX_IB_RPTR                                                                            0x008b
219 #define mmSDMA1_GFX_IB_RPTR_BASE_IDX                                                                   0
220 #define mmSDMA1_GFX_IB_OFFSET                                                                          0x008c
221 #define mmSDMA1_GFX_IB_OFFSET_BASE_IDX                                                                 0
222 #define mmSDMA1_GFX_IB_BASE_LO                                                                         0x008d
223 #define mmSDMA1_GFX_IB_BASE_LO_BASE_IDX                                                                0
224 #define mmSDMA1_GFX_IB_BASE_HI                                                                         0x008e
225 #define mmSDMA1_GFX_IB_BASE_HI_BASE_IDX                                                                0
226 #define mmSDMA1_GFX_IB_SIZE                                                                            0x008f
227 #define mmSDMA1_GFX_IB_SIZE_BASE_IDX                                                                   0
228 #define mmSDMA1_GFX_SKIP_CNTL                                                                          0x0090
229 #define mmSDMA1_GFX_SKIP_CNTL_BASE_IDX                                                                 0
230 #define mmSDMA1_GFX_CONTEXT_STATUS                                                                     0x0091
231 #define mmSDMA1_GFX_CONTEXT_STATUS_BASE_IDX                                                            0
232 #define mmSDMA1_GFX_DOORBELL                                                                           0x0092
233 #define mmSDMA1_GFX_DOORBELL_BASE_IDX                                                                  0
234 #define mmSDMA1_GFX_CONTEXT_CNTL                                                                       0x0093
235 #define mmSDMA1_GFX_CONTEXT_CNTL_BASE_IDX                                                              0
236 #define mmSDMA1_GFX_STATUS                                                                             0x00a8
237 #define mmSDMA1_GFX_STATUS_BASE_IDX                                                                    0
238 #define mmSDMA1_GFX_DOORBELL_LOG                                                                       0x00a9
239 #define mmSDMA1_GFX_DOORBELL_LOG_BASE_IDX                                                              0
240 #define mmSDMA1_GFX_WATERMARK                                                                          0x00aa
241 #define mmSDMA1_GFX_WATERMARK_BASE_IDX                                                                 0
242 #define mmSDMA1_GFX_DOORBELL_OFFSET                                                                    0x00ab
243 #define mmSDMA1_GFX_DOORBELL_OFFSET_BASE_IDX                                                           0
244 #define mmSDMA1_GFX_CSA_ADDR_LO                                                                        0x00ac
245 #define mmSDMA1_GFX_CSA_ADDR_LO_BASE_IDX                                                               0
246 #define mmSDMA1_GFX_CSA_ADDR_HI                                                                        0x00ad
247 #define mmSDMA1_GFX_CSA_ADDR_HI_BASE_IDX                                                               0
248 #define mmSDMA1_GFX_IB_SUB_REMAIN                                                                      0x00af
249 #define mmSDMA1_GFX_IB_SUB_REMAIN_BASE_IDX                                                             0
250 #define mmSDMA1_GFX_PREEMPT                                                                            0x00b0
251 #define mmSDMA1_GFX_PREEMPT_BASE_IDX                                                                   0
252 #define mmSDMA1_GFX_DUMMY_REG                                                                          0x00b1
253 #define mmSDMA1_GFX_DUMMY_REG_BASE_IDX                                                                 0
254 #define mmSDMA1_GFX_RB_WPTR_POLL_ADDR_HI                                                               0x00b2
255 #define mmSDMA1_GFX_RB_WPTR_POLL_ADDR_HI_BASE_IDX                                                      0
256 #define mmSDMA1_GFX_RB_WPTR_POLL_ADDR_LO                                                               0x00b3
257 #define mmSDMA1_GFX_RB_WPTR_POLL_ADDR_LO_BASE_IDX                                                      0
258 #define mmSDMA1_GFX_RB_AQL_CNTL                                                                        0x00b4
259 #define mmSDMA1_GFX_RB_AQL_CNTL_BASE_IDX                                                               0
260 #define mmSDMA1_GFX_MINOR_PTR_UPDATE                                                                   0x00b5
261 #define mmSDMA1_GFX_MINOR_PTR_UPDATE_BASE_IDX                                                          0
262 #define mmSDMA1_GFX_MIDCMD_DATA0                                                                       0x00c0
263 #define mmSDMA1_GFX_MIDCMD_DATA0_BASE_IDX                                                              0
264 #define mmSDMA1_GFX_MIDCMD_DATA1                                                                       0x00c1
265 #define mmSDMA1_GFX_MIDCMD_DATA1_BASE_IDX                                                              0
266 #define mmSDMA1_GFX_MIDCMD_DATA2                                                                       0x00c2
267 #define mmSDMA1_GFX_MIDCMD_DATA2_BASE_IDX                                                              0
268 #define mmSDMA1_GFX_MIDCMD_DATA3                                                                       0x00c3
269 #define mmSDMA1_GFX_MIDCMD_DATA3_BASE_IDX                                                              0
270 #define mmSDMA1_GFX_MIDCMD_DATA4                                                                       0x00c4
271 #define mmSDMA1_GFX_MIDCMD_DATA4_BASE_IDX                                                              0
272 #define mmSDMA1_GFX_MIDCMD_DATA5                                                                       0x00c5
273 #define mmSDMA1_GFX_MIDCMD_DATA5_BASE_IDX                                                              0
274 #define mmSDMA1_GFX_MIDCMD_DATA6                                                                       0x00c6
275 #define mmSDMA1_GFX_MIDCMD_DATA6_BASE_IDX                                                              0
276 #define mmSDMA1_GFX_MIDCMD_DATA7                                                                       0x00c7
277 #define mmSDMA1_GFX_MIDCMD_DATA7_BASE_IDX                                                              0
278 #define mmSDMA1_GFX_MIDCMD_DATA8                                                                       0x00c8
279 #define mmSDMA1_GFX_MIDCMD_DATA8_BASE_IDX                                                              0
280 #define mmSDMA1_GFX_MIDCMD_CNTL                                                                        0x00c9
281 #define mmSDMA1_GFX_MIDCMD_CNTL_BASE_IDX                                                               0
282 #define mmSDMA1_PAGE_RB_CNTL                                                                           0x00e0
283 #define mmSDMA1_PAGE_RB_CNTL_BASE_IDX                                                                  0
284 #define mmSDMA1_PAGE_RB_BASE                                                                           0x00e1
285 #define mmSDMA1_PAGE_RB_BASE_BASE_IDX                                                                  0
286 #define mmSDMA1_PAGE_RB_BASE_HI                                                                        0x00e2
287 #define mmSDMA1_PAGE_RB_BASE_HI_BASE_IDX                                                               0
288 #define mmSDMA1_PAGE_RB_RPTR                                                                           0x00e3
289 #define mmSDMA1_PAGE_RB_RPTR_BASE_IDX                                                                  0
290 #define mmSDMA1_PAGE_RB_RPTR_HI                                                                        0x00e4
291 #define mmSDMA1_PAGE_RB_RPTR_HI_BASE_IDX                                                               0
292 #define mmSDMA1_PAGE_RB_WPTR                                                                           0x00e5
293 #define mmSDMA1_PAGE_RB_WPTR_BASE_IDX                                                                  0
294 #define mmSDMA1_PAGE_RB_WPTR_HI                                                                        0x00e6
295 #define mmSDMA1_PAGE_RB_WPTR_HI_BASE_IDX                                                               0
296 #define mmSDMA1_PAGE_RB_WPTR_POLL_CNTL                                                                 0x00e7
297 #define mmSDMA1_PAGE_RB_WPTR_POLL_CNTL_BASE_IDX                                                        0
298 #define mmSDMA1_PAGE_RB_RPTR_ADDR_HI                                                                   0x00e8
299 #define mmSDMA1_PAGE_RB_RPTR_ADDR_HI_BASE_IDX                                                          0
300 #define mmSDMA1_PAGE_RB_RPTR_ADDR_LO                                                                   0x00e9
301 #define mmSDMA1_PAGE_RB_RPTR_ADDR_LO_BASE_IDX                                                          0
302 #define mmSDMA1_PAGE_IB_CNTL                                                                           0x00ea
303 #define mmSDMA1_PAGE_IB_CNTL_BASE_IDX                                                                  0
304 #define mmSDMA1_PAGE_IB_RPTR                                                                           0x00eb
305 #define mmSDMA1_PAGE_IB_RPTR_BASE_IDX                                                                  0
306 #define mmSDMA1_PAGE_IB_OFFSET                                                                         0x00ec
307 #define mmSDMA1_PAGE_IB_OFFSET_BASE_IDX                                                                0
308 #define mmSDMA1_PAGE_IB_BASE_LO                                                                        0x00ed
309 #define mmSDMA1_PAGE_IB_BASE_LO_BASE_IDX                                                               0
310 #define mmSDMA1_PAGE_IB_BASE_HI                                                                        0x00ee
311 #define mmSDMA1_PAGE_IB_BASE_HI_BASE_IDX                                                               0
312 #define mmSDMA1_PAGE_IB_SIZE                                                                           0x00ef
313 #define mmSDMA1_PAGE_IB_SIZE_BASE_IDX                                                                  0
314 #define mmSDMA1_PAGE_SKIP_CNTL                                                                         0x00f0
315 #define mmSDMA1_PAGE_SKIP_CNTL_BASE_IDX                                                                0
316 #define mmSDMA1_PAGE_CONTEXT_STATUS                                                                    0x00f1
317 #define mmSDMA1_PAGE_CONTEXT_STATUS_BASE_IDX                                                           0
318 #define mmSDMA1_PAGE_DOORBELL                                                                          0x00f2
319 #define mmSDMA1_PAGE_DOORBELL_BASE_IDX                                                                 0
320 #define mmSDMA1_PAGE_STATUS                                                                            0x0108
321 #define mmSDMA1_PAGE_STATUS_BASE_IDX                                                                   0
322 #define mmSDMA1_PAGE_DOORBELL_LOG                                                                      0x0109
323 #define mmSDMA1_PAGE_DOORBELL_LOG_BASE_IDX                                                             0
324 #define mmSDMA1_PAGE_WATERMARK                                                                         0x010a
325 #define mmSDMA1_PAGE_WATERMARK_BASE_IDX                                                                0
326 #define mmSDMA1_PAGE_DOORBELL_OFFSET                                                                   0x010b
327 #define mmSDMA1_PAGE_DOORBELL_OFFSET_BASE_IDX                                                          0
328 #define mmSDMA1_PAGE_CSA_ADDR_LO                                                                       0x010c
329 #define mmSDMA1_PAGE_CSA_ADDR_LO_BASE_IDX                                                              0
330 #define mmSDMA1_PAGE_CSA_ADDR_HI                                                                       0x010d
331 #define mmSDMA1_PAGE_CSA_ADDR_HI_BASE_IDX                                                              0
332 #define mmSDMA1_PAGE_IB_SUB_REMAIN                                                                     0x010f
333 #define mmSDMA1_PAGE_IB_SUB_REMAIN_BASE_IDX                                                            0
334 #define mmSDMA1_PAGE_PREEMPT                                                                           0x0110
335 #define mmSDMA1_PAGE_PREEMPT_BASE_IDX                                                                  0
336 #define mmSDMA1_PAGE_DUMMY_REG                                                                         0x0111
337 #define mmSDMA1_PAGE_DUMMY_REG_BASE_IDX                                                                0
338 #define mmSDMA1_PAGE_RB_WPTR_POLL_ADDR_HI                                                              0x0112
339 #define mmSDMA1_PAGE_RB_WPTR_POLL_ADDR_HI_BASE_IDX                                                     0
340 #define mmSDMA1_PAGE_RB_WPTR_POLL_ADDR_LO                                                              0x0113
341 #define mmSDMA1_PAGE_RB_WPTR_POLL_ADDR_LO_BASE_IDX                                                     0
342 #define mmSDMA1_PAGE_RB_AQL_CNTL                                                                       0x0114
343 #define mmSDMA1_PAGE_RB_AQL_CNTL_BASE_IDX                                                              0
344 #define mmSDMA1_PAGE_MINOR_PTR_UPDATE                                                                  0x0115
345 #define mmSDMA1_PAGE_MINOR_PTR_UPDATE_BASE_IDX                                                         0
346 #define mmSDMA1_PAGE_MIDCMD_DATA0                                                                      0x0120
347 #define mmSDMA1_PAGE_MIDCMD_DATA0_BASE_IDX                                                             0
348 #define mmSDMA1_PAGE_MIDCMD_DATA1                                                                      0x0121
349 #define mmSDMA1_PAGE_MIDCMD_DATA1_BASE_IDX                                                             0
350 #define mmSDMA1_PAGE_MIDCMD_DATA2                                                                      0x0122
351 #define mmSDMA1_PAGE_MIDCMD_DATA2_BASE_IDX                                                             0
352 #define mmSDMA1_PAGE_MIDCMD_DATA3                                                                      0x0123
353 #define mmSDMA1_PAGE_MIDCMD_DATA3_BASE_IDX                                                             0
354 #define mmSDMA1_PAGE_MIDCMD_DATA4                                                                      0x0124
355 #define mmSDMA1_PAGE_MIDCMD_DATA4_BASE_IDX                                                             0
356 #define mmSDMA1_PAGE_MIDCMD_DATA5                                                                      0x0125
357 #define mmSDMA1_PAGE_MIDCMD_DATA5_BASE_IDX                                                             0
358 #define mmSDMA1_PAGE_MIDCMD_DATA6                                                                      0x0126
359 #define mmSDMA1_PAGE_MIDCMD_DATA6_BASE_IDX                                                             0
360 #define mmSDMA1_PAGE_MIDCMD_DATA7                                                                      0x0127
361 #define mmSDMA1_PAGE_MIDCMD_DATA7_BASE_IDX                                                             0
362 #define mmSDMA1_PAGE_MIDCMD_DATA8                                                                      0x0128
363 #define mmSDMA1_PAGE_MIDCMD_DATA8_BASE_IDX                                                             0
364 #define mmSDMA1_PAGE_MIDCMD_CNTL                                                                       0x0129
365 #define mmSDMA1_PAGE_MIDCMD_CNTL_BASE_IDX                                                              0
366 #define mmSDMA1_RLC0_RB_CNTL                                                                           0x0140
367 #define mmSDMA1_RLC0_RB_CNTL_BASE_IDX                                                                  0
368 #define mmSDMA1_RLC0_RB_BASE                                                                           0x0141
369 #define mmSDMA1_RLC0_RB_BASE_BASE_IDX                                                                  0
370 #define mmSDMA1_RLC0_RB_BASE_HI                                                                        0x0142
371 #define mmSDMA1_RLC0_RB_BASE_HI_BASE_IDX                                                               0
372 #define mmSDMA1_RLC0_RB_RPTR                                                                           0x0143
373 #define mmSDMA1_RLC0_RB_RPTR_BASE_IDX                                                                  0
374 #define mmSDMA1_RLC0_RB_RPTR_HI                                                                        0x0144
375 #define mmSDMA1_RLC0_RB_RPTR_HI_BASE_IDX                                                               0
376 #define mmSDMA1_RLC0_RB_WPTR                                                                           0x0145
377 #define mmSDMA1_RLC0_RB_WPTR_BASE_IDX                                                                  0
378 #define mmSDMA1_RLC0_RB_WPTR_HI                                                                        0x0146
379 #define mmSDMA1_RLC0_RB_WPTR_HI_BASE_IDX                                                               0
380 #define mmSDMA1_RLC0_RB_WPTR_POLL_CNTL                                                                 0x0147
381 #define mmSDMA1_RLC0_RB_WPTR_POLL_CNTL_BASE_IDX                                                        0
382 #define mmSDMA1_RLC0_RB_RPTR_ADDR_HI                                                                   0x0148
383 #define mmSDMA1_RLC0_RB_RPTR_ADDR_HI_BASE_IDX                                                          0
384 #define mmSDMA1_RLC0_RB_RPTR_ADDR_LO                                                                   0x0149
385 #define mmSDMA1_RLC0_RB_RPTR_ADDR_LO_BASE_IDX                                                          0
386 #define mmSDMA1_RLC0_IB_CNTL                                                                           0x014a
387 #define mmSDMA1_RLC0_IB_CNTL_BASE_IDX                                                                  0
388 #define mmSDMA1_RLC0_IB_RPTR                                                                           0x014b
389 #define mmSDMA1_RLC0_IB_RPTR_BASE_IDX                                                                  0
390 #define mmSDMA1_RLC0_IB_OFFSET                                                                         0x014c
391 #define mmSDMA1_RLC0_IB_OFFSET_BASE_IDX                                                                0
392 #define mmSDMA1_RLC0_IB_BASE_LO                                                                        0x014d
393 #define mmSDMA1_RLC0_IB_BASE_LO_BASE_IDX                                                               0
394 #define mmSDMA1_RLC0_IB_BASE_HI                                                                        0x014e
395 #define mmSDMA1_RLC0_IB_BASE_HI_BASE_IDX                                                               0
396 #define mmSDMA1_RLC0_IB_SIZE                                                                           0x014f
397 #define mmSDMA1_RLC0_IB_SIZE_BASE_IDX                                                                  0
398 #define mmSDMA1_RLC0_SKIP_CNTL                                                                         0x0150
399 #define mmSDMA1_RLC0_SKIP_CNTL_BASE_IDX                                                                0
400 #define mmSDMA1_RLC0_CONTEXT_STATUS                                                                    0x0151
401 #define mmSDMA1_RLC0_CONTEXT_STATUS_BASE_IDX                                                           0
402 #define mmSDMA1_RLC0_DOORBELL                                                                          0x0152
403 #define mmSDMA1_RLC0_DOORBELL_BASE_IDX                                                                 0
404 #define mmSDMA1_RLC0_STATUS                                                                            0x0168
405 #define mmSDMA1_RLC0_STATUS_BASE_IDX                                                                   0
406 #define mmSDMA1_RLC0_DOORBELL_LOG                                                                      0x0169
407 #define mmSDMA1_RLC0_DOORBELL_LOG_BASE_IDX                                                             0
408 #define mmSDMA1_RLC0_WATERMARK                                                                         0x016a
409 #define mmSDMA1_RLC0_WATERMARK_BASE_IDX                                                                0
410 #define mmSDMA1_RLC0_DOORBELL_OFFSET                                                                   0x016b
411 #define mmSDMA1_RLC0_DOORBELL_OFFSET_BASE_IDX                                                          0
412 #define mmSDMA1_RLC0_CSA_ADDR_LO                                                                       0x016c
413 #define mmSDMA1_RLC0_CSA_ADDR_LO_BASE_IDX                                                              0
414 #define mmSDMA1_RLC0_CSA_ADDR_HI                                                                       0x016d
415 #define mmSDMA1_RLC0_CSA_ADDR_HI_BASE_IDX                                                              0
416 #define mmSDMA1_RLC0_IB_SUB_REMAIN                                                                     0x016f
417 #define mmSDMA1_RLC0_IB_SUB_REMAIN_BASE_IDX                                                            0
418 #define mmSDMA1_RLC0_PREEMPT                                                                           0x0170
419 #define mmSDMA1_RLC0_PREEMPT_BASE_IDX                                                                  0
420 #define mmSDMA1_RLC0_DUMMY_REG                                                                         0x0171
421 #define mmSDMA1_RLC0_DUMMY_REG_BASE_IDX                                                                0
422 #define mmSDMA1_RLC0_RB_WPTR_POLL_ADDR_HI                                                              0x0172
423 #define mmSDMA1_RLC0_RB_WPTR_POLL_ADDR_HI_BASE_IDX                                                     0
424 #define mmSDMA1_RLC0_RB_WPTR_POLL_ADDR_LO                                                              0x0173
425 #define mmSDMA1_RLC0_RB_WPTR_POLL_ADDR_LO_BASE_IDX                                                     0
426 #define mmSDMA1_RLC0_RB_AQL_CNTL                                                                       0x0174
427 #define mmSDMA1_RLC0_RB_AQL_CNTL_BASE_IDX                                                              0
428 #define mmSDMA1_RLC0_MINOR_PTR_UPDATE                                                                  0x0175
429 #define mmSDMA1_RLC0_MINOR_PTR_UPDATE_BASE_IDX                                                         0
430 #define mmSDMA1_RLC0_MIDCMD_DATA0                                                                      0x0180
431 #define mmSDMA1_RLC0_MIDCMD_DATA0_BASE_IDX                                                             0
432 #define mmSDMA1_RLC0_MIDCMD_DATA1                                                                      0x0181
433 #define mmSDMA1_RLC0_MIDCMD_DATA1_BASE_IDX                                                             0
434 #define mmSDMA1_RLC0_MIDCMD_DATA2                                                                      0x0182
435 #define mmSDMA1_RLC0_MIDCMD_DATA2_BASE_IDX                                                             0
436 #define mmSDMA1_RLC0_MIDCMD_DATA3                                                                      0x0183
437 #define mmSDMA1_RLC0_MIDCMD_DATA3_BASE_IDX                                                             0
438 #define mmSDMA1_RLC0_MIDCMD_DATA4                                                                      0x0184
439 #define mmSDMA1_RLC0_MIDCMD_DATA4_BASE_IDX                                                             0
440 #define mmSDMA1_RLC0_MIDCMD_DATA5                                                                      0x0185
441 #define mmSDMA1_RLC0_MIDCMD_DATA5_BASE_IDX                                                             0
442 #define mmSDMA1_RLC0_MIDCMD_DATA6                                                                      0x0186
443 #define mmSDMA1_RLC0_MIDCMD_DATA6_BASE_IDX                                                             0
444 #define mmSDMA1_RLC0_MIDCMD_DATA7                                                                      0x0187
445 #define mmSDMA1_RLC0_MIDCMD_DATA7_BASE_IDX                                                             0
446 #define mmSDMA1_RLC0_MIDCMD_DATA8                                                                      0x0188
447 #define mmSDMA1_RLC0_MIDCMD_DATA8_BASE_IDX                                                             0
448 #define mmSDMA1_RLC0_MIDCMD_CNTL                                                                       0x0189
449 #define mmSDMA1_RLC0_MIDCMD_CNTL_BASE_IDX                                                              0
450 #define mmSDMA1_RLC1_RB_CNTL                                                                           0x01a0
451 #define mmSDMA1_RLC1_RB_CNTL_BASE_IDX                                                                  0
452 #define mmSDMA1_RLC1_RB_BASE                                                                           0x01a1
453 #define mmSDMA1_RLC1_RB_BASE_BASE_IDX                                                                  0
454 #define mmSDMA1_RLC1_RB_BASE_HI                                                                        0x01a2
455 #define mmSDMA1_RLC1_RB_BASE_HI_BASE_IDX                                                               0
456 #define mmSDMA1_RLC1_RB_RPTR                                                                           0x01a3
457 #define mmSDMA1_RLC1_RB_RPTR_BASE_IDX                                                                  0
458 #define mmSDMA1_RLC1_RB_RPTR_HI                                                                        0x01a4
459 #define mmSDMA1_RLC1_RB_RPTR_HI_BASE_IDX                                                               0
460 #define mmSDMA1_RLC1_RB_WPTR                                                                           0x01a5
461 #define mmSDMA1_RLC1_RB_WPTR_BASE_IDX                                                                  0
462 #define mmSDMA1_RLC1_RB_WPTR_HI                                                                        0x01a6
463 #define mmSDMA1_RLC1_RB_WPTR_HI_BASE_IDX                                                               0
464 #define mmSDMA1_RLC1_RB_WPTR_POLL_CNTL                                                                 0x01a7
465 #define mmSDMA1_RLC1_RB_WPTR_POLL_CNTL_BASE_IDX                                                        0
466 #define mmSDMA1_RLC1_RB_RPTR_ADDR_HI                                                                   0x01a8
467 #define mmSDMA1_RLC1_RB_RPTR_ADDR_HI_BASE_IDX                                                          0
468 #define mmSDMA1_RLC1_RB_RPTR_ADDR_LO                                                                   0x01a9
469 #define mmSDMA1_RLC1_RB_RPTR_ADDR_LO_BASE_IDX                                                          0
470 #define mmSDMA1_RLC1_IB_CNTL                                                                           0x01aa
471 #define mmSDMA1_RLC1_IB_CNTL_BASE_IDX                                                                  0
472 #define mmSDMA1_RLC1_IB_RPTR                                                                           0x01ab
473 #define mmSDMA1_RLC1_IB_RPTR_BASE_IDX                                                                  0
474 #define mmSDMA1_RLC1_IB_OFFSET                                                                         0x01ac
475 #define mmSDMA1_RLC1_IB_OFFSET_BASE_IDX                                                                0
476 #define mmSDMA1_RLC1_IB_BASE_LO                                                                        0x01ad
477 #define mmSDMA1_RLC1_IB_BASE_LO_BASE_IDX                                                               0
478 #define mmSDMA1_RLC1_IB_BASE_HI                                                                        0x01ae
479 #define mmSDMA1_RLC1_IB_BASE_HI_BASE_IDX                                                               0
480 #define mmSDMA1_RLC1_IB_SIZE                                                                           0x01af
481 #define mmSDMA1_RLC1_IB_SIZE_BASE_IDX                                                                  0
482 #define mmSDMA1_RLC1_SKIP_CNTL                                                                         0x01b0
483 #define mmSDMA1_RLC1_SKIP_CNTL_BASE_IDX                                                                0
484 #define mmSDMA1_RLC1_CONTEXT_STATUS                                                                    0x01b1
485 #define mmSDMA1_RLC1_CONTEXT_STATUS_BASE_IDX                                                           0
486 #define mmSDMA1_RLC1_DOORBELL                                                                          0x01b2
487 #define mmSDMA1_RLC1_DOORBELL_BASE_IDX                                                                 0
488 #define mmSDMA1_RLC1_STATUS                                                                            0x01c8
489 #define mmSDMA1_RLC1_STATUS_BASE_IDX                                                                   0
490 #define mmSDMA1_RLC1_DOORBELL_LOG                                                                      0x01c9
491 #define mmSDMA1_RLC1_DOORBELL_LOG_BASE_IDX                                                             0
492 #define mmSDMA1_RLC1_WATERMARK                                                                         0x01ca
493 #define mmSDMA1_RLC1_WATERMARK_BASE_IDX                                                                0
494 #define mmSDMA1_RLC1_DOORBELL_OFFSET                                                                   0x01cb
495 #define mmSDMA1_RLC1_DOORBELL_OFFSET_BASE_IDX                                                          0
496 #define mmSDMA1_RLC1_CSA_ADDR_LO                                                                       0x01cc
497 #define mmSDMA1_RLC1_CSA_ADDR_LO_BASE_IDX                                                              0
498 #define mmSDMA1_RLC1_CSA_ADDR_HI                                                                       0x01cd
499 #define mmSDMA1_RLC1_CSA_ADDR_HI_BASE_IDX                                                              0
500 #define mmSDMA1_RLC1_IB_SUB_REMAIN                                                                     0x01cf
501 #define mmSDMA1_RLC1_IB_SUB_REMAIN_BASE_IDX                                                            0
502 #define mmSDMA1_RLC1_PREEMPT                                                                           0x01d0
503 #define mmSDMA1_RLC1_PREEMPT_BASE_IDX                                                                  0
504 #define mmSDMA1_RLC1_DUMMY_REG                                                                         0x01d1
505 #define mmSDMA1_RLC1_DUMMY_REG_BASE_IDX                                                                0
506 #define mmSDMA1_RLC1_RB_WPTR_POLL_ADDR_HI                                                              0x01d2
507 #define mmSDMA1_RLC1_RB_WPTR_POLL_ADDR_HI_BASE_IDX                                                     0
508 #define mmSDMA1_RLC1_RB_WPTR_POLL_ADDR_LO                                                              0x01d3
509 #define mmSDMA1_RLC1_RB_WPTR_POLL_ADDR_LO_BASE_IDX                                                     0
510 #define mmSDMA1_RLC1_RB_AQL_CNTL                                                                       0x01d4
511 #define mmSDMA1_RLC1_RB_AQL_CNTL_BASE_IDX                                                              0
512 #define mmSDMA1_RLC1_MINOR_PTR_UPDATE                                                                  0x01d5
513 #define mmSDMA1_RLC1_MINOR_PTR_UPDATE_BASE_IDX                                                         0
514 #define mmSDMA1_RLC1_MIDCMD_DATA0                                                                      0x01e0
515 #define mmSDMA1_RLC1_MIDCMD_DATA0_BASE_IDX                                                             0
516 #define mmSDMA1_RLC1_MIDCMD_DATA1                                                                      0x01e1
517 #define mmSDMA1_RLC1_MIDCMD_DATA1_BASE_IDX                                                             0
518 #define mmSDMA1_RLC1_MIDCMD_DATA2                                                                      0x01e2
519 #define mmSDMA1_RLC1_MIDCMD_DATA2_BASE_IDX                                                             0
520 #define mmSDMA1_RLC1_MIDCMD_DATA3                                                                      0x01e3
521 #define mmSDMA1_RLC1_MIDCMD_DATA3_BASE_IDX                                                             0
522 #define mmSDMA1_RLC1_MIDCMD_DATA4                                                                      0x01e4
523 #define mmSDMA1_RLC1_MIDCMD_DATA4_BASE_IDX                                                             0
524 #define mmSDMA1_RLC1_MIDCMD_DATA5                                                                      0x01e5
525 #define mmSDMA1_RLC1_MIDCMD_DATA5_BASE_IDX                                                             0
526 #define mmSDMA1_RLC1_MIDCMD_DATA6                                                                      0x01e6
527 #define mmSDMA1_RLC1_MIDCMD_DATA6_BASE_IDX                                                             0
528 #define mmSDMA1_RLC1_MIDCMD_DATA7                                                                      0x01e7
529 #define mmSDMA1_RLC1_MIDCMD_DATA7_BASE_IDX                                                             0
530 #define mmSDMA1_RLC1_MIDCMD_DATA8                                                                      0x01e8
531 #define mmSDMA1_RLC1_MIDCMD_DATA8_BASE_IDX                                                             0
532 #define mmSDMA1_RLC1_MIDCMD_CNTL                                                                       0x01e9
533 #define mmSDMA1_RLC1_MIDCMD_CNTL_BASE_IDX                                                              0
534 #define mmSDMA1_RLC2_RB_CNTL                                                                           0x0200
535 #define mmSDMA1_RLC2_RB_CNTL_BASE_IDX                                                                  0
536 #define mmSDMA1_RLC2_RB_BASE                                                                           0x0201
537 #define mmSDMA1_RLC2_RB_BASE_BASE_IDX                                                                  0
538 #define mmSDMA1_RLC2_RB_BASE_HI                                                                        0x0202
539 #define mmSDMA1_RLC2_RB_BASE_HI_BASE_IDX                                                               0
540 #define mmSDMA1_RLC2_RB_RPTR                                                                           0x0203
541 #define mmSDMA1_RLC2_RB_RPTR_BASE_IDX                                                                  0
542 #define mmSDMA1_RLC2_RB_RPTR_HI                                                                        0x0204
543 #define mmSDMA1_RLC2_RB_RPTR_HI_BASE_IDX                                                               0
544 #define mmSDMA1_RLC2_RB_WPTR                                                                           0x0205
545 #define mmSDMA1_RLC2_RB_WPTR_BASE_IDX                                                                  0
546 #define mmSDMA1_RLC2_RB_WPTR_HI                                                                        0x0206
547 #define mmSDMA1_RLC2_RB_WPTR_HI_BASE_IDX                                                               0
548 #define mmSDMA1_RLC2_RB_WPTR_POLL_CNTL                                                                 0x0207
549 #define mmSDMA1_RLC2_RB_WPTR_POLL_CNTL_BASE_IDX                                                        0
550 #define mmSDMA1_RLC2_RB_RPTR_ADDR_HI                                                                   0x0208
551 #define mmSDMA1_RLC2_RB_RPTR_ADDR_HI_BASE_IDX                                                          0
552 #define mmSDMA1_RLC2_RB_RPTR_ADDR_LO                                                                   0x0209
553 #define mmSDMA1_RLC2_RB_RPTR_ADDR_LO_BASE_IDX                                                          0
554 #define mmSDMA1_RLC2_IB_CNTL                                                                           0x020a
555 #define mmSDMA1_RLC2_IB_CNTL_BASE_IDX                                                                  0
556 #define mmSDMA1_RLC2_IB_RPTR                                                                           0x020b
557 #define mmSDMA1_RLC2_IB_RPTR_BASE_IDX                                                                  0
558 #define mmSDMA1_RLC2_IB_OFFSET                                                                         0x020c
559 #define mmSDMA1_RLC2_IB_OFFSET_BASE_IDX                                                                0
560 #define mmSDMA1_RLC2_IB_BASE_LO                                                                        0x020d
561 #define mmSDMA1_RLC2_IB_BASE_LO_BASE_IDX                                                               0
562 #define mmSDMA1_RLC2_IB_BASE_HI                                                                        0x020e
563 #define mmSDMA1_RLC2_IB_BASE_HI_BASE_IDX                                                               0
564 #define mmSDMA1_RLC2_IB_SIZE                                                                           0x020f
565 #define mmSDMA1_RLC2_IB_SIZE_BASE_IDX                                                                  0
566 #define mmSDMA1_RLC2_SKIP_CNTL                                                                         0x0210
567 #define mmSDMA1_RLC2_SKIP_CNTL_BASE_IDX                                                                0
568 #define mmSDMA1_RLC2_CONTEXT_STATUS                                                                    0x0211
569 #define mmSDMA1_RLC2_CONTEXT_STATUS_BASE_IDX                                                           0
570 #define mmSDMA1_RLC2_DOORBELL                                                                          0x0212
571 #define mmSDMA1_RLC2_DOORBELL_BASE_IDX                                                                 0
572 #define mmSDMA1_RLC2_STATUS                                                                            0x0228
573 #define mmSDMA1_RLC2_STATUS_BASE_IDX                                                                   0
574 #define mmSDMA1_RLC2_DOORBELL_LOG                                                                      0x0229
575 #define mmSDMA1_RLC2_DOORBELL_LOG_BASE_IDX                                                             0
576 #define mmSDMA1_RLC2_WATERMARK                                                                         0x022a
577 #define mmSDMA1_RLC2_WATERMARK_BASE_IDX                                                                0
578 #define mmSDMA1_RLC2_DOORBELL_OFFSET                                                                   0x022b
579 #define mmSDMA1_RLC2_DOORBELL_OFFSET_BASE_IDX                                                          0
580 #define mmSDMA1_RLC2_CSA_ADDR_LO                                                                       0x022c
581 #define mmSDMA1_RLC2_CSA_ADDR_LO_BASE_IDX                                                              0
582 #define mmSDMA1_RLC2_CSA_ADDR_HI                                                                       0x022d
583 #define mmSDMA1_RLC2_CSA_ADDR_HI_BASE_IDX                                                              0
584 #define mmSDMA1_RLC2_IB_SUB_REMAIN                                                                     0x022f
585 #define mmSDMA1_RLC2_IB_SUB_REMAIN_BASE_IDX                                                            0
586 #define mmSDMA1_RLC2_PREEMPT                                                                           0x0230
587 #define mmSDMA1_RLC2_PREEMPT_BASE_IDX                                                                  0
588 #define mmSDMA1_RLC2_DUMMY_REG                                                                         0x0231
589 #define mmSDMA1_RLC2_DUMMY_REG_BASE_IDX                                                                0
590 #define mmSDMA1_RLC2_RB_WPTR_POLL_ADDR_HI                                                              0x0232
591 #define mmSDMA1_RLC2_RB_WPTR_POLL_ADDR_HI_BASE_IDX                                                     0
592 #define mmSDMA1_RLC2_RB_WPTR_POLL_ADDR_LO                                                              0x0233
593 #define mmSDMA1_RLC2_RB_WPTR_POLL_ADDR_LO_BASE_IDX                                                     0
594 #define mmSDMA1_RLC2_RB_AQL_CNTL                                                                       0x0234
595 #define mmSDMA1_RLC2_RB_AQL_CNTL_BASE_IDX                                                              0
596 #define mmSDMA1_RLC2_MINOR_PTR_UPDATE                                                                  0x0235
597 #define mmSDMA1_RLC2_MINOR_PTR_UPDATE_BASE_IDX                                                         0
598 #define mmSDMA1_RLC2_MIDCMD_DATA0                                                                      0x0240
599 #define mmSDMA1_RLC2_MIDCMD_DATA0_BASE_IDX                                                             0
600 #define mmSDMA1_RLC2_MIDCMD_DATA1                                                                      0x0241
601 #define mmSDMA1_RLC2_MIDCMD_DATA1_BASE_IDX                                                             0
602 #define mmSDMA1_RLC2_MIDCMD_DATA2                                                                      0x0242
603 #define mmSDMA1_RLC2_MIDCMD_DATA2_BASE_IDX                                                             0
604 #define mmSDMA1_RLC2_MIDCMD_DATA3                                                                      0x0243
605 #define mmSDMA1_RLC2_MIDCMD_DATA3_BASE_IDX                                                             0
606 #define mmSDMA1_RLC2_MIDCMD_DATA4                                                                      0x0244
607 #define mmSDMA1_RLC2_MIDCMD_DATA4_BASE_IDX                                                             0
608 #define mmSDMA1_RLC2_MIDCMD_DATA5                                                                      0x0245
609 #define mmSDMA1_RLC2_MIDCMD_DATA5_BASE_IDX                                                             0
610 #define mmSDMA1_RLC2_MIDCMD_DATA6                                                                      0x0246
611 #define mmSDMA1_RLC2_MIDCMD_DATA6_BASE_IDX                                                             0
612 #define mmSDMA1_RLC2_MIDCMD_DATA7                                                                      0x0247
613 #define mmSDMA1_RLC2_MIDCMD_DATA7_BASE_IDX                                                             0
614 #define mmSDMA1_RLC2_MIDCMD_DATA8                                                                      0x0248
615 #define mmSDMA1_RLC2_MIDCMD_DATA8_BASE_IDX                                                             0
616 #define mmSDMA1_RLC2_MIDCMD_CNTL                                                                       0x0249
617 #define mmSDMA1_RLC2_MIDCMD_CNTL_BASE_IDX                                                              0
618 #define mmSDMA1_RLC3_RB_CNTL                                                                           0x0260
619 #define mmSDMA1_RLC3_RB_CNTL_BASE_IDX                                                                  0
620 #define mmSDMA1_RLC3_RB_BASE                                                                           0x0261
621 #define mmSDMA1_RLC3_RB_BASE_BASE_IDX                                                                  0
622 #define mmSDMA1_RLC3_RB_BASE_HI                                                                        0x0262
623 #define mmSDMA1_RLC3_RB_BASE_HI_BASE_IDX                                                               0
624 #define mmSDMA1_RLC3_RB_RPTR                                                                           0x0263
625 #define mmSDMA1_RLC3_RB_RPTR_BASE_IDX                                                                  0
626 #define mmSDMA1_RLC3_RB_RPTR_HI                                                                        0x0264
627 #define mmSDMA1_RLC3_RB_RPTR_HI_BASE_IDX                                                               0
628 #define mmSDMA1_RLC3_RB_WPTR                                                                           0x0265
629 #define mmSDMA1_RLC3_RB_WPTR_BASE_IDX                                                                  0
630 #define mmSDMA1_RLC3_RB_WPTR_HI                                                                        0x0266
631 #define mmSDMA1_RLC3_RB_WPTR_HI_BASE_IDX                                                               0
632 #define mmSDMA1_RLC3_RB_WPTR_POLL_CNTL                                                                 0x0267
633 #define mmSDMA1_RLC3_RB_WPTR_POLL_CNTL_BASE_IDX                                                        0
634 #define mmSDMA1_RLC3_RB_RPTR_ADDR_HI                                                                   0x0268
635 #define mmSDMA1_RLC3_RB_RPTR_ADDR_HI_BASE_IDX                                                          0
636 #define mmSDMA1_RLC3_RB_RPTR_ADDR_LO                                                                   0x0269
637 #define mmSDMA1_RLC3_RB_RPTR_ADDR_LO_BASE_IDX                                                          0
638 #define mmSDMA1_RLC3_IB_CNTL                                                                           0x026a
639 #define mmSDMA1_RLC3_IB_CNTL_BASE_IDX                                                                  0
640 #define mmSDMA1_RLC3_IB_RPTR                                                                           0x026b
641 #define mmSDMA1_RLC3_IB_RPTR_BASE_IDX                                                                  0
642 #define mmSDMA1_RLC3_IB_OFFSET                                                                         0x026c
643 #define mmSDMA1_RLC3_IB_OFFSET_BASE_IDX                                                                0
644 #define mmSDMA1_RLC3_IB_BASE_LO                                                                        0x026d
645 #define mmSDMA1_RLC3_IB_BASE_LO_BASE_IDX                                                               0
646 #define mmSDMA1_RLC3_IB_BASE_HI                                                                        0x026e
647 #define mmSDMA1_RLC3_IB_BASE_HI_BASE_IDX                                                               0
648 #define mmSDMA1_RLC3_IB_SIZE                                                                           0x026f
649 #define mmSDMA1_RLC3_IB_SIZE_BASE_IDX                                                                  0
650 #define mmSDMA1_RLC3_SKIP_CNTL                                                                         0x0270
651 #define mmSDMA1_RLC3_SKIP_CNTL_BASE_IDX                                                                0
652 #define mmSDMA1_RLC3_CONTEXT_STATUS                                                                    0x0271
653 #define mmSDMA1_RLC3_CONTEXT_STATUS_BASE_IDX                                                           0
654 #define mmSDMA1_RLC3_DOORBELL                                                                          0x0272
655 #define mmSDMA1_RLC3_DOORBELL_BASE_IDX                                                                 0
656 #define mmSDMA1_RLC3_STATUS                                                                            0x0288
657 #define mmSDMA1_RLC3_STATUS_BASE_IDX                                                                   0
658 #define mmSDMA1_RLC3_DOORBELL_LOG                                                                      0x0289
659 #define mmSDMA1_RLC3_DOORBELL_LOG_BASE_IDX                                                             0
660 #define mmSDMA1_RLC3_WATERMARK                                                                         0x028a
661 #define mmSDMA1_RLC3_WATERMARK_BASE_IDX                                                                0
662 #define mmSDMA1_RLC3_DOORBELL_OFFSET                                                                   0x028b
663 #define mmSDMA1_RLC3_DOORBELL_OFFSET_BASE_IDX                                                          0
664 #define mmSDMA1_RLC3_CSA_ADDR_LO                                                                       0x028c
665 #define mmSDMA1_RLC3_CSA_ADDR_LO_BASE_IDX                                                              0
666 #define mmSDMA1_RLC3_CSA_ADDR_HI                                                                       0x028d
667 #define mmSDMA1_RLC3_CSA_ADDR_HI_BASE_IDX                                                              0
668 #define mmSDMA1_RLC3_IB_SUB_REMAIN                                                                     0x028f
669 #define mmSDMA1_RLC3_IB_SUB_REMAIN_BASE_IDX                                                            0
670 #define mmSDMA1_RLC3_PREEMPT                                                                           0x0290
671 #define mmSDMA1_RLC3_PREEMPT_BASE_IDX                                                                  0
672 #define mmSDMA1_RLC3_DUMMY_REG                                                                         0x0291
673 #define mmSDMA1_RLC3_DUMMY_REG_BASE_IDX                                                                0
674 #define mmSDMA1_RLC3_RB_WPTR_POLL_ADDR_HI                                                              0x0292
675 #define mmSDMA1_RLC3_RB_WPTR_POLL_ADDR_HI_BASE_IDX                                                     0
676 #define mmSDMA1_RLC3_RB_WPTR_POLL_ADDR_LO                                                              0x0293
677 #define mmSDMA1_RLC3_RB_WPTR_POLL_ADDR_LO_BASE_IDX                                                     0
678 #define mmSDMA1_RLC3_RB_AQL_CNTL                                                                       0x0294
679 #define mmSDMA1_RLC3_RB_AQL_CNTL_BASE_IDX                                                              0
680 #define mmSDMA1_RLC3_MINOR_PTR_UPDATE                                                                  0x0295
681 #define mmSDMA1_RLC3_MINOR_PTR_UPDATE_BASE_IDX                                                         0
682 #define mmSDMA1_RLC3_MIDCMD_DATA0                                                                      0x02a0
683 #define mmSDMA1_RLC3_MIDCMD_DATA0_BASE_IDX                                                             0
684 #define mmSDMA1_RLC3_MIDCMD_DATA1                                                                      0x02a1
685 #define mmSDMA1_RLC3_MIDCMD_DATA1_BASE_IDX                                                             0
686 #define mmSDMA1_RLC3_MIDCMD_DATA2                                                                      0x02a2
687 #define mmSDMA1_RLC3_MIDCMD_DATA2_BASE_IDX                                                             0
688 #define mmSDMA1_RLC3_MIDCMD_DATA3                                                                      0x02a3
689 #define mmSDMA1_RLC3_MIDCMD_DATA3_BASE_IDX                                                             0
690 #define mmSDMA1_RLC3_MIDCMD_DATA4                                                                      0x02a4
691 #define mmSDMA1_RLC3_MIDCMD_DATA4_BASE_IDX                                                             0
692 #define mmSDMA1_RLC3_MIDCMD_DATA5                                                                      0x02a5
693 #define mmSDMA1_RLC3_MIDCMD_DATA5_BASE_IDX                                                             0
694 #define mmSDMA1_RLC3_MIDCMD_DATA6                                                                      0x02a6
695 #define mmSDMA1_RLC3_MIDCMD_DATA6_BASE_IDX                                                             0
696 #define mmSDMA1_RLC3_MIDCMD_DATA7                                                                      0x02a7
697 #define mmSDMA1_RLC3_MIDCMD_DATA7_BASE_IDX                                                             0
698 #define mmSDMA1_RLC3_MIDCMD_DATA8                                                                      0x02a8
699 #define mmSDMA1_RLC3_MIDCMD_DATA8_BASE_IDX                                                             0
700 #define mmSDMA1_RLC3_MIDCMD_CNTL                                                                       0x02a9
701 #define mmSDMA1_RLC3_MIDCMD_CNTL_BASE_IDX                                                              0
702 #define mmSDMA1_RLC4_RB_CNTL                                                                           0x02c0
703 #define mmSDMA1_RLC4_RB_CNTL_BASE_IDX                                                                  0
704 #define mmSDMA1_RLC4_RB_BASE                                                                           0x02c1
705 #define mmSDMA1_RLC4_RB_BASE_BASE_IDX                                                                  0
706 #define mmSDMA1_RLC4_RB_BASE_HI                                                                        0x02c2
707 #define mmSDMA1_RLC4_RB_BASE_HI_BASE_IDX                                                               0
708 #define mmSDMA1_RLC4_RB_RPTR                                                                           0x02c3
709 #define mmSDMA1_RLC4_RB_RPTR_BASE_IDX                                                                  0
710 #define mmSDMA1_RLC4_RB_RPTR_HI                                                                        0x02c4
711 #define mmSDMA1_RLC4_RB_RPTR_HI_BASE_IDX                                                               0
712 #define mmSDMA1_RLC4_RB_WPTR                                                                           0x02c5
713 #define mmSDMA1_RLC4_RB_WPTR_BASE_IDX                                                                  0
714 #define mmSDMA1_RLC4_RB_WPTR_HI                                                                        0x02c6
715 #define mmSDMA1_RLC4_RB_WPTR_HI_BASE_IDX                                                               0
716 #define mmSDMA1_RLC4_RB_WPTR_POLL_CNTL                                                                 0x02c7
717 #define mmSDMA1_RLC4_RB_WPTR_POLL_CNTL_BASE_IDX                                                        0
718 #define mmSDMA1_RLC4_RB_RPTR_ADDR_HI                                                                   0x02c8
719 #define mmSDMA1_RLC4_RB_RPTR_ADDR_HI_BASE_IDX                                                          0
720 #define mmSDMA1_RLC4_RB_RPTR_ADDR_LO                                                                   0x02c9
721 #define mmSDMA1_RLC4_RB_RPTR_ADDR_LO_BASE_IDX                                                          0
722 #define mmSDMA1_RLC4_IB_CNTL                                                                           0x02ca
723 #define mmSDMA1_RLC4_IB_CNTL_BASE_IDX                                                                  0
724 #define mmSDMA1_RLC4_IB_RPTR                                                                           0x02cb
725 #define mmSDMA1_RLC4_IB_RPTR_BASE_IDX                                                                  0
726 #define mmSDMA1_RLC4_IB_OFFSET                                                                         0x02cc
727 #define mmSDMA1_RLC4_IB_OFFSET_BASE_IDX                                                                0
728 #define mmSDMA1_RLC4_IB_BASE_LO                                                                        0x02cd
729 #define mmSDMA1_RLC4_IB_BASE_LO_BASE_IDX                                                               0
730 #define mmSDMA1_RLC4_IB_BASE_HI                                                                        0x02ce
731 #define mmSDMA1_RLC4_IB_BASE_HI_BASE_IDX                                                               0
732 #define mmSDMA1_RLC4_IB_SIZE                                                                           0x02cf
733 #define mmSDMA1_RLC4_IB_SIZE_BASE_IDX                                                                  0
734 #define mmSDMA1_RLC4_SKIP_CNTL                                                                         0x02d0
735 #define mmSDMA1_RLC4_SKIP_CNTL_BASE_IDX                                                                0
736 #define mmSDMA1_RLC4_CONTEXT_STATUS                                                                    0x02d1
737 #define mmSDMA1_RLC4_CONTEXT_STATUS_BASE_IDX                                                           0
738 #define mmSDMA1_RLC4_DOORBELL                                                                          0x02d2
739 #define mmSDMA1_RLC4_DOORBELL_BASE_IDX                                                                 0
740 #define mmSDMA1_RLC4_STATUS                                                                            0x02e8
741 #define mmSDMA1_RLC4_STATUS_BASE_IDX                                                                   0
742 #define mmSDMA1_RLC4_DOORBELL_LOG                                                                      0x02e9
743 #define mmSDMA1_RLC4_DOORBELL_LOG_BASE_IDX                                                             0
744 #define mmSDMA1_RLC4_WATERMARK                                                                         0x02ea
745 #define mmSDMA1_RLC4_WATERMARK_BASE_IDX                                                                0
746 #define mmSDMA1_RLC4_DOORBELL_OFFSET                                                                   0x02eb
747 #define mmSDMA1_RLC4_DOORBELL_OFFSET_BASE_IDX                                                          0
748 #define mmSDMA1_RLC4_CSA_ADDR_LO                                                                       0x02ec
749 #define mmSDMA1_RLC4_CSA_ADDR_LO_BASE_IDX                                                              0
750 #define mmSDMA1_RLC4_CSA_ADDR_HI                                                                       0x02ed
751 #define mmSDMA1_RLC4_CSA_ADDR_HI_BASE_IDX                                                              0
752 #define mmSDMA1_RLC4_IB_SUB_REMAIN                                                                     0x02ef
753 #define mmSDMA1_RLC4_IB_SUB_REMAIN_BASE_IDX                                                            0
754 #define mmSDMA1_RLC4_PREEMPT                                                                           0x02f0
755 #define mmSDMA1_RLC4_PREEMPT_BASE_IDX                                                                  0
756 #define mmSDMA1_RLC4_DUMMY_REG                                                                         0x02f1
757 #define mmSDMA1_RLC4_DUMMY_REG_BASE_IDX                                                                0
758 #define mmSDMA1_RLC4_RB_WPTR_POLL_ADDR_HI                                                              0x02f2
759 #define mmSDMA1_RLC4_RB_WPTR_POLL_ADDR_HI_BASE_IDX                                                     0
760 #define mmSDMA1_RLC4_RB_WPTR_POLL_ADDR_LO                                                              0x02f3
761 #define mmSDMA1_RLC4_RB_WPTR_POLL_ADDR_LO_BASE_IDX                                                     0
762 #define mmSDMA1_RLC4_RB_AQL_CNTL                                                                       0x02f4
763 #define mmSDMA1_RLC4_RB_AQL_CNTL_BASE_IDX                                                              0
764 #define mmSDMA1_RLC4_MINOR_PTR_UPDATE                                                                  0x02f5
765 #define mmSDMA1_RLC4_MINOR_PTR_UPDATE_BASE_IDX                                                         0
766 #define mmSDMA1_RLC4_MIDCMD_DATA0                                                                      0x0300
767 #define mmSDMA1_RLC4_MIDCMD_DATA0_BASE_IDX                                                             0
768 #define mmSDMA1_RLC4_MIDCMD_DATA1                                                                      0x0301
769 #define mmSDMA1_RLC4_MIDCMD_DATA1_BASE_IDX                                                             0
770 #define mmSDMA1_RLC4_MIDCMD_DATA2                                                                      0x0302
771 #define mmSDMA1_RLC4_MIDCMD_DATA2_BASE_IDX                                                             0
772 #define mmSDMA1_RLC4_MIDCMD_DATA3                                                                      0x0303
773 #define mmSDMA1_RLC4_MIDCMD_DATA3_BASE_IDX                                                             0
774 #define mmSDMA1_RLC4_MIDCMD_DATA4                                                                      0x0304
775 #define mmSDMA1_RLC4_MIDCMD_DATA4_BASE_IDX                                                             0
776 #define mmSDMA1_RLC4_MIDCMD_DATA5                                                                      0x0305
777 #define mmSDMA1_RLC4_MIDCMD_DATA5_BASE_IDX                                                             0
778 #define mmSDMA1_RLC4_MIDCMD_DATA6                                                                      0x0306
779 #define mmSDMA1_RLC4_MIDCMD_DATA6_BASE_IDX                                                             0
780 #define mmSDMA1_RLC4_MIDCMD_DATA7                                                                      0x0307
781 #define mmSDMA1_RLC4_MIDCMD_DATA7_BASE_IDX                                                             0
782 #define mmSDMA1_RLC4_MIDCMD_DATA8                                                                      0x0308
783 #define mmSDMA1_RLC4_MIDCMD_DATA8_BASE_IDX                                                             0
784 #define mmSDMA1_RLC4_MIDCMD_CNTL                                                                       0x0309
785 #define mmSDMA1_RLC4_MIDCMD_CNTL_BASE_IDX                                                              0
786 #define mmSDMA1_RLC5_RB_CNTL                                                                           0x0320
787 #define mmSDMA1_RLC5_RB_CNTL_BASE_IDX                                                                  0
788 #define mmSDMA1_RLC5_RB_BASE                                                                           0x0321
789 #define mmSDMA1_RLC5_RB_BASE_BASE_IDX                                                                  0
790 #define mmSDMA1_RLC5_RB_BASE_HI                                                                        0x0322
791 #define mmSDMA1_RLC5_RB_BASE_HI_BASE_IDX                                                               0
792 #define mmSDMA1_RLC5_RB_RPTR                                                                           0x0323
793 #define mmSDMA1_RLC5_RB_RPTR_BASE_IDX                                                                  0
794 #define mmSDMA1_RLC5_RB_RPTR_HI                                                                        0x0324
795 #define mmSDMA1_RLC5_RB_RPTR_HI_BASE_IDX                                                               0
796 #define mmSDMA1_RLC5_RB_WPTR                                                                           0x0325
797 #define mmSDMA1_RLC5_RB_WPTR_BASE_IDX                                                                  0
798 #define mmSDMA1_RLC5_RB_WPTR_HI                                                                        0x0326
799 #define mmSDMA1_RLC5_RB_WPTR_HI_BASE_IDX                                                               0
800 #define mmSDMA1_RLC5_RB_WPTR_POLL_CNTL                                                                 0x0327
801 #define mmSDMA1_RLC5_RB_WPTR_POLL_CNTL_BASE_IDX                                                        0
802 #define mmSDMA1_RLC5_RB_RPTR_ADDR_HI                                                                   0x0328
803 #define mmSDMA1_RLC5_RB_RPTR_ADDR_HI_BASE_IDX                                                          0
804 #define mmSDMA1_RLC5_RB_RPTR_ADDR_LO                                                                   0x0329
805 #define mmSDMA1_RLC5_RB_RPTR_ADDR_LO_BASE_IDX                                                          0
806 #define mmSDMA1_RLC5_IB_CNTL                                                                           0x032a
807 #define mmSDMA1_RLC5_IB_CNTL_BASE_IDX                                                                  0
808 #define mmSDMA1_RLC5_IB_RPTR                                                                           0x032b
809 #define mmSDMA1_RLC5_IB_RPTR_BASE_IDX                                                                  0
810 #define mmSDMA1_RLC5_IB_OFFSET                                                                         0x032c
811 #define mmSDMA1_RLC5_IB_OFFSET_BASE_IDX                                                                0
812 #define mmSDMA1_RLC5_IB_BASE_LO                                                                        0x032d
813 #define mmSDMA1_RLC5_IB_BASE_LO_BASE_IDX                                                               0
814 #define mmSDMA1_RLC5_IB_BASE_HI                                                                        0x032e
815 #define mmSDMA1_RLC5_IB_BASE_HI_BASE_IDX                                                               0
816 #define mmSDMA1_RLC5_IB_SIZE                                                                           0x032f
817 #define mmSDMA1_RLC5_IB_SIZE_BASE_IDX                                                                  0
818 #define mmSDMA1_RLC5_SKIP_CNTL                                                                         0x0330
819 #define mmSDMA1_RLC5_SKIP_CNTL_BASE_IDX                                                                0
820 #define mmSDMA1_RLC5_CONTEXT_STATUS                                                                    0x0331
821 #define mmSDMA1_RLC5_CONTEXT_STATUS_BASE_IDX                                                           0
822 #define mmSDMA1_RLC5_DOORBELL                                                                          0x0332
823 #define mmSDMA1_RLC5_DOORBELL_BASE_IDX                                                                 0
824 #define mmSDMA1_RLC5_STATUS                                                                            0x0348
825 #define mmSDMA1_RLC5_STATUS_BASE_IDX                                                                   0
826 #define mmSDMA1_RLC5_DOORBELL_LOG                                                                      0x0349
827 #define mmSDMA1_RLC5_DOORBELL_LOG_BASE_IDX                                                             0
828 #define mmSDMA1_RLC5_WATERMARK                                                                         0x034a
829 #define mmSDMA1_RLC5_WATERMARK_BASE_IDX                                                                0
830 #define mmSDMA1_RLC5_DOORBELL_OFFSET                                                                   0x034b
831 #define mmSDMA1_RLC5_DOORBELL_OFFSET_BASE_IDX                                                          0
832 #define mmSDMA1_RLC5_CSA_ADDR_LO                                                                       0x034c
833 #define mmSDMA1_RLC5_CSA_ADDR_LO_BASE_IDX                                                              0
834 #define mmSDMA1_RLC5_CSA_ADDR_HI                                                                       0x034d
835 #define mmSDMA1_RLC5_CSA_ADDR_HI_BASE_IDX                                                              0
836 #define mmSDMA1_RLC5_IB_SUB_REMAIN                                                                     0x034f
837 #define mmSDMA1_RLC5_IB_SUB_REMAIN_BASE_IDX                                                            0
838 #define mmSDMA1_RLC5_PREEMPT                                                                           0x0350
839 #define mmSDMA1_RLC5_PREEMPT_BASE_IDX                                                                  0
840 #define mmSDMA1_RLC5_DUMMY_REG                                                                         0x0351
841 #define mmSDMA1_RLC5_DUMMY_REG_BASE_IDX                                                                0
842 #define mmSDMA1_RLC5_RB_WPTR_POLL_ADDR_HI                                                              0x0352
843 #define mmSDMA1_RLC5_RB_WPTR_POLL_ADDR_HI_BASE_IDX                                                     0
844 #define mmSDMA1_RLC5_RB_WPTR_POLL_ADDR_LO                                                              0x0353
845 #define mmSDMA1_RLC5_RB_WPTR_POLL_ADDR_LO_BASE_IDX                                                     0
846 #define mmSDMA1_RLC5_RB_AQL_CNTL                                                                       0x0354
847 #define mmSDMA1_RLC5_RB_AQL_CNTL_BASE_IDX                                                              0
848 #define mmSDMA1_RLC5_MINOR_PTR_UPDATE                                                                  0x0355
849 #define mmSDMA1_RLC5_MINOR_PTR_UPDATE_BASE_IDX                                                         0
850 #define mmSDMA1_RLC5_MIDCMD_DATA0                                                                      0x0360
851 #define mmSDMA1_RLC5_MIDCMD_DATA0_BASE_IDX                                                             0
852 #define mmSDMA1_RLC5_MIDCMD_DATA1                                                                      0x0361
853 #define mmSDMA1_RLC5_MIDCMD_DATA1_BASE_IDX                                                             0
854 #define mmSDMA1_RLC5_MIDCMD_DATA2                                                                      0x0362
855 #define mmSDMA1_RLC5_MIDCMD_DATA2_BASE_IDX                                                             0
856 #define mmSDMA1_RLC5_MIDCMD_DATA3                                                                      0x0363
857 #define mmSDMA1_RLC5_MIDCMD_DATA3_BASE_IDX                                                             0
858 #define mmSDMA1_RLC5_MIDCMD_DATA4                                                                      0x0364
859 #define mmSDMA1_RLC5_MIDCMD_DATA4_BASE_IDX                                                             0
860 #define mmSDMA1_RLC5_MIDCMD_DATA5                                                                      0x0365
861 #define mmSDMA1_RLC5_MIDCMD_DATA5_BASE_IDX                                                             0
862 #define mmSDMA1_RLC5_MIDCMD_DATA6                                                                      0x0366
863 #define mmSDMA1_RLC5_MIDCMD_DATA6_BASE_IDX                                                             0
864 #define mmSDMA1_RLC5_MIDCMD_DATA7                                                                      0x0367
865 #define mmSDMA1_RLC5_MIDCMD_DATA7_BASE_IDX                                                             0
866 #define mmSDMA1_RLC5_MIDCMD_DATA8                                                                      0x0368
867 #define mmSDMA1_RLC5_MIDCMD_DATA8_BASE_IDX                                                             0
868 #define mmSDMA1_RLC5_MIDCMD_CNTL                                                                       0x0369
869 #define mmSDMA1_RLC5_MIDCMD_CNTL_BASE_IDX                                                              0
870 #define mmSDMA1_RLC6_RB_CNTL                                                                           0x0380
871 #define mmSDMA1_RLC6_RB_CNTL_BASE_IDX                                                                  0
872 #define mmSDMA1_RLC6_RB_BASE                                                                           0x0381
873 #define mmSDMA1_RLC6_RB_BASE_BASE_IDX                                                                  0
874 #define mmSDMA1_RLC6_RB_BASE_HI                                                                        0x0382
875 #define mmSDMA1_RLC6_RB_BASE_HI_BASE_IDX                                                               0
876 #define mmSDMA1_RLC6_RB_RPTR                                                                           0x0383
877 #define mmSDMA1_RLC6_RB_RPTR_BASE_IDX                                                                  0
878 #define mmSDMA1_RLC6_RB_RPTR_HI                                                                        0x0384
879 #define mmSDMA1_RLC6_RB_RPTR_HI_BASE_IDX                                                               0
880 #define mmSDMA1_RLC6_RB_WPTR                                                                           0x0385
881 #define mmSDMA1_RLC6_RB_WPTR_BASE_IDX                                                                  0
882 #define mmSDMA1_RLC6_RB_WPTR_HI                                                                        0x0386
883 #define mmSDMA1_RLC6_RB_WPTR_HI_BASE_IDX                                                               0
884 #define mmSDMA1_RLC6_RB_WPTR_POLL_CNTL                                                                 0x0387
885 #define mmSDMA1_RLC6_RB_WPTR_POLL_CNTL_BASE_IDX                                                        0
886 #define mmSDMA1_RLC6_RB_RPTR_ADDR_HI                                                                   0x0388
887 #define mmSDMA1_RLC6_RB_RPTR_ADDR_HI_BASE_IDX                                                          0
888 #define mmSDMA1_RLC6_RB_RPTR_ADDR_LO                                                                   0x0389
889 #define mmSDMA1_RLC6_RB_RPTR_ADDR_LO_BASE_IDX                                                          0
890 #define mmSDMA1_RLC6_IB_CNTL                                                                           0x038a
891 #define mmSDMA1_RLC6_IB_CNTL_BASE_IDX                                                                  0
892 #define mmSDMA1_RLC6_IB_RPTR                                                                           0x038b
893 #define mmSDMA1_RLC6_IB_RPTR_BASE_IDX                                                                  0
894 #define mmSDMA1_RLC6_IB_OFFSET                                                                         0x038c
895 #define mmSDMA1_RLC6_IB_OFFSET_BASE_IDX                                                                0
896 #define mmSDMA1_RLC6_IB_BASE_LO                                                                        0x038d
897 #define mmSDMA1_RLC6_IB_BASE_LO_BASE_IDX                                                               0
898 #define mmSDMA1_RLC6_IB_BASE_HI                                                                        0x038e
899 #define mmSDMA1_RLC6_IB_BASE_HI_BASE_IDX                                                               0
900 #define mmSDMA1_RLC6_IB_SIZE                                                                           0x038f
901 #define mmSDMA1_RLC6_IB_SIZE_BASE_IDX                                                                  0
902 #define mmSDMA1_RLC6_SKIP_CNTL                                                                         0x0390
903 #define mmSDMA1_RLC6_SKIP_CNTL_BASE_IDX                                                                0
904 #define mmSDMA1_RLC6_CONTEXT_STATUS                                                                    0x0391
905 #define mmSDMA1_RLC6_CONTEXT_STATUS_BASE_IDX                                                           0
906 #define mmSDMA1_RLC6_DOORBELL                                                                          0x0392
907 #define mmSDMA1_RLC6_DOORBELL_BASE_IDX                                                                 0
908 #define mmSDMA1_RLC6_STATUS                                                                            0x03a8
909 #define mmSDMA1_RLC6_STATUS_BASE_IDX                                                                   0
910 #define mmSDMA1_RLC6_DOORBELL_LOG                                                                      0x03a9
911 #define mmSDMA1_RLC6_DOORBELL_LOG_BASE_IDX                                                             0
912 #define mmSDMA1_RLC6_WATERMARK                                                                         0x03aa
913 #define mmSDMA1_RLC6_WATERMARK_BASE_IDX                                                                0
914 #define mmSDMA1_RLC6_DOORBELL_OFFSET                                                                   0x03ab
915 #define mmSDMA1_RLC6_DOORBELL_OFFSET_BASE_IDX                                                          0
916 #define mmSDMA1_RLC6_CSA_ADDR_LO                                                                       0x03ac
917 #define mmSDMA1_RLC6_CSA_ADDR_LO_BASE_IDX                                                              0
918 #define mmSDMA1_RLC6_CSA_ADDR_HI                                                                       0x03ad
919 #define mmSDMA1_RLC6_CSA_ADDR_HI_BASE_IDX                                                              0
920 #define mmSDMA1_RLC6_IB_SUB_REMAIN                                                                     0x03af
921 #define mmSDMA1_RLC6_IB_SUB_REMAIN_BASE_IDX                                                            0
922 #define mmSDMA1_RLC6_PREEMPT                                                                           0x03b0
923 #define mmSDMA1_RLC6_PREEMPT_BASE_IDX                                                                  0
924 #define mmSDMA1_RLC6_DUMMY_REG                                                                         0x03b1
925 #define mmSDMA1_RLC6_DUMMY_REG_BASE_IDX                                                                0
926 #define mmSDMA1_RLC6_RB_WPTR_POLL_ADDR_HI                                                              0x03b2
927 #define mmSDMA1_RLC6_RB_WPTR_POLL_ADDR_HI_BASE_IDX                                                     0
928 #define mmSDMA1_RLC6_RB_WPTR_POLL_ADDR_LO                                                              0x03b3
929 #define mmSDMA1_RLC6_RB_WPTR_POLL_ADDR_LO_BASE_IDX                                                     0
930 #define mmSDMA1_RLC6_RB_AQL_CNTL                                                                       0x03b4
931 #define mmSDMA1_RLC6_RB_AQL_CNTL_BASE_IDX                                                              0
932 #define mmSDMA1_RLC6_MINOR_PTR_UPDATE                                                                  0x03b5
933 #define mmSDMA1_RLC6_MINOR_PTR_UPDATE_BASE_IDX                                                         0
934 #define mmSDMA1_RLC6_MIDCMD_DATA0                                                                      0x03c0
935 #define mmSDMA1_RLC6_MIDCMD_DATA0_BASE_IDX                                                             0
936 #define mmSDMA1_RLC6_MIDCMD_DATA1                                                                      0x03c1
937 #define mmSDMA1_RLC6_MIDCMD_DATA1_BASE_IDX                                                             0
938 #define mmSDMA1_RLC6_MIDCMD_DATA2                                                                      0x03c2
939 #define mmSDMA1_RLC6_MIDCMD_DATA2_BASE_IDX                                                             0
940 #define mmSDMA1_RLC6_MIDCMD_DATA3                                                                      0x03c3
941 #define mmSDMA1_RLC6_MIDCMD_DATA3_BASE_IDX                                                             0
942 #define mmSDMA1_RLC6_MIDCMD_DATA4                                                                      0x03c4
943 #define mmSDMA1_RLC6_MIDCMD_DATA4_BASE_IDX                                                             0
944 #define mmSDMA1_RLC6_MIDCMD_DATA5                                                                      0x03c5
945 #define mmSDMA1_RLC6_MIDCMD_DATA5_BASE_IDX                                                             0
946 #define mmSDMA1_RLC6_MIDCMD_DATA6                                                                      0x03c6
947 #define mmSDMA1_RLC6_MIDCMD_DATA6_BASE_IDX                                                             0
948 #define mmSDMA1_RLC6_MIDCMD_DATA7                                                                      0x03c7
949 #define mmSDMA1_RLC6_MIDCMD_DATA7_BASE_IDX                                                             0
950 #define mmSDMA1_RLC6_MIDCMD_DATA8                                                                      0x03c8
951 #define mmSDMA1_RLC6_MIDCMD_DATA8_BASE_IDX                                                             0
952 #define mmSDMA1_RLC6_MIDCMD_CNTL                                                                       0x03c9
953 #define mmSDMA1_RLC6_MIDCMD_CNTL_BASE_IDX                                                              0
954 #define mmSDMA1_RLC7_RB_CNTL                                                                           0x03e0
955 #define mmSDMA1_RLC7_RB_CNTL_BASE_IDX                                                                  0
956 #define mmSDMA1_RLC7_RB_BASE                                                                           0x03e1
957 #define mmSDMA1_RLC7_RB_BASE_BASE_IDX                                                                  0
958 #define mmSDMA1_RLC7_RB_BASE_HI                                                                        0x03e2
959 #define mmSDMA1_RLC7_RB_BASE_HI_BASE_IDX                                                               0
960 #define mmSDMA1_RLC7_RB_RPTR                                                                           0x03e3
961 #define mmSDMA1_RLC7_RB_RPTR_BASE_IDX                                                                  0
962 #define mmSDMA1_RLC7_RB_RPTR_HI                                                                        0x03e4
963 #define mmSDMA1_RLC7_RB_RPTR_HI_BASE_IDX                                                               0
964 #define mmSDMA1_RLC7_RB_WPTR                                                                           0x03e5
965 #define mmSDMA1_RLC7_RB_WPTR_BASE_IDX                                                                  0
966 #define mmSDMA1_RLC7_RB_WPTR_HI                                                                        0x03e6
967 #define mmSDMA1_RLC7_RB_WPTR_HI_BASE_IDX                                                               0
968 #define mmSDMA1_RLC7_RB_WPTR_POLL_CNTL                                                                 0x03e7
969 #define mmSDMA1_RLC7_RB_WPTR_POLL_CNTL_BASE_IDX                                                        0
970 #define mmSDMA1_RLC7_RB_RPTR_ADDR_HI                                                                   0x03e8
971 #define mmSDMA1_RLC7_RB_RPTR_ADDR_HI_BASE_IDX                                                          0
972 #define mmSDMA1_RLC7_RB_RPTR_ADDR_LO                                                                   0x03e9
973 #define mmSDMA1_RLC7_RB_RPTR_ADDR_LO_BASE_IDX                                                          0
974 #define mmSDMA1_RLC7_IB_CNTL                                                                           0x03ea
975 #define mmSDMA1_RLC7_IB_CNTL_BASE_IDX                                                                  0
976 #define mmSDMA1_RLC7_IB_RPTR                                                                           0x03eb
977 #define mmSDMA1_RLC7_IB_RPTR_BASE_IDX                                                                  0
978 #define mmSDMA1_RLC7_IB_OFFSET                                                                         0x03ec
979 #define mmSDMA1_RLC7_IB_OFFSET_BASE_IDX                                                                0
980 #define mmSDMA1_RLC7_IB_BASE_LO                                                                        0x03ed
981 #define mmSDMA1_RLC7_IB_BASE_LO_BASE_IDX                                                               0
982 #define mmSDMA1_RLC7_IB_BASE_HI                                                                        0x03ee
983 #define mmSDMA1_RLC7_IB_BASE_HI_BASE_IDX                                                               0
984 #define mmSDMA1_RLC7_IB_SIZE                                                                           0x03ef
985 #define mmSDMA1_RLC7_IB_SIZE_BASE_IDX                                                                  0
986 #define mmSDMA1_RLC7_SKIP_CNTL                                                                         0x03f0
987 #define mmSDMA1_RLC7_SKIP_CNTL_BASE_IDX                                                                0
988 #define mmSDMA1_RLC7_CONTEXT_STATUS                                                                    0x03f1
989 #define mmSDMA1_RLC7_CONTEXT_STATUS_BASE_IDX                                                           0
990 #define mmSDMA1_RLC7_DOORBELL                                                                          0x03f2
991 #define mmSDMA1_RLC7_DOORBELL_BASE_IDX                                                                 0
992 #define mmSDMA1_RLC7_STATUS                                                                            0x0408
993 #define mmSDMA1_RLC7_STATUS_BASE_IDX                                                                   0
994 #define mmSDMA1_RLC7_DOORBELL_LOG                                                                      0x0409
995 #define mmSDMA1_RLC7_DOORBELL_LOG_BASE_IDX                                                             0
996 #define mmSDMA1_RLC7_WATERMARK                                                                         0x040a
997 #define mmSDMA1_RLC7_WATERMARK_BASE_IDX                                                                0
998 #define mmSDMA1_RLC7_DOORBELL_OFFSET                                                                   0x040b
999 #define mmSDMA1_RLC7_DOORBELL_OFFSET_BASE_IDX                                                          0
1000 #define mmSDMA1_RLC7_CSA_ADDR_LO                                                                       0x040c
1001 #define mmSDMA1_RLC7_CSA_ADDR_LO_BASE_IDX                                                              0
1002 #define mmSDMA1_RLC7_CSA_ADDR_HI                                                                       0x040d
1003 #define mmSDMA1_RLC7_CSA_ADDR_HI_BASE_IDX                                                              0
1004 #define mmSDMA1_RLC7_IB_SUB_REMAIN                                                                     0x040f
1005 #define mmSDMA1_RLC7_IB_SUB_REMAIN_BASE_IDX                                                            0
1006 #define mmSDMA1_RLC7_PREEMPT                                                                           0x0410
1007 #define mmSDMA1_RLC7_PREEMPT_BASE_IDX                                                                  0
1008 #define mmSDMA1_RLC7_DUMMY_REG                                                                         0x0411
1009 #define mmSDMA1_RLC7_DUMMY_REG_BASE_IDX                                                                0
1010 #define mmSDMA1_RLC7_RB_WPTR_POLL_ADDR_HI                                                              0x0412
1011 #define mmSDMA1_RLC7_RB_WPTR_POLL_ADDR_HI_BASE_IDX                                                     0
1012 #define mmSDMA1_RLC7_RB_WPTR_POLL_ADDR_LO                                                              0x0413
1013 #define mmSDMA1_RLC7_RB_WPTR_POLL_ADDR_LO_BASE_IDX                                                     0
1014 #define mmSDMA1_RLC7_RB_AQL_CNTL                                                                       0x0414
1015 #define mmSDMA1_RLC7_RB_AQL_CNTL_BASE_IDX                                                              0
1016 #define mmSDMA1_RLC7_MINOR_PTR_UPDATE                                                                  0x0415
1017 #define mmSDMA1_RLC7_MINOR_PTR_UPDATE_BASE_IDX                                                         0
1018 #define mmSDMA1_RLC7_MIDCMD_DATA0                                                                      0x0420
1019 #define mmSDMA1_RLC7_MIDCMD_DATA0_BASE_IDX                                                             0
1020 #define mmSDMA1_RLC7_MIDCMD_DATA1                                                                      0x0421
1021 #define mmSDMA1_RLC7_MIDCMD_DATA1_BASE_IDX                                                             0
1022 #define mmSDMA1_RLC7_MIDCMD_DATA2                                                                      0x0422
1023 #define mmSDMA1_RLC7_MIDCMD_DATA2_BASE_IDX                                                             0
1024 #define mmSDMA1_RLC7_MIDCMD_DATA3                                                                      0x0423
1025 #define mmSDMA1_RLC7_MIDCMD_DATA3_BASE_IDX                                                             0
1026 #define mmSDMA1_RLC7_MIDCMD_DATA4                                                                      0x0424
1027 #define mmSDMA1_RLC7_MIDCMD_DATA4_BASE_IDX                                                             0
1028 #define mmSDMA1_RLC7_MIDCMD_DATA5                                                                      0x0425
1029 #define mmSDMA1_RLC7_MIDCMD_DATA5_BASE_IDX                                                             0
1030 #define mmSDMA1_RLC7_MIDCMD_DATA6                                                                      0x0426
1031 #define mmSDMA1_RLC7_MIDCMD_DATA6_BASE_IDX                                                             0
1032 #define mmSDMA1_RLC7_MIDCMD_DATA7                                                                      0x0427
1033 #define mmSDMA1_RLC7_MIDCMD_DATA7_BASE_IDX                                                             0
1034 #define mmSDMA1_RLC7_MIDCMD_DATA8                                                                      0x0428
1035 #define mmSDMA1_RLC7_MIDCMD_DATA8_BASE_IDX                                                             0
1036 #define mmSDMA1_RLC7_MIDCMD_CNTL                                                                       0x0429
1037 #define mmSDMA1_RLC7_MIDCMD_CNTL_BASE_IDX                                                              0
1038 
1039 #endif
1040