1*502173acSHawking Zhang /* 2*502173acSHawking Zhang * Copyright 2020 Advanced Micro Devices, Inc. 3*502173acSHawking Zhang * 4*502173acSHawking Zhang * Permission is hereby granted, free of charge, to any person obtaining a 5*502173acSHawking Zhang * copy of this software and associated documentation files (the "Software"), 6*502173acSHawking Zhang * to deal in the Software without restriction, including without limitation 7*502173acSHawking Zhang * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8*502173acSHawking Zhang * and/or sell copies of the Software, and to permit persons to whom the 9*502173acSHawking Zhang * Software is furnished to do so, subject to the following conditions: 10*502173acSHawking Zhang * 11*502173acSHawking Zhang * The above copyright notice and this permission notice shall be included in 12*502173acSHawking Zhang * all copies or substantial portions of the Software. 13*502173acSHawking Zhang * 14*502173acSHawking Zhang * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15*502173acSHawking Zhang * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16*502173acSHawking Zhang * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17*502173acSHawking Zhang * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18*502173acSHawking Zhang * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19*502173acSHawking Zhang * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20*502173acSHawking Zhang * OTHER DEALINGS IN THE SOFTWARE. 21*502173acSHawking Zhang * 22*502173acSHawking Zhang */ 23*502173acSHawking Zhang #ifndef _osssys_4_2_0_OFFSET_HEADER 24*502173acSHawking Zhang #define _osssys_4_2_0_OFFSET_HEADER 25*502173acSHawking Zhang 26*502173acSHawking Zhang 27*502173acSHawking Zhang 28*502173acSHawking Zhang // addressBlock: osssys_osssysdec 29*502173acSHawking Zhang // base address: 0x4280 30*502173acSHawking Zhang #define mmIH_VMID_0_LUT 0x0000 31*502173acSHawking Zhang #define mmIH_VMID_0_LUT_BASE_IDX 0 32*502173acSHawking Zhang #define mmIH_VMID_1_LUT 0x0001 33*502173acSHawking Zhang #define mmIH_VMID_1_LUT_BASE_IDX 0 34*502173acSHawking Zhang #define mmIH_VMID_2_LUT 0x0002 35*502173acSHawking Zhang #define mmIH_VMID_2_LUT_BASE_IDX 0 36*502173acSHawking Zhang #define mmIH_VMID_3_LUT 0x0003 37*502173acSHawking Zhang #define mmIH_VMID_3_LUT_BASE_IDX 0 38*502173acSHawking Zhang #define mmIH_VMID_4_LUT 0x0004 39*502173acSHawking Zhang #define mmIH_VMID_4_LUT_BASE_IDX 0 40*502173acSHawking Zhang #define mmIH_VMID_5_LUT 0x0005 41*502173acSHawking Zhang #define mmIH_VMID_5_LUT_BASE_IDX 0 42*502173acSHawking Zhang #define mmIH_VMID_6_LUT 0x0006 43*502173acSHawking Zhang #define mmIH_VMID_6_LUT_BASE_IDX 0 44*502173acSHawking Zhang #define mmIH_VMID_7_LUT 0x0007 45*502173acSHawking Zhang #define mmIH_VMID_7_LUT_BASE_IDX 0 46*502173acSHawking Zhang #define mmIH_VMID_8_LUT 0x0008 47*502173acSHawking Zhang #define mmIH_VMID_8_LUT_BASE_IDX 0 48*502173acSHawking Zhang #define mmIH_VMID_9_LUT 0x0009 49*502173acSHawking Zhang #define mmIH_VMID_9_LUT_BASE_IDX 0 50*502173acSHawking Zhang #define mmIH_VMID_10_LUT 0x000a 51*502173acSHawking Zhang #define mmIH_VMID_10_LUT_BASE_IDX 0 52*502173acSHawking Zhang #define mmIH_VMID_11_LUT 0x000b 53*502173acSHawking Zhang #define mmIH_VMID_11_LUT_BASE_IDX 0 54*502173acSHawking Zhang #define mmIH_VMID_12_LUT 0x000c 55*502173acSHawking Zhang #define mmIH_VMID_12_LUT_BASE_IDX 0 56*502173acSHawking Zhang #define mmIH_VMID_13_LUT 0x000d 57*502173acSHawking Zhang #define mmIH_VMID_13_LUT_BASE_IDX 0 58*502173acSHawking Zhang #define mmIH_VMID_14_LUT 0x000e 59*502173acSHawking Zhang #define mmIH_VMID_14_LUT_BASE_IDX 0 60*502173acSHawking Zhang #define mmIH_VMID_15_LUT 0x000f 61*502173acSHawking Zhang #define mmIH_VMID_15_LUT_BASE_IDX 0 62*502173acSHawking Zhang #define mmIH_VMID_0_LUT_MM 0x0010 63*502173acSHawking Zhang #define mmIH_VMID_0_LUT_MM_BASE_IDX 0 64*502173acSHawking Zhang #define mmIH_VMID_1_LUT_MM 0x0011 65*502173acSHawking Zhang #define mmIH_VMID_1_LUT_MM_BASE_IDX 0 66*502173acSHawking Zhang #define mmIH_VMID_2_LUT_MM 0x0012 67*502173acSHawking Zhang #define mmIH_VMID_2_LUT_MM_BASE_IDX 0 68*502173acSHawking Zhang #define mmIH_VMID_3_LUT_MM 0x0013 69*502173acSHawking Zhang #define mmIH_VMID_3_LUT_MM_BASE_IDX 0 70*502173acSHawking Zhang #define mmIH_VMID_4_LUT_MM 0x0014 71*502173acSHawking Zhang #define mmIH_VMID_4_LUT_MM_BASE_IDX 0 72*502173acSHawking Zhang #define mmIH_VMID_5_LUT_MM 0x0015 73*502173acSHawking Zhang #define mmIH_VMID_5_LUT_MM_BASE_IDX 0 74*502173acSHawking Zhang #define mmIH_VMID_6_LUT_MM 0x0016 75*502173acSHawking Zhang #define mmIH_VMID_6_LUT_MM_BASE_IDX 0 76*502173acSHawking Zhang #define mmIH_VMID_7_LUT_MM 0x0017 77*502173acSHawking Zhang #define mmIH_VMID_7_LUT_MM_BASE_IDX 0 78*502173acSHawking Zhang #define mmIH_VMID_8_LUT_MM 0x0018 79*502173acSHawking Zhang #define mmIH_VMID_8_LUT_MM_BASE_IDX 0 80*502173acSHawking Zhang #define mmIH_VMID_9_LUT_MM 0x0019 81*502173acSHawking Zhang #define mmIH_VMID_9_LUT_MM_BASE_IDX 0 82*502173acSHawking Zhang #define mmIH_VMID_10_LUT_MM 0x001a 83*502173acSHawking Zhang #define mmIH_VMID_10_LUT_MM_BASE_IDX 0 84*502173acSHawking Zhang #define mmIH_VMID_11_LUT_MM 0x001b 85*502173acSHawking Zhang #define mmIH_VMID_11_LUT_MM_BASE_IDX 0 86*502173acSHawking Zhang #define mmIH_VMID_12_LUT_MM 0x001c 87*502173acSHawking Zhang #define mmIH_VMID_12_LUT_MM_BASE_IDX 0 88*502173acSHawking Zhang #define mmIH_VMID_13_LUT_MM 0x001d 89*502173acSHawking Zhang #define mmIH_VMID_13_LUT_MM_BASE_IDX 0 90*502173acSHawking Zhang #define mmIH_VMID_14_LUT_MM 0x001e 91*502173acSHawking Zhang #define mmIH_VMID_14_LUT_MM_BASE_IDX 0 92*502173acSHawking Zhang #define mmIH_VMID_15_LUT_MM 0x001f 93*502173acSHawking Zhang #define mmIH_VMID_15_LUT_MM_BASE_IDX 0 94*502173acSHawking Zhang #define mmIH_COOKIE_0 0x0020 95*502173acSHawking Zhang #define mmIH_COOKIE_0_BASE_IDX 0 96*502173acSHawking Zhang #define mmIH_COOKIE_1 0x0021 97*502173acSHawking Zhang #define mmIH_COOKIE_1_BASE_IDX 0 98*502173acSHawking Zhang #define mmIH_COOKIE_2 0x0022 99*502173acSHawking Zhang #define mmIH_COOKIE_2_BASE_IDX 0 100*502173acSHawking Zhang #define mmIH_COOKIE_3 0x0023 101*502173acSHawking Zhang #define mmIH_COOKIE_3_BASE_IDX 0 102*502173acSHawking Zhang #define mmIH_COOKIE_4 0x0024 103*502173acSHawking Zhang #define mmIH_COOKIE_4_BASE_IDX 0 104*502173acSHawking Zhang #define mmIH_COOKIE_5 0x0025 105*502173acSHawking Zhang #define mmIH_COOKIE_5_BASE_IDX 0 106*502173acSHawking Zhang #define mmIH_COOKIE_6 0x0026 107*502173acSHawking Zhang #define mmIH_COOKIE_6_BASE_IDX 0 108*502173acSHawking Zhang #define mmIH_COOKIE_7 0x0027 109*502173acSHawking Zhang #define mmIH_COOKIE_7_BASE_IDX 0 110*502173acSHawking Zhang #define mmIH_REGISTER_LAST_PART0 0x003f 111*502173acSHawking Zhang #define mmIH_REGISTER_LAST_PART0_BASE_IDX 0 112*502173acSHawking Zhang #define mmSEM_REQ_INPUT_0 0x0040 113*502173acSHawking Zhang #define mmSEM_REQ_INPUT_0_BASE_IDX 0 114*502173acSHawking Zhang #define mmSEM_REQ_INPUT_1 0x0041 115*502173acSHawking Zhang #define mmSEM_REQ_INPUT_1_BASE_IDX 0 116*502173acSHawking Zhang #define mmSEM_REQ_INPUT_2 0x0042 117*502173acSHawking Zhang #define mmSEM_REQ_INPUT_2_BASE_IDX 0 118*502173acSHawking Zhang #define mmSEM_REQ_INPUT_3 0x0043 119*502173acSHawking Zhang #define mmSEM_REQ_INPUT_3_BASE_IDX 0 120*502173acSHawking Zhang #define mmSEM_REGISTER_LAST_PART0 0x007f 121*502173acSHawking Zhang #define mmSEM_REGISTER_LAST_PART0_BASE_IDX 0 122*502173acSHawking Zhang #define mmIH_RB_CNTL 0x0080 123*502173acSHawking Zhang #define mmIH_RB_CNTL_BASE_IDX 0 124*502173acSHawking Zhang #define mmIH_RB_BASE 0x0081 125*502173acSHawking Zhang #define mmIH_RB_BASE_BASE_IDX 0 126*502173acSHawking Zhang #define mmIH_RB_BASE_HI 0x0082 127*502173acSHawking Zhang #define mmIH_RB_BASE_HI_BASE_IDX 0 128*502173acSHawking Zhang #define mmIH_RB_RPTR 0x0083 129*502173acSHawking Zhang #define mmIH_RB_RPTR_BASE_IDX 0 130*502173acSHawking Zhang #define mmIH_RB_WPTR 0x0084 131*502173acSHawking Zhang #define mmIH_RB_WPTR_BASE_IDX 0 132*502173acSHawking Zhang #define mmIH_RB_WPTR_ADDR_HI 0x0085 133*502173acSHawking Zhang #define mmIH_RB_WPTR_ADDR_HI_BASE_IDX 0 134*502173acSHawking Zhang #define mmIH_RB_WPTR_ADDR_LO 0x0086 135*502173acSHawking Zhang #define mmIH_RB_WPTR_ADDR_LO_BASE_IDX 0 136*502173acSHawking Zhang #define mmIH_DOORBELL_RPTR 0x0087 137*502173acSHawking Zhang #define mmIH_DOORBELL_RPTR_BASE_IDX 0 138*502173acSHawking Zhang #define mmIH_RB_CNTL_RING1 0x008c 139*502173acSHawking Zhang #define mmIH_RB_CNTL_RING1_BASE_IDX 0 140*502173acSHawking Zhang #define mmIH_RB_BASE_RING1 0x008d 141*502173acSHawking Zhang #define mmIH_RB_BASE_RING1_BASE_IDX 0 142*502173acSHawking Zhang #define mmIH_RB_BASE_HI_RING1 0x008e 143*502173acSHawking Zhang #define mmIH_RB_BASE_HI_RING1_BASE_IDX 0 144*502173acSHawking Zhang #define mmIH_RB_RPTR_RING1 0x008f 145*502173acSHawking Zhang #define mmIH_RB_RPTR_RING1_BASE_IDX 0 146*502173acSHawking Zhang #define mmIH_RB_WPTR_RING1 0x0090 147*502173acSHawking Zhang #define mmIH_RB_WPTR_RING1_BASE_IDX 0 148*502173acSHawking Zhang #define mmIH_DOORBELL_RPTR_RING1 0x0093 149*502173acSHawking Zhang #define mmIH_DOORBELL_RPTR_RING1_BASE_IDX 0 150*502173acSHawking Zhang #define mmIH_RB_CNTL_RING2 0x0098 151*502173acSHawking Zhang #define mmIH_RB_CNTL_RING2_BASE_IDX 0 152*502173acSHawking Zhang #define mmIH_RB_BASE_RING2 0x0099 153*502173acSHawking Zhang #define mmIH_RB_BASE_RING2_BASE_IDX 0 154*502173acSHawking Zhang #define mmIH_RB_BASE_HI_RING2 0x009a 155*502173acSHawking Zhang #define mmIH_RB_BASE_HI_RING2_BASE_IDX 0 156*502173acSHawking Zhang #define mmIH_RB_RPTR_RING2 0x009b 157*502173acSHawking Zhang #define mmIH_RB_RPTR_RING2_BASE_IDX 0 158*502173acSHawking Zhang #define mmIH_RB_WPTR_RING2 0x009c 159*502173acSHawking Zhang #define mmIH_RB_WPTR_RING2_BASE_IDX 0 160*502173acSHawking Zhang #define mmIH_DOORBELL_RPTR_RING2 0x009f 161*502173acSHawking Zhang #define mmIH_DOORBELL_RPTR_RING2_BASE_IDX 0 162*502173acSHawking Zhang #define mmIH_VERSION 0x00a5 163*502173acSHawking Zhang #define mmIH_VERSION_BASE_IDX 0 164*502173acSHawking Zhang #define mmIH_CNTL 0x00c0 165*502173acSHawking Zhang #define mmIH_CNTL_BASE_IDX 0 166*502173acSHawking Zhang #define mmIH_CNTL2 0x00c1 167*502173acSHawking Zhang #define mmIH_CNTL2_BASE_IDX 0 168*502173acSHawking Zhang #define mmIH_STATUS 0x00c2 169*502173acSHawking Zhang #define mmIH_STATUS_BASE_IDX 0 170*502173acSHawking Zhang #define mmIH_PERFMON_CNTL 0x00c3 171*502173acSHawking Zhang #define mmIH_PERFMON_CNTL_BASE_IDX 0 172*502173acSHawking Zhang #define mmIH_PERFCOUNTER0_RESULT 0x00c4 173*502173acSHawking Zhang #define mmIH_PERFCOUNTER0_RESULT_BASE_IDX 0 174*502173acSHawking Zhang #define mmIH_PERFCOUNTER1_RESULT 0x00c5 175*502173acSHawking Zhang #define mmIH_PERFCOUNTER1_RESULT_BASE_IDX 0 176*502173acSHawking Zhang #define mmIH_DSM_MATCH_VALUE_BIT_31_0 0x00c7 177*502173acSHawking Zhang #define mmIH_DSM_MATCH_VALUE_BIT_31_0_BASE_IDX 0 178*502173acSHawking Zhang #define mmIH_DSM_MATCH_VALUE_BIT_63_32 0x00c8 179*502173acSHawking Zhang #define mmIH_DSM_MATCH_VALUE_BIT_63_32_BASE_IDX 0 180*502173acSHawking Zhang #define mmIH_DSM_MATCH_VALUE_BIT_95_64 0x00c9 181*502173acSHawking Zhang #define mmIH_DSM_MATCH_VALUE_BIT_95_64_BASE_IDX 0 182*502173acSHawking Zhang #define mmIH_DSM_MATCH_FIELD_CONTROL 0x00ca 183*502173acSHawking Zhang #define mmIH_DSM_MATCH_FIELD_CONTROL_BASE_IDX 0 184*502173acSHawking Zhang #define mmIH_DSM_MATCH_DATA_CONTROL 0x00cb 185*502173acSHawking Zhang #define mmIH_DSM_MATCH_DATA_CONTROL_BASE_IDX 0 186*502173acSHawking Zhang #define mmIH_DSM_MATCH_FCN_ID 0x00cc 187*502173acSHawking Zhang #define mmIH_DSM_MATCH_FCN_ID_BASE_IDX 0 188*502173acSHawking Zhang #define mmIH_LIMIT_INT_RATE_CNTL 0x00cd 189*502173acSHawking Zhang #define mmIH_LIMIT_INT_RATE_CNTL_BASE_IDX 0 190*502173acSHawking Zhang #define mmIH_VF_RB_STATUS 0x00ce 191*502173acSHawking Zhang #define mmIH_VF_RB_STATUS_BASE_IDX 0 192*502173acSHawking Zhang #define mmIH_VF_RB_STATUS2 0x00cf 193*502173acSHawking Zhang #define mmIH_VF_RB_STATUS2_BASE_IDX 0 194*502173acSHawking Zhang #define mmIH_VF_RB1_STATUS 0x00d0 195*502173acSHawking Zhang #define mmIH_VF_RB1_STATUS_BASE_IDX 0 196*502173acSHawking Zhang #define mmIH_VF_RB1_STATUS2 0x00d1 197*502173acSHawking Zhang #define mmIH_VF_RB1_STATUS2_BASE_IDX 0 198*502173acSHawking Zhang #define mmIH_VF_RB2_STATUS 0x00d2 199*502173acSHawking Zhang #define mmIH_VF_RB2_STATUS_BASE_IDX 0 200*502173acSHawking Zhang #define mmIH_VF_RB2_STATUS2 0x00d3 201*502173acSHawking Zhang #define mmIH_VF_RB2_STATUS2_BASE_IDX 0 202*502173acSHawking Zhang #define mmIH_INT_FLOOD_CNTL 0x00d5 203*502173acSHawking Zhang #define mmIH_INT_FLOOD_CNTL_BASE_IDX 0 204*502173acSHawking Zhang #define mmIH_RB0_INT_FLOOD_STATUS 0x00d6 205*502173acSHawking Zhang #define mmIH_RB0_INT_FLOOD_STATUS_BASE_IDX 0 206*502173acSHawking Zhang #define mmIH_RB1_INT_FLOOD_STATUS 0x00d7 207*502173acSHawking Zhang #define mmIH_RB1_INT_FLOOD_STATUS_BASE_IDX 0 208*502173acSHawking Zhang #define mmIH_RB2_INT_FLOOD_STATUS 0x00d8 209*502173acSHawking Zhang #define mmIH_RB2_INT_FLOOD_STATUS_BASE_IDX 0 210*502173acSHawking Zhang #define mmIH_INT_FLOOD_STATUS 0x00d9 211*502173acSHawking Zhang #define mmIH_INT_FLOOD_STATUS_BASE_IDX 0 212*502173acSHawking Zhang #define mmIH_STORM_CLIENT_LIST_CNTL 0x00da 213*502173acSHawking Zhang #define mmIH_STORM_CLIENT_LIST_CNTL_BASE_IDX 0 214*502173acSHawking Zhang #define mmIH_CLK_CTRL 0x00db 215*502173acSHawking Zhang #define mmIH_CLK_CTRL_BASE_IDX 0 216*502173acSHawking Zhang #define mmIH_INT_FLAGS 0x00dc 217*502173acSHawking Zhang #define mmIH_INT_FLAGS_BASE_IDX 0 218*502173acSHawking Zhang #define mmIH_LAST_INT_INFO0 0x00dd 219*502173acSHawking Zhang #define mmIH_LAST_INT_INFO0_BASE_IDX 0 220*502173acSHawking Zhang #define mmIH_LAST_INT_INFO1 0x00de 221*502173acSHawking Zhang #define mmIH_LAST_INT_INFO1_BASE_IDX 0 222*502173acSHawking Zhang #define mmIH_LAST_INT_INFO2 0x00df 223*502173acSHawking Zhang #define mmIH_LAST_INT_INFO2_BASE_IDX 0 224*502173acSHawking Zhang #define mmIH_SCRATCH 0x00e0 225*502173acSHawking Zhang #define mmIH_SCRATCH_BASE_IDX 0 226*502173acSHawking Zhang #define mmIH_CLIENT_CREDIT_ERROR 0x00e1 227*502173acSHawking Zhang #define mmIH_CLIENT_CREDIT_ERROR_BASE_IDX 0 228*502173acSHawking Zhang #define mmIH_GPU_IOV_VIOLATION_LOG 0x00e2 229*502173acSHawking Zhang #define mmIH_GPU_IOV_VIOLATION_LOG_BASE_IDX 0 230*502173acSHawking Zhang #define mmIH_COOKIE_REC_VIOLATION_LOG 0x00e3 231*502173acSHawking Zhang #define mmIH_COOKIE_REC_VIOLATION_LOG_BASE_IDX 0 232*502173acSHawking Zhang #define mmIH_CREDIT_STATUS 0x00e4 233*502173acSHawking Zhang #define mmIH_CREDIT_STATUS_BASE_IDX 0 234*502173acSHawking Zhang #define mmIH_MMHUB_ERROR 0x00e5 235*502173acSHawking Zhang #define mmIH_MMHUB_ERROR_BASE_IDX 0 236*502173acSHawking Zhang #define mmIH_MEM_POWER_CTRL 0x00e8 237*502173acSHawking Zhang #define mmIH_MEM_POWER_CTRL_BASE_IDX 0 238*502173acSHawking Zhang #define mmIH_REGISTER_LAST_PART2 0x00ff 239*502173acSHawking Zhang #define mmIH_REGISTER_LAST_PART2_BASE_IDX 0 240*502173acSHawking Zhang #define mmSEM_CLK_CTRL 0x0100 241*502173acSHawking Zhang #define mmSEM_CLK_CTRL_BASE_IDX 0 242*502173acSHawking Zhang #define mmSEM_UTC_CREDIT 0x0101 243*502173acSHawking Zhang #define mmSEM_UTC_CREDIT_BASE_IDX 0 244*502173acSHawking Zhang #define mmSEM_UTC_CONFIG 0x0102 245*502173acSHawking Zhang #define mmSEM_UTC_CONFIG_BASE_IDX 0 246*502173acSHawking Zhang #define mmSEM_UTCL2_TRAN_EN_LUT 0x0103 247*502173acSHawking Zhang #define mmSEM_UTCL2_TRAN_EN_LUT_BASE_IDX 0 248*502173acSHawking Zhang #define mmSEM_MCIF_CONFIG 0x0104 249*502173acSHawking Zhang #define mmSEM_MCIF_CONFIG_BASE_IDX 0 250*502173acSHawking Zhang #define mmSEM_PERFMON_CNTL 0x0105 251*502173acSHawking Zhang #define mmSEM_PERFMON_CNTL_BASE_IDX 0 252*502173acSHawking Zhang #define mmSEM_PERFCOUNTER0_RESULT 0x0106 253*502173acSHawking Zhang #define mmSEM_PERFCOUNTER0_RESULT_BASE_IDX 0 254*502173acSHawking Zhang #define mmSEM_PERFCOUNTER1_RESULT 0x0107 255*502173acSHawking Zhang #define mmSEM_PERFCOUNTER1_RESULT_BASE_IDX 0 256*502173acSHawking Zhang #define mmSEM_STATUS 0x0108 257*502173acSHawking Zhang #define mmSEM_STATUS_BASE_IDX 0 258*502173acSHawking Zhang #define mmSEM_MAILBOX_CLIENTCONFIG 0x0109 259*502173acSHawking Zhang #define mmSEM_MAILBOX_CLIENTCONFIG_BASE_IDX 0 260*502173acSHawking Zhang #define mmSEM_MAILBOX 0x010a 261*502173acSHawking Zhang #define mmSEM_MAILBOX_BASE_IDX 0 262*502173acSHawking Zhang #define mmSEM_MAILBOX_CONTROL 0x010b 263*502173acSHawking Zhang #define mmSEM_MAILBOX_CONTROL_BASE_IDX 0 264*502173acSHawking Zhang #define mmSEM_CHICKEN_BITS 0x010c 265*502173acSHawking Zhang #define mmSEM_CHICKEN_BITS_BASE_IDX 0 266*502173acSHawking Zhang #define mmSEM_MAILBOX_CLIENTCONFIG_EXTRA 0x010d 267*502173acSHawking Zhang #define mmSEM_MAILBOX_CLIENTCONFIG_EXTRA_BASE_IDX 0 268*502173acSHawking Zhang #define mmSEM_GPU_IOV_VIOLATION_LOG 0x010e 269*502173acSHawking Zhang #define mmSEM_GPU_IOV_VIOLATION_LOG_BASE_IDX 0 270*502173acSHawking Zhang #define mmSEM_OUTSTANDING_THRESHOLD 0x010f 271*502173acSHawking Zhang #define mmSEM_OUTSTANDING_THRESHOLD_BASE_IDX 0 272*502173acSHawking Zhang #define mmSEM_MEM_POWER_CTRL 0x0110 273*502173acSHawking Zhang #define mmSEM_MEM_POWER_CTRL_BASE_IDX 0 274*502173acSHawking Zhang #define mmSEM_REGISTER_LAST_PART2 0x017f 275*502173acSHawking Zhang #define mmSEM_REGISTER_LAST_PART2_BASE_IDX 0 276*502173acSHawking Zhang #define mmIH_ACTIVE_FCN_ID 0x0180 277*502173acSHawking Zhang #define mmIH_ACTIVE_FCN_ID_BASE_IDX 0 278*502173acSHawking Zhang #define mmIH_VIRT_RESET_REQ 0x0181 279*502173acSHawking Zhang #define mmIH_VIRT_RESET_REQ_BASE_IDX 0 280*502173acSHawking Zhang #define mmIH_CLIENT_CFG 0x0184 281*502173acSHawking Zhang #define mmIH_CLIENT_CFG_BASE_IDX 0 282*502173acSHawking Zhang #define mmIH_CLIENT_CFG_INDEX 0x0188 283*502173acSHawking Zhang #define mmIH_CLIENT_CFG_INDEX_BASE_IDX 0 284*502173acSHawking Zhang #define mmIH_CLIENT_CFG_DATA 0x0189 285*502173acSHawking Zhang #define mmIH_CLIENT_CFG_DATA_BASE_IDX 0 286*502173acSHawking Zhang #define mmIH_CID_REMAP_INDEX 0x018a 287*502173acSHawking Zhang #define mmIH_CID_REMAP_INDEX_BASE_IDX 0 288*502173acSHawking Zhang #define mmIH_CID_REMAP_DATA 0x018b 289*502173acSHawking Zhang #define mmIH_CID_REMAP_DATA_BASE_IDX 0 290*502173acSHawking Zhang #define mmIH_CHICKEN 0x018c 291*502173acSHawking Zhang #define mmIH_CHICKEN_BASE_IDX 0 292*502173acSHawking Zhang #define mmIH_MMHUB_CNTL 0x018d 293*502173acSHawking Zhang #define mmIH_MMHUB_CNTL_BASE_IDX 0 294*502173acSHawking Zhang #define mmIH_INT_DROP_CNTL 0x018e 295*502173acSHawking Zhang #define mmIH_INT_DROP_CNTL_BASE_IDX 0 296*502173acSHawking Zhang #define mmIH_INT_DROP_MATCH_VALUE0 0x018f 297*502173acSHawking Zhang #define mmIH_INT_DROP_MATCH_VALUE0_BASE_IDX 0 298*502173acSHawking Zhang #define mmIH_INT_DROP_MATCH_VALUE1 0x0190 299*502173acSHawking Zhang #define mmIH_INT_DROP_MATCH_VALUE1_BASE_IDX 0 300*502173acSHawking Zhang #define mmIH_INT_DROP_MATCH_MASK0 0x0191 301*502173acSHawking Zhang #define mmIH_INT_DROP_MATCH_MASK0_BASE_IDX 0 302*502173acSHawking Zhang #define mmIH_INT_DROP_MATCH_MASK1 0x0192 303*502173acSHawking Zhang #define mmIH_INT_DROP_MATCH_MASK1_BASE_IDX 0 304*502173acSHawking Zhang #define mmIH_REGISTER_LAST_PART1 0x019f 305*502173acSHawking Zhang #define mmIH_REGISTER_LAST_PART1_BASE_IDX 0 306*502173acSHawking Zhang #define mmSEM_ACTIVE_FCN_ID 0x01a0 307*502173acSHawking Zhang #define mmSEM_ACTIVE_FCN_ID_BASE_IDX 0 308*502173acSHawking Zhang #define mmSEM_VIRT_RESET_REQ 0x01a1 309*502173acSHawking Zhang #define mmSEM_VIRT_RESET_REQ_BASE_IDX 0 310*502173acSHawking Zhang #define mmSEM_RESP_SDMA0 0x01a4 311*502173acSHawking Zhang #define mmSEM_RESP_SDMA0_BASE_IDX 0 312*502173acSHawking Zhang #define mmSEM_RESP_SDMA1 0x01a5 313*502173acSHawking Zhang #define mmSEM_RESP_SDMA1_BASE_IDX 0 314*502173acSHawking Zhang #define mmSEM_RESP_UVD 0x01a6 315*502173acSHawking Zhang #define mmSEM_RESP_UVD_BASE_IDX 0 316*502173acSHawking Zhang #define mmSEM_RESP_VCE_0 0x01a7 317*502173acSHawking Zhang #define mmSEM_RESP_VCE_0_BASE_IDX 0 318*502173acSHawking Zhang #define mmSEM_RESP_ACP 0x01a8 319*502173acSHawking Zhang #define mmSEM_RESP_ACP_BASE_IDX 0 320*502173acSHawking Zhang #define mmSEM_RESP_ISP 0x01a9 321*502173acSHawking Zhang #define mmSEM_RESP_ISP_BASE_IDX 0 322*502173acSHawking Zhang #define mmSEM_RESP_VCE_1 0x01aa 323*502173acSHawking Zhang #define mmSEM_RESP_VCE_1_BASE_IDX 0 324*502173acSHawking Zhang #define mmSEM_RESP_VP8 0x01ab 325*502173acSHawking Zhang #define mmSEM_RESP_VP8_BASE_IDX 0 326*502173acSHawking Zhang #define mmSEM_RESP_GC 0x01ac 327*502173acSHawking Zhang #define mmSEM_RESP_GC_BASE_IDX 0 328*502173acSHawking Zhang #define mmSEM_RESP_UVD_1 0x01ad 329*502173acSHawking Zhang #define mmSEM_RESP_UVD_1_BASE_IDX 0 330*502173acSHawking Zhang #define mmSEM_CID_REMAP_INDEX 0x01b0 331*502173acSHawking Zhang #define mmSEM_CID_REMAP_INDEX_BASE_IDX 0 332*502173acSHawking Zhang #define mmSEM_CID_REMAP_DATA 0x01b1 333*502173acSHawking Zhang #define mmSEM_CID_REMAP_DATA_BASE_IDX 0 334*502173acSHawking Zhang #define mmSEM_ATOMIC_OP_LUT 0x01b2 335*502173acSHawking Zhang #define mmSEM_ATOMIC_OP_LUT_BASE_IDX 0 336*502173acSHawking Zhang #define mmSEM_EDC_CONFIG 0x01b3 337*502173acSHawking Zhang #define mmSEM_EDC_CONFIG_BASE_IDX 0 338*502173acSHawking Zhang #define mmSEM_CHICKEN_BITS2 0x01b4 339*502173acSHawking Zhang #define mmSEM_CHICKEN_BITS2_BASE_IDX 0 340*502173acSHawking Zhang #define mmSEM_MMHUB_CNTL 0x01b5 341*502173acSHawking Zhang #define mmSEM_MMHUB_CNTL_BASE_IDX 0 342*502173acSHawking Zhang #define mmSEM_REGISTER_LAST_PART1 0x01bf 343*502173acSHawking Zhang #define mmSEM_REGISTER_LAST_PART1_BASE_IDX 0 344*502173acSHawking Zhang 345*502173acSHawking Zhang #endif 346