1a0bb79e2SKent Russell /* 2a0bb79e2SKent Russell * Copyright (C) 2019 Advanced Micro Devices, Inc. 3a0bb79e2SKent Russell * 4a0bb79e2SKent Russell * Permission is hereby granted, free of charge, to any person obtaining a 5a0bb79e2SKent Russell * copy of this software and associated documentation files (the "Software"), 6a0bb79e2SKent Russell * to deal in the Software without restriction, including without limitation 7a0bb79e2SKent Russell * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8a0bb79e2SKent Russell * and/or sell copies of the Software, and to permit persons to whom the 9a0bb79e2SKent Russell * Software is furnished to do so, subject to the following conditions: 10a0bb79e2SKent Russell * 11a0bb79e2SKent Russell * The above copyright notice and this permission notice shall be included 12a0bb79e2SKent Russell * in all copies or substantial portions of the Software. 13a0bb79e2SKent Russell * 14a0bb79e2SKent Russell * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 15a0bb79e2SKent Russell * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16a0bb79e2SKent Russell * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17a0bb79e2SKent Russell * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN 18a0bb79e2SKent Russell * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 19a0bb79e2SKent Russell * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 20a0bb79e2SKent Russell */ 21a0bb79e2SKent Russell 22a0bb79e2SKent Russell #ifndef _nbio_6_1_SMN_HEADER 23a0bb79e2SKent Russell #define _nbio_6_1_SMN_HEADER 24a0bb79e2SKent Russell 25a0bb79e2SKent Russell 26a0bb79e2SKent Russell #define smnCPM_CONTROL 0x11180460 27a0bb79e2SKent Russell #define smnPCIE_CNTL2 0x11180070 28a0bb79e2SKent Russell #define smnPCIE_CONFIG_CNTL 0x11180044 29a0bb79e2SKent Russell #define smnPCIE_CI_CNTL 0x11180080 30a0bb79e2SKent Russell 31a0bb79e2SKent Russell 32a0bb79e2SKent Russell #define smnPCIE_PERF_COUNT_CNTL 0x11180200 33a0bb79e2SKent Russell #define smnPCIE_PERF_CNTL_TXCLK 0x11180204 34a0bb79e2SKent Russell #define smnPCIE_PERF_COUNT0_TXCLK 0x11180208 35a0bb79e2SKent Russell #define smnPCIE_PERF_COUNT1_TXCLK 0x1118020c 36a0bb79e2SKent Russell #define smnPCIE_PERF_CNTL_MST_R_CLK 0x11180210 37a0bb79e2SKent Russell #define smnPCIE_PERF_COUNT0_MST_R_CLK 0x11180214 38a0bb79e2SKent Russell #define smnPCIE_PERF_COUNT1_MST_R_CLK 0x11180218 39a0bb79e2SKent Russell #define smnPCIE_PERF_CNTL_MST_C_CLK 0x1118021c 40a0bb79e2SKent Russell #define smnPCIE_PERF_COUNT0_MST_C_CLK 0x11180220 41a0bb79e2SKent Russell #define smnPCIE_PERF_COUNT1_MST_C_CLK 0x11180224 42a0bb79e2SKent Russell #define smnPCIE_PERF_CNTL_SLV_R_CLK 0x11180228 43a0bb79e2SKent Russell #define smnPCIE_PERF_COUNT0_SLV_R_CLK 0x1118022c 44a0bb79e2SKent Russell #define smnPCIE_PERF_COUNT1_SLV_R_CLK 0x11180230 45a0bb79e2SKent Russell #define smnPCIE_PERF_CNTL_SLV_S_C_CLK 0x11180234 46a0bb79e2SKent Russell #define smnPCIE_PERF_COUNT0_SLV_S_C_CLK 0x11180238 47a0bb79e2SKent Russell #define smnPCIE_PERF_COUNT1_SLV_S_C_CLK 0x1118023c 48a0bb79e2SKent Russell #define smnPCIE_PERF_CNTL_SLV_NS_C_CLK 0x11180240 49a0bb79e2SKent Russell #define smnPCIE_PERF_COUNT0_SLV_NS_C_CLK 0x11180244 50a0bb79e2SKent Russell #define smnPCIE_PERF_COUNT1_SLV_NS_C_CLK 0x11180248 51a0bb79e2SKent Russell #define smnPCIE_PERF_CNTL_EVENT0_PORT_SEL 0x1118024c 52a0bb79e2SKent Russell #define smnPCIE_PERF_CNTL_EVENT1_PORT_SEL 0x11180250 53a0bb79e2SKent Russell #define smnPCIE_PERF_CNTL_TXCLK2 0x11180254 54a0bb79e2SKent Russell #define smnPCIE_PERF_COUNT0_TXCLK2 0x11180258 55a0bb79e2SKent Russell #define smnPCIE_PERF_COUNT1_TXCLK2 0x1118025c 56a0bb79e2SKent Russell 57673b366bSKent Russell #define smnPCIE_RX_NUM_NAK 0x11180038 58673b366bSKent Russell #define smnPCIE_RX_NUM_NAK_GENERATED 0x1118003c 59673b366bSKent Russell 60a0bb79e2SKent Russell #endif // _nbio_6_1_SMN_HEADER 61a0bb79e2SKent Russell 62