1 /* 2 * Copyright (C) 2018 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included 12 * in all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN 18 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 19 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 20 */ 21 22 #ifndef _mp_11_0_2_SH_MASK_HEADER 23 #define _mp_11_0_2_SH_MASK_HEADER 24 25 26 // addressBlock: mp_SmuMp0_SmnDec 27 //MP0_SMN_C2PMSG_32 28 #define MP0_SMN_C2PMSG_32__CONTENT__SHIFT 0x0 29 #define MP0_SMN_C2PMSG_32__CONTENT_MASK 0xFFFFFFFFL 30 //MP0_SMN_C2PMSG_33 31 #define MP0_SMN_C2PMSG_33__CONTENT__SHIFT 0x0 32 #define MP0_SMN_C2PMSG_33__CONTENT_MASK 0xFFFFFFFFL 33 //MP0_SMN_C2PMSG_34 34 #define MP0_SMN_C2PMSG_34__CONTENT__SHIFT 0x0 35 #define MP0_SMN_C2PMSG_34__CONTENT_MASK 0xFFFFFFFFL 36 //MP0_SMN_C2PMSG_35 37 #define MP0_SMN_C2PMSG_35__CONTENT__SHIFT 0x0 38 #define MP0_SMN_C2PMSG_35__CONTENT_MASK 0xFFFFFFFFL 39 //MP0_SMN_C2PMSG_36 40 #define MP0_SMN_C2PMSG_36__CONTENT__SHIFT 0x0 41 #define MP0_SMN_C2PMSG_36__CONTENT_MASK 0xFFFFFFFFL 42 //MP0_SMN_C2PMSG_37 43 #define MP0_SMN_C2PMSG_37__CONTENT__SHIFT 0x0 44 #define MP0_SMN_C2PMSG_37__CONTENT_MASK 0xFFFFFFFFL 45 //MP0_SMN_C2PMSG_38 46 #define MP0_SMN_C2PMSG_38__CONTENT__SHIFT 0x0 47 #define MP0_SMN_C2PMSG_38__CONTENT_MASK 0xFFFFFFFFL 48 //MP0_SMN_C2PMSG_39 49 #define MP0_SMN_C2PMSG_39__CONTENT__SHIFT 0x0 50 #define MP0_SMN_C2PMSG_39__CONTENT_MASK 0xFFFFFFFFL 51 //MP0_SMN_C2PMSG_40 52 #define MP0_SMN_C2PMSG_40__CONTENT__SHIFT 0x0 53 #define MP0_SMN_C2PMSG_40__CONTENT_MASK 0xFFFFFFFFL 54 //MP0_SMN_C2PMSG_41 55 #define MP0_SMN_C2PMSG_41__CONTENT__SHIFT 0x0 56 #define MP0_SMN_C2PMSG_41__CONTENT_MASK 0xFFFFFFFFL 57 //MP0_SMN_C2PMSG_42 58 #define MP0_SMN_C2PMSG_42__CONTENT__SHIFT 0x0 59 #define MP0_SMN_C2PMSG_42__CONTENT_MASK 0xFFFFFFFFL 60 //MP0_SMN_C2PMSG_43 61 #define MP0_SMN_C2PMSG_43__CONTENT__SHIFT 0x0 62 #define MP0_SMN_C2PMSG_43__CONTENT_MASK 0xFFFFFFFFL 63 //MP0_SMN_C2PMSG_44 64 #define MP0_SMN_C2PMSG_44__CONTENT__SHIFT 0x0 65 #define MP0_SMN_C2PMSG_44__CONTENT_MASK 0xFFFFFFFFL 66 //MP0_SMN_C2PMSG_45 67 #define MP0_SMN_C2PMSG_45__CONTENT__SHIFT 0x0 68 #define MP0_SMN_C2PMSG_45__CONTENT_MASK 0xFFFFFFFFL 69 //MP0_SMN_C2PMSG_46 70 #define MP0_SMN_C2PMSG_46__CONTENT__SHIFT 0x0 71 #define MP0_SMN_C2PMSG_46__CONTENT_MASK 0xFFFFFFFFL 72 //MP0_SMN_C2PMSG_47 73 #define MP0_SMN_C2PMSG_47__CONTENT__SHIFT 0x0 74 #define MP0_SMN_C2PMSG_47__CONTENT_MASK 0xFFFFFFFFL 75 //MP0_SMN_C2PMSG_48 76 #define MP0_SMN_C2PMSG_48__CONTENT__SHIFT 0x0 77 #define MP0_SMN_C2PMSG_48__CONTENT_MASK 0xFFFFFFFFL 78 //MP0_SMN_C2PMSG_49 79 #define MP0_SMN_C2PMSG_49__CONTENT__SHIFT 0x0 80 #define MP0_SMN_C2PMSG_49__CONTENT_MASK 0xFFFFFFFFL 81 //MP0_SMN_C2PMSG_50 82 #define MP0_SMN_C2PMSG_50__CONTENT__SHIFT 0x0 83 #define MP0_SMN_C2PMSG_50__CONTENT_MASK 0xFFFFFFFFL 84 //MP0_SMN_C2PMSG_51 85 #define MP0_SMN_C2PMSG_51__CONTENT__SHIFT 0x0 86 #define MP0_SMN_C2PMSG_51__CONTENT_MASK 0xFFFFFFFFL 87 //MP0_SMN_C2PMSG_52 88 #define MP0_SMN_C2PMSG_52__CONTENT__SHIFT 0x0 89 #define MP0_SMN_C2PMSG_52__CONTENT_MASK 0xFFFFFFFFL 90 //MP0_SMN_C2PMSG_53 91 #define MP0_SMN_C2PMSG_53__CONTENT__SHIFT 0x0 92 #define MP0_SMN_C2PMSG_53__CONTENT_MASK 0xFFFFFFFFL 93 //MP0_SMN_C2PMSG_54 94 #define MP0_SMN_C2PMSG_54__CONTENT__SHIFT 0x0 95 #define MP0_SMN_C2PMSG_54__CONTENT_MASK 0xFFFFFFFFL 96 //MP0_SMN_C2PMSG_55 97 #define MP0_SMN_C2PMSG_55__CONTENT__SHIFT 0x0 98 #define MP0_SMN_C2PMSG_55__CONTENT_MASK 0xFFFFFFFFL 99 //MP0_SMN_C2PMSG_56 100 #define MP0_SMN_C2PMSG_56__CONTENT__SHIFT 0x0 101 #define MP0_SMN_C2PMSG_56__CONTENT_MASK 0xFFFFFFFFL 102 //MP0_SMN_C2PMSG_57 103 #define MP0_SMN_C2PMSG_57__CONTENT__SHIFT 0x0 104 #define MP0_SMN_C2PMSG_57__CONTENT_MASK 0xFFFFFFFFL 105 //MP0_SMN_C2PMSG_58 106 #define MP0_SMN_C2PMSG_58__CONTENT__SHIFT 0x0 107 #define MP0_SMN_C2PMSG_58__CONTENT_MASK 0xFFFFFFFFL 108 //MP0_SMN_C2PMSG_59 109 #define MP0_SMN_C2PMSG_59__CONTENT__SHIFT 0x0 110 #define MP0_SMN_C2PMSG_59__CONTENT_MASK 0xFFFFFFFFL 111 //MP0_SMN_C2PMSG_60 112 #define MP0_SMN_C2PMSG_60__CONTENT__SHIFT 0x0 113 #define MP0_SMN_C2PMSG_60__CONTENT_MASK 0xFFFFFFFFL 114 //MP0_SMN_C2PMSG_61 115 #define MP0_SMN_C2PMSG_61__CONTENT__SHIFT 0x0 116 #define MP0_SMN_C2PMSG_61__CONTENT_MASK 0xFFFFFFFFL 117 //MP0_SMN_C2PMSG_62 118 #define MP0_SMN_C2PMSG_62__CONTENT__SHIFT 0x0 119 #define MP0_SMN_C2PMSG_62__CONTENT_MASK 0xFFFFFFFFL 120 //MP0_SMN_C2PMSG_63 121 #define MP0_SMN_C2PMSG_63__CONTENT__SHIFT 0x0 122 #define MP0_SMN_C2PMSG_63__CONTENT_MASK 0xFFFFFFFFL 123 //MP0_SMN_C2PMSG_64 124 #define MP0_SMN_C2PMSG_64__CONTENT__SHIFT 0x0 125 #define MP0_SMN_C2PMSG_64__CONTENT_MASK 0xFFFFFFFFL 126 //MP0_SMN_C2PMSG_65 127 #define MP0_SMN_C2PMSG_65__CONTENT__SHIFT 0x0 128 #define MP0_SMN_C2PMSG_65__CONTENT_MASK 0xFFFFFFFFL 129 //MP0_SMN_C2PMSG_66 130 #define MP0_SMN_C2PMSG_66__CONTENT__SHIFT 0x0 131 #define MP0_SMN_C2PMSG_66__CONTENT_MASK 0xFFFFFFFFL 132 //MP0_SMN_C2PMSG_67 133 #define MP0_SMN_C2PMSG_67__CONTENT__SHIFT 0x0 134 #define MP0_SMN_C2PMSG_67__CONTENT_MASK 0xFFFFFFFFL 135 //MP0_SMN_C2PMSG_68 136 #define MP0_SMN_C2PMSG_68__CONTENT__SHIFT 0x0 137 #define MP0_SMN_C2PMSG_68__CONTENT_MASK 0xFFFFFFFFL 138 //MP0_SMN_C2PMSG_69 139 #define MP0_SMN_C2PMSG_69__CONTENT__SHIFT 0x0 140 #define MP0_SMN_C2PMSG_69__CONTENT_MASK 0xFFFFFFFFL 141 //MP0_SMN_C2PMSG_70 142 #define MP0_SMN_C2PMSG_70__CONTENT__SHIFT 0x0 143 #define MP0_SMN_C2PMSG_70__CONTENT_MASK 0xFFFFFFFFL 144 //MP0_SMN_C2PMSG_71 145 #define MP0_SMN_C2PMSG_71__CONTENT__SHIFT 0x0 146 #define MP0_SMN_C2PMSG_71__CONTENT_MASK 0xFFFFFFFFL 147 //MP0_SMN_C2PMSG_72 148 #define MP0_SMN_C2PMSG_72__CONTENT__SHIFT 0x0 149 #define MP0_SMN_C2PMSG_72__CONTENT_MASK 0xFFFFFFFFL 150 //MP0_SMN_C2PMSG_73 151 #define MP0_SMN_C2PMSG_73__CONTENT__SHIFT 0x0 152 #define MP0_SMN_C2PMSG_73__CONTENT_MASK 0xFFFFFFFFL 153 //MP0_SMN_C2PMSG_74 154 #define MP0_SMN_C2PMSG_74__CONTENT__SHIFT 0x0 155 #define MP0_SMN_C2PMSG_74__CONTENT_MASK 0xFFFFFFFFL 156 //MP0_SMN_C2PMSG_75 157 #define MP0_SMN_C2PMSG_75__CONTENT__SHIFT 0x0 158 #define MP0_SMN_C2PMSG_75__CONTENT_MASK 0xFFFFFFFFL 159 //MP0_SMN_C2PMSG_76 160 #define MP0_SMN_C2PMSG_76__CONTENT__SHIFT 0x0 161 #define MP0_SMN_C2PMSG_76__CONTENT_MASK 0xFFFFFFFFL 162 //MP0_SMN_C2PMSG_77 163 #define MP0_SMN_C2PMSG_77__CONTENT__SHIFT 0x0 164 #define MP0_SMN_C2PMSG_77__CONTENT_MASK 0xFFFFFFFFL 165 //MP0_SMN_C2PMSG_78 166 #define MP0_SMN_C2PMSG_78__CONTENT__SHIFT 0x0 167 #define MP0_SMN_C2PMSG_78__CONTENT_MASK 0xFFFFFFFFL 168 //MP0_SMN_C2PMSG_79 169 #define MP0_SMN_C2PMSG_79__CONTENT__SHIFT 0x0 170 #define MP0_SMN_C2PMSG_79__CONTENT_MASK 0xFFFFFFFFL 171 //MP0_SMN_C2PMSG_80 172 #define MP0_SMN_C2PMSG_80__CONTENT__SHIFT 0x0 173 #define MP0_SMN_C2PMSG_80__CONTENT_MASK 0xFFFFFFFFL 174 //MP0_SMN_C2PMSG_81 175 #define MP0_SMN_C2PMSG_81__CONTENT__SHIFT 0x0 176 #define MP0_SMN_C2PMSG_81__CONTENT_MASK 0xFFFFFFFFL 177 //MP0_SMN_C2PMSG_82 178 #define MP0_SMN_C2PMSG_82__CONTENT__SHIFT 0x0 179 #define MP0_SMN_C2PMSG_82__CONTENT_MASK 0xFFFFFFFFL 180 //MP0_SMN_C2PMSG_83 181 #define MP0_SMN_C2PMSG_83__CONTENT__SHIFT 0x0 182 #define MP0_SMN_C2PMSG_83__CONTENT_MASK 0xFFFFFFFFL 183 //MP0_SMN_C2PMSG_84 184 #define MP0_SMN_C2PMSG_84__CONTENT__SHIFT 0x0 185 #define MP0_SMN_C2PMSG_84__CONTENT_MASK 0xFFFFFFFFL 186 //MP0_SMN_C2PMSG_85 187 #define MP0_SMN_C2PMSG_85__CONTENT__SHIFT 0x0 188 #define MP0_SMN_C2PMSG_85__CONTENT_MASK 0xFFFFFFFFL 189 //MP0_SMN_C2PMSG_86 190 #define MP0_SMN_C2PMSG_86__CONTENT__SHIFT 0x0 191 #define MP0_SMN_C2PMSG_86__CONTENT_MASK 0xFFFFFFFFL 192 //MP0_SMN_C2PMSG_87 193 #define MP0_SMN_C2PMSG_87__CONTENT__SHIFT 0x0 194 #define MP0_SMN_C2PMSG_87__CONTENT_MASK 0xFFFFFFFFL 195 //MP0_SMN_C2PMSG_88 196 #define MP0_SMN_C2PMSG_88__CONTENT__SHIFT 0x0 197 #define MP0_SMN_C2PMSG_88__CONTENT_MASK 0xFFFFFFFFL 198 //MP0_SMN_C2PMSG_89 199 #define MP0_SMN_C2PMSG_89__CONTENT__SHIFT 0x0 200 #define MP0_SMN_C2PMSG_89__CONTENT_MASK 0xFFFFFFFFL 201 //MP0_SMN_C2PMSG_90 202 #define MP0_SMN_C2PMSG_90__CONTENT__SHIFT 0x0 203 #define MP0_SMN_C2PMSG_90__CONTENT_MASK 0xFFFFFFFFL 204 //MP0_SMN_C2PMSG_91 205 #define MP0_SMN_C2PMSG_91__CONTENT__SHIFT 0x0 206 #define MP0_SMN_C2PMSG_91__CONTENT_MASK 0xFFFFFFFFL 207 //MP0_SMN_C2PMSG_92 208 #define MP0_SMN_C2PMSG_92__CONTENT__SHIFT 0x0 209 #define MP0_SMN_C2PMSG_92__CONTENT_MASK 0xFFFFFFFFL 210 //MP0_SMN_C2PMSG_93 211 #define MP0_SMN_C2PMSG_93__CONTENT__SHIFT 0x0 212 #define MP0_SMN_C2PMSG_93__CONTENT_MASK 0xFFFFFFFFL 213 //MP0_SMN_C2PMSG_94 214 #define MP0_SMN_C2PMSG_94__CONTENT__SHIFT 0x0 215 #define MP0_SMN_C2PMSG_94__CONTENT_MASK 0xFFFFFFFFL 216 //MP0_SMN_C2PMSG_95 217 #define MP0_SMN_C2PMSG_95__CONTENT__SHIFT 0x0 218 #define MP0_SMN_C2PMSG_95__CONTENT_MASK 0xFFFFFFFFL 219 //MP0_SMN_C2PMSG_96 220 #define MP0_SMN_C2PMSG_96__CONTENT__SHIFT 0x0 221 #define MP0_SMN_C2PMSG_96__CONTENT_MASK 0xFFFFFFFFL 222 //MP0_SMN_C2PMSG_97 223 #define MP0_SMN_C2PMSG_97__CONTENT__SHIFT 0x0 224 #define MP0_SMN_C2PMSG_97__CONTENT_MASK 0xFFFFFFFFL 225 //MP0_SMN_C2PMSG_98 226 #define MP0_SMN_C2PMSG_98__CONTENT__SHIFT 0x0 227 #define MP0_SMN_C2PMSG_98__CONTENT_MASK 0xFFFFFFFFL 228 //MP0_SMN_C2PMSG_99 229 #define MP0_SMN_C2PMSG_99__CONTENT__SHIFT 0x0 230 #define MP0_SMN_C2PMSG_99__CONTENT_MASK 0xFFFFFFFFL 231 //MP0_SMN_C2PMSG_100 232 #define MP0_SMN_C2PMSG_100__CONTENT__SHIFT 0x0 233 #define MP0_SMN_C2PMSG_100__CONTENT_MASK 0xFFFFFFFFL 234 //MP0_SMN_C2PMSG_101 235 #define MP0_SMN_C2PMSG_101__CONTENT__SHIFT 0x0 236 #define MP0_SMN_C2PMSG_101__CONTENT_MASK 0xFFFFFFFFL 237 //MP0_SMN_C2PMSG_102 238 #define MP0_SMN_C2PMSG_102__CONTENT__SHIFT 0x0 239 #define MP0_SMN_C2PMSG_102__CONTENT_MASK 0xFFFFFFFFL 240 //MP0_SMN_C2PMSG_103 241 #define MP0_SMN_C2PMSG_103__CONTENT__SHIFT 0x0 242 #define MP0_SMN_C2PMSG_103__CONTENT_MASK 0xFFFFFFFFL 243 //MP0_SMN_ACTIVE_FCN_ID 244 #define MP0_SMN_ACTIVE_FCN_ID__VFID__SHIFT 0x0 245 #define MP0_SMN_ACTIVE_FCN_ID__VF__SHIFT 0x1f 246 #define MP0_SMN_ACTIVE_FCN_ID__VFID_MASK 0x0000001FL 247 #define MP0_SMN_ACTIVE_FCN_ID__VF_MASK 0x80000000L 248 //MP0_SMN_IH_CREDIT 249 #define MP0_SMN_IH_CREDIT__CREDIT_VALUE__SHIFT 0x0 250 #define MP0_SMN_IH_CREDIT__CLIENT_ID__SHIFT 0x10 251 #define MP0_SMN_IH_CREDIT__CREDIT_VALUE_MASK 0x00000003L 252 #define MP0_SMN_IH_CREDIT__CLIENT_ID_MASK 0x00FF0000L 253 //MP0_SMN_IH_SW_INT 254 #define MP0_SMN_IH_SW_INT__ID__SHIFT 0x0 255 #define MP0_SMN_IH_SW_INT__VALID__SHIFT 0x8 256 #define MP0_SMN_IH_SW_INT__ID_MASK 0x000000FFL 257 #define MP0_SMN_IH_SW_INT__VALID_MASK 0x00000100L 258 //MP0_SMN_IH_SW_INT_CTRL 259 #define MP0_SMN_IH_SW_INT_CTRL__INT_MASK__SHIFT 0x0 260 #define MP0_SMN_IH_SW_INT_CTRL__INT_ACK__SHIFT 0x8 261 #define MP0_SMN_IH_SW_INT_CTRL__INT_MASK_MASK 0x00000001L 262 #define MP0_SMN_IH_SW_INT_CTRL__INT_ACK_MASK 0x00000100L 263 264 265 // addressBlock: mp_SmuMp1_SmnDec 266 //MP1_SMN_C2PMSG_32 267 #define MP1_SMN_C2PMSG_32__CONTENT__SHIFT 0x0 268 #define MP1_SMN_C2PMSG_32__CONTENT_MASK 0xFFFFFFFFL 269 //MP1_SMN_C2PMSG_33 270 #define MP1_SMN_C2PMSG_33__CONTENT__SHIFT 0x0 271 #define MP1_SMN_C2PMSG_33__CONTENT_MASK 0xFFFFFFFFL 272 //MP1_SMN_C2PMSG_34 273 #define MP1_SMN_C2PMSG_34__CONTENT__SHIFT 0x0 274 #define MP1_SMN_C2PMSG_34__CONTENT_MASK 0xFFFFFFFFL 275 //MP1_SMN_C2PMSG_35 276 #define MP1_SMN_C2PMSG_35__CONTENT__SHIFT 0x0 277 #define MP1_SMN_C2PMSG_35__CONTENT_MASK 0xFFFFFFFFL 278 //MP1_SMN_C2PMSG_36 279 #define MP1_SMN_C2PMSG_36__CONTENT__SHIFT 0x0 280 #define MP1_SMN_C2PMSG_36__CONTENT_MASK 0xFFFFFFFFL 281 //MP1_SMN_C2PMSG_37 282 #define MP1_SMN_C2PMSG_37__CONTENT__SHIFT 0x0 283 #define MP1_SMN_C2PMSG_37__CONTENT_MASK 0xFFFFFFFFL 284 //MP1_SMN_C2PMSG_38 285 #define MP1_SMN_C2PMSG_38__CONTENT__SHIFT 0x0 286 #define MP1_SMN_C2PMSG_38__CONTENT_MASK 0xFFFFFFFFL 287 //MP1_SMN_C2PMSG_39 288 #define MP1_SMN_C2PMSG_39__CONTENT__SHIFT 0x0 289 #define MP1_SMN_C2PMSG_39__CONTENT_MASK 0xFFFFFFFFL 290 //MP1_SMN_C2PMSG_40 291 #define MP1_SMN_C2PMSG_40__CONTENT__SHIFT 0x0 292 #define MP1_SMN_C2PMSG_40__CONTENT_MASK 0xFFFFFFFFL 293 //MP1_SMN_C2PMSG_41 294 #define MP1_SMN_C2PMSG_41__CONTENT__SHIFT 0x0 295 #define MP1_SMN_C2PMSG_41__CONTENT_MASK 0xFFFFFFFFL 296 //MP1_SMN_C2PMSG_42 297 #define MP1_SMN_C2PMSG_42__CONTENT__SHIFT 0x0 298 #define MP1_SMN_C2PMSG_42__CONTENT_MASK 0xFFFFFFFFL 299 //MP1_SMN_C2PMSG_43 300 #define MP1_SMN_C2PMSG_43__CONTENT__SHIFT 0x0 301 #define MP1_SMN_C2PMSG_43__CONTENT_MASK 0xFFFFFFFFL 302 //MP1_SMN_C2PMSG_44 303 #define MP1_SMN_C2PMSG_44__CONTENT__SHIFT 0x0 304 #define MP1_SMN_C2PMSG_44__CONTENT_MASK 0xFFFFFFFFL 305 //MP1_SMN_C2PMSG_45 306 #define MP1_SMN_C2PMSG_45__CONTENT__SHIFT 0x0 307 #define MP1_SMN_C2PMSG_45__CONTENT_MASK 0xFFFFFFFFL 308 //MP1_SMN_C2PMSG_46 309 #define MP1_SMN_C2PMSG_46__CONTENT__SHIFT 0x0 310 #define MP1_SMN_C2PMSG_46__CONTENT_MASK 0xFFFFFFFFL 311 //MP1_SMN_C2PMSG_47 312 #define MP1_SMN_C2PMSG_47__CONTENT__SHIFT 0x0 313 #define MP1_SMN_C2PMSG_47__CONTENT_MASK 0xFFFFFFFFL 314 //MP1_SMN_C2PMSG_48 315 #define MP1_SMN_C2PMSG_48__CONTENT__SHIFT 0x0 316 #define MP1_SMN_C2PMSG_48__CONTENT_MASK 0xFFFFFFFFL 317 //MP1_SMN_C2PMSG_49 318 #define MP1_SMN_C2PMSG_49__CONTENT__SHIFT 0x0 319 #define MP1_SMN_C2PMSG_49__CONTENT_MASK 0xFFFFFFFFL 320 //MP1_SMN_C2PMSG_50 321 #define MP1_SMN_C2PMSG_50__CONTENT__SHIFT 0x0 322 #define MP1_SMN_C2PMSG_50__CONTENT_MASK 0xFFFFFFFFL 323 //MP1_SMN_C2PMSG_51 324 #define MP1_SMN_C2PMSG_51__CONTENT__SHIFT 0x0 325 #define MP1_SMN_C2PMSG_51__CONTENT_MASK 0xFFFFFFFFL 326 //MP1_SMN_C2PMSG_52 327 #define MP1_SMN_C2PMSG_52__CONTENT__SHIFT 0x0 328 #define MP1_SMN_C2PMSG_52__CONTENT_MASK 0xFFFFFFFFL 329 //MP1_SMN_C2PMSG_53 330 #define MP1_SMN_C2PMSG_53__CONTENT__SHIFT 0x0 331 #define MP1_SMN_C2PMSG_53__CONTENT_MASK 0xFFFFFFFFL 332 //MP1_SMN_C2PMSG_54 333 #define MP1_SMN_C2PMSG_54__CONTENT__SHIFT 0x0 334 #define MP1_SMN_C2PMSG_54__CONTENT_MASK 0xFFFFFFFFL 335 //MP1_SMN_C2PMSG_55 336 #define MP1_SMN_C2PMSG_55__CONTENT__SHIFT 0x0 337 #define MP1_SMN_C2PMSG_55__CONTENT_MASK 0xFFFFFFFFL 338 //MP1_SMN_C2PMSG_56 339 #define MP1_SMN_C2PMSG_56__CONTENT__SHIFT 0x0 340 #define MP1_SMN_C2PMSG_56__CONTENT_MASK 0xFFFFFFFFL 341 //MP1_SMN_C2PMSG_57 342 #define MP1_SMN_C2PMSG_57__CONTENT__SHIFT 0x0 343 #define MP1_SMN_C2PMSG_57__CONTENT_MASK 0xFFFFFFFFL 344 //MP1_SMN_C2PMSG_58 345 #define MP1_SMN_C2PMSG_58__CONTENT__SHIFT 0x0 346 #define MP1_SMN_C2PMSG_58__CONTENT_MASK 0xFFFFFFFFL 347 //MP1_SMN_C2PMSG_59 348 #define MP1_SMN_C2PMSG_59__CONTENT__SHIFT 0x0 349 #define MP1_SMN_C2PMSG_59__CONTENT_MASK 0xFFFFFFFFL 350 //MP1_SMN_C2PMSG_60 351 #define MP1_SMN_C2PMSG_60__CONTENT__SHIFT 0x0 352 #define MP1_SMN_C2PMSG_60__CONTENT_MASK 0xFFFFFFFFL 353 //MP1_SMN_C2PMSG_61 354 #define MP1_SMN_C2PMSG_61__CONTENT__SHIFT 0x0 355 #define MP1_SMN_C2PMSG_61__CONTENT_MASK 0xFFFFFFFFL 356 //MP1_SMN_C2PMSG_62 357 #define MP1_SMN_C2PMSG_62__CONTENT__SHIFT 0x0 358 #define MP1_SMN_C2PMSG_62__CONTENT_MASK 0xFFFFFFFFL 359 //MP1_SMN_C2PMSG_63 360 #define MP1_SMN_C2PMSG_63__CONTENT__SHIFT 0x0 361 #define MP1_SMN_C2PMSG_63__CONTENT_MASK 0xFFFFFFFFL 362 //MP1_SMN_C2PMSG_64 363 #define MP1_SMN_C2PMSG_64__CONTENT__SHIFT 0x0 364 #define MP1_SMN_C2PMSG_64__CONTENT_MASK 0xFFFFFFFFL 365 //MP1_SMN_C2PMSG_65 366 #define MP1_SMN_C2PMSG_65__CONTENT__SHIFT 0x0 367 #define MP1_SMN_C2PMSG_65__CONTENT_MASK 0xFFFFFFFFL 368 //MP1_SMN_C2PMSG_66 369 #define MP1_SMN_C2PMSG_66__CONTENT__SHIFT 0x0 370 #define MP1_SMN_C2PMSG_66__CONTENT_MASK 0xFFFFFFFFL 371 //MP1_SMN_C2PMSG_67 372 #define MP1_SMN_C2PMSG_67__CONTENT__SHIFT 0x0 373 #define MP1_SMN_C2PMSG_67__CONTENT_MASK 0xFFFFFFFFL 374 //MP1_SMN_C2PMSG_68 375 #define MP1_SMN_C2PMSG_68__CONTENT__SHIFT 0x0 376 #define MP1_SMN_C2PMSG_68__CONTENT_MASK 0xFFFFFFFFL 377 //MP1_SMN_C2PMSG_69 378 #define MP1_SMN_C2PMSG_69__CONTENT__SHIFT 0x0 379 #define MP1_SMN_C2PMSG_69__CONTENT_MASK 0xFFFFFFFFL 380 //MP1_SMN_C2PMSG_70 381 #define MP1_SMN_C2PMSG_70__CONTENT__SHIFT 0x0 382 #define MP1_SMN_C2PMSG_70__CONTENT_MASK 0xFFFFFFFFL 383 //MP1_SMN_C2PMSG_71 384 #define MP1_SMN_C2PMSG_71__CONTENT__SHIFT 0x0 385 #define MP1_SMN_C2PMSG_71__CONTENT_MASK 0xFFFFFFFFL 386 //MP1_SMN_C2PMSG_72 387 #define MP1_SMN_C2PMSG_72__CONTENT__SHIFT 0x0 388 #define MP1_SMN_C2PMSG_72__CONTENT_MASK 0xFFFFFFFFL 389 //MP1_SMN_C2PMSG_73 390 #define MP1_SMN_C2PMSG_73__CONTENT__SHIFT 0x0 391 #define MP1_SMN_C2PMSG_73__CONTENT_MASK 0xFFFFFFFFL 392 //MP1_SMN_C2PMSG_74 393 #define MP1_SMN_C2PMSG_74__CONTENT__SHIFT 0x0 394 #define MP1_SMN_C2PMSG_74__CONTENT_MASK 0xFFFFFFFFL 395 //MP1_SMN_C2PMSG_75 396 #define MP1_SMN_C2PMSG_75__CONTENT__SHIFT 0x0 397 #define MP1_SMN_C2PMSG_75__CONTENT_MASK 0xFFFFFFFFL 398 //MP1_SMN_C2PMSG_76 399 #define MP1_SMN_C2PMSG_76__CONTENT__SHIFT 0x0 400 #define MP1_SMN_C2PMSG_76__CONTENT_MASK 0xFFFFFFFFL 401 //MP1_SMN_C2PMSG_77 402 #define MP1_SMN_C2PMSG_77__CONTENT__SHIFT 0x0 403 #define MP1_SMN_C2PMSG_77__CONTENT_MASK 0xFFFFFFFFL 404 //MP1_SMN_C2PMSG_78 405 #define MP1_SMN_C2PMSG_78__CONTENT__SHIFT 0x0 406 #define MP1_SMN_C2PMSG_78__CONTENT_MASK 0xFFFFFFFFL 407 //MP1_SMN_C2PMSG_79 408 #define MP1_SMN_C2PMSG_79__CONTENT__SHIFT 0x0 409 #define MP1_SMN_C2PMSG_79__CONTENT_MASK 0xFFFFFFFFL 410 //MP1_SMN_C2PMSG_80 411 #define MP1_SMN_C2PMSG_80__CONTENT__SHIFT 0x0 412 #define MP1_SMN_C2PMSG_80__CONTENT_MASK 0xFFFFFFFFL 413 //MP1_SMN_C2PMSG_81 414 #define MP1_SMN_C2PMSG_81__CONTENT__SHIFT 0x0 415 #define MP1_SMN_C2PMSG_81__CONTENT_MASK 0xFFFFFFFFL 416 //MP1_SMN_C2PMSG_82 417 #define MP1_SMN_C2PMSG_82__CONTENT__SHIFT 0x0 418 #define MP1_SMN_C2PMSG_82__CONTENT_MASK 0xFFFFFFFFL 419 //MP1_SMN_C2PMSG_83 420 #define MP1_SMN_C2PMSG_83__CONTENT__SHIFT 0x0 421 #define MP1_SMN_C2PMSG_83__CONTENT_MASK 0xFFFFFFFFL 422 //MP1_SMN_C2PMSG_84 423 #define MP1_SMN_C2PMSG_84__CONTENT__SHIFT 0x0 424 #define MP1_SMN_C2PMSG_84__CONTENT_MASK 0xFFFFFFFFL 425 //MP1_SMN_C2PMSG_85 426 #define MP1_SMN_C2PMSG_85__CONTENT__SHIFT 0x0 427 #define MP1_SMN_C2PMSG_85__CONTENT_MASK 0xFFFFFFFFL 428 //MP1_SMN_C2PMSG_86 429 #define MP1_SMN_C2PMSG_86__CONTENT__SHIFT 0x0 430 #define MP1_SMN_C2PMSG_86__CONTENT_MASK 0xFFFFFFFFL 431 //MP1_SMN_C2PMSG_87 432 #define MP1_SMN_C2PMSG_87__CONTENT__SHIFT 0x0 433 #define MP1_SMN_C2PMSG_87__CONTENT_MASK 0xFFFFFFFFL 434 //MP1_SMN_C2PMSG_88 435 #define MP1_SMN_C2PMSG_88__CONTENT__SHIFT 0x0 436 #define MP1_SMN_C2PMSG_88__CONTENT_MASK 0xFFFFFFFFL 437 //MP1_SMN_C2PMSG_89 438 #define MP1_SMN_C2PMSG_89__CONTENT__SHIFT 0x0 439 #define MP1_SMN_C2PMSG_89__CONTENT_MASK 0xFFFFFFFFL 440 //MP1_SMN_C2PMSG_90 441 #define MP1_SMN_C2PMSG_90__CONTENT__SHIFT 0x0 442 #define MP1_SMN_C2PMSG_90__CONTENT_MASK 0xFFFFFFFFL 443 //MP1_SMN_C2PMSG_91 444 #define MP1_SMN_C2PMSG_91__CONTENT__SHIFT 0x0 445 #define MP1_SMN_C2PMSG_91__CONTENT_MASK 0xFFFFFFFFL 446 //MP1_SMN_C2PMSG_92 447 #define MP1_SMN_C2PMSG_92__CONTENT__SHIFT 0x0 448 #define MP1_SMN_C2PMSG_92__CONTENT_MASK 0xFFFFFFFFL 449 //MP1_SMN_C2PMSG_93 450 #define MP1_SMN_C2PMSG_93__CONTENT__SHIFT 0x0 451 #define MP1_SMN_C2PMSG_93__CONTENT_MASK 0xFFFFFFFFL 452 //MP1_SMN_C2PMSG_94 453 #define MP1_SMN_C2PMSG_94__CONTENT__SHIFT 0x0 454 #define MP1_SMN_C2PMSG_94__CONTENT_MASK 0xFFFFFFFFL 455 //MP1_SMN_C2PMSG_95 456 #define MP1_SMN_C2PMSG_95__CONTENT__SHIFT 0x0 457 #define MP1_SMN_C2PMSG_95__CONTENT_MASK 0xFFFFFFFFL 458 //MP1_SMN_C2PMSG_96 459 #define MP1_SMN_C2PMSG_96__CONTENT__SHIFT 0x0 460 #define MP1_SMN_C2PMSG_96__CONTENT_MASK 0xFFFFFFFFL 461 //MP1_SMN_C2PMSG_97 462 #define MP1_SMN_C2PMSG_97__CONTENT__SHIFT 0x0 463 #define MP1_SMN_C2PMSG_97__CONTENT_MASK 0xFFFFFFFFL 464 //MP1_SMN_C2PMSG_98 465 #define MP1_SMN_C2PMSG_98__CONTENT__SHIFT 0x0 466 #define MP1_SMN_C2PMSG_98__CONTENT_MASK 0xFFFFFFFFL 467 //MP1_SMN_C2PMSG_99 468 #define MP1_SMN_C2PMSG_99__CONTENT__SHIFT 0x0 469 #define MP1_SMN_C2PMSG_99__CONTENT_MASK 0xFFFFFFFFL 470 //MP1_SMN_C2PMSG_100 471 #define MP1_SMN_C2PMSG_100__CONTENT__SHIFT 0x0 472 #define MP1_SMN_C2PMSG_100__CONTENT_MASK 0xFFFFFFFFL 473 //MP1_SMN_C2PMSG_101 474 #define MP1_SMN_C2PMSG_101__CONTENT__SHIFT 0x0 475 #define MP1_SMN_C2PMSG_101__CONTENT_MASK 0xFFFFFFFFL 476 //MP1_SMN_C2PMSG_102 477 #define MP1_SMN_C2PMSG_102__CONTENT__SHIFT 0x0 478 #define MP1_SMN_C2PMSG_102__CONTENT_MASK 0xFFFFFFFFL 479 //MP1_SMN_C2PMSG_103 480 #define MP1_SMN_C2PMSG_103__CONTENT__SHIFT 0x0 481 #define MP1_SMN_C2PMSG_103__CONTENT_MASK 0xFFFFFFFFL 482 //MP1_SMN_ACTIVE_FCN_ID 483 #define MP1_SMN_ACTIVE_FCN_ID__VFID__SHIFT 0x0 484 #define MP1_SMN_ACTIVE_FCN_ID__VF__SHIFT 0x1f 485 #define MP1_SMN_ACTIVE_FCN_ID__VFID_MASK 0x0000001FL 486 #define MP1_SMN_ACTIVE_FCN_ID__VF_MASK 0x80000000L 487 //MP1_SMN_IH_CREDIT 488 #define MP1_SMN_IH_CREDIT__CREDIT_VALUE__SHIFT 0x0 489 #define MP1_SMN_IH_CREDIT__CLIENT_ID__SHIFT 0x10 490 #define MP1_SMN_IH_CREDIT__CREDIT_VALUE_MASK 0x00000003L 491 #define MP1_SMN_IH_CREDIT__CLIENT_ID_MASK 0x00FF0000L 492 //MP1_SMN_IH_SW_INT 493 #define MP1_SMN_IH_SW_INT__ID__SHIFT 0x0 494 #define MP1_SMN_IH_SW_INT__VALID__SHIFT 0x8 495 #define MP1_SMN_IH_SW_INT__ID_MASK 0x000000FFL 496 #define MP1_SMN_IH_SW_INT__VALID_MASK 0x00000100L 497 //MP1_SMN_IH_SW_INT_CTRL 498 #define MP1_SMN_IH_SW_INT_CTRL__INT_MASK__SHIFT 0x0 499 #define MP1_SMN_IH_SW_INT_CTRL__INT_ACK__SHIFT 0x8 500 #define MP1_SMN_IH_SW_INT_CTRL__INT_MASK_MASK 0x00000001L 501 #define MP1_SMN_IH_SW_INT_CTRL__INT_ACK_MASK 0x00000100L 502 //MP1_SMN_FPS_CNT 503 #define MP1_SMN_FPS_CNT__COUNT__SHIFT 0x0 504 #define MP1_SMN_FPS_CNT__COUNT_MASK 0xFFFFFFFFL 505 //MP1_SMN_PUB_CTRL 506 #define MP1_SMN_PUB_CTRL__RESET__SHIFT 0x0 507 #define MP1_SMN_PUB_CTRL__RESET_MASK 0x00000001L 508 //MP1_SMN_EXT_SCRATCH0 509 #define MP1_SMN_EXT_SCRATCH0__DATA__SHIFT 0x0 510 #define MP1_SMN_EXT_SCRATCH0__DATA_MASK 0xFFFFFFFFL 511 //MP1_SMN_EXT_SCRATCH1 512 #define MP1_SMN_EXT_SCRATCH1__DATA__SHIFT 0x0 513 #define MP1_SMN_EXT_SCRATCH1__DATA_MASK 0xFFFFFFFFL 514 //MP1_SMN_EXT_SCRATCH2 515 #define MP1_SMN_EXT_SCRATCH2__DATA__SHIFT 0x0 516 #define MP1_SMN_EXT_SCRATCH2__DATA_MASK 0xFFFFFFFFL 517 //MP1_SMN_EXT_SCRATCH3 518 #define MP1_SMN_EXT_SCRATCH3__DATA__SHIFT 0x0 519 #define MP1_SMN_EXT_SCRATCH3__DATA_MASK 0xFFFFFFFFL 520 //MP1_SMN_EXT_SCRATCH4 521 #define MP1_SMN_EXT_SCRATCH4__DATA__SHIFT 0x0 522 #define MP1_SMN_EXT_SCRATCH4__DATA_MASK 0xFFFFFFFFL 523 //MP1_SMN_EXT_SCRATCH5 524 #define MP1_SMN_EXT_SCRATCH5__DATA__SHIFT 0x0 525 #define MP1_SMN_EXT_SCRATCH5__DATA_MASK 0xFFFFFFFFL 526 //MP1_SMN_EXT_SCRATCH6 527 #define MP1_SMN_EXT_SCRATCH6__DATA__SHIFT 0x0 528 #define MP1_SMN_EXT_SCRATCH6__DATA_MASK 0xFFFFFFFFL 529 //MP1_SMN_EXT_SCRATCH7 530 #define MP1_SMN_EXT_SCRATCH7__DATA__SHIFT 0x0 531 #define MP1_SMN_EXT_SCRATCH7__DATA_MASK 0xFFFFFFFFL 532 533 534 #endif 535