195c1f7aaSFeifei Xu /* 295c1f7aaSFeifei Xu * Copyright (C) 2017 Advanced Micro Devices, Inc. 395c1f7aaSFeifei Xu * 495c1f7aaSFeifei Xu * Permission is hereby granted, free of charge, to any person obtaining a 595c1f7aaSFeifei Xu * copy of this software and associated documentation files (the "Software"), 695c1f7aaSFeifei Xu * to deal in the Software without restriction, including without limitation 795c1f7aaSFeifei Xu * the rights to use, copy, modify, merge, publish, distribute, sublicense, 895c1f7aaSFeifei Xu * and/or sell copies of the Software, and to permit persons to whom the 995c1f7aaSFeifei Xu * Software is furnished to do so, subject to the following conditions: 1095c1f7aaSFeifei Xu * 1195c1f7aaSFeifei Xu * The above copyright notice and this permission notice shall be included 1295c1f7aaSFeifei Xu * in all copies or substantial portions of the Software. 1395c1f7aaSFeifei Xu * 1495c1f7aaSFeifei Xu * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 1595c1f7aaSFeifei Xu * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 1695c1f7aaSFeifei Xu * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 1795c1f7aaSFeifei Xu * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN 1895c1f7aaSFeifei Xu * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 1995c1f7aaSFeifei Xu * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 2095c1f7aaSFeifei Xu */ 2195c1f7aaSFeifei Xu #ifndef _mmhub_9_1_SH_MASK_HEADER 2295c1f7aaSFeifei Xu #define _mmhub_9_1_SH_MASK_HEADER 2395c1f7aaSFeifei Xu 2495c1f7aaSFeifei Xu 2595c1f7aaSFeifei Xu // addressBlock: mmhub_dagbdec 2695c1f7aaSFeifei Xu //DAGB0_RDCLI0 2795c1f7aaSFeifei Xu #define DAGB0_RDCLI0__VIRT_CHAN__SHIFT 0x0 2895c1f7aaSFeifei Xu #define DAGB0_RDCLI0__CHECK_TLB_CREDIT__SHIFT 0x3 2995c1f7aaSFeifei Xu #define DAGB0_RDCLI0__URG_HIGH__SHIFT 0x4 3095c1f7aaSFeifei Xu #define DAGB0_RDCLI0__URG_LOW__SHIFT 0x8 3195c1f7aaSFeifei Xu #define DAGB0_RDCLI0__MAX_BW_ENABLE__SHIFT 0xc 3295c1f7aaSFeifei Xu #define DAGB0_RDCLI0__MAX_BW__SHIFT 0xd 3395c1f7aaSFeifei Xu #define DAGB0_RDCLI0__MIN_BW_ENABLE__SHIFT 0x15 3495c1f7aaSFeifei Xu #define DAGB0_RDCLI0__MIN_BW__SHIFT 0x16 3595c1f7aaSFeifei Xu #define DAGB0_RDCLI0__OSD_LIMITER_ENABLE__SHIFT 0x19 3695c1f7aaSFeifei Xu #define DAGB0_RDCLI0__MAX_OSD__SHIFT 0x1a 3795c1f7aaSFeifei Xu #define DAGB0_RDCLI0__VIRT_CHAN_MASK 0x00000007L 3895c1f7aaSFeifei Xu #define DAGB0_RDCLI0__CHECK_TLB_CREDIT_MASK 0x00000008L 3995c1f7aaSFeifei Xu #define DAGB0_RDCLI0__URG_HIGH_MASK 0x000000F0L 4095c1f7aaSFeifei Xu #define DAGB0_RDCLI0__URG_LOW_MASK 0x00000F00L 4195c1f7aaSFeifei Xu #define DAGB0_RDCLI0__MAX_BW_ENABLE_MASK 0x00001000L 4295c1f7aaSFeifei Xu #define DAGB0_RDCLI0__MAX_BW_MASK 0x001FE000L 4395c1f7aaSFeifei Xu #define DAGB0_RDCLI0__MIN_BW_ENABLE_MASK 0x00200000L 4495c1f7aaSFeifei Xu #define DAGB0_RDCLI0__MIN_BW_MASK 0x01C00000L 4595c1f7aaSFeifei Xu #define DAGB0_RDCLI0__OSD_LIMITER_ENABLE_MASK 0x02000000L 4695c1f7aaSFeifei Xu #define DAGB0_RDCLI0__MAX_OSD_MASK 0xFC000000L 4795c1f7aaSFeifei Xu //DAGB0_RDCLI1 4895c1f7aaSFeifei Xu #define DAGB0_RDCLI1__VIRT_CHAN__SHIFT 0x0 4995c1f7aaSFeifei Xu #define DAGB0_RDCLI1__CHECK_TLB_CREDIT__SHIFT 0x3 5095c1f7aaSFeifei Xu #define DAGB0_RDCLI1__URG_HIGH__SHIFT 0x4 5195c1f7aaSFeifei Xu #define DAGB0_RDCLI1__URG_LOW__SHIFT 0x8 5295c1f7aaSFeifei Xu #define DAGB0_RDCLI1__MAX_BW_ENABLE__SHIFT 0xc 5395c1f7aaSFeifei Xu #define DAGB0_RDCLI1__MAX_BW__SHIFT 0xd 5495c1f7aaSFeifei Xu #define DAGB0_RDCLI1__MIN_BW_ENABLE__SHIFT 0x15 5595c1f7aaSFeifei Xu #define DAGB0_RDCLI1__MIN_BW__SHIFT 0x16 5695c1f7aaSFeifei Xu #define DAGB0_RDCLI1__OSD_LIMITER_ENABLE__SHIFT 0x19 5795c1f7aaSFeifei Xu #define DAGB0_RDCLI1__MAX_OSD__SHIFT 0x1a 5895c1f7aaSFeifei Xu #define DAGB0_RDCLI1__VIRT_CHAN_MASK 0x00000007L 5995c1f7aaSFeifei Xu #define DAGB0_RDCLI1__CHECK_TLB_CREDIT_MASK 0x00000008L 6095c1f7aaSFeifei Xu #define DAGB0_RDCLI1__URG_HIGH_MASK 0x000000F0L 6195c1f7aaSFeifei Xu #define DAGB0_RDCLI1__URG_LOW_MASK 0x00000F00L 6295c1f7aaSFeifei Xu #define DAGB0_RDCLI1__MAX_BW_ENABLE_MASK 0x00001000L 6395c1f7aaSFeifei Xu #define DAGB0_RDCLI1__MAX_BW_MASK 0x001FE000L 6495c1f7aaSFeifei Xu #define DAGB0_RDCLI1__MIN_BW_ENABLE_MASK 0x00200000L 6595c1f7aaSFeifei Xu #define DAGB0_RDCLI1__MIN_BW_MASK 0x01C00000L 6695c1f7aaSFeifei Xu #define DAGB0_RDCLI1__OSD_LIMITER_ENABLE_MASK 0x02000000L 6795c1f7aaSFeifei Xu #define DAGB0_RDCLI1__MAX_OSD_MASK 0xFC000000L 6895c1f7aaSFeifei Xu //DAGB0_RDCLI2 6995c1f7aaSFeifei Xu #define DAGB0_RDCLI2__VIRT_CHAN__SHIFT 0x0 7095c1f7aaSFeifei Xu #define DAGB0_RDCLI2__CHECK_TLB_CREDIT__SHIFT 0x3 7195c1f7aaSFeifei Xu #define DAGB0_RDCLI2__URG_HIGH__SHIFT 0x4 7295c1f7aaSFeifei Xu #define DAGB0_RDCLI2__URG_LOW__SHIFT 0x8 7395c1f7aaSFeifei Xu #define DAGB0_RDCLI2__MAX_BW_ENABLE__SHIFT 0xc 7495c1f7aaSFeifei Xu #define DAGB0_RDCLI2__MAX_BW__SHIFT 0xd 7595c1f7aaSFeifei Xu #define DAGB0_RDCLI2__MIN_BW_ENABLE__SHIFT 0x15 7695c1f7aaSFeifei Xu #define DAGB0_RDCLI2__MIN_BW__SHIFT 0x16 7795c1f7aaSFeifei Xu #define DAGB0_RDCLI2__OSD_LIMITER_ENABLE__SHIFT 0x19 7895c1f7aaSFeifei Xu #define DAGB0_RDCLI2__MAX_OSD__SHIFT 0x1a 7995c1f7aaSFeifei Xu #define DAGB0_RDCLI2__VIRT_CHAN_MASK 0x00000007L 8095c1f7aaSFeifei Xu #define DAGB0_RDCLI2__CHECK_TLB_CREDIT_MASK 0x00000008L 8195c1f7aaSFeifei Xu #define DAGB0_RDCLI2__URG_HIGH_MASK 0x000000F0L 8295c1f7aaSFeifei Xu #define DAGB0_RDCLI2__URG_LOW_MASK 0x00000F00L 8395c1f7aaSFeifei Xu #define DAGB0_RDCLI2__MAX_BW_ENABLE_MASK 0x00001000L 8495c1f7aaSFeifei Xu #define DAGB0_RDCLI2__MAX_BW_MASK 0x001FE000L 8595c1f7aaSFeifei Xu #define DAGB0_RDCLI2__MIN_BW_ENABLE_MASK 0x00200000L 8695c1f7aaSFeifei Xu #define DAGB0_RDCLI2__MIN_BW_MASK 0x01C00000L 8795c1f7aaSFeifei Xu #define DAGB0_RDCLI2__OSD_LIMITER_ENABLE_MASK 0x02000000L 8895c1f7aaSFeifei Xu #define DAGB0_RDCLI2__MAX_OSD_MASK 0xFC000000L 8995c1f7aaSFeifei Xu //DAGB0_RDCLI3 9095c1f7aaSFeifei Xu #define DAGB0_RDCLI3__VIRT_CHAN__SHIFT 0x0 9195c1f7aaSFeifei Xu #define DAGB0_RDCLI3__CHECK_TLB_CREDIT__SHIFT 0x3 9295c1f7aaSFeifei Xu #define DAGB0_RDCLI3__URG_HIGH__SHIFT 0x4 9395c1f7aaSFeifei Xu #define DAGB0_RDCLI3__URG_LOW__SHIFT 0x8 9495c1f7aaSFeifei Xu #define DAGB0_RDCLI3__MAX_BW_ENABLE__SHIFT 0xc 9595c1f7aaSFeifei Xu #define DAGB0_RDCLI3__MAX_BW__SHIFT 0xd 9695c1f7aaSFeifei Xu #define DAGB0_RDCLI3__MIN_BW_ENABLE__SHIFT 0x15 9795c1f7aaSFeifei Xu #define DAGB0_RDCLI3__MIN_BW__SHIFT 0x16 9895c1f7aaSFeifei Xu #define DAGB0_RDCLI3__OSD_LIMITER_ENABLE__SHIFT 0x19 9995c1f7aaSFeifei Xu #define DAGB0_RDCLI3__MAX_OSD__SHIFT 0x1a 10095c1f7aaSFeifei Xu #define DAGB0_RDCLI3__VIRT_CHAN_MASK 0x00000007L 10195c1f7aaSFeifei Xu #define DAGB0_RDCLI3__CHECK_TLB_CREDIT_MASK 0x00000008L 10295c1f7aaSFeifei Xu #define DAGB0_RDCLI3__URG_HIGH_MASK 0x000000F0L 10395c1f7aaSFeifei Xu #define DAGB0_RDCLI3__URG_LOW_MASK 0x00000F00L 10495c1f7aaSFeifei Xu #define DAGB0_RDCLI3__MAX_BW_ENABLE_MASK 0x00001000L 10595c1f7aaSFeifei Xu #define DAGB0_RDCLI3__MAX_BW_MASK 0x001FE000L 10695c1f7aaSFeifei Xu #define DAGB0_RDCLI3__MIN_BW_ENABLE_MASK 0x00200000L 10795c1f7aaSFeifei Xu #define DAGB0_RDCLI3__MIN_BW_MASK 0x01C00000L 10895c1f7aaSFeifei Xu #define DAGB0_RDCLI3__OSD_LIMITER_ENABLE_MASK 0x02000000L 10995c1f7aaSFeifei Xu #define DAGB0_RDCLI3__MAX_OSD_MASK 0xFC000000L 11095c1f7aaSFeifei Xu //DAGB0_RDCLI4 11195c1f7aaSFeifei Xu #define DAGB0_RDCLI4__VIRT_CHAN__SHIFT 0x0 11295c1f7aaSFeifei Xu #define DAGB0_RDCLI4__CHECK_TLB_CREDIT__SHIFT 0x3 11395c1f7aaSFeifei Xu #define DAGB0_RDCLI4__URG_HIGH__SHIFT 0x4 11495c1f7aaSFeifei Xu #define DAGB0_RDCLI4__URG_LOW__SHIFT 0x8 11595c1f7aaSFeifei Xu #define DAGB0_RDCLI4__MAX_BW_ENABLE__SHIFT 0xc 11695c1f7aaSFeifei Xu #define DAGB0_RDCLI4__MAX_BW__SHIFT 0xd 11795c1f7aaSFeifei Xu #define DAGB0_RDCLI4__MIN_BW_ENABLE__SHIFT 0x15 11895c1f7aaSFeifei Xu #define DAGB0_RDCLI4__MIN_BW__SHIFT 0x16 11995c1f7aaSFeifei Xu #define DAGB0_RDCLI4__OSD_LIMITER_ENABLE__SHIFT 0x19 12095c1f7aaSFeifei Xu #define DAGB0_RDCLI4__MAX_OSD__SHIFT 0x1a 12195c1f7aaSFeifei Xu #define DAGB0_RDCLI4__VIRT_CHAN_MASK 0x00000007L 12295c1f7aaSFeifei Xu #define DAGB0_RDCLI4__CHECK_TLB_CREDIT_MASK 0x00000008L 12395c1f7aaSFeifei Xu #define DAGB0_RDCLI4__URG_HIGH_MASK 0x000000F0L 12495c1f7aaSFeifei Xu #define DAGB0_RDCLI4__URG_LOW_MASK 0x00000F00L 12595c1f7aaSFeifei Xu #define DAGB0_RDCLI4__MAX_BW_ENABLE_MASK 0x00001000L 12695c1f7aaSFeifei Xu #define DAGB0_RDCLI4__MAX_BW_MASK 0x001FE000L 12795c1f7aaSFeifei Xu #define DAGB0_RDCLI4__MIN_BW_ENABLE_MASK 0x00200000L 12895c1f7aaSFeifei Xu #define DAGB0_RDCLI4__MIN_BW_MASK 0x01C00000L 12995c1f7aaSFeifei Xu #define DAGB0_RDCLI4__OSD_LIMITER_ENABLE_MASK 0x02000000L 13095c1f7aaSFeifei Xu #define DAGB0_RDCLI4__MAX_OSD_MASK 0xFC000000L 13195c1f7aaSFeifei Xu //DAGB0_RDCLI5 13295c1f7aaSFeifei Xu #define DAGB0_RDCLI5__VIRT_CHAN__SHIFT 0x0 13395c1f7aaSFeifei Xu #define DAGB0_RDCLI5__CHECK_TLB_CREDIT__SHIFT 0x3 13495c1f7aaSFeifei Xu #define DAGB0_RDCLI5__URG_HIGH__SHIFT 0x4 13595c1f7aaSFeifei Xu #define DAGB0_RDCLI5__URG_LOW__SHIFT 0x8 13695c1f7aaSFeifei Xu #define DAGB0_RDCLI5__MAX_BW_ENABLE__SHIFT 0xc 13795c1f7aaSFeifei Xu #define DAGB0_RDCLI5__MAX_BW__SHIFT 0xd 13895c1f7aaSFeifei Xu #define DAGB0_RDCLI5__MIN_BW_ENABLE__SHIFT 0x15 13995c1f7aaSFeifei Xu #define DAGB0_RDCLI5__MIN_BW__SHIFT 0x16 14095c1f7aaSFeifei Xu #define DAGB0_RDCLI5__OSD_LIMITER_ENABLE__SHIFT 0x19 14195c1f7aaSFeifei Xu #define DAGB0_RDCLI5__MAX_OSD__SHIFT 0x1a 14295c1f7aaSFeifei Xu #define DAGB0_RDCLI5__VIRT_CHAN_MASK 0x00000007L 14395c1f7aaSFeifei Xu #define DAGB0_RDCLI5__CHECK_TLB_CREDIT_MASK 0x00000008L 14495c1f7aaSFeifei Xu #define DAGB0_RDCLI5__URG_HIGH_MASK 0x000000F0L 14595c1f7aaSFeifei Xu #define DAGB0_RDCLI5__URG_LOW_MASK 0x00000F00L 14695c1f7aaSFeifei Xu #define DAGB0_RDCLI5__MAX_BW_ENABLE_MASK 0x00001000L 14795c1f7aaSFeifei Xu #define DAGB0_RDCLI5__MAX_BW_MASK 0x001FE000L 14895c1f7aaSFeifei Xu #define DAGB0_RDCLI5__MIN_BW_ENABLE_MASK 0x00200000L 14995c1f7aaSFeifei Xu #define DAGB0_RDCLI5__MIN_BW_MASK 0x01C00000L 15095c1f7aaSFeifei Xu #define DAGB0_RDCLI5__OSD_LIMITER_ENABLE_MASK 0x02000000L 15195c1f7aaSFeifei Xu #define DAGB0_RDCLI5__MAX_OSD_MASK 0xFC000000L 15295c1f7aaSFeifei Xu //DAGB0_RDCLI6 15395c1f7aaSFeifei Xu #define DAGB0_RDCLI6__VIRT_CHAN__SHIFT 0x0 15495c1f7aaSFeifei Xu #define DAGB0_RDCLI6__CHECK_TLB_CREDIT__SHIFT 0x3 15595c1f7aaSFeifei Xu #define DAGB0_RDCLI6__URG_HIGH__SHIFT 0x4 15695c1f7aaSFeifei Xu #define DAGB0_RDCLI6__URG_LOW__SHIFT 0x8 15795c1f7aaSFeifei Xu #define DAGB0_RDCLI6__MAX_BW_ENABLE__SHIFT 0xc 15895c1f7aaSFeifei Xu #define DAGB0_RDCLI6__MAX_BW__SHIFT 0xd 15995c1f7aaSFeifei Xu #define DAGB0_RDCLI6__MIN_BW_ENABLE__SHIFT 0x15 16095c1f7aaSFeifei Xu #define DAGB0_RDCLI6__MIN_BW__SHIFT 0x16 16195c1f7aaSFeifei Xu #define DAGB0_RDCLI6__OSD_LIMITER_ENABLE__SHIFT 0x19 16295c1f7aaSFeifei Xu #define DAGB0_RDCLI6__MAX_OSD__SHIFT 0x1a 16395c1f7aaSFeifei Xu #define DAGB0_RDCLI6__VIRT_CHAN_MASK 0x00000007L 16495c1f7aaSFeifei Xu #define DAGB0_RDCLI6__CHECK_TLB_CREDIT_MASK 0x00000008L 16595c1f7aaSFeifei Xu #define DAGB0_RDCLI6__URG_HIGH_MASK 0x000000F0L 16695c1f7aaSFeifei Xu #define DAGB0_RDCLI6__URG_LOW_MASK 0x00000F00L 16795c1f7aaSFeifei Xu #define DAGB0_RDCLI6__MAX_BW_ENABLE_MASK 0x00001000L 16895c1f7aaSFeifei Xu #define DAGB0_RDCLI6__MAX_BW_MASK 0x001FE000L 16995c1f7aaSFeifei Xu #define DAGB0_RDCLI6__MIN_BW_ENABLE_MASK 0x00200000L 17095c1f7aaSFeifei Xu #define DAGB0_RDCLI6__MIN_BW_MASK 0x01C00000L 17195c1f7aaSFeifei Xu #define DAGB0_RDCLI6__OSD_LIMITER_ENABLE_MASK 0x02000000L 17295c1f7aaSFeifei Xu #define DAGB0_RDCLI6__MAX_OSD_MASK 0xFC000000L 17395c1f7aaSFeifei Xu //DAGB0_RDCLI7 17495c1f7aaSFeifei Xu #define DAGB0_RDCLI7__VIRT_CHAN__SHIFT 0x0 17595c1f7aaSFeifei Xu #define DAGB0_RDCLI7__CHECK_TLB_CREDIT__SHIFT 0x3 17695c1f7aaSFeifei Xu #define DAGB0_RDCLI7__URG_HIGH__SHIFT 0x4 17795c1f7aaSFeifei Xu #define DAGB0_RDCLI7__URG_LOW__SHIFT 0x8 17895c1f7aaSFeifei Xu #define DAGB0_RDCLI7__MAX_BW_ENABLE__SHIFT 0xc 17995c1f7aaSFeifei Xu #define DAGB0_RDCLI7__MAX_BW__SHIFT 0xd 18095c1f7aaSFeifei Xu #define DAGB0_RDCLI7__MIN_BW_ENABLE__SHIFT 0x15 18195c1f7aaSFeifei Xu #define DAGB0_RDCLI7__MIN_BW__SHIFT 0x16 18295c1f7aaSFeifei Xu #define DAGB0_RDCLI7__OSD_LIMITER_ENABLE__SHIFT 0x19 18395c1f7aaSFeifei Xu #define DAGB0_RDCLI7__MAX_OSD__SHIFT 0x1a 18495c1f7aaSFeifei Xu #define DAGB0_RDCLI7__VIRT_CHAN_MASK 0x00000007L 18595c1f7aaSFeifei Xu #define DAGB0_RDCLI7__CHECK_TLB_CREDIT_MASK 0x00000008L 18695c1f7aaSFeifei Xu #define DAGB0_RDCLI7__URG_HIGH_MASK 0x000000F0L 18795c1f7aaSFeifei Xu #define DAGB0_RDCLI7__URG_LOW_MASK 0x00000F00L 18895c1f7aaSFeifei Xu #define DAGB0_RDCLI7__MAX_BW_ENABLE_MASK 0x00001000L 18995c1f7aaSFeifei Xu #define DAGB0_RDCLI7__MAX_BW_MASK 0x001FE000L 19095c1f7aaSFeifei Xu #define DAGB0_RDCLI7__MIN_BW_ENABLE_MASK 0x00200000L 19195c1f7aaSFeifei Xu #define DAGB0_RDCLI7__MIN_BW_MASK 0x01C00000L 19295c1f7aaSFeifei Xu #define DAGB0_RDCLI7__OSD_LIMITER_ENABLE_MASK 0x02000000L 19395c1f7aaSFeifei Xu #define DAGB0_RDCLI7__MAX_OSD_MASK 0xFC000000L 19495c1f7aaSFeifei Xu //DAGB0_RDCLI8 19595c1f7aaSFeifei Xu #define DAGB0_RDCLI8__VIRT_CHAN__SHIFT 0x0 19695c1f7aaSFeifei Xu #define DAGB0_RDCLI8__CHECK_TLB_CREDIT__SHIFT 0x3 19795c1f7aaSFeifei Xu #define DAGB0_RDCLI8__URG_HIGH__SHIFT 0x4 19895c1f7aaSFeifei Xu #define DAGB0_RDCLI8__URG_LOW__SHIFT 0x8 19995c1f7aaSFeifei Xu #define DAGB0_RDCLI8__MAX_BW_ENABLE__SHIFT 0xc 20095c1f7aaSFeifei Xu #define DAGB0_RDCLI8__MAX_BW__SHIFT 0xd 20195c1f7aaSFeifei Xu #define DAGB0_RDCLI8__MIN_BW_ENABLE__SHIFT 0x15 20295c1f7aaSFeifei Xu #define DAGB0_RDCLI8__MIN_BW__SHIFT 0x16 20395c1f7aaSFeifei Xu #define DAGB0_RDCLI8__OSD_LIMITER_ENABLE__SHIFT 0x19 20495c1f7aaSFeifei Xu #define DAGB0_RDCLI8__MAX_OSD__SHIFT 0x1a 20595c1f7aaSFeifei Xu #define DAGB0_RDCLI8__VIRT_CHAN_MASK 0x00000007L 20695c1f7aaSFeifei Xu #define DAGB0_RDCLI8__CHECK_TLB_CREDIT_MASK 0x00000008L 20795c1f7aaSFeifei Xu #define DAGB0_RDCLI8__URG_HIGH_MASK 0x000000F0L 20895c1f7aaSFeifei Xu #define DAGB0_RDCLI8__URG_LOW_MASK 0x00000F00L 20995c1f7aaSFeifei Xu #define DAGB0_RDCLI8__MAX_BW_ENABLE_MASK 0x00001000L 21095c1f7aaSFeifei Xu #define DAGB0_RDCLI8__MAX_BW_MASK 0x001FE000L 21195c1f7aaSFeifei Xu #define DAGB0_RDCLI8__MIN_BW_ENABLE_MASK 0x00200000L 21295c1f7aaSFeifei Xu #define DAGB0_RDCLI8__MIN_BW_MASK 0x01C00000L 21395c1f7aaSFeifei Xu #define DAGB0_RDCLI8__OSD_LIMITER_ENABLE_MASK 0x02000000L 21495c1f7aaSFeifei Xu #define DAGB0_RDCLI8__MAX_OSD_MASK 0xFC000000L 21595c1f7aaSFeifei Xu //DAGB0_RDCLI9 21695c1f7aaSFeifei Xu #define DAGB0_RDCLI9__VIRT_CHAN__SHIFT 0x0 21795c1f7aaSFeifei Xu #define DAGB0_RDCLI9__CHECK_TLB_CREDIT__SHIFT 0x3 21895c1f7aaSFeifei Xu #define DAGB0_RDCLI9__URG_HIGH__SHIFT 0x4 21995c1f7aaSFeifei Xu #define DAGB0_RDCLI9__URG_LOW__SHIFT 0x8 22095c1f7aaSFeifei Xu #define DAGB0_RDCLI9__MAX_BW_ENABLE__SHIFT 0xc 22195c1f7aaSFeifei Xu #define DAGB0_RDCLI9__MAX_BW__SHIFT 0xd 22295c1f7aaSFeifei Xu #define DAGB0_RDCLI9__MIN_BW_ENABLE__SHIFT 0x15 22395c1f7aaSFeifei Xu #define DAGB0_RDCLI9__MIN_BW__SHIFT 0x16 22495c1f7aaSFeifei Xu #define DAGB0_RDCLI9__OSD_LIMITER_ENABLE__SHIFT 0x19 22595c1f7aaSFeifei Xu #define DAGB0_RDCLI9__MAX_OSD__SHIFT 0x1a 22695c1f7aaSFeifei Xu #define DAGB0_RDCLI9__VIRT_CHAN_MASK 0x00000007L 22795c1f7aaSFeifei Xu #define DAGB0_RDCLI9__CHECK_TLB_CREDIT_MASK 0x00000008L 22895c1f7aaSFeifei Xu #define DAGB0_RDCLI9__URG_HIGH_MASK 0x000000F0L 22995c1f7aaSFeifei Xu #define DAGB0_RDCLI9__URG_LOW_MASK 0x00000F00L 23095c1f7aaSFeifei Xu #define DAGB0_RDCLI9__MAX_BW_ENABLE_MASK 0x00001000L 23195c1f7aaSFeifei Xu #define DAGB0_RDCLI9__MAX_BW_MASK 0x001FE000L 23295c1f7aaSFeifei Xu #define DAGB0_RDCLI9__MIN_BW_ENABLE_MASK 0x00200000L 23395c1f7aaSFeifei Xu #define DAGB0_RDCLI9__MIN_BW_MASK 0x01C00000L 23495c1f7aaSFeifei Xu #define DAGB0_RDCLI9__OSD_LIMITER_ENABLE_MASK 0x02000000L 23595c1f7aaSFeifei Xu #define DAGB0_RDCLI9__MAX_OSD_MASK 0xFC000000L 23695c1f7aaSFeifei Xu //DAGB0_RDCLI10 23795c1f7aaSFeifei Xu #define DAGB0_RDCLI10__VIRT_CHAN__SHIFT 0x0 23895c1f7aaSFeifei Xu #define DAGB0_RDCLI10__CHECK_TLB_CREDIT__SHIFT 0x3 23995c1f7aaSFeifei Xu #define DAGB0_RDCLI10__URG_HIGH__SHIFT 0x4 24095c1f7aaSFeifei Xu #define DAGB0_RDCLI10__URG_LOW__SHIFT 0x8 24195c1f7aaSFeifei Xu #define DAGB0_RDCLI10__MAX_BW_ENABLE__SHIFT 0xc 24295c1f7aaSFeifei Xu #define DAGB0_RDCLI10__MAX_BW__SHIFT 0xd 24395c1f7aaSFeifei Xu #define DAGB0_RDCLI10__MIN_BW_ENABLE__SHIFT 0x15 24495c1f7aaSFeifei Xu #define DAGB0_RDCLI10__MIN_BW__SHIFT 0x16 24595c1f7aaSFeifei Xu #define DAGB0_RDCLI10__OSD_LIMITER_ENABLE__SHIFT 0x19 24695c1f7aaSFeifei Xu #define DAGB0_RDCLI10__MAX_OSD__SHIFT 0x1a 24795c1f7aaSFeifei Xu #define DAGB0_RDCLI10__VIRT_CHAN_MASK 0x00000007L 24895c1f7aaSFeifei Xu #define DAGB0_RDCLI10__CHECK_TLB_CREDIT_MASK 0x00000008L 24995c1f7aaSFeifei Xu #define DAGB0_RDCLI10__URG_HIGH_MASK 0x000000F0L 25095c1f7aaSFeifei Xu #define DAGB0_RDCLI10__URG_LOW_MASK 0x00000F00L 25195c1f7aaSFeifei Xu #define DAGB0_RDCLI10__MAX_BW_ENABLE_MASK 0x00001000L 25295c1f7aaSFeifei Xu #define DAGB0_RDCLI10__MAX_BW_MASK 0x001FE000L 25395c1f7aaSFeifei Xu #define DAGB0_RDCLI10__MIN_BW_ENABLE_MASK 0x00200000L 25495c1f7aaSFeifei Xu #define DAGB0_RDCLI10__MIN_BW_MASK 0x01C00000L 25595c1f7aaSFeifei Xu #define DAGB0_RDCLI10__OSD_LIMITER_ENABLE_MASK 0x02000000L 25695c1f7aaSFeifei Xu #define DAGB0_RDCLI10__MAX_OSD_MASK 0xFC000000L 25795c1f7aaSFeifei Xu //DAGB0_RDCLI11 25895c1f7aaSFeifei Xu #define DAGB0_RDCLI11__VIRT_CHAN__SHIFT 0x0 25995c1f7aaSFeifei Xu #define DAGB0_RDCLI11__CHECK_TLB_CREDIT__SHIFT 0x3 26095c1f7aaSFeifei Xu #define DAGB0_RDCLI11__URG_HIGH__SHIFT 0x4 26195c1f7aaSFeifei Xu #define DAGB0_RDCLI11__URG_LOW__SHIFT 0x8 26295c1f7aaSFeifei Xu #define DAGB0_RDCLI11__MAX_BW_ENABLE__SHIFT 0xc 26395c1f7aaSFeifei Xu #define DAGB0_RDCLI11__MAX_BW__SHIFT 0xd 26495c1f7aaSFeifei Xu #define DAGB0_RDCLI11__MIN_BW_ENABLE__SHIFT 0x15 26595c1f7aaSFeifei Xu #define DAGB0_RDCLI11__MIN_BW__SHIFT 0x16 26695c1f7aaSFeifei Xu #define DAGB0_RDCLI11__OSD_LIMITER_ENABLE__SHIFT 0x19 26795c1f7aaSFeifei Xu #define DAGB0_RDCLI11__MAX_OSD__SHIFT 0x1a 26895c1f7aaSFeifei Xu #define DAGB0_RDCLI11__VIRT_CHAN_MASK 0x00000007L 26995c1f7aaSFeifei Xu #define DAGB0_RDCLI11__CHECK_TLB_CREDIT_MASK 0x00000008L 27095c1f7aaSFeifei Xu #define DAGB0_RDCLI11__URG_HIGH_MASK 0x000000F0L 27195c1f7aaSFeifei Xu #define DAGB0_RDCLI11__URG_LOW_MASK 0x00000F00L 27295c1f7aaSFeifei Xu #define DAGB0_RDCLI11__MAX_BW_ENABLE_MASK 0x00001000L 27395c1f7aaSFeifei Xu #define DAGB0_RDCLI11__MAX_BW_MASK 0x001FE000L 27495c1f7aaSFeifei Xu #define DAGB0_RDCLI11__MIN_BW_ENABLE_MASK 0x00200000L 27595c1f7aaSFeifei Xu #define DAGB0_RDCLI11__MIN_BW_MASK 0x01C00000L 27695c1f7aaSFeifei Xu #define DAGB0_RDCLI11__OSD_LIMITER_ENABLE_MASK 0x02000000L 27795c1f7aaSFeifei Xu #define DAGB0_RDCLI11__MAX_OSD_MASK 0xFC000000L 27895c1f7aaSFeifei Xu //DAGB0_RDCLI12 27995c1f7aaSFeifei Xu #define DAGB0_RDCLI12__VIRT_CHAN__SHIFT 0x0 28095c1f7aaSFeifei Xu #define DAGB0_RDCLI12__CHECK_TLB_CREDIT__SHIFT 0x3 28195c1f7aaSFeifei Xu #define DAGB0_RDCLI12__URG_HIGH__SHIFT 0x4 28295c1f7aaSFeifei Xu #define DAGB0_RDCLI12__URG_LOW__SHIFT 0x8 28395c1f7aaSFeifei Xu #define DAGB0_RDCLI12__MAX_BW_ENABLE__SHIFT 0xc 28495c1f7aaSFeifei Xu #define DAGB0_RDCLI12__MAX_BW__SHIFT 0xd 28595c1f7aaSFeifei Xu #define DAGB0_RDCLI12__MIN_BW_ENABLE__SHIFT 0x15 28695c1f7aaSFeifei Xu #define DAGB0_RDCLI12__MIN_BW__SHIFT 0x16 28795c1f7aaSFeifei Xu #define DAGB0_RDCLI12__OSD_LIMITER_ENABLE__SHIFT 0x19 28895c1f7aaSFeifei Xu #define DAGB0_RDCLI12__MAX_OSD__SHIFT 0x1a 28995c1f7aaSFeifei Xu #define DAGB0_RDCLI12__VIRT_CHAN_MASK 0x00000007L 29095c1f7aaSFeifei Xu #define DAGB0_RDCLI12__CHECK_TLB_CREDIT_MASK 0x00000008L 29195c1f7aaSFeifei Xu #define DAGB0_RDCLI12__URG_HIGH_MASK 0x000000F0L 29295c1f7aaSFeifei Xu #define DAGB0_RDCLI12__URG_LOW_MASK 0x00000F00L 29395c1f7aaSFeifei Xu #define DAGB0_RDCLI12__MAX_BW_ENABLE_MASK 0x00001000L 29495c1f7aaSFeifei Xu #define DAGB0_RDCLI12__MAX_BW_MASK 0x001FE000L 29595c1f7aaSFeifei Xu #define DAGB0_RDCLI12__MIN_BW_ENABLE_MASK 0x00200000L 29695c1f7aaSFeifei Xu #define DAGB0_RDCLI12__MIN_BW_MASK 0x01C00000L 29795c1f7aaSFeifei Xu #define DAGB0_RDCLI12__OSD_LIMITER_ENABLE_MASK 0x02000000L 29895c1f7aaSFeifei Xu #define DAGB0_RDCLI12__MAX_OSD_MASK 0xFC000000L 29995c1f7aaSFeifei Xu //DAGB0_RDCLI13 30095c1f7aaSFeifei Xu #define DAGB0_RDCLI13__VIRT_CHAN__SHIFT 0x0 30195c1f7aaSFeifei Xu #define DAGB0_RDCLI13__CHECK_TLB_CREDIT__SHIFT 0x3 30295c1f7aaSFeifei Xu #define DAGB0_RDCLI13__URG_HIGH__SHIFT 0x4 30395c1f7aaSFeifei Xu #define DAGB0_RDCLI13__URG_LOW__SHIFT 0x8 30495c1f7aaSFeifei Xu #define DAGB0_RDCLI13__MAX_BW_ENABLE__SHIFT 0xc 30595c1f7aaSFeifei Xu #define DAGB0_RDCLI13__MAX_BW__SHIFT 0xd 30695c1f7aaSFeifei Xu #define DAGB0_RDCLI13__MIN_BW_ENABLE__SHIFT 0x15 30795c1f7aaSFeifei Xu #define DAGB0_RDCLI13__MIN_BW__SHIFT 0x16 30895c1f7aaSFeifei Xu #define DAGB0_RDCLI13__OSD_LIMITER_ENABLE__SHIFT 0x19 30995c1f7aaSFeifei Xu #define DAGB0_RDCLI13__MAX_OSD__SHIFT 0x1a 31095c1f7aaSFeifei Xu #define DAGB0_RDCLI13__VIRT_CHAN_MASK 0x00000007L 31195c1f7aaSFeifei Xu #define DAGB0_RDCLI13__CHECK_TLB_CREDIT_MASK 0x00000008L 31295c1f7aaSFeifei Xu #define DAGB0_RDCLI13__URG_HIGH_MASK 0x000000F0L 31395c1f7aaSFeifei Xu #define DAGB0_RDCLI13__URG_LOW_MASK 0x00000F00L 31495c1f7aaSFeifei Xu #define DAGB0_RDCLI13__MAX_BW_ENABLE_MASK 0x00001000L 31595c1f7aaSFeifei Xu #define DAGB0_RDCLI13__MAX_BW_MASK 0x001FE000L 31695c1f7aaSFeifei Xu #define DAGB0_RDCLI13__MIN_BW_ENABLE_MASK 0x00200000L 31795c1f7aaSFeifei Xu #define DAGB0_RDCLI13__MIN_BW_MASK 0x01C00000L 31895c1f7aaSFeifei Xu #define DAGB0_RDCLI13__OSD_LIMITER_ENABLE_MASK 0x02000000L 31995c1f7aaSFeifei Xu #define DAGB0_RDCLI13__MAX_OSD_MASK 0xFC000000L 32095c1f7aaSFeifei Xu //DAGB0_RDCLI14 32195c1f7aaSFeifei Xu #define DAGB0_RDCLI14__VIRT_CHAN__SHIFT 0x0 32295c1f7aaSFeifei Xu #define DAGB0_RDCLI14__CHECK_TLB_CREDIT__SHIFT 0x3 32395c1f7aaSFeifei Xu #define DAGB0_RDCLI14__URG_HIGH__SHIFT 0x4 32495c1f7aaSFeifei Xu #define DAGB0_RDCLI14__URG_LOW__SHIFT 0x8 32595c1f7aaSFeifei Xu #define DAGB0_RDCLI14__MAX_BW_ENABLE__SHIFT 0xc 32695c1f7aaSFeifei Xu #define DAGB0_RDCLI14__MAX_BW__SHIFT 0xd 32795c1f7aaSFeifei Xu #define DAGB0_RDCLI14__MIN_BW_ENABLE__SHIFT 0x15 32895c1f7aaSFeifei Xu #define DAGB0_RDCLI14__MIN_BW__SHIFT 0x16 32995c1f7aaSFeifei Xu #define DAGB0_RDCLI14__OSD_LIMITER_ENABLE__SHIFT 0x19 33095c1f7aaSFeifei Xu #define DAGB0_RDCLI14__MAX_OSD__SHIFT 0x1a 33195c1f7aaSFeifei Xu #define DAGB0_RDCLI14__VIRT_CHAN_MASK 0x00000007L 33295c1f7aaSFeifei Xu #define DAGB0_RDCLI14__CHECK_TLB_CREDIT_MASK 0x00000008L 33395c1f7aaSFeifei Xu #define DAGB0_RDCLI14__URG_HIGH_MASK 0x000000F0L 33495c1f7aaSFeifei Xu #define DAGB0_RDCLI14__URG_LOW_MASK 0x00000F00L 33595c1f7aaSFeifei Xu #define DAGB0_RDCLI14__MAX_BW_ENABLE_MASK 0x00001000L 33695c1f7aaSFeifei Xu #define DAGB0_RDCLI14__MAX_BW_MASK 0x001FE000L 33795c1f7aaSFeifei Xu #define DAGB0_RDCLI14__MIN_BW_ENABLE_MASK 0x00200000L 33895c1f7aaSFeifei Xu #define DAGB0_RDCLI14__MIN_BW_MASK 0x01C00000L 33995c1f7aaSFeifei Xu #define DAGB0_RDCLI14__OSD_LIMITER_ENABLE_MASK 0x02000000L 34095c1f7aaSFeifei Xu #define DAGB0_RDCLI14__MAX_OSD_MASK 0xFC000000L 34195c1f7aaSFeifei Xu //DAGB0_RDCLI15 34295c1f7aaSFeifei Xu #define DAGB0_RDCLI15__VIRT_CHAN__SHIFT 0x0 34395c1f7aaSFeifei Xu #define DAGB0_RDCLI15__CHECK_TLB_CREDIT__SHIFT 0x3 34495c1f7aaSFeifei Xu #define DAGB0_RDCLI15__URG_HIGH__SHIFT 0x4 34595c1f7aaSFeifei Xu #define DAGB0_RDCLI15__URG_LOW__SHIFT 0x8 34695c1f7aaSFeifei Xu #define DAGB0_RDCLI15__MAX_BW_ENABLE__SHIFT 0xc 34795c1f7aaSFeifei Xu #define DAGB0_RDCLI15__MAX_BW__SHIFT 0xd 34895c1f7aaSFeifei Xu #define DAGB0_RDCLI15__MIN_BW_ENABLE__SHIFT 0x15 34995c1f7aaSFeifei Xu #define DAGB0_RDCLI15__MIN_BW__SHIFT 0x16 35095c1f7aaSFeifei Xu #define DAGB0_RDCLI15__OSD_LIMITER_ENABLE__SHIFT 0x19 35195c1f7aaSFeifei Xu #define DAGB0_RDCLI15__MAX_OSD__SHIFT 0x1a 35295c1f7aaSFeifei Xu #define DAGB0_RDCLI15__VIRT_CHAN_MASK 0x00000007L 35395c1f7aaSFeifei Xu #define DAGB0_RDCLI15__CHECK_TLB_CREDIT_MASK 0x00000008L 35495c1f7aaSFeifei Xu #define DAGB0_RDCLI15__URG_HIGH_MASK 0x000000F0L 35595c1f7aaSFeifei Xu #define DAGB0_RDCLI15__URG_LOW_MASK 0x00000F00L 35695c1f7aaSFeifei Xu #define DAGB0_RDCLI15__MAX_BW_ENABLE_MASK 0x00001000L 35795c1f7aaSFeifei Xu #define DAGB0_RDCLI15__MAX_BW_MASK 0x001FE000L 35895c1f7aaSFeifei Xu #define DAGB0_RDCLI15__MIN_BW_ENABLE_MASK 0x00200000L 35995c1f7aaSFeifei Xu #define DAGB0_RDCLI15__MIN_BW_MASK 0x01C00000L 36095c1f7aaSFeifei Xu #define DAGB0_RDCLI15__OSD_LIMITER_ENABLE_MASK 0x02000000L 36195c1f7aaSFeifei Xu #define DAGB0_RDCLI15__MAX_OSD_MASK 0xFC000000L 36295c1f7aaSFeifei Xu //DAGB0_RDCLI16 36395c1f7aaSFeifei Xu #define DAGB0_RDCLI16__VIRT_CHAN__SHIFT 0x0 36495c1f7aaSFeifei Xu #define DAGB0_RDCLI16__CHECK_TLB_CREDIT__SHIFT 0x3 36595c1f7aaSFeifei Xu #define DAGB0_RDCLI16__URG_HIGH__SHIFT 0x4 36695c1f7aaSFeifei Xu #define DAGB0_RDCLI16__URG_LOW__SHIFT 0x8 36795c1f7aaSFeifei Xu #define DAGB0_RDCLI16__MAX_BW_ENABLE__SHIFT 0xc 36895c1f7aaSFeifei Xu #define DAGB0_RDCLI16__MAX_BW__SHIFT 0xd 36995c1f7aaSFeifei Xu #define DAGB0_RDCLI16__MIN_BW_ENABLE__SHIFT 0x15 37095c1f7aaSFeifei Xu #define DAGB0_RDCLI16__MIN_BW__SHIFT 0x16 37195c1f7aaSFeifei Xu #define DAGB0_RDCLI16__OSD_LIMITER_ENABLE__SHIFT 0x19 37295c1f7aaSFeifei Xu #define DAGB0_RDCLI16__MAX_OSD__SHIFT 0x1a 37395c1f7aaSFeifei Xu #define DAGB0_RDCLI16__VIRT_CHAN_MASK 0x00000007L 37495c1f7aaSFeifei Xu #define DAGB0_RDCLI16__CHECK_TLB_CREDIT_MASK 0x00000008L 37595c1f7aaSFeifei Xu #define DAGB0_RDCLI16__URG_HIGH_MASK 0x000000F0L 37695c1f7aaSFeifei Xu #define DAGB0_RDCLI16__URG_LOW_MASK 0x00000F00L 37795c1f7aaSFeifei Xu #define DAGB0_RDCLI16__MAX_BW_ENABLE_MASK 0x00001000L 37895c1f7aaSFeifei Xu #define DAGB0_RDCLI16__MAX_BW_MASK 0x001FE000L 37995c1f7aaSFeifei Xu #define DAGB0_RDCLI16__MIN_BW_ENABLE_MASK 0x00200000L 38095c1f7aaSFeifei Xu #define DAGB0_RDCLI16__MIN_BW_MASK 0x01C00000L 38195c1f7aaSFeifei Xu #define DAGB0_RDCLI16__OSD_LIMITER_ENABLE_MASK 0x02000000L 38295c1f7aaSFeifei Xu #define DAGB0_RDCLI16__MAX_OSD_MASK 0xFC000000L 38395c1f7aaSFeifei Xu //DAGB0_RDCLI17 38495c1f7aaSFeifei Xu #define DAGB0_RDCLI17__VIRT_CHAN__SHIFT 0x0 38595c1f7aaSFeifei Xu #define DAGB0_RDCLI17__CHECK_TLB_CREDIT__SHIFT 0x3 38695c1f7aaSFeifei Xu #define DAGB0_RDCLI17__URG_HIGH__SHIFT 0x4 38795c1f7aaSFeifei Xu #define DAGB0_RDCLI17__URG_LOW__SHIFT 0x8 38895c1f7aaSFeifei Xu #define DAGB0_RDCLI17__MAX_BW_ENABLE__SHIFT 0xc 38995c1f7aaSFeifei Xu #define DAGB0_RDCLI17__MAX_BW__SHIFT 0xd 39095c1f7aaSFeifei Xu #define DAGB0_RDCLI17__MIN_BW_ENABLE__SHIFT 0x15 39195c1f7aaSFeifei Xu #define DAGB0_RDCLI17__MIN_BW__SHIFT 0x16 39295c1f7aaSFeifei Xu #define DAGB0_RDCLI17__OSD_LIMITER_ENABLE__SHIFT 0x19 39395c1f7aaSFeifei Xu #define DAGB0_RDCLI17__MAX_OSD__SHIFT 0x1a 39495c1f7aaSFeifei Xu #define DAGB0_RDCLI17__VIRT_CHAN_MASK 0x00000007L 39595c1f7aaSFeifei Xu #define DAGB0_RDCLI17__CHECK_TLB_CREDIT_MASK 0x00000008L 39695c1f7aaSFeifei Xu #define DAGB0_RDCLI17__URG_HIGH_MASK 0x000000F0L 39795c1f7aaSFeifei Xu #define DAGB0_RDCLI17__URG_LOW_MASK 0x00000F00L 39895c1f7aaSFeifei Xu #define DAGB0_RDCLI17__MAX_BW_ENABLE_MASK 0x00001000L 39995c1f7aaSFeifei Xu #define DAGB0_RDCLI17__MAX_BW_MASK 0x001FE000L 40095c1f7aaSFeifei Xu #define DAGB0_RDCLI17__MIN_BW_ENABLE_MASK 0x00200000L 40195c1f7aaSFeifei Xu #define DAGB0_RDCLI17__MIN_BW_MASK 0x01C00000L 40295c1f7aaSFeifei Xu #define DAGB0_RDCLI17__OSD_LIMITER_ENABLE_MASK 0x02000000L 40395c1f7aaSFeifei Xu #define DAGB0_RDCLI17__MAX_OSD_MASK 0xFC000000L 40495c1f7aaSFeifei Xu //DAGB0_RDCLI18 40595c1f7aaSFeifei Xu #define DAGB0_RDCLI18__VIRT_CHAN__SHIFT 0x0 40695c1f7aaSFeifei Xu #define DAGB0_RDCLI18__CHECK_TLB_CREDIT__SHIFT 0x3 40795c1f7aaSFeifei Xu #define DAGB0_RDCLI18__URG_HIGH__SHIFT 0x4 40895c1f7aaSFeifei Xu #define DAGB0_RDCLI18__URG_LOW__SHIFT 0x8 40995c1f7aaSFeifei Xu #define DAGB0_RDCLI18__MAX_BW_ENABLE__SHIFT 0xc 41095c1f7aaSFeifei Xu #define DAGB0_RDCLI18__MAX_BW__SHIFT 0xd 41195c1f7aaSFeifei Xu #define DAGB0_RDCLI18__MIN_BW_ENABLE__SHIFT 0x15 41295c1f7aaSFeifei Xu #define DAGB0_RDCLI18__MIN_BW__SHIFT 0x16 41395c1f7aaSFeifei Xu #define DAGB0_RDCLI18__OSD_LIMITER_ENABLE__SHIFT 0x19 41495c1f7aaSFeifei Xu #define DAGB0_RDCLI18__MAX_OSD__SHIFT 0x1a 41595c1f7aaSFeifei Xu #define DAGB0_RDCLI18__VIRT_CHAN_MASK 0x00000007L 41695c1f7aaSFeifei Xu #define DAGB0_RDCLI18__CHECK_TLB_CREDIT_MASK 0x00000008L 41795c1f7aaSFeifei Xu #define DAGB0_RDCLI18__URG_HIGH_MASK 0x000000F0L 41895c1f7aaSFeifei Xu #define DAGB0_RDCLI18__URG_LOW_MASK 0x00000F00L 41995c1f7aaSFeifei Xu #define DAGB0_RDCLI18__MAX_BW_ENABLE_MASK 0x00001000L 42095c1f7aaSFeifei Xu #define DAGB0_RDCLI18__MAX_BW_MASK 0x001FE000L 42195c1f7aaSFeifei Xu #define DAGB0_RDCLI18__MIN_BW_ENABLE_MASK 0x00200000L 42295c1f7aaSFeifei Xu #define DAGB0_RDCLI18__MIN_BW_MASK 0x01C00000L 42395c1f7aaSFeifei Xu #define DAGB0_RDCLI18__OSD_LIMITER_ENABLE_MASK 0x02000000L 42495c1f7aaSFeifei Xu #define DAGB0_RDCLI18__MAX_OSD_MASK 0xFC000000L 42595c1f7aaSFeifei Xu //DAGB0_RDCLI19 42695c1f7aaSFeifei Xu #define DAGB0_RDCLI19__VIRT_CHAN__SHIFT 0x0 42795c1f7aaSFeifei Xu #define DAGB0_RDCLI19__CHECK_TLB_CREDIT__SHIFT 0x3 42895c1f7aaSFeifei Xu #define DAGB0_RDCLI19__URG_HIGH__SHIFT 0x4 42995c1f7aaSFeifei Xu #define DAGB0_RDCLI19__URG_LOW__SHIFT 0x8 43095c1f7aaSFeifei Xu #define DAGB0_RDCLI19__MAX_BW_ENABLE__SHIFT 0xc 43195c1f7aaSFeifei Xu #define DAGB0_RDCLI19__MAX_BW__SHIFT 0xd 43295c1f7aaSFeifei Xu #define DAGB0_RDCLI19__MIN_BW_ENABLE__SHIFT 0x15 43395c1f7aaSFeifei Xu #define DAGB0_RDCLI19__MIN_BW__SHIFT 0x16 43495c1f7aaSFeifei Xu #define DAGB0_RDCLI19__OSD_LIMITER_ENABLE__SHIFT 0x19 43595c1f7aaSFeifei Xu #define DAGB0_RDCLI19__MAX_OSD__SHIFT 0x1a 43695c1f7aaSFeifei Xu #define DAGB0_RDCLI19__VIRT_CHAN_MASK 0x00000007L 43795c1f7aaSFeifei Xu #define DAGB0_RDCLI19__CHECK_TLB_CREDIT_MASK 0x00000008L 43895c1f7aaSFeifei Xu #define DAGB0_RDCLI19__URG_HIGH_MASK 0x000000F0L 43995c1f7aaSFeifei Xu #define DAGB0_RDCLI19__URG_LOW_MASK 0x00000F00L 44095c1f7aaSFeifei Xu #define DAGB0_RDCLI19__MAX_BW_ENABLE_MASK 0x00001000L 44195c1f7aaSFeifei Xu #define DAGB0_RDCLI19__MAX_BW_MASK 0x001FE000L 44295c1f7aaSFeifei Xu #define DAGB0_RDCLI19__MIN_BW_ENABLE_MASK 0x00200000L 44395c1f7aaSFeifei Xu #define DAGB0_RDCLI19__MIN_BW_MASK 0x01C00000L 44495c1f7aaSFeifei Xu #define DAGB0_RDCLI19__OSD_LIMITER_ENABLE_MASK 0x02000000L 44595c1f7aaSFeifei Xu #define DAGB0_RDCLI19__MAX_OSD_MASK 0xFC000000L 44695c1f7aaSFeifei Xu //DAGB0_RDCLI20 44795c1f7aaSFeifei Xu #define DAGB0_RDCLI20__VIRT_CHAN__SHIFT 0x0 44895c1f7aaSFeifei Xu #define DAGB0_RDCLI20__CHECK_TLB_CREDIT__SHIFT 0x3 44995c1f7aaSFeifei Xu #define DAGB0_RDCLI20__URG_HIGH__SHIFT 0x4 45095c1f7aaSFeifei Xu #define DAGB0_RDCLI20__URG_LOW__SHIFT 0x8 45195c1f7aaSFeifei Xu #define DAGB0_RDCLI20__MAX_BW_ENABLE__SHIFT 0xc 45295c1f7aaSFeifei Xu #define DAGB0_RDCLI20__MAX_BW__SHIFT 0xd 45395c1f7aaSFeifei Xu #define DAGB0_RDCLI20__MIN_BW_ENABLE__SHIFT 0x15 45495c1f7aaSFeifei Xu #define DAGB0_RDCLI20__MIN_BW__SHIFT 0x16 45595c1f7aaSFeifei Xu #define DAGB0_RDCLI20__OSD_LIMITER_ENABLE__SHIFT 0x19 45695c1f7aaSFeifei Xu #define DAGB0_RDCLI20__MAX_OSD__SHIFT 0x1a 45795c1f7aaSFeifei Xu #define DAGB0_RDCLI20__VIRT_CHAN_MASK 0x00000007L 45895c1f7aaSFeifei Xu #define DAGB0_RDCLI20__CHECK_TLB_CREDIT_MASK 0x00000008L 45995c1f7aaSFeifei Xu #define DAGB0_RDCLI20__URG_HIGH_MASK 0x000000F0L 46095c1f7aaSFeifei Xu #define DAGB0_RDCLI20__URG_LOW_MASK 0x00000F00L 46195c1f7aaSFeifei Xu #define DAGB0_RDCLI20__MAX_BW_ENABLE_MASK 0x00001000L 46295c1f7aaSFeifei Xu #define DAGB0_RDCLI20__MAX_BW_MASK 0x001FE000L 46395c1f7aaSFeifei Xu #define DAGB0_RDCLI20__MIN_BW_ENABLE_MASK 0x00200000L 46495c1f7aaSFeifei Xu #define DAGB0_RDCLI20__MIN_BW_MASK 0x01C00000L 46595c1f7aaSFeifei Xu #define DAGB0_RDCLI20__OSD_LIMITER_ENABLE_MASK 0x02000000L 46695c1f7aaSFeifei Xu #define DAGB0_RDCLI20__MAX_OSD_MASK 0xFC000000L 46795c1f7aaSFeifei Xu //DAGB0_RDCLI21 46895c1f7aaSFeifei Xu #define DAGB0_RDCLI21__VIRT_CHAN__SHIFT 0x0 46995c1f7aaSFeifei Xu #define DAGB0_RDCLI21__CHECK_TLB_CREDIT__SHIFT 0x3 47095c1f7aaSFeifei Xu #define DAGB0_RDCLI21__URG_HIGH__SHIFT 0x4 47195c1f7aaSFeifei Xu #define DAGB0_RDCLI21__URG_LOW__SHIFT 0x8 47295c1f7aaSFeifei Xu #define DAGB0_RDCLI21__MAX_BW_ENABLE__SHIFT 0xc 47395c1f7aaSFeifei Xu #define DAGB0_RDCLI21__MAX_BW__SHIFT 0xd 47495c1f7aaSFeifei Xu #define DAGB0_RDCLI21__MIN_BW_ENABLE__SHIFT 0x15 47595c1f7aaSFeifei Xu #define DAGB0_RDCLI21__MIN_BW__SHIFT 0x16 47695c1f7aaSFeifei Xu #define DAGB0_RDCLI21__OSD_LIMITER_ENABLE__SHIFT 0x19 47795c1f7aaSFeifei Xu #define DAGB0_RDCLI21__MAX_OSD__SHIFT 0x1a 47895c1f7aaSFeifei Xu #define DAGB0_RDCLI21__VIRT_CHAN_MASK 0x00000007L 47995c1f7aaSFeifei Xu #define DAGB0_RDCLI21__CHECK_TLB_CREDIT_MASK 0x00000008L 48095c1f7aaSFeifei Xu #define DAGB0_RDCLI21__URG_HIGH_MASK 0x000000F0L 48195c1f7aaSFeifei Xu #define DAGB0_RDCLI21__URG_LOW_MASK 0x00000F00L 48295c1f7aaSFeifei Xu #define DAGB0_RDCLI21__MAX_BW_ENABLE_MASK 0x00001000L 48395c1f7aaSFeifei Xu #define DAGB0_RDCLI21__MAX_BW_MASK 0x001FE000L 48495c1f7aaSFeifei Xu #define DAGB0_RDCLI21__MIN_BW_ENABLE_MASK 0x00200000L 48595c1f7aaSFeifei Xu #define DAGB0_RDCLI21__MIN_BW_MASK 0x01C00000L 48695c1f7aaSFeifei Xu #define DAGB0_RDCLI21__OSD_LIMITER_ENABLE_MASK 0x02000000L 48795c1f7aaSFeifei Xu #define DAGB0_RDCLI21__MAX_OSD_MASK 0xFC000000L 48895c1f7aaSFeifei Xu //DAGB0_RDCLI22 48995c1f7aaSFeifei Xu #define DAGB0_RDCLI22__VIRT_CHAN__SHIFT 0x0 49095c1f7aaSFeifei Xu #define DAGB0_RDCLI22__CHECK_TLB_CREDIT__SHIFT 0x3 49195c1f7aaSFeifei Xu #define DAGB0_RDCLI22__URG_HIGH__SHIFT 0x4 49295c1f7aaSFeifei Xu #define DAGB0_RDCLI22__URG_LOW__SHIFT 0x8 49395c1f7aaSFeifei Xu #define DAGB0_RDCLI22__MAX_BW_ENABLE__SHIFT 0xc 49495c1f7aaSFeifei Xu #define DAGB0_RDCLI22__MAX_BW__SHIFT 0xd 49595c1f7aaSFeifei Xu #define DAGB0_RDCLI22__MIN_BW_ENABLE__SHIFT 0x15 49695c1f7aaSFeifei Xu #define DAGB0_RDCLI22__MIN_BW__SHIFT 0x16 49795c1f7aaSFeifei Xu #define DAGB0_RDCLI22__OSD_LIMITER_ENABLE__SHIFT 0x19 49895c1f7aaSFeifei Xu #define DAGB0_RDCLI22__MAX_OSD__SHIFT 0x1a 49995c1f7aaSFeifei Xu #define DAGB0_RDCLI22__VIRT_CHAN_MASK 0x00000007L 50095c1f7aaSFeifei Xu #define DAGB0_RDCLI22__CHECK_TLB_CREDIT_MASK 0x00000008L 50195c1f7aaSFeifei Xu #define DAGB0_RDCLI22__URG_HIGH_MASK 0x000000F0L 50295c1f7aaSFeifei Xu #define DAGB0_RDCLI22__URG_LOW_MASK 0x00000F00L 50395c1f7aaSFeifei Xu #define DAGB0_RDCLI22__MAX_BW_ENABLE_MASK 0x00001000L 50495c1f7aaSFeifei Xu #define DAGB0_RDCLI22__MAX_BW_MASK 0x001FE000L 50595c1f7aaSFeifei Xu #define DAGB0_RDCLI22__MIN_BW_ENABLE_MASK 0x00200000L 50695c1f7aaSFeifei Xu #define DAGB0_RDCLI22__MIN_BW_MASK 0x01C00000L 50795c1f7aaSFeifei Xu #define DAGB0_RDCLI22__OSD_LIMITER_ENABLE_MASK 0x02000000L 50895c1f7aaSFeifei Xu #define DAGB0_RDCLI22__MAX_OSD_MASK 0xFC000000L 50995c1f7aaSFeifei Xu //DAGB0_RDCLI23 51095c1f7aaSFeifei Xu #define DAGB0_RDCLI23__VIRT_CHAN__SHIFT 0x0 51195c1f7aaSFeifei Xu #define DAGB0_RDCLI23__CHECK_TLB_CREDIT__SHIFT 0x3 51295c1f7aaSFeifei Xu #define DAGB0_RDCLI23__URG_HIGH__SHIFT 0x4 51395c1f7aaSFeifei Xu #define DAGB0_RDCLI23__URG_LOW__SHIFT 0x8 51495c1f7aaSFeifei Xu #define DAGB0_RDCLI23__MAX_BW_ENABLE__SHIFT 0xc 51595c1f7aaSFeifei Xu #define DAGB0_RDCLI23__MAX_BW__SHIFT 0xd 51695c1f7aaSFeifei Xu #define DAGB0_RDCLI23__MIN_BW_ENABLE__SHIFT 0x15 51795c1f7aaSFeifei Xu #define DAGB0_RDCLI23__MIN_BW__SHIFT 0x16 51895c1f7aaSFeifei Xu #define DAGB0_RDCLI23__OSD_LIMITER_ENABLE__SHIFT 0x19 51995c1f7aaSFeifei Xu #define DAGB0_RDCLI23__MAX_OSD__SHIFT 0x1a 52095c1f7aaSFeifei Xu #define DAGB0_RDCLI23__VIRT_CHAN_MASK 0x00000007L 52195c1f7aaSFeifei Xu #define DAGB0_RDCLI23__CHECK_TLB_CREDIT_MASK 0x00000008L 52295c1f7aaSFeifei Xu #define DAGB0_RDCLI23__URG_HIGH_MASK 0x000000F0L 52395c1f7aaSFeifei Xu #define DAGB0_RDCLI23__URG_LOW_MASK 0x00000F00L 52495c1f7aaSFeifei Xu #define DAGB0_RDCLI23__MAX_BW_ENABLE_MASK 0x00001000L 52595c1f7aaSFeifei Xu #define DAGB0_RDCLI23__MAX_BW_MASK 0x001FE000L 52695c1f7aaSFeifei Xu #define DAGB0_RDCLI23__MIN_BW_ENABLE_MASK 0x00200000L 52795c1f7aaSFeifei Xu #define DAGB0_RDCLI23__MIN_BW_MASK 0x01C00000L 52895c1f7aaSFeifei Xu #define DAGB0_RDCLI23__OSD_LIMITER_ENABLE_MASK 0x02000000L 52995c1f7aaSFeifei Xu #define DAGB0_RDCLI23__MAX_OSD_MASK 0xFC000000L 53095c1f7aaSFeifei Xu //DAGB0_RDCLI24 53195c1f7aaSFeifei Xu #define DAGB0_RDCLI24__VIRT_CHAN__SHIFT 0x0 53295c1f7aaSFeifei Xu #define DAGB0_RDCLI24__CHECK_TLB_CREDIT__SHIFT 0x3 53395c1f7aaSFeifei Xu #define DAGB0_RDCLI24__URG_HIGH__SHIFT 0x4 53495c1f7aaSFeifei Xu #define DAGB0_RDCLI24__URG_LOW__SHIFT 0x8 53595c1f7aaSFeifei Xu #define DAGB0_RDCLI24__MAX_BW_ENABLE__SHIFT 0xc 53695c1f7aaSFeifei Xu #define DAGB0_RDCLI24__MAX_BW__SHIFT 0xd 53795c1f7aaSFeifei Xu #define DAGB0_RDCLI24__MIN_BW_ENABLE__SHIFT 0x15 53895c1f7aaSFeifei Xu #define DAGB0_RDCLI24__MIN_BW__SHIFT 0x16 53995c1f7aaSFeifei Xu #define DAGB0_RDCLI24__OSD_LIMITER_ENABLE__SHIFT 0x19 54095c1f7aaSFeifei Xu #define DAGB0_RDCLI24__MAX_OSD__SHIFT 0x1a 54195c1f7aaSFeifei Xu #define DAGB0_RDCLI24__VIRT_CHAN_MASK 0x00000007L 54295c1f7aaSFeifei Xu #define DAGB0_RDCLI24__CHECK_TLB_CREDIT_MASK 0x00000008L 54395c1f7aaSFeifei Xu #define DAGB0_RDCLI24__URG_HIGH_MASK 0x000000F0L 54495c1f7aaSFeifei Xu #define DAGB0_RDCLI24__URG_LOW_MASK 0x00000F00L 54595c1f7aaSFeifei Xu #define DAGB0_RDCLI24__MAX_BW_ENABLE_MASK 0x00001000L 54695c1f7aaSFeifei Xu #define DAGB0_RDCLI24__MAX_BW_MASK 0x001FE000L 54795c1f7aaSFeifei Xu #define DAGB0_RDCLI24__MIN_BW_ENABLE_MASK 0x00200000L 54895c1f7aaSFeifei Xu #define DAGB0_RDCLI24__MIN_BW_MASK 0x01C00000L 54995c1f7aaSFeifei Xu #define DAGB0_RDCLI24__OSD_LIMITER_ENABLE_MASK 0x02000000L 55095c1f7aaSFeifei Xu #define DAGB0_RDCLI24__MAX_OSD_MASK 0xFC000000L 55195c1f7aaSFeifei Xu //DAGB0_RDCLI25 55295c1f7aaSFeifei Xu #define DAGB0_RDCLI25__VIRT_CHAN__SHIFT 0x0 55395c1f7aaSFeifei Xu #define DAGB0_RDCLI25__CHECK_TLB_CREDIT__SHIFT 0x3 55495c1f7aaSFeifei Xu #define DAGB0_RDCLI25__URG_HIGH__SHIFT 0x4 55595c1f7aaSFeifei Xu #define DAGB0_RDCLI25__URG_LOW__SHIFT 0x8 55695c1f7aaSFeifei Xu #define DAGB0_RDCLI25__MAX_BW_ENABLE__SHIFT 0xc 55795c1f7aaSFeifei Xu #define DAGB0_RDCLI25__MAX_BW__SHIFT 0xd 55895c1f7aaSFeifei Xu #define DAGB0_RDCLI25__MIN_BW_ENABLE__SHIFT 0x15 55995c1f7aaSFeifei Xu #define DAGB0_RDCLI25__MIN_BW__SHIFT 0x16 56095c1f7aaSFeifei Xu #define DAGB0_RDCLI25__OSD_LIMITER_ENABLE__SHIFT 0x19 56195c1f7aaSFeifei Xu #define DAGB0_RDCLI25__MAX_OSD__SHIFT 0x1a 56295c1f7aaSFeifei Xu #define DAGB0_RDCLI25__VIRT_CHAN_MASK 0x00000007L 56395c1f7aaSFeifei Xu #define DAGB0_RDCLI25__CHECK_TLB_CREDIT_MASK 0x00000008L 56495c1f7aaSFeifei Xu #define DAGB0_RDCLI25__URG_HIGH_MASK 0x000000F0L 56595c1f7aaSFeifei Xu #define DAGB0_RDCLI25__URG_LOW_MASK 0x00000F00L 56695c1f7aaSFeifei Xu #define DAGB0_RDCLI25__MAX_BW_ENABLE_MASK 0x00001000L 56795c1f7aaSFeifei Xu #define DAGB0_RDCLI25__MAX_BW_MASK 0x001FE000L 56895c1f7aaSFeifei Xu #define DAGB0_RDCLI25__MIN_BW_ENABLE_MASK 0x00200000L 56995c1f7aaSFeifei Xu #define DAGB0_RDCLI25__MIN_BW_MASK 0x01C00000L 57095c1f7aaSFeifei Xu #define DAGB0_RDCLI25__OSD_LIMITER_ENABLE_MASK 0x02000000L 57195c1f7aaSFeifei Xu #define DAGB0_RDCLI25__MAX_OSD_MASK 0xFC000000L 57295c1f7aaSFeifei Xu //DAGB0_RDCLI26 57395c1f7aaSFeifei Xu #define DAGB0_RDCLI26__VIRT_CHAN__SHIFT 0x0 57495c1f7aaSFeifei Xu #define DAGB0_RDCLI26__CHECK_TLB_CREDIT__SHIFT 0x3 57595c1f7aaSFeifei Xu #define DAGB0_RDCLI26__URG_HIGH__SHIFT 0x4 57695c1f7aaSFeifei Xu #define DAGB0_RDCLI26__URG_LOW__SHIFT 0x8 57795c1f7aaSFeifei Xu #define DAGB0_RDCLI26__MAX_BW_ENABLE__SHIFT 0xc 57895c1f7aaSFeifei Xu #define DAGB0_RDCLI26__MAX_BW__SHIFT 0xd 57995c1f7aaSFeifei Xu #define DAGB0_RDCLI26__MIN_BW_ENABLE__SHIFT 0x15 58095c1f7aaSFeifei Xu #define DAGB0_RDCLI26__MIN_BW__SHIFT 0x16 58195c1f7aaSFeifei Xu #define DAGB0_RDCLI26__OSD_LIMITER_ENABLE__SHIFT 0x19 58295c1f7aaSFeifei Xu #define DAGB0_RDCLI26__MAX_OSD__SHIFT 0x1a 58395c1f7aaSFeifei Xu #define DAGB0_RDCLI26__VIRT_CHAN_MASK 0x00000007L 58495c1f7aaSFeifei Xu #define DAGB0_RDCLI26__CHECK_TLB_CREDIT_MASK 0x00000008L 58595c1f7aaSFeifei Xu #define DAGB0_RDCLI26__URG_HIGH_MASK 0x000000F0L 58695c1f7aaSFeifei Xu #define DAGB0_RDCLI26__URG_LOW_MASK 0x00000F00L 58795c1f7aaSFeifei Xu #define DAGB0_RDCLI26__MAX_BW_ENABLE_MASK 0x00001000L 58895c1f7aaSFeifei Xu #define DAGB0_RDCLI26__MAX_BW_MASK 0x001FE000L 58995c1f7aaSFeifei Xu #define DAGB0_RDCLI26__MIN_BW_ENABLE_MASK 0x00200000L 59095c1f7aaSFeifei Xu #define DAGB0_RDCLI26__MIN_BW_MASK 0x01C00000L 59195c1f7aaSFeifei Xu #define DAGB0_RDCLI26__OSD_LIMITER_ENABLE_MASK 0x02000000L 59295c1f7aaSFeifei Xu #define DAGB0_RDCLI26__MAX_OSD_MASK 0xFC000000L 59395c1f7aaSFeifei Xu //DAGB0_RDCLI27 59495c1f7aaSFeifei Xu #define DAGB0_RDCLI27__VIRT_CHAN__SHIFT 0x0 59595c1f7aaSFeifei Xu #define DAGB0_RDCLI27__CHECK_TLB_CREDIT__SHIFT 0x3 59695c1f7aaSFeifei Xu #define DAGB0_RDCLI27__URG_HIGH__SHIFT 0x4 59795c1f7aaSFeifei Xu #define DAGB0_RDCLI27__URG_LOW__SHIFT 0x8 59895c1f7aaSFeifei Xu #define DAGB0_RDCLI27__MAX_BW_ENABLE__SHIFT 0xc 59995c1f7aaSFeifei Xu #define DAGB0_RDCLI27__MAX_BW__SHIFT 0xd 60095c1f7aaSFeifei Xu #define DAGB0_RDCLI27__MIN_BW_ENABLE__SHIFT 0x15 60195c1f7aaSFeifei Xu #define DAGB0_RDCLI27__MIN_BW__SHIFT 0x16 60295c1f7aaSFeifei Xu #define DAGB0_RDCLI27__OSD_LIMITER_ENABLE__SHIFT 0x19 60395c1f7aaSFeifei Xu #define DAGB0_RDCLI27__MAX_OSD__SHIFT 0x1a 60495c1f7aaSFeifei Xu #define DAGB0_RDCLI27__VIRT_CHAN_MASK 0x00000007L 60595c1f7aaSFeifei Xu #define DAGB0_RDCLI27__CHECK_TLB_CREDIT_MASK 0x00000008L 60695c1f7aaSFeifei Xu #define DAGB0_RDCLI27__URG_HIGH_MASK 0x000000F0L 60795c1f7aaSFeifei Xu #define DAGB0_RDCLI27__URG_LOW_MASK 0x00000F00L 60895c1f7aaSFeifei Xu #define DAGB0_RDCLI27__MAX_BW_ENABLE_MASK 0x00001000L 60995c1f7aaSFeifei Xu #define DAGB0_RDCLI27__MAX_BW_MASK 0x001FE000L 61095c1f7aaSFeifei Xu #define DAGB0_RDCLI27__MIN_BW_ENABLE_MASK 0x00200000L 61195c1f7aaSFeifei Xu #define DAGB0_RDCLI27__MIN_BW_MASK 0x01C00000L 61295c1f7aaSFeifei Xu #define DAGB0_RDCLI27__OSD_LIMITER_ENABLE_MASK 0x02000000L 61395c1f7aaSFeifei Xu #define DAGB0_RDCLI27__MAX_OSD_MASK 0xFC000000L 61495c1f7aaSFeifei Xu //DAGB0_RDCLI28 61595c1f7aaSFeifei Xu #define DAGB0_RDCLI28__VIRT_CHAN__SHIFT 0x0 61695c1f7aaSFeifei Xu #define DAGB0_RDCLI28__CHECK_TLB_CREDIT__SHIFT 0x3 61795c1f7aaSFeifei Xu #define DAGB0_RDCLI28__URG_HIGH__SHIFT 0x4 61895c1f7aaSFeifei Xu #define DAGB0_RDCLI28__URG_LOW__SHIFT 0x8 61995c1f7aaSFeifei Xu #define DAGB0_RDCLI28__MAX_BW_ENABLE__SHIFT 0xc 62095c1f7aaSFeifei Xu #define DAGB0_RDCLI28__MAX_BW__SHIFT 0xd 62195c1f7aaSFeifei Xu #define DAGB0_RDCLI28__MIN_BW_ENABLE__SHIFT 0x15 62295c1f7aaSFeifei Xu #define DAGB0_RDCLI28__MIN_BW__SHIFT 0x16 62395c1f7aaSFeifei Xu #define DAGB0_RDCLI28__OSD_LIMITER_ENABLE__SHIFT 0x19 62495c1f7aaSFeifei Xu #define DAGB0_RDCLI28__MAX_OSD__SHIFT 0x1a 62595c1f7aaSFeifei Xu #define DAGB0_RDCLI28__VIRT_CHAN_MASK 0x00000007L 62695c1f7aaSFeifei Xu #define DAGB0_RDCLI28__CHECK_TLB_CREDIT_MASK 0x00000008L 62795c1f7aaSFeifei Xu #define DAGB0_RDCLI28__URG_HIGH_MASK 0x000000F0L 62895c1f7aaSFeifei Xu #define DAGB0_RDCLI28__URG_LOW_MASK 0x00000F00L 62995c1f7aaSFeifei Xu #define DAGB0_RDCLI28__MAX_BW_ENABLE_MASK 0x00001000L 63095c1f7aaSFeifei Xu #define DAGB0_RDCLI28__MAX_BW_MASK 0x001FE000L 63195c1f7aaSFeifei Xu #define DAGB0_RDCLI28__MIN_BW_ENABLE_MASK 0x00200000L 63295c1f7aaSFeifei Xu #define DAGB0_RDCLI28__MIN_BW_MASK 0x01C00000L 63395c1f7aaSFeifei Xu #define DAGB0_RDCLI28__OSD_LIMITER_ENABLE_MASK 0x02000000L 63495c1f7aaSFeifei Xu #define DAGB0_RDCLI28__MAX_OSD_MASK 0xFC000000L 63595c1f7aaSFeifei Xu //DAGB0_RDCLI29 63695c1f7aaSFeifei Xu #define DAGB0_RDCLI29__VIRT_CHAN__SHIFT 0x0 63795c1f7aaSFeifei Xu #define DAGB0_RDCLI29__CHECK_TLB_CREDIT__SHIFT 0x3 63895c1f7aaSFeifei Xu #define DAGB0_RDCLI29__URG_HIGH__SHIFT 0x4 63995c1f7aaSFeifei Xu #define DAGB0_RDCLI29__URG_LOW__SHIFT 0x8 64095c1f7aaSFeifei Xu #define DAGB0_RDCLI29__MAX_BW_ENABLE__SHIFT 0xc 64195c1f7aaSFeifei Xu #define DAGB0_RDCLI29__MAX_BW__SHIFT 0xd 64295c1f7aaSFeifei Xu #define DAGB0_RDCLI29__MIN_BW_ENABLE__SHIFT 0x15 64395c1f7aaSFeifei Xu #define DAGB0_RDCLI29__MIN_BW__SHIFT 0x16 64495c1f7aaSFeifei Xu #define DAGB0_RDCLI29__OSD_LIMITER_ENABLE__SHIFT 0x19 64595c1f7aaSFeifei Xu #define DAGB0_RDCLI29__MAX_OSD__SHIFT 0x1a 64695c1f7aaSFeifei Xu #define DAGB0_RDCLI29__VIRT_CHAN_MASK 0x00000007L 64795c1f7aaSFeifei Xu #define DAGB0_RDCLI29__CHECK_TLB_CREDIT_MASK 0x00000008L 64895c1f7aaSFeifei Xu #define DAGB0_RDCLI29__URG_HIGH_MASK 0x000000F0L 64995c1f7aaSFeifei Xu #define DAGB0_RDCLI29__URG_LOW_MASK 0x00000F00L 65095c1f7aaSFeifei Xu #define DAGB0_RDCLI29__MAX_BW_ENABLE_MASK 0x00001000L 65195c1f7aaSFeifei Xu #define DAGB0_RDCLI29__MAX_BW_MASK 0x001FE000L 65295c1f7aaSFeifei Xu #define DAGB0_RDCLI29__MIN_BW_ENABLE_MASK 0x00200000L 65395c1f7aaSFeifei Xu #define DAGB0_RDCLI29__MIN_BW_MASK 0x01C00000L 65495c1f7aaSFeifei Xu #define DAGB0_RDCLI29__OSD_LIMITER_ENABLE_MASK 0x02000000L 65595c1f7aaSFeifei Xu #define DAGB0_RDCLI29__MAX_OSD_MASK 0xFC000000L 65695c1f7aaSFeifei Xu //DAGB0_RDCLI30 65795c1f7aaSFeifei Xu #define DAGB0_RDCLI30__VIRT_CHAN__SHIFT 0x0 65895c1f7aaSFeifei Xu #define DAGB0_RDCLI30__CHECK_TLB_CREDIT__SHIFT 0x3 65995c1f7aaSFeifei Xu #define DAGB0_RDCLI30__URG_HIGH__SHIFT 0x4 66095c1f7aaSFeifei Xu #define DAGB0_RDCLI30__URG_LOW__SHIFT 0x8 66195c1f7aaSFeifei Xu #define DAGB0_RDCLI30__MAX_BW_ENABLE__SHIFT 0xc 66295c1f7aaSFeifei Xu #define DAGB0_RDCLI30__MAX_BW__SHIFT 0xd 66395c1f7aaSFeifei Xu #define DAGB0_RDCLI30__MIN_BW_ENABLE__SHIFT 0x15 66495c1f7aaSFeifei Xu #define DAGB0_RDCLI30__MIN_BW__SHIFT 0x16 66595c1f7aaSFeifei Xu #define DAGB0_RDCLI30__OSD_LIMITER_ENABLE__SHIFT 0x19 66695c1f7aaSFeifei Xu #define DAGB0_RDCLI30__MAX_OSD__SHIFT 0x1a 66795c1f7aaSFeifei Xu #define DAGB0_RDCLI30__VIRT_CHAN_MASK 0x00000007L 66895c1f7aaSFeifei Xu #define DAGB0_RDCLI30__CHECK_TLB_CREDIT_MASK 0x00000008L 66995c1f7aaSFeifei Xu #define DAGB0_RDCLI30__URG_HIGH_MASK 0x000000F0L 67095c1f7aaSFeifei Xu #define DAGB0_RDCLI30__URG_LOW_MASK 0x00000F00L 67195c1f7aaSFeifei Xu #define DAGB0_RDCLI30__MAX_BW_ENABLE_MASK 0x00001000L 67295c1f7aaSFeifei Xu #define DAGB0_RDCLI30__MAX_BW_MASK 0x001FE000L 67395c1f7aaSFeifei Xu #define DAGB0_RDCLI30__MIN_BW_ENABLE_MASK 0x00200000L 67495c1f7aaSFeifei Xu #define DAGB0_RDCLI30__MIN_BW_MASK 0x01C00000L 67595c1f7aaSFeifei Xu #define DAGB0_RDCLI30__OSD_LIMITER_ENABLE_MASK 0x02000000L 67695c1f7aaSFeifei Xu #define DAGB0_RDCLI30__MAX_OSD_MASK 0xFC000000L 67795c1f7aaSFeifei Xu //DAGB0_RDCLI31 67895c1f7aaSFeifei Xu #define DAGB0_RDCLI31__VIRT_CHAN__SHIFT 0x0 67995c1f7aaSFeifei Xu #define DAGB0_RDCLI31__CHECK_TLB_CREDIT__SHIFT 0x3 68095c1f7aaSFeifei Xu #define DAGB0_RDCLI31__URG_HIGH__SHIFT 0x4 68195c1f7aaSFeifei Xu #define DAGB0_RDCLI31__URG_LOW__SHIFT 0x8 68295c1f7aaSFeifei Xu #define DAGB0_RDCLI31__MAX_BW_ENABLE__SHIFT 0xc 68395c1f7aaSFeifei Xu #define DAGB0_RDCLI31__MAX_BW__SHIFT 0xd 68495c1f7aaSFeifei Xu #define DAGB0_RDCLI31__MIN_BW_ENABLE__SHIFT 0x15 68595c1f7aaSFeifei Xu #define DAGB0_RDCLI31__MIN_BW__SHIFT 0x16 68695c1f7aaSFeifei Xu #define DAGB0_RDCLI31__OSD_LIMITER_ENABLE__SHIFT 0x19 68795c1f7aaSFeifei Xu #define DAGB0_RDCLI31__MAX_OSD__SHIFT 0x1a 68895c1f7aaSFeifei Xu #define DAGB0_RDCLI31__VIRT_CHAN_MASK 0x00000007L 68995c1f7aaSFeifei Xu #define DAGB0_RDCLI31__CHECK_TLB_CREDIT_MASK 0x00000008L 69095c1f7aaSFeifei Xu #define DAGB0_RDCLI31__URG_HIGH_MASK 0x000000F0L 69195c1f7aaSFeifei Xu #define DAGB0_RDCLI31__URG_LOW_MASK 0x00000F00L 69295c1f7aaSFeifei Xu #define DAGB0_RDCLI31__MAX_BW_ENABLE_MASK 0x00001000L 69395c1f7aaSFeifei Xu #define DAGB0_RDCLI31__MAX_BW_MASK 0x001FE000L 69495c1f7aaSFeifei Xu #define DAGB0_RDCLI31__MIN_BW_ENABLE_MASK 0x00200000L 69595c1f7aaSFeifei Xu #define DAGB0_RDCLI31__MIN_BW_MASK 0x01C00000L 69695c1f7aaSFeifei Xu #define DAGB0_RDCLI31__OSD_LIMITER_ENABLE_MASK 0x02000000L 69795c1f7aaSFeifei Xu #define DAGB0_RDCLI31__MAX_OSD_MASK 0xFC000000L 69895c1f7aaSFeifei Xu //DAGB0_RD_CNTL 69995c1f7aaSFeifei Xu #define DAGB0_RD_CNTL__SCLK_FREQ__SHIFT 0x0 70095c1f7aaSFeifei Xu #define DAGB0_RD_CNTL__CLI_MAX_BW_WINDOW__SHIFT 0x4 70195c1f7aaSFeifei Xu #define DAGB0_RD_CNTL__VC_MAX_BW_WINDOW__SHIFT 0xa 70295c1f7aaSFeifei Xu #define DAGB0_RD_CNTL__IO_LEVEL_OVERRIDE_ENABLE__SHIFT 0x10 70395c1f7aaSFeifei Xu #define DAGB0_RD_CNTL__IO_LEVEL__SHIFT 0x11 70495c1f7aaSFeifei Xu #define DAGB0_RD_CNTL__IO_LEVEL_COMPLY_VC__SHIFT 0x14 70595c1f7aaSFeifei Xu #define DAGB0_RD_CNTL__SHARE_VC_NUM__SHIFT 0x17 70695c1f7aaSFeifei Xu #define DAGB0_RD_CNTL__SCLK_FREQ_MASK 0x0000000FL 70795c1f7aaSFeifei Xu #define DAGB0_RD_CNTL__CLI_MAX_BW_WINDOW_MASK 0x000003F0L 70895c1f7aaSFeifei Xu #define DAGB0_RD_CNTL__VC_MAX_BW_WINDOW_MASK 0x0000FC00L 70995c1f7aaSFeifei Xu #define DAGB0_RD_CNTL__IO_LEVEL_OVERRIDE_ENABLE_MASK 0x00010000L 71095c1f7aaSFeifei Xu #define DAGB0_RD_CNTL__IO_LEVEL_MASK 0x000E0000L 71195c1f7aaSFeifei Xu #define DAGB0_RD_CNTL__IO_LEVEL_COMPLY_VC_MASK 0x00700000L 71295c1f7aaSFeifei Xu #define DAGB0_RD_CNTL__SHARE_VC_NUM_MASK 0x03800000L 71395c1f7aaSFeifei Xu //DAGB0_RD_GMI_CNTL 71495c1f7aaSFeifei Xu #define DAGB0_RD_GMI_CNTL__EA_CREDIT__SHIFT 0x0 71595c1f7aaSFeifei Xu #define DAGB0_RD_GMI_CNTL__LEVEL__SHIFT 0x6 71695c1f7aaSFeifei Xu #define DAGB0_RD_GMI_CNTL__MAX_BURST__SHIFT 0x9 71795c1f7aaSFeifei Xu #define DAGB0_RD_GMI_CNTL__LAZY_TIMER__SHIFT 0xd 71895c1f7aaSFeifei Xu #define DAGB0_RD_GMI_CNTL__EA_CREDIT_MASK 0x0000003FL 71995c1f7aaSFeifei Xu #define DAGB0_RD_GMI_CNTL__LEVEL_MASK 0x000001C0L 72095c1f7aaSFeifei Xu #define DAGB0_RD_GMI_CNTL__MAX_BURST_MASK 0x00001E00L 72195c1f7aaSFeifei Xu #define DAGB0_RD_GMI_CNTL__LAZY_TIMER_MASK 0x0001E000L 72295c1f7aaSFeifei Xu //DAGB0_RD_ADDR_DAGB 72395c1f7aaSFeifei Xu #define DAGB0_RD_ADDR_DAGB__DAGB_ENABLE__SHIFT 0x0 72495c1f7aaSFeifei Xu #define DAGB0_RD_ADDR_DAGB__ENABLE_JUMP_AHEAD__SHIFT 0x3 72595c1f7aaSFeifei Xu #define DAGB0_RD_ADDR_DAGB__DISABLE_SELF_INIT__SHIFT 0x6 72695c1f7aaSFeifei Xu #define DAGB0_RD_ADDR_DAGB__WHOAMI__SHIFT 0x7 72795c1f7aaSFeifei Xu #define DAGB0_RD_ADDR_DAGB__DAGB_ENABLE_MASK 0x00000007L 72895c1f7aaSFeifei Xu #define DAGB0_RD_ADDR_DAGB__ENABLE_JUMP_AHEAD_MASK 0x00000038L 72995c1f7aaSFeifei Xu #define DAGB0_RD_ADDR_DAGB__DISABLE_SELF_INIT_MASK 0x00000040L 73095c1f7aaSFeifei Xu #define DAGB0_RD_ADDR_DAGB__WHOAMI_MASK 0x00001F80L 73195c1f7aaSFeifei Xu //DAGB0_RD_OUTPUT_DAGB_MAX_BURST 73295c1f7aaSFeifei Xu #define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC0__SHIFT 0x0 73395c1f7aaSFeifei Xu #define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC1__SHIFT 0x4 73495c1f7aaSFeifei Xu #define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC2__SHIFT 0x8 73595c1f7aaSFeifei Xu #define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC3__SHIFT 0xc 73695c1f7aaSFeifei Xu #define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC4__SHIFT 0x10 73795c1f7aaSFeifei Xu #define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC5__SHIFT 0x14 73895c1f7aaSFeifei Xu #define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC6__SHIFT 0x18 73995c1f7aaSFeifei Xu #define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC7__SHIFT 0x1c 74095c1f7aaSFeifei Xu #define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC0_MASK 0x0000000FL 74195c1f7aaSFeifei Xu #define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC1_MASK 0x000000F0L 74295c1f7aaSFeifei Xu #define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC2_MASK 0x00000F00L 74395c1f7aaSFeifei Xu #define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC3_MASK 0x0000F000L 74495c1f7aaSFeifei Xu #define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC4_MASK 0x000F0000L 74595c1f7aaSFeifei Xu #define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC5_MASK 0x00F00000L 74695c1f7aaSFeifei Xu #define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC6_MASK 0x0F000000L 74795c1f7aaSFeifei Xu #define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC7_MASK 0xF0000000L 74895c1f7aaSFeifei Xu //DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER 74995c1f7aaSFeifei Xu #define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC0__SHIFT 0x0 75095c1f7aaSFeifei Xu #define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC1__SHIFT 0x4 75195c1f7aaSFeifei Xu #define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC2__SHIFT 0x8 75295c1f7aaSFeifei Xu #define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC3__SHIFT 0xc 75395c1f7aaSFeifei Xu #define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC4__SHIFT 0x10 75495c1f7aaSFeifei Xu #define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC5__SHIFT 0x14 75595c1f7aaSFeifei Xu #define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC6__SHIFT 0x18 75695c1f7aaSFeifei Xu #define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC7__SHIFT 0x1c 75795c1f7aaSFeifei Xu #define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC0_MASK 0x0000000FL 75895c1f7aaSFeifei Xu #define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC1_MASK 0x000000F0L 75995c1f7aaSFeifei Xu #define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC2_MASK 0x00000F00L 76095c1f7aaSFeifei Xu #define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC3_MASK 0x0000F000L 76195c1f7aaSFeifei Xu #define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC4_MASK 0x000F0000L 76295c1f7aaSFeifei Xu #define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC5_MASK 0x00F00000L 76395c1f7aaSFeifei Xu #define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC6_MASK 0x0F000000L 76495c1f7aaSFeifei Xu #define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC7_MASK 0xF0000000L 76595c1f7aaSFeifei Xu //DAGB0_RD_CGTT_CLK_CTRL 76695c1f7aaSFeifei Xu #define DAGB0_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 76795c1f7aaSFeifei Xu #define DAGB0_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 76895c1f7aaSFeifei Xu #define DAGB0_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16 76995c1f7aaSFeifei Xu #define DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b 77095c1f7aaSFeifei Xu #define DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c 77195c1f7aaSFeifei Xu #define DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d 77295c1f7aaSFeifei Xu #define DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e 77395c1f7aaSFeifei Xu #define DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f 77495c1f7aaSFeifei Xu #define DAGB0_RD_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL 77595c1f7aaSFeifei Xu #define DAGB0_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L 77695c1f7aaSFeifei Xu #define DAGB0_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L 77795c1f7aaSFeifei Xu #define DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L 77895c1f7aaSFeifei Xu #define DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L 77995c1f7aaSFeifei Xu #define DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L 78095c1f7aaSFeifei Xu #define DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L 78195c1f7aaSFeifei Xu #define DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L 78295c1f7aaSFeifei Xu //DAGB0_L1TLB_RD_CGTT_CLK_CTRL 78395c1f7aaSFeifei Xu #define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 78495c1f7aaSFeifei Xu #define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 78595c1f7aaSFeifei Xu #define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16 78695c1f7aaSFeifei Xu #define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b 78795c1f7aaSFeifei Xu #define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c 78895c1f7aaSFeifei Xu #define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d 78995c1f7aaSFeifei Xu #define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e 79095c1f7aaSFeifei Xu #define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f 79195c1f7aaSFeifei Xu #define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL 79295c1f7aaSFeifei Xu #define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L 79395c1f7aaSFeifei Xu #define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L 79495c1f7aaSFeifei Xu #define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L 79595c1f7aaSFeifei Xu #define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L 79695c1f7aaSFeifei Xu #define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L 79795c1f7aaSFeifei Xu #define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L 79895c1f7aaSFeifei Xu #define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L 79995c1f7aaSFeifei Xu //DAGB0_ATCVM_RD_CGTT_CLK_CTRL 80095c1f7aaSFeifei Xu #define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 80195c1f7aaSFeifei Xu #define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 80295c1f7aaSFeifei Xu #define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16 80395c1f7aaSFeifei Xu #define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b 80495c1f7aaSFeifei Xu #define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c 80595c1f7aaSFeifei Xu #define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d 80695c1f7aaSFeifei Xu #define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e 80795c1f7aaSFeifei Xu #define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f 80895c1f7aaSFeifei Xu #define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL 80995c1f7aaSFeifei Xu #define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L 81095c1f7aaSFeifei Xu #define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L 81195c1f7aaSFeifei Xu #define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L 81295c1f7aaSFeifei Xu #define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L 81395c1f7aaSFeifei Xu #define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L 81495c1f7aaSFeifei Xu #define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L 81595c1f7aaSFeifei Xu #define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L 81695c1f7aaSFeifei Xu //DAGB0_RD_ADDR_DAGB_MAX_BURST0 81795c1f7aaSFeifei Xu #define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT0__SHIFT 0x0 81895c1f7aaSFeifei Xu #define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT1__SHIFT 0x4 81995c1f7aaSFeifei Xu #define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT2__SHIFT 0x8 82095c1f7aaSFeifei Xu #define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT3__SHIFT 0xc 82195c1f7aaSFeifei Xu #define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT4__SHIFT 0x10 82295c1f7aaSFeifei Xu #define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT5__SHIFT 0x14 82395c1f7aaSFeifei Xu #define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT6__SHIFT 0x18 82495c1f7aaSFeifei Xu #define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT7__SHIFT 0x1c 82595c1f7aaSFeifei Xu #define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT0_MASK 0x0000000FL 82695c1f7aaSFeifei Xu #define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT1_MASK 0x000000F0L 82795c1f7aaSFeifei Xu #define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT2_MASK 0x00000F00L 82895c1f7aaSFeifei Xu #define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT3_MASK 0x0000F000L 82995c1f7aaSFeifei Xu #define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT4_MASK 0x000F0000L 83095c1f7aaSFeifei Xu #define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT5_MASK 0x00F00000L 83195c1f7aaSFeifei Xu #define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT6_MASK 0x0F000000L 83295c1f7aaSFeifei Xu #define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT7_MASK 0xF0000000L 83395c1f7aaSFeifei Xu //DAGB0_RD_ADDR_DAGB_LAZY_TIMER0 83495c1f7aaSFeifei Xu #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT0__SHIFT 0x0 83595c1f7aaSFeifei Xu #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT1__SHIFT 0x4 83695c1f7aaSFeifei Xu #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT2__SHIFT 0x8 83795c1f7aaSFeifei Xu #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT3__SHIFT 0xc 83895c1f7aaSFeifei Xu #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT4__SHIFT 0x10 83995c1f7aaSFeifei Xu #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT5__SHIFT 0x14 84095c1f7aaSFeifei Xu #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT6__SHIFT 0x18 84195c1f7aaSFeifei Xu #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT7__SHIFT 0x1c 84295c1f7aaSFeifei Xu #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT0_MASK 0x0000000FL 84395c1f7aaSFeifei Xu #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT1_MASK 0x000000F0L 84495c1f7aaSFeifei Xu #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT2_MASK 0x00000F00L 84595c1f7aaSFeifei Xu #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT3_MASK 0x0000F000L 84695c1f7aaSFeifei Xu #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT4_MASK 0x000F0000L 84795c1f7aaSFeifei Xu #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT5_MASK 0x00F00000L 84895c1f7aaSFeifei Xu #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT6_MASK 0x0F000000L 84995c1f7aaSFeifei Xu #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT7_MASK 0xF0000000L 85095c1f7aaSFeifei Xu //DAGB0_RD_ADDR_DAGB_MAX_BURST1 85195c1f7aaSFeifei Xu #define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT8__SHIFT 0x0 85295c1f7aaSFeifei Xu #define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT9__SHIFT 0x4 85395c1f7aaSFeifei Xu #define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT10__SHIFT 0x8 85495c1f7aaSFeifei Xu #define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT11__SHIFT 0xc 85595c1f7aaSFeifei Xu #define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT12__SHIFT 0x10 85695c1f7aaSFeifei Xu #define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT13__SHIFT 0x14 85795c1f7aaSFeifei Xu #define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT14__SHIFT 0x18 85895c1f7aaSFeifei Xu #define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT15__SHIFT 0x1c 85995c1f7aaSFeifei Xu #define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT8_MASK 0x0000000FL 86095c1f7aaSFeifei Xu #define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT9_MASK 0x000000F0L 86195c1f7aaSFeifei Xu #define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT10_MASK 0x00000F00L 86295c1f7aaSFeifei Xu #define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT11_MASK 0x0000F000L 86395c1f7aaSFeifei Xu #define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT12_MASK 0x000F0000L 86495c1f7aaSFeifei Xu #define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT13_MASK 0x00F00000L 86595c1f7aaSFeifei Xu #define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT14_MASK 0x0F000000L 86695c1f7aaSFeifei Xu #define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT15_MASK 0xF0000000L 86795c1f7aaSFeifei Xu //DAGB0_RD_ADDR_DAGB_LAZY_TIMER1 86895c1f7aaSFeifei Xu #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT8__SHIFT 0x0 86995c1f7aaSFeifei Xu #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT9__SHIFT 0x4 87095c1f7aaSFeifei Xu #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT10__SHIFT 0x8 87195c1f7aaSFeifei Xu #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT11__SHIFT 0xc 87295c1f7aaSFeifei Xu #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT12__SHIFT 0x10 87395c1f7aaSFeifei Xu #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT13__SHIFT 0x14 87495c1f7aaSFeifei Xu #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT14__SHIFT 0x18 87595c1f7aaSFeifei Xu #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT15__SHIFT 0x1c 87695c1f7aaSFeifei Xu #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT8_MASK 0x0000000FL 87795c1f7aaSFeifei Xu #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT9_MASK 0x000000F0L 87895c1f7aaSFeifei Xu #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT10_MASK 0x00000F00L 87995c1f7aaSFeifei Xu #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT11_MASK 0x0000F000L 88095c1f7aaSFeifei Xu #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT12_MASK 0x000F0000L 88195c1f7aaSFeifei Xu #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT13_MASK 0x00F00000L 88295c1f7aaSFeifei Xu #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT14_MASK 0x0F000000L 88395c1f7aaSFeifei Xu #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT15_MASK 0xF0000000L 88495c1f7aaSFeifei Xu //DAGB0_RD_ADDR_DAGB_MAX_BURST2 88595c1f7aaSFeifei Xu #define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT16__SHIFT 0x0 88695c1f7aaSFeifei Xu #define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT17__SHIFT 0x4 88795c1f7aaSFeifei Xu #define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT18__SHIFT 0x8 88895c1f7aaSFeifei Xu #define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT19__SHIFT 0xc 88995c1f7aaSFeifei Xu #define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT20__SHIFT 0x10 89095c1f7aaSFeifei Xu #define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT21__SHIFT 0x14 89195c1f7aaSFeifei Xu #define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT22__SHIFT 0x18 89295c1f7aaSFeifei Xu #define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT23__SHIFT 0x1c 89395c1f7aaSFeifei Xu #define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT16_MASK 0x0000000FL 89495c1f7aaSFeifei Xu #define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT17_MASK 0x000000F0L 89595c1f7aaSFeifei Xu #define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT18_MASK 0x00000F00L 89695c1f7aaSFeifei Xu #define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT19_MASK 0x0000F000L 89795c1f7aaSFeifei Xu #define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT20_MASK 0x000F0000L 89895c1f7aaSFeifei Xu #define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT21_MASK 0x00F00000L 89995c1f7aaSFeifei Xu #define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT22_MASK 0x0F000000L 90095c1f7aaSFeifei Xu #define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT23_MASK 0xF0000000L 90195c1f7aaSFeifei Xu //DAGB0_RD_ADDR_DAGB_LAZY_TIMER2 90295c1f7aaSFeifei Xu #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT16__SHIFT 0x0 90395c1f7aaSFeifei Xu #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT17__SHIFT 0x4 90495c1f7aaSFeifei Xu #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT18__SHIFT 0x8 90595c1f7aaSFeifei Xu #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT19__SHIFT 0xc 90695c1f7aaSFeifei Xu #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT20__SHIFT 0x10 90795c1f7aaSFeifei Xu #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT21__SHIFT 0x14 90895c1f7aaSFeifei Xu #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT22__SHIFT 0x18 90995c1f7aaSFeifei Xu #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT23__SHIFT 0x1c 91095c1f7aaSFeifei Xu #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT16_MASK 0x0000000FL 91195c1f7aaSFeifei Xu #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT17_MASK 0x000000F0L 91295c1f7aaSFeifei Xu #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT18_MASK 0x00000F00L 91395c1f7aaSFeifei Xu #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT19_MASK 0x0000F000L 91495c1f7aaSFeifei Xu #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT20_MASK 0x000F0000L 91595c1f7aaSFeifei Xu #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT21_MASK 0x00F00000L 91695c1f7aaSFeifei Xu #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT22_MASK 0x0F000000L 91795c1f7aaSFeifei Xu #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT23_MASK 0xF0000000L 91895c1f7aaSFeifei Xu //DAGB0_RD_ADDR_DAGB_MAX_BURST3 91995c1f7aaSFeifei Xu #define DAGB0_RD_ADDR_DAGB_MAX_BURST3__CLIENT24__SHIFT 0x0 92095c1f7aaSFeifei Xu #define DAGB0_RD_ADDR_DAGB_MAX_BURST3__CLIENT25__SHIFT 0x4 92195c1f7aaSFeifei Xu #define DAGB0_RD_ADDR_DAGB_MAX_BURST3__CLIENT26__SHIFT 0x8 92295c1f7aaSFeifei Xu #define DAGB0_RD_ADDR_DAGB_MAX_BURST3__CLIENT27__SHIFT 0xc 92395c1f7aaSFeifei Xu #define DAGB0_RD_ADDR_DAGB_MAX_BURST3__CLIENT28__SHIFT 0x10 92495c1f7aaSFeifei Xu #define DAGB0_RD_ADDR_DAGB_MAX_BURST3__CLIENT29__SHIFT 0x14 92595c1f7aaSFeifei Xu #define DAGB0_RD_ADDR_DAGB_MAX_BURST3__CLIENT30__SHIFT 0x18 92695c1f7aaSFeifei Xu #define DAGB0_RD_ADDR_DAGB_MAX_BURST3__CLIENT31__SHIFT 0x1c 92795c1f7aaSFeifei Xu #define DAGB0_RD_ADDR_DAGB_MAX_BURST3__CLIENT24_MASK 0x0000000FL 92895c1f7aaSFeifei Xu #define DAGB0_RD_ADDR_DAGB_MAX_BURST3__CLIENT25_MASK 0x000000F0L 92995c1f7aaSFeifei Xu #define DAGB0_RD_ADDR_DAGB_MAX_BURST3__CLIENT26_MASK 0x00000F00L 93095c1f7aaSFeifei Xu #define DAGB0_RD_ADDR_DAGB_MAX_BURST3__CLIENT27_MASK 0x0000F000L 93195c1f7aaSFeifei Xu #define DAGB0_RD_ADDR_DAGB_MAX_BURST3__CLIENT28_MASK 0x000F0000L 93295c1f7aaSFeifei Xu #define DAGB0_RD_ADDR_DAGB_MAX_BURST3__CLIENT29_MASK 0x00F00000L 93395c1f7aaSFeifei Xu #define DAGB0_RD_ADDR_DAGB_MAX_BURST3__CLIENT30_MASK 0x0F000000L 93495c1f7aaSFeifei Xu #define DAGB0_RD_ADDR_DAGB_MAX_BURST3__CLIENT31_MASK 0xF0000000L 93595c1f7aaSFeifei Xu //DAGB0_RD_ADDR_DAGB_LAZY_TIMER3 93695c1f7aaSFeifei Xu #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER3__CLIENT24__SHIFT 0x0 93795c1f7aaSFeifei Xu #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER3__CLIENT25__SHIFT 0x4 93895c1f7aaSFeifei Xu #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER3__CLIENT26__SHIFT 0x8 93995c1f7aaSFeifei Xu #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER3__CLIENT27__SHIFT 0xc 94095c1f7aaSFeifei Xu #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER3__CLIENT28__SHIFT 0x10 94195c1f7aaSFeifei Xu #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER3__CLIENT29__SHIFT 0x14 94295c1f7aaSFeifei Xu #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER3__CLIENT30__SHIFT 0x18 94395c1f7aaSFeifei Xu #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER3__CLIENT31__SHIFT 0x1c 94495c1f7aaSFeifei Xu #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER3__CLIENT24_MASK 0x0000000FL 94595c1f7aaSFeifei Xu #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER3__CLIENT25_MASK 0x000000F0L 94695c1f7aaSFeifei Xu #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER3__CLIENT26_MASK 0x00000F00L 94795c1f7aaSFeifei Xu #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER3__CLIENT27_MASK 0x0000F000L 94895c1f7aaSFeifei Xu #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER3__CLIENT28_MASK 0x000F0000L 94995c1f7aaSFeifei Xu #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER3__CLIENT29_MASK 0x00F00000L 95095c1f7aaSFeifei Xu #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER3__CLIENT30_MASK 0x0F000000L 95195c1f7aaSFeifei Xu #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER3__CLIENT31_MASK 0xF0000000L 95295c1f7aaSFeifei Xu //DAGB0_RD_VC0_CNTL 95395c1f7aaSFeifei Xu #define DAGB0_RD_VC0_CNTL__STOR_CREDIT__SHIFT 0x0 95495c1f7aaSFeifei Xu #define DAGB0_RD_VC0_CNTL__EA_CREDIT__SHIFT 0x5 95595c1f7aaSFeifei Xu #define DAGB0_RD_VC0_CNTL__MAX_BW_ENABLE__SHIFT 0xb 95695c1f7aaSFeifei Xu #define DAGB0_RD_VC0_CNTL__MAX_BW__SHIFT 0xc 95795c1f7aaSFeifei Xu #define DAGB0_RD_VC0_CNTL__MIN_BW_ENABLE__SHIFT 0x14 95895c1f7aaSFeifei Xu #define DAGB0_RD_VC0_CNTL__MIN_BW__SHIFT 0x15 95995c1f7aaSFeifei Xu #define DAGB0_RD_VC0_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 96095c1f7aaSFeifei Xu #define DAGB0_RD_VC0_CNTL__MAX_OSD__SHIFT 0x19 96195c1f7aaSFeifei Xu #define DAGB0_RD_VC0_CNTL__STOR_CREDIT_MASK 0x0000001FL 96295c1f7aaSFeifei Xu #define DAGB0_RD_VC0_CNTL__EA_CREDIT_MASK 0x000007E0L 96395c1f7aaSFeifei Xu #define DAGB0_RD_VC0_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 96495c1f7aaSFeifei Xu #define DAGB0_RD_VC0_CNTL__MAX_BW_MASK 0x000FF000L 96595c1f7aaSFeifei Xu #define DAGB0_RD_VC0_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 96695c1f7aaSFeifei Xu #define DAGB0_RD_VC0_CNTL__MIN_BW_MASK 0x00E00000L 96795c1f7aaSFeifei Xu #define DAGB0_RD_VC0_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 96895c1f7aaSFeifei Xu #define DAGB0_RD_VC0_CNTL__MAX_OSD_MASK 0xFE000000L 96995c1f7aaSFeifei Xu //DAGB0_RD_VC1_CNTL 97095c1f7aaSFeifei Xu #define DAGB0_RD_VC1_CNTL__STOR_CREDIT__SHIFT 0x0 97195c1f7aaSFeifei Xu #define DAGB0_RD_VC1_CNTL__EA_CREDIT__SHIFT 0x5 97295c1f7aaSFeifei Xu #define DAGB0_RD_VC1_CNTL__MAX_BW_ENABLE__SHIFT 0xb 97395c1f7aaSFeifei Xu #define DAGB0_RD_VC1_CNTL__MAX_BW__SHIFT 0xc 97495c1f7aaSFeifei Xu #define DAGB0_RD_VC1_CNTL__MIN_BW_ENABLE__SHIFT 0x14 97595c1f7aaSFeifei Xu #define DAGB0_RD_VC1_CNTL__MIN_BW__SHIFT 0x15 97695c1f7aaSFeifei Xu #define DAGB0_RD_VC1_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 97795c1f7aaSFeifei Xu #define DAGB0_RD_VC1_CNTL__MAX_OSD__SHIFT 0x19 97895c1f7aaSFeifei Xu #define DAGB0_RD_VC1_CNTL__STOR_CREDIT_MASK 0x0000001FL 97995c1f7aaSFeifei Xu #define DAGB0_RD_VC1_CNTL__EA_CREDIT_MASK 0x000007E0L 98095c1f7aaSFeifei Xu #define DAGB0_RD_VC1_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 98195c1f7aaSFeifei Xu #define DAGB0_RD_VC1_CNTL__MAX_BW_MASK 0x000FF000L 98295c1f7aaSFeifei Xu #define DAGB0_RD_VC1_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 98395c1f7aaSFeifei Xu #define DAGB0_RD_VC1_CNTL__MIN_BW_MASK 0x00E00000L 98495c1f7aaSFeifei Xu #define DAGB0_RD_VC1_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 98595c1f7aaSFeifei Xu #define DAGB0_RD_VC1_CNTL__MAX_OSD_MASK 0xFE000000L 98695c1f7aaSFeifei Xu //DAGB0_RD_VC2_CNTL 98795c1f7aaSFeifei Xu #define DAGB0_RD_VC2_CNTL__STOR_CREDIT__SHIFT 0x0 98895c1f7aaSFeifei Xu #define DAGB0_RD_VC2_CNTL__EA_CREDIT__SHIFT 0x5 98995c1f7aaSFeifei Xu #define DAGB0_RD_VC2_CNTL__MAX_BW_ENABLE__SHIFT 0xb 99095c1f7aaSFeifei Xu #define DAGB0_RD_VC2_CNTL__MAX_BW__SHIFT 0xc 99195c1f7aaSFeifei Xu #define DAGB0_RD_VC2_CNTL__MIN_BW_ENABLE__SHIFT 0x14 99295c1f7aaSFeifei Xu #define DAGB0_RD_VC2_CNTL__MIN_BW__SHIFT 0x15 99395c1f7aaSFeifei Xu #define DAGB0_RD_VC2_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 99495c1f7aaSFeifei Xu #define DAGB0_RD_VC2_CNTL__MAX_OSD__SHIFT 0x19 99595c1f7aaSFeifei Xu #define DAGB0_RD_VC2_CNTL__STOR_CREDIT_MASK 0x0000001FL 99695c1f7aaSFeifei Xu #define DAGB0_RD_VC2_CNTL__EA_CREDIT_MASK 0x000007E0L 99795c1f7aaSFeifei Xu #define DAGB0_RD_VC2_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 99895c1f7aaSFeifei Xu #define DAGB0_RD_VC2_CNTL__MAX_BW_MASK 0x000FF000L 99995c1f7aaSFeifei Xu #define DAGB0_RD_VC2_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 100095c1f7aaSFeifei Xu #define DAGB0_RD_VC2_CNTL__MIN_BW_MASK 0x00E00000L 100195c1f7aaSFeifei Xu #define DAGB0_RD_VC2_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 100295c1f7aaSFeifei Xu #define DAGB0_RD_VC2_CNTL__MAX_OSD_MASK 0xFE000000L 100395c1f7aaSFeifei Xu //DAGB0_RD_VC3_CNTL 100495c1f7aaSFeifei Xu #define DAGB0_RD_VC3_CNTL__STOR_CREDIT__SHIFT 0x0 100595c1f7aaSFeifei Xu #define DAGB0_RD_VC3_CNTL__EA_CREDIT__SHIFT 0x5 100695c1f7aaSFeifei Xu #define DAGB0_RD_VC3_CNTL__MAX_BW_ENABLE__SHIFT 0xb 100795c1f7aaSFeifei Xu #define DAGB0_RD_VC3_CNTL__MAX_BW__SHIFT 0xc 100895c1f7aaSFeifei Xu #define DAGB0_RD_VC3_CNTL__MIN_BW_ENABLE__SHIFT 0x14 100995c1f7aaSFeifei Xu #define DAGB0_RD_VC3_CNTL__MIN_BW__SHIFT 0x15 101095c1f7aaSFeifei Xu #define DAGB0_RD_VC3_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 101195c1f7aaSFeifei Xu #define DAGB0_RD_VC3_CNTL__MAX_OSD__SHIFT 0x19 101295c1f7aaSFeifei Xu #define DAGB0_RD_VC3_CNTL__STOR_CREDIT_MASK 0x0000001FL 101395c1f7aaSFeifei Xu #define DAGB0_RD_VC3_CNTL__EA_CREDIT_MASK 0x000007E0L 101495c1f7aaSFeifei Xu #define DAGB0_RD_VC3_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 101595c1f7aaSFeifei Xu #define DAGB0_RD_VC3_CNTL__MAX_BW_MASK 0x000FF000L 101695c1f7aaSFeifei Xu #define DAGB0_RD_VC3_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 101795c1f7aaSFeifei Xu #define DAGB0_RD_VC3_CNTL__MIN_BW_MASK 0x00E00000L 101895c1f7aaSFeifei Xu #define DAGB0_RD_VC3_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 101995c1f7aaSFeifei Xu #define DAGB0_RD_VC3_CNTL__MAX_OSD_MASK 0xFE000000L 102095c1f7aaSFeifei Xu //DAGB0_RD_VC4_CNTL 102195c1f7aaSFeifei Xu #define DAGB0_RD_VC4_CNTL__STOR_CREDIT__SHIFT 0x0 102295c1f7aaSFeifei Xu #define DAGB0_RD_VC4_CNTL__EA_CREDIT__SHIFT 0x5 102395c1f7aaSFeifei Xu #define DAGB0_RD_VC4_CNTL__MAX_BW_ENABLE__SHIFT 0xb 102495c1f7aaSFeifei Xu #define DAGB0_RD_VC4_CNTL__MAX_BW__SHIFT 0xc 102595c1f7aaSFeifei Xu #define DAGB0_RD_VC4_CNTL__MIN_BW_ENABLE__SHIFT 0x14 102695c1f7aaSFeifei Xu #define DAGB0_RD_VC4_CNTL__MIN_BW__SHIFT 0x15 102795c1f7aaSFeifei Xu #define DAGB0_RD_VC4_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 102895c1f7aaSFeifei Xu #define DAGB0_RD_VC4_CNTL__MAX_OSD__SHIFT 0x19 102995c1f7aaSFeifei Xu #define DAGB0_RD_VC4_CNTL__STOR_CREDIT_MASK 0x0000001FL 103095c1f7aaSFeifei Xu #define DAGB0_RD_VC4_CNTL__EA_CREDIT_MASK 0x000007E0L 103195c1f7aaSFeifei Xu #define DAGB0_RD_VC4_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 103295c1f7aaSFeifei Xu #define DAGB0_RD_VC4_CNTL__MAX_BW_MASK 0x000FF000L 103395c1f7aaSFeifei Xu #define DAGB0_RD_VC4_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 103495c1f7aaSFeifei Xu #define DAGB0_RD_VC4_CNTL__MIN_BW_MASK 0x00E00000L 103595c1f7aaSFeifei Xu #define DAGB0_RD_VC4_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 103695c1f7aaSFeifei Xu #define DAGB0_RD_VC4_CNTL__MAX_OSD_MASK 0xFE000000L 103795c1f7aaSFeifei Xu //DAGB0_RD_VC5_CNTL 103895c1f7aaSFeifei Xu #define DAGB0_RD_VC5_CNTL__STOR_CREDIT__SHIFT 0x0 103995c1f7aaSFeifei Xu #define DAGB0_RD_VC5_CNTL__EA_CREDIT__SHIFT 0x5 104095c1f7aaSFeifei Xu #define DAGB0_RD_VC5_CNTL__MAX_BW_ENABLE__SHIFT 0xb 104195c1f7aaSFeifei Xu #define DAGB0_RD_VC5_CNTL__MAX_BW__SHIFT 0xc 104295c1f7aaSFeifei Xu #define DAGB0_RD_VC5_CNTL__MIN_BW_ENABLE__SHIFT 0x14 104395c1f7aaSFeifei Xu #define DAGB0_RD_VC5_CNTL__MIN_BW__SHIFT 0x15 104495c1f7aaSFeifei Xu #define DAGB0_RD_VC5_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 104595c1f7aaSFeifei Xu #define DAGB0_RD_VC5_CNTL__MAX_OSD__SHIFT 0x19 104695c1f7aaSFeifei Xu #define DAGB0_RD_VC5_CNTL__STOR_CREDIT_MASK 0x0000001FL 104795c1f7aaSFeifei Xu #define DAGB0_RD_VC5_CNTL__EA_CREDIT_MASK 0x000007E0L 104895c1f7aaSFeifei Xu #define DAGB0_RD_VC5_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 104995c1f7aaSFeifei Xu #define DAGB0_RD_VC5_CNTL__MAX_BW_MASK 0x000FF000L 105095c1f7aaSFeifei Xu #define DAGB0_RD_VC5_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 105195c1f7aaSFeifei Xu #define DAGB0_RD_VC5_CNTL__MIN_BW_MASK 0x00E00000L 105295c1f7aaSFeifei Xu #define DAGB0_RD_VC5_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 105395c1f7aaSFeifei Xu #define DAGB0_RD_VC5_CNTL__MAX_OSD_MASK 0xFE000000L 105495c1f7aaSFeifei Xu //DAGB0_RD_VC6_CNTL 105595c1f7aaSFeifei Xu #define DAGB0_RD_VC6_CNTL__STOR_CREDIT__SHIFT 0x0 105695c1f7aaSFeifei Xu #define DAGB0_RD_VC6_CNTL__EA_CREDIT__SHIFT 0x5 105795c1f7aaSFeifei Xu #define DAGB0_RD_VC6_CNTL__MAX_BW_ENABLE__SHIFT 0xb 105895c1f7aaSFeifei Xu #define DAGB0_RD_VC6_CNTL__MAX_BW__SHIFT 0xc 105995c1f7aaSFeifei Xu #define DAGB0_RD_VC6_CNTL__MIN_BW_ENABLE__SHIFT 0x14 106095c1f7aaSFeifei Xu #define DAGB0_RD_VC6_CNTL__MIN_BW__SHIFT 0x15 106195c1f7aaSFeifei Xu #define DAGB0_RD_VC6_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 106295c1f7aaSFeifei Xu #define DAGB0_RD_VC6_CNTL__MAX_OSD__SHIFT 0x19 106395c1f7aaSFeifei Xu #define DAGB0_RD_VC6_CNTL__STOR_CREDIT_MASK 0x0000001FL 106495c1f7aaSFeifei Xu #define DAGB0_RD_VC6_CNTL__EA_CREDIT_MASK 0x000007E0L 106595c1f7aaSFeifei Xu #define DAGB0_RD_VC6_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 106695c1f7aaSFeifei Xu #define DAGB0_RD_VC6_CNTL__MAX_BW_MASK 0x000FF000L 106795c1f7aaSFeifei Xu #define DAGB0_RD_VC6_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 106895c1f7aaSFeifei Xu #define DAGB0_RD_VC6_CNTL__MIN_BW_MASK 0x00E00000L 106995c1f7aaSFeifei Xu #define DAGB0_RD_VC6_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 107095c1f7aaSFeifei Xu #define DAGB0_RD_VC6_CNTL__MAX_OSD_MASK 0xFE000000L 107195c1f7aaSFeifei Xu //DAGB0_RD_VC7_CNTL 107295c1f7aaSFeifei Xu #define DAGB0_RD_VC7_CNTL__STOR_CREDIT__SHIFT 0x0 107395c1f7aaSFeifei Xu #define DAGB0_RD_VC7_CNTL__EA_CREDIT__SHIFT 0x5 107495c1f7aaSFeifei Xu #define DAGB0_RD_VC7_CNTL__MAX_BW_ENABLE__SHIFT 0xb 107595c1f7aaSFeifei Xu #define DAGB0_RD_VC7_CNTL__MAX_BW__SHIFT 0xc 107695c1f7aaSFeifei Xu #define DAGB0_RD_VC7_CNTL__MIN_BW_ENABLE__SHIFT 0x14 107795c1f7aaSFeifei Xu #define DAGB0_RD_VC7_CNTL__MIN_BW__SHIFT 0x15 107895c1f7aaSFeifei Xu #define DAGB0_RD_VC7_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 107995c1f7aaSFeifei Xu #define DAGB0_RD_VC7_CNTL__MAX_OSD__SHIFT 0x19 108095c1f7aaSFeifei Xu #define DAGB0_RD_VC7_CNTL__STOR_CREDIT_MASK 0x0000001FL 108195c1f7aaSFeifei Xu #define DAGB0_RD_VC7_CNTL__EA_CREDIT_MASK 0x000007E0L 108295c1f7aaSFeifei Xu #define DAGB0_RD_VC7_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 108395c1f7aaSFeifei Xu #define DAGB0_RD_VC7_CNTL__MAX_BW_MASK 0x000FF000L 108495c1f7aaSFeifei Xu #define DAGB0_RD_VC7_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 108595c1f7aaSFeifei Xu #define DAGB0_RD_VC7_CNTL__MIN_BW_MASK 0x00E00000L 108695c1f7aaSFeifei Xu #define DAGB0_RD_VC7_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 108795c1f7aaSFeifei Xu #define DAGB0_RD_VC7_CNTL__MAX_OSD_MASK 0xFE000000L 108895c1f7aaSFeifei Xu //DAGB0_RD_CNTL_MISC 108995c1f7aaSFeifei Xu #define DAGB0_RD_CNTL_MISC__STOR_POOL_CREDIT__SHIFT 0x0 109095c1f7aaSFeifei Xu #define DAGB0_RD_CNTL_MISC__EA_POOL_CREDIT__SHIFT 0x6 109195c1f7aaSFeifei Xu #define DAGB0_RD_CNTL_MISC__IO_EA_CREDIT__SHIFT 0xd 109295c1f7aaSFeifei Xu #define DAGB0_RD_CNTL_MISC__STOR_CC_LEGACY_MODE__SHIFT 0x13 109395c1f7aaSFeifei Xu #define DAGB0_RD_CNTL_MISC__EA_CC_LEGACY_MODE__SHIFT 0x14 109495c1f7aaSFeifei Xu #define DAGB0_RD_CNTL_MISC__UTCL2_CID__SHIFT 0x15 109595c1f7aaSFeifei Xu #define DAGB0_RD_CNTL_MISC__STOR_POOL_CREDIT_MASK 0x0000003FL 109695c1f7aaSFeifei Xu #define DAGB0_RD_CNTL_MISC__EA_POOL_CREDIT_MASK 0x00001FC0L 109795c1f7aaSFeifei Xu #define DAGB0_RD_CNTL_MISC__IO_EA_CREDIT_MASK 0x0007E000L 109895c1f7aaSFeifei Xu #define DAGB0_RD_CNTL_MISC__STOR_CC_LEGACY_MODE_MASK 0x00080000L 109995c1f7aaSFeifei Xu #define DAGB0_RD_CNTL_MISC__EA_CC_LEGACY_MODE_MASK 0x00100000L 110095c1f7aaSFeifei Xu #define DAGB0_RD_CNTL_MISC__UTCL2_CID_MASK 0x03E00000L 110195c1f7aaSFeifei Xu //DAGB0_RD_TLB_CREDIT 110295c1f7aaSFeifei Xu #define DAGB0_RD_TLB_CREDIT__TLB0__SHIFT 0x0 110395c1f7aaSFeifei Xu #define DAGB0_RD_TLB_CREDIT__TLB1__SHIFT 0x5 110495c1f7aaSFeifei Xu #define DAGB0_RD_TLB_CREDIT__TLB2__SHIFT 0xa 110595c1f7aaSFeifei Xu #define DAGB0_RD_TLB_CREDIT__TLB3__SHIFT 0xf 110695c1f7aaSFeifei Xu #define DAGB0_RD_TLB_CREDIT__TLB4__SHIFT 0x14 110795c1f7aaSFeifei Xu #define DAGB0_RD_TLB_CREDIT__TLB5__SHIFT 0x19 110895c1f7aaSFeifei Xu #define DAGB0_RD_TLB_CREDIT__TLB0_MASK 0x0000001FL 110995c1f7aaSFeifei Xu #define DAGB0_RD_TLB_CREDIT__TLB1_MASK 0x000003E0L 111095c1f7aaSFeifei Xu #define DAGB0_RD_TLB_CREDIT__TLB2_MASK 0x00007C00L 111195c1f7aaSFeifei Xu #define DAGB0_RD_TLB_CREDIT__TLB3_MASK 0x000F8000L 111295c1f7aaSFeifei Xu #define DAGB0_RD_TLB_CREDIT__TLB4_MASK 0x01F00000L 111395c1f7aaSFeifei Xu #define DAGB0_RD_TLB_CREDIT__TLB5_MASK 0x3E000000L 111495c1f7aaSFeifei Xu //DAGB0_RDCLI_ASK_PENDING 111595c1f7aaSFeifei Xu #define DAGB0_RDCLI_ASK_PENDING__BUSY__SHIFT 0x0 111695c1f7aaSFeifei Xu #define DAGB0_RDCLI_ASK_PENDING__BUSY_MASK 0xFFFFFFFFL 111795c1f7aaSFeifei Xu //DAGB0_RDCLI_GO_PENDING 111895c1f7aaSFeifei Xu #define DAGB0_RDCLI_GO_PENDING__BUSY__SHIFT 0x0 111995c1f7aaSFeifei Xu #define DAGB0_RDCLI_GO_PENDING__BUSY_MASK 0xFFFFFFFFL 112095c1f7aaSFeifei Xu //DAGB0_RDCLI_GBLSEND_PENDING 112195c1f7aaSFeifei Xu #define DAGB0_RDCLI_GBLSEND_PENDING__BUSY__SHIFT 0x0 112295c1f7aaSFeifei Xu #define DAGB0_RDCLI_GBLSEND_PENDING__BUSY_MASK 0xFFFFFFFFL 112395c1f7aaSFeifei Xu //DAGB0_RDCLI_TLB_PENDING 112495c1f7aaSFeifei Xu #define DAGB0_RDCLI_TLB_PENDING__BUSY__SHIFT 0x0 112595c1f7aaSFeifei Xu #define DAGB0_RDCLI_TLB_PENDING__BUSY_MASK 0xFFFFFFFFL 112695c1f7aaSFeifei Xu //DAGB0_RDCLI_OARB_PENDING 112795c1f7aaSFeifei Xu #define DAGB0_RDCLI_OARB_PENDING__BUSY__SHIFT 0x0 112895c1f7aaSFeifei Xu #define DAGB0_RDCLI_OARB_PENDING__BUSY_MASK 0xFFFFFFFFL 112995c1f7aaSFeifei Xu //DAGB0_RDCLI_OSD_PENDING 113095c1f7aaSFeifei Xu #define DAGB0_RDCLI_OSD_PENDING__BUSY__SHIFT 0x0 113195c1f7aaSFeifei Xu #define DAGB0_RDCLI_OSD_PENDING__BUSY_MASK 0xFFFFFFFFL 113295c1f7aaSFeifei Xu //DAGB0_WRCLI0 113395c1f7aaSFeifei Xu #define DAGB0_WRCLI0__VIRT_CHAN__SHIFT 0x0 113495c1f7aaSFeifei Xu #define DAGB0_WRCLI0__CHECK_TLB_CREDIT__SHIFT 0x3 113595c1f7aaSFeifei Xu #define DAGB0_WRCLI0__URG_HIGH__SHIFT 0x4 113695c1f7aaSFeifei Xu #define DAGB0_WRCLI0__URG_LOW__SHIFT 0x8 113795c1f7aaSFeifei Xu #define DAGB0_WRCLI0__MAX_BW_ENABLE__SHIFT 0xc 113895c1f7aaSFeifei Xu #define DAGB0_WRCLI0__MAX_BW__SHIFT 0xd 113995c1f7aaSFeifei Xu #define DAGB0_WRCLI0__MIN_BW_ENABLE__SHIFT 0x15 114095c1f7aaSFeifei Xu #define DAGB0_WRCLI0__MIN_BW__SHIFT 0x16 114195c1f7aaSFeifei Xu #define DAGB0_WRCLI0__OSD_LIMITER_ENABLE__SHIFT 0x19 114295c1f7aaSFeifei Xu #define DAGB0_WRCLI0__MAX_OSD__SHIFT 0x1a 114395c1f7aaSFeifei Xu #define DAGB0_WRCLI0__VIRT_CHAN_MASK 0x00000007L 114495c1f7aaSFeifei Xu #define DAGB0_WRCLI0__CHECK_TLB_CREDIT_MASK 0x00000008L 114595c1f7aaSFeifei Xu #define DAGB0_WRCLI0__URG_HIGH_MASK 0x000000F0L 114695c1f7aaSFeifei Xu #define DAGB0_WRCLI0__URG_LOW_MASK 0x00000F00L 114795c1f7aaSFeifei Xu #define DAGB0_WRCLI0__MAX_BW_ENABLE_MASK 0x00001000L 114895c1f7aaSFeifei Xu #define DAGB0_WRCLI0__MAX_BW_MASK 0x001FE000L 114995c1f7aaSFeifei Xu #define DAGB0_WRCLI0__MIN_BW_ENABLE_MASK 0x00200000L 115095c1f7aaSFeifei Xu #define DAGB0_WRCLI0__MIN_BW_MASK 0x01C00000L 115195c1f7aaSFeifei Xu #define DAGB0_WRCLI0__OSD_LIMITER_ENABLE_MASK 0x02000000L 115295c1f7aaSFeifei Xu #define DAGB0_WRCLI0__MAX_OSD_MASK 0xFC000000L 115395c1f7aaSFeifei Xu //DAGB0_WRCLI1 115495c1f7aaSFeifei Xu #define DAGB0_WRCLI1__VIRT_CHAN__SHIFT 0x0 115595c1f7aaSFeifei Xu #define DAGB0_WRCLI1__CHECK_TLB_CREDIT__SHIFT 0x3 115695c1f7aaSFeifei Xu #define DAGB0_WRCLI1__URG_HIGH__SHIFT 0x4 115795c1f7aaSFeifei Xu #define DAGB0_WRCLI1__URG_LOW__SHIFT 0x8 115895c1f7aaSFeifei Xu #define DAGB0_WRCLI1__MAX_BW_ENABLE__SHIFT 0xc 115995c1f7aaSFeifei Xu #define DAGB0_WRCLI1__MAX_BW__SHIFT 0xd 116095c1f7aaSFeifei Xu #define DAGB0_WRCLI1__MIN_BW_ENABLE__SHIFT 0x15 116195c1f7aaSFeifei Xu #define DAGB0_WRCLI1__MIN_BW__SHIFT 0x16 116295c1f7aaSFeifei Xu #define DAGB0_WRCLI1__OSD_LIMITER_ENABLE__SHIFT 0x19 116395c1f7aaSFeifei Xu #define DAGB0_WRCLI1__MAX_OSD__SHIFT 0x1a 116495c1f7aaSFeifei Xu #define DAGB0_WRCLI1__VIRT_CHAN_MASK 0x00000007L 116595c1f7aaSFeifei Xu #define DAGB0_WRCLI1__CHECK_TLB_CREDIT_MASK 0x00000008L 116695c1f7aaSFeifei Xu #define DAGB0_WRCLI1__URG_HIGH_MASK 0x000000F0L 116795c1f7aaSFeifei Xu #define DAGB0_WRCLI1__URG_LOW_MASK 0x00000F00L 116895c1f7aaSFeifei Xu #define DAGB0_WRCLI1__MAX_BW_ENABLE_MASK 0x00001000L 116995c1f7aaSFeifei Xu #define DAGB0_WRCLI1__MAX_BW_MASK 0x001FE000L 117095c1f7aaSFeifei Xu #define DAGB0_WRCLI1__MIN_BW_ENABLE_MASK 0x00200000L 117195c1f7aaSFeifei Xu #define DAGB0_WRCLI1__MIN_BW_MASK 0x01C00000L 117295c1f7aaSFeifei Xu #define DAGB0_WRCLI1__OSD_LIMITER_ENABLE_MASK 0x02000000L 117395c1f7aaSFeifei Xu #define DAGB0_WRCLI1__MAX_OSD_MASK 0xFC000000L 117495c1f7aaSFeifei Xu //DAGB0_WRCLI2 117595c1f7aaSFeifei Xu #define DAGB0_WRCLI2__VIRT_CHAN__SHIFT 0x0 117695c1f7aaSFeifei Xu #define DAGB0_WRCLI2__CHECK_TLB_CREDIT__SHIFT 0x3 117795c1f7aaSFeifei Xu #define DAGB0_WRCLI2__URG_HIGH__SHIFT 0x4 117895c1f7aaSFeifei Xu #define DAGB0_WRCLI2__URG_LOW__SHIFT 0x8 117995c1f7aaSFeifei Xu #define DAGB0_WRCLI2__MAX_BW_ENABLE__SHIFT 0xc 118095c1f7aaSFeifei Xu #define DAGB0_WRCLI2__MAX_BW__SHIFT 0xd 118195c1f7aaSFeifei Xu #define DAGB0_WRCLI2__MIN_BW_ENABLE__SHIFT 0x15 118295c1f7aaSFeifei Xu #define DAGB0_WRCLI2__MIN_BW__SHIFT 0x16 118395c1f7aaSFeifei Xu #define DAGB0_WRCLI2__OSD_LIMITER_ENABLE__SHIFT 0x19 118495c1f7aaSFeifei Xu #define DAGB0_WRCLI2__MAX_OSD__SHIFT 0x1a 118595c1f7aaSFeifei Xu #define DAGB0_WRCLI2__VIRT_CHAN_MASK 0x00000007L 118695c1f7aaSFeifei Xu #define DAGB0_WRCLI2__CHECK_TLB_CREDIT_MASK 0x00000008L 118795c1f7aaSFeifei Xu #define DAGB0_WRCLI2__URG_HIGH_MASK 0x000000F0L 118895c1f7aaSFeifei Xu #define DAGB0_WRCLI2__URG_LOW_MASK 0x00000F00L 118995c1f7aaSFeifei Xu #define DAGB0_WRCLI2__MAX_BW_ENABLE_MASK 0x00001000L 119095c1f7aaSFeifei Xu #define DAGB0_WRCLI2__MAX_BW_MASK 0x001FE000L 119195c1f7aaSFeifei Xu #define DAGB0_WRCLI2__MIN_BW_ENABLE_MASK 0x00200000L 119295c1f7aaSFeifei Xu #define DAGB0_WRCLI2__MIN_BW_MASK 0x01C00000L 119395c1f7aaSFeifei Xu #define DAGB0_WRCLI2__OSD_LIMITER_ENABLE_MASK 0x02000000L 119495c1f7aaSFeifei Xu #define DAGB0_WRCLI2__MAX_OSD_MASK 0xFC000000L 119595c1f7aaSFeifei Xu //DAGB0_WRCLI3 119695c1f7aaSFeifei Xu #define DAGB0_WRCLI3__VIRT_CHAN__SHIFT 0x0 119795c1f7aaSFeifei Xu #define DAGB0_WRCLI3__CHECK_TLB_CREDIT__SHIFT 0x3 119895c1f7aaSFeifei Xu #define DAGB0_WRCLI3__URG_HIGH__SHIFT 0x4 119995c1f7aaSFeifei Xu #define DAGB0_WRCLI3__URG_LOW__SHIFT 0x8 120095c1f7aaSFeifei Xu #define DAGB0_WRCLI3__MAX_BW_ENABLE__SHIFT 0xc 120195c1f7aaSFeifei Xu #define DAGB0_WRCLI3__MAX_BW__SHIFT 0xd 120295c1f7aaSFeifei Xu #define DAGB0_WRCLI3__MIN_BW_ENABLE__SHIFT 0x15 120395c1f7aaSFeifei Xu #define DAGB0_WRCLI3__MIN_BW__SHIFT 0x16 120495c1f7aaSFeifei Xu #define DAGB0_WRCLI3__OSD_LIMITER_ENABLE__SHIFT 0x19 120595c1f7aaSFeifei Xu #define DAGB0_WRCLI3__MAX_OSD__SHIFT 0x1a 120695c1f7aaSFeifei Xu #define DAGB0_WRCLI3__VIRT_CHAN_MASK 0x00000007L 120795c1f7aaSFeifei Xu #define DAGB0_WRCLI3__CHECK_TLB_CREDIT_MASK 0x00000008L 120895c1f7aaSFeifei Xu #define DAGB0_WRCLI3__URG_HIGH_MASK 0x000000F0L 120995c1f7aaSFeifei Xu #define DAGB0_WRCLI3__URG_LOW_MASK 0x00000F00L 121095c1f7aaSFeifei Xu #define DAGB0_WRCLI3__MAX_BW_ENABLE_MASK 0x00001000L 121195c1f7aaSFeifei Xu #define DAGB0_WRCLI3__MAX_BW_MASK 0x001FE000L 121295c1f7aaSFeifei Xu #define DAGB0_WRCLI3__MIN_BW_ENABLE_MASK 0x00200000L 121395c1f7aaSFeifei Xu #define DAGB0_WRCLI3__MIN_BW_MASK 0x01C00000L 121495c1f7aaSFeifei Xu #define DAGB0_WRCLI3__OSD_LIMITER_ENABLE_MASK 0x02000000L 121595c1f7aaSFeifei Xu #define DAGB0_WRCLI3__MAX_OSD_MASK 0xFC000000L 121695c1f7aaSFeifei Xu //DAGB0_WRCLI4 121795c1f7aaSFeifei Xu #define DAGB0_WRCLI4__VIRT_CHAN__SHIFT 0x0 121895c1f7aaSFeifei Xu #define DAGB0_WRCLI4__CHECK_TLB_CREDIT__SHIFT 0x3 121995c1f7aaSFeifei Xu #define DAGB0_WRCLI4__URG_HIGH__SHIFT 0x4 122095c1f7aaSFeifei Xu #define DAGB0_WRCLI4__URG_LOW__SHIFT 0x8 122195c1f7aaSFeifei Xu #define DAGB0_WRCLI4__MAX_BW_ENABLE__SHIFT 0xc 122295c1f7aaSFeifei Xu #define DAGB0_WRCLI4__MAX_BW__SHIFT 0xd 122395c1f7aaSFeifei Xu #define DAGB0_WRCLI4__MIN_BW_ENABLE__SHIFT 0x15 122495c1f7aaSFeifei Xu #define DAGB0_WRCLI4__MIN_BW__SHIFT 0x16 122595c1f7aaSFeifei Xu #define DAGB0_WRCLI4__OSD_LIMITER_ENABLE__SHIFT 0x19 122695c1f7aaSFeifei Xu #define DAGB0_WRCLI4__MAX_OSD__SHIFT 0x1a 122795c1f7aaSFeifei Xu #define DAGB0_WRCLI4__VIRT_CHAN_MASK 0x00000007L 122895c1f7aaSFeifei Xu #define DAGB0_WRCLI4__CHECK_TLB_CREDIT_MASK 0x00000008L 122995c1f7aaSFeifei Xu #define DAGB0_WRCLI4__URG_HIGH_MASK 0x000000F0L 123095c1f7aaSFeifei Xu #define DAGB0_WRCLI4__URG_LOW_MASK 0x00000F00L 123195c1f7aaSFeifei Xu #define DAGB0_WRCLI4__MAX_BW_ENABLE_MASK 0x00001000L 123295c1f7aaSFeifei Xu #define DAGB0_WRCLI4__MAX_BW_MASK 0x001FE000L 123395c1f7aaSFeifei Xu #define DAGB0_WRCLI4__MIN_BW_ENABLE_MASK 0x00200000L 123495c1f7aaSFeifei Xu #define DAGB0_WRCLI4__MIN_BW_MASK 0x01C00000L 123595c1f7aaSFeifei Xu #define DAGB0_WRCLI4__OSD_LIMITER_ENABLE_MASK 0x02000000L 123695c1f7aaSFeifei Xu #define DAGB0_WRCLI4__MAX_OSD_MASK 0xFC000000L 123795c1f7aaSFeifei Xu //DAGB0_WRCLI5 123895c1f7aaSFeifei Xu #define DAGB0_WRCLI5__VIRT_CHAN__SHIFT 0x0 123995c1f7aaSFeifei Xu #define DAGB0_WRCLI5__CHECK_TLB_CREDIT__SHIFT 0x3 124095c1f7aaSFeifei Xu #define DAGB0_WRCLI5__URG_HIGH__SHIFT 0x4 124195c1f7aaSFeifei Xu #define DAGB0_WRCLI5__URG_LOW__SHIFT 0x8 124295c1f7aaSFeifei Xu #define DAGB0_WRCLI5__MAX_BW_ENABLE__SHIFT 0xc 124395c1f7aaSFeifei Xu #define DAGB0_WRCLI5__MAX_BW__SHIFT 0xd 124495c1f7aaSFeifei Xu #define DAGB0_WRCLI5__MIN_BW_ENABLE__SHIFT 0x15 124595c1f7aaSFeifei Xu #define DAGB0_WRCLI5__MIN_BW__SHIFT 0x16 124695c1f7aaSFeifei Xu #define DAGB0_WRCLI5__OSD_LIMITER_ENABLE__SHIFT 0x19 124795c1f7aaSFeifei Xu #define DAGB0_WRCLI5__MAX_OSD__SHIFT 0x1a 124895c1f7aaSFeifei Xu #define DAGB0_WRCLI5__VIRT_CHAN_MASK 0x00000007L 124995c1f7aaSFeifei Xu #define DAGB0_WRCLI5__CHECK_TLB_CREDIT_MASK 0x00000008L 125095c1f7aaSFeifei Xu #define DAGB0_WRCLI5__URG_HIGH_MASK 0x000000F0L 125195c1f7aaSFeifei Xu #define DAGB0_WRCLI5__URG_LOW_MASK 0x00000F00L 125295c1f7aaSFeifei Xu #define DAGB0_WRCLI5__MAX_BW_ENABLE_MASK 0x00001000L 125395c1f7aaSFeifei Xu #define DAGB0_WRCLI5__MAX_BW_MASK 0x001FE000L 125495c1f7aaSFeifei Xu #define DAGB0_WRCLI5__MIN_BW_ENABLE_MASK 0x00200000L 125595c1f7aaSFeifei Xu #define DAGB0_WRCLI5__MIN_BW_MASK 0x01C00000L 125695c1f7aaSFeifei Xu #define DAGB0_WRCLI5__OSD_LIMITER_ENABLE_MASK 0x02000000L 125795c1f7aaSFeifei Xu #define DAGB0_WRCLI5__MAX_OSD_MASK 0xFC000000L 125895c1f7aaSFeifei Xu //DAGB0_WRCLI6 125995c1f7aaSFeifei Xu #define DAGB0_WRCLI6__VIRT_CHAN__SHIFT 0x0 126095c1f7aaSFeifei Xu #define DAGB0_WRCLI6__CHECK_TLB_CREDIT__SHIFT 0x3 126195c1f7aaSFeifei Xu #define DAGB0_WRCLI6__URG_HIGH__SHIFT 0x4 126295c1f7aaSFeifei Xu #define DAGB0_WRCLI6__URG_LOW__SHIFT 0x8 126395c1f7aaSFeifei Xu #define DAGB0_WRCLI6__MAX_BW_ENABLE__SHIFT 0xc 126495c1f7aaSFeifei Xu #define DAGB0_WRCLI6__MAX_BW__SHIFT 0xd 126595c1f7aaSFeifei Xu #define DAGB0_WRCLI6__MIN_BW_ENABLE__SHIFT 0x15 126695c1f7aaSFeifei Xu #define DAGB0_WRCLI6__MIN_BW__SHIFT 0x16 126795c1f7aaSFeifei Xu #define DAGB0_WRCLI6__OSD_LIMITER_ENABLE__SHIFT 0x19 126895c1f7aaSFeifei Xu #define DAGB0_WRCLI6__MAX_OSD__SHIFT 0x1a 126995c1f7aaSFeifei Xu #define DAGB0_WRCLI6__VIRT_CHAN_MASK 0x00000007L 127095c1f7aaSFeifei Xu #define DAGB0_WRCLI6__CHECK_TLB_CREDIT_MASK 0x00000008L 127195c1f7aaSFeifei Xu #define DAGB0_WRCLI6__URG_HIGH_MASK 0x000000F0L 127295c1f7aaSFeifei Xu #define DAGB0_WRCLI6__URG_LOW_MASK 0x00000F00L 127395c1f7aaSFeifei Xu #define DAGB0_WRCLI6__MAX_BW_ENABLE_MASK 0x00001000L 127495c1f7aaSFeifei Xu #define DAGB0_WRCLI6__MAX_BW_MASK 0x001FE000L 127595c1f7aaSFeifei Xu #define DAGB0_WRCLI6__MIN_BW_ENABLE_MASK 0x00200000L 127695c1f7aaSFeifei Xu #define DAGB0_WRCLI6__MIN_BW_MASK 0x01C00000L 127795c1f7aaSFeifei Xu #define DAGB0_WRCLI6__OSD_LIMITER_ENABLE_MASK 0x02000000L 127895c1f7aaSFeifei Xu #define DAGB0_WRCLI6__MAX_OSD_MASK 0xFC000000L 127995c1f7aaSFeifei Xu //DAGB0_WRCLI7 128095c1f7aaSFeifei Xu #define DAGB0_WRCLI7__VIRT_CHAN__SHIFT 0x0 128195c1f7aaSFeifei Xu #define DAGB0_WRCLI7__CHECK_TLB_CREDIT__SHIFT 0x3 128295c1f7aaSFeifei Xu #define DAGB0_WRCLI7__URG_HIGH__SHIFT 0x4 128395c1f7aaSFeifei Xu #define DAGB0_WRCLI7__URG_LOW__SHIFT 0x8 128495c1f7aaSFeifei Xu #define DAGB0_WRCLI7__MAX_BW_ENABLE__SHIFT 0xc 128595c1f7aaSFeifei Xu #define DAGB0_WRCLI7__MAX_BW__SHIFT 0xd 128695c1f7aaSFeifei Xu #define DAGB0_WRCLI7__MIN_BW_ENABLE__SHIFT 0x15 128795c1f7aaSFeifei Xu #define DAGB0_WRCLI7__MIN_BW__SHIFT 0x16 128895c1f7aaSFeifei Xu #define DAGB0_WRCLI7__OSD_LIMITER_ENABLE__SHIFT 0x19 128995c1f7aaSFeifei Xu #define DAGB0_WRCLI7__MAX_OSD__SHIFT 0x1a 129095c1f7aaSFeifei Xu #define DAGB0_WRCLI7__VIRT_CHAN_MASK 0x00000007L 129195c1f7aaSFeifei Xu #define DAGB0_WRCLI7__CHECK_TLB_CREDIT_MASK 0x00000008L 129295c1f7aaSFeifei Xu #define DAGB0_WRCLI7__URG_HIGH_MASK 0x000000F0L 129395c1f7aaSFeifei Xu #define DAGB0_WRCLI7__URG_LOW_MASK 0x00000F00L 129495c1f7aaSFeifei Xu #define DAGB0_WRCLI7__MAX_BW_ENABLE_MASK 0x00001000L 129595c1f7aaSFeifei Xu #define DAGB0_WRCLI7__MAX_BW_MASK 0x001FE000L 129695c1f7aaSFeifei Xu #define DAGB0_WRCLI7__MIN_BW_ENABLE_MASK 0x00200000L 129795c1f7aaSFeifei Xu #define DAGB0_WRCLI7__MIN_BW_MASK 0x01C00000L 129895c1f7aaSFeifei Xu #define DAGB0_WRCLI7__OSD_LIMITER_ENABLE_MASK 0x02000000L 129995c1f7aaSFeifei Xu #define DAGB0_WRCLI7__MAX_OSD_MASK 0xFC000000L 130095c1f7aaSFeifei Xu //DAGB0_WRCLI8 130195c1f7aaSFeifei Xu #define DAGB0_WRCLI8__VIRT_CHAN__SHIFT 0x0 130295c1f7aaSFeifei Xu #define DAGB0_WRCLI8__CHECK_TLB_CREDIT__SHIFT 0x3 130395c1f7aaSFeifei Xu #define DAGB0_WRCLI8__URG_HIGH__SHIFT 0x4 130495c1f7aaSFeifei Xu #define DAGB0_WRCLI8__URG_LOW__SHIFT 0x8 130595c1f7aaSFeifei Xu #define DAGB0_WRCLI8__MAX_BW_ENABLE__SHIFT 0xc 130695c1f7aaSFeifei Xu #define DAGB0_WRCLI8__MAX_BW__SHIFT 0xd 130795c1f7aaSFeifei Xu #define DAGB0_WRCLI8__MIN_BW_ENABLE__SHIFT 0x15 130895c1f7aaSFeifei Xu #define DAGB0_WRCLI8__MIN_BW__SHIFT 0x16 130995c1f7aaSFeifei Xu #define DAGB0_WRCLI8__OSD_LIMITER_ENABLE__SHIFT 0x19 131095c1f7aaSFeifei Xu #define DAGB0_WRCLI8__MAX_OSD__SHIFT 0x1a 131195c1f7aaSFeifei Xu #define DAGB0_WRCLI8__VIRT_CHAN_MASK 0x00000007L 131295c1f7aaSFeifei Xu #define DAGB0_WRCLI8__CHECK_TLB_CREDIT_MASK 0x00000008L 131395c1f7aaSFeifei Xu #define DAGB0_WRCLI8__URG_HIGH_MASK 0x000000F0L 131495c1f7aaSFeifei Xu #define DAGB0_WRCLI8__URG_LOW_MASK 0x00000F00L 131595c1f7aaSFeifei Xu #define DAGB0_WRCLI8__MAX_BW_ENABLE_MASK 0x00001000L 131695c1f7aaSFeifei Xu #define DAGB0_WRCLI8__MAX_BW_MASK 0x001FE000L 131795c1f7aaSFeifei Xu #define DAGB0_WRCLI8__MIN_BW_ENABLE_MASK 0x00200000L 131895c1f7aaSFeifei Xu #define DAGB0_WRCLI8__MIN_BW_MASK 0x01C00000L 131995c1f7aaSFeifei Xu #define DAGB0_WRCLI8__OSD_LIMITER_ENABLE_MASK 0x02000000L 132095c1f7aaSFeifei Xu #define DAGB0_WRCLI8__MAX_OSD_MASK 0xFC000000L 132195c1f7aaSFeifei Xu //DAGB0_WRCLI9 132295c1f7aaSFeifei Xu #define DAGB0_WRCLI9__VIRT_CHAN__SHIFT 0x0 132395c1f7aaSFeifei Xu #define DAGB0_WRCLI9__CHECK_TLB_CREDIT__SHIFT 0x3 132495c1f7aaSFeifei Xu #define DAGB0_WRCLI9__URG_HIGH__SHIFT 0x4 132595c1f7aaSFeifei Xu #define DAGB0_WRCLI9__URG_LOW__SHIFT 0x8 132695c1f7aaSFeifei Xu #define DAGB0_WRCLI9__MAX_BW_ENABLE__SHIFT 0xc 132795c1f7aaSFeifei Xu #define DAGB0_WRCLI9__MAX_BW__SHIFT 0xd 132895c1f7aaSFeifei Xu #define DAGB0_WRCLI9__MIN_BW_ENABLE__SHIFT 0x15 132995c1f7aaSFeifei Xu #define DAGB0_WRCLI9__MIN_BW__SHIFT 0x16 133095c1f7aaSFeifei Xu #define DAGB0_WRCLI9__OSD_LIMITER_ENABLE__SHIFT 0x19 133195c1f7aaSFeifei Xu #define DAGB0_WRCLI9__MAX_OSD__SHIFT 0x1a 133295c1f7aaSFeifei Xu #define DAGB0_WRCLI9__VIRT_CHAN_MASK 0x00000007L 133395c1f7aaSFeifei Xu #define DAGB0_WRCLI9__CHECK_TLB_CREDIT_MASK 0x00000008L 133495c1f7aaSFeifei Xu #define DAGB0_WRCLI9__URG_HIGH_MASK 0x000000F0L 133595c1f7aaSFeifei Xu #define DAGB0_WRCLI9__URG_LOW_MASK 0x00000F00L 133695c1f7aaSFeifei Xu #define DAGB0_WRCLI9__MAX_BW_ENABLE_MASK 0x00001000L 133795c1f7aaSFeifei Xu #define DAGB0_WRCLI9__MAX_BW_MASK 0x001FE000L 133895c1f7aaSFeifei Xu #define DAGB0_WRCLI9__MIN_BW_ENABLE_MASK 0x00200000L 133995c1f7aaSFeifei Xu #define DAGB0_WRCLI9__MIN_BW_MASK 0x01C00000L 134095c1f7aaSFeifei Xu #define DAGB0_WRCLI9__OSD_LIMITER_ENABLE_MASK 0x02000000L 134195c1f7aaSFeifei Xu #define DAGB0_WRCLI9__MAX_OSD_MASK 0xFC000000L 134295c1f7aaSFeifei Xu //DAGB0_WRCLI10 134395c1f7aaSFeifei Xu #define DAGB0_WRCLI10__VIRT_CHAN__SHIFT 0x0 134495c1f7aaSFeifei Xu #define DAGB0_WRCLI10__CHECK_TLB_CREDIT__SHIFT 0x3 134595c1f7aaSFeifei Xu #define DAGB0_WRCLI10__URG_HIGH__SHIFT 0x4 134695c1f7aaSFeifei Xu #define DAGB0_WRCLI10__URG_LOW__SHIFT 0x8 134795c1f7aaSFeifei Xu #define DAGB0_WRCLI10__MAX_BW_ENABLE__SHIFT 0xc 134895c1f7aaSFeifei Xu #define DAGB0_WRCLI10__MAX_BW__SHIFT 0xd 134995c1f7aaSFeifei Xu #define DAGB0_WRCLI10__MIN_BW_ENABLE__SHIFT 0x15 135095c1f7aaSFeifei Xu #define DAGB0_WRCLI10__MIN_BW__SHIFT 0x16 135195c1f7aaSFeifei Xu #define DAGB0_WRCLI10__OSD_LIMITER_ENABLE__SHIFT 0x19 135295c1f7aaSFeifei Xu #define DAGB0_WRCLI10__MAX_OSD__SHIFT 0x1a 135395c1f7aaSFeifei Xu #define DAGB0_WRCLI10__VIRT_CHAN_MASK 0x00000007L 135495c1f7aaSFeifei Xu #define DAGB0_WRCLI10__CHECK_TLB_CREDIT_MASK 0x00000008L 135595c1f7aaSFeifei Xu #define DAGB0_WRCLI10__URG_HIGH_MASK 0x000000F0L 135695c1f7aaSFeifei Xu #define DAGB0_WRCLI10__URG_LOW_MASK 0x00000F00L 135795c1f7aaSFeifei Xu #define DAGB0_WRCLI10__MAX_BW_ENABLE_MASK 0x00001000L 135895c1f7aaSFeifei Xu #define DAGB0_WRCLI10__MAX_BW_MASK 0x001FE000L 135995c1f7aaSFeifei Xu #define DAGB0_WRCLI10__MIN_BW_ENABLE_MASK 0x00200000L 136095c1f7aaSFeifei Xu #define DAGB0_WRCLI10__MIN_BW_MASK 0x01C00000L 136195c1f7aaSFeifei Xu #define DAGB0_WRCLI10__OSD_LIMITER_ENABLE_MASK 0x02000000L 136295c1f7aaSFeifei Xu #define DAGB0_WRCLI10__MAX_OSD_MASK 0xFC000000L 136395c1f7aaSFeifei Xu //DAGB0_WRCLI11 136495c1f7aaSFeifei Xu #define DAGB0_WRCLI11__VIRT_CHAN__SHIFT 0x0 136595c1f7aaSFeifei Xu #define DAGB0_WRCLI11__CHECK_TLB_CREDIT__SHIFT 0x3 136695c1f7aaSFeifei Xu #define DAGB0_WRCLI11__URG_HIGH__SHIFT 0x4 136795c1f7aaSFeifei Xu #define DAGB0_WRCLI11__URG_LOW__SHIFT 0x8 136895c1f7aaSFeifei Xu #define DAGB0_WRCLI11__MAX_BW_ENABLE__SHIFT 0xc 136995c1f7aaSFeifei Xu #define DAGB0_WRCLI11__MAX_BW__SHIFT 0xd 137095c1f7aaSFeifei Xu #define DAGB0_WRCLI11__MIN_BW_ENABLE__SHIFT 0x15 137195c1f7aaSFeifei Xu #define DAGB0_WRCLI11__MIN_BW__SHIFT 0x16 137295c1f7aaSFeifei Xu #define DAGB0_WRCLI11__OSD_LIMITER_ENABLE__SHIFT 0x19 137395c1f7aaSFeifei Xu #define DAGB0_WRCLI11__MAX_OSD__SHIFT 0x1a 137495c1f7aaSFeifei Xu #define DAGB0_WRCLI11__VIRT_CHAN_MASK 0x00000007L 137595c1f7aaSFeifei Xu #define DAGB0_WRCLI11__CHECK_TLB_CREDIT_MASK 0x00000008L 137695c1f7aaSFeifei Xu #define DAGB0_WRCLI11__URG_HIGH_MASK 0x000000F0L 137795c1f7aaSFeifei Xu #define DAGB0_WRCLI11__URG_LOW_MASK 0x00000F00L 137895c1f7aaSFeifei Xu #define DAGB0_WRCLI11__MAX_BW_ENABLE_MASK 0x00001000L 137995c1f7aaSFeifei Xu #define DAGB0_WRCLI11__MAX_BW_MASK 0x001FE000L 138095c1f7aaSFeifei Xu #define DAGB0_WRCLI11__MIN_BW_ENABLE_MASK 0x00200000L 138195c1f7aaSFeifei Xu #define DAGB0_WRCLI11__MIN_BW_MASK 0x01C00000L 138295c1f7aaSFeifei Xu #define DAGB0_WRCLI11__OSD_LIMITER_ENABLE_MASK 0x02000000L 138395c1f7aaSFeifei Xu #define DAGB0_WRCLI11__MAX_OSD_MASK 0xFC000000L 138495c1f7aaSFeifei Xu //DAGB0_WRCLI12 138595c1f7aaSFeifei Xu #define DAGB0_WRCLI12__VIRT_CHAN__SHIFT 0x0 138695c1f7aaSFeifei Xu #define DAGB0_WRCLI12__CHECK_TLB_CREDIT__SHIFT 0x3 138795c1f7aaSFeifei Xu #define DAGB0_WRCLI12__URG_HIGH__SHIFT 0x4 138895c1f7aaSFeifei Xu #define DAGB0_WRCLI12__URG_LOW__SHIFT 0x8 138995c1f7aaSFeifei Xu #define DAGB0_WRCLI12__MAX_BW_ENABLE__SHIFT 0xc 139095c1f7aaSFeifei Xu #define DAGB0_WRCLI12__MAX_BW__SHIFT 0xd 139195c1f7aaSFeifei Xu #define DAGB0_WRCLI12__MIN_BW_ENABLE__SHIFT 0x15 139295c1f7aaSFeifei Xu #define DAGB0_WRCLI12__MIN_BW__SHIFT 0x16 139395c1f7aaSFeifei Xu #define DAGB0_WRCLI12__OSD_LIMITER_ENABLE__SHIFT 0x19 139495c1f7aaSFeifei Xu #define DAGB0_WRCLI12__MAX_OSD__SHIFT 0x1a 139595c1f7aaSFeifei Xu #define DAGB0_WRCLI12__VIRT_CHAN_MASK 0x00000007L 139695c1f7aaSFeifei Xu #define DAGB0_WRCLI12__CHECK_TLB_CREDIT_MASK 0x00000008L 139795c1f7aaSFeifei Xu #define DAGB0_WRCLI12__URG_HIGH_MASK 0x000000F0L 139895c1f7aaSFeifei Xu #define DAGB0_WRCLI12__URG_LOW_MASK 0x00000F00L 139995c1f7aaSFeifei Xu #define DAGB0_WRCLI12__MAX_BW_ENABLE_MASK 0x00001000L 140095c1f7aaSFeifei Xu #define DAGB0_WRCLI12__MAX_BW_MASK 0x001FE000L 140195c1f7aaSFeifei Xu #define DAGB0_WRCLI12__MIN_BW_ENABLE_MASK 0x00200000L 140295c1f7aaSFeifei Xu #define DAGB0_WRCLI12__MIN_BW_MASK 0x01C00000L 140395c1f7aaSFeifei Xu #define DAGB0_WRCLI12__OSD_LIMITER_ENABLE_MASK 0x02000000L 140495c1f7aaSFeifei Xu #define DAGB0_WRCLI12__MAX_OSD_MASK 0xFC000000L 140595c1f7aaSFeifei Xu //DAGB0_WRCLI13 140695c1f7aaSFeifei Xu #define DAGB0_WRCLI13__VIRT_CHAN__SHIFT 0x0 140795c1f7aaSFeifei Xu #define DAGB0_WRCLI13__CHECK_TLB_CREDIT__SHIFT 0x3 140895c1f7aaSFeifei Xu #define DAGB0_WRCLI13__URG_HIGH__SHIFT 0x4 140995c1f7aaSFeifei Xu #define DAGB0_WRCLI13__URG_LOW__SHIFT 0x8 141095c1f7aaSFeifei Xu #define DAGB0_WRCLI13__MAX_BW_ENABLE__SHIFT 0xc 141195c1f7aaSFeifei Xu #define DAGB0_WRCLI13__MAX_BW__SHIFT 0xd 141295c1f7aaSFeifei Xu #define DAGB0_WRCLI13__MIN_BW_ENABLE__SHIFT 0x15 141395c1f7aaSFeifei Xu #define DAGB0_WRCLI13__MIN_BW__SHIFT 0x16 141495c1f7aaSFeifei Xu #define DAGB0_WRCLI13__OSD_LIMITER_ENABLE__SHIFT 0x19 141595c1f7aaSFeifei Xu #define DAGB0_WRCLI13__MAX_OSD__SHIFT 0x1a 141695c1f7aaSFeifei Xu #define DAGB0_WRCLI13__VIRT_CHAN_MASK 0x00000007L 141795c1f7aaSFeifei Xu #define DAGB0_WRCLI13__CHECK_TLB_CREDIT_MASK 0x00000008L 141895c1f7aaSFeifei Xu #define DAGB0_WRCLI13__URG_HIGH_MASK 0x000000F0L 141995c1f7aaSFeifei Xu #define DAGB0_WRCLI13__URG_LOW_MASK 0x00000F00L 142095c1f7aaSFeifei Xu #define DAGB0_WRCLI13__MAX_BW_ENABLE_MASK 0x00001000L 142195c1f7aaSFeifei Xu #define DAGB0_WRCLI13__MAX_BW_MASK 0x001FE000L 142295c1f7aaSFeifei Xu #define DAGB0_WRCLI13__MIN_BW_ENABLE_MASK 0x00200000L 142395c1f7aaSFeifei Xu #define DAGB0_WRCLI13__MIN_BW_MASK 0x01C00000L 142495c1f7aaSFeifei Xu #define DAGB0_WRCLI13__OSD_LIMITER_ENABLE_MASK 0x02000000L 142595c1f7aaSFeifei Xu #define DAGB0_WRCLI13__MAX_OSD_MASK 0xFC000000L 142695c1f7aaSFeifei Xu //DAGB0_WRCLI14 142795c1f7aaSFeifei Xu #define DAGB0_WRCLI14__VIRT_CHAN__SHIFT 0x0 142895c1f7aaSFeifei Xu #define DAGB0_WRCLI14__CHECK_TLB_CREDIT__SHIFT 0x3 142995c1f7aaSFeifei Xu #define DAGB0_WRCLI14__URG_HIGH__SHIFT 0x4 143095c1f7aaSFeifei Xu #define DAGB0_WRCLI14__URG_LOW__SHIFT 0x8 143195c1f7aaSFeifei Xu #define DAGB0_WRCLI14__MAX_BW_ENABLE__SHIFT 0xc 143295c1f7aaSFeifei Xu #define DAGB0_WRCLI14__MAX_BW__SHIFT 0xd 143395c1f7aaSFeifei Xu #define DAGB0_WRCLI14__MIN_BW_ENABLE__SHIFT 0x15 143495c1f7aaSFeifei Xu #define DAGB0_WRCLI14__MIN_BW__SHIFT 0x16 143595c1f7aaSFeifei Xu #define DAGB0_WRCLI14__OSD_LIMITER_ENABLE__SHIFT 0x19 143695c1f7aaSFeifei Xu #define DAGB0_WRCLI14__MAX_OSD__SHIFT 0x1a 143795c1f7aaSFeifei Xu #define DAGB0_WRCLI14__VIRT_CHAN_MASK 0x00000007L 143895c1f7aaSFeifei Xu #define DAGB0_WRCLI14__CHECK_TLB_CREDIT_MASK 0x00000008L 143995c1f7aaSFeifei Xu #define DAGB0_WRCLI14__URG_HIGH_MASK 0x000000F0L 144095c1f7aaSFeifei Xu #define DAGB0_WRCLI14__URG_LOW_MASK 0x00000F00L 144195c1f7aaSFeifei Xu #define DAGB0_WRCLI14__MAX_BW_ENABLE_MASK 0x00001000L 144295c1f7aaSFeifei Xu #define DAGB0_WRCLI14__MAX_BW_MASK 0x001FE000L 144395c1f7aaSFeifei Xu #define DAGB0_WRCLI14__MIN_BW_ENABLE_MASK 0x00200000L 144495c1f7aaSFeifei Xu #define DAGB0_WRCLI14__MIN_BW_MASK 0x01C00000L 144595c1f7aaSFeifei Xu #define DAGB0_WRCLI14__OSD_LIMITER_ENABLE_MASK 0x02000000L 144695c1f7aaSFeifei Xu #define DAGB0_WRCLI14__MAX_OSD_MASK 0xFC000000L 144795c1f7aaSFeifei Xu //DAGB0_WRCLI15 144895c1f7aaSFeifei Xu #define DAGB0_WRCLI15__VIRT_CHAN__SHIFT 0x0 144995c1f7aaSFeifei Xu #define DAGB0_WRCLI15__CHECK_TLB_CREDIT__SHIFT 0x3 145095c1f7aaSFeifei Xu #define DAGB0_WRCLI15__URG_HIGH__SHIFT 0x4 145195c1f7aaSFeifei Xu #define DAGB0_WRCLI15__URG_LOW__SHIFT 0x8 145295c1f7aaSFeifei Xu #define DAGB0_WRCLI15__MAX_BW_ENABLE__SHIFT 0xc 145395c1f7aaSFeifei Xu #define DAGB0_WRCLI15__MAX_BW__SHIFT 0xd 145495c1f7aaSFeifei Xu #define DAGB0_WRCLI15__MIN_BW_ENABLE__SHIFT 0x15 145595c1f7aaSFeifei Xu #define DAGB0_WRCLI15__MIN_BW__SHIFT 0x16 145695c1f7aaSFeifei Xu #define DAGB0_WRCLI15__OSD_LIMITER_ENABLE__SHIFT 0x19 145795c1f7aaSFeifei Xu #define DAGB0_WRCLI15__MAX_OSD__SHIFT 0x1a 145895c1f7aaSFeifei Xu #define DAGB0_WRCLI15__VIRT_CHAN_MASK 0x00000007L 145995c1f7aaSFeifei Xu #define DAGB0_WRCLI15__CHECK_TLB_CREDIT_MASK 0x00000008L 146095c1f7aaSFeifei Xu #define DAGB0_WRCLI15__URG_HIGH_MASK 0x000000F0L 146195c1f7aaSFeifei Xu #define DAGB0_WRCLI15__URG_LOW_MASK 0x00000F00L 146295c1f7aaSFeifei Xu #define DAGB0_WRCLI15__MAX_BW_ENABLE_MASK 0x00001000L 146395c1f7aaSFeifei Xu #define DAGB0_WRCLI15__MAX_BW_MASK 0x001FE000L 146495c1f7aaSFeifei Xu #define DAGB0_WRCLI15__MIN_BW_ENABLE_MASK 0x00200000L 146595c1f7aaSFeifei Xu #define DAGB0_WRCLI15__MIN_BW_MASK 0x01C00000L 146695c1f7aaSFeifei Xu #define DAGB0_WRCLI15__OSD_LIMITER_ENABLE_MASK 0x02000000L 146795c1f7aaSFeifei Xu #define DAGB0_WRCLI15__MAX_OSD_MASK 0xFC000000L 146895c1f7aaSFeifei Xu //DAGB0_WRCLI16 146995c1f7aaSFeifei Xu #define DAGB0_WRCLI16__VIRT_CHAN__SHIFT 0x0 147095c1f7aaSFeifei Xu #define DAGB0_WRCLI16__CHECK_TLB_CREDIT__SHIFT 0x3 147195c1f7aaSFeifei Xu #define DAGB0_WRCLI16__URG_HIGH__SHIFT 0x4 147295c1f7aaSFeifei Xu #define DAGB0_WRCLI16__URG_LOW__SHIFT 0x8 147395c1f7aaSFeifei Xu #define DAGB0_WRCLI16__MAX_BW_ENABLE__SHIFT 0xc 147495c1f7aaSFeifei Xu #define DAGB0_WRCLI16__MAX_BW__SHIFT 0xd 147595c1f7aaSFeifei Xu #define DAGB0_WRCLI16__MIN_BW_ENABLE__SHIFT 0x15 147695c1f7aaSFeifei Xu #define DAGB0_WRCLI16__MIN_BW__SHIFT 0x16 147795c1f7aaSFeifei Xu #define DAGB0_WRCLI16__OSD_LIMITER_ENABLE__SHIFT 0x19 147895c1f7aaSFeifei Xu #define DAGB0_WRCLI16__MAX_OSD__SHIFT 0x1a 147995c1f7aaSFeifei Xu #define DAGB0_WRCLI16__VIRT_CHAN_MASK 0x00000007L 148095c1f7aaSFeifei Xu #define DAGB0_WRCLI16__CHECK_TLB_CREDIT_MASK 0x00000008L 148195c1f7aaSFeifei Xu #define DAGB0_WRCLI16__URG_HIGH_MASK 0x000000F0L 148295c1f7aaSFeifei Xu #define DAGB0_WRCLI16__URG_LOW_MASK 0x00000F00L 148395c1f7aaSFeifei Xu #define DAGB0_WRCLI16__MAX_BW_ENABLE_MASK 0x00001000L 148495c1f7aaSFeifei Xu #define DAGB0_WRCLI16__MAX_BW_MASK 0x001FE000L 148595c1f7aaSFeifei Xu #define DAGB0_WRCLI16__MIN_BW_ENABLE_MASK 0x00200000L 148695c1f7aaSFeifei Xu #define DAGB0_WRCLI16__MIN_BW_MASK 0x01C00000L 148795c1f7aaSFeifei Xu #define DAGB0_WRCLI16__OSD_LIMITER_ENABLE_MASK 0x02000000L 148895c1f7aaSFeifei Xu #define DAGB0_WRCLI16__MAX_OSD_MASK 0xFC000000L 148995c1f7aaSFeifei Xu //DAGB0_WRCLI17 149095c1f7aaSFeifei Xu #define DAGB0_WRCLI17__VIRT_CHAN__SHIFT 0x0 149195c1f7aaSFeifei Xu #define DAGB0_WRCLI17__CHECK_TLB_CREDIT__SHIFT 0x3 149295c1f7aaSFeifei Xu #define DAGB0_WRCLI17__URG_HIGH__SHIFT 0x4 149395c1f7aaSFeifei Xu #define DAGB0_WRCLI17__URG_LOW__SHIFT 0x8 149495c1f7aaSFeifei Xu #define DAGB0_WRCLI17__MAX_BW_ENABLE__SHIFT 0xc 149595c1f7aaSFeifei Xu #define DAGB0_WRCLI17__MAX_BW__SHIFT 0xd 149695c1f7aaSFeifei Xu #define DAGB0_WRCLI17__MIN_BW_ENABLE__SHIFT 0x15 149795c1f7aaSFeifei Xu #define DAGB0_WRCLI17__MIN_BW__SHIFT 0x16 149895c1f7aaSFeifei Xu #define DAGB0_WRCLI17__OSD_LIMITER_ENABLE__SHIFT 0x19 149995c1f7aaSFeifei Xu #define DAGB0_WRCLI17__MAX_OSD__SHIFT 0x1a 150095c1f7aaSFeifei Xu #define DAGB0_WRCLI17__VIRT_CHAN_MASK 0x00000007L 150195c1f7aaSFeifei Xu #define DAGB0_WRCLI17__CHECK_TLB_CREDIT_MASK 0x00000008L 150295c1f7aaSFeifei Xu #define DAGB0_WRCLI17__URG_HIGH_MASK 0x000000F0L 150395c1f7aaSFeifei Xu #define DAGB0_WRCLI17__URG_LOW_MASK 0x00000F00L 150495c1f7aaSFeifei Xu #define DAGB0_WRCLI17__MAX_BW_ENABLE_MASK 0x00001000L 150595c1f7aaSFeifei Xu #define DAGB0_WRCLI17__MAX_BW_MASK 0x001FE000L 150695c1f7aaSFeifei Xu #define DAGB0_WRCLI17__MIN_BW_ENABLE_MASK 0x00200000L 150795c1f7aaSFeifei Xu #define DAGB0_WRCLI17__MIN_BW_MASK 0x01C00000L 150895c1f7aaSFeifei Xu #define DAGB0_WRCLI17__OSD_LIMITER_ENABLE_MASK 0x02000000L 150995c1f7aaSFeifei Xu #define DAGB0_WRCLI17__MAX_OSD_MASK 0xFC000000L 151095c1f7aaSFeifei Xu //DAGB0_WRCLI18 151195c1f7aaSFeifei Xu #define DAGB0_WRCLI18__VIRT_CHAN__SHIFT 0x0 151295c1f7aaSFeifei Xu #define DAGB0_WRCLI18__CHECK_TLB_CREDIT__SHIFT 0x3 151395c1f7aaSFeifei Xu #define DAGB0_WRCLI18__URG_HIGH__SHIFT 0x4 151495c1f7aaSFeifei Xu #define DAGB0_WRCLI18__URG_LOW__SHIFT 0x8 151595c1f7aaSFeifei Xu #define DAGB0_WRCLI18__MAX_BW_ENABLE__SHIFT 0xc 151695c1f7aaSFeifei Xu #define DAGB0_WRCLI18__MAX_BW__SHIFT 0xd 151795c1f7aaSFeifei Xu #define DAGB0_WRCLI18__MIN_BW_ENABLE__SHIFT 0x15 151895c1f7aaSFeifei Xu #define DAGB0_WRCLI18__MIN_BW__SHIFT 0x16 151995c1f7aaSFeifei Xu #define DAGB0_WRCLI18__OSD_LIMITER_ENABLE__SHIFT 0x19 152095c1f7aaSFeifei Xu #define DAGB0_WRCLI18__MAX_OSD__SHIFT 0x1a 152195c1f7aaSFeifei Xu #define DAGB0_WRCLI18__VIRT_CHAN_MASK 0x00000007L 152295c1f7aaSFeifei Xu #define DAGB0_WRCLI18__CHECK_TLB_CREDIT_MASK 0x00000008L 152395c1f7aaSFeifei Xu #define DAGB0_WRCLI18__URG_HIGH_MASK 0x000000F0L 152495c1f7aaSFeifei Xu #define DAGB0_WRCLI18__URG_LOW_MASK 0x00000F00L 152595c1f7aaSFeifei Xu #define DAGB0_WRCLI18__MAX_BW_ENABLE_MASK 0x00001000L 152695c1f7aaSFeifei Xu #define DAGB0_WRCLI18__MAX_BW_MASK 0x001FE000L 152795c1f7aaSFeifei Xu #define DAGB0_WRCLI18__MIN_BW_ENABLE_MASK 0x00200000L 152895c1f7aaSFeifei Xu #define DAGB0_WRCLI18__MIN_BW_MASK 0x01C00000L 152995c1f7aaSFeifei Xu #define DAGB0_WRCLI18__OSD_LIMITER_ENABLE_MASK 0x02000000L 153095c1f7aaSFeifei Xu #define DAGB0_WRCLI18__MAX_OSD_MASK 0xFC000000L 153195c1f7aaSFeifei Xu //DAGB0_WRCLI19 153295c1f7aaSFeifei Xu #define DAGB0_WRCLI19__VIRT_CHAN__SHIFT 0x0 153395c1f7aaSFeifei Xu #define DAGB0_WRCLI19__CHECK_TLB_CREDIT__SHIFT 0x3 153495c1f7aaSFeifei Xu #define DAGB0_WRCLI19__URG_HIGH__SHIFT 0x4 153595c1f7aaSFeifei Xu #define DAGB0_WRCLI19__URG_LOW__SHIFT 0x8 153695c1f7aaSFeifei Xu #define DAGB0_WRCLI19__MAX_BW_ENABLE__SHIFT 0xc 153795c1f7aaSFeifei Xu #define DAGB0_WRCLI19__MAX_BW__SHIFT 0xd 153895c1f7aaSFeifei Xu #define DAGB0_WRCLI19__MIN_BW_ENABLE__SHIFT 0x15 153995c1f7aaSFeifei Xu #define DAGB0_WRCLI19__MIN_BW__SHIFT 0x16 154095c1f7aaSFeifei Xu #define DAGB0_WRCLI19__OSD_LIMITER_ENABLE__SHIFT 0x19 154195c1f7aaSFeifei Xu #define DAGB0_WRCLI19__MAX_OSD__SHIFT 0x1a 154295c1f7aaSFeifei Xu #define DAGB0_WRCLI19__VIRT_CHAN_MASK 0x00000007L 154395c1f7aaSFeifei Xu #define DAGB0_WRCLI19__CHECK_TLB_CREDIT_MASK 0x00000008L 154495c1f7aaSFeifei Xu #define DAGB0_WRCLI19__URG_HIGH_MASK 0x000000F0L 154595c1f7aaSFeifei Xu #define DAGB0_WRCLI19__URG_LOW_MASK 0x00000F00L 154695c1f7aaSFeifei Xu #define DAGB0_WRCLI19__MAX_BW_ENABLE_MASK 0x00001000L 154795c1f7aaSFeifei Xu #define DAGB0_WRCLI19__MAX_BW_MASK 0x001FE000L 154895c1f7aaSFeifei Xu #define DAGB0_WRCLI19__MIN_BW_ENABLE_MASK 0x00200000L 154995c1f7aaSFeifei Xu #define DAGB0_WRCLI19__MIN_BW_MASK 0x01C00000L 155095c1f7aaSFeifei Xu #define DAGB0_WRCLI19__OSD_LIMITER_ENABLE_MASK 0x02000000L 155195c1f7aaSFeifei Xu #define DAGB0_WRCLI19__MAX_OSD_MASK 0xFC000000L 155295c1f7aaSFeifei Xu //DAGB0_WRCLI20 155395c1f7aaSFeifei Xu #define DAGB0_WRCLI20__VIRT_CHAN__SHIFT 0x0 155495c1f7aaSFeifei Xu #define DAGB0_WRCLI20__CHECK_TLB_CREDIT__SHIFT 0x3 155595c1f7aaSFeifei Xu #define DAGB0_WRCLI20__URG_HIGH__SHIFT 0x4 155695c1f7aaSFeifei Xu #define DAGB0_WRCLI20__URG_LOW__SHIFT 0x8 155795c1f7aaSFeifei Xu #define DAGB0_WRCLI20__MAX_BW_ENABLE__SHIFT 0xc 155895c1f7aaSFeifei Xu #define DAGB0_WRCLI20__MAX_BW__SHIFT 0xd 155995c1f7aaSFeifei Xu #define DAGB0_WRCLI20__MIN_BW_ENABLE__SHIFT 0x15 156095c1f7aaSFeifei Xu #define DAGB0_WRCLI20__MIN_BW__SHIFT 0x16 156195c1f7aaSFeifei Xu #define DAGB0_WRCLI20__OSD_LIMITER_ENABLE__SHIFT 0x19 156295c1f7aaSFeifei Xu #define DAGB0_WRCLI20__MAX_OSD__SHIFT 0x1a 156395c1f7aaSFeifei Xu #define DAGB0_WRCLI20__VIRT_CHAN_MASK 0x00000007L 156495c1f7aaSFeifei Xu #define DAGB0_WRCLI20__CHECK_TLB_CREDIT_MASK 0x00000008L 156595c1f7aaSFeifei Xu #define DAGB0_WRCLI20__URG_HIGH_MASK 0x000000F0L 156695c1f7aaSFeifei Xu #define DAGB0_WRCLI20__URG_LOW_MASK 0x00000F00L 156795c1f7aaSFeifei Xu #define DAGB0_WRCLI20__MAX_BW_ENABLE_MASK 0x00001000L 156895c1f7aaSFeifei Xu #define DAGB0_WRCLI20__MAX_BW_MASK 0x001FE000L 156995c1f7aaSFeifei Xu #define DAGB0_WRCLI20__MIN_BW_ENABLE_MASK 0x00200000L 157095c1f7aaSFeifei Xu #define DAGB0_WRCLI20__MIN_BW_MASK 0x01C00000L 157195c1f7aaSFeifei Xu #define DAGB0_WRCLI20__OSD_LIMITER_ENABLE_MASK 0x02000000L 157295c1f7aaSFeifei Xu #define DAGB0_WRCLI20__MAX_OSD_MASK 0xFC000000L 157395c1f7aaSFeifei Xu //DAGB0_WRCLI21 157495c1f7aaSFeifei Xu #define DAGB0_WRCLI21__VIRT_CHAN__SHIFT 0x0 157595c1f7aaSFeifei Xu #define DAGB0_WRCLI21__CHECK_TLB_CREDIT__SHIFT 0x3 157695c1f7aaSFeifei Xu #define DAGB0_WRCLI21__URG_HIGH__SHIFT 0x4 157795c1f7aaSFeifei Xu #define DAGB0_WRCLI21__URG_LOW__SHIFT 0x8 157895c1f7aaSFeifei Xu #define DAGB0_WRCLI21__MAX_BW_ENABLE__SHIFT 0xc 157995c1f7aaSFeifei Xu #define DAGB0_WRCLI21__MAX_BW__SHIFT 0xd 158095c1f7aaSFeifei Xu #define DAGB0_WRCLI21__MIN_BW_ENABLE__SHIFT 0x15 158195c1f7aaSFeifei Xu #define DAGB0_WRCLI21__MIN_BW__SHIFT 0x16 158295c1f7aaSFeifei Xu #define DAGB0_WRCLI21__OSD_LIMITER_ENABLE__SHIFT 0x19 158395c1f7aaSFeifei Xu #define DAGB0_WRCLI21__MAX_OSD__SHIFT 0x1a 158495c1f7aaSFeifei Xu #define DAGB0_WRCLI21__VIRT_CHAN_MASK 0x00000007L 158595c1f7aaSFeifei Xu #define DAGB0_WRCLI21__CHECK_TLB_CREDIT_MASK 0x00000008L 158695c1f7aaSFeifei Xu #define DAGB0_WRCLI21__URG_HIGH_MASK 0x000000F0L 158795c1f7aaSFeifei Xu #define DAGB0_WRCLI21__URG_LOW_MASK 0x00000F00L 158895c1f7aaSFeifei Xu #define DAGB0_WRCLI21__MAX_BW_ENABLE_MASK 0x00001000L 158995c1f7aaSFeifei Xu #define DAGB0_WRCLI21__MAX_BW_MASK 0x001FE000L 159095c1f7aaSFeifei Xu #define DAGB0_WRCLI21__MIN_BW_ENABLE_MASK 0x00200000L 159195c1f7aaSFeifei Xu #define DAGB0_WRCLI21__MIN_BW_MASK 0x01C00000L 159295c1f7aaSFeifei Xu #define DAGB0_WRCLI21__OSD_LIMITER_ENABLE_MASK 0x02000000L 159395c1f7aaSFeifei Xu #define DAGB0_WRCLI21__MAX_OSD_MASK 0xFC000000L 159495c1f7aaSFeifei Xu //DAGB0_WRCLI22 159595c1f7aaSFeifei Xu #define DAGB0_WRCLI22__VIRT_CHAN__SHIFT 0x0 159695c1f7aaSFeifei Xu #define DAGB0_WRCLI22__CHECK_TLB_CREDIT__SHIFT 0x3 159795c1f7aaSFeifei Xu #define DAGB0_WRCLI22__URG_HIGH__SHIFT 0x4 159895c1f7aaSFeifei Xu #define DAGB0_WRCLI22__URG_LOW__SHIFT 0x8 159995c1f7aaSFeifei Xu #define DAGB0_WRCLI22__MAX_BW_ENABLE__SHIFT 0xc 160095c1f7aaSFeifei Xu #define DAGB0_WRCLI22__MAX_BW__SHIFT 0xd 160195c1f7aaSFeifei Xu #define DAGB0_WRCLI22__MIN_BW_ENABLE__SHIFT 0x15 160295c1f7aaSFeifei Xu #define DAGB0_WRCLI22__MIN_BW__SHIFT 0x16 160395c1f7aaSFeifei Xu #define DAGB0_WRCLI22__OSD_LIMITER_ENABLE__SHIFT 0x19 160495c1f7aaSFeifei Xu #define DAGB0_WRCLI22__MAX_OSD__SHIFT 0x1a 160595c1f7aaSFeifei Xu #define DAGB0_WRCLI22__VIRT_CHAN_MASK 0x00000007L 160695c1f7aaSFeifei Xu #define DAGB0_WRCLI22__CHECK_TLB_CREDIT_MASK 0x00000008L 160795c1f7aaSFeifei Xu #define DAGB0_WRCLI22__URG_HIGH_MASK 0x000000F0L 160895c1f7aaSFeifei Xu #define DAGB0_WRCLI22__URG_LOW_MASK 0x00000F00L 160995c1f7aaSFeifei Xu #define DAGB0_WRCLI22__MAX_BW_ENABLE_MASK 0x00001000L 161095c1f7aaSFeifei Xu #define DAGB0_WRCLI22__MAX_BW_MASK 0x001FE000L 161195c1f7aaSFeifei Xu #define DAGB0_WRCLI22__MIN_BW_ENABLE_MASK 0x00200000L 161295c1f7aaSFeifei Xu #define DAGB0_WRCLI22__MIN_BW_MASK 0x01C00000L 161395c1f7aaSFeifei Xu #define DAGB0_WRCLI22__OSD_LIMITER_ENABLE_MASK 0x02000000L 161495c1f7aaSFeifei Xu #define DAGB0_WRCLI22__MAX_OSD_MASK 0xFC000000L 161595c1f7aaSFeifei Xu //DAGB0_WRCLI23 161695c1f7aaSFeifei Xu #define DAGB0_WRCLI23__VIRT_CHAN__SHIFT 0x0 161795c1f7aaSFeifei Xu #define DAGB0_WRCLI23__CHECK_TLB_CREDIT__SHIFT 0x3 161895c1f7aaSFeifei Xu #define DAGB0_WRCLI23__URG_HIGH__SHIFT 0x4 161995c1f7aaSFeifei Xu #define DAGB0_WRCLI23__URG_LOW__SHIFT 0x8 162095c1f7aaSFeifei Xu #define DAGB0_WRCLI23__MAX_BW_ENABLE__SHIFT 0xc 162195c1f7aaSFeifei Xu #define DAGB0_WRCLI23__MAX_BW__SHIFT 0xd 162295c1f7aaSFeifei Xu #define DAGB0_WRCLI23__MIN_BW_ENABLE__SHIFT 0x15 162395c1f7aaSFeifei Xu #define DAGB0_WRCLI23__MIN_BW__SHIFT 0x16 162495c1f7aaSFeifei Xu #define DAGB0_WRCLI23__OSD_LIMITER_ENABLE__SHIFT 0x19 162595c1f7aaSFeifei Xu #define DAGB0_WRCLI23__MAX_OSD__SHIFT 0x1a 162695c1f7aaSFeifei Xu #define DAGB0_WRCLI23__VIRT_CHAN_MASK 0x00000007L 162795c1f7aaSFeifei Xu #define DAGB0_WRCLI23__CHECK_TLB_CREDIT_MASK 0x00000008L 162895c1f7aaSFeifei Xu #define DAGB0_WRCLI23__URG_HIGH_MASK 0x000000F0L 162995c1f7aaSFeifei Xu #define DAGB0_WRCLI23__URG_LOW_MASK 0x00000F00L 163095c1f7aaSFeifei Xu #define DAGB0_WRCLI23__MAX_BW_ENABLE_MASK 0x00001000L 163195c1f7aaSFeifei Xu #define DAGB0_WRCLI23__MAX_BW_MASK 0x001FE000L 163295c1f7aaSFeifei Xu #define DAGB0_WRCLI23__MIN_BW_ENABLE_MASK 0x00200000L 163395c1f7aaSFeifei Xu #define DAGB0_WRCLI23__MIN_BW_MASK 0x01C00000L 163495c1f7aaSFeifei Xu #define DAGB0_WRCLI23__OSD_LIMITER_ENABLE_MASK 0x02000000L 163595c1f7aaSFeifei Xu #define DAGB0_WRCLI23__MAX_OSD_MASK 0xFC000000L 163695c1f7aaSFeifei Xu //DAGB0_WRCLI24 163795c1f7aaSFeifei Xu #define DAGB0_WRCLI24__VIRT_CHAN__SHIFT 0x0 163895c1f7aaSFeifei Xu #define DAGB0_WRCLI24__CHECK_TLB_CREDIT__SHIFT 0x3 163995c1f7aaSFeifei Xu #define DAGB0_WRCLI24__URG_HIGH__SHIFT 0x4 164095c1f7aaSFeifei Xu #define DAGB0_WRCLI24__URG_LOW__SHIFT 0x8 164195c1f7aaSFeifei Xu #define DAGB0_WRCLI24__MAX_BW_ENABLE__SHIFT 0xc 164295c1f7aaSFeifei Xu #define DAGB0_WRCLI24__MAX_BW__SHIFT 0xd 164395c1f7aaSFeifei Xu #define DAGB0_WRCLI24__MIN_BW_ENABLE__SHIFT 0x15 164495c1f7aaSFeifei Xu #define DAGB0_WRCLI24__MIN_BW__SHIFT 0x16 164595c1f7aaSFeifei Xu #define DAGB0_WRCLI24__OSD_LIMITER_ENABLE__SHIFT 0x19 164695c1f7aaSFeifei Xu #define DAGB0_WRCLI24__MAX_OSD__SHIFT 0x1a 164795c1f7aaSFeifei Xu #define DAGB0_WRCLI24__VIRT_CHAN_MASK 0x00000007L 164895c1f7aaSFeifei Xu #define DAGB0_WRCLI24__CHECK_TLB_CREDIT_MASK 0x00000008L 164995c1f7aaSFeifei Xu #define DAGB0_WRCLI24__URG_HIGH_MASK 0x000000F0L 165095c1f7aaSFeifei Xu #define DAGB0_WRCLI24__URG_LOW_MASK 0x00000F00L 165195c1f7aaSFeifei Xu #define DAGB0_WRCLI24__MAX_BW_ENABLE_MASK 0x00001000L 165295c1f7aaSFeifei Xu #define DAGB0_WRCLI24__MAX_BW_MASK 0x001FE000L 165395c1f7aaSFeifei Xu #define DAGB0_WRCLI24__MIN_BW_ENABLE_MASK 0x00200000L 165495c1f7aaSFeifei Xu #define DAGB0_WRCLI24__MIN_BW_MASK 0x01C00000L 165595c1f7aaSFeifei Xu #define DAGB0_WRCLI24__OSD_LIMITER_ENABLE_MASK 0x02000000L 165695c1f7aaSFeifei Xu #define DAGB0_WRCLI24__MAX_OSD_MASK 0xFC000000L 165795c1f7aaSFeifei Xu //DAGB0_WRCLI25 165895c1f7aaSFeifei Xu #define DAGB0_WRCLI25__VIRT_CHAN__SHIFT 0x0 165995c1f7aaSFeifei Xu #define DAGB0_WRCLI25__CHECK_TLB_CREDIT__SHIFT 0x3 166095c1f7aaSFeifei Xu #define DAGB0_WRCLI25__URG_HIGH__SHIFT 0x4 166195c1f7aaSFeifei Xu #define DAGB0_WRCLI25__URG_LOW__SHIFT 0x8 166295c1f7aaSFeifei Xu #define DAGB0_WRCLI25__MAX_BW_ENABLE__SHIFT 0xc 166395c1f7aaSFeifei Xu #define DAGB0_WRCLI25__MAX_BW__SHIFT 0xd 166495c1f7aaSFeifei Xu #define DAGB0_WRCLI25__MIN_BW_ENABLE__SHIFT 0x15 166595c1f7aaSFeifei Xu #define DAGB0_WRCLI25__MIN_BW__SHIFT 0x16 166695c1f7aaSFeifei Xu #define DAGB0_WRCLI25__OSD_LIMITER_ENABLE__SHIFT 0x19 166795c1f7aaSFeifei Xu #define DAGB0_WRCLI25__MAX_OSD__SHIFT 0x1a 166895c1f7aaSFeifei Xu #define DAGB0_WRCLI25__VIRT_CHAN_MASK 0x00000007L 166995c1f7aaSFeifei Xu #define DAGB0_WRCLI25__CHECK_TLB_CREDIT_MASK 0x00000008L 167095c1f7aaSFeifei Xu #define DAGB0_WRCLI25__URG_HIGH_MASK 0x000000F0L 167195c1f7aaSFeifei Xu #define DAGB0_WRCLI25__URG_LOW_MASK 0x00000F00L 167295c1f7aaSFeifei Xu #define DAGB0_WRCLI25__MAX_BW_ENABLE_MASK 0x00001000L 167395c1f7aaSFeifei Xu #define DAGB0_WRCLI25__MAX_BW_MASK 0x001FE000L 167495c1f7aaSFeifei Xu #define DAGB0_WRCLI25__MIN_BW_ENABLE_MASK 0x00200000L 167595c1f7aaSFeifei Xu #define DAGB0_WRCLI25__MIN_BW_MASK 0x01C00000L 167695c1f7aaSFeifei Xu #define DAGB0_WRCLI25__OSD_LIMITER_ENABLE_MASK 0x02000000L 167795c1f7aaSFeifei Xu #define DAGB0_WRCLI25__MAX_OSD_MASK 0xFC000000L 167895c1f7aaSFeifei Xu //DAGB0_WRCLI26 167995c1f7aaSFeifei Xu #define DAGB0_WRCLI26__VIRT_CHAN__SHIFT 0x0 168095c1f7aaSFeifei Xu #define DAGB0_WRCLI26__CHECK_TLB_CREDIT__SHIFT 0x3 168195c1f7aaSFeifei Xu #define DAGB0_WRCLI26__URG_HIGH__SHIFT 0x4 168295c1f7aaSFeifei Xu #define DAGB0_WRCLI26__URG_LOW__SHIFT 0x8 168395c1f7aaSFeifei Xu #define DAGB0_WRCLI26__MAX_BW_ENABLE__SHIFT 0xc 168495c1f7aaSFeifei Xu #define DAGB0_WRCLI26__MAX_BW__SHIFT 0xd 168595c1f7aaSFeifei Xu #define DAGB0_WRCLI26__MIN_BW_ENABLE__SHIFT 0x15 168695c1f7aaSFeifei Xu #define DAGB0_WRCLI26__MIN_BW__SHIFT 0x16 168795c1f7aaSFeifei Xu #define DAGB0_WRCLI26__OSD_LIMITER_ENABLE__SHIFT 0x19 168895c1f7aaSFeifei Xu #define DAGB0_WRCLI26__MAX_OSD__SHIFT 0x1a 168995c1f7aaSFeifei Xu #define DAGB0_WRCLI26__VIRT_CHAN_MASK 0x00000007L 169095c1f7aaSFeifei Xu #define DAGB0_WRCLI26__CHECK_TLB_CREDIT_MASK 0x00000008L 169195c1f7aaSFeifei Xu #define DAGB0_WRCLI26__URG_HIGH_MASK 0x000000F0L 169295c1f7aaSFeifei Xu #define DAGB0_WRCLI26__URG_LOW_MASK 0x00000F00L 169395c1f7aaSFeifei Xu #define DAGB0_WRCLI26__MAX_BW_ENABLE_MASK 0x00001000L 169495c1f7aaSFeifei Xu #define DAGB0_WRCLI26__MAX_BW_MASK 0x001FE000L 169595c1f7aaSFeifei Xu #define DAGB0_WRCLI26__MIN_BW_ENABLE_MASK 0x00200000L 169695c1f7aaSFeifei Xu #define DAGB0_WRCLI26__MIN_BW_MASK 0x01C00000L 169795c1f7aaSFeifei Xu #define DAGB0_WRCLI26__OSD_LIMITER_ENABLE_MASK 0x02000000L 169895c1f7aaSFeifei Xu #define DAGB0_WRCLI26__MAX_OSD_MASK 0xFC000000L 169995c1f7aaSFeifei Xu //DAGB0_WRCLI27 170095c1f7aaSFeifei Xu #define DAGB0_WRCLI27__VIRT_CHAN__SHIFT 0x0 170195c1f7aaSFeifei Xu #define DAGB0_WRCLI27__CHECK_TLB_CREDIT__SHIFT 0x3 170295c1f7aaSFeifei Xu #define DAGB0_WRCLI27__URG_HIGH__SHIFT 0x4 170395c1f7aaSFeifei Xu #define DAGB0_WRCLI27__URG_LOW__SHIFT 0x8 170495c1f7aaSFeifei Xu #define DAGB0_WRCLI27__MAX_BW_ENABLE__SHIFT 0xc 170595c1f7aaSFeifei Xu #define DAGB0_WRCLI27__MAX_BW__SHIFT 0xd 170695c1f7aaSFeifei Xu #define DAGB0_WRCLI27__MIN_BW_ENABLE__SHIFT 0x15 170795c1f7aaSFeifei Xu #define DAGB0_WRCLI27__MIN_BW__SHIFT 0x16 170895c1f7aaSFeifei Xu #define DAGB0_WRCLI27__OSD_LIMITER_ENABLE__SHIFT 0x19 170995c1f7aaSFeifei Xu #define DAGB0_WRCLI27__MAX_OSD__SHIFT 0x1a 171095c1f7aaSFeifei Xu #define DAGB0_WRCLI27__VIRT_CHAN_MASK 0x00000007L 171195c1f7aaSFeifei Xu #define DAGB0_WRCLI27__CHECK_TLB_CREDIT_MASK 0x00000008L 171295c1f7aaSFeifei Xu #define DAGB0_WRCLI27__URG_HIGH_MASK 0x000000F0L 171395c1f7aaSFeifei Xu #define DAGB0_WRCLI27__URG_LOW_MASK 0x00000F00L 171495c1f7aaSFeifei Xu #define DAGB0_WRCLI27__MAX_BW_ENABLE_MASK 0x00001000L 171595c1f7aaSFeifei Xu #define DAGB0_WRCLI27__MAX_BW_MASK 0x001FE000L 171695c1f7aaSFeifei Xu #define DAGB0_WRCLI27__MIN_BW_ENABLE_MASK 0x00200000L 171795c1f7aaSFeifei Xu #define DAGB0_WRCLI27__MIN_BW_MASK 0x01C00000L 171895c1f7aaSFeifei Xu #define DAGB0_WRCLI27__OSD_LIMITER_ENABLE_MASK 0x02000000L 171995c1f7aaSFeifei Xu #define DAGB0_WRCLI27__MAX_OSD_MASK 0xFC000000L 172095c1f7aaSFeifei Xu //DAGB0_WRCLI28 172195c1f7aaSFeifei Xu #define DAGB0_WRCLI28__VIRT_CHAN__SHIFT 0x0 172295c1f7aaSFeifei Xu #define DAGB0_WRCLI28__CHECK_TLB_CREDIT__SHIFT 0x3 172395c1f7aaSFeifei Xu #define DAGB0_WRCLI28__URG_HIGH__SHIFT 0x4 172495c1f7aaSFeifei Xu #define DAGB0_WRCLI28__URG_LOW__SHIFT 0x8 172595c1f7aaSFeifei Xu #define DAGB0_WRCLI28__MAX_BW_ENABLE__SHIFT 0xc 172695c1f7aaSFeifei Xu #define DAGB0_WRCLI28__MAX_BW__SHIFT 0xd 172795c1f7aaSFeifei Xu #define DAGB0_WRCLI28__MIN_BW_ENABLE__SHIFT 0x15 172895c1f7aaSFeifei Xu #define DAGB0_WRCLI28__MIN_BW__SHIFT 0x16 172995c1f7aaSFeifei Xu #define DAGB0_WRCLI28__OSD_LIMITER_ENABLE__SHIFT 0x19 173095c1f7aaSFeifei Xu #define DAGB0_WRCLI28__MAX_OSD__SHIFT 0x1a 173195c1f7aaSFeifei Xu #define DAGB0_WRCLI28__VIRT_CHAN_MASK 0x00000007L 173295c1f7aaSFeifei Xu #define DAGB0_WRCLI28__CHECK_TLB_CREDIT_MASK 0x00000008L 173395c1f7aaSFeifei Xu #define DAGB0_WRCLI28__URG_HIGH_MASK 0x000000F0L 173495c1f7aaSFeifei Xu #define DAGB0_WRCLI28__URG_LOW_MASK 0x00000F00L 173595c1f7aaSFeifei Xu #define DAGB0_WRCLI28__MAX_BW_ENABLE_MASK 0x00001000L 173695c1f7aaSFeifei Xu #define DAGB0_WRCLI28__MAX_BW_MASK 0x001FE000L 173795c1f7aaSFeifei Xu #define DAGB0_WRCLI28__MIN_BW_ENABLE_MASK 0x00200000L 173895c1f7aaSFeifei Xu #define DAGB0_WRCLI28__MIN_BW_MASK 0x01C00000L 173995c1f7aaSFeifei Xu #define DAGB0_WRCLI28__OSD_LIMITER_ENABLE_MASK 0x02000000L 174095c1f7aaSFeifei Xu #define DAGB0_WRCLI28__MAX_OSD_MASK 0xFC000000L 174195c1f7aaSFeifei Xu //DAGB0_WRCLI29 174295c1f7aaSFeifei Xu #define DAGB0_WRCLI29__VIRT_CHAN__SHIFT 0x0 174395c1f7aaSFeifei Xu #define DAGB0_WRCLI29__CHECK_TLB_CREDIT__SHIFT 0x3 174495c1f7aaSFeifei Xu #define DAGB0_WRCLI29__URG_HIGH__SHIFT 0x4 174595c1f7aaSFeifei Xu #define DAGB0_WRCLI29__URG_LOW__SHIFT 0x8 174695c1f7aaSFeifei Xu #define DAGB0_WRCLI29__MAX_BW_ENABLE__SHIFT 0xc 174795c1f7aaSFeifei Xu #define DAGB0_WRCLI29__MAX_BW__SHIFT 0xd 174895c1f7aaSFeifei Xu #define DAGB0_WRCLI29__MIN_BW_ENABLE__SHIFT 0x15 174995c1f7aaSFeifei Xu #define DAGB0_WRCLI29__MIN_BW__SHIFT 0x16 175095c1f7aaSFeifei Xu #define DAGB0_WRCLI29__OSD_LIMITER_ENABLE__SHIFT 0x19 175195c1f7aaSFeifei Xu #define DAGB0_WRCLI29__MAX_OSD__SHIFT 0x1a 175295c1f7aaSFeifei Xu #define DAGB0_WRCLI29__VIRT_CHAN_MASK 0x00000007L 175395c1f7aaSFeifei Xu #define DAGB0_WRCLI29__CHECK_TLB_CREDIT_MASK 0x00000008L 175495c1f7aaSFeifei Xu #define DAGB0_WRCLI29__URG_HIGH_MASK 0x000000F0L 175595c1f7aaSFeifei Xu #define DAGB0_WRCLI29__URG_LOW_MASK 0x00000F00L 175695c1f7aaSFeifei Xu #define DAGB0_WRCLI29__MAX_BW_ENABLE_MASK 0x00001000L 175795c1f7aaSFeifei Xu #define DAGB0_WRCLI29__MAX_BW_MASK 0x001FE000L 175895c1f7aaSFeifei Xu #define DAGB0_WRCLI29__MIN_BW_ENABLE_MASK 0x00200000L 175995c1f7aaSFeifei Xu #define DAGB0_WRCLI29__MIN_BW_MASK 0x01C00000L 176095c1f7aaSFeifei Xu #define DAGB0_WRCLI29__OSD_LIMITER_ENABLE_MASK 0x02000000L 176195c1f7aaSFeifei Xu #define DAGB0_WRCLI29__MAX_OSD_MASK 0xFC000000L 176295c1f7aaSFeifei Xu //DAGB0_WRCLI30 176395c1f7aaSFeifei Xu #define DAGB0_WRCLI30__VIRT_CHAN__SHIFT 0x0 176495c1f7aaSFeifei Xu #define DAGB0_WRCLI30__CHECK_TLB_CREDIT__SHIFT 0x3 176595c1f7aaSFeifei Xu #define DAGB0_WRCLI30__URG_HIGH__SHIFT 0x4 176695c1f7aaSFeifei Xu #define DAGB0_WRCLI30__URG_LOW__SHIFT 0x8 176795c1f7aaSFeifei Xu #define DAGB0_WRCLI30__MAX_BW_ENABLE__SHIFT 0xc 176895c1f7aaSFeifei Xu #define DAGB0_WRCLI30__MAX_BW__SHIFT 0xd 176995c1f7aaSFeifei Xu #define DAGB0_WRCLI30__MIN_BW_ENABLE__SHIFT 0x15 177095c1f7aaSFeifei Xu #define DAGB0_WRCLI30__MIN_BW__SHIFT 0x16 177195c1f7aaSFeifei Xu #define DAGB0_WRCLI30__OSD_LIMITER_ENABLE__SHIFT 0x19 177295c1f7aaSFeifei Xu #define DAGB0_WRCLI30__MAX_OSD__SHIFT 0x1a 177395c1f7aaSFeifei Xu #define DAGB0_WRCLI30__VIRT_CHAN_MASK 0x00000007L 177495c1f7aaSFeifei Xu #define DAGB0_WRCLI30__CHECK_TLB_CREDIT_MASK 0x00000008L 177595c1f7aaSFeifei Xu #define DAGB0_WRCLI30__URG_HIGH_MASK 0x000000F0L 177695c1f7aaSFeifei Xu #define DAGB0_WRCLI30__URG_LOW_MASK 0x00000F00L 177795c1f7aaSFeifei Xu #define DAGB0_WRCLI30__MAX_BW_ENABLE_MASK 0x00001000L 177895c1f7aaSFeifei Xu #define DAGB0_WRCLI30__MAX_BW_MASK 0x001FE000L 177995c1f7aaSFeifei Xu #define DAGB0_WRCLI30__MIN_BW_ENABLE_MASK 0x00200000L 178095c1f7aaSFeifei Xu #define DAGB0_WRCLI30__MIN_BW_MASK 0x01C00000L 178195c1f7aaSFeifei Xu #define DAGB0_WRCLI30__OSD_LIMITER_ENABLE_MASK 0x02000000L 178295c1f7aaSFeifei Xu #define DAGB0_WRCLI30__MAX_OSD_MASK 0xFC000000L 178395c1f7aaSFeifei Xu //DAGB0_WRCLI31 178495c1f7aaSFeifei Xu #define DAGB0_WRCLI31__VIRT_CHAN__SHIFT 0x0 178595c1f7aaSFeifei Xu #define DAGB0_WRCLI31__CHECK_TLB_CREDIT__SHIFT 0x3 178695c1f7aaSFeifei Xu #define DAGB0_WRCLI31__URG_HIGH__SHIFT 0x4 178795c1f7aaSFeifei Xu #define DAGB0_WRCLI31__URG_LOW__SHIFT 0x8 178895c1f7aaSFeifei Xu #define DAGB0_WRCLI31__MAX_BW_ENABLE__SHIFT 0xc 178995c1f7aaSFeifei Xu #define DAGB0_WRCLI31__MAX_BW__SHIFT 0xd 179095c1f7aaSFeifei Xu #define DAGB0_WRCLI31__MIN_BW_ENABLE__SHIFT 0x15 179195c1f7aaSFeifei Xu #define DAGB0_WRCLI31__MIN_BW__SHIFT 0x16 179295c1f7aaSFeifei Xu #define DAGB0_WRCLI31__OSD_LIMITER_ENABLE__SHIFT 0x19 179395c1f7aaSFeifei Xu #define DAGB0_WRCLI31__MAX_OSD__SHIFT 0x1a 179495c1f7aaSFeifei Xu #define DAGB0_WRCLI31__VIRT_CHAN_MASK 0x00000007L 179595c1f7aaSFeifei Xu #define DAGB0_WRCLI31__CHECK_TLB_CREDIT_MASK 0x00000008L 179695c1f7aaSFeifei Xu #define DAGB0_WRCLI31__URG_HIGH_MASK 0x000000F0L 179795c1f7aaSFeifei Xu #define DAGB0_WRCLI31__URG_LOW_MASK 0x00000F00L 179895c1f7aaSFeifei Xu #define DAGB0_WRCLI31__MAX_BW_ENABLE_MASK 0x00001000L 179995c1f7aaSFeifei Xu #define DAGB0_WRCLI31__MAX_BW_MASK 0x001FE000L 180095c1f7aaSFeifei Xu #define DAGB0_WRCLI31__MIN_BW_ENABLE_MASK 0x00200000L 180195c1f7aaSFeifei Xu #define DAGB0_WRCLI31__MIN_BW_MASK 0x01C00000L 180295c1f7aaSFeifei Xu #define DAGB0_WRCLI31__OSD_LIMITER_ENABLE_MASK 0x02000000L 180395c1f7aaSFeifei Xu #define DAGB0_WRCLI31__MAX_OSD_MASK 0xFC000000L 180495c1f7aaSFeifei Xu //DAGB0_WR_CNTL 180595c1f7aaSFeifei Xu #define DAGB0_WR_CNTL__SCLK_FREQ__SHIFT 0x0 180695c1f7aaSFeifei Xu #define DAGB0_WR_CNTL__CLI_MAX_BW_WINDOW__SHIFT 0x4 180795c1f7aaSFeifei Xu #define DAGB0_WR_CNTL__VC_MAX_BW_WINDOW__SHIFT 0xa 180895c1f7aaSFeifei Xu #define DAGB0_WR_CNTL__IO_LEVEL_OVERRIDE_ENABLE__SHIFT 0x10 180995c1f7aaSFeifei Xu #define DAGB0_WR_CNTL__IO_LEVEL__SHIFT 0x11 181095c1f7aaSFeifei Xu #define DAGB0_WR_CNTL__IO_LEVEL_COMPLY_VC__SHIFT 0x14 181195c1f7aaSFeifei Xu #define DAGB0_WR_CNTL__SHARE_VC_NUM__SHIFT 0x17 181295c1f7aaSFeifei Xu #define DAGB0_WR_CNTL__SCLK_FREQ_MASK 0x0000000FL 181395c1f7aaSFeifei Xu #define DAGB0_WR_CNTL__CLI_MAX_BW_WINDOW_MASK 0x000003F0L 181495c1f7aaSFeifei Xu #define DAGB0_WR_CNTL__VC_MAX_BW_WINDOW_MASK 0x0000FC00L 181595c1f7aaSFeifei Xu #define DAGB0_WR_CNTL__IO_LEVEL_OVERRIDE_ENABLE_MASK 0x00010000L 181695c1f7aaSFeifei Xu #define DAGB0_WR_CNTL__IO_LEVEL_MASK 0x000E0000L 181795c1f7aaSFeifei Xu #define DAGB0_WR_CNTL__IO_LEVEL_COMPLY_VC_MASK 0x00700000L 181895c1f7aaSFeifei Xu #define DAGB0_WR_CNTL__SHARE_VC_NUM_MASK 0x03800000L 181995c1f7aaSFeifei Xu //DAGB0_WR_GMI_CNTL 182095c1f7aaSFeifei Xu #define DAGB0_WR_GMI_CNTL__EA_CREDIT__SHIFT 0x0 182195c1f7aaSFeifei Xu #define DAGB0_WR_GMI_CNTL__LEVEL__SHIFT 0x6 182295c1f7aaSFeifei Xu #define DAGB0_WR_GMI_CNTL__MAX_BURST__SHIFT 0x9 182395c1f7aaSFeifei Xu #define DAGB0_WR_GMI_CNTL__LAZY_TIMER__SHIFT 0xd 182495c1f7aaSFeifei Xu #define DAGB0_WR_GMI_CNTL__EA_CREDIT_MASK 0x0000003FL 182595c1f7aaSFeifei Xu #define DAGB0_WR_GMI_CNTL__LEVEL_MASK 0x000001C0L 182695c1f7aaSFeifei Xu #define DAGB0_WR_GMI_CNTL__MAX_BURST_MASK 0x00001E00L 182795c1f7aaSFeifei Xu #define DAGB0_WR_GMI_CNTL__LAZY_TIMER_MASK 0x0001E000L 182895c1f7aaSFeifei Xu //DAGB0_WR_ADDR_DAGB 182995c1f7aaSFeifei Xu #define DAGB0_WR_ADDR_DAGB__DAGB_ENABLE__SHIFT 0x0 183095c1f7aaSFeifei Xu #define DAGB0_WR_ADDR_DAGB__ENABLE_JUMP_AHEAD__SHIFT 0x3 183195c1f7aaSFeifei Xu #define DAGB0_WR_ADDR_DAGB__DISABLE_SELF_INIT__SHIFT 0x6 183295c1f7aaSFeifei Xu #define DAGB0_WR_ADDR_DAGB__WHOAMI__SHIFT 0x7 183395c1f7aaSFeifei Xu #define DAGB0_WR_ADDR_DAGB__DAGB_ENABLE_MASK 0x00000007L 183495c1f7aaSFeifei Xu #define DAGB0_WR_ADDR_DAGB__ENABLE_JUMP_AHEAD_MASK 0x00000038L 183595c1f7aaSFeifei Xu #define DAGB0_WR_ADDR_DAGB__DISABLE_SELF_INIT_MASK 0x00000040L 183695c1f7aaSFeifei Xu #define DAGB0_WR_ADDR_DAGB__WHOAMI_MASK 0x00001F80L 183795c1f7aaSFeifei Xu //DAGB0_WR_OUTPUT_DAGB_MAX_BURST 183895c1f7aaSFeifei Xu #define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC0__SHIFT 0x0 183995c1f7aaSFeifei Xu #define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC1__SHIFT 0x4 184095c1f7aaSFeifei Xu #define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC2__SHIFT 0x8 184195c1f7aaSFeifei Xu #define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC3__SHIFT 0xc 184295c1f7aaSFeifei Xu #define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC4__SHIFT 0x10 184395c1f7aaSFeifei Xu #define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC5__SHIFT 0x14 184495c1f7aaSFeifei Xu #define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC6__SHIFT 0x18 184595c1f7aaSFeifei Xu #define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC7__SHIFT 0x1c 184695c1f7aaSFeifei Xu #define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC0_MASK 0x0000000FL 184795c1f7aaSFeifei Xu #define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC1_MASK 0x000000F0L 184895c1f7aaSFeifei Xu #define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC2_MASK 0x00000F00L 184995c1f7aaSFeifei Xu #define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC3_MASK 0x0000F000L 185095c1f7aaSFeifei Xu #define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC4_MASK 0x000F0000L 185195c1f7aaSFeifei Xu #define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC5_MASK 0x00F00000L 185295c1f7aaSFeifei Xu #define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC6_MASK 0x0F000000L 185395c1f7aaSFeifei Xu #define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC7_MASK 0xF0000000L 185495c1f7aaSFeifei Xu //DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER 185595c1f7aaSFeifei Xu #define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC0__SHIFT 0x0 185695c1f7aaSFeifei Xu #define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC1__SHIFT 0x4 185795c1f7aaSFeifei Xu #define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC2__SHIFT 0x8 185895c1f7aaSFeifei Xu #define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC3__SHIFT 0xc 185995c1f7aaSFeifei Xu #define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC4__SHIFT 0x10 186095c1f7aaSFeifei Xu #define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC5__SHIFT 0x14 186195c1f7aaSFeifei Xu #define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC6__SHIFT 0x18 186295c1f7aaSFeifei Xu #define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC7__SHIFT 0x1c 186395c1f7aaSFeifei Xu #define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC0_MASK 0x0000000FL 186495c1f7aaSFeifei Xu #define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC1_MASK 0x000000F0L 186595c1f7aaSFeifei Xu #define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC2_MASK 0x00000F00L 186695c1f7aaSFeifei Xu #define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC3_MASK 0x0000F000L 186795c1f7aaSFeifei Xu #define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC4_MASK 0x000F0000L 186895c1f7aaSFeifei Xu #define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC5_MASK 0x00F00000L 186995c1f7aaSFeifei Xu #define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC6_MASK 0x0F000000L 187095c1f7aaSFeifei Xu #define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC7_MASK 0xF0000000L 187195c1f7aaSFeifei Xu //DAGB0_WR_CGTT_CLK_CTRL 187295c1f7aaSFeifei Xu #define DAGB0_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 187395c1f7aaSFeifei Xu #define DAGB0_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 187495c1f7aaSFeifei Xu #define DAGB0_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16 187595c1f7aaSFeifei Xu #define DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b 187695c1f7aaSFeifei Xu #define DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c 187795c1f7aaSFeifei Xu #define DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d 187895c1f7aaSFeifei Xu #define DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e 187995c1f7aaSFeifei Xu #define DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f 188095c1f7aaSFeifei Xu #define DAGB0_WR_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL 188195c1f7aaSFeifei Xu #define DAGB0_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L 188295c1f7aaSFeifei Xu #define DAGB0_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L 188395c1f7aaSFeifei Xu #define DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L 188495c1f7aaSFeifei Xu #define DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L 188595c1f7aaSFeifei Xu #define DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L 188695c1f7aaSFeifei Xu #define DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L 188795c1f7aaSFeifei Xu #define DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L 188895c1f7aaSFeifei Xu //DAGB0_L1TLB_WR_CGTT_CLK_CTRL 188995c1f7aaSFeifei Xu #define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 189095c1f7aaSFeifei Xu #define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 189195c1f7aaSFeifei Xu #define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16 189295c1f7aaSFeifei Xu #define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b 189395c1f7aaSFeifei Xu #define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c 189495c1f7aaSFeifei Xu #define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d 189595c1f7aaSFeifei Xu #define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e 189695c1f7aaSFeifei Xu #define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f 189795c1f7aaSFeifei Xu #define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL 189895c1f7aaSFeifei Xu #define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L 189995c1f7aaSFeifei Xu #define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L 190095c1f7aaSFeifei Xu #define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L 190195c1f7aaSFeifei Xu #define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L 190295c1f7aaSFeifei Xu #define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L 190395c1f7aaSFeifei Xu #define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L 190495c1f7aaSFeifei Xu #define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L 190595c1f7aaSFeifei Xu //DAGB0_ATCVM_WR_CGTT_CLK_CTRL 190695c1f7aaSFeifei Xu #define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 190795c1f7aaSFeifei Xu #define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 190895c1f7aaSFeifei Xu #define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16 190995c1f7aaSFeifei Xu #define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b 191095c1f7aaSFeifei Xu #define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c 191195c1f7aaSFeifei Xu #define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d 191295c1f7aaSFeifei Xu #define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e 191395c1f7aaSFeifei Xu #define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f 191495c1f7aaSFeifei Xu #define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL 191595c1f7aaSFeifei Xu #define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L 191695c1f7aaSFeifei Xu #define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L 191795c1f7aaSFeifei Xu #define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L 191895c1f7aaSFeifei Xu #define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L 191995c1f7aaSFeifei Xu #define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L 192095c1f7aaSFeifei Xu #define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L 192195c1f7aaSFeifei Xu #define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L 192295c1f7aaSFeifei Xu //DAGB0_WR_ADDR_DAGB_MAX_BURST0 192395c1f7aaSFeifei Xu #define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT0__SHIFT 0x0 192495c1f7aaSFeifei Xu #define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT1__SHIFT 0x4 192595c1f7aaSFeifei Xu #define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT2__SHIFT 0x8 192695c1f7aaSFeifei Xu #define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT3__SHIFT 0xc 192795c1f7aaSFeifei Xu #define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT4__SHIFT 0x10 192895c1f7aaSFeifei Xu #define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT5__SHIFT 0x14 192995c1f7aaSFeifei Xu #define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT6__SHIFT 0x18 193095c1f7aaSFeifei Xu #define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT7__SHIFT 0x1c 193195c1f7aaSFeifei Xu #define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT0_MASK 0x0000000FL 193295c1f7aaSFeifei Xu #define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT1_MASK 0x000000F0L 193395c1f7aaSFeifei Xu #define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT2_MASK 0x00000F00L 193495c1f7aaSFeifei Xu #define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT3_MASK 0x0000F000L 193595c1f7aaSFeifei Xu #define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT4_MASK 0x000F0000L 193695c1f7aaSFeifei Xu #define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT5_MASK 0x00F00000L 193795c1f7aaSFeifei Xu #define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT6_MASK 0x0F000000L 193895c1f7aaSFeifei Xu #define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT7_MASK 0xF0000000L 193995c1f7aaSFeifei Xu //DAGB0_WR_ADDR_DAGB_LAZY_TIMER0 194095c1f7aaSFeifei Xu #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT0__SHIFT 0x0 194195c1f7aaSFeifei Xu #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT1__SHIFT 0x4 194295c1f7aaSFeifei Xu #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT2__SHIFT 0x8 194395c1f7aaSFeifei Xu #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT3__SHIFT 0xc 194495c1f7aaSFeifei Xu #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT4__SHIFT 0x10 194595c1f7aaSFeifei Xu #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT5__SHIFT 0x14 194695c1f7aaSFeifei Xu #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT6__SHIFT 0x18 194795c1f7aaSFeifei Xu #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT7__SHIFT 0x1c 194895c1f7aaSFeifei Xu #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT0_MASK 0x0000000FL 194995c1f7aaSFeifei Xu #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT1_MASK 0x000000F0L 195095c1f7aaSFeifei Xu #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT2_MASK 0x00000F00L 195195c1f7aaSFeifei Xu #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT3_MASK 0x0000F000L 195295c1f7aaSFeifei Xu #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT4_MASK 0x000F0000L 195395c1f7aaSFeifei Xu #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT5_MASK 0x00F00000L 195495c1f7aaSFeifei Xu #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT6_MASK 0x0F000000L 195595c1f7aaSFeifei Xu #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT7_MASK 0xF0000000L 195695c1f7aaSFeifei Xu //DAGB0_WR_ADDR_DAGB_MAX_BURST1 195795c1f7aaSFeifei Xu #define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT8__SHIFT 0x0 195895c1f7aaSFeifei Xu #define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT9__SHIFT 0x4 195995c1f7aaSFeifei Xu #define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT10__SHIFT 0x8 196095c1f7aaSFeifei Xu #define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT11__SHIFT 0xc 196195c1f7aaSFeifei Xu #define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT12__SHIFT 0x10 196295c1f7aaSFeifei Xu #define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT13__SHIFT 0x14 196395c1f7aaSFeifei Xu #define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT14__SHIFT 0x18 196495c1f7aaSFeifei Xu #define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT15__SHIFT 0x1c 196595c1f7aaSFeifei Xu #define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT8_MASK 0x0000000FL 196695c1f7aaSFeifei Xu #define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT9_MASK 0x000000F0L 196795c1f7aaSFeifei Xu #define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT10_MASK 0x00000F00L 196895c1f7aaSFeifei Xu #define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT11_MASK 0x0000F000L 196995c1f7aaSFeifei Xu #define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT12_MASK 0x000F0000L 197095c1f7aaSFeifei Xu #define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT13_MASK 0x00F00000L 197195c1f7aaSFeifei Xu #define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT14_MASK 0x0F000000L 197295c1f7aaSFeifei Xu #define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT15_MASK 0xF0000000L 197395c1f7aaSFeifei Xu //DAGB0_WR_ADDR_DAGB_LAZY_TIMER1 197495c1f7aaSFeifei Xu #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT8__SHIFT 0x0 197595c1f7aaSFeifei Xu #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT9__SHIFT 0x4 197695c1f7aaSFeifei Xu #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT10__SHIFT 0x8 197795c1f7aaSFeifei Xu #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT11__SHIFT 0xc 197895c1f7aaSFeifei Xu #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT12__SHIFT 0x10 197995c1f7aaSFeifei Xu #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT13__SHIFT 0x14 198095c1f7aaSFeifei Xu #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT14__SHIFT 0x18 198195c1f7aaSFeifei Xu #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT15__SHIFT 0x1c 198295c1f7aaSFeifei Xu #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT8_MASK 0x0000000FL 198395c1f7aaSFeifei Xu #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT9_MASK 0x000000F0L 198495c1f7aaSFeifei Xu #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT10_MASK 0x00000F00L 198595c1f7aaSFeifei Xu #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT11_MASK 0x0000F000L 198695c1f7aaSFeifei Xu #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT12_MASK 0x000F0000L 198795c1f7aaSFeifei Xu #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT13_MASK 0x00F00000L 198895c1f7aaSFeifei Xu #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT14_MASK 0x0F000000L 198995c1f7aaSFeifei Xu #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT15_MASK 0xF0000000L 199095c1f7aaSFeifei Xu //DAGB0_WR_ADDR_DAGB_MAX_BURST2 199195c1f7aaSFeifei Xu #define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT16__SHIFT 0x0 199295c1f7aaSFeifei Xu #define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT17__SHIFT 0x4 199395c1f7aaSFeifei Xu #define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT18__SHIFT 0x8 199495c1f7aaSFeifei Xu #define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT19__SHIFT 0xc 199595c1f7aaSFeifei Xu #define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT20__SHIFT 0x10 199695c1f7aaSFeifei Xu #define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT21__SHIFT 0x14 199795c1f7aaSFeifei Xu #define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT22__SHIFT 0x18 199895c1f7aaSFeifei Xu #define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT23__SHIFT 0x1c 199995c1f7aaSFeifei Xu #define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT16_MASK 0x0000000FL 200095c1f7aaSFeifei Xu #define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT17_MASK 0x000000F0L 200195c1f7aaSFeifei Xu #define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT18_MASK 0x00000F00L 200295c1f7aaSFeifei Xu #define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT19_MASK 0x0000F000L 200395c1f7aaSFeifei Xu #define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT20_MASK 0x000F0000L 200495c1f7aaSFeifei Xu #define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT21_MASK 0x00F00000L 200595c1f7aaSFeifei Xu #define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT22_MASK 0x0F000000L 200695c1f7aaSFeifei Xu #define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT23_MASK 0xF0000000L 200795c1f7aaSFeifei Xu //DAGB0_WR_ADDR_DAGB_LAZY_TIMER2 200895c1f7aaSFeifei Xu #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT16__SHIFT 0x0 200995c1f7aaSFeifei Xu #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT17__SHIFT 0x4 201095c1f7aaSFeifei Xu #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT18__SHIFT 0x8 201195c1f7aaSFeifei Xu #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT19__SHIFT 0xc 201295c1f7aaSFeifei Xu #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT20__SHIFT 0x10 201395c1f7aaSFeifei Xu #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT21__SHIFT 0x14 201495c1f7aaSFeifei Xu #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT22__SHIFT 0x18 201595c1f7aaSFeifei Xu #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT23__SHIFT 0x1c 201695c1f7aaSFeifei Xu #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT16_MASK 0x0000000FL 201795c1f7aaSFeifei Xu #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT17_MASK 0x000000F0L 201895c1f7aaSFeifei Xu #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT18_MASK 0x00000F00L 201995c1f7aaSFeifei Xu #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT19_MASK 0x0000F000L 202095c1f7aaSFeifei Xu #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT20_MASK 0x000F0000L 202195c1f7aaSFeifei Xu #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT21_MASK 0x00F00000L 202295c1f7aaSFeifei Xu #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT22_MASK 0x0F000000L 202395c1f7aaSFeifei Xu #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT23_MASK 0xF0000000L 202495c1f7aaSFeifei Xu //DAGB0_WR_ADDR_DAGB_MAX_BURST3 202595c1f7aaSFeifei Xu #define DAGB0_WR_ADDR_DAGB_MAX_BURST3__CLIENT24__SHIFT 0x0 202695c1f7aaSFeifei Xu #define DAGB0_WR_ADDR_DAGB_MAX_BURST3__CLIENT25__SHIFT 0x4 202795c1f7aaSFeifei Xu #define DAGB0_WR_ADDR_DAGB_MAX_BURST3__CLIENT26__SHIFT 0x8 202895c1f7aaSFeifei Xu #define DAGB0_WR_ADDR_DAGB_MAX_BURST3__CLIENT27__SHIFT 0xc 202995c1f7aaSFeifei Xu #define DAGB0_WR_ADDR_DAGB_MAX_BURST3__CLIENT28__SHIFT 0x10 203095c1f7aaSFeifei Xu #define DAGB0_WR_ADDR_DAGB_MAX_BURST3__CLIENT29__SHIFT 0x14 203195c1f7aaSFeifei Xu #define DAGB0_WR_ADDR_DAGB_MAX_BURST3__CLIENT30__SHIFT 0x18 203295c1f7aaSFeifei Xu #define DAGB0_WR_ADDR_DAGB_MAX_BURST3__CLIENT31__SHIFT 0x1c 203395c1f7aaSFeifei Xu #define DAGB0_WR_ADDR_DAGB_MAX_BURST3__CLIENT24_MASK 0x0000000FL 203495c1f7aaSFeifei Xu #define DAGB0_WR_ADDR_DAGB_MAX_BURST3__CLIENT25_MASK 0x000000F0L 203595c1f7aaSFeifei Xu #define DAGB0_WR_ADDR_DAGB_MAX_BURST3__CLIENT26_MASK 0x00000F00L 203695c1f7aaSFeifei Xu #define DAGB0_WR_ADDR_DAGB_MAX_BURST3__CLIENT27_MASK 0x0000F000L 203795c1f7aaSFeifei Xu #define DAGB0_WR_ADDR_DAGB_MAX_BURST3__CLIENT28_MASK 0x000F0000L 203895c1f7aaSFeifei Xu #define DAGB0_WR_ADDR_DAGB_MAX_BURST3__CLIENT29_MASK 0x00F00000L 203995c1f7aaSFeifei Xu #define DAGB0_WR_ADDR_DAGB_MAX_BURST3__CLIENT30_MASK 0x0F000000L 204095c1f7aaSFeifei Xu #define DAGB0_WR_ADDR_DAGB_MAX_BURST3__CLIENT31_MASK 0xF0000000L 204195c1f7aaSFeifei Xu //DAGB0_WR_ADDR_DAGB_LAZY_TIMER3 204295c1f7aaSFeifei Xu #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER3__CLIENT24__SHIFT 0x0 204395c1f7aaSFeifei Xu #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER3__CLIENT25__SHIFT 0x4 204495c1f7aaSFeifei Xu #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER3__CLIENT26__SHIFT 0x8 204595c1f7aaSFeifei Xu #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER3__CLIENT27__SHIFT 0xc 204695c1f7aaSFeifei Xu #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER3__CLIENT28__SHIFT 0x10 204795c1f7aaSFeifei Xu #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER3__CLIENT29__SHIFT 0x14 204895c1f7aaSFeifei Xu #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER3__CLIENT30__SHIFT 0x18 204995c1f7aaSFeifei Xu #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER3__CLIENT31__SHIFT 0x1c 205095c1f7aaSFeifei Xu #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER3__CLIENT24_MASK 0x0000000FL 205195c1f7aaSFeifei Xu #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER3__CLIENT25_MASK 0x000000F0L 205295c1f7aaSFeifei Xu #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER3__CLIENT26_MASK 0x00000F00L 205395c1f7aaSFeifei Xu #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER3__CLIENT27_MASK 0x0000F000L 205495c1f7aaSFeifei Xu #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER3__CLIENT28_MASK 0x000F0000L 205595c1f7aaSFeifei Xu #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER3__CLIENT29_MASK 0x00F00000L 205695c1f7aaSFeifei Xu #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER3__CLIENT30_MASK 0x0F000000L 205795c1f7aaSFeifei Xu #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER3__CLIENT31_MASK 0xF0000000L 205895c1f7aaSFeifei Xu //DAGB0_WR_DATA_DAGB 205995c1f7aaSFeifei Xu #define DAGB0_WR_DATA_DAGB__DAGB_ENABLE__SHIFT 0x0 206095c1f7aaSFeifei Xu #define DAGB0_WR_DATA_DAGB__ENABLE_JUMP_AHEAD__SHIFT 0x3 206195c1f7aaSFeifei Xu #define DAGB0_WR_DATA_DAGB__DISABLE_SELF_INIT__SHIFT 0x6 206295c1f7aaSFeifei Xu #define DAGB0_WR_DATA_DAGB__WHOAMI__SHIFT 0x7 206395c1f7aaSFeifei Xu #define DAGB0_WR_DATA_DAGB__DAGB_ENABLE_MASK 0x00000007L 206495c1f7aaSFeifei Xu #define DAGB0_WR_DATA_DAGB__ENABLE_JUMP_AHEAD_MASK 0x00000038L 206595c1f7aaSFeifei Xu #define DAGB0_WR_DATA_DAGB__DISABLE_SELF_INIT_MASK 0x00000040L 206695c1f7aaSFeifei Xu #define DAGB0_WR_DATA_DAGB__WHOAMI_MASK 0x00001F80L 206795c1f7aaSFeifei Xu //DAGB0_WR_DATA_DAGB_MAX_BURST0 206895c1f7aaSFeifei Xu #define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT0__SHIFT 0x0 206995c1f7aaSFeifei Xu #define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT1__SHIFT 0x4 207095c1f7aaSFeifei Xu #define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT2__SHIFT 0x8 207195c1f7aaSFeifei Xu #define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT3__SHIFT 0xc 207295c1f7aaSFeifei Xu #define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT4__SHIFT 0x10 207395c1f7aaSFeifei Xu #define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT5__SHIFT 0x14 207495c1f7aaSFeifei Xu #define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT6__SHIFT 0x18 207595c1f7aaSFeifei Xu #define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT7__SHIFT 0x1c 207695c1f7aaSFeifei Xu #define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT0_MASK 0x0000000FL 207795c1f7aaSFeifei Xu #define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT1_MASK 0x000000F0L 207895c1f7aaSFeifei Xu #define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT2_MASK 0x00000F00L 207995c1f7aaSFeifei Xu #define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT3_MASK 0x0000F000L 208095c1f7aaSFeifei Xu #define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT4_MASK 0x000F0000L 208195c1f7aaSFeifei Xu #define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT5_MASK 0x00F00000L 208295c1f7aaSFeifei Xu #define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT6_MASK 0x0F000000L 208395c1f7aaSFeifei Xu #define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT7_MASK 0xF0000000L 208495c1f7aaSFeifei Xu //DAGB0_WR_DATA_DAGB_LAZY_TIMER0 208595c1f7aaSFeifei Xu #define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT0__SHIFT 0x0 208695c1f7aaSFeifei Xu #define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT1__SHIFT 0x4 208795c1f7aaSFeifei Xu #define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT2__SHIFT 0x8 208895c1f7aaSFeifei Xu #define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT3__SHIFT 0xc 208995c1f7aaSFeifei Xu #define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT4__SHIFT 0x10 209095c1f7aaSFeifei Xu #define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT5__SHIFT 0x14 209195c1f7aaSFeifei Xu #define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT6__SHIFT 0x18 209295c1f7aaSFeifei Xu #define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT7__SHIFT 0x1c 209395c1f7aaSFeifei Xu #define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT0_MASK 0x0000000FL 209495c1f7aaSFeifei Xu #define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT1_MASK 0x000000F0L 209595c1f7aaSFeifei Xu #define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT2_MASK 0x00000F00L 209695c1f7aaSFeifei Xu #define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT3_MASK 0x0000F000L 209795c1f7aaSFeifei Xu #define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT4_MASK 0x000F0000L 209895c1f7aaSFeifei Xu #define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT5_MASK 0x00F00000L 209995c1f7aaSFeifei Xu #define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT6_MASK 0x0F000000L 210095c1f7aaSFeifei Xu #define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT7_MASK 0xF0000000L 210195c1f7aaSFeifei Xu //DAGB0_WR_DATA_DAGB_MAX_BURST1 210295c1f7aaSFeifei Xu #define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT8__SHIFT 0x0 210395c1f7aaSFeifei Xu #define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT9__SHIFT 0x4 210495c1f7aaSFeifei Xu #define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT10__SHIFT 0x8 210595c1f7aaSFeifei Xu #define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT11__SHIFT 0xc 210695c1f7aaSFeifei Xu #define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT12__SHIFT 0x10 210795c1f7aaSFeifei Xu #define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT13__SHIFT 0x14 210895c1f7aaSFeifei Xu #define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT14__SHIFT 0x18 210995c1f7aaSFeifei Xu #define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT15__SHIFT 0x1c 211095c1f7aaSFeifei Xu #define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT8_MASK 0x0000000FL 211195c1f7aaSFeifei Xu #define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT9_MASK 0x000000F0L 211295c1f7aaSFeifei Xu #define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT10_MASK 0x00000F00L 211395c1f7aaSFeifei Xu #define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT11_MASK 0x0000F000L 211495c1f7aaSFeifei Xu #define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT12_MASK 0x000F0000L 211595c1f7aaSFeifei Xu #define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT13_MASK 0x00F00000L 211695c1f7aaSFeifei Xu #define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT14_MASK 0x0F000000L 211795c1f7aaSFeifei Xu #define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT15_MASK 0xF0000000L 211895c1f7aaSFeifei Xu //DAGB0_WR_DATA_DAGB_LAZY_TIMER1 211995c1f7aaSFeifei Xu #define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT8__SHIFT 0x0 212095c1f7aaSFeifei Xu #define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT9__SHIFT 0x4 212195c1f7aaSFeifei Xu #define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT10__SHIFT 0x8 212295c1f7aaSFeifei Xu #define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT11__SHIFT 0xc 212395c1f7aaSFeifei Xu #define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT12__SHIFT 0x10 212495c1f7aaSFeifei Xu #define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT13__SHIFT 0x14 212595c1f7aaSFeifei Xu #define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT14__SHIFT 0x18 212695c1f7aaSFeifei Xu #define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT15__SHIFT 0x1c 212795c1f7aaSFeifei Xu #define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT8_MASK 0x0000000FL 212895c1f7aaSFeifei Xu #define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT9_MASK 0x000000F0L 212995c1f7aaSFeifei Xu #define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT10_MASK 0x00000F00L 213095c1f7aaSFeifei Xu #define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT11_MASK 0x0000F000L 213195c1f7aaSFeifei Xu #define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT12_MASK 0x000F0000L 213295c1f7aaSFeifei Xu #define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT13_MASK 0x00F00000L 213395c1f7aaSFeifei Xu #define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT14_MASK 0x0F000000L 213495c1f7aaSFeifei Xu #define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT15_MASK 0xF0000000L 213595c1f7aaSFeifei Xu //DAGB0_WR_DATA_DAGB_MAX_BURST2 213695c1f7aaSFeifei Xu #define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT16__SHIFT 0x0 213795c1f7aaSFeifei Xu #define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT17__SHIFT 0x4 213895c1f7aaSFeifei Xu #define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT18__SHIFT 0x8 213995c1f7aaSFeifei Xu #define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT19__SHIFT 0xc 214095c1f7aaSFeifei Xu #define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT20__SHIFT 0x10 214195c1f7aaSFeifei Xu #define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT21__SHIFT 0x14 214295c1f7aaSFeifei Xu #define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT22__SHIFT 0x18 214395c1f7aaSFeifei Xu #define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT23__SHIFT 0x1c 214495c1f7aaSFeifei Xu #define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT16_MASK 0x0000000FL 214595c1f7aaSFeifei Xu #define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT17_MASK 0x000000F0L 214695c1f7aaSFeifei Xu #define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT18_MASK 0x00000F00L 214795c1f7aaSFeifei Xu #define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT19_MASK 0x0000F000L 214895c1f7aaSFeifei Xu #define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT20_MASK 0x000F0000L 214995c1f7aaSFeifei Xu #define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT21_MASK 0x00F00000L 215095c1f7aaSFeifei Xu #define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT22_MASK 0x0F000000L 215195c1f7aaSFeifei Xu #define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT23_MASK 0xF0000000L 215295c1f7aaSFeifei Xu //DAGB0_WR_DATA_DAGB_LAZY_TIMER2 215395c1f7aaSFeifei Xu #define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT16__SHIFT 0x0 215495c1f7aaSFeifei Xu #define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT17__SHIFT 0x4 215595c1f7aaSFeifei Xu #define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT18__SHIFT 0x8 215695c1f7aaSFeifei Xu #define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT19__SHIFT 0xc 215795c1f7aaSFeifei Xu #define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT20__SHIFT 0x10 215895c1f7aaSFeifei Xu #define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT21__SHIFT 0x14 215995c1f7aaSFeifei Xu #define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT22__SHIFT 0x18 216095c1f7aaSFeifei Xu #define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT23__SHIFT 0x1c 216195c1f7aaSFeifei Xu #define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT16_MASK 0x0000000FL 216295c1f7aaSFeifei Xu #define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT17_MASK 0x000000F0L 216395c1f7aaSFeifei Xu #define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT18_MASK 0x00000F00L 216495c1f7aaSFeifei Xu #define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT19_MASK 0x0000F000L 216595c1f7aaSFeifei Xu #define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT20_MASK 0x000F0000L 216695c1f7aaSFeifei Xu #define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT21_MASK 0x00F00000L 216795c1f7aaSFeifei Xu #define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT22_MASK 0x0F000000L 216895c1f7aaSFeifei Xu #define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT23_MASK 0xF0000000L 216995c1f7aaSFeifei Xu //DAGB0_WR_DATA_DAGB_MAX_BURST3 217095c1f7aaSFeifei Xu #define DAGB0_WR_DATA_DAGB_MAX_BURST3__CLIENT24__SHIFT 0x0 217195c1f7aaSFeifei Xu #define DAGB0_WR_DATA_DAGB_MAX_BURST3__CLIENT25__SHIFT 0x4 217295c1f7aaSFeifei Xu #define DAGB0_WR_DATA_DAGB_MAX_BURST3__CLIENT26__SHIFT 0x8 217395c1f7aaSFeifei Xu #define DAGB0_WR_DATA_DAGB_MAX_BURST3__CLIENT27__SHIFT 0xc 217495c1f7aaSFeifei Xu #define DAGB0_WR_DATA_DAGB_MAX_BURST3__CLIENT28__SHIFT 0x10 217595c1f7aaSFeifei Xu #define DAGB0_WR_DATA_DAGB_MAX_BURST3__CLIENT29__SHIFT 0x14 217695c1f7aaSFeifei Xu #define DAGB0_WR_DATA_DAGB_MAX_BURST3__CLIENT30__SHIFT 0x18 217795c1f7aaSFeifei Xu #define DAGB0_WR_DATA_DAGB_MAX_BURST3__CLIENT31__SHIFT 0x1c 217895c1f7aaSFeifei Xu #define DAGB0_WR_DATA_DAGB_MAX_BURST3__CLIENT24_MASK 0x0000000FL 217995c1f7aaSFeifei Xu #define DAGB0_WR_DATA_DAGB_MAX_BURST3__CLIENT25_MASK 0x000000F0L 218095c1f7aaSFeifei Xu #define DAGB0_WR_DATA_DAGB_MAX_BURST3__CLIENT26_MASK 0x00000F00L 218195c1f7aaSFeifei Xu #define DAGB0_WR_DATA_DAGB_MAX_BURST3__CLIENT27_MASK 0x0000F000L 218295c1f7aaSFeifei Xu #define DAGB0_WR_DATA_DAGB_MAX_BURST3__CLIENT28_MASK 0x000F0000L 218395c1f7aaSFeifei Xu #define DAGB0_WR_DATA_DAGB_MAX_BURST3__CLIENT29_MASK 0x00F00000L 218495c1f7aaSFeifei Xu #define DAGB0_WR_DATA_DAGB_MAX_BURST3__CLIENT30_MASK 0x0F000000L 218595c1f7aaSFeifei Xu #define DAGB0_WR_DATA_DAGB_MAX_BURST3__CLIENT31_MASK 0xF0000000L 218695c1f7aaSFeifei Xu //DAGB0_WR_DATA_DAGB_LAZY_TIMER3 218795c1f7aaSFeifei Xu #define DAGB0_WR_DATA_DAGB_LAZY_TIMER3__CLIENT24__SHIFT 0x0 218895c1f7aaSFeifei Xu #define DAGB0_WR_DATA_DAGB_LAZY_TIMER3__CLIENT25__SHIFT 0x4 218995c1f7aaSFeifei Xu #define DAGB0_WR_DATA_DAGB_LAZY_TIMER3__CLIENT26__SHIFT 0x8 219095c1f7aaSFeifei Xu #define DAGB0_WR_DATA_DAGB_LAZY_TIMER3__CLIENT27__SHIFT 0xc 219195c1f7aaSFeifei Xu #define DAGB0_WR_DATA_DAGB_LAZY_TIMER3__CLIENT28__SHIFT 0x10 219295c1f7aaSFeifei Xu #define DAGB0_WR_DATA_DAGB_LAZY_TIMER3__CLIENT29__SHIFT 0x14 219395c1f7aaSFeifei Xu #define DAGB0_WR_DATA_DAGB_LAZY_TIMER3__CLIENT30__SHIFT 0x18 219495c1f7aaSFeifei Xu #define DAGB0_WR_DATA_DAGB_LAZY_TIMER3__CLIENT31__SHIFT 0x1c 219595c1f7aaSFeifei Xu #define DAGB0_WR_DATA_DAGB_LAZY_TIMER3__CLIENT24_MASK 0x0000000FL 219695c1f7aaSFeifei Xu #define DAGB0_WR_DATA_DAGB_LAZY_TIMER3__CLIENT25_MASK 0x000000F0L 219795c1f7aaSFeifei Xu #define DAGB0_WR_DATA_DAGB_LAZY_TIMER3__CLIENT26_MASK 0x00000F00L 219895c1f7aaSFeifei Xu #define DAGB0_WR_DATA_DAGB_LAZY_TIMER3__CLIENT27_MASK 0x0000F000L 219995c1f7aaSFeifei Xu #define DAGB0_WR_DATA_DAGB_LAZY_TIMER3__CLIENT28_MASK 0x000F0000L 220095c1f7aaSFeifei Xu #define DAGB0_WR_DATA_DAGB_LAZY_TIMER3__CLIENT29_MASK 0x00F00000L 220195c1f7aaSFeifei Xu #define DAGB0_WR_DATA_DAGB_LAZY_TIMER3__CLIENT30_MASK 0x0F000000L 220295c1f7aaSFeifei Xu #define DAGB0_WR_DATA_DAGB_LAZY_TIMER3__CLIENT31_MASK 0xF0000000L 220395c1f7aaSFeifei Xu //DAGB0_WR_VC0_CNTL 220495c1f7aaSFeifei Xu #define DAGB0_WR_VC0_CNTL__STOR_CREDIT__SHIFT 0x0 220595c1f7aaSFeifei Xu #define DAGB0_WR_VC0_CNTL__EA_CREDIT__SHIFT 0x5 220695c1f7aaSFeifei Xu #define DAGB0_WR_VC0_CNTL__MAX_BW_ENABLE__SHIFT 0xb 220795c1f7aaSFeifei Xu #define DAGB0_WR_VC0_CNTL__MAX_BW__SHIFT 0xc 220895c1f7aaSFeifei Xu #define DAGB0_WR_VC0_CNTL__MIN_BW_ENABLE__SHIFT 0x14 220995c1f7aaSFeifei Xu #define DAGB0_WR_VC0_CNTL__MIN_BW__SHIFT 0x15 221095c1f7aaSFeifei Xu #define DAGB0_WR_VC0_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 221195c1f7aaSFeifei Xu #define DAGB0_WR_VC0_CNTL__MAX_OSD__SHIFT 0x19 221295c1f7aaSFeifei Xu #define DAGB0_WR_VC0_CNTL__STOR_CREDIT_MASK 0x0000001FL 221395c1f7aaSFeifei Xu #define DAGB0_WR_VC0_CNTL__EA_CREDIT_MASK 0x000007E0L 221495c1f7aaSFeifei Xu #define DAGB0_WR_VC0_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 221595c1f7aaSFeifei Xu #define DAGB0_WR_VC0_CNTL__MAX_BW_MASK 0x000FF000L 221695c1f7aaSFeifei Xu #define DAGB0_WR_VC0_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 221795c1f7aaSFeifei Xu #define DAGB0_WR_VC0_CNTL__MIN_BW_MASK 0x00E00000L 221895c1f7aaSFeifei Xu #define DAGB0_WR_VC0_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 221995c1f7aaSFeifei Xu #define DAGB0_WR_VC0_CNTL__MAX_OSD_MASK 0xFE000000L 222095c1f7aaSFeifei Xu //DAGB0_WR_VC1_CNTL 222195c1f7aaSFeifei Xu #define DAGB0_WR_VC1_CNTL__STOR_CREDIT__SHIFT 0x0 222295c1f7aaSFeifei Xu #define DAGB0_WR_VC1_CNTL__EA_CREDIT__SHIFT 0x5 222395c1f7aaSFeifei Xu #define DAGB0_WR_VC1_CNTL__MAX_BW_ENABLE__SHIFT 0xb 222495c1f7aaSFeifei Xu #define DAGB0_WR_VC1_CNTL__MAX_BW__SHIFT 0xc 222595c1f7aaSFeifei Xu #define DAGB0_WR_VC1_CNTL__MIN_BW_ENABLE__SHIFT 0x14 222695c1f7aaSFeifei Xu #define DAGB0_WR_VC1_CNTL__MIN_BW__SHIFT 0x15 222795c1f7aaSFeifei Xu #define DAGB0_WR_VC1_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 222895c1f7aaSFeifei Xu #define DAGB0_WR_VC1_CNTL__MAX_OSD__SHIFT 0x19 222995c1f7aaSFeifei Xu #define DAGB0_WR_VC1_CNTL__STOR_CREDIT_MASK 0x0000001FL 223095c1f7aaSFeifei Xu #define DAGB0_WR_VC1_CNTL__EA_CREDIT_MASK 0x000007E0L 223195c1f7aaSFeifei Xu #define DAGB0_WR_VC1_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 223295c1f7aaSFeifei Xu #define DAGB0_WR_VC1_CNTL__MAX_BW_MASK 0x000FF000L 223395c1f7aaSFeifei Xu #define DAGB0_WR_VC1_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 223495c1f7aaSFeifei Xu #define DAGB0_WR_VC1_CNTL__MIN_BW_MASK 0x00E00000L 223595c1f7aaSFeifei Xu #define DAGB0_WR_VC1_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 223695c1f7aaSFeifei Xu #define DAGB0_WR_VC1_CNTL__MAX_OSD_MASK 0xFE000000L 223795c1f7aaSFeifei Xu //DAGB0_WR_VC2_CNTL 223895c1f7aaSFeifei Xu #define DAGB0_WR_VC2_CNTL__STOR_CREDIT__SHIFT 0x0 223995c1f7aaSFeifei Xu #define DAGB0_WR_VC2_CNTL__EA_CREDIT__SHIFT 0x5 224095c1f7aaSFeifei Xu #define DAGB0_WR_VC2_CNTL__MAX_BW_ENABLE__SHIFT 0xb 224195c1f7aaSFeifei Xu #define DAGB0_WR_VC2_CNTL__MAX_BW__SHIFT 0xc 224295c1f7aaSFeifei Xu #define DAGB0_WR_VC2_CNTL__MIN_BW_ENABLE__SHIFT 0x14 224395c1f7aaSFeifei Xu #define DAGB0_WR_VC2_CNTL__MIN_BW__SHIFT 0x15 224495c1f7aaSFeifei Xu #define DAGB0_WR_VC2_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 224595c1f7aaSFeifei Xu #define DAGB0_WR_VC2_CNTL__MAX_OSD__SHIFT 0x19 224695c1f7aaSFeifei Xu #define DAGB0_WR_VC2_CNTL__STOR_CREDIT_MASK 0x0000001FL 224795c1f7aaSFeifei Xu #define DAGB0_WR_VC2_CNTL__EA_CREDIT_MASK 0x000007E0L 224895c1f7aaSFeifei Xu #define DAGB0_WR_VC2_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 224995c1f7aaSFeifei Xu #define DAGB0_WR_VC2_CNTL__MAX_BW_MASK 0x000FF000L 225095c1f7aaSFeifei Xu #define DAGB0_WR_VC2_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 225195c1f7aaSFeifei Xu #define DAGB0_WR_VC2_CNTL__MIN_BW_MASK 0x00E00000L 225295c1f7aaSFeifei Xu #define DAGB0_WR_VC2_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 225395c1f7aaSFeifei Xu #define DAGB0_WR_VC2_CNTL__MAX_OSD_MASK 0xFE000000L 225495c1f7aaSFeifei Xu //DAGB0_WR_VC3_CNTL 225595c1f7aaSFeifei Xu #define DAGB0_WR_VC3_CNTL__STOR_CREDIT__SHIFT 0x0 225695c1f7aaSFeifei Xu #define DAGB0_WR_VC3_CNTL__EA_CREDIT__SHIFT 0x5 225795c1f7aaSFeifei Xu #define DAGB0_WR_VC3_CNTL__MAX_BW_ENABLE__SHIFT 0xb 225895c1f7aaSFeifei Xu #define DAGB0_WR_VC3_CNTL__MAX_BW__SHIFT 0xc 225995c1f7aaSFeifei Xu #define DAGB0_WR_VC3_CNTL__MIN_BW_ENABLE__SHIFT 0x14 226095c1f7aaSFeifei Xu #define DAGB0_WR_VC3_CNTL__MIN_BW__SHIFT 0x15 226195c1f7aaSFeifei Xu #define DAGB0_WR_VC3_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 226295c1f7aaSFeifei Xu #define DAGB0_WR_VC3_CNTL__MAX_OSD__SHIFT 0x19 226395c1f7aaSFeifei Xu #define DAGB0_WR_VC3_CNTL__STOR_CREDIT_MASK 0x0000001FL 226495c1f7aaSFeifei Xu #define DAGB0_WR_VC3_CNTL__EA_CREDIT_MASK 0x000007E0L 226595c1f7aaSFeifei Xu #define DAGB0_WR_VC3_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 226695c1f7aaSFeifei Xu #define DAGB0_WR_VC3_CNTL__MAX_BW_MASK 0x000FF000L 226795c1f7aaSFeifei Xu #define DAGB0_WR_VC3_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 226895c1f7aaSFeifei Xu #define DAGB0_WR_VC3_CNTL__MIN_BW_MASK 0x00E00000L 226995c1f7aaSFeifei Xu #define DAGB0_WR_VC3_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 227095c1f7aaSFeifei Xu #define DAGB0_WR_VC3_CNTL__MAX_OSD_MASK 0xFE000000L 227195c1f7aaSFeifei Xu //DAGB0_WR_VC4_CNTL 227295c1f7aaSFeifei Xu #define DAGB0_WR_VC4_CNTL__STOR_CREDIT__SHIFT 0x0 227395c1f7aaSFeifei Xu #define DAGB0_WR_VC4_CNTL__EA_CREDIT__SHIFT 0x5 227495c1f7aaSFeifei Xu #define DAGB0_WR_VC4_CNTL__MAX_BW_ENABLE__SHIFT 0xb 227595c1f7aaSFeifei Xu #define DAGB0_WR_VC4_CNTL__MAX_BW__SHIFT 0xc 227695c1f7aaSFeifei Xu #define DAGB0_WR_VC4_CNTL__MIN_BW_ENABLE__SHIFT 0x14 227795c1f7aaSFeifei Xu #define DAGB0_WR_VC4_CNTL__MIN_BW__SHIFT 0x15 227895c1f7aaSFeifei Xu #define DAGB0_WR_VC4_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 227995c1f7aaSFeifei Xu #define DAGB0_WR_VC4_CNTL__MAX_OSD__SHIFT 0x19 228095c1f7aaSFeifei Xu #define DAGB0_WR_VC4_CNTL__STOR_CREDIT_MASK 0x0000001FL 228195c1f7aaSFeifei Xu #define DAGB0_WR_VC4_CNTL__EA_CREDIT_MASK 0x000007E0L 228295c1f7aaSFeifei Xu #define DAGB0_WR_VC4_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 228395c1f7aaSFeifei Xu #define DAGB0_WR_VC4_CNTL__MAX_BW_MASK 0x000FF000L 228495c1f7aaSFeifei Xu #define DAGB0_WR_VC4_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 228595c1f7aaSFeifei Xu #define DAGB0_WR_VC4_CNTL__MIN_BW_MASK 0x00E00000L 228695c1f7aaSFeifei Xu #define DAGB0_WR_VC4_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 228795c1f7aaSFeifei Xu #define DAGB0_WR_VC4_CNTL__MAX_OSD_MASK 0xFE000000L 228895c1f7aaSFeifei Xu //DAGB0_WR_VC5_CNTL 228995c1f7aaSFeifei Xu #define DAGB0_WR_VC5_CNTL__STOR_CREDIT__SHIFT 0x0 229095c1f7aaSFeifei Xu #define DAGB0_WR_VC5_CNTL__EA_CREDIT__SHIFT 0x5 229195c1f7aaSFeifei Xu #define DAGB0_WR_VC5_CNTL__MAX_BW_ENABLE__SHIFT 0xb 229295c1f7aaSFeifei Xu #define DAGB0_WR_VC5_CNTL__MAX_BW__SHIFT 0xc 229395c1f7aaSFeifei Xu #define DAGB0_WR_VC5_CNTL__MIN_BW_ENABLE__SHIFT 0x14 229495c1f7aaSFeifei Xu #define DAGB0_WR_VC5_CNTL__MIN_BW__SHIFT 0x15 229595c1f7aaSFeifei Xu #define DAGB0_WR_VC5_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 229695c1f7aaSFeifei Xu #define DAGB0_WR_VC5_CNTL__MAX_OSD__SHIFT 0x19 229795c1f7aaSFeifei Xu #define DAGB0_WR_VC5_CNTL__STOR_CREDIT_MASK 0x0000001FL 229895c1f7aaSFeifei Xu #define DAGB0_WR_VC5_CNTL__EA_CREDIT_MASK 0x000007E0L 229995c1f7aaSFeifei Xu #define DAGB0_WR_VC5_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 230095c1f7aaSFeifei Xu #define DAGB0_WR_VC5_CNTL__MAX_BW_MASK 0x000FF000L 230195c1f7aaSFeifei Xu #define DAGB0_WR_VC5_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 230295c1f7aaSFeifei Xu #define DAGB0_WR_VC5_CNTL__MIN_BW_MASK 0x00E00000L 230395c1f7aaSFeifei Xu #define DAGB0_WR_VC5_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 230495c1f7aaSFeifei Xu #define DAGB0_WR_VC5_CNTL__MAX_OSD_MASK 0xFE000000L 230595c1f7aaSFeifei Xu //DAGB0_WR_VC6_CNTL 230695c1f7aaSFeifei Xu #define DAGB0_WR_VC6_CNTL__STOR_CREDIT__SHIFT 0x0 230795c1f7aaSFeifei Xu #define DAGB0_WR_VC6_CNTL__EA_CREDIT__SHIFT 0x5 230895c1f7aaSFeifei Xu #define DAGB0_WR_VC6_CNTL__MAX_BW_ENABLE__SHIFT 0xb 230995c1f7aaSFeifei Xu #define DAGB0_WR_VC6_CNTL__MAX_BW__SHIFT 0xc 231095c1f7aaSFeifei Xu #define DAGB0_WR_VC6_CNTL__MIN_BW_ENABLE__SHIFT 0x14 231195c1f7aaSFeifei Xu #define DAGB0_WR_VC6_CNTL__MIN_BW__SHIFT 0x15 231295c1f7aaSFeifei Xu #define DAGB0_WR_VC6_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 231395c1f7aaSFeifei Xu #define DAGB0_WR_VC6_CNTL__MAX_OSD__SHIFT 0x19 231495c1f7aaSFeifei Xu #define DAGB0_WR_VC6_CNTL__STOR_CREDIT_MASK 0x0000001FL 231595c1f7aaSFeifei Xu #define DAGB0_WR_VC6_CNTL__EA_CREDIT_MASK 0x000007E0L 231695c1f7aaSFeifei Xu #define DAGB0_WR_VC6_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 231795c1f7aaSFeifei Xu #define DAGB0_WR_VC6_CNTL__MAX_BW_MASK 0x000FF000L 231895c1f7aaSFeifei Xu #define DAGB0_WR_VC6_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 231995c1f7aaSFeifei Xu #define DAGB0_WR_VC6_CNTL__MIN_BW_MASK 0x00E00000L 232095c1f7aaSFeifei Xu #define DAGB0_WR_VC6_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 232195c1f7aaSFeifei Xu #define DAGB0_WR_VC6_CNTL__MAX_OSD_MASK 0xFE000000L 232295c1f7aaSFeifei Xu //DAGB0_WR_VC7_CNTL 232395c1f7aaSFeifei Xu #define DAGB0_WR_VC7_CNTL__STOR_CREDIT__SHIFT 0x0 232495c1f7aaSFeifei Xu #define DAGB0_WR_VC7_CNTL__EA_CREDIT__SHIFT 0x5 232595c1f7aaSFeifei Xu #define DAGB0_WR_VC7_CNTL__MAX_BW_ENABLE__SHIFT 0xb 232695c1f7aaSFeifei Xu #define DAGB0_WR_VC7_CNTL__MAX_BW__SHIFT 0xc 232795c1f7aaSFeifei Xu #define DAGB0_WR_VC7_CNTL__MIN_BW_ENABLE__SHIFT 0x14 232895c1f7aaSFeifei Xu #define DAGB0_WR_VC7_CNTL__MIN_BW__SHIFT 0x15 232995c1f7aaSFeifei Xu #define DAGB0_WR_VC7_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 233095c1f7aaSFeifei Xu #define DAGB0_WR_VC7_CNTL__MAX_OSD__SHIFT 0x19 233195c1f7aaSFeifei Xu #define DAGB0_WR_VC7_CNTL__STOR_CREDIT_MASK 0x0000001FL 233295c1f7aaSFeifei Xu #define DAGB0_WR_VC7_CNTL__EA_CREDIT_MASK 0x000007E0L 233395c1f7aaSFeifei Xu #define DAGB0_WR_VC7_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 233495c1f7aaSFeifei Xu #define DAGB0_WR_VC7_CNTL__MAX_BW_MASK 0x000FF000L 233595c1f7aaSFeifei Xu #define DAGB0_WR_VC7_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 233695c1f7aaSFeifei Xu #define DAGB0_WR_VC7_CNTL__MIN_BW_MASK 0x00E00000L 233795c1f7aaSFeifei Xu #define DAGB0_WR_VC7_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 233895c1f7aaSFeifei Xu #define DAGB0_WR_VC7_CNTL__MAX_OSD_MASK 0xFE000000L 233995c1f7aaSFeifei Xu //DAGB0_WR_CNTL_MISC 234095c1f7aaSFeifei Xu #define DAGB0_WR_CNTL_MISC__STOR_POOL_CREDIT__SHIFT 0x0 234195c1f7aaSFeifei Xu #define DAGB0_WR_CNTL_MISC__EA_POOL_CREDIT__SHIFT 0x6 234295c1f7aaSFeifei Xu #define DAGB0_WR_CNTL_MISC__IO_EA_CREDIT__SHIFT 0xd 234395c1f7aaSFeifei Xu #define DAGB0_WR_CNTL_MISC__STOR_CC_LEGACY_MODE__SHIFT 0x13 234495c1f7aaSFeifei Xu #define DAGB0_WR_CNTL_MISC__EA_CC_LEGACY_MODE__SHIFT 0x14 234595c1f7aaSFeifei Xu #define DAGB0_WR_CNTL_MISC__UTCL2_CID__SHIFT 0x15 234695c1f7aaSFeifei Xu #define DAGB0_WR_CNTL_MISC__STOR_POOL_CREDIT_MASK 0x0000003FL 234795c1f7aaSFeifei Xu #define DAGB0_WR_CNTL_MISC__EA_POOL_CREDIT_MASK 0x00001FC0L 234895c1f7aaSFeifei Xu #define DAGB0_WR_CNTL_MISC__IO_EA_CREDIT_MASK 0x0007E000L 234995c1f7aaSFeifei Xu #define DAGB0_WR_CNTL_MISC__STOR_CC_LEGACY_MODE_MASK 0x00080000L 235095c1f7aaSFeifei Xu #define DAGB0_WR_CNTL_MISC__EA_CC_LEGACY_MODE_MASK 0x00100000L 235195c1f7aaSFeifei Xu #define DAGB0_WR_CNTL_MISC__UTCL2_CID_MASK 0x03E00000L 235295c1f7aaSFeifei Xu //DAGB0_WR_TLB_CREDIT 235395c1f7aaSFeifei Xu #define DAGB0_WR_TLB_CREDIT__TLB0__SHIFT 0x0 235495c1f7aaSFeifei Xu #define DAGB0_WR_TLB_CREDIT__TLB1__SHIFT 0x5 235595c1f7aaSFeifei Xu #define DAGB0_WR_TLB_CREDIT__TLB2__SHIFT 0xa 235695c1f7aaSFeifei Xu #define DAGB0_WR_TLB_CREDIT__TLB3__SHIFT 0xf 235795c1f7aaSFeifei Xu #define DAGB0_WR_TLB_CREDIT__TLB4__SHIFT 0x14 235895c1f7aaSFeifei Xu #define DAGB0_WR_TLB_CREDIT__TLB5__SHIFT 0x19 235995c1f7aaSFeifei Xu #define DAGB0_WR_TLB_CREDIT__TLB0_MASK 0x0000001FL 236095c1f7aaSFeifei Xu #define DAGB0_WR_TLB_CREDIT__TLB1_MASK 0x000003E0L 236195c1f7aaSFeifei Xu #define DAGB0_WR_TLB_CREDIT__TLB2_MASK 0x00007C00L 236295c1f7aaSFeifei Xu #define DAGB0_WR_TLB_CREDIT__TLB3_MASK 0x000F8000L 236395c1f7aaSFeifei Xu #define DAGB0_WR_TLB_CREDIT__TLB4_MASK 0x01F00000L 236495c1f7aaSFeifei Xu #define DAGB0_WR_TLB_CREDIT__TLB5_MASK 0x3E000000L 236595c1f7aaSFeifei Xu //DAGB0_WR_DATA_CREDIT 236695c1f7aaSFeifei Xu #define DAGB0_WR_DATA_CREDIT__DLOCK_VC_CREDITS__SHIFT 0x0 236795c1f7aaSFeifei Xu #define DAGB0_WR_DATA_CREDIT__LARGE_BURST_CREDITS__SHIFT 0x8 236895c1f7aaSFeifei Xu #define DAGB0_WR_DATA_CREDIT__MIDDLE_BURST_CREDITS__SHIFT 0x10 236995c1f7aaSFeifei Xu #define DAGB0_WR_DATA_CREDIT__SMALL_BURST_CREDITS__SHIFT 0x18 237095c1f7aaSFeifei Xu #define DAGB0_WR_DATA_CREDIT__DLOCK_VC_CREDITS_MASK 0x000000FFL 237195c1f7aaSFeifei Xu #define DAGB0_WR_DATA_CREDIT__LARGE_BURST_CREDITS_MASK 0x0000FF00L 237295c1f7aaSFeifei Xu #define DAGB0_WR_DATA_CREDIT__MIDDLE_BURST_CREDITS_MASK 0x00FF0000L 237395c1f7aaSFeifei Xu #define DAGB0_WR_DATA_CREDIT__SMALL_BURST_CREDITS_MASK 0xFF000000L 237495c1f7aaSFeifei Xu //DAGB0_WR_MISC_CREDIT 237595c1f7aaSFeifei Xu #define DAGB0_WR_MISC_CREDIT__ATOMIC_CREDIT__SHIFT 0x0 237695c1f7aaSFeifei Xu #define DAGB0_WR_MISC_CREDIT__DLOCK_VC_NUM__SHIFT 0x6 237795c1f7aaSFeifei Xu #define DAGB0_WR_MISC_CREDIT__OSD_CREDIT__SHIFT 0x9 237895c1f7aaSFeifei Xu #define DAGB0_WR_MISC_CREDIT__OSD_DLOCK_CREDIT__SHIFT 0x10 237995c1f7aaSFeifei Xu #define DAGB0_WR_MISC_CREDIT__ATOMIC_CREDIT_MASK 0x0000003FL 238095c1f7aaSFeifei Xu #define DAGB0_WR_MISC_CREDIT__DLOCK_VC_NUM_MASK 0x000001C0L 238195c1f7aaSFeifei Xu #define DAGB0_WR_MISC_CREDIT__OSD_CREDIT_MASK 0x0000FE00L 238295c1f7aaSFeifei Xu #define DAGB0_WR_MISC_CREDIT__OSD_DLOCK_CREDIT_MASK 0x007F0000L 238395c1f7aaSFeifei Xu //DAGB0_WRCLI_ASK_PENDING 238495c1f7aaSFeifei Xu #define DAGB0_WRCLI_ASK_PENDING__BUSY__SHIFT 0x0 238595c1f7aaSFeifei Xu #define DAGB0_WRCLI_ASK_PENDING__BUSY_MASK 0xFFFFFFFFL 238695c1f7aaSFeifei Xu //DAGB0_WRCLI_GO_PENDING 238795c1f7aaSFeifei Xu #define DAGB0_WRCLI_GO_PENDING__BUSY__SHIFT 0x0 238895c1f7aaSFeifei Xu #define DAGB0_WRCLI_GO_PENDING__BUSY_MASK 0xFFFFFFFFL 238995c1f7aaSFeifei Xu //DAGB0_WRCLI_GBLSEND_PENDING 239095c1f7aaSFeifei Xu #define DAGB0_WRCLI_GBLSEND_PENDING__BUSY__SHIFT 0x0 239195c1f7aaSFeifei Xu #define DAGB0_WRCLI_GBLSEND_PENDING__BUSY_MASK 0xFFFFFFFFL 239295c1f7aaSFeifei Xu //DAGB0_WRCLI_TLB_PENDING 239395c1f7aaSFeifei Xu #define DAGB0_WRCLI_TLB_PENDING__BUSY__SHIFT 0x0 239495c1f7aaSFeifei Xu #define DAGB0_WRCLI_TLB_PENDING__BUSY_MASK 0xFFFFFFFFL 239595c1f7aaSFeifei Xu //DAGB0_WRCLI_OARB_PENDING 239695c1f7aaSFeifei Xu #define DAGB0_WRCLI_OARB_PENDING__BUSY__SHIFT 0x0 239795c1f7aaSFeifei Xu #define DAGB0_WRCLI_OARB_PENDING__BUSY_MASK 0xFFFFFFFFL 239895c1f7aaSFeifei Xu //DAGB0_WRCLI_OSD_PENDING 239995c1f7aaSFeifei Xu #define DAGB0_WRCLI_OSD_PENDING__BUSY__SHIFT 0x0 240095c1f7aaSFeifei Xu #define DAGB0_WRCLI_OSD_PENDING__BUSY_MASK 0xFFFFFFFFL 240195c1f7aaSFeifei Xu //DAGB0_WRCLI_DBUS_ASK_PENDING 240295c1f7aaSFeifei Xu #define DAGB0_WRCLI_DBUS_ASK_PENDING__BUSY__SHIFT 0x0 240395c1f7aaSFeifei Xu #define DAGB0_WRCLI_DBUS_ASK_PENDING__BUSY_MASK 0xFFFFFFFFL 240495c1f7aaSFeifei Xu //DAGB0_WRCLI_DBUS_GO_PENDING 240595c1f7aaSFeifei Xu #define DAGB0_WRCLI_DBUS_GO_PENDING__BUSY__SHIFT 0x0 240695c1f7aaSFeifei Xu #define DAGB0_WRCLI_DBUS_GO_PENDING__BUSY_MASK 0xFFFFFFFFL 240795c1f7aaSFeifei Xu //DAGB0_DAGB_DLY 240895c1f7aaSFeifei Xu #define DAGB0_DAGB_DLY__DLY__SHIFT 0x0 240995c1f7aaSFeifei Xu #define DAGB0_DAGB_DLY__CLI__SHIFT 0x8 241095c1f7aaSFeifei Xu #define DAGB0_DAGB_DLY__POS__SHIFT 0x10 241195c1f7aaSFeifei Xu #define DAGB0_DAGB_DLY__DLY_MASK 0x000000FFL 241295c1f7aaSFeifei Xu #define DAGB0_DAGB_DLY__CLI_MASK 0x0000FF00L 241395c1f7aaSFeifei Xu #define DAGB0_DAGB_DLY__POS_MASK 0x000F0000L 241495c1f7aaSFeifei Xu //DAGB0_CNTL_MISC 241595c1f7aaSFeifei Xu #define DAGB0_CNTL_MISC__EA_VC0_REMAP__SHIFT 0x0 241695c1f7aaSFeifei Xu #define DAGB0_CNTL_MISC__EA_VC1_REMAP__SHIFT 0x3 241795c1f7aaSFeifei Xu #define DAGB0_CNTL_MISC__EA_VC2_REMAP__SHIFT 0x6 241895c1f7aaSFeifei Xu #define DAGB0_CNTL_MISC__EA_VC3_REMAP__SHIFT 0x9 241995c1f7aaSFeifei Xu #define DAGB0_CNTL_MISC__EA_VC4_REMAP__SHIFT 0xc 242095c1f7aaSFeifei Xu #define DAGB0_CNTL_MISC__EA_VC5_REMAP__SHIFT 0xf 242195c1f7aaSFeifei Xu #define DAGB0_CNTL_MISC__EA_VC6_REMAP__SHIFT 0x12 242295c1f7aaSFeifei Xu #define DAGB0_CNTL_MISC__EA_VC7_REMAP__SHIFT 0x15 242395c1f7aaSFeifei Xu #define DAGB0_CNTL_MISC__BW_INIT_CYCLE__SHIFT 0x18 242495c1f7aaSFeifei Xu #define DAGB0_CNTL_MISC__BW_RW_GAP_CYCLE__SHIFT 0x1e 242595c1f7aaSFeifei Xu #define DAGB0_CNTL_MISC__EA_VC0_REMAP_MASK 0x00000007L 242695c1f7aaSFeifei Xu #define DAGB0_CNTL_MISC__EA_VC1_REMAP_MASK 0x00000038L 242795c1f7aaSFeifei Xu #define DAGB0_CNTL_MISC__EA_VC2_REMAP_MASK 0x000001C0L 242895c1f7aaSFeifei Xu #define DAGB0_CNTL_MISC__EA_VC3_REMAP_MASK 0x00000E00L 242995c1f7aaSFeifei Xu #define DAGB0_CNTL_MISC__EA_VC4_REMAP_MASK 0x00007000L 243095c1f7aaSFeifei Xu #define DAGB0_CNTL_MISC__EA_VC5_REMAP_MASK 0x00038000L 243195c1f7aaSFeifei Xu #define DAGB0_CNTL_MISC__EA_VC6_REMAP_MASK 0x001C0000L 243295c1f7aaSFeifei Xu #define DAGB0_CNTL_MISC__EA_VC7_REMAP_MASK 0x00E00000L 243395c1f7aaSFeifei Xu #define DAGB0_CNTL_MISC__BW_INIT_CYCLE_MASK 0x3F000000L 243495c1f7aaSFeifei Xu #define DAGB0_CNTL_MISC__BW_RW_GAP_CYCLE_MASK 0xC0000000L 243595c1f7aaSFeifei Xu //DAGB0_CNTL_MISC2 243695c1f7aaSFeifei Xu #define DAGB0_CNTL_MISC2__URG_BOOST_ENABLE__SHIFT 0x0 243795c1f7aaSFeifei Xu #define DAGB0_CNTL_MISC2__URG_HALT_ENABLE__SHIFT 0x1 243895c1f7aaSFeifei Xu #define DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG__SHIFT 0x2 243995c1f7aaSFeifei Xu #define DAGB0_CNTL_MISC2__DISABLE_WRRET_CG__SHIFT 0x3 244095c1f7aaSFeifei Xu #define DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG__SHIFT 0x4 244195c1f7aaSFeifei Xu #define DAGB0_CNTL_MISC2__DISABLE_RDRET_CG__SHIFT 0x5 244295c1f7aaSFeifei Xu #define DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG__SHIFT 0x6 244395c1f7aaSFeifei Xu #define DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG__SHIFT 0x7 244495c1f7aaSFeifei Xu #define DAGB0_CNTL_MISC2__DISABLE_EAWRREQ_BUSY__SHIFT 0x8 244595c1f7aaSFeifei Xu #define DAGB0_CNTL_MISC2__DISABLE_EARDREQ_BUSY__SHIFT 0x9 244695c1f7aaSFeifei Xu #define DAGB0_CNTL_MISC2__SWAP_CTL__SHIFT 0xa 244795c1f7aaSFeifei Xu #define DAGB0_CNTL_MISC2__URG_BOOST_ENABLE_MASK 0x00000001L 244895c1f7aaSFeifei Xu #define DAGB0_CNTL_MISC2__URG_HALT_ENABLE_MASK 0x00000002L 244995c1f7aaSFeifei Xu #define DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG_MASK 0x00000004L 245095c1f7aaSFeifei Xu #define DAGB0_CNTL_MISC2__DISABLE_WRRET_CG_MASK 0x00000008L 245195c1f7aaSFeifei Xu #define DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG_MASK 0x00000010L 245295c1f7aaSFeifei Xu #define DAGB0_CNTL_MISC2__DISABLE_RDRET_CG_MASK 0x00000020L 245395c1f7aaSFeifei Xu #define DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG_MASK 0x00000040L 245495c1f7aaSFeifei Xu #define DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK 0x00000080L 245595c1f7aaSFeifei Xu #define DAGB0_CNTL_MISC2__DISABLE_EAWRREQ_BUSY_MASK 0x00000100L 245695c1f7aaSFeifei Xu #define DAGB0_CNTL_MISC2__DISABLE_EARDREQ_BUSY_MASK 0x00000200L 245795c1f7aaSFeifei Xu #define DAGB0_CNTL_MISC2__SWAP_CTL_MASK 0x00000400L 245895c1f7aaSFeifei Xu //DAGB0_FIFO_EMPTY 245995c1f7aaSFeifei Xu #define DAGB0_FIFO_EMPTY__EMPTY__SHIFT 0x0 246095c1f7aaSFeifei Xu #define DAGB0_FIFO_EMPTY__EMPTY_MASK 0x00FFFFFFL 246195c1f7aaSFeifei Xu //DAGB0_FIFO_FULL 246295c1f7aaSFeifei Xu #define DAGB0_FIFO_FULL__FULL__SHIFT 0x0 246395c1f7aaSFeifei Xu #define DAGB0_FIFO_FULL__FULL_MASK 0x007FFFFFL 246495c1f7aaSFeifei Xu //DAGB0_WR_CREDITS_FULL 246595c1f7aaSFeifei Xu #define DAGB0_WR_CREDITS_FULL__FULL__SHIFT 0x0 246695c1f7aaSFeifei Xu #define DAGB0_WR_CREDITS_FULL__FULL_MASK 0x0007FFFFL 246795c1f7aaSFeifei Xu //DAGB0_RD_CREDITS_FULL 246895c1f7aaSFeifei Xu #define DAGB0_RD_CREDITS_FULL__FULL__SHIFT 0x0 246995c1f7aaSFeifei Xu #define DAGB0_RD_CREDITS_FULL__FULL_MASK 0x0003FFFFL 247095c1f7aaSFeifei Xu //DAGB0_PERFCOUNTER_LO 247195c1f7aaSFeifei Xu #define DAGB0_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 247295c1f7aaSFeifei Xu #define DAGB0_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL 247395c1f7aaSFeifei Xu //DAGB0_PERFCOUNTER_HI 247495c1f7aaSFeifei Xu #define DAGB0_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 247595c1f7aaSFeifei Xu #define DAGB0_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 247695c1f7aaSFeifei Xu #define DAGB0_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL 247795c1f7aaSFeifei Xu #define DAGB0_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L 247895c1f7aaSFeifei Xu //DAGB0_PERFCOUNTER0_CFG 247995c1f7aaSFeifei Xu #define DAGB0_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 248095c1f7aaSFeifei Xu #define DAGB0_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 248195c1f7aaSFeifei Xu #define DAGB0_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 248295c1f7aaSFeifei Xu #define DAGB0_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c 248395c1f7aaSFeifei Xu #define DAGB0_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d 248495c1f7aaSFeifei Xu #define DAGB0_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL 248595c1f7aaSFeifei Xu #define DAGB0_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L 248695c1f7aaSFeifei Xu #define DAGB0_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L 248795c1f7aaSFeifei Xu #define DAGB0_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L 248895c1f7aaSFeifei Xu #define DAGB0_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L 248995c1f7aaSFeifei Xu //DAGB0_PERFCOUNTER1_CFG 249095c1f7aaSFeifei Xu #define DAGB0_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 249195c1f7aaSFeifei Xu #define DAGB0_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 249295c1f7aaSFeifei Xu #define DAGB0_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 249395c1f7aaSFeifei Xu #define DAGB0_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c 249495c1f7aaSFeifei Xu #define DAGB0_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d 249595c1f7aaSFeifei Xu #define DAGB0_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL 249695c1f7aaSFeifei Xu #define DAGB0_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L 249795c1f7aaSFeifei Xu #define DAGB0_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L 249895c1f7aaSFeifei Xu #define DAGB0_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L 249995c1f7aaSFeifei Xu #define DAGB0_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L 250095c1f7aaSFeifei Xu //DAGB0_PERFCOUNTER2_CFG 250195c1f7aaSFeifei Xu #define DAGB0_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0 250295c1f7aaSFeifei Xu #define DAGB0_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8 250395c1f7aaSFeifei Xu #define DAGB0_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18 250495c1f7aaSFeifei Xu #define DAGB0_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c 250595c1f7aaSFeifei Xu #define DAGB0_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d 250695c1f7aaSFeifei Xu #define DAGB0_PERFCOUNTER2_CFG__PERF_SEL_MASK 0x000000FFL 250795c1f7aaSFeifei Xu #define DAGB0_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0x0000FF00L 250895c1f7aaSFeifei Xu #define DAGB0_PERFCOUNTER2_CFG__PERF_MODE_MASK 0x0F000000L 250995c1f7aaSFeifei Xu #define DAGB0_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000L 251095c1f7aaSFeifei Xu #define DAGB0_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000L 251195c1f7aaSFeifei Xu //DAGB0_PERFCOUNTER_RSLT_CNTL 251295c1f7aaSFeifei Xu #define DAGB0_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 251395c1f7aaSFeifei Xu #define DAGB0_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 251495c1f7aaSFeifei Xu #define DAGB0_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 251595c1f7aaSFeifei Xu #define DAGB0_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 251695c1f7aaSFeifei Xu #define DAGB0_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 251795c1f7aaSFeifei Xu #define DAGB0_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a 251895c1f7aaSFeifei Xu #define DAGB0_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL 251995c1f7aaSFeifei Xu #define DAGB0_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L 252095c1f7aaSFeifei Xu #define DAGB0_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L 252195c1f7aaSFeifei Xu #define DAGB0_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L 252295c1f7aaSFeifei Xu #define DAGB0_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L 252395c1f7aaSFeifei Xu #define DAGB0_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L 252495c1f7aaSFeifei Xu //DAGB0_RESERVE0 252595c1f7aaSFeifei Xu #define DAGB0_RESERVE0__RESERVE__SHIFT 0x0 252695c1f7aaSFeifei Xu #define DAGB0_RESERVE0__RESERVE_MASK 0xFFFFFFFFL 252795c1f7aaSFeifei Xu //DAGB0_RESERVE1 252895c1f7aaSFeifei Xu #define DAGB0_RESERVE1__RESERVE__SHIFT 0x0 252995c1f7aaSFeifei Xu #define DAGB0_RESERVE1__RESERVE_MASK 0xFFFFFFFFL 253095c1f7aaSFeifei Xu //DAGB0_RESERVE2 253195c1f7aaSFeifei Xu #define DAGB0_RESERVE2__RESERVE__SHIFT 0x0 253295c1f7aaSFeifei Xu #define DAGB0_RESERVE2__RESERVE_MASK 0xFFFFFFFFL 253395c1f7aaSFeifei Xu //DAGB0_RESERVE3 253495c1f7aaSFeifei Xu #define DAGB0_RESERVE3__RESERVE__SHIFT 0x0 253595c1f7aaSFeifei Xu #define DAGB0_RESERVE3__RESERVE_MASK 0xFFFFFFFFL 253695c1f7aaSFeifei Xu //DAGB0_RESERVE4 253795c1f7aaSFeifei Xu #define DAGB0_RESERVE4__RESERVE__SHIFT 0x0 253895c1f7aaSFeifei Xu #define DAGB0_RESERVE4__RESERVE_MASK 0xFFFFFFFFL 253995c1f7aaSFeifei Xu //DAGB0_RESERVE5 254095c1f7aaSFeifei Xu #define DAGB0_RESERVE5__RESERVE__SHIFT 0x0 254195c1f7aaSFeifei Xu #define DAGB0_RESERVE5__RESERVE_MASK 0xFFFFFFFFL 254295c1f7aaSFeifei Xu //DAGB0_RESERVE6 254395c1f7aaSFeifei Xu #define DAGB0_RESERVE6__RESERVE__SHIFT 0x0 254495c1f7aaSFeifei Xu #define DAGB0_RESERVE6__RESERVE_MASK 0xFFFFFFFFL 254595c1f7aaSFeifei Xu //DAGB0_RESERVE7 254695c1f7aaSFeifei Xu #define DAGB0_RESERVE7__RESERVE__SHIFT 0x0 254795c1f7aaSFeifei Xu #define DAGB0_RESERVE7__RESERVE_MASK 0xFFFFFFFFL 254895c1f7aaSFeifei Xu //DAGB0_RESERVE8 254995c1f7aaSFeifei Xu #define DAGB0_RESERVE8__RESERVE__SHIFT 0x0 255095c1f7aaSFeifei Xu #define DAGB0_RESERVE8__RESERVE_MASK 0xFFFFFFFFL 255195c1f7aaSFeifei Xu //DAGB0_RESERVE9 255295c1f7aaSFeifei Xu #define DAGB0_RESERVE9__RESERVE__SHIFT 0x0 255395c1f7aaSFeifei Xu #define DAGB0_RESERVE9__RESERVE_MASK 0xFFFFFFFFL 255495c1f7aaSFeifei Xu //DAGB0_RESERVE10 255595c1f7aaSFeifei Xu #define DAGB0_RESERVE10__RESERVE__SHIFT 0x0 255695c1f7aaSFeifei Xu #define DAGB0_RESERVE10__RESERVE_MASK 0xFFFFFFFFL 255795c1f7aaSFeifei Xu //DAGB0_RESERVE11 255895c1f7aaSFeifei Xu #define DAGB0_RESERVE11__RESERVE__SHIFT 0x0 255995c1f7aaSFeifei Xu #define DAGB0_RESERVE11__RESERVE_MASK 0xFFFFFFFFL 256095c1f7aaSFeifei Xu //DAGB0_RESERVE12 256195c1f7aaSFeifei Xu #define DAGB0_RESERVE12__RESERVE__SHIFT 0x0 256295c1f7aaSFeifei Xu #define DAGB0_RESERVE12__RESERVE_MASK 0xFFFFFFFFL 256395c1f7aaSFeifei Xu //DAGB0_RESERVE13 256495c1f7aaSFeifei Xu #define DAGB0_RESERVE13__RESERVE__SHIFT 0x0 256595c1f7aaSFeifei Xu #define DAGB0_RESERVE13__RESERVE_MASK 0xFFFFFFFFL 256695c1f7aaSFeifei Xu //DAGB0_RESERVE14 256795c1f7aaSFeifei Xu #define DAGB0_RESERVE14__RESERVE__SHIFT 0x0 256895c1f7aaSFeifei Xu #define DAGB0_RESERVE14__RESERVE_MASK 0xFFFFFFFFL 256995c1f7aaSFeifei Xu //DAGB0_RESERVE15 257095c1f7aaSFeifei Xu #define DAGB0_RESERVE15__RESERVE__SHIFT 0x0 257195c1f7aaSFeifei Xu #define DAGB0_RESERVE15__RESERVE_MASK 0xFFFFFFFFL 257295c1f7aaSFeifei Xu //DAGB0_RESERVE16 257395c1f7aaSFeifei Xu #define DAGB0_RESERVE16__RESERVE__SHIFT 0x0 257495c1f7aaSFeifei Xu #define DAGB0_RESERVE16__RESERVE_MASK 0xFFFFFFFFL 257595c1f7aaSFeifei Xu //DAGB0_RESERVE17 257695c1f7aaSFeifei Xu #define DAGB0_RESERVE17__RESERVE__SHIFT 0x0 257795c1f7aaSFeifei Xu #define DAGB0_RESERVE17__RESERVE_MASK 0xFFFFFFFFL 257895c1f7aaSFeifei Xu //DAGB0_RESERVE18 257995c1f7aaSFeifei Xu #define DAGB0_RESERVE18__RESERVE__SHIFT 0x0 258095c1f7aaSFeifei Xu #define DAGB0_RESERVE18__RESERVE_MASK 0xFFFFFFFFL 258195c1f7aaSFeifei Xu //DAGB0_RESERVE19 258295c1f7aaSFeifei Xu #define DAGB0_RESERVE19__RESERVE__SHIFT 0x0 258395c1f7aaSFeifei Xu #define DAGB0_RESERVE19__RESERVE_MASK 0xFFFFFFFFL 258495c1f7aaSFeifei Xu //DAGB0_RESERVE20 258595c1f7aaSFeifei Xu #define DAGB0_RESERVE20__RESERVE__SHIFT 0x0 258695c1f7aaSFeifei Xu #define DAGB0_RESERVE20__RESERVE_MASK 0xFFFFFFFFL 258795c1f7aaSFeifei Xu //DAGB0_RESERVE21 258895c1f7aaSFeifei Xu #define DAGB0_RESERVE21__RESERVE__SHIFT 0x0 258995c1f7aaSFeifei Xu #define DAGB0_RESERVE21__RESERVE_MASK 0xFFFFFFFFL 259095c1f7aaSFeifei Xu //DAGB0_RESERVE22 259195c1f7aaSFeifei Xu #define DAGB0_RESERVE22__RESERVE__SHIFT 0x0 259295c1f7aaSFeifei Xu #define DAGB0_RESERVE22__RESERVE_MASK 0xFFFFFFFFL 259395c1f7aaSFeifei Xu //DAGB0_RESERVE23 259495c1f7aaSFeifei Xu #define DAGB0_RESERVE23__RESERVE__SHIFT 0x0 259595c1f7aaSFeifei Xu #define DAGB0_RESERVE23__RESERVE_MASK 0xFFFFFFFFL 259695c1f7aaSFeifei Xu //DAGB0_RESERVE24 259795c1f7aaSFeifei Xu #define DAGB0_RESERVE24__RESERVE__SHIFT 0x0 259895c1f7aaSFeifei Xu #define DAGB0_RESERVE24__RESERVE_MASK 0xFFFFFFFFL 259995c1f7aaSFeifei Xu //DAGB0_RESERVE25 260095c1f7aaSFeifei Xu #define DAGB0_RESERVE25__RESERVE__SHIFT 0x0 260195c1f7aaSFeifei Xu #define DAGB0_RESERVE25__RESERVE_MASK 0xFFFFFFFFL 260295c1f7aaSFeifei Xu //DAGB0_RESERVE26 260395c1f7aaSFeifei Xu #define DAGB0_RESERVE26__RESERVE__SHIFT 0x0 260495c1f7aaSFeifei Xu #define DAGB0_RESERVE26__RESERVE_MASK 0xFFFFFFFFL 260595c1f7aaSFeifei Xu //DAGB0_RESERVE27 260695c1f7aaSFeifei Xu #define DAGB0_RESERVE27__RESERVE__SHIFT 0x0 260795c1f7aaSFeifei Xu #define DAGB0_RESERVE27__RESERVE_MASK 0xFFFFFFFFL 260895c1f7aaSFeifei Xu //DAGB0_RESERVE28 260995c1f7aaSFeifei Xu #define DAGB0_RESERVE28__RESERVE__SHIFT 0x0 261095c1f7aaSFeifei Xu #define DAGB0_RESERVE28__RESERVE_MASK 0xFFFFFFFFL 261195c1f7aaSFeifei Xu //DAGB0_RESERVE29 261295c1f7aaSFeifei Xu #define DAGB0_RESERVE29__RESERVE__SHIFT 0x0 261395c1f7aaSFeifei Xu #define DAGB0_RESERVE29__RESERVE_MASK 0xFFFFFFFFL 261495c1f7aaSFeifei Xu //DAGB0_RESERVE30 261595c1f7aaSFeifei Xu #define DAGB0_RESERVE30__RESERVE__SHIFT 0x0 261695c1f7aaSFeifei Xu #define DAGB0_RESERVE30__RESERVE_MASK 0xFFFFFFFFL 261795c1f7aaSFeifei Xu //DAGB0_RESERVE31 261895c1f7aaSFeifei Xu #define DAGB0_RESERVE31__RESERVE__SHIFT 0x0 261995c1f7aaSFeifei Xu #define DAGB0_RESERVE31__RESERVE_MASK 0xFFFFFFFFL 262095c1f7aaSFeifei Xu //DAGB0_RESERVE32 262195c1f7aaSFeifei Xu #define DAGB0_RESERVE32__RESERVE__SHIFT 0x0 262295c1f7aaSFeifei Xu #define DAGB0_RESERVE32__RESERVE_MASK 0xFFFFFFFFL 262395c1f7aaSFeifei Xu //DAGB0_RESERVE33 262495c1f7aaSFeifei Xu #define DAGB0_RESERVE33__RESERVE__SHIFT 0x0 262595c1f7aaSFeifei Xu #define DAGB0_RESERVE33__RESERVE_MASK 0xFFFFFFFFL 262695c1f7aaSFeifei Xu //DAGB0_RESERVE34 262795c1f7aaSFeifei Xu #define DAGB0_RESERVE34__RESERVE__SHIFT 0x0 262895c1f7aaSFeifei Xu #define DAGB0_RESERVE34__RESERVE_MASK 0xFFFFFFFFL 262995c1f7aaSFeifei Xu //DAGB0_RESERVE35 263095c1f7aaSFeifei Xu #define DAGB0_RESERVE35__RESERVE__SHIFT 0x0 263195c1f7aaSFeifei Xu #define DAGB0_RESERVE35__RESERVE_MASK 0xFFFFFFFFL 263295c1f7aaSFeifei Xu //DAGB0_RESERVE36 263395c1f7aaSFeifei Xu #define DAGB0_RESERVE36__RESERVE__SHIFT 0x0 263495c1f7aaSFeifei Xu #define DAGB0_RESERVE36__RESERVE_MASK 0xFFFFFFFFL 263595c1f7aaSFeifei Xu //DAGB0_RESERVE37 263695c1f7aaSFeifei Xu #define DAGB0_RESERVE37__RESERVE__SHIFT 0x0 263795c1f7aaSFeifei Xu #define DAGB0_RESERVE37__RESERVE_MASK 0xFFFFFFFFL 263895c1f7aaSFeifei Xu //DAGB0_RESERVE38 263995c1f7aaSFeifei Xu #define DAGB0_RESERVE38__RESERVE__SHIFT 0x0 264095c1f7aaSFeifei Xu #define DAGB0_RESERVE38__RESERVE_MASK 0xFFFFFFFFL 264195c1f7aaSFeifei Xu //DAGB0_RESERVE39 264295c1f7aaSFeifei Xu #define DAGB0_RESERVE39__RESERVE__SHIFT 0x0 264395c1f7aaSFeifei Xu #define DAGB0_RESERVE39__RESERVE_MASK 0xFFFFFFFFL 264495c1f7aaSFeifei Xu //DAGB0_RESERVE40 264595c1f7aaSFeifei Xu #define DAGB0_RESERVE40__RESERVE__SHIFT 0x0 264695c1f7aaSFeifei Xu #define DAGB0_RESERVE40__RESERVE_MASK 0xFFFFFFFFL 264795c1f7aaSFeifei Xu //DAGB0_RESERVE41 264895c1f7aaSFeifei Xu #define DAGB0_RESERVE41__RESERVE__SHIFT 0x0 264995c1f7aaSFeifei Xu #define DAGB0_RESERVE41__RESERVE_MASK 0xFFFFFFFFL 265095c1f7aaSFeifei Xu //DAGB0_RESERVE42 265195c1f7aaSFeifei Xu #define DAGB0_RESERVE42__RESERVE__SHIFT 0x0 265295c1f7aaSFeifei Xu #define DAGB0_RESERVE42__RESERVE_MASK 0xFFFFFFFFL 265395c1f7aaSFeifei Xu //DAGB0_RESERVE43 265495c1f7aaSFeifei Xu #define DAGB0_RESERVE43__RESERVE__SHIFT 0x0 265595c1f7aaSFeifei Xu #define DAGB0_RESERVE43__RESERVE_MASK 0xFFFFFFFFL 265695c1f7aaSFeifei Xu //DAGB0_RESERVE44 265795c1f7aaSFeifei Xu #define DAGB0_RESERVE44__RESERVE__SHIFT 0x0 265895c1f7aaSFeifei Xu #define DAGB0_RESERVE44__RESERVE_MASK 0xFFFFFFFFL 265995c1f7aaSFeifei Xu //DAGB0_RESERVE45 266095c1f7aaSFeifei Xu #define DAGB0_RESERVE45__RESERVE__SHIFT 0x0 266195c1f7aaSFeifei Xu #define DAGB0_RESERVE45__RESERVE_MASK 0xFFFFFFFFL 266295c1f7aaSFeifei Xu //DAGB0_RESERVE46 266395c1f7aaSFeifei Xu #define DAGB0_RESERVE46__RESERVE__SHIFT 0x0 266495c1f7aaSFeifei Xu #define DAGB0_RESERVE46__RESERVE_MASK 0xFFFFFFFFL 266595c1f7aaSFeifei Xu //DAGB0_RESERVE47 266695c1f7aaSFeifei Xu #define DAGB0_RESERVE47__RESERVE__SHIFT 0x0 266795c1f7aaSFeifei Xu #define DAGB0_RESERVE47__RESERVE_MASK 0xFFFFFFFFL 266895c1f7aaSFeifei Xu //DAGB0_RESERVE48 266995c1f7aaSFeifei Xu #define DAGB0_RESERVE48__RESERVE__SHIFT 0x0 267095c1f7aaSFeifei Xu #define DAGB0_RESERVE48__RESERVE_MASK 0xFFFFFFFFL 267195c1f7aaSFeifei Xu //DAGB0_RESERVE49 267295c1f7aaSFeifei Xu #define DAGB0_RESERVE49__RESERVE__SHIFT 0x0 267395c1f7aaSFeifei Xu #define DAGB0_RESERVE49__RESERVE_MASK 0xFFFFFFFFL 267495c1f7aaSFeifei Xu //DAGB0_RESERVE50 267595c1f7aaSFeifei Xu #define DAGB0_RESERVE50__RESERVE__SHIFT 0x0 267695c1f7aaSFeifei Xu #define DAGB0_RESERVE50__RESERVE_MASK 0xFFFFFFFFL 267795c1f7aaSFeifei Xu //DAGB0_RESERVE51 267895c1f7aaSFeifei Xu #define DAGB0_RESERVE51__RESERVE__SHIFT 0x0 267995c1f7aaSFeifei Xu #define DAGB0_RESERVE51__RESERVE_MASK 0xFFFFFFFFL 268095c1f7aaSFeifei Xu //DAGB0_RESERVE52 268195c1f7aaSFeifei Xu #define DAGB0_RESERVE52__RESERVE__SHIFT 0x0 268295c1f7aaSFeifei Xu #define DAGB0_RESERVE52__RESERVE_MASK 0xFFFFFFFFL 268395c1f7aaSFeifei Xu //DAGB0_RESERVE53 268495c1f7aaSFeifei Xu #define DAGB0_RESERVE53__RESERVE__SHIFT 0x0 268595c1f7aaSFeifei Xu #define DAGB0_RESERVE53__RESERVE_MASK 0xFFFFFFFFL 268695c1f7aaSFeifei Xu //DAGB0_RESERVE54 268795c1f7aaSFeifei Xu #define DAGB0_RESERVE54__RESERVE__SHIFT 0x0 268895c1f7aaSFeifei Xu #define DAGB0_RESERVE54__RESERVE_MASK 0xFFFFFFFFL 268995c1f7aaSFeifei Xu //DAGB0_RESERVE55 269095c1f7aaSFeifei Xu #define DAGB0_RESERVE55__RESERVE__SHIFT 0x0 269195c1f7aaSFeifei Xu #define DAGB0_RESERVE55__RESERVE_MASK 0xFFFFFFFFL 269295c1f7aaSFeifei Xu //DAGB0_RESERVE56 269395c1f7aaSFeifei Xu #define DAGB0_RESERVE56__RESERVE__SHIFT 0x0 269495c1f7aaSFeifei Xu #define DAGB0_RESERVE56__RESERVE_MASK 0xFFFFFFFFL 269595c1f7aaSFeifei Xu //DAGB0_RESERVE57 269695c1f7aaSFeifei Xu #define DAGB0_RESERVE57__RESERVE__SHIFT 0x0 269795c1f7aaSFeifei Xu #define DAGB0_RESERVE57__RESERVE_MASK 0xFFFFFFFFL 269895c1f7aaSFeifei Xu //DAGB0_RESERVE58 269995c1f7aaSFeifei Xu #define DAGB0_RESERVE58__RESERVE__SHIFT 0x0 270095c1f7aaSFeifei Xu #define DAGB0_RESERVE58__RESERVE_MASK 0xFFFFFFFFL 270195c1f7aaSFeifei Xu //DAGB0_RESERVE59 270295c1f7aaSFeifei Xu #define DAGB0_RESERVE59__RESERVE__SHIFT 0x0 270395c1f7aaSFeifei Xu #define DAGB0_RESERVE59__RESERVE_MASK 0xFFFFFFFFL 270495c1f7aaSFeifei Xu //DAGB0_RESERVE60 270595c1f7aaSFeifei Xu #define DAGB0_RESERVE60__RESERVE__SHIFT 0x0 270695c1f7aaSFeifei Xu #define DAGB0_RESERVE60__RESERVE_MASK 0xFFFFFFFFL 270795c1f7aaSFeifei Xu //DAGB0_RESERVE61 270895c1f7aaSFeifei Xu #define DAGB0_RESERVE61__RESERVE__SHIFT 0x0 270995c1f7aaSFeifei Xu #define DAGB0_RESERVE61__RESERVE_MASK 0xFFFFFFFFL 271095c1f7aaSFeifei Xu //DAGB0_RESERVE62 271195c1f7aaSFeifei Xu #define DAGB0_RESERVE62__RESERVE__SHIFT 0x0 271295c1f7aaSFeifei Xu #define DAGB0_RESERVE62__RESERVE_MASK 0xFFFFFFFFL 271395c1f7aaSFeifei Xu //DAGB0_RESERVE63 271495c1f7aaSFeifei Xu #define DAGB0_RESERVE63__RESERVE__SHIFT 0x0 271595c1f7aaSFeifei Xu #define DAGB0_RESERVE63__RESERVE_MASK 0xFFFFFFFFL 271695c1f7aaSFeifei Xu //DAGB0_RESERVE64 271795c1f7aaSFeifei Xu #define DAGB0_RESERVE64__RESERVE__SHIFT 0x0 271895c1f7aaSFeifei Xu #define DAGB0_RESERVE64__RESERVE_MASK 0xFFFFFFFFL 271995c1f7aaSFeifei Xu //DAGB0_RESERVE65 272095c1f7aaSFeifei Xu #define DAGB0_RESERVE65__RESERVE__SHIFT 0x0 272195c1f7aaSFeifei Xu #define DAGB0_RESERVE65__RESERVE_MASK 0xFFFFFFFFL 272295c1f7aaSFeifei Xu //DAGB0_RESERVE66 272395c1f7aaSFeifei Xu #define DAGB0_RESERVE66__RESERVE__SHIFT 0x0 272495c1f7aaSFeifei Xu #define DAGB0_RESERVE66__RESERVE_MASK 0xFFFFFFFFL 272595c1f7aaSFeifei Xu //DAGB0_RESERVE67 272695c1f7aaSFeifei Xu #define DAGB0_RESERVE67__RESERVE__SHIFT 0x0 272795c1f7aaSFeifei Xu #define DAGB0_RESERVE67__RESERVE_MASK 0xFFFFFFFFL 272895c1f7aaSFeifei Xu //DAGB0_RESERVE68 272995c1f7aaSFeifei Xu #define DAGB0_RESERVE68__RESERVE__SHIFT 0x0 273095c1f7aaSFeifei Xu #define DAGB0_RESERVE68__RESERVE_MASK 0xFFFFFFFFL 273195c1f7aaSFeifei Xu //DAGB0_RESERVE69 273295c1f7aaSFeifei Xu #define DAGB0_RESERVE69__RESERVE__SHIFT 0x0 273395c1f7aaSFeifei Xu #define DAGB0_RESERVE69__RESERVE_MASK 0xFFFFFFFFL 273495c1f7aaSFeifei Xu //DAGB0_RESERVE70 273595c1f7aaSFeifei Xu #define DAGB0_RESERVE70__RESERVE__SHIFT 0x0 273695c1f7aaSFeifei Xu #define DAGB0_RESERVE70__RESERVE_MASK 0xFFFFFFFFL 273795c1f7aaSFeifei Xu //DAGB0_RESERVE71 273895c1f7aaSFeifei Xu #define DAGB0_RESERVE71__RESERVE__SHIFT 0x0 273995c1f7aaSFeifei Xu #define DAGB0_RESERVE71__RESERVE_MASK 0xFFFFFFFFL 274095c1f7aaSFeifei Xu //DAGB0_RESERVE72 274195c1f7aaSFeifei Xu #define DAGB0_RESERVE72__RESERVE__SHIFT 0x0 274295c1f7aaSFeifei Xu #define DAGB0_RESERVE72__RESERVE_MASK 0xFFFFFFFFL 274395c1f7aaSFeifei Xu //DAGB0_RESERVE73 274495c1f7aaSFeifei Xu #define DAGB0_RESERVE73__RESERVE__SHIFT 0x0 274595c1f7aaSFeifei Xu #define DAGB0_RESERVE73__RESERVE_MASK 0xFFFFFFFFL 274695c1f7aaSFeifei Xu //DAGB0_RESERVE74 274795c1f7aaSFeifei Xu #define DAGB0_RESERVE74__RESERVE__SHIFT 0x0 274895c1f7aaSFeifei Xu #define DAGB0_RESERVE74__RESERVE_MASK 0xFFFFFFFFL 274995c1f7aaSFeifei Xu //DAGB0_RESERVE75 275095c1f7aaSFeifei Xu #define DAGB0_RESERVE75__RESERVE__SHIFT 0x0 275195c1f7aaSFeifei Xu #define DAGB0_RESERVE75__RESERVE_MASK 0xFFFFFFFFL 275295c1f7aaSFeifei Xu //DAGB0_RESERVE76 275395c1f7aaSFeifei Xu #define DAGB0_RESERVE76__RESERVE__SHIFT 0x0 275495c1f7aaSFeifei Xu #define DAGB0_RESERVE76__RESERVE_MASK 0xFFFFFFFFL 275595c1f7aaSFeifei Xu //DAGB0_RESERVE77 275695c1f7aaSFeifei Xu #define DAGB0_RESERVE77__RESERVE__SHIFT 0x0 275795c1f7aaSFeifei Xu #define DAGB0_RESERVE77__RESERVE_MASK 0xFFFFFFFFL 275895c1f7aaSFeifei Xu //DAGB0_RESERVE78 275995c1f7aaSFeifei Xu #define DAGB0_RESERVE78__RESERVE__SHIFT 0x0 276095c1f7aaSFeifei Xu #define DAGB0_RESERVE78__RESERVE_MASK 0xFFFFFFFFL 276195c1f7aaSFeifei Xu //DAGB0_RESERVE79 276295c1f7aaSFeifei Xu #define DAGB0_RESERVE79__RESERVE__SHIFT 0x0 276395c1f7aaSFeifei Xu #define DAGB0_RESERVE79__RESERVE_MASK 0xFFFFFFFFL 276495c1f7aaSFeifei Xu //DAGB0_RESERVE80 276595c1f7aaSFeifei Xu #define DAGB0_RESERVE80__RESERVE__SHIFT 0x0 276695c1f7aaSFeifei Xu #define DAGB0_RESERVE80__RESERVE_MASK 0xFFFFFFFFL 276795c1f7aaSFeifei Xu //DAGB0_RESERVE81 276895c1f7aaSFeifei Xu #define DAGB0_RESERVE81__RESERVE__SHIFT 0x0 276995c1f7aaSFeifei Xu #define DAGB0_RESERVE81__RESERVE_MASK 0xFFFFFFFFL 277095c1f7aaSFeifei Xu //DAGB0_RESERVE82 277195c1f7aaSFeifei Xu #define DAGB0_RESERVE82__RESERVE__SHIFT 0x0 277295c1f7aaSFeifei Xu #define DAGB0_RESERVE82__RESERVE_MASK 0xFFFFFFFFL 277395c1f7aaSFeifei Xu //DAGB0_RESERVE83 277495c1f7aaSFeifei Xu #define DAGB0_RESERVE83__RESERVE__SHIFT 0x0 277595c1f7aaSFeifei Xu #define DAGB0_RESERVE83__RESERVE_MASK 0xFFFFFFFFL 277695c1f7aaSFeifei Xu //DAGB0_RESERVE84 277795c1f7aaSFeifei Xu #define DAGB0_RESERVE84__RESERVE__SHIFT 0x0 277895c1f7aaSFeifei Xu #define DAGB0_RESERVE84__RESERVE_MASK 0xFFFFFFFFL 277995c1f7aaSFeifei Xu //DAGB0_RESERVE85 278095c1f7aaSFeifei Xu #define DAGB0_RESERVE85__RESERVE__SHIFT 0x0 278195c1f7aaSFeifei Xu #define DAGB0_RESERVE85__RESERVE_MASK 0xFFFFFFFFL 278295c1f7aaSFeifei Xu //DAGB0_RESERVE86 278395c1f7aaSFeifei Xu #define DAGB0_RESERVE86__RESERVE__SHIFT 0x0 278495c1f7aaSFeifei Xu #define DAGB0_RESERVE86__RESERVE_MASK 0xFFFFFFFFL 278595c1f7aaSFeifei Xu //DAGB0_RESERVE87 278695c1f7aaSFeifei Xu #define DAGB0_RESERVE87__RESERVE__SHIFT 0x0 278795c1f7aaSFeifei Xu #define DAGB0_RESERVE87__RESERVE_MASK 0xFFFFFFFFL 278895c1f7aaSFeifei Xu //DAGB0_RESERVE88 278995c1f7aaSFeifei Xu #define DAGB0_RESERVE88__RESERVE__SHIFT 0x0 279095c1f7aaSFeifei Xu #define DAGB0_RESERVE88__RESERVE_MASK 0xFFFFFFFFL 279195c1f7aaSFeifei Xu //DAGB0_RESERVE89 279295c1f7aaSFeifei Xu #define DAGB0_RESERVE89__RESERVE__SHIFT 0x0 279395c1f7aaSFeifei Xu #define DAGB0_RESERVE89__RESERVE_MASK 0xFFFFFFFFL 279495c1f7aaSFeifei Xu //DAGB0_RESERVE90 279595c1f7aaSFeifei Xu #define DAGB0_RESERVE90__RESERVE__SHIFT 0x0 279695c1f7aaSFeifei Xu #define DAGB0_RESERVE90__RESERVE_MASK 0xFFFFFFFFL 279795c1f7aaSFeifei Xu //DAGB0_RESERVE91 279895c1f7aaSFeifei Xu #define DAGB0_RESERVE91__RESERVE__SHIFT 0x0 279995c1f7aaSFeifei Xu #define DAGB0_RESERVE91__RESERVE_MASK 0xFFFFFFFFL 280095c1f7aaSFeifei Xu //DAGB0_RESERVE92 280195c1f7aaSFeifei Xu #define DAGB0_RESERVE92__RESERVE__SHIFT 0x0 280295c1f7aaSFeifei Xu #define DAGB0_RESERVE92__RESERVE_MASK 0xFFFFFFFFL 280395c1f7aaSFeifei Xu //DAGB0_RESERVE93 280495c1f7aaSFeifei Xu #define DAGB0_RESERVE93__RESERVE__SHIFT 0x0 280595c1f7aaSFeifei Xu #define DAGB0_RESERVE93__RESERVE_MASK 0xFFFFFFFFL 280695c1f7aaSFeifei Xu //DAGB0_RESERVE94 280795c1f7aaSFeifei Xu #define DAGB0_RESERVE94__RESERVE__SHIFT 0x0 280895c1f7aaSFeifei Xu #define DAGB0_RESERVE94__RESERVE_MASK 0xFFFFFFFFL 280995c1f7aaSFeifei Xu //DAGB0_RESERVE95 281095c1f7aaSFeifei Xu #define DAGB0_RESERVE95__RESERVE__SHIFT 0x0 281195c1f7aaSFeifei Xu #define DAGB0_RESERVE95__RESERVE_MASK 0xFFFFFFFFL 281295c1f7aaSFeifei Xu //DAGB0_RESERVE96 281395c1f7aaSFeifei Xu #define DAGB0_RESERVE96__RESERVE__SHIFT 0x0 281495c1f7aaSFeifei Xu #define DAGB0_RESERVE96__RESERVE_MASK 0xFFFFFFFFL 281595c1f7aaSFeifei Xu //DAGB0_RESERVE97 281695c1f7aaSFeifei Xu #define DAGB0_RESERVE97__RESERVE__SHIFT 0x0 281795c1f7aaSFeifei Xu #define DAGB0_RESERVE97__RESERVE_MASK 0xFFFFFFFFL 281895c1f7aaSFeifei Xu //DAGB0_RESERVE98 281995c1f7aaSFeifei Xu #define DAGB0_RESERVE98__RESERVE__SHIFT 0x0 282095c1f7aaSFeifei Xu #define DAGB0_RESERVE98__RESERVE_MASK 0xFFFFFFFFL 282195c1f7aaSFeifei Xu //DAGB0_RESERVE99 282295c1f7aaSFeifei Xu #define DAGB0_RESERVE99__RESERVE__SHIFT 0x0 282395c1f7aaSFeifei Xu #define DAGB0_RESERVE99__RESERVE_MASK 0xFFFFFFFFL 282495c1f7aaSFeifei Xu //DAGB0_RESERVE100 282595c1f7aaSFeifei Xu #define DAGB0_RESERVE100__RESERVE__SHIFT 0x0 282695c1f7aaSFeifei Xu #define DAGB0_RESERVE100__RESERVE_MASK 0xFFFFFFFFL 282795c1f7aaSFeifei Xu //DAGB0_RESERVE101 282895c1f7aaSFeifei Xu #define DAGB0_RESERVE101__RESERVE__SHIFT 0x0 282995c1f7aaSFeifei Xu #define DAGB0_RESERVE101__RESERVE_MASK 0xFFFFFFFFL 283095c1f7aaSFeifei Xu 283195c1f7aaSFeifei Xu 283295c1f7aaSFeifei Xu // addressBlock: mmhub_ea_mmeadec 283395c1f7aaSFeifei Xu //MMEA0_DRAM_RD_CLI2GRP_MAP0 283495c1f7aaSFeifei Xu #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 283595c1f7aaSFeifei Xu #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 283695c1f7aaSFeifei Xu #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 283795c1f7aaSFeifei Xu #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 283895c1f7aaSFeifei Xu #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 283995c1f7aaSFeifei Xu #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa 284095c1f7aaSFeifei Xu #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc 284195c1f7aaSFeifei Xu #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe 284295c1f7aaSFeifei Xu #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 284395c1f7aaSFeifei Xu #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 284495c1f7aaSFeifei Xu #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 284595c1f7aaSFeifei Xu #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 284695c1f7aaSFeifei Xu #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 284795c1f7aaSFeifei Xu #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a 284895c1f7aaSFeifei Xu #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c 284995c1f7aaSFeifei Xu #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e 285095c1f7aaSFeifei Xu #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L 285195c1f7aaSFeifei Xu #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL 285295c1f7aaSFeifei Xu #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L 285395c1f7aaSFeifei Xu #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L 285495c1f7aaSFeifei Xu #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L 285595c1f7aaSFeifei Xu #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L 285695c1f7aaSFeifei Xu #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L 285795c1f7aaSFeifei Xu #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L 285895c1f7aaSFeifei Xu #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L 285995c1f7aaSFeifei Xu #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L 286095c1f7aaSFeifei Xu #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L 286195c1f7aaSFeifei Xu #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L 286295c1f7aaSFeifei Xu #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L 286395c1f7aaSFeifei Xu #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L 286495c1f7aaSFeifei Xu #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L 286595c1f7aaSFeifei Xu #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L 286695c1f7aaSFeifei Xu //MMEA0_DRAM_RD_CLI2GRP_MAP1 286795c1f7aaSFeifei Xu #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 286895c1f7aaSFeifei Xu #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 286995c1f7aaSFeifei Xu #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 287095c1f7aaSFeifei Xu #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 287195c1f7aaSFeifei Xu #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 287295c1f7aaSFeifei Xu #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa 287395c1f7aaSFeifei Xu #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc 287495c1f7aaSFeifei Xu #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe 287595c1f7aaSFeifei Xu #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 287695c1f7aaSFeifei Xu #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 287795c1f7aaSFeifei Xu #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 287895c1f7aaSFeifei Xu #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 287995c1f7aaSFeifei Xu #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 288095c1f7aaSFeifei Xu #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a 288195c1f7aaSFeifei Xu #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c 288295c1f7aaSFeifei Xu #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e 288395c1f7aaSFeifei Xu #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L 288495c1f7aaSFeifei Xu #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL 288595c1f7aaSFeifei Xu #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L 288695c1f7aaSFeifei Xu #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L 288795c1f7aaSFeifei Xu #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L 288895c1f7aaSFeifei Xu #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L 288995c1f7aaSFeifei Xu #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L 289095c1f7aaSFeifei Xu #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L 289195c1f7aaSFeifei Xu #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L 289295c1f7aaSFeifei Xu #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L 289395c1f7aaSFeifei Xu #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L 289495c1f7aaSFeifei Xu #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L 289595c1f7aaSFeifei Xu #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L 289695c1f7aaSFeifei Xu #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L 289795c1f7aaSFeifei Xu #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L 289895c1f7aaSFeifei Xu #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L 289995c1f7aaSFeifei Xu //MMEA0_DRAM_WR_CLI2GRP_MAP0 290095c1f7aaSFeifei Xu #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 290195c1f7aaSFeifei Xu #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 290295c1f7aaSFeifei Xu #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 290395c1f7aaSFeifei Xu #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 290495c1f7aaSFeifei Xu #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 290595c1f7aaSFeifei Xu #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa 290695c1f7aaSFeifei Xu #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc 290795c1f7aaSFeifei Xu #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe 290895c1f7aaSFeifei Xu #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 290995c1f7aaSFeifei Xu #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 291095c1f7aaSFeifei Xu #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 291195c1f7aaSFeifei Xu #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 291295c1f7aaSFeifei Xu #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 291395c1f7aaSFeifei Xu #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a 291495c1f7aaSFeifei Xu #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c 291595c1f7aaSFeifei Xu #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e 291695c1f7aaSFeifei Xu #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L 291795c1f7aaSFeifei Xu #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL 291895c1f7aaSFeifei Xu #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L 291995c1f7aaSFeifei Xu #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L 292095c1f7aaSFeifei Xu #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L 292195c1f7aaSFeifei Xu #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L 292295c1f7aaSFeifei Xu #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L 292395c1f7aaSFeifei Xu #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L 292495c1f7aaSFeifei Xu #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L 292595c1f7aaSFeifei Xu #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L 292695c1f7aaSFeifei Xu #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L 292795c1f7aaSFeifei Xu #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L 292895c1f7aaSFeifei Xu #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L 292995c1f7aaSFeifei Xu #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L 293095c1f7aaSFeifei Xu #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L 293195c1f7aaSFeifei Xu #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L 293295c1f7aaSFeifei Xu //MMEA0_DRAM_WR_CLI2GRP_MAP1 293395c1f7aaSFeifei Xu #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 293495c1f7aaSFeifei Xu #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 293595c1f7aaSFeifei Xu #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 293695c1f7aaSFeifei Xu #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 293795c1f7aaSFeifei Xu #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 293895c1f7aaSFeifei Xu #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa 293995c1f7aaSFeifei Xu #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc 294095c1f7aaSFeifei Xu #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe 294195c1f7aaSFeifei Xu #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 294295c1f7aaSFeifei Xu #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 294395c1f7aaSFeifei Xu #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 294495c1f7aaSFeifei Xu #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 294595c1f7aaSFeifei Xu #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 294695c1f7aaSFeifei Xu #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a 294795c1f7aaSFeifei Xu #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c 294895c1f7aaSFeifei Xu #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e 294995c1f7aaSFeifei Xu #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L 295095c1f7aaSFeifei Xu #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL 295195c1f7aaSFeifei Xu #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L 295295c1f7aaSFeifei Xu #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L 295395c1f7aaSFeifei Xu #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L 295495c1f7aaSFeifei Xu #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L 295595c1f7aaSFeifei Xu #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L 295695c1f7aaSFeifei Xu #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L 295795c1f7aaSFeifei Xu #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L 295895c1f7aaSFeifei Xu #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L 295995c1f7aaSFeifei Xu #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L 296095c1f7aaSFeifei Xu #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L 296195c1f7aaSFeifei Xu #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L 296295c1f7aaSFeifei Xu #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L 296395c1f7aaSFeifei Xu #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L 296495c1f7aaSFeifei Xu #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L 296595c1f7aaSFeifei Xu //MMEA0_DRAM_RD_GRP2VC_MAP 296695c1f7aaSFeifei Xu #define MMEA0_DRAM_RD_GRP2VC_MAP__GROUP0_VC__SHIFT 0x0 296795c1f7aaSFeifei Xu #define MMEA0_DRAM_RD_GRP2VC_MAP__GROUP1_VC__SHIFT 0x3 296895c1f7aaSFeifei Xu #define MMEA0_DRAM_RD_GRP2VC_MAP__GROUP2_VC__SHIFT 0x6 296995c1f7aaSFeifei Xu #define MMEA0_DRAM_RD_GRP2VC_MAP__GROUP3_VC__SHIFT 0x9 297095c1f7aaSFeifei Xu #define MMEA0_DRAM_RD_GRP2VC_MAP__GROUP0_VC_MASK 0x00000007L 297195c1f7aaSFeifei Xu #define MMEA0_DRAM_RD_GRP2VC_MAP__GROUP1_VC_MASK 0x00000038L 297295c1f7aaSFeifei Xu #define MMEA0_DRAM_RD_GRP2VC_MAP__GROUP2_VC_MASK 0x000001C0L 297395c1f7aaSFeifei Xu #define MMEA0_DRAM_RD_GRP2VC_MAP__GROUP3_VC_MASK 0x00000E00L 297495c1f7aaSFeifei Xu //MMEA0_DRAM_WR_GRP2VC_MAP 297595c1f7aaSFeifei Xu #define MMEA0_DRAM_WR_GRP2VC_MAP__GROUP0_VC__SHIFT 0x0 297695c1f7aaSFeifei Xu #define MMEA0_DRAM_WR_GRP2VC_MAP__GROUP1_VC__SHIFT 0x3 297795c1f7aaSFeifei Xu #define MMEA0_DRAM_WR_GRP2VC_MAP__GROUP2_VC__SHIFT 0x6 297895c1f7aaSFeifei Xu #define MMEA0_DRAM_WR_GRP2VC_MAP__GROUP3_VC__SHIFT 0x9 297995c1f7aaSFeifei Xu #define MMEA0_DRAM_WR_GRP2VC_MAP__GROUP0_VC_MASK 0x00000007L 298095c1f7aaSFeifei Xu #define MMEA0_DRAM_WR_GRP2VC_MAP__GROUP1_VC_MASK 0x00000038L 298195c1f7aaSFeifei Xu #define MMEA0_DRAM_WR_GRP2VC_MAP__GROUP2_VC_MASK 0x000001C0L 298295c1f7aaSFeifei Xu #define MMEA0_DRAM_WR_GRP2VC_MAP__GROUP3_VC_MASK 0x00000E00L 298395c1f7aaSFeifei Xu //MMEA0_DRAM_RD_LAZY 298495c1f7aaSFeifei Xu #define MMEA0_DRAM_RD_LAZY__GROUP0_DELAY__SHIFT 0x0 298595c1f7aaSFeifei Xu #define MMEA0_DRAM_RD_LAZY__GROUP1_DELAY__SHIFT 0x3 298695c1f7aaSFeifei Xu #define MMEA0_DRAM_RD_LAZY__GROUP2_DELAY__SHIFT 0x6 298795c1f7aaSFeifei Xu #define MMEA0_DRAM_RD_LAZY__GROUP3_DELAY__SHIFT 0x9 298895c1f7aaSFeifei Xu #define MMEA0_DRAM_RD_LAZY__GROUP0_DELAY_MASK 0x00000007L 298995c1f7aaSFeifei Xu #define MMEA0_DRAM_RD_LAZY__GROUP1_DELAY_MASK 0x00000038L 299095c1f7aaSFeifei Xu #define MMEA0_DRAM_RD_LAZY__GROUP2_DELAY_MASK 0x000001C0L 299195c1f7aaSFeifei Xu #define MMEA0_DRAM_RD_LAZY__GROUP3_DELAY_MASK 0x00000E00L 299295c1f7aaSFeifei Xu //MMEA0_DRAM_WR_LAZY 299395c1f7aaSFeifei Xu #define MMEA0_DRAM_WR_LAZY__GROUP0_DELAY__SHIFT 0x0 299495c1f7aaSFeifei Xu #define MMEA0_DRAM_WR_LAZY__GROUP1_DELAY__SHIFT 0x3 299595c1f7aaSFeifei Xu #define MMEA0_DRAM_WR_LAZY__GROUP2_DELAY__SHIFT 0x6 299695c1f7aaSFeifei Xu #define MMEA0_DRAM_WR_LAZY__GROUP3_DELAY__SHIFT 0x9 299795c1f7aaSFeifei Xu #define MMEA0_DRAM_WR_LAZY__GROUP0_DELAY_MASK 0x00000007L 299895c1f7aaSFeifei Xu #define MMEA0_DRAM_WR_LAZY__GROUP1_DELAY_MASK 0x00000038L 299995c1f7aaSFeifei Xu #define MMEA0_DRAM_WR_LAZY__GROUP2_DELAY_MASK 0x000001C0L 300095c1f7aaSFeifei Xu #define MMEA0_DRAM_WR_LAZY__GROUP3_DELAY_MASK 0x00000E00L 300195c1f7aaSFeifei Xu //MMEA0_DRAM_RD_CAM_CNTL 300295c1f7aaSFeifei Xu #define MMEA0_DRAM_RD_CAM_CNTL__DEPTH_GROUP0__SHIFT 0x0 300395c1f7aaSFeifei Xu #define MMEA0_DRAM_RD_CAM_CNTL__DEPTH_GROUP1__SHIFT 0x4 300495c1f7aaSFeifei Xu #define MMEA0_DRAM_RD_CAM_CNTL__DEPTH_GROUP2__SHIFT 0x8 300595c1f7aaSFeifei Xu #define MMEA0_DRAM_RD_CAM_CNTL__DEPTH_GROUP3__SHIFT 0xc 300695c1f7aaSFeifei Xu #define MMEA0_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT 0x10 300795c1f7aaSFeifei Xu #define MMEA0_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT 0x13 300895c1f7aaSFeifei Xu #define MMEA0_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT 0x16 300995c1f7aaSFeifei Xu #define MMEA0_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT 0x19 301095c1f7aaSFeifei Xu #define MMEA0_DRAM_RD_CAM_CNTL__DEPTH_GROUP0_MASK 0x0000000FL 301195c1f7aaSFeifei Xu #define MMEA0_DRAM_RD_CAM_CNTL__DEPTH_GROUP1_MASK 0x000000F0L 301295c1f7aaSFeifei Xu #define MMEA0_DRAM_RD_CAM_CNTL__DEPTH_GROUP2_MASK 0x00000F00L 301395c1f7aaSFeifei Xu #define MMEA0_DRAM_RD_CAM_CNTL__DEPTH_GROUP3_MASK 0x0000F000L 301495c1f7aaSFeifei Xu #define MMEA0_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK 0x00070000L 301595c1f7aaSFeifei Xu #define MMEA0_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK 0x00380000L 301695c1f7aaSFeifei Xu #define MMEA0_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK 0x01C00000L 301795c1f7aaSFeifei Xu #define MMEA0_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK 0x0E000000L 301895c1f7aaSFeifei Xu //MMEA0_DRAM_WR_CAM_CNTL 301995c1f7aaSFeifei Xu #define MMEA0_DRAM_WR_CAM_CNTL__DEPTH_GROUP0__SHIFT 0x0 302095c1f7aaSFeifei Xu #define MMEA0_DRAM_WR_CAM_CNTL__DEPTH_GROUP1__SHIFT 0x4 302195c1f7aaSFeifei Xu #define MMEA0_DRAM_WR_CAM_CNTL__DEPTH_GROUP2__SHIFT 0x8 302295c1f7aaSFeifei Xu #define MMEA0_DRAM_WR_CAM_CNTL__DEPTH_GROUP3__SHIFT 0xc 302395c1f7aaSFeifei Xu #define MMEA0_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT 0x10 302495c1f7aaSFeifei Xu #define MMEA0_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT 0x13 302595c1f7aaSFeifei Xu #define MMEA0_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT 0x16 302695c1f7aaSFeifei Xu #define MMEA0_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT 0x19 302795c1f7aaSFeifei Xu #define MMEA0_DRAM_WR_CAM_CNTL__DEPTH_GROUP0_MASK 0x0000000FL 302895c1f7aaSFeifei Xu #define MMEA0_DRAM_WR_CAM_CNTL__DEPTH_GROUP1_MASK 0x000000F0L 302995c1f7aaSFeifei Xu #define MMEA0_DRAM_WR_CAM_CNTL__DEPTH_GROUP2_MASK 0x00000F00L 303095c1f7aaSFeifei Xu #define MMEA0_DRAM_WR_CAM_CNTL__DEPTH_GROUP3_MASK 0x0000F000L 303195c1f7aaSFeifei Xu #define MMEA0_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK 0x00070000L 303295c1f7aaSFeifei Xu #define MMEA0_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK 0x00380000L 303395c1f7aaSFeifei Xu #define MMEA0_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK 0x01C00000L 303495c1f7aaSFeifei Xu #define MMEA0_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK 0x0E000000L 303595c1f7aaSFeifei Xu //MMEA0_DRAM_PAGE_BURST 303695c1f7aaSFeifei Xu #define MMEA0_DRAM_PAGE_BURST__RD_LIMIT_LO__SHIFT 0x0 303795c1f7aaSFeifei Xu #define MMEA0_DRAM_PAGE_BURST__RD_LIMIT_HI__SHIFT 0x8 303895c1f7aaSFeifei Xu #define MMEA0_DRAM_PAGE_BURST__WR_LIMIT_LO__SHIFT 0x10 303995c1f7aaSFeifei Xu #define MMEA0_DRAM_PAGE_BURST__WR_LIMIT_HI__SHIFT 0x18 304095c1f7aaSFeifei Xu #define MMEA0_DRAM_PAGE_BURST__RD_LIMIT_LO_MASK 0x000000FFL 304195c1f7aaSFeifei Xu #define MMEA0_DRAM_PAGE_BURST__RD_LIMIT_HI_MASK 0x0000FF00L 304295c1f7aaSFeifei Xu #define MMEA0_DRAM_PAGE_BURST__WR_LIMIT_LO_MASK 0x00FF0000L 304395c1f7aaSFeifei Xu #define MMEA0_DRAM_PAGE_BURST__WR_LIMIT_HI_MASK 0xFF000000L 304495c1f7aaSFeifei Xu //MMEA0_DRAM_RD_PRI_AGE 304595c1f7aaSFeifei Xu #define MMEA0_DRAM_RD_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 304695c1f7aaSFeifei Xu #define MMEA0_DRAM_RD_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 304795c1f7aaSFeifei Xu #define MMEA0_DRAM_RD_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 304895c1f7aaSFeifei Xu #define MMEA0_DRAM_RD_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 304995c1f7aaSFeifei Xu #define MMEA0_DRAM_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc 305095c1f7aaSFeifei Xu #define MMEA0_DRAM_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf 305195c1f7aaSFeifei Xu #define MMEA0_DRAM_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 305295c1f7aaSFeifei Xu #define MMEA0_DRAM_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 305395c1f7aaSFeifei Xu #define MMEA0_DRAM_RD_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L 305495c1f7aaSFeifei Xu #define MMEA0_DRAM_RD_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L 305595c1f7aaSFeifei Xu #define MMEA0_DRAM_RD_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L 305695c1f7aaSFeifei Xu #define MMEA0_DRAM_RD_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L 305795c1f7aaSFeifei Xu #define MMEA0_DRAM_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L 305895c1f7aaSFeifei Xu #define MMEA0_DRAM_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L 305995c1f7aaSFeifei Xu #define MMEA0_DRAM_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L 306095c1f7aaSFeifei Xu #define MMEA0_DRAM_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L 306195c1f7aaSFeifei Xu //MMEA0_DRAM_WR_PRI_AGE 306295c1f7aaSFeifei Xu #define MMEA0_DRAM_WR_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 306395c1f7aaSFeifei Xu #define MMEA0_DRAM_WR_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 306495c1f7aaSFeifei Xu #define MMEA0_DRAM_WR_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 306595c1f7aaSFeifei Xu #define MMEA0_DRAM_WR_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 306695c1f7aaSFeifei Xu #define MMEA0_DRAM_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc 306795c1f7aaSFeifei Xu #define MMEA0_DRAM_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf 306895c1f7aaSFeifei Xu #define MMEA0_DRAM_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 306995c1f7aaSFeifei Xu #define MMEA0_DRAM_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 307095c1f7aaSFeifei Xu #define MMEA0_DRAM_WR_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L 307195c1f7aaSFeifei Xu #define MMEA0_DRAM_WR_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L 307295c1f7aaSFeifei Xu #define MMEA0_DRAM_WR_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L 307395c1f7aaSFeifei Xu #define MMEA0_DRAM_WR_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L 307495c1f7aaSFeifei Xu #define MMEA0_DRAM_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L 307595c1f7aaSFeifei Xu #define MMEA0_DRAM_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L 307695c1f7aaSFeifei Xu #define MMEA0_DRAM_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L 307795c1f7aaSFeifei Xu #define MMEA0_DRAM_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L 307895c1f7aaSFeifei Xu //MMEA0_DRAM_RD_PRI_QUEUING 307995c1f7aaSFeifei Xu #define MMEA0_DRAM_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 308095c1f7aaSFeifei Xu #define MMEA0_DRAM_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 308195c1f7aaSFeifei Xu #define MMEA0_DRAM_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 308295c1f7aaSFeifei Xu #define MMEA0_DRAM_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 308395c1f7aaSFeifei Xu #define MMEA0_DRAM_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L 308495c1f7aaSFeifei Xu #define MMEA0_DRAM_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L 308595c1f7aaSFeifei Xu #define MMEA0_DRAM_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L 308695c1f7aaSFeifei Xu #define MMEA0_DRAM_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L 308795c1f7aaSFeifei Xu //MMEA0_DRAM_WR_PRI_QUEUING 308895c1f7aaSFeifei Xu #define MMEA0_DRAM_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 308995c1f7aaSFeifei Xu #define MMEA0_DRAM_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 309095c1f7aaSFeifei Xu #define MMEA0_DRAM_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 309195c1f7aaSFeifei Xu #define MMEA0_DRAM_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 309295c1f7aaSFeifei Xu #define MMEA0_DRAM_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L 309395c1f7aaSFeifei Xu #define MMEA0_DRAM_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L 309495c1f7aaSFeifei Xu #define MMEA0_DRAM_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L 309595c1f7aaSFeifei Xu #define MMEA0_DRAM_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L 309695c1f7aaSFeifei Xu //MMEA0_DRAM_RD_PRI_FIXED 309795c1f7aaSFeifei Xu #define MMEA0_DRAM_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 309895c1f7aaSFeifei Xu #define MMEA0_DRAM_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 309995c1f7aaSFeifei Xu #define MMEA0_DRAM_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 310095c1f7aaSFeifei Xu #define MMEA0_DRAM_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 310195c1f7aaSFeifei Xu #define MMEA0_DRAM_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L 310295c1f7aaSFeifei Xu #define MMEA0_DRAM_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L 310395c1f7aaSFeifei Xu #define MMEA0_DRAM_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L 310495c1f7aaSFeifei Xu #define MMEA0_DRAM_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L 310595c1f7aaSFeifei Xu //MMEA0_DRAM_WR_PRI_FIXED 310695c1f7aaSFeifei Xu #define MMEA0_DRAM_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 310795c1f7aaSFeifei Xu #define MMEA0_DRAM_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 310895c1f7aaSFeifei Xu #define MMEA0_DRAM_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 310995c1f7aaSFeifei Xu #define MMEA0_DRAM_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 311095c1f7aaSFeifei Xu #define MMEA0_DRAM_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L 311195c1f7aaSFeifei Xu #define MMEA0_DRAM_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L 311295c1f7aaSFeifei Xu #define MMEA0_DRAM_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L 311395c1f7aaSFeifei Xu #define MMEA0_DRAM_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L 311495c1f7aaSFeifei Xu //MMEA0_DRAM_RD_PRI_URGENCY 311595c1f7aaSFeifei Xu #define MMEA0_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 311695c1f7aaSFeifei Xu #define MMEA0_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 311795c1f7aaSFeifei Xu #define MMEA0_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 311895c1f7aaSFeifei Xu #define MMEA0_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 311995c1f7aaSFeifei Xu #define MMEA0_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc 312095c1f7aaSFeifei Xu #define MMEA0_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd 312195c1f7aaSFeifei Xu #define MMEA0_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe 312295c1f7aaSFeifei Xu #define MMEA0_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf 312395c1f7aaSFeifei Xu #define MMEA0_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L 312495c1f7aaSFeifei Xu #define MMEA0_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L 312595c1f7aaSFeifei Xu #define MMEA0_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L 312695c1f7aaSFeifei Xu #define MMEA0_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L 312795c1f7aaSFeifei Xu #define MMEA0_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L 312895c1f7aaSFeifei Xu #define MMEA0_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L 312995c1f7aaSFeifei Xu #define MMEA0_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L 313095c1f7aaSFeifei Xu #define MMEA0_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L 313195c1f7aaSFeifei Xu //MMEA0_DRAM_WR_PRI_URGENCY 313295c1f7aaSFeifei Xu #define MMEA0_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 313395c1f7aaSFeifei Xu #define MMEA0_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 313495c1f7aaSFeifei Xu #define MMEA0_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 313595c1f7aaSFeifei Xu #define MMEA0_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 313695c1f7aaSFeifei Xu #define MMEA0_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc 313795c1f7aaSFeifei Xu #define MMEA0_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd 313895c1f7aaSFeifei Xu #define MMEA0_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe 313995c1f7aaSFeifei Xu #define MMEA0_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf 314095c1f7aaSFeifei Xu #define MMEA0_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L 314195c1f7aaSFeifei Xu #define MMEA0_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L 314295c1f7aaSFeifei Xu #define MMEA0_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L 314395c1f7aaSFeifei Xu #define MMEA0_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L 314495c1f7aaSFeifei Xu #define MMEA0_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L 314595c1f7aaSFeifei Xu #define MMEA0_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L 314695c1f7aaSFeifei Xu #define MMEA0_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L 314795c1f7aaSFeifei Xu #define MMEA0_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L 314895c1f7aaSFeifei Xu //MMEA0_DRAM_RD_PRI_QUANT_PRI1 314995c1f7aaSFeifei Xu #define MMEA0_DRAM_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 315095c1f7aaSFeifei Xu #define MMEA0_DRAM_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 315195c1f7aaSFeifei Xu #define MMEA0_DRAM_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 315295c1f7aaSFeifei Xu #define MMEA0_DRAM_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 315395c1f7aaSFeifei Xu #define MMEA0_DRAM_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL 315495c1f7aaSFeifei Xu #define MMEA0_DRAM_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L 315595c1f7aaSFeifei Xu #define MMEA0_DRAM_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L 315695c1f7aaSFeifei Xu #define MMEA0_DRAM_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L 315795c1f7aaSFeifei Xu //MMEA0_DRAM_RD_PRI_QUANT_PRI2 315895c1f7aaSFeifei Xu #define MMEA0_DRAM_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 315995c1f7aaSFeifei Xu #define MMEA0_DRAM_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 316095c1f7aaSFeifei Xu #define MMEA0_DRAM_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 316195c1f7aaSFeifei Xu #define MMEA0_DRAM_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 316295c1f7aaSFeifei Xu #define MMEA0_DRAM_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL 316395c1f7aaSFeifei Xu #define MMEA0_DRAM_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L 316495c1f7aaSFeifei Xu #define MMEA0_DRAM_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L 316595c1f7aaSFeifei Xu #define MMEA0_DRAM_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L 316695c1f7aaSFeifei Xu //MMEA0_DRAM_RD_PRI_QUANT_PRI3 316795c1f7aaSFeifei Xu #define MMEA0_DRAM_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 316895c1f7aaSFeifei Xu #define MMEA0_DRAM_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 316995c1f7aaSFeifei Xu #define MMEA0_DRAM_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 317095c1f7aaSFeifei Xu #define MMEA0_DRAM_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 317195c1f7aaSFeifei Xu #define MMEA0_DRAM_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL 317295c1f7aaSFeifei Xu #define MMEA0_DRAM_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L 317395c1f7aaSFeifei Xu #define MMEA0_DRAM_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L 317495c1f7aaSFeifei Xu #define MMEA0_DRAM_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L 317595c1f7aaSFeifei Xu //MMEA0_DRAM_WR_PRI_QUANT_PRI1 317695c1f7aaSFeifei Xu #define MMEA0_DRAM_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 317795c1f7aaSFeifei Xu #define MMEA0_DRAM_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 317895c1f7aaSFeifei Xu #define MMEA0_DRAM_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 317995c1f7aaSFeifei Xu #define MMEA0_DRAM_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 318095c1f7aaSFeifei Xu #define MMEA0_DRAM_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL 318195c1f7aaSFeifei Xu #define MMEA0_DRAM_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L 318295c1f7aaSFeifei Xu #define MMEA0_DRAM_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L 318395c1f7aaSFeifei Xu #define MMEA0_DRAM_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L 318495c1f7aaSFeifei Xu //MMEA0_DRAM_WR_PRI_QUANT_PRI2 318595c1f7aaSFeifei Xu #define MMEA0_DRAM_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 318695c1f7aaSFeifei Xu #define MMEA0_DRAM_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 318795c1f7aaSFeifei Xu #define MMEA0_DRAM_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 318895c1f7aaSFeifei Xu #define MMEA0_DRAM_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 318995c1f7aaSFeifei Xu #define MMEA0_DRAM_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL 319095c1f7aaSFeifei Xu #define MMEA0_DRAM_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L 319195c1f7aaSFeifei Xu #define MMEA0_DRAM_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L 319295c1f7aaSFeifei Xu #define MMEA0_DRAM_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L 319395c1f7aaSFeifei Xu //MMEA0_DRAM_WR_PRI_QUANT_PRI3 319495c1f7aaSFeifei Xu #define MMEA0_DRAM_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 319595c1f7aaSFeifei Xu #define MMEA0_DRAM_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 319695c1f7aaSFeifei Xu #define MMEA0_DRAM_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 319795c1f7aaSFeifei Xu #define MMEA0_DRAM_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 319895c1f7aaSFeifei Xu #define MMEA0_DRAM_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL 319995c1f7aaSFeifei Xu #define MMEA0_DRAM_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L 320095c1f7aaSFeifei Xu #define MMEA0_DRAM_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L 320195c1f7aaSFeifei Xu #define MMEA0_DRAM_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L 320295c1f7aaSFeifei Xu //MMEA0_ADDRNORM_BASE_ADDR0 320395c1f7aaSFeifei Xu #define MMEA0_ADDRNORM_BASE_ADDR0__ADDR_RNG_VAL__SHIFT 0x0 320495c1f7aaSFeifei Xu #define MMEA0_ADDRNORM_BASE_ADDR0__LGCY_MMIO_HOLE_EN__SHIFT 0x1 320595c1f7aaSFeifei Xu #define MMEA0_ADDRNORM_BASE_ADDR0__INTLV_NUM_CHAN__SHIFT 0x4 320695c1f7aaSFeifei Xu #define MMEA0_ADDRNORM_BASE_ADDR0__INTLV_ADDR_SEL__SHIFT 0x8 320795c1f7aaSFeifei Xu #define MMEA0_ADDRNORM_BASE_ADDR0__BASE_ADDR__SHIFT 0xc 320895c1f7aaSFeifei Xu #define MMEA0_ADDRNORM_BASE_ADDR0__ADDR_RNG_VAL_MASK 0x00000001L 320995c1f7aaSFeifei Xu #define MMEA0_ADDRNORM_BASE_ADDR0__LGCY_MMIO_HOLE_EN_MASK 0x00000002L 321095c1f7aaSFeifei Xu #define MMEA0_ADDRNORM_BASE_ADDR0__INTLV_NUM_CHAN_MASK 0x000000F0L 321195c1f7aaSFeifei Xu #define MMEA0_ADDRNORM_BASE_ADDR0__INTLV_ADDR_SEL_MASK 0x00000700L 321295c1f7aaSFeifei Xu #define MMEA0_ADDRNORM_BASE_ADDR0__BASE_ADDR_MASK 0xFFFFF000L 321395c1f7aaSFeifei Xu //MMEA0_ADDRNORM_LIMIT_ADDR0 321495c1f7aaSFeifei Xu #define MMEA0_ADDRNORM_LIMIT_ADDR0__DST_FABRIC_ID__SHIFT 0x0 321595c1f7aaSFeifei Xu #define MMEA0_ADDRNORM_LIMIT_ADDR0__INTLV_NUM_SOCKETS__SHIFT 0x8 321695c1f7aaSFeifei Xu #define MMEA0_ADDRNORM_LIMIT_ADDR0__INTLV_NUM_DIES__SHIFT 0xa 321795c1f7aaSFeifei Xu #define MMEA0_ADDRNORM_LIMIT_ADDR0__LIMIT_ADDR__SHIFT 0xc 321895c1f7aaSFeifei Xu #define MMEA0_ADDRNORM_LIMIT_ADDR0__DST_FABRIC_ID_MASK 0x0000000FL 321995c1f7aaSFeifei Xu #define MMEA0_ADDRNORM_LIMIT_ADDR0__INTLV_NUM_SOCKETS_MASK 0x00000100L 322095c1f7aaSFeifei Xu #define MMEA0_ADDRNORM_LIMIT_ADDR0__INTLV_NUM_DIES_MASK 0x00000C00L 322195c1f7aaSFeifei Xu #define MMEA0_ADDRNORM_LIMIT_ADDR0__LIMIT_ADDR_MASK 0xFFFFF000L 322295c1f7aaSFeifei Xu //MMEA0_ADDRNORM_BASE_ADDR1 322395c1f7aaSFeifei Xu #define MMEA0_ADDRNORM_BASE_ADDR1__ADDR_RNG_VAL__SHIFT 0x0 322495c1f7aaSFeifei Xu #define MMEA0_ADDRNORM_BASE_ADDR1__LGCY_MMIO_HOLE_EN__SHIFT 0x1 322595c1f7aaSFeifei Xu #define MMEA0_ADDRNORM_BASE_ADDR1__INTLV_NUM_CHAN__SHIFT 0x4 322695c1f7aaSFeifei Xu #define MMEA0_ADDRNORM_BASE_ADDR1__INTLV_ADDR_SEL__SHIFT 0x8 322795c1f7aaSFeifei Xu #define MMEA0_ADDRNORM_BASE_ADDR1__BASE_ADDR__SHIFT 0xc 322895c1f7aaSFeifei Xu #define MMEA0_ADDRNORM_BASE_ADDR1__ADDR_RNG_VAL_MASK 0x00000001L 322995c1f7aaSFeifei Xu #define MMEA0_ADDRNORM_BASE_ADDR1__LGCY_MMIO_HOLE_EN_MASK 0x00000002L 323095c1f7aaSFeifei Xu #define MMEA0_ADDRNORM_BASE_ADDR1__INTLV_NUM_CHAN_MASK 0x000000F0L 323195c1f7aaSFeifei Xu #define MMEA0_ADDRNORM_BASE_ADDR1__INTLV_ADDR_SEL_MASK 0x00000700L 323295c1f7aaSFeifei Xu #define MMEA0_ADDRNORM_BASE_ADDR1__BASE_ADDR_MASK 0xFFFFF000L 323395c1f7aaSFeifei Xu //MMEA0_ADDRNORM_LIMIT_ADDR1 323495c1f7aaSFeifei Xu #define MMEA0_ADDRNORM_LIMIT_ADDR1__DST_FABRIC_ID__SHIFT 0x0 323595c1f7aaSFeifei Xu #define MMEA0_ADDRNORM_LIMIT_ADDR1__INTLV_NUM_SOCKETS__SHIFT 0x8 323695c1f7aaSFeifei Xu #define MMEA0_ADDRNORM_LIMIT_ADDR1__INTLV_NUM_DIES__SHIFT 0xa 323795c1f7aaSFeifei Xu #define MMEA0_ADDRNORM_LIMIT_ADDR1__LIMIT_ADDR__SHIFT 0xc 323895c1f7aaSFeifei Xu #define MMEA0_ADDRNORM_LIMIT_ADDR1__DST_FABRIC_ID_MASK 0x0000000FL 323995c1f7aaSFeifei Xu #define MMEA0_ADDRNORM_LIMIT_ADDR1__INTLV_NUM_SOCKETS_MASK 0x00000100L 324095c1f7aaSFeifei Xu #define MMEA0_ADDRNORM_LIMIT_ADDR1__INTLV_NUM_DIES_MASK 0x00000C00L 324195c1f7aaSFeifei Xu #define MMEA0_ADDRNORM_LIMIT_ADDR1__LIMIT_ADDR_MASK 0xFFFFF000L 324295c1f7aaSFeifei Xu //MMEA0_ADDRNORM_OFFSET_ADDR1 324395c1f7aaSFeifei Xu #define MMEA0_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET_EN__SHIFT 0x0 324495c1f7aaSFeifei Xu #define MMEA0_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET__SHIFT 0x14 324595c1f7aaSFeifei Xu #define MMEA0_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET_EN_MASK 0x00000001L 324695c1f7aaSFeifei Xu #define MMEA0_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET_MASK 0xFFF00000L 324795c1f7aaSFeifei Xu //MMEA0_ADDRNORM_HOLE_CNTL 324895c1f7aaSFeifei Xu #define MMEA0_ADDRNORM_HOLE_CNTL__DRAM_HOLE_VALID__SHIFT 0x0 324995c1f7aaSFeifei Xu #define MMEA0_ADDRNORM_HOLE_CNTL__DRAM_HOLE_OFFSET__SHIFT 0x7 325095c1f7aaSFeifei Xu #define MMEA0_ADDRNORM_HOLE_CNTL__DRAM_HOLE_VALID_MASK 0x00000001L 325195c1f7aaSFeifei Xu #define MMEA0_ADDRNORM_HOLE_CNTL__DRAM_HOLE_OFFSET_MASK 0x0000FF80L 325295c1f7aaSFeifei Xu //MMEA0_ADDRDEC_BANK_CFG 325395c1f7aaSFeifei Xu #define MMEA0_ADDRDEC_BANK_CFG__BANK_MASK_DRAM__SHIFT 0x0 325495c1f7aaSFeifei Xu #define MMEA0_ADDRDEC_BANK_CFG__BANK_MASK_GMI__SHIFT 0x5 325595c1f7aaSFeifei Xu #define MMEA0_ADDRDEC_BANK_CFG__BANKGROUP_SEL_DRAM__SHIFT 0xa 325695c1f7aaSFeifei Xu #define MMEA0_ADDRDEC_BANK_CFG__BANKGROUP_SEL_GMI__SHIFT 0xd 325795c1f7aaSFeifei Xu #define MMEA0_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_DRAM__SHIFT 0x10 325895c1f7aaSFeifei Xu #define MMEA0_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_GMI__SHIFT 0x11 325995c1f7aaSFeifei Xu #define MMEA0_ADDRDEC_BANK_CFG__BANK_MASK_DRAM_MASK 0x0000001FL 326095c1f7aaSFeifei Xu #define MMEA0_ADDRDEC_BANK_CFG__BANK_MASK_GMI_MASK 0x000003E0L 326195c1f7aaSFeifei Xu #define MMEA0_ADDRDEC_BANK_CFG__BANKGROUP_SEL_DRAM_MASK 0x00001C00L 326295c1f7aaSFeifei Xu #define MMEA0_ADDRDEC_BANK_CFG__BANKGROUP_SEL_GMI_MASK 0x0000E000L 326395c1f7aaSFeifei Xu #define MMEA0_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_DRAM_MASK 0x00010000L 326495c1f7aaSFeifei Xu #define MMEA0_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_GMI_MASK 0x00020000L 326595c1f7aaSFeifei Xu //MMEA0_ADDRDEC_MISC_CFG 326695c1f7aaSFeifei Xu #define MMEA0_ADDRDEC_MISC_CFG__VCM_EN0__SHIFT 0x0 326795c1f7aaSFeifei Xu #define MMEA0_ADDRDEC_MISC_CFG__VCM_EN1__SHIFT 0x1 326895c1f7aaSFeifei Xu #define MMEA0_ADDRDEC_MISC_CFG__VCM_EN2__SHIFT 0x2 326995c1f7aaSFeifei Xu #define MMEA0_ADDRDEC_MISC_CFG__VCM_EN3__SHIFT 0x3 327095c1f7aaSFeifei Xu #define MMEA0_ADDRDEC_MISC_CFG__VCM_EN4__SHIFT 0x4 327195c1f7aaSFeifei Xu #define MMEA0_ADDRDEC_MISC_CFG__PCH_MASK_DRAM__SHIFT 0x8 327295c1f7aaSFeifei Xu #define MMEA0_ADDRDEC_MISC_CFG__PCH_MASK_GMI__SHIFT 0x9 327395c1f7aaSFeifei Xu #define MMEA0_ADDRDEC_MISC_CFG__CH_MASK_DRAM__SHIFT 0xc 327495c1f7aaSFeifei Xu #define MMEA0_ADDRDEC_MISC_CFG__CH_MASK_GMI__SHIFT 0x10 327595c1f7aaSFeifei Xu #define MMEA0_ADDRDEC_MISC_CFG__CS_MASK_DRAM__SHIFT 0x14 327695c1f7aaSFeifei Xu #define MMEA0_ADDRDEC_MISC_CFG__CS_MASK_GMI__SHIFT 0x16 327795c1f7aaSFeifei Xu #define MMEA0_ADDRDEC_MISC_CFG__RM_MASK_DRAM__SHIFT 0x18 327895c1f7aaSFeifei Xu #define MMEA0_ADDRDEC_MISC_CFG__RM_MASK_GMI__SHIFT 0x1b 327995c1f7aaSFeifei Xu #define MMEA0_ADDRDEC_MISC_CFG__VCM_EN0_MASK 0x00000001L 328095c1f7aaSFeifei Xu #define MMEA0_ADDRDEC_MISC_CFG__VCM_EN1_MASK 0x00000002L 328195c1f7aaSFeifei Xu #define MMEA0_ADDRDEC_MISC_CFG__VCM_EN2_MASK 0x00000004L 328295c1f7aaSFeifei Xu #define MMEA0_ADDRDEC_MISC_CFG__VCM_EN3_MASK 0x00000008L 328395c1f7aaSFeifei Xu #define MMEA0_ADDRDEC_MISC_CFG__VCM_EN4_MASK 0x00000010L 328495c1f7aaSFeifei Xu #define MMEA0_ADDRDEC_MISC_CFG__PCH_MASK_DRAM_MASK 0x00000100L 328595c1f7aaSFeifei Xu #define MMEA0_ADDRDEC_MISC_CFG__PCH_MASK_GMI_MASK 0x00000200L 328695c1f7aaSFeifei Xu #define MMEA0_ADDRDEC_MISC_CFG__CH_MASK_DRAM_MASK 0x0000F000L 328795c1f7aaSFeifei Xu #define MMEA0_ADDRDEC_MISC_CFG__CH_MASK_GMI_MASK 0x000F0000L 328895c1f7aaSFeifei Xu #define MMEA0_ADDRDEC_MISC_CFG__CS_MASK_DRAM_MASK 0x00300000L 328995c1f7aaSFeifei Xu #define MMEA0_ADDRDEC_MISC_CFG__CS_MASK_GMI_MASK 0x00C00000L 329095c1f7aaSFeifei Xu #define MMEA0_ADDRDEC_MISC_CFG__RM_MASK_DRAM_MASK 0x07000000L 329195c1f7aaSFeifei Xu #define MMEA0_ADDRDEC_MISC_CFG__RM_MASK_GMI_MASK 0x38000000L 329295c1f7aaSFeifei Xu //MMEA0_ADDRDECDRAM_ADDR_HASH_BANK0 329395c1f7aaSFeifei Xu #define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK0__XOR_ENABLE__SHIFT 0x0 329495c1f7aaSFeifei Xu #define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK0__COL_XOR__SHIFT 0x1 329595c1f7aaSFeifei Xu #define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK0__ROW_XOR__SHIFT 0xe 329695c1f7aaSFeifei Xu #define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK0__XOR_ENABLE_MASK 0x00000001L 329795c1f7aaSFeifei Xu #define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK0__COL_XOR_MASK 0x00003FFEL 329895c1f7aaSFeifei Xu #define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK0__ROW_XOR_MASK 0xFFFFC000L 329995c1f7aaSFeifei Xu //MMEA0_ADDRDECDRAM_ADDR_HASH_BANK1 330095c1f7aaSFeifei Xu #define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK1__XOR_ENABLE__SHIFT 0x0 330195c1f7aaSFeifei Xu #define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK1__COL_XOR__SHIFT 0x1 330295c1f7aaSFeifei Xu #define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK1__ROW_XOR__SHIFT 0xe 330395c1f7aaSFeifei Xu #define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK1__XOR_ENABLE_MASK 0x00000001L 330495c1f7aaSFeifei Xu #define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK1__COL_XOR_MASK 0x00003FFEL 330595c1f7aaSFeifei Xu #define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK1__ROW_XOR_MASK 0xFFFFC000L 330695c1f7aaSFeifei Xu //MMEA0_ADDRDECDRAM_ADDR_HASH_BANK2 330795c1f7aaSFeifei Xu #define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK2__XOR_ENABLE__SHIFT 0x0 330895c1f7aaSFeifei Xu #define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK2__COL_XOR__SHIFT 0x1 330995c1f7aaSFeifei Xu #define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK2__ROW_XOR__SHIFT 0xe 331095c1f7aaSFeifei Xu #define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK2__XOR_ENABLE_MASK 0x00000001L 331195c1f7aaSFeifei Xu #define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK2__COL_XOR_MASK 0x00003FFEL 331295c1f7aaSFeifei Xu #define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK2__ROW_XOR_MASK 0xFFFFC000L 331395c1f7aaSFeifei Xu //MMEA0_ADDRDECDRAM_ADDR_HASH_BANK3 331495c1f7aaSFeifei Xu #define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK3__XOR_ENABLE__SHIFT 0x0 331595c1f7aaSFeifei Xu #define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK3__COL_XOR__SHIFT 0x1 331695c1f7aaSFeifei Xu #define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK3__ROW_XOR__SHIFT 0xe 331795c1f7aaSFeifei Xu #define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK3__XOR_ENABLE_MASK 0x00000001L 331895c1f7aaSFeifei Xu #define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK3__COL_XOR_MASK 0x00003FFEL 331995c1f7aaSFeifei Xu #define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK3__ROW_XOR_MASK 0xFFFFC000L 332095c1f7aaSFeifei Xu //MMEA0_ADDRDECDRAM_ADDR_HASH_BANK4 332195c1f7aaSFeifei Xu #define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK4__XOR_ENABLE__SHIFT 0x0 332295c1f7aaSFeifei Xu #define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK4__COL_XOR__SHIFT 0x1 332395c1f7aaSFeifei Xu #define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK4__ROW_XOR__SHIFT 0xe 332495c1f7aaSFeifei Xu #define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK4__XOR_ENABLE_MASK 0x00000001L 332595c1f7aaSFeifei Xu #define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK4__COL_XOR_MASK 0x00003FFEL 332695c1f7aaSFeifei Xu #define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK4__ROW_XOR_MASK 0xFFFFC000L 332795c1f7aaSFeifei Xu //MMEA0_ADDRDECDRAM_ADDR_HASH_PC 332895c1f7aaSFeifei Xu #define MMEA0_ADDRDECDRAM_ADDR_HASH_PC__XOR_ENABLE__SHIFT 0x0 332995c1f7aaSFeifei Xu #define MMEA0_ADDRDECDRAM_ADDR_HASH_PC__COL_XOR__SHIFT 0x1 333095c1f7aaSFeifei Xu #define MMEA0_ADDRDECDRAM_ADDR_HASH_PC__ROW_XOR__SHIFT 0xe 333195c1f7aaSFeifei Xu #define MMEA0_ADDRDECDRAM_ADDR_HASH_PC__XOR_ENABLE_MASK 0x00000001L 333295c1f7aaSFeifei Xu #define MMEA0_ADDRDECDRAM_ADDR_HASH_PC__COL_XOR_MASK 0x00003FFEL 333395c1f7aaSFeifei Xu #define MMEA0_ADDRDECDRAM_ADDR_HASH_PC__ROW_XOR_MASK 0xFFFFC000L 333495c1f7aaSFeifei Xu //MMEA0_ADDRDECDRAM_ADDR_HASH_PC2 333595c1f7aaSFeifei Xu #define MMEA0_ADDRDECDRAM_ADDR_HASH_PC2__BANK_XOR__SHIFT 0x0 333695c1f7aaSFeifei Xu #define MMEA0_ADDRDECDRAM_ADDR_HASH_PC2__BANK_XOR_MASK 0x0000001FL 333795c1f7aaSFeifei Xu //MMEA0_ADDRDECDRAM_ADDR_HASH_CS0 333895c1f7aaSFeifei Xu #define MMEA0_ADDRDECDRAM_ADDR_HASH_CS0__XOR_ENABLE__SHIFT 0x0 333995c1f7aaSFeifei Xu #define MMEA0_ADDRDECDRAM_ADDR_HASH_CS0__NA_XOR__SHIFT 0x1 334095c1f7aaSFeifei Xu #define MMEA0_ADDRDECDRAM_ADDR_HASH_CS0__XOR_ENABLE_MASK 0x00000001L 334195c1f7aaSFeifei Xu #define MMEA0_ADDRDECDRAM_ADDR_HASH_CS0__NA_XOR_MASK 0xFFFFFFFEL 334295c1f7aaSFeifei Xu //MMEA0_ADDRDECDRAM_ADDR_HASH_CS1 334395c1f7aaSFeifei Xu #define MMEA0_ADDRDECDRAM_ADDR_HASH_CS1__XOR_ENABLE__SHIFT 0x0 334495c1f7aaSFeifei Xu #define MMEA0_ADDRDECDRAM_ADDR_HASH_CS1__NA_XOR__SHIFT 0x1 334595c1f7aaSFeifei Xu #define MMEA0_ADDRDECDRAM_ADDR_HASH_CS1__XOR_ENABLE_MASK 0x00000001L 334695c1f7aaSFeifei Xu #define MMEA0_ADDRDECDRAM_ADDR_HASH_CS1__NA_XOR_MASK 0xFFFFFFFEL 334795c1f7aaSFeifei Xu //MMEA0_ADDRDECDRAM_HARVEST_ENABLE 334895c1f7aaSFeifei Xu #define MMEA0_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_EN__SHIFT 0x0 334995c1f7aaSFeifei Xu #define MMEA0_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_VAL__SHIFT 0x1 335095c1f7aaSFeifei Xu #define MMEA0_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_EN__SHIFT 0x2 335195c1f7aaSFeifei Xu #define MMEA0_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_VAL__SHIFT 0x3 335295c1f7aaSFeifei Xu #define MMEA0_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_EN_MASK 0x00000001L 335395c1f7aaSFeifei Xu #define MMEA0_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_VAL_MASK 0x00000002L 335495c1f7aaSFeifei Xu #define MMEA0_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_EN_MASK 0x00000004L 335595c1f7aaSFeifei Xu #define MMEA0_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_VAL_MASK 0x00000008L 335695c1f7aaSFeifei Xu //MMEA0_ADDRDEC0_BASE_ADDR_CS0 335795c1f7aaSFeifei Xu #define MMEA0_ADDRDEC0_BASE_ADDR_CS0__CS_ENABLE__SHIFT 0x0 335895c1f7aaSFeifei Xu #define MMEA0_ADDRDEC0_BASE_ADDR_CS0__BASE_ADDR__SHIFT 0x1 335995c1f7aaSFeifei Xu #define MMEA0_ADDRDEC0_BASE_ADDR_CS0__CS_ENABLE_MASK 0x00000001L 336095c1f7aaSFeifei Xu #define MMEA0_ADDRDEC0_BASE_ADDR_CS0__BASE_ADDR_MASK 0xFFFFFFFEL 336195c1f7aaSFeifei Xu //MMEA0_ADDRDEC0_BASE_ADDR_CS1 336295c1f7aaSFeifei Xu #define MMEA0_ADDRDEC0_BASE_ADDR_CS1__CS_ENABLE__SHIFT 0x0 336395c1f7aaSFeifei Xu #define MMEA0_ADDRDEC0_BASE_ADDR_CS1__BASE_ADDR__SHIFT 0x1 336495c1f7aaSFeifei Xu #define MMEA0_ADDRDEC0_BASE_ADDR_CS1__CS_ENABLE_MASK 0x00000001L 336595c1f7aaSFeifei Xu #define MMEA0_ADDRDEC0_BASE_ADDR_CS1__BASE_ADDR_MASK 0xFFFFFFFEL 336695c1f7aaSFeifei Xu //MMEA0_ADDRDEC0_BASE_ADDR_CS2 336795c1f7aaSFeifei Xu #define MMEA0_ADDRDEC0_BASE_ADDR_CS2__CS_ENABLE__SHIFT 0x0 336895c1f7aaSFeifei Xu #define MMEA0_ADDRDEC0_BASE_ADDR_CS2__BASE_ADDR__SHIFT 0x1 336995c1f7aaSFeifei Xu #define MMEA0_ADDRDEC0_BASE_ADDR_CS2__CS_ENABLE_MASK 0x00000001L 337095c1f7aaSFeifei Xu #define MMEA0_ADDRDEC0_BASE_ADDR_CS2__BASE_ADDR_MASK 0xFFFFFFFEL 337195c1f7aaSFeifei Xu //MMEA0_ADDRDEC0_BASE_ADDR_CS3 337295c1f7aaSFeifei Xu #define MMEA0_ADDRDEC0_BASE_ADDR_CS3__CS_ENABLE__SHIFT 0x0 337395c1f7aaSFeifei Xu #define MMEA0_ADDRDEC0_BASE_ADDR_CS3__BASE_ADDR__SHIFT 0x1 337495c1f7aaSFeifei Xu #define MMEA0_ADDRDEC0_BASE_ADDR_CS3__CS_ENABLE_MASK 0x00000001L 337595c1f7aaSFeifei Xu #define MMEA0_ADDRDEC0_BASE_ADDR_CS3__BASE_ADDR_MASK 0xFFFFFFFEL 337695c1f7aaSFeifei Xu //MMEA0_ADDRDEC0_BASE_ADDR_SECCS0 337795c1f7aaSFeifei Xu #define MMEA0_ADDRDEC0_BASE_ADDR_SECCS0__CS_ENABLE__SHIFT 0x0 337895c1f7aaSFeifei Xu #define MMEA0_ADDRDEC0_BASE_ADDR_SECCS0__BASE_ADDR__SHIFT 0x1 337995c1f7aaSFeifei Xu #define MMEA0_ADDRDEC0_BASE_ADDR_SECCS0__CS_ENABLE_MASK 0x00000001L 338095c1f7aaSFeifei Xu #define MMEA0_ADDRDEC0_BASE_ADDR_SECCS0__BASE_ADDR_MASK 0xFFFFFFFEL 338195c1f7aaSFeifei Xu //MMEA0_ADDRDEC0_BASE_ADDR_SECCS1 338295c1f7aaSFeifei Xu #define MMEA0_ADDRDEC0_BASE_ADDR_SECCS1__CS_ENABLE__SHIFT 0x0 338395c1f7aaSFeifei Xu #define MMEA0_ADDRDEC0_BASE_ADDR_SECCS1__BASE_ADDR__SHIFT 0x1 338495c1f7aaSFeifei Xu #define MMEA0_ADDRDEC0_BASE_ADDR_SECCS1__CS_ENABLE_MASK 0x00000001L 338595c1f7aaSFeifei Xu #define MMEA0_ADDRDEC0_BASE_ADDR_SECCS1__BASE_ADDR_MASK 0xFFFFFFFEL 338695c1f7aaSFeifei Xu //MMEA0_ADDRDEC0_BASE_ADDR_SECCS2 338795c1f7aaSFeifei Xu #define MMEA0_ADDRDEC0_BASE_ADDR_SECCS2__CS_ENABLE__SHIFT 0x0 338895c1f7aaSFeifei Xu #define MMEA0_ADDRDEC0_BASE_ADDR_SECCS2__BASE_ADDR__SHIFT 0x1 338995c1f7aaSFeifei Xu #define MMEA0_ADDRDEC0_BASE_ADDR_SECCS2__CS_ENABLE_MASK 0x00000001L 339095c1f7aaSFeifei Xu #define MMEA0_ADDRDEC0_BASE_ADDR_SECCS2__BASE_ADDR_MASK 0xFFFFFFFEL 339195c1f7aaSFeifei Xu //MMEA0_ADDRDEC0_BASE_ADDR_SECCS3 339295c1f7aaSFeifei Xu #define MMEA0_ADDRDEC0_BASE_ADDR_SECCS3__CS_ENABLE__SHIFT 0x0 339395c1f7aaSFeifei Xu #define MMEA0_ADDRDEC0_BASE_ADDR_SECCS3__BASE_ADDR__SHIFT 0x1 339495c1f7aaSFeifei Xu #define MMEA0_ADDRDEC0_BASE_ADDR_SECCS3__CS_ENABLE_MASK 0x00000001L 339595c1f7aaSFeifei Xu #define MMEA0_ADDRDEC0_BASE_ADDR_SECCS3__BASE_ADDR_MASK 0xFFFFFFFEL 339695c1f7aaSFeifei Xu //MMEA0_ADDRDEC0_ADDR_MASK_CS01 339795c1f7aaSFeifei Xu #define MMEA0_ADDRDEC0_ADDR_MASK_CS01__ADDR_MASK__SHIFT 0x1 339895c1f7aaSFeifei Xu #define MMEA0_ADDRDEC0_ADDR_MASK_CS01__ADDR_MASK_MASK 0xFFFFFFFEL 339995c1f7aaSFeifei Xu //MMEA0_ADDRDEC0_ADDR_MASK_CS23 340095c1f7aaSFeifei Xu #define MMEA0_ADDRDEC0_ADDR_MASK_CS23__ADDR_MASK__SHIFT 0x1 340195c1f7aaSFeifei Xu #define MMEA0_ADDRDEC0_ADDR_MASK_CS23__ADDR_MASK_MASK 0xFFFFFFFEL 340295c1f7aaSFeifei Xu //MMEA0_ADDRDEC0_ADDR_MASK_SECCS01 340395c1f7aaSFeifei Xu #define MMEA0_ADDRDEC0_ADDR_MASK_SECCS01__ADDR_MASK__SHIFT 0x1 340495c1f7aaSFeifei Xu #define MMEA0_ADDRDEC0_ADDR_MASK_SECCS01__ADDR_MASK_MASK 0xFFFFFFFEL 340595c1f7aaSFeifei Xu //MMEA0_ADDRDEC0_ADDR_MASK_SECCS23 340695c1f7aaSFeifei Xu #define MMEA0_ADDRDEC0_ADDR_MASK_SECCS23__ADDR_MASK__SHIFT 0x1 340795c1f7aaSFeifei Xu #define MMEA0_ADDRDEC0_ADDR_MASK_SECCS23__ADDR_MASK_MASK 0xFFFFFFFEL 340895c1f7aaSFeifei Xu //MMEA0_ADDRDEC0_ADDR_CFG_CS01 340995c1f7aaSFeifei Xu #define MMEA0_ADDRDEC0_ADDR_CFG_CS01__NUM_BANK_GROUPS__SHIFT 0x2 341095c1f7aaSFeifei Xu #define MMEA0_ADDRDEC0_ADDR_CFG_CS01__NUM_RM__SHIFT 0x4 341195c1f7aaSFeifei Xu #define MMEA0_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_LO__SHIFT 0x8 341295c1f7aaSFeifei Xu #define MMEA0_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_HI__SHIFT 0xc 341395c1f7aaSFeifei Xu #define MMEA0_ADDRDEC0_ADDR_CFG_CS01__NUM_COL__SHIFT 0x10 341495c1f7aaSFeifei Xu #define MMEA0_ADDRDEC0_ADDR_CFG_CS01__NUM_BANKS__SHIFT 0x14 341595c1f7aaSFeifei Xu #define MMEA0_ADDRDEC0_ADDR_CFG_CS01__NUM_BANK_GROUPS_MASK 0x0000000CL 341695c1f7aaSFeifei Xu #define MMEA0_ADDRDEC0_ADDR_CFG_CS01__NUM_RM_MASK 0x00000030L 341795c1f7aaSFeifei Xu #define MMEA0_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_LO_MASK 0x00000F00L 341895c1f7aaSFeifei Xu #define MMEA0_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_HI_MASK 0x0000F000L 341995c1f7aaSFeifei Xu #define MMEA0_ADDRDEC0_ADDR_CFG_CS01__NUM_COL_MASK 0x000F0000L 342095c1f7aaSFeifei Xu #define MMEA0_ADDRDEC0_ADDR_CFG_CS01__NUM_BANKS_MASK 0x00300000L 342195c1f7aaSFeifei Xu //MMEA0_ADDRDEC0_ADDR_CFG_CS23 342295c1f7aaSFeifei Xu #define MMEA0_ADDRDEC0_ADDR_CFG_CS23__NUM_BANK_GROUPS__SHIFT 0x2 342395c1f7aaSFeifei Xu #define MMEA0_ADDRDEC0_ADDR_CFG_CS23__NUM_RM__SHIFT 0x4 342495c1f7aaSFeifei Xu #define MMEA0_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_LO__SHIFT 0x8 342595c1f7aaSFeifei Xu #define MMEA0_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_HI__SHIFT 0xc 342695c1f7aaSFeifei Xu #define MMEA0_ADDRDEC0_ADDR_CFG_CS23__NUM_COL__SHIFT 0x10 342795c1f7aaSFeifei Xu #define MMEA0_ADDRDEC0_ADDR_CFG_CS23__NUM_BANKS__SHIFT 0x14 342895c1f7aaSFeifei Xu #define MMEA0_ADDRDEC0_ADDR_CFG_CS23__NUM_BANK_GROUPS_MASK 0x0000000CL 342995c1f7aaSFeifei Xu #define MMEA0_ADDRDEC0_ADDR_CFG_CS23__NUM_RM_MASK 0x00000030L 343095c1f7aaSFeifei Xu #define MMEA0_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_LO_MASK 0x00000F00L 343195c1f7aaSFeifei Xu #define MMEA0_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_HI_MASK 0x0000F000L 343295c1f7aaSFeifei Xu #define MMEA0_ADDRDEC0_ADDR_CFG_CS23__NUM_COL_MASK 0x000F0000L 343395c1f7aaSFeifei Xu #define MMEA0_ADDRDEC0_ADDR_CFG_CS23__NUM_BANKS_MASK 0x00300000L 343495c1f7aaSFeifei Xu //MMEA0_ADDRDEC0_ADDR_SEL_CS01 343595c1f7aaSFeifei Xu #define MMEA0_ADDRDEC0_ADDR_SEL_CS01__BANK0__SHIFT 0x0 343695c1f7aaSFeifei Xu #define MMEA0_ADDRDEC0_ADDR_SEL_CS01__BANK1__SHIFT 0x4 343795c1f7aaSFeifei Xu #define MMEA0_ADDRDEC0_ADDR_SEL_CS01__BANK2__SHIFT 0x8 343895c1f7aaSFeifei Xu #define MMEA0_ADDRDEC0_ADDR_SEL_CS01__BANK3__SHIFT 0xc 343995c1f7aaSFeifei Xu #define MMEA0_ADDRDEC0_ADDR_SEL_CS01__BANK4__SHIFT 0x10 344095c1f7aaSFeifei Xu #define MMEA0_ADDRDEC0_ADDR_SEL_CS01__ROW_LO__SHIFT 0x18 344195c1f7aaSFeifei Xu #define MMEA0_ADDRDEC0_ADDR_SEL_CS01__ROW_HI__SHIFT 0x1c 344295c1f7aaSFeifei Xu #define MMEA0_ADDRDEC0_ADDR_SEL_CS01__BANK0_MASK 0x0000000FL 344395c1f7aaSFeifei Xu #define MMEA0_ADDRDEC0_ADDR_SEL_CS01__BANK1_MASK 0x000000F0L 344495c1f7aaSFeifei Xu #define MMEA0_ADDRDEC0_ADDR_SEL_CS01__BANK2_MASK 0x00000F00L 344595c1f7aaSFeifei Xu #define MMEA0_ADDRDEC0_ADDR_SEL_CS01__BANK3_MASK 0x0000F000L 344695c1f7aaSFeifei Xu #define MMEA0_ADDRDEC0_ADDR_SEL_CS01__BANK4_MASK 0x000F0000L 344795c1f7aaSFeifei Xu #define MMEA0_ADDRDEC0_ADDR_SEL_CS01__ROW_LO_MASK 0x0F000000L 344895c1f7aaSFeifei Xu #define MMEA0_ADDRDEC0_ADDR_SEL_CS01__ROW_HI_MASK 0xF0000000L 344995c1f7aaSFeifei Xu //MMEA0_ADDRDEC0_ADDR_SEL_CS23 345095c1f7aaSFeifei Xu #define MMEA0_ADDRDEC0_ADDR_SEL_CS23__BANK0__SHIFT 0x0 345195c1f7aaSFeifei Xu #define MMEA0_ADDRDEC0_ADDR_SEL_CS23__BANK1__SHIFT 0x4 345295c1f7aaSFeifei Xu #define MMEA0_ADDRDEC0_ADDR_SEL_CS23__BANK2__SHIFT 0x8 345395c1f7aaSFeifei Xu #define MMEA0_ADDRDEC0_ADDR_SEL_CS23__BANK3__SHIFT 0xc 345495c1f7aaSFeifei Xu #define MMEA0_ADDRDEC0_ADDR_SEL_CS23__BANK4__SHIFT 0x10 345595c1f7aaSFeifei Xu #define MMEA0_ADDRDEC0_ADDR_SEL_CS23__ROW_LO__SHIFT 0x18 345695c1f7aaSFeifei Xu #define MMEA0_ADDRDEC0_ADDR_SEL_CS23__ROW_HI__SHIFT 0x1c 345795c1f7aaSFeifei Xu #define MMEA0_ADDRDEC0_ADDR_SEL_CS23__BANK0_MASK 0x0000000FL 345895c1f7aaSFeifei Xu #define MMEA0_ADDRDEC0_ADDR_SEL_CS23__BANK1_MASK 0x000000F0L 345995c1f7aaSFeifei Xu #define MMEA0_ADDRDEC0_ADDR_SEL_CS23__BANK2_MASK 0x00000F00L 346095c1f7aaSFeifei Xu #define MMEA0_ADDRDEC0_ADDR_SEL_CS23__BANK3_MASK 0x0000F000L 346195c1f7aaSFeifei Xu #define MMEA0_ADDRDEC0_ADDR_SEL_CS23__BANK4_MASK 0x000F0000L 346295c1f7aaSFeifei Xu #define MMEA0_ADDRDEC0_ADDR_SEL_CS23__ROW_LO_MASK 0x0F000000L 346395c1f7aaSFeifei Xu #define MMEA0_ADDRDEC0_ADDR_SEL_CS23__ROW_HI_MASK 0xF0000000L 346495c1f7aaSFeifei Xu //MMEA0_ADDRDEC0_COL_SEL_LO_CS01 346595c1f7aaSFeifei Xu #define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL0__SHIFT 0x0 346695c1f7aaSFeifei Xu #define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL1__SHIFT 0x4 346795c1f7aaSFeifei Xu #define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL2__SHIFT 0x8 346895c1f7aaSFeifei Xu #define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL3__SHIFT 0xc 346995c1f7aaSFeifei Xu #define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL4__SHIFT 0x10 347095c1f7aaSFeifei Xu #define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL5__SHIFT 0x14 347195c1f7aaSFeifei Xu #define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL6__SHIFT 0x18 347295c1f7aaSFeifei Xu #define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL7__SHIFT 0x1c 347395c1f7aaSFeifei Xu #define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL0_MASK 0x0000000FL 347495c1f7aaSFeifei Xu #define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL1_MASK 0x000000F0L 347595c1f7aaSFeifei Xu #define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL2_MASK 0x00000F00L 347695c1f7aaSFeifei Xu #define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL3_MASK 0x0000F000L 347795c1f7aaSFeifei Xu #define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL4_MASK 0x000F0000L 347895c1f7aaSFeifei Xu #define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL5_MASK 0x00F00000L 347995c1f7aaSFeifei Xu #define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL6_MASK 0x0F000000L 348095c1f7aaSFeifei Xu #define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL7_MASK 0xF0000000L 348195c1f7aaSFeifei Xu //MMEA0_ADDRDEC0_COL_SEL_LO_CS23 348295c1f7aaSFeifei Xu #define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL0__SHIFT 0x0 348395c1f7aaSFeifei Xu #define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL1__SHIFT 0x4 348495c1f7aaSFeifei Xu #define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL2__SHIFT 0x8 348595c1f7aaSFeifei Xu #define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL3__SHIFT 0xc 348695c1f7aaSFeifei Xu #define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL4__SHIFT 0x10 348795c1f7aaSFeifei Xu #define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL5__SHIFT 0x14 348895c1f7aaSFeifei Xu #define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL6__SHIFT 0x18 348995c1f7aaSFeifei Xu #define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL7__SHIFT 0x1c 349095c1f7aaSFeifei Xu #define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL0_MASK 0x0000000FL 349195c1f7aaSFeifei Xu #define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL1_MASK 0x000000F0L 349295c1f7aaSFeifei Xu #define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL2_MASK 0x00000F00L 349395c1f7aaSFeifei Xu #define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL3_MASK 0x0000F000L 349495c1f7aaSFeifei Xu #define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL4_MASK 0x000F0000L 349595c1f7aaSFeifei Xu #define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL5_MASK 0x00F00000L 349695c1f7aaSFeifei Xu #define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL6_MASK 0x0F000000L 349795c1f7aaSFeifei Xu #define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL7_MASK 0xF0000000L 349895c1f7aaSFeifei Xu //MMEA0_ADDRDEC0_COL_SEL_HI_CS01 349995c1f7aaSFeifei Xu #define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL8__SHIFT 0x0 350095c1f7aaSFeifei Xu #define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL9__SHIFT 0x4 350195c1f7aaSFeifei Xu #define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL10__SHIFT 0x8 350295c1f7aaSFeifei Xu #define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL11__SHIFT 0xc 350395c1f7aaSFeifei Xu #define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL12__SHIFT 0x10 350495c1f7aaSFeifei Xu #define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL13__SHIFT 0x14 350595c1f7aaSFeifei Xu #define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL14__SHIFT 0x18 350695c1f7aaSFeifei Xu #define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL15__SHIFT 0x1c 350795c1f7aaSFeifei Xu #define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL8_MASK 0x0000000FL 350895c1f7aaSFeifei Xu #define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL9_MASK 0x000000F0L 350995c1f7aaSFeifei Xu #define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL10_MASK 0x00000F00L 351095c1f7aaSFeifei Xu #define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL11_MASK 0x0000F000L 351195c1f7aaSFeifei Xu #define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL12_MASK 0x000F0000L 351295c1f7aaSFeifei Xu #define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL13_MASK 0x00F00000L 351395c1f7aaSFeifei Xu #define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL14_MASK 0x0F000000L 351495c1f7aaSFeifei Xu #define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL15_MASK 0xF0000000L 351595c1f7aaSFeifei Xu //MMEA0_ADDRDEC0_COL_SEL_HI_CS23 351695c1f7aaSFeifei Xu #define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL8__SHIFT 0x0 351795c1f7aaSFeifei Xu #define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL9__SHIFT 0x4 351895c1f7aaSFeifei Xu #define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL10__SHIFT 0x8 351995c1f7aaSFeifei Xu #define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL11__SHIFT 0xc 352095c1f7aaSFeifei Xu #define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL12__SHIFT 0x10 352195c1f7aaSFeifei Xu #define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL13__SHIFT 0x14 352295c1f7aaSFeifei Xu #define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL14__SHIFT 0x18 352395c1f7aaSFeifei Xu #define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL15__SHIFT 0x1c 352495c1f7aaSFeifei Xu #define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL8_MASK 0x0000000FL 352595c1f7aaSFeifei Xu #define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL9_MASK 0x000000F0L 352695c1f7aaSFeifei Xu #define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL10_MASK 0x00000F00L 352795c1f7aaSFeifei Xu #define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL11_MASK 0x0000F000L 352895c1f7aaSFeifei Xu #define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL12_MASK 0x000F0000L 352995c1f7aaSFeifei Xu #define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL13_MASK 0x00F00000L 353095c1f7aaSFeifei Xu #define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL14_MASK 0x0F000000L 353195c1f7aaSFeifei Xu #define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL15_MASK 0xF0000000L 353295c1f7aaSFeifei Xu //MMEA0_ADDRDEC0_RM_SEL_CS01 353395c1f7aaSFeifei Xu #define MMEA0_ADDRDEC0_RM_SEL_CS01__RM0__SHIFT 0x0 353495c1f7aaSFeifei Xu #define MMEA0_ADDRDEC0_RM_SEL_CS01__RM1__SHIFT 0x4 353595c1f7aaSFeifei Xu #define MMEA0_ADDRDEC0_RM_SEL_CS01__RM2__SHIFT 0x8 353695c1f7aaSFeifei Xu #define MMEA0_ADDRDEC0_RM_SEL_CS01__CHAN_BIT__SHIFT 0xc 353795c1f7aaSFeifei Xu #define MMEA0_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 353895c1f7aaSFeifei Xu #define MMEA0_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12 353995c1f7aaSFeifei Xu #define MMEA0_ADDRDEC0_RM_SEL_CS01__RM0_MASK 0x0000000FL 354095c1f7aaSFeifei Xu #define MMEA0_ADDRDEC0_RM_SEL_CS01__RM1_MASK 0x000000F0L 354195c1f7aaSFeifei Xu #define MMEA0_ADDRDEC0_RM_SEL_CS01__RM2_MASK 0x00000F00L 354295c1f7aaSFeifei Xu #define MMEA0_ADDRDEC0_RM_SEL_CS01__CHAN_BIT_MASK 0x0000F000L 354395c1f7aaSFeifei Xu #define MMEA0_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L 354495c1f7aaSFeifei Xu #define MMEA0_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L 354595c1f7aaSFeifei Xu //MMEA0_ADDRDEC0_RM_SEL_CS23 354695c1f7aaSFeifei Xu #define MMEA0_ADDRDEC0_RM_SEL_CS23__RM0__SHIFT 0x0 354795c1f7aaSFeifei Xu #define MMEA0_ADDRDEC0_RM_SEL_CS23__RM1__SHIFT 0x4 354895c1f7aaSFeifei Xu #define MMEA0_ADDRDEC0_RM_SEL_CS23__RM2__SHIFT 0x8 354995c1f7aaSFeifei Xu #define MMEA0_ADDRDEC0_RM_SEL_CS23__CHAN_BIT__SHIFT 0xc 355095c1f7aaSFeifei Xu #define MMEA0_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 355195c1f7aaSFeifei Xu #define MMEA0_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12 355295c1f7aaSFeifei Xu #define MMEA0_ADDRDEC0_RM_SEL_CS23__RM0_MASK 0x0000000FL 355395c1f7aaSFeifei Xu #define MMEA0_ADDRDEC0_RM_SEL_CS23__RM1_MASK 0x000000F0L 355495c1f7aaSFeifei Xu #define MMEA0_ADDRDEC0_RM_SEL_CS23__RM2_MASK 0x00000F00L 355595c1f7aaSFeifei Xu #define MMEA0_ADDRDEC0_RM_SEL_CS23__CHAN_BIT_MASK 0x0000F000L 355695c1f7aaSFeifei Xu #define MMEA0_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L 355795c1f7aaSFeifei Xu #define MMEA0_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L 355895c1f7aaSFeifei Xu //MMEA0_ADDRDEC0_RM_SEL_SECCS01 355995c1f7aaSFeifei Xu #define MMEA0_ADDRDEC0_RM_SEL_SECCS01__RM0__SHIFT 0x0 356095c1f7aaSFeifei Xu #define MMEA0_ADDRDEC0_RM_SEL_SECCS01__RM1__SHIFT 0x4 356195c1f7aaSFeifei Xu #define MMEA0_ADDRDEC0_RM_SEL_SECCS01__RM2__SHIFT 0x8 356295c1f7aaSFeifei Xu #define MMEA0_ADDRDEC0_RM_SEL_SECCS01__CHAN_BIT__SHIFT 0xc 356395c1f7aaSFeifei Xu #define MMEA0_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 356495c1f7aaSFeifei Xu #define MMEA0_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12 356595c1f7aaSFeifei Xu #define MMEA0_ADDRDEC0_RM_SEL_SECCS01__RM0_MASK 0x0000000FL 356695c1f7aaSFeifei Xu #define MMEA0_ADDRDEC0_RM_SEL_SECCS01__RM1_MASK 0x000000F0L 356795c1f7aaSFeifei Xu #define MMEA0_ADDRDEC0_RM_SEL_SECCS01__RM2_MASK 0x00000F00L 356895c1f7aaSFeifei Xu #define MMEA0_ADDRDEC0_RM_SEL_SECCS01__CHAN_BIT_MASK 0x0000F000L 356995c1f7aaSFeifei Xu #define MMEA0_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L 357095c1f7aaSFeifei Xu #define MMEA0_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L 357195c1f7aaSFeifei Xu //MMEA0_ADDRDEC0_RM_SEL_SECCS23 357295c1f7aaSFeifei Xu #define MMEA0_ADDRDEC0_RM_SEL_SECCS23__RM0__SHIFT 0x0 357395c1f7aaSFeifei Xu #define MMEA0_ADDRDEC0_RM_SEL_SECCS23__RM1__SHIFT 0x4 357495c1f7aaSFeifei Xu #define MMEA0_ADDRDEC0_RM_SEL_SECCS23__RM2__SHIFT 0x8 357595c1f7aaSFeifei Xu #define MMEA0_ADDRDEC0_RM_SEL_SECCS23__CHAN_BIT__SHIFT 0xc 357695c1f7aaSFeifei Xu #define MMEA0_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 357795c1f7aaSFeifei Xu #define MMEA0_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12 357895c1f7aaSFeifei Xu #define MMEA0_ADDRDEC0_RM_SEL_SECCS23__RM0_MASK 0x0000000FL 357995c1f7aaSFeifei Xu #define MMEA0_ADDRDEC0_RM_SEL_SECCS23__RM1_MASK 0x000000F0L 358095c1f7aaSFeifei Xu #define MMEA0_ADDRDEC0_RM_SEL_SECCS23__RM2_MASK 0x00000F00L 358195c1f7aaSFeifei Xu #define MMEA0_ADDRDEC0_RM_SEL_SECCS23__CHAN_BIT_MASK 0x0000F000L 358295c1f7aaSFeifei Xu #define MMEA0_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L 358395c1f7aaSFeifei Xu #define MMEA0_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L 358495c1f7aaSFeifei Xu //MMEA0_ADDRDEC1_BASE_ADDR_CS0 358595c1f7aaSFeifei Xu #define MMEA0_ADDRDEC1_BASE_ADDR_CS0__CS_ENABLE__SHIFT 0x0 358695c1f7aaSFeifei Xu #define MMEA0_ADDRDEC1_BASE_ADDR_CS0__BASE_ADDR__SHIFT 0x1 358795c1f7aaSFeifei Xu #define MMEA0_ADDRDEC1_BASE_ADDR_CS0__CS_ENABLE_MASK 0x00000001L 358895c1f7aaSFeifei Xu #define MMEA0_ADDRDEC1_BASE_ADDR_CS0__BASE_ADDR_MASK 0xFFFFFFFEL 358995c1f7aaSFeifei Xu //MMEA0_ADDRDEC1_BASE_ADDR_CS1 359095c1f7aaSFeifei Xu #define MMEA0_ADDRDEC1_BASE_ADDR_CS1__CS_ENABLE__SHIFT 0x0 359195c1f7aaSFeifei Xu #define MMEA0_ADDRDEC1_BASE_ADDR_CS1__BASE_ADDR__SHIFT 0x1 359295c1f7aaSFeifei Xu #define MMEA0_ADDRDEC1_BASE_ADDR_CS1__CS_ENABLE_MASK 0x00000001L 359395c1f7aaSFeifei Xu #define MMEA0_ADDRDEC1_BASE_ADDR_CS1__BASE_ADDR_MASK 0xFFFFFFFEL 359495c1f7aaSFeifei Xu //MMEA0_ADDRDEC1_BASE_ADDR_CS2 359595c1f7aaSFeifei Xu #define MMEA0_ADDRDEC1_BASE_ADDR_CS2__CS_ENABLE__SHIFT 0x0 359695c1f7aaSFeifei Xu #define MMEA0_ADDRDEC1_BASE_ADDR_CS2__BASE_ADDR__SHIFT 0x1 359795c1f7aaSFeifei Xu #define MMEA0_ADDRDEC1_BASE_ADDR_CS2__CS_ENABLE_MASK 0x00000001L 359895c1f7aaSFeifei Xu #define MMEA0_ADDRDEC1_BASE_ADDR_CS2__BASE_ADDR_MASK 0xFFFFFFFEL 359995c1f7aaSFeifei Xu //MMEA0_ADDRDEC1_BASE_ADDR_CS3 360095c1f7aaSFeifei Xu #define MMEA0_ADDRDEC1_BASE_ADDR_CS3__CS_ENABLE__SHIFT 0x0 360195c1f7aaSFeifei Xu #define MMEA0_ADDRDEC1_BASE_ADDR_CS3__BASE_ADDR__SHIFT 0x1 360295c1f7aaSFeifei Xu #define MMEA0_ADDRDEC1_BASE_ADDR_CS3__CS_ENABLE_MASK 0x00000001L 360395c1f7aaSFeifei Xu #define MMEA0_ADDRDEC1_BASE_ADDR_CS3__BASE_ADDR_MASK 0xFFFFFFFEL 360495c1f7aaSFeifei Xu //MMEA0_ADDRDEC1_BASE_ADDR_SECCS0 360595c1f7aaSFeifei Xu #define MMEA0_ADDRDEC1_BASE_ADDR_SECCS0__CS_ENABLE__SHIFT 0x0 360695c1f7aaSFeifei Xu #define MMEA0_ADDRDEC1_BASE_ADDR_SECCS0__BASE_ADDR__SHIFT 0x1 360795c1f7aaSFeifei Xu #define MMEA0_ADDRDEC1_BASE_ADDR_SECCS0__CS_ENABLE_MASK 0x00000001L 360895c1f7aaSFeifei Xu #define MMEA0_ADDRDEC1_BASE_ADDR_SECCS0__BASE_ADDR_MASK 0xFFFFFFFEL 360995c1f7aaSFeifei Xu //MMEA0_ADDRDEC1_BASE_ADDR_SECCS1 361095c1f7aaSFeifei Xu #define MMEA0_ADDRDEC1_BASE_ADDR_SECCS1__CS_ENABLE__SHIFT 0x0 361195c1f7aaSFeifei Xu #define MMEA0_ADDRDEC1_BASE_ADDR_SECCS1__BASE_ADDR__SHIFT 0x1 361295c1f7aaSFeifei Xu #define MMEA0_ADDRDEC1_BASE_ADDR_SECCS1__CS_ENABLE_MASK 0x00000001L 361395c1f7aaSFeifei Xu #define MMEA0_ADDRDEC1_BASE_ADDR_SECCS1__BASE_ADDR_MASK 0xFFFFFFFEL 361495c1f7aaSFeifei Xu //MMEA0_ADDRDEC1_BASE_ADDR_SECCS2 361595c1f7aaSFeifei Xu #define MMEA0_ADDRDEC1_BASE_ADDR_SECCS2__CS_ENABLE__SHIFT 0x0 361695c1f7aaSFeifei Xu #define MMEA0_ADDRDEC1_BASE_ADDR_SECCS2__BASE_ADDR__SHIFT 0x1 361795c1f7aaSFeifei Xu #define MMEA0_ADDRDEC1_BASE_ADDR_SECCS2__CS_ENABLE_MASK 0x00000001L 361895c1f7aaSFeifei Xu #define MMEA0_ADDRDEC1_BASE_ADDR_SECCS2__BASE_ADDR_MASK 0xFFFFFFFEL 361995c1f7aaSFeifei Xu //MMEA0_ADDRDEC1_BASE_ADDR_SECCS3 362095c1f7aaSFeifei Xu #define MMEA0_ADDRDEC1_BASE_ADDR_SECCS3__CS_ENABLE__SHIFT 0x0 362195c1f7aaSFeifei Xu #define MMEA0_ADDRDEC1_BASE_ADDR_SECCS3__BASE_ADDR__SHIFT 0x1 362295c1f7aaSFeifei Xu #define MMEA0_ADDRDEC1_BASE_ADDR_SECCS3__CS_ENABLE_MASK 0x00000001L 362395c1f7aaSFeifei Xu #define MMEA0_ADDRDEC1_BASE_ADDR_SECCS3__BASE_ADDR_MASK 0xFFFFFFFEL 362495c1f7aaSFeifei Xu //MMEA0_ADDRDEC1_ADDR_MASK_CS01 362595c1f7aaSFeifei Xu #define MMEA0_ADDRDEC1_ADDR_MASK_CS01__ADDR_MASK__SHIFT 0x1 362695c1f7aaSFeifei Xu #define MMEA0_ADDRDEC1_ADDR_MASK_CS01__ADDR_MASK_MASK 0xFFFFFFFEL 362795c1f7aaSFeifei Xu //MMEA0_ADDRDEC1_ADDR_MASK_CS23 362895c1f7aaSFeifei Xu #define MMEA0_ADDRDEC1_ADDR_MASK_CS23__ADDR_MASK__SHIFT 0x1 362995c1f7aaSFeifei Xu #define MMEA0_ADDRDEC1_ADDR_MASK_CS23__ADDR_MASK_MASK 0xFFFFFFFEL 363095c1f7aaSFeifei Xu //MMEA0_ADDRDEC1_ADDR_MASK_SECCS01 363195c1f7aaSFeifei Xu #define MMEA0_ADDRDEC1_ADDR_MASK_SECCS01__ADDR_MASK__SHIFT 0x1 363295c1f7aaSFeifei Xu #define MMEA0_ADDRDEC1_ADDR_MASK_SECCS01__ADDR_MASK_MASK 0xFFFFFFFEL 363395c1f7aaSFeifei Xu //MMEA0_ADDRDEC1_ADDR_MASK_SECCS23 363495c1f7aaSFeifei Xu #define MMEA0_ADDRDEC1_ADDR_MASK_SECCS23__ADDR_MASK__SHIFT 0x1 363595c1f7aaSFeifei Xu #define MMEA0_ADDRDEC1_ADDR_MASK_SECCS23__ADDR_MASK_MASK 0xFFFFFFFEL 363695c1f7aaSFeifei Xu //MMEA0_ADDRDEC1_ADDR_CFG_CS01 363795c1f7aaSFeifei Xu #define MMEA0_ADDRDEC1_ADDR_CFG_CS01__NUM_BANK_GROUPS__SHIFT 0x2 363895c1f7aaSFeifei Xu #define MMEA0_ADDRDEC1_ADDR_CFG_CS01__NUM_RM__SHIFT 0x4 363995c1f7aaSFeifei Xu #define MMEA0_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_LO__SHIFT 0x8 364095c1f7aaSFeifei Xu #define MMEA0_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_HI__SHIFT 0xc 364195c1f7aaSFeifei Xu #define MMEA0_ADDRDEC1_ADDR_CFG_CS01__NUM_COL__SHIFT 0x10 364295c1f7aaSFeifei Xu #define MMEA0_ADDRDEC1_ADDR_CFG_CS01__NUM_BANKS__SHIFT 0x14 364395c1f7aaSFeifei Xu #define MMEA0_ADDRDEC1_ADDR_CFG_CS01__NUM_BANK_GROUPS_MASK 0x0000000CL 364495c1f7aaSFeifei Xu #define MMEA0_ADDRDEC1_ADDR_CFG_CS01__NUM_RM_MASK 0x00000030L 364595c1f7aaSFeifei Xu #define MMEA0_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_LO_MASK 0x00000F00L 364695c1f7aaSFeifei Xu #define MMEA0_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_HI_MASK 0x0000F000L 364795c1f7aaSFeifei Xu #define MMEA0_ADDRDEC1_ADDR_CFG_CS01__NUM_COL_MASK 0x000F0000L 364895c1f7aaSFeifei Xu #define MMEA0_ADDRDEC1_ADDR_CFG_CS01__NUM_BANKS_MASK 0x00300000L 364995c1f7aaSFeifei Xu //MMEA0_ADDRDEC1_ADDR_CFG_CS23 365095c1f7aaSFeifei Xu #define MMEA0_ADDRDEC1_ADDR_CFG_CS23__NUM_BANK_GROUPS__SHIFT 0x2 365195c1f7aaSFeifei Xu #define MMEA0_ADDRDEC1_ADDR_CFG_CS23__NUM_RM__SHIFT 0x4 365295c1f7aaSFeifei Xu #define MMEA0_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_LO__SHIFT 0x8 365395c1f7aaSFeifei Xu #define MMEA0_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_HI__SHIFT 0xc 365495c1f7aaSFeifei Xu #define MMEA0_ADDRDEC1_ADDR_CFG_CS23__NUM_COL__SHIFT 0x10 365595c1f7aaSFeifei Xu #define MMEA0_ADDRDEC1_ADDR_CFG_CS23__NUM_BANKS__SHIFT 0x14 365695c1f7aaSFeifei Xu #define MMEA0_ADDRDEC1_ADDR_CFG_CS23__NUM_BANK_GROUPS_MASK 0x0000000CL 365795c1f7aaSFeifei Xu #define MMEA0_ADDRDEC1_ADDR_CFG_CS23__NUM_RM_MASK 0x00000030L 365895c1f7aaSFeifei Xu #define MMEA0_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_LO_MASK 0x00000F00L 365995c1f7aaSFeifei Xu #define MMEA0_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_HI_MASK 0x0000F000L 366095c1f7aaSFeifei Xu #define MMEA0_ADDRDEC1_ADDR_CFG_CS23__NUM_COL_MASK 0x000F0000L 366195c1f7aaSFeifei Xu #define MMEA0_ADDRDEC1_ADDR_CFG_CS23__NUM_BANKS_MASK 0x00300000L 366295c1f7aaSFeifei Xu //MMEA0_ADDRDEC1_ADDR_SEL_CS01 366395c1f7aaSFeifei Xu #define MMEA0_ADDRDEC1_ADDR_SEL_CS01__BANK0__SHIFT 0x0 366495c1f7aaSFeifei Xu #define MMEA0_ADDRDEC1_ADDR_SEL_CS01__BANK1__SHIFT 0x4 366595c1f7aaSFeifei Xu #define MMEA0_ADDRDEC1_ADDR_SEL_CS01__BANK2__SHIFT 0x8 366695c1f7aaSFeifei Xu #define MMEA0_ADDRDEC1_ADDR_SEL_CS01__BANK3__SHIFT 0xc 366795c1f7aaSFeifei Xu #define MMEA0_ADDRDEC1_ADDR_SEL_CS01__BANK4__SHIFT 0x10 366895c1f7aaSFeifei Xu #define MMEA0_ADDRDEC1_ADDR_SEL_CS01__ROW_LO__SHIFT 0x18 366995c1f7aaSFeifei Xu #define MMEA0_ADDRDEC1_ADDR_SEL_CS01__ROW_HI__SHIFT 0x1c 367095c1f7aaSFeifei Xu #define MMEA0_ADDRDEC1_ADDR_SEL_CS01__BANK0_MASK 0x0000000FL 367195c1f7aaSFeifei Xu #define MMEA0_ADDRDEC1_ADDR_SEL_CS01__BANK1_MASK 0x000000F0L 367295c1f7aaSFeifei Xu #define MMEA0_ADDRDEC1_ADDR_SEL_CS01__BANK2_MASK 0x00000F00L 367395c1f7aaSFeifei Xu #define MMEA0_ADDRDEC1_ADDR_SEL_CS01__BANK3_MASK 0x0000F000L 367495c1f7aaSFeifei Xu #define MMEA0_ADDRDEC1_ADDR_SEL_CS01__BANK4_MASK 0x000F0000L 367595c1f7aaSFeifei Xu #define MMEA0_ADDRDEC1_ADDR_SEL_CS01__ROW_LO_MASK 0x0F000000L 367695c1f7aaSFeifei Xu #define MMEA0_ADDRDEC1_ADDR_SEL_CS01__ROW_HI_MASK 0xF0000000L 367795c1f7aaSFeifei Xu //MMEA0_ADDRDEC1_ADDR_SEL_CS23 367895c1f7aaSFeifei Xu #define MMEA0_ADDRDEC1_ADDR_SEL_CS23__BANK0__SHIFT 0x0 367995c1f7aaSFeifei Xu #define MMEA0_ADDRDEC1_ADDR_SEL_CS23__BANK1__SHIFT 0x4 368095c1f7aaSFeifei Xu #define MMEA0_ADDRDEC1_ADDR_SEL_CS23__BANK2__SHIFT 0x8 368195c1f7aaSFeifei Xu #define MMEA0_ADDRDEC1_ADDR_SEL_CS23__BANK3__SHIFT 0xc 368295c1f7aaSFeifei Xu #define MMEA0_ADDRDEC1_ADDR_SEL_CS23__BANK4__SHIFT 0x10 368395c1f7aaSFeifei Xu #define MMEA0_ADDRDEC1_ADDR_SEL_CS23__ROW_LO__SHIFT 0x18 368495c1f7aaSFeifei Xu #define MMEA0_ADDRDEC1_ADDR_SEL_CS23__ROW_HI__SHIFT 0x1c 368595c1f7aaSFeifei Xu #define MMEA0_ADDRDEC1_ADDR_SEL_CS23__BANK0_MASK 0x0000000FL 368695c1f7aaSFeifei Xu #define MMEA0_ADDRDEC1_ADDR_SEL_CS23__BANK1_MASK 0x000000F0L 368795c1f7aaSFeifei Xu #define MMEA0_ADDRDEC1_ADDR_SEL_CS23__BANK2_MASK 0x00000F00L 368895c1f7aaSFeifei Xu #define MMEA0_ADDRDEC1_ADDR_SEL_CS23__BANK3_MASK 0x0000F000L 368995c1f7aaSFeifei Xu #define MMEA0_ADDRDEC1_ADDR_SEL_CS23__BANK4_MASK 0x000F0000L 369095c1f7aaSFeifei Xu #define MMEA0_ADDRDEC1_ADDR_SEL_CS23__ROW_LO_MASK 0x0F000000L 369195c1f7aaSFeifei Xu #define MMEA0_ADDRDEC1_ADDR_SEL_CS23__ROW_HI_MASK 0xF0000000L 369295c1f7aaSFeifei Xu //MMEA0_ADDRDEC1_COL_SEL_LO_CS01 369395c1f7aaSFeifei Xu #define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL0__SHIFT 0x0 369495c1f7aaSFeifei Xu #define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL1__SHIFT 0x4 369595c1f7aaSFeifei Xu #define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL2__SHIFT 0x8 369695c1f7aaSFeifei Xu #define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL3__SHIFT 0xc 369795c1f7aaSFeifei Xu #define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL4__SHIFT 0x10 369895c1f7aaSFeifei Xu #define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL5__SHIFT 0x14 369995c1f7aaSFeifei Xu #define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL6__SHIFT 0x18 370095c1f7aaSFeifei Xu #define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL7__SHIFT 0x1c 370195c1f7aaSFeifei Xu #define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL0_MASK 0x0000000FL 370295c1f7aaSFeifei Xu #define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL1_MASK 0x000000F0L 370395c1f7aaSFeifei Xu #define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL2_MASK 0x00000F00L 370495c1f7aaSFeifei Xu #define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL3_MASK 0x0000F000L 370595c1f7aaSFeifei Xu #define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL4_MASK 0x000F0000L 370695c1f7aaSFeifei Xu #define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL5_MASK 0x00F00000L 370795c1f7aaSFeifei Xu #define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL6_MASK 0x0F000000L 370895c1f7aaSFeifei Xu #define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL7_MASK 0xF0000000L 370995c1f7aaSFeifei Xu //MMEA0_ADDRDEC1_COL_SEL_LO_CS23 371095c1f7aaSFeifei Xu #define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL0__SHIFT 0x0 371195c1f7aaSFeifei Xu #define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL1__SHIFT 0x4 371295c1f7aaSFeifei Xu #define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL2__SHIFT 0x8 371395c1f7aaSFeifei Xu #define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL3__SHIFT 0xc 371495c1f7aaSFeifei Xu #define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL4__SHIFT 0x10 371595c1f7aaSFeifei Xu #define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL5__SHIFT 0x14 371695c1f7aaSFeifei Xu #define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL6__SHIFT 0x18 371795c1f7aaSFeifei Xu #define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL7__SHIFT 0x1c 371895c1f7aaSFeifei Xu #define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL0_MASK 0x0000000FL 371995c1f7aaSFeifei Xu #define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL1_MASK 0x000000F0L 372095c1f7aaSFeifei Xu #define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL2_MASK 0x00000F00L 372195c1f7aaSFeifei Xu #define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL3_MASK 0x0000F000L 372295c1f7aaSFeifei Xu #define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL4_MASK 0x000F0000L 372395c1f7aaSFeifei Xu #define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL5_MASK 0x00F00000L 372495c1f7aaSFeifei Xu #define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL6_MASK 0x0F000000L 372595c1f7aaSFeifei Xu #define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL7_MASK 0xF0000000L 372695c1f7aaSFeifei Xu //MMEA0_ADDRDEC1_COL_SEL_HI_CS01 372795c1f7aaSFeifei Xu #define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL8__SHIFT 0x0 372895c1f7aaSFeifei Xu #define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL9__SHIFT 0x4 372995c1f7aaSFeifei Xu #define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL10__SHIFT 0x8 373095c1f7aaSFeifei Xu #define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL11__SHIFT 0xc 373195c1f7aaSFeifei Xu #define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL12__SHIFT 0x10 373295c1f7aaSFeifei Xu #define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL13__SHIFT 0x14 373395c1f7aaSFeifei Xu #define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL14__SHIFT 0x18 373495c1f7aaSFeifei Xu #define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL15__SHIFT 0x1c 373595c1f7aaSFeifei Xu #define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL8_MASK 0x0000000FL 373695c1f7aaSFeifei Xu #define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL9_MASK 0x000000F0L 373795c1f7aaSFeifei Xu #define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL10_MASK 0x00000F00L 373895c1f7aaSFeifei Xu #define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL11_MASK 0x0000F000L 373995c1f7aaSFeifei Xu #define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL12_MASK 0x000F0000L 374095c1f7aaSFeifei Xu #define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL13_MASK 0x00F00000L 374195c1f7aaSFeifei Xu #define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL14_MASK 0x0F000000L 374295c1f7aaSFeifei Xu #define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL15_MASK 0xF0000000L 374395c1f7aaSFeifei Xu //MMEA0_ADDRDEC1_COL_SEL_HI_CS23 374495c1f7aaSFeifei Xu #define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL8__SHIFT 0x0 374595c1f7aaSFeifei Xu #define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL9__SHIFT 0x4 374695c1f7aaSFeifei Xu #define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL10__SHIFT 0x8 374795c1f7aaSFeifei Xu #define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL11__SHIFT 0xc 374895c1f7aaSFeifei Xu #define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL12__SHIFT 0x10 374995c1f7aaSFeifei Xu #define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL13__SHIFT 0x14 375095c1f7aaSFeifei Xu #define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL14__SHIFT 0x18 375195c1f7aaSFeifei Xu #define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL15__SHIFT 0x1c 375295c1f7aaSFeifei Xu #define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL8_MASK 0x0000000FL 375395c1f7aaSFeifei Xu #define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL9_MASK 0x000000F0L 375495c1f7aaSFeifei Xu #define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL10_MASK 0x00000F00L 375595c1f7aaSFeifei Xu #define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL11_MASK 0x0000F000L 375695c1f7aaSFeifei Xu #define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL12_MASK 0x000F0000L 375795c1f7aaSFeifei Xu #define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL13_MASK 0x00F00000L 375895c1f7aaSFeifei Xu #define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL14_MASK 0x0F000000L 375995c1f7aaSFeifei Xu #define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL15_MASK 0xF0000000L 376095c1f7aaSFeifei Xu //MMEA0_ADDRDEC1_RM_SEL_CS01 376195c1f7aaSFeifei Xu #define MMEA0_ADDRDEC1_RM_SEL_CS01__RM0__SHIFT 0x0 376295c1f7aaSFeifei Xu #define MMEA0_ADDRDEC1_RM_SEL_CS01__RM1__SHIFT 0x4 376395c1f7aaSFeifei Xu #define MMEA0_ADDRDEC1_RM_SEL_CS01__RM2__SHIFT 0x8 376495c1f7aaSFeifei Xu #define MMEA0_ADDRDEC1_RM_SEL_CS01__CHAN_BIT__SHIFT 0xc 376595c1f7aaSFeifei Xu #define MMEA0_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 376695c1f7aaSFeifei Xu #define MMEA0_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12 376795c1f7aaSFeifei Xu #define MMEA0_ADDRDEC1_RM_SEL_CS01__RM0_MASK 0x0000000FL 376895c1f7aaSFeifei Xu #define MMEA0_ADDRDEC1_RM_SEL_CS01__RM1_MASK 0x000000F0L 376995c1f7aaSFeifei Xu #define MMEA0_ADDRDEC1_RM_SEL_CS01__RM2_MASK 0x00000F00L 377095c1f7aaSFeifei Xu #define MMEA0_ADDRDEC1_RM_SEL_CS01__CHAN_BIT_MASK 0x0000F000L 377195c1f7aaSFeifei Xu #define MMEA0_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L 377295c1f7aaSFeifei Xu #define MMEA0_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L 377395c1f7aaSFeifei Xu //MMEA0_ADDRDEC1_RM_SEL_CS23 377495c1f7aaSFeifei Xu #define MMEA0_ADDRDEC1_RM_SEL_CS23__RM0__SHIFT 0x0 377595c1f7aaSFeifei Xu #define MMEA0_ADDRDEC1_RM_SEL_CS23__RM1__SHIFT 0x4 377695c1f7aaSFeifei Xu #define MMEA0_ADDRDEC1_RM_SEL_CS23__RM2__SHIFT 0x8 377795c1f7aaSFeifei Xu #define MMEA0_ADDRDEC1_RM_SEL_CS23__CHAN_BIT__SHIFT 0xc 377895c1f7aaSFeifei Xu #define MMEA0_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 377995c1f7aaSFeifei Xu #define MMEA0_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12 378095c1f7aaSFeifei Xu #define MMEA0_ADDRDEC1_RM_SEL_CS23__RM0_MASK 0x0000000FL 378195c1f7aaSFeifei Xu #define MMEA0_ADDRDEC1_RM_SEL_CS23__RM1_MASK 0x000000F0L 378295c1f7aaSFeifei Xu #define MMEA0_ADDRDEC1_RM_SEL_CS23__RM2_MASK 0x00000F00L 378395c1f7aaSFeifei Xu #define MMEA0_ADDRDEC1_RM_SEL_CS23__CHAN_BIT_MASK 0x0000F000L 378495c1f7aaSFeifei Xu #define MMEA0_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L 378595c1f7aaSFeifei Xu #define MMEA0_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L 378695c1f7aaSFeifei Xu //MMEA0_ADDRDEC1_RM_SEL_SECCS01 378795c1f7aaSFeifei Xu #define MMEA0_ADDRDEC1_RM_SEL_SECCS01__RM0__SHIFT 0x0 378895c1f7aaSFeifei Xu #define MMEA0_ADDRDEC1_RM_SEL_SECCS01__RM1__SHIFT 0x4 378995c1f7aaSFeifei Xu #define MMEA0_ADDRDEC1_RM_SEL_SECCS01__RM2__SHIFT 0x8 379095c1f7aaSFeifei Xu #define MMEA0_ADDRDEC1_RM_SEL_SECCS01__CHAN_BIT__SHIFT 0xc 379195c1f7aaSFeifei Xu #define MMEA0_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 379295c1f7aaSFeifei Xu #define MMEA0_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12 379395c1f7aaSFeifei Xu #define MMEA0_ADDRDEC1_RM_SEL_SECCS01__RM0_MASK 0x0000000FL 379495c1f7aaSFeifei Xu #define MMEA0_ADDRDEC1_RM_SEL_SECCS01__RM1_MASK 0x000000F0L 379595c1f7aaSFeifei Xu #define MMEA0_ADDRDEC1_RM_SEL_SECCS01__RM2_MASK 0x00000F00L 379695c1f7aaSFeifei Xu #define MMEA0_ADDRDEC1_RM_SEL_SECCS01__CHAN_BIT_MASK 0x0000F000L 379795c1f7aaSFeifei Xu #define MMEA0_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L 379895c1f7aaSFeifei Xu #define MMEA0_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L 379995c1f7aaSFeifei Xu //MMEA0_ADDRDEC1_RM_SEL_SECCS23 380095c1f7aaSFeifei Xu #define MMEA0_ADDRDEC1_RM_SEL_SECCS23__RM0__SHIFT 0x0 380195c1f7aaSFeifei Xu #define MMEA0_ADDRDEC1_RM_SEL_SECCS23__RM1__SHIFT 0x4 380295c1f7aaSFeifei Xu #define MMEA0_ADDRDEC1_RM_SEL_SECCS23__RM2__SHIFT 0x8 380395c1f7aaSFeifei Xu #define MMEA0_ADDRDEC1_RM_SEL_SECCS23__CHAN_BIT__SHIFT 0xc 380495c1f7aaSFeifei Xu #define MMEA0_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 380595c1f7aaSFeifei Xu #define MMEA0_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12 380695c1f7aaSFeifei Xu #define MMEA0_ADDRDEC1_RM_SEL_SECCS23__RM0_MASK 0x0000000FL 380795c1f7aaSFeifei Xu #define MMEA0_ADDRDEC1_RM_SEL_SECCS23__RM1_MASK 0x000000F0L 380895c1f7aaSFeifei Xu #define MMEA0_ADDRDEC1_RM_SEL_SECCS23__RM2_MASK 0x00000F00L 380995c1f7aaSFeifei Xu #define MMEA0_ADDRDEC1_RM_SEL_SECCS23__CHAN_BIT_MASK 0x0000F000L 381095c1f7aaSFeifei Xu #define MMEA0_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L 381195c1f7aaSFeifei Xu #define MMEA0_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L 381295c1f7aaSFeifei Xu //MMEA0_IO_RD_CLI2GRP_MAP0 381395c1f7aaSFeifei Xu #define MMEA0_IO_RD_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 381495c1f7aaSFeifei Xu #define MMEA0_IO_RD_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 381595c1f7aaSFeifei Xu #define MMEA0_IO_RD_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 381695c1f7aaSFeifei Xu #define MMEA0_IO_RD_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 381795c1f7aaSFeifei Xu #define MMEA0_IO_RD_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 381895c1f7aaSFeifei Xu #define MMEA0_IO_RD_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa 381995c1f7aaSFeifei Xu #define MMEA0_IO_RD_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc 382095c1f7aaSFeifei Xu #define MMEA0_IO_RD_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe 382195c1f7aaSFeifei Xu #define MMEA0_IO_RD_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 382295c1f7aaSFeifei Xu #define MMEA0_IO_RD_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 382395c1f7aaSFeifei Xu #define MMEA0_IO_RD_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 382495c1f7aaSFeifei Xu #define MMEA0_IO_RD_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 382595c1f7aaSFeifei Xu #define MMEA0_IO_RD_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 382695c1f7aaSFeifei Xu #define MMEA0_IO_RD_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a 382795c1f7aaSFeifei Xu #define MMEA0_IO_RD_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c 382895c1f7aaSFeifei Xu #define MMEA0_IO_RD_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e 382995c1f7aaSFeifei Xu #define MMEA0_IO_RD_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L 383095c1f7aaSFeifei Xu #define MMEA0_IO_RD_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL 383195c1f7aaSFeifei Xu #define MMEA0_IO_RD_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L 383295c1f7aaSFeifei Xu #define MMEA0_IO_RD_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L 383395c1f7aaSFeifei Xu #define MMEA0_IO_RD_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L 383495c1f7aaSFeifei Xu #define MMEA0_IO_RD_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L 383595c1f7aaSFeifei Xu #define MMEA0_IO_RD_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L 383695c1f7aaSFeifei Xu #define MMEA0_IO_RD_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L 383795c1f7aaSFeifei Xu #define MMEA0_IO_RD_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L 383895c1f7aaSFeifei Xu #define MMEA0_IO_RD_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L 383995c1f7aaSFeifei Xu #define MMEA0_IO_RD_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L 384095c1f7aaSFeifei Xu #define MMEA0_IO_RD_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L 384195c1f7aaSFeifei Xu #define MMEA0_IO_RD_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L 384295c1f7aaSFeifei Xu #define MMEA0_IO_RD_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L 384395c1f7aaSFeifei Xu #define MMEA0_IO_RD_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L 384495c1f7aaSFeifei Xu #define MMEA0_IO_RD_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L 384595c1f7aaSFeifei Xu //MMEA0_IO_RD_CLI2GRP_MAP1 384695c1f7aaSFeifei Xu #define MMEA0_IO_RD_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 384795c1f7aaSFeifei Xu #define MMEA0_IO_RD_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 384895c1f7aaSFeifei Xu #define MMEA0_IO_RD_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 384995c1f7aaSFeifei Xu #define MMEA0_IO_RD_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 385095c1f7aaSFeifei Xu #define MMEA0_IO_RD_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 385195c1f7aaSFeifei Xu #define MMEA0_IO_RD_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa 385295c1f7aaSFeifei Xu #define MMEA0_IO_RD_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc 385395c1f7aaSFeifei Xu #define MMEA0_IO_RD_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe 385495c1f7aaSFeifei Xu #define MMEA0_IO_RD_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 385595c1f7aaSFeifei Xu #define MMEA0_IO_RD_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 385695c1f7aaSFeifei Xu #define MMEA0_IO_RD_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 385795c1f7aaSFeifei Xu #define MMEA0_IO_RD_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 385895c1f7aaSFeifei Xu #define MMEA0_IO_RD_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 385995c1f7aaSFeifei Xu #define MMEA0_IO_RD_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a 386095c1f7aaSFeifei Xu #define MMEA0_IO_RD_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c 386195c1f7aaSFeifei Xu #define MMEA0_IO_RD_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e 386295c1f7aaSFeifei Xu #define MMEA0_IO_RD_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L 386395c1f7aaSFeifei Xu #define MMEA0_IO_RD_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL 386495c1f7aaSFeifei Xu #define MMEA0_IO_RD_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L 386595c1f7aaSFeifei Xu #define MMEA0_IO_RD_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L 386695c1f7aaSFeifei Xu #define MMEA0_IO_RD_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L 386795c1f7aaSFeifei Xu #define MMEA0_IO_RD_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L 386895c1f7aaSFeifei Xu #define MMEA0_IO_RD_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L 386995c1f7aaSFeifei Xu #define MMEA0_IO_RD_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L 387095c1f7aaSFeifei Xu #define MMEA0_IO_RD_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L 387195c1f7aaSFeifei Xu #define MMEA0_IO_RD_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L 387295c1f7aaSFeifei Xu #define MMEA0_IO_RD_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L 387395c1f7aaSFeifei Xu #define MMEA0_IO_RD_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L 387495c1f7aaSFeifei Xu #define MMEA0_IO_RD_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L 387595c1f7aaSFeifei Xu #define MMEA0_IO_RD_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L 387695c1f7aaSFeifei Xu #define MMEA0_IO_RD_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L 387795c1f7aaSFeifei Xu #define MMEA0_IO_RD_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L 387895c1f7aaSFeifei Xu //MMEA0_IO_WR_CLI2GRP_MAP0 387995c1f7aaSFeifei Xu #define MMEA0_IO_WR_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 388095c1f7aaSFeifei Xu #define MMEA0_IO_WR_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 388195c1f7aaSFeifei Xu #define MMEA0_IO_WR_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 388295c1f7aaSFeifei Xu #define MMEA0_IO_WR_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 388395c1f7aaSFeifei Xu #define MMEA0_IO_WR_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 388495c1f7aaSFeifei Xu #define MMEA0_IO_WR_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa 388595c1f7aaSFeifei Xu #define MMEA0_IO_WR_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc 388695c1f7aaSFeifei Xu #define MMEA0_IO_WR_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe 388795c1f7aaSFeifei Xu #define MMEA0_IO_WR_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 388895c1f7aaSFeifei Xu #define MMEA0_IO_WR_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 388995c1f7aaSFeifei Xu #define MMEA0_IO_WR_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 389095c1f7aaSFeifei Xu #define MMEA0_IO_WR_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 389195c1f7aaSFeifei Xu #define MMEA0_IO_WR_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 389295c1f7aaSFeifei Xu #define MMEA0_IO_WR_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a 389395c1f7aaSFeifei Xu #define MMEA0_IO_WR_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c 389495c1f7aaSFeifei Xu #define MMEA0_IO_WR_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e 389595c1f7aaSFeifei Xu #define MMEA0_IO_WR_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L 389695c1f7aaSFeifei Xu #define MMEA0_IO_WR_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL 389795c1f7aaSFeifei Xu #define MMEA0_IO_WR_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L 389895c1f7aaSFeifei Xu #define MMEA0_IO_WR_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L 389995c1f7aaSFeifei Xu #define MMEA0_IO_WR_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L 390095c1f7aaSFeifei Xu #define MMEA0_IO_WR_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L 390195c1f7aaSFeifei Xu #define MMEA0_IO_WR_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L 390295c1f7aaSFeifei Xu #define MMEA0_IO_WR_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L 390395c1f7aaSFeifei Xu #define MMEA0_IO_WR_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L 390495c1f7aaSFeifei Xu #define MMEA0_IO_WR_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L 390595c1f7aaSFeifei Xu #define MMEA0_IO_WR_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L 390695c1f7aaSFeifei Xu #define MMEA0_IO_WR_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L 390795c1f7aaSFeifei Xu #define MMEA0_IO_WR_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L 390895c1f7aaSFeifei Xu #define MMEA0_IO_WR_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L 390995c1f7aaSFeifei Xu #define MMEA0_IO_WR_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L 391095c1f7aaSFeifei Xu #define MMEA0_IO_WR_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L 391195c1f7aaSFeifei Xu //MMEA0_IO_WR_CLI2GRP_MAP1 391295c1f7aaSFeifei Xu #define MMEA0_IO_WR_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 391395c1f7aaSFeifei Xu #define MMEA0_IO_WR_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 391495c1f7aaSFeifei Xu #define MMEA0_IO_WR_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 391595c1f7aaSFeifei Xu #define MMEA0_IO_WR_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 391695c1f7aaSFeifei Xu #define MMEA0_IO_WR_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 391795c1f7aaSFeifei Xu #define MMEA0_IO_WR_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa 391895c1f7aaSFeifei Xu #define MMEA0_IO_WR_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc 391995c1f7aaSFeifei Xu #define MMEA0_IO_WR_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe 392095c1f7aaSFeifei Xu #define MMEA0_IO_WR_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 392195c1f7aaSFeifei Xu #define MMEA0_IO_WR_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 392295c1f7aaSFeifei Xu #define MMEA0_IO_WR_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 392395c1f7aaSFeifei Xu #define MMEA0_IO_WR_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 392495c1f7aaSFeifei Xu #define MMEA0_IO_WR_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 392595c1f7aaSFeifei Xu #define MMEA0_IO_WR_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a 392695c1f7aaSFeifei Xu #define MMEA0_IO_WR_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c 392795c1f7aaSFeifei Xu #define MMEA0_IO_WR_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e 392895c1f7aaSFeifei Xu #define MMEA0_IO_WR_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L 392995c1f7aaSFeifei Xu #define MMEA0_IO_WR_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL 393095c1f7aaSFeifei Xu #define MMEA0_IO_WR_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L 393195c1f7aaSFeifei Xu #define MMEA0_IO_WR_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L 393295c1f7aaSFeifei Xu #define MMEA0_IO_WR_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L 393395c1f7aaSFeifei Xu #define MMEA0_IO_WR_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L 393495c1f7aaSFeifei Xu #define MMEA0_IO_WR_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L 393595c1f7aaSFeifei Xu #define MMEA0_IO_WR_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L 393695c1f7aaSFeifei Xu #define MMEA0_IO_WR_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L 393795c1f7aaSFeifei Xu #define MMEA0_IO_WR_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L 393895c1f7aaSFeifei Xu #define MMEA0_IO_WR_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L 393995c1f7aaSFeifei Xu #define MMEA0_IO_WR_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L 394095c1f7aaSFeifei Xu #define MMEA0_IO_WR_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L 394195c1f7aaSFeifei Xu #define MMEA0_IO_WR_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L 394295c1f7aaSFeifei Xu #define MMEA0_IO_WR_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L 394395c1f7aaSFeifei Xu #define MMEA0_IO_WR_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L 394495c1f7aaSFeifei Xu //MMEA0_IO_RD_COMBINE_FLUSH 394595c1f7aaSFeifei Xu #define MMEA0_IO_RD_COMBINE_FLUSH__GROUP0_TIMER__SHIFT 0x0 394695c1f7aaSFeifei Xu #define MMEA0_IO_RD_COMBINE_FLUSH__GROUP1_TIMER__SHIFT 0x4 394795c1f7aaSFeifei Xu #define MMEA0_IO_RD_COMBINE_FLUSH__GROUP2_TIMER__SHIFT 0x8 394895c1f7aaSFeifei Xu #define MMEA0_IO_RD_COMBINE_FLUSH__GROUP3_TIMER__SHIFT 0xc 394995c1f7aaSFeifei Xu #define MMEA0_IO_RD_COMBINE_FLUSH__GROUP0_TIMER_MASK 0x0000000FL 395095c1f7aaSFeifei Xu #define MMEA0_IO_RD_COMBINE_FLUSH__GROUP1_TIMER_MASK 0x000000F0L 395195c1f7aaSFeifei Xu #define MMEA0_IO_RD_COMBINE_FLUSH__GROUP2_TIMER_MASK 0x00000F00L 395295c1f7aaSFeifei Xu #define MMEA0_IO_RD_COMBINE_FLUSH__GROUP3_TIMER_MASK 0x0000F000L 395395c1f7aaSFeifei Xu //MMEA0_IO_WR_COMBINE_FLUSH 395495c1f7aaSFeifei Xu #define MMEA0_IO_WR_COMBINE_FLUSH__GROUP0_TIMER__SHIFT 0x0 395595c1f7aaSFeifei Xu #define MMEA0_IO_WR_COMBINE_FLUSH__GROUP1_TIMER__SHIFT 0x4 395695c1f7aaSFeifei Xu #define MMEA0_IO_WR_COMBINE_FLUSH__GROUP2_TIMER__SHIFT 0x8 395795c1f7aaSFeifei Xu #define MMEA0_IO_WR_COMBINE_FLUSH__GROUP3_TIMER__SHIFT 0xc 395895c1f7aaSFeifei Xu #define MMEA0_IO_WR_COMBINE_FLUSH__GROUP0_TIMER_MASK 0x0000000FL 395995c1f7aaSFeifei Xu #define MMEA0_IO_WR_COMBINE_FLUSH__GROUP1_TIMER_MASK 0x000000F0L 396095c1f7aaSFeifei Xu #define MMEA0_IO_WR_COMBINE_FLUSH__GROUP2_TIMER_MASK 0x00000F00L 396195c1f7aaSFeifei Xu #define MMEA0_IO_WR_COMBINE_FLUSH__GROUP3_TIMER_MASK 0x0000F000L 396295c1f7aaSFeifei Xu //MMEA0_IO_GROUP_BURST 396395c1f7aaSFeifei Xu #define MMEA0_IO_GROUP_BURST__RD_LIMIT_LO__SHIFT 0x0 396495c1f7aaSFeifei Xu #define MMEA0_IO_GROUP_BURST__RD_LIMIT_HI__SHIFT 0x8 396595c1f7aaSFeifei Xu #define MMEA0_IO_GROUP_BURST__WR_LIMIT_LO__SHIFT 0x10 396695c1f7aaSFeifei Xu #define MMEA0_IO_GROUP_BURST__WR_LIMIT_HI__SHIFT 0x18 396795c1f7aaSFeifei Xu #define MMEA0_IO_GROUP_BURST__RD_LIMIT_LO_MASK 0x000000FFL 396895c1f7aaSFeifei Xu #define MMEA0_IO_GROUP_BURST__RD_LIMIT_HI_MASK 0x0000FF00L 396995c1f7aaSFeifei Xu #define MMEA0_IO_GROUP_BURST__WR_LIMIT_LO_MASK 0x00FF0000L 397095c1f7aaSFeifei Xu #define MMEA0_IO_GROUP_BURST__WR_LIMIT_HI_MASK 0xFF000000L 397195c1f7aaSFeifei Xu //MMEA0_IO_RD_PRI_AGE 397295c1f7aaSFeifei Xu #define MMEA0_IO_RD_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 397395c1f7aaSFeifei Xu #define MMEA0_IO_RD_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 397495c1f7aaSFeifei Xu #define MMEA0_IO_RD_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 397595c1f7aaSFeifei Xu #define MMEA0_IO_RD_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 397695c1f7aaSFeifei Xu #define MMEA0_IO_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc 397795c1f7aaSFeifei Xu #define MMEA0_IO_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf 397895c1f7aaSFeifei Xu #define MMEA0_IO_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 397995c1f7aaSFeifei Xu #define MMEA0_IO_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 398095c1f7aaSFeifei Xu #define MMEA0_IO_RD_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L 398195c1f7aaSFeifei Xu #define MMEA0_IO_RD_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L 398295c1f7aaSFeifei Xu #define MMEA0_IO_RD_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L 398395c1f7aaSFeifei Xu #define MMEA0_IO_RD_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L 398495c1f7aaSFeifei Xu #define MMEA0_IO_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L 398595c1f7aaSFeifei Xu #define MMEA0_IO_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L 398695c1f7aaSFeifei Xu #define MMEA0_IO_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L 398795c1f7aaSFeifei Xu #define MMEA0_IO_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L 398895c1f7aaSFeifei Xu //MMEA0_IO_WR_PRI_AGE 398995c1f7aaSFeifei Xu #define MMEA0_IO_WR_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 399095c1f7aaSFeifei Xu #define MMEA0_IO_WR_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 399195c1f7aaSFeifei Xu #define MMEA0_IO_WR_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 399295c1f7aaSFeifei Xu #define MMEA0_IO_WR_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 399395c1f7aaSFeifei Xu #define MMEA0_IO_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc 399495c1f7aaSFeifei Xu #define MMEA0_IO_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf 399595c1f7aaSFeifei Xu #define MMEA0_IO_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 399695c1f7aaSFeifei Xu #define MMEA0_IO_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 399795c1f7aaSFeifei Xu #define MMEA0_IO_WR_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L 399895c1f7aaSFeifei Xu #define MMEA0_IO_WR_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L 399995c1f7aaSFeifei Xu #define MMEA0_IO_WR_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L 400095c1f7aaSFeifei Xu #define MMEA0_IO_WR_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L 400195c1f7aaSFeifei Xu #define MMEA0_IO_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L 400295c1f7aaSFeifei Xu #define MMEA0_IO_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L 400395c1f7aaSFeifei Xu #define MMEA0_IO_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L 400495c1f7aaSFeifei Xu #define MMEA0_IO_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L 400595c1f7aaSFeifei Xu //MMEA0_IO_RD_PRI_QUEUING 400695c1f7aaSFeifei Xu #define MMEA0_IO_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 400795c1f7aaSFeifei Xu #define MMEA0_IO_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 400895c1f7aaSFeifei Xu #define MMEA0_IO_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 400995c1f7aaSFeifei Xu #define MMEA0_IO_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 401095c1f7aaSFeifei Xu #define MMEA0_IO_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L 401195c1f7aaSFeifei Xu #define MMEA0_IO_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L 401295c1f7aaSFeifei Xu #define MMEA0_IO_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L 401395c1f7aaSFeifei Xu #define MMEA0_IO_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L 401495c1f7aaSFeifei Xu //MMEA0_IO_WR_PRI_QUEUING 401595c1f7aaSFeifei Xu #define MMEA0_IO_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 401695c1f7aaSFeifei Xu #define MMEA0_IO_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 401795c1f7aaSFeifei Xu #define MMEA0_IO_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 401895c1f7aaSFeifei Xu #define MMEA0_IO_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 401995c1f7aaSFeifei Xu #define MMEA0_IO_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L 402095c1f7aaSFeifei Xu #define MMEA0_IO_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L 402195c1f7aaSFeifei Xu #define MMEA0_IO_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L 402295c1f7aaSFeifei Xu #define MMEA0_IO_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L 402395c1f7aaSFeifei Xu //MMEA0_IO_RD_PRI_FIXED 402495c1f7aaSFeifei Xu #define MMEA0_IO_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 402595c1f7aaSFeifei Xu #define MMEA0_IO_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 402695c1f7aaSFeifei Xu #define MMEA0_IO_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 402795c1f7aaSFeifei Xu #define MMEA0_IO_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 402895c1f7aaSFeifei Xu #define MMEA0_IO_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L 402995c1f7aaSFeifei Xu #define MMEA0_IO_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L 403095c1f7aaSFeifei Xu #define MMEA0_IO_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L 403195c1f7aaSFeifei Xu #define MMEA0_IO_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L 403295c1f7aaSFeifei Xu //MMEA0_IO_WR_PRI_FIXED 403395c1f7aaSFeifei Xu #define MMEA0_IO_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 403495c1f7aaSFeifei Xu #define MMEA0_IO_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 403595c1f7aaSFeifei Xu #define MMEA0_IO_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 403695c1f7aaSFeifei Xu #define MMEA0_IO_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 403795c1f7aaSFeifei Xu #define MMEA0_IO_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L 403895c1f7aaSFeifei Xu #define MMEA0_IO_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L 403995c1f7aaSFeifei Xu #define MMEA0_IO_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L 404095c1f7aaSFeifei Xu #define MMEA0_IO_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L 404195c1f7aaSFeifei Xu //MMEA0_IO_RD_PRI_URGENCY 404295c1f7aaSFeifei Xu #define MMEA0_IO_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 404395c1f7aaSFeifei Xu #define MMEA0_IO_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 404495c1f7aaSFeifei Xu #define MMEA0_IO_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 404595c1f7aaSFeifei Xu #define MMEA0_IO_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 404695c1f7aaSFeifei Xu #define MMEA0_IO_RD_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc 404795c1f7aaSFeifei Xu #define MMEA0_IO_RD_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd 404895c1f7aaSFeifei Xu #define MMEA0_IO_RD_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe 404995c1f7aaSFeifei Xu #define MMEA0_IO_RD_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf 405095c1f7aaSFeifei Xu #define MMEA0_IO_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L 405195c1f7aaSFeifei Xu #define MMEA0_IO_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L 405295c1f7aaSFeifei Xu #define MMEA0_IO_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L 405395c1f7aaSFeifei Xu #define MMEA0_IO_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L 405495c1f7aaSFeifei Xu #define MMEA0_IO_RD_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L 405595c1f7aaSFeifei Xu #define MMEA0_IO_RD_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L 405695c1f7aaSFeifei Xu #define MMEA0_IO_RD_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L 405795c1f7aaSFeifei Xu #define MMEA0_IO_RD_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L 405895c1f7aaSFeifei Xu //MMEA0_IO_WR_PRI_URGENCY 405995c1f7aaSFeifei Xu #define MMEA0_IO_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 406095c1f7aaSFeifei Xu #define MMEA0_IO_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 406195c1f7aaSFeifei Xu #define MMEA0_IO_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 406295c1f7aaSFeifei Xu #define MMEA0_IO_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 406395c1f7aaSFeifei Xu #define MMEA0_IO_WR_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc 406495c1f7aaSFeifei Xu #define MMEA0_IO_WR_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd 406595c1f7aaSFeifei Xu #define MMEA0_IO_WR_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe 406695c1f7aaSFeifei Xu #define MMEA0_IO_WR_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf 406795c1f7aaSFeifei Xu #define MMEA0_IO_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L 406895c1f7aaSFeifei Xu #define MMEA0_IO_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L 406995c1f7aaSFeifei Xu #define MMEA0_IO_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L 407095c1f7aaSFeifei Xu #define MMEA0_IO_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L 407195c1f7aaSFeifei Xu #define MMEA0_IO_WR_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L 407295c1f7aaSFeifei Xu #define MMEA0_IO_WR_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L 407395c1f7aaSFeifei Xu #define MMEA0_IO_WR_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L 407495c1f7aaSFeifei Xu #define MMEA0_IO_WR_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L 407595c1f7aaSFeifei Xu //MMEA0_IO_RD_PRI_URGENCY_MASK 407695c1f7aaSFeifei Xu #define MMEA0_IO_RD_PRI_URGENCY_MASK__CID0_MASK__SHIFT 0x0 407795c1f7aaSFeifei Xu #define MMEA0_IO_RD_PRI_URGENCY_MASK__CID1_MASK__SHIFT 0x1 407895c1f7aaSFeifei Xu #define MMEA0_IO_RD_PRI_URGENCY_MASK__CID2_MASK__SHIFT 0x2 407995c1f7aaSFeifei Xu #define MMEA0_IO_RD_PRI_URGENCY_MASK__CID3_MASK__SHIFT 0x3 408095c1f7aaSFeifei Xu #define MMEA0_IO_RD_PRI_URGENCY_MASK__CID4_MASK__SHIFT 0x4 408195c1f7aaSFeifei Xu #define MMEA0_IO_RD_PRI_URGENCY_MASK__CID5_MASK__SHIFT 0x5 408295c1f7aaSFeifei Xu #define MMEA0_IO_RD_PRI_URGENCY_MASK__CID6_MASK__SHIFT 0x6 408395c1f7aaSFeifei Xu #define MMEA0_IO_RD_PRI_URGENCY_MASK__CID7_MASK__SHIFT 0x7 408495c1f7aaSFeifei Xu #define MMEA0_IO_RD_PRI_URGENCY_MASK__CID8_MASK__SHIFT 0x8 408595c1f7aaSFeifei Xu #define MMEA0_IO_RD_PRI_URGENCY_MASK__CID9_MASK__SHIFT 0x9 408695c1f7aaSFeifei Xu #define MMEA0_IO_RD_PRI_URGENCY_MASK__CID10_MASK__SHIFT 0xa 408795c1f7aaSFeifei Xu #define MMEA0_IO_RD_PRI_URGENCY_MASK__CID11_MASK__SHIFT 0xb 408895c1f7aaSFeifei Xu #define MMEA0_IO_RD_PRI_URGENCY_MASK__CID12_MASK__SHIFT 0xc 408995c1f7aaSFeifei Xu #define MMEA0_IO_RD_PRI_URGENCY_MASK__CID13_MASK__SHIFT 0xd 409095c1f7aaSFeifei Xu #define MMEA0_IO_RD_PRI_URGENCY_MASK__CID14_MASK__SHIFT 0xe 409195c1f7aaSFeifei Xu #define MMEA0_IO_RD_PRI_URGENCY_MASK__CID15_MASK__SHIFT 0xf 409295c1f7aaSFeifei Xu #define MMEA0_IO_RD_PRI_URGENCY_MASK__CID16_MASK__SHIFT 0x10 409395c1f7aaSFeifei Xu #define MMEA0_IO_RD_PRI_URGENCY_MASK__CID17_MASK__SHIFT 0x11 409495c1f7aaSFeifei Xu #define MMEA0_IO_RD_PRI_URGENCY_MASK__CID18_MASK__SHIFT 0x12 409595c1f7aaSFeifei Xu #define MMEA0_IO_RD_PRI_URGENCY_MASK__CID19_MASK__SHIFT 0x13 409695c1f7aaSFeifei Xu #define MMEA0_IO_RD_PRI_URGENCY_MASK__CID20_MASK__SHIFT 0x14 409795c1f7aaSFeifei Xu #define MMEA0_IO_RD_PRI_URGENCY_MASK__CID21_MASK__SHIFT 0x15 409895c1f7aaSFeifei Xu #define MMEA0_IO_RD_PRI_URGENCY_MASK__CID22_MASK__SHIFT 0x16 409995c1f7aaSFeifei Xu #define MMEA0_IO_RD_PRI_URGENCY_MASK__CID23_MASK__SHIFT 0x17 410095c1f7aaSFeifei Xu #define MMEA0_IO_RD_PRI_URGENCY_MASK__CID24_MASK__SHIFT 0x18 410195c1f7aaSFeifei Xu #define MMEA0_IO_RD_PRI_URGENCY_MASK__CID25_MASK__SHIFT 0x19 410295c1f7aaSFeifei Xu #define MMEA0_IO_RD_PRI_URGENCY_MASK__CID26_MASK__SHIFT 0x1a 410395c1f7aaSFeifei Xu #define MMEA0_IO_RD_PRI_URGENCY_MASK__CID27_MASK__SHIFT 0x1b 410495c1f7aaSFeifei Xu #define MMEA0_IO_RD_PRI_URGENCY_MASK__CID28_MASK__SHIFT 0x1c 410595c1f7aaSFeifei Xu #define MMEA0_IO_RD_PRI_URGENCY_MASK__CID29_MASK__SHIFT 0x1d 410695c1f7aaSFeifei Xu #define MMEA0_IO_RD_PRI_URGENCY_MASK__CID30_MASK__SHIFT 0x1e 410795c1f7aaSFeifei Xu #define MMEA0_IO_RD_PRI_URGENCY_MASK__CID31_MASK__SHIFT 0x1f 410895c1f7aaSFeifei Xu #define MMEA0_IO_RD_PRI_URGENCY_MASK__CID0_MASK_MASK 0x00000001L 410995c1f7aaSFeifei Xu #define MMEA0_IO_RD_PRI_URGENCY_MASK__CID1_MASK_MASK 0x00000002L 411095c1f7aaSFeifei Xu #define MMEA0_IO_RD_PRI_URGENCY_MASK__CID2_MASK_MASK 0x00000004L 411195c1f7aaSFeifei Xu #define MMEA0_IO_RD_PRI_URGENCY_MASK__CID3_MASK_MASK 0x00000008L 411295c1f7aaSFeifei Xu #define MMEA0_IO_RD_PRI_URGENCY_MASK__CID4_MASK_MASK 0x00000010L 411395c1f7aaSFeifei Xu #define MMEA0_IO_RD_PRI_URGENCY_MASK__CID5_MASK_MASK 0x00000020L 411495c1f7aaSFeifei Xu #define MMEA0_IO_RD_PRI_URGENCY_MASK__CID6_MASK_MASK 0x00000040L 411595c1f7aaSFeifei Xu #define MMEA0_IO_RD_PRI_URGENCY_MASK__CID7_MASK_MASK 0x00000080L 411695c1f7aaSFeifei Xu #define MMEA0_IO_RD_PRI_URGENCY_MASK__CID8_MASK_MASK 0x00000100L 411795c1f7aaSFeifei Xu #define MMEA0_IO_RD_PRI_URGENCY_MASK__CID9_MASK_MASK 0x00000200L 411895c1f7aaSFeifei Xu #define MMEA0_IO_RD_PRI_URGENCY_MASK__CID10_MASK_MASK 0x00000400L 411995c1f7aaSFeifei Xu #define MMEA0_IO_RD_PRI_URGENCY_MASK__CID11_MASK_MASK 0x00000800L 412095c1f7aaSFeifei Xu #define MMEA0_IO_RD_PRI_URGENCY_MASK__CID12_MASK_MASK 0x00001000L 412195c1f7aaSFeifei Xu #define MMEA0_IO_RD_PRI_URGENCY_MASK__CID13_MASK_MASK 0x00002000L 412295c1f7aaSFeifei Xu #define MMEA0_IO_RD_PRI_URGENCY_MASK__CID14_MASK_MASK 0x00004000L 412395c1f7aaSFeifei Xu #define MMEA0_IO_RD_PRI_URGENCY_MASK__CID15_MASK_MASK 0x00008000L 412495c1f7aaSFeifei Xu #define MMEA0_IO_RD_PRI_URGENCY_MASK__CID16_MASK_MASK 0x00010000L 412595c1f7aaSFeifei Xu #define MMEA0_IO_RD_PRI_URGENCY_MASK__CID17_MASK_MASK 0x00020000L 412695c1f7aaSFeifei Xu #define MMEA0_IO_RD_PRI_URGENCY_MASK__CID18_MASK_MASK 0x00040000L 412795c1f7aaSFeifei Xu #define MMEA0_IO_RD_PRI_URGENCY_MASK__CID19_MASK_MASK 0x00080000L 412895c1f7aaSFeifei Xu #define MMEA0_IO_RD_PRI_URGENCY_MASK__CID20_MASK_MASK 0x00100000L 412995c1f7aaSFeifei Xu #define MMEA0_IO_RD_PRI_URGENCY_MASK__CID21_MASK_MASK 0x00200000L 413095c1f7aaSFeifei Xu #define MMEA0_IO_RD_PRI_URGENCY_MASK__CID22_MASK_MASK 0x00400000L 413195c1f7aaSFeifei Xu #define MMEA0_IO_RD_PRI_URGENCY_MASK__CID23_MASK_MASK 0x00800000L 413295c1f7aaSFeifei Xu #define MMEA0_IO_RD_PRI_URGENCY_MASK__CID24_MASK_MASK 0x01000000L 413395c1f7aaSFeifei Xu #define MMEA0_IO_RD_PRI_URGENCY_MASK__CID25_MASK_MASK 0x02000000L 413495c1f7aaSFeifei Xu #define MMEA0_IO_RD_PRI_URGENCY_MASK__CID26_MASK_MASK 0x04000000L 413595c1f7aaSFeifei Xu #define MMEA0_IO_RD_PRI_URGENCY_MASK__CID27_MASK_MASK 0x08000000L 413695c1f7aaSFeifei Xu #define MMEA0_IO_RD_PRI_URGENCY_MASK__CID28_MASK_MASK 0x10000000L 413795c1f7aaSFeifei Xu #define MMEA0_IO_RD_PRI_URGENCY_MASK__CID29_MASK_MASK 0x20000000L 413895c1f7aaSFeifei Xu #define MMEA0_IO_RD_PRI_URGENCY_MASK__CID30_MASK_MASK 0x40000000L 413995c1f7aaSFeifei Xu #define MMEA0_IO_RD_PRI_URGENCY_MASK__CID31_MASK_MASK 0x80000000L 414095c1f7aaSFeifei Xu //MMEA0_IO_WR_PRI_URGENCY_MASK 414195c1f7aaSFeifei Xu #define MMEA0_IO_WR_PRI_URGENCY_MASK__CID0_MASK__SHIFT 0x0 414295c1f7aaSFeifei Xu #define MMEA0_IO_WR_PRI_URGENCY_MASK__CID1_MASK__SHIFT 0x1 414395c1f7aaSFeifei Xu #define MMEA0_IO_WR_PRI_URGENCY_MASK__CID2_MASK__SHIFT 0x2 414495c1f7aaSFeifei Xu #define MMEA0_IO_WR_PRI_URGENCY_MASK__CID3_MASK__SHIFT 0x3 414595c1f7aaSFeifei Xu #define MMEA0_IO_WR_PRI_URGENCY_MASK__CID4_MASK__SHIFT 0x4 414695c1f7aaSFeifei Xu #define MMEA0_IO_WR_PRI_URGENCY_MASK__CID5_MASK__SHIFT 0x5 414795c1f7aaSFeifei Xu #define MMEA0_IO_WR_PRI_URGENCY_MASK__CID6_MASK__SHIFT 0x6 414895c1f7aaSFeifei Xu #define MMEA0_IO_WR_PRI_URGENCY_MASK__CID7_MASK__SHIFT 0x7 414995c1f7aaSFeifei Xu #define MMEA0_IO_WR_PRI_URGENCY_MASK__CID8_MASK__SHIFT 0x8 415095c1f7aaSFeifei Xu #define MMEA0_IO_WR_PRI_URGENCY_MASK__CID9_MASK__SHIFT 0x9 415195c1f7aaSFeifei Xu #define MMEA0_IO_WR_PRI_URGENCY_MASK__CID10_MASK__SHIFT 0xa 415295c1f7aaSFeifei Xu #define MMEA0_IO_WR_PRI_URGENCY_MASK__CID11_MASK__SHIFT 0xb 415395c1f7aaSFeifei Xu #define MMEA0_IO_WR_PRI_URGENCY_MASK__CID12_MASK__SHIFT 0xc 415495c1f7aaSFeifei Xu #define MMEA0_IO_WR_PRI_URGENCY_MASK__CID13_MASK__SHIFT 0xd 415595c1f7aaSFeifei Xu #define MMEA0_IO_WR_PRI_URGENCY_MASK__CID14_MASK__SHIFT 0xe 415695c1f7aaSFeifei Xu #define MMEA0_IO_WR_PRI_URGENCY_MASK__CID15_MASK__SHIFT 0xf 415795c1f7aaSFeifei Xu #define MMEA0_IO_WR_PRI_URGENCY_MASK__CID16_MASK__SHIFT 0x10 415895c1f7aaSFeifei Xu #define MMEA0_IO_WR_PRI_URGENCY_MASK__CID17_MASK__SHIFT 0x11 415995c1f7aaSFeifei Xu #define MMEA0_IO_WR_PRI_URGENCY_MASK__CID18_MASK__SHIFT 0x12 416095c1f7aaSFeifei Xu #define MMEA0_IO_WR_PRI_URGENCY_MASK__CID19_MASK__SHIFT 0x13 416195c1f7aaSFeifei Xu #define MMEA0_IO_WR_PRI_URGENCY_MASK__CID20_MASK__SHIFT 0x14 416295c1f7aaSFeifei Xu #define MMEA0_IO_WR_PRI_URGENCY_MASK__CID21_MASK__SHIFT 0x15 416395c1f7aaSFeifei Xu #define MMEA0_IO_WR_PRI_URGENCY_MASK__CID22_MASK__SHIFT 0x16 416495c1f7aaSFeifei Xu #define MMEA0_IO_WR_PRI_URGENCY_MASK__CID23_MASK__SHIFT 0x17 416595c1f7aaSFeifei Xu #define MMEA0_IO_WR_PRI_URGENCY_MASK__CID24_MASK__SHIFT 0x18 416695c1f7aaSFeifei Xu #define MMEA0_IO_WR_PRI_URGENCY_MASK__CID25_MASK__SHIFT 0x19 416795c1f7aaSFeifei Xu #define MMEA0_IO_WR_PRI_URGENCY_MASK__CID26_MASK__SHIFT 0x1a 416895c1f7aaSFeifei Xu #define MMEA0_IO_WR_PRI_URGENCY_MASK__CID27_MASK__SHIFT 0x1b 416995c1f7aaSFeifei Xu #define MMEA0_IO_WR_PRI_URGENCY_MASK__CID28_MASK__SHIFT 0x1c 417095c1f7aaSFeifei Xu #define MMEA0_IO_WR_PRI_URGENCY_MASK__CID29_MASK__SHIFT 0x1d 417195c1f7aaSFeifei Xu #define MMEA0_IO_WR_PRI_URGENCY_MASK__CID30_MASK__SHIFT 0x1e 417295c1f7aaSFeifei Xu #define MMEA0_IO_WR_PRI_URGENCY_MASK__CID31_MASK__SHIFT 0x1f 417395c1f7aaSFeifei Xu #define MMEA0_IO_WR_PRI_URGENCY_MASK__CID0_MASK_MASK 0x00000001L 417495c1f7aaSFeifei Xu #define MMEA0_IO_WR_PRI_URGENCY_MASK__CID1_MASK_MASK 0x00000002L 417595c1f7aaSFeifei Xu #define MMEA0_IO_WR_PRI_URGENCY_MASK__CID2_MASK_MASK 0x00000004L 417695c1f7aaSFeifei Xu #define MMEA0_IO_WR_PRI_URGENCY_MASK__CID3_MASK_MASK 0x00000008L 417795c1f7aaSFeifei Xu #define MMEA0_IO_WR_PRI_URGENCY_MASK__CID4_MASK_MASK 0x00000010L 417895c1f7aaSFeifei Xu #define MMEA0_IO_WR_PRI_URGENCY_MASK__CID5_MASK_MASK 0x00000020L 417995c1f7aaSFeifei Xu #define MMEA0_IO_WR_PRI_URGENCY_MASK__CID6_MASK_MASK 0x00000040L 418095c1f7aaSFeifei Xu #define MMEA0_IO_WR_PRI_URGENCY_MASK__CID7_MASK_MASK 0x00000080L 418195c1f7aaSFeifei Xu #define MMEA0_IO_WR_PRI_URGENCY_MASK__CID8_MASK_MASK 0x00000100L 418295c1f7aaSFeifei Xu #define MMEA0_IO_WR_PRI_URGENCY_MASK__CID9_MASK_MASK 0x00000200L 418395c1f7aaSFeifei Xu #define MMEA0_IO_WR_PRI_URGENCY_MASK__CID10_MASK_MASK 0x00000400L 418495c1f7aaSFeifei Xu #define MMEA0_IO_WR_PRI_URGENCY_MASK__CID11_MASK_MASK 0x00000800L 418595c1f7aaSFeifei Xu #define MMEA0_IO_WR_PRI_URGENCY_MASK__CID12_MASK_MASK 0x00001000L 418695c1f7aaSFeifei Xu #define MMEA0_IO_WR_PRI_URGENCY_MASK__CID13_MASK_MASK 0x00002000L 418795c1f7aaSFeifei Xu #define MMEA0_IO_WR_PRI_URGENCY_MASK__CID14_MASK_MASK 0x00004000L 418895c1f7aaSFeifei Xu #define MMEA0_IO_WR_PRI_URGENCY_MASK__CID15_MASK_MASK 0x00008000L 418995c1f7aaSFeifei Xu #define MMEA0_IO_WR_PRI_URGENCY_MASK__CID16_MASK_MASK 0x00010000L 419095c1f7aaSFeifei Xu #define MMEA0_IO_WR_PRI_URGENCY_MASK__CID17_MASK_MASK 0x00020000L 419195c1f7aaSFeifei Xu #define MMEA0_IO_WR_PRI_URGENCY_MASK__CID18_MASK_MASK 0x00040000L 419295c1f7aaSFeifei Xu #define MMEA0_IO_WR_PRI_URGENCY_MASK__CID19_MASK_MASK 0x00080000L 419395c1f7aaSFeifei Xu #define MMEA0_IO_WR_PRI_URGENCY_MASK__CID20_MASK_MASK 0x00100000L 419495c1f7aaSFeifei Xu #define MMEA0_IO_WR_PRI_URGENCY_MASK__CID21_MASK_MASK 0x00200000L 419595c1f7aaSFeifei Xu #define MMEA0_IO_WR_PRI_URGENCY_MASK__CID22_MASK_MASK 0x00400000L 419695c1f7aaSFeifei Xu #define MMEA0_IO_WR_PRI_URGENCY_MASK__CID23_MASK_MASK 0x00800000L 419795c1f7aaSFeifei Xu #define MMEA0_IO_WR_PRI_URGENCY_MASK__CID24_MASK_MASK 0x01000000L 419895c1f7aaSFeifei Xu #define MMEA0_IO_WR_PRI_URGENCY_MASK__CID25_MASK_MASK 0x02000000L 419995c1f7aaSFeifei Xu #define MMEA0_IO_WR_PRI_URGENCY_MASK__CID26_MASK_MASK 0x04000000L 420095c1f7aaSFeifei Xu #define MMEA0_IO_WR_PRI_URGENCY_MASK__CID27_MASK_MASK 0x08000000L 420195c1f7aaSFeifei Xu #define MMEA0_IO_WR_PRI_URGENCY_MASK__CID28_MASK_MASK 0x10000000L 420295c1f7aaSFeifei Xu #define MMEA0_IO_WR_PRI_URGENCY_MASK__CID29_MASK_MASK 0x20000000L 420395c1f7aaSFeifei Xu #define MMEA0_IO_WR_PRI_URGENCY_MASK__CID30_MASK_MASK 0x40000000L 420495c1f7aaSFeifei Xu #define MMEA0_IO_WR_PRI_URGENCY_MASK__CID31_MASK_MASK 0x80000000L 420595c1f7aaSFeifei Xu //MMEA0_IO_RD_PRI_QUANT_PRI1 420695c1f7aaSFeifei Xu #define MMEA0_IO_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 420795c1f7aaSFeifei Xu #define MMEA0_IO_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 420895c1f7aaSFeifei Xu #define MMEA0_IO_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 420995c1f7aaSFeifei Xu #define MMEA0_IO_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 421095c1f7aaSFeifei Xu #define MMEA0_IO_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL 421195c1f7aaSFeifei Xu #define MMEA0_IO_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L 421295c1f7aaSFeifei Xu #define MMEA0_IO_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L 421395c1f7aaSFeifei Xu #define MMEA0_IO_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L 421495c1f7aaSFeifei Xu //MMEA0_IO_RD_PRI_QUANT_PRI2 421595c1f7aaSFeifei Xu #define MMEA0_IO_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 421695c1f7aaSFeifei Xu #define MMEA0_IO_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 421795c1f7aaSFeifei Xu #define MMEA0_IO_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 421895c1f7aaSFeifei Xu #define MMEA0_IO_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 421995c1f7aaSFeifei Xu #define MMEA0_IO_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL 422095c1f7aaSFeifei Xu #define MMEA0_IO_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L 422195c1f7aaSFeifei Xu #define MMEA0_IO_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L 422295c1f7aaSFeifei Xu #define MMEA0_IO_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L 422395c1f7aaSFeifei Xu //MMEA0_IO_RD_PRI_QUANT_PRI3 422495c1f7aaSFeifei Xu #define MMEA0_IO_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 422595c1f7aaSFeifei Xu #define MMEA0_IO_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 422695c1f7aaSFeifei Xu #define MMEA0_IO_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 422795c1f7aaSFeifei Xu #define MMEA0_IO_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 422895c1f7aaSFeifei Xu #define MMEA0_IO_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL 422995c1f7aaSFeifei Xu #define MMEA0_IO_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L 423095c1f7aaSFeifei Xu #define MMEA0_IO_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L 423195c1f7aaSFeifei Xu #define MMEA0_IO_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L 423295c1f7aaSFeifei Xu //MMEA0_IO_WR_PRI_QUANT_PRI1 423395c1f7aaSFeifei Xu #define MMEA0_IO_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 423495c1f7aaSFeifei Xu #define MMEA0_IO_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 423595c1f7aaSFeifei Xu #define MMEA0_IO_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 423695c1f7aaSFeifei Xu #define MMEA0_IO_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 423795c1f7aaSFeifei Xu #define MMEA0_IO_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL 423895c1f7aaSFeifei Xu #define MMEA0_IO_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L 423995c1f7aaSFeifei Xu #define MMEA0_IO_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L 424095c1f7aaSFeifei Xu #define MMEA0_IO_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L 424195c1f7aaSFeifei Xu //MMEA0_IO_WR_PRI_QUANT_PRI2 424295c1f7aaSFeifei Xu #define MMEA0_IO_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 424395c1f7aaSFeifei Xu #define MMEA0_IO_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 424495c1f7aaSFeifei Xu #define MMEA0_IO_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 424595c1f7aaSFeifei Xu #define MMEA0_IO_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 424695c1f7aaSFeifei Xu #define MMEA0_IO_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL 424795c1f7aaSFeifei Xu #define MMEA0_IO_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L 424895c1f7aaSFeifei Xu #define MMEA0_IO_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L 424995c1f7aaSFeifei Xu #define MMEA0_IO_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L 425095c1f7aaSFeifei Xu //MMEA0_IO_WR_PRI_QUANT_PRI3 425195c1f7aaSFeifei Xu #define MMEA0_IO_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 425295c1f7aaSFeifei Xu #define MMEA0_IO_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 425395c1f7aaSFeifei Xu #define MMEA0_IO_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 425495c1f7aaSFeifei Xu #define MMEA0_IO_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 425595c1f7aaSFeifei Xu #define MMEA0_IO_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL 425695c1f7aaSFeifei Xu #define MMEA0_IO_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L 425795c1f7aaSFeifei Xu #define MMEA0_IO_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L 425895c1f7aaSFeifei Xu #define MMEA0_IO_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L 425995c1f7aaSFeifei Xu //MMEA0_SDP_ARB_DRAM 426095c1f7aaSFeifei Xu #define MMEA0_SDP_ARB_DRAM__RDWR_BURST_LIMIT_CYCL__SHIFT 0x0 426195c1f7aaSFeifei Xu #define MMEA0_SDP_ARB_DRAM__RDWR_BURST_LIMIT_DATA__SHIFT 0x8 426295c1f7aaSFeifei Xu #define MMEA0_SDP_ARB_DRAM__EARLY_SW2RD_ON_PRI__SHIFT 0x10 426395c1f7aaSFeifei Xu #define MMEA0_SDP_ARB_DRAM__EARLY_SW2WR_ON_PRI__SHIFT 0x11 426495c1f7aaSFeifei Xu #define MMEA0_SDP_ARB_DRAM__EARLY_SW2RD_ON_RES__SHIFT 0x12 426595c1f7aaSFeifei Xu #define MMEA0_SDP_ARB_DRAM__EARLY_SW2WR_ON_RES__SHIFT 0x13 426695c1f7aaSFeifei Xu #define MMEA0_SDP_ARB_DRAM__EOB_ON_EXPIRE__SHIFT 0x14 426795c1f7aaSFeifei Xu #define MMEA0_SDP_ARB_DRAM__RDWR_BURST_LIMIT_CYCL_MASK 0x0000007FL 426895c1f7aaSFeifei Xu #define MMEA0_SDP_ARB_DRAM__RDWR_BURST_LIMIT_DATA_MASK 0x00007F00L 426995c1f7aaSFeifei Xu #define MMEA0_SDP_ARB_DRAM__EARLY_SW2RD_ON_PRI_MASK 0x00010000L 427095c1f7aaSFeifei Xu #define MMEA0_SDP_ARB_DRAM__EARLY_SW2WR_ON_PRI_MASK 0x00020000L 427195c1f7aaSFeifei Xu #define MMEA0_SDP_ARB_DRAM__EARLY_SW2RD_ON_RES_MASK 0x00040000L 427295c1f7aaSFeifei Xu #define MMEA0_SDP_ARB_DRAM__EARLY_SW2WR_ON_RES_MASK 0x00080000L 427395c1f7aaSFeifei Xu #define MMEA0_SDP_ARB_DRAM__EOB_ON_EXPIRE_MASK 0x00100000L 427495c1f7aaSFeifei Xu //MMEA0_SDP_ARB_FINAL 427595c1f7aaSFeifei Xu #define MMEA0_SDP_ARB_FINAL__DRAM_BURST_LIMIT__SHIFT 0x0 427695c1f7aaSFeifei Xu #define MMEA0_SDP_ARB_FINAL__GMI_BURST_LIMIT__SHIFT 0x5 427795c1f7aaSFeifei Xu #define MMEA0_SDP_ARB_FINAL__IO_BURST_LIMIT__SHIFT 0xa 427895c1f7aaSFeifei Xu #define MMEA0_SDP_ARB_FINAL__BURST_LIMIT_MULTIPLIER__SHIFT 0xf 427995c1f7aaSFeifei Xu #define MMEA0_SDP_ARB_FINAL__RDONLY_VC0__SHIFT 0x11 428095c1f7aaSFeifei Xu #define MMEA0_SDP_ARB_FINAL__RDONLY_VC1__SHIFT 0x12 428195c1f7aaSFeifei Xu #define MMEA0_SDP_ARB_FINAL__RDONLY_VC2__SHIFT 0x13 428295c1f7aaSFeifei Xu #define MMEA0_SDP_ARB_FINAL__RDONLY_VC3__SHIFT 0x14 428395c1f7aaSFeifei Xu #define MMEA0_SDP_ARB_FINAL__RDONLY_VC4__SHIFT 0x15 428495c1f7aaSFeifei Xu #define MMEA0_SDP_ARB_FINAL__RDONLY_VC5__SHIFT 0x16 428595c1f7aaSFeifei Xu #define MMEA0_SDP_ARB_FINAL__RDONLY_VC6__SHIFT 0x17 428695c1f7aaSFeifei Xu #define MMEA0_SDP_ARB_FINAL__RDONLY_VC7__SHIFT 0x18 428795c1f7aaSFeifei Xu #define MMEA0_SDP_ARB_FINAL__ERREVENT_ON_ERROR__SHIFT 0x19 428895c1f7aaSFeifei Xu #define MMEA0_SDP_ARB_FINAL__HALTREQ_ON_ERROR__SHIFT 0x1a 428995c1f7aaSFeifei Xu #define MMEA0_SDP_ARB_FINAL__DRAM_BURST_LIMIT_MASK 0x0000001FL 429095c1f7aaSFeifei Xu #define MMEA0_SDP_ARB_FINAL__GMI_BURST_LIMIT_MASK 0x000003E0L 429195c1f7aaSFeifei Xu #define MMEA0_SDP_ARB_FINAL__IO_BURST_LIMIT_MASK 0x00007C00L 429295c1f7aaSFeifei Xu #define MMEA0_SDP_ARB_FINAL__BURST_LIMIT_MULTIPLIER_MASK 0x00018000L 429395c1f7aaSFeifei Xu #define MMEA0_SDP_ARB_FINAL__RDONLY_VC0_MASK 0x00020000L 429495c1f7aaSFeifei Xu #define MMEA0_SDP_ARB_FINAL__RDONLY_VC1_MASK 0x00040000L 429595c1f7aaSFeifei Xu #define MMEA0_SDP_ARB_FINAL__RDONLY_VC2_MASK 0x00080000L 429695c1f7aaSFeifei Xu #define MMEA0_SDP_ARB_FINAL__RDONLY_VC3_MASK 0x00100000L 429795c1f7aaSFeifei Xu #define MMEA0_SDP_ARB_FINAL__RDONLY_VC4_MASK 0x00200000L 429895c1f7aaSFeifei Xu #define MMEA0_SDP_ARB_FINAL__RDONLY_VC5_MASK 0x00400000L 429995c1f7aaSFeifei Xu #define MMEA0_SDP_ARB_FINAL__RDONLY_VC6_MASK 0x00800000L 430095c1f7aaSFeifei Xu #define MMEA0_SDP_ARB_FINAL__RDONLY_VC7_MASK 0x01000000L 430195c1f7aaSFeifei Xu #define MMEA0_SDP_ARB_FINAL__ERREVENT_ON_ERROR_MASK 0x02000000L 430295c1f7aaSFeifei Xu #define MMEA0_SDP_ARB_FINAL__HALTREQ_ON_ERROR_MASK 0x04000000L 430395c1f7aaSFeifei Xu //MMEA0_SDP_DRAM_PRIORITY 430495c1f7aaSFeifei Xu #define MMEA0_SDP_DRAM_PRIORITY__RD_GROUP0_PRIORITY__SHIFT 0x0 430595c1f7aaSFeifei Xu #define MMEA0_SDP_DRAM_PRIORITY__RD_GROUP1_PRIORITY__SHIFT 0x4 430695c1f7aaSFeifei Xu #define MMEA0_SDP_DRAM_PRIORITY__RD_GROUP2_PRIORITY__SHIFT 0x8 430795c1f7aaSFeifei Xu #define MMEA0_SDP_DRAM_PRIORITY__RD_GROUP3_PRIORITY__SHIFT 0xc 430895c1f7aaSFeifei Xu #define MMEA0_SDP_DRAM_PRIORITY__WR_GROUP0_PRIORITY__SHIFT 0x10 430995c1f7aaSFeifei Xu #define MMEA0_SDP_DRAM_PRIORITY__WR_GROUP1_PRIORITY__SHIFT 0x14 431095c1f7aaSFeifei Xu #define MMEA0_SDP_DRAM_PRIORITY__WR_GROUP2_PRIORITY__SHIFT 0x18 431195c1f7aaSFeifei Xu #define MMEA0_SDP_DRAM_PRIORITY__WR_GROUP3_PRIORITY__SHIFT 0x1c 431295c1f7aaSFeifei Xu #define MMEA0_SDP_DRAM_PRIORITY__RD_GROUP0_PRIORITY_MASK 0x0000000FL 431395c1f7aaSFeifei Xu #define MMEA0_SDP_DRAM_PRIORITY__RD_GROUP1_PRIORITY_MASK 0x000000F0L 431495c1f7aaSFeifei Xu #define MMEA0_SDP_DRAM_PRIORITY__RD_GROUP2_PRIORITY_MASK 0x00000F00L 431595c1f7aaSFeifei Xu #define MMEA0_SDP_DRAM_PRIORITY__RD_GROUP3_PRIORITY_MASK 0x0000F000L 431695c1f7aaSFeifei Xu #define MMEA0_SDP_DRAM_PRIORITY__WR_GROUP0_PRIORITY_MASK 0x000F0000L 431795c1f7aaSFeifei Xu #define MMEA0_SDP_DRAM_PRIORITY__WR_GROUP1_PRIORITY_MASK 0x00F00000L 431895c1f7aaSFeifei Xu #define MMEA0_SDP_DRAM_PRIORITY__WR_GROUP2_PRIORITY_MASK 0x0F000000L 431995c1f7aaSFeifei Xu #define MMEA0_SDP_DRAM_PRIORITY__WR_GROUP3_PRIORITY_MASK 0xF0000000L 432095c1f7aaSFeifei Xu //MMEA0_SDP_IO_PRIORITY 432195c1f7aaSFeifei Xu #define MMEA0_SDP_IO_PRIORITY__RD_GROUP0_PRIORITY__SHIFT 0x0 432295c1f7aaSFeifei Xu #define MMEA0_SDP_IO_PRIORITY__RD_GROUP1_PRIORITY__SHIFT 0x4 432395c1f7aaSFeifei Xu #define MMEA0_SDP_IO_PRIORITY__RD_GROUP2_PRIORITY__SHIFT 0x8 432495c1f7aaSFeifei Xu #define MMEA0_SDP_IO_PRIORITY__RD_GROUP3_PRIORITY__SHIFT 0xc 432595c1f7aaSFeifei Xu #define MMEA0_SDP_IO_PRIORITY__WR_GROUP0_PRIORITY__SHIFT 0x10 432695c1f7aaSFeifei Xu #define MMEA0_SDP_IO_PRIORITY__WR_GROUP1_PRIORITY__SHIFT 0x14 432795c1f7aaSFeifei Xu #define MMEA0_SDP_IO_PRIORITY__WR_GROUP2_PRIORITY__SHIFT 0x18 432895c1f7aaSFeifei Xu #define MMEA0_SDP_IO_PRIORITY__WR_GROUP3_PRIORITY__SHIFT 0x1c 432995c1f7aaSFeifei Xu #define MMEA0_SDP_IO_PRIORITY__RD_GROUP0_PRIORITY_MASK 0x0000000FL 433095c1f7aaSFeifei Xu #define MMEA0_SDP_IO_PRIORITY__RD_GROUP1_PRIORITY_MASK 0x000000F0L 433195c1f7aaSFeifei Xu #define MMEA0_SDP_IO_PRIORITY__RD_GROUP2_PRIORITY_MASK 0x00000F00L 433295c1f7aaSFeifei Xu #define MMEA0_SDP_IO_PRIORITY__RD_GROUP3_PRIORITY_MASK 0x0000F000L 433395c1f7aaSFeifei Xu #define MMEA0_SDP_IO_PRIORITY__WR_GROUP0_PRIORITY_MASK 0x000F0000L 433495c1f7aaSFeifei Xu #define MMEA0_SDP_IO_PRIORITY__WR_GROUP1_PRIORITY_MASK 0x00F00000L 433595c1f7aaSFeifei Xu #define MMEA0_SDP_IO_PRIORITY__WR_GROUP2_PRIORITY_MASK 0x0F000000L 433695c1f7aaSFeifei Xu #define MMEA0_SDP_IO_PRIORITY__WR_GROUP3_PRIORITY_MASK 0xF0000000L 433795c1f7aaSFeifei Xu //MMEA0_SDP_CREDITS 433895c1f7aaSFeifei Xu #define MMEA0_SDP_CREDITS__TAG_LIMIT__SHIFT 0x0 433995c1f7aaSFeifei Xu #define MMEA0_SDP_CREDITS__WR_RESP_CREDITS__SHIFT 0x8 434095c1f7aaSFeifei Xu #define MMEA0_SDP_CREDITS__RD_RESP_CREDITS__SHIFT 0x10 434195c1f7aaSFeifei Xu #define MMEA0_SDP_CREDITS__TAG_LIMIT_MASK 0x000000FFL 434295c1f7aaSFeifei Xu #define MMEA0_SDP_CREDITS__WR_RESP_CREDITS_MASK 0x00007F00L 434395c1f7aaSFeifei Xu #define MMEA0_SDP_CREDITS__RD_RESP_CREDITS_MASK 0x007F0000L 434495c1f7aaSFeifei Xu //MMEA0_SDP_TAG_RESERVE0 434595c1f7aaSFeifei Xu #define MMEA0_SDP_TAG_RESERVE0__VC0__SHIFT 0x0 434695c1f7aaSFeifei Xu #define MMEA0_SDP_TAG_RESERVE0__VC1__SHIFT 0x8 434795c1f7aaSFeifei Xu #define MMEA0_SDP_TAG_RESERVE0__VC2__SHIFT 0x10 434895c1f7aaSFeifei Xu #define MMEA0_SDP_TAG_RESERVE0__VC3__SHIFT 0x18 434995c1f7aaSFeifei Xu #define MMEA0_SDP_TAG_RESERVE0__VC0_MASK 0x000000FFL 435095c1f7aaSFeifei Xu #define MMEA0_SDP_TAG_RESERVE0__VC1_MASK 0x0000FF00L 435195c1f7aaSFeifei Xu #define MMEA0_SDP_TAG_RESERVE0__VC2_MASK 0x00FF0000L 435295c1f7aaSFeifei Xu #define MMEA0_SDP_TAG_RESERVE0__VC3_MASK 0xFF000000L 435395c1f7aaSFeifei Xu //MMEA0_SDP_TAG_RESERVE1 435495c1f7aaSFeifei Xu #define MMEA0_SDP_TAG_RESERVE1__VC4__SHIFT 0x0 435595c1f7aaSFeifei Xu #define MMEA0_SDP_TAG_RESERVE1__VC5__SHIFT 0x8 435695c1f7aaSFeifei Xu #define MMEA0_SDP_TAG_RESERVE1__VC6__SHIFT 0x10 435795c1f7aaSFeifei Xu #define MMEA0_SDP_TAG_RESERVE1__VC7__SHIFT 0x18 435895c1f7aaSFeifei Xu #define MMEA0_SDP_TAG_RESERVE1__VC4_MASK 0x000000FFL 435995c1f7aaSFeifei Xu #define MMEA0_SDP_TAG_RESERVE1__VC5_MASK 0x0000FF00L 436095c1f7aaSFeifei Xu #define MMEA0_SDP_TAG_RESERVE1__VC6_MASK 0x00FF0000L 436195c1f7aaSFeifei Xu #define MMEA0_SDP_TAG_RESERVE1__VC7_MASK 0xFF000000L 436295c1f7aaSFeifei Xu //MMEA0_SDP_VCC_RESERVE0 436395c1f7aaSFeifei Xu #define MMEA0_SDP_VCC_RESERVE0__VC0_CREDITS__SHIFT 0x0 436495c1f7aaSFeifei Xu #define MMEA0_SDP_VCC_RESERVE0__VC1_CREDITS__SHIFT 0x6 436595c1f7aaSFeifei Xu #define MMEA0_SDP_VCC_RESERVE0__VC2_CREDITS__SHIFT 0xc 436695c1f7aaSFeifei Xu #define MMEA0_SDP_VCC_RESERVE0__VC3_CREDITS__SHIFT 0x12 436795c1f7aaSFeifei Xu #define MMEA0_SDP_VCC_RESERVE0__VC4_CREDITS__SHIFT 0x18 436895c1f7aaSFeifei Xu #define MMEA0_SDP_VCC_RESERVE0__VC0_CREDITS_MASK 0x0000003FL 436995c1f7aaSFeifei Xu #define MMEA0_SDP_VCC_RESERVE0__VC1_CREDITS_MASK 0x00000FC0L 437095c1f7aaSFeifei Xu #define MMEA0_SDP_VCC_RESERVE0__VC2_CREDITS_MASK 0x0003F000L 437195c1f7aaSFeifei Xu #define MMEA0_SDP_VCC_RESERVE0__VC3_CREDITS_MASK 0x00FC0000L 437295c1f7aaSFeifei Xu #define MMEA0_SDP_VCC_RESERVE0__VC4_CREDITS_MASK 0x3F000000L 437395c1f7aaSFeifei Xu //MMEA0_SDP_VCC_RESERVE1 437495c1f7aaSFeifei Xu #define MMEA0_SDP_VCC_RESERVE1__VC5_CREDITS__SHIFT 0x0 437595c1f7aaSFeifei Xu #define MMEA0_SDP_VCC_RESERVE1__VC6_CREDITS__SHIFT 0x6 437695c1f7aaSFeifei Xu #define MMEA0_SDP_VCC_RESERVE1__VC7_CREDITS__SHIFT 0xc 437795c1f7aaSFeifei Xu #define MMEA0_SDP_VCC_RESERVE1__DISTRIBUTE_POOL__SHIFT 0x1f 437895c1f7aaSFeifei Xu #define MMEA0_SDP_VCC_RESERVE1__VC5_CREDITS_MASK 0x0000003FL 437995c1f7aaSFeifei Xu #define MMEA0_SDP_VCC_RESERVE1__VC6_CREDITS_MASK 0x00000FC0L 438095c1f7aaSFeifei Xu #define MMEA0_SDP_VCC_RESERVE1__VC7_CREDITS_MASK 0x0003F000L 438195c1f7aaSFeifei Xu #define MMEA0_SDP_VCC_RESERVE1__DISTRIBUTE_POOL_MASK 0x80000000L 438295c1f7aaSFeifei Xu //MMEA0_SDP_VCD_RESERVE0 438395c1f7aaSFeifei Xu #define MMEA0_SDP_VCD_RESERVE0__VC0_CREDITS__SHIFT 0x0 438495c1f7aaSFeifei Xu #define MMEA0_SDP_VCD_RESERVE0__VC1_CREDITS__SHIFT 0x6 438595c1f7aaSFeifei Xu #define MMEA0_SDP_VCD_RESERVE0__VC2_CREDITS__SHIFT 0xc 438695c1f7aaSFeifei Xu #define MMEA0_SDP_VCD_RESERVE0__VC3_CREDITS__SHIFT 0x12 438795c1f7aaSFeifei Xu #define MMEA0_SDP_VCD_RESERVE0__VC4_CREDITS__SHIFT 0x18 438895c1f7aaSFeifei Xu #define MMEA0_SDP_VCD_RESERVE0__VC0_CREDITS_MASK 0x0000003FL 438995c1f7aaSFeifei Xu #define MMEA0_SDP_VCD_RESERVE0__VC1_CREDITS_MASK 0x00000FC0L 439095c1f7aaSFeifei Xu #define MMEA0_SDP_VCD_RESERVE0__VC2_CREDITS_MASK 0x0003F000L 439195c1f7aaSFeifei Xu #define MMEA0_SDP_VCD_RESERVE0__VC3_CREDITS_MASK 0x00FC0000L 439295c1f7aaSFeifei Xu #define MMEA0_SDP_VCD_RESERVE0__VC4_CREDITS_MASK 0x3F000000L 439395c1f7aaSFeifei Xu //MMEA0_SDP_VCD_RESERVE1 439495c1f7aaSFeifei Xu #define MMEA0_SDP_VCD_RESERVE1__VC5_CREDITS__SHIFT 0x0 439595c1f7aaSFeifei Xu #define MMEA0_SDP_VCD_RESERVE1__VC6_CREDITS__SHIFT 0x6 439695c1f7aaSFeifei Xu #define MMEA0_SDP_VCD_RESERVE1__VC7_CREDITS__SHIFT 0xc 439795c1f7aaSFeifei Xu #define MMEA0_SDP_VCD_RESERVE1__DISTRIBUTE_POOL__SHIFT 0x1f 439895c1f7aaSFeifei Xu #define MMEA0_SDP_VCD_RESERVE1__VC5_CREDITS_MASK 0x0000003FL 439995c1f7aaSFeifei Xu #define MMEA0_SDP_VCD_RESERVE1__VC6_CREDITS_MASK 0x00000FC0L 440095c1f7aaSFeifei Xu #define MMEA0_SDP_VCD_RESERVE1__VC7_CREDITS_MASK 0x0003F000L 440195c1f7aaSFeifei Xu #define MMEA0_SDP_VCD_RESERVE1__DISTRIBUTE_POOL_MASK 0x80000000L 440295c1f7aaSFeifei Xu //MMEA0_SDP_REQ_CNTL 440395c1f7aaSFeifei Xu #define MMEA0_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_READ__SHIFT 0x0 440495c1f7aaSFeifei Xu #define MMEA0_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_WRITE__SHIFT 0x1 440595c1f7aaSFeifei Xu #define MMEA0_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_ATOMIC__SHIFT 0x2 440695c1f7aaSFeifei Xu #define MMEA0_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_DRAM__SHIFT 0x3 440795c1f7aaSFeifei Xu #define MMEA0_SDP_REQ_CNTL__INNER_DOMAIN_MODE__SHIFT 0x4 440895c1f7aaSFeifei Xu #define MMEA0_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_READ_MASK 0x00000001L 440995c1f7aaSFeifei Xu #define MMEA0_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_WRITE_MASK 0x00000002L 441095c1f7aaSFeifei Xu #define MMEA0_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_ATOMIC_MASK 0x00000004L 441195c1f7aaSFeifei Xu #define MMEA0_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_DRAM_MASK 0x00000008L 441295c1f7aaSFeifei Xu #define MMEA0_SDP_REQ_CNTL__INNER_DOMAIN_MODE_MASK 0x00000010L 441395c1f7aaSFeifei Xu //MMEA0_MISC 441495c1f7aaSFeifei Xu #define MMEA0_MISC__RELATIVE_PRI_IN_DRAM_RD_ARB__SHIFT 0x0 441595c1f7aaSFeifei Xu #define MMEA0_MISC__RELATIVE_PRI_IN_DRAM_WR_ARB__SHIFT 0x1 441695c1f7aaSFeifei Xu #define MMEA0_MISC__RELATIVE_PRI_IN_GMI_RD_ARB__SHIFT 0x2 441795c1f7aaSFeifei Xu #define MMEA0_MISC__RELATIVE_PRI_IN_GMI_WR_ARB__SHIFT 0x3 441895c1f7aaSFeifei Xu #define MMEA0_MISC__RELATIVE_PRI_IN_IO_RD_ARB__SHIFT 0x4 441995c1f7aaSFeifei Xu #define MMEA0_MISC__RELATIVE_PRI_IN_IO_WR_ARB__SHIFT 0x5 442095c1f7aaSFeifei Xu #define MMEA0_MISC__RRET_SWAP_MODE__SHIFT 0x6 442195c1f7aaSFeifei Xu #define MMEA0_MISC__EARLY_SDP_ORIGDATA__SHIFT 0x7 442295c1f7aaSFeifei Xu #define MMEA0_MISC__LINKMGR_DYNAMIC_MODE__SHIFT 0x8 442395c1f7aaSFeifei Xu #define MMEA0_MISC__LINKMGR_HALT_THRESHOLD__SHIFT 0xa 442495c1f7aaSFeifei Xu #define MMEA0_MISC__LINKMGR_RECONNECT_DELAY__SHIFT 0xc 442595c1f7aaSFeifei Xu #define MMEA0_MISC__LINKMGR_IDLE_THRESHOLD__SHIFT 0xe 442695c1f7aaSFeifei Xu #define MMEA0_MISC__FAVOUR_MIDCHAIN_CS_IN_DRAM_ARB__SHIFT 0x13 442795c1f7aaSFeifei Xu #define MMEA0_MISC__FAVOUR_MIDCHAIN_CS_IN_GMI_ARB__SHIFT 0x14 442895c1f7aaSFeifei Xu #define MMEA0_MISC__FAVOUR_LAST_CS_IN_DRAM_ARB__SHIFT 0x15 442995c1f7aaSFeifei Xu #define MMEA0_MISC__FAVOUR_LAST_CS_IN_GMI_ARB__SHIFT 0x16 443095c1f7aaSFeifei Xu #define MMEA0_MISC__SWITCH_CS_ON_W2R_IN_DRAM_ARB__SHIFT 0x17 443195c1f7aaSFeifei Xu #define MMEA0_MISC__SWITCH_CS_ON_W2R_IN_GMI_ARB__SHIFT 0x18 443295c1f7aaSFeifei Xu #define MMEA0_MISC__RELATIVE_PRI_IN_DRAM_RD_ARB_MASK 0x00000001L 443395c1f7aaSFeifei Xu #define MMEA0_MISC__RELATIVE_PRI_IN_DRAM_WR_ARB_MASK 0x00000002L 443495c1f7aaSFeifei Xu #define MMEA0_MISC__RELATIVE_PRI_IN_GMI_RD_ARB_MASK 0x00000004L 443595c1f7aaSFeifei Xu #define MMEA0_MISC__RELATIVE_PRI_IN_GMI_WR_ARB_MASK 0x00000008L 443695c1f7aaSFeifei Xu #define MMEA0_MISC__RELATIVE_PRI_IN_IO_RD_ARB_MASK 0x00000010L 443795c1f7aaSFeifei Xu #define MMEA0_MISC__RELATIVE_PRI_IN_IO_WR_ARB_MASK 0x00000020L 443895c1f7aaSFeifei Xu #define MMEA0_MISC__RRET_SWAP_MODE_MASK 0x00000040L 443995c1f7aaSFeifei Xu #define MMEA0_MISC__EARLY_SDP_ORIGDATA_MASK 0x00000080L 444095c1f7aaSFeifei Xu #define MMEA0_MISC__LINKMGR_DYNAMIC_MODE_MASK 0x00000300L 444195c1f7aaSFeifei Xu #define MMEA0_MISC__LINKMGR_HALT_THRESHOLD_MASK 0x00000C00L 444295c1f7aaSFeifei Xu #define MMEA0_MISC__LINKMGR_RECONNECT_DELAY_MASK 0x00003000L 444395c1f7aaSFeifei Xu #define MMEA0_MISC__LINKMGR_IDLE_THRESHOLD_MASK 0x0007C000L 444495c1f7aaSFeifei Xu #define MMEA0_MISC__FAVOUR_MIDCHAIN_CS_IN_DRAM_ARB_MASK 0x00080000L 444595c1f7aaSFeifei Xu #define MMEA0_MISC__FAVOUR_MIDCHAIN_CS_IN_GMI_ARB_MASK 0x00100000L 444695c1f7aaSFeifei Xu #define MMEA0_MISC__FAVOUR_LAST_CS_IN_DRAM_ARB_MASK 0x00200000L 444795c1f7aaSFeifei Xu #define MMEA0_MISC__FAVOUR_LAST_CS_IN_GMI_ARB_MASK 0x00400000L 444895c1f7aaSFeifei Xu #define MMEA0_MISC__SWITCH_CS_ON_W2R_IN_DRAM_ARB_MASK 0x00800000L 444995c1f7aaSFeifei Xu #define MMEA0_MISC__SWITCH_CS_ON_W2R_IN_GMI_ARB_MASK 0x01000000L 445095c1f7aaSFeifei Xu //MMEA0_LATENCY_SAMPLING 445195c1f7aaSFeifei Xu #define MMEA0_LATENCY_SAMPLING__SAMPLER0_DRAM__SHIFT 0x0 445295c1f7aaSFeifei Xu #define MMEA0_LATENCY_SAMPLING__SAMPLER1_DRAM__SHIFT 0x1 445395c1f7aaSFeifei Xu #define MMEA0_LATENCY_SAMPLING__SAMPLER0_GMI__SHIFT 0x2 445495c1f7aaSFeifei Xu #define MMEA0_LATENCY_SAMPLING__SAMPLER1_GMI__SHIFT 0x3 445595c1f7aaSFeifei Xu #define MMEA0_LATENCY_SAMPLING__SAMPLER0_IO__SHIFT 0x4 445695c1f7aaSFeifei Xu #define MMEA0_LATENCY_SAMPLING__SAMPLER1_IO__SHIFT 0x5 445795c1f7aaSFeifei Xu #define MMEA0_LATENCY_SAMPLING__SAMPLER0_READ__SHIFT 0x6 445895c1f7aaSFeifei Xu #define MMEA0_LATENCY_SAMPLING__SAMPLER1_READ__SHIFT 0x7 445995c1f7aaSFeifei Xu #define MMEA0_LATENCY_SAMPLING__SAMPLER0_WRITE__SHIFT 0x8 446095c1f7aaSFeifei Xu #define MMEA0_LATENCY_SAMPLING__SAMPLER1_WRITE__SHIFT 0x9 446195c1f7aaSFeifei Xu #define MMEA0_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET__SHIFT 0xa 446295c1f7aaSFeifei Xu #define MMEA0_LATENCY_SAMPLING__SAMPLER1_ATOMIC_RET__SHIFT 0xb 446395c1f7aaSFeifei Xu #define MMEA0_LATENCY_SAMPLING__SAMPLER0_ATOMIC_NORET__SHIFT 0xc 446495c1f7aaSFeifei Xu #define MMEA0_LATENCY_SAMPLING__SAMPLER1_ATOMIC_NORET__SHIFT 0xd 446595c1f7aaSFeifei Xu #define MMEA0_LATENCY_SAMPLING__SAMPLER0_VC__SHIFT 0xe 446695c1f7aaSFeifei Xu #define MMEA0_LATENCY_SAMPLING__SAMPLER1_VC__SHIFT 0x16 446795c1f7aaSFeifei Xu #define MMEA0_LATENCY_SAMPLING__SAMPLER0_DRAM_MASK 0x00000001L 446895c1f7aaSFeifei Xu #define MMEA0_LATENCY_SAMPLING__SAMPLER1_DRAM_MASK 0x00000002L 446995c1f7aaSFeifei Xu #define MMEA0_LATENCY_SAMPLING__SAMPLER0_GMI_MASK 0x00000004L 447095c1f7aaSFeifei Xu #define MMEA0_LATENCY_SAMPLING__SAMPLER1_GMI_MASK 0x00000008L 447195c1f7aaSFeifei Xu #define MMEA0_LATENCY_SAMPLING__SAMPLER0_IO_MASK 0x00000010L 447295c1f7aaSFeifei Xu #define MMEA0_LATENCY_SAMPLING__SAMPLER1_IO_MASK 0x00000020L 447395c1f7aaSFeifei Xu #define MMEA0_LATENCY_SAMPLING__SAMPLER0_READ_MASK 0x00000040L 447495c1f7aaSFeifei Xu #define MMEA0_LATENCY_SAMPLING__SAMPLER1_READ_MASK 0x00000080L 447595c1f7aaSFeifei Xu #define MMEA0_LATENCY_SAMPLING__SAMPLER0_WRITE_MASK 0x00000100L 447695c1f7aaSFeifei Xu #define MMEA0_LATENCY_SAMPLING__SAMPLER1_WRITE_MASK 0x00000200L 447795c1f7aaSFeifei Xu #define MMEA0_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET_MASK 0x00000400L 447895c1f7aaSFeifei Xu #define MMEA0_LATENCY_SAMPLING__SAMPLER1_ATOMIC_RET_MASK 0x00000800L 447995c1f7aaSFeifei Xu #define MMEA0_LATENCY_SAMPLING__SAMPLER0_ATOMIC_NORET_MASK 0x00001000L 448095c1f7aaSFeifei Xu #define MMEA0_LATENCY_SAMPLING__SAMPLER1_ATOMIC_NORET_MASK 0x00002000L 448195c1f7aaSFeifei Xu #define MMEA0_LATENCY_SAMPLING__SAMPLER0_VC_MASK 0x003FC000L 448295c1f7aaSFeifei Xu #define MMEA0_LATENCY_SAMPLING__SAMPLER1_VC_MASK 0x3FC00000L 448395c1f7aaSFeifei Xu //MMEA0_PERFCOUNTER_LO 448495c1f7aaSFeifei Xu #define MMEA0_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 448595c1f7aaSFeifei Xu #define MMEA0_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL 448695c1f7aaSFeifei Xu //MMEA0_PERFCOUNTER_HI 448795c1f7aaSFeifei Xu #define MMEA0_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 448895c1f7aaSFeifei Xu #define MMEA0_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 448995c1f7aaSFeifei Xu #define MMEA0_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL 449095c1f7aaSFeifei Xu #define MMEA0_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L 449195c1f7aaSFeifei Xu //MMEA0_PERFCOUNTER0_CFG 449295c1f7aaSFeifei Xu #define MMEA0_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 449395c1f7aaSFeifei Xu #define MMEA0_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 449495c1f7aaSFeifei Xu #define MMEA0_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 449595c1f7aaSFeifei Xu #define MMEA0_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c 449695c1f7aaSFeifei Xu #define MMEA0_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d 449795c1f7aaSFeifei Xu #define MMEA0_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL 449895c1f7aaSFeifei Xu #define MMEA0_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L 449995c1f7aaSFeifei Xu #define MMEA0_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L 450095c1f7aaSFeifei Xu #define MMEA0_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L 450195c1f7aaSFeifei Xu #define MMEA0_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L 450295c1f7aaSFeifei Xu //MMEA0_PERFCOUNTER1_CFG 450395c1f7aaSFeifei Xu #define MMEA0_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 450495c1f7aaSFeifei Xu #define MMEA0_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 450595c1f7aaSFeifei Xu #define MMEA0_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 450695c1f7aaSFeifei Xu #define MMEA0_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c 450795c1f7aaSFeifei Xu #define MMEA0_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d 450895c1f7aaSFeifei Xu #define MMEA0_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL 450995c1f7aaSFeifei Xu #define MMEA0_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L 451095c1f7aaSFeifei Xu #define MMEA0_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L 451195c1f7aaSFeifei Xu #define MMEA0_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L 451295c1f7aaSFeifei Xu #define MMEA0_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L 451395c1f7aaSFeifei Xu //MMEA0_PERFCOUNTER_RSLT_CNTL 451495c1f7aaSFeifei Xu #define MMEA0_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 451595c1f7aaSFeifei Xu #define MMEA0_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 451695c1f7aaSFeifei Xu #define MMEA0_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 451795c1f7aaSFeifei Xu #define MMEA0_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 451895c1f7aaSFeifei Xu #define MMEA0_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 451995c1f7aaSFeifei Xu #define MMEA0_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a 452095c1f7aaSFeifei Xu #define MMEA0_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL 452195c1f7aaSFeifei Xu #define MMEA0_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L 452295c1f7aaSFeifei Xu #define MMEA0_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L 452395c1f7aaSFeifei Xu #define MMEA0_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L 452495c1f7aaSFeifei Xu #define MMEA0_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L 452595c1f7aaSFeifei Xu #define MMEA0_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L 452695c1f7aaSFeifei Xu //MMEA0_EDC_CNT 452795c1f7aaSFeifei Xu #define MMEA0_EDC_CNT__DRAMRD_CMDMEM_SEC_COUNT__SHIFT 0x0 452895c1f7aaSFeifei Xu #define MMEA0_EDC_CNT__DRAMRD_CMDMEM_DED_COUNT__SHIFT 0x2 452995c1f7aaSFeifei Xu #define MMEA0_EDC_CNT__DRAMWR_CMDMEM_SEC_COUNT__SHIFT 0x4 453095c1f7aaSFeifei Xu #define MMEA0_EDC_CNT__DRAMWR_CMDMEM_DED_COUNT__SHIFT 0x6 453195c1f7aaSFeifei Xu #define MMEA0_EDC_CNT__DRAMWR_DATAMEM_SEC_COUNT__SHIFT 0x8 453295c1f7aaSFeifei Xu #define MMEA0_EDC_CNT__DRAMWR_DATAMEM_DED_COUNT__SHIFT 0xa 453395c1f7aaSFeifei Xu #define MMEA0_EDC_CNT__RRET_TAGMEM_SEC_COUNT__SHIFT 0xc 453495c1f7aaSFeifei Xu #define MMEA0_EDC_CNT__RRET_TAGMEM_DED_COUNT__SHIFT 0xe 453595c1f7aaSFeifei Xu #define MMEA0_EDC_CNT__WRET_TAGMEM_SEC_COUNT__SHIFT 0x10 453695c1f7aaSFeifei Xu #define MMEA0_EDC_CNT__WRET_TAGMEM_DED_COUNT__SHIFT 0x12 453795c1f7aaSFeifei Xu #define MMEA0_EDC_CNT__DRAMRD_PAGEMEM_SED_COUNT__SHIFT 0x14 453895c1f7aaSFeifei Xu #define MMEA0_EDC_CNT__DRAMWR_PAGEMEM_SED_COUNT__SHIFT 0x16 453995c1f7aaSFeifei Xu #define MMEA0_EDC_CNT__IORD_CMDMEM_SED_COUNT__SHIFT 0x18 454095c1f7aaSFeifei Xu #define MMEA0_EDC_CNT__IOWR_CMDMEM_SED_COUNT__SHIFT 0x1a 454195c1f7aaSFeifei Xu #define MMEA0_EDC_CNT__IOWR_DATAMEM_SED_COUNT__SHIFT 0x1c 454295c1f7aaSFeifei Xu #define MMEA0_EDC_CNT__DRAMRD_CMDMEM_SEC_COUNT_MASK 0x00000003L 454395c1f7aaSFeifei Xu #define MMEA0_EDC_CNT__DRAMRD_CMDMEM_DED_COUNT_MASK 0x0000000CL 454495c1f7aaSFeifei Xu #define MMEA0_EDC_CNT__DRAMWR_CMDMEM_SEC_COUNT_MASK 0x00000030L 454595c1f7aaSFeifei Xu #define MMEA0_EDC_CNT__DRAMWR_CMDMEM_DED_COUNT_MASK 0x000000C0L 454695c1f7aaSFeifei Xu #define MMEA0_EDC_CNT__DRAMWR_DATAMEM_SEC_COUNT_MASK 0x00000300L 454795c1f7aaSFeifei Xu #define MMEA0_EDC_CNT__DRAMWR_DATAMEM_DED_COUNT_MASK 0x00000C00L 454895c1f7aaSFeifei Xu #define MMEA0_EDC_CNT__RRET_TAGMEM_SEC_COUNT_MASK 0x00003000L 454995c1f7aaSFeifei Xu #define MMEA0_EDC_CNT__RRET_TAGMEM_DED_COUNT_MASK 0x0000C000L 455095c1f7aaSFeifei Xu #define MMEA0_EDC_CNT__WRET_TAGMEM_SEC_COUNT_MASK 0x00030000L 455195c1f7aaSFeifei Xu #define MMEA0_EDC_CNT__WRET_TAGMEM_DED_COUNT_MASK 0x000C0000L 455295c1f7aaSFeifei Xu #define MMEA0_EDC_CNT__DRAMRD_PAGEMEM_SED_COUNT_MASK 0x00300000L 455395c1f7aaSFeifei Xu #define MMEA0_EDC_CNT__DRAMWR_PAGEMEM_SED_COUNT_MASK 0x00C00000L 455495c1f7aaSFeifei Xu #define MMEA0_EDC_CNT__IORD_CMDMEM_SED_COUNT_MASK 0x03000000L 455595c1f7aaSFeifei Xu #define MMEA0_EDC_CNT__IOWR_CMDMEM_SED_COUNT_MASK 0x0C000000L 455695c1f7aaSFeifei Xu #define MMEA0_EDC_CNT__IOWR_DATAMEM_SED_COUNT_MASK 0x30000000L 455795c1f7aaSFeifei Xu //MMEA0_EDC_CNT2 455895c1f7aaSFeifei Xu #define MMEA0_EDC_CNT2__GMIRD_CMDMEM_SEC_COUNT__SHIFT 0x0 455995c1f7aaSFeifei Xu #define MMEA0_EDC_CNT2__GMIRD_CMDMEM_DED_COUNT__SHIFT 0x2 456095c1f7aaSFeifei Xu #define MMEA0_EDC_CNT2__GMIWR_CMDMEM_SEC_COUNT__SHIFT 0x4 456195c1f7aaSFeifei Xu #define MMEA0_EDC_CNT2__GMIWR_CMDMEM_DED_COUNT__SHIFT 0x6 456295c1f7aaSFeifei Xu #define MMEA0_EDC_CNT2__GMIWR_DATAMEM_SEC_COUNT__SHIFT 0x8 456395c1f7aaSFeifei Xu #define MMEA0_EDC_CNT2__GMIWR_DATAMEM_DED_COUNT__SHIFT 0xa 456495c1f7aaSFeifei Xu #define MMEA0_EDC_CNT2__GMIRD_PAGEMEM_SED_COUNT__SHIFT 0xc 456595c1f7aaSFeifei Xu #define MMEA0_EDC_CNT2__GMIWR_PAGEMEM_SED_COUNT__SHIFT 0xe 456695c1f7aaSFeifei Xu #define MMEA0_EDC_CNT2__GMIRD_CMDMEM_SEC_COUNT_MASK 0x00000003L 456795c1f7aaSFeifei Xu #define MMEA0_EDC_CNT2__GMIRD_CMDMEM_DED_COUNT_MASK 0x0000000CL 456895c1f7aaSFeifei Xu #define MMEA0_EDC_CNT2__GMIWR_CMDMEM_SEC_COUNT_MASK 0x00000030L 456995c1f7aaSFeifei Xu #define MMEA0_EDC_CNT2__GMIWR_CMDMEM_DED_COUNT_MASK 0x000000C0L 457095c1f7aaSFeifei Xu #define MMEA0_EDC_CNT2__GMIWR_DATAMEM_SEC_COUNT_MASK 0x00000300L 457195c1f7aaSFeifei Xu #define MMEA0_EDC_CNT2__GMIWR_DATAMEM_DED_COUNT_MASK 0x00000C00L 457295c1f7aaSFeifei Xu #define MMEA0_EDC_CNT2__GMIRD_PAGEMEM_SED_COUNT_MASK 0x00003000L 457395c1f7aaSFeifei Xu #define MMEA0_EDC_CNT2__GMIWR_PAGEMEM_SED_COUNT_MASK 0x0000C000L 457495c1f7aaSFeifei Xu //MMEA0_DSM_CNTL 457595c1f7aaSFeifei Xu #define MMEA0_DSM_CNTL__DRAMRD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x0 457695c1f7aaSFeifei Xu #define MMEA0_DSM_CNTL__DRAMRD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x2 457795c1f7aaSFeifei Xu #define MMEA0_DSM_CNTL__DRAMWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x3 457895c1f7aaSFeifei Xu #define MMEA0_DSM_CNTL__DRAMWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x5 457995c1f7aaSFeifei Xu #define MMEA0_DSM_CNTL__DRAMWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT 0x6 458095c1f7aaSFeifei Xu #define MMEA0_DSM_CNTL__DRAMWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT 0x8 458195c1f7aaSFeifei Xu #define MMEA0_DSM_CNTL__RRET_TAGMEM_DSM_IRRITATOR_DATA__SHIFT 0x9 458295c1f7aaSFeifei Xu #define MMEA0_DSM_CNTL__RRET_TAGMEM_ENABLE_SINGLE_WRITE__SHIFT 0xb 458395c1f7aaSFeifei Xu #define MMEA0_DSM_CNTL__WRET_TAGMEM_DSM_IRRITATOR_DATA__SHIFT 0xc 458495c1f7aaSFeifei Xu #define MMEA0_DSM_CNTL__WRET_TAGMEM_ENABLE_SINGLE_WRITE__SHIFT 0xe 458595c1f7aaSFeifei Xu #define MMEA0_DSM_CNTL__GMIRD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0xf 458695c1f7aaSFeifei Xu #define MMEA0_DSM_CNTL__GMIRD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x11 458795c1f7aaSFeifei Xu #define MMEA0_DSM_CNTL__GMIWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x12 458895c1f7aaSFeifei Xu #define MMEA0_DSM_CNTL__GMIWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x14 458995c1f7aaSFeifei Xu #define MMEA0_DSM_CNTL__GMIWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT 0x15 459095c1f7aaSFeifei Xu #define MMEA0_DSM_CNTL__GMIWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT 0x17 459195c1f7aaSFeifei Xu #define MMEA0_DSM_CNTL__DRAMRD_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00000003L 459295c1f7aaSFeifei Xu #define MMEA0_DSM_CNTL__DRAMRD_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000004L 459395c1f7aaSFeifei Xu #define MMEA0_DSM_CNTL__DRAMWR_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00000018L 459495c1f7aaSFeifei Xu #define MMEA0_DSM_CNTL__DRAMWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000020L 459595c1f7aaSFeifei Xu #define MMEA0_DSM_CNTL__DRAMWR_DATAMEM_DSM_IRRITATOR_DATA_MASK 0x000000C0L 459695c1f7aaSFeifei Xu #define MMEA0_DSM_CNTL__DRAMWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK 0x00000100L 459795c1f7aaSFeifei Xu #define MMEA0_DSM_CNTL__RRET_TAGMEM_DSM_IRRITATOR_DATA_MASK 0x00000600L 459895c1f7aaSFeifei Xu #define MMEA0_DSM_CNTL__RRET_TAGMEM_ENABLE_SINGLE_WRITE_MASK 0x00000800L 459995c1f7aaSFeifei Xu #define MMEA0_DSM_CNTL__WRET_TAGMEM_DSM_IRRITATOR_DATA_MASK 0x00003000L 460095c1f7aaSFeifei Xu #define MMEA0_DSM_CNTL__WRET_TAGMEM_ENABLE_SINGLE_WRITE_MASK 0x00004000L 460195c1f7aaSFeifei Xu #define MMEA0_DSM_CNTL__GMIRD_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00018000L 460295c1f7aaSFeifei Xu #define MMEA0_DSM_CNTL__GMIRD_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00020000L 460395c1f7aaSFeifei Xu #define MMEA0_DSM_CNTL__GMIWR_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x000C0000L 460495c1f7aaSFeifei Xu #define MMEA0_DSM_CNTL__GMIWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00100000L 460595c1f7aaSFeifei Xu #define MMEA0_DSM_CNTL__GMIWR_DATAMEM_DSM_IRRITATOR_DATA_MASK 0x00600000L 460695c1f7aaSFeifei Xu #define MMEA0_DSM_CNTL__GMIWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK 0x00800000L 460795c1f7aaSFeifei Xu //MMEA0_DSM_CNTLA 460895c1f7aaSFeifei Xu #define MMEA0_DSM_CNTLA__DRAMRD_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0x0 460995c1f7aaSFeifei Xu #define MMEA0_DSM_CNTLA__DRAMRD_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x2 461095c1f7aaSFeifei Xu #define MMEA0_DSM_CNTLA__DRAMWR_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0x3 461195c1f7aaSFeifei Xu #define MMEA0_DSM_CNTLA__DRAMWR_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x5 461295c1f7aaSFeifei Xu #define MMEA0_DSM_CNTLA__IORD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x6 461395c1f7aaSFeifei Xu #define MMEA0_DSM_CNTLA__IORD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x8 461495c1f7aaSFeifei Xu #define MMEA0_DSM_CNTLA__IOWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x9 461595c1f7aaSFeifei Xu #define MMEA0_DSM_CNTLA__IOWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0xb 461695c1f7aaSFeifei Xu #define MMEA0_DSM_CNTLA__IOWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT 0xc 461795c1f7aaSFeifei Xu #define MMEA0_DSM_CNTLA__IOWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT 0xe 461895c1f7aaSFeifei Xu #define MMEA0_DSM_CNTLA__GMIRD_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0xf 461995c1f7aaSFeifei Xu #define MMEA0_DSM_CNTLA__GMIRD_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x11 462095c1f7aaSFeifei Xu #define MMEA0_DSM_CNTLA__GMIWR_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0x12 462195c1f7aaSFeifei Xu #define MMEA0_DSM_CNTLA__GMIWR_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x14 462295c1f7aaSFeifei Xu #define MMEA0_DSM_CNTLA__DRAMRD_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x00000003L 462395c1f7aaSFeifei Xu #define MMEA0_DSM_CNTLA__DRAMRD_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00000004L 462495c1f7aaSFeifei Xu #define MMEA0_DSM_CNTLA__DRAMWR_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x00000018L 462595c1f7aaSFeifei Xu #define MMEA0_DSM_CNTLA__DRAMWR_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00000020L 462695c1f7aaSFeifei Xu #define MMEA0_DSM_CNTLA__IORD_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x000000C0L 462795c1f7aaSFeifei Xu #define MMEA0_DSM_CNTLA__IORD_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000100L 462895c1f7aaSFeifei Xu #define MMEA0_DSM_CNTLA__IOWR_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00000600L 462995c1f7aaSFeifei Xu #define MMEA0_DSM_CNTLA__IOWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000800L 463095c1f7aaSFeifei Xu #define MMEA0_DSM_CNTLA__IOWR_DATAMEM_DSM_IRRITATOR_DATA_MASK 0x00003000L 463195c1f7aaSFeifei Xu #define MMEA0_DSM_CNTLA__IOWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK 0x00004000L 463295c1f7aaSFeifei Xu #define MMEA0_DSM_CNTLA__GMIRD_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x00018000L 463395c1f7aaSFeifei Xu #define MMEA0_DSM_CNTLA__GMIRD_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00020000L 463495c1f7aaSFeifei Xu #define MMEA0_DSM_CNTLA__GMIWR_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x000C0000L 463595c1f7aaSFeifei Xu #define MMEA0_DSM_CNTLA__GMIWR_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00100000L 463695c1f7aaSFeifei Xu //MMEA0_DSM_CNTLB 463795c1f7aaSFeifei Xu //MMEA0_DSM_CNTL2 463895c1f7aaSFeifei Xu #define MMEA0_DSM_CNTL2__DRAMRD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x0 463995c1f7aaSFeifei Xu #define MMEA0_DSM_CNTL2__DRAMRD_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x2 464095c1f7aaSFeifei Xu #define MMEA0_DSM_CNTL2__DRAMWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x3 464195c1f7aaSFeifei Xu #define MMEA0_DSM_CNTL2__DRAMWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x5 464295c1f7aaSFeifei Xu #define MMEA0_DSM_CNTL2__DRAMWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT 0x6 464395c1f7aaSFeifei Xu #define MMEA0_DSM_CNTL2__DRAMWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT 0x8 464495c1f7aaSFeifei Xu #define MMEA0_DSM_CNTL2__RRET_TAGMEM_ENABLE_ERROR_INJECT__SHIFT 0x9 464595c1f7aaSFeifei Xu #define MMEA0_DSM_CNTL2__RRET_TAGMEM_SELECT_INJECT_DELAY__SHIFT 0xb 464695c1f7aaSFeifei Xu #define MMEA0_DSM_CNTL2__WRET_TAGMEM_ENABLE_ERROR_INJECT__SHIFT 0xc 464795c1f7aaSFeifei Xu #define MMEA0_DSM_CNTL2__WRET_TAGMEM_SELECT_INJECT_DELAY__SHIFT 0xe 464895c1f7aaSFeifei Xu #define MMEA0_DSM_CNTL2__GMIRD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0xf 464995c1f7aaSFeifei Xu #define MMEA0_DSM_CNTL2__GMIRD_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x11 465095c1f7aaSFeifei Xu #define MMEA0_DSM_CNTL2__GMIWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x12 465195c1f7aaSFeifei Xu #define MMEA0_DSM_CNTL2__GMIWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x14 465295c1f7aaSFeifei Xu #define MMEA0_DSM_CNTL2__GMIWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT 0x15 465395c1f7aaSFeifei Xu #define MMEA0_DSM_CNTL2__GMIWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT 0x17 465495c1f7aaSFeifei Xu #define MMEA0_DSM_CNTL2__INJECT_DELAY__SHIFT 0x1a 465595c1f7aaSFeifei Xu #define MMEA0_DSM_CNTL2__DRAMRD_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00000003L 465695c1f7aaSFeifei Xu #define MMEA0_DSM_CNTL2__DRAMRD_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000004L 465795c1f7aaSFeifei Xu #define MMEA0_DSM_CNTL2__DRAMWR_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00000018L 465895c1f7aaSFeifei Xu #define MMEA0_DSM_CNTL2__DRAMWR_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000020L 465995c1f7aaSFeifei Xu #define MMEA0_DSM_CNTL2__DRAMWR_DATAMEM_ENABLE_ERROR_INJECT_MASK 0x000000C0L 466095c1f7aaSFeifei Xu #define MMEA0_DSM_CNTL2__DRAMWR_DATAMEM_SELECT_INJECT_DELAY_MASK 0x00000100L 466195c1f7aaSFeifei Xu #define MMEA0_DSM_CNTL2__RRET_TAGMEM_ENABLE_ERROR_INJECT_MASK 0x00000600L 466295c1f7aaSFeifei Xu #define MMEA0_DSM_CNTL2__RRET_TAGMEM_SELECT_INJECT_DELAY_MASK 0x00000800L 466395c1f7aaSFeifei Xu #define MMEA0_DSM_CNTL2__WRET_TAGMEM_ENABLE_ERROR_INJECT_MASK 0x00003000L 466495c1f7aaSFeifei Xu #define MMEA0_DSM_CNTL2__WRET_TAGMEM_SELECT_INJECT_DELAY_MASK 0x00004000L 466595c1f7aaSFeifei Xu #define MMEA0_DSM_CNTL2__GMIRD_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00018000L 466695c1f7aaSFeifei Xu #define MMEA0_DSM_CNTL2__GMIRD_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00020000L 466795c1f7aaSFeifei Xu #define MMEA0_DSM_CNTL2__GMIWR_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x000C0000L 466895c1f7aaSFeifei Xu #define MMEA0_DSM_CNTL2__GMIWR_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00100000L 466995c1f7aaSFeifei Xu #define MMEA0_DSM_CNTL2__GMIWR_DATAMEM_ENABLE_ERROR_INJECT_MASK 0x00600000L 467095c1f7aaSFeifei Xu #define MMEA0_DSM_CNTL2__GMIWR_DATAMEM_SELECT_INJECT_DELAY_MASK 0x00800000L 467195c1f7aaSFeifei Xu #define MMEA0_DSM_CNTL2__INJECT_DELAY_MASK 0xFC000000L 467295c1f7aaSFeifei Xu //MMEA0_DSM_CNTL2A 467395c1f7aaSFeifei Xu #define MMEA0_DSM_CNTL2A__DRAMRD_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0x0 467495c1f7aaSFeifei Xu #define MMEA0_DSM_CNTL2A__DRAMRD_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x2 467595c1f7aaSFeifei Xu #define MMEA0_DSM_CNTL2A__DRAMWR_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0x3 467695c1f7aaSFeifei Xu #define MMEA0_DSM_CNTL2A__DRAMWR_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x5 467795c1f7aaSFeifei Xu #define MMEA0_DSM_CNTL2A__IORD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x6 467895c1f7aaSFeifei Xu #define MMEA0_DSM_CNTL2A__IORD_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x8 467995c1f7aaSFeifei Xu #define MMEA0_DSM_CNTL2A__IOWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x9 468095c1f7aaSFeifei Xu #define MMEA0_DSM_CNTL2A__IOWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0xb 468195c1f7aaSFeifei Xu #define MMEA0_DSM_CNTL2A__IOWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT 0xc 468295c1f7aaSFeifei Xu #define MMEA0_DSM_CNTL2A__IOWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT 0xe 468395c1f7aaSFeifei Xu #define MMEA0_DSM_CNTL2A__GMIRD_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0xf 468495c1f7aaSFeifei Xu #define MMEA0_DSM_CNTL2A__GMIRD_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x11 468595c1f7aaSFeifei Xu #define MMEA0_DSM_CNTL2A__GMIWR_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0x12 468695c1f7aaSFeifei Xu #define MMEA0_DSM_CNTL2A__GMIWR_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x14 468795c1f7aaSFeifei Xu #define MMEA0_DSM_CNTL2A__DRAMRD_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x00000003L 468895c1f7aaSFeifei Xu #define MMEA0_DSM_CNTL2A__DRAMRD_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00000004L 468995c1f7aaSFeifei Xu #define MMEA0_DSM_CNTL2A__DRAMWR_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x00000018L 469095c1f7aaSFeifei Xu #define MMEA0_DSM_CNTL2A__DRAMWR_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00000020L 469195c1f7aaSFeifei Xu #define MMEA0_DSM_CNTL2A__IORD_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x000000C0L 469295c1f7aaSFeifei Xu #define MMEA0_DSM_CNTL2A__IORD_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000100L 469395c1f7aaSFeifei Xu #define MMEA0_DSM_CNTL2A__IOWR_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00000600L 469495c1f7aaSFeifei Xu #define MMEA0_DSM_CNTL2A__IOWR_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000800L 469595c1f7aaSFeifei Xu #define MMEA0_DSM_CNTL2A__IOWR_DATAMEM_ENABLE_ERROR_INJECT_MASK 0x00003000L 469695c1f7aaSFeifei Xu #define MMEA0_DSM_CNTL2A__IOWR_DATAMEM_SELECT_INJECT_DELAY_MASK 0x00004000L 469795c1f7aaSFeifei Xu #define MMEA0_DSM_CNTL2A__GMIRD_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x00018000L 469895c1f7aaSFeifei Xu #define MMEA0_DSM_CNTL2A__GMIRD_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00020000L 469995c1f7aaSFeifei Xu #define MMEA0_DSM_CNTL2A__GMIWR_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x000C0000L 470095c1f7aaSFeifei Xu #define MMEA0_DSM_CNTL2A__GMIWR_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00100000L 470195c1f7aaSFeifei Xu //MMEA0_DSM_CNTL2B 470295c1f7aaSFeifei Xu //MMEA0_CGTT_CLK_CTRL 470395c1f7aaSFeifei Xu #define MMEA0_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 470495c1f7aaSFeifei Xu #define MMEA0_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 470595c1f7aaSFeifei Xu #define MMEA0_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16 470695c1f7aaSFeifei Xu #define MMEA0_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b 470795c1f7aaSFeifei Xu #define MMEA0_CGTT_CLK_CTRL__SOFT_OVERRIDE_WRITE__SHIFT 0x1c 470895c1f7aaSFeifei Xu #define MMEA0_CGTT_CLK_CTRL__SOFT_OVERRIDE_READ__SHIFT 0x1d 470995c1f7aaSFeifei Xu #define MMEA0_CGTT_CLK_CTRL__SOFT_OVERRIDE_RETURN__SHIFT 0x1e 471095c1f7aaSFeifei Xu #define MMEA0_CGTT_CLK_CTRL__SOFT_OVERRIDE_REGISTER__SHIFT 0x1f 471195c1f7aaSFeifei Xu #define MMEA0_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL 471295c1f7aaSFeifei Xu #define MMEA0_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L 471395c1f7aaSFeifei Xu #define MMEA0_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L 471495c1f7aaSFeifei Xu #define MMEA0_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L 471595c1f7aaSFeifei Xu #define MMEA0_CGTT_CLK_CTRL__SOFT_OVERRIDE_WRITE_MASK 0x10000000L 471695c1f7aaSFeifei Xu #define MMEA0_CGTT_CLK_CTRL__SOFT_OVERRIDE_READ_MASK 0x20000000L 471795c1f7aaSFeifei Xu #define MMEA0_CGTT_CLK_CTRL__SOFT_OVERRIDE_RETURN_MASK 0x40000000L 471895c1f7aaSFeifei Xu #define MMEA0_CGTT_CLK_CTRL__SOFT_OVERRIDE_REGISTER_MASK 0x80000000L 471995c1f7aaSFeifei Xu //MMEA0_EDC_MODE 472095c1f7aaSFeifei Xu #define MMEA0_EDC_MODE__COUNT_FED_OUT__SHIFT 0x10 472195c1f7aaSFeifei Xu #define MMEA0_EDC_MODE__GATE_FUE__SHIFT 0x11 472295c1f7aaSFeifei Xu #define MMEA0_EDC_MODE__DED_MODE__SHIFT 0x14 472395c1f7aaSFeifei Xu #define MMEA0_EDC_MODE__PROP_FED__SHIFT 0x1d 472495c1f7aaSFeifei Xu #define MMEA0_EDC_MODE__BYPASS__SHIFT 0x1f 472595c1f7aaSFeifei Xu #define MMEA0_EDC_MODE__COUNT_FED_OUT_MASK 0x00010000L 472695c1f7aaSFeifei Xu #define MMEA0_EDC_MODE__GATE_FUE_MASK 0x00020000L 472795c1f7aaSFeifei Xu #define MMEA0_EDC_MODE__DED_MODE_MASK 0x00300000L 472895c1f7aaSFeifei Xu #define MMEA0_EDC_MODE__PROP_FED_MASK 0x20000000L 472995c1f7aaSFeifei Xu #define MMEA0_EDC_MODE__BYPASS_MASK 0x80000000L 473095c1f7aaSFeifei Xu //MMEA0_ERR_STATUS 473195c1f7aaSFeifei Xu #define MMEA0_ERR_STATUS__SDP_RDRSP_STATUS__SHIFT 0x0 473295c1f7aaSFeifei Xu #define MMEA0_ERR_STATUS__SDP_WRRSP_STATUS__SHIFT 0x4 473395c1f7aaSFeifei Xu #define MMEA0_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR__SHIFT 0x8 473495c1f7aaSFeifei Xu #define MMEA0_ERR_STATUS__CLEAR_ERROR_STATUS__SHIFT 0x9 473595c1f7aaSFeifei Xu #define MMEA0_ERR_STATUS__BUSY_ON_ERROR__SHIFT 0xa 473695c1f7aaSFeifei Xu #define MMEA0_ERR_STATUS__SDP_RDRSP_STATUS_MASK 0x0000000FL 473795c1f7aaSFeifei Xu #define MMEA0_ERR_STATUS__SDP_WRRSP_STATUS_MASK 0x000000F0L 473895c1f7aaSFeifei Xu #define MMEA0_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR_MASK 0x00000100L 473995c1f7aaSFeifei Xu #define MMEA0_ERR_STATUS__CLEAR_ERROR_STATUS_MASK 0x00000200L 474095c1f7aaSFeifei Xu #define MMEA0_ERR_STATUS__BUSY_ON_ERROR_MASK 0x00000400L 474195c1f7aaSFeifei Xu //MMEA0_MISC2 474295c1f7aaSFeifei Xu #define MMEA0_MISC2__CSGROUP_SWAP_IN_DRAM_ARB__SHIFT 0x0 474395c1f7aaSFeifei Xu #define MMEA0_MISC2__CSGROUP_SWAP_IN_GMI_ARB__SHIFT 0x1 474495c1f7aaSFeifei Xu #define MMEA0_MISC2__CSGRP_BURST_LIMIT_DATA_DRAM__SHIFT 0x2 474595c1f7aaSFeifei Xu #define MMEA0_MISC2__CSGRP_BURST_LIMIT_DATA_GMI__SHIFT 0x7 474695c1f7aaSFeifei Xu #define MMEA0_MISC2__CSGROUP_SWAP_IN_DRAM_ARB_MASK 0x00000001L 474795c1f7aaSFeifei Xu #define MMEA0_MISC2__CSGROUP_SWAP_IN_GMI_ARB_MASK 0x00000002L 474895c1f7aaSFeifei Xu #define MMEA0_MISC2__CSGRP_BURST_LIMIT_DATA_DRAM_MASK 0x0000007CL 474995c1f7aaSFeifei Xu #define MMEA0_MISC2__CSGRP_BURST_LIMIT_DATA_GMI_MASK 0x00000F80L 475095c1f7aaSFeifei Xu //MMEA1_DRAM_RD_CLI2GRP_MAP0 475195c1f7aaSFeifei Xu #define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 475295c1f7aaSFeifei Xu #define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 475395c1f7aaSFeifei Xu #define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 475495c1f7aaSFeifei Xu #define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 475595c1f7aaSFeifei Xu #define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 475695c1f7aaSFeifei Xu #define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa 475795c1f7aaSFeifei Xu #define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc 475895c1f7aaSFeifei Xu #define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe 475995c1f7aaSFeifei Xu #define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 476095c1f7aaSFeifei Xu #define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 476195c1f7aaSFeifei Xu #define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 476295c1f7aaSFeifei Xu #define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 476395c1f7aaSFeifei Xu #define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 476495c1f7aaSFeifei Xu #define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a 476595c1f7aaSFeifei Xu #define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c 476695c1f7aaSFeifei Xu #define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e 476795c1f7aaSFeifei Xu #define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L 476895c1f7aaSFeifei Xu #define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL 476995c1f7aaSFeifei Xu #define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L 477095c1f7aaSFeifei Xu #define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L 477195c1f7aaSFeifei Xu #define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L 477295c1f7aaSFeifei Xu #define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L 477395c1f7aaSFeifei Xu #define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L 477495c1f7aaSFeifei Xu #define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L 477595c1f7aaSFeifei Xu #define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L 477695c1f7aaSFeifei Xu #define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L 477795c1f7aaSFeifei Xu #define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L 477895c1f7aaSFeifei Xu #define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L 477995c1f7aaSFeifei Xu #define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L 478095c1f7aaSFeifei Xu #define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L 478195c1f7aaSFeifei Xu #define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L 478295c1f7aaSFeifei Xu #define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L 478395c1f7aaSFeifei Xu //MMEA1_DRAM_RD_CLI2GRP_MAP1 478495c1f7aaSFeifei Xu #define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 478595c1f7aaSFeifei Xu #define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 478695c1f7aaSFeifei Xu #define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 478795c1f7aaSFeifei Xu #define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 478895c1f7aaSFeifei Xu #define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 478995c1f7aaSFeifei Xu #define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa 479095c1f7aaSFeifei Xu #define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc 479195c1f7aaSFeifei Xu #define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe 479295c1f7aaSFeifei Xu #define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 479395c1f7aaSFeifei Xu #define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 479495c1f7aaSFeifei Xu #define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 479595c1f7aaSFeifei Xu #define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 479695c1f7aaSFeifei Xu #define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 479795c1f7aaSFeifei Xu #define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a 479895c1f7aaSFeifei Xu #define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c 479995c1f7aaSFeifei Xu #define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e 480095c1f7aaSFeifei Xu #define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L 480195c1f7aaSFeifei Xu #define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL 480295c1f7aaSFeifei Xu #define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L 480395c1f7aaSFeifei Xu #define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L 480495c1f7aaSFeifei Xu #define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L 480595c1f7aaSFeifei Xu #define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L 480695c1f7aaSFeifei Xu #define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L 480795c1f7aaSFeifei Xu #define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L 480895c1f7aaSFeifei Xu #define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L 480995c1f7aaSFeifei Xu #define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L 481095c1f7aaSFeifei Xu #define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L 481195c1f7aaSFeifei Xu #define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L 481295c1f7aaSFeifei Xu #define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L 481395c1f7aaSFeifei Xu #define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L 481495c1f7aaSFeifei Xu #define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L 481595c1f7aaSFeifei Xu #define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L 481695c1f7aaSFeifei Xu //MMEA1_DRAM_WR_CLI2GRP_MAP0 481795c1f7aaSFeifei Xu #define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 481895c1f7aaSFeifei Xu #define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 481995c1f7aaSFeifei Xu #define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 482095c1f7aaSFeifei Xu #define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 482195c1f7aaSFeifei Xu #define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 482295c1f7aaSFeifei Xu #define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa 482395c1f7aaSFeifei Xu #define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc 482495c1f7aaSFeifei Xu #define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe 482595c1f7aaSFeifei Xu #define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 482695c1f7aaSFeifei Xu #define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 482795c1f7aaSFeifei Xu #define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 482895c1f7aaSFeifei Xu #define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 482995c1f7aaSFeifei Xu #define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 483095c1f7aaSFeifei Xu #define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a 483195c1f7aaSFeifei Xu #define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c 483295c1f7aaSFeifei Xu #define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e 483395c1f7aaSFeifei Xu #define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L 483495c1f7aaSFeifei Xu #define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL 483595c1f7aaSFeifei Xu #define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L 483695c1f7aaSFeifei Xu #define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L 483795c1f7aaSFeifei Xu #define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L 483895c1f7aaSFeifei Xu #define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L 483995c1f7aaSFeifei Xu #define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L 484095c1f7aaSFeifei Xu #define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L 484195c1f7aaSFeifei Xu #define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L 484295c1f7aaSFeifei Xu #define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L 484395c1f7aaSFeifei Xu #define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L 484495c1f7aaSFeifei Xu #define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L 484595c1f7aaSFeifei Xu #define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L 484695c1f7aaSFeifei Xu #define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L 484795c1f7aaSFeifei Xu #define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L 484895c1f7aaSFeifei Xu #define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L 484995c1f7aaSFeifei Xu //MMEA1_DRAM_WR_CLI2GRP_MAP1 485095c1f7aaSFeifei Xu #define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 485195c1f7aaSFeifei Xu #define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 485295c1f7aaSFeifei Xu #define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 485395c1f7aaSFeifei Xu #define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 485495c1f7aaSFeifei Xu #define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 485595c1f7aaSFeifei Xu #define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa 485695c1f7aaSFeifei Xu #define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc 485795c1f7aaSFeifei Xu #define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe 485895c1f7aaSFeifei Xu #define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 485995c1f7aaSFeifei Xu #define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 486095c1f7aaSFeifei Xu #define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 486195c1f7aaSFeifei Xu #define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 486295c1f7aaSFeifei Xu #define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 486395c1f7aaSFeifei Xu #define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a 486495c1f7aaSFeifei Xu #define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c 486595c1f7aaSFeifei Xu #define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e 486695c1f7aaSFeifei Xu #define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L 486795c1f7aaSFeifei Xu #define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL 486895c1f7aaSFeifei Xu #define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L 486995c1f7aaSFeifei Xu #define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L 487095c1f7aaSFeifei Xu #define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L 487195c1f7aaSFeifei Xu #define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L 487295c1f7aaSFeifei Xu #define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L 487395c1f7aaSFeifei Xu #define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L 487495c1f7aaSFeifei Xu #define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L 487595c1f7aaSFeifei Xu #define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L 487695c1f7aaSFeifei Xu #define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L 487795c1f7aaSFeifei Xu #define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L 487895c1f7aaSFeifei Xu #define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L 487995c1f7aaSFeifei Xu #define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L 488095c1f7aaSFeifei Xu #define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L 488195c1f7aaSFeifei Xu #define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L 488295c1f7aaSFeifei Xu //MMEA1_DRAM_RD_GRP2VC_MAP 488395c1f7aaSFeifei Xu #define MMEA1_DRAM_RD_GRP2VC_MAP__GROUP0_VC__SHIFT 0x0 488495c1f7aaSFeifei Xu #define MMEA1_DRAM_RD_GRP2VC_MAP__GROUP1_VC__SHIFT 0x3 488595c1f7aaSFeifei Xu #define MMEA1_DRAM_RD_GRP2VC_MAP__GROUP2_VC__SHIFT 0x6 488695c1f7aaSFeifei Xu #define MMEA1_DRAM_RD_GRP2VC_MAP__GROUP3_VC__SHIFT 0x9 488795c1f7aaSFeifei Xu #define MMEA1_DRAM_RD_GRP2VC_MAP__GROUP0_VC_MASK 0x00000007L 488895c1f7aaSFeifei Xu #define MMEA1_DRAM_RD_GRP2VC_MAP__GROUP1_VC_MASK 0x00000038L 488995c1f7aaSFeifei Xu #define MMEA1_DRAM_RD_GRP2VC_MAP__GROUP2_VC_MASK 0x000001C0L 489095c1f7aaSFeifei Xu #define MMEA1_DRAM_RD_GRP2VC_MAP__GROUP3_VC_MASK 0x00000E00L 489195c1f7aaSFeifei Xu //MMEA1_DRAM_WR_GRP2VC_MAP 489295c1f7aaSFeifei Xu #define MMEA1_DRAM_WR_GRP2VC_MAP__GROUP0_VC__SHIFT 0x0 489395c1f7aaSFeifei Xu #define MMEA1_DRAM_WR_GRP2VC_MAP__GROUP1_VC__SHIFT 0x3 489495c1f7aaSFeifei Xu #define MMEA1_DRAM_WR_GRP2VC_MAP__GROUP2_VC__SHIFT 0x6 489595c1f7aaSFeifei Xu #define MMEA1_DRAM_WR_GRP2VC_MAP__GROUP3_VC__SHIFT 0x9 489695c1f7aaSFeifei Xu #define MMEA1_DRAM_WR_GRP2VC_MAP__GROUP0_VC_MASK 0x00000007L 489795c1f7aaSFeifei Xu #define MMEA1_DRAM_WR_GRP2VC_MAP__GROUP1_VC_MASK 0x00000038L 489895c1f7aaSFeifei Xu #define MMEA1_DRAM_WR_GRP2VC_MAP__GROUP2_VC_MASK 0x000001C0L 489995c1f7aaSFeifei Xu #define MMEA1_DRAM_WR_GRP2VC_MAP__GROUP3_VC_MASK 0x00000E00L 490095c1f7aaSFeifei Xu //MMEA1_DRAM_RD_LAZY 490195c1f7aaSFeifei Xu #define MMEA1_DRAM_RD_LAZY__GROUP0_DELAY__SHIFT 0x0 490295c1f7aaSFeifei Xu #define MMEA1_DRAM_RD_LAZY__GROUP1_DELAY__SHIFT 0x3 490395c1f7aaSFeifei Xu #define MMEA1_DRAM_RD_LAZY__GROUP2_DELAY__SHIFT 0x6 490495c1f7aaSFeifei Xu #define MMEA1_DRAM_RD_LAZY__GROUP3_DELAY__SHIFT 0x9 490595c1f7aaSFeifei Xu #define MMEA1_DRAM_RD_LAZY__GROUP0_DELAY_MASK 0x00000007L 490695c1f7aaSFeifei Xu #define MMEA1_DRAM_RD_LAZY__GROUP1_DELAY_MASK 0x00000038L 490795c1f7aaSFeifei Xu #define MMEA1_DRAM_RD_LAZY__GROUP2_DELAY_MASK 0x000001C0L 490895c1f7aaSFeifei Xu #define MMEA1_DRAM_RD_LAZY__GROUP3_DELAY_MASK 0x00000E00L 490995c1f7aaSFeifei Xu //MMEA1_DRAM_WR_LAZY 491095c1f7aaSFeifei Xu #define MMEA1_DRAM_WR_LAZY__GROUP0_DELAY__SHIFT 0x0 491195c1f7aaSFeifei Xu #define MMEA1_DRAM_WR_LAZY__GROUP1_DELAY__SHIFT 0x3 491295c1f7aaSFeifei Xu #define MMEA1_DRAM_WR_LAZY__GROUP2_DELAY__SHIFT 0x6 491395c1f7aaSFeifei Xu #define MMEA1_DRAM_WR_LAZY__GROUP3_DELAY__SHIFT 0x9 491495c1f7aaSFeifei Xu #define MMEA1_DRAM_WR_LAZY__GROUP0_DELAY_MASK 0x00000007L 491595c1f7aaSFeifei Xu #define MMEA1_DRAM_WR_LAZY__GROUP1_DELAY_MASK 0x00000038L 491695c1f7aaSFeifei Xu #define MMEA1_DRAM_WR_LAZY__GROUP2_DELAY_MASK 0x000001C0L 491795c1f7aaSFeifei Xu #define MMEA1_DRAM_WR_LAZY__GROUP3_DELAY_MASK 0x00000E00L 491895c1f7aaSFeifei Xu //MMEA1_DRAM_RD_CAM_CNTL 491995c1f7aaSFeifei Xu #define MMEA1_DRAM_RD_CAM_CNTL__DEPTH_GROUP0__SHIFT 0x0 492095c1f7aaSFeifei Xu #define MMEA1_DRAM_RD_CAM_CNTL__DEPTH_GROUP1__SHIFT 0x4 492195c1f7aaSFeifei Xu #define MMEA1_DRAM_RD_CAM_CNTL__DEPTH_GROUP2__SHIFT 0x8 492295c1f7aaSFeifei Xu #define MMEA1_DRAM_RD_CAM_CNTL__DEPTH_GROUP3__SHIFT 0xc 492395c1f7aaSFeifei Xu #define MMEA1_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT 0x10 492495c1f7aaSFeifei Xu #define MMEA1_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT 0x13 492595c1f7aaSFeifei Xu #define MMEA1_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT 0x16 492695c1f7aaSFeifei Xu #define MMEA1_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT 0x19 492795c1f7aaSFeifei Xu #define MMEA1_DRAM_RD_CAM_CNTL__DEPTH_GROUP0_MASK 0x0000000FL 492895c1f7aaSFeifei Xu #define MMEA1_DRAM_RD_CAM_CNTL__DEPTH_GROUP1_MASK 0x000000F0L 492995c1f7aaSFeifei Xu #define MMEA1_DRAM_RD_CAM_CNTL__DEPTH_GROUP2_MASK 0x00000F00L 493095c1f7aaSFeifei Xu #define MMEA1_DRAM_RD_CAM_CNTL__DEPTH_GROUP3_MASK 0x0000F000L 493195c1f7aaSFeifei Xu #define MMEA1_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK 0x00070000L 493295c1f7aaSFeifei Xu #define MMEA1_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK 0x00380000L 493395c1f7aaSFeifei Xu #define MMEA1_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK 0x01C00000L 493495c1f7aaSFeifei Xu #define MMEA1_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK 0x0E000000L 493595c1f7aaSFeifei Xu //MMEA1_DRAM_WR_CAM_CNTL 493695c1f7aaSFeifei Xu #define MMEA1_DRAM_WR_CAM_CNTL__DEPTH_GROUP0__SHIFT 0x0 493795c1f7aaSFeifei Xu #define MMEA1_DRAM_WR_CAM_CNTL__DEPTH_GROUP1__SHIFT 0x4 493895c1f7aaSFeifei Xu #define MMEA1_DRAM_WR_CAM_CNTL__DEPTH_GROUP2__SHIFT 0x8 493995c1f7aaSFeifei Xu #define MMEA1_DRAM_WR_CAM_CNTL__DEPTH_GROUP3__SHIFT 0xc 494095c1f7aaSFeifei Xu #define MMEA1_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT 0x10 494195c1f7aaSFeifei Xu #define MMEA1_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT 0x13 494295c1f7aaSFeifei Xu #define MMEA1_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT 0x16 494395c1f7aaSFeifei Xu #define MMEA1_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT 0x19 494495c1f7aaSFeifei Xu #define MMEA1_DRAM_WR_CAM_CNTL__DEPTH_GROUP0_MASK 0x0000000FL 494595c1f7aaSFeifei Xu #define MMEA1_DRAM_WR_CAM_CNTL__DEPTH_GROUP1_MASK 0x000000F0L 494695c1f7aaSFeifei Xu #define MMEA1_DRAM_WR_CAM_CNTL__DEPTH_GROUP2_MASK 0x00000F00L 494795c1f7aaSFeifei Xu #define MMEA1_DRAM_WR_CAM_CNTL__DEPTH_GROUP3_MASK 0x0000F000L 494895c1f7aaSFeifei Xu #define MMEA1_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK 0x00070000L 494995c1f7aaSFeifei Xu #define MMEA1_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK 0x00380000L 495095c1f7aaSFeifei Xu #define MMEA1_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK 0x01C00000L 495195c1f7aaSFeifei Xu #define MMEA1_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK 0x0E000000L 495295c1f7aaSFeifei Xu //MMEA1_DRAM_PAGE_BURST 495395c1f7aaSFeifei Xu #define MMEA1_DRAM_PAGE_BURST__RD_LIMIT_LO__SHIFT 0x0 495495c1f7aaSFeifei Xu #define MMEA1_DRAM_PAGE_BURST__RD_LIMIT_HI__SHIFT 0x8 495595c1f7aaSFeifei Xu #define MMEA1_DRAM_PAGE_BURST__WR_LIMIT_LO__SHIFT 0x10 495695c1f7aaSFeifei Xu #define MMEA1_DRAM_PAGE_BURST__WR_LIMIT_HI__SHIFT 0x18 495795c1f7aaSFeifei Xu #define MMEA1_DRAM_PAGE_BURST__RD_LIMIT_LO_MASK 0x000000FFL 495895c1f7aaSFeifei Xu #define MMEA1_DRAM_PAGE_BURST__RD_LIMIT_HI_MASK 0x0000FF00L 495995c1f7aaSFeifei Xu #define MMEA1_DRAM_PAGE_BURST__WR_LIMIT_LO_MASK 0x00FF0000L 496095c1f7aaSFeifei Xu #define MMEA1_DRAM_PAGE_BURST__WR_LIMIT_HI_MASK 0xFF000000L 496195c1f7aaSFeifei Xu //MMEA1_DRAM_RD_PRI_AGE 496295c1f7aaSFeifei Xu #define MMEA1_DRAM_RD_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 496395c1f7aaSFeifei Xu #define MMEA1_DRAM_RD_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 496495c1f7aaSFeifei Xu #define MMEA1_DRAM_RD_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 496595c1f7aaSFeifei Xu #define MMEA1_DRAM_RD_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 496695c1f7aaSFeifei Xu #define MMEA1_DRAM_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc 496795c1f7aaSFeifei Xu #define MMEA1_DRAM_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf 496895c1f7aaSFeifei Xu #define MMEA1_DRAM_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 496995c1f7aaSFeifei Xu #define MMEA1_DRAM_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 497095c1f7aaSFeifei Xu #define MMEA1_DRAM_RD_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L 497195c1f7aaSFeifei Xu #define MMEA1_DRAM_RD_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L 497295c1f7aaSFeifei Xu #define MMEA1_DRAM_RD_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L 497395c1f7aaSFeifei Xu #define MMEA1_DRAM_RD_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L 497495c1f7aaSFeifei Xu #define MMEA1_DRAM_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L 497595c1f7aaSFeifei Xu #define MMEA1_DRAM_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L 497695c1f7aaSFeifei Xu #define MMEA1_DRAM_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L 497795c1f7aaSFeifei Xu #define MMEA1_DRAM_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L 497895c1f7aaSFeifei Xu //MMEA1_DRAM_WR_PRI_AGE 497995c1f7aaSFeifei Xu #define MMEA1_DRAM_WR_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 498095c1f7aaSFeifei Xu #define MMEA1_DRAM_WR_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 498195c1f7aaSFeifei Xu #define MMEA1_DRAM_WR_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 498295c1f7aaSFeifei Xu #define MMEA1_DRAM_WR_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 498395c1f7aaSFeifei Xu #define MMEA1_DRAM_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc 498495c1f7aaSFeifei Xu #define MMEA1_DRAM_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf 498595c1f7aaSFeifei Xu #define MMEA1_DRAM_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 498695c1f7aaSFeifei Xu #define MMEA1_DRAM_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 498795c1f7aaSFeifei Xu #define MMEA1_DRAM_WR_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L 498895c1f7aaSFeifei Xu #define MMEA1_DRAM_WR_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L 498995c1f7aaSFeifei Xu #define MMEA1_DRAM_WR_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L 499095c1f7aaSFeifei Xu #define MMEA1_DRAM_WR_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L 499195c1f7aaSFeifei Xu #define MMEA1_DRAM_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L 499295c1f7aaSFeifei Xu #define MMEA1_DRAM_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L 499395c1f7aaSFeifei Xu #define MMEA1_DRAM_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L 499495c1f7aaSFeifei Xu #define MMEA1_DRAM_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L 499595c1f7aaSFeifei Xu //MMEA1_DRAM_RD_PRI_QUEUING 499695c1f7aaSFeifei Xu #define MMEA1_DRAM_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 499795c1f7aaSFeifei Xu #define MMEA1_DRAM_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 499895c1f7aaSFeifei Xu #define MMEA1_DRAM_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 499995c1f7aaSFeifei Xu #define MMEA1_DRAM_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 500095c1f7aaSFeifei Xu #define MMEA1_DRAM_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L 500195c1f7aaSFeifei Xu #define MMEA1_DRAM_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L 500295c1f7aaSFeifei Xu #define MMEA1_DRAM_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L 500395c1f7aaSFeifei Xu #define MMEA1_DRAM_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L 500495c1f7aaSFeifei Xu //MMEA1_DRAM_WR_PRI_QUEUING 500595c1f7aaSFeifei Xu #define MMEA1_DRAM_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 500695c1f7aaSFeifei Xu #define MMEA1_DRAM_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 500795c1f7aaSFeifei Xu #define MMEA1_DRAM_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 500895c1f7aaSFeifei Xu #define MMEA1_DRAM_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 500995c1f7aaSFeifei Xu #define MMEA1_DRAM_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L 501095c1f7aaSFeifei Xu #define MMEA1_DRAM_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L 501195c1f7aaSFeifei Xu #define MMEA1_DRAM_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L 501295c1f7aaSFeifei Xu #define MMEA1_DRAM_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L 501395c1f7aaSFeifei Xu //MMEA1_DRAM_RD_PRI_FIXED 501495c1f7aaSFeifei Xu #define MMEA1_DRAM_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 501595c1f7aaSFeifei Xu #define MMEA1_DRAM_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 501695c1f7aaSFeifei Xu #define MMEA1_DRAM_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 501795c1f7aaSFeifei Xu #define MMEA1_DRAM_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 501895c1f7aaSFeifei Xu #define MMEA1_DRAM_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L 501995c1f7aaSFeifei Xu #define MMEA1_DRAM_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L 502095c1f7aaSFeifei Xu #define MMEA1_DRAM_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L 502195c1f7aaSFeifei Xu #define MMEA1_DRAM_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L 502295c1f7aaSFeifei Xu //MMEA1_DRAM_WR_PRI_FIXED 502395c1f7aaSFeifei Xu #define MMEA1_DRAM_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 502495c1f7aaSFeifei Xu #define MMEA1_DRAM_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 502595c1f7aaSFeifei Xu #define MMEA1_DRAM_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 502695c1f7aaSFeifei Xu #define MMEA1_DRAM_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 502795c1f7aaSFeifei Xu #define MMEA1_DRAM_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L 502895c1f7aaSFeifei Xu #define MMEA1_DRAM_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L 502995c1f7aaSFeifei Xu #define MMEA1_DRAM_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L 503095c1f7aaSFeifei Xu #define MMEA1_DRAM_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L 503195c1f7aaSFeifei Xu //MMEA1_DRAM_RD_PRI_URGENCY 503295c1f7aaSFeifei Xu #define MMEA1_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 503395c1f7aaSFeifei Xu #define MMEA1_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 503495c1f7aaSFeifei Xu #define MMEA1_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 503595c1f7aaSFeifei Xu #define MMEA1_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 503695c1f7aaSFeifei Xu #define MMEA1_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc 503795c1f7aaSFeifei Xu #define MMEA1_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd 503895c1f7aaSFeifei Xu #define MMEA1_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe 503995c1f7aaSFeifei Xu #define MMEA1_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf 504095c1f7aaSFeifei Xu #define MMEA1_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L 504195c1f7aaSFeifei Xu #define MMEA1_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L 504295c1f7aaSFeifei Xu #define MMEA1_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L 504395c1f7aaSFeifei Xu #define MMEA1_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L 504495c1f7aaSFeifei Xu #define MMEA1_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L 504595c1f7aaSFeifei Xu #define MMEA1_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L 504695c1f7aaSFeifei Xu #define MMEA1_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L 504795c1f7aaSFeifei Xu #define MMEA1_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L 504895c1f7aaSFeifei Xu //MMEA1_DRAM_WR_PRI_URGENCY 504995c1f7aaSFeifei Xu #define MMEA1_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 505095c1f7aaSFeifei Xu #define MMEA1_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 505195c1f7aaSFeifei Xu #define MMEA1_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 505295c1f7aaSFeifei Xu #define MMEA1_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 505395c1f7aaSFeifei Xu #define MMEA1_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc 505495c1f7aaSFeifei Xu #define MMEA1_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd 505595c1f7aaSFeifei Xu #define MMEA1_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe 505695c1f7aaSFeifei Xu #define MMEA1_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf 505795c1f7aaSFeifei Xu #define MMEA1_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L 505895c1f7aaSFeifei Xu #define MMEA1_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L 505995c1f7aaSFeifei Xu #define MMEA1_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L 506095c1f7aaSFeifei Xu #define MMEA1_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L 506195c1f7aaSFeifei Xu #define MMEA1_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L 506295c1f7aaSFeifei Xu #define MMEA1_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L 506395c1f7aaSFeifei Xu #define MMEA1_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L 506495c1f7aaSFeifei Xu #define MMEA1_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L 506595c1f7aaSFeifei Xu //MMEA1_DRAM_RD_PRI_QUANT_PRI1 506695c1f7aaSFeifei Xu #define MMEA1_DRAM_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 506795c1f7aaSFeifei Xu #define MMEA1_DRAM_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 506895c1f7aaSFeifei Xu #define MMEA1_DRAM_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 506995c1f7aaSFeifei Xu #define MMEA1_DRAM_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 507095c1f7aaSFeifei Xu #define MMEA1_DRAM_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL 507195c1f7aaSFeifei Xu #define MMEA1_DRAM_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L 507295c1f7aaSFeifei Xu #define MMEA1_DRAM_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L 507395c1f7aaSFeifei Xu #define MMEA1_DRAM_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L 507495c1f7aaSFeifei Xu //MMEA1_DRAM_RD_PRI_QUANT_PRI2 507595c1f7aaSFeifei Xu #define MMEA1_DRAM_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 507695c1f7aaSFeifei Xu #define MMEA1_DRAM_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 507795c1f7aaSFeifei Xu #define MMEA1_DRAM_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 507895c1f7aaSFeifei Xu #define MMEA1_DRAM_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 507995c1f7aaSFeifei Xu #define MMEA1_DRAM_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL 508095c1f7aaSFeifei Xu #define MMEA1_DRAM_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L 508195c1f7aaSFeifei Xu #define MMEA1_DRAM_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L 508295c1f7aaSFeifei Xu #define MMEA1_DRAM_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L 508395c1f7aaSFeifei Xu //MMEA1_DRAM_RD_PRI_QUANT_PRI3 508495c1f7aaSFeifei Xu #define MMEA1_DRAM_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 508595c1f7aaSFeifei Xu #define MMEA1_DRAM_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 508695c1f7aaSFeifei Xu #define MMEA1_DRAM_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 508795c1f7aaSFeifei Xu #define MMEA1_DRAM_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 508895c1f7aaSFeifei Xu #define MMEA1_DRAM_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL 508995c1f7aaSFeifei Xu #define MMEA1_DRAM_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L 509095c1f7aaSFeifei Xu #define MMEA1_DRAM_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L 509195c1f7aaSFeifei Xu #define MMEA1_DRAM_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L 509295c1f7aaSFeifei Xu //MMEA1_DRAM_WR_PRI_QUANT_PRI1 509395c1f7aaSFeifei Xu #define MMEA1_DRAM_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 509495c1f7aaSFeifei Xu #define MMEA1_DRAM_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 509595c1f7aaSFeifei Xu #define MMEA1_DRAM_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 509695c1f7aaSFeifei Xu #define MMEA1_DRAM_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 509795c1f7aaSFeifei Xu #define MMEA1_DRAM_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL 509895c1f7aaSFeifei Xu #define MMEA1_DRAM_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L 509995c1f7aaSFeifei Xu #define MMEA1_DRAM_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L 510095c1f7aaSFeifei Xu #define MMEA1_DRAM_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L 510195c1f7aaSFeifei Xu //MMEA1_DRAM_WR_PRI_QUANT_PRI2 510295c1f7aaSFeifei Xu #define MMEA1_DRAM_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 510395c1f7aaSFeifei Xu #define MMEA1_DRAM_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 510495c1f7aaSFeifei Xu #define MMEA1_DRAM_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 510595c1f7aaSFeifei Xu #define MMEA1_DRAM_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 510695c1f7aaSFeifei Xu #define MMEA1_DRAM_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL 510795c1f7aaSFeifei Xu #define MMEA1_DRAM_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L 510895c1f7aaSFeifei Xu #define MMEA1_DRAM_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L 510995c1f7aaSFeifei Xu #define MMEA1_DRAM_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L 511095c1f7aaSFeifei Xu //MMEA1_DRAM_WR_PRI_QUANT_PRI3 511195c1f7aaSFeifei Xu #define MMEA1_DRAM_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 511295c1f7aaSFeifei Xu #define MMEA1_DRAM_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 511395c1f7aaSFeifei Xu #define MMEA1_DRAM_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 511495c1f7aaSFeifei Xu #define MMEA1_DRAM_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 511595c1f7aaSFeifei Xu #define MMEA1_DRAM_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL 511695c1f7aaSFeifei Xu #define MMEA1_DRAM_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L 511795c1f7aaSFeifei Xu #define MMEA1_DRAM_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L 511895c1f7aaSFeifei Xu #define MMEA1_DRAM_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L 511995c1f7aaSFeifei Xu //MMEA1_ADDRNORM_BASE_ADDR0 512095c1f7aaSFeifei Xu #define MMEA1_ADDRNORM_BASE_ADDR0__ADDR_RNG_VAL__SHIFT 0x0 512195c1f7aaSFeifei Xu #define MMEA1_ADDRNORM_BASE_ADDR0__LGCY_MMIO_HOLE_EN__SHIFT 0x1 512295c1f7aaSFeifei Xu #define MMEA1_ADDRNORM_BASE_ADDR0__INTLV_NUM_CHAN__SHIFT 0x4 512395c1f7aaSFeifei Xu #define MMEA1_ADDRNORM_BASE_ADDR0__INTLV_ADDR_SEL__SHIFT 0x8 512495c1f7aaSFeifei Xu #define MMEA1_ADDRNORM_BASE_ADDR0__BASE_ADDR__SHIFT 0xc 512595c1f7aaSFeifei Xu #define MMEA1_ADDRNORM_BASE_ADDR0__ADDR_RNG_VAL_MASK 0x00000001L 512695c1f7aaSFeifei Xu #define MMEA1_ADDRNORM_BASE_ADDR0__LGCY_MMIO_HOLE_EN_MASK 0x00000002L 512795c1f7aaSFeifei Xu #define MMEA1_ADDRNORM_BASE_ADDR0__INTLV_NUM_CHAN_MASK 0x000000F0L 512895c1f7aaSFeifei Xu #define MMEA1_ADDRNORM_BASE_ADDR0__INTLV_ADDR_SEL_MASK 0x00000700L 512995c1f7aaSFeifei Xu #define MMEA1_ADDRNORM_BASE_ADDR0__BASE_ADDR_MASK 0xFFFFF000L 513095c1f7aaSFeifei Xu //MMEA1_ADDRNORM_LIMIT_ADDR0 513195c1f7aaSFeifei Xu #define MMEA1_ADDRNORM_LIMIT_ADDR0__DST_FABRIC_ID__SHIFT 0x0 513295c1f7aaSFeifei Xu #define MMEA1_ADDRNORM_LIMIT_ADDR0__INTLV_NUM_SOCKETS__SHIFT 0x8 513395c1f7aaSFeifei Xu #define MMEA1_ADDRNORM_LIMIT_ADDR0__INTLV_NUM_DIES__SHIFT 0xa 513495c1f7aaSFeifei Xu #define MMEA1_ADDRNORM_LIMIT_ADDR0__LIMIT_ADDR__SHIFT 0xc 513595c1f7aaSFeifei Xu #define MMEA1_ADDRNORM_LIMIT_ADDR0__DST_FABRIC_ID_MASK 0x0000000FL 513695c1f7aaSFeifei Xu #define MMEA1_ADDRNORM_LIMIT_ADDR0__INTLV_NUM_SOCKETS_MASK 0x00000100L 513795c1f7aaSFeifei Xu #define MMEA1_ADDRNORM_LIMIT_ADDR0__INTLV_NUM_DIES_MASK 0x00000C00L 513895c1f7aaSFeifei Xu #define MMEA1_ADDRNORM_LIMIT_ADDR0__LIMIT_ADDR_MASK 0xFFFFF000L 513995c1f7aaSFeifei Xu //MMEA1_ADDRNORM_BASE_ADDR1 514095c1f7aaSFeifei Xu #define MMEA1_ADDRNORM_BASE_ADDR1__ADDR_RNG_VAL__SHIFT 0x0 514195c1f7aaSFeifei Xu #define MMEA1_ADDRNORM_BASE_ADDR1__LGCY_MMIO_HOLE_EN__SHIFT 0x1 514295c1f7aaSFeifei Xu #define MMEA1_ADDRNORM_BASE_ADDR1__INTLV_NUM_CHAN__SHIFT 0x4 514395c1f7aaSFeifei Xu #define MMEA1_ADDRNORM_BASE_ADDR1__INTLV_ADDR_SEL__SHIFT 0x8 514495c1f7aaSFeifei Xu #define MMEA1_ADDRNORM_BASE_ADDR1__BASE_ADDR__SHIFT 0xc 514595c1f7aaSFeifei Xu #define MMEA1_ADDRNORM_BASE_ADDR1__ADDR_RNG_VAL_MASK 0x00000001L 514695c1f7aaSFeifei Xu #define MMEA1_ADDRNORM_BASE_ADDR1__LGCY_MMIO_HOLE_EN_MASK 0x00000002L 514795c1f7aaSFeifei Xu #define MMEA1_ADDRNORM_BASE_ADDR1__INTLV_NUM_CHAN_MASK 0x000000F0L 514895c1f7aaSFeifei Xu #define MMEA1_ADDRNORM_BASE_ADDR1__INTLV_ADDR_SEL_MASK 0x00000700L 514995c1f7aaSFeifei Xu #define MMEA1_ADDRNORM_BASE_ADDR1__BASE_ADDR_MASK 0xFFFFF000L 515095c1f7aaSFeifei Xu //MMEA1_ADDRNORM_LIMIT_ADDR1 515195c1f7aaSFeifei Xu #define MMEA1_ADDRNORM_LIMIT_ADDR1__DST_FABRIC_ID__SHIFT 0x0 515295c1f7aaSFeifei Xu #define MMEA1_ADDRNORM_LIMIT_ADDR1__INTLV_NUM_SOCKETS__SHIFT 0x8 515395c1f7aaSFeifei Xu #define MMEA1_ADDRNORM_LIMIT_ADDR1__INTLV_NUM_DIES__SHIFT 0xa 515495c1f7aaSFeifei Xu #define MMEA1_ADDRNORM_LIMIT_ADDR1__LIMIT_ADDR__SHIFT 0xc 515595c1f7aaSFeifei Xu #define MMEA1_ADDRNORM_LIMIT_ADDR1__DST_FABRIC_ID_MASK 0x0000000FL 515695c1f7aaSFeifei Xu #define MMEA1_ADDRNORM_LIMIT_ADDR1__INTLV_NUM_SOCKETS_MASK 0x00000100L 515795c1f7aaSFeifei Xu #define MMEA1_ADDRNORM_LIMIT_ADDR1__INTLV_NUM_DIES_MASK 0x00000C00L 515895c1f7aaSFeifei Xu #define MMEA1_ADDRNORM_LIMIT_ADDR1__LIMIT_ADDR_MASK 0xFFFFF000L 515995c1f7aaSFeifei Xu //MMEA1_ADDRNORM_OFFSET_ADDR1 516095c1f7aaSFeifei Xu #define MMEA1_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET_EN__SHIFT 0x0 516195c1f7aaSFeifei Xu #define MMEA1_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET__SHIFT 0x14 516295c1f7aaSFeifei Xu #define MMEA1_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET_EN_MASK 0x00000001L 516395c1f7aaSFeifei Xu #define MMEA1_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET_MASK 0xFFF00000L 516495c1f7aaSFeifei Xu //MMEA1_ADDRNORM_HOLE_CNTL 516595c1f7aaSFeifei Xu #define MMEA1_ADDRNORM_HOLE_CNTL__DRAM_HOLE_VALID__SHIFT 0x0 516695c1f7aaSFeifei Xu #define MMEA1_ADDRNORM_HOLE_CNTL__DRAM_HOLE_OFFSET__SHIFT 0x7 516795c1f7aaSFeifei Xu #define MMEA1_ADDRNORM_HOLE_CNTL__DRAM_HOLE_VALID_MASK 0x00000001L 516895c1f7aaSFeifei Xu #define MMEA1_ADDRNORM_HOLE_CNTL__DRAM_HOLE_OFFSET_MASK 0x0000FF80L 516995c1f7aaSFeifei Xu //MMEA1_ADDRDEC_BANK_CFG 517095c1f7aaSFeifei Xu #define MMEA1_ADDRDEC_BANK_CFG__BANK_MASK_DRAM__SHIFT 0x0 517195c1f7aaSFeifei Xu #define MMEA1_ADDRDEC_BANK_CFG__BANK_MASK_GMI__SHIFT 0x5 517295c1f7aaSFeifei Xu #define MMEA1_ADDRDEC_BANK_CFG__BANKGROUP_SEL_DRAM__SHIFT 0xa 517395c1f7aaSFeifei Xu #define MMEA1_ADDRDEC_BANK_CFG__BANKGROUP_SEL_GMI__SHIFT 0xd 517495c1f7aaSFeifei Xu #define MMEA1_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_DRAM__SHIFT 0x10 517595c1f7aaSFeifei Xu #define MMEA1_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_GMI__SHIFT 0x11 517695c1f7aaSFeifei Xu #define MMEA1_ADDRDEC_BANK_CFG__BANK_MASK_DRAM_MASK 0x0000001FL 517795c1f7aaSFeifei Xu #define MMEA1_ADDRDEC_BANK_CFG__BANK_MASK_GMI_MASK 0x000003E0L 517895c1f7aaSFeifei Xu #define MMEA1_ADDRDEC_BANK_CFG__BANKGROUP_SEL_DRAM_MASK 0x00001C00L 517995c1f7aaSFeifei Xu #define MMEA1_ADDRDEC_BANK_CFG__BANKGROUP_SEL_GMI_MASK 0x0000E000L 518095c1f7aaSFeifei Xu #define MMEA1_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_DRAM_MASK 0x00010000L 518195c1f7aaSFeifei Xu #define MMEA1_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_GMI_MASK 0x00020000L 518295c1f7aaSFeifei Xu //MMEA1_ADDRDEC_MISC_CFG 518395c1f7aaSFeifei Xu #define MMEA1_ADDRDEC_MISC_CFG__VCM_EN0__SHIFT 0x0 518495c1f7aaSFeifei Xu #define MMEA1_ADDRDEC_MISC_CFG__VCM_EN1__SHIFT 0x1 518595c1f7aaSFeifei Xu #define MMEA1_ADDRDEC_MISC_CFG__VCM_EN2__SHIFT 0x2 518695c1f7aaSFeifei Xu #define MMEA1_ADDRDEC_MISC_CFG__VCM_EN3__SHIFT 0x3 518795c1f7aaSFeifei Xu #define MMEA1_ADDRDEC_MISC_CFG__VCM_EN4__SHIFT 0x4 518895c1f7aaSFeifei Xu #define MMEA1_ADDRDEC_MISC_CFG__PCH_MASK_DRAM__SHIFT 0x8 518995c1f7aaSFeifei Xu #define MMEA1_ADDRDEC_MISC_CFG__PCH_MASK_GMI__SHIFT 0x9 519095c1f7aaSFeifei Xu #define MMEA1_ADDRDEC_MISC_CFG__CH_MASK_DRAM__SHIFT 0xc 519195c1f7aaSFeifei Xu #define MMEA1_ADDRDEC_MISC_CFG__CH_MASK_GMI__SHIFT 0x10 519295c1f7aaSFeifei Xu #define MMEA1_ADDRDEC_MISC_CFG__CS_MASK_DRAM__SHIFT 0x14 519395c1f7aaSFeifei Xu #define MMEA1_ADDRDEC_MISC_CFG__CS_MASK_GMI__SHIFT 0x16 519495c1f7aaSFeifei Xu #define MMEA1_ADDRDEC_MISC_CFG__RM_MASK_DRAM__SHIFT 0x18 519595c1f7aaSFeifei Xu #define MMEA1_ADDRDEC_MISC_CFG__RM_MASK_GMI__SHIFT 0x1b 519695c1f7aaSFeifei Xu #define MMEA1_ADDRDEC_MISC_CFG__VCM_EN0_MASK 0x00000001L 519795c1f7aaSFeifei Xu #define MMEA1_ADDRDEC_MISC_CFG__VCM_EN1_MASK 0x00000002L 519895c1f7aaSFeifei Xu #define MMEA1_ADDRDEC_MISC_CFG__VCM_EN2_MASK 0x00000004L 519995c1f7aaSFeifei Xu #define MMEA1_ADDRDEC_MISC_CFG__VCM_EN3_MASK 0x00000008L 520095c1f7aaSFeifei Xu #define MMEA1_ADDRDEC_MISC_CFG__VCM_EN4_MASK 0x00000010L 520195c1f7aaSFeifei Xu #define MMEA1_ADDRDEC_MISC_CFG__PCH_MASK_DRAM_MASK 0x00000100L 520295c1f7aaSFeifei Xu #define MMEA1_ADDRDEC_MISC_CFG__PCH_MASK_GMI_MASK 0x00000200L 520395c1f7aaSFeifei Xu #define MMEA1_ADDRDEC_MISC_CFG__CH_MASK_DRAM_MASK 0x0000F000L 520495c1f7aaSFeifei Xu #define MMEA1_ADDRDEC_MISC_CFG__CH_MASK_GMI_MASK 0x000F0000L 520595c1f7aaSFeifei Xu #define MMEA1_ADDRDEC_MISC_CFG__CS_MASK_DRAM_MASK 0x00300000L 520695c1f7aaSFeifei Xu #define MMEA1_ADDRDEC_MISC_CFG__CS_MASK_GMI_MASK 0x00C00000L 520795c1f7aaSFeifei Xu #define MMEA1_ADDRDEC_MISC_CFG__RM_MASK_DRAM_MASK 0x07000000L 520895c1f7aaSFeifei Xu #define MMEA1_ADDRDEC_MISC_CFG__RM_MASK_GMI_MASK 0x38000000L 520995c1f7aaSFeifei Xu //MMEA1_ADDRDECDRAM_ADDR_HASH_BANK0 521095c1f7aaSFeifei Xu #define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK0__XOR_ENABLE__SHIFT 0x0 521195c1f7aaSFeifei Xu #define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK0__COL_XOR__SHIFT 0x1 521295c1f7aaSFeifei Xu #define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK0__ROW_XOR__SHIFT 0xe 521395c1f7aaSFeifei Xu #define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK0__XOR_ENABLE_MASK 0x00000001L 521495c1f7aaSFeifei Xu #define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK0__COL_XOR_MASK 0x00003FFEL 521595c1f7aaSFeifei Xu #define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK0__ROW_XOR_MASK 0xFFFFC000L 521695c1f7aaSFeifei Xu //MMEA1_ADDRDECDRAM_ADDR_HASH_BANK1 521795c1f7aaSFeifei Xu #define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK1__XOR_ENABLE__SHIFT 0x0 521895c1f7aaSFeifei Xu #define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK1__COL_XOR__SHIFT 0x1 521995c1f7aaSFeifei Xu #define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK1__ROW_XOR__SHIFT 0xe 522095c1f7aaSFeifei Xu #define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK1__XOR_ENABLE_MASK 0x00000001L 522195c1f7aaSFeifei Xu #define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK1__COL_XOR_MASK 0x00003FFEL 522295c1f7aaSFeifei Xu #define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK1__ROW_XOR_MASK 0xFFFFC000L 522395c1f7aaSFeifei Xu //MMEA1_ADDRDECDRAM_ADDR_HASH_BANK2 522495c1f7aaSFeifei Xu #define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK2__XOR_ENABLE__SHIFT 0x0 522595c1f7aaSFeifei Xu #define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK2__COL_XOR__SHIFT 0x1 522695c1f7aaSFeifei Xu #define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK2__ROW_XOR__SHIFT 0xe 522795c1f7aaSFeifei Xu #define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK2__XOR_ENABLE_MASK 0x00000001L 522895c1f7aaSFeifei Xu #define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK2__COL_XOR_MASK 0x00003FFEL 522995c1f7aaSFeifei Xu #define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK2__ROW_XOR_MASK 0xFFFFC000L 523095c1f7aaSFeifei Xu //MMEA1_ADDRDECDRAM_ADDR_HASH_BANK3 523195c1f7aaSFeifei Xu #define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK3__XOR_ENABLE__SHIFT 0x0 523295c1f7aaSFeifei Xu #define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK3__COL_XOR__SHIFT 0x1 523395c1f7aaSFeifei Xu #define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK3__ROW_XOR__SHIFT 0xe 523495c1f7aaSFeifei Xu #define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK3__XOR_ENABLE_MASK 0x00000001L 523595c1f7aaSFeifei Xu #define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK3__COL_XOR_MASK 0x00003FFEL 523695c1f7aaSFeifei Xu #define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK3__ROW_XOR_MASK 0xFFFFC000L 523795c1f7aaSFeifei Xu //MMEA1_ADDRDECDRAM_ADDR_HASH_BANK4 523895c1f7aaSFeifei Xu #define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK4__XOR_ENABLE__SHIFT 0x0 523995c1f7aaSFeifei Xu #define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK4__COL_XOR__SHIFT 0x1 524095c1f7aaSFeifei Xu #define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK4__ROW_XOR__SHIFT 0xe 524195c1f7aaSFeifei Xu #define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK4__XOR_ENABLE_MASK 0x00000001L 524295c1f7aaSFeifei Xu #define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK4__COL_XOR_MASK 0x00003FFEL 524395c1f7aaSFeifei Xu #define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK4__ROW_XOR_MASK 0xFFFFC000L 524495c1f7aaSFeifei Xu //MMEA1_ADDRDECDRAM_ADDR_HASH_PC 524595c1f7aaSFeifei Xu #define MMEA1_ADDRDECDRAM_ADDR_HASH_PC__XOR_ENABLE__SHIFT 0x0 524695c1f7aaSFeifei Xu #define MMEA1_ADDRDECDRAM_ADDR_HASH_PC__COL_XOR__SHIFT 0x1 524795c1f7aaSFeifei Xu #define MMEA1_ADDRDECDRAM_ADDR_HASH_PC__ROW_XOR__SHIFT 0xe 524895c1f7aaSFeifei Xu #define MMEA1_ADDRDECDRAM_ADDR_HASH_PC__XOR_ENABLE_MASK 0x00000001L 524995c1f7aaSFeifei Xu #define MMEA1_ADDRDECDRAM_ADDR_HASH_PC__COL_XOR_MASK 0x00003FFEL 525095c1f7aaSFeifei Xu #define MMEA1_ADDRDECDRAM_ADDR_HASH_PC__ROW_XOR_MASK 0xFFFFC000L 525195c1f7aaSFeifei Xu //MMEA1_ADDRDECDRAM_ADDR_HASH_PC2 525295c1f7aaSFeifei Xu #define MMEA1_ADDRDECDRAM_ADDR_HASH_PC2__BANK_XOR__SHIFT 0x0 525395c1f7aaSFeifei Xu #define MMEA1_ADDRDECDRAM_ADDR_HASH_PC2__BANK_XOR_MASK 0x0000001FL 525495c1f7aaSFeifei Xu //MMEA1_ADDRDECDRAM_ADDR_HASH_CS0 525595c1f7aaSFeifei Xu #define MMEA1_ADDRDECDRAM_ADDR_HASH_CS0__XOR_ENABLE__SHIFT 0x0 525695c1f7aaSFeifei Xu #define MMEA1_ADDRDECDRAM_ADDR_HASH_CS0__NA_XOR__SHIFT 0x1 525795c1f7aaSFeifei Xu #define MMEA1_ADDRDECDRAM_ADDR_HASH_CS0__XOR_ENABLE_MASK 0x00000001L 525895c1f7aaSFeifei Xu #define MMEA1_ADDRDECDRAM_ADDR_HASH_CS0__NA_XOR_MASK 0xFFFFFFFEL 525995c1f7aaSFeifei Xu //MMEA1_ADDRDECDRAM_ADDR_HASH_CS1 526095c1f7aaSFeifei Xu #define MMEA1_ADDRDECDRAM_ADDR_HASH_CS1__XOR_ENABLE__SHIFT 0x0 526195c1f7aaSFeifei Xu #define MMEA1_ADDRDECDRAM_ADDR_HASH_CS1__NA_XOR__SHIFT 0x1 526295c1f7aaSFeifei Xu #define MMEA1_ADDRDECDRAM_ADDR_HASH_CS1__XOR_ENABLE_MASK 0x00000001L 526395c1f7aaSFeifei Xu #define MMEA1_ADDRDECDRAM_ADDR_HASH_CS1__NA_XOR_MASK 0xFFFFFFFEL 526495c1f7aaSFeifei Xu //MMEA1_ADDRDECDRAM_HARVEST_ENABLE 526595c1f7aaSFeifei Xu #define MMEA1_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_EN__SHIFT 0x0 526695c1f7aaSFeifei Xu #define MMEA1_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_VAL__SHIFT 0x1 526795c1f7aaSFeifei Xu #define MMEA1_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_EN__SHIFT 0x2 526895c1f7aaSFeifei Xu #define MMEA1_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_VAL__SHIFT 0x3 526995c1f7aaSFeifei Xu #define MMEA1_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_EN_MASK 0x00000001L 527095c1f7aaSFeifei Xu #define MMEA1_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_VAL_MASK 0x00000002L 527195c1f7aaSFeifei Xu #define MMEA1_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_EN_MASK 0x00000004L 527295c1f7aaSFeifei Xu #define MMEA1_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_VAL_MASK 0x00000008L 527395c1f7aaSFeifei Xu //MMEA1_ADDRDEC0_BASE_ADDR_CS0 527495c1f7aaSFeifei Xu #define MMEA1_ADDRDEC0_BASE_ADDR_CS0__CS_ENABLE__SHIFT 0x0 527595c1f7aaSFeifei Xu #define MMEA1_ADDRDEC0_BASE_ADDR_CS0__BASE_ADDR__SHIFT 0x1 527695c1f7aaSFeifei Xu #define MMEA1_ADDRDEC0_BASE_ADDR_CS0__CS_ENABLE_MASK 0x00000001L 527795c1f7aaSFeifei Xu #define MMEA1_ADDRDEC0_BASE_ADDR_CS0__BASE_ADDR_MASK 0xFFFFFFFEL 527895c1f7aaSFeifei Xu //MMEA1_ADDRDEC0_BASE_ADDR_CS1 527995c1f7aaSFeifei Xu #define MMEA1_ADDRDEC0_BASE_ADDR_CS1__CS_ENABLE__SHIFT 0x0 528095c1f7aaSFeifei Xu #define MMEA1_ADDRDEC0_BASE_ADDR_CS1__BASE_ADDR__SHIFT 0x1 528195c1f7aaSFeifei Xu #define MMEA1_ADDRDEC0_BASE_ADDR_CS1__CS_ENABLE_MASK 0x00000001L 528295c1f7aaSFeifei Xu #define MMEA1_ADDRDEC0_BASE_ADDR_CS1__BASE_ADDR_MASK 0xFFFFFFFEL 528395c1f7aaSFeifei Xu //MMEA1_ADDRDEC0_BASE_ADDR_CS2 528495c1f7aaSFeifei Xu #define MMEA1_ADDRDEC0_BASE_ADDR_CS2__CS_ENABLE__SHIFT 0x0 528595c1f7aaSFeifei Xu #define MMEA1_ADDRDEC0_BASE_ADDR_CS2__BASE_ADDR__SHIFT 0x1 528695c1f7aaSFeifei Xu #define MMEA1_ADDRDEC0_BASE_ADDR_CS2__CS_ENABLE_MASK 0x00000001L 528795c1f7aaSFeifei Xu #define MMEA1_ADDRDEC0_BASE_ADDR_CS2__BASE_ADDR_MASK 0xFFFFFFFEL 528895c1f7aaSFeifei Xu //MMEA1_ADDRDEC0_BASE_ADDR_CS3 528995c1f7aaSFeifei Xu #define MMEA1_ADDRDEC0_BASE_ADDR_CS3__CS_ENABLE__SHIFT 0x0 529095c1f7aaSFeifei Xu #define MMEA1_ADDRDEC0_BASE_ADDR_CS3__BASE_ADDR__SHIFT 0x1 529195c1f7aaSFeifei Xu #define MMEA1_ADDRDEC0_BASE_ADDR_CS3__CS_ENABLE_MASK 0x00000001L 529295c1f7aaSFeifei Xu #define MMEA1_ADDRDEC0_BASE_ADDR_CS3__BASE_ADDR_MASK 0xFFFFFFFEL 529395c1f7aaSFeifei Xu //MMEA1_ADDRDEC0_BASE_ADDR_SECCS0 529495c1f7aaSFeifei Xu #define MMEA1_ADDRDEC0_BASE_ADDR_SECCS0__CS_ENABLE__SHIFT 0x0 529595c1f7aaSFeifei Xu #define MMEA1_ADDRDEC0_BASE_ADDR_SECCS0__BASE_ADDR__SHIFT 0x1 529695c1f7aaSFeifei Xu #define MMEA1_ADDRDEC0_BASE_ADDR_SECCS0__CS_ENABLE_MASK 0x00000001L 529795c1f7aaSFeifei Xu #define MMEA1_ADDRDEC0_BASE_ADDR_SECCS0__BASE_ADDR_MASK 0xFFFFFFFEL 529895c1f7aaSFeifei Xu //MMEA1_ADDRDEC0_BASE_ADDR_SECCS1 529995c1f7aaSFeifei Xu #define MMEA1_ADDRDEC0_BASE_ADDR_SECCS1__CS_ENABLE__SHIFT 0x0 530095c1f7aaSFeifei Xu #define MMEA1_ADDRDEC0_BASE_ADDR_SECCS1__BASE_ADDR__SHIFT 0x1 530195c1f7aaSFeifei Xu #define MMEA1_ADDRDEC0_BASE_ADDR_SECCS1__CS_ENABLE_MASK 0x00000001L 530295c1f7aaSFeifei Xu #define MMEA1_ADDRDEC0_BASE_ADDR_SECCS1__BASE_ADDR_MASK 0xFFFFFFFEL 530395c1f7aaSFeifei Xu //MMEA1_ADDRDEC0_BASE_ADDR_SECCS2 530495c1f7aaSFeifei Xu #define MMEA1_ADDRDEC0_BASE_ADDR_SECCS2__CS_ENABLE__SHIFT 0x0 530595c1f7aaSFeifei Xu #define MMEA1_ADDRDEC0_BASE_ADDR_SECCS2__BASE_ADDR__SHIFT 0x1 530695c1f7aaSFeifei Xu #define MMEA1_ADDRDEC0_BASE_ADDR_SECCS2__CS_ENABLE_MASK 0x00000001L 530795c1f7aaSFeifei Xu #define MMEA1_ADDRDEC0_BASE_ADDR_SECCS2__BASE_ADDR_MASK 0xFFFFFFFEL 530895c1f7aaSFeifei Xu //MMEA1_ADDRDEC0_BASE_ADDR_SECCS3 530995c1f7aaSFeifei Xu #define MMEA1_ADDRDEC0_BASE_ADDR_SECCS3__CS_ENABLE__SHIFT 0x0 531095c1f7aaSFeifei Xu #define MMEA1_ADDRDEC0_BASE_ADDR_SECCS3__BASE_ADDR__SHIFT 0x1 531195c1f7aaSFeifei Xu #define MMEA1_ADDRDEC0_BASE_ADDR_SECCS3__CS_ENABLE_MASK 0x00000001L 531295c1f7aaSFeifei Xu #define MMEA1_ADDRDEC0_BASE_ADDR_SECCS3__BASE_ADDR_MASK 0xFFFFFFFEL 531395c1f7aaSFeifei Xu //MMEA1_ADDRDEC0_ADDR_MASK_CS01 531495c1f7aaSFeifei Xu #define MMEA1_ADDRDEC0_ADDR_MASK_CS01__ADDR_MASK__SHIFT 0x1 531595c1f7aaSFeifei Xu #define MMEA1_ADDRDEC0_ADDR_MASK_CS01__ADDR_MASK_MASK 0xFFFFFFFEL 531695c1f7aaSFeifei Xu //MMEA1_ADDRDEC0_ADDR_MASK_CS23 531795c1f7aaSFeifei Xu #define MMEA1_ADDRDEC0_ADDR_MASK_CS23__ADDR_MASK__SHIFT 0x1 531895c1f7aaSFeifei Xu #define MMEA1_ADDRDEC0_ADDR_MASK_CS23__ADDR_MASK_MASK 0xFFFFFFFEL 531995c1f7aaSFeifei Xu //MMEA1_ADDRDEC0_ADDR_MASK_SECCS01 532095c1f7aaSFeifei Xu #define MMEA1_ADDRDEC0_ADDR_MASK_SECCS01__ADDR_MASK__SHIFT 0x1 532195c1f7aaSFeifei Xu #define MMEA1_ADDRDEC0_ADDR_MASK_SECCS01__ADDR_MASK_MASK 0xFFFFFFFEL 532295c1f7aaSFeifei Xu //MMEA1_ADDRDEC0_ADDR_MASK_SECCS23 532395c1f7aaSFeifei Xu #define MMEA1_ADDRDEC0_ADDR_MASK_SECCS23__ADDR_MASK__SHIFT 0x1 532495c1f7aaSFeifei Xu #define MMEA1_ADDRDEC0_ADDR_MASK_SECCS23__ADDR_MASK_MASK 0xFFFFFFFEL 532595c1f7aaSFeifei Xu //MMEA1_ADDRDEC0_ADDR_CFG_CS01 532695c1f7aaSFeifei Xu #define MMEA1_ADDRDEC0_ADDR_CFG_CS01__NUM_BANK_GROUPS__SHIFT 0x2 532795c1f7aaSFeifei Xu #define MMEA1_ADDRDEC0_ADDR_CFG_CS01__NUM_RM__SHIFT 0x4 532895c1f7aaSFeifei Xu #define MMEA1_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_LO__SHIFT 0x8 532995c1f7aaSFeifei Xu #define MMEA1_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_HI__SHIFT 0xc 533095c1f7aaSFeifei Xu #define MMEA1_ADDRDEC0_ADDR_CFG_CS01__NUM_COL__SHIFT 0x10 533195c1f7aaSFeifei Xu #define MMEA1_ADDRDEC0_ADDR_CFG_CS01__NUM_BANKS__SHIFT 0x14 533295c1f7aaSFeifei Xu #define MMEA1_ADDRDEC0_ADDR_CFG_CS01__NUM_BANK_GROUPS_MASK 0x0000000CL 533395c1f7aaSFeifei Xu #define MMEA1_ADDRDEC0_ADDR_CFG_CS01__NUM_RM_MASK 0x00000030L 533495c1f7aaSFeifei Xu #define MMEA1_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_LO_MASK 0x00000F00L 533595c1f7aaSFeifei Xu #define MMEA1_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_HI_MASK 0x0000F000L 533695c1f7aaSFeifei Xu #define MMEA1_ADDRDEC0_ADDR_CFG_CS01__NUM_COL_MASK 0x000F0000L 533795c1f7aaSFeifei Xu #define MMEA1_ADDRDEC0_ADDR_CFG_CS01__NUM_BANKS_MASK 0x00300000L 533895c1f7aaSFeifei Xu //MMEA1_ADDRDEC0_ADDR_CFG_CS23 533995c1f7aaSFeifei Xu #define MMEA1_ADDRDEC0_ADDR_CFG_CS23__NUM_BANK_GROUPS__SHIFT 0x2 534095c1f7aaSFeifei Xu #define MMEA1_ADDRDEC0_ADDR_CFG_CS23__NUM_RM__SHIFT 0x4 534195c1f7aaSFeifei Xu #define MMEA1_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_LO__SHIFT 0x8 534295c1f7aaSFeifei Xu #define MMEA1_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_HI__SHIFT 0xc 534395c1f7aaSFeifei Xu #define MMEA1_ADDRDEC0_ADDR_CFG_CS23__NUM_COL__SHIFT 0x10 534495c1f7aaSFeifei Xu #define MMEA1_ADDRDEC0_ADDR_CFG_CS23__NUM_BANKS__SHIFT 0x14 534595c1f7aaSFeifei Xu #define MMEA1_ADDRDEC0_ADDR_CFG_CS23__NUM_BANK_GROUPS_MASK 0x0000000CL 534695c1f7aaSFeifei Xu #define MMEA1_ADDRDEC0_ADDR_CFG_CS23__NUM_RM_MASK 0x00000030L 534795c1f7aaSFeifei Xu #define MMEA1_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_LO_MASK 0x00000F00L 534895c1f7aaSFeifei Xu #define MMEA1_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_HI_MASK 0x0000F000L 534995c1f7aaSFeifei Xu #define MMEA1_ADDRDEC0_ADDR_CFG_CS23__NUM_COL_MASK 0x000F0000L 535095c1f7aaSFeifei Xu #define MMEA1_ADDRDEC0_ADDR_CFG_CS23__NUM_BANKS_MASK 0x00300000L 535195c1f7aaSFeifei Xu //MMEA1_ADDRDEC0_ADDR_SEL_CS01 535295c1f7aaSFeifei Xu #define MMEA1_ADDRDEC0_ADDR_SEL_CS01__BANK0__SHIFT 0x0 535395c1f7aaSFeifei Xu #define MMEA1_ADDRDEC0_ADDR_SEL_CS01__BANK1__SHIFT 0x4 535495c1f7aaSFeifei Xu #define MMEA1_ADDRDEC0_ADDR_SEL_CS01__BANK2__SHIFT 0x8 535595c1f7aaSFeifei Xu #define MMEA1_ADDRDEC0_ADDR_SEL_CS01__BANK3__SHIFT 0xc 535695c1f7aaSFeifei Xu #define MMEA1_ADDRDEC0_ADDR_SEL_CS01__BANK4__SHIFT 0x10 535795c1f7aaSFeifei Xu #define MMEA1_ADDRDEC0_ADDR_SEL_CS01__ROW_LO__SHIFT 0x18 535895c1f7aaSFeifei Xu #define MMEA1_ADDRDEC0_ADDR_SEL_CS01__ROW_HI__SHIFT 0x1c 535995c1f7aaSFeifei Xu #define MMEA1_ADDRDEC0_ADDR_SEL_CS01__BANK0_MASK 0x0000000FL 536095c1f7aaSFeifei Xu #define MMEA1_ADDRDEC0_ADDR_SEL_CS01__BANK1_MASK 0x000000F0L 536195c1f7aaSFeifei Xu #define MMEA1_ADDRDEC0_ADDR_SEL_CS01__BANK2_MASK 0x00000F00L 536295c1f7aaSFeifei Xu #define MMEA1_ADDRDEC0_ADDR_SEL_CS01__BANK3_MASK 0x0000F000L 536395c1f7aaSFeifei Xu #define MMEA1_ADDRDEC0_ADDR_SEL_CS01__BANK4_MASK 0x000F0000L 536495c1f7aaSFeifei Xu #define MMEA1_ADDRDEC0_ADDR_SEL_CS01__ROW_LO_MASK 0x0F000000L 536595c1f7aaSFeifei Xu #define MMEA1_ADDRDEC0_ADDR_SEL_CS01__ROW_HI_MASK 0xF0000000L 536695c1f7aaSFeifei Xu //MMEA1_ADDRDEC0_ADDR_SEL_CS23 536795c1f7aaSFeifei Xu #define MMEA1_ADDRDEC0_ADDR_SEL_CS23__BANK0__SHIFT 0x0 536895c1f7aaSFeifei Xu #define MMEA1_ADDRDEC0_ADDR_SEL_CS23__BANK1__SHIFT 0x4 536995c1f7aaSFeifei Xu #define MMEA1_ADDRDEC0_ADDR_SEL_CS23__BANK2__SHIFT 0x8 537095c1f7aaSFeifei Xu #define MMEA1_ADDRDEC0_ADDR_SEL_CS23__BANK3__SHIFT 0xc 537195c1f7aaSFeifei Xu #define MMEA1_ADDRDEC0_ADDR_SEL_CS23__BANK4__SHIFT 0x10 537295c1f7aaSFeifei Xu #define MMEA1_ADDRDEC0_ADDR_SEL_CS23__ROW_LO__SHIFT 0x18 537395c1f7aaSFeifei Xu #define MMEA1_ADDRDEC0_ADDR_SEL_CS23__ROW_HI__SHIFT 0x1c 537495c1f7aaSFeifei Xu #define MMEA1_ADDRDEC0_ADDR_SEL_CS23__BANK0_MASK 0x0000000FL 537595c1f7aaSFeifei Xu #define MMEA1_ADDRDEC0_ADDR_SEL_CS23__BANK1_MASK 0x000000F0L 537695c1f7aaSFeifei Xu #define MMEA1_ADDRDEC0_ADDR_SEL_CS23__BANK2_MASK 0x00000F00L 537795c1f7aaSFeifei Xu #define MMEA1_ADDRDEC0_ADDR_SEL_CS23__BANK3_MASK 0x0000F000L 537895c1f7aaSFeifei Xu #define MMEA1_ADDRDEC0_ADDR_SEL_CS23__BANK4_MASK 0x000F0000L 537995c1f7aaSFeifei Xu #define MMEA1_ADDRDEC0_ADDR_SEL_CS23__ROW_LO_MASK 0x0F000000L 538095c1f7aaSFeifei Xu #define MMEA1_ADDRDEC0_ADDR_SEL_CS23__ROW_HI_MASK 0xF0000000L 538195c1f7aaSFeifei Xu //MMEA1_ADDRDEC0_COL_SEL_LO_CS01 538295c1f7aaSFeifei Xu #define MMEA1_ADDRDEC0_COL_SEL_LO_CS01__COL0__SHIFT 0x0 538395c1f7aaSFeifei Xu #define MMEA1_ADDRDEC0_COL_SEL_LO_CS01__COL1__SHIFT 0x4 538495c1f7aaSFeifei Xu #define MMEA1_ADDRDEC0_COL_SEL_LO_CS01__COL2__SHIFT 0x8 538595c1f7aaSFeifei Xu #define MMEA1_ADDRDEC0_COL_SEL_LO_CS01__COL3__SHIFT 0xc 538695c1f7aaSFeifei Xu #define MMEA1_ADDRDEC0_COL_SEL_LO_CS01__COL4__SHIFT 0x10 538795c1f7aaSFeifei Xu #define MMEA1_ADDRDEC0_COL_SEL_LO_CS01__COL5__SHIFT 0x14 538895c1f7aaSFeifei Xu #define MMEA1_ADDRDEC0_COL_SEL_LO_CS01__COL6__SHIFT 0x18 538995c1f7aaSFeifei Xu #define MMEA1_ADDRDEC0_COL_SEL_LO_CS01__COL7__SHIFT 0x1c 539095c1f7aaSFeifei Xu #define MMEA1_ADDRDEC0_COL_SEL_LO_CS01__COL0_MASK 0x0000000FL 539195c1f7aaSFeifei Xu #define MMEA1_ADDRDEC0_COL_SEL_LO_CS01__COL1_MASK 0x000000F0L 539295c1f7aaSFeifei Xu #define MMEA1_ADDRDEC0_COL_SEL_LO_CS01__COL2_MASK 0x00000F00L 539395c1f7aaSFeifei Xu #define MMEA1_ADDRDEC0_COL_SEL_LO_CS01__COL3_MASK 0x0000F000L 539495c1f7aaSFeifei Xu #define MMEA1_ADDRDEC0_COL_SEL_LO_CS01__COL4_MASK 0x000F0000L 539595c1f7aaSFeifei Xu #define MMEA1_ADDRDEC0_COL_SEL_LO_CS01__COL5_MASK 0x00F00000L 539695c1f7aaSFeifei Xu #define MMEA1_ADDRDEC0_COL_SEL_LO_CS01__COL6_MASK 0x0F000000L 539795c1f7aaSFeifei Xu #define MMEA1_ADDRDEC0_COL_SEL_LO_CS01__COL7_MASK 0xF0000000L 539895c1f7aaSFeifei Xu //MMEA1_ADDRDEC0_COL_SEL_LO_CS23 539995c1f7aaSFeifei Xu #define MMEA1_ADDRDEC0_COL_SEL_LO_CS23__COL0__SHIFT 0x0 540095c1f7aaSFeifei Xu #define MMEA1_ADDRDEC0_COL_SEL_LO_CS23__COL1__SHIFT 0x4 540195c1f7aaSFeifei Xu #define MMEA1_ADDRDEC0_COL_SEL_LO_CS23__COL2__SHIFT 0x8 540295c1f7aaSFeifei Xu #define MMEA1_ADDRDEC0_COL_SEL_LO_CS23__COL3__SHIFT 0xc 540395c1f7aaSFeifei Xu #define MMEA1_ADDRDEC0_COL_SEL_LO_CS23__COL4__SHIFT 0x10 540495c1f7aaSFeifei Xu #define MMEA1_ADDRDEC0_COL_SEL_LO_CS23__COL5__SHIFT 0x14 540595c1f7aaSFeifei Xu #define MMEA1_ADDRDEC0_COL_SEL_LO_CS23__COL6__SHIFT 0x18 540695c1f7aaSFeifei Xu #define MMEA1_ADDRDEC0_COL_SEL_LO_CS23__COL7__SHIFT 0x1c 540795c1f7aaSFeifei Xu #define MMEA1_ADDRDEC0_COL_SEL_LO_CS23__COL0_MASK 0x0000000FL 540895c1f7aaSFeifei Xu #define MMEA1_ADDRDEC0_COL_SEL_LO_CS23__COL1_MASK 0x000000F0L 540995c1f7aaSFeifei Xu #define MMEA1_ADDRDEC0_COL_SEL_LO_CS23__COL2_MASK 0x00000F00L 541095c1f7aaSFeifei Xu #define MMEA1_ADDRDEC0_COL_SEL_LO_CS23__COL3_MASK 0x0000F000L 541195c1f7aaSFeifei Xu #define MMEA1_ADDRDEC0_COL_SEL_LO_CS23__COL4_MASK 0x000F0000L 541295c1f7aaSFeifei Xu #define MMEA1_ADDRDEC0_COL_SEL_LO_CS23__COL5_MASK 0x00F00000L 541395c1f7aaSFeifei Xu #define MMEA1_ADDRDEC0_COL_SEL_LO_CS23__COL6_MASK 0x0F000000L 541495c1f7aaSFeifei Xu #define MMEA1_ADDRDEC0_COL_SEL_LO_CS23__COL7_MASK 0xF0000000L 541595c1f7aaSFeifei Xu //MMEA1_ADDRDEC0_COL_SEL_HI_CS01 541695c1f7aaSFeifei Xu #define MMEA1_ADDRDEC0_COL_SEL_HI_CS01__COL8__SHIFT 0x0 541795c1f7aaSFeifei Xu #define MMEA1_ADDRDEC0_COL_SEL_HI_CS01__COL9__SHIFT 0x4 541895c1f7aaSFeifei Xu #define MMEA1_ADDRDEC0_COL_SEL_HI_CS01__COL10__SHIFT 0x8 541995c1f7aaSFeifei Xu #define MMEA1_ADDRDEC0_COL_SEL_HI_CS01__COL11__SHIFT 0xc 542095c1f7aaSFeifei Xu #define MMEA1_ADDRDEC0_COL_SEL_HI_CS01__COL12__SHIFT 0x10 542195c1f7aaSFeifei Xu #define MMEA1_ADDRDEC0_COL_SEL_HI_CS01__COL13__SHIFT 0x14 542295c1f7aaSFeifei Xu #define MMEA1_ADDRDEC0_COL_SEL_HI_CS01__COL14__SHIFT 0x18 542395c1f7aaSFeifei Xu #define MMEA1_ADDRDEC0_COL_SEL_HI_CS01__COL15__SHIFT 0x1c 542495c1f7aaSFeifei Xu #define MMEA1_ADDRDEC0_COL_SEL_HI_CS01__COL8_MASK 0x0000000FL 542595c1f7aaSFeifei Xu #define MMEA1_ADDRDEC0_COL_SEL_HI_CS01__COL9_MASK 0x000000F0L 542695c1f7aaSFeifei Xu #define MMEA1_ADDRDEC0_COL_SEL_HI_CS01__COL10_MASK 0x00000F00L 542795c1f7aaSFeifei Xu #define MMEA1_ADDRDEC0_COL_SEL_HI_CS01__COL11_MASK 0x0000F000L 542895c1f7aaSFeifei Xu #define MMEA1_ADDRDEC0_COL_SEL_HI_CS01__COL12_MASK 0x000F0000L 542995c1f7aaSFeifei Xu #define MMEA1_ADDRDEC0_COL_SEL_HI_CS01__COL13_MASK 0x00F00000L 543095c1f7aaSFeifei Xu #define MMEA1_ADDRDEC0_COL_SEL_HI_CS01__COL14_MASK 0x0F000000L 543195c1f7aaSFeifei Xu #define MMEA1_ADDRDEC0_COL_SEL_HI_CS01__COL15_MASK 0xF0000000L 543295c1f7aaSFeifei Xu //MMEA1_ADDRDEC0_COL_SEL_HI_CS23 543395c1f7aaSFeifei Xu #define MMEA1_ADDRDEC0_COL_SEL_HI_CS23__COL8__SHIFT 0x0 543495c1f7aaSFeifei Xu #define MMEA1_ADDRDEC0_COL_SEL_HI_CS23__COL9__SHIFT 0x4 543595c1f7aaSFeifei Xu #define MMEA1_ADDRDEC0_COL_SEL_HI_CS23__COL10__SHIFT 0x8 543695c1f7aaSFeifei Xu #define MMEA1_ADDRDEC0_COL_SEL_HI_CS23__COL11__SHIFT 0xc 543795c1f7aaSFeifei Xu #define MMEA1_ADDRDEC0_COL_SEL_HI_CS23__COL12__SHIFT 0x10 543895c1f7aaSFeifei Xu #define MMEA1_ADDRDEC0_COL_SEL_HI_CS23__COL13__SHIFT 0x14 543995c1f7aaSFeifei Xu #define MMEA1_ADDRDEC0_COL_SEL_HI_CS23__COL14__SHIFT 0x18 544095c1f7aaSFeifei Xu #define MMEA1_ADDRDEC0_COL_SEL_HI_CS23__COL15__SHIFT 0x1c 544195c1f7aaSFeifei Xu #define MMEA1_ADDRDEC0_COL_SEL_HI_CS23__COL8_MASK 0x0000000FL 544295c1f7aaSFeifei Xu #define MMEA1_ADDRDEC0_COL_SEL_HI_CS23__COL9_MASK 0x000000F0L 544395c1f7aaSFeifei Xu #define MMEA1_ADDRDEC0_COL_SEL_HI_CS23__COL10_MASK 0x00000F00L 544495c1f7aaSFeifei Xu #define MMEA1_ADDRDEC0_COL_SEL_HI_CS23__COL11_MASK 0x0000F000L 544595c1f7aaSFeifei Xu #define MMEA1_ADDRDEC0_COL_SEL_HI_CS23__COL12_MASK 0x000F0000L 544695c1f7aaSFeifei Xu #define MMEA1_ADDRDEC0_COL_SEL_HI_CS23__COL13_MASK 0x00F00000L 544795c1f7aaSFeifei Xu #define MMEA1_ADDRDEC0_COL_SEL_HI_CS23__COL14_MASK 0x0F000000L 544895c1f7aaSFeifei Xu #define MMEA1_ADDRDEC0_COL_SEL_HI_CS23__COL15_MASK 0xF0000000L 544995c1f7aaSFeifei Xu //MMEA1_ADDRDEC0_RM_SEL_CS01 545095c1f7aaSFeifei Xu #define MMEA1_ADDRDEC0_RM_SEL_CS01__RM0__SHIFT 0x0 545195c1f7aaSFeifei Xu #define MMEA1_ADDRDEC0_RM_SEL_CS01__RM1__SHIFT 0x4 545295c1f7aaSFeifei Xu #define MMEA1_ADDRDEC0_RM_SEL_CS01__RM2__SHIFT 0x8 545395c1f7aaSFeifei Xu #define MMEA1_ADDRDEC0_RM_SEL_CS01__CHAN_BIT__SHIFT 0xc 545495c1f7aaSFeifei Xu #define MMEA1_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 545595c1f7aaSFeifei Xu #define MMEA1_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12 545695c1f7aaSFeifei Xu #define MMEA1_ADDRDEC0_RM_SEL_CS01__RM0_MASK 0x0000000FL 545795c1f7aaSFeifei Xu #define MMEA1_ADDRDEC0_RM_SEL_CS01__RM1_MASK 0x000000F0L 545895c1f7aaSFeifei Xu #define MMEA1_ADDRDEC0_RM_SEL_CS01__RM2_MASK 0x00000F00L 545995c1f7aaSFeifei Xu #define MMEA1_ADDRDEC0_RM_SEL_CS01__CHAN_BIT_MASK 0x0000F000L 546095c1f7aaSFeifei Xu #define MMEA1_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L 546195c1f7aaSFeifei Xu #define MMEA1_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L 546295c1f7aaSFeifei Xu //MMEA1_ADDRDEC0_RM_SEL_CS23 546395c1f7aaSFeifei Xu #define MMEA1_ADDRDEC0_RM_SEL_CS23__RM0__SHIFT 0x0 546495c1f7aaSFeifei Xu #define MMEA1_ADDRDEC0_RM_SEL_CS23__RM1__SHIFT 0x4 546595c1f7aaSFeifei Xu #define MMEA1_ADDRDEC0_RM_SEL_CS23__RM2__SHIFT 0x8 546695c1f7aaSFeifei Xu #define MMEA1_ADDRDEC0_RM_SEL_CS23__CHAN_BIT__SHIFT 0xc 546795c1f7aaSFeifei Xu #define MMEA1_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 546895c1f7aaSFeifei Xu #define MMEA1_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12 546995c1f7aaSFeifei Xu #define MMEA1_ADDRDEC0_RM_SEL_CS23__RM0_MASK 0x0000000FL 547095c1f7aaSFeifei Xu #define MMEA1_ADDRDEC0_RM_SEL_CS23__RM1_MASK 0x000000F0L 547195c1f7aaSFeifei Xu #define MMEA1_ADDRDEC0_RM_SEL_CS23__RM2_MASK 0x00000F00L 547295c1f7aaSFeifei Xu #define MMEA1_ADDRDEC0_RM_SEL_CS23__CHAN_BIT_MASK 0x0000F000L 547395c1f7aaSFeifei Xu #define MMEA1_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L 547495c1f7aaSFeifei Xu #define MMEA1_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L 547595c1f7aaSFeifei Xu //MMEA1_ADDRDEC0_RM_SEL_SECCS01 547695c1f7aaSFeifei Xu #define MMEA1_ADDRDEC0_RM_SEL_SECCS01__RM0__SHIFT 0x0 547795c1f7aaSFeifei Xu #define MMEA1_ADDRDEC0_RM_SEL_SECCS01__RM1__SHIFT 0x4 547895c1f7aaSFeifei Xu #define MMEA1_ADDRDEC0_RM_SEL_SECCS01__RM2__SHIFT 0x8 547995c1f7aaSFeifei Xu #define MMEA1_ADDRDEC0_RM_SEL_SECCS01__CHAN_BIT__SHIFT 0xc 548095c1f7aaSFeifei Xu #define MMEA1_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 548195c1f7aaSFeifei Xu #define MMEA1_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12 548295c1f7aaSFeifei Xu #define MMEA1_ADDRDEC0_RM_SEL_SECCS01__RM0_MASK 0x0000000FL 548395c1f7aaSFeifei Xu #define MMEA1_ADDRDEC0_RM_SEL_SECCS01__RM1_MASK 0x000000F0L 548495c1f7aaSFeifei Xu #define MMEA1_ADDRDEC0_RM_SEL_SECCS01__RM2_MASK 0x00000F00L 548595c1f7aaSFeifei Xu #define MMEA1_ADDRDEC0_RM_SEL_SECCS01__CHAN_BIT_MASK 0x0000F000L 548695c1f7aaSFeifei Xu #define MMEA1_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L 548795c1f7aaSFeifei Xu #define MMEA1_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L 548895c1f7aaSFeifei Xu //MMEA1_ADDRDEC0_RM_SEL_SECCS23 548995c1f7aaSFeifei Xu #define MMEA1_ADDRDEC0_RM_SEL_SECCS23__RM0__SHIFT 0x0 549095c1f7aaSFeifei Xu #define MMEA1_ADDRDEC0_RM_SEL_SECCS23__RM1__SHIFT 0x4 549195c1f7aaSFeifei Xu #define MMEA1_ADDRDEC0_RM_SEL_SECCS23__RM2__SHIFT 0x8 549295c1f7aaSFeifei Xu #define MMEA1_ADDRDEC0_RM_SEL_SECCS23__CHAN_BIT__SHIFT 0xc 549395c1f7aaSFeifei Xu #define MMEA1_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 549495c1f7aaSFeifei Xu #define MMEA1_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12 549595c1f7aaSFeifei Xu #define MMEA1_ADDRDEC0_RM_SEL_SECCS23__RM0_MASK 0x0000000FL 549695c1f7aaSFeifei Xu #define MMEA1_ADDRDEC0_RM_SEL_SECCS23__RM1_MASK 0x000000F0L 549795c1f7aaSFeifei Xu #define MMEA1_ADDRDEC0_RM_SEL_SECCS23__RM2_MASK 0x00000F00L 549895c1f7aaSFeifei Xu #define MMEA1_ADDRDEC0_RM_SEL_SECCS23__CHAN_BIT_MASK 0x0000F000L 549995c1f7aaSFeifei Xu #define MMEA1_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L 550095c1f7aaSFeifei Xu #define MMEA1_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L 550195c1f7aaSFeifei Xu //MMEA1_ADDRDEC1_BASE_ADDR_CS0 550295c1f7aaSFeifei Xu #define MMEA1_ADDRDEC1_BASE_ADDR_CS0__CS_ENABLE__SHIFT 0x0 550395c1f7aaSFeifei Xu #define MMEA1_ADDRDEC1_BASE_ADDR_CS0__BASE_ADDR__SHIFT 0x1 550495c1f7aaSFeifei Xu #define MMEA1_ADDRDEC1_BASE_ADDR_CS0__CS_ENABLE_MASK 0x00000001L 550595c1f7aaSFeifei Xu #define MMEA1_ADDRDEC1_BASE_ADDR_CS0__BASE_ADDR_MASK 0xFFFFFFFEL 550695c1f7aaSFeifei Xu //MMEA1_ADDRDEC1_BASE_ADDR_CS1 550795c1f7aaSFeifei Xu #define MMEA1_ADDRDEC1_BASE_ADDR_CS1__CS_ENABLE__SHIFT 0x0 550895c1f7aaSFeifei Xu #define MMEA1_ADDRDEC1_BASE_ADDR_CS1__BASE_ADDR__SHIFT 0x1 550995c1f7aaSFeifei Xu #define MMEA1_ADDRDEC1_BASE_ADDR_CS1__CS_ENABLE_MASK 0x00000001L 551095c1f7aaSFeifei Xu #define MMEA1_ADDRDEC1_BASE_ADDR_CS1__BASE_ADDR_MASK 0xFFFFFFFEL 551195c1f7aaSFeifei Xu //MMEA1_ADDRDEC1_BASE_ADDR_CS2 551295c1f7aaSFeifei Xu #define MMEA1_ADDRDEC1_BASE_ADDR_CS2__CS_ENABLE__SHIFT 0x0 551395c1f7aaSFeifei Xu #define MMEA1_ADDRDEC1_BASE_ADDR_CS2__BASE_ADDR__SHIFT 0x1 551495c1f7aaSFeifei Xu #define MMEA1_ADDRDEC1_BASE_ADDR_CS2__CS_ENABLE_MASK 0x00000001L 551595c1f7aaSFeifei Xu #define MMEA1_ADDRDEC1_BASE_ADDR_CS2__BASE_ADDR_MASK 0xFFFFFFFEL 551695c1f7aaSFeifei Xu //MMEA1_ADDRDEC1_BASE_ADDR_CS3 551795c1f7aaSFeifei Xu #define MMEA1_ADDRDEC1_BASE_ADDR_CS3__CS_ENABLE__SHIFT 0x0 551895c1f7aaSFeifei Xu #define MMEA1_ADDRDEC1_BASE_ADDR_CS3__BASE_ADDR__SHIFT 0x1 551995c1f7aaSFeifei Xu #define MMEA1_ADDRDEC1_BASE_ADDR_CS3__CS_ENABLE_MASK 0x00000001L 552095c1f7aaSFeifei Xu #define MMEA1_ADDRDEC1_BASE_ADDR_CS3__BASE_ADDR_MASK 0xFFFFFFFEL 552195c1f7aaSFeifei Xu //MMEA1_ADDRDEC1_BASE_ADDR_SECCS0 552295c1f7aaSFeifei Xu #define MMEA1_ADDRDEC1_BASE_ADDR_SECCS0__CS_ENABLE__SHIFT 0x0 552395c1f7aaSFeifei Xu #define MMEA1_ADDRDEC1_BASE_ADDR_SECCS0__BASE_ADDR__SHIFT 0x1 552495c1f7aaSFeifei Xu #define MMEA1_ADDRDEC1_BASE_ADDR_SECCS0__CS_ENABLE_MASK 0x00000001L 552595c1f7aaSFeifei Xu #define MMEA1_ADDRDEC1_BASE_ADDR_SECCS0__BASE_ADDR_MASK 0xFFFFFFFEL 552695c1f7aaSFeifei Xu //MMEA1_ADDRDEC1_BASE_ADDR_SECCS1 552795c1f7aaSFeifei Xu #define MMEA1_ADDRDEC1_BASE_ADDR_SECCS1__CS_ENABLE__SHIFT 0x0 552895c1f7aaSFeifei Xu #define MMEA1_ADDRDEC1_BASE_ADDR_SECCS1__BASE_ADDR__SHIFT 0x1 552995c1f7aaSFeifei Xu #define MMEA1_ADDRDEC1_BASE_ADDR_SECCS1__CS_ENABLE_MASK 0x00000001L 553095c1f7aaSFeifei Xu #define MMEA1_ADDRDEC1_BASE_ADDR_SECCS1__BASE_ADDR_MASK 0xFFFFFFFEL 553195c1f7aaSFeifei Xu //MMEA1_ADDRDEC1_BASE_ADDR_SECCS2 553295c1f7aaSFeifei Xu #define MMEA1_ADDRDEC1_BASE_ADDR_SECCS2__CS_ENABLE__SHIFT 0x0 553395c1f7aaSFeifei Xu #define MMEA1_ADDRDEC1_BASE_ADDR_SECCS2__BASE_ADDR__SHIFT 0x1 553495c1f7aaSFeifei Xu #define MMEA1_ADDRDEC1_BASE_ADDR_SECCS2__CS_ENABLE_MASK 0x00000001L 553595c1f7aaSFeifei Xu #define MMEA1_ADDRDEC1_BASE_ADDR_SECCS2__BASE_ADDR_MASK 0xFFFFFFFEL 553695c1f7aaSFeifei Xu //MMEA1_ADDRDEC1_BASE_ADDR_SECCS3 553795c1f7aaSFeifei Xu #define MMEA1_ADDRDEC1_BASE_ADDR_SECCS3__CS_ENABLE__SHIFT 0x0 553895c1f7aaSFeifei Xu #define MMEA1_ADDRDEC1_BASE_ADDR_SECCS3__BASE_ADDR__SHIFT 0x1 553995c1f7aaSFeifei Xu #define MMEA1_ADDRDEC1_BASE_ADDR_SECCS3__CS_ENABLE_MASK 0x00000001L 554095c1f7aaSFeifei Xu #define MMEA1_ADDRDEC1_BASE_ADDR_SECCS3__BASE_ADDR_MASK 0xFFFFFFFEL 554195c1f7aaSFeifei Xu //MMEA1_ADDRDEC1_ADDR_MASK_CS01 554295c1f7aaSFeifei Xu #define MMEA1_ADDRDEC1_ADDR_MASK_CS01__ADDR_MASK__SHIFT 0x1 554395c1f7aaSFeifei Xu #define MMEA1_ADDRDEC1_ADDR_MASK_CS01__ADDR_MASK_MASK 0xFFFFFFFEL 554495c1f7aaSFeifei Xu //MMEA1_ADDRDEC1_ADDR_MASK_CS23 554595c1f7aaSFeifei Xu #define MMEA1_ADDRDEC1_ADDR_MASK_CS23__ADDR_MASK__SHIFT 0x1 554695c1f7aaSFeifei Xu #define MMEA1_ADDRDEC1_ADDR_MASK_CS23__ADDR_MASK_MASK 0xFFFFFFFEL 554795c1f7aaSFeifei Xu //MMEA1_ADDRDEC1_ADDR_MASK_SECCS01 554895c1f7aaSFeifei Xu #define MMEA1_ADDRDEC1_ADDR_MASK_SECCS01__ADDR_MASK__SHIFT 0x1 554995c1f7aaSFeifei Xu #define MMEA1_ADDRDEC1_ADDR_MASK_SECCS01__ADDR_MASK_MASK 0xFFFFFFFEL 555095c1f7aaSFeifei Xu //MMEA1_ADDRDEC1_ADDR_MASK_SECCS23 555195c1f7aaSFeifei Xu #define MMEA1_ADDRDEC1_ADDR_MASK_SECCS23__ADDR_MASK__SHIFT 0x1 555295c1f7aaSFeifei Xu #define MMEA1_ADDRDEC1_ADDR_MASK_SECCS23__ADDR_MASK_MASK 0xFFFFFFFEL 555395c1f7aaSFeifei Xu //MMEA1_ADDRDEC1_ADDR_CFG_CS01 555495c1f7aaSFeifei Xu #define MMEA1_ADDRDEC1_ADDR_CFG_CS01__NUM_BANK_GROUPS__SHIFT 0x2 555595c1f7aaSFeifei Xu #define MMEA1_ADDRDEC1_ADDR_CFG_CS01__NUM_RM__SHIFT 0x4 555695c1f7aaSFeifei Xu #define MMEA1_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_LO__SHIFT 0x8 555795c1f7aaSFeifei Xu #define MMEA1_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_HI__SHIFT 0xc 555895c1f7aaSFeifei Xu #define MMEA1_ADDRDEC1_ADDR_CFG_CS01__NUM_COL__SHIFT 0x10 555995c1f7aaSFeifei Xu #define MMEA1_ADDRDEC1_ADDR_CFG_CS01__NUM_BANKS__SHIFT 0x14 556095c1f7aaSFeifei Xu #define MMEA1_ADDRDEC1_ADDR_CFG_CS01__NUM_BANK_GROUPS_MASK 0x0000000CL 556195c1f7aaSFeifei Xu #define MMEA1_ADDRDEC1_ADDR_CFG_CS01__NUM_RM_MASK 0x00000030L 556295c1f7aaSFeifei Xu #define MMEA1_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_LO_MASK 0x00000F00L 556395c1f7aaSFeifei Xu #define MMEA1_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_HI_MASK 0x0000F000L 556495c1f7aaSFeifei Xu #define MMEA1_ADDRDEC1_ADDR_CFG_CS01__NUM_COL_MASK 0x000F0000L 556595c1f7aaSFeifei Xu #define MMEA1_ADDRDEC1_ADDR_CFG_CS01__NUM_BANKS_MASK 0x00300000L 556695c1f7aaSFeifei Xu //MMEA1_ADDRDEC1_ADDR_CFG_CS23 556795c1f7aaSFeifei Xu #define MMEA1_ADDRDEC1_ADDR_CFG_CS23__NUM_BANK_GROUPS__SHIFT 0x2 556895c1f7aaSFeifei Xu #define MMEA1_ADDRDEC1_ADDR_CFG_CS23__NUM_RM__SHIFT 0x4 556995c1f7aaSFeifei Xu #define MMEA1_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_LO__SHIFT 0x8 557095c1f7aaSFeifei Xu #define MMEA1_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_HI__SHIFT 0xc 557195c1f7aaSFeifei Xu #define MMEA1_ADDRDEC1_ADDR_CFG_CS23__NUM_COL__SHIFT 0x10 557295c1f7aaSFeifei Xu #define MMEA1_ADDRDEC1_ADDR_CFG_CS23__NUM_BANKS__SHIFT 0x14 557395c1f7aaSFeifei Xu #define MMEA1_ADDRDEC1_ADDR_CFG_CS23__NUM_BANK_GROUPS_MASK 0x0000000CL 557495c1f7aaSFeifei Xu #define MMEA1_ADDRDEC1_ADDR_CFG_CS23__NUM_RM_MASK 0x00000030L 557595c1f7aaSFeifei Xu #define MMEA1_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_LO_MASK 0x00000F00L 557695c1f7aaSFeifei Xu #define MMEA1_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_HI_MASK 0x0000F000L 557795c1f7aaSFeifei Xu #define MMEA1_ADDRDEC1_ADDR_CFG_CS23__NUM_COL_MASK 0x000F0000L 557895c1f7aaSFeifei Xu #define MMEA1_ADDRDEC1_ADDR_CFG_CS23__NUM_BANKS_MASK 0x00300000L 557995c1f7aaSFeifei Xu //MMEA1_ADDRDEC1_ADDR_SEL_CS01 558095c1f7aaSFeifei Xu #define MMEA1_ADDRDEC1_ADDR_SEL_CS01__BANK0__SHIFT 0x0 558195c1f7aaSFeifei Xu #define MMEA1_ADDRDEC1_ADDR_SEL_CS01__BANK1__SHIFT 0x4 558295c1f7aaSFeifei Xu #define MMEA1_ADDRDEC1_ADDR_SEL_CS01__BANK2__SHIFT 0x8 558395c1f7aaSFeifei Xu #define MMEA1_ADDRDEC1_ADDR_SEL_CS01__BANK3__SHIFT 0xc 558495c1f7aaSFeifei Xu #define MMEA1_ADDRDEC1_ADDR_SEL_CS01__BANK4__SHIFT 0x10 558595c1f7aaSFeifei Xu #define MMEA1_ADDRDEC1_ADDR_SEL_CS01__ROW_LO__SHIFT 0x18 558695c1f7aaSFeifei Xu #define MMEA1_ADDRDEC1_ADDR_SEL_CS01__ROW_HI__SHIFT 0x1c 558795c1f7aaSFeifei Xu #define MMEA1_ADDRDEC1_ADDR_SEL_CS01__BANK0_MASK 0x0000000FL 558895c1f7aaSFeifei Xu #define MMEA1_ADDRDEC1_ADDR_SEL_CS01__BANK1_MASK 0x000000F0L 558995c1f7aaSFeifei Xu #define MMEA1_ADDRDEC1_ADDR_SEL_CS01__BANK2_MASK 0x00000F00L 559095c1f7aaSFeifei Xu #define MMEA1_ADDRDEC1_ADDR_SEL_CS01__BANK3_MASK 0x0000F000L 559195c1f7aaSFeifei Xu #define MMEA1_ADDRDEC1_ADDR_SEL_CS01__BANK4_MASK 0x000F0000L 559295c1f7aaSFeifei Xu #define MMEA1_ADDRDEC1_ADDR_SEL_CS01__ROW_LO_MASK 0x0F000000L 559395c1f7aaSFeifei Xu #define MMEA1_ADDRDEC1_ADDR_SEL_CS01__ROW_HI_MASK 0xF0000000L 559495c1f7aaSFeifei Xu //MMEA1_ADDRDEC1_ADDR_SEL_CS23 559595c1f7aaSFeifei Xu #define MMEA1_ADDRDEC1_ADDR_SEL_CS23__BANK0__SHIFT 0x0 559695c1f7aaSFeifei Xu #define MMEA1_ADDRDEC1_ADDR_SEL_CS23__BANK1__SHIFT 0x4 559795c1f7aaSFeifei Xu #define MMEA1_ADDRDEC1_ADDR_SEL_CS23__BANK2__SHIFT 0x8 559895c1f7aaSFeifei Xu #define MMEA1_ADDRDEC1_ADDR_SEL_CS23__BANK3__SHIFT 0xc 559995c1f7aaSFeifei Xu #define MMEA1_ADDRDEC1_ADDR_SEL_CS23__BANK4__SHIFT 0x10 560095c1f7aaSFeifei Xu #define MMEA1_ADDRDEC1_ADDR_SEL_CS23__ROW_LO__SHIFT 0x18 560195c1f7aaSFeifei Xu #define MMEA1_ADDRDEC1_ADDR_SEL_CS23__ROW_HI__SHIFT 0x1c 560295c1f7aaSFeifei Xu #define MMEA1_ADDRDEC1_ADDR_SEL_CS23__BANK0_MASK 0x0000000FL 560395c1f7aaSFeifei Xu #define MMEA1_ADDRDEC1_ADDR_SEL_CS23__BANK1_MASK 0x000000F0L 560495c1f7aaSFeifei Xu #define MMEA1_ADDRDEC1_ADDR_SEL_CS23__BANK2_MASK 0x00000F00L 560595c1f7aaSFeifei Xu #define MMEA1_ADDRDEC1_ADDR_SEL_CS23__BANK3_MASK 0x0000F000L 560695c1f7aaSFeifei Xu #define MMEA1_ADDRDEC1_ADDR_SEL_CS23__BANK4_MASK 0x000F0000L 560795c1f7aaSFeifei Xu #define MMEA1_ADDRDEC1_ADDR_SEL_CS23__ROW_LO_MASK 0x0F000000L 560895c1f7aaSFeifei Xu #define MMEA1_ADDRDEC1_ADDR_SEL_CS23__ROW_HI_MASK 0xF0000000L 560995c1f7aaSFeifei Xu //MMEA1_ADDRDEC1_COL_SEL_LO_CS01 561095c1f7aaSFeifei Xu #define MMEA1_ADDRDEC1_COL_SEL_LO_CS01__COL0__SHIFT 0x0 561195c1f7aaSFeifei Xu #define MMEA1_ADDRDEC1_COL_SEL_LO_CS01__COL1__SHIFT 0x4 561295c1f7aaSFeifei Xu #define MMEA1_ADDRDEC1_COL_SEL_LO_CS01__COL2__SHIFT 0x8 561395c1f7aaSFeifei Xu #define MMEA1_ADDRDEC1_COL_SEL_LO_CS01__COL3__SHIFT 0xc 561495c1f7aaSFeifei Xu #define MMEA1_ADDRDEC1_COL_SEL_LO_CS01__COL4__SHIFT 0x10 561595c1f7aaSFeifei Xu #define MMEA1_ADDRDEC1_COL_SEL_LO_CS01__COL5__SHIFT 0x14 561695c1f7aaSFeifei Xu #define MMEA1_ADDRDEC1_COL_SEL_LO_CS01__COL6__SHIFT 0x18 561795c1f7aaSFeifei Xu #define MMEA1_ADDRDEC1_COL_SEL_LO_CS01__COL7__SHIFT 0x1c 561895c1f7aaSFeifei Xu #define MMEA1_ADDRDEC1_COL_SEL_LO_CS01__COL0_MASK 0x0000000FL 561995c1f7aaSFeifei Xu #define MMEA1_ADDRDEC1_COL_SEL_LO_CS01__COL1_MASK 0x000000F0L 562095c1f7aaSFeifei Xu #define MMEA1_ADDRDEC1_COL_SEL_LO_CS01__COL2_MASK 0x00000F00L 562195c1f7aaSFeifei Xu #define MMEA1_ADDRDEC1_COL_SEL_LO_CS01__COL3_MASK 0x0000F000L 562295c1f7aaSFeifei Xu #define MMEA1_ADDRDEC1_COL_SEL_LO_CS01__COL4_MASK 0x000F0000L 562395c1f7aaSFeifei Xu #define MMEA1_ADDRDEC1_COL_SEL_LO_CS01__COL5_MASK 0x00F00000L 562495c1f7aaSFeifei Xu #define MMEA1_ADDRDEC1_COL_SEL_LO_CS01__COL6_MASK 0x0F000000L 562595c1f7aaSFeifei Xu #define MMEA1_ADDRDEC1_COL_SEL_LO_CS01__COL7_MASK 0xF0000000L 562695c1f7aaSFeifei Xu //MMEA1_ADDRDEC1_COL_SEL_LO_CS23 562795c1f7aaSFeifei Xu #define MMEA1_ADDRDEC1_COL_SEL_LO_CS23__COL0__SHIFT 0x0 562895c1f7aaSFeifei Xu #define MMEA1_ADDRDEC1_COL_SEL_LO_CS23__COL1__SHIFT 0x4 562995c1f7aaSFeifei Xu #define MMEA1_ADDRDEC1_COL_SEL_LO_CS23__COL2__SHIFT 0x8 563095c1f7aaSFeifei Xu #define MMEA1_ADDRDEC1_COL_SEL_LO_CS23__COL3__SHIFT 0xc 563195c1f7aaSFeifei Xu #define MMEA1_ADDRDEC1_COL_SEL_LO_CS23__COL4__SHIFT 0x10 563295c1f7aaSFeifei Xu #define MMEA1_ADDRDEC1_COL_SEL_LO_CS23__COL5__SHIFT 0x14 563395c1f7aaSFeifei Xu #define MMEA1_ADDRDEC1_COL_SEL_LO_CS23__COL6__SHIFT 0x18 563495c1f7aaSFeifei Xu #define MMEA1_ADDRDEC1_COL_SEL_LO_CS23__COL7__SHIFT 0x1c 563595c1f7aaSFeifei Xu #define MMEA1_ADDRDEC1_COL_SEL_LO_CS23__COL0_MASK 0x0000000FL 563695c1f7aaSFeifei Xu #define MMEA1_ADDRDEC1_COL_SEL_LO_CS23__COL1_MASK 0x000000F0L 563795c1f7aaSFeifei Xu #define MMEA1_ADDRDEC1_COL_SEL_LO_CS23__COL2_MASK 0x00000F00L 563895c1f7aaSFeifei Xu #define MMEA1_ADDRDEC1_COL_SEL_LO_CS23__COL3_MASK 0x0000F000L 563995c1f7aaSFeifei Xu #define MMEA1_ADDRDEC1_COL_SEL_LO_CS23__COL4_MASK 0x000F0000L 564095c1f7aaSFeifei Xu #define MMEA1_ADDRDEC1_COL_SEL_LO_CS23__COL5_MASK 0x00F00000L 564195c1f7aaSFeifei Xu #define MMEA1_ADDRDEC1_COL_SEL_LO_CS23__COL6_MASK 0x0F000000L 564295c1f7aaSFeifei Xu #define MMEA1_ADDRDEC1_COL_SEL_LO_CS23__COL7_MASK 0xF0000000L 564395c1f7aaSFeifei Xu //MMEA1_ADDRDEC1_COL_SEL_HI_CS01 564495c1f7aaSFeifei Xu #define MMEA1_ADDRDEC1_COL_SEL_HI_CS01__COL8__SHIFT 0x0 564595c1f7aaSFeifei Xu #define MMEA1_ADDRDEC1_COL_SEL_HI_CS01__COL9__SHIFT 0x4 564695c1f7aaSFeifei Xu #define MMEA1_ADDRDEC1_COL_SEL_HI_CS01__COL10__SHIFT 0x8 564795c1f7aaSFeifei Xu #define MMEA1_ADDRDEC1_COL_SEL_HI_CS01__COL11__SHIFT 0xc 564895c1f7aaSFeifei Xu #define MMEA1_ADDRDEC1_COL_SEL_HI_CS01__COL12__SHIFT 0x10 564995c1f7aaSFeifei Xu #define MMEA1_ADDRDEC1_COL_SEL_HI_CS01__COL13__SHIFT 0x14 565095c1f7aaSFeifei Xu #define MMEA1_ADDRDEC1_COL_SEL_HI_CS01__COL14__SHIFT 0x18 565195c1f7aaSFeifei Xu #define MMEA1_ADDRDEC1_COL_SEL_HI_CS01__COL15__SHIFT 0x1c 565295c1f7aaSFeifei Xu #define MMEA1_ADDRDEC1_COL_SEL_HI_CS01__COL8_MASK 0x0000000FL 565395c1f7aaSFeifei Xu #define MMEA1_ADDRDEC1_COL_SEL_HI_CS01__COL9_MASK 0x000000F0L 565495c1f7aaSFeifei Xu #define MMEA1_ADDRDEC1_COL_SEL_HI_CS01__COL10_MASK 0x00000F00L 565595c1f7aaSFeifei Xu #define MMEA1_ADDRDEC1_COL_SEL_HI_CS01__COL11_MASK 0x0000F000L 565695c1f7aaSFeifei Xu #define MMEA1_ADDRDEC1_COL_SEL_HI_CS01__COL12_MASK 0x000F0000L 565795c1f7aaSFeifei Xu #define MMEA1_ADDRDEC1_COL_SEL_HI_CS01__COL13_MASK 0x00F00000L 565895c1f7aaSFeifei Xu #define MMEA1_ADDRDEC1_COL_SEL_HI_CS01__COL14_MASK 0x0F000000L 565995c1f7aaSFeifei Xu #define MMEA1_ADDRDEC1_COL_SEL_HI_CS01__COL15_MASK 0xF0000000L 566095c1f7aaSFeifei Xu //MMEA1_ADDRDEC1_COL_SEL_HI_CS23 566195c1f7aaSFeifei Xu #define MMEA1_ADDRDEC1_COL_SEL_HI_CS23__COL8__SHIFT 0x0 566295c1f7aaSFeifei Xu #define MMEA1_ADDRDEC1_COL_SEL_HI_CS23__COL9__SHIFT 0x4 566395c1f7aaSFeifei Xu #define MMEA1_ADDRDEC1_COL_SEL_HI_CS23__COL10__SHIFT 0x8 566495c1f7aaSFeifei Xu #define MMEA1_ADDRDEC1_COL_SEL_HI_CS23__COL11__SHIFT 0xc 566595c1f7aaSFeifei Xu #define MMEA1_ADDRDEC1_COL_SEL_HI_CS23__COL12__SHIFT 0x10 566695c1f7aaSFeifei Xu #define MMEA1_ADDRDEC1_COL_SEL_HI_CS23__COL13__SHIFT 0x14 566795c1f7aaSFeifei Xu #define MMEA1_ADDRDEC1_COL_SEL_HI_CS23__COL14__SHIFT 0x18 566895c1f7aaSFeifei Xu #define MMEA1_ADDRDEC1_COL_SEL_HI_CS23__COL15__SHIFT 0x1c 566995c1f7aaSFeifei Xu #define MMEA1_ADDRDEC1_COL_SEL_HI_CS23__COL8_MASK 0x0000000FL 567095c1f7aaSFeifei Xu #define MMEA1_ADDRDEC1_COL_SEL_HI_CS23__COL9_MASK 0x000000F0L 567195c1f7aaSFeifei Xu #define MMEA1_ADDRDEC1_COL_SEL_HI_CS23__COL10_MASK 0x00000F00L 567295c1f7aaSFeifei Xu #define MMEA1_ADDRDEC1_COL_SEL_HI_CS23__COL11_MASK 0x0000F000L 567395c1f7aaSFeifei Xu #define MMEA1_ADDRDEC1_COL_SEL_HI_CS23__COL12_MASK 0x000F0000L 567495c1f7aaSFeifei Xu #define MMEA1_ADDRDEC1_COL_SEL_HI_CS23__COL13_MASK 0x00F00000L 567595c1f7aaSFeifei Xu #define MMEA1_ADDRDEC1_COL_SEL_HI_CS23__COL14_MASK 0x0F000000L 567695c1f7aaSFeifei Xu #define MMEA1_ADDRDEC1_COL_SEL_HI_CS23__COL15_MASK 0xF0000000L 567795c1f7aaSFeifei Xu //MMEA1_ADDRDEC1_RM_SEL_CS01 567895c1f7aaSFeifei Xu #define MMEA1_ADDRDEC1_RM_SEL_CS01__RM0__SHIFT 0x0 567995c1f7aaSFeifei Xu #define MMEA1_ADDRDEC1_RM_SEL_CS01__RM1__SHIFT 0x4 568095c1f7aaSFeifei Xu #define MMEA1_ADDRDEC1_RM_SEL_CS01__RM2__SHIFT 0x8 568195c1f7aaSFeifei Xu #define MMEA1_ADDRDEC1_RM_SEL_CS01__CHAN_BIT__SHIFT 0xc 568295c1f7aaSFeifei Xu #define MMEA1_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 568395c1f7aaSFeifei Xu #define MMEA1_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12 568495c1f7aaSFeifei Xu #define MMEA1_ADDRDEC1_RM_SEL_CS01__RM0_MASK 0x0000000FL 568595c1f7aaSFeifei Xu #define MMEA1_ADDRDEC1_RM_SEL_CS01__RM1_MASK 0x000000F0L 568695c1f7aaSFeifei Xu #define MMEA1_ADDRDEC1_RM_SEL_CS01__RM2_MASK 0x00000F00L 568795c1f7aaSFeifei Xu #define MMEA1_ADDRDEC1_RM_SEL_CS01__CHAN_BIT_MASK 0x0000F000L 568895c1f7aaSFeifei Xu #define MMEA1_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L 568995c1f7aaSFeifei Xu #define MMEA1_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L 569095c1f7aaSFeifei Xu //MMEA1_ADDRDEC1_RM_SEL_CS23 569195c1f7aaSFeifei Xu #define MMEA1_ADDRDEC1_RM_SEL_CS23__RM0__SHIFT 0x0 569295c1f7aaSFeifei Xu #define MMEA1_ADDRDEC1_RM_SEL_CS23__RM1__SHIFT 0x4 569395c1f7aaSFeifei Xu #define MMEA1_ADDRDEC1_RM_SEL_CS23__RM2__SHIFT 0x8 569495c1f7aaSFeifei Xu #define MMEA1_ADDRDEC1_RM_SEL_CS23__CHAN_BIT__SHIFT 0xc 569595c1f7aaSFeifei Xu #define MMEA1_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 569695c1f7aaSFeifei Xu #define MMEA1_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12 569795c1f7aaSFeifei Xu #define MMEA1_ADDRDEC1_RM_SEL_CS23__RM0_MASK 0x0000000FL 569895c1f7aaSFeifei Xu #define MMEA1_ADDRDEC1_RM_SEL_CS23__RM1_MASK 0x000000F0L 569995c1f7aaSFeifei Xu #define MMEA1_ADDRDEC1_RM_SEL_CS23__RM2_MASK 0x00000F00L 570095c1f7aaSFeifei Xu #define MMEA1_ADDRDEC1_RM_SEL_CS23__CHAN_BIT_MASK 0x0000F000L 570195c1f7aaSFeifei Xu #define MMEA1_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L 570295c1f7aaSFeifei Xu #define MMEA1_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L 570395c1f7aaSFeifei Xu //MMEA1_ADDRDEC1_RM_SEL_SECCS01 570495c1f7aaSFeifei Xu #define MMEA1_ADDRDEC1_RM_SEL_SECCS01__RM0__SHIFT 0x0 570595c1f7aaSFeifei Xu #define MMEA1_ADDRDEC1_RM_SEL_SECCS01__RM1__SHIFT 0x4 570695c1f7aaSFeifei Xu #define MMEA1_ADDRDEC1_RM_SEL_SECCS01__RM2__SHIFT 0x8 570795c1f7aaSFeifei Xu #define MMEA1_ADDRDEC1_RM_SEL_SECCS01__CHAN_BIT__SHIFT 0xc 570895c1f7aaSFeifei Xu #define MMEA1_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 570995c1f7aaSFeifei Xu #define MMEA1_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12 571095c1f7aaSFeifei Xu #define MMEA1_ADDRDEC1_RM_SEL_SECCS01__RM0_MASK 0x0000000FL 571195c1f7aaSFeifei Xu #define MMEA1_ADDRDEC1_RM_SEL_SECCS01__RM1_MASK 0x000000F0L 571295c1f7aaSFeifei Xu #define MMEA1_ADDRDEC1_RM_SEL_SECCS01__RM2_MASK 0x00000F00L 571395c1f7aaSFeifei Xu #define MMEA1_ADDRDEC1_RM_SEL_SECCS01__CHAN_BIT_MASK 0x0000F000L 571495c1f7aaSFeifei Xu #define MMEA1_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L 571595c1f7aaSFeifei Xu #define MMEA1_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L 571695c1f7aaSFeifei Xu //MMEA1_ADDRDEC1_RM_SEL_SECCS23 571795c1f7aaSFeifei Xu #define MMEA1_ADDRDEC1_RM_SEL_SECCS23__RM0__SHIFT 0x0 571895c1f7aaSFeifei Xu #define MMEA1_ADDRDEC1_RM_SEL_SECCS23__RM1__SHIFT 0x4 571995c1f7aaSFeifei Xu #define MMEA1_ADDRDEC1_RM_SEL_SECCS23__RM2__SHIFT 0x8 572095c1f7aaSFeifei Xu #define MMEA1_ADDRDEC1_RM_SEL_SECCS23__CHAN_BIT__SHIFT 0xc 572195c1f7aaSFeifei Xu #define MMEA1_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 572295c1f7aaSFeifei Xu #define MMEA1_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12 572395c1f7aaSFeifei Xu #define MMEA1_ADDRDEC1_RM_SEL_SECCS23__RM0_MASK 0x0000000FL 572495c1f7aaSFeifei Xu #define MMEA1_ADDRDEC1_RM_SEL_SECCS23__RM1_MASK 0x000000F0L 572595c1f7aaSFeifei Xu #define MMEA1_ADDRDEC1_RM_SEL_SECCS23__RM2_MASK 0x00000F00L 572695c1f7aaSFeifei Xu #define MMEA1_ADDRDEC1_RM_SEL_SECCS23__CHAN_BIT_MASK 0x0000F000L 572795c1f7aaSFeifei Xu #define MMEA1_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L 572895c1f7aaSFeifei Xu #define MMEA1_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L 572995c1f7aaSFeifei Xu //MMEA1_IO_RD_CLI2GRP_MAP0 573095c1f7aaSFeifei Xu #define MMEA1_IO_RD_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 573195c1f7aaSFeifei Xu #define MMEA1_IO_RD_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 573295c1f7aaSFeifei Xu #define MMEA1_IO_RD_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 573395c1f7aaSFeifei Xu #define MMEA1_IO_RD_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 573495c1f7aaSFeifei Xu #define MMEA1_IO_RD_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 573595c1f7aaSFeifei Xu #define MMEA1_IO_RD_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa 573695c1f7aaSFeifei Xu #define MMEA1_IO_RD_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc 573795c1f7aaSFeifei Xu #define MMEA1_IO_RD_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe 573895c1f7aaSFeifei Xu #define MMEA1_IO_RD_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 573995c1f7aaSFeifei Xu #define MMEA1_IO_RD_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 574095c1f7aaSFeifei Xu #define MMEA1_IO_RD_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 574195c1f7aaSFeifei Xu #define MMEA1_IO_RD_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 574295c1f7aaSFeifei Xu #define MMEA1_IO_RD_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 574395c1f7aaSFeifei Xu #define MMEA1_IO_RD_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a 574495c1f7aaSFeifei Xu #define MMEA1_IO_RD_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c 574595c1f7aaSFeifei Xu #define MMEA1_IO_RD_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e 574695c1f7aaSFeifei Xu #define MMEA1_IO_RD_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L 574795c1f7aaSFeifei Xu #define MMEA1_IO_RD_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL 574895c1f7aaSFeifei Xu #define MMEA1_IO_RD_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L 574995c1f7aaSFeifei Xu #define MMEA1_IO_RD_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L 575095c1f7aaSFeifei Xu #define MMEA1_IO_RD_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L 575195c1f7aaSFeifei Xu #define MMEA1_IO_RD_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L 575295c1f7aaSFeifei Xu #define MMEA1_IO_RD_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L 575395c1f7aaSFeifei Xu #define MMEA1_IO_RD_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L 575495c1f7aaSFeifei Xu #define MMEA1_IO_RD_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L 575595c1f7aaSFeifei Xu #define MMEA1_IO_RD_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L 575695c1f7aaSFeifei Xu #define MMEA1_IO_RD_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L 575795c1f7aaSFeifei Xu #define MMEA1_IO_RD_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L 575895c1f7aaSFeifei Xu #define MMEA1_IO_RD_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L 575995c1f7aaSFeifei Xu #define MMEA1_IO_RD_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L 576095c1f7aaSFeifei Xu #define MMEA1_IO_RD_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L 576195c1f7aaSFeifei Xu #define MMEA1_IO_RD_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L 576295c1f7aaSFeifei Xu //MMEA1_IO_RD_CLI2GRP_MAP1 576395c1f7aaSFeifei Xu #define MMEA1_IO_RD_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 576495c1f7aaSFeifei Xu #define MMEA1_IO_RD_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 576595c1f7aaSFeifei Xu #define MMEA1_IO_RD_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 576695c1f7aaSFeifei Xu #define MMEA1_IO_RD_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 576795c1f7aaSFeifei Xu #define MMEA1_IO_RD_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 576895c1f7aaSFeifei Xu #define MMEA1_IO_RD_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa 576995c1f7aaSFeifei Xu #define MMEA1_IO_RD_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc 577095c1f7aaSFeifei Xu #define MMEA1_IO_RD_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe 577195c1f7aaSFeifei Xu #define MMEA1_IO_RD_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 577295c1f7aaSFeifei Xu #define MMEA1_IO_RD_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 577395c1f7aaSFeifei Xu #define MMEA1_IO_RD_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 577495c1f7aaSFeifei Xu #define MMEA1_IO_RD_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 577595c1f7aaSFeifei Xu #define MMEA1_IO_RD_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 577695c1f7aaSFeifei Xu #define MMEA1_IO_RD_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a 577795c1f7aaSFeifei Xu #define MMEA1_IO_RD_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c 577895c1f7aaSFeifei Xu #define MMEA1_IO_RD_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e 577995c1f7aaSFeifei Xu #define MMEA1_IO_RD_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L 578095c1f7aaSFeifei Xu #define MMEA1_IO_RD_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL 578195c1f7aaSFeifei Xu #define MMEA1_IO_RD_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L 578295c1f7aaSFeifei Xu #define MMEA1_IO_RD_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L 578395c1f7aaSFeifei Xu #define MMEA1_IO_RD_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L 578495c1f7aaSFeifei Xu #define MMEA1_IO_RD_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L 578595c1f7aaSFeifei Xu #define MMEA1_IO_RD_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L 578695c1f7aaSFeifei Xu #define MMEA1_IO_RD_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L 578795c1f7aaSFeifei Xu #define MMEA1_IO_RD_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L 578895c1f7aaSFeifei Xu #define MMEA1_IO_RD_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L 578995c1f7aaSFeifei Xu #define MMEA1_IO_RD_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L 579095c1f7aaSFeifei Xu #define MMEA1_IO_RD_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L 579195c1f7aaSFeifei Xu #define MMEA1_IO_RD_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L 579295c1f7aaSFeifei Xu #define MMEA1_IO_RD_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L 579395c1f7aaSFeifei Xu #define MMEA1_IO_RD_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L 579495c1f7aaSFeifei Xu #define MMEA1_IO_RD_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L 579595c1f7aaSFeifei Xu //MMEA1_IO_WR_CLI2GRP_MAP0 579695c1f7aaSFeifei Xu #define MMEA1_IO_WR_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 579795c1f7aaSFeifei Xu #define MMEA1_IO_WR_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 579895c1f7aaSFeifei Xu #define MMEA1_IO_WR_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 579995c1f7aaSFeifei Xu #define MMEA1_IO_WR_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 580095c1f7aaSFeifei Xu #define MMEA1_IO_WR_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 580195c1f7aaSFeifei Xu #define MMEA1_IO_WR_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa 580295c1f7aaSFeifei Xu #define MMEA1_IO_WR_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc 580395c1f7aaSFeifei Xu #define MMEA1_IO_WR_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe 580495c1f7aaSFeifei Xu #define MMEA1_IO_WR_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 580595c1f7aaSFeifei Xu #define MMEA1_IO_WR_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 580695c1f7aaSFeifei Xu #define MMEA1_IO_WR_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 580795c1f7aaSFeifei Xu #define MMEA1_IO_WR_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 580895c1f7aaSFeifei Xu #define MMEA1_IO_WR_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 580995c1f7aaSFeifei Xu #define MMEA1_IO_WR_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a 581095c1f7aaSFeifei Xu #define MMEA1_IO_WR_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c 581195c1f7aaSFeifei Xu #define MMEA1_IO_WR_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e 581295c1f7aaSFeifei Xu #define MMEA1_IO_WR_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L 581395c1f7aaSFeifei Xu #define MMEA1_IO_WR_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL 581495c1f7aaSFeifei Xu #define MMEA1_IO_WR_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L 581595c1f7aaSFeifei Xu #define MMEA1_IO_WR_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L 581695c1f7aaSFeifei Xu #define MMEA1_IO_WR_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L 581795c1f7aaSFeifei Xu #define MMEA1_IO_WR_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L 581895c1f7aaSFeifei Xu #define MMEA1_IO_WR_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L 581995c1f7aaSFeifei Xu #define MMEA1_IO_WR_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L 582095c1f7aaSFeifei Xu #define MMEA1_IO_WR_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L 582195c1f7aaSFeifei Xu #define MMEA1_IO_WR_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L 582295c1f7aaSFeifei Xu #define MMEA1_IO_WR_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L 582395c1f7aaSFeifei Xu #define MMEA1_IO_WR_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L 582495c1f7aaSFeifei Xu #define MMEA1_IO_WR_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L 582595c1f7aaSFeifei Xu #define MMEA1_IO_WR_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L 582695c1f7aaSFeifei Xu #define MMEA1_IO_WR_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L 582795c1f7aaSFeifei Xu #define MMEA1_IO_WR_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L 582895c1f7aaSFeifei Xu //MMEA1_IO_WR_CLI2GRP_MAP1 582995c1f7aaSFeifei Xu #define MMEA1_IO_WR_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 583095c1f7aaSFeifei Xu #define MMEA1_IO_WR_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 583195c1f7aaSFeifei Xu #define MMEA1_IO_WR_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 583295c1f7aaSFeifei Xu #define MMEA1_IO_WR_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 583395c1f7aaSFeifei Xu #define MMEA1_IO_WR_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 583495c1f7aaSFeifei Xu #define MMEA1_IO_WR_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa 583595c1f7aaSFeifei Xu #define MMEA1_IO_WR_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc 583695c1f7aaSFeifei Xu #define MMEA1_IO_WR_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe 583795c1f7aaSFeifei Xu #define MMEA1_IO_WR_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 583895c1f7aaSFeifei Xu #define MMEA1_IO_WR_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 583995c1f7aaSFeifei Xu #define MMEA1_IO_WR_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 584095c1f7aaSFeifei Xu #define MMEA1_IO_WR_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 584195c1f7aaSFeifei Xu #define MMEA1_IO_WR_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 584295c1f7aaSFeifei Xu #define MMEA1_IO_WR_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a 584395c1f7aaSFeifei Xu #define MMEA1_IO_WR_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c 584495c1f7aaSFeifei Xu #define MMEA1_IO_WR_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e 584595c1f7aaSFeifei Xu #define MMEA1_IO_WR_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L 584695c1f7aaSFeifei Xu #define MMEA1_IO_WR_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL 584795c1f7aaSFeifei Xu #define MMEA1_IO_WR_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L 584895c1f7aaSFeifei Xu #define MMEA1_IO_WR_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L 584995c1f7aaSFeifei Xu #define MMEA1_IO_WR_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L 585095c1f7aaSFeifei Xu #define MMEA1_IO_WR_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L 585195c1f7aaSFeifei Xu #define MMEA1_IO_WR_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L 585295c1f7aaSFeifei Xu #define MMEA1_IO_WR_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L 585395c1f7aaSFeifei Xu #define MMEA1_IO_WR_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L 585495c1f7aaSFeifei Xu #define MMEA1_IO_WR_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L 585595c1f7aaSFeifei Xu #define MMEA1_IO_WR_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L 585695c1f7aaSFeifei Xu #define MMEA1_IO_WR_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L 585795c1f7aaSFeifei Xu #define MMEA1_IO_WR_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L 585895c1f7aaSFeifei Xu #define MMEA1_IO_WR_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L 585995c1f7aaSFeifei Xu #define MMEA1_IO_WR_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L 586095c1f7aaSFeifei Xu #define MMEA1_IO_WR_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L 586195c1f7aaSFeifei Xu //MMEA1_IO_RD_COMBINE_FLUSH 586295c1f7aaSFeifei Xu #define MMEA1_IO_RD_COMBINE_FLUSH__GROUP0_TIMER__SHIFT 0x0 586395c1f7aaSFeifei Xu #define MMEA1_IO_RD_COMBINE_FLUSH__GROUP1_TIMER__SHIFT 0x4 586495c1f7aaSFeifei Xu #define MMEA1_IO_RD_COMBINE_FLUSH__GROUP2_TIMER__SHIFT 0x8 586595c1f7aaSFeifei Xu #define MMEA1_IO_RD_COMBINE_FLUSH__GROUP3_TIMER__SHIFT 0xc 586695c1f7aaSFeifei Xu #define MMEA1_IO_RD_COMBINE_FLUSH__GROUP0_TIMER_MASK 0x0000000FL 586795c1f7aaSFeifei Xu #define MMEA1_IO_RD_COMBINE_FLUSH__GROUP1_TIMER_MASK 0x000000F0L 586895c1f7aaSFeifei Xu #define MMEA1_IO_RD_COMBINE_FLUSH__GROUP2_TIMER_MASK 0x00000F00L 586995c1f7aaSFeifei Xu #define MMEA1_IO_RD_COMBINE_FLUSH__GROUP3_TIMER_MASK 0x0000F000L 587095c1f7aaSFeifei Xu //MMEA1_IO_WR_COMBINE_FLUSH 587195c1f7aaSFeifei Xu #define MMEA1_IO_WR_COMBINE_FLUSH__GROUP0_TIMER__SHIFT 0x0 587295c1f7aaSFeifei Xu #define MMEA1_IO_WR_COMBINE_FLUSH__GROUP1_TIMER__SHIFT 0x4 587395c1f7aaSFeifei Xu #define MMEA1_IO_WR_COMBINE_FLUSH__GROUP2_TIMER__SHIFT 0x8 587495c1f7aaSFeifei Xu #define MMEA1_IO_WR_COMBINE_FLUSH__GROUP3_TIMER__SHIFT 0xc 587595c1f7aaSFeifei Xu #define MMEA1_IO_WR_COMBINE_FLUSH__GROUP0_TIMER_MASK 0x0000000FL 587695c1f7aaSFeifei Xu #define MMEA1_IO_WR_COMBINE_FLUSH__GROUP1_TIMER_MASK 0x000000F0L 587795c1f7aaSFeifei Xu #define MMEA1_IO_WR_COMBINE_FLUSH__GROUP2_TIMER_MASK 0x00000F00L 587895c1f7aaSFeifei Xu #define MMEA1_IO_WR_COMBINE_FLUSH__GROUP3_TIMER_MASK 0x0000F000L 587995c1f7aaSFeifei Xu //MMEA1_IO_GROUP_BURST 588095c1f7aaSFeifei Xu #define MMEA1_IO_GROUP_BURST__RD_LIMIT_LO__SHIFT 0x0 588195c1f7aaSFeifei Xu #define MMEA1_IO_GROUP_BURST__RD_LIMIT_HI__SHIFT 0x8 588295c1f7aaSFeifei Xu #define MMEA1_IO_GROUP_BURST__WR_LIMIT_LO__SHIFT 0x10 588395c1f7aaSFeifei Xu #define MMEA1_IO_GROUP_BURST__WR_LIMIT_HI__SHIFT 0x18 588495c1f7aaSFeifei Xu #define MMEA1_IO_GROUP_BURST__RD_LIMIT_LO_MASK 0x000000FFL 588595c1f7aaSFeifei Xu #define MMEA1_IO_GROUP_BURST__RD_LIMIT_HI_MASK 0x0000FF00L 588695c1f7aaSFeifei Xu #define MMEA1_IO_GROUP_BURST__WR_LIMIT_LO_MASK 0x00FF0000L 588795c1f7aaSFeifei Xu #define MMEA1_IO_GROUP_BURST__WR_LIMIT_HI_MASK 0xFF000000L 588895c1f7aaSFeifei Xu //MMEA1_IO_RD_PRI_AGE 588995c1f7aaSFeifei Xu #define MMEA1_IO_RD_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 589095c1f7aaSFeifei Xu #define MMEA1_IO_RD_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 589195c1f7aaSFeifei Xu #define MMEA1_IO_RD_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 589295c1f7aaSFeifei Xu #define MMEA1_IO_RD_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 589395c1f7aaSFeifei Xu #define MMEA1_IO_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc 589495c1f7aaSFeifei Xu #define MMEA1_IO_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf 589595c1f7aaSFeifei Xu #define MMEA1_IO_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 589695c1f7aaSFeifei Xu #define MMEA1_IO_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 589795c1f7aaSFeifei Xu #define MMEA1_IO_RD_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L 589895c1f7aaSFeifei Xu #define MMEA1_IO_RD_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L 589995c1f7aaSFeifei Xu #define MMEA1_IO_RD_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L 590095c1f7aaSFeifei Xu #define MMEA1_IO_RD_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L 590195c1f7aaSFeifei Xu #define MMEA1_IO_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L 590295c1f7aaSFeifei Xu #define MMEA1_IO_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L 590395c1f7aaSFeifei Xu #define MMEA1_IO_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L 590495c1f7aaSFeifei Xu #define MMEA1_IO_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L 590595c1f7aaSFeifei Xu //MMEA1_IO_WR_PRI_AGE 590695c1f7aaSFeifei Xu #define MMEA1_IO_WR_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 590795c1f7aaSFeifei Xu #define MMEA1_IO_WR_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 590895c1f7aaSFeifei Xu #define MMEA1_IO_WR_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 590995c1f7aaSFeifei Xu #define MMEA1_IO_WR_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 591095c1f7aaSFeifei Xu #define MMEA1_IO_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc 591195c1f7aaSFeifei Xu #define MMEA1_IO_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf 591295c1f7aaSFeifei Xu #define MMEA1_IO_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 591395c1f7aaSFeifei Xu #define MMEA1_IO_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 591495c1f7aaSFeifei Xu #define MMEA1_IO_WR_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L 591595c1f7aaSFeifei Xu #define MMEA1_IO_WR_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L 591695c1f7aaSFeifei Xu #define MMEA1_IO_WR_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L 591795c1f7aaSFeifei Xu #define MMEA1_IO_WR_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L 591895c1f7aaSFeifei Xu #define MMEA1_IO_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L 591995c1f7aaSFeifei Xu #define MMEA1_IO_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L 592095c1f7aaSFeifei Xu #define MMEA1_IO_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L 592195c1f7aaSFeifei Xu #define MMEA1_IO_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L 592295c1f7aaSFeifei Xu //MMEA1_IO_RD_PRI_QUEUING 592395c1f7aaSFeifei Xu #define MMEA1_IO_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 592495c1f7aaSFeifei Xu #define MMEA1_IO_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 592595c1f7aaSFeifei Xu #define MMEA1_IO_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 592695c1f7aaSFeifei Xu #define MMEA1_IO_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 592795c1f7aaSFeifei Xu #define MMEA1_IO_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L 592895c1f7aaSFeifei Xu #define MMEA1_IO_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L 592995c1f7aaSFeifei Xu #define MMEA1_IO_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L 593095c1f7aaSFeifei Xu #define MMEA1_IO_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L 593195c1f7aaSFeifei Xu //MMEA1_IO_WR_PRI_QUEUING 593295c1f7aaSFeifei Xu #define MMEA1_IO_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 593395c1f7aaSFeifei Xu #define MMEA1_IO_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 593495c1f7aaSFeifei Xu #define MMEA1_IO_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 593595c1f7aaSFeifei Xu #define MMEA1_IO_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 593695c1f7aaSFeifei Xu #define MMEA1_IO_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L 593795c1f7aaSFeifei Xu #define MMEA1_IO_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L 593895c1f7aaSFeifei Xu #define MMEA1_IO_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L 593995c1f7aaSFeifei Xu #define MMEA1_IO_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L 594095c1f7aaSFeifei Xu //MMEA1_IO_RD_PRI_FIXED 594195c1f7aaSFeifei Xu #define MMEA1_IO_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 594295c1f7aaSFeifei Xu #define MMEA1_IO_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 594395c1f7aaSFeifei Xu #define MMEA1_IO_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 594495c1f7aaSFeifei Xu #define MMEA1_IO_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 594595c1f7aaSFeifei Xu #define MMEA1_IO_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L 594695c1f7aaSFeifei Xu #define MMEA1_IO_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L 594795c1f7aaSFeifei Xu #define MMEA1_IO_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L 594895c1f7aaSFeifei Xu #define MMEA1_IO_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L 594995c1f7aaSFeifei Xu //MMEA1_IO_WR_PRI_FIXED 595095c1f7aaSFeifei Xu #define MMEA1_IO_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 595195c1f7aaSFeifei Xu #define MMEA1_IO_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 595295c1f7aaSFeifei Xu #define MMEA1_IO_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 595395c1f7aaSFeifei Xu #define MMEA1_IO_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 595495c1f7aaSFeifei Xu #define MMEA1_IO_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L 595595c1f7aaSFeifei Xu #define MMEA1_IO_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L 595695c1f7aaSFeifei Xu #define MMEA1_IO_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L 595795c1f7aaSFeifei Xu #define MMEA1_IO_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L 595895c1f7aaSFeifei Xu //MMEA1_IO_RD_PRI_URGENCY 595995c1f7aaSFeifei Xu #define MMEA1_IO_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 596095c1f7aaSFeifei Xu #define MMEA1_IO_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 596195c1f7aaSFeifei Xu #define MMEA1_IO_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 596295c1f7aaSFeifei Xu #define MMEA1_IO_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 596395c1f7aaSFeifei Xu #define MMEA1_IO_RD_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc 596495c1f7aaSFeifei Xu #define MMEA1_IO_RD_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd 596595c1f7aaSFeifei Xu #define MMEA1_IO_RD_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe 596695c1f7aaSFeifei Xu #define MMEA1_IO_RD_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf 596795c1f7aaSFeifei Xu #define MMEA1_IO_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L 596895c1f7aaSFeifei Xu #define MMEA1_IO_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L 596995c1f7aaSFeifei Xu #define MMEA1_IO_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L 597095c1f7aaSFeifei Xu #define MMEA1_IO_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L 597195c1f7aaSFeifei Xu #define MMEA1_IO_RD_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L 597295c1f7aaSFeifei Xu #define MMEA1_IO_RD_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L 597395c1f7aaSFeifei Xu #define MMEA1_IO_RD_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L 597495c1f7aaSFeifei Xu #define MMEA1_IO_RD_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L 597595c1f7aaSFeifei Xu //MMEA1_IO_WR_PRI_URGENCY 597695c1f7aaSFeifei Xu #define MMEA1_IO_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 597795c1f7aaSFeifei Xu #define MMEA1_IO_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 597895c1f7aaSFeifei Xu #define MMEA1_IO_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 597995c1f7aaSFeifei Xu #define MMEA1_IO_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 598095c1f7aaSFeifei Xu #define MMEA1_IO_WR_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc 598195c1f7aaSFeifei Xu #define MMEA1_IO_WR_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd 598295c1f7aaSFeifei Xu #define MMEA1_IO_WR_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe 598395c1f7aaSFeifei Xu #define MMEA1_IO_WR_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf 598495c1f7aaSFeifei Xu #define MMEA1_IO_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L 598595c1f7aaSFeifei Xu #define MMEA1_IO_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L 598695c1f7aaSFeifei Xu #define MMEA1_IO_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L 598795c1f7aaSFeifei Xu #define MMEA1_IO_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L 598895c1f7aaSFeifei Xu #define MMEA1_IO_WR_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L 598995c1f7aaSFeifei Xu #define MMEA1_IO_WR_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L 599095c1f7aaSFeifei Xu #define MMEA1_IO_WR_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L 599195c1f7aaSFeifei Xu #define MMEA1_IO_WR_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L 599295c1f7aaSFeifei Xu //MMEA1_IO_RD_PRI_URGENCY_MASK 599395c1f7aaSFeifei Xu #define MMEA1_IO_RD_PRI_URGENCY_MASK__CID0_MASK__SHIFT 0x0 599495c1f7aaSFeifei Xu #define MMEA1_IO_RD_PRI_URGENCY_MASK__CID1_MASK__SHIFT 0x1 599595c1f7aaSFeifei Xu #define MMEA1_IO_RD_PRI_URGENCY_MASK__CID2_MASK__SHIFT 0x2 599695c1f7aaSFeifei Xu #define MMEA1_IO_RD_PRI_URGENCY_MASK__CID3_MASK__SHIFT 0x3 599795c1f7aaSFeifei Xu #define MMEA1_IO_RD_PRI_URGENCY_MASK__CID4_MASK__SHIFT 0x4 599895c1f7aaSFeifei Xu #define MMEA1_IO_RD_PRI_URGENCY_MASK__CID5_MASK__SHIFT 0x5 599995c1f7aaSFeifei Xu #define MMEA1_IO_RD_PRI_URGENCY_MASK__CID6_MASK__SHIFT 0x6 600095c1f7aaSFeifei Xu #define MMEA1_IO_RD_PRI_URGENCY_MASK__CID7_MASK__SHIFT 0x7 600195c1f7aaSFeifei Xu #define MMEA1_IO_RD_PRI_URGENCY_MASK__CID8_MASK__SHIFT 0x8 600295c1f7aaSFeifei Xu #define MMEA1_IO_RD_PRI_URGENCY_MASK__CID9_MASK__SHIFT 0x9 600395c1f7aaSFeifei Xu #define MMEA1_IO_RD_PRI_URGENCY_MASK__CID10_MASK__SHIFT 0xa 600495c1f7aaSFeifei Xu #define MMEA1_IO_RD_PRI_URGENCY_MASK__CID11_MASK__SHIFT 0xb 600595c1f7aaSFeifei Xu #define MMEA1_IO_RD_PRI_URGENCY_MASK__CID12_MASK__SHIFT 0xc 600695c1f7aaSFeifei Xu #define MMEA1_IO_RD_PRI_URGENCY_MASK__CID13_MASK__SHIFT 0xd 600795c1f7aaSFeifei Xu #define MMEA1_IO_RD_PRI_URGENCY_MASK__CID14_MASK__SHIFT 0xe 600895c1f7aaSFeifei Xu #define MMEA1_IO_RD_PRI_URGENCY_MASK__CID15_MASK__SHIFT 0xf 600995c1f7aaSFeifei Xu #define MMEA1_IO_RD_PRI_URGENCY_MASK__CID16_MASK__SHIFT 0x10 601095c1f7aaSFeifei Xu #define MMEA1_IO_RD_PRI_URGENCY_MASK__CID17_MASK__SHIFT 0x11 601195c1f7aaSFeifei Xu #define MMEA1_IO_RD_PRI_URGENCY_MASK__CID18_MASK__SHIFT 0x12 601295c1f7aaSFeifei Xu #define MMEA1_IO_RD_PRI_URGENCY_MASK__CID19_MASK__SHIFT 0x13 601395c1f7aaSFeifei Xu #define MMEA1_IO_RD_PRI_URGENCY_MASK__CID20_MASK__SHIFT 0x14 601495c1f7aaSFeifei Xu #define MMEA1_IO_RD_PRI_URGENCY_MASK__CID21_MASK__SHIFT 0x15 601595c1f7aaSFeifei Xu #define MMEA1_IO_RD_PRI_URGENCY_MASK__CID22_MASK__SHIFT 0x16 601695c1f7aaSFeifei Xu #define MMEA1_IO_RD_PRI_URGENCY_MASK__CID23_MASK__SHIFT 0x17 601795c1f7aaSFeifei Xu #define MMEA1_IO_RD_PRI_URGENCY_MASK__CID24_MASK__SHIFT 0x18 601895c1f7aaSFeifei Xu #define MMEA1_IO_RD_PRI_URGENCY_MASK__CID25_MASK__SHIFT 0x19 601995c1f7aaSFeifei Xu #define MMEA1_IO_RD_PRI_URGENCY_MASK__CID26_MASK__SHIFT 0x1a 602095c1f7aaSFeifei Xu #define MMEA1_IO_RD_PRI_URGENCY_MASK__CID27_MASK__SHIFT 0x1b 602195c1f7aaSFeifei Xu #define MMEA1_IO_RD_PRI_URGENCY_MASK__CID28_MASK__SHIFT 0x1c 602295c1f7aaSFeifei Xu #define MMEA1_IO_RD_PRI_URGENCY_MASK__CID29_MASK__SHIFT 0x1d 602395c1f7aaSFeifei Xu #define MMEA1_IO_RD_PRI_URGENCY_MASK__CID30_MASK__SHIFT 0x1e 602495c1f7aaSFeifei Xu #define MMEA1_IO_RD_PRI_URGENCY_MASK__CID31_MASK__SHIFT 0x1f 602595c1f7aaSFeifei Xu #define MMEA1_IO_RD_PRI_URGENCY_MASK__CID0_MASK_MASK 0x00000001L 602695c1f7aaSFeifei Xu #define MMEA1_IO_RD_PRI_URGENCY_MASK__CID1_MASK_MASK 0x00000002L 602795c1f7aaSFeifei Xu #define MMEA1_IO_RD_PRI_URGENCY_MASK__CID2_MASK_MASK 0x00000004L 602895c1f7aaSFeifei Xu #define MMEA1_IO_RD_PRI_URGENCY_MASK__CID3_MASK_MASK 0x00000008L 602995c1f7aaSFeifei Xu #define MMEA1_IO_RD_PRI_URGENCY_MASK__CID4_MASK_MASK 0x00000010L 603095c1f7aaSFeifei Xu #define MMEA1_IO_RD_PRI_URGENCY_MASK__CID5_MASK_MASK 0x00000020L 603195c1f7aaSFeifei Xu #define MMEA1_IO_RD_PRI_URGENCY_MASK__CID6_MASK_MASK 0x00000040L 603295c1f7aaSFeifei Xu #define MMEA1_IO_RD_PRI_URGENCY_MASK__CID7_MASK_MASK 0x00000080L 603395c1f7aaSFeifei Xu #define MMEA1_IO_RD_PRI_URGENCY_MASK__CID8_MASK_MASK 0x00000100L 603495c1f7aaSFeifei Xu #define MMEA1_IO_RD_PRI_URGENCY_MASK__CID9_MASK_MASK 0x00000200L 603595c1f7aaSFeifei Xu #define MMEA1_IO_RD_PRI_URGENCY_MASK__CID10_MASK_MASK 0x00000400L 603695c1f7aaSFeifei Xu #define MMEA1_IO_RD_PRI_URGENCY_MASK__CID11_MASK_MASK 0x00000800L 603795c1f7aaSFeifei Xu #define MMEA1_IO_RD_PRI_URGENCY_MASK__CID12_MASK_MASK 0x00001000L 603895c1f7aaSFeifei Xu #define MMEA1_IO_RD_PRI_URGENCY_MASK__CID13_MASK_MASK 0x00002000L 603995c1f7aaSFeifei Xu #define MMEA1_IO_RD_PRI_URGENCY_MASK__CID14_MASK_MASK 0x00004000L 604095c1f7aaSFeifei Xu #define MMEA1_IO_RD_PRI_URGENCY_MASK__CID15_MASK_MASK 0x00008000L 604195c1f7aaSFeifei Xu #define MMEA1_IO_RD_PRI_URGENCY_MASK__CID16_MASK_MASK 0x00010000L 604295c1f7aaSFeifei Xu #define MMEA1_IO_RD_PRI_URGENCY_MASK__CID17_MASK_MASK 0x00020000L 604395c1f7aaSFeifei Xu #define MMEA1_IO_RD_PRI_URGENCY_MASK__CID18_MASK_MASK 0x00040000L 604495c1f7aaSFeifei Xu #define MMEA1_IO_RD_PRI_URGENCY_MASK__CID19_MASK_MASK 0x00080000L 604595c1f7aaSFeifei Xu #define MMEA1_IO_RD_PRI_URGENCY_MASK__CID20_MASK_MASK 0x00100000L 604695c1f7aaSFeifei Xu #define MMEA1_IO_RD_PRI_URGENCY_MASK__CID21_MASK_MASK 0x00200000L 604795c1f7aaSFeifei Xu #define MMEA1_IO_RD_PRI_URGENCY_MASK__CID22_MASK_MASK 0x00400000L 604895c1f7aaSFeifei Xu #define MMEA1_IO_RD_PRI_URGENCY_MASK__CID23_MASK_MASK 0x00800000L 604995c1f7aaSFeifei Xu #define MMEA1_IO_RD_PRI_URGENCY_MASK__CID24_MASK_MASK 0x01000000L 605095c1f7aaSFeifei Xu #define MMEA1_IO_RD_PRI_URGENCY_MASK__CID25_MASK_MASK 0x02000000L 605195c1f7aaSFeifei Xu #define MMEA1_IO_RD_PRI_URGENCY_MASK__CID26_MASK_MASK 0x04000000L 605295c1f7aaSFeifei Xu #define MMEA1_IO_RD_PRI_URGENCY_MASK__CID27_MASK_MASK 0x08000000L 605395c1f7aaSFeifei Xu #define MMEA1_IO_RD_PRI_URGENCY_MASK__CID28_MASK_MASK 0x10000000L 605495c1f7aaSFeifei Xu #define MMEA1_IO_RD_PRI_URGENCY_MASK__CID29_MASK_MASK 0x20000000L 605595c1f7aaSFeifei Xu #define MMEA1_IO_RD_PRI_URGENCY_MASK__CID30_MASK_MASK 0x40000000L 605695c1f7aaSFeifei Xu #define MMEA1_IO_RD_PRI_URGENCY_MASK__CID31_MASK_MASK 0x80000000L 605795c1f7aaSFeifei Xu //MMEA1_IO_WR_PRI_URGENCY_MASK 605895c1f7aaSFeifei Xu #define MMEA1_IO_WR_PRI_URGENCY_MASK__CID0_MASK__SHIFT 0x0 605995c1f7aaSFeifei Xu #define MMEA1_IO_WR_PRI_URGENCY_MASK__CID1_MASK__SHIFT 0x1 606095c1f7aaSFeifei Xu #define MMEA1_IO_WR_PRI_URGENCY_MASK__CID2_MASK__SHIFT 0x2 606195c1f7aaSFeifei Xu #define MMEA1_IO_WR_PRI_URGENCY_MASK__CID3_MASK__SHIFT 0x3 606295c1f7aaSFeifei Xu #define MMEA1_IO_WR_PRI_URGENCY_MASK__CID4_MASK__SHIFT 0x4 606395c1f7aaSFeifei Xu #define MMEA1_IO_WR_PRI_URGENCY_MASK__CID5_MASK__SHIFT 0x5 606495c1f7aaSFeifei Xu #define MMEA1_IO_WR_PRI_URGENCY_MASK__CID6_MASK__SHIFT 0x6 606595c1f7aaSFeifei Xu #define MMEA1_IO_WR_PRI_URGENCY_MASK__CID7_MASK__SHIFT 0x7 606695c1f7aaSFeifei Xu #define MMEA1_IO_WR_PRI_URGENCY_MASK__CID8_MASK__SHIFT 0x8 606795c1f7aaSFeifei Xu #define MMEA1_IO_WR_PRI_URGENCY_MASK__CID9_MASK__SHIFT 0x9 606895c1f7aaSFeifei Xu #define MMEA1_IO_WR_PRI_URGENCY_MASK__CID10_MASK__SHIFT 0xa 606995c1f7aaSFeifei Xu #define MMEA1_IO_WR_PRI_URGENCY_MASK__CID11_MASK__SHIFT 0xb 607095c1f7aaSFeifei Xu #define MMEA1_IO_WR_PRI_URGENCY_MASK__CID12_MASK__SHIFT 0xc 607195c1f7aaSFeifei Xu #define MMEA1_IO_WR_PRI_URGENCY_MASK__CID13_MASK__SHIFT 0xd 607295c1f7aaSFeifei Xu #define MMEA1_IO_WR_PRI_URGENCY_MASK__CID14_MASK__SHIFT 0xe 607395c1f7aaSFeifei Xu #define MMEA1_IO_WR_PRI_URGENCY_MASK__CID15_MASK__SHIFT 0xf 607495c1f7aaSFeifei Xu #define MMEA1_IO_WR_PRI_URGENCY_MASK__CID16_MASK__SHIFT 0x10 607595c1f7aaSFeifei Xu #define MMEA1_IO_WR_PRI_URGENCY_MASK__CID17_MASK__SHIFT 0x11 607695c1f7aaSFeifei Xu #define MMEA1_IO_WR_PRI_URGENCY_MASK__CID18_MASK__SHIFT 0x12 607795c1f7aaSFeifei Xu #define MMEA1_IO_WR_PRI_URGENCY_MASK__CID19_MASK__SHIFT 0x13 607895c1f7aaSFeifei Xu #define MMEA1_IO_WR_PRI_URGENCY_MASK__CID20_MASK__SHIFT 0x14 607995c1f7aaSFeifei Xu #define MMEA1_IO_WR_PRI_URGENCY_MASK__CID21_MASK__SHIFT 0x15 608095c1f7aaSFeifei Xu #define MMEA1_IO_WR_PRI_URGENCY_MASK__CID22_MASK__SHIFT 0x16 608195c1f7aaSFeifei Xu #define MMEA1_IO_WR_PRI_URGENCY_MASK__CID23_MASK__SHIFT 0x17 608295c1f7aaSFeifei Xu #define MMEA1_IO_WR_PRI_URGENCY_MASK__CID24_MASK__SHIFT 0x18 608395c1f7aaSFeifei Xu #define MMEA1_IO_WR_PRI_URGENCY_MASK__CID25_MASK__SHIFT 0x19 608495c1f7aaSFeifei Xu #define MMEA1_IO_WR_PRI_URGENCY_MASK__CID26_MASK__SHIFT 0x1a 608595c1f7aaSFeifei Xu #define MMEA1_IO_WR_PRI_URGENCY_MASK__CID27_MASK__SHIFT 0x1b 608695c1f7aaSFeifei Xu #define MMEA1_IO_WR_PRI_URGENCY_MASK__CID28_MASK__SHIFT 0x1c 608795c1f7aaSFeifei Xu #define MMEA1_IO_WR_PRI_URGENCY_MASK__CID29_MASK__SHIFT 0x1d 608895c1f7aaSFeifei Xu #define MMEA1_IO_WR_PRI_URGENCY_MASK__CID30_MASK__SHIFT 0x1e 608995c1f7aaSFeifei Xu #define MMEA1_IO_WR_PRI_URGENCY_MASK__CID31_MASK__SHIFT 0x1f 609095c1f7aaSFeifei Xu #define MMEA1_IO_WR_PRI_URGENCY_MASK__CID0_MASK_MASK 0x00000001L 609195c1f7aaSFeifei Xu #define MMEA1_IO_WR_PRI_URGENCY_MASK__CID1_MASK_MASK 0x00000002L 609295c1f7aaSFeifei Xu #define MMEA1_IO_WR_PRI_URGENCY_MASK__CID2_MASK_MASK 0x00000004L 609395c1f7aaSFeifei Xu #define MMEA1_IO_WR_PRI_URGENCY_MASK__CID3_MASK_MASK 0x00000008L 609495c1f7aaSFeifei Xu #define MMEA1_IO_WR_PRI_URGENCY_MASK__CID4_MASK_MASK 0x00000010L 609595c1f7aaSFeifei Xu #define MMEA1_IO_WR_PRI_URGENCY_MASK__CID5_MASK_MASK 0x00000020L 609695c1f7aaSFeifei Xu #define MMEA1_IO_WR_PRI_URGENCY_MASK__CID6_MASK_MASK 0x00000040L 609795c1f7aaSFeifei Xu #define MMEA1_IO_WR_PRI_URGENCY_MASK__CID7_MASK_MASK 0x00000080L 609895c1f7aaSFeifei Xu #define MMEA1_IO_WR_PRI_URGENCY_MASK__CID8_MASK_MASK 0x00000100L 609995c1f7aaSFeifei Xu #define MMEA1_IO_WR_PRI_URGENCY_MASK__CID9_MASK_MASK 0x00000200L 610095c1f7aaSFeifei Xu #define MMEA1_IO_WR_PRI_URGENCY_MASK__CID10_MASK_MASK 0x00000400L 610195c1f7aaSFeifei Xu #define MMEA1_IO_WR_PRI_URGENCY_MASK__CID11_MASK_MASK 0x00000800L 610295c1f7aaSFeifei Xu #define MMEA1_IO_WR_PRI_URGENCY_MASK__CID12_MASK_MASK 0x00001000L 610395c1f7aaSFeifei Xu #define MMEA1_IO_WR_PRI_URGENCY_MASK__CID13_MASK_MASK 0x00002000L 610495c1f7aaSFeifei Xu #define MMEA1_IO_WR_PRI_URGENCY_MASK__CID14_MASK_MASK 0x00004000L 610595c1f7aaSFeifei Xu #define MMEA1_IO_WR_PRI_URGENCY_MASK__CID15_MASK_MASK 0x00008000L 610695c1f7aaSFeifei Xu #define MMEA1_IO_WR_PRI_URGENCY_MASK__CID16_MASK_MASK 0x00010000L 610795c1f7aaSFeifei Xu #define MMEA1_IO_WR_PRI_URGENCY_MASK__CID17_MASK_MASK 0x00020000L 610895c1f7aaSFeifei Xu #define MMEA1_IO_WR_PRI_URGENCY_MASK__CID18_MASK_MASK 0x00040000L 610995c1f7aaSFeifei Xu #define MMEA1_IO_WR_PRI_URGENCY_MASK__CID19_MASK_MASK 0x00080000L 611095c1f7aaSFeifei Xu #define MMEA1_IO_WR_PRI_URGENCY_MASK__CID20_MASK_MASK 0x00100000L 611195c1f7aaSFeifei Xu #define MMEA1_IO_WR_PRI_URGENCY_MASK__CID21_MASK_MASK 0x00200000L 611295c1f7aaSFeifei Xu #define MMEA1_IO_WR_PRI_URGENCY_MASK__CID22_MASK_MASK 0x00400000L 611395c1f7aaSFeifei Xu #define MMEA1_IO_WR_PRI_URGENCY_MASK__CID23_MASK_MASK 0x00800000L 611495c1f7aaSFeifei Xu #define MMEA1_IO_WR_PRI_URGENCY_MASK__CID24_MASK_MASK 0x01000000L 611595c1f7aaSFeifei Xu #define MMEA1_IO_WR_PRI_URGENCY_MASK__CID25_MASK_MASK 0x02000000L 611695c1f7aaSFeifei Xu #define MMEA1_IO_WR_PRI_URGENCY_MASK__CID26_MASK_MASK 0x04000000L 611795c1f7aaSFeifei Xu #define MMEA1_IO_WR_PRI_URGENCY_MASK__CID27_MASK_MASK 0x08000000L 611895c1f7aaSFeifei Xu #define MMEA1_IO_WR_PRI_URGENCY_MASK__CID28_MASK_MASK 0x10000000L 611995c1f7aaSFeifei Xu #define MMEA1_IO_WR_PRI_URGENCY_MASK__CID29_MASK_MASK 0x20000000L 612095c1f7aaSFeifei Xu #define MMEA1_IO_WR_PRI_URGENCY_MASK__CID30_MASK_MASK 0x40000000L 612195c1f7aaSFeifei Xu #define MMEA1_IO_WR_PRI_URGENCY_MASK__CID31_MASK_MASK 0x80000000L 612295c1f7aaSFeifei Xu //MMEA1_IO_RD_PRI_QUANT_PRI1 612395c1f7aaSFeifei Xu #define MMEA1_IO_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 612495c1f7aaSFeifei Xu #define MMEA1_IO_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 612595c1f7aaSFeifei Xu #define MMEA1_IO_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 612695c1f7aaSFeifei Xu #define MMEA1_IO_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 612795c1f7aaSFeifei Xu #define MMEA1_IO_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL 612895c1f7aaSFeifei Xu #define MMEA1_IO_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L 612995c1f7aaSFeifei Xu #define MMEA1_IO_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L 613095c1f7aaSFeifei Xu #define MMEA1_IO_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L 613195c1f7aaSFeifei Xu //MMEA1_IO_RD_PRI_QUANT_PRI2 613295c1f7aaSFeifei Xu #define MMEA1_IO_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 613395c1f7aaSFeifei Xu #define MMEA1_IO_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 613495c1f7aaSFeifei Xu #define MMEA1_IO_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 613595c1f7aaSFeifei Xu #define MMEA1_IO_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 613695c1f7aaSFeifei Xu #define MMEA1_IO_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL 613795c1f7aaSFeifei Xu #define MMEA1_IO_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L 613895c1f7aaSFeifei Xu #define MMEA1_IO_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L 613995c1f7aaSFeifei Xu #define MMEA1_IO_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L 614095c1f7aaSFeifei Xu //MMEA1_IO_RD_PRI_QUANT_PRI3 614195c1f7aaSFeifei Xu #define MMEA1_IO_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 614295c1f7aaSFeifei Xu #define MMEA1_IO_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 614395c1f7aaSFeifei Xu #define MMEA1_IO_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 614495c1f7aaSFeifei Xu #define MMEA1_IO_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 614595c1f7aaSFeifei Xu #define MMEA1_IO_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL 614695c1f7aaSFeifei Xu #define MMEA1_IO_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L 614795c1f7aaSFeifei Xu #define MMEA1_IO_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L 614895c1f7aaSFeifei Xu #define MMEA1_IO_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L 614995c1f7aaSFeifei Xu //MMEA1_IO_WR_PRI_QUANT_PRI1 615095c1f7aaSFeifei Xu #define MMEA1_IO_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 615195c1f7aaSFeifei Xu #define MMEA1_IO_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 615295c1f7aaSFeifei Xu #define MMEA1_IO_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 615395c1f7aaSFeifei Xu #define MMEA1_IO_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 615495c1f7aaSFeifei Xu #define MMEA1_IO_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL 615595c1f7aaSFeifei Xu #define MMEA1_IO_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L 615695c1f7aaSFeifei Xu #define MMEA1_IO_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L 615795c1f7aaSFeifei Xu #define MMEA1_IO_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L 615895c1f7aaSFeifei Xu //MMEA1_IO_WR_PRI_QUANT_PRI2 615995c1f7aaSFeifei Xu #define MMEA1_IO_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 616095c1f7aaSFeifei Xu #define MMEA1_IO_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 616195c1f7aaSFeifei Xu #define MMEA1_IO_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 616295c1f7aaSFeifei Xu #define MMEA1_IO_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 616395c1f7aaSFeifei Xu #define MMEA1_IO_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL 616495c1f7aaSFeifei Xu #define MMEA1_IO_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L 616595c1f7aaSFeifei Xu #define MMEA1_IO_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L 616695c1f7aaSFeifei Xu #define MMEA1_IO_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L 616795c1f7aaSFeifei Xu //MMEA1_IO_WR_PRI_QUANT_PRI3 616895c1f7aaSFeifei Xu #define MMEA1_IO_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 616995c1f7aaSFeifei Xu #define MMEA1_IO_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 617095c1f7aaSFeifei Xu #define MMEA1_IO_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 617195c1f7aaSFeifei Xu #define MMEA1_IO_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 617295c1f7aaSFeifei Xu #define MMEA1_IO_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL 617395c1f7aaSFeifei Xu #define MMEA1_IO_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L 617495c1f7aaSFeifei Xu #define MMEA1_IO_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L 617595c1f7aaSFeifei Xu #define MMEA1_IO_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L 617695c1f7aaSFeifei Xu //MMEA1_SDP_ARB_DRAM 617795c1f7aaSFeifei Xu #define MMEA1_SDP_ARB_DRAM__RDWR_BURST_LIMIT_CYCL__SHIFT 0x0 617895c1f7aaSFeifei Xu #define MMEA1_SDP_ARB_DRAM__RDWR_BURST_LIMIT_DATA__SHIFT 0x8 617995c1f7aaSFeifei Xu #define MMEA1_SDP_ARB_DRAM__EARLY_SW2RD_ON_PRI__SHIFT 0x10 618095c1f7aaSFeifei Xu #define MMEA1_SDP_ARB_DRAM__EARLY_SW2WR_ON_PRI__SHIFT 0x11 618195c1f7aaSFeifei Xu #define MMEA1_SDP_ARB_DRAM__EARLY_SW2RD_ON_RES__SHIFT 0x12 618295c1f7aaSFeifei Xu #define MMEA1_SDP_ARB_DRAM__EARLY_SW2WR_ON_RES__SHIFT 0x13 618395c1f7aaSFeifei Xu #define MMEA1_SDP_ARB_DRAM__EOB_ON_EXPIRE__SHIFT 0x14 618495c1f7aaSFeifei Xu #define MMEA1_SDP_ARB_DRAM__RDWR_BURST_LIMIT_CYCL_MASK 0x0000007FL 618595c1f7aaSFeifei Xu #define MMEA1_SDP_ARB_DRAM__RDWR_BURST_LIMIT_DATA_MASK 0x00007F00L 618695c1f7aaSFeifei Xu #define MMEA1_SDP_ARB_DRAM__EARLY_SW2RD_ON_PRI_MASK 0x00010000L 618795c1f7aaSFeifei Xu #define MMEA1_SDP_ARB_DRAM__EARLY_SW2WR_ON_PRI_MASK 0x00020000L 618895c1f7aaSFeifei Xu #define MMEA1_SDP_ARB_DRAM__EARLY_SW2RD_ON_RES_MASK 0x00040000L 618995c1f7aaSFeifei Xu #define MMEA1_SDP_ARB_DRAM__EARLY_SW2WR_ON_RES_MASK 0x00080000L 619095c1f7aaSFeifei Xu #define MMEA1_SDP_ARB_DRAM__EOB_ON_EXPIRE_MASK 0x00100000L 619195c1f7aaSFeifei Xu //MMEA1_SDP_ARB_FINAL 619295c1f7aaSFeifei Xu #define MMEA1_SDP_ARB_FINAL__DRAM_BURST_LIMIT__SHIFT 0x0 619395c1f7aaSFeifei Xu #define MMEA1_SDP_ARB_FINAL__GMI_BURST_LIMIT__SHIFT 0x5 619495c1f7aaSFeifei Xu #define MMEA1_SDP_ARB_FINAL__IO_BURST_LIMIT__SHIFT 0xa 619595c1f7aaSFeifei Xu #define MMEA1_SDP_ARB_FINAL__BURST_LIMIT_MULTIPLIER__SHIFT 0xf 619695c1f7aaSFeifei Xu #define MMEA1_SDP_ARB_FINAL__RDONLY_VC0__SHIFT 0x11 619795c1f7aaSFeifei Xu #define MMEA1_SDP_ARB_FINAL__RDONLY_VC1__SHIFT 0x12 619895c1f7aaSFeifei Xu #define MMEA1_SDP_ARB_FINAL__RDONLY_VC2__SHIFT 0x13 619995c1f7aaSFeifei Xu #define MMEA1_SDP_ARB_FINAL__RDONLY_VC3__SHIFT 0x14 620095c1f7aaSFeifei Xu #define MMEA1_SDP_ARB_FINAL__RDONLY_VC4__SHIFT 0x15 620195c1f7aaSFeifei Xu #define MMEA1_SDP_ARB_FINAL__RDONLY_VC5__SHIFT 0x16 620295c1f7aaSFeifei Xu #define MMEA1_SDP_ARB_FINAL__RDONLY_VC6__SHIFT 0x17 620395c1f7aaSFeifei Xu #define MMEA1_SDP_ARB_FINAL__RDONLY_VC7__SHIFT 0x18 620495c1f7aaSFeifei Xu #define MMEA1_SDP_ARB_FINAL__ERREVENT_ON_ERROR__SHIFT 0x19 620595c1f7aaSFeifei Xu #define MMEA1_SDP_ARB_FINAL__HALTREQ_ON_ERROR__SHIFT 0x1a 620695c1f7aaSFeifei Xu #define MMEA1_SDP_ARB_FINAL__DRAM_BURST_LIMIT_MASK 0x0000001FL 620795c1f7aaSFeifei Xu #define MMEA1_SDP_ARB_FINAL__GMI_BURST_LIMIT_MASK 0x000003E0L 620895c1f7aaSFeifei Xu #define MMEA1_SDP_ARB_FINAL__IO_BURST_LIMIT_MASK 0x00007C00L 620995c1f7aaSFeifei Xu #define MMEA1_SDP_ARB_FINAL__BURST_LIMIT_MULTIPLIER_MASK 0x00018000L 621095c1f7aaSFeifei Xu #define MMEA1_SDP_ARB_FINAL__RDONLY_VC0_MASK 0x00020000L 621195c1f7aaSFeifei Xu #define MMEA1_SDP_ARB_FINAL__RDONLY_VC1_MASK 0x00040000L 621295c1f7aaSFeifei Xu #define MMEA1_SDP_ARB_FINAL__RDONLY_VC2_MASK 0x00080000L 621395c1f7aaSFeifei Xu #define MMEA1_SDP_ARB_FINAL__RDONLY_VC3_MASK 0x00100000L 621495c1f7aaSFeifei Xu #define MMEA1_SDP_ARB_FINAL__RDONLY_VC4_MASK 0x00200000L 621595c1f7aaSFeifei Xu #define MMEA1_SDP_ARB_FINAL__RDONLY_VC5_MASK 0x00400000L 621695c1f7aaSFeifei Xu #define MMEA1_SDP_ARB_FINAL__RDONLY_VC6_MASK 0x00800000L 621795c1f7aaSFeifei Xu #define MMEA1_SDP_ARB_FINAL__RDONLY_VC7_MASK 0x01000000L 621895c1f7aaSFeifei Xu #define MMEA1_SDP_ARB_FINAL__ERREVENT_ON_ERROR_MASK 0x02000000L 621995c1f7aaSFeifei Xu #define MMEA1_SDP_ARB_FINAL__HALTREQ_ON_ERROR_MASK 0x04000000L 622095c1f7aaSFeifei Xu //MMEA1_SDP_DRAM_PRIORITY 622195c1f7aaSFeifei Xu #define MMEA1_SDP_DRAM_PRIORITY__RD_GROUP0_PRIORITY__SHIFT 0x0 622295c1f7aaSFeifei Xu #define MMEA1_SDP_DRAM_PRIORITY__RD_GROUP1_PRIORITY__SHIFT 0x4 622395c1f7aaSFeifei Xu #define MMEA1_SDP_DRAM_PRIORITY__RD_GROUP2_PRIORITY__SHIFT 0x8 622495c1f7aaSFeifei Xu #define MMEA1_SDP_DRAM_PRIORITY__RD_GROUP3_PRIORITY__SHIFT 0xc 622595c1f7aaSFeifei Xu #define MMEA1_SDP_DRAM_PRIORITY__WR_GROUP0_PRIORITY__SHIFT 0x10 622695c1f7aaSFeifei Xu #define MMEA1_SDP_DRAM_PRIORITY__WR_GROUP1_PRIORITY__SHIFT 0x14 622795c1f7aaSFeifei Xu #define MMEA1_SDP_DRAM_PRIORITY__WR_GROUP2_PRIORITY__SHIFT 0x18 622895c1f7aaSFeifei Xu #define MMEA1_SDP_DRAM_PRIORITY__WR_GROUP3_PRIORITY__SHIFT 0x1c 622995c1f7aaSFeifei Xu #define MMEA1_SDP_DRAM_PRIORITY__RD_GROUP0_PRIORITY_MASK 0x0000000FL 623095c1f7aaSFeifei Xu #define MMEA1_SDP_DRAM_PRIORITY__RD_GROUP1_PRIORITY_MASK 0x000000F0L 623195c1f7aaSFeifei Xu #define MMEA1_SDP_DRAM_PRIORITY__RD_GROUP2_PRIORITY_MASK 0x00000F00L 623295c1f7aaSFeifei Xu #define MMEA1_SDP_DRAM_PRIORITY__RD_GROUP3_PRIORITY_MASK 0x0000F000L 623395c1f7aaSFeifei Xu #define MMEA1_SDP_DRAM_PRIORITY__WR_GROUP0_PRIORITY_MASK 0x000F0000L 623495c1f7aaSFeifei Xu #define MMEA1_SDP_DRAM_PRIORITY__WR_GROUP1_PRIORITY_MASK 0x00F00000L 623595c1f7aaSFeifei Xu #define MMEA1_SDP_DRAM_PRIORITY__WR_GROUP2_PRIORITY_MASK 0x0F000000L 623695c1f7aaSFeifei Xu #define MMEA1_SDP_DRAM_PRIORITY__WR_GROUP3_PRIORITY_MASK 0xF0000000L 623795c1f7aaSFeifei Xu //MMEA1_SDP_IO_PRIORITY 623895c1f7aaSFeifei Xu #define MMEA1_SDP_IO_PRIORITY__RD_GROUP0_PRIORITY__SHIFT 0x0 623995c1f7aaSFeifei Xu #define MMEA1_SDP_IO_PRIORITY__RD_GROUP1_PRIORITY__SHIFT 0x4 624095c1f7aaSFeifei Xu #define MMEA1_SDP_IO_PRIORITY__RD_GROUP2_PRIORITY__SHIFT 0x8 624195c1f7aaSFeifei Xu #define MMEA1_SDP_IO_PRIORITY__RD_GROUP3_PRIORITY__SHIFT 0xc 624295c1f7aaSFeifei Xu #define MMEA1_SDP_IO_PRIORITY__WR_GROUP0_PRIORITY__SHIFT 0x10 624395c1f7aaSFeifei Xu #define MMEA1_SDP_IO_PRIORITY__WR_GROUP1_PRIORITY__SHIFT 0x14 624495c1f7aaSFeifei Xu #define MMEA1_SDP_IO_PRIORITY__WR_GROUP2_PRIORITY__SHIFT 0x18 624595c1f7aaSFeifei Xu #define MMEA1_SDP_IO_PRIORITY__WR_GROUP3_PRIORITY__SHIFT 0x1c 624695c1f7aaSFeifei Xu #define MMEA1_SDP_IO_PRIORITY__RD_GROUP0_PRIORITY_MASK 0x0000000FL 624795c1f7aaSFeifei Xu #define MMEA1_SDP_IO_PRIORITY__RD_GROUP1_PRIORITY_MASK 0x000000F0L 624895c1f7aaSFeifei Xu #define MMEA1_SDP_IO_PRIORITY__RD_GROUP2_PRIORITY_MASK 0x00000F00L 624995c1f7aaSFeifei Xu #define MMEA1_SDP_IO_PRIORITY__RD_GROUP3_PRIORITY_MASK 0x0000F000L 625095c1f7aaSFeifei Xu #define MMEA1_SDP_IO_PRIORITY__WR_GROUP0_PRIORITY_MASK 0x000F0000L 625195c1f7aaSFeifei Xu #define MMEA1_SDP_IO_PRIORITY__WR_GROUP1_PRIORITY_MASK 0x00F00000L 625295c1f7aaSFeifei Xu #define MMEA1_SDP_IO_PRIORITY__WR_GROUP2_PRIORITY_MASK 0x0F000000L 625395c1f7aaSFeifei Xu #define MMEA1_SDP_IO_PRIORITY__WR_GROUP3_PRIORITY_MASK 0xF0000000L 625495c1f7aaSFeifei Xu //MMEA1_SDP_CREDITS 625595c1f7aaSFeifei Xu #define MMEA1_SDP_CREDITS__TAG_LIMIT__SHIFT 0x0 625695c1f7aaSFeifei Xu #define MMEA1_SDP_CREDITS__WR_RESP_CREDITS__SHIFT 0x8 625795c1f7aaSFeifei Xu #define MMEA1_SDP_CREDITS__RD_RESP_CREDITS__SHIFT 0x10 625895c1f7aaSFeifei Xu #define MMEA1_SDP_CREDITS__TAG_LIMIT_MASK 0x000000FFL 625995c1f7aaSFeifei Xu #define MMEA1_SDP_CREDITS__WR_RESP_CREDITS_MASK 0x00007F00L 626095c1f7aaSFeifei Xu #define MMEA1_SDP_CREDITS__RD_RESP_CREDITS_MASK 0x007F0000L 626195c1f7aaSFeifei Xu //MMEA1_SDP_TAG_RESERVE0 626295c1f7aaSFeifei Xu #define MMEA1_SDP_TAG_RESERVE0__VC0__SHIFT 0x0 626395c1f7aaSFeifei Xu #define MMEA1_SDP_TAG_RESERVE0__VC1__SHIFT 0x8 626495c1f7aaSFeifei Xu #define MMEA1_SDP_TAG_RESERVE0__VC2__SHIFT 0x10 626595c1f7aaSFeifei Xu #define MMEA1_SDP_TAG_RESERVE0__VC3__SHIFT 0x18 626695c1f7aaSFeifei Xu #define MMEA1_SDP_TAG_RESERVE0__VC0_MASK 0x000000FFL 626795c1f7aaSFeifei Xu #define MMEA1_SDP_TAG_RESERVE0__VC1_MASK 0x0000FF00L 626895c1f7aaSFeifei Xu #define MMEA1_SDP_TAG_RESERVE0__VC2_MASK 0x00FF0000L 626995c1f7aaSFeifei Xu #define MMEA1_SDP_TAG_RESERVE0__VC3_MASK 0xFF000000L 627095c1f7aaSFeifei Xu //MMEA1_SDP_TAG_RESERVE1 627195c1f7aaSFeifei Xu #define MMEA1_SDP_TAG_RESERVE1__VC4__SHIFT 0x0 627295c1f7aaSFeifei Xu #define MMEA1_SDP_TAG_RESERVE1__VC5__SHIFT 0x8 627395c1f7aaSFeifei Xu #define MMEA1_SDP_TAG_RESERVE1__VC6__SHIFT 0x10 627495c1f7aaSFeifei Xu #define MMEA1_SDP_TAG_RESERVE1__VC7__SHIFT 0x18 627595c1f7aaSFeifei Xu #define MMEA1_SDP_TAG_RESERVE1__VC4_MASK 0x000000FFL 627695c1f7aaSFeifei Xu #define MMEA1_SDP_TAG_RESERVE1__VC5_MASK 0x0000FF00L 627795c1f7aaSFeifei Xu #define MMEA1_SDP_TAG_RESERVE1__VC6_MASK 0x00FF0000L 627895c1f7aaSFeifei Xu #define MMEA1_SDP_TAG_RESERVE1__VC7_MASK 0xFF000000L 627995c1f7aaSFeifei Xu //MMEA1_SDP_VCC_RESERVE0 628095c1f7aaSFeifei Xu #define MMEA1_SDP_VCC_RESERVE0__VC0_CREDITS__SHIFT 0x0 628195c1f7aaSFeifei Xu #define MMEA1_SDP_VCC_RESERVE0__VC1_CREDITS__SHIFT 0x6 628295c1f7aaSFeifei Xu #define MMEA1_SDP_VCC_RESERVE0__VC2_CREDITS__SHIFT 0xc 628395c1f7aaSFeifei Xu #define MMEA1_SDP_VCC_RESERVE0__VC3_CREDITS__SHIFT 0x12 628495c1f7aaSFeifei Xu #define MMEA1_SDP_VCC_RESERVE0__VC4_CREDITS__SHIFT 0x18 628595c1f7aaSFeifei Xu #define MMEA1_SDP_VCC_RESERVE0__VC0_CREDITS_MASK 0x0000003FL 628695c1f7aaSFeifei Xu #define MMEA1_SDP_VCC_RESERVE0__VC1_CREDITS_MASK 0x00000FC0L 628795c1f7aaSFeifei Xu #define MMEA1_SDP_VCC_RESERVE0__VC2_CREDITS_MASK 0x0003F000L 628895c1f7aaSFeifei Xu #define MMEA1_SDP_VCC_RESERVE0__VC3_CREDITS_MASK 0x00FC0000L 628995c1f7aaSFeifei Xu #define MMEA1_SDP_VCC_RESERVE0__VC4_CREDITS_MASK 0x3F000000L 629095c1f7aaSFeifei Xu //MMEA1_SDP_VCC_RESERVE1 629195c1f7aaSFeifei Xu #define MMEA1_SDP_VCC_RESERVE1__VC5_CREDITS__SHIFT 0x0 629295c1f7aaSFeifei Xu #define MMEA1_SDP_VCC_RESERVE1__VC6_CREDITS__SHIFT 0x6 629395c1f7aaSFeifei Xu #define MMEA1_SDP_VCC_RESERVE1__VC7_CREDITS__SHIFT 0xc 629495c1f7aaSFeifei Xu #define MMEA1_SDP_VCC_RESERVE1__DISTRIBUTE_POOL__SHIFT 0x1f 629595c1f7aaSFeifei Xu #define MMEA1_SDP_VCC_RESERVE1__VC5_CREDITS_MASK 0x0000003FL 629695c1f7aaSFeifei Xu #define MMEA1_SDP_VCC_RESERVE1__VC6_CREDITS_MASK 0x00000FC0L 629795c1f7aaSFeifei Xu #define MMEA1_SDP_VCC_RESERVE1__VC7_CREDITS_MASK 0x0003F000L 629895c1f7aaSFeifei Xu #define MMEA1_SDP_VCC_RESERVE1__DISTRIBUTE_POOL_MASK 0x80000000L 629995c1f7aaSFeifei Xu //MMEA1_SDP_VCD_RESERVE0 630095c1f7aaSFeifei Xu #define MMEA1_SDP_VCD_RESERVE0__VC0_CREDITS__SHIFT 0x0 630195c1f7aaSFeifei Xu #define MMEA1_SDP_VCD_RESERVE0__VC1_CREDITS__SHIFT 0x6 630295c1f7aaSFeifei Xu #define MMEA1_SDP_VCD_RESERVE0__VC2_CREDITS__SHIFT 0xc 630395c1f7aaSFeifei Xu #define MMEA1_SDP_VCD_RESERVE0__VC3_CREDITS__SHIFT 0x12 630495c1f7aaSFeifei Xu #define MMEA1_SDP_VCD_RESERVE0__VC4_CREDITS__SHIFT 0x18 630595c1f7aaSFeifei Xu #define MMEA1_SDP_VCD_RESERVE0__VC0_CREDITS_MASK 0x0000003FL 630695c1f7aaSFeifei Xu #define MMEA1_SDP_VCD_RESERVE0__VC1_CREDITS_MASK 0x00000FC0L 630795c1f7aaSFeifei Xu #define MMEA1_SDP_VCD_RESERVE0__VC2_CREDITS_MASK 0x0003F000L 630895c1f7aaSFeifei Xu #define MMEA1_SDP_VCD_RESERVE0__VC3_CREDITS_MASK 0x00FC0000L 630995c1f7aaSFeifei Xu #define MMEA1_SDP_VCD_RESERVE0__VC4_CREDITS_MASK 0x3F000000L 631095c1f7aaSFeifei Xu //MMEA1_SDP_VCD_RESERVE1 631195c1f7aaSFeifei Xu #define MMEA1_SDP_VCD_RESERVE1__VC5_CREDITS__SHIFT 0x0 631295c1f7aaSFeifei Xu #define MMEA1_SDP_VCD_RESERVE1__VC6_CREDITS__SHIFT 0x6 631395c1f7aaSFeifei Xu #define MMEA1_SDP_VCD_RESERVE1__VC7_CREDITS__SHIFT 0xc 631495c1f7aaSFeifei Xu #define MMEA1_SDP_VCD_RESERVE1__DISTRIBUTE_POOL__SHIFT 0x1f 631595c1f7aaSFeifei Xu #define MMEA1_SDP_VCD_RESERVE1__VC5_CREDITS_MASK 0x0000003FL 631695c1f7aaSFeifei Xu #define MMEA1_SDP_VCD_RESERVE1__VC6_CREDITS_MASK 0x00000FC0L 631795c1f7aaSFeifei Xu #define MMEA1_SDP_VCD_RESERVE1__VC7_CREDITS_MASK 0x0003F000L 631895c1f7aaSFeifei Xu #define MMEA1_SDP_VCD_RESERVE1__DISTRIBUTE_POOL_MASK 0x80000000L 631995c1f7aaSFeifei Xu //MMEA1_SDP_REQ_CNTL 632095c1f7aaSFeifei Xu #define MMEA1_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_READ__SHIFT 0x0 632195c1f7aaSFeifei Xu #define MMEA1_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_WRITE__SHIFT 0x1 632295c1f7aaSFeifei Xu #define MMEA1_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_ATOMIC__SHIFT 0x2 632395c1f7aaSFeifei Xu #define MMEA1_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_DRAM__SHIFT 0x3 632495c1f7aaSFeifei Xu #define MMEA1_SDP_REQ_CNTL__INNER_DOMAIN_MODE__SHIFT 0x4 632595c1f7aaSFeifei Xu #define MMEA1_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_READ_MASK 0x00000001L 632695c1f7aaSFeifei Xu #define MMEA1_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_WRITE_MASK 0x00000002L 632795c1f7aaSFeifei Xu #define MMEA1_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_ATOMIC_MASK 0x00000004L 632895c1f7aaSFeifei Xu #define MMEA1_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_DRAM_MASK 0x00000008L 632995c1f7aaSFeifei Xu #define MMEA1_SDP_REQ_CNTL__INNER_DOMAIN_MODE_MASK 0x00000010L 633095c1f7aaSFeifei Xu //MMEA1_MISC 633195c1f7aaSFeifei Xu #define MMEA1_MISC__RELATIVE_PRI_IN_DRAM_RD_ARB__SHIFT 0x0 633295c1f7aaSFeifei Xu #define MMEA1_MISC__RELATIVE_PRI_IN_DRAM_WR_ARB__SHIFT 0x1 633395c1f7aaSFeifei Xu #define MMEA1_MISC__RELATIVE_PRI_IN_GMI_RD_ARB__SHIFT 0x2 633495c1f7aaSFeifei Xu #define MMEA1_MISC__RELATIVE_PRI_IN_GMI_WR_ARB__SHIFT 0x3 633595c1f7aaSFeifei Xu #define MMEA1_MISC__RELATIVE_PRI_IN_IO_RD_ARB__SHIFT 0x4 633695c1f7aaSFeifei Xu #define MMEA1_MISC__RELATIVE_PRI_IN_IO_WR_ARB__SHIFT 0x5 633795c1f7aaSFeifei Xu #define MMEA1_MISC__RRET_SWAP_MODE__SHIFT 0x6 633895c1f7aaSFeifei Xu #define MMEA1_MISC__EARLY_SDP_ORIGDATA__SHIFT 0x7 633995c1f7aaSFeifei Xu #define MMEA1_MISC__LINKMGR_DYNAMIC_MODE__SHIFT 0x8 634095c1f7aaSFeifei Xu #define MMEA1_MISC__LINKMGR_HALT_THRESHOLD__SHIFT 0xa 634195c1f7aaSFeifei Xu #define MMEA1_MISC__LINKMGR_RECONNECT_DELAY__SHIFT 0xc 634295c1f7aaSFeifei Xu #define MMEA1_MISC__LINKMGR_IDLE_THRESHOLD__SHIFT 0xe 634395c1f7aaSFeifei Xu #define MMEA1_MISC__FAVOUR_MIDCHAIN_CS_IN_DRAM_ARB__SHIFT 0x13 634495c1f7aaSFeifei Xu #define MMEA1_MISC__FAVOUR_MIDCHAIN_CS_IN_GMI_ARB__SHIFT 0x14 634595c1f7aaSFeifei Xu #define MMEA1_MISC__FAVOUR_LAST_CS_IN_DRAM_ARB__SHIFT 0x15 634695c1f7aaSFeifei Xu #define MMEA1_MISC__FAVOUR_LAST_CS_IN_GMI_ARB__SHIFT 0x16 634795c1f7aaSFeifei Xu #define MMEA1_MISC__SWITCH_CS_ON_W2R_IN_DRAM_ARB__SHIFT 0x17 634895c1f7aaSFeifei Xu #define MMEA1_MISC__SWITCH_CS_ON_W2R_IN_GMI_ARB__SHIFT 0x18 634995c1f7aaSFeifei Xu #define MMEA1_MISC__RELATIVE_PRI_IN_DRAM_RD_ARB_MASK 0x00000001L 635095c1f7aaSFeifei Xu #define MMEA1_MISC__RELATIVE_PRI_IN_DRAM_WR_ARB_MASK 0x00000002L 635195c1f7aaSFeifei Xu #define MMEA1_MISC__RELATIVE_PRI_IN_GMI_RD_ARB_MASK 0x00000004L 635295c1f7aaSFeifei Xu #define MMEA1_MISC__RELATIVE_PRI_IN_GMI_WR_ARB_MASK 0x00000008L 635395c1f7aaSFeifei Xu #define MMEA1_MISC__RELATIVE_PRI_IN_IO_RD_ARB_MASK 0x00000010L 635495c1f7aaSFeifei Xu #define MMEA1_MISC__RELATIVE_PRI_IN_IO_WR_ARB_MASK 0x00000020L 635595c1f7aaSFeifei Xu #define MMEA1_MISC__RRET_SWAP_MODE_MASK 0x00000040L 635695c1f7aaSFeifei Xu #define MMEA1_MISC__EARLY_SDP_ORIGDATA_MASK 0x00000080L 635795c1f7aaSFeifei Xu #define MMEA1_MISC__LINKMGR_DYNAMIC_MODE_MASK 0x00000300L 635895c1f7aaSFeifei Xu #define MMEA1_MISC__LINKMGR_HALT_THRESHOLD_MASK 0x00000C00L 635995c1f7aaSFeifei Xu #define MMEA1_MISC__LINKMGR_RECONNECT_DELAY_MASK 0x00003000L 636095c1f7aaSFeifei Xu #define MMEA1_MISC__LINKMGR_IDLE_THRESHOLD_MASK 0x0007C000L 636195c1f7aaSFeifei Xu #define MMEA1_MISC__FAVOUR_MIDCHAIN_CS_IN_DRAM_ARB_MASK 0x00080000L 636295c1f7aaSFeifei Xu #define MMEA1_MISC__FAVOUR_MIDCHAIN_CS_IN_GMI_ARB_MASK 0x00100000L 636395c1f7aaSFeifei Xu #define MMEA1_MISC__FAVOUR_LAST_CS_IN_DRAM_ARB_MASK 0x00200000L 636495c1f7aaSFeifei Xu #define MMEA1_MISC__FAVOUR_LAST_CS_IN_GMI_ARB_MASK 0x00400000L 636595c1f7aaSFeifei Xu #define MMEA1_MISC__SWITCH_CS_ON_W2R_IN_DRAM_ARB_MASK 0x00800000L 636695c1f7aaSFeifei Xu #define MMEA1_MISC__SWITCH_CS_ON_W2R_IN_GMI_ARB_MASK 0x01000000L 636795c1f7aaSFeifei Xu //MMEA1_LATENCY_SAMPLING 636895c1f7aaSFeifei Xu #define MMEA1_LATENCY_SAMPLING__SAMPLER0_DRAM__SHIFT 0x0 636995c1f7aaSFeifei Xu #define MMEA1_LATENCY_SAMPLING__SAMPLER1_DRAM__SHIFT 0x1 637095c1f7aaSFeifei Xu #define MMEA1_LATENCY_SAMPLING__SAMPLER0_GMI__SHIFT 0x2 637195c1f7aaSFeifei Xu #define MMEA1_LATENCY_SAMPLING__SAMPLER1_GMI__SHIFT 0x3 637295c1f7aaSFeifei Xu #define MMEA1_LATENCY_SAMPLING__SAMPLER0_IO__SHIFT 0x4 637395c1f7aaSFeifei Xu #define MMEA1_LATENCY_SAMPLING__SAMPLER1_IO__SHIFT 0x5 637495c1f7aaSFeifei Xu #define MMEA1_LATENCY_SAMPLING__SAMPLER0_READ__SHIFT 0x6 637595c1f7aaSFeifei Xu #define MMEA1_LATENCY_SAMPLING__SAMPLER1_READ__SHIFT 0x7 637695c1f7aaSFeifei Xu #define MMEA1_LATENCY_SAMPLING__SAMPLER0_WRITE__SHIFT 0x8 637795c1f7aaSFeifei Xu #define MMEA1_LATENCY_SAMPLING__SAMPLER1_WRITE__SHIFT 0x9 637895c1f7aaSFeifei Xu #define MMEA1_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET__SHIFT 0xa 637995c1f7aaSFeifei Xu #define MMEA1_LATENCY_SAMPLING__SAMPLER1_ATOMIC_RET__SHIFT 0xb 638095c1f7aaSFeifei Xu #define MMEA1_LATENCY_SAMPLING__SAMPLER0_ATOMIC_NORET__SHIFT 0xc 638195c1f7aaSFeifei Xu #define MMEA1_LATENCY_SAMPLING__SAMPLER1_ATOMIC_NORET__SHIFT 0xd 638295c1f7aaSFeifei Xu #define MMEA1_LATENCY_SAMPLING__SAMPLER0_VC__SHIFT 0xe 638395c1f7aaSFeifei Xu #define MMEA1_LATENCY_SAMPLING__SAMPLER1_VC__SHIFT 0x16 638495c1f7aaSFeifei Xu #define MMEA1_LATENCY_SAMPLING__SAMPLER0_DRAM_MASK 0x00000001L 638595c1f7aaSFeifei Xu #define MMEA1_LATENCY_SAMPLING__SAMPLER1_DRAM_MASK 0x00000002L 638695c1f7aaSFeifei Xu #define MMEA1_LATENCY_SAMPLING__SAMPLER0_GMI_MASK 0x00000004L 638795c1f7aaSFeifei Xu #define MMEA1_LATENCY_SAMPLING__SAMPLER1_GMI_MASK 0x00000008L 638895c1f7aaSFeifei Xu #define MMEA1_LATENCY_SAMPLING__SAMPLER0_IO_MASK 0x00000010L 638995c1f7aaSFeifei Xu #define MMEA1_LATENCY_SAMPLING__SAMPLER1_IO_MASK 0x00000020L 639095c1f7aaSFeifei Xu #define MMEA1_LATENCY_SAMPLING__SAMPLER0_READ_MASK 0x00000040L 639195c1f7aaSFeifei Xu #define MMEA1_LATENCY_SAMPLING__SAMPLER1_READ_MASK 0x00000080L 639295c1f7aaSFeifei Xu #define MMEA1_LATENCY_SAMPLING__SAMPLER0_WRITE_MASK 0x00000100L 639395c1f7aaSFeifei Xu #define MMEA1_LATENCY_SAMPLING__SAMPLER1_WRITE_MASK 0x00000200L 639495c1f7aaSFeifei Xu #define MMEA1_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET_MASK 0x00000400L 639595c1f7aaSFeifei Xu #define MMEA1_LATENCY_SAMPLING__SAMPLER1_ATOMIC_RET_MASK 0x00000800L 639695c1f7aaSFeifei Xu #define MMEA1_LATENCY_SAMPLING__SAMPLER0_ATOMIC_NORET_MASK 0x00001000L 639795c1f7aaSFeifei Xu #define MMEA1_LATENCY_SAMPLING__SAMPLER1_ATOMIC_NORET_MASK 0x00002000L 639895c1f7aaSFeifei Xu #define MMEA1_LATENCY_SAMPLING__SAMPLER0_VC_MASK 0x003FC000L 639995c1f7aaSFeifei Xu #define MMEA1_LATENCY_SAMPLING__SAMPLER1_VC_MASK 0x3FC00000L 640095c1f7aaSFeifei Xu //MMEA1_PERFCOUNTER_LO 640195c1f7aaSFeifei Xu #define MMEA1_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 640295c1f7aaSFeifei Xu #define MMEA1_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL 640395c1f7aaSFeifei Xu //MMEA1_PERFCOUNTER_HI 640495c1f7aaSFeifei Xu #define MMEA1_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 640595c1f7aaSFeifei Xu #define MMEA1_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 640695c1f7aaSFeifei Xu #define MMEA1_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL 640795c1f7aaSFeifei Xu #define MMEA1_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L 640895c1f7aaSFeifei Xu //MMEA1_PERFCOUNTER0_CFG 640995c1f7aaSFeifei Xu #define MMEA1_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 641095c1f7aaSFeifei Xu #define MMEA1_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 641195c1f7aaSFeifei Xu #define MMEA1_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 641295c1f7aaSFeifei Xu #define MMEA1_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c 641395c1f7aaSFeifei Xu #define MMEA1_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d 641495c1f7aaSFeifei Xu #define MMEA1_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL 641595c1f7aaSFeifei Xu #define MMEA1_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L 641695c1f7aaSFeifei Xu #define MMEA1_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L 641795c1f7aaSFeifei Xu #define MMEA1_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L 641895c1f7aaSFeifei Xu #define MMEA1_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L 641995c1f7aaSFeifei Xu //MMEA1_PERFCOUNTER1_CFG 642095c1f7aaSFeifei Xu #define MMEA1_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 642195c1f7aaSFeifei Xu #define MMEA1_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 642295c1f7aaSFeifei Xu #define MMEA1_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 642395c1f7aaSFeifei Xu #define MMEA1_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c 642495c1f7aaSFeifei Xu #define MMEA1_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d 642595c1f7aaSFeifei Xu #define MMEA1_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL 642695c1f7aaSFeifei Xu #define MMEA1_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L 642795c1f7aaSFeifei Xu #define MMEA1_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L 642895c1f7aaSFeifei Xu #define MMEA1_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L 642995c1f7aaSFeifei Xu #define MMEA1_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L 643095c1f7aaSFeifei Xu //MMEA1_PERFCOUNTER_RSLT_CNTL 643195c1f7aaSFeifei Xu #define MMEA1_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 643295c1f7aaSFeifei Xu #define MMEA1_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 643395c1f7aaSFeifei Xu #define MMEA1_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 643495c1f7aaSFeifei Xu #define MMEA1_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 643595c1f7aaSFeifei Xu #define MMEA1_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 643695c1f7aaSFeifei Xu #define MMEA1_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a 643795c1f7aaSFeifei Xu #define MMEA1_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL 643895c1f7aaSFeifei Xu #define MMEA1_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L 643995c1f7aaSFeifei Xu #define MMEA1_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L 644095c1f7aaSFeifei Xu #define MMEA1_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L 644195c1f7aaSFeifei Xu #define MMEA1_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L 644295c1f7aaSFeifei Xu #define MMEA1_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L 644395c1f7aaSFeifei Xu //MMEA1_EDC_CNT 644495c1f7aaSFeifei Xu #define MMEA1_EDC_CNT__DRAMRD_CMDMEM_SEC_COUNT__SHIFT 0x0 644595c1f7aaSFeifei Xu #define MMEA1_EDC_CNT__DRAMRD_CMDMEM_DED_COUNT__SHIFT 0x2 644695c1f7aaSFeifei Xu #define MMEA1_EDC_CNT__DRAMWR_CMDMEM_SEC_COUNT__SHIFT 0x4 644795c1f7aaSFeifei Xu #define MMEA1_EDC_CNT__DRAMWR_CMDMEM_DED_COUNT__SHIFT 0x6 644895c1f7aaSFeifei Xu #define MMEA1_EDC_CNT__DRAMWR_DATAMEM_SEC_COUNT__SHIFT 0x8 644995c1f7aaSFeifei Xu #define MMEA1_EDC_CNT__DRAMWR_DATAMEM_DED_COUNT__SHIFT 0xa 645095c1f7aaSFeifei Xu #define MMEA1_EDC_CNT__RRET_TAGMEM_SEC_COUNT__SHIFT 0xc 645195c1f7aaSFeifei Xu #define MMEA1_EDC_CNT__RRET_TAGMEM_DED_COUNT__SHIFT 0xe 645295c1f7aaSFeifei Xu #define MMEA1_EDC_CNT__WRET_TAGMEM_SEC_COUNT__SHIFT 0x10 645395c1f7aaSFeifei Xu #define MMEA1_EDC_CNT__WRET_TAGMEM_DED_COUNT__SHIFT 0x12 645495c1f7aaSFeifei Xu #define MMEA1_EDC_CNT__DRAMRD_PAGEMEM_SED_COUNT__SHIFT 0x14 645595c1f7aaSFeifei Xu #define MMEA1_EDC_CNT__DRAMWR_PAGEMEM_SED_COUNT__SHIFT 0x16 645695c1f7aaSFeifei Xu #define MMEA1_EDC_CNT__IORD_CMDMEM_SED_COUNT__SHIFT 0x18 645795c1f7aaSFeifei Xu #define MMEA1_EDC_CNT__IOWR_CMDMEM_SED_COUNT__SHIFT 0x1a 645895c1f7aaSFeifei Xu #define MMEA1_EDC_CNT__IOWR_DATAMEM_SED_COUNT__SHIFT 0x1c 645995c1f7aaSFeifei Xu #define MMEA1_EDC_CNT__DRAMRD_CMDMEM_SEC_COUNT_MASK 0x00000003L 646095c1f7aaSFeifei Xu #define MMEA1_EDC_CNT__DRAMRD_CMDMEM_DED_COUNT_MASK 0x0000000CL 646195c1f7aaSFeifei Xu #define MMEA1_EDC_CNT__DRAMWR_CMDMEM_SEC_COUNT_MASK 0x00000030L 646295c1f7aaSFeifei Xu #define MMEA1_EDC_CNT__DRAMWR_CMDMEM_DED_COUNT_MASK 0x000000C0L 646395c1f7aaSFeifei Xu #define MMEA1_EDC_CNT__DRAMWR_DATAMEM_SEC_COUNT_MASK 0x00000300L 646495c1f7aaSFeifei Xu #define MMEA1_EDC_CNT__DRAMWR_DATAMEM_DED_COUNT_MASK 0x00000C00L 646595c1f7aaSFeifei Xu #define MMEA1_EDC_CNT__RRET_TAGMEM_SEC_COUNT_MASK 0x00003000L 646695c1f7aaSFeifei Xu #define MMEA1_EDC_CNT__RRET_TAGMEM_DED_COUNT_MASK 0x0000C000L 646795c1f7aaSFeifei Xu #define MMEA1_EDC_CNT__WRET_TAGMEM_SEC_COUNT_MASK 0x00030000L 646895c1f7aaSFeifei Xu #define MMEA1_EDC_CNT__WRET_TAGMEM_DED_COUNT_MASK 0x000C0000L 646995c1f7aaSFeifei Xu #define MMEA1_EDC_CNT__DRAMRD_PAGEMEM_SED_COUNT_MASK 0x00300000L 647095c1f7aaSFeifei Xu #define MMEA1_EDC_CNT__DRAMWR_PAGEMEM_SED_COUNT_MASK 0x00C00000L 647195c1f7aaSFeifei Xu #define MMEA1_EDC_CNT__IORD_CMDMEM_SED_COUNT_MASK 0x03000000L 647295c1f7aaSFeifei Xu #define MMEA1_EDC_CNT__IOWR_CMDMEM_SED_COUNT_MASK 0x0C000000L 647395c1f7aaSFeifei Xu #define MMEA1_EDC_CNT__IOWR_DATAMEM_SED_COUNT_MASK 0x30000000L 647495c1f7aaSFeifei Xu //MMEA1_EDC_CNT2 647595c1f7aaSFeifei Xu #define MMEA1_EDC_CNT2__GMIRD_CMDMEM_SEC_COUNT__SHIFT 0x0 647695c1f7aaSFeifei Xu #define MMEA1_EDC_CNT2__GMIRD_CMDMEM_DED_COUNT__SHIFT 0x2 647795c1f7aaSFeifei Xu #define MMEA1_EDC_CNT2__GMIWR_CMDMEM_SEC_COUNT__SHIFT 0x4 647895c1f7aaSFeifei Xu #define MMEA1_EDC_CNT2__GMIWR_CMDMEM_DED_COUNT__SHIFT 0x6 647995c1f7aaSFeifei Xu #define MMEA1_EDC_CNT2__GMIWR_DATAMEM_SEC_COUNT__SHIFT 0x8 648095c1f7aaSFeifei Xu #define MMEA1_EDC_CNT2__GMIWR_DATAMEM_DED_COUNT__SHIFT 0xa 648195c1f7aaSFeifei Xu #define MMEA1_EDC_CNT2__GMIRD_PAGEMEM_SED_COUNT__SHIFT 0xc 648295c1f7aaSFeifei Xu #define MMEA1_EDC_CNT2__GMIWR_PAGEMEM_SED_COUNT__SHIFT 0xe 648395c1f7aaSFeifei Xu #define MMEA1_EDC_CNT2__GMIRD_CMDMEM_SEC_COUNT_MASK 0x00000003L 648495c1f7aaSFeifei Xu #define MMEA1_EDC_CNT2__GMIRD_CMDMEM_DED_COUNT_MASK 0x0000000CL 648595c1f7aaSFeifei Xu #define MMEA1_EDC_CNT2__GMIWR_CMDMEM_SEC_COUNT_MASK 0x00000030L 648695c1f7aaSFeifei Xu #define MMEA1_EDC_CNT2__GMIWR_CMDMEM_DED_COUNT_MASK 0x000000C0L 648795c1f7aaSFeifei Xu #define MMEA1_EDC_CNT2__GMIWR_DATAMEM_SEC_COUNT_MASK 0x00000300L 648895c1f7aaSFeifei Xu #define MMEA1_EDC_CNT2__GMIWR_DATAMEM_DED_COUNT_MASK 0x00000C00L 648995c1f7aaSFeifei Xu #define MMEA1_EDC_CNT2__GMIRD_PAGEMEM_SED_COUNT_MASK 0x00003000L 649095c1f7aaSFeifei Xu #define MMEA1_EDC_CNT2__GMIWR_PAGEMEM_SED_COUNT_MASK 0x0000C000L 649195c1f7aaSFeifei Xu //MMEA1_DSM_CNTL 649295c1f7aaSFeifei Xu #define MMEA1_DSM_CNTL__DRAMRD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x0 649395c1f7aaSFeifei Xu #define MMEA1_DSM_CNTL__DRAMRD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x2 649495c1f7aaSFeifei Xu #define MMEA1_DSM_CNTL__DRAMWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x3 649595c1f7aaSFeifei Xu #define MMEA1_DSM_CNTL__DRAMWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x5 649695c1f7aaSFeifei Xu #define MMEA1_DSM_CNTL__DRAMWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT 0x6 649795c1f7aaSFeifei Xu #define MMEA1_DSM_CNTL__DRAMWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT 0x8 649895c1f7aaSFeifei Xu #define MMEA1_DSM_CNTL__RRET_TAGMEM_DSM_IRRITATOR_DATA__SHIFT 0x9 649995c1f7aaSFeifei Xu #define MMEA1_DSM_CNTL__RRET_TAGMEM_ENABLE_SINGLE_WRITE__SHIFT 0xb 650095c1f7aaSFeifei Xu #define MMEA1_DSM_CNTL__WRET_TAGMEM_DSM_IRRITATOR_DATA__SHIFT 0xc 650195c1f7aaSFeifei Xu #define MMEA1_DSM_CNTL__WRET_TAGMEM_ENABLE_SINGLE_WRITE__SHIFT 0xe 650295c1f7aaSFeifei Xu #define MMEA1_DSM_CNTL__GMIRD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0xf 650395c1f7aaSFeifei Xu #define MMEA1_DSM_CNTL__GMIRD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x11 650495c1f7aaSFeifei Xu #define MMEA1_DSM_CNTL__GMIWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x12 650595c1f7aaSFeifei Xu #define MMEA1_DSM_CNTL__GMIWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x14 650695c1f7aaSFeifei Xu #define MMEA1_DSM_CNTL__GMIWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT 0x15 650795c1f7aaSFeifei Xu #define MMEA1_DSM_CNTL__GMIWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT 0x17 650895c1f7aaSFeifei Xu #define MMEA1_DSM_CNTL__DRAMRD_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00000003L 650995c1f7aaSFeifei Xu #define MMEA1_DSM_CNTL__DRAMRD_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000004L 651095c1f7aaSFeifei Xu #define MMEA1_DSM_CNTL__DRAMWR_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00000018L 651195c1f7aaSFeifei Xu #define MMEA1_DSM_CNTL__DRAMWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000020L 651295c1f7aaSFeifei Xu #define MMEA1_DSM_CNTL__DRAMWR_DATAMEM_DSM_IRRITATOR_DATA_MASK 0x000000C0L 651395c1f7aaSFeifei Xu #define MMEA1_DSM_CNTL__DRAMWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK 0x00000100L 651495c1f7aaSFeifei Xu #define MMEA1_DSM_CNTL__RRET_TAGMEM_DSM_IRRITATOR_DATA_MASK 0x00000600L 651595c1f7aaSFeifei Xu #define MMEA1_DSM_CNTL__RRET_TAGMEM_ENABLE_SINGLE_WRITE_MASK 0x00000800L 651695c1f7aaSFeifei Xu #define MMEA1_DSM_CNTL__WRET_TAGMEM_DSM_IRRITATOR_DATA_MASK 0x00003000L 651795c1f7aaSFeifei Xu #define MMEA1_DSM_CNTL__WRET_TAGMEM_ENABLE_SINGLE_WRITE_MASK 0x00004000L 651895c1f7aaSFeifei Xu #define MMEA1_DSM_CNTL__GMIRD_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00018000L 651995c1f7aaSFeifei Xu #define MMEA1_DSM_CNTL__GMIRD_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00020000L 652095c1f7aaSFeifei Xu #define MMEA1_DSM_CNTL__GMIWR_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x000C0000L 652195c1f7aaSFeifei Xu #define MMEA1_DSM_CNTL__GMIWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00100000L 652295c1f7aaSFeifei Xu #define MMEA1_DSM_CNTL__GMIWR_DATAMEM_DSM_IRRITATOR_DATA_MASK 0x00600000L 652395c1f7aaSFeifei Xu #define MMEA1_DSM_CNTL__GMIWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK 0x00800000L 652495c1f7aaSFeifei Xu //MMEA1_DSM_CNTLA 652595c1f7aaSFeifei Xu #define MMEA1_DSM_CNTLA__DRAMRD_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0x0 652695c1f7aaSFeifei Xu #define MMEA1_DSM_CNTLA__DRAMRD_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x2 652795c1f7aaSFeifei Xu #define MMEA1_DSM_CNTLA__DRAMWR_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0x3 652895c1f7aaSFeifei Xu #define MMEA1_DSM_CNTLA__DRAMWR_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x5 652995c1f7aaSFeifei Xu #define MMEA1_DSM_CNTLA__IORD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x6 653095c1f7aaSFeifei Xu #define MMEA1_DSM_CNTLA__IORD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x8 653195c1f7aaSFeifei Xu #define MMEA1_DSM_CNTLA__IOWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x9 653295c1f7aaSFeifei Xu #define MMEA1_DSM_CNTLA__IOWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0xb 653395c1f7aaSFeifei Xu #define MMEA1_DSM_CNTLA__IOWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT 0xc 653495c1f7aaSFeifei Xu #define MMEA1_DSM_CNTLA__IOWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT 0xe 653595c1f7aaSFeifei Xu #define MMEA1_DSM_CNTLA__GMIRD_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0xf 653695c1f7aaSFeifei Xu #define MMEA1_DSM_CNTLA__GMIRD_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x11 653795c1f7aaSFeifei Xu #define MMEA1_DSM_CNTLA__GMIWR_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0x12 653895c1f7aaSFeifei Xu #define MMEA1_DSM_CNTLA__GMIWR_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x14 653995c1f7aaSFeifei Xu #define MMEA1_DSM_CNTLA__DRAMRD_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x00000003L 654095c1f7aaSFeifei Xu #define MMEA1_DSM_CNTLA__DRAMRD_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00000004L 654195c1f7aaSFeifei Xu #define MMEA1_DSM_CNTLA__DRAMWR_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x00000018L 654295c1f7aaSFeifei Xu #define MMEA1_DSM_CNTLA__DRAMWR_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00000020L 654395c1f7aaSFeifei Xu #define MMEA1_DSM_CNTLA__IORD_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x000000C0L 654495c1f7aaSFeifei Xu #define MMEA1_DSM_CNTLA__IORD_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000100L 654595c1f7aaSFeifei Xu #define MMEA1_DSM_CNTLA__IOWR_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00000600L 654695c1f7aaSFeifei Xu #define MMEA1_DSM_CNTLA__IOWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000800L 654795c1f7aaSFeifei Xu #define MMEA1_DSM_CNTLA__IOWR_DATAMEM_DSM_IRRITATOR_DATA_MASK 0x00003000L 654895c1f7aaSFeifei Xu #define MMEA1_DSM_CNTLA__IOWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK 0x00004000L 654995c1f7aaSFeifei Xu #define MMEA1_DSM_CNTLA__GMIRD_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x00018000L 655095c1f7aaSFeifei Xu #define MMEA1_DSM_CNTLA__GMIRD_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00020000L 655195c1f7aaSFeifei Xu #define MMEA1_DSM_CNTLA__GMIWR_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x000C0000L 655295c1f7aaSFeifei Xu #define MMEA1_DSM_CNTLA__GMIWR_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00100000L 655395c1f7aaSFeifei Xu //MMEA1_DSM_CNTLB 655495c1f7aaSFeifei Xu //MMEA1_DSM_CNTL2 655595c1f7aaSFeifei Xu #define MMEA1_DSM_CNTL2__DRAMRD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x0 655695c1f7aaSFeifei Xu #define MMEA1_DSM_CNTL2__DRAMRD_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x2 655795c1f7aaSFeifei Xu #define MMEA1_DSM_CNTL2__DRAMWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x3 655895c1f7aaSFeifei Xu #define MMEA1_DSM_CNTL2__DRAMWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x5 655995c1f7aaSFeifei Xu #define MMEA1_DSM_CNTL2__DRAMWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT 0x6 656095c1f7aaSFeifei Xu #define MMEA1_DSM_CNTL2__DRAMWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT 0x8 656195c1f7aaSFeifei Xu #define MMEA1_DSM_CNTL2__RRET_TAGMEM_ENABLE_ERROR_INJECT__SHIFT 0x9 656295c1f7aaSFeifei Xu #define MMEA1_DSM_CNTL2__RRET_TAGMEM_SELECT_INJECT_DELAY__SHIFT 0xb 656395c1f7aaSFeifei Xu #define MMEA1_DSM_CNTL2__WRET_TAGMEM_ENABLE_ERROR_INJECT__SHIFT 0xc 656495c1f7aaSFeifei Xu #define MMEA1_DSM_CNTL2__WRET_TAGMEM_SELECT_INJECT_DELAY__SHIFT 0xe 656595c1f7aaSFeifei Xu #define MMEA1_DSM_CNTL2__GMIRD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0xf 656695c1f7aaSFeifei Xu #define MMEA1_DSM_CNTL2__GMIRD_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x11 656795c1f7aaSFeifei Xu #define MMEA1_DSM_CNTL2__GMIWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x12 656895c1f7aaSFeifei Xu #define MMEA1_DSM_CNTL2__GMIWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x14 656995c1f7aaSFeifei Xu #define MMEA1_DSM_CNTL2__GMIWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT 0x15 657095c1f7aaSFeifei Xu #define MMEA1_DSM_CNTL2__GMIWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT 0x17 657195c1f7aaSFeifei Xu #define MMEA1_DSM_CNTL2__INJECT_DELAY__SHIFT 0x1a 657295c1f7aaSFeifei Xu #define MMEA1_DSM_CNTL2__DRAMRD_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00000003L 657395c1f7aaSFeifei Xu #define MMEA1_DSM_CNTL2__DRAMRD_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000004L 657495c1f7aaSFeifei Xu #define MMEA1_DSM_CNTL2__DRAMWR_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00000018L 657595c1f7aaSFeifei Xu #define MMEA1_DSM_CNTL2__DRAMWR_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000020L 657695c1f7aaSFeifei Xu #define MMEA1_DSM_CNTL2__DRAMWR_DATAMEM_ENABLE_ERROR_INJECT_MASK 0x000000C0L 657795c1f7aaSFeifei Xu #define MMEA1_DSM_CNTL2__DRAMWR_DATAMEM_SELECT_INJECT_DELAY_MASK 0x00000100L 657895c1f7aaSFeifei Xu #define MMEA1_DSM_CNTL2__RRET_TAGMEM_ENABLE_ERROR_INJECT_MASK 0x00000600L 657995c1f7aaSFeifei Xu #define MMEA1_DSM_CNTL2__RRET_TAGMEM_SELECT_INJECT_DELAY_MASK 0x00000800L 658095c1f7aaSFeifei Xu #define MMEA1_DSM_CNTL2__WRET_TAGMEM_ENABLE_ERROR_INJECT_MASK 0x00003000L 658195c1f7aaSFeifei Xu #define MMEA1_DSM_CNTL2__WRET_TAGMEM_SELECT_INJECT_DELAY_MASK 0x00004000L 658295c1f7aaSFeifei Xu #define MMEA1_DSM_CNTL2__GMIRD_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00018000L 658395c1f7aaSFeifei Xu #define MMEA1_DSM_CNTL2__GMIRD_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00020000L 658495c1f7aaSFeifei Xu #define MMEA1_DSM_CNTL2__GMIWR_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x000C0000L 658595c1f7aaSFeifei Xu #define MMEA1_DSM_CNTL2__GMIWR_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00100000L 658695c1f7aaSFeifei Xu #define MMEA1_DSM_CNTL2__GMIWR_DATAMEM_ENABLE_ERROR_INJECT_MASK 0x00600000L 658795c1f7aaSFeifei Xu #define MMEA1_DSM_CNTL2__GMIWR_DATAMEM_SELECT_INJECT_DELAY_MASK 0x00800000L 658895c1f7aaSFeifei Xu #define MMEA1_DSM_CNTL2__INJECT_DELAY_MASK 0xFC000000L 658995c1f7aaSFeifei Xu //MMEA1_DSM_CNTL2A 659095c1f7aaSFeifei Xu #define MMEA1_DSM_CNTL2A__DRAMRD_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0x0 659195c1f7aaSFeifei Xu #define MMEA1_DSM_CNTL2A__DRAMRD_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x2 659295c1f7aaSFeifei Xu #define MMEA1_DSM_CNTL2A__DRAMWR_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0x3 659395c1f7aaSFeifei Xu #define MMEA1_DSM_CNTL2A__DRAMWR_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x5 659495c1f7aaSFeifei Xu #define MMEA1_DSM_CNTL2A__IORD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x6 659595c1f7aaSFeifei Xu #define MMEA1_DSM_CNTL2A__IORD_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x8 659695c1f7aaSFeifei Xu #define MMEA1_DSM_CNTL2A__IOWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x9 659795c1f7aaSFeifei Xu #define MMEA1_DSM_CNTL2A__IOWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0xb 659895c1f7aaSFeifei Xu #define MMEA1_DSM_CNTL2A__IOWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT 0xc 659995c1f7aaSFeifei Xu #define MMEA1_DSM_CNTL2A__IOWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT 0xe 660095c1f7aaSFeifei Xu #define MMEA1_DSM_CNTL2A__GMIRD_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0xf 660195c1f7aaSFeifei Xu #define MMEA1_DSM_CNTL2A__GMIRD_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x11 660295c1f7aaSFeifei Xu #define MMEA1_DSM_CNTL2A__GMIWR_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0x12 660395c1f7aaSFeifei Xu #define MMEA1_DSM_CNTL2A__GMIWR_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x14 660495c1f7aaSFeifei Xu #define MMEA1_DSM_CNTL2A__DRAMRD_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x00000003L 660595c1f7aaSFeifei Xu #define MMEA1_DSM_CNTL2A__DRAMRD_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00000004L 660695c1f7aaSFeifei Xu #define MMEA1_DSM_CNTL2A__DRAMWR_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x00000018L 660795c1f7aaSFeifei Xu #define MMEA1_DSM_CNTL2A__DRAMWR_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00000020L 660895c1f7aaSFeifei Xu #define MMEA1_DSM_CNTL2A__IORD_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x000000C0L 660995c1f7aaSFeifei Xu #define MMEA1_DSM_CNTL2A__IORD_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000100L 661095c1f7aaSFeifei Xu #define MMEA1_DSM_CNTL2A__IOWR_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00000600L 661195c1f7aaSFeifei Xu #define MMEA1_DSM_CNTL2A__IOWR_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000800L 661295c1f7aaSFeifei Xu #define MMEA1_DSM_CNTL2A__IOWR_DATAMEM_ENABLE_ERROR_INJECT_MASK 0x00003000L 661395c1f7aaSFeifei Xu #define MMEA1_DSM_CNTL2A__IOWR_DATAMEM_SELECT_INJECT_DELAY_MASK 0x00004000L 661495c1f7aaSFeifei Xu #define MMEA1_DSM_CNTL2A__GMIRD_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x00018000L 661595c1f7aaSFeifei Xu #define MMEA1_DSM_CNTL2A__GMIRD_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00020000L 661695c1f7aaSFeifei Xu #define MMEA1_DSM_CNTL2A__GMIWR_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x000C0000L 661795c1f7aaSFeifei Xu #define MMEA1_DSM_CNTL2A__GMIWR_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00100000L 661895c1f7aaSFeifei Xu //MMEA1_DSM_CNTL2B 661995c1f7aaSFeifei Xu //MMEA1_CGTT_CLK_CTRL 662095c1f7aaSFeifei Xu #define MMEA1_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 662195c1f7aaSFeifei Xu #define MMEA1_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 662295c1f7aaSFeifei Xu #define MMEA1_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16 662395c1f7aaSFeifei Xu #define MMEA1_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b 662495c1f7aaSFeifei Xu #define MMEA1_CGTT_CLK_CTRL__SOFT_OVERRIDE_WRITE__SHIFT 0x1c 662595c1f7aaSFeifei Xu #define MMEA1_CGTT_CLK_CTRL__SOFT_OVERRIDE_READ__SHIFT 0x1d 662695c1f7aaSFeifei Xu #define MMEA1_CGTT_CLK_CTRL__SOFT_OVERRIDE_RETURN__SHIFT 0x1e 662795c1f7aaSFeifei Xu #define MMEA1_CGTT_CLK_CTRL__SOFT_OVERRIDE_REGISTER__SHIFT 0x1f 662895c1f7aaSFeifei Xu #define MMEA1_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL 662995c1f7aaSFeifei Xu #define MMEA1_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L 663095c1f7aaSFeifei Xu #define MMEA1_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L 663195c1f7aaSFeifei Xu #define MMEA1_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L 663295c1f7aaSFeifei Xu #define MMEA1_CGTT_CLK_CTRL__SOFT_OVERRIDE_WRITE_MASK 0x10000000L 663395c1f7aaSFeifei Xu #define MMEA1_CGTT_CLK_CTRL__SOFT_OVERRIDE_READ_MASK 0x20000000L 663495c1f7aaSFeifei Xu #define MMEA1_CGTT_CLK_CTRL__SOFT_OVERRIDE_RETURN_MASK 0x40000000L 663595c1f7aaSFeifei Xu #define MMEA1_CGTT_CLK_CTRL__SOFT_OVERRIDE_REGISTER_MASK 0x80000000L 663695c1f7aaSFeifei Xu //MMEA1_EDC_MODE 663795c1f7aaSFeifei Xu #define MMEA1_EDC_MODE__COUNT_FED_OUT__SHIFT 0x10 663895c1f7aaSFeifei Xu #define MMEA1_EDC_MODE__GATE_FUE__SHIFT 0x11 663995c1f7aaSFeifei Xu #define MMEA1_EDC_MODE__DED_MODE__SHIFT 0x14 664095c1f7aaSFeifei Xu #define MMEA1_EDC_MODE__PROP_FED__SHIFT 0x1d 664195c1f7aaSFeifei Xu #define MMEA1_EDC_MODE__BYPASS__SHIFT 0x1f 664295c1f7aaSFeifei Xu #define MMEA1_EDC_MODE__COUNT_FED_OUT_MASK 0x00010000L 664395c1f7aaSFeifei Xu #define MMEA1_EDC_MODE__GATE_FUE_MASK 0x00020000L 664495c1f7aaSFeifei Xu #define MMEA1_EDC_MODE__DED_MODE_MASK 0x00300000L 664595c1f7aaSFeifei Xu #define MMEA1_EDC_MODE__PROP_FED_MASK 0x20000000L 664695c1f7aaSFeifei Xu #define MMEA1_EDC_MODE__BYPASS_MASK 0x80000000L 664795c1f7aaSFeifei Xu //MMEA1_ERR_STATUS 664895c1f7aaSFeifei Xu #define MMEA1_ERR_STATUS__SDP_RDRSP_STATUS__SHIFT 0x0 664995c1f7aaSFeifei Xu #define MMEA1_ERR_STATUS__SDP_WRRSP_STATUS__SHIFT 0x4 665095c1f7aaSFeifei Xu #define MMEA1_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR__SHIFT 0x8 665195c1f7aaSFeifei Xu #define MMEA1_ERR_STATUS__CLEAR_ERROR_STATUS__SHIFT 0x9 665295c1f7aaSFeifei Xu #define MMEA1_ERR_STATUS__BUSY_ON_ERROR__SHIFT 0xa 665395c1f7aaSFeifei Xu #define MMEA1_ERR_STATUS__SDP_RDRSP_STATUS_MASK 0x0000000FL 665495c1f7aaSFeifei Xu #define MMEA1_ERR_STATUS__SDP_WRRSP_STATUS_MASK 0x000000F0L 665595c1f7aaSFeifei Xu #define MMEA1_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR_MASK 0x00000100L 665695c1f7aaSFeifei Xu #define MMEA1_ERR_STATUS__CLEAR_ERROR_STATUS_MASK 0x00000200L 665795c1f7aaSFeifei Xu #define MMEA1_ERR_STATUS__BUSY_ON_ERROR_MASK 0x00000400L 665895c1f7aaSFeifei Xu //MMEA1_MISC2 665995c1f7aaSFeifei Xu #define MMEA1_MISC2__CSGROUP_SWAP_IN_DRAM_ARB__SHIFT 0x0 666095c1f7aaSFeifei Xu #define MMEA1_MISC2__CSGROUP_SWAP_IN_GMI_ARB__SHIFT 0x1 666195c1f7aaSFeifei Xu #define MMEA1_MISC2__CSGRP_BURST_LIMIT_DATA_DRAM__SHIFT 0x2 666295c1f7aaSFeifei Xu #define MMEA1_MISC2__CSGRP_BURST_LIMIT_DATA_GMI__SHIFT 0x7 666395c1f7aaSFeifei Xu #define MMEA1_MISC2__CSGROUP_SWAP_IN_DRAM_ARB_MASK 0x00000001L 666495c1f7aaSFeifei Xu #define MMEA1_MISC2__CSGROUP_SWAP_IN_GMI_ARB_MASK 0x00000002L 666595c1f7aaSFeifei Xu #define MMEA1_MISC2__CSGRP_BURST_LIMIT_DATA_DRAM_MASK 0x0000007CL 666695c1f7aaSFeifei Xu #define MMEA1_MISC2__CSGRP_BURST_LIMIT_DATA_GMI_MASK 0x00000F80L 666795c1f7aaSFeifei Xu 666895c1f7aaSFeifei Xu 666995c1f7aaSFeifei Xu // addressBlock: mmhub_pctldec 667095c1f7aaSFeifei Xu //PCTL_MISC 667195c1f7aaSFeifei Xu #define PCTL_MISC__ALLOW_DEEP_SLEEP_MODE__SHIFT 0x0 667295c1f7aaSFeifei Xu #define PCTL_MISC__STCTRL_RSMU_IDLE_THRESHOLD__SHIFT 0x3 667395c1f7aaSFeifei Xu #define PCTL_MISC__STCTRL_DAGB_IDLE_THRESHOLD__SHIFT 0x6 667495c1f7aaSFeifei Xu #define PCTL_MISC__STCTRL_IGNORE_PROTECTION_FAULT__SHIFT 0xb 667595c1f7aaSFeifei Xu #define PCTL_MISC__IGNORE_EA0_SDP_ACK__SHIFT 0xc 667695c1f7aaSFeifei Xu #define PCTL_MISC__IGNORE_EA1_SDP_ACK__SHIFT 0xd 667795c1f7aaSFeifei Xu #define PCTL_MISC__PGFSM_CMD_STATUS__SHIFT 0xe 667895c1f7aaSFeifei Xu #define PCTL_MISC__ALLOW_DEEP_SLEEP_MODE_MASK 0x00000007L 667995c1f7aaSFeifei Xu #define PCTL_MISC__STCTRL_RSMU_IDLE_THRESHOLD_MASK 0x00000038L 668095c1f7aaSFeifei Xu #define PCTL_MISC__STCTRL_DAGB_IDLE_THRESHOLD_MASK 0x000007C0L 668195c1f7aaSFeifei Xu #define PCTL_MISC__STCTRL_IGNORE_PROTECTION_FAULT_MASK 0x00000800L 668295c1f7aaSFeifei Xu #define PCTL_MISC__IGNORE_EA0_SDP_ACK_MASK 0x00001000L 668395c1f7aaSFeifei Xu #define PCTL_MISC__IGNORE_EA1_SDP_ACK_MASK 0x00002000L 668495c1f7aaSFeifei Xu #define PCTL_MISC__PGFSM_CMD_STATUS_MASK 0x0000C000L 668595c1f7aaSFeifei Xu //PCTL_MMHUB_DEEPSLEEP 668695c1f7aaSFeifei Xu #define PCTL_MMHUB_DEEPSLEEP__DS0__SHIFT 0x0 668795c1f7aaSFeifei Xu #define PCTL_MMHUB_DEEPSLEEP__DS1__SHIFT 0x1 668895c1f7aaSFeifei Xu #define PCTL_MMHUB_DEEPSLEEP__DS2__SHIFT 0x2 668995c1f7aaSFeifei Xu #define PCTL_MMHUB_DEEPSLEEP__DS3__SHIFT 0x3 669095c1f7aaSFeifei Xu #define PCTL_MMHUB_DEEPSLEEP__DS4__SHIFT 0x4 669195c1f7aaSFeifei Xu #define PCTL_MMHUB_DEEPSLEEP__DS5__SHIFT 0x5 669295c1f7aaSFeifei Xu #define PCTL_MMHUB_DEEPSLEEP__DS6__SHIFT 0x6 669395c1f7aaSFeifei Xu #define PCTL_MMHUB_DEEPSLEEP__DS7__SHIFT 0x7 669495c1f7aaSFeifei Xu #define PCTL_MMHUB_DEEPSLEEP__DS8__SHIFT 0x8 669595c1f7aaSFeifei Xu #define PCTL_MMHUB_DEEPSLEEP__DS9__SHIFT 0x9 669695c1f7aaSFeifei Xu #define PCTL_MMHUB_DEEPSLEEP__DS10__SHIFT 0xa 669795c1f7aaSFeifei Xu #define PCTL_MMHUB_DEEPSLEEP__DS11__SHIFT 0xb 669895c1f7aaSFeifei Xu #define PCTL_MMHUB_DEEPSLEEP__DS12__SHIFT 0xc 669995c1f7aaSFeifei Xu #define PCTL_MMHUB_DEEPSLEEP__DS13__SHIFT 0xd 670095c1f7aaSFeifei Xu #define PCTL_MMHUB_DEEPSLEEP__DS14__SHIFT 0xe 670195c1f7aaSFeifei Xu #define PCTL_MMHUB_DEEPSLEEP__DS15__SHIFT 0xf 670295c1f7aaSFeifei Xu #define PCTL_MMHUB_DEEPSLEEP__DS16__SHIFT 0x10 670395c1f7aaSFeifei Xu #define PCTL_MMHUB_DEEPSLEEP__SETCLEAR__SHIFT 0x1f 670495c1f7aaSFeifei Xu #define PCTL_MMHUB_DEEPSLEEP__DS0_MASK 0x00000001L 670595c1f7aaSFeifei Xu #define PCTL_MMHUB_DEEPSLEEP__DS1_MASK 0x00000002L 670695c1f7aaSFeifei Xu #define PCTL_MMHUB_DEEPSLEEP__DS2_MASK 0x00000004L 670795c1f7aaSFeifei Xu #define PCTL_MMHUB_DEEPSLEEP__DS3_MASK 0x00000008L 670895c1f7aaSFeifei Xu #define PCTL_MMHUB_DEEPSLEEP__DS4_MASK 0x00000010L 670995c1f7aaSFeifei Xu #define PCTL_MMHUB_DEEPSLEEP__DS5_MASK 0x00000020L 671095c1f7aaSFeifei Xu #define PCTL_MMHUB_DEEPSLEEP__DS6_MASK 0x00000040L 671195c1f7aaSFeifei Xu #define PCTL_MMHUB_DEEPSLEEP__DS7_MASK 0x00000080L 671295c1f7aaSFeifei Xu #define PCTL_MMHUB_DEEPSLEEP__DS8_MASK 0x00000100L 671395c1f7aaSFeifei Xu #define PCTL_MMHUB_DEEPSLEEP__DS9_MASK 0x00000200L 671495c1f7aaSFeifei Xu #define PCTL_MMHUB_DEEPSLEEP__DS10_MASK 0x00000400L 671595c1f7aaSFeifei Xu #define PCTL_MMHUB_DEEPSLEEP__DS11_MASK 0x00000800L 671695c1f7aaSFeifei Xu #define PCTL_MMHUB_DEEPSLEEP__DS12_MASK 0x00001000L 671795c1f7aaSFeifei Xu #define PCTL_MMHUB_DEEPSLEEP__DS13_MASK 0x00002000L 671895c1f7aaSFeifei Xu #define PCTL_MMHUB_DEEPSLEEP__DS14_MASK 0x00004000L 671995c1f7aaSFeifei Xu #define PCTL_MMHUB_DEEPSLEEP__DS15_MASK 0x00008000L 672095c1f7aaSFeifei Xu #define PCTL_MMHUB_DEEPSLEEP__DS16_MASK 0x00010000L 672195c1f7aaSFeifei Xu #define PCTL_MMHUB_DEEPSLEEP__SETCLEAR_MASK 0x80000000L 672295c1f7aaSFeifei Xu //PCTL_MMHUB_DEEPSLEEP_OVERRIDE 672395c1f7aaSFeifei Xu #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS0__SHIFT 0x0 672495c1f7aaSFeifei Xu #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS1__SHIFT 0x1 672595c1f7aaSFeifei Xu #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS2__SHIFT 0x2 672695c1f7aaSFeifei Xu #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS3__SHIFT 0x3 672795c1f7aaSFeifei Xu #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS4__SHIFT 0x4 672895c1f7aaSFeifei Xu #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS5__SHIFT 0x5 672995c1f7aaSFeifei Xu #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS6__SHIFT 0x6 673095c1f7aaSFeifei Xu #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS7__SHIFT 0x7 673195c1f7aaSFeifei Xu #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS8__SHIFT 0x8 673295c1f7aaSFeifei Xu #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS9__SHIFT 0x9 673395c1f7aaSFeifei Xu #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS10__SHIFT 0xa 673495c1f7aaSFeifei Xu #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS11__SHIFT 0xb 673595c1f7aaSFeifei Xu #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS12__SHIFT 0xc 673695c1f7aaSFeifei Xu #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS13__SHIFT 0xd 673795c1f7aaSFeifei Xu #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS14__SHIFT 0xe 673895c1f7aaSFeifei Xu #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS15__SHIFT 0xf 673995c1f7aaSFeifei Xu #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS16__SHIFT 0x10 674095c1f7aaSFeifei Xu #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS0_MASK 0x00000001L 674195c1f7aaSFeifei Xu #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS1_MASK 0x00000002L 674295c1f7aaSFeifei Xu #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS2_MASK 0x00000004L 674395c1f7aaSFeifei Xu #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS3_MASK 0x00000008L 674495c1f7aaSFeifei Xu #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS4_MASK 0x00000010L 674595c1f7aaSFeifei Xu #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS5_MASK 0x00000020L 674695c1f7aaSFeifei Xu #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS6_MASK 0x00000040L 674795c1f7aaSFeifei Xu #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS7_MASK 0x00000080L 674895c1f7aaSFeifei Xu #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS8_MASK 0x00000100L 674995c1f7aaSFeifei Xu #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS9_MASK 0x00000200L 675095c1f7aaSFeifei Xu #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS10_MASK 0x00000400L 675195c1f7aaSFeifei Xu #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS11_MASK 0x00000800L 675295c1f7aaSFeifei Xu #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS12_MASK 0x00001000L 675395c1f7aaSFeifei Xu #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS13_MASK 0x00002000L 675495c1f7aaSFeifei Xu #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS14_MASK 0x00004000L 675595c1f7aaSFeifei Xu #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS15_MASK 0x00008000L 675695c1f7aaSFeifei Xu #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS16_MASK 0x00010000L 675795c1f7aaSFeifei Xu //PCTL_PG_IGNORE_DEEPSLEEP 675895c1f7aaSFeifei Xu #define PCTL_PG_IGNORE_DEEPSLEEP__ALLIPS__SHIFT 0x0 675995c1f7aaSFeifei Xu #define PCTL_PG_IGNORE_DEEPSLEEP__DS0__SHIFT 0x1 676095c1f7aaSFeifei Xu #define PCTL_PG_IGNORE_DEEPSLEEP__DS1__SHIFT 0x2 676195c1f7aaSFeifei Xu #define PCTL_PG_IGNORE_DEEPSLEEP__DS2__SHIFT 0x3 676295c1f7aaSFeifei Xu #define PCTL_PG_IGNORE_DEEPSLEEP__DS3__SHIFT 0x4 676395c1f7aaSFeifei Xu #define PCTL_PG_IGNORE_DEEPSLEEP__DS4__SHIFT 0x5 676495c1f7aaSFeifei Xu #define PCTL_PG_IGNORE_DEEPSLEEP__DS5__SHIFT 0x6 676595c1f7aaSFeifei Xu #define PCTL_PG_IGNORE_DEEPSLEEP__DS6__SHIFT 0x7 676695c1f7aaSFeifei Xu #define PCTL_PG_IGNORE_DEEPSLEEP__DS7__SHIFT 0x8 676795c1f7aaSFeifei Xu #define PCTL_PG_IGNORE_DEEPSLEEP__DS8__SHIFT 0x9 676895c1f7aaSFeifei Xu #define PCTL_PG_IGNORE_DEEPSLEEP__DS9__SHIFT 0xa 676995c1f7aaSFeifei Xu #define PCTL_PG_IGNORE_DEEPSLEEP__DS10__SHIFT 0xb 677095c1f7aaSFeifei Xu #define PCTL_PG_IGNORE_DEEPSLEEP__DS11__SHIFT 0xc 677195c1f7aaSFeifei Xu #define PCTL_PG_IGNORE_DEEPSLEEP__DS12__SHIFT 0xd 677295c1f7aaSFeifei Xu #define PCTL_PG_IGNORE_DEEPSLEEP__DS13__SHIFT 0xe 677395c1f7aaSFeifei Xu #define PCTL_PG_IGNORE_DEEPSLEEP__DS14__SHIFT 0xf 677495c1f7aaSFeifei Xu #define PCTL_PG_IGNORE_DEEPSLEEP__DS15__SHIFT 0x10 677595c1f7aaSFeifei Xu #define PCTL_PG_IGNORE_DEEPSLEEP__DS16__SHIFT 0x11 677695c1f7aaSFeifei Xu #define PCTL_PG_IGNORE_DEEPSLEEP__ALLIPS_MASK 0x00000001L 677795c1f7aaSFeifei Xu #define PCTL_PG_IGNORE_DEEPSLEEP__DS0_MASK 0x00000002L 677895c1f7aaSFeifei Xu #define PCTL_PG_IGNORE_DEEPSLEEP__DS1_MASK 0x00000004L 677995c1f7aaSFeifei Xu #define PCTL_PG_IGNORE_DEEPSLEEP__DS2_MASK 0x00000008L 678095c1f7aaSFeifei Xu #define PCTL_PG_IGNORE_DEEPSLEEP__DS3_MASK 0x00000010L 678195c1f7aaSFeifei Xu #define PCTL_PG_IGNORE_DEEPSLEEP__DS4_MASK 0x00000020L 678295c1f7aaSFeifei Xu #define PCTL_PG_IGNORE_DEEPSLEEP__DS5_MASK 0x00000040L 678395c1f7aaSFeifei Xu #define PCTL_PG_IGNORE_DEEPSLEEP__DS6_MASK 0x00000080L 678495c1f7aaSFeifei Xu #define PCTL_PG_IGNORE_DEEPSLEEP__DS7_MASK 0x00000100L 678595c1f7aaSFeifei Xu #define PCTL_PG_IGNORE_DEEPSLEEP__DS8_MASK 0x00000200L 678695c1f7aaSFeifei Xu #define PCTL_PG_IGNORE_DEEPSLEEP__DS9_MASK 0x00000400L 678795c1f7aaSFeifei Xu #define PCTL_PG_IGNORE_DEEPSLEEP__DS10_MASK 0x00000800L 678895c1f7aaSFeifei Xu #define PCTL_PG_IGNORE_DEEPSLEEP__DS11_MASK 0x00001000L 678995c1f7aaSFeifei Xu #define PCTL_PG_IGNORE_DEEPSLEEP__DS12_MASK 0x00002000L 679095c1f7aaSFeifei Xu #define PCTL_PG_IGNORE_DEEPSLEEP__DS13_MASK 0x00004000L 679195c1f7aaSFeifei Xu #define PCTL_PG_IGNORE_DEEPSLEEP__DS14_MASK 0x00008000L 679295c1f7aaSFeifei Xu #define PCTL_PG_IGNORE_DEEPSLEEP__DS15_MASK 0x00010000L 679395c1f7aaSFeifei Xu #define PCTL_PG_IGNORE_DEEPSLEEP__DS16_MASK 0x00020000L 679495c1f7aaSFeifei Xu //PCTL_PG_DAGB 679595c1f7aaSFeifei Xu #define PCTL_PG_DAGB__DS0__SHIFT 0x0 679695c1f7aaSFeifei Xu #define PCTL_PG_DAGB__DS1__SHIFT 0x1 679795c1f7aaSFeifei Xu #define PCTL_PG_DAGB__DS2__SHIFT 0x2 679895c1f7aaSFeifei Xu #define PCTL_PG_DAGB__DS3__SHIFT 0x3 679995c1f7aaSFeifei Xu #define PCTL_PG_DAGB__DS4__SHIFT 0x4 680095c1f7aaSFeifei Xu #define PCTL_PG_DAGB__DS5__SHIFT 0x5 680195c1f7aaSFeifei Xu #define PCTL_PG_DAGB__DS6__SHIFT 0x6 680295c1f7aaSFeifei Xu #define PCTL_PG_DAGB__DS7__SHIFT 0x7 680395c1f7aaSFeifei Xu #define PCTL_PG_DAGB__DS8__SHIFT 0x8 680495c1f7aaSFeifei Xu #define PCTL_PG_DAGB__DS9__SHIFT 0x9 680595c1f7aaSFeifei Xu #define PCTL_PG_DAGB__DS10__SHIFT 0xa 680695c1f7aaSFeifei Xu #define PCTL_PG_DAGB__DS11__SHIFT 0xb 680795c1f7aaSFeifei Xu #define PCTL_PG_DAGB__DS12__SHIFT 0xc 680895c1f7aaSFeifei Xu #define PCTL_PG_DAGB__DS13__SHIFT 0xd 680995c1f7aaSFeifei Xu #define PCTL_PG_DAGB__DS14__SHIFT 0xe 681095c1f7aaSFeifei Xu #define PCTL_PG_DAGB__DS15__SHIFT 0xf 681195c1f7aaSFeifei Xu #define PCTL_PG_DAGB__DS16__SHIFT 0x10 681295c1f7aaSFeifei Xu #define PCTL_PG_DAGB__DS0_MASK 0x00000001L 681395c1f7aaSFeifei Xu #define PCTL_PG_DAGB__DS1_MASK 0x00000002L 681495c1f7aaSFeifei Xu #define PCTL_PG_DAGB__DS2_MASK 0x00000004L 681595c1f7aaSFeifei Xu #define PCTL_PG_DAGB__DS3_MASK 0x00000008L 681695c1f7aaSFeifei Xu #define PCTL_PG_DAGB__DS4_MASK 0x00000010L 681795c1f7aaSFeifei Xu #define PCTL_PG_DAGB__DS5_MASK 0x00000020L 681895c1f7aaSFeifei Xu #define PCTL_PG_DAGB__DS6_MASK 0x00000040L 681995c1f7aaSFeifei Xu #define PCTL_PG_DAGB__DS7_MASK 0x00000080L 682095c1f7aaSFeifei Xu #define PCTL_PG_DAGB__DS8_MASK 0x00000100L 682195c1f7aaSFeifei Xu #define PCTL_PG_DAGB__DS9_MASK 0x00000200L 682295c1f7aaSFeifei Xu #define PCTL_PG_DAGB__DS10_MASK 0x00000400L 682395c1f7aaSFeifei Xu #define PCTL_PG_DAGB__DS11_MASK 0x00000800L 682495c1f7aaSFeifei Xu #define PCTL_PG_DAGB__DS12_MASK 0x00001000L 682595c1f7aaSFeifei Xu #define PCTL_PG_DAGB__DS13_MASK 0x00002000L 682695c1f7aaSFeifei Xu #define PCTL_PG_DAGB__DS14_MASK 0x00004000L 682795c1f7aaSFeifei Xu #define PCTL_PG_DAGB__DS15_MASK 0x00008000L 682895c1f7aaSFeifei Xu #define PCTL_PG_DAGB__DS16_MASK 0x00010000L 682995c1f7aaSFeifei Xu //PCTL0_RENG_RAM_INDEX 683095c1f7aaSFeifei Xu #define PCTL0_RENG_RAM_INDEX__RENG_RAM_INDEX__SHIFT 0x0 683195c1f7aaSFeifei Xu #define PCTL0_RENG_RAM_INDEX__RENG_RAM_INDEX_MASK 0x000007FFL 683295c1f7aaSFeifei Xu //PCTL0_RENG_RAM_DATA 683395c1f7aaSFeifei Xu #define PCTL0_RENG_RAM_DATA__RENG_RAM_DATA__SHIFT 0x0 683495c1f7aaSFeifei Xu #define PCTL0_RENG_RAM_DATA__RENG_RAM_DATA_MASK 0xFFFFFFFFL 683595c1f7aaSFeifei Xu //PCTL0_RENG_EXECUTE 683695c1f7aaSFeifei Xu #define PCTL0_RENG_EXECUTE__RENG_EXECUTE_ON_PWR_UP__SHIFT 0x0 683795c1f7aaSFeifei Xu #define PCTL0_RENG_EXECUTE__RENG_EXECUTE_NOW__SHIFT 0x1 683895c1f7aaSFeifei Xu #define PCTL0_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE__SHIFT 0x2 683995c1f7aaSFeifei Xu #define PCTL0_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR__SHIFT 0x3 684095c1f7aaSFeifei Xu #define PCTL0_RENG_EXECUTE__RENG_EXECUTE_END_PTR__SHIFT 0xe 684195c1f7aaSFeifei Xu #define PCTL0_RENG_EXECUTE__RENG_EXECUTE_ON_REG_UPDATE__SHIFT 0x19 684295c1f7aaSFeifei Xu #define PCTL0_RENG_EXECUTE__RENG_EXECUTE_ON_PWR_UP_MASK 0x00000001L 684395c1f7aaSFeifei Xu #define PCTL0_RENG_EXECUTE__RENG_EXECUTE_NOW_MASK 0x00000002L 684495c1f7aaSFeifei Xu #define PCTL0_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE_MASK 0x00000004L 684595c1f7aaSFeifei Xu #define PCTL0_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR_MASK 0x00003FF8L 684695c1f7aaSFeifei Xu #define PCTL0_RENG_EXECUTE__RENG_EXECUTE_END_PTR_MASK 0x01FFC000L 684795c1f7aaSFeifei Xu #define PCTL0_RENG_EXECUTE__RENG_EXECUTE_ON_REG_UPDATE_MASK 0x02000000L 684895c1f7aaSFeifei Xu //PCTL0_MISC 684995c1f7aaSFeifei Xu #define PCTL0_MISC__CRITICAL_REGS_LOCK__SHIFT 0xb 685095c1f7aaSFeifei Xu #define PCTL0_MISC__TILE_IDLE_THRESHOLD__SHIFT 0xc 685195c1f7aaSFeifei Xu #define PCTL0_MISC__RENG_MEM_LS_ENABLE__SHIFT 0xf 685295c1f7aaSFeifei Xu #define PCTL0_MISC__STCTRL_FORCE_PGFSM_CMD_DONE__SHIFT 0x10 685395c1f7aaSFeifei Xu #define PCTL0_MISC__CRITICAL_REGS_LOCK_MASK 0x00000800L 685495c1f7aaSFeifei Xu #define PCTL0_MISC__TILE_IDLE_THRESHOLD_MASK 0x00007000L 685595c1f7aaSFeifei Xu #define PCTL0_MISC__RENG_MEM_LS_ENABLE_MASK 0x00008000L 685695c1f7aaSFeifei Xu #define PCTL0_MISC__STCTRL_FORCE_PGFSM_CMD_DONE_MASK 0x00010000L 685795c1f7aaSFeifei Xu //PCTL0_STCTRL_REGISTER_SAVE_RANGE0 685895c1f7aaSFeifei Xu #define PCTL0_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 685995c1f7aaSFeifei Xu #define PCTL0_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 686095c1f7aaSFeifei Xu #define PCTL0_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL 686195c1f7aaSFeifei Xu #define PCTL0_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L 686295c1f7aaSFeifei Xu //PCTL0_STCTRL_REGISTER_SAVE_RANGE1 686395c1f7aaSFeifei Xu #define PCTL0_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 686495c1f7aaSFeifei Xu #define PCTL0_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 686595c1f7aaSFeifei Xu #define PCTL0_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL 686695c1f7aaSFeifei Xu #define PCTL0_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L 686795c1f7aaSFeifei Xu //PCTL0_STCTRL_REGISTER_SAVE_RANGE2 686895c1f7aaSFeifei Xu #define PCTL0_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 686995c1f7aaSFeifei Xu #define PCTL0_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 687095c1f7aaSFeifei Xu #define PCTL0_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL 687195c1f7aaSFeifei Xu #define PCTL0_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L 687295c1f7aaSFeifei Xu //PCTL0_STCTRL_REGISTER_SAVE_EXCL_SET 687395c1f7aaSFeifei Xu #define PCTL0_STCTRL_REGISTER_SAVE_EXCL_SET__STCTRL_REGISTER_SAVE_EXCL0__SHIFT 0x0 687495c1f7aaSFeifei Xu #define PCTL0_STCTRL_REGISTER_SAVE_EXCL_SET__STCTRL_REGISTER_SAVE_EXCL1__SHIFT 0x10 687595c1f7aaSFeifei Xu #define PCTL0_STCTRL_REGISTER_SAVE_EXCL_SET__STCTRL_REGISTER_SAVE_EXCL0_MASK 0x0000FFFFL 687695c1f7aaSFeifei Xu #define PCTL0_STCTRL_REGISTER_SAVE_EXCL_SET__STCTRL_REGISTER_SAVE_EXCL1_MASK 0xFFFF0000L 687795c1f7aaSFeifei Xu //PCTL0_STCTRL_REGISTER_SAVE_EXCL_SET1 687895c1f7aaSFeifei Xu #define PCTL0_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL2__SHIFT 0x0 687995c1f7aaSFeifei Xu #define PCTL0_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL3__SHIFT 0x10 688095c1f7aaSFeifei Xu #define PCTL0_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL2_MASK 0x0000FFFFL 688195c1f7aaSFeifei Xu #define PCTL0_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL3_MASK 0xFFFF0000L 688295c1f7aaSFeifei Xu //PCTL1_RENG_RAM_INDEX 688395c1f7aaSFeifei Xu #define PCTL1_RENG_RAM_INDEX__RENG_RAM_INDEX__SHIFT 0x0 688495c1f7aaSFeifei Xu #define PCTL1_RENG_RAM_INDEX__RENG_RAM_INDEX_MASK 0x000003FFL 688595c1f7aaSFeifei Xu //PCTL1_RENG_RAM_DATA 688695c1f7aaSFeifei Xu #define PCTL1_RENG_RAM_DATA__RENG_RAM_DATA__SHIFT 0x0 688795c1f7aaSFeifei Xu #define PCTL1_RENG_RAM_DATA__RENG_RAM_DATA_MASK 0xFFFFFFFFL 688895c1f7aaSFeifei Xu //PCTL1_RENG_EXECUTE 688995c1f7aaSFeifei Xu #define PCTL1_RENG_EXECUTE__RENG_EXECUTE_ON_PWR_UP__SHIFT 0x0 689095c1f7aaSFeifei Xu #define PCTL1_RENG_EXECUTE__RENG_EXECUTE_NOW__SHIFT 0x1 689195c1f7aaSFeifei Xu #define PCTL1_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE__SHIFT 0x2 689295c1f7aaSFeifei Xu #define PCTL1_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR__SHIFT 0x3 689395c1f7aaSFeifei Xu #define PCTL1_RENG_EXECUTE__RENG_EXECUTE_END_PTR__SHIFT 0xd 689495c1f7aaSFeifei Xu #define PCTL1_RENG_EXECUTE__RENG_EXECUTE_ON_REG_UPDATE__SHIFT 0x17 689595c1f7aaSFeifei Xu #define PCTL1_RENG_EXECUTE__RENG_EXECUTE_ON_PWR_UP_MASK 0x00000001L 689695c1f7aaSFeifei Xu #define PCTL1_RENG_EXECUTE__RENG_EXECUTE_NOW_MASK 0x00000002L 689795c1f7aaSFeifei Xu #define PCTL1_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE_MASK 0x00000004L 689895c1f7aaSFeifei Xu #define PCTL1_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR_MASK 0x00001FF8L 689995c1f7aaSFeifei Xu #define PCTL1_RENG_EXECUTE__RENG_EXECUTE_END_PTR_MASK 0x007FE000L 690095c1f7aaSFeifei Xu #define PCTL1_RENG_EXECUTE__RENG_EXECUTE_ON_REG_UPDATE_MASK 0x00800000L 690195c1f7aaSFeifei Xu //PCTL1_MISC 690295c1f7aaSFeifei Xu #define PCTL1_MISC__CRITICAL_REGS_LOCK__SHIFT 0xa 690395c1f7aaSFeifei Xu #define PCTL1_MISC__TILE_IDLE_THRESHOLD__SHIFT 0xb 690495c1f7aaSFeifei Xu #define PCTL1_MISC__RENG_MEM_LS_ENABLE__SHIFT 0xe 690595c1f7aaSFeifei Xu #define PCTL1_MISC__STCTRL_FORCE_PGFSM_CMD_DONE__SHIFT 0xf 690695c1f7aaSFeifei Xu #define PCTL1_MISC__DEEPSLEEP_DISCSDP__SHIFT 0x10 690795c1f7aaSFeifei Xu #define PCTL1_MISC__CRITICAL_REGS_LOCK_MASK 0x00000400L 690895c1f7aaSFeifei Xu #define PCTL1_MISC__TILE_IDLE_THRESHOLD_MASK 0x00003800L 690995c1f7aaSFeifei Xu #define PCTL1_MISC__RENG_MEM_LS_ENABLE_MASK 0x00004000L 691095c1f7aaSFeifei Xu #define PCTL1_MISC__STCTRL_FORCE_PGFSM_CMD_DONE_MASK 0x00008000L 691195c1f7aaSFeifei Xu #define PCTL1_MISC__DEEPSLEEP_DISCSDP_MASK 0x00010000L 691295c1f7aaSFeifei Xu //PCTL1_STCTRL_REGISTER_SAVE_RANGE0 691395c1f7aaSFeifei Xu #define PCTL1_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 691495c1f7aaSFeifei Xu #define PCTL1_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 691595c1f7aaSFeifei Xu #define PCTL1_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL 691695c1f7aaSFeifei Xu #define PCTL1_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L 691795c1f7aaSFeifei Xu //PCTL1_STCTRL_REGISTER_SAVE_RANGE1 691895c1f7aaSFeifei Xu #define PCTL1_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 691995c1f7aaSFeifei Xu #define PCTL1_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 692095c1f7aaSFeifei Xu #define PCTL1_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL 692195c1f7aaSFeifei Xu #define PCTL1_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L 692295c1f7aaSFeifei Xu //PCTL1_STCTRL_REGISTER_SAVE_RANGE2 692395c1f7aaSFeifei Xu #define PCTL1_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 692495c1f7aaSFeifei Xu #define PCTL1_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 692595c1f7aaSFeifei Xu #define PCTL1_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL 692695c1f7aaSFeifei Xu #define PCTL1_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L 692795c1f7aaSFeifei Xu //PCTL1_STCTRL_REGISTER_SAVE_EXCL_SET 692895c1f7aaSFeifei Xu #define PCTL1_STCTRL_REGISTER_SAVE_EXCL_SET__STCTRL_REGISTER_SAVE_EXCL0__SHIFT 0x0 692995c1f7aaSFeifei Xu #define PCTL1_STCTRL_REGISTER_SAVE_EXCL_SET__STCTRL_REGISTER_SAVE_EXCL1__SHIFT 0x10 693095c1f7aaSFeifei Xu #define PCTL1_STCTRL_REGISTER_SAVE_EXCL_SET__STCTRL_REGISTER_SAVE_EXCL0_MASK 0x0000FFFFL 693195c1f7aaSFeifei Xu #define PCTL1_STCTRL_REGISTER_SAVE_EXCL_SET__STCTRL_REGISTER_SAVE_EXCL1_MASK 0xFFFF0000L 693295c1f7aaSFeifei Xu //PCTL1_STCTRL_REGISTER_SAVE_EXCL_SET1 693395c1f7aaSFeifei Xu #define PCTL1_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL2__SHIFT 0x0 693495c1f7aaSFeifei Xu #define PCTL1_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL3__SHIFT 0x10 693595c1f7aaSFeifei Xu #define PCTL1_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL2_MASK 0x0000FFFFL 693695c1f7aaSFeifei Xu #define PCTL1_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL3_MASK 0xFFFF0000L 693795c1f7aaSFeifei Xu //PCTL2_RENG_RAM_INDEX 693895c1f7aaSFeifei Xu #define PCTL2_RENG_RAM_INDEX__RENG_RAM_INDEX__SHIFT 0x0 693995c1f7aaSFeifei Xu #define PCTL2_RENG_RAM_INDEX__RENG_RAM_INDEX_MASK 0x000003FFL 694095c1f7aaSFeifei Xu //PCTL2_RENG_RAM_DATA 694195c1f7aaSFeifei Xu #define PCTL2_RENG_RAM_DATA__RENG_RAM_DATA__SHIFT 0x0 694295c1f7aaSFeifei Xu #define PCTL2_RENG_RAM_DATA__RENG_RAM_DATA_MASK 0xFFFFFFFFL 694395c1f7aaSFeifei Xu //PCTL2_RENG_EXECUTE 694495c1f7aaSFeifei Xu #define PCTL2_RENG_EXECUTE__RENG_EXECUTE_ON_PWR_UP__SHIFT 0x0 694595c1f7aaSFeifei Xu #define PCTL2_RENG_EXECUTE__RENG_EXECUTE_NOW__SHIFT 0x1 694695c1f7aaSFeifei Xu #define PCTL2_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE__SHIFT 0x2 694795c1f7aaSFeifei Xu #define PCTL2_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR__SHIFT 0x3 694895c1f7aaSFeifei Xu #define PCTL2_RENG_EXECUTE__RENG_EXECUTE_END_PTR__SHIFT 0xd 694995c1f7aaSFeifei Xu #define PCTL2_RENG_EXECUTE__RENG_EXECUTE_ON_REG_UPDATE__SHIFT 0x17 695095c1f7aaSFeifei Xu #define PCTL2_RENG_EXECUTE__RENG_EXECUTE_ON_PWR_UP_MASK 0x00000001L 695195c1f7aaSFeifei Xu #define PCTL2_RENG_EXECUTE__RENG_EXECUTE_NOW_MASK 0x00000002L 695295c1f7aaSFeifei Xu #define PCTL2_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE_MASK 0x00000004L 695395c1f7aaSFeifei Xu #define PCTL2_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR_MASK 0x00001FF8L 695495c1f7aaSFeifei Xu #define PCTL2_RENG_EXECUTE__RENG_EXECUTE_END_PTR_MASK 0x007FE000L 695595c1f7aaSFeifei Xu #define PCTL2_RENG_EXECUTE__RENG_EXECUTE_ON_REG_UPDATE_MASK 0x00800000L 695695c1f7aaSFeifei Xu //PCTL2_MISC 695795c1f7aaSFeifei Xu #define PCTL2_MISC__CRITICAL_REGS_LOCK__SHIFT 0xa 695895c1f7aaSFeifei Xu #define PCTL2_MISC__TILE_IDLE_THRESHOLD__SHIFT 0xb 695995c1f7aaSFeifei Xu #define PCTL2_MISC__RENG_MEM_LS_ENABLE__SHIFT 0xe 696095c1f7aaSFeifei Xu #define PCTL2_MISC__STCTRL_FORCE_PGFSM_CMD_DONE__SHIFT 0xf 696195c1f7aaSFeifei Xu #define PCTL2_MISC__DEEPSLEEP_DISCSDP__SHIFT 0x10 696295c1f7aaSFeifei Xu #define PCTL2_MISC__CRITICAL_REGS_LOCK_MASK 0x00000400L 696395c1f7aaSFeifei Xu #define PCTL2_MISC__TILE_IDLE_THRESHOLD_MASK 0x00003800L 696495c1f7aaSFeifei Xu #define PCTL2_MISC__RENG_MEM_LS_ENABLE_MASK 0x00004000L 696595c1f7aaSFeifei Xu #define PCTL2_MISC__STCTRL_FORCE_PGFSM_CMD_DONE_MASK 0x00008000L 696695c1f7aaSFeifei Xu #define PCTL2_MISC__DEEPSLEEP_DISCSDP_MASK 0x00010000L 696795c1f7aaSFeifei Xu //PCTL2_STCTRL_REGISTER_SAVE_RANGE0 696895c1f7aaSFeifei Xu #define PCTL2_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 696995c1f7aaSFeifei Xu #define PCTL2_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 697095c1f7aaSFeifei Xu #define PCTL2_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL 697195c1f7aaSFeifei Xu #define PCTL2_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L 697295c1f7aaSFeifei Xu //PCTL2_STCTRL_REGISTER_SAVE_RANGE1 697395c1f7aaSFeifei Xu #define PCTL2_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 697495c1f7aaSFeifei Xu #define PCTL2_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 697595c1f7aaSFeifei Xu #define PCTL2_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL 697695c1f7aaSFeifei Xu #define PCTL2_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L 697795c1f7aaSFeifei Xu //PCTL2_STCTRL_REGISTER_SAVE_RANGE2 697895c1f7aaSFeifei Xu #define PCTL2_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 697995c1f7aaSFeifei Xu #define PCTL2_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 698095c1f7aaSFeifei Xu #define PCTL2_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL 698195c1f7aaSFeifei Xu #define PCTL2_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L 698295c1f7aaSFeifei Xu //PCTL2_STCTRL_REGISTER_SAVE_EXCL_SET 698395c1f7aaSFeifei Xu #define PCTL2_STCTRL_REGISTER_SAVE_EXCL_SET__STCTRL_REGISTER_SAVE_EXCL0__SHIFT 0x0 698495c1f7aaSFeifei Xu #define PCTL2_STCTRL_REGISTER_SAVE_EXCL_SET__STCTRL_REGISTER_SAVE_EXCL1__SHIFT 0x10 698595c1f7aaSFeifei Xu #define PCTL2_STCTRL_REGISTER_SAVE_EXCL_SET__STCTRL_REGISTER_SAVE_EXCL0_MASK 0x0000FFFFL 698695c1f7aaSFeifei Xu #define PCTL2_STCTRL_REGISTER_SAVE_EXCL_SET__STCTRL_REGISTER_SAVE_EXCL1_MASK 0xFFFF0000L 698795c1f7aaSFeifei Xu //PCTL2_STCTRL_REGISTER_SAVE_EXCL_SET1 698895c1f7aaSFeifei Xu #define PCTL2_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL2__SHIFT 0x0 698995c1f7aaSFeifei Xu #define PCTL2_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL3__SHIFT 0x10 699095c1f7aaSFeifei Xu #define PCTL2_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL2_MASK 0x0000FFFFL 699195c1f7aaSFeifei Xu #define PCTL2_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL3_MASK 0xFFFF0000L 699295c1f7aaSFeifei Xu 699395c1f7aaSFeifei Xu 699495c1f7aaSFeifei Xu // addressBlock: mmhub_l1tlb_vml1dec 699595c1f7aaSFeifei Xu //MC_VM_MX_L1_TLB0_STATUS 699695c1f7aaSFeifei Xu #define MC_VM_MX_L1_TLB0_STATUS__BUSY__SHIFT 0x0 699795c1f7aaSFeifei Xu #define MC_VM_MX_L1_TLB0_STATUS__FOUND_PARITY_ERRORS__SHIFT 0x1 699895c1f7aaSFeifei Xu #define MC_VM_MX_L1_TLB0_STATUS__BUSY_MASK 0x00000001L 699995c1f7aaSFeifei Xu #define MC_VM_MX_L1_TLB0_STATUS__FOUND_PARITY_ERRORS_MASK 0x00000002L 700095c1f7aaSFeifei Xu //MC_VM_MX_L1_TLB1_STATUS 700195c1f7aaSFeifei Xu #define MC_VM_MX_L1_TLB1_STATUS__BUSY__SHIFT 0x0 700295c1f7aaSFeifei Xu #define MC_VM_MX_L1_TLB1_STATUS__FOUND_PARITY_ERRORS__SHIFT 0x1 700395c1f7aaSFeifei Xu #define MC_VM_MX_L1_TLB1_STATUS__BUSY_MASK 0x00000001L 700495c1f7aaSFeifei Xu #define MC_VM_MX_L1_TLB1_STATUS__FOUND_PARITY_ERRORS_MASK 0x00000002L 700595c1f7aaSFeifei Xu //MC_VM_MX_L1_TLB2_STATUS 700695c1f7aaSFeifei Xu #define MC_VM_MX_L1_TLB2_STATUS__BUSY__SHIFT 0x0 700795c1f7aaSFeifei Xu #define MC_VM_MX_L1_TLB2_STATUS__FOUND_PARITY_ERRORS__SHIFT 0x1 700895c1f7aaSFeifei Xu #define MC_VM_MX_L1_TLB2_STATUS__BUSY_MASK 0x00000001L 700995c1f7aaSFeifei Xu #define MC_VM_MX_L1_TLB2_STATUS__FOUND_PARITY_ERRORS_MASK 0x00000002L 701095c1f7aaSFeifei Xu //MC_VM_MX_L1_TLB3_STATUS 701195c1f7aaSFeifei Xu #define MC_VM_MX_L1_TLB3_STATUS__BUSY__SHIFT 0x0 701295c1f7aaSFeifei Xu #define MC_VM_MX_L1_TLB3_STATUS__FOUND_PARITY_ERRORS__SHIFT 0x1 701395c1f7aaSFeifei Xu #define MC_VM_MX_L1_TLB3_STATUS__BUSY_MASK 0x00000001L 701495c1f7aaSFeifei Xu #define MC_VM_MX_L1_TLB3_STATUS__FOUND_PARITY_ERRORS_MASK 0x00000002L 701595c1f7aaSFeifei Xu //MC_VM_MX_L1_TLB4_STATUS 701695c1f7aaSFeifei Xu #define MC_VM_MX_L1_TLB4_STATUS__BUSY__SHIFT 0x0 701795c1f7aaSFeifei Xu #define MC_VM_MX_L1_TLB4_STATUS__FOUND_PARITY_ERRORS__SHIFT 0x1 701895c1f7aaSFeifei Xu #define MC_VM_MX_L1_TLB4_STATUS__BUSY_MASK 0x00000001L 701995c1f7aaSFeifei Xu #define MC_VM_MX_L1_TLB4_STATUS__FOUND_PARITY_ERRORS_MASK 0x00000002L 702095c1f7aaSFeifei Xu //MC_VM_MX_L1_TLB5_STATUS 702195c1f7aaSFeifei Xu #define MC_VM_MX_L1_TLB5_STATUS__BUSY__SHIFT 0x0 702295c1f7aaSFeifei Xu #define MC_VM_MX_L1_TLB5_STATUS__FOUND_PARITY_ERRORS__SHIFT 0x1 702395c1f7aaSFeifei Xu #define MC_VM_MX_L1_TLB5_STATUS__BUSY_MASK 0x00000001L 702495c1f7aaSFeifei Xu #define MC_VM_MX_L1_TLB5_STATUS__FOUND_PARITY_ERRORS_MASK 0x00000002L 702595c1f7aaSFeifei Xu //MC_VM_MX_L1_TLB6_STATUS 702695c1f7aaSFeifei Xu #define MC_VM_MX_L1_TLB6_STATUS__BUSY__SHIFT 0x0 702795c1f7aaSFeifei Xu #define MC_VM_MX_L1_TLB6_STATUS__FOUND_PARITY_ERRORS__SHIFT 0x1 702895c1f7aaSFeifei Xu #define MC_VM_MX_L1_TLB6_STATUS__BUSY_MASK 0x00000001L 702995c1f7aaSFeifei Xu #define MC_VM_MX_L1_TLB6_STATUS__FOUND_PARITY_ERRORS_MASK 0x00000002L 703095c1f7aaSFeifei Xu //MC_VM_MX_L1_TLB7_STATUS 703195c1f7aaSFeifei Xu #define MC_VM_MX_L1_TLB7_STATUS__BUSY__SHIFT 0x0 703295c1f7aaSFeifei Xu #define MC_VM_MX_L1_TLB7_STATUS__FOUND_PARITY_ERRORS__SHIFT 0x1 703395c1f7aaSFeifei Xu #define MC_VM_MX_L1_TLB7_STATUS__BUSY_MASK 0x00000001L 703495c1f7aaSFeifei Xu #define MC_VM_MX_L1_TLB7_STATUS__FOUND_PARITY_ERRORS_MASK 0x00000002L 703595c1f7aaSFeifei Xu 703695c1f7aaSFeifei Xu 703795c1f7aaSFeifei Xu // addressBlock: mmhub_l1tlb_vml1pldec 703895c1f7aaSFeifei Xu //MC_VM_MX_L1_PERFCOUNTER0_CFG 703995c1f7aaSFeifei Xu #define MC_VM_MX_L1_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 704095c1f7aaSFeifei Xu #define MC_VM_MX_L1_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 704195c1f7aaSFeifei Xu #define MC_VM_MX_L1_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 704295c1f7aaSFeifei Xu #define MC_VM_MX_L1_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c 704395c1f7aaSFeifei Xu #define MC_VM_MX_L1_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d 704495c1f7aaSFeifei Xu #define MC_VM_MX_L1_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL 704595c1f7aaSFeifei Xu #define MC_VM_MX_L1_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L 704695c1f7aaSFeifei Xu #define MC_VM_MX_L1_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L 704795c1f7aaSFeifei Xu #define MC_VM_MX_L1_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L 704895c1f7aaSFeifei Xu #define MC_VM_MX_L1_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L 704995c1f7aaSFeifei Xu //MC_VM_MX_L1_PERFCOUNTER1_CFG 705095c1f7aaSFeifei Xu #define MC_VM_MX_L1_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 705195c1f7aaSFeifei Xu #define MC_VM_MX_L1_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 705295c1f7aaSFeifei Xu #define MC_VM_MX_L1_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 705395c1f7aaSFeifei Xu #define MC_VM_MX_L1_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c 705495c1f7aaSFeifei Xu #define MC_VM_MX_L1_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d 705595c1f7aaSFeifei Xu #define MC_VM_MX_L1_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL 705695c1f7aaSFeifei Xu #define MC_VM_MX_L1_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L 705795c1f7aaSFeifei Xu #define MC_VM_MX_L1_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L 705895c1f7aaSFeifei Xu #define MC_VM_MX_L1_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L 705995c1f7aaSFeifei Xu #define MC_VM_MX_L1_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L 706095c1f7aaSFeifei Xu //MC_VM_MX_L1_PERFCOUNTER2_CFG 706195c1f7aaSFeifei Xu #define MC_VM_MX_L1_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0 706295c1f7aaSFeifei Xu #define MC_VM_MX_L1_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8 706395c1f7aaSFeifei Xu #define MC_VM_MX_L1_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18 706495c1f7aaSFeifei Xu #define MC_VM_MX_L1_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c 706595c1f7aaSFeifei Xu #define MC_VM_MX_L1_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d 706695c1f7aaSFeifei Xu #define MC_VM_MX_L1_PERFCOUNTER2_CFG__PERF_SEL_MASK 0x000000FFL 706795c1f7aaSFeifei Xu #define MC_VM_MX_L1_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0x0000FF00L 706895c1f7aaSFeifei Xu #define MC_VM_MX_L1_PERFCOUNTER2_CFG__PERF_MODE_MASK 0x0F000000L 706995c1f7aaSFeifei Xu #define MC_VM_MX_L1_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000L 707095c1f7aaSFeifei Xu #define MC_VM_MX_L1_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000L 707195c1f7aaSFeifei Xu //MC_VM_MX_L1_PERFCOUNTER3_CFG 707295c1f7aaSFeifei Xu #define MC_VM_MX_L1_PERFCOUNTER3_CFG__PERF_SEL__SHIFT 0x0 707395c1f7aaSFeifei Xu #define MC_VM_MX_L1_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT 0x8 707495c1f7aaSFeifei Xu #define MC_VM_MX_L1_PERFCOUNTER3_CFG__PERF_MODE__SHIFT 0x18 707595c1f7aaSFeifei Xu #define MC_VM_MX_L1_PERFCOUNTER3_CFG__ENABLE__SHIFT 0x1c 707695c1f7aaSFeifei Xu #define MC_VM_MX_L1_PERFCOUNTER3_CFG__CLEAR__SHIFT 0x1d 707795c1f7aaSFeifei Xu #define MC_VM_MX_L1_PERFCOUNTER3_CFG__PERF_SEL_MASK 0x000000FFL 707895c1f7aaSFeifei Xu #define MC_VM_MX_L1_PERFCOUNTER3_CFG__PERF_SEL_END_MASK 0x0000FF00L 707995c1f7aaSFeifei Xu #define MC_VM_MX_L1_PERFCOUNTER3_CFG__PERF_MODE_MASK 0x0F000000L 708095c1f7aaSFeifei Xu #define MC_VM_MX_L1_PERFCOUNTER3_CFG__ENABLE_MASK 0x10000000L 708195c1f7aaSFeifei Xu #define MC_VM_MX_L1_PERFCOUNTER3_CFG__CLEAR_MASK 0x20000000L 708295c1f7aaSFeifei Xu //MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL 708395c1f7aaSFeifei Xu #define MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 708495c1f7aaSFeifei Xu #define MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 708595c1f7aaSFeifei Xu #define MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 708695c1f7aaSFeifei Xu #define MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 708795c1f7aaSFeifei Xu #define MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 708895c1f7aaSFeifei Xu #define MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a 708995c1f7aaSFeifei Xu #define MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL 709095c1f7aaSFeifei Xu #define MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L 709195c1f7aaSFeifei Xu #define MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L 709295c1f7aaSFeifei Xu #define MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L 709395c1f7aaSFeifei Xu #define MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L 709495c1f7aaSFeifei Xu #define MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L 709595c1f7aaSFeifei Xu 709695c1f7aaSFeifei Xu 709795c1f7aaSFeifei Xu // addressBlock: mmhub_l1tlb_vml1prdec 709895c1f7aaSFeifei Xu //MC_VM_MX_L1_PERFCOUNTER_LO 709995c1f7aaSFeifei Xu #define MC_VM_MX_L1_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 710095c1f7aaSFeifei Xu #define MC_VM_MX_L1_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL 710195c1f7aaSFeifei Xu //MC_VM_MX_L1_PERFCOUNTER_HI 710295c1f7aaSFeifei Xu #define MC_VM_MX_L1_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 710395c1f7aaSFeifei Xu #define MC_VM_MX_L1_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 710495c1f7aaSFeifei Xu #define MC_VM_MX_L1_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL 710595c1f7aaSFeifei Xu #define MC_VM_MX_L1_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L 710695c1f7aaSFeifei Xu 710795c1f7aaSFeifei Xu 710895c1f7aaSFeifei Xu // addressBlock: mmhub_l1tlb_vmtlspfdec 710995c1f7aaSFeifei Xu //VM_L2_SAW_CNTL 711095c1f7aaSFeifei Xu #define VM_L2_SAW_CNTL__ENABLE_L2_CACHE__SHIFT 0x0 711195c1f7aaSFeifei Xu #define VM_L2_SAW_CNTL__ENABLE_L2_FRAGMENT_PROCESSING__SHIFT 0x1 711295c1f7aaSFeifei Xu #define VM_L2_SAW_CNTL__L2_CACHE_PTE_ENDIAN_SWAP_MODE__SHIFT 0x2 711395c1f7aaSFeifei Xu #define VM_L2_SAW_CNTL__L2_CACHE_PDE_ENDIAN_SWAP_MODE__SHIFT 0x4 711495c1f7aaSFeifei Xu #define VM_L2_SAW_CNTL__L2_PDE0_CACHE_TAG_GENERATION_MODE__SHIFT 0x8 711595c1f7aaSFeifei Xu #define VM_L2_SAW_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE__SHIFT 0x9 711695c1f7aaSFeifei Xu #define VM_L2_SAW_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE__SHIFT 0xa 711795c1f7aaSFeifei Xu #define VM_L2_SAW_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY__SHIFT 0xb 711895c1f7aaSFeifei Xu #define VM_L2_SAW_CNTL__L2_PDE0_CACHE_SPLIT_MODE__SHIFT 0xc 711995c1f7aaSFeifei Xu #define VM_L2_SAW_CNTL__EFFECTIVE_L2_QUEUE_SIZE__SHIFT 0xf 712095c1f7aaSFeifei Xu #define VM_L2_SAW_CNTL__PDE_FAULT_CLASSIFICATION__SHIFT 0x12 712195c1f7aaSFeifei Xu #define VM_L2_SAW_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE__SHIFT 0x13 712295c1f7aaSFeifei Xu #define VM_L2_SAW_CNTL__IDENTITY_MODE_FRAGMENT_SIZE__SHIFT 0x15 712395c1f7aaSFeifei Xu #define VM_L2_SAW_CNTL__L2_CACHE_4K_SWAP_TAG_INDEX_LSBS__SHIFT 0x1a 712495c1f7aaSFeifei Xu #define VM_L2_SAW_CNTL__L2_CACHE_BIGK_SWAP_TAG_INDEX_LSBS__SHIFT 0x1c 712595c1f7aaSFeifei Xu #define VM_L2_SAW_CNTL__ENABLE_L2_CACHE_MASK 0x00000001L 712695c1f7aaSFeifei Xu #define VM_L2_SAW_CNTL__ENABLE_L2_FRAGMENT_PROCESSING_MASK 0x00000002L 712795c1f7aaSFeifei Xu #define VM_L2_SAW_CNTL__L2_CACHE_PTE_ENDIAN_SWAP_MODE_MASK 0x0000000CL 712895c1f7aaSFeifei Xu #define VM_L2_SAW_CNTL__L2_CACHE_PDE_ENDIAN_SWAP_MODE_MASK 0x00000030L 712995c1f7aaSFeifei Xu #define VM_L2_SAW_CNTL__L2_PDE0_CACHE_TAG_GENERATION_MODE_MASK 0x00000100L 713095c1f7aaSFeifei Xu #define VM_L2_SAW_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE_MASK 0x00000200L 713195c1f7aaSFeifei Xu #define VM_L2_SAW_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE_MASK 0x00000400L 713295c1f7aaSFeifei Xu #define VM_L2_SAW_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY_MASK 0x00000800L 713395c1f7aaSFeifei Xu #define VM_L2_SAW_CNTL__L2_PDE0_CACHE_SPLIT_MODE_MASK 0x00007000L 713495c1f7aaSFeifei Xu #define VM_L2_SAW_CNTL__EFFECTIVE_L2_QUEUE_SIZE_MASK 0x00038000L 713595c1f7aaSFeifei Xu #define VM_L2_SAW_CNTL__PDE_FAULT_CLASSIFICATION_MASK 0x00040000L 713695c1f7aaSFeifei Xu #define VM_L2_SAW_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE_MASK 0x00180000L 713795c1f7aaSFeifei Xu #define VM_L2_SAW_CNTL__IDENTITY_MODE_FRAGMENT_SIZE_MASK 0x03E00000L 713895c1f7aaSFeifei Xu #define VM_L2_SAW_CNTL__L2_CACHE_4K_SWAP_TAG_INDEX_LSBS_MASK 0x0C000000L 713995c1f7aaSFeifei Xu #define VM_L2_SAW_CNTL__L2_CACHE_BIGK_SWAP_TAG_INDEX_LSBS_MASK 0x70000000L 714095c1f7aaSFeifei Xu //VM_L2_SAW_CNTL2 714195c1f7aaSFeifei Xu #define VM_L2_SAW_CNTL2__INVALIDATE_ALL_L1_TLBS__SHIFT 0x0 714295c1f7aaSFeifei Xu #define VM_L2_SAW_CNTL2__INVALIDATE_L2_CACHE__SHIFT 0x1 714395c1f7aaSFeifei Xu #define VM_L2_SAW_CNTL2__DISABLE_INVALIDATE_PER_DOMAIN__SHIFT 0x15 714495c1f7aaSFeifei Xu #define VM_L2_SAW_CNTL2__DISABLE_BIGK_CACHE_OPTIMIZATION__SHIFT 0x16 714595c1f7aaSFeifei Xu #define VM_L2_SAW_CNTL2__L2_CACHE_BIGK_VMID_MODE__SHIFT 0x17 714695c1f7aaSFeifei Xu #define VM_L2_SAW_CNTL2__INVALIDATE_CACHE_MODE__SHIFT 0x1a 714795c1f7aaSFeifei Xu #define VM_L2_SAW_CNTL2__PDE_CACHE_EFFECTIVE_SIZE__SHIFT 0x1c 714895c1f7aaSFeifei Xu #define VM_L2_SAW_CNTL2__INVALIDATE_ALL_L1_TLBS_MASK 0x00000001L 714995c1f7aaSFeifei Xu #define VM_L2_SAW_CNTL2__INVALIDATE_L2_CACHE_MASK 0x00000002L 715095c1f7aaSFeifei Xu #define VM_L2_SAW_CNTL2__DISABLE_INVALIDATE_PER_DOMAIN_MASK 0x00200000L 715195c1f7aaSFeifei Xu #define VM_L2_SAW_CNTL2__DISABLE_BIGK_CACHE_OPTIMIZATION_MASK 0x00400000L 715295c1f7aaSFeifei Xu #define VM_L2_SAW_CNTL2__L2_CACHE_BIGK_VMID_MODE_MASK 0x03800000L 715395c1f7aaSFeifei Xu #define VM_L2_SAW_CNTL2__INVALIDATE_CACHE_MODE_MASK 0x0C000000L 715495c1f7aaSFeifei Xu #define VM_L2_SAW_CNTL2__PDE_CACHE_EFFECTIVE_SIZE_MASK 0x70000000L 715595c1f7aaSFeifei Xu //VM_L2_SAW_CNTL3 715695c1f7aaSFeifei Xu #define VM_L2_SAW_CNTL3__BANK_SELECT__SHIFT 0x0 715795c1f7aaSFeifei Xu #define VM_L2_SAW_CNTL3__L2_CACHE_UPDATE_MODE__SHIFT 0x6 715895c1f7aaSFeifei Xu #define VM_L2_SAW_CNTL3__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE__SHIFT 0x8 715995c1f7aaSFeifei Xu #define VM_L2_SAW_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0xf 716095c1f7aaSFeifei Xu #define VM_L2_SAW_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY__SHIFT 0x14 716195c1f7aaSFeifei Xu #define VM_L2_SAW_CNTL3__L2_CACHE_4K_EFFECTIVE_SIZE__SHIFT 0x15 716295c1f7aaSFeifei Xu #define VM_L2_SAW_CNTL3__L2_CACHE_BIGK_EFFECTIVE_SIZE__SHIFT 0x18 716395c1f7aaSFeifei Xu #define VM_L2_SAW_CNTL3__L2_CACHE_4K_FORCE_MISS__SHIFT 0x1c 716495c1f7aaSFeifei Xu #define VM_L2_SAW_CNTL3__L2_CACHE_BIGK_FORCE_MISS__SHIFT 0x1d 716595c1f7aaSFeifei Xu #define VM_L2_SAW_CNTL3__PDE_CACHE_FORCE_MISS__SHIFT 0x1e 716695c1f7aaSFeifei Xu #define VM_L2_SAW_CNTL3__L2_CACHE_4K_ASSOCIATIVITY__SHIFT 0x1f 716795c1f7aaSFeifei Xu #define VM_L2_SAW_CNTL3__BANK_SELECT_MASK 0x0000003FL 716895c1f7aaSFeifei Xu #define VM_L2_SAW_CNTL3__L2_CACHE_UPDATE_MODE_MASK 0x000000C0L 716995c1f7aaSFeifei Xu #define VM_L2_SAW_CNTL3__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE_MASK 0x00001F00L 717095c1f7aaSFeifei Xu #define VM_L2_SAW_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000F8000L 717195c1f7aaSFeifei Xu #define VM_L2_SAW_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY_MASK 0x00100000L 717295c1f7aaSFeifei Xu #define VM_L2_SAW_CNTL3__L2_CACHE_4K_EFFECTIVE_SIZE_MASK 0x00E00000L 717395c1f7aaSFeifei Xu #define VM_L2_SAW_CNTL3__L2_CACHE_BIGK_EFFECTIVE_SIZE_MASK 0x0F000000L 717495c1f7aaSFeifei Xu #define VM_L2_SAW_CNTL3__L2_CACHE_4K_FORCE_MISS_MASK 0x10000000L 717595c1f7aaSFeifei Xu #define VM_L2_SAW_CNTL3__L2_CACHE_BIGK_FORCE_MISS_MASK 0x20000000L 717695c1f7aaSFeifei Xu #define VM_L2_SAW_CNTL3__PDE_CACHE_FORCE_MISS_MASK 0x40000000L 717795c1f7aaSFeifei Xu #define VM_L2_SAW_CNTL3__L2_CACHE_4K_ASSOCIATIVITY_MASK 0x80000000L 717895c1f7aaSFeifei Xu //VM_L2_SAW_CNTL4 717995c1f7aaSFeifei Xu #define VM_L2_SAW_CNTL4__L2_CACHE_4K_PARTITION_COUNT__SHIFT 0x0 718095c1f7aaSFeifei Xu #define VM_L2_SAW_CNTL4__VMC_TAP_CONTEXT0_PDE_REQUEST_PHYSICAL__SHIFT 0x6 718195c1f7aaSFeifei Xu #define VM_L2_SAW_CNTL4__VMC_TAP_CONTEXT0_PDE_REQUEST_SHARED__SHIFT 0x7 718295c1f7aaSFeifei Xu #define VM_L2_SAW_CNTL4__VMC_TAP_CONTEXT0_PDE_REQUEST_SNOOP__SHIFT 0x8 718395c1f7aaSFeifei Xu #define VM_L2_SAW_CNTL4__VMC_TAP_CONTEXT0_PTE_REQUEST_PHYSICAL__SHIFT 0x9 718495c1f7aaSFeifei Xu #define VM_L2_SAW_CNTL4__VMC_TAP_CONTEXT0_PTE_REQUEST_SHARED__SHIFT 0xa 718595c1f7aaSFeifei Xu #define VM_L2_SAW_CNTL4__VMC_TAP_CONTEXT0_PTE_REQUEST_SNOOP__SHIFT 0xb 718695c1f7aaSFeifei Xu #define VM_L2_SAW_CNTL4__VMC_TAP_CONTEXT1_PDE_REQUEST_PHYSICAL__SHIFT 0xc 718795c1f7aaSFeifei Xu #define VM_L2_SAW_CNTL4__VMC_TAP_CONTEXT1_PDE_REQUEST_SHARED__SHIFT 0xd 718895c1f7aaSFeifei Xu #define VM_L2_SAW_CNTL4__VMC_TAP_CONTEXT1_PDE_REQUEST_SNOOP__SHIFT 0xe 718995c1f7aaSFeifei Xu #define VM_L2_SAW_CNTL4__VMC_TAP_CONTEXT1_PTE_REQUEST_PHYSICAL__SHIFT 0xf 719095c1f7aaSFeifei Xu #define VM_L2_SAW_CNTL4__VMC_TAP_CONTEXT1_PTE_REQUEST_SHARED__SHIFT 0x10 719195c1f7aaSFeifei Xu #define VM_L2_SAW_CNTL4__VMC_TAP_CONTEXT1_PTE_REQUEST_SNOOP__SHIFT 0x11 719295c1f7aaSFeifei Xu #define VM_L2_SAW_CNTL4__L2_CACHE_4K_LRU_ADDR_MATCHING__SHIFT 0x12 719395c1f7aaSFeifei Xu #define VM_L2_SAW_CNTL4__L2_CACHE_4K_PARTITION_COUNT_MASK 0x0000003FL 719495c1f7aaSFeifei Xu #define VM_L2_SAW_CNTL4__VMC_TAP_CONTEXT0_PDE_REQUEST_PHYSICAL_MASK 0x00000040L 719595c1f7aaSFeifei Xu #define VM_L2_SAW_CNTL4__VMC_TAP_CONTEXT0_PDE_REQUEST_SHARED_MASK 0x00000080L 719695c1f7aaSFeifei Xu #define VM_L2_SAW_CNTL4__VMC_TAP_CONTEXT0_PDE_REQUEST_SNOOP_MASK 0x00000100L 719795c1f7aaSFeifei Xu #define VM_L2_SAW_CNTL4__VMC_TAP_CONTEXT0_PTE_REQUEST_PHYSICAL_MASK 0x00000200L 719895c1f7aaSFeifei Xu #define VM_L2_SAW_CNTL4__VMC_TAP_CONTEXT0_PTE_REQUEST_SHARED_MASK 0x00000400L 719995c1f7aaSFeifei Xu #define VM_L2_SAW_CNTL4__VMC_TAP_CONTEXT0_PTE_REQUEST_SNOOP_MASK 0x00000800L 720095c1f7aaSFeifei Xu #define VM_L2_SAW_CNTL4__VMC_TAP_CONTEXT1_PDE_REQUEST_PHYSICAL_MASK 0x00001000L 720195c1f7aaSFeifei Xu #define VM_L2_SAW_CNTL4__VMC_TAP_CONTEXT1_PDE_REQUEST_SHARED_MASK 0x00002000L 720295c1f7aaSFeifei Xu #define VM_L2_SAW_CNTL4__VMC_TAP_CONTEXT1_PDE_REQUEST_SNOOP_MASK 0x00004000L 720395c1f7aaSFeifei Xu #define VM_L2_SAW_CNTL4__VMC_TAP_CONTEXT1_PTE_REQUEST_PHYSICAL_MASK 0x00008000L 720495c1f7aaSFeifei Xu #define VM_L2_SAW_CNTL4__VMC_TAP_CONTEXT1_PTE_REQUEST_SHARED_MASK 0x00010000L 720595c1f7aaSFeifei Xu #define VM_L2_SAW_CNTL4__VMC_TAP_CONTEXT1_PTE_REQUEST_SNOOP_MASK 0x00020000L 720695c1f7aaSFeifei Xu #define VM_L2_SAW_CNTL4__L2_CACHE_4K_LRU_ADDR_MATCHING_MASK 0x00040000L 720795c1f7aaSFeifei Xu //VM_L2_SAW_CONTEXT0_CNTL 720895c1f7aaSFeifei Xu #define VM_L2_SAW_CONTEXT0_CNTL__ENABLE_CONTEXT__SHIFT 0x0 720995c1f7aaSFeifei Xu #define VM_L2_SAW_CONTEXT0_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 721095c1f7aaSFeifei Xu #define VM_L2_SAW_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x3 721195c1f7aaSFeifei Xu #define VM_L2_SAW_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x4 721295c1f7aaSFeifei Xu #define VM_L2_SAW_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x6 721395c1f7aaSFeifei Xu #define VM_L2_SAW_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x7 721495c1f7aaSFeifei Xu #define VM_L2_SAW_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 721595c1f7aaSFeifei Xu #define VM_L2_SAW_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa 721695c1f7aaSFeifei Xu #define VM_L2_SAW_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_SAVE__SHIFT 0xb 721795c1f7aaSFeifei Xu #define VM_L2_SAW_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xc 721895c1f7aaSFeifei Xu #define VM_L2_SAW_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xd 721995c1f7aaSFeifei Xu #define VM_L2_SAW_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_SAVE__SHIFT 0xe 722095c1f7aaSFeifei Xu #define VM_L2_SAW_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf 722195c1f7aaSFeifei Xu #define VM_L2_SAW_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 722295c1f7aaSFeifei Xu #define VM_L2_SAW_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_SAVE__SHIFT 0x11 722395c1f7aaSFeifei Xu #define VM_L2_SAW_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x12 722495c1f7aaSFeifei Xu #define VM_L2_SAW_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x13 722595c1f7aaSFeifei Xu #define VM_L2_SAW_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_SAVE__SHIFT 0x14 722695c1f7aaSFeifei Xu #define VM_L2_SAW_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 722795c1f7aaSFeifei Xu #define VM_L2_SAW_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 722895c1f7aaSFeifei Xu #define VM_L2_SAW_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_SAVE__SHIFT 0x17 722995c1f7aaSFeifei Xu #define VM_L2_SAW_CONTEXT0_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x18 723095c1f7aaSFeifei Xu #define VM_L2_SAW_CONTEXT0_CNTL__ENABLE_CONTEXT_MASK 0x00000001L 723195c1f7aaSFeifei Xu #define VM_L2_SAW_CONTEXT0_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L 723295c1f7aaSFeifei Xu #define VM_L2_SAW_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000008L 723395c1f7aaSFeifei Xu #define VM_L2_SAW_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000010L 723495c1f7aaSFeifei Xu #define VM_L2_SAW_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000040L 723595c1f7aaSFeifei Xu #define VM_L2_SAW_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000080L 723695c1f7aaSFeifei Xu #define VM_L2_SAW_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L 723795c1f7aaSFeifei Xu #define VM_L2_SAW_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L 723895c1f7aaSFeifei Xu #define VM_L2_SAW_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_SAVE_MASK 0x00000800L 723995c1f7aaSFeifei Xu #define VM_L2_SAW_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00001000L 724095c1f7aaSFeifei Xu #define VM_L2_SAW_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00002000L 724195c1f7aaSFeifei Xu #define VM_L2_SAW_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_SAVE_MASK 0x00004000L 724295c1f7aaSFeifei Xu #define VM_L2_SAW_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L 724395c1f7aaSFeifei Xu #define VM_L2_SAW_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L 724495c1f7aaSFeifei Xu #define VM_L2_SAW_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_SAVE_MASK 0x00020000L 724595c1f7aaSFeifei Xu #define VM_L2_SAW_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00040000L 724695c1f7aaSFeifei Xu #define VM_L2_SAW_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00080000L 724795c1f7aaSFeifei Xu #define VM_L2_SAW_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_SAVE_MASK 0x00100000L 724895c1f7aaSFeifei Xu #define VM_L2_SAW_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L 724995c1f7aaSFeifei Xu #define VM_L2_SAW_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L 725095c1f7aaSFeifei Xu #define VM_L2_SAW_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_SAVE_MASK 0x00800000L 725195c1f7aaSFeifei Xu #define VM_L2_SAW_CONTEXT0_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x0F000000L 725295c1f7aaSFeifei Xu //VM_L2_SAW_CONTEXT0_CNTL2 725395c1f7aaSFeifei Xu #define VM_L2_SAW_CONTEXT0_CNTL2__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x0 725495c1f7aaSFeifei Xu #define VM_L2_SAW_CONTEXT0_CNTL2__ENABLE_CLEAR_PROTECTION_FAULT_STATUS_ADDR_WHEN_INVALIDATE_CONTEXT__SHIFT 0x1 725595c1f7aaSFeifei Xu #define VM_L2_SAW_CONTEXT0_CNTL2__ENABLE_INTERRUPT_PROCESSING_FOR_SUBSEQUENT_FAULTS_PER_CONTEXT__SHIFT 0x2 725695c1f7aaSFeifei Xu #define VM_L2_SAW_CONTEXT0_CNTL2__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES__SHIFT 0x3 725795c1f7aaSFeifei Xu #define VM_L2_SAW_CONTEXT0_CNTL2__WAIT_FOR_IDLE_WHEN_INVALIDATE__SHIFT 0x4 725895c1f7aaSFeifei Xu #define VM_L2_SAW_CONTEXT0_CNTL2__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00000001L 725995c1f7aaSFeifei Xu #define VM_L2_SAW_CONTEXT0_CNTL2__ENABLE_CLEAR_PROTECTION_FAULT_STATUS_ADDR_WHEN_INVALIDATE_CONTEXT_MASK 0x00000002L 726095c1f7aaSFeifei Xu #define VM_L2_SAW_CONTEXT0_CNTL2__ENABLE_INTERRUPT_PROCESSING_FOR_SUBSEQUENT_FAULTS_PER_CONTEXT_MASK 0x00000004L 726195c1f7aaSFeifei Xu #define VM_L2_SAW_CONTEXT0_CNTL2__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES_MASK 0x00000008L 726295c1f7aaSFeifei Xu #define VM_L2_SAW_CONTEXT0_CNTL2__WAIT_FOR_IDLE_WHEN_INVALIDATE_MASK 0x00000010L 726395c1f7aaSFeifei Xu //VM_L2_SAW_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32 726495c1f7aaSFeifei Xu #define VM_L2_SAW_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32__PHYSICAL_PAGE_NUMBER_LO32__SHIFT 0x0 726595c1f7aaSFeifei Xu #define VM_L2_SAW_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32__PHYSICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 726695c1f7aaSFeifei Xu //VM_L2_SAW_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32 726795c1f7aaSFeifei Xu #define VM_L2_SAW_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32__PHYSICAL_PAGE_NUMBER_HI4__SHIFT 0x0 726895c1f7aaSFeifei Xu #define VM_L2_SAW_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32__PHYSICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 726995c1f7aaSFeifei Xu //VM_L2_SAW_CONTEXT0_PAGE_TABLE_START_ADDR_LO32 727095c1f7aaSFeifei Xu #define VM_L2_SAW_CONTEXT0_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 727195c1f7aaSFeifei Xu #define VM_L2_SAW_CONTEXT0_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 727295c1f7aaSFeifei Xu //VM_L2_SAW_CONTEXT0_PAGE_TABLE_START_ADDR_HI32 727395c1f7aaSFeifei Xu #define VM_L2_SAW_CONTEXT0_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 727495c1f7aaSFeifei Xu #define VM_L2_SAW_CONTEXT0_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 727595c1f7aaSFeifei Xu //VM_L2_SAW_CONTEXT0_PAGE_TABLE_END_ADDR_LO32 727695c1f7aaSFeifei Xu #define VM_L2_SAW_CONTEXT0_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 727795c1f7aaSFeifei Xu #define VM_L2_SAW_CONTEXT0_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 727895c1f7aaSFeifei Xu //VM_L2_SAW_CONTEXT0_PAGE_TABLE_END_ADDR_HI32 727995c1f7aaSFeifei Xu #define VM_L2_SAW_CONTEXT0_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 728095c1f7aaSFeifei Xu #define VM_L2_SAW_CONTEXT0_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 728195c1f7aaSFeifei Xu //VM_L2_SAW_CONTEXTS_DISABLE 728295c1f7aaSFeifei Xu #define VM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_0__SHIFT 0x0 728395c1f7aaSFeifei Xu #define VM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_1__SHIFT 0x1 728495c1f7aaSFeifei Xu #define VM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_2__SHIFT 0x2 728595c1f7aaSFeifei Xu #define VM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_3__SHIFT 0x3 728695c1f7aaSFeifei Xu #define VM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_4__SHIFT 0x4 728795c1f7aaSFeifei Xu #define VM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_5__SHIFT 0x5 728895c1f7aaSFeifei Xu #define VM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_6__SHIFT 0x6 728995c1f7aaSFeifei Xu #define VM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_7__SHIFT 0x7 729095c1f7aaSFeifei Xu #define VM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_8__SHIFT 0x8 729195c1f7aaSFeifei Xu #define VM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_9__SHIFT 0x9 729295c1f7aaSFeifei Xu #define VM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_10__SHIFT 0xa 729395c1f7aaSFeifei Xu #define VM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_11__SHIFT 0xb 729495c1f7aaSFeifei Xu #define VM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_12__SHIFT 0xc 729595c1f7aaSFeifei Xu #define VM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_13__SHIFT 0xd 729695c1f7aaSFeifei Xu #define VM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_14__SHIFT 0xe 729795c1f7aaSFeifei Xu #define VM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_15__SHIFT 0xf 729895c1f7aaSFeifei Xu #define VM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_0_MASK 0x00000001L 729995c1f7aaSFeifei Xu #define VM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_1_MASK 0x00000002L 730095c1f7aaSFeifei Xu #define VM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_2_MASK 0x00000004L 730195c1f7aaSFeifei Xu #define VM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_3_MASK 0x00000008L 730295c1f7aaSFeifei Xu #define VM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_4_MASK 0x00000010L 730395c1f7aaSFeifei Xu #define VM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_5_MASK 0x00000020L 730495c1f7aaSFeifei Xu #define VM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_6_MASK 0x00000040L 730595c1f7aaSFeifei Xu #define VM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_7_MASK 0x00000080L 730695c1f7aaSFeifei Xu #define VM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_8_MASK 0x00000100L 730795c1f7aaSFeifei Xu #define VM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_9_MASK 0x00000200L 730895c1f7aaSFeifei Xu #define VM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_10_MASK 0x00000400L 730995c1f7aaSFeifei Xu #define VM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_11_MASK 0x00000800L 731095c1f7aaSFeifei Xu #define VM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_12_MASK 0x00001000L 731195c1f7aaSFeifei Xu #define VM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_13_MASK 0x00002000L 731295c1f7aaSFeifei Xu #define VM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_14_MASK 0x00004000L 731395c1f7aaSFeifei Xu #define VM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_15_MASK 0x00008000L 731495c1f7aaSFeifei Xu //VM_L2_SAW_PIPES_BUSY 731595c1f7aaSFeifei Xu #define VM_L2_SAW_PIPES_BUSY__PIPES_BUSY__SHIFT 0x0 731695c1f7aaSFeifei Xu #define VM_L2_SAW_PIPES_BUSY__PIPES_BUSY_MASK 0xFFFFFFFFL 731795c1f7aaSFeifei Xu 731895c1f7aaSFeifei Xu 731995c1f7aaSFeifei Xu // addressBlock: mmhub_utcl2_atcl2dec 732095c1f7aaSFeifei Xu //ATC_L2_CNTL 732195c1f7aaSFeifei Xu #define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READ_REQUESTS__SHIFT 0x0 732295c1f7aaSFeifei Xu #define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITE_REQUESTS__SHIFT 0x3 732395c1f7aaSFeifei Xu #define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READS_DEPENDS_ON_ADDR_MOD__SHIFT 0x6 732495c1f7aaSFeifei Xu #define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITES_DEPENDS_ON_ADDR_MOD__SHIFT 0x7 732595c1f7aaSFeifei Xu #define ATC_L2_CNTL__CACHE_INVALIDATE_MODE__SHIFT 0x8 732695c1f7aaSFeifei Xu #define ATC_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY__SHIFT 0xb 732795c1f7aaSFeifei Xu #define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READ_REQUESTS_MASK 0x00000003L 732895c1f7aaSFeifei Xu #define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITE_REQUESTS_MASK 0x00000018L 732995c1f7aaSFeifei Xu #define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READS_DEPENDS_ON_ADDR_MOD_MASK 0x00000040L 733095c1f7aaSFeifei Xu #define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITES_DEPENDS_ON_ADDR_MOD_MASK 0x00000080L 733195c1f7aaSFeifei Xu #define ATC_L2_CNTL__CACHE_INVALIDATE_MODE_MASK 0x00000700L 733295c1f7aaSFeifei Xu #define ATC_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY_MASK 0x00000800L 733395c1f7aaSFeifei Xu //ATC_L2_CNTL2 733495c1f7aaSFeifei Xu #define ATC_L2_CNTL2__BANK_SELECT__SHIFT 0x0 733595c1f7aaSFeifei Xu #define ATC_L2_CNTL2__L2_CACHE_UPDATE_MODE__SHIFT 0x6 733695c1f7aaSFeifei Xu #define ATC_L2_CNTL2__ENABLE_L2_CACHE_LRU_UPDATE_BY_WRITE__SHIFT 0x8 733795c1f7aaSFeifei Xu #define ATC_L2_CNTL2__L2_CACHE_SWAP_TAG_INDEX_LSBS__SHIFT 0x9 733895c1f7aaSFeifei Xu #define ATC_L2_CNTL2__L2_CACHE_VMID_MODE__SHIFT 0xc 733995c1f7aaSFeifei Xu #define ATC_L2_CNTL2__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE__SHIFT 0xf 734095c1f7aaSFeifei Xu #define ATC_L2_CNTL2__BANK_SELECT_MASK 0x0000003FL 734195c1f7aaSFeifei Xu #define ATC_L2_CNTL2__L2_CACHE_UPDATE_MODE_MASK 0x000000C0L 734295c1f7aaSFeifei Xu #define ATC_L2_CNTL2__ENABLE_L2_CACHE_LRU_UPDATE_BY_WRITE_MASK 0x00000100L 734395c1f7aaSFeifei Xu #define ATC_L2_CNTL2__L2_CACHE_SWAP_TAG_INDEX_LSBS_MASK 0x00000E00L 734495c1f7aaSFeifei Xu #define ATC_L2_CNTL2__L2_CACHE_VMID_MODE_MASK 0x00007000L 734595c1f7aaSFeifei Xu #define ATC_L2_CNTL2__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE_MASK 0x001F8000L 734695c1f7aaSFeifei Xu //ATC_L2_CACHE_DATA0 734795c1f7aaSFeifei Xu #define ATC_L2_CACHE_DATA0__DATA_REGISTER_VALID__SHIFT 0x0 734895c1f7aaSFeifei Xu #define ATC_L2_CACHE_DATA0__CACHE_ENTRY_VALID__SHIFT 0x1 734995c1f7aaSFeifei Xu #define ATC_L2_CACHE_DATA0__CACHED_ATTRIBUTES__SHIFT 0x2 735095c1f7aaSFeifei Xu #define ATC_L2_CACHE_DATA0__VIRTUAL_PAGE_ADDRESS_HIGH__SHIFT 0x17 735195c1f7aaSFeifei Xu #define ATC_L2_CACHE_DATA0__DATA_REGISTER_VALID_MASK 0x00000001L 735295c1f7aaSFeifei Xu #define ATC_L2_CACHE_DATA0__CACHE_ENTRY_VALID_MASK 0x00000002L 735395c1f7aaSFeifei Xu #define ATC_L2_CACHE_DATA0__CACHED_ATTRIBUTES_MASK 0x007FFFFCL 735495c1f7aaSFeifei Xu #define ATC_L2_CACHE_DATA0__VIRTUAL_PAGE_ADDRESS_HIGH_MASK 0x07800000L 735595c1f7aaSFeifei Xu //ATC_L2_CACHE_DATA1 735695c1f7aaSFeifei Xu #define ATC_L2_CACHE_DATA1__VIRTUAL_PAGE_ADDRESS_LOW__SHIFT 0x0 735795c1f7aaSFeifei Xu #define ATC_L2_CACHE_DATA1__VIRTUAL_PAGE_ADDRESS_LOW_MASK 0xFFFFFFFFL 735895c1f7aaSFeifei Xu //ATC_L2_CACHE_DATA2 735995c1f7aaSFeifei Xu #define ATC_L2_CACHE_DATA2__PHYSICAL_PAGE_ADDRESS__SHIFT 0x0 736095c1f7aaSFeifei Xu #define ATC_L2_CACHE_DATA2__PHYSICAL_PAGE_ADDRESS_MASK 0xFFFFFFFFL 736195c1f7aaSFeifei Xu //ATC_L2_CNTL3 736295c1f7aaSFeifei Xu #define ATC_L2_CNTL3__DELAY_SEND_INVALIDATION_REQUEST__SHIFT 0x0 736395c1f7aaSFeifei Xu #define ATC_L2_CNTL3__ATS_REQUEST_CREDIT_MINUS1__SHIFT 0x3 736495c1f7aaSFeifei Xu #define ATC_L2_CNTL3__DELAY_SEND_INVALIDATION_REQUEST_MASK 0x00000007L 736595c1f7aaSFeifei Xu #define ATC_L2_CNTL3__ATS_REQUEST_CREDIT_MINUS1_MASK 0x000001F8L 736695c1f7aaSFeifei Xu //ATC_L2_STATUS 736795c1f7aaSFeifei Xu #define ATC_L2_STATUS__BUSY__SHIFT 0x0 736895c1f7aaSFeifei Xu #define ATC_L2_STATUS__PARITY_ERROR_INFO__SHIFT 0x1 736995c1f7aaSFeifei Xu #define ATC_L2_STATUS__BUSY_MASK 0x00000001L 737095c1f7aaSFeifei Xu #define ATC_L2_STATUS__PARITY_ERROR_INFO_MASK 0x3FFFFFFEL 737195c1f7aaSFeifei Xu //ATC_L2_STATUS2 737295c1f7aaSFeifei Xu #define ATC_L2_STATUS2__IFIFO_NON_FATAL_PARITY_ERROR_INFO__SHIFT 0x0 737395c1f7aaSFeifei Xu #define ATC_L2_STATUS2__IFIFO_FATAL_PARITY_ERROR_INFO__SHIFT 0x8 737495c1f7aaSFeifei Xu #define ATC_L2_STATUS2__IFIFO_NON_FATAL_PARITY_ERROR_INFO_MASK 0x000000FFL 737595c1f7aaSFeifei Xu #define ATC_L2_STATUS2__IFIFO_FATAL_PARITY_ERROR_INFO_MASK 0x0000FF00L 737695c1f7aaSFeifei Xu //ATC_L2_MISC_CG 737795c1f7aaSFeifei Xu #define ATC_L2_MISC_CG__OFFDLY__SHIFT 0x6 737895c1f7aaSFeifei Xu #define ATC_L2_MISC_CG__ENABLE__SHIFT 0x12 737995c1f7aaSFeifei Xu #define ATC_L2_MISC_CG__MEM_LS_ENABLE__SHIFT 0x13 738095c1f7aaSFeifei Xu #define ATC_L2_MISC_CG__OFFDLY_MASK 0x00000FC0L 738195c1f7aaSFeifei Xu #define ATC_L2_MISC_CG__ENABLE_MASK 0x00040000L 738295c1f7aaSFeifei Xu #define ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK 0x00080000L 738395c1f7aaSFeifei Xu //ATC_L2_MEM_POWER_LS 738495c1f7aaSFeifei Xu #define ATC_L2_MEM_POWER_LS__LS_SETUP__SHIFT 0x0 738595c1f7aaSFeifei Xu #define ATC_L2_MEM_POWER_LS__LS_HOLD__SHIFT 0x6 738695c1f7aaSFeifei Xu #define ATC_L2_MEM_POWER_LS__LS_SETUP_MASK 0x0000003FL 738795c1f7aaSFeifei Xu #define ATC_L2_MEM_POWER_LS__LS_HOLD_MASK 0x00000FC0L 738895c1f7aaSFeifei Xu //ATC_L2_CGTT_CLK_CTRL 738995c1f7aaSFeifei Xu #define ATC_L2_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 739095c1f7aaSFeifei Xu #define ATC_L2_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 739195c1f7aaSFeifei Xu #define ATC_L2_CGTT_CLK_CTRL__MGLS_OVERRIDE__SHIFT 0xf 739295c1f7aaSFeifei Xu #define ATC_L2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x10 739395c1f7aaSFeifei Xu #define ATC_L2_CGTT_CLK_CTRL__SOFT_OVERRIDE__SHIFT 0x18 739495c1f7aaSFeifei Xu #define ATC_L2_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL 739595c1f7aaSFeifei Xu #define ATC_L2_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L 739695c1f7aaSFeifei Xu #define ATC_L2_CGTT_CLK_CTRL__MGLS_OVERRIDE_MASK 0x00008000L 739795c1f7aaSFeifei Xu #define ATC_L2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00FF0000L 739895c1f7aaSFeifei Xu #define ATC_L2_CGTT_CLK_CTRL__SOFT_OVERRIDE_MASK 0xFF000000L 739995c1f7aaSFeifei Xu 740095c1f7aaSFeifei Xu 740195c1f7aaSFeifei Xu // addressBlock: mmhub_utcl2_vml2pfdec 740295c1f7aaSFeifei Xu //VM_L2_CNTL 740395c1f7aaSFeifei Xu #define VM_L2_CNTL__ENABLE_L2_CACHE__SHIFT 0x0 740495c1f7aaSFeifei Xu #define VM_L2_CNTL__ENABLE_L2_FRAGMENT_PROCESSING__SHIFT 0x1 740595c1f7aaSFeifei Xu #define VM_L2_CNTL__L2_CACHE_PTE_ENDIAN_SWAP_MODE__SHIFT 0x2 740695c1f7aaSFeifei Xu #define VM_L2_CNTL__L2_CACHE_PDE_ENDIAN_SWAP_MODE__SHIFT 0x4 740795c1f7aaSFeifei Xu #define VM_L2_CNTL__L2_PDE0_CACHE_TAG_GENERATION_MODE__SHIFT 0x8 740895c1f7aaSFeifei Xu #define VM_L2_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE__SHIFT 0x9 740995c1f7aaSFeifei Xu #define VM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE__SHIFT 0xa 741095c1f7aaSFeifei Xu #define VM_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY__SHIFT 0xb 741195c1f7aaSFeifei Xu #define VM_L2_CNTL__L2_PDE0_CACHE_SPLIT_MODE__SHIFT 0xc 741295c1f7aaSFeifei Xu #define VM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE__SHIFT 0xf 741395c1f7aaSFeifei Xu #define VM_L2_CNTL__PDE_FAULT_CLASSIFICATION__SHIFT 0x12 741495c1f7aaSFeifei Xu #define VM_L2_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE__SHIFT 0x13 741595c1f7aaSFeifei Xu #define VM_L2_CNTL__IDENTITY_MODE_FRAGMENT_SIZE__SHIFT 0x15 741695c1f7aaSFeifei Xu #define VM_L2_CNTL__L2_PTE_CACHE_ADDR_MODE__SHIFT 0x1a 741795c1f7aaSFeifei Xu #define VM_L2_CNTL__ENABLE_L2_CACHE_MASK 0x00000001L 741895c1f7aaSFeifei Xu #define VM_L2_CNTL__ENABLE_L2_FRAGMENT_PROCESSING_MASK 0x00000002L 741995c1f7aaSFeifei Xu #define VM_L2_CNTL__L2_CACHE_PTE_ENDIAN_SWAP_MODE_MASK 0x0000000CL 742095c1f7aaSFeifei Xu #define VM_L2_CNTL__L2_CACHE_PDE_ENDIAN_SWAP_MODE_MASK 0x00000030L 742195c1f7aaSFeifei Xu #define VM_L2_CNTL__L2_PDE0_CACHE_TAG_GENERATION_MODE_MASK 0x00000100L 742295c1f7aaSFeifei Xu #define VM_L2_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE_MASK 0x00000200L 742395c1f7aaSFeifei Xu #define VM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE_MASK 0x00000400L 742495c1f7aaSFeifei Xu #define VM_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY_MASK 0x00000800L 742595c1f7aaSFeifei Xu #define VM_L2_CNTL__L2_PDE0_CACHE_SPLIT_MODE_MASK 0x00007000L 742695c1f7aaSFeifei Xu #define VM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE_MASK 0x00038000L 742795c1f7aaSFeifei Xu #define VM_L2_CNTL__PDE_FAULT_CLASSIFICATION_MASK 0x00040000L 742895c1f7aaSFeifei Xu #define VM_L2_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE_MASK 0x00180000L 742995c1f7aaSFeifei Xu #define VM_L2_CNTL__IDENTITY_MODE_FRAGMENT_SIZE_MASK 0x03E00000L 743095c1f7aaSFeifei Xu #define VM_L2_CNTL__L2_PTE_CACHE_ADDR_MODE_MASK 0x0C000000L 743195c1f7aaSFeifei Xu //VM_L2_CNTL2 743295c1f7aaSFeifei Xu #define VM_L2_CNTL2__INVALIDATE_ALL_L1_TLBS__SHIFT 0x0 743395c1f7aaSFeifei Xu #define VM_L2_CNTL2__INVALIDATE_L2_CACHE__SHIFT 0x1 743495c1f7aaSFeifei Xu #define VM_L2_CNTL2__DISABLE_INVALIDATE_PER_DOMAIN__SHIFT 0x15 743595c1f7aaSFeifei Xu #define VM_L2_CNTL2__DISABLE_BIGK_CACHE_OPTIMIZATION__SHIFT 0x16 743695c1f7aaSFeifei Xu #define VM_L2_CNTL2__L2_PTE_CACHE_VMID_MODE__SHIFT 0x17 743795c1f7aaSFeifei Xu #define VM_L2_CNTL2__INVALIDATE_CACHE_MODE__SHIFT 0x1a 743895c1f7aaSFeifei Xu #define VM_L2_CNTL2__PDE_CACHE_EFFECTIVE_SIZE__SHIFT 0x1c 743995c1f7aaSFeifei Xu #define VM_L2_CNTL2__INVALIDATE_ALL_L1_TLBS_MASK 0x00000001L 744095c1f7aaSFeifei Xu #define VM_L2_CNTL2__INVALIDATE_L2_CACHE_MASK 0x00000002L 744195c1f7aaSFeifei Xu #define VM_L2_CNTL2__DISABLE_INVALIDATE_PER_DOMAIN_MASK 0x00200000L 744295c1f7aaSFeifei Xu #define VM_L2_CNTL2__DISABLE_BIGK_CACHE_OPTIMIZATION_MASK 0x00400000L 744395c1f7aaSFeifei Xu #define VM_L2_CNTL2__L2_PTE_CACHE_VMID_MODE_MASK 0x03800000L 744495c1f7aaSFeifei Xu #define VM_L2_CNTL2__INVALIDATE_CACHE_MODE_MASK 0x0C000000L 744595c1f7aaSFeifei Xu #define VM_L2_CNTL2__PDE_CACHE_EFFECTIVE_SIZE_MASK 0x70000000L 744695c1f7aaSFeifei Xu //VM_L2_CNTL3 744795c1f7aaSFeifei Xu #define VM_L2_CNTL3__BANK_SELECT__SHIFT 0x0 744895c1f7aaSFeifei Xu #define VM_L2_CNTL3__L2_CACHE_UPDATE_MODE__SHIFT 0x6 744995c1f7aaSFeifei Xu #define VM_L2_CNTL3__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE__SHIFT 0x8 745095c1f7aaSFeifei Xu #define VM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0xf 745195c1f7aaSFeifei Xu #define VM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY__SHIFT 0x14 745295c1f7aaSFeifei Xu #define VM_L2_CNTL3__L2_CACHE_4K_EFFECTIVE_SIZE__SHIFT 0x15 745395c1f7aaSFeifei Xu #define VM_L2_CNTL3__L2_CACHE_BIGK_EFFECTIVE_SIZE__SHIFT 0x18 745495c1f7aaSFeifei Xu #define VM_L2_CNTL3__L2_CACHE_4K_FORCE_MISS__SHIFT 0x1c 745595c1f7aaSFeifei Xu #define VM_L2_CNTL3__L2_CACHE_BIGK_FORCE_MISS__SHIFT 0x1d 745695c1f7aaSFeifei Xu #define VM_L2_CNTL3__PDE_CACHE_FORCE_MISS__SHIFT 0x1e 745795c1f7aaSFeifei Xu #define VM_L2_CNTL3__L2_CACHE_4K_ASSOCIATIVITY__SHIFT 0x1f 745895c1f7aaSFeifei Xu #define VM_L2_CNTL3__BANK_SELECT_MASK 0x0000003FL 745995c1f7aaSFeifei Xu #define VM_L2_CNTL3__L2_CACHE_UPDATE_MODE_MASK 0x000000C0L 746095c1f7aaSFeifei Xu #define VM_L2_CNTL3__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE_MASK 0x00001F00L 746195c1f7aaSFeifei Xu #define VM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000F8000L 746295c1f7aaSFeifei Xu #define VM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY_MASK 0x00100000L 746395c1f7aaSFeifei Xu #define VM_L2_CNTL3__L2_CACHE_4K_EFFECTIVE_SIZE_MASK 0x00E00000L 746495c1f7aaSFeifei Xu #define VM_L2_CNTL3__L2_CACHE_BIGK_EFFECTIVE_SIZE_MASK 0x0F000000L 746595c1f7aaSFeifei Xu #define VM_L2_CNTL3__L2_CACHE_4K_FORCE_MISS_MASK 0x10000000L 746695c1f7aaSFeifei Xu #define VM_L2_CNTL3__L2_CACHE_BIGK_FORCE_MISS_MASK 0x20000000L 746795c1f7aaSFeifei Xu #define VM_L2_CNTL3__PDE_CACHE_FORCE_MISS_MASK 0x40000000L 746895c1f7aaSFeifei Xu #define VM_L2_CNTL3__L2_CACHE_4K_ASSOCIATIVITY_MASK 0x80000000L 746995c1f7aaSFeifei Xu //VM_L2_STATUS 747095c1f7aaSFeifei Xu #define VM_L2_STATUS__L2_BUSY__SHIFT 0x0 747195c1f7aaSFeifei Xu #define VM_L2_STATUS__CONTEXT_DOMAIN_BUSY__SHIFT 0x1 747295c1f7aaSFeifei Xu #define VM_L2_STATUS__FOUND_4K_PTE_CACHE_PARITY_ERRORS__SHIFT 0x11 747395c1f7aaSFeifei Xu #define VM_L2_STATUS__FOUND_BIGK_PTE_CACHE_PARITY_ERRORS__SHIFT 0x12 747495c1f7aaSFeifei Xu #define VM_L2_STATUS__FOUND_PDE0_CACHE_PARITY_ERRORS__SHIFT 0x13 747595c1f7aaSFeifei Xu #define VM_L2_STATUS__FOUND_PDE1_CACHE_PARITY_ERRORS__SHIFT 0x14 747695c1f7aaSFeifei Xu #define VM_L2_STATUS__FOUND_PDE2_CACHE_PARITY_ERRORS__SHIFT 0x15 747795c1f7aaSFeifei Xu #define VM_L2_STATUS__L2_BUSY_MASK 0x00000001L 747895c1f7aaSFeifei Xu #define VM_L2_STATUS__CONTEXT_DOMAIN_BUSY_MASK 0x0001FFFEL 747995c1f7aaSFeifei Xu #define VM_L2_STATUS__FOUND_4K_PTE_CACHE_PARITY_ERRORS_MASK 0x00020000L 748095c1f7aaSFeifei Xu #define VM_L2_STATUS__FOUND_BIGK_PTE_CACHE_PARITY_ERRORS_MASK 0x00040000L 748195c1f7aaSFeifei Xu #define VM_L2_STATUS__FOUND_PDE0_CACHE_PARITY_ERRORS_MASK 0x00080000L 748295c1f7aaSFeifei Xu #define VM_L2_STATUS__FOUND_PDE1_CACHE_PARITY_ERRORS_MASK 0x00100000L 748395c1f7aaSFeifei Xu #define VM_L2_STATUS__FOUND_PDE2_CACHE_PARITY_ERRORS_MASK 0x00200000L 748495c1f7aaSFeifei Xu //VM_DUMMY_PAGE_FAULT_CNTL 748595c1f7aaSFeifei Xu #define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_FAULT_ENABLE__SHIFT 0x0 748695c1f7aaSFeifei Xu #define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_ADDRESS_LOGICAL__SHIFT 0x1 748795c1f7aaSFeifei Xu #define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_COMPARE_MSBS__SHIFT 0x2 748895c1f7aaSFeifei Xu #define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_FAULT_ENABLE_MASK 0x00000001L 748995c1f7aaSFeifei Xu #define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_ADDRESS_LOGICAL_MASK 0x00000002L 749095c1f7aaSFeifei Xu #define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_COMPARE_MSBS_MASK 0x000000FCL 749195c1f7aaSFeifei Xu //VM_DUMMY_PAGE_FAULT_ADDR_LO32 749295c1f7aaSFeifei Xu #define VM_DUMMY_PAGE_FAULT_ADDR_LO32__DUMMY_PAGE_ADDR_LO32__SHIFT 0x0 749395c1f7aaSFeifei Xu #define VM_DUMMY_PAGE_FAULT_ADDR_LO32__DUMMY_PAGE_ADDR_LO32_MASK 0xFFFFFFFFL 749495c1f7aaSFeifei Xu //VM_DUMMY_PAGE_FAULT_ADDR_HI32 749595c1f7aaSFeifei Xu #define VM_DUMMY_PAGE_FAULT_ADDR_HI32__DUMMY_PAGE_ADDR_HI4__SHIFT 0x0 749695c1f7aaSFeifei Xu #define VM_DUMMY_PAGE_FAULT_ADDR_HI32__DUMMY_PAGE_ADDR_HI4_MASK 0x0000000FL 749795c1f7aaSFeifei Xu //VM_L2_PROTECTION_FAULT_CNTL 749895c1f7aaSFeifei Xu #define VM_L2_PROTECTION_FAULT_CNTL__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x0 749995c1f7aaSFeifei Xu #define VM_L2_PROTECTION_FAULT_CNTL__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES__SHIFT 0x1 750095c1f7aaSFeifei Xu #define VM_L2_PROTECTION_FAULT_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x2 750195c1f7aaSFeifei Xu #define VM_L2_PROTECTION_FAULT_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x3 750295c1f7aaSFeifei Xu #define VM_L2_PROTECTION_FAULT_CNTL__PDE1_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x4 750395c1f7aaSFeifei Xu #define VM_L2_PROTECTION_FAULT_CNTL__PDE2_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x5 750495c1f7aaSFeifei Xu #define VM_L2_PROTECTION_FAULT_CNTL__TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x6 750595c1f7aaSFeifei Xu #define VM_L2_PROTECTION_FAULT_CNTL__NACK_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x7 750695c1f7aaSFeifei Xu #define VM_L2_PROTECTION_FAULT_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x8 750795c1f7aaSFeifei Xu #define VM_L2_PROTECTION_FAULT_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x9 750895c1f7aaSFeifei Xu #define VM_L2_PROTECTION_FAULT_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa 750995c1f7aaSFeifei Xu #define VM_L2_PROTECTION_FAULT_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xb 751095c1f7aaSFeifei Xu #define VM_L2_PROTECTION_FAULT_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc 751195c1f7aaSFeifei Xu #define VM_L2_PROTECTION_FAULT_CNTL__CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT 0xd 751295c1f7aaSFeifei Xu #define VM_L2_PROTECTION_FAULT_CNTL__OTHER_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT 0x1d 751395c1f7aaSFeifei Xu #define VM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_NO_RETRY_FAULT__SHIFT 0x1e 751495c1f7aaSFeifei Xu #define VM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_RETRY_FAULT__SHIFT 0x1f 751595c1f7aaSFeifei Xu #define VM_L2_PROTECTION_FAULT_CNTL__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00000001L 751695c1f7aaSFeifei Xu #define VM_L2_PROTECTION_FAULT_CNTL__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES_MASK 0x00000002L 751795c1f7aaSFeifei Xu #define VM_L2_PROTECTION_FAULT_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000004L 751895c1f7aaSFeifei Xu #define VM_L2_PROTECTION_FAULT_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000008L 751995c1f7aaSFeifei Xu #define VM_L2_PROTECTION_FAULT_CNTL__PDE1_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000010L 752095c1f7aaSFeifei Xu #define VM_L2_PROTECTION_FAULT_CNTL__PDE2_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000020L 752195c1f7aaSFeifei Xu #define VM_L2_PROTECTION_FAULT_CNTL__TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000040L 752295c1f7aaSFeifei Xu #define VM_L2_PROTECTION_FAULT_CNTL__NACK_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000080L 752395c1f7aaSFeifei Xu #define VM_L2_PROTECTION_FAULT_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000100L 752495c1f7aaSFeifei Xu #define VM_L2_PROTECTION_FAULT_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000200L 752595c1f7aaSFeifei Xu #define VM_L2_PROTECTION_FAULT_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L 752695c1f7aaSFeifei Xu #define VM_L2_PROTECTION_FAULT_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000800L 752795c1f7aaSFeifei Xu #define VM_L2_PROTECTION_FAULT_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L 752895c1f7aaSFeifei Xu #define VM_L2_PROTECTION_FAULT_CNTL__CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK 0x1FFFE000L 752995c1f7aaSFeifei Xu #define VM_L2_PROTECTION_FAULT_CNTL__OTHER_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK 0x20000000L 753095c1f7aaSFeifei Xu #define VM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_NO_RETRY_FAULT_MASK 0x40000000L 753195c1f7aaSFeifei Xu #define VM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_RETRY_FAULT_MASK 0x80000000L 753295c1f7aaSFeifei Xu //VM_L2_PROTECTION_FAULT_CNTL2 753395c1f7aaSFeifei Xu #define VM_L2_PROTECTION_FAULT_CNTL2__CLIENT_ID_PRT_FAULT_INTERRUPT__SHIFT 0x0 753495c1f7aaSFeifei Xu #define VM_L2_PROTECTION_FAULT_CNTL2__OTHER_CLIENT_ID_PRT_FAULT_INTERRUPT__SHIFT 0x10 753595c1f7aaSFeifei Xu #define VM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE__SHIFT 0x11 753695c1f7aaSFeifei Xu #define VM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY__SHIFT 0x12 753795c1f7aaSFeifei Xu #define VM_L2_PROTECTION_FAULT_CNTL2__ENABLE_RETRY_FAULT_INTERRUPT__SHIFT 0x13 753895c1f7aaSFeifei Xu #define VM_L2_PROTECTION_FAULT_CNTL2__CLIENT_ID_PRT_FAULT_INTERRUPT_MASK 0x0000FFFFL 753995c1f7aaSFeifei Xu #define VM_L2_PROTECTION_FAULT_CNTL2__OTHER_CLIENT_ID_PRT_FAULT_INTERRUPT_MASK 0x00010000L 754095c1f7aaSFeifei Xu #define VM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE_MASK 0x00020000L 754195c1f7aaSFeifei Xu #define VM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY_MASK 0x00040000L 754295c1f7aaSFeifei Xu #define VM_L2_PROTECTION_FAULT_CNTL2__ENABLE_RETRY_FAULT_INTERRUPT_MASK 0x00080000L 754395c1f7aaSFeifei Xu //VM_L2_PROTECTION_FAULT_MM_CNTL3 754495c1f7aaSFeifei Xu #define VM_L2_PROTECTION_FAULT_MM_CNTL3__VML1_READ_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT 0x0 754595c1f7aaSFeifei Xu #define VM_L2_PROTECTION_FAULT_MM_CNTL3__VML1_READ_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK 0xFFFFFFFFL 754695c1f7aaSFeifei Xu //VM_L2_PROTECTION_FAULT_MM_CNTL4 754795c1f7aaSFeifei Xu #define VM_L2_PROTECTION_FAULT_MM_CNTL4__VML1_WRITE_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT 0x0 754895c1f7aaSFeifei Xu #define VM_L2_PROTECTION_FAULT_MM_CNTL4__VML1_WRITE_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK 0xFFFFFFFFL 754995c1f7aaSFeifei Xu //VM_L2_PROTECTION_FAULT_STATUS 755095c1f7aaSFeifei Xu #define VM_L2_PROTECTION_FAULT_STATUS__MORE_FAULTS__SHIFT 0x0 755195c1f7aaSFeifei Xu #define VM_L2_PROTECTION_FAULT_STATUS__WALKER_ERROR__SHIFT 0x1 755295c1f7aaSFeifei Xu #define VM_L2_PROTECTION_FAULT_STATUS__PERMISSION_FAULTS__SHIFT 0x4 755395c1f7aaSFeifei Xu #define VM_L2_PROTECTION_FAULT_STATUS__MAPPING_ERROR__SHIFT 0x8 755495c1f7aaSFeifei Xu #define VM_L2_PROTECTION_FAULT_STATUS__CID__SHIFT 0x9 755595c1f7aaSFeifei Xu #define VM_L2_PROTECTION_FAULT_STATUS__RW__SHIFT 0x12 755695c1f7aaSFeifei Xu #define VM_L2_PROTECTION_FAULT_STATUS__ATOMIC__SHIFT 0x13 755795c1f7aaSFeifei Xu #define VM_L2_PROTECTION_FAULT_STATUS__VMID__SHIFT 0x14 755895c1f7aaSFeifei Xu #define VM_L2_PROTECTION_FAULT_STATUS__VF__SHIFT 0x18 755995c1f7aaSFeifei Xu #define VM_L2_PROTECTION_FAULT_STATUS__VFID__SHIFT 0x19 756095c1f7aaSFeifei Xu #define VM_L2_PROTECTION_FAULT_STATUS__MORE_FAULTS_MASK 0x00000001L 756195c1f7aaSFeifei Xu #define VM_L2_PROTECTION_FAULT_STATUS__WALKER_ERROR_MASK 0x0000000EL 756295c1f7aaSFeifei Xu #define VM_L2_PROTECTION_FAULT_STATUS__PERMISSION_FAULTS_MASK 0x000000F0L 756395c1f7aaSFeifei Xu #define VM_L2_PROTECTION_FAULT_STATUS__MAPPING_ERROR_MASK 0x00000100L 756495c1f7aaSFeifei Xu #define VM_L2_PROTECTION_FAULT_STATUS__CID_MASK 0x0003FE00L 756595c1f7aaSFeifei Xu #define VM_L2_PROTECTION_FAULT_STATUS__RW_MASK 0x00040000L 756695c1f7aaSFeifei Xu #define VM_L2_PROTECTION_FAULT_STATUS__ATOMIC_MASK 0x00080000L 756795c1f7aaSFeifei Xu #define VM_L2_PROTECTION_FAULT_STATUS__VMID_MASK 0x00F00000L 756895c1f7aaSFeifei Xu #define VM_L2_PROTECTION_FAULT_STATUS__VF_MASK 0x01000000L 756995c1f7aaSFeifei Xu #define VM_L2_PROTECTION_FAULT_STATUS__VFID_MASK 0x1E000000L 757095c1f7aaSFeifei Xu //VM_L2_PROTECTION_FAULT_ADDR_LO32 757195c1f7aaSFeifei Xu #define VM_L2_PROTECTION_FAULT_ADDR_LO32__LOGICAL_PAGE_ADDR_LO32__SHIFT 0x0 757295c1f7aaSFeifei Xu #define VM_L2_PROTECTION_FAULT_ADDR_LO32__LOGICAL_PAGE_ADDR_LO32_MASK 0xFFFFFFFFL 757395c1f7aaSFeifei Xu //VM_L2_PROTECTION_FAULT_ADDR_HI32 757495c1f7aaSFeifei Xu #define VM_L2_PROTECTION_FAULT_ADDR_HI32__LOGICAL_PAGE_ADDR_HI4__SHIFT 0x0 757595c1f7aaSFeifei Xu #define VM_L2_PROTECTION_FAULT_ADDR_HI32__LOGICAL_PAGE_ADDR_HI4_MASK 0x0000000FL 757695c1f7aaSFeifei Xu //VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32 757795c1f7aaSFeifei Xu #define VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32__PHYSICAL_PAGE_ADDR_LO32__SHIFT 0x0 757895c1f7aaSFeifei Xu #define VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32__PHYSICAL_PAGE_ADDR_LO32_MASK 0xFFFFFFFFL 757995c1f7aaSFeifei Xu //VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32 758095c1f7aaSFeifei Xu #define VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32__PHYSICAL_PAGE_ADDR_HI4__SHIFT 0x0 758195c1f7aaSFeifei Xu #define VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32__PHYSICAL_PAGE_ADDR_HI4_MASK 0x0000000FL 758295c1f7aaSFeifei Xu //VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32 758395c1f7aaSFeifei Xu #define VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 758495c1f7aaSFeifei Xu #define VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 758595c1f7aaSFeifei Xu //VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32 758695c1f7aaSFeifei Xu #define VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 758795c1f7aaSFeifei Xu #define VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 758895c1f7aaSFeifei Xu //VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32 758995c1f7aaSFeifei Xu #define VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 759095c1f7aaSFeifei Xu #define VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 759195c1f7aaSFeifei Xu //VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32 759295c1f7aaSFeifei Xu #define VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 759395c1f7aaSFeifei Xu #define VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 759495c1f7aaSFeifei Xu //VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32 759595c1f7aaSFeifei Xu #define VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32__PHYSICAL_PAGE_OFFSET_LO32__SHIFT 0x0 759695c1f7aaSFeifei Xu #define VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32__PHYSICAL_PAGE_OFFSET_LO32_MASK 0xFFFFFFFFL 759795c1f7aaSFeifei Xu //VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32 759895c1f7aaSFeifei Xu #define VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32__PHYSICAL_PAGE_OFFSET_HI4__SHIFT 0x0 759995c1f7aaSFeifei Xu #define VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32__PHYSICAL_PAGE_OFFSET_HI4_MASK 0x0000000FL 760095c1f7aaSFeifei Xu //VM_L2_CNTL4 760195c1f7aaSFeifei Xu #define VM_L2_CNTL4__L2_CACHE_4K_PARTITION_COUNT__SHIFT 0x0 760295c1f7aaSFeifei Xu #define VM_L2_CNTL4__VMC_TAP_PDE_REQUEST_PHYSICAL__SHIFT 0x6 760395c1f7aaSFeifei Xu #define VM_L2_CNTL4__VMC_TAP_PTE_REQUEST_PHYSICAL__SHIFT 0x7 760495c1f7aaSFeifei Xu #define VM_L2_CNTL4__MM_NONRT_IFIFO_ACTIVE_TRANSACTION_LIMIT__SHIFT 0x8 760595c1f7aaSFeifei Xu #define VM_L2_CNTL4__MM_SOFTRT_IFIFO_ACTIVE_TRANSACTION_LIMIT__SHIFT 0x12 760695c1f7aaSFeifei Xu #define VM_L2_CNTL4__BPM_CGCGLS_OVERRIDE__SHIFT 0x1c 760795c1f7aaSFeifei Xu #define VM_L2_CNTL4__L2_CACHE_4K_PARTITION_COUNT_MASK 0x0000003FL 760895c1f7aaSFeifei Xu #define VM_L2_CNTL4__VMC_TAP_PDE_REQUEST_PHYSICAL_MASK 0x00000040L 760995c1f7aaSFeifei Xu #define VM_L2_CNTL4__VMC_TAP_PTE_REQUEST_PHYSICAL_MASK 0x00000080L 761095c1f7aaSFeifei Xu #define VM_L2_CNTL4__MM_NONRT_IFIFO_ACTIVE_TRANSACTION_LIMIT_MASK 0x0003FF00L 761195c1f7aaSFeifei Xu #define VM_L2_CNTL4__MM_SOFTRT_IFIFO_ACTIVE_TRANSACTION_LIMIT_MASK 0x0FFC0000L 761295c1f7aaSFeifei Xu #define VM_L2_CNTL4__BPM_CGCGLS_OVERRIDE_MASK 0x10000000L 761395c1f7aaSFeifei Xu //VM_L2_MM_GROUP_RT_CLASSES 761495c1f7aaSFeifei Xu #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_0_RT_CLASS__SHIFT 0x0 761595c1f7aaSFeifei Xu #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_1_RT_CLASS__SHIFT 0x1 761695c1f7aaSFeifei Xu #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_2_RT_CLASS__SHIFT 0x2 761795c1f7aaSFeifei Xu #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_3_RT_CLASS__SHIFT 0x3 761895c1f7aaSFeifei Xu #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_4_RT_CLASS__SHIFT 0x4 761995c1f7aaSFeifei Xu #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_5_RT_CLASS__SHIFT 0x5 762095c1f7aaSFeifei Xu #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_6_RT_CLASS__SHIFT 0x6 762195c1f7aaSFeifei Xu #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_7_RT_CLASS__SHIFT 0x7 762295c1f7aaSFeifei Xu #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_8_RT_CLASS__SHIFT 0x8 762395c1f7aaSFeifei Xu #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_9_RT_CLASS__SHIFT 0x9 762495c1f7aaSFeifei Xu #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_10_RT_CLASS__SHIFT 0xa 762595c1f7aaSFeifei Xu #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_11_RT_CLASS__SHIFT 0xb 762695c1f7aaSFeifei Xu #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_12_RT_CLASS__SHIFT 0xc 762795c1f7aaSFeifei Xu #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_13_RT_CLASS__SHIFT 0xd 762895c1f7aaSFeifei Xu #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_14_RT_CLASS__SHIFT 0xe 762995c1f7aaSFeifei Xu #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_15_RT_CLASS__SHIFT 0xf 763095c1f7aaSFeifei Xu #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_16_RT_CLASS__SHIFT 0x10 763195c1f7aaSFeifei Xu #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_17_RT_CLASS__SHIFT 0x11 763295c1f7aaSFeifei Xu #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_18_RT_CLASS__SHIFT 0x12 763395c1f7aaSFeifei Xu #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_19_RT_CLASS__SHIFT 0x13 763495c1f7aaSFeifei Xu #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_20_RT_CLASS__SHIFT 0x14 763595c1f7aaSFeifei Xu #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_21_RT_CLASS__SHIFT 0x15 763695c1f7aaSFeifei Xu #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_22_RT_CLASS__SHIFT 0x16 763795c1f7aaSFeifei Xu #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_23_RT_CLASS__SHIFT 0x17 763895c1f7aaSFeifei Xu #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_24_RT_CLASS__SHIFT 0x18 763995c1f7aaSFeifei Xu #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_25_RT_CLASS__SHIFT 0x19 764095c1f7aaSFeifei Xu #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_26_RT_CLASS__SHIFT 0x1a 764195c1f7aaSFeifei Xu #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_27_RT_CLASS__SHIFT 0x1b 764295c1f7aaSFeifei Xu #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_28_RT_CLASS__SHIFT 0x1c 764395c1f7aaSFeifei Xu #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_29_RT_CLASS__SHIFT 0x1d 764495c1f7aaSFeifei Xu #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_30_RT_CLASS__SHIFT 0x1e 764595c1f7aaSFeifei Xu #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_31_RT_CLASS__SHIFT 0x1f 764695c1f7aaSFeifei Xu #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_0_RT_CLASS_MASK 0x00000001L 764795c1f7aaSFeifei Xu #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_1_RT_CLASS_MASK 0x00000002L 764895c1f7aaSFeifei Xu #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_2_RT_CLASS_MASK 0x00000004L 764995c1f7aaSFeifei Xu #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_3_RT_CLASS_MASK 0x00000008L 765095c1f7aaSFeifei Xu #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_4_RT_CLASS_MASK 0x00000010L 765195c1f7aaSFeifei Xu #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_5_RT_CLASS_MASK 0x00000020L 765295c1f7aaSFeifei Xu #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_6_RT_CLASS_MASK 0x00000040L 765395c1f7aaSFeifei Xu #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_7_RT_CLASS_MASK 0x00000080L 765495c1f7aaSFeifei Xu #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_8_RT_CLASS_MASK 0x00000100L 765595c1f7aaSFeifei Xu #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_9_RT_CLASS_MASK 0x00000200L 765695c1f7aaSFeifei Xu #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_10_RT_CLASS_MASK 0x00000400L 765795c1f7aaSFeifei Xu #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_11_RT_CLASS_MASK 0x00000800L 765895c1f7aaSFeifei Xu #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_12_RT_CLASS_MASK 0x00001000L 765995c1f7aaSFeifei Xu #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_13_RT_CLASS_MASK 0x00002000L 766095c1f7aaSFeifei Xu #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_14_RT_CLASS_MASK 0x00004000L 766195c1f7aaSFeifei Xu #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_15_RT_CLASS_MASK 0x00008000L 766295c1f7aaSFeifei Xu #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_16_RT_CLASS_MASK 0x00010000L 766395c1f7aaSFeifei Xu #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_17_RT_CLASS_MASK 0x00020000L 766495c1f7aaSFeifei Xu #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_18_RT_CLASS_MASK 0x00040000L 766595c1f7aaSFeifei Xu #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_19_RT_CLASS_MASK 0x00080000L 766695c1f7aaSFeifei Xu #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_20_RT_CLASS_MASK 0x00100000L 766795c1f7aaSFeifei Xu #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_21_RT_CLASS_MASK 0x00200000L 766895c1f7aaSFeifei Xu #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_22_RT_CLASS_MASK 0x00400000L 766995c1f7aaSFeifei Xu #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_23_RT_CLASS_MASK 0x00800000L 767095c1f7aaSFeifei Xu #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_24_RT_CLASS_MASK 0x01000000L 767195c1f7aaSFeifei Xu #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_25_RT_CLASS_MASK 0x02000000L 767295c1f7aaSFeifei Xu #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_26_RT_CLASS_MASK 0x04000000L 767395c1f7aaSFeifei Xu #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_27_RT_CLASS_MASK 0x08000000L 767495c1f7aaSFeifei Xu #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_28_RT_CLASS_MASK 0x10000000L 767595c1f7aaSFeifei Xu #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_29_RT_CLASS_MASK 0x20000000L 767695c1f7aaSFeifei Xu #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_30_RT_CLASS_MASK 0x40000000L 767795c1f7aaSFeifei Xu #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_31_RT_CLASS_MASK 0x80000000L 767895c1f7aaSFeifei Xu //VM_L2_BANK_SELECT_RESERVED_CID 767995c1f7aaSFeifei Xu #define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_READ_CLIENT_ID__SHIFT 0x0 768095c1f7aaSFeifei Xu #define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_WRITE_CLIENT_ID__SHIFT 0xa 768195c1f7aaSFeifei Xu #define VM_L2_BANK_SELECT_RESERVED_CID__ENABLE__SHIFT 0x14 768295c1f7aaSFeifei Xu #define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_INVALIDATION_MODE__SHIFT 0x18 768395c1f7aaSFeifei Xu #define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_PRIVATE_INVALIDATION__SHIFT 0x19 768495c1f7aaSFeifei Xu #define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_READ_CLIENT_ID_MASK 0x000001FFL 768595c1f7aaSFeifei Xu #define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_WRITE_CLIENT_ID_MASK 0x0007FC00L 768695c1f7aaSFeifei Xu #define VM_L2_BANK_SELECT_RESERVED_CID__ENABLE_MASK 0x00100000L 768795c1f7aaSFeifei Xu #define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_INVALIDATION_MODE_MASK 0x01000000L 768895c1f7aaSFeifei Xu #define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_PRIVATE_INVALIDATION_MASK 0x02000000L 768995c1f7aaSFeifei Xu //VM_L2_BANK_SELECT_RESERVED_CID2 769095c1f7aaSFeifei Xu #define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_READ_CLIENT_ID__SHIFT 0x0 769195c1f7aaSFeifei Xu #define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_WRITE_CLIENT_ID__SHIFT 0xa 769295c1f7aaSFeifei Xu #define VM_L2_BANK_SELECT_RESERVED_CID2__ENABLE__SHIFT 0x14 769395c1f7aaSFeifei Xu #define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_INVALIDATION_MODE__SHIFT 0x18 769495c1f7aaSFeifei Xu #define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_PRIVATE_INVALIDATION__SHIFT 0x19 769595c1f7aaSFeifei Xu #define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_READ_CLIENT_ID_MASK 0x000001FFL 769695c1f7aaSFeifei Xu #define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_WRITE_CLIENT_ID_MASK 0x0007FC00L 769795c1f7aaSFeifei Xu #define VM_L2_BANK_SELECT_RESERVED_CID2__ENABLE_MASK 0x00100000L 769895c1f7aaSFeifei Xu #define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_INVALIDATION_MODE_MASK 0x01000000L 769995c1f7aaSFeifei Xu #define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_PRIVATE_INVALIDATION_MASK 0x02000000L 770095c1f7aaSFeifei Xu //VM_L2_CACHE_PARITY_CNTL 770195c1f7aaSFeifei Xu #define VM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_4K_PTE_CACHES__SHIFT 0x0 770295c1f7aaSFeifei Xu #define VM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_BIGK_PTE_CACHES__SHIFT 0x1 770395c1f7aaSFeifei Xu #define VM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_PDE_CACHES__SHIFT 0x2 770495c1f7aaSFeifei Xu #define VM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_4K_PTE_CACHE__SHIFT 0x3 770595c1f7aaSFeifei Xu #define VM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_BIGK_PTE_CACHE__SHIFT 0x4 770695c1f7aaSFeifei Xu #define VM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_PDE_CACHE__SHIFT 0x5 770795c1f7aaSFeifei Xu #define VM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_BANK__SHIFT 0x6 770895c1f7aaSFeifei Xu #define VM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_NUMBER__SHIFT 0x9 770995c1f7aaSFeifei Xu #define VM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_ASSOC__SHIFT 0xc 771095c1f7aaSFeifei Xu #define VM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_4K_PTE_CACHES_MASK 0x00000001L 771195c1f7aaSFeifei Xu #define VM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_BIGK_PTE_CACHES_MASK 0x00000002L 771295c1f7aaSFeifei Xu #define VM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_PDE_CACHES_MASK 0x00000004L 771395c1f7aaSFeifei Xu #define VM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_4K_PTE_CACHE_MASK 0x00000008L 771495c1f7aaSFeifei Xu #define VM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_BIGK_PTE_CACHE_MASK 0x00000010L 771595c1f7aaSFeifei Xu #define VM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_PDE_CACHE_MASK 0x00000020L 771695c1f7aaSFeifei Xu #define VM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_BANK_MASK 0x000001C0L 771795c1f7aaSFeifei Xu #define VM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_NUMBER_MASK 0x00000E00L 771895c1f7aaSFeifei Xu #define VM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_ASSOC_MASK 0x0000F000L 771995c1f7aaSFeifei Xu //VM_L2_CGTT_CLK_CTRL 772095c1f7aaSFeifei Xu #define VM_L2_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 772195c1f7aaSFeifei Xu #define VM_L2_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 772295c1f7aaSFeifei Xu #define VM_L2_CGTT_CLK_CTRL__MGLS_OVERRIDE__SHIFT 0xf 772395c1f7aaSFeifei Xu #define VM_L2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x10 772495c1f7aaSFeifei Xu #define VM_L2_CGTT_CLK_CTRL__SOFT_OVERRIDE__SHIFT 0x18 772595c1f7aaSFeifei Xu #define VM_L2_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL 772695c1f7aaSFeifei Xu #define VM_L2_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L 772795c1f7aaSFeifei Xu #define VM_L2_CGTT_CLK_CTRL__MGLS_OVERRIDE_MASK 0x00008000L 772895c1f7aaSFeifei Xu #define VM_L2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00FF0000L 772995c1f7aaSFeifei Xu #define VM_L2_CGTT_CLK_CTRL__SOFT_OVERRIDE_MASK 0xFF000000L 773095c1f7aaSFeifei Xu 773195c1f7aaSFeifei Xu 773295c1f7aaSFeifei Xu // addressBlock: mmhub_utcl2_vml2vcdec 773395c1f7aaSFeifei Xu //VM_CONTEXT0_CNTL 773495c1f7aaSFeifei Xu #define VM_CONTEXT0_CNTL__ENABLE_CONTEXT__SHIFT 0x0 773595c1f7aaSFeifei Xu #define VM_CONTEXT0_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 773695c1f7aaSFeifei Xu #define VM_CONTEXT0_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 773795c1f7aaSFeifei Xu #define VM_CONTEXT0_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 773895c1f7aaSFeifei Xu #define VM_CONTEXT0_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 773995c1f7aaSFeifei Xu #define VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 774095c1f7aaSFeifei Xu #define VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa 774195c1f7aaSFeifei Xu #define VM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb 774295c1f7aaSFeifei Xu #define VM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc 774395c1f7aaSFeifei Xu #define VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd 774495c1f7aaSFeifei Xu #define VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe 774595c1f7aaSFeifei Xu #define VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf 774695c1f7aaSFeifei Xu #define VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 774795c1f7aaSFeifei Xu #define VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 774895c1f7aaSFeifei Xu #define VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 774995c1f7aaSFeifei Xu #define VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 775095c1f7aaSFeifei Xu #define VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 775195c1f7aaSFeifei Xu #define VM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 775295c1f7aaSFeifei Xu #define VM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 775395c1f7aaSFeifei Xu #define VM_CONTEXT0_CNTL__ENABLE_CONTEXT_MASK 0x00000001L 775495c1f7aaSFeifei Xu #define VM_CONTEXT0_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L 775595c1f7aaSFeifei Xu #define VM_CONTEXT0_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L 775695c1f7aaSFeifei Xu #define VM_CONTEXT0_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L 775795c1f7aaSFeifei Xu #define VM_CONTEXT0_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L 775895c1f7aaSFeifei Xu #define VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L 775995c1f7aaSFeifei Xu #define VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L 776095c1f7aaSFeifei Xu #define VM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L 776195c1f7aaSFeifei Xu #define VM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L 776295c1f7aaSFeifei Xu #define VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L 776395c1f7aaSFeifei Xu #define VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L 776495c1f7aaSFeifei Xu #define VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L 776595c1f7aaSFeifei Xu #define VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L 776695c1f7aaSFeifei Xu #define VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L 776795c1f7aaSFeifei Xu #define VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L 776895c1f7aaSFeifei Xu #define VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L 776995c1f7aaSFeifei Xu #define VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L 777095c1f7aaSFeifei Xu #define VM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L 777195c1f7aaSFeifei Xu #define VM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L 777295c1f7aaSFeifei Xu //VM_CONTEXT1_CNTL 777395c1f7aaSFeifei Xu #define VM_CONTEXT1_CNTL__ENABLE_CONTEXT__SHIFT 0x0 777495c1f7aaSFeifei Xu #define VM_CONTEXT1_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 777595c1f7aaSFeifei Xu #define VM_CONTEXT1_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 777695c1f7aaSFeifei Xu #define VM_CONTEXT1_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 777795c1f7aaSFeifei Xu #define VM_CONTEXT1_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 777895c1f7aaSFeifei Xu #define VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 777995c1f7aaSFeifei Xu #define VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa 778095c1f7aaSFeifei Xu #define VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb 778195c1f7aaSFeifei Xu #define VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc 778295c1f7aaSFeifei Xu #define VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd 778395c1f7aaSFeifei Xu #define VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe 778495c1f7aaSFeifei Xu #define VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf 778595c1f7aaSFeifei Xu #define VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 778695c1f7aaSFeifei Xu #define VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 778795c1f7aaSFeifei Xu #define VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 778895c1f7aaSFeifei Xu #define VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 778995c1f7aaSFeifei Xu #define VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 779095c1f7aaSFeifei Xu #define VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 779195c1f7aaSFeifei Xu #define VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 779295c1f7aaSFeifei Xu #define VM_CONTEXT1_CNTL__ENABLE_CONTEXT_MASK 0x00000001L 779395c1f7aaSFeifei Xu #define VM_CONTEXT1_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L 779495c1f7aaSFeifei Xu #define VM_CONTEXT1_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L 779595c1f7aaSFeifei Xu #define VM_CONTEXT1_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L 779695c1f7aaSFeifei Xu #define VM_CONTEXT1_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L 779795c1f7aaSFeifei Xu #define VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L 779895c1f7aaSFeifei Xu #define VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L 779995c1f7aaSFeifei Xu #define VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L 780095c1f7aaSFeifei Xu #define VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L 780195c1f7aaSFeifei Xu #define VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L 780295c1f7aaSFeifei Xu #define VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L 780395c1f7aaSFeifei Xu #define VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L 780495c1f7aaSFeifei Xu #define VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L 780595c1f7aaSFeifei Xu #define VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L 780695c1f7aaSFeifei Xu #define VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L 780795c1f7aaSFeifei Xu #define VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L 780895c1f7aaSFeifei Xu #define VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L 780995c1f7aaSFeifei Xu #define VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L 781095c1f7aaSFeifei Xu #define VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L 781195c1f7aaSFeifei Xu //VM_CONTEXT2_CNTL 781295c1f7aaSFeifei Xu #define VM_CONTEXT2_CNTL__ENABLE_CONTEXT__SHIFT 0x0 781395c1f7aaSFeifei Xu #define VM_CONTEXT2_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 781495c1f7aaSFeifei Xu #define VM_CONTEXT2_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 781595c1f7aaSFeifei Xu #define VM_CONTEXT2_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 781695c1f7aaSFeifei Xu #define VM_CONTEXT2_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 781795c1f7aaSFeifei Xu #define VM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 781895c1f7aaSFeifei Xu #define VM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa 781995c1f7aaSFeifei Xu #define VM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb 782095c1f7aaSFeifei Xu #define VM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc 782195c1f7aaSFeifei Xu #define VM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd 782295c1f7aaSFeifei Xu #define VM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe 782395c1f7aaSFeifei Xu #define VM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf 782495c1f7aaSFeifei Xu #define VM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 782595c1f7aaSFeifei Xu #define VM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 782695c1f7aaSFeifei Xu #define VM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 782795c1f7aaSFeifei Xu #define VM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 782895c1f7aaSFeifei Xu #define VM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 782995c1f7aaSFeifei Xu #define VM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 783095c1f7aaSFeifei Xu #define VM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 783195c1f7aaSFeifei Xu #define VM_CONTEXT2_CNTL__ENABLE_CONTEXT_MASK 0x00000001L 783295c1f7aaSFeifei Xu #define VM_CONTEXT2_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L 783395c1f7aaSFeifei Xu #define VM_CONTEXT2_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L 783495c1f7aaSFeifei Xu #define VM_CONTEXT2_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L 783595c1f7aaSFeifei Xu #define VM_CONTEXT2_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L 783695c1f7aaSFeifei Xu #define VM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L 783795c1f7aaSFeifei Xu #define VM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L 783895c1f7aaSFeifei Xu #define VM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L 783995c1f7aaSFeifei Xu #define VM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L 784095c1f7aaSFeifei Xu #define VM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L 784195c1f7aaSFeifei Xu #define VM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L 784295c1f7aaSFeifei Xu #define VM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L 784395c1f7aaSFeifei Xu #define VM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L 784495c1f7aaSFeifei Xu #define VM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L 784595c1f7aaSFeifei Xu #define VM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L 784695c1f7aaSFeifei Xu #define VM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L 784795c1f7aaSFeifei Xu #define VM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L 784895c1f7aaSFeifei Xu #define VM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L 784995c1f7aaSFeifei Xu #define VM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L 785095c1f7aaSFeifei Xu //VM_CONTEXT3_CNTL 785195c1f7aaSFeifei Xu #define VM_CONTEXT3_CNTL__ENABLE_CONTEXT__SHIFT 0x0 785295c1f7aaSFeifei Xu #define VM_CONTEXT3_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 785395c1f7aaSFeifei Xu #define VM_CONTEXT3_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 785495c1f7aaSFeifei Xu #define VM_CONTEXT3_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 785595c1f7aaSFeifei Xu #define VM_CONTEXT3_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 785695c1f7aaSFeifei Xu #define VM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 785795c1f7aaSFeifei Xu #define VM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa 785895c1f7aaSFeifei Xu #define VM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb 785995c1f7aaSFeifei Xu #define VM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc 786095c1f7aaSFeifei Xu #define VM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd 786195c1f7aaSFeifei Xu #define VM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe 786295c1f7aaSFeifei Xu #define VM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf 786395c1f7aaSFeifei Xu #define VM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 786495c1f7aaSFeifei Xu #define VM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 786595c1f7aaSFeifei Xu #define VM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 786695c1f7aaSFeifei Xu #define VM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 786795c1f7aaSFeifei Xu #define VM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 786895c1f7aaSFeifei Xu #define VM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 786995c1f7aaSFeifei Xu #define VM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 787095c1f7aaSFeifei Xu #define VM_CONTEXT3_CNTL__ENABLE_CONTEXT_MASK 0x00000001L 787195c1f7aaSFeifei Xu #define VM_CONTEXT3_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L 787295c1f7aaSFeifei Xu #define VM_CONTEXT3_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L 787395c1f7aaSFeifei Xu #define VM_CONTEXT3_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L 787495c1f7aaSFeifei Xu #define VM_CONTEXT3_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L 787595c1f7aaSFeifei Xu #define VM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L 787695c1f7aaSFeifei Xu #define VM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L 787795c1f7aaSFeifei Xu #define VM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L 787895c1f7aaSFeifei Xu #define VM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L 787995c1f7aaSFeifei Xu #define VM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L 788095c1f7aaSFeifei Xu #define VM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L 788195c1f7aaSFeifei Xu #define VM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L 788295c1f7aaSFeifei Xu #define VM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L 788395c1f7aaSFeifei Xu #define VM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L 788495c1f7aaSFeifei Xu #define VM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L 788595c1f7aaSFeifei Xu #define VM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L 788695c1f7aaSFeifei Xu #define VM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L 788795c1f7aaSFeifei Xu #define VM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L 788895c1f7aaSFeifei Xu #define VM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L 788995c1f7aaSFeifei Xu //VM_CONTEXT4_CNTL 789095c1f7aaSFeifei Xu #define VM_CONTEXT4_CNTL__ENABLE_CONTEXT__SHIFT 0x0 789195c1f7aaSFeifei Xu #define VM_CONTEXT4_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 789295c1f7aaSFeifei Xu #define VM_CONTEXT4_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 789395c1f7aaSFeifei Xu #define VM_CONTEXT4_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 789495c1f7aaSFeifei Xu #define VM_CONTEXT4_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 789595c1f7aaSFeifei Xu #define VM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 789695c1f7aaSFeifei Xu #define VM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa 789795c1f7aaSFeifei Xu #define VM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb 789895c1f7aaSFeifei Xu #define VM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc 789995c1f7aaSFeifei Xu #define VM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd 790095c1f7aaSFeifei Xu #define VM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe 790195c1f7aaSFeifei Xu #define VM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf 790295c1f7aaSFeifei Xu #define VM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 790395c1f7aaSFeifei Xu #define VM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 790495c1f7aaSFeifei Xu #define VM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 790595c1f7aaSFeifei Xu #define VM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 790695c1f7aaSFeifei Xu #define VM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 790795c1f7aaSFeifei Xu #define VM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 790895c1f7aaSFeifei Xu #define VM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 790995c1f7aaSFeifei Xu #define VM_CONTEXT4_CNTL__ENABLE_CONTEXT_MASK 0x00000001L 791095c1f7aaSFeifei Xu #define VM_CONTEXT4_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L 791195c1f7aaSFeifei Xu #define VM_CONTEXT4_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L 791295c1f7aaSFeifei Xu #define VM_CONTEXT4_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L 791395c1f7aaSFeifei Xu #define VM_CONTEXT4_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L 791495c1f7aaSFeifei Xu #define VM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L 791595c1f7aaSFeifei Xu #define VM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L 791695c1f7aaSFeifei Xu #define VM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L 791795c1f7aaSFeifei Xu #define VM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L 791895c1f7aaSFeifei Xu #define VM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L 791995c1f7aaSFeifei Xu #define VM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L 792095c1f7aaSFeifei Xu #define VM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L 792195c1f7aaSFeifei Xu #define VM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L 792295c1f7aaSFeifei Xu #define VM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L 792395c1f7aaSFeifei Xu #define VM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L 792495c1f7aaSFeifei Xu #define VM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L 792595c1f7aaSFeifei Xu #define VM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L 792695c1f7aaSFeifei Xu #define VM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L 792795c1f7aaSFeifei Xu #define VM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L 792895c1f7aaSFeifei Xu //VM_CONTEXT5_CNTL 792995c1f7aaSFeifei Xu #define VM_CONTEXT5_CNTL__ENABLE_CONTEXT__SHIFT 0x0 793095c1f7aaSFeifei Xu #define VM_CONTEXT5_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 793195c1f7aaSFeifei Xu #define VM_CONTEXT5_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 793295c1f7aaSFeifei Xu #define VM_CONTEXT5_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 793395c1f7aaSFeifei Xu #define VM_CONTEXT5_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 793495c1f7aaSFeifei Xu #define VM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 793595c1f7aaSFeifei Xu #define VM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa 793695c1f7aaSFeifei Xu #define VM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb 793795c1f7aaSFeifei Xu #define VM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc 793895c1f7aaSFeifei Xu #define VM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd 793995c1f7aaSFeifei Xu #define VM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe 794095c1f7aaSFeifei Xu #define VM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf 794195c1f7aaSFeifei Xu #define VM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 794295c1f7aaSFeifei Xu #define VM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 794395c1f7aaSFeifei Xu #define VM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 794495c1f7aaSFeifei Xu #define VM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 794595c1f7aaSFeifei Xu #define VM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 794695c1f7aaSFeifei Xu #define VM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 794795c1f7aaSFeifei Xu #define VM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 794895c1f7aaSFeifei Xu #define VM_CONTEXT5_CNTL__ENABLE_CONTEXT_MASK 0x00000001L 794995c1f7aaSFeifei Xu #define VM_CONTEXT5_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L 795095c1f7aaSFeifei Xu #define VM_CONTEXT5_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L 795195c1f7aaSFeifei Xu #define VM_CONTEXT5_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L 795295c1f7aaSFeifei Xu #define VM_CONTEXT5_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L 795395c1f7aaSFeifei Xu #define VM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L 795495c1f7aaSFeifei Xu #define VM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L 795595c1f7aaSFeifei Xu #define VM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L 795695c1f7aaSFeifei Xu #define VM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L 795795c1f7aaSFeifei Xu #define VM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L 795895c1f7aaSFeifei Xu #define VM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L 795995c1f7aaSFeifei Xu #define VM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L 796095c1f7aaSFeifei Xu #define VM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L 796195c1f7aaSFeifei Xu #define VM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L 796295c1f7aaSFeifei Xu #define VM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L 796395c1f7aaSFeifei Xu #define VM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L 796495c1f7aaSFeifei Xu #define VM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L 796595c1f7aaSFeifei Xu #define VM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L 796695c1f7aaSFeifei Xu #define VM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L 796795c1f7aaSFeifei Xu //VM_CONTEXT6_CNTL 796895c1f7aaSFeifei Xu #define VM_CONTEXT6_CNTL__ENABLE_CONTEXT__SHIFT 0x0 796995c1f7aaSFeifei Xu #define VM_CONTEXT6_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 797095c1f7aaSFeifei Xu #define VM_CONTEXT6_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 797195c1f7aaSFeifei Xu #define VM_CONTEXT6_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 797295c1f7aaSFeifei Xu #define VM_CONTEXT6_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 797395c1f7aaSFeifei Xu #define VM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 797495c1f7aaSFeifei Xu #define VM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa 797595c1f7aaSFeifei Xu #define VM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb 797695c1f7aaSFeifei Xu #define VM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc 797795c1f7aaSFeifei Xu #define VM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd 797895c1f7aaSFeifei Xu #define VM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe 797995c1f7aaSFeifei Xu #define VM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf 798095c1f7aaSFeifei Xu #define VM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 798195c1f7aaSFeifei Xu #define VM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 798295c1f7aaSFeifei Xu #define VM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 798395c1f7aaSFeifei Xu #define VM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 798495c1f7aaSFeifei Xu #define VM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 798595c1f7aaSFeifei Xu #define VM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 798695c1f7aaSFeifei Xu #define VM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 798795c1f7aaSFeifei Xu #define VM_CONTEXT6_CNTL__ENABLE_CONTEXT_MASK 0x00000001L 798895c1f7aaSFeifei Xu #define VM_CONTEXT6_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L 798995c1f7aaSFeifei Xu #define VM_CONTEXT6_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L 799095c1f7aaSFeifei Xu #define VM_CONTEXT6_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L 799195c1f7aaSFeifei Xu #define VM_CONTEXT6_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L 799295c1f7aaSFeifei Xu #define VM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L 799395c1f7aaSFeifei Xu #define VM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L 799495c1f7aaSFeifei Xu #define VM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L 799595c1f7aaSFeifei Xu #define VM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L 799695c1f7aaSFeifei Xu #define VM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L 799795c1f7aaSFeifei Xu #define VM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L 799895c1f7aaSFeifei Xu #define VM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L 799995c1f7aaSFeifei Xu #define VM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L 800095c1f7aaSFeifei Xu #define VM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L 800195c1f7aaSFeifei Xu #define VM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L 800295c1f7aaSFeifei Xu #define VM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L 800395c1f7aaSFeifei Xu #define VM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L 800495c1f7aaSFeifei Xu #define VM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L 800595c1f7aaSFeifei Xu #define VM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L 800695c1f7aaSFeifei Xu //VM_CONTEXT7_CNTL 800795c1f7aaSFeifei Xu #define VM_CONTEXT7_CNTL__ENABLE_CONTEXT__SHIFT 0x0 800895c1f7aaSFeifei Xu #define VM_CONTEXT7_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 800995c1f7aaSFeifei Xu #define VM_CONTEXT7_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 801095c1f7aaSFeifei Xu #define VM_CONTEXT7_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 801195c1f7aaSFeifei Xu #define VM_CONTEXT7_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 801295c1f7aaSFeifei Xu #define VM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 801395c1f7aaSFeifei Xu #define VM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa 801495c1f7aaSFeifei Xu #define VM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb 801595c1f7aaSFeifei Xu #define VM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc 801695c1f7aaSFeifei Xu #define VM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd 801795c1f7aaSFeifei Xu #define VM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe 801895c1f7aaSFeifei Xu #define VM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf 801995c1f7aaSFeifei Xu #define VM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 802095c1f7aaSFeifei Xu #define VM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 802195c1f7aaSFeifei Xu #define VM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 802295c1f7aaSFeifei Xu #define VM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 802395c1f7aaSFeifei Xu #define VM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 802495c1f7aaSFeifei Xu #define VM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 802595c1f7aaSFeifei Xu #define VM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 802695c1f7aaSFeifei Xu #define VM_CONTEXT7_CNTL__ENABLE_CONTEXT_MASK 0x00000001L 802795c1f7aaSFeifei Xu #define VM_CONTEXT7_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L 802895c1f7aaSFeifei Xu #define VM_CONTEXT7_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L 802995c1f7aaSFeifei Xu #define VM_CONTEXT7_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L 803095c1f7aaSFeifei Xu #define VM_CONTEXT7_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L 803195c1f7aaSFeifei Xu #define VM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L 803295c1f7aaSFeifei Xu #define VM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L 803395c1f7aaSFeifei Xu #define VM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L 803495c1f7aaSFeifei Xu #define VM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L 803595c1f7aaSFeifei Xu #define VM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L 803695c1f7aaSFeifei Xu #define VM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L 803795c1f7aaSFeifei Xu #define VM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L 803895c1f7aaSFeifei Xu #define VM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L 803995c1f7aaSFeifei Xu #define VM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L 804095c1f7aaSFeifei Xu #define VM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L 804195c1f7aaSFeifei Xu #define VM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L 804295c1f7aaSFeifei Xu #define VM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L 804395c1f7aaSFeifei Xu #define VM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L 804495c1f7aaSFeifei Xu #define VM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L 804595c1f7aaSFeifei Xu //VM_CONTEXT8_CNTL 804695c1f7aaSFeifei Xu #define VM_CONTEXT8_CNTL__ENABLE_CONTEXT__SHIFT 0x0 804795c1f7aaSFeifei Xu #define VM_CONTEXT8_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 804895c1f7aaSFeifei Xu #define VM_CONTEXT8_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 804995c1f7aaSFeifei Xu #define VM_CONTEXT8_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 805095c1f7aaSFeifei Xu #define VM_CONTEXT8_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 805195c1f7aaSFeifei Xu #define VM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 805295c1f7aaSFeifei Xu #define VM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa 805395c1f7aaSFeifei Xu #define VM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb 805495c1f7aaSFeifei Xu #define VM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc 805595c1f7aaSFeifei Xu #define VM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd 805695c1f7aaSFeifei Xu #define VM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe 805795c1f7aaSFeifei Xu #define VM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf 805895c1f7aaSFeifei Xu #define VM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 805995c1f7aaSFeifei Xu #define VM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 806095c1f7aaSFeifei Xu #define VM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 806195c1f7aaSFeifei Xu #define VM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 806295c1f7aaSFeifei Xu #define VM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 806395c1f7aaSFeifei Xu #define VM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 806495c1f7aaSFeifei Xu #define VM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 806595c1f7aaSFeifei Xu #define VM_CONTEXT8_CNTL__ENABLE_CONTEXT_MASK 0x00000001L 806695c1f7aaSFeifei Xu #define VM_CONTEXT8_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L 806795c1f7aaSFeifei Xu #define VM_CONTEXT8_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L 806895c1f7aaSFeifei Xu #define VM_CONTEXT8_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L 806995c1f7aaSFeifei Xu #define VM_CONTEXT8_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L 807095c1f7aaSFeifei Xu #define VM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L 807195c1f7aaSFeifei Xu #define VM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L 807295c1f7aaSFeifei Xu #define VM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L 807395c1f7aaSFeifei Xu #define VM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L 807495c1f7aaSFeifei Xu #define VM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L 807595c1f7aaSFeifei Xu #define VM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L 807695c1f7aaSFeifei Xu #define VM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L 807795c1f7aaSFeifei Xu #define VM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L 807895c1f7aaSFeifei Xu #define VM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L 807995c1f7aaSFeifei Xu #define VM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L 808095c1f7aaSFeifei Xu #define VM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L 808195c1f7aaSFeifei Xu #define VM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L 808295c1f7aaSFeifei Xu #define VM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L 808395c1f7aaSFeifei Xu #define VM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L 808495c1f7aaSFeifei Xu //VM_CONTEXT9_CNTL 808595c1f7aaSFeifei Xu #define VM_CONTEXT9_CNTL__ENABLE_CONTEXT__SHIFT 0x0 808695c1f7aaSFeifei Xu #define VM_CONTEXT9_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 808795c1f7aaSFeifei Xu #define VM_CONTEXT9_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 808895c1f7aaSFeifei Xu #define VM_CONTEXT9_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 808995c1f7aaSFeifei Xu #define VM_CONTEXT9_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 809095c1f7aaSFeifei Xu #define VM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 809195c1f7aaSFeifei Xu #define VM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa 809295c1f7aaSFeifei Xu #define VM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb 809395c1f7aaSFeifei Xu #define VM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc 809495c1f7aaSFeifei Xu #define VM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd 809595c1f7aaSFeifei Xu #define VM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe 809695c1f7aaSFeifei Xu #define VM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf 809795c1f7aaSFeifei Xu #define VM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 809895c1f7aaSFeifei Xu #define VM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 809995c1f7aaSFeifei Xu #define VM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 810095c1f7aaSFeifei Xu #define VM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 810195c1f7aaSFeifei Xu #define VM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 810295c1f7aaSFeifei Xu #define VM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 810395c1f7aaSFeifei Xu #define VM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 810495c1f7aaSFeifei Xu #define VM_CONTEXT9_CNTL__ENABLE_CONTEXT_MASK 0x00000001L 810595c1f7aaSFeifei Xu #define VM_CONTEXT9_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L 810695c1f7aaSFeifei Xu #define VM_CONTEXT9_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L 810795c1f7aaSFeifei Xu #define VM_CONTEXT9_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L 810895c1f7aaSFeifei Xu #define VM_CONTEXT9_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L 810995c1f7aaSFeifei Xu #define VM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L 811095c1f7aaSFeifei Xu #define VM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L 811195c1f7aaSFeifei Xu #define VM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L 811295c1f7aaSFeifei Xu #define VM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L 811395c1f7aaSFeifei Xu #define VM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L 811495c1f7aaSFeifei Xu #define VM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L 811595c1f7aaSFeifei Xu #define VM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L 811695c1f7aaSFeifei Xu #define VM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L 811795c1f7aaSFeifei Xu #define VM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L 811895c1f7aaSFeifei Xu #define VM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L 811995c1f7aaSFeifei Xu #define VM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L 812095c1f7aaSFeifei Xu #define VM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L 812195c1f7aaSFeifei Xu #define VM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L 812295c1f7aaSFeifei Xu #define VM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L 812395c1f7aaSFeifei Xu //VM_CONTEXT10_CNTL 812495c1f7aaSFeifei Xu #define VM_CONTEXT10_CNTL__ENABLE_CONTEXT__SHIFT 0x0 812595c1f7aaSFeifei Xu #define VM_CONTEXT10_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 812695c1f7aaSFeifei Xu #define VM_CONTEXT10_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 812795c1f7aaSFeifei Xu #define VM_CONTEXT10_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 812895c1f7aaSFeifei Xu #define VM_CONTEXT10_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 812995c1f7aaSFeifei Xu #define VM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 813095c1f7aaSFeifei Xu #define VM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa 813195c1f7aaSFeifei Xu #define VM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb 813295c1f7aaSFeifei Xu #define VM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc 813395c1f7aaSFeifei Xu #define VM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd 813495c1f7aaSFeifei Xu #define VM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe 813595c1f7aaSFeifei Xu #define VM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf 813695c1f7aaSFeifei Xu #define VM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 813795c1f7aaSFeifei Xu #define VM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 813895c1f7aaSFeifei Xu #define VM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 813995c1f7aaSFeifei Xu #define VM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 814095c1f7aaSFeifei Xu #define VM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 814195c1f7aaSFeifei Xu #define VM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 814295c1f7aaSFeifei Xu #define VM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 814395c1f7aaSFeifei Xu #define VM_CONTEXT10_CNTL__ENABLE_CONTEXT_MASK 0x00000001L 814495c1f7aaSFeifei Xu #define VM_CONTEXT10_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L 814595c1f7aaSFeifei Xu #define VM_CONTEXT10_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L 814695c1f7aaSFeifei Xu #define VM_CONTEXT10_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L 814795c1f7aaSFeifei Xu #define VM_CONTEXT10_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L 814895c1f7aaSFeifei Xu #define VM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L 814995c1f7aaSFeifei Xu #define VM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L 815095c1f7aaSFeifei Xu #define VM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L 815195c1f7aaSFeifei Xu #define VM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L 815295c1f7aaSFeifei Xu #define VM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L 815395c1f7aaSFeifei Xu #define VM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L 815495c1f7aaSFeifei Xu #define VM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L 815595c1f7aaSFeifei Xu #define VM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L 815695c1f7aaSFeifei Xu #define VM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L 815795c1f7aaSFeifei Xu #define VM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L 815895c1f7aaSFeifei Xu #define VM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L 815995c1f7aaSFeifei Xu #define VM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L 816095c1f7aaSFeifei Xu #define VM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L 816195c1f7aaSFeifei Xu #define VM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L 816295c1f7aaSFeifei Xu //VM_CONTEXT11_CNTL 816395c1f7aaSFeifei Xu #define VM_CONTEXT11_CNTL__ENABLE_CONTEXT__SHIFT 0x0 816495c1f7aaSFeifei Xu #define VM_CONTEXT11_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 816595c1f7aaSFeifei Xu #define VM_CONTEXT11_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 816695c1f7aaSFeifei Xu #define VM_CONTEXT11_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 816795c1f7aaSFeifei Xu #define VM_CONTEXT11_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 816895c1f7aaSFeifei Xu #define VM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 816995c1f7aaSFeifei Xu #define VM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa 817095c1f7aaSFeifei Xu #define VM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb 817195c1f7aaSFeifei Xu #define VM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc 817295c1f7aaSFeifei Xu #define VM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd 817395c1f7aaSFeifei Xu #define VM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe 817495c1f7aaSFeifei Xu #define VM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf 817595c1f7aaSFeifei Xu #define VM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 817695c1f7aaSFeifei Xu #define VM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 817795c1f7aaSFeifei Xu #define VM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 817895c1f7aaSFeifei Xu #define VM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 817995c1f7aaSFeifei Xu #define VM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 818095c1f7aaSFeifei Xu #define VM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 818195c1f7aaSFeifei Xu #define VM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 818295c1f7aaSFeifei Xu #define VM_CONTEXT11_CNTL__ENABLE_CONTEXT_MASK 0x00000001L 818395c1f7aaSFeifei Xu #define VM_CONTEXT11_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L 818495c1f7aaSFeifei Xu #define VM_CONTEXT11_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L 818595c1f7aaSFeifei Xu #define VM_CONTEXT11_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L 818695c1f7aaSFeifei Xu #define VM_CONTEXT11_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L 818795c1f7aaSFeifei Xu #define VM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L 818895c1f7aaSFeifei Xu #define VM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L 818995c1f7aaSFeifei Xu #define VM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L 819095c1f7aaSFeifei Xu #define VM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L 819195c1f7aaSFeifei Xu #define VM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L 819295c1f7aaSFeifei Xu #define VM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L 819395c1f7aaSFeifei Xu #define VM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L 819495c1f7aaSFeifei Xu #define VM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L 819595c1f7aaSFeifei Xu #define VM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L 819695c1f7aaSFeifei Xu #define VM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L 819795c1f7aaSFeifei Xu #define VM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L 819895c1f7aaSFeifei Xu #define VM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L 819995c1f7aaSFeifei Xu #define VM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L 820095c1f7aaSFeifei Xu #define VM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L 820195c1f7aaSFeifei Xu //VM_CONTEXT12_CNTL 820295c1f7aaSFeifei Xu #define VM_CONTEXT12_CNTL__ENABLE_CONTEXT__SHIFT 0x0 820395c1f7aaSFeifei Xu #define VM_CONTEXT12_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 820495c1f7aaSFeifei Xu #define VM_CONTEXT12_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 820595c1f7aaSFeifei Xu #define VM_CONTEXT12_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 820695c1f7aaSFeifei Xu #define VM_CONTEXT12_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 820795c1f7aaSFeifei Xu #define VM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 820895c1f7aaSFeifei Xu #define VM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa 820995c1f7aaSFeifei Xu #define VM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb 821095c1f7aaSFeifei Xu #define VM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc 821195c1f7aaSFeifei Xu #define VM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd 821295c1f7aaSFeifei Xu #define VM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe 821395c1f7aaSFeifei Xu #define VM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf 821495c1f7aaSFeifei Xu #define VM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 821595c1f7aaSFeifei Xu #define VM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 821695c1f7aaSFeifei Xu #define VM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 821795c1f7aaSFeifei Xu #define VM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 821895c1f7aaSFeifei Xu #define VM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 821995c1f7aaSFeifei Xu #define VM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 822095c1f7aaSFeifei Xu #define VM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 822195c1f7aaSFeifei Xu #define VM_CONTEXT12_CNTL__ENABLE_CONTEXT_MASK 0x00000001L 822295c1f7aaSFeifei Xu #define VM_CONTEXT12_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L 822395c1f7aaSFeifei Xu #define VM_CONTEXT12_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L 822495c1f7aaSFeifei Xu #define VM_CONTEXT12_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L 822595c1f7aaSFeifei Xu #define VM_CONTEXT12_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L 822695c1f7aaSFeifei Xu #define VM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L 822795c1f7aaSFeifei Xu #define VM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L 822895c1f7aaSFeifei Xu #define VM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L 822995c1f7aaSFeifei Xu #define VM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L 823095c1f7aaSFeifei Xu #define VM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L 823195c1f7aaSFeifei Xu #define VM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L 823295c1f7aaSFeifei Xu #define VM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L 823395c1f7aaSFeifei Xu #define VM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L 823495c1f7aaSFeifei Xu #define VM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L 823595c1f7aaSFeifei Xu #define VM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L 823695c1f7aaSFeifei Xu #define VM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L 823795c1f7aaSFeifei Xu #define VM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L 823895c1f7aaSFeifei Xu #define VM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L 823995c1f7aaSFeifei Xu #define VM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L 824095c1f7aaSFeifei Xu //VM_CONTEXT13_CNTL 824195c1f7aaSFeifei Xu #define VM_CONTEXT13_CNTL__ENABLE_CONTEXT__SHIFT 0x0 824295c1f7aaSFeifei Xu #define VM_CONTEXT13_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 824395c1f7aaSFeifei Xu #define VM_CONTEXT13_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 824495c1f7aaSFeifei Xu #define VM_CONTEXT13_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 824595c1f7aaSFeifei Xu #define VM_CONTEXT13_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 824695c1f7aaSFeifei Xu #define VM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 824795c1f7aaSFeifei Xu #define VM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa 824895c1f7aaSFeifei Xu #define VM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb 824995c1f7aaSFeifei Xu #define VM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc 825095c1f7aaSFeifei Xu #define VM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd 825195c1f7aaSFeifei Xu #define VM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe 825295c1f7aaSFeifei Xu #define VM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf 825395c1f7aaSFeifei Xu #define VM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 825495c1f7aaSFeifei Xu #define VM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 825595c1f7aaSFeifei Xu #define VM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 825695c1f7aaSFeifei Xu #define VM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 825795c1f7aaSFeifei Xu #define VM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 825895c1f7aaSFeifei Xu #define VM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 825995c1f7aaSFeifei Xu #define VM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 826095c1f7aaSFeifei Xu #define VM_CONTEXT13_CNTL__ENABLE_CONTEXT_MASK 0x00000001L 826195c1f7aaSFeifei Xu #define VM_CONTEXT13_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L 826295c1f7aaSFeifei Xu #define VM_CONTEXT13_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L 826395c1f7aaSFeifei Xu #define VM_CONTEXT13_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L 826495c1f7aaSFeifei Xu #define VM_CONTEXT13_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L 826595c1f7aaSFeifei Xu #define VM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L 826695c1f7aaSFeifei Xu #define VM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L 826795c1f7aaSFeifei Xu #define VM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L 826895c1f7aaSFeifei Xu #define VM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L 826995c1f7aaSFeifei Xu #define VM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L 827095c1f7aaSFeifei Xu #define VM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L 827195c1f7aaSFeifei Xu #define VM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L 827295c1f7aaSFeifei Xu #define VM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L 827395c1f7aaSFeifei Xu #define VM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L 827495c1f7aaSFeifei Xu #define VM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L 827595c1f7aaSFeifei Xu #define VM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L 827695c1f7aaSFeifei Xu #define VM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L 827795c1f7aaSFeifei Xu #define VM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L 827895c1f7aaSFeifei Xu #define VM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L 827995c1f7aaSFeifei Xu //VM_CONTEXT14_CNTL 828095c1f7aaSFeifei Xu #define VM_CONTEXT14_CNTL__ENABLE_CONTEXT__SHIFT 0x0 828195c1f7aaSFeifei Xu #define VM_CONTEXT14_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 828295c1f7aaSFeifei Xu #define VM_CONTEXT14_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 828395c1f7aaSFeifei Xu #define VM_CONTEXT14_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 828495c1f7aaSFeifei Xu #define VM_CONTEXT14_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 828595c1f7aaSFeifei Xu #define VM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 828695c1f7aaSFeifei Xu #define VM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa 828795c1f7aaSFeifei Xu #define VM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb 828895c1f7aaSFeifei Xu #define VM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc 828995c1f7aaSFeifei Xu #define VM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd 829095c1f7aaSFeifei Xu #define VM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe 829195c1f7aaSFeifei Xu #define VM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf 829295c1f7aaSFeifei Xu #define VM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 829395c1f7aaSFeifei Xu #define VM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 829495c1f7aaSFeifei Xu #define VM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 829595c1f7aaSFeifei Xu #define VM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 829695c1f7aaSFeifei Xu #define VM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 829795c1f7aaSFeifei Xu #define VM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 829895c1f7aaSFeifei Xu #define VM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 829995c1f7aaSFeifei Xu #define VM_CONTEXT14_CNTL__ENABLE_CONTEXT_MASK 0x00000001L 830095c1f7aaSFeifei Xu #define VM_CONTEXT14_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L 830195c1f7aaSFeifei Xu #define VM_CONTEXT14_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L 830295c1f7aaSFeifei Xu #define VM_CONTEXT14_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L 830395c1f7aaSFeifei Xu #define VM_CONTEXT14_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L 830495c1f7aaSFeifei Xu #define VM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L 830595c1f7aaSFeifei Xu #define VM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L 830695c1f7aaSFeifei Xu #define VM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L 830795c1f7aaSFeifei Xu #define VM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L 830895c1f7aaSFeifei Xu #define VM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L 830995c1f7aaSFeifei Xu #define VM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L 831095c1f7aaSFeifei Xu #define VM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L 831195c1f7aaSFeifei Xu #define VM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L 831295c1f7aaSFeifei Xu #define VM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L 831395c1f7aaSFeifei Xu #define VM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L 831495c1f7aaSFeifei Xu #define VM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L 831595c1f7aaSFeifei Xu #define VM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L 831695c1f7aaSFeifei Xu #define VM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L 831795c1f7aaSFeifei Xu #define VM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L 831895c1f7aaSFeifei Xu //VM_CONTEXT15_CNTL 831995c1f7aaSFeifei Xu #define VM_CONTEXT15_CNTL__ENABLE_CONTEXT__SHIFT 0x0 832095c1f7aaSFeifei Xu #define VM_CONTEXT15_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 832195c1f7aaSFeifei Xu #define VM_CONTEXT15_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 832295c1f7aaSFeifei Xu #define VM_CONTEXT15_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 832395c1f7aaSFeifei Xu #define VM_CONTEXT15_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 832495c1f7aaSFeifei Xu #define VM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 832595c1f7aaSFeifei Xu #define VM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa 832695c1f7aaSFeifei Xu #define VM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb 832795c1f7aaSFeifei Xu #define VM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc 832895c1f7aaSFeifei Xu #define VM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd 832995c1f7aaSFeifei Xu #define VM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe 833095c1f7aaSFeifei Xu #define VM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf 833195c1f7aaSFeifei Xu #define VM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 833295c1f7aaSFeifei Xu #define VM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 833395c1f7aaSFeifei Xu #define VM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 833495c1f7aaSFeifei Xu #define VM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 833595c1f7aaSFeifei Xu #define VM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 833695c1f7aaSFeifei Xu #define VM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 833795c1f7aaSFeifei Xu #define VM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 833895c1f7aaSFeifei Xu #define VM_CONTEXT15_CNTL__ENABLE_CONTEXT_MASK 0x00000001L 833995c1f7aaSFeifei Xu #define VM_CONTEXT15_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L 834095c1f7aaSFeifei Xu #define VM_CONTEXT15_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L 834195c1f7aaSFeifei Xu #define VM_CONTEXT15_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L 834295c1f7aaSFeifei Xu #define VM_CONTEXT15_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L 834395c1f7aaSFeifei Xu #define VM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L 834495c1f7aaSFeifei Xu #define VM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L 834595c1f7aaSFeifei Xu #define VM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L 834695c1f7aaSFeifei Xu #define VM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L 834795c1f7aaSFeifei Xu #define VM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L 834895c1f7aaSFeifei Xu #define VM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L 834995c1f7aaSFeifei Xu #define VM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L 835095c1f7aaSFeifei Xu #define VM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L 835195c1f7aaSFeifei Xu #define VM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L 835295c1f7aaSFeifei Xu #define VM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L 835395c1f7aaSFeifei Xu #define VM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L 835495c1f7aaSFeifei Xu #define VM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L 835595c1f7aaSFeifei Xu #define VM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L 835695c1f7aaSFeifei Xu #define VM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L 835795c1f7aaSFeifei Xu //VM_CONTEXTS_DISABLE 835895c1f7aaSFeifei Xu #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_0__SHIFT 0x0 835995c1f7aaSFeifei Xu #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_1__SHIFT 0x1 836095c1f7aaSFeifei Xu #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_2__SHIFT 0x2 836195c1f7aaSFeifei Xu #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_3__SHIFT 0x3 836295c1f7aaSFeifei Xu #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_4__SHIFT 0x4 836395c1f7aaSFeifei Xu #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_5__SHIFT 0x5 836495c1f7aaSFeifei Xu #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_6__SHIFT 0x6 836595c1f7aaSFeifei Xu #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_7__SHIFT 0x7 836695c1f7aaSFeifei Xu #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_8__SHIFT 0x8 836795c1f7aaSFeifei Xu #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_9__SHIFT 0x9 836895c1f7aaSFeifei Xu #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_10__SHIFT 0xa 836995c1f7aaSFeifei Xu #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_11__SHIFT 0xb 837095c1f7aaSFeifei Xu #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_12__SHIFT 0xc 837195c1f7aaSFeifei Xu #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_13__SHIFT 0xd 837295c1f7aaSFeifei Xu #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_14__SHIFT 0xe 837395c1f7aaSFeifei Xu #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_15__SHIFT 0xf 837495c1f7aaSFeifei Xu #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_0_MASK 0x00000001L 837595c1f7aaSFeifei Xu #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_1_MASK 0x00000002L 837695c1f7aaSFeifei Xu #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_2_MASK 0x00000004L 837795c1f7aaSFeifei Xu #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_3_MASK 0x00000008L 837895c1f7aaSFeifei Xu #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_4_MASK 0x00000010L 837995c1f7aaSFeifei Xu #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_5_MASK 0x00000020L 838095c1f7aaSFeifei Xu #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_6_MASK 0x00000040L 838195c1f7aaSFeifei Xu #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_7_MASK 0x00000080L 838295c1f7aaSFeifei Xu #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_8_MASK 0x00000100L 838395c1f7aaSFeifei Xu #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_9_MASK 0x00000200L 838495c1f7aaSFeifei Xu #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_10_MASK 0x00000400L 838595c1f7aaSFeifei Xu #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_11_MASK 0x00000800L 838695c1f7aaSFeifei Xu #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_12_MASK 0x00001000L 838795c1f7aaSFeifei Xu #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_13_MASK 0x00002000L 838895c1f7aaSFeifei Xu #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_14_MASK 0x00004000L 838995c1f7aaSFeifei Xu #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_15_MASK 0x00008000L 839095c1f7aaSFeifei Xu //VM_INVALIDATE_ENG0_SEM 839195c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG0_SEM__SEMAPHORE__SHIFT 0x0 839295c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG0_SEM__SEMAPHORE_MASK 0x00000001L 839395c1f7aaSFeifei Xu //VM_INVALIDATE_ENG1_SEM 839495c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG1_SEM__SEMAPHORE__SHIFT 0x0 839595c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG1_SEM__SEMAPHORE_MASK 0x00000001L 839695c1f7aaSFeifei Xu //VM_INVALIDATE_ENG2_SEM 839795c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG2_SEM__SEMAPHORE__SHIFT 0x0 839895c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG2_SEM__SEMAPHORE_MASK 0x00000001L 839995c1f7aaSFeifei Xu //VM_INVALIDATE_ENG3_SEM 840095c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG3_SEM__SEMAPHORE__SHIFT 0x0 840195c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG3_SEM__SEMAPHORE_MASK 0x00000001L 840295c1f7aaSFeifei Xu //VM_INVALIDATE_ENG4_SEM 840395c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG4_SEM__SEMAPHORE__SHIFT 0x0 840495c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG4_SEM__SEMAPHORE_MASK 0x00000001L 840595c1f7aaSFeifei Xu //VM_INVALIDATE_ENG5_SEM 840695c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG5_SEM__SEMAPHORE__SHIFT 0x0 840795c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG5_SEM__SEMAPHORE_MASK 0x00000001L 840895c1f7aaSFeifei Xu //VM_INVALIDATE_ENG6_SEM 840995c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG6_SEM__SEMAPHORE__SHIFT 0x0 841095c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG6_SEM__SEMAPHORE_MASK 0x00000001L 841195c1f7aaSFeifei Xu //VM_INVALIDATE_ENG7_SEM 841295c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG7_SEM__SEMAPHORE__SHIFT 0x0 841395c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG7_SEM__SEMAPHORE_MASK 0x00000001L 841495c1f7aaSFeifei Xu //VM_INVALIDATE_ENG8_SEM 841595c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG8_SEM__SEMAPHORE__SHIFT 0x0 841695c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG8_SEM__SEMAPHORE_MASK 0x00000001L 841795c1f7aaSFeifei Xu //VM_INVALIDATE_ENG9_SEM 841895c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG9_SEM__SEMAPHORE__SHIFT 0x0 841995c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG9_SEM__SEMAPHORE_MASK 0x00000001L 842095c1f7aaSFeifei Xu //VM_INVALIDATE_ENG10_SEM 842195c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG10_SEM__SEMAPHORE__SHIFT 0x0 842295c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG10_SEM__SEMAPHORE_MASK 0x00000001L 842395c1f7aaSFeifei Xu //VM_INVALIDATE_ENG11_SEM 842495c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG11_SEM__SEMAPHORE__SHIFT 0x0 842595c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG11_SEM__SEMAPHORE_MASK 0x00000001L 842695c1f7aaSFeifei Xu //VM_INVALIDATE_ENG12_SEM 842795c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG12_SEM__SEMAPHORE__SHIFT 0x0 842895c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG12_SEM__SEMAPHORE_MASK 0x00000001L 842995c1f7aaSFeifei Xu //VM_INVALIDATE_ENG13_SEM 843095c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG13_SEM__SEMAPHORE__SHIFT 0x0 843195c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG13_SEM__SEMAPHORE_MASK 0x00000001L 843295c1f7aaSFeifei Xu //VM_INVALIDATE_ENG14_SEM 843395c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG14_SEM__SEMAPHORE__SHIFT 0x0 843495c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG14_SEM__SEMAPHORE_MASK 0x00000001L 843595c1f7aaSFeifei Xu //VM_INVALIDATE_ENG15_SEM 843695c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG15_SEM__SEMAPHORE__SHIFT 0x0 843795c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG15_SEM__SEMAPHORE_MASK 0x00000001L 843895c1f7aaSFeifei Xu //VM_INVALIDATE_ENG16_SEM 843995c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG16_SEM__SEMAPHORE__SHIFT 0x0 844095c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG16_SEM__SEMAPHORE_MASK 0x00000001L 844195c1f7aaSFeifei Xu //VM_INVALIDATE_ENG17_SEM 844295c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG17_SEM__SEMAPHORE__SHIFT 0x0 844395c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG17_SEM__SEMAPHORE_MASK 0x00000001L 844495c1f7aaSFeifei Xu //VM_INVALIDATE_ENG0_REQ 844595c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG0_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 844695c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG0_REQ__FLUSH_TYPE__SHIFT 0x10 844795c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 844895c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 844995c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 845095c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 845195c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 845295c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG0_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 845395c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG0_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL 845495c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG0_REQ__FLUSH_TYPE_MASK 0x00030000L 845595c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L 845695c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L 845795c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L 845895c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L 845995c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L 846095c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG0_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L 846195c1f7aaSFeifei Xu //VM_INVALIDATE_ENG1_REQ 846295c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG1_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 846395c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG1_REQ__FLUSH_TYPE__SHIFT 0x10 846495c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 846595c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 846695c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 846795c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 846895c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 846995c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG1_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 847095c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG1_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL 847195c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG1_REQ__FLUSH_TYPE_MASK 0x00030000L 847295c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L 847395c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L 847495c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L 847595c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L 847695c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L 847795c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG1_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L 847895c1f7aaSFeifei Xu //VM_INVALIDATE_ENG2_REQ 847995c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG2_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 848095c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG2_REQ__FLUSH_TYPE__SHIFT 0x10 848195c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 848295c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 848395c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 848495c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 848595c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 848695c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG2_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 848795c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG2_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL 848895c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG2_REQ__FLUSH_TYPE_MASK 0x00030000L 848995c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L 849095c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L 849195c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L 849295c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L 849395c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L 849495c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG2_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L 849595c1f7aaSFeifei Xu //VM_INVALIDATE_ENG3_REQ 849695c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG3_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 849795c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG3_REQ__FLUSH_TYPE__SHIFT 0x10 849895c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 849995c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 850095c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 850195c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 850295c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 850395c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG3_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 850495c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG3_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL 850595c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG3_REQ__FLUSH_TYPE_MASK 0x00030000L 850695c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L 850795c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L 850895c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L 850995c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L 851095c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L 851195c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG3_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L 851295c1f7aaSFeifei Xu //VM_INVALIDATE_ENG4_REQ 851395c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG4_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 851495c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG4_REQ__FLUSH_TYPE__SHIFT 0x10 851595c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 851695c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 851795c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 851895c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 851995c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 852095c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG4_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 852195c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG4_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL 852295c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG4_REQ__FLUSH_TYPE_MASK 0x00030000L 852395c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L 852495c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L 852595c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L 852695c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L 852795c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L 852895c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG4_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L 852995c1f7aaSFeifei Xu //VM_INVALIDATE_ENG5_REQ 853095c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG5_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 853195c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG5_REQ__FLUSH_TYPE__SHIFT 0x10 853295c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 853395c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 853495c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 853595c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 853695c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 853795c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG5_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 853895c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG5_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL 853995c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG5_REQ__FLUSH_TYPE_MASK 0x00030000L 854095c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L 854195c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L 854295c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L 854395c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L 854495c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L 854595c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG5_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L 854695c1f7aaSFeifei Xu //VM_INVALIDATE_ENG6_REQ 854795c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG6_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 854895c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG6_REQ__FLUSH_TYPE__SHIFT 0x10 854995c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 855095c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 855195c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 855295c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 855395c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 855495c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG6_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 855595c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG6_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL 855695c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG6_REQ__FLUSH_TYPE_MASK 0x00030000L 855795c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L 855895c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L 855995c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L 856095c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L 856195c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L 856295c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG6_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L 856395c1f7aaSFeifei Xu //VM_INVALIDATE_ENG7_REQ 856495c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG7_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 856595c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG7_REQ__FLUSH_TYPE__SHIFT 0x10 856695c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 856795c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 856895c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 856995c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 857095c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 857195c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG7_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 857295c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG7_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL 857395c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG7_REQ__FLUSH_TYPE_MASK 0x00030000L 857495c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L 857595c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L 857695c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L 857795c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L 857895c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L 857995c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG7_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L 858095c1f7aaSFeifei Xu //VM_INVALIDATE_ENG8_REQ 858195c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG8_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 858295c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG8_REQ__FLUSH_TYPE__SHIFT 0x10 858395c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 858495c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 858595c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 858695c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 858795c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 858895c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG8_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 858995c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG8_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL 859095c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG8_REQ__FLUSH_TYPE_MASK 0x00030000L 859195c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L 859295c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L 859395c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L 859495c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L 859595c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L 859695c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG8_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L 859795c1f7aaSFeifei Xu //VM_INVALIDATE_ENG9_REQ 859895c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG9_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 859995c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG9_REQ__FLUSH_TYPE__SHIFT 0x10 860095c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 860195c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 860295c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 860395c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 860495c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 860595c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG9_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 860695c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG9_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL 860795c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG9_REQ__FLUSH_TYPE_MASK 0x00030000L 860895c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L 860995c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L 861095c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L 861195c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L 861295c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L 861395c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG9_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L 861495c1f7aaSFeifei Xu //VM_INVALIDATE_ENG10_REQ 861595c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG10_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 861695c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG10_REQ__FLUSH_TYPE__SHIFT 0x10 861795c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 861895c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 861995c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 862095c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 862195c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 862295c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG10_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 862395c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG10_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL 862495c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG10_REQ__FLUSH_TYPE_MASK 0x00030000L 862595c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L 862695c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L 862795c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L 862895c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L 862995c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L 863095c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG10_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L 863195c1f7aaSFeifei Xu //VM_INVALIDATE_ENG11_REQ 863295c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG11_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 863395c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG11_REQ__FLUSH_TYPE__SHIFT 0x10 863495c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 863595c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 863695c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 863795c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 863895c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 863995c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG11_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 864095c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG11_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL 864195c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG11_REQ__FLUSH_TYPE_MASK 0x00030000L 864295c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L 864395c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L 864495c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L 864595c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L 864695c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L 864795c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG11_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L 864895c1f7aaSFeifei Xu //VM_INVALIDATE_ENG12_REQ 864995c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG12_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 865095c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG12_REQ__FLUSH_TYPE__SHIFT 0x10 865195c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 865295c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 865395c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 865495c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 865595c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 865695c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG12_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 865795c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG12_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL 865895c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG12_REQ__FLUSH_TYPE_MASK 0x00030000L 865995c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L 866095c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L 866195c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L 866295c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L 866395c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L 866495c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG12_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L 866595c1f7aaSFeifei Xu //VM_INVALIDATE_ENG13_REQ 866695c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG13_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 866795c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG13_REQ__FLUSH_TYPE__SHIFT 0x10 866895c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 866995c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 867095c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 867195c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 867295c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 867395c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG13_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 867495c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG13_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL 867595c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG13_REQ__FLUSH_TYPE_MASK 0x00030000L 867695c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L 867795c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L 867895c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L 867995c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L 868095c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L 868195c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG13_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L 868295c1f7aaSFeifei Xu //VM_INVALIDATE_ENG14_REQ 868395c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG14_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 868495c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG14_REQ__FLUSH_TYPE__SHIFT 0x10 868595c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 868695c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 868795c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 868895c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 868995c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 869095c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG14_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 869195c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG14_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL 869295c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG14_REQ__FLUSH_TYPE_MASK 0x00030000L 869395c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L 869495c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L 869595c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L 869695c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L 869795c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L 869895c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG14_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L 869995c1f7aaSFeifei Xu //VM_INVALIDATE_ENG15_REQ 870095c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG15_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 870195c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG15_REQ__FLUSH_TYPE__SHIFT 0x10 870295c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 870395c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 870495c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 870595c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 870695c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 870795c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG15_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 870895c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG15_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL 870995c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG15_REQ__FLUSH_TYPE_MASK 0x00030000L 871095c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L 871195c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L 871295c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L 871395c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L 871495c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L 871595c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG15_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L 871695c1f7aaSFeifei Xu //VM_INVALIDATE_ENG16_REQ 871795c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG16_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 871895c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG16_REQ__FLUSH_TYPE__SHIFT 0x10 871995c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 872095c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 872195c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 872295c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 872395c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 872495c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG16_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 872595c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG16_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL 872695c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG16_REQ__FLUSH_TYPE_MASK 0x00030000L 872795c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L 872895c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L 872995c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L 873095c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L 873195c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L 873295c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG16_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L 873395c1f7aaSFeifei Xu //VM_INVALIDATE_ENG17_REQ 873495c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG17_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 873595c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG17_REQ__FLUSH_TYPE__SHIFT 0x10 873695c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 873795c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 873895c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 873995c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 874095c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 874195c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG17_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 874295c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG17_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL 874395c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG17_REQ__FLUSH_TYPE_MASK 0x00030000L 874495c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L 874595c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L 874695c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L 874795c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L 874895c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L 874995c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG17_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L 875095c1f7aaSFeifei Xu //VM_INVALIDATE_ENG0_ACK 875195c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG0_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 875295c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG0_ACK__SEMAPHORE__SHIFT 0x10 875395c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG0_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL 875495c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG0_ACK__SEMAPHORE_MASK 0x00010000L 875595c1f7aaSFeifei Xu //VM_INVALIDATE_ENG1_ACK 875695c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG1_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 875795c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG1_ACK__SEMAPHORE__SHIFT 0x10 875895c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG1_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL 875995c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG1_ACK__SEMAPHORE_MASK 0x00010000L 876095c1f7aaSFeifei Xu //VM_INVALIDATE_ENG2_ACK 876195c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG2_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 876295c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG2_ACK__SEMAPHORE__SHIFT 0x10 876395c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG2_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL 876495c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG2_ACK__SEMAPHORE_MASK 0x00010000L 876595c1f7aaSFeifei Xu //VM_INVALIDATE_ENG3_ACK 876695c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG3_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 876795c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG3_ACK__SEMAPHORE__SHIFT 0x10 876895c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG3_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL 876995c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG3_ACK__SEMAPHORE_MASK 0x00010000L 877095c1f7aaSFeifei Xu //VM_INVALIDATE_ENG4_ACK 877195c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG4_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 877295c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG4_ACK__SEMAPHORE__SHIFT 0x10 877395c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG4_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL 877495c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG4_ACK__SEMAPHORE_MASK 0x00010000L 877595c1f7aaSFeifei Xu //VM_INVALIDATE_ENG5_ACK 877695c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG5_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 877795c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG5_ACK__SEMAPHORE__SHIFT 0x10 877895c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG5_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL 877995c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG5_ACK__SEMAPHORE_MASK 0x00010000L 878095c1f7aaSFeifei Xu //VM_INVALIDATE_ENG6_ACK 878195c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG6_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 878295c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG6_ACK__SEMAPHORE__SHIFT 0x10 878395c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG6_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL 878495c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG6_ACK__SEMAPHORE_MASK 0x00010000L 878595c1f7aaSFeifei Xu //VM_INVALIDATE_ENG7_ACK 878695c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG7_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 878795c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG7_ACK__SEMAPHORE__SHIFT 0x10 878895c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG7_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL 878995c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG7_ACK__SEMAPHORE_MASK 0x00010000L 879095c1f7aaSFeifei Xu //VM_INVALIDATE_ENG8_ACK 879195c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG8_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 879295c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG8_ACK__SEMAPHORE__SHIFT 0x10 879395c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG8_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL 879495c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG8_ACK__SEMAPHORE_MASK 0x00010000L 879595c1f7aaSFeifei Xu //VM_INVALIDATE_ENG9_ACK 879695c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG9_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 879795c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG9_ACK__SEMAPHORE__SHIFT 0x10 879895c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG9_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL 879995c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG9_ACK__SEMAPHORE_MASK 0x00010000L 880095c1f7aaSFeifei Xu //VM_INVALIDATE_ENG10_ACK 880195c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG10_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 880295c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG10_ACK__SEMAPHORE__SHIFT 0x10 880395c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG10_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL 880495c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG10_ACK__SEMAPHORE_MASK 0x00010000L 880595c1f7aaSFeifei Xu //VM_INVALIDATE_ENG11_ACK 880695c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG11_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 880795c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG11_ACK__SEMAPHORE__SHIFT 0x10 880895c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG11_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL 880995c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG11_ACK__SEMAPHORE_MASK 0x00010000L 881095c1f7aaSFeifei Xu //VM_INVALIDATE_ENG12_ACK 881195c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG12_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 881295c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG12_ACK__SEMAPHORE__SHIFT 0x10 881395c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG12_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL 881495c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG12_ACK__SEMAPHORE_MASK 0x00010000L 881595c1f7aaSFeifei Xu //VM_INVALIDATE_ENG13_ACK 881695c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG13_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 881795c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG13_ACK__SEMAPHORE__SHIFT 0x10 881895c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG13_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL 881995c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG13_ACK__SEMAPHORE_MASK 0x00010000L 882095c1f7aaSFeifei Xu //VM_INVALIDATE_ENG14_ACK 882195c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG14_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 882295c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG14_ACK__SEMAPHORE__SHIFT 0x10 882395c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG14_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL 882495c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG14_ACK__SEMAPHORE_MASK 0x00010000L 882595c1f7aaSFeifei Xu //VM_INVALIDATE_ENG15_ACK 882695c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG15_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 882795c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG15_ACK__SEMAPHORE__SHIFT 0x10 882895c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG15_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL 882995c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG15_ACK__SEMAPHORE_MASK 0x00010000L 883095c1f7aaSFeifei Xu //VM_INVALIDATE_ENG16_ACK 883195c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG16_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 883295c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG16_ACK__SEMAPHORE__SHIFT 0x10 883395c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG16_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL 883495c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG16_ACK__SEMAPHORE_MASK 0x00010000L 883595c1f7aaSFeifei Xu //VM_INVALIDATE_ENG17_ACK 883695c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG17_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 883795c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG17_ACK__SEMAPHORE__SHIFT 0x10 883895c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG17_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL 883995c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG17_ACK__SEMAPHORE_MASK 0x00010000L 884095c1f7aaSFeifei Xu //VM_INVALIDATE_ENG0_ADDR_RANGE_LO32 884195c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG0_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 884295c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG0_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 884395c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG0_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L 884495c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG0_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL 884595c1f7aaSFeifei Xu //VM_INVALIDATE_ENG0_ADDR_RANGE_HI32 884695c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG0_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 884795c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG0_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL 884895c1f7aaSFeifei Xu //VM_INVALIDATE_ENG1_ADDR_RANGE_LO32 884995c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG1_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 885095c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG1_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 885195c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG1_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L 885295c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG1_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL 885395c1f7aaSFeifei Xu //VM_INVALIDATE_ENG1_ADDR_RANGE_HI32 885495c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG1_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 885595c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG1_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL 885695c1f7aaSFeifei Xu //VM_INVALIDATE_ENG2_ADDR_RANGE_LO32 885795c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG2_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 885895c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG2_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 885995c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG2_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L 886095c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG2_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL 886195c1f7aaSFeifei Xu //VM_INVALIDATE_ENG2_ADDR_RANGE_HI32 886295c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG2_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 886395c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG2_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL 886495c1f7aaSFeifei Xu //VM_INVALIDATE_ENG3_ADDR_RANGE_LO32 886595c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG3_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 886695c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG3_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 886795c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG3_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L 886895c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG3_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL 886995c1f7aaSFeifei Xu //VM_INVALIDATE_ENG3_ADDR_RANGE_HI32 887095c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG3_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 887195c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG3_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL 887295c1f7aaSFeifei Xu //VM_INVALIDATE_ENG4_ADDR_RANGE_LO32 887395c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG4_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 887495c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG4_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 887595c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG4_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L 887695c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG4_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL 887795c1f7aaSFeifei Xu //VM_INVALIDATE_ENG4_ADDR_RANGE_HI32 887895c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG4_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 887995c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG4_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL 888095c1f7aaSFeifei Xu //VM_INVALIDATE_ENG5_ADDR_RANGE_LO32 888195c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG5_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 888295c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG5_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 888395c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG5_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L 888495c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG5_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL 888595c1f7aaSFeifei Xu //VM_INVALIDATE_ENG5_ADDR_RANGE_HI32 888695c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG5_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 888795c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG5_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL 888895c1f7aaSFeifei Xu //VM_INVALIDATE_ENG6_ADDR_RANGE_LO32 888995c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG6_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 889095c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG6_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 889195c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG6_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L 889295c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG6_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL 889395c1f7aaSFeifei Xu //VM_INVALIDATE_ENG6_ADDR_RANGE_HI32 889495c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG6_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 889595c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG6_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL 889695c1f7aaSFeifei Xu //VM_INVALIDATE_ENG7_ADDR_RANGE_LO32 889795c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG7_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 889895c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG7_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 889995c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG7_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L 890095c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG7_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL 890195c1f7aaSFeifei Xu //VM_INVALIDATE_ENG7_ADDR_RANGE_HI32 890295c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG7_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 890395c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG7_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL 890495c1f7aaSFeifei Xu //VM_INVALIDATE_ENG8_ADDR_RANGE_LO32 890595c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG8_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 890695c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG8_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 890795c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG8_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L 890895c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG8_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL 890995c1f7aaSFeifei Xu //VM_INVALIDATE_ENG8_ADDR_RANGE_HI32 891095c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG8_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 891195c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG8_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL 891295c1f7aaSFeifei Xu //VM_INVALIDATE_ENG9_ADDR_RANGE_LO32 891395c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG9_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 891495c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG9_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 891595c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG9_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L 891695c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG9_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL 891795c1f7aaSFeifei Xu //VM_INVALIDATE_ENG9_ADDR_RANGE_HI32 891895c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG9_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 891995c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG9_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL 892095c1f7aaSFeifei Xu //VM_INVALIDATE_ENG10_ADDR_RANGE_LO32 892195c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG10_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 892295c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG10_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 892395c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG10_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L 892495c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG10_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL 892595c1f7aaSFeifei Xu //VM_INVALIDATE_ENG10_ADDR_RANGE_HI32 892695c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG10_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 892795c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG10_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL 892895c1f7aaSFeifei Xu //VM_INVALIDATE_ENG11_ADDR_RANGE_LO32 892995c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG11_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 893095c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG11_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 893195c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG11_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L 893295c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG11_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL 893395c1f7aaSFeifei Xu //VM_INVALIDATE_ENG11_ADDR_RANGE_HI32 893495c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG11_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 893595c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG11_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL 893695c1f7aaSFeifei Xu //VM_INVALIDATE_ENG12_ADDR_RANGE_LO32 893795c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG12_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 893895c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG12_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 893995c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG12_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L 894095c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG12_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL 894195c1f7aaSFeifei Xu //VM_INVALIDATE_ENG12_ADDR_RANGE_HI32 894295c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG12_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 894395c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG12_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL 894495c1f7aaSFeifei Xu //VM_INVALIDATE_ENG13_ADDR_RANGE_LO32 894595c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG13_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 894695c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG13_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 894795c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG13_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L 894895c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG13_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL 894995c1f7aaSFeifei Xu //VM_INVALIDATE_ENG13_ADDR_RANGE_HI32 895095c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG13_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 895195c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG13_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL 895295c1f7aaSFeifei Xu //VM_INVALIDATE_ENG14_ADDR_RANGE_LO32 895395c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG14_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 895495c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG14_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 895595c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG14_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L 895695c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG14_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL 895795c1f7aaSFeifei Xu //VM_INVALIDATE_ENG14_ADDR_RANGE_HI32 895895c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG14_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 895995c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG14_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL 896095c1f7aaSFeifei Xu //VM_INVALIDATE_ENG15_ADDR_RANGE_LO32 896195c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG15_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 896295c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG15_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 896395c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG15_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L 896495c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG15_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL 896595c1f7aaSFeifei Xu //VM_INVALIDATE_ENG15_ADDR_RANGE_HI32 896695c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG15_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 896795c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG15_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL 896895c1f7aaSFeifei Xu //VM_INVALIDATE_ENG16_ADDR_RANGE_LO32 896995c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG16_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 897095c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG16_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 897195c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG16_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L 897295c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG16_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL 897395c1f7aaSFeifei Xu //VM_INVALIDATE_ENG16_ADDR_RANGE_HI32 897495c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG16_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 897595c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG16_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL 897695c1f7aaSFeifei Xu //VM_INVALIDATE_ENG17_ADDR_RANGE_LO32 897795c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG17_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 897895c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG17_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 897995c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG17_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L 898095c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG17_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL 898195c1f7aaSFeifei Xu //VM_INVALIDATE_ENG17_ADDR_RANGE_HI32 898295c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG17_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 898395c1f7aaSFeifei Xu #define VM_INVALIDATE_ENG17_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL 898495c1f7aaSFeifei Xu //VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32 898595c1f7aaSFeifei Xu #define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 898695c1f7aaSFeifei Xu #define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL 898795c1f7aaSFeifei Xu //VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32 898895c1f7aaSFeifei Xu #define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 898995c1f7aaSFeifei Xu #define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL 899095c1f7aaSFeifei Xu //VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32 899195c1f7aaSFeifei Xu #define VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 899295c1f7aaSFeifei Xu #define VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL 899395c1f7aaSFeifei Xu //VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32 899495c1f7aaSFeifei Xu #define VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 899595c1f7aaSFeifei Xu #define VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL 899695c1f7aaSFeifei Xu //VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32 899795c1f7aaSFeifei Xu #define VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 899895c1f7aaSFeifei Xu #define VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL 899995c1f7aaSFeifei Xu //VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32 900095c1f7aaSFeifei Xu #define VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 900195c1f7aaSFeifei Xu #define VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL 900295c1f7aaSFeifei Xu //VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32 900395c1f7aaSFeifei Xu #define VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 900495c1f7aaSFeifei Xu #define VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL 900595c1f7aaSFeifei Xu //VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32 900695c1f7aaSFeifei Xu #define VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 900795c1f7aaSFeifei Xu #define VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL 900895c1f7aaSFeifei Xu //VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32 900995c1f7aaSFeifei Xu #define VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 901095c1f7aaSFeifei Xu #define VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL 901195c1f7aaSFeifei Xu //VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32 901295c1f7aaSFeifei Xu #define VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 901395c1f7aaSFeifei Xu #define VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL 901495c1f7aaSFeifei Xu //VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32 901595c1f7aaSFeifei Xu #define VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 901695c1f7aaSFeifei Xu #define VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL 901795c1f7aaSFeifei Xu //VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32 901895c1f7aaSFeifei Xu #define VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 901995c1f7aaSFeifei Xu #define VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL 902095c1f7aaSFeifei Xu //VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32 902195c1f7aaSFeifei Xu #define VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 902295c1f7aaSFeifei Xu #define VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL 902395c1f7aaSFeifei Xu //VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32 902495c1f7aaSFeifei Xu #define VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 902595c1f7aaSFeifei Xu #define VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL 902695c1f7aaSFeifei Xu //VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32 902795c1f7aaSFeifei Xu #define VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 902895c1f7aaSFeifei Xu #define VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL 902995c1f7aaSFeifei Xu //VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32 903095c1f7aaSFeifei Xu #define VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 903195c1f7aaSFeifei Xu #define VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL 903295c1f7aaSFeifei Xu //VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32 903395c1f7aaSFeifei Xu #define VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 903495c1f7aaSFeifei Xu #define VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL 903595c1f7aaSFeifei Xu //VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32 903695c1f7aaSFeifei Xu #define VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 903795c1f7aaSFeifei Xu #define VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL 903895c1f7aaSFeifei Xu //VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32 903995c1f7aaSFeifei Xu #define VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 904095c1f7aaSFeifei Xu #define VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL 904195c1f7aaSFeifei Xu //VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32 904295c1f7aaSFeifei Xu #define VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 904395c1f7aaSFeifei Xu #define VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL 904495c1f7aaSFeifei Xu //VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32 904595c1f7aaSFeifei Xu #define VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 904695c1f7aaSFeifei Xu #define VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL 904795c1f7aaSFeifei Xu //VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32 904895c1f7aaSFeifei Xu #define VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 904995c1f7aaSFeifei Xu #define VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL 905095c1f7aaSFeifei Xu //VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32 905195c1f7aaSFeifei Xu #define VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 905295c1f7aaSFeifei Xu #define VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL 905395c1f7aaSFeifei Xu //VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32 905495c1f7aaSFeifei Xu #define VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 905595c1f7aaSFeifei Xu #define VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL 905695c1f7aaSFeifei Xu //VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32 905795c1f7aaSFeifei Xu #define VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 905895c1f7aaSFeifei Xu #define VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL 905995c1f7aaSFeifei Xu //VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32 906095c1f7aaSFeifei Xu #define VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 906195c1f7aaSFeifei Xu #define VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL 906295c1f7aaSFeifei Xu //VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32 906395c1f7aaSFeifei Xu #define VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 906495c1f7aaSFeifei Xu #define VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL 906595c1f7aaSFeifei Xu //VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32 906695c1f7aaSFeifei Xu #define VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 906795c1f7aaSFeifei Xu #define VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL 906895c1f7aaSFeifei Xu //VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32 906995c1f7aaSFeifei Xu #define VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 907095c1f7aaSFeifei Xu #define VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL 907195c1f7aaSFeifei Xu //VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32 907295c1f7aaSFeifei Xu #define VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 907395c1f7aaSFeifei Xu #define VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL 907495c1f7aaSFeifei Xu //VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32 907595c1f7aaSFeifei Xu #define VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 907695c1f7aaSFeifei Xu #define VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL 907795c1f7aaSFeifei Xu //VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32 907895c1f7aaSFeifei Xu #define VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 907995c1f7aaSFeifei Xu #define VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL 908095c1f7aaSFeifei Xu //VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32 908195c1f7aaSFeifei Xu #define VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 908295c1f7aaSFeifei Xu #define VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 908395c1f7aaSFeifei Xu //VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32 908495c1f7aaSFeifei Xu #define VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 908595c1f7aaSFeifei Xu #define VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 908695c1f7aaSFeifei Xu //VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32 908795c1f7aaSFeifei Xu #define VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 908895c1f7aaSFeifei Xu #define VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 908995c1f7aaSFeifei Xu //VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32 909095c1f7aaSFeifei Xu #define VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 909195c1f7aaSFeifei Xu #define VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 909295c1f7aaSFeifei Xu //VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32 909395c1f7aaSFeifei Xu #define VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 909495c1f7aaSFeifei Xu #define VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 909595c1f7aaSFeifei Xu //VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32 909695c1f7aaSFeifei Xu #define VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 909795c1f7aaSFeifei Xu #define VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 909895c1f7aaSFeifei Xu //VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32 909995c1f7aaSFeifei Xu #define VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 910095c1f7aaSFeifei Xu #define VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 910195c1f7aaSFeifei Xu //VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32 910295c1f7aaSFeifei Xu #define VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 910395c1f7aaSFeifei Xu #define VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 910495c1f7aaSFeifei Xu //VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32 910595c1f7aaSFeifei Xu #define VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 910695c1f7aaSFeifei Xu #define VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 910795c1f7aaSFeifei Xu //VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32 910895c1f7aaSFeifei Xu #define VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 910995c1f7aaSFeifei Xu #define VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 911095c1f7aaSFeifei Xu //VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32 911195c1f7aaSFeifei Xu #define VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 911295c1f7aaSFeifei Xu #define VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 911395c1f7aaSFeifei Xu //VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32 911495c1f7aaSFeifei Xu #define VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 911595c1f7aaSFeifei Xu #define VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 911695c1f7aaSFeifei Xu //VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32 911795c1f7aaSFeifei Xu #define VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 911895c1f7aaSFeifei Xu #define VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 911995c1f7aaSFeifei Xu //VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32 912095c1f7aaSFeifei Xu #define VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 912195c1f7aaSFeifei Xu #define VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 912295c1f7aaSFeifei Xu //VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32 912395c1f7aaSFeifei Xu #define VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 912495c1f7aaSFeifei Xu #define VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 912595c1f7aaSFeifei Xu //VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32 912695c1f7aaSFeifei Xu #define VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 912795c1f7aaSFeifei Xu #define VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 912895c1f7aaSFeifei Xu //VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32 912995c1f7aaSFeifei Xu #define VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 913095c1f7aaSFeifei Xu #define VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 913195c1f7aaSFeifei Xu //VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32 913295c1f7aaSFeifei Xu #define VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 913395c1f7aaSFeifei Xu #define VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 913495c1f7aaSFeifei Xu //VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32 913595c1f7aaSFeifei Xu #define VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 913695c1f7aaSFeifei Xu #define VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 913795c1f7aaSFeifei Xu //VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32 913895c1f7aaSFeifei Xu #define VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 913995c1f7aaSFeifei Xu #define VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 914095c1f7aaSFeifei Xu //VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32 914195c1f7aaSFeifei Xu #define VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 914295c1f7aaSFeifei Xu #define VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 914395c1f7aaSFeifei Xu //VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32 914495c1f7aaSFeifei Xu #define VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 914595c1f7aaSFeifei Xu #define VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 914695c1f7aaSFeifei Xu //VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32 914795c1f7aaSFeifei Xu #define VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 914895c1f7aaSFeifei Xu #define VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 914995c1f7aaSFeifei Xu //VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32 915095c1f7aaSFeifei Xu #define VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 915195c1f7aaSFeifei Xu #define VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 915295c1f7aaSFeifei Xu //VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32 915395c1f7aaSFeifei Xu #define VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 915495c1f7aaSFeifei Xu #define VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 915595c1f7aaSFeifei Xu //VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32 915695c1f7aaSFeifei Xu #define VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 915795c1f7aaSFeifei Xu #define VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 915895c1f7aaSFeifei Xu //VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32 915995c1f7aaSFeifei Xu #define VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 916095c1f7aaSFeifei Xu #define VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 916195c1f7aaSFeifei Xu //VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32 916295c1f7aaSFeifei Xu #define VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 916395c1f7aaSFeifei Xu #define VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 916495c1f7aaSFeifei Xu //VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32 916595c1f7aaSFeifei Xu #define VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 916695c1f7aaSFeifei Xu #define VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 916795c1f7aaSFeifei Xu //VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32 916895c1f7aaSFeifei Xu #define VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 916995c1f7aaSFeifei Xu #define VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 917095c1f7aaSFeifei Xu //VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32 917195c1f7aaSFeifei Xu #define VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 917295c1f7aaSFeifei Xu #define VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 917395c1f7aaSFeifei Xu //VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32 917495c1f7aaSFeifei Xu #define VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 917595c1f7aaSFeifei Xu #define VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 917695c1f7aaSFeifei Xu //VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32 917795c1f7aaSFeifei Xu #define VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 917895c1f7aaSFeifei Xu #define VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 917995c1f7aaSFeifei Xu //VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32 918095c1f7aaSFeifei Xu #define VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 918195c1f7aaSFeifei Xu #define VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 918295c1f7aaSFeifei Xu //VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32 918395c1f7aaSFeifei Xu #define VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 918495c1f7aaSFeifei Xu #define VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 918595c1f7aaSFeifei Xu //VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32 918695c1f7aaSFeifei Xu #define VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 918795c1f7aaSFeifei Xu #define VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 918895c1f7aaSFeifei Xu //VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32 918995c1f7aaSFeifei Xu #define VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 919095c1f7aaSFeifei Xu #define VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 919195c1f7aaSFeifei Xu //VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32 919295c1f7aaSFeifei Xu #define VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 919395c1f7aaSFeifei Xu #define VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 919495c1f7aaSFeifei Xu //VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32 919595c1f7aaSFeifei Xu #define VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 919695c1f7aaSFeifei Xu #define VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 919795c1f7aaSFeifei Xu //VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32 919895c1f7aaSFeifei Xu #define VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 919995c1f7aaSFeifei Xu #define VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 920095c1f7aaSFeifei Xu //VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32 920195c1f7aaSFeifei Xu #define VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 920295c1f7aaSFeifei Xu #define VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 920395c1f7aaSFeifei Xu //VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32 920495c1f7aaSFeifei Xu #define VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 920595c1f7aaSFeifei Xu #define VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 920695c1f7aaSFeifei Xu //VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32 920795c1f7aaSFeifei Xu #define VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 920895c1f7aaSFeifei Xu #define VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 920995c1f7aaSFeifei Xu //VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32 921095c1f7aaSFeifei Xu #define VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 921195c1f7aaSFeifei Xu #define VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 921295c1f7aaSFeifei Xu //VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32 921395c1f7aaSFeifei Xu #define VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 921495c1f7aaSFeifei Xu #define VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 921595c1f7aaSFeifei Xu //VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32 921695c1f7aaSFeifei Xu #define VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 921795c1f7aaSFeifei Xu #define VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 921895c1f7aaSFeifei Xu //VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32 921995c1f7aaSFeifei Xu #define VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 922095c1f7aaSFeifei Xu #define VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 922195c1f7aaSFeifei Xu //VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32 922295c1f7aaSFeifei Xu #define VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 922395c1f7aaSFeifei Xu #define VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 922495c1f7aaSFeifei Xu //VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32 922595c1f7aaSFeifei Xu #define VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 922695c1f7aaSFeifei Xu #define VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 922795c1f7aaSFeifei Xu //VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32 922895c1f7aaSFeifei Xu #define VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 922995c1f7aaSFeifei Xu #define VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 923095c1f7aaSFeifei Xu //VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32 923195c1f7aaSFeifei Xu #define VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 923295c1f7aaSFeifei Xu #define VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 923395c1f7aaSFeifei Xu //VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32 923495c1f7aaSFeifei Xu #define VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 923595c1f7aaSFeifei Xu #define VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 923695c1f7aaSFeifei Xu //VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32 923795c1f7aaSFeifei Xu #define VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 923895c1f7aaSFeifei Xu #define VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 923995c1f7aaSFeifei Xu //VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32 924095c1f7aaSFeifei Xu #define VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 924195c1f7aaSFeifei Xu #define VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 924295c1f7aaSFeifei Xu //VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32 924395c1f7aaSFeifei Xu #define VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 924495c1f7aaSFeifei Xu #define VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 924595c1f7aaSFeifei Xu //VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32 924695c1f7aaSFeifei Xu #define VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 924795c1f7aaSFeifei Xu #define VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 924895c1f7aaSFeifei Xu //VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32 924995c1f7aaSFeifei Xu #define VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 925095c1f7aaSFeifei Xu #define VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 925195c1f7aaSFeifei Xu //VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32 925295c1f7aaSFeifei Xu #define VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 925395c1f7aaSFeifei Xu #define VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 925495c1f7aaSFeifei Xu //VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32 925595c1f7aaSFeifei Xu #define VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 925695c1f7aaSFeifei Xu #define VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 925795c1f7aaSFeifei Xu //VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32 925895c1f7aaSFeifei Xu #define VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 925995c1f7aaSFeifei Xu #define VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 926095c1f7aaSFeifei Xu //VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32 926195c1f7aaSFeifei Xu #define VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 926295c1f7aaSFeifei Xu #define VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 926395c1f7aaSFeifei Xu //VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32 926495c1f7aaSFeifei Xu #define VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 926595c1f7aaSFeifei Xu #define VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 926695c1f7aaSFeifei Xu //VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32 926795c1f7aaSFeifei Xu #define VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 926895c1f7aaSFeifei Xu #define VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 926995c1f7aaSFeifei Xu //VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32 927095c1f7aaSFeifei Xu #define VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 927195c1f7aaSFeifei Xu #define VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 927295c1f7aaSFeifei Xu 927395c1f7aaSFeifei Xu 927495c1f7aaSFeifei Xu // addressBlock: mmhub_utcl2_vml2pldec 927595c1f7aaSFeifei Xu //MC_VM_L2_PERFCOUNTER0_CFG 927695c1f7aaSFeifei Xu #define MC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 927795c1f7aaSFeifei Xu #define MC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 927895c1f7aaSFeifei Xu #define MC_VM_L2_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 927995c1f7aaSFeifei Xu #define MC_VM_L2_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c 928095c1f7aaSFeifei Xu #define MC_VM_L2_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d 928195c1f7aaSFeifei Xu #define MC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL 928295c1f7aaSFeifei Xu #define MC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L 928395c1f7aaSFeifei Xu #define MC_VM_L2_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L 928495c1f7aaSFeifei Xu #define MC_VM_L2_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L 928595c1f7aaSFeifei Xu #define MC_VM_L2_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L 928695c1f7aaSFeifei Xu //MC_VM_L2_PERFCOUNTER1_CFG 928795c1f7aaSFeifei Xu #define MC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 928895c1f7aaSFeifei Xu #define MC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 928995c1f7aaSFeifei Xu #define MC_VM_L2_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 929095c1f7aaSFeifei Xu #define MC_VM_L2_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c 929195c1f7aaSFeifei Xu #define MC_VM_L2_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d 929295c1f7aaSFeifei Xu #define MC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL 929395c1f7aaSFeifei Xu #define MC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L 929495c1f7aaSFeifei Xu #define MC_VM_L2_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L 929595c1f7aaSFeifei Xu #define MC_VM_L2_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L 929695c1f7aaSFeifei Xu #define MC_VM_L2_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L 929795c1f7aaSFeifei Xu //MC_VM_L2_PERFCOUNTER2_CFG 929895c1f7aaSFeifei Xu #define MC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0 929995c1f7aaSFeifei Xu #define MC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8 930095c1f7aaSFeifei Xu #define MC_VM_L2_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18 930195c1f7aaSFeifei Xu #define MC_VM_L2_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c 930295c1f7aaSFeifei Xu #define MC_VM_L2_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d 930395c1f7aaSFeifei Xu #define MC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL_MASK 0x000000FFL 930495c1f7aaSFeifei Xu #define MC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0x0000FF00L 930595c1f7aaSFeifei Xu #define MC_VM_L2_PERFCOUNTER2_CFG__PERF_MODE_MASK 0x0F000000L 930695c1f7aaSFeifei Xu #define MC_VM_L2_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000L 930795c1f7aaSFeifei Xu #define MC_VM_L2_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000L 930895c1f7aaSFeifei Xu //MC_VM_L2_PERFCOUNTER3_CFG 930995c1f7aaSFeifei Xu #define MC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL__SHIFT 0x0 931095c1f7aaSFeifei Xu #define MC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT 0x8 931195c1f7aaSFeifei Xu #define MC_VM_L2_PERFCOUNTER3_CFG__PERF_MODE__SHIFT 0x18 931295c1f7aaSFeifei Xu #define MC_VM_L2_PERFCOUNTER3_CFG__ENABLE__SHIFT 0x1c 931395c1f7aaSFeifei Xu #define MC_VM_L2_PERFCOUNTER3_CFG__CLEAR__SHIFT 0x1d 931495c1f7aaSFeifei Xu #define MC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL_MASK 0x000000FFL 931595c1f7aaSFeifei Xu #define MC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL_END_MASK 0x0000FF00L 931695c1f7aaSFeifei Xu #define MC_VM_L2_PERFCOUNTER3_CFG__PERF_MODE_MASK 0x0F000000L 931795c1f7aaSFeifei Xu #define MC_VM_L2_PERFCOUNTER3_CFG__ENABLE_MASK 0x10000000L 931895c1f7aaSFeifei Xu #define MC_VM_L2_PERFCOUNTER3_CFG__CLEAR_MASK 0x20000000L 931995c1f7aaSFeifei Xu //MC_VM_L2_PERFCOUNTER4_CFG 932095c1f7aaSFeifei Xu #define MC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL__SHIFT 0x0 932195c1f7aaSFeifei Xu #define MC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL_END__SHIFT 0x8 932295c1f7aaSFeifei Xu #define MC_VM_L2_PERFCOUNTER4_CFG__PERF_MODE__SHIFT 0x18 932395c1f7aaSFeifei Xu #define MC_VM_L2_PERFCOUNTER4_CFG__ENABLE__SHIFT 0x1c 932495c1f7aaSFeifei Xu #define MC_VM_L2_PERFCOUNTER4_CFG__CLEAR__SHIFT 0x1d 932595c1f7aaSFeifei Xu #define MC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL_MASK 0x000000FFL 932695c1f7aaSFeifei Xu #define MC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL_END_MASK 0x0000FF00L 932795c1f7aaSFeifei Xu #define MC_VM_L2_PERFCOUNTER4_CFG__PERF_MODE_MASK 0x0F000000L 932895c1f7aaSFeifei Xu #define MC_VM_L2_PERFCOUNTER4_CFG__ENABLE_MASK 0x10000000L 932995c1f7aaSFeifei Xu #define MC_VM_L2_PERFCOUNTER4_CFG__CLEAR_MASK 0x20000000L 933095c1f7aaSFeifei Xu //MC_VM_L2_PERFCOUNTER5_CFG 933195c1f7aaSFeifei Xu #define MC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL__SHIFT 0x0 933295c1f7aaSFeifei Xu #define MC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL_END__SHIFT 0x8 933395c1f7aaSFeifei Xu #define MC_VM_L2_PERFCOUNTER5_CFG__PERF_MODE__SHIFT 0x18 933495c1f7aaSFeifei Xu #define MC_VM_L2_PERFCOUNTER5_CFG__ENABLE__SHIFT 0x1c 933595c1f7aaSFeifei Xu #define MC_VM_L2_PERFCOUNTER5_CFG__CLEAR__SHIFT 0x1d 933695c1f7aaSFeifei Xu #define MC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL_MASK 0x000000FFL 933795c1f7aaSFeifei Xu #define MC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL_END_MASK 0x0000FF00L 933895c1f7aaSFeifei Xu #define MC_VM_L2_PERFCOUNTER5_CFG__PERF_MODE_MASK 0x0F000000L 933995c1f7aaSFeifei Xu #define MC_VM_L2_PERFCOUNTER5_CFG__ENABLE_MASK 0x10000000L 934095c1f7aaSFeifei Xu #define MC_VM_L2_PERFCOUNTER5_CFG__CLEAR_MASK 0x20000000L 934195c1f7aaSFeifei Xu //MC_VM_L2_PERFCOUNTER6_CFG 934295c1f7aaSFeifei Xu #define MC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL__SHIFT 0x0 934395c1f7aaSFeifei Xu #define MC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL_END__SHIFT 0x8 934495c1f7aaSFeifei Xu #define MC_VM_L2_PERFCOUNTER6_CFG__PERF_MODE__SHIFT 0x18 934595c1f7aaSFeifei Xu #define MC_VM_L2_PERFCOUNTER6_CFG__ENABLE__SHIFT 0x1c 934695c1f7aaSFeifei Xu #define MC_VM_L2_PERFCOUNTER6_CFG__CLEAR__SHIFT 0x1d 934795c1f7aaSFeifei Xu #define MC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL_MASK 0x000000FFL 934895c1f7aaSFeifei Xu #define MC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL_END_MASK 0x0000FF00L 934995c1f7aaSFeifei Xu #define MC_VM_L2_PERFCOUNTER6_CFG__PERF_MODE_MASK 0x0F000000L 935095c1f7aaSFeifei Xu #define MC_VM_L2_PERFCOUNTER6_CFG__ENABLE_MASK 0x10000000L 935195c1f7aaSFeifei Xu #define MC_VM_L2_PERFCOUNTER6_CFG__CLEAR_MASK 0x20000000L 935295c1f7aaSFeifei Xu //MC_VM_L2_PERFCOUNTER7_CFG 935395c1f7aaSFeifei Xu #define MC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL__SHIFT 0x0 935495c1f7aaSFeifei Xu #define MC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL_END__SHIFT 0x8 935595c1f7aaSFeifei Xu #define MC_VM_L2_PERFCOUNTER7_CFG__PERF_MODE__SHIFT 0x18 935695c1f7aaSFeifei Xu #define MC_VM_L2_PERFCOUNTER7_CFG__ENABLE__SHIFT 0x1c 935795c1f7aaSFeifei Xu #define MC_VM_L2_PERFCOUNTER7_CFG__CLEAR__SHIFT 0x1d 935895c1f7aaSFeifei Xu #define MC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL_MASK 0x000000FFL 935995c1f7aaSFeifei Xu #define MC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL_END_MASK 0x0000FF00L 936095c1f7aaSFeifei Xu #define MC_VM_L2_PERFCOUNTER7_CFG__PERF_MODE_MASK 0x0F000000L 936195c1f7aaSFeifei Xu #define MC_VM_L2_PERFCOUNTER7_CFG__ENABLE_MASK 0x10000000L 936295c1f7aaSFeifei Xu #define MC_VM_L2_PERFCOUNTER7_CFG__CLEAR_MASK 0x20000000L 936395c1f7aaSFeifei Xu //MC_VM_L2_PERFCOUNTER_RSLT_CNTL 936495c1f7aaSFeifei Xu #define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 936595c1f7aaSFeifei Xu #define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 936695c1f7aaSFeifei Xu #define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 936795c1f7aaSFeifei Xu #define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 936895c1f7aaSFeifei Xu #define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 936995c1f7aaSFeifei Xu #define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a 937095c1f7aaSFeifei Xu #define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL 937195c1f7aaSFeifei Xu #define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L 937295c1f7aaSFeifei Xu #define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L 937395c1f7aaSFeifei Xu #define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L 937495c1f7aaSFeifei Xu #define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L 937595c1f7aaSFeifei Xu #define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L 937695c1f7aaSFeifei Xu 937795c1f7aaSFeifei Xu 937895c1f7aaSFeifei Xu // addressBlock: mmhub_utcl2_vml2prdec 937995c1f7aaSFeifei Xu //MC_VM_L2_PERFCOUNTER_LO 938095c1f7aaSFeifei Xu #define MC_VM_L2_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 938195c1f7aaSFeifei Xu #define MC_VM_L2_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL 938295c1f7aaSFeifei Xu //MC_VM_L2_PERFCOUNTER_HI 938395c1f7aaSFeifei Xu #define MC_VM_L2_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 938495c1f7aaSFeifei Xu #define MC_VM_L2_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 938595c1f7aaSFeifei Xu #define MC_VM_L2_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL 938695c1f7aaSFeifei Xu #define MC_VM_L2_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L 938795c1f7aaSFeifei Xu 938895c1f7aaSFeifei Xu 938995c1f7aaSFeifei Xu // addressBlock: mmhub_utcl2_vmsharedhvdec 939095c1f7aaSFeifei Xu //MC_VM_FB_SIZE_OFFSET_VF0 939195c1f7aaSFeifei Xu #define MC_VM_FB_SIZE_OFFSET_VF0__VF_FB_SIZE__SHIFT 0x0 939295c1f7aaSFeifei Xu #define MC_VM_FB_SIZE_OFFSET_VF0__VF_FB_OFFSET__SHIFT 0x10 939395c1f7aaSFeifei Xu #define MC_VM_FB_SIZE_OFFSET_VF0__VF_FB_SIZE_MASK 0x0000FFFFL 939495c1f7aaSFeifei Xu #define MC_VM_FB_SIZE_OFFSET_VF0__VF_FB_OFFSET_MASK 0xFFFF0000L 939595c1f7aaSFeifei Xu //MC_VM_FB_SIZE_OFFSET_VF1 939695c1f7aaSFeifei Xu #define MC_VM_FB_SIZE_OFFSET_VF1__VF_FB_SIZE__SHIFT 0x0 939795c1f7aaSFeifei Xu #define MC_VM_FB_SIZE_OFFSET_VF1__VF_FB_OFFSET__SHIFT 0x10 939895c1f7aaSFeifei Xu #define MC_VM_FB_SIZE_OFFSET_VF1__VF_FB_SIZE_MASK 0x0000FFFFL 939995c1f7aaSFeifei Xu #define MC_VM_FB_SIZE_OFFSET_VF1__VF_FB_OFFSET_MASK 0xFFFF0000L 940095c1f7aaSFeifei Xu //MC_VM_FB_SIZE_OFFSET_VF2 940195c1f7aaSFeifei Xu #define MC_VM_FB_SIZE_OFFSET_VF2__VF_FB_SIZE__SHIFT 0x0 940295c1f7aaSFeifei Xu #define MC_VM_FB_SIZE_OFFSET_VF2__VF_FB_OFFSET__SHIFT 0x10 940395c1f7aaSFeifei Xu #define MC_VM_FB_SIZE_OFFSET_VF2__VF_FB_SIZE_MASK 0x0000FFFFL 940495c1f7aaSFeifei Xu #define MC_VM_FB_SIZE_OFFSET_VF2__VF_FB_OFFSET_MASK 0xFFFF0000L 940595c1f7aaSFeifei Xu //MC_VM_FB_SIZE_OFFSET_VF3 940695c1f7aaSFeifei Xu #define MC_VM_FB_SIZE_OFFSET_VF3__VF_FB_SIZE__SHIFT 0x0 940795c1f7aaSFeifei Xu #define MC_VM_FB_SIZE_OFFSET_VF3__VF_FB_OFFSET__SHIFT 0x10 940895c1f7aaSFeifei Xu #define MC_VM_FB_SIZE_OFFSET_VF3__VF_FB_SIZE_MASK 0x0000FFFFL 940995c1f7aaSFeifei Xu #define MC_VM_FB_SIZE_OFFSET_VF3__VF_FB_OFFSET_MASK 0xFFFF0000L 941095c1f7aaSFeifei Xu //MC_VM_FB_SIZE_OFFSET_VF4 941195c1f7aaSFeifei Xu #define MC_VM_FB_SIZE_OFFSET_VF4__VF_FB_SIZE__SHIFT 0x0 941295c1f7aaSFeifei Xu #define MC_VM_FB_SIZE_OFFSET_VF4__VF_FB_OFFSET__SHIFT 0x10 941395c1f7aaSFeifei Xu #define MC_VM_FB_SIZE_OFFSET_VF4__VF_FB_SIZE_MASK 0x0000FFFFL 941495c1f7aaSFeifei Xu #define MC_VM_FB_SIZE_OFFSET_VF4__VF_FB_OFFSET_MASK 0xFFFF0000L 941595c1f7aaSFeifei Xu //MC_VM_FB_SIZE_OFFSET_VF5 941695c1f7aaSFeifei Xu #define MC_VM_FB_SIZE_OFFSET_VF5__VF_FB_SIZE__SHIFT 0x0 941795c1f7aaSFeifei Xu #define MC_VM_FB_SIZE_OFFSET_VF5__VF_FB_OFFSET__SHIFT 0x10 941895c1f7aaSFeifei Xu #define MC_VM_FB_SIZE_OFFSET_VF5__VF_FB_SIZE_MASK 0x0000FFFFL 941995c1f7aaSFeifei Xu #define MC_VM_FB_SIZE_OFFSET_VF5__VF_FB_OFFSET_MASK 0xFFFF0000L 942095c1f7aaSFeifei Xu //MC_VM_FB_SIZE_OFFSET_VF6 942195c1f7aaSFeifei Xu #define MC_VM_FB_SIZE_OFFSET_VF6__VF_FB_SIZE__SHIFT 0x0 942295c1f7aaSFeifei Xu #define MC_VM_FB_SIZE_OFFSET_VF6__VF_FB_OFFSET__SHIFT 0x10 942395c1f7aaSFeifei Xu #define MC_VM_FB_SIZE_OFFSET_VF6__VF_FB_SIZE_MASK 0x0000FFFFL 942495c1f7aaSFeifei Xu #define MC_VM_FB_SIZE_OFFSET_VF6__VF_FB_OFFSET_MASK 0xFFFF0000L 942595c1f7aaSFeifei Xu //MC_VM_FB_SIZE_OFFSET_VF7 942695c1f7aaSFeifei Xu #define MC_VM_FB_SIZE_OFFSET_VF7__VF_FB_SIZE__SHIFT 0x0 942795c1f7aaSFeifei Xu #define MC_VM_FB_SIZE_OFFSET_VF7__VF_FB_OFFSET__SHIFT 0x10 942895c1f7aaSFeifei Xu #define MC_VM_FB_SIZE_OFFSET_VF7__VF_FB_SIZE_MASK 0x0000FFFFL 942995c1f7aaSFeifei Xu #define MC_VM_FB_SIZE_OFFSET_VF7__VF_FB_OFFSET_MASK 0xFFFF0000L 943095c1f7aaSFeifei Xu //MC_VM_FB_SIZE_OFFSET_VF8 943195c1f7aaSFeifei Xu #define MC_VM_FB_SIZE_OFFSET_VF8__VF_FB_SIZE__SHIFT 0x0 943295c1f7aaSFeifei Xu #define MC_VM_FB_SIZE_OFFSET_VF8__VF_FB_OFFSET__SHIFT 0x10 943395c1f7aaSFeifei Xu #define MC_VM_FB_SIZE_OFFSET_VF8__VF_FB_SIZE_MASK 0x0000FFFFL 943495c1f7aaSFeifei Xu #define MC_VM_FB_SIZE_OFFSET_VF8__VF_FB_OFFSET_MASK 0xFFFF0000L 943595c1f7aaSFeifei Xu //MC_VM_FB_SIZE_OFFSET_VF9 943695c1f7aaSFeifei Xu #define MC_VM_FB_SIZE_OFFSET_VF9__VF_FB_SIZE__SHIFT 0x0 943795c1f7aaSFeifei Xu #define MC_VM_FB_SIZE_OFFSET_VF9__VF_FB_OFFSET__SHIFT 0x10 943895c1f7aaSFeifei Xu #define MC_VM_FB_SIZE_OFFSET_VF9__VF_FB_SIZE_MASK 0x0000FFFFL 943995c1f7aaSFeifei Xu #define MC_VM_FB_SIZE_OFFSET_VF9__VF_FB_OFFSET_MASK 0xFFFF0000L 944095c1f7aaSFeifei Xu //MC_VM_FB_SIZE_OFFSET_VF10 944195c1f7aaSFeifei Xu #define MC_VM_FB_SIZE_OFFSET_VF10__VF_FB_SIZE__SHIFT 0x0 944295c1f7aaSFeifei Xu #define MC_VM_FB_SIZE_OFFSET_VF10__VF_FB_OFFSET__SHIFT 0x10 944395c1f7aaSFeifei Xu #define MC_VM_FB_SIZE_OFFSET_VF10__VF_FB_SIZE_MASK 0x0000FFFFL 944495c1f7aaSFeifei Xu #define MC_VM_FB_SIZE_OFFSET_VF10__VF_FB_OFFSET_MASK 0xFFFF0000L 944595c1f7aaSFeifei Xu //MC_VM_FB_SIZE_OFFSET_VF11 944695c1f7aaSFeifei Xu #define MC_VM_FB_SIZE_OFFSET_VF11__VF_FB_SIZE__SHIFT 0x0 944795c1f7aaSFeifei Xu #define MC_VM_FB_SIZE_OFFSET_VF11__VF_FB_OFFSET__SHIFT 0x10 944895c1f7aaSFeifei Xu #define MC_VM_FB_SIZE_OFFSET_VF11__VF_FB_SIZE_MASK 0x0000FFFFL 944995c1f7aaSFeifei Xu #define MC_VM_FB_SIZE_OFFSET_VF11__VF_FB_OFFSET_MASK 0xFFFF0000L 945095c1f7aaSFeifei Xu //MC_VM_FB_SIZE_OFFSET_VF12 945195c1f7aaSFeifei Xu #define MC_VM_FB_SIZE_OFFSET_VF12__VF_FB_SIZE__SHIFT 0x0 945295c1f7aaSFeifei Xu #define MC_VM_FB_SIZE_OFFSET_VF12__VF_FB_OFFSET__SHIFT 0x10 945395c1f7aaSFeifei Xu #define MC_VM_FB_SIZE_OFFSET_VF12__VF_FB_SIZE_MASK 0x0000FFFFL 945495c1f7aaSFeifei Xu #define MC_VM_FB_SIZE_OFFSET_VF12__VF_FB_OFFSET_MASK 0xFFFF0000L 945595c1f7aaSFeifei Xu //MC_VM_FB_SIZE_OFFSET_VF13 945695c1f7aaSFeifei Xu #define MC_VM_FB_SIZE_OFFSET_VF13__VF_FB_SIZE__SHIFT 0x0 945795c1f7aaSFeifei Xu #define MC_VM_FB_SIZE_OFFSET_VF13__VF_FB_OFFSET__SHIFT 0x10 945895c1f7aaSFeifei Xu #define MC_VM_FB_SIZE_OFFSET_VF13__VF_FB_SIZE_MASK 0x0000FFFFL 945995c1f7aaSFeifei Xu #define MC_VM_FB_SIZE_OFFSET_VF13__VF_FB_OFFSET_MASK 0xFFFF0000L 946095c1f7aaSFeifei Xu //MC_VM_FB_SIZE_OFFSET_VF14 946195c1f7aaSFeifei Xu #define MC_VM_FB_SIZE_OFFSET_VF14__VF_FB_SIZE__SHIFT 0x0 946295c1f7aaSFeifei Xu #define MC_VM_FB_SIZE_OFFSET_VF14__VF_FB_OFFSET__SHIFT 0x10 946395c1f7aaSFeifei Xu #define MC_VM_FB_SIZE_OFFSET_VF14__VF_FB_SIZE_MASK 0x0000FFFFL 946495c1f7aaSFeifei Xu #define MC_VM_FB_SIZE_OFFSET_VF14__VF_FB_OFFSET_MASK 0xFFFF0000L 946595c1f7aaSFeifei Xu //MC_VM_FB_SIZE_OFFSET_VF15 946695c1f7aaSFeifei Xu #define MC_VM_FB_SIZE_OFFSET_VF15__VF_FB_SIZE__SHIFT 0x0 946795c1f7aaSFeifei Xu #define MC_VM_FB_SIZE_OFFSET_VF15__VF_FB_OFFSET__SHIFT 0x10 946895c1f7aaSFeifei Xu #define MC_VM_FB_SIZE_OFFSET_VF15__VF_FB_SIZE_MASK 0x0000FFFFL 946995c1f7aaSFeifei Xu #define MC_VM_FB_SIZE_OFFSET_VF15__VF_FB_OFFSET_MASK 0xFFFF0000L 947095c1f7aaSFeifei Xu //VM_IOMMU_MMIO_CNTRL_1 947195c1f7aaSFeifei Xu #define VM_IOMMU_MMIO_CNTRL_1__MARC_EN__SHIFT 0x8 947295c1f7aaSFeifei Xu #define VM_IOMMU_MMIO_CNTRL_1__MARC_EN_MASK 0x00000100L 947395c1f7aaSFeifei Xu //MC_VM_MARC_BASE_LO_0 947495c1f7aaSFeifei Xu #define MC_VM_MARC_BASE_LO_0__MARC_BASE_LO_0__SHIFT 0xc 947595c1f7aaSFeifei Xu #define MC_VM_MARC_BASE_LO_0__MARC_BASE_LO_0_MASK 0xFFFFF000L 947695c1f7aaSFeifei Xu //MC_VM_MARC_BASE_LO_1 947795c1f7aaSFeifei Xu #define MC_VM_MARC_BASE_LO_1__MARC_BASE_LO_1__SHIFT 0xc 947895c1f7aaSFeifei Xu #define MC_VM_MARC_BASE_LO_1__MARC_BASE_LO_1_MASK 0xFFFFF000L 947995c1f7aaSFeifei Xu //MC_VM_MARC_BASE_LO_2 948095c1f7aaSFeifei Xu #define MC_VM_MARC_BASE_LO_2__MARC_BASE_LO_2__SHIFT 0xc 948195c1f7aaSFeifei Xu #define MC_VM_MARC_BASE_LO_2__MARC_BASE_LO_2_MASK 0xFFFFF000L 948295c1f7aaSFeifei Xu //MC_VM_MARC_BASE_LO_3 948395c1f7aaSFeifei Xu #define MC_VM_MARC_BASE_LO_3__MARC_BASE_LO_3__SHIFT 0xc 948495c1f7aaSFeifei Xu #define MC_VM_MARC_BASE_LO_3__MARC_BASE_LO_3_MASK 0xFFFFF000L 948595c1f7aaSFeifei Xu //MC_VM_MARC_BASE_HI_0 948695c1f7aaSFeifei Xu #define MC_VM_MARC_BASE_HI_0__MARC_BASE_HI_0__SHIFT 0x0 948795c1f7aaSFeifei Xu #define MC_VM_MARC_BASE_HI_0__MARC_BASE_HI_0_MASK 0x000FFFFFL 948895c1f7aaSFeifei Xu //MC_VM_MARC_BASE_HI_1 948995c1f7aaSFeifei Xu #define MC_VM_MARC_BASE_HI_1__MARC_BASE_HI_1__SHIFT 0x0 949095c1f7aaSFeifei Xu #define MC_VM_MARC_BASE_HI_1__MARC_BASE_HI_1_MASK 0x000FFFFFL 949195c1f7aaSFeifei Xu //MC_VM_MARC_BASE_HI_2 949295c1f7aaSFeifei Xu #define MC_VM_MARC_BASE_HI_2__MARC_BASE_HI_2__SHIFT 0x0 949395c1f7aaSFeifei Xu #define MC_VM_MARC_BASE_HI_2__MARC_BASE_HI_2_MASK 0x000FFFFFL 949495c1f7aaSFeifei Xu //MC_VM_MARC_BASE_HI_3 949595c1f7aaSFeifei Xu #define MC_VM_MARC_BASE_HI_3__MARC_BASE_HI_3__SHIFT 0x0 949695c1f7aaSFeifei Xu #define MC_VM_MARC_BASE_HI_3__MARC_BASE_HI_3_MASK 0x000FFFFFL 949795c1f7aaSFeifei Xu //MC_VM_MARC_RELOC_LO_0 949895c1f7aaSFeifei Xu #define MC_VM_MARC_RELOC_LO_0__MARC_ENABLE_0__SHIFT 0x0 949995c1f7aaSFeifei Xu #define MC_VM_MARC_RELOC_LO_0__MARC_READONLY_0__SHIFT 0x1 950095c1f7aaSFeifei Xu #define MC_VM_MARC_RELOC_LO_0__MARC_RELOC_LO_0__SHIFT 0xc 950195c1f7aaSFeifei Xu #define MC_VM_MARC_RELOC_LO_0__MARC_ENABLE_0_MASK 0x00000001L 950295c1f7aaSFeifei Xu #define MC_VM_MARC_RELOC_LO_0__MARC_READONLY_0_MASK 0x00000002L 950395c1f7aaSFeifei Xu #define MC_VM_MARC_RELOC_LO_0__MARC_RELOC_LO_0_MASK 0xFFFFF000L 950495c1f7aaSFeifei Xu //MC_VM_MARC_RELOC_LO_1 950595c1f7aaSFeifei Xu #define MC_VM_MARC_RELOC_LO_1__MARC_ENABLE_1__SHIFT 0x0 950695c1f7aaSFeifei Xu #define MC_VM_MARC_RELOC_LO_1__MARC_READONLY_1__SHIFT 0x1 950795c1f7aaSFeifei Xu #define MC_VM_MARC_RELOC_LO_1__MARC_RELOC_LO_1__SHIFT 0xc 950895c1f7aaSFeifei Xu #define MC_VM_MARC_RELOC_LO_1__MARC_ENABLE_1_MASK 0x00000001L 950995c1f7aaSFeifei Xu #define MC_VM_MARC_RELOC_LO_1__MARC_READONLY_1_MASK 0x00000002L 951095c1f7aaSFeifei Xu #define MC_VM_MARC_RELOC_LO_1__MARC_RELOC_LO_1_MASK 0xFFFFF000L 951195c1f7aaSFeifei Xu //MC_VM_MARC_RELOC_LO_2 951295c1f7aaSFeifei Xu #define MC_VM_MARC_RELOC_LO_2__MARC_ENABLE_2__SHIFT 0x0 951395c1f7aaSFeifei Xu #define MC_VM_MARC_RELOC_LO_2__MARC_READONLY_2__SHIFT 0x1 951495c1f7aaSFeifei Xu #define MC_VM_MARC_RELOC_LO_2__MARC_RELOC_LO_2__SHIFT 0xc 951595c1f7aaSFeifei Xu #define MC_VM_MARC_RELOC_LO_2__MARC_ENABLE_2_MASK 0x00000001L 951695c1f7aaSFeifei Xu #define MC_VM_MARC_RELOC_LO_2__MARC_READONLY_2_MASK 0x00000002L 951795c1f7aaSFeifei Xu #define MC_VM_MARC_RELOC_LO_2__MARC_RELOC_LO_2_MASK 0xFFFFF000L 951895c1f7aaSFeifei Xu //MC_VM_MARC_RELOC_LO_3 951995c1f7aaSFeifei Xu #define MC_VM_MARC_RELOC_LO_3__MARC_ENABLE_3__SHIFT 0x0 952095c1f7aaSFeifei Xu #define MC_VM_MARC_RELOC_LO_3__MARC_READONLY_3__SHIFT 0x1 952195c1f7aaSFeifei Xu #define MC_VM_MARC_RELOC_LO_3__MARC_RELOC_LO_3__SHIFT 0xc 952295c1f7aaSFeifei Xu #define MC_VM_MARC_RELOC_LO_3__MARC_ENABLE_3_MASK 0x00000001L 952395c1f7aaSFeifei Xu #define MC_VM_MARC_RELOC_LO_3__MARC_READONLY_3_MASK 0x00000002L 952495c1f7aaSFeifei Xu #define MC_VM_MARC_RELOC_LO_3__MARC_RELOC_LO_3_MASK 0xFFFFF000L 952595c1f7aaSFeifei Xu //MC_VM_MARC_RELOC_HI_0 952695c1f7aaSFeifei Xu #define MC_VM_MARC_RELOC_HI_0__MARC_RELOC_HI_0__SHIFT 0x0 952795c1f7aaSFeifei Xu #define MC_VM_MARC_RELOC_HI_0__MARC_RELOC_HI_0_MASK 0x000FFFFFL 952895c1f7aaSFeifei Xu //MC_VM_MARC_RELOC_HI_1 952995c1f7aaSFeifei Xu #define MC_VM_MARC_RELOC_HI_1__MARC_RELOC_HI_1__SHIFT 0x0 953095c1f7aaSFeifei Xu #define MC_VM_MARC_RELOC_HI_1__MARC_RELOC_HI_1_MASK 0x000FFFFFL 953195c1f7aaSFeifei Xu //MC_VM_MARC_RELOC_HI_2 953295c1f7aaSFeifei Xu #define MC_VM_MARC_RELOC_HI_2__MARC_RELOC_HI_2__SHIFT 0x0 953395c1f7aaSFeifei Xu #define MC_VM_MARC_RELOC_HI_2__MARC_RELOC_HI_2_MASK 0x000FFFFFL 953495c1f7aaSFeifei Xu //MC_VM_MARC_RELOC_HI_3 953595c1f7aaSFeifei Xu #define MC_VM_MARC_RELOC_HI_3__MARC_RELOC_HI_3__SHIFT 0x0 953695c1f7aaSFeifei Xu #define MC_VM_MARC_RELOC_HI_3__MARC_RELOC_HI_3_MASK 0x000FFFFFL 953795c1f7aaSFeifei Xu //MC_VM_MARC_LEN_LO_0 953895c1f7aaSFeifei Xu #define MC_VM_MARC_LEN_LO_0__MARC_LEN_LO_0__SHIFT 0xc 953995c1f7aaSFeifei Xu #define MC_VM_MARC_LEN_LO_0__MARC_LEN_LO_0_MASK 0xFFFFF000L 954095c1f7aaSFeifei Xu //MC_VM_MARC_LEN_LO_1 954195c1f7aaSFeifei Xu #define MC_VM_MARC_LEN_LO_1__MARC_LEN_LO_1__SHIFT 0xc 954295c1f7aaSFeifei Xu #define MC_VM_MARC_LEN_LO_1__MARC_LEN_LO_1_MASK 0xFFFFF000L 954395c1f7aaSFeifei Xu //MC_VM_MARC_LEN_LO_2 954495c1f7aaSFeifei Xu #define MC_VM_MARC_LEN_LO_2__MARC_LEN_LO_2__SHIFT 0xc 954595c1f7aaSFeifei Xu #define MC_VM_MARC_LEN_LO_2__MARC_LEN_LO_2_MASK 0xFFFFF000L 954695c1f7aaSFeifei Xu //MC_VM_MARC_LEN_LO_3 954795c1f7aaSFeifei Xu #define MC_VM_MARC_LEN_LO_3__MARC_LEN_LO_3__SHIFT 0xc 954895c1f7aaSFeifei Xu #define MC_VM_MARC_LEN_LO_3__MARC_LEN_LO_3_MASK 0xFFFFF000L 954995c1f7aaSFeifei Xu //MC_VM_MARC_LEN_HI_0 955095c1f7aaSFeifei Xu #define MC_VM_MARC_LEN_HI_0__MARC_LEN_HI_0__SHIFT 0x0 955195c1f7aaSFeifei Xu #define MC_VM_MARC_LEN_HI_0__MARC_LEN_HI_0_MASK 0x000FFFFFL 955295c1f7aaSFeifei Xu //MC_VM_MARC_LEN_HI_1 955395c1f7aaSFeifei Xu #define MC_VM_MARC_LEN_HI_1__MARC_LEN_HI_1__SHIFT 0x0 955495c1f7aaSFeifei Xu #define MC_VM_MARC_LEN_HI_1__MARC_LEN_HI_1_MASK 0x000FFFFFL 955595c1f7aaSFeifei Xu //MC_VM_MARC_LEN_HI_2 955695c1f7aaSFeifei Xu #define MC_VM_MARC_LEN_HI_2__MARC_LEN_HI_2__SHIFT 0x0 955795c1f7aaSFeifei Xu #define MC_VM_MARC_LEN_HI_2__MARC_LEN_HI_2_MASK 0x000FFFFFL 955895c1f7aaSFeifei Xu //MC_VM_MARC_LEN_HI_3 955995c1f7aaSFeifei Xu #define MC_VM_MARC_LEN_HI_3__MARC_LEN_HI_3__SHIFT 0x0 956095c1f7aaSFeifei Xu #define MC_VM_MARC_LEN_HI_3__MARC_LEN_HI_3_MASK 0x000FFFFFL 956195c1f7aaSFeifei Xu //VM_IOMMU_CONTROL_REGISTER 956295c1f7aaSFeifei Xu #define VM_IOMMU_CONTROL_REGISTER__IOMMUEN__SHIFT 0x0 956395c1f7aaSFeifei Xu #define VM_IOMMU_CONTROL_REGISTER__IOMMUEN_MASK 0x00000001L 956495c1f7aaSFeifei Xu //VM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER 956595c1f7aaSFeifei Xu #define VM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER__PERFOPTEN__SHIFT 0xd 956695c1f7aaSFeifei Xu #define VM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER__PERFOPTEN_MASK 0x00002000L 956795c1f7aaSFeifei Xu //VM_PCIE_ATS_CNTL 956895c1f7aaSFeifei Xu #define VM_PCIE_ATS_CNTL__STU__SHIFT 0x10 956995c1f7aaSFeifei Xu #define VM_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0x1f 957095c1f7aaSFeifei Xu #define VM_PCIE_ATS_CNTL__STU_MASK 0x001F0000L 957195c1f7aaSFeifei Xu #define VM_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x80000000L 957295c1f7aaSFeifei Xu //VM_PCIE_ATS_CNTL_VF_0 957395c1f7aaSFeifei Xu #define VM_PCIE_ATS_CNTL_VF_0__ATC_ENABLE__SHIFT 0x1f 957495c1f7aaSFeifei Xu #define VM_PCIE_ATS_CNTL_VF_0__ATC_ENABLE_MASK 0x80000000L 957595c1f7aaSFeifei Xu //VM_PCIE_ATS_CNTL_VF_1 957695c1f7aaSFeifei Xu #define VM_PCIE_ATS_CNTL_VF_1__ATC_ENABLE__SHIFT 0x1f 957795c1f7aaSFeifei Xu #define VM_PCIE_ATS_CNTL_VF_1__ATC_ENABLE_MASK 0x80000000L 957895c1f7aaSFeifei Xu //VM_PCIE_ATS_CNTL_VF_2 957995c1f7aaSFeifei Xu #define VM_PCIE_ATS_CNTL_VF_2__ATC_ENABLE__SHIFT 0x1f 958095c1f7aaSFeifei Xu #define VM_PCIE_ATS_CNTL_VF_2__ATC_ENABLE_MASK 0x80000000L 958195c1f7aaSFeifei Xu //VM_PCIE_ATS_CNTL_VF_3 958295c1f7aaSFeifei Xu #define VM_PCIE_ATS_CNTL_VF_3__ATC_ENABLE__SHIFT 0x1f 958395c1f7aaSFeifei Xu #define VM_PCIE_ATS_CNTL_VF_3__ATC_ENABLE_MASK 0x80000000L 958495c1f7aaSFeifei Xu //VM_PCIE_ATS_CNTL_VF_4 958595c1f7aaSFeifei Xu #define VM_PCIE_ATS_CNTL_VF_4__ATC_ENABLE__SHIFT 0x1f 958695c1f7aaSFeifei Xu #define VM_PCIE_ATS_CNTL_VF_4__ATC_ENABLE_MASK 0x80000000L 958795c1f7aaSFeifei Xu //VM_PCIE_ATS_CNTL_VF_5 958895c1f7aaSFeifei Xu #define VM_PCIE_ATS_CNTL_VF_5__ATC_ENABLE__SHIFT 0x1f 958995c1f7aaSFeifei Xu #define VM_PCIE_ATS_CNTL_VF_5__ATC_ENABLE_MASK 0x80000000L 959095c1f7aaSFeifei Xu //VM_PCIE_ATS_CNTL_VF_6 959195c1f7aaSFeifei Xu #define VM_PCIE_ATS_CNTL_VF_6__ATC_ENABLE__SHIFT 0x1f 959295c1f7aaSFeifei Xu #define VM_PCIE_ATS_CNTL_VF_6__ATC_ENABLE_MASK 0x80000000L 959395c1f7aaSFeifei Xu //VM_PCIE_ATS_CNTL_VF_7 959495c1f7aaSFeifei Xu #define VM_PCIE_ATS_CNTL_VF_7__ATC_ENABLE__SHIFT 0x1f 959595c1f7aaSFeifei Xu #define VM_PCIE_ATS_CNTL_VF_7__ATC_ENABLE_MASK 0x80000000L 959695c1f7aaSFeifei Xu //VM_PCIE_ATS_CNTL_VF_8 959795c1f7aaSFeifei Xu #define VM_PCIE_ATS_CNTL_VF_8__ATC_ENABLE__SHIFT 0x1f 959895c1f7aaSFeifei Xu #define VM_PCIE_ATS_CNTL_VF_8__ATC_ENABLE_MASK 0x80000000L 959995c1f7aaSFeifei Xu //VM_PCIE_ATS_CNTL_VF_9 960095c1f7aaSFeifei Xu #define VM_PCIE_ATS_CNTL_VF_9__ATC_ENABLE__SHIFT 0x1f 960195c1f7aaSFeifei Xu #define VM_PCIE_ATS_CNTL_VF_9__ATC_ENABLE_MASK 0x80000000L 960295c1f7aaSFeifei Xu //VM_PCIE_ATS_CNTL_VF_10 960395c1f7aaSFeifei Xu #define VM_PCIE_ATS_CNTL_VF_10__ATC_ENABLE__SHIFT 0x1f 960495c1f7aaSFeifei Xu #define VM_PCIE_ATS_CNTL_VF_10__ATC_ENABLE_MASK 0x80000000L 960595c1f7aaSFeifei Xu //VM_PCIE_ATS_CNTL_VF_11 960695c1f7aaSFeifei Xu #define VM_PCIE_ATS_CNTL_VF_11__ATC_ENABLE__SHIFT 0x1f 960795c1f7aaSFeifei Xu #define VM_PCIE_ATS_CNTL_VF_11__ATC_ENABLE_MASK 0x80000000L 960895c1f7aaSFeifei Xu //VM_PCIE_ATS_CNTL_VF_12 960995c1f7aaSFeifei Xu #define VM_PCIE_ATS_CNTL_VF_12__ATC_ENABLE__SHIFT 0x1f 961095c1f7aaSFeifei Xu #define VM_PCIE_ATS_CNTL_VF_12__ATC_ENABLE_MASK 0x80000000L 961195c1f7aaSFeifei Xu //VM_PCIE_ATS_CNTL_VF_13 961295c1f7aaSFeifei Xu #define VM_PCIE_ATS_CNTL_VF_13__ATC_ENABLE__SHIFT 0x1f 961395c1f7aaSFeifei Xu #define VM_PCIE_ATS_CNTL_VF_13__ATC_ENABLE_MASK 0x80000000L 961495c1f7aaSFeifei Xu //VM_PCIE_ATS_CNTL_VF_14 961595c1f7aaSFeifei Xu #define VM_PCIE_ATS_CNTL_VF_14__ATC_ENABLE__SHIFT 0x1f 961695c1f7aaSFeifei Xu #define VM_PCIE_ATS_CNTL_VF_14__ATC_ENABLE_MASK 0x80000000L 961795c1f7aaSFeifei Xu //VM_PCIE_ATS_CNTL_VF_15 961895c1f7aaSFeifei Xu #define VM_PCIE_ATS_CNTL_VF_15__ATC_ENABLE__SHIFT 0x1f 961995c1f7aaSFeifei Xu #define VM_PCIE_ATS_CNTL_VF_15__ATC_ENABLE_MASK 0x80000000L 962095c1f7aaSFeifei Xu //UTCL2_CGTT_CLK_CTRL 962195c1f7aaSFeifei Xu #define UTCL2_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 962295c1f7aaSFeifei Xu #define UTCL2_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 962395c1f7aaSFeifei Xu #define UTCL2_CGTT_CLK_CTRL__SOFT_OVERRIDE_EXTRA__SHIFT 0xc 962495c1f7aaSFeifei Xu #define UTCL2_CGTT_CLK_CTRL__MGLS_OVERRIDE__SHIFT 0xf 962595c1f7aaSFeifei Xu #define UTCL2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x10 962695c1f7aaSFeifei Xu #define UTCL2_CGTT_CLK_CTRL__SOFT_OVERRIDE__SHIFT 0x18 962795c1f7aaSFeifei Xu #define UTCL2_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL 962895c1f7aaSFeifei Xu #define UTCL2_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L 962995c1f7aaSFeifei Xu #define UTCL2_CGTT_CLK_CTRL__SOFT_OVERRIDE_EXTRA_MASK 0x00007000L 963095c1f7aaSFeifei Xu #define UTCL2_CGTT_CLK_CTRL__MGLS_OVERRIDE_MASK 0x00008000L 963195c1f7aaSFeifei Xu #define UTCL2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00FF0000L 963295c1f7aaSFeifei Xu #define UTCL2_CGTT_CLK_CTRL__SOFT_OVERRIDE_MASK 0xFF000000L 963395c1f7aaSFeifei Xu 963495c1f7aaSFeifei Xu 963595c1f7aaSFeifei Xu // addressBlock: mmhub_utcl2_vmsharedpfdec 963695c1f7aaSFeifei Xu //MC_VM_NB_MMIOBASE 963795c1f7aaSFeifei Xu #define MC_VM_NB_MMIOBASE__MMIOBASE__SHIFT 0x0 963895c1f7aaSFeifei Xu #define MC_VM_NB_MMIOBASE__MMIOBASE_MASK 0xFFFFFFFFL 963995c1f7aaSFeifei Xu //MC_VM_NB_MMIOLIMIT 964095c1f7aaSFeifei Xu #define MC_VM_NB_MMIOLIMIT__MMIOLIMIT__SHIFT 0x0 964195c1f7aaSFeifei Xu #define MC_VM_NB_MMIOLIMIT__MMIOLIMIT_MASK 0xFFFFFFFFL 964295c1f7aaSFeifei Xu //MC_VM_NB_PCI_CTRL 964395c1f7aaSFeifei Xu #define MC_VM_NB_PCI_CTRL__MMIOENABLE__SHIFT 0x17 964495c1f7aaSFeifei Xu #define MC_VM_NB_PCI_CTRL__MMIOENABLE_MASK 0x00800000L 964595c1f7aaSFeifei Xu //MC_VM_NB_PCI_ARB 964695c1f7aaSFeifei Xu #define MC_VM_NB_PCI_ARB__VGA_HOLE__SHIFT 0x3 964795c1f7aaSFeifei Xu #define MC_VM_NB_PCI_ARB__VGA_HOLE_MASK 0x00000008L 964895c1f7aaSFeifei Xu //MC_VM_NB_TOP_OF_DRAM_SLOT1 964995c1f7aaSFeifei Xu #define MC_VM_NB_TOP_OF_DRAM_SLOT1__TOP_OF_DRAM__SHIFT 0x17 965095c1f7aaSFeifei Xu #define MC_VM_NB_TOP_OF_DRAM_SLOT1__TOP_OF_DRAM_MASK 0xFF800000L 965195c1f7aaSFeifei Xu //MC_VM_NB_LOWER_TOP_OF_DRAM2 965295c1f7aaSFeifei Xu #define MC_VM_NB_LOWER_TOP_OF_DRAM2__ENABLE__SHIFT 0x0 965395c1f7aaSFeifei Xu #define MC_VM_NB_LOWER_TOP_OF_DRAM2__LOWER_TOM2__SHIFT 0x17 965495c1f7aaSFeifei Xu #define MC_VM_NB_LOWER_TOP_OF_DRAM2__ENABLE_MASK 0x00000001L 965595c1f7aaSFeifei Xu #define MC_VM_NB_LOWER_TOP_OF_DRAM2__LOWER_TOM2_MASK 0xFF800000L 965695c1f7aaSFeifei Xu //MC_VM_NB_UPPER_TOP_OF_DRAM2 965795c1f7aaSFeifei Xu #define MC_VM_NB_UPPER_TOP_OF_DRAM2__UPPER_TOM2__SHIFT 0x0 965895c1f7aaSFeifei Xu #define MC_VM_NB_UPPER_TOP_OF_DRAM2__UPPER_TOM2_MASK 0x00000FFFL 965995c1f7aaSFeifei Xu //MC_VM_FB_OFFSET 966095c1f7aaSFeifei Xu #define MC_VM_FB_OFFSET__FB_OFFSET__SHIFT 0x0 966195c1f7aaSFeifei Xu #define MC_VM_FB_OFFSET__FB_OFFSET_MASK 0x00FFFFFFL 966295c1f7aaSFeifei Xu //MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB 966395c1f7aaSFeifei Xu #define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB__PHYSICAL_PAGE_NUMBER_LSB__SHIFT 0x0 966495c1f7aaSFeifei Xu #define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB__PHYSICAL_PAGE_NUMBER_LSB_MASK 0xFFFFFFFFL 966595c1f7aaSFeifei Xu //MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB 966695c1f7aaSFeifei Xu #define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__PHYSICAL_PAGE_NUMBER_MSB__SHIFT 0x0 966795c1f7aaSFeifei Xu #define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__PHYSICAL_PAGE_NUMBER_MSB_MASK 0x0000000FL 966895c1f7aaSFeifei Xu //MC_VM_STEERING 966995c1f7aaSFeifei Xu #define MC_VM_STEERING__DEFAULT_STEERING__SHIFT 0x0 967095c1f7aaSFeifei Xu #define MC_VM_STEERING__DEFAULT_STEERING_MASK 0x00000003L 967195c1f7aaSFeifei Xu //MC_SHARED_VIRT_RESET_REQ 967295c1f7aaSFeifei Xu #define MC_SHARED_VIRT_RESET_REQ__VF__SHIFT 0x0 967395c1f7aaSFeifei Xu #define MC_SHARED_VIRT_RESET_REQ__PF__SHIFT 0x1f 967495c1f7aaSFeifei Xu #define MC_SHARED_VIRT_RESET_REQ__VF_MASK 0x0000FFFFL 967595c1f7aaSFeifei Xu #define MC_SHARED_VIRT_RESET_REQ__PF_MASK 0x80000000L 967695c1f7aaSFeifei Xu //MC_MEM_POWER_LS 967795c1f7aaSFeifei Xu #define MC_MEM_POWER_LS__LS_SETUP__SHIFT 0x0 967895c1f7aaSFeifei Xu #define MC_MEM_POWER_LS__LS_HOLD__SHIFT 0x6 967995c1f7aaSFeifei Xu #define MC_MEM_POWER_LS__LS_SETUP_MASK 0x0000003FL 968095c1f7aaSFeifei Xu #define MC_MEM_POWER_LS__LS_HOLD_MASK 0x00000FC0L 968195c1f7aaSFeifei Xu //MC_VM_CACHEABLE_DRAM_ADDRESS_START 968295c1f7aaSFeifei Xu #define MC_VM_CACHEABLE_DRAM_ADDRESS_START__ADDRESS__SHIFT 0x0 968395c1f7aaSFeifei Xu #define MC_VM_CACHEABLE_DRAM_ADDRESS_START__ADDRESS_MASK 0x000FFFFFL 968495c1f7aaSFeifei Xu //MC_VM_CACHEABLE_DRAM_ADDRESS_END 968595c1f7aaSFeifei Xu #define MC_VM_CACHEABLE_DRAM_ADDRESS_END__ADDRESS__SHIFT 0x0 968695c1f7aaSFeifei Xu #define MC_VM_CACHEABLE_DRAM_ADDRESS_END__ADDRESS_MASK 0x000FFFFFL 968795c1f7aaSFeifei Xu //MC_VM_APT_CNTL 968895c1f7aaSFeifei Xu #define MC_VM_APT_CNTL__FORCE_MTYPE_UC__SHIFT 0x0 968995c1f7aaSFeifei Xu #define MC_VM_APT_CNTL__DIRECT_SYSTEM_EN__SHIFT 0x1 969095c1f7aaSFeifei Xu #define MC_VM_APT_CNTL__FORCE_MTYPE_UC_MASK 0x00000001L 969195c1f7aaSFeifei Xu #define MC_VM_APT_CNTL__DIRECT_SYSTEM_EN_MASK 0x00000002L 969295c1f7aaSFeifei Xu //MC_VM_LOCAL_HBM_ADDRESS_START 969395c1f7aaSFeifei Xu #define MC_VM_LOCAL_HBM_ADDRESS_START__ADDRESS__SHIFT 0x0 969495c1f7aaSFeifei Xu #define MC_VM_LOCAL_HBM_ADDRESS_START__ADDRESS_MASK 0x000FFFFFL 969595c1f7aaSFeifei Xu //MC_VM_LOCAL_HBM_ADDRESS_END 969695c1f7aaSFeifei Xu #define MC_VM_LOCAL_HBM_ADDRESS_END__ADDRESS__SHIFT 0x0 969795c1f7aaSFeifei Xu #define MC_VM_LOCAL_HBM_ADDRESS_END__ADDRESS_MASK 0x000FFFFFL 969895c1f7aaSFeifei Xu //MC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL 969995c1f7aaSFeifei Xu #define MC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL__LOCK__SHIFT 0x0 970095c1f7aaSFeifei Xu #define MC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL__LOCK_MASK 0x00000001L 970195c1f7aaSFeifei Xu 970295c1f7aaSFeifei Xu 970395c1f7aaSFeifei Xu // addressBlock: mmhub_utcl2_vmsharedvcdec 970495c1f7aaSFeifei Xu //MC_VM_FB_LOCATION_BASE 970595c1f7aaSFeifei Xu #define MC_VM_FB_LOCATION_BASE__FB_BASE__SHIFT 0x0 970695c1f7aaSFeifei Xu #define MC_VM_FB_LOCATION_BASE__FB_BASE_MASK 0x00FFFFFFL 970795c1f7aaSFeifei Xu //MC_VM_FB_LOCATION_TOP 970895c1f7aaSFeifei Xu #define MC_VM_FB_LOCATION_TOP__FB_TOP__SHIFT 0x0 970995c1f7aaSFeifei Xu #define MC_VM_FB_LOCATION_TOP__FB_TOP_MASK 0x00FFFFFFL 971095c1f7aaSFeifei Xu //MC_VM_AGP_TOP 971195c1f7aaSFeifei Xu #define MC_VM_AGP_TOP__AGP_TOP__SHIFT 0x0 971295c1f7aaSFeifei Xu #define MC_VM_AGP_TOP__AGP_TOP_MASK 0x00FFFFFFL 971395c1f7aaSFeifei Xu //MC_VM_AGP_BOT 971495c1f7aaSFeifei Xu #define MC_VM_AGP_BOT__AGP_BOT__SHIFT 0x0 971595c1f7aaSFeifei Xu #define MC_VM_AGP_BOT__AGP_BOT_MASK 0x00FFFFFFL 971695c1f7aaSFeifei Xu //MC_VM_AGP_BASE 971795c1f7aaSFeifei Xu #define MC_VM_AGP_BASE__AGP_BASE__SHIFT 0x0 971895c1f7aaSFeifei Xu #define MC_VM_AGP_BASE__AGP_BASE_MASK 0x00FFFFFFL 971995c1f7aaSFeifei Xu //MC_VM_SYSTEM_APERTURE_LOW_ADDR 972095c1f7aaSFeifei Xu #define MC_VM_SYSTEM_APERTURE_LOW_ADDR__LOGICAL_ADDR__SHIFT 0x0 972195c1f7aaSFeifei Xu #define MC_VM_SYSTEM_APERTURE_LOW_ADDR__LOGICAL_ADDR_MASK 0x3FFFFFFFL 972295c1f7aaSFeifei Xu //MC_VM_SYSTEM_APERTURE_HIGH_ADDR 972395c1f7aaSFeifei Xu #define MC_VM_SYSTEM_APERTURE_HIGH_ADDR__LOGICAL_ADDR__SHIFT 0x0 972495c1f7aaSFeifei Xu #define MC_VM_SYSTEM_APERTURE_HIGH_ADDR__LOGICAL_ADDR_MASK 0x3FFFFFFFL 972595c1f7aaSFeifei Xu //MC_VM_MX_L1_TLB_CNTL 972695c1f7aaSFeifei Xu #define MC_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB__SHIFT 0x0 972795c1f7aaSFeifei Xu #define MC_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE__SHIFT 0x3 972895c1f7aaSFeifei Xu #define MC_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS__SHIFT 0x5 972995c1f7aaSFeifei Xu #define MC_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL__SHIFT 0x6 973095c1f7aaSFeifei Xu #define MC_VM_MX_L1_TLB_CNTL__ECO_BITS__SHIFT 0x7 973195c1f7aaSFeifei Xu #define MC_VM_MX_L1_TLB_CNTL__MTYPE__SHIFT 0xb 973295c1f7aaSFeifei Xu #define MC_VM_MX_L1_TLB_CNTL__ATC_EN__SHIFT 0xd 973395c1f7aaSFeifei Xu #define MC_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB_MASK 0x00000001L 973495c1f7aaSFeifei Xu #define MC_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE_MASK 0x00000018L 973595c1f7aaSFeifei Xu #define MC_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS_MASK 0x00000020L 973695c1f7aaSFeifei Xu #define MC_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL_MASK 0x00000040L 973795c1f7aaSFeifei Xu #define MC_VM_MX_L1_TLB_CNTL__ECO_BITS_MASK 0x00000780L 973895c1f7aaSFeifei Xu #define MC_VM_MX_L1_TLB_CNTL__MTYPE_MASK 0x00001800L 973995c1f7aaSFeifei Xu #define MC_VM_MX_L1_TLB_CNTL__ATC_EN_MASK 0x00002000L 974095c1f7aaSFeifei Xu 974195c1f7aaSFeifei Xu 974295c1f7aaSFeifei Xu // addressBlock: mmhub_utcl2_atcl2pfcntrdec 974395c1f7aaSFeifei Xu //ATC_L2_PERFCOUNTER_LO 974495c1f7aaSFeifei Xu #define ATC_L2_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 974595c1f7aaSFeifei Xu #define ATC_L2_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL 974695c1f7aaSFeifei Xu //ATC_L2_PERFCOUNTER_HI 974795c1f7aaSFeifei Xu #define ATC_L2_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 974895c1f7aaSFeifei Xu #define ATC_L2_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 974995c1f7aaSFeifei Xu #define ATC_L2_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL 975095c1f7aaSFeifei Xu #define ATC_L2_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L 975195c1f7aaSFeifei Xu 975295c1f7aaSFeifei Xu 975395c1f7aaSFeifei Xu // addressBlock: mmhub_utcl2_atcl2pfcntldec 975495c1f7aaSFeifei Xu //ATC_L2_PERFCOUNTER0_CFG 975595c1f7aaSFeifei Xu #define ATC_L2_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 975695c1f7aaSFeifei Xu #define ATC_L2_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 975795c1f7aaSFeifei Xu #define ATC_L2_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 975895c1f7aaSFeifei Xu #define ATC_L2_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c 975995c1f7aaSFeifei Xu #define ATC_L2_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d 976095c1f7aaSFeifei Xu #define ATC_L2_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL 976195c1f7aaSFeifei Xu #define ATC_L2_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L 976295c1f7aaSFeifei Xu #define ATC_L2_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L 976395c1f7aaSFeifei Xu #define ATC_L2_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L 976495c1f7aaSFeifei Xu #define ATC_L2_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L 976595c1f7aaSFeifei Xu //ATC_L2_PERFCOUNTER1_CFG 976695c1f7aaSFeifei Xu #define ATC_L2_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 976795c1f7aaSFeifei Xu #define ATC_L2_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 976895c1f7aaSFeifei Xu #define ATC_L2_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 976995c1f7aaSFeifei Xu #define ATC_L2_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c 977095c1f7aaSFeifei Xu #define ATC_L2_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d 977195c1f7aaSFeifei Xu #define ATC_L2_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL 977295c1f7aaSFeifei Xu #define ATC_L2_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L 977395c1f7aaSFeifei Xu #define ATC_L2_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L 977495c1f7aaSFeifei Xu #define ATC_L2_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L 977595c1f7aaSFeifei Xu #define ATC_L2_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L 977695c1f7aaSFeifei Xu //ATC_L2_PERFCOUNTER_RSLT_CNTL 977795c1f7aaSFeifei Xu #define ATC_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 977895c1f7aaSFeifei Xu #define ATC_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 977995c1f7aaSFeifei Xu #define ATC_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 978095c1f7aaSFeifei Xu #define ATC_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 978195c1f7aaSFeifei Xu #define ATC_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 978295c1f7aaSFeifei Xu #define ATC_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a 978395c1f7aaSFeifei Xu #define ATC_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL 978495c1f7aaSFeifei Xu #define ATC_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L 978595c1f7aaSFeifei Xu #define ATC_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L 978695c1f7aaSFeifei Xu #define ATC_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L 978795c1f7aaSFeifei Xu #define ATC_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L 978895c1f7aaSFeifei Xu #define ATC_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L 978995c1f7aaSFeifei Xu 979095c1f7aaSFeifei Xu #endif 9791