1 /* 2 * Copyright 2021 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #ifndef _mmhub_3_0_0_SH_MASK_HEADER 24 #define _mmhub_3_0_0_SH_MASK_HEADER 25 26 27 // addressBlock: mmhub_dagbdec 28 //DAGB0_RDCLI0 29 #define DAGB0_RDCLI0__VIRT_CHAN__SHIFT 0x0 30 #define DAGB0_RDCLI0__CHECK_TLB_CREDIT__SHIFT 0x3 31 #define DAGB0_RDCLI0__URG_HIGH__SHIFT 0x4 32 #define DAGB0_RDCLI0__URG_LOW__SHIFT 0x8 33 #define DAGB0_RDCLI0__MAX_BW_ENABLE__SHIFT 0xc 34 #define DAGB0_RDCLI0__MAX_BW__SHIFT 0xd 35 #define DAGB0_RDCLI0__MIN_BW_ENABLE__SHIFT 0x15 36 #define DAGB0_RDCLI0__MIN_BW__SHIFT 0x16 37 #define DAGB0_RDCLI0__OSD_LIMITER_ENABLE__SHIFT 0x19 38 #define DAGB0_RDCLI0__MAX_OSD__SHIFT 0x1a 39 #define DAGB0_RDCLI0__VIRT_CHAN_MASK 0x00000007L 40 #define DAGB0_RDCLI0__CHECK_TLB_CREDIT_MASK 0x00000008L 41 #define DAGB0_RDCLI0__URG_HIGH_MASK 0x000000F0L 42 #define DAGB0_RDCLI0__URG_LOW_MASK 0x00000F00L 43 #define DAGB0_RDCLI0__MAX_BW_ENABLE_MASK 0x00001000L 44 #define DAGB0_RDCLI0__MAX_BW_MASK 0x001FE000L 45 #define DAGB0_RDCLI0__MIN_BW_ENABLE_MASK 0x00200000L 46 #define DAGB0_RDCLI0__MIN_BW_MASK 0x01C00000L 47 #define DAGB0_RDCLI0__OSD_LIMITER_ENABLE_MASK 0x02000000L 48 #define DAGB0_RDCLI0__MAX_OSD_MASK 0xFC000000L 49 //DAGB0_RDCLI1 50 #define DAGB0_RDCLI1__VIRT_CHAN__SHIFT 0x0 51 #define DAGB0_RDCLI1__CHECK_TLB_CREDIT__SHIFT 0x3 52 #define DAGB0_RDCLI1__URG_HIGH__SHIFT 0x4 53 #define DAGB0_RDCLI1__URG_LOW__SHIFT 0x8 54 #define DAGB0_RDCLI1__MAX_BW_ENABLE__SHIFT 0xc 55 #define DAGB0_RDCLI1__MAX_BW__SHIFT 0xd 56 #define DAGB0_RDCLI1__MIN_BW_ENABLE__SHIFT 0x15 57 #define DAGB0_RDCLI1__MIN_BW__SHIFT 0x16 58 #define DAGB0_RDCLI1__OSD_LIMITER_ENABLE__SHIFT 0x19 59 #define DAGB0_RDCLI1__MAX_OSD__SHIFT 0x1a 60 #define DAGB0_RDCLI1__VIRT_CHAN_MASK 0x00000007L 61 #define DAGB0_RDCLI1__CHECK_TLB_CREDIT_MASK 0x00000008L 62 #define DAGB0_RDCLI1__URG_HIGH_MASK 0x000000F0L 63 #define DAGB0_RDCLI1__URG_LOW_MASK 0x00000F00L 64 #define DAGB0_RDCLI1__MAX_BW_ENABLE_MASK 0x00001000L 65 #define DAGB0_RDCLI1__MAX_BW_MASK 0x001FE000L 66 #define DAGB0_RDCLI1__MIN_BW_ENABLE_MASK 0x00200000L 67 #define DAGB0_RDCLI1__MIN_BW_MASK 0x01C00000L 68 #define DAGB0_RDCLI1__OSD_LIMITER_ENABLE_MASK 0x02000000L 69 #define DAGB0_RDCLI1__MAX_OSD_MASK 0xFC000000L 70 //DAGB0_RDCLI2 71 #define DAGB0_RDCLI2__VIRT_CHAN__SHIFT 0x0 72 #define DAGB0_RDCLI2__CHECK_TLB_CREDIT__SHIFT 0x3 73 #define DAGB0_RDCLI2__URG_HIGH__SHIFT 0x4 74 #define DAGB0_RDCLI2__URG_LOW__SHIFT 0x8 75 #define DAGB0_RDCLI2__MAX_BW_ENABLE__SHIFT 0xc 76 #define DAGB0_RDCLI2__MAX_BW__SHIFT 0xd 77 #define DAGB0_RDCLI2__MIN_BW_ENABLE__SHIFT 0x15 78 #define DAGB0_RDCLI2__MIN_BW__SHIFT 0x16 79 #define DAGB0_RDCLI2__OSD_LIMITER_ENABLE__SHIFT 0x19 80 #define DAGB0_RDCLI2__MAX_OSD__SHIFT 0x1a 81 #define DAGB0_RDCLI2__VIRT_CHAN_MASK 0x00000007L 82 #define DAGB0_RDCLI2__CHECK_TLB_CREDIT_MASK 0x00000008L 83 #define DAGB0_RDCLI2__URG_HIGH_MASK 0x000000F0L 84 #define DAGB0_RDCLI2__URG_LOW_MASK 0x00000F00L 85 #define DAGB0_RDCLI2__MAX_BW_ENABLE_MASK 0x00001000L 86 #define DAGB0_RDCLI2__MAX_BW_MASK 0x001FE000L 87 #define DAGB0_RDCLI2__MIN_BW_ENABLE_MASK 0x00200000L 88 #define DAGB0_RDCLI2__MIN_BW_MASK 0x01C00000L 89 #define DAGB0_RDCLI2__OSD_LIMITER_ENABLE_MASK 0x02000000L 90 #define DAGB0_RDCLI2__MAX_OSD_MASK 0xFC000000L 91 //DAGB0_RDCLI3 92 #define DAGB0_RDCLI3__VIRT_CHAN__SHIFT 0x0 93 #define DAGB0_RDCLI3__CHECK_TLB_CREDIT__SHIFT 0x3 94 #define DAGB0_RDCLI3__URG_HIGH__SHIFT 0x4 95 #define DAGB0_RDCLI3__URG_LOW__SHIFT 0x8 96 #define DAGB0_RDCLI3__MAX_BW_ENABLE__SHIFT 0xc 97 #define DAGB0_RDCLI3__MAX_BW__SHIFT 0xd 98 #define DAGB0_RDCLI3__MIN_BW_ENABLE__SHIFT 0x15 99 #define DAGB0_RDCLI3__MIN_BW__SHIFT 0x16 100 #define DAGB0_RDCLI3__OSD_LIMITER_ENABLE__SHIFT 0x19 101 #define DAGB0_RDCLI3__MAX_OSD__SHIFT 0x1a 102 #define DAGB0_RDCLI3__VIRT_CHAN_MASK 0x00000007L 103 #define DAGB0_RDCLI3__CHECK_TLB_CREDIT_MASK 0x00000008L 104 #define DAGB0_RDCLI3__URG_HIGH_MASK 0x000000F0L 105 #define DAGB0_RDCLI3__URG_LOW_MASK 0x00000F00L 106 #define DAGB0_RDCLI3__MAX_BW_ENABLE_MASK 0x00001000L 107 #define DAGB0_RDCLI3__MAX_BW_MASK 0x001FE000L 108 #define DAGB0_RDCLI3__MIN_BW_ENABLE_MASK 0x00200000L 109 #define DAGB0_RDCLI3__MIN_BW_MASK 0x01C00000L 110 #define DAGB0_RDCLI3__OSD_LIMITER_ENABLE_MASK 0x02000000L 111 #define DAGB0_RDCLI3__MAX_OSD_MASK 0xFC000000L 112 //DAGB0_RDCLI4 113 #define DAGB0_RDCLI4__VIRT_CHAN__SHIFT 0x0 114 #define DAGB0_RDCLI4__CHECK_TLB_CREDIT__SHIFT 0x3 115 #define DAGB0_RDCLI4__URG_HIGH__SHIFT 0x4 116 #define DAGB0_RDCLI4__URG_LOW__SHIFT 0x8 117 #define DAGB0_RDCLI4__MAX_BW_ENABLE__SHIFT 0xc 118 #define DAGB0_RDCLI4__MAX_BW__SHIFT 0xd 119 #define DAGB0_RDCLI4__MIN_BW_ENABLE__SHIFT 0x15 120 #define DAGB0_RDCLI4__MIN_BW__SHIFT 0x16 121 #define DAGB0_RDCLI4__OSD_LIMITER_ENABLE__SHIFT 0x19 122 #define DAGB0_RDCLI4__MAX_OSD__SHIFT 0x1a 123 #define DAGB0_RDCLI4__VIRT_CHAN_MASK 0x00000007L 124 #define DAGB0_RDCLI4__CHECK_TLB_CREDIT_MASK 0x00000008L 125 #define DAGB0_RDCLI4__URG_HIGH_MASK 0x000000F0L 126 #define DAGB0_RDCLI4__URG_LOW_MASK 0x00000F00L 127 #define DAGB0_RDCLI4__MAX_BW_ENABLE_MASK 0x00001000L 128 #define DAGB0_RDCLI4__MAX_BW_MASK 0x001FE000L 129 #define DAGB0_RDCLI4__MIN_BW_ENABLE_MASK 0x00200000L 130 #define DAGB0_RDCLI4__MIN_BW_MASK 0x01C00000L 131 #define DAGB0_RDCLI4__OSD_LIMITER_ENABLE_MASK 0x02000000L 132 #define DAGB0_RDCLI4__MAX_OSD_MASK 0xFC000000L 133 //DAGB0_RDCLI5 134 #define DAGB0_RDCLI5__VIRT_CHAN__SHIFT 0x0 135 #define DAGB0_RDCLI5__CHECK_TLB_CREDIT__SHIFT 0x3 136 #define DAGB0_RDCLI5__URG_HIGH__SHIFT 0x4 137 #define DAGB0_RDCLI5__URG_LOW__SHIFT 0x8 138 #define DAGB0_RDCLI5__MAX_BW_ENABLE__SHIFT 0xc 139 #define DAGB0_RDCLI5__MAX_BW__SHIFT 0xd 140 #define DAGB0_RDCLI5__MIN_BW_ENABLE__SHIFT 0x15 141 #define DAGB0_RDCLI5__MIN_BW__SHIFT 0x16 142 #define DAGB0_RDCLI5__OSD_LIMITER_ENABLE__SHIFT 0x19 143 #define DAGB0_RDCLI5__MAX_OSD__SHIFT 0x1a 144 #define DAGB0_RDCLI5__VIRT_CHAN_MASK 0x00000007L 145 #define DAGB0_RDCLI5__CHECK_TLB_CREDIT_MASK 0x00000008L 146 #define DAGB0_RDCLI5__URG_HIGH_MASK 0x000000F0L 147 #define DAGB0_RDCLI5__URG_LOW_MASK 0x00000F00L 148 #define DAGB0_RDCLI5__MAX_BW_ENABLE_MASK 0x00001000L 149 #define DAGB0_RDCLI5__MAX_BW_MASK 0x001FE000L 150 #define DAGB0_RDCLI5__MIN_BW_ENABLE_MASK 0x00200000L 151 #define DAGB0_RDCLI5__MIN_BW_MASK 0x01C00000L 152 #define DAGB0_RDCLI5__OSD_LIMITER_ENABLE_MASK 0x02000000L 153 #define DAGB0_RDCLI5__MAX_OSD_MASK 0xFC000000L 154 //DAGB0_RDCLI6 155 #define DAGB0_RDCLI6__VIRT_CHAN__SHIFT 0x0 156 #define DAGB0_RDCLI6__CHECK_TLB_CREDIT__SHIFT 0x3 157 #define DAGB0_RDCLI6__URG_HIGH__SHIFT 0x4 158 #define DAGB0_RDCLI6__URG_LOW__SHIFT 0x8 159 #define DAGB0_RDCLI6__MAX_BW_ENABLE__SHIFT 0xc 160 #define DAGB0_RDCLI6__MAX_BW__SHIFT 0xd 161 #define DAGB0_RDCLI6__MIN_BW_ENABLE__SHIFT 0x15 162 #define DAGB0_RDCLI6__MIN_BW__SHIFT 0x16 163 #define DAGB0_RDCLI6__OSD_LIMITER_ENABLE__SHIFT 0x19 164 #define DAGB0_RDCLI6__MAX_OSD__SHIFT 0x1a 165 #define DAGB0_RDCLI6__VIRT_CHAN_MASK 0x00000007L 166 #define DAGB0_RDCLI6__CHECK_TLB_CREDIT_MASK 0x00000008L 167 #define DAGB0_RDCLI6__URG_HIGH_MASK 0x000000F0L 168 #define DAGB0_RDCLI6__URG_LOW_MASK 0x00000F00L 169 #define DAGB0_RDCLI6__MAX_BW_ENABLE_MASK 0x00001000L 170 #define DAGB0_RDCLI6__MAX_BW_MASK 0x001FE000L 171 #define DAGB0_RDCLI6__MIN_BW_ENABLE_MASK 0x00200000L 172 #define DAGB0_RDCLI6__MIN_BW_MASK 0x01C00000L 173 #define DAGB0_RDCLI6__OSD_LIMITER_ENABLE_MASK 0x02000000L 174 #define DAGB0_RDCLI6__MAX_OSD_MASK 0xFC000000L 175 //DAGB0_RDCLI7 176 #define DAGB0_RDCLI7__VIRT_CHAN__SHIFT 0x0 177 #define DAGB0_RDCLI7__CHECK_TLB_CREDIT__SHIFT 0x3 178 #define DAGB0_RDCLI7__URG_HIGH__SHIFT 0x4 179 #define DAGB0_RDCLI7__URG_LOW__SHIFT 0x8 180 #define DAGB0_RDCLI7__MAX_BW_ENABLE__SHIFT 0xc 181 #define DAGB0_RDCLI7__MAX_BW__SHIFT 0xd 182 #define DAGB0_RDCLI7__MIN_BW_ENABLE__SHIFT 0x15 183 #define DAGB0_RDCLI7__MIN_BW__SHIFT 0x16 184 #define DAGB0_RDCLI7__OSD_LIMITER_ENABLE__SHIFT 0x19 185 #define DAGB0_RDCLI7__MAX_OSD__SHIFT 0x1a 186 #define DAGB0_RDCLI7__VIRT_CHAN_MASK 0x00000007L 187 #define DAGB0_RDCLI7__CHECK_TLB_CREDIT_MASK 0x00000008L 188 #define DAGB0_RDCLI7__URG_HIGH_MASK 0x000000F0L 189 #define DAGB0_RDCLI7__URG_LOW_MASK 0x00000F00L 190 #define DAGB0_RDCLI7__MAX_BW_ENABLE_MASK 0x00001000L 191 #define DAGB0_RDCLI7__MAX_BW_MASK 0x001FE000L 192 #define DAGB0_RDCLI7__MIN_BW_ENABLE_MASK 0x00200000L 193 #define DAGB0_RDCLI7__MIN_BW_MASK 0x01C00000L 194 #define DAGB0_RDCLI7__OSD_LIMITER_ENABLE_MASK 0x02000000L 195 #define DAGB0_RDCLI7__MAX_OSD_MASK 0xFC000000L 196 //DAGB0_RDCLI8 197 #define DAGB0_RDCLI8__VIRT_CHAN__SHIFT 0x0 198 #define DAGB0_RDCLI8__CHECK_TLB_CREDIT__SHIFT 0x3 199 #define DAGB0_RDCLI8__URG_HIGH__SHIFT 0x4 200 #define DAGB0_RDCLI8__URG_LOW__SHIFT 0x8 201 #define DAGB0_RDCLI8__MAX_BW_ENABLE__SHIFT 0xc 202 #define DAGB0_RDCLI8__MAX_BW__SHIFT 0xd 203 #define DAGB0_RDCLI8__MIN_BW_ENABLE__SHIFT 0x15 204 #define DAGB0_RDCLI8__MIN_BW__SHIFT 0x16 205 #define DAGB0_RDCLI8__OSD_LIMITER_ENABLE__SHIFT 0x19 206 #define DAGB0_RDCLI8__MAX_OSD__SHIFT 0x1a 207 #define DAGB0_RDCLI8__VIRT_CHAN_MASK 0x00000007L 208 #define DAGB0_RDCLI8__CHECK_TLB_CREDIT_MASK 0x00000008L 209 #define DAGB0_RDCLI8__URG_HIGH_MASK 0x000000F0L 210 #define DAGB0_RDCLI8__URG_LOW_MASK 0x00000F00L 211 #define DAGB0_RDCLI8__MAX_BW_ENABLE_MASK 0x00001000L 212 #define DAGB0_RDCLI8__MAX_BW_MASK 0x001FE000L 213 #define DAGB0_RDCLI8__MIN_BW_ENABLE_MASK 0x00200000L 214 #define DAGB0_RDCLI8__MIN_BW_MASK 0x01C00000L 215 #define DAGB0_RDCLI8__OSD_LIMITER_ENABLE_MASK 0x02000000L 216 #define DAGB0_RDCLI8__MAX_OSD_MASK 0xFC000000L 217 //DAGB0_RDCLI9 218 #define DAGB0_RDCLI9__VIRT_CHAN__SHIFT 0x0 219 #define DAGB0_RDCLI9__CHECK_TLB_CREDIT__SHIFT 0x3 220 #define DAGB0_RDCLI9__URG_HIGH__SHIFT 0x4 221 #define DAGB0_RDCLI9__URG_LOW__SHIFT 0x8 222 #define DAGB0_RDCLI9__MAX_BW_ENABLE__SHIFT 0xc 223 #define DAGB0_RDCLI9__MAX_BW__SHIFT 0xd 224 #define DAGB0_RDCLI9__MIN_BW_ENABLE__SHIFT 0x15 225 #define DAGB0_RDCLI9__MIN_BW__SHIFT 0x16 226 #define DAGB0_RDCLI9__OSD_LIMITER_ENABLE__SHIFT 0x19 227 #define DAGB0_RDCLI9__MAX_OSD__SHIFT 0x1a 228 #define DAGB0_RDCLI9__VIRT_CHAN_MASK 0x00000007L 229 #define DAGB0_RDCLI9__CHECK_TLB_CREDIT_MASK 0x00000008L 230 #define DAGB0_RDCLI9__URG_HIGH_MASK 0x000000F0L 231 #define DAGB0_RDCLI9__URG_LOW_MASK 0x00000F00L 232 #define DAGB0_RDCLI9__MAX_BW_ENABLE_MASK 0x00001000L 233 #define DAGB0_RDCLI9__MAX_BW_MASK 0x001FE000L 234 #define DAGB0_RDCLI9__MIN_BW_ENABLE_MASK 0x00200000L 235 #define DAGB0_RDCLI9__MIN_BW_MASK 0x01C00000L 236 #define DAGB0_RDCLI9__OSD_LIMITER_ENABLE_MASK 0x02000000L 237 #define DAGB0_RDCLI9__MAX_OSD_MASK 0xFC000000L 238 //DAGB0_RDCLI10 239 #define DAGB0_RDCLI10__VIRT_CHAN__SHIFT 0x0 240 #define DAGB0_RDCLI10__CHECK_TLB_CREDIT__SHIFT 0x3 241 #define DAGB0_RDCLI10__URG_HIGH__SHIFT 0x4 242 #define DAGB0_RDCLI10__URG_LOW__SHIFT 0x8 243 #define DAGB0_RDCLI10__MAX_BW_ENABLE__SHIFT 0xc 244 #define DAGB0_RDCLI10__MAX_BW__SHIFT 0xd 245 #define DAGB0_RDCLI10__MIN_BW_ENABLE__SHIFT 0x15 246 #define DAGB0_RDCLI10__MIN_BW__SHIFT 0x16 247 #define DAGB0_RDCLI10__OSD_LIMITER_ENABLE__SHIFT 0x19 248 #define DAGB0_RDCLI10__MAX_OSD__SHIFT 0x1a 249 #define DAGB0_RDCLI10__VIRT_CHAN_MASK 0x00000007L 250 #define DAGB0_RDCLI10__CHECK_TLB_CREDIT_MASK 0x00000008L 251 #define DAGB0_RDCLI10__URG_HIGH_MASK 0x000000F0L 252 #define DAGB0_RDCLI10__URG_LOW_MASK 0x00000F00L 253 #define DAGB0_RDCLI10__MAX_BW_ENABLE_MASK 0x00001000L 254 #define DAGB0_RDCLI10__MAX_BW_MASK 0x001FE000L 255 #define DAGB0_RDCLI10__MIN_BW_ENABLE_MASK 0x00200000L 256 #define DAGB0_RDCLI10__MIN_BW_MASK 0x01C00000L 257 #define DAGB0_RDCLI10__OSD_LIMITER_ENABLE_MASK 0x02000000L 258 #define DAGB0_RDCLI10__MAX_OSD_MASK 0xFC000000L 259 //DAGB0_RDCLI11 260 #define DAGB0_RDCLI11__VIRT_CHAN__SHIFT 0x0 261 #define DAGB0_RDCLI11__CHECK_TLB_CREDIT__SHIFT 0x3 262 #define DAGB0_RDCLI11__URG_HIGH__SHIFT 0x4 263 #define DAGB0_RDCLI11__URG_LOW__SHIFT 0x8 264 #define DAGB0_RDCLI11__MAX_BW_ENABLE__SHIFT 0xc 265 #define DAGB0_RDCLI11__MAX_BW__SHIFT 0xd 266 #define DAGB0_RDCLI11__MIN_BW_ENABLE__SHIFT 0x15 267 #define DAGB0_RDCLI11__MIN_BW__SHIFT 0x16 268 #define DAGB0_RDCLI11__OSD_LIMITER_ENABLE__SHIFT 0x19 269 #define DAGB0_RDCLI11__MAX_OSD__SHIFT 0x1a 270 #define DAGB0_RDCLI11__VIRT_CHAN_MASK 0x00000007L 271 #define DAGB0_RDCLI11__CHECK_TLB_CREDIT_MASK 0x00000008L 272 #define DAGB0_RDCLI11__URG_HIGH_MASK 0x000000F0L 273 #define DAGB0_RDCLI11__URG_LOW_MASK 0x00000F00L 274 #define DAGB0_RDCLI11__MAX_BW_ENABLE_MASK 0x00001000L 275 #define DAGB0_RDCLI11__MAX_BW_MASK 0x001FE000L 276 #define DAGB0_RDCLI11__MIN_BW_ENABLE_MASK 0x00200000L 277 #define DAGB0_RDCLI11__MIN_BW_MASK 0x01C00000L 278 #define DAGB0_RDCLI11__OSD_LIMITER_ENABLE_MASK 0x02000000L 279 #define DAGB0_RDCLI11__MAX_OSD_MASK 0xFC000000L 280 //DAGB0_RDCLI12 281 #define DAGB0_RDCLI12__VIRT_CHAN__SHIFT 0x0 282 #define DAGB0_RDCLI12__CHECK_TLB_CREDIT__SHIFT 0x3 283 #define DAGB0_RDCLI12__URG_HIGH__SHIFT 0x4 284 #define DAGB0_RDCLI12__URG_LOW__SHIFT 0x8 285 #define DAGB0_RDCLI12__MAX_BW_ENABLE__SHIFT 0xc 286 #define DAGB0_RDCLI12__MAX_BW__SHIFT 0xd 287 #define DAGB0_RDCLI12__MIN_BW_ENABLE__SHIFT 0x15 288 #define DAGB0_RDCLI12__MIN_BW__SHIFT 0x16 289 #define DAGB0_RDCLI12__OSD_LIMITER_ENABLE__SHIFT 0x19 290 #define DAGB0_RDCLI12__MAX_OSD__SHIFT 0x1a 291 #define DAGB0_RDCLI12__VIRT_CHAN_MASK 0x00000007L 292 #define DAGB0_RDCLI12__CHECK_TLB_CREDIT_MASK 0x00000008L 293 #define DAGB0_RDCLI12__URG_HIGH_MASK 0x000000F0L 294 #define DAGB0_RDCLI12__URG_LOW_MASK 0x00000F00L 295 #define DAGB0_RDCLI12__MAX_BW_ENABLE_MASK 0x00001000L 296 #define DAGB0_RDCLI12__MAX_BW_MASK 0x001FE000L 297 #define DAGB0_RDCLI12__MIN_BW_ENABLE_MASK 0x00200000L 298 #define DAGB0_RDCLI12__MIN_BW_MASK 0x01C00000L 299 #define DAGB0_RDCLI12__OSD_LIMITER_ENABLE_MASK 0x02000000L 300 #define DAGB0_RDCLI12__MAX_OSD_MASK 0xFC000000L 301 //DAGB0_RDCLI13 302 #define DAGB0_RDCLI13__VIRT_CHAN__SHIFT 0x0 303 #define DAGB0_RDCLI13__CHECK_TLB_CREDIT__SHIFT 0x3 304 #define DAGB0_RDCLI13__URG_HIGH__SHIFT 0x4 305 #define DAGB0_RDCLI13__URG_LOW__SHIFT 0x8 306 #define DAGB0_RDCLI13__MAX_BW_ENABLE__SHIFT 0xc 307 #define DAGB0_RDCLI13__MAX_BW__SHIFT 0xd 308 #define DAGB0_RDCLI13__MIN_BW_ENABLE__SHIFT 0x15 309 #define DAGB0_RDCLI13__MIN_BW__SHIFT 0x16 310 #define DAGB0_RDCLI13__OSD_LIMITER_ENABLE__SHIFT 0x19 311 #define DAGB0_RDCLI13__MAX_OSD__SHIFT 0x1a 312 #define DAGB0_RDCLI13__VIRT_CHAN_MASK 0x00000007L 313 #define DAGB0_RDCLI13__CHECK_TLB_CREDIT_MASK 0x00000008L 314 #define DAGB0_RDCLI13__URG_HIGH_MASK 0x000000F0L 315 #define DAGB0_RDCLI13__URG_LOW_MASK 0x00000F00L 316 #define DAGB0_RDCLI13__MAX_BW_ENABLE_MASK 0x00001000L 317 #define DAGB0_RDCLI13__MAX_BW_MASK 0x001FE000L 318 #define DAGB0_RDCLI13__MIN_BW_ENABLE_MASK 0x00200000L 319 #define DAGB0_RDCLI13__MIN_BW_MASK 0x01C00000L 320 #define DAGB0_RDCLI13__OSD_LIMITER_ENABLE_MASK 0x02000000L 321 #define DAGB0_RDCLI13__MAX_OSD_MASK 0xFC000000L 322 //DAGB0_RDCLI14 323 #define DAGB0_RDCLI14__VIRT_CHAN__SHIFT 0x0 324 #define DAGB0_RDCLI14__CHECK_TLB_CREDIT__SHIFT 0x3 325 #define DAGB0_RDCLI14__URG_HIGH__SHIFT 0x4 326 #define DAGB0_RDCLI14__URG_LOW__SHIFT 0x8 327 #define DAGB0_RDCLI14__MAX_BW_ENABLE__SHIFT 0xc 328 #define DAGB0_RDCLI14__MAX_BW__SHIFT 0xd 329 #define DAGB0_RDCLI14__MIN_BW_ENABLE__SHIFT 0x15 330 #define DAGB0_RDCLI14__MIN_BW__SHIFT 0x16 331 #define DAGB0_RDCLI14__OSD_LIMITER_ENABLE__SHIFT 0x19 332 #define DAGB0_RDCLI14__MAX_OSD__SHIFT 0x1a 333 #define DAGB0_RDCLI14__VIRT_CHAN_MASK 0x00000007L 334 #define DAGB0_RDCLI14__CHECK_TLB_CREDIT_MASK 0x00000008L 335 #define DAGB0_RDCLI14__URG_HIGH_MASK 0x000000F0L 336 #define DAGB0_RDCLI14__URG_LOW_MASK 0x00000F00L 337 #define DAGB0_RDCLI14__MAX_BW_ENABLE_MASK 0x00001000L 338 #define DAGB0_RDCLI14__MAX_BW_MASK 0x001FE000L 339 #define DAGB0_RDCLI14__MIN_BW_ENABLE_MASK 0x00200000L 340 #define DAGB0_RDCLI14__MIN_BW_MASK 0x01C00000L 341 #define DAGB0_RDCLI14__OSD_LIMITER_ENABLE_MASK 0x02000000L 342 #define DAGB0_RDCLI14__MAX_OSD_MASK 0xFC000000L 343 //DAGB0_RDCLI15 344 #define DAGB0_RDCLI15__VIRT_CHAN__SHIFT 0x0 345 #define DAGB0_RDCLI15__CHECK_TLB_CREDIT__SHIFT 0x3 346 #define DAGB0_RDCLI15__URG_HIGH__SHIFT 0x4 347 #define DAGB0_RDCLI15__URG_LOW__SHIFT 0x8 348 #define DAGB0_RDCLI15__MAX_BW_ENABLE__SHIFT 0xc 349 #define DAGB0_RDCLI15__MAX_BW__SHIFT 0xd 350 #define DAGB0_RDCLI15__MIN_BW_ENABLE__SHIFT 0x15 351 #define DAGB0_RDCLI15__MIN_BW__SHIFT 0x16 352 #define DAGB0_RDCLI15__OSD_LIMITER_ENABLE__SHIFT 0x19 353 #define DAGB0_RDCLI15__MAX_OSD__SHIFT 0x1a 354 #define DAGB0_RDCLI15__VIRT_CHAN_MASK 0x00000007L 355 #define DAGB0_RDCLI15__CHECK_TLB_CREDIT_MASK 0x00000008L 356 #define DAGB0_RDCLI15__URG_HIGH_MASK 0x000000F0L 357 #define DAGB0_RDCLI15__URG_LOW_MASK 0x00000F00L 358 #define DAGB0_RDCLI15__MAX_BW_ENABLE_MASK 0x00001000L 359 #define DAGB0_RDCLI15__MAX_BW_MASK 0x001FE000L 360 #define DAGB0_RDCLI15__MIN_BW_ENABLE_MASK 0x00200000L 361 #define DAGB0_RDCLI15__MIN_BW_MASK 0x01C00000L 362 #define DAGB0_RDCLI15__OSD_LIMITER_ENABLE_MASK 0x02000000L 363 #define DAGB0_RDCLI15__MAX_OSD_MASK 0xFC000000L 364 //DAGB0_RDCLI16 365 #define DAGB0_RDCLI16__VIRT_CHAN__SHIFT 0x0 366 #define DAGB0_RDCLI16__CHECK_TLB_CREDIT__SHIFT 0x3 367 #define DAGB0_RDCLI16__URG_HIGH__SHIFT 0x4 368 #define DAGB0_RDCLI16__URG_LOW__SHIFT 0x8 369 #define DAGB0_RDCLI16__MAX_BW_ENABLE__SHIFT 0xc 370 #define DAGB0_RDCLI16__MAX_BW__SHIFT 0xd 371 #define DAGB0_RDCLI16__MIN_BW_ENABLE__SHIFT 0x15 372 #define DAGB0_RDCLI16__MIN_BW__SHIFT 0x16 373 #define DAGB0_RDCLI16__OSD_LIMITER_ENABLE__SHIFT 0x19 374 #define DAGB0_RDCLI16__MAX_OSD__SHIFT 0x1a 375 #define DAGB0_RDCLI16__VIRT_CHAN_MASK 0x00000007L 376 #define DAGB0_RDCLI16__CHECK_TLB_CREDIT_MASK 0x00000008L 377 #define DAGB0_RDCLI16__URG_HIGH_MASK 0x000000F0L 378 #define DAGB0_RDCLI16__URG_LOW_MASK 0x00000F00L 379 #define DAGB0_RDCLI16__MAX_BW_ENABLE_MASK 0x00001000L 380 #define DAGB0_RDCLI16__MAX_BW_MASK 0x001FE000L 381 #define DAGB0_RDCLI16__MIN_BW_ENABLE_MASK 0x00200000L 382 #define DAGB0_RDCLI16__MIN_BW_MASK 0x01C00000L 383 #define DAGB0_RDCLI16__OSD_LIMITER_ENABLE_MASK 0x02000000L 384 #define DAGB0_RDCLI16__MAX_OSD_MASK 0xFC000000L 385 //DAGB0_RDCLI17 386 #define DAGB0_RDCLI17__VIRT_CHAN__SHIFT 0x0 387 #define DAGB0_RDCLI17__CHECK_TLB_CREDIT__SHIFT 0x3 388 #define DAGB0_RDCLI17__URG_HIGH__SHIFT 0x4 389 #define DAGB0_RDCLI17__URG_LOW__SHIFT 0x8 390 #define DAGB0_RDCLI17__MAX_BW_ENABLE__SHIFT 0xc 391 #define DAGB0_RDCLI17__MAX_BW__SHIFT 0xd 392 #define DAGB0_RDCLI17__MIN_BW_ENABLE__SHIFT 0x15 393 #define DAGB0_RDCLI17__MIN_BW__SHIFT 0x16 394 #define DAGB0_RDCLI17__OSD_LIMITER_ENABLE__SHIFT 0x19 395 #define DAGB0_RDCLI17__MAX_OSD__SHIFT 0x1a 396 #define DAGB0_RDCLI17__VIRT_CHAN_MASK 0x00000007L 397 #define DAGB0_RDCLI17__CHECK_TLB_CREDIT_MASK 0x00000008L 398 #define DAGB0_RDCLI17__URG_HIGH_MASK 0x000000F0L 399 #define DAGB0_RDCLI17__URG_LOW_MASK 0x00000F00L 400 #define DAGB0_RDCLI17__MAX_BW_ENABLE_MASK 0x00001000L 401 #define DAGB0_RDCLI17__MAX_BW_MASK 0x001FE000L 402 #define DAGB0_RDCLI17__MIN_BW_ENABLE_MASK 0x00200000L 403 #define DAGB0_RDCLI17__MIN_BW_MASK 0x01C00000L 404 #define DAGB0_RDCLI17__OSD_LIMITER_ENABLE_MASK 0x02000000L 405 #define DAGB0_RDCLI17__MAX_OSD_MASK 0xFC000000L 406 //DAGB0_RDCLI18 407 #define DAGB0_RDCLI18__VIRT_CHAN__SHIFT 0x0 408 #define DAGB0_RDCLI18__CHECK_TLB_CREDIT__SHIFT 0x3 409 #define DAGB0_RDCLI18__URG_HIGH__SHIFT 0x4 410 #define DAGB0_RDCLI18__URG_LOW__SHIFT 0x8 411 #define DAGB0_RDCLI18__MAX_BW_ENABLE__SHIFT 0xc 412 #define DAGB0_RDCLI18__MAX_BW__SHIFT 0xd 413 #define DAGB0_RDCLI18__MIN_BW_ENABLE__SHIFT 0x15 414 #define DAGB0_RDCLI18__MIN_BW__SHIFT 0x16 415 #define DAGB0_RDCLI18__OSD_LIMITER_ENABLE__SHIFT 0x19 416 #define DAGB0_RDCLI18__MAX_OSD__SHIFT 0x1a 417 #define DAGB0_RDCLI18__VIRT_CHAN_MASK 0x00000007L 418 #define DAGB0_RDCLI18__CHECK_TLB_CREDIT_MASK 0x00000008L 419 #define DAGB0_RDCLI18__URG_HIGH_MASK 0x000000F0L 420 #define DAGB0_RDCLI18__URG_LOW_MASK 0x00000F00L 421 #define DAGB0_RDCLI18__MAX_BW_ENABLE_MASK 0x00001000L 422 #define DAGB0_RDCLI18__MAX_BW_MASK 0x001FE000L 423 #define DAGB0_RDCLI18__MIN_BW_ENABLE_MASK 0x00200000L 424 #define DAGB0_RDCLI18__MIN_BW_MASK 0x01C00000L 425 #define DAGB0_RDCLI18__OSD_LIMITER_ENABLE_MASK 0x02000000L 426 #define DAGB0_RDCLI18__MAX_OSD_MASK 0xFC000000L 427 //DAGB0_RDCLI19 428 #define DAGB0_RDCLI19__VIRT_CHAN__SHIFT 0x0 429 #define DAGB0_RDCLI19__CHECK_TLB_CREDIT__SHIFT 0x3 430 #define DAGB0_RDCLI19__URG_HIGH__SHIFT 0x4 431 #define DAGB0_RDCLI19__URG_LOW__SHIFT 0x8 432 #define DAGB0_RDCLI19__MAX_BW_ENABLE__SHIFT 0xc 433 #define DAGB0_RDCLI19__MAX_BW__SHIFT 0xd 434 #define DAGB0_RDCLI19__MIN_BW_ENABLE__SHIFT 0x15 435 #define DAGB0_RDCLI19__MIN_BW__SHIFT 0x16 436 #define DAGB0_RDCLI19__OSD_LIMITER_ENABLE__SHIFT 0x19 437 #define DAGB0_RDCLI19__MAX_OSD__SHIFT 0x1a 438 #define DAGB0_RDCLI19__VIRT_CHAN_MASK 0x00000007L 439 #define DAGB0_RDCLI19__CHECK_TLB_CREDIT_MASK 0x00000008L 440 #define DAGB0_RDCLI19__URG_HIGH_MASK 0x000000F0L 441 #define DAGB0_RDCLI19__URG_LOW_MASK 0x00000F00L 442 #define DAGB0_RDCLI19__MAX_BW_ENABLE_MASK 0x00001000L 443 #define DAGB0_RDCLI19__MAX_BW_MASK 0x001FE000L 444 #define DAGB0_RDCLI19__MIN_BW_ENABLE_MASK 0x00200000L 445 #define DAGB0_RDCLI19__MIN_BW_MASK 0x01C00000L 446 #define DAGB0_RDCLI19__OSD_LIMITER_ENABLE_MASK 0x02000000L 447 #define DAGB0_RDCLI19__MAX_OSD_MASK 0xFC000000L 448 //DAGB0_RDCLI20 449 #define DAGB0_RDCLI20__VIRT_CHAN__SHIFT 0x0 450 #define DAGB0_RDCLI20__CHECK_TLB_CREDIT__SHIFT 0x3 451 #define DAGB0_RDCLI20__URG_HIGH__SHIFT 0x4 452 #define DAGB0_RDCLI20__URG_LOW__SHIFT 0x8 453 #define DAGB0_RDCLI20__MAX_BW_ENABLE__SHIFT 0xc 454 #define DAGB0_RDCLI20__MAX_BW__SHIFT 0xd 455 #define DAGB0_RDCLI20__MIN_BW_ENABLE__SHIFT 0x15 456 #define DAGB0_RDCLI20__MIN_BW__SHIFT 0x16 457 #define DAGB0_RDCLI20__OSD_LIMITER_ENABLE__SHIFT 0x19 458 #define DAGB0_RDCLI20__MAX_OSD__SHIFT 0x1a 459 #define DAGB0_RDCLI20__VIRT_CHAN_MASK 0x00000007L 460 #define DAGB0_RDCLI20__CHECK_TLB_CREDIT_MASK 0x00000008L 461 #define DAGB0_RDCLI20__URG_HIGH_MASK 0x000000F0L 462 #define DAGB0_RDCLI20__URG_LOW_MASK 0x00000F00L 463 #define DAGB0_RDCLI20__MAX_BW_ENABLE_MASK 0x00001000L 464 #define DAGB0_RDCLI20__MAX_BW_MASK 0x001FE000L 465 #define DAGB0_RDCLI20__MIN_BW_ENABLE_MASK 0x00200000L 466 #define DAGB0_RDCLI20__MIN_BW_MASK 0x01C00000L 467 #define DAGB0_RDCLI20__OSD_LIMITER_ENABLE_MASK 0x02000000L 468 #define DAGB0_RDCLI20__MAX_OSD_MASK 0xFC000000L 469 //DAGB0_RDCLI21 470 #define DAGB0_RDCLI21__VIRT_CHAN__SHIFT 0x0 471 #define DAGB0_RDCLI21__CHECK_TLB_CREDIT__SHIFT 0x3 472 #define DAGB0_RDCLI21__URG_HIGH__SHIFT 0x4 473 #define DAGB0_RDCLI21__URG_LOW__SHIFT 0x8 474 #define DAGB0_RDCLI21__MAX_BW_ENABLE__SHIFT 0xc 475 #define DAGB0_RDCLI21__MAX_BW__SHIFT 0xd 476 #define DAGB0_RDCLI21__MIN_BW_ENABLE__SHIFT 0x15 477 #define DAGB0_RDCLI21__MIN_BW__SHIFT 0x16 478 #define DAGB0_RDCLI21__OSD_LIMITER_ENABLE__SHIFT 0x19 479 #define DAGB0_RDCLI21__MAX_OSD__SHIFT 0x1a 480 #define DAGB0_RDCLI21__VIRT_CHAN_MASK 0x00000007L 481 #define DAGB0_RDCLI21__CHECK_TLB_CREDIT_MASK 0x00000008L 482 #define DAGB0_RDCLI21__URG_HIGH_MASK 0x000000F0L 483 #define DAGB0_RDCLI21__URG_LOW_MASK 0x00000F00L 484 #define DAGB0_RDCLI21__MAX_BW_ENABLE_MASK 0x00001000L 485 #define DAGB0_RDCLI21__MAX_BW_MASK 0x001FE000L 486 #define DAGB0_RDCLI21__MIN_BW_ENABLE_MASK 0x00200000L 487 #define DAGB0_RDCLI21__MIN_BW_MASK 0x01C00000L 488 #define DAGB0_RDCLI21__OSD_LIMITER_ENABLE_MASK 0x02000000L 489 #define DAGB0_RDCLI21__MAX_OSD_MASK 0xFC000000L 490 //DAGB0_RDCLI22 491 #define DAGB0_RDCLI22__VIRT_CHAN__SHIFT 0x0 492 #define DAGB0_RDCLI22__CHECK_TLB_CREDIT__SHIFT 0x3 493 #define DAGB0_RDCLI22__URG_HIGH__SHIFT 0x4 494 #define DAGB0_RDCLI22__URG_LOW__SHIFT 0x8 495 #define DAGB0_RDCLI22__MAX_BW_ENABLE__SHIFT 0xc 496 #define DAGB0_RDCLI22__MAX_BW__SHIFT 0xd 497 #define DAGB0_RDCLI22__MIN_BW_ENABLE__SHIFT 0x15 498 #define DAGB0_RDCLI22__MIN_BW__SHIFT 0x16 499 #define DAGB0_RDCLI22__OSD_LIMITER_ENABLE__SHIFT 0x19 500 #define DAGB0_RDCLI22__MAX_OSD__SHIFT 0x1a 501 #define DAGB0_RDCLI22__VIRT_CHAN_MASK 0x00000007L 502 #define DAGB0_RDCLI22__CHECK_TLB_CREDIT_MASK 0x00000008L 503 #define DAGB0_RDCLI22__URG_HIGH_MASK 0x000000F0L 504 #define DAGB0_RDCLI22__URG_LOW_MASK 0x00000F00L 505 #define DAGB0_RDCLI22__MAX_BW_ENABLE_MASK 0x00001000L 506 #define DAGB0_RDCLI22__MAX_BW_MASK 0x001FE000L 507 #define DAGB0_RDCLI22__MIN_BW_ENABLE_MASK 0x00200000L 508 #define DAGB0_RDCLI22__MIN_BW_MASK 0x01C00000L 509 #define DAGB0_RDCLI22__OSD_LIMITER_ENABLE_MASK 0x02000000L 510 #define DAGB0_RDCLI22__MAX_OSD_MASK 0xFC000000L 511 //DAGB0_RDCLI23 512 #define DAGB0_RDCLI23__VIRT_CHAN__SHIFT 0x0 513 #define DAGB0_RDCLI23__CHECK_TLB_CREDIT__SHIFT 0x3 514 #define DAGB0_RDCLI23__URG_HIGH__SHIFT 0x4 515 #define DAGB0_RDCLI23__URG_LOW__SHIFT 0x8 516 #define DAGB0_RDCLI23__MAX_BW_ENABLE__SHIFT 0xc 517 #define DAGB0_RDCLI23__MAX_BW__SHIFT 0xd 518 #define DAGB0_RDCLI23__MIN_BW_ENABLE__SHIFT 0x15 519 #define DAGB0_RDCLI23__MIN_BW__SHIFT 0x16 520 #define DAGB0_RDCLI23__OSD_LIMITER_ENABLE__SHIFT 0x19 521 #define DAGB0_RDCLI23__MAX_OSD__SHIFT 0x1a 522 #define DAGB0_RDCLI23__VIRT_CHAN_MASK 0x00000007L 523 #define DAGB0_RDCLI23__CHECK_TLB_CREDIT_MASK 0x00000008L 524 #define DAGB0_RDCLI23__URG_HIGH_MASK 0x000000F0L 525 #define DAGB0_RDCLI23__URG_LOW_MASK 0x00000F00L 526 #define DAGB0_RDCLI23__MAX_BW_ENABLE_MASK 0x00001000L 527 #define DAGB0_RDCLI23__MAX_BW_MASK 0x001FE000L 528 #define DAGB0_RDCLI23__MIN_BW_ENABLE_MASK 0x00200000L 529 #define DAGB0_RDCLI23__MIN_BW_MASK 0x01C00000L 530 #define DAGB0_RDCLI23__OSD_LIMITER_ENABLE_MASK 0x02000000L 531 #define DAGB0_RDCLI23__MAX_OSD_MASK 0xFC000000L 532 //DAGB0_RD_CNTL 533 #define DAGB0_RD_CNTL__CLI_MAX_BW_WINDOW__SHIFT 0x0 534 #define DAGB0_RD_CNTL__VC_MAX_BW_WINDOW__SHIFT 0x6 535 #define DAGB0_RD_CNTL__SHARE_VC_NUM__SHIFT 0xc 536 #define DAGB0_RD_CNTL__VC_ROUNDROBIN_EN__SHIFT 0xf 537 #define DAGB0_RD_CNTL__CLI_MAX_BW_WINDOW_MASK 0x0000003FL 538 #define DAGB0_RD_CNTL__VC_MAX_BW_WINDOW_MASK 0x00000FC0L 539 #define DAGB0_RD_CNTL__SHARE_VC_NUM_MASK 0x00007000L 540 #define DAGB0_RD_CNTL__VC_ROUNDROBIN_EN_MASK 0x00008000L 541 //DAGB0_RD_IO_CNTL 542 #define DAGB0_RD_IO_CNTL__OVERRIDE0_ENABLE__SHIFT 0x0 543 #define DAGB0_RD_IO_CNTL__OVERRIDE0_PRIORITY__SHIFT 0x1 544 #define DAGB0_RD_IO_CNTL__OVERRIDE0_CLIENT_ID__SHIFT 0x4 545 #define DAGB0_RD_IO_CNTL__OVERRIDE1_ENABLE__SHIFT 0x9 546 #define DAGB0_RD_IO_CNTL__OVERRIDE1_PRIORITY__SHIFT 0xa 547 #define DAGB0_RD_IO_CNTL__OVERRIDE1_CLIENT_ID__SHIFT 0xd 548 #define DAGB0_RD_IO_CNTL__COMMON_PRIORITY__SHIFT 0x12 549 #define DAGB0_RD_IO_CNTL__OVERRIDE0_ENABLE_MASK 0x00000001L 550 #define DAGB0_RD_IO_CNTL__OVERRIDE0_PRIORITY_MASK 0x0000000EL 551 #define DAGB0_RD_IO_CNTL__OVERRIDE0_CLIENT_ID_MASK 0x000001F0L 552 #define DAGB0_RD_IO_CNTL__OVERRIDE1_ENABLE_MASK 0x00000200L 553 #define DAGB0_RD_IO_CNTL__OVERRIDE1_PRIORITY_MASK 0x00001C00L 554 #define DAGB0_RD_IO_CNTL__OVERRIDE1_CLIENT_ID_MASK 0x0003E000L 555 #define DAGB0_RD_IO_CNTL__COMMON_PRIORITY_MASK 0x001C0000L 556 //DAGB0_RD_GMI_CNTL 557 #define DAGB0_RD_GMI_CNTL__OVERRIDE0_ENABLE__SHIFT 0x0 558 #define DAGB0_RD_GMI_CNTL__OVERRIDE0_PRIORITY__SHIFT 0x1 559 #define DAGB0_RD_GMI_CNTL__OVERRIDE0_CLIENT_ID__SHIFT 0x4 560 #define DAGB0_RD_GMI_CNTL__OVERRIDE1_ENABLE__SHIFT 0x9 561 #define DAGB0_RD_GMI_CNTL__OVERRIDE1_PRIORITY__SHIFT 0xa 562 #define DAGB0_RD_GMI_CNTL__OVERRIDE1_CLIENT_ID__SHIFT 0xd 563 #define DAGB0_RD_GMI_CNTL__COMMON_PRIORITY__SHIFT 0x12 564 #define DAGB0_RD_GMI_CNTL__OVERRIDE0_ENABLE_MASK 0x00000001L 565 #define DAGB0_RD_GMI_CNTL__OVERRIDE0_PRIORITY_MASK 0x0000000EL 566 #define DAGB0_RD_GMI_CNTL__OVERRIDE0_CLIENT_ID_MASK 0x000001F0L 567 #define DAGB0_RD_GMI_CNTL__OVERRIDE1_ENABLE_MASK 0x00000200L 568 #define DAGB0_RD_GMI_CNTL__OVERRIDE1_PRIORITY_MASK 0x00001C00L 569 #define DAGB0_RD_GMI_CNTL__OVERRIDE1_CLIENT_ID_MASK 0x0003E000L 570 #define DAGB0_RD_GMI_CNTL__COMMON_PRIORITY_MASK 0x001C0000L 571 //DAGB0_RD_ADDR_DAGB 572 #define DAGB0_RD_ADDR_DAGB__DAGB_ENABLE__SHIFT 0x0 573 #define DAGB0_RD_ADDR_DAGB__ENABLE_JUMP_AHEAD__SHIFT 0x3 574 #define DAGB0_RD_ADDR_DAGB__DISABLE_SELF_INIT__SHIFT 0x6 575 #define DAGB0_RD_ADDR_DAGB__WHOAMI__SHIFT 0x7 576 #define DAGB0_RD_ADDR_DAGB__JUMP_MODE__SHIFT 0xd 577 #define DAGB0_RD_ADDR_DAGB__DAGB_ENABLE_MASK 0x00000007L 578 #define DAGB0_RD_ADDR_DAGB__ENABLE_JUMP_AHEAD_MASK 0x00000038L 579 #define DAGB0_RD_ADDR_DAGB__DISABLE_SELF_INIT_MASK 0x00000040L 580 #define DAGB0_RD_ADDR_DAGB__WHOAMI_MASK 0x00001F80L 581 #define DAGB0_RD_ADDR_DAGB__JUMP_MODE_MASK 0x00002000L 582 //DAGB0_RD_CGTT_CLK_CTRL 583 #define DAGB0_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 584 #define DAGB0_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x5 585 #define DAGB0_RD_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS__SHIFT 0xd 586 #define DAGB0_RD_CGTT_CLK_CTRL__LS_DISABLE__SHIFT 0x1e 587 #define DAGB0_RD_CGTT_CLK_CTRL__BUSY_OVERRIDE__SHIFT 0x1f 588 #define DAGB0_RD_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000001FL 589 #define DAGB0_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00001FE0L 590 #define DAGB0_RD_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS_MASK 0x1FFFE000L 591 #define DAGB0_RD_CGTT_CLK_CTRL__LS_DISABLE_MASK 0x40000000L 592 #define DAGB0_RD_CGTT_CLK_CTRL__BUSY_OVERRIDE_MASK 0x80000000L 593 //DAGB0_L1TLB_RD_CGTT_CLK_CTRL 594 #define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 595 #define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x5 596 #define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS__SHIFT 0xd 597 #define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_DISABLE__SHIFT 0x1e 598 #define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__BUSY_OVERRIDE__SHIFT 0x1f 599 #define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000001FL 600 #define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00001FE0L 601 #define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS_MASK 0x1FFFE000L 602 #define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_DISABLE_MASK 0x40000000L 603 #define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__BUSY_OVERRIDE_MASK 0x80000000L 604 //DAGB0_RD_ADDR_DAGB_MAX_BURST0 605 #define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT0__SHIFT 0x0 606 #define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT1__SHIFT 0x4 607 #define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT2__SHIFT 0x8 608 #define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT3__SHIFT 0xc 609 #define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT4__SHIFT 0x10 610 #define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT5__SHIFT 0x14 611 #define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT6__SHIFT 0x18 612 #define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT7__SHIFT 0x1c 613 #define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT0_MASK 0x0000000FL 614 #define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT1_MASK 0x000000F0L 615 #define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT2_MASK 0x00000F00L 616 #define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT3_MASK 0x0000F000L 617 #define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT4_MASK 0x000F0000L 618 #define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT5_MASK 0x00F00000L 619 #define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT6_MASK 0x0F000000L 620 #define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT7_MASK 0xF0000000L 621 //DAGB0_RD_ADDR_DAGB_LAZY_TIMER0 622 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT0__SHIFT 0x0 623 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT1__SHIFT 0x4 624 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT2__SHIFT 0x8 625 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT3__SHIFT 0xc 626 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT4__SHIFT 0x10 627 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT5__SHIFT 0x14 628 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT6__SHIFT 0x18 629 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT7__SHIFT 0x1c 630 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT0_MASK 0x0000000FL 631 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT1_MASK 0x000000F0L 632 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT2_MASK 0x00000F00L 633 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT3_MASK 0x0000F000L 634 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT4_MASK 0x000F0000L 635 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT5_MASK 0x00F00000L 636 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT6_MASK 0x0F000000L 637 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT7_MASK 0xF0000000L 638 //DAGB0_RD_ADDR_DAGB_MAX_BURST1 639 #define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT8__SHIFT 0x0 640 #define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT9__SHIFT 0x4 641 #define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT10__SHIFT 0x8 642 #define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT11__SHIFT 0xc 643 #define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT12__SHIFT 0x10 644 #define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT13__SHIFT 0x14 645 #define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT14__SHIFT 0x18 646 #define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT15__SHIFT 0x1c 647 #define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT8_MASK 0x0000000FL 648 #define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT9_MASK 0x000000F0L 649 #define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT10_MASK 0x00000F00L 650 #define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT11_MASK 0x0000F000L 651 #define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT12_MASK 0x000F0000L 652 #define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT13_MASK 0x00F00000L 653 #define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT14_MASK 0x0F000000L 654 #define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT15_MASK 0xF0000000L 655 //DAGB0_RD_ADDR_DAGB_LAZY_TIMER1 656 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT8__SHIFT 0x0 657 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT9__SHIFT 0x4 658 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT10__SHIFT 0x8 659 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT11__SHIFT 0xc 660 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT12__SHIFT 0x10 661 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT13__SHIFT 0x14 662 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT14__SHIFT 0x18 663 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT15__SHIFT 0x1c 664 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT8_MASK 0x0000000FL 665 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT9_MASK 0x000000F0L 666 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT10_MASK 0x00000F00L 667 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT11_MASK 0x0000F000L 668 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT12_MASK 0x000F0000L 669 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT13_MASK 0x00F00000L 670 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT14_MASK 0x0F000000L 671 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT15_MASK 0xF0000000L 672 //DAGB0_RD_ADDR_DAGB_MAX_BURST2 673 #define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT16__SHIFT 0x0 674 #define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT17__SHIFT 0x4 675 #define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT18__SHIFT 0x8 676 #define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT19__SHIFT 0xc 677 #define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT20__SHIFT 0x10 678 #define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT21__SHIFT 0x14 679 #define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT22__SHIFT 0x18 680 #define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT23__SHIFT 0x1c 681 #define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT16_MASK 0x0000000FL 682 #define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT17_MASK 0x000000F0L 683 #define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT18_MASK 0x00000F00L 684 #define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT19_MASK 0x0000F000L 685 #define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT20_MASK 0x000F0000L 686 #define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT21_MASK 0x00F00000L 687 #define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT22_MASK 0x0F000000L 688 #define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT23_MASK 0xF0000000L 689 //DAGB0_RD_ADDR_DAGB_LAZY_TIMER2 690 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT16__SHIFT 0x0 691 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT17__SHIFT 0x4 692 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT18__SHIFT 0x8 693 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT19__SHIFT 0xc 694 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT20__SHIFT 0x10 695 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT21__SHIFT 0x14 696 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT22__SHIFT 0x18 697 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT23__SHIFT 0x1c 698 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT16_MASK 0x0000000FL 699 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT17_MASK 0x000000F0L 700 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT18_MASK 0x00000F00L 701 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT19_MASK 0x0000F000L 702 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT20_MASK 0x000F0000L 703 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT21_MASK 0x00F00000L 704 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT22_MASK 0x0F000000L 705 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT23_MASK 0xF0000000L 706 //DAGB0_RD_VC0_CNTL 707 #define DAGB0_RD_VC0_CNTL__STOR_CREDIT__SHIFT 0x0 708 #define DAGB0_RD_VC0_CNTL__MAX_BW_ENABLE__SHIFT 0xb 709 #define DAGB0_RD_VC0_CNTL__MAX_BW__SHIFT 0xc 710 #define DAGB0_RD_VC0_CNTL__MIN_BW_ENABLE__SHIFT 0x14 711 #define DAGB0_RD_VC0_CNTL__MIN_BW__SHIFT 0x15 712 #define DAGB0_RD_VC0_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 713 #define DAGB0_RD_VC0_CNTL__MAX_OSD__SHIFT 0x19 714 #define DAGB0_RD_VC0_CNTL__STOR_CREDIT_MASK 0x0000001FL 715 #define DAGB0_RD_VC0_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 716 #define DAGB0_RD_VC0_CNTL__MAX_BW_MASK 0x000FF000L 717 #define DAGB0_RD_VC0_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 718 #define DAGB0_RD_VC0_CNTL__MIN_BW_MASK 0x00E00000L 719 #define DAGB0_RD_VC0_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 720 #define DAGB0_RD_VC0_CNTL__MAX_OSD_MASK 0xFE000000L 721 //DAGB0_RD_VC1_CNTL 722 #define DAGB0_RD_VC1_CNTL__STOR_CREDIT__SHIFT 0x0 723 #define DAGB0_RD_VC1_CNTL__MAX_BW_ENABLE__SHIFT 0xb 724 #define DAGB0_RD_VC1_CNTL__MAX_BW__SHIFT 0xc 725 #define DAGB0_RD_VC1_CNTL__MIN_BW_ENABLE__SHIFT 0x14 726 #define DAGB0_RD_VC1_CNTL__MIN_BW__SHIFT 0x15 727 #define DAGB0_RD_VC1_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 728 #define DAGB0_RD_VC1_CNTL__MAX_OSD__SHIFT 0x19 729 #define DAGB0_RD_VC1_CNTL__STOR_CREDIT_MASK 0x0000001FL 730 #define DAGB0_RD_VC1_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 731 #define DAGB0_RD_VC1_CNTL__MAX_BW_MASK 0x000FF000L 732 #define DAGB0_RD_VC1_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 733 #define DAGB0_RD_VC1_CNTL__MIN_BW_MASK 0x00E00000L 734 #define DAGB0_RD_VC1_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 735 #define DAGB0_RD_VC1_CNTL__MAX_OSD_MASK 0xFE000000L 736 //DAGB0_RD_VC2_CNTL 737 #define DAGB0_RD_VC2_CNTL__STOR_CREDIT__SHIFT 0x0 738 #define DAGB0_RD_VC2_CNTL__MAX_BW_ENABLE__SHIFT 0xb 739 #define DAGB0_RD_VC2_CNTL__MAX_BW__SHIFT 0xc 740 #define DAGB0_RD_VC2_CNTL__MIN_BW_ENABLE__SHIFT 0x14 741 #define DAGB0_RD_VC2_CNTL__MIN_BW__SHIFT 0x15 742 #define DAGB0_RD_VC2_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 743 #define DAGB0_RD_VC2_CNTL__MAX_OSD__SHIFT 0x19 744 #define DAGB0_RD_VC2_CNTL__STOR_CREDIT_MASK 0x0000001FL 745 #define DAGB0_RD_VC2_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 746 #define DAGB0_RD_VC2_CNTL__MAX_BW_MASK 0x000FF000L 747 #define DAGB0_RD_VC2_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 748 #define DAGB0_RD_VC2_CNTL__MIN_BW_MASK 0x00E00000L 749 #define DAGB0_RD_VC2_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 750 #define DAGB0_RD_VC2_CNTL__MAX_OSD_MASK 0xFE000000L 751 //DAGB0_RD_VC3_CNTL 752 #define DAGB0_RD_VC3_CNTL__STOR_CREDIT__SHIFT 0x0 753 #define DAGB0_RD_VC3_CNTL__MAX_BW_ENABLE__SHIFT 0xb 754 #define DAGB0_RD_VC3_CNTL__MAX_BW__SHIFT 0xc 755 #define DAGB0_RD_VC3_CNTL__MIN_BW_ENABLE__SHIFT 0x14 756 #define DAGB0_RD_VC3_CNTL__MIN_BW__SHIFT 0x15 757 #define DAGB0_RD_VC3_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 758 #define DAGB0_RD_VC3_CNTL__MAX_OSD__SHIFT 0x19 759 #define DAGB0_RD_VC3_CNTL__STOR_CREDIT_MASK 0x0000001FL 760 #define DAGB0_RD_VC3_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 761 #define DAGB0_RD_VC3_CNTL__MAX_BW_MASK 0x000FF000L 762 #define DAGB0_RD_VC3_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 763 #define DAGB0_RD_VC3_CNTL__MIN_BW_MASK 0x00E00000L 764 #define DAGB0_RD_VC3_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 765 #define DAGB0_RD_VC3_CNTL__MAX_OSD_MASK 0xFE000000L 766 //DAGB0_RD_VC4_CNTL 767 #define DAGB0_RD_VC4_CNTL__STOR_CREDIT__SHIFT 0x0 768 #define DAGB0_RD_VC4_CNTL__MAX_BW_ENABLE__SHIFT 0xb 769 #define DAGB0_RD_VC4_CNTL__MAX_BW__SHIFT 0xc 770 #define DAGB0_RD_VC4_CNTL__MIN_BW_ENABLE__SHIFT 0x14 771 #define DAGB0_RD_VC4_CNTL__MIN_BW__SHIFT 0x15 772 #define DAGB0_RD_VC4_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 773 #define DAGB0_RD_VC4_CNTL__MAX_OSD__SHIFT 0x19 774 #define DAGB0_RD_VC4_CNTL__STOR_CREDIT_MASK 0x0000001FL 775 #define DAGB0_RD_VC4_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 776 #define DAGB0_RD_VC4_CNTL__MAX_BW_MASK 0x000FF000L 777 #define DAGB0_RD_VC4_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 778 #define DAGB0_RD_VC4_CNTL__MIN_BW_MASK 0x00E00000L 779 #define DAGB0_RD_VC4_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 780 #define DAGB0_RD_VC4_CNTL__MAX_OSD_MASK 0xFE000000L 781 //DAGB0_RD_VC5_CNTL 782 #define DAGB0_RD_VC5_CNTL__STOR_CREDIT__SHIFT 0x0 783 #define DAGB0_RD_VC5_CNTL__MAX_BW_ENABLE__SHIFT 0xb 784 #define DAGB0_RD_VC5_CNTL__MAX_BW__SHIFT 0xc 785 #define DAGB0_RD_VC5_CNTL__MIN_BW_ENABLE__SHIFT 0x14 786 #define DAGB0_RD_VC5_CNTL__MIN_BW__SHIFT 0x15 787 #define DAGB0_RD_VC5_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 788 #define DAGB0_RD_VC5_CNTL__MAX_OSD__SHIFT 0x19 789 #define DAGB0_RD_VC5_CNTL__STOR_CREDIT_MASK 0x0000001FL 790 #define DAGB0_RD_VC5_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 791 #define DAGB0_RD_VC5_CNTL__MAX_BW_MASK 0x000FF000L 792 #define DAGB0_RD_VC5_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 793 #define DAGB0_RD_VC5_CNTL__MIN_BW_MASK 0x00E00000L 794 #define DAGB0_RD_VC5_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 795 #define DAGB0_RD_VC5_CNTL__MAX_OSD_MASK 0xFE000000L 796 //DAGB0_RD_IO_VC_CNTL 797 #define DAGB0_RD_IO_VC_CNTL__MAX_BW_ENABLE__SHIFT 0x0 798 #define DAGB0_RD_IO_VC_CNTL__MAX_BW__SHIFT 0xc 799 #define DAGB0_RD_IO_VC_CNTL__MIN_BW_ENABLE__SHIFT 0x14 800 #define DAGB0_RD_IO_VC_CNTL__MIN_BW__SHIFT 0x15 801 #define DAGB0_RD_IO_VC_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 802 #define DAGB0_RD_IO_VC_CNTL__MAX_OSD__SHIFT 0x19 803 #define DAGB0_RD_IO_VC_CNTL__MAX_BW_ENABLE_MASK 0x00000001L 804 #define DAGB0_RD_IO_VC_CNTL__MAX_BW_MASK 0x000FF000L 805 #define DAGB0_RD_IO_VC_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 806 #define DAGB0_RD_IO_VC_CNTL__MIN_BW_MASK 0x00E00000L 807 #define DAGB0_RD_IO_VC_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 808 #define DAGB0_RD_IO_VC_CNTL__MAX_OSD_MASK 0xFE000000L 809 //DAGB0_RD_GMI_VC_CNTL 810 #define DAGB0_RD_GMI_VC_CNTL__MAX_BW_ENABLE__SHIFT 0x0 811 #define DAGB0_RD_GMI_VC_CNTL__MAX_BW__SHIFT 0xc 812 #define DAGB0_RD_GMI_VC_CNTL__MIN_BW_ENABLE__SHIFT 0x14 813 #define DAGB0_RD_GMI_VC_CNTL__MIN_BW__SHIFT 0x15 814 #define DAGB0_RD_GMI_VC_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 815 #define DAGB0_RD_GMI_VC_CNTL__MAX_OSD__SHIFT 0x19 816 #define DAGB0_RD_GMI_VC_CNTL__MAX_BW_ENABLE_MASK 0x00000001L 817 #define DAGB0_RD_GMI_VC_CNTL__MAX_BW_MASK 0x000FF000L 818 #define DAGB0_RD_GMI_VC_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 819 #define DAGB0_RD_GMI_VC_CNTL__MIN_BW_MASK 0x00E00000L 820 #define DAGB0_RD_GMI_VC_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 821 #define DAGB0_RD_GMI_VC_CNTL__MAX_OSD_MASK 0xFE000000L 822 //DAGB0_RD_CNTL_MISC 823 #define DAGB0_RD_CNTL_MISC__STOR_POOL_CREDIT__SHIFT 0x0 824 #define DAGB0_RD_CNTL_MISC__UTCL2_VCI__SHIFT 0x6 825 #define DAGB0_RD_CNTL_MISC__RDRET_CC_LEGACY_MODE__SHIFT 0x9 826 #define DAGB0_RD_CNTL_MISC__STOR_POOL_CREDIT_MASK 0x0000003FL 827 #define DAGB0_RD_CNTL_MISC__UTCL2_VCI_MASK 0x000001C0L 828 #define DAGB0_RD_CNTL_MISC__RDRET_CC_LEGACY_MODE_MASK 0x00000200L 829 //DAGB0_RD_TLB_CREDIT 830 #define DAGB0_RD_TLB_CREDIT__TLB0__SHIFT 0x0 831 #define DAGB0_RD_TLB_CREDIT__TLB1__SHIFT 0x5 832 #define DAGB0_RD_TLB_CREDIT__TLB2__SHIFT 0xa 833 #define DAGB0_RD_TLB_CREDIT__TLB3__SHIFT 0xf 834 #define DAGB0_RD_TLB_CREDIT__TLB4__SHIFT 0x14 835 #define DAGB0_RD_TLB_CREDIT__TLB5__SHIFT 0x19 836 #define DAGB0_RD_TLB_CREDIT__TLB0_MASK 0x0000001FL 837 #define DAGB0_RD_TLB_CREDIT__TLB1_MASK 0x000003E0L 838 #define DAGB0_RD_TLB_CREDIT__TLB2_MASK 0x00007C00L 839 #define DAGB0_RD_TLB_CREDIT__TLB3_MASK 0x000F8000L 840 #define DAGB0_RD_TLB_CREDIT__TLB4_MASK 0x01F00000L 841 #define DAGB0_RD_TLB_CREDIT__TLB5_MASK 0x3E000000L 842 //DAGB0_RD_RDRET_CREDIT_CNTL 843 #define DAGB0_RD_RDRET_CREDIT_CNTL__VC0_CREDIT__SHIFT 0x0 844 #define DAGB0_RD_RDRET_CREDIT_CNTL__VC1_CREDIT__SHIFT 0x5 845 #define DAGB0_RD_RDRET_CREDIT_CNTL__VC2_CREDIT__SHIFT 0xa 846 #define DAGB0_RD_RDRET_CREDIT_CNTL__VC3_CREDIT__SHIFT 0xf 847 #define DAGB0_RD_RDRET_CREDIT_CNTL__VC4_CREDIT__SHIFT 0x14 848 #define DAGB0_RD_RDRET_CREDIT_CNTL__VC5_CREDIT__SHIFT 0x19 849 #define DAGB0_RD_RDRET_CREDIT_CNTL__VC_MODE__SHIFT 0x1e 850 #define DAGB0_RD_RDRET_CREDIT_CNTL__FIX_EQ__SHIFT 0x1f 851 #define DAGB0_RD_RDRET_CREDIT_CNTL__VC0_CREDIT_MASK 0x0000001FL 852 #define DAGB0_RD_RDRET_CREDIT_CNTL__VC1_CREDIT_MASK 0x000003E0L 853 #define DAGB0_RD_RDRET_CREDIT_CNTL__VC2_CREDIT_MASK 0x00007C00L 854 #define DAGB0_RD_RDRET_CREDIT_CNTL__VC3_CREDIT_MASK 0x000F8000L 855 #define DAGB0_RD_RDRET_CREDIT_CNTL__VC4_CREDIT_MASK 0x01F00000L 856 #define DAGB0_RD_RDRET_CREDIT_CNTL__VC5_CREDIT_MASK 0x3E000000L 857 #define DAGB0_RD_RDRET_CREDIT_CNTL__VC_MODE_MASK 0x40000000L 858 #define DAGB0_RD_RDRET_CREDIT_CNTL__FIX_EQ_MASK 0x80000000L 859 //DAGB0_RD_RDRET_CREDIT_CNTL2 860 #define DAGB0_RD_RDRET_CREDIT_CNTL2__POOL_CREDIT__SHIFT 0x0 861 #define DAGB0_RD_RDRET_CREDIT_CNTL2__POOL_CREDIT_MASK 0x0000003FL 862 //DAGB0_RDCLI_ASK_PENDING 863 #define DAGB0_RDCLI_ASK_PENDING__BUSY__SHIFT 0x0 864 #define DAGB0_RDCLI_ASK_PENDING__BUSY_MASK 0xFFFFFFFFL 865 //DAGB0_RDCLI_GO_PENDING 866 #define DAGB0_RDCLI_GO_PENDING__BUSY__SHIFT 0x0 867 #define DAGB0_RDCLI_GO_PENDING__BUSY_MASK 0xFFFFFFFFL 868 //DAGB0_RDCLI_GBLSEND_PENDING 869 #define DAGB0_RDCLI_GBLSEND_PENDING__BUSY__SHIFT 0x0 870 #define DAGB0_RDCLI_GBLSEND_PENDING__BUSY_MASK 0xFFFFFFFFL 871 //DAGB0_RDCLI_TLB_PENDING 872 #define DAGB0_RDCLI_TLB_PENDING__BUSY__SHIFT 0x0 873 #define DAGB0_RDCLI_TLB_PENDING__BUSY_MASK 0xFFFFFFFFL 874 //DAGB0_RDCLI_OARB_PENDING 875 #define DAGB0_RDCLI_OARB_PENDING__BUSY__SHIFT 0x0 876 #define DAGB0_RDCLI_OARB_PENDING__BUSY_MASK 0xFFFFFFFFL 877 //DAGB0_RDCLI_ASK2ARB_PENDING 878 #define DAGB0_RDCLI_ASK2ARB_PENDING__BUSY__SHIFT 0x0 879 #define DAGB0_RDCLI_ASK2ARB_PENDING__BUSY_MASK 0xFFFFFFFFL 880 //DAGB0_RDCLI_ASK2DF_PENDING 881 #define DAGB0_RDCLI_ASK2DF_PENDING__BUSY__SHIFT 0x0 882 #define DAGB0_RDCLI_ASK2DF_PENDING__BUSY_MASK 0xFFFFFFFFL 883 //DAGB0_RDCLI_OSD_PENDING 884 #define DAGB0_RDCLI_OSD_PENDING__BUSY__SHIFT 0x0 885 #define DAGB0_RDCLI_OSD_PENDING__BUSY_MASK 0xFFFFFFFFL 886 //DAGB0_RDCLI_ASK_OSD_PENDING 887 #define DAGB0_RDCLI_ASK_OSD_PENDING__BUSY__SHIFT 0x0 888 #define DAGB0_RDCLI_ASK_OSD_PENDING__BUSY_MASK 0xFFFFFFFFL 889 //DAGB0_RDCLI_NOALLOC_OVERRIDE 890 #define DAGB0_RDCLI_NOALLOC_OVERRIDE__ENABLE__SHIFT 0x0 891 #define DAGB0_RDCLI_NOALLOC_OVERRIDE__ENABLE_MASK 0xFFFFFFFFL 892 //DAGB0_RDCLI_NOALLOC_OVERRIDE_VALUE 893 #define DAGB0_RDCLI_NOALLOC_OVERRIDE_VALUE__VALUE__SHIFT 0x0 894 #define DAGB0_RDCLI_NOALLOC_OVERRIDE_VALUE__VALUE_MASK 0xFFFFFFFFL 895 //DAGB0_WRCLI0 896 #define DAGB0_WRCLI0__VIRT_CHAN__SHIFT 0x0 897 #define DAGB0_WRCLI0__CHECK_TLB_CREDIT__SHIFT 0x3 898 #define DAGB0_WRCLI0__URG_HIGH__SHIFT 0x4 899 #define DAGB0_WRCLI0__URG_LOW__SHIFT 0x8 900 #define DAGB0_WRCLI0__MAX_BW_ENABLE__SHIFT 0xc 901 #define DAGB0_WRCLI0__MAX_BW__SHIFT 0xd 902 #define DAGB0_WRCLI0__MIN_BW_ENABLE__SHIFT 0x15 903 #define DAGB0_WRCLI0__MIN_BW__SHIFT 0x16 904 #define DAGB0_WRCLI0__OSD_LIMITER_ENABLE__SHIFT 0x19 905 #define DAGB0_WRCLI0__MAX_OSD__SHIFT 0x1a 906 #define DAGB0_WRCLI0__VIRT_CHAN_MASK 0x00000007L 907 #define DAGB0_WRCLI0__CHECK_TLB_CREDIT_MASK 0x00000008L 908 #define DAGB0_WRCLI0__URG_HIGH_MASK 0x000000F0L 909 #define DAGB0_WRCLI0__URG_LOW_MASK 0x00000F00L 910 #define DAGB0_WRCLI0__MAX_BW_ENABLE_MASK 0x00001000L 911 #define DAGB0_WRCLI0__MAX_BW_MASK 0x001FE000L 912 #define DAGB0_WRCLI0__MIN_BW_ENABLE_MASK 0x00200000L 913 #define DAGB0_WRCLI0__MIN_BW_MASK 0x01C00000L 914 #define DAGB0_WRCLI0__OSD_LIMITER_ENABLE_MASK 0x02000000L 915 #define DAGB0_WRCLI0__MAX_OSD_MASK 0xFC000000L 916 //DAGB0_WRCLI1 917 #define DAGB0_WRCLI1__VIRT_CHAN__SHIFT 0x0 918 #define DAGB0_WRCLI1__CHECK_TLB_CREDIT__SHIFT 0x3 919 #define DAGB0_WRCLI1__URG_HIGH__SHIFT 0x4 920 #define DAGB0_WRCLI1__URG_LOW__SHIFT 0x8 921 #define DAGB0_WRCLI1__MAX_BW_ENABLE__SHIFT 0xc 922 #define DAGB0_WRCLI1__MAX_BW__SHIFT 0xd 923 #define DAGB0_WRCLI1__MIN_BW_ENABLE__SHIFT 0x15 924 #define DAGB0_WRCLI1__MIN_BW__SHIFT 0x16 925 #define DAGB0_WRCLI1__OSD_LIMITER_ENABLE__SHIFT 0x19 926 #define DAGB0_WRCLI1__MAX_OSD__SHIFT 0x1a 927 #define DAGB0_WRCLI1__VIRT_CHAN_MASK 0x00000007L 928 #define DAGB0_WRCLI1__CHECK_TLB_CREDIT_MASK 0x00000008L 929 #define DAGB0_WRCLI1__URG_HIGH_MASK 0x000000F0L 930 #define DAGB0_WRCLI1__URG_LOW_MASK 0x00000F00L 931 #define DAGB0_WRCLI1__MAX_BW_ENABLE_MASK 0x00001000L 932 #define DAGB0_WRCLI1__MAX_BW_MASK 0x001FE000L 933 #define DAGB0_WRCLI1__MIN_BW_ENABLE_MASK 0x00200000L 934 #define DAGB0_WRCLI1__MIN_BW_MASK 0x01C00000L 935 #define DAGB0_WRCLI1__OSD_LIMITER_ENABLE_MASK 0x02000000L 936 #define DAGB0_WRCLI1__MAX_OSD_MASK 0xFC000000L 937 //DAGB0_WRCLI2 938 #define DAGB0_WRCLI2__VIRT_CHAN__SHIFT 0x0 939 #define DAGB0_WRCLI2__CHECK_TLB_CREDIT__SHIFT 0x3 940 #define DAGB0_WRCLI2__URG_HIGH__SHIFT 0x4 941 #define DAGB0_WRCLI2__URG_LOW__SHIFT 0x8 942 #define DAGB0_WRCLI2__MAX_BW_ENABLE__SHIFT 0xc 943 #define DAGB0_WRCLI2__MAX_BW__SHIFT 0xd 944 #define DAGB0_WRCLI2__MIN_BW_ENABLE__SHIFT 0x15 945 #define DAGB0_WRCLI2__MIN_BW__SHIFT 0x16 946 #define DAGB0_WRCLI2__OSD_LIMITER_ENABLE__SHIFT 0x19 947 #define DAGB0_WRCLI2__MAX_OSD__SHIFT 0x1a 948 #define DAGB0_WRCLI2__VIRT_CHAN_MASK 0x00000007L 949 #define DAGB0_WRCLI2__CHECK_TLB_CREDIT_MASK 0x00000008L 950 #define DAGB0_WRCLI2__URG_HIGH_MASK 0x000000F0L 951 #define DAGB0_WRCLI2__URG_LOW_MASK 0x00000F00L 952 #define DAGB0_WRCLI2__MAX_BW_ENABLE_MASK 0x00001000L 953 #define DAGB0_WRCLI2__MAX_BW_MASK 0x001FE000L 954 #define DAGB0_WRCLI2__MIN_BW_ENABLE_MASK 0x00200000L 955 #define DAGB0_WRCLI2__MIN_BW_MASK 0x01C00000L 956 #define DAGB0_WRCLI2__OSD_LIMITER_ENABLE_MASK 0x02000000L 957 #define DAGB0_WRCLI2__MAX_OSD_MASK 0xFC000000L 958 //DAGB0_WRCLI3 959 #define DAGB0_WRCLI3__VIRT_CHAN__SHIFT 0x0 960 #define DAGB0_WRCLI3__CHECK_TLB_CREDIT__SHIFT 0x3 961 #define DAGB0_WRCLI3__URG_HIGH__SHIFT 0x4 962 #define DAGB0_WRCLI3__URG_LOW__SHIFT 0x8 963 #define DAGB0_WRCLI3__MAX_BW_ENABLE__SHIFT 0xc 964 #define DAGB0_WRCLI3__MAX_BW__SHIFT 0xd 965 #define DAGB0_WRCLI3__MIN_BW_ENABLE__SHIFT 0x15 966 #define DAGB0_WRCLI3__MIN_BW__SHIFT 0x16 967 #define DAGB0_WRCLI3__OSD_LIMITER_ENABLE__SHIFT 0x19 968 #define DAGB0_WRCLI3__MAX_OSD__SHIFT 0x1a 969 #define DAGB0_WRCLI3__VIRT_CHAN_MASK 0x00000007L 970 #define DAGB0_WRCLI3__CHECK_TLB_CREDIT_MASK 0x00000008L 971 #define DAGB0_WRCLI3__URG_HIGH_MASK 0x000000F0L 972 #define DAGB0_WRCLI3__URG_LOW_MASK 0x00000F00L 973 #define DAGB0_WRCLI3__MAX_BW_ENABLE_MASK 0x00001000L 974 #define DAGB0_WRCLI3__MAX_BW_MASK 0x001FE000L 975 #define DAGB0_WRCLI3__MIN_BW_ENABLE_MASK 0x00200000L 976 #define DAGB0_WRCLI3__MIN_BW_MASK 0x01C00000L 977 #define DAGB0_WRCLI3__OSD_LIMITER_ENABLE_MASK 0x02000000L 978 #define DAGB0_WRCLI3__MAX_OSD_MASK 0xFC000000L 979 //DAGB0_WRCLI4 980 #define DAGB0_WRCLI4__VIRT_CHAN__SHIFT 0x0 981 #define DAGB0_WRCLI4__CHECK_TLB_CREDIT__SHIFT 0x3 982 #define DAGB0_WRCLI4__URG_HIGH__SHIFT 0x4 983 #define DAGB0_WRCLI4__URG_LOW__SHIFT 0x8 984 #define DAGB0_WRCLI4__MAX_BW_ENABLE__SHIFT 0xc 985 #define DAGB0_WRCLI4__MAX_BW__SHIFT 0xd 986 #define DAGB0_WRCLI4__MIN_BW_ENABLE__SHIFT 0x15 987 #define DAGB0_WRCLI4__MIN_BW__SHIFT 0x16 988 #define DAGB0_WRCLI4__OSD_LIMITER_ENABLE__SHIFT 0x19 989 #define DAGB0_WRCLI4__MAX_OSD__SHIFT 0x1a 990 #define DAGB0_WRCLI4__VIRT_CHAN_MASK 0x00000007L 991 #define DAGB0_WRCLI4__CHECK_TLB_CREDIT_MASK 0x00000008L 992 #define DAGB0_WRCLI4__URG_HIGH_MASK 0x000000F0L 993 #define DAGB0_WRCLI4__URG_LOW_MASK 0x00000F00L 994 #define DAGB0_WRCLI4__MAX_BW_ENABLE_MASK 0x00001000L 995 #define DAGB0_WRCLI4__MAX_BW_MASK 0x001FE000L 996 #define DAGB0_WRCLI4__MIN_BW_ENABLE_MASK 0x00200000L 997 #define DAGB0_WRCLI4__MIN_BW_MASK 0x01C00000L 998 #define DAGB0_WRCLI4__OSD_LIMITER_ENABLE_MASK 0x02000000L 999 #define DAGB0_WRCLI4__MAX_OSD_MASK 0xFC000000L 1000 //DAGB0_WRCLI5 1001 #define DAGB0_WRCLI5__VIRT_CHAN__SHIFT 0x0 1002 #define DAGB0_WRCLI5__CHECK_TLB_CREDIT__SHIFT 0x3 1003 #define DAGB0_WRCLI5__URG_HIGH__SHIFT 0x4 1004 #define DAGB0_WRCLI5__URG_LOW__SHIFT 0x8 1005 #define DAGB0_WRCLI5__MAX_BW_ENABLE__SHIFT 0xc 1006 #define DAGB0_WRCLI5__MAX_BW__SHIFT 0xd 1007 #define DAGB0_WRCLI5__MIN_BW_ENABLE__SHIFT 0x15 1008 #define DAGB0_WRCLI5__MIN_BW__SHIFT 0x16 1009 #define DAGB0_WRCLI5__OSD_LIMITER_ENABLE__SHIFT 0x19 1010 #define DAGB0_WRCLI5__MAX_OSD__SHIFT 0x1a 1011 #define DAGB0_WRCLI5__VIRT_CHAN_MASK 0x00000007L 1012 #define DAGB0_WRCLI5__CHECK_TLB_CREDIT_MASK 0x00000008L 1013 #define DAGB0_WRCLI5__URG_HIGH_MASK 0x000000F0L 1014 #define DAGB0_WRCLI5__URG_LOW_MASK 0x00000F00L 1015 #define DAGB0_WRCLI5__MAX_BW_ENABLE_MASK 0x00001000L 1016 #define DAGB0_WRCLI5__MAX_BW_MASK 0x001FE000L 1017 #define DAGB0_WRCLI5__MIN_BW_ENABLE_MASK 0x00200000L 1018 #define DAGB0_WRCLI5__MIN_BW_MASK 0x01C00000L 1019 #define DAGB0_WRCLI5__OSD_LIMITER_ENABLE_MASK 0x02000000L 1020 #define DAGB0_WRCLI5__MAX_OSD_MASK 0xFC000000L 1021 //DAGB0_WRCLI6 1022 #define DAGB0_WRCLI6__VIRT_CHAN__SHIFT 0x0 1023 #define DAGB0_WRCLI6__CHECK_TLB_CREDIT__SHIFT 0x3 1024 #define DAGB0_WRCLI6__URG_HIGH__SHIFT 0x4 1025 #define DAGB0_WRCLI6__URG_LOW__SHIFT 0x8 1026 #define DAGB0_WRCLI6__MAX_BW_ENABLE__SHIFT 0xc 1027 #define DAGB0_WRCLI6__MAX_BW__SHIFT 0xd 1028 #define DAGB0_WRCLI6__MIN_BW_ENABLE__SHIFT 0x15 1029 #define DAGB0_WRCLI6__MIN_BW__SHIFT 0x16 1030 #define DAGB0_WRCLI6__OSD_LIMITER_ENABLE__SHIFT 0x19 1031 #define DAGB0_WRCLI6__MAX_OSD__SHIFT 0x1a 1032 #define DAGB0_WRCLI6__VIRT_CHAN_MASK 0x00000007L 1033 #define DAGB0_WRCLI6__CHECK_TLB_CREDIT_MASK 0x00000008L 1034 #define DAGB0_WRCLI6__URG_HIGH_MASK 0x000000F0L 1035 #define DAGB0_WRCLI6__URG_LOW_MASK 0x00000F00L 1036 #define DAGB0_WRCLI6__MAX_BW_ENABLE_MASK 0x00001000L 1037 #define DAGB0_WRCLI6__MAX_BW_MASK 0x001FE000L 1038 #define DAGB0_WRCLI6__MIN_BW_ENABLE_MASK 0x00200000L 1039 #define DAGB0_WRCLI6__MIN_BW_MASK 0x01C00000L 1040 #define DAGB0_WRCLI6__OSD_LIMITER_ENABLE_MASK 0x02000000L 1041 #define DAGB0_WRCLI6__MAX_OSD_MASK 0xFC000000L 1042 //DAGB0_WRCLI7 1043 #define DAGB0_WRCLI7__VIRT_CHAN__SHIFT 0x0 1044 #define DAGB0_WRCLI7__CHECK_TLB_CREDIT__SHIFT 0x3 1045 #define DAGB0_WRCLI7__URG_HIGH__SHIFT 0x4 1046 #define DAGB0_WRCLI7__URG_LOW__SHIFT 0x8 1047 #define DAGB0_WRCLI7__MAX_BW_ENABLE__SHIFT 0xc 1048 #define DAGB0_WRCLI7__MAX_BW__SHIFT 0xd 1049 #define DAGB0_WRCLI7__MIN_BW_ENABLE__SHIFT 0x15 1050 #define DAGB0_WRCLI7__MIN_BW__SHIFT 0x16 1051 #define DAGB0_WRCLI7__OSD_LIMITER_ENABLE__SHIFT 0x19 1052 #define DAGB0_WRCLI7__MAX_OSD__SHIFT 0x1a 1053 #define DAGB0_WRCLI7__VIRT_CHAN_MASK 0x00000007L 1054 #define DAGB0_WRCLI7__CHECK_TLB_CREDIT_MASK 0x00000008L 1055 #define DAGB0_WRCLI7__URG_HIGH_MASK 0x000000F0L 1056 #define DAGB0_WRCLI7__URG_LOW_MASK 0x00000F00L 1057 #define DAGB0_WRCLI7__MAX_BW_ENABLE_MASK 0x00001000L 1058 #define DAGB0_WRCLI7__MAX_BW_MASK 0x001FE000L 1059 #define DAGB0_WRCLI7__MIN_BW_ENABLE_MASK 0x00200000L 1060 #define DAGB0_WRCLI7__MIN_BW_MASK 0x01C00000L 1061 #define DAGB0_WRCLI7__OSD_LIMITER_ENABLE_MASK 0x02000000L 1062 #define DAGB0_WRCLI7__MAX_OSD_MASK 0xFC000000L 1063 //DAGB0_WRCLI8 1064 #define DAGB0_WRCLI8__VIRT_CHAN__SHIFT 0x0 1065 #define DAGB0_WRCLI8__CHECK_TLB_CREDIT__SHIFT 0x3 1066 #define DAGB0_WRCLI8__URG_HIGH__SHIFT 0x4 1067 #define DAGB0_WRCLI8__URG_LOW__SHIFT 0x8 1068 #define DAGB0_WRCLI8__MAX_BW_ENABLE__SHIFT 0xc 1069 #define DAGB0_WRCLI8__MAX_BW__SHIFT 0xd 1070 #define DAGB0_WRCLI8__MIN_BW_ENABLE__SHIFT 0x15 1071 #define DAGB0_WRCLI8__MIN_BW__SHIFT 0x16 1072 #define DAGB0_WRCLI8__OSD_LIMITER_ENABLE__SHIFT 0x19 1073 #define DAGB0_WRCLI8__MAX_OSD__SHIFT 0x1a 1074 #define DAGB0_WRCLI8__VIRT_CHAN_MASK 0x00000007L 1075 #define DAGB0_WRCLI8__CHECK_TLB_CREDIT_MASK 0x00000008L 1076 #define DAGB0_WRCLI8__URG_HIGH_MASK 0x000000F0L 1077 #define DAGB0_WRCLI8__URG_LOW_MASK 0x00000F00L 1078 #define DAGB0_WRCLI8__MAX_BW_ENABLE_MASK 0x00001000L 1079 #define DAGB0_WRCLI8__MAX_BW_MASK 0x001FE000L 1080 #define DAGB0_WRCLI8__MIN_BW_ENABLE_MASK 0x00200000L 1081 #define DAGB0_WRCLI8__MIN_BW_MASK 0x01C00000L 1082 #define DAGB0_WRCLI8__OSD_LIMITER_ENABLE_MASK 0x02000000L 1083 #define DAGB0_WRCLI8__MAX_OSD_MASK 0xFC000000L 1084 //DAGB0_WRCLI9 1085 #define DAGB0_WRCLI9__VIRT_CHAN__SHIFT 0x0 1086 #define DAGB0_WRCLI9__CHECK_TLB_CREDIT__SHIFT 0x3 1087 #define DAGB0_WRCLI9__URG_HIGH__SHIFT 0x4 1088 #define DAGB0_WRCLI9__URG_LOW__SHIFT 0x8 1089 #define DAGB0_WRCLI9__MAX_BW_ENABLE__SHIFT 0xc 1090 #define DAGB0_WRCLI9__MAX_BW__SHIFT 0xd 1091 #define DAGB0_WRCLI9__MIN_BW_ENABLE__SHIFT 0x15 1092 #define DAGB0_WRCLI9__MIN_BW__SHIFT 0x16 1093 #define DAGB0_WRCLI9__OSD_LIMITER_ENABLE__SHIFT 0x19 1094 #define DAGB0_WRCLI9__MAX_OSD__SHIFT 0x1a 1095 #define DAGB0_WRCLI9__VIRT_CHAN_MASK 0x00000007L 1096 #define DAGB0_WRCLI9__CHECK_TLB_CREDIT_MASK 0x00000008L 1097 #define DAGB0_WRCLI9__URG_HIGH_MASK 0x000000F0L 1098 #define DAGB0_WRCLI9__URG_LOW_MASK 0x00000F00L 1099 #define DAGB0_WRCLI9__MAX_BW_ENABLE_MASK 0x00001000L 1100 #define DAGB0_WRCLI9__MAX_BW_MASK 0x001FE000L 1101 #define DAGB0_WRCLI9__MIN_BW_ENABLE_MASK 0x00200000L 1102 #define DAGB0_WRCLI9__MIN_BW_MASK 0x01C00000L 1103 #define DAGB0_WRCLI9__OSD_LIMITER_ENABLE_MASK 0x02000000L 1104 #define DAGB0_WRCLI9__MAX_OSD_MASK 0xFC000000L 1105 //DAGB0_WRCLI10 1106 #define DAGB0_WRCLI10__VIRT_CHAN__SHIFT 0x0 1107 #define DAGB0_WRCLI10__CHECK_TLB_CREDIT__SHIFT 0x3 1108 #define DAGB0_WRCLI10__URG_HIGH__SHIFT 0x4 1109 #define DAGB0_WRCLI10__URG_LOW__SHIFT 0x8 1110 #define DAGB0_WRCLI10__MAX_BW_ENABLE__SHIFT 0xc 1111 #define DAGB0_WRCLI10__MAX_BW__SHIFT 0xd 1112 #define DAGB0_WRCLI10__MIN_BW_ENABLE__SHIFT 0x15 1113 #define DAGB0_WRCLI10__MIN_BW__SHIFT 0x16 1114 #define DAGB0_WRCLI10__OSD_LIMITER_ENABLE__SHIFT 0x19 1115 #define DAGB0_WRCLI10__MAX_OSD__SHIFT 0x1a 1116 #define DAGB0_WRCLI10__VIRT_CHAN_MASK 0x00000007L 1117 #define DAGB0_WRCLI10__CHECK_TLB_CREDIT_MASK 0x00000008L 1118 #define DAGB0_WRCLI10__URG_HIGH_MASK 0x000000F0L 1119 #define DAGB0_WRCLI10__URG_LOW_MASK 0x00000F00L 1120 #define DAGB0_WRCLI10__MAX_BW_ENABLE_MASK 0x00001000L 1121 #define DAGB0_WRCLI10__MAX_BW_MASK 0x001FE000L 1122 #define DAGB0_WRCLI10__MIN_BW_ENABLE_MASK 0x00200000L 1123 #define DAGB0_WRCLI10__MIN_BW_MASK 0x01C00000L 1124 #define DAGB0_WRCLI10__OSD_LIMITER_ENABLE_MASK 0x02000000L 1125 #define DAGB0_WRCLI10__MAX_OSD_MASK 0xFC000000L 1126 //DAGB0_WRCLI11 1127 #define DAGB0_WRCLI11__VIRT_CHAN__SHIFT 0x0 1128 #define DAGB0_WRCLI11__CHECK_TLB_CREDIT__SHIFT 0x3 1129 #define DAGB0_WRCLI11__URG_HIGH__SHIFT 0x4 1130 #define DAGB0_WRCLI11__URG_LOW__SHIFT 0x8 1131 #define DAGB0_WRCLI11__MAX_BW_ENABLE__SHIFT 0xc 1132 #define DAGB0_WRCLI11__MAX_BW__SHIFT 0xd 1133 #define DAGB0_WRCLI11__MIN_BW_ENABLE__SHIFT 0x15 1134 #define DAGB0_WRCLI11__MIN_BW__SHIFT 0x16 1135 #define DAGB0_WRCLI11__OSD_LIMITER_ENABLE__SHIFT 0x19 1136 #define DAGB0_WRCLI11__MAX_OSD__SHIFT 0x1a 1137 #define DAGB0_WRCLI11__VIRT_CHAN_MASK 0x00000007L 1138 #define DAGB0_WRCLI11__CHECK_TLB_CREDIT_MASK 0x00000008L 1139 #define DAGB0_WRCLI11__URG_HIGH_MASK 0x000000F0L 1140 #define DAGB0_WRCLI11__URG_LOW_MASK 0x00000F00L 1141 #define DAGB0_WRCLI11__MAX_BW_ENABLE_MASK 0x00001000L 1142 #define DAGB0_WRCLI11__MAX_BW_MASK 0x001FE000L 1143 #define DAGB0_WRCLI11__MIN_BW_ENABLE_MASK 0x00200000L 1144 #define DAGB0_WRCLI11__MIN_BW_MASK 0x01C00000L 1145 #define DAGB0_WRCLI11__OSD_LIMITER_ENABLE_MASK 0x02000000L 1146 #define DAGB0_WRCLI11__MAX_OSD_MASK 0xFC000000L 1147 //DAGB0_WRCLI12 1148 #define DAGB0_WRCLI12__VIRT_CHAN__SHIFT 0x0 1149 #define DAGB0_WRCLI12__CHECK_TLB_CREDIT__SHIFT 0x3 1150 #define DAGB0_WRCLI12__URG_HIGH__SHIFT 0x4 1151 #define DAGB0_WRCLI12__URG_LOW__SHIFT 0x8 1152 #define DAGB0_WRCLI12__MAX_BW_ENABLE__SHIFT 0xc 1153 #define DAGB0_WRCLI12__MAX_BW__SHIFT 0xd 1154 #define DAGB0_WRCLI12__MIN_BW_ENABLE__SHIFT 0x15 1155 #define DAGB0_WRCLI12__MIN_BW__SHIFT 0x16 1156 #define DAGB0_WRCLI12__OSD_LIMITER_ENABLE__SHIFT 0x19 1157 #define DAGB0_WRCLI12__MAX_OSD__SHIFT 0x1a 1158 #define DAGB0_WRCLI12__VIRT_CHAN_MASK 0x00000007L 1159 #define DAGB0_WRCLI12__CHECK_TLB_CREDIT_MASK 0x00000008L 1160 #define DAGB0_WRCLI12__URG_HIGH_MASK 0x000000F0L 1161 #define DAGB0_WRCLI12__URG_LOW_MASK 0x00000F00L 1162 #define DAGB0_WRCLI12__MAX_BW_ENABLE_MASK 0x00001000L 1163 #define DAGB0_WRCLI12__MAX_BW_MASK 0x001FE000L 1164 #define DAGB0_WRCLI12__MIN_BW_ENABLE_MASK 0x00200000L 1165 #define DAGB0_WRCLI12__MIN_BW_MASK 0x01C00000L 1166 #define DAGB0_WRCLI12__OSD_LIMITER_ENABLE_MASK 0x02000000L 1167 #define DAGB0_WRCLI12__MAX_OSD_MASK 0xFC000000L 1168 //DAGB0_WRCLI13 1169 #define DAGB0_WRCLI13__VIRT_CHAN__SHIFT 0x0 1170 #define DAGB0_WRCLI13__CHECK_TLB_CREDIT__SHIFT 0x3 1171 #define DAGB0_WRCLI13__URG_HIGH__SHIFT 0x4 1172 #define DAGB0_WRCLI13__URG_LOW__SHIFT 0x8 1173 #define DAGB0_WRCLI13__MAX_BW_ENABLE__SHIFT 0xc 1174 #define DAGB0_WRCLI13__MAX_BW__SHIFT 0xd 1175 #define DAGB0_WRCLI13__MIN_BW_ENABLE__SHIFT 0x15 1176 #define DAGB0_WRCLI13__MIN_BW__SHIFT 0x16 1177 #define DAGB0_WRCLI13__OSD_LIMITER_ENABLE__SHIFT 0x19 1178 #define DAGB0_WRCLI13__MAX_OSD__SHIFT 0x1a 1179 #define DAGB0_WRCLI13__VIRT_CHAN_MASK 0x00000007L 1180 #define DAGB0_WRCLI13__CHECK_TLB_CREDIT_MASK 0x00000008L 1181 #define DAGB0_WRCLI13__URG_HIGH_MASK 0x000000F0L 1182 #define DAGB0_WRCLI13__URG_LOW_MASK 0x00000F00L 1183 #define DAGB0_WRCLI13__MAX_BW_ENABLE_MASK 0x00001000L 1184 #define DAGB0_WRCLI13__MAX_BW_MASK 0x001FE000L 1185 #define DAGB0_WRCLI13__MIN_BW_ENABLE_MASK 0x00200000L 1186 #define DAGB0_WRCLI13__MIN_BW_MASK 0x01C00000L 1187 #define DAGB0_WRCLI13__OSD_LIMITER_ENABLE_MASK 0x02000000L 1188 #define DAGB0_WRCLI13__MAX_OSD_MASK 0xFC000000L 1189 //DAGB0_WRCLI14 1190 #define DAGB0_WRCLI14__VIRT_CHAN__SHIFT 0x0 1191 #define DAGB0_WRCLI14__CHECK_TLB_CREDIT__SHIFT 0x3 1192 #define DAGB0_WRCLI14__URG_HIGH__SHIFT 0x4 1193 #define DAGB0_WRCLI14__URG_LOW__SHIFT 0x8 1194 #define DAGB0_WRCLI14__MAX_BW_ENABLE__SHIFT 0xc 1195 #define DAGB0_WRCLI14__MAX_BW__SHIFT 0xd 1196 #define DAGB0_WRCLI14__MIN_BW_ENABLE__SHIFT 0x15 1197 #define DAGB0_WRCLI14__MIN_BW__SHIFT 0x16 1198 #define DAGB0_WRCLI14__OSD_LIMITER_ENABLE__SHIFT 0x19 1199 #define DAGB0_WRCLI14__MAX_OSD__SHIFT 0x1a 1200 #define DAGB0_WRCLI14__VIRT_CHAN_MASK 0x00000007L 1201 #define DAGB0_WRCLI14__CHECK_TLB_CREDIT_MASK 0x00000008L 1202 #define DAGB0_WRCLI14__URG_HIGH_MASK 0x000000F0L 1203 #define DAGB0_WRCLI14__URG_LOW_MASK 0x00000F00L 1204 #define DAGB0_WRCLI14__MAX_BW_ENABLE_MASK 0x00001000L 1205 #define DAGB0_WRCLI14__MAX_BW_MASK 0x001FE000L 1206 #define DAGB0_WRCLI14__MIN_BW_ENABLE_MASK 0x00200000L 1207 #define DAGB0_WRCLI14__MIN_BW_MASK 0x01C00000L 1208 #define DAGB0_WRCLI14__OSD_LIMITER_ENABLE_MASK 0x02000000L 1209 #define DAGB0_WRCLI14__MAX_OSD_MASK 0xFC000000L 1210 //DAGB0_WRCLI15 1211 #define DAGB0_WRCLI15__VIRT_CHAN__SHIFT 0x0 1212 #define DAGB0_WRCLI15__CHECK_TLB_CREDIT__SHIFT 0x3 1213 #define DAGB0_WRCLI15__URG_HIGH__SHIFT 0x4 1214 #define DAGB0_WRCLI15__URG_LOW__SHIFT 0x8 1215 #define DAGB0_WRCLI15__MAX_BW_ENABLE__SHIFT 0xc 1216 #define DAGB0_WRCLI15__MAX_BW__SHIFT 0xd 1217 #define DAGB0_WRCLI15__MIN_BW_ENABLE__SHIFT 0x15 1218 #define DAGB0_WRCLI15__MIN_BW__SHIFT 0x16 1219 #define DAGB0_WRCLI15__OSD_LIMITER_ENABLE__SHIFT 0x19 1220 #define DAGB0_WRCLI15__MAX_OSD__SHIFT 0x1a 1221 #define DAGB0_WRCLI15__VIRT_CHAN_MASK 0x00000007L 1222 #define DAGB0_WRCLI15__CHECK_TLB_CREDIT_MASK 0x00000008L 1223 #define DAGB0_WRCLI15__URG_HIGH_MASK 0x000000F0L 1224 #define DAGB0_WRCLI15__URG_LOW_MASK 0x00000F00L 1225 #define DAGB0_WRCLI15__MAX_BW_ENABLE_MASK 0x00001000L 1226 #define DAGB0_WRCLI15__MAX_BW_MASK 0x001FE000L 1227 #define DAGB0_WRCLI15__MIN_BW_ENABLE_MASK 0x00200000L 1228 #define DAGB0_WRCLI15__MIN_BW_MASK 0x01C00000L 1229 #define DAGB0_WRCLI15__OSD_LIMITER_ENABLE_MASK 0x02000000L 1230 #define DAGB0_WRCLI15__MAX_OSD_MASK 0xFC000000L 1231 //DAGB0_WRCLI16 1232 #define DAGB0_WRCLI16__VIRT_CHAN__SHIFT 0x0 1233 #define DAGB0_WRCLI16__CHECK_TLB_CREDIT__SHIFT 0x3 1234 #define DAGB0_WRCLI16__URG_HIGH__SHIFT 0x4 1235 #define DAGB0_WRCLI16__URG_LOW__SHIFT 0x8 1236 #define DAGB0_WRCLI16__MAX_BW_ENABLE__SHIFT 0xc 1237 #define DAGB0_WRCLI16__MAX_BW__SHIFT 0xd 1238 #define DAGB0_WRCLI16__MIN_BW_ENABLE__SHIFT 0x15 1239 #define DAGB0_WRCLI16__MIN_BW__SHIFT 0x16 1240 #define DAGB0_WRCLI16__OSD_LIMITER_ENABLE__SHIFT 0x19 1241 #define DAGB0_WRCLI16__MAX_OSD__SHIFT 0x1a 1242 #define DAGB0_WRCLI16__VIRT_CHAN_MASK 0x00000007L 1243 #define DAGB0_WRCLI16__CHECK_TLB_CREDIT_MASK 0x00000008L 1244 #define DAGB0_WRCLI16__URG_HIGH_MASK 0x000000F0L 1245 #define DAGB0_WRCLI16__URG_LOW_MASK 0x00000F00L 1246 #define DAGB0_WRCLI16__MAX_BW_ENABLE_MASK 0x00001000L 1247 #define DAGB0_WRCLI16__MAX_BW_MASK 0x001FE000L 1248 #define DAGB0_WRCLI16__MIN_BW_ENABLE_MASK 0x00200000L 1249 #define DAGB0_WRCLI16__MIN_BW_MASK 0x01C00000L 1250 #define DAGB0_WRCLI16__OSD_LIMITER_ENABLE_MASK 0x02000000L 1251 #define DAGB0_WRCLI16__MAX_OSD_MASK 0xFC000000L 1252 //DAGB0_WRCLI17 1253 #define DAGB0_WRCLI17__VIRT_CHAN__SHIFT 0x0 1254 #define DAGB0_WRCLI17__CHECK_TLB_CREDIT__SHIFT 0x3 1255 #define DAGB0_WRCLI17__URG_HIGH__SHIFT 0x4 1256 #define DAGB0_WRCLI17__URG_LOW__SHIFT 0x8 1257 #define DAGB0_WRCLI17__MAX_BW_ENABLE__SHIFT 0xc 1258 #define DAGB0_WRCLI17__MAX_BW__SHIFT 0xd 1259 #define DAGB0_WRCLI17__MIN_BW_ENABLE__SHIFT 0x15 1260 #define DAGB0_WRCLI17__MIN_BW__SHIFT 0x16 1261 #define DAGB0_WRCLI17__OSD_LIMITER_ENABLE__SHIFT 0x19 1262 #define DAGB0_WRCLI17__MAX_OSD__SHIFT 0x1a 1263 #define DAGB0_WRCLI17__VIRT_CHAN_MASK 0x00000007L 1264 #define DAGB0_WRCLI17__CHECK_TLB_CREDIT_MASK 0x00000008L 1265 #define DAGB0_WRCLI17__URG_HIGH_MASK 0x000000F0L 1266 #define DAGB0_WRCLI17__URG_LOW_MASK 0x00000F00L 1267 #define DAGB0_WRCLI17__MAX_BW_ENABLE_MASK 0x00001000L 1268 #define DAGB0_WRCLI17__MAX_BW_MASK 0x001FE000L 1269 #define DAGB0_WRCLI17__MIN_BW_ENABLE_MASK 0x00200000L 1270 #define DAGB0_WRCLI17__MIN_BW_MASK 0x01C00000L 1271 #define DAGB0_WRCLI17__OSD_LIMITER_ENABLE_MASK 0x02000000L 1272 #define DAGB0_WRCLI17__MAX_OSD_MASK 0xFC000000L 1273 //DAGB0_WRCLI18 1274 #define DAGB0_WRCLI18__VIRT_CHAN__SHIFT 0x0 1275 #define DAGB0_WRCLI18__CHECK_TLB_CREDIT__SHIFT 0x3 1276 #define DAGB0_WRCLI18__URG_HIGH__SHIFT 0x4 1277 #define DAGB0_WRCLI18__URG_LOW__SHIFT 0x8 1278 #define DAGB0_WRCLI18__MAX_BW_ENABLE__SHIFT 0xc 1279 #define DAGB0_WRCLI18__MAX_BW__SHIFT 0xd 1280 #define DAGB0_WRCLI18__MIN_BW_ENABLE__SHIFT 0x15 1281 #define DAGB0_WRCLI18__MIN_BW__SHIFT 0x16 1282 #define DAGB0_WRCLI18__OSD_LIMITER_ENABLE__SHIFT 0x19 1283 #define DAGB0_WRCLI18__MAX_OSD__SHIFT 0x1a 1284 #define DAGB0_WRCLI18__VIRT_CHAN_MASK 0x00000007L 1285 #define DAGB0_WRCLI18__CHECK_TLB_CREDIT_MASK 0x00000008L 1286 #define DAGB0_WRCLI18__URG_HIGH_MASK 0x000000F0L 1287 #define DAGB0_WRCLI18__URG_LOW_MASK 0x00000F00L 1288 #define DAGB0_WRCLI18__MAX_BW_ENABLE_MASK 0x00001000L 1289 #define DAGB0_WRCLI18__MAX_BW_MASK 0x001FE000L 1290 #define DAGB0_WRCLI18__MIN_BW_ENABLE_MASK 0x00200000L 1291 #define DAGB0_WRCLI18__MIN_BW_MASK 0x01C00000L 1292 #define DAGB0_WRCLI18__OSD_LIMITER_ENABLE_MASK 0x02000000L 1293 #define DAGB0_WRCLI18__MAX_OSD_MASK 0xFC000000L 1294 //DAGB0_WRCLI19 1295 #define DAGB0_WRCLI19__VIRT_CHAN__SHIFT 0x0 1296 #define DAGB0_WRCLI19__CHECK_TLB_CREDIT__SHIFT 0x3 1297 #define DAGB0_WRCLI19__URG_HIGH__SHIFT 0x4 1298 #define DAGB0_WRCLI19__URG_LOW__SHIFT 0x8 1299 #define DAGB0_WRCLI19__MAX_BW_ENABLE__SHIFT 0xc 1300 #define DAGB0_WRCLI19__MAX_BW__SHIFT 0xd 1301 #define DAGB0_WRCLI19__MIN_BW_ENABLE__SHIFT 0x15 1302 #define DAGB0_WRCLI19__MIN_BW__SHIFT 0x16 1303 #define DAGB0_WRCLI19__OSD_LIMITER_ENABLE__SHIFT 0x19 1304 #define DAGB0_WRCLI19__MAX_OSD__SHIFT 0x1a 1305 #define DAGB0_WRCLI19__VIRT_CHAN_MASK 0x00000007L 1306 #define DAGB0_WRCLI19__CHECK_TLB_CREDIT_MASK 0x00000008L 1307 #define DAGB0_WRCLI19__URG_HIGH_MASK 0x000000F0L 1308 #define DAGB0_WRCLI19__URG_LOW_MASK 0x00000F00L 1309 #define DAGB0_WRCLI19__MAX_BW_ENABLE_MASK 0x00001000L 1310 #define DAGB0_WRCLI19__MAX_BW_MASK 0x001FE000L 1311 #define DAGB0_WRCLI19__MIN_BW_ENABLE_MASK 0x00200000L 1312 #define DAGB0_WRCLI19__MIN_BW_MASK 0x01C00000L 1313 #define DAGB0_WRCLI19__OSD_LIMITER_ENABLE_MASK 0x02000000L 1314 #define DAGB0_WRCLI19__MAX_OSD_MASK 0xFC000000L 1315 //DAGB0_WRCLI20 1316 #define DAGB0_WRCLI20__VIRT_CHAN__SHIFT 0x0 1317 #define DAGB0_WRCLI20__CHECK_TLB_CREDIT__SHIFT 0x3 1318 #define DAGB0_WRCLI20__URG_HIGH__SHIFT 0x4 1319 #define DAGB0_WRCLI20__URG_LOW__SHIFT 0x8 1320 #define DAGB0_WRCLI20__MAX_BW_ENABLE__SHIFT 0xc 1321 #define DAGB0_WRCLI20__MAX_BW__SHIFT 0xd 1322 #define DAGB0_WRCLI20__MIN_BW_ENABLE__SHIFT 0x15 1323 #define DAGB0_WRCLI20__MIN_BW__SHIFT 0x16 1324 #define DAGB0_WRCLI20__OSD_LIMITER_ENABLE__SHIFT 0x19 1325 #define DAGB0_WRCLI20__MAX_OSD__SHIFT 0x1a 1326 #define DAGB0_WRCLI20__VIRT_CHAN_MASK 0x00000007L 1327 #define DAGB0_WRCLI20__CHECK_TLB_CREDIT_MASK 0x00000008L 1328 #define DAGB0_WRCLI20__URG_HIGH_MASK 0x000000F0L 1329 #define DAGB0_WRCLI20__URG_LOW_MASK 0x00000F00L 1330 #define DAGB0_WRCLI20__MAX_BW_ENABLE_MASK 0x00001000L 1331 #define DAGB0_WRCLI20__MAX_BW_MASK 0x001FE000L 1332 #define DAGB0_WRCLI20__MIN_BW_ENABLE_MASK 0x00200000L 1333 #define DAGB0_WRCLI20__MIN_BW_MASK 0x01C00000L 1334 #define DAGB0_WRCLI20__OSD_LIMITER_ENABLE_MASK 0x02000000L 1335 #define DAGB0_WRCLI20__MAX_OSD_MASK 0xFC000000L 1336 //DAGB0_WRCLI21 1337 #define DAGB0_WRCLI21__VIRT_CHAN__SHIFT 0x0 1338 #define DAGB0_WRCLI21__CHECK_TLB_CREDIT__SHIFT 0x3 1339 #define DAGB0_WRCLI21__URG_HIGH__SHIFT 0x4 1340 #define DAGB0_WRCLI21__URG_LOW__SHIFT 0x8 1341 #define DAGB0_WRCLI21__MAX_BW_ENABLE__SHIFT 0xc 1342 #define DAGB0_WRCLI21__MAX_BW__SHIFT 0xd 1343 #define DAGB0_WRCLI21__MIN_BW_ENABLE__SHIFT 0x15 1344 #define DAGB0_WRCLI21__MIN_BW__SHIFT 0x16 1345 #define DAGB0_WRCLI21__OSD_LIMITER_ENABLE__SHIFT 0x19 1346 #define DAGB0_WRCLI21__MAX_OSD__SHIFT 0x1a 1347 #define DAGB0_WRCLI21__VIRT_CHAN_MASK 0x00000007L 1348 #define DAGB0_WRCLI21__CHECK_TLB_CREDIT_MASK 0x00000008L 1349 #define DAGB0_WRCLI21__URG_HIGH_MASK 0x000000F0L 1350 #define DAGB0_WRCLI21__URG_LOW_MASK 0x00000F00L 1351 #define DAGB0_WRCLI21__MAX_BW_ENABLE_MASK 0x00001000L 1352 #define DAGB0_WRCLI21__MAX_BW_MASK 0x001FE000L 1353 #define DAGB0_WRCLI21__MIN_BW_ENABLE_MASK 0x00200000L 1354 #define DAGB0_WRCLI21__MIN_BW_MASK 0x01C00000L 1355 #define DAGB0_WRCLI21__OSD_LIMITER_ENABLE_MASK 0x02000000L 1356 #define DAGB0_WRCLI21__MAX_OSD_MASK 0xFC000000L 1357 //DAGB0_WRCLI22 1358 #define DAGB0_WRCLI22__VIRT_CHAN__SHIFT 0x0 1359 #define DAGB0_WRCLI22__CHECK_TLB_CREDIT__SHIFT 0x3 1360 #define DAGB0_WRCLI22__URG_HIGH__SHIFT 0x4 1361 #define DAGB0_WRCLI22__URG_LOW__SHIFT 0x8 1362 #define DAGB0_WRCLI22__MAX_BW_ENABLE__SHIFT 0xc 1363 #define DAGB0_WRCLI22__MAX_BW__SHIFT 0xd 1364 #define DAGB0_WRCLI22__MIN_BW_ENABLE__SHIFT 0x15 1365 #define DAGB0_WRCLI22__MIN_BW__SHIFT 0x16 1366 #define DAGB0_WRCLI22__OSD_LIMITER_ENABLE__SHIFT 0x19 1367 #define DAGB0_WRCLI22__MAX_OSD__SHIFT 0x1a 1368 #define DAGB0_WRCLI22__VIRT_CHAN_MASK 0x00000007L 1369 #define DAGB0_WRCLI22__CHECK_TLB_CREDIT_MASK 0x00000008L 1370 #define DAGB0_WRCLI22__URG_HIGH_MASK 0x000000F0L 1371 #define DAGB0_WRCLI22__URG_LOW_MASK 0x00000F00L 1372 #define DAGB0_WRCLI22__MAX_BW_ENABLE_MASK 0x00001000L 1373 #define DAGB0_WRCLI22__MAX_BW_MASK 0x001FE000L 1374 #define DAGB0_WRCLI22__MIN_BW_ENABLE_MASK 0x00200000L 1375 #define DAGB0_WRCLI22__MIN_BW_MASK 0x01C00000L 1376 #define DAGB0_WRCLI22__OSD_LIMITER_ENABLE_MASK 0x02000000L 1377 #define DAGB0_WRCLI22__MAX_OSD_MASK 0xFC000000L 1378 //DAGB0_WRCLI23 1379 #define DAGB0_WRCLI23__VIRT_CHAN__SHIFT 0x0 1380 #define DAGB0_WRCLI23__CHECK_TLB_CREDIT__SHIFT 0x3 1381 #define DAGB0_WRCLI23__URG_HIGH__SHIFT 0x4 1382 #define DAGB0_WRCLI23__URG_LOW__SHIFT 0x8 1383 #define DAGB0_WRCLI23__MAX_BW_ENABLE__SHIFT 0xc 1384 #define DAGB0_WRCLI23__MAX_BW__SHIFT 0xd 1385 #define DAGB0_WRCLI23__MIN_BW_ENABLE__SHIFT 0x15 1386 #define DAGB0_WRCLI23__MIN_BW__SHIFT 0x16 1387 #define DAGB0_WRCLI23__OSD_LIMITER_ENABLE__SHIFT 0x19 1388 #define DAGB0_WRCLI23__MAX_OSD__SHIFT 0x1a 1389 #define DAGB0_WRCLI23__VIRT_CHAN_MASK 0x00000007L 1390 #define DAGB0_WRCLI23__CHECK_TLB_CREDIT_MASK 0x00000008L 1391 #define DAGB0_WRCLI23__URG_HIGH_MASK 0x000000F0L 1392 #define DAGB0_WRCLI23__URG_LOW_MASK 0x00000F00L 1393 #define DAGB0_WRCLI23__MAX_BW_ENABLE_MASK 0x00001000L 1394 #define DAGB0_WRCLI23__MAX_BW_MASK 0x001FE000L 1395 #define DAGB0_WRCLI23__MIN_BW_ENABLE_MASK 0x00200000L 1396 #define DAGB0_WRCLI23__MIN_BW_MASK 0x01C00000L 1397 #define DAGB0_WRCLI23__OSD_LIMITER_ENABLE_MASK 0x02000000L 1398 #define DAGB0_WRCLI23__MAX_OSD_MASK 0xFC000000L 1399 //DAGB0_WR_CNTL 1400 #define DAGB0_WR_CNTL__CLI_MAX_BW_WINDOW__SHIFT 0x0 1401 #define DAGB0_WR_CNTL__VC_MAX_BW_WINDOW__SHIFT 0x6 1402 #define DAGB0_WR_CNTL__VC_ROUNDROBIN_EN__SHIFT 0xc 1403 #define DAGB0_WR_CNTL__UPDATE_FED__SHIFT 0xd 1404 #define DAGB0_WR_CNTL__UPDATE_NACK__SHIFT 0xe 1405 #define DAGB0_WR_CNTL__CLI_MAX_BW_WINDOW_MASK 0x0000003FL 1406 #define DAGB0_WR_CNTL__VC_MAX_BW_WINDOW_MASK 0x00000FC0L 1407 #define DAGB0_WR_CNTL__VC_ROUNDROBIN_EN_MASK 0x00001000L 1408 #define DAGB0_WR_CNTL__UPDATE_FED_MASK 0x00002000L 1409 #define DAGB0_WR_CNTL__UPDATE_NACK_MASK 0x00004000L 1410 //DAGB0_WR_IO_CNTL 1411 #define DAGB0_WR_IO_CNTL__OVERRIDE0_ENABLE__SHIFT 0x0 1412 #define DAGB0_WR_IO_CNTL__OVERRIDE0_PRIORITY__SHIFT 0x1 1413 #define DAGB0_WR_IO_CNTL__OVERRIDE0_CLIENT_ID__SHIFT 0x4 1414 #define DAGB0_WR_IO_CNTL__OVERRIDE1_ENABLE__SHIFT 0x9 1415 #define DAGB0_WR_IO_CNTL__OVERRIDE1_PRIORITY__SHIFT 0xa 1416 #define DAGB0_WR_IO_CNTL__OVERRIDE1_CLIENT_ID__SHIFT 0xd 1417 #define DAGB0_WR_IO_CNTL__COMMON_PRIORITY__SHIFT 0x12 1418 #define DAGB0_WR_IO_CNTL__OVERRIDE0_ENABLE_MASK 0x00000001L 1419 #define DAGB0_WR_IO_CNTL__OVERRIDE0_PRIORITY_MASK 0x0000000EL 1420 #define DAGB0_WR_IO_CNTL__OVERRIDE0_CLIENT_ID_MASK 0x000001F0L 1421 #define DAGB0_WR_IO_CNTL__OVERRIDE1_ENABLE_MASK 0x00000200L 1422 #define DAGB0_WR_IO_CNTL__OVERRIDE1_PRIORITY_MASK 0x00001C00L 1423 #define DAGB0_WR_IO_CNTL__OVERRIDE1_CLIENT_ID_MASK 0x0003E000L 1424 #define DAGB0_WR_IO_CNTL__COMMON_PRIORITY_MASK 0x001C0000L 1425 //DAGB0_WR_GMI_CNTL 1426 #define DAGB0_WR_GMI_CNTL__OVERRIDE0_ENABLE__SHIFT 0x0 1427 #define DAGB0_WR_GMI_CNTL__OVERRIDE0_PRIORITY__SHIFT 0x1 1428 #define DAGB0_WR_GMI_CNTL__OVERRIDE0_CLIENT_ID__SHIFT 0x4 1429 #define DAGB0_WR_GMI_CNTL__OVERRIDE1_ENABLE__SHIFT 0x9 1430 #define DAGB0_WR_GMI_CNTL__OVERRIDE1_PRIORITY__SHIFT 0xa 1431 #define DAGB0_WR_GMI_CNTL__OVERRIDE1_CLIENT_ID__SHIFT 0xd 1432 #define DAGB0_WR_GMI_CNTL__COMMON_PRIORITY__SHIFT 0x12 1433 #define DAGB0_WR_GMI_CNTL__OVERRIDE0_ENABLE_MASK 0x00000001L 1434 #define DAGB0_WR_GMI_CNTL__OVERRIDE0_PRIORITY_MASK 0x0000000EL 1435 #define DAGB0_WR_GMI_CNTL__OVERRIDE0_CLIENT_ID_MASK 0x000001F0L 1436 #define DAGB0_WR_GMI_CNTL__OVERRIDE1_ENABLE_MASK 0x00000200L 1437 #define DAGB0_WR_GMI_CNTL__OVERRIDE1_PRIORITY_MASK 0x00001C00L 1438 #define DAGB0_WR_GMI_CNTL__OVERRIDE1_CLIENT_ID_MASK 0x0003E000L 1439 #define DAGB0_WR_GMI_CNTL__COMMON_PRIORITY_MASK 0x001C0000L 1440 //DAGB0_WR_ADDR_DAGB 1441 #define DAGB0_WR_ADDR_DAGB__DAGB_ENABLE__SHIFT 0x0 1442 #define DAGB0_WR_ADDR_DAGB__ENABLE_JUMP_AHEAD__SHIFT 0x3 1443 #define DAGB0_WR_ADDR_DAGB__DISABLE_SELF_INIT__SHIFT 0x6 1444 #define DAGB0_WR_ADDR_DAGB__WHOAMI__SHIFT 0x7 1445 #define DAGB0_WR_ADDR_DAGB__JUMP_MODE__SHIFT 0xd 1446 #define DAGB0_WR_ADDR_DAGB__DAGB_ENABLE_MASK 0x00000007L 1447 #define DAGB0_WR_ADDR_DAGB__ENABLE_JUMP_AHEAD_MASK 0x00000038L 1448 #define DAGB0_WR_ADDR_DAGB__DISABLE_SELF_INIT_MASK 0x00000040L 1449 #define DAGB0_WR_ADDR_DAGB__WHOAMI_MASK 0x00001F80L 1450 #define DAGB0_WR_ADDR_DAGB__JUMP_MODE_MASK 0x00002000L 1451 //DAGB0_WR_CGTT_CLK_CTRL 1452 #define DAGB0_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 1453 #define DAGB0_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x5 1454 #define DAGB0_WR_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS__SHIFT 0xd 1455 #define DAGB0_WR_CGTT_CLK_CTRL__LS_DISABLE__SHIFT 0x1e 1456 #define DAGB0_WR_CGTT_CLK_CTRL__BUSY_OVERRIDE__SHIFT 0x1f 1457 #define DAGB0_WR_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000001FL 1458 #define DAGB0_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00001FE0L 1459 #define DAGB0_WR_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS_MASK 0x1FFFE000L 1460 #define DAGB0_WR_CGTT_CLK_CTRL__LS_DISABLE_MASK 0x40000000L 1461 #define DAGB0_WR_CGTT_CLK_CTRL__BUSY_OVERRIDE_MASK 0x80000000L 1462 //DAGB0_L1TLB_WR_CGTT_CLK_CTRL 1463 #define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 1464 #define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x5 1465 #define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS__SHIFT 0xd 1466 #define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_DISABLE__SHIFT 0x1e 1467 #define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__BUSY_OVERRIDE__SHIFT 0x1f 1468 #define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000001FL 1469 #define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00001FE0L 1470 #define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS_MASK 0x1FFFE000L 1471 #define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_DISABLE_MASK 0x40000000L 1472 #define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__BUSY_OVERRIDE_MASK 0x80000000L 1473 //DAGB0_WR_ADDR_DAGB_MAX_BURST0 1474 #define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT0__SHIFT 0x0 1475 #define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT1__SHIFT 0x4 1476 #define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT2__SHIFT 0x8 1477 #define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT3__SHIFT 0xc 1478 #define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT4__SHIFT 0x10 1479 #define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT5__SHIFT 0x14 1480 #define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT6__SHIFT 0x18 1481 #define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT7__SHIFT 0x1c 1482 #define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT0_MASK 0x0000000FL 1483 #define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT1_MASK 0x000000F0L 1484 #define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT2_MASK 0x00000F00L 1485 #define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT3_MASK 0x0000F000L 1486 #define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT4_MASK 0x000F0000L 1487 #define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT5_MASK 0x00F00000L 1488 #define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT6_MASK 0x0F000000L 1489 #define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT7_MASK 0xF0000000L 1490 //DAGB0_WR_ADDR_DAGB_LAZY_TIMER0 1491 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT0__SHIFT 0x0 1492 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT1__SHIFT 0x4 1493 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT2__SHIFT 0x8 1494 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT3__SHIFT 0xc 1495 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT4__SHIFT 0x10 1496 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT5__SHIFT 0x14 1497 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT6__SHIFT 0x18 1498 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT7__SHIFT 0x1c 1499 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT0_MASK 0x0000000FL 1500 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT1_MASK 0x000000F0L 1501 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT2_MASK 0x00000F00L 1502 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT3_MASK 0x0000F000L 1503 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT4_MASK 0x000F0000L 1504 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT5_MASK 0x00F00000L 1505 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT6_MASK 0x0F000000L 1506 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT7_MASK 0xF0000000L 1507 //DAGB0_WR_ADDR_DAGB_MAX_BURST1 1508 #define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT8__SHIFT 0x0 1509 #define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT9__SHIFT 0x4 1510 #define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT10__SHIFT 0x8 1511 #define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT11__SHIFT 0xc 1512 #define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT12__SHIFT 0x10 1513 #define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT13__SHIFT 0x14 1514 #define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT14__SHIFT 0x18 1515 #define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT15__SHIFT 0x1c 1516 #define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT8_MASK 0x0000000FL 1517 #define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT9_MASK 0x000000F0L 1518 #define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT10_MASK 0x00000F00L 1519 #define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT11_MASK 0x0000F000L 1520 #define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT12_MASK 0x000F0000L 1521 #define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT13_MASK 0x00F00000L 1522 #define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT14_MASK 0x0F000000L 1523 #define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT15_MASK 0xF0000000L 1524 //DAGB0_WR_ADDR_DAGB_LAZY_TIMER1 1525 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT8__SHIFT 0x0 1526 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT9__SHIFT 0x4 1527 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT10__SHIFT 0x8 1528 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT11__SHIFT 0xc 1529 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT12__SHIFT 0x10 1530 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT13__SHIFT 0x14 1531 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT14__SHIFT 0x18 1532 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT15__SHIFT 0x1c 1533 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT8_MASK 0x0000000FL 1534 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT9_MASK 0x000000F0L 1535 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT10_MASK 0x00000F00L 1536 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT11_MASK 0x0000F000L 1537 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT12_MASK 0x000F0000L 1538 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT13_MASK 0x00F00000L 1539 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT14_MASK 0x0F000000L 1540 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT15_MASK 0xF0000000L 1541 //DAGB0_WR_ADDR_DAGB_MAX_BURST2 1542 #define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT16__SHIFT 0x0 1543 #define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT17__SHIFT 0x4 1544 #define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT18__SHIFT 0x8 1545 #define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT19__SHIFT 0xc 1546 #define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT20__SHIFT 0x10 1547 #define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT21__SHIFT 0x14 1548 #define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT22__SHIFT 0x18 1549 #define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT23__SHIFT 0x1c 1550 #define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT16_MASK 0x0000000FL 1551 #define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT17_MASK 0x000000F0L 1552 #define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT18_MASK 0x00000F00L 1553 #define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT19_MASK 0x0000F000L 1554 #define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT20_MASK 0x000F0000L 1555 #define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT21_MASK 0x00F00000L 1556 #define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT22_MASK 0x0F000000L 1557 #define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT23_MASK 0xF0000000L 1558 //DAGB0_WR_ADDR_DAGB_LAZY_TIMER2 1559 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT16__SHIFT 0x0 1560 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT17__SHIFT 0x4 1561 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT18__SHIFT 0x8 1562 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT19__SHIFT 0xc 1563 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT20__SHIFT 0x10 1564 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT21__SHIFT 0x14 1565 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT22__SHIFT 0x18 1566 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT23__SHIFT 0x1c 1567 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT16_MASK 0x0000000FL 1568 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT17_MASK 0x000000F0L 1569 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT18_MASK 0x00000F00L 1570 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT19_MASK 0x0000F000L 1571 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT20_MASK 0x000F0000L 1572 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT21_MASK 0x00F00000L 1573 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT22_MASK 0x0F000000L 1574 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT23_MASK 0xF0000000L 1575 //DAGB0_WR_DATA_DAGB 1576 #define DAGB0_WR_DATA_DAGB__DAGB_ENABLE__SHIFT 0x0 1577 #define DAGB0_WR_DATA_DAGB__ENABLE_JUMP_AHEAD__SHIFT 0x3 1578 #define DAGB0_WR_DATA_DAGB__DISABLE_SELF_INIT__SHIFT 0x6 1579 #define DAGB0_WR_DATA_DAGB__WHOAMI__SHIFT 0x7 1580 #define DAGB0_WR_DATA_DAGB__DAGB_ENABLE_MASK 0x00000007L 1581 #define DAGB0_WR_DATA_DAGB__ENABLE_JUMP_AHEAD_MASK 0x00000038L 1582 #define DAGB0_WR_DATA_DAGB__DISABLE_SELF_INIT_MASK 0x00000040L 1583 #define DAGB0_WR_DATA_DAGB__WHOAMI_MASK 0x00001F80L 1584 //DAGB0_WR_DATA_DAGB_MAX_BURST0 1585 #define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT0__SHIFT 0x0 1586 #define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT1__SHIFT 0x4 1587 #define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT2__SHIFT 0x8 1588 #define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT3__SHIFT 0xc 1589 #define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT4__SHIFT 0x10 1590 #define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT5__SHIFT 0x14 1591 #define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT6__SHIFT 0x18 1592 #define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT7__SHIFT 0x1c 1593 #define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT0_MASK 0x0000000FL 1594 #define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT1_MASK 0x000000F0L 1595 #define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT2_MASK 0x00000F00L 1596 #define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT3_MASK 0x0000F000L 1597 #define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT4_MASK 0x000F0000L 1598 #define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT5_MASK 0x00F00000L 1599 #define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT6_MASK 0x0F000000L 1600 #define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT7_MASK 0xF0000000L 1601 //DAGB0_WR_DATA_DAGB_LAZY_TIMER0 1602 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT0__SHIFT 0x0 1603 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT1__SHIFT 0x4 1604 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT2__SHIFT 0x8 1605 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT3__SHIFT 0xc 1606 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT4__SHIFT 0x10 1607 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT5__SHIFT 0x14 1608 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT6__SHIFT 0x18 1609 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT7__SHIFT 0x1c 1610 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT0_MASK 0x0000000FL 1611 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT1_MASK 0x000000F0L 1612 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT2_MASK 0x00000F00L 1613 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT3_MASK 0x0000F000L 1614 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT4_MASK 0x000F0000L 1615 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT5_MASK 0x00F00000L 1616 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT6_MASK 0x0F000000L 1617 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT7_MASK 0xF0000000L 1618 //DAGB0_WR_DATA_DAGB_MAX_BURST1 1619 #define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT8__SHIFT 0x0 1620 #define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT9__SHIFT 0x4 1621 #define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT10__SHIFT 0x8 1622 #define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT11__SHIFT 0xc 1623 #define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT12__SHIFT 0x10 1624 #define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT13__SHIFT 0x14 1625 #define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT14__SHIFT 0x18 1626 #define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT15__SHIFT 0x1c 1627 #define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT8_MASK 0x0000000FL 1628 #define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT9_MASK 0x000000F0L 1629 #define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT10_MASK 0x00000F00L 1630 #define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT11_MASK 0x0000F000L 1631 #define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT12_MASK 0x000F0000L 1632 #define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT13_MASK 0x00F00000L 1633 #define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT14_MASK 0x0F000000L 1634 #define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT15_MASK 0xF0000000L 1635 //DAGB0_WR_DATA_DAGB_LAZY_TIMER1 1636 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT8__SHIFT 0x0 1637 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT9__SHIFT 0x4 1638 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT10__SHIFT 0x8 1639 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT11__SHIFT 0xc 1640 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT12__SHIFT 0x10 1641 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT13__SHIFT 0x14 1642 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT14__SHIFT 0x18 1643 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT15__SHIFT 0x1c 1644 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT8_MASK 0x0000000FL 1645 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT9_MASK 0x000000F0L 1646 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT10_MASK 0x00000F00L 1647 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT11_MASK 0x0000F000L 1648 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT12_MASK 0x000F0000L 1649 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT13_MASK 0x00F00000L 1650 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT14_MASK 0x0F000000L 1651 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT15_MASK 0xF0000000L 1652 //DAGB0_WR_DATA_DAGB_MAX_BURST2 1653 #define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT16__SHIFT 0x0 1654 #define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT17__SHIFT 0x4 1655 #define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT18__SHIFT 0x8 1656 #define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT19__SHIFT 0xc 1657 #define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT20__SHIFT 0x10 1658 #define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT21__SHIFT 0x14 1659 #define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT22__SHIFT 0x18 1660 #define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT23__SHIFT 0x1c 1661 #define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT16_MASK 0x0000000FL 1662 #define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT17_MASK 0x000000F0L 1663 #define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT18_MASK 0x00000F00L 1664 #define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT19_MASK 0x0000F000L 1665 #define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT20_MASK 0x000F0000L 1666 #define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT21_MASK 0x00F00000L 1667 #define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT22_MASK 0x0F000000L 1668 #define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT23_MASK 0xF0000000L 1669 //DAGB0_WR_DATA_DAGB_LAZY_TIMER2 1670 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT16__SHIFT 0x0 1671 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT17__SHIFT 0x4 1672 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT18__SHIFT 0x8 1673 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT19__SHIFT 0xc 1674 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT20__SHIFT 0x10 1675 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT21__SHIFT 0x14 1676 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT22__SHIFT 0x18 1677 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT23__SHIFT 0x1c 1678 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT16_MASK 0x0000000FL 1679 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT17_MASK 0x000000F0L 1680 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT18_MASK 0x00000F00L 1681 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT19_MASK 0x0000F000L 1682 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT20_MASK 0x000F0000L 1683 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT21_MASK 0x00F00000L 1684 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT22_MASK 0x0F000000L 1685 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT23_MASK 0xF0000000L 1686 //DAGB0_WR_VC0_CNTL 1687 #define DAGB0_WR_VC0_CNTL__STOR_CREDIT__SHIFT 0x0 1688 #define DAGB0_WR_VC0_CNTL__MAX_BW_ENABLE__SHIFT 0xb 1689 #define DAGB0_WR_VC0_CNTL__MAX_BW__SHIFT 0xc 1690 #define DAGB0_WR_VC0_CNTL__MIN_BW_ENABLE__SHIFT 0x14 1691 #define DAGB0_WR_VC0_CNTL__MIN_BW__SHIFT 0x15 1692 #define DAGB0_WR_VC0_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 1693 #define DAGB0_WR_VC0_CNTL__MAX_OSD__SHIFT 0x19 1694 #define DAGB0_WR_VC0_CNTL__STOR_CREDIT_MASK 0x0000001FL 1695 #define DAGB0_WR_VC0_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 1696 #define DAGB0_WR_VC0_CNTL__MAX_BW_MASK 0x000FF000L 1697 #define DAGB0_WR_VC0_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 1698 #define DAGB0_WR_VC0_CNTL__MIN_BW_MASK 0x00E00000L 1699 #define DAGB0_WR_VC0_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 1700 #define DAGB0_WR_VC0_CNTL__MAX_OSD_MASK 0xFE000000L 1701 //DAGB0_WR_VC1_CNTL 1702 #define DAGB0_WR_VC1_CNTL__STOR_CREDIT__SHIFT 0x0 1703 #define DAGB0_WR_VC1_CNTL__MAX_BW_ENABLE__SHIFT 0xb 1704 #define DAGB0_WR_VC1_CNTL__MAX_BW__SHIFT 0xc 1705 #define DAGB0_WR_VC1_CNTL__MIN_BW_ENABLE__SHIFT 0x14 1706 #define DAGB0_WR_VC1_CNTL__MIN_BW__SHIFT 0x15 1707 #define DAGB0_WR_VC1_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 1708 #define DAGB0_WR_VC1_CNTL__MAX_OSD__SHIFT 0x19 1709 #define DAGB0_WR_VC1_CNTL__STOR_CREDIT_MASK 0x0000001FL 1710 #define DAGB0_WR_VC1_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 1711 #define DAGB0_WR_VC1_CNTL__MAX_BW_MASK 0x000FF000L 1712 #define DAGB0_WR_VC1_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 1713 #define DAGB0_WR_VC1_CNTL__MIN_BW_MASK 0x00E00000L 1714 #define DAGB0_WR_VC1_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 1715 #define DAGB0_WR_VC1_CNTL__MAX_OSD_MASK 0xFE000000L 1716 //DAGB0_WR_VC2_CNTL 1717 #define DAGB0_WR_VC2_CNTL__STOR_CREDIT__SHIFT 0x0 1718 #define DAGB0_WR_VC2_CNTL__MAX_BW_ENABLE__SHIFT 0xb 1719 #define DAGB0_WR_VC2_CNTL__MAX_BW__SHIFT 0xc 1720 #define DAGB0_WR_VC2_CNTL__MIN_BW_ENABLE__SHIFT 0x14 1721 #define DAGB0_WR_VC2_CNTL__MIN_BW__SHIFT 0x15 1722 #define DAGB0_WR_VC2_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 1723 #define DAGB0_WR_VC2_CNTL__MAX_OSD__SHIFT 0x19 1724 #define DAGB0_WR_VC2_CNTL__STOR_CREDIT_MASK 0x0000001FL 1725 #define DAGB0_WR_VC2_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 1726 #define DAGB0_WR_VC2_CNTL__MAX_BW_MASK 0x000FF000L 1727 #define DAGB0_WR_VC2_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 1728 #define DAGB0_WR_VC2_CNTL__MIN_BW_MASK 0x00E00000L 1729 #define DAGB0_WR_VC2_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 1730 #define DAGB0_WR_VC2_CNTL__MAX_OSD_MASK 0xFE000000L 1731 //DAGB0_WR_VC3_CNTL 1732 #define DAGB0_WR_VC3_CNTL__STOR_CREDIT__SHIFT 0x0 1733 #define DAGB0_WR_VC3_CNTL__MAX_BW_ENABLE__SHIFT 0xb 1734 #define DAGB0_WR_VC3_CNTL__MAX_BW__SHIFT 0xc 1735 #define DAGB0_WR_VC3_CNTL__MIN_BW_ENABLE__SHIFT 0x14 1736 #define DAGB0_WR_VC3_CNTL__MIN_BW__SHIFT 0x15 1737 #define DAGB0_WR_VC3_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 1738 #define DAGB0_WR_VC3_CNTL__MAX_OSD__SHIFT 0x19 1739 #define DAGB0_WR_VC3_CNTL__STOR_CREDIT_MASK 0x0000001FL 1740 #define DAGB0_WR_VC3_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 1741 #define DAGB0_WR_VC3_CNTL__MAX_BW_MASK 0x000FF000L 1742 #define DAGB0_WR_VC3_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 1743 #define DAGB0_WR_VC3_CNTL__MIN_BW_MASK 0x00E00000L 1744 #define DAGB0_WR_VC3_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 1745 #define DAGB0_WR_VC3_CNTL__MAX_OSD_MASK 0xFE000000L 1746 //DAGB0_WR_VC4_CNTL 1747 #define DAGB0_WR_VC4_CNTL__STOR_CREDIT__SHIFT 0x0 1748 #define DAGB0_WR_VC4_CNTL__MAX_BW_ENABLE__SHIFT 0xb 1749 #define DAGB0_WR_VC4_CNTL__MAX_BW__SHIFT 0xc 1750 #define DAGB0_WR_VC4_CNTL__MIN_BW_ENABLE__SHIFT 0x14 1751 #define DAGB0_WR_VC4_CNTL__MIN_BW__SHIFT 0x15 1752 #define DAGB0_WR_VC4_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 1753 #define DAGB0_WR_VC4_CNTL__MAX_OSD__SHIFT 0x19 1754 #define DAGB0_WR_VC4_CNTL__STOR_CREDIT_MASK 0x0000001FL 1755 #define DAGB0_WR_VC4_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 1756 #define DAGB0_WR_VC4_CNTL__MAX_BW_MASK 0x000FF000L 1757 #define DAGB0_WR_VC4_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 1758 #define DAGB0_WR_VC4_CNTL__MIN_BW_MASK 0x00E00000L 1759 #define DAGB0_WR_VC4_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 1760 #define DAGB0_WR_VC4_CNTL__MAX_OSD_MASK 0xFE000000L 1761 //DAGB0_WR_VC5_CNTL 1762 #define DAGB0_WR_VC5_CNTL__STOR_CREDIT__SHIFT 0x0 1763 #define DAGB0_WR_VC5_CNTL__MAX_BW_ENABLE__SHIFT 0xb 1764 #define DAGB0_WR_VC5_CNTL__MAX_BW__SHIFT 0xc 1765 #define DAGB0_WR_VC5_CNTL__MIN_BW_ENABLE__SHIFT 0x14 1766 #define DAGB0_WR_VC5_CNTL__MIN_BW__SHIFT 0x15 1767 #define DAGB0_WR_VC5_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 1768 #define DAGB0_WR_VC5_CNTL__MAX_OSD__SHIFT 0x19 1769 #define DAGB0_WR_VC5_CNTL__STOR_CREDIT_MASK 0x0000001FL 1770 #define DAGB0_WR_VC5_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 1771 #define DAGB0_WR_VC5_CNTL__MAX_BW_MASK 0x000FF000L 1772 #define DAGB0_WR_VC5_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 1773 #define DAGB0_WR_VC5_CNTL__MIN_BW_MASK 0x00E00000L 1774 #define DAGB0_WR_VC5_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 1775 #define DAGB0_WR_VC5_CNTL__MAX_OSD_MASK 0xFE000000L 1776 //DAGB0_WR_IO_VC_CNTL 1777 #define DAGB0_WR_IO_VC_CNTL__MAX_BW_ENABLE__SHIFT 0x0 1778 #define DAGB0_WR_IO_VC_CNTL__MAX_BW__SHIFT 0xc 1779 #define DAGB0_WR_IO_VC_CNTL__MIN_BW_ENABLE__SHIFT 0x14 1780 #define DAGB0_WR_IO_VC_CNTL__MIN_BW__SHIFT 0x15 1781 #define DAGB0_WR_IO_VC_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 1782 #define DAGB0_WR_IO_VC_CNTL__MAX_OSD__SHIFT 0x19 1783 #define DAGB0_WR_IO_VC_CNTL__MAX_BW_ENABLE_MASK 0x00000001L 1784 #define DAGB0_WR_IO_VC_CNTL__MAX_BW_MASK 0x000FF000L 1785 #define DAGB0_WR_IO_VC_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 1786 #define DAGB0_WR_IO_VC_CNTL__MIN_BW_MASK 0x00E00000L 1787 #define DAGB0_WR_IO_VC_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 1788 #define DAGB0_WR_IO_VC_CNTL__MAX_OSD_MASK 0xFE000000L 1789 //DAGB0_WR_GMI_VC_CNTL 1790 #define DAGB0_WR_GMI_VC_CNTL__MAX_BW_ENABLE__SHIFT 0x0 1791 #define DAGB0_WR_GMI_VC_CNTL__MAX_BW__SHIFT 0xc 1792 #define DAGB0_WR_GMI_VC_CNTL__MIN_BW_ENABLE__SHIFT 0x14 1793 #define DAGB0_WR_GMI_VC_CNTL__MIN_BW__SHIFT 0x15 1794 #define DAGB0_WR_GMI_VC_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 1795 #define DAGB0_WR_GMI_VC_CNTL__MAX_OSD__SHIFT 0x19 1796 #define DAGB0_WR_GMI_VC_CNTL__MAX_BW_ENABLE_MASK 0x00000001L 1797 #define DAGB0_WR_GMI_VC_CNTL__MAX_BW_MASK 0x000FF000L 1798 #define DAGB0_WR_GMI_VC_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 1799 #define DAGB0_WR_GMI_VC_CNTL__MIN_BW_MASK 0x00E00000L 1800 #define DAGB0_WR_GMI_VC_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 1801 #define DAGB0_WR_GMI_VC_CNTL__MAX_OSD_MASK 0xFE000000L 1802 //DAGB0_WR_CNTL_MISC 1803 #define DAGB0_WR_CNTL_MISC__STOR_POOL_CREDIT__SHIFT 0x0 1804 #define DAGB0_WR_CNTL_MISC__HDP_CID__SHIFT 0x6 1805 #define DAGB0_WR_CNTL_MISC__STOR_POOL_CREDIT_MASK 0x0000003FL 1806 #define DAGB0_WR_CNTL_MISC__HDP_CID_MASK 0x000007C0L 1807 //DAGB0_WR_TLB_CREDIT 1808 #define DAGB0_WR_TLB_CREDIT__TLB0__SHIFT 0x0 1809 #define DAGB0_WR_TLB_CREDIT__TLB1__SHIFT 0x5 1810 #define DAGB0_WR_TLB_CREDIT__TLB2__SHIFT 0xa 1811 #define DAGB0_WR_TLB_CREDIT__TLB3__SHIFT 0xf 1812 #define DAGB0_WR_TLB_CREDIT__TLB4__SHIFT 0x14 1813 #define DAGB0_WR_TLB_CREDIT__TLB5__SHIFT 0x19 1814 #define DAGB0_WR_TLB_CREDIT__TLB0_MASK 0x0000001FL 1815 #define DAGB0_WR_TLB_CREDIT__TLB1_MASK 0x000003E0L 1816 #define DAGB0_WR_TLB_CREDIT__TLB2_MASK 0x00007C00L 1817 #define DAGB0_WR_TLB_CREDIT__TLB3_MASK 0x000F8000L 1818 #define DAGB0_WR_TLB_CREDIT__TLB4_MASK 0x01F00000L 1819 #define DAGB0_WR_TLB_CREDIT__TLB5_MASK 0x3E000000L 1820 //DAGB0_WR_DATA_CREDIT 1821 #define DAGB0_WR_DATA_CREDIT__DLOCK_VC_CREDITS__SHIFT 0x0 1822 #define DAGB0_WR_DATA_CREDIT__LARGE_BURST_CREDITS__SHIFT 0x8 1823 #define DAGB0_WR_DATA_CREDIT__MIDDLE_BURST_CREDITS__SHIFT 0x10 1824 #define DAGB0_WR_DATA_CREDIT__SMALL_BURST_CREDITS__SHIFT 0x18 1825 #define DAGB0_WR_DATA_CREDIT__DLOCK_VC_CREDITS_MASK 0x000000FFL 1826 #define DAGB0_WR_DATA_CREDIT__LARGE_BURST_CREDITS_MASK 0x0000FF00L 1827 #define DAGB0_WR_DATA_CREDIT__MIDDLE_BURST_CREDITS_MASK 0x00FF0000L 1828 #define DAGB0_WR_DATA_CREDIT__SMALL_BURST_CREDITS_MASK 0xFF000000L 1829 //DAGB0_WR_MISC_CREDIT 1830 #define DAGB0_WR_MISC_CREDIT__ATOMIC_CREDIT__SHIFT 0x0 1831 #define DAGB0_WR_MISC_CREDIT__DLOCK_VC_NUM__SHIFT 0x6 1832 #define DAGB0_WR_MISC_CREDIT__ATOMIC_CREDIT_MASK 0x0000003FL 1833 #define DAGB0_WR_MISC_CREDIT__DLOCK_VC_NUM_MASK 0x000001C0L 1834 //DAGB0_WR_DATA_FIFO_CREDIT_CNTL1 1835 #define DAGB0_WR_DATA_FIFO_CREDIT_CNTL1__VC0_CREDIT__SHIFT 0x0 1836 #define DAGB0_WR_DATA_FIFO_CREDIT_CNTL1__VC1_CREDIT__SHIFT 0x5 1837 #define DAGB0_WR_DATA_FIFO_CREDIT_CNTL1__VC2_CREDIT__SHIFT 0xa 1838 #define DAGB0_WR_DATA_FIFO_CREDIT_CNTL1__VC3_CREDIT__SHIFT 0xf 1839 #define DAGB0_WR_DATA_FIFO_CREDIT_CNTL1__POOL_CREDIT__SHIFT 0x14 1840 #define DAGB0_WR_DATA_FIFO_CREDIT_CNTL1__VC_MODE__SHIFT 0x19 1841 #define DAGB0_WR_DATA_FIFO_CREDIT_CNTL1__FIX_EQ__SHIFT 0x1a 1842 #define DAGB0_WR_DATA_FIFO_CREDIT_CNTL1__FIX0__SHIFT 0x1b 1843 #define DAGB0_WR_DATA_FIFO_CREDIT_CNTL1__VC0_CREDIT_MASK 0x0000001FL 1844 #define DAGB0_WR_DATA_FIFO_CREDIT_CNTL1__VC1_CREDIT_MASK 0x000003E0L 1845 #define DAGB0_WR_DATA_FIFO_CREDIT_CNTL1__VC2_CREDIT_MASK 0x00007C00L 1846 #define DAGB0_WR_DATA_FIFO_CREDIT_CNTL1__VC3_CREDIT_MASK 0x000F8000L 1847 #define DAGB0_WR_DATA_FIFO_CREDIT_CNTL1__POOL_CREDIT_MASK 0x01F00000L 1848 #define DAGB0_WR_DATA_FIFO_CREDIT_CNTL1__VC_MODE_MASK 0x02000000L 1849 #define DAGB0_WR_DATA_FIFO_CREDIT_CNTL1__FIX_EQ_MASK 0x04000000L 1850 #define DAGB0_WR_DATA_FIFO_CREDIT_CNTL1__FIX0_MASK 0x08000000L 1851 //DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1 1852 #define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC0_CREDIT__SHIFT 0x0 1853 #define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC1_CREDIT__SHIFT 0x5 1854 #define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC2_CREDIT__SHIFT 0xa 1855 #define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC3_CREDIT__SHIFT 0xf 1856 #define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__POOL_CREDIT__SHIFT 0x14 1857 #define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC_MODE__SHIFT 0x1a 1858 #define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX_EQ__SHIFT 0x1b 1859 #define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX0__SHIFT 0x1c 1860 #define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC0_CREDIT_MASK 0x0000001FL 1861 #define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC1_CREDIT_MASK 0x000003E0L 1862 #define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC2_CREDIT_MASK 0x00007C00L 1863 #define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC3_CREDIT_MASK 0x000F8000L 1864 #define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__POOL_CREDIT_MASK 0x03F00000L 1865 #define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC_MODE_MASK 0x04000000L 1866 #define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX_EQ_MASK 0x08000000L 1867 #define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX0_MASK 0x10000000L 1868 //DAGB0_WRCLI_ASK_PENDING 1869 #define DAGB0_WRCLI_ASK_PENDING__BUSY__SHIFT 0x0 1870 #define DAGB0_WRCLI_ASK_PENDING__BUSY_MASK 0xFFFFFFFFL 1871 //DAGB0_WRCLI_GO_PENDING 1872 #define DAGB0_WRCLI_GO_PENDING__BUSY__SHIFT 0x0 1873 #define DAGB0_WRCLI_GO_PENDING__BUSY_MASK 0xFFFFFFFFL 1874 //DAGB0_WRCLI_GBLSEND_PENDING 1875 #define DAGB0_WRCLI_GBLSEND_PENDING__BUSY__SHIFT 0x0 1876 #define DAGB0_WRCLI_GBLSEND_PENDING__BUSY_MASK 0xFFFFFFFFL 1877 //DAGB0_WRCLI_TLB_PENDING 1878 #define DAGB0_WRCLI_TLB_PENDING__BUSY__SHIFT 0x0 1879 #define DAGB0_WRCLI_TLB_PENDING__BUSY_MASK 0xFFFFFFFFL 1880 //DAGB0_WRCLI_OARB_PENDING 1881 #define DAGB0_WRCLI_OARB_PENDING__BUSY__SHIFT 0x0 1882 #define DAGB0_WRCLI_OARB_PENDING__BUSY_MASK 0xFFFFFFFFL 1883 //DAGB0_WRCLI_ASK2ARB_PENDING 1884 #define DAGB0_WRCLI_ASK2ARB_PENDING__BUSY__SHIFT 0x0 1885 #define DAGB0_WRCLI_ASK2ARB_PENDING__BUSY_MASK 0xFFFFFFFFL 1886 //DAGB0_WRCLI_ASK2DF_PENDING 1887 #define DAGB0_WRCLI_ASK2DF_PENDING__BUSY__SHIFT 0x0 1888 #define DAGB0_WRCLI_ASK2DF_PENDING__BUSY_MASK 0xFFFFFFFFL 1889 //DAGB0_WRCLI_OSD_PENDING 1890 #define DAGB0_WRCLI_OSD_PENDING__BUSY__SHIFT 0x0 1891 #define DAGB0_WRCLI_OSD_PENDING__BUSY_MASK 0xFFFFFFFFL 1892 //DAGB0_WRCLI_ASK_OSD_PENDING 1893 #define DAGB0_WRCLI_ASK_OSD_PENDING__BUSY__SHIFT 0x0 1894 #define DAGB0_WRCLI_ASK_OSD_PENDING__BUSY_MASK 0xFFFFFFFFL 1895 //DAGB0_WRCLI_DBUS_ASK_PENDING 1896 #define DAGB0_WRCLI_DBUS_ASK_PENDING__BUSY__SHIFT 0x0 1897 #define DAGB0_WRCLI_DBUS_ASK_PENDING__BUSY_MASK 0xFFFFFFFFL 1898 //DAGB0_WRCLI_DBUS_GO_PENDING 1899 #define DAGB0_WRCLI_DBUS_GO_PENDING__BUSY__SHIFT 0x0 1900 #define DAGB0_WRCLI_DBUS_GO_PENDING__BUSY_MASK 0xFFFFFFFFL 1901 //DAGB0_WRCLI_GPU_SNOOP_OVERRIDE 1902 #define DAGB0_WRCLI_GPU_SNOOP_OVERRIDE__ENABLE__SHIFT 0x0 1903 #define DAGB0_WRCLI_GPU_SNOOP_OVERRIDE__ENABLE_MASK 0xFFFFFFFFL 1904 //DAGB0_WRCLI_GPU_SNOOP_OVERRIDE_VALUE 1905 #define DAGB0_WRCLI_GPU_SNOOP_OVERRIDE_VALUE__ENABLE__SHIFT 0x0 1906 #define DAGB0_WRCLI_GPU_SNOOP_OVERRIDE_VALUE__ENABLE_MASK 0xFFFFFFFFL 1907 //DAGB0_WRCLI_NOALLOC_OVERRIDE 1908 #define DAGB0_WRCLI_NOALLOC_OVERRIDE__ENABLE__SHIFT 0x0 1909 #define DAGB0_WRCLI_NOALLOC_OVERRIDE__ENABLE_MASK 0xFFFFFFFFL 1910 //DAGB0_WRCLI_NOALLOC_OVERRIDE_VALUE 1911 #define DAGB0_WRCLI_NOALLOC_OVERRIDE_VALUE__VALUE__SHIFT 0x0 1912 #define DAGB0_WRCLI_NOALLOC_OVERRIDE_VALUE__VALUE_MASK 0xFFFFFFFFL 1913 //DAGB0_DAGB_DLY 1914 #define DAGB0_DAGB_DLY__DLY__SHIFT 0x0 1915 #define DAGB0_DAGB_DLY__CLI__SHIFT 0x8 1916 #define DAGB0_DAGB_DLY__POS__SHIFT 0x10 1917 #define DAGB0_DAGB_DLY__DLY_MASK 0x000000FFL 1918 #define DAGB0_DAGB_DLY__CLI_MASK 0x0000FF00L 1919 #define DAGB0_DAGB_DLY__POS_MASK 0x000F0000L 1920 //DAGB0_CNTL_MISC 1921 #define DAGB0_CNTL_MISC__BW_INIT_CYCLE__SHIFT 0x0 1922 #define DAGB0_CNTL_MISC__BW_INIT_CYCLE_MASK 0x0000003FL 1923 //DAGB0_CNTL_MISC2 1924 #define DAGB0_CNTL_MISC2__WR_BUSY_OVERRIDE__SHIFT 0x0 1925 #define DAGB0_CNTL_MISC2__RD_BUSY_OVERRIDE__SHIFT 0x1 1926 #define DAGB0_CNTL_MISC2__TLBWR_BUSY_OVERRIDE__SHIFT 0x2 1927 #define DAGB0_CNTL_MISC2__TLBRD_BUSY_OVERRIDE__SHIFT 0x3 1928 #define DAGB0_CNTL_MISC2__SDP_BUSY_OVERRIDE__SHIFT 0x4 1929 #define DAGB0_CNTL_MISC2__SWAP_CTL__SHIFT 0x5 1930 #define DAGB0_CNTL_MISC2__ENABLE_PARITY_CHECK__SHIFT 0x6 1931 #define DAGB0_CNTL_MISC2__RDATA_PARITY_CHECK4NACK__SHIFT 0x7 1932 #define DAGB0_CNTL_MISC2__WDATA_PARITY_CHECK4RAS__SHIFT 0x8 1933 #define DAGB0_CNTL_MISC2__RDRET_FIFO_PERF__SHIFT 0x9 1934 #define DAGB0_CNTL_MISC2__DISABLE_RDRET_TAP_CHAIN_FGCG__SHIFT 0xa 1935 #define DAGB0_CNTL_MISC2__DISABLE_WRRET_TAP_CHAIN_FGCG__SHIFT 0xb 1936 #define DAGB0_CNTL_MISC2__WR_BUSY_OVERRIDE_MASK 0x00000001L 1937 #define DAGB0_CNTL_MISC2__RD_BUSY_OVERRIDE_MASK 0x00000002L 1938 #define DAGB0_CNTL_MISC2__TLBWR_BUSY_OVERRIDE_MASK 0x00000004L 1939 #define DAGB0_CNTL_MISC2__TLBRD_BUSY_OVERRIDE_MASK 0x00000008L 1940 #define DAGB0_CNTL_MISC2__SDP_BUSY_OVERRIDE_MASK 0x00000010L 1941 #define DAGB0_CNTL_MISC2__SWAP_CTL_MASK 0x00000020L 1942 #define DAGB0_CNTL_MISC2__ENABLE_PARITY_CHECK_MASK 0x00000040L 1943 #define DAGB0_CNTL_MISC2__RDATA_PARITY_CHECK4NACK_MASK 0x00000080L 1944 #define DAGB0_CNTL_MISC2__WDATA_PARITY_CHECK4RAS_MASK 0x00000100L 1945 #define DAGB0_CNTL_MISC2__RDRET_FIFO_PERF_MASK 0x00000200L 1946 #define DAGB0_CNTL_MISC2__DISABLE_RDRET_TAP_CHAIN_FGCG_MASK 0x00000400L 1947 #define DAGB0_CNTL_MISC2__DISABLE_WRRET_TAP_CHAIN_FGCG_MASK 0x00000800L 1948 //DAGB0_FIFO_EMPTY 1949 #define DAGB0_FIFO_EMPTY__EMPTY__SHIFT 0x0 1950 #define DAGB0_FIFO_EMPTY__EMPTY_MASK 0x0001FFFFL 1951 //DAGB0_FIFO_FULL 1952 #define DAGB0_FIFO_FULL__FULL__SHIFT 0x0 1953 #define DAGB0_FIFO_FULL__FULL_MASK 0x0000FFFFL 1954 //DAGB0_RD_CREDITS_FULL 1955 #define DAGB0_RD_CREDITS_FULL__FULL__SHIFT 0x0 1956 #define DAGB0_RD_CREDITS_FULL__FULL_MASK 0x0000007FL 1957 //DAGB0_WR_CREDITS_FULL 1958 #define DAGB0_WR_CREDITS_FULL__FULL__SHIFT 0x0 1959 #define DAGB0_WR_CREDITS_FULL__FULL_MASK 0x0001FFFFL 1960 //DAGB0_PERFCOUNTER_LO 1961 #define DAGB0_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 1962 #define DAGB0_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL 1963 //DAGB0_PERFCOUNTER_HI 1964 #define DAGB0_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 1965 #define DAGB0_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 1966 #define DAGB0_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL 1967 #define DAGB0_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L 1968 //DAGB0_PERFCOUNTER0_CFG 1969 #define DAGB0_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 1970 #define DAGB0_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 1971 #define DAGB0_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 1972 #define DAGB0_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c 1973 #define DAGB0_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d 1974 #define DAGB0_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL 1975 #define DAGB0_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L 1976 #define DAGB0_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L 1977 #define DAGB0_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L 1978 #define DAGB0_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L 1979 //DAGB0_PERFCOUNTER1_CFG 1980 #define DAGB0_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 1981 #define DAGB0_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 1982 #define DAGB0_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 1983 #define DAGB0_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c 1984 #define DAGB0_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d 1985 #define DAGB0_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL 1986 #define DAGB0_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L 1987 #define DAGB0_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L 1988 #define DAGB0_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L 1989 #define DAGB0_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L 1990 //DAGB0_PERFCOUNTER2_CFG 1991 #define DAGB0_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0 1992 #define DAGB0_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8 1993 #define DAGB0_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18 1994 #define DAGB0_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c 1995 #define DAGB0_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d 1996 #define DAGB0_PERFCOUNTER2_CFG__PERF_SEL_MASK 0x000000FFL 1997 #define DAGB0_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0x0000FF00L 1998 #define DAGB0_PERFCOUNTER2_CFG__PERF_MODE_MASK 0x0F000000L 1999 #define DAGB0_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000L 2000 #define DAGB0_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000L 2001 //DAGB0_PERFCOUNTER_RSLT_CNTL 2002 #define DAGB0_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 2003 #define DAGB0_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 2004 #define DAGB0_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 2005 #define DAGB0_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 2006 #define DAGB0_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 2007 #define DAGB0_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a 2008 #define DAGB0_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x00000003L 2009 #define DAGB0_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L 2010 #define DAGB0_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L 2011 #define DAGB0_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L 2012 #define DAGB0_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L 2013 #define DAGB0_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L 2014 //DAGB0_L1TLB_REG_RW 2015 #define DAGB0_L1TLB_REG_RW__REG_WRITE_L1TLB_CTRL__SHIFT 0x0 2016 #define DAGB0_L1TLB_REG_RW__REG_READ_L1TLB_CTRL__SHIFT 0x1 2017 #define DAGB0_L1TLB_REG_RW__RESERVE__SHIFT 0x2 2018 #define DAGB0_L1TLB_REG_RW__REG_WRITE_L1TLB_CTRL_MASK 0x00000001L 2019 #define DAGB0_L1TLB_REG_RW__REG_READ_L1TLB_CTRL_MASK 0x00000002L 2020 #define DAGB0_L1TLB_REG_RW__RESERVE_MASK 0x3FFFFFFCL 2021 //DAGB0_RESERVE1 2022 #define DAGB0_RESERVE1__RESERVE__SHIFT 0x0 2023 #define DAGB0_RESERVE1__RESERVE_MASK 0xFFFFFFFFL 2024 //DAGB0_RESERVE2 2025 #define DAGB0_RESERVE2__RESERVE__SHIFT 0x0 2026 #define DAGB0_RESERVE2__RESERVE_MASK 0xFFFFFFFFL 2027 //DAGB0_RESERVE3 2028 #define DAGB0_RESERVE3__RESERVE__SHIFT 0x0 2029 #define DAGB0_RESERVE3__RESERVE_MASK 0xFFFFFFFFL 2030 //DAGB0_RESERVE4 2031 #define DAGB0_RESERVE4__RESERVE__SHIFT 0x0 2032 #define DAGB0_RESERVE4__RESERVE_MASK 0xFFFFFFFFL 2033 //DAGB0_SDP_RD_BW_CNTL 2034 #define DAGB0_SDP_RD_BW_CNTL__MAX_BW_ENABLE__SHIFT 0x0 2035 #define DAGB0_SDP_RD_BW_CNTL__MAX_BW__SHIFT 0x1 2036 #define DAGB0_SDP_RD_BW_CNTL__MIN_BW_ENABLE__SHIFT 0x9 2037 #define DAGB0_SDP_RD_BW_CNTL__MIN_BW__SHIFT 0xa 2038 #define DAGB0_SDP_RD_BW_CNTL__MAX_BW_WINDOW__SHIFT 0xd 2039 #define DAGB0_SDP_RD_BW_CNTL__MAX_BW_ENABLE_MASK 0x00000001L 2040 #define DAGB0_SDP_RD_BW_CNTL__MAX_BW_MASK 0x000001FEL 2041 #define DAGB0_SDP_RD_BW_CNTL__MIN_BW_ENABLE_MASK 0x00000200L 2042 #define DAGB0_SDP_RD_BW_CNTL__MIN_BW_MASK 0x00001C00L 2043 #define DAGB0_SDP_RD_BW_CNTL__MAX_BW_WINDOW_MASK 0x0007E000L 2044 //DAGB0_SDP_PRIORITY_OVERRIDE 2045 #define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE0_PRIORITY__SHIFT 0x0 2046 #define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE0_CLIENT_ID__SHIFT 0x4 2047 #define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_DRAM_RD__SHIFT 0x9 2048 #define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_DRAM_WR__SHIFT 0xa 2049 #define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_GMI_RD__SHIFT 0xb 2050 #define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_GMI_WR__SHIFT 0xc 2051 #define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_IO_RD__SHIFT 0xd 2052 #define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_IO_WR__SHIFT 0xe 2053 #define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE1_PRIORITY__SHIFT 0x10 2054 #define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE1_CLIENT_ID__SHIFT 0x14 2055 #define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_DRAM_RD__SHIFT 0x19 2056 #define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_DRAM_WR__SHIFT 0x1a 2057 #define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_GMI_RD__SHIFT 0x1b 2058 #define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_GMI_WR__SHIFT 0x1c 2059 #define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_IO_RD__SHIFT 0x1d 2060 #define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_IO_WR__SHIFT 0x1e 2061 #define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE0_PRIORITY_MASK 0x0000000FL 2062 #define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE0_CLIENT_ID_MASK 0x000001F0L 2063 #define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_DRAM_RD_MASK 0x00000200L 2064 #define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_DRAM_WR_MASK 0x00000400L 2065 #define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_GMI_RD_MASK 0x00000800L 2066 #define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_GMI_WR_MASK 0x00001000L 2067 #define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_IO_RD_MASK 0x00002000L 2068 #define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_IO_WR_MASK 0x00004000L 2069 #define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE1_PRIORITY_MASK 0x000F0000L 2070 #define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE1_CLIENT_ID_MASK 0x01F00000L 2071 #define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_DRAM_RD_MASK 0x02000000L 2072 #define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_DRAM_WR_MASK 0x04000000L 2073 #define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_GMI_RD_MASK 0x08000000L 2074 #define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_GMI_WR_MASK 0x10000000L 2075 #define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_IO_RD_MASK 0x20000000L 2076 #define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_IO_WR_MASK 0x40000000L 2077 //DAGB0_SDP_RD_PRIORITY 2078 #define DAGB0_SDP_RD_PRIORITY__RD_VC0_PRIORITY__SHIFT 0x0 2079 #define DAGB0_SDP_RD_PRIORITY__RD_VC1_PRIORITY__SHIFT 0x4 2080 #define DAGB0_SDP_RD_PRIORITY__RD_VC2_PRIORITY__SHIFT 0x8 2081 #define DAGB0_SDP_RD_PRIORITY__RD_VC3_PRIORITY__SHIFT 0xc 2082 #define DAGB0_SDP_RD_PRIORITY__RD_VC4_PRIORITY__SHIFT 0x10 2083 #define DAGB0_SDP_RD_PRIORITY__RD_VC5_PRIORITY__SHIFT 0x14 2084 #define DAGB0_SDP_RD_PRIORITY__RD_VC0_PRIORITY_MASK 0x0000000FL 2085 #define DAGB0_SDP_RD_PRIORITY__RD_VC1_PRIORITY_MASK 0x000000F0L 2086 #define DAGB0_SDP_RD_PRIORITY__RD_VC2_PRIORITY_MASK 0x00000F00L 2087 #define DAGB0_SDP_RD_PRIORITY__RD_VC3_PRIORITY_MASK 0x0000F000L 2088 #define DAGB0_SDP_RD_PRIORITY__RD_VC4_PRIORITY_MASK 0x000F0000L 2089 #define DAGB0_SDP_RD_PRIORITY__RD_VC5_PRIORITY_MASK 0x00F00000L 2090 //DAGB0_SDP_WR_PRIORITY 2091 #define DAGB0_SDP_WR_PRIORITY__WR_VC0_PRIORITY__SHIFT 0x0 2092 #define DAGB0_SDP_WR_PRIORITY__WR_VC1_PRIORITY__SHIFT 0x4 2093 #define DAGB0_SDP_WR_PRIORITY__WR_VC2_PRIORITY__SHIFT 0x8 2094 #define DAGB0_SDP_WR_PRIORITY__WR_VC3_PRIORITY__SHIFT 0xc 2095 #define DAGB0_SDP_WR_PRIORITY__WR_VC4_PRIORITY__SHIFT 0x10 2096 #define DAGB0_SDP_WR_PRIORITY__WR_VC5_PRIORITY__SHIFT 0x14 2097 #define DAGB0_SDP_WR_PRIORITY__WR_VC0_PRIORITY_MASK 0x0000000FL 2098 #define DAGB0_SDP_WR_PRIORITY__WR_VC1_PRIORITY_MASK 0x000000F0L 2099 #define DAGB0_SDP_WR_PRIORITY__WR_VC2_PRIORITY_MASK 0x00000F00L 2100 #define DAGB0_SDP_WR_PRIORITY__WR_VC3_PRIORITY_MASK 0x0000F000L 2101 #define DAGB0_SDP_WR_PRIORITY__WR_VC4_PRIORITY_MASK 0x000F0000L 2102 #define DAGB0_SDP_WR_PRIORITY__WR_VC5_PRIORITY_MASK 0x00F00000L 2103 //DAGB0_SDP_RD_CLI2SDP_VC_MAP 2104 #define DAGB0_SDP_RD_CLI2SDP_VC_MAP__SRT_VC_MAP__SHIFT 0x0 2105 #define DAGB0_SDP_RD_CLI2SDP_VC_MAP__NRT_VC_MAP__SHIFT 0x3 2106 #define DAGB0_SDP_RD_CLI2SDP_VC_MAP__DLOCK_VC_MAP__SHIFT 0x6 2107 #define DAGB0_SDP_RD_CLI2SDP_VC_MAP__HRT_VC_MAP__SHIFT 0x9 2108 #define DAGB0_SDP_RD_CLI2SDP_VC_MAP__IO_VC_MAP__SHIFT 0xc 2109 #define DAGB0_SDP_RD_CLI2SDP_VC_MAP__GMI_VC_MAP__SHIFT 0xf 2110 #define DAGB0_SDP_RD_CLI2SDP_VC_MAP__SRT_VC_MAP_MASK 0x00000007L 2111 #define DAGB0_SDP_RD_CLI2SDP_VC_MAP__NRT_VC_MAP_MASK 0x00000038L 2112 #define DAGB0_SDP_RD_CLI2SDP_VC_MAP__DLOCK_VC_MAP_MASK 0x000001C0L 2113 #define DAGB0_SDP_RD_CLI2SDP_VC_MAP__HRT_VC_MAP_MASK 0x00000E00L 2114 #define DAGB0_SDP_RD_CLI2SDP_VC_MAP__IO_VC_MAP_MASK 0x00007000L 2115 #define DAGB0_SDP_RD_CLI2SDP_VC_MAP__GMI_VC_MAP_MASK 0x00038000L 2116 //DAGB0_SDP_WR_CLI2SDP_VC_MAP 2117 #define DAGB0_SDP_WR_CLI2SDP_VC_MAP__SRT_VC_MAP__SHIFT 0x0 2118 #define DAGB0_SDP_WR_CLI2SDP_VC_MAP__NRT_VC_MAP__SHIFT 0x3 2119 #define DAGB0_SDP_WR_CLI2SDP_VC_MAP__DLOCK_VC_MAP__SHIFT 0x6 2120 #define DAGB0_SDP_WR_CLI2SDP_VC_MAP__HRT_VC_MAP__SHIFT 0x9 2121 #define DAGB0_SDP_WR_CLI2SDP_VC_MAP__IO_VC_MAP__SHIFT 0xc 2122 #define DAGB0_SDP_WR_CLI2SDP_VC_MAP__GMI_VC_MAP__SHIFT 0xf 2123 #define DAGB0_SDP_WR_CLI2SDP_VC_MAP__SRT_VC_MAP_MASK 0x00000007L 2124 #define DAGB0_SDP_WR_CLI2SDP_VC_MAP__NRT_VC_MAP_MASK 0x00000038L 2125 #define DAGB0_SDP_WR_CLI2SDP_VC_MAP__DLOCK_VC_MAP_MASK 0x000001C0L 2126 #define DAGB0_SDP_WR_CLI2SDP_VC_MAP__HRT_VC_MAP_MASK 0x00000E00L 2127 #define DAGB0_SDP_WR_CLI2SDP_VC_MAP__IO_VC_MAP_MASK 0x00007000L 2128 #define DAGB0_SDP_WR_CLI2SDP_VC_MAP__GMI_VC_MAP_MASK 0x00038000L 2129 //DAGB0_SDP_ENABLE 2130 #define DAGB0_SDP_ENABLE__ENABLE__SHIFT 0x0 2131 #define DAGB0_SDP_ENABLE__ENABLE_MASK 0x00000001L 2132 //DAGB0_SDP_CREDITS 2133 #define DAGB0_SDP_CREDITS__TAG_LIMIT__SHIFT 0x0 2134 #define DAGB0_SDP_CREDITS__WR_RESP_CREDITS__SHIFT 0x8 2135 #define DAGB0_SDP_CREDITS__RD_RESP_CREDITS__SHIFT 0x10 2136 #define DAGB0_SDP_CREDITS__TAG_LIMIT_MASK 0x000000FFL 2137 #define DAGB0_SDP_CREDITS__WR_RESP_CREDITS_MASK 0x00007F00L 2138 #define DAGB0_SDP_CREDITS__RD_RESP_CREDITS_MASK 0x01FF0000L 2139 //DAGB0_SDP_TAG_RESERVE0 2140 #define DAGB0_SDP_TAG_RESERVE0__VC0__SHIFT 0x0 2141 #define DAGB0_SDP_TAG_RESERVE0__VC1__SHIFT 0x8 2142 #define DAGB0_SDP_TAG_RESERVE0__VC2__SHIFT 0x10 2143 #define DAGB0_SDP_TAG_RESERVE0__VC3__SHIFT 0x18 2144 #define DAGB0_SDP_TAG_RESERVE0__VC0_MASK 0x000000FFL 2145 #define DAGB0_SDP_TAG_RESERVE0__VC1_MASK 0x0000FF00L 2146 #define DAGB0_SDP_TAG_RESERVE0__VC2_MASK 0x00FF0000L 2147 #define DAGB0_SDP_TAG_RESERVE0__VC3_MASK 0xFF000000L 2148 //DAGB0_SDP_TAG_RESERVE1 2149 #define DAGB0_SDP_TAG_RESERVE1__VC4__SHIFT 0x0 2150 #define DAGB0_SDP_TAG_RESERVE1__VC5__SHIFT 0x8 2151 #define DAGB0_SDP_TAG_RESERVE1__VC6__SHIFT 0x10 2152 #define DAGB0_SDP_TAG_RESERVE1__VC7__SHIFT 0x18 2153 #define DAGB0_SDP_TAG_RESERVE1__VC4_MASK 0x000000FFL 2154 #define DAGB0_SDP_TAG_RESERVE1__VC5_MASK 0x0000FF00L 2155 #define DAGB0_SDP_TAG_RESERVE1__VC6_MASK 0x00FF0000L 2156 #define DAGB0_SDP_TAG_RESERVE1__VC7_MASK 0xFF000000L 2157 //DAGB0_SDP_VCC_RESERVE0 2158 #define DAGB0_SDP_VCC_RESERVE0__VC0_CREDITS__SHIFT 0x0 2159 #define DAGB0_SDP_VCC_RESERVE0__VC1_CREDITS__SHIFT 0x6 2160 #define DAGB0_SDP_VCC_RESERVE0__VC2_CREDITS__SHIFT 0xc 2161 #define DAGB0_SDP_VCC_RESERVE0__VC3_CREDITS__SHIFT 0x12 2162 #define DAGB0_SDP_VCC_RESERVE0__VC4_CREDITS__SHIFT 0x18 2163 #define DAGB0_SDP_VCC_RESERVE0__VC0_CREDITS_MASK 0x0000003FL 2164 #define DAGB0_SDP_VCC_RESERVE0__VC1_CREDITS_MASK 0x00000FC0L 2165 #define DAGB0_SDP_VCC_RESERVE0__VC2_CREDITS_MASK 0x0003F000L 2166 #define DAGB0_SDP_VCC_RESERVE0__VC3_CREDITS_MASK 0x00FC0000L 2167 #define DAGB0_SDP_VCC_RESERVE0__VC4_CREDITS_MASK 0x3F000000L 2168 //DAGB0_SDP_VCC_RESERVE1 2169 #define DAGB0_SDP_VCC_RESERVE1__VC5_CREDITS__SHIFT 0x0 2170 #define DAGB0_SDP_VCC_RESERVE1__VC6_CREDITS__SHIFT 0x6 2171 #define DAGB0_SDP_VCC_RESERVE1__VC7_CREDITS__SHIFT 0xc 2172 #define DAGB0_SDP_VCC_RESERVE1__DISTRIBUTE_POOL__SHIFT 0x1f 2173 #define DAGB0_SDP_VCC_RESERVE1__VC5_CREDITS_MASK 0x0000003FL 2174 #define DAGB0_SDP_VCC_RESERVE1__VC6_CREDITS_MASK 0x00000FC0L 2175 #define DAGB0_SDP_VCC_RESERVE1__VC7_CREDITS_MASK 0x0003F000L 2176 #define DAGB0_SDP_VCC_RESERVE1__DISTRIBUTE_POOL_MASK 0x80000000L 2177 //DAGB0_SDP_ERR_STATUS 2178 #define DAGB0_SDP_ERR_STATUS__SDP_RDRSP_STATUS__SHIFT 0x0 2179 #define DAGB0_SDP_ERR_STATUS__SDP_WRRSP_STATUS__SHIFT 0x4 2180 #define DAGB0_SDP_ERR_STATUS__SDP_RDRSP_DATASTATUS__SHIFT 0x8 2181 #define DAGB0_SDP_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR__SHIFT 0xa 2182 #define DAGB0_SDP_ERR_STATUS__CLEAR_ERROR_STATUS__SHIFT 0xb 2183 #define DAGB0_SDP_ERR_STATUS__BUSY_ON_ERROR__SHIFT 0xc 2184 #define DAGB0_SDP_ERR_STATUS__FUE_FLAG__SHIFT 0xd 2185 #define DAGB0_SDP_ERR_STATUS__IGNORE_RDRSP_FED__SHIFT 0xe 2186 #define DAGB0_SDP_ERR_STATUS__INTERRUPT_ON_FATAL__SHIFT 0xf 2187 #define DAGB0_SDP_ERR_STATUS__INTERRUPT_IGNORE_CLI_FATAL__SHIFT 0x10 2188 #define DAGB0_SDP_ERR_STATUS__LEVEL_INTERRUPT__SHIFT 0x11 2189 #define DAGB0_SDP_ERR_STATUS__BUSY_ON_CMPL_FATAL_ERROR__SHIFT 0x12 2190 #define DAGB0_SDP_ERR_STATUS__SDP_RDRSP_STATUS_MASK 0x0000000FL 2191 #define DAGB0_SDP_ERR_STATUS__SDP_WRRSP_STATUS_MASK 0x000000F0L 2192 #define DAGB0_SDP_ERR_STATUS__SDP_RDRSP_DATASTATUS_MASK 0x00000300L 2193 #define DAGB0_SDP_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR_MASK 0x00000400L 2194 #define DAGB0_SDP_ERR_STATUS__CLEAR_ERROR_STATUS_MASK 0x00000800L 2195 #define DAGB0_SDP_ERR_STATUS__BUSY_ON_ERROR_MASK 0x00001000L 2196 #define DAGB0_SDP_ERR_STATUS__FUE_FLAG_MASK 0x00002000L 2197 #define DAGB0_SDP_ERR_STATUS__IGNORE_RDRSP_FED_MASK 0x00004000L 2198 #define DAGB0_SDP_ERR_STATUS__INTERRUPT_ON_FATAL_MASK 0x00008000L 2199 #define DAGB0_SDP_ERR_STATUS__INTERRUPT_IGNORE_CLI_FATAL_MASK 0x00010000L 2200 #define DAGB0_SDP_ERR_STATUS__LEVEL_INTERRUPT_MASK 0x00020000L 2201 #define DAGB0_SDP_ERR_STATUS__BUSY_ON_CMPL_FATAL_ERROR_MASK 0x00040000L 2202 //DAGB0_SDP_REQ_CNTL 2203 #define DAGB0_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_READ__SHIFT 0x0 2204 #define DAGB0_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_WRITE__SHIFT 0x1 2205 #define DAGB0_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_ATOMIC__SHIFT 0x2 2206 #define DAGB0_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_DRAM__SHIFT 0x3 2207 #define DAGB0_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_GMI__SHIFT 0x4 2208 #define DAGB0_SDP_REQ_CNTL__INNER_DOMAIN_MODE__SHIFT 0x5 2209 #define DAGB0_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_READ__SHIFT 0x6 2210 #define DAGB0_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_WRITE__SHIFT 0x8 2211 #define DAGB0_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_ATOMIC__SHIFT 0xa 2212 #define DAGB0_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_READ_MASK 0x00000001L 2213 #define DAGB0_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_WRITE_MASK 0x00000002L 2214 #define DAGB0_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_ATOMIC_MASK 0x00000004L 2215 #define DAGB0_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_DRAM_MASK 0x00000008L 2216 #define DAGB0_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_GMI_MASK 0x00000010L 2217 #define DAGB0_SDP_REQ_CNTL__INNER_DOMAIN_MODE_MASK 0x00000020L 2218 #define DAGB0_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_READ_MASK 0x000000C0L 2219 #define DAGB0_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_WRITE_MASK 0x00000300L 2220 #define DAGB0_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_ATOMIC_MASK 0x00000C00L 2221 //DAGB0_SDP_MISC 2222 #define DAGB0_SDP_MISC__EARLYWRRET_ENABLE_VC0__SHIFT 0x0 2223 #define DAGB0_SDP_MISC__EARLYWRRET_ENABLE_VC1__SHIFT 0x1 2224 #define DAGB0_SDP_MISC__EARLYWRRET_ENABLE_VC2__SHIFT 0x2 2225 #define DAGB0_SDP_MISC__EARLYWRRET_ENABLE_VC3__SHIFT 0x3 2226 #define DAGB0_SDP_MISC__EARLYWRRET_ENABLE_VC4__SHIFT 0x4 2227 #define DAGB0_SDP_MISC__EARLYWRRET_ENABLE_VC5__SHIFT 0x5 2228 #define DAGB0_SDP_MISC__EARLYWRRET_ENABLE_VC6__SHIFT 0x6 2229 #define DAGB0_SDP_MISC__EARLYWRRET_ENABLE_VC7__SHIFT 0x7 2230 #define DAGB0_SDP_MISC__EARLY_SDP_ORIGDATA__SHIFT 0x8 2231 #define DAGB0_SDP_MISC__LINKMGR_DYNAMIC_MODE__SHIFT 0x9 2232 #define DAGB0_SDP_MISC__LINKMGR_HALT_THRESHOLD__SHIFT 0xb 2233 #define DAGB0_SDP_MISC__LINKMGR_RECONNECT_DELAY__SHIFT 0xd 2234 #define DAGB0_SDP_MISC__LINKMGR_IDLE_THRESHOLD__SHIFT 0xf 2235 #define DAGB0_SDP_MISC__SDP_DAT_FIFO0_MARGIN__SHIFT 0x14 2236 #define DAGB0_SDP_MISC__SDP_DAT_FIFO1_MARGIN__SHIFT 0x15 2237 #define DAGB0_SDP_MISC__EARLYWRRET_ENABLE_VC0_MASK 0x00000001L 2238 #define DAGB0_SDP_MISC__EARLYWRRET_ENABLE_VC1_MASK 0x00000002L 2239 #define DAGB0_SDP_MISC__EARLYWRRET_ENABLE_VC2_MASK 0x00000004L 2240 #define DAGB0_SDP_MISC__EARLYWRRET_ENABLE_VC3_MASK 0x00000008L 2241 #define DAGB0_SDP_MISC__EARLYWRRET_ENABLE_VC4_MASK 0x00000010L 2242 #define DAGB0_SDP_MISC__EARLYWRRET_ENABLE_VC5_MASK 0x00000020L 2243 #define DAGB0_SDP_MISC__EARLYWRRET_ENABLE_VC6_MASK 0x00000040L 2244 #define DAGB0_SDP_MISC__EARLYWRRET_ENABLE_VC7_MASK 0x00000080L 2245 #define DAGB0_SDP_MISC__EARLY_SDP_ORIGDATA_MASK 0x00000100L 2246 #define DAGB0_SDP_MISC__LINKMGR_DYNAMIC_MODE_MASK 0x00000600L 2247 #define DAGB0_SDP_MISC__LINKMGR_HALT_THRESHOLD_MASK 0x00001800L 2248 #define DAGB0_SDP_MISC__LINKMGR_RECONNECT_DELAY_MASK 0x00006000L 2249 #define DAGB0_SDP_MISC__LINKMGR_IDLE_THRESHOLD_MASK 0x000F8000L 2250 #define DAGB0_SDP_MISC__SDP_DAT_FIFO0_MARGIN_MASK 0x00100000L 2251 #define DAGB0_SDP_MISC__SDP_DAT_FIFO1_MARGIN_MASK 0x00200000L 2252 //DAGB0_SDP_MISC2 2253 #define DAGB0_SDP_MISC2__RRET_SWAP_MODE__SHIFT 0x0 2254 #define DAGB0_SDP_MISC2__BLOCK_REQUESTS__SHIFT 0x1 2255 #define DAGB0_SDP_MISC2__REQUESTS_BLOCKED__SHIFT 0x2 2256 #define DAGB0_SDP_MISC2__RDRSP_CR_RELEASE_MODE__SHIFT 0x3 2257 #define DAGB0_SDP_MISC2__RRET_SWAP_MODE_MASK 0x00000001L 2258 #define DAGB0_SDP_MISC2__BLOCK_REQUESTS_MASK 0x00000002L 2259 #define DAGB0_SDP_MISC2__REQUESTS_BLOCKED_MASK 0x00000004L 2260 #define DAGB0_SDP_MISC2__RDRSP_CR_RELEASE_MODE_MASK 0x00000008L 2261 //DAGB0_SDP_VCD_RESERVE0 2262 #define DAGB0_SDP_VCD_RESERVE0__VC0_CREDITS__SHIFT 0x0 2263 #define DAGB0_SDP_VCD_RESERVE0__VC1_CREDITS__SHIFT 0x6 2264 #define DAGB0_SDP_VCD_RESERVE0__VC2_CREDITS__SHIFT 0xc 2265 #define DAGB0_SDP_VCD_RESERVE0__VC3_CREDITS__SHIFT 0x12 2266 #define DAGB0_SDP_VCD_RESERVE0__VC4_CREDITS__SHIFT 0x18 2267 #define DAGB0_SDP_VCD_RESERVE0__VC0_CREDITS_MASK 0x0000003FL 2268 #define DAGB0_SDP_VCD_RESERVE0__VC1_CREDITS_MASK 0x00000FC0L 2269 #define DAGB0_SDP_VCD_RESERVE0__VC2_CREDITS_MASK 0x0003F000L 2270 #define DAGB0_SDP_VCD_RESERVE0__VC3_CREDITS_MASK 0x00FC0000L 2271 #define DAGB0_SDP_VCD_RESERVE0__VC4_CREDITS_MASK 0x3F000000L 2272 //DAGB0_SDP_VCD_RESERVE1 2273 #define DAGB0_SDP_VCD_RESERVE1__VC5_CREDITS__SHIFT 0x0 2274 #define DAGB0_SDP_VCD_RESERVE1__VC6_CREDITS__SHIFT 0x6 2275 #define DAGB0_SDP_VCD_RESERVE1__VC7_CREDITS__SHIFT 0xc 2276 #define DAGB0_SDP_VCD_RESERVE1__DISTRIBUTE_POOL__SHIFT 0x12 2277 #define DAGB0_SDP_VCD_RESERVE1__VC5_CREDITS_MASK 0x0000003FL 2278 #define DAGB0_SDP_VCD_RESERVE1__VC6_CREDITS_MASK 0x00000FC0L 2279 #define DAGB0_SDP_VCD_RESERVE1__VC7_CREDITS_MASK 0x0003F000L 2280 #define DAGB0_SDP_VCD_RESERVE1__DISTRIBUTE_POOL_MASK 0x00040000L 2281 //DAGB0_SDP_ARB_CNTL0 2282 #define DAGB0_SDP_ARB_CNTL0__EARLY_SW2RD_ON_PRI__SHIFT 0x0 2283 #define DAGB0_SDP_ARB_CNTL0__EARLY_SW2WR_ON_PRI__SHIFT 0x1 2284 #define DAGB0_SDP_ARB_CNTL0__EARLY_SW2RD_ON_RES__SHIFT 0x2 2285 #define DAGB0_SDP_ARB_CNTL0__EARLY_SW2WR_ON_RES__SHIFT 0x3 2286 #define DAGB0_SDP_ARB_CNTL0__RW_SWITCH_POP_MODE__SHIFT 0x4 2287 #define DAGB0_SDP_ARB_CNTL0__ERREVENT_ON_ERROR__SHIFT 0x5 2288 #define DAGB0_SDP_ARB_CNTL0__HALTREQ_ON_ERROR__SHIFT 0x6 2289 #define DAGB0_SDP_ARB_CNTL0__DED_MODE__SHIFT 0x7 2290 #define DAGB0_SDP_ARB_CNTL0__EARLY_SW2RD_ON_PRI_MASK 0x00000001L 2291 #define DAGB0_SDP_ARB_CNTL0__EARLY_SW2WR_ON_PRI_MASK 0x00000002L 2292 #define DAGB0_SDP_ARB_CNTL0__EARLY_SW2RD_ON_RES_MASK 0x00000004L 2293 #define DAGB0_SDP_ARB_CNTL0__EARLY_SW2WR_ON_RES_MASK 0x00000008L 2294 #define DAGB0_SDP_ARB_CNTL0__RW_SWITCH_POP_MODE_MASK 0x00000010L 2295 #define DAGB0_SDP_ARB_CNTL0__ERREVENT_ON_ERROR_MASK 0x00000020L 2296 #define DAGB0_SDP_ARB_CNTL0__HALTREQ_ON_ERROR_MASK 0x00000040L 2297 #define DAGB0_SDP_ARB_CNTL0__DED_MODE_MASK 0x00000080L 2298 //DAGB0_SDP_ARB_CNTL1 2299 #define DAGB0_SDP_ARB_CNTL1__RD_BURST_LIMIT_CYCL__SHIFT 0x0 2300 #define DAGB0_SDP_ARB_CNTL1__WR_BURST_LIMIT_CYCL__SHIFT 0x8 2301 #define DAGB0_SDP_ARB_CNTL1__RD_BURST_LIMIT_DATA__SHIFT 0x10 2302 #define DAGB0_SDP_ARB_CNTL1__WR_BURST_LIMIT_DATA__SHIFT 0x18 2303 #define DAGB0_SDP_ARB_CNTL1__RD_BURST_LIMIT_CYCL_MASK 0x0000007FL 2304 #define DAGB0_SDP_ARB_CNTL1__WR_BURST_LIMIT_CYCL_MASK 0x00007F00L 2305 #define DAGB0_SDP_ARB_CNTL1__RD_BURST_LIMIT_DATA_MASK 0x007F0000L 2306 #define DAGB0_SDP_ARB_CNTL1__WR_BURST_LIMIT_DATA_MASK 0x7F000000L 2307 //DAGB0_FATAL_ERROR_CNTL 2308 #define DAGB0_FATAL_ERROR_CNTL__FILTER_NUM__SHIFT 0x0 2309 #define DAGB0_FATAL_ERROR_CNTL__FILTER_NUM_MASK 0x000003FFL 2310 //DAGB0_FATAL_ERROR_CLEAR 2311 #define DAGB0_FATAL_ERROR_CLEAR__CLEAR__SHIFT 0x0 2312 #define DAGB0_FATAL_ERROR_CLEAR__CLEAR_MASK 0x00000001L 2313 //DAGB0_FATAL_ERROR_STATUS0 2314 #define DAGB0_FATAL_ERROR_STATUS0__VALID__SHIFT 0x0 2315 #define DAGB0_FATAL_ERROR_STATUS0__CID__SHIFT 0x1 2316 #define DAGB0_FATAL_ERROR_STATUS0__ADDR_LO__SHIFT 0x6 2317 #define DAGB0_FATAL_ERROR_STATUS0__VALID_MASK 0x00000001L 2318 #define DAGB0_FATAL_ERROR_STATUS0__CID_MASK 0x0000003EL 2319 #define DAGB0_FATAL_ERROR_STATUS0__ADDR_LO_MASK 0xFFFFFFC0L 2320 //DAGB0_FATAL_ERROR_STATUS1 2321 #define DAGB0_FATAL_ERROR_STATUS1__ADDR_HI__SHIFT 0x0 2322 #define DAGB0_FATAL_ERROR_STATUS1__ADDR_HI_MASK 0x0001FFFFL 2323 //DAGB0_FATAL_ERROR_STATUS2 2324 #define DAGB0_FATAL_ERROR_STATUS2__CLI_TAG__SHIFT 0x0 2325 #define DAGB0_FATAL_ERROR_STATUS2__SDP_TAG__SHIFT 0x10 2326 #define DAGB0_FATAL_ERROR_STATUS2__VFID__SHIFT 0x18 2327 #define DAGB0_FATAL_ERROR_STATUS2__VF__SHIFT 0x1c 2328 #define DAGB0_FATAL_ERROR_STATUS2__SPACE__SHIFT 0x1d 2329 #define DAGB0_FATAL_ERROR_STATUS2__IO__SHIFT 0x1e 2330 #define DAGB0_FATAL_ERROR_STATUS2__SIZE__SHIFT 0x1f 2331 #define DAGB0_FATAL_ERROR_STATUS2__CLI_TAG_MASK 0x0000FFFFL 2332 #define DAGB0_FATAL_ERROR_STATUS2__SDP_TAG_MASK 0x00FF0000L 2333 #define DAGB0_FATAL_ERROR_STATUS2__VFID_MASK 0x0F000000L 2334 #define DAGB0_FATAL_ERROR_STATUS2__VF_MASK 0x10000000L 2335 #define DAGB0_FATAL_ERROR_STATUS2__SPACE_MASK 0x20000000L 2336 #define DAGB0_FATAL_ERROR_STATUS2__IO_MASK 0x40000000L 2337 #define DAGB0_FATAL_ERROR_STATUS2__SIZE_MASK 0x80000000L 2338 //DAGB0_FATAL_ERROR_STATUS3 2339 #define DAGB0_FATAL_ERROR_STATUS3__OP__SHIFT 0x6 2340 #define DAGB0_FATAL_ERROR_STATUS3__WRTMZ__SHIFT 0x10 2341 #define DAGB0_FATAL_ERROR_STATUS3__RDTMZ__SHIFT 0x11 2342 #define DAGB0_FATAL_ERROR_STATUS3__SNOOP__SHIFT 0x12 2343 #define DAGB0_FATAL_ERROR_STATUS3__INVAL__SHIFT 0x13 2344 #define DAGB0_FATAL_ERROR_STATUS3__NACK__SHIFT 0x14 2345 #define DAGB0_FATAL_ERROR_STATUS3__RO__SHIFT 0x16 2346 #define DAGB0_FATAL_ERROR_STATUS3__MEMLOG__SHIFT 0x17 2347 #define DAGB0_FATAL_ERROR_STATUS3__INT_FATAL__SHIFT 0x18 2348 #define DAGB0_FATAL_ERROR_STATUS3__EXT_FATAL__SHIFT 0x19 2349 #define DAGB0_FATAL_ERROR_STATUS3__OP_MASK 0x00001FC0L 2350 #define DAGB0_FATAL_ERROR_STATUS3__WRTMZ_MASK 0x00010000L 2351 #define DAGB0_FATAL_ERROR_STATUS3__RDTMZ_MASK 0x00020000L 2352 #define DAGB0_FATAL_ERROR_STATUS3__SNOOP_MASK 0x00040000L 2353 #define DAGB0_FATAL_ERROR_STATUS3__INVAL_MASK 0x00080000L 2354 #define DAGB0_FATAL_ERROR_STATUS3__NACK_MASK 0x00300000L 2355 #define DAGB0_FATAL_ERROR_STATUS3__RO_MASK 0x00400000L 2356 #define DAGB0_FATAL_ERROR_STATUS3__MEMLOG_MASK 0x00800000L 2357 #define DAGB0_FATAL_ERROR_STATUS3__INT_FATAL_MASK 0x01000000L 2358 #define DAGB0_FATAL_ERROR_STATUS3__EXT_FATAL_MASK 0x02000000L 2359 //DAGB0_FATAL_ERROR_STATUS4 2360 #define DAGB0_FATAL_ERROR_STATUS4__PRI__SHIFT 0x0 2361 #define DAGB0_FATAL_ERROR_STATUS4__CHAIN__SHIFT 0x4 2362 #define DAGB0_FATAL_ERROR_STATUS4__FULL__SHIFT 0x5 2363 #define DAGB0_FATAL_ERROR_STATUS4__DROP__SHIFT 0x6 2364 #define DAGB0_FATAL_ERROR_STATUS4__WADDR_PHASE__SHIFT 0x7 2365 #define DAGB0_FATAL_ERROR_STATUS4__NOALLOC__SHIFT 0x8 2366 #define DAGB0_FATAL_ERROR_STATUS4__PRI_MASK 0x0000000FL 2367 #define DAGB0_FATAL_ERROR_STATUS4__CHAIN_MASK 0x00000010L 2368 #define DAGB0_FATAL_ERROR_STATUS4__FULL_MASK 0x00000020L 2369 #define DAGB0_FATAL_ERROR_STATUS4__DROP_MASK 0x00000040L 2370 #define DAGB0_FATAL_ERROR_STATUS4__WADDR_PHASE_MASK 0x00000080L 2371 #define DAGB0_FATAL_ERROR_STATUS4__NOALLOC_MASK 0x00000100L 2372 //DAGB0_SDP_CGTT_CLK_CTRL 2373 #define DAGB0_SDP_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 2374 #define DAGB0_SDP_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x5 2375 #define DAGB0_SDP_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS__SHIFT 0xd 2376 #define DAGB0_SDP_CGTT_CLK_CTRL__LS_DISABLE__SHIFT 0x1e 2377 #define DAGB0_SDP_CGTT_CLK_CTRL__BUSY_OVERRIDE__SHIFT 0x1f 2378 #define DAGB0_SDP_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000001FL 2379 #define DAGB0_SDP_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00001FE0L 2380 #define DAGB0_SDP_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS_MASK 0x1FFFE000L 2381 #define DAGB0_SDP_CGTT_CLK_CTRL__LS_DISABLE_MASK 0x40000000L 2382 #define DAGB0_SDP_CGTT_CLK_CTRL__BUSY_OVERRIDE_MASK 0x80000000L 2383 //DAGB0_SDP_LATENCY_SAMPLING 2384 #define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER0_DRAM__SHIFT 0x0 2385 #define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER1_DRAM__SHIFT 0x1 2386 #define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER0_GMI__SHIFT 0x2 2387 #define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER1_GMI__SHIFT 0x3 2388 #define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER0_IO__SHIFT 0x4 2389 #define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER1_IO__SHIFT 0x5 2390 #define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER0_READ__SHIFT 0x6 2391 #define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER1_READ__SHIFT 0x7 2392 #define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER0_WRITE__SHIFT 0x8 2393 #define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER1_WRITE__SHIFT 0x9 2394 #define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET__SHIFT 0xa 2395 #define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER1_ATOMIC_RET__SHIFT 0xb 2396 #define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER0_ATOMIC_NORET__SHIFT 0xc 2397 #define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER1_ATOMIC_NORET__SHIFT 0xd 2398 #define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER0_VC__SHIFT 0xe 2399 #define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER1_VC__SHIFT 0x16 2400 #define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER0_DRAM_MASK 0x00000001L 2401 #define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER1_DRAM_MASK 0x00000002L 2402 #define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER0_GMI_MASK 0x00000004L 2403 #define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER1_GMI_MASK 0x00000008L 2404 #define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER0_IO_MASK 0x00000010L 2405 #define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER1_IO_MASK 0x00000020L 2406 #define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER0_READ_MASK 0x00000040L 2407 #define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER1_READ_MASK 0x00000080L 2408 #define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER0_WRITE_MASK 0x00000100L 2409 #define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER1_WRITE_MASK 0x00000200L 2410 #define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET_MASK 0x00000400L 2411 #define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER1_ATOMIC_RET_MASK 0x00000800L 2412 #define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER0_ATOMIC_NORET_MASK 0x00001000L 2413 #define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER1_ATOMIC_NORET_MASK 0x00002000L 2414 #define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER0_VC_MASK 0x003FC000L 2415 #define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER1_VC_MASK 0x3FC00000L 2416 //DAGB1_RDCLI0 2417 #define DAGB1_RDCLI0__VIRT_CHAN__SHIFT 0x0 2418 #define DAGB1_RDCLI0__CHECK_TLB_CREDIT__SHIFT 0x3 2419 #define DAGB1_RDCLI0__URG_HIGH__SHIFT 0x4 2420 #define DAGB1_RDCLI0__URG_LOW__SHIFT 0x8 2421 #define DAGB1_RDCLI0__MAX_BW_ENABLE__SHIFT 0xc 2422 #define DAGB1_RDCLI0__MAX_BW__SHIFT 0xd 2423 #define DAGB1_RDCLI0__MIN_BW_ENABLE__SHIFT 0x15 2424 #define DAGB1_RDCLI0__MIN_BW__SHIFT 0x16 2425 #define DAGB1_RDCLI0__OSD_LIMITER_ENABLE__SHIFT 0x19 2426 #define DAGB1_RDCLI0__MAX_OSD__SHIFT 0x1a 2427 #define DAGB1_RDCLI0__VIRT_CHAN_MASK 0x00000007L 2428 #define DAGB1_RDCLI0__CHECK_TLB_CREDIT_MASK 0x00000008L 2429 #define DAGB1_RDCLI0__URG_HIGH_MASK 0x000000F0L 2430 #define DAGB1_RDCLI0__URG_LOW_MASK 0x00000F00L 2431 #define DAGB1_RDCLI0__MAX_BW_ENABLE_MASK 0x00001000L 2432 #define DAGB1_RDCLI0__MAX_BW_MASK 0x001FE000L 2433 #define DAGB1_RDCLI0__MIN_BW_ENABLE_MASK 0x00200000L 2434 #define DAGB1_RDCLI0__MIN_BW_MASK 0x01C00000L 2435 #define DAGB1_RDCLI0__OSD_LIMITER_ENABLE_MASK 0x02000000L 2436 #define DAGB1_RDCLI0__MAX_OSD_MASK 0xFC000000L 2437 //DAGB1_RDCLI1 2438 #define DAGB1_RDCLI1__VIRT_CHAN__SHIFT 0x0 2439 #define DAGB1_RDCLI1__CHECK_TLB_CREDIT__SHIFT 0x3 2440 #define DAGB1_RDCLI1__URG_HIGH__SHIFT 0x4 2441 #define DAGB1_RDCLI1__URG_LOW__SHIFT 0x8 2442 #define DAGB1_RDCLI1__MAX_BW_ENABLE__SHIFT 0xc 2443 #define DAGB1_RDCLI1__MAX_BW__SHIFT 0xd 2444 #define DAGB1_RDCLI1__MIN_BW_ENABLE__SHIFT 0x15 2445 #define DAGB1_RDCLI1__MIN_BW__SHIFT 0x16 2446 #define DAGB1_RDCLI1__OSD_LIMITER_ENABLE__SHIFT 0x19 2447 #define DAGB1_RDCLI1__MAX_OSD__SHIFT 0x1a 2448 #define DAGB1_RDCLI1__VIRT_CHAN_MASK 0x00000007L 2449 #define DAGB1_RDCLI1__CHECK_TLB_CREDIT_MASK 0x00000008L 2450 #define DAGB1_RDCLI1__URG_HIGH_MASK 0x000000F0L 2451 #define DAGB1_RDCLI1__URG_LOW_MASK 0x00000F00L 2452 #define DAGB1_RDCLI1__MAX_BW_ENABLE_MASK 0x00001000L 2453 #define DAGB1_RDCLI1__MAX_BW_MASK 0x001FE000L 2454 #define DAGB1_RDCLI1__MIN_BW_ENABLE_MASK 0x00200000L 2455 #define DAGB1_RDCLI1__MIN_BW_MASK 0x01C00000L 2456 #define DAGB1_RDCLI1__OSD_LIMITER_ENABLE_MASK 0x02000000L 2457 #define DAGB1_RDCLI1__MAX_OSD_MASK 0xFC000000L 2458 //DAGB1_RDCLI2 2459 #define DAGB1_RDCLI2__VIRT_CHAN__SHIFT 0x0 2460 #define DAGB1_RDCLI2__CHECK_TLB_CREDIT__SHIFT 0x3 2461 #define DAGB1_RDCLI2__URG_HIGH__SHIFT 0x4 2462 #define DAGB1_RDCLI2__URG_LOW__SHIFT 0x8 2463 #define DAGB1_RDCLI2__MAX_BW_ENABLE__SHIFT 0xc 2464 #define DAGB1_RDCLI2__MAX_BW__SHIFT 0xd 2465 #define DAGB1_RDCLI2__MIN_BW_ENABLE__SHIFT 0x15 2466 #define DAGB1_RDCLI2__MIN_BW__SHIFT 0x16 2467 #define DAGB1_RDCLI2__OSD_LIMITER_ENABLE__SHIFT 0x19 2468 #define DAGB1_RDCLI2__MAX_OSD__SHIFT 0x1a 2469 #define DAGB1_RDCLI2__VIRT_CHAN_MASK 0x00000007L 2470 #define DAGB1_RDCLI2__CHECK_TLB_CREDIT_MASK 0x00000008L 2471 #define DAGB1_RDCLI2__URG_HIGH_MASK 0x000000F0L 2472 #define DAGB1_RDCLI2__URG_LOW_MASK 0x00000F00L 2473 #define DAGB1_RDCLI2__MAX_BW_ENABLE_MASK 0x00001000L 2474 #define DAGB1_RDCLI2__MAX_BW_MASK 0x001FE000L 2475 #define DAGB1_RDCLI2__MIN_BW_ENABLE_MASK 0x00200000L 2476 #define DAGB1_RDCLI2__MIN_BW_MASK 0x01C00000L 2477 #define DAGB1_RDCLI2__OSD_LIMITER_ENABLE_MASK 0x02000000L 2478 #define DAGB1_RDCLI2__MAX_OSD_MASK 0xFC000000L 2479 //DAGB1_RDCLI3 2480 #define DAGB1_RDCLI3__VIRT_CHAN__SHIFT 0x0 2481 #define DAGB1_RDCLI3__CHECK_TLB_CREDIT__SHIFT 0x3 2482 #define DAGB1_RDCLI3__URG_HIGH__SHIFT 0x4 2483 #define DAGB1_RDCLI3__URG_LOW__SHIFT 0x8 2484 #define DAGB1_RDCLI3__MAX_BW_ENABLE__SHIFT 0xc 2485 #define DAGB1_RDCLI3__MAX_BW__SHIFT 0xd 2486 #define DAGB1_RDCLI3__MIN_BW_ENABLE__SHIFT 0x15 2487 #define DAGB1_RDCLI3__MIN_BW__SHIFT 0x16 2488 #define DAGB1_RDCLI3__OSD_LIMITER_ENABLE__SHIFT 0x19 2489 #define DAGB1_RDCLI3__MAX_OSD__SHIFT 0x1a 2490 #define DAGB1_RDCLI3__VIRT_CHAN_MASK 0x00000007L 2491 #define DAGB1_RDCLI3__CHECK_TLB_CREDIT_MASK 0x00000008L 2492 #define DAGB1_RDCLI3__URG_HIGH_MASK 0x000000F0L 2493 #define DAGB1_RDCLI3__URG_LOW_MASK 0x00000F00L 2494 #define DAGB1_RDCLI3__MAX_BW_ENABLE_MASK 0x00001000L 2495 #define DAGB1_RDCLI3__MAX_BW_MASK 0x001FE000L 2496 #define DAGB1_RDCLI3__MIN_BW_ENABLE_MASK 0x00200000L 2497 #define DAGB1_RDCLI3__MIN_BW_MASK 0x01C00000L 2498 #define DAGB1_RDCLI3__OSD_LIMITER_ENABLE_MASK 0x02000000L 2499 #define DAGB1_RDCLI3__MAX_OSD_MASK 0xFC000000L 2500 //DAGB1_RDCLI4 2501 #define DAGB1_RDCLI4__VIRT_CHAN__SHIFT 0x0 2502 #define DAGB1_RDCLI4__CHECK_TLB_CREDIT__SHIFT 0x3 2503 #define DAGB1_RDCLI4__URG_HIGH__SHIFT 0x4 2504 #define DAGB1_RDCLI4__URG_LOW__SHIFT 0x8 2505 #define DAGB1_RDCLI4__MAX_BW_ENABLE__SHIFT 0xc 2506 #define DAGB1_RDCLI4__MAX_BW__SHIFT 0xd 2507 #define DAGB1_RDCLI4__MIN_BW_ENABLE__SHIFT 0x15 2508 #define DAGB1_RDCLI4__MIN_BW__SHIFT 0x16 2509 #define DAGB1_RDCLI4__OSD_LIMITER_ENABLE__SHIFT 0x19 2510 #define DAGB1_RDCLI4__MAX_OSD__SHIFT 0x1a 2511 #define DAGB1_RDCLI4__VIRT_CHAN_MASK 0x00000007L 2512 #define DAGB1_RDCLI4__CHECK_TLB_CREDIT_MASK 0x00000008L 2513 #define DAGB1_RDCLI4__URG_HIGH_MASK 0x000000F0L 2514 #define DAGB1_RDCLI4__URG_LOW_MASK 0x00000F00L 2515 #define DAGB1_RDCLI4__MAX_BW_ENABLE_MASK 0x00001000L 2516 #define DAGB1_RDCLI4__MAX_BW_MASK 0x001FE000L 2517 #define DAGB1_RDCLI4__MIN_BW_ENABLE_MASK 0x00200000L 2518 #define DAGB1_RDCLI4__MIN_BW_MASK 0x01C00000L 2519 #define DAGB1_RDCLI4__OSD_LIMITER_ENABLE_MASK 0x02000000L 2520 #define DAGB1_RDCLI4__MAX_OSD_MASK 0xFC000000L 2521 //DAGB1_RDCLI5 2522 #define DAGB1_RDCLI5__VIRT_CHAN__SHIFT 0x0 2523 #define DAGB1_RDCLI5__CHECK_TLB_CREDIT__SHIFT 0x3 2524 #define DAGB1_RDCLI5__URG_HIGH__SHIFT 0x4 2525 #define DAGB1_RDCLI5__URG_LOW__SHIFT 0x8 2526 #define DAGB1_RDCLI5__MAX_BW_ENABLE__SHIFT 0xc 2527 #define DAGB1_RDCLI5__MAX_BW__SHIFT 0xd 2528 #define DAGB1_RDCLI5__MIN_BW_ENABLE__SHIFT 0x15 2529 #define DAGB1_RDCLI5__MIN_BW__SHIFT 0x16 2530 #define DAGB1_RDCLI5__OSD_LIMITER_ENABLE__SHIFT 0x19 2531 #define DAGB1_RDCLI5__MAX_OSD__SHIFT 0x1a 2532 #define DAGB1_RDCLI5__VIRT_CHAN_MASK 0x00000007L 2533 #define DAGB1_RDCLI5__CHECK_TLB_CREDIT_MASK 0x00000008L 2534 #define DAGB1_RDCLI5__URG_HIGH_MASK 0x000000F0L 2535 #define DAGB1_RDCLI5__URG_LOW_MASK 0x00000F00L 2536 #define DAGB1_RDCLI5__MAX_BW_ENABLE_MASK 0x00001000L 2537 #define DAGB1_RDCLI5__MAX_BW_MASK 0x001FE000L 2538 #define DAGB1_RDCLI5__MIN_BW_ENABLE_MASK 0x00200000L 2539 #define DAGB1_RDCLI5__MIN_BW_MASK 0x01C00000L 2540 #define DAGB1_RDCLI5__OSD_LIMITER_ENABLE_MASK 0x02000000L 2541 #define DAGB1_RDCLI5__MAX_OSD_MASK 0xFC000000L 2542 //DAGB1_RDCLI6 2543 #define DAGB1_RDCLI6__VIRT_CHAN__SHIFT 0x0 2544 #define DAGB1_RDCLI6__CHECK_TLB_CREDIT__SHIFT 0x3 2545 #define DAGB1_RDCLI6__URG_HIGH__SHIFT 0x4 2546 #define DAGB1_RDCLI6__URG_LOW__SHIFT 0x8 2547 #define DAGB1_RDCLI6__MAX_BW_ENABLE__SHIFT 0xc 2548 #define DAGB1_RDCLI6__MAX_BW__SHIFT 0xd 2549 #define DAGB1_RDCLI6__MIN_BW_ENABLE__SHIFT 0x15 2550 #define DAGB1_RDCLI6__MIN_BW__SHIFT 0x16 2551 #define DAGB1_RDCLI6__OSD_LIMITER_ENABLE__SHIFT 0x19 2552 #define DAGB1_RDCLI6__MAX_OSD__SHIFT 0x1a 2553 #define DAGB1_RDCLI6__VIRT_CHAN_MASK 0x00000007L 2554 #define DAGB1_RDCLI6__CHECK_TLB_CREDIT_MASK 0x00000008L 2555 #define DAGB1_RDCLI6__URG_HIGH_MASK 0x000000F0L 2556 #define DAGB1_RDCLI6__URG_LOW_MASK 0x00000F00L 2557 #define DAGB1_RDCLI6__MAX_BW_ENABLE_MASK 0x00001000L 2558 #define DAGB1_RDCLI6__MAX_BW_MASK 0x001FE000L 2559 #define DAGB1_RDCLI6__MIN_BW_ENABLE_MASK 0x00200000L 2560 #define DAGB1_RDCLI6__MIN_BW_MASK 0x01C00000L 2561 #define DAGB1_RDCLI6__OSD_LIMITER_ENABLE_MASK 0x02000000L 2562 #define DAGB1_RDCLI6__MAX_OSD_MASK 0xFC000000L 2563 //DAGB1_RDCLI7 2564 #define DAGB1_RDCLI7__VIRT_CHAN__SHIFT 0x0 2565 #define DAGB1_RDCLI7__CHECK_TLB_CREDIT__SHIFT 0x3 2566 #define DAGB1_RDCLI7__URG_HIGH__SHIFT 0x4 2567 #define DAGB1_RDCLI7__URG_LOW__SHIFT 0x8 2568 #define DAGB1_RDCLI7__MAX_BW_ENABLE__SHIFT 0xc 2569 #define DAGB1_RDCLI7__MAX_BW__SHIFT 0xd 2570 #define DAGB1_RDCLI7__MIN_BW_ENABLE__SHIFT 0x15 2571 #define DAGB1_RDCLI7__MIN_BW__SHIFT 0x16 2572 #define DAGB1_RDCLI7__OSD_LIMITER_ENABLE__SHIFT 0x19 2573 #define DAGB1_RDCLI7__MAX_OSD__SHIFT 0x1a 2574 #define DAGB1_RDCLI7__VIRT_CHAN_MASK 0x00000007L 2575 #define DAGB1_RDCLI7__CHECK_TLB_CREDIT_MASK 0x00000008L 2576 #define DAGB1_RDCLI7__URG_HIGH_MASK 0x000000F0L 2577 #define DAGB1_RDCLI7__URG_LOW_MASK 0x00000F00L 2578 #define DAGB1_RDCLI7__MAX_BW_ENABLE_MASK 0x00001000L 2579 #define DAGB1_RDCLI7__MAX_BW_MASK 0x001FE000L 2580 #define DAGB1_RDCLI7__MIN_BW_ENABLE_MASK 0x00200000L 2581 #define DAGB1_RDCLI7__MIN_BW_MASK 0x01C00000L 2582 #define DAGB1_RDCLI7__OSD_LIMITER_ENABLE_MASK 0x02000000L 2583 #define DAGB1_RDCLI7__MAX_OSD_MASK 0xFC000000L 2584 //DAGB1_RDCLI8 2585 #define DAGB1_RDCLI8__VIRT_CHAN__SHIFT 0x0 2586 #define DAGB1_RDCLI8__CHECK_TLB_CREDIT__SHIFT 0x3 2587 #define DAGB1_RDCLI8__URG_HIGH__SHIFT 0x4 2588 #define DAGB1_RDCLI8__URG_LOW__SHIFT 0x8 2589 #define DAGB1_RDCLI8__MAX_BW_ENABLE__SHIFT 0xc 2590 #define DAGB1_RDCLI8__MAX_BW__SHIFT 0xd 2591 #define DAGB1_RDCLI8__MIN_BW_ENABLE__SHIFT 0x15 2592 #define DAGB1_RDCLI8__MIN_BW__SHIFT 0x16 2593 #define DAGB1_RDCLI8__OSD_LIMITER_ENABLE__SHIFT 0x19 2594 #define DAGB1_RDCLI8__MAX_OSD__SHIFT 0x1a 2595 #define DAGB1_RDCLI8__VIRT_CHAN_MASK 0x00000007L 2596 #define DAGB1_RDCLI8__CHECK_TLB_CREDIT_MASK 0x00000008L 2597 #define DAGB1_RDCLI8__URG_HIGH_MASK 0x000000F0L 2598 #define DAGB1_RDCLI8__URG_LOW_MASK 0x00000F00L 2599 #define DAGB1_RDCLI8__MAX_BW_ENABLE_MASK 0x00001000L 2600 #define DAGB1_RDCLI8__MAX_BW_MASK 0x001FE000L 2601 #define DAGB1_RDCLI8__MIN_BW_ENABLE_MASK 0x00200000L 2602 #define DAGB1_RDCLI8__MIN_BW_MASK 0x01C00000L 2603 #define DAGB1_RDCLI8__OSD_LIMITER_ENABLE_MASK 0x02000000L 2604 #define DAGB1_RDCLI8__MAX_OSD_MASK 0xFC000000L 2605 //DAGB1_RDCLI9 2606 #define DAGB1_RDCLI9__VIRT_CHAN__SHIFT 0x0 2607 #define DAGB1_RDCLI9__CHECK_TLB_CREDIT__SHIFT 0x3 2608 #define DAGB1_RDCLI9__URG_HIGH__SHIFT 0x4 2609 #define DAGB1_RDCLI9__URG_LOW__SHIFT 0x8 2610 #define DAGB1_RDCLI9__MAX_BW_ENABLE__SHIFT 0xc 2611 #define DAGB1_RDCLI9__MAX_BW__SHIFT 0xd 2612 #define DAGB1_RDCLI9__MIN_BW_ENABLE__SHIFT 0x15 2613 #define DAGB1_RDCLI9__MIN_BW__SHIFT 0x16 2614 #define DAGB1_RDCLI9__OSD_LIMITER_ENABLE__SHIFT 0x19 2615 #define DAGB1_RDCLI9__MAX_OSD__SHIFT 0x1a 2616 #define DAGB1_RDCLI9__VIRT_CHAN_MASK 0x00000007L 2617 #define DAGB1_RDCLI9__CHECK_TLB_CREDIT_MASK 0x00000008L 2618 #define DAGB1_RDCLI9__URG_HIGH_MASK 0x000000F0L 2619 #define DAGB1_RDCLI9__URG_LOW_MASK 0x00000F00L 2620 #define DAGB1_RDCLI9__MAX_BW_ENABLE_MASK 0x00001000L 2621 #define DAGB1_RDCLI9__MAX_BW_MASK 0x001FE000L 2622 #define DAGB1_RDCLI9__MIN_BW_ENABLE_MASK 0x00200000L 2623 #define DAGB1_RDCLI9__MIN_BW_MASK 0x01C00000L 2624 #define DAGB1_RDCLI9__OSD_LIMITER_ENABLE_MASK 0x02000000L 2625 #define DAGB1_RDCLI9__MAX_OSD_MASK 0xFC000000L 2626 //DAGB1_RDCLI10 2627 #define DAGB1_RDCLI10__VIRT_CHAN__SHIFT 0x0 2628 #define DAGB1_RDCLI10__CHECK_TLB_CREDIT__SHIFT 0x3 2629 #define DAGB1_RDCLI10__URG_HIGH__SHIFT 0x4 2630 #define DAGB1_RDCLI10__URG_LOW__SHIFT 0x8 2631 #define DAGB1_RDCLI10__MAX_BW_ENABLE__SHIFT 0xc 2632 #define DAGB1_RDCLI10__MAX_BW__SHIFT 0xd 2633 #define DAGB1_RDCLI10__MIN_BW_ENABLE__SHIFT 0x15 2634 #define DAGB1_RDCLI10__MIN_BW__SHIFT 0x16 2635 #define DAGB1_RDCLI10__OSD_LIMITER_ENABLE__SHIFT 0x19 2636 #define DAGB1_RDCLI10__MAX_OSD__SHIFT 0x1a 2637 #define DAGB1_RDCLI10__VIRT_CHAN_MASK 0x00000007L 2638 #define DAGB1_RDCLI10__CHECK_TLB_CREDIT_MASK 0x00000008L 2639 #define DAGB1_RDCLI10__URG_HIGH_MASK 0x000000F0L 2640 #define DAGB1_RDCLI10__URG_LOW_MASK 0x00000F00L 2641 #define DAGB1_RDCLI10__MAX_BW_ENABLE_MASK 0x00001000L 2642 #define DAGB1_RDCLI10__MAX_BW_MASK 0x001FE000L 2643 #define DAGB1_RDCLI10__MIN_BW_ENABLE_MASK 0x00200000L 2644 #define DAGB1_RDCLI10__MIN_BW_MASK 0x01C00000L 2645 #define DAGB1_RDCLI10__OSD_LIMITER_ENABLE_MASK 0x02000000L 2646 #define DAGB1_RDCLI10__MAX_OSD_MASK 0xFC000000L 2647 //DAGB1_RDCLI11 2648 #define DAGB1_RDCLI11__VIRT_CHAN__SHIFT 0x0 2649 #define DAGB1_RDCLI11__CHECK_TLB_CREDIT__SHIFT 0x3 2650 #define DAGB1_RDCLI11__URG_HIGH__SHIFT 0x4 2651 #define DAGB1_RDCLI11__URG_LOW__SHIFT 0x8 2652 #define DAGB1_RDCLI11__MAX_BW_ENABLE__SHIFT 0xc 2653 #define DAGB1_RDCLI11__MAX_BW__SHIFT 0xd 2654 #define DAGB1_RDCLI11__MIN_BW_ENABLE__SHIFT 0x15 2655 #define DAGB1_RDCLI11__MIN_BW__SHIFT 0x16 2656 #define DAGB1_RDCLI11__OSD_LIMITER_ENABLE__SHIFT 0x19 2657 #define DAGB1_RDCLI11__MAX_OSD__SHIFT 0x1a 2658 #define DAGB1_RDCLI11__VIRT_CHAN_MASK 0x00000007L 2659 #define DAGB1_RDCLI11__CHECK_TLB_CREDIT_MASK 0x00000008L 2660 #define DAGB1_RDCLI11__URG_HIGH_MASK 0x000000F0L 2661 #define DAGB1_RDCLI11__URG_LOW_MASK 0x00000F00L 2662 #define DAGB1_RDCLI11__MAX_BW_ENABLE_MASK 0x00001000L 2663 #define DAGB1_RDCLI11__MAX_BW_MASK 0x001FE000L 2664 #define DAGB1_RDCLI11__MIN_BW_ENABLE_MASK 0x00200000L 2665 #define DAGB1_RDCLI11__MIN_BW_MASK 0x01C00000L 2666 #define DAGB1_RDCLI11__OSD_LIMITER_ENABLE_MASK 0x02000000L 2667 #define DAGB1_RDCLI11__MAX_OSD_MASK 0xFC000000L 2668 //DAGB1_RDCLI12 2669 #define DAGB1_RDCLI12__VIRT_CHAN__SHIFT 0x0 2670 #define DAGB1_RDCLI12__CHECK_TLB_CREDIT__SHIFT 0x3 2671 #define DAGB1_RDCLI12__URG_HIGH__SHIFT 0x4 2672 #define DAGB1_RDCLI12__URG_LOW__SHIFT 0x8 2673 #define DAGB1_RDCLI12__MAX_BW_ENABLE__SHIFT 0xc 2674 #define DAGB1_RDCLI12__MAX_BW__SHIFT 0xd 2675 #define DAGB1_RDCLI12__MIN_BW_ENABLE__SHIFT 0x15 2676 #define DAGB1_RDCLI12__MIN_BW__SHIFT 0x16 2677 #define DAGB1_RDCLI12__OSD_LIMITER_ENABLE__SHIFT 0x19 2678 #define DAGB1_RDCLI12__MAX_OSD__SHIFT 0x1a 2679 #define DAGB1_RDCLI12__VIRT_CHAN_MASK 0x00000007L 2680 #define DAGB1_RDCLI12__CHECK_TLB_CREDIT_MASK 0x00000008L 2681 #define DAGB1_RDCLI12__URG_HIGH_MASK 0x000000F0L 2682 #define DAGB1_RDCLI12__URG_LOW_MASK 0x00000F00L 2683 #define DAGB1_RDCLI12__MAX_BW_ENABLE_MASK 0x00001000L 2684 #define DAGB1_RDCLI12__MAX_BW_MASK 0x001FE000L 2685 #define DAGB1_RDCLI12__MIN_BW_ENABLE_MASK 0x00200000L 2686 #define DAGB1_RDCLI12__MIN_BW_MASK 0x01C00000L 2687 #define DAGB1_RDCLI12__OSD_LIMITER_ENABLE_MASK 0x02000000L 2688 #define DAGB1_RDCLI12__MAX_OSD_MASK 0xFC000000L 2689 //DAGB1_RDCLI13 2690 #define DAGB1_RDCLI13__VIRT_CHAN__SHIFT 0x0 2691 #define DAGB1_RDCLI13__CHECK_TLB_CREDIT__SHIFT 0x3 2692 #define DAGB1_RDCLI13__URG_HIGH__SHIFT 0x4 2693 #define DAGB1_RDCLI13__URG_LOW__SHIFT 0x8 2694 #define DAGB1_RDCLI13__MAX_BW_ENABLE__SHIFT 0xc 2695 #define DAGB1_RDCLI13__MAX_BW__SHIFT 0xd 2696 #define DAGB1_RDCLI13__MIN_BW_ENABLE__SHIFT 0x15 2697 #define DAGB1_RDCLI13__MIN_BW__SHIFT 0x16 2698 #define DAGB1_RDCLI13__OSD_LIMITER_ENABLE__SHIFT 0x19 2699 #define DAGB1_RDCLI13__MAX_OSD__SHIFT 0x1a 2700 #define DAGB1_RDCLI13__VIRT_CHAN_MASK 0x00000007L 2701 #define DAGB1_RDCLI13__CHECK_TLB_CREDIT_MASK 0x00000008L 2702 #define DAGB1_RDCLI13__URG_HIGH_MASK 0x000000F0L 2703 #define DAGB1_RDCLI13__URG_LOW_MASK 0x00000F00L 2704 #define DAGB1_RDCLI13__MAX_BW_ENABLE_MASK 0x00001000L 2705 #define DAGB1_RDCLI13__MAX_BW_MASK 0x001FE000L 2706 #define DAGB1_RDCLI13__MIN_BW_ENABLE_MASK 0x00200000L 2707 #define DAGB1_RDCLI13__MIN_BW_MASK 0x01C00000L 2708 #define DAGB1_RDCLI13__OSD_LIMITER_ENABLE_MASK 0x02000000L 2709 #define DAGB1_RDCLI13__MAX_OSD_MASK 0xFC000000L 2710 //DAGB1_RDCLI14 2711 #define DAGB1_RDCLI14__VIRT_CHAN__SHIFT 0x0 2712 #define DAGB1_RDCLI14__CHECK_TLB_CREDIT__SHIFT 0x3 2713 #define DAGB1_RDCLI14__URG_HIGH__SHIFT 0x4 2714 #define DAGB1_RDCLI14__URG_LOW__SHIFT 0x8 2715 #define DAGB1_RDCLI14__MAX_BW_ENABLE__SHIFT 0xc 2716 #define DAGB1_RDCLI14__MAX_BW__SHIFT 0xd 2717 #define DAGB1_RDCLI14__MIN_BW_ENABLE__SHIFT 0x15 2718 #define DAGB1_RDCLI14__MIN_BW__SHIFT 0x16 2719 #define DAGB1_RDCLI14__OSD_LIMITER_ENABLE__SHIFT 0x19 2720 #define DAGB1_RDCLI14__MAX_OSD__SHIFT 0x1a 2721 #define DAGB1_RDCLI14__VIRT_CHAN_MASK 0x00000007L 2722 #define DAGB1_RDCLI14__CHECK_TLB_CREDIT_MASK 0x00000008L 2723 #define DAGB1_RDCLI14__URG_HIGH_MASK 0x000000F0L 2724 #define DAGB1_RDCLI14__URG_LOW_MASK 0x00000F00L 2725 #define DAGB1_RDCLI14__MAX_BW_ENABLE_MASK 0x00001000L 2726 #define DAGB1_RDCLI14__MAX_BW_MASK 0x001FE000L 2727 #define DAGB1_RDCLI14__MIN_BW_ENABLE_MASK 0x00200000L 2728 #define DAGB1_RDCLI14__MIN_BW_MASK 0x01C00000L 2729 #define DAGB1_RDCLI14__OSD_LIMITER_ENABLE_MASK 0x02000000L 2730 #define DAGB1_RDCLI14__MAX_OSD_MASK 0xFC000000L 2731 //DAGB1_RDCLI15 2732 #define DAGB1_RDCLI15__VIRT_CHAN__SHIFT 0x0 2733 #define DAGB1_RDCLI15__CHECK_TLB_CREDIT__SHIFT 0x3 2734 #define DAGB1_RDCLI15__URG_HIGH__SHIFT 0x4 2735 #define DAGB1_RDCLI15__URG_LOW__SHIFT 0x8 2736 #define DAGB1_RDCLI15__MAX_BW_ENABLE__SHIFT 0xc 2737 #define DAGB1_RDCLI15__MAX_BW__SHIFT 0xd 2738 #define DAGB1_RDCLI15__MIN_BW_ENABLE__SHIFT 0x15 2739 #define DAGB1_RDCLI15__MIN_BW__SHIFT 0x16 2740 #define DAGB1_RDCLI15__OSD_LIMITER_ENABLE__SHIFT 0x19 2741 #define DAGB1_RDCLI15__MAX_OSD__SHIFT 0x1a 2742 #define DAGB1_RDCLI15__VIRT_CHAN_MASK 0x00000007L 2743 #define DAGB1_RDCLI15__CHECK_TLB_CREDIT_MASK 0x00000008L 2744 #define DAGB1_RDCLI15__URG_HIGH_MASK 0x000000F0L 2745 #define DAGB1_RDCLI15__URG_LOW_MASK 0x00000F00L 2746 #define DAGB1_RDCLI15__MAX_BW_ENABLE_MASK 0x00001000L 2747 #define DAGB1_RDCLI15__MAX_BW_MASK 0x001FE000L 2748 #define DAGB1_RDCLI15__MIN_BW_ENABLE_MASK 0x00200000L 2749 #define DAGB1_RDCLI15__MIN_BW_MASK 0x01C00000L 2750 #define DAGB1_RDCLI15__OSD_LIMITER_ENABLE_MASK 0x02000000L 2751 #define DAGB1_RDCLI15__MAX_OSD_MASK 0xFC000000L 2752 //DAGB1_RDCLI16 2753 #define DAGB1_RDCLI16__VIRT_CHAN__SHIFT 0x0 2754 #define DAGB1_RDCLI16__CHECK_TLB_CREDIT__SHIFT 0x3 2755 #define DAGB1_RDCLI16__URG_HIGH__SHIFT 0x4 2756 #define DAGB1_RDCLI16__URG_LOW__SHIFT 0x8 2757 #define DAGB1_RDCLI16__MAX_BW_ENABLE__SHIFT 0xc 2758 #define DAGB1_RDCLI16__MAX_BW__SHIFT 0xd 2759 #define DAGB1_RDCLI16__MIN_BW_ENABLE__SHIFT 0x15 2760 #define DAGB1_RDCLI16__MIN_BW__SHIFT 0x16 2761 #define DAGB1_RDCLI16__OSD_LIMITER_ENABLE__SHIFT 0x19 2762 #define DAGB1_RDCLI16__MAX_OSD__SHIFT 0x1a 2763 #define DAGB1_RDCLI16__VIRT_CHAN_MASK 0x00000007L 2764 #define DAGB1_RDCLI16__CHECK_TLB_CREDIT_MASK 0x00000008L 2765 #define DAGB1_RDCLI16__URG_HIGH_MASK 0x000000F0L 2766 #define DAGB1_RDCLI16__URG_LOW_MASK 0x00000F00L 2767 #define DAGB1_RDCLI16__MAX_BW_ENABLE_MASK 0x00001000L 2768 #define DAGB1_RDCLI16__MAX_BW_MASK 0x001FE000L 2769 #define DAGB1_RDCLI16__MIN_BW_ENABLE_MASK 0x00200000L 2770 #define DAGB1_RDCLI16__MIN_BW_MASK 0x01C00000L 2771 #define DAGB1_RDCLI16__OSD_LIMITER_ENABLE_MASK 0x02000000L 2772 #define DAGB1_RDCLI16__MAX_OSD_MASK 0xFC000000L 2773 //DAGB1_RDCLI17 2774 #define DAGB1_RDCLI17__VIRT_CHAN__SHIFT 0x0 2775 #define DAGB1_RDCLI17__CHECK_TLB_CREDIT__SHIFT 0x3 2776 #define DAGB1_RDCLI17__URG_HIGH__SHIFT 0x4 2777 #define DAGB1_RDCLI17__URG_LOW__SHIFT 0x8 2778 #define DAGB1_RDCLI17__MAX_BW_ENABLE__SHIFT 0xc 2779 #define DAGB1_RDCLI17__MAX_BW__SHIFT 0xd 2780 #define DAGB1_RDCLI17__MIN_BW_ENABLE__SHIFT 0x15 2781 #define DAGB1_RDCLI17__MIN_BW__SHIFT 0x16 2782 #define DAGB1_RDCLI17__OSD_LIMITER_ENABLE__SHIFT 0x19 2783 #define DAGB1_RDCLI17__MAX_OSD__SHIFT 0x1a 2784 #define DAGB1_RDCLI17__VIRT_CHAN_MASK 0x00000007L 2785 #define DAGB1_RDCLI17__CHECK_TLB_CREDIT_MASK 0x00000008L 2786 #define DAGB1_RDCLI17__URG_HIGH_MASK 0x000000F0L 2787 #define DAGB1_RDCLI17__URG_LOW_MASK 0x00000F00L 2788 #define DAGB1_RDCLI17__MAX_BW_ENABLE_MASK 0x00001000L 2789 #define DAGB1_RDCLI17__MAX_BW_MASK 0x001FE000L 2790 #define DAGB1_RDCLI17__MIN_BW_ENABLE_MASK 0x00200000L 2791 #define DAGB1_RDCLI17__MIN_BW_MASK 0x01C00000L 2792 #define DAGB1_RDCLI17__OSD_LIMITER_ENABLE_MASK 0x02000000L 2793 #define DAGB1_RDCLI17__MAX_OSD_MASK 0xFC000000L 2794 //DAGB1_RDCLI18 2795 #define DAGB1_RDCLI18__VIRT_CHAN__SHIFT 0x0 2796 #define DAGB1_RDCLI18__CHECK_TLB_CREDIT__SHIFT 0x3 2797 #define DAGB1_RDCLI18__URG_HIGH__SHIFT 0x4 2798 #define DAGB1_RDCLI18__URG_LOW__SHIFT 0x8 2799 #define DAGB1_RDCLI18__MAX_BW_ENABLE__SHIFT 0xc 2800 #define DAGB1_RDCLI18__MAX_BW__SHIFT 0xd 2801 #define DAGB1_RDCLI18__MIN_BW_ENABLE__SHIFT 0x15 2802 #define DAGB1_RDCLI18__MIN_BW__SHIFT 0x16 2803 #define DAGB1_RDCLI18__OSD_LIMITER_ENABLE__SHIFT 0x19 2804 #define DAGB1_RDCLI18__MAX_OSD__SHIFT 0x1a 2805 #define DAGB1_RDCLI18__VIRT_CHAN_MASK 0x00000007L 2806 #define DAGB1_RDCLI18__CHECK_TLB_CREDIT_MASK 0x00000008L 2807 #define DAGB1_RDCLI18__URG_HIGH_MASK 0x000000F0L 2808 #define DAGB1_RDCLI18__URG_LOW_MASK 0x00000F00L 2809 #define DAGB1_RDCLI18__MAX_BW_ENABLE_MASK 0x00001000L 2810 #define DAGB1_RDCLI18__MAX_BW_MASK 0x001FE000L 2811 #define DAGB1_RDCLI18__MIN_BW_ENABLE_MASK 0x00200000L 2812 #define DAGB1_RDCLI18__MIN_BW_MASK 0x01C00000L 2813 #define DAGB1_RDCLI18__OSD_LIMITER_ENABLE_MASK 0x02000000L 2814 #define DAGB1_RDCLI18__MAX_OSD_MASK 0xFC000000L 2815 //DAGB1_RDCLI19 2816 #define DAGB1_RDCLI19__VIRT_CHAN__SHIFT 0x0 2817 #define DAGB1_RDCLI19__CHECK_TLB_CREDIT__SHIFT 0x3 2818 #define DAGB1_RDCLI19__URG_HIGH__SHIFT 0x4 2819 #define DAGB1_RDCLI19__URG_LOW__SHIFT 0x8 2820 #define DAGB1_RDCLI19__MAX_BW_ENABLE__SHIFT 0xc 2821 #define DAGB1_RDCLI19__MAX_BW__SHIFT 0xd 2822 #define DAGB1_RDCLI19__MIN_BW_ENABLE__SHIFT 0x15 2823 #define DAGB1_RDCLI19__MIN_BW__SHIFT 0x16 2824 #define DAGB1_RDCLI19__OSD_LIMITER_ENABLE__SHIFT 0x19 2825 #define DAGB1_RDCLI19__MAX_OSD__SHIFT 0x1a 2826 #define DAGB1_RDCLI19__VIRT_CHAN_MASK 0x00000007L 2827 #define DAGB1_RDCLI19__CHECK_TLB_CREDIT_MASK 0x00000008L 2828 #define DAGB1_RDCLI19__URG_HIGH_MASK 0x000000F0L 2829 #define DAGB1_RDCLI19__URG_LOW_MASK 0x00000F00L 2830 #define DAGB1_RDCLI19__MAX_BW_ENABLE_MASK 0x00001000L 2831 #define DAGB1_RDCLI19__MAX_BW_MASK 0x001FE000L 2832 #define DAGB1_RDCLI19__MIN_BW_ENABLE_MASK 0x00200000L 2833 #define DAGB1_RDCLI19__MIN_BW_MASK 0x01C00000L 2834 #define DAGB1_RDCLI19__OSD_LIMITER_ENABLE_MASK 0x02000000L 2835 #define DAGB1_RDCLI19__MAX_OSD_MASK 0xFC000000L 2836 //DAGB1_RDCLI20 2837 #define DAGB1_RDCLI20__VIRT_CHAN__SHIFT 0x0 2838 #define DAGB1_RDCLI20__CHECK_TLB_CREDIT__SHIFT 0x3 2839 #define DAGB1_RDCLI20__URG_HIGH__SHIFT 0x4 2840 #define DAGB1_RDCLI20__URG_LOW__SHIFT 0x8 2841 #define DAGB1_RDCLI20__MAX_BW_ENABLE__SHIFT 0xc 2842 #define DAGB1_RDCLI20__MAX_BW__SHIFT 0xd 2843 #define DAGB1_RDCLI20__MIN_BW_ENABLE__SHIFT 0x15 2844 #define DAGB1_RDCLI20__MIN_BW__SHIFT 0x16 2845 #define DAGB1_RDCLI20__OSD_LIMITER_ENABLE__SHIFT 0x19 2846 #define DAGB1_RDCLI20__MAX_OSD__SHIFT 0x1a 2847 #define DAGB1_RDCLI20__VIRT_CHAN_MASK 0x00000007L 2848 #define DAGB1_RDCLI20__CHECK_TLB_CREDIT_MASK 0x00000008L 2849 #define DAGB1_RDCLI20__URG_HIGH_MASK 0x000000F0L 2850 #define DAGB1_RDCLI20__URG_LOW_MASK 0x00000F00L 2851 #define DAGB1_RDCLI20__MAX_BW_ENABLE_MASK 0x00001000L 2852 #define DAGB1_RDCLI20__MAX_BW_MASK 0x001FE000L 2853 #define DAGB1_RDCLI20__MIN_BW_ENABLE_MASK 0x00200000L 2854 #define DAGB1_RDCLI20__MIN_BW_MASK 0x01C00000L 2855 #define DAGB1_RDCLI20__OSD_LIMITER_ENABLE_MASK 0x02000000L 2856 #define DAGB1_RDCLI20__MAX_OSD_MASK 0xFC000000L 2857 //DAGB1_RDCLI21 2858 #define DAGB1_RDCLI21__VIRT_CHAN__SHIFT 0x0 2859 #define DAGB1_RDCLI21__CHECK_TLB_CREDIT__SHIFT 0x3 2860 #define DAGB1_RDCLI21__URG_HIGH__SHIFT 0x4 2861 #define DAGB1_RDCLI21__URG_LOW__SHIFT 0x8 2862 #define DAGB1_RDCLI21__MAX_BW_ENABLE__SHIFT 0xc 2863 #define DAGB1_RDCLI21__MAX_BW__SHIFT 0xd 2864 #define DAGB1_RDCLI21__MIN_BW_ENABLE__SHIFT 0x15 2865 #define DAGB1_RDCLI21__MIN_BW__SHIFT 0x16 2866 #define DAGB1_RDCLI21__OSD_LIMITER_ENABLE__SHIFT 0x19 2867 #define DAGB1_RDCLI21__MAX_OSD__SHIFT 0x1a 2868 #define DAGB1_RDCLI21__VIRT_CHAN_MASK 0x00000007L 2869 #define DAGB1_RDCLI21__CHECK_TLB_CREDIT_MASK 0x00000008L 2870 #define DAGB1_RDCLI21__URG_HIGH_MASK 0x000000F0L 2871 #define DAGB1_RDCLI21__URG_LOW_MASK 0x00000F00L 2872 #define DAGB1_RDCLI21__MAX_BW_ENABLE_MASK 0x00001000L 2873 #define DAGB1_RDCLI21__MAX_BW_MASK 0x001FE000L 2874 #define DAGB1_RDCLI21__MIN_BW_ENABLE_MASK 0x00200000L 2875 #define DAGB1_RDCLI21__MIN_BW_MASK 0x01C00000L 2876 #define DAGB1_RDCLI21__OSD_LIMITER_ENABLE_MASK 0x02000000L 2877 #define DAGB1_RDCLI21__MAX_OSD_MASK 0xFC000000L 2878 //DAGB1_RDCLI22 2879 #define DAGB1_RDCLI22__VIRT_CHAN__SHIFT 0x0 2880 #define DAGB1_RDCLI22__CHECK_TLB_CREDIT__SHIFT 0x3 2881 #define DAGB1_RDCLI22__URG_HIGH__SHIFT 0x4 2882 #define DAGB1_RDCLI22__URG_LOW__SHIFT 0x8 2883 #define DAGB1_RDCLI22__MAX_BW_ENABLE__SHIFT 0xc 2884 #define DAGB1_RDCLI22__MAX_BW__SHIFT 0xd 2885 #define DAGB1_RDCLI22__MIN_BW_ENABLE__SHIFT 0x15 2886 #define DAGB1_RDCLI22__MIN_BW__SHIFT 0x16 2887 #define DAGB1_RDCLI22__OSD_LIMITER_ENABLE__SHIFT 0x19 2888 #define DAGB1_RDCLI22__MAX_OSD__SHIFT 0x1a 2889 #define DAGB1_RDCLI22__VIRT_CHAN_MASK 0x00000007L 2890 #define DAGB1_RDCLI22__CHECK_TLB_CREDIT_MASK 0x00000008L 2891 #define DAGB1_RDCLI22__URG_HIGH_MASK 0x000000F0L 2892 #define DAGB1_RDCLI22__URG_LOW_MASK 0x00000F00L 2893 #define DAGB1_RDCLI22__MAX_BW_ENABLE_MASK 0x00001000L 2894 #define DAGB1_RDCLI22__MAX_BW_MASK 0x001FE000L 2895 #define DAGB1_RDCLI22__MIN_BW_ENABLE_MASK 0x00200000L 2896 #define DAGB1_RDCLI22__MIN_BW_MASK 0x01C00000L 2897 #define DAGB1_RDCLI22__OSD_LIMITER_ENABLE_MASK 0x02000000L 2898 #define DAGB1_RDCLI22__MAX_OSD_MASK 0xFC000000L 2899 //DAGB1_RDCLI23 2900 #define DAGB1_RDCLI23__VIRT_CHAN__SHIFT 0x0 2901 #define DAGB1_RDCLI23__CHECK_TLB_CREDIT__SHIFT 0x3 2902 #define DAGB1_RDCLI23__URG_HIGH__SHIFT 0x4 2903 #define DAGB1_RDCLI23__URG_LOW__SHIFT 0x8 2904 #define DAGB1_RDCLI23__MAX_BW_ENABLE__SHIFT 0xc 2905 #define DAGB1_RDCLI23__MAX_BW__SHIFT 0xd 2906 #define DAGB1_RDCLI23__MIN_BW_ENABLE__SHIFT 0x15 2907 #define DAGB1_RDCLI23__MIN_BW__SHIFT 0x16 2908 #define DAGB1_RDCLI23__OSD_LIMITER_ENABLE__SHIFT 0x19 2909 #define DAGB1_RDCLI23__MAX_OSD__SHIFT 0x1a 2910 #define DAGB1_RDCLI23__VIRT_CHAN_MASK 0x00000007L 2911 #define DAGB1_RDCLI23__CHECK_TLB_CREDIT_MASK 0x00000008L 2912 #define DAGB1_RDCLI23__URG_HIGH_MASK 0x000000F0L 2913 #define DAGB1_RDCLI23__URG_LOW_MASK 0x00000F00L 2914 #define DAGB1_RDCLI23__MAX_BW_ENABLE_MASK 0x00001000L 2915 #define DAGB1_RDCLI23__MAX_BW_MASK 0x001FE000L 2916 #define DAGB1_RDCLI23__MIN_BW_ENABLE_MASK 0x00200000L 2917 #define DAGB1_RDCLI23__MIN_BW_MASK 0x01C00000L 2918 #define DAGB1_RDCLI23__OSD_LIMITER_ENABLE_MASK 0x02000000L 2919 #define DAGB1_RDCLI23__MAX_OSD_MASK 0xFC000000L 2920 //DAGB1_RD_CNTL 2921 #define DAGB1_RD_CNTL__CLI_MAX_BW_WINDOW__SHIFT 0x0 2922 #define DAGB1_RD_CNTL__VC_MAX_BW_WINDOW__SHIFT 0x6 2923 #define DAGB1_RD_CNTL__SHARE_VC_NUM__SHIFT 0xc 2924 #define DAGB1_RD_CNTL__VC_ROUNDROBIN_EN__SHIFT 0xf 2925 #define DAGB1_RD_CNTL__CLI_MAX_BW_WINDOW_MASK 0x0000003FL 2926 #define DAGB1_RD_CNTL__VC_MAX_BW_WINDOW_MASK 0x00000FC0L 2927 #define DAGB1_RD_CNTL__SHARE_VC_NUM_MASK 0x00007000L 2928 #define DAGB1_RD_CNTL__VC_ROUNDROBIN_EN_MASK 0x00008000L 2929 //DAGB1_RD_IO_CNTL 2930 #define DAGB1_RD_IO_CNTL__OVERRIDE0_ENABLE__SHIFT 0x0 2931 #define DAGB1_RD_IO_CNTL__OVERRIDE0_PRIORITY__SHIFT 0x1 2932 #define DAGB1_RD_IO_CNTL__OVERRIDE0_CLIENT_ID__SHIFT 0x4 2933 #define DAGB1_RD_IO_CNTL__OVERRIDE1_ENABLE__SHIFT 0x9 2934 #define DAGB1_RD_IO_CNTL__OVERRIDE1_PRIORITY__SHIFT 0xa 2935 #define DAGB1_RD_IO_CNTL__OVERRIDE1_CLIENT_ID__SHIFT 0xd 2936 #define DAGB1_RD_IO_CNTL__COMMON_PRIORITY__SHIFT 0x12 2937 #define DAGB1_RD_IO_CNTL__OVERRIDE0_ENABLE_MASK 0x00000001L 2938 #define DAGB1_RD_IO_CNTL__OVERRIDE0_PRIORITY_MASK 0x0000000EL 2939 #define DAGB1_RD_IO_CNTL__OVERRIDE0_CLIENT_ID_MASK 0x000001F0L 2940 #define DAGB1_RD_IO_CNTL__OVERRIDE1_ENABLE_MASK 0x00000200L 2941 #define DAGB1_RD_IO_CNTL__OVERRIDE1_PRIORITY_MASK 0x00001C00L 2942 #define DAGB1_RD_IO_CNTL__OVERRIDE1_CLIENT_ID_MASK 0x0003E000L 2943 #define DAGB1_RD_IO_CNTL__COMMON_PRIORITY_MASK 0x001C0000L 2944 //DAGB1_RD_GMI_CNTL 2945 #define DAGB1_RD_GMI_CNTL__OVERRIDE0_ENABLE__SHIFT 0x0 2946 #define DAGB1_RD_GMI_CNTL__OVERRIDE0_PRIORITY__SHIFT 0x1 2947 #define DAGB1_RD_GMI_CNTL__OVERRIDE0_CLIENT_ID__SHIFT 0x4 2948 #define DAGB1_RD_GMI_CNTL__OVERRIDE1_ENABLE__SHIFT 0x9 2949 #define DAGB1_RD_GMI_CNTL__OVERRIDE1_PRIORITY__SHIFT 0xa 2950 #define DAGB1_RD_GMI_CNTL__OVERRIDE1_CLIENT_ID__SHIFT 0xd 2951 #define DAGB1_RD_GMI_CNTL__COMMON_PRIORITY__SHIFT 0x12 2952 #define DAGB1_RD_GMI_CNTL__OVERRIDE0_ENABLE_MASK 0x00000001L 2953 #define DAGB1_RD_GMI_CNTL__OVERRIDE0_PRIORITY_MASK 0x0000000EL 2954 #define DAGB1_RD_GMI_CNTL__OVERRIDE0_CLIENT_ID_MASK 0x000001F0L 2955 #define DAGB1_RD_GMI_CNTL__OVERRIDE1_ENABLE_MASK 0x00000200L 2956 #define DAGB1_RD_GMI_CNTL__OVERRIDE1_PRIORITY_MASK 0x00001C00L 2957 #define DAGB1_RD_GMI_CNTL__OVERRIDE1_CLIENT_ID_MASK 0x0003E000L 2958 #define DAGB1_RD_GMI_CNTL__COMMON_PRIORITY_MASK 0x001C0000L 2959 //DAGB1_RD_ADDR_DAGB 2960 #define DAGB1_RD_ADDR_DAGB__DAGB_ENABLE__SHIFT 0x0 2961 #define DAGB1_RD_ADDR_DAGB__ENABLE_JUMP_AHEAD__SHIFT 0x3 2962 #define DAGB1_RD_ADDR_DAGB__DISABLE_SELF_INIT__SHIFT 0x6 2963 #define DAGB1_RD_ADDR_DAGB__WHOAMI__SHIFT 0x7 2964 #define DAGB1_RD_ADDR_DAGB__JUMP_MODE__SHIFT 0xd 2965 #define DAGB1_RD_ADDR_DAGB__DAGB_ENABLE_MASK 0x00000007L 2966 #define DAGB1_RD_ADDR_DAGB__ENABLE_JUMP_AHEAD_MASK 0x00000038L 2967 #define DAGB1_RD_ADDR_DAGB__DISABLE_SELF_INIT_MASK 0x00000040L 2968 #define DAGB1_RD_ADDR_DAGB__WHOAMI_MASK 0x00001F80L 2969 #define DAGB1_RD_ADDR_DAGB__JUMP_MODE_MASK 0x00002000L 2970 //DAGB1_RD_CGTT_CLK_CTRL 2971 #define DAGB1_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 2972 #define DAGB1_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x5 2973 #define DAGB1_RD_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS__SHIFT 0xd 2974 #define DAGB1_RD_CGTT_CLK_CTRL__LS_DISABLE__SHIFT 0x1e 2975 #define DAGB1_RD_CGTT_CLK_CTRL__BUSY_OVERRIDE__SHIFT 0x1f 2976 #define DAGB1_RD_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000001FL 2977 #define DAGB1_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00001FE0L 2978 #define DAGB1_RD_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS_MASK 0x1FFFE000L 2979 #define DAGB1_RD_CGTT_CLK_CTRL__LS_DISABLE_MASK 0x40000000L 2980 #define DAGB1_RD_CGTT_CLK_CTRL__BUSY_OVERRIDE_MASK 0x80000000L 2981 //DAGB1_L1TLB_RD_CGTT_CLK_CTRL 2982 #define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 2983 #define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x5 2984 #define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS__SHIFT 0xd 2985 #define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__LS_DISABLE__SHIFT 0x1e 2986 #define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__BUSY_OVERRIDE__SHIFT 0x1f 2987 #define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000001FL 2988 #define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00001FE0L 2989 #define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS_MASK 0x1FFFE000L 2990 #define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__LS_DISABLE_MASK 0x40000000L 2991 #define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__BUSY_OVERRIDE_MASK 0x80000000L 2992 //DAGB1_RD_ADDR_DAGB_MAX_BURST0 2993 #define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT0__SHIFT 0x0 2994 #define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT1__SHIFT 0x4 2995 #define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT2__SHIFT 0x8 2996 #define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT3__SHIFT 0xc 2997 #define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT4__SHIFT 0x10 2998 #define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT5__SHIFT 0x14 2999 #define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT6__SHIFT 0x18 3000 #define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT7__SHIFT 0x1c 3001 #define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT0_MASK 0x0000000FL 3002 #define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT1_MASK 0x000000F0L 3003 #define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT2_MASK 0x00000F00L 3004 #define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT3_MASK 0x0000F000L 3005 #define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT4_MASK 0x000F0000L 3006 #define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT5_MASK 0x00F00000L 3007 #define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT6_MASK 0x0F000000L 3008 #define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT7_MASK 0xF0000000L 3009 //DAGB1_RD_ADDR_DAGB_LAZY_TIMER0 3010 #define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT0__SHIFT 0x0 3011 #define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT1__SHIFT 0x4 3012 #define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT2__SHIFT 0x8 3013 #define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT3__SHIFT 0xc 3014 #define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT4__SHIFT 0x10 3015 #define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT5__SHIFT 0x14 3016 #define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT6__SHIFT 0x18 3017 #define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT7__SHIFT 0x1c 3018 #define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT0_MASK 0x0000000FL 3019 #define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT1_MASK 0x000000F0L 3020 #define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT2_MASK 0x00000F00L 3021 #define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT3_MASK 0x0000F000L 3022 #define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT4_MASK 0x000F0000L 3023 #define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT5_MASK 0x00F00000L 3024 #define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT6_MASK 0x0F000000L 3025 #define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT7_MASK 0xF0000000L 3026 //DAGB1_RD_ADDR_DAGB_MAX_BURST1 3027 #define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT8__SHIFT 0x0 3028 #define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT9__SHIFT 0x4 3029 #define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT10__SHIFT 0x8 3030 #define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT11__SHIFT 0xc 3031 #define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT12__SHIFT 0x10 3032 #define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT13__SHIFT 0x14 3033 #define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT14__SHIFT 0x18 3034 #define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT15__SHIFT 0x1c 3035 #define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT8_MASK 0x0000000FL 3036 #define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT9_MASK 0x000000F0L 3037 #define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT10_MASK 0x00000F00L 3038 #define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT11_MASK 0x0000F000L 3039 #define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT12_MASK 0x000F0000L 3040 #define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT13_MASK 0x00F00000L 3041 #define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT14_MASK 0x0F000000L 3042 #define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT15_MASK 0xF0000000L 3043 //DAGB1_RD_ADDR_DAGB_LAZY_TIMER1 3044 #define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT8__SHIFT 0x0 3045 #define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT9__SHIFT 0x4 3046 #define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT10__SHIFT 0x8 3047 #define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT11__SHIFT 0xc 3048 #define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT12__SHIFT 0x10 3049 #define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT13__SHIFT 0x14 3050 #define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT14__SHIFT 0x18 3051 #define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT15__SHIFT 0x1c 3052 #define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT8_MASK 0x0000000FL 3053 #define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT9_MASK 0x000000F0L 3054 #define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT10_MASK 0x00000F00L 3055 #define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT11_MASK 0x0000F000L 3056 #define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT12_MASK 0x000F0000L 3057 #define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT13_MASK 0x00F00000L 3058 #define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT14_MASK 0x0F000000L 3059 #define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT15_MASK 0xF0000000L 3060 //DAGB1_RD_ADDR_DAGB_MAX_BURST2 3061 #define DAGB1_RD_ADDR_DAGB_MAX_BURST2__CLIENT16__SHIFT 0x0 3062 #define DAGB1_RD_ADDR_DAGB_MAX_BURST2__CLIENT17__SHIFT 0x4 3063 #define DAGB1_RD_ADDR_DAGB_MAX_BURST2__CLIENT18__SHIFT 0x8 3064 #define DAGB1_RD_ADDR_DAGB_MAX_BURST2__CLIENT19__SHIFT 0xc 3065 #define DAGB1_RD_ADDR_DAGB_MAX_BURST2__CLIENT20__SHIFT 0x10 3066 #define DAGB1_RD_ADDR_DAGB_MAX_BURST2__CLIENT21__SHIFT 0x14 3067 #define DAGB1_RD_ADDR_DAGB_MAX_BURST2__CLIENT22__SHIFT 0x18 3068 #define DAGB1_RD_ADDR_DAGB_MAX_BURST2__CLIENT23__SHIFT 0x1c 3069 #define DAGB1_RD_ADDR_DAGB_MAX_BURST2__CLIENT16_MASK 0x0000000FL 3070 #define DAGB1_RD_ADDR_DAGB_MAX_BURST2__CLIENT17_MASK 0x000000F0L 3071 #define DAGB1_RD_ADDR_DAGB_MAX_BURST2__CLIENT18_MASK 0x00000F00L 3072 #define DAGB1_RD_ADDR_DAGB_MAX_BURST2__CLIENT19_MASK 0x0000F000L 3073 #define DAGB1_RD_ADDR_DAGB_MAX_BURST2__CLIENT20_MASK 0x000F0000L 3074 #define DAGB1_RD_ADDR_DAGB_MAX_BURST2__CLIENT21_MASK 0x00F00000L 3075 #define DAGB1_RD_ADDR_DAGB_MAX_BURST2__CLIENT22_MASK 0x0F000000L 3076 #define DAGB1_RD_ADDR_DAGB_MAX_BURST2__CLIENT23_MASK 0xF0000000L 3077 //DAGB1_RD_ADDR_DAGB_LAZY_TIMER2 3078 #define DAGB1_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT16__SHIFT 0x0 3079 #define DAGB1_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT17__SHIFT 0x4 3080 #define DAGB1_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT18__SHIFT 0x8 3081 #define DAGB1_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT19__SHIFT 0xc 3082 #define DAGB1_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT20__SHIFT 0x10 3083 #define DAGB1_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT21__SHIFT 0x14 3084 #define DAGB1_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT22__SHIFT 0x18 3085 #define DAGB1_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT23__SHIFT 0x1c 3086 #define DAGB1_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT16_MASK 0x0000000FL 3087 #define DAGB1_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT17_MASK 0x000000F0L 3088 #define DAGB1_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT18_MASK 0x00000F00L 3089 #define DAGB1_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT19_MASK 0x0000F000L 3090 #define DAGB1_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT20_MASK 0x000F0000L 3091 #define DAGB1_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT21_MASK 0x00F00000L 3092 #define DAGB1_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT22_MASK 0x0F000000L 3093 #define DAGB1_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT23_MASK 0xF0000000L 3094 //DAGB1_RD_VC0_CNTL 3095 #define DAGB1_RD_VC0_CNTL__STOR_CREDIT__SHIFT 0x0 3096 #define DAGB1_RD_VC0_CNTL__MAX_BW_ENABLE__SHIFT 0xb 3097 #define DAGB1_RD_VC0_CNTL__MAX_BW__SHIFT 0xc 3098 #define DAGB1_RD_VC0_CNTL__MIN_BW_ENABLE__SHIFT 0x14 3099 #define DAGB1_RD_VC0_CNTL__MIN_BW__SHIFT 0x15 3100 #define DAGB1_RD_VC0_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 3101 #define DAGB1_RD_VC0_CNTL__MAX_OSD__SHIFT 0x19 3102 #define DAGB1_RD_VC0_CNTL__STOR_CREDIT_MASK 0x0000001FL 3103 #define DAGB1_RD_VC0_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 3104 #define DAGB1_RD_VC0_CNTL__MAX_BW_MASK 0x000FF000L 3105 #define DAGB1_RD_VC0_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 3106 #define DAGB1_RD_VC0_CNTL__MIN_BW_MASK 0x00E00000L 3107 #define DAGB1_RD_VC0_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 3108 #define DAGB1_RD_VC0_CNTL__MAX_OSD_MASK 0xFE000000L 3109 //DAGB1_RD_VC1_CNTL 3110 #define DAGB1_RD_VC1_CNTL__STOR_CREDIT__SHIFT 0x0 3111 #define DAGB1_RD_VC1_CNTL__MAX_BW_ENABLE__SHIFT 0xb 3112 #define DAGB1_RD_VC1_CNTL__MAX_BW__SHIFT 0xc 3113 #define DAGB1_RD_VC1_CNTL__MIN_BW_ENABLE__SHIFT 0x14 3114 #define DAGB1_RD_VC1_CNTL__MIN_BW__SHIFT 0x15 3115 #define DAGB1_RD_VC1_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 3116 #define DAGB1_RD_VC1_CNTL__MAX_OSD__SHIFT 0x19 3117 #define DAGB1_RD_VC1_CNTL__STOR_CREDIT_MASK 0x0000001FL 3118 #define DAGB1_RD_VC1_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 3119 #define DAGB1_RD_VC1_CNTL__MAX_BW_MASK 0x000FF000L 3120 #define DAGB1_RD_VC1_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 3121 #define DAGB1_RD_VC1_CNTL__MIN_BW_MASK 0x00E00000L 3122 #define DAGB1_RD_VC1_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 3123 #define DAGB1_RD_VC1_CNTL__MAX_OSD_MASK 0xFE000000L 3124 //DAGB1_RD_VC2_CNTL 3125 #define DAGB1_RD_VC2_CNTL__STOR_CREDIT__SHIFT 0x0 3126 #define DAGB1_RD_VC2_CNTL__MAX_BW_ENABLE__SHIFT 0xb 3127 #define DAGB1_RD_VC2_CNTL__MAX_BW__SHIFT 0xc 3128 #define DAGB1_RD_VC2_CNTL__MIN_BW_ENABLE__SHIFT 0x14 3129 #define DAGB1_RD_VC2_CNTL__MIN_BW__SHIFT 0x15 3130 #define DAGB1_RD_VC2_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 3131 #define DAGB1_RD_VC2_CNTL__MAX_OSD__SHIFT 0x19 3132 #define DAGB1_RD_VC2_CNTL__STOR_CREDIT_MASK 0x0000001FL 3133 #define DAGB1_RD_VC2_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 3134 #define DAGB1_RD_VC2_CNTL__MAX_BW_MASK 0x000FF000L 3135 #define DAGB1_RD_VC2_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 3136 #define DAGB1_RD_VC2_CNTL__MIN_BW_MASK 0x00E00000L 3137 #define DAGB1_RD_VC2_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 3138 #define DAGB1_RD_VC2_CNTL__MAX_OSD_MASK 0xFE000000L 3139 //DAGB1_RD_VC3_CNTL 3140 #define DAGB1_RD_VC3_CNTL__STOR_CREDIT__SHIFT 0x0 3141 #define DAGB1_RD_VC3_CNTL__MAX_BW_ENABLE__SHIFT 0xb 3142 #define DAGB1_RD_VC3_CNTL__MAX_BW__SHIFT 0xc 3143 #define DAGB1_RD_VC3_CNTL__MIN_BW_ENABLE__SHIFT 0x14 3144 #define DAGB1_RD_VC3_CNTL__MIN_BW__SHIFT 0x15 3145 #define DAGB1_RD_VC3_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 3146 #define DAGB1_RD_VC3_CNTL__MAX_OSD__SHIFT 0x19 3147 #define DAGB1_RD_VC3_CNTL__STOR_CREDIT_MASK 0x0000001FL 3148 #define DAGB1_RD_VC3_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 3149 #define DAGB1_RD_VC3_CNTL__MAX_BW_MASK 0x000FF000L 3150 #define DAGB1_RD_VC3_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 3151 #define DAGB1_RD_VC3_CNTL__MIN_BW_MASK 0x00E00000L 3152 #define DAGB1_RD_VC3_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 3153 #define DAGB1_RD_VC3_CNTL__MAX_OSD_MASK 0xFE000000L 3154 //DAGB1_RD_VC4_CNTL 3155 #define DAGB1_RD_VC4_CNTL__STOR_CREDIT__SHIFT 0x0 3156 #define DAGB1_RD_VC4_CNTL__MAX_BW_ENABLE__SHIFT 0xb 3157 #define DAGB1_RD_VC4_CNTL__MAX_BW__SHIFT 0xc 3158 #define DAGB1_RD_VC4_CNTL__MIN_BW_ENABLE__SHIFT 0x14 3159 #define DAGB1_RD_VC4_CNTL__MIN_BW__SHIFT 0x15 3160 #define DAGB1_RD_VC4_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 3161 #define DAGB1_RD_VC4_CNTL__MAX_OSD__SHIFT 0x19 3162 #define DAGB1_RD_VC4_CNTL__STOR_CREDIT_MASK 0x0000001FL 3163 #define DAGB1_RD_VC4_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 3164 #define DAGB1_RD_VC4_CNTL__MAX_BW_MASK 0x000FF000L 3165 #define DAGB1_RD_VC4_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 3166 #define DAGB1_RD_VC4_CNTL__MIN_BW_MASK 0x00E00000L 3167 #define DAGB1_RD_VC4_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 3168 #define DAGB1_RD_VC4_CNTL__MAX_OSD_MASK 0xFE000000L 3169 //DAGB1_RD_VC5_CNTL 3170 #define DAGB1_RD_VC5_CNTL__STOR_CREDIT__SHIFT 0x0 3171 #define DAGB1_RD_VC5_CNTL__MAX_BW_ENABLE__SHIFT 0xb 3172 #define DAGB1_RD_VC5_CNTL__MAX_BW__SHIFT 0xc 3173 #define DAGB1_RD_VC5_CNTL__MIN_BW_ENABLE__SHIFT 0x14 3174 #define DAGB1_RD_VC5_CNTL__MIN_BW__SHIFT 0x15 3175 #define DAGB1_RD_VC5_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 3176 #define DAGB1_RD_VC5_CNTL__MAX_OSD__SHIFT 0x19 3177 #define DAGB1_RD_VC5_CNTL__STOR_CREDIT_MASK 0x0000001FL 3178 #define DAGB1_RD_VC5_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 3179 #define DAGB1_RD_VC5_CNTL__MAX_BW_MASK 0x000FF000L 3180 #define DAGB1_RD_VC5_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 3181 #define DAGB1_RD_VC5_CNTL__MIN_BW_MASK 0x00E00000L 3182 #define DAGB1_RD_VC5_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 3183 #define DAGB1_RD_VC5_CNTL__MAX_OSD_MASK 0xFE000000L 3184 //DAGB1_RD_IO_VC_CNTL 3185 #define DAGB1_RD_IO_VC_CNTL__MAX_BW_ENABLE__SHIFT 0x0 3186 #define DAGB1_RD_IO_VC_CNTL__MAX_BW__SHIFT 0xc 3187 #define DAGB1_RD_IO_VC_CNTL__MIN_BW_ENABLE__SHIFT 0x14 3188 #define DAGB1_RD_IO_VC_CNTL__MIN_BW__SHIFT 0x15 3189 #define DAGB1_RD_IO_VC_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 3190 #define DAGB1_RD_IO_VC_CNTL__MAX_OSD__SHIFT 0x19 3191 #define DAGB1_RD_IO_VC_CNTL__MAX_BW_ENABLE_MASK 0x00000001L 3192 #define DAGB1_RD_IO_VC_CNTL__MAX_BW_MASK 0x000FF000L 3193 #define DAGB1_RD_IO_VC_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 3194 #define DAGB1_RD_IO_VC_CNTL__MIN_BW_MASK 0x00E00000L 3195 #define DAGB1_RD_IO_VC_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 3196 #define DAGB1_RD_IO_VC_CNTL__MAX_OSD_MASK 0xFE000000L 3197 //DAGB1_RD_GMI_VC_CNTL 3198 #define DAGB1_RD_GMI_VC_CNTL__MAX_BW_ENABLE__SHIFT 0x0 3199 #define DAGB1_RD_GMI_VC_CNTL__MAX_BW__SHIFT 0xc 3200 #define DAGB1_RD_GMI_VC_CNTL__MIN_BW_ENABLE__SHIFT 0x14 3201 #define DAGB1_RD_GMI_VC_CNTL__MIN_BW__SHIFT 0x15 3202 #define DAGB1_RD_GMI_VC_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 3203 #define DAGB1_RD_GMI_VC_CNTL__MAX_OSD__SHIFT 0x19 3204 #define DAGB1_RD_GMI_VC_CNTL__MAX_BW_ENABLE_MASK 0x00000001L 3205 #define DAGB1_RD_GMI_VC_CNTL__MAX_BW_MASK 0x000FF000L 3206 #define DAGB1_RD_GMI_VC_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 3207 #define DAGB1_RD_GMI_VC_CNTL__MIN_BW_MASK 0x00E00000L 3208 #define DAGB1_RD_GMI_VC_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 3209 #define DAGB1_RD_GMI_VC_CNTL__MAX_OSD_MASK 0xFE000000L 3210 //DAGB1_RD_CNTL_MISC 3211 #define DAGB1_RD_CNTL_MISC__STOR_POOL_CREDIT__SHIFT 0x0 3212 #define DAGB1_RD_CNTL_MISC__UTCL2_VCI__SHIFT 0x6 3213 #define DAGB1_RD_CNTL_MISC__RDRET_CC_LEGACY_MODE__SHIFT 0x9 3214 #define DAGB1_RD_CNTL_MISC__STOR_POOL_CREDIT_MASK 0x0000003FL 3215 #define DAGB1_RD_CNTL_MISC__UTCL2_VCI_MASK 0x000001C0L 3216 #define DAGB1_RD_CNTL_MISC__RDRET_CC_LEGACY_MODE_MASK 0x00000200L 3217 //DAGB1_RD_TLB_CREDIT 3218 #define DAGB1_RD_TLB_CREDIT__TLB0__SHIFT 0x0 3219 #define DAGB1_RD_TLB_CREDIT__TLB1__SHIFT 0x5 3220 #define DAGB1_RD_TLB_CREDIT__TLB2__SHIFT 0xa 3221 #define DAGB1_RD_TLB_CREDIT__TLB3__SHIFT 0xf 3222 #define DAGB1_RD_TLB_CREDIT__TLB4__SHIFT 0x14 3223 #define DAGB1_RD_TLB_CREDIT__TLB5__SHIFT 0x19 3224 #define DAGB1_RD_TLB_CREDIT__TLB0_MASK 0x0000001FL 3225 #define DAGB1_RD_TLB_CREDIT__TLB1_MASK 0x000003E0L 3226 #define DAGB1_RD_TLB_CREDIT__TLB2_MASK 0x00007C00L 3227 #define DAGB1_RD_TLB_CREDIT__TLB3_MASK 0x000F8000L 3228 #define DAGB1_RD_TLB_CREDIT__TLB4_MASK 0x01F00000L 3229 #define DAGB1_RD_TLB_CREDIT__TLB5_MASK 0x3E000000L 3230 //DAGB1_RD_RDRET_CREDIT_CNTL 3231 #define DAGB1_RD_RDRET_CREDIT_CNTL__VC0_CREDIT__SHIFT 0x0 3232 #define DAGB1_RD_RDRET_CREDIT_CNTL__VC1_CREDIT__SHIFT 0x5 3233 #define DAGB1_RD_RDRET_CREDIT_CNTL__VC2_CREDIT__SHIFT 0xa 3234 #define DAGB1_RD_RDRET_CREDIT_CNTL__VC3_CREDIT__SHIFT 0xf 3235 #define DAGB1_RD_RDRET_CREDIT_CNTL__VC4_CREDIT__SHIFT 0x14 3236 #define DAGB1_RD_RDRET_CREDIT_CNTL__VC5_CREDIT__SHIFT 0x19 3237 #define DAGB1_RD_RDRET_CREDIT_CNTL__VC_MODE__SHIFT 0x1e 3238 #define DAGB1_RD_RDRET_CREDIT_CNTL__FIX_EQ__SHIFT 0x1f 3239 #define DAGB1_RD_RDRET_CREDIT_CNTL__VC0_CREDIT_MASK 0x0000001FL 3240 #define DAGB1_RD_RDRET_CREDIT_CNTL__VC1_CREDIT_MASK 0x000003E0L 3241 #define DAGB1_RD_RDRET_CREDIT_CNTL__VC2_CREDIT_MASK 0x00007C00L 3242 #define DAGB1_RD_RDRET_CREDIT_CNTL__VC3_CREDIT_MASK 0x000F8000L 3243 #define DAGB1_RD_RDRET_CREDIT_CNTL__VC4_CREDIT_MASK 0x01F00000L 3244 #define DAGB1_RD_RDRET_CREDIT_CNTL__VC5_CREDIT_MASK 0x3E000000L 3245 #define DAGB1_RD_RDRET_CREDIT_CNTL__VC_MODE_MASK 0x40000000L 3246 #define DAGB1_RD_RDRET_CREDIT_CNTL__FIX_EQ_MASK 0x80000000L 3247 //DAGB1_RD_RDRET_CREDIT_CNTL2 3248 #define DAGB1_RD_RDRET_CREDIT_CNTL2__POOL_CREDIT__SHIFT 0x0 3249 #define DAGB1_RD_RDRET_CREDIT_CNTL2__POOL_CREDIT_MASK 0x0000003FL 3250 //DAGB1_RDCLI_ASK_PENDING 3251 #define DAGB1_RDCLI_ASK_PENDING__BUSY__SHIFT 0x0 3252 #define DAGB1_RDCLI_ASK_PENDING__BUSY_MASK 0xFFFFFFFFL 3253 //DAGB1_RDCLI_GO_PENDING 3254 #define DAGB1_RDCLI_GO_PENDING__BUSY__SHIFT 0x0 3255 #define DAGB1_RDCLI_GO_PENDING__BUSY_MASK 0xFFFFFFFFL 3256 //DAGB1_RDCLI_GBLSEND_PENDING 3257 #define DAGB1_RDCLI_GBLSEND_PENDING__BUSY__SHIFT 0x0 3258 #define DAGB1_RDCLI_GBLSEND_PENDING__BUSY_MASK 0xFFFFFFFFL 3259 //DAGB1_RDCLI_TLB_PENDING 3260 #define DAGB1_RDCLI_TLB_PENDING__BUSY__SHIFT 0x0 3261 #define DAGB1_RDCLI_TLB_PENDING__BUSY_MASK 0xFFFFFFFFL 3262 //DAGB1_RDCLI_OARB_PENDING 3263 #define DAGB1_RDCLI_OARB_PENDING__BUSY__SHIFT 0x0 3264 #define DAGB1_RDCLI_OARB_PENDING__BUSY_MASK 0xFFFFFFFFL 3265 //DAGB1_RDCLI_ASK2ARB_PENDING 3266 #define DAGB1_RDCLI_ASK2ARB_PENDING__BUSY__SHIFT 0x0 3267 #define DAGB1_RDCLI_ASK2ARB_PENDING__BUSY_MASK 0xFFFFFFFFL 3268 //DAGB1_RDCLI_ASK2DF_PENDING 3269 #define DAGB1_RDCLI_ASK2DF_PENDING__BUSY__SHIFT 0x0 3270 #define DAGB1_RDCLI_ASK2DF_PENDING__BUSY_MASK 0xFFFFFFFFL 3271 //DAGB1_RDCLI_OSD_PENDING 3272 #define DAGB1_RDCLI_OSD_PENDING__BUSY__SHIFT 0x0 3273 #define DAGB1_RDCLI_OSD_PENDING__BUSY_MASK 0xFFFFFFFFL 3274 //DAGB1_RDCLI_ASK_OSD_PENDING 3275 #define DAGB1_RDCLI_ASK_OSD_PENDING__BUSY__SHIFT 0x0 3276 #define DAGB1_RDCLI_ASK_OSD_PENDING__BUSY_MASK 0xFFFFFFFFL 3277 //DAGB1_RDCLI_NOALLOC_OVERRIDE 3278 #define DAGB1_RDCLI_NOALLOC_OVERRIDE__ENABLE__SHIFT 0x0 3279 #define DAGB1_RDCLI_NOALLOC_OVERRIDE__ENABLE_MASK 0xFFFFFFFFL 3280 //DAGB1_RDCLI_NOALLOC_OVERRIDE_VALUE 3281 #define DAGB1_RDCLI_NOALLOC_OVERRIDE_VALUE__VALUE__SHIFT 0x0 3282 #define DAGB1_RDCLI_NOALLOC_OVERRIDE_VALUE__VALUE_MASK 0xFFFFFFFFL 3283 //DAGB1_DAGB_DLY 3284 #define DAGB1_DAGB_DLY__DLY__SHIFT 0x0 3285 #define DAGB1_DAGB_DLY__CLI__SHIFT 0x8 3286 #define DAGB1_DAGB_DLY__POS__SHIFT 0x10 3287 #define DAGB1_DAGB_DLY__DLY_MASK 0x000000FFL 3288 #define DAGB1_DAGB_DLY__CLI_MASK 0x0000FF00L 3289 #define DAGB1_DAGB_DLY__POS_MASK 0x000F0000L 3290 //DAGB1_CNTL_MISC 3291 #define DAGB1_CNTL_MISC__BW_INIT_CYCLE__SHIFT 0x0 3292 #define DAGB1_CNTL_MISC__BW_INIT_CYCLE_MASK 0x0000003FL 3293 //DAGB1_CNTL_MISC2 3294 #define DAGB1_CNTL_MISC2__WR_BUSY_OVERRIDE__SHIFT 0x0 3295 #define DAGB1_CNTL_MISC2__RD_BUSY_OVERRIDE__SHIFT 0x1 3296 #define DAGB1_CNTL_MISC2__TLBWR_BUSY_OVERRIDE__SHIFT 0x2 3297 #define DAGB1_CNTL_MISC2__TLBRD_BUSY_OVERRIDE__SHIFT 0x3 3298 #define DAGB1_CNTL_MISC2__SDP_BUSY_OVERRIDE__SHIFT 0x4 3299 #define DAGB1_CNTL_MISC2__SWAP_CTL__SHIFT 0x5 3300 #define DAGB1_CNTL_MISC2__ENABLE_PARITY_CHECK__SHIFT 0x6 3301 #define DAGB1_CNTL_MISC2__RDATA_PARITY_CHECK4NACK__SHIFT 0x7 3302 #define DAGB1_CNTL_MISC2__WDATA_PARITY_CHECK4RAS__SHIFT 0x8 3303 #define DAGB1_CNTL_MISC2__RDRET_FIFO_PERF__SHIFT 0x9 3304 #define DAGB1_CNTL_MISC2__DISABLE_RDRET_TAP_CHAIN_FGCG__SHIFT 0xa 3305 #define DAGB1_CNTL_MISC2__DISABLE_WRRET_TAP_CHAIN_FGCG__SHIFT 0xb 3306 #define DAGB1_CNTL_MISC2__WR_BUSY_OVERRIDE_MASK 0x00000001L 3307 #define DAGB1_CNTL_MISC2__RD_BUSY_OVERRIDE_MASK 0x00000002L 3308 #define DAGB1_CNTL_MISC2__TLBWR_BUSY_OVERRIDE_MASK 0x00000004L 3309 #define DAGB1_CNTL_MISC2__TLBRD_BUSY_OVERRIDE_MASK 0x00000008L 3310 #define DAGB1_CNTL_MISC2__SDP_BUSY_OVERRIDE_MASK 0x00000010L 3311 #define DAGB1_CNTL_MISC2__SWAP_CTL_MASK 0x00000020L 3312 #define DAGB1_CNTL_MISC2__ENABLE_PARITY_CHECK_MASK 0x00000040L 3313 #define DAGB1_CNTL_MISC2__RDATA_PARITY_CHECK4NACK_MASK 0x00000080L 3314 #define DAGB1_CNTL_MISC2__WDATA_PARITY_CHECK4RAS_MASK 0x00000100L 3315 #define DAGB1_CNTL_MISC2__RDRET_FIFO_PERF_MASK 0x00000200L 3316 #define DAGB1_CNTL_MISC2__DISABLE_RDRET_TAP_CHAIN_FGCG_MASK 0x00000400L 3317 #define DAGB1_CNTL_MISC2__DISABLE_WRRET_TAP_CHAIN_FGCG_MASK 0x00000800L 3318 //DAGB1_FIFO_EMPTY 3319 #define DAGB1_FIFO_EMPTY__EMPTY__SHIFT 0x0 3320 #define DAGB1_FIFO_EMPTY__EMPTY_MASK 0x0000007FL 3321 //DAGB1_FIFO_FULL 3322 #define DAGB1_FIFO_FULL__FULL__SHIFT 0x0 3323 #define DAGB1_FIFO_FULL__FULL_MASK 0x0000007FL 3324 //DAGB1_RD_CREDITS_FULL 3325 #define DAGB1_RD_CREDITS_FULL__FULL__SHIFT 0x0 3326 #define DAGB1_RD_CREDITS_FULL__FULL_MASK 0x0000007FL 3327 //DAGB1_PERFCOUNTER_LO 3328 #define DAGB1_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 3329 #define DAGB1_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL 3330 //DAGB1_PERFCOUNTER_HI 3331 #define DAGB1_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 3332 #define DAGB1_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 3333 #define DAGB1_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL 3334 #define DAGB1_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L 3335 //DAGB1_PERFCOUNTER0_CFG 3336 #define DAGB1_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 3337 #define DAGB1_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 3338 #define DAGB1_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 3339 #define DAGB1_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c 3340 #define DAGB1_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d 3341 #define DAGB1_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL 3342 #define DAGB1_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L 3343 #define DAGB1_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L 3344 #define DAGB1_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L 3345 #define DAGB1_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L 3346 //DAGB1_PERFCOUNTER1_CFG 3347 #define DAGB1_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 3348 #define DAGB1_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 3349 #define DAGB1_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 3350 #define DAGB1_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c 3351 #define DAGB1_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d 3352 #define DAGB1_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL 3353 #define DAGB1_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L 3354 #define DAGB1_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L 3355 #define DAGB1_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L 3356 #define DAGB1_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L 3357 //DAGB1_PERFCOUNTER2_CFG 3358 #define DAGB1_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0 3359 #define DAGB1_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8 3360 #define DAGB1_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18 3361 #define DAGB1_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c 3362 #define DAGB1_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d 3363 #define DAGB1_PERFCOUNTER2_CFG__PERF_SEL_MASK 0x000000FFL 3364 #define DAGB1_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0x0000FF00L 3365 #define DAGB1_PERFCOUNTER2_CFG__PERF_MODE_MASK 0x0F000000L 3366 #define DAGB1_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000L 3367 #define DAGB1_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000L 3368 //DAGB1_PERFCOUNTER_RSLT_CNTL 3369 #define DAGB1_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 3370 #define DAGB1_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 3371 #define DAGB1_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 3372 #define DAGB1_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 3373 #define DAGB1_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 3374 #define DAGB1_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a 3375 #define DAGB1_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x00000003L 3376 #define DAGB1_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L 3377 #define DAGB1_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L 3378 #define DAGB1_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L 3379 #define DAGB1_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L 3380 #define DAGB1_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L 3381 //DAGB1_L1TLB_REG_RW 3382 #define DAGB1_L1TLB_REG_RW__REG_WRITE_L1TLB_CTRL__SHIFT 0x0 3383 #define DAGB1_L1TLB_REG_RW__REG_READ_L1TLB_CTRL__SHIFT 0x1 3384 #define DAGB1_L1TLB_REG_RW__RESERVE__SHIFT 0x2 3385 #define DAGB1_L1TLB_REG_RW__REG_WRITE_L1TLB_CTRL_MASK 0x00000001L 3386 #define DAGB1_L1TLB_REG_RW__REG_READ_L1TLB_CTRL_MASK 0x00000002L 3387 #define DAGB1_L1TLB_REG_RW__RESERVE_MASK 0x3FFFFFFCL 3388 //DAGB1_RESERVE1 3389 #define DAGB1_RESERVE1__RESERVE__SHIFT 0x0 3390 #define DAGB1_RESERVE1__RESERVE_MASK 0xFFFFFFFFL 3391 //DAGB1_RESERVE2 3392 #define DAGB1_RESERVE2__RESERVE__SHIFT 0x0 3393 #define DAGB1_RESERVE2__RESERVE_MASK 0xFFFFFFFFL 3394 //DAGB1_RESERVE3 3395 #define DAGB1_RESERVE3__RESERVE__SHIFT 0x0 3396 #define DAGB1_RESERVE3__RESERVE_MASK 0xFFFFFFFFL 3397 //DAGB1_RESERVE4 3398 #define DAGB1_RESERVE4__RESERVE__SHIFT 0x0 3399 #define DAGB1_RESERVE4__RESERVE_MASK 0xFFFFFFFFL 3400 //DAGB1_SDP_RD_BW_CNTL 3401 #define DAGB1_SDP_RD_BW_CNTL__MAX_BW_ENABLE__SHIFT 0x0 3402 #define DAGB1_SDP_RD_BW_CNTL__MAX_BW__SHIFT 0x1 3403 #define DAGB1_SDP_RD_BW_CNTL__MIN_BW_ENABLE__SHIFT 0x9 3404 #define DAGB1_SDP_RD_BW_CNTL__MIN_BW__SHIFT 0xa 3405 #define DAGB1_SDP_RD_BW_CNTL__MAX_BW_WINDOW__SHIFT 0xd 3406 #define DAGB1_SDP_RD_BW_CNTL__MAX_BW_ENABLE_MASK 0x00000001L 3407 #define DAGB1_SDP_RD_BW_CNTL__MAX_BW_MASK 0x000001FEL 3408 #define DAGB1_SDP_RD_BW_CNTL__MIN_BW_ENABLE_MASK 0x00000200L 3409 #define DAGB1_SDP_RD_BW_CNTL__MIN_BW_MASK 0x00001C00L 3410 #define DAGB1_SDP_RD_BW_CNTL__MAX_BW_WINDOW_MASK 0x0007E000L 3411 //DAGB1_SDP_PRIORITY_OVERRIDE 3412 #define DAGB1_SDP_PRIORITY_OVERRIDE__OVERRIDE0_PRIORITY__SHIFT 0x0 3413 #define DAGB1_SDP_PRIORITY_OVERRIDE__OVERRIDE0_CLIENT_ID__SHIFT 0x4 3414 #define DAGB1_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_DRAM_RD__SHIFT 0x9 3415 #define DAGB1_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_DRAM_WR__SHIFT 0xa 3416 #define DAGB1_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_GMI_RD__SHIFT 0xb 3417 #define DAGB1_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_GMI_WR__SHIFT 0xc 3418 #define DAGB1_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_IO_RD__SHIFT 0xd 3419 #define DAGB1_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_IO_WR__SHIFT 0xe 3420 #define DAGB1_SDP_PRIORITY_OVERRIDE__OVERRIDE1_PRIORITY__SHIFT 0x10 3421 #define DAGB1_SDP_PRIORITY_OVERRIDE__OVERRIDE1_CLIENT_ID__SHIFT 0x14 3422 #define DAGB1_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_DRAM_RD__SHIFT 0x19 3423 #define DAGB1_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_DRAM_WR__SHIFT 0x1a 3424 #define DAGB1_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_GMI_RD__SHIFT 0x1b 3425 #define DAGB1_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_GMI_WR__SHIFT 0x1c 3426 #define DAGB1_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_IO_RD__SHIFT 0x1d 3427 #define DAGB1_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_IO_WR__SHIFT 0x1e 3428 #define DAGB1_SDP_PRIORITY_OVERRIDE__OVERRIDE0_PRIORITY_MASK 0x0000000FL 3429 #define DAGB1_SDP_PRIORITY_OVERRIDE__OVERRIDE0_CLIENT_ID_MASK 0x000001F0L 3430 #define DAGB1_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_DRAM_RD_MASK 0x00000200L 3431 #define DAGB1_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_DRAM_WR_MASK 0x00000400L 3432 #define DAGB1_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_GMI_RD_MASK 0x00000800L 3433 #define DAGB1_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_GMI_WR_MASK 0x00001000L 3434 #define DAGB1_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_IO_RD_MASK 0x00002000L 3435 #define DAGB1_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_IO_WR_MASK 0x00004000L 3436 #define DAGB1_SDP_PRIORITY_OVERRIDE__OVERRIDE1_PRIORITY_MASK 0x000F0000L 3437 #define DAGB1_SDP_PRIORITY_OVERRIDE__OVERRIDE1_CLIENT_ID_MASK 0x01F00000L 3438 #define DAGB1_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_DRAM_RD_MASK 0x02000000L 3439 #define DAGB1_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_DRAM_WR_MASK 0x04000000L 3440 #define DAGB1_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_GMI_RD_MASK 0x08000000L 3441 #define DAGB1_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_GMI_WR_MASK 0x10000000L 3442 #define DAGB1_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_IO_RD_MASK 0x20000000L 3443 #define DAGB1_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_IO_WR_MASK 0x40000000L 3444 //DAGB1_SDP_RD_PRIORITY 3445 #define DAGB1_SDP_RD_PRIORITY__RD_VC0_PRIORITY__SHIFT 0x0 3446 #define DAGB1_SDP_RD_PRIORITY__RD_VC1_PRIORITY__SHIFT 0x4 3447 #define DAGB1_SDP_RD_PRIORITY__RD_VC2_PRIORITY__SHIFT 0x8 3448 #define DAGB1_SDP_RD_PRIORITY__RD_VC3_PRIORITY__SHIFT 0xc 3449 #define DAGB1_SDP_RD_PRIORITY__RD_VC4_PRIORITY__SHIFT 0x10 3450 #define DAGB1_SDP_RD_PRIORITY__RD_VC5_PRIORITY__SHIFT 0x14 3451 #define DAGB1_SDP_RD_PRIORITY__RD_VC0_PRIORITY_MASK 0x0000000FL 3452 #define DAGB1_SDP_RD_PRIORITY__RD_VC1_PRIORITY_MASK 0x000000F0L 3453 #define DAGB1_SDP_RD_PRIORITY__RD_VC2_PRIORITY_MASK 0x00000F00L 3454 #define DAGB1_SDP_RD_PRIORITY__RD_VC3_PRIORITY_MASK 0x0000F000L 3455 #define DAGB1_SDP_RD_PRIORITY__RD_VC4_PRIORITY_MASK 0x000F0000L 3456 #define DAGB1_SDP_RD_PRIORITY__RD_VC5_PRIORITY_MASK 0x00F00000L 3457 //DAGB1_SDP_RD_CLI2SDP_VC_MAP 3458 #define DAGB1_SDP_RD_CLI2SDP_VC_MAP__SRT_VC_MAP__SHIFT 0x0 3459 #define DAGB1_SDP_RD_CLI2SDP_VC_MAP__NRT_VC_MAP__SHIFT 0x3 3460 #define DAGB1_SDP_RD_CLI2SDP_VC_MAP__DLOCK_VC_MAP__SHIFT 0x6 3461 #define DAGB1_SDP_RD_CLI2SDP_VC_MAP__HRT_VC_MAP__SHIFT 0x9 3462 #define DAGB1_SDP_RD_CLI2SDP_VC_MAP__IO_VC_MAP__SHIFT 0xc 3463 #define DAGB1_SDP_RD_CLI2SDP_VC_MAP__GMI_VC_MAP__SHIFT 0xf 3464 #define DAGB1_SDP_RD_CLI2SDP_VC_MAP__SRT_VC_MAP_MASK 0x00000007L 3465 #define DAGB1_SDP_RD_CLI2SDP_VC_MAP__NRT_VC_MAP_MASK 0x00000038L 3466 #define DAGB1_SDP_RD_CLI2SDP_VC_MAP__DLOCK_VC_MAP_MASK 0x000001C0L 3467 #define DAGB1_SDP_RD_CLI2SDP_VC_MAP__HRT_VC_MAP_MASK 0x00000E00L 3468 #define DAGB1_SDP_RD_CLI2SDP_VC_MAP__IO_VC_MAP_MASK 0x00007000L 3469 #define DAGB1_SDP_RD_CLI2SDP_VC_MAP__GMI_VC_MAP_MASK 0x00038000L 3470 //DAGB1_SDP_ENABLE 3471 #define DAGB1_SDP_ENABLE__ENABLE__SHIFT 0x0 3472 #define DAGB1_SDP_ENABLE__ENABLE_MASK 0x00000001L 3473 //DAGB1_SDP_CREDITS 3474 #define DAGB1_SDP_CREDITS__TAG_LIMIT__SHIFT 0x0 3475 #define DAGB1_SDP_CREDITS__WR_RESP_CREDITS__SHIFT 0x8 3476 #define DAGB1_SDP_CREDITS__RD_RESP_CREDITS__SHIFT 0x10 3477 #define DAGB1_SDP_CREDITS__TAG_LIMIT_MASK 0x000000FFL 3478 #define DAGB1_SDP_CREDITS__WR_RESP_CREDITS_MASK 0x00007F00L 3479 #define DAGB1_SDP_CREDITS__RD_RESP_CREDITS_MASK 0x01FF0000L 3480 //DAGB1_SDP_TAG_RESERVE0 3481 #define DAGB1_SDP_TAG_RESERVE0__VC0__SHIFT 0x0 3482 #define DAGB1_SDP_TAG_RESERVE0__VC1__SHIFT 0x8 3483 #define DAGB1_SDP_TAG_RESERVE0__VC2__SHIFT 0x10 3484 #define DAGB1_SDP_TAG_RESERVE0__VC3__SHIFT 0x18 3485 #define DAGB1_SDP_TAG_RESERVE0__VC0_MASK 0x000000FFL 3486 #define DAGB1_SDP_TAG_RESERVE0__VC1_MASK 0x0000FF00L 3487 #define DAGB1_SDP_TAG_RESERVE0__VC2_MASK 0x00FF0000L 3488 #define DAGB1_SDP_TAG_RESERVE0__VC3_MASK 0xFF000000L 3489 //DAGB1_SDP_TAG_RESERVE1 3490 #define DAGB1_SDP_TAG_RESERVE1__VC4__SHIFT 0x0 3491 #define DAGB1_SDP_TAG_RESERVE1__VC5__SHIFT 0x8 3492 #define DAGB1_SDP_TAG_RESERVE1__VC6__SHIFT 0x10 3493 #define DAGB1_SDP_TAG_RESERVE1__VC7__SHIFT 0x18 3494 #define DAGB1_SDP_TAG_RESERVE1__VC4_MASK 0x000000FFL 3495 #define DAGB1_SDP_TAG_RESERVE1__VC5_MASK 0x0000FF00L 3496 #define DAGB1_SDP_TAG_RESERVE1__VC6_MASK 0x00FF0000L 3497 #define DAGB1_SDP_TAG_RESERVE1__VC7_MASK 0xFF000000L 3498 //DAGB1_SDP_VCC_RESERVE0 3499 #define DAGB1_SDP_VCC_RESERVE0__VC0_CREDITS__SHIFT 0x0 3500 #define DAGB1_SDP_VCC_RESERVE0__VC1_CREDITS__SHIFT 0x6 3501 #define DAGB1_SDP_VCC_RESERVE0__VC2_CREDITS__SHIFT 0xc 3502 #define DAGB1_SDP_VCC_RESERVE0__VC3_CREDITS__SHIFT 0x12 3503 #define DAGB1_SDP_VCC_RESERVE0__VC4_CREDITS__SHIFT 0x18 3504 #define DAGB1_SDP_VCC_RESERVE0__VC0_CREDITS_MASK 0x0000003FL 3505 #define DAGB1_SDP_VCC_RESERVE0__VC1_CREDITS_MASK 0x00000FC0L 3506 #define DAGB1_SDP_VCC_RESERVE0__VC2_CREDITS_MASK 0x0003F000L 3507 #define DAGB1_SDP_VCC_RESERVE0__VC3_CREDITS_MASK 0x00FC0000L 3508 #define DAGB1_SDP_VCC_RESERVE0__VC4_CREDITS_MASK 0x3F000000L 3509 //DAGB1_SDP_VCC_RESERVE1 3510 #define DAGB1_SDP_VCC_RESERVE1__VC5_CREDITS__SHIFT 0x0 3511 #define DAGB1_SDP_VCC_RESERVE1__VC6_CREDITS__SHIFT 0x6 3512 #define DAGB1_SDP_VCC_RESERVE1__VC7_CREDITS__SHIFT 0xc 3513 #define DAGB1_SDP_VCC_RESERVE1__DISTRIBUTE_POOL__SHIFT 0x1f 3514 #define DAGB1_SDP_VCC_RESERVE1__VC5_CREDITS_MASK 0x0000003FL 3515 #define DAGB1_SDP_VCC_RESERVE1__VC6_CREDITS_MASK 0x00000FC0L 3516 #define DAGB1_SDP_VCC_RESERVE1__VC7_CREDITS_MASK 0x0003F000L 3517 #define DAGB1_SDP_VCC_RESERVE1__DISTRIBUTE_POOL_MASK 0x80000000L 3518 //DAGB1_SDP_ERR_STATUS 3519 #define DAGB1_SDP_ERR_STATUS__SDP_RDRSP_STATUS__SHIFT 0x0 3520 #define DAGB1_SDP_ERR_STATUS__SDP_WRRSP_STATUS__SHIFT 0x4 3521 #define DAGB1_SDP_ERR_STATUS__SDP_RDRSP_DATASTATUS__SHIFT 0x8 3522 #define DAGB1_SDP_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR__SHIFT 0xa 3523 #define DAGB1_SDP_ERR_STATUS__CLEAR_ERROR_STATUS__SHIFT 0xb 3524 #define DAGB1_SDP_ERR_STATUS__BUSY_ON_ERROR__SHIFT 0xc 3525 #define DAGB1_SDP_ERR_STATUS__FUE_FLAG__SHIFT 0xd 3526 #define DAGB1_SDP_ERR_STATUS__IGNORE_RDRSP_FED__SHIFT 0xe 3527 #define DAGB1_SDP_ERR_STATUS__INTERRUPT_ON_FATAL__SHIFT 0xf 3528 #define DAGB1_SDP_ERR_STATUS__INTERRUPT_IGNORE_CLI_FATAL__SHIFT 0x10 3529 #define DAGB1_SDP_ERR_STATUS__LEVEL_INTERRUPT__SHIFT 0x11 3530 #define DAGB1_SDP_ERR_STATUS__BUSY_ON_CMPL_FATAL_ERROR__SHIFT 0x12 3531 #define DAGB1_SDP_ERR_STATUS__SDP_RDRSP_STATUS_MASK 0x0000000FL 3532 #define DAGB1_SDP_ERR_STATUS__SDP_WRRSP_STATUS_MASK 0x000000F0L 3533 #define DAGB1_SDP_ERR_STATUS__SDP_RDRSP_DATASTATUS_MASK 0x00000300L 3534 #define DAGB1_SDP_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR_MASK 0x00000400L 3535 #define DAGB1_SDP_ERR_STATUS__CLEAR_ERROR_STATUS_MASK 0x00000800L 3536 #define DAGB1_SDP_ERR_STATUS__BUSY_ON_ERROR_MASK 0x00001000L 3537 #define DAGB1_SDP_ERR_STATUS__FUE_FLAG_MASK 0x00002000L 3538 #define DAGB1_SDP_ERR_STATUS__IGNORE_RDRSP_FED_MASK 0x00004000L 3539 #define DAGB1_SDP_ERR_STATUS__INTERRUPT_ON_FATAL_MASK 0x00008000L 3540 #define DAGB1_SDP_ERR_STATUS__INTERRUPT_IGNORE_CLI_FATAL_MASK 0x00010000L 3541 #define DAGB1_SDP_ERR_STATUS__LEVEL_INTERRUPT_MASK 0x00020000L 3542 #define DAGB1_SDP_ERR_STATUS__BUSY_ON_CMPL_FATAL_ERROR_MASK 0x00040000L 3543 //DAGB1_SDP_REQ_CNTL 3544 #define DAGB1_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_READ__SHIFT 0x0 3545 #define DAGB1_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_WRITE__SHIFT 0x1 3546 #define DAGB1_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_ATOMIC__SHIFT 0x2 3547 #define DAGB1_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_DRAM__SHIFT 0x3 3548 #define DAGB1_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_GMI__SHIFT 0x4 3549 #define DAGB1_SDP_REQ_CNTL__INNER_DOMAIN_MODE__SHIFT 0x5 3550 #define DAGB1_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_READ__SHIFT 0x6 3551 #define DAGB1_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_WRITE__SHIFT 0x8 3552 #define DAGB1_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_ATOMIC__SHIFT 0xa 3553 #define DAGB1_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_READ_MASK 0x00000001L 3554 #define DAGB1_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_WRITE_MASK 0x00000002L 3555 #define DAGB1_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_ATOMIC_MASK 0x00000004L 3556 #define DAGB1_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_DRAM_MASK 0x00000008L 3557 #define DAGB1_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_GMI_MASK 0x00000010L 3558 #define DAGB1_SDP_REQ_CNTL__INNER_DOMAIN_MODE_MASK 0x00000020L 3559 #define DAGB1_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_READ_MASK 0x000000C0L 3560 #define DAGB1_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_WRITE_MASK 0x00000300L 3561 #define DAGB1_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_ATOMIC_MASK 0x00000C00L 3562 //DAGB1_SDP_MISC 3563 #define DAGB1_SDP_MISC__EARLYWRRET_ENABLE_VC0__SHIFT 0x0 3564 #define DAGB1_SDP_MISC__EARLYWRRET_ENABLE_VC1__SHIFT 0x1 3565 #define DAGB1_SDP_MISC__EARLYWRRET_ENABLE_VC2__SHIFT 0x2 3566 #define DAGB1_SDP_MISC__EARLYWRRET_ENABLE_VC3__SHIFT 0x3 3567 #define DAGB1_SDP_MISC__EARLYWRRET_ENABLE_VC4__SHIFT 0x4 3568 #define DAGB1_SDP_MISC__EARLYWRRET_ENABLE_VC5__SHIFT 0x5 3569 #define DAGB1_SDP_MISC__EARLYWRRET_ENABLE_VC6__SHIFT 0x6 3570 #define DAGB1_SDP_MISC__EARLYWRRET_ENABLE_VC7__SHIFT 0x7 3571 #define DAGB1_SDP_MISC__EARLY_SDP_ORIGDATA__SHIFT 0x8 3572 #define DAGB1_SDP_MISC__LINKMGR_DYNAMIC_MODE__SHIFT 0x9 3573 #define DAGB1_SDP_MISC__LINKMGR_HALT_THRESHOLD__SHIFT 0xb 3574 #define DAGB1_SDP_MISC__LINKMGR_RECONNECT_DELAY__SHIFT 0xd 3575 #define DAGB1_SDP_MISC__LINKMGR_IDLE_THRESHOLD__SHIFT 0xf 3576 #define DAGB1_SDP_MISC__SDP_DAT_FIFO0_MARGIN__SHIFT 0x14 3577 #define DAGB1_SDP_MISC__SDP_DAT_FIFO1_MARGIN__SHIFT 0x15 3578 #define DAGB1_SDP_MISC__EARLYWRRET_ENABLE_VC0_MASK 0x00000001L 3579 #define DAGB1_SDP_MISC__EARLYWRRET_ENABLE_VC1_MASK 0x00000002L 3580 #define DAGB1_SDP_MISC__EARLYWRRET_ENABLE_VC2_MASK 0x00000004L 3581 #define DAGB1_SDP_MISC__EARLYWRRET_ENABLE_VC3_MASK 0x00000008L 3582 #define DAGB1_SDP_MISC__EARLYWRRET_ENABLE_VC4_MASK 0x00000010L 3583 #define DAGB1_SDP_MISC__EARLYWRRET_ENABLE_VC5_MASK 0x00000020L 3584 #define DAGB1_SDP_MISC__EARLYWRRET_ENABLE_VC6_MASK 0x00000040L 3585 #define DAGB1_SDP_MISC__EARLYWRRET_ENABLE_VC7_MASK 0x00000080L 3586 #define DAGB1_SDP_MISC__EARLY_SDP_ORIGDATA_MASK 0x00000100L 3587 #define DAGB1_SDP_MISC__LINKMGR_DYNAMIC_MODE_MASK 0x00000600L 3588 #define DAGB1_SDP_MISC__LINKMGR_HALT_THRESHOLD_MASK 0x00001800L 3589 #define DAGB1_SDP_MISC__LINKMGR_RECONNECT_DELAY_MASK 0x00006000L 3590 #define DAGB1_SDP_MISC__LINKMGR_IDLE_THRESHOLD_MASK 0x000F8000L 3591 #define DAGB1_SDP_MISC__SDP_DAT_FIFO0_MARGIN_MASK 0x00100000L 3592 #define DAGB1_SDP_MISC__SDP_DAT_FIFO1_MARGIN_MASK 0x00200000L 3593 //DAGB1_SDP_MISC2 3594 #define DAGB1_SDP_MISC2__RRET_SWAP_MODE__SHIFT 0x0 3595 #define DAGB1_SDP_MISC2__BLOCK_REQUESTS__SHIFT 0x1 3596 #define DAGB1_SDP_MISC2__REQUESTS_BLOCKED__SHIFT 0x2 3597 #define DAGB1_SDP_MISC2__RDRSP_CR_RELEASE_MODE__SHIFT 0x3 3598 #define DAGB1_SDP_MISC2__RRET_SWAP_MODE_MASK 0x00000001L 3599 #define DAGB1_SDP_MISC2__BLOCK_REQUESTS_MASK 0x00000002L 3600 #define DAGB1_SDP_MISC2__REQUESTS_BLOCKED_MASK 0x00000004L 3601 #define DAGB1_SDP_MISC2__RDRSP_CR_RELEASE_MODE_MASK 0x00000008L 3602 //DAGB1_SDP_ARB_CNTL0 3603 #define DAGB1_SDP_ARB_CNTL0__EARLY_SW2RD_ON_PRI__SHIFT 0x0 3604 #define DAGB1_SDP_ARB_CNTL0__EARLY_SW2WR_ON_PRI__SHIFT 0x1 3605 #define DAGB1_SDP_ARB_CNTL0__EARLY_SW2RD_ON_RES__SHIFT 0x2 3606 #define DAGB1_SDP_ARB_CNTL0__EARLY_SW2WR_ON_RES__SHIFT 0x3 3607 #define DAGB1_SDP_ARB_CNTL0__RW_SWITCH_POP_MODE__SHIFT 0x4 3608 #define DAGB1_SDP_ARB_CNTL0__ERREVENT_ON_ERROR__SHIFT 0x5 3609 #define DAGB1_SDP_ARB_CNTL0__HALTREQ_ON_ERROR__SHIFT 0x6 3610 #define DAGB1_SDP_ARB_CNTL0__DED_MODE__SHIFT 0x7 3611 #define DAGB1_SDP_ARB_CNTL0__EARLY_SW2RD_ON_PRI_MASK 0x00000001L 3612 #define DAGB1_SDP_ARB_CNTL0__EARLY_SW2WR_ON_PRI_MASK 0x00000002L 3613 #define DAGB1_SDP_ARB_CNTL0__EARLY_SW2RD_ON_RES_MASK 0x00000004L 3614 #define DAGB1_SDP_ARB_CNTL0__EARLY_SW2WR_ON_RES_MASK 0x00000008L 3615 #define DAGB1_SDP_ARB_CNTL0__RW_SWITCH_POP_MODE_MASK 0x00000010L 3616 #define DAGB1_SDP_ARB_CNTL0__ERREVENT_ON_ERROR_MASK 0x00000020L 3617 #define DAGB1_SDP_ARB_CNTL0__HALTREQ_ON_ERROR_MASK 0x00000040L 3618 #define DAGB1_SDP_ARB_CNTL0__DED_MODE_MASK 0x00000080L 3619 //DAGB1_SDP_ARB_CNTL1 3620 #define DAGB1_SDP_ARB_CNTL1__RD_BURST_LIMIT_CYCL__SHIFT 0x0 3621 #define DAGB1_SDP_ARB_CNTL1__WR_BURST_LIMIT_CYCL__SHIFT 0x8 3622 #define DAGB1_SDP_ARB_CNTL1__RD_BURST_LIMIT_DATA__SHIFT 0x10 3623 #define DAGB1_SDP_ARB_CNTL1__WR_BURST_LIMIT_DATA__SHIFT 0x18 3624 #define DAGB1_SDP_ARB_CNTL1__RD_BURST_LIMIT_CYCL_MASK 0x0000007FL 3625 #define DAGB1_SDP_ARB_CNTL1__WR_BURST_LIMIT_CYCL_MASK 0x00007F00L 3626 #define DAGB1_SDP_ARB_CNTL1__RD_BURST_LIMIT_DATA_MASK 0x007F0000L 3627 #define DAGB1_SDP_ARB_CNTL1__WR_BURST_LIMIT_DATA_MASK 0x7F000000L 3628 //DAGB1_SDP_CGTT_CLK_CTRL 3629 #define DAGB1_SDP_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 3630 #define DAGB1_SDP_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x5 3631 #define DAGB1_SDP_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS__SHIFT 0xd 3632 #define DAGB1_SDP_CGTT_CLK_CTRL__LS_DISABLE__SHIFT 0x1e 3633 #define DAGB1_SDP_CGTT_CLK_CTRL__BUSY_OVERRIDE__SHIFT 0x1f 3634 #define DAGB1_SDP_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000001FL 3635 #define DAGB1_SDP_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00001FE0L 3636 #define DAGB1_SDP_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS_MASK 0x1FFFE000L 3637 #define DAGB1_SDP_CGTT_CLK_CTRL__LS_DISABLE_MASK 0x40000000L 3638 #define DAGB1_SDP_CGTT_CLK_CTRL__BUSY_OVERRIDE_MASK 0x80000000L 3639 //DAGB1_SDP_LATENCY_SAMPLING 3640 #define DAGB1_SDP_LATENCY_SAMPLING__SAMPLER0_DRAM__SHIFT 0x0 3641 #define DAGB1_SDP_LATENCY_SAMPLING__SAMPLER1_DRAM__SHIFT 0x1 3642 #define DAGB1_SDP_LATENCY_SAMPLING__SAMPLER0_GMI__SHIFT 0x2 3643 #define DAGB1_SDP_LATENCY_SAMPLING__SAMPLER1_GMI__SHIFT 0x3 3644 #define DAGB1_SDP_LATENCY_SAMPLING__SAMPLER0_IO__SHIFT 0x4 3645 #define DAGB1_SDP_LATENCY_SAMPLING__SAMPLER1_IO__SHIFT 0x5 3646 #define DAGB1_SDP_LATENCY_SAMPLING__SAMPLER0_READ__SHIFT 0x6 3647 #define DAGB1_SDP_LATENCY_SAMPLING__SAMPLER1_READ__SHIFT 0x7 3648 #define DAGB1_SDP_LATENCY_SAMPLING__SAMPLER0_WRITE__SHIFT 0x8 3649 #define DAGB1_SDP_LATENCY_SAMPLING__SAMPLER1_WRITE__SHIFT 0x9 3650 #define DAGB1_SDP_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET__SHIFT 0xa 3651 #define DAGB1_SDP_LATENCY_SAMPLING__SAMPLER1_ATOMIC_RET__SHIFT 0xb 3652 #define DAGB1_SDP_LATENCY_SAMPLING__SAMPLER0_ATOMIC_NORET__SHIFT 0xc 3653 #define DAGB1_SDP_LATENCY_SAMPLING__SAMPLER1_ATOMIC_NORET__SHIFT 0xd 3654 #define DAGB1_SDP_LATENCY_SAMPLING__SAMPLER0_VC__SHIFT 0xe 3655 #define DAGB1_SDP_LATENCY_SAMPLING__SAMPLER1_VC__SHIFT 0x16 3656 #define DAGB1_SDP_LATENCY_SAMPLING__SAMPLER0_DRAM_MASK 0x00000001L 3657 #define DAGB1_SDP_LATENCY_SAMPLING__SAMPLER1_DRAM_MASK 0x00000002L 3658 #define DAGB1_SDP_LATENCY_SAMPLING__SAMPLER0_GMI_MASK 0x00000004L 3659 #define DAGB1_SDP_LATENCY_SAMPLING__SAMPLER1_GMI_MASK 0x00000008L 3660 #define DAGB1_SDP_LATENCY_SAMPLING__SAMPLER0_IO_MASK 0x00000010L 3661 #define DAGB1_SDP_LATENCY_SAMPLING__SAMPLER1_IO_MASK 0x00000020L 3662 #define DAGB1_SDP_LATENCY_SAMPLING__SAMPLER0_READ_MASK 0x00000040L 3663 #define DAGB1_SDP_LATENCY_SAMPLING__SAMPLER1_READ_MASK 0x00000080L 3664 #define DAGB1_SDP_LATENCY_SAMPLING__SAMPLER0_WRITE_MASK 0x00000100L 3665 #define DAGB1_SDP_LATENCY_SAMPLING__SAMPLER1_WRITE_MASK 0x00000200L 3666 #define DAGB1_SDP_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET_MASK 0x00000400L 3667 #define DAGB1_SDP_LATENCY_SAMPLING__SAMPLER1_ATOMIC_RET_MASK 0x00000800L 3668 #define DAGB1_SDP_LATENCY_SAMPLING__SAMPLER0_ATOMIC_NORET_MASK 0x00001000L 3669 #define DAGB1_SDP_LATENCY_SAMPLING__SAMPLER1_ATOMIC_NORET_MASK 0x00002000L 3670 #define DAGB1_SDP_LATENCY_SAMPLING__SAMPLER0_VC_MASK 0x003FC000L 3671 #define DAGB1_SDP_LATENCY_SAMPLING__SAMPLER1_VC_MASK 0x3FC00000L 3672 3673 3674 // addressBlock: mmhub_pctldec 3675 //PCTL_CTRL 3676 #define PCTL_CTRL__PG_ENABLE__SHIFT 0x0 3677 #define PCTL_CTRL__ALLOW_DEEP_SLEEP_MODE__SHIFT 0x1 3678 #define PCTL_CTRL__STCTRL_DAGB_IDLE_THRESHOLD__SHIFT 0xe 3679 #define PCTL_CTRL__STCTRL_IGNORE_PROTECTION_FAULT__SHIFT 0x13 3680 #define PCTL_CTRL__UTCL2_LEGACY_MODE__SHIFT 0x14 3681 #define PCTL_CTRL__SDP_DISCONNECT_MODE__SHIFT 0x15 3682 #define PCTL_CTRL__STCTRL_ZSC_IDLE_THRESHOLD__SHIFT 0x16 3683 #define PCTL_CTRL__ZSC_TIMER_ENABLE__SHIFT 0x1b 3684 #define PCTL_CTRL__Z9_PWRDOWN__SHIFT 0x1c 3685 #define PCTL_CTRL__Z9_PWRUP__SHIFT 0x1d 3686 #define PCTL_CTRL__SNR_DISABLE__SHIFT 0x1e 3687 #define PCTL_CTRL__WRACK_GUARD__SHIFT 0x1f 3688 #define PCTL_CTRL__PG_ENABLE_MASK 0x00000001L 3689 #define PCTL_CTRL__ALLOW_DEEP_SLEEP_MODE_MASK 0x0000000EL 3690 #define PCTL_CTRL__STCTRL_DAGB_IDLE_THRESHOLD_MASK 0x0007C000L 3691 #define PCTL_CTRL__STCTRL_IGNORE_PROTECTION_FAULT_MASK 0x00080000L 3692 #define PCTL_CTRL__UTCL2_LEGACY_MODE_MASK 0x00100000L 3693 #define PCTL_CTRL__SDP_DISCONNECT_MODE_MASK 0x00200000L 3694 #define PCTL_CTRL__STCTRL_ZSC_IDLE_THRESHOLD_MASK 0x07C00000L 3695 #define PCTL_CTRL__ZSC_TIMER_ENABLE_MASK 0x08000000L 3696 #define PCTL_CTRL__Z9_PWRDOWN_MASK 0x10000000L 3697 #define PCTL_CTRL__Z9_PWRUP_MASK 0x20000000L 3698 #define PCTL_CTRL__SNR_DISABLE_MASK 0x40000000L 3699 #define PCTL_CTRL__WRACK_GUARD_MASK 0x80000000L 3700 //PCTL_MMHUB_DEEPSLEEP_IB 3701 #define PCTL_MMHUB_DEEPSLEEP_IB__DS0__SHIFT 0x0 3702 #define PCTL_MMHUB_DEEPSLEEP_IB__DS1__SHIFT 0x1 3703 #define PCTL_MMHUB_DEEPSLEEP_IB__DS2__SHIFT 0x2 3704 #define PCTL_MMHUB_DEEPSLEEP_IB__DS3__SHIFT 0x3 3705 #define PCTL_MMHUB_DEEPSLEEP_IB__DS4__SHIFT 0x4 3706 #define PCTL_MMHUB_DEEPSLEEP_IB__DS5__SHIFT 0x5 3707 #define PCTL_MMHUB_DEEPSLEEP_IB__DS6__SHIFT 0x6 3708 #define PCTL_MMHUB_DEEPSLEEP_IB__DS7__SHIFT 0x7 3709 #define PCTL_MMHUB_DEEPSLEEP_IB__DS8__SHIFT 0x8 3710 #define PCTL_MMHUB_DEEPSLEEP_IB__DS9__SHIFT 0x9 3711 #define PCTL_MMHUB_DEEPSLEEP_IB__DS10__SHIFT 0xa 3712 #define PCTL_MMHUB_DEEPSLEEP_IB__DS11__SHIFT 0xb 3713 #define PCTL_MMHUB_DEEPSLEEP_IB__DS12__SHIFT 0xc 3714 #define PCTL_MMHUB_DEEPSLEEP_IB__DS13__SHIFT 0xd 3715 #define PCTL_MMHUB_DEEPSLEEP_IB__DS14__SHIFT 0xe 3716 #define PCTL_MMHUB_DEEPSLEEP_IB__DS15__SHIFT 0xf 3717 #define PCTL_MMHUB_DEEPSLEEP_IB__DS16__SHIFT 0x10 3718 #define PCTL_MMHUB_DEEPSLEEP_IB__SETCLEAR__SHIFT 0x1f 3719 #define PCTL_MMHUB_DEEPSLEEP_IB__DS0_MASK 0x00000001L 3720 #define PCTL_MMHUB_DEEPSLEEP_IB__DS1_MASK 0x00000002L 3721 #define PCTL_MMHUB_DEEPSLEEP_IB__DS2_MASK 0x00000004L 3722 #define PCTL_MMHUB_DEEPSLEEP_IB__DS3_MASK 0x00000008L 3723 #define PCTL_MMHUB_DEEPSLEEP_IB__DS4_MASK 0x00000010L 3724 #define PCTL_MMHUB_DEEPSLEEP_IB__DS5_MASK 0x00000020L 3725 #define PCTL_MMHUB_DEEPSLEEP_IB__DS6_MASK 0x00000040L 3726 #define PCTL_MMHUB_DEEPSLEEP_IB__DS7_MASK 0x00000080L 3727 #define PCTL_MMHUB_DEEPSLEEP_IB__DS8_MASK 0x00000100L 3728 #define PCTL_MMHUB_DEEPSLEEP_IB__DS9_MASK 0x00000200L 3729 #define PCTL_MMHUB_DEEPSLEEP_IB__DS10_MASK 0x00000400L 3730 #define PCTL_MMHUB_DEEPSLEEP_IB__DS11_MASK 0x00000800L 3731 #define PCTL_MMHUB_DEEPSLEEP_IB__DS12_MASK 0x00001000L 3732 #define PCTL_MMHUB_DEEPSLEEP_IB__DS13_MASK 0x00002000L 3733 #define PCTL_MMHUB_DEEPSLEEP_IB__DS14_MASK 0x00004000L 3734 #define PCTL_MMHUB_DEEPSLEEP_IB__DS15_MASK 0x00008000L 3735 #define PCTL_MMHUB_DEEPSLEEP_IB__DS16_MASK 0x00010000L 3736 #define PCTL_MMHUB_DEEPSLEEP_IB__SETCLEAR_MASK 0x80000000L 3737 //PCTL_MMHUB_DEEPSLEEP_OVERRIDE 3738 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS0__SHIFT 0x0 3739 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS1__SHIFT 0x1 3740 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS2__SHIFT 0x2 3741 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS3__SHIFT 0x3 3742 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS4__SHIFT 0x4 3743 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS5__SHIFT 0x5 3744 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS6__SHIFT 0x6 3745 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS7__SHIFT 0x7 3746 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS8__SHIFT 0x8 3747 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS9__SHIFT 0x9 3748 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS10__SHIFT 0xa 3749 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS11__SHIFT 0xb 3750 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS12__SHIFT 0xc 3751 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS13__SHIFT 0xd 3752 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS14__SHIFT 0xe 3753 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS15__SHIFT 0xf 3754 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS16__SHIFT 0x10 3755 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS_ATHUB__SHIFT 0x11 3756 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS0_MASK 0x00000001L 3757 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS1_MASK 0x00000002L 3758 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS2_MASK 0x00000004L 3759 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS3_MASK 0x00000008L 3760 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS4_MASK 0x00000010L 3761 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS5_MASK 0x00000020L 3762 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS6_MASK 0x00000040L 3763 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS7_MASK 0x00000080L 3764 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS8_MASK 0x00000100L 3765 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS9_MASK 0x00000200L 3766 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS10_MASK 0x00000400L 3767 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS11_MASK 0x00000800L 3768 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS12_MASK 0x00001000L 3769 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS13_MASK 0x00002000L 3770 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS14_MASK 0x00004000L 3771 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS15_MASK 0x00008000L 3772 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS16_MASK 0x00010000L 3773 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS_ATHUB_MASK 0x00020000L 3774 //PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB 3775 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS0__SHIFT 0x0 3776 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS1__SHIFT 0x1 3777 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS2__SHIFT 0x2 3778 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS3__SHIFT 0x3 3779 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS4__SHIFT 0x4 3780 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS5__SHIFT 0x5 3781 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS6__SHIFT 0x6 3782 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS7__SHIFT 0x7 3783 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS8__SHIFT 0x8 3784 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS9__SHIFT 0x9 3785 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS10__SHIFT 0xa 3786 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS11__SHIFT 0xb 3787 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS12__SHIFT 0xc 3788 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS13__SHIFT 0xd 3789 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS14__SHIFT 0xe 3790 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS15__SHIFT 0xf 3791 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS16__SHIFT 0x10 3792 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS0_MASK 0x00000001L 3793 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS1_MASK 0x00000002L 3794 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS2_MASK 0x00000004L 3795 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS3_MASK 0x00000008L 3796 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS4_MASK 0x00000010L 3797 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS5_MASK 0x00000020L 3798 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS6_MASK 0x00000040L 3799 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS7_MASK 0x00000080L 3800 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS8_MASK 0x00000100L 3801 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS9_MASK 0x00000200L 3802 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS10_MASK 0x00000400L 3803 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS11_MASK 0x00000800L 3804 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS12_MASK 0x00001000L 3805 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS13_MASK 0x00002000L 3806 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS14_MASK 0x00004000L 3807 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS15_MASK 0x00008000L 3808 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS16_MASK 0x00010000L 3809 //PCTL_PG_IGNORE_DEEPSLEEP 3810 #define PCTL_PG_IGNORE_DEEPSLEEP__DS0__SHIFT 0x0 3811 #define PCTL_PG_IGNORE_DEEPSLEEP__DS1__SHIFT 0x1 3812 #define PCTL_PG_IGNORE_DEEPSLEEP__DS2__SHIFT 0x2 3813 #define PCTL_PG_IGNORE_DEEPSLEEP__DS3__SHIFT 0x3 3814 #define PCTL_PG_IGNORE_DEEPSLEEP__DS4__SHIFT 0x4 3815 #define PCTL_PG_IGNORE_DEEPSLEEP__DS5__SHIFT 0x5 3816 #define PCTL_PG_IGNORE_DEEPSLEEP__DS6__SHIFT 0x6 3817 #define PCTL_PG_IGNORE_DEEPSLEEP__DS7__SHIFT 0x7 3818 #define PCTL_PG_IGNORE_DEEPSLEEP__DS8__SHIFT 0x8 3819 #define PCTL_PG_IGNORE_DEEPSLEEP__DS9__SHIFT 0x9 3820 #define PCTL_PG_IGNORE_DEEPSLEEP__DS10__SHIFT 0xa 3821 #define PCTL_PG_IGNORE_DEEPSLEEP__DS11__SHIFT 0xb 3822 #define PCTL_PG_IGNORE_DEEPSLEEP__DS12__SHIFT 0xc 3823 #define PCTL_PG_IGNORE_DEEPSLEEP__DS13__SHIFT 0xd 3824 #define PCTL_PG_IGNORE_DEEPSLEEP__DS14__SHIFT 0xe 3825 #define PCTL_PG_IGNORE_DEEPSLEEP__DS15__SHIFT 0xf 3826 #define PCTL_PG_IGNORE_DEEPSLEEP__DS16__SHIFT 0x10 3827 #define PCTL_PG_IGNORE_DEEPSLEEP__DS_ATHUB__SHIFT 0x11 3828 #define PCTL_PG_IGNORE_DEEPSLEEP__ALLIPS__SHIFT 0x12 3829 #define PCTL_PG_IGNORE_DEEPSLEEP__DS0_MASK 0x00000001L 3830 #define PCTL_PG_IGNORE_DEEPSLEEP__DS1_MASK 0x00000002L 3831 #define PCTL_PG_IGNORE_DEEPSLEEP__DS2_MASK 0x00000004L 3832 #define PCTL_PG_IGNORE_DEEPSLEEP__DS3_MASK 0x00000008L 3833 #define PCTL_PG_IGNORE_DEEPSLEEP__DS4_MASK 0x00000010L 3834 #define PCTL_PG_IGNORE_DEEPSLEEP__DS5_MASK 0x00000020L 3835 #define PCTL_PG_IGNORE_DEEPSLEEP__DS6_MASK 0x00000040L 3836 #define PCTL_PG_IGNORE_DEEPSLEEP__DS7_MASK 0x00000080L 3837 #define PCTL_PG_IGNORE_DEEPSLEEP__DS8_MASK 0x00000100L 3838 #define PCTL_PG_IGNORE_DEEPSLEEP__DS9_MASK 0x00000200L 3839 #define PCTL_PG_IGNORE_DEEPSLEEP__DS10_MASK 0x00000400L 3840 #define PCTL_PG_IGNORE_DEEPSLEEP__DS11_MASK 0x00000800L 3841 #define PCTL_PG_IGNORE_DEEPSLEEP__DS12_MASK 0x00001000L 3842 #define PCTL_PG_IGNORE_DEEPSLEEP__DS13_MASK 0x00002000L 3843 #define PCTL_PG_IGNORE_DEEPSLEEP__DS14_MASK 0x00004000L 3844 #define PCTL_PG_IGNORE_DEEPSLEEP__DS15_MASK 0x00008000L 3845 #define PCTL_PG_IGNORE_DEEPSLEEP__DS16_MASK 0x00010000L 3846 #define PCTL_PG_IGNORE_DEEPSLEEP__DS_ATHUB_MASK 0x00020000L 3847 #define PCTL_PG_IGNORE_DEEPSLEEP__ALLIPS_MASK 0x00040000L 3848 //PCTL_PG_IGNORE_DEEPSLEEP_IB 3849 #define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS0__SHIFT 0x0 3850 #define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS1__SHIFT 0x1 3851 #define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS2__SHIFT 0x2 3852 #define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS3__SHIFT 0x3 3853 #define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS4__SHIFT 0x4 3854 #define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS5__SHIFT 0x5 3855 #define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS6__SHIFT 0x6 3856 #define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS7__SHIFT 0x7 3857 #define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS8__SHIFT 0x8 3858 #define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS9__SHIFT 0x9 3859 #define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS10__SHIFT 0xa 3860 #define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS11__SHIFT 0xb 3861 #define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS12__SHIFT 0xc 3862 #define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS13__SHIFT 0xd 3863 #define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS14__SHIFT 0xe 3864 #define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS15__SHIFT 0xf 3865 #define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS16__SHIFT 0x10 3866 #define PCTL_PG_IGNORE_DEEPSLEEP_IB__ALLIPS__SHIFT 0x11 3867 #define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS0_MASK 0x00000001L 3868 #define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS1_MASK 0x00000002L 3869 #define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS2_MASK 0x00000004L 3870 #define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS3_MASK 0x00000008L 3871 #define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS4_MASK 0x00000010L 3872 #define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS5_MASK 0x00000020L 3873 #define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS6_MASK 0x00000040L 3874 #define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS7_MASK 0x00000080L 3875 #define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS8_MASK 0x00000100L 3876 #define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS9_MASK 0x00000200L 3877 #define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS10_MASK 0x00000400L 3878 #define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS11_MASK 0x00000800L 3879 #define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS12_MASK 0x00001000L 3880 #define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS13_MASK 0x00002000L 3881 #define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS14_MASK 0x00004000L 3882 #define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS15_MASK 0x00008000L 3883 #define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS16_MASK 0x00010000L 3884 #define PCTL_PG_IGNORE_DEEPSLEEP_IB__ALLIPS_MASK 0x00020000L 3885 //PCTL_SLICE0_CFG_DAGB_WRBUSY 3886 #define PCTL_SLICE0_CFG_DAGB_WRBUSY__DB_LNCFG__SHIFT 0x0 3887 #define PCTL_SLICE0_CFG_DAGB_WRBUSY__DB_LNCFG_MASK 0xFFFFFFFFL 3888 //PCTL_SLICE0_CFG_DAGB_RDBUSY 3889 #define PCTL_SLICE0_CFG_DAGB_RDBUSY__DB_LNCFG__SHIFT 0x0 3890 #define PCTL_SLICE0_CFG_DAGB_RDBUSY__DB_LNCFG_MASK 0xFFFFFFFFL 3891 //PCTL_SLICE0_CFG_DS_ALLOW 3892 #define PCTL_SLICE0_CFG_DS_ALLOW__DS0__SHIFT 0x0 3893 #define PCTL_SLICE0_CFG_DS_ALLOW__DS1__SHIFT 0x1 3894 #define PCTL_SLICE0_CFG_DS_ALLOW__DS2__SHIFT 0x2 3895 #define PCTL_SLICE0_CFG_DS_ALLOW__DS3__SHIFT 0x3 3896 #define PCTL_SLICE0_CFG_DS_ALLOW__DS4__SHIFT 0x4 3897 #define PCTL_SLICE0_CFG_DS_ALLOW__DS5__SHIFT 0x5 3898 #define PCTL_SLICE0_CFG_DS_ALLOW__DS6__SHIFT 0x6 3899 #define PCTL_SLICE0_CFG_DS_ALLOW__DS7__SHIFT 0x7 3900 #define PCTL_SLICE0_CFG_DS_ALLOW__DS8__SHIFT 0x8 3901 #define PCTL_SLICE0_CFG_DS_ALLOW__DS9__SHIFT 0x9 3902 #define PCTL_SLICE0_CFG_DS_ALLOW__DS10__SHIFT 0xa 3903 #define PCTL_SLICE0_CFG_DS_ALLOW__DS11__SHIFT 0xb 3904 #define PCTL_SLICE0_CFG_DS_ALLOW__DS12__SHIFT 0xc 3905 #define PCTL_SLICE0_CFG_DS_ALLOW__DS13__SHIFT 0xd 3906 #define PCTL_SLICE0_CFG_DS_ALLOW__DS14__SHIFT 0xe 3907 #define PCTL_SLICE0_CFG_DS_ALLOW__DS15__SHIFT 0xf 3908 #define PCTL_SLICE0_CFG_DS_ALLOW__DS16__SHIFT 0x10 3909 #define PCTL_SLICE0_CFG_DS_ALLOW__DS0_MASK 0x00000001L 3910 #define PCTL_SLICE0_CFG_DS_ALLOW__DS1_MASK 0x00000002L 3911 #define PCTL_SLICE0_CFG_DS_ALLOW__DS2_MASK 0x00000004L 3912 #define PCTL_SLICE0_CFG_DS_ALLOW__DS3_MASK 0x00000008L 3913 #define PCTL_SLICE0_CFG_DS_ALLOW__DS4_MASK 0x00000010L 3914 #define PCTL_SLICE0_CFG_DS_ALLOW__DS5_MASK 0x00000020L 3915 #define PCTL_SLICE0_CFG_DS_ALLOW__DS6_MASK 0x00000040L 3916 #define PCTL_SLICE0_CFG_DS_ALLOW__DS7_MASK 0x00000080L 3917 #define PCTL_SLICE0_CFG_DS_ALLOW__DS8_MASK 0x00000100L 3918 #define PCTL_SLICE0_CFG_DS_ALLOW__DS9_MASK 0x00000200L 3919 #define PCTL_SLICE0_CFG_DS_ALLOW__DS10_MASK 0x00000400L 3920 #define PCTL_SLICE0_CFG_DS_ALLOW__DS11_MASK 0x00000800L 3921 #define PCTL_SLICE0_CFG_DS_ALLOW__DS12_MASK 0x00001000L 3922 #define PCTL_SLICE0_CFG_DS_ALLOW__DS13_MASK 0x00002000L 3923 #define PCTL_SLICE0_CFG_DS_ALLOW__DS14_MASK 0x00004000L 3924 #define PCTL_SLICE0_CFG_DS_ALLOW__DS15_MASK 0x00008000L 3925 #define PCTL_SLICE0_CFG_DS_ALLOW__DS16_MASK 0x00010000L 3926 //PCTL_SLICE0_CFG_DS_ALLOW_IB 3927 #define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS0__SHIFT 0x0 3928 #define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS1__SHIFT 0x1 3929 #define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS2__SHIFT 0x2 3930 #define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS3__SHIFT 0x3 3931 #define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS4__SHIFT 0x4 3932 #define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS5__SHIFT 0x5 3933 #define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS6__SHIFT 0x6 3934 #define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS7__SHIFT 0x7 3935 #define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS8__SHIFT 0x8 3936 #define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS9__SHIFT 0x9 3937 #define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS10__SHIFT 0xa 3938 #define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS11__SHIFT 0xb 3939 #define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS12__SHIFT 0xc 3940 #define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS13__SHIFT 0xd 3941 #define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS14__SHIFT 0xe 3942 #define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS15__SHIFT 0xf 3943 #define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS16__SHIFT 0x10 3944 #define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS0_MASK 0x00000001L 3945 #define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS1_MASK 0x00000002L 3946 #define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS2_MASK 0x00000004L 3947 #define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS3_MASK 0x00000008L 3948 #define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS4_MASK 0x00000010L 3949 #define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS5_MASK 0x00000020L 3950 #define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS6_MASK 0x00000040L 3951 #define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS7_MASK 0x00000080L 3952 #define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS8_MASK 0x00000100L 3953 #define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS9_MASK 0x00000200L 3954 #define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS10_MASK 0x00000400L 3955 #define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS11_MASK 0x00000800L 3956 #define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS12_MASK 0x00001000L 3957 #define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS13_MASK 0x00002000L 3958 #define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS14_MASK 0x00004000L 3959 #define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS15_MASK 0x00008000L 3960 #define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS16_MASK 0x00010000L 3961 //PCTL_SLICE1_CFG_DAGB_WRBUSY 3962 #define PCTL_SLICE1_CFG_DAGB_WRBUSY__DB_LNCFG__SHIFT 0x0 3963 #define PCTL_SLICE1_CFG_DAGB_WRBUSY__DB_LNCFG_MASK 0xFFFFFFFFL 3964 //PCTL_SLICE1_CFG_DAGB_RDBUSY 3965 #define PCTL_SLICE1_CFG_DAGB_RDBUSY__DB_LNCFG__SHIFT 0x0 3966 #define PCTL_SLICE1_CFG_DAGB_RDBUSY__DB_LNCFG_MASK 0xFFFFFFFFL 3967 //PCTL_SLICE1_CFG_DS_ALLOW 3968 #define PCTL_SLICE1_CFG_DS_ALLOW__DS0__SHIFT 0x0 3969 #define PCTL_SLICE1_CFG_DS_ALLOW__DS1__SHIFT 0x1 3970 #define PCTL_SLICE1_CFG_DS_ALLOW__DS2__SHIFT 0x2 3971 #define PCTL_SLICE1_CFG_DS_ALLOW__DS3__SHIFT 0x3 3972 #define PCTL_SLICE1_CFG_DS_ALLOW__DS4__SHIFT 0x4 3973 #define PCTL_SLICE1_CFG_DS_ALLOW__DS5__SHIFT 0x5 3974 #define PCTL_SLICE1_CFG_DS_ALLOW__DS6__SHIFT 0x6 3975 #define PCTL_SLICE1_CFG_DS_ALLOW__DS7__SHIFT 0x7 3976 #define PCTL_SLICE1_CFG_DS_ALLOW__DS8__SHIFT 0x8 3977 #define PCTL_SLICE1_CFG_DS_ALLOW__DS9__SHIFT 0x9 3978 #define PCTL_SLICE1_CFG_DS_ALLOW__DS10__SHIFT 0xa 3979 #define PCTL_SLICE1_CFG_DS_ALLOW__DS11__SHIFT 0xb 3980 #define PCTL_SLICE1_CFG_DS_ALLOW__DS12__SHIFT 0xc 3981 #define PCTL_SLICE1_CFG_DS_ALLOW__DS13__SHIFT 0xd 3982 #define PCTL_SLICE1_CFG_DS_ALLOW__DS14__SHIFT 0xe 3983 #define PCTL_SLICE1_CFG_DS_ALLOW__DS15__SHIFT 0xf 3984 #define PCTL_SLICE1_CFG_DS_ALLOW__DS16__SHIFT 0x10 3985 #define PCTL_SLICE1_CFG_DS_ALLOW__DS0_MASK 0x00000001L 3986 #define PCTL_SLICE1_CFG_DS_ALLOW__DS1_MASK 0x00000002L 3987 #define PCTL_SLICE1_CFG_DS_ALLOW__DS2_MASK 0x00000004L 3988 #define PCTL_SLICE1_CFG_DS_ALLOW__DS3_MASK 0x00000008L 3989 #define PCTL_SLICE1_CFG_DS_ALLOW__DS4_MASK 0x00000010L 3990 #define PCTL_SLICE1_CFG_DS_ALLOW__DS5_MASK 0x00000020L 3991 #define PCTL_SLICE1_CFG_DS_ALLOW__DS6_MASK 0x00000040L 3992 #define PCTL_SLICE1_CFG_DS_ALLOW__DS7_MASK 0x00000080L 3993 #define PCTL_SLICE1_CFG_DS_ALLOW__DS8_MASK 0x00000100L 3994 #define PCTL_SLICE1_CFG_DS_ALLOW__DS9_MASK 0x00000200L 3995 #define PCTL_SLICE1_CFG_DS_ALLOW__DS10_MASK 0x00000400L 3996 #define PCTL_SLICE1_CFG_DS_ALLOW__DS11_MASK 0x00000800L 3997 #define PCTL_SLICE1_CFG_DS_ALLOW__DS12_MASK 0x00001000L 3998 #define PCTL_SLICE1_CFG_DS_ALLOW__DS13_MASK 0x00002000L 3999 #define PCTL_SLICE1_CFG_DS_ALLOW__DS14_MASK 0x00004000L 4000 #define PCTL_SLICE1_CFG_DS_ALLOW__DS15_MASK 0x00008000L 4001 #define PCTL_SLICE1_CFG_DS_ALLOW__DS16_MASK 0x00010000L 4002 //PCTL_SLICE1_CFG_DS_ALLOW_IB 4003 #define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS0__SHIFT 0x0 4004 #define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS1__SHIFT 0x1 4005 #define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS2__SHIFT 0x2 4006 #define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS3__SHIFT 0x3 4007 #define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS4__SHIFT 0x4 4008 #define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS5__SHIFT 0x5 4009 #define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS6__SHIFT 0x6 4010 #define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS7__SHIFT 0x7 4011 #define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS8__SHIFT 0x8 4012 #define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS9__SHIFT 0x9 4013 #define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS10__SHIFT 0xa 4014 #define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS11__SHIFT 0xb 4015 #define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS12__SHIFT 0xc 4016 #define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS13__SHIFT 0xd 4017 #define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS14__SHIFT 0xe 4018 #define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS15__SHIFT 0xf 4019 #define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS16__SHIFT 0x10 4020 #define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS0_MASK 0x00000001L 4021 #define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS1_MASK 0x00000002L 4022 #define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS2_MASK 0x00000004L 4023 #define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS3_MASK 0x00000008L 4024 #define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS4_MASK 0x00000010L 4025 #define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS5_MASK 0x00000020L 4026 #define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS6_MASK 0x00000040L 4027 #define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS7_MASK 0x00000080L 4028 #define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS8_MASK 0x00000100L 4029 #define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS9_MASK 0x00000200L 4030 #define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS10_MASK 0x00000400L 4031 #define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS11_MASK 0x00000800L 4032 #define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS12_MASK 0x00001000L 4033 #define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS13_MASK 0x00002000L 4034 #define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS14_MASK 0x00004000L 4035 #define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS15_MASK 0x00008000L 4036 #define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS16_MASK 0x00010000L 4037 //PCTL_UTCL2_MISC 4038 #define PCTL_UTCL2_MISC__CRITICAL_REGS_LOCK__SHIFT 0xb 4039 #define PCTL_UTCL2_MISC__TILE_IDLE_THRESHOLD__SHIFT 0xc 4040 #define PCTL_UTCL2_MISC__RENG_MEM_LS_ENABLE__SHIFT 0xf 4041 #define PCTL_UTCL2_MISC__STCTRL_FORCE_PGFSM_CMD_DONE__SHIFT 0x10 4042 #define PCTL_UTCL2_MISC__RENG_EXECUTE_ON_REG_UPDATE__SHIFT 0x11 4043 #define PCTL_UTCL2_MISC__RD_TIMER_ENABLE__SHIFT 0x12 4044 #define PCTL_UTCL2_MISC__RENG_MEM_DS_ENABLE__SHIFT 0x13 4045 #define PCTL_UTCL2_MISC__RENG_MEM_LS_TIMER__SHIFT 0x14 4046 #define PCTL_UTCL2_MISC__RENG_MEM_SLEEP_TIMER__SHIFT 0x1a 4047 #define PCTL_UTCL2_MISC__CRITICAL_REGS_LOCK_MASK 0x00000800L 4048 #define PCTL_UTCL2_MISC__TILE_IDLE_THRESHOLD_MASK 0x00007000L 4049 #define PCTL_UTCL2_MISC__RENG_MEM_LS_ENABLE_MASK 0x00008000L 4050 #define PCTL_UTCL2_MISC__STCTRL_FORCE_PGFSM_CMD_DONE_MASK 0x00010000L 4051 #define PCTL_UTCL2_MISC__RENG_EXECUTE_ON_REG_UPDATE_MASK 0x00020000L 4052 #define PCTL_UTCL2_MISC__RD_TIMER_ENABLE_MASK 0x00040000L 4053 #define PCTL_UTCL2_MISC__RENG_MEM_DS_ENABLE_MASK 0x00080000L 4054 #define PCTL_UTCL2_MISC__RENG_MEM_LS_TIMER_MASK 0x03F00000L 4055 #define PCTL_UTCL2_MISC__RENG_MEM_SLEEP_TIMER_MASK 0x3C000000L 4056 //PCTL_SLICE0_MISC 4057 #define PCTL_SLICE0_MISC__CRITICAL_REGS_LOCK__SHIFT 0xa 4058 #define PCTL_SLICE0_MISC__TILE_IDLE_THRESHOLD__SHIFT 0xb 4059 #define PCTL_SLICE0_MISC__RENG_MEM_LS_ENABLE__SHIFT 0xe 4060 #define PCTL_SLICE0_MISC__STCTRL_FORCE_PGFSM_CMD_DONE__SHIFT 0xf 4061 #define PCTL_SLICE0_MISC__DEEPSLEEP_DISCSDP__SHIFT 0x10 4062 #define PCTL_SLICE0_MISC__RENG_EXECUTE_ON_REG_UPDATE__SHIFT 0x11 4063 #define PCTL_SLICE0_MISC__RD_TIMER_ENABLE__SHIFT 0x12 4064 #define PCTL_SLICE0_MISC__RENG_MEM_DS_ENABLE__SHIFT 0x13 4065 #define PCTL_SLICE0_MISC__RENG_MEM_LS_TIMER__SHIFT 0x14 4066 #define PCTL_SLICE0_MISC__RENG_MEM_SLEEP_TIMER__SHIFT 0x1a 4067 #define PCTL_SLICE0_MISC__OVR_EA_SDP0_PARTACK__SHIFT 0x1e 4068 #define PCTL_SLICE0_MISC__OVR_EA_SDP0_FULLACK__SHIFT 0x1f 4069 #define PCTL_SLICE0_MISC__CRITICAL_REGS_LOCK_MASK 0x00000400L 4070 #define PCTL_SLICE0_MISC__TILE_IDLE_THRESHOLD_MASK 0x00003800L 4071 #define PCTL_SLICE0_MISC__RENG_MEM_LS_ENABLE_MASK 0x00004000L 4072 #define PCTL_SLICE0_MISC__STCTRL_FORCE_PGFSM_CMD_DONE_MASK 0x00008000L 4073 #define PCTL_SLICE0_MISC__DEEPSLEEP_DISCSDP_MASK 0x00010000L 4074 #define PCTL_SLICE0_MISC__RENG_EXECUTE_ON_REG_UPDATE_MASK 0x00020000L 4075 #define PCTL_SLICE0_MISC__RD_TIMER_ENABLE_MASK 0x00040000L 4076 #define PCTL_SLICE0_MISC__RENG_MEM_DS_ENABLE_MASK 0x00080000L 4077 #define PCTL_SLICE0_MISC__RENG_MEM_LS_TIMER_MASK 0x03F00000L 4078 #define PCTL_SLICE0_MISC__RENG_MEM_SLEEP_TIMER_MASK 0x3C000000L 4079 #define PCTL_SLICE0_MISC__OVR_EA_SDP0_PARTACK_MASK 0x40000000L 4080 #define PCTL_SLICE0_MISC__OVR_EA_SDP0_FULLACK_MASK 0x80000000L 4081 //PCTL_SLICE1_MISC 4082 #define PCTL_SLICE1_MISC__CRITICAL_REGS_LOCK__SHIFT 0xa 4083 #define PCTL_SLICE1_MISC__TILE_IDLE_THRESHOLD__SHIFT 0xb 4084 #define PCTL_SLICE1_MISC__RENG_MEM_LS_ENABLE__SHIFT 0xe 4085 #define PCTL_SLICE1_MISC__STCTRL_FORCE_PGFSM_CMD_DONE__SHIFT 0xf 4086 #define PCTL_SLICE1_MISC__DEEPSLEEP_DISCSDP__SHIFT 0x10 4087 #define PCTL_SLICE1_MISC__RENG_EXECUTE_ON_REG_UPDATE__SHIFT 0x11 4088 #define PCTL_SLICE1_MISC__RD_TIMER_ENABLE__SHIFT 0x12 4089 #define PCTL_SLICE1_MISC__RENG_MEM_DS_ENABLE__SHIFT 0x13 4090 #define PCTL_SLICE1_MISC__RENG_MEM_LS_TIMER__SHIFT 0x14 4091 #define PCTL_SLICE1_MISC__RENG_MEM_SLEEP_TIMER__SHIFT 0x1a 4092 #define PCTL_SLICE1_MISC__OVR_EA_SDP1_PARTACK__SHIFT 0x1e 4093 #define PCTL_SLICE1_MISC__OVR_EA_SDP1_FULLACK__SHIFT 0x1f 4094 #define PCTL_SLICE1_MISC__CRITICAL_REGS_LOCK_MASK 0x00000400L 4095 #define PCTL_SLICE1_MISC__TILE_IDLE_THRESHOLD_MASK 0x00003800L 4096 #define PCTL_SLICE1_MISC__RENG_MEM_LS_ENABLE_MASK 0x00004000L 4097 #define PCTL_SLICE1_MISC__STCTRL_FORCE_PGFSM_CMD_DONE_MASK 0x00008000L 4098 #define PCTL_SLICE1_MISC__DEEPSLEEP_DISCSDP_MASK 0x00010000L 4099 #define PCTL_SLICE1_MISC__RENG_EXECUTE_ON_REG_UPDATE_MASK 0x00020000L 4100 #define PCTL_SLICE1_MISC__RD_TIMER_ENABLE_MASK 0x00040000L 4101 #define PCTL_SLICE1_MISC__RENG_MEM_DS_ENABLE_MASK 0x00080000L 4102 #define PCTL_SLICE1_MISC__RENG_MEM_LS_TIMER_MASK 0x03F00000L 4103 #define PCTL_SLICE1_MISC__RENG_MEM_SLEEP_TIMER_MASK 0x3C000000L 4104 #define PCTL_SLICE1_MISC__OVR_EA_SDP1_PARTACK_MASK 0x40000000L 4105 #define PCTL_SLICE1_MISC__OVR_EA_SDP1_FULLACK_MASK 0x80000000L 4106 //PCTL_RENG_CTRL 4107 #define PCTL_RENG_CTRL__RENG_EXECUTE_NOW__SHIFT 0x0 4108 #define PCTL_RENG_CTRL__RENG_EXECUTE_NOW_MODE__SHIFT 0x1 4109 #define PCTL_RENG_CTRL__RENG_EXECUTE_NOW_MASK 0x00000001L 4110 #define PCTL_RENG_CTRL__RENG_EXECUTE_NOW_MODE_MASK 0x00000002L 4111 //PCTL_UTCL2_RENG_EXECUTE 4112 #define PCTL_UTCL2_RENG_EXECUTE__RENG_EXECUTE_NOW__SHIFT 0x0 4113 #define PCTL_UTCL2_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE__SHIFT 0x1 4114 #define PCTL_UTCL2_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR__SHIFT 0x2 4115 #define PCTL_UTCL2_RENG_EXECUTE__RENG_EXECUTE_END_PTR__SHIFT 0xd 4116 #define PCTL_UTCL2_RENG_EXECUTE__RENG_EXECUTE_NOW_MASK 0x00000001L 4117 #define PCTL_UTCL2_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE_MASK 0x00000002L 4118 #define PCTL_UTCL2_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR_MASK 0x00001FFCL 4119 #define PCTL_UTCL2_RENG_EXECUTE__RENG_EXECUTE_END_PTR_MASK 0x00FFE000L 4120 //PCTL_SLICE0_RENG_EXECUTE 4121 #define PCTL_SLICE0_RENG_EXECUTE__RENG_EXECUTE_NOW__SHIFT 0x0 4122 #define PCTL_SLICE0_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE__SHIFT 0x1 4123 #define PCTL_SLICE0_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR__SHIFT 0x2 4124 #define PCTL_SLICE0_RENG_EXECUTE__RENG_EXECUTE_END_PTR__SHIFT 0xc 4125 #define PCTL_SLICE0_RENG_EXECUTE__RENG_EXECUTE_NOW_MASK 0x00000001L 4126 #define PCTL_SLICE0_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE_MASK 0x00000002L 4127 #define PCTL_SLICE0_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR_MASK 0x00000FFCL 4128 #define PCTL_SLICE0_RENG_EXECUTE__RENG_EXECUTE_END_PTR_MASK 0x003FF000L 4129 //PCTL_SLICE1_RENG_EXECUTE 4130 #define PCTL_SLICE1_RENG_EXECUTE__RENG_EXECUTE_NOW__SHIFT 0x0 4131 #define PCTL_SLICE1_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE__SHIFT 0x1 4132 #define PCTL_SLICE1_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR__SHIFT 0x2 4133 #define PCTL_SLICE1_RENG_EXECUTE__RENG_EXECUTE_END_PTR__SHIFT 0xc 4134 #define PCTL_SLICE1_RENG_EXECUTE__RENG_EXECUTE_NOW_MASK 0x00000001L 4135 #define PCTL_SLICE1_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE_MASK 0x00000002L 4136 #define PCTL_SLICE1_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR_MASK 0x00000FFCL 4137 #define PCTL_SLICE1_RENG_EXECUTE__RENG_EXECUTE_END_PTR_MASK 0x003FF000L 4138 //PCTL_UTCL2_RENG_RAM_INDEX 4139 #define PCTL_UTCL2_RENG_RAM_INDEX__RENG_RAM_INDEX__SHIFT 0x0 4140 #define PCTL_UTCL2_RENG_RAM_INDEX__RENG_RAM_INDEX_MASK 0x000007FFL 4141 //PCTL_UTCL2_RENG_RAM_DATA 4142 #define PCTL_UTCL2_RENG_RAM_DATA__RENG_RAM_DATA__SHIFT 0x0 4143 #define PCTL_UTCL2_RENG_RAM_DATA__RENG_RAM_DATA_MASK 0xFFFFFFFFL 4144 //PCTL_SLICE0_RENG_RAM_INDEX 4145 #define PCTL_SLICE0_RENG_RAM_INDEX__RENG_RAM_INDEX__SHIFT 0x0 4146 #define PCTL_SLICE0_RENG_RAM_INDEX__RENG_RAM_INDEX_MASK 0x000003FFL 4147 //PCTL_SLICE0_RENG_RAM_DATA 4148 #define PCTL_SLICE0_RENG_RAM_DATA__RENG_RAM_DATA__SHIFT 0x0 4149 #define PCTL_SLICE0_RENG_RAM_DATA__RENG_RAM_DATA_MASK 0xFFFFFFFFL 4150 //PCTL_SLICE1_RENG_RAM_INDEX 4151 #define PCTL_SLICE1_RENG_RAM_INDEX__RENG_RAM_INDEX__SHIFT 0x0 4152 #define PCTL_SLICE1_RENG_RAM_INDEX__RENG_RAM_INDEX_MASK 0x000003FFL 4153 //PCTL_SLICE1_RENG_RAM_DATA 4154 #define PCTL_SLICE1_RENG_RAM_DATA__RENG_RAM_DATA__SHIFT 0x0 4155 #define PCTL_SLICE1_RENG_RAM_DATA__RENG_RAM_DATA_MASK 0xFFFFFFFFL 4156 //PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE0 4157 #define PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 4158 #define PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 4159 #define PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL 4160 #define PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L 4161 //PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE1 4162 #define PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 4163 #define PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 4164 #define PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL 4165 #define PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L 4166 //PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE2 4167 #define PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 4168 #define PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 4169 #define PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL 4170 #define PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L 4171 //PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE3 4172 #define PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 4173 #define PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 4174 #define PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL 4175 #define PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L 4176 //PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE4 4177 #define PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 4178 #define PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 4179 #define PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL 4180 #define PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L 4181 //PCTL_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET0 4182 #define PCTL_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL0__SHIFT 0x0 4183 #define PCTL_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL1__SHIFT 0x10 4184 #define PCTL_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL0_MASK 0x0000FFFFL 4185 #define PCTL_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL1_MASK 0xFFFF0000L 4186 //PCTL_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET1 4187 #define PCTL_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL2__SHIFT 0x0 4188 #define PCTL_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL3__SHIFT 0x10 4189 #define PCTL_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL2_MASK 0x0000FFFFL 4190 #define PCTL_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL3_MASK 0xFFFF0000L 4191 //PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE0 4192 #define PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 4193 #define PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 4194 #define PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL 4195 #define PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L 4196 //PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE1 4197 #define PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 4198 #define PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 4199 #define PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL 4200 #define PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L 4201 //PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE2 4202 #define PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 4203 #define PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 4204 #define PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL 4205 #define PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L 4206 //PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE3 4207 #define PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 4208 #define PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 4209 #define PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL 4210 #define PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L 4211 //PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE4 4212 #define PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 4213 #define PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 4214 #define PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL 4215 #define PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L 4216 //PCTL_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET0 4217 #define PCTL_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL0__SHIFT 0x0 4218 #define PCTL_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL1__SHIFT 0x10 4219 #define PCTL_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL0_MASK 0x0000FFFFL 4220 #define PCTL_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL1_MASK 0xFFFF0000L 4221 //PCTL_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET1 4222 #define PCTL_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL2__SHIFT 0x0 4223 #define PCTL_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL3__SHIFT 0x10 4224 #define PCTL_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL2_MASK 0x0000FFFFL 4225 #define PCTL_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL3_MASK 0xFFFF0000L 4226 //PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE0 4227 #define PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 4228 #define PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 4229 #define PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL 4230 #define PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L 4231 //PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE1 4232 #define PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 4233 #define PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 4234 #define PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL 4235 #define PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L 4236 //PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE2 4237 #define PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 4238 #define PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 4239 #define PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL 4240 #define PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L 4241 //PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE3 4242 #define PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 4243 #define PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 4244 #define PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL 4245 #define PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L 4246 //PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE4 4247 #define PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 4248 #define PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 4249 #define PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL 4250 #define PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L 4251 //PCTL_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET0 4252 #define PCTL_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL0__SHIFT 0x0 4253 #define PCTL_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL1__SHIFT 0x10 4254 #define PCTL_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL0_MASK 0x0000FFFFL 4255 #define PCTL_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL1_MASK 0xFFFF0000L 4256 //PCTL_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET1 4257 #define PCTL_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL2__SHIFT 0x0 4258 #define PCTL_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL3__SHIFT 0x10 4259 #define PCTL_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL2_MASK 0x0000FFFFL 4260 #define PCTL_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL3_MASK 0xFFFF0000L 4261 //PCTL_STATUS 4262 #define PCTL_STATUS__MMHUB_CONFIG_DONE__SHIFT 0x0 4263 #define PCTL_STATUS__MMHUB_INTERLOCK_ENABLE__SHIFT 0x1 4264 #define PCTL_STATUS__MMHUB_FENCE_REQ__SHIFT 0x2 4265 #define PCTL_STATUS__MMHUB_FENCE_ACK__SHIFT 0x3 4266 #define PCTL_STATUS__MMHUB_IDLE__SHIFT 0x4 4267 #define PCTL_STATUS__PGFSM_CMD_STATUS__SHIFT 0x5 4268 #define PCTL_STATUS__MMHUB_POWER__SHIFT 0x10 4269 #define PCTL_STATUS__RENG_RAM_STALE__SHIFT 0x11 4270 #define PCTL_STATUS__UTCL2_RENG_RAM_STALE__SHIFT 0x12 4271 #define PCTL_STATUS__SLICE0_RENG_RAM_STALE__SHIFT 0x13 4272 #define PCTL_STATUS__SLICE1_RENG_RAM_STALE__SHIFT 0x14 4273 #define PCTL_STATUS__MMHUB_CONFIG_DONE_MASK 0x00000001L 4274 #define PCTL_STATUS__MMHUB_INTERLOCK_ENABLE_MASK 0x00000002L 4275 #define PCTL_STATUS__MMHUB_FENCE_REQ_MASK 0x00000004L 4276 #define PCTL_STATUS__MMHUB_FENCE_ACK_MASK 0x00000008L 4277 #define PCTL_STATUS__MMHUB_IDLE_MASK 0x00000010L 4278 #define PCTL_STATUS__PGFSM_CMD_STATUS_MASK 0x00000060L 4279 #define PCTL_STATUS__MMHUB_POWER_MASK 0x00010000L 4280 #define PCTL_STATUS__RENG_RAM_STALE_MASK 0x00020000L 4281 #define PCTL_STATUS__UTCL2_RENG_RAM_STALE_MASK 0x00040000L 4282 #define PCTL_STATUS__SLICE0_RENG_RAM_STALE_MASK 0x00080000L 4283 #define PCTL_STATUS__SLICE1_RENG_RAM_STALE_MASK 0x00100000L 4284 //PCTL_PERFCOUNTER_LO 4285 #define PCTL_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 4286 #define PCTL_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL 4287 //PCTL_PERFCOUNTER_HI 4288 #define PCTL_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 4289 #define PCTL_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 4290 #define PCTL_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL 4291 #define PCTL_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L 4292 //PCTL_PERFCOUNTER0_CFG 4293 #define PCTL_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 4294 #define PCTL_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 4295 #define PCTL_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 4296 #define PCTL_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c 4297 #define PCTL_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d 4298 #define PCTL_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL 4299 #define PCTL_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L 4300 #define PCTL_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L 4301 #define PCTL_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L 4302 #define PCTL_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L 4303 //PCTL_PERFCOUNTER1_CFG 4304 #define PCTL_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 4305 #define PCTL_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 4306 #define PCTL_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 4307 #define PCTL_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c 4308 #define PCTL_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d 4309 #define PCTL_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL 4310 #define PCTL_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L 4311 #define PCTL_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L 4312 #define PCTL_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L 4313 #define PCTL_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L 4314 //PCTL_PERFCOUNTER_RSLT_CNTL 4315 #define PCTL_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 4316 #define PCTL_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 4317 #define PCTL_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 4318 #define PCTL_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 4319 #define PCTL_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 4320 #define PCTL_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a 4321 #define PCTL_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL 4322 #define PCTL_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L 4323 #define PCTL_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L 4324 #define PCTL_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L 4325 #define PCTL_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L 4326 #define PCTL_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L 4327 //PCTL_RESERVED_0 4328 #define PCTL_RESERVED_0__WORD__SHIFT 0x0 4329 #define PCTL_RESERVED_0__BYTE__SHIFT 0x10 4330 #define PCTL_RESERVED_0__BIT7__SHIFT 0x18 4331 #define PCTL_RESERVED_0__BIT6__SHIFT 0x19 4332 #define PCTL_RESERVED_0__BIT5__SHIFT 0x1a 4333 #define PCTL_RESERVED_0__BIT4__SHIFT 0x1b 4334 #define PCTL_RESERVED_0__BIT3__SHIFT 0x1c 4335 #define PCTL_RESERVED_0__BIT2__SHIFT 0x1d 4336 #define PCTL_RESERVED_0__BIT1__SHIFT 0x1e 4337 #define PCTL_RESERVED_0__BIT0__SHIFT 0x1f 4338 #define PCTL_RESERVED_0__WORD_MASK 0x0000FFFFL 4339 #define PCTL_RESERVED_0__BYTE_MASK 0x00FF0000L 4340 #define PCTL_RESERVED_0__BIT7_MASK 0x01000000L 4341 #define PCTL_RESERVED_0__BIT6_MASK 0x02000000L 4342 #define PCTL_RESERVED_0__BIT5_MASK 0x04000000L 4343 #define PCTL_RESERVED_0__BIT4_MASK 0x08000000L 4344 #define PCTL_RESERVED_0__BIT3_MASK 0x10000000L 4345 #define PCTL_RESERVED_0__BIT2_MASK 0x20000000L 4346 #define PCTL_RESERVED_0__BIT1_MASK 0x40000000L 4347 #define PCTL_RESERVED_0__BIT0_MASK 0x80000000L 4348 //PCTL_RESERVED_1 4349 #define PCTL_RESERVED_1__WORD__SHIFT 0x0 4350 #define PCTL_RESERVED_1__BYTE__SHIFT 0x10 4351 #define PCTL_RESERVED_1__BIT7__SHIFT 0x18 4352 #define PCTL_RESERVED_1__BIT6__SHIFT 0x19 4353 #define PCTL_RESERVED_1__BIT5__SHIFT 0x1a 4354 #define PCTL_RESERVED_1__BIT4__SHIFT 0x1b 4355 #define PCTL_RESERVED_1__BIT3__SHIFT 0x1c 4356 #define PCTL_RESERVED_1__BIT2__SHIFT 0x1d 4357 #define PCTL_RESERVED_1__BIT1__SHIFT 0x1e 4358 #define PCTL_RESERVED_1__BIT0__SHIFT 0x1f 4359 #define PCTL_RESERVED_1__WORD_MASK 0x0000FFFFL 4360 #define PCTL_RESERVED_1__BYTE_MASK 0x00FF0000L 4361 #define PCTL_RESERVED_1__BIT7_MASK 0x01000000L 4362 #define PCTL_RESERVED_1__BIT6_MASK 0x02000000L 4363 #define PCTL_RESERVED_1__BIT5_MASK 0x04000000L 4364 #define PCTL_RESERVED_1__BIT4_MASK 0x08000000L 4365 #define PCTL_RESERVED_1__BIT3_MASK 0x10000000L 4366 #define PCTL_RESERVED_1__BIT2_MASK 0x20000000L 4367 #define PCTL_RESERVED_1__BIT1_MASK 0x40000000L 4368 #define PCTL_RESERVED_1__BIT0_MASK 0x80000000L 4369 //PCTL_RESERVED_2 4370 #define PCTL_RESERVED_2__WORD__SHIFT 0x0 4371 #define PCTL_RESERVED_2__BYTE__SHIFT 0x10 4372 #define PCTL_RESERVED_2__BIT7__SHIFT 0x18 4373 #define PCTL_RESERVED_2__BIT6__SHIFT 0x19 4374 #define PCTL_RESERVED_2__BIT5__SHIFT 0x1a 4375 #define PCTL_RESERVED_2__BIT4__SHIFT 0x1b 4376 #define PCTL_RESERVED_2__BIT3__SHIFT 0x1c 4377 #define PCTL_RESERVED_2__BIT2__SHIFT 0x1d 4378 #define PCTL_RESERVED_2__BIT1__SHIFT 0x1e 4379 #define PCTL_RESERVED_2__BIT0__SHIFT 0x1f 4380 #define PCTL_RESERVED_2__WORD_MASK 0x0000FFFFL 4381 #define PCTL_RESERVED_2__BYTE_MASK 0x00FF0000L 4382 #define PCTL_RESERVED_2__BIT7_MASK 0x01000000L 4383 #define PCTL_RESERVED_2__BIT6_MASK 0x02000000L 4384 #define PCTL_RESERVED_2__BIT5_MASK 0x04000000L 4385 #define PCTL_RESERVED_2__BIT4_MASK 0x08000000L 4386 #define PCTL_RESERVED_2__BIT3_MASK 0x10000000L 4387 #define PCTL_RESERVED_2__BIT2_MASK 0x20000000L 4388 #define PCTL_RESERVED_2__BIT1_MASK 0x40000000L 4389 #define PCTL_RESERVED_2__BIT0_MASK 0x80000000L 4390 //PCTL_RESERVED_3 4391 #define PCTL_RESERVED_3__WORD__SHIFT 0x0 4392 #define PCTL_RESERVED_3__BYTE__SHIFT 0x10 4393 #define PCTL_RESERVED_3__BIT7__SHIFT 0x18 4394 #define PCTL_RESERVED_3__BIT6__SHIFT 0x19 4395 #define PCTL_RESERVED_3__BIT5__SHIFT 0x1a 4396 #define PCTL_RESERVED_3__BIT4__SHIFT 0x1b 4397 #define PCTL_RESERVED_3__BIT3__SHIFT 0x1c 4398 #define PCTL_RESERVED_3__BIT2__SHIFT 0x1d 4399 #define PCTL_RESERVED_3__BIT1__SHIFT 0x1e 4400 #define PCTL_RESERVED_3__BIT0__SHIFT 0x1f 4401 #define PCTL_RESERVED_3__WORD_MASK 0x0000FFFFL 4402 #define PCTL_RESERVED_3__BYTE_MASK 0x00FF0000L 4403 #define PCTL_RESERVED_3__BIT7_MASK 0x01000000L 4404 #define PCTL_RESERVED_3__BIT6_MASK 0x02000000L 4405 #define PCTL_RESERVED_3__BIT5_MASK 0x04000000L 4406 #define PCTL_RESERVED_3__BIT4_MASK 0x08000000L 4407 #define PCTL_RESERVED_3__BIT3_MASK 0x10000000L 4408 #define PCTL_RESERVED_3__BIT2_MASK 0x20000000L 4409 #define PCTL_RESERVED_3__BIT1_MASK 0x40000000L 4410 #define PCTL_RESERVED_3__BIT0_MASK 0x80000000L 4411 4412 4413 // addressBlock: mmhub_l1tlb_mmutcl1pfdec 4414 //MMMC_VM_MX_L1_TLB0_STATUS 4415 #define MMMC_VM_MX_L1_TLB0_STATUS__BUSY__SHIFT 0x0 4416 #define MMMC_VM_MX_L1_TLB0_STATUS__FOUND_PARITY_ERRORS__SHIFT 0x1 4417 #define MMMC_VM_MX_L1_TLB0_STATUS__FOUND_APERTURE_FAULTS__SHIFT 0x2 4418 #define MMMC_VM_MX_L1_TLB0_STATUS__BUSY_MASK 0x00000001L 4419 #define MMMC_VM_MX_L1_TLB0_STATUS__FOUND_PARITY_ERRORS_MASK 0x00000002L 4420 #define MMMC_VM_MX_L1_TLB0_STATUS__FOUND_APERTURE_FAULTS_MASK 0x00000004L 4421 //MMMC_VM_MX_L1_TLB1_STATUS 4422 #define MMMC_VM_MX_L1_TLB1_STATUS__BUSY__SHIFT 0x0 4423 #define MMMC_VM_MX_L1_TLB1_STATUS__FOUND_PARITY_ERRORS__SHIFT 0x1 4424 #define MMMC_VM_MX_L1_TLB1_STATUS__FOUND_APERTURE_FAULTS__SHIFT 0x2 4425 #define MMMC_VM_MX_L1_TLB1_STATUS__BUSY_MASK 0x00000001L 4426 #define MMMC_VM_MX_L1_TLB1_STATUS__FOUND_PARITY_ERRORS_MASK 0x00000002L 4427 #define MMMC_VM_MX_L1_TLB1_STATUS__FOUND_APERTURE_FAULTS_MASK 0x00000004L 4428 //MMMC_VM_MX_L1_TLB2_STATUS 4429 #define MMMC_VM_MX_L1_TLB2_STATUS__BUSY__SHIFT 0x0 4430 #define MMMC_VM_MX_L1_TLB2_STATUS__FOUND_PARITY_ERRORS__SHIFT 0x1 4431 #define MMMC_VM_MX_L1_TLB2_STATUS__FOUND_APERTURE_FAULTS__SHIFT 0x2 4432 #define MMMC_VM_MX_L1_TLB2_STATUS__BUSY_MASK 0x00000001L 4433 #define MMMC_VM_MX_L1_TLB2_STATUS__FOUND_PARITY_ERRORS_MASK 0x00000002L 4434 #define MMMC_VM_MX_L1_TLB2_STATUS__FOUND_APERTURE_FAULTS_MASK 0x00000004L 4435 //MMMC_VM_MX_L1_TLB3_STATUS 4436 #define MMMC_VM_MX_L1_TLB3_STATUS__BUSY__SHIFT 0x0 4437 #define MMMC_VM_MX_L1_TLB3_STATUS__FOUND_PARITY_ERRORS__SHIFT 0x1 4438 #define MMMC_VM_MX_L1_TLB3_STATUS__FOUND_APERTURE_FAULTS__SHIFT 0x2 4439 #define MMMC_VM_MX_L1_TLB3_STATUS__BUSY_MASK 0x00000001L 4440 #define MMMC_VM_MX_L1_TLB3_STATUS__FOUND_PARITY_ERRORS_MASK 0x00000002L 4441 #define MMMC_VM_MX_L1_TLB3_STATUS__FOUND_APERTURE_FAULTS_MASK 0x00000004L 4442 //MMMC_VM_MX_L1_TLB4_STATUS 4443 #define MMMC_VM_MX_L1_TLB4_STATUS__BUSY__SHIFT 0x0 4444 #define MMMC_VM_MX_L1_TLB4_STATUS__FOUND_PARITY_ERRORS__SHIFT 0x1 4445 #define MMMC_VM_MX_L1_TLB4_STATUS__FOUND_APERTURE_FAULTS__SHIFT 0x2 4446 #define MMMC_VM_MX_L1_TLB4_STATUS__BUSY_MASK 0x00000001L 4447 #define MMMC_VM_MX_L1_TLB4_STATUS__FOUND_PARITY_ERRORS_MASK 0x00000002L 4448 #define MMMC_VM_MX_L1_TLB4_STATUS__FOUND_APERTURE_FAULTS_MASK 0x00000004L 4449 //MMMC_VM_MX_L1_TLB5_STATUS 4450 #define MMMC_VM_MX_L1_TLB5_STATUS__BUSY__SHIFT 0x0 4451 #define MMMC_VM_MX_L1_TLB5_STATUS__FOUND_PARITY_ERRORS__SHIFT 0x1 4452 #define MMMC_VM_MX_L1_TLB5_STATUS__FOUND_APERTURE_FAULTS__SHIFT 0x2 4453 #define MMMC_VM_MX_L1_TLB5_STATUS__BUSY_MASK 0x00000001L 4454 #define MMMC_VM_MX_L1_TLB5_STATUS__FOUND_PARITY_ERRORS_MASK 0x00000002L 4455 #define MMMC_VM_MX_L1_TLB5_STATUS__FOUND_APERTURE_FAULTS_MASK 0x00000004L 4456 4457 4458 // addressBlock: mmhub_l1tlb_mmutcl1pldec 4459 //MMMC_VM_MX_L1_PERFCOUNTER0_CFG 4460 #define MMMC_VM_MX_L1_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 4461 #define MMMC_VM_MX_L1_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 4462 #define MMMC_VM_MX_L1_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 4463 #define MMMC_VM_MX_L1_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c 4464 #define MMMC_VM_MX_L1_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d 4465 #define MMMC_VM_MX_L1_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL 4466 #define MMMC_VM_MX_L1_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L 4467 #define MMMC_VM_MX_L1_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L 4468 #define MMMC_VM_MX_L1_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L 4469 #define MMMC_VM_MX_L1_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L 4470 //MMMC_VM_MX_L1_PERFCOUNTER1_CFG 4471 #define MMMC_VM_MX_L1_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 4472 #define MMMC_VM_MX_L1_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 4473 #define MMMC_VM_MX_L1_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 4474 #define MMMC_VM_MX_L1_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c 4475 #define MMMC_VM_MX_L1_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d 4476 #define MMMC_VM_MX_L1_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL 4477 #define MMMC_VM_MX_L1_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L 4478 #define MMMC_VM_MX_L1_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L 4479 #define MMMC_VM_MX_L1_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L 4480 #define MMMC_VM_MX_L1_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L 4481 //MMMC_VM_MX_L1_PERFCOUNTER2_CFG 4482 #define MMMC_VM_MX_L1_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0 4483 #define MMMC_VM_MX_L1_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8 4484 #define MMMC_VM_MX_L1_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18 4485 #define MMMC_VM_MX_L1_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c 4486 #define MMMC_VM_MX_L1_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d 4487 #define MMMC_VM_MX_L1_PERFCOUNTER2_CFG__PERF_SEL_MASK 0x000000FFL 4488 #define MMMC_VM_MX_L1_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0x0000FF00L 4489 #define MMMC_VM_MX_L1_PERFCOUNTER2_CFG__PERF_MODE_MASK 0x0F000000L 4490 #define MMMC_VM_MX_L1_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000L 4491 #define MMMC_VM_MX_L1_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000L 4492 //MMMC_VM_MX_L1_PERFCOUNTER3_CFG 4493 #define MMMC_VM_MX_L1_PERFCOUNTER3_CFG__PERF_SEL__SHIFT 0x0 4494 #define MMMC_VM_MX_L1_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT 0x8 4495 #define MMMC_VM_MX_L1_PERFCOUNTER3_CFG__PERF_MODE__SHIFT 0x18 4496 #define MMMC_VM_MX_L1_PERFCOUNTER3_CFG__ENABLE__SHIFT 0x1c 4497 #define MMMC_VM_MX_L1_PERFCOUNTER3_CFG__CLEAR__SHIFT 0x1d 4498 #define MMMC_VM_MX_L1_PERFCOUNTER3_CFG__PERF_SEL_MASK 0x000000FFL 4499 #define MMMC_VM_MX_L1_PERFCOUNTER3_CFG__PERF_SEL_END_MASK 0x0000FF00L 4500 #define MMMC_VM_MX_L1_PERFCOUNTER3_CFG__PERF_MODE_MASK 0x0F000000L 4501 #define MMMC_VM_MX_L1_PERFCOUNTER3_CFG__ENABLE_MASK 0x10000000L 4502 #define MMMC_VM_MX_L1_PERFCOUNTER3_CFG__CLEAR_MASK 0x20000000L 4503 //MMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL 4504 #define MMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 4505 #define MMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 4506 #define MMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 4507 #define MMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 4508 #define MMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 4509 #define MMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a 4510 #define MMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL 4511 #define MMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L 4512 #define MMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L 4513 #define MMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L 4514 #define MMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L 4515 #define MMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L 4516 4517 4518 // addressBlock: mmhub_l1tlb_mmutcl1prdec 4519 //MMMC_VM_MX_L1_PERFCOUNTER_LO 4520 #define MMMC_VM_MX_L1_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 4521 #define MMMC_VM_MX_L1_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL 4522 //MMMC_VM_MX_L1_PERFCOUNTER_HI 4523 #define MMMC_VM_MX_L1_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 4524 #define MMMC_VM_MX_L1_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 4525 #define MMMC_VM_MX_L1_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL 4526 #define MMMC_VM_MX_L1_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L 4527 4528 4529 // addressBlock: mmhub_mmutcl2_mmatcl2dec 4530 //MM_ATC_L2_CNTL 4531 #define MM_ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READ_REQUESTS__SHIFT 0x0 4532 #define MM_ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITE_REQUESTS__SHIFT 0x3 4533 #define MM_ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READS_DEPENDS_ON_ADDR_MOD__SHIFT 0x6 4534 #define MM_ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITES_DEPENDS_ON_ADDR_MOD__SHIFT 0x7 4535 #define MM_ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_READ_REQUESTS__SHIFT 0x8 4536 #define MM_ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_WRITE_REQUESTS__SHIFT 0xb 4537 #define MM_ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_READS_DEPENDS_ON_ADDR_MOD__SHIFT 0xe 4538 #define MM_ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_WRITES_DEPENDS_ON_ADDR_MOD__SHIFT 0xf 4539 #define MM_ATC_L2_CNTL__CACHE_INVALIDATE_MODE__SHIFT 0x10 4540 #define MM_ATC_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY__SHIFT 0x13 4541 #define MM_ATC_L2_CNTL__FRAG_APT_INTXN_MODE__SHIFT 0x14 4542 #define MM_ATC_L2_CNTL__CLI_GPA_REQ_FRAG_SIZE__SHIFT 0x16 4543 #define MM_ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READ_REQUESTS_MASK 0x00000003L 4544 #define MM_ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITE_REQUESTS_MASK 0x00000018L 4545 #define MM_ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READS_DEPENDS_ON_ADDR_MOD_MASK 0x00000040L 4546 #define MM_ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITES_DEPENDS_ON_ADDR_MOD_MASK 0x00000080L 4547 #define MM_ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_READ_REQUESTS_MASK 0x00000300L 4548 #define MM_ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_WRITE_REQUESTS_MASK 0x00001800L 4549 #define MM_ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_READS_DEPENDS_ON_ADDR_MOD_MASK 0x00004000L 4550 #define MM_ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_WRITES_DEPENDS_ON_ADDR_MOD_MASK 0x00008000L 4551 #define MM_ATC_L2_CNTL__CACHE_INVALIDATE_MODE_MASK 0x00070000L 4552 #define MM_ATC_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY_MASK 0x00080000L 4553 #define MM_ATC_L2_CNTL__FRAG_APT_INTXN_MODE_MASK 0x00300000L 4554 #define MM_ATC_L2_CNTL__CLI_GPA_REQ_FRAG_SIZE_MASK 0x0FC00000L 4555 //MM_ATC_L2_CNTL2 4556 #define MM_ATC_L2_CNTL2__BANK_SELECT__SHIFT 0x0 4557 #define MM_ATC_L2_CNTL2__NUM_BANKS_LOG2__SHIFT 0x6 4558 #define MM_ATC_L2_CNTL2__L2_CACHE_UPDATE_MODE__SHIFT 0x9 4559 #define MM_ATC_L2_CNTL2__ENABLE_L2_CACHE_LRU_UPDATE_BY_WRITE__SHIFT 0xb 4560 #define MM_ATC_L2_CNTL2__L2_CACHE_SWAP_TAG_INDEX_LSBS__SHIFT 0xc 4561 #define MM_ATC_L2_CNTL2__L2_CACHE_VMID_MODE__SHIFT 0xf 4562 #define MM_ATC_L2_CNTL2__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE__SHIFT 0x12 4563 #define MM_ATC_L2_CNTL2__BANK_SELECT_MASK 0x0000003FL 4564 #define MM_ATC_L2_CNTL2__NUM_BANKS_LOG2_MASK 0x000001C0L 4565 #define MM_ATC_L2_CNTL2__L2_CACHE_UPDATE_MODE_MASK 0x00000600L 4566 #define MM_ATC_L2_CNTL2__ENABLE_L2_CACHE_LRU_UPDATE_BY_WRITE_MASK 0x00000800L 4567 #define MM_ATC_L2_CNTL2__L2_CACHE_SWAP_TAG_INDEX_LSBS_MASK 0x00007000L 4568 #define MM_ATC_L2_CNTL2__L2_CACHE_VMID_MODE_MASK 0x00038000L 4569 #define MM_ATC_L2_CNTL2__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE_MASK 0x00FC0000L 4570 //MM_ATC_L2_CACHE_DATA0 4571 #define MM_ATC_L2_CACHE_DATA0__DATA_REGISTER_VALID__SHIFT 0x0 4572 #define MM_ATC_L2_CACHE_DATA0__CACHE_ENTRY_VALID__SHIFT 0x1 4573 #define MM_ATC_L2_CACHE_DATA0__CACHED_ATTRIBUTES__SHIFT 0x2 4574 #define MM_ATC_L2_CACHE_DATA0__VIRTUAL_PAGE_ADDRESS_HIGH__SHIFT 0x18 4575 #define MM_ATC_L2_CACHE_DATA0__DATA_REGISTER_VALID_MASK 0x00000001L 4576 #define MM_ATC_L2_CACHE_DATA0__CACHE_ENTRY_VALID_MASK 0x00000002L 4577 #define MM_ATC_L2_CACHE_DATA0__CACHED_ATTRIBUTES_MASK 0x00FFFFFCL 4578 #define MM_ATC_L2_CACHE_DATA0__VIRTUAL_PAGE_ADDRESS_HIGH_MASK 0x0F000000L 4579 //MM_ATC_L2_CACHE_DATA1 4580 #define MM_ATC_L2_CACHE_DATA1__VIRTUAL_PAGE_ADDRESS_LOW__SHIFT 0x0 4581 #define MM_ATC_L2_CACHE_DATA1__VIRTUAL_PAGE_ADDRESS_LOW_MASK 0xFFFFFFFFL 4582 //MM_ATC_L2_CACHE_DATA2 4583 #define MM_ATC_L2_CACHE_DATA2__PHYSICAL_PAGE_ADDRESS__SHIFT 0x0 4584 #define MM_ATC_L2_CACHE_DATA2__PHYSICAL_PAGE_ADDRESS_MASK 0xFFFFFFFFL 4585 //MM_ATC_L2_CNTL3 4586 #define MM_ATC_L2_CNTL3__L2_SMALLK_CACHE_FRAGMENT_SIZE__SHIFT 0x0 4587 #define MM_ATC_L2_CNTL3__L2_MIDK_CACHE_FRAGMENT_SIZE__SHIFT 0x6 4588 #define MM_ATC_L2_CNTL3__L2_BIGK_CACHE_FRAGMENT_SIZE__SHIFT 0xc 4589 #define MM_ATC_L2_CNTL3__DELAY_SEND_INVALIDATION_REQUEST__SHIFT 0x12 4590 #define MM_ATC_L2_CNTL3__ATS_REQUEST_CREDIT_MINUS1__SHIFT 0x15 4591 #define MM_ATC_L2_CNTL3__COMPCLKREQ_OFF_HYSTERESIS__SHIFT 0x1b 4592 #define MM_ATC_L2_CNTL3__REPEATER_FGCG_OFF__SHIFT 0x1e 4593 #define MM_ATC_L2_CNTL3__L2_SMALLK_CACHE_FRAGMENT_SIZE_MASK 0x0000003FL 4594 #define MM_ATC_L2_CNTL3__L2_MIDK_CACHE_FRAGMENT_SIZE_MASK 0x00000FC0L 4595 #define MM_ATC_L2_CNTL3__L2_BIGK_CACHE_FRAGMENT_SIZE_MASK 0x0003F000L 4596 #define MM_ATC_L2_CNTL3__DELAY_SEND_INVALIDATION_REQUEST_MASK 0x001C0000L 4597 #define MM_ATC_L2_CNTL3__ATS_REQUEST_CREDIT_MINUS1_MASK 0x07E00000L 4598 #define MM_ATC_L2_CNTL3__COMPCLKREQ_OFF_HYSTERESIS_MASK 0x38000000L 4599 #define MM_ATC_L2_CNTL3__REPEATER_FGCG_OFF_MASK 0x40000000L 4600 //MM_ATC_L2_CNTL4 4601 #define MM_ATC_L2_CNTL4__L2_RT_SMALLK_CACHE_FRAGMENT_SIZE__SHIFT 0x0 4602 #define MM_ATC_L2_CNTL4__L2_RT_MIDK_CACHE_FRAGMENT_SIZE__SHIFT 0x6 4603 #define MM_ATC_L2_CNTL4__L2_RT_BIGK_CACHE_FRAGMENT_SIZE__SHIFT 0xc 4604 #define MM_ATC_L2_CNTL4__L2_RT_SMALLK_CACHE_FRAGMENT_SIZE_MASK 0x0000003FL 4605 #define MM_ATC_L2_CNTL4__L2_RT_MIDK_CACHE_FRAGMENT_SIZE_MASK 0x00000FC0L 4606 #define MM_ATC_L2_CNTL4__L2_RT_BIGK_CACHE_FRAGMENT_SIZE_MASK 0x0003F000L 4607 //MM_ATC_L2_CNTL5 4608 #define MM_ATC_L2_CNTL5__MM_NONRT_IFIFO_ACTIVE_TRANSACTION_LIMIT__SHIFT 0x0 4609 #define MM_ATC_L2_CNTL5__MM_SOFTRT_IFIFO_ACTIVE_TRANSACTION_LIMIT__SHIFT 0xa 4610 #define MM_ATC_L2_CNTL5__MM_NONRT_IFIFO_ACTIVE_TRANSACTION_LIMIT_MASK 0x000003FFL 4611 #define MM_ATC_L2_CNTL5__MM_SOFTRT_IFIFO_ACTIVE_TRANSACTION_LIMIT_MASK 0x000FFC00L 4612 //MM_ATC_L2_MM_GROUP_RT_CLASSES 4613 #define MM_ATC_L2_MM_GROUP_RT_CLASSES__GROUP_RT_CLASS__SHIFT 0x0 4614 #define MM_ATC_L2_MM_GROUP_RT_CLASSES__GROUP_RT_CLASS_MASK 0xFFFFFFFFL 4615 //MM_ATC_L2_STATUS 4616 #define MM_ATC_L2_STATUS__BUSY__SHIFT 0x0 4617 #define MM_ATC_L2_STATUS__NO_OUTSTANDING_AT_REQUESTS__SHIFT 0x1 4618 #define MM_ATC_L2_STATUS__BUSY_MASK 0x00000001L 4619 #define MM_ATC_L2_STATUS__NO_OUTSTANDING_AT_REQUESTS_MASK 0x00000002L 4620 //MM_ATC_L2_STATUS2 4621 #define MM_ATC_L2_STATUS2__IFIFO_NON_FATAL_PARITY_ERROR_INFO__SHIFT 0x0 4622 #define MM_ATC_L2_STATUS2__IFIFO_FATAL_PARITY_ERROR_INFO__SHIFT 0x8 4623 #define MM_ATC_L2_STATUS2__IFIFO_NON_FATAL_PARITY_ERROR_INFO_MASK 0x000000FFL 4624 #define MM_ATC_L2_STATUS2__IFIFO_FATAL_PARITY_ERROR_INFO_MASK 0x0000FF00L 4625 //MM_ATC_L2_MISC_CG 4626 #define MM_ATC_L2_MISC_CG__OFFDLY__SHIFT 0x6 4627 #define MM_ATC_L2_MISC_CG__ENABLE__SHIFT 0x12 4628 #define MM_ATC_L2_MISC_CG__MEM_LS_ENABLE__SHIFT 0x13 4629 #define MM_ATC_L2_MISC_CG__OFFDLY_MASK 0x00000FC0L 4630 #define MM_ATC_L2_MISC_CG__ENABLE_MASK 0x00040000L 4631 #define MM_ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK 0x00080000L 4632 //MM_ATC_L2_MEM_POWER_LS 4633 #define MM_ATC_L2_MEM_POWER_LS__LS_SETUP__SHIFT 0x0 4634 #define MM_ATC_L2_MEM_POWER_LS__LS_HOLD__SHIFT 0x6 4635 #define MM_ATC_L2_MEM_POWER_LS__LS_SETUP_MASK 0x0000003FL 4636 #define MM_ATC_L2_MEM_POWER_LS__LS_HOLD_MASK 0x00000FC0L 4637 //MM_ATC_L2_CGTT_CLK_CTRL 4638 #define MM_ATC_L2_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 4639 #define MM_ATC_L2_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x5 4640 #define MM_ATC_L2_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS__SHIFT 0xd 4641 #define MM_ATC_L2_CGTT_CLK_CTRL__LS_DISABLE__SHIFT 0x1e 4642 #define MM_ATC_L2_CGTT_CLK_CTRL__BUSY_OVERRIDE__SHIFT 0x1f 4643 #define MM_ATC_L2_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000001FL 4644 #define MM_ATC_L2_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00001FE0L 4645 #define MM_ATC_L2_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS_MASK 0x1FFFE000L 4646 #define MM_ATC_L2_CGTT_CLK_CTRL__LS_DISABLE_MASK 0x40000000L 4647 #define MM_ATC_L2_CGTT_CLK_CTRL__BUSY_OVERRIDE_MASK 0x80000000L 4648 //MM_ATC_L2_SDPPORT_CTRL 4649 #define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_RDRSPCKEN__SHIFT 0x0 4650 #define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_RDRSPCKENRCV__SHIFT 0x1 4651 #define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_RDRSPDATACKEN__SHIFT 0x2 4652 #define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_RDRSPDATACKENRCV__SHIFT 0x3 4653 #define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_WRRSPCKEN__SHIFT 0x4 4654 #define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_WRRSPCKENRCV__SHIFT 0x5 4655 #define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_REQCKEN__SHIFT 0x6 4656 #define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_REQCKENRCV__SHIFT 0x7 4657 #define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_ORIGDATACKEN__SHIFT 0x8 4658 #define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_ORIGDATACKENRCV__SHIFT 0x9 4659 #define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_RDRSPCKEN_MASK 0x00000001L 4660 #define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_RDRSPCKENRCV_MASK 0x00000002L 4661 #define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_RDRSPDATACKEN_MASK 0x00000004L 4662 #define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_RDRSPDATACKENRCV_MASK 0x00000008L 4663 #define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_WRRSPCKEN_MASK 0x00000010L 4664 #define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_WRRSPCKENRCV_MASK 0x00000020L 4665 #define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_REQCKEN_MASK 0x00000040L 4666 #define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_REQCKENRCV_MASK 0x00000080L 4667 #define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_ORIGDATACKEN_MASK 0x00000100L 4668 #define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_ORIGDATACKENRCV_MASK 0x00000200L 4669 //MMUTCL2_FFBM_CONFIG 4670 #define MMUTCL2_FFBM_CONFIG__TLB_PAGE_SIZE__SHIFT 0x0 4671 #define MMUTCL2_FFBM_CONFIG__TLB_PAGE_SIZE_MASK 0x0000001FL 4672 //MMUTCL2_FFBM_ACCESS_CNTL 4673 #define MMUTCL2_FFBM_ACCESS_CNTL__TLB_ACCESS_REQUEST__SHIFT 0x0 4674 #define MMUTCL2_FFBM_ACCESS_CNTL__TLB_ACCESS_GRANT__SHIFT 0x1 4675 #define MMUTCL2_FFBM_ACCESS_CNTL__TLB_ACCESS_REQUEST_MASK 0x00000001L 4676 #define MMUTCL2_FFBM_ACCESS_CNTL__TLB_ACCESS_GRANT_MASK 0x00000002L 4677 //MMUTCL2_FFBM_ADDRESS 4678 #define MMUTCL2_FFBM_ADDRESS__VFID__SHIFT 0x0 4679 #define MMUTCL2_FFBM_ADDRESS__ADDRESS__SHIFT 0x4 4680 #define MMUTCL2_FFBM_ADDRESS__VFID_MASK 0x0000000FL 4681 #define MMUTCL2_FFBM_ADDRESS__ADDRESS_MASK 0x07FFFFF0L 4682 //MMUTCL2_FFBM_DATA 4683 #define MMUTCL2_FFBM_DATA__VALID__SHIFT 0x0 4684 #define MMUTCL2_FFBM_DATA__READ_PERMISSION__SHIFT 0x1 4685 #define MMUTCL2_FFBM_DATA__WRITE_PERMISSION__SHIFT 0x2 4686 #define MMUTCL2_FFBM_DATA__FRAGMENT__SHIFT 0x3 4687 #define MMUTCL2_FFBM_DATA__FB_SPA__SHIFT 0x8 4688 #define MMUTCL2_FFBM_DATA__VALID_MASK 0x00000001L 4689 #define MMUTCL2_FFBM_DATA__READ_PERMISSION_MASK 0x00000002L 4690 #define MMUTCL2_FFBM_DATA__WRITE_PERMISSION_MASK 0x00000004L 4691 #define MMUTCL2_FFBM_DATA__FRAGMENT_MASK 0x000000F8L 4692 #define MMUTCL2_FFBM_DATA__FB_SPA_MASK 0x7FFFFF00L 4693 //MMUTCL2_FFBM_INVALIDATE_REQUEST 4694 #define MMUTCL2_FFBM_INVALIDATE_REQUEST__REQ__SHIFT 0x0 4695 #define MMUTCL2_FFBM_INVALIDATE_REQUEST__VFID__SHIFT 0x1 4696 #define MMUTCL2_FFBM_INVALIDATE_REQUEST__FLUSHTYPE__SHIFT 0x6 4697 #define MMUTCL2_FFBM_INVALIDATE_REQUEST__SIZE__SHIFT 0x7 4698 #define MMUTCL2_FFBM_INVALIDATE_REQUEST__ADDRESS__SHIFT 0x8 4699 #define MMUTCL2_FFBM_INVALIDATE_REQUEST__REQ_MASK 0x00000001L 4700 #define MMUTCL2_FFBM_INVALIDATE_REQUEST__VFID_MASK 0x0000001EL 4701 #define MMUTCL2_FFBM_INVALIDATE_REQUEST__FLUSHTYPE_MASK 0x00000040L 4702 #define MMUTCL2_FFBM_INVALIDATE_REQUEST__SIZE_MASK 0x00000080L 4703 #define MMUTCL2_FFBM_INVALIDATE_REQUEST__ADDRESS_MASK 0x7FFFFF00L 4704 //MMUTCL2_FFBM_INVALIDATE_RESPONSE 4705 #define MMUTCL2_FFBM_INVALIDATE_RESPONSE__NON_FLUSHTYPE_INVALIDATE_ACK__SHIFT 0x0 4706 #define MMUTCL2_FFBM_INVALIDATE_RESPONSE__FLUSHTYPE_INVALIDATE_ACK__SHIFT 0x1 4707 #define MMUTCL2_FFBM_INVALIDATE_RESPONSE__NON_FLUSHTYPE_INVALIDATE_ACK_MASK 0x00000001L 4708 #define MMUTCL2_FFBM_INVALIDATE_RESPONSE__FLUSHTYPE_INVALIDATE_ACK_MASK 0x00000002L 4709 4710 4711 // addressBlock: mmhub_mmutcl2_mmvml2pfdec 4712 //MMVM_L2_CNTL 4713 #define MMVM_L2_CNTL__ENABLE_L2_CACHE__SHIFT 0x0 4714 #define MMVM_L2_CNTL__ENABLE_L2_FRAGMENT_PROCESSING__SHIFT 0x1 4715 #define MMVM_L2_CNTL__L2_CACHE_PTE_ENDIAN_SWAP_MODE__SHIFT 0x2 4716 #define MMVM_L2_CNTL__L2_CACHE_PDE_ENDIAN_SWAP_MODE__SHIFT 0x4 4717 #define MMVM_L2_CNTL__L2_PDE0_CACHE_TAG_GENERATION_MODE__SHIFT 0x8 4718 #define MMVM_L2_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE__SHIFT 0x9 4719 #define MMVM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE__SHIFT 0xa 4720 #define MMVM_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY__SHIFT 0xb 4721 #define MMVM_L2_CNTL__L2_PDE0_CACHE_SPLIT_MODE__SHIFT 0xc 4722 #define MMVM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE__SHIFT 0xf 4723 #define MMVM_L2_CNTL__PDE_FAULT_CLASSIFICATION__SHIFT 0x12 4724 #define MMVM_L2_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE__SHIFT 0x13 4725 #define MMVM_L2_CNTL__IDENTITY_MODE_FRAGMENT_SIZE__SHIFT 0x15 4726 #define MMVM_L2_CNTL__L2_PTE_CACHE_ADDR_MODE__SHIFT 0x1a 4727 #define MMVM_L2_CNTL__ENABLE_L2_CACHE_MASK 0x00000001L 4728 #define MMVM_L2_CNTL__ENABLE_L2_FRAGMENT_PROCESSING_MASK 0x00000002L 4729 #define MMVM_L2_CNTL__L2_CACHE_PTE_ENDIAN_SWAP_MODE_MASK 0x0000000CL 4730 #define MMVM_L2_CNTL__L2_CACHE_PDE_ENDIAN_SWAP_MODE_MASK 0x00000030L 4731 #define MMVM_L2_CNTL__L2_PDE0_CACHE_TAG_GENERATION_MODE_MASK 0x00000100L 4732 #define MMVM_L2_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE_MASK 0x00000200L 4733 #define MMVM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE_MASK 0x00000400L 4734 #define MMVM_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY_MASK 0x00000800L 4735 #define MMVM_L2_CNTL__L2_PDE0_CACHE_SPLIT_MODE_MASK 0x00007000L 4736 #define MMVM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE_MASK 0x00038000L 4737 #define MMVM_L2_CNTL__PDE_FAULT_CLASSIFICATION_MASK 0x00040000L 4738 #define MMVM_L2_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE_MASK 0x00180000L 4739 #define MMVM_L2_CNTL__IDENTITY_MODE_FRAGMENT_SIZE_MASK 0x03E00000L 4740 #define MMVM_L2_CNTL__L2_PTE_CACHE_ADDR_MODE_MASK 0x0C000000L 4741 //MMVM_L2_CNTL2 4742 #define MMVM_L2_CNTL2__INVALIDATE_ALL_L1_TLBS__SHIFT 0x0 4743 #define MMVM_L2_CNTL2__INVALIDATE_L2_CACHE__SHIFT 0x1 4744 #define MMVM_L2_CNTL2__DISABLE_INVALIDATE_PER_DOMAIN__SHIFT 0x15 4745 #define MMVM_L2_CNTL2__DISABLE_BIGK_CACHE_OPTIMIZATION__SHIFT 0x16 4746 #define MMVM_L2_CNTL2__L2_PTE_CACHE_VMID_MODE__SHIFT 0x17 4747 #define MMVM_L2_CNTL2__INVALIDATE_CACHE_MODE__SHIFT 0x1a 4748 #define MMVM_L2_CNTL2__PDE_CACHE_EFFECTIVE_SIZE__SHIFT 0x1c 4749 #define MMVM_L2_CNTL2__INVALIDATE_ALL_L1_TLBS_MASK 0x00000001L 4750 #define MMVM_L2_CNTL2__INVALIDATE_L2_CACHE_MASK 0x00000002L 4751 #define MMVM_L2_CNTL2__DISABLE_INVALIDATE_PER_DOMAIN_MASK 0x00200000L 4752 #define MMVM_L2_CNTL2__DISABLE_BIGK_CACHE_OPTIMIZATION_MASK 0x00400000L 4753 #define MMVM_L2_CNTL2__L2_PTE_CACHE_VMID_MODE_MASK 0x03800000L 4754 #define MMVM_L2_CNTL2__INVALIDATE_CACHE_MODE_MASK 0x0C000000L 4755 #define MMVM_L2_CNTL2__PDE_CACHE_EFFECTIVE_SIZE_MASK 0x70000000L 4756 //MMVM_L2_CNTL3 4757 #define MMVM_L2_CNTL3__BANK_SELECT__SHIFT 0x0 4758 #define MMVM_L2_CNTL3__L2_CACHE_UPDATE_MODE__SHIFT 0x6 4759 #define MMVM_L2_CNTL3__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE__SHIFT 0x8 4760 #define MMVM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0xf 4761 #define MMVM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY__SHIFT 0x14 4762 #define MMVM_L2_CNTL3__L2_CACHE_4K_EFFECTIVE_SIZE__SHIFT 0x15 4763 #define MMVM_L2_CNTL3__L2_CACHE_BIGK_EFFECTIVE_SIZE__SHIFT 0x18 4764 #define MMVM_L2_CNTL3__L2_CACHE_4K_FORCE_MISS__SHIFT 0x1c 4765 #define MMVM_L2_CNTL3__L2_CACHE_BIGK_FORCE_MISS__SHIFT 0x1d 4766 #define MMVM_L2_CNTL3__PDE_CACHE_FORCE_MISS__SHIFT 0x1e 4767 #define MMVM_L2_CNTL3__L2_CACHE_4K_ASSOCIATIVITY__SHIFT 0x1f 4768 #define MMVM_L2_CNTL3__BANK_SELECT_MASK 0x0000003FL 4769 #define MMVM_L2_CNTL3__L2_CACHE_UPDATE_MODE_MASK 0x000000C0L 4770 #define MMVM_L2_CNTL3__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE_MASK 0x00001F00L 4771 #define MMVM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000F8000L 4772 #define MMVM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY_MASK 0x00100000L 4773 #define MMVM_L2_CNTL3__L2_CACHE_4K_EFFECTIVE_SIZE_MASK 0x00E00000L 4774 #define MMVM_L2_CNTL3__L2_CACHE_BIGK_EFFECTIVE_SIZE_MASK 0x0F000000L 4775 #define MMVM_L2_CNTL3__L2_CACHE_4K_FORCE_MISS_MASK 0x10000000L 4776 #define MMVM_L2_CNTL3__L2_CACHE_BIGK_FORCE_MISS_MASK 0x20000000L 4777 #define MMVM_L2_CNTL3__PDE_CACHE_FORCE_MISS_MASK 0x40000000L 4778 #define MMVM_L2_CNTL3__L2_CACHE_4K_ASSOCIATIVITY_MASK 0x80000000L 4779 //MMVM_L2_STATUS 4780 #define MMVM_L2_STATUS__L2_BUSY__SHIFT 0x0 4781 #define MMVM_L2_STATUS__CONTEXT_DOMAIN_BUSY__SHIFT 0x1 4782 #define MMVM_L2_STATUS__FOUND_4K_PTE_CACHE_PARITY_ERRORS__SHIFT 0x11 4783 #define MMVM_L2_STATUS__FOUND_BIGK_PTE_CACHE_PARITY_ERRORS__SHIFT 0x12 4784 #define MMVM_L2_STATUS__FOUND_PDE0_CACHE_PARITY_ERRORS__SHIFT 0x13 4785 #define MMVM_L2_STATUS__FOUND_PDE1_CACHE_PARITY_ERRORS__SHIFT 0x14 4786 #define MMVM_L2_STATUS__FOUND_PDE2_CACHE_PARITY_ERRORS__SHIFT 0x15 4787 #define MMVM_L2_STATUS__L2_BUSY_MASK 0x00000001L 4788 #define MMVM_L2_STATUS__CONTEXT_DOMAIN_BUSY_MASK 0x0001FFFEL 4789 #define MMVM_L2_STATUS__FOUND_4K_PTE_CACHE_PARITY_ERRORS_MASK 0x00020000L 4790 #define MMVM_L2_STATUS__FOUND_BIGK_PTE_CACHE_PARITY_ERRORS_MASK 0x00040000L 4791 #define MMVM_L2_STATUS__FOUND_PDE0_CACHE_PARITY_ERRORS_MASK 0x00080000L 4792 #define MMVM_L2_STATUS__FOUND_PDE1_CACHE_PARITY_ERRORS_MASK 0x00100000L 4793 #define MMVM_L2_STATUS__FOUND_PDE2_CACHE_PARITY_ERRORS_MASK 0x00200000L 4794 //MMVM_DUMMY_PAGE_FAULT_CNTL 4795 #define MMVM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_FAULT_ENABLE__SHIFT 0x0 4796 #define MMVM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_ADDRESS_LOGICAL__SHIFT 0x1 4797 #define MMVM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_COMPARE_MSBS__SHIFT 0x2 4798 #define MMVM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_FAULT_ENABLE_MASK 0x00000001L 4799 #define MMVM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_ADDRESS_LOGICAL_MASK 0x00000002L 4800 #define MMVM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_COMPARE_MSBS_MASK 0x000000FCL 4801 //MMVM_DUMMY_PAGE_FAULT_ADDR_LO32 4802 #define MMVM_DUMMY_PAGE_FAULT_ADDR_LO32__DUMMY_PAGE_ADDR_LO32__SHIFT 0x0 4803 #define MMVM_DUMMY_PAGE_FAULT_ADDR_LO32__DUMMY_PAGE_ADDR_LO32_MASK 0xFFFFFFFFL 4804 //MMVM_DUMMY_PAGE_FAULT_ADDR_HI32 4805 #define MMVM_DUMMY_PAGE_FAULT_ADDR_HI32__DUMMY_PAGE_ADDR_HI4__SHIFT 0x0 4806 #define MMVM_DUMMY_PAGE_FAULT_ADDR_HI32__DUMMY_PAGE_ADDR_HI4_MASK 0x0000000FL 4807 //MMVM_INVALIDATE_CNTL 4808 #define MMVM_INVALIDATE_CNTL__PRI_REG_ALTERNATING__SHIFT 0x0 4809 #define MMVM_INVALIDATE_CNTL__MAX_REG_OUTSTANDING__SHIFT 0x8 4810 #define MMVM_INVALIDATE_CNTL__PRI_REG_ALTERNATING_MASK 0x000000FFL 4811 #define MMVM_INVALIDATE_CNTL__MAX_REG_OUTSTANDING_MASK 0x0000FF00L 4812 //MMVM_L2_PROTECTION_FAULT_CNTL 4813 #define MMVM_L2_PROTECTION_FAULT_CNTL__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x0 4814 #define MMVM_L2_PROTECTION_FAULT_CNTL__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES__SHIFT 0x1 4815 #define MMVM_L2_PROTECTION_FAULT_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x2 4816 #define MMVM_L2_PROTECTION_FAULT_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x3 4817 #define MMVM_L2_PROTECTION_FAULT_CNTL__PDE1_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x4 4818 #define MMVM_L2_PROTECTION_FAULT_CNTL__PDE2_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x5 4819 #define MMVM_L2_PROTECTION_FAULT_CNTL__TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x6 4820 #define MMVM_L2_PROTECTION_FAULT_CNTL__NACK_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x7 4821 #define MMVM_L2_PROTECTION_FAULT_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x8 4822 #define MMVM_L2_PROTECTION_FAULT_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x9 4823 #define MMVM_L2_PROTECTION_FAULT_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa 4824 #define MMVM_L2_PROTECTION_FAULT_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xb 4825 #define MMVM_L2_PROTECTION_FAULT_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc 4826 #define MMVM_L2_PROTECTION_FAULT_CNTL__CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT 0xd 4827 #define MMVM_L2_PROTECTION_FAULT_CNTL__OTHER_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT 0x1d 4828 #define MMVM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_NO_RETRY_FAULT__SHIFT 0x1e 4829 #define MMVM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_RETRY_FAULT__SHIFT 0x1f 4830 #define MMVM_L2_PROTECTION_FAULT_CNTL__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00000001L 4831 #define MMVM_L2_PROTECTION_FAULT_CNTL__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES_MASK 0x00000002L 4832 #define MMVM_L2_PROTECTION_FAULT_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000004L 4833 #define MMVM_L2_PROTECTION_FAULT_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000008L 4834 #define MMVM_L2_PROTECTION_FAULT_CNTL__PDE1_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000010L 4835 #define MMVM_L2_PROTECTION_FAULT_CNTL__PDE2_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000020L 4836 #define MMVM_L2_PROTECTION_FAULT_CNTL__TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000040L 4837 #define MMVM_L2_PROTECTION_FAULT_CNTL__NACK_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000080L 4838 #define MMVM_L2_PROTECTION_FAULT_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000100L 4839 #define MMVM_L2_PROTECTION_FAULT_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000200L 4840 #define MMVM_L2_PROTECTION_FAULT_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L 4841 #define MMVM_L2_PROTECTION_FAULT_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000800L 4842 #define MMVM_L2_PROTECTION_FAULT_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L 4843 #define MMVM_L2_PROTECTION_FAULT_CNTL__CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK 0x1FFFE000L 4844 #define MMVM_L2_PROTECTION_FAULT_CNTL__OTHER_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK 0x20000000L 4845 #define MMVM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_NO_RETRY_FAULT_MASK 0x40000000L 4846 #define MMVM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_RETRY_FAULT_MASK 0x80000000L 4847 //MMVM_L2_PROTECTION_FAULT_CNTL2 4848 #define MMVM_L2_PROTECTION_FAULT_CNTL2__CLIENT_ID_PRT_FAULT_INTERRUPT__SHIFT 0x0 4849 #define MMVM_L2_PROTECTION_FAULT_CNTL2__OTHER_CLIENT_ID_PRT_FAULT_INTERRUPT__SHIFT 0x10 4850 #define MMVM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE__SHIFT 0x11 4851 #define MMVM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY__SHIFT 0x12 4852 #define MMVM_L2_PROTECTION_FAULT_CNTL2__ENABLE_RETRY_FAULT_INTERRUPT__SHIFT 0x13 4853 #define MMVM_L2_PROTECTION_FAULT_CNTL2__CLIENT_ID_PRT_FAULT_INTERRUPT_MASK 0x0000FFFFL 4854 #define MMVM_L2_PROTECTION_FAULT_CNTL2__OTHER_CLIENT_ID_PRT_FAULT_INTERRUPT_MASK 0x00010000L 4855 #define MMVM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE_MASK 0x00020000L 4856 #define MMVM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY_MASK 0x00040000L 4857 #define MMVM_L2_PROTECTION_FAULT_CNTL2__ENABLE_RETRY_FAULT_INTERRUPT_MASK 0x00080000L 4858 //MMVM_L2_PROTECTION_FAULT_MM_CNTL3 4859 #define MMVM_L2_PROTECTION_FAULT_MM_CNTL3__VML1_READ_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT 0x0 4860 #define MMVM_L2_PROTECTION_FAULT_MM_CNTL3__VML1_READ_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK 0xFFFFFFFFL 4861 //MMVM_L2_PROTECTION_FAULT_MM_CNTL4 4862 #define MMVM_L2_PROTECTION_FAULT_MM_CNTL4__VML1_WRITE_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT 0x0 4863 #define MMVM_L2_PROTECTION_FAULT_MM_CNTL4__VML1_WRITE_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK 0xFFFFFFFFL 4864 //MMVM_L2_PROTECTION_FAULT_STATUS 4865 #define MMVM_L2_PROTECTION_FAULT_STATUS__MORE_FAULTS__SHIFT 0x0 4866 #define MMVM_L2_PROTECTION_FAULT_STATUS__WALKER_ERROR__SHIFT 0x1 4867 #define MMVM_L2_PROTECTION_FAULT_STATUS__PERMISSION_FAULTS__SHIFT 0x4 4868 #define MMVM_L2_PROTECTION_FAULT_STATUS__MAPPING_ERROR__SHIFT 0x8 4869 #define MMVM_L2_PROTECTION_FAULT_STATUS__CID__SHIFT 0x9 4870 #define MMVM_L2_PROTECTION_FAULT_STATUS__RW__SHIFT 0x12 4871 #define MMVM_L2_PROTECTION_FAULT_STATUS__ATOMIC__SHIFT 0x13 4872 #define MMVM_L2_PROTECTION_FAULT_STATUS__VMID__SHIFT 0x14 4873 #define MMVM_L2_PROTECTION_FAULT_STATUS__VF__SHIFT 0x18 4874 #define MMVM_L2_PROTECTION_FAULT_STATUS__VFID__SHIFT 0x19 4875 #define MMVM_L2_PROTECTION_FAULT_STATUS__PRT__SHIFT 0x1d 4876 #define MMVM_L2_PROTECTION_FAULT_STATUS__MORE_FAULTS_MASK 0x00000001L 4877 #define MMVM_L2_PROTECTION_FAULT_STATUS__WALKER_ERROR_MASK 0x0000000EL 4878 #define MMVM_L2_PROTECTION_FAULT_STATUS__PERMISSION_FAULTS_MASK 0x000000F0L 4879 #define MMVM_L2_PROTECTION_FAULT_STATUS__MAPPING_ERROR_MASK 0x00000100L 4880 #define MMVM_L2_PROTECTION_FAULT_STATUS__CID_MASK 0x0003FE00L 4881 #define MMVM_L2_PROTECTION_FAULT_STATUS__RW_MASK 0x00040000L 4882 #define MMVM_L2_PROTECTION_FAULT_STATUS__ATOMIC_MASK 0x00080000L 4883 #define MMVM_L2_PROTECTION_FAULT_STATUS__VMID_MASK 0x00F00000L 4884 #define MMVM_L2_PROTECTION_FAULT_STATUS__VF_MASK 0x01000000L 4885 #define MMVM_L2_PROTECTION_FAULT_STATUS__VFID_MASK 0x1E000000L 4886 #define MMVM_L2_PROTECTION_FAULT_STATUS__PRT_MASK 0x20000000L 4887 //MMVM_L2_PROTECTION_FAULT_ADDR_LO32 4888 #define MMVM_L2_PROTECTION_FAULT_ADDR_LO32__LOGICAL_PAGE_ADDR_LO32__SHIFT 0x0 4889 #define MMVM_L2_PROTECTION_FAULT_ADDR_LO32__LOGICAL_PAGE_ADDR_LO32_MASK 0xFFFFFFFFL 4890 //MMVM_L2_PROTECTION_FAULT_ADDR_HI32 4891 #define MMVM_L2_PROTECTION_FAULT_ADDR_HI32__LOGICAL_PAGE_ADDR_HI4__SHIFT 0x0 4892 #define MMVM_L2_PROTECTION_FAULT_ADDR_HI32__LOGICAL_PAGE_ADDR_HI4_MASK 0x0000000FL 4893 //MMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32 4894 #define MMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32__PHYSICAL_PAGE_ADDR_LO32__SHIFT 0x0 4895 #define MMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32__PHYSICAL_PAGE_ADDR_LO32_MASK 0xFFFFFFFFL 4896 //MMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32 4897 #define MMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32__PHYSICAL_PAGE_ADDR_HI4__SHIFT 0x0 4898 #define MMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32__PHYSICAL_PAGE_ADDR_HI4_MASK 0x0000000FL 4899 //MMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32 4900 #define MMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 4901 #define MMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 4902 //MMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32 4903 #define MMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 4904 #define MMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 4905 //MMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32 4906 #define MMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 4907 #define MMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 4908 //MMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32 4909 #define MMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 4910 #define MMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 4911 //MMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32 4912 #define MMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32__PHYSICAL_PAGE_OFFSET_LO32__SHIFT 0x0 4913 #define MMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32__PHYSICAL_PAGE_OFFSET_LO32_MASK 0xFFFFFFFFL 4914 //MMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32 4915 #define MMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32__PHYSICAL_PAGE_OFFSET_HI4__SHIFT 0x0 4916 #define MMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32__PHYSICAL_PAGE_OFFSET_HI4_MASK 0x0000000FL 4917 //MMVM_L2_CNTL4 4918 #define MMVM_L2_CNTL4__L2_CACHE_4K_PARTITION_COUNT__SHIFT 0x0 4919 #define MMVM_L2_CNTL4__VMC_TAP_PDE_REQUEST_PHYSICAL__SHIFT 0x6 4920 #define MMVM_L2_CNTL4__VMC_TAP_PTE_REQUEST_PHYSICAL__SHIFT 0x7 4921 #define MMVM_L2_CNTL4__MM_NONRT_IFIFO_ACTIVE_TRANSACTION_LIMIT__SHIFT 0x8 4922 #define MMVM_L2_CNTL4__MM_SOFTRT_IFIFO_ACTIVE_TRANSACTION_LIMIT__SHIFT 0x12 4923 #define MMVM_L2_CNTL4__BPM_CGCGLS_OVERRIDE__SHIFT 0x1c 4924 #define MMVM_L2_CNTL4__GC_CH_FGCG_OFF__SHIFT 0x1d 4925 #define MMVM_L2_CNTL4__VFIFO_HEAD_OF_QUEUE__SHIFT 0x1e 4926 #define MMVM_L2_CNTL4__VFIFO_VISIBLE_BANK_SILOS__SHIFT 0x1f 4927 #define MMVM_L2_CNTL4__L2_CACHE_4K_PARTITION_COUNT_MASK 0x0000003FL 4928 #define MMVM_L2_CNTL4__VMC_TAP_PDE_REQUEST_PHYSICAL_MASK 0x00000040L 4929 #define MMVM_L2_CNTL4__VMC_TAP_PTE_REQUEST_PHYSICAL_MASK 0x00000080L 4930 #define MMVM_L2_CNTL4__MM_NONRT_IFIFO_ACTIVE_TRANSACTION_LIMIT_MASK 0x0003FF00L 4931 #define MMVM_L2_CNTL4__MM_SOFTRT_IFIFO_ACTIVE_TRANSACTION_LIMIT_MASK 0x0FFC0000L 4932 #define MMVM_L2_CNTL4__BPM_CGCGLS_OVERRIDE_MASK 0x10000000L 4933 #define MMVM_L2_CNTL4__GC_CH_FGCG_OFF_MASK 0x20000000L 4934 #define MMVM_L2_CNTL4__VFIFO_HEAD_OF_QUEUE_MASK 0x40000000L 4935 #define MMVM_L2_CNTL4__VFIFO_VISIBLE_BANK_SILOS_MASK 0x80000000L 4936 //MMVM_L2_MM_GROUP_RT_CLASSES 4937 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_0_RT_CLASS__SHIFT 0x0 4938 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_1_RT_CLASS__SHIFT 0x1 4939 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_2_RT_CLASS__SHIFT 0x2 4940 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_3_RT_CLASS__SHIFT 0x3 4941 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_4_RT_CLASS__SHIFT 0x4 4942 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_5_RT_CLASS__SHIFT 0x5 4943 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_6_RT_CLASS__SHIFT 0x6 4944 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_7_RT_CLASS__SHIFT 0x7 4945 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_8_RT_CLASS__SHIFT 0x8 4946 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_9_RT_CLASS__SHIFT 0x9 4947 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_10_RT_CLASS__SHIFT 0xa 4948 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_11_RT_CLASS__SHIFT 0xb 4949 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_12_RT_CLASS__SHIFT 0xc 4950 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_13_RT_CLASS__SHIFT 0xd 4951 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_14_RT_CLASS__SHIFT 0xe 4952 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_15_RT_CLASS__SHIFT 0xf 4953 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_16_RT_CLASS__SHIFT 0x10 4954 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_17_RT_CLASS__SHIFT 0x11 4955 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_18_RT_CLASS__SHIFT 0x12 4956 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_19_RT_CLASS__SHIFT 0x13 4957 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_20_RT_CLASS__SHIFT 0x14 4958 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_21_RT_CLASS__SHIFT 0x15 4959 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_22_RT_CLASS__SHIFT 0x16 4960 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_23_RT_CLASS__SHIFT 0x17 4961 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_24_RT_CLASS__SHIFT 0x18 4962 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_25_RT_CLASS__SHIFT 0x19 4963 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_26_RT_CLASS__SHIFT 0x1a 4964 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_27_RT_CLASS__SHIFT 0x1b 4965 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_28_RT_CLASS__SHIFT 0x1c 4966 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_29_RT_CLASS__SHIFT 0x1d 4967 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_30_RT_CLASS__SHIFT 0x1e 4968 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_31_RT_CLASS__SHIFT 0x1f 4969 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_0_RT_CLASS_MASK 0x00000001L 4970 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_1_RT_CLASS_MASK 0x00000002L 4971 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_2_RT_CLASS_MASK 0x00000004L 4972 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_3_RT_CLASS_MASK 0x00000008L 4973 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_4_RT_CLASS_MASK 0x00000010L 4974 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_5_RT_CLASS_MASK 0x00000020L 4975 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_6_RT_CLASS_MASK 0x00000040L 4976 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_7_RT_CLASS_MASK 0x00000080L 4977 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_8_RT_CLASS_MASK 0x00000100L 4978 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_9_RT_CLASS_MASK 0x00000200L 4979 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_10_RT_CLASS_MASK 0x00000400L 4980 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_11_RT_CLASS_MASK 0x00000800L 4981 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_12_RT_CLASS_MASK 0x00001000L 4982 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_13_RT_CLASS_MASK 0x00002000L 4983 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_14_RT_CLASS_MASK 0x00004000L 4984 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_15_RT_CLASS_MASK 0x00008000L 4985 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_16_RT_CLASS_MASK 0x00010000L 4986 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_17_RT_CLASS_MASK 0x00020000L 4987 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_18_RT_CLASS_MASK 0x00040000L 4988 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_19_RT_CLASS_MASK 0x00080000L 4989 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_20_RT_CLASS_MASK 0x00100000L 4990 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_21_RT_CLASS_MASK 0x00200000L 4991 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_22_RT_CLASS_MASK 0x00400000L 4992 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_23_RT_CLASS_MASK 0x00800000L 4993 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_24_RT_CLASS_MASK 0x01000000L 4994 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_25_RT_CLASS_MASK 0x02000000L 4995 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_26_RT_CLASS_MASK 0x04000000L 4996 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_27_RT_CLASS_MASK 0x08000000L 4997 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_28_RT_CLASS_MASK 0x10000000L 4998 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_29_RT_CLASS_MASK 0x20000000L 4999 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_30_RT_CLASS_MASK 0x40000000L 5000 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_31_RT_CLASS_MASK 0x80000000L 5001 //MMVM_L2_BANK_SELECT_RESERVED_CID 5002 #define MMVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_READ_CLIENT_ID__SHIFT 0x0 5003 #define MMVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_WRITE_CLIENT_ID__SHIFT 0xa 5004 #define MMVM_L2_BANK_SELECT_RESERVED_CID__ENABLE__SHIFT 0x14 5005 #define MMVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_INVALIDATION_MODE__SHIFT 0x18 5006 #define MMVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_PRIVATE_INVALIDATION__SHIFT 0x19 5007 #define MMVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_FRAGMENT_SIZE__SHIFT 0x1a 5008 #define MMVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_READ_CLIENT_ID_MASK 0x000001FFL 5009 #define MMVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_WRITE_CLIENT_ID_MASK 0x0007FC00L 5010 #define MMVM_L2_BANK_SELECT_RESERVED_CID__ENABLE_MASK 0x00100000L 5011 #define MMVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_INVALIDATION_MODE_MASK 0x01000000L 5012 #define MMVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_PRIVATE_INVALIDATION_MASK 0x02000000L 5013 #define MMVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_FRAGMENT_SIZE_MASK 0x7C000000L 5014 //MMVM_L2_BANK_SELECT_RESERVED_CID2 5015 #define MMVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_READ_CLIENT_ID__SHIFT 0x0 5016 #define MMVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_WRITE_CLIENT_ID__SHIFT 0xa 5017 #define MMVM_L2_BANK_SELECT_RESERVED_CID2__ENABLE__SHIFT 0x14 5018 #define MMVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_INVALIDATION_MODE__SHIFT 0x18 5019 #define MMVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_PRIVATE_INVALIDATION__SHIFT 0x19 5020 #define MMVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_FRAGMENT_SIZE__SHIFT 0x1a 5021 #define MMVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_READ_CLIENT_ID_MASK 0x000001FFL 5022 #define MMVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_WRITE_CLIENT_ID_MASK 0x0007FC00L 5023 #define MMVM_L2_BANK_SELECT_RESERVED_CID2__ENABLE_MASK 0x00100000L 5024 #define MMVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_INVALIDATION_MODE_MASK 0x01000000L 5025 #define MMVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_PRIVATE_INVALIDATION_MASK 0x02000000L 5026 #define MMVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_FRAGMENT_SIZE_MASK 0x7C000000L 5027 //MMVM_L2_CACHE_PARITY_CNTL 5028 #define MMVM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_4K_PTE_CACHES__SHIFT 0x0 5029 #define MMVM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_BIGK_PTE_CACHES__SHIFT 0x1 5030 #define MMVM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_PDE_CACHES__SHIFT 0x2 5031 #define MMVM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_4K_PTE_CACHE__SHIFT 0x3 5032 #define MMVM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_BIGK_PTE_CACHE__SHIFT 0x4 5033 #define MMVM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_PDE_CACHE__SHIFT 0x5 5034 #define MMVM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_BANK__SHIFT 0x6 5035 #define MMVM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_NUMBER__SHIFT 0x9 5036 #define MMVM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_ASSOC__SHIFT 0xc 5037 #define MMVM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_4K_PTE_CACHES_MASK 0x00000001L 5038 #define MMVM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_BIGK_PTE_CACHES_MASK 0x00000002L 5039 #define MMVM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_PDE_CACHES_MASK 0x00000004L 5040 #define MMVM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_4K_PTE_CACHE_MASK 0x00000008L 5041 #define MMVM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_BIGK_PTE_CACHE_MASK 0x00000010L 5042 #define MMVM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_PDE_CACHE_MASK 0x00000020L 5043 #define MMVM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_BANK_MASK 0x000001C0L 5044 #define MMVM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_NUMBER_MASK 0x00000E00L 5045 #define MMVM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_ASSOC_MASK 0x0000F000L 5046 //MMVM_L2_CGTT_CLK_CTRL 5047 #define MMVM_L2_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 5048 #define MMVM_L2_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x5 5049 #define MMVM_L2_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS__SHIFT 0xd 5050 #define MMVM_L2_CGTT_CLK_CTRL__LS_DISABLE__SHIFT 0x1e 5051 #define MMVM_L2_CGTT_CLK_CTRL__BUSY_OVERRIDE__SHIFT 0x1f 5052 #define MMVM_L2_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000001FL 5053 #define MMVM_L2_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00001FE0L 5054 #define MMVM_L2_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS_MASK 0x1FFFE000L 5055 #define MMVM_L2_CGTT_CLK_CTRL__LS_DISABLE_MASK 0x40000000L 5056 #define MMVM_L2_CGTT_CLK_CTRL__BUSY_OVERRIDE_MASK 0x80000000L 5057 //MMVM_L2_CNTL5 5058 #define MMVM_L2_CNTL5__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0 5059 #define MMVM_L2_CNTL5__WALKER_PRIORITY_CLIENT_ID__SHIFT 0x5 5060 #define MMVM_L2_CNTL5__WALKER_FETCH_PDE_NOALLOC_ENABLE__SHIFT 0xe 5061 #define MMVM_L2_CNTL5__WALKER_FETCH_PDE_MTYPE_ENABLE__SHIFT 0xf 5062 #define MMVM_L2_CNTL5__MM_CLIENT_RET_FGCG_OFF__SHIFT 0x10 5063 #define MMVM_L2_CNTL5__UTCL2_ATC_REQ_FGCG_OFF__SHIFT 0x11 5064 #define MMVM_L2_CNTL5__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL 5065 #define MMVM_L2_CNTL5__WALKER_PRIORITY_CLIENT_ID_MASK 0x00003FE0L 5066 #define MMVM_L2_CNTL5__WALKER_FETCH_PDE_NOALLOC_ENABLE_MASK 0x00004000L 5067 #define MMVM_L2_CNTL5__WALKER_FETCH_PDE_MTYPE_ENABLE_MASK 0x00008000L 5068 #define MMVM_L2_CNTL5__MM_CLIENT_RET_FGCG_OFF_MASK 0x00010000L 5069 #define MMVM_L2_CNTL5__UTCL2_ATC_REQ_FGCG_OFF_MASK 0x00020000L 5070 //MMVM_L2_GCR_CNTL 5071 #define MMVM_L2_GCR_CNTL__GCR_ENABLE__SHIFT 0x0 5072 #define MMVM_L2_GCR_CNTL__GCR_CLIENT_ID__SHIFT 0x1 5073 #define MMVM_L2_GCR_CNTL__GCR_ENABLE_MASK 0x00000001L 5074 #define MMVM_L2_GCR_CNTL__GCR_CLIENT_ID_MASK 0x000003FEL 5075 //MMVM_L2_CGTT_BUSY_CTRL 5076 #define MMVM_L2_CGTT_BUSY_CTRL__READ_DELAY__SHIFT 0x0 5077 #define MMVM_L2_CGTT_BUSY_CTRL__ALWAYS_BUSY__SHIFT 0x5 5078 #define MMVM_L2_CGTT_BUSY_CTRL__READ_DELAY_MASK 0x0000001FL 5079 #define MMVM_L2_CGTT_BUSY_CTRL__ALWAYS_BUSY_MASK 0x00000020L 5080 //MMVM_L2_PTE_CACHE_DUMP_CNTL 5081 #define MMVM_L2_PTE_CACHE_DUMP_CNTL__ENABLE__SHIFT 0x0 5082 #define MMVM_L2_PTE_CACHE_DUMP_CNTL__READY__SHIFT 0x1 5083 #define MMVM_L2_PTE_CACHE_DUMP_CNTL__BANK__SHIFT 0x4 5084 #define MMVM_L2_PTE_CACHE_DUMP_CNTL__CACHE__SHIFT 0x8 5085 #define MMVM_L2_PTE_CACHE_DUMP_CNTL__ASSOC__SHIFT 0xc 5086 #define MMVM_L2_PTE_CACHE_DUMP_CNTL__INDEX__SHIFT 0x10 5087 #define MMVM_L2_PTE_CACHE_DUMP_CNTL__ENABLE_MASK 0x00000001L 5088 #define MMVM_L2_PTE_CACHE_DUMP_CNTL__READY_MASK 0x00000002L 5089 #define MMVM_L2_PTE_CACHE_DUMP_CNTL__BANK_MASK 0x000000F0L 5090 #define MMVM_L2_PTE_CACHE_DUMP_CNTL__CACHE_MASK 0x00000F00L 5091 #define MMVM_L2_PTE_CACHE_DUMP_CNTL__ASSOC_MASK 0x0000F000L 5092 #define MMVM_L2_PTE_CACHE_DUMP_CNTL__INDEX_MASK 0xFFFF0000L 5093 //MMVM_L2_PTE_CACHE_DUMP_READ 5094 #define MMVM_L2_PTE_CACHE_DUMP_READ__DATA__SHIFT 0x0 5095 #define MMVM_L2_PTE_CACHE_DUMP_READ__DATA_MASK 0xFFFFFFFFL 5096 //MMVM_L2_BANK_SELECT_MASKS 5097 #define MMVM_L2_BANK_SELECT_MASKS__MASK0__SHIFT 0x0 5098 #define MMVM_L2_BANK_SELECT_MASKS__MASK1__SHIFT 0x4 5099 #define MMVM_L2_BANK_SELECT_MASKS__MASK2__SHIFT 0x8 5100 #define MMVM_L2_BANK_SELECT_MASKS__MASK3__SHIFT 0xc 5101 #define MMVM_L2_BANK_SELECT_MASKS__MASK0_MASK 0x0000000FL 5102 #define MMVM_L2_BANK_SELECT_MASKS__MASK1_MASK 0x000000F0L 5103 #define MMVM_L2_BANK_SELECT_MASKS__MASK2_MASK 0x00000F00L 5104 #define MMVM_L2_BANK_SELECT_MASKS__MASK3_MASK 0x0000F000L 5105 //MMUTCL2_CREDIT_SAFETY_GROUP_RET_CDC 5106 #define MMUTCL2_CREDIT_SAFETY_GROUP_RET_CDC__CREDITS__SHIFT 0x0 5107 #define MMUTCL2_CREDIT_SAFETY_GROUP_RET_CDC__UPDATE__SHIFT 0xa 5108 #define MMUTCL2_CREDIT_SAFETY_GROUP_RET_CDC__CREDITS_MASK 0x000003FFL 5109 #define MMUTCL2_CREDIT_SAFETY_GROUP_RET_CDC__UPDATE_MASK 0x00000400L 5110 //MMUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_CDC 5111 #define MMUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_CDC__CREDITS__SHIFT 0x0 5112 #define MMUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_CDC__UPDATE__SHIFT 0xa 5113 #define MMUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_CDC__CREDITS_MASK 0x000003FFL 5114 #define MMUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_CDC__UPDATE_MASK 0x00000400L 5115 //MMUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_NOCDC 5116 #define MMUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_NOCDC__CREDITS__SHIFT 0x0 5117 #define MMUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_NOCDC__UPDATE__SHIFT 0xa 5118 #define MMUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_NOCDC__CREDITS_MASK 0x000003FFL 5119 #define MMUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_NOCDC__UPDATE_MASK 0x00000400L 5120 //MMVML2_CREDIT_SAFETY_IH_FAULT_INTERRUPT 5121 #define MMVML2_CREDIT_SAFETY_IH_FAULT_INTERRUPT__CREDITS__SHIFT 0x0 5122 #define MMVML2_CREDIT_SAFETY_IH_FAULT_INTERRUPT__UPDATE__SHIFT 0xa 5123 #define MMVML2_CREDIT_SAFETY_IH_FAULT_INTERRUPT__CREDITS_MASK 0x000003FFL 5124 #define MMVML2_CREDIT_SAFETY_IH_FAULT_INTERRUPT__UPDATE_MASK 0x00000400L 5125 //MMVML2_WALKER_CREDIT_SAFETY_FETCH_RDREQ 5126 #define MMVML2_WALKER_CREDIT_SAFETY_FETCH_RDREQ__CREDITS__SHIFT 0x0 5127 #define MMVML2_WALKER_CREDIT_SAFETY_FETCH_RDREQ__UPDATE__SHIFT 0xa 5128 #define MMVML2_WALKER_CREDIT_SAFETY_FETCH_RDREQ__CREDITS_MASK 0x000003FFL 5129 #define MMVML2_WALKER_CREDIT_SAFETY_FETCH_RDREQ__UPDATE_MASK 0x00000400L 5130 5131 5132 // addressBlock: mmhub_mmutcl2_mmvml2vcdec 5133 //MMVM_CONTEXT0_CNTL 5134 #define MMVM_CONTEXT0_CNTL__ENABLE_CONTEXT__SHIFT 0x0 5135 #define MMVM_CONTEXT0_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 5136 #define MMVM_CONTEXT0_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 5137 #define MMVM_CONTEXT0_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 5138 #define MMVM_CONTEXT0_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 5139 #define MMVM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 5140 #define MMVM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa 5141 #define MMVM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb 5142 #define MMVM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc 5143 #define MMVM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd 5144 #define MMVM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe 5145 #define MMVM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf 5146 #define MMVM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 5147 #define MMVM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 5148 #define MMVM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 5149 #define MMVM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 5150 #define MMVM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 5151 #define MMVM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 5152 #define MMVM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 5153 #define MMVM_CONTEXT0_CNTL__ENABLE_CONTEXT_MASK 0x00000001L 5154 #define MMVM_CONTEXT0_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L 5155 #define MMVM_CONTEXT0_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L 5156 #define MMVM_CONTEXT0_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L 5157 #define MMVM_CONTEXT0_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L 5158 #define MMVM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L 5159 #define MMVM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L 5160 #define MMVM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L 5161 #define MMVM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L 5162 #define MMVM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L 5163 #define MMVM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L 5164 #define MMVM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L 5165 #define MMVM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L 5166 #define MMVM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L 5167 #define MMVM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L 5168 #define MMVM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L 5169 #define MMVM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L 5170 #define MMVM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L 5171 #define MMVM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L 5172 //MMVM_CONTEXT1_CNTL 5173 #define MMVM_CONTEXT1_CNTL__ENABLE_CONTEXT__SHIFT 0x0 5174 #define MMVM_CONTEXT1_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 5175 #define MMVM_CONTEXT1_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 5176 #define MMVM_CONTEXT1_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 5177 #define MMVM_CONTEXT1_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 5178 #define MMVM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 5179 #define MMVM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa 5180 #define MMVM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb 5181 #define MMVM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc 5182 #define MMVM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd 5183 #define MMVM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe 5184 #define MMVM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf 5185 #define MMVM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 5186 #define MMVM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 5187 #define MMVM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 5188 #define MMVM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 5189 #define MMVM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 5190 #define MMVM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 5191 #define MMVM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 5192 #define MMVM_CONTEXT1_CNTL__ENABLE_CONTEXT_MASK 0x00000001L 5193 #define MMVM_CONTEXT1_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L 5194 #define MMVM_CONTEXT1_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L 5195 #define MMVM_CONTEXT1_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L 5196 #define MMVM_CONTEXT1_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L 5197 #define MMVM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L 5198 #define MMVM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L 5199 #define MMVM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L 5200 #define MMVM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L 5201 #define MMVM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L 5202 #define MMVM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L 5203 #define MMVM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L 5204 #define MMVM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L 5205 #define MMVM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L 5206 #define MMVM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L 5207 #define MMVM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L 5208 #define MMVM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L 5209 #define MMVM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L 5210 #define MMVM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L 5211 //MMVM_CONTEXT2_CNTL 5212 #define MMVM_CONTEXT2_CNTL__ENABLE_CONTEXT__SHIFT 0x0 5213 #define MMVM_CONTEXT2_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 5214 #define MMVM_CONTEXT2_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 5215 #define MMVM_CONTEXT2_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 5216 #define MMVM_CONTEXT2_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 5217 #define MMVM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 5218 #define MMVM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa 5219 #define MMVM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb 5220 #define MMVM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc 5221 #define MMVM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd 5222 #define MMVM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe 5223 #define MMVM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf 5224 #define MMVM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 5225 #define MMVM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 5226 #define MMVM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 5227 #define MMVM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 5228 #define MMVM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 5229 #define MMVM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 5230 #define MMVM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 5231 #define MMVM_CONTEXT2_CNTL__ENABLE_CONTEXT_MASK 0x00000001L 5232 #define MMVM_CONTEXT2_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L 5233 #define MMVM_CONTEXT2_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L 5234 #define MMVM_CONTEXT2_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L 5235 #define MMVM_CONTEXT2_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L 5236 #define MMVM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L 5237 #define MMVM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L 5238 #define MMVM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L 5239 #define MMVM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L 5240 #define MMVM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L 5241 #define MMVM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L 5242 #define MMVM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L 5243 #define MMVM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L 5244 #define MMVM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L 5245 #define MMVM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L 5246 #define MMVM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L 5247 #define MMVM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L 5248 #define MMVM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L 5249 #define MMVM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L 5250 //MMVM_CONTEXT3_CNTL 5251 #define MMVM_CONTEXT3_CNTL__ENABLE_CONTEXT__SHIFT 0x0 5252 #define MMVM_CONTEXT3_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 5253 #define MMVM_CONTEXT3_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 5254 #define MMVM_CONTEXT3_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 5255 #define MMVM_CONTEXT3_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 5256 #define MMVM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 5257 #define MMVM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa 5258 #define MMVM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb 5259 #define MMVM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc 5260 #define MMVM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd 5261 #define MMVM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe 5262 #define MMVM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf 5263 #define MMVM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 5264 #define MMVM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 5265 #define MMVM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 5266 #define MMVM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 5267 #define MMVM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 5268 #define MMVM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 5269 #define MMVM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 5270 #define MMVM_CONTEXT3_CNTL__ENABLE_CONTEXT_MASK 0x00000001L 5271 #define MMVM_CONTEXT3_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L 5272 #define MMVM_CONTEXT3_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L 5273 #define MMVM_CONTEXT3_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L 5274 #define MMVM_CONTEXT3_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L 5275 #define MMVM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L 5276 #define MMVM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L 5277 #define MMVM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L 5278 #define MMVM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L 5279 #define MMVM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L 5280 #define MMVM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L 5281 #define MMVM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L 5282 #define MMVM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L 5283 #define MMVM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L 5284 #define MMVM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L 5285 #define MMVM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L 5286 #define MMVM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L 5287 #define MMVM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L 5288 #define MMVM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L 5289 //MMVM_CONTEXT4_CNTL 5290 #define MMVM_CONTEXT4_CNTL__ENABLE_CONTEXT__SHIFT 0x0 5291 #define MMVM_CONTEXT4_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 5292 #define MMVM_CONTEXT4_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 5293 #define MMVM_CONTEXT4_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 5294 #define MMVM_CONTEXT4_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 5295 #define MMVM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 5296 #define MMVM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa 5297 #define MMVM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb 5298 #define MMVM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc 5299 #define MMVM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd 5300 #define MMVM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe 5301 #define MMVM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf 5302 #define MMVM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 5303 #define MMVM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 5304 #define MMVM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 5305 #define MMVM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 5306 #define MMVM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 5307 #define MMVM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 5308 #define MMVM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 5309 #define MMVM_CONTEXT4_CNTL__ENABLE_CONTEXT_MASK 0x00000001L 5310 #define MMVM_CONTEXT4_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L 5311 #define MMVM_CONTEXT4_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L 5312 #define MMVM_CONTEXT4_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L 5313 #define MMVM_CONTEXT4_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L 5314 #define MMVM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L 5315 #define MMVM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L 5316 #define MMVM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L 5317 #define MMVM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L 5318 #define MMVM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L 5319 #define MMVM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L 5320 #define MMVM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L 5321 #define MMVM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L 5322 #define MMVM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L 5323 #define MMVM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L 5324 #define MMVM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L 5325 #define MMVM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L 5326 #define MMVM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L 5327 #define MMVM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L 5328 //MMVM_CONTEXT5_CNTL 5329 #define MMVM_CONTEXT5_CNTL__ENABLE_CONTEXT__SHIFT 0x0 5330 #define MMVM_CONTEXT5_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 5331 #define MMVM_CONTEXT5_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 5332 #define MMVM_CONTEXT5_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 5333 #define MMVM_CONTEXT5_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 5334 #define MMVM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 5335 #define MMVM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa 5336 #define MMVM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb 5337 #define MMVM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc 5338 #define MMVM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd 5339 #define MMVM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe 5340 #define MMVM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf 5341 #define MMVM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 5342 #define MMVM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 5343 #define MMVM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 5344 #define MMVM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 5345 #define MMVM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 5346 #define MMVM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 5347 #define MMVM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 5348 #define MMVM_CONTEXT5_CNTL__ENABLE_CONTEXT_MASK 0x00000001L 5349 #define MMVM_CONTEXT5_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L 5350 #define MMVM_CONTEXT5_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L 5351 #define MMVM_CONTEXT5_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L 5352 #define MMVM_CONTEXT5_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L 5353 #define MMVM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L 5354 #define MMVM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L 5355 #define MMVM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L 5356 #define MMVM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L 5357 #define MMVM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L 5358 #define MMVM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L 5359 #define MMVM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L 5360 #define MMVM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L 5361 #define MMVM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L 5362 #define MMVM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L 5363 #define MMVM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L 5364 #define MMVM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L 5365 #define MMVM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L 5366 #define MMVM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L 5367 //MMVM_CONTEXT6_CNTL 5368 #define MMVM_CONTEXT6_CNTL__ENABLE_CONTEXT__SHIFT 0x0 5369 #define MMVM_CONTEXT6_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 5370 #define MMVM_CONTEXT6_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 5371 #define MMVM_CONTEXT6_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 5372 #define MMVM_CONTEXT6_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 5373 #define MMVM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 5374 #define MMVM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa 5375 #define MMVM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb 5376 #define MMVM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc 5377 #define MMVM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd 5378 #define MMVM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe 5379 #define MMVM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf 5380 #define MMVM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 5381 #define MMVM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 5382 #define MMVM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 5383 #define MMVM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 5384 #define MMVM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 5385 #define MMVM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 5386 #define MMVM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 5387 #define MMVM_CONTEXT6_CNTL__ENABLE_CONTEXT_MASK 0x00000001L 5388 #define MMVM_CONTEXT6_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L 5389 #define MMVM_CONTEXT6_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L 5390 #define MMVM_CONTEXT6_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L 5391 #define MMVM_CONTEXT6_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L 5392 #define MMVM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L 5393 #define MMVM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L 5394 #define MMVM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L 5395 #define MMVM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L 5396 #define MMVM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L 5397 #define MMVM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L 5398 #define MMVM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L 5399 #define MMVM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L 5400 #define MMVM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L 5401 #define MMVM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L 5402 #define MMVM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L 5403 #define MMVM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L 5404 #define MMVM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L 5405 #define MMVM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L 5406 //MMVM_CONTEXT7_CNTL 5407 #define MMVM_CONTEXT7_CNTL__ENABLE_CONTEXT__SHIFT 0x0 5408 #define MMVM_CONTEXT7_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 5409 #define MMVM_CONTEXT7_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 5410 #define MMVM_CONTEXT7_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 5411 #define MMVM_CONTEXT7_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 5412 #define MMVM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 5413 #define MMVM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa 5414 #define MMVM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb 5415 #define MMVM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc 5416 #define MMVM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd 5417 #define MMVM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe 5418 #define MMVM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf 5419 #define MMVM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 5420 #define MMVM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 5421 #define MMVM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 5422 #define MMVM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 5423 #define MMVM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 5424 #define MMVM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 5425 #define MMVM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 5426 #define MMVM_CONTEXT7_CNTL__ENABLE_CONTEXT_MASK 0x00000001L 5427 #define MMVM_CONTEXT7_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L 5428 #define MMVM_CONTEXT7_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L 5429 #define MMVM_CONTEXT7_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L 5430 #define MMVM_CONTEXT7_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L 5431 #define MMVM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L 5432 #define MMVM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L 5433 #define MMVM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L 5434 #define MMVM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L 5435 #define MMVM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L 5436 #define MMVM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L 5437 #define MMVM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L 5438 #define MMVM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L 5439 #define MMVM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L 5440 #define MMVM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L 5441 #define MMVM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L 5442 #define MMVM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L 5443 #define MMVM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L 5444 #define MMVM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L 5445 //MMVM_CONTEXT8_CNTL 5446 #define MMVM_CONTEXT8_CNTL__ENABLE_CONTEXT__SHIFT 0x0 5447 #define MMVM_CONTEXT8_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 5448 #define MMVM_CONTEXT8_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 5449 #define MMVM_CONTEXT8_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 5450 #define MMVM_CONTEXT8_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 5451 #define MMVM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 5452 #define MMVM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa 5453 #define MMVM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb 5454 #define MMVM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc 5455 #define MMVM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd 5456 #define MMVM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe 5457 #define MMVM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf 5458 #define MMVM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 5459 #define MMVM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 5460 #define MMVM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 5461 #define MMVM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 5462 #define MMVM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 5463 #define MMVM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 5464 #define MMVM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 5465 #define MMVM_CONTEXT8_CNTL__ENABLE_CONTEXT_MASK 0x00000001L 5466 #define MMVM_CONTEXT8_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L 5467 #define MMVM_CONTEXT8_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L 5468 #define MMVM_CONTEXT8_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L 5469 #define MMVM_CONTEXT8_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L 5470 #define MMVM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L 5471 #define MMVM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L 5472 #define MMVM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L 5473 #define MMVM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L 5474 #define MMVM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L 5475 #define MMVM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L 5476 #define MMVM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L 5477 #define MMVM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L 5478 #define MMVM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L 5479 #define MMVM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L 5480 #define MMVM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L 5481 #define MMVM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L 5482 #define MMVM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L 5483 #define MMVM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L 5484 //MMVM_CONTEXT9_CNTL 5485 #define MMVM_CONTEXT9_CNTL__ENABLE_CONTEXT__SHIFT 0x0 5486 #define MMVM_CONTEXT9_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 5487 #define MMVM_CONTEXT9_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 5488 #define MMVM_CONTEXT9_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 5489 #define MMVM_CONTEXT9_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 5490 #define MMVM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 5491 #define MMVM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa 5492 #define MMVM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb 5493 #define MMVM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc 5494 #define MMVM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd 5495 #define MMVM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe 5496 #define MMVM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf 5497 #define MMVM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 5498 #define MMVM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 5499 #define MMVM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 5500 #define MMVM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 5501 #define MMVM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 5502 #define MMVM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 5503 #define MMVM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 5504 #define MMVM_CONTEXT9_CNTL__ENABLE_CONTEXT_MASK 0x00000001L 5505 #define MMVM_CONTEXT9_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L 5506 #define MMVM_CONTEXT9_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L 5507 #define MMVM_CONTEXT9_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L 5508 #define MMVM_CONTEXT9_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L 5509 #define MMVM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L 5510 #define MMVM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L 5511 #define MMVM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L 5512 #define MMVM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L 5513 #define MMVM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L 5514 #define MMVM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L 5515 #define MMVM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L 5516 #define MMVM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L 5517 #define MMVM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L 5518 #define MMVM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L 5519 #define MMVM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L 5520 #define MMVM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L 5521 #define MMVM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L 5522 #define MMVM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L 5523 //MMVM_CONTEXT10_CNTL 5524 #define MMVM_CONTEXT10_CNTL__ENABLE_CONTEXT__SHIFT 0x0 5525 #define MMVM_CONTEXT10_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 5526 #define MMVM_CONTEXT10_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 5527 #define MMVM_CONTEXT10_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 5528 #define MMVM_CONTEXT10_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 5529 #define MMVM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 5530 #define MMVM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa 5531 #define MMVM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb 5532 #define MMVM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc 5533 #define MMVM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd 5534 #define MMVM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe 5535 #define MMVM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf 5536 #define MMVM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 5537 #define MMVM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 5538 #define MMVM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 5539 #define MMVM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 5540 #define MMVM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 5541 #define MMVM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 5542 #define MMVM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 5543 #define MMVM_CONTEXT10_CNTL__ENABLE_CONTEXT_MASK 0x00000001L 5544 #define MMVM_CONTEXT10_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L 5545 #define MMVM_CONTEXT10_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L 5546 #define MMVM_CONTEXT10_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L 5547 #define MMVM_CONTEXT10_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L 5548 #define MMVM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L 5549 #define MMVM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L 5550 #define MMVM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L 5551 #define MMVM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L 5552 #define MMVM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L 5553 #define MMVM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L 5554 #define MMVM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L 5555 #define MMVM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L 5556 #define MMVM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L 5557 #define MMVM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L 5558 #define MMVM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L 5559 #define MMVM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L 5560 #define MMVM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L 5561 #define MMVM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L 5562 //MMVM_CONTEXT11_CNTL 5563 #define MMVM_CONTEXT11_CNTL__ENABLE_CONTEXT__SHIFT 0x0 5564 #define MMVM_CONTEXT11_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 5565 #define MMVM_CONTEXT11_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 5566 #define MMVM_CONTEXT11_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 5567 #define MMVM_CONTEXT11_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 5568 #define MMVM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 5569 #define MMVM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa 5570 #define MMVM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb 5571 #define MMVM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc 5572 #define MMVM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd 5573 #define MMVM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe 5574 #define MMVM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf 5575 #define MMVM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 5576 #define MMVM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 5577 #define MMVM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 5578 #define MMVM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 5579 #define MMVM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 5580 #define MMVM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 5581 #define MMVM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 5582 #define MMVM_CONTEXT11_CNTL__ENABLE_CONTEXT_MASK 0x00000001L 5583 #define MMVM_CONTEXT11_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L 5584 #define MMVM_CONTEXT11_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L 5585 #define MMVM_CONTEXT11_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L 5586 #define MMVM_CONTEXT11_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L 5587 #define MMVM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L 5588 #define MMVM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L 5589 #define MMVM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L 5590 #define MMVM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L 5591 #define MMVM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L 5592 #define MMVM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L 5593 #define MMVM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L 5594 #define MMVM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L 5595 #define MMVM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L 5596 #define MMVM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L 5597 #define MMVM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L 5598 #define MMVM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L 5599 #define MMVM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L 5600 #define MMVM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L 5601 //MMVM_CONTEXT12_CNTL 5602 #define MMVM_CONTEXT12_CNTL__ENABLE_CONTEXT__SHIFT 0x0 5603 #define MMVM_CONTEXT12_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 5604 #define MMVM_CONTEXT12_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 5605 #define MMVM_CONTEXT12_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 5606 #define MMVM_CONTEXT12_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 5607 #define MMVM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 5608 #define MMVM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa 5609 #define MMVM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb 5610 #define MMVM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc 5611 #define MMVM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd 5612 #define MMVM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe 5613 #define MMVM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf 5614 #define MMVM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 5615 #define MMVM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 5616 #define MMVM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 5617 #define MMVM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 5618 #define MMVM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 5619 #define MMVM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 5620 #define MMVM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 5621 #define MMVM_CONTEXT12_CNTL__ENABLE_CONTEXT_MASK 0x00000001L 5622 #define MMVM_CONTEXT12_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L 5623 #define MMVM_CONTEXT12_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L 5624 #define MMVM_CONTEXT12_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L 5625 #define MMVM_CONTEXT12_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L 5626 #define MMVM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L 5627 #define MMVM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L 5628 #define MMVM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L 5629 #define MMVM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L 5630 #define MMVM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L 5631 #define MMVM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L 5632 #define MMVM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L 5633 #define MMVM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L 5634 #define MMVM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L 5635 #define MMVM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L 5636 #define MMVM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L 5637 #define MMVM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L 5638 #define MMVM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L 5639 #define MMVM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L 5640 //MMVM_CONTEXT13_CNTL 5641 #define MMVM_CONTEXT13_CNTL__ENABLE_CONTEXT__SHIFT 0x0 5642 #define MMVM_CONTEXT13_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 5643 #define MMVM_CONTEXT13_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 5644 #define MMVM_CONTEXT13_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 5645 #define MMVM_CONTEXT13_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 5646 #define MMVM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 5647 #define MMVM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa 5648 #define MMVM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb 5649 #define MMVM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc 5650 #define MMVM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd 5651 #define MMVM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe 5652 #define MMVM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf 5653 #define MMVM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 5654 #define MMVM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 5655 #define MMVM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 5656 #define MMVM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 5657 #define MMVM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 5658 #define MMVM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 5659 #define MMVM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 5660 #define MMVM_CONTEXT13_CNTL__ENABLE_CONTEXT_MASK 0x00000001L 5661 #define MMVM_CONTEXT13_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L 5662 #define MMVM_CONTEXT13_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L 5663 #define MMVM_CONTEXT13_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L 5664 #define MMVM_CONTEXT13_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L 5665 #define MMVM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L 5666 #define MMVM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L 5667 #define MMVM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L 5668 #define MMVM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L 5669 #define MMVM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L 5670 #define MMVM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L 5671 #define MMVM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L 5672 #define MMVM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L 5673 #define MMVM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L 5674 #define MMVM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L 5675 #define MMVM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L 5676 #define MMVM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L 5677 #define MMVM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L 5678 #define MMVM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L 5679 //MMVM_CONTEXT14_CNTL 5680 #define MMVM_CONTEXT14_CNTL__ENABLE_CONTEXT__SHIFT 0x0 5681 #define MMVM_CONTEXT14_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 5682 #define MMVM_CONTEXT14_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 5683 #define MMVM_CONTEXT14_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 5684 #define MMVM_CONTEXT14_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 5685 #define MMVM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 5686 #define MMVM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa 5687 #define MMVM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb 5688 #define MMVM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc 5689 #define MMVM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd 5690 #define MMVM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe 5691 #define MMVM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf 5692 #define MMVM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 5693 #define MMVM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 5694 #define MMVM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 5695 #define MMVM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 5696 #define MMVM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 5697 #define MMVM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 5698 #define MMVM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 5699 #define MMVM_CONTEXT14_CNTL__ENABLE_CONTEXT_MASK 0x00000001L 5700 #define MMVM_CONTEXT14_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L 5701 #define MMVM_CONTEXT14_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L 5702 #define MMVM_CONTEXT14_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L 5703 #define MMVM_CONTEXT14_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L 5704 #define MMVM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L 5705 #define MMVM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L 5706 #define MMVM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L 5707 #define MMVM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L 5708 #define MMVM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L 5709 #define MMVM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L 5710 #define MMVM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L 5711 #define MMVM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L 5712 #define MMVM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L 5713 #define MMVM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L 5714 #define MMVM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L 5715 #define MMVM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L 5716 #define MMVM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L 5717 #define MMVM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L 5718 //MMVM_CONTEXT15_CNTL 5719 #define MMVM_CONTEXT15_CNTL__ENABLE_CONTEXT__SHIFT 0x0 5720 #define MMVM_CONTEXT15_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 5721 #define MMVM_CONTEXT15_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 5722 #define MMVM_CONTEXT15_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 5723 #define MMVM_CONTEXT15_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 5724 #define MMVM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 5725 #define MMVM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa 5726 #define MMVM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb 5727 #define MMVM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc 5728 #define MMVM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd 5729 #define MMVM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe 5730 #define MMVM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf 5731 #define MMVM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 5732 #define MMVM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 5733 #define MMVM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 5734 #define MMVM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 5735 #define MMVM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 5736 #define MMVM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 5737 #define MMVM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 5738 #define MMVM_CONTEXT15_CNTL__ENABLE_CONTEXT_MASK 0x00000001L 5739 #define MMVM_CONTEXT15_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L 5740 #define MMVM_CONTEXT15_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L 5741 #define MMVM_CONTEXT15_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L 5742 #define MMVM_CONTEXT15_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L 5743 #define MMVM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L 5744 #define MMVM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L 5745 #define MMVM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L 5746 #define MMVM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L 5747 #define MMVM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L 5748 #define MMVM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L 5749 #define MMVM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L 5750 #define MMVM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L 5751 #define MMVM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L 5752 #define MMVM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L 5753 #define MMVM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L 5754 #define MMVM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L 5755 #define MMVM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L 5756 #define MMVM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L 5757 //MMVM_CONTEXTS_DISABLE 5758 #define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_0__SHIFT 0x0 5759 #define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_1__SHIFT 0x1 5760 #define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_2__SHIFT 0x2 5761 #define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_3__SHIFT 0x3 5762 #define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_4__SHIFT 0x4 5763 #define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_5__SHIFT 0x5 5764 #define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_6__SHIFT 0x6 5765 #define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_7__SHIFT 0x7 5766 #define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_8__SHIFT 0x8 5767 #define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_9__SHIFT 0x9 5768 #define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_10__SHIFT 0xa 5769 #define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_11__SHIFT 0xb 5770 #define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_12__SHIFT 0xc 5771 #define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_13__SHIFT 0xd 5772 #define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_14__SHIFT 0xe 5773 #define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_15__SHIFT 0xf 5774 #define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_0_MASK 0x00000001L 5775 #define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_1_MASK 0x00000002L 5776 #define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_2_MASK 0x00000004L 5777 #define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_3_MASK 0x00000008L 5778 #define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_4_MASK 0x00000010L 5779 #define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_5_MASK 0x00000020L 5780 #define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_6_MASK 0x00000040L 5781 #define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_7_MASK 0x00000080L 5782 #define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_8_MASK 0x00000100L 5783 #define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_9_MASK 0x00000200L 5784 #define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_10_MASK 0x00000400L 5785 #define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_11_MASK 0x00000800L 5786 #define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_12_MASK 0x00001000L 5787 #define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_13_MASK 0x00002000L 5788 #define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_14_MASK 0x00004000L 5789 #define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_15_MASK 0x00008000L 5790 //MMVM_INVALIDATE_ENG0_SEM 5791 #define MMVM_INVALIDATE_ENG0_SEM__SEMAPHORE__SHIFT 0x0 5792 #define MMVM_INVALIDATE_ENG0_SEM__SEMAPHORE_MASK 0x00000001L 5793 //MMVM_INVALIDATE_ENG1_SEM 5794 #define MMVM_INVALIDATE_ENG1_SEM__SEMAPHORE__SHIFT 0x0 5795 #define MMVM_INVALIDATE_ENG1_SEM__SEMAPHORE_MASK 0x00000001L 5796 //MMVM_INVALIDATE_ENG2_SEM 5797 #define MMVM_INVALIDATE_ENG2_SEM__SEMAPHORE__SHIFT 0x0 5798 #define MMVM_INVALIDATE_ENG2_SEM__SEMAPHORE_MASK 0x00000001L 5799 //MMVM_INVALIDATE_ENG3_SEM 5800 #define MMVM_INVALIDATE_ENG3_SEM__SEMAPHORE__SHIFT 0x0 5801 #define MMVM_INVALIDATE_ENG3_SEM__SEMAPHORE_MASK 0x00000001L 5802 //MMVM_INVALIDATE_ENG4_SEM 5803 #define MMVM_INVALIDATE_ENG4_SEM__SEMAPHORE__SHIFT 0x0 5804 #define MMVM_INVALIDATE_ENG4_SEM__SEMAPHORE_MASK 0x00000001L 5805 //MMVM_INVALIDATE_ENG5_SEM 5806 #define MMVM_INVALIDATE_ENG5_SEM__SEMAPHORE__SHIFT 0x0 5807 #define MMVM_INVALIDATE_ENG5_SEM__SEMAPHORE_MASK 0x00000001L 5808 //MMVM_INVALIDATE_ENG6_SEM 5809 #define MMVM_INVALIDATE_ENG6_SEM__SEMAPHORE__SHIFT 0x0 5810 #define MMVM_INVALIDATE_ENG6_SEM__SEMAPHORE_MASK 0x00000001L 5811 //MMVM_INVALIDATE_ENG7_SEM 5812 #define MMVM_INVALIDATE_ENG7_SEM__SEMAPHORE__SHIFT 0x0 5813 #define MMVM_INVALIDATE_ENG7_SEM__SEMAPHORE_MASK 0x00000001L 5814 //MMVM_INVALIDATE_ENG8_SEM 5815 #define MMVM_INVALIDATE_ENG8_SEM__SEMAPHORE__SHIFT 0x0 5816 #define MMVM_INVALIDATE_ENG8_SEM__SEMAPHORE_MASK 0x00000001L 5817 //MMVM_INVALIDATE_ENG9_SEM 5818 #define MMVM_INVALIDATE_ENG9_SEM__SEMAPHORE__SHIFT 0x0 5819 #define MMVM_INVALIDATE_ENG9_SEM__SEMAPHORE_MASK 0x00000001L 5820 //MMVM_INVALIDATE_ENG10_SEM 5821 #define MMVM_INVALIDATE_ENG10_SEM__SEMAPHORE__SHIFT 0x0 5822 #define MMVM_INVALIDATE_ENG10_SEM__SEMAPHORE_MASK 0x00000001L 5823 //MMVM_INVALIDATE_ENG11_SEM 5824 #define MMVM_INVALIDATE_ENG11_SEM__SEMAPHORE__SHIFT 0x0 5825 #define MMVM_INVALIDATE_ENG11_SEM__SEMAPHORE_MASK 0x00000001L 5826 //MMVM_INVALIDATE_ENG12_SEM 5827 #define MMVM_INVALIDATE_ENG12_SEM__SEMAPHORE__SHIFT 0x0 5828 #define MMVM_INVALIDATE_ENG12_SEM__SEMAPHORE_MASK 0x00000001L 5829 //MMVM_INVALIDATE_ENG13_SEM 5830 #define MMVM_INVALIDATE_ENG13_SEM__SEMAPHORE__SHIFT 0x0 5831 #define MMVM_INVALIDATE_ENG13_SEM__SEMAPHORE_MASK 0x00000001L 5832 //MMVM_INVALIDATE_ENG14_SEM 5833 #define MMVM_INVALIDATE_ENG14_SEM__SEMAPHORE__SHIFT 0x0 5834 #define MMVM_INVALIDATE_ENG14_SEM__SEMAPHORE_MASK 0x00000001L 5835 //MMVM_INVALIDATE_ENG15_SEM 5836 #define MMVM_INVALIDATE_ENG15_SEM__SEMAPHORE__SHIFT 0x0 5837 #define MMVM_INVALIDATE_ENG15_SEM__SEMAPHORE_MASK 0x00000001L 5838 //MMVM_INVALIDATE_ENG16_SEM 5839 #define MMVM_INVALIDATE_ENG16_SEM__SEMAPHORE__SHIFT 0x0 5840 #define MMVM_INVALIDATE_ENG16_SEM__SEMAPHORE_MASK 0x00000001L 5841 //MMVM_INVALIDATE_ENG17_SEM 5842 #define MMVM_INVALIDATE_ENG17_SEM__SEMAPHORE__SHIFT 0x0 5843 #define MMVM_INVALIDATE_ENG17_SEM__SEMAPHORE_MASK 0x00000001L 5844 //MMVM_INVALIDATE_ENG0_REQ 5845 #define MMVM_INVALIDATE_ENG0_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 5846 #define MMVM_INVALIDATE_ENG0_REQ__FLUSH_TYPE__SHIFT 0x10 5847 #define MMVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 5848 #define MMVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 5849 #define MMVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 5850 #define MMVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 5851 #define MMVM_INVALIDATE_ENG0_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 5852 #define MMVM_INVALIDATE_ENG0_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 5853 #define MMVM_INVALIDATE_ENG0_REQ__LOG_REQUEST__SHIFT 0x19 5854 #define MMVM_INVALIDATE_ENG0_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a 5855 #define MMVM_INVALIDATE_ENG0_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL 5856 #define MMVM_INVALIDATE_ENG0_REQ__FLUSH_TYPE_MASK 0x00070000L 5857 #define MMVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L 5858 #define MMVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L 5859 #define MMVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L 5860 #define MMVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L 5861 #define MMVM_INVALIDATE_ENG0_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L 5862 #define MMVM_INVALIDATE_ENG0_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L 5863 #define MMVM_INVALIDATE_ENG0_REQ__LOG_REQUEST_MASK 0x02000000L 5864 #define MMVM_INVALIDATE_ENG0_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L 5865 //MMVM_INVALIDATE_ENG1_REQ 5866 #define MMVM_INVALIDATE_ENG1_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 5867 #define MMVM_INVALIDATE_ENG1_REQ__FLUSH_TYPE__SHIFT 0x10 5868 #define MMVM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 5869 #define MMVM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 5870 #define MMVM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 5871 #define MMVM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 5872 #define MMVM_INVALIDATE_ENG1_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 5873 #define MMVM_INVALIDATE_ENG1_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 5874 #define MMVM_INVALIDATE_ENG1_REQ__LOG_REQUEST__SHIFT 0x19 5875 #define MMVM_INVALIDATE_ENG1_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a 5876 #define MMVM_INVALIDATE_ENG1_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL 5877 #define MMVM_INVALIDATE_ENG1_REQ__FLUSH_TYPE_MASK 0x00070000L 5878 #define MMVM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L 5879 #define MMVM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L 5880 #define MMVM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L 5881 #define MMVM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L 5882 #define MMVM_INVALIDATE_ENG1_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L 5883 #define MMVM_INVALIDATE_ENG1_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L 5884 #define MMVM_INVALIDATE_ENG1_REQ__LOG_REQUEST_MASK 0x02000000L 5885 #define MMVM_INVALIDATE_ENG1_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L 5886 //MMVM_INVALIDATE_ENG2_REQ 5887 #define MMVM_INVALIDATE_ENG2_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 5888 #define MMVM_INVALIDATE_ENG2_REQ__FLUSH_TYPE__SHIFT 0x10 5889 #define MMVM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 5890 #define MMVM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 5891 #define MMVM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 5892 #define MMVM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 5893 #define MMVM_INVALIDATE_ENG2_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 5894 #define MMVM_INVALIDATE_ENG2_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 5895 #define MMVM_INVALIDATE_ENG2_REQ__LOG_REQUEST__SHIFT 0x19 5896 #define MMVM_INVALIDATE_ENG2_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a 5897 #define MMVM_INVALIDATE_ENG2_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL 5898 #define MMVM_INVALIDATE_ENG2_REQ__FLUSH_TYPE_MASK 0x00070000L 5899 #define MMVM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L 5900 #define MMVM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L 5901 #define MMVM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L 5902 #define MMVM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L 5903 #define MMVM_INVALIDATE_ENG2_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L 5904 #define MMVM_INVALIDATE_ENG2_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L 5905 #define MMVM_INVALIDATE_ENG2_REQ__LOG_REQUEST_MASK 0x02000000L 5906 #define MMVM_INVALIDATE_ENG2_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L 5907 //MMVM_INVALIDATE_ENG3_REQ 5908 #define MMVM_INVALIDATE_ENG3_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 5909 #define MMVM_INVALIDATE_ENG3_REQ__FLUSH_TYPE__SHIFT 0x10 5910 #define MMVM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 5911 #define MMVM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 5912 #define MMVM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 5913 #define MMVM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 5914 #define MMVM_INVALIDATE_ENG3_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 5915 #define MMVM_INVALIDATE_ENG3_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 5916 #define MMVM_INVALIDATE_ENG3_REQ__LOG_REQUEST__SHIFT 0x19 5917 #define MMVM_INVALIDATE_ENG3_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a 5918 #define MMVM_INVALIDATE_ENG3_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL 5919 #define MMVM_INVALIDATE_ENG3_REQ__FLUSH_TYPE_MASK 0x00070000L 5920 #define MMVM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L 5921 #define MMVM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L 5922 #define MMVM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L 5923 #define MMVM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L 5924 #define MMVM_INVALIDATE_ENG3_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L 5925 #define MMVM_INVALIDATE_ENG3_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L 5926 #define MMVM_INVALIDATE_ENG3_REQ__LOG_REQUEST_MASK 0x02000000L 5927 #define MMVM_INVALIDATE_ENG3_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L 5928 //MMVM_INVALIDATE_ENG4_REQ 5929 #define MMVM_INVALIDATE_ENG4_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 5930 #define MMVM_INVALIDATE_ENG4_REQ__FLUSH_TYPE__SHIFT 0x10 5931 #define MMVM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 5932 #define MMVM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 5933 #define MMVM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 5934 #define MMVM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 5935 #define MMVM_INVALIDATE_ENG4_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 5936 #define MMVM_INVALIDATE_ENG4_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 5937 #define MMVM_INVALIDATE_ENG4_REQ__LOG_REQUEST__SHIFT 0x19 5938 #define MMVM_INVALIDATE_ENG4_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a 5939 #define MMVM_INVALIDATE_ENG4_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL 5940 #define MMVM_INVALIDATE_ENG4_REQ__FLUSH_TYPE_MASK 0x00070000L 5941 #define MMVM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L 5942 #define MMVM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L 5943 #define MMVM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L 5944 #define MMVM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L 5945 #define MMVM_INVALIDATE_ENG4_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L 5946 #define MMVM_INVALIDATE_ENG4_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L 5947 #define MMVM_INVALIDATE_ENG4_REQ__LOG_REQUEST_MASK 0x02000000L 5948 #define MMVM_INVALIDATE_ENG4_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L 5949 //MMVM_INVALIDATE_ENG5_REQ 5950 #define MMVM_INVALIDATE_ENG5_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 5951 #define MMVM_INVALIDATE_ENG5_REQ__FLUSH_TYPE__SHIFT 0x10 5952 #define MMVM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 5953 #define MMVM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 5954 #define MMVM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 5955 #define MMVM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 5956 #define MMVM_INVALIDATE_ENG5_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 5957 #define MMVM_INVALIDATE_ENG5_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 5958 #define MMVM_INVALIDATE_ENG5_REQ__LOG_REQUEST__SHIFT 0x19 5959 #define MMVM_INVALIDATE_ENG5_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a 5960 #define MMVM_INVALIDATE_ENG5_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL 5961 #define MMVM_INVALIDATE_ENG5_REQ__FLUSH_TYPE_MASK 0x00070000L 5962 #define MMVM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L 5963 #define MMVM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L 5964 #define MMVM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L 5965 #define MMVM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L 5966 #define MMVM_INVALIDATE_ENG5_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L 5967 #define MMVM_INVALIDATE_ENG5_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L 5968 #define MMVM_INVALIDATE_ENG5_REQ__LOG_REQUEST_MASK 0x02000000L 5969 #define MMVM_INVALIDATE_ENG5_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L 5970 //MMVM_INVALIDATE_ENG6_REQ 5971 #define MMVM_INVALIDATE_ENG6_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 5972 #define MMVM_INVALIDATE_ENG6_REQ__FLUSH_TYPE__SHIFT 0x10 5973 #define MMVM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 5974 #define MMVM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 5975 #define MMVM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 5976 #define MMVM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 5977 #define MMVM_INVALIDATE_ENG6_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 5978 #define MMVM_INVALIDATE_ENG6_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 5979 #define MMVM_INVALIDATE_ENG6_REQ__LOG_REQUEST__SHIFT 0x19 5980 #define MMVM_INVALIDATE_ENG6_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a 5981 #define MMVM_INVALIDATE_ENG6_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL 5982 #define MMVM_INVALIDATE_ENG6_REQ__FLUSH_TYPE_MASK 0x00070000L 5983 #define MMVM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L 5984 #define MMVM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L 5985 #define MMVM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L 5986 #define MMVM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L 5987 #define MMVM_INVALIDATE_ENG6_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L 5988 #define MMVM_INVALIDATE_ENG6_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L 5989 #define MMVM_INVALIDATE_ENG6_REQ__LOG_REQUEST_MASK 0x02000000L 5990 #define MMVM_INVALIDATE_ENG6_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L 5991 //MMVM_INVALIDATE_ENG7_REQ 5992 #define MMVM_INVALIDATE_ENG7_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 5993 #define MMVM_INVALIDATE_ENG7_REQ__FLUSH_TYPE__SHIFT 0x10 5994 #define MMVM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 5995 #define MMVM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 5996 #define MMVM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 5997 #define MMVM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 5998 #define MMVM_INVALIDATE_ENG7_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 5999 #define MMVM_INVALIDATE_ENG7_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 6000 #define MMVM_INVALIDATE_ENG7_REQ__LOG_REQUEST__SHIFT 0x19 6001 #define MMVM_INVALIDATE_ENG7_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a 6002 #define MMVM_INVALIDATE_ENG7_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL 6003 #define MMVM_INVALIDATE_ENG7_REQ__FLUSH_TYPE_MASK 0x00070000L 6004 #define MMVM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L 6005 #define MMVM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L 6006 #define MMVM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L 6007 #define MMVM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L 6008 #define MMVM_INVALIDATE_ENG7_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L 6009 #define MMVM_INVALIDATE_ENG7_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L 6010 #define MMVM_INVALIDATE_ENG7_REQ__LOG_REQUEST_MASK 0x02000000L 6011 #define MMVM_INVALIDATE_ENG7_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L 6012 //MMVM_INVALIDATE_ENG8_REQ 6013 #define MMVM_INVALIDATE_ENG8_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 6014 #define MMVM_INVALIDATE_ENG8_REQ__FLUSH_TYPE__SHIFT 0x10 6015 #define MMVM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 6016 #define MMVM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 6017 #define MMVM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 6018 #define MMVM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 6019 #define MMVM_INVALIDATE_ENG8_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 6020 #define MMVM_INVALIDATE_ENG8_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 6021 #define MMVM_INVALIDATE_ENG8_REQ__LOG_REQUEST__SHIFT 0x19 6022 #define MMVM_INVALIDATE_ENG8_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a 6023 #define MMVM_INVALIDATE_ENG8_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL 6024 #define MMVM_INVALIDATE_ENG8_REQ__FLUSH_TYPE_MASK 0x00070000L 6025 #define MMVM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L 6026 #define MMVM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L 6027 #define MMVM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L 6028 #define MMVM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L 6029 #define MMVM_INVALIDATE_ENG8_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L 6030 #define MMVM_INVALIDATE_ENG8_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L 6031 #define MMVM_INVALIDATE_ENG8_REQ__LOG_REQUEST_MASK 0x02000000L 6032 #define MMVM_INVALIDATE_ENG8_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L 6033 //MMVM_INVALIDATE_ENG9_REQ 6034 #define MMVM_INVALIDATE_ENG9_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 6035 #define MMVM_INVALIDATE_ENG9_REQ__FLUSH_TYPE__SHIFT 0x10 6036 #define MMVM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 6037 #define MMVM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 6038 #define MMVM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 6039 #define MMVM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 6040 #define MMVM_INVALIDATE_ENG9_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 6041 #define MMVM_INVALIDATE_ENG9_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 6042 #define MMVM_INVALIDATE_ENG9_REQ__LOG_REQUEST__SHIFT 0x19 6043 #define MMVM_INVALIDATE_ENG9_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a 6044 #define MMVM_INVALIDATE_ENG9_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL 6045 #define MMVM_INVALIDATE_ENG9_REQ__FLUSH_TYPE_MASK 0x00070000L 6046 #define MMVM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L 6047 #define MMVM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L 6048 #define MMVM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L 6049 #define MMVM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L 6050 #define MMVM_INVALIDATE_ENG9_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L 6051 #define MMVM_INVALIDATE_ENG9_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L 6052 #define MMVM_INVALIDATE_ENG9_REQ__LOG_REQUEST_MASK 0x02000000L 6053 #define MMVM_INVALIDATE_ENG9_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L 6054 //MMVM_INVALIDATE_ENG10_REQ 6055 #define MMVM_INVALIDATE_ENG10_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 6056 #define MMVM_INVALIDATE_ENG10_REQ__FLUSH_TYPE__SHIFT 0x10 6057 #define MMVM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 6058 #define MMVM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 6059 #define MMVM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 6060 #define MMVM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 6061 #define MMVM_INVALIDATE_ENG10_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 6062 #define MMVM_INVALIDATE_ENG10_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 6063 #define MMVM_INVALIDATE_ENG10_REQ__LOG_REQUEST__SHIFT 0x19 6064 #define MMVM_INVALIDATE_ENG10_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a 6065 #define MMVM_INVALIDATE_ENG10_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL 6066 #define MMVM_INVALIDATE_ENG10_REQ__FLUSH_TYPE_MASK 0x00070000L 6067 #define MMVM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L 6068 #define MMVM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L 6069 #define MMVM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L 6070 #define MMVM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L 6071 #define MMVM_INVALIDATE_ENG10_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L 6072 #define MMVM_INVALIDATE_ENG10_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L 6073 #define MMVM_INVALIDATE_ENG10_REQ__LOG_REQUEST_MASK 0x02000000L 6074 #define MMVM_INVALIDATE_ENG10_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L 6075 //MMVM_INVALIDATE_ENG11_REQ 6076 #define MMVM_INVALIDATE_ENG11_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 6077 #define MMVM_INVALIDATE_ENG11_REQ__FLUSH_TYPE__SHIFT 0x10 6078 #define MMVM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 6079 #define MMVM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 6080 #define MMVM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 6081 #define MMVM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 6082 #define MMVM_INVALIDATE_ENG11_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 6083 #define MMVM_INVALIDATE_ENG11_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 6084 #define MMVM_INVALIDATE_ENG11_REQ__LOG_REQUEST__SHIFT 0x19 6085 #define MMVM_INVALIDATE_ENG11_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a 6086 #define MMVM_INVALIDATE_ENG11_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL 6087 #define MMVM_INVALIDATE_ENG11_REQ__FLUSH_TYPE_MASK 0x00070000L 6088 #define MMVM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L 6089 #define MMVM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L 6090 #define MMVM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L 6091 #define MMVM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L 6092 #define MMVM_INVALIDATE_ENG11_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L 6093 #define MMVM_INVALIDATE_ENG11_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L 6094 #define MMVM_INVALIDATE_ENG11_REQ__LOG_REQUEST_MASK 0x02000000L 6095 #define MMVM_INVALIDATE_ENG11_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L 6096 //MMVM_INVALIDATE_ENG12_REQ 6097 #define MMVM_INVALIDATE_ENG12_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 6098 #define MMVM_INVALIDATE_ENG12_REQ__FLUSH_TYPE__SHIFT 0x10 6099 #define MMVM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 6100 #define MMVM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 6101 #define MMVM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 6102 #define MMVM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 6103 #define MMVM_INVALIDATE_ENG12_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 6104 #define MMVM_INVALIDATE_ENG12_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 6105 #define MMVM_INVALIDATE_ENG12_REQ__LOG_REQUEST__SHIFT 0x19 6106 #define MMVM_INVALIDATE_ENG12_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a 6107 #define MMVM_INVALIDATE_ENG12_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL 6108 #define MMVM_INVALIDATE_ENG12_REQ__FLUSH_TYPE_MASK 0x00070000L 6109 #define MMVM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L 6110 #define MMVM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L 6111 #define MMVM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L 6112 #define MMVM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L 6113 #define MMVM_INVALIDATE_ENG12_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L 6114 #define MMVM_INVALIDATE_ENG12_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L 6115 #define MMVM_INVALIDATE_ENG12_REQ__LOG_REQUEST_MASK 0x02000000L 6116 #define MMVM_INVALIDATE_ENG12_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L 6117 //MMVM_INVALIDATE_ENG13_REQ 6118 #define MMVM_INVALIDATE_ENG13_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 6119 #define MMVM_INVALIDATE_ENG13_REQ__FLUSH_TYPE__SHIFT 0x10 6120 #define MMVM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 6121 #define MMVM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 6122 #define MMVM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 6123 #define MMVM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 6124 #define MMVM_INVALIDATE_ENG13_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 6125 #define MMVM_INVALIDATE_ENG13_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 6126 #define MMVM_INVALIDATE_ENG13_REQ__LOG_REQUEST__SHIFT 0x19 6127 #define MMVM_INVALIDATE_ENG13_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a 6128 #define MMVM_INVALIDATE_ENG13_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL 6129 #define MMVM_INVALIDATE_ENG13_REQ__FLUSH_TYPE_MASK 0x00070000L 6130 #define MMVM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L 6131 #define MMVM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L 6132 #define MMVM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L 6133 #define MMVM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L 6134 #define MMVM_INVALIDATE_ENG13_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L 6135 #define MMVM_INVALIDATE_ENG13_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L 6136 #define MMVM_INVALIDATE_ENG13_REQ__LOG_REQUEST_MASK 0x02000000L 6137 #define MMVM_INVALIDATE_ENG13_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L 6138 //MMVM_INVALIDATE_ENG14_REQ 6139 #define MMVM_INVALIDATE_ENG14_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 6140 #define MMVM_INVALIDATE_ENG14_REQ__FLUSH_TYPE__SHIFT 0x10 6141 #define MMVM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 6142 #define MMVM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 6143 #define MMVM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 6144 #define MMVM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 6145 #define MMVM_INVALIDATE_ENG14_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 6146 #define MMVM_INVALIDATE_ENG14_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 6147 #define MMVM_INVALIDATE_ENG14_REQ__LOG_REQUEST__SHIFT 0x19 6148 #define MMVM_INVALIDATE_ENG14_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a 6149 #define MMVM_INVALIDATE_ENG14_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL 6150 #define MMVM_INVALIDATE_ENG14_REQ__FLUSH_TYPE_MASK 0x00070000L 6151 #define MMVM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L 6152 #define MMVM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L 6153 #define MMVM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L 6154 #define MMVM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L 6155 #define MMVM_INVALIDATE_ENG14_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L 6156 #define MMVM_INVALIDATE_ENG14_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L 6157 #define MMVM_INVALIDATE_ENG14_REQ__LOG_REQUEST_MASK 0x02000000L 6158 #define MMVM_INVALIDATE_ENG14_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L 6159 //MMVM_INVALIDATE_ENG15_REQ 6160 #define MMVM_INVALIDATE_ENG15_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 6161 #define MMVM_INVALIDATE_ENG15_REQ__FLUSH_TYPE__SHIFT 0x10 6162 #define MMVM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 6163 #define MMVM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 6164 #define MMVM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 6165 #define MMVM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 6166 #define MMVM_INVALIDATE_ENG15_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 6167 #define MMVM_INVALIDATE_ENG15_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 6168 #define MMVM_INVALIDATE_ENG15_REQ__LOG_REQUEST__SHIFT 0x19 6169 #define MMVM_INVALIDATE_ENG15_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a 6170 #define MMVM_INVALIDATE_ENG15_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL 6171 #define MMVM_INVALIDATE_ENG15_REQ__FLUSH_TYPE_MASK 0x00070000L 6172 #define MMVM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L 6173 #define MMVM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L 6174 #define MMVM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L 6175 #define MMVM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L 6176 #define MMVM_INVALIDATE_ENG15_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L 6177 #define MMVM_INVALIDATE_ENG15_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L 6178 #define MMVM_INVALIDATE_ENG15_REQ__LOG_REQUEST_MASK 0x02000000L 6179 #define MMVM_INVALIDATE_ENG15_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L 6180 //MMVM_INVALIDATE_ENG16_REQ 6181 #define MMVM_INVALIDATE_ENG16_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 6182 #define MMVM_INVALIDATE_ENG16_REQ__FLUSH_TYPE__SHIFT 0x10 6183 #define MMVM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 6184 #define MMVM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 6185 #define MMVM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 6186 #define MMVM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 6187 #define MMVM_INVALIDATE_ENG16_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 6188 #define MMVM_INVALIDATE_ENG16_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 6189 #define MMVM_INVALIDATE_ENG16_REQ__LOG_REQUEST__SHIFT 0x19 6190 #define MMVM_INVALIDATE_ENG16_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a 6191 #define MMVM_INVALIDATE_ENG16_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL 6192 #define MMVM_INVALIDATE_ENG16_REQ__FLUSH_TYPE_MASK 0x00070000L 6193 #define MMVM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L 6194 #define MMVM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L 6195 #define MMVM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L 6196 #define MMVM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L 6197 #define MMVM_INVALIDATE_ENG16_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L 6198 #define MMVM_INVALIDATE_ENG16_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L 6199 #define MMVM_INVALIDATE_ENG16_REQ__LOG_REQUEST_MASK 0x02000000L 6200 #define MMVM_INVALIDATE_ENG16_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L 6201 //MMVM_INVALIDATE_ENG17_REQ 6202 #define MMVM_INVALIDATE_ENG17_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 6203 #define MMVM_INVALIDATE_ENG17_REQ__FLUSH_TYPE__SHIFT 0x10 6204 #define MMVM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 6205 #define MMVM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 6206 #define MMVM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 6207 #define MMVM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 6208 #define MMVM_INVALIDATE_ENG17_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 6209 #define MMVM_INVALIDATE_ENG17_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 6210 #define MMVM_INVALIDATE_ENG17_REQ__LOG_REQUEST__SHIFT 0x19 6211 #define MMVM_INVALIDATE_ENG17_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a 6212 #define MMVM_INVALIDATE_ENG17_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL 6213 #define MMVM_INVALIDATE_ENG17_REQ__FLUSH_TYPE_MASK 0x00070000L 6214 #define MMVM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L 6215 #define MMVM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L 6216 #define MMVM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L 6217 #define MMVM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L 6218 #define MMVM_INVALIDATE_ENG17_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L 6219 #define MMVM_INVALIDATE_ENG17_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L 6220 #define MMVM_INVALIDATE_ENG17_REQ__LOG_REQUEST_MASK 0x02000000L 6221 #define MMVM_INVALIDATE_ENG17_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L 6222 //MMVM_INVALIDATE_ENG0_ACK 6223 #define MMVM_INVALIDATE_ENG0_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 6224 #define MMVM_INVALIDATE_ENG0_ACK__SEMAPHORE__SHIFT 0x10 6225 #define MMVM_INVALIDATE_ENG0_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL 6226 #define MMVM_INVALIDATE_ENG0_ACK__SEMAPHORE_MASK 0x00010000L 6227 //MMVM_INVALIDATE_ENG1_ACK 6228 #define MMVM_INVALIDATE_ENG1_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 6229 #define MMVM_INVALIDATE_ENG1_ACK__SEMAPHORE__SHIFT 0x10 6230 #define MMVM_INVALIDATE_ENG1_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL 6231 #define MMVM_INVALIDATE_ENG1_ACK__SEMAPHORE_MASK 0x00010000L 6232 //MMVM_INVALIDATE_ENG2_ACK 6233 #define MMVM_INVALIDATE_ENG2_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 6234 #define MMVM_INVALIDATE_ENG2_ACK__SEMAPHORE__SHIFT 0x10 6235 #define MMVM_INVALIDATE_ENG2_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL 6236 #define MMVM_INVALIDATE_ENG2_ACK__SEMAPHORE_MASK 0x00010000L 6237 //MMVM_INVALIDATE_ENG3_ACK 6238 #define MMVM_INVALIDATE_ENG3_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 6239 #define MMVM_INVALIDATE_ENG3_ACK__SEMAPHORE__SHIFT 0x10 6240 #define MMVM_INVALIDATE_ENG3_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL 6241 #define MMVM_INVALIDATE_ENG3_ACK__SEMAPHORE_MASK 0x00010000L 6242 //MMVM_INVALIDATE_ENG4_ACK 6243 #define MMVM_INVALIDATE_ENG4_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 6244 #define MMVM_INVALIDATE_ENG4_ACK__SEMAPHORE__SHIFT 0x10 6245 #define MMVM_INVALIDATE_ENG4_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL 6246 #define MMVM_INVALIDATE_ENG4_ACK__SEMAPHORE_MASK 0x00010000L 6247 //MMVM_INVALIDATE_ENG5_ACK 6248 #define MMVM_INVALIDATE_ENG5_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 6249 #define MMVM_INVALIDATE_ENG5_ACK__SEMAPHORE__SHIFT 0x10 6250 #define MMVM_INVALIDATE_ENG5_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL 6251 #define MMVM_INVALIDATE_ENG5_ACK__SEMAPHORE_MASK 0x00010000L 6252 //MMVM_INVALIDATE_ENG6_ACK 6253 #define MMVM_INVALIDATE_ENG6_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 6254 #define MMVM_INVALIDATE_ENG6_ACK__SEMAPHORE__SHIFT 0x10 6255 #define MMVM_INVALIDATE_ENG6_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL 6256 #define MMVM_INVALIDATE_ENG6_ACK__SEMAPHORE_MASK 0x00010000L 6257 //MMVM_INVALIDATE_ENG7_ACK 6258 #define MMVM_INVALIDATE_ENG7_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 6259 #define MMVM_INVALIDATE_ENG7_ACK__SEMAPHORE__SHIFT 0x10 6260 #define MMVM_INVALIDATE_ENG7_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL 6261 #define MMVM_INVALIDATE_ENG7_ACK__SEMAPHORE_MASK 0x00010000L 6262 //MMVM_INVALIDATE_ENG8_ACK 6263 #define MMVM_INVALIDATE_ENG8_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 6264 #define MMVM_INVALIDATE_ENG8_ACK__SEMAPHORE__SHIFT 0x10 6265 #define MMVM_INVALIDATE_ENG8_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL 6266 #define MMVM_INVALIDATE_ENG8_ACK__SEMAPHORE_MASK 0x00010000L 6267 //MMVM_INVALIDATE_ENG9_ACK 6268 #define MMVM_INVALIDATE_ENG9_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 6269 #define MMVM_INVALIDATE_ENG9_ACK__SEMAPHORE__SHIFT 0x10 6270 #define MMVM_INVALIDATE_ENG9_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL 6271 #define MMVM_INVALIDATE_ENG9_ACK__SEMAPHORE_MASK 0x00010000L 6272 //MMVM_INVALIDATE_ENG10_ACK 6273 #define MMVM_INVALIDATE_ENG10_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 6274 #define MMVM_INVALIDATE_ENG10_ACK__SEMAPHORE__SHIFT 0x10 6275 #define MMVM_INVALIDATE_ENG10_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL 6276 #define MMVM_INVALIDATE_ENG10_ACK__SEMAPHORE_MASK 0x00010000L 6277 //MMVM_INVALIDATE_ENG11_ACK 6278 #define MMVM_INVALIDATE_ENG11_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 6279 #define MMVM_INVALIDATE_ENG11_ACK__SEMAPHORE__SHIFT 0x10 6280 #define MMVM_INVALIDATE_ENG11_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL 6281 #define MMVM_INVALIDATE_ENG11_ACK__SEMAPHORE_MASK 0x00010000L 6282 //MMVM_INVALIDATE_ENG12_ACK 6283 #define MMVM_INVALIDATE_ENG12_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 6284 #define MMVM_INVALIDATE_ENG12_ACK__SEMAPHORE__SHIFT 0x10 6285 #define MMVM_INVALIDATE_ENG12_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL 6286 #define MMVM_INVALIDATE_ENG12_ACK__SEMAPHORE_MASK 0x00010000L 6287 //MMVM_INVALIDATE_ENG13_ACK 6288 #define MMVM_INVALIDATE_ENG13_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 6289 #define MMVM_INVALIDATE_ENG13_ACK__SEMAPHORE__SHIFT 0x10 6290 #define MMVM_INVALIDATE_ENG13_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL 6291 #define MMVM_INVALIDATE_ENG13_ACK__SEMAPHORE_MASK 0x00010000L 6292 //MMVM_INVALIDATE_ENG14_ACK 6293 #define MMVM_INVALIDATE_ENG14_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 6294 #define MMVM_INVALIDATE_ENG14_ACK__SEMAPHORE__SHIFT 0x10 6295 #define MMVM_INVALIDATE_ENG14_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL 6296 #define MMVM_INVALIDATE_ENG14_ACK__SEMAPHORE_MASK 0x00010000L 6297 //MMVM_INVALIDATE_ENG15_ACK 6298 #define MMVM_INVALIDATE_ENG15_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 6299 #define MMVM_INVALIDATE_ENG15_ACK__SEMAPHORE__SHIFT 0x10 6300 #define MMVM_INVALIDATE_ENG15_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL 6301 #define MMVM_INVALIDATE_ENG15_ACK__SEMAPHORE_MASK 0x00010000L 6302 //MMVM_INVALIDATE_ENG16_ACK 6303 #define MMVM_INVALIDATE_ENG16_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 6304 #define MMVM_INVALIDATE_ENG16_ACK__SEMAPHORE__SHIFT 0x10 6305 #define MMVM_INVALIDATE_ENG16_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL 6306 #define MMVM_INVALIDATE_ENG16_ACK__SEMAPHORE_MASK 0x00010000L 6307 //MMVM_INVALIDATE_ENG17_ACK 6308 #define MMVM_INVALIDATE_ENG17_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 6309 #define MMVM_INVALIDATE_ENG17_ACK__SEMAPHORE__SHIFT 0x10 6310 #define MMVM_INVALIDATE_ENG17_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL 6311 #define MMVM_INVALIDATE_ENG17_ACK__SEMAPHORE_MASK 0x00010000L 6312 //MMVM_INVALIDATE_ENG0_ADDR_RANGE_LO32 6313 #define MMVM_INVALIDATE_ENG0_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 6314 #define MMVM_INVALIDATE_ENG0_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 6315 #define MMVM_INVALIDATE_ENG0_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L 6316 #define MMVM_INVALIDATE_ENG0_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL 6317 //MMVM_INVALIDATE_ENG0_ADDR_RANGE_HI32 6318 #define MMVM_INVALIDATE_ENG0_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 6319 #define MMVM_INVALIDATE_ENG0_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL 6320 //MMVM_INVALIDATE_ENG1_ADDR_RANGE_LO32 6321 #define MMVM_INVALIDATE_ENG1_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 6322 #define MMVM_INVALIDATE_ENG1_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 6323 #define MMVM_INVALIDATE_ENG1_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L 6324 #define MMVM_INVALIDATE_ENG1_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL 6325 //MMVM_INVALIDATE_ENG1_ADDR_RANGE_HI32 6326 #define MMVM_INVALIDATE_ENG1_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 6327 #define MMVM_INVALIDATE_ENG1_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL 6328 //MMVM_INVALIDATE_ENG2_ADDR_RANGE_LO32 6329 #define MMVM_INVALIDATE_ENG2_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 6330 #define MMVM_INVALIDATE_ENG2_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 6331 #define MMVM_INVALIDATE_ENG2_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L 6332 #define MMVM_INVALIDATE_ENG2_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL 6333 //MMVM_INVALIDATE_ENG2_ADDR_RANGE_HI32 6334 #define MMVM_INVALIDATE_ENG2_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 6335 #define MMVM_INVALIDATE_ENG2_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL 6336 //MMVM_INVALIDATE_ENG3_ADDR_RANGE_LO32 6337 #define MMVM_INVALIDATE_ENG3_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 6338 #define MMVM_INVALIDATE_ENG3_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 6339 #define MMVM_INVALIDATE_ENG3_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L 6340 #define MMVM_INVALIDATE_ENG3_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL 6341 //MMVM_INVALIDATE_ENG3_ADDR_RANGE_HI32 6342 #define MMVM_INVALIDATE_ENG3_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 6343 #define MMVM_INVALIDATE_ENG3_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL 6344 //MMVM_INVALIDATE_ENG4_ADDR_RANGE_LO32 6345 #define MMVM_INVALIDATE_ENG4_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 6346 #define MMVM_INVALIDATE_ENG4_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 6347 #define MMVM_INVALIDATE_ENG4_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L 6348 #define MMVM_INVALIDATE_ENG4_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL 6349 //MMVM_INVALIDATE_ENG4_ADDR_RANGE_HI32 6350 #define MMVM_INVALIDATE_ENG4_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 6351 #define MMVM_INVALIDATE_ENG4_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL 6352 //MMVM_INVALIDATE_ENG5_ADDR_RANGE_LO32 6353 #define MMVM_INVALIDATE_ENG5_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 6354 #define MMVM_INVALIDATE_ENG5_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 6355 #define MMVM_INVALIDATE_ENG5_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L 6356 #define MMVM_INVALIDATE_ENG5_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL 6357 //MMVM_INVALIDATE_ENG5_ADDR_RANGE_HI32 6358 #define MMVM_INVALIDATE_ENG5_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 6359 #define MMVM_INVALIDATE_ENG5_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL 6360 //MMVM_INVALIDATE_ENG6_ADDR_RANGE_LO32 6361 #define MMVM_INVALIDATE_ENG6_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 6362 #define MMVM_INVALIDATE_ENG6_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 6363 #define MMVM_INVALIDATE_ENG6_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L 6364 #define MMVM_INVALIDATE_ENG6_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL 6365 //MMVM_INVALIDATE_ENG6_ADDR_RANGE_HI32 6366 #define MMVM_INVALIDATE_ENG6_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 6367 #define MMVM_INVALIDATE_ENG6_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL 6368 //MMVM_INVALIDATE_ENG7_ADDR_RANGE_LO32 6369 #define MMVM_INVALIDATE_ENG7_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 6370 #define MMVM_INVALIDATE_ENG7_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 6371 #define MMVM_INVALIDATE_ENG7_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L 6372 #define MMVM_INVALIDATE_ENG7_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL 6373 //MMVM_INVALIDATE_ENG7_ADDR_RANGE_HI32 6374 #define MMVM_INVALIDATE_ENG7_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 6375 #define MMVM_INVALIDATE_ENG7_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL 6376 //MMVM_INVALIDATE_ENG8_ADDR_RANGE_LO32 6377 #define MMVM_INVALIDATE_ENG8_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 6378 #define MMVM_INVALIDATE_ENG8_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 6379 #define MMVM_INVALIDATE_ENG8_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L 6380 #define MMVM_INVALIDATE_ENG8_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL 6381 //MMVM_INVALIDATE_ENG8_ADDR_RANGE_HI32 6382 #define MMVM_INVALIDATE_ENG8_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 6383 #define MMVM_INVALIDATE_ENG8_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL 6384 //MMVM_INVALIDATE_ENG9_ADDR_RANGE_LO32 6385 #define MMVM_INVALIDATE_ENG9_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 6386 #define MMVM_INVALIDATE_ENG9_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 6387 #define MMVM_INVALIDATE_ENG9_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L 6388 #define MMVM_INVALIDATE_ENG9_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL 6389 //MMVM_INVALIDATE_ENG9_ADDR_RANGE_HI32 6390 #define MMVM_INVALIDATE_ENG9_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 6391 #define MMVM_INVALIDATE_ENG9_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL 6392 //MMVM_INVALIDATE_ENG10_ADDR_RANGE_LO32 6393 #define MMVM_INVALIDATE_ENG10_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 6394 #define MMVM_INVALIDATE_ENG10_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 6395 #define MMVM_INVALIDATE_ENG10_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L 6396 #define MMVM_INVALIDATE_ENG10_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL 6397 //MMVM_INVALIDATE_ENG10_ADDR_RANGE_HI32 6398 #define MMVM_INVALIDATE_ENG10_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 6399 #define MMVM_INVALIDATE_ENG10_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL 6400 //MMVM_INVALIDATE_ENG11_ADDR_RANGE_LO32 6401 #define MMVM_INVALIDATE_ENG11_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 6402 #define MMVM_INVALIDATE_ENG11_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 6403 #define MMVM_INVALIDATE_ENG11_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L 6404 #define MMVM_INVALIDATE_ENG11_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL 6405 //MMVM_INVALIDATE_ENG11_ADDR_RANGE_HI32 6406 #define MMVM_INVALIDATE_ENG11_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 6407 #define MMVM_INVALIDATE_ENG11_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL 6408 //MMVM_INVALIDATE_ENG12_ADDR_RANGE_LO32 6409 #define MMVM_INVALIDATE_ENG12_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 6410 #define MMVM_INVALIDATE_ENG12_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 6411 #define MMVM_INVALIDATE_ENG12_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L 6412 #define MMVM_INVALIDATE_ENG12_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL 6413 //MMVM_INVALIDATE_ENG12_ADDR_RANGE_HI32 6414 #define MMVM_INVALIDATE_ENG12_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 6415 #define MMVM_INVALIDATE_ENG12_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL 6416 //MMVM_INVALIDATE_ENG13_ADDR_RANGE_LO32 6417 #define MMVM_INVALIDATE_ENG13_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 6418 #define MMVM_INVALIDATE_ENG13_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 6419 #define MMVM_INVALIDATE_ENG13_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L 6420 #define MMVM_INVALIDATE_ENG13_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL 6421 //MMVM_INVALIDATE_ENG13_ADDR_RANGE_HI32 6422 #define MMVM_INVALIDATE_ENG13_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 6423 #define MMVM_INVALIDATE_ENG13_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL 6424 //MMVM_INVALIDATE_ENG14_ADDR_RANGE_LO32 6425 #define MMVM_INVALIDATE_ENG14_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 6426 #define MMVM_INVALIDATE_ENG14_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 6427 #define MMVM_INVALIDATE_ENG14_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L 6428 #define MMVM_INVALIDATE_ENG14_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL 6429 //MMVM_INVALIDATE_ENG14_ADDR_RANGE_HI32 6430 #define MMVM_INVALIDATE_ENG14_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 6431 #define MMVM_INVALIDATE_ENG14_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL 6432 //MMVM_INVALIDATE_ENG15_ADDR_RANGE_LO32 6433 #define MMVM_INVALIDATE_ENG15_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 6434 #define MMVM_INVALIDATE_ENG15_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 6435 #define MMVM_INVALIDATE_ENG15_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L 6436 #define MMVM_INVALIDATE_ENG15_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL 6437 //MMVM_INVALIDATE_ENG15_ADDR_RANGE_HI32 6438 #define MMVM_INVALIDATE_ENG15_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 6439 #define MMVM_INVALIDATE_ENG15_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL 6440 //MMVM_INVALIDATE_ENG16_ADDR_RANGE_LO32 6441 #define MMVM_INVALIDATE_ENG16_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 6442 #define MMVM_INVALIDATE_ENG16_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 6443 #define MMVM_INVALIDATE_ENG16_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L 6444 #define MMVM_INVALIDATE_ENG16_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL 6445 //MMVM_INVALIDATE_ENG16_ADDR_RANGE_HI32 6446 #define MMVM_INVALIDATE_ENG16_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 6447 #define MMVM_INVALIDATE_ENG16_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL 6448 //MMVM_INVALIDATE_ENG17_ADDR_RANGE_LO32 6449 #define MMVM_INVALIDATE_ENG17_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 6450 #define MMVM_INVALIDATE_ENG17_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 6451 #define MMVM_INVALIDATE_ENG17_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L 6452 #define MMVM_INVALIDATE_ENG17_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL 6453 //MMVM_INVALIDATE_ENG17_ADDR_RANGE_HI32 6454 #define MMVM_INVALIDATE_ENG17_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 6455 #define MMVM_INVALIDATE_ENG17_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL 6456 //MMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32 6457 #define MMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 6458 #define MMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL 6459 //MMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32 6460 #define MMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 6461 #define MMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL 6462 //MMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32 6463 #define MMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 6464 #define MMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL 6465 //MMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32 6466 #define MMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 6467 #define MMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL 6468 //MMVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32 6469 #define MMVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 6470 #define MMVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL 6471 //MMVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32 6472 #define MMVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 6473 #define MMVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL 6474 //MMVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32 6475 #define MMVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 6476 #define MMVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL 6477 //MMVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32 6478 #define MMVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 6479 #define MMVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL 6480 //MMVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32 6481 #define MMVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 6482 #define MMVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL 6483 //MMVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32 6484 #define MMVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 6485 #define MMVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL 6486 //MMVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32 6487 #define MMVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 6488 #define MMVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL 6489 //MMVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32 6490 #define MMVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 6491 #define MMVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL 6492 //MMVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32 6493 #define MMVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 6494 #define MMVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL 6495 //MMVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32 6496 #define MMVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 6497 #define MMVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL 6498 //MMVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32 6499 #define MMVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 6500 #define MMVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL 6501 //MMVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32 6502 #define MMVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 6503 #define MMVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL 6504 //MMVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32 6505 #define MMVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 6506 #define MMVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL 6507 //MMVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32 6508 #define MMVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 6509 #define MMVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL 6510 //MMVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32 6511 #define MMVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 6512 #define MMVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL 6513 //MMVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32 6514 #define MMVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 6515 #define MMVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL 6516 //MMVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32 6517 #define MMVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 6518 #define MMVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL 6519 //MMVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32 6520 #define MMVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 6521 #define MMVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL 6522 //MMVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32 6523 #define MMVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 6524 #define MMVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL 6525 //MMVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32 6526 #define MMVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 6527 #define MMVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL 6528 //MMVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32 6529 #define MMVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 6530 #define MMVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL 6531 //MMVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32 6532 #define MMVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 6533 #define MMVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL 6534 //MMVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32 6535 #define MMVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 6536 #define MMVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL 6537 //MMVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32 6538 #define MMVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 6539 #define MMVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL 6540 //MMVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32 6541 #define MMVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 6542 #define MMVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL 6543 //MMVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32 6544 #define MMVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 6545 #define MMVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL 6546 //MMVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32 6547 #define MMVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 6548 #define MMVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL 6549 //MMVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32 6550 #define MMVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 6551 #define MMVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL 6552 //MMVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32 6553 #define MMVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 6554 #define MMVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 6555 //MMVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32 6556 #define MMVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 6557 #define MMVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 6558 //MMVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32 6559 #define MMVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 6560 #define MMVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 6561 //MMVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32 6562 #define MMVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 6563 #define MMVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 6564 //MMVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32 6565 #define MMVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 6566 #define MMVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 6567 //MMVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32 6568 #define MMVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 6569 #define MMVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 6570 //MMVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32 6571 #define MMVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 6572 #define MMVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 6573 //MMVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32 6574 #define MMVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 6575 #define MMVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 6576 //MMVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32 6577 #define MMVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 6578 #define MMVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 6579 //MMVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32 6580 #define MMVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 6581 #define MMVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 6582 //MMVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32 6583 #define MMVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 6584 #define MMVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 6585 //MMVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32 6586 #define MMVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 6587 #define MMVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 6588 //MMVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32 6589 #define MMVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 6590 #define MMVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 6591 //MMVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32 6592 #define MMVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 6593 #define MMVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 6594 //MMVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32 6595 #define MMVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 6596 #define MMVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 6597 //MMVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32 6598 #define MMVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 6599 #define MMVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 6600 //MMVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32 6601 #define MMVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 6602 #define MMVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 6603 //MMVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32 6604 #define MMVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 6605 #define MMVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 6606 //MMVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32 6607 #define MMVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 6608 #define MMVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 6609 //MMVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32 6610 #define MMVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 6611 #define MMVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 6612 //MMVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32 6613 #define MMVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 6614 #define MMVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 6615 //MMVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32 6616 #define MMVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 6617 #define MMVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 6618 //MMVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32 6619 #define MMVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 6620 #define MMVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 6621 //MMVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32 6622 #define MMVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 6623 #define MMVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 6624 //MMVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32 6625 #define MMVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 6626 #define MMVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 6627 //MMVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32 6628 #define MMVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 6629 #define MMVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 6630 //MMVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32 6631 #define MMVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 6632 #define MMVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 6633 //MMVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32 6634 #define MMVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 6635 #define MMVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 6636 //MMVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32 6637 #define MMVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 6638 #define MMVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 6639 //MMVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32 6640 #define MMVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 6641 #define MMVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 6642 //MMVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32 6643 #define MMVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 6644 #define MMVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 6645 //MMVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32 6646 #define MMVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 6647 #define MMVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 6648 //MMVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32 6649 #define MMVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 6650 #define MMVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 6651 //MMVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32 6652 #define MMVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 6653 #define MMVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 6654 //MMVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32 6655 #define MMVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 6656 #define MMVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 6657 //MMVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32 6658 #define MMVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 6659 #define MMVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 6660 //MMVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32 6661 #define MMVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 6662 #define MMVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 6663 //MMVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32 6664 #define MMVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 6665 #define MMVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 6666 //MMVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32 6667 #define MMVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 6668 #define MMVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 6669 //MMVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32 6670 #define MMVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 6671 #define MMVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 6672 //MMVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32 6673 #define MMVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 6674 #define MMVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 6675 //MMVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32 6676 #define MMVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 6677 #define MMVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 6678 //MMVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32 6679 #define MMVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 6680 #define MMVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 6681 //MMVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32 6682 #define MMVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 6683 #define MMVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 6684 //MMVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32 6685 #define MMVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 6686 #define MMVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 6687 //MMVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32 6688 #define MMVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 6689 #define MMVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 6690 //MMVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32 6691 #define MMVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 6692 #define MMVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 6693 //MMVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32 6694 #define MMVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 6695 #define MMVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 6696 //MMVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32 6697 #define MMVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 6698 #define MMVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 6699 //MMVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32 6700 #define MMVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 6701 #define MMVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 6702 //MMVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32 6703 #define MMVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 6704 #define MMVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 6705 //MMVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32 6706 #define MMVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 6707 #define MMVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 6708 //MMVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32 6709 #define MMVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 6710 #define MMVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 6711 //MMVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32 6712 #define MMVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 6713 #define MMVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 6714 //MMVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32 6715 #define MMVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 6716 #define MMVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 6717 //MMVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32 6718 #define MMVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 6719 #define MMVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 6720 //MMVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32 6721 #define MMVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 6722 #define MMVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 6723 //MMVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32 6724 #define MMVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 6725 #define MMVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 6726 //MMVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32 6727 #define MMVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 6728 #define MMVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 6729 //MMVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32 6730 #define MMVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 6731 #define MMVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 6732 //MMVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32 6733 #define MMVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 6734 #define MMVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 6735 //MMVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32 6736 #define MMVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 6737 #define MMVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 6738 //MMVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32 6739 #define MMVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 6740 #define MMVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 6741 //MMVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32 6742 #define MMVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 6743 #define MMVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 6744 //MMVM_L2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 6745 #define MMVM_L2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0 6746 #define MMVM_L2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0x5 6747 #define MMVM_L2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa 6748 #define MMVM_L2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL 6749 #define MMVM_L2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000003E0L 6750 #define MMVM_L2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK 0x0000FC00L 6751 //MMVM_L2_CONTEXT0_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 6752 #define MMVM_L2_CONTEXT0_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0 6753 #define MMVM_L2_CONTEXT0_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0x5 6754 #define MMVM_L2_CONTEXT0_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa 6755 #define MMVM_L2_CONTEXT0_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL 6756 #define MMVM_L2_CONTEXT0_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000003E0L 6757 #define MMVM_L2_CONTEXT0_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK 0x0000FC00L 6758 //MMVM_L2_CONTEXT1_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 6759 #define MMVM_L2_CONTEXT1_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0 6760 #define MMVM_L2_CONTEXT1_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0x5 6761 #define MMVM_L2_CONTEXT1_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa 6762 #define MMVM_L2_CONTEXT1_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL 6763 #define MMVM_L2_CONTEXT1_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000003E0L 6764 #define MMVM_L2_CONTEXT1_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK 0x0000FC00L 6765 //MMVM_L2_CONTEXT2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 6766 #define MMVM_L2_CONTEXT2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0 6767 #define MMVM_L2_CONTEXT2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0x5 6768 #define MMVM_L2_CONTEXT2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa 6769 #define MMVM_L2_CONTEXT2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL 6770 #define MMVM_L2_CONTEXT2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000003E0L 6771 #define MMVM_L2_CONTEXT2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK 0x0000FC00L 6772 //MMVM_L2_CONTEXT3_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 6773 #define MMVM_L2_CONTEXT3_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0 6774 #define MMVM_L2_CONTEXT3_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0x5 6775 #define MMVM_L2_CONTEXT3_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa 6776 #define MMVM_L2_CONTEXT3_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL 6777 #define MMVM_L2_CONTEXT3_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000003E0L 6778 #define MMVM_L2_CONTEXT3_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK 0x0000FC00L 6779 //MMVM_L2_CONTEXT4_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 6780 #define MMVM_L2_CONTEXT4_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0 6781 #define MMVM_L2_CONTEXT4_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0x5 6782 #define MMVM_L2_CONTEXT4_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa 6783 #define MMVM_L2_CONTEXT4_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL 6784 #define MMVM_L2_CONTEXT4_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000003E0L 6785 #define MMVM_L2_CONTEXT4_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK 0x0000FC00L 6786 //MMVM_L2_CONTEXT5_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 6787 #define MMVM_L2_CONTEXT5_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0 6788 #define MMVM_L2_CONTEXT5_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0x5 6789 #define MMVM_L2_CONTEXT5_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa 6790 #define MMVM_L2_CONTEXT5_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL 6791 #define MMVM_L2_CONTEXT5_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000003E0L 6792 #define MMVM_L2_CONTEXT5_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK 0x0000FC00L 6793 //MMVM_L2_CONTEXT6_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 6794 #define MMVM_L2_CONTEXT6_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0 6795 #define MMVM_L2_CONTEXT6_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0x5 6796 #define MMVM_L2_CONTEXT6_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa 6797 #define MMVM_L2_CONTEXT6_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL 6798 #define MMVM_L2_CONTEXT6_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000003E0L 6799 #define MMVM_L2_CONTEXT6_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK 0x0000FC00L 6800 //MMVM_L2_CONTEXT7_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 6801 #define MMVM_L2_CONTEXT7_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0 6802 #define MMVM_L2_CONTEXT7_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0x5 6803 #define MMVM_L2_CONTEXT7_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa 6804 #define MMVM_L2_CONTEXT7_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL 6805 #define MMVM_L2_CONTEXT7_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000003E0L 6806 #define MMVM_L2_CONTEXT7_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK 0x0000FC00L 6807 //MMVM_L2_CONTEXT8_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 6808 #define MMVM_L2_CONTEXT8_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0 6809 #define MMVM_L2_CONTEXT8_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0x5 6810 #define MMVM_L2_CONTEXT8_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa 6811 #define MMVM_L2_CONTEXT8_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL 6812 #define MMVM_L2_CONTEXT8_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000003E0L 6813 #define MMVM_L2_CONTEXT8_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK 0x0000FC00L 6814 //MMVM_L2_CONTEXT9_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 6815 #define MMVM_L2_CONTEXT9_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0 6816 #define MMVM_L2_CONTEXT9_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0x5 6817 #define MMVM_L2_CONTEXT9_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa 6818 #define MMVM_L2_CONTEXT9_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL 6819 #define MMVM_L2_CONTEXT9_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000003E0L 6820 #define MMVM_L2_CONTEXT9_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK 0x0000FC00L 6821 //MMVM_L2_CONTEXT10_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 6822 #define MMVM_L2_CONTEXT10_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0 6823 #define MMVM_L2_CONTEXT10_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0x5 6824 #define MMVM_L2_CONTEXT10_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa 6825 #define MMVM_L2_CONTEXT10_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL 6826 #define MMVM_L2_CONTEXT10_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000003E0L 6827 #define MMVM_L2_CONTEXT10_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK 0x0000FC00L 6828 //MMVM_L2_CONTEXT11_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 6829 #define MMVM_L2_CONTEXT11_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0 6830 #define MMVM_L2_CONTEXT11_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0x5 6831 #define MMVM_L2_CONTEXT11_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa 6832 #define MMVM_L2_CONTEXT11_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL 6833 #define MMVM_L2_CONTEXT11_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000003E0L 6834 #define MMVM_L2_CONTEXT11_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK 0x0000FC00L 6835 //MMVM_L2_CONTEXT12_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 6836 #define MMVM_L2_CONTEXT12_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0 6837 #define MMVM_L2_CONTEXT12_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0x5 6838 #define MMVM_L2_CONTEXT12_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa 6839 #define MMVM_L2_CONTEXT12_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL 6840 #define MMVM_L2_CONTEXT12_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000003E0L 6841 #define MMVM_L2_CONTEXT12_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK 0x0000FC00L 6842 //MMVM_L2_CONTEXT13_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 6843 #define MMVM_L2_CONTEXT13_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0 6844 #define MMVM_L2_CONTEXT13_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0x5 6845 #define MMVM_L2_CONTEXT13_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa 6846 #define MMVM_L2_CONTEXT13_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL 6847 #define MMVM_L2_CONTEXT13_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000003E0L 6848 #define MMVM_L2_CONTEXT13_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK 0x0000FC00L 6849 //MMVM_L2_CONTEXT14_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 6850 #define MMVM_L2_CONTEXT14_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0 6851 #define MMVM_L2_CONTEXT14_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0x5 6852 #define MMVM_L2_CONTEXT14_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa 6853 #define MMVM_L2_CONTEXT14_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL 6854 #define MMVM_L2_CONTEXT14_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000003E0L 6855 #define MMVM_L2_CONTEXT14_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK 0x0000FC00L 6856 //MMVM_L2_CONTEXT15_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 6857 #define MMVM_L2_CONTEXT15_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0 6858 #define MMVM_L2_CONTEXT15_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0x5 6859 #define MMVM_L2_CONTEXT15_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa 6860 #define MMVM_L2_CONTEXT15_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL 6861 #define MMVM_L2_CONTEXT15_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000003E0L 6862 #define MMVM_L2_CONTEXT15_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK 0x0000FC00L 6863 6864 6865 // addressBlock: mmhub_mmutcl2_mmvml2pldec 6866 //MMMC_VM_L2_PERFCOUNTER0_CFG 6867 #define MMMC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 6868 #define MMMC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 6869 #define MMMC_VM_L2_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 6870 #define MMMC_VM_L2_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c 6871 #define MMMC_VM_L2_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d 6872 #define MMMC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL 6873 #define MMMC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L 6874 #define MMMC_VM_L2_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L 6875 #define MMMC_VM_L2_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L 6876 #define MMMC_VM_L2_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L 6877 //MMMC_VM_L2_PERFCOUNTER1_CFG 6878 #define MMMC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 6879 #define MMMC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 6880 #define MMMC_VM_L2_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 6881 #define MMMC_VM_L2_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c 6882 #define MMMC_VM_L2_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d 6883 #define MMMC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL 6884 #define MMMC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L 6885 #define MMMC_VM_L2_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L 6886 #define MMMC_VM_L2_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L 6887 #define MMMC_VM_L2_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L 6888 //MMMC_VM_L2_PERFCOUNTER2_CFG 6889 #define MMMC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0 6890 #define MMMC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8 6891 #define MMMC_VM_L2_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18 6892 #define MMMC_VM_L2_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c 6893 #define MMMC_VM_L2_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d 6894 #define MMMC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL_MASK 0x000000FFL 6895 #define MMMC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0x0000FF00L 6896 #define MMMC_VM_L2_PERFCOUNTER2_CFG__PERF_MODE_MASK 0x0F000000L 6897 #define MMMC_VM_L2_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000L 6898 #define MMMC_VM_L2_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000L 6899 //MMMC_VM_L2_PERFCOUNTER3_CFG 6900 #define MMMC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL__SHIFT 0x0 6901 #define MMMC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT 0x8 6902 #define MMMC_VM_L2_PERFCOUNTER3_CFG__PERF_MODE__SHIFT 0x18 6903 #define MMMC_VM_L2_PERFCOUNTER3_CFG__ENABLE__SHIFT 0x1c 6904 #define MMMC_VM_L2_PERFCOUNTER3_CFG__CLEAR__SHIFT 0x1d 6905 #define MMMC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL_MASK 0x000000FFL 6906 #define MMMC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL_END_MASK 0x0000FF00L 6907 #define MMMC_VM_L2_PERFCOUNTER3_CFG__PERF_MODE_MASK 0x0F000000L 6908 #define MMMC_VM_L2_PERFCOUNTER3_CFG__ENABLE_MASK 0x10000000L 6909 #define MMMC_VM_L2_PERFCOUNTER3_CFG__CLEAR_MASK 0x20000000L 6910 //MMMC_VM_L2_PERFCOUNTER4_CFG 6911 #define MMMC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL__SHIFT 0x0 6912 #define MMMC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL_END__SHIFT 0x8 6913 #define MMMC_VM_L2_PERFCOUNTER4_CFG__PERF_MODE__SHIFT 0x18 6914 #define MMMC_VM_L2_PERFCOUNTER4_CFG__ENABLE__SHIFT 0x1c 6915 #define MMMC_VM_L2_PERFCOUNTER4_CFG__CLEAR__SHIFT 0x1d 6916 #define MMMC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL_MASK 0x000000FFL 6917 #define MMMC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL_END_MASK 0x0000FF00L 6918 #define MMMC_VM_L2_PERFCOUNTER4_CFG__PERF_MODE_MASK 0x0F000000L 6919 #define MMMC_VM_L2_PERFCOUNTER4_CFG__ENABLE_MASK 0x10000000L 6920 #define MMMC_VM_L2_PERFCOUNTER4_CFG__CLEAR_MASK 0x20000000L 6921 //MMMC_VM_L2_PERFCOUNTER5_CFG 6922 #define MMMC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL__SHIFT 0x0 6923 #define MMMC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL_END__SHIFT 0x8 6924 #define MMMC_VM_L2_PERFCOUNTER5_CFG__PERF_MODE__SHIFT 0x18 6925 #define MMMC_VM_L2_PERFCOUNTER5_CFG__ENABLE__SHIFT 0x1c 6926 #define MMMC_VM_L2_PERFCOUNTER5_CFG__CLEAR__SHIFT 0x1d 6927 #define MMMC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL_MASK 0x000000FFL 6928 #define MMMC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL_END_MASK 0x0000FF00L 6929 #define MMMC_VM_L2_PERFCOUNTER5_CFG__PERF_MODE_MASK 0x0F000000L 6930 #define MMMC_VM_L2_PERFCOUNTER5_CFG__ENABLE_MASK 0x10000000L 6931 #define MMMC_VM_L2_PERFCOUNTER5_CFG__CLEAR_MASK 0x20000000L 6932 //MMMC_VM_L2_PERFCOUNTER6_CFG 6933 #define MMMC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL__SHIFT 0x0 6934 #define MMMC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL_END__SHIFT 0x8 6935 #define MMMC_VM_L2_PERFCOUNTER6_CFG__PERF_MODE__SHIFT 0x18 6936 #define MMMC_VM_L2_PERFCOUNTER6_CFG__ENABLE__SHIFT 0x1c 6937 #define MMMC_VM_L2_PERFCOUNTER6_CFG__CLEAR__SHIFT 0x1d 6938 #define MMMC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL_MASK 0x000000FFL 6939 #define MMMC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL_END_MASK 0x0000FF00L 6940 #define MMMC_VM_L2_PERFCOUNTER6_CFG__PERF_MODE_MASK 0x0F000000L 6941 #define MMMC_VM_L2_PERFCOUNTER6_CFG__ENABLE_MASK 0x10000000L 6942 #define MMMC_VM_L2_PERFCOUNTER6_CFG__CLEAR_MASK 0x20000000L 6943 //MMMC_VM_L2_PERFCOUNTER7_CFG 6944 #define MMMC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL__SHIFT 0x0 6945 #define MMMC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL_END__SHIFT 0x8 6946 #define MMMC_VM_L2_PERFCOUNTER7_CFG__PERF_MODE__SHIFT 0x18 6947 #define MMMC_VM_L2_PERFCOUNTER7_CFG__ENABLE__SHIFT 0x1c 6948 #define MMMC_VM_L2_PERFCOUNTER7_CFG__CLEAR__SHIFT 0x1d 6949 #define MMMC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL_MASK 0x000000FFL 6950 #define MMMC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL_END_MASK 0x0000FF00L 6951 #define MMMC_VM_L2_PERFCOUNTER7_CFG__PERF_MODE_MASK 0x0F000000L 6952 #define MMMC_VM_L2_PERFCOUNTER7_CFG__ENABLE_MASK 0x10000000L 6953 #define MMMC_VM_L2_PERFCOUNTER7_CFG__CLEAR_MASK 0x20000000L 6954 //MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL 6955 #define MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 6956 #define MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 6957 #define MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 6958 #define MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 6959 #define MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 6960 #define MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a 6961 #define MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL 6962 #define MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L 6963 #define MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L 6964 #define MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L 6965 #define MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L 6966 #define MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L 6967 //MMUTCL2_PERFCOUNTER0_CFG 6968 #define MMUTCL2_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 6969 #define MMUTCL2_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 6970 #define MMUTCL2_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 6971 #define MMUTCL2_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c 6972 #define MMUTCL2_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d 6973 #define MMUTCL2_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL 6974 #define MMUTCL2_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L 6975 #define MMUTCL2_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L 6976 #define MMUTCL2_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L 6977 #define MMUTCL2_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L 6978 //MMUTCL2_PERFCOUNTER1_CFG 6979 #define MMUTCL2_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 6980 #define MMUTCL2_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 6981 #define MMUTCL2_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 6982 #define MMUTCL2_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c 6983 #define MMUTCL2_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d 6984 #define MMUTCL2_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL 6985 #define MMUTCL2_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L 6986 #define MMUTCL2_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L 6987 #define MMUTCL2_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L 6988 #define MMUTCL2_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L 6989 //MMUTCL2_PERFCOUNTER2_CFG 6990 #define MMUTCL2_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0 6991 #define MMUTCL2_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8 6992 #define MMUTCL2_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18 6993 #define MMUTCL2_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c 6994 #define MMUTCL2_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d 6995 #define MMUTCL2_PERFCOUNTER2_CFG__PERF_SEL_MASK 0x000000FFL 6996 #define MMUTCL2_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0x0000FF00L 6997 #define MMUTCL2_PERFCOUNTER2_CFG__PERF_MODE_MASK 0x0F000000L 6998 #define MMUTCL2_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000L 6999 #define MMUTCL2_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000L 7000 //MMUTCL2_PERFCOUNTER3_CFG 7001 #define MMUTCL2_PERFCOUNTER3_CFG__PERF_SEL__SHIFT 0x0 7002 #define MMUTCL2_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT 0x8 7003 #define MMUTCL2_PERFCOUNTER3_CFG__PERF_MODE__SHIFT 0x18 7004 #define MMUTCL2_PERFCOUNTER3_CFG__ENABLE__SHIFT 0x1c 7005 #define MMUTCL2_PERFCOUNTER3_CFG__CLEAR__SHIFT 0x1d 7006 #define MMUTCL2_PERFCOUNTER3_CFG__PERF_SEL_MASK 0x000000FFL 7007 #define MMUTCL2_PERFCOUNTER3_CFG__PERF_SEL_END_MASK 0x0000FF00L 7008 #define MMUTCL2_PERFCOUNTER3_CFG__PERF_MODE_MASK 0x0F000000L 7009 #define MMUTCL2_PERFCOUNTER3_CFG__ENABLE_MASK 0x10000000L 7010 #define MMUTCL2_PERFCOUNTER3_CFG__CLEAR_MASK 0x20000000L 7011 //MMUTCL2_PERFCOUNTER_RSLT_CNTL 7012 #define MMUTCL2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 7013 #define MMUTCL2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 7014 #define MMUTCL2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 7015 #define MMUTCL2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 7016 #define MMUTCL2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 7017 #define MMUTCL2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a 7018 #define MMUTCL2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL 7019 #define MMUTCL2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L 7020 #define MMUTCL2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L 7021 #define MMUTCL2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L 7022 #define MMUTCL2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L 7023 #define MMUTCL2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L 7024 7025 7026 // addressBlock: mmhub_mmutcl2_mmvml2prdec 7027 //MMMC_VM_L2_PERFCOUNTER_LO 7028 #define MMMC_VM_L2_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 7029 #define MMMC_VM_L2_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL 7030 //MMMC_VM_L2_PERFCOUNTER_HI 7031 #define MMMC_VM_L2_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 7032 #define MMMC_VM_L2_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 7033 #define MMMC_VM_L2_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL 7034 #define MMMC_VM_L2_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L 7035 //MMUTCL2_PERFCOUNTER_LO 7036 #define MMUTCL2_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 7037 #define MMUTCL2_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL 7038 //MMUTCL2_PERFCOUNTER_HI 7039 #define MMUTCL2_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 7040 #define MMUTCL2_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 7041 #define MMUTCL2_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL 7042 #define MMUTCL2_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L 7043 7044 7045 // addressBlock: mmhub_mmutcl2_mmvmsharedhvdec 7046 //MMMC_VM_FB_SIZE_OFFSET_VF0 7047 #define MMMC_VM_FB_SIZE_OFFSET_VF0__VF_FB_SIZE__SHIFT 0x0 7048 #define MMMC_VM_FB_SIZE_OFFSET_VF0__VF_FB_OFFSET__SHIFT 0x10 7049 #define MMMC_VM_FB_SIZE_OFFSET_VF0__VF_FB_SIZE_MASK 0x0000FFFFL 7050 #define MMMC_VM_FB_SIZE_OFFSET_VF0__VF_FB_OFFSET_MASK 0xFFFF0000L 7051 //MMMC_VM_FB_SIZE_OFFSET_VF1 7052 #define MMMC_VM_FB_SIZE_OFFSET_VF1__VF_FB_SIZE__SHIFT 0x0 7053 #define MMMC_VM_FB_SIZE_OFFSET_VF1__VF_FB_OFFSET__SHIFT 0x10 7054 #define MMMC_VM_FB_SIZE_OFFSET_VF1__VF_FB_SIZE_MASK 0x0000FFFFL 7055 #define MMMC_VM_FB_SIZE_OFFSET_VF1__VF_FB_OFFSET_MASK 0xFFFF0000L 7056 //MMMC_VM_FB_SIZE_OFFSET_VF2 7057 #define MMMC_VM_FB_SIZE_OFFSET_VF2__VF_FB_SIZE__SHIFT 0x0 7058 #define MMMC_VM_FB_SIZE_OFFSET_VF2__VF_FB_OFFSET__SHIFT 0x10 7059 #define MMMC_VM_FB_SIZE_OFFSET_VF2__VF_FB_SIZE_MASK 0x0000FFFFL 7060 #define MMMC_VM_FB_SIZE_OFFSET_VF2__VF_FB_OFFSET_MASK 0xFFFF0000L 7061 //MMMC_VM_FB_SIZE_OFFSET_VF3 7062 #define MMMC_VM_FB_SIZE_OFFSET_VF3__VF_FB_SIZE__SHIFT 0x0 7063 #define MMMC_VM_FB_SIZE_OFFSET_VF3__VF_FB_OFFSET__SHIFT 0x10 7064 #define MMMC_VM_FB_SIZE_OFFSET_VF3__VF_FB_SIZE_MASK 0x0000FFFFL 7065 #define MMMC_VM_FB_SIZE_OFFSET_VF3__VF_FB_OFFSET_MASK 0xFFFF0000L 7066 //MMMC_VM_FB_SIZE_OFFSET_VF4 7067 #define MMMC_VM_FB_SIZE_OFFSET_VF4__VF_FB_SIZE__SHIFT 0x0 7068 #define MMMC_VM_FB_SIZE_OFFSET_VF4__VF_FB_OFFSET__SHIFT 0x10 7069 #define MMMC_VM_FB_SIZE_OFFSET_VF4__VF_FB_SIZE_MASK 0x0000FFFFL 7070 #define MMMC_VM_FB_SIZE_OFFSET_VF4__VF_FB_OFFSET_MASK 0xFFFF0000L 7071 //MMMC_VM_FB_SIZE_OFFSET_VF5 7072 #define MMMC_VM_FB_SIZE_OFFSET_VF5__VF_FB_SIZE__SHIFT 0x0 7073 #define MMMC_VM_FB_SIZE_OFFSET_VF5__VF_FB_OFFSET__SHIFT 0x10 7074 #define MMMC_VM_FB_SIZE_OFFSET_VF5__VF_FB_SIZE_MASK 0x0000FFFFL 7075 #define MMMC_VM_FB_SIZE_OFFSET_VF5__VF_FB_OFFSET_MASK 0xFFFF0000L 7076 //MMMC_VM_FB_SIZE_OFFSET_VF6 7077 #define MMMC_VM_FB_SIZE_OFFSET_VF6__VF_FB_SIZE__SHIFT 0x0 7078 #define MMMC_VM_FB_SIZE_OFFSET_VF6__VF_FB_OFFSET__SHIFT 0x10 7079 #define MMMC_VM_FB_SIZE_OFFSET_VF6__VF_FB_SIZE_MASK 0x0000FFFFL 7080 #define MMMC_VM_FB_SIZE_OFFSET_VF6__VF_FB_OFFSET_MASK 0xFFFF0000L 7081 //MMMC_VM_FB_SIZE_OFFSET_VF7 7082 #define MMMC_VM_FB_SIZE_OFFSET_VF7__VF_FB_SIZE__SHIFT 0x0 7083 #define MMMC_VM_FB_SIZE_OFFSET_VF7__VF_FB_OFFSET__SHIFT 0x10 7084 #define MMMC_VM_FB_SIZE_OFFSET_VF7__VF_FB_SIZE_MASK 0x0000FFFFL 7085 #define MMMC_VM_FB_SIZE_OFFSET_VF7__VF_FB_OFFSET_MASK 0xFFFF0000L 7086 //MMMC_VM_FB_SIZE_OFFSET_VF8 7087 #define MMMC_VM_FB_SIZE_OFFSET_VF8__VF_FB_SIZE__SHIFT 0x0 7088 #define MMMC_VM_FB_SIZE_OFFSET_VF8__VF_FB_OFFSET__SHIFT 0x10 7089 #define MMMC_VM_FB_SIZE_OFFSET_VF8__VF_FB_SIZE_MASK 0x0000FFFFL 7090 #define MMMC_VM_FB_SIZE_OFFSET_VF8__VF_FB_OFFSET_MASK 0xFFFF0000L 7091 //MMMC_VM_FB_SIZE_OFFSET_VF9 7092 #define MMMC_VM_FB_SIZE_OFFSET_VF9__VF_FB_SIZE__SHIFT 0x0 7093 #define MMMC_VM_FB_SIZE_OFFSET_VF9__VF_FB_OFFSET__SHIFT 0x10 7094 #define MMMC_VM_FB_SIZE_OFFSET_VF9__VF_FB_SIZE_MASK 0x0000FFFFL 7095 #define MMMC_VM_FB_SIZE_OFFSET_VF9__VF_FB_OFFSET_MASK 0xFFFF0000L 7096 //MMMC_VM_FB_SIZE_OFFSET_VF10 7097 #define MMMC_VM_FB_SIZE_OFFSET_VF10__VF_FB_SIZE__SHIFT 0x0 7098 #define MMMC_VM_FB_SIZE_OFFSET_VF10__VF_FB_OFFSET__SHIFT 0x10 7099 #define MMMC_VM_FB_SIZE_OFFSET_VF10__VF_FB_SIZE_MASK 0x0000FFFFL 7100 #define MMMC_VM_FB_SIZE_OFFSET_VF10__VF_FB_OFFSET_MASK 0xFFFF0000L 7101 //MMMC_VM_FB_SIZE_OFFSET_VF11 7102 #define MMMC_VM_FB_SIZE_OFFSET_VF11__VF_FB_SIZE__SHIFT 0x0 7103 #define MMMC_VM_FB_SIZE_OFFSET_VF11__VF_FB_OFFSET__SHIFT 0x10 7104 #define MMMC_VM_FB_SIZE_OFFSET_VF11__VF_FB_SIZE_MASK 0x0000FFFFL 7105 #define MMMC_VM_FB_SIZE_OFFSET_VF11__VF_FB_OFFSET_MASK 0xFFFF0000L 7106 //MMMC_VM_FB_SIZE_OFFSET_VF12 7107 #define MMMC_VM_FB_SIZE_OFFSET_VF12__VF_FB_SIZE__SHIFT 0x0 7108 #define MMMC_VM_FB_SIZE_OFFSET_VF12__VF_FB_OFFSET__SHIFT 0x10 7109 #define MMMC_VM_FB_SIZE_OFFSET_VF12__VF_FB_SIZE_MASK 0x0000FFFFL 7110 #define MMMC_VM_FB_SIZE_OFFSET_VF12__VF_FB_OFFSET_MASK 0xFFFF0000L 7111 //MMMC_VM_FB_SIZE_OFFSET_VF13 7112 #define MMMC_VM_FB_SIZE_OFFSET_VF13__VF_FB_SIZE__SHIFT 0x0 7113 #define MMMC_VM_FB_SIZE_OFFSET_VF13__VF_FB_OFFSET__SHIFT 0x10 7114 #define MMMC_VM_FB_SIZE_OFFSET_VF13__VF_FB_SIZE_MASK 0x0000FFFFL 7115 #define MMMC_VM_FB_SIZE_OFFSET_VF13__VF_FB_OFFSET_MASK 0xFFFF0000L 7116 //MMMC_VM_FB_SIZE_OFFSET_VF14 7117 #define MMMC_VM_FB_SIZE_OFFSET_VF14__VF_FB_SIZE__SHIFT 0x0 7118 #define MMMC_VM_FB_SIZE_OFFSET_VF14__VF_FB_OFFSET__SHIFT 0x10 7119 #define MMMC_VM_FB_SIZE_OFFSET_VF14__VF_FB_SIZE_MASK 0x0000FFFFL 7120 #define MMMC_VM_FB_SIZE_OFFSET_VF14__VF_FB_OFFSET_MASK 0xFFFF0000L 7121 //MMMC_VM_FB_SIZE_OFFSET_VF15 7122 #define MMMC_VM_FB_SIZE_OFFSET_VF15__VF_FB_SIZE__SHIFT 0x0 7123 #define MMMC_VM_FB_SIZE_OFFSET_VF15__VF_FB_OFFSET__SHIFT 0x10 7124 #define MMMC_VM_FB_SIZE_OFFSET_VF15__VF_FB_SIZE_MASK 0x0000FFFFL 7125 #define MMMC_VM_FB_SIZE_OFFSET_VF15__VF_FB_OFFSET_MASK 0xFFFF0000L 7126 7127 7128 // addressBlock: mmhub_mmutcl2_mmvmsharedpfdec 7129 //MMMC_VM_FB_OFFSET 7130 #define MMMC_VM_FB_OFFSET__FB_OFFSET__SHIFT 0x0 7131 #define MMMC_VM_FB_OFFSET__FB_OFFSET_MASK 0x00FFFFFFL 7132 //MMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB 7133 #define MMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB__PHYSICAL_PAGE_NUMBER_LSB__SHIFT 0x0 7134 #define MMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB__PHYSICAL_PAGE_NUMBER_LSB_MASK 0xFFFFFFFFL 7135 //MMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB 7136 #define MMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__PHYSICAL_PAGE_NUMBER_MSB__SHIFT 0x0 7137 #define MMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__PHYSICAL_PAGE_NUMBER_MSB_MASK 0x0000000FL 7138 //MMMC_VM_STEERING 7139 #define MMMC_VM_STEERING__DEFAULT_STEERING__SHIFT 0x0 7140 #define MMMC_VM_STEERING__DEFAULT_STEERING_MASK 0x00000003L 7141 //MMMC_MEM_POWER_LS 7142 #define MMMC_MEM_POWER_LS__LS_SETUP__SHIFT 0x0 7143 #define MMMC_MEM_POWER_LS__LS_HOLD__SHIFT 0x6 7144 #define MMMC_MEM_POWER_LS__LS_SETUP_MASK 0x0000003FL 7145 #define MMMC_MEM_POWER_LS__LS_HOLD_MASK 0x00000FC0L 7146 //MMMC_VM_CACHEABLE_DRAM_ADDRESS_START 7147 #define MMMC_VM_CACHEABLE_DRAM_ADDRESS_START__ADDRESS__SHIFT 0x0 7148 #define MMMC_VM_CACHEABLE_DRAM_ADDRESS_START__ADDRESS_MASK 0x000FFFFFL 7149 //MMMC_VM_CACHEABLE_DRAM_ADDRESS_END 7150 #define MMMC_VM_CACHEABLE_DRAM_ADDRESS_END__ADDRESS__SHIFT 0x0 7151 #define MMMC_VM_CACHEABLE_DRAM_ADDRESS_END__ADDRESS_MASK 0x000FFFFFL 7152 //MMMC_VM_LOCAL_SYSMEM_ADDRESS_START 7153 #define MMMC_VM_LOCAL_SYSMEM_ADDRESS_START__ADDRESS__SHIFT 0x0 7154 #define MMMC_VM_LOCAL_SYSMEM_ADDRESS_START__ADDRESS_MASK 0x000FFFFFL 7155 //MMMC_VM_LOCAL_SYSMEM_ADDRESS_END 7156 #define MMMC_VM_LOCAL_SYSMEM_ADDRESS_END__ADDRESS__SHIFT 0x0 7157 #define MMMC_VM_LOCAL_SYSMEM_ADDRESS_END__ADDRESS_MASK 0x000FFFFFL 7158 //MMMC_VM_APT_CNTL 7159 #define MMMC_VM_APT_CNTL__FORCE_MTYPE_UC__SHIFT 0x0 7160 #define MMMC_VM_APT_CNTL__DIRECT_SYSTEM_EN__SHIFT 0x1 7161 #define MMMC_VM_APT_CNTL__FRAG_APT_INTXN_MODE__SHIFT 0x2 7162 #define MMMC_VM_APT_CNTL__CHECK_IS_LOCAL__SHIFT 0x4 7163 #define MMMC_VM_APT_CNTL__CAP_FRAG_SIZE_2M__SHIFT 0x5 7164 #define MMMC_VM_APT_CNTL__LOCAL_SYSMEM_APERTURE_CNTL__SHIFT 0x6 7165 #define MMMC_VM_APT_CNTL__FORCE_MTYPE_UC_MASK 0x00000001L 7166 #define MMMC_VM_APT_CNTL__DIRECT_SYSTEM_EN_MASK 0x00000002L 7167 #define MMMC_VM_APT_CNTL__FRAG_APT_INTXN_MODE_MASK 0x0000000CL 7168 #define MMMC_VM_APT_CNTL__CHECK_IS_LOCAL_MASK 0x00000010L 7169 #define MMMC_VM_APT_CNTL__CAP_FRAG_SIZE_2M_MASK 0x00000020L 7170 #define MMMC_VM_APT_CNTL__LOCAL_SYSMEM_APERTURE_CNTL_MASK 0x000000C0L 7171 //MMMC_VM_LOCAL_FB_ADDRESS_START 7172 #define MMMC_VM_LOCAL_FB_ADDRESS_START__ADDRESS__SHIFT 0x0 7173 #define MMMC_VM_LOCAL_FB_ADDRESS_START__ADDRESS_MASK 0x000FFFFFL 7174 //MMMC_VM_LOCAL_FB_ADDRESS_END 7175 #define MMMC_VM_LOCAL_FB_ADDRESS_END__ADDRESS__SHIFT 0x0 7176 #define MMMC_VM_LOCAL_FB_ADDRESS_END__ADDRESS_MASK 0x000FFFFFL 7177 //MMMC_VM_LOCAL_FB_ADDRESS_LOCK_CNTL 7178 #define MMMC_VM_LOCAL_FB_ADDRESS_LOCK_CNTL__LOCK__SHIFT 0x0 7179 #define MMMC_VM_LOCAL_FB_ADDRESS_LOCK_CNTL__LOCK_MASK 0x00000001L 7180 //MMUTCL2_CGTT_CLK_CTRL 7181 #define MMUTCL2_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 7182 #define MMUTCL2_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x5 7183 #define MMUTCL2_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS__SHIFT 0xd 7184 #define MMUTCL2_CGTT_CLK_CTRL__LS_DISABLE__SHIFT 0x1e 7185 #define MMUTCL2_CGTT_CLK_CTRL__BUSY_OVERRIDE__SHIFT 0x1f 7186 #define MMUTCL2_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000001FL 7187 #define MMUTCL2_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00001FE0L 7188 #define MMUTCL2_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS_MASK 0x1FFFE000L 7189 #define MMUTCL2_CGTT_CLK_CTRL__LS_DISABLE_MASK 0x40000000L 7190 #define MMUTCL2_CGTT_CLK_CTRL__BUSY_OVERRIDE_MASK 0x80000000L 7191 //MMUTCL2_CGTT_BUSY_CTRL 7192 #define MMUTCL2_CGTT_BUSY_CTRL__READ_DELAY__SHIFT 0x0 7193 #define MMUTCL2_CGTT_BUSY_CTRL__ALWAYS_BUSY__SHIFT 0x5 7194 #define MMUTCL2_CGTT_BUSY_CTRL__READ_DELAY_MASK 0x0000001FL 7195 #define MMUTCL2_CGTT_BUSY_CTRL__ALWAYS_BUSY_MASK 0x00000020L 7196 //MMMC_VM_FB_NOALLOC_CNTL 7197 #define MMMC_VM_FB_NOALLOC_CNTL__LOCAL_FB_NOALLOC_NOPTE__SHIFT 0x0 7198 #define MMMC_VM_FB_NOALLOC_CNTL__REMOTE_FB_NOALLOC_NOPTE__SHIFT 0x1 7199 #define MMMC_VM_FB_NOALLOC_CNTL__ROUTER_ATCL2_NOALLOC__SHIFT 0x2 7200 #define MMMC_VM_FB_NOALLOC_CNTL__ROUTER_GPA_MODE2_NOALLOC__SHIFT 0x3 7201 #define MMMC_VM_FB_NOALLOC_CNTL__ROUTER_GPA_MODE3_NOALLOC__SHIFT 0x4 7202 #define MMMC_VM_FB_NOALLOC_CNTL__LOCAL_FB_NOALLOC_NOPTE_MASK 0x00000001L 7203 #define MMMC_VM_FB_NOALLOC_CNTL__REMOTE_FB_NOALLOC_NOPTE_MASK 0x00000002L 7204 #define MMMC_VM_FB_NOALLOC_CNTL__ROUTER_ATCL2_NOALLOC_MASK 0x00000004L 7205 #define MMMC_VM_FB_NOALLOC_CNTL__ROUTER_GPA_MODE2_NOALLOC_MASK 0x00000008L 7206 #define MMMC_VM_FB_NOALLOC_CNTL__ROUTER_GPA_MODE3_NOALLOC_MASK 0x00000010L 7207 //MMUTCL2_HARVEST_BYPASS_GROUPS 7208 #define MMUTCL2_HARVEST_BYPASS_GROUPS__BYPASS_GROUPS__SHIFT 0x0 7209 #define MMUTCL2_HARVEST_BYPASS_GROUPS__BYPASS_GROUPS_MASK 0xFFFFFFFFL 7210 //MMUTCL2_GROUP_RET_FAULT_STATUS 7211 #define MMUTCL2_GROUP_RET_FAULT_STATUS__FAULT_GROUPS__SHIFT 0x0 7212 #define MMUTCL2_GROUP_RET_FAULT_STATUS__FAULT_GROUPS_MASK 0xFFFFFFFFL 7213 7214 7215 // addressBlock: mmhub_mmutcl2_mmvmsharedvcdec 7216 //MMMC_VM_FB_LOCATION_BASE 7217 #define MMMC_VM_FB_LOCATION_BASE__FB_BASE__SHIFT 0x0 7218 #define MMMC_VM_FB_LOCATION_BASE__FB_BASE_MASK 0x00FFFFFFL 7219 //MMMC_VM_FB_LOCATION_TOP 7220 #define MMMC_VM_FB_LOCATION_TOP__FB_TOP__SHIFT 0x0 7221 #define MMMC_VM_FB_LOCATION_TOP__FB_TOP_MASK 0x00FFFFFFL 7222 //MMMC_VM_AGP_TOP 7223 #define MMMC_VM_AGP_TOP__AGP_TOP__SHIFT 0x0 7224 #define MMMC_VM_AGP_TOP__AGP_TOP_MASK 0x00FFFFFFL 7225 //MMMC_VM_AGP_BOT 7226 #define MMMC_VM_AGP_BOT__AGP_BOT__SHIFT 0x0 7227 #define MMMC_VM_AGP_BOT__AGP_BOT_MASK 0x00FFFFFFL 7228 //MMMC_VM_AGP_BASE 7229 #define MMMC_VM_AGP_BASE__AGP_BASE__SHIFT 0x0 7230 #define MMMC_VM_AGP_BASE__AGP_BASE_MASK 0x00FFFFFFL 7231 //MMMC_VM_SYSTEM_APERTURE_LOW_ADDR 7232 #define MMMC_VM_SYSTEM_APERTURE_LOW_ADDR__LOGICAL_ADDR__SHIFT 0x0 7233 #define MMMC_VM_SYSTEM_APERTURE_LOW_ADDR__LOGICAL_ADDR_MASK 0x3FFFFFFFL 7234 //MMMC_VM_SYSTEM_APERTURE_HIGH_ADDR 7235 #define MMMC_VM_SYSTEM_APERTURE_HIGH_ADDR__LOGICAL_ADDR__SHIFT 0x0 7236 #define MMMC_VM_SYSTEM_APERTURE_HIGH_ADDR__LOGICAL_ADDR_MASK 0x3FFFFFFFL 7237 //MMMC_VM_MX_L1_TLB_CNTL 7238 #define MMMC_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB__SHIFT 0x0 7239 #define MMMC_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE__SHIFT 0x3 7240 #define MMMC_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS__SHIFT 0x5 7241 #define MMMC_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL__SHIFT 0x6 7242 #define MMMC_VM_MX_L1_TLB_CNTL__ECO_BITS__SHIFT 0x7 7243 #define MMMC_VM_MX_L1_TLB_CNTL__MTYPE__SHIFT 0xb 7244 #define MMMC_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB_MASK 0x00000001L 7245 #define MMMC_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE_MASK 0x00000018L 7246 #define MMMC_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS_MASK 0x00000020L 7247 #define MMMC_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL_MASK 0x00000040L 7248 #define MMMC_VM_MX_L1_TLB_CNTL__ECO_BITS_MASK 0x00000780L 7249 #define MMMC_VM_MX_L1_TLB_CNTL__MTYPE_MASK 0x00003800L 7250 7251 7252 // addressBlock: mmhub_mmutcl2_mmatcl2pfcntrdec 7253 //MM_ATC_L2_PERFCOUNTER_LO 7254 #define MM_ATC_L2_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 7255 #define MM_ATC_L2_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL 7256 //MM_ATC_L2_PERFCOUNTER_HI 7257 #define MM_ATC_L2_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 7258 #define MM_ATC_L2_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 7259 #define MM_ATC_L2_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL 7260 #define MM_ATC_L2_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L 7261 7262 7263 // addressBlock: mmhub_mmutcl2_mmatcl2pfcntldec 7264 //MM_ATC_L2_PERFCOUNTER0_CFG 7265 #define MM_ATC_L2_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 7266 #define MM_ATC_L2_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 7267 #define MM_ATC_L2_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 7268 #define MM_ATC_L2_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c 7269 #define MM_ATC_L2_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d 7270 #define MM_ATC_L2_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL 7271 #define MM_ATC_L2_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L 7272 #define MM_ATC_L2_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L 7273 #define MM_ATC_L2_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L 7274 #define MM_ATC_L2_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L 7275 //MM_ATC_L2_PERFCOUNTER1_CFG 7276 #define MM_ATC_L2_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 7277 #define MM_ATC_L2_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 7278 #define MM_ATC_L2_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 7279 #define MM_ATC_L2_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c 7280 #define MM_ATC_L2_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d 7281 #define MM_ATC_L2_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL 7282 #define MM_ATC_L2_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L 7283 #define MM_ATC_L2_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L 7284 #define MM_ATC_L2_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L 7285 #define MM_ATC_L2_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L 7286 //MM_ATC_L2_PERFCOUNTER_RSLT_CNTL 7287 #define MM_ATC_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 7288 #define MM_ATC_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 7289 #define MM_ATC_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 7290 #define MM_ATC_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 7291 #define MM_ATC_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 7292 #define MM_ATC_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a 7293 #define MM_ATC_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL 7294 #define MM_ATC_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L 7295 #define MM_ATC_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L 7296 #define MM_ATC_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L 7297 #define MM_ATC_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L 7298 #define MM_ATC_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L 7299 7300 7301 // addressBlock: mmhub_mmutcl2_mmvml2pspdec 7302 //MMUTCL2_TRANSLATION_BYPASS_BY_VMID 7303 #define MMUTCL2_TRANSLATION_BYPASS_BY_VMID__TRANS_BYPASS_VMIDS__SHIFT 0x0 7304 #define MMUTCL2_TRANSLATION_BYPASS_BY_VMID__GPA_MODE_VMIDS__SHIFT 0x10 7305 #define MMUTCL2_TRANSLATION_BYPASS_BY_VMID__TRANS_BYPASS_VMIDS_MASK 0x0000FFFFL 7306 #define MMUTCL2_TRANSLATION_BYPASS_BY_VMID__GPA_MODE_VMIDS_MASK 0xFFFF0000L 7307 //MMUTC_TRANSLATION_FAULT_CNTL0 7308 #define MMUTC_TRANSLATION_FAULT_CNTL0__DEFAULT_PHYSICAL_PAGE_ADDRESS_LSB__SHIFT 0x0 7309 #define MMUTC_TRANSLATION_FAULT_CNTL0__DEFAULT_PHYSICAL_PAGE_ADDRESS_LSB_MASK 0xFFFFFFFFL 7310 //MMUTC_TRANSLATION_FAULT_CNTL1 7311 #define MMUTC_TRANSLATION_FAULT_CNTL1__DEFAULT_PHYSICAL_PAGE_ADDRESS_MSB__SHIFT 0x0 7312 #define MMUTC_TRANSLATION_FAULT_CNTL1__DEFAULT_IO__SHIFT 0x4 7313 #define MMUTC_TRANSLATION_FAULT_CNTL1__DEFAULT_SPA__SHIFT 0x5 7314 #define MMUTC_TRANSLATION_FAULT_CNTL1__DEFAULT_SNOOP__SHIFT 0x6 7315 #define MMUTC_TRANSLATION_FAULT_CNTL1__DEFAULT_PHYSICAL_PAGE_ADDRESS_MSB_MASK 0x0000000FL 7316 #define MMUTC_TRANSLATION_FAULT_CNTL1__DEFAULT_IO_MASK 0x00000010L 7317 #define MMUTC_TRANSLATION_FAULT_CNTL1__DEFAULT_SPA_MASK 0x00000020L 7318 #define MMUTC_TRANSLATION_FAULT_CNTL1__DEFAULT_SNOOP_MASK 0x00000040L 7319 //MMUTCL2_FFBM_ENABLE_CNTL 7320 #define MMUTCL2_FFBM_ENABLE_CNTL__ENABLE_FFBM__SHIFT 0x0 7321 #define MMUTCL2_FFBM_ENABLE_CNTL__ENABLE_FFBM_MASK 0x00000001L 7322 7323 7324 // addressBlock: mmhub_mmutcl2_mml2tlbpspdec 7325 //MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_CNTL 7326 #define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_CNTL__ENABLE__SHIFT 0x0 7327 #define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_CNTL__ENABLE_MASK 0x00000001L 7328 7329 7330 // addressBlock: mmhub_mmutcl2_mmatcl2pspdec 7331 //MM_ATC_L2_IOV_MODE_CNTL 7332 #define MM_ATC_L2_IOV_MODE_CNTL__PSEUDO_IOV_EN__SHIFT 0x0 7333 #define MM_ATC_L2_IOV_MODE_CNTL__PSEUDO_IOV_EN_MASK 0x00000001L 7334 7335 7336 // addressBlock: mmhub_mmutcl2_mml2tlbpfdec 7337 //MML2TLB_TLB0_STATUS 7338 #define MML2TLB_TLB0_STATUS__BUSY__SHIFT 0x0 7339 #define MML2TLB_TLB0_STATUS__FOUND_PARITY_ERRORS__SHIFT 0x1 7340 #define MML2TLB_TLB0_STATUS__FOUND_APERTURE_FAULTS__SHIFT 0x2 7341 #define MML2TLB_TLB0_STATUS__BUSY_MASK 0x00000001L 7342 #define MML2TLB_TLB0_STATUS__FOUND_PARITY_ERRORS_MASK 0x00000002L 7343 #define MML2TLB_TLB0_STATUS__FOUND_APERTURE_FAULTS_MASK 0x00000004L 7344 //MML2TLB_TMZ_CNTL 7345 #define MML2TLB_TMZ_CNTL__TMZ_MODULATION__SHIFT 0x0 7346 #define MML2TLB_TMZ_CNTL__TMZ_MODULATION_MASK 0x00000001L 7347 //MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_LO 7348 #define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_LO__ADDR__SHIFT 0x0 7349 #define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_LO__ADDR_MASK 0xFFFFFFFFL 7350 //MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI 7351 #define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__ADDR__SHIFT 0x0 7352 #define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__VMID__SHIFT 0x4 7353 #define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__VFID__SHIFT 0x8 7354 #define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__VF__SHIFT 0xc 7355 #define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__GPA__SHIFT 0xd 7356 #define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__RD_PERM__SHIFT 0xf 7357 #define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__WR_PERM__SHIFT 0x10 7358 #define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__EX_PERM__SHIFT 0x11 7359 #define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__CLIENT_ID__SHIFT 0x12 7360 #define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__REQ__SHIFT 0x1e 7361 #define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__ADDR_MASK 0x0000000FL 7362 #define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__VMID_MASK 0x000000F0L 7363 #define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__VFID_MASK 0x00000F00L 7364 #define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__VF_MASK 0x00001000L 7365 #define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__GPA_MASK 0x00006000L 7366 #define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__RD_PERM_MASK 0x00008000L 7367 #define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__WR_PERM_MASK 0x00010000L 7368 #define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__EX_PERM_MASK 0x00020000L 7369 #define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__CLIENT_ID_MASK 0x07FC0000L 7370 #define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__REQ_MASK 0x40000000L 7371 //MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_LO 7372 #define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_LO__ADDR__SHIFT 0x0 7373 #define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_LO__ADDR_MASK 0xFFFFFFFFL 7374 //MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI 7375 #define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__ADDR__SHIFT 0x0 7376 #define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__PERMS__SHIFT 0x4 7377 #define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__FRAGMENT_SIZE__SHIFT 0x7 7378 #define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__SNOOP__SHIFT 0xd 7379 #define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__SPA__SHIFT 0xe 7380 #define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__IO__SHIFT 0xf 7381 #define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__PTE_TMZ__SHIFT 0x10 7382 #define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__NO_PTE__SHIFT 0x11 7383 #define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__MTYPE__SHIFT 0x12 7384 #define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__MEMLOG__SHIFT 0x15 7385 #define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__NACK__SHIFT 0x16 7386 #define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__LLC_NOALLOC__SHIFT 0x18 7387 #define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__ACK__SHIFT 0x1f 7388 #define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__ADDR_MASK 0x0000000FL 7389 #define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__PERMS_MASK 0x00000070L 7390 #define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__FRAGMENT_SIZE_MASK 0x00001F80L 7391 #define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__SNOOP_MASK 0x00002000L 7392 #define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__SPA_MASK 0x00004000L 7393 #define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__IO_MASK 0x00008000L 7394 #define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__PTE_TMZ_MASK 0x00010000L 7395 #define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__NO_PTE_MASK 0x00020000L 7396 #define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__MTYPE_MASK 0x001C0000L 7397 #define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__MEMLOG_MASK 0x00200000L 7398 #define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__NACK_MASK 0x00C00000L 7399 #define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__LLC_NOALLOC_MASK 0x01000000L 7400 #define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__ACK_MASK 0x80000000L 7401 //MMUTCL2_L2TLB_CREDIT_SAFETY_FETCH_RDREQ 7402 #define MMUTCL2_L2TLB_CREDIT_SAFETY_FETCH_RDREQ__CREDITS__SHIFT 0x0 7403 #define MMUTCL2_L2TLB_CREDIT_SAFETY_FETCH_RDREQ__WRITE__SHIFT 0xa 7404 #define MMUTCL2_L2TLB_CREDIT_SAFETY_FETCH_RDREQ__CREDITS_MASK 0x000003FFL 7405 #define MMUTCL2_L2TLB_CREDIT_SAFETY_FETCH_RDREQ__WRITE_MASK 0x00000400L 7406 7407 7408 // addressBlock: mmhub_mmutcl2_mml2tlbpldec 7409 //MML2TLB_PERFCOUNTER0_CFG 7410 #define MML2TLB_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 7411 #define MML2TLB_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 7412 #define MML2TLB_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 7413 #define MML2TLB_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c 7414 #define MML2TLB_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d 7415 #define MML2TLB_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL 7416 #define MML2TLB_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L 7417 #define MML2TLB_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L 7418 #define MML2TLB_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L 7419 #define MML2TLB_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L 7420 //MML2TLB_PERFCOUNTER1_CFG 7421 #define MML2TLB_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 7422 #define MML2TLB_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 7423 #define MML2TLB_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 7424 #define MML2TLB_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c 7425 #define MML2TLB_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d 7426 #define MML2TLB_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL 7427 #define MML2TLB_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L 7428 #define MML2TLB_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L 7429 #define MML2TLB_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L 7430 #define MML2TLB_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L 7431 //MML2TLB_PERFCOUNTER2_CFG 7432 #define MML2TLB_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0 7433 #define MML2TLB_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8 7434 #define MML2TLB_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18 7435 #define MML2TLB_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c 7436 #define MML2TLB_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d 7437 #define MML2TLB_PERFCOUNTER2_CFG__PERF_SEL_MASK 0x000000FFL 7438 #define MML2TLB_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0x0000FF00L 7439 #define MML2TLB_PERFCOUNTER2_CFG__PERF_MODE_MASK 0x0F000000L 7440 #define MML2TLB_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000L 7441 #define MML2TLB_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000L 7442 //MML2TLB_PERFCOUNTER3_CFG 7443 #define MML2TLB_PERFCOUNTER3_CFG__PERF_SEL__SHIFT 0x0 7444 #define MML2TLB_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT 0x8 7445 #define MML2TLB_PERFCOUNTER3_CFG__PERF_MODE__SHIFT 0x18 7446 #define MML2TLB_PERFCOUNTER3_CFG__ENABLE__SHIFT 0x1c 7447 #define MML2TLB_PERFCOUNTER3_CFG__CLEAR__SHIFT 0x1d 7448 #define MML2TLB_PERFCOUNTER3_CFG__PERF_SEL_MASK 0x000000FFL 7449 #define MML2TLB_PERFCOUNTER3_CFG__PERF_SEL_END_MASK 0x0000FF00L 7450 #define MML2TLB_PERFCOUNTER3_CFG__PERF_MODE_MASK 0x0F000000L 7451 #define MML2TLB_PERFCOUNTER3_CFG__ENABLE_MASK 0x10000000L 7452 #define MML2TLB_PERFCOUNTER3_CFG__CLEAR_MASK 0x20000000L 7453 //MML2TLB_PERFCOUNTER_RSLT_CNTL 7454 #define MML2TLB_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 7455 #define MML2TLB_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 7456 #define MML2TLB_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 7457 #define MML2TLB_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 7458 #define MML2TLB_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 7459 #define MML2TLB_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a 7460 #define MML2TLB_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL 7461 #define MML2TLB_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L 7462 #define MML2TLB_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L 7463 #define MML2TLB_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L 7464 #define MML2TLB_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L 7465 #define MML2TLB_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L 7466 7467 7468 // addressBlock: mmhub_mmutcl2_mml2tlbprdec 7469 //MML2TLB_PERFCOUNTER_LO 7470 #define MML2TLB_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 7471 #define MML2TLB_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL 7472 //MML2TLB_PERFCOUNTER_HI 7473 #define MML2TLB_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 7474 #define MML2TLB_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 7475 #define MML2TLB_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL 7476 #define MML2TLB_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L 7477 7478 #endif 7479