1 /* 2 * Copyright (C) 2020 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included 12 * in all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN 18 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 19 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 20 */ 21 #ifndef _mmhub_2_3_0_SH_MASK_HEADER 22 #define _mmhub_2_3_0_SH_MASK_HEADER 23 24 25 // addressBlock: mmhub_dagbdec 26 //DAGB0_RDCLI0 27 #define DAGB0_RDCLI0__VIRT_CHAN__SHIFT 0x0 28 #define DAGB0_RDCLI0__CHECK_TLB_CREDIT__SHIFT 0x3 29 #define DAGB0_RDCLI0__URG_HIGH__SHIFT 0x4 30 #define DAGB0_RDCLI0__URG_LOW__SHIFT 0x8 31 #define DAGB0_RDCLI0__MAX_BW_ENABLE__SHIFT 0xc 32 #define DAGB0_RDCLI0__MAX_BW__SHIFT 0xd 33 #define DAGB0_RDCLI0__MIN_BW_ENABLE__SHIFT 0x15 34 #define DAGB0_RDCLI0__MIN_BW__SHIFT 0x16 35 #define DAGB0_RDCLI0__OSD_LIMITER_ENABLE__SHIFT 0x19 36 #define DAGB0_RDCLI0__MAX_OSD__SHIFT 0x1a 37 #define DAGB0_RDCLI0__VIRT_CHAN_MASK 0x00000007L 38 #define DAGB0_RDCLI0__CHECK_TLB_CREDIT_MASK 0x00000008L 39 #define DAGB0_RDCLI0__URG_HIGH_MASK 0x000000F0L 40 #define DAGB0_RDCLI0__URG_LOW_MASK 0x00000F00L 41 #define DAGB0_RDCLI0__MAX_BW_ENABLE_MASK 0x00001000L 42 #define DAGB0_RDCLI0__MAX_BW_MASK 0x001FE000L 43 #define DAGB0_RDCLI0__MIN_BW_ENABLE_MASK 0x00200000L 44 #define DAGB0_RDCLI0__MIN_BW_MASK 0x01C00000L 45 #define DAGB0_RDCLI0__OSD_LIMITER_ENABLE_MASK 0x02000000L 46 #define DAGB0_RDCLI0__MAX_OSD_MASK 0xFC000000L 47 //DAGB0_RDCLI1 48 #define DAGB0_RDCLI1__VIRT_CHAN__SHIFT 0x0 49 #define DAGB0_RDCLI1__CHECK_TLB_CREDIT__SHIFT 0x3 50 #define DAGB0_RDCLI1__URG_HIGH__SHIFT 0x4 51 #define DAGB0_RDCLI1__URG_LOW__SHIFT 0x8 52 #define DAGB0_RDCLI1__MAX_BW_ENABLE__SHIFT 0xc 53 #define DAGB0_RDCLI1__MAX_BW__SHIFT 0xd 54 #define DAGB0_RDCLI1__MIN_BW_ENABLE__SHIFT 0x15 55 #define DAGB0_RDCLI1__MIN_BW__SHIFT 0x16 56 #define DAGB0_RDCLI1__OSD_LIMITER_ENABLE__SHIFT 0x19 57 #define DAGB0_RDCLI1__MAX_OSD__SHIFT 0x1a 58 #define DAGB0_RDCLI1__VIRT_CHAN_MASK 0x00000007L 59 #define DAGB0_RDCLI1__CHECK_TLB_CREDIT_MASK 0x00000008L 60 #define DAGB0_RDCLI1__URG_HIGH_MASK 0x000000F0L 61 #define DAGB0_RDCLI1__URG_LOW_MASK 0x00000F00L 62 #define DAGB0_RDCLI1__MAX_BW_ENABLE_MASK 0x00001000L 63 #define DAGB0_RDCLI1__MAX_BW_MASK 0x001FE000L 64 #define DAGB0_RDCLI1__MIN_BW_ENABLE_MASK 0x00200000L 65 #define DAGB0_RDCLI1__MIN_BW_MASK 0x01C00000L 66 #define DAGB0_RDCLI1__OSD_LIMITER_ENABLE_MASK 0x02000000L 67 #define DAGB0_RDCLI1__MAX_OSD_MASK 0xFC000000L 68 //DAGB0_RDCLI2 69 #define DAGB0_RDCLI2__VIRT_CHAN__SHIFT 0x0 70 #define DAGB0_RDCLI2__CHECK_TLB_CREDIT__SHIFT 0x3 71 #define DAGB0_RDCLI2__URG_HIGH__SHIFT 0x4 72 #define DAGB0_RDCLI2__URG_LOW__SHIFT 0x8 73 #define DAGB0_RDCLI2__MAX_BW_ENABLE__SHIFT 0xc 74 #define DAGB0_RDCLI2__MAX_BW__SHIFT 0xd 75 #define DAGB0_RDCLI2__MIN_BW_ENABLE__SHIFT 0x15 76 #define DAGB0_RDCLI2__MIN_BW__SHIFT 0x16 77 #define DAGB0_RDCLI2__OSD_LIMITER_ENABLE__SHIFT 0x19 78 #define DAGB0_RDCLI2__MAX_OSD__SHIFT 0x1a 79 #define DAGB0_RDCLI2__VIRT_CHAN_MASK 0x00000007L 80 #define DAGB0_RDCLI2__CHECK_TLB_CREDIT_MASK 0x00000008L 81 #define DAGB0_RDCLI2__URG_HIGH_MASK 0x000000F0L 82 #define DAGB0_RDCLI2__URG_LOW_MASK 0x00000F00L 83 #define DAGB0_RDCLI2__MAX_BW_ENABLE_MASK 0x00001000L 84 #define DAGB0_RDCLI2__MAX_BW_MASK 0x001FE000L 85 #define DAGB0_RDCLI2__MIN_BW_ENABLE_MASK 0x00200000L 86 #define DAGB0_RDCLI2__MIN_BW_MASK 0x01C00000L 87 #define DAGB0_RDCLI2__OSD_LIMITER_ENABLE_MASK 0x02000000L 88 #define DAGB0_RDCLI2__MAX_OSD_MASK 0xFC000000L 89 //DAGB0_RDCLI3 90 #define DAGB0_RDCLI3__VIRT_CHAN__SHIFT 0x0 91 #define DAGB0_RDCLI3__CHECK_TLB_CREDIT__SHIFT 0x3 92 #define DAGB0_RDCLI3__URG_HIGH__SHIFT 0x4 93 #define DAGB0_RDCLI3__URG_LOW__SHIFT 0x8 94 #define DAGB0_RDCLI3__MAX_BW_ENABLE__SHIFT 0xc 95 #define DAGB0_RDCLI3__MAX_BW__SHIFT 0xd 96 #define DAGB0_RDCLI3__MIN_BW_ENABLE__SHIFT 0x15 97 #define DAGB0_RDCLI3__MIN_BW__SHIFT 0x16 98 #define DAGB0_RDCLI3__OSD_LIMITER_ENABLE__SHIFT 0x19 99 #define DAGB0_RDCLI3__MAX_OSD__SHIFT 0x1a 100 #define DAGB0_RDCLI3__VIRT_CHAN_MASK 0x00000007L 101 #define DAGB0_RDCLI3__CHECK_TLB_CREDIT_MASK 0x00000008L 102 #define DAGB0_RDCLI3__URG_HIGH_MASK 0x000000F0L 103 #define DAGB0_RDCLI3__URG_LOW_MASK 0x00000F00L 104 #define DAGB0_RDCLI3__MAX_BW_ENABLE_MASK 0x00001000L 105 #define DAGB0_RDCLI3__MAX_BW_MASK 0x001FE000L 106 #define DAGB0_RDCLI3__MIN_BW_ENABLE_MASK 0x00200000L 107 #define DAGB0_RDCLI3__MIN_BW_MASK 0x01C00000L 108 #define DAGB0_RDCLI3__OSD_LIMITER_ENABLE_MASK 0x02000000L 109 #define DAGB0_RDCLI3__MAX_OSD_MASK 0xFC000000L 110 //DAGB0_RDCLI4 111 #define DAGB0_RDCLI4__VIRT_CHAN__SHIFT 0x0 112 #define DAGB0_RDCLI4__CHECK_TLB_CREDIT__SHIFT 0x3 113 #define DAGB0_RDCLI4__URG_HIGH__SHIFT 0x4 114 #define DAGB0_RDCLI4__URG_LOW__SHIFT 0x8 115 #define DAGB0_RDCLI4__MAX_BW_ENABLE__SHIFT 0xc 116 #define DAGB0_RDCLI4__MAX_BW__SHIFT 0xd 117 #define DAGB0_RDCLI4__MIN_BW_ENABLE__SHIFT 0x15 118 #define DAGB0_RDCLI4__MIN_BW__SHIFT 0x16 119 #define DAGB0_RDCLI4__OSD_LIMITER_ENABLE__SHIFT 0x19 120 #define DAGB0_RDCLI4__MAX_OSD__SHIFT 0x1a 121 #define DAGB0_RDCLI4__VIRT_CHAN_MASK 0x00000007L 122 #define DAGB0_RDCLI4__CHECK_TLB_CREDIT_MASK 0x00000008L 123 #define DAGB0_RDCLI4__URG_HIGH_MASK 0x000000F0L 124 #define DAGB0_RDCLI4__URG_LOW_MASK 0x00000F00L 125 #define DAGB0_RDCLI4__MAX_BW_ENABLE_MASK 0x00001000L 126 #define DAGB0_RDCLI4__MAX_BW_MASK 0x001FE000L 127 #define DAGB0_RDCLI4__MIN_BW_ENABLE_MASK 0x00200000L 128 #define DAGB0_RDCLI4__MIN_BW_MASK 0x01C00000L 129 #define DAGB0_RDCLI4__OSD_LIMITER_ENABLE_MASK 0x02000000L 130 #define DAGB0_RDCLI4__MAX_OSD_MASK 0xFC000000L 131 //DAGB0_RDCLI5 132 #define DAGB0_RDCLI5__VIRT_CHAN__SHIFT 0x0 133 #define DAGB0_RDCLI5__CHECK_TLB_CREDIT__SHIFT 0x3 134 #define DAGB0_RDCLI5__URG_HIGH__SHIFT 0x4 135 #define DAGB0_RDCLI5__URG_LOW__SHIFT 0x8 136 #define DAGB0_RDCLI5__MAX_BW_ENABLE__SHIFT 0xc 137 #define DAGB0_RDCLI5__MAX_BW__SHIFT 0xd 138 #define DAGB0_RDCLI5__MIN_BW_ENABLE__SHIFT 0x15 139 #define DAGB0_RDCLI5__MIN_BW__SHIFT 0x16 140 #define DAGB0_RDCLI5__OSD_LIMITER_ENABLE__SHIFT 0x19 141 #define DAGB0_RDCLI5__MAX_OSD__SHIFT 0x1a 142 #define DAGB0_RDCLI5__VIRT_CHAN_MASK 0x00000007L 143 #define DAGB0_RDCLI5__CHECK_TLB_CREDIT_MASK 0x00000008L 144 #define DAGB0_RDCLI5__URG_HIGH_MASK 0x000000F0L 145 #define DAGB0_RDCLI5__URG_LOW_MASK 0x00000F00L 146 #define DAGB0_RDCLI5__MAX_BW_ENABLE_MASK 0x00001000L 147 #define DAGB0_RDCLI5__MAX_BW_MASK 0x001FE000L 148 #define DAGB0_RDCLI5__MIN_BW_ENABLE_MASK 0x00200000L 149 #define DAGB0_RDCLI5__MIN_BW_MASK 0x01C00000L 150 #define DAGB0_RDCLI5__OSD_LIMITER_ENABLE_MASK 0x02000000L 151 #define DAGB0_RDCLI5__MAX_OSD_MASK 0xFC000000L 152 //DAGB0_RDCLI6 153 #define DAGB0_RDCLI6__VIRT_CHAN__SHIFT 0x0 154 #define DAGB0_RDCLI6__CHECK_TLB_CREDIT__SHIFT 0x3 155 #define DAGB0_RDCLI6__URG_HIGH__SHIFT 0x4 156 #define DAGB0_RDCLI6__URG_LOW__SHIFT 0x8 157 #define DAGB0_RDCLI6__MAX_BW_ENABLE__SHIFT 0xc 158 #define DAGB0_RDCLI6__MAX_BW__SHIFT 0xd 159 #define DAGB0_RDCLI6__MIN_BW_ENABLE__SHIFT 0x15 160 #define DAGB0_RDCLI6__MIN_BW__SHIFT 0x16 161 #define DAGB0_RDCLI6__OSD_LIMITER_ENABLE__SHIFT 0x19 162 #define DAGB0_RDCLI6__MAX_OSD__SHIFT 0x1a 163 #define DAGB0_RDCLI6__VIRT_CHAN_MASK 0x00000007L 164 #define DAGB0_RDCLI6__CHECK_TLB_CREDIT_MASK 0x00000008L 165 #define DAGB0_RDCLI6__URG_HIGH_MASK 0x000000F0L 166 #define DAGB0_RDCLI6__URG_LOW_MASK 0x00000F00L 167 #define DAGB0_RDCLI6__MAX_BW_ENABLE_MASK 0x00001000L 168 #define DAGB0_RDCLI6__MAX_BW_MASK 0x001FE000L 169 #define DAGB0_RDCLI6__MIN_BW_ENABLE_MASK 0x00200000L 170 #define DAGB0_RDCLI6__MIN_BW_MASK 0x01C00000L 171 #define DAGB0_RDCLI6__OSD_LIMITER_ENABLE_MASK 0x02000000L 172 #define DAGB0_RDCLI6__MAX_OSD_MASK 0xFC000000L 173 //DAGB0_RDCLI7 174 #define DAGB0_RDCLI7__VIRT_CHAN__SHIFT 0x0 175 #define DAGB0_RDCLI7__CHECK_TLB_CREDIT__SHIFT 0x3 176 #define DAGB0_RDCLI7__URG_HIGH__SHIFT 0x4 177 #define DAGB0_RDCLI7__URG_LOW__SHIFT 0x8 178 #define DAGB0_RDCLI7__MAX_BW_ENABLE__SHIFT 0xc 179 #define DAGB0_RDCLI7__MAX_BW__SHIFT 0xd 180 #define DAGB0_RDCLI7__MIN_BW_ENABLE__SHIFT 0x15 181 #define DAGB0_RDCLI7__MIN_BW__SHIFT 0x16 182 #define DAGB0_RDCLI7__OSD_LIMITER_ENABLE__SHIFT 0x19 183 #define DAGB0_RDCLI7__MAX_OSD__SHIFT 0x1a 184 #define DAGB0_RDCLI7__VIRT_CHAN_MASK 0x00000007L 185 #define DAGB0_RDCLI7__CHECK_TLB_CREDIT_MASK 0x00000008L 186 #define DAGB0_RDCLI7__URG_HIGH_MASK 0x000000F0L 187 #define DAGB0_RDCLI7__URG_LOW_MASK 0x00000F00L 188 #define DAGB0_RDCLI7__MAX_BW_ENABLE_MASK 0x00001000L 189 #define DAGB0_RDCLI7__MAX_BW_MASK 0x001FE000L 190 #define DAGB0_RDCLI7__MIN_BW_ENABLE_MASK 0x00200000L 191 #define DAGB0_RDCLI7__MIN_BW_MASK 0x01C00000L 192 #define DAGB0_RDCLI7__OSD_LIMITER_ENABLE_MASK 0x02000000L 193 #define DAGB0_RDCLI7__MAX_OSD_MASK 0xFC000000L 194 //DAGB0_RDCLI8 195 #define DAGB0_RDCLI8__VIRT_CHAN__SHIFT 0x0 196 #define DAGB0_RDCLI8__CHECK_TLB_CREDIT__SHIFT 0x3 197 #define DAGB0_RDCLI8__URG_HIGH__SHIFT 0x4 198 #define DAGB0_RDCLI8__URG_LOW__SHIFT 0x8 199 #define DAGB0_RDCLI8__MAX_BW_ENABLE__SHIFT 0xc 200 #define DAGB0_RDCLI8__MAX_BW__SHIFT 0xd 201 #define DAGB0_RDCLI8__MIN_BW_ENABLE__SHIFT 0x15 202 #define DAGB0_RDCLI8__MIN_BW__SHIFT 0x16 203 #define DAGB0_RDCLI8__OSD_LIMITER_ENABLE__SHIFT 0x19 204 #define DAGB0_RDCLI8__MAX_OSD__SHIFT 0x1a 205 #define DAGB0_RDCLI8__VIRT_CHAN_MASK 0x00000007L 206 #define DAGB0_RDCLI8__CHECK_TLB_CREDIT_MASK 0x00000008L 207 #define DAGB0_RDCLI8__URG_HIGH_MASK 0x000000F0L 208 #define DAGB0_RDCLI8__URG_LOW_MASK 0x00000F00L 209 #define DAGB0_RDCLI8__MAX_BW_ENABLE_MASK 0x00001000L 210 #define DAGB0_RDCLI8__MAX_BW_MASK 0x001FE000L 211 #define DAGB0_RDCLI8__MIN_BW_ENABLE_MASK 0x00200000L 212 #define DAGB0_RDCLI8__MIN_BW_MASK 0x01C00000L 213 #define DAGB0_RDCLI8__OSD_LIMITER_ENABLE_MASK 0x02000000L 214 #define DAGB0_RDCLI8__MAX_OSD_MASK 0xFC000000L 215 //DAGB0_RDCLI9 216 #define DAGB0_RDCLI9__VIRT_CHAN__SHIFT 0x0 217 #define DAGB0_RDCLI9__CHECK_TLB_CREDIT__SHIFT 0x3 218 #define DAGB0_RDCLI9__URG_HIGH__SHIFT 0x4 219 #define DAGB0_RDCLI9__URG_LOW__SHIFT 0x8 220 #define DAGB0_RDCLI9__MAX_BW_ENABLE__SHIFT 0xc 221 #define DAGB0_RDCLI9__MAX_BW__SHIFT 0xd 222 #define DAGB0_RDCLI9__MIN_BW_ENABLE__SHIFT 0x15 223 #define DAGB0_RDCLI9__MIN_BW__SHIFT 0x16 224 #define DAGB0_RDCLI9__OSD_LIMITER_ENABLE__SHIFT 0x19 225 #define DAGB0_RDCLI9__MAX_OSD__SHIFT 0x1a 226 #define DAGB0_RDCLI9__VIRT_CHAN_MASK 0x00000007L 227 #define DAGB0_RDCLI9__CHECK_TLB_CREDIT_MASK 0x00000008L 228 #define DAGB0_RDCLI9__URG_HIGH_MASK 0x000000F0L 229 #define DAGB0_RDCLI9__URG_LOW_MASK 0x00000F00L 230 #define DAGB0_RDCLI9__MAX_BW_ENABLE_MASK 0x00001000L 231 #define DAGB0_RDCLI9__MAX_BW_MASK 0x001FE000L 232 #define DAGB0_RDCLI9__MIN_BW_ENABLE_MASK 0x00200000L 233 #define DAGB0_RDCLI9__MIN_BW_MASK 0x01C00000L 234 #define DAGB0_RDCLI9__OSD_LIMITER_ENABLE_MASK 0x02000000L 235 #define DAGB0_RDCLI9__MAX_OSD_MASK 0xFC000000L 236 //DAGB0_RDCLI10 237 #define DAGB0_RDCLI10__VIRT_CHAN__SHIFT 0x0 238 #define DAGB0_RDCLI10__CHECK_TLB_CREDIT__SHIFT 0x3 239 #define DAGB0_RDCLI10__URG_HIGH__SHIFT 0x4 240 #define DAGB0_RDCLI10__URG_LOW__SHIFT 0x8 241 #define DAGB0_RDCLI10__MAX_BW_ENABLE__SHIFT 0xc 242 #define DAGB0_RDCLI10__MAX_BW__SHIFT 0xd 243 #define DAGB0_RDCLI10__MIN_BW_ENABLE__SHIFT 0x15 244 #define DAGB0_RDCLI10__MIN_BW__SHIFT 0x16 245 #define DAGB0_RDCLI10__OSD_LIMITER_ENABLE__SHIFT 0x19 246 #define DAGB0_RDCLI10__MAX_OSD__SHIFT 0x1a 247 #define DAGB0_RDCLI10__VIRT_CHAN_MASK 0x00000007L 248 #define DAGB0_RDCLI10__CHECK_TLB_CREDIT_MASK 0x00000008L 249 #define DAGB0_RDCLI10__URG_HIGH_MASK 0x000000F0L 250 #define DAGB0_RDCLI10__URG_LOW_MASK 0x00000F00L 251 #define DAGB0_RDCLI10__MAX_BW_ENABLE_MASK 0x00001000L 252 #define DAGB0_RDCLI10__MAX_BW_MASK 0x001FE000L 253 #define DAGB0_RDCLI10__MIN_BW_ENABLE_MASK 0x00200000L 254 #define DAGB0_RDCLI10__MIN_BW_MASK 0x01C00000L 255 #define DAGB0_RDCLI10__OSD_LIMITER_ENABLE_MASK 0x02000000L 256 #define DAGB0_RDCLI10__MAX_OSD_MASK 0xFC000000L 257 //DAGB0_RDCLI11 258 #define DAGB0_RDCLI11__VIRT_CHAN__SHIFT 0x0 259 #define DAGB0_RDCLI11__CHECK_TLB_CREDIT__SHIFT 0x3 260 #define DAGB0_RDCLI11__URG_HIGH__SHIFT 0x4 261 #define DAGB0_RDCLI11__URG_LOW__SHIFT 0x8 262 #define DAGB0_RDCLI11__MAX_BW_ENABLE__SHIFT 0xc 263 #define DAGB0_RDCLI11__MAX_BW__SHIFT 0xd 264 #define DAGB0_RDCLI11__MIN_BW_ENABLE__SHIFT 0x15 265 #define DAGB0_RDCLI11__MIN_BW__SHIFT 0x16 266 #define DAGB0_RDCLI11__OSD_LIMITER_ENABLE__SHIFT 0x19 267 #define DAGB0_RDCLI11__MAX_OSD__SHIFT 0x1a 268 #define DAGB0_RDCLI11__VIRT_CHAN_MASK 0x00000007L 269 #define DAGB0_RDCLI11__CHECK_TLB_CREDIT_MASK 0x00000008L 270 #define DAGB0_RDCLI11__URG_HIGH_MASK 0x000000F0L 271 #define DAGB0_RDCLI11__URG_LOW_MASK 0x00000F00L 272 #define DAGB0_RDCLI11__MAX_BW_ENABLE_MASK 0x00001000L 273 #define DAGB0_RDCLI11__MAX_BW_MASK 0x001FE000L 274 #define DAGB0_RDCLI11__MIN_BW_ENABLE_MASK 0x00200000L 275 #define DAGB0_RDCLI11__MIN_BW_MASK 0x01C00000L 276 #define DAGB0_RDCLI11__OSD_LIMITER_ENABLE_MASK 0x02000000L 277 #define DAGB0_RDCLI11__MAX_OSD_MASK 0xFC000000L 278 //DAGB0_RDCLI12 279 #define DAGB0_RDCLI12__VIRT_CHAN__SHIFT 0x0 280 #define DAGB0_RDCLI12__CHECK_TLB_CREDIT__SHIFT 0x3 281 #define DAGB0_RDCLI12__URG_HIGH__SHIFT 0x4 282 #define DAGB0_RDCLI12__URG_LOW__SHIFT 0x8 283 #define DAGB0_RDCLI12__MAX_BW_ENABLE__SHIFT 0xc 284 #define DAGB0_RDCLI12__MAX_BW__SHIFT 0xd 285 #define DAGB0_RDCLI12__MIN_BW_ENABLE__SHIFT 0x15 286 #define DAGB0_RDCLI12__MIN_BW__SHIFT 0x16 287 #define DAGB0_RDCLI12__OSD_LIMITER_ENABLE__SHIFT 0x19 288 #define DAGB0_RDCLI12__MAX_OSD__SHIFT 0x1a 289 #define DAGB0_RDCLI12__VIRT_CHAN_MASK 0x00000007L 290 #define DAGB0_RDCLI12__CHECK_TLB_CREDIT_MASK 0x00000008L 291 #define DAGB0_RDCLI12__URG_HIGH_MASK 0x000000F0L 292 #define DAGB0_RDCLI12__URG_LOW_MASK 0x00000F00L 293 #define DAGB0_RDCLI12__MAX_BW_ENABLE_MASK 0x00001000L 294 #define DAGB0_RDCLI12__MAX_BW_MASK 0x001FE000L 295 #define DAGB0_RDCLI12__MIN_BW_ENABLE_MASK 0x00200000L 296 #define DAGB0_RDCLI12__MIN_BW_MASK 0x01C00000L 297 #define DAGB0_RDCLI12__OSD_LIMITER_ENABLE_MASK 0x02000000L 298 #define DAGB0_RDCLI12__MAX_OSD_MASK 0xFC000000L 299 //DAGB0_RDCLI13 300 #define DAGB0_RDCLI13__VIRT_CHAN__SHIFT 0x0 301 #define DAGB0_RDCLI13__CHECK_TLB_CREDIT__SHIFT 0x3 302 #define DAGB0_RDCLI13__URG_HIGH__SHIFT 0x4 303 #define DAGB0_RDCLI13__URG_LOW__SHIFT 0x8 304 #define DAGB0_RDCLI13__MAX_BW_ENABLE__SHIFT 0xc 305 #define DAGB0_RDCLI13__MAX_BW__SHIFT 0xd 306 #define DAGB0_RDCLI13__MIN_BW_ENABLE__SHIFT 0x15 307 #define DAGB0_RDCLI13__MIN_BW__SHIFT 0x16 308 #define DAGB0_RDCLI13__OSD_LIMITER_ENABLE__SHIFT 0x19 309 #define DAGB0_RDCLI13__MAX_OSD__SHIFT 0x1a 310 #define DAGB0_RDCLI13__VIRT_CHAN_MASK 0x00000007L 311 #define DAGB0_RDCLI13__CHECK_TLB_CREDIT_MASK 0x00000008L 312 #define DAGB0_RDCLI13__URG_HIGH_MASK 0x000000F0L 313 #define DAGB0_RDCLI13__URG_LOW_MASK 0x00000F00L 314 #define DAGB0_RDCLI13__MAX_BW_ENABLE_MASK 0x00001000L 315 #define DAGB0_RDCLI13__MAX_BW_MASK 0x001FE000L 316 #define DAGB0_RDCLI13__MIN_BW_ENABLE_MASK 0x00200000L 317 #define DAGB0_RDCLI13__MIN_BW_MASK 0x01C00000L 318 #define DAGB0_RDCLI13__OSD_LIMITER_ENABLE_MASK 0x02000000L 319 #define DAGB0_RDCLI13__MAX_OSD_MASK 0xFC000000L 320 //DAGB0_RDCLI14 321 #define DAGB0_RDCLI14__VIRT_CHAN__SHIFT 0x0 322 #define DAGB0_RDCLI14__CHECK_TLB_CREDIT__SHIFT 0x3 323 #define DAGB0_RDCLI14__URG_HIGH__SHIFT 0x4 324 #define DAGB0_RDCLI14__URG_LOW__SHIFT 0x8 325 #define DAGB0_RDCLI14__MAX_BW_ENABLE__SHIFT 0xc 326 #define DAGB0_RDCLI14__MAX_BW__SHIFT 0xd 327 #define DAGB0_RDCLI14__MIN_BW_ENABLE__SHIFT 0x15 328 #define DAGB0_RDCLI14__MIN_BW__SHIFT 0x16 329 #define DAGB0_RDCLI14__OSD_LIMITER_ENABLE__SHIFT 0x19 330 #define DAGB0_RDCLI14__MAX_OSD__SHIFT 0x1a 331 #define DAGB0_RDCLI14__VIRT_CHAN_MASK 0x00000007L 332 #define DAGB0_RDCLI14__CHECK_TLB_CREDIT_MASK 0x00000008L 333 #define DAGB0_RDCLI14__URG_HIGH_MASK 0x000000F0L 334 #define DAGB0_RDCLI14__URG_LOW_MASK 0x00000F00L 335 #define DAGB0_RDCLI14__MAX_BW_ENABLE_MASK 0x00001000L 336 #define DAGB0_RDCLI14__MAX_BW_MASK 0x001FE000L 337 #define DAGB0_RDCLI14__MIN_BW_ENABLE_MASK 0x00200000L 338 #define DAGB0_RDCLI14__MIN_BW_MASK 0x01C00000L 339 #define DAGB0_RDCLI14__OSD_LIMITER_ENABLE_MASK 0x02000000L 340 #define DAGB0_RDCLI14__MAX_OSD_MASK 0xFC000000L 341 //DAGB0_RDCLI15 342 #define DAGB0_RDCLI15__VIRT_CHAN__SHIFT 0x0 343 #define DAGB0_RDCLI15__CHECK_TLB_CREDIT__SHIFT 0x3 344 #define DAGB0_RDCLI15__URG_HIGH__SHIFT 0x4 345 #define DAGB0_RDCLI15__URG_LOW__SHIFT 0x8 346 #define DAGB0_RDCLI15__MAX_BW_ENABLE__SHIFT 0xc 347 #define DAGB0_RDCLI15__MAX_BW__SHIFT 0xd 348 #define DAGB0_RDCLI15__MIN_BW_ENABLE__SHIFT 0x15 349 #define DAGB0_RDCLI15__MIN_BW__SHIFT 0x16 350 #define DAGB0_RDCLI15__OSD_LIMITER_ENABLE__SHIFT 0x19 351 #define DAGB0_RDCLI15__MAX_OSD__SHIFT 0x1a 352 #define DAGB0_RDCLI15__VIRT_CHAN_MASK 0x00000007L 353 #define DAGB0_RDCLI15__CHECK_TLB_CREDIT_MASK 0x00000008L 354 #define DAGB0_RDCLI15__URG_HIGH_MASK 0x000000F0L 355 #define DAGB0_RDCLI15__URG_LOW_MASK 0x00000F00L 356 #define DAGB0_RDCLI15__MAX_BW_ENABLE_MASK 0x00001000L 357 #define DAGB0_RDCLI15__MAX_BW_MASK 0x001FE000L 358 #define DAGB0_RDCLI15__MIN_BW_ENABLE_MASK 0x00200000L 359 #define DAGB0_RDCLI15__MIN_BW_MASK 0x01C00000L 360 #define DAGB0_RDCLI15__OSD_LIMITER_ENABLE_MASK 0x02000000L 361 #define DAGB0_RDCLI15__MAX_OSD_MASK 0xFC000000L 362 //DAGB0_RDCLI16 363 #define DAGB0_RDCLI16__VIRT_CHAN__SHIFT 0x0 364 #define DAGB0_RDCLI16__CHECK_TLB_CREDIT__SHIFT 0x3 365 #define DAGB0_RDCLI16__URG_HIGH__SHIFT 0x4 366 #define DAGB0_RDCLI16__URG_LOW__SHIFT 0x8 367 #define DAGB0_RDCLI16__MAX_BW_ENABLE__SHIFT 0xc 368 #define DAGB0_RDCLI16__MAX_BW__SHIFT 0xd 369 #define DAGB0_RDCLI16__MIN_BW_ENABLE__SHIFT 0x15 370 #define DAGB0_RDCLI16__MIN_BW__SHIFT 0x16 371 #define DAGB0_RDCLI16__OSD_LIMITER_ENABLE__SHIFT 0x19 372 #define DAGB0_RDCLI16__MAX_OSD__SHIFT 0x1a 373 #define DAGB0_RDCLI16__VIRT_CHAN_MASK 0x00000007L 374 #define DAGB0_RDCLI16__CHECK_TLB_CREDIT_MASK 0x00000008L 375 #define DAGB0_RDCLI16__URG_HIGH_MASK 0x000000F0L 376 #define DAGB0_RDCLI16__URG_LOW_MASK 0x00000F00L 377 #define DAGB0_RDCLI16__MAX_BW_ENABLE_MASK 0x00001000L 378 #define DAGB0_RDCLI16__MAX_BW_MASK 0x001FE000L 379 #define DAGB0_RDCLI16__MIN_BW_ENABLE_MASK 0x00200000L 380 #define DAGB0_RDCLI16__MIN_BW_MASK 0x01C00000L 381 #define DAGB0_RDCLI16__OSD_LIMITER_ENABLE_MASK 0x02000000L 382 #define DAGB0_RDCLI16__MAX_OSD_MASK 0xFC000000L 383 //DAGB0_RDCLI17 384 #define DAGB0_RDCLI17__VIRT_CHAN__SHIFT 0x0 385 #define DAGB0_RDCLI17__CHECK_TLB_CREDIT__SHIFT 0x3 386 #define DAGB0_RDCLI17__URG_HIGH__SHIFT 0x4 387 #define DAGB0_RDCLI17__URG_LOW__SHIFT 0x8 388 #define DAGB0_RDCLI17__MAX_BW_ENABLE__SHIFT 0xc 389 #define DAGB0_RDCLI17__MAX_BW__SHIFT 0xd 390 #define DAGB0_RDCLI17__MIN_BW_ENABLE__SHIFT 0x15 391 #define DAGB0_RDCLI17__MIN_BW__SHIFT 0x16 392 #define DAGB0_RDCLI17__OSD_LIMITER_ENABLE__SHIFT 0x19 393 #define DAGB0_RDCLI17__MAX_OSD__SHIFT 0x1a 394 #define DAGB0_RDCLI17__VIRT_CHAN_MASK 0x00000007L 395 #define DAGB0_RDCLI17__CHECK_TLB_CREDIT_MASK 0x00000008L 396 #define DAGB0_RDCLI17__URG_HIGH_MASK 0x000000F0L 397 #define DAGB0_RDCLI17__URG_LOW_MASK 0x00000F00L 398 #define DAGB0_RDCLI17__MAX_BW_ENABLE_MASK 0x00001000L 399 #define DAGB0_RDCLI17__MAX_BW_MASK 0x001FE000L 400 #define DAGB0_RDCLI17__MIN_BW_ENABLE_MASK 0x00200000L 401 #define DAGB0_RDCLI17__MIN_BW_MASK 0x01C00000L 402 #define DAGB0_RDCLI17__OSD_LIMITER_ENABLE_MASK 0x02000000L 403 #define DAGB0_RDCLI17__MAX_OSD_MASK 0xFC000000L 404 //DAGB0_RDCLI18 405 #define DAGB0_RDCLI18__VIRT_CHAN__SHIFT 0x0 406 #define DAGB0_RDCLI18__CHECK_TLB_CREDIT__SHIFT 0x3 407 #define DAGB0_RDCLI18__URG_HIGH__SHIFT 0x4 408 #define DAGB0_RDCLI18__URG_LOW__SHIFT 0x8 409 #define DAGB0_RDCLI18__MAX_BW_ENABLE__SHIFT 0xc 410 #define DAGB0_RDCLI18__MAX_BW__SHIFT 0xd 411 #define DAGB0_RDCLI18__MIN_BW_ENABLE__SHIFT 0x15 412 #define DAGB0_RDCLI18__MIN_BW__SHIFT 0x16 413 #define DAGB0_RDCLI18__OSD_LIMITER_ENABLE__SHIFT 0x19 414 #define DAGB0_RDCLI18__MAX_OSD__SHIFT 0x1a 415 #define DAGB0_RDCLI18__VIRT_CHAN_MASK 0x00000007L 416 #define DAGB0_RDCLI18__CHECK_TLB_CREDIT_MASK 0x00000008L 417 #define DAGB0_RDCLI18__URG_HIGH_MASK 0x000000F0L 418 #define DAGB0_RDCLI18__URG_LOW_MASK 0x00000F00L 419 #define DAGB0_RDCLI18__MAX_BW_ENABLE_MASK 0x00001000L 420 #define DAGB0_RDCLI18__MAX_BW_MASK 0x001FE000L 421 #define DAGB0_RDCLI18__MIN_BW_ENABLE_MASK 0x00200000L 422 #define DAGB0_RDCLI18__MIN_BW_MASK 0x01C00000L 423 #define DAGB0_RDCLI18__OSD_LIMITER_ENABLE_MASK 0x02000000L 424 #define DAGB0_RDCLI18__MAX_OSD_MASK 0xFC000000L 425 //DAGB0_RDCLI19 426 #define DAGB0_RDCLI19__VIRT_CHAN__SHIFT 0x0 427 #define DAGB0_RDCLI19__CHECK_TLB_CREDIT__SHIFT 0x3 428 #define DAGB0_RDCLI19__URG_HIGH__SHIFT 0x4 429 #define DAGB0_RDCLI19__URG_LOW__SHIFT 0x8 430 #define DAGB0_RDCLI19__MAX_BW_ENABLE__SHIFT 0xc 431 #define DAGB0_RDCLI19__MAX_BW__SHIFT 0xd 432 #define DAGB0_RDCLI19__MIN_BW_ENABLE__SHIFT 0x15 433 #define DAGB0_RDCLI19__MIN_BW__SHIFT 0x16 434 #define DAGB0_RDCLI19__OSD_LIMITER_ENABLE__SHIFT 0x19 435 #define DAGB0_RDCLI19__MAX_OSD__SHIFT 0x1a 436 #define DAGB0_RDCLI19__VIRT_CHAN_MASK 0x00000007L 437 #define DAGB0_RDCLI19__CHECK_TLB_CREDIT_MASK 0x00000008L 438 #define DAGB0_RDCLI19__URG_HIGH_MASK 0x000000F0L 439 #define DAGB0_RDCLI19__URG_LOW_MASK 0x00000F00L 440 #define DAGB0_RDCLI19__MAX_BW_ENABLE_MASK 0x00001000L 441 #define DAGB0_RDCLI19__MAX_BW_MASK 0x001FE000L 442 #define DAGB0_RDCLI19__MIN_BW_ENABLE_MASK 0x00200000L 443 #define DAGB0_RDCLI19__MIN_BW_MASK 0x01C00000L 444 #define DAGB0_RDCLI19__OSD_LIMITER_ENABLE_MASK 0x02000000L 445 #define DAGB0_RDCLI19__MAX_OSD_MASK 0xFC000000L 446 //DAGB0_RDCLI20 447 #define DAGB0_RDCLI20__VIRT_CHAN__SHIFT 0x0 448 #define DAGB0_RDCLI20__CHECK_TLB_CREDIT__SHIFT 0x3 449 #define DAGB0_RDCLI20__URG_HIGH__SHIFT 0x4 450 #define DAGB0_RDCLI20__URG_LOW__SHIFT 0x8 451 #define DAGB0_RDCLI20__MAX_BW_ENABLE__SHIFT 0xc 452 #define DAGB0_RDCLI20__MAX_BW__SHIFT 0xd 453 #define DAGB0_RDCLI20__MIN_BW_ENABLE__SHIFT 0x15 454 #define DAGB0_RDCLI20__MIN_BW__SHIFT 0x16 455 #define DAGB0_RDCLI20__OSD_LIMITER_ENABLE__SHIFT 0x19 456 #define DAGB0_RDCLI20__MAX_OSD__SHIFT 0x1a 457 #define DAGB0_RDCLI20__VIRT_CHAN_MASK 0x00000007L 458 #define DAGB0_RDCLI20__CHECK_TLB_CREDIT_MASK 0x00000008L 459 #define DAGB0_RDCLI20__URG_HIGH_MASK 0x000000F0L 460 #define DAGB0_RDCLI20__URG_LOW_MASK 0x00000F00L 461 #define DAGB0_RDCLI20__MAX_BW_ENABLE_MASK 0x00001000L 462 #define DAGB0_RDCLI20__MAX_BW_MASK 0x001FE000L 463 #define DAGB0_RDCLI20__MIN_BW_ENABLE_MASK 0x00200000L 464 #define DAGB0_RDCLI20__MIN_BW_MASK 0x01C00000L 465 #define DAGB0_RDCLI20__OSD_LIMITER_ENABLE_MASK 0x02000000L 466 #define DAGB0_RDCLI20__MAX_OSD_MASK 0xFC000000L 467 //DAGB0_RDCLI21 468 #define DAGB0_RDCLI21__VIRT_CHAN__SHIFT 0x0 469 #define DAGB0_RDCLI21__CHECK_TLB_CREDIT__SHIFT 0x3 470 #define DAGB0_RDCLI21__URG_HIGH__SHIFT 0x4 471 #define DAGB0_RDCLI21__URG_LOW__SHIFT 0x8 472 #define DAGB0_RDCLI21__MAX_BW_ENABLE__SHIFT 0xc 473 #define DAGB0_RDCLI21__MAX_BW__SHIFT 0xd 474 #define DAGB0_RDCLI21__MIN_BW_ENABLE__SHIFT 0x15 475 #define DAGB0_RDCLI21__MIN_BW__SHIFT 0x16 476 #define DAGB0_RDCLI21__OSD_LIMITER_ENABLE__SHIFT 0x19 477 #define DAGB0_RDCLI21__MAX_OSD__SHIFT 0x1a 478 #define DAGB0_RDCLI21__VIRT_CHAN_MASK 0x00000007L 479 #define DAGB0_RDCLI21__CHECK_TLB_CREDIT_MASK 0x00000008L 480 #define DAGB0_RDCLI21__URG_HIGH_MASK 0x000000F0L 481 #define DAGB0_RDCLI21__URG_LOW_MASK 0x00000F00L 482 #define DAGB0_RDCLI21__MAX_BW_ENABLE_MASK 0x00001000L 483 #define DAGB0_RDCLI21__MAX_BW_MASK 0x001FE000L 484 #define DAGB0_RDCLI21__MIN_BW_ENABLE_MASK 0x00200000L 485 #define DAGB0_RDCLI21__MIN_BW_MASK 0x01C00000L 486 #define DAGB0_RDCLI21__OSD_LIMITER_ENABLE_MASK 0x02000000L 487 #define DAGB0_RDCLI21__MAX_OSD_MASK 0xFC000000L 488 //DAGB0_RDCLI22 489 #define DAGB0_RDCLI22__VIRT_CHAN__SHIFT 0x0 490 #define DAGB0_RDCLI22__CHECK_TLB_CREDIT__SHIFT 0x3 491 #define DAGB0_RDCLI22__URG_HIGH__SHIFT 0x4 492 #define DAGB0_RDCLI22__URG_LOW__SHIFT 0x8 493 #define DAGB0_RDCLI22__MAX_BW_ENABLE__SHIFT 0xc 494 #define DAGB0_RDCLI22__MAX_BW__SHIFT 0xd 495 #define DAGB0_RDCLI22__MIN_BW_ENABLE__SHIFT 0x15 496 #define DAGB0_RDCLI22__MIN_BW__SHIFT 0x16 497 #define DAGB0_RDCLI22__OSD_LIMITER_ENABLE__SHIFT 0x19 498 #define DAGB0_RDCLI22__MAX_OSD__SHIFT 0x1a 499 #define DAGB0_RDCLI22__VIRT_CHAN_MASK 0x00000007L 500 #define DAGB0_RDCLI22__CHECK_TLB_CREDIT_MASK 0x00000008L 501 #define DAGB0_RDCLI22__URG_HIGH_MASK 0x000000F0L 502 #define DAGB0_RDCLI22__URG_LOW_MASK 0x00000F00L 503 #define DAGB0_RDCLI22__MAX_BW_ENABLE_MASK 0x00001000L 504 #define DAGB0_RDCLI22__MAX_BW_MASK 0x001FE000L 505 #define DAGB0_RDCLI22__MIN_BW_ENABLE_MASK 0x00200000L 506 #define DAGB0_RDCLI22__MIN_BW_MASK 0x01C00000L 507 #define DAGB0_RDCLI22__OSD_LIMITER_ENABLE_MASK 0x02000000L 508 #define DAGB0_RDCLI22__MAX_OSD_MASK 0xFC000000L 509 //DAGB0_RDCLI23 510 #define DAGB0_RDCLI23__VIRT_CHAN__SHIFT 0x0 511 #define DAGB0_RDCLI23__CHECK_TLB_CREDIT__SHIFT 0x3 512 #define DAGB0_RDCLI23__URG_HIGH__SHIFT 0x4 513 #define DAGB0_RDCLI23__URG_LOW__SHIFT 0x8 514 #define DAGB0_RDCLI23__MAX_BW_ENABLE__SHIFT 0xc 515 #define DAGB0_RDCLI23__MAX_BW__SHIFT 0xd 516 #define DAGB0_RDCLI23__MIN_BW_ENABLE__SHIFT 0x15 517 #define DAGB0_RDCLI23__MIN_BW__SHIFT 0x16 518 #define DAGB0_RDCLI23__OSD_LIMITER_ENABLE__SHIFT 0x19 519 #define DAGB0_RDCLI23__MAX_OSD__SHIFT 0x1a 520 #define DAGB0_RDCLI23__VIRT_CHAN_MASK 0x00000007L 521 #define DAGB0_RDCLI23__CHECK_TLB_CREDIT_MASK 0x00000008L 522 #define DAGB0_RDCLI23__URG_HIGH_MASK 0x000000F0L 523 #define DAGB0_RDCLI23__URG_LOW_MASK 0x00000F00L 524 #define DAGB0_RDCLI23__MAX_BW_ENABLE_MASK 0x00001000L 525 #define DAGB0_RDCLI23__MAX_BW_MASK 0x001FE000L 526 #define DAGB0_RDCLI23__MIN_BW_ENABLE_MASK 0x00200000L 527 #define DAGB0_RDCLI23__MIN_BW_MASK 0x01C00000L 528 #define DAGB0_RDCLI23__OSD_LIMITER_ENABLE_MASK 0x02000000L 529 #define DAGB0_RDCLI23__MAX_OSD_MASK 0xFC000000L 530 //DAGB0_RDCLI24 531 #define DAGB0_RDCLI24__VIRT_CHAN__SHIFT 0x0 532 #define DAGB0_RDCLI24__CHECK_TLB_CREDIT__SHIFT 0x3 533 #define DAGB0_RDCLI24__URG_HIGH__SHIFT 0x4 534 #define DAGB0_RDCLI24__URG_LOW__SHIFT 0x8 535 #define DAGB0_RDCLI24__MAX_BW_ENABLE__SHIFT 0xc 536 #define DAGB0_RDCLI24__MAX_BW__SHIFT 0xd 537 #define DAGB0_RDCLI24__MIN_BW_ENABLE__SHIFT 0x15 538 #define DAGB0_RDCLI24__MIN_BW__SHIFT 0x16 539 #define DAGB0_RDCLI24__OSD_LIMITER_ENABLE__SHIFT 0x19 540 #define DAGB0_RDCLI24__MAX_OSD__SHIFT 0x1a 541 #define DAGB0_RDCLI24__VIRT_CHAN_MASK 0x00000007L 542 #define DAGB0_RDCLI24__CHECK_TLB_CREDIT_MASK 0x00000008L 543 #define DAGB0_RDCLI24__URG_HIGH_MASK 0x000000F0L 544 #define DAGB0_RDCLI24__URG_LOW_MASK 0x00000F00L 545 #define DAGB0_RDCLI24__MAX_BW_ENABLE_MASK 0x00001000L 546 #define DAGB0_RDCLI24__MAX_BW_MASK 0x001FE000L 547 #define DAGB0_RDCLI24__MIN_BW_ENABLE_MASK 0x00200000L 548 #define DAGB0_RDCLI24__MIN_BW_MASK 0x01C00000L 549 #define DAGB0_RDCLI24__OSD_LIMITER_ENABLE_MASK 0x02000000L 550 #define DAGB0_RDCLI24__MAX_OSD_MASK 0xFC000000L 551 //DAGB0_RDCLI25 552 #define DAGB0_RDCLI25__VIRT_CHAN__SHIFT 0x0 553 #define DAGB0_RDCLI25__CHECK_TLB_CREDIT__SHIFT 0x3 554 #define DAGB0_RDCLI25__URG_HIGH__SHIFT 0x4 555 #define DAGB0_RDCLI25__URG_LOW__SHIFT 0x8 556 #define DAGB0_RDCLI25__MAX_BW_ENABLE__SHIFT 0xc 557 #define DAGB0_RDCLI25__MAX_BW__SHIFT 0xd 558 #define DAGB0_RDCLI25__MIN_BW_ENABLE__SHIFT 0x15 559 #define DAGB0_RDCLI25__MIN_BW__SHIFT 0x16 560 #define DAGB0_RDCLI25__OSD_LIMITER_ENABLE__SHIFT 0x19 561 #define DAGB0_RDCLI25__MAX_OSD__SHIFT 0x1a 562 #define DAGB0_RDCLI25__VIRT_CHAN_MASK 0x00000007L 563 #define DAGB0_RDCLI25__CHECK_TLB_CREDIT_MASK 0x00000008L 564 #define DAGB0_RDCLI25__URG_HIGH_MASK 0x000000F0L 565 #define DAGB0_RDCLI25__URG_LOW_MASK 0x00000F00L 566 #define DAGB0_RDCLI25__MAX_BW_ENABLE_MASK 0x00001000L 567 #define DAGB0_RDCLI25__MAX_BW_MASK 0x001FE000L 568 #define DAGB0_RDCLI25__MIN_BW_ENABLE_MASK 0x00200000L 569 #define DAGB0_RDCLI25__MIN_BW_MASK 0x01C00000L 570 #define DAGB0_RDCLI25__OSD_LIMITER_ENABLE_MASK 0x02000000L 571 #define DAGB0_RDCLI25__MAX_OSD_MASK 0xFC000000L 572 //DAGB0_RDCLI26 573 #define DAGB0_RDCLI26__VIRT_CHAN__SHIFT 0x0 574 #define DAGB0_RDCLI26__CHECK_TLB_CREDIT__SHIFT 0x3 575 #define DAGB0_RDCLI26__URG_HIGH__SHIFT 0x4 576 #define DAGB0_RDCLI26__URG_LOW__SHIFT 0x8 577 #define DAGB0_RDCLI26__MAX_BW_ENABLE__SHIFT 0xc 578 #define DAGB0_RDCLI26__MAX_BW__SHIFT 0xd 579 #define DAGB0_RDCLI26__MIN_BW_ENABLE__SHIFT 0x15 580 #define DAGB0_RDCLI26__MIN_BW__SHIFT 0x16 581 #define DAGB0_RDCLI26__OSD_LIMITER_ENABLE__SHIFT 0x19 582 #define DAGB0_RDCLI26__MAX_OSD__SHIFT 0x1a 583 #define DAGB0_RDCLI26__VIRT_CHAN_MASK 0x00000007L 584 #define DAGB0_RDCLI26__CHECK_TLB_CREDIT_MASK 0x00000008L 585 #define DAGB0_RDCLI26__URG_HIGH_MASK 0x000000F0L 586 #define DAGB0_RDCLI26__URG_LOW_MASK 0x00000F00L 587 #define DAGB0_RDCLI26__MAX_BW_ENABLE_MASK 0x00001000L 588 #define DAGB0_RDCLI26__MAX_BW_MASK 0x001FE000L 589 #define DAGB0_RDCLI26__MIN_BW_ENABLE_MASK 0x00200000L 590 #define DAGB0_RDCLI26__MIN_BW_MASK 0x01C00000L 591 #define DAGB0_RDCLI26__OSD_LIMITER_ENABLE_MASK 0x02000000L 592 #define DAGB0_RDCLI26__MAX_OSD_MASK 0xFC000000L 593 //DAGB0_RDCLI27 594 #define DAGB0_RDCLI27__VIRT_CHAN__SHIFT 0x0 595 #define DAGB0_RDCLI27__CHECK_TLB_CREDIT__SHIFT 0x3 596 #define DAGB0_RDCLI27__URG_HIGH__SHIFT 0x4 597 #define DAGB0_RDCLI27__URG_LOW__SHIFT 0x8 598 #define DAGB0_RDCLI27__MAX_BW_ENABLE__SHIFT 0xc 599 #define DAGB0_RDCLI27__MAX_BW__SHIFT 0xd 600 #define DAGB0_RDCLI27__MIN_BW_ENABLE__SHIFT 0x15 601 #define DAGB0_RDCLI27__MIN_BW__SHIFT 0x16 602 #define DAGB0_RDCLI27__OSD_LIMITER_ENABLE__SHIFT 0x19 603 #define DAGB0_RDCLI27__MAX_OSD__SHIFT 0x1a 604 #define DAGB0_RDCLI27__VIRT_CHAN_MASK 0x00000007L 605 #define DAGB0_RDCLI27__CHECK_TLB_CREDIT_MASK 0x00000008L 606 #define DAGB0_RDCLI27__URG_HIGH_MASK 0x000000F0L 607 #define DAGB0_RDCLI27__URG_LOW_MASK 0x00000F00L 608 #define DAGB0_RDCLI27__MAX_BW_ENABLE_MASK 0x00001000L 609 #define DAGB0_RDCLI27__MAX_BW_MASK 0x001FE000L 610 #define DAGB0_RDCLI27__MIN_BW_ENABLE_MASK 0x00200000L 611 #define DAGB0_RDCLI27__MIN_BW_MASK 0x01C00000L 612 #define DAGB0_RDCLI27__OSD_LIMITER_ENABLE_MASK 0x02000000L 613 #define DAGB0_RDCLI27__MAX_OSD_MASK 0xFC000000L 614 //DAGB0_RDCLI28 615 #define DAGB0_RDCLI28__VIRT_CHAN__SHIFT 0x0 616 #define DAGB0_RDCLI28__CHECK_TLB_CREDIT__SHIFT 0x3 617 #define DAGB0_RDCLI28__URG_HIGH__SHIFT 0x4 618 #define DAGB0_RDCLI28__URG_LOW__SHIFT 0x8 619 #define DAGB0_RDCLI28__MAX_BW_ENABLE__SHIFT 0xc 620 #define DAGB0_RDCLI28__MAX_BW__SHIFT 0xd 621 #define DAGB0_RDCLI28__MIN_BW_ENABLE__SHIFT 0x15 622 #define DAGB0_RDCLI28__MIN_BW__SHIFT 0x16 623 #define DAGB0_RDCLI28__OSD_LIMITER_ENABLE__SHIFT 0x19 624 #define DAGB0_RDCLI28__MAX_OSD__SHIFT 0x1a 625 #define DAGB0_RDCLI28__VIRT_CHAN_MASK 0x00000007L 626 #define DAGB0_RDCLI28__CHECK_TLB_CREDIT_MASK 0x00000008L 627 #define DAGB0_RDCLI28__URG_HIGH_MASK 0x000000F0L 628 #define DAGB0_RDCLI28__URG_LOW_MASK 0x00000F00L 629 #define DAGB0_RDCLI28__MAX_BW_ENABLE_MASK 0x00001000L 630 #define DAGB0_RDCLI28__MAX_BW_MASK 0x001FE000L 631 #define DAGB0_RDCLI28__MIN_BW_ENABLE_MASK 0x00200000L 632 #define DAGB0_RDCLI28__MIN_BW_MASK 0x01C00000L 633 #define DAGB0_RDCLI28__OSD_LIMITER_ENABLE_MASK 0x02000000L 634 #define DAGB0_RDCLI28__MAX_OSD_MASK 0xFC000000L 635 //DAGB0_RDCLI29 636 #define DAGB0_RDCLI29__VIRT_CHAN__SHIFT 0x0 637 #define DAGB0_RDCLI29__CHECK_TLB_CREDIT__SHIFT 0x3 638 #define DAGB0_RDCLI29__URG_HIGH__SHIFT 0x4 639 #define DAGB0_RDCLI29__URG_LOW__SHIFT 0x8 640 #define DAGB0_RDCLI29__MAX_BW_ENABLE__SHIFT 0xc 641 #define DAGB0_RDCLI29__MAX_BW__SHIFT 0xd 642 #define DAGB0_RDCLI29__MIN_BW_ENABLE__SHIFT 0x15 643 #define DAGB0_RDCLI29__MIN_BW__SHIFT 0x16 644 #define DAGB0_RDCLI29__OSD_LIMITER_ENABLE__SHIFT 0x19 645 #define DAGB0_RDCLI29__MAX_OSD__SHIFT 0x1a 646 #define DAGB0_RDCLI29__VIRT_CHAN_MASK 0x00000007L 647 #define DAGB0_RDCLI29__CHECK_TLB_CREDIT_MASK 0x00000008L 648 #define DAGB0_RDCLI29__URG_HIGH_MASK 0x000000F0L 649 #define DAGB0_RDCLI29__URG_LOW_MASK 0x00000F00L 650 #define DAGB0_RDCLI29__MAX_BW_ENABLE_MASK 0x00001000L 651 #define DAGB0_RDCLI29__MAX_BW_MASK 0x001FE000L 652 #define DAGB0_RDCLI29__MIN_BW_ENABLE_MASK 0x00200000L 653 #define DAGB0_RDCLI29__MIN_BW_MASK 0x01C00000L 654 #define DAGB0_RDCLI29__OSD_LIMITER_ENABLE_MASK 0x02000000L 655 #define DAGB0_RDCLI29__MAX_OSD_MASK 0xFC000000L 656 //DAGB0_RDCLI30 657 #define DAGB0_RDCLI30__VIRT_CHAN__SHIFT 0x0 658 #define DAGB0_RDCLI30__CHECK_TLB_CREDIT__SHIFT 0x3 659 #define DAGB0_RDCLI30__URG_HIGH__SHIFT 0x4 660 #define DAGB0_RDCLI30__URG_LOW__SHIFT 0x8 661 #define DAGB0_RDCLI30__MAX_BW_ENABLE__SHIFT 0xc 662 #define DAGB0_RDCLI30__MAX_BW__SHIFT 0xd 663 #define DAGB0_RDCLI30__MIN_BW_ENABLE__SHIFT 0x15 664 #define DAGB0_RDCLI30__MIN_BW__SHIFT 0x16 665 #define DAGB0_RDCLI30__OSD_LIMITER_ENABLE__SHIFT 0x19 666 #define DAGB0_RDCLI30__MAX_OSD__SHIFT 0x1a 667 #define DAGB0_RDCLI30__VIRT_CHAN_MASK 0x00000007L 668 #define DAGB0_RDCLI30__CHECK_TLB_CREDIT_MASK 0x00000008L 669 #define DAGB0_RDCLI30__URG_HIGH_MASK 0x000000F0L 670 #define DAGB0_RDCLI30__URG_LOW_MASK 0x00000F00L 671 #define DAGB0_RDCLI30__MAX_BW_ENABLE_MASK 0x00001000L 672 #define DAGB0_RDCLI30__MAX_BW_MASK 0x001FE000L 673 #define DAGB0_RDCLI30__MIN_BW_ENABLE_MASK 0x00200000L 674 #define DAGB0_RDCLI30__MIN_BW_MASK 0x01C00000L 675 #define DAGB0_RDCLI30__OSD_LIMITER_ENABLE_MASK 0x02000000L 676 #define DAGB0_RDCLI30__MAX_OSD_MASK 0xFC000000L 677 //DAGB0_RD_CNTL 678 #define DAGB0_RD_CNTL__SCLK_FREQ__SHIFT 0x0 679 #define DAGB0_RD_CNTL__CLI_MAX_BW_WINDOW__SHIFT 0x4 680 #define DAGB0_RD_CNTL__VC_MAX_BW_WINDOW__SHIFT 0xa 681 #define DAGB0_RD_CNTL__IO_LEVEL_OVERRIDE_ENABLE__SHIFT 0x10 682 #define DAGB0_RD_CNTL__IO_LEVEL__SHIFT 0x11 683 #define DAGB0_RD_CNTL__IO_LEVEL_COMPLY_VC__SHIFT 0x14 684 #define DAGB0_RD_CNTL__SHARE_VC_NUM__SHIFT 0x17 685 #define DAGB0_RD_CNTL__SCLK_FREQ_MASK 0x0000000FL 686 #define DAGB0_RD_CNTL__CLI_MAX_BW_WINDOW_MASK 0x000003F0L 687 #define DAGB0_RD_CNTL__VC_MAX_BW_WINDOW_MASK 0x0000FC00L 688 #define DAGB0_RD_CNTL__IO_LEVEL_OVERRIDE_ENABLE_MASK 0x00010000L 689 #define DAGB0_RD_CNTL__IO_LEVEL_MASK 0x000E0000L 690 #define DAGB0_RD_CNTL__IO_LEVEL_COMPLY_VC_MASK 0x00700000L 691 #define DAGB0_RD_CNTL__SHARE_VC_NUM_MASK 0x03800000L 692 //DAGB0_RD_GMI_CNTL 693 #define DAGB0_RD_GMI_CNTL__EA_CREDIT__SHIFT 0x0 694 #define DAGB0_RD_GMI_CNTL__LEVEL__SHIFT 0x6 695 #define DAGB0_RD_GMI_CNTL__MAX_BURST__SHIFT 0x9 696 #define DAGB0_RD_GMI_CNTL__LAZY_TIMER__SHIFT 0xd 697 #define DAGB0_RD_GMI_CNTL__EA_CREDIT_MASK 0x0000003FL 698 #define DAGB0_RD_GMI_CNTL__LEVEL_MASK 0x000001C0L 699 #define DAGB0_RD_GMI_CNTL__MAX_BURST_MASK 0x00001E00L 700 #define DAGB0_RD_GMI_CNTL__LAZY_TIMER_MASK 0x0001E000L 701 //DAGB0_RD_ADDR_DAGB 702 #define DAGB0_RD_ADDR_DAGB__DAGB_ENABLE__SHIFT 0x0 703 #define DAGB0_RD_ADDR_DAGB__ENABLE_JUMP_AHEAD__SHIFT 0x3 704 #define DAGB0_RD_ADDR_DAGB__DISABLE_SELF_INIT__SHIFT 0x6 705 #define DAGB0_RD_ADDR_DAGB__WHOAMI__SHIFT 0x7 706 #define DAGB0_RD_ADDR_DAGB__JUMP_MODE__SHIFT 0xd 707 #define DAGB0_RD_ADDR_DAGB__DAGB_ENABLE_MASK 0x00000007L 708 #define DAGB0_RD_ADDR_DAGB__ENABLE_JUMP_AHEAD_MASK 0x00000038L 709 #define DAGB0_RD_ADDR_DAGB__DISABLE_SELF_INIT_MASK 0x00000040L 710 #define DAGB0_RD_ADDR_DAGB__WHOAMI_MASK 0x00001F80L 711 #define DAGB0_RD_ADDR_DAGB__JUMP_MODE_MASK 0x00002000L 712 //DAGB0_RD_OUTPUT_DAGB_MAX_BURST 713 #define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC0__SHIFT 0x0 714 #define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC1__SHIFT 0x4 715 #define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC2__SHIFT 0x8 716 #define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC3__SHIFT 0xc 717 #define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC4__SHIFT 0x10 718 #define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC5__SHIFT 0x14 719 #define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC6__SHIFT 0x18 720 #define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC7__SHIFT 0x1c 721 #define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC0_MASK 0x0000000FL 722 #define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC1_MASK 0x000000F0L 723 #define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC2_MASK 0x00000F00L 724 #define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC3_MASK 0x0000F000L 725 #define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC4_MASK 0x000F0000L 726 #define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC5_MASK 0x00F00000L 727 #define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC6_MASK 0x0F000000L 728 #define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC7_MASK 0xF0000000L 729 //DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER 730 #define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC0__SHIFT 0x0 731 #define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC1__SHIFT 0x4 732 #define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC2__SHIFT 0x8 733 #define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC3__SHIFT 0xc 734 #define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC4__SHIFT 0x10 735 #define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC5__SHIFT 0x14 736 #define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC6__SHIFT 0x18 737 #define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC7__SHIFT 0x1c 738 #define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC0_MASK 0x0000000FL 739 #define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC1_MASK 0x000000F0L 740 #define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC2_MASK 0x00000F00L 741 #define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC3_MASK 0x0000F000L 742 #define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC4_MASK 0x000F0000L 743 #define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC5_MASK 0x00F00000L 744 #define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC6_MASK 0x0F000000L 745 #define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC7_MASK 0xF0000000L 746 //DAGB0_RD_CGTT_CLK_CTRL 747 #define DAGB0_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 748 #define DAGB0_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 749 #define DAGB0_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16 750 #define DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b 751 #define DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c 752 #define DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d 753 #define DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e 754 #define DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f 755 #define DAGB0_RD_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL 756 #define DAGB0_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L 757 #define DAGB0_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L 758 #define DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L 759 #define DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L 760 #define DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L 761 #define DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L 762 #define DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L 763 //DAGB0_L1TLB_RD_CGTT_CLK_CTRL 764 #define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 765 #define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 766 #define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16 767 #define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b 768 #define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c 769 #define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d 770 #define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e 771 #define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f 772 #define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL 773 #define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L 774 #define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L 775 #define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L 776 #define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L 777 #define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L 778 #define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L 779 #define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L 780 //DAGB0_ATCVM_RD_CGTT_CLK_CTRL 781 #define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 782 #define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 783 #define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16 784 #define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b 785 #define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c 786 #define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d 787 #define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e 788 #define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f 789 #define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL 790 #define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L 791 #define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L 792 #define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L 793 #define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L 794 #define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L 795 #define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L 796 #define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L 797 //DAGB0_RD_ADDR_DAGB_MAX_BURST0 798 #define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT0__SHIFT 0x0 799 #define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT1__SHIFT 0x4 800 #define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT2__SHIFT 0x8 801 #define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT3__SHIFT 0xc 802 #define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT4__SHIFT 0x10 803 #define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT5__SHIFT 0x14 804 #define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT6__SHIFT 0x18 805 #define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT7__SHIFT 0x1c 806 #define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT0_MASK 0x0000000FL 807 #define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT1_MASK 0x000000F0L 808 #define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT2_MASK 0x00000F00L 809 #define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT3_MASK 0x0000F000L 810 #define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT4_MASK 0x000F0000L 811 #define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT5_MASK 0x00F00000L 812 #define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT6_MASK 0x0F000000L 813 #define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT7_MASK 0xF0000000L 814 //DAGB0_RD_ADDR_DAGB_LAZY_TIMER0 815 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT0__SHIFT 0x0 816 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT1__SHIFT 0x4 817 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT2__SHIFT 0x8 818 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT3__SHIFT 0xc 819 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT4__SHIFT 0x10 820 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT5__SHIFT 0x14 821 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT6__SHIFT 0x18 822 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT7__SHIFT 0x1c 823 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT0_MASK 0x0000000FL 824 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT1_MASK 0x000000F0L 825 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT2_MASK 0x00000F00L 826 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT3_MASK 0x0000F000L 827 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT4_MASK 0x000F0000L 828 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT5_MASK 0x00F00000L 829 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT6_MASK 0x0F000000L 830 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT7_MASK 0xF0000000L 831 //DAGB0_RD_ADDR_DAGB_MAX_BURST1 832 #define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT8__SHIFT 0x0 833 #define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT9__SHIFT 0x4 834 #define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT10__SHIFT 0x8 835 #define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT11__SHIFT 0xc 836 #define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT12__SHIFT 0x10 837 #define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT13__SHIFT 0x14 838 #define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT14__SHIFT 0x18 839 #define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT15__SHIFT 0x1c 840 #define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT8_MASK 0x0000000FL 841 #define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT9_MASK 0x000000F0L 842 #define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT10_MASK 0x00000F00L 843 #define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT11_MASK 0x0000F000L 844 #define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT12_MASK 0x000F0000L 845 #define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT13_MASK 0x00F00000L 846 #define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT14_MASK 0x0F000000L 847 #define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT15_MASK 0xF0000000L 848 //DAGB0_RD_ADDR_DAGB_LAZY_TIMER1 849 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT8__SHIFT 0x0 850 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT9__SHIFT 0x4 851 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT10__SHIFT 0x8 852 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT11__SHIFT 0xc 853 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT12__SHIFT 0x10 854 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT13__SHIFT 0x14 855 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT14__SHIFT 0x18 856 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT15__SHIFT 0x1c 857 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT8_MASK 0x0000000FL 858 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT9_MASK 0x000000F0L 859 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT10_MASK 0x00000F00L 860 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT11_MASK 0x0000F000L 861 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT12_MASK 0x000F0000L 862 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT13_MASK 0x00F00000L 863 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT14_MASK 0x0F000000L 864 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT15_MASK 0xF0000000L 865 //DAGB0_RD_ADDR_DAGB_MAX_BURST2 866 #define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT16__SHIFT 0x0 867 #define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT17__SHIFT 0x4 868 #define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT18__SHIFT 0x8 869 #define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT19__SHIFT 0xc 870 #define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT20__SHIFT 0x10 871 #define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT21__SHIFT 0x14 872 #define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT22__SHIFT 0x18 873 #define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT23__SHIFT 0x1c 874 #define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT16_MASK 0x0000000FL 875 #define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT17_MASK 0x000000F0L 876 #define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT18_MASK 0x00000F00L 877 #define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT19_MASK 0x0000F000L 878 #define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT20_MASK 0x000F0000L 879 #define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT21_MASK 0x00F00000L 880 #define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT22_MASK 0x0F000000L 881 #define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT23_MASK 0xF0000000L 882 //DAGB0_RD_ADDR_DAGB_LAZY_TIMER2 883 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT16__SHIFT 0x0 884 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT17__SHIFT 0x4 885 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT18__SHIFT 0x8 886 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT19__SHIFT 0xc 887 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT20__SHIFT 0x10 888 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT21__SHIFT 0x14 889 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT22__SHIFT 0x18 890 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT23__SHIFT 0x1c 891 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT16_MASK 0x0000000FL 892 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT17_MASK 0x000000F0L 893 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT18_MASK 0x00000F00L 894 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT19_MASK 0x0000F000L 895 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT20_MASK 0x000F0000L 896 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT21_MASK 0x00F00000L 897 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT22_MASK 0x0F000000L 898 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT23_MASK 0xF0000000L 899 //DAGB0_RD_ADDR_DAGB_MAX_BURST3 900 #define DAGB0_RD_ADDR_DAGB_MAX_BURST3__CLIENT24__SHIFT 0x0 901 #define DAGB0_RD_ADDR_DAGB_MAX_BURST3__CLIENT25__SHIFT 0x4 902 #define DAGB0_RD_ADDR_DAGB_MAX_BURST3__CLIENT26__SHIFT 0x8 903 #define DAGB0_RD_ADDR_DAGB_MAX_BURST3__CLIENT27__SHIFT 0xc 904 #define DAGB0_RD_ADDR_DAGB_MAX_BURST3__CLIENT28__SHIFT 0x10 905 #define DAGB0_RD_ADDR_DAGB_MAX_BURST3__CLIENT29__SHIFT 0x14 906 #define DAGB0_RD_ADDR_DAGB_MAX_BURST3__CLIENT30__SHIFT 0x18 907 #define DAGB0_RD_ADDR_DAGB_MAX_BURST3__CLIENT31__SHIFT 0x1c 908 #define DAGB0_RD_ADDR_DAGB_MAX_BURST3__CLIENT24_MASK 0x0000000FL 909 #define DAGB0_RD_ADDR_DAGB_MAX_BURST3__CLIENT25_MASK 0x000000F0L 910 #define DAGB0_RD_ADDR_DAGB_MAX_BURST3__CLIENT26_MASK 0x00000F00L 911 #define DAGB0_RD_ADDR_DAGB_MAX_BURST3__CLIENT27_MASK 0x0000F000L 912 #define DAGB0_RD_ADDR_DAGB_MAX_BURST3__CLIENT28_MASK 0x000F0000L 913 #define DAGB0_RD_ADDR_DAGB_MAX_BURST3__CLIENT29_MASK 0x00F00000L 914 #define DAGB0_RD_ADDR_DAGB_MAX_BURST3__CLIENT30_MASK 0x0F000000L 915 #define DAGB0_RD_ADDR_DAGB_MAX_BURST3__CLIENT31_MASK 0xF0000000L 916 //DAGB0_RD_ADDR_DAGB_LAZY_TIMER3 917 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER3__CLIENT24__SHIFT 0x0 918 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER3__CLIENT25__SHIFT 0x4 919 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER3__CLIENT26__SHIFT 0x8 920 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER3__CLIENT27__SHIFT 0xc 921 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER3__CLIENT28__SHIFT 0x10 922 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER3__CLIENT29__SHIFT 0x14 923 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER3__CLIENT30__SHIFT 0x18 924 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER3__CLIENT31__SHIFT 0x1c 925 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER3__CLIENT24_MASK 0x0000000FL 926 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER3__CLIENT25_MASK 0x000000F0L 927 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER3__CLIENT26_MASK 0x00000F00L 928 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER3__CLIENT27_MASK 0x0000F000L 929 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER3__CLIENT28_MASK 0x000F0000L 930 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER3__CLIENT29_MASK 0x00F00000L 931 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER3__CLIENT30_MASK 0x0F000000L 932 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER3__CLIENT31_MASK 0xF0000000L 933 //DAGB0_RD_VC0_CNTL 934 #define DAGB0_RD_VC0_CNTL__STOR_CREDIT__SHIFT 0x0 935 #define DAGB0_RD_VC0_CNTL__EA_CREDIT__SHIFT 0x5 936 #define DAGB0_RD_VC0_CNTL__MAX_BW_ENABLE__SHIFT 0xb 937 #define DAGB0_RD_VC0_CNTL__MAX_BW__SHIFT 0xc 938 #define DAGB0_RD_VC0_CNTL__MIN_BW_ENABLE__SHIFT 0x14 939 #define DAGB0_RD_VC0_CNTL__MIN_BW__SHIFT 0x15 940 #define DAGB0_RD_VC0_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 941 #define DAGB0_RD_VC0_CNTL__MAX_OSD__SHIFT 0x19 942 #define DAGB0_RD_VC0_CNTL__STOR_CREDIT_MASK 0x0000001FL 943 #define DAGB0_RD_VC0_CNTL__EA_CREDIT_MASK 0x000007E0L 944 #define DAGB0_RD_VC0_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 945 #define DAGB0_RD_VC0_CNTL__MAX_BW_MASK 0x000FF000L 946 #define DAGB0_RD_VC0_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 947 #define DAGB0_RD_VC0_CNTL__MIN_BW_MASK 0x00E00000L 948 #define DAGB0_RD_VC0_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 949 #define DAGB0_RD_VC0_CNTL__MAX_OSD_MASK 0xFE000000L 950 //DAGB0_RD_VC1_CNTL 951 #define DAGB0_RD_VC1_CNTL__STOR_CREDIT__SHIFT 0x0 952 #define DAGB0_RD_VC1_CNTL__EA_CREDIT__SHIFT 0x5 953 #define DAGB0_RD_VC1_CNTL__MAX_BW_ENABLE__SHIFT 0xb 954 #define DAGB0_RD_VC1_CNTL__MAX_BW__SHIFT 0xc 955 #define DAGB0_RD_VC1_CNTL__MIN_BW_ENABLE__SHIFT 0x14 956 #define DAGB0_RD_VC1_CNTL__MIN_BW__SHIFT 0x15 957 #define DAGB0_RD_VC1_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 958 #define DAGB0_RD_VC1_CNTL__MAX_OSD__SHIFT 0x19 959 #define DAGB0_RD_VC1_CNTL__STOR_CREDIT_MASK 0x0000001FL 960 #define DAGB0_RD_VC1_CNTL__EA_CREDIT_MASK 0x000007E0L 961 #define DAGB0_RD_VC1_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 962 #define DAGB0_RD_VC1_CNTL__MAX_BW_MASK 0x000FF000L 963 #define DAGB0_RD_VC1_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 964 #define DAGB0_RD_VC1_CNTL__MIN_BW_MASK 0x00E00000L 965 #define DAGB0_RD_VC1_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 966 #define DAGB0_RD_VC1_CNTL__MAX_OSD_MASK 0xFE000000L 967 //DAGB0_RD_VC2_CNTL 968 #define DAGB0_RD_VC2_CNTL__STOR_CREDIT__SHIFT 0x0 969 #define DAGB0_RD_VC2_CNTL__EA_CREDIT__SHIFT 0x5 970 #define DAGB0_RD_VC2_CNTL__MAX_BW_ENABLE__SHIFT 0xb 971 #define DAGB0_RD_VC2_CNTL__MAX_BW__SHIFT 0xc 972 #define DAGB0_RD_VC2_CNTL__MIN_BW_ENABLE__SHIFT 0x14 973 #define DAGB0_RD_VC2_CNTL__MIN_BW__SHIFT 0x15 974 #define DAGB0_RD_VC2_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 975 #define DAGB0_RD_VC2_CNTL__MAX_OSD__SHIFT 0x19 976 #define DAGB0_RD_VC2_CNTL__STOR_CREDIT_MASK 0x0000001FL 977 #define DAGB0_RD_VC2_CNTL__EA_CREDIT_MASK 0x000007E0L 978 #define DAGB0_RD_VC2_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 979 #define DAGB0_RD_VC2_CNTL__MAX_BW_MASK 0x000FF000L 980 #define DAGB0_RD_VC2_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 981 #define DAGB0_RD_VC2_CNTL__MIN_BW_MASK 0x00E00000L 982 #define DAGB0_RD_VC2_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 983 #define DAGB0_RD_VC2_CNTL__MAX_OSD_MASK 0xFE000000L 984 //DAGB0_RD_VC3_CNTL 985 #define DAGB0_RD_VC3_CNTL__STOR_CREDIT__SHIFT 0x0 986 #define DAGB0_RD_VC3_CNTL__EA_CREDIT__SHIFT 0x5 987 #define DAGB0_RD_VC3_CNTL__MAX_BW_ENABLE__SHIFT 0xb 988 #define DAGB0_RD_VC3_CNTL__MAX_BW__SHIFT 0xc 989 #define DAGB0_RD_VC3_CNTL__MIN_BW_ENABLE__SHIFT 0x14 990 #define DAGB0_RD_VC3_CNTL__MIN_BW__SHIFT 0x15 991 #define DAGB0_RD_VC3_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 992 #define DAGB0_RD_VC3_CNTL__MAX_OSD__SHIFT 0x19 993 #define DAGB0_RD_VC3_CNTL__STOR_CREDIT_MASK 0x0000001FL 994 #define DAGB0_RD_VC3_CNTL__EA_CREDIT_MASK 0x000007E0L 995 #define DAGB0_RD_VC3_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 996 #define DAGB0_RD_VC3_CNTL__MAX_BW_MASK 0x000FF000L 997 #define DAGB0_RD_VC3_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 998 #define DAGB0_RD_VC3_CNTL__MIN_BW_MASK 0x00E00000L 999 #define DAGB0_RD_VC3_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 1000 #define DAGB0_RD_VC3_CNTL__MAX_OSD_MASK 0xFE000000L 1001 //DAGB0_RD_VC4_CNTL 1002 #define DAGB0_RD_VC4_CNTL__STOR_CREDIT__SHIFT 0x0 1003 #define DAGB0_RD_VC4_CNTL__EA_CREDIT__SHIFT 0x5 1004 #define DAGB0_RD_VC4_CNTL__MAX_BW_ENABLE__SHIFT 0xb 1005 #define DAGB0_RD_VC4_CNTL__MAX_BW__SHIFT 0xc 1006 #define DAGB0_RD_VC4_CNTL__MIN_BW_ENABLE__SHIFT 0x14 1007 #define DAGB0_RD_VC4_CNTL__MIN_BW__SHIFT 0x15 1008 #define DAGB0_RD_VC4_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 1009 #define DAGB0_RD_VC4_CNTL__MAX_OSD__SHIFT 0x19 1010 #define DAGB0_RD_VC4_CNTL__STOR_CREDIT_MASK 0x0000001FL 1011 #define DAGB0_RD_VC4_CNTL__EA_CREDIT_MASK 0x000007E0L 1012 #define DAGB0_RD_VC4_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 1013 #define DAGB0_RD_VC4_CNTL__MAX_BW_MASK 0x000FF000L 1014 #define DAGB0_RD_VC4_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 1015 #define DAGB0_RD_VC4_CNTL__MIN_BW_MASK 0x00E00000L 1016 #define DAGB0_RD_VC4_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 1017 #define DAGB0_RD_VC4_CNTL__MAX_OSD_MASK 0xFE000000L 1018 //DAGB0_RD_VC5_CNTL 1019 #define DAGB0_RD_VC5_CNTL__STOR_CREDIT__SHIFT 0x0 1020 #define DAGB0_RD_VC5_CNTL__EA_CREDIT__SHIFT 0x5 1021 #define DAGB0_RD_VC5_CNTL__MAX_BW_ENABLE__SHIFT 0xb 1022 #define DAGB0_RD_VC5_CNTL__MAX_BW__SHIFT 0xc 1023 #define DAGB0_RD_VC5_CNTL__MIN_BW_ENABLE__SHIFT 0x14 1024 #define DAGB0_RD_VC5_CNTL__MIN_BW__SHIFT 0x15 1025 #define DAGB0_RD_VC5_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 1026 #define DAGB0_RD_VC5_CNTL__MAX_OSD__SHIFT 0x19 1027 #define DAGB0_RD_VC5_CNTL__STOR_CREDIT_MASK 0x0000001FL 1028 #define DAGB0_RD_VC5_CNTL__EA_CREDIT_MASK 0x000007E0L 1029 #define DAGB0_RD_VC5_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 1030 #define DAGB0_RD_VC5_CNTL__MAX_BW_MASK 0x000FF000L 1031 #define DAGB0_RD_VC5_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 1032 #define DAGB0_RD_VC5_CNTL__MIN_BW_MASK 0x00E00000L 1033 #define DAGB0_RD_VC5_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 1034 #define DAGB0_RD_VC5_CNTL__MAX_OSD_MASK 0xFE000000L 1035 //DAGB0_RD_VC6_CNTL 1036 #define DAGB0_RD_VC6_CNTL__STOR_CREDIT__SHIFT 0x0 1037 #define DAGB0_RD_VC6_CNTL__EA_CREDIT__SHIFT 0x5 1038 #define DAGB0_RD_VC6_CNTL__MAX_BW_ENABLE__SHIFT 0xb 1039 #define DAGB0_RD_VC6_CNTL__MAX_BW__SHIFT 0xc 1040 #define DAGB0_RD_VC6_CNTL__MIN_BW_ENABLE__SHIFT 0x14 1041 #define DAGB0_RD_VC6_CNTL__MIN_BW__SHIFT 0x15 1042 #define DAGB0_RD_VC6_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 1043 #define DAGB0_RD_VC6_CNTL__MAX_OSD__SHIFT 0x19 1044 #define DAGB0_RD_VC6_CNTL__STOR_CREDIT_MASK 0x0000001FL 1045 #define DAGB0_RD_VC6_CNTL__EA_CREDIT_MASK 0x000007E0L 1046 #define DAGB0_RD_VC6_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 1047 #define DAGB0_RD_VC6_CNTL__MAX_BW_MASK 0x000FF000L 1048 #define DAGB0_RD_VC6_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 1049 #define DAGB0_RD_VC6_CNTL__MIN_BW_MASK 0x00E00000L 1050 #define DAGB0_RD_VC6_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 1051 #define DAGB0_RD_VC6_CNTL__MAX_OSD_MASK 0xFE000000L 1052 //DAGB0_RD_VC7_CNTL 1053 #define DAGB0_RD_VC7_CNTL__STOR_CREDIT__SHIFT 0x0 1054 #define DAGB0_RD_VC7_CNTL__EA_CREDIT__SHIFT 0x5 1055 #define DAGB0_RD_VC7_CNTL__MAX_BW_ENABLE__SHIFT 0xb 1056 #define DAGB0_RD_VC7_CNTL__MAX_BW__SHIFT 0xc 1057 #define DAGB0_RD_VC7_CNTL__MIN_BW_ENABLE__SHIFT 0x14 1058 #define DAGB0_RD_VC7_CNTL__MIN_BW__SHIFT 0x15 1059 #define DAGB0_RD_VC7_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 1060 #define DAGB0_RD_VC7_CNTL__MAX_OSD__SHIFT 0x19 1061 #define DAGB0_RD_VC7_CNTL__STOR_CREDIT_MASK 0x0000001FL 1062 #define DAGB0_RD_VC7_CNTL__EA_CREDIT_MASK 0x000007E0L 1063 #define DAGB0_RD_VC7_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 1064 #define DAGB0_RD_VC7_CNTL__MAX_BW_MASK 0x000FF000L 1065 #define DAGB0_RD_VC7_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 1066 #define DAGB0_RD_VC7_CNTL__MIN_BW_MASK 0x00E00000L 1067 #define DAGB0_RD_VC7_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 1068 #define DAGB0_RD_VC7_CNTL__MAX_OSD_MASK 0xFE000000L 1069 //DAGB0_RD_CNTL_MISC 1070 #define DAGB0_RD_CNTL_MISC__STOR_POOL_CREDIT__SHIFT 0x0 1071 #define DAGB0_RD_CNTL_MISC__EA_POOL_CREDIT__SHIFT 0x6 1072 #define DAGB0_RD_CNTL_MISC__IO_EA_CREDIT__SHIFT 0xd 1073 #define DAGB0_RD_CNTL_MISC__STOR_CC_LEGACY_MODE__SHIFT 0x13 1074 #define DAGB0_RD_CNTL_MISC__EA_CC_LEGACY_MODE__SHIFT 0x14 1075 #define DAGB0_RD_CNTL_MISC__UTCL2_CID__SHIFT 0x15 1076 #define DAGB0_RD_CNTL_MISC__HDP_CID__SHIFT 0x1a 1077 #define DAGB0_RD_CNTL_MISC__STOR_POOL_CREDIT_MASK 0x0000003FL 1078 #define DAGB0_RD_CNTL_MISC__EA_POOL_CREDIT_MASK 0x00001FC0L 1079 #define DAGB0_RD_CNTL_MISC__IO_EA_CREDIT_MASK 0x0007E000L 1080 #define DAGB0_RD_CNTL_MISC__STOR_CC_LEGACY_MODE_MASK 0x00080000L 1081 #define DAGB0_RD_CNTL_MISC__EA_CC_LEGACY_MODE_MASK 0x00100000L 1082 #define DAGB0_RD_CNTL_MISC__UTCL2_CID_MASK 0x03E00000L 1083 #define DAGB0_RD_CNTL_MISC__HDP_CID_MASK 0x7C000000L 1084 //DAGB0_RD_TLB_CREDIT 1085 #define DAGB0_RD_TLB_CREDIT__TLB0__SHIFT 0x0 1086 #define DAGB0_RD_TLB_CREDIT__TLB1__SHIFT 0x5 1087 #define DAGB0_RD_TLB_CREDIT__TLB2__SHIFT 0xa 1088 #define DAGB0_RD_TLB_CREDIT__TLB3__SHIFT 0xf 1089 #define DAGB0_RD_TLB_CREDIT__TLB4__SHIFT 0x14 1090 #define DAGB0_RD_TLB_CREDIT__TLB5__SHIFT 0x19 1091 #define DAGB0_RD_TLB_CREDIT__TLB0_MASK 0x0000001FL 1092 #define DAGB0_RD_TLB_CREDIT__TLB1_MASK 0x000003E0L 1093 #define DAGB0_RD_TLB_CREDIT__TLB2_MASK 0x00007C00L 1094 #define DAGB0_RD_TLB_CREDIT__TLB3_MASK 0x000F8000L 1095 #define DAGB0_RD_TLB_CREDIT__TLB4_MASK 0x01F00000L 1096 #define DAGB0_RD_TLB_CREDIT__TLB5_MASK 0x3E000000L 1097 //DAGB0_RD_RDRET_CREDIT_CNTL 1098 #define DAGB0_RD_RDRET_CREDIT_CNTL__VC0_CREDIT__SHIFT 0x0 1099 #define DAGB0_RD_RDRET_CREDIT_CNTL__VC1_CREDIT__SHIFT 0x6 1100 #define DAGB0_RD_RDRET_CREDIT_CNTL__VC2_CREDIT__SHIFT 0xc 1101 #define DAGB0_RD_RDRET_CREDIT_CNTL__VC3_CREDIT__SHIFT 0x12 1102 #define DAGB0_RD_RDRET_CREDIT_CNTL__VC4_CREDIT__SHIFT 0x18 1103 #define DAGB0_RD_RDRET_CREDIT_CNTL__VC_MODE__SHIFT 0x1e 1104 #define DAGB0_RD_RDRET_CREDIT_CNTL__FIX_EQ__SHIFT 0x1f 1105 #define DAGB0_RD_RDRET_CREDIT_CNTL__VC0_CREDIT_MASK 0x0000003FL 1106 #define DAGB0_RD_RDRET_CREDIT_CNTL__VC1_CREDIT_MASK 0x00000FC0L 1107 #define DAGB0_RD_RDRET_CREDIT_CNTL__VC2_CREDIT_MASK 0x0003F000L 1108 #define DAGB0_RD_RDRET_CREDIT_CNTL__VC3_CREDIT_MASK 0x00FC0000L 1109 #define DAGB0_RD_RDRET_CREDIT_CNTL__VC4_CREDIT_MASK 0x3F000000L 1110 #define DAGB0_RD_RDRET_CREDIT_CNTL__VC_MODE_MASK 0x40000000L 1111 #define DAGB0_RD_RDRET_CREDIT_CNTL__FIX_EQ_MASK 0x80000000L 1112 //DAGB0_RD_RDRET_CREDIT_CNTL2 1113 #define DAGB0_RD_RDRET_CREDIT_CNTL2__POOL_CREDIT__SHIFT 0x0 1114 #define DAGB0_RD_RDRET_CREDIT_CNTL2__POOL_CREDIT_MASK 0x0000007FL 1115 //DAGB0_RDCLI_ASK_PENDING 1116 #define DAGB0_RDCLI_ASK_PENDING__BUSY__SHIFT 0x0 1117 #define DAGB0_RDCLI_ASK_PENDING__BUSY_MASK 0xFFFFFFFFL 1118 //DAGB0_RDCLI_GO_PENDING 1119 #define DAGB0_RDCLI_GO_PENDING__BUSY__SHIFT 0x0 1120 #define DAGB0_RDCLI_GO_PENDING__BUSY_MASK 0xFFFFFFFFL 1121 //DAGB0_RDCLI_GBLSEND_PENDING 1122 #define DAGB0_RDCLI_GBLSEND_PENDING__BUSY__SHIFT 0x0 1123 #define DAGB0_RDCLI_GBLSEND_PENDING__BUSY_MASK 0xFFFFFFFFL 1124 //DAGB0_RDCLI_TLB_PENDING 1125 #define DAGB0_RDCLI_TLB_PENDING__BUSY__SHIFT 0x0 1126 #define DAGB0_RDCLI_TLB_PENDING__BUSY_MASK 0xFFFFFFFFL 1127 //DAGB0_RDCLI_OARB_PENDING 1128 #define DAGB0_RDCLI_OARB_PENDING__BUSY__SHIFT 0x0 1129 #define DAGB0_RDCLI_OARB_PENDING__BUSY_MASK 0xFFFFFFFFL 1130 //DAGB0_RDCLI_OSD_PENDING 1131 #define DAGB0_RDCLI_OSD_PENDING__BUSY__SHIFT 0x0 1132 #define DAGB0_RDCLI_OSD_PENDING__BUSY_MASK 0xFFFFFFFFL 1133 //DAGB0_WRCLI0 1134 #define DAGB0_WRCLI0__VIRT_CHAN__SHIFT 0x0 1135 #define DAGB0_WRCLI0__CHECK_TLB_CREDIT__SHIFT 0x3 1136 #define DAGB0_WRCLI0__URG_HIGH__SHIFT 0x4 1137 #define DAGB0_WRCLI0__URG_LOW__SHIFT 0x8 1138 #define DAGB0_WRCLI0__MAX_BW_ENABLE__SHIFT 0xc 1139 #define DAGB0_WRCLI0__MAX_BW__SHIFT 0xd 1140 #define DAGB0_WRCLI0__MIN_BW_ENABLE__SHIFT 0x15 1141 #define DAGB0_WRCLI0__MIN_BW__SHIFT 0x16 1142 #define DAGB0_WRCLI0__OSD_LIMITER_ENABLE__SHIFT 0x19 1143 #define DAGB0_WRCLI0__MAX_OSD__SHIFT 0x1a 1144 #define DAGB0_WRCLI0__VIRT_CHAN_MASK 0x00000007L 1145 #define DAGB0_WRCLI0__CHECK_TLB_CREDIT_MASK 0x00000008L 1146 #define DAGB0_WRCLI0__URG_HIGH_MASK 0x000000F0L 1147 #define DAGB0_WRCLI0__URG_LOW_MASK 0x00000F00L 1148 #define DAGB0_WRCLI0__MAX_BW_ENABLE_MASK 0x00001000L 1149 #define DAGB0_WRCLI0__MAX_BW_MASK 0x001FE000L 1150 #define DAGB0_WRCLI0__MIN_BW_ENABLE_MASK 0x00200000L 1151 #define DAGB0_WRCLI0__MIN_BW_MASK 0x01C00000L 1152 #define DAGB0_WRCLI0__OSD_LIMITER_ENABLE_MASK 0x02000000L 1153 #define DAGB0_WRCLI0__MAX_OSD_MASK 0xFC000000L 1154 //DAGB0_WRCLI1 1155 #define DAGB0_WRCLI1__VIRT_CHAN__SHIFT 0x0 1156 #define DAGB0_WRCLI1__CHECK_TLB_CREDIT__SHIFT 0x3 1157 #define DAGB0_WRCLI1__URG_HIGH__SHIFT 0x4 1158 #define DAGB0_WRCLI1__URG_LOW__SHIFT 0x8 1159 #define DAGB0_WRCLI1__MAX_BW_ENABLE__SHIFT 0xc 1160 #define DAGB0_WRCLI1__MAX_BW__SHIFT 0xd 1161 #define DAGB0_WRCLI1__MIN_BW_ENABLE__SHIFT 0x15 1162 #define DAGB0_WRCLI1__MIN_BW__SHIFT 0x16 1163 #define DAGB0_WRCLI1__OSD_LIMITER_ENABLE__SHIFT 0x19 1164 #define DAGB0_WRCLI1__MAX_OSD__SHIFT 0x1a 1165 #define DAGB0_WRCLI1__VIRT_CHAN_MASK 0x00000007L 1166 #define DAGB0_WRCLI1__CHECK_TLB_CREDIT_MASK 0x00000008L 1167 #define DAGB0_WRCLI1__URG_HIGH_MASK 0x000000F0L 1168 #define DAGB0_WRCLI1__URG_LOW_MASK 0x00000F00L 1169 #define DAGB0_WRCLI1__MAX_BW_ENABLE_MASK 0x00001000L 1170 #define DAGB0_WRCLI1__MAX_BW_MASK 0x001FE000L 1171 #define DAGB0_WRCLI1__MIN_BW_ENABLE_MASK 0x00200000L 1172 #define DAGB0_WRCLI1__MIN_BW_MASK 0x01C00000L 1173 #define DAGB0_WRCLI1__OSD_LIMITER_ENABLE_MASK 0x02000000L 1174 #define DAGB0_WRCLI1__MAX_OSD_MASK 0xFC000000L 1175 //DAGB0_WRCLI2 1176 #define DAGB0_WRCLI2__VIRT_CHAN__SHIFT 0x0 1177 #define DAGB0_WRCLI2__CHECK_TLB_CREDIT__SHIFT 0x3 1178 #define DAGB0_WRCLI2__URG_HIGH__SHIFT 0x4 1179 #define DAGB0_WRCLI2__URG_LOW__SHIFT 0x8 1180 #define DAGB0_WRCLI2__MAX_BW_ENABLE__SHIFT 0xc 1181 #define DAGB0_WRCLI2__MAX_BW__SHIFT 0xd 1182 #define DAGB0_WRCLI2__MIN_BW_ENABLE__SHIFT 0x15 1183 #define DAGB0_WRCLI2__MIN_BW__SHIFT 0x16 1184 #define DAGB0_WRCLI2__OSD_LIMITER_ENABLE__SHIFT 0x19 1185 #define DAGB0_WRCLI2__MAX_OSD__SHIFT 0x1a 1186 #define DAGB0_WRCLI2__VIRT_CHAN_MASK 0x00000007L 1187 #define DAGB0_WRCLI2__CHECK_TLB_CREDIT_MASK 0x00000008L 1188 #define DAGB0_WRCLI2__URG_HIGH_MASK 0x000000F0L 1189 #define DAGB0_WRCLI2__URG_LOW_MASK 0x00000F00L 1190 #define DAGB0_WRCLI2__MAX_BW_ENABLE_MASK 0x00001000L 1191 #define DAGB0_WRCLI2__MAX_BW_MASK 0x001FE000L 1192 #define DAGB0_WRCLI2__MIN_BW_ENABLE_MASK 0x00200000L 1193 #define DAGB0_WRCLI2__MIN_BW_MASK 0x01C00000L 1194 #define DAGB0_WRCLI2__OSD_LIMITER_ENABLE_MASK 0x02000000L 1195 #define DAGB0_WRCLI2__MAX_OSD_MASK 0xFC000000L 1196 //DAGB0_WRCLI3 1197 #define DAGB0_WRCLI3__VIRT_CHAN__SHIFT 0x0 1198 #define DAGB0_WRCLI3__CHECK_TLB_CREDIT__SHIFT 0x3 1199 #define DAGB0_WRCLI3__URG_HIGH__SHIFT 0x4 1200 #define DAGB0_WRCLI3__URG_LOW__SHIFT 0x8 1201 #define DAGB0_WRCLI3__MAX_BW_ENABLE__SHIFT 0xc 1202 #define DAGB0_WRCLI3__MAX_BW__SHIFT 0xd 1203 #define DAGB0_WRCLI3__MIN_BW_ENABLE__SHIFT 0x15 1204 #define DAGB0_WRCLI3__MIN_BW__SHIFT 0x16 1205 #define DAGB0_WRCLI3__OSD_LIMITER_ENABLE__SHIFT 0x19 1206 #define DAGB0_WRCLI3__MAX_OSD__SHIFT 0x1a 1207 #define DAGB0_WRCLI3__VIRT_CHAN_MASK 0x00000007L 1208 #define DAGB0_WRCLI3__CHECK_TLB_CREDIT_MASK 0x00000008L 1209 #define DAGB0_WRCLI3__URG_HIGH_MASK 0x000000F0L 1210 #define DAGB0_WRCLI3__URG_LOW_MASK 0x00000F00L 1211 #define DAGB0_WRCLI3__MAX_BW_ENABLE_MASK 0x00001000L 1212 #define DAGB0_WRCLI3__MAX_BW_MASK 0x001FE000L 1213 #define DAGB0_WRCLI3__MIN_BW_ENABLE_MASK 0x00200000L 1214 #define DAGB0_WRCLI3__MIN_BW_MASK 0x01C00000L 1215 #define DAGB0_WRCLI3__OSD_LIMITER_ENABLE_MASK 0x02000000L 1216 #define DAGB0_WRCLI3__MAX_OSD_MASK 0xFC000000L 1217 //DAGB0_WRCLI4 1218 #define DAGB0_WRCLI4__VIRT_CHAN__SHIFT 0x0 1219 #define DAGB0_WRCLI4__CHECK_TLB_CREDIT__SHIFT 0x3 1220 #define DAGB0_WRCLI4__URG_HIGH__SHIFT 0x4 1221 #define DAGB0_WRCLI4__URG_LOW__SHIFT 0x8 1222 #define DAGB0_WRCLI4__MAX_BW_ENABLE__SHIFT 0xc 1223 #define DAGB0_WRCLI4__MAX_BW__SHIFT 0xd 1224 #define DAGB0_WRCLI4__MIN_BW_ENABLE__SHIFT 0x15 1225 #define DAGB0_WRCLI4__MIN_BW__SHIFT 0x16 1226 #define DAGB0_WRCLI4__OSD_LIMITER_ENABLE__SHIFT 0x19 1227 #define DAGB0_WRCLI4__MAX_OSD__SHIFT 0x1a 1228 #define DAGB0_WRCLI4__VIRT_CHAN_MASK 0x00000007L 1229 #define DAGB0_WRCLI4__CHECK_TLB_CREDIT_MASK 0x00000008L 1230 #define DAGB0_WRCLI4__URG_HIGH_MASK 0x000000F0L 1231 #define DAGB0_WRCLI4__URG_LOW_MASK 0x00000F00L 1232 #define DAGB0_WRCLI4__MAX_BW_ENABLE_MASK 0x00001000L 1233 #define DAGB0_WRCLI4__MAX_BW_MASK 0x001FE000L 1234 #define DAGB0_WRCLI4__MIN_BW_ENABLE_MASK 0x00200000L 1235 #define DAGB0_WRCLI4__MIN_BW_MASK 0x01C00000L 1236 #define DAGB0_WRCLI4__OSD_LIMITER_ENABLE_MASK 0x02000000L 1237 #define DAGB0_WRCLI4__MAX_OSD_MASK 0xFC000000L 1238 //DAGB0_WRCLI5 1239 #define DAGB0_WRCLI5__VIRT_CHAN__SHIFT 0x0 1240 #define DAGB0_WRCLI5__CHECK_TLB_CREDIT__SHIFT 0x3 1241 #define DAGB0_WRCLI5__URG_HIGH__SHIFT 0x4 1242 #define DAGB0_WRCLI5__URG_LOW__SHIFT 0x8 1243 #define DAGB0_WRCLI5__MAX_BW_ENABLE__SHIFT 0xc 1244 #define DAGB0_WRCLI5__MAX_BW__SHIFT 0xd 1245 #define DAGB0_WRCLI5__MIN_BW_ENABLE__SHIFT 0x15 1246 #define DAGB0_WRCLI5__MIN_BW__SHIFT 0x16 1247 #define DAGB0_WRCLI5__OSD_LIMITER_ENABLE__SHIFT 0x19 1248 #define DAGB0_WRCLI5__MAX_OSD__SHIFT 0x1a 1249 #define DAGB0_WRCLI5__VIRT_CHAN_MASK 0x00000007L 1250 #define DAGB0_WRCLI5__CHECK_TLB_CREDIT_MASK 0x00000008L 1251 #define DAGB0_WRCLI5__URG_HIGH_MASK 0x000000F0L 1252 #define DAGB0_WRCLI5__URG_LOW_MASK 0x00000F00L 1253 #define DAGB0_WRCLI5__MAX_BW_ENABLE_MASK 0x00001000L 1254 #define DAGB0_WRCLI5__MAX_BW_MASK 0x001FE000L 1255 #define DAGB0_WRCLI5__MIN_BW_ENABLE_MASK 0x00200000L 1256 #define DAGB0_WRCLI5__MIN_BW_MASK 0x01C00000L 1257 #define DAGB0_WRCLI5__OSD_LIMITER_ENABLE_MASK 0x02000000L 1258 #define DAGB0_WRCLI5__MAX_OSD_MASK 0xFC000000L 1259 //DAGB0_WRCLI6 1260 #define DAGB0_WRCLI6__VIRT_CHAN__SHIFT 0x0 1261 #define DAGB0_WRCLI6__CHECK_TLB_CREDIT__SHIFT 0x3 1262 #define DAGB0_WRCLI6__URG_HIGH__SHIFT 0x4 1263 #define DAGB0_WRCLI6__URG_LOW__SHIFT 0x8 1264 #define DAGB0_WRCLI6__MAX_BW_ENABLE__SHIFT 0xc 1265 #define DAGB0_WRCLI6__MAX_BW__SHIFT 0xd 1266 #define DAGB0_WRCLI6__MIN_BW_ENABLE__SHIFT 0x15 1267 #define DAGB0_WRCLI6__MIN_BW__SHIFT 0x16 1268 #define DAGB0_WRCLI6__OSD_LIMITER_ENABLE__SHIFT 0x19 1269 #define DAGB0_WRCLI6__MAX_OSD__SHIFT 0x1a 1270 #define DAGB0_WRCLI6__VIRT_CHAN_MASK 0x00000007L 1271 #define DAGB0_WRCLI6__CHECK_TLB_CREDIT_MASK 0x00000008L 1272 #define DAGB0_WRCLI6__URG_HIGH_MASK 0x000000F0L 1273 #define DAGB0_WRCLI6__URG_LOW_MASK 0x00000F00L 1274 #define DAGB0_WRCLI6__MAX_BW_ENABLE_MASK 0x00001000L 1275 #define DAGB0_WRCLI6__MAX_BW_MASK 0x001FE000L 1276 #define DAGB0_WRCLI6__MIN_BW_ENABLE_MASK 0x00200000L 1277 #define DAGB0_WRCLI6__MIN_BW_MASK 0x01C00000L 1278 #define DAGB0_WRCLI6__OSD_LIMITER_ENABLE_MASK 0x02000000L 1279 #define DAGB0_WRCLI6__MAX_OSD_MASK 0xFC000000L 1280 //DAGB0_WRCLI7 1281 #define DAGB0_WRCLI7__VIRT_CHAN__SHIFT 0x0 1282 #define DAGB0_WRCLI7__CHECK_TLB_CREDIT__SHIFT 0x3 1283 #define DAGB0_WRCLI7__URG_HIGH__SHIFT 0x4 1284 #define DAGB0_WRCLI7__URG_LOW__SHIFT 0x8 1285 #define DAGB0_WRCLI7__MAX_BW_ENABLE__SHIFT 0xc 1286 #define DAGB0_WRCLI7__MAX_BW__SHIFT 0xd 1287 #define DAGB0_WRCLI7__MIN_BW_ENABLE__SHIFT 0x15 1288 #define DAGB0_WRCLI7__MIN_BW__SHIFT 0x16 1289 #define DAGB0_WRCLI7__OSD_LIMITER_ENABLE__SHIFT 0x19 1290 #define DAGB0_WRCLI7__MAX_OSD__SHIFT 0x1a 1291 #define DAGB0_WRCLI7__VIRT_CHAN_MASK 0x00000007L 1292 #define DAGB0_WRCLI7__CHECK_TLB_CREDIT_MASK 0x00000008L 1293 #define DAGB0_WRCLI7__URG_HIGH_MASK 0x000000F0L 1294 #define DAGB0_WRCLI7__URG_LOW_MASK 0x00000F00L 1295 #define DAGB0_WRCLI7__MAX_BW_ENABLE_MASK 0x00001000L 1296 #define DAGB0_WRCLI7__MAX_BW_MASK 0x001FE000L 1297 #define DAGB0_WRCLI7__MIN_BW_ENABLE_MASK 0x00200000L 1298 #define DAGB0_WRCLI7__MIN_BW_MASK 0x01C00000L 1299 #define DAGB0_WRCLI7__OSD_LIMITER_ENABLE_MASK 0x02000000L 1300 #define DAGB0_WRCLI7__MAX_OSD_MASK 0xFC000000L 1301 //DAGB0_WRCLI8 1302 #define DAGB0_WRCLI8__VIRT_CHAN__SHIFT 0x0 1303 #define DAGB0_WRCLI8__CHECK_TLB_CREDIT__SHIFT 0x3 1304 #define DAGB0_WRCLI8__URG_HIGH__SHIFT 0x4 1305 #define DAGB0_WRCLI8__URG_LOW__SHIFT 0x8 1306 #define DAGB0_WRCLI8__MAX_BW_ENABLE__SHIFT 0xc 1307 #define DAGB0_WRCLI8__MAX_BW__SHIFT 0xd 1308 #define DAGB0_WRCLI8__MIN_BW_ENABLE__SHIFT 0x15 1309 #define DAGB0_WRCLI8__MIN_BW__SHIFT 0x16 1310 #define DAGB0_WRCLI8__OSD_LIMITER_ENABLE__SHIFT 0x19 1311 #define DAGB0_WRCLI8__MAX_OSD__SHIFT 0x1a 1312 #define DAGB0_WRCLI8__VIRT_CHAN_MASK 0x00000007L 1313 #define DAGB0_WRCLI8__CHECK_TLB_CREDIT_MASK 0x00000008L 1314 #define DAGB0_WRCLI8__URG_HIGH_MASK 0x000000F0L 1315 #define DAGB0_WRCLI8__URG_LOW_MASK 0x00000F00L 1316 #define DAGB0_WRCLI8__MAX_BW_ENABLE_MASK 0x00001000L 1317 #define DAGB0_WRCLI8__MAX_BW_MASK 0x001FE000L 1318 #define DAGB0_WRCLI8__MIN_BW_ENABLE_MASK 0x00200000L 1319 #define DAGB0_WRCLI8__MIN_BW_MASK 0x01C00000L 1320 #define DAGB0_WRCLI8__OSD_LIMITER_ENABLE_MASK 0x02000000L 1321 #define DAGB0_WRCLI8__MAX_OSD_MASK 0xFC000000L 1322 //DAGB0_WRCLI9 1323 #define DAGB0_WRCLI9__VIRT_CHAN__SHIFT 0x0 1324 #define DAGB0_WRCLI9__CHECK_TLB_CREDIT__SHIFT 0x3 1325 #define DAGB0_WRCLI9__URG_HIGH__SHIFT 0x4 1326 #define DAGB0_WRCLI9__URG_LOW__SHIFT 0x8 1327 #define DAGB0_WRCLI9__MAX_BW_ENABLE__SHIFT 0xc 1328 #define DAGB0_WRCLI9__MAX_BW__SHIFT 0xd 1329 #define DAGB0_WRCLI9__MIN_BW_ENABLE__SHIFT 0x15 1330 #define DAGB0_WRCLI9__MIN_BW__SHIFT 0x16 1331 #define DAGB0_WRCLI9__OSD_LIMITER_ENABLE__SHIFT 0x19 1332 #define DAGB0_WRCLI9__MAX_OSD__SHIFT 0x1a 1333 #define DAGB0_WRCLI9__VIRT_CHAN_MASK 0x00000007L 1334 #define DAGB0_WRCLI9__CHECK_TLB_CREDIT_MASK 0x00000008L 1335 #define DAGB0_WRCLI9__URG_HIGH_MASK 0x000000F0L 1336 #define DAGB0_WRCLI9__URG_LOW_MASK 0x00000F00L 1337 #define DAGB0_WRCLI9__MAX_BW_ENABLE_MASK 0x00001000L 1338 #define DAGB0_WRCLI9__MAX_BW_MASK 0x001FE000L 1339 #define DAGB0_WRCLI9__MIN_BW_ENABLE_MASK 0x00200000L 1340 #define DAGB0_WRCLI9__MIN_BW_MASK 0x01C00000L 1341 #define DAGB0_WRCLI9__OSD_LIMITER_ENABLE_MASK 0x02000000L 1342 #define DAGB0_WRCLI9__MAX_OSD_MASK 0xFC000000L 1343 //DAGB0_WRCLI10 1344 #define DAGB0_WRCLI10__VIRT_CHAN__SHIFT 0x0 1345 #define DAGB0_WRCLI10__CHECK_TLB_CREDIT__SHIFT 0x3 1346 #define DAGB0_WRCLI10__URG_HIGH__SHIFT 0x4 1347 #define DAGB0_WRCLI10__URG_LOW__SHIFT 0x8 1348 #define DAGB0_WRCLI10__MAX_BW_ENABLE__SHIFT 0xc 1349 #define DAGB0_WRCLI10__MAX_BW__SHIFT 0xd 1350 #define DAGB0_WRCLI10__MIN_BW_ENABLE__SHIFT 0x15 1351 #define DAGB0_WRCLI10__MIN_BW__SHIFT 0x16 1352 #define DAGB0_WRCLI10__OSD_LIMITER_ENABLE__SHIFT 0x19 1353 #define DAGB0_WRCLI10__MAX_OSD__SHIFT 0x1a 1354 #define DAGB0_WRCLI10__VIRT_CHAN_MASK 0x00000007L 1355 #define DAGB0_WRCLI10__CHECK_TLB_CREDIT_MASK 0x00000008L 1356 #define DAGB0_WRCLI10__URG_HIGH_MASK 0x000000F0L 1357 #define DAGB0_WRCLI10__URG_LOW_MASK 0x00000F00L 1358 #define DAGB0_WRCLI10__MAX_BW_ENABLE_MASK 0x00001000L 1359 #define DAGB0_WRCLI10__MAX_BW_MASK 0x001FE000L 1360 #define DAGB0_WRCLI10__MIN_BW_ENABLE_MASK 0x00200000L 1361 #define DAGB0_WRCLI10__MIN_BW_MASK 0x01C00000L 1362 #define DAGB0_WRCLI10__OSD_LIMITER_ENABLE_MASK 0x02000000L 1363 #define DAGB0_WRCLI10__MAX_OSD_MASK 0xFC000000L 1364 //DAGB0_WRCLI11 1365 #define DAGB0_WRCLI11__VIRT_CHAN__SHIFT 0x0 1366 #define DAGB0_WRCLI11__CHECK_TLB_CREDIT__SHIFT 0x3 1367 #define DAGB0_WRCLI11__URG_HIGH__SHIFT 0x4 1368 #define DAGB0_WRCLI11__URG_LOW__SHIFT 0x8 1369 #define DAGB0_WRCLI11__MAX_BW_ENABLE__SHIFT 0xc 1370 #define DAGB0_WRCLI11__MAX_BW__SHIFT 0xd 1371 #define DAGB0_WRCLI11__MIN_BW_ENABLE__SHIFT 0x15 1372 #define DAGB0_WRCLI11__MIN_BW__SHIFT 0x16 1373 #define DAGB0_WRCLI11__OSD_LIMITER_ENABLE__SHIFT 0x19 1374 #define DAGB0_WRCLI11__MAX_OSD__SHIFT 0x1a 1375 #define DAGB0_WRCLI11__VIRT_CHAN_MASK 0x00000007L 1376 #define DAGB0_WRCLI11__CHECK_TLB_CREDIT_MASK 0x00000008L 1377 #define DAGB0_WRCLI11__URG_HIGH_MASK 0x000000F0L 1378 #define DAGB0_WRCLI11__URG_LOW_MASK 0x00000F00L 1379 #define DAGB0_WRCLI11__MAX_BW_ENABLE_MASK 0x00001000L 1380 #define DAGB0_WRCLI11__MAX_BW_MASK 0x001FE000L 1381 #define DAGB0_WRCLI11__MIN_BW_ENABLE_MASK 0x00200000L 1382 #define DAGB0_WRCLI11__MIN_BW_MASK 0x01C00000L 1383 #define DAGB0_WRCLI11__OSD_LIMITER_ENABLE_MASK 0x02000000L 1384 #define DAGB0_WRCLI11__MAX_OSD_MASK 0xFC000000L 1385 //DAGB0_WRCLI12 1386 #define DAGB0_WRCLI12__VIRT_CHAN__SHIFT 0x0 1387 #define DAGB0_WRCLI12__CHECK_TLB_CREDIT__SHIFT 0x3 1388 #define DAGB0_WRCLI12__URG_HIGH__SHIFT 0x4 1389 #define DAGB0_WRCLI12__URG_LOW__SHIFT 0x8 1390 #define DAGB0_WRCLI12__MAX_BW_ENABLE__SHIFT 0xc 1391 #define DAGB0_WRCLI12__MAX_BW__SHIFT 0xd 1392 #define DAGB0_WRCLI12__MIN_BW_ENABLE__SHIFT 0x15 1393 #define DAGB0_WRCLI12__MIN_BW__SHIFT 0x16 1394 #define DAGB0_WRCLI12__OSD_LIMITER_ENABLE__SHIFT 0x19 1395 #define DAGB0_WRCLI12__MAX_OSD__SHIFT 0x1a 1396 #define DAGB0_WRCLI12__VIRT_CHAN_MASK 0x00000007L 1397 #define DAGB0_WRCLI12__CHECK_TLB_CREDIT_MASK 0x00000008L 1398 #define DAGB0_WRCLI12__URG_HIGH_MASK 0x000000F0L 1399 #define DAGB0_WRCLI12__URG_LOW_MASK 0x00000F00L 1400 #define DAGB0_WRCLI12__MAX_BW_ENABLE_MASK 0x00001000L 1401 #define DAGB0_WRCLI12__MAX_BW_MASK 0x001FE000L 1402 #define DAGB0_WRCLI12__MIN_BW_ENABLE_MASK 0x00200000L 1403 #define DAGB0_WRCLI12__MIN_BW_MASK 0x01C00000L 1404 #define DAGB0_WRCLI12__OSD_LIMITER_ENABLE_MASK 0x02000000L 1405 #define DAGB0_WRCLI12__MAX_OSD_MASK 0xFC000000L 1406 //DAGB0_WRCLI13 1407 #define DAGB0_WRCLI13__VIRT_CHAN__SHIFT 0x0 1408 #define DAGB0_WRCLI13__CHECK_TLB_CREDIT__SHIFT 0x3 1409 #define DAGB0_WRCLI13__URG_HIGH__SHIFT 0x4 1410 #define DAGB0_WRCLI13__URG_LOW__SHIFT 0x8 1411 #define DAGB0_WRCLI13__MAX_BW_ENABLE__SHIFT 0xc 1412 #define DAGB0_WRCLI13__MAX_BW__SHIFT 0xd 1413 #define DAGB0_WRCLI13__MIN_BW_ENABLE__SHIFT 0x15 1414 #define DAGB0_WRCLI13__MIN_BW__SHIFT 0x16 1415 #define DAGB0_WRCLI13__OSD_LIMITER_ENABLE__SHIFT 0x19 1416 #define DAGB0_WRCLI13__MAX_OSD__SHIFT 0x1a 1417 #define DAGB0_WRCLI13__VIRT_CHAN_MASK 0x00000007L 1418 #define DAGB0_WRCLI13__CHECK_TLB_CREDIT_MASK 0x00000008L 1419 #define DAGB0_WRCLI13__URG_HIGH_MASK 0x000000F0L 1420 #define DAGB0_WRCLI13__URG_LOW_MASK 0x00000F00L 1421 #define DAGB0_WRCLI13__MAX_BW_ENABLE_MASK 0x00001000L 1422 #define DAGB0_WRCLI13__MAX_BW_MASK 0x001FE000L 1423 #define DAGB0_WRCLI13__MIN_BW_ENABLE_MASK 0x00200000L 1424 #define DAGB0_WRCLI13__MIN_BW_MASK 0x01C00000L 1425 #define DAGB0_WRCLI13__OSD_LIMITER_ENABLE_MASK 0x02000000L 1426 #define DAGB0_WRCLI13__MAX_OSD_MASK 0xFC000000L 1427 //DAGB0_WRCLI14 1428 #define DAGB0_WRCLI14__VIRT_CHAN__SHIFT 0x0 1429 #define DAGB0_WRCLI14__CHECK_TLB_CREDIT__SHIFT 0x3 1430 #define DAGB0_WRCLI14__URG_HIGH__SHIFT 0x4 1431 #define DAGB0_WRCLI14__URG_LOW__SHIFT 0x8 1432 #define DAGB0_WRCLI14__MAX_BW_ENABLE__SHIFT 0xc 1433 #define DAGB0_WRCLI14__MAX_BW__SHIFT 0xd 1434 #define DAGB0_WRCLI14__MIN_BW_ENABLE__SHIFT 0x15 1435 #define DAGB0_WRCLI14__MIN_BW__SHIFT 0x16 1436 #define DAGB0_WRCLI14__OSD_LIMITER_ENABLE__SHIFT 0x19 1437 #define DAGB0_WRCLI14__MAX_OSD__SHIFT 0x1a 1438 #define DAGB0_WRCLI14__VIRT_CHAN_MASK 0x00000007L 1439 #define DAGB0_WRCLI14__CHECK_TLB_CREDIT_MASK 0x00000008L 1440 #define DAGB0_WRCLI14__URG_HIGH_MASK 0x000000F0L 1441 #define DAGB0_WRCLI14__URG_LOW_MASK 0x00000F00L 1442 #define DAGB0_WRCLI14__MAX_BW_ENABLE_MASK 0x00001000L 1443 #define DAGB0_WRCLI14__MAX_BW_MASK 0x001FE000L 1444 #define DAGB0_WRCLI14__MIN_BW_ENABLE_MASK 0x00200000L 1445 #define DAGB0_WRCLI14__MIN_BW_MASK 0x01C00000L 1446 #define DAGB0_WRCLI14__OSD_LIMITER_ENABLE_MASK 0x02000000L 1447 #define DAGB0_WRCLI14__MAX_OSD_MASK 0xFC000000L 1448 //DAGB0_WRCLI15 1449 #define DAGB0_WRCLI15__VIRT_CHAN__SHIFT 0x0 1450 #define DAGB0_WRCLI15__CHECK_TLB_CREDIT__SHIFT 0x3 1451 #define DAGB0_WRCLI15__URG_HIGH__SHIFT 0x4 1452 #define DAGB0_WRCLI15__URG_LOW__SHIFT 0x8 1453 #define DAGB0_WRCLI15__MAX_BW_ENABLE__SHIFT 0xc 1454 #define DAGB0_WRCLI15__MAX_BW__SHIFT 0xd 1455 #define DAGB0_WRCLI15__MIN_BW_ENABLE__SHIFT 0x15 1456 #define DAGB0_WRCLI15__MIN_BW__SHIFT 0x16 1457 #define DAGB0_WRCLI15__OSD_LIMITER_ENABLE__SHIFT 0x19 1458 #define DAGB0_WRCLI15__MAX_OSD__SHIFT 0x1a 1459 #define DAGB0_WRCLI15__VIRT_CHAN_MASK 0x00000007L 1460 #define DAGB0_WRCLI15__CHECK_TLB_CREDIT_MASK 0x00000008L 1461 #define DAGB0_WRCLI15__URG_HIGH_MASK 0x000000F0L 1462 #define DAGB0_WRCLI15__URG_LOW_MASK 0x00000F00L 1463 #define DAGB0_WRCLI15__MAX_BW_ENABLE_MASK 0x00001000L 1464 #define DAGB0_WRCLI15__MAX_BW_MASK 0x001FE000L 1465 #define DAGB0_WRCLI15__MIN_BW_ENABLE_MASK 0x00200000L 1466 #define DAGB0_WRCLI15__MIN_BW_MASK 0x01C00000L 1467 #define DAGB0_WRCLI15__OSD_LIMITER_ENABLE_MASK 0x02000000L 1468 #define DAGB0_WRCLI15__MAX_OSD_MASK 0xFC000000L 1469 //DAGB0_WRCLI16 1470 #define DAGB0_WRCLI16__VIRT_CHAN__SHIFT 0x0 1471 #define DAGB0_WRCLI16__CHECK_TLB_CREDIT__SHIFT 0x3 1472 #define DAGB0_WRCLI16__URG_HIGH__SHIFT 0x4 1473 #define DAGB0_WRCLI16__URG_LOW__SHIFT 0x8 1474 #define DAGB0_WRCLI16__MAX_BW_ENABLE__SHIFT 0xc 1475 #define DAGB0_WRCLI16__MAX_BW__SHIFT 0xd 1476 #define DAGB0_WRCLI16__MIN_BW_ENABLE__SHIFT 0x15 1477 #define DAGB0_WRCLI16__MIN_BW__SHIFT 0x16 1478 #define DAGB0_WRCLI16__OSD_LIMITER_ENABLE__SHIFT 0x19 1479 #define DAGB0_WRCLI16__MAX_OSD__SHIFT 0x1a 1480 #define DAGB0_WRCLI16__VIRT_CHAN_MASK 0x00000007L 1481 #define DAGB0_WRCLI16__CHECK_TLB_CREDIT_MASK 0x00000008L 1482 #define DAGB0_WRCLI16__URG_HIGH_MASK 0x000000F0L 1483 #define DAGB0_WRCLI16__URG_LOW_MASK 0x00000F00L 1484 #define DAGB0_WRCLI16__MAX_BW_ENABLE_MASK 0x00001000L 1485 #define DAGB0_WRCLI16__MAX_BW_MASK 0x001FE000L 1486 #define DAGB0_WRCLI16__MIN_BW_ENABLE_MASK 0x00200000L 1487 #define DAGB0_WRCLI16__MIN_BW_MASK 0x01C00000L 1488 #define DAGB0_WRCLI16__OSD_LIMITER_ENABLE_MASK 0x02000000L 1489 #define DAGB0_WRCLI16__MAX_OSD_MASK 0xFC000000L 1490 //DAGB0_WRCLI17 1491 #define DAGB0_WRCLI17__VIRT_CHAN__SHIFT 0x0 1492 #define DAGB0_WRCLI17__CHECK_TLB_CREDIT__SHIFT 0x3 1493 #define DAGB0_WRCLI17__URG_HIGH__SHIFT 0x4 1494 #define DAGB0_WRCLI17__URG_LOW__SHIFT 0x8 1495 #define DAGB0_WRCLI17__MAX_BW_ENABLE__SHIFT 0xc 1496 #define DAGB0_WRCLI17__MAX_BW__SHIFT 0xd 1497 #define DAGB0_WRCLI17__MIN_BW_ENABLE__SHIFT 0x15 1498 #define DAGB0_WRCLI17__MIN_BW__SHIFT 0x16 1499 #define DAGB0_WRCLI17__OSD_LIMITER_ENABLE__SHIFT 0x19 1500 #define DAGB0_WRCLI17__MAX_OSD__SHIFT 0x1a 1501 #define DAGB0_WRCLI17__VIRT_CHAN_MASK 0x00000007L 1502 #define DAGB0_WRCLI17__CHECK_TLB_CREDIT_MASK 0x00000008L 1503 #define DAGB0_WRCLI17__URG_HIGH_MASK 0x000000F0L 1504 #define DAGB0_WRCLI17__URG_LOW_MASK 0x00000F00L 1505 #define DAGB0_WRCLI17__MAX_BW_ENABLE_MASK 0x00001000L 1506 #define DAGB0_WRCLI17__MAX_BW_MASK 0x001FE000L 1507 #define DAGB0_WRCLI17__MIN_BW_ENABLE_MASK 0x00200000L 1508 #define DAGB0_WRCLI17__MIN_BW_MASK 0x01C00000L 1509 #define DAGB0_WRCLI17__OSD_LIMITER_ENABLE_MASK 0x02000000L 1510 #define DAGB0_WRCLI17__MAX_OSD_MASK 0xFC000000L 1511 //DAGB0_WRCLI18 1512 #define DAGB0_WRCLI18__VIRT_CHAN__SHIFT 0x0 1513 #define DAGB0_WRCLI18__CHECK_TLB_CREDIT__SHIFT 0x3 1514 #define DAGB0_WRCLI18__URG_HIGH__SHIFT 0x4 1515 #define DAGB0_WRCLI18__URG_LOW__SHIFT 0x8 1516 #define DAGB0_WRCLI18__MAX_BW_ENABLE__SHIFT 0xc 1517 #define DAGB0_WRCLI18__MAX_BW__SHIFT 0xd 1518 #define DAGB0_WRCLI18__MIN_BW_ENABLE__SHIFT 0x15 1519 #define DAGB0_WRCLI18__MIN_BW__SHIFT 0x16 1520 #define DAGB0_WRCLI18__OSD_LIMITER_ENABLE__SHIFT 0x19 1521 #define DAGB0_WRCLI18__MAX_OSD__SHIFT 0x1a 1522 #define DAGB0_WRCLI18__VIRT_CHAN_MASK 0x00000007L 1523 #define DAGB0_WRCLI18__CHECK_TLB_CREDIT_MASK 0x00000008L 1524 #define DAGB0_WRCLI18__URG_HIGH_MASK 0x000000F0L 1525 #define DAGB0_WRCLI18__URG_LOW_MASK 0x00000F00L 1526 #define DAGB0_WRCLI18__MAX_BW_ENABLE_MASK 0x00001000L 1527 #define DAGB0_WRCLI18__MAX_BW_MASK 0x001FE000L 1528 #define DAGB0_WRCLI18__MIN_BW_ENABLE_MASK 0x00200000L 1529 #define DAGB0_WRCLI18__MIN_BW_MASK 0x01C00000L 1530 #define DAGB0_WRCLI18__OSD_LIMITER_ENABLE_MASK 0x02000000L 1531 #define DAGB0_WRCLI18__MAX_OSD_MASK 0xFC000000L 1532 //DAGB0_WRCLI19 1533 #define DAGB0_WRCLI19__VIRT_CHAN__SHIFT 0x0 1534 #define DAGB0_WRCLI19__CHECK_TLB_CREDIT__SHIFT 0x3 1535 #define DAGB0_WRCLI19__URG_HIGH__SHIFT 0x4 1536 #define DAGB0_WRCLI19__URG_LOW__SHIFT 0x8 1537 #define DAGB0_WRCLI19__MAX_BW_ENABLE__SHIFT 0xc 1538 #define DAGB0_WRCLI19__MAX_BW__SHIFT 0xd 1539 #define DAGB0_WRCLI19__MIN_BW_ENABLE__SHIFT 0x15 1540 #define DAGB0_WRCLI19__MIN_BW__SHIFT 0x16 1541 #define DAGB0_WRCLI19__OSD_LIMITER_ENABLE__SHIFT 0x19 1542 #define DAGB0_WRCLI19__MAX_OSD__SHIFT 0x1a 1543 #define DAGB0_WRCLI19__VIRT_CHAN_MASK 0x00000007L 1544 #define DAGB0_WRCLI19__CHECK_TLB_CREDIT_MASK 0x00000008L 1545 #define DAGB0_WRCLI19__URG_HIGH_MASK 0x000000F0L 1546 #define DAGB0_WRCLI19__URG_LOW_MASK 0x00000F00L 1547 #define DAGB0_WRCLI19__MAX_BW_ENABLE_MASK 0x00001000L 1548 #define DAGB0_WRCLI19__MAX_BW_MASK 0x001FE000L 1549 #define DAGB0_WRCLI19__MIN_BW_ENABLE_MASK 0x00200000L 1550 #define DAGB0_WRCLI19__MIN_BW_MASK 0x01C00000L 1551 #define DAGB0_WRCLI19__OSD_LIMITER_ENABLE_MASK 0x02000000L 1552 #define DAGB0_WRCLI19__MAX_OSD_MASK 0xFC000000L 1553 //DAGB0_WRCLI20 1554 #define DAGB0_WRCLI20__VIRT_CHAN__SHIFT 0x0 1555 #define DAGB0_WRCLI20__CHECK_TLB_CREDIT__SHIFT 0x3 1556 #define DAGB0_WRCLI20__URG_HIGH__SHIFT 0x4 1557 #define DAGB0_WRCLI20__URG_LOW__SHIFT 0x8 1558 #define DAGB0_WRCLI20__MAX_BW_ENABLE__SHIFT 0xc 1559 #define DAGB0_WRCLI20__MAX_BW__SHIFT 0xd 1560 #define DAGB0_WRCLI20__MIN_BW_ENABLE__SHIFT 0x15 1561 #define DAGB0_WRCLI20__MIN_BW__SHIFT 0x16 1562 #define DAGB0_WRCLI20__OSD_LIMITER_ENABLE__SHIFT 0x19 1563 #define DAGB0_WRCLI20__MAX_OSD__SHIFT 0x1a 1564 #define DAGB0_WRCLI20__VIRT_CHAN_MASK 0x00000007L 1565 #define DAGB0_WRCLI20__CHECK_TLB_CREDIT_MASK 0x00000008L 1566 #define DAGB0_WRCLI20__URG_HIGH_MASK 0x000000F0L 1567 #define DAGB0_WRCLI20__URG_LOW_MASK 0x00000F00L 1568 #define DAGB0_WRCLI20__MAX_BW_ENABLE_MASK 0x00001000L 1569 #define DAGB0_WRCLI20__MAX_BW_MASK 0x001FE000L 1570 #define DAGB0_WRCLI20__MIN_BW_ENABLE_MASK 0x00200000L 1571 #define DAGB0_WRCLI20__MIN_BW_MASK 0x01C00000L 1572 #define DAGB0_WRCLI20__OSD_LIMITER_ENABLE_MASK 0x02000000L 1573 #define DAGB0_WRCLI20__MAX_OSD_MASK 0xFC000000L 1574 //DAGB0_WRCLI21 1575 #define DAGB0_WRCLI21__VIRT_CHAN__SHIFT 0x0 1576 #define DAGB0_WRCLI21__CHECK_TLB_CREDIT__SHIFT 0x3 1577 #define DAGB0_WRCLI21__URG_HIGH__SHIFT 0x4 1578 #define DAGB0_WRCLI21__URG_LOW__SHIFT 0x8 1579 #define DAGB0_WRCLI21__MAX_BW_ENABLE__SHIFT 0xc 1580 #define DAGB0_WRCLI21__MAX_BW__SHIFT 0xd 1581 #define DAGB0_WRCLI21__MIN_BW_ENABLE__SHIFT 0x15 1582 #define DAGB0_WRCLI21__MIN_BW__SHIFT 0x16 1583 #define DAGB0_WRCLI21__OSD_LIMITER_ENABLE__SHIFT 0x19 1584 #define DAGB0_WRCLI21__MAX_OSD__SHIFT 0x1a 1585 #define DAGB0_WRCLI21__VIRT_CHAN_MASK 0x00000007L 1586 #define DAGB0_WRCLI21__CHECK_TLB_CREDIT_MASK 0x00000008L 1587 #define DAGB0_WRCLI21__URG_HIGH_MASK 0x000000F0L 1588 #define DAGB0_WRCLI21__URG_LOW_MASK 0x00000F00L 1589 #define DAGB0_WRCLI21__MAX_BW_ENABLE_MASK 0x00001000L 1590 #define DAGB0_WRCLI21__MAX_BW_MASK 0x001FE000L 1591 #define DAGB0_WRCLI21__MIN_BW_ENABLE_MASK 0x00200000L 1592 #define DAGB0_WRCLI21__MIN_BW_MASK 0x01C00000L 1593 #define DAGB0_WRCLI21__OSD_LIMITER_ENABLE_MASK 0x02000000L 1594 #define DAGB0_WRCLI21__MAX_OSD_MASK 0xFC000000L 1595 //DAGB0_WRCLI22 1596 #define DAGB0_WRCLI22__VIRT_CHAN__SHIFT 0x0 1597 #define DAGB0_WRCLI22__CHECK_TLB_CREDIT__SHIFT 0x3 1598 #define DAGB0_WRCLI22__URG_HIGH__SHIFT 0x4 1599 #define DAGB0_WRCLI22__URG_LOW__SHIFT 0x8 1600 #define DAGB0_WRCLI22__MAX_BW_ENABLE__SHIFT 0xc 1601 #define DAGB0_WRCLI22__MAX_BW__SHIFT 0xd 1602 #define DAGB0_WRCLI22__MIN_BW_ENABLE__SHIFT 0x15 1603 #define DAGB0_WRCLI22__MIN_BW__SHIFT 0x16 1604 #define DAGB0_WRCLI22__OSD_LIMITER_ENABLE__SHIFT 0x19 1605 #define DAGB0_WRCLI22__MAX_OSD__SHIFT 0x1a 1606 #define DAGB0_WRCLI22__VIRT_CHAN_MASK 0x00000007L 1607 #define DAGB0_WRCLI22__CHECK_TLB_CREDIT_MASK 0x00000008L 1608 #define DAGB0_WRCLI22__URG_HIGH_MASK 0x000000F0L 1609 #define DAGB0_WRCLI22__URG_LOW_MASK 0x00000F00L 1610 #define DAGB0_WRCLI22__MAX_BW_ENABLE_MASK 0x00001000L 1611 #define DAGB0_WRCLI22__MAX_BW_MASK 0x001FE000L 1612 #define DAGB0_WRCLI22__MIN_BW_ENABLE_MASK 0x00200000L 1613 #define DAGB0_WRCLI22__MIN_BW_MASK 0x01C00000L 1614 #define DAGB0_WRCLI22__OSD_LIMITER_ENABLE_MASK 0x02000000L 1615 #define DAGB0_WRCLI22__MAX_OSD_MASK 0xFC000000L 1616 //DAGB0_WRCLI23 1617 #define DAGB0_WRCLI23__VIRT_CHAN__SHIFT 0x0 1618 #define DAGB0_WRCLI23__CHECK_TLB_CREDIT__SHIFT 0x3 1619 #define DAGB0_WRCLI23__URG_HIGH__SHIFT 0x4 1620 #define DAGB0_WRCLI23__URG_LOW__SHIFT 0x8 1621 #define DAGB0_WRCLI23__MAX_BW_ENABLE__SHIFT 0xc 1622 #define DAGB0_WRCLI23__MAX_BW__SHIFT 0xd 1623 #define DAGB0_WRCLI23__MIN_BW_ENABLE__SHIFT 0x15 1624 #define DAGB0_WRCLI23__MIN_BW__SHIFT 0x16 1625 #define DAGB0_WRCLI23__OSD_LIMITER_ENABLE__SHIFT 0x19 1626 #define DAGB0_WRCLI23__MAX_OSD__SHIFT 0x1a 1627 #define DAGB0_WRCLI23__VIRT_CHAN_MASK 0x00000007L 1628 #define DAGB0_WRCLI23__CHECK_TLB_CREDIT_MASK 0x00000008L 1629 #define DAGB0_WRCLI23__URG_HIGH_MASK 0x000000F0L 1630 #define DAGB0_WRCLI23__URG_LOW_MASK 0x00000F00L 1631 #define DAGB0_WRCLI23__MAX_BW_ENABLE_MASK 0x00001000L 1632 #define DAGB0_WRCLI23__MAX_BW_MASK 0x001FE000L 1633 #define DAGB0_WRCLI23__MIN_BW_ENABLE_MASK 0x00200000L 1634 #define DAGB0_WRCLI23__MIN_BW_MASK 0x01C00000L 1635 #define DAGB0_WRCLI23__OSD_LIMITER_ENABLE_MASK 0x02000000L 1636 #define DAGB0_WRCLI23__MAX_OSD_MASK 0xFC000000L 1637 //DAGB0_WRCLI24 1638 #define DAGB0_WRCLI24__VIRT_CHAN__SHIFT 0x0 1639 #define DAGB0_WRCLI24__CHECK_TLB_CREDIT__SHIFT 0x3 1640 #define DAGB0_WRCLI24__URG_HIGH__SHIFT 0x4 1641 #define DAGB0_WRCLI24__URG_LOW__SHIFT 0x8 1642 #define DAGB0_WRCLI24__MAX_BW_ENABLE__SHIFT 0xc 1643 #define DAGB0_WRCLI24__MAX_BW__SHIFT 0xd 1644 #define DAGB0_WRCLI24__MIN_BW_ENABLE__SHIFT 0x15 1645 #define DAGB0_WRCLI24__MIN_BW__SHIFT 0x16 1646 #define DAGB0_WRCLI24__OSD_LIMITER_ENABLE__SHIFT 0x19 1647 #define DAGB0_WRCLI24__MAX_OSD__SHIFT 0x1a 1648 #define DAGB0_WRCLI24__VIRT_CHAN_MASK 0x00000007L 1649 #define DAGB0_WRCLI24__CHECK_TLB_CREDIT_MASK 0x00000008L 1650 #define DAGB0_WRCLI24__URG_HIGH_MASK 0x000000F0L 1651 #define DAGB0_WRCLI24__URG_LOW_MASK 0x00000F00L 1652 #define DAGB0_WRCLI24__MAX_BW_ENABLE_MASK 0x00001000L 1653 #define DAGB0_WRCLI24__MAX_BW_MASK 0x001FE000L 1654 #define DAGB0_WRCLI24__MIN_BW_ENABLE_MASK 0x00200000L 1655 #define DAGB0_WRCLI24__MIN_BW_MASK 0x01C00000L 1656 #define DAGB0_WRCLI24__OSD_LIMITER_ENABLE_MASK 0x02000000L 1657 #define DAGB0_WRCLI24__MAX_OSD_MASK 0xFC000000L 1658 //DAGB0_WRCLI25 1659 #define DAGB0_WRCLI25__VIRT_CHAN__SHIFT 0x0 1660 #define DAGB0_WRCLI25__CHECK_TLB_CREDIT__SHIFT 0x3 1661 #define DAGB0_WRCLI25__URG_HIGH__SHIFT 0x4 1662 #define DAGB0_WRCLI25__URG_LOW__SHIFT 0x8 1663 #define DAGB0_WRCLI25__MAX_BW_ENABLE__SHIFT 0xc 1664 #define DAGB0_WRCLI25__MAX_BW__SHIFT 0xd 1665 #define DAGB0_WRCLI25__MIN_BW_ENABLE__SHIFT 0x15 1666 #define DAGB0_WRCLI25__MIN_BW__SHIFT 0x16 1667 #define DAGB0_WRCLI25__OSD_LIMITER_ENABLE__SHIFT 0x19 1668 #define DAGB0_WRCLI25__MAX_OSD__SHIFT 0x1a 1669 #define DAGB0_WRCLI25__VIRT_CHAN_MASK 0x00000007L 1670 #define DAGB0_WRCLI25__CHECK_TLB_CREDIT_MASK 0x00000008L 1671 #define DAGB0_WRCLI25__URG_HIGH_MASK 0x000000F0L 1672 #define DAGB0_WRCLI25__URG_LOW_MASK 0x00000F00L 1673 #define DAGB0_WRCLI25__MAX_BW_ENABLE_MASK 0x00001000L 1674 #define DAGB0_WRCLI25__MAX_BW_MASK 0x001FE000L 1675 #define DAGB0_WRCLI25__MIN_BW_ENABLE_MASK 0x00200000L 1676 #define DAGB0_WRCLI25__MIN_BW_MASK 0x01C00000L 1677 #define DAGB0_WRCLI25__OSD_LIMITER_ENABLE_MASK 0x02000000L 1678 #define DAGB0_WRCLI25__MAX_OSD_MASK 0xFC000000L 1679 //DAGB0_WRCLI26 1680 #define DAGB0_WRCLI26__VIRT_CHAN__SHIFT 0x0 1681 #define DAGB0_WRCLI26__CHECK_TLB_CREDIT__SHIFT 0x3 1682 #define DAGB0_WRCLI26__URG_HIGH__SHIFT 0x4 1683 #define DAGB0_WRCLI26__URG_LOW__SHIFT 0x8 1684 #define DAGB0_WRCLI26__MAX_BW_ENABLE__SHIFT 0xc 1685 #define DAGB0_WRCLI26__MAX_BW__SHIFT 0xd 1686 #define DAGB0_WRCLI26__MIN_BW_ENABLE__SHIFT 0x15 1687 #define DAGB0_WRCLI26__MIN_BW__SHIFT 0x16 1688 #define DAGB0_WRCLI26__OSD_LIMITER_ENABLE__SHIFT 0x19 1689 #define DAGB0_WRCLI26__MAX_OSD__SHIFT 0x1a 1690 #define DAGB0_WRCLI26__VIRT_CHAN_MASK 0x00000007L 1691 #define DAGB0_WRCLI26__CHECK_TLB_CREDIT_MASK 0x00000008L 1692 #define DAGB0_WRCLI26__URG_HIGH_MASK 0x000000F0L 1693 #define DAGB0_WRCLI26__URG_LOW_MASK 0x00000F00L 1694 #define DAGB0_WRCLI26__MAX_BW_ENABLE_MASK 0x00001000L 1695 #define DAGB0_WRCLI26__MAX_BW_MASK 0x001FE000L 1696 #define DAGB0_WRCLI26__MIN_BW_ENABLE_MASK 0x00200000L 1697 #define DAGB0_WRCLI26__MIN_BW_MASK 0x01C00000L 1698 #define DAGB0_WRCLI26__OSD_LIMITER_ENABLE_MASK 0x02000000L 1699 #define DAGB0_WRCLI26__MAX_OSD_MASK 0xFC000000L 1700 //DAGB0_WRCLI27 1701 #define DAGB0_WRCLI27__VIRT_CHAN__SHIFT 0x0 1702 #define DAGB0_WRCLI27__CHECK_TLB_CREDIT__SHIFT 0x3 1703 #define DAGB0_WRCLI27__URG_HIGH__SHIFT 0x4 1704 #define DAGB0_WRCLI27__URG_LOW__SHIFT 0x8 1705 #define DAGB0_WRCLI27__MAX_BW_ENABLE__SHIFT 0xc 1706 #define DAGB0_WRCLI27__MAX_BW__SHIFT 0xd 1707 #define DAGB0_WRCLI27__MIN_BW_ENABLE__SHIFT 0x15 1708 #define DAGB0_WRCLI27__MIN_BW__SHIFT 0x16 1709 #define DAGB0_WRCLI27__OSD_LIMITER_ENABLE__SHIFT 0x19 1710 #define DAGB0_WRCLI27__MAX_OSD__SHIFT 0x1a 1711 #define DAGB0_WRCLI27__VIRT_CHAN_MASK 0x00000007L 1712 #define DAGB0_WRCLI27__CHECK_TLB_CREDIT_MASK 0x00000008L 1713 #define DAGB0_WRCLI27__URG_HIGH_MASK 0x000000F0L 1714 #define DAGB0_WRCLI27__URG_LOW_MASK 0x00000F00L 1715 #define DAGB0_WRCLI27__MAX_BW_ENABLE_MASK 0x00001000L 1716 #define DAGB0_WRCLI27__MAX_BW_MASK 0x001FE000L 1717 #define DAGB0_WRCLI27__MIN_BW_ENABLE_MASK 0x00200000L 1718 #define DAGB0_WRCLI27__MIN_BW_MASK 0x01C00000L 1719 #define DAGB0_WRCLI27__OSD_LIMITER_ENABLE_MASK 0x02000000L 1720 #define DAGB0_WRCLI27__MAX_OSD_MASK 0xFC000000L 1721 //DAGB0_WRCLI28 1722 #define DAGB0_WRCLI28__VIRT_CHAN__SHIFT 0x0 1723 #define DAGB0_WRCLI28__CHECK_TLB_CREDIT__SHIFT 0x3 1724 #define DAGB0_WRCLI28__URG_HIGH__SHIFT 0x4 1725 #define DAGB0_WRCLI28__URG_LOW__SHIFT 0x8 1726 #define DAGB0_WRCLI28__MAX_BW_ENABLE__SHIFT 0xc 1727 #define DAGB0_WRCLI28__MAX_BW__SHIFT 0xd 1728 #define DAGB0_WRCLI28__MIN_BW_ENABLE__SHIFT 0x15 1729 #define DAGB0_WRCLI28__MIN_BW__SHIFT 0x16 1730 #define DAGB0_WRCLI28__OSD_LIMITER_ENABLE__SHIFT 0x19 1731 #define DAGB0_WRCLI28__MAX_OSD__SHIFT 0x1a 1732 #define DAGB0_WRCLI28__VIRT_CHAN_MASK 0x00000007L 1733 #define DAGB0_WRCLI28__CHECK_TLB_CREDIT_MASK 0x00000008L 1734 #define DAGB0_WRCLI28__URG_HIGH_MASK 0x000000F0L 1735 #define DAGB0_WRCLI28__URG_LOW_MASK 0x00000F00L 1736 #define DAGB0_WRCLI28__MAX_BW_ENABLE_MASK 0x00001000L 1737 #define DAGB0_WRCLI28__MAX_BW_MASK 0x001FE000L 1738 #define DAGB0_WRCLI28__MIN_BW_ENABLE_MASK 0x00200000L 1739 #define DAGB0_WRCLI28__MIN_BW_MASK 0x01C00000L 1740 #define DAGB0_WRCLI28__OSD_LIMITER_ENABLE_MASK 0x02000000L 1741 #define DAGB0_WRCLI28__MAX_OSD_MASK 0xFC000000L 1742 //DAGB0_WRCLI29 1743 #define DAGB0_WRCLI29__VIRT_CHAN__SHIFT 0x0 1744 #define DAGB0_WRCLI29__CHECK_TLB_CREDIT__SHIFT 0x3 1745 #define DAGB0_WRCLI29__URG_HIGH__SHIFT 0x4 1746 #define DAGB0_WRCLI29__URG_LOW__SHIFT 0x8 1747 #define DAGB0_WRCLI29__MAX_BW_ENABLE__SHIFT 0xc 1748 #define DAGB0_WRCLI29__MAX_BW__SHIFT 0xd 1749 #define DAGB0_WRCLI29__MIN_BW_ENABLE__SHIFT 0x15 1750 #define DAGB0_WRCLI29__MIN_BW__SHIFT 0x16 1751 #define DAGB0_WRCLI29__OSD_LIMITER_ENABLE__SHIFT 0x19 1752 #define DAGB0_WRCLI29__MAX_OSD__SHIFT 0x1a 1753 #define DAGB0_WRCLI29__VIRT_CHAN_MASK 0x00000007L 1754 #define DAGB0_WRCLI29__CHECK_TLB_CREDIT_MASK 0x00000008L 1755 #define DAGB0_WRCLI29__URG_HIGH_MASK 0x000000F0L 1756 #define DAGB0_WRCLI29__URG_LOW_MASK 0x00000F00L 1757 #define DAGB0_WRCLI29__MAX_BW_ENABLE_MASK 0x00001000L 1758 #define DAGB0_WRCLI29__MAX_BW_MASK 0x001FE000L 1759 #define DAGB0_WRCLI29__MIN_BW_ENABLE_MASK 0x00200000L 1760 #define DAGB0_WRCLI29__MIN_BW_MASK 0x01C00000L 1761 #define DAGB0_WRCLI29__OSD_LIMITER_ENABLE_MASK 0x02000000L 1762 #define DAGB0_WRCLI29__MAX_OSD_MASK 0xFC000000L 1763 //DAGB0_WRCLI30 1764 #define DAGB0_WRCLI30__VIRT_CHAN__SHIFT 0x0 1765 #define DAGB0_WRCLI30__CHECK_TLB_CREDIT__SHIFT 0x3 1766 #define DAGB0_WRCLI30__URG_HIGH__SHIFT 0x4 1767 #define DAGB0_WRCLI30__URG_LOW__SHIFT 0x8 1768 #define DAGB0_WRCLI30__MAX_BW_ENABLE__SHIFT 0xc 1769 #define DAGB0_WRCLI30__MAX_BW__SHIFT 0xd 1770 #define DAGB0_WRCLI30__MIN_BW_ENABLE__SHIFT 0x15 1771 #define DAGB0_WRCLI30__MIN_BW__SHIFT 0x16 1772 #define DAGB0_WRCLI30__OSD_LIMITER_ENABLE__SHIFT 0x19 1773 #define DAGB0_WRCLI30__MAX_OSD__SHIFT 0x1a 1774 #define DAGB0_WRCLI30__VIRT_CHAN_MASK 0x00000007L 1775 #define DAGB0_WRCLI30__CHECK_TLB_CREDIT_MASK 0x00000008L 1776 #define DAGB0_WRCLI30__URG_HIGH_MASK 0x000000F0L 1777 #define DAGB0_WRCLI30__URG_LOW_MASK 0x00000F00L 1778 #define DAGB0_WRCLI30__MAX_BW_ENABLE_MASK 0x00001000L 1779 #define DAGB0_WRCLI30__MAX_BW_MASK 0x001FE000L 1780 #define DAGB0_WRCLI30__MIN_BW_ENABLE_MASK 0x00200000L 1781 #define DAGB0_WRCLI30__MIN_BW_MASK 0x01C00000L 1782 #define DAGB0_WRCLI30__OSD_LIMITER_ENABLE_MASK 0x02000000L 1783 #define DAGB0_WRCLI30__MAX_OSD_MASK 0xFC000000L 1784 //DAGB0_WR_CNTL 1785 #define DAGB0_WR_CNTL__SCLK_FREQ__SHIFT 0x0 1786 #define DAGB0_WR_CNTL__CLI_MAX_BW_WINDOW__SHIFT 0x4 1787 #define DAGB0_WR_CNTL__VC_MAX_BW_WINDOW__SHIFT 0xa 1788 #define DAGB0_WR_CNTL__IO_LEVEL_OVERRIDE_ENABLE__SHIFT 0x10 1789 #define DAGB0_WR_CNTL__IO_LEVEL__SHIFT 0x11 1790 #define DAGB0_WR_CNTL__IO_LEVEL_COMPLY_VC__SHIFT 0x14 1791 #define DAGB0_WR_CNTL__SHARE_VC_NUM__SHIFT 0x17 1792 #define DAGB0_WR_CNTL__SCLK_FREQ_MASK 0x0000000FL 1793 #define DAGB0_WR_CNTL__CLI_MAX_BW_WINDOW_MASK 0x000003F0L 1794 #define DAGB0_WR_CNTL__VC_MAX_BW_WINDOW_MASK 0x0000FC00L 1795 #define DAGB0_WR_CNTL__IO_LEVEL_OVERRIDE_ENABLE_MASK 0x00010000L 1796 #define DAGB0_WR_CNTL__IO_LEVEL_MASK 0x000E0000L 1797 #define DAGB0_WR_CNTL__IO_LEVEL_COMPLY_VC_MASK 0x00700000L 1798 #define DAGB0_WR_CNTL__SHARE_VC_NUM_MASK 0x03800000L 1799 //DAGB0_WR_GMI_CNTL 1800 #define DAGB0_WR_GMI_CNTL__EA_CREDIT__SHIFT 0x0 1801 #define DAGB0_WR_GMI_CNTL__LEVEL__SHIFT 0x6 1802 #define DAGB0_WR_GMI_CNTL__MAX_BURST__SHIFT 0x9 1803 #define DAGB0_WR_GMI_CNTL__LAZY_TIMER__SHIFT 0xd 1804 #define DAGB0_WR_GMI_CNTL__EA_CREDIT_MASK 0x0000003FL 1805 #define DAGB0_WR_GMI_CNTL__LEVEL_MASK 0x000001C0L 1806 #define DAGB0_WR_GMI_CNTL__MAX_BURST_MASK 0x00001E00L 1807 #define DAGB0_WR_GMI_CNTL__LAZY_TIMER_MASK 0x0001E000L 1808 //DAGB0_WR_ADDR_DAGB 1809 #define DAGB0_WR_ADDR_DAGB__DAGB_ENABLE__SHIFT 0x0 1810 #define DAGB0_WR_ADDR_DAGB__ENABLE_JUMP_AHEAD__SHIFT 0x3 1811 #define DAGB0_WR_ADDR_DAGB__DISABLE_SELF_INIT__SHIFT 0x6 1812 #define DAGB0_WR_ADDR_DAGB__WHOAMI__SHIFT 0x7 1813 #define DAGB0_WR_ADDR_DAGB__JUMP_MODE__SHIFT 0xd 1814 #define DAGB0_WR_ADDR_DAGB__DAGB_ENABLE_MASK 0x00000007L 1815 #define DAGB0_WR_ADDR_DAGB__ENABLE_JUMP_AHEAD_MASK 0x00000038L 1816 #define DAGB0_WR_ADDR_DAGB__DISABLE_SELF_INIT_MASK 0x00000040L 1817 #define DAGB0_WR_ADDR_DAGB__WHOAMI_MASK 0x00001F80L 1818 #define DAGB0_WR_ADDR_DAGB__JUMP_MODE_MASK 0x00002000L 1819 //DAGB0_WR_OUTPUT_DAGB_MAX_BURST 1820 #define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC0__SHIFT 0x0 1821 #define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC1__SHIFT 0x4 1822 #define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC2__SHIFT 0x8 1823 #define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC3__SHIFT 0xc 1824 #define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC4__SHIFT 0x10 1825 #define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC5__SHIFT 0x14 1826 #define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC6__SHIFT 0x18 1827 #define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC7__SHIFT 0x1c 1828 #define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC0_MASK 0x0000000FL 1829 #define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC1_MASK 0x000000F0L 1830 #define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC2_MASK 0x00000F00L 1831 #define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC3_MASK 0x0000F000L 1832 #define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC4_MASK 0x000F0000L 1833 #define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC5_MASK 0x00F00000L 1834 #define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC6_MASK 0x0F000000L 1835 #define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC7_MASK 0xF0000000L 1836 //DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER 1837 #define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC0__SHIFT 0x0 1838 #define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC1__SHIFT 0x4 1839 #define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC2__SHIFT 0x8 1840 #define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC3__SHIFT 0xc 1841 #define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC4__SHIFT 0x10 1842 #define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC5__SHIFT 0x14 1843 #define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC6__SHIFT 0x18 1844 #define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC7__SHIFT 0x1c 1845 #define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC0_MASK 0x0000000FL 1846 #define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC1_MASK 0x000000F0L 1847 #define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC2_MASK 0x00000F00L 1848 #define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC3_MASK 0x0000F000L 1849 #define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC4_MASK 0x000F0000L 1850 #define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC5_MASK 0x00F00000L 1851 #define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC6_MASK 0x0F000000L 1852 #define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC7_MASK 0xF0000000L 1853 //DAGB0_WR_CGTT_CLK_CTRL 1854 #define DAGB0_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 1855 #define DAGB0_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 1856 #define DAGB0_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16 1857 #define DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b 1858 #define DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c 1859 #define DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d 1860 #define DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e 1861 #define DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f 1862 #define DAGB0_WR_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL 1863 #define DAGB0_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L 1864 #define DAGB0_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L 1865 #define DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L 1866 #define DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L 1867 #define DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L 1868 #define DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L 1869 #define DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L 1870 //DAGB0_L1TLB_WR_CGTT_CLK_CTRL 1871 #define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 1872 #define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 1873 #define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16 1874 #define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b 1875 #define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c 1876 #define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d 1877 #define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e 1878 #define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f 1879 #define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL 1880 #define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L 1881 #define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L 1882 #define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L 1883 #define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L 1884 #define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L 1885 #define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L 1886 #define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L 1887 //DAGB0_ATCVM_WR_CGTT_CLK_CTRL 1888 #define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 1889 #define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 1890 #define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16 1891 #define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b 1892 #define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c 1893 #define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d 1894 #define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e 1895 #define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f 1896 #define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL 1897 #define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L 1898 #define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L 1899 #define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L 1900 #define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L 1901 #define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L 1902 #define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L 1903 #define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L 1904 //DAGB0_WR_ADDR_DAGB_MAX_BURST0 1905 #define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT0__SHIFT 0x0 1906 #define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT1__SHIFT 0x4 1907 #define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT2__SHIFT 0x8 1908 #define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT3__SHIFT 0xc 1909 #define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT4__SHIFT 0x10 1910 #define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT5__SHIFT 0x14 1911 #define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT6__SHIFT 0x18 1912 #define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT7__SHIFT 0x1c 1913 #define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT0_MASK 0x0000000FL 1914 #define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT1_MASK 0x000000F0L 1915 #define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT2_MASK 0x00000F00L 1916 #define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT3_MASK 0x0000F000L 1917 #define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT4_MASK 0x000F0000L 1918 #define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT5_MASK 0x00F00000L 1919 #define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT6_MASK 0x0F000000L 1920 #define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT7_MASK 0xF0000000L 1921 //DAGB0_WR_ADDR_DAGB_LAZY_TIMER0 1922 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT0__SHIFT 0x0 1923 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT1__SHIFT 0x4 1924 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT2__SHIFT 0x8 1925 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT3__SHIFT 0xc 1926 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT4__SHIFT 0x10 1927 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT5__SHIFT 0x14 1928 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT6__SHIFT 0x18 1929 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT7__SHIFT 0x1c 1930 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT0_MASK 0x0000000FL 1931 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT1_MASK 0x000000F0L 1932 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT2_MASK 0x00000F00L 1933 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT3_MASK 0x0000F000L 1934 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT4_MASK 0x000F0000L 1935 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT5_MASK 0x00F00000L 1936 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT6_MASK 0x0F000000L 1937 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT7_MASK 0xF0000000L 1938 //DAGB0_WR_ADDR_DAGB_MAX_BURST1 1939 #define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT8__SHIFT 0x0 1940 #define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT9__SHIFT 0x4 1941 #define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT10__SHIFT 0x8 1942 #define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT11__SHIFT 0xc 1943 #define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT12__SHIFT 0x10 1944 #define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT13__SHIFT 0x14 1945 #define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT14__SHIFT 0x18 1946 #define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT15__SHIFT 0x1c 1947 #define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT8_MASK 0x0000000FL 1948 #define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT9_MASK 0x000000F0L 1949 #define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT10_MASK 0x00000F00L 1950 #define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT11_MASK 0x0000F000L 1951 #define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT12_MASK 0x000F0000L 1952 #define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT13_MASK 0x00F00000L 1953 #define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT14_MASK 0x0F000000L 1954 #define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT15_MASK 0xF0000000L 1955 //DAGB0_WR_ADDR_DAGB_LAZY_TIMER1 1956 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT8__SHIFT 0x0 1957 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT9__SHIFT 0x4 1958 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT10__SHIFT 0x8 1959 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT11__SHIFT 0xc 1960 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT12__SHIFT 0x10 1961 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT13__SHIFT 0x14 1962 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT14__SHIFT 0x18 1963 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT15__SHIFT 0x1c 1964 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT8_MASK 0x0000000FL 1965 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT9_MASK 0x000000F0L 1966 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT10_MASK 0x00000F00L 1967 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT11_MASK 0x0000F000L 1968 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT12_MASK 0x000F0000L 1969 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT13_MASK 0x00F00000L 1970 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT14_MASK 0x0F000000L 1971 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT15_MASK 0xF0000000L 1972 //DAGB0_WR_ADDR_DAGB_MAX_BURST2 1973 #define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT16__SHIFT 0x0 1974 #define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT17__SHIFT 0x4 1975 #define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT18__SHIFT 0x8 1976 #define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT19__SHIFT 0xc 1977 #define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT20__SHIFT 0x10 1978 #define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT21__SHIFT 0x14 1979 #define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT22__SHIFT 0x18 1980 #define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT23__SHIFT 0x1c 1981 #define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT16_MASK 0x0000000FL 1982 #define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT17_MASK 0x000000F0L 1983 #define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT18_MASK 0x00000F00L 1984 #define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT19_MASK 0x0000F000L 1985 #define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT20_MASK 0x000F0000L 1986 #define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT21_MASK 0x00F00000L 1987 #define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT22_MASK 0x0F000000L 1988 #define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT23_MASK 0xF0000000L 1989 //DAGB0_WR_ADDR_DAGB_LAZY_TIMER2 1990 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT16__SHIFT 0x0 1991 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT17__SHIFT 0x4 1992 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT18__SHIFT 0x8 1993 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT19__SHIFT 0xc 1994 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT20__SHIFT 0x10 1995 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT21__SHIFT 0x14 1996 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT22__SHIFT 0x18 1997 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT23__SHIFT 0x1c 1998 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT16_MASK 0x0000000FL 1999 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT17_MASK 0x000000F0L 2000 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT18_MASK 0x00000F00L 2001 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT19_MASK 0x0000F000L 2002 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT20_MASK 0x000F0000L 2003 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT21_MASK 0x00F00000L 2004 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT22_MASK 0x0F000000L 2005 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT23_MASK 0xF0000000L 2006 //DAGB0_WR_ADDR_DAGB_MAX_BURST3 2007 #define DAGB0_WR_ADDR_DAGB_MAX_BURST3__CLIENT24__SHIFT 0x0 2008 #define DAGB0_WR_ADDR_DAGB_MAX_BURST3__CLIENT25__SHIFT 0x4 2009 #define DAGB0_WR_ADDR_DAGB_MAX_BURST3__CLIENT26__SHIFT 0x8 2010 #define DAGB0_WR_ADDR_DAGB_MAX_BURST3__CLIENT27__SHIFT 0xc 2011 #define DAGB0_WR_ADDR_DAGB_MAX_BURST3__CLIENT28__SHIFT 0x10 2012 #define DAGB0_WR_ADDR_DAGB_MAX_BURST3__CLIENT29__SHIFT 0x14 2013 #define DAGB0_WR_ADDR_DAGB_MAX_BURST3__CLIENT30__SHIFT 0x18 2014 #define DAGB0_WR_ADDR_DAGB_MAX_BURST3__CLIENT31__SHIFT 0x1c 2015 #define DAGB0_WR_ADDR_DAGB_MAX_BURST3__CLIENT24_MASK 0x0000000FL 2016 #define DAGB0_WR_ADDR_DAGB_MAX_BURST3__CLIENT25_MASK 0x000000F0L 2017 #define DAGB0_WR_ADDR_DAGB_MAX_BURST3__CLIENT26_MASK 0x00000F00L 2018 #define DAGB0_WR_ADDR_DAGB_MAX_BURST3__CLIENT27_MASK 0x0000F000L 2019 #define DAGB0_WR_ADDR_DAGB_MAX_BURST3__CLIENT28_MASK 0x000F0000L 2020 #define DAGB0_WR_ADDR_DAGB_MAX_BURST3__CLIENT29_MASK 0x00F00000L 2021 #define DAGB0_WR_ADDR_DAGB_MAX_BURST3__CLIENT30_MASK 0x0F000000L 2022 #define DAGB0_WR_ADDR_DAGB_MAX_BURST3__CLIENT31_MASK 0xF0000000L 2023 //DAGB0_WR_ADDR_DAGB_LAZY_TIMER3 2024 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER3__CLIENT24__SHIFT 0x0 2025 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER3__CLIENT25__SHIFT 0x4 2026 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER3__CLIENT26__SHIFT 0x8 2027 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER3__CLIENT27__SHIFT 0xc 2028 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER3__CLIENT28__SHIFT 0x10 2029 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER3__CLIENT29__SHIFT 0x14 2030 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER3__CLIENT30__SHIFT 0x18 2031 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER3__CLIENT31__SHIFT 0x1c 2032 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER3__CLIENT24_MASK 0x0000000FL 2033 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER3__CLIENT25_MASK 0x000000F0L 2034 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER3__CLIENT26_MASK 0x00000F00L 2035 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER3__CLIENT27_MASK 0x0000F000L 2036 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER3__CLIENT28_MASK 0x000F0000L 2037 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER3__CLIENT29_MASK 0x00F00000L 2038 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER3__CLIENT30_MASK 0x0F000000L 2039 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER3__CLIENT31_MASK 0xF0000000L 2040 //DAGB0_WR_DATA_DAGB 2041 #define DAGB0_WR_DATA_DAGB__DAGB_ENABLE__SHIFT 0x0 2042 #define DAGB0_WR_DATA_DAGB__ENABLE_JUMP_AHEAD__SHIFT 0x3 2043 #define DAGB0_WR_DATA_DAGB__DISABLE_SELF_INIT__SHIFT 0x6 2044 #define DAGB0_WR_DATA_DAGB__WHOAMI__SHIFT 0x7 2045 #define DAGB0_WR_DATA_DAGB__DAGB_ENABLE_MASK 0x00000007L 2046 #define DAGB0_WR_DATA_DAGB__ENABLE_JUMP_AHEAD_MASK 0x00000038L 2047 #define DAGB0_WR_DATA_DAGB__DISABLE_SELF_INIT_MASK 0x00000040L 2048 #define DAGB0_WR_DATA_DAGB__WHOAMI_MASK 0x00001F80L 2049 //DAGB0_WR_DATA_DAGB_MAX_BURST0 2050 #define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT0__SHIFT 0x0 2051 #define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT1__SHIFT 0x4 2052 #define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT2__SHIFT 0x8 2053 #define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT3__SHIFT 0xc 2054 #define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT4__SHIFT 0x10 2055 #define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT5__SHIFT 0x14 2056 #define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT6__SHIFT 0x18 2057 #define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT7__SHIFT 0x1c 2058 #define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT0_MASK 0x0000000FL 2059 #define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT1_MASK 0x000000F0L 2060 #define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT2_MASK 0x00000F00L 2061 #define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT3_MASK 0x0000F000L 2062 #define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT4_MASK 0x000F0000L 2063 #define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT5_MASK 0x00F00000L 2064 #define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT6_MASK 0x0F000000L 2065 #define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT7_MASK 0xF0000000L 2066 //DAGB0_WR_DATA_DAGB_LAZY_TIMER0 2067 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT0__SHIFT 0x0 2068 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT1__SHIFT 0x4 2069 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT2__SHIFT 0x8 2070 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT3__SHIFT 0xc 2071 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT4__SHIFT 0x10 2072 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT5__SHIFT 0x14 2073 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT6__SHIFT 0x18 2074 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT7__SHIFT 0x1c 2075 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT0_MASK 0x0000000FL 2076 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT1_MASK 0x000000F0L 2077 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT2_MASK 0x00000F00L 2078 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT3_MASK 0x0000F000L 2079 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT4_MASK 0x000F0000L 2080 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT5_MASK 0x00F00000L 2081 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT6_MASK 0x0F000000L 2082 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT7_MASK 0xF0000000L 2083 //DAGB0_WR_DATA_DAGB_MAX_BURST1 2084 #define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT8__SHIFT 0x0 2085 #define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT9__SHIFT 0x4 2086 #define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT10__SHIFT 0x8 2087 #define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT11__SHIFT 0xc 2088 #define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT12__SHIFT 0x10 2089 #define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT13__SHIFT 0x14 2090 #define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT14__SHIFT 0x18 2091 #define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT15__SHIFT 0x1c 2092 #define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT8_MASK 0x0000000FL 2093 #define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT9_MASK 0x000000F0L 2094 #define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT10_MASK 0x00000F00L 2095 #define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT11_MASK 0x0000F000L 2096 #define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT12_MASK 0x000F0000L 2097 #define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT13_MASK 0x00F00000L 2098 #define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT14_MASK 0x0F000000L 2099 #define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT15_MASK 0xF0000000L 2100 //DAGB0_WR_DATA_DAGB_LAZY_TIMER1 2101 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT8__SHIFT 0x0 2102 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT9__SHIFT 0x4 2103 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT10__SHIFT 0x8 2104 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT11__SHIFT 0xc 2105 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT12__SHIFT 0x10 2106 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT13__SHIFT 0x14 2107 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT14__SHIFT 0x18 2108 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT15__SHIFT 0x1c 2109 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT8_MASK 0x0000000FL 2110 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT9_MASK 0x000000F0L 2111 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT10_MASK 0x00000F00L 2112 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT11_MASK 0x0000F000L 2113 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT12_MASK 0x000F0000L 2114 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT13_MASK 0x00F00000L 2115 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT14_MASK 0x0F000000L 2116 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT15_MASK 0xF0000000L 2117 //DAGB0_WR_DATA_DAGB_MAX_BURST2 2118 #define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT16__SHIFT 0x0 2119 #define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT17__SHIFT 0x4 2120 #define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT18__SHIFT 0x8 2121 #define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT19__SHIFT 0xc 2122 #define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT20__SHIFT 0x10 2123 #define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT21__SHIFT 0x14 2124 #define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT22__SHIFT 0x18 2125 #define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT23__SHIFT 0x1c 2126 #define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT16_MASK 0x0000000FL 2127 #define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT17_MASK 0x000000F0L 2128 #define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT18_MASK 0x00000F00L 2129 #define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT19_MASK 0x0000F000L 2130 #define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT20_MASK 0x000F0000L 2131 #define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT21_MASK 0x00F00000L 2132 #define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT22_MASK 0x0F000000L 2133 #define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT23_MASK 0xF0000000L 2134 //DAGB0_WR_DATA_DAGB_LAZY_TIMER2 2135 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT16__SHIFT 0x0 2136 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT17__SHIFT 0x4 2137 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT18__SHIFT 0x8 2138 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT19__SHIFT 0xc 2139 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT20__SHIFT 0x10 2140 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT21__SHIFT 0x14 2141 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT22__SHIFT 0x18 2142 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT23__SHIFT 0x1c 2143 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT16_MASK 0x0000000FL 2144 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT17_MASK 0x000000F0L 2145 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT18_MASK 0x00000F00L 2146 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT19_MASK 0x0000F000L 2147 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT20_MASK 0x000F0000L 2148 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT21_MASK 0x00F00000L 2149 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT22_MASK 0x0F000000L 2150 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT23_MASK 0xF0000000L 2151 //DAGB0_WR_DATA_DAGB_MAX_BURST3 2152 #define DAGB0_WR_DATA_DAGB_MAX_BURST3__CLIENT24__SHIFT 0x0 2153 #define DAGB0_WR_DATA_DAGB_MAX_BURST3__CLIENT25__SHIFT 0x4 2154 #define DAGB0_WR_DATA_DAGB_MAX_BURST3__CLIENT26__SHIFT 0x8 2155 #define DAGB0_WR_DATA_DAGB_MAX_BURST3__CLIENT27__SHIFT 0xc 2156 #define DAGB0_WR_DATA_DAGB_MAX_BURST3__CLIENT28__SHIFT 0x10 2157 #define DAGB0_WR_DATA_DAGB_MAX_BURST3__CLIENT29__SHIFT 0x14 2158 #define DAGB0_WR_DATA_DAGB_MAX_BURST3__CLIENT30__SHIFT 0x18 2159 #define DAGB0_WR_DATA_DAGB_MAX_BURST3__CLIENT31__SHIFT 0x1c 2160 #define DAGB0_WR_DATA_DAGB_MAX_BURST3__CLIENT24_MASK 0x0000000FL 2161 #define DAGB0_WR_DATA_DAGB_MAX_BURST3__CLIENT25_MASK 0x000000F0L 2162 #define DAGB0_WR_DATA_DAGB_MAX_BURST3__CLIENT26_MASK 0x00000F00L 2163 #define DAGB0_WR_DATA_DAGB_MAX_BURST3__CLIENT27_MASK 0x0000F000L 2164 #define DAGB0_WR_DATA_DAGB_MAX_BURST3__CLIENT28_MASK 0x000F0000L 2165 #define DAGB0_WR_DATA_DAGB_MAX_BURST3__CLIENT29_MASK 0x00F00000L 2166 #define DAGB0_WR_DATA_DAGB_MAX_BURST3__CLIENT30_MASK 0x0F000000L 2167 #define DAGB0_WR_DATA_DAGB_MAX_BURST3__CLIENT31_MASK 0xF0000000L 2168 //DAGB0_WR_DATA_DAGB_LAZY_TIMER3 2169 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER3__CLIENT24__SHIFT 0x0 2170 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER3__CLIENT25__SHIFT 0x4 2171 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER3__CLIENT26__SHIFT 0x8 2172 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER3__CLIENT27__SHIFT 0xc 2173 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER3__CLIENT28__SHIFT 0x10 2174 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER3__CLIENT29__SHIFT 0x14 2175 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER3__CLIENT30__SHIFT 0x18 2176 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER3__CLIENT31__SHIFT 0x1c 2177 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER3__CLIENT24_MASK 0x0000000FL 2178 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER3__CLIENT25_MASK 0x000000F0L 2179 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER3__CLIENT26_MASK 0x00000F00L 2180 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER3__CLIENT27_MASK 0x0000F000L 2181 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER3__CLIENT28_MASK 0x000F0000L 2182 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER3__CLIENT29_MASK 0x00F00000L 2183 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER3__CLIENT30_MASK 0x0F000000L 2184 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER3__CLIENT31_MASK 0xF0000000L 2185 //DAGB0_WR_VC0_CNTL 2186 #define DAGB0_WR_VC0_CNTL__STOR_CREDIT__SHIFT 0x0 2187 #define DAGB0_WR_VC0_CNTL__EA_CREDIT__SHIFT 0x5 2188 #define DAGB0_WR_VC0_CNTL__MAX_BW_ENABLE__SHIFT 0xb 2189 #define DAGB0_WR_VC0_CNTL__MAX_BW__SHIFT 0xc 2190 #define DAGB0_WR_VC0_CNTL__MIN_BW_ENABLE__SHIFT 0x14 2191 #define DAGB0_WR_VC0_CNTL__MIN_BW__SHIFT 0x15 2192 #define DAGB0_WR_VC0_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 2193 #define DAGB0_WR_VC0_CNTL__MAX_OSD__SHIFT 0x19 2194 #define DAGB0_WR_VC0_CNTL__STOR_CREDIT_MASK 0x0000001FL 2195 #define DAGB0_WR_VC0_CNTL__EA_CREDIT_MASK 0x000007E0L 2196 #define DAGB0_WR_VC0_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 2197 #define DAGB0_WR_VC0_CNTL__MAX_BW_MASK 0x000FF000L 2198 #define DAGB0_WR_VC0_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 2199 #define DAGB0_WR_VC0_CNTL__MIN_BW_MASK 0x00E00000L 2200 #define DAGB0_WR_VC0_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 2201 #define DAGB0_WR_VC0_CNTL__MAX_OSD_MASK 0xFE000000L 2202 //DAGB0_WR_VC1_CNTL 2203 #define DAGB0_WR_VC1_CNTL__STOR_CREDIT__SHIFT 0x0 2204 #define DAGB0_WR_VC1_CNTL__EA_CREDIT__SHIFT 0x5 2205 #define DAGB0_WR_VC1_CNTL__MAX_BW_ENABLE__SHIFT 0xb 2206 #define DAGB0_WR_VC1_CNTL__MAX_BW__SHIFT 0xc 2207 #define DAGB0_WR_VC1_CNTL__MIN_BW_ENABLE__SHIFT 0x14 2208 #define DAGB0_WR_VC1_CNTL__MIN_BW__SHIFT 0x15 2209 #define DAGB0_WR_VC1_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 2210 #define DAGB0_WR_VC1_CNTL__MAX_OSD__SHIFT 0x19 2211 #define DAGB0_WR_VC1_CNTL__STOR_CREDIT_MASK 0x0000001FL 2212 #define DAGB0_WR_VC1_CNTL__EA_CREDIT_MASK 0x000007E0L 2213 #define DAGB0_WR_VC1_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 2214 #define DAGB0_WR_VC1_CNTL__MAX_BW_MASK 0x000FF000L 2215 #define DAGB0_WR_VC1_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 2216 #define DAGB0_WR_VC1_CNTL__MIN_BW_MASK 0x00E00000L 2217 #define DAGB0_WR_VC1_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 2218 #define DAGB0_WR_VC1_CNTL__MAX_OSD_MASK 0xFE000000L 2219 //DAGB0_WR_VC2_CNTL 2220 #define DAGB0_WR_VC2_CNTL__STOR_CREDIT__SHIFT 0x0 2221 #define DAGB0_WR_VC2_CNTL__EA_CREDIT__SHIFT 0x5 2222 #define DAGB0_WR_VC2_CNTL__MAX_BW_ENABLE__SHIFT 0xb 2223 #define DAGB0_WR_VC2_CNTL__MAX_BW__SHIFT 0xc 2224 #define DAGB0_WR_VC2_CNTL__MIN_BW_ENABLE__SHIFT 0x14 2225 #define DAGB0_WR_VC2_CNTL__MIN_BW__SHIFT 0x15 2226 #define DAGB0_WR_VC2_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 2227 #define DAGB0_WR_VC2_CNTL__MAX_OSD__SHIFT 0x19 2228 #define DAGB0_WR_VC2_CNTL__STOR_CREDIT_MASK 0x0000001FL 2229 #define DAGB0_WR_VC2_CNTL__EA_CREDIT_MASK 0x000007E0L 2230 #define DAGB0_WR_VC2_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 2231 #define DAGB0_WR_VC2_CNTL__MAX_BW_MASK 0x000FF000L 2232 #define DAGB0_WR_VC2_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 2233 #define DAGB0_WR_VC2_CNTL__MIN_BW_MASK 0x00E00000L 2234 #define DAGB0_WR_VC2_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 2235 #define DAGB0_WR_VC2_CNTL__MAX_OSD_MASK 0xFE000000L 2236 //DAGB0_WR_VC3_CNTL 2237 #define DAGB0_WR_VC3_CNTL__STOR_CREDIT__SHIFT 0x0 2238 #define DAGB0_WR_VC3_CNTL__EA_CREDIT__SHIFT 0x5 2239 #define DAGB0_WR_VC3_CNTL__MAX_BW_ENABLE__SHIFT 0xb 2240 #define DAGB0_WR_VC3_CNTL__MAX_BW__SHIFT 0xc 2241 #define DAGB0_WR_VC3_CNTL__MIN_BW_ENABLE__SHIFT 0x14 2242 #define DAGB0_WR_VC3_CNTL__MIN_BW__SHIFT 0x15 2243 #define DAGB0_WR_VC3_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 2244 #define DAGB0_WR_VC3_CNTL__MAX_OSD__SHIFT 0x19 2245 #define DAGB0_WR_VC3_CNTL__STOR_CREDIT_MASK 0x0000001FL 2246 #define DAGB0_WR_VC3_CNTL__EA_CREDIT_MASK 0x000007E0L 2247 #define DAGB0_WR_VC3_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 2248 #define DAGB0_WR_VC3_CNTL__MAX_BW_MASK 0x000FF000L 2249 #define DAGB0_WR_VC3_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 2250 #define DAGB0_WR_VC3_CNTL__MIN_BW_MASK 0x00E00000L 2251 #define DAGB0_WR_VC3_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 2252 #define DAGB0_WR_VC3_CNTL__MAX_OSD_MASK 0xFE000000L 2253 //DAGB0_WR_VC4_CNTL 2254 #define DAGB0_WR_VC4_CNTL__STOR_CREDIT__SHIFT 0x0 2255 #define DAGB0_WR_VC4_CNTL__EA_CREDIT__SHIFT 0x5 2256 #define DAGB0_WR_VC4_CNTL__MAX_BW_ENABLE__SHIFT 0xb 2257 #define DAGB0_WR_VC4_CNTL__MAX_BW__SHIFT 0xc 2258 #define DAGB0_WR_VC4_CNTL__MIN_BW_ENABLE__SHIFT 0x14 2259 #define DAGB0_WR_VC4_CNTL__MIN_BW__SHIFT 0x15 2260 #define DAGB0_WR_VC4_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 2261 #define DAGB0_WR_VC4_CNTL__MAX_OSD__SHIFT 0x19 2262 #define DAGB0_WR_VC4_CNTL__STOR_CREDIT_MASK 0x0000001FL 2263 #define DAGB0_WR_VC4_CNTL__EA_CREDIT_MASK 0x000007E0L 2264 #define DAGB0_WR_VC4_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 2265 #define DAGB0_WR_VC4_CNTL__MAX_BW_MASK 0x000FF000L 2266 #define DAGB0_WR_VC4_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 2267 #define DAGB0_WR_VC4_CNTL__MIN_BW_MASK 0x00E00000L 2268 #define DAGB0_WR_VC4_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 2269 #define DAGB0_WR_VC4_CNTL__MAX_OSD_MASK 0xFE000000L 2270 //DAGB0_WR_VC5_CNTL 2271 #define DAGB0_WR_VC5_CNTL__STOR_CREDIT__SHIFT 0x0 2272 #define DAGB0_WR_VC5_CNTL__EA_CREDIT__SHIFT 0x5 2273 #define DAGB0_WR_VC5_CNTL__MAX_BW_ENABLE__SHIFT 0xb 2274 #define DAGB0_WR_VC5_CNTL__MAX_BW__SHIFT 0xc 2275 #define DAGB0_WR_VC5_CNTL__MIN_BW_ENABLE__SHIFT 0x14 2276 #define DAGB0_WR_VC5_CNTL__MIN_BW__SHIFT 0x15 2277 #define DAGB0_WR_VC5_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 2278 #define DAGB0_WR_VC5_CNTL__MAX_OSD__SHIFT 0x19 2279 #define DAGB0_WR_VC5_CNTL__STOR_CREDIT_MASK 0x0000001FL 2280 #define DAGB0_WR_VC5_CNTL__EA_CREDIT_MASK 0x000007E0L 2281 #define DAGB0_WR_VC5_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 2282 #define DAGB0_WR_VC5_CNTL__MAX_BW_MASK 0x000FF000L 2283 #define DAGB0_WR_VC5_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 2284 #define DAGB0_WR_VC5_CNTL__MIN_BW_MASK 0x00E00000L 2285 #define DAGB0_WR_VC5_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 2286 #define DAGB0_WR_VC5_CNTL__MAX_OSD_MASK 0xFE000000L 2287 //DAGB0_WR_VC6_CNTL 2288 #define DAGB0_WR_VC6_CNTL__STOR_CREDIT__SHIFT 0x0 2289 #define DAGB0_WR_VC6_CNTL__EA_CREDIT__SHIFT 0x5 2290 #define DAGB0_WR_VC6_CNTL__MAX_BW_ENABLE__SHIFT 0xb 2291 #define DAGB0_WR_VC6_CNTL__MAX_BW__SHIFT 0xc 2292 #define DAGB0_WR_VC6_CNTL__MIN_BW_ENABLE__SHIFT 0x14 2293 #define DAGB0_WR_VC6_CNTL__MIN_BW__SHIFT 0x15 2294 #define DAGB0_WR_VC6_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 2295 #define DAGB0_WR_VC6_CNTL__MAX_OSD__SHIFT 0x19 2296 #define DAGB0_WR_VC6_CNTL__STOR_CREDIT_MASK 0x0000001FL 2297 #define DAGB0_WR_VC6_CNTL__EA_CREDIT_MASK 0x000007E0L 2298 #define DAGB0_WR_VC6_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 2299 #define DAGB0_WR_VC6_CNTL__MAX_BW_MASK 0x000FF000L 2300 #define DAGB0_WR_VC6_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 2301 #define DAGB0_WR_VC6_CNTL__MIN_BW_MASK 0x00E00000L 2302 #define DAGB0_WR_VC6_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 2303 #define DAGB0_WR_VC6_CNTL__MAX_OSD_MASK 0xFE000000L 2304 //DAGB0_WR_VC7_CNTL 2305 #define DAGB0_WR_VC7_CNTL__STOR_CREDIT__SHIFT 0x0 2306 #define DAGB0_WR_VC7_CNTL__EA_CREDIT__SHIFT 0x5 2307 #define DAGB0_WR_VC7_CNTL__MAX_BW_ENABLE__SHIFT 0xb 2308 #define DAGB0_WR_VC7_CNTL__MAX_BW__SHIFT 0xc 2309 #define DAGB0_WR_VC7_CNTL__MIN_BW_ENABLE__SHIFT 0x14 2310 #define DAGB0_WR_VC7_CNTL__MIN_BW__SHIFT 0x15 2311 #define DAGB0_WR_VC7_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 2312 #define DAGB0_WR_VC7_CNTL__MAX_OSD__SHIFT 0x19 2313 #define DAGB0_WR_VC7_CNTL__STOR_CREDIT_MASK 0x0000001FL 2314 #define DAGB0_WR_VC7_CNTL__EA_CREDIT_MASK 0x000007E0L 2315 #define DAGB0_WR_VC7_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 2316 #define DAGB0_WR_VC7_CNTL__MAX_BW_MASK 0x000FF000L 2317 #define DAGB0_WR_VC7_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 2318 #define DAGB0_WR_VC7_CNTL__MIN_BW_MASK 0x00E00000L 2319 #define DAGB0_WR_VC7_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 2320 #define DAGB0_WR_VC7_CNTL__MAX_OSD_MASK 0xFE000000L 2321 //DAGB0_WR_CNTL_MISC 2322 #define DAGB0_WR_CNTL_MISC__STOR_POOL_CREDIT__SHIFT 0x0 2323 #define DAGB0_WR_CNTL_MISC__EA_POOL_CREDIT__SHIFT 0x6 2324 #define DAGB0_WR_CNTL_MISC__IO_EA_CREDIT__SHIFT 0xd 2325 #define DAGB0_WR_CNTL_MISC__STOR_CC_LEGACY_MODE__SHIFT 0x13 2326 #define DAGB0_WR_CNTL_MISC__EA_CC_LEGACY_MODE__SHIFT 0x14 2327 #define DAGB0_WR_CNTL_MISC__UTCL2_CID__SHIFT 0x15 2328 #define DAGB0_WR_CNTL_MISC__HDP_CID__SHIFT 0x1a 2329 #define DAGB0_WR_CNTL_MISC__STOR_POOL_CREDIT_MASK 0x0000003FL 2330 #define DAGB0_WR_CNTL_MISC__EA_POOL_CREDIT_MASK 0x00001FC0L 2331 #define DAGB0_WR_CNTL_MISC__IO_EA_CREDIT_MASK 0x0007E000L 2332 #define DAGB0_WR_CNTL_MISC__STOR_CC_LEGACY_MODE_MASK 0x00080000L 2333 #define DAGB0_WR_CNTL_MISC__EA_CC_LEGACY_MODE_MASK 0x00100000L 2334 #define DAGB0_WR_CNTL_MISC__UTCL2_CID_MASK 0x03E00000L 2335 #define DAGB0_WR_CNTL_MISC__HDP_CID_MASK 0x7C000000L 2336 //DAGB0_WR_TLB_CREDIT 2337 #define DAGB0_WR_TLB_CREDIT__TLB0__SHIFT 0x0 2338 #define DAGB0_WR_TLB_CREDIT__TLB1__SHIFT 0x5 2339 #define DAGB0_WR_TLB_CREDIT__TLB2__SHIFT 0xa 2340 #define DAGB0_WR_TLB_CREDIT__TLB3__SHIFT 0xf 2341 #define DAGB0_WR_TLB_CREDIT__TLB4__SHIFT 0x14 2342 #define DAGB0_WR_TLB_CREDIT__TLB5__SHIFT 0x19 2343 #define DAGB0_WR_TLB_CREDIT__TLB0_MASK 0x0000001FL 2344 #define DAGB0_WR_TLB_CREDIT__TLB1_MASK 0x000003E0L 2345 #define DAGB0_WR_TLB_CREDIT__TLB2_MASK 0x00007C00L 2346 #define DAGB0_WR_TLB_CREDIT__TLB3_MASK 0x000F8000L 2347 #define DAGB0_WR_TLB_CREDIT__TLB4_MASK 0x01F00000L 2348 #define DAGB0_WR_TLB_CREDIT__TLB5_MASK 0x3E000000L 2349 //DAGB0_WR_DATA_CREDIT 2350 #define DAGB0_WR_DATA_CREDIT__DLOCK_VC_CREDITS__SHIFT 0x0 2351 #define DAGB0_WR_DATA_CREDIT__LARGE_BURST_CREDITS__SHIFT 0x8 2352 #define DAGB0_WR_DATA_CREDIT__MIDDLE_BURST_CREDITS__SHIFT 0x10 2353 #define DAGB0_WR_DATA_CREDIT__SMALL_BURST_CREDITS__SHIFT 0x18 2354 #define DAGB0_WR_DATA_CREDIT__DLOCK_VC_CREDITS_MASK 0x000000FFL 2355 #define DAGB0_WR_DATA_CREDIT__LARGE_BURST_CREDITS_MASK 0x0000FF00L 2356 #define DAGB0_WR_DATA_CREDIT__MIDDLE_BURST_CREDITS_MASK 0x00FF0000L 2357 #define DAGB0_WR_DATA_CREDIT__SMALL_BURST_CREDITS_MASK 0xFF000000L 2358 //DAGB0_WR_MISC_CREDIT 2359 #define DAGB0_WR_MISC_CREDIT__ATOMIC_CREDIT__SHIFT 0x0 2360 #define DAGB0_WR_MISC_CREDIT__DLOCK_VC_NUM__SHIFT 0x6 2361 #define DAGB0_WR_MISC_CREDIT__OSD_CREDIT__SHIFT 0x9 2362 #define DAGB0_WR_MISC_CREDIT__OSD_DLOCK_CREDIT__SHIFT 0x10 2363 #define DAGB0_WR_MISC_CREDIT__ATOMIC_CREDIT_MASK 0x0000003FL 2364 #define DAGB0_WR_MISC_CREDIT__DLOCK_VC_NUM_MASK 0x000001C0L 2365 #define DAGB0_WR_MISC_CREDIT__OSD_CREDIT_MASK 0x0000FE00L 2366 #define DAGB0_WR_MISC_CREDIT__OSD_DLOCK_CREDIT_MASK 0x007F0000L 2367 //DAGB0_WR_OSD_CREDIT_CNTL1 2368 #define DAGB0_WR_OSD_CREDIT_CNTL1__VC0_CREDIT__SHIFT 0x0 2369 #define DAGB0_WR_OSD_CREDIT_CNTL1__VC1_CREDIT__SHIFT 0x4 2370 #define DAGB0_WR_OSD_CREDIT_CNTL1__VC2_CREDIT__SHIFT 0x8 2371 #define DAGB0_WR_OSD_CREDIT_CNTL1__VC3_CREDIT__SHIFT 0xc 2372 #define DAGB0_WR_OSD_CREDIT_CNTL1__IO_CREDIT__SHIFT 0x10 2373 #define DAGB0_WR_OSD_CREDIT_CNTL1__GMI_CREDIT__SHIFT 0x14 2374 #define DAGB0_WR_OSD_CREDIT_CNTL1__POOL_CREDIT__SHIFT 0x18 2375 #define DAGB0_WR_OSD_CREDIT_CNTL1__VC0_CREDIT_MASK 0x0000000FL 2376 #define DAGB0_WR_OSD_CREDIT_CNTL1__VC1_CREDIT_MASK 0x000000F0L 2377 #define DAGB0_WR_OSD_CREDIT_CNTL1__VC2_CREDIT_MASK 0x00000F00L 2378 #define DAGB0_WR_OSD_CREDIT_CNTL1__VC3_CREDIT_MASK 0x0000F000L 2379 #define DAGB0_WR_OSD_CREDIT_CNTL1__IO_CREDIT_MASK 0x000F0000L 2380 #define DAGB0_WR_OSD_CREDIT_CNTL1__GMI_CREDIT_MASK 0x00F00000L 2381 #define DAGB0_WR_OSD_CREDIT_CNTL1__POOL_CREDIT_MASK 0x3F000000L 2382 //DAGB0_WR_OSD_CREDIT_CNTL2 2383 #define DAGB0_WR_OSD_CREDIT_CNTL2__CREDIT_MARGIN__SHIFT 0x0 2384 #define DAGB0_WR_OSD_CREDIT_CNTL2__ENABLE_LEGACY__SHIFT 0x4 2385 #define DAGB0_WR_OSD_CREDIT_CNTL2__CREDIT_MARGIN_MASK 0x0000000FL 2386 #define DAGB0_WR_OSD_CREDIT_CNTL2__ENABLE_LEGACY_MASK 0x00000010L 2387 //DAGB0_WR_DATA_FIFO_CREDIT_CNTL1 2388 #define DAGB0_WR_DATA_FIFO_CREDIT_CNTL1__VC0_CREDIT__SHIFT 0x0 2389 #define DAGB0_WR_DATA_FIFO_CREDIT_CNTL1__VC1_CREDIT__SHIFT 0x5 2390 #define DAGB0_WR_DATA_FIFO_CREDIT_CNTL1__VC2_CREDIT__SHIFT 0xa 2391 #define DAGB0_WR_DATA_FIFO_CREDIT_CNTL1__VC3_CREDIT__SHIFT 0xf 2392 #define DAGB0_WR_DATA_FIFO_CREDIT_CNTL1__POOL_CREDIT__SHIFT 0x14 2393 #define DAGB0_WR_DATA_FIFO_CREDIT_CNTL1__VC_MODE__SHIFT 0x19 2394 #define DAGB0_WR_DATA_FIFO_CREDIT_CNTL1__FIX_EQ__SHIFT 0x1a 2395 #define DAGB0_WR_DATA_FIFO_CREDIT_CNTL1__FIX0__SHIFT 0x1b 2396 #define DAGB0_WR_DATA_FIFO_CREDIT_CNTL1__FIX1__SHIFT 0x1c 2397 #define DAGB0_WR_DATA_FIFO_CREDIT_CNTL1__FIX2__SHIFT 0x1d 2398 #define DAGB0_WR_DATA_FIFO_CREDIT_CNTL1__VC0_CREDIT_MASK 0x0000001FL 2399 #define DAGB0_WR_DATA_FIFO_CREDIT_CNTL1__VC1_CREDIT_MASK 0x000003E0L 2400 #define DAGB0_WR_DATA_FIFO_CREDIT_CNTL1__VC2_CREDIT_MASK 0x00007C00L 2401 #define DAGB0_WR_DATA_FIFO_CREDIT_CNTL1__VC3_CREDIT_MASK 0x000F8000L 2402 #define DAGB0_WR_DATA_FIFO_CREDIT_CNTL1__POOL_CREDIT_MASK 0x01F00000L 2403 #define DAGB0_WR_DATA_FIFO_CREDIT_CNTL1__VC_MODE_MASK 0x02000000L 2404 #define DAGB0_WR_DATA_FIFO_CREDIT_CNTL1__FIX_EQ_MASK 0x04000000L 2405 #define DAGB0_WR_DATA_FIFO_CREDIT_CNTL1__FIX0_MASK 0x08000000L 2406 #define DAGB0_WR_DATA_FIFO_CREDIT_CNTL1__FIX1_MASK 0x10000000L 2407 #define DAGB0_WR_DATA_FIFO_CREDIT_CNTL1__FIX2_MASK 0x20000000L 2408 //DAGB0_WR_DATA_FIFO_CREDIT_CNTL2 2409 #define DAGB0_WR_DATA_FIFO_CREDIT_CNTL2__VC0_MAX_LENGTH__SHIFT 0x0 2410 #define DAGB0_WR_DATA_FIFO_CREDIT_CNTL2__VC1_MAX_LENGTH__SHIFT 0x4 2411 #define DAGB0_WR_DATA_FIFO_CREDIT_CNTL2__VC2_MAX_LENGTH__SHIFT 0x8 2412 #define DAGB0_WR_DATA_FIFO_CREDIT_CNTL2__VC3_MAX_LENGTH__SHIFT 0xc 2413 #define DAGB0_WR_DATA_FIFO_CREDIT_CNTL2__VC4_MAX_LENGTH__SHIFT 0x10 2414 #define DAGB0_WR_DATA_FIFO_CREDIT_CNTL2__VC0_MAX_LENGTH_MASK 0x0000000FL 2415 #define DAGB0_WR_DATA_FIFO_CREDIT_CNTL2__VC1_MAX_LENGTH_MASK 0x000000F0L 2416 #define DAGB0_WR_DATA_FIFO_CREDIT_CNTL2__VC2_MAX_LENGTH_MASK 0x00000F00L 2417 #define DAGB0_WR_DATA_FIFO_CREDIT_CNTL2__VC3_MAX_LENGTH_MASK 0x0000F000L 2418 #define DAGB0_WR_DATA_FIFO_CREDIT_CNTL2__VC4_MAX_LENGTH_MASK 0x000F0000L 2419 //DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1 2420 #define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC0_CREDIT__SHIFT 0x0 2421 #define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC1_CREDIT__SHIFT 0x5 2422 #define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC2_CREDIT__SHIFT 0xa 2423 #define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC3_CREDIT__SHIFT 0xf 2424 #define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__POOL_CREDIT__SHIFT 0x14 2425 #define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC_MODE__SHIFT 0x19 2426 #define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX_EQ__SHIFT 0x1a 2427 #define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX0__SHIFT 0x1b 2428 #define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX1__SHIFT 0x1c 2429 #define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX2__SHIFT 0x1d 2430 #define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC0_CREDIT_MASK 0x0000001FL 2431 #define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC1_CREDIT_MASK 0x000003E0L 2432 #define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC2_CREDIT_MASK 0x00007C00L 2433 #define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC3_CREDIT_MASK 0x000F8000L 2434 #define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__POOL_CREDIT_MASK 0x01F00000L 2435 #define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC_MODE_MASK 0x02000000L 2436 #define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX_EQ_MASK 0x04000000L 2437 #define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX0_MASK 0x08000000L 2438 #define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX1_MASK 0x10000000L 2439 #define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX2_MASK 0x20000000L 2440 //DAGB0_WRCLI_ASK_PENDING 2441 #define DAGB0_WRCLI_ASK_PENDING__BUSY__SHIFT 0x0 2442 #define DAGB0_WRCLI_ASK_PENDING__BUSY_MASK 0xFFFFFFFFL 2443 //DAGB0_WRCLI_GO_PENDING 2444 #define DAGB0_WRCLI_GO_PENDING__BUSY__SHIFT 0x0 2445 #define DAGB0_WRCLI_GO_PENDING__BUSY_MASK 0xFFFFFFFFL 2446 //DAGB0_WRCLI_GBLSEND_PENDING 2447 #define DAGB0_WRCLI_GBLSEND_PENDING__BUSY__SHIFT 0x0 2448 #define DAGB0_WRCLI_GBLSEND_PENDING__BUSY_MASK 0xFFFFFFFFL 2449 //DAGB0_WRCLI_TLB_PENDING 2450 #define DAGB0_WRCLI_TLB_PENDING__BUSY__SHIFT 0x0 2451 #define DAGB0_WRCLI_TLB_PENDING__BUSY_MASK 0xFFFFFFFFL 2452 //DAGB0_WRCLI_OARB_PENDING 2453 #define DAGB0_WRCLI_OARB_PENDING__BUSY__SHIFT 0x0 2454 #define DAGB0_WRCLI_OARB_PENDING__BUSY_MASK 0xFFFFFFFFL 2455 //DAGB0_WRCLI_OSD_PENDING 2456 #define DAGB0_WRCLI_OSD_PENDING__BUSY__SHIFT 0x0 2457 #define DAGB0_WRCLI_OSD_PENDING__BUSY_MASK 0xFFFFFFFFL 2458 //DAGB0_WRCLI_DBUS_ASK_PENDING 2459 #define DAGB0_WRCLI_DBUS_ASK_PENDING__BUSY__SHIFT 0x0 2460 #define DAGB0_WRCLI_DBUS_ASK_PENDING__BUSY_MASK 0xFFFFFFFFL 2461 //DAGB0_WRCLI_DBUS_GO_PENDING 2462 #define DAGB0_WRCLI_DBUS_GO_PENDING__BUSY__SHIFT 0x0 2463 #define DAGB0_WRCLI_DBUS_GO_PENDING__BUSY_MASK 0xFFFFFFFFL 2464 //DAGB0_WRCLI_GPU_SNOOP_OVERRIDE 2465 #define DAGB0_WRCLI_GPU_SNOOP_OVERRIDE__ENABLE__SHIFT 0x0 2466 #define DAGB0_WRCLI_GPU_SNOOP_OVERRIDE__ENABLE_MASK 0xFFFFFFFFL 2467 //DAGB0_WRCLI_GPU_SNOOP_OVERRIDE_VALUE 2468 #define DAGB0_WRCLI_GPU_SNOOP_OVERRIDE_VALUE__ENABLE__SHIFT 0x0 2469 #define DAGB0_WRCLI_GPU_SNOOP_OVERRIDE_VALUE__ENABLE_MASK 0xFFFFFFFFL 2470 //DAGB0_DAGB_DLY 2471 #define DAGB0_DAGB_DLY__DLY__SHIFT 0x0 2472 #define DAGB0_DAGB_DLY__CLI__SHIFT 0x8 2473 #define DAGB0_DAGB_DLY__POS__SHIFT 0x10 2474 #define DAGB0_DAGB_DLY__DLY_MASK 0x000000FFL 2475 #define DAGB0_DAGB_DLY__CLI_MASK 0x0000FF00L 2476 #define DAGB0_DAGB_DLY__POS_MASK 0x000F0000L 2477 //DAGB0_CNTL_MISC 2478 #define DAGB0_CNTL_MISC__EA_VC0_REMAP__SHIFT 0x0 2479 #define DAGB0_CNTL_MISC__EA_VC1_REMAP__SHIFT 0x3 2480 #define DAGB0_CNTL_MISC__EA_VC2_REMAP__SHIFT 0x6 2481 #define DAGB0_CNTL_MISC__EA_VC3_REMAP__SHIFT 0x9 2482 #define DAGB0_CNTL_MISC__EA_VC4_REMAP__SHIFT 0xc 2483 #define DAGB0_CNTL_MISC__EA_VC5_REMAP__SHIFT 0xf 2484 #define DAGB0_CNTL_MISC__EA_VC6_REMAP__SHIFT 0x12 2485 #define DAGB0_CNTL_MISC__EA_VC7_REMAP__SHIFT 0x15 2486 #define DAGB0_CNTL_MISC__BW_INIT_CYCLE__SHIFT 0x18 2487 #define DAGB0_CNTL_MISC__BW_RW_GAP_CYCLE__SHIFT 0x1e 2488 #define DAGB0_CNTL_MISC__EA_VC0_REMAP_MASK 0x00000007L 2489 #define DAGB0_CNTL_MISC__EA_VC1_REMAP_MASK 0x00000038L 2490 #define DAGB0_CNTL_MISC__EA_VC2_REMAP_MASK 0x000001C0L 2491 #define DAGB0_CNTL_MISC__EA_VC3_REMAP_MASK 0x00000E00L 2492 #define DAGB0_CNTL_MISC__EA_VC4_REMAP_MASK 0x00007000L 2493 #define DAGB0_CNTL_MISC__EA_VC5_REMAP_MASK 0x00038000L 2494 #define DAGB0_CNTL_MISC__EA_VC6_REMAP_MASK 0x001C0000L 2495 #define DAGB0_CNTL_MISC__EA_VC7_REMAP_MASK 0x00E00000L 2496 #define DAGB0_CNTL_MISC__BW_INIT_CYCLE_MASK 0x3F000000L 2497 #define DAGB0_CNTL_MISC__BW_RW_GAP_CYCLE_MASK 0xC0000000L 2498 //DAGB0_CNTL_MISC2 2499 #define DAGB0_CNTL_MISC2__URG_BOOST_ENABLE__SHIFT 0x0 2500 #define DAGB0_CNTL_MISC2__URG_HALT_ENABLE__SHIFT 0x1 2501 #define DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG__SHIFT 0x2 2502 #define DAGB0_CNTL_MISC2__DISABLE_WRRET_CG__SHIFT 0x3 2503 #define DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG__SHIFT 0x4 2504 #define DAGB0_CNTL_MISC2__DISABLE_RDRET_CG__SHIFT 0x5 2505 #define DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG__SHIFT 0x6 2506 #define DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG__SHIFT 0x7 2507 #define DAGB0_CNTL_MISC2__DISABLE_EAWRREQ_BUSY__SHIFT 0x8 2508 #define DAGB0_CNTL_MISC2__DISABLE_EARDREQ_BUSY__SHIFT 0x9 2509 #define DAGB0_CNTL_MISC2__SWAP_CTL__SHIFT 0xa 2510 #define DAGB0_CNTL_MISC2__ENABLE_PARITY_CHECK__SHIFT 0xb 2511 #define DAGB0_CNTL_MISC2__RDRET_FIFO_PERF__SHIFT 0xc 2512 #define DAGB0_CNTL_MISC2__RDRET_FIFO_CREDITS__SHIFT 0xd 2513 #define DAGB0_CNTL_MISC2__RDRET_FIFO_DLOCK_CREDITS__SHIFT 0x13 2514 #define DAGB0_CNTL_MISC2__URG_BOOST_ENABLE_MASK 0x00000001L 2515 #define DAGB0_CNTL_MISC2__URG_HALT_ENABLE_MASK 0x00000002L 2516 #define DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG_MASK 0x00000004L 2517 #define DAGB0_CNTL_MISC2__DISABLE_WRRET_CG_MASK 0x00000008L 2518 #define DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG_MASK 0x00000010L 2519 #define DAGB0_CNTL_MISC2__DISABLE_RDRET_CG_MASK 0x00000020L 2520 #define DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG_MASK 0x00000040L 2521 #define DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK 0x00000080L 2522 #define DAGB0_CNTL_MISC2__DISABLE_EAWRREQ_BUSY_MASK 0x00000100L 2523 #define DAGB0_CNTL_MISC2__DISABLE_EARDREQ_BUSY_MASK 0x00000200L 2524 #define DAGB0_CNTL_MISC2__SWAP_CTL_MASK 0x00000400L 2525 #define DAGB0_CNTL_MISC2__ENABLE_PARITY_CHECK_MASK 0x00000800L 2526 #define DAGB0_CNTL_MISC2__RDRET_FIFO_PERF_MASK 0x00001000L 2527 #define DAGB0_CNTL_MISC2__RDRET_FIFO_CREDITS_MASK 0x0007E000L 2528 #define DAGB0_CNTL_MISC2__RDRET_FIFO_DLOCK_CREDITS_MASK 0x01F80000L 2529 //DAGB0_FIFO_EMPTY 2530 #define DAGB0_FIFO_EMPTY__EMPTY__SHIFT 0x0 2531 #define DAGB0_FIFO_EMPTY__EMPTY_MASK 0x00FFFFFFL 2532 //DAGB0_FIFO_FULL 2533 #define DAGB0_FIFO_FULL__FULL__SHIFT 0x0 2534 #define DAGB0_FIFO_FULL__FULL_MASK 0x007FFFFFL 2535 //DAGB0_WR_CREDITS_FULL 2536 #define DAGB0_WR_CREDITS_FULL__FULL__SHIFT 0x0 2537 #define DAGB0_WR_CREDITS_FULL__FULL_MASK 0x1FFFFFFFL 2538 //DAGB0_RD_CREDITS_FULL 2539 #define DAGB0_RD_CREDITS_FULL__FULL__SHIFT 0x0 2540 #define DAGB0_RD_CREDITS_FULL__FULL_MASK 0x0003FFFFL 2541 //DAGB0_PERFCOUNTER_LO 2542 #define DAGB0_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 2543 #define DAGB0_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL 2544 //DAGB0_PERFCOUNTER_HI 2545 #define DAGB0_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 2546 #define DAGB0_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 2547 #define DAGB0_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL 2548 #define DAGB0_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L 2549 //DAGB0_PERFCOUNTER0_CFG 2550 #define DAGB0_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 2551 #define DAGB0_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 2552 #define DAGB0_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 2553 #define DAGB0_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c 2554 #define DAGB0_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d 2555 #define DAGB0_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL 2556 #define DAGB0_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L 2557 #define DAGB0_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L 2558 #define DAGB0_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L 2559 #define DAGB0_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L 2560 //DAGB0_PERFCOUNTER1_CFG 2561 #define DAGB0_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 2562 #define DAGB0_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 2563 #define DAGB0_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 2564 #define DAGB0_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c 2565 #define DAGB0_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d 2566 #define DAGB0_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL 2567 #define DAGB0_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L 2568 #define DAGB0_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L 2569 #define DAGB0_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L 2570 #define DAGB0_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L 2571 //DAGB0_PERFCOUNTER2_CFG 2572 #define DAGB0_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0 2573 #define DAGB0_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8 2574 #define DAGB0_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18 2575 #define DAGB0_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c 2576 #define DAGB0_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d 2577 #define DAGB0_PERFCOUNTER2_CFG__PERF_SEL_MASK 0x000000FFL 2578 #define DAGB0_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0x0000FF00L 2579 #define DAGB0_PERFCOUNTER2_CFG__PERF_MODE_MASK 0x0F000000L 2580 #define DAGB0_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000L 2581 #define DAGB0_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000L 2582 //DAGB0_PERFCOUNTER_RSLT_CNTL 2583 #define DAGB0_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 2584 #define DAGB0_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 2585 #define DAGB0_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 2586 #define DAGB0_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 2587 #define DAGB0_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 2588 #define DAGB0_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a 2589 #define DAGB0_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL 2590 #define DAGB0_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L 2591 #define DAGB0_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L 2592 #define DAGB0_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L 2593 #define DAGB0_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L 2594 #define DAGB0_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L 2595 //DAGB0_RESERVE0 2596 #define DAGB0_RESERVE0__RESERVE__SHIFT 0x0 2597 #define DAGB0_RESERVE0__RESERVE_MASK 0xFFFFFFFFL 2598 //DAGB0_RESERVE1 2599 #define DAGB0_RESERVE1__RESERVE__SHIFT 0x0 2600 #define DAGB0_RESERVE1__RESERVE_MASK 0xFFFFFFFFL 2601 //DAGB0_RESERVE2 2602 #define DAGB0_RESERVE2__RESERVE__SHIFT 0x0 2603 #define DAGB0_RESERVE2__RESERVE_MASK 0xFFFFFFFFL 2604 //DAGB0_RESERVE3 2605 #define DAGB0_RESERVE3__RESERVE__SHIFT 0x0 2606 #define DAGB0_RESERVE3__RESERVE_MASK 0xFFFFFFFFL 2607 //DAGB0_RESERVE4 2608 #define DAGB0_RESERVE4__RESERVE__SHIFT 0x0 2609 #define DAGB0_RESERVE4__RESERVE_MASK 0xFFFFFFFFL 2610 //DAGB0_RESERVE5 2611 #define DAGB0_RESERVE5__RESERVE__SHIFT 0x0 2612 #define DAGB0_RESERVE5__RESERVE_MASK 0xFFFFFFFFL 2613 //DAGB0_RESERVE6 2614 #define DAGB0_RESERVE6__RESERVE__SHIFT 0x0 2615 #define DAGB0_RESERVE6__RESERVE_MASK 0xFFFFFFFFL 2616 //DAGB0_RESERVE7 2617 #define DAGB0_RESERVE7__RESERVE__SHIFT 0x0 2618 #define DAGB0_RESERVE7__RESERVE_MASK 0xFFFFFFFFL 2619 //DAGB0_RESERVE8 2620 #define DAGB0_RESERVE8__RESERVE__SHIFT 0x0 2621 #define DAGB0_RESERVE8__RESERVE_MASK 0xFFFFFFFFL 2622 //DAGB0_RESERVE9 2623 #define DAGB0_RESERVE9__RESERVE__SHIFT 0x0 2624 #define DAGB0_RESERVE9__RESERVE_MASK 0xFFFFFFFFL 2625 2626 2627 // addressBlock: mmhub_mmea_mmeadec0 2628 //MMEA0_DRAM_RD_CLI2GRP_MAP0 2629 #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 2630 #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 2631 #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 2632 #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 2633 #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 2634 #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa 2635 #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc 2636 #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe 2637 #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 2638 #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 2639 #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 2640 #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 2641 #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 2642 #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a 2643 #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c 2644 #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e 2645 #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L 2646 #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL 2647 #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L 2648 #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L 2649 #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L 2650 #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L 2651 #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L 2652 #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L 2653 #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L 2654 #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L 2655 #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L 2656 #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L 2657 #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L 2658 #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L 2659 #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L 2660 #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L 2661 //MMEA0_DRAM_RD_CLI2GRP_MAP1 2662 #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 2663 #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 2664 #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 2665 #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 2666 #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 2667 #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa 2668 #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc 2669 #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe 2670 #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 2671 #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 2672 #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 2673 #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 2674 #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 2675 #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a 2676 #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c 2677 #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e 2678 #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L 2679 #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL 2680 #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L 2681 #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L 2682 #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L 2683 #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L 2684 #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L 2685 #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L 2686 #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L 2687 #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L 2688 #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L 2689 #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L 2690 #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L 2691 #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L 2692 #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L 2693 #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L 2694 //MMEA0_DRAM_WR_CLI2GRP_MAP0 2695 #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 2696 #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 2697 #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 2698 #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 2699 #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 2700 #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa 2701 #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc 2702 #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe 2703 #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 2704 #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 2705 #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 2706 #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 2707 #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 2708 #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a 2709 #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c 2710 #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e 2711 #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L 2712 #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL 2713 #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L 2714 #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L 2715 #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L 2716 #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L 2717 #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L 2718 #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L 2719 #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L 2720 #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L 2721 #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L 2722 #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L 2723 #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L 2724 #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L 2725 #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L 2726 #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L 2727 //MMEA0_DRAM_WR_CLI2GRP_MAP1 2728 #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 2729 #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 2730 #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 2731 #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 2732 #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 2733 #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa 2734 #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc 2735 #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe 2736 #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 2737 #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 2738 #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 2739 #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 2740 #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 2741 #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a 2742 #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c 2743 #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e 2744 #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L 2745 #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL 2746 #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L 2747 #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L 2748 #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L 2749 #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L 2750 #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L 2751 #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L 2752 #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L 2753 #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L 2754 #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L 2755 #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L 2756 #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L 2757 #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L 2758 #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L 2759 #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L 2760 //MMEA0_DRAM_RD_GRP2VC_MAP 2761 #define MMEA0_DRAM_RD_GRP2VC_MAP__GROUP0_VC__SHIFT 0x0 2762 #define MMEA0_DRAM_RD_GRP2VC_MAP__GROUP1_VC__SHIFT 0x3 2763 #define MMEA0_DRAM_RD_GRP2VC_MAP__GROUP2_VC__SHIFT 0x6 2764 #define MMEA0_DRAM_RD_GRP2VC_MAP__GROUP3_VC__SHIFT 0x9 2765 #define MMEA0_DRAM_RD_GRP2VC_MAP__GROUP0_VC_MASK 0x00000007L 2766 #define MMEA0_DRAM_RD_GRP2VC_MAP__GROUP1_VC_MASK 0x00000038L 2767 #define MMEA0_DRAM_RD_GRP2VC_MAP__GROUP2_VC_MASK 0x000001C0L 2768 #define MMEA0_DRAM_RD_GRP2VC_MAP__GROUP3_VC_MASK 0x00000E00L 2769 //MMEA0_DRAM_WR_GRP2VC_MAP 2770 #define MMEA0_DRAM_WR_GRP2VC_MAP__GROUP0_VC__SHIFT 0x0 2771 #define MMEA0_DRAM_WR_GRP2VC_MAP__GROUP1_VC__SHIFT 0x3 2772 #define MMEA0_DRAM_WR_GRP2VC_MAP__GROUP2_VC__SHIFT 0x6 2773 #define MMEA0_DRAM_WR_GRP2VC_MAP__GROUP3_VC__SHIFT 0x9 2774 #define MMEA0_DRAM_WR_GRP2VC_MAP__GROUP0_VC_MASK 0x00000007L 2775 #define MMEA0_DRAM_WR_GRP2VC_MAP__GROUP1_VC_MASK 0x00000038L 2776 #define MMEA0_DRAM_WR_GRP2VC_MAP__GROUP2_VC_MASK 0x000001C0L 2777 #define MMEA0_DRAM_WR_GRP2VC_MAP__GROUP3_VC_MASK 0x00000E00L 2778 //MMEA0_DRAM_RD_LAZY 2779 #define MMEA0_DRAM_RD_LAZY__GROUP0_DELAY__SHIFT 0x0 2780 #define MMEA0_DRAM_RD_LAZY__GROUP1_DELAY__SHIFT 0x3 2781 #define MMEA0_DRAM_RD_LAZY__GROUP2_DELAY__SHIFT 0x6 2782 #define MMEA0_DRAM_RD_LAZY__GROUP3_DELAY__SHIFT 0x9 2783 #define MMEA0_DRAM_RD_LAZY__REQ_ACCUM_THRESH__SHIFT 0xc 2784 #define MMEA0_DRAM_RD_LAZY__REQ_ACCUM_TIMEOUT__SHIFT 0x14 2785 #define MMEA0_DRAM_RD_LAZY__REQ_ACCUM_IDLEMAX__SHIFT 0x1b 2786 #define MMEA0_DRAM_RD_LAZY__GROUP0_DELAY_MASK 0x00000007L 2787 #define MMEA0_DRAM_RD_LAZY__GROUP1_DELAY_MASK 0x00000038L 2788 #define MMEA0_DRAM_RD_LAZY__GROUP2_DELAY_MASK 0x000001C0L 2789 #define MMEA0_DRAM_RD_LAZY__GROUP3_DELAY_MASK 0x00000E00L 2790 #define MMEA0_DRAM_RD_LAZY__REQ_ACCUM_THRESH_MASK 0x0003F000L 2791 #define MMEA0_DRAM_RD_LAZY__REQ_ACCUM_TIMEOUT_MASK 0x07F00000L 2792 #define MMEA0_DRAM_RD_LAZY__REQ_ACCUM_IDLEMAX_MASK 0x78000000L 2793 //MMEA0_DRAM_WR_LAZY 2794 #define MMEA0_DRAM_WR_LAZY__GROUP0_DELAY__SHIFT 0x0 2795 #define MMEA0_DRAM_WR_LAZY__GROUP1_DELAY__SHIFT 0x3 2796 #define MMEA0_DRAM_WR_LAZY__GROUP2_DELAY__SHIFT 0x6 2797 #define MMEA0_DRAM_WR_LAZY__GROUP3_DELAY__SHIFT 0x9 2798 #define MMEA0_DRAM_WR_LAZY__REQ_ACCUM_THRESH__SHIFT 0xc 2799 #define MMEA0_DRAM_WR_LAZY__REQ_ACCUM_TIMEOUT__SHIFT 0x14 2800 #define MMEA0_DRAM_WR_LAZY__REQ_ACCUM_IDLEMAX__SHIFT 0x1b 2801 #define MMEA0_DRAM_WR_LAZY__GROUP0_DELAY_MASK 0x00000007L 2802 #define MMEA0_DRAM_WR_LAZY__GROUP1_DELAY_MASK 0x00000038L 2803 #define MMEA0_DRAM_WR_LAZY__GROUP2_DELAY_MASK 0x000001C0L 2804 #define MMEA0_DRAM_WR_LAZY__GROUP3_DELAY_MASK 0x00000E00L 2805 #define MMEA0_DRAM_WR_LAZY__REQ_ACCUM_THRESH_MASK 0x0003F000L 2806 #define MMEA0_DRAM_WR_LAZY__REQ_ACCUM_TIMEOUT_MASK 0x07F00000L 2807 #define MMEA0_DRAM_WR_LAZY__REQ_ACCUM_IDLEMAX_MASK 0x78000000L 2808 //MMEA0_DRAM_RD_CAM_CNTL 2809 #define MMEA0_DRAM_RD_CAM_CNTL__DEPTH_GROUP0__SHIFT 0x0 2810 #define MMEA0_DRAM_RD_CAM_CNTL__DEPTH_GROUP1__SHIFT 0x4 2811 #define MMEA0_DRAM_RD_CAM_CNTL__DEPTH_GROUP2__SHIFT 0x8 2812 #define MMEA0_DRAM_RD_CAM_CNTL__DEPTH_GROUP3__SHIFT 0xc 2813 #define MMEA0_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT 0x10 2814 #define MMEA0_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT 0x13 2815 #define MMEA0_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT 0x16 2816 #define MMEA0_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT 0x19 2817 #define MMEA0_DRAM_RD_CAM_CNTL__REFILL_CHAIN__SHIFT 0x1c 2818 #define MMEA0_DRAM_RD_CAM_CNTL__DEPTH_GROUP0_MASK 0x0000000FL 2819 #define MMEA0_DRAM_RD_CAM_CNTL__DEPTH_GROUP1_MASK 0x000000F0L 2820 #define MMEA0_DRAM_RD_CAM_CNTL__DEPTH_GROUP2_MASK 0x00000F00L 2821 #define MMEA0_DRAM_RD_CAM_CNTL__DEPTH_GROUP3_MASK 0x0000F000L 2822 #define MMEA0_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK 0x00070000L 2823 #define MMEA0_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK 0x00380000L 2824 #define MMEA0_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK 0x01C00000L 2825 #define MMEA0_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK 0x0E000000L 2826 #define MMEA0_DRAM_RD_CAM_CNTL__REFILL_CHAIN_MASK 0x10000000L 2827 //MMEA0_DRAM_WR_CAM_CNTL 2828 #define MMEA0_DRAM_WR_CAM_CNTL__DEPTH_GROUP0__SHIFT 0x0 2829 #define MMEA0_DRAM_WR_CAM_CNTL__DEPTH_GROUP1__SHIFT 0x4 2830 #define MMEA0_DRAM_WR_CAM_CNTL__DEPTH_GROUP2__SHIFT 0x8 2831 #define MMEA0_DRAM_WR_CAM_CNTL__DEPTH_GROUP3__SHIFT 0xc 2832 #define MMEA0_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT 0x10 2833 #define MMEA0_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT 0x13 2834 #define MMEA0_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT 0x16 2835 #define MMEA0_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT 0x19 2836 #define MMEA0_DRAM_WR_CAM_CNTL__REFILL_CHAIN__SHIFT 0x1c 2837 #define MMEA0_DRAM_WR_CAM_CNTL__DEPTH_GROUP0_MASK 0x0000000FL 2838 #define MMEA0_DRAM_WR_CAM_CNTL__DEPTH_GROUP1_MASK 0x000000F0L 2839 #define MMEA0_DRAM_WR_CAM_CNTL__DEPTH_GROUP2_MASK 0x00000F00L 2840 #define MMEA0_DRAM_WR_CAM_CNTL__DEPTH_GROUP3_MASK 0x0000F000L 2841 #define MMEA0_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK 0x00070000L 2842 #define MMEA0_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK 0x00380000L 2843 #define MMEA0_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK 0x01C00000L 2844 #define MMEA0_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK 0x0E000000L 2845 #define MMEA0_DRAM_WR_CAM_CNTL__REFILL_CHAIN_MASK 0x10000000L 2846 //MMEA0_DRAM_PAGE_BURST 2847 #define MMEA0_DRAM_PAGE_BURST__RD_LIMIT_LO__SHIFT 0x0 2848 #define MMEA0_DRAM_PAGE_BURST__RD_LIMIT_HI__SHIFT 0x8 2849 #define MMEA0_DRAM_PAGE_BURST__WR_LIMIT_LO__SHIFT 0x10 2850 #define MMEA0_DRAM_PAGE_BURST__WR_LIMIT_HI__SHIFT 0x18 2851 #define MMEA0_DRAM_PAGE_BURST__RD_LIMIT_LO_MASK 0x000000FFL 2852 #define MMEA0_DRAM_PAGE_BURST__RD_LIMIT_HI_MASK 0x0000FF00L 2853 #define MMEA0_DRAM_PAGE_BURST__WR_LIMIT_LO_MASK 0x00FF0000L 2854 #define MMEA0_DRAM_PAGE_BURST__WR_LIMIT_HI_MASK 0xFF000000L 2855 //MMEA0_DRAM_RD_PRI_AGE 2856 #define MMEA0_DRAM_RD_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 2857 #define MMEA0_DRAM_RD_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 2858 #define MMEA0_DRAM_RD_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 2859 #define MMEA0_DRAM_RD_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 2860 #define MMEA0_DRAM_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc 2861 #define MMEA0_DRAM_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf 2862 #define MMEA0_DRAM_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 2863 #define MMEA0_DRAM_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 2864 #define MMEA0_DRAM_RD_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L 2865 #define MMEA0_DRAM_RD_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L 2866 #define MMEA0_DRAM_RD_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L 2867 #define MMEA0_DRAM_RD_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L 2868 #define MMEA0_DRAM_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L 2869 #define MMEA0_DRAM_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L 2870 #define MMEA0_DRAM_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L 2871 #define MMEA0_DRAM_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L 2872 //MMEA0_DRAM_WR_PRI_AGE 2873 #define MMEA0_DRAM_WR_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 2874 #define MMEA0_DRAM_WR_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 2875 #define MMEA0_DRAM_WR_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 2876 #define MMEA0_DRAM_WR_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 2877 #define MMEA0_DRAM_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc 2878 #define MMEA0_DRAM_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf 2879 #define MMEA0_DRAM_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 2880 #define MMEA0_DRAM_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 2881 #define MMEA0_DRAM_WR_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L 2882 #define MMEA0_DRAM_WR_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L 2883 #define MMEA0_DRAM_WR_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L 2884 #define MMEA0_DRAM_WR_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L 2885 #define MMEA0_DRAM_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L 2886 #define MMEA0_DRAM_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L 2887 #define MMEA0_DRAM_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L 2888 #define MMEA0_DRAM_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L 2889 //MMEA0_DRAM_RD_PRI_QUEUING 2890 #define MMEA0_DRAM_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 2891 #define MMEA0_DRAM_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 2892 #define MMEA0_DRAM_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 2893 #define MMEA0_DRAM_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 2894 #define MMEA0_DRAM_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L 2895 #define MMEA0_DRAM_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L 2896 #define MMEA0_DRAM_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L 2897 #define MMEA0_DRAM_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L 2898 //MMEA0_DRAM_WR_PRI_QUEUING 2899 #define MMEA0_DRAM_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 2900 #define MMEA0_DRAM_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 2901 #define MMEA0_DRAM_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 2902 #define MMEA0_DRAM_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 2903 #define MMEA0_DRAM_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L 2904 #define MMEA0_DRAM_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L 2905 #define MMEA0_DRAM_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L 2906 #define MMEA0_DRAM_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L 2907 //MMEA0_DRAM_RD_PRI_FIXED 2908 #define MMEA0_DRAM_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 2909 #define MMEA0_DRAM_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 2910 #define MMEA0_DRAM_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 2911 #define MMEA0_DRAM_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 2912 #define MMEA0_DRAM_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L 2913 #define MMEA0_DRAM_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L 2914 #define MMEA0_DRAM_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L 2915 #define MMEA0_DRAM_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L 2916 //MMEA0_DRAM_WR_PRI_FIXED 2917 #define MMEA0_DRAM_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 2918 #define MMEA0_DRAM_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 2919 #define MMEA0_DRAM_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 2920 #define MMEA0_DRAM_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 2921 #define MMEA0_DRAM_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L 2922 #define MMEA0_DRAM_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L 2923 #define MMEA0_DRAM_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L 2924 #define MMEA0_DRAM_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L 2925 //MMEA0_DRAM_RD_PRI_URGENCY 2926 #define MMEA0_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 2927 #define MMEA0_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 2928 #define MMEA0_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 2929 #define MMEA0_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 2930 #define MMEA0_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc 2931 #define MMEA0_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd 2932 #define MMEA0_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe 2933 #define MMEA0_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf 2934 #define MMEA0_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L 2935 #define MMEA0_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L 2936 #define MMEA0_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L 2937 #define MMEA0_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L 2938 #define MMEA0_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L 2939 #define MMEA0_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L 2940 #define MMEA0_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L 2941 #define MMEA0_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L 2942 //MMEA0_DRAM_WR_PRI_URGENCY 2943 #define MMEA0_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 2944 #define MMEA0_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 2945 #define MMEA0_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 2946 #define MMEA0_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 2947 #define MMEA0_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc 2948 #define MMEA0_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd 2949 #define MMEA0_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe 2950 #define MMEA0_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf 2951 #define MMEA0_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L 2952 #define MMEA0_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L 2953 #define MMEA0_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L 2954 #define MMEA0_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L 2955 #define MMEA0_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L 2956 #define MMEA0_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L 2957 #define MMEA0_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L 2958 #define MMEA0_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L 2959 //MMEA0_DRAM_RD_PRI_QUANT_PRI1 2960 #define MMEA0_DRAM_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 2961 #define MMEA0_DRAM_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 2962 #define MMEA0_DRAM_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 2963 #define MMEA0_DRAM_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 2964 #define MMEA0_DRAM_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL 2965 #define MMEA0_DRAM_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L 2966 #define MMEA0_DRAM_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L 2967 #define MMEA0_DRAM_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L 2968 //MMEA0_DRAM_RD_PRI_QUANT_PRI2 2969 #define MMEA0_DRAM_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 2970 #define MMEA0_DRAM_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 2971 #define MMEA0_DRAM_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 2972 #define MMEA0_DRAM_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 2973 #define MMEA0_DRAM_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL 2974 #define MMEA0_DRAM_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L 2975 #define MMEA0_DRAM_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L 2976 #define MMEA0_DRAM_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L 2977 //MMEA0_DRAM_RD_PRI_QUANT_PRI3 2978 #define MMEA0_DRAM_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 2979 #define MMEA0_DRAM_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 2980 #define MMEA0_DRAM_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 2981 #define MMEA0_DRAM_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 2982 #define MMEA0_DRAM_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL 2983 #define MMEA0_DRAM_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L 2984 #define MMEA0_DRAM_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L 2985 #define MMEA0_DRAM_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L 2986 //MMEA0_DRAM_WR_PRI_QUANT_PRI1 2987 #define MMEA0_DRAM_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 2988 #define MMEA0_DRAM_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 2989 #define MMEA0_DRAM_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 2990 #define MMEA0_DRAM_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 2991 #define MMEA0_DRAM_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL 2992 #define MMEA0_DRAM_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L 2993 #define MMEA0_DRAM_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L 2994 #define MMEA0_DRAM_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L 2995 //MMEA0_DRAM_WR_PRI_QUANT_PRI2 2996 #define MMEA0_DRAM_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 2997 #define MMEA0_DRAM_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 2998 #define MMEA0_DRAM_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 2999 #define MMEA0_DRAM_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 3000 #define MMEA0_DRAM_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL 3001 #define MMEA0_DRAM_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L 3002 #define MMEA0_DRAM_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L 3003 #define MMEA0_DRAM_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L 3004 //MMEA0_DRAM_WR_PRI_QUANT_PRI3 3005 #define MMEA0_DRAM_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 3006 #define MMEA0_DRAM_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 3007 #define MMEA0_DRAM_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 3008 #define MMEA0_DRAM_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 3009 #define MMEA0_DRAM_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL 3010 #define MMEA0_DRAM_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L 3011 #define MMEA0_DRAM_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L 3012 #define MMEA0_DRAM_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L 3013 //MMEA0_ADDRNORM_BASE_ADDR0 3014 #define MMEA0_ADDRNORM_BASE_ADDR0__ADDR_RNG_VAL__SHIFT 0x0 3015 #define MMEA0_ADDRNORM_BASE_ADDR0__LGCY_MMIO_HOLE_EN__SHIFT 0x1 3016 #define MMEA0_ADDRNORM_BASE_ADDR0__INTLV_NUM_CHAN__SHIFT 0x2 3017 #define MMEA0_ADDRNORM_BASE_ADDR0__INTLV_NUM_DIES__SHIFT 0x6 3018 #define MMEA0_ADDRNORM_BASE_ADDR0__INTLV_NUM_SOCKETS__SHIFT 0x8 3019 #define MMEA0_ADDRNORM_BASE_ADDR0__INTLV_ADDR_SEL__SHIFT 0x9 3020 #define MMEA0_ADDRNORM_BASE_ADDR0__BASE_ADDR__SHIFT 0xc 3021 #define MMEA0_ADDRNORM_BASE_ADDR0__ADDR_RNG_VAL_MASK 0x00000001L 3022 #define MMEA0_ADDRNORM_BASE_ADDR0__LGCY_MMIO_HOLE_EN_MASK 0x00000002L 3023 #define MMEA0_ADDRNORM_BASE_ADDR0__INTLV_NUM_CHAN_MASK 0x0000003CL 3024 #define MMEA0_ADDRNORM_BASE_ADDR0__INTLV_NUM_DIES_MASK 0x000000C0L 3025 #define MMEA0_ADDRNORM_BASE_ADDR0__INTLV_NUM_SOCKETS_MASK 0x00000100L 3026 #define MMEA0_ADDRNORM_BASE_ADDR0__INTLV_ADDR_SEL_MASK 0x00000E00L 3027 #define MMEA0_ADDRNORM_BASE_ADDR0__BASE_ADDR_MASK 0xFFFFF000L 3028 //MMEA0_ADDRNORM_LIMIT_ADDR0 3029 #define MMEA0_ADDRNORM_LIMIT_ADDR0__DST_FABRIC_ID__SHIFT 0x0 3030 #define MMEA0_ADDRNORM_LIMIT_ADDR0__LIMIT_ADDR__SHIFT 0xc 3031 #define MMEA0_ADDRNORM_LIMIT_ADDR0__DST_FABRIC_ID_MASK 0x0000001FL 3032 #define MMEA0_ADDRNORM_LIMIT_ADDR0__LIMIT_ADDR_MASK 0xFFFFF000L 3033 //MMEA0_ADDRNORM_BASE_ADDR1 3034 #define MMEA0_ADDRNORM_BASE_ADDR1__ADDR_RNG_VAL__SHIFT 0x0 3035 #define MMEA0_ADDRNORM_BASE_ADDR1__LGCY_MMIO_HOLE_EN__SHIFT 0x1 3036 #define MMEA0_ADDRNORM_BASE_ADDR1__INTLV_NUM_CHAN__SHIFT 0x2 3037 #define MMEA0_ADDRNORM_BASE_ADDR1__INTLV_NUM_DIES__SHIFT 0x6 3038 #define MMEA0_ADDRNORM_BASE_ADDR1__INTLV_NUM_SOCKETS__SHIFT 0x8 3039 #define MMEA0_ADDRNORM_BASE_ADDR1__INTLV_ADDR_SEL__SHIFT 0x9 3040 #define MMEA0_ADDRNORM_BASE_ADDR1__BASE_ADDR__SHIFT 0xc 3041 #define MMEA0_ADDRNORM_BASE_ADDR1__ADDR_RNG_VAL_MASK 0x00000001L 3042 #define MMEA0_ADDRNORM_BASE_ADDR1__LGCY_MMIO_HOLE_EN_MASK 0x00000002L 3043 #define MMEA0_ADDRNORM_BASE_ADDR1__INTLV_NUM_CHAN_MASK 0x0000003CL 3044 #define MMEA0_ADDRNORM_BASE_ADDR1__INTLV_NUM_DIES_MASK 0x000000C0L 3045 #define MMEA0_ADDRNORM_BASE_ADDR1__INTLV_NUM_SOCKETS_MASK 0x00000100L 3046 #define MMEA0_ADDRNORM_BASE_ADDR1__INTLV_ADDR_SEL_MASK 0x00000E00L 3047 #define MMEA0_ADDRNORM_BASE_ADDR1__BASE_ADDR_MASK 0xFFFFF000L 3048 //MMEA0_ADDRNORM_LIMIT_ADDR1 3049 #define MMEA0_ADDRNORM_LIMIT_ADDR1__DST_FABRIC_ID__SHIFT 0x0 3050 #define MMEA0_ADDRNORM_LIMIT_ADDR1__LIMIT_ADDR__SHIFT 0xc 3051 #define MMEA0_ADDRNORM_LIMIT_ADDR1__DST_FABRIC_ID_MASK 0x0000001FL 3052 #define MMEA0_ADDRNORM_LIMIT_ADDR1__LIMIT_ADDR_MASK 0xFFFFF000L 3053 //MMEA0_ADDRNORM_OFFSET_ADDR1 3054 #define MMEA0_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET_EN__SHIFT 0x0 3055 #define MMEA0_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET__SHIFT 0x14 3056 #define MMEA0_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET_EN_MASK 0x00000001L 3057 #define MMEA0_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET_MASK 0xFFF00000L 3058 //MMEA0_ADDRNORMDRAM_HOLE_CNTL 3059 #define MMEA0_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_VALID__SHIFT 0x0 3060 #define MMEA0_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_OFFSET__SHIFT 0x7 3061 #define MMEA0_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_VALID_MASK 0x00000001L 3062 #define MMEA0_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_OFFSET_MASK 0x0000FF80L 3063 //MMEA0_ADDRNORMDRAM_NP2_CHANNEL_CFG 3064 #define MMEA0_ADDRNORMDRAM_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE0__SHIFT 0x0 3065 #define MMEA0_ADDRNORMDRAM_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE1__SHIFT 0x6 3066 #define MMEA0_ADDRNORMDRAM_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE0_MASK 0x0000003FL 3067 #define MMEA0_ADDRNORMDRAM_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE1_MASK 0x00000FC0L 3068 //MMEA0_ADDRDEC_BANK_CFG 3069 #define MMEA0_ADDRDEC_BANK_CFG__BANK_MASK_DRAM__SHIFT 0x0 3070 #define MMEA0_ADDRDEC_BANK_CFG__BANK_MASK_GMI__SHIFT 0x6 3071 #define MMEA0_ADDRDEC_BANK_CFG__BANKGROUP_SEL_DRAM__SHIFT 0xc 3072 #define MMEA0_ADDRDEC_BANK_CFG__BANKGROUP_SEL_GMI__SHIFT 0xf 3073 #define MMEA0_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_DRAM__SHIFT 0x12 3074 #define MMEA0_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_GMI__SHIFT 0x13 3075 #define MMEA0_ADDRDEC_BANK_CFG__BANK_MASK_DRAM_MASK 0x0000003FL 3076 #define MMEA0_ADDRDEC_BANK_CFG__BANK_MASK_GMI_MASK 0x00000FC0L 3077 #define MMEA0_ADDRDEC_BANK_CFG__BANKGROUP_SEL_DRAM_MASK 0x00007000L 3078 #define MMEA0_ADDRDEC_BANK_CFG__BANKGROUP_SEL_GMI_MASK 0x00038000L 3079 #define MMEA0_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_DRAM_MASK 0x00040000L 3080 #define MMEA0_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_GMI_MASK 0x00080000L 3081 //MMEA0_ADDRDEC_MISC_CFG 3082 #define MMEA0_ADDRDEC_MISC_CFG__VCM_EN0__SHIFT 0x0 3083 #define MMEA0_ADDRDEC_MISC_CFG__VCM_EN1__SHIFT 0x1 3084 #define MMEA0_ADDRDEC_MISC_CFG__VCM_EN2__SHIFT 0x2 3085 #define MMEA0_ADDRDEC_MISC_CFG__PCH_MASK_DRAM__SHIFT 0x8 3086 #define MMEA0_ADDRDEC_MISC_CFG__PCH_MASK_GMI__SHIFT 0x9 3087 #define MMEA0_ADDRDEC_MISC_CFG__CH_MASK_DRAM__SHIFT 0xc 3088 #define MMEA0_ADDRDEC_MISC_CFG__CH_MASK_GMI__SHIFT 0x11 3089 #define MMEA0_ADDRDEC_MISC_CFG__CS_MASK_DRAM__SHIFT 0x16 3090 #define MMEA0_ADDRDEC_MISC_CFG__CS_MASK_GMI__SHIFT 0x18 3091 #define MMEA0_ADDRDEC_MISC_CFG__RM_MASK_DRAM__SHIFT 0x1a 3092 #define MMEA0_ADDRDEC_MISC_CFG__RM_MASK_GMI__SHIFT 0x1d 3093 #define MMEA0_ADDRDEC_MISC_CFG__VCM_EN0_MASK 0x00000001L 3094 #define MMEA0_ADDRDEC_MISC_CFG__VCM_EN1_MASK 0x00000002L 3095 #define MMEA0_ADDRDEC_MISC_CFG__VCM_EN2_MASK 0x00000004L 3096 #define MMEA0_ADDRDEC_MISC_CFG__PCH_MASK_DRAM_MASK 0x00000100L 3097 #define MMEA0_ADDRDEC_MISC_CFG__PCH_MASK_GMI_MASK 0x00000200L 3098 #define MMEA0_ADDRDEC_MISC_CFG__CH_MASK_DRAM_MASK 0x0001F000L 3099 #define MMEA0_ADDRDEC_MISC_CFG__CH_MASK_GMI_MASK 0x003E0000L 3100 #define MMEA0_ADDRDEC_MISC_CFG__CS_MASK_DRAM_MASK 0x00C00000L 3101 #define MMEA0_ADDRDEC_MISC_CFG__CS_MASK_GMI_MASK 0x03000000L 3102 #define MMEA0_ADDRDEC_MISC_CFG__RM_MASK_DRAM_MASK 0x1C000000L 3103 #define MMEA0_ADDRDEC_MISC_CFG__RM_MASK_GMI_MASK 0xE0000000L 3104 //MMEA0_ADDRDECDRAM_ADDR_HASH_BANK0 3105 #define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK0__XOR_ENABLE__SHIFT 0x0 3106 #define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK0__COL_XOR__SHIFT 0x1 3107 #define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK0__ROW_XOR__SHIFT 0xe 3108 #define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK0__XOR_ENABLE_MASK 0x00000001L 3109 #define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK0__COL_XOR_MASK 0x00003FFEL 3110 #define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK0__ROW_XOR_MASK 0xFFFFC000L 3111 //MMEA0_ADDRDECDRAM_ADDR_HASH_BANK1 3112 #define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK1__XOR_ENABLE__SHIFT 0x0 3113 #define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK1__COL_XOR__SHIFT 0x1 3114 #define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK1__ROW_XOR__SHIFT 0xe 3115 #define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK1__XOR_ENABLE_MASK 0x00000001L 3116 #define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK1__COL_XOR_MASK 0x00003FFEL 3117 #define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK1__ROW_XOR_MASK 0xFFFFC000L 3118 //MMEA0_ADDRDECDRAM_ADDR_HASH_BANK2 3119 #define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK2__XOR_ENABLE__SHIFT 0x0 3120 #define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK2__COL_XOR__SHIFT 0x1 3121 #define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK2__ROW_XOR__SHIFT 0xe 3122 #define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK2__XOR_ENABLE_MASK 0x00000001L 3123 #define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK2__COL_XOR_MASK 0x00003FFEL 3124 #define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK2__ROW_XOR_MASK 0xFFFFC000L 3125 //MMEA0_ADDRDECDRAM_ADDR_HASH_BANK3 3126 #define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK3__XOR_ENABLE__SHIFT 0x0 3127 #define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK3__COL_XOR__SHIFT 0x1 3128 #define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK3__ROW_XOR__SHIFT 0xe 3129 #define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK3__XOR_ENABLE_MASK 0x00000001L 3130 #define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK3__COL_XOR_MASK 0x00003FFEL 3131 #define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK3__ROW_XOR_MASK 0xFFFFC000L 3132 //MMEA0_ADDRDECDRAM_ADDR_HASH_BANK4 3133 #define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK4__XOR_ENABLE__SHIFT 0x0 3134 #define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK4__COL_XOR__SHIFT 0x1 3135 #define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK4__ROW_XOR__SHIFT 0xe 3136 #define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK4__XOR_ENABLE_MASK 0x00000001L 3137 #define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK4__COL_XOR_MASK 0x00003FFEL 3138 #define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK4__ROW_XOR_MASK 0xFFFFC000L 3139 //MMEA0_ADDRDECDRAM_ADDR_HASH_BANK5 3140 #define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK5__XOR_ENABLE__SHIFT 0x0 3141 #define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK5__COL_XOR__SHIFT 0x1 3142 #define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK5__ROW_XOR__SHIFT 0xe 3143 #define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK5__XOR_ENABLE_MASK 0x00000001L 3144 #define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK5__COL_XOR_MASK 0x00003FFEL 3145 #define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK5__ROW_XOR_MASK 0xFFFFC000L 3146 //MMEA0_ADDRDECDRAM_ADDR_HASH_PC 3147 #define MMEA0_ADDRDECDRAM_ADDR_HASH_PC__XOR_ENABLE__SHIFT 0x0 3148 #define MMEA0_ADDRDECDRAM_ADDR_HASH_PC__COL_XOR__SHIFT 0x1 3149 #define MMEA0_ADDRDECDRAM_ADDR_HASH_PC__ROW_XOR__SHIFT 0xe 3150 #define MMEA0_ADDRDECDRAM_ADDR_HASH_PC__XOR_ENABLE_MASK 0x00000001L 3151 #define MMEA0_ADDRDECDRAM_ADDR_HASH_PC__COL_XOR_MASK 0x00003FFEL 3152 #define MMEA0_ADDRDECDRAM_ADDR_HASH_PC__ROW_XOR_MASK 0xFFFFC000L 3153 //MMEA0_ADDRDECDRAM_ADDR_HASH_PC2 3154 #define MMEA0_ADDRDECDRAM_ADDR_HASH_PC2__BANK_XOR__SHIFT 0x0 3155 #define MMEA0_ADDRDECDRAM_ADDR_HASH_PC2__BANK_XOR_MASK 0x0000003FL 3156 //MMEA0_ADDRDECDRAM_ADDR_HASH_CS0 3157 #define MMEA0_ADDRDECDRAM_ADDR_HASH_CS0__XOR_ENABLE__SHIFT 0x0 3158 #define MMEA0_ADDRDECDRAM_ADDR_HASH_CS0__NA_XOR__SHIFT 0x1 3159 #define MMEA0_ADDRDECDRAM_ADDR_HASH_CS0__XOR_ENABLE_MASK 0x00000001L 3160 #define MMEA0_ADDRDECDRAM_ADDR_HASH_CS0__NA_XOR_MASK 0xFFFFFFFEL 3161 //MMEA0_ADDRDECDRAM_ADDR_HASH_CS1 3162 #define MMEA0_ADDRDECDRAM_ADDR_HASH_CS1__XOR_ENABLE__SHIFT 0x0 3163 #define MMEA0_ADDRDECDRAM_ADDR_HASH_CS1__NA_XOR__SHIFT 0x1 3164 #define MMEA0_ADDRDECDRAM_ADDR_HASH_CS1__XOR_ENABLE_MASK 0x00000001L 3165 #define MMEA0_ADDRDECDRAM_ADDR_HASH_CS1__NA_XOR_MASK 0xFFFFFFFEL 3166 //MMEA0_ADDRDECDRAM_HARVEST_ENABLE 3167 #define MMEA0_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_EN__SHIFT 0x0 3168 #define MMEA0_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_VAL__SHIFT 0x1 3169 #define MMEA0_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_EN__SHIFT 0x2 3170 #define MMEA0_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_VAL__SHIFT 0x3 3171 #define MMEA0_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B5_EN__SHIFT 0x4 3172 #define MMEA0_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B5_VAL__SHIFT 0x5 3173 #define MMEA0_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_EN_MASK 0x00000001L 3174 #define MMEA0_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_VAL_MASK 0x00000002L 3175 #define MMEA0_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_EN_MASK 0x00000004L 3176 #define MMEA0_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_VAL_MASK 0x00000008L 3177 #define MMEA0_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B5_EN_MASK 0x00000010L 3178 #define MMEA0_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B5_VAL_MASK 0x00000020L 3179 //MMEA0_ADDRDECDRAM_HARVNA_ADDR_START0 3180 #define MMEA0_ADDRDECDRAM_HARVNA_ADDR_START0__START__SHIFT 0x0 3181 #define MMEA0_ADDRDECDRAM_HARVNA_ADDR_START0__BANK_XOR__SHIFT 0x1c 3182 #define MMEA0_ADDRDECDRAM_HARVNA_ADDR_START0__START_MASK 0x000FFFFFL 3183 #define MMEA0_ADDRDECDRAM_HARVNA_ADDR_START0__BANK_XOR_MASK 0xF0000000L 3184 //MMEA0_ADDRDECDRAM_HARVNA_ADDR_END0 3185 #define MMEA0_ADDRDECDRAM_HARVNA_ADDR_END0__END__SHIFT 0x0 3186 #define MMEA0_ADDRDECDRAM_HARVNA_ADDR_END0__END_MASK 0x000FFFFFL 3187 //MMEA0_ADDRDECDRAM_HARVNA_ADDR_START1 3188 #define MMEA0_ADDRDECDRAM_HARVNA_ADDR_START1__START__SHIFT 0x0 3189 #define MMEA0_ADDRDECDRAM_HARVNA_ADDR_START1__BANK_XOR__SHIFT 0x1c 3190 #define MMEA0_ADDRDECDRAM_HARVNA_ADDR_START1__START_MASK 0x000FFFFFL 3191 #define MMEA0_ADDRDECDRAM_HARVNA_ADDR_START1__BANK_XOR_MASK 0xF0000000L 3192 //MMEA0_ADDRDECDRAM_HARVNA_ADDR_END1 3193 #define MMEA0_ADDRDECDRAM_HARVNA_ADDR_END1__END__SHIFT 0x0 3194 #define MMEA0_ADDRDECDRAM_HARVNA_ADDR_END1__END_MASK 0x000FFFFFL 3195 //MMEA0_ADDRDEC0_BASE_ADDR_CS0 3196 #define MMEA0_ADDRDEC0_BASE_ADDR_CS0__CS_EN__SHIFT 0x0 3197 #define MMEA0_ADDRDEC0_BASE_ADDR_CS0__BASE_ADDR__SHIFT 0x1 3198 #define MMEA0_ADDRDEC0_BASE_ADDR_CS0__CS_EN_MASK 0x00000001L 3199 #define MMEA0_ADDRDEC0_BASE_ADDR_CS0__BASE_ADDR_MASK 0xFFFFFFFEL 3200 //MMEA0_ADDRDEC0_BASE_ADDR_CS1 3201 #define MMEA0_ADDRDEC0_BASE_ADDR_CS1__CS_EN__SHIFT 0x0 3202 #define MMEA0_ADDRDEC0_BASE_ADDR_CS1__BASE_ADDR__SHIFT 0x1 3203 #define MMEA0_ADDRDEC0_BASE_ADDR_CS1__CS_EN_MASK 0x00000001L 3204 #define MMEA0_ADDRDEC0_BASE_ADDR_CS1__BASE_ADDR_MASK 0xFFFFFFFEL 3205 //MMEA0_ADDRDEC0_BASE_ADDR_CS2 3206 #define MMEA0_ADDRDEC0_BASE_ADDR_CS2__CS_EN__SHIFT 0x0 3207 #define MMEA0_ADDRDEC0_BASE_ADDR_CS2__BASE_ADDR__SHIFT 0x1 3208 #define MMEA0_ADDRDEC0_BASE_ADDR_CS2__CS_EN_MASK 0x00000001L 3209 #define MMEA0_ADDRDEC0_BASE_ADDR_CS2__BASE_ADDR_MASK 0xFFFFFFFEL 3210 //MMEA0_ADDRDEC0_BASE_ADDR_CS3 3211 #define MMEA0_ADDRDEC0_BASE_ADDR_CS3__CS_EN__SHIFT 0x0 3212 #define MMEA0_ADDRDEC0_BASE_ADDR_CS3__BASE_ADDR__SHIFT 0x1 3213 #define MMEA0_ADDRDEC0_BASE_ADDR_CS3__CS_EN_MASK 0x00000001L 3214 #define MMEA0_ADDRDEC0_BASE_ADDR_CS3__BASE_ADDR_MASK 0xFFFFFFFEL 3215 //MMEA0_ADDRDEC0_BASE_ADDR_SECCS0 3216 #define MMEA0_ADDRDEC0_BASE_ADDR_SECCS0__CS_EN__SHIFT 0x0 3217 #define MMEA0_ADDRDEC0_BASE_ADDR_SECCS0__BASE_ADDR__SHIFT 0x1 3218 #define MMEA0_ADDRDEC0_BASE_ADDR_SECCS0__CS_EN_MASK 0x00000001L 3219 #define MMEA0_ADDRDEC0_BASE_ADDR_SECCS0__BASE_ADDR_MASK 0xFFFFFFFEL 3220 //MMEA0_ADDRDEC0_BASE_ADDR_SECCS1 3221 #define MMEA0_ADDRDEC0_BASE_ADDR_SECCS1__CS_EN__SHIFT 0x0 3222 #define MMEA0_ADDRDEC0_BASE_ADDR_SECCS1__BASE_ADDR__SHIFT 0x1 3223 #define MMEA0_ADDRDEC0_BASE_ADDR_SECCS1__CS_EN_MASK 0x00000001L 3224 #define MMEA0_ADDRDEC0_BASE_ADDR_SECCS1__BASE_ADDR_MASK 0xFFFFFFFEL 3225 //MMEA0_ADDRDEC0_BASE_ADDR_SECCS2 3226 #define MMEA0_ADDRDEC0_BASE_ADDR_SECCS2__CS_EN__SHIFT 0x0 3227 #define MMEA0_ADDRDEC0_BASE_ADDR_SECCS2__BASE_ADDR__SHIFT 0x1 3228 #define MMEA0_ADDRDEC0_BASE_ADDR_SECCS2__CS_EN_MASK 0x00000001L 3229 #define MMEA0_ADDRDEC0_BASE_ADDR_SECCS2__BASE_ADDR_MASK 0xFFFFFFFEL 3230 //MMEA0_ADDRDEC0_BASE_ADDR_SECCS3 3231 #define MMEA0_ADDRDEC0_BASE_ADDR_SECCS3__CS_EN__SHIFT 0x0 3232 #define MMEA0_ADDRDEC0_BASE_ADDR_SECCS3__BASE_ADDR__SHIFT 0x1 3233 #define MMEA0_ADDRDEC0_BASE_ADDR_SECCS3__CS_EN_MASK 0x00000001L 3234 #define MMEA0_ADDRDEC0_BASE_ADDR_SECCS3__BASE_ADDR_MASK 0xFFFFFFFEL 3235 //MMEA0_ADDRDEC0_ADDR_MASK_CS01 3236 #define MMEA0_ADDRDEC0_ADDR_MASK_CS01__ADDR_MASK__SHIFT 0x1 3237 #define MMEA0_ADDRDEC0_ADDR_MASK_CS01__ADDR_MASK_MASK 0xFFFFFFFEL 3238 //MMEA0_ADDRDEC0_ADDR_MASK_CS23 3239 #define MMEA0_ADDRDEC0_ADDR_MASK_CS23__ADDR_MASK__SHIFT 0x1 3240 #define MMEA0_ADDRDEC0_ADDR_MASK_CS23__ADDR_MASK_MASK 0xFFFFFFFEL 3241 //MMEA0_ADDRDEC0_ADDR_MASK_SECCS01 3242 #define MMEA0_ADDRDEC0_ADDR_MASK_SECCS01__ADDR_MASK__SHIFT 0x1 3243 #define MMEA0_ADDRDEC0_ADDR_MASK_SECCS01__ADDR_MASK_MASK 0xFFFFFFFEL 3244 //MMEA0_ADDRDEC0_ADDR_MASK_SECCS23 3245 #define MMEA0_ADDRDEC0_ADDR_MASK_SECCS23__ADDR_MASK__SHIFT 0x1 3246 #define MMEA0_ADDRDEC0_ADDR_MASK_SECCS23__ADDR_MASK_MASK 0xFFFFFFFEL 3247 //MMEA0_ADDRDEC0_ADDR_CFG_CS01 3248 #define MMEA0_ADDRDEC0_ADDR_CFG_CS01__NUM_BANK_GROUPS__SHIFT 0x1 3249 #define MMEA0_ADDRDEC0_ADDR_CFG_CS01__NUM_RM__SHIFT 0x4 3250 #define MMEA0_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_LO__SHIFT 0x8 3251 #define MMEA0_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_HI__SHIFT 0xc 3252 #define MMEA0_ADDRDEC0_ADDR_CFG_CS01__NUM_COL__SHIFT 0x10 3253 #define MMEA0_ADDRDEC0_ADDR_CFG_CS01__NUM_BANKS__SHIFT 0x14 3254 #define MMEA0_ADDRDEC0_ADDR_CFG_CS01__HI_COL_EN__SHIFT 0x1f 3255 #define MMEA0_ADDRDEC0_ADDR_CFG_CS01__NUM_BANK_GROUPS_MASK 0x0000000EL 3256 #define MMEA0_ADDRDEC0_ADDR_CFG_CS01__NUM_RM_MASK 0x00000030L 3257 #define MMEA0_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_LO_MASK 0x00000F00L 3258 #define MMEA0_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_HI_MASK 0x0000F000L 3259 #define MMEA0_ADDRDEC0_ADDR_CFG_CS01__NUM_COL_MASK 0x000F0000L 3260 #define MMEA0_ADDRDEC0_ADDR_CFG_CS01__NUM_BANKS_MASK 0x00300000L 3261 #define MMEA0_ADDRDEC0_ADDR_CFG_CS01__HI_COL_EN_MASK 0x80000000L 3262 //MMEA0_ADDRDEC0_ADDR_CFG_CS23 3263 #define MMEA0_ADDRDEC0_ADDR_CFG_CS23__NUM_BANK_GROUPS__SHIFT 0x1 3264 #define MMEA0_ADDRDEC0_ADDR_CFG_CS23__NUM_RM__SHIFT 0x4 3265 #define MMEA0_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_LO__SHIFT 0x8 3266 #define MMEA0_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_HI__SHIFT 0xc 3267 #define MMEA0_ADDRDEC0_ADDR_CFG_CS23__NUM_COL__SHIFT 0x10 3268 #define MMEA0_ADDRDEC0_ADDR_CFG_CS23__NUM_BANKS__SHIFT 0x14 3269 #define MMEA0_ADDRDEC0_ADDR_CFG_CS23__HI_COL_EN__SHIFT 0x1f 3270 #define MMEA0_ADDRDEC0_ADDR_CFG_CS23__NUM_BANK_GROUPS_MASK 0x0000000EL 3271 #define MMEA0_ADDRDEC0_ADDR_CFG_CS23__NUM_RM_MASK 0x00000030L 3272 #define MMEA0_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_LO_MASK 0x00000F00L 3273 #define MMEA0_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_HI_MASK 0x0000F000L 3274 #define MMEA0_ADDRDEC0_ADDR_CFG_CS23__NUM_COL_MASK 0x000F0000L 3275 #define MMEA0_ADDRDEC0_ADDR_CFG_CS23__NUM_BANKS_MASK 0x00300000L 3276 #define MMEA0_ADDRDEC0_ADDR_CFG_CS23__HI_COL_EN_MASK 0x80000000L 3277 //MMEA0_ADDRDEC0_ADDR_SEL_CS01 3278 #define MMEA0_ADDRDEC0_ADDR_SEL_CS01__BANK0__SHIFT 0x0 3279 #define MMEA0_ADDRDEC0_ADDR_SEL_CS01__BANK1__SHIFT 0x4 3280 #define MMEA0_ADDRDEC0_ADDR_SEL_CS01__BANK2__SHIFT 0x8 3281 #define MMEA0_ADDRDEC0_ADDR_SEL_CS01__BANK3__SHIFT 0xc 3282 #define MMEA0_ADDRDEC0_ADDR_SEL_CS01__BANK4__SHIFT 0x10 3283 #define MMEA0_ADDRDEC0_ADDR_SEL_CS01__ROW_LO__SHIFT 0x18 3284 #define MMEA0_ADDRDEC0_ADDR_SEL_CS01__ROW_HI__SHIFT 0x1c 3285 #define MMEA0_ADDRDEC0_ADDR_SEL_CS01__BANK0_MASK 0x0000000FL 3286 #define MMEA0_ADDRDEC0_ADDR_SEL_CS01__BANK1_MASK 0x000000F0L 3287 #define MMEA0_ADDRDEC0_ADDR_SEL_CS01__BANK2_MASK 0x00000F00L 3288 #define MMEA0_ADDRDEC0_ADDR_SEL_CS01__BANK3_MASK 0x0000F000L 3289 #define MMEA0_ADDRDEC0_ADDR_SEL_CS01__BANK4_MASK 0x001F0000L 3290 #define MMEA0_ADDRDEC0_ADDR_SEL_CS01__ROW_LO_MASK 0x0F000000L 3291 #define MMEA0_ADDRDEC0_ADDR_SEL_CS01__ROW_HI_MASK 0xF0000000L 3292 //MMEA0_ADDRDEC0_ADDR_SEL_CS23 3293 #define MMEA0_ADDRDEC0_ADDR_SEL_CS23__BANK0__SHIFT 0x0 3294 #define MMEA0_ADDRDEC0_ADDR_SEL_CS23__BANK1__SHIFT 0x4 3295 #define MMEA0_ADDRDEC0_ADDR_SEL_CS23__BANK2__SHIFT 0x8 3296 #define MMEA0_ADDRDEC0_ADDR_SEL_CS23__BANK3__SHIFT 0xc 3297 #define MMEA0_ADDRDEC0_ADDR_SEL_CS23__BANK4__SHIFT 0x10 3298 #define MMEA0_ADDRDEC0_ADDR_SEL_CS23__ROW_LO__SHIFT 0x18 3299 #define MMEA0_ADDRDEC0_ADDR_SEL_CS23__ROW_HI__SHIFT 0x1c 3300 #define MMEA0_ADDRDEC0_ADDR_SEL_CS23__BANK0_MASK 0x0000000FL 3301 #define MMEA0_ADDRDEC0_ADDR_SEL_CS23__BANK1_MASK 0x000000F0L 3302 #define MMEA0_ADDRDEC0_ADDR_SEL_CS23__BANK2_MASK 0x00000F00L 3303 #define MMEA0_ADDRDEC0_ADDR_SEL_CS23__BANK3_MASK 0x0000F000L 3304 #define MMEA0_ADDRDEC0_ADDR_SEL_CS23__BANK4_MASK 0x001F0000L 3305 #define MMEA0_ADDRDEC0_ADDR_SEL_CS23__ROW_LO_MASK 0x0F000000L 3306 #define MMEA0_ADDRDEC0_ADDR_SEL_CS23__ROW_HI_MASK 0xF0000000L 3307 //MMEA0_ADDRDEC0_ADDR_SEL2_CS01 3308 #define MMEA0_ADDRDEC0_ADDR_SEL2_CS01__BANK5__SHIFT 0x0 3309 #define MMEA0_ADDRDEC0_ADDR_SEL2_CS01__CHAN_BIT__SHIFT 0xc 3310 #define MMEA0_ADDRDEC0_ADDR_SEL2_CS01__BANK5_MASK 0x0000001FL 3311 #define MMEA0_ADDRDEC0_ADDR_SEL2_CS01__CHAN_BIT_MASK 0x0000F000L 3312 //MMEA0_ADDRDEC0_ADDR_SEL2_CS23 3313 #define MMEA0_ADDRDEC0_ADDR_SEL2_CS23__BANK5__SHIFT 0x0 3314 #define MMEA0_ADDRDEC0_ADDR_SEL2_CS23__CHAN_BIT__SHIFT 0xc 3315 #define MMEA0_ADDRDEC0_ADDR_SEL2_CS23__BANK5_MASK 0x0000001FL 3316 #define MMEA0_ADDRDEC0_ADDR_SEL2_CS23__CHAN_BIT_MASK 0x0000F000L 3317 //MMEA0_ADDRDEC0_COL_SEL_LO_CS01 3318 #define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL0__SHIFT 0x0 3319 #define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL1__SHIFT 0x4 3320 #define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL2__SHIFT 0x8 3321 #define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL3__SHIFT 0xc 3322 #define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL4__SHIFT 0x10 3323 #define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL5__SHIFT 0x14 3324 #define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL6__SHIFT 0x18 3325 #define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL7__SHIFT 0x1c 3326 #define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL0_MASK 0x0000000FL 3327 #define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL1_MASK 0x000000F0L 3328 #define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL2_MASK 0x00000F00L 3329 #define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL3_MASK 0x0000F000L 3330 #define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL4_MASK 0x000F0000L 3331 #define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL5_MASK 0x00F00000L 3332 #define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL6_MASK 0x0F000000L 3333 #define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL7_MASK 0xF0000000L 3334 //MMEA0_ADDRDEC0_COL_SEL_LO_CS23 3335 #define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL0__SHIFT 0x0 3336 #define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL1__SHIFT 0x4 3337 #define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL2__SHIFT 0x8 3338 #define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL3__SHIFT 0xc 3339 #define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL4__SHIFT 0x10 3340 #define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL5__SHIFT 0x14 3341 #define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL6__SHIFT 0x18 3342 #define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL7__SHIFT 0x1c 3343 #define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL0_MASK 0x0000000FL 3344 #define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL1_MASK 0x000000F0L 3345 #define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL2_MASK 0x00000F00L 3346 #define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL3_MASK 0x0000F000L 3347 #define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL4_MASK 0x000F0000L 3348 #define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL5_MASK 0x00F00000L 3349 #define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL6_MASK 0x0F000000L 3350 #define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL7_MASK 0xF0000000L 3351 //MMEA0_ADDRDEC0_COL_SEL_HI_CS01 3352 #define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL8__SHIFT 0x0 3353 #define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL9__SHIFT 0x4 3354 #define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL10__SHIFT 0x8 3355 #define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL11__SHIFT 0xc 3356 #define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL12__SHIFT 0x10 3357 #define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL13__SHIFT 0x14 3358 #define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL14__SHIFT 0x18 3359 #define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL15__SHIFT 0x1c 3360 #define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL8_MASK 0x0000000FL 3361 #define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL9_MASK 0x000000F0L 3362 #define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL10_MASK 0x00000F00L 3363 #define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL11_MASK 0x0000F000L 3364 #define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL12_MASK 0x000F0000L 3365 #define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL13_MASK 0x00F00000L 3366 #define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL14_MASK 0x0F000000L 3367 #define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL15_MASK 0xF0000000L 3368 //MMEA0_ADDRDEC0_COL_SEL_HI_CS23 3369 #define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL8__SHIFT 0x0 3370 #define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL9__SHIFT 0x4 3371 #define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL10__SHIFT 0x8 3372 #define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL11__SHIFT 0xc 3373 #define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL12__SHIFT 0x10 3374 #define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL13__SHIFT 0x14 3375 #define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL14__SHIFT 0x18 3376 #define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL15__SHIFT 0x1c 3377 #define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL8_MASK 0x0000000FL 3378 #define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL9_MASK 0x000000F0L 3379 #define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL10_MASK 0x00000F00L 3380 #define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL11_MASK 0x0000F000L 3381 #define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL12_MASK 0x000F0000L 3382 #define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL13_MASK 0x00F00000L 3383 #define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL14_MASK 0x0F000000L 3384 #define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL15_MASK 0xF0000000L 3385 //MMEA0_ADDRDEC0_RM_SEL_CS01 3386 #define MMEA0_ADDRDEC0_RM_SEL_CS01__RM0__SHIFT 0x0 3387 #define MMEA0_ADDRDEC0_RM_SEL_CS01__RM1__SHIFT 0x4 3388 #define MMEA0_ADDRDEC0_RM_SEL_CS01__RM2__SHIFT 0x8 3389 #define MMEA0_ADDRDEC0_RM_SEL_CS01__CHAN_BIT__SHIFT 0x10 3390 #define MMEA0_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS__SHIFT 0x1c 3391 #define MMEA0_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_SEC__SHIFT 0x1e 3392 #define MMEA0_ADDRDEC0_RM_SEL_CS01__RM0_MASK 0x0000000FL 3393 #define MMEA0_ADDRDEC0_RM_SEL_CS01__RM1_MASK 0x000000F0L 3394 #define MMEA0_ADDRDEC0_RM_SEL_CS01__RM2_MASK 0x00000F00L 3395 #define MMEA0_ADDRDEC0_RM_SEL_CS01__CHAN_BIT_MASK 0x000F0000L 3396 #define MMEA0_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_MASK 0x30000000L 3397 #define MMEA0_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_SEC_MASK 0xC0000000L 3398 //MMEA0_ADDRDEC0_RM_SEL_CS23 3399 #define MMEA0_ADDRDEC0_RM_SEL_CS23__RM0__SHIFT 0x0 3400 #define MMEA0_ADDRDEC0_RM_SEL_CS23__RM1__SHIFT 0x4 3401 #define MMEA0_ADDRDEC0_RM_SEL_CS23__RM2__SHIFT 0x8 3402 #define MMEA0_ADDRDEC0_RM_SEL_CS23__CHAN_BIT__SHIFT 0x10 3403 #define MMEA0_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS__SHIFT 0x1c 3404 #define MMEA0_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_SEC__SHIFT 0x1e 3405 #define MMEA0_ADDRDEC0_RM_SEL_CS23__RM0_MASK 0x0000000FL 3406 #define MMEA0_ADDRDEC0_RM_SEL_CS23__RM1_MASK 0x000000F0L 3407 #define MMEA0_ADDRDEC0_RM_SEL_CS23__RM2_MASK 0x00000F00L 3408 #define MMEA0_ADDRDEC0_RM_SEL_CS23__CHAN_BIT_MASK 0x000F0000L 3409 #define MMEA0_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_MASK 0x30000000L 3410 #define MMEA0_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_SEC_MASK 0xC0000000L 3411 //MMEA0_ADDRDEC0_RM_SEL_CS1 3412 #define MMEA0_ADDRDEC0_RM_SEL_CS1__RM0__SHIFT 0x0 3413 #define MMEA0_ADDRDEC0_RM_SEL_CS1__RM1__SHIFT 0x4 3414 #define MMEA0_ADDRDEC0_RM_SEL_CS1__RM2__SHIFT 0x8 3415 #define MMEA0_ADDRDEC0_RM_SEL_CS1__CHAN_BIT__SHIFT 0x10 3416 #define MMEA0_ADDRDEC0_RM_SEL_CS1__INVERT_ROW_MSBS__SHIFT 0x1c 3417 #define MMEA0_ADDRDEC0_RM_SEL_CS1__INVERT_ROW_MSBS_SEC__SHIFT 0x1e 3418 #define MMEA0_ADDRDEC0_RM_SEL_CS1__RM0_MASK 0x0000000FL 3419 #define MMEA0_ADDRDEC0_RM_SEL_CS1__RM1_MASK 0x000000F0L 3420 #define MMEA0_ADDRDEC0_RM_SEL_CS1__RM2_MASK 0x00000F00L 3421 #define MMEA0_ADDRDEC0_RM_SEL_CS1__CHAN_BIT_MASK 0x000F0000L 3422 #define MMEA0_ADDRDEC0_RM_SEL_CS1__INVERT_ROW_MSBS_MASK 0x30000000L 3423 #define MMEA0_ADDRDEC0_RM_SEL_CS1__INVERT_ROW_MSBS_SEC_MASK 0xC0000000L 3424 //MMEA0_ADDRDEC0_RM_SEL_CS3 3425 #define MMEA0_ADDRDEC0_RM_SEL_CS3__RM0__SHIFT 0x0 3426 #define MMEA0_ADDRDEC0_RM_SEL_CS3__RM1__SHIFT 0x4 3427 #define MMEA0_ADDRDEC0_RM_SEL_CS3__RM2__SHIFT 0x8 3428 #define MMEA0_ADDRDEC0_RM_SEL_CS3__CHAN_BIT__SHIFT 0x10 3429 #define MMEA0_ADDRDEC0_RM_SEL_CS3__INVERT_ROW_MSBS__SHIFT 0x1c 3430 #define MMEA0_ADDRDEC0_RM_SEL_CS3__INVERT_ROW_MSBS_SEC__SHIFT 0x1e 3431 #define MMEA0_ADDRDEC0_RM_SEL_CS3__RM0_MASK 0x0000000FL 3432 #define MMEA0_ADDRDEC0_RM_SEL_CS3__RM1_MASK 0x000000F0L 3433 #define MMEA0_ADDRDEC0_RM_SEL_CS3__RM2_MASK 0x00000F00L 3434 #define MMEA0_ADDRDEC0_RM_SEL_CS3__CHAN_BIT_MASK 0x000F0000L 3435 #define MMEA0_ADDRDEC0_RM_SEL_CS3__INVERT_ROW_MSBS_MASK 0x30000000L 3436 #define MMEA0_ADDRDEC0_RM_SEL_CS3__INVERT_ROW_MSBS_SEC_MASK 0xC0000000L 3437 //MMEA0_ADDRDEC1_BASE_ADDR_CS0 3438 #define MMEA0_ADDRDEC1_BASE_ADDR_CS0__CS_EN__SHIFT 0x0 3439 #define MMEA0_ADDRDEC1_BASE_ADDR_CS0__BASE_ADDR__SHIFT 0x1 3440 #define MMEA0_ADDRDEC1_BASE_ADDR_CS0__CS_EN_MASK 0x00000001L 3441 #define MMEA0_ADDRDEC1_BASE_ADDR_CS0__BASE_ADDR_MASK 0xFFFFFFFEL 3442 //MMEA0_ADDRDEC1_BASE_ADDR_CS1 3443 #define MMEA0_ADDRDEC1_BASE_ADDR_CS1__CS_EN__SHIFT 0x0 3444 #define MMEA0_ADDRDEC1_BASE_ADDR_CS1__BASE_ADDR__SHIFT 0x1 3445 #define MMEA0_ADDRDEC1_BASE_ADDR_CS1__CS_EN_MASK 0x00000001L 3446 #define MMEA0_ADDRDEC1_BASE_ADDR_CS1__BASE_ADDR_MASK 0xFFFFFFFEL 3447 //MMEA0_ADDRDEC1_BASE_ADDR_CS2 3448 #define MMEA0_ADDRDEC1_BASE_ADDR_CS2__CS_EN__SHIFT 0x0 3449 #define MMEA0_ADDRDEC1_BASE_ADDR_CS2__BASE_ADDR__SHIFT 0x1 3450 #define MMEA0_ADDRDEC1_BASE_ADDR_CS2__CS_EN_MASK 0x00000001L 3451 #define MMEA0_ADDRDEC1_BASE_ADDR_CS2__BASE_ADDR_MASK 0xFFFFFFFEL 3452 //MMEA0_ADDRDEC1_BASE_ADDR_CS3 3453 #define MMEA0_ADDRDEC1_BASE_ADDR_CS3__CS_EN__SHIFT 0x0 3454 #define MMEA0_ADDRDEC1_BASE_ADDR_CS3__BASE_ADDR__SHIFT 0x1 3455 #define MMEA0_ADDRDEC1_BASE_ADDR_CS3__CS_EN_MASK 0x00000001L 3456 #define MMEA0_ADDRDEC1_BASE_ADDR_CS3__BASE_ADDR_MASK 0xFFFFFFFEL 3457 //MMEA0_ADDRDEC1_BASE_ADDR_SECCS0 3458 #define MMEA0_ADDRDEC1_BASE_ADDR_SECCS0__CS_EN__SHIFT 0x0 3459 #define MMEA0_ADDRDEC1_BASE_ADDR_SECCS0__BASE_ADDR__SHIFT 0x1 3460 #define MMEA0_ADDRDEC1_BASE_ADDR_SECCS0__CS_EN_MASK 0x00000001L 3461 #define MMEA0_ADDRDEC1_BASE_ADDR_SECCS0__BASE_ADDR_MASK 0xFFFFFFFEL 3462 //MMEA0_ADDRDEC1_BASE_ADDR_SECCS1 3463 #define MMEA0_ADDRDEC1_BASE_ADDR_SECCS1__CS_EN__SHIFT 0x0 3464 #define MMEA0_ADDRDEC1_BASE_ADDR_SECCS1__BASE_ADDR__SHIFT 0x1 3465 #define MMEA0_ADDRDEC1_BASE_ADDR_SECCS1__CS_EN_MASK 0x00000001L 3466 #define MMEA0_ADDRDEC1_BASE_ADDR_SECCS1__BASE_ADDR_MASK 0xFFFFFFFEL 3467 //MMEA0_ADDRDEC1_BASE_ADDR_SECCS2 3468 #define MMEA0_ADDRDEC1_BASE_ADDR_SECCS2__CS_EN__SHIFT 0x0 3469 #define MMEA0_ADDRDEC1_BASE_ADDR_SECCS2__BASE_ADDR__SHIFT 0x1 3470 #define MMEA0_ADDRDEC1_BASE_ADDR_SECCS2__CS_EN_MASK 0x00000001L 3471 #define MMEA0_ADDRDEC1_BASE_ADDR_SECCS2__BASE_ADDR_MASK 0xFFFFFFFEL 3472 //MMEA0_ADDRDEC1_BASE_ADDR_SECCS3 3473 #define MMEA0_ADDRDEC1_BASE_ADDR_SECCS3__CS_EN__SHIFT 0x0 3474 #define MMEA0_ADDRDEC1_BASE_ADDR_SECCS3__BASE_ADDR__SHIFT 0x1 3475 #define MMEA0_ADDRDEC1_BASE_ADDR_SECCS3__CS_EN_MASK 0x00000001L 3476 #define MMEA0_ADDRDEC1_BASE_ADDR_SECCS3__BASE_ADDR_MASK 0xFFFFFFFEL 3477 //MMEA0_ADDRDEC1_ADDR_MASK_CS01 3478 #define MMEA0_ADDRDEC1_ADDR_MASK_CS01__ADDR_MASK__SHIFT 0x1 3479 #define MMEA0_ADDRDEC1_ADDR_MASK_CS01__ADDR_MASK_MASK 0xFFFFFFFEL 3480 //MMEA0_ADDRDEC1_ADDR_MASK_CS23 3481 #define MMEA0_ADDRDEC1_ADDR_MASK_CS23__ADDR_MASK__SHIFT 0x1 3482 #define MMEA0_ADDRDEC1_ADDR_MASK_CS23__ADDR_MASK_MASK 0xFFFFFFFEL 3483 //MMEA0_ADDRDEC1_ADDR_MASK_SECCS01 3484 #define MMEA0_ADDRDEC1_ADDR_MASK_SECCS01__ADDR_MASK__SHIFT 0x1 3485 #define MMEA0_ADDRDEC1_ADDR_MASK_SECCS01__ADDR_MASK_MASK 0xFFFFFFFEL 3486 //MMEA0_ADDRDEC1_ADDR_MASK_SECCS23 3487 #define MMEA0_ADDRDEC1_ADDR_MASK_SECCS23__ADDR_MASK__SHIFT 0x1 3488 #define MMEA0_ADDRDEC1_ADDR_MASK_SECCS23__ADDR_MASK_MASK 0xFFFFFFFEL 3489 //MMEA0_ADDRDEC1_ADDR_CFG_CS01 3490 #define MMEA0_ADDRDEC1_ADDR_CFG_CS01__NUM_BANK_GROUPS__SHIFT 0x1 3491 #define MMEA0_ADDRDEC1_ADDR_CFG_CS01__NUM_RM__SHIFT 0x4 3492 #define MMEA0_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_LO__SHIFT 0x8 3493 #define MMEA0_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_HI__SHIFT 0xc 3494 #define MMEA0_ADDRDEC1_ADDR_CFG_CS01__NUM_COL__SHIFT 0x10 3495 #define MMEA0_ADDRDEC1_ADDR_CFG_CS01__NUM_BANKS__SHIFT 0x14 3496 #define MMEA0_ADDRDEC1_ADDR_CFG_CS01__HI_COL_EN__SHIFT 0x1f 3497 #define MMEA0_ADDRDEC1_ADDR_CFG_CS01__NUM_BANK_GROUPS_MASK 0x0000000EL 3498 #define MMEA0_ADDRDEC1_ADDR_CFG_CS01__NUM_RM_MASK 0x00000030L 3499 #define MMEA0_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_LO_MASK 0x00000F00L 3500 #define MMEA0_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_HI_MASK 0x0000F000L 3501 #define MMEA0_ADDRDEC1_ADDR_CFG_CS01__NUM_COL_MASK 0x000F0000L 3502 #define MMEA0_ADDRDEC1_ADDR_CFG_CS01__NUM_BANKS_MASK 0x00300000L 3503 #define MMEA0_ADDRDEC1_ADDR_CFG_CS01__HI_COL_EN_MASK 0x80000000L 3504 //MMEA0_ADDRDEC1_ADDR_CFG_CS23 3505 #define MMEA0_ADDRDEC1_ADDR_CFG_CS23__NUM_BANK_GROUPS__SHIFT 0x1 3506 #define MMEA0_ADDRDEC1_ADDR_CFG_CS23__NUM_RM__SHIFT 0x4 3507 #define MMEA0_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_LO__SHIFT 0x8 3508 #define MMEA0_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_HI__SHIFT 0xc 3509 #define MMEA0_ADDRDEC1_ADDR_CFG_CS23__NUM_COL__SHIFT 0x10 3510 #define MMEA0_ADDRDEC1_ADDR_CFG_CS23__NUM_BANKS__SHIFT 0x14 3511 #define MMEA0_ADDRDEC1_ADDR_CFG_CS23__HI_COL_EN__SHIFT 0x1f 3512 #define MMEA0_ADDRDEC1_ADDR_CFG_CS23__NUM_BANK_GROUPS_MASK 0x0000000EL 3513 #define MMEA0_ADDRDEC1_ADDR_CFG_CS23__NUM_RM_MASK 0x00000030L 3514 #define MMEA0_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_LO_MASK 0x00000F00L 3515 #define MMEA0_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_HI_MASK 0x0000F000L 3516 #define MMEA0_ADDRDEC1_ADDR_CFG_CS23__NUM_COL_MASK 0x000F0000L 3517 #define MMEA0_ADDRDEC1_ADDR_CFG_CS23__NUM_BANKS_MASK 0x00300000L 3518 #define MMEA0_ADDRDEC1_ADDR_CFG_CS23__HI_COL_EN_MASK 0x80000000L 3519 //MMEA0_ADDRDEC1_ADDR_SEL_CS01 3520 #define MMEA0_ADDRDEC1_ADDR_SEL_CS01__BANK0__SHIFT 0x0 3521 #define MMEA0_ADDRDEC1_ADDR_SEL_CS01__BANK1__SHIFT 0x4 3522 #define MMEA0_ADDRDEC1_ADDR_SEL_CS01__BANK2__SHIFT 0x8 3523 #define MMEA0_ADDRDEC1_ADDR_SEL_CS01__BANK3__SHIFT 0xc 3524 #define MMEA0_ADDRDEC1_ADDR_SEL_CS01__BANK4__SHIFT 0x10 3525 #define MMEA0_ADDRDEC1_ADDR_SEL_CS01__ROW_LO__SHIFT 0x18 3526 #define MMEA0_ADDRDEC1_ADDR_SEL_CS01__ROW_HI__SHIFT 0x1c 3527 #define MMEA0_ADDRDEC1_ADDR_SEL_CS01__BANK0_MASK 0x0000000FL 3528 #define MMEA0_ADDRDEC1_ADDR_SEL_CS01__BANK1_MASK 0x000000F0L 3529 #define MMEA0_ADDRDEC1_ADDR_SEL_CS01__BANK2_MASK 0x00000F00L 3530 #define MMEA0_ADDRDEC1_ADDR_SEL_CS01__BANK3_MASK 0x0000F000L 3531 #define MMEA0_ADDRDEC1_ADDR_SEL_CS01__BANK4_MASK 0x001F0000L 3532 #define MMEA0_ADDRDEC1_ADDR_SEL_CS01__ROW_LO_MASK 0x0F000000L 3533 #define MMEA0_ADDRDEC1_ADDR_SEL_CS01__ROW_HI_MASK 0xF0000000L 3534 //MMEA0_ADDRDEC1_ADDR_SEL_CS23 3535 #define MMEA0_ADDRDEC1_ADDR_SEL_CS23__BANK0__SHIFT 0x0 3536 #define MMEA0_ADDRDEC1_ADDR_SEL_CS23__BANK1__SHIFT 0x4 3537 #define MMEA0_ADDRDEC1_ADDR_SEL_CS23__BANK2__SHIFT 0x8 3538 #define MMEA0_ADDRDEC1_ADDR_SEL_CS23__BANK3__SHIFT 0xc 3539 #define MMEA0_ADDRDEC1_ADDR_SEL_CS23__BANK4__SHIFT 0x10 3540 #define MMEA0_ADDRDEC1_ADDR_SEL_CS23__ROW_LO__SHIFT 0x18 3541 #define MMEA0_ADDRDEC1_ADDR_SEL_CS23__ROW_HI__SHIFT 0x1c 3542 #define MMEA0_ADDRDEC1_ADDR_SEL_CS23__BANK0_MASK 0x0000000FL 3543 #define MMEA0_ADDRDEC1_ADDR_SEL_CS23__BANK1_MASK 0x000000F0L 3544 #define MMEA0_ADDRDEC1_ADDR_SEL_CS23__BANK2_MASK 0x00000F00L 3545 #define MMEA0_ADDRDEC1_ADDR_SEL_CS23__BANK3_MASK 0x0000F000L 3546 #define MMEA0_ADDRDEC1_ADDR_SEL_CS23__BANK4_MASK 0x001F0000L 3547 #define MMEA0_ADDRDEC1_ADDR_SEL_CS23__ROW_LO_MASK 0x0F000000L 3548 #define MMEA0_ADDRDEC1_ADDR_SEL_CS23__ROW_HI_MASK 0xF0000000L 3549 //MMEA0_ADDRDEC1_ADDR_SEL2_CS01 3550 #define MMEA0_ADDRDEC1_ADDR_SEL2_CS01__BANK5__SHIFT 0x0 3551 #define MMEA0_ADDRDEC1_ADDR_SEL2_CS01__CHAN_BIT__SHIFT 0xc 3552 #define MMEA0_ADDRDEC1_ADDR_SEL2_CS01__BANK5_MASK 0x0000001FL 3553 #define MMEA0_ADDRDEC1_ADDR_SEL2_CS01__CHAN_BIT_MASK 0x0000F000L 3554 //MMEA0_ADDRDEC1_ADDR_SEL2_CS23 3555 #define MMEA0_ADDRDEC1_ADDR_SEL2_CS23__BANK5__SHIFT 0x0 3556 #define MMEA0_ADDRDEC1_ADDR_SEL2_CS23__CHAN_BIT__SHIFT 0xc 3557 #define MMEA0_ADDRDEC1_ADDR_SEL2_CS23__BANK5_MASK 0x0000001FL 3558 #define MMEA0_ADDRDEC1_ADDR_SEL2_CS23__CHAN_BIT_MASK 0x0000F000L 3559 //MMEA0_ADDRDEC1_COL_SEL_LO_CS01 3560 #define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL0__SHIFT 0x0 3561 #define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL1__SHIFT 0x4 3562 #define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL2__SHIFT 0x8 3563 #define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL3__SHIFT 0xc 3564 #define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL4__SHIFT 0x10 3565 #define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL5__SHIFT 0x14 3566 #define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL6__SHIFT 0x18 3567 #define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL7__SHIFT 0x1c 3568 #define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL0_MASK 0x0000000FL 3569 #define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL1_MASK 0x000000F0L 3570 #define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL2_MASK 0x00000F00L 3571 #define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL3_MASK 0x0000F000L 3572 #define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL4_MASK 0x000F0000L 3573 #define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL5_MASK 0x00F00000L 3574 #define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL6_MASK 0x0F000000L 3575 #define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL7_MASK 0xF0000000L 3576 //MMEA0_ADDRDEC1_COL_SEL_LO_CS23 3577 #define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL0__SHIFT 0x0 3578 #define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL1__SHIFT 0x4 3579 #define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL2__SHIFT 0x8 3580 #define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL3__SHIFT 0xc 3581 #define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL4__SHIFT 0x10 3582 #define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL5__SHIFT 0x14 3583 #define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL6__SHIFT 0x18 3584 #define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL7__SHIFT 0x1c 3585 #define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL0_MASK 0x0000000FL 3586 #define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL1_MASK 0x000000F0L 3587 #define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL2_MASK 0x00000F00L 3588 #define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL3_MASK 0x0000F000L 3589 #define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL4_MASK 0x000F0000L 3590 #define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL5_MASK 0x00F00000L 3591 #define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL6_MASK 0x0F000000L 3592 #define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL7_MASK 0xF0000000L 3593 //MMEA0_ADDRDEC1_COL_SEL_HI_CS01 3594 #define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL8__SHIFT 0x0 3595 #define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL9__SHIFT 0x4 3596 #define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL10__SHIFT 0x8 3597 #define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL11__SHIFT 0xc 3598 #define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL12__SHIFT 0x10 3599 #define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL13__SHIFT 0x14 3600 #define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL14__SHIFT 0x18 3601 #define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL15__SHIFT 0x1c 3602 #define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL8_MASK 0x0000000FL 3603 #define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL9_MASK 0x000000F0L 3604 #define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL10_MASK 0x00000F00L 3605 #define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL11_MASK 0x0000F000L 3606 #define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL12_MASK 0x000F0000L 3607 #define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL13_MASK 0x00F00000L 3608 #define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL14_MASK 0x0F000000L 3609 #define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL15_MASK 0xF0000000L 3610 //MMEA0_ADDRDEC1_COL_SEL_HI_CS23 3611 #define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL8__SHIFT 0x0 3612 #define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL9__SHIFT 0x4 3613 #define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL10__SHIFT 0x8 3614 #define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL11__SHIFT 0xc 3615 #define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL12__SHIFT 0x10 3616 #define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL13__SHIFT 0x14 3617 #define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL14__SHIFT 0x18 3618 #define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL15__SHIFT 0x1c 3619 #define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL8_MASK 0x0000000FL 3620 #define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL9_MASK 0x000000F0L 3621 #define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL10_MASK 0x00000F00L 3622 #define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL11_MASK 0x0000F000L 3623 #define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL12_MASK 0x000F0000L 3624 #define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL13_MASK 0x00F00000L 3625 #define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL14_MASK 0x0F000000L 3626 #define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL15_MASK 0xF0000000L 3627 //MMEA0_ADDRDEC1_RM_SEL_CS01 3628 #define MMEA0_ADDRDEC1_RM_SEL_CS01__RM0__SHIFT 0x0 3629 #define MMEA0_ADDRDEC1_RM_SEL_CS01__RM1__SHIFT 0x4 3630 #define MMEA0_ADDRDEC1_RM_SEL_CS01__RM2__SHIFT 0x8 3631 #define MMEA0_ADDRDEC1_RM_SEL_CS01__CHAN_BIT__SHIFT 0x10 3632 #define MMEA0_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS__SHIFT 0x1c 3633 #define MMEA0_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_SEC__SHIFT 0x1e 3634 #define MMEA0_ADDRDEC1_RM_SEL_CS01__RM0_MASK 0x0000000FL 3635 #define MMEA0_ADDRDEC1_RM_SEL_CS01__RM1_MASK 0x000000F0L 3636 #define MMEA0_ADDRDEC1_RM_SEL_CS01__RM2_MASK 0x00000F00L 3637 #define MMEA0_ADDRDEC1_RM_SEL_CS01__CHAN_BIT_MASK 0x000F0000L 3638 #define MMEA0_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_MASK 0x30000000L 3639 #define MMEA0_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_SEC_MASK 0xC0000000L 3640 //MMEA0_ADDRDEC1_RM_SEL_CS23 3641 #define MMEA0_ADDRDEC1_RM_SEL_CS23__RM0__SHIFT 0x0 3642 #define MMEA0_ADDRDEC1_RM_SEL_CS23__RM1__SHIFT 0x4 3643 #define MMEA0_ADDRDEC1_RM_SEL_CS23__RM2__SHIFT 0x8 3644 #define MMEA0_ADDRDEC1_RM_SEL_CS23__CHAN_BIT__SHIFT 0x10 3645 #define MMEA0_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS__SHIFT 0x1c 3646 #define MMEA0_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_SEC__SHIFT 0x1e 3647 #define MMEA0_ADDRDEC1_RM_SEL_CS23__RM0_MASK 0x0000000FL 3648 #define MMEA0_ADDRDEC1_RM_SEL_CS23__RM1_MASK 0x000000F0L 3649 #define MMEA0_ADDRDEC1_RM_SEL_CS23__RM2_MASK 0x00000F00L 3650 #define MMEA0_ADDRDEC1_RM_SEL_CS23__CHAN_BIT_MASK 0x000F0000L 3651 #define MMEA0_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_MASK 0x30000000L 3652 #define MMEA0_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_SEC_MASK 0xC0000000L 3653 //MMEA0_ADDRDEC1_RM_SEL_CS1 3654 #define MMEA0_ADDRDEC1_RM_SEL_CS1__RM0__SHIFT 0x0 3655 #define MMEA0_ADDRDEC1_RM_SEL_CS1__RM1__SHIFT 0x4 3656 #define MMEA0_ADDRDEC1_RM_SEL_CS1__RM2__SHIFT 0x8 3657 #define MMEA0_ADDRDEC1_RM_SEL_CS1__CHAN_BIT__SHIFT 0x10 3658 #define MMEA0_ADDRDEC1_RM_SEL_CS1__INVERT_ROW_MSBS__SHIFT 0x1c 3659 #define MMEA0_ADDRDEC1_RM_SEL_CS1__INVERT_ROW_MSBS_SEC__SHIFT 0x1e 3660 #define MMEA0_ADDRDEC1_RM_SEL_CS1__RM0_MASK 0x0000000FL 3661 #define MMEA0_ADDRDEC1_RM_SEL_CS1__RM1_MASK 0x000000F0L 3662 #define MMEA0_ADDRDEC1_RM_SEL_CS1__RM2_MASK 0x00000F00L 3663 #define MMEA0_ADDRDEC1_RM_SEL_CS1__CHAN_BIT_MASK 0x000F0000L 3664 #define MMEA0_ADDRDEC1_RM_SEL_CS1__INVERT_ROW_MSBS_MASK 0x30000000L 3665 #define MMEA0_ADDRDEC1_RM_SEL_CS1__INVERT_ROW_MSBS_SEC_MASK 0xC0000000L 3666 //MMEA0_ADDRDEC1_RM_SEL_CS3 3667 #define MMEA0_ADDRDEC1_RM_SEL_CS3__RM0__SHIFT 0x0 3668 #define MMEA0_ADDRDEC1_RM_SEL_CS3__RM1__SHIFT 0x4 3669 #define MMEA0_ADDRDEC1_RM_SEL_CS3__RM2__SHIFT 0x8 3670 #define MMEA0_ADDRDEC1_RM_SEL_CS3__CHAN_BIT__SHIFT 0x10 3671 #define MMEA0_ADDRDEC1_RM_SEL_CS3__INVERT_ROW_MSBS__SHIFT 0x1c 3672 #define MMEA0_ADDRDEC1_RM_SEL_CS3__INVERT_ROW_MSBS_SEC__SHIFT 0x1e 3673 #define MMEA0_ADDRDEC1_RM_SEL_CS3__RM0_MASK 0x0000000FL 3674 #define MMEA0_ADDRDEC1_RM_SEL_CS3__RM1_MASK 0x000000F0L 3675 #define MMEA0_ADDRDEC1_RM_SEL_CS3__RM2_MASK 0x00000F00L 3676 #define MMEA0_ADDRDEC1_RM_SEL_CS3__CHAN_BIT_MASK 0x000F0000L 3677 #define MMEA0_ADDRDEC1_RM_SEL_CS3__INVERT_ROW_MSBS_MASK 0x30000000L 3678 #define MMEA0_ADDRDEC1_RM_SEL_CS3__INVERT_ROW_MSBS_SEC_MASK 0xC0000000L 3679 //MMEA0_ADDRNORMDRAM_GLOBAL_CNTL 3680 #define MMEA0_ADDRNORMDRAM_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_64K__SHIFT 0x14 3681 #define MMEA0_ADDRNORMDRAM_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_2M__SHIFT 0x15 3682 #define MMEA0_ADDRNORMDRAM_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_1G__SHIFT 0x16 3683 #define MMEA0_ADDRNORMDRAM_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_64K_MASK 0x00100000L 3684 #define MMEA0_ADDRNORMDRAM_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_2M_MASK 0x00200000L 3685 #define MMEA0_ADDRNORMDRAM_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_1G_MASK 0x00400000L 3686 //MMEA0_ADDRDECDRAM_GECC_HARV_ADJ0 3687 #define MMEA0_ADDRDECDRAM_GECC_HARV_ADJ0__START__SHIFT 0x0 3688 #define MMEA0_ADDRDECDRAM_GECC_HARV_ADJ0__END__SHIFT 0xa 3689 #define MMEA0_ADDRDECDRAM_GECC_HARV_ADJ0__SUB__SHIFT 0x14 3690 #define MMEA0_ADDRDECDRAM_GECC_HARV_ADJ0__START_MASK 0x000003FFL 3691 #define MMEA0_ADDRDECDRAM_GECC_HARV_ADJ0__END_MASK 0x000FFC00L 3692 #define MMEA0_ADDRDECDRAM_GECC_HARV_ADJ0__SUB_MASK 0x3FF00000L 3693 //MMEA0_ADDRDECDRAM_GECC_HARV_ADJ1 3694 #define MMEA0_ADDRDECDRAM_GECC_HARV_ADJ1__START__SHIFT 0x0 3695 #define MMEA0_ADDRDECDRAM_GECC_HARV_ADJ1__END__SHIFT 0xa 3696 #define MMEA0_ADDRDECDRAM_GECC_HARV_ADJ1__SUB__SHIFT 0x14 3697 #define MMEA0_ADDRDECDRAM_GECC_HARV_ADJ1__START_MASK 0x000003FFL 3698 #define MMEA0_ADDRDECDRAM_GECC_HARV_ADJ1__END_MASK 0x000FFC00L 3699 #define MMEA0_ADDRDECDRAM_GECC_HARV_ADJ1__SUB_MASK 0x3FF00000L 3700 //MMEA0_ADDRDECDRAM_GECC_HARV_ADJ2 3701 #define MMEA0_ADDRDECDRAM_GECC_HARV_ADJ2__START__SHIFT 0x0 3702 #define MMEA0_ADDRDECDRAM_GECC_HARV_ADJ2__END__SHIFT 0xa 3703 #define MMEA0_ADDRDECDRAM_GECC_HARV_ADJ2__SUB__SHIFT 0x14 3704 #define MMEA0_ADDRDECDRAM_GECC_HARV_ADJ2__START_MASK 0x000003FFL 3705 #define MMEA0_ADDRDECDRAM_GECC_HARV_ADJ2__END_MASK 0x000FFC00L 3706 #define MMEA0_ADDRDECDRAM_GECC_HARV_ADJ2__SUB_MASK 0x3FF00000L 3707 //MMEA0_ADDRDECDRAM_GECC_HARV_ADJ3 3708 #define MMEA0_ADDRDECDRAM_GECC_HARV_ADJ3__START__SHIFT 0x0 3709 #define MMEA0_ADDRDECDRAM_GECC_HARV_ADJ3__END__SHIFT 0xa 3710 #define MMEA0_ADDRDECDRAM_GECC_HARV_ADJ3__SUB__SHIFT 0x14 3711 #define MMEA0_ADDRDECDRAM_GECC_HARV_ADJ3__START_MASK 0x000003FFL 3712 #define MMEA0_ADDRDECDRAM_GECC_HARV_ADJ3__END_MASK 0x000FFC00L 3713 #define MMEA0_ADDRDECDRAM_GECC_HARV_ADJ3__SUB_MASK 0x3FF00000L 3714 //MMEA0_ADDRDECDRAM_GECC_HARV_ADJ4 3715 #define MMEA0_ADDRDECDRAM_GECC_HARV_ADJ4__START__SHIFT 0x0 3716 #define MMEA0_ADDRDECDRAM_GECC_HARV_ADJ4__END__SHIFT 0xa 3717 #define MMEA0_ADDRDECDRAM_GECC_HARV_ADJ4__SUB__SHIFT 0x14 3718 #define MMEA0_ADDRDECDRAM_GECC_HARV_ADJ4__START_MASK 0x000003FFL 3719 #define MMEA0_ADDRDECDRAM_GECC_HARV_ADJ4__END_MASK 0x000FFC00L 3720 #define MMEA0_ADDRDECDRAM_GECC_HARV_ADJ4__SUB_MASK 0x3FF00000L 3721 //MMEA0_ADDRDECDRAM_GECC_HARV_ADJ5 3722 #define MMEA0_ADDRDECDRAM_GECC_HARV_ADJ5__START__SHIFT 0x0 3723 #define MMEA0_ADDRDECDRAM_GECC_HARV_ADJ5__END__SHIFT 0xa 3724 #define MMEA0_ADDRDECDRAM_GECC_HARV_ADJ5__SUB__SHIFT 0x14 3725 #define MMEA0_ADDRDECDRAM_GECC_HARV_ADJ5__START_MASK 0x000003FFL 3726 #define MMEA0_ADDRDECDRAM_GECC_HARV_ADJ5__END_MASK 0x000FFC00L 3727 #define MMEA0_ADDRDECDRAM_GECC_HARV_ADJ5__SUB_MASK 0x3FF00000L 3728 //MMEA0_ADDRDEC0_ADDR_MASK_CS1 3729 #define MMEA0_ADDRDEC0_ADDR_MASK_CS1__ADDR_MASK__SHIFT 0x1 3730 #define MMEA0_ADDRDEC0_ADDR_MASK_CS1__ADDR_MASK_MASK 0xFFFFFFFEL 3731 //MMEA0_ADDRDEC0_ADDR_MASK_CS3 3732 #define MMEA0_ADDRDEC0_ADDR_MASK_CS3__ADDR_MASK__SHIFT 0x1 3733 #define MMEA0_ADDRDEC0_ADDR_MASK_CS3__ADDR_MASK_MASK 0xFFFFFFFEL 3734 //MMEA0_ADDRDEC0_ADDR_MASK_SECCS1 3735 #define MMEA0_ADDRDEC0_ADDR_MASK_SECCS1__ADDR_MASK__SHIFT 0x1 3736 #define MMEA0_ADDRDEC0_ADDR_MASK_SECCS1__ADDR_MASK_MASK 0xFFFFFFFEL 3737 //MMEA0_ADDRDEC0_ADDR_MASK_SECCS3 3738 #define MMEA0_ADDRDEC0_ADDR_MASK_SECCS3__ADDR_MASK__SHIFT 0x1 3739 #define MMEA0_ADDRDEC0_ADDR_MASK_SECCS3__ADDR_MASK_MASK 0xFFFFFFFEL 3740 //MMEA0_ADDRDEC0_ADDR_CFG_CS1 3741 #define MMEA0_ADDRDEC0_ADDR_CFG_CS1__NUM_BANK_GROUPS__SHIFT 0x1 3742 #define MMEA0_ADDRDEC0_ADDR_CFG_CS1__NUM_RM__SHIFT 0x4 3743 #define MMEA0_ADDRDEC0_ADDR_CFG_CS1__NUM_ROW_LO__SHIFT 0x8 3744 #define MMEA0_ADDRDEC0_ADDR_CFG_CS1__NUM_ROW_HI__SHIFT 0xc 3745 #define MMEA0_ADDRDEC0_ADDR_CFG_CS1__NUM_COL__SHIFT 0x10 3746 #define MMEA0_ADDRDEC0_ADDR_CFG_CS1__NUM_BANKS__SHIFT 0x14 3747 #define MMEA0_ADDRDEC0_ADDR_CFG_CS1__HI_COL_EN__SHIFT 0x1f 3748 #define MMEA0_ADDRDEC0_ADDR_CFG_CS1__NUM_BANK_GROUPS_MASK 0x0000000EL 3749 #define MMEA0_ADDRDEC0_ADDR_CFG_CS1__NUM_RM_MASK 0x00000030L 3750 #define MMEA0_ADDRDEC0_ADDR_CFG_CS1__NUM_ROW_LO_MASK 0x00000F00L 3751 #define MMEA0_ADDRDEC0_ADDR_CFG_CS1__NUM_ROW_HI_MASK 0x0000F000L 3752 #define MMEA0_ADDRDEC0_ADDR_CFG_CS1__NUM_COL_MASK 0x000F0000L 3753 #define MMEA0_ADDRDEC0_ADDR_CFG_CS1__NUM_BANKS_MASK 0x00300000L 3754 #define MMEA0_ADDRDEC0_ADDR_CFG_CS1__HI_COL_EN_MASK 0x80000000L 3755 //MMEA0_ADDRDEC0_ADDR_CFG_CS3 3756 #define MMEA0_ADDRDEC0_ADDR_CFG_CS3__NUM_BANK_GROUPS__SHIFT 0x1 3757 #define MMEA0_ADDRDEC0_ADDR_CFG_CS3__NUM_RM__SHIFT 0x4 3758 #define MMEA0_ADDRDEC0_ADDR_CFG_CS3__NUM_ROW_LO__SHIFT 0x8 3759 #define MMEA0_ADDRDEC0_ADDR_CFG_CS3__NUM_ROW_HI__SHIFT 0xc 3760 #define MMEA0_ADDRDEC0_ADDR_CFG_CS3__NUM_COL__SHIFT 0x10 3761 #define MMEA0_ADDRDEC0_ADDR_CFG_CS3__NUM_BANKS__SHIFT 0x14 3762 #define MMEA0_ADDRDEC0_ADDR_CFG_CS3__HI_COL_EN__SHIFT 0x1f 3763 #define MMEA0_ADDRDEC0_ADDR_CFG_CS3__NUM_BANK_GROUPS_MASK 0x0000000EL 3764 #define MMEA0_ADDRDEC0_ADDR_CFG_CS3__NUM_RM_MASK 0x00000030L 3765 #define MMEA0_ADDRDEC0_ADDR_CFG_CS3__NUM_ROW_LO_MASK 0x00000F00L 3766 #define MMEA0_ADDRDEC0_ADDR_CFG_CS3__NUM_ROW_HI_MASK 0x0000F000L 3767 #define MMEA0_ADDRDEC0_ADDR_CFG_CS3__NUM_COL_MASK 0x000F0000L 3768 #define MMEA0_ADDRDEC0_ADDR_CFG_CS3__NUM_BANKS_MASK 0x00300000L 3769 #define MMEA0_ADDRDEC0_ADDR_CFG_CS3__HI_COL_EN_MASK 0x80000000L 3770 //MMEA0_ADDRDEC0_ADDR_SEL_CS1 3771 #define MMEA0_ADDRDEC0_ADDR_SEL_CS1__BANK0__SHIFT 0x0 3772 #define MMEA0_ADDRDEC0_ADDR_SEL_CS1__BANK1__SHIFT 0x4 3773 #define MMEA0_ADDRDEC0_ADDR_SEL_CS1__BANK2__SHIFT 0x8 3774 #define MMEA0_ADDRDEC0_ADDR_SEL_CS1__BANK3__SHIFT 0xc 3775 #define MMEA0_ADDRDEC0_ADDR_SEL_CS1__BANK4__SHIFT 0x10 3776 #define MMEA0_ADDRDEC0_ADDR_SEL_CS1__ROW_LO__SHIFT 0x18 3777 #define MMEA0_ADDRDEC0_ADDR_SEL_CS1__ROW_HI__SHIFT 0x1c 3778 #define MMEA0_ADDRDEC0_ADDR_SEL_CS1__BANK0_MASK 0x0000000FL 3779 #define MMEA0_ADDRDEC0_ADDR_SEL_CS1__BANK1_MASK 0x000000F0L 3780 #define MMEA0_ADDRDEC0_ADDR_SEL_CS1__BANK2_MASK 0x00000F00L 3781 #define MMEA0_ADDRDEC0_ADDR_SEL_CS1__BANK3_MASK 0x0000F000L 3782 #define MMEA0_ADDRDEC0_ADDR_SEL_CS1__BANK4_MASK 0x001F0000L 3783 #define MMEA0_ADDRDEC0_ADDR_SEL_CS1__ROW_LO_MASK 0x0F000000L 3784 #define MMEA0_ADDRDEC0_ADDR_SEL_CS1__ROW_HI_MASK 0xF0000000L 3785 //MMEA0_ADDRDEC0_ADDR_SEL_CS3 3786 #define MMEA0_ADDRDEC0_ADDR_SEL_CS3__BANK0__SHIFT 0x0 3787 #define MMEA0_ADDRDEC0_ADDR_SEL_CS3__BANK1__SHIFT 0x4 3788 #define MMEA0_ADDRDEC0_ADDR_SEL_CS3__BANK2__SHIFT 0x8 3789 #define MMEA0_ADDRDEC0_ADDR_SEL_CS3__BANK3__SHIFT 0xc 3790 #define MMEA0_ADDRDEC0_ADDR_SEL_CS3__BANK4__SHIFT 0x10 3791 #define MMEA0_ADDRDEC0_ADDR_SEL_CS3__ROW_LO__SHIFT 0x18 3792 #define MMEA0_ADDRDEC0_ADDR_SEL_CS3__ROW_HI__SHIFT 0x1c 3793 #define MMEA0_ADDRDEC0_ADDR_SEL_CS3__BANK0_MASK 0x0000000FL 3794 #define MMEA0_ADDRDEC0_ADDR_SEL_CS3__BANK1_MASK 0x000000F0L 3795 #define MMEA0_ADDRDEC0_ADDR_SEL_CS3__BANK2_MASK 0x00000F00L 3796 #define MMEA0_ADDRDEC0_ADDR_SEL_CS3__BANK3_MASK 0x0000F000L 3797 #define MMEA0_ADDRDEC0_ADDR_SEL_CS3__BANK4_MASK 0x001F0000L 3798 #define MMEA0_ADDRDEC0_ADDR_SEL_CS3__ROW_LO_MASK 0x0F000000L 3799 #define MMEA0_ADDRDEC0_ADDR_SEL_CS3__ROW_HI_MASK 0xF0000000L 3800 //MMEA0_ADDRDEC0_COL_SEL_LO_CS1 3801 #define MMEA0_ADDRDEC0_COL_SEL_LO_CS1__COL0__SHIFT 0x0 3802 #define MMEA0_ADDRDEC0_COL_SEL_LO_CS1__COL1__SHIFT 0x4 3803 #define MMEA0_ADDRDEC0_COL_SEL_LO_CS1__COL2__SHIFT 0x8 3804 #define MMEA0_ADDRDEC0_COL_SEL_LO_CS1__COL3__SHIFT 0xc 3805 #define MMEA0_ADDRDEC0_COL_SEL_LO_CS1__COL4__SHIFT 0x10 3806 #define MMEA0_ADDRDEC0_COL_SEL_LO_CS1__COL5__SHIFT 0x14 3807 #define MMEA0_ADDRDEC0_COL_SEL_LO_CS1__COL6__SHIFT 0x18 3808 #define MMEA0_ADDRDEC0_COL_SEL_LO_CS1__COL7__SHIFT 0x1c 3809 #define MMEA0_ADDRDEC0_COL_SEL_LO_CS1__COL0_MASK 0x0000000FL 3810 #define MMEA0_ADDRDEC0_COL_SEL_LO_CS1__COL1_MASK 0x000000F0L 3811 #define MMEA0_ADDRDEC0_COL_SEL_LO_CS1__COL2_MASK 0x00000F00L 3812 #define MMEA0_ADDRDEC0_COL_SEL_LO_CS1__COL3_MASK 0x0000F000L 3813 #define MMEA0_ADDRDEC0_COL_SEL_LO_CS1__COL4_MASK 0x000F0000L 3814 #define MMEA0_ADDRDEC0_COL_SEL_LO_CS1__COL5_MASK 0x00F00000L 3815 #define MMEA0_ADDRDEC0_COL_SEL_LO_CS1__COL6_MASK 0x0F000000L 3816 #define MMEA0_ADDRDEC0_COL_SEL_LO_CS1__COL7_MASK 0xF0000000L 3817 //MMEA0_ADDRDEC0_COL_SEL_LO_CS3 3818 #define MMEA0_ADDRDEC0_COL_SEL_LO_CS3__COL0__SHIFT 0x0 3819 #define MMEA0_ADDRDEC0_COL_SEL_LO_CS3__COL1__SHIFT 0x4 3820 #define MMEA0_ADDRDEC0_COL_SEL_LO_CS3__COL2__SHIFT 0x8 3821 #define MMEA0_ADDRDEC0_COL_SEL_LO_CS3__COL3__SHIFT 0xc 3822 #define MMEA0_ADDRDEC0_COL_SEL_LO_CS3__COL4__SHIFT 0x10 3823 #define MMEA0_ADDRDEC0_COL_SEL_LO_CS3__COL5__SHIFT 0x14 3824 #define MMEA0_ADDRDEC0_COL_SEL_LO_CS3__COL6__SHIFT 0x18 3825 #define MMEA0_ADDRDEC0_COL_SEL_LO_CS3__COL7__SHIFT 0x1c 3826 #define MMEA0_ADDRDEC0_COL_SEL_LO_CS3__COL0_MASK 0x0000000FL 3827 #define MMEA0_ADDRDEC0_COL_SEL_LO_CS3__COL1_MASK 0x000000F0L 3828 #define MMEA0_ADDRDEC0_COL_SEL_LO_CS3__COL2_MASK 0x00000F00L 3829 #define MMEA0_ADDRDEC0_COL_SEL_LO_CS3__COL3_MASK 0x0000F000L 3830 #define MMEA0_ADDRDEC0_COL_SEL_LO_CS3__COL4_MASK 0x000F0000L 3831 #define MMEA0_ADDRDEC0_COL_SEL_LO_CS3__COL5_MASK 0x00F00000L 3832 #define MMEA0_ADDRDEC0_COL_SEL_LO_CS3__COL6_MASK 0x0F000000L 3833 #define MMEA0_ADDRDEC0_COL_SEL_LO_CS3__COL7_MASK 0xF0000000L 3834 //MMEA0_ADDRDEC0_COL_SEL_HI_CS1 3835 #define MMEA0_ADDRDEC0_COL_SEL_HI_CS1__COL8__SHIFT 0x0 3836 #define MMEA0_ADDRDEC0_COL_SEL_HI_CS1__COL9__SHIFT 0x4 3837 #define MMEA0_ADDRDEC0_COL_SEL_HI_CS1__COL10__SHIFT 0x8 3838 #define MMEA0_ADDRDEC0_COL_SEL_HI_CS1__COL11__SHIFT 0xc 3839 #define MMEA0_ADDRDEC0_COL_SEL_HI_CS1__COL12__SHIFT 0x10 3840 #define MMEA0_ADDRDEC0_COL_SEL_HI_CS1__COL13__SHIFT 0x14 3841 #define MMEA0_ADDRDEC0_COL_SEL_HI_CS1__COL14__SHIFT 0x18 3842 #define MMEA0_ADDRDEC0_COL_SEL_HI_CS1__COL15__SHIFT 0x1c 3843 #define MMEA0_ADDRDEC0_COL_SEL_HI_CS1__COL8_MASK 0x0000000FL 3844 #define MMEA0_ADDRDEC0_COL_SEL_HI_CS1__COL9_MASK 0x000000F0L 3845 #define MMEA0_ADDRDEC0_COL_SEL_HI_CS1__COL10_MASK 0x00000F00L 3846 #define MMEA0_ADDRDEC0_COL_SEL_HI_CS1__COL11_MASK 0x0000F000L 3847 #define MMEA0_ADDRDEC0_COL_SEL_HI_CS1__COL12_MASK 0x000F0000L 3848 #define MMEA0_ADDRDEC0_COL_SEL_HI_CS1__COL13_MASK 0x00F00000L 3849 #define MMEA0_ADDRDEC0_COL_SEL_HI_CS1__COL14_MASK 0x0F000000L 3850 #define MMEA0_ADDRDEC0_COL_SEL_HI_CS1__COL15_MASK 0xF0000000L 3851 //MMEA0_ADDRDEC0_COL_SEL_HI_CS3 3852 #define MMEA0_ADDRDEC0_COL_SEL_HI_CS3__COL8__SHIFT 0x0 3853 #define MMEA0_ADDRDEC0_COL_SEL_HI_CS3__COL9__SHIFT 0x4 3854 #define MMEA0_ADDRDEC0_COL_SEL_HI_CS3__COL10__SHIFT 0x8 3855 #define MMEA0_ADDRDEC0_COL_SEL_HI_CS3__COL11__SHIFT 0xc 3856 #define MMEA0_ADDRDEC0_COL_SEL_HI_CS3__COL12__SHIFT 0x10 3857 #define MMEA0_ADDRDEC0_COL_SEL_HI_CS3__COL13__SHIFT 0x14 3858 #define MMEA0_ADDRDEC0_COL_SEL_HI_CS3__COL14__SHIFT 0x18 3859 #define MMEA0_ADDRDEC0_COL_SEL_HI_CS3__COL15__SHIFT 0x1c 3860 #define MMEA0_ADDRDEC0_COL_SEL_HI_CS3__COL8_MASK 0x0000000FL 3861 #define MMEA0_ADDRDEC0_COL_SEL_HI_CS3__COL9_MASK 0x000000F0L 3862 #define MMEA0_ADDRDEC0_COL_SEL_HI_CS3__COL10_MASK 0x00000F00L 3863 #define MMEA0_ADDRDEC0_COL_SEL_HI_CS3__COL11_MASK 0x0000F000L 3864 #define MMEA0_ADDRDEC0_COL_SEL_HI_CS3__COL12_MASK 0x000F0000L 3865 #define MMEA0_ADDRDEC0_COL_SEL_HI_CS3__COL13_MASK 0x00F00000L 3866 #define MMEA0_ADDRDEC0_COL_SEL_HI_CS3__COL14_MASK 0x0F000000L 3867 #define MMEA0_ADDRDEC0_COL_SEL_HI_CS3__COL15_MASK 0xF0000000L 3868 //MMEA0_ADDRDEC1_ADDR_MASK_CS1 3869 #define MMEA0_ADDRDEC1_ADDR_MASK_CS1__ADDR_MASK__SHIFT 0x1 3870 #define MMEA0_ADDRDEC1_ADDR_MASK_CS1__ADDR_MASK_MASK 0xFFFFFFFEL 3871 //MMEA0_ADDRDEC1_ADDR_MASK_CS3 3872 #define MMEA0_ADDRDEC1_ADDR_MASK_CS3__ADDR_MASK__SHIFT 0x1 3873 #define MMEA0_ADDRDEC1_ADDR_MASK_CS3__ADDR_MASK_MASK 0xFFFFFFFEL 3874 //MMEA0_ADDRDEC1_ADDR_MASK_SECCS1 3875 #define MMEA0_ADDRDEC1_ADDR_MASK_SECCS1__ADDR_MASK__SHIFT 0x1 3876 #define MMEA0_ADDRDEC1_ADDR_MASK_SECCS1__ADDR_MASK_MASK 0xFFFFFFFEL 3877 //MMEA0_ADDRDEC1_ADDR_MASK_SECCS3 3878 #define MMEA0_ADDRDEC1_ADDR_MASK_SECCS3__ADDR_MASK__SHIFT 0x1 3879 #define MMEA0_ADDRDEC1_ADDR_MASK_SECCS3__ADDR_MASK_MASK 0xFFFFFFFEL 3880 //MMEA0_ADDRDEC1_ADDR_CFG_CS1 3881 #define MMEA0_ADDRDEC1_ADDR_CFG_CS1__NUM_BANK_GROUPS__SHIFT 0x1 3882 #define MMEA0_ADDRDEC1_ADDR_CFG_CS1__NUM_RM__SHIFT 0x4 3883 #define MMEA0_ADDRDEC1_ADDR_CFG_CS1__NUM_ROW_LO__SHIFT 0x8 3884 #define MMEA0_ADDRDEC1_ADDR_CFG_CS1__NUM_ROW_HI__SHIFT 0xc 3885 #define MMEA0_ADDRDEC1_ADDR_CFG_CS1__NUM_COL__SHIFT 0x10 3886 #define MMEA0_ADDRDEC1_ADDR_CFG_CS1__NUM_BANKS__SHIFT 0x14 3887 #define MMEA0_ADDRDEC1_ADDR_CFG_CS1__HI_COL_EN__SHIFT 0x1f 3888 #define MMEA0_ADDRDEC1_ADDR_CFG_CS1__NUM_BANK_GROUPS_MASK 0x0000000EL 3889 #define MMEA0_ADDRDEC1_ADDR_CFG_CS1__NUM_RM_MASK 0x00000030L 3890 #define MMEA0_ADDRDEC1_ADDR_CFG_CS1__NUM_ROW_LO_MASK 0x00000F00L 3891 #define MMEA0_ADDRDEC1_ADDR_CFG_CS1__NUM_ROW_HI_MASK 0x0000F000L 3892 #define MMEA0_ADDRDEC1_ADDR_CFG_CS1__NUM_COL_MASK 0x000F0000L 3893 #define MMEA0_ADDRDEC1_ADDR_CFG_CS1__NUM_BANKS_MASK 0x00300000L 3894 #define MMEA0_ADDRDEC1_ADDR_CFG_CS1__HI_COL_EN_MASK 0x80000000L 3895 //MMEA0_ADDRDEC1_ADDR_CFG_CS3 3896 #define MMEA0_ADDRDEC1_ADDR_CFG_CS3__NUM_BANK_GROUPS__SHIFT 0x1 3897 #define MMEA0_ADDRDEC1_ADDR_CFG_CS3__NUM_RM__SHIFT 0x4 3898 #define MMEA0_ADDRDEC1_ADDR_CFG_CS3__NUM_ROW_LO__SHIFT 0x8 3899 #define MMEA0_ADDRDEC1_ADDR_CFG_CS3__NUM_ROW_HI__SHIFT 0xc 3900 #define MMEA0_ADDRDEC1_ADDR_CFG_CS3__NUM_COL__SHIFT 0x10 3901 #define MMEA0_ADDRDEC1_ADDR_CFG_CS3__NUM_BANKS__SHIFT 0x14 3902 #define MMEA0_ADDRDEC1_ADDR_CFG_CS3__HI_COL_EN__SHIFT 0x1f 3903 #define MMEA0_ADDRDEC1_ADDR_CFG_CS3__NUM_BANK_GROUPS_MASK 0x0000000EL 3904 #define MMEA0_ADDRDEC1_ADDR_CFG_CS3__NUM_RM_MASK 0x00000030L 3905 #define MMEA0_ADDRDEC1_ADDR_CFG_CS3__NUM_ROW_LO_MASK 0x00000F00L 3906 #define MMEA0_ADDRDEC1_ADDR_CFG_CS3__NUM_ROW_HI_MASK 0x0000F000L 3907 #define MMEA0_ADDRDEC1_ADDR_CFG_CS3__NUM_COL_MASK 0x000F0000L 3908 #define MMEA0_ADDRDEC1_ADDR_CFG_CS3__NUM_BANKS_MASK 0x00300000L 3909 #define MMEA0_ADDRDEC1_ADDR_CFG_CS3__HI_COL_EN_MASK 0x80000000L 3910 //MMEA0_ADDRDEC1_ADDR_SEL_CS1 3911 #define MMEA0_ADDRDEC1_ADDR_SEL_CS1__BANK0__SHIFT 0x0 3912 #define MMEA0_ADDRDEC1_ADDR_SEL_CS1__BANK1__SHIFT 0x4 3913 #define MMEA0_ADDRDEC1_ADDR_SEL_CS1__BANK2__SHIFT 0x8 3914 #define MMEA0_ADDRDEC1_ADDR_SEL_CS1__BANK3__SHIFT 0xc 3915 #define MMEA0_ADDRDEC1_ADDR_SEL_CS1__BANK4__SHIFT 0x10 3916 #define MMEA0_ADDRDEC1_ADDR_SEL_CS1__ROW_LO__SHIFT 0x18 3917 #define MMEA0_ADDRDEC1_ADDR_SEL_CS1__ROW_HI__SHIFT 0x1c 3918 #define MMEA0_ADDRDEC1_ADDR_SEL_CS1__BANK0_MASK 0x0000000FL 3919 #define MMEA0_ADDRDEC1_ADDR_SEL_CS1__BANK1_MASK 0x000000F0L 3920 #define MMEA0_ADDRDEC1_ADDR_SEL_CS1__BANK2_MASK 0x00000F00L 3921 #define MMEA0_ADDRDEC1_ADDR_SEL_CS1__BANK3_MASK 0x0000F000L 3922 #define MMEA0_ADDRDEC1_ADDR_SEL_CS1__BANK4_MASK 0x001F0000L 3923 #define MMEA0_ADDRDEC1_ADDR_SEL_CS1__ROW_LO_MASK 0x0F000000L 3924 #define MMEA0_ADDRDEC1_ADDR_SEL_CS1__ROW_HI_MASK 0xF0000000L 3925 //MMEA0_ADDRDEC1_ADDR_SEL_CS3 3926 #define MMEA0_ADDRDEC1_ADDR_SEL_CS3__BANK0__SHIFT 0x0 3927 #define MMEA0_ADDRDEC1_ADDR_SEL_CS3__BANK1__SHIFT 0x4 3928 #define MMEA0_ADDRDEC1_ADDR_SEL_CS3__BANK2__SHIFT 0x8 3929 #define MMEA0_ADDRDEC1_ADDR_SEL_CS3__BANK3__SHIFT 0xc 3930 #define MMEA0_ADDRDEC1_ADDR_SEL_CS3__BANK4__SHIFT 0x10 3931 #define MMEA0_ADDRDEC1_ADDR_SEL_CS3__ROW_LO__SHIFT 0x18 3932 #define MMEA0_ADDRDEC1_ADDR_SEL_CS3__ROW_HI__SHIFT 0x1c 3933 #define MMEA0_ADDRDEC1_ADDR_SEL_CS3__BANK0_MASK 0x0000000FL 3934 #define MMEA0_ADDRDEC1_ADDR_SEL_CS3__BANK1_MASK 0x000000F0L 3935 #define MMEA0_ADDRDEC1_ADDR_SEL_CS3__BANK2_MASK 0x00000F00L 3936 #define MMEA0_ADDRDEC1_ADDR_SEL_CS3__BANK3_MASK 0x0000F000L 3937 #define MMEA0_ADDRDEC1_ADDR_SEL_CS3__BANK4_MASK 0x001F0000L 3938 #define MMEA0_ADDRDEC1_ADDR_SEL_CS3__ROW_LO_MASK 0x0F000000L 3939 #define MMEA0_ADDRDEC1_ADDR_SEL_CS3__ROW_HI_MASK 0xF0000000L 3940 //MMEA0_ADDRDEC1_COL_SEL_LO_CS1 3941 #define MMEA0_ADDRDEC1_COL_SEL_LO_CS1__COL0__SHIFT 0x0 3942 #define MMEA0_ADDRDEC1_COL_SEL_LO_CS1__COL1__SHIFT 0x4 3943 #define MMEA0_ADDRDEC1_COL_SEL_LO_CS1__COL2__SHIFT 0x8 3944 #define MMEA0_ADDRDEC1_COL_SEL_LO_CS1__COL3__SHIFT 0xc 3945 #define MMEA0_ADDRDEC1_COL_SEL_LO_CS1__COL4__SHIFT 0x10 3946 #define MMEA0_ADDRDEC1_COL_SEL_LO_CS1__COL5__SHIFT 0x14 3947 #define MMEA0_ADDRDEC1_COL_SEL_LO_CS1__COL6__SHIFT 0x18 3948 #define MMEA0_ADDRDEC1_COL_SEL_LO_CS1__COL7__SHIFT 0x1c 3949 #define MMEA0_ADDRDEC1_COL_SEL_LO_CS1__COL0_MASK 0x0000000FL 3950 #define MMEA0_ADDRDEC1_COL_SEL_LO_CS1__COL1_MASK 0x000000F0L 3951 #define MMEA0_ADDRDEC1_COL_SEL_LO_CS1__COL2_MASK 0x00000F00L 3952 #define MMEA0_ADDRDEC1_COL_SEL_LO_CS1__COL3_MASK 0x0000F000L 3953 #define MMEA0_ADDRDEC1_COL_SEL_LO_CS1__COL4_MASK 0x000F0000L 3954 #define MMEA0_ADDRDEC1_COL_SEL_LO_CS1__COL5_MASK 0x00F00000L 3955 #define MMEA0_ADDRDEC1_COL_SEL_LO_CS1__COL6_MASK 0x0F000000L 3956 #define MMEA0_ADDRDEC1_COL_SEL_LO_CS1__COL7_MASK 0xF0000000L 3957 //MMEA0_ADDRDEC1_COL_SEL_LO_CS3 3958 #define MMEA0_ADDRDEC1_COL_SEL_LO_CS3__COL0__SHIFT 0x0 3959 #define MMEA0_ADDRDEC1_COL_SEL_LO_CS3__COL1__SHIFT 0x4 3960 #define MMEA0_ADDRDEC1_COL_SEL_LO_CS3__COL2__SHIFT 0x8 3961 #define MMEA0_ADDRDEC1_COL_SEL_LO_CS3__COL3__SHIFT 0xc 3962 #define MMEA0_ADDRDEC1_COL_SEL_LO_CS3__COL4__SHIFT 0x10 3963 #define MMEA0_ADDRDEC1_COL_SEL_LO_CS3__COL5__SHIFT 0x14 3964 #define MMEA0_ADDRDEC1_COL_SEL_LO_CS3__COL6__SHIFT 0x18 3965 #define MMEA0_ADDRDEC1_COL_SEL_LO_CS3__COL7__SHIFT 0x1c 3966 #define MMEA0_ADDRDEC1_COL_SEL_LO_CS3__COL0_MASK 0x0000000FL 3967 #define MMEA0_ADDRDEC1_COL_SEL_LO_CS3__COL1_MASK 0x000000F0L 3968 #define MMEA0_ADDRDEC1_COL_SEL_LO_CS3__COL2_MASK 0x00000F00L 3969 #define MMEA0_ADDRDEC1_COL_SEL_LO_CS3__COL3_MASK 0x0000F000L 3970 #define MMEA0_ADDRDEC1_COL_SEL_LO_CS3__COL4_MASK 0x000F0000L 3971 #define MMEA0_ADDRDEC1_COL_SEL_LO_CS3__COL5_MASK 0x00F00000L 3972 #define MMEA0_ADDRDEC1_COL_SEL_LO_CS3__COL6_MASK 0x0F000000L 3973 #define MMEA0_ADDRDEC1_COL_SEL_LO_CS3__COL7_MASK 0xF0000000L 3974 //MMEA0_ADDRDEC1_COL_SEL_HI_CS1 3975 #define MMEA0_ADDRDEC1_COL_SEL_HI_CS1__COL8__SHIFT 0x0 3976 #define MMEA0_ADDRDEC1_COL_SEL_HI_CS1__COL9__SHIFT 0x4 3977 #define MMEA0_ADDRDEC1_COL_SEL_HI_CS1__COL10__SHIFT 0x8 3978 #define MMEA0_ADDRDEC1_COL_SEL_HI_CS1__COL11__SHIFT 0xc 3979 #define MMEA0_ADDRDEC1_COL_SEL_HI_CS1__COL12__SHIFT 0x10 3980 #define MMEA0_ADDRDEC1_COL_SEL_HI_CS1__COL13__SHIFT 0x14 3981 #define MMEA0_ADDRDEC1_COL_SEL_HI_CS1__COL14__SHIFT 0x18 3982 #define MMEA0_ADDRDEC1_COL_SEL_HI_CS1__COL15__SHIFT 0x1c 3983 #define MMEA0_ADDRDEC1_COL_SEL_HI_CS1__COL8_MASK 0x0000000FL 3984 #define MMEA0_ADDRDEC1_COL_SEL_HI_CS1__COL9_MASK 0x000000F0L 3985 #define MMEA0_ADDRDEC1_COL_SEL_HI_CS1__COL10_MASK 0x00000F00L 3986 #define MMEA0_ADDRDEC1_COL_SEL_HI_CS1__COL11_MASK 0x0000F000L 3987 #define MMEA0_ADDRDEC1_COL_SEL_HI_CS1__COL12_MASK 0x000F0000L 3988 #define MMEA0_ADDRDEC1_COL_SEL_HI_CS1__COL13_MASK 0x00F00000L 3989 #define MMEA0_ADDRDEC1_COL_SEL_HI_CS1__COL14_MASK 0x0F000000L 3990 #define MMEA0_ADDRDEC1_COL_SEL_HI_CS1__COL15_MASK 0xF0000000L 3991 //MMEA0_ADDRDEC1_COL_SEL_HI_CS3 3992 #define MMEA0_ADDRDEC1_COL_SEL_HI_CS3__COL8__SHIFT 0x0 3993 #define MMEA0_ADDRDEC1_COL_SEL_HI_CS3__COL9__SHIFT 0x4 3994 #define MMEA0_ADDRDEC1_COL_SEL_HI_CS3__COL10__SHIFT 0x8 3995 #define MMEA0_ADDRDEC1_COL_SEL_HI_CS3__COL11__SHIFT 0xc 3996 #define MMEA0_ADDRDEC1_COL_SEL_HI_CS3__COL12__SHIFT 0x10 3997 #define MMEA0_ADDRDEC1_COL_SEL_HI_CS3__COL13__SHIFT 0x14 3998 #define MMEA0_ADDRDEC1_COL_SEL_HI_CS3__COL14__SHIFT 0x18 3999 #define MMEA0_ADDRDEC1_COL_SEL_HI_CS3__COL15__SHIFT 0x1c 4000 #define MMEA0_ADDRDEC1_COL_SEL_HI_CS3__COL8_MASK 0x0000000FL 4001 #define MMEA0_ADDRDEC1_COL_SEL_HI_CS3__COL9_MASK 0x000000F0L 4002 #define MMEA0_ADDRDEC1_COL_SEL_HI_CS3__COL10_MASK 0x00000F00L 4003 #define MMEA0_ADDRDEC1_COL_SEL_HI_CS3__COL11_MASK 0x0000F000L 4004 #define MMEA0_ADDRDEC1_COL_SEL_HI_CS3__COL12_MASK 0x000F0000L 4005 #define MMEA0_ADDRDEC1_COL_SEL_HI_CS3__COL13_MASK 0x00F00000L 4006 #define MMEA0_ADDRDEC1_COL_SEL_HI_CS3__COL14_MASK 0x0F000000L 4007 #define MMEA0_ADDRDEC1_COL_SEL_HI_CS3__COL15_MASK 0xF0000000L 4008 //MMEA0_ADDRNORMDRAM_MASKING 4009 #define MMEA0_ADDRNORMDRAM_MASKING__ADDRHI_MASK__SHIFT 0x0 4010 #define MMEA0_ADDRNORMDRAM_MASKING__ADDRHI_MASK_MASK 0x00000FFFL 4011 //MMEA0_IO_RD_CLI2GRP_MAP0 4012 #define MMEA0_IO_RD_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 4013 #define MMEA0_IO_RD_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 4014 #define MMEA0_IO_RD_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 4015 #define MMEA0_IO_RD_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 4016 #define MMEA0_IO_RD_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 4017 #define MMEA0_IO_RD_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa 4018 #define MMEA0_IO_RD_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc 4019 #define MMEA0_IO_RD_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe 4020 #define MMEA0_IO_RD_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 4021 #define MMEA0_IO_RD_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 4022 #define MMEA0_IO_RD_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 4023 #define MMEA0_IO_RD_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 4024 #define MMEA0_IO_RD_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 4025 #define MMEA0_IO_RD_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a 4026 #define MMEA0_IO_RD_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c 4027 #define MMEA0_IO_RD_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e 4028 #define MMEA0_IO_RD_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L 4029 #define MMEA0_IO_RD_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL 4030 #define MMEA0_IO_RD_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L 4031 #define MMEA0_IO_RD_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L 4032 #define MMEA0_IO_RD_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L 4033 #define MMEA0_IO_RD_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L 4034 #define MMEA0_IO_RD_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L 4035 #define MMEA0_IO_RD_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L 4036 #define MMEA0_IO_RD_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L 4037 #define MMEA0_IO_RD_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L 4038 #define MMEA0_IO_RD_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L 4039 #define MMEA0_IO_RD_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L 4040 #define MMEA0_IO_RD_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L 4041 #define MMEA0_IO_RD_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L 4042 #define MMEA0_IO_RD_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L 4043 #define MMEA0_IO_RD_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L 4044 //MMEA0_IO_RD_CLI2GRP_MAP1 4045 #define MMEA0_IO_RD_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 4046 #define MMEA0_IO_RD_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 4047 #define MMEA0_IO_RD_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 4048 #define MMEA0_IO_RD_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 4049 #define MMEA0_IO_RD_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 4050 #define MMEA0_IO_RD_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa 4051 #define MMEA0_IO_RD_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc 4052 #define MMEA0_IO_RD_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe 4053 #define MMEA0_IO_RD_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 4054 #define MMEA0_IO_RD_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 4055 #define MMEA0_IO_RD_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 4056 #define MMEA0_IO_RD_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 4057 #define MMEA0_IO_RD_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 4058 #define MMEA0_IO_RD_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a 4059 #define MMEA0_IO_RD_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c 4060 #define MMEA0_IO_RD_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e 4061 #define MMEA0_IO_RD_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L 4062 #define MMEA0_IO_RD_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL 4063 #define MMEA0_IO_RD_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L 4064 #define MMEA0_IO_RD_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L 4065 #define MMEA0_IO_RD_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L 4066 #define MMEA0_IO_RD_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L 4067 #define MMEA0_IO_RD_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L 4068 #define MMEA0_IO_RD_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L 4069 #define MMEA0_IO_RD_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L 4070 #define MMEA0_IO_RD_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L 4071 #define MMEA0_IO_RD_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L 4072 #define MMEA0_IO_RD_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L 4073 #define MMEA0_IO_RD_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L 4074 #define MMEA0_IO_RD_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L 4075 #define MMEA0_IO_RD_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L 4076 #define MMEA0_IO_RD_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L 4077 //MMEA0_IO_WR_CLI2GRP_MAP0 4078 #define MMEA0_IO_WR_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 4079 #define MMEA0_IO_WR_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 4080 #define MMEA0_IO_WR_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 4081 #define MMEA0_IO_WR_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 4082 #define MMEA0_IO_WR_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 4083 #define MMEA0_IO_WR_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa 4084 #define MMEA0_IO_WR_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc 4085 #define MMEA0_IO_WR_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe 4086 #define MMEA0_IO_WR_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 4087 #define MMEA0_IO_WR_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 4088 #define MMEA0_IO_WR_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 4089 #define MMEA0_IO_WR_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 4090 #define MMEA0_IO_WR_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 4091 #define MMEA0_IO_WR_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a 4092 #define MMEA0_IO_WR_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c 4093 #define MMEA0_IO_WR_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e 4094 #define MMEA0_IO_WR_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L 4095 #define MMEA0_IO_WR_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL 4096 #define MMEA0_IO_WR_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L 4097 #define MMEA0_IO_WR_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L 4098 #define MMEA0_IO_WR_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L 4099 #define MMEA0_IO_WR_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L 4100 #define MMEA0_IO_WR_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L 4101 #define MMEA0_IO_WR_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L 4102 #define MMEA0_IO_WR_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L 4103 #define MMEA0_IO_WR_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L 4104 #define MMEA0_IO_WR_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L 4105 #define MMEA0_IO_WR_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L 4106 #define MMEA0_IO_WR_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L 4107 #define MMEA0_IO_WR_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L 4108 #define MMEA0_IO_WR_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L 4109 #define MMEA0_IO_WR_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L 4110 //MMEA0_IO_WR_CLI2GRP_MAP1 4111 #define MMEA0_IO_WR_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 4112 #define MMEA0_IO_WR_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 4113 #define MMEA0_IO_WR_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 4114 #define MMEA0_IO_WR_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 4115 #define MMEA0_IO_WR_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 4116 #define MMEA0_IO_WR_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa 4117 #define MMEA0_IO_WR_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc 4118 #define MMEA0_IO_WR_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe 4119 #define MMEA0_IO_WR_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 4120 #define MMEA0_IO_WR_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 4121 #define MMEA0_IO_WR_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 4122 #define MMEA0_IO_WR_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 4123 #define MMEA0_IO_WR_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 4124 #define MMEA0_IO_WR_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a 4125 #define MMEA0_IO_WR_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c 4126 #define MMEA0_IO_WR_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e 4127 #define MMEA0_IO_WR_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L 4128 #define MMEA0_IO_WR_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL 4129 #define MMEA0_IO_WR_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L 4130 #define MMEA0_IO_WR_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L 4131 #define MMEA0_IO_WR_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L 4132 #define MMEA0_IO_WR_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L 4133 #define MMEA0_IO_WR_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L 4134 #define MMEA0_IO_WR_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L 4135 #define MMEA0_IO_WR_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L 4136 #define MMEA0_IO_WR_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L 4137 #define MMEA0_IO_WR_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L 4138 #define MMEA0_IO_WR_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L 4139 #define MMEA0_IO_WR_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L 4140 #define MMEA0_IO_WR_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L 4141 #define MMEA0_IO_WR_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L 4142 #define MMEA0_IO_WR_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L 4143 //MMEA0_IO_RD_COMBINE_FLUSH 4144 #define MMEA0_IO_RD_COMBINE_FLUSH__GROUP0_TIMER__SHIFT 0x0 4145 #define MMEA0_IO_RD_COMBINE_FLUSH__GROUP1_TIMER__SHIFT 0x4 4146 #define MMEA0_IO_RD_COMBINE_FLUSH__GROUP2_TIMER__SHIFT 0x8 4147 #define MMEA0_IO_RD_COMBINE_FLUSH__GROUP3_TIMER__SHIFT 0xc 4148 #define MMEA0_IO_RD_COMBINE_FLUSH__COMB_MODE__SHIFT 0x10 4149 #define MMEA0_IO_RD_COMBINE_FLUSH__GROUP0_TIMER_MASK 0x0000000FL 4150 #define MMEA0_IO_RD_COMBINE_FLUSH__GROUP1_TIMER_MASK 0x000000F0L 4151 #define MMEA0_IO_RD_COMBINE_FLUSH__GROUP2_TIMER_MASK 0x00000F00L 4152 #define MMEA0_IO_RD_COMBINE_FLUSH__GROUP3_TIMER_MASK 0x0000F000L 4153 #define MMEA0_IO_RD_COMBINE_FLUSH__COMB_MODE_MASK 0x00030000L 4154 //MMEA0_IO_WR_COMBINE_FLUSH 4155 #define MMEA0_IO_WR_COMBINE_FLUSH__GROUP0_TIMER__SHIFT 0x0 4156 #define MMEA0_IO_WR_COMBINE_FLUSH__GROUP1_TIMER__SHIFT 0x4 4157 #define MMEA0_IO_WR_COMBINE_FLUSH__GROUP2_TIMER__SHIFT 0x8 4158 #define MMEA0_IO_WR_COMBINE_FLUSH__GROUP3_TIMER__SHIFT 0xc 4159 #define MMEA0_IO_WR_COMBINE_FLUSH__COMB_MODE__SHIFT 0x10 4160 #define MMEA0_IO_WR_COMBINE_FLUSH__GROUP0_TIMER_MASK 0x0000000FL 4161 #define MMEA0_IO_WR_COMBINE_FLUSH__GROUP1_TIMER_MASK 0x000000F0L 4162 #define MMEA0_IO_WR_COMBINE_FLUSH__GROUP2_TIMER_MASK 0x00000F00L 4163 #define MMEA0_IO_WR_COMBINE_FLUSH__GROUP3_TIMER_MASK 0x0000F000L 4164 #define MMEA0_IO_WR_COMBINE_FLUSH__COMB_MODE_MASK 0x00030000L 4165 //MMEA0_IO_GROUP_BURST 4166 #define MMEA0_IO_GROUP_BURST__RD_LIMIT_LO__SHIFT 0x0 4167 #define MMEA0_IO_GROUP_BURST__RD_LIMIT_HI__SHIFT 0x8 4168 #define MMEA0_IO_GROUP_BURST__WR_LIMIT_LO__SHIFT 0x10 4169 #define MMEA0_IO_GROUP_BURST__WR_LIMIT_HI__SHIFT 0x18 4170 #define MMEA0_IO_GROUP_BURST__RD_LIMIT_LO_MASK 0x000000FFL 4171 #define MMEA0_IO_GROUP_BURST__RD_LIMIT_HI_MASK 0x0000FF00L 4172 #define MMEA0_IO_GROUP_BURST__WR_LIMIT_LO_MASK 0x00FF0000L 4173 #define MMEA0_IO_GROUP_BURST__WR_LIMIT_HI_MASK 0xFF000000L 4174 //MMEA0_IO_RD_PRI_AGE 4175 #define MMEA0_IO_RD_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 4176 #define MMEA0_IO_RD_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 4177 #define MMEA0_IO_RD_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 4178 #define MMEA0_IO_RD_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 4179 #define MMEA0_IO_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc 4180 #define MMEA0_IO_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf 4181 #define MMEA0_IO_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 4182 #define MMEA0_IO_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 4183 #define MMEA0_IO_RD_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L 4184 #define MMEA0_IO_RD_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L 4185 #define MMEA0_IO_RD_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L 4186 #define MMEA0_IO_RD_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L 4187 #define MMEA0_IO_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L 4188 #define MMEA0_IO_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L 4189 #define MMEA0_IO_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L 4190 #define MMEA0_IO_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L 4191 //MMEA0_IO_WR_PRI_AGE 4192 #define MMEA0_IO_WR_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 4193 #define MMEA0_IO_WR_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 4194 #define MMEA0_IO_WR_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 4195 #define MMEA0_IO_WR_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 4196 #define MMEA0_IO_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc 4197 #define MMEA0_IO_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf 4198 #define MMEA0_IO_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 4199 #define MMEA0_IO_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 4200 #define MMEA0_IO_WR_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L 4201 #define MMEA0_IO_WR_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L 4202 #define MMEA0_IO_WR_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L 4203 #define MMEA0_IO_WR_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L 4204 #define MMEA0_IO_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L 4205 #define MMEA0_IO_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L 4206 #define MMEA0_IO_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L 4207 #define MMEA0_IO_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L 4208 //MMEA0_IO_RD_PRI_QUEUING 4209 #define MMEA0_IO_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 4210 #define MMEA0_IO_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 4211 #define MMEA0_IO_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 4212 #define MMEA0_IO_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 4213 #define MMEA0_IO_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L 4214 #define MMEA0_IO_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L 4215 #define MMEA0_IO_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L 4216 #define MMEA0_IO_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L 4217 //MMEA0_IO_WR_PRI_QUEUING 4218 #define MMEA0_IO_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 4219 #define MMEA0_IO_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 4220 #define MMEA0_IO_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 4221 #define MMEA0_IO_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 4222 #define MMEA0_IO_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L 4223 #define MMEA0_IO_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L 4224 #define MMEA0_IO_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L 4225 #define MMEA0_IO_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L 4226 //MMEA0_IO_RD_PRI_FIXED 4227 #define MMEA0_IO_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 4228 #define MMEA0_IO_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 4229 #define MMEA0_IO_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 4230 #define MMEA0_IO_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 4231 #define MMEA0_IO_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L 4232 #define MMEA0_IO_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L 4233 #define MMEA0_IO_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L 4234 #define MMEA0_IO_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L 4235 //MMEA0_IO_WR_PRI_FIXED 4236 #define MMEA0_IO_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 4237 #define MMEA0_IO_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 4238 #define MMEA0_IO_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 4239 #define MMEA0_IO_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 4240 #define MMEA0_IO_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L 4241 #define MMEA0_IO_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L 4242 #define MMEA0_IO_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L 4243 #define MMEA0_IO_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L 4244 //MMEA0_IO_RD_PRI_URGENCY 4245 #define MMEA0_IO_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 4246 #define MMEA0_IO_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 4247 #define MMEA0_IO_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 4248 #define MMEA0_IO_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 4249 #define MMEA0_IO_RD_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc 4250 #define MMEA0_IO_RD_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd 4251 #define MMEA0_IO_RD_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe 4252 #define MMEA0_IO_RD_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf 4253 #define MMEA0_IO_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L 4254 #define MMEA0_IO_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L 4255 #define MMEA0_IO_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L 4256 #define MMEA0_IO_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L 4257 #define MMEA0_IO_RD_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L 4258 #define MMEA0_IO_RD_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L 4259 #define MMEA0_IO_RD_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L 4260 #define MMEA0_IO_RD_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L 4261 //MMEA0_IO_WR_PRI_URGENCY 4262 #define MMEA0_IO_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 4263 #define MMEA0_IO_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 4264 #define MMEA0_IO_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 4265 #define MMEA0_IO_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 4266 #define MMEA0_IO_WR_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc 4267 #define MMEA0_IO_WR_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd 4268 #define MMEA0_IO_WR_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe 4269 #define MMEA0_IO_WR_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf 4270 #define MMEA0_IO_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L 4271 #define MMEA0_IO_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L 4272 #define MMEA0_IO_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L 4273 #define MMEA0_IO_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L 4274 #define MMEA0_IO_WR_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L 4275 #define MMEA0_IO_WR_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L 4276 #define MMEA0_IO_WR_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L 4277 #define MMEA0_IO_WR_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L 4278 //MMEA0_IO_RD_PRI_URGENCY_MASKING 4279 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID0_MASK__SHIFT 0x0 4280 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID1_MASK__SHIFT 0x1 4281 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID2_MASK__SHIFT 0x2 4282 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID3_MASK__SHIFT 0x3 4283 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID4_MASK__SHIFT 0x4 4284 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID5_MASK__SHIFT 0x5 4285 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID6_MASK__SHIFT 0x6 4286 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID7_MASK__SHIFT 0x7 4287 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID8_MASK__SHIFT 0x8 4288 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID9_MASK__SHIFT 0x9 4289 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID10_MASK__SHIFT 0xa 4290 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID11_MASK__SHIFT 0xb 4291 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID12_MASK__SHIFT 0xc 4292 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID13_MASK__SHIFT 0xd 4293 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID14_MASK__SHIFT 0xe 4294 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID15_MASK__SHIFT 0xf 4295 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID16_MASK__SHIFT 0x10 4296 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID17_MASK__SHIFT 0x11 4297 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID18_MASK__SHIFT 0x12 4298 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID19_MASK__SHIFT 0x13 4299 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID20_MASK__SHIFT 0x14 4300 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID21_MASK__SHIFT 0x15 4301 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID22_MASK__SHIFT 0x16 4302 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID23_MASK__SHIFT 0x17 4303 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID24_MASK__SHIFT 0x18 4304 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID25_MASK__SHIFT 0x19 4305 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID26_MASK__SHIFT 0x1a 4306 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID27_MASK__SHIFT 0x1b 4307 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID28_MASK__SHIFT 0x1c 4308 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID29_MASK__SHIFT 0x1d 4309 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID30_MASK__SHIFT 0x1e 4310 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID31_MASK__SHIFT 0x1f 4311 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID0_MASK_MASK 0x00000001L 4312 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID1_MASK_MASK 0x00000002L 4313 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID2_MASK_MASK 0x00000004L 4314 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID3_MASK_MASK 0x00000008L 4315 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID4_MASK_MASK 0x00000010L 4316 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID5_MASK_MASK 0x00000020L 4317 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID6_MASK_MASK 0x00000040L 4318 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID7_MASK_MASK 0x00000080L 4319 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID8_MASK_MASK 0x00000100L 4320 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID9_MASK_MASK 0x00000200L 4321 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID10_MASK_MASK 0x00000400L 4322 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID11_MASK_MASK 0x00000800L 4323 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID12_MASK_MASK 0x00001000L 4324 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID13_MASK_MASK 0x00002000L 4325 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID14_MASK_MASK 0x00004000L 4326 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID15_MASK_MASK 0x00008000L 4327 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID16_MASK_MASK 0x00010000L 4328 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID17_MASK_MASK 0x00020000L 4329 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID18_MASK_MASK 0x00040000L 4330 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID19_MASK_MASK 0x00080000L 4331 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID20_MASK_MASK 0x00100000L 4332 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID21_MASK_MASK 0x00200000L 4333 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID22_MASK_MASK 0x00400000L 4334 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID23_MASK_MASK 0x00800000L 4335 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID24_MASK_MASK 0x01000000L 4336 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID25_MASK_MASK 0x02000000L 4337 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID26_MASK_MASK 0x04000000L 4338 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID27_MASK_MASK 0x08000000L 4339 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID28_MASK_MASK 0x10000000L 4340 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID29_MASK_MASK 0x20000000L 4341 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID30_MASK_MASK 0x40000000L 4342 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID31_MASK_MASK 0x80000000L 4343 //MMEA0_IO_WR_PRI_URGENCY_MASKING 4344 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID0_MASK__SHIFT 0x0 4345 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID1_MASK__SHIFT 0x1 4346 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID2_MASK__SHIFT 0x2 4347 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID3_MASK__SHIFT 0x3 4348 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID4_MASK__SHIFT 0x4 4349 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID5_MASK__SHIFT 0x5 4350 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID6_MASK__SHIFT 0x6 4351 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID7_MASK__SHIFT 0x7 4352 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID8_MASK__SHIFT 0x8 4353 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID9_MASK__SHIFT 0x9 4354 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID10_MASK__SHIFT 0xa 4355 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID11_MASK__SHIFT 0xb 4356 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID12_MASK__SHIFT 0xc 4357 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID13_MASK__SHIFT 0xd 4358 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID14_MASK__SHIFT 0xe 4359 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID15_MASK__SHIFT 0xf 4360 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID16_MASK__SHIFT 0x10 4361 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID17_MASK__SHIFT 0x11 4362 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID18_MASK__SHIFT 0x12 4363 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID19_MASK__SHIFT 0x13 4364 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID20_MASK__SHIFT 0x14 4365 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID21_MASK__SHIFT 0x15 4366 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID22_MASK__SHIFT 0x16 4367 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID23_MASK__SHIFT 0x17 4368 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID24_MASK__SHIFT 0x18 4369 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID25_MASK__SHIFT 0x19 4370 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID26_MASK__SHIFT 0x1a 4371 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID27_MASK__SHIFT 0x1b 4372 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID28_MASK__SHIFT 0x1c 4373 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID29_MASK__SHIFT 0x1d 4374 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID30_MASK__SHIFT 0x1e 4375 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID31_MASK__SHIFT 0x1f 4376 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID0_MASK_MASK 0x00000001L 4377 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID1_MASK_MASK 0x00000002L 4378 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID2_MASK_MASK 0x00000004L 4379 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID3_MASK_MASK 0x00000008L 4380 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID4_MASK_MASK 0x00000010L 4381 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID5_MASK_MASK 0x00000020L 4382 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID6_MASK_MASK 0x00000040L 4383 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID7_MASK_MASK 0x00000080L 4384 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID8_MASK_MASK 0x00000100L 4385 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID9_MASK_MASK 0x00000200L 4386 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID10_MASK_MASK 0x00000400L 4387 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID11_MASK_MASK 0x00000800L 4388 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID12_MASK_MASK 0x00001000L 4389 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID13_MASK_MASK 0x00002000L 4390 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID14_MASK_MASK 0x00004000L 4391 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID15_MASK_MASK 0x00008000L 4392 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID16_MASK_MASK 0x00010000L 4393 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID17_MASK_MASK 0x00020000L 4394 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID18_MASK_MASK 0x00040000L 4395 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID19_MASK_MASK 0x00080000L 4396 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID20_MASK_MASK 0x00100000L 4397 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID21_MASK_MASK 0x00200000L 4398 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID22_MASK_MASK 0x00400000L 4399 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID23_MASK_MASK 0x00800000L 4400 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID24_MASK_MASK 0x01000000L 4401 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID25_MASK_MASK 0x02000000L 4402 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID26_MASK_MASK 0x04000000L 4403 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID27_MASK_MASK 0x08000000L 4404 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID28_MASK_MASK 0x10000000L 4405 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID29_MASK_MASK 0x20000000L 4406 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID30_MASK_MASK 0x40000000L 4407 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID31_MASK_MASK 0x80000000L 4408 //MMEA0_IO_RD_PRI_QUANT_PRI1 4409 #define MMEA0_IO_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 4410 #define MMEA0_IO_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 4411 #define MMEA0_IO_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 4412 #define MMEA0_IO_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 4413 #define MMEA0_IO_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL 4414 #define MMEA0_IO_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L 4415 #define MMEA0_IO_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L 4416 #define MMEA0_IO_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L 4417 //MMEA0_IO_RD_PRI_QUANT_PRI2 4418 #define MMEA0_IO_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 4419 #define MMEA0_IO_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 4420 #define MMEA0_IO_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 4421 #define MMEA0_IO_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 4422 #define MMEA0_IO_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL 4423 #define MMEA0_IO_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L 4424 #define MMEA0_IO_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L 4425 #define MMEA0_IO_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L 4426 //MMEA0_IO_RD_PRI_QUANT_PRI3 4427 #define MMEA0_IO_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 4428 #define MMEA0_IO_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 4429 #define MMEA0_IO_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 4430 #define MMEA0_IO_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 4431 #define MMEA0_IO_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL 4432 #define MMEA0_IO_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L 4433 #define MMEA0_IO_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L 4434 #define MMEA0_IO_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L 4435 //MMEA0_IO_WR_PRI_QUANT_PRI1 4436 #define MMEA0_IO_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 4437 #define MMEA0_IO_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 4438 #define MMEA0_IO_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 4439 #define MMEA0_IO_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 4440 #define MMEA0_IO_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL 4441 #define MMEA0_IO_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L 4442 #define MMEA0_IO_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L 4443 #define MMEA0_IO_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L 4444 //MMEA0_IO_WR_PRI_QUANT_PRI2 4445 #define MMEA0_IO_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 4446 #define MMEA0_IO_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 4447 #define MMEA0_IO_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 4448 #define MMEA0_IO_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 4449 #define MMEA0_IO_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL 4450 #define MMEA0_IO_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L 4451 #define MMEA0_IO_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L 4452 #define MMEA0_IO_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L 4453 //MMEA0_IO_WR_PRI_QUANT_PRI3 4454 #define MMEA0_IO_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 4455 #define MMEA0_IO_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 4456 #define MMEA0_IO_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 4457 #define MMEA0_IO_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 4458 #define MMEA0_IO_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL 4459 #define MMEA0_IO_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L 4460 #define MMEA0_IO_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L 4461 #define MMEA0_IO_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L 4462 //MMEA0_SDP_ARB_DRAM 4463 #define MMEA0_SDP_ARB_DRAM__RDWR_BURST_LIMIT_CYCL__SHIFT 0x0 4464 #define MMEA0_SDP_ARB_DRAM__RDWR_BURST_LIMIT_DATA__SHIFT 0x8 4465 #define MMEA0_SDP_ARB_DRAM__EARLY_SW2RD_ON_PRI__SHIFT 0x10 4466 #define MMEA0_SDP_ARB_DRAM__EARLY_SW2WR_ON_PRI__SHIFT 0x11 4467 #define MMEA0_SDP_ARB_DRAM__EARLY_SW2RD_ON_RES__SHIFT 0x12 4468 #define MMEA0_SDP_ARB_DRAM__EARLY_SW2WR_ON_RES__SHIFT 0x13 4469 #define MMEA0_SDP_ARB_DRAM__EOB_ON_EXPIRE__SHIFT 0x14 4470 #define MMEA0_SDP_ARB_DRAM__DECOUPLE_RDWR_BNKSTATE__SHIFT 0x15 4471 #define MMEA0_SDP_ARB_DRAM__RDWR_BURST_LIMIT_CYCL_MASK 0x0000007FL 4472 #define MMEA0_SDP_ARB_DRAM__RDWR_BURST_LIMIT_DATA_MASK 0x00007F00L 4473 #define MMEA0_SDP_ARB_DRAM__EARLY_SW2RD_ON_PRI_MASK 0x00010000L 4474 #define MMEA0_SDP_ARB_DRAM__EARLY_SW2WR_ON_PRI_MASK 0x00020000L 4475 #define MMEA0_SDP_ARB_DRAM__EARLY_SW2RD_ON_RES_MASK 0x00040000L 4476 #define MMEA0_SDP_ARB_DRAM__EARLY_SW2WR_ON_RES_MASK 0x00080000L 4477 #define MMEA0_SDP_ARB_DRAM__EOB_ON_EXPIRE_MASK 0x00100000L 4478 #define MMEA0_SDP_ARB_DRAM__DECOUPLE_RDWR_BNKSTATE_MASK 0x00200000L 4479 //MMEA0_SDP_ARB_FINAL 4480 #define MMEA0_SDP_ARB_FINAL__DRAM_BURST_LIMIT__SHIFT 0x0 4481 #define MMEA0_SDP_ARB_FINAL__GMI_BURST_LIMIT__SHIFT 0x5 4482 #define MMEA0_SDP_ARB_FINAL__IO_BURST_LIMIT__SHIFT 0xa 4483 #define MMEA0_SDP_ARB_FINAL__BURST_LIMIT_MULTIPLIER__SHIFT 0xf 4484 #define MMEA0_SDP_ARB_FINAL__RDONLY_VC0__SHIFT 0x11 4485 #define MMEA0_SDP_ARB_FINAL__RDONLY_VC1__SHIFT 0x12 4486 #define MMEA0_SDP_ARB_FINAL__RDONLY_VC2__SHIFT 0x13 4487 #define MMEA0_SDP_ARB_FINAL__RDONLY_VC3__SHIFT 0x14 4488 #define MMEA0_SDP_ARB_FINAL__RDONLY_VC4__SHIFT 0x15 4489 #define MMEA0_SDP_ARB_FINAL__RDONLY_VC5__SHIFT 0x16 4490 #define MMEA0_SDP_ARB_FINAL__RDONLY_VC6__SHIFT 0x17 4491 #define MMEA0_SDP_ARB_FINAL__RDONLY_VC7__SHIFT 0x18 4492 #define MMEA0_SDP_ARB_FINAL__ERREVENT_ON_ERROR__SHIFT 0x19 4493 #define MMEA0_SDP_ARB_FINAL__HALTREQ_ON_ERROR__SHIFT 0x1a 4494 #define MMEA0_SDP_ARB_FINAL__GMI_BURST_STRETCH__SHIFT 0x1b 4495 #define MMEA0_SDP_ARB_FINAL__DRAM_RD_THROTTLE__SHIFT 0x1c 4496 #define MMEA0_SDP_ARB_FINAL__DRAM_WR_THROTTLE__SHIFT 0x1d 4497 #define MMEA0_SDP_ARB_FINAL__GMI_RD_THROTTLE__SHIFT 0x1e 4498 #define MMEA0_SDP_ARB_FINAL__GMI_WR_THROTTLE__SHIFT 0x1f 4499 #define MMEA0_SDP_ARB_FINAL__DRAM_BURST_LIMIT_MASK 0x0000001FL 4500 #define MMEA0_SDP_ARB_FINAL__GMI_BURST_LIMIT_MASK 0x000003E0L 4501 #define MMEA0_SDP_ARB_FINAL__IO_BURST_LIMIT_MASK 0x00007C00L 4502 #define MMEA0_SDP_ARB_FINAL__BURST_LIMIT_MULTIPLIER_MASK 0x00018000L 4503 #define MMEA0_SDP_ARB_FINAL__RDONLY_VC0_MASK 0x00020000L 4504 #define MMEA0_SDP_ARB_FINAL__RDONLY_VC1_MASK 0x00040000L 4505 #define MMEA0_SDP_ARB_FINAL__RDONLY_VC2_MASK 0x00080000L 4506 #define MMEA0_SDP_ARB_FINAL__RDONLY_VC3_MASK 0x00100000L 4507 #define MMEA0_SDP_ARB_FINAL__RDONLY_VC4_MASK 0x00200000L 4508 #define MMEA0_SDP_ARB_FINAL__RDONLY_VC5_MASK 0x00400000L 4509 #define MMEA0_SDP_ARB_FINAL__RDONLY_VC6_MASK 0x00800000L 4510 #define MMEA0_SDP_ARB_FINAL__RDONLY_VC7_MASK 0x01000000L 4511 #define MMEA0_SDP_ARB_FINAL__ERREVENT_ON_ERROR_MASK 0x02000000L 4512 #define MMEA0_SDP_ARB_FINAL__HALTREQ_ON_ERROR_MASK 0x04000000L 4513 #define MMEA0_SDP_ARB_FINAL__GMI_BURST_STRETCH_MASK 0x08000000L 4514 #define MMEA0_SDP_ARB_FINAL__DRAM_RD_THROTTLE_MASK 0x10000000L 4515 #define MMEA0_SDP_ARB_FINAL__DRAM_WR_THROTTLE_MASK 0x20000000L 4516 #define MMEA0_SDP_ARB_FINAL__GMI_RD_THROTTLE_MASK 0x40000000L 4517 #define MMEA0_SDP_ARB_FINAL__GMI_WR_THROTTLE_MASK 0x80000000L 4518 //MMEA0_SDP_DRAM_PRIORITY 4519 #define MMEA0_SDP_DRAM_PRIORITY__RD_GROUP0_PRIORITY__SHIFT 0x0 4520 #define MMEA0_SDP_DRAM_PRIORITY__RD_GROUP1_PRIORITY__SHIFT 0x4 4521 #define MMEA0_SDP_DRAM_PRIORITY__RD_GROUP2_PRIORITY__SHIFT 0x8 4522 #define MMEA0_SDP_DRAM_PRIORITY__RD_GROUP3_PRIORITY__SHIFT 0xc 4523 #define MMEA0_SDP_DRAM_PRIORITY__WR_GROUP0_PRIORITY__SHIFT 0x10 4524 #define MMEA0_SDP_DRAM_PRIORITY__WR_GROUP1_PRIORITY__SHIFT 0x14 4525 #define MMEA0_SDP_DRAM_PRIORITY__WR_GROUP2_PRIORITY__SHIFT 0x18 4526 #define MMEA0_SDP_DRAM_PRIORITY__WR_GROUP3_PRIORITY__SHIFT 0x1c 4527 #define MMEA0_SDP_DRAM_PRIORITY__RD_GROUP0_PRIORITY_MASK 0x0000000FL 4528 #define MMEA0_SDP_DRAM_PRIORITY__RD_GROUP1_PRIORITY_MASK 0x000000F0L 4529 #define MMEA0_SDP_DRAM_PRIORITY__RD_GROUP2_PRIORITY_MASK 0x00000F00L 4530 #define MMEA0_SDP_DRAM_PRIORITY__RD_GROUP3_PRIORITY_MASK 0x0000F000L 4531 #define MMEA0_SDP_DRAM_PRIORITY__WR_GROUP0_PRIORITY_MASK 0x000F0000L 4532 #define MMEA0_SDP_DRAM_PRIORITY__WR_GROUP1_PRIORITY_MASK 0x00F00000L 4533 #define MMEA0_SDP_DRAM_PRIORITY__WR_GROUP2_PRIORITY_MASK 0x0F000000L 4534 #define MMEA0_SDP_DRAM_PRIORITY__WR_GROUP3_PRIORITY_MASK 0xF0000000L 4535 //MMEA0_SDP_IO_PRIORITY 4536 #define MMEA0_SDP_IO_PRIORITY__RD_GROUP0_PRIORITY__SHIFT 0x0 4537 #define MMEA0_SDP_IO_PRIORITY__RD_GROUP1_PRIORITY__SHIFT 0x4 4538 #define MMEA0_SDP_IO_PRIORITY__RD_GROUP2_PRIORITY__SHIFT 0x8 4539 #define MMEA0_SDP_IO_PRIORITY__RD_GROUP3_PRIORITY__SHIFT 0xc 4540 #define MMEA0_SDP_IO_PRIORITY__WR_GROUP0_PRIORITY__SHIFT 0x10 4541 #define MMEA0_SDP_IO_PRIORITY__WR_GROUP1_PRIORITY__SHIFT 0x14 4542 #define MMEA0_SDP_IO_PRIORITY__WR_GROUP2_PRIORITY__SHIFT 0x18 4543 #define MMEA0_SDP_IO_PRIORITY__WR_GROUP3_PRIORITY__SHIFT 0x1c 4544 #define MMEA0_SDP_IO_PRIORITY__RD_GROUP0_PRIORITY_MASK 0x0000000FL 4545 #define MMEA0_SDP_IO_PRIORITY__RD_GROUP1_PRIORITY_MASK 0x000000F0L 4546 #define MMEA0_SDP_IO_PRIORITY__RD_GROUP2_PRIORITY_MASK 0x00000F00L 4547 #define MMEA0_SDP_IO_PRIORITY__RD_GROUP3_PRIORITY_MASK 0x0000F000L 4548 #define MMEA0_SDP_IO_PRIORITY__WR_GROUP0_PRIORITY_MASK 0x000F0000L 4549 #define MMEA0_SDP_IO_PRIORITY__WR_GROUP1_PRIORITY_MASK 0x00F00000L 4550 #define MMEA0_SDP_IO_PRIORITY__WR_GROUP2_PRIORITY_MASK 0x0F000000L 4551 #define MMEA0_SDP_IO_PRIORITY__WR_GROUP3_PRIORITY_MASK 0xF0000000L 4552 //MMEA0_SDP_CREDITS 4553 #define MMEA0_SDP_CREDITS__TAG_LIMIT__SHIFT 0x0 4554 #define MMEA0_SDP_CREDITS__WR_RESP_CREDITS__SHIFT 0x8 4555 #define MMEA0_SDP_CREDITS__RD_RESP_CREDITS__SHIFT 0x10 4556 #define MMEA0_SDP_CREDITS__TAG_LIMIT_MASK 0x000000FFL 4557 #define MMEA0_SDP_CREDITS__WR_RESP_CREDITS_MASK 0x00007F00L 4558 #define MMEA0_SDP_CREDITS__RD_RESP_CREDITS_MASK 0x007F0000L 4559 //MMEA0_SDP_TAG_RESERVE0 4560 #define MMEA0_SDP_TAG_RESERVE0__VC0__SHIFT 0x0 4561 #define MMEA0_SDP_TAG_RESERVE0__VC1__SHIFT 0x8 4562 #define MMEA0_SDP_TAG_RESERVE0__VC2__SHIFT 0x10 4563 #define MMEA0_SDP_TAG_RESERVE0__VC3__SHIFT 0x18 4564 #define MMEA0_SDP_TAG_RESERVE0__VC0_MASK 0x000000FFL 4565 #define MMEA0_SDP_TAG_RESERVE0__VC1_MASK 0x0000FF00L 4566 #define MMEA0_SDP_TAG_RESERVE0__VC2_MASK 0x00FF0000L 4567 #define MMEA0_SDP_TAG_RESERVE0__VC3_MASK 0xFF000000L 4568 //MMEA0_SDP_TAG_RESERVE1 4569 #define MMEA0_SDP_TAG_RESERVE1__VC4__SHIFT 0x0 4570 #define MMEA0_SDP_TAG_RESERVE1__VC5__SHIFT 0x8 4571 #define MMEA0_SDP_TAG_RESERVE1__VC6__SHIFT 0x10 4572 #define MMEA0_SDP_TAG_RESERVE1__VC7__SHIFT 0x18 4573 #define MMEA0_SDP_TAG_RESERVE1__VC4_MASK 0x000000FFL 4574 #define MMEA0_SDP_TAG_RESERVE1__VC5_MASK 0x0000FF00L 4575 #define MMEA0_SDP_TAG_RESERVE1__VC6_MASK 0x00FF0000L 4576 #define MMEA0_SDP_TAG_RESERVE1__VC7_MASK 0xFF000000L 4577 //MMEA0_SDP_VCC_RESERVE0 4578 #define MMEA0_SDP_VCC_RESERVE0__VC0_CREDITS__SHIFT 0x0 4579 #define MMEA0_SDP_VCC_RESERVE0__VC1_CREDITS__SHIFT 0x6 4580 #define MMEA0_SDP_VCC_RESERVE0__VC2_CREDITS__SHIFT 0xc 4581 #define MMEA0_SDP_VCC_RESERVE0__VC3_CREDITS__SHIFT 0x12 4582 #define MMEA0_SDP_VCC_RESERVE0__VC4_CREDITS__SHIFT 0x18 4583 #define MMEA0_SDP_VCC_RESERVE0__VC0_CREDITS_MASK 0x0000003FL 4584 #define MMEA0_SDP_VCC_RESERVE0__VC1_CREDITS_MASK 0x00000FC0L 4585 #define MMEA0_SDP_VCC_RESERVE0__VC2_CREDITS_MASK 0x0003F000L 4586 #define MMEA0_SDP_VCC_RESERVE0__VC3_CREDITS_MASK 0x00FC0000L 4587 #define MMEA0_SDP_VCC_RESERVE0__VC4_CREDITS_MASK 0x3F000000L 4588 //MMEA0_SDP_VCC_RESERVE1 4589 #define MMEA0_SDP_VCC_RESERVE1__VC5_CREDITS__SHIFT 0x0 4590 #define MMEA0_SDP_VCC_RESERVE1__VC6_CREDITS__SHIFT 0x6 4591 #define MMEA0_SDP_VCC_RESERVE1__VC7_CREDITS__SHIFT 0xc 4592 #define MMEA0_SDP_VCC_RESERVE1__DISTRIBUTE_POOL__SHIFT 0x1f 4593 #define MMEA0_SDP_VCC_RESERVE1__VC5_CREDITS_MASK 0x0000003FL 4594 #define MMEA0_SDP_VCC_RESERVE1__VC6_CREDITS_MASK 0x00000FC0L 4595 #define MMEA0_SDP_VCC_RESERVE1__VC7_CREDITS_MASK 0x0003F000L 4596 #define MMEA0_SDP_VCC_RESERVE1__DISTRIBUTE_POOL_MASK 0x80000000L 4597 //MMEA0_SDP_VCD_RESERVE0 4598 #define MMEA0_SDP_VCD_RESERVE0__VC0_CREDITS__SHIFT 0x0 4599 #define MMEA0_SDP_VCD_RESERVE0__VC1_CREDITS__SHIFT 0x6 4600 #define MMEA0_SDP_VCD_RESERVE0__VC2_CREDITS__SHIFT 0xc 4601 #define MMEA0_SDP_VCD_RESERVE0__VC3_CREDITS__SHIFT 0x12 4602 #define MMEA0_SDP_VCD_RESERVE0__VC4_CREDITS__SHIFT 0x18 4603 #define MMEA0_SDP_VCD_RESERVE0__VC0_CREDITS_MASK 0x0000003FL 4604 #define MMEA0_SDP_VCD_RESERVE0__VC1_CREDITS_MASK 0x00000FC0L 4605 #define MMEA0_SDP_VCD_RESERVE0__VC2_CREDITS_MASK 0x0003F000L 4606 #define MMEA0_SDP_VCD_RESERVE0__VC3_CREDITS_MASK 0x00FC0000L 4607 #define MMEA0_SDP_VCD_RESERVE0__VC4_CREDITS_MASK 0x3F000000L 4608 //MMEA0_SDP_VCD_RESERVE1 4609 #define MMEA0_SDP_VCD_RESERVE1__VC5_CREDITS__SHIFT 0x0 4610 #define MMEA0_SDP_VCD_RESERVE1__VC6_CREDITS__SHIFT 0x6 4611 #define MMEA0_SDP_VCD_RESERVE1__VC7_CREDITS__SHIFT 0xc 4612 #define MMEA0_SDP_VCD_RESERVE1__DISTRIBUTE_POOL__SHIFT 0x1f 4613 #define MMEA0_SDP_VCD_RESERVE1__VC5_CREDITS_MASK 0x0000003FL 4614 #define MMEA0_SDP_VCD_RESERVE1__VC6_CREDITS_MASK 0x00000FC0L 4615 #define MMEA0_SDP_VCD_RESERVE1__VC7_CREDITS_MASK 0x0003F000L 4616 #define MMEA0_SDP_VCD_RESERVE1__DISTRIBUTE_POOL_MASK 0x80000000L 4617 //MMEA0_SDP_REQ_CNTL 4618 #define MMEA0_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_READ__SHIFT 0x0 4619 #define MMEA0_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_WRITE__SHIFT 0x1 4620 #define MMEA0_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_ATOMIC__SHIFT 0x2 4621 #define MMEA0_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_DRAM__SHIFT 0x3 4622 #define MMEA0_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_GMI__SHIFT 0x4 4623 #define MMEA0_SDP_REQ_CNTL__INNER_DOMAIN_MODE__SHIFT 0x5 4624 #define MMEA0_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_READ__SHIFT 0x6 4625 #define MMEA0_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_WRITE__SHIFT 0x8 4626 #define MMEA0_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_ATOMIC__SHIFT 0xa 4627 #define MMEA0_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_READ_MASK 0x00000001L 4628 #define MMEA0_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_WRITE_MASK 0x00000002L 4629 #define MMEA0_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_ATOMIC_MASK 0x00000004L 4630 #define MMEA0_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_DRAM_MASK 0x00000008L 4631 #define MMEA0_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_GMI_MASK 0x00000010L 4632 #define MMEA0_SDP_REQ_CNTL__INNER_DOMAIN_MODE_MASK 0x00000020L 4633 #define MMEA0_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_READ_MASK 0x000000C0L 4634 #define MMEA0_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_WRITE_MASK 0x00000300L 4635 #define MMEA0_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_ATOMIC_MASK 0x00000C00L 4636 //MMEA0_MISC 4637 #define MMEA0_MISC__RELATIVE_PRI_IN_DRAM_RD_ARB__SHIFT 0x0 4638 #define MMEA0_MISC__RELATIVE_PRI_IN_DRAM_WR_ARB__SHIFT 0x1 4639 #define MMEA0_MISC__RELATIVE_PRI_IN_GMI_RD_ARB__SHIFT 0x2 4640 #define MMEA0_MISC__RELATIVE_PRI_IN_GMI_WR_ARB__SHIFT 0x3 4641 #define MMEA0_MISC__RELATIVE_PRI_IN_IO_RD_ARB__SHIFT 0x4 4642 #define MMEA0_MISC__RELATIVE_PRI_IN_IO_WR_ARB__SHIFT 0x5 4643 #define MMEA0_MISC__EARLYWRRET_ENABLE_VC0__SHIFT 0x6 4644 #define MMEA0_MISC__EARLYWRRET_ENABLE_VC1__SHIFT 0x7 4645 #define MMEA0_MISC__EARLYWRRET_ENABLE_VC2__SHIFT 0x8 4646 #define MMEA0_MISC__EARLYWRRET_ENABLE_VC3__SHIFT 0x9 4647 #define MMEA0_MISC__EARLYWRRET_ENABLE_VC4__SHIFT 0xa 4648 #define MMEA0_MISC__EARLYWRRET_ENABLE_VC5__SHIFT 0xb 4649 #define MMEA0_MISC__EARLYWRRET_ENABLE_VC6__SHIFT 0xc 4650 #define MMEA0_MISC__EARLYWRRET_ENABLE_VC7__SHIFT 0xd 4651 #define MMEA0_MISC__EARLY_SDP_ORIGDATA__SHIFT 0xe 4652 #define MMEA0_MISC__LINKMGR_DYNAMIC_MODE__SHIFT 0xf 4653 #define MMEA0_MISC__LINKMGR_HALT_THRESHOLD__SHIFT 0x11 4654 #define MMEA0_MISC__LINKMGR_RECONNECT_DELAY__SHIFT 0x13 4655 #define MMEA0_MISC__LINKMGR_IDLE_THRESHOLD__SHIFT 0x15 4656 #define MMEA0_MISC__FAVOUR_MIDCHAIN_CS_IN_DRAM_ARB__SHIFT 0x1a 4657 #define MMEA0_MISC__FAVOUR_MIDCHAIN_CS_IN_GMI_ARB__SHIFT 0x1b 4658 #define MMEA0_MISC__FAVOUR_LAST_CS_IN_DRAM_ARB__SHIFT 0x1c 4659 #define MMEA0_MISC__FAVOUR_LAST_CS_IN_GMI_ARB__SHIFT 0x1d 4660 #define MMEA0_MISC__SWITCH_CS_ON_W2R_IN_DRAM_ARB__SHIFT 0x1e 4661 #define MMEA0_MISC__SWITCH_CS_ON_W2R_IN_GMI_ARB__SHIFT 0x1f 4662 #define MMEA0_MISC__RELATIVE_PRI_IN_DRAM_RD_ARB_MASK 0x00000001L 4663 #define MMEA0_MISC__RELATIVE_PRI_IN_DRAM_WR_ARB_MASK 0x00000002L 4664 #define MMEA0_MISC__RELATIVE_PRI_IN_GMI_RD_ARB_MASK 0x00000004L 4665 #define MMEA0_MISC__RELATIVE_PRI_IN_GMI_WR_ARB_MASK 0x00000008L 4666 #define MMEA0_MISC__RELATIVE_PRI_IN_IO_RD_ARB_MASK 0x00000010L 4667 #define MMEA0_MISC__RELATIVE_PRI_IN_IO_WR_ARB_MASK 0x00000020L 4668 #define MMEA0_MISC__EARLYWRRET_ENABLE_VC0_MASK 0x00000040L 4669 #define MMEA0_MISC__EARLYWRRET_ENABLE_VC1_MASK 0x00000080L 4670 #define MMEA0_MISC__EARLYWRRET_ENABLE_VC2_MASK 0x00000100L 4671 #define MMEA0_MISC__EARLYWRRET_ENABLE_VC3_MASK 0x00000200L 4672 #define MMEA0_MISC__EARLYWRRET_ENABLE_VC4_MASK 0x00000400L 4673 #define MMEA0_MISC__EARLYWRRET_ENABLE_VC5_MASK 0x00000800L 4674 #define MMEA0_MISC__EARLYWRRET_ENABLE_VC6_MASK 0x00001000L 4675 #define MMEA0_MISC__EARLYWRRET_ENABLE_VC7_MASK 0x00002000L 4676 #define MMEA0_MISC__EARLY_SDP_ORIGDATA_MASK 0x00004000L 4677 #define MMEA0_MISC__LINKMGR_DYNAMIC_MODE_MASK 0x00018000L 4678 #define MMEA0_MISC__LINKMGR_HALT_THRESHOLD_MASK 0x00060000L 4679 #define MMEA0_MISC__LINKMGR_RECONNECT_DELAY_MASK 0x00180000L 4680 #define MMEA0_MISC__LINKMGR_IDLE_THRESHOLD_MASK 0x03E00000L 4681 #define MMEA0_MISC__FAVOUR_MIDCHAIN_CS_IN_DRAM_ARB_MASK 0x04000000L 4682 #define MMEA0_MISC__FAVOUR_MIDCHAIN_CS_IN_GMI_ARB_MASK 0x08000000L 4683 #define MMEA0_MISC__FAVOUR_LAST_CS_IN_DRAM_ARB_MASK 0x10000000L 4684 #define MMEA0_MISC__FAVOUR_LAST_CS_IN_GMI_ARB_MASK 0x20000000L 4685 #define MMEA0_MISC__SWITCH_CS_ON_W2R_IN_DRAM_ARB_MASK 0x40000000L 4686 #define MMEA0_MISC__SWITCH_CS_ON_W2R_IN_GMI_ARB_MASK 0x80000000L 4687 //MMEA0_LATENCY_SAMPLING 4688 #define MMEA0_LATENCY_SAMPLING__SAMPLER0_DRAM__SHIFT 0x0 4689 #define MMEA0_LATENCY_SAMPLING__SAMPLER1_DRAM__SHIFT 0x1 4690 #define MMEA0_LATENCY_SAMPLING__SAMPLER0_GMI__SHIFT 0x2 4691 #define MMEA0_LATENCY_SAMPLING__SAMPLER1_GMI__SHIFT 0x3 4692 #define MMEA0_LATENCY_SAMPLING__SAMPLER0_IO__SHIFT 0x4 4693 #define MMEA0_LATENCY_SAMPLING__SAMPLER1_IO__SHIFT 0x5 4694 #define MMEA0_LATENCY_SAMPLING__SAMPLER0_READ__SHIFT 0x6 4695 #define MMEA0_LATENCY_SAMPLING__SAMPLER1_READ__SHIFT 0x7 4696 #define MMEA0_LATENCY_SAMPLING__SAMPLER0_WRITE__SHIFT 0x8 4697 #define MMEA0_LATENCY_SAMPLING__SAMPLER1_WRITE__SHIFT 0x9 4698 #define MMEA0_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET__SHIFT 0xa 4699 #define MMEA0_LATENCY_SAMPLING__SAMPLER1_ATOMIC_RET__SHIFT 0xb 4700 #define MMEA0_LATENCY_SAMPLING__SAMPLER0_ATOMIC_NORET__SHIFT 0xc 4701 #define MMEA0_LATENCY_SAMPLING__SAMPLER1_ATOMIC_NORET__SHIFT 0xd 4702 #define MMEA0_LATENCY_SAMPLING__SAMPLER0_VC__SHIFT 0xe 4703 #define MMEA0_LATENCY_SAMPLING__SAMPLER1_VC__SHIFT 0x16 4704 #define MMEA0_LATENCY_SAMPLING__SAMPLER0_DRAM_MASK 0x00000001L 4705 #define MMEA0_LATENCY_SAMPLING__SAMPLER1_DRAM_MASK 0x00000002L 4706 #define MMEA0_LATENCY_SAMPLING__SAMPLER0_GMI_MASK 0x00000004L 4707 #define MMEA0_LATENCY_SAMPLING__SAMPLER1_GMI_MASK 0x00000008L 4708 #define MMEA0_LATENCY_SAMPLING__SAMPLER0_IO_MASK 0x00000010L 4709 #define MMEA0_LATENCY_SAMPLING__SAMPLER1_IO_MASK 0x00000020L 4710 #define MMEA0_LATENCY_SAMPLING__SAMPLER0_READ_MASK 0x00000040L 4711 #define MMEA0_LATENCY_SAMPLING__SAMPLER1_READ_MASK 0x00000080L 4712 #define MMEA0_LATENCY_SAMPLING__SAMPLER0_WRITE_MASK 0x00000100L 4713 #define MMEA0_LATENCY_SAMPLING__SAMPLER1_WRITE_MASK 0x00000200L 4714 #define MMEA0_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET_MASK 0x00000400L 4715 #define MMEA0_LATENCY_SAMPLING__SAMPLER1_ATOMIC_RET_MASK 0x00000800L 4716 #define MMEA0_LATENCY_SAMPLING__SAMPLER0_ATOMIC_NORET_MASK 0x00001000L 4717 #define MMEA0_LATENCY_SAMPLING__SAMPLER1_ATOMIC_NORET_MASK 0x00002000L 4718 #define MMEA0_LATENCY_SAMPLING__SAMPLER0_VC_MASK 0x003FC000L 4719 #define MMEA0_LATENCY_SAMPLING__SAMPLER1_VC_MASK 0x3FC00000L 4720 //MMEA0_PERFCOUNTER_LO 4721 #define MMEA0_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 4722 #define MMEA0_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL 4723 //MMEA0_PERFCOUNTER_HI 4724 #define MMEA0_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 4725 #define MMEA0_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 4726 #define MMEA0_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL 4727 #define MMEA0_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L 4728 //MMEA0_PERFCOUNTER0_CFG 4729 #define MMEA0_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 4730 #define MMEA0_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 4731 #define MMEA0_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 4732 #define MMEA0_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c 4733 #define MMEA0_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d 4734 #define MMEA0_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL 4735 #define MMEA0_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L 4736 #define MMEA0_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L 4737 #define MMEA0_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L 4738 #define MMEA0_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L 4739 //MMEA0_PERFCOUNTER1_CFG 4740 #define MMEA0_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 4741 #define MMEA0_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 4742 #define MMEA0_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 4743 #define MMEA0_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c 4744 #define MMEA0_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d 4745 #define MMEA0_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL 4746 #define MMEA0_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L 4747 #define MMEA0_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L 4748 #define MMEA0_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L 4749 #define MMEA0_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L 4750 //MMEA0_PERFCOUNTER_RSLT_CNTL 4751 #define MMEA0_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 4752 #define MMEA0_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 4753 #define MMEA0_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 4754 #define MMEA0_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 4755 #define MMEA0_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 4756 #define MMEA0_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a 4757 #define MMEA0_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL 4758 #define MMEA0_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L 4759 #define MMEA0_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L 4760 #define MMEA0_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L 4761 #define MMEA0_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L 4762 #define MMEA0_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L 4763 //MMEA0_EDC_CNT 4764 #define MMEA0_EDC_CNT__DRAMRD_CMDMEM_SEC_COUNT__SHIFT 0x0 4765 #define MMEA0_EDC_CNT__DRAMRD_CMDMEM_DED_COUNT__SHIFT 0x2 4766 #define MMEA0_EDC_CNT__DRAMWR_CMDMEM_SEC_COUNT__SHIFT 0x4 4767 #define MMEA0_EDC_CNT__DRAMWR_CMDMEM_DED_COUNT__SHIFT 0x6 4768 #define MMEA0_EDC_CNT__DRAMWR_DATAMEM_SEC_COUNT__SHIFT 0x8 4769 #define MMEA0_EDC_CNT__DRAMWR_DATAMEM_DED_COUNT__SHIFT 0xa 4770 #define MMEA0_EDC_CNT__RRET_TAGMEM_SEC_COUNT__SHIFT 0xc 4771 #define MMEA0_EDC_CNT__RRET_TAGMEM_DED_COUNT__SHIFT 0xe 4772 #define MMEA0_EDC_CNT__WRET_TAGMEM_SEC_COUNT__SHIFT 0x10 4773 #define MMEA0_EDC_CNT__WRET_TAGMEM_DED_COUNT__SHIFT 0x12 4774 #define MMEA0_EDC_CNT__IOWR_DATAMEM_SEC_COUNT__SHIFT 0x14 4775 #define MMEA0_EDC_CNT__IOWR_DATAMEM_DED_COUNT__SHIFT 0x16 4776 #define MMEA0_EDC_CNT__DRAMRD_PAGEMEM_SED_COUNT__SHIFT 0x18 4777 #define MMEA0_EDC_CNT__DRAMWR_PAGEMEM_SED_COUNT__SHIFT 0x1a 4778 #define MMEA0_EDC_CNT__IORD_CMDMEM_SED_COUNT__SHIFT 0x1c 4779 #define MMEA0_EDC_CNT__IOWR_CMDMEM_SED_COUNT__SHIFT 0x1e 4780 #define MMEA0_EDC_CNT__DRAMRD_CMDMEM_SEC_COUNT_MASK 0x00000003L 4781 #define MMEA0_EDC_CNT__DRAMRD_CMDMEM_DED_COUNT_MASK 0x0000000CL 4782 #define MMEA0_EDC_CNT__DRAMWR_CMDMEM_SEC_COUNT_MASK 0x00000030L 4783 #define MMEA0_EDC_CNT__DRAMWR_CMDMEM_DED_COUNT_MASK 0x000000C0L 4784 #define MMEA0_EDC_CNT__DRAMWR_DATAMEM_SEC_COUNT_MASK 0x00000300L 4785 #define MMEA0_EDC_CNT__DRAMWR_DATAMEM_DED_COUNT_MASK 0x00000C00L 4786 #define MMEA0_EDC_CNT__RRET_TAGMEM_SEC_COUNT_MASK 0x00003000L 4787 #define MMEA0_EDC_CNT__RRET_TAGMEM_DED_COUNT_MASK 0x0000C000L 4788 #define MMEA0_EDC_CNT__WRET_TAGMEM_SEC_COUNT_MASK 0x00030000L 4789 #define MMEA0_EDC_CNT__WRET_TAGMEM_DED_COUNT_MASK 0x000C0000L 4790 #define MMEA0_EDC_CNT__IOWR_DATAMEM_SEC_COUNT_MASK 0x00300000L 4791 #define MMEA0_EDC_CNT__IOWR_DATAMEM_DED_COUNT_MASK 0x00C00000L 4792 #define MMEA0_EDC_CNT__DRAMRD_PAGEMEM_SED_COUNT_MASK 0x03000000L 4793 #define MMEA0_EDC_CNT__DRAMWR_PAGEMEM_SED_COUNT_MASK 0x0C000000L 4794 #define MMEA0_EDC_CNT__IORD_CMDMEM_SED_COUNT_MASK 0x30000000L 4795 #define MMEA0_EDC_CNT__IOWR_CMDMEM_SED_COUNT_MASK 0xC0000000L 4796 //MMEA0_EDC_CNT2 4797 #define MMEA0_EDC_CNT2__GMIRD_CMDMEM_SEC_COUNT__SHIFT 0x0 4798 #define MMEA0_EDC_CNT2__GMIRD_CMDMEM_DED_COUNT__SHIFT 0x2 4799 #define MMEA0_EDC_CNT2__GMIWR_CMDMEM_SEC_COUNT__SHIFT 0x4 4800 #define MMEA0_EDC_CNT2__GMIWR_CMDMEM_DED_COUNT__SHIFT 0x6 4801 #define MMEA0_EDC_CNT2__GMIWR_DATAMEM_SEC_COUNT__SHIFT 0x8 4802 #define MMEA0_EDC_CNT2__GMIWR_DATAMEM_DED_COUNT__SHIFT 0xa 4803 #define MMEA0_EDC_CNT2__GMIRD_PAGEMEM_SED_COUNT__SHIFT 0xc 4804 #define MMEA0_EDC_CNT2__GMIWR_PAGEMEM_SED_COUNT__SHIFT 0xe 4805 #define MMEA0_EDC_CNT2__MAM_D0MEM_SED_COUNT__SHIFT 0x10 4806 #define MMEA0_EDC_CNT2__MAM_D1MEM_SED_COUNT__SHIFT 0x12 4807 #define MMEA0_EDC_CNT2__MAM_D2MEM_SED_COUNT__SHIFT 0x14 4808 #define MMEA0_EDC_CNT2__MAM_D3MEM_SED_COUNT__SHIFT 0x16 4809 #define MMEA0_EDC_CNT2__MAM_D0MEM_DED_COUNT__SHIFT 0x18 4810 #define MMEA0_EDC_CNT2__MAM_D1MEM_DED_COUNT__SHIFT 0x1a 4811 #define MMEA0_EDC_CNT2__MAM_D2MEM_DED_COUNT__SHIFT 0x1c 4812 #define MMEA0_EDC_CNT2__MAM_D3MEM_DED_COUNT__SHIFT 0x1e 4813 #define MMEA0_EDC_CNT2__GMIRD_CMDMEM_SEC_COUNT_MASK 0x00000003L 4814 #define MMEA0_EDC_CNT2__GMIRD_CMDMEM_DED_COUNT_MASK 0x0000000CL 4815 #define MMEA0_EDC_CNT2__GMIWR_CMDMEM_SEC_COUNT_MASK 0x00000030L 4816 #define MMEA0_EDC_CNT2__GMIWR_CMDMEM_DED_COUNT_MASK 0x000000C0L 4817 #define MMEA0_EDC_CNT2__GMIWR_DATAMEM_SEC_COUNT_MASK 0x00000300L 4818 #define MMEA0_EDC_CNT2__GMIWR_DATAMEM_DED_COUNT_MASK 0x00000C00L 4819 #define MMEA0_EDC_CNT2__GMIRD_PAGEMEM_SED_COUNT_MASK 0x00003000L 4820 #define MMEA0_EDC_CNT2__GMIWR_PAGEMEM_SED_COUNT_MASK 0x0000C000L 4821 #define MMEA0_EDC_CNT2__MAM_D0MEM_SED_COUNT_MASK 0x00030000L 4822 #define MMEA0_EDC_CNT2__MAM_D1MEM_SED_COUNT_MASK 0x000C0000L 4823 #define MMEA0_EDC_CNT2__MAM_D2MEM_SED_COUNT_MASK 0x00300000L 4824 #define MMEA0_EDC_CNT2__MAM_D3MEM_SED_COUNT_MASK 0x00C00000L 4825 #define MMEA0_EDC_CNT2__MAM_D0MEM_DED_COUNT_MASK 0x03000000L 4826 #define MMEA0_EDC_CNT2__MAM_D1MEM_DED_COUNT_MASK 0x0C000000L 4827 #define MMEA0_EDC_CNT2__MAM_D2MEM_DED_COUNT_MASK 0x30000000L 4828 #define MMEA0_EDC_CNT2__MAM_D3MEM_DED_COUNT_MASK 0xC0000000L 4829 //MMEA0_DSM_CNTL 4830 #define MMEA0_DSM_CNTL__DRAMRD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x0 4831 #define MMEA0_DSM_CNTL__DRAMRD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x2 4832 #define MMEA0_DSM_CNTL__DRAMWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x3 4833 #define MMEA0_DSM_CNTL__DRAMWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x5 4834 #define MMEA0_DSM_CNTL__DRAMWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT 0x6 4835 #define MMEA0_DSM_CNTL__DRAMWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT 0x8 4836 #define MMEA0_DSM_CNTL__RRET_TAGMEM_DSM_IRRITATOR_DATA__SHIFT 0x9 4837 #define MMEA0_DSM_CNTL__RRET_TAGMEM_ENABLE_SINGLE_WRITE__SHIFT 0xb 4838 #define MMEA0_DSM_CNTL__WRET_TAGMEM_DSM_IRRITATOR_DATA__SHIFT 0xc 4839 #define MMEA0_DSM_CNTL__WRET_TAGMEM_ENABLE_SINGLE_WRITE__SHIFT 0xe 4840 #define MMEA0_DSM_CNTL__GMIRD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0xf 4841 #define MMEA0_DSM_CNTL__GMIRD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x11 4842 #define MMEA0_DSM_CNTL__GMIWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x12 4843 #define MMEA0_DSM_CNTL__GMIWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x14 4844 #define MMEA0_DSM_CNTL__GMIWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT 0x15 4845 #define MMEA0_DSM_CNTL__GMIWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT 0x17 4846 #define MMEA0_DSM_CNTL__DRAMRD_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00000003L 4847 #define MMEA0_DSM_CNTL__DRAMRD_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000004L 4848 #define MMEA0_DSM_CNTL__DRAMWR_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00000018L 4849 #define MMEA0_DSM_CNTL__DRAMWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000020L 4850 #define MMEA0_DSM_CNTL__DRAMWR_DATAMEM_DSM_IRRITATOR_DATA_MASK 0x000000C0L 4851 #define MMEA0_DSM_CNTL__DRAMWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK 0x00000100L 4852 #define MMEA0_DSM_CNTL__RRET_TAGMEM_DSM_IRRITATOR_DATA_MASK 0x00000600L 4853 #define MMEA0_DSM_CNTL__RRET_TAGMEM_ENABLE_SINGLE_WRITE_MASK 0x00000800L 4854 #define MMEA0_DSM_CNTL__WRET_TAGMEM_DSM_IRRITATOR_DATA_MASK 0x00003000L 4855 #define MMEA0_DSM_CNTL__WRET_TAGMEM_ENABLE_SINGLE_WRITE_MASK 0x00004000L 4856 #define MMEA0_DSM_CNTL__GMIRD_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00018000L 4857 #define MMEA0_DSM_CNTL__GMIRD_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00020000L 4858 #define MMEA0_DSM_CNTL__GMIWR_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x000C0000L 4859 #define MMEA0_DSM_CNTL__GMIWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00100000L 4860 #define MMEA0_DSM_CNTL__GMIWR_DATAMEM_DSM_IRRITATOR_DATA_MASK 0x00600000L 4861 #define MMEA0_DSM_CNTL__GMIWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK 0x00800000L 4862 //MMEA0_DSM_CNTLA 4863 #define MMEA0_DSM_CNTLA__DRAMRD_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0x0 4864 #define MMEA0_DSM_CNTLA__DRAMRD_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x2 4865 #define MMEA0_DSM_CNTLA__DRAMWR_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0x3 4866 #define MMEA0_DSM_CNTLA__DRAMWR_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x5 4867 #define MMEA0_DSM_CNTLA__IORD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x6 4868 #define MMEA0_DSM_CNTLA__IORD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x8 4869 #define MMEA0_DSM_CNTLA__IOWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x9 4870 #define MMEA0_DSM_CNTLA__IOWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0xb 4871 #define MMEA0_DSM_CNTLA__IOWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT 0xc 4872 #define MMEA0_DSM_CNTLA__IOWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT 0xe 4873 #define MMEA0_DSM_CNTLA__GMIRD_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0xf 4874 #define MMEA0_DSM_CNTLA__GMIRD_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x11 4875 #define MMEA0_DSM_CNTLA__GMIWR_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0x12 4876 #define MMEA0_DSM_CNTLA__GMIWR_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x14 4877 #define MMEA0_DSM_CNTLA__DRAMRD_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x00000003L 4878 #define MMEA0_DSM_CNTLA__DRAMRD_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00000004L 4879 #define MMEA0_DSM_CNTLA__DRAMWR_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x00000018L 4880 #define MMEA0_DSM_CNTLA__DRAMWR_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00000020L 4881 #define MMEA0_DSM_CNTLA__IORD_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x000000C0L 4882 #define MMEA0_DSM_CNTLA__IORD_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000100L 4883 #define MMEA0_DSM_CNTLA__IOWR_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00000600L 4884 #define MMEA0_DSM_CNTLA__IOWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000800L 4885 #define MMEA0_DSM_CNTLA__IOWR_DATAMEM_DSM_IRRITATOR_DATA_MASK 0x00003000L 4886 #define MMEA0_DSM_CNTLA__IOWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK 0x00004000L 4887 #define MMEA0_DSM_CNTLA__GMIRD_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x00018000L 4888 #define MMEA0_DSM_CNTLA__GMIRD_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00020000L 4889 #define MMEA0_DSM_CNTLA__GMIWR_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x000C0000L 4890 #define MMEA0_DSM_CNTLA__GMIWR_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00100000L 4891 //MMEA0_DSM_CNTLB 4892 #define MMEA0_DSM_CNTLB__MAM_D0MEM_DSM_IRRITATOR_DATA__SHIFT 0x0 4893 #define MMEA0_DSM_CNTLB__MAM_D0MEM_ENABLE_SINGLE_WRITE__SHIFT 0x2 4894 #define MMEA0_DSM_CNTLB__MAM_D1MEM_DSM_IRRITATOR_DATA__SHIFT 0x3 4895 #define MMEA0_DSM_CNTLB__MAM_D1MEM_ENABLE_SINGLE_WRITE__SHIFT 0x5 4896 #define MMEA0_DSM_CNTLB__MAM_D2MEM_DSM_IRRITATOR_DATA__SHIFT 0x6 4897 #define MMEA0_DSM_CNTLB__MAM_D2MEM_ENABLE_SINGLE_WRITE__SHIFT 0x8 4898 #define MMEA0_DSM_CNTLB__MAM_D3MEM_DSM_IRRITATOR_DATA__SHIFT 0x9 4899 #define MMEA0_DSM_CNTLB__MAM_D3MEM_ENABLE_SINGLE_WRITE__SHIFT 0xb 4900 #define MMEA0_DSM_CNTLB__MAM_D0MEM_DSM_IRRITATOR_DATA_MASK 0x00000003L 4901 #define MMEA0_DSM_CNTLB__MAM_D0MEM_ENABLE_SINGLE_WRITE_MASK 0x00000004L 4902 #define MMEA0_DSM_CNTLB__MAM_D1MEM_DSM_IRRITATOR_DATA_MASK 0x00000018L 4903 #define MMEA0_DSM_CNTLB__MAM_D1MEM_ENABLE_SINGLE_WRITE_MASK 0x00000020L 4904 #define MMEA0_DSM_CNTLB__MAM_D2MEM_DSM_IRRITATOR_DATA_MASK 0x000000C0L 4905 #define MMEA0_DSM_CNTLB__MAM_D2MEM_ENABLE_SINGLE_WRITE_MASK 0x00000100L 4906 #define MMEA0_DSM_CNTLB__MAM_D3MEM_DSM_IRRITATOR_DATA_MASK 0x00000600L 4907 #define MMEA0_DSM_CNTLB__MAM_D3MEM_ENABLE_SINGLE_WRITE_MASK 0x00000800L 4908 //MMEA0_DSM_CNTL2 4909 #define MMEA0_DSM_CNTL2__DRAMRD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x0 4910 #define MMEA0_DSM_CNTL2__DRAMRD_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x2 4911 #define MMEA0_DSM_CNTL2__DRAMWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x3 4912 #define MMEA0_DSM_CNTL2__DRAMWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x5 4913 #define MMEA0_DSM_CNTL2__DRAMWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT 0x6 4914 #define MMEA0_DSM_CNTL2__DRAMWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT 0x8 4915 #define MMEA0_DSM_CNTL2__RRET_TAGMEM_ENABLE_ERROR_INJECT__SHIFT 0x9 4916 #define MMEA0_DSM_CNTL2__RRET_TAGMEM_SELECT_INJECT_DELAY__SHIFT 0xb 4917 #define MMEA0_DSM_CNTL2__WRET_TAGMEM_ENABLE_ERROR_INJECT__SHIFT 0xc 4918 #define MMEA0_DSM_CNTL2__WRET_TAGMEM_SELECT_INJECT_DELAY__SHIFT 0xe 4919 #define MMEA0_DSM_CNTL2__GMIRD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0xf 4920 #define MMEA0_DSM_CNTL2__GMIRD_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x11 4921 #define MMEA0_DSM_CNTL2__GMIWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x12 4922 #define MMEA0_DSM_CNTL2__GMIWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x14 4923 #define MMEA0_DSM_CNTL2__GMIWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT 0x15 4924 #define MMEA0_DSM_CNTL2__GMIWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT 0x17 4925 #define MMEA0_DSM_CNTL2__INJECT_DELAY__SHIFT 0x1a 4926 #define MMEA0_DSM_CNTL2__DRAMRD_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00000003L 4927 #define MMEA0_DSM_CNTL2__DRAMRD_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000004L 4928 #define MMEA0_DSM_CNTL2__DRAMWR_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00000018L 4929 #define MMEA0_DSM_CNTL2__DRAMWR_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000020L 4930 #define MMEA0_DSM_CNTL2__DRAMWR_DATAMEM_ENABLE_ERROR_INJECT_MASK 0x000000C0L 4931 #define MMEA0_DSM_CNTL2__DRAMWR_DATAMEM_SELECT_INJECT_DELAY_MASK 0x00000100L 4932 #define MMEA0_DSM_CNTL2__RRET_TAGMEM_ENABLE_ERROR_INJECT_MASK 0x00000600L 4933 #define MMEA0_DSM_CNTL2__RRET_TAGMEM_SELECT_INJECT_DELAY_MASK 0x00000800L 4934 #define MMEA0_DSM_CNTL2__WRET_TAGMEM_ENABLE_ERROR_INJECT_MASK 0x00003000L 4935 #define MMEA0_DSM_CNTL2__WRET_TAGMEM_SELECT_INJECT_DELAY_MASK 0x00004000L 4936 #define MMEA0_DSM_CNTL2__GMIRD_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00018000L 4937 #define MMEA0_DSM_CNTL2__GMIRD_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00020000L 4938 #define MMEA0_DSM_CNTL2__GMIWR_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x000C0000L 4939 #define MMEA0_DSM_CNTL2__GMIWR_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00100000L 4940 #define MMEA0_DSM_CNTL2__GMIWR_DATAMEM_ENABLE_ERROR_INJECT_MASK 0x00600000L 4941 #define MMEA0_DSM_CNTL2__GMIWR_DATAMEM_SELECT_INJECT_DELAY_MASK 0x00800000L 4942 #define MMEA0_DSM_CNTL2__INJECT_DELAY_MASK 0xFC000000L 4943 //MMEA0_DSM_CNTL2A 4944 #define MMEA0_DSM_CNTL2A__DRAMRD_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0x0 4945 #define MMEA0_DSM_CNTL2A__DRAMRD_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x2 4946 #define MMEA0_DSM_CNTL2A__DRAMWR_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0x3 4947 #define MMEA0_DSM_CNTL2A__DRAMWR_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x5 4948 #define MMEA0_DSM_CNTL2A__IORD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x6 4949 #define MMEA0_DSM_CNTL2A__IORD_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x8 4950 #define MMEA0_DSM_CNTL2A__IOWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x9 4951 #define MMEA0_DSM_CNTL2A__IOWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0xb 4952 #define MMEA0_DSM_CNTL2A__IOWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT 0xc 4953 #define MMEA0_DSM_CNTL2A__IOWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT 0xe 4954 #define MMEA0_DSM_CNTL2A__GMIRD_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0xf 4955 #define MMEA0_DSM_CNTL2A__GMIRD_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x11 4956 #define MMEA0_DSM_CNTL2A__GMIWR_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0x12 4957 #define MMEA0_DSM_CNTL2A__GMIWR_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x14 4958 #define MMEA0_DSM_CNTL2A__DRAMRD_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x00000003L 4959 #define MMEA0_DSM_CNTL2A__DRAMRD_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00000004L 4960 #define MMEA0_DSM_CNTL2A__DRAMWR_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x00000018L 4961 #define MMEA0_DSM_CNTL2A__DRAMWR_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00000020L 4962 #define MMEA0_DSM_CNTL2A__IORD_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x000000C0L 4963 #define MMEA0_DSM_CNTL2A__IORD_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000100L 4964 #define MMEA0_DSM_CNTL2A__IOWR_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00000600L 4965 #define MMEA0_DSM_CNTL2A__IOWR_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000800L 4966 #define MMEA0_DSM_CNTL2A__IOWR_DATAMEM_ENABLE_ERROR_INJECT_MASK 0x00003000L 4967 #define MMEA0_DSM_CNTL2A__IOWR_DATAMEM_SELECT_INJECT_DELAY_MASK 0x00004000L 4968 #define MMEA0_DSM_CNTL2A__GMIRD_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x00018000L 4969 #define MMEA0_DSM_CNTL2A__GMIRD_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00020000L 4970 #define MMEA0_DSM_CNTL2A__GMIWR_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x000C0000L 4971 #define MMEA0_DSM_CNTL2A__GMIWR_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00100000L 4972 //MMEA0_DSM_CNTL2B 4973 #define MMEA0_DSM_CNTL2B__MAM_D0MEM_ENABLE_ERROR_INJECT__SHIFT 0x0 4974 #define MMEA0_DSM_CNTL2B__MAM_D0MEM_SELECT_INJECT_DELAY__SHIFT 0x2 4975 #define MMEA0_DSM_CNTL2B__MAM_D1MEM_ENABLE_ERROR_INJECT__SHIFT 0x3 4976 #define MMEA0_DSM_CNTL2B__MAM_D1MEM_SELECT_INJECT_DELAY__SHIFT 0x5 4977 #define MMEA0_DSM_CNTL2B__MAM_D2MEM_ENABLE_ERROR_INJECT__SHIFT 0x6 4978 #define MMEA0_DSM_CNTL2B__MAM_D2MEM_SELECT_INJECT_DELAY__SHIFT 0x8 4979 #define MMEA0_DSM_CNTL2B__MAM_D3MEM_ENABLE_ERROR_INJECT__SHIFT 0x9 4980 #define MMEA0_DSM_CNTL2B__MAM_D3MEM_SELECT_INJECT_DELAY__SHIFT 0xb 4981 #define MMEA0_DSM_CNTL2B__MAM_D0MEM_ENABLE_ERROR_INJECT_MASK 0x00000003L 4982 #define MMEA0_DSM_CNTL2B__MAM_D0MEM_SELECT_INJECT_DELAY_MASK 0x00000004L 4983 #define MMEA0_DSM_CNTL2B__MAM_D1MEM_ENABLE_ERROR_INJECT_MASK 0x00000018L 4984 #define MMEA0_DSM_CNTL2B__MAM_D1MEM_SELECT_INJECT_DELAY_MASK 0x00000020L 4985 #define MMEA0_DSM_CNTL2B__MAM_D2MEM_ENABLE_ERROR_INJECT_MASK 0x000000C0L 4986 #define MMEA0_DSM_CNTL2B__MAM_D2MEM_SELECT_INJECT_DELAY_MASK 0x00000100L 4987 #define MMEA0_DSM_CNTL2B__MAM_D3MEM_ENABLE_ERROR_INJECT_MASK 0x00000600L 4988 #define MMEA0_DSM_CNTL2B__MAM_D3MEM_SELECT_INJECT_DELAY_MASK 0x00000800L 4989 //MMEA0_CGTT_CLK_CTRL 4990 #define MMEA0_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 4991 #define MMEA0_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 4992 #define MMEA0_CGTT_CLK_CTRL__SPARE0__SHIFT 0xc 4993 #define MMEA0_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_WRITE__SHIFT 0x14 4994 #define MMEA0_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_READ__SHIFT 0x15 4995 #define MMEA0_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_RETURN__SHIFT 0x16 4996 #define MMEA0_CGTT_CLK_CTRL__SPARE1__SHIFT 0x17 4997 #define MMEA0_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b 4998 #define MMEA0_CGTT_CLK_CTRL__SOFT_OVERRIDE_WRITE__SHIFT 0x1c 4999 #define MMEA0_CGTT_CLK_CTRL__SOFT_OVERRIDE_READ__SHIFT 0x1d 5000 #define MMEA0_CGTT_CLK_CTRL__SOFT_OVERRIDE_RETURN__SHIFT 0x1e 5001 #define MMEA0_CGTT_CLK_CTRL__SOFT_OVERRIDE_REGISTER__SHIFT 0x1f 5002 #define MMEA0_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL 5003 #define MMEA0_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L 5004 #define MMEA0_CGTT_CLK_CTRL__SPARE0_MASK 0x000FF000L 5005 #define MMEA0_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_WRITE_MASK 0x00100000L 5006 #define MMEA0_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_READ_MASK 0x00200000L 5007 #define MMEA0_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_RETURN_MASK 0x00400000L 5008 #define MMEA0_CGTT_CLK_CTRL__SPARE1_MASK 0x07800000L 5009 #define MMEA0_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L 5010 #define MMEA0_CGTT_CLK_CTRL__SOFT_OVERRIDE_WRITE_MASK 0x10000000L 5011 #define MMEA0_CGTT_CLK_CTRL__SOFT_OVERRIDE_READ_MASK 0x20000000L 5012 #define MMEA0_CGTT_CLK_CTRL__SOFT_OVERRIDE_RETURN_MASK 0x40000000L 5013 #define MMEA0_CGTT_CLK_CTRL__SOFT_OVERRIDE_REGISTER_MASK 0x80000000L 5014 //MMEA0_EDC_MODE 5015 #define MMEA0_EDC_MODE__COUNT_FED_OUT__SHIFT 0x10 5016 #define MMEA0_EDC_MODE__GATE_FUE__SHIFT 0x11 5017 #define MMEA0_EDC_MODE__DED_MODE__SHIFT 0x14 5018 #define MMEA0_EDC_MODE__PROP_FED__SHIFT 0x1d 5019 #define MMEA0_EDC_MODE__BYPASS__SHIFT 0x1f 5020 #define MMEA0_EDC_MODE__COUNT_FED_OUT_MASK 0x00010000L 5021 #define MMEA0_EDC_MODE__GATE_FUE_MASK 0x00020000L 5022 #define MMEA0_EDC_MODE__DED_MODE_MASK 0x00300000L 5023 #define MMEA0_EDC_MODE__PROP_FED_MASK 0x20000000L 5024 #define MMEA0_EDC_MODE__BYPASS_MASK 0x80000000L 5025 //MMEA0_ERR_STATUS 5026 #define MMEA0_ERR_STATUS__SDP_RDRSP_STATUS__SHIFT 0x0 5027 #define MMEA0_ERR_STATUS__SDP_WRRSP_STATUS__SHIFT 0x4 5028 #define MMEA0_ERR_STATUS__SDP_RDRSP_DATASTATUS__SHIFT 0x8 5029 #define MMEA0_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR__SHIFT 0xa 5030 #define MMEA0_ERR_STATUS__CLEAR_ERROR_STATUS__SHIFT 0xb 5031 #define MMEA0_ERR_STATUS__BUSY_ON_ERROR__SHIFT 0xc 5032 #define MMEA0_ERR_STATUS__FUE_FLAG__SHIFT 0xd 5033 #define MMEA0_ERR_STATUS__IGNORE_RDRSP_FED__SHIFT 0xe 5034 #define MMEA0_ERR_STATUS__INTERRUPT_ON_FATAL__SHIFT 0xf 5035 #define MMEA0_ERR_STATUS__INTERRUPT_IGNORE_CLI_FATAL__SHIFT 0x10 5036 #define MMEA0_ERR_STATUS__LEVEL_INTERRUPT__SHIFT 0x11 5037 #define MMEA0_ERR_STATUS__SDP_RDRSP_STATUS_MASK 0x0000000FL 5038 #define MMEA0_ERR_STATUS__SDP_WRRSP_STATUS_MASK 0x000000F0L 5039 #define MMEA0_ERR_STATUS__SDP_RDRSP_DATASTATUS_MASK 0x00000300L 5040 #define MMEA0_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR_MASK 0x00000400L 5041 #define MMEA0_ERR_STATUS__CLEAR_ERROR_STATUS_MASK 0x00000800L 5042 #define MMEA0_ERR_STATUS__BUSY_ON_ERROR_MASK 0x00001000L 5043 #define MMEA0_ERR_STATUS__FUE_FLAG_MASK 0x00002000L 5044 #define MMEA0_ERR_STATUS__IGNORE_RDRSP_FED_MASK 0x00004000L 5045 #define MMEA0_ERR_STATUS__INTERRUPT_ON_FATAL_MASK 0x00008000L 5046 #define MMEA0_ERR_STATUS__INTERRUPT_IGNORE_CLI_FATAL_MASK 0x00010000L 5047 #define MMEA0_ERR_STATUS__LEVEL_INTERRUPT_MASK 0x00020000L 5048 //MMEA0_MISC2 5049 #define MMEA0_MISC2__CSGROUP_SWAP_IN_DRAM_ARB__SHIFT 0x0 5050 #define MMEA0_MISC2__CSGROUP_SWAP_IN_GMI_ARB__SHIFT 0x1 5051 #define MMEA0_MISC2__CSGRP_BURST_LIMIT_DATA_DRAM__SHIFT 0x2 5052 #define MMEA0_MISC2__CSGRP_BURST_LIMIT_DATA_GMI__SHIFT 0x7 5053 #define MMEA0_MISC2__IO_RDWR_PRIORITY_ENABLE__SHIFT 0xc 5054 #define MMEA0_MISC2__RRET_SWAP_MODE__SHIFT 0xd 5055 #define MMEA0_MISC2__BLOCK_REQUESTS__SHIFT 0xe 5056 #define MMEA0_MISC2__REQUESTS_BLOCKED__SHIFT 0xf 5057 #define MMEA0_MISC2__CSGROUP_SWAP_IN_DRAM_ARB_MASK 0x00000001L 5058 #define MMEA0_MISC2__CSGROUP_SWAP_IN_GMI_ARB_MASK 0x00000002L 5059 #define MMEA0_MISC2__CSGRP_BURST_LIMIT_DATA_DRAM_MASK 0x0000007CL 5060 #define MMEA0_MISC2__CSGRP_BURST_LIMIT_DATA_GMI_MASK 0x00000F80L 5061 #define MMEA0_MISC2__IO_RDWR_PRIORITY_ENABLE_MASK 0x00001000L 5062 #define MMEA0_MISC2__RRET_SWAP_MODE_MASK 0x00002000L 5063 #define MMEA0_MISC2__BLOCK_REQUESTS_MASK 0x00004000L 5064 #define MMEA0_MISC2__REQUESTS_BLOCKED_MASK 0x00008000L 5065 //MMEA0_ADDRDEC_SELECT 5066 #define MMEA0_ADDRDEC_SELECT__DRAM_ADDRDEC_CHANNEL_START__SHIFT 0x0 5067 #define MMEA0_ADDRDEC_SELECT__DRAM_ADDRDEC_CHANNEL_END__SHIFT 0x5 5068 #define MMEA0_ADDRDEC_SELECT__GMI_ADDRDEC_CHANNEL_START__SHIFT 0xa 5069 #define MMEA0_ADDRDEC_SELECT__GMI_ADDRDEC_CHANNEL_END__SHIFT 0xf 5070 #define MMEA0_ADDRDEC_SELECT__DRAM_GECC_ENABLE__SHIFT 0x14 5071 #define MMEA0_ADDRDEC_SELECT__GMI_GECC_ENABLE__SHIFT 0x15 5072 #define MMEA0_ADDRDEC_SELECT__DRAM_SKIP_MSB__SHIFT 0x16 5073 #define MMEA0_ADDRDEC_SELECT__GMI_SKIP_MSB__SHIFT 0x17 5074 #define MMEA0_ADDRDEC_SELECT__DRAM_ADDRDEC_CHANNEL_START_MASK 0x0000001FL 5075 #define MMEA0_ADDRDEC_SELECT__DRAM_ADDRDEC_CHANNEL_END_MASK 0x000003E0L 5076 #define MMEA0_ADDRDEC_SELECT__GMI_ADDRDEC_CHANNEL_START_MASK 0x00007C00L 5077 #define MMEA0_ADDRDEC_SELECT__GMI_ADDRDEC_CHANNEL_END_MASK 0x000F8000L 5078 #define MMEA0_ADDRDEC_SELECT__DRAM_GECC_ENABLE_MASK 0x00100000L 5079 #define MMEA0_ADDRDEC_SELECT__GMI_GECC_ENABLE_MASK 0x00200000L 5080 #define MMEA0_ADDRDEC_SELECT__DRAM_SKIP_MSB_MASK 0x00400000L 5081 #define MMEA0_ADDRDEC_SELECT__GMI_SKIP_MSB_MASK 0x00800000L 5082 //MMEA0_EDC_CNT3 5083 #define MMEA0_EDC_CNT3__DRAMRD_PAGEMEM_DED_COUNT__SHIFT 0x0 5084 #define MMEA0_EDC_CNT3__DRAMWR_PAGEMEM_DED_COUNT__SHIFT 0x2 5085 #define MMEA0_EDC_CNT3__IORD_CMDMEM_DED_COUNT__SHIFT 0x4 5086 #define MMEA0_EDC_CNT3__IOWR_CMDMEM_DED_COUNT__SHIFT 0x6 5087 #define MMEA0_EDC_CNT3__GMIRD_PAGEMEM_DED_COUNT__SHIFT 0x8 5088 #define MMEA0_EDC_CNT3__GMIWR_PAGEMEM_DED_COUNT__SHIFT 0xa 5089 #define MMEA0_EDC_CNT3__DRAMRD_PAGEMEM_DED_COUNT_MASK 0x00000003L 5090 #define MMEA0_EDC_CNT3__DRAMWR_PAGEMEM_DED_COUNT_MASK 0x0000000CL 5091 #define MMEA0_EDC_CNT3__IORD_CMDMEM_DED_COUNT_MASK 0x00000030L 5092 #define MMEA0_EDC_CNT3__IOWR_CMDMEM_DED_COUNT_MASK 0x000000C0L 5093 #define MMEA0_EDC_CNT3__GMIRD_PAGEMEM_DED_COUNT_MASK 0x00000300L 5094 #define MMEA0_EDC_CNT3__GMIWR_PAGEMEM_DED_COUNT_MASK 0x00000C00L 5095 //MMEA0_SDP_PRIORITY_OVERRIDE 5096 #define MMEA0_SDP_PRIORITY_OVERRIDE__OVERRIDE0_PRIORITY__SHIFT 0x0 5097 #define MMEA0_SDP_PRIORITY_OVERRIDE__OVERRIDE0_CLIENT_ID__SHIFT 0x4 5098 #define MMEA0_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_DRAM_RD__SHIFT 0x9 5099 #define MMEA0_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_DRAM_WR__SHIFT 0xa 5100 #define MMEA0_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_GMI_RD__SHIFT 0xb 5101 #define MMEA0_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_GMI_WR__SHIFT 0xc 5102 #define MMEA0_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_IO_RD__SHIFT 0xd 5103 #define MMEA0_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_IO_WR__SHIFT 0xe 5104 #define MMEA0_SDP_PRIORITY_OVERRIDE__OVERRIDE1_PRIORITY__SHIFT 0x10 5105 #define MMEA0_SDP_PRIORITY_OVERRIDE__OVERRIDE1_CLIENT_ID__SHIFT 0x14 5106 #define MMEA0_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_DRAM_RD__SHIFT 0x19 5107 #define MMEA0_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_DRAM_WR__SHIFT 0x1a 5108 #define MMEA0_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_GMI_RD__SHIFT 0x1b 5109 #define MMEA0_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_GMI_WR__SHIFT 0x1c 5110 #define MMEA0_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_IO_RD__SHIFT 0x1d 5111 #define MMEA0_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_IO_WR__SHIFT 0x1e 5112 #define MMEA0_SDP_PRIORITY_OVERRIDE__OVERRIDE0_PRIORITY_MASK 0x0000000FL 5113 #define MMEA0_SDP_PRIORITY_OVERRIDE__OVERRIDE0_CLIENT_ID_MASK 0x000001F0L 5114 #define MMEA0_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_DRAM_RD_MASK 0x00000200L 5115 #define MMEA0_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_DRAM_WR_MASK 0x00000400L 5116 #define MMEA0_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_GMI_RD_MASK 0x00000800L 5117 #define MMEA0_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_GMI_WR_MASK 0x00001000L 5118 #define MMEA0_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_IO_RD_MASK 0x00002000L 5119 #define MMEA0_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_IO_WR_MASK 0x00004000L 5120 #define MMEA0_SDP_PRIORITY_OVERRIDE__OVERRIDE1_PRIORITY_MASK 0x000F0000L 5121 #define MMEA0_SDP_PRIORITY_OVERRIDE__OVERRIDE1_CLIENT_ID_MASK 0x01F00000L 5122 #define MMEA0_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_DRAM_RD_MASK 0x02000000L 5123 #define MMEA0_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_DRAM_WR_MASK 0x04000000L 5124 #define MMEA0_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_GMI_RD_MASK 0x08000000L 5125 #define MMEA0_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_GMI_WR_MASK 0x10000000L 5126 #define MMEA0_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_IO_RD_MASK 0x20000000L 5127 #define MMEA0_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_IO_WR_MASK 0x40000000L 5128 //MMEA0_MISC_AON 5129 #define MMEA0_MISC_AON__LINKMGR_PARTACK_HYSTERESIS__SHIFT 0x0 5130 #define MMEA0_MISC_AON__LINKMGR_PARTACK_DEASSERT_MODE__SHIFT 0x2 5131 #define MMEA0_MISC_AON__LINKMGR_PARTACK_HYSTERESIS_MASK 0x00000003L 5132 #define MMEA0_MISC_AON__LINKMGR_PARTACK_DEASSERT_MODE_MASK 0x00000004L 5133 5134 5135 // addressBlock: mmhub_pctldec 5136 //PCTL_CTRL 5137 #define PCTL_CTRL__PG_ENABLE__SHIFT 0x0 5138 #define PCTL_CTRL__ALLOW_DEEP_SLEEP_MODE__SHIFT 0x1 5139 #define PCTL_CTRL__STCTRL_DAGB_IDLE_THRESHOLD__SHIFT 0xe 5140 #define PCTL_CTRL__STCTRL_IGNORE_PROTECTION_FAULT__SHIFT 0x13 5141 #define PCTL_CTRL__UTCL2_LEGACY_MODE__SHIFT 0x14 5142 #define PCTL_CTRL__SDP_DISCONNECT_MODE__SHIFT 0x15 5143 #define PCTL_CTRL__PG_ENABLE_MASK 0x00000001L 5144 #define PCTL_CTRL__ALLOW_DEEP_SLEEP_MODE_MASK 0x0000000EL 5145 #define PCTL_CTRL__STCTRL_DAGB_IDLE_THRESHOLD_MASK 0x0007C000L 5146 #define PCTL_CTRL__STCTRL_IGNORE_PROTECTION_FAULT_MASK 0x00080000L 5147 #define PCTL_CTRL__UTCL2_LEGACY_MODE_MASK 0x00100000L 5148 #define PCTL_CTRL__SDP_DISCONNECT_MODE_MASK 0x00200000L 5149 //PCTL_MMHUB_DEEPSLEEP_IB 5150 #define PCTL_MMHUB_DEEPSLEEP_IB__DS0__SHIFT 0x0 5151 #define PCTL_MMHUB_DEEPSLEEP_IB__DS1__SHIFT 0x1 5152 #define PCTL_MMHUB_DEEPSLEEP_IB__DS2__SHIFT 0x2 5153 #define PCTL_MMHUB_DEEPSLEEP_IB__DS3__SHIFT 0x3 5154 #define PCTL_MMHUB_DEEPSLEEP_IB__DS4__SHIFT 0x4 5155 #define PCTL_MMHUB_DEEPSLEEP_IB__DS5__SHIFT 0x5 5156 #define PCTL_MMHUB_DEEPSLEEP_IB__DS6__SHIFT 0x6 5157 #define PCTL_MMHUB_DEEPSLEEP_IB__DS7__SHIFT 0x7 5158 #define PCTL_MMHUB_DEEPSLEEP_IB__DS8__SHIFT 0x8 5159 #define PCTL_MMHUB_DEEPSLEEP_IB__DS9__SHIFT 0x9 5160 #define PCTL_MMHUB_DEEPSLEEP_IB__DS10__SHIFT 0xa 5161 #define PCTL_MMHUB_DEEPSLEEP_IB__DS11__SHIFT 0xb 5162 #define PCTL_MMHUB_DEEPSLEEP_IB__DS12__SHIFT 0xc 5163 #define PCTL_MMHUB_DEEPSLEEP_IB__DS13__SHIFT 0xd 5164 #define PCTL_MMHUB_DEEPSLEEP_IB__DS14__SHIFT 0xe 5165 #define PCTL_MMHUB_DEEPSLEEP_IB__DS15__SHIFT 0xf 5166 #define PCTL_MMHUB_DEEPSLEEP_IB__DS16__SHIFT 0x10 5167 #define PCTL_MMHUB_DEEPSLEEP_IB__SETCLEAR__SHIFT 0x1f 5168 #define PCTL_MMHUB_DEEPSLEEP_IB__DS0_MASK 0x00000001L 5169 #define PCTL_MMHUB_DEEPSLEEP_IB__DS1_MASK 0x00000002L 5170 #define PCTL_MMHUB_DEEPSLEEP_IB__DS2_MASK 0x00000004L 5171 #define PCTL_MMHUB_DEEPSLEEP_IB__DS3_MASK 0x00000008L 5172 #define PCTL_MMHUB_DEEPSLEEP_IB__DS4_MASK 0x00000010L 5173 #define PCTL_MMHUB_DEEPSLEEP_IB__DS5_MASK 0x00000020L 5174 #define PCTL_MMHUB_DEEPSLEEP_IB__DS6_MASK 0x00000040L 5175 #define PCTL_MMHUB_DEEPSLEEP_IB__DS7_MASK 0x00000080L 5176 #define PCTL_MMHUB_DEEPSLEEP_IB__DS8_MASK 0x00000100L 5177 #define PCTL_MMHUB_DEEPSLEEP_IB__DS9_MASK 0x00000200L 5178 #define PCTL_MMHUB_DEEPSLEEP_IB__DS10_MASK 0x00000400L 5179 #define PCTL_MMHUB_DEEPSLEEP_IB__DS11_MASK 0x00000800L 5180 #define PCTL_MMHUB_DEEPSLEEP_IB__DS12_MASK 0x00001000L 5181 #define PCTL_MMHUB_DEEPSLEEP_IB__DS13_MASK 0x00002000L 5182 #define PCTL_MMHUB_DEEPSLEEP_IB__DS14_MASK 0x00004000L 5183 #define PCTL_MMHUB_DEEPSLEEP_IB__DS15_MASK 0x00008000L 5184 #define PCTL_MMHUB_DEEPSLEEP_IB__DS16_MASK 0x00010000L 5185 #define PCTL_MMHUB_DEEPSLEEP_IB__SETCLEAR_MASK 0x80000000L 5186 //PCTL_MMHUB_DEEPSLEEP_OVERRIDE 5187 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS0__SHIFT 0x0 5188 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS1__SHIFT 0x1 5189 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS2__SHIFT 0x2 5190 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS3__SHIFT 0x3 5191 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS4__SHIFT 0x4 5192 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS5__SHIFT 0x5 5193 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS6__SHIFT 0x6 5194 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS7__SHIFT 0x7 5195 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS8__SHIFT 0x8 5196 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS9__SHIFT 0x9 5197 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS10__SHIFT 0xa 5198 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS11__SHIFT 0xb 5199 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS12__SHIFT 0xc 5200 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS13__SHIFT 0xd 5201 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS14__SHIFT 0xe 5202 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS15__SHIFT 0xf 5203 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS16__SHIFT 0x10 5204 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS_ATHUB__SHIFT 0x11 5205 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS0_MASK 0x00000001L 5206 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS1_MASK 0x00000002L 5207 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS2_MASK 0x00000004L 5208 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS3_MASK 0x00000008L 5209 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS4_MASK 0x00000010L 5210 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS5_MASK 0x00000020L 5211 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS6_MASK 0x00000040L 5212 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS7_MASK 0x00000080L 5213 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS8_MASK 0x00000100L 5214 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS9_MASK 0x00000200L 5215 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS10_MASK 0x00000400L 5216 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS11_MASK 0x00000800L 5217 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS12_MASK 0x00001000L 5218 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS13_MASK 0x00002000L 5219 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS14_MASK 0x00004000L 5220 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS15_MASK 0x00008000L 5221 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS16_MASK 0x00010000L 5222 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS_ATHUB_MASK 0x00020000L 5223 //PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB 5224 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS0__SHIFT 0x0 5225 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS1__SHIFT 0x1 5226 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS2__SHIFT 0x2 5227 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS3__SHIFT 0x3 5228 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS4__SHIFT 0x4 5229 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS5__SHIFT 0x5 5230 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS6__SHIFT 0x6 5231 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS7__SHIFT 0x7 5232 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS8__SHIFT 0x8 5233 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS9__SHIFT 0x9 5234 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS10__SHIFT 0xa 5235 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS11__SHIFT 0xb 5236 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS12__SHIFT 0xc 5237 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS13__SHIFT 0xd 5238 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS14__SHIFT 0xe 5239 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS15__SHIFT 0xf 5240 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS16__SHIFT 0x10 5241 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS0_MASK 0x00000001L 5242 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS1_MASK 0x00000002L 5243 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS2_MASK 0x00000004L 5244 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS3_MASK 0x00000008L 5245 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS4_MASK 0x00000010L 5246 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS5_MASK 0x00000020L 5247 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS6_MASK 0x00000040L 5248 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS7_MASK 0x00000080L 5249 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS8_MASK 0x00000100L 5250 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS9_MASK 0x00000200L 5251 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS10_MASK 0x00000400L 5252 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS11_MASK 0x00000800L 5253 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS12_MASK 0x00001000L 5254 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS13_MASK 0x00002000L 5255 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS14_MASK 0x00004000L 5256 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS15_MASK 0x00008000L 5257 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS16_MASK 0x00010000L 5258 //PCTL_PG_IGNORE_DEEPSLEEP 5259 #define PCTL_PG_IGNORE_DEEPSLEEP__DS0__SHIFT 0x0 5260 #define PCTL_PG_IGNORE_DEEPSLEEP__DS1__SHIFT 0x1 5261 #define PCTL_PG_IGNORE_DEEPSLEEP__DS2__SHIFT 0x2 5262 #define PCTL_PG_IGNORE_DEEPSLEEP__DS3__SHIFT 0x3 5263 #define PCTL_PG_IGNORE_DEEPSLEEP__DS4__SHIFT 0x4 5264 #define PCTL_PG_IGNORE_DEEPSLEEP__DS5__SHIFT 0x5 5265 #define PCTL_PG_IGNORE_DEEPSLEEP__DS6__SHIFT 0x6 5266 #define PCTL_PG_IGNORE_DEEPSLEEP__DS7__SHIFT 0x7 5267 #define PCTL_PG_IGNORE_DEEPSLEEP__DS8__SHIFT 0x8 5268 #define PCTL_PG_IGNORE_DEEPSLEEP__DS9__SHIFT 0x9 5269 #define PCTL_PG_IGNORE_DEEPSLEEP__DS10__SHIFT 0xa 5270 #define PCTL_PG_IGNORE_DEEPSLEEP__DS11__SHIFT 0xb 5271 #define PCTL_PG_IGNORE_DEEPSLEEP__DS12__SHIFT 0xc 5272 #define PCTL_PG_IGNORE_DEEPSLEEP__DS13__SHIFT 0xd 5273 #define PCTL_PG_IGNORE_DEEPSLEEP__DS14__SHIFT 0xe 5274 #define PCTL_PG_IGNORE_DEEPSLEEP__DS15__SHIFT 0xf 5275 #define PCTL_PG_IGNORE_DEEPSLEEP__DS16__SHIFT 0x10 5276 #define PCTL_PG_IGNORE_DEEPSLEEP__DS_ATHUB__SHIFT 0x11 5277 #define PCTL_PG_IGNORE_DEEPSLEEP__ALLIPS__SHIFT 0x12 5278 #define PCTL_PG_IGNORE_DEEPSLEEP__DS0_MASK 0x00000001L 5279 #define PCTL_PG_IGNORE_DEEPSLEEP__DS1_MASK 0x00000002L 5280 #define PCTL_PG_IGNORE_DEEPSLEEP__DS2_MASK 0x00000004L 5281 #define PCTL_PG_IGNORE_DEEPSLEEP__DS3_MASK 0x00000008L 5282 #define PCTL_PG_IGNORE_DEEPSLEEP__DS4_MASK 0x00000010L 5283 #define PCTL_PG_IGNORE_DEEPSLEEP__DS5_MASK 0x00000020L 5284 #define PCTL_PG_IGNORE_DEEPSLEEP__DS6_MASK 0x00000040L 5285 #define PCTL_PG_IGNORE_DEEPSLEEP__DS7_MASK 0x00000080L 5286 #define PCTL_PG_IGNORE_DEEPSLEEP__DS8_MASK 0x00000100L 5287 #define PCTL_PG_IGNORE_DEEPSLEEP__DS9_MASK 0x00000200L 5288 #define PCTL_PG_IGNORE_DEEPSLEEP__DS10_MASK 0x00000400L 5289 #define PCTL_PG_IGNORE_DEEPSLEEP__DS11_MASK 0x00000800L 5290 #define PCTL_PG_IGNORE_DEEPSLEEP__DS12_MASK 0x00001000L 5291 #define PCTL_PG_IGNORE_DEEPSLEEP__DS13_MASK 0x00002000L 5292 #define PCTL_PG_IGNORE_DEEPSLEEP__DS14_MASK 0x00004000L 5293 #define PCTL_PG_IGNORE_DEEPSLEEP__DS15_MASK 0x00008000L 5294 #define PCTL_PG_IGNORE_DEEPSLEEP__DS16_MASK 0x00010000L 5295 #define PCTL_PG_IGNORE_DEEPSLEEP__DS_ATHUB_MASK 0x00020000L 5296 #define PCTL_PG_IGNORE_DEEPSLEEP__ALLIPS_MASK 0x00040000L 5297 //PCTL_PG_IGNORE_DEEPSLEEP_IB 5298 #define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS0__SHIFT 0x0 5299 #define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS1__SHIFT 0x1 5300 #define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS2__SHIFT 0x2 5301 #define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS3__SHIFT 0x3 5302 #define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS4__SHIFT 0x4 5303 #define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS5__SHIFT 0x5 5304 #define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS6__SHIFT 0x6 5305 #define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS7__SHIFT 0x7 5306 #define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS8__SHIFT 0x8 5307 #define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS9__SHIFT 0x9 5308 #define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS10__SHIFT 0xa 5309 #define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS11__SHIFT 0xb 5310 #define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS12__SHIFT 0xc 5311 #define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS13__SHIFT 0xd 5312 #define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS14__SHIFT 0xe 5313 #define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS15__SHIFT 0xf 5314 #define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS16__SHIFT 0x10 5315 #define PCTL_PG_IGNORE_DEEPSLEEP_IB__ALLIPS__SHIFT 0x11 5316 #define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS0_MASK 0x00000001L 5317 #define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS1_MASK 0x00000002L 5318 #define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS2_MASK 0x00000004L 5319 #define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS3_MASK 0x00000008L 5320 #define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS4_MASK 0x00000010L 5321 #define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS5_MASK 0x00000020L 5322 #define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS6_MASK 0x00000040L 5323 #define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS7_MASK 0x00000080L 5324 #define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS8_MASK 0x00000100L 5325 #define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS9_MASK 0x00000200L 5326 #define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS10_MASK 0x00000400L 5327 #define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS11_MASK 0x00000800L 5328 #define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS12_MASK 0x00001000L 5329 #define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS13_MASK 0x00002000L 5330 #define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS14_MASK 0x00004000L 5331 #define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS15_MASK 0x00008000L 5332 #define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS16_MASK 0x00010000L 5333 #define PCTL_PG_IGNORE_DEEPSLEEP_IB__ALLIPS_MASK 0x00020000L 5334 //PCTL_SLICE0_CFG_DAGB_WRBUSY 5335 #define PCTL_SLICE0_CFG_DAGB_WRBUSY__DB_LNCFG__SHIFT 0x0 5336 #define PCTL_SLICE0_CFG_DAGB_WRBUSY__DB_LNCFG_MASK 0xFFFFFFFFL 5337 //PCTL_SLICE0_CFG_DAGB_RDBUSY 5338 #define PCTL_SLICE0_CFG_DAGB_RDBUSY__DB_LNCFG__SHIFT 0x0 5339 #define PCTL_SLICE0_CFG_DAGB_RDBUSY__DB_LNCFG_MASK 0xFFFFFFFFL 5340 //PCTL_SLICE0_CFG_DS_ALLOW 5341 #define PCTL_SLICE0_CFG_DS_ALLOW__DS0__SHIFT 0x0 5342 #define PCTL_SLICE0_CFG_DS_ALLOW__DS1__SHIFT 0x1 5343 #define PCTL_SLICE0_CFG_DS_ALLOW__DS2__SHIFT 0x2 5344 #define PCTL_SLICE0_CFG_DS_ALLOW__DS3__SHIFT 0x3 5345 #define PCTL_SLICE0_CFG_DS_ALLOW__DS4__SHIFT 0x4 5346 #define PCTL_SLICE0_CFG_DS_ALLOW__DS5__SHIFT 0x5 5347 #define PCTL_SLICE0_CFG_DS_ALLOW__DS6__SHIFT 0x6 5348 #define PCTL_SLICE0_CFG_DS_ALLOW__DS7__SHIFT 0x7 5349 #define PCTL_SLICE0_CFG_DS_ALLOW__DS8__SHIFT 0x8 5350 #define PCTL_SLICE0_CFG_DS_ALLOW__DS9__SHIFT 0x9 5351 #define PCTL_SLICE0_CFG_DS_ALLOW__DS10__SHIFT 0xa 5352 #define PCTL_SLICE0_CFG_DS_ALLOW__DS11__SHIFT 0xb 5353 #define PCTL_SLICE0_CFG_DS_ALLOW__DS12__SHIFT 0xc 5354 #define PCTL_SLICE0_CFG_DS_ALLOW__DS13__SHIFT 0xd 5355 #define PCTL_SLICE0_CFG_DS_ALLOW__DS14__SHIFT 0xe 5356 #define PCTL_SLICE0_CFG_DS_ALLOW__DS15__SHIFT 0xf 5357 #define PCTL_SLICE0_CFG_DS_ALLOW__DS16__SHIFT 0x10 5358 #define PCTL_SLICE0_CFG_DS_ALLOW__DS0_MASK 0x00000001L 5359 #define PCTL_SLICE0_CFG_DS_ALLOW__DS1_MASK 0x00000002L 5360 #define PCTL_SLICE0_CFG_DS_ALLOW__DS2_MASK 0x00000004L 5361 #define PCTL_SLICE0_CFG_DS_ALLOW__DS3_MASK 0x00000008L 5362 #define PCTL_SLICE0_CFG_DS_ALLOW__DS4_MASK 0x00000010L 5363 #define PCTL_SLICE0_CFG_DS_ALLOW__DS5_MASK 0x00000020L 5364 #define PCTL_SLICE0_CFG_DS_ALLOW__DS6_MASK 0x00000040L 5365 #define PCTL_SLICE0_CFG_DS_ALLOW__DS7_MASK 0x00000080L 5366 #define PCTL_SLICE0_CFG_DS_ALLOW__DS8_MASK 0x00000100L 5367 #define PCTL_SLICE0_CFG_DS_ALLOW__DS9_MASK 0x00000200L 5368 #define PCTL_SLICE0_CFG_DS_ALLOW__DS10_MASK 0x00000400L 5369 #define PCTL_SLICE0_CFG_DS_ALLOW__DS11_MASK 0x00000800L 5370 #define PCTL_SLICE0_CFG_DS_ALLOW__DS12_MASK 0x00001000L 5371 #define PCTL_SLICE0_CFG_DS_ALLOW__DS13_MASK 0x00002000L 5372 #define PCTL_SLICE0_CFG_DS_ALLOW__DS14_MASK 0x00004000L 5373 #define PCTL_SLICE0_CFG_DS_ALLOW__DS15_MASK 0x00008000L 5374 #define PCTL_SLICE0_CFG_DS_ALLOW__DS16_MASK 0x00010000L 5375 //PCTL_SLICE0_CFG_DS_ALLOW_IB 5376 #define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS0__SHIFT 0x0 5377 #define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS1__SHIFT 0x1 5378 #define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS2__SHIFT 0x2 5379 #define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS3__SHIFT 0x3 5380 #define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS4__SHIFT 0x4 5381 #define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS5__SHIFT 0x5 5382 #define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS6__SHIFT 0x6 5383 #define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS7__SHIFT 0x7 5384 #define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS8__SHIFT 0x8 5385 #define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS9__SHIFT 0x9 5386 #define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS10__SHIFT 0xa 5387 #define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS11__SHIFT 0xb 5388 #define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS12__SHIFT 0xc 5389 #define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS13__SHIFT 0xd 5390 #define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS14__SHIFT 0xe 5391 #define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS15__SHIFT 0xf 5392 #define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS16__SHIFT 0x10 5393 #define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS0_MASK 0x00000001L 5394 #define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS1_MASK 0x00000002L 5395 #define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS2_MASK 0x00000004L 5396 #define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS3_MASK 0x00000008L 5397 #define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS4_MASK 0x00000010L 5398 #define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS5_MASK 0x00000020L 5399 #define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS6_MASK 0x00000040L 5400 #define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS7_MASK 0x00000080L 5401 #define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS8_MASK 0x00000100L 5402 #define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS9_MASK 0x00000200L 5403 #define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS10_MASK 0x00000400L 5404 #define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS11_MASK 0x00000800L 5405 #define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS12_MASK 0x00001000L 5406 #define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS13_MASK 0x00002000L 5407 #define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS14_MASK 0x00004000L 5408 #define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS15_MASK 0x00008000L 5409 #define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS16_MASK 0x00010000L 5410 //PCTL_SLICE1_CFG_DAGB_WRBUSY 5411 #define PCTL_SLICE1_CFG_DAGB_WRBUSY__DB_LNCFG__SHIFT 0x0 5412 #define PCTL_SLICE1_CFG_DAGB_WRBUSY__DB_LNCFG_MASK 0xFFFFFFFFL 5413 //PCTL_SLICE1_CFG_DAGB_RDBUSY 5414 #define PCTL_SLICE1_CFG_DAGB_RDBUSY__DB_LNCFG__SHIFT 0x0 5415 #define PCTL_SLICE1_CFG_DAGB_RDBUSY__DB_LNCFG_MASK 0xFFFFFFFFL 5416 //PCTL_SLICE1_CFG_DS_ALLOW 5417 #define PCTL_SLICE1_CFG_DS_ALLOW__DS0__SHIFT 0x0 5418 #define PCTL_SLICE1_CFG_DS_ALLOW__DS1__SHIFT 0x1 5419 #define PCTL_SLICE1_CFG_DS_ALLOW__DS2__SHIFT 0x2 5420 #define PCTL_SLICE1_CFG_DS_ALLOW__DS3__SHIFT 0x3 5421 #define PCTL_SLICE1_CFG_DS_ALLOW__DS4__SHIFT 0x4 5422 #define PCTL_SLICE1_CFG_DS_ALLOW__DS5__SHIFT 0x5 5423 #define PCTL_SLICE1_CFG_DS_ALLOW__DS6__SHIFT 0x6 5424 #define PCTL_SLICE1_CFG_DS_ALLOW__DS7__SHIFT 0x7 5425 #define PCTL_SLICE1_CFG_DS_ALLOW__DS8__SHIFT 0x8 5426 #define PCTL_SLICE1_CFG_DS_ALLOW__DS9__SHIFT 0x9 5427 #define PCTL_SLICE1_CFG_DS_ALLOW__DS10__SHIFT 0xa 5428 #define PCTL_SLICE1_CFG_DS_ALLOW__DS11__SHIFT 0xb 5429 #define PCTL_SLICE1_CFG_DS_ALLOW__DS12__SHIFT 0xc 5430 #define PCTL_SLICE1_CFG_DS_ALLOW__DS13__SHIFT 0xd 5431 #define PCTL_SLICE1_CFG_DS_ALLOW__DS14__SHIFT 0xe 5432 #define PCTL_SLICE1_CFG_DS_ALLOW__DS15__SHIFT 0xf 5433 #define PCTL_SLICE1_CFG_DS_ALLOW__DS16__SHIFT 0x10 5434 #define PCTL_SLICE1_CFG_DS_ALLOW__DS0_MASK 0x00000001L 5435 #define PCTL_SLICE1_CFG_DS_ALLOW__DS1_MASK 0x00000002L 5436 #define PCTL_SLICE1_CFG_DS_ALLOW__DS2_MASK 0x00000004L 5437 #define PCTL_SLICE1_CFG_DS_ALLOW__DS3_MASK 0x00000008L 5438 #define PCTL_SLICE1_CFG_DS_ALLOW__DS4_MASK 0x00000010L 5439 #define PCTL_SLICE1_CFG_DS_ALLOW__DS5_MASK 0x00000020L 5440 #define PCTL_SLICE1_CFG_DS_ALLOW__DS6_MASK 0x00000040L 5441 #define PCTL_SLICE1_CFG_DS_ALLOW__DS7_MASK 0x00000080L 5442 #define PCTL_SLICE1_CFG_DS_ALLOW__DS8_MASK 0x00000100L 5443 #define PCTL_SLICE1_CFG_DS_ALLOW__DS9_MASK 0x00000200L 5444 #define PCTL_SLICE1_CFG_DS_ALLOW__DS10_MASK 0x00000400L 5445 #define PCTL_SLICE1_CFG_DS_ALLOW__DS11_MASK 0x00000800L 5446 #define PCTL_SLICE1_CFG_DS_ALLOW__DS12_MASK 0x00001000L 5447 #define PCTL_SLICE1_CFG_DS_ALLOW__DS13_MASK 0x00002000L 5448 #define PCTL_SLICE1_CFG_DS_ALLOW__DS14_MASK 0x00004000L 5449 #define PCTL_SLICE1_CFG_DS_ALLOW__DS15_MASK 0x00008000L 5450 #define PCTL_SLICE1_CFG_DS_ALLOW__DS16_MASK 0x00010000L 5451 //PCTL_SLICE1_CFG_DS_ALLOW_IB 5452 #define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS0__SHIFT 0x0 5453 #define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS1__SHIFT 0x1 5454 #define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS2__SHIFT 0x2 5455 #define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS3__SHIFT 0x3 5456 #define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS4__SHIFT 0x4 5457 #define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS5__SHIFT 0x5 5458 #define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS6__SHIFT 0x6 5459 #define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS7__SHIFT 0x7 5460 #define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS8__SHIFT 0x8 5461 #define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS9__SHIFT 0x9 5462 #define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS10__SHIFT 0xa 5463 #define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS11__SHIFT 0xb 5464 #define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS12__SHIFT 0xc 5465 #define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS13__SHIFT 0xd 5466 #define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS14__SHIFT 0xe 5467 #define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS15__SHIFT 0xf 5468 #define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS16__SHIFT 0x10 5469 #define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS0_MASK 0x00000001L 5470 #define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS1_MASK 0x00000002L 5471 #define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS2_MASK 0x00000004L 5472 #define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS3_MASK 0x00000008L 5473 #define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS4_MASK 0x00000010L 5474 #define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS5_MASK 0x00000020L 5475 #define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS6_MASK 0x00000040L 5476 #define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS7_MASK 0x00000080L 5477 #define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS8_MASK 0x00000100L 5478 #define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS9_MASK 0x00000200L 5479 #define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS10_MASK 0x00000400L 5480 #define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS11_MASK 0x00000800L 5481 #define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS12_MASK 0x00001000L 5482 #define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS13_MASK 0x00002000L 5483 #define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS14_MASK 0x00004000L 5484 #define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS15_MASK 0x00008000L 5485 #define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS16_MASK 0x00010000L 5486 //PCTL_UTCL2_MISC 5487 #define PCTL_UTCL2_MISC__CRITICAL_REGS_LOCK__SHIFT 0xb 5488 #define PCTL_UTCL2_MISC__TILE_IDLE_THRESHOLD__SHIFT 0xc 5489 #define PCTL_UTCL2_MISC__RENG_MEM_LS_ENABLE__SHIFT 0xf 5490 #define PCTL_UTCL2_MISC__STCTRL_FORCE_PGFSM_CMD_DONE__SHIFT 0x10 5491 #define PCTL_UTCL2_MISC__RENG_EXECUTE_ON_REG_UPDATE__SHIFT 0x11 5492 #define PCTL_UTCL2_MISC__RD_TIMER_ENABLE__SHIFT 0x12 5493 #define PCTL_UTCL2_MISC__CRITICAL_REGS_LOCK_MASK 0x00000800L 5494 #define PCTL_UTCL2_MISC__TILE_IDLE_THRESHOLD_MASK 0x00007000L 5495 #define PCTL_UTCL2_MISC__RENG_MEM_LS_ENABLE_MASK 0x00008000L 5496 #define PCTL_UTCL2_MISC__STCTRL_FORCE_PGFSM_CMD_DONE_MASK 0x00010000L 5497 #define PCTL_UTCL2_MISC__RENG_EXECUTE_ON_REG_UPDATE_MASK 0x00020000L 5498 #define PCTL_UTCL2_MISC__RD_TIMER_ENABLE_MASK 0x00040000L 5499 //PCTL_SLICE0_MISC 5500 #define PCTL_SLICE0_MISC__CRITICAL_REGS_LOCK__SHIFT 0xa 5501 #define PCTL_SLICE0_MISC__TILE_IDLE_THRESHOLD__SHIFT 0xb 5502 #define PCTL_SLICE0_MISC__RENG_MEM_LS_ENABLE__SHIFT 0xe 5503 #define PCTL_SLICE0_MISC__STCTRL_FORCE_PGFSM_CMD_DONE__SHIFT 0xf 5504 #define PCTL_SLICE0_MISC__DEEPSLEEP_DISCSDP__SHIFT 0x10 5505 #define PCTL_SLICE0_MISC__RENG_EXECUTE_ON_REG_UPDATE__SHIFT 0x11 5506 #define PCTL_SLICE0_MISC__RD_TIMER_ENABLE__SHIFT 0x12 5507 #define PCTL_SLICE0_MISC__OVR_EA_SDP0_PARTACK__SHIFT 0x13 5508 #define PCTL_SLICE0_MISC__OVR_EA_SDP0_FULLACK__SHIFT 0x14 5509 #define PCTL_SLICE0_MISC__CRITICAL_REGS_LOCK_MASK 0x00000400L 5510 #define PCTL_SLICE0_MISC__TILE_IDLE_THRESHOLD_MASK 0x00003800L 5511 #define PCTL_SLICE0_MISC__RENG_MEM_LS_ENABLE_MASK 0x00004000L 5512 #define PCTL_SLICE0_MISC__STCTRL_FORCE_PGFSM_CMD_DONE_MASK 0x00008000L 5513 #define PCTL_SLICE0_MISC__DEEPSLEEP_DISCSDP_MASK 0x00010000L 5514 #define PCTL_SLICE0_MISC__RENG_EXECUTE_ON_REG_UPDATE_MASK 0x00020000L 5515 #define PCTL_SLICE0_MISC__RD_TIMER_ENABLE_MASK 0x00040000L 5516 #define PCTL_SLICE0_MISC__OVR_EA_SDP0_PARTACK_MASK 0x00080000L 5517 #define PCTL_SLICE0_MISC__OVR_EA_SDP0_FULLACK_MASK 0x00100000L 5518 //PCTL_SLICE1_MISC 5519 #define PCTL_SLICE1_MISC__CRITICAL_REGS_LOCK__SHIFT 0xa 5520 #define PCTL_SLICE1_MISC__TILE_IDLE_THRESHOLD__SHIFT 0xb 5521 #define PCTL_SLICE1_MISC__RENG_MEM_LS_ENABLE__SHIFT 0xe 5522 #define PCTL_SLICE1_MISC__STCTRL_FORCE_PGFSM_CMD_DONE__SHIFT 0xf 5523 #define PCTL_SLICE1_MISC__DEEPSLEEP_DISCSDP__SHIFT 0x10 5524 #define PCTL_SLICE1_MISC__RENG_EXECUTE_ON_REG_UPDATE__SHIFT 0x11 5525 #define PCTL_SLICE1_MISC__RD_TIMER_ENABLE__SHIFT 0x12 5526 #define PCTL_SLICE1_MISC__OVR_EA_SDP1_PARTACK__SHIFT 0x13 5527 #define PCTL_SLICE1_MISC__OVR_EA_SDP1_FULLACK__SHIFT 0x14 5528 #define PCTL_SLICE1_MISC__CRITICAL_REGS_LOCK_MASK 0x00000400L 5529 #define PCTL_SLICE1_MISC__TILE_IDLE_THRESHOLD_MASK 0x00003800L 5530 #define PCTL_SLICE1_MISC__RENG_MEM_LS_ENABLE_MASK 0x00004000L 5531 #define PCTL_SLICE1_MISC__STCTRL_FORCE_PGFSM_CMD_DONE_MASK 0x00008000L 5532 #define PCTL_SLICE1_MISC__DEEPSLEEP_DISCSDP_MASK 0x00010000L 5533 #define PCTL_SLICE1_MISC__RENG_EXECUTE_ON_REG_UPDATE_MASK 0x00020000L 5534 #define PCTL_SLICE1_MISC__RD_TIMER_ENABLE_MASK 0x00040000L 5535 #define PCTL_SLICE1_MISC__OVR_EA_SDP1_PARTACK_MASK 0x00080000L 5536 #define PCTL_SLICE1_MISC__OVR_EA_SDP1_FULLACK_MASK 0x00100000L 5537 //PCTL_RENG_CTRL 5538 #define PCTL_RENG_CTRL__RENG_EXECUTE_NOW__SHIFT 0x0 5539 #define PCTL_RENG_CTRL__RENG_EXECUTE_NOW_MODE__SHIFT 0x1 5540 #define PCTL_RENG_CTRL__RENG_EXECUTE_NOW_MASK 0x00000001L 5541 #define PCTL_RENG_CTRL__RENG_EXECUTE_NOW_MODE_MASK 0x00000002L 5542 //PCTL_UTCL2_RENG_EXECUTE 5543 #define PCTL_UTCL2_RENG_EXECUTE__RENG_EXECUTE_NOW__SHIFT 0x0 5544 #define PCTL_UTCL2_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE__SHIFT 0x1 5545 #define PCTL_UTCL2_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR__SHIFT 0x2 5546 #define PCTL_UTCL2_RENG_EXECUTE__RENG_EXECUTE_END_PTR__SHIFT 0xd 5547 #define PCTL_UTCL2_RENG_EXECUTE__RENG_EXECUTE_NOW_MASK 0x00000001L 5548 #define PCTL_UTCL2_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE_MASK 0x00000002L 5549 #define PCTL_UTCL2_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR_MASK 0x00001FFCL 5550 #define PCTL_UTCL2_RENG_EXECUTE__RENG_EXECUTE_END_PTR_MASK 0x00FFE000L 5551 //PCTL_SLICE0_RENG_EXECUTE 5552 #define PCTL_SLICE0_RENG_EXECUTE__RENG_EXECUTE_NOW__SHIFT 0x0 5553 #define PCTL_SLICE0_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE__SHIFT 0x1 5554 #define PCTL_SLICE0_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR__SHIFT 0x2 5555 #define PCTL_SLICE0_RENG_EXECUTE__RENG_EXECUTE_END_PTR__SHIFT 0xc 5556 #define PCTL_SLICE0_RENG_EXECUTE__RENG_EXECUTE_NOW_MASK 0x00000001L 5557 #define PCTL_SLICE0_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE_MASK 0x00000002L 5558 #define PCTL_SLICE0_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR_MASK 0x00000FFCL 5559 #define PCTL_SLICE0_RENG_EXECUTE__RENG_EXECUTE_END_PTR_MASK 0x003FF000L 5560 //PCTL_SLICE1_RENG_EXECUTE 5561 #define PCTL_SLICE1_RENG_EXECUTE__RENG_EXECUTE_NOW__SHIFT 0x0 5562 #define PCTL_SLICE1_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE__SHIFT 0x1 5563 #define PCTL_SLICE1_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR__SHIFT 0x2 5564 #define PCTL_SLICE1_RENG_EXECUTE__RENG_EXECUTE_END_PTR__SHIFT 0xc 5565 #define PCTL_SLICE1_RENG_EXECUTE__RENG_EXECUTE_NOW_MASK 0x00000001L 5566 #define PCTL_SLICE1_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE_MASK 0x00000002L 5567 #define PCTL_SLICE1_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR_MASK 0x00000FFCL 5568 #define PCTL_SLICE1_RENG_EXECUTE__RENG_EXECUTE_END_PTR_MASK 0x003FF000L 5569 //PCTL_UTCL2_RENG_RAM_INDEX 5570 #define PCTL_UTCL2_RENG_RAM_INDEX__RENG_RAM_INDEX__SHIFT 0x0 5571 #define PCTL_UTCL2_RENG_RAM_INDEX__RENG_RAM_INDEX_MASK 0x000007FFL 5572 //PCTL_UTCL2_RENG_RAM_DATA 5573 #define PCTL_UTCL2_RENG_RAM_DATA__RENG_RAM_DATA__SHIFT 0x0 5574 #define PCTL_UTCL2_RENG_RAM_DATA__RENG_RAM_DATA_MASK 0xFFFFFFFFL 5575 //PCTL_SLICE0_RENG_RAM_INDEX 5576 #define PCTL_SLICE0_RENG_RAM_INDEX__RENG_RAM_INDEX__SHIFT 0x0 5577 #define PCTL_SLICE0_RENG_RAM_INDEX__RENG_RAM_INDEX_MASK 0x000003FFL 5578 //PCTL_SLICE0_RENG_RAM_DATA 5579 #define PCTL_SLICE0_RENG_RAM_DATA__RENG_RAM_DATA__SHIFT 0x0 5580 #define PCTL_SLICE0_RENG_RAM_DATA__RENG_RAM_DATA_MASK 0xFFFFFFFFL 5581 //PCTL_SLICE1_RENG_RAM_INDEX 5582 #define PCTL_SLICE1_RENG_RAM_INDEX__RENG_RAM_INDEX__SHIFT 0x0 5583 #define PCTL_SLICE1_RENG_RAM_INDEX__RENG_RAM_INDEX_MASK 0x000003FFL 5584 //PCTL_SLICE1_RENG_RAM_DATA 5585 #define PCTL_SLICE1_RENG_RAM_DATA__RENG_RAM_DATA__SHIFT 0x0 5586 #define PCTL_SLICE1_RENG_RAM_DATA__RENG_RAM_DATA_MASK 0xFFFFFFFFL 5587 //PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE0 5588 #define PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 5589 #define PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 5590 #define PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL 5591 #define PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L 5592 //PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE1 5593 #define PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 5594 #define PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 5595 #define PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL 5596 #define PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L 5597 //PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE2 5598 #define PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 5599 #define PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 5600 #define PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL 5601 #define PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L 5602 //PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE3 5603 #define PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 5604 #define PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 5605 #define PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL 5606 #define PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L 5607 //PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE4 5608 #define PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 5609 #define PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 5610 #define PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL 5611 #define PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L 5612 //PCTL_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET0 5613 #define PCTL_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL0__SHIFT 0x0 5614 #define PCTL_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL1__SHIFT 0x10 5615 #define PCTL_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL0_MASK 0x0000FFFFL 5616 #define PCTL_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL1_MASK 0xFFFF0000L 5617 //PCTL_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET1 5618 #define PCTL_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL2__SHIFT 0x0 5619 #define PCTL_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL3__SHIFT 0x10 5620 #define PCTL_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL2_MASK 0x0000FFFFL 5621 #define PCTL_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL3_MASK 0xFFFF0000L 5622 //PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE0 5623 #define PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 5624 #define PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 5625 #define PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL 5626 #define PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L 5627 //PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE1 5628 #define PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 5629 #define PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 5630 #define PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL 5631 #define PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L 5632 //PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE2 5633 #define PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 5634 #define PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 5635 #define PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL 5636 #define PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L 5637 //PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE3 5638 #define PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 5639 #define PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 5640 #define PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL 5641 #define PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L 5642 //PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE4 5643 #define PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 5644 #define PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 5645 #define PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL 5646 #define PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L 5647 //PCTL_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET0 5648 #define PCTL_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL0__SHIFT 0x0 5649 #define PCTL_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL1__SHIFT 0x10 5650 #define PCTL_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL0_MASK 0x0000FFFFL 5651 #define PCTL_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL1_MASK 0xFFFF0000L 5652 //PCTL_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET1 5653 #define PCTL_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL2__SHIFT 0x0 5654 #define PCTL_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL3__SHIFT 0x10 5655 #define PCTL_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL2_MASK 0x0000FFFFL 5656 #define PCTL_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL3_MASK 0xFFFF0000L 5657 //PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE0 5658 #define PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 5659 #define PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 5660 #define PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL 5661 #define PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L 5662 //PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE1 5663 #define PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 5664 #define PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 5665 #define PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL 5666 #define PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L 5667 //PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE2 5668 #define PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 5669 #define PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 5670 #define PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL 5671 #define PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L 5672 //PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE3 5673 #define PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 5674 #define PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 5675 #define PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL 5676 #define PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L 5677 //PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE4 5678 #define PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 5679 #define PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 5680 #define PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL 5681 #define PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L 5682 //PCTL_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET0 5683 #define PCTL_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL0__SHIFT 0x0 5684 #define PCTL_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL1__SHIFT 0x10 5685 #define PCTL_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL0_MASK 0x0000FFFFL 5686 #define PCTL_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL1_MASK 0xFFFF0000L 5687 //PCTL_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET1 5688 #define PCTL_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL2__SHIFT 0x0 5689 #define PCTL_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL3__SHIFT 0x10 5690 #define PCTL_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL2_MASK 0x0000FFFFL 5691 #define PCTL_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL3_MASK 0xFFFF0000L 5692 //PCTL_STATUS 5693 #define PCTL_STATUS__PGFSM_CMD_STATUS__SHIFT 0x0 5694 #define PCTL_STATUS__MMHUB_POWER__SHIFT 0xb 5695 #define PCTL_STATUS__UTCL2_RENG_RAM_STALE__SHIFT 0xc 5696 #define PCTL_STATUS__SLICE0_RENG_RAM_STALE__SHIFT 0xd 5697 #define PCTL_STATUS__SLICE1_RENG_RAM_STALE__SHIFT 0xe 5698 #define PCTL_STATUS__PGFSM_CMD_STATUS_MASK 0x00000003L 5699 #define PCTL_STATUS__MMHUB_POWER_MASK 0x00000800L 5700 #define PCTL_STATUS__UTCL2_RENG_RAM_STALE_MASK 0x00001000L 5701 #define PCTL_STATUS__SLICE0_RENG_RAM_STALE_MASK 0x00002000L 5702 #define PCTL_STATUS__SLICE1_RENG_RAM_STALE_MASK 0x00004000L 5703 //PCTL_PERFCOUNTER_LO 5704 #define PCTL_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 5705 #define PCTL_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL 5706 //PCTL_PERFCOUNTER_HI 5707 #define PCTL_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 5708 #define PCTL_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 5709 #define PCTL_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL 5710 #define PCTL_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L 5711 //PCTL_PERFCOUNTER0_CFG 5712 #define PCTL_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 5713 #define PCTL_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 5714 #define PCTL_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 5715 #define PCTL_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c 5716 #define PCTL_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d 5717 #define PCTL_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL 5718 #define PCTL_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L 5719 #define PCTL_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L 5720 #define PCTL_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L 5721 #define PCTL_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L 5722 //PCTL_PERFCOUNTER1_CFG 5723 #define PCTL_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 5724 #define PCTL_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 5725 #define PCTL_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 5726 #define PCTL_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c 5727 #define PCTL_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d 5728 #define PCTL_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL 5729 #define PCTL_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L 5730 #define PCTL_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L 5731 #define PCTL_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L 5732 #define PCTL_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L 5733 //PCTL_PERFCOUNTER_RSLT_CNTL 5734 #define PCTL_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 5735 #define PCTL_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 5736 #define PCTL_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 5737 #define PCTL_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 5738 #define PCTL_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 5739 #define PCTL_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a 5740 #define PCTL_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL 5741 #define PCTL_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L 5742 #define PCTL_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L 5743 #define PCTL_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L 5744 #define PCTL_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L 5745 #define PCTL_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L 5746 //PCTL_RESERVED_0 5747 #define PCTL_RESERVED_0__WORD__SHIFT 0x0 5748 #define PCTL_RESERVED_0__BYTE__SHIFT 0x10 5749 #define PCTL_RESERVED_0__BIT7__SHIFT 0x18 5750 #define PCTL_RESERVED_0__BIT6__SHIFT 0x19 5751 #define PCTL_RESERVED_0__BIT5__SHIFT 0x1a 5752 #define PCTL_RESERVED_0__BIT4__SHIFT 0x1b 5753 #define PCTL_RESERVED_0__BIT3__SHIFT 0x1c 5754 #define PCTL_RESERVED_0__BIT2__SHIFT 0x1d 5755 #define PCTL_RESERVED_0__BIT1__SHIFT 0x1e 5756 #define PCTL_RESERVED_0__BIT0__SHIFT 0x1f 5757 #define PCTL_RESERVED_0__WORD_MASK 0x0000FFFFL 5758 #define PCTL_RESERVED_0__BYTE_MASK 0x00FF0000L 5759 #define PCTL_RESERVED_0__BIT7_MASK 0x01000000L 5760 #define PCTL_RESERVED_0__BIT6_MASK 0x02000000L 5761 #define PCTL_RESERVED_0__BIT5_MASK 0x04000000L 5762 #define PCTL_RESERVED_0__BIT4_MASK 0x08000000L 5763 #define PCTL_RESERVED_0__BIT3_MASK 0x10000000L 5764 #define PCTL_RESERVED_0__BIT2_MASK 0x20000000L 5765 #define PCTL_RESERVED_0__BIT1_MASK 0x40000000L 5766 #define PCTL_RESERVED_0__BIT0_MASK 0x80000000L 5767 //PCTL_RESERVED_1 5768 #define PCTL_RESERVED_1__WORD__SHIFT 0x0 5769 #define PCTL_RESERVED_1__BYTE__SHIFT 0x10 5770 #define PCTL_RESERVED_1__BIT7__SHIFT 0x18 5771 #define PCTL_RESERVED_1__BIT6__SHIFT 0x19 5772 #define PCTL_RESERVED_1__BIT5__SHIFT 0x1a 5773 #define PCTL_RESERVED_1__BIT4__SHIFT 0x1b 5774 #define PCTL_RESERVED_1__BIT3__SHIFT 0x1c 5775 #define PCTL_RESERVED_1__BIT2__SHIFT 0x1d 5776 #define PCTL_RESERVED_1__BIT1__SHIFT 0x1e 5777 #define PCTL_RESERVED_1__BIT0__SHIFT 0x1f 5778 #define PCTL_RESERVED_1__WORD_MASK 0x0000FFFFL 5779 #define PCTL_RESERVED_1__BYTE_MASK 0x00FF0000L 5780 #define PCTL_RESERVED_1__BIT7_MASK 0x01000000L 5781 #define PCTL_RESERVED_1__BIT6_MASK 0x02000000L 5782 #define PCTL_RESERVED_1__BIT5_MASK 0x04000000L 5783 #define PCTL_RESERVED_1__BIT4_MASK 0x08000000L 5784 #define PCTL_RESERVED_1__BIT3_MASK 0x10000000L 5785 #define PCTL_RESERVED_1__BIT2_MASK 0x20000000L 5786 #define PCTL_RESERVED_1__BIT1_MASK 0x40000000L 5787 #define PCTL_RESERVED_1__BIT0_MASK 0x80000000L 5788 //PCTL_RESERVED_2 5789 #define PCTL_RESERVED_2__WORD__SHIFT 0x0 5790 #define PCTL_RESERVED_2__BYTE__SHIFT 0x10 5791 #define PCTL_RESERVED_2__BIT7__SHIFT 0x18 5792 #define PCTL_RESERVED_2__BIT6__SHIFT 0x19 5793 #define PCTL_RESERVED_2__BIT5__SHIFT 0x1a 5794 #define PCTL_RESERVED_2__BIT4__SHIFT 0x1b 5795 #define PCTL_RESERVED_2__BIT3__SHIFT 0x1c 5796 #define PCTL_RESERVED_2__BIT2__SHIFT 0x1d 5797 #define PCTL_RESERVED_2__BIT1__SHIFT 0x1e 5798 #define PCTL_RESERVED_2__BIT0__SHIFT 0x1f 5799 #define PCTL_RESERVED_2__WORD_MASK 0x0000FFFFL 5800 #define PCTL_RESERVED_2__BYTE_MASK 0x00FF0000L 5801 #define PCTL_RESERVED_2__BIT7_MASK 0x01000000L 5802 #define PCTL_RESERVED_2__BIT6_MASK 0x02000000L 5803 #define PCTL_RESERVED_2__BIT5_MASK 0x04000000L 5804 #define PCTL_RESERVED_2__BIT4_MASK 0x08000000L 5805 #define PCTL_RESERVED_2__BIT3_MASK 0x10000000L 5806 #define PCTL_RESERVED_2__BIT2_MASK 0x20000000L 5807 #define PCTL_RESERVED_2__BIT1_MASK 0x40000000L 5808 #define PCTL_RESERVED_2__BIT0_MASK 0x80000000L 5809 //PCTL_RESERVED_3 5810 #define PCTL_RESERVED_3__WORD__SHIFT 0x0 5811 #define PCTL_RESERVED_3__BYTE__SHIFT 0x10 5812 #define PCTL_RESERVED_3__BIT7__SHIFT 0x18 5813 #define PCTL_RESERVED_3__BIT6__SHIFT 0x19 5814 #define PCTL_RESERVED_3__BIT5__SHIFT 0x1a 5815 #define PCTL_RESERVED_3__BIT4__SHIFT 0x1b 5816 #define PCTL_RESERVED_3__BIT3__SHIFT 0x1c 5817 #define PCTL_RESERVED_3__BIT2__SHIFT 0x1d 5818 #define PCTL_RESERVED_3__BIT1__SHIFT 0x1e 5819 #define PCTL_RESERVED_3__BIT0__SHIFT 0x1f 5820 #define PCTL_RESERVED_3__WORD_MASK 0x0000FFFFL 5821 #define PCTL_RESERVED_3__BYTE_MASK 0x00FF0000L 5822 #define PCTL_RESERVED_3__BIT7_MASK 0x01000000L 5823 #define PCTL_RESERVED_3__BIT6_MASK 0x02000000L 5824 #define PCTL_RESERVED_3__BIT5_MASK 0x04000000L 5825 #define PCTL_RESERVED_3__BIT4_MASK 0x08000000L 5826 #define PCTL_RESERVED_3__BIT3_MASK 0x10000000L 5827 #define PCTL_RESERVED_3__BIT2_MASK 0x20000000L 5828 #define PCTL_RESERVED_3__BIT1_MASK 0x40000000L 5829 #define PCTL_RESERVED_3__BIT0_MASK 0x80000000L 5830 5831 5832 // addressBlock: mmhub_l1tlb_mmutcl1pfdec 5833 //MMMC_VM_MX_L1_TLB0_STATUS 5834 #define MMMC_VM_MX_L1_TLB0_STATUS__BUSY__SHIFT 0x0 5835 #define MMMC_VM_MX_L1_TLB0_STATUS__FOUND_PARITY_ERRORS__SHIFT 0x1 5836 #define MMMC_VM_MX_L1_TLB0_STATUS__BUSY_MASK 0x00000001L 5837 #define MMMC_VM_MX_L1_TLB0_STATUS__FOUND_PARITY_ERRORS_MASK 0x00000002L 5838 //MMMC_VM_MX_L1_TLB1_STATUS 5839 #define MMMC_VM_MX_L1_TLB1_STATUS__BUSY__SHIFT 0x0 5840 #define MMMC_VM_MX_L1_TLB1_STATUS__FOUND_PARITY_ERRORS__SHIFT 0x1 5841 #define MMMC_VM_MX_L1_TLB1_STATUS__BUSY_MASK 0x00000001L 5842 #define MMMC_VM_MX_L1_TLB1_STATUS__FOUND_PARITY_ERRORS_MASK 0x00000002L 5843 //MMMC_VM_MX_L1_TLB2_STATUS 5844 #define MMMC_VM_MX_L1_TLB2_STATUS__BUSY__SHIFT 0x0 5845 #define MMMC_VM_MX_L1_TLB2_STATUS__FOUND_PARITY_ERRORS__SHIFT 0x1 5846 #define MMMC_VM_MX_L1_TLB2_STATUS__BUSY_MASK 0x00000001L 5847 #define MMMC_VM_MX_L1_TLB2_STATUS__FOUND_PARITY_ERRORS_MASK 0x00000002L 5848 //MMMC_VM_MX_L1_TLB3_STATUS 5849 #define MMMC_VM_MX_L1_TLB3_STATUS__BUSY__SHIFT 0x0 5850 #define MMMC_VM_MX_L1_TLB3_STATUS__FOUND_PARITY_ERRORS__SHIFT 0x1 5851 #define MMMC_VM_MX_L1_TLB3_STATUS__BUSY_MASK 0x00000001L 5852 #define MMMC_VM_MX_L1_TLB3_STATUS__FOUND_PARITY_ERRORS_MASK 0x00000002L 5853 //MMMC_VM_MX_L1_TLB4_STATUS 5854 #define MMMC_VM_MX_L1_TLB4_STATUS__BUSY__SHIFT 0x0 5855 #define MMMC_VM_MX_L1_TLB4_STATUS__FOUND_PARITY_ERRORS__SHIFT 0x1 5856 #define MMMC_VM_MX_L1_TLB4_STATUS__BUSY_MASK 0x00000001L 5857 #define MMMC_VM_MX_L1_TLB4_STATUS__FOUND_PARITY_ERRORS_MASK 0x00000002L 5858 //MMMC_VM_MX_L1_TLB5_STATUS 5859 #define MMMC_VM_MX_L1_TLB5_STATUS__BUSY__SHIFT 0x0 5860 #define MMMC_VM_MX_L1_TLB5_STATUS__FOUND_PARITY_ERRORS__SHIFT 0x1 5861 #define MMMC_VM_MX_L1_TLB5_STATUS__BUSY_MASK 0x00000001L 5862 #define MMMC_VM_MX_L1_TLB5_STATUS__FOUND_PARITY_ERRORS_MASK 0x00000002L 5863 //MMMC_VM_MX_L1_TLB6_STATUS 5864 #define MMMC_VM_MX_L1_TLB6_STATUS__BUSY__SHIFT 0x0 5865 #define MMMC_VM_MX_L1_TLB6_STATUS__FOUND_PARITY_ERRORS__SHIFT 0x1 5866 #define MMMC_VM_MX_L1_TLB6_STATUS__BUSY_MASK 0x00000001L 5867 #define MMMC_VM_MX_L1_TLB6_STATUS__FOUND_PARITY_ERRORS_MASK 0x00000002L 5868 //MMMC_VM_MX_L1_TLB7_STATUS 5869 #define MMMC_VM_MX_L1_TLB7_STATUS__BUSY__SHIFT 0x0 5870 #define MMMC_VM_MX_L1_TLB7_STATUS__FOUND_PARITY_ERRORS__SHIFT 0x1 5871 #define MMMC_VM_MX_L1_TLB7_STATUS__BUSY_MASK 0x00000001L 5872 #define MMMC_VM_MX_L1_TLB7_STATUS__FOUND_PARITY_ERRORS_MASK 0x00000002L 5873 5874 5875 // addressBlock: mmhub_l1tlb_mmutcl1pldec 5876 //MMMC_VM_MX_L1_PERFCOUNTER0_CFG 5877 #define MMMC_VM_MX_L1_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 5878 #define MMMC_VM_MX_L1_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 5879 #define MMMC_VM_MX_L1_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 5880 #define MMMC_VM_MX_L1_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c 5881 #define MMMC_VM_MX_L1_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d 5882 #define MMMC_VM_MX_L1_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL 5883 #define MMMC_VM_MX_L1_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L 5884 #define MMMC_VM_MX_L1_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L 5885 #define MMMC_VM_MX_L1_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L 5886 #define MMMC_VM_MX_L1_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L 5887 //MMMC_VM_MX_L1_PERFCOUNTER1_CFG 5888 #define MMMC_VM_MX_L1_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 5889 #define MMMC_VM_MX_L1_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 5890 #define MMMC_VM_MX_L1_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 5891 #define MMMC_VM_MX_L1_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c 5892 #define MMMC_VM_MX_L1_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d 5893 #define MMMC_VM_MX_L1_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL 5894 #define MMMC_VM_MX_L1_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L 5895 #define MMMC_VM_MX_L1_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L 5896 #define MMMC_VM_MX_L1_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L 5897 #define MMMC_VM_MX_L1_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L 5898 //MMMC_VM_MX_L1_PERFCOUNTER2_CFG 5899 #define MMMC_VM_MX_L1_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0 5900 #define MMMC_VM_MX_L1_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8 5901 #define MMMC_VM_MX_L1_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18 5902 #define MMMC_VM_MX_L1_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c 5903 #define MMMC_VM_MX_L1_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d 5904 #define MMMC_VM_MX_L1_PERFCOUNTER2_CFG__PERF_SEL_MASK 0x000000FFL 5905 #define MMMC_VM_MX_L1_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0x0000FF00L 5906 #define MMMC_VM_MX_L1_PERFCOUNTER2_CFG__PERF_MODE_MASK 0x0F000000L 5907 #define MMMC_VM_MX_L1_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000L 5908 #define MMMC_VM_MX_L1_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000L 5909 //MMMC_VM_MX_L1_PERFCOUNTER3_CFG 5910 #define MMMC_VM_MX_L1_PERFCOUNTER3_CFG__PERF_SEL__SHIFT 0x0 5911 #define MMMC_VM_MX_L1_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT 0x8 5912 #define MMMC_VM_MX_L1_PERFCOUNTER3_CFG__PERF_MODE__SHIFT 0x18 5913 #define MMMC_VM_MX_L1_PERFCOUNTER3_CFG__ENABLE__SHIFT 0x1c 5914 #define MMMC_VM_MX_L1_PERFCOUNTER3_CFG__CLEAR__SHIFT 0x1d 5915 #define MMMC_VM_MX_L1_PERFCOUNTER3_CFG__PERF_SEL_MASK 0x000000FFL 5916 #define MMMC_VM_MX_L1_PERFCOUNTER3_CFG__PERF_SEL_END_MASK 0x0000FF00L 5917 #define MMMC_VM_MX_L1_PERFCOUNTER3_CFG__PERF_MODE_MASK 0x0F000000L 5918 #define MMMC_VM_MX_L1_PERFCOUNTER3_CFG__ENABLE_MASK 0x10000000L 5919 #define MMMC_VM_MX_L1_PERFCOUNTER3_CFG__CLEAR_MASK 0x20000000L 5920 //MMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL 5921 #define MMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 5922 #define MMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 5923 #define MMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 5924 #define MMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 5925 #define MMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 5926 #define MMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a 5927 #define MMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL 5928 #define MMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L 5929 #define MMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L 5930 #define MMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L 5931 #define MMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L 5932 #define MMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L 5933 5934 5935 // addressBlock: mmhub_l1tlb_mmutcl1prdec 5936 //MMMC_VM_MX_L1_PERFCOUNTER_LO 5937 #define MMMC_VM_MX_L1_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 5938 #define MMMC_VM_MX_L1_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL 5939 //MMMC_VM_MX_L1_PERFCOUNTER_HI 5940 #define MMMC_VM_MX_L1_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 5941 #define MMMC_VM_MX_L1_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 5942 #define MMMC_VM_MX_L1_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL 5943 #define MMMC_VM_MX_L1_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L 5944 5945 5946 // addressBlock: mmhub_l1tlb_mmvmtlspfdec 5947 //MMMC_VM_MX_L1_TLS0_CNTL 5948 #define MMMC_VM_MX_L1_TLS0_CNTL__PREFETCH_COUNT__SHIFT 0x0 5949 #define MMMC_VM_MX_L1_TLS0_CNTL__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x4 5950 #define MMMC_VM_MX_L1_TLS0_CNTL__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES__SHIFT 0x5 5951 #define MMMC_VM_MX_L1_TLS0_CNTL__IOMGR_SNOOP_SELECT__SHIFT 0x6 5952 #define MMMC_VM_MX_L1_TLS0_CNTL__IOMGR_DEFAULT_SYSTEM__SHIFT 0x8 5953 #define MMMC_VM_MX_L1_TLS0_CNTL__IOMGR_DEFAULT_SNOOP__SHIFT 0x9 5954 #define MMMC_VM_MX_L1_TLS0_CNTL__PREFETCH_COUNT_MASK 0x0000000FL 5955 #define MMMC_VM_MX_L1_TLS0_CNTL__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00000010L 5956 #define MMMC_VM_MX_L1_TLS0_CNTL__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES_MASK 0x00000020L 5957 #define MMMC_VM_MX_L1_TLS0_CNTL__IOMGR_SNOOP_SELECT_MASK 0x000000C0L 5958 #define MMMC_VM_MX_L1_TLS0_CNTL__IOMGR_DEFAULT_SYSTEM_MASK 0x00000100L 5959 #define MMMC_VM_MX_L1_TLS0_CNTL__IOMGR_DEFAULT_SNOOP_MASK 0x00000200L 5960 //MMMC_VM_MX_L1_TLS0_CNTL0 5961 #define MMMC_VM_MX_L1_TLS0_CNTL0__REQ_STREAM_ID__SHIFT 0x0 5962 #define MMMC_VM_MX_L1_TLS0_CNTL0__EN__SHIFT 0xc 5963 #define MMMC_VM_MX_L1_TLS0_CNTL0__PREFETCH_DONE__SHIFT 0xd 5964 #define MMMC_VM_MX_L1_TLS0_CNTL0__REQ_STREAM_ID_MASK 0x000001FFL 5965 #define MMMC_VM_MX_L1_TLS0_CNTL0__EN_MASK 0x00001000L 5966 #define MMMC_VM_MX_L1_TLS0_CNTL0__PREFETCH_DONE_MASK 0x00002000L 5967 //MMMC_VM_MX_L1_TLS0_CNTL1 5968 #define MMMC_VM_MX_L1_TLS0_CNTL1__REQ_STREAM_ID__SHIFT 0x0 5969 #define MMMC_VM_MX_L1_TLS0_CNTL1__EN__SHIFT 0xc 5970 #define MMMC_VM_MX_L1_TLS0_CNTL1__PREFETCH_DONE__SHIFT 0xd 5971 #define MMMC_VM_MX_L1_TLS0_CNTL1__REQ_STREAM_ID_MASK 0x000001FFL 5972 #define MMMC_VM_MX_L1_TLS0_CNTL1__EN_MASK 0x00001000L 5973 #define MMMC_VM_MX_L1_TLS0_CNTL1__PREFETCH_DONE_MASK 0x00002000L 5974 //MMMC_VM_MX_L1_TLS0_CNTL2 5975 #define MMMC_VM_MX_L1_TLS0_CNTL2__REQ_STREAM_ID__SHIFT 0x0 5976 #define MMMC_VM_MX_L1_TLS0_CNTL2__EN__SHIFT 0xc 5977 #define MMMC_VM_MX_L1_TLS0_CNTL2__PREFETCH_DONE__SHIFT 0xd 5978 #define MMMC_VM_MX_L1_TLS0_CNTL2__REQ_STREAM_ID_MASK 0x000001FFL 5979 #define MMMC_VM_MX_L1_TLS0_CNTL2__EN_MASK 0x00001000L 5980 #define MMMC_VM_MX_L1_TLS0_CNTL2__PREFETCH_DONE_MASK 0x00002000L 5981 //MMMC_VM_MX_L1_TLS0_CNTL3 5982 #define MMMC_VM_MX_L1_TLS0_CNTL3__REQ_STREAM_ID__SHIFT 0x0 5983 #define MMMC_VM_MX_L1_TLS0_CNTL3__EN__SHIFT 0xc 5984 #define MMMC_VM_MX_L1_TLS0_CNTL3__PREFETCH_DONE__SHIFT 0xd 5985 #define MMMC_VM_MX_L1_TLS0_CNTL3__REQ_STREAM_ID_MASK 0x000001FFL 5986 #define MMMC_VM_MX_L1_TLS0_CNTL3__EN_MASK 0x00001000L 5987 #define MMMC_VM_MX_L1_TLS0_CNTL3__PREFETCH_DONE_MASK 0x00002000L 5988 //MMMC_VM_MX_L1_TLS0_CNTL4 5989 #define MMMC_VM_MX_L1_TLS0_CNTL4__REQ_STREAM_ID__SHIFT 0x0 5990 #define MMMC_VM_MX_L1_TLS0_CNTL4__EN__SHIFT 0xc 5991 #define MMMC_VM_MX_L1_TLS0_CNTL4__PREFETCH_DONE__SHIFT 0xd 5992 #define MMMC_VM_MX_L1_TLS0_CNTL4__REQ_STREAM_ID_MASK 0x000001FFL 5993 #define MMMC_VM_MX_L1_TLS0_CNTL4__EN_MASK 0x00001000L 5994 #define MMMC_VM_MX_L1_TLS0_CNTL4__PREFETCH_DONE_MASK 0x00002000L 5995 //MMMC_VM_MX_L1_TLS0_CNTL5 5996 #define MMMC_VM_MX_L1_TLS0_CNTL5__REQ_STREAM_ID__SHIFT 0x0 5997 #define MMMC_VM_MX_L1_TLS0_CNTL5__EN__SHIFT 0xc 5998 #define MMMC_VM_MX_L1_TLS0_CNTL5__PREFETCH_DONE__SHIFT 0xd 5999 #define MMMC_VM_MX_L1_TLS0_CNTL5__REQ_STREAM_ID_MASK 0x000001FFL 6000 #define MMMC_VM_MX_L1_TLS0_CNTL5__EN_MASK 0x00001000L 6001 #define MMMC_VM_MX_L1_TLS0_CNTL5__PREFETCH_DONE_MASK 0x00002000L 6002 //MMMC_VM_MX_L1_TLS0_CNTL6 6003 #define MMMC_VM_MX_L1_TLS0_CNTL6__REQ_STREAM_ID__SHIFT 0x0 6004 #define MMMC_VM_MX_L1_TLS0_CNTL6__EN__SHIFT 0xc 6005 #define MMMC_VM_MX_L1_TLS0_CNTL6__PREFETCH_DONE__SHIFT 0xd 6006 #define MMMC_VM_MX_L1_TLS0_CNTL6__REQ_STREAM_ID_MASK 0x000001FFL 6007 #define MMMC_VM_MX_L1_TLS0_CNTL6__EN_MASK 0x00001000L 6008 #define MMMC_VM_MX_L1_TLS0_CNTL6__PREFETCH_DONE_MASK 0x00002000L 6009 //MMMC_VM_MX_L1_TLS0_CNTL7 6010 #define MMMC_VM_MX_L1_TLS0_CNTL7__REQ_STREAM_ID__SHIFT 0x0 6011 #define MMMC_VM_MX_L1_TLS0_CNTL7__EN__SHIFT 0xc 6012 #define MMMC_VM_MX_L1_TLS0_CNTL7__PREFETCH_DONE__SHIFT 0xd 6013 #define MMMC_VM_MX_L1_TLS0_CNTL7__REQ_STREAM_ID_MASK 0x000001FFL 6014 #define MMMC_VM_MX_L1_TLS0_CNTL7__EN_MASK 0x00001000L 6015 #define MMMC_VM_MX_L1_TLS0_CNTL7__PREFETCH_DONE_MASK 0x00002000L 6016 //MMMC_VM_MX_L1_TLS0_CNTL8 6017 #define MMMC_VM_MX_L1_TLS0_CNTL8__REQ_STREAM_ID__SHIFT 0x0 6018 #define MMMC_VM_MX_L1_TLS0_CNTL8__EN__SHIFT 0xc 6019 #define MMMC_VM_MX_L1_TLS0_CNTL8__PREFETCH_DONE__SHIFT 0xd 6020 #define MMMC_VM_MX_L1_TLS0_CNTL8__REQ_STREAM_ID_MASK 0x000001FFL 6021 #define MMMC_VM_MX_L1_TLS0_CNTL8__EN_MASK 0x00001000L 6022 #define MMMC_VM_MX_L1_TLS0_CNTL8__PREFETCH_DONE_MASK 0x00002000L 6023 //MMMC_VM_MX_L1_TLS0_CNTL9 6024 #define MMMC_VM_MX_L1_TLS0_CNTL9__REQ_STREAM_ID__SHIFT 0x0 6025 #define MMMC_VM_MX_L1_TLS0_CNTL9__EN__SHIFT 0xc 6026 #define MMMC_VM_MX_L1_TLS0_CNTL9__PREFETCH_DONE__SHIFT 0xd 6027 #define MMMC_VM_MX_L1_TLS0_CNTL9__REQ_STREAM_ID_MASK 0x000001FFL 6028 #define MMMC_VM_MX_L1_TLS0_CNTL9__EN_MASK 0x00001000L 6029 #define MMMC_VM_MX_L1_TLS0_CNTL9__PREFETCH_DONE_MASK 0x00002000L 6030 //MMMC_VM_MX_L1_TLS0_CNTL10 6031 #define MMMC_VM_MX_L1_TLS0_CNTL10__REQ_STREAM_ID__SHIFT 0x0 6032 #define MMMC_VM_MX_L1_TLS0_CNTL10__EN__SHIFT 0xc 6033 #define MMMC_VM_MX_L1_TLS0_CNTL10__PREFETCH_DONE__SHIFT 0xd 6034 #define MMMC_VM_MX_L1_TLS0_CNTL10__REQ_STREAM_ID_MASK 0x000001FFL 6035 #define MMMC_VM_MX_L1_TLS0_CNTL10__EN_MASK 0x00001000L 6036 #define MMMC_VM_MX_L1_TLS0_CNTL10__PREFETCH_DONE_MASK 0x00002000L 6037 //MMMC_VM_MX_L1_TLS0_CNTL11 6038 #define MMMC_VM_MX_L1_TLS0_CNTL11__REQ_STREAM_ID__SHIFT 0x0 6039 #define MMMC_VM_MX_L1_TLS0_CNTL11__EN__SHIFT 0xc 6040 #define MMMC_VM_MX_L1_TLS0_CNTL11__PREFETCH_DONE__SHIFT 0xd 6041 #define MMMC_VM_MX_L1_TLS0_CNTL11__REQ_STREAM_ID_MASK 0x000001FFL 6042 #define MMMC_VM_MX_L1_TLS0_CNTL11__EN_MASK 0x00001000L 6043 #define MMMC_VM_MX_L1_TLS0_CNTL11__PREFETCH_DONE_MASK 0x00002000L 6044 //MMMC_VM_MX_L1_TLS0_CNTL12 6045 #define MMMC_VM_MX_L1_TLS0_CNTL12__REQ_STREAM_ID__SHIFT 0x0 6046 #define MMMC_VM_MX_L1_TLS0_CNTL12__EN__SHIFT 0xc 6047 #define MMMC_VM_MX_L1_TLS0_CNTL12__PREFETCH_DONE__SHIFT 0xd 6048 #define MMMC_VM_MX_L1_TLS0_CNTL12__REQ_STREAM_ID_MASK 0x000001FFL 6049 #define MMMC_VM_MX_L1_TLS0_CNTL12__EN_MASK 0x00001000L 6050 #define MMMC_VM_MX_L1_TLS0_CNTL12__PREFETCH_DONE_MASK 0x00002000L 6051 //MMMC_VM_MX_L1_TLS0_CNTL13 6052 #define MMMC_VM_MX_L1_TLS0_CNTL13__REQ_STREAM_ID__SHIFT 0x0 6053 #define MMMC_VM_MX_L1_TLS0_CNTL13__EN__SHIFT 0xc 6054 #define MMMC_VM_MX_L1_TLS0_CNTL13__PREFETCH_DONE__SHIFT 0xd 6055 #define MMMC_VM_MX_L1_TLS0_CNTL13__REQ_STREAM_ID_MASK 0x000001FFL 6056 #define MMMC_VM_MX_L1_TLS0_CNTL13__EN_MASK 0x00001000L 6057 #define MMMC_VM_MX_L1_TLS0_CNTL13__PREFETCH_DONE_MASK 0x00002000L 6058 //MMMC_VM_MX_L1_TLS0_CNTL14 6059 #define MMMC_VM_MX_L1_TLS0_CNTL14__REQ_STREAM_ID__SHIFT 0x0 6060 #define MMMC_VM_MX_L1_TLS0_CNTL14__EN__SHIFT 0xc 6061 #define MMMC_VM_MX_L1_TLS0_CNTL14__PREFETCH_DONE__SHIFT 0xd 6062 #define MMMC_VM_MX_L1_TLS0_CNTL14__REQ_STREAM_ID_MASK 0x000001FFL 6063 #define MMMC_VM_MX_L1_TLS0_CNTL14__EN_MASK 0x00001000L 6064 #define MMMC_VM_MX_L1_TLS0_CNTL14__PREFETCH_DONE_MASK 0x00002000L 6065 //MMMC_VM_MX_L1_TLS0_CNTL15 6066 #define MMMC_VM_MX_L1_TLS0_CNTL15__REQ_STREAM_ID__SHIFT 0x0 6067 #define MMMC_VM_MX_L1_TLS0_CNTL15__EN__SHIFT 0xc 6068 #define MMMC_VM_MX_L1_TLS0_CNTL15__PREFETCH_DONE__SHIFT 0xd 6069 #define MMMC_VM_MX_L1_TLS0_CNTL15__REQ_STREAM_ID_MASK 0x000001FFL 6070 #define MMMC_VM_MX_L1_TLS0_CNTL15__EN_MASK 0x00001000L 6071 #define MMMC_VM_MX_L1_TLS0_CNTL15__PREFETCH_DONE_MASK 0x00002000L 6072 //MMMC_VM_MX_L1_TLS0_CNTL16 6073 #define MMMC_VM_MX_L1_TLS0_CNTL16__REQ_STREAM_ID__SHIFT 0x0 6074 #define MMMC_VM_MX_L1_TLS0_CNTL16__EN__SHIFT 0xc 6075 #define MMMC_VM_MX_L1_TLS0_CNTL16__PREFETCH_DONE__SHIFT 0xd 6076 #define MMMC_VM_MX_L1_TLS0_CNTL16__REQ_STREAM_ID_MASK 0x000001FFL 6077 #define MMMC_VM_MX_L1_TLS0_CNTL16__EN_MASK 0x00001000L 6078 #define MMMC_VM_MX_L1_TLS0_CNTL16__PREFETCH_DONE_MASK 0x00002000L 6079 //MMMC_VM_MX_L1_TLS0_CNTL17 6080 #define MMMC_VM_MX_L1_TLS0_CNTL17__REQ_STREAM_ID__SHIFT 0x0 6081 #define MMMC_VM_MX_L1_TLS0_CNTL17__EN__SHIFT 0xc 6082 #define MMMC_VM_MX_L1_TLS0_CNTL17__PREFETCH_DONE__SHIFT 0xd 6083 #define MMMC_VM_MX_L1_TLS0_CNTL17__REQ_STREAM_ID_MASK 0x000001FFL 6084 #define MMMC_VM_MX_L1_TLS0_CNTL17__EN_MASK 0x00001000L 6085 #define MMMC_VM_MX_L1_TLS0_CNTL17__PREFETCH_DONE_MASK 0x00002000L 6086 //MMMC_VM_MX_L1_TLS0_CNTL18 6087 #define MMMC_VM_MX_L1_TLS0_CNTL18__REQ_STREAM_ID__SHIFT 0x0 6088 #define MMMC_VM_MX_L1_TLS0_CNTL18__EN__SHIFT 0xc 6089 #define MMMC_VM_MX_L1_TLS0_CNTL18__PREFETCH_DONE__SHIFT 0xd 6090 #define MMMC_VM_MX_L1_TLS0_CNTL18__REQ_STREAM_ID_MASK 0x000001FFL 6091 #define MMMC_VM_MX_L1_TLS0_CNTL18__EN_MASK 0x00001000L 6092 #define MMMC_VM_MX_L1_TLS0_CNTL18__PREFETCH_DONE_MASK 0x00002000L 6093 //MMMC_VM_MX_L1_TLS0_CNTL19 6094 #define MMMC_VM_MX_L1_TLS0_CNTL19__REQ_STREAM_ID__SHIFT 0x0 6095 #define MMMC_VM_MX_L1_TLS0_CNTL19__EN__SHIFT 0xc 6096 #define MMMC_VM_MX_L1_TLS0_CNTL19__PREFETCH_DONE__SHIFT 0xd 6097 #define MMMC_VM_MX_L1_TLS0_CNTL19__REQ_STREAM_ID_MASK 0x000001FFL 6098 #define MMMC_VM_MX_L1_TLS0_CNTL19__EN_MASK 0x00001000L 6099 #define MMMC_VM_MX_L1_TLS0_CNTL19__PREFETCH_DONE_MASK 0x00002000L 6100 //MMMC_VM_MX_L1_TLS0_CNTL20 6101 #define MMMC_VM_MX_L1_TLS0_CNTL20__REQ_STREAM_ID__SHIFT 0x0 6102 #define MMMC_VM_MX_L1_TLS0_CNTL20__EN__SHIFT 0xc 6103 #define MMMC_VM_MX_L1_TLS0_CNTL20__PREFETCH_DONE__SHIFT 0xd 6104 #define MMMC_VM_MX_L1_TLS0_CNTL20__REQ_STREAM_ID_MASK 0x000001FFL 6105 #define MMMC_VM_MX_L1_TLS0_CNTL20__EN_MASK 0x00001000L 6106 #define MMMC_VM_MX_L1_TLS0_CNTL20__PREFETCH_DONE_MASK 0x00002000L 6107 //MMMC_VM_MX_L1_TLS0_CNTL21 6108 #define MMMC_VM_MX_L1_TLS0_CNTL21__REQ_STREAM_ID__SHIFT 0x0 6109 #define MMMC_VM_MX_L1_TLS0_CNTL21__EN__SHIFT 0xc 6110 #define MMMC_VM_MX_L1_TLS0_CNTL21__PREFETCH_DONE__SHIFT 0xd 6111 #define MMMC_VM_MX_L1_TLS0_CNTL21__REQ_STREAM_ID_MASK 0x000001FFL 6112 #define MMMC_VM_MX_L1_TLS0_CNTL21__EN_MASK 0x00001000L 6113 #define MMMC_VM_MX_L1_TLS0_CNTL21__PREFETCH_DONE_MASK 0x00002000L 6114 //MMMC_VM_MX_L1_TLS0_CNTL22 6115 #define MMMC_VM_MX_L1_TLS0_CNTL22__REQ_STREAM_ID__SHIFT 0x0 6116 #define MMMC_VM_MX_L1_TLS0_CNTL22__EN__SHIFT 0xc 6117 #define MMMC_VM_MX_L1_TLS0_CNTL22__PREFETCH_DONE__SHIFT 0xd 6118 #define MMMC_VM_MX_L1_TLS0_CNTL22__REQ_STREAM_ID_MASK 0x000001FFL 6119 #define MMMC_VM_MX_L1_TLS0_CNTL22__EN_MASK 0x00001000L 6120 #define MMMC_VM_MX_L1_TLS0_CNTL22__PREFETCH_DONE_MASK 0x00002000L 6121 //MMMC_VM_MX_L1_TLS0_CNTL23 6122 #define MMMC_VM_MX_L1_TLS0_CNTL23__REQ_STREAM_ID__SHIFT 0x0 6123 #define MMMC_VM_MX_L1_TLS0_CNTL23__EN__SHIFT 0xc 6124 #define MMMC_VM_MX_L1_TLS0_CNTL23__PREFETCH_DONE__SHIFT 0xd 6125 #define MMMC_VM_MX_L1_TLS0_CNTL23__REQ_STREAM_ID_MASK 0x000001FFL 6126 #define MMMC_VM_MX_L1_TLS0_CNTL23__EN_MASK 0x00001000L 6127 #define MMMC_VM_MX_L1_TLS0_CNTL23__PREFETCH_DONE_MASK 0x00002000L 6128 //MMMC_VM_MX_L1_TLS0_CNTL24 6129 #define MMMC_VM_MX_L1_TLS0_CNTL24__REQ_STREAM_ID__SHIFT 0x0 6130 #define MMMC_VM_MX_L1_TLS0_CNTL24__EN__SHIFT 0xc 6131 #define MMMC_VM_MX_L1_TLS0_CNTL24__PREFETCH_DONE__SHIFT 0xd 6132 #define MMMC_VM_MX_L1_TLS0_CNTL24__REQ_STREAM_ID_MASK 0x000001FFL 6133 #define MMMC_VM_MX_L1_TLS0_CNTL24__EN_MASK 0x00001000L 6134 #define MMMC_VM_MX_L1_TLS0_CNTL24__PREFETCH_DONE_MASK 0x00002000L 6135 //MMMC_VM_MX_L1_TLS0_CNTL25 6136 #define MMMC_VM_MX_L1_TLS0_CNTL25__REQ_STREAM_ID__SHIFT 0x0 6137 #define MMMC_VM_MX_L1_TLS0_CNTL25__EN__SHIFT 0xc 6138 #define MMMC_VM_MX_L1_TLS0_CNTL25__PREFETCH_DONE__SHIFT 0xd 6139 #define MMMC_VM_MX_L1_TLS0_CNTL25__REQ_STREAM_ID_MASK 0x000001FFL 6140 #define MMMC_VM_MX_L1_TLS0_CNTL25__EN_MASK 0x00001000L 6141 #define MMMC_VM_MX_L1_TLS0_CNTL25__PREFETCH_DONE_MASK 0x00002000L 6142 //MMMC_VM_MX_L1_TLS0_CNTL26 6143 #define MMMC_VM_MX_L1_TLS0_CNTL26__REQ_STREAM_ID__SHIFT 0x0 6144 #define MMMC_VM_MX_L1_TLS0_CNTL26__EN__SHIFT 0xc 6145 #define MMMC_VM_MX_L1_TLS0_CNTL26__PREFETCH_DONE__SHIFT 0xd 6146 #define MMMC_VM_MX_L1_TLS0_CNTL26__REQ_STREAM_ID_MASK 0x000001FFL 6147 #define MMMC_VM_MX_L1_TLS0_CNTL26__EN_MASK 0x00001000L 6148 #define MMMC_VM_MX_L1_TLS0_CNTL26__PREFETCH_DONE_MASK 0x00002000L 6149 //MMMC_VM_MX_L1_TLS0_CNTL27 6150 #define MMMC_VM_MX_L1_TLS0_CNTL27__REQ_STREAM_ID__SHIFT 0x0 6151 #define MMMC_VM_MX_L1_TLS0_CNTL27__EN__SHIFT 0xc 6152 #define MMMC_VM_MX_L1_TLS0_CNTL27__PREFETCH_DONE__SHIFT 0xd 6153 #define MMMC_VM_MX_L1_TLS0_CNTL27__REQ_STREAM_ID_MASK 0x000001FFL 6154 #define MMMC_VM_MX_L1_TLS0_CNTL27__EN_MASK 0x00001000L 6155 #define MMMC_VM_MX_L1_TLS0_CNTL27__PREFETCH_DONE_MASK 0x00002000L 6156 //MMMC_VM_MX_L1_TLS0_CNTL28 6157 #define MMMC_VM_MX_L1_TLS0_CNTL28__REQ_STREAM_ID__SHIFT 0x0 6158 #define MMMC_VM_MX_L1_TLS0_CNTL28__EN__SHIFT 0xc 6159 #define MMMC_VM_MX_L1_TLS0_CNTL28__PREFETCH_DONE__SHIFT 0xd 6160 #define MMMC_VM_MX_L1_TLS0_CNTL28__REQ_STREAM_ID_MASK 0x000001FFL 6161 #define MMMC_VM_MX_L1_TLS0_CNTL28__EN_MASK 0x00001000L 6162 #define MMMC_VM_MX_L1_TLS0_CNTL28__PREFETCH_DONE_MASK 0x00002000L 6163 //MMMC_VM_MX_L1_TLS0_CNTL29 6164 #define MMMC_VM_MX_L1_TLS0_CNTL29__REQ_STREAM_ID__SHIFT 0x0 6165 #define MMMC_VM_MX_L1_TLS0_CNTL29__EN__SHIFT 0xc 6166 #define MMMC_VM_MX_L1_TLS0_CNTL29__PREFETCH_DONE__SHIFT 0xd 6167 #define MMMC_VM_MX_L1_TLS0_CNTL29__REQ_STREAM_ID_MASK 0x000001FFL 6168 #define MMMC_VM_MX_L1_TLS0_CNTL29__EN_MASK 0x00001000L 6169 #define MMMC_VM_MX_L1_TLS0_CNTL29__PREFETCH_DONE_MASK 0x00002000L 6170 //MMMC_VM_MX_L1_TLS0_CNTL30 6171 #define MMMC_VM_MX_L1_TLS0_CNTL30__REQ_STREAM_ID__SHIFT 0x0 6172 #define MMMC_VM_MX_L1_TLS0_CNTL30__EN__SHIFT 0xc 6173 #define MMMC_VM_MX_L1_TLS0_CNTL30__PREFETCH_DONE__SHIFT 0xd 6174 #define MMMC_VM_MX_L1_TLS0_CNTL30__REQ_STREAM_ID_MASK 0x000001FFL 6175 #define MMMC_VM_MX_L1_TLS0_CNTL30__EN_MASK 0x00001000L 6176 #define MMMC_VM_MX_L1_TLS0_CNTL30__PREFETCH_DONE_MASK 0x00002000L 6177 //MMMC_VM_MX_L1_TLS0_CNTL31 6178 #define MMMC_VM_MX_L1_TLS0_CNTL31__REQ_STREAM_ID__SHIFT 0x0 6179 #define MMMC_VM_MX_L1_TLS0_CNTL31__EN__SHIFT 0xc 6180 #define MMMC_VM_MX_L1_TLS0_CNTL31__PREFETCH_DONE__SHIFT 0xd 6181 #define MMMC_VM_MX_L1_TLS0_CNTL31__REQ_STREAM_ID_MASK 0x000001FFL 6182 #define MMMC_VM_MX_L1_TLS0_CNTL31__EN_MASK 0x00001000L 6183 #define MMMC_VM_MX_L1_TLS0_CNTL31__PREFETCH_DONE_MASK 0x00002000L 6184 //MMMC_VM_MX_L1_TLS0_CNTL32 6185 #define MMMC_VM_MX_L1_TLS0_CNTL32__REQ_STREAM_ID__SHIFT 0x0 6186 #define MMMC_VM_MX_L1_TLS0_CNTL32__EN__SHIFT 0xc 6187 #define MMMC_VM_MX_L1_TLS0_CNTL32__PREFETCH_DONE__SHIFT 0xd 6188 #define MMMC_VM_MX_L1_TLS0_CNTL32__REQ_STREAM_ID_MASK 0x000001FFL 6189 #define MMMC_VM_MX_L1_TLS0_CNTL32__EN_MASK 0x00001000L 6190 #define MMMC_VM_MX_L1_TLS0_CNTL32__PREFETCH_DONE_MASK 0x00002000L 6191 //MMMC_VM_MX_L1_TLS0_CNTL33 6192 #define MMMC_VM_MX_L1_TLS0_CNTL33__REQ_STREAM_ID__SHIFT 0x0 6193 #define MMMC_VM_MX_L1_TLS0_CNTL33__EN__SHIFT 0xc 6194 #define MMMC_VM_MX_L1_TLS0_CNTL33__PREFETCH_DONE__SHIFT 0xd 6195 #define MMMC_VM_MX_L1_TLS0_CNTL33__REQ_STREAM_ID_MASK 0x000001FFL 6196 #define MMMC_VM_MX_L1_TLS0_CNTL33__EN_MASK 0x00001000L 6197 #define MMMC_VM_MX_L1_TLS0_CNTL33__PREFETCH_DONE_MASK 0x00002000L 6198 //MMMC_VM_MX_L1_TLS0_CNTL34 6199 #define MMMC_VM_MX_L1_TLS0_CNTL34__REQ_STREAM_ID__SHIFT 0x0 6200 #define MMMC_VM_MX_L1_TLS0_CNTL34__EN__SHIFT 0xc 6201 #define MMMC_VM_MX_L1_TLS0_CNTL34__PREFETCH_DONE__SHIFT 0xd 6202 #define MMMC_VM_MX_L1_TLS0_CNTL34__REQ_STREAM_ID_MASK 0x000001FFL 6203 #define MMMC_VM_MX_L1_TLS0_CNTL34__EN_MASK 0x00001000L 6204 #define MMMC_VM_MX_L1_TLS0_CNTL34__PREFETCH_DONE_MASK 0x00002000L 6205 //MMMC_VM_MX_L1_TLS0_CNTL35 6206 #define MMMC_VM_MX_L1_TLS0_CNTL35__REQ_STREAM_ID__SHIFT 0x0 6207 #define MMMC_VM_MX_L1_TLS0_CNTL35__EN__SHIFT 0xc 6208 #define MMMC_VM_MX_L1_TLS0_CNTL35__PREFETCH_DONE__SHIFT 0xd 6209 #define MMMC_VM_MX_L1_TLS0_CNTL35__REQ_STREAM_ID_MASK 0x000001FFL 6210 #define MMMC_VM_MX_L1_TLS0_CNTL35__EN_MASK 0x00001000L 6211 #define MMMC_VM_MX_L1_TLS0_CNTL35__PREFETCH_DONE_MASK 0x00002000L 6212 //MMMC_VM_MX_L1_TLS0_CNTL36 6213 #define MMMC_VM_MX_L1_TLS0_CNTL36__REQ_STREAM_ID__SHIFT 0x0 6214 #define MMMC_VM_MX_L1_TLS0_CNTL36__EN__SHIFT 0xc 6215 #define MMMC_VM_MX_L1_TLS0_CNTL36__PREFETCH_DONE__SHIFT 0xd 6216 #define MMMC_VM_MX_L1_TLS0_CNTL36__REQ_STREAM_ID_MASK 0x000001FFL 6217 #define MMMC_VM_MX_L1_TLS0_CNTL36__EN_MASK 0x00001000L 6218 #define MMMC_VM_MX_L1_TLS0_CNTL36__PREFETCH_DONE_MASK 0x00002000L 6219 //MMMC_VM_MX_L1_TLS0_CNTL37 6220 #define MMMC_VM_MX_L1_TLS0_CNTL37__REQ_STREAM_ID__SHIFT 0x0 6221 #define MMMC_VM_MX_L1_TLS0_CNTL37__EN__SHIFT 0xc 6222 #define MMMC_VM_MX_L1_TLS0_CNTL37__PREFETCH_DONE__SHIFT 0xd 6223 #define MMMC_VM_MX_L1_TLS0_CNTL37__REQ_STREAM_ID_MASK 0x000001FFL 6224 #define MMMC_VM_MX_L1_TLS0_CNTL37__EN_MASK 0x00001000L 6225 #define MMMC_VM_MX_L1_TLS0_CNTL37__PREFETCH_DONE_MASK 0x00002000L 6226 //MMMC_VM_MX_L1_TLS0_START_ADDR0_LO32 6227 #define MMMC_VM_MX_L1_TLS0_START_ADDR0_LO32__START_ADDR_LO32__SHIFT 0x0 6228 #define MMMC_VM_MX_L1_TLS0_START_ADDR0_LO32__START_ADDR_LO32_MASK 0xFFFFFFFFL 6229 //MMMC_VM_MX_L1_TLS0_START_ADDR0_HI32 6230 #define MMMC_VM_MX_L1_TLS0_START_ADDR0_HI32__START_ADDR_HI4__SHIFT 0x0 6231 #define MMMC_VM_MX_L1_TLS0_START_ADDR0_HI32__START_ADDR_HI4_MASK 0x0000000FL 6232 //MMMC_VM_MX_L1_TLS0_START_ADDR1_LO32 6233 #define MMMC_VM_MX_L1_TLS0_START_ADDR1_LO32__START_ADDR_LO32__SHIFT 0x0 6234 #define MMMC_VM_MX_L1_TLS0_START_ADDR1_LO32__START_ADDR_LO32_MASK 0xFFFFFFFFL 6235 //MMMC_VM_MX_L1_TLS0_START_ADDR1_HI32 6236 #define MMMC_VM_MX_L1_TLS0_START_ADDR1_HI32__START_ADDR_HI4__SHIFT 0x0 6237 #define MMMC_VM_MX_L1_TLS0_START_ADDR1_HI32__START_ADDR_HI4_MASK 0x0000000FL 6238 //MMMC_VM_MX_L1_TLS0_START_ADDR2_LO32 6239 #define MMMC_VM_MX_L1_TLS0_START_ADDR2_LO32__START_ADDR_LO32__SHIFT 0x0 6240 #define MMMC_VM_MX_L1_TLS0_START_ADDR2_LO32__START_ADDR_LO32_MASK 0xFFFFFFFFL 6241 //MMMC_VM_MX_L1_TLS0_START_ADDR2_HI32 6242 #define MMMC_VM_MX_L1_TLS0_START_ADDR2_HI32__START_ADDR_HI4__SHIFT 0x0 6243 #define MMMC_VM_MX_L1_TLS0_START_ADDR2_HI32__START_ADDR_HI4_MASK 0x0000000FL 6244 //MMMC_VM_MX_L1_TLS0_START_ADDR3_LO32 6245 #define MMMC_VM_MX_L1_TLS0_START_ADDR3_LO32__START_ADDR_LO32__SHIFT 0x0 6246 #define MMMC_VM_MX_L1_TLS0_START_ADDR3_LO32__START_ADDR_LO32_MASK 0xFFFFFFFFL 6247 //MMMC_VM_MX_L1_TLS0_START_ADDR3_HI32 6248 #define MMMC_VM_MX_L1_TLS0_START_ADDR3_HI32__START_ADDR_HI4__SHIFT 0x0 6249 #define MMMC_VM_MX_L1_TLS0_START_ADDR3_HI32__START_ADDR_HI4_MASK 0x0000000FL 6250 //MMMC_VM_MX_L1_TLS0_START_ADDR4_LO32 6251 #define MMMC_VM_MX_L1_TLS0_START_ADDR4_LO32__START_ADDR_LO32__SHIFT 0x0 6252 #define MMMC_VM_MX_L1_TLS0_START_ADDR4_LO32__START_ADDR_LO32_MASK 0xFFFFFFFFL 6253 //MMMC_VM_MX_L1_TLS0_START_ADDR4_HI32 6254 #define MMMC_VM_MX_L1_TLS0_START_ADDR4_HI32__START_ADDR_HI4__SHIFT 0x0 6255 #define MMMC_VM_MX_L1_TLS0_START_ADDR4_HI32__START_ADDR_HI4_MASK 0x0000000FL 6256 //MMMC_VM_MX_L1_TLS0_START_ADDR5_LO32 6257 #define MMMC_VM_MX_L1_TLS0_START_ADDR5_LO32__START_ADDR_LO32__SHIFT 0x0 6258 #define MMMC_VM_MX_L1_TLS0_START_ADDR5_LO32__START_ADDR_LO32_MASK 0xFFFFFFFFL 6259 //MMMC_VM_MX_L1_TLS0_START_ADDR5_HI32 6260 #define MMMC_VM_MX_L1_TLS0_START_ADDR5_HI32__START_ADDR_HI4__SHIFT 0x0 6261 #define MMMC_VM_MX_L1_TLS0_START_ADDR5_HI32__START_ADDR_HI4_MASK 0x0000000FL 6262 //MMMC_VM_MX_L1_TLS0_START_ADDR6_LO32 6263 #define MMMC_VM_MX_L1_TLS0_START_ADDR6_LO32__START_ADDR_LO32__SHIFT 0x0 6264 #define MMMC_VM_MX_L1_TLS0_START_ADDR6_LO32__START_ADDR_LO32_MASK 0xFFFFFFFFL 6265 //MMMC_VM_MX_L1_TLS0_START_ADDR6_HI32 6266 #define MMMC_VM_MX_L1_TLS0_START_ADDR6_HI32__START_ADDR_HI4__SHIFT 0x0 6267 #define MMMC_VM_MX_L1_TLS0_START_ADDR6_HI32__START_ADDR_HI4_MASK 0x0000000FL 6268 //MMMC_VM_MX_L1_TLS0_START_ADDR7_LO32 6269 #define MMMC_VM_MX_L1_TLS0_START_ADDR7_LO32__START_ADDR_LO32__SHIFT 0x0 6270 #define MMMC_VM_MX_L1_TLS0_START_ADDR7_LO32__START_ADDR_LO32_MASK 0xFFFFFFFFL 6271 //MMMC_VM_MX_L1_TLS0_START_ADDR7_HI32 6272 #define MMMC_VM_MX_L1_TLS0_START_ADDR7_HI32__START_ADDR_HI4__SHIFT 0x0 6273 #define MMMC_VM_MX_L1_TLS0_START_ADDR7_HI32__START_ADDR_HI4_MASK 0x0000000FL 6274 //MMMC_VM_MX_L1_TLS0_START_ADDR8_LO32 6275 #define MMMC_VM_MX_L1_TLS0_START_ADDR8_LO32__START_ADDR_LO32__SHIFT 0x0 6276 #define MMMC_VM_MX_L1_TLS0_START_ADDR8_LO32__START_ADDR_LO32_MASK 0xFFFFFFFFL 6277 //MMMC_VM_MX_L1_TLS0_START_ADDR8_HI32 6278 #define MMMC_VM_MX_L1_TLS0_START_ADDR8_HI32__START_ADDR_HI4__SHIFT 0x0 6279 #define MMMC_VM_MX_L1_TLS0_START_ADDR8_HI32__START_ADDR_HI4_MASK 0x0000000FL 6280 //MMMC_VM_MX_L1_TLS0_START_ADDR9_LO32 6281 #define MMMC_VM_MX_L1_TLS0_START_ADDR9_LO32__START_ADDR_LO32__SHIFT 0x0 6282 #define MMMC_VM_MX_L1_TLS0_START_ADDR9_LO32__START_ADDR_LO32_MASK 0xFFFFFFFFL 6283 //MMMC_VM_MX_L1_TLS0_START_ADDR9_HI32 6284 #define MMMC_VM_MX_L1_TLS0_START_ADDR9_HI32__START_ADDR_HI4__SHIFT 0x0 6285 #define MMMC_VM_MX_L1_TLS0_START_ADDR9_HI32__START_ADDR_HI4_MASK 0x0000000FL 6286 //MMMC_VM_MX_L1_TLS0_START_ADDR10_LO32 6287 #define MMMC_VM_MX_L1_TLS0_START_ADDR10_LO32__START_ADDR_LO32__SHIFT 0x0 6288 #define MMMC_VM_MX_L1_TLS0_START_ADDR10_LO32__START_ADDR_LO32_MASK 0xFFFFFFFFL 6289 //MMMC_VM_MX_L1_TLS0_START_ADDR10_HI32 6290 #define MMMC_VM_MX_L1_TLS0_START_ADDR10_HI32__START_ADDR_HI4__SHIFT 0x0 6291 #define MMMC_VM_MX_L1_TLS0_START_ADDR10_HI32__START_ADDR_HI4_MASK 0x0000000FL 6292 //MMMC_VM_MX_L1_TLS0_START_ADDR11_LO32 6293 #define MMMC_VM_MX_L1_TLS0_START_ADDR11_LO32__START_ADDR_LO32__SHIFT 0x0 6294 #define MMMC_VM_MX_L1_TLS0_START_ADDR11_LO32__START_ADDR_LO32_MASK 0xFFFFFFFFL 6295 //MMMC_VM_MX_L1_TLS0_START_ADDR11_HI32 6296 #define MMMC_VM_MX_L1_TLS0_START_ADDR11_HI32__START_ADDR_HI4__SHIFT 0x0 6297 #define MMMC_VM_MX_L1_TLS0_START_ADDR11_HI32__START_ADDR_HI4_MASK 0x0000000FL 6298 //MMMC_VM_MX_L1_TLS0_START_ADDR12_LO32 6299 #define MMMC_VM_MX_L1_TLS0_START_ADDR12_LO32__START_ADDR_LO32__SHIFT 0x0 6300 #define MMMC_VM_MX_L1_TLS0_START_ADDR12_LO32__START_ADDR_LO32_MASK 0xFFFFFFFFL 6301 //MMMC_VM_MX_L1_TLS0_START_ADDR12_HI32 6302 #define MMMC_VM_MX_L1_TLS0_START_ADDR12_HI32__START_ADDR_HI4__SHIFT 0x0 6303 #define MMMC_VM_MX_L1_TLS0_START_ADDR12_HI32__START_ADDR_HI4_MASK 0x0000000FL 6304 //MMMC_VM_MX_L1_TLS0_START_ADDR13_LO32 6305 #define MMMC_VM_MX_L1_TLS0_START_ADDR13_LO32__START_ADDR_LO32__SHIFT 0x0 6306 #define MMMC_VM_MX_L1_TLS0_START_ADDR13_LO32__START_ADDR_LO32_MASK 0xFFFFFFFFL 6307 //MMMC_VM_MX_L1_TLS0_START_ADDR13_HI32 6308 #define MMMC_VM_MX_L1_TLS0_START_ADDR13_HI32__START_ADDR_HI4__SHIFT 0x0 6309 #define MMMC_VM_MX_L1_TLS0_START_ADDR13_HI32__START_ADDR_HI4_MASK 0x0000000FL 6310 //MMMC_VM_MX_L1_TLS0_START_ADDR14_LO32 6311 #define MMMC_VM_MX_L1_TLS0_START_ADDR14_LO32__START_ADDR_LO32__SHIFT 0x0 6312 #define MMMC_VM_MX_L1_TLS0_START_ADDR14_LO32__START_ADDR_LO32_MASK 0xFFFFFFFFL 6313 //MMMC_VM_MX_L1_TLS0_START_ADDR14_HI32 6314 #define MMMC_VM_MX_L1_TLS0_START_ADDR14_HI32__START_ADDR_HI4__SHIFT 0x0 6315 #define MMMC_VM_MX_L1_TLS0_START_ADDR14_HI32__START_ADDR_HI4_MASK 0x0000000FL 6316 //MMMC_VM_MX_L1_TLS0_START_ADDR15_LO32 6317 #define MMMC_VM_MX_L1_TLS0_START_ADDR15_LO32__START_ADDR_LO32__SHIFT 0x0 6318 #define MMMC_VM_MX_L1_TLS0_START_ADDR15_LO32__START_ADDR_LO32_MASK 0xFFFFFFFFL 6319 //MMMC_VM_MX_L1_TLS0_START_ADDR15_HI32 6320 #define MMMC_VM_MX_L1_TLS0_START_ADDR15_HI32__START_ADDR_HI4__SHIFT 0x0 6321 #define MMMC_VM_MX_L1_TLS0_START_ADDR15_HI32__START_ADDR_HI4_MASK 0x0000000FL 6322 //MMMC_VM_MX_L1_TLS0_START_ADDR16_LO32 6323 #define MMMC_VM_MX_L1_TLS0_START_ADDR16_LO32__START_ADDR_LO32__SHIFT 0x0 6324 #define MMMC_VM_MX_L1_TLS0_START_ADDR16_LO32__START_ADDR_LO32_MASK 0xFFFFFFFFL 6325 //MMMC_VM_MX_L1_TLS0_START_ADDR16_HI32 6326 #define MMMC_VM_MX_L1_TLS0_START_ADDR16_HI32__START_ADDR_HI4__SHIFT 0x0 6327 #define MMMC_VM_MX_L1_TLS0_START_ADDR16_HI32__START_ADDR_HI4_MASK 0x0000000FL 6328 //MMMC_VM_MX_L1_TLS0_START_ADDR17_LO32 6329 #define MMMC_VM_MX_L1_TLS0_START_ADDR17_LO32__START_ADDR_LO32__SHIFT 0x0 6330 #define MMMC_VM_MX_L1_TLS0_START_ADDR17_LO32__START_ADDR_LO32_MASK 0xFFFFFFFFL 6331 //MMMC_VM_MX_L1_TLS0_START_ADDR17_HI32 6332 #define MMMC_VM_MX_L1_TLS0_START_ADDR17_HI32__START_ADDR_HI4__SHIFT 0x0 6333 #define MMMC_VM_MX_L1_TLS0_START_ADDR17_HI32__START_ADDR_HI4_MASK 0x0000000FL 6334 //MMMC_VM_MX_L1_TLS0_START_ADDR18_LO32 6335 #define MMMC_VM_MX_L1_TLS0_START_ADDR18_LO32__START_ADDR_LO32__SHIFT 0x0 6336 #define MMMC_VM_MX_L1_TLS0_START_ADDR18_LO32__START_ADDR_LO32_MASK 0xFFFFFFFFL 6337 //MMMC_VM_MX_L1_TLS0_START_ADDR18_HI32 6338 #define MMMC_VM_MX_L1_TLS0_START_ADDR18_HI32__START_ADDR_HI4__SHIFT 0x0 6339 #define MMMC_VM_MX_L1_TLS0_START_ADDR18_HI32__START_ADDR_HI4_MASK 0x0000000FL 6340 //MMMC_VM_MX_L1_TLS0_START_ADDR19_LO32 6341 #define MMMC_VM_MX_L1_TLS0_START_ADDR19_LO32__START_ADDR_LO32__SHIFT 0x0 6342 #define MMMC_VM_MX_L1_TLS0_START_ADDR19_LO32__START_ADDR_LO32_MASK 0xFFFFFFFFL 6343 //MMMC_VM_MX_L1_TLS0_START_ADDR19_HI32 6344 #define MMMC_VM_MX_L1_TLS0_START_ADDR19_HI32__START_ADDR_HI4__SHIFT 0x0 6345 #define MMMC_VM_MX_L1_TLS0_START_ADDR19_HI32__START_ADDR_HI4_MASK 0x0000000FL 6346 //MMMC_VM_MX_L1_TLS0_START_ADDR20_LO32 6347 #define MMMC_VM_MX_L1_TLS0_START_ADDR20_LO32__START_ADDR_LO32__SHIFT 0x0 6348 #define MMMC_VM_MX_L1_TLS0_START_ADDR20_LO32__START_ADDR_LO32_MASK 0xFFFFFFFFL 6349 //MMMC_VM_MX_L1_TLS0_START_ADDR20_HI32 6350 #define MMMC_VM_MX_L1_TLS0_START_ADDR20_HI32__START_ADDR_HI4__SHIFT 0x0 6351 #define MMMC_VM_MX_L1_TLS0_START_ADDR20_HI32__START_ADDR_HI4_MASK 0x0000000FL 6352 //MMMC_VM_MX_L1_TLS0_START_ADDR21_LO32 6353 #define MMMC_VM_MX_L1_TLS0_START_ADDR21_LO32__START_ADDR_LO32__SHIFT 0x0 6354 #define MMMC_VM_MX_L1_TLS0_START_ADDR21_LO32__START_ADDR_LO32_MASK 0xFFFFFFFFL 6355 //MMMC_VM_MX_L1_TLS0_START_ADDR21_HI32 6356 #define MMMC_VM_MX_L1_TLS0_START_ADDR21_HI32__START_ADDR_HI4__SHIFT 0x0 6357 #define MMMC_VM_MX_L1_TLS0_START_ADDR21_HI32__START_ADDR_HI4_MASK 0x0000000FL 6358 //MMMC_VM_MX_L1_TLS0_START_ADDR22_LO32 6359 #define MMMC_VM_MX_L1_TLS0_START_ADDR22_LO32__START_ADDR_LO32__SHIFT 0x0 6360 #define MMMC_VM_MX_L1_TLS0_START_ADDR22_LO32__START_ADDR_LO32_MASK 0xFFFFFFFFL 6361 //MMMC_VM_MX_L1_TLS0_START_ADDR22_HI32 6362 #define MMMC_VM_MX_L1_TLS0_START_ADDR22_HI32__START_ADDR_HI4__SHIFT 0x0 6363 #define MMMC_VM_MX_L1_TLS0_START_ADDR22_HI32__START_ADDR_HI4_MASK 0x0000000FL 6364 //MMMC_VM_MX_L1_TLS0_START_ADDR23_LO32 6365 #define MMMC_VM_MX_L1_TLS0_START_ADDR23_LO32__START_ADDR_LO32__SHIFT 0x0 6366 #define MMMC_VM_MX_L1_TLS0_START_ADDR23_LO32__START_ADDR_LO32_MASK 0xFFFFFFFFL 6367 //MMMC_VM_MX_L1_TLS0_START_ADDR23_HI32 6368 #define MMMC_VM_MX_L1_TLS0_START_ADDR23_HI32__START_ADDR_HI4__SHIFT 0x0 6369 #define MMMC_VM_MX_L1_TLS0_START_ADDR23_HI32__START_ADDR_HI4_MASK 0x0000000FL 6370 //MMMC_VM_MX_L1_TLS0_START_ADDR24_LO32 6371 #define MMMC_VM_MX_L1_TLS0_START_ADDR24_LO32__START_ADDR_LO32__SHIFT 0x0 6372 #define MMMC_VM_MX_L1_TLS0_START_ADDR24_LO32__START_ADDR_LO32_MASK 0xFFFFFFFFL 6373 //MMMC_VM_MX_L1_TLS0_START_ADDR24_HI32 6374 #define MMMC_VM_MX_L1_TLS0_START_ADDR24_HI32__START_ADDR_HI4__SHIFT 0x0 6375 #define MMMC_VM_MX_L1_TLS0_START_ADDR24_HI32__START_ADDR_HI4_MASK 0x0000000FL 6376 //MMMC_VM_MX_L1_TLS0_START_ADDR25_LO32 6377 #define MMMC_VM_MX_L1_TLS0_START_ADDR25_LO32__START_ADDR_LO32__SHIFT 0x0 6378 #define MMMC_VM_MX_L1_TLS0_START_ADDR25_LO32__START_ADDR_LO32_MASK 0xFFFFFFFFL 6379 //MMMC_VM_MX_L1_TLS0_START_ADDR25_HI32 6380 #define MMMC_VM_MX_L1_TLS0_START_ADDR25_HI32__START_ADDR_HI4__SHIFT 0x0 6381 #define MMMC_VM_MX_L1_TLS0_START_ADDR25_HI32__START_ADDR_HI4_MASK 0x0000000FL 6382 //MMMC_VM_MX_L1_TLS0_START_ADDR26_LO32 6383 #define MMMC_VM_MX_L1_TLS0_START_ADDR26_LO32__START_ADDR_LO32__SHIFT 0x0 6384 #define MMMC_VM_MX_L1_TLS0_START_ADDR26_LO32__START_ADDR_LO32_MASK 0xFFFFFFFFL 6385 //MMMC_VM_MX_L1_TLS0_START_ADDR26_HI32 6386 #define MMMC_VM_MX_L1_TLS0_START_ADDR26_HI32__START_ADDR_HI4__SHIFT 0x0 6387 #define MMMC_VM_MX_L1_TLS0_START_ADDR26_HI32__START_ADDR_HI4_MASK 0x0000000FL 6388 //MMMC_VM_MX_L1_TLS0_START_ADDR27_LO32 6389 #define MMMC_VM_MX_L1_TLS0_START_ADDR27_LO32__START_ADDR_LO32__SHIFT 0x0 6390 #define MMMC_VM_MX_L1_TLS0_START_ADDR27_LO32__START_ADDR_LO32_MASK 0xFFFFFFFFL 6391 //MMMC_VM_MX_L1_TLS0_START_ADDR27_HI32 6392 #define MMMC_VM_MX_L1_TLS0_START_ADDR27_HI32__START_ADDR_HI4__SHIFT 0x0 6393 #define MMMC_VM_MX_L1_TLS0_START_ADDR27_HI32__START_ADDR_HI4_MASK 0x0000000FL 6394 //MMMC_VM_MX_L1_TLS0_START_ADDR28_LO32 6395 #define MMMC_VM_MX_L1_TLS0_START_ADDR28_LO32__START_ADDR_LO32__SHIFT 0x0 6396 #define MMMC_VM_MX_L1_TLS0_START_ADDR28_LO32__START_ADDR_LO32_MASK 0xFFFFFFFFL 6397 //MMMC_VM_MX_L1_TLS0_START_ADDR28_HI32 6398 #define MMMC_VM_MX_L1_TLS0_START_ADDR28_HI32__START_ADDR_HI4__SHIFT 0x0 6399 #define MMMC_VM_MX_L1_TLS0_START_ADDR28_HI32__START_ADDR_HI4_MASK 0x0000000FL 6400 //MMMC_VM_MX_L1_TLS0_START_ADDR29_LO32 6401 #define MMMC_VM_MX_L1_TLS0_START_ADDR29_LO32__START_ADDR_LO32__SHIFT 0x0 6402 #define MMMC_VM_MX_L1_TLS0_START_ADDR29_LO32__START_ADDR_LO32_MASK 0xFFFFFFFFL 6403 //MMMC_VM_MX_L1_TLS0_START_ADDR29_HI32 6404 #define MMMC_VM_MX_L1_TLS0_START_ADDR29_HI32__START_ADDR_HI4__SHIFT 0x0 6405 #define MMMC_VM_MX_L1_TLS0_START_ADDR29_HI32__START_ADDR_HI4_MASK 0x0000000FL 6406 //MMMC_VM_MX_L1_TLS0_START_ADDR30_LO32 6407 #define MMMC_VM_MX_L1_TLS0_START_ADDR30_LO32__START_ADDR_LO32__SHIFT 0x0 6408 #define MMMC_VM_MX_L1_TLS0_START_ADDR30_LO32__START_ADDR_LO32_MASK 0xFFFFFFFFL 6409 //MMMC_VM_MX_L1_TLS0_START_ADDR30_HI32 6410 #define MMMC_VM_MX_L1_TLS0_START_ADDR30_HI32__START_ADDR_HI4__SHIFT 0x0 6411 #define MMMC_VM_MX_L1_TLS0_START_ADDR30_HI32__START_ADDR_HI4_MASK 0x0000000FL 6412 //MMMC_VM_MX_L1_TLS0_START_ADDR31_LO32 6413 #define MMMC_VM_MX_L1_TLS0_START_ADDR31_LO32__START_ADDR_LO32__SHIFT 0x0 6414 #define MMMC_VM_MX_L1_TLS0_START_ADDR31_LO32__START_ADDR_LO32_MASK 0xFFFFFFFFL 6415 //MMMC_VM_MX_L1_TLS0_START_ADDR31_HI32 6416 #define MMMC_VM_MX_L1_TLS0_START_ADDR31_HI32__START_ADDR_HI4__SHIFT 0x0 6417 #define MMMC_VM_MX_L1_TLS0_START_ADDR31_HI32__START_ADDR_HI4_MASK 0x0000000FL 6418 //MMMC_VM_MX_L1_TLS0_START_ADDR32_LO32 6419 #define MMMC_VM_MX_L1_TLS0_START_ADDR32_LO32__START_ADDR_LO32__SHIFT 0x0 6420 #define MMMC_VM_MX_L1_TLS0_START_ADDR32_LO32__START_ADDR_LO32_MASK 0xFFFFFFFFL 6421 //MMMC_VM_MX_L1_TLS0_START_ADDR32_HI32 6422 #define MMMC_VM_MX_L1_TLS0_START_ADDR32_HI32__START_ADDR_HI4__SHIFT 0x0 6423 #define MMMC_VM_MX_L1_TLS0_START_ADDR32_HI32__START_ADDR_HI4_MASK 0x0000000FL 6424 //MMMC_VM_MX_L1_TLS0_START_ADDR33_LO32 6425 #define MMMC_VM_MX_L1_TLS0_START_ADDR33_LO32__START_ADDR_LO32__SHIFT 0x0 6426 #define MMMC_VM_MX_L1_TLS0_START_ADDR33_LO32__START_ADDR_LO32_MASK 0xFFFFFFFFL 6427 //MMMC_VM_MX_L1_TLS0_START_ADDR33_HI32 6428 #define MMMC_VM_MX_L1_TLS0_START_ADDR33_HI32__START_ADDR_HI4__SHIFT 0x0 6429 #define MMMC_VM_MX_L1_TLS0_START_ADDR33_HI32__START_ADDR_HI4_MASK 0x0000000FL 6430 //MMMC_VM_MX_L1_TLS0_START_ADDR34_LO32 6431 #define MMMC_VM_MX_L1_TLS0_START_ADDR34_LO32__START_ADDR_LO32__SHIFT 0x0 6432 #define MMMC_VM_MX_L1_TLS0_START_ADDR34_LO32__START_ADDR_LO32_MASK 0xFFFFFFFFL 6433 //MMMC_VM_MX_L1_TLS0_START_ADDR34_HI32 6434 #define MMMC_VM_MX_L1_TLS0_START_ADDR34_HI32__START_ADDR_HI4__SHIFT 0x0 6435 #define MMMC_VM_MX_L1_TLS0_START_ADDR34_HI32__START_ADDR_HI4_MASK 0x0000000FL 6436 //MMMC_VM_MX_L1_TLS0_START_ADDR35_LO32 6437 #define MMMC_VM_MX_L1_TLS0_START_ADDR35_LO32__START_ADDR_LO32__SHIFT 0x0 6438 #define MMMC_VM_MX_L1_TLS0_START_ADDR35_LO32__START_ADDR_LO32_MASK 0xFFFFFFFFL 6439 //MMMC_VM_MX_L1_TLS0_START_ADDR35_HI32 6440 #define MMMC_VM_MX_L1_TLS0_START_ADDR35_HI32__START_ADDR_HI4__SHIFT 0x0 6441 #define MMMC_VM_MX_L1_TLS0_START_ADDR35_HI32__START_ADDR_HI4_MASK 0x0000000FL 6442 //MMMC_VM_MX_L1_TLS0_START_ADDR36_LO32 6443 #define MMMC_VM_MX_L1_TLS0_START_ADDR36_LO32__START_ADDR_LO32__SHIFT 0x0 6444 #define MMMC_VM_MX_L1_TLS0_START_ADDR36_LO32__START_ADDR_LO32_MASK 0xFFFFFFFFL 6445 //MMMC_VM_MX_L1_TLS0_START_ADDR36_HI32 6446 #define MMMC_VM_MX_L1_TLS0_START_ADDR36_HI32__START_ADDR_HI4__SHIFT 0x0 6447 #define MMMC_VM_MX_L1_TLS0_START_ADDR36_HI32__START_ADDR_HI4_MASK 0x0000000FL 6448 //MMMC_VM_MX_L1_TLS0_START_ADDR37_LO32 6449 #define MMMC_VM_MX_L1_TLS0_START_ADDR37_LO32__START_ADDR_LO32__SHIFT 0x0 6450 #define MMMC_VM_MX_L1_TLS0_START_ADDR37_LO32__START_ADDR_LO32_MASK 0xFFFFFFFFL 6451 //MMMC_VM_MX_L1_TLS0_START_ADDR37_HI32 6452 #define MMMC_VM_MX_L1_TLS0_START_ADDR37_HI32__START_ADDR_HI4__SHIFT 0x0 6453 #define MMMC_VM_MX_L1_TLS0_START_ADDR37_HI32__START_ADDR_HI4_MASK 0x0000000FL 6454 //MMMC_VM_MX_L1_TLS0_END_ADDR0_LO32 6455 #define MMMC_VM_MX_L1_TLS0_END_ADDR0_LO32__END_ADDR_LO32__SHIFT 0x0 6456 #define MMMC_VM_MX_L1_TLS0_END_ADDR0_LO32__END_ADDR_LO32_MASK 0xFFFFFFFFL 6457 //MMMC_VM_MX_L1_TLS0_END_ADDR0_HI32 6458 #define MMMC_VM_MX_L1_TLS0_END_ADDR0_HI32__END_ADDR_HI4__SHIFT 0x0 6459 #define MMMC_VM_MX_L1_TLS0_END_ADDR0_HI32__END_ADDR_HI4_MASK 0x0000000FL 6460 //MMMC_VM_MX_L1_TLS0_END_ADDR1_LO32 6461 #define MMMC_VM_MX_L1_TLS0_END_ADDR1_LO32__END_ADDR_LO32__SHIFT 0x0 6462 #define MMMC_VM_MX_L1_TLS0_END_ADDR1_LO32__END_ADDR_LO32_MASK 0xFFFFFFFFL 6463 //MMMC_VM_MX_L1_TLS0_END_ADDR1_HI32 6464 #define MMMC_VM_MX_L1_TLS0_END_ADDR1_HI32__END_ADDR_HI4__SHIFT 0x0 6465 #define MMMC_VM_MX_L1_TLS0_END_ADDR1_HI32__END_ADDR_HI4_MASK 0x0000000FL 6466 //MMMC_VM_MX_L1_TLS0_END_ADDR2_LO32 6467 #define MMMC_VM_MX_L1_TLS0_END_ADDR2_LO32__END_ADDR_LO32__SHIFT 0x0 6468 #define MMMC_VM_MX_L1_TLS0_END_ADDR2_LO32__END_ADDR_LO32_MASK 0xFFFFFFFFL 6469 //MMMC_VM_MX_L1_TLS0_END_ADDR2_HI32 6470 #define MMMC_VM_MX_L1_TLS0_END_ADDR2_HI32__END_ADDR_HI4__SHIFT 0x0 6471 #define MMMC_VM_MX_L1_TLS0_END_ADDR2_HI32__END_ADDR_HI4_MASK 0x0000000FL 6472 //MMMC_VM_MX_L1_TLS0_END_ADDR3_LO32 6473 #define MMMC_VM_MX_L1_TLS0_END_ADDR3_LO32__END_ADDR_LO32__SHIFT 0x0 6474 #define MMMC_VM_MX_L1_TLS0_END_ADDR3_LO32__END_ADDR_LO32_MASK 0xFFFFFFFFL 6475 //MMMC_VM_MX_L1_TLS0_END_ADDR3_HI32 6476 #define MMMC_VM_MX_L1_TLS0_END_ADDR3_HI32__END_ADDR_HI4__SHIFT 0x0 6477 #define MMMC_VM_MX_L1_TLS0_END_ADDR3_HI32__END_ADDR_HI4_MASK 0x0000000FL 6478 //MMMC_VM_MX_L1_TLS0_END_ADDR4_LO32 6479 #define MMMC_VM_MX_L1_TLS0_END_ADDR4_LO32__END_ADDR_LO32__SHIFT 0x0 6480 #define MMMC_VM_MX_L1_TLS0_END_ADDR4_LO32__END_ADDR_LO32_MASK 0xFFFFFFFFL 6481 //MMMC_VM_MX_L1_TLS0_END_ADDR4_HI32 6482 #define MMMC_VM_MX_L1_TLS0_END_ADDR4_HI32__END_ADDR_HI4__SHIFT 0x0 6483 #define MMMC_VM_MX_L1_TLS0_END_ADDR4_HI32__END_ADDR_HI4_MASK 0x0000000FL 6484 //MMMC_VM_MX_L1_TLS0_END_ADDR5_LO32 6485 #define MMMC_VM_MX_L1_TLS0_END_ADDR5_LO32__END_ADDR_LO32__SHIFT 0x0 6486 #define MMMC_VM_MX_L1_TLS0_END_ADDR5_LO32__END_ADDR_LO32_MASK 0xFFFFFFFFL 6487 //MMMC_VM_MX_L1_TLS0_END_ADDR5_HI32 6488 #define MMMC_VM_MX_L1_TLS0_END_ADDR5_HI32__END_ADDR_HI4__SHIFT 0x0 6489 #define MMMC_VM_MX_L1_TLS0_END_ADDR5_HI32__END_ADDR_HI4_MASK 0x0000000FL 6490 //MMMC_VM_MX_L1_TLS0_END_ADDR6_LO32 6491 #define MMMC_VM_MX_L1_TLS0_END_ADDR6_LO32__END_ADDR_LO32__SHIFT 0x0 6492 #define MMMC_VM_MX_L1_TLS0_END_ADDR6_LO32__END_ADDR_LO32_MASK 0xFFFFFFFFL 6493 //MMMC_VM_MX_L1_TLS0_END_ADDR6_HI32 6494 #define MMMC_VM_MX_L1_TLS0_END_ADDR6_HI32__END_ADDR_HI4__SHIFT 0x0 6495 #define MMMC_VM_MX_L1_TLS0_END_ADDR6_HI32__END_ADDR_HI4_MASK 0x0000000FL 6496 //MMMC_VM_MX_L1_TLS0_END_ADDR7_LO32 6497 #define MMMC_VM_MX_L1_TLS0_END_ADDR7_LO32__END_ADDR_LO32__SHIFT 0x0 6498 #define MMMC_VM_MX_L1_TLS0_END_ADDR7_LO32__END_ADDR_LO32_MASK 0xFFFFFFFFL 6499 //MMMC_VM_MX_L1_TLS0_END_ADDR7_HI32 6500 #define MMMC_VM_MX_L1_TLS0_END_ADDR7_HI32__END_ADDR_HI4__SHIFT 0x0 6501 #define MMMC_VM_MX_L1_TLS0_END_ADDR7_HI32__END_ADDR_HI4_MASK 0x0000000FL 6502 //MMMC_VM_MX_L1_TLS0_END_ADDR8_LO32 6503 #define MMMC_VM_MX_L1_TLS0_END_ADDR8_LO32__END_ADDR_LO32__SHIFT 0x0 6504 #define MMMC_VM_MX_L1_TLS0_END_ADDR8_LO32__END_ADDR_LO32_MASK 0xFFFFFFFFL 6505 //MMMC_VM_MX_L1_TLS0_END_ADDR8_HI32 6506 #define MMMC_VM_MX_L1_TLS0_END_ADDR8_HI32__END_ADDR_HI4__SHIFT 0x0 6507 #define MMMC_VM_MX_L1_TLS0_END_ADDR8_HI32__END_ADDR_HI4_MASK 0x0000000FL 6508 //MMMC_VM_MX_L1_TLS0_END_ADDR9_LO32 6509 #define MMMC_VM_MX_L1_TLS0_END_ADDR9_LO32__END_ADDR_LO32__SHIFT 0x0 6510 #define MMMC_VM_MX_L1_TLS0_END_ADDR9_LO32__END_ADDR_LO32_MASK 0xFFFFFFFFL 6511 //MMMC_VM_MX_L1_TLS0_END_ADDR9_HI32 6512 #define MMMC_VM_MX_L1_TLS0_END_ADDR9_HI32__END_ADDR_HI4__SHIFT 0x0 6513 #define MMMC_VM_MX_L1_TLS0_END_ADDR9_HI32__END_ADDR_HI4_MASK 0x0000000FL 6514 //MMMC_VM_MX_L1_TLS0_END_ADDR10_LO32 6515 #define MMMC_VM_MX_L1_TLS0_END_ADDR10_LO32__END_ADDR_LO32__SHIFT 0x0 6516 #define MMMC_VM_MX_L1_TLS0_END_ADDR10_LO32__END_ADDR_LO32_MASK 0xFFFFFFFFL 6517 //MMMC_VM_MX_L1_TLS0_END_ADDR10_HI32 6518 #define MMMC_VM_MX_L1_TLS0_END_ADDR10_HI32__END_ADDR_HI4__SHIFT 0x0 6519 #define MMMC_VM_MX_L1_TLS0_END_ADDR10_HI32__END_ADDR_HI4_MASK 0x0000000FL 6520 //MMMC_VM_MX_L1_TLS0_END_ADDR11_LO32 6521 #define MMMC_VM_MX_L1_TLS0_END_ADDR11_LO32__END_ADDR_LO32__SHIFT 0x0 6522 #define MMMC_VM_MX_L1_TLS0_END_ADDR11_LO32__END_ADDR_LO32_MASK 0xFFFFFFFFL 6523 //MMMC_VM_MX_L1_TLS0_END_ADDR11_HI32 6524 #define MMMC_VM_MX_L1_TLS0_END_ADDR11_HI32__END_ADDR_HI4__SHIFT 0x0 6525 #define MMMC_VM_MX_L1_TLS0_END_ADDR11_HI32__END_ADDR_HI4_MASK 0x0000000FL 6526 //MMMC_VM_MX_L1_TLS0_END_ADDR12_LO32 6527 #define MMMC_VM_MX_L1_TLS0_END_ADDR12_LO32__END_ADDR_LO32__SHIFT 0x0 6528 #define MMMC_VM_MX_L1_TLS0_END_ADDR12_LO32__END_ADDR_LO32_MASK 0xFFFFFFFFL 6529 //MMMC_VM_MX_L1_TLS0_END_ADDR12_HI32 6530 #define MMMC_VM_MX_L1_TLS0_END_ADDR12_HI32__END_ADDR_HI4__SHIFT 0x0 6531 #define MMMC_VM_MX_L1_TLS0_END_ADDR12_HI32__END_ADDR_HI4_MASK 0x0000000FL 6532 //MMMC_VM_MX_L1_TLS0_END_ADDR13_LO32 6533 #define MMMC_VM_MX_L1_TLS0_END_ADDR13_LO32__END_ADDR_LO32__SHIFT 0x0 6534 #define MMMC_VM_MX_L1_TLS0_END_ADDR13_LO32__END_ADDR_LO32_MASK 0xFFFFFFFFL 6535 //MMMC_VM_MX_L1_TLS0_END_ADDR13_HI32 6536 #define MMMC_VM_MX_L1_TLS0_END_ADDR13_HI32__END_ADDR_HI4__SHIFT 0x0 6537 #define MMMC_VM_MX_L1_TLS0_END_ADDR13_HI32__END_ADDR_HI4_MASK 0x0000000FL 6538 //MMMC_VM_MX_L1_TLS0_END_ADDR14_LO32 6539 #define MMMC_VM_MX_L1_TLS0_END_ADDR14_LO32__END_ADDR_LO32__SHIFT 0x0 6540 #define MMMC_VM_MX_L1_TLS0_END_ADDR14_LO32__END_ADDR_LO32_MASK 0xFFFFFFFFL 6541 //MMMC_VM_MX_L1_TLS0_END_ADDR14_HI32 6542 #define MMMC_VM_MX_L1_TLS0_END_ADDR14_HI32__END_ADDR_HI4__SHIFT 0x0 6543 #define MMMC_VM_MX_L1_TLS0_END_ADDR14_HI32__END_ADDR_HI4_MASK 0x0000000FL 6544 //MMMC_VM_MX_L1_TLS0_END_ADDR15_LO32 6545 #define MMMC_VM_MX_L1_TLS0_END_ADDR15_LO32__END_ADDR_LO32__SHIFT 0x0 6546 #define MMMC_VM_MX_L1_TLS0_END_ADDR15_LO32__END_ADDR_LO32_MASK 0xFFFFFFFFL 6547 //MMMC_VM_MX_L1_TLS0_END_ADDR15_HI32 6548 #define MMMC_VM_MX_L1_TLS0_END_ADDR15_HI32__END_ADDR_HI4__SHIFT 0x0 6549 #define MMMC_VM_MX_L1_TLS0_END_ADDR15_HI32__END_ADDR_HI4_MASK 0x0000000FL 6550 //MMMC_VM_MX_L1_TLS0_END_ADDR16_LO32 6551 #define MMMC_VM_MX_L1_TLS0_END_ADDR16_LO32__END_ADDR_LO32__SHIFT 0x0 6552 #define MMMC_VM_MX_L1_TLS0_END_ADDR16_LO32__END_ADDR_LO32_MASK 0xFFFFFFFFL 6553 //MMMC_VM_MX_L1_TLS0_END_ADDR16_HI32 6554 #define MMMC_VM_MX_L1_TLS0_END_ADDR16_HI32__END_ADDR_HI4__SHIFT 0x0 6555 #define MMMC_VM_MX_L1_TLS0_END_ADDR16_HI32__END_ADDR_HI4_MASK 0x0000000FL 6556 //MMMC_VM_MX_L1_TLS0_END_ADDR17_LO32 6557 #define MMMC_VM_MX_L1_TLS0_END_ADDR17_LO32__END_ADDR_LO32__SHIFT 0x0 6558 #define MMMC_VM_MX_L1_TLS0_END_ADDR17_LO32__END_ADDR_LO32_MASK 0xFFFFFFFFL 6559 //MMMC_VM_MX_L1_TLS0_END_ADDR17_HI32 6560 #define MMMC_VM_MX_L1_TLS0_END_ADDR17_HI32__END_ADDR_HI4__SHIFT 0x0 6561 #define MMMC_VM_MX_L1_TLS0_END_ADDR17_HI32__END_ADDR_HI4_MASK 0x0000000FL 6562 //MMMC_VM_MX_L1_TLS0_END_ADDR18_LO32 6563 #define MMMC_VM_MX_L1_TLS0_END_ADDR18_LO32__END_ADDR_LO32__SHIFT 0x0 6564 #define MMMC_VM_MX_L1_TLS0_END_ADDR18_LO32__END_ADDR_LO32_MASK 0xFFFFFFFFL 6565 //MMMC_VM_MX_L1_TLS0_END_ADDR18_HI32 6566 #define MMMC_VM_MX_L1_TLS0_END_ADDR18_HI32__END_ADDR_HI4__SHIFT 0x0 6567 #define MMMC_VM_MX_L1_TLS0_END_ADDR18_HI32__END_ADDR_HI4_MASK 0x0000000FL 6568 //MMMC_VM_MX_L1_TLS0_END_ADDR19_LO32 6569 #define MMMC_VM_MX_L1_TLS0_END_ADDR19_LO32__END_ADDR_LO32__SHIFT 0x0 6570 #define MMMC_VM_MX_L1_TLS0_END_ADDR19_LO32__END_ADDR_LO32_MASK 0xFFFFFFFFL 6571 //MMMC_VM_MX_L1_TLS0_END_ADDR19_HI32 6572 #define MMMC_VM_MX_L1_TLS0_END_ADDR19_HI32__END_ADDR_HI4__SHIFT 0x0 6573 #define MMMC_VM_MX_L1_TLS0_END_ADDR19_HI32__END_ADDR_HI4_MASK 0x0000000FL 6574 //MMMC_VM_MX_L1_TLS0_END_ADDR20_LO32 6575 #define MMMC_VM_MX_L1_TLS0_END_ADDR20_LO32__END_ADDR_LO32__SHIFT 0x0 6576 #define MMMC_VM_MX_L1_TLS0_END_ADDR20_LO32__END_ADDR_LO32_MASK 0xFFFFFFFFL 6577 //MMMC_VM_MX_L1_TLS0_END_ADDR20_HI32 6578 #define MMMC_VM_MX_L1_TLS0_END_ADDR20_HI32__END_ADDR_HI4__SHIFT 0x0 6579 #define MMMC_VM_MX_L1_TLS0_END_ADDR20_HI32__END_ADDR_HI4_MASK 0x0000000FL 6580 //MMMC_VM_MX_L1_TLS0_END_ADDR21_LO32 6581 #define MMMC_VM_MX_L1_TLS0_END_ADDR21_LO32__END_ADDR_LO32__SHIFT 0x0 6582 #define MMMC_VM_MX_L1_TLS0_END_ADDR21_LO32__END_ADDR_LO32_MASK 0xFFFFFFFFL 6583 //MMMC_VM_MX_L1_TLS0_END_ADDR21_HI32 6584 #define MMMC_VM_MX_L1_TLS0_END_ADDR21_HI32__END_ADDR_HI4__SHIFT 0x0 6585 #define MMMC_VM_MX_L1_TLS0_END_ADDR21_HI32__END_ADDR_HI4_MASK 0x0000000FL 6586 //MMMC_VM_MX_L1_TLS0_END_ADDR22_LO32 6587 #define MMMC_VM_MX_L1_TLS0_END_ADDR22_LO32__END_ADDR_LO32__SHIFT 0x0 6588 #define MMMC_VM_MX_L1_TLS0_END_ADDR22_LO32__END_ADDR_LO32_MASK 0xFFFFFFFFL 6589 //MMMC_VM_MX_L1_TLS0_END_ADDR22_HI32 6590 #define MMMC_VM_MX_L1_TLS0_END_ADDR22_HI32__END_ADDR_HI4__SHIFT 0x0 6591 #define MMMC_VM_MX_L1_TLS0_END_ADDR22_HI32__END_ADDR_HI4_MASK 0x0000000FL 6592 //MMMC_VM_MX_L1_TLS0_END_ADDR23_LO32 6593 #define MMMC_VM_MX_L1_TLS0_END_ADDR23_LO32__END_ADDR_LO32__SHIFT 0x0 6594 #define MMMC_VM_MX_L1_TLS0_END_ADDR23_LO32__END_ADDR_LO32_MASK 0xFFFFFFFFL 6595 //MMMC_VM_MX_L1_TLS0_END_ADDR23_HI32 6596 #define MMMC_VM_MX_L1_TLS0_END_ADDR23_HI32__END_ADDR_HI4__SHIFT 0x0 6597 #define MMMC_VM_MX_L1_TLS0_END_ADDR23_HI32__END_ADDR_HI4_MASK 0x0000000FL 6598 //MMMC_VM_MX_L1_TLS0_END_ADDR24_LO32 6599 #define MMMC_VM_MX_L1_TLS0_END_ADDR24_LO32__END_ADDR_LO32__SHIFT 0x0 6600 #define MMMC_VM_MX_L1_TLS0_END_ADDR24_LO32__END_ADDR_LO32_MASK 0xFFFFFFFFL 6601 //MMMC_VM_MX_L1_TLS0_END_ADDR24_HI32 6602 #define MMMC_VM_MX_L1_TLS0_END_ADDR24_HI32__END_ADDR_HI4__SHIFT 0x0 6603 #define MMMC_VM_MX_L1_TLS0_END_ADDR24_HI32__END_ADDR_HI4_MASK 0x0000000FL 6604 //MMMC_VM_MX_L1_TLS0_END_ADDR25_LO32 6605 #define MMMC_VM_MX_L1_TLS0_END_ADDR25_LO32__END_ADDR_LO32__SHIFT 0x0 6606 #define MMMC_VM_MX_L1_TLS0_END_ADDR25_LO32__END_ADDR_LO32_MASK 0xFFFFFFFFL 6607 //MMMC_VM_MX_L1_TLS0_END_ADDR25_HI32 6608 #define MMMC_VM_MX_L1_TLS0_END_ADDR25_HI32__END_ADDR_HI4__SHIFT 0x0 6609 #define MMMC_VM_MX_L1_TLS0_END_ADDR25_HI32__END_ADDR_HI4_MASK 0x0000000FL 6610 //MMMC_VM_MX_L1_TLS0_END_ADDR26_LO32 6611 #define MMMC_VM_MX_L1_TLS0_END_ADDR26_LO32__END_ADDR_LO32__SHIFT 0x0 6612 #define MMMC_VM_MX_L1_TLS0_END_ADDR26_LO32__END_ADDR_LO32_MASK 0xFFFFFFFFL 6613 //MMMC_VM_MX_L1_TLS0_END_ADDR26_HI32 6614 #define MMMC_VM_MX_L1_TLS0_END_ADDR26_HI32__END_ADDR_HI4__SHIFT 0x0 6615 #define MMMC_VM_MX_L1_TLS0_END_ADDR26_HI32__END_ADDR_HI4_MASK 0x0000000FL 6616 //MMMC_VM_MX_L1_TLS0_END_ADDR27_LO32 6617 #define MMMC_VM_MX_L1_TLS0_END_ADDR27_LO32__END_ADDR_LO32__SHIFT 0x0 6618 #define MMMC_VM_MX_L1_TLS0_END_ADDR27_LO32__END_ADDR_LO32_MASK 0xFFFFFFFFL 6619 //MMMC_VM_MX_L1_TLS0_END_ADDR27_HI32 6620 #define MMMC_VM_MX_L1_TLS0_END_ADDR27_HI32__END_ADDR_HI4__SHIFT 0x0 6621 #define MMMC_VM_MX_L1_TLS0_END_ADDR27_HI32__END_ADDR_HI4_MASK 0x0000000FL 6622 //MMMC_VM_MX_L1_TLS0_END_ADDR28_LO32 6623 #define MMMC_VM_MX_L1_TLS0_END_ADDR28_LO32__END_ADDR_LO32__SHIFT 0x0 6624 #define MMMC_VM_MX_L1_TLS0_END_ADDR28_LO32__END_ADDR_LO32_MASK 0xFFFFFFFFL 6625 //MMMC_VM_MX_L1_TLS0_END_ADDR28_HI32 6626 #define MMMC_VM_MX_L1_TLS0_END_ADDR28_HI32__END_ADDR_HI4__SHIFT 0x0 6627 #define MMMC_VM_MX_L1_TLS0_END_ADDR28_HI32__END_ADDR_HI4_MASK 0x0000000FL 6628 //MMMC_VM_MX_L1_TLS0_END_ADDR29_LO32 6629 #define MMMC_VM_MX_L1_TLS0_END_ADDR29_LO32__END_ADDR_LO32__SHIFT 0x0 6630 #define MMMC_VM_MX_L1_TLS0_END_ADDR29_LO32__END_ADDR_LO32_MASK 0xFFFFFFFFL 6631 //MMMC_VM_MX_L1_TLS0_END_ADDR29_HI32 6632 #define MMMC_VM_MX_L1_TLS0_END_ADDR29_HI32__END_ADDR_HI4__SHIFT 0x0 6633 #define MMMC_VM_MX_L1_TLS0_END_ADDR29_HI32__END_ADDR_HI4_MASK 0x0000000FL 6634 //MMMC_VM_MX_L1_TLS0_END_ADDR30_LO32 6635 #define MMMC_VM_MX_L1_TLS0_END_ADDR30_LO32__END_ADDR_LO32__SHIFT 0x0 6636 #define MMMC_VM_MX_L1_TLS0_END_ADDR30_LO32__END_ADDR_LO32_MASK 0xFFFFFFFFL 6637 //MMMC_VM_MX_L1_TLS0_END_ADDR30_HI32 6638 #define MMMC_VM_MX_L1_TLS0_END_ADDR30_HI32__END_ADDR_HI4__SHIFT 0x0 6639 #define MMMC_VM_MX_L1_TLS0_END_ADDR30_HI32__END_ADDR_HI4_MASK 0x0000000FL 6640 //MMMC_VM_MX_L1_TLS0_END_ADDR31_LO32 6641 #define MMMC_VM_MX_L1_TLS0_END_ADDR31_LO32__END_ADDR_LO32__SHIFT 0x0 6642 #define MMMC_VM_MX_L1_TLS0_END_ADDR31_LO32__END_ADDR_LO32_MASK 0xFFFFFFFFL 6643 //MMMC_VM_MX_L1_TLS0_END_ADDR31_HI32 6644 #define MMMC_VM_MX_L1_TLS0_END_ADDR31_HI32__END_ADDR_HI4__SHIFT 0x0 6645 #define MMMC_VM_MX_L1_TLS0_END_ADDR31_HI32__END_ADDR_HI4_MASK 0x0000000FL 6646 //MMMC_VM_MX_L1_TLS0_END_ADDR32_LO32 6647 #define MMMC_VM_MX_L1_TLS0_END_ADDR32_LO32__END_ADDR_LO32__SHIFT 0x0 6648 #define MMMC_VM_MX_L1_TLS0_END_ADDR32_LO32__END_ADDR_LO32_MASK 0xFFFFFFFFL 6649 //MMMC_VM_MX_L1_TLS0_END_ADDR32_HI32 6650 #define MMMC_VM_MX_L1_TLS0_END_ADDR32_HI32__END_ADDR_HI4__SHIFT 0x0 6651 #define MMMC_VM_MX_L1_TLS0_END_ADDR32_HI32__END_ADDR_HI4_MASK 0x0000000FL 6652 //MMMC_VM_MX_L1_TLS0_END_ADDR33_LO32 6653 #define MMMC_VM_MX_L1_TLS0_END_ADDR33_LO32__END_ADDR_LO32__SHIFT 0x0 6654 #define MMMC_VM_MX_L1_TLS0_END_ADDR33_LO32__END_ADDR_LO32_MASK 0xFFFFFFFFL 6655 //MMMC_VM_MX_L1_TLS0_END_ADDR33_HI32 6656 #define MMMC_VM_MX_L1_TLS0_END_ADDR33_HI32__END_ADDR_HI4__SHIFT 0x0 6657 #define MMMC_VM_MX_L1_TLS0_END_ADDR33_HI32__END_ADDR_HI4_MASK 0x0000000FL 6658 //MMMC_VM_MX_L1_TLS0_END_ADDR34_LO32 6659 #define MMMC_VM_MX_L1_TLS0_END_ADDR34_LO32__END_ADDR_LO32__SHIFT 0x0 6660 #define MMMC_VM_MX_L1_TLS0_END_ADDR34_LO32__END_ADDR_LO32_MASK 0xFFFFFFFFL 6661 //MMMC_VM_MX_L1_TLS0_END_ADDR34_HI32 6662 #define MMMC_VM_MX_L1_TLS0_END_ADDR34_HI32__END_ADDR_HI4__SHIFT 0x0 6663 #define MMMC_VM_MX_L1_TLS0_END_ADDR34_HI32__END_ADDR_HI4_MASK 0x0000000FL 6664 //MMMC_VM_MX_L1_TLS0_END_ADDR35_LO32 6665 #define MMMC_VM_MX_L1_TLS0_END_ADDR35_LO32__END_ADDR_LO32__SHIFT 0x0 6666 #define MMMC_VM_MX_L1_TLS0_END_ADDR35_LO32__END_ADDR_LO32_MASK 0xFFFFFFFFL 6667 //MMMC_VM_MX_L1_TLS0_END_ADDR35_HI32 6668 #define MMMC_VM_MX_L1_TLS0_END_ADDR35_HI32__END_ADDR_HI4__SHIFT 0x0 6669 #define MMMC_VM_MX_L1_TLS0_END_ADDR35_HI32__END_ADDR_HI4_MASK 0x0000000FL 6670 //MMMC_VM_MX_L1_TLS0_END_ADDR36_LO32 6671 #define MMMC_VM_MX_L1_TLS0_END_ADDR36_LO32__END_ADDR_LO32__SHIFT 0x0 6672 #define MMMC_VM_MX_L1_TLS0_END_ADDR36_LO32__END_ADDR_LO32_MASK 0xFFFFFFFFL 6673 //MMMC_VM_MX_L1_TLS0_END_ADDR36_HI32 6674 #define MMMC_VM_MX_L1_TLS0_END_ADDR36_HI32__END_ADDR_HI4__SHIFT 0x0 6675 #define MMMC_VM_MX_L1_TLS0_END_ADDR36_HI32__END_ADDR_HI4_MASK 0x0000000FL 6676 //MMMC_VM_MX_L1_TLS0_END_ADDR37_LO32 6677 #define MMMC_VM_MX_L1_TLS0_END_ADDR37_LO32__END_ADDR_LO32__SHIFT 0x0 6678 #define MMMC_VM_MX_L1_TLS0_END_ADDR37_LO32__END_ADDR_LO32_MASK 0xFFFFFFFFL 6679 //MMMC_VM_MX_L1_TLS0_END_ADDR37_HI32 6680 #define MMMC_VM_MX_L1_TLS0_END_ADDR37_HI32__END_ADDR_HI4__SHIFT 0x0 6681 #define MMMC_VM_MX_L1_TLS0_END_ADDR37_HI32__END_ADDR_HI4_MASK 0x0000000FL 6682 //MMMC_VM_MX_L1_TLS0_INVALIDATE_STREAM_LO32 6683 #define MMMC_VM_MX_L1_TLS0_INVALIDATE_STREAM_LO32__INVALIDATE_STREAM_LO32__SHIFT 0x0 6684 #define MMMC_VM_MX_L1_TLS0_INVALIDATE_STREAM_LO32__INVALIDATE_STREAM_LO32_MASK 0xFFFFFFFFL 6685 //MMMC_VM_MX_L1_TLS0_INVALIDATE_STREAM_HI32 6686 #define MMMC_VM_MX_L1_TLS0_INVALIDATE_STREAM_HI32__INVALIDATE_STREAM_HI6__SHIFT 0x0 6687 #define MMMC_VM_MX_L1_TLS0_INVALIDATE_STREAM_HI32__INVALIDATE_STREAM_HI6_MASK 0x0000003FL 6688 //MMMC_VM_MX_L1_TLS0_INVALIDATE_REQUEST_PENDING_LO32 6689 #define MMMC_VM_MX_L1_TLS0_INVALIDATE_REQUEST_PENDING_LO32__INVALIDATE_REQUEST_PENDING_LO32__SHIFT 0x0 6690 #define MMMC_VM_MX_L1_TLS0_INVALIDATE_REQUEST_PENDING_LO32__INVALIDATE_REQUEST_PENDING_LO32_MASK 0xFFFFFFFFL 6691 //MMMC_VM_MX_L1_TLS0_INVALIDATE_REQUEST_PENDING_HI32 6692 #define MMMC_VM_MX_L1_TLS0_INVALIDATE_REQUEST_PENDING_HI32__INVALIDATE_REQUEST_PENDING_HI6__SHIFT 0x0 6693 #define MMMC_VM_MX_L1_TLS0_INVALIDATE_REQUEST_PENDING_HI32__INVALIDATE_REQUEST_PENDING_HI6_MASK 0x0000003FL 6694 //MMMC_VM_MX_L1_TLS0_PROTECTION_FAULT_STATUS 6695 #define MMMC_VM_MX_L1_TLS0_PROTECTION_FAULT_STATUS__PROTECTIONS__SHIFT 0x0 6696 #define MMMC_VM_MX_L1_TLS0_PROTECTION_FAULT_STATUS__MEMORY_CLIENT_ID__SHIFT 0xc 6697 #define MMMC_VM_MX_L1_TLS0_PROTECTION_FAULT_STATUS__MEMORY_CLIENT_RW__SHIFT 0x18 6698 #define MMMC_VM_MX_L1_TLS0_PROTECTION_FAULT_STATUS__VMID__SHIFT 0x19 6699 #define MMMC_VM_MX_L1_TLS0_PROTECTION_FAULT_STATUS__ATOMIC__SHIFT 0x1d 6700 #define MMMC_VM_MX_L1_TLS0_PROTECTION_FAULT_STATUS__PROTECTIONS_MASK 0x000000FFL 6701 #define MMMC_VM_MX_L1_TLS0_PROTECTION_FAULT_STATUS__MEMORY_CLIENT_ID_MASK 0x001FF000L 6702 #define MMMC_VM_MX_L1_TLS0_PROTECTION_FAULT_STATUS__MEMORY_CLIENT_RW_MASK 0x01000000L 6703 #define MMMC_VM_MX_L1_TLS0_PROTECTION_FAULT_STATUS__VMID_MASK 0x1E000000L 6704 #define MMMC_VM_MX_L1_TLS0_PROTECTION_FAULT_STATUS__ATOMIC_MASK 0x20000000L 6705 //MMMC_VM_MX_L1_TLS0_PROTECTION_FAULT_ADDR_LO32 6706 #define MMMC_VM_MX_L1_TLS0_PROTECTION_FAULT_ADDR_LO32__LOGICAL_PAGE_ADDR_LO32__SHIFT 0x0 6707 #define MMMC_VM_MX_L1_TLS0_PROTECTION_FAULT_ADDR_LO32__LOGICAL_PAGE_ADDR_LO32_MASK 0xFFFFFFFFL 6708 //MMMC_VM_MX_L1_TLS0_PROTECTION_FAULT_ADDR_HI32 6709 #define MMMC_VM_MX_L1_TLS0_PROTECTION_FAULT_ADDR_HI32__LOGICAL_PAGE_ADDR_HI4__SHIFT 0x0 6710 #define MMMC_VM_MX_L1_TLS0_PROTECTION_FAULT_ADDR_HI32__LOGICAL_PAGE_ADDR_HI4_MASK 0x0000000FL 6711 //MMVM_L2_SAW_CNTL 6712 #define MMVM_L2_SAW_CNTL__ENABLE_L2_CACHE__SHIFT 0x0 6713 #define MMVM_L2_SAW_CNTL__ENABLE_L2_FRAGMENT_PROCESSING__SHIFT 0x1 6714 #define MMVM_L2_SAW_CNTL__L2_CACHE_PTE_ENDIAN_SWAP_MODE__SHIFT 0x2 6715 #define MMVM_L2_SAW_CNTL__L2_CACHE_PDE_ENDIAN_SWAP_MODE__SHIFT 0x4 6716 #define MMVM_L2_SAW_CNTL__L2_PDE0_CACHE_TAG_GENERATION_MODE__SHIFT 0x8 6717 #define MMVM_L2_SAW_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE__SHIFT 0x9 6718 #define MMVM_L2_SAW_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE__SHIFT 0xa 6719 #define MMVM_L2_SAW_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY__SHIFT 0xb 6720 #define MMVM_L2_SAW_CNTL__L2_PDE0_CACHE_SPLIT_MODE__SHIFT 0xc 6721 #define MMVM_L2_SAW_CNTL__EFFECTIVE_L2_QUEUE_SIZE__SHIFT 0xf 6722 #define MMVM_L2_SAW_CNTL__PDE_FAULT_CLASSIFICATION__SHIFT 0x12 6723 #define MMVM_L2_SAW_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE__SHIFT 0x13 6724 #define MMVM_L2_SAW_CNTL__IDENTITY_MODE_FRAGMENT_SIZE__SHIFT 0x15 6725 #define MMVM_L2_SAW_CNTL__L2_CACHE_4K_SWAP_TAG_INDEX_LSBS__SHIFT 0x1a 6726 #define MMVM_L2_SAW_CNTL__L2_CACHE_BIGK_SWAP_TAG_INDEX_LSBS__SHIFT 0x1c 6727 #define MMVM_L2_SAW_CNTL__ENABLE_L2_CACHE_MASK 0x00000001L 6728 #define MMVM_L2_SAW_CNTL__ENABLE_L2_FRAGMENT_PROCESSING_MASK 0x00000002L 6729 #define MMVM_L2_SAW_CNTL__L2_CACHE_PTE_ENDIAN_SWAP_MODE_MASK 0x0000000CL 6730 #define MMVM_L2_SAW_CNTL__L2_CACHE_PDE_ENDIAN_SWAP_MODE_MASK 0x00000030L 6731 #define MMVM_L2_SAW_CNTL__L2_PDE0_CACHE_TAG_GENERATION_MODE_MASK 0x00000100L 6732 #define MMVM_L2_SAW_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE_MASK 0x00000200L 6733 #define MMVM_L2_SAW_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE_MASK 0x00000400L 6734 #define MMVM_L2_SAW_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY_MASK 0x00000800L 6735 #define MMVM_L2_SAW_CNTL__L2_PDE0_CACHE_SPLIT_MODE_MASK 0x00007000L 6736 #define MMVM_L2_SAW_CNTL__EFFECTIVE_L2_QUEUE_SIZE_MASK 0x00038000L 6737 #define MMVM_L2_SAW_CNTL__PDE_FAULT_CLASSIFICATION_MASK 0x00040000L 6738 #define MMVM_L2_SAW_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE_MASK 0x00180000L 6739 #define MMVM_L2_SAW_CNTL__IDENTITY_MODE_FRAGMENT_SIZE_MASK 0x03E00000L 6740 #define MMVM_L2_SAW_CNTL__L2_CACHE_4K_SWAP_TAG_INDEX_LSBS_MASK 0x0C000000L 6741 #define MMVM_L2_SAW_CNTL__L2_CACHE_BIGK_SWAP_TAG_INDEX_LSBS_MASK 0x70000000L 6742 //MMVM_L2_SAW_CNTL2 6743 #define MMVM_L2_SAW_CNTL2__INVALIDATE_ALL_L1_TLBS__SHIFT 0x0 6744 #define MMVM_L2_SAW_CNTL2__INVALIDATE_L2_CACHE__SHIFT 0x1 6745 #define MMVM_L2_SAW_CNTL2__DISABLE_INVALIDATE_PER_DOMAIN__SHIFT 0x15 6746 #define MMVM_L2_SAW_CNTL2__DISABLE_BIGK_CACHE_OPTIMIZATION__SHIFT 0x16 6747 #define MMVM_L2_SAW_CNTL2__L2_CACHE_BIGK_VMID_MODE__SHIFT 0x17 6748 #define MMVM_L2_SAW_CNTL2__INVALIDATE_CACHE_MODE__SHIFT 0x1a 6749 #define MMVM_L2_SAW_CNTL2__PDE_CACHE_EFFECTIVE_SIZE__SHIFT 0x1c 6750 #define MMVM_L2_SAW_CNTL2__INVALIDATE_ALL_L1_TLBS_MASK 0x00000001L 6751 #define MMVM_L2_SAW_CNTL2__INVALIDATE_L2_CACHE_MASK 0x00000002L 6752 #define MMVM_L2_SAW_CNTL2__DISABLE_INVALIDATE_PER_DOMAIN_MASK 0x00200000L 6753 #define MMVM_L2_SAW_CNTL2__DISABLE_BIGK_CACHE_OPTIMIZATION_MASK 0x00400000L 6754 #define MMVM_L2_SAW_CNTL2__L2_CACHE_BIGK_VMID_MODE_MASK 0x03800000L 6755 #define MMVM_L2_SAW_CNTL2__INVALIDATE_CACHE_MODE_MASK 0x0C000000L 6756 #define MMVM_L2_SAW_CNTL2__PDE_CACHE_EFFECTIVE_SIZE_MASK 0x70000000L 6757 //MMVM_L2_SAW_CNTL3 6758 #define MMVM_L2_SAW_CNTL3__BANK_SELECT__SHIFT 0x0 6759 #define MMVM_L2_SAW_CNTL3__L2_CACHE_UPDATE_MODE__SHIFT 0x6 6760 #define MMVM_L2_SAW_CNTL3__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE__SHIFT 0x8 6761 #define MMVM_L2_SAW_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0xf 6762 #define MMVM_L2_SAW_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY__SHIFT 0x14 6763 #define MMVM_L2_SAW_CNTL3__L2_CACHE_4K_EFFECTIVE_SIZE__SHIFT 0x15 6764 #define MMVM_L2_SAW_CNTL3__L2_CACHE_BIGK_EFFECTIVE_SIZE__SHIFT 0x18 6765 #define MMVM_L2_SAW_CNTL3__L2_CACHE_4K_FORCE_MISS__SHIFT 0x1c 6766 #define MMVM_L2_SAW_CNTL3__L2_CACHE_BIGK_FORCE_MISS__SHIFT 0x1d 6767 #define MMVM_L2_SAW_CNTL3__PDE_CACHE_FORCE_MISS__SHIFT 0x1e 6768 #define MMVM_L2_SAW_CNTL3__L2_CACHE_4K_ASSOCIATIVITY__SHIFT 0x1f 6769 #define MMVM_L2_SAW_CNTL3__BANK_SELECT_MASK 0x0000003FL 6770 #define MMVM_L2_SAW_CNTL3__L2_CACHE_UPDATE_MODE_MASK 0x000000C0L 6771 #define MMVM_L2_SAW_CNTL3__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE_MASK 0x00001F00L 6772 #define MMVM_L2_SAW_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000F8000L 6773 #define MMVM_L2_SAW_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY_MASK 0x00100000L 6774 #define MMVM_L2_SAW_CNTL3__L2_CACHE_4K_EFFECTIVE_SIZE_MASK 0x00E00000L 6775 #define MMVM_L2_SAW_CNTL3__L2_CACHE_BIGK_EFFECTIVE_SIZE_MASK 0x0F000000L 6776 #define MMVM_L2_SAW_CNTL3__L2_CACHE_4K_FORCE_MISS_MASK 0x10000000L 6777 #define MMVM_L2_SAW_CNTL3__L2_CACHE_BIGK_FORCE_MISS_MASK 0x20000000L 6778 #define MMVM_L2_SAW_CNTL3__PDE_CACHE_FORCE_MISS_MASK 0x40000000L 6779 #define MMVM_L2_SAW_CNTL3__L2_CACHE_4K_ASSOCIATIVITY_MASK 0x80000000L 6780 //MMVM_L2_SAW_CNTL4 6781 #define MMVM_L2_SAW_CNTL4__L2_CACHE_4K_PARTITION_COUNT__SHIFT 0x0 6782 #define MMVM_L2_SAW_CNTL4__VMC_TAP_CONTEXT0_PDE_REQUEST_PHYSICAL__SHIFT 0x6 6783 #define MMVM_L2_SAW_CNTL4__VMC_TAP_CONTEXT0_PDE_REQUEST_SHARED__SHIFT 0x7 6784 #define MMVM_L2_SAW_CNTL4__VMC_TAP_CONTEXT0_PDE_REQUEST_SNOOP__SHIFT 0x8 6785 #define MMVM_L2_SAW_CNTL4__VMC_TAP_CONTEXT0_PTE_REQUEST_PHYSICAL__SHIFT 0x9 6786 #define MMVM_L2_SAW_CNTL4__VMC_TAP_CONTEXT0_PTE_REQUEST_SHARED__SHIFT 0xa 6787 #define MMVM_L2_SAW_CNTL4__VMC_TAP_CONTEXT0_PTE_REQUEST_SNOOP__SHIFT 0xb 6788 #define MMVM_L2_SAW_CNTL4__VMC_TAP_CONTEXT1_PDE_REQUEST_PHYSICAL__SHIFT 0xc 6789 #define MMVM_L2_SAW_CNTL4__VMC_TAP_CONTEXT1_PDE_REQUEST_SHARED__SHIFT 0xd 6790 #define MMVM_L2_SAW_CNTL4__VMC_TAP_CONTEXT1_PDE_REQUEST_SNOOP__SHIFT 0xe 6791 #define MMVM_L2_SAW_CNTL4__VMC_TAP_CONTEXT1_PTE_REQUEST_PHYSICAL__SHIFT 0xf 6792 #define MMVM_L2_SAW_CNTL4__VMC_TAP_CONTEXT1_PTE_REQUEST_SHARED__SHIFT 0x10 6793 #define MMVM_L2_SAW_CNTL4__VMC_TAP_CONTEXT1_PTE_REQUEST_SNOOP__SHIFT 0x11 6794 #define MMVM_L2_SAW_CNTL4__L2_CACHE_4K_LRU_ADDR_MATCHING__SHIFT 0x12 6795 #define MMVM_L2_SAW_CNTL4__L2_CACHE_4K_PARTITION_COUNT_MASK 0x0000003FL 6796 #define MMVM_L2_SAW_CNTL4__VMC_TAP_CONTEXT0_PDE_REQUEST_PHYSICAL_MASK 0x00000040L 6797 #define MMVM_L2_SAW_CNTL4__VMC_TAP_CONTEXT0_PDE_REQUEST_SHARED_MASK 0x00000080L 6798 #define MMVM_L2_SAW_CNTL4__VMC_TAP_CONTEXT0_PDE_REQUEST_SNOOP_MASK 0x00000100L 6799 #define MMVM_L2_SAW_CNTL4__VMC_TAP_CONTEXT0_PTE_REQUEST_PHYSICAL_MASK 0x00000200L 6800 #define MMVM_L2_SAW_CNTL4__VMC_TAP_CONTEXT0_PTE_REQUEST_SHARED_MASK 0x00000400L 6801 #define MMVM_L2_SAW_CNTL4__VMC_TAP_CONTEXT0_PTE_REQUEST_SNOOP_MASK 0x00000800L 6802 #define MMVM_L2_SAW_CNTL4__VMC_TAP_CONTEXT1_PDE_REQUEST_PHYSICAL_MASK 0x00001000L 6803 #define MMVM_L2_SAW_CNTL4__VMC_TAP_CONTEXT1_PDE_REQUEST_SHARED_MASK 0x00002000L 6804 #define MMVM_L2_SAW_CNTL4__VMC_TAP_CONTEXT1_PDE_REQUEST_SNOOP_MASK 0x00004000L 6805 #define MMVM_L2_SAW_CNTL4__VMC_TAP_CONTEXT1_PTE_REQUEST_PHYSICAL_MASK 0x00008000L 6806 #define MMVM_L2_SAW_CNTL4__VMC_TAP_CONTEXT1_PTE_REQUEST_SHARED_MASK 0x00010000L 6807 #define MMVM_L2_SAW_CNTL4__VMC_TAP_CONTEXT1_PTE_REQUEST_SNOOP_MASK 0x00020000L 6808 #define MMVM_L2_SAW_CNTL4__L2_CACHE_4K_LRU_ADDR_MATCHING_MASK 0x00040000L 6809 //MMVM_L2_SAW_CONTEXT0_CNTL 6810 #define MMVM_L2_SAW_CONTEXT0_CNTL__ENABLE_CONTEXT__SHIFT 0x0 6811 #define MMVM_L2_SAW_CONTEXT0_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 6812 #define MMVM_L2_SAW_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x3 6813 #define MMVM_L2_SAW_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x4 6814 #define MMVM_L2_SAW_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x6 6815 #define MMVM_L2_SAW_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x7 6816 #define MMVM_L2_SAW_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 6817 #define MMVM_L2_SAW_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa 6818 #define MMVM_L2_SAW_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_SAVE__SHIFT 0xb 6819 #define MMVM_L2_SAW_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xc 6820 #define MMVM_L2_SAW_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xd 6821 #define MMVM_L2_SAW_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_SAVE__SHIFT 0xe 6822 #define MMVM_L2_SAW_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf 6823 #define MMVM_L2_SAW_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 6824 #define MMVM_L2_SAW_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_SAVE__SHIFT 0x11 6825 #define MMVM_L2_SAW_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x12 6826 #define MMVM_L2_SAW_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x13 6827 #define MMVM_L2_SAW_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_SAVE__SHIFT 0x14 6828 #define MMVM_L2_SAW_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 6829 #define MMVM_L2_SAW_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 6830 #define MMVM_L2_SAW_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_SAVE__SHIFT 0x17 6831 #define MMVM_L2_SAW_CONTEXT0_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x18 6832 #define MMVM_L2_SAW_CONTEXT0_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x1c 6833 #define MMVM_L2_SAW_CONTEXT0_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x1d 6834 #define MMVM_L2_SAW_CONTEXT0_CNTL__ENABLE_CONTEXT_MASK 0x00000001L 6835 #define MMVM_L2_SAW_CONTEXT0_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L 6836 #define MMVM_L2_SAW_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000008L 6837 #define MMVM_L2_SAW_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000010L 6838 #define MMVM_L2_SAW_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000040L 6839 #define MMVM_L2_SAW_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000080L 6840 #define MMVM_L2_SAW_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L 6841 #define MMVM_L2_SAW_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L 6842 #define MMVM_L2_SAW_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_SAVE_MASK 0x00000800L 6843 #define MMVM_L2_SAW_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00001000L 6844 #define MMVM_L2_SAW_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00002000L 6845 #define MMVM_L2_SAW_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_SAVE_MASK 0x00004000L 6846 #define MMVM_L2_SAW_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L 6847 #define MMVM_L2_SAW_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L 6848 #define MMVM_L2_SAW_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_SAVE_MASK 0x00020000L 6849 #define MMVM_L2_SAW_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00040000L 6850 #define MMVM_L2_SAW_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00080000L 6851 #define MMVM_L2_SAW_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_SAVE_MASK 0x00100000L 6852 #define MMVM_L2_SAW_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L 6853 #define MMVM_L2_SAW_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L 6854 #define MMVM_L2_SAW_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_SAVE_MASK 0x00800000L 6855 #define MMVM_L2_SAW_CONTEXT0_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x0F000000L 6856 #define MMVM_L2_SAW_CONTEXT0_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x10000000L 6857 #define MMVM_L2_SAW_CONTEXT0_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x20000000L 6858 //MMVM_L2_SAW_CONTEXT0_CNTL2 6859 #define MMVM_L2_SAW_CONTEXT0_CNTL2__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x0 6860 #define MMVM_L2_SAW_CONTEXT0_CNTL2__ENABLE_CLEAR_PROTECTION_FAULT_STATUS_ADDR_WHEN_INVALIDATE_CONTEXT__SHIFT 0x1 6861 #define MMVM_L2_SAW_CONTEXT0_CNTL2__ENABLE_INTERRUPT_PROCESSING_FOR_SUBSEQUENT_FAULTS_PER_CONTEXT__SHIFT 0x2 6862 #define MMVM_L2_SAW_CONTEXT0_CNTL2__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES__SHIFT 0x3 6863 #define MMVM_L2_SAW_CONTEXT0_CNTL2__WAIT_FOR_IDLE_WHEN_INVALIDATE__SHIFT 0x4 6864 #define MMVM_L2_SAW_CONTEXT0_CNTL2__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00000001L 6865 #define MMVM_L2_SAW_CONTEXT0_CNTL2__ENABLE_CLEAR_PROTECTION_FAULT_STATUS_ADDR_WHEN_INVALIDATE_CONTEXT_MASK 0x00000002L 6866 #define MMVM_L2_SAW_CONTEXT0_CNTL2__ENABLE_INTERRUPT_PROCESSING_FOR_SUBSEQUENT_FAULTS_PER_CONTEXT_MASK 0x00000004L 6867 #define MMVM_L2_SAW_CONTEXT0_CNTL2__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES_MASK 0x00000008L 6868 #define MMVM_L2_SAW_CONTEXT0_CNTL2__WAIT_FOR_IDLE_WHEN_INVALIDATE_MASK 0x00000010L 6869 //MMVM_L2_SAW_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32 6870 #define MMVM_L2_SAW_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32__PHYSICAL_PAGE_NUMBER_LO32__SHIFT 0x0 6871 #define MMVM_L2_SAW_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32__PHYSICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 6872 //MMVM_L2_SAW_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32 6873 #define MMVM_L2_SAW_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32__PHYSICAL_PAGE_NUMBER_HI4__SHIFT 0x0 6874 #define MMVM_L2_SAW_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32__PHYSICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 6875 //MMVM_L2_SAW_CONTEXT0_PAGE_TABLE_START_ADDR_LO32 6876 #define MMVM_L2_SAW_CONTEXT0_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 6877 #define MMVM_L2_SAW_CONTEXT0_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 6878 //MMVM_L2_SAW_CONTEXT0_PAGE_TABLE_START_ADDR_HI32 6879 #define MMVM_L2_SAW_CONTEXT0_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 6880 #define MMVM_L2_SAW_CONTEXT0_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 6881 //MMVM_L2_SAW_CONTEXT0_PAGE_TABLE_END_ADDR_LO32 6882 #define MMVM_L2_SAW_CONTEXT0_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 6883 #define MMVM_L2_SAW_CONTEXT0_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 6884 //MMVM_L2_SAW_CONTEXT0_PAGE_TABLE_END_ADDR_HI32 6885 #define MMVM_L2_SAW_CONTEXT0_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 6886 #define MMVM_L2_SAW_CONTEXT0_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 6887 //MMVM_L2_SAW_CONTEXTS_DISABLE 6888 #define MMVM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_0__SHIFT 0x0 6889 #define MMVM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_1__SHIFT 0x1 6890 #define MMVM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_2__SHIFT 0x2 6891 #define MMVM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_3__SHIFT 0x3 6892 #define MMVM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_4__SHIFT 0x4 6893 #define MMVM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_5__SHIFT 0x5 6894 #define MMVM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_6__SHIFT 0x6 6895 #define MMVM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_7__SHIFT 0x7 6896 #define MMVM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_8__SHIFT 0x8 6897 #define MMVM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_9__SHIFT 0x9 6898 #define MMVM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_10__SHIFT 0xa 6899 #define MMVM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_11__SHIFT 0xb 6900 #define MMVM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_12__SHIFT 0xc 6901 #define MMVM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_13__SHIFT 0xd 6902 #define MMVM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_14__SHIFT 0xe 6903 #define MMVM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_15__SHIFT 0xf 6904 #define MMVM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_0_MASK 0x00000001L 6905 #define MMVM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_1_MASK 0x00000002L 6906 #define MMVM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_2_MASK 0x00000004L 6907 #define MMVM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_3_MASK 0x00000008L 6908 #define MMVM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_4_MASK 0x00000010L 6909 #define MMVM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_5_MASK 0x00000020L 6910 #define MMVM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_6_MASK 0x00000040L 6911 #define MMVM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_7_MASK 0x00000080L 6912 #define MMVM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_8_MASK 0x00000100L 6913 #define MMVM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_9_MASK 0x00000200L 6914 #define MMVM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_10_MASK 0x00000400L 6915 #define MMVM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_11_MASK 0x00000800L 6916 #define MMVM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_12_MASK 0x00001000L 6917 #define MMVM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_13_MASK 0x00002000L 6918 #define MMVM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_14_MASK 0x00004000L 6919 #define MMVM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_15_MASK 0x00008000L 6920 //MMVM_L2_SAW_PIPES_BUSY_LO32 6921 #define MMVM_L2_SAW_PIPES_BUSY_LO32__PIPES_BUSY_LO32__SHIFT 0x0 6922 #define MMVM_L2_SAW_PIPES_BUSY_LO32__PIPES_BUSY_LO32_MASK 0xFFFFFFFFL 6923 //MMVM_L2_SAW_PIPES_BUSY_HI32 6924 #define MMVM_L2_SAW_PIPES_BUSY_HI32__PIPES_BUSY_HI32__SHIFT 0x0 6925 #define MMVM_L2_SAW_PIPES_BUSY_HI32__PIPES_BUSY_HI32_MASK 0xFFFFFFFFL 6926 //MMMC_VM_MX_L1_TLS0_IOMMU_FAULT_STATUS 6927 #define MMMC_VM_MX_L1_TLS0_IOMMU_FAULT_STATUS__MORE_FAULTS__SHIFT 0x0 6928 #define MMMC_VM_MX_L1_TLS0_IOMMU_FAULT_STATUS__ABORT_STATUS__SHIFT 0x1 6929 #define MMMC_VM_MX_L1_TLS0_IOMMU_FAULT_STATUS__STREAM_ID__SHIFT 0x3 6930 #define MMMC_VM_MX_L1_TLS0_IOMMU_FAULT_STATUS__MORE_FAULTS_MASK 0x00000001L 6931 #define MMMC_VM_MX_L1_TLS0_IOMMU_FAULT_STATUS__ABORT_STATUS_MASK 0x00000006L 6932 #define MMMC_VM_MX_L1_TLS0_IOMMU_FAULT_STATUS__STREAM_ID_MASK 0x000001F8L 6933 //MMMC_VM_MX_L1_TLS0_IOMMU_FAULT_GVADDR_LO32 6934 #define MMMC_VM_MX_L1_TLS0_IOMMU_FAULT_GVADDR_LO32__LOGICAL_PAGE_ADDR_LO32__SHIFT 0x0 6935 #define MMMC_VM_MX_L1_TLS0_IOMMU_FAULT_GVADDR_LO32__LOGICAL_PAGE_ADDR_LO32_MASK 0xFFFFFFFFL 6936 //MMMC_VM_MX_L1_TLS0_IOMMU_FAULT_GVADDR_HI32 6937 #define MMMC_VM_MX_L1_TLS0_IOMMU_FAULT_GVADDR_HI32__LOGICAL_PAGE_ADDR_HI4__SHIFT 0x0 6938 #define MMMC_VM_MX_L1_TLS0_IOMMU_FAULT_GVADDR_HI32__LOGICAL_PAGE_ADDR_HI4_MASK 0x0000000FL 6939 6940 6941 // addressBlock: mmhub_mmutcl2_mmatcl2dec 6942 //MM_ATC_L2_CNTL 6943 #define MM_ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READ_REQUESTS__SHIFT 0x0 6944 #define MM_ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITE_REQUESTS__SHIFT 0x3 6945 #define MM_ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READS_DEPENDS_ON_ADDR_MOD__SHIFT 0x6 6946 #define MM_ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITES_DEPENDS_ON_ADDR_MOD__SHIFT 0x7 6947 #define MM_ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_READ_REQUESTS__SHIFT 0x8 6948 #define MM_ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_WRITE_REQUESTS__SHIFT 0xb 6949 #define MM_ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_READS_DEPENDS_ON_ADDR_MOD__SHIFT 0xe 6950 #define MM_ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_WRITES_DEPENDS_ON_ADDR_MOD__SHIFT 0xf 6951 #define MM_ATC_L2_CNTL__CACHE_INVALIDATE_MODE__SHIFT 0x10 6952 #define MM_ATC_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY__SHIFT 0x13 6953 #define MM_ATC_L2_CNTL__FRAG_APT_INTXN_MODE__SHIFT 0x14 6954 #define MM_ATC_L2_CNTL__CLI_GPA_REQ_FRAG_SIZE__SHIFT 0x16 6955 #define MM_ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READ_REQUESTS_MASK 0x00000003L 6956 #define MM_ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITE_REQUESTS_MASK 0x00000018L 6957 #define MM_ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READS_DEPENDS_ON_ADDR_MOD_MASK 0x00000040L 6958 #define MM_ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITES_DEPENDS_ON_ADDR_MOD_MASK 0x00000080L 6959 #define MM_ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_READ_REQUESTS_MASK 0x00000300L 6960 #define MM_ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_WRITE_REQUESTS_MASK 0x00001800L 6961 #define MM_ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_READS_DEPENDS_ON_ADDR_MOD_MASK 0x00004000L 6962 #define MM_ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_WRITES_DEPENDS_ON_ADDR_MOD_MASK 0x00008000L 6963 #define MM_ATC_L2_CNTL__CACHE_INVALIDATE_MODE_MASK 0x00070000L 6964 #define MM_ATC_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY_MASK 0x00080000L 6965 #define MM_ATC_L2_CNTL__FRAG_APT_INTXN_MODE_MASK 0x00300000L 6966 #define MM_ATC_L2_CNTL__CLI_GPA_REQ_FRAG_SIZE_MASK 0x0FC00000L 6967 //MM_ATC_L2_CNTL2 6968 #define MM_ATC_L2_CNTL2__BANK_SELECT__SHIFT 0x0 6969 #define MM_ATC_L2_CNTL2__L2_CACHE_UPDATE_MODE__SHIFT 0x6 6970 #define MM_ATC_L2_CNTL2__ENABLE_L2_CACHE_LRU_UPDATE_BY_WRITE__SHIFT 0x8 6971 #define MM_ATC_L2_CNTL2__L2_CACHE_SWAP_TAG_INDEX_LSBS__SHIFT 0x9 6972 #define MM_ATC_L2_CNTL2__L2_CACHE_VMID_MODE__SHIFT 0xc 6973 #define MM_ATC_L2_CNTL2__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE__SHIFT 0xf 6974 #define MM_ATC_L2_CNTL2__BANK_SELECT_MASK 0x0000003FL 6975 #define MM_ATC_L2_CNTL2__L2_CACHE_UPDATE_MODE_MASK 0x000000C0L 6976 #define MM_ATC_L2_CNTL2__ENABLE_L2_CACHE_LRU_UPDATE_BY_WRITE_MASK 0x00000100L 6977 #define MM_ATC_L2_CNTL2__L2_CACHE_SWAP_TAG_INDEX_LSBS_MASK 0x00000E00L 6978 #define MM_ATC_L2_CNTL2__L2_CACHE_VMID_MODE_MASK 0x00007000L 6979 #define MM_ATC_L2_CNTL2__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE_MASK 0x001F8000L 6980 //MM_ATC_L2_CACHE_DATA0 6981 #define MM_ATC_L2_CACHE_DATA0__DATA_REGISTER_VALID__SHIFT 0x0 6982 #define MM_ATC_L2_CACHE_DATA0__CACHE_ENTRY_VALID__SHIFT 0x1 6983 #define MM_ATC_L2_CACHE_DATA0__CACHED_ATTRIBUTES__SHIFT 0x2 6984 #define MM_ATC_L2_CACHE_DATA0__VIRTUAL_PAGE_ADDRESS_HIGH__SHIFT 0x18 6985 #define MM_ATC_L2_CACHE_DATA0__DATA_REGISTER_VALID_MASK 0x00000001L 6986 #define MM_ATC_L2_CACHE_DATA0__CACHE_ENTRY_VALID_MASK 0x00000002L 6987 #define MM_ATC_L2_CACHE_DATA0__CACHED_ATTRIBUTES_MASK 0x00FFFFFCL 6988 #define MM_ATC_L2_CACHE_DATA0__VIRTUAL_PAGE_ADDRESS_HIGH_MASK 0x0F000000L 6989 //MM_ATC_L2_CACHE_DATA1 6990 #define MM_ATC_L2_CACHE_DATA1__VIRTUAL_PAGE_ADDRESS_LOW__SHIFT 0x0 6991 #define MM_ATC_L2_CACHE_DATA1__VIRTUAL_PAGE_ADDRESS_LOW_MASK 0xFFFFFFFFL 6992 //MM_ATC_L2_CACHE_DATA2 6993 #define MM_ATC_L2_CACHE_DATA2__PHYSICAL_PAGE_ADDRESS__SHIFT 0x0 6994 #define MM_ATC_L2_CACHE_DATA2__PHYSICAL_PAGE_ADDRESS_MASK 0xFFFFFFFFL 6995 //MM_ATC_L2_CNTL3 6996 #define MM_ATC_L2_CNTL3__L2_SMALLK_CACHE_FRAGMENT_SIZE__SHIFT 0x0 6997 #define MM_ATC_L2_CNTL3__L2_MIDK_CACHE_FRAGMENT_SIZE__SHIFT 0x6 6998 #define MM_ATC_L2_CNTL3__L2_BIGK_CACHE_FRAGMENT_SIZE__SHIFT 0xc 6999 #define MM_ATC_L2_CNTL3__DELAY_SEND_INVALIDATION_REQUEST__SHIFT 0x12 7000 #define MM_ATC_L2_CNTL3__ATS_REQUEST_CREDIT_MINUS1__SHIFT 0x15 7001 #define MM_ATC_L2_CNTL3__COMPCLKREQ_OFF_HYSTERESIS__SHIFT 0x1b 7002 #define MM_ATC_L2_CNTL3__L2_SMALLK_CACHE_FRAGMENT_SIZE_MASK 0x0000003FL 7003 #define MM_ATC_L2_CNTL3__L2_MIDK_CACHE_FRAGMENT_SIZE_MASK 0x00000FC0L 7004 #define MM_ATC_L2_CNTL3__L2_BIGK_CACHE_FRAGMENT_SIZE_MASK 0x0003F000L 7005 #define MM_ATC_L2_CNTL3__DELAY_SEND_INVALIDATION_REQUEST_MASK 0x001C0000L 7006 #define MM_ATC_L2_CNTL3__ATS_REQUEST_CREDIT_MINUS1_MASK 0x07E00000L 7007 #define MM_ATC_L2_CNTL3__COMPCLKREQ_OFF_HYSTERESIS_MASK 0x38000000L 7008 //MM_ATC_L2_CNTL4 7009 #define MM_ATC_L2_CNTL4__L2_RT_SMALLK_CACHE_FRAGMENT_SIZE__SHIFT 0x0 7010 #define MM_ATC_L2_CNTL4__L2_RT_MIDK_CACHE_FRAGMENT_SIZE__SHIFT 0x6 7011 #define MM_ATC_L2_CNTL4__L2_RT_BIGK_CACHE_FRAGMENT_SIZE__SHIFT 0xc 7012 #define MM_ATC_L2_CNTL4__L2_RT_SMALLK_CACHE_FRAGMENT_SIZE_MASK 0x0000003FL 7013 #define MM_ATC_L2_CNTL4__L2_RT_MIDK_CACHE_FRAGMENT_SIZE_MASK 0x00000FC0L 7014 #define MM_ATC_L2_CNTL4__L2_RT_BIGK_CACHE_FRAGMENT_SIZE_MASK 0x0003F000L 7015 //MM_ATC_L2_CNTL5 7016 #define MM_ATC_L2_CNTL5__MM_NONRT_IFIFO_ACTIVE_TRANSACTION_LIMIT__SHIFT 0x0 7017 #define MM_ATC_L2_CNTL5__MM_SOFTRT_IFIFO_ACTIVE_TRANSACTION_LIMIT__SHIFT 0xa 7018 #define MM_ATC_L2_CNTL5__MM_NONRT_IFIFO_ACTIVE_TRANSACTION_LIMIT_MASK 0x000003FFL 7019 #define MM_ATC_L2_CNTL5__MM_SOFTRT_IFIFO_ACTIVE_TRANSACTION_LIMIT_MASK 0x000FFC00L 7020 //MM_ATC_L2_MM_GROUP_RT_CLASSES 7021 #define MM_ATC_L2_MM_GROUP_RT_CLASSES__GROUP_RT_CLASS__SHIFT 0x0 7022 #define MM_ATC_L2_MM_GROUP_RT_CLASSES__GROUP_RT_CLASS_MASK 0xFFFFFFFFL 7023 //MM_ATC_L2_STATUS 7024 #define MM_ATC_L2_STATUS__BUSY__SHIFT 0x0 7025 #define MM_ATC_L2_STATUS__PARITY_ERROR_INFO__SHIFT 0x1 7026 #define MM_ATC_L2_STATUS__BUSY_MASK 0x00000001L 7027 #define MM_ATC_L2_STATUS__PARITY_ERROR_INFO_MASK 0x3FFFFFFEL 7028 //MM_ATC_L2_STATUS2 7029 #define MM_ATC_L2_STATUS2__IFIFO_NON_FATAL_PARITY_ERROR_INFO__SHIFT 0x0 7030 #define MM_ATC_L2_STATUS2__IFIFO_FATAL_PARITY_ERROR_INFO__SHIFT 0x8 7031 #define MM_ATC_L2_STATUS2__IFIFO_NON_FATAL_PARITY_ERROR_INFO_MASK 0x000000FFL 7032 #define MM_ATC_L2_STATUS2__IFIFO_FATAL_PARITY_ERROR_INFO_MASK 0x0000FF00L 7033 //MM_ATC_L2_MISC_CG 7034 #define MM_ATC_L2_MISC_CG__OFFDLY__SHIFT 0x6 7035 #define MM_ATC_L2_MISC_CG__ENABLE__SHIFT 0x12 7036 #define MM_ATC_L2_MISC_CG__MEM_LS_ENABLE__SHIFT 0x13 7037 #define MM_ATC_L2_MISC_CG__OFFDLY_MASK 0x00000FC0L 7038 #define MM_ATC_L2_MISC_CG__ENABLE_MASK 0x00040000L 7039 #define MM_ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK 0x00080000L 7040 //MM_ATC_L2_MEM_POWER_LS 7041 #define MM_ATC_L2_MEM_POWER_LS__LS_SETUP__SHIFT 0x0 7042 #define MM_ATC_L2_MEM_POWER_LS__LS_HOLD__SHIFT 0x6 7043 #define MM_ATC_L2_MEM_POWER_LS__LS_SETUP_MASK 0x0000003FL 7044 #define MM_ATC_L2_MEM_POWER_LS__LS_HOLD_MASK 0x00000FC0L 7045 //MM_ATC_L2_CGTT_CLK_CTRL 7046 #define MM_ATC_L2_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 7047 #define MM_ATC_L2_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 7048 #define MM_ATC_L2_CGTT_CLK_CTRL__MGLS_OVERRIDE__SHIFT 0xf 7049 #define MM_ATC_L2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x10 7050 #define MM_ATC_L2_CGTT_CLK_CTRL__SOFT_OVERRIDE__SHIFT 0x18 7051 #define MM_ATC_L2_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL 7052 #define MM_ATC_L2_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L 7053 #define MM_ATC_L2_CGTT_CLK_CTRL__MGLS_OVERRIDE_MASK 0x00008000L 7054 #define MM_ATC_L2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00FF0000L 7055 #define MM_ATC_L2_CGTT_CLK_CTRL__SOFT_OVERRIDE_MASK 0xFF000000L 7056 //MM_ATC_L2_SDPPORT_CTRL 7057 #define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_RDRSPCKEN__SHIFT 0x0 7058 #define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_RDRSPCKENRCV__SHIFT 0x1 7059 #define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_RDRSPDATACKEN__SHIFT 0x2 7060 #define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_RDRSPDATACKENRCV__SHIFT 0x3 7061 #define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_WRRSPCKEN__SHIFT 0x4 7062 #define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_WRRSPCKENRCV__SHIFT 0x5 7063 #define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_REQCKEN__SHIFT 0x6 7064 #define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_REQCKENRCV__SHIFT 0x7 7065 #define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_ORIGDATACKEN__SHIFT 0x8 7066 #define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_ORIGDATACKENRCV__SHIFT 0x9 7067 #define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_RDRSPCKEN_MASK 0x00000001L 7068 #define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_RDRSPCKENRCV_MASK 0x00000002L 7069 #define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_RDRSPDATACKEN_MASK 0x00000004L 7070 #define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_RDRSPDATACKENRCV_MASK 0x00000008L 7071 #define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_WRRSPCKEN_MASK 0x00000010L 7072 #define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_WRRSPCKENRCV_MASK 0x00000020L 7073 #define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_REQCKEN_MASK 0x00000040L 7074 #define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_REQCKENRCV_MASK 0x00000080L 7075 #define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_ORIGDATACKEN_MASK 0x00000100L 7076 #define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_ORIGDATACKENRCV_MASK 0x00000200L 7077 7078 7079 // addressBlock: mmhub_mmutcl2_mmvml2pfdec 7080 //MMVM_L2_CNTL 7081 #define MMVM_L2_CNTL__ENABLE_L2_CACHE__SHIFT 0x0 7082 #define MMVM_L2_CNTL__ENABLE_L2_FRAGMENT_PROCESSING__SHIFT 0x1 7083 #define MMVM_L2_CNTL__L2_CACHE_PTE_ENDIAN_SWAP_MODE__SHIFT 0x2 7084 #define MMVM_L2_CNTL__L2_CACHE_PDE_ENDIAN_SWAP_MODE__SHIFT 0x4 7085 #define MMVM_L2_CNTL__L2_PDE0_CACHE_TAG_GENERATION_MODE__SHIFT 0x8 7086 #define MMVM_L2_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE__SHIFT 0x9 7087 #define MMVM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE__SHIFT 0xa 7088 #define MMVM_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY__SHIFT 0xb 7089 #define MMVM_L2_CNTL__L2_PDE0_CACHE_SPLIT_MODE__SHIFT 0xc 7090 #define MMVM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE__SHIFT 0xf 7091 #define MMVM_L2_CNTL__PDE_FAULT_CLASSIFICATION__SHIFT 0x12 7092 #define MMVM_L2_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE__SHIFT 0x13 7093 #define MMVM_L2_CNTL__IDENTITY_MODE_FRAGMENT_SIZE__SHIFT 0x15 7094 #define MMVM_L2_CNTL__L2_PTE_CACHE_ADDR_MODE__SHIFT 0x1a 7095 #define MMVM_L2_CNTL__ENABLE_L2_CACHE_MASK 0x00000001L 7096 #define MMVM_L2_CNTL__ENABLE_L2_FRAGMENT_PROCESSING_MASK 0x00000002L 7097 #define MMVM_L2_CNTL__L2_CACHE_PTE_ENDIAN_SWAP_MODE_MASK 0x0000000CL 7098 #define MMVM_L2_CNTL__L2_CACHE_PDE_ENDIAN_SWAP_MODE_MASK 0x00000030L 7099 #define MMVM_L2_CNTL__L2_PDE0_CACHE_TAG_GENERATION_MODE_MASK 0x00000100L 7100 #define MMVM_L2_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE_MASK 0x00000200L 7101 #define MMVM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE_MASK 0x00000400L 7102 #define MMVM_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY_MASK 0x00000800L 7103 #define MMVM_L2_CNTL__L2_PDE0_CACHE_SPLIT_MODE_MASK 0x00007000L 7104 #define MMVM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE_MASK 0x00038000L 7105 #define MMVM_L2_CNTL__PDE_FAULT_CLASSIFICATION_MASK 0x00040000L 7106 #define MMVM_L2_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE_MASK 0x00180000L 7107 #define MMVM_L2_CNTL__IDENTITY_MODE_FRAGMENT_SIZE_MASK 0x03E00000L 7108 #define MMVM_L2_CNTL__L2_PTE_CACHE_ADDR_MODE_MASK 0x0C000000L 7109 //MMVM_L2_CNTL2 7110 #define MMVM_L2_CNTL2__INVALIDATE_ALL_L1_TLBS__SHIFT 0x0 7111 #define MMVM_L2_CNTL2__INVALIDATE_L2_CACHE__SHIFT 0x1 7112 #define MMVM_L2_CNTL2__DISABLE_INVALIDATE_PER_DOMAIN__SHIFT 0x15 7113 #define MMVM_L2_CNTL2__DISABLE_BIGK_CACHE_OPTIMIZATION__SHIFT 0x16 7114 #define MMVM_L2_CNTL2__L2_PTE_CACHE_VMID_MODE__SHIFT 0x17 7115 #define MMVM_L2_CNTL2__INVALIDATE_CACHE_MODE__SHIFT 0x1a 7116 #define MMVM_L2_CNTL2__PDE_CACHE_EFFECTIVE_SIZE__SHIFT 0x1c 7117 #define MMVM_L2_CNTL2__INVALIDATE_ALL_L1_TLBS_MASK 0x00000001L 7118 #define MMVM_L2_CNTL2__INVALIDATE_L2_CACHE_MASK 0x00000002L 7119 #define MMVM_L2_CNTL2__DISABLE_INVALIDATE_PER_DOMAIN_MASK 0x00200000L 7120 #define MMVM_L2_CNTL2__DISABLE_BIGK_CACHE_OPTIMIZATION_MASK 0x00400000L 7121 #define MMVM_L2_CNTL2__L2_PTE_CACHE_VMID_MODE_MASK 0x03800000L 7122 #define MMVM_L2_CNTL2__INVALIDATE_CACHE_MODE_MASK 0x0C000000L 7123 #define MMVM_L2_CNTL2__PDE_CACHE_EFFECTIVE_SIZE_MASK 0x70000000L 7124 //MMVM_L2_CNTL3 7125 #define MMVM_L2_CNTL3__BANK_SELECT__SHIFT 0x0 7126 #define MMVM_L2_CNTL3__L2_CACHE_UPDATE_MODE__SHIFT 0x6 7127 #define MMVM_L2_CNTL3__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE__SHIFT 0x8 7128 #define MMVM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0xf 7129 #define MMVM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY__SHIFT 0x14 7130 #define MMVM_L2_CNTL3__L2_CACHE_4K_EFFECTIVE_SIZE__SHIFT 0x15 7131 #define MMVM_L2_CNTL3__L2_CACHE_BIGK_EFFECTIVE_SIZE__SHIFT 0x18 7132 #define MMVM_L2_CNTL3__L2_CACHE_4K_FORCE_MISS__SHIFT 0x1c 7133 #define MMVM_L2_CNTL3__L2_CACHE_BIGK_FORCE_MISS__SHIFT 0x1d 7134 #define MMVM_L2_CNTL3__PDE_CACHE_FORCE_MISS__SHIFT 0x1e 7135 #define MMVM_L2_CNTL3__L2_CACHE_4K_ASSOCIATIVITY__SHIFT 0x1f 7136 #define MMVM_L2_CNTL3__BANK_SELECT_MASK 0x0000003FL 7137 #define MMVM_L2_CNTL3__L2_CACHE_UPDATE_MODE_MASK 0x000000C0L 7138 #define MMVM_L2_CNTL3__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE_MASK 0x00001F00L 7139 #define MMVM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000F8000L 7140 #define MMVM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY_MASK 0x00100000L 7141 #define MMVM_L2_CNTL3__L2_CACHE_4K_EFFECTIVE_SIZE_MASK 0x00E00000L 7142 #define MMVM_L2_CNTL3__L2_CACHE_BIGK_EFFECTIVE_SIZE_MASK 0x0F000000L 7143 #define MMVM_L2_CNTL3__L2_CACHE_4K_FORCE_MISS_MASK 0x10000000L 7144 #define MMVM_L2_CNTL3__L2_CACHE_BIGK_FORCE_MISS_MASK 0x20000000L 7145 #define MMVM_L2_CNTL3__PDE_CACHE_FORCE_MISS_MASK 0x40000000L 7146 #define MMVM_L2_CNTL3__L2_CACHE_4K_ASSOCIATIVITY_MASK 0x80000000L 7147 //MMVM_L2_STATUS 7148 #define MMVM_L2_STATUS__L2_BUSY__SHIFT 0x0 7149 #define MMVM_L2_STATUS__CONTEXT_DOMAIN_BUSY__SHIFT 0x1 7150 #define MMVM_L2_STATUS__FOUND_4K_PTE_CACHE_PARITY_ERRORS__SHIFT 0x11 7151 #define MMVM_L2_STATUS__FOUND_BIGK_PTE_CACHE_PARITY_ERRORS__SHIFT 0x12 7152 #define MMVM_L2_STATUS__FOUND_PDE0_CACHE_PARITY_ERRORS__SHIFT 0x13 7153 #define MMVM_L2_STATUS__FOUND_PDE1_CACHE_PARITY_ERRORS__SHIFT 0x14 7154 #define MMVM_L2_STATUS__FOUND_PDE2_CACHE_PARITY_ERRORS__SHIFT 0x15 7155 #define MMVM_L2_STATUS__L2_BUSY_MASK 0x00000001L 7156 #define MMVM_L2_STATUS__CONTEXT_DOMAIN_BUSY_MASK 0x0001FFFEL 7157 #define MMVM_L2_STATUS__FOUND_4K_PTE_CACHE_PARITY_ERRORS_MASK 0x00020000L 7158 #define MMVM_L2_STATUS__FOUND_BIGK_PTE_CACHE_PARITY_ERRORS_MASK 0x00040000L 7159 #define MMVM_L2_STATUS__FOUND_PDE0_CACHE_PARITY_ERRORS_MASK 0x00080000L 7160 #define MMVM_L2_STATUS__FOUND_PDE1_CACHE_PARITY_ERRORS_MASK 0x00100000L 7161 #define MMVM_L2_STATUS__FOUND_PDE2_CACHE_PARITY_ERRORS_MASK 0x00200000L 7162 //MMVM_DUMMY_PAGE_FAULT_CNTL 7163 #define MMVM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_FAULT_ENABLE__SHIFT 0x0 7164 #define MMVM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_ADDRESS_LOGICAL__SHIFT 0x1 7165 #define MMVM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_COMPARE_MSBS__SHIFT 0x2 7166 #define MMVM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_FAULT_ENABLE_MASK 0x00000001L 7167 #define MMVM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_ADDRESS_LOGICAL_MASK 0x00000002L 7168 #define MMVM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_COMPARE_MSBS_MASK 0x000000FCL 7169 //MMVM_DUMMY_PAGE_FAULT_ADDR_LO32 7170 #define MMVM_DUMMY_PAGE_FAULT_ADDR_LO32__DUMMY_PAGE_ADDR_LO32__SHIFT 0x0 7171 #define MMVM_DUMMY_PAGE_FAULT_ADDR_LO32__DUMMY_PAGE_ADDR_LO32_MASK 0xFFFFFFFFL 7172 //MMVM_DUMMY_PAGE_FAULT_ADDR_HI32 7173 #define MMVM_DUMMY_PAGE_FAULT_ADDR_HI32__DUMMY_PAGE_ADDR_HI4__SHIFT 0x0 7174 #define MMVM_DUMMY_PAGE_FAULT_ADDR_HI32__DUMMY_PAGE_ADDR_HI4_MASK 0x0000000FL 7175 //MMVM_INVALIDATE_CNTL 7176 #define MMVM_INVALIDATE_CNTL__PRI_REG_ALTERNATING__SHIFT 0x0 7177 #define MMVM_INVALIDATE_CNTL__MAX_REG_OUTSTANDING__SHIFT 0x8 7178 #define MMVM_INVALIDATE_CNTL__PRI_REG_ALTERNATING_MASK 0x000000FFL 7179 #define MMVM_INVALIDATE_CNTL__MAX_REG_OUTSTANDING_MASK 0x0000FF00L 7180 //MMVM_L2_PROTECTION_FAULT_CNTL 7181 #define MMVM_L2_PROTECTION_FAULT_CNTL__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x0 7182 #define MMVM_L2_PROTECTION_FAULT_CNTL__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES__SHIFT 0x1 7183 #define MMVM_L2_PROTECTION_FAULT_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x2 7184 #define MMVM_L2_PROTECTION_FAULT_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x3 7185 #define MMVM_L2_PROTECTION_FAULT_CNTL__PDE1_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x4 7186 #define MMVM_L2_PROTECTION_FAULT_CNTL__PDE2_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x5 7187 #define MMVM_L2_PROTECTION_FAULT_CNTL__TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x6 7188 #define MMVM_L2_PROTECTION_FAULT_CNTL__NACK_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x7 7189 #define MMVM_L2_PROTECTION_FAULT_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x8 7190 #define MMVM_L2_PROTECTION_FAULT_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x9 7191 #define MMVM_L2_PROTECTION_FAULT_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa 7192 #define MMVM_L2_PROTECTION_FAULT_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xb 7193 #define MMVM_L2_PROTECTION_FAULT_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc 7194 #define MMVM_L2_PROTECTION_FAULT_CNTL__CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT 0xd 7195 #define MMVM_L2_PROTECTION_FAULT_CNTL__OTHER_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT 0x1d 7196 #define MMVM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_NO_RETRY_FAULT__SHIFT 0x1e 7197 #define MMVM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_RETRY_FAULT__SHIFT 0x1f 7198 #define MMVM_L2_PROTECTION_FAULT_CNTL__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00000001L 7199 #define MMVM_L2_PROTECTION_FAULT_CNTL__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES_MASK 0x00000002L 7200 #define MMVM_L2_PROTECTION_FAULT_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000004L 7201 #define MMVM_L2_PROTECTION_FAULT_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000008L 7202 #define MMVM_L2_PROTECTION_FAULT_CNTL__PDE1_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000010L 7203 #define MMVM_L2_PROTECTION_FAULT_CNTL__PDE2_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000020L 7204 #define MMVM_L2_PROTECTION_FAULT_CNTL__TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000040L 7205 #define MMVM_L2_PROTECTION_FAULT_CNTL__NACK_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000080L 7206 #define MMVM_L2_PROTECTION_FAULT_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000100L 7207 #define MMVM_L2_PROTECTION_FAULT_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000200L 7208 #define MMVM_L2_PROTECTION_FAULT_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L 7209 #define MMVM_L2_PROTECTION_FAULT_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000800L 7210 #define MMVM_L2_PROTECTION_FAULT_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L 7211 #define MMVM_L2_PROTECTION_FAULT_CNTL__CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK 0x1FFFE000L 7212 #define MMVM_L2_PROTECTION_FAULT_CNTL__OTHER_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK 0x20000000L 7213 #define MMVM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_NO_RETRY_FAULT_MASK 0x40000000L 7214 #define MMVM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_RETRY_FAULT_MASK 0x80000000L 7215 //MMVM_L2_PROTECTION_FAULT_CNTL2 7216 #define MMVM_L2_PROTECTION_FAULT_CNTL2__CLIENT_ID_PRT_FAULT_INTERRUPT__SHIFT 0x0 7217 #define MMVM_L2_PROTECTION_FAULT_CNTL2__OTHER_CLIENT_ID_PRT_FAULT_INTERRUPT__SHIFT 0x10 7218 #define MMVM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE__SHIFT 0x11 7219 #define MMVM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY__SHIFT 0x12 7220 #define MMVM_L2_PROTECTION_FAULT_CNTL2__ENABLE_RETRY_FAULT_INTERRUPT__SHIFT 0x13 7221 #define MMVM_L2_PROTECTION_FAULT_CNTL2__CLIENT_ID_PRT_FAULT_INTERRUPT_MASK 0x0000FFFFL 7222 #define MMVM_L2_PROTECTION_FAULT_CNTL2__OTHER_CLIENT_ID_PRT_FAULT_INTERRUPT_MASK 0x00010000L 7223 #define MMVM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE_MASK 0x00020000L 7224 #define MMVM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY_MASK 0x00040000L 7225 #define MMVM_L2_PROTECTION_FAULT_CNTL2__ENABLE_RETRY_FAULT_INTERRUPT_MASK 0x00080000L 7226 //MMVM_L2_PROTECTION_FAULT_MM_CNTL3 7227 #define MMVM_L2_PROTECTION_FAULT_MM_CNTL3__VML1_READ_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT 0x0 7228 #define MMVM_L2_PROTECTION_FAULT_MM_CNTL3__VML1_READ_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK 0xFFFFFFFFL 7229 //MMVM_L2_PROTECTION_FAULT_MM_CNTL4 7230 #define MMVM_L2_PROTECTION_FAULT_MM_CNTL4__VML1_WRITE_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT 0x0 7231 #define MMVM_L2_PROTECTION_FAULT_MM_CNTL4__VML1_WRITE_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK 0xFFFFFFFFL 7232 //MMVM_L2_PROTECTION_FAULT_STATUS 7233 #define MMVM_L2_PROTECTION_FAULT_STATUS__MORE_FAULTS__SHIFT 0x0 7234 #define MMVM_L2_PROTECTION_FAULT_STATUS__WALKER_ERROR__SHIFT 0x1 7235 #define MMVM_L2_PROTECTION_FAULT_STATUS__PERMISSION_FAULTS__SHIFT 0x4 7236 #define MMVM_L2_PROTECTION_FAULT_STATUS__MAPPING_ERROR__SHIFT 0x8 7237 #define MMVM_L2_PROTECTION_FAULT_STATUS__CID__SHIFT 0x9 7238 #define MMVM_L2_PROTECTION_FAULT_STATUS__RW__SHIFT 0x12 7239 #define MMVM_L2_PROTECTION_FAULT_STATUS__ATOMIC__SHIFT 0x13 7240 #define MMVM_L2_PROTECTION_FAULT_STATUS__VMID__SHIFT 0x14 7241 #define MMVM_L2_PROTECTION_FAULT_STATUS__VF__SHIFT 0x18 7242 #define MMVM_L2_PROTECTION_FAULT_STATUS__VFID__SHIFT 0x19 7243 #define MMVM_L2_PROTECTION_FAULT_STATUS__MORE_FAULTS_MASK 0x00000001L 7244 #define MMVM_L2_PROTECTION_FAULT_STATUS__WALKER_ERROR_MASK 0x0000000EL 7245 #define MMVM_L2_PROTECTION_FAULT_STATUS__PERMISSION_FAULTS_MASK 0x000000F0L 7246 #define MMVM_L2_PROTECTION_FAULT_STATUS__MAPPING_ERROR_MASK 0x00000100L 7247 #define MMVM_L2_PROTECTION_FAULT_STATUS__CID_MASK 0x0003FE00L 7248 #define MMVM_L2_PROTECTION_FAULT_STATUS__RW_MASK 0x00040000L 7249 #define MMVM_L2_PROTECTION_FAULT_STATUS__ATOMIC_MASK 0x00080000L 7250 #define MMVM_L2_PROTECTION_FAULT_STATUS__VMID_MASK 0x00F00000L 7251 #define MMVM_L2_PROTECTION_FAULT_STATUS__VF_MASK 0x01000000L 7252 #define MMVM_L2_PROTECTION_FAULT_STATUS__VFID_MASK 0x3E000000L 7253 //MMVM_L2_PROTECTION_FAULT_ADDR_LO32 7254 #define MMVM_L2_PROTECTION_FAULT_ADDR_LO32__LOGICAL_PAGE_ADDR_LO32__SHIFT 0x0 7255 #define MMVM_L2_PROTECTION_FAULT_ADDR_LO32__LOGICAL_PAGE_ADDR_LO32_MASK 0xFFFFFFFFL 7256 //MMVM_L2_PROTECTION_FAULT_ADDR_HI32 7257 #define MMVM_L2_PROTECTION_FAULT_ADDR_HI32__LOGICAL_PAGE_ADDR_HI4__SHIFT 0x0 7258 #define MMVM_L2_PROTECTION_FAULT_ADDR_HI32__LOGICAL_PAGE_ADDR_HI4_MASK 0x0000000FL 7259 //MMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32 7260 #define MMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32__PHYSICAL_PAGE_ADDR_LO32__SHIFT 0x0 7261 #define MMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32__PHYSICAL_PAGE_ADDR_LO32_MASK 0xFFFFFFFFL 7262 //MMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32 7263 #define MMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32__PHYSICAL_PAGE_ADDR_HI4__SHIFT 0x0 7264 #define MMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32__PHYSICAL_PAGE_ADDR_HI4_MASK 0x0000000FL 7265 //MMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32 7266 #define MMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 7267 #define MMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 7268 //MMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32 7269 #define MMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 7270 #define MMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 7271 //MMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32 7272 #define MMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 7273 #define MMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 7274 //MMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32 7275 #define MMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 7276 #define MMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 7277 //MMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32 7278 #define MMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32__PHYSICAL_PAGE_OFFSET_LO32__SHIFT 0x0 7279 #define MMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32__PHYSICAL_PAGE_OFFSET_LO32_MASK 0xFFFFFFFFL 7280 //MMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32 7281 #define MMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32__PHYSICAL_PAGE_OFFSET_HI4__SHIFT 0x0 7282 #define MMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32__PHYSICAL_PAGE_OFFSET_HI4_MASK 0x0000000FL 7283 //MMVM_L2_CNTL4 7284 #define MMVM_L2_CNTL4__L2_CACHE_4K_PARTITION_COUNT__SHIFT 0x0 7285 #define MMVM_L2_CNTL4__VMC_TAP_PDE_REQUEST_PHYSICAL__SHIFT 0x6 7286 #define MMVM_L2_CNTL4__VMC_TAP_PTE_REQUEST_PHYSICAL__SHIFT 0x7 7287 #define MMVM_L2_CNTL4__MM_NONRT_IFIFO_ACTIVE_TRANSACTION_LIMIT__SHIFT 0x8 7288 #define MMVM_L2_CNTL4__MM_SOFTRT_IFIFO_ACTIVE_TRANSACTION_LIMIT__SHIFT 0x12 7289 #define MMVM_L2_CNTL4__BPM_CGCGLS_OVERRIDE__SHIFT 0x1c 7290 #define MMVM_L2_CNTL4__GC_CH_FGCG_OFF__SHIFT 0x1d 7291 #define MMVM_L2_CNTL4__L2_CACHE_4K_PARTITION_COUNT_MASK 0x0000003FL 7292 #define MMVM_L2_CNTL4__VMC_TAP_PDE_REQUEST_PHYSICAL_MASK 0x00000040L 7293 #define MMVM_L2_CNTL4__VMC_TAP_PTE_REQUEST_PHYSICAL_MASK 0x00000080L 7294 #define MMVM_L2_CNTL4__MM_NONRT_IFIFO_ACTIVE_TRANSACTION_LIMIT_MASK 0x0003FF00L 7295 #define MMVM_L2_CNTL4__MM_SOFTRT_IFIFO_ACTIVE_TRANSACTION_LIMIT_MASK 0x0FFC0000L 7296 #define MMVM_L2_CNTL4__BPM_CGCGLS_OVERRIDE_MASK 0x10000000L 7297 #define MMVM_L2_CNTL4__GC_CH_FGCG_OFF_MASK 0x20000000L 7298 //MMVM_L2_MM_GROUP_RT_CLASSES 7299 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_0_RT_CLASS__SHIFT 0x0 7300 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_1_RT_CLASS__SHIFT 0x1 7301 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_2_RT_CLASS__SHIFT 0x2 7302 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_3_RT_CLASS__SHIFT 0x3 7303 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_4_RT_CLASS__SHIFT 0x4 7304 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_5_RT_CLASS__SHIFT 0x5 7305 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_6_RT_CLASS__SHIFT 0x6 7306 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_7_RT_CLASS__SHIFT 0x7 7307 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_8_RT_CLASS__SHIFT 0x8 7308 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_9_RT_CLASS__SHIFT 0x9 7309 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_10_RT_CLASS__SHIFT 0xa 7310 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_11_RT_CLASS__SHIFT 0xb 7311 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_12_RT_CLASS__SHIFT 0xc 7312 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_13_RT_CLASS__SHIFT 0xd 7313 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_14_RT_CLASS__SHIFT 0xe 7314 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_15_RT_CLASS__SHIFT 0xf 7315 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_16_RT_CLASS__SHIFT 0x10 7316 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_17_RT_CLASS__SHIFT 0x11 7317 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_18_RT_CLASS__SHIFT 0x12 7318 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_19_RT_CLASS__SHIFT 0x13 7319 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_20_RT_CLASS__SHIFT 0x14 7320 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_21_RT_CLASS__SHIFT 0x15 7321 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_22_RT_CLASS__SHIFT 0x16 7322 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_23_RT_CLASS__SHIFT 0x17 7323 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_24_RT_CLASS__SHIFT 0x18 7324 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_25_RT_CLASS__SHIFT 0x19 7325 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_26_RT_CLASS__SHIFT 0x1a 7326 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_27_RT_CLASS__SHIFT 0x1b 7327 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_28_RT_CLASS__SHIFT 0x1c 7328 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_29_RT_CLASS__SHIFT 0x1d 7329 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_30_RT_CLASS__SHIFT 0x1e 7330 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_31_RT_CLASS__SHIFT 0x1f 7331 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_0_RT_CLASS_MASK 0x00000001L 7332 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_1_RT_CLASS_MASK 0x00000002L 7333 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_2_RT_CLASS_MASK 0x00000004L 7334 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_3_RT_CLASS_MASK 0x00000008L 7335 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_4_RT_CLASS_MASK 0x00000010L 7336 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_5_RT_CLASS_MASK 0x00000020L 7337 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_6_RT_CLASS_MASK 0x00000040L 7338 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_7_RT_CLASS_MASK 0x00000080L 7339 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_8_RT_CLASS_MASK 0x00000100L 7340 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_9_RT_CLASS_MASK 0x00000200L 7341 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_10_RT_CLASS_MASK 0x00000400L 7342 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_11_RT_CLASS_MASK 0x00000800L 7343 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_12_RT_CLASS_MASK 0x00001000L 7344 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_13_RT_CLASS_MASK 0x00002000L 7345 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_14_RT_CLASS_MASK 0x00004000L 7346 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_15_RT_CLASS_MASK 0x00008000L 7347 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_16_RT_CLASS_MASK 0x00010000L 7348 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_17_RT_CLASS_MASK 0x00020000L 7349 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_18_RT_CLASS_MASK 0x00040000L 7350 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_19_RT_CLASS_MASK 0x00080000L 7351 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_20_RT_CLASS_MASK 0x00100000L 7352 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_21_RT_CLASS_MASK 0x00200000L 7353 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_22_RT_CLASS_MASK 0x00400000L 7354 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_23_RT_CLASS_MASK 0x00800000L 7355 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_24_RT_CLASS_MASK 0x01000000L 7356 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_25_RT_CLASS_MASK 0x02000000L 7357 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_26_RT_CLASS_MASK 0x04000000L 7358 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_27_RT_CLASS_MASK 0x08000000L 7359 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_28_RT_CLASS_MASK 0x10000000L 7360 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_29_RT_CLASS_MASK 0x20000000L 7361 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_30_RT_CLASS_MASK 0x40000000L 7362 #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_31_RT_CLASS_MASK 0x80000000L 7363 //MMVM_L2_BANK_SELECT_RESERVED_CID 7364 #define MMVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_READ_CLIENT_ID__SHIFT 0x0 7365 #define MMVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_WRITE_CLIENT_ID__SHIFT 0xa 7366 #define MMVM_L2_BANK_SELECT_RESERVED_CID__ENABLE__SHIFT 0x14 7367 #define MMVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_INVALIDATION_MODE__SHIFT 0x18 7368 #define MMVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_PRIVATE_INVALIDATION__SHIFT 0x19 7369 #define MMVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_FRAGMENT_SIZE__SHIFT 0x1a 7370 #define MMVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_READ_CLIENT_ID_MASK 0x000001FFL 7371 #define MMVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_WRITE_CLIENT_ID_MASK 0x0007FC00L 7372 #define MMVM_L2_BANK_SELECT_RESERVED_CID__ENABLE_MASK 0x00100000L 7373 #define MMVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_INVALIDATION_MODE_MASK 0x01000000L 7374 #define MMVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_PRIVATE_INVALIDATION_MASK 0x02000000L 7375 #define MMVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_FRAGMENT_SIZE_MASK 0x7C000000L 7376 //MMVM_L2_BANK_SELECT_RESERVED_CID2 7377 #define MMVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_READ_CLIENT_ID__SHIFT 0x0 7378 #define MMVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_WRITE_CLIENT_ID__SHIFT 0xa 7379 #define MMVM_L2_BANK_SELECT_RESERVED_CID2__ENABLE__SHIFT 0x14 7380 #define MMVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_INVALIDATION_MODE__SHIFT 0x18 7381 #define MMVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_PRIVATE_INVALIDATION__SHIFT 0x19 7382 #define MMVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_FRAGMENT_SIZE__SHIFT 0x1a 7383 #define MMVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_READ_CLIENT_ID_MASK 0x000001FFL 7384 #define MMVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_WRITE_CLIENT_ID_MASK 0x0007FC00L 7385 #define MMVM_L2_BANK_SELECT_RESERVED_CID2__ENABLE_MASK 0x00100000L 7386 #define MMVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_INVALIDATION_MODE_MASK 0x01000000L 7387 #define MMVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_PRIVATE_INVALIDATION_MASK 0x02000000L 7388 #define MMVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_FRAGMENT_SIZE_MASK 0x7C000000L 7389 //MMVM_L2_CACHE_PARITY_CNTL 7390 #define MMVM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_4K_PTE_CACHES__SHIFT 0x0 7391 #define MMVM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_BIGK_PTE_CACHES__SHIFT 0x1 7392 #define MMVM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_PDE_CACHES__SHIFT 0x2 7393 #define MMVM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_4K_PTE_CACHE__SHIFT 0x3 7394 #define MMVM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_BIGK_PTE_CACHE__SHIFT 0x4 7395 #define MMVM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_PDE_CACHE__SHIFT 0x5 7396 #define MMVM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_BANK__SHIFT 0x6 7397 #define MMVM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_NUMBER__SHIFT 0x9 7398 #define MMVM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_ASSOC__SHIFT 0xc 7399 #define MMVM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_4K_PTE_CACHES_MASK 0x00000001L 7400 #define MMVM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_BIGK_PTE_CACHES_MASK 0x00000002L 7401 #define MMVM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_PDE_CACHES_MASK 0x00000004L 7402 #define MMVM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_4K_PTE_CACHE_MASK 0x00000008L 7403 #define MMVM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_BIGK_PTE_CACHE_MASK 0x00000010L 7404 #define MMVM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_PDE_CACHE_MASK 0x00000020L 7405 #define MMVM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_BANK_MASK 0x000001C0L 7406 #define MMVM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_NUMBER_MASK 0x00000E00L 7407 #define MMVM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_ASSOC_MASK 0x0000F000L 7408 //MMVM_L2_IH_LOG_CNTL 7409 #define MMVM_L2_IH_LOG_CNTL__ENABLE_LOGGING__SHIFT 0x0 7410 #define MMVM_L2_IH_LOG_CNTL__USE_L_BIT__SHIFT 0x1 7411 #define MMVM_L2_IH_LOG_CNTL__REGISTER_ADDRESS__SHIFT 0x2 7412 #define MMVM_L2_IH_LOG_CNTL__LOG_ALL_TRANSLATIONS__SHIFT 0x14 7413 #define MMVM_L2_IH_LOG_CNTL__ENABLE_LOGGING_MASK 0x00000001L 7414 #define MMVM_L2_IH_LOG_CNTL__USE_L_BIT_MASK 0x00000002L 7415 #define MMVM_L2_IH_LOG_CNTL__REGISTER_ADDRESS_MASK 0x000FFFFCL 7416 #define MMVM_L2_IH_LOG_CNTL__LOG_ALL_TRANSLATIONS_MASK 0x00100000L 7417 //MMVM_L2_IH_LOG_BUSY 7418 #define MMVM_L2_IH_LOG_BUSY__PER_VMID_TRANSLATION_BUSY__SHIFT 0x0 7419 #define MMVM_L2_IH_LOG_BUSY__PER_VMID_INVALIDATION_BUSY__SHIFT 0x10 7420 #define MMVM_L2_IH_LOG_BUSY__PER_VMID_TRANSLATION_BUSY_MASK 0x0000FFFFL 7421 #define MMVM_L2_IH_LOG_BUSY__PER_VMID_INVALIDATION_BUSY_MASK 0xFFFF0000L 7422 //MMVM_L2_CGTT_CLK_CTRL 7423 #define MMVM_L2_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 7424 #define MMVM_L2_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 7425 #define MMVM_L2_CGTT_CLK_CTRL__MGLS_OVERRIDE__SHIFT 0xf 7426 #define MMVM_L2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x10 7427 #define MMVM_L2_CGTT_CLK_CTRL__SOFT_OVERRIDE__SHIFT 0x18 7428 #define MMVM_L2_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL 7429 #define MMVM_L2_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L 7430 #define MMVM_L2_CGTT_CLK_CTRL__MGLS_OVERRIDE_MASK 0x00008000L 7431 #define MMVM_L2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00FF0000L 7432 #define MMVM_L2_CGTT_CLK_CTRL__SOFT_OVERRIDE_MASK 0xFF000000L 7433 //MMVM_L2_CNTL5 7434 #define MMVM_L2_CNTL5__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0 7435 #define MMVM_L2_CNTL5__WALKER_PRIORITY_CLIENT_ID__SHIFT 0x5 7436 #define MMVM_L2_CNTL5__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL 7437 #define MMVM_L2_CNTL5__WALKER_PRIORITY_CLIENT_ID_MASK 0x00003FE0L 7438 //MMVM_L2_GCR_CNTL 7439 #define MMVM_L2_GCR_CNTL__GCR_ENABLE__SHIFT 0x0 7440 #define MMVM_L2_GCR_CNTL__GCR_CLIENT_ID__SHIFT 0x1 7441 #define MMVM_L2_GCR_CNTL__GCR_ENABLE_MASK 0x00000001L 7442 #define MMVM_L2_GCR_CNTL__GCR_CLIENT_ID_MASK 0x000003FEL 7443 //MMVM_L2_CGTT_BUSY_CTRL 7444 #define MMVM_L2_CGTT_BUSY_CTRL__READ_DELAY__SHIFT 0x0 7445 #define MMVM_L2_CGTT_BUSY_CTRL__ALWAYS_BUSY__SHIFT 0x4 7446 #define MMVM_L2_CGTT_BUSY_CTRL__READ_DELAY_MASK 0x0000000FL 7447 #define MMVM_L2_CGTT_BUSY_CTRL__ALWAYS_BUSY_MASK 0x00000010L 7448 //MMVM_L2_PTE_CACHE_DUMP_CNTL 7449 #define MMVM_L2_PTE_CACHE_DUMP_CNTL__ENABLE__SHIFT 0x0 7450 #define MMVM_L2_PTE_CACHE_DUMP_CNTL__READY__SHIFT 0x1 7451 #define MMVM_L2_PTE_CACHE_DUMP_CNTL__BANK__SHIFT 0x4 7452 #define MMVM_L2_PTE_CACHE_DUMP_CNTL__CACHE__SHIFT 0x8 7453 #define MMVM_L2_PTE_CACHE_DUMP_CNTL__ASSOC__SHIFT 0xc 7454 #define MMVM_L2_PTE_CACHE_DUMP_CNTL__INDEX__SHIFT 0x10 7455 #define MMVM_L2_PTE_CACHE_DUMP_CNTL__ENABLE_MASK 0x00000001L 7456 #define MMVM_L2_PTE_CACHE_DUMP_CNTL__READY_MASK 0x00000002L 7457 #define MMVM_L2_PTE_CACHE_DUMP_CNTL__BANK_MASK 0x000000F0L 7458 #define MMVM_L2_PTE_CACHE_DUMP_CNTL__CACHE_MASK 0x00000F00L 7459 #define MMVM_L2_PTE_CACHE_DUMP_CNTL__ASSOC_MASK 0x0000F000L 7460 #define MMVM_L2_PTE_CACHE_DUMP_CNTL__INDEX_MASK 0xFFFF0000L 7461 //MMVM_L2_PTE_CACHE_DUMP_READ 7462 #define MMVM_L2_PTE_CACHE_DUMP_READ__DATA__SHIFT 0x0 7463 #define MMVM_L2_PTE_CACHE_DUMP_READ__DATA_MASK 0xFFFFFFFFL 7464 7465 7466 // addressBlock: mmhub_mmutcl2_mmvml2vcdec 7467 //MMVM_CONTEXT0_CNTL 7468 #define MMVM_CONTEXT0_CNTL__ENABLE_CONTEXT__SHIFT 0x0 7469 #define MMVM_CONTEXT0_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 7470 #define MMVM_CONTEXT0_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 7471 #define MMVM_CONTEXT0_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 7472 #define MMVM_CONTEXT0_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 7473 #define MMVM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 7474 #define MMVM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa 7475 #define MMVM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb 7476 #define MMVM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc 7477 #define MMVM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd 7478 #define MMVM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe 7479 #define MMVM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf 7480 #define MMVM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 7481 #define MMVM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 7482 #define MMVM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 7483 #define MMVM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 7484 #define MMVM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 7485 #define MMVM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 7486 #define MMVM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 7487 #define MMVM_CONTEXT0_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x17 7488 #define MMVM_CONTEXT0_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x18 7489 #define MMVM_CONTEXT0_CNTL__ENABLE_CONTEXT_MASK 0x00000001L 7490 #define MMVM_CONTEXT0_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L 7491 #define MMVM_CONTEXT0_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L 7492 #define MMVM_CONTEXT0_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L 7493 #define MMVM_CONTEXT0_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L 7494 #define MMVM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L 7495 #define MMVM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L 7496 #define MMVM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L 7497 #define MMVM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L 7498 #define MMVM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L 7499 #define MMVM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L 7500 #define MMVM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L 7501 #define MMVM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L 7502 #define MMVM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L 7503 #define MMVM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L 7504 #define MMVM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L 7505 #define MMVM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L 7506 #define MMVM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L 7507 #define MMVM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L 7508 #define MMVM_CONTEXT0_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00800000L 7509 #define MMVM_CONTEXT0_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x01000000L 7510 //MMVM_CONTEXT1_CNTL 7511 #define MMVM_CONTEXT1_CNTL__ENABLE_CONTEXT__SHIFT 0x0 7512 #define MMVM_CONTEXT1_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 7513 #define MMVM_CONTEXT1_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 7514 #define MMVM_CONTEXT1_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 7515 #define MMVM_CONTEXT1_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 7516 #define MMVM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 7517 #define MMVM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa 7518 #define MMVM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb 7519 #define MMVM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc 7520 #define MMVM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd 7521 #define MMVM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe 7522 #define MMVM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf 7523 #define MMVM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 7524 #define MMVM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 7525 #define MMVM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 7526 #define MMVM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 7527 #define MMVM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 7528 #define MMVM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 7529 #define MMVM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 7530 #define MMVM_CONTEXT1_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x17 7531 #define MMVM_CONTEXT1_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x18 7532 #define MMVM_CONTEXT1_CNTL__ENABLE_CONTEXT_MASK 0x00000001L 7533 #define MMVM_CONTEXT1_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L 7534 #define MMVM_CONTEXT1_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L 7535 #define MMVM_CONTEXT1_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L 7536 #define MMVM_CONTEXT1_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L 7537 #define MMVM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L 7538 #define MMVM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L 7539 #define MMVM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L 7540 #define MMVM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L 7541 #define MMVM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L 7542 #define MMVM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L 7543 #define MMVM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L 7544 #define MMVM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L 7545 #define MMVM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L 7546 #define MMVM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L 7547 #define MMVM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L 7548 #define MMVM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L 7549 #define MMVM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L 7550 #define MMVM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L 7551 #define MMVM_CONTEXT1_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00800000L 7552 #define MMVM_CONTEXT1_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x01000000L 7553 //MMVM_CONTEXT2_CNTL 7554 #define MMVM_CONTEXT2_CNTL__ENABLE_CONTEXT__SHIFT 0x0 7555 #define MMVM_CONTEXT2_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 7556 #define MMVM_CONTEXT2_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 7557 #define MMVM_CONTEXT2_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 7558 #define MMVM_CONTEXT2_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 7559 #define MMVM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 7560 #define MMVM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa 7561 #define MMVM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb 7562 #define MMVM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc 7563 #define MMVM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd 7564 #define MMVM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe 7565 #define MMVM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf 7566 #define MMVM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 7567 #define MMVM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 7568 #define MMVM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 7569 #define MMVM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 7570 #define MMVM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 7571 #define MMVM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 7572 #define MMVM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 7573 #define MMVM_CONTEXT2_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x17 7574 #define MMVM_CONTEXT2_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x18 7575 #define MMVM_CONTEXT2_CNTL__ENABLE_CONTEXT_MASK 0x00000001L 7576 #define MMVM_CONTEXT2_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L 7577 #define MMVM_CONTEXT2_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L 7578 #define MMVM_CONTEXT2_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L 7579 #define MMVM_CONTEXT2_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L 7580 #define MMVM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L 7581 #define MMVM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L 7582 #define MMVM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L 7583 #define MMVM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L 7584 #define MMVM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L 7585 #define MMVM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L 7586 #define MMVM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L 7587 #define MMVM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L 7588 #define MMVM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L 7589 #define MMVM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L 7590 #define MMVM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L 7591 #define MMVM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L 7592 #define MMVM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L 7593 #define MMVM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L 7594 #define MMVM_CONTEXT2_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00800000L 7595 #define MMVM_CONTEXT2_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x01000000L 7596 //MMVM_CONTEXT3_CNTL 7597 #define MMVM_CONTEXT3_CNTL__ENABLE_CONTEXT__SHIFT 0x0 7598 #define MMVM_CONTEXT3_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 7599 #define MMVM_CONTEXT3_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 7600 #define MMVM_CONTEXT3_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 7601 #define MMVM_CONTEXT3_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 7602 #define MMVM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 7603 #define MMVM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa 7604 #define MMVM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb 7605 #define MMVM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc 7606 #define MMVM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd 7607 #define MMVM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe 7608 #define MMVM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf 7609 #define MMVM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 7610 #define MMVM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 7611 #define MMVM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 7612 #define MMVM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 7613 #define MMVM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 7614 #define MMVM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 7615 #define MMVM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 7616 #define MMVM_CONTEXT3_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x17 7617 #define MMVM_CONTEXT3_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x18 7618 #define MMVM_CONTEXT3_CNTL__ENABLE_CONTEXT_MASK 0x00000001L 7619 #define MMVM_CONTEXT3_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L 7620 #define MMVM_CONTEXT3_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L 7621 #define MMVM_CONTEXT3_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L 7622 #define MMVM_CONTEXT3_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L 7623 #define MMVM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L 7624 #define MMVM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L 7625 #define MMVM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L 7626 #define MMVM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L 7627 #define MMVM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L 7628 #define MMVM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L 7629 #define MMVM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L 7630 #define MMVM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L 7631 #define MMVM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L 7632 #define MMVM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L 7633 #define MMVM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L 7634 #define MMVM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L 7635 #define MMVM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L 7636 #define MMVM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L 7637 #define MMVM_CONTEXT3_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00800000L 7638 #define MMVM_CONTEXT3_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x01000000L 7639 //MMVM_CONTEXT4_CNTL 7640 #define MMVM_CONTEXT4_CNTL__ENABLE_CONTEXT__SHIFT 0x0 7641 #define MMVM_CONTEXT4_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 7642 #define MMVM_CONTEXT4_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 7643 #define MMVM_CONTEXT4_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 7644 #define MMVM_CONTEXT4_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 7645 #define MMVM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 7646 #define MMVM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa 7647 #define MMVM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb 7648 #define MMVM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc 7649 #define MMVM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd 7650 #define MMVM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe 7651 #define MMVM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf 7652 #define MMVM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 7653 #define MMVM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 7654 #define MMVM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 7655 #define MMVM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 7656 #define MMVM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 7657 #define MMVM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 7658 #define MMVM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 7659 #define MMVM_CONTEXT4_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x17 7660 #define MMVM_CONTEXT4_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x18 7661 #define MMVM_CONTEXT4_CNTL__ENABLE_CONTEXT_MASK 0x00000001L 7662 #define MMVM_CONTEXT4_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L 7663 #define MMVM_CONTEXT4_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L 7664 #define MMVM_CONTEXT4_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L 7665 #define MMVM_CONTEXT4_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L 7666 #define MMVM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L 7667 #define MMVM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L 7668 #define MMVM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L 7669 #define MMVM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L 7670 #define MMVM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L 7671 #define MMVM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L 7672 #define MMVM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L 7673 #define MMVM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L 7674 #define MMVM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L 7675 #define MMVM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L 7676 #define MMVM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L 7677 #define MMVM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L 7678 #define MMVM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L 7679 #define MMVM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L 7680 #define MMVM_CONTEXT4_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00800000L 7681 #define MMVM_CONTEXT4_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x01000000L 7682 //MMVM_CONTEXT5_CNTL 7683 #define MMVM_CONTEXT5_CNTL__ENABLE_CONTEXT__SHIFT 0x0 7684 #define MMVM_CONTEXT5_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 7685 #define MMVM_CONTEXT5_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 7686 #define MMVM_CONTEXT5_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 7687 #define MMVM_CONTEXT5_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 7688 #define MMVM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 7689 #define MMVM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa 7690 #define MMVM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb 7691 #define MMVM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc 7692 #define MMVM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd 7693 #define MMVM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe 7694 #define MMVM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf 7695 #define MMVM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 7696 #define MMVM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 7697 #define MMVM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 7698 #define MMVM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 7699 #define MMVM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 7700 #define MMVM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 7701 #define MMVM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 7702 #define MMVM_CONTEXT5_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x17 7703 #define MMVM_CONTEXT5_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x18 7704 #define MMVM_CONTEXT5_CNTL__ENABLE_CONTEXT_MASK 0x00000001L 7705 #define MMVM_CONTEXT5_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L 7706 #define MMVM_CONTEXT5_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L 7707 #define MMVM_CONTEXT5_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L 7708 #define MMVM_CONTEXT5_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L 7709 #define MMVM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L 7710 #define MMVM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L 7711 #define MMVM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L 7712 #define MMVM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L 7713 #define MMVM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L 7714 #define MMVM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L 7715 #define MMVM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L 7716 #define MMVM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L 7717 #define MMVM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L 7718 #define MMVM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L 7719 #define MMVM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L 7720 #define MMVM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L 7721 #define MMVM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L 7722 #define MMVM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L 7723 #define MMVM_CONTEXT5_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00800000L 7724 #define MMVM_CONTEXT5_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x01000000L 7725 //MMVM_CONTEXT6_CNTL 7726 #define MMVM_CONTEXT6_CNTL__ENABLE_CONTEXT__SHIFT 0x0 7727 #define MMVM_CONTEXT6_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 7728 #define MMVM_CONTEXT6_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 7729 #define MMVM_CONTEXT6_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 7730 #define MMVM_CONTEXT6_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 7731 #define MMVM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 7732 #define MMVM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa 7733 #define MMVM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb 7734 #define MMVM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc 7735 #define MMVM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd 7736 #define MMVM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe 7737 #define MMVM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf 7738 #define MMVM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 7739 #define MMVM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 7740 #define MMVM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 7741 #define MMVM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 7742 #define MMVM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 7743 #define MMVM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 7744 #define MMVM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 7745 #define MMVM_CONTEXT6_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x17 7746 #define MMVM_CONTEXT6_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x18 7747 #define MMVM_CONTEXT6_CNTL__ENABLE_CONTEXT_MASK 0x00000001L 7748 #define MMVM_CONTEXT6_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L 7749 #define MMVM_CONTEXT6_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L 7750 #define MMVM_CONTEXT6_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L 7751 #define MMVM_CONTEXT6_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L 7752 #define MMVM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L 7753 #define MMVM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L 7754 #define MMVM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L 7755 #define MMVM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L 7756 #define MMVM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L 7757 #define MMVM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L 7758 #define MMVM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L 7759 #define MMVM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L 7760 #define MMVM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L 7761 #define MMVM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L 7762 #define MMVM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L 7763 #define MMVM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L 7764 #define MMVM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L 7765 #define MMVM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L 7766 #define MMVM_CONTEXT6_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00800000L 7767 #define MMVM_CONTEXT6_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x01000000L 7768 //MMVM_CONTEXT7_CNTL 7769 #define MMVM_CONTEXT7_CNTL__ENABLE_CONTEXT__SHIFT 0x0 7770 #define MMVM_CONTEXT7_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 7771 #define MMVM_CONTEXT7_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 7772 #define MMVM_CONTEXT7_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 7773 #define MMVM_CONTEXT7_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 7774 #define MMVM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 7775 #define MMVM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa 7776 #define MMVM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb 7777 #define MMVM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc 7778 #define MMVM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd 7779 #define MMVM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe 7780 #define MMVM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf 7781 #define MMVM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 7782 #define MMVM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 7783 #define MMVM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 7784 #define MMVM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 7785 #define MMVM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 7786 #define MMVM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 7787 #define MMVM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 7788 #define MMVM_CONTEXT7_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x17 7789 #define MMVM_CONTEXT7_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x18 7790 #define MMVM_CONTEXT7_CNTL__ENABLE_CONTEXT_MASK 0x00000001L 7791 #define MMVM_CONTEXT7_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L 7792 #define MMVM_CONTEXT7_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L 7793 #define MMVM_CONTEXT7_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L 7794 #define MMVM_CONTEXT7_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L 7795 #define MMVM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L 7796 #define MMVM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L 7797 #define MMVM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L 7798 #define MMVM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L 7799 #define MMVM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L 7800 #define MMVM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L 7801 #define MMVM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L 7802 #define MMVM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L 7803 #define MMVM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L 7804 #define MMVM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L 7805 #define MMVM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L 7806 #define MMVM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L 7807 #define MMVM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L 7808 #define MMVM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L 7809 #define MMVM_CONTEXT7_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00800000L 7810 #define MMVM_CONTEXT7_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x01000000L 7811 //MMVM_CONTEXT8_CNTL 7812 #define MMVM_CONTEXT8_CNTL__ENABLE_CONTEXT__SHIFT 0x0 7813 #define MMVM_CONTEXT8_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 7814 #define MMVM_CONTEXT8_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 7815 #define MMVM_CONTEXT8_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 7816 #define MMVM_CONTEXT8_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 7817 #define MMVM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 7818 #define MMVM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa 7819 #define MMVM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb 7820 #define MMVM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc 7821 #define MMVM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd 7822 #define MMVM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe 7823 #define MMVM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf 7824 #define MMVM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 7825 #define MMVM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 7826 #define MMVM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 7827 #define MMVM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 7828 #define MMVM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 7829 #define MMVM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 7830 #define MMVM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 7831 #define MMVM_CONTEXT8_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x17 7832 #define MMVM_CONTEXT8_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x18 7833 #define MMVM_CONTEXT8_CNTL__ENABLE_CONTEXT_MASK 0x00000001L 7834 #define MMVM_CONTEXT8_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L 7835 #define MMVM_CONTEXT8_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L 7836 #define MMVM_CONTEXT8_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L 7837 #define MMVM_CONTEXT8_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L 7838 #define MMVM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L 7839 #define MMVM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L 7840 #define MMVM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L 7841 #define MMVM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L 7842 #define MMVM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L 7843 #define MMVM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L 7844 #define MMVM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L 7845 #define MMVM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L 7846 #define MMVM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L 7847 #define MMVM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L 7848 #define MMVM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L 7849 #define MMVM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L 7850 #define MMVM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L 7851 #define MMVM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L 7852 #define MMVM_CONTEXT8_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00800000L 7853 #define MMVM_CONTEXT8_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x01000000L 7854 //MMVM_CONTEXT9_CNTL 7855 #define MMVM_CONTEXT9_CNTL__ENABLE_CONTEXT__SHIFT 0x0 7856 #define MMVM_CONTEXT9_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 7857 #define MMVM_CONTEXT9_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 7858 #define MMVM_CONTEXT9_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 7859 #define MMVM_CONTEXT9_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 7860 #define MMVM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 7861 #define MMVM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa 7862 #define MMVM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb 7863 #define MMVM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc 7864 #define MMVM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd 7865 #define MMVM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe 7866 #define MMVM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf 7867 #define MMVM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 7868 #define MMVM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 7869 #define MMVM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 7870 #define MMVM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 7871 #define MMVM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 7872 #define MMVM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 7873 #define MMVM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 7874 #define MMVM_CONTEXT9_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x17 7875 #define MMVM_CONTEXT9_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x18 7876 #define MMVM_CONTEXT9_CNTL__ENABLE_CONTEXT_MASK 0x00000001L 7877 #define MMVM_CONTEXT9_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L 7878 #define MMVM_CONTEXT9_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L 7879 #define MMVM_CONTEXT9_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L 7880 #define MMVM_CONTEXT9_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L 7881 #define MMVM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L 7882 #define MMVM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L 7883 #define MMVM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L 7884 #define MMVM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L 7885 #define MMVM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L 7886 #define MMVM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L 7887 #define MMVM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L 7888 #define MMVM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L 7889 #define MMVM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L 7890 #define MMVM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L 7891 #define MMVM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L 7892 #define MMVM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L 7893 #define MMVM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L 7894 #define MMVM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L 7895 #define MMVM_CONTEXT9_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00800000L 7896 #define MMVM_CONTEXT9_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x01000000L 7897 //MMVM_CONTEXT10_CNTL 7898 #define MMVM_CONTEXT10_CNTL__ENABLE_CONTEXT__SHIFT 0x0 7899 #define MMVM_CONTEXT10_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 7900 #define MMVM_CONTEXT10_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 7901 #define MMVM_CONTEXT10_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 7902 #define MMVM_CONTEXT10_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 7903 #define MMVM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 7904 #define MMVM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa 7905 #define MMVM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb 7906 #define MMVM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc 7907 #define MMVM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd 7908 #define MMVM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe 7909 #define MMVM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf 7910 #define MMVM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 7911 #define MMVM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 7912 #define MMVM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 7913 #define MMVM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 7914 #define MMVM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 7915 #define MMVM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 7916 #define MMVM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 7917 #define MMVM_CONTEXT10_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x17 7918 #define MMVM_CONTEXT10_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x18 7919 #define MMVM_CONTEXT10_CNTL__ENABLE_CONTEXT_MASK 0x00000001L 7920 #define MMVM_CONTEXT10_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L 7921 #define MMVM_CONTEXT10_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L 7922 #define MMVM_CONTEXT10_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L 7923 #define MMVM_CONTEXT10_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L 7924 #define MMVM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L 7925 #define MMVM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L 7926 #define MMVM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L 7927 #define MMVM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L 7928 #define MMVM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L 7929 #define MMVM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L 7930 #define MMVM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L 7931 #define MMVM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L 7932 #define MMVM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L 7933 #define MMVM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L 7934 #define MMVM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L 7935 #define MMVM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L 7936 #define MMVM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L 7937 #define MMVM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L 7938 #define MMVM_CONTEXT10_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00800000L 7939 #define MMVM_CONTEXT10_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x01000000L 7940 //MMVM_CONTEXT11_CNTL 7941 #define MMVM_CONTEXT11_CNTL__ENABLE_CONTEXT__SHIFT 0x0 7942 #define MMVM_CONTEXT11_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 7943 #define MMVM_CONTEXT11_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 7944 #define MMVM_CONTEXT11_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 7945 #define MMVM_CONTEXT11_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 7946 #define MMVM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 7947 #define MMVM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa 7948 #define MMVM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb 7949 #define MMVM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc 7950 #define MMVM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd 7951 #define MMVM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe 7952 #define MMVM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf 7953 #define MMVM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 7954 #define MMVM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 7955 #define MMVM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 7956 #define MMVM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 7957 #define MMVM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 7958 #define MMVM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 7959 #define MMVM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 7960 #define MMVM_CONTEXT11_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x17 7961 #define MMVM_CONTEXT11_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x18 7962 #define MMVM_CONTEXT11_CNTL__ENABLE_CONTEXT_MASK 0x00000001L 7963 #define MMVM_CONTEXT11_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L 7964 #define MMVM_CONTEXT11_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L 7965 #define MMVM_CONTEXT11_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L 7966 #define MMVM_CONTEXT11_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L 7967 #define MMVM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L 7968 #define MMVM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L 7969 #define MMVM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L 7970 #define MMVM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L 7971 #define MMVM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L 7972 #define MMVM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L 7973 #define MMVM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L 7974 #define MMVM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L 7975 #define MMVM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L 7976 #define MMVM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L 7977 #define MMVM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L 7978 #define MMVM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L 7979 #define MMVM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L 7980 #define MMVM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L 7981 #define MMVM_CONTEXT11_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00800000L 7982 #define MMVM_CONTEXT11_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x01000000L 7983 //MMVM_CONTEXT12_CNTL 7984 #define MMVM_CONTEXT12_CNTL__ENABLE_CONTEXT__SHIFT 0x0 7985 #define MMVM_CONTEXT12_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 7986 #define MMVM_CONTEXT12_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 7987 #define MMVM_CONTEXT12_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 7988 #define MMVM_CONTEXT12_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 7989 #define MMVM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 7990 #define MMVM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa 7991 #define MMVM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb 7992 #define MMVM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc 7993 #define MMVM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd 7994 #define MMVM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe 7995 #define MMVM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf 7996 #define MMVM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 7997 #define MMVM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 7998 #define MMVM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 7999 #define MMVM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 8000 #define MMVM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 8001 #define MMVM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 8002 #define MMVM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 8003 #define MMVM_CONTEXT12_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x17 8004 #define MMVM_CONTEXT12_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x18 8005 #define MMVM_CONTEXT12_CNTL__ENABLE_CONTEXT_MASK 0x00000001L 8006 #define MMVM_CONTEXT12_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L 8007 #define MMVM_CONTEXT12_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L 8008 #define MMVM_CONTEXT12_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L 8009 #define MMVM_CONTEXT12_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L 8010 #define MMVM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L 8011 #define MMVM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L 8012 #define MMVM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L 8013 #define MMVM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L 8014 #define MMVM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L 8015 #define MMVM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L 8016 #define MMVM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L 8017 #define MMVM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L 8018 #define MMVM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L 8019 #define MMVM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L 8020 #define MMVM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L 8021 #define MMVM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L 8022 #define MMVM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L 8023 #define MMVM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L 8024 #define MMVM_CONTEXT12_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00800000L 8025 #define MMVM_CONTEXT12_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x01000000L 8026 //MMVM_CONTEXT13_CNTL 8027 #define MMVM_CONTEXT13_CNTL__ENABLE_CONTEXT__SHIFT 0x0 8028 #define MMVM_CONTEXT13_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 8029 #define MMVM_CONTEXT13_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 8030 #define MMVM_CONTEXT13_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 8031 #define MMVM_CONTEXT13_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 8032 #define MMVM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 8033 #define MMVM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa 8034 #define MMVM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb 8035 #define MMVM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc 8036 #define MMVM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd 8037 #define MMVM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe 8038 #define MMVM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf 8039 #define MMVM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 8040 #define MMVM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 8041 #define MMVM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 8042 #define MMVM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 8043 #define MMVM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 8044 #define MMVM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 8045 #define MMVM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 8046 #define MMVM_CONTEXT13_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x17 8047 #define MMVM_CONTEXT13_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x18 8048 #define MMVM_CONTEXT13_CNTL__ENABLE_CONTEXT_MASK 0x00000001L 8049 #define MMVM_CONTEXT13_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L 8050 #define MMVM_CONTEXT13_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L 8051 #define MMVM_CONTEXT13_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L 8052 #define MMVM_CONTEXT13_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L 8053 #define MMVM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L 8054 #define MMVM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L 8055 #define MMVM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L 8056 #define MMVM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L 8057 #define MMVM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L 8058 #define MMVM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L 8059 #define MMVM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L 8060 #define MMVM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L 8061 #define MMVM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L 8062 #define MMVM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L 8063 #define MMVM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L 8064 #define MMVM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L 8065 #define MMVM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L 8066 #define MMVM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L 8067 #define MMVM_CONTEXT13_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00800000L 8068 #define MMVM_CONTEXT13_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x01000000L 8069 //MMVM_CONTEXT14_CNTL 8070 #define MMVM_CONTEXT14_CNTL__ENABLE_CONTEXT__SHIFT 0x0 8071 #define MMVM_CONTEXT14_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 8072 #define MMVM_CONTEXT14_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 8073 #define MMVM_CONTEXT14_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 8074 #define MMVM_CONTEXT14_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 8075 #define MMVM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 8076 #define MMVM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa 8077 #define MMVM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb 8078 #define MMVM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc 8079 #define MMVM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd 8080 #define MMVM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe 8081 #define MMVM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf 8082 #define MMVM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 8083 #define MMVM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 8084 #define MMVM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 8085 #define MMVM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 8086 #define MMVM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 8087 #define MMVM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 8088 #define MMVM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 8089 #define MMVM_CONTEXT14_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x17 8090 #define MMVM_CONTEXT14_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x18 8091 #define MMVM_CONTEXT14_CNTL__ENABLE_CONTEXT_MASK 0x00000001L 8092 #define MMVM_CONTEXT14_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L 8093 #define MMVM_CONTEXT14_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L 8094 #define MMVM_CONTEXT14_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L 8095 #define MMVM_CONTEXT14_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L 8096 #define MMVM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L 8097 #define MMVM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L 8098 #define MMVM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L 8099 #define MMVM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L 8100 #define MMVM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L 8101 #define MMVM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L 8102 #define MMVM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L 8103 #define MMVM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L 8104 #define MMVM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L 8105 #define MMVM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L 8106 #define MMVM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L 8107 #define MMVM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L 8108 #define MMVM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L 8109 #define MMVM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L 8110 #define MMVM_CONTEXT14_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00800000L 8111 #define MMVM_CONTEXT14_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x01000000L 8112 //MMVM_CONTEXT15_CNTL 8113 #define MMVM_CONTEXT15_CNTL__ENABLE_CONTEXT__SHIFT 0x0 8114 #define MMVM_CONTEXT15_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 8115 #define MMVM_CONTEXT15_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 8116 #define MMVM_CONTEXT15_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 8117 #define MMVM_CONTEXT15_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 8118 #define MMVM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 8119 #define MMVM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa 8120 #define MMVM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb 8121 #define MMVM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc 8122 #define MMVM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd 8123 #define MMVM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe 8124 #define MMVM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf 8125 #define MMVM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 8126 #define MMVM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 8127 #define MMVM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 8128 #define MMVM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 8129 #define MMVM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 8130 #define MMVM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 8131 #define MMVM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 8132 #define MMVM_CONTEXT15_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x17 8133 #define MMVM_CONTEXT15_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x18 8134 #define MMVM_CONTEXT15_CNTL__ENABLE_CONTEXT_MASK 0x00000001L 8135 #define MMVM_CONTEXT15_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L 8136 #define MMVM_CONTEXT15_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L 8137 #define MMVM_CONTEXT15_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L 8138 #define MMVM_CONTEXT15_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L 8139 #define MMVM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L 8140 #define MMVM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L 8141 #define MMVM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L 8142 #define MMVM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L 8143 #define MMVM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L 8144 #define MMVM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L 8145 #define MMVM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L 8146 #define MMVM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L 8147 #define MMVM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L 8148 #define MMVM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L 8149 #define MMVM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L 8150 #define MMVM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L 8151 #define MMVM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L 8152 #define MMVM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L 8153 #define MMVM_CONTEXT15_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00800000L 8154 #define MMVM_CONTEXT15_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x01000000L 8155 //MMVM_CONTEXTS_DISABLE 8156 #define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_0__SHIFT 0x0 8157 #define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_1__SHIFT 0x1 8158 #define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_2__SHIFT 0x2 8159 #define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_3__SHIFT 0x3 8160 #define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_4__SHIFT 0x4 8161 #define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_5__SHIFT 0x5 8162 #define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_6__SHIFT 0x6 8163 #define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_7__SHIFT 0x7 8164 #define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_8__SHIFT 0x8 8165 #define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_9__SHIFT 0x9 8166 #define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_10__SHIFT 0xa 8167 #define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_11__SHIFT 0xb 8168 #define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_12__SHIFT 0xc 8169 #define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_13__SHIFT 0xd 8170 #define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_14__SHIFT 0xe 8171 #define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_15__SHIFT 0xf 8172 #define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_0_MASK 0x00000001L 8173 #define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_1_MASK 0x00000002L 8174 #define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_2_MASK 0x00000004L 8175 #define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_3_MASK 0x00000008L 8176 #define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_4_MASK 0x00000010L 8177 #define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_5_MASK 0x00000020L 8178 #define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_6_MASK 0x00000040L 8179 #define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_7_MASK 0x00000080L 8180 #define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_8_MASK 0x00000100L 8181 #define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_9_MASK 0x00000200L 8182 #define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_10_MASK 0x00000400L 8183 #define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_11_MASK 0x00000800L 8184 #define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_12_MASK 0x00001000L 8185 #define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_13_MASK 0x00002000L 8186 #define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_14_MASK 0x00004000L 8187 #define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_15_MASK 0x00008000L 8188 //MMVM_L2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 8189 #define MMVM_L2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0 8190 #define MMVM_L2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0x5 8191 #define MMVM_L2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa 8192 #define MMVM_L2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL 8193 #define MMVM_L2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000003E0L 8194 #define MMVM_L2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK 0x0000FC00L 8195 //MMVM_L2_CONTEXT0_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 8196 #define MMVM_L2_CONTEXT0_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0 8197 #define MMVM_L2_CONTEXT0_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0x5 8198 #define MMVM_L2_CONTEXT0_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa 8199 #define MMVM_L2_CONTEXT0_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL 8200 #define MMVM_L2_CONTEXT0_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000003E0L 8201 #define MMVM_L2_CONTEXT0_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK 0x0000FC00L 8202 //MMVM_L2_CONTEXT1_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 8203 #define MMVM_L2_CONTEXT1_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0 8204 #define MMVM_L2_CONTEXT1_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0x5 8205 #define MMVM_L2_CONTEXT1_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa 8206 #define MMVM_L2_CONTEXT1_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL 8207 #define MMVM_L2_CONTEXT1_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000003E0L 8208 #define MMVM_L2_CONTEXT1_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK 0x0000FC00L 8209 //MMVM_L2_CONTEXT2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 8210 #define MMVM_L2_CONTEXT2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0 8211 #define MMVM_L2_CONTEXT2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0x5 8212 #define MMVM_L2_CONTEXT2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa 8213 #define MMVM_L2_CONTEXT2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL 8214 #define MMVM_L2_CONTEXT2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000003E0L 8215 #define MMVM_L2_CONTEXT2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK 0x0000FC00L 8216 //MMVM_L2_CONTEXT3_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 8217 #define MMVM_L2_CONTEXT3_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0 8218 #define MMVM_L2_CONTEXT3_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0x5 8219 #define MMVM_L2_CONTEXT3_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa 8220 #define MMVM_L2_CONTEXT3_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL 8221 #define MMVM_L2_CONTEXT3_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000003E0L 8222 #define MMVM_L2_CONTEXT3_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK 0x0000FC00L 8223 //MMVM_L2_CONTEXT4_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 8224 #define MMVM_L2_CONTEXT4_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0 8225 #define MMVM_L2_CONTEXT4_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0x5 8226 #define MMVM_L2_CONTEXT4_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa 8227 #define MMVM_L2_CONTEXT4_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL 8228 #define MMVM_L2_CONTEXT4_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000003E0L 8229 #define MMVM_L2_CONTEXT4_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK 0x0000FC00L 8230 //MMVM_L2_CONTEXT5_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 8231 #define MMVM_L2_CONTEXT5_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0 8232 #define MMVM_L2_CONTEXT5_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0x5 8233 #define MMVM_L2_CONTEXT5_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa 8234 #define MMVM_L2_CONTEXT5_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL 8235 #define MMVM_L2_CONTEXT5_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000003E0L 8236 #define MMVM_L2_CONTEXT5_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK 0x0000FC00L 8237 //MMVM_L2_CONTEXT6_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 8238 #define MMVM_L2_CONTEXT6_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0 8239 #define MMVM_L2_CONTEXT6_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0x5 8240 #define MMVM_L2_CONTEXT6_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa 8241 #define MMVM_L2_CONTEXT6_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL 8242 #define MMVM_L2_CONTEXT6_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000003E0L 8243 #define MMVM_L2_CONTEXT6_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK 0x0000FC00L 8244 //MMVM_L2_CONTEXT7_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 8245 #define MMVM_L2_CONTEXT7_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0 8246 #define MMVM_L2_CONTEXT7_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0x5 8247 #define MMVM_L2_CONTEXT7_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa 8248 #define MMVM_L2_CONTEXT7_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL 8249 #define MMVM_L2_CONTEXT7_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000003E0L 8250 #define MMVM_L2_CONTEXT7_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK 0x0000FC00L 8251 //MMVM_L2_CONTEXT8_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 8252 #define MMVM_L2_CONTEXT8_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0 8253 #define MMVM_L2_CONTEXT8_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0x5 8254 #define MMVM_L2_CONTEXT8_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa 8255 #define MMVM_L2_CONTEXT8_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL 8256 #define MMVM_L2_CONTEXT8_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000003E0L 8257 #define MMVM_L2_CONTEXT8_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK 0x0000FC00L 8258 //MMVM_L2_CONTEXT9_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 8259 #define MMVM_L2_CONTEXT9_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0 8260 #define MMVM_L2_CONTEXT9_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0x5 8261 #define MMVM_L2_CONTEXT9_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa 8262 #define MMVM_L2_CONTEXT9_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL 8263 #define MMVM_L2_CONTEXT9_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000003E0L 8264 #define MMVM_L2_CONTEXT9_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK 0x0000FC00L 8265 //MMVM_L2_CONTEXT10_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 8266 #define MMVM_L2_CONTEXT10_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0 8267 #define MMVM_L2_CONTEXT10_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0x5 8268 #define MMVM_L2_CONTEXT10_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa 8269 #define MMVM_L2_CONTEXT10_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL 8270 #define MMVM_L2_CONTEXT10_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000003E0L 8271 #define MMVM_L2_CONTEXT10_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK 0x0000FC00L 8272 //MMVM_L2_CONTEXT11_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 8273 #define MMVM_L2_CONTEXT11_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0 8274 #define MMVM_L2_CONTEXT11_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0x5 8275 #define MMVM_L2_CONTEXT11_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa 8276 #define MMVM_L2_CONTEXT11_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL 8277 #define MMVM_L2_CONTEXT11_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000003E0L 8278 #define MMVM_L2_CONTEXT11_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK 0x0000FC00L 8279 //MMVM_L2_CONTEXT12_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 8280 #define MMVM_L2_CONTEXT12_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0 8281 #define MMVM_L2_CONTEXT12_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0x5 8282 #define MMVM_L2_CONTEXT12_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa 8283 #define MMVM_L2_CONTEXT12_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL 8284 #define MMVM_L2_CONTEXT12_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000003E0L 8285 #define MMVM_L2_CONTEXT12_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK 0x0000FC00L 8286 //MMVM_L2_CONTEXT13_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 8287 #define MMVM_L2_CONTEXT13_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0 8288 #define MMVM_L2_CONTEXT13_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0x5 8289 #define MMVM_L2_CONTEXT13_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa 8290 #define MMVM_L2_CONTEXT13_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL 8291 #define MMVM_L2_CONTEXT13_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000003E0L 8292 #define MMVM_L2_CONTEXT13_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK 0x0000FC00L 8293 //MMVM_L2_CONTEXT14_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 8294 #define MMVM_L2_CONTEXT14_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0 8295 #define MMVM_L2_CONTEXT14_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0x5 8296 #define MMVM_L2_CONTEXT14_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa 8297 #define MMVM_L2_CONTEXT14_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL 8298 #define MMVM_L2_CONTEXT14_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000003E0L 8299 #define MMVM_L2_CONTEXT14_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK 0x0000FC00L 8300 //MMVM_L2_CONTEXT15_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 8301 #define MMVM_L2_CONTEXT15_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0 8302 #define MMVM_L2_CONTEXT15_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0x5 8303 #define MMVM_L2_CONTEXT15_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa 8304 #define MMVM_L2_CONTEXT15_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL 8305 #define MMVM_L2_CONTEXT15_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000003E0L 8306 #define MMVM_L2_CONTEXT15_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK 0x0000FC00L 8307 8308 8309 // addressBlock: mmhub_mmutcl2_mmvml2pldec 8310 //MMMC_VM_L2_PERFCOUNTER0_CFG 8311 #define MMMC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 8312 #define MMMC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 8313 #define MMMC_VM_L2_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 8314 #define MMMC_VM_L2_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c 8315 #define MMMC_VM_L2_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d 8316 #define MMMC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL 8317 #define MMMC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L 8318 #define MMMC_VM_L2_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L 8319 #define MMMC_VM_L2_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L 8320 #define MMMC_VM_L2_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L 8321 //MMMC_VM_L2_PERFCOUNTER1_CFG 8322 #define MMMC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 8323 #define MMMC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 8324 #define MMMC_VM_L2_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 8325 #define MMMC_VM_L2_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c 8326 #define MMMC_VM_L2_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d 8327 #define MMMC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL 8328 #define MMMC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L 8329 #define MMMC_VM_L2_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L 8330 #define MMMC_VM_L2_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L 8331 #define MMMC_VM_L2_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L 8332 //MMMC_VM_L2_PERFCOUNTER2_CFG 8333 #define MMMC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0 8334 #define MMMC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8 8335 #define MMMC_VM_L2_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18 8336 #define MMMC_VM_L2_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c 8337 #define MMMC_VM_L2_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d 8338 #define MMMC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL_MASK 0x000000FFL 8339 #define MMMC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0x0000FF00L 8340 #define MMMC_VM_L2_PERFCOUNTER2_CFG__PERF_MODE_MASK 0x0F000000L 8341 #define MMMC_VM_L2_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000L 8342 #define MMMC_VM_L2_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000L 8343 //MMMC_VM_L2_PERFCOUNTER3_CFG 8344 #define MMMC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL__SHIFT 0x0 8345 #define MMMC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT 0x8 8346 #define MMMC_VM_L2_PERFCOUNTER3_CFG__PERF_MODE__SHIFT 0x18 8347 #define MMMC_VM_L2_PERFCOUNTER3_CFG__ENABLE__SHIFT 0x1c 8348 #define MMMC_VM_L2_PERFCOUNTER3_CFG__CLEAR__SHIFT 0x1d 8349 #define MMMC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL_MASK 0x000000FFL 8350 #define MMMC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL_END_MASK 0x0000FF00L 8351 #define MMMC_VM_L2_PERFCOUNTER3_CFG__PERF_MODE_MASK 0x0F000000L 8352 #define MMMC_VM_L2_PERFCOUNTER3_CFG__ENABLE_MASK 0x10000000L 8353 #define MMMC_VM_L2_PERFCOUNTER3_CFG__CLEAR_MASK 0x20000000L 8354 //MMMC_VM_L2_PERFCOUNTER4_CFG 8355 #define MMMC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL__SHIFT 0x0 8356 #define MMMC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL_END__SHIFT 0x8 8357 #define MMMC_VM_L2_PERFCOUNTER4_CFG__PERF_MODE__SHIFT 0x18 8358 #define MMMC_VM_L2_PERFCOUNTER4_CFG__ENABLE__SHIFT 0x1c 8359 #define MMMC_VM_L2_PERFCOUNTER4_CFG__CLEAR__SHIFT 0x1d 8360 #define MMMC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL_MASK 0x000000FFL 8361 #define MMMC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL_END_MASK 0x0000FF00L 8362 #define MMMC_VM_L2_PERFCOUNTER4_CFG__PERF_MODE_MASK 0x0F000000L 8363 #define MMMC_VM_L2_PERFCOUNTER4_CFG__ENABLE_MASK 0x10000000L 8364 #define MMMC_VM_L2_PERFCOUNTER4_CFG__CLEAR_MASK 0x20000000L 8365 //MMMC_VM_L2_PERFCOUNTER5_CFG 8366 #define MMMC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL__SHIFT 0x0 8367 #define MMMC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL_END__SHIFT 0x8 8368 #define MMMC_VM_L2_PERFCOUNTER5_CFG__PERF_MODE__SHIFT 0x18 8369 #define MMMC_VM_L2_PERFCOUNTER5_CFG__ENABLE__SHIFT 0x1c 8370 #define MMMC_VM_L2_PERFCOUNTER5_CFG__CLEAR__SHIFT 0x1d 8371 #define MMMC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL_MASK 0x000000FFL 8372 #define MMMC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL_END_MASK 0x0000FF00L 8373 #define MMMC_VM_L2_PERFCOUNTER5_CFG__PERF_MODE_MASK 0x0F000000L 8374 #define MMMC_VM_L2_PERFCOUNTER5_CFG__ENABLE_MASK 0x10000000L 8375 #define MMMC_VM_L2_PERFCOUNTER5_CFG__CLEAR_MASK 0x20000000L 8376 //MMMC_VM_L2_PERFCOUNTER6_CFG 8377 #define MMMC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL__SHIFT 0x0 8378 #define MMMC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL_END__SHIFT 0x8 8379 #define MMMC_VM_L2_PERFCOUNTER6_CFG__PERF_MODE__SHIFT 0x18 8380 #define MMMC_VM_L2_PERFCOUNTER6_CFG__ENABLE__SHIFT 0x1c 8381 #define MMMC_VM_L2_PERFCOUNTER6_CFG__CLEAR__SHIFT 0x1d 8382 #define MMMC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL_MASK 0x000000FFL 8383 #define MMMC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL_END_MASK 0x0000FF00L 8384 #define MMMC_VM_L2_PERFCOUNTER6_CFG__PERF_MODE_MASK 0x0F000000L 8385 #define MMMC_VM_L2_PERFCOUNTER6_CFG__ENABLE_MASK 0x10000000L 8386 #define MMMC_VM_L2_PERFCOUNTER6_CFG__CLEAR_MASK 0x20000000L 8387 //MMMC_VM_L2_PERFCOUNTER7_CFG 8388 #define MMMC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL__SHIFT 0x0 8389 #define MMMC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL_END__SHIFT 0x8 8390 #define MMMC_VM_L2_PERFCOUNTER7_CFG__PERF_MODE__SHIFT 0x18 8391 #define MMMC_VM_L2_PERFCOUNTER7_CFG__ENABLE__SHIFT 0x1c 8392 #define MMMC_VM_L2_PERFCOUNTER7_CFG__CLEAR__SHIFT 0x1d 8393 #define MMMC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL_MASK 0x000000FFL 8394 #define MMMC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL_END_MASK 0x0000FF00L 8395 #define MMMC_VM_L2_PERFCOUNTER7_CFG__PERF_MODE_MASK 0x0F000000L 8396 #define MMMC_VM_L2_PERFCOUNTER7_CFG__ENABLE_MASK 0x10000000L 8397 #define MMMC_VM_L2_PERFCOUNTER7_CFG__CLEAR_MASK 0x20000000L 8398 //MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL 8399 #define MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 8400 #define MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 8401 #define MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 8402 #define MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 8403 #define MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 8404 #define MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a 8405 #define MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL 8406 #define MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L 8407 #define MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L 8408 #define MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L 8409 #define MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L 8410 #define MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L 8411 //MMUTCL2_PERFCOUNTER0_CFG 8412 #define MMUTCL2_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 8413 #define MMUTCL2_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 8414 #define MMUTCL2_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 8415 #define MMUTCL2_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c 8416 #define MMUTCL2_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d 8417 #define MMUTCL2_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL 8418 #define MMUTCL2_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L 8419 #define MMUTCL2_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L 8420 #define MMUTCL2_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L 8421 #define MMUTCL2_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L 8422 //MMUTCL2_PERFCOUNTER1_CFG 8423 #define MMUTCL2_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 8424 #define MMUTCL2_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 8425 #define MMUTCL2_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 8426 #define MMUTCL2_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c 8427 #define MMUTCL2_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d 8428 #define MMUTCL2_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL 8429 #define MMUTCL2_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L 8430 #define MMUTCL2_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L 8431 #define MMUTCL2_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L 8432 #define MMUTCL2_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L 8433 //MMUTCL2_PERFCOUNTER2_CFG 8434 #define MMUTCL2_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0 8435 #define MMUTCL2_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8 8436 #define MMUTCL2_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18 8437 #define MMUTCL2_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c 8438 #define MMUTCL2_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d 8439 #define MMUTCL2_PERFCOUNTER2_CFG__PERF_SEL_MASK 0x000000FFL 8440 #define MMUTCL2_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0x0000FF00L 8441 #define MMUTCL2_PERFCOUNTER2_CFG__PERF_MODE_MASK 0x0F000000L 8442 #define MMUTCL2_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000L 8443 #define MMUTCL2_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000L 8444 //MMUTCL2_PERFCOUNTER3_CFG 8445 #define MMUTCL2_PERFCOUNTER3_CFG__PERF_SEL__SHIFT 0x0 8446 #define MMUTCL2_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT 0x8 8447 #define MMUTCL2_PERFCOUNTER3_CFG__PERF_MODE__SHIFT 0x18 8448 #define MMUTCL2_PERFCOUNTER3_CFG__ENABLE__SHIFT 0x1c 8449 #define MMUTCL2_PERFCOUNTER3_CFG__CLEAR__SHIFT 0x1d 8450 #define MMUTCL2_PERFCOUNTER3_CFG__PERF_SEL_MASK 0x000000FFL 8451 #define MMUTCL2_PERFCOUNTER3_CFG__PERF_SEL_END_MASK 0x0000FF00L 8452 #define MMUTCL2_PERFCOUNTER3_CFG__PERF_MODE_MASK 0x0F000000L 8453 #define MMUTCL2_PERFCOUNTER3_CFG__ENABLE_MASK 0x10000000L 8454 #define MMUTCL2_PERFCOUNTER3_CFG__CLEAR_MASK 0x20000000L 8455 //MMUTCL2_PERFCOUNTER_RSLT_CNTL 8456 #define MMUTCL2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 8457 #define MMUTCL2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 8458 #define MMUTCL2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 8459 #define MMUTCL2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 8460 #define MMUTCL2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 8461 #define MMUTCL2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a 8462 #define MMUTCL2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL 8463 #define MMUTCL2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L 8464 #define MMUTCL2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L 8465 #define MMUTCL2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L 8466 #define MMUTCL2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L 8467 #define MMUTCL2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L 8468 8469 8470 // addressBlock: mmhub_mmutcl2_mmvml2prdec 8471 //MMMC_VM_L2_PERFCOUNTER_LO 8472 #define MMMC_VM_L2_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 8473 #define MMMC_VM_L2_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL 8474 //MMMC_VM_L2_PERFCOUNTER_HI 8475 #define MMMC_VM_L2_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 8476 #define MMMC_VM_L2_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 8477 #define MMMC_VM_L2_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL 8478 #define MMMC_VM_L2_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L 8479 //MMUTCL2_PERFCOUNTER_LO 8480 #define MMUTCL2_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 8481 #define MMUTCL2_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL 8482 //MMUTCL2_PERFCOUNTER_HI 8483 #define MMUTCL2_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 8484 #define MMUTCL2_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 8485 #define MMUTCL2_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL 8486 #define MMUTCL2_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L 8487 8488 8489 // addressBlock: mmhub_mmutcl2_mmvmsharedhvdec 8490 //MMMC_VM_FB_SIZE_OFFSET_VF0 8491 #define MMMC_VM_FB_SIZE_OFFSET_VF0__VF_FB_SIZE__SHIFT 0x0 8492 #define MMMC_VM_FB_SIZE_OFFSET_VF0__VF_FB_OFFSET__SHIFT 0x10 8493 #define MMMC_VM_FB_SIZE_OFFSET_VF0__VF_FB_SIZE_MASK 0x0000FFFFL 8494 #define MMMC_VM_FB_SIZE_OFFSET_VF0__VF_FB_OFFSET_MASK 0xFFFF0000L 8495 //MMMC_VM_FB_SIZE_OFFSET_VF1 8496 #define MMMC_VM_FB_SIZE_OFFSET_VF1__VF_FB_SIZE__SHIFT 0x0 8497 #define MMMC_VM_FB_SIZE_OFFSET_VF1__VF_FB_OFFSET__SHIFT 0x10 8498 #define MMMC_VM_FB_SIZE_OFFSET_VF1__VF_FB_SIZE_MASK 0x0000FFFFL 8499 #define MMMC_VM_FB_SIZE_OFFSET_VF1__VF_FB_OFFSET_MASK 0xFFFF0000L 8500 //MMMC_VM_FB_SIZE_OFFSET_VF2 8501 #define MMMC_VM_FB_SIZE_OFFSET_VF2__VF_FB_SIZE__SHIFT 0x0 8502 #define MMMC_VM_FB_SIZE_OFFSET_VF2__VF_FB_OFFSET__SHIFT 0x10 8503 #define MMMC_VM_FB_SIZE_OFFSET_VF2__VF_FB_SIZE_MASK 0x0000FFFFL 8504 #define MMMC_VM_FB_SIZE_OFFSET_VF2__VF_FB_OFFSET_MASK 0xFFFF0000L 8505 //MMMC_VM_FB_SIZE_OFFSET_VF3 8506 #define MMMC_VM_FB_SIZE_OFFSET_VF3__VF_FB_SIZE__SHIFT 0x0 8507 #define MMMC_VM_FB_SIZE_OFFSET_VF3__VF_FB_OFFSET__SHIFT 0x10 8508 #define MMMC_VM_FB_SIZE_OFFSET_VF3__VF_FB_SIZE_MASK 0x0000FFFFL 8509 #define MMMC_VM_FB_SIZE_OFFSET_VF3__VF_FB_OFFSET_MASK 0xFFFF0000L 8510 //MMMC_VM_FB_SIZE_OFFSET_VF4 8511 #define MMMC_VM_FB_SIZE_OFFSET_VF4__VF_FB_SIZE__SHIFT 0x0 8512 #define MMMC_VM_FB_SIZE_OFFSET_VF4__VF_FB_OFFSET__SHIFT 0x10 8513 #define MMMC_VM_FB_SIZE_OFFSET_VF4__VF_FB_SIZE_MASK 0x0000FFFFL 8514 #define MMMC_VM_FB_SIZE_OFFSET_VF4__VF_FB_OFFSET_MASK 0xFFFF0000L 8515 //MMMC_VM_FB_SIZE_OFFSET_VF5 8516 #define MMMC_VM_FB_SIZE_OFFSET_VF5__VF_FB_SIZE__SHIFT 0x0 8517 #define MMMC_VM_FB_SIZE_OFFSET_VF5__VF_FB_OFFSET__SHIFT 0x10 8518 #define MMMC_VM_FB_SIZE_OFFSET_VF5__VF_FB_SIZE_MASK 0x0000FFFFL 8519 #define MMMC_VM_FB_SIZE_OFFSET_VF5__VF_FB_OFFSET_MASK 0xFFFF0000L 8520 //MMMC_VM_FB_SIZE_OFFSET_VF6 8521 #define MMMC_VM_FB_SIZE_OFFSET_VF6__VF_FB_SIZE__SHIFT 0x0 8522 #define MMMC_VM_FB_SIZE_OFFSET_VF6__VF_FB_OFFSET__SHIFT 0x10 8523 #define MMMC_VM_FB_SIZE_OFFSET_VF6__VF_FB_SIZE_MASK 0x0000FFFFL 8524 #define MMMC_VM_FB_SIZE_OFFSET_VF6__VF_FB_OFFSET_MASK 0xFFFF0000L 8525 //MMMC_VM_FB_SIZE_OFFSET_VF7 8526 #define MMMC_VM_FB_SIZE_OFFSET_VF7__VF_FB_SIZE__SHIFT 0x0 8527 #define MMMC_VM_FB_SIZE_OFFSET_VF7__VF_FB_OFFSET__SHIFT 0x10 8528 #define MMMC_VM_FB_SIZE_OFFSET_VF7__VF_FB_SIZE_MASK 0x0000FFFFL 8529 #define MMMC_VM_FB_SIZE_OFFSET_VF7__VF_FB_OFFSET_MASK 0xFFFF0000L 8530 //MMMC_VM_FB_SIZE_OFFSET_VF8 8531 #define MMMC_VM_FB_SIZE_OFFSET_VF8__VF_FB_SIZE__SHIFT 0x0 8532 #define MMMC_VM_FB_SIZE_OFFSET_VF8__VF_FB_OFFSET__SHIFT 0x10 8533 #define MMMC_VM_FB_SIZE_OFFSET_VF8__VF_FB_SIZE_MASK 0x0000FFFFL 8534 #define MMMC_VM_FB_SIZE_OFFSET_VF8__VF_FB_OFFSET_MASK 0xFFFF0000L 8535 //MMMC_VM_FB_SIZE_OFFSET_VF9 8536 #define MMMC_VM_FB_SIZE_OFFSET_VF9__VF_FB_SIZE__SHIFT 0x0 8537 #define MMMC_VM_FB_SIZE_OFFSET_VF9__VF_FB_OFFSET__SHIFT 0x10 8538 #define MMMC_VM_FB_SIZE_OFFSET_VF9__VF_FB_SIZE_MASK 0x0000FFFFL 8539 #define MMMC_VM_FB_SIZE_OFFSET_VF9__VF_FB_OFFSET_MASK 0xFFFF0000L 8540 //MMMC_VM_FB_SIZE_OFFSET_VF10 8541 #define MMMC_VM_FB_SIZE_OFFSET_VF10__VF_FB_SIZE__SHIFT 0x0 8542 #define MMMC_VM_FB_SIZE_OFFSET_VF10__VF_FB_OFFSET__SHIFT 0x10 8543 #define MMMC_VM_FB_SIZE_OFFSET_VF10__VF_FB_SIZE_MASK 0x0000FFFFL 8544 #define MMMC_VM_FB_SIZE_OFFSET_VF10__VF_FB_OFFSET_MASK 0xFFFF0000L 8545 //MMMC_VM_FB_SIZE_OFFSET_VF11 8546 #define MMMC_VM_FB_SIZE_OFFSET_VF11__VF_FB_SIZE__SHIFT 0x0 8547 #define MMMC_VM_FB_SIZE_OFFSET_VF11__VF_FB_OFFSET__SHIFT 0x10 8548 #define MMMC_VM_FB_SIZE_OFFSET_VF11__VF_FB_SIZE_MASK 0x0000FFFFL 8549 #define MMMC_VM_FB_SIZE_OFFSET_VF11__VF_FB_OFFSET_MASK 0xFFFF0000L 8550 //MMMC_VM_FB_SIZE_OFFSET_VF12 8551 #define MMMC_VM_FB_SIZE_OFFSET_VF12__VF_FB_SIZE__SHIFT 0x0 8552 #define MMMC_VM_FB_SIZE_OFFSET_VF12__VF_FB_OFFSET__SHIFT 0x10 8553 #define MMMC_VM_FB_SIZE_OFFSET_VF12__VF_FB_SIZE_MASK 0x0000FFFFL 8554 #define MMMC_VM_FB_SIZE_OFFSET_VF12__VF_FB_OFFSET_MASK 0xFFFF0000L 8555 //MMMC_VM_FB_SIZE_OFFSET_VF13 8556 #define MMMC_VM_FB_SIZE_OFFSET_VF13__VF_FB_SIZE__SHIFT 0x0 8557 #define MMMC_VM_FB_SIZE_OFFSET_VF13__VF_FB_OFFSET__SHIFT 0x10 8558 #define MMMC_VM_FB_SIZE_OFFSET_VF13__VF_FB_SIZE_MASK 0x0000FFFFL 8559 #define MMMC_VM_FB_SIZE_OFFSET_VF13__VF_FB_OFFSET_MASK 0xFFFF0000L 8560 //MMMC_VM_FB_SIZE_OFFSET_VF14 8561 #define MMMC_VM_FB_SIZE_OFFSET_VF14__VF_FB_SIZE__SHIFT 0x0 8562 #define MMMC_VM_FB_SIZE_OFFSET_VF14__VF_FB_OFFSET__SHIFT 0x10 8563 #define MMMC_VM_FB_SIZE_OFFSET_VF14__VF_FB_SIZE_MASK 0x0000FFFFL 8564 #define MMMC_VM_FB_SIZE_OFFSET_VF14__VF_FB_OFFSET_MASK 0xFFFF0000L 8565 //MMMC_VM_FB_SIZE_OFFSET_VF15 8566 #define MMMC_VM_FB_SIZE_OFFSET_VF15__VF_FB_SIZE__SHIFT 0x0 8567 #define MMMC_VM_FB_SIZE_OFFSET_VF15__VF_FB_OFFSET__SHIFT 0x10 8568 #define MMMC_VM_FB_SIZE_OFFSET_VF15__VF_FB_SIZE_MASK 0x0000FFFFL 8569 #define MMMC_VM_FB_SIZE_OFFSET_VF15__VF_FB_OFFSET_MASK 0xFFFF0000L 8570 //MMMC_VM_FB_SIZE_OFFSET_VF16 8571 #define MMMC_VM_FB_SIZE_OFFSET_VF16__VF_FB_SIZE__SHIFT 0x0 8572 #define MMMC_VM_FB_SIZE_OFFSET_VF16__VF_FB_OFFSET__SHIFT 0x10 8573 #define MMMC_VM_FB_SIZE_OFFSET_VF16__VF_FB_SIZE_MASK 0x0000FFFFL 8574 #define MMMC_VM_FB_SIZE_OFFSET_VF16__VF_FB_OFFSET_MASK 0xFFFF0000L 8575 //MMMC_VM_FB_SIZE_OFFSET_VF17 8576 #define MMMC_VM_FB_SIZE_OFFSET_VF17__VF_FB_SIZE__SHIFT 0x0 8577 #define MMMC_VM_FB_SIZE_OFFSET_VF17__VF_FB_OFFSET__SHIFT 0x10 8578 #define MMMC_VM_FB_SIZE_OFFSET_VF17__VF_FB_SIZE_MASK 0x0000FFFFL 8579 #define MMMC_VM_FB_SIZE_OFFSET_VF17__VF_FB_OFFSET_MASK 0xFFFF0000L 8580 //MMMC_VM_FB_SIZE_OFFSET_VF18 8581 #define MMMC_VM_FB_SIZE_OFFSET_VF18__VF_FB_SIZE__SHIFT 0x0 8582 #define MMMC_VM_FB_SIZE_OFFSET_VF18__VF_FB_OFFSET__SHIFT 0x10 8583 #define MMMC_VM_FB_SIZE_OFFSET_VF18__VF_FB_SIZE_MASK 0x0000FFFFL 8584 #define MMMC_VM_FB_SIZE_OFFSET_VF18__VF_FB_OFFSET_MASK 0xFFFF0000L 8585 //MMMC_VM_FB_SIZE_OFFSET_VF19 8586 #define MMMC_VM_FB_SIZE_OFFSET_VF19__VF_FB_SIZE__SHIFT 0x0 8587 #define MMMC_VM_FB_SIZE_OFFSET_VF19__VF_FB_OFFSET__SHIFT 0x10 8588 #define MMMC_VM_FB_SIZE_OFFSET_VF19__VF_FB_SIZE_MASK 0x0000FFFFL 8589 #define MMMC_VM_FB_SIZE_OFFSET_VF19__VF_FB_OFFSET_MASK 0xFFFF0000L 8590 //MMMC_VM_FB_SIZE_OFFSET_VF20 8591 #define MMMC_VM_FB_SIZE_OFFSET_VF20__VF_FB_SIZE__SHIFT 0x0 8592 #define MMMC_VM_FB_SIZE_OFFSET_VF20__VF_FB_OFFSET__SHIFT 0x10 8593 #define MMMC_VM_FB_SIZE_OFFSET_VF20__VF_FB_SIZE_MASK 0x0000FFFFL 8594 #define MMMC_VM_FB_SIZE_OFFSET_VF20__VF_FB_OFFSET_MASK 0xFFFF0000L 8595 //MMMC_VM_FB_SIZE_OFFSET_VF21 8596 #define MMMC_VM_FB_SIZE_OFFSET_VF21__VF_FB_SIZE__SHIFT 0x0 8597 #define MMMC_VM_FB_SIZE_OFFSET_VF21__VF_FB_OFFSET__SHIFT 0x10 8598 #define MMMC_VM_FB_SIZE_OFFSET_VF21__VF_FB_SIZE_MASK 0x0000FFFFL 8599 #define MMMC_VM_FB_SIZE_OFFSET_VF21__VF_FB_OFFSET_MASK 0xFFFF0000L 8600 //MMMC_VM_FB_SIZE_OFFSET_VF22 8601 #define MMMC_VM_FB_SIZE_OFFSET_VF22__VF_FB_SIZE__SHIFT 0x0 8602 #define MMMC_VM_FB_SIZE_OFFSET_VF22__VF_FB_OFFSET__SHIFT 0x10 8603 #define MMMC_VM_FB_SIZE_OFFSET_VF22__VF_FB_SIZE_MASK 0x0000FFFFL 8604 #define MMMC_VM_FB_SIZE_OFFSET_VF22__VF_FB_OFFSET_MASK 0xFFFF0000L 8605 //MMMC_VM_FB_SIZE_OFFSET_VF23 8606 #define MMMC_VM_FB_SIZE_OFFSET_VF23__VF_FB_SIZE__SHIFT 0x0 8607 #define MMMC_VM_FB_SIZE_OFFSET_VF23__VF_FB_OFFSET__SHIFT 0x10 8608 #define MMMC_VM_FB_SIZE_OFFSET_VF23__VF_FB_SIZE_MASK 0x0000FFFFL 8609 #define MMMC_VM_FB_SIZE_OFFSET_VF23__VF_FB_OFFSET_MASK 0xFFFF0000L 8610 //MMMC_VM_FB_SIZE_OFFSET_VF24 8611 #define MMMC_VM_FB_SIZE_OFFSET_VF24__VF_FB_SIZE__SHIFT 0x0 8612 #define MMMC_VM_FB_SIZE_OFFSET_VF24__VF_FB_OFFSET__SHIFT 0x10 8613 #define MMMC_VM_FB_SIZE_OFFSET_VF24__VF_FB_SIZE_MASK 0x0000FFFFL 8614 #define MMMC_VM_FB_SIZE_OFFSET_VF24__VF_FB_OFFSET_MASK 0xFFFF0000L 8615 //MMMC_VM_FB_SIZE_OFFSET_VF25 8616 #define MMMC_VM_FB_SIZE_OFFSET_VF25__VF_FB_SIZE__SHIFT 0x0 8617 #define MMMC_VM_FB_SIZE_OFFSET_VF25__VF_FB_OFFSET__SHIFT 0x10 8618 #define MMMC_VM_FB_SIZE_OFFSET_VF25__VF_FB_SIZE_MASK 0x0000FFFFL 8619 #define MMMC_VM_FB_SIZE_OFFSET_VF25__VF_FB_OFFSET_MASK 0xFFFF0000L 8620 //MMMC_VM_FB_SIZE_OFFSET_VF26 8621 #define MMMC_VM_FB_SIZE_OFFSET_VF26__VF_FB_SIZE__SHIFT 0x0 8622 #define MMMC_VM_FB_SIZE_OFFSET_VF26__VF_FB_OFFSET__SHIFT 0x10 8623 #define MMMC_VM_FB_SIZE_OFFSET_VF26__VF_FB_SIZE_MASK 0x0000FFFFL 8624 #define MMMC_VM_FB_SIZE_OFFSET_VF26__VF_FB_OFFSET_MASK 0xFFFF0000L 8625 //MMMC_VM_FB_SIZE_OFFSET_VF27 8626 #define MMMC_VM_FB_SIZE_OFFSET_VF27__VF_FB_SIZE__SHIFT 0x0 8627 #define MMMC_VM_FB_SIZE_OFFSET_VF27__VF_FB_OFFSET__SHIFT 0x10 8628 #define MMMC_VM_FB_SIZE_OFFSET_VF27__VF_FB_SIZE_MASK 0x0000FFFFL 8629 #define MMMC_VM_FB_SIZE_OFFSET_VF27__VF_FB_OFFSET_MASK 0xFFFF0000L 8630 //MMMC_VM_FB_SIZE_OFFSET_VF28 8631 #define MMMC_VM_FB_SIZE_OFFSET_VF28__VF_FB_SIZE__SHIFT 0x0 8632 #define MMMC_VM_FB_SIZE_OFFSET_VF28__VF_FB_OFFSET__SHIFT 0x10 8633 #define MMMC_VM_FB_SIZE_OFFSET_VF28__VF_FB_SIZE_MASK 0x0000FFFFL 8634 #define MMMC_VM_FB_SIZE_OFFSET_VF28__VF_FB_OFFSET_MASK 0xFFFF0000L 8635 //MMMC_VM_FB_SIZE_OFFSET_VF29 8636 #define MMMC_VM_FB_SIZE_OFFSET_VF29__VF_FB_SIZE__SHIFT 0x0 8637 #define MMMC_VM_FB_SIZE_OFFSET_VF29__VF_FB_OFFSET__SHIFT 0x10 8638 #define MMMC_VM_FB_SIZE_OFFSET_VF29__VF_FB_SIZE_MASK 0x0000FFFFL 8639 #define MMMC_VM_FB_SIZE_OFFSET_VF29__VF_FB_OFFSET_MASK 0xFFFF0000L 8640 //MMMC_VM_FB_SIZE_OFFSET_VF30 8641 #define MMMC_VM_FB_SIZE_OFFSET_VF30__VF_FB_SIZE__SHIFT 0x0 8642 #define MMMC_VM_FB_SIZE_OFFSET_VF30__VF_FB_OFFSET__SHIFT 0x10 8643 #define MMMC_VM_FB_SIZE_OFFSET_VF30__VF_FB_SIZE_MASK 0x0000FFFFL 8644 #define MMMC_VM_FB_SIZE_OFFSET_VF30__VF_FB_OFFSET_MASK 0xFFFF0000L 8645 //MMMC_VM_FB_SIZE_OFFSET_VF31 8646 #define MMMC_VM_FB_SIZE_OFFSET_VF31__VF_FB_SIZE__SHIFT 0x0 8647 #define MMMC_VM_FB_SIZE_OFFSET_VF31__VF_FB_OFFSET__SHIFT 0x10 8648 #define MMMC_VM_FB_SIZE_OFFSET_VF31__VF_FB_SIZE_MASK 0x0000FFFFL 8649 #define MMMC_VM_FB_SIZE_OFFSET_VF31__VF_FB_OFFSET_MASK 0xFFFF0000L 8650 //MMVM_IOMMU_MMIO_CNTRL_1 8651 #define MMVM_IOMMU_MMIO_CNTRL_1__MARC_EN__SHIFT 0x8 8652 #define MMVM_IOMMU_MMIO_CNTRL_1__MARC_EN_MASK 0x00000100L 8653 //MMMC_VM_MARC_BASE_LO_0 8654 #define MMMC_VM_MARC_BASE_LO_0__MARC_BASE_LO_0__SHIFT 0xc 8655 #define MMMC_VM_MARC_BASE_LO_0__MARC_BASE_LO_0_MASK 0xFFFFF000L 8656 //MMMC_VM_MARC_BASE_LO_1 8657 #define MMMC_VM_MARC_BASE_LO_1__MARC_BASE_LO_1__SHIFT 0xc 8658 #define MMMC_VM_MARC_BASE_LO_1__MARC_BASE_LO_1_MASK 0xFFFFF000L 8659 //MMMC_VM_MARC_BASE_LO_2 8660 #define MMMC_VM_MARC_BASE_LO_2__MARC_BASE_LO_2__SHIFT 0xc 8661 #define MMMC_VM_MARC_BASE_LO_2__MARC_BASE_LO_2_MASK 0xFFFFF000L 8662 //MMMC_VM_MARC_BASE_LO_3 8663 #define MMMC_VM_MARC_BASE_LO_3__MARC_BASE_LO_3__SHIFT 0xc 8664 #define MMMC_VM_MARC_BASE_LO_3__MARC_BASE_LO_3_MASK 0xFFFFF000L 8665 //MMMC_VM_MARC_BASE_HI_0 8666 #define MMMC_VM_MARC_BASE_HI_0__MARC_BASE_HI_0__SHIFT 0x0 8667 #define MMMC_VM_MARC_BASE_HI_0__MARC_BASE_HI_0_MASK 0x000FFFFFL 8668 //MMMC_VM_MARC_BASE_HI_1 8669 #define MMMC_VM_MARC_BASE_HI_1__MARC_BASE_HI_1__SHIFT 0x0 8670 #define MMMC_VM_MARC_BASE_HI_1__MARC_BASE_HI_1_MASK 0x000FFFFFL 8671 //MMMC_VM_MARC_BASE_HI_2 8672 #define MMMC_VM_MARC_BASE_HI_2__MARC_BASE_HI_2__SHIFT 0x0 8673 #define MMMC_VM_MARC_BASE_HI_2__MARC_BASE_HI_2_MASK 0x000FFFFFL 8674 //MMMC_VM_MARC_BASE_HI_3 8675 #define MMMC_VM_MARC_BASE_HI_3__MARC_BASE_HI_3__SHIFT 0x0 8676 #define MMMC_VM_MARC_BASE_HI_3__MARC_BASE_HI_3_MASK 0x000FFFFFL 8677 //MMMC_VM_MARC_RELOC_LO_0 8678 #define MMMC_VM_MARC_RELOC_LO_0__MARC_ENABLE_0__SHIFT 0x0 8679 #define MMMC_VM_MARC_RELOC_LO_0__MARC_READONLY_0__SHIFT 0x1 8680 #define MMMC_VM_MARC_RELOC_LO_0__MARC_RELOC_LO_0__SHIFT 0xc 8681 #define MMMC_VM_MARC_RELOC_LO_0__MARC_ENABLE_0_MASK 0x00000001L 8682 #define MMMC_VM_MARC_RELOC_LO_0__MARC_READONLY_0_MASK 0x00000002L 8683 #define MMMC_VM_MARC_RELOC_LO_0__MARC_RELOC_LO_0_MASK 0xFFFFF000L 8684 //MMMC_VM_MARC_RELOC_LO_1 8685 #define MMMC_VM_MARC_RELOC_LO_1__MARC_ENABLE_1__SHIFT 0x0 8686 #define MMMC_VM_MARC_RELOC_LO_1__MARC_READONLY_1__SHIFT 0x1 8687 #define MMMC_VM_MARC_RELOC_LO_1__MARC_RELOC_LO_1__SHIFT 0xc 8688 #define MMMC_VM_MARC_RELOC_LO_1__MARC_ENABLE_1_MASK 0x00000001L 8689 #define MMMC_VM_MARC_RELOC_LO_1__MARC_READONLY_1_MASK 0x00000002L 8690 #define MMMC_VM_MARC_RELOC_LO_1__MARC_RELOC_LO_1_MASK 0xFFFFF000L 8691 //MMMC_VM_MARC_RELOC_LO_2 8692 #define MMMC_VM_MARC_RELOC_LO_2__MARC_ENABLE_2__SHIFT 0x0 8693 #define MMMC_VM_MARC_RELOC_LO_2__MARC_READONLY_2__SHIFT 0x1 8694 #define MMMC_VM_MARC_RELOC_LO_2__MARC_RELOC_LO_2__SHIFT 0xc 8695 #define MMMC_VM_MARC_RELOC_LO_2__MARC_ENABLE_2_MASK 0x00000001L 8696 #define MMMC_VM_MARC_RELOC_LO_2__MARC_READONLY_2_MASK 0x00000002L 8697 #define MMMC_VM_MARC_RELOC_LO_2__MARC_RELOC_LO_2_MASK 0xFFFFF000L 8698 //MMMC_VM_MARC_RELOC_LO_3 8699 #define MMMC_VM_MARC_RELOC_LO_3__MARC_ENABLE_3__SHIFT 0x0 8700 #define MMMC_VM_MARC_RELOC_LO_3__MARC_READONLY_3__SHIFT 0x1 8701 #define MMMC_VM_MARC_RELOC_LO_3__MARC_RELOC_LO_3__SHIFT 0xc 8702 #define MMMC_VM_MARC_RELOC_LO_3__MARC_ENABLE_3_MASK 0x00000001L 8703 #define MMMC_VM_MARC_RELOC_LO_3__MARC_READONLY_3_MASK 0x00000002L 8704 #define MMMC_VM_MARC_RELOC_LO_3__MARC_RELOC_LO_3_MASK 0xFFFFF000L 8705 //MMMC_VM_MARC_RELOC_HI_0 8706 #define MMMC_VM_MARC_RELOC_HI_0__MARC_RELOC_HI_0__SHIFT 0x0 8707 #define MMMC_VM_MARC_RELOC_HI_0__MARC_RELOC_HI_0_MASK 0x000FFFFFL 8708 //MMMC_VM_MARC_RELOC_HI_1 8709 #define MMMC_VM_MARC_RELOC_HI_1__MARC_RELOC_HI_1__SHIFT 0x0 8710 #define MMMC_VM_MARC_RELOC_HI_1__MARC_RELOC_HI_1_MASK 0x000FFFFFL 8711 //MMMC_VM_MARC_RELOC_HI_2 8712 #define MMMC_VM_MARC_RELOC_HI_2__MARC_RELOC_HI_2__SHIFT 0x0 8713 #define MMMC_VM_MARC_RELOC_HI_2__MARC_RELOC_HI_2_MASK 0x000FFFFFL 8714 //MMMC_VM_MARC_RELOC_HI_3 8715 #define MMMC_VM_MARC_RELOC_HI_3__MARC_RELOC_HI_3__SHIFT 0x0 8716 #define MMMC_VM_MARC_RELOC_HI_3__MARC_RELOC_HI_3_MASK 0x000FFFFFL 8717 //MMMC_VM_MARC_LEN_LO_0 8718 #define MMMC_VM_MARC_LEN_LO_0__MARC_LEN_LO_0__SHIFT 0xc 8719 #define MMMC_VM_MARC_LEN_LO_0__MARC_LEN_LO_0_MASK 0xFFFFF000L 8720 //MMMC_VM_MARC_LEN_LO_1 8721 #define MMMC_VM_MARC_LEN_LO_1__MARC_LEN_LO_1__SHIFT 0xc 8722 #define MMMC_VM_MARC_LEN_LO_1__MARC_LEN_LO_1_MASK 0xFFFFF000L 8723 //MMMC_VM_MARC_LEN_LO_2 8724 #define MMMC_VM_MARC_LEN_LO_2__MARC_LEN_LO_2__SHIFT 0xc 8725 #define MMMC_VM_MARC_LEN_LO_2__MARC_LEN_LO_2_MASK 0xFFFFF000L 8726 //MMMC_VM_MARC_LEN_LO_3 8727 #define MMMC_VM_MARC_LEN_LO_3__MARC_LEN_LO_3__SHIFT 0xc 8728 #define MMMC_VM_MARC_LEN_LO_3__MARC_LEN_LO_3_MASK 0xFFFFF000L 8729 //MMMC_VM_MARC_LEN_HI_0 8730 #define MMMC_VM_MARC_LEN_HI_0__MARC_LEN_HI_0__SHIFT 0x0 8731 #define MMMC_VM_MARC_LEN_HI_0__MARC_LEN_HI_0_MASK 0x000FFFFFL 8732 //MMMC_VM_MARC_LEN_HI_1 8733 #define MMMC_VM_MARC_LEN_HI_1__MARC_LEN_HI_1__SHIFT 0x0 8734 #define MMMC_VM_MARC_LEN_HI_1__MARC_LEN_HI_1_MASK 0x000FFFFFL 8735 //MMMC_VM_MARC_LEN_HI_2 8736 #define MMMC_VM_MARC_LEN_HI_2__MARC_LEN_HI_2__SHIFT 0x0 8737 #define MMMC_VM_MARC_LEN_HI_2__MARC_LEN_HI_2_MASK 0x000FFFFFL 8738 //MMMC_VM_MARC_LEN_HI_3 8739 #define MMMC_VM_MARC_LEN_HI_3__MARC_LEN_HI_3__SHIFT 0x0 8740 #define MMMC_VM_MARC_LEN_HI_3__MARC_LEN_HI_3_MASK 0x000FFFFFL 8741 //MMVM_IOMMU_CONTROL_REGISTER 8742 #define MMVM_IOMMU_CONTROL_REGISTER__IOMMUEN__SHIFT 0x0 8743 #define MMVM_IOMMU_CONTROL_REGISTER__IOMMUEN_MASK 0x00000001L 8744 //MMVM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER 8745 #define MMVM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER__PERFOPTEN__SHIFT 0xd 8746 #define MMVM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER__PERFOPTEN_MASK 0x00002000L 8747 //MMVM_PCIE_ATS_CNTL 8748 #define MMVM_PCIE_ATS_CNTL__STU__SHIFT 0x10 8749 #define MMVM_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0x1f 8750 #define MMVM_PCIE_ATS_CNTL__STU_MASK 0x001F0000L 8751 #define MMVM_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x80000000L 8752 //MMVM_PCIE_ATS_CNTL_VF_0 8753 #define MMVM_PCIE_ATS_CNTL_VF_0__ATC_ENABLE__SHIFT 0x1f 8754 #define MMVM_PCIE_ATS_CNTL_VF_0__ATC_ENABLE_MASK 0x80000000L 8755 //MMVM_PCIE_ATS_CNTL_VF_1 8756 #define MMVM_PCIE_ATS_CNTL_VF_1__ATC_ENABLE__SHIFT 0x1f 8757 #define MMVM_PCIE_ATS_CNTL_VF_1__ATC_ENABLE_MASK 0x80000000L 8758 //MMVM_PCIE_ATS_CNTL_VF_2 8759 #define MMVM_PCIE_ATS_CNTL_VF_2__ATC_ENABLE__SHIFT 0x1f 8760 #define MMVM_PCIE_ATS_CNTL_VF_2__ATC_ENABLE_MASK 0x80000000L 8761 //MMVM_PCIE_ATS_CNTL_VF_3 8762 #define MMVM_PCIE_ATS_CNTL_VF_3__ATC_ENABLE__SHIFT 0x1f 8763 #define MMVM_PCIE_ATS_CNTL_VF_3__ATC_ENABLE_MASK 0x80000000L 8764 //MMVM_PCIE_ATS_CNTL_VF_4 8765 #define MMVM_PCIE_ATS_CNTL_VF_4__ATC_ENABLE__SHIFT 0x1f 8766 #define MMVM_PCIE_ATS_CNTL_VF_4__ATC_ENABLE_MASK 0x80000000L 8767 //MMVM_PCIE_ATS_CNTL_VF_5 8768 #define MMVM_PCIE_ATS_CNTL_VF_5__ATC_ENABLE__SHIFT 0x1f 8769 #define MMVM_PCIE_ATS_CNTL_VF_5__ATC_ENABLE_MASK 0x80000000L 8770 //MMVM_PCIE_ATS_CNTL_VF_6 8771 #define MMVM_PCIE_ATS_CNTL_VF_6__ATC_ENABLE__SHIFT 0x1f 8772 #define MMVM_PCIE_ATS_CNTL_VF_6__ATC_ENABLE_MASK 0x80000000L 8773 //MMVM_PCIE_ATS_CNTL_VF_7 8774 #define MMVM_PCIE_ATS_CNTL_VF_7__ATC_ENABLE__SHIFT 0x1f 8775 #define MMVM_PCIE_ATS_CNTL_VF_7__ATC_ENABLE_MASK 0x80000000L 8776 //MMVM_PCIE_ATS_CNTL_VF_8 8777 #define MMVM_PCIE_ATS_CNTL_VF_8__ATC_ENABLE__SHIFT 0x1f 8778 #define MMVM_PCIE_ATS_CNTL_VF_8__ATC_ENABLE_MASK 0x80000000L 8779 //MMVM_PCIE_ATS_CNTL_VF_9 8780 #define MMVM_PCIE_ATS_CNTL_VF_9__ATC_ENABLE__SHIFT 0x1f 8781 #define MMVM_PCIE_ATS_CNTL_VF_9__ATC_ENABLE_MASK 0x80000000L 8782 //MMVM_PCIE_ATS_CNTL_VF_10 8783 #define MMVM_PCIE_ATS_CNTL_VF_10__ATC_ENABLE__SHIFT 0x1f 8784 #define MMVM_PCIE_ATS_CNTL_VF_10__ATC_ENABLE_MASK 0x80000000L 8785 //MMVM_PCIE_ATS_CNTL_VF_11 8786 #define MMVM_PCIE_ATS_CNTL_VF_11__ATC_ENABLE__SHIFT 0x1f 8787 #define MMVM_PCIE_ATS_CNTL_VF_11__ATC_ENABLE_MASK 0x80000000L 8788 //MMVM_PCIE_ATS_CNTL_VF_12 8789 #define MMVM_PCIE_ATS_CNTL_VF_12__ATC_ENABLE__SHIFT 0x1f 8790 #define MMVM_PCIE_ATS_CNTL_VF_12__ATC_ENABLE_MASK 0x80000000L 8791 //MMVM_PCIE_ATS_CNTL_VF_13 8792 #define MMVM_PCIE_ATS_CNTL_VF_13__ATC_ENABLE__SHIFT 0x1f 8793 #define MMVM_PCIE_ATS_CNTL_VF_13__ATC_ENABLE_MASK 0x80000000L 8794 //MMVM_PCIE_ATS_CNTL_VF_14 8795 #define MMVM_PCIE_ATS_CNTL_VF_14__ATC_ENABLE__SHIFT 0x1f 8796 #define MMVM_PCIE_ATS_CNTL_VF_14__ATC_ENABLE_MASK 0x80000000L 8797 //MMVM_PCIE_ATS_CNTL_VF_15 8798 #define MMVM_PCIE_ATS_CNTL_VF_15__ATC_ENABLE__SHIFT 0x1f 8799 #define MMVM_PCIE_ATS_CNTL_VF_15__ATC_ENABLE_MASK 0x80000000L 8800 //MMVM_PCIE_ATS_CNTL_VF_16 8801 #define MMVM_PCIE_ATS_CNTL_VF_16__ATC_ENABLE__SHIFT 0x1f 8802 #define MMVM_PCIE_ATS_CNTL_VF_16__ATC_ENABLE_MASK 0x80000000L 8803 //MMVM_PCIE_ATS_CNTL_VF_17 8804 #define MMVM_PCIE_ATS_CNTL_VF_17__ATC_ENABLE__SHIFT 0x1f 8805 #define MMVM_PCIE_ATS_CNTL_VF_17__ATC_ENABLE_MASK 0x80000000L 8806 //MMVM_PCIE_ATS_CNTL_VF_18 8807 #define MMVM_PCIE_ATS_CNTL_VF_18__ATC_ENABLE__SHIFT 0x1f 8808 #define MMVM_PCIE_ATS_CNTL_VF_18__ATC_ENABLE_MASK 0x80000000L 8809 //MMVM_PCIE_ATS_CNTL_VF_19 8810 #define MMVM_PCIE_ATS_CNTL_VF_19__ATC_ENABLE__SHIFT 0x1f 8811 #define MMVM_PCIE_ATS_CNTL_VF_19__ATC_ENABLE_MASK 0x80000000L 8812 //MMVM_PCIE_ATS_CNTL_VF_20 8813 #define MMVM_PCIE_ATS_CNTL_VF_20__ATC_ENABLE__SHIFT 0x1f 8814 #define MMVM_PCIE_ATS_CNTL_VF_20__ATC_ENABLE_MASK 0x80000000L 8815 //MMVM_PCIE_ATS_CNTL_VF_21 8816 #define MMVM_PCIE_ATS_CNTL_VF_21__ATC_ENABLE__SHIFT 0x1f 8817 #define MMVM_PCIE_ATS_CNTL_VF_21__ATC_ENABLE_MASK 0x80000000L 8818 //MMVM_PCIE_ATS_CNTL_VF_22 8819 #define MMVM_PCIE_ATS_CNTL_VF_22__ATC_ENABLE__SHIFT 0x1f 8820 #define MMVM_PCIE_ATS_CNTL_VF_22__ATC_ENABLE_MASK 0x80000000L 8821 //MMVM_PCIE_ATS_CNTL_VF_23 8822 #define MMVM_PCIE_ATS_CNTL_VF_23__ATC_ENABLE__SHIFT 0x1f 8823 #define MMVM_PCIE_ATS_CNTL_VF_23__ATC_ENABLE_MASK 0x80000000L 8824 //MMVM_PCIE_ATS_CNTL_VF_24 8825 #define MMVM_PCIE_ATS_CNTL_VF_24__ATC_ENABLE__SHIFT 0x1f 8826 #define MMVM_PCIE_ATS_CNTL_VF_24__ATC_ENABLE_MASK 0x80000000L 8827 //MMVM_PCIE_ATS_CNTL_VF_25 8828 #define MMVM_PCIE_ATS_CNTL_VF_25__ATC_ENABLE__SHIFT 0x1f 8829 #define MMVM_PCIE_ATS_CNTL_VF_25__ATC_ENABLE_MASK 0x80000000L 8830 //MMVM_PCIE_ATS_CNTL_VF_26 8831 #define MMVM_PCIE_ATS_CNTL_VF_26__ATC_ENABLE__SHIFT 0x1f 8832 #define MMVM_PCIE_ATS_CNTL_VF_26__ATC_ENABLE_MASK 0x80000000L 8833 //MMVM_PCIE_ATS_CNTL_VF_27 8834 #define MMVM_PCIE_ATS_CNTL_VF_27__ATC_ENABLE__SHIFT 0x1f 8835 #define MMVM_PCIE_ATS_CNTL_VF_27__ATC_ENABLE_MASK 0x80000000L 8836 //MMVM_PCIE_ATS_CNTL_VF_28 8837 #define MMVM_PCIE_ATS_CNTL_VF_28__ATC_ENABLE__SHIFT 0x1f 8838 #define MMVM_PCIE_ATS_CNTL_VF_28__ATC_ENABLE_MASK 0x80000000L 8839 //MMVM_PCIE_ATS_CNTL_VF_29 8840 #define MMVM_PCIE_ATS_CNTL_VF_29__ATC_ENABLE__SHIFT 0x1f 8841 #define MMVM_PCIE_ATS_CNTL_VF_29__ATC_ENABLE_MASK 0x80000000L 8842 //MMVM_PCIE_ATS_CNTL_VF_30 8843 #define MMVM_PCIE_ATS_CNTL_VF_30__ATC_ENABLE__SHIFT 0x1f 8844 #define MMVM_PCIE_ATS_CNTL_VF_30__ATC_ENABLE_MASK 0x80000000L 8845 //MMVM_PCIE_ATS_CNTL_VF_31 8846 #define MMVM_PCIE_ATS_CNTL_VF_31__ATC_ENABLE__SHIFT 0x1f 8847 #define MMVM_PCIE_ATS_CNTL_VF_31__ATC_ENABLE_MASK 0x80000000L 8848 8849 8850 // addressBlock: mmhub_mmutcl2_mmvmsharedpfdec 8851 //MMMC_VM_NB_MMIOBASE 8852 #define MMMC_VM_NB_MMIOBASE__MMIOBASE__SHIFT 0x0 8853 #define MMMC_VM_NB_MMIOBASE__MMIOBASE_MASK 0xFFFFFFFFL 8854 //MMMC_VM_NB_MMIOLIMIT 8855 #define MMMC_VM_NB_MMIOLIMIT__MMIOLIMIT__SHIFT 0x0 8856 #define MMMC_VM_NB_MMIOLIMIT__MMIOLIMIT_MASK 0xFFFFFFFFL 8857 //MMMC_VM_NB_PCI_CTRL 8858 #define MMMC_VM_NB_PCI_CTRL__MMIOENABLE__SHIFT 0x17 8859 #define MMMC_VM_NB_PCI_CTRL__MMIOENABLE_MASK 0x00800000L 8860 //MMMC_VM_NB_PCI_ARB 8861 #define MMMC_VM_NB_PCI_ARB__VGA_HOLE__SHIFT 0x3 8862 #define MMMC_VM_NB_PCI_ARB__VGA_HOLE_MASK 0x00000008L 8863 //MMMC_VM_NB_TOP_OF_DRAM_SLOT1 8864 #define MMMC_VM_NB_TOP_OF_DRAM_SLOT1__TOP_OF_DRAM__SHIFT 0x17 8865 #define MMMC_VM_NB_TOP_OF_DRAM_SLOT1__TOP_OF_DRAM_MASK 0xFF800000L 8866 //MMMC_VM_NB_LOWER_TOP_OF_DRAM2 8867 #define MMMC_VM_NB_LOWER_TOP_OF_DRAM2__ENABLE__SHIFT 0x0 8868 #define MMMC_VM_NB_LOWER_TOP_OF_DRAM2__LOWER_TOM2__SHIFT 0x17 8869 #define MMMC_VM_NB_LOWER_TOP_OF_DRAM2__ENABLE_MASK 0x00000001L 8870 #define MMMC_VM_NB_LOWER_TOP_OF_DRAM2__LOWER_TOM2_MASK 0xFF800000L 8871 //MMMC_VM_NB_UPPER_TOP_OF_DRAM2 8872 #define MMMC_VM_NB_UPPER_TOP_OF_DRAM2__UPPER_TOM2__SHIFT 0x0 8873 #define MMMC_VM_NB_UPPER_TOP_OF_DRAM2__UPPER_TOM2_MASK 0x00000FFFL 8874 //MMMC_VM_FB_OFFSET 8875 #define MMMC_VM_FB_OFFSET__FB_OFFSET__SHIFT 0x0 8876 #define MMMC_VM_FB_OFFSET__FB_OFFSET_MASK 0x00FFFFFFL 8877 //MMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB 8878 #define MMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB__PHYSICAL_PAGE_NUMBER_LSB__SHIFT 0x0 8879 #define MMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB__PHYSICAL_PAGE_NUMBER_LSB_MASK 0xFFFFFFFFL 8880 //MMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB 8881 #define MMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__PHYSICAL_PAGE_NUMBER_MSB__SHIFT 0x0 8882 #define MMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__PHYSICAL_PAGE_NUMBER_MSB_MASK 0x0000000FL 8883 //MMMC_VM_STEERING 8884 #define MMMC_VM_STEERING__DEFAULT_STEERING__SHIFT 0x0 8885 #define MMMC_VM_STEERING__DEFAULT_STEERING_MASK 0x00000003L 8886 //MMMC_SHARED_VIRT_RESET_REQ 8887 #define MMMC_SHARED_VIRT_RESET_REQ__VF__SHIFT 0x0 8888 #define MMMC_SHARED_VIRT_RESET_REQ__PF__SHIFT 0x1f 8889 #define MMMC_SHARED_VIRT_RESET_REQ__VF_MASK 0x7FFFFFFFL 8890 #define MMMC_SHARED_VIRT_RESET_REQ__PF_MASK 0x80000000L 8891 //MMMC_MEM_POWER_LS 8892 #define MMMC_MEM_POWER_LS__LS_SETUP__SHIFT 0x0 8893 #define MMMC_MEM_POWER_LS__LS_HOLD__SHIFT 0x6 8894 #define MMMC_MEM_POWER_LS__LS_SETUP_MASK 0x0000003FL 8895 #define MMMC_MEM_POWER_LS__LS_HOLD_MASK 0x00000FC0L 8896 //MMMC_VM_CACHEABLE_DRAM_ADDRESS_START 8897 #define MMMC_VM_CACHEABLE_DRAM_ADDRESS_START__ADDRESS__SHIFT 0x0 8898 #define MMMC_VM_CACHEABLE_DRAM_ADDRESS_START__ADDRESS_MASK 0x000FFFFFL 8899 //MMMC_VM_CACHEABLE_DRAM_ADDRESS_END 8900 #define MMMC_VM_CACHEABLE_DRAM_ADDRESS_END__ADDRESS__SHIFT 0x0 8901 #define MMMC_VM_CACHEABLE_DRAM_ADDRESS_END__ADDRESS_MASK 0x000FFFFFL 8902 //MMMC_VM_APT_CNTL 8903 #define MMMC_VM_APT_CNTL__FORCE_MTYPE_UC__SHIFT 0x0 8904 #define MMMC_VM_APT_CNTL__DIRECT_SYSTEM_EN__SHIFT 0x1 8905 #define MMMC_VM_APT_CNTL__FRAG_APT_INTXN_MODE__SHIFT 0x2 8906 #define MMMC_VM_APT_CNTL__FORCE_MTYPE_UC_MASK 0x00000001L 8907 #define MMMC_VM_APT_CNTL__DIRECT_SYSTEM_EN_MASK 0x00000002L 8908 #define MMMC_VM_APT_CNTL__FRAG_APT_INTXN_MODE_MASK 0x0000000CL 8909 //MMMC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL 8910 #define MMMC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL__LOCK__SHIFT 0x0 8911 #define MMMC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL__LOCK_MASK 0x00000001L 8912 //MMMC_VM_LOCAL_HBM_ADDRESS_START 8913 #define MMMC_VM_LOCAL_HBM_ADDRESS_START__ADDRESS__SHIFT 0x0 8914 #define MMMC_VM_LOCAL_HBM_ADDRESS_START__ADDRESS_MASK 0x000FFFFFL 8915 //MMMC_VM_LOCAL_HBM_ADDRESS_END 8916 #define MMMC_VM_LOCAL_HBM_ADDRESS_END__ADDRESS__SHIFT 0x0 8917 #define MMMC_VM_LOCAL_HBM_ADDRESS_END__ADDRESS_MASK 0x000FFFFFL 8918 //MMUTCL2_CGTT_CLK_CTRL 8919 #define MMUTCL2_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 8920 #define MMUTCL2_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 8921 #define MMUTCL2_CGTT_CLK_CTRL__SOFT_OVERRIDE_EXTRA__SHIFT 0xc 8922 #define MMUTCL2_CGTT_CLK_CTRL__MGLS_OVERRIDE__SHIFT 0xf 8923 #define MMUTCL2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x10 8924 #define MMUTCL2_CGTT_CLK_CTRL__SOFT_OVERRIDE__SHIFT 0x18 8925 #define MMUTCL2_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL 8926 #define MMUTCL2_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L 8927 #define MMUTCL2_CGTT_CLK_CTRL__SOFT_OVERRIDE_EXTRA_MASK 0x00007000L 8928 #define MMUTCL2_CGTT_CLK_CTRL__MGLS_OVERRIDE_MASK 0x00008000L 8929 #define MMUTCL2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00FF0000L 8930 #define MMUTCL2_CGTT_CLK_CTRL__SOFT_OVERRIDE_MASK 0xFF000000L 8931 //MMMC_SHARED_ACTIVE_FCN_ID 8932 #define MMMC_SHARED_ACTIVE_FCN_ID__VFID__SHIFT 0x0 8933 #define MMMC_SHARED_ACTIVE_FCN_ID__VF__SHIFT 0x1f 8934 #define MMMC_SHARED_ACTIVE_FCN_ID__VFID_MASK 0x0000001FL 8935 #define MMMC_SHARED_ACTIVE_FCN_ID__VF_MASK 0x80000000L 8936 //MMMC_SHARED_VIRT_RESET_REQ2 8937 #define MMMC_SHARED_VIRT_RESET_REQ2__VF__SHIFT 0x0 8938 #define MMMC_SHARED_VIRT_RESET_REQ2__VF_MASK 0x00000001L 8939 //MMUTCL2_CGTT_BUSY_CTRL 8940 #define MMUTCL2_CGTT_BUSY_CTRL__READ_DELAY__SHIFT 0x0 8941 #define MMUTCL2_CGTT_BUSY_CTRL__ALWAYS_BUSY__SHIFT 0x4 8942 #define MMUTCL2_CGTT_BUSY_CTRL__READ_DELAY_MASK 0x0000000FL 8943 #define MMUTCL2_CGTT_BUSY_CTRL__ALWAYS_BUSY_MASK 0x00000010L 8944 //MMUTCL2_HARVEST_BYPASS_GROUPS 8945 #define MMUTCL2_HARVEST_BYPASS_GROUPS__BYPASS_GROUPS__SHIFT 0x0 8946 #define MMUTCL2_HARVEST_BYPASS_GROUPS__BYPASS_GROUPS_MASK 0xFFFFFFFFL 8947 8948 8949 // addressBlock: mmhub_mmutcl2_mmvmsharedvcdec 8950 //MMMC_VM_FB_LOCATION_BASE 8951 #define MMMC_VM_FB_LOCATION_BASE__FB_BASE__SHIFT 0x0 8952 #define MMMC_VM_FB_LOCATION_BASE__FB_BASE_MASK 0x00FFFFFFL 8953 //MMMC_VM_FB_LOCATION_TOP 8954 #define MMMC_VM_FB_LOCATION_TOP__FB_TOP__SHIFT 0x0 8955 #define MMMC_VM_FB_LOCATION_TOP__FB_TOP_MASK 0x00FFFFFFL 8956 //MMMC_VM_AGP_TOP 8957 #define MMMC_VM_AGP_TOP__AGP_TOP__SHIFT 0x0 8958 #define MMMC_VM_AGP_TOP__AGP_TOP_MASK 0x00FFFFFFL 8959 //MMMC_VM_AGP_BOT 8960 #define MMMC_VM_AGP_BOT__AGP_BOT__SHIFT 0x0 8961 #define MMMC_VM_AGP_BOT__AGP_BOT_MASK 0x00FFFFFFL 8962 //MMMC_VM_AGP_BASE 8963 #define MMMC_VM_AGP_BASE__AGP_BASE__SHIFT 0x0 8964 #define MMMC_VM_AGP_BASE__AGP_BASE_MASK 0x00FFFFFFL 8965 //MMMC_VM_SYSTEM_APERTURE_LOW_ADDR 8966 #define MMMC_VM_SYSTEM_APERTURE_LOW_ADDR__LOGICAL_ADDR__SHIFT 0x0 8967 #define MMMC_VM_SYSTEM_APERTURE_LOW_ADDR__LOGICAL_ADDR_MASK 0x3FFFFFFFL 8968 //MMMC_VM_SYSTEM_APERTURE_HIGH_ADDR 8969 #define MMMC_VM_SYSTEM_APERTURE_HIGH_ADDR__LOGICAL_ADDR__SHIFT 0x0 8970 #define MMMC_VM_SYSTEM_APERTURE_HIGH_ADDR__LOGICAL_ADDR_MASK 0x3FFFFFFFL 8971 //MMMC_VM_MX_L1_TLB_CNTL 8972 #define MMMC_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB__SHIFT 0x0 8973 #define MMMC_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE__SHIFT 0x3 8974 #define MMMC_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS__SHIFT 0x5 8975 #define MMMC_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL__SHIFT 0x6 8976 #define MMMC_VM_MX_L1_TLB_CNTL__ECO_BITS__SHIFT 0x7 8977 #define MMMC_VM_MX_L1_TLB_CNTL__MTYPE__SHIFT 0xb 8978 #define MMMC_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB_MASK 0x00000001L 8979 #define MMMC_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE_MASK 0x00000018L 8980 #define MMMC_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS_MASK 0x00000020L 8981 #define MMMC_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL_MASK 0x00000040L 8982 #define MMMC_VM_MX_L1_TLB_CNTL__ECO_BITS_MASK 0x00000780L 8983 #define MMMC_VM_MX_L1_TLB_CNTL__MTYPE_MASK 0x00003800L 8984 8985 8986 // addressBlock: mmhub_mmutcl2_mmatcl2pfcntrdec 8987 //MM_ATC_L2_PERFCOUNTER_LO 8988 #define MM_ATC_L2_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 8989 #define MM_ATC_L2_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL 8990 //MM_ATC_L2_PERFCOUNTER_HI 8991 #define MM_ATC_L2_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 8992 #define MM_ATC_L2_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 8993 #define MM_ATC_L2_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL 8994 #define MM_ATC_L2_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L 8995 8996 8997 // addressBlock: mmhub_mmutcl2_mmatcl2pfcntldec 8998 //MM_ATC_L2_PERFCOUNTER0_CFG 8999 #define MM_ATC_L2_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 9000 #define MM_ATC_L2_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 9001 #define MM_ATC_L2_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 9002 #define MM_ATC_L2_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c 9003 #define MM_ATC_L2_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d 9004 #define MM_ATC_L2_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL 9005 #define MM_ATC_L2_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L 9006 #define MM_ATC_L2_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L 9007 #define MM_ATC_L2_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L 9008 #define MM_ATC_L2_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L 9009 //MM_ATC_L2_PERFCOUNTER1_CFG 9010 #define MM_ATC_L2_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 9011 #define MM_ATC_L2_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 9012 #define MM_ATC_L2_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 9013 #define MM_ATC_L2_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c 9014 #define MM_ATC_L2_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d 9015 #define MM_ATC_L2_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL 9016 #define MM_ATC_L2_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L 9017 #define MM_ATC_L2_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L 9018 #define MM_ATC_L2_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L 9019 #define MM_ATC_L2_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L 9020 //MM_ATC_L2_PERFCOUNTER_RSLT_CNTL 9021 #define MM_ATC_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 9022 #define MM_ATC_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 9023 #define MM_ATC_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 9024 #define MM_ATC_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 9025 #define MM_ATC_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 9026 #define MM_ATC_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a 9027 #define MM_ATC_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL 9028 #define MM_ATC_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L 9029 #define MM_ATC_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L 9030 #define MM_ATC_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L 9031 #define MM_ATC_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L 9032 #define MM_ATC_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L 9033 9034 9035 // addressBlock: mmhub_mmutcl2_mmvml2ptdec 9036 //MMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32 9037 #define MMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 9038 #define MMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL 9039 //MMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32 9040 #define MMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 9041 #define MMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL 9042 //MMVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32 9043 #define MMVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 9044 #define MMVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 9045 //MMVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32 9046 #define MMVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 9047 #define MMVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 9048 //MMVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32 9049 #define MMVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 9050 #define MMVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 9051 //MMVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32 9052 #define MMVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 9053 #define MMVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 9054 //MMVM_CONTEXT0_PAGE_TABLE_RESERVE0 9055 #define MMVM_CONTEXT0_PAGE_TABLE_RESERVE0__DUMMY__SHIFT 0x0 9056 #define MMVM_CONTEXT0_PAGE_TABLE_RESERVE0__DUMMY_MASK 0xFFFFFFFFL 9057 //MMVM_CONTEXT0_PAGE_TABLE_RESERVE1 9058 #define MMVM_CONTEXT0_PAGE_TABLE_RESERVE1__DUMMY__SHIFT 0x0 9059 #define MMVM_CONTEXT0_PAGE_TABLE_RESERVE1__DUMMY_MASK 0xFFFFFFFFL 9060 //MMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32 9061 #define MMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 9062 #define MMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL 9063 //MMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32 9064 #define MMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 9065 #define MMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL 9066 //MMVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32 9067 #define MMVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 9068 #define MMVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 9069 //MMVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32 9070 #define MMVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 9071 #define MMVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 9072 //MMVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32 9073 #define MMVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 9074 #define MMVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 9075 //MMVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32 9076 #define MMVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 9077 #define MMVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 9078 //MMVM_CONTEXT1_PAGE_TABLE_RESERVE0 9079 #define MMVM_CONTEXT1_PAGE_TABLE_RESERVE0__DUMMY__SHIFT 0x0 9080 #define MMVM_CONTEXT1_PAGE_TABLE_RESERVE0__DUMMY_MASK 0xFFFFFFFFL 9081 //MMVM_CONTEXT1_PAGE_TABLE_RESERVE1 9082 #define MMVM_CONTEXT1_PAGE_TABLE_RESERVE1__DUMMY__SHIFT 0x0 9083 #define MMVM_CONTEXT1_PAGE_TABLE_RESERVE1__DUMMY_MASK 0xFFFFFFFFL 9084 //MMVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32 9085 #define MMVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 9086 #define MMVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL 9087 //MMVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32 9088 #define MMVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 9089 #define MMVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL 9090 //MMVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32 9091 #define MMVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 9092 #define MMVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 9093 //MMVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32 9094 #define MMVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 9095 #define MMVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 9096 //MMVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32 9097 #define MMVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 9098 #define MMVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 9099 //MMVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32 9100 #define MMVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 9101 #define MMVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 9102 //MMVM_CONTEXT2_PAGE_TABLE_RESERVE0 9103 #define MMVM_CONTEXT2_PAGE_TABLE_RESERVE0__DUMMY__SHIFT 0x0 9104 #define MMVM_CONTEXT2_PAGE_TABLE_RESERVE0__DUMMY_MASK 0xFFFFFFFFL 9105 //MMVM_CONTEXT2_PAGE_TABLE_RESERVE1 9106 #define MMVM_CONTEXT2_PAGE_TABLE_RESERVE1__DUMMY__SHIFT 0x0 9107 #define MMVM_CONTEXT2_PAGE_TABLE_RESERVE1__DUMMY_MASK 0xFFFFFFFFL 9108 //MMVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32 9109 #define MMVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 9110 #define MMVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL 9111 //MMVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32 9112 #define MMVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 9113 #define MMVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL 9114 //MMVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32 9115 #define MMVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 9116 #define MMVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 9117 //MMVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32 9118 #define MMVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 9119 #define MMVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 9120 //MMVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32 9121 #define MMVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 9122 #define MMVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 9123 //MMVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32 9124 #define MMVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 9125 #define MMVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 9126 //MMVM_CONTEXT3_PAGE_TABLE_RESERVE0 9127 #define MMVM_CONTEXT3_PAGE_TABLE_RESERVE0__DUMMY__SHIFT 0x0 9128 #define MMVM_CONTEXT3_PAGE_TABLE_RESERVE0__DUMMY_MASK 0xFFFFFFFFL 9129 //MMVM_CONTEXT3_PAGE_TABLE_RESERVE1 9130 #define MMVM_CONTEXT3_PAGE_TABLE_RESERVE1__DUMMY__SHIFT 0x0 9131 #define MMVM_CONTEXT3_PAGE_TABLE_RESERVE1__DUMMY_MASK 0xFFFFFFFFL 9132 //MMVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32 9133 #define MMVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 9134 #define MMVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL 9135 //MMVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32 9136 #define MMVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 9137 #define MMVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL 9138 //MMVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32 9139 #define MMVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 9140 #define MMVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 9141 //MMVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32 9142 #define MMVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 9143 #define MMVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 9144 //MMVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32 9145 #define MMVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 9146 #define MMVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 9147 //MMVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32 9148 #define MMVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 9149 #define MMVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 9150 //MMVM_CONTEXT4_PAGE_TABLE_RESERVE0 9151 #define MMVM_CONTEXT4_PAGE_TABLE_RESERVE0__DUMMY__SHIFT 0x0 9152 #define MMVM_CONTEXT4_PAGE_TABLE_RESERVE0__DUMMY_MASK 0xFFFFFFFFL 9153 //MMVM_CONTEXT4_PAGE_TABLE_RESERVE1 9154 #define MMVM_CONTEXT4_PAGE_TABLE_RESERVE1__DUMMY__SHIFT 0x0 9155 #define MMVM_CONTEXT4_PAGE_TABLE_RESERVE1__DUMMY_MASK 0xFFFFFFFFL 9156 //MMVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32 9157 #define MMVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 9158 #define MMVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL 9159 //MMVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32 9160 #define MMVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 9161 #define MMVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL 9162 //MMVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32 9163 #define MMVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 9164 #define MMVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 9165 //MMVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32 9166 #define MMVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 9167 #define MMVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 9168 //MMVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32 9169 #define MMVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 9170 #define MMVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 9171 //MMVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32 9172 #define MMVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 9173 #define MMVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 9174 //MMVM_CONTEXT5_PAGE_TABLE_RESERVE0 9175 #define MMVM_CONTEXT5_PAGE_TABLE_RESERVE0__DUMMY__SHIFT 0x0 9176 #define MMVM_CONTEXT5_PAGE_TABLE_RESERVE0__DUMMY_MASK 0xFFFFFFFFL 9177 //MMVM_CONTEXT5_PAGE_TABLE_RESERVE1 9178 #define MMVM_CONTEXT5_PAGE_TABLE_RESERVE1__DUMMY__SHIFT 0x0 9179 #define MMVM_CONTEXT5_PAGE_TABLE_RESERVE1__DUMMY_MASK 0xFFFFFFFFL 9180 //MMVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32 9181 #define MMVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 9182 #define MMVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL 9183 //MMVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32 9184 #define MMVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 9185 #define MMVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL 9186 //MMVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32 9187 #define MMVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 9188 #define MMVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 9189 //MMVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32 9190 #define MMVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 9191 #define MMVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 9192 //MMVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32 9193 #define MMVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 9194 #define MMVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 9195 //MMVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32 9196 #define MMVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 9197 #define MMVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 9198 //MMVM_CONTEXT6_PAGE_TABLE_RESERVE0 9199 #define MMVM_CONTEXT6_PAGE_TABLE_RESERVE0__DUMMY__SHIFT 0x0 9200 #define MMVM_CONTEXT6_PAGE_TABLE_RESERVE0__DUMMY_MASK 0xFFFFFFFFL 9201 //MMVM_CONTEXT6_PAGE_TABLE_RESERVE1 9202 #define MMVM_CONTEXT6_PAGE_TABLE_RESERVE1__DUMMY__SHIFT 0x0 9203 #define MMVM_CONTEXT6_PAGE_TABLE_RESERVE1__DUMMY_MASK 0xFFFFFFFFL 9204 //MMVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32 9205 #define MMVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 9206 #define MMVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL 9207 //MMVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32 9208 #define MMVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 9209 #define MMVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL 9210 //MMVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32 9211 #define MMVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 9212 #define MMVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 9213 //MMVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32 9214 #define MMVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 9215 #define MMVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 9216 //MMVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32 9217 #define MMVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 9218 #define MMVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 9219 //MMVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32 9220 #define MMVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 9221 #define MMVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 9222 //MMVM_CONTEXT7_PAGE_TABLE_RESERVE0 9223 #define MMVM_CONTEXT7_PAGE_TABLE_RESERVE0__DUMMY__SHIFT 0x0 9224 #define MMVM_CONTEXT7_PAGE_TABLE_RESERVE0__DUMMY_MASK 0xFFFFFFFFL 9225 //MMVM_CONTEXT7_PAGE_TABLE_RESERVE1 9226 #define MMVM_CONTEXT7_PAGE_TABLE_RESERVE1__DUMMY__SHIFT 0x0 9227 #define MMVM_CONTEXT7_PAGE_TABLE_RESERVE1__DUMMY_MASK 0xFFFFFFFFL 9228 //MMVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32 9229 #define MMVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 9230 #define MMVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL 9231 //MMVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32 9232 #define MMVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 9233 #define MMVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL 9234 //MMVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32 9235 #define MMVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 9236 #define MMVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 9237 //MMVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32 9238 #define MMVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 9239 #define MMVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 9240 //MMVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32 9241 #define MMVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 9242 #define MMVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 9243 //MMVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32 9244 #define MMVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 9245 #define MMVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 9246 //MMVM_CONTEXT8_PAGE_TABLE_RESERVE0 9247 #define MMVM_CONTEXT8_PAGE_TABLE_RESERVE0__DUMMY__SHIFT 0x0 9248 #define MMVM_CONTEXT8_PAGE_TABLE_RESERVE0__DUMMY_MASK 0xFFFFFFFFL 9249 //MMVM_CONTEXT8_PAGE_TABLE_RESERVE1 9250 #define MMVM_CONTEXT8_PAGE_TABLE_RESERVE1__DUMMY__SHIFT 0x0 9251 #define MMVM_CONTEXT8_PAGE_TABLE_RESERVE1__DUMMY_MASK 0xFFFFFFFFL 9252 //MMVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32 9253 #define MMVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 9254 #define MMVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL 9255 //MMVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32 9256 #define MMVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 9257 #define MMVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL 9258 //MMVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32 9259 #define MMVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 9260 #define MMVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 9261 //MMVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32 9262 #define MMVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 9263 #define MMVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 9264 //MMVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32 9265 #define MMVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 9266 #define MMVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 9267 //MMVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32 9268 #define MMVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 9269 #define MMVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 9270 //MMVM_CONTEXT9_PAGE_TABLE_RESERVE0 9271 #define MMVM_CONTEXT9_PAGE_TABLE_RESERVE0__DUMMY__SHIFT 0x0 9272 #define MMVM_CONTEXT9_PAGE_TABLE_RESERVE0__DUMMY_MASK 0xFFFFFFFFL 9273 //MMVM_CONTEXT9_PAGE_TABLE_RESERVE1 9274 #define MMVM_CONTEXT9_PAGE_TABLE_RESERVE1__DUMMY__SHIFT 0x0 9275 #define MMVM_CONTEXT9_PAGE_TABLE_RESERVE1__DUMMY_MASK 0xFFFFFFFFL 9276 //MMVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32 9277 #define MMVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 9278 #define MMVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL 9279 //MMVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32 9280 #define MMVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 9281 #define MMVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL 9282 //MMVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32 9283 #define MMVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 9284 #define MMVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 9285 //MMVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32 9286 #define MMVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 9287 #define MMVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 9288 //MMVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32 9289 #define MMVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 9290 #define MMVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 9291 //MMVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32 9292 #define MMVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 9293 #define MMVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 9294 //MMVM_CONTEXT10_PAGE_TABLE_RESERVE0 9295 #define MMVM_CONTEXT10_PAGE_TABLE_RESERVE0__DUMMY__SHIFT 0x0 9296 #define MMVM_CONTEXT10_PAGE_TABLE_RESERVE0__DUMMY_MASK 0xFFFFFFFFL 9297 //MMVM_CONTEXT10_PAGE_TABLE_RESERVE1 9298 #define MMVM_CONTEXT10_PAGE_TABLE_RESERVE1__DUMMY__SHIFT 0x0 9299 #define MMVM_CONTEXT10_PAGE_TABLE_RESERVE1__DUMMY_MASK 0xFFFFFFFFL 9300 //MMVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32 9301 #define MMVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 9302 #define MMVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL 9303 //MMVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32 9304 #define MMVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 9305 #define MMVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL 9306 //MMVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32 9307 #define MMVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 9308 #define MMVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 9309 //MMVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32 9310 #define MMVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 9311 #define MMVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 9312 //MMVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32 9313 #define MMVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 9314 #define MMVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 9315 //MMVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32 9316 #define MMVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 9317 #define MMVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 9318 //MMVM_CONTEXT11_PAGE_TABLE_RESERVE0 9319 #define MMVM_CONTEXT11_PAGE_TABLE_RESERVE0__DUMMY__SHIFT 0x0 9320 #define MMVM_CONTEXT11_PAGE_TABLE_RESERVE0__DUMMY_MASK 0xFFFFFFFFL 9321 //MMVM_CONTEXT11_PAGE_TABLE_RESERVE1 9322 #define MMVM_CONTEXT11_PAGE_TABLE_RESERVE1__DUMMY__SHIFT 0x0 9323 #define MMVM_CONTEXT11_PAGE_TABLE_RESERVE1__DUMMY_MASK 0xFFFFFFFFL 9324 //MMVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32 9325 #define MMVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 9326 #define MMVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL 9327 //MMVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32 9328 #define MMVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 9329 #define MMVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL 9330 //MMVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32 9331 #define MMVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 9332 #define MMVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 9333 //MMVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32 9334 #define MMVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 9335 #define MMVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 9336 //MMVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32 9337 #define MMVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 9338 #define MMVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 9339 //MMVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32 9340 #define MMVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 9341 #define MMVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 9342 //MMVM_CONTEXT12_PAGE_TABLE_RESERVE0 9343 #define MMVM_CONTEXT12_PAGE_TABLE_RESERVE0__DUMMY__SHIFT 0x0 9344 #define MMVM_CONTEXT12_PAGE_TABLE_RESERVE0__DUMMY_MASK 0xFFFFFFFFL 9345 //MMVM_CONTEXT12_PAGE_TABLE_RESERVE1 9346 #define MMVM_CONTEXT12_PAGE_TABLE_RESERVE1__DUMMY__SHIFT 0x0 9347 #define MMVM_CONTEXT12_PAGE_TABLE_RESERVE1__DUMMY_MASK 0xFFFFFFFFL 9348 //MMVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32 9349 #define MMVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 9350 #define MMVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL 9351 //MMVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32 9352 #define MMVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 9353 #define MMVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL 9354 //MMVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32 9355 #define MMVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 9356 #define MMVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 9357 //MMVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32 9358 #define MMVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 9359 #define MMVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 9360 //MMVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32 9361 #define MMVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 9362 #define MMVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 9363 //MMVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32 9364 #define MMVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 9365 #define MMVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 9366 //MMVM_CONTEXT13_PAGE_TABLE_RESERVE0 9367 #define MMVM_CONTEXT13_PAGE_TABLE_RESERVE0__DUMMY__SHIFT 0x0 9368 #define MMVM_CONTEXT13_PAGE_TABLE_RESERVE0__DUMMY_MASK 0xFFFFFFFFL 9369 //MMVM_CONTEXT13_PAGE_TABLE_RESERVE1 9370 #define MMVM_CONTEXT13_PAGE_TABLE_RESERVE1__DUMMY__SHIFT 0x0 9371 #define MMVM_CONTEXT13_PAGE_TABLE_RESERVE1__DUMMY_MASK 0xFFFFFFFFL 9372 //MMVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32 9373 #define MMVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 9374 #define MMVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL 9375 //MMVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32 9376 #define MMVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 9377 #define MMVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL 9378 //MMVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32 9379 #define MMVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 9380 #define MMVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 9381 //MMVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32 9382 #define MMVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 9383 #define MMVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 9384 //MMVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32 9385 #define MMVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 9386 #define MMVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 9387 //MMVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32 9388 #define MMVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 9389 #define MMVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 9390 //MMVM_CONTEXT14_PAGE_TABLE_RESERVE0 9391 #define MMVM_CONTEXT14_PAGE_TABLE_RESERVE0__DUMMY__SHIFT 0x0 9392 #define MMVM_CONTEXT14_PAGE_TABLE_RESERVE0__DUMMY_MASK 0xFFFFFFFFL 9393 //MMVM_CONTEXT14_PAGE_TABLE_RESERVE1 9394 #define MMVM_CONTEXT14_PAGE_TABLE_RESERVE1__DUMMY__SHIFT 0x0 9395 #define MMVM_CONTEXT14_PAGE_TABLE_RESERVE1__DUMMY_MASK 0xFFFFFFFFL 9396 //MMVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32 9397 #define MMVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 9398 #define MMVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL 9399 //MMVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32 9400 #define MMVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 9401 #define MMVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL 9402 //MMVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32 9403 #define MMVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 9404 #define MMVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 9405 //MMVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32 9406 #define MMVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 9407 #define MMVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 9408 //MMVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32 9409 #define MMVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 9410 #define MMVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 9411 //MMVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32 9412 #define MMVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 9413 #define MMVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 9414 //MMVM_CONTEXT15_PAGE_TABLE_RESERVE0 9415 #define MMVM_CONTEXT15_PAGE_TABLE_RESERVE0__DUMMY__SHIFT 0x0 9416 #define MMVM_CONTEXT15_PAGE_TABLE_RESERVE0__DUMMY_MASK 0xFFFFFFFFL 9417 //MMVM_CONTEXT15_PAGE_TABLE_RESERVE1 9418 #define MMVM_CONTEXT15_PAGE_TABLE_RESERVE1__DUMMY__SHIFT 0x0 9419 #define MMVM_CONTEXT15_PAGE_TABLE_RESERVE1__DUMMY_MASK 0xFFFFFFFFL 9420 9421 9422 // addressBlock: mmhub_mmutcl2_mmvml2indec 9423 //MMVM_INVALIDATE_ENG0_SEM 9424 #define MMVM_INVALIDATE_ENG0_SEM__SEMAPHORE__SHIFT 0x0 9425 #define MMVM_INVALIDATE_ENG0_SEM__SEMAPHORE_MASK 0x00000001L 9426 //MMVM_INVALIDATE_ENG0_REQ 9427 #define MMVM_INVALIDATE_ENG0_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 9428 #define MMVM_INVALIDATE_ENG0_REQ__FLUSH_TYPE__SHIFT 0x10 9429 #define MMVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 9430 #define MMVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 9431 #define MMVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 9432 #define MMVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 9433 #define MMVM_INVALIDATE_ENG0_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 9434 #define MMVM_INVALIDATE_ENG0_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 9435 #define MMVM_INVALIDATE_ENG0_REQ__LOG_REQUEST__SHIFT 0x19 9436 #define MMVM_INVALIDATE_ENG0_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a 9437 #define MMVM_INVALIDATE_ENG0_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL 9438 #define MMVM_INVALIDATE_ENG0_REQ__FLUSH_TYPE_MASK 0x00070000L 9439 #define MMVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L 9440 #define MMVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L 9441 #define MMVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L 9442 #define MMVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L 9443 #define MMVM_INVALIDATE_ENG0_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L 9444 #define MMVM_INVALIDATE_ENG0_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L 9445 #define MMVM_INVALIDATE_ENG0_REQ__LOG_REQUEST_MASK 0x02000000L 9446 #define MMVM_INVALIDATE_ENG0_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L 9447 //MMVM_INVALIDATE_ENG0_ACK 9448 #define MMVM_INVALIDATE_ENG0_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 9449 #define MMVM_INVALIDATE_ENG0_ACK__SEMAPHORE__SHIFT 0x10 9450 #define MMVM_INVALIDATE_ENG0_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL 9451 #define MMVM_INVALIDATE_ENG0_ACK__SEMAPHORE_MASK 0x00010000L 9452 //MMVM_INVALIDATE_ENG0_ADDR_RANGE_LO32 9453 #define MMVM_INVALIDATE_ENG0_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 9454 #define MMVM_INVALIDATE_ENG0_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 9455 #define MMVM_INVALIDATE_ENG0_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L 9456 #define MMVM_INVALIDATE_ENG0_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL 9457 //MMVM_INVALIDATE_ENG0_ADDR_RANGE_HI32 9458 #define MMVM_INVALIDATE_ENG0_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 9459 #define MMVM_INVALIDATE_ENG0_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL 9460 //MMVM_INVALIDATE_ENG0_RESERVE0 9461 #define MMVM_INVALIDATE_ENG0_RESERVE0__DUMMY__SHIFT 0x0 9462 #define MMVM_INVALIDATE_ENG0_RESERVE0__DUMMY_MASK 0xFFFFFFFFL 9463 //MMVM_INVALIDATE_ENG0_RESERVE1 9464 #define MMVM_INVALIDATE_ENG0_RESERVE1__DUMMY__SHIFT 0x0 9465 #define MMVM_INVALIDATE_ENG0_RESERVE1__DUMMY_MASK 0xFFFFFFFFL 9466 //MMVM_INVALIDATE_ENG0_RESERVE2 9467 #define MMVM_INVALIDATE_ENG0_RESERVE2__DUMMY__SHIFT 0x0 9468 #define MMVM_INVALIDATE_ENG0_RESERVE2__DUMMY_MASK 0xFFFFFFFFL 9469 //MMVM_INVALIDATE_ENG1_SEM 9470 #define MMVM_INVALIDATE_ENG1_SEM__SEMAPHORE__SHIFT 0x0 9471 #define MMVM_INVALIDATE_ENG1_SEM__SEMAPHORE_MASK 0x00000001L 9472 //MMVM_INVALIDATE_ENG1_REQ 9473 #define MMVM_INVALIDATE_ENG1_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 9474 #define MMVM_INVALIDATE_ENG1_REQ__FLUSH_TYPE__SHIFT 0x10 9475 #define MMVM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 9476 #define MMVM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 9477 #define MMVM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 9478 #define MMVM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 9479 #define MMVM_INVALIDATE_ENG1_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 9480 #define MMVM_INVALIDATE_ENG1_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 9481 #define MMVM_INVALIDATE_ENG1_REQ__LOG_REQUEST__SHIFT 0x19 9482 #define MMVM_INVALIDATE_ENG1_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a 9483 #define MMVM_INVALIDATE_ENG1_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL 9484 #define MMVM_INVALIDATE_ENG1_REQ__FLUSH_TYPE_MASK 0x00070000L 9485 #define MMVM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L 9486 #define MMVM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L 9487 #define MMVM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L 9488 #define MMVM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L 9489 #define MMVM_INVALIDATE_ENG1_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L 9490 #define MMVM_INVALIDATE_ENG1_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L 9491 #define MMVM_INVALIDATE_ENG1_REQ__LOG_REQUEST_MASK 0x02000000L 9492 #define MMVM_INVALIDATE_ENG1_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L 9493 //MMVM_INVALIDATE_ENG1_ACK 9494 #define MMVM_INVALIDATE_ENG1_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 9495 #define MMVM_INVALIDATE_ENG1_ACK__SEMAPHORE__SHIFT 0x10 9496 #define MMVM_INVALIDATE_ENG1_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL 9497 #define MMVM_INVALIDATE_ENG1_ACK__SEMAPHORE_MASK 0x00010000L 9498 //MMVM_INVALIDATE_ENG1_ADDR_RANGE_LO32 9499 #define MMVM_INVALIDATE_ENG1_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 9500 #define MMVM_INVALIDATE_ENG1_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 9501 #define MMVM_INVALIDATE_ENG1_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L 9502 #define MMVM_INVALIDATE_ENG1_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL 9503 //MMVM_INVALIDATE_ENG1_ADDR_RANGE_HI32 9504 #define MMVM_INVALIDATE_ENG1_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 9505 #define MMVM_INVALIDATE_ENG1_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL 9506 //MMVM_INVALIDATE_ENG1_RESERVE0 9507 #define MMVM_INVALIDATE_ENG1_RESERVE0__DUMMY__SHIFT 0x0 9508 #define MMVM_INVALIDATE_ENG1_RESERVE0__DUMMY_MASK 0xFFFFFFFFL 9509 //MMVM_INVALIDATE_ENG1_RESERVE1 9510 #define MMVM_INVALIDATE_ENG1_RESERVE1__DUMMY__SHIFT 0x0 9511 #define MMVM_INVALIDATE_ENG1_RESERVE1__DUMMY_MASK 0xFFFFFFFFL 9512 //MMVM_INVALIDATE_ENG1_RESERVE2 9513 #define MMVM_INVALIDATE_ENG1_RESERVE2__DUMMY__SHIFT 0x0 9514 #define MMVM_INVALIDATE_ENG1_RESERVE2__DUMMY_MASK 0xFFFFFFFFL 9515 //MMVM_INVALIDATE_ENG2_SEM 9516 #define MMVM_INVALIDATE_ENG2_SEM__SEMAPHORE__SHIFT 0x0 9517 #define MMVM_INVALIDATE_ENG2_SEM__SEMAPHORE_MASK 0x00000001L 9518 //MMVM_INVALIDATE_ENG2_REQ 9519 #define MMVM_INVALIDATE_ENG2_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 9520 #define MMVM_INVALIDATE_ENG2_REQ__FLUSH_TYPE__SHIFT 0x10 9521 #define MMVM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 9522 #define MMVM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 9523 #define MMVM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 9524 #define MMVM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 9525 #define MMVM_INVALIDATE_ENG2_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 9526 #define MMVM_INVALIDATE_ENG2_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 9527 #define MMVM_INVALIDATE_ENG2_REQ__LOG_REQUEST__SHIFT 0x19 9528 #define MMVM_INVALIDATE_ENG2_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a 9529 #define MMVM_INVALIDATE_ENG2_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL 9530 #define MMVM_INVALIDATE_ENG2_REQ__FLUSH_TYPE_MASK 0x00070000L 9531 #define MMVM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L 9532 #define MMVM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L 9533 #define MMVM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L 9534 #define MMVM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L 9535 #define MMVM_INVALIDATE_ENG2_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L 9536 #define MMVM_INVALIDATE_ENG2_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L 9537 #define MMVM_INVALIDATE_ENG2_REQ__LOG_REQUEST_MASK 0x02000000L 9538 #define MMVM_INVALIDATE_ENG2_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L 9539 //MMVM_INVALIDATE_ENG2_ACK 9540 #define MMVM_INVALIDATE_ENG2_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 9541 #define MMVM_INVALIDATE_ENG2_ACK__SEMAPHORE__SHIFT 0x10 9542 #define MMVM_INVALIDATE_ENG2_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL 9543 #define MMVM_INVALIDATE_ENG2_ACK__SEMAPHORE_MASK 0x00010000L 9544 //MMVM_INVALIDATE_ENG2_ADDR_RANGE_LO32 9545 #define MMVM_INVALIDATE_ENG2_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 9546 #define MMVM_INVALIDATE_ENG2_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 9547 #define MMVM_INVALIDATE_ENG2_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L 9548 #define MMVM_INVALIDATE_ENG2_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL 9549 //MMVM_INVALIDATE_ENG2_ADDR_RANGE_HI32 9550 #define MMVM_INVALIDATE_ENG2_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 9551 #define MMVM_INVALIDATE_ENG2_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL 9552 //MMVM_INVALIDATE_ENG2_RESERVE0 9553 #define MMVM_INVALIDATE_ENG2_RESERVE0__DUMMY__SHIFT 0x0 9554 #define MMVM_INVALIDATE_ENG2_RESERVE0__DUMMY_MASK 0xFFFFFFFFL 9555 //MMVM_INVALIDATE_ENG2_RESERVE1 9556 #define MMVM_INVALIDATE_ENG2_RESERVE1__DUMMY__SHIFT 0x0 9557 #define MMVM_INVALIDATE_ENG2_RESERVE1__DUMMY_MASK 0xFFFFFFFFL 9558 //MMVM_INVALIDATE_ENG2_RESERVE2 9559 #define MMVM_INVALIDATE_ENG2_RESERVE2__DUMMY__SHIFT 0x0 9560 #define MMVM_INVALIDATE_ENG2_RESERVE2__DUMMY_MASK 0xFFFFFFFFL 9561 //MMVM_INVALIDATE_ENG3_SEM 9562 #define MMVM_INVALIDATE_ENG3_SEM__SEMAPHORE__SHIFT 0x0 9563 #define MMVM_INVALIDATE_ENG3_SEM__SEMAPHORE_MASK 0x00000001L 9564 //MMVM_INVALIDATE_ENG3_REQ 9565 #define MMVM_INVALIDATE_ENG3_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 9566 #define MMVM_INVALIDATE_ENG3_REQ__FLUSH_TYPE__SHIFT 0x10 9567 #define MMVM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 9568 #define MMVM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 9569 #define MMVM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 9570 #define MMVM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 9571 #define MMVM_INVALIDATE_ENG3_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 9572 #define MMVM_INVALIDATE_ENG3_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 9573 #define MMVM_INVALIDATE_ENG3_REQ__LOG_REQUEST__SHIFT 0x19 9574 #define MMVM_INVALIDATE_ENG3_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a 9575 #define MMVM_INVALIDATE_ENG3_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL 9576 #define MMVM_INVALIDATE_ENG3_REQ__FLUSH_TYPE_MASK 0x00070000L 9577 #define MMVM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L 9578 #define MMVM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L 9579 #define MMVM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L 9580 #define MMVM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L 9581 #define MMVM_INVALIDATE_ENG3_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L 9582 #define MMVM_INVALIDATE_ENG3_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L 9583 #define MMVM_INVALIDATE_ENG3_REQ__LOG_REQUEST_MASK 0x02000000L 9584 #define MMVM_INVALIDATE_ENG3_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L 9585 //MMVM_INVALIDATE_ENG3_ACK 9586 #define MMVM_INVALIDATE_ENG3_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 9587 #define MMVM_INVALIDATE_ENG3_ACK__SEMAPHORE__SHIFT 0x10 9588 #define MMVM_INVALIDATE_ENG3_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL 9589 #define MMVM_INVALIDATE_ENG3_ACK__SEMAPHORE_MASK 0x00010000L 9590 //MMVM_INVALIDATE_ENG3_ADDR_RANGE_LO32 9591 #define MMVM_INVALIDATE_ENG3_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 9592 #define MMVM_INVALIDATE_ENG3_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 9593 #define MMVM_INVALIDATE_ENG3_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L 9594 #define MMVM_INVALIDATE_ENG3_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL 9595 //MMVM_INVALIDATE_ENG3_ADDR_RANGE_HI32 9596 #define MMVM_INVALIDATE_ENG3_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 9597 #define MMVM_INVALIDATE_ENG3_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL 9598 //MMVM_INVALIDATE_ENG3_RESERVE0 9599 #define MMVM_INVALIDATE_ENG3_RESERVE0__DUMMY__SHIFT 0x0 9600 #define MMVM_INVALIDATE_ENG3_RESERVE0__DUMMY_MASK 0xFFFFFFFFL 9601 //MMVM_INVALIDATE_ENG3_RESERVE1 9602 #define MMVM_INVALIDATE_ENG3_RESERVE1__DUMMY__SHIFT 0x0 9603 #define MMVM_INVALIDATE_ENG3_RESERVE1__DUMMY_MASK 0xFFFFFFFFL 9604 //MMVM_INVALIDATE_ENG3_RESERVE2 9605 #define MMVM_INVALIDATE_ENG3_RESERVE2__DUMMY__SHIFT 0x0 9606 #define MMVM_INVALIDATE_ENG3_RESERVE2__DUMMY_MASK 0xFFFFFFFFL 9607 //MMVM_INVALIDATE_ENG4_SEM 9608 #define MMVM_INVALIDATE_ENG4_SEM__SEMAPHORE__SHIFT 0x0 9609 #define MMVM_INVALIDATE_ENG4_SEM__SEMAPHORE_MASK 0x00000001L 9610 //MMVM_INVALIDATE_ENG4_REQ 9611 #define MMVM_INVALIDATE_ENG4_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 9612 #define MMVM_INVALIDATE_ENG4_REQ__FLUSH_TYPE__SHIFT 0x10 9613 #define MMVM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 9614 #define MMVM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 9615 #define MMVM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 9616 #define MMVM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 9617 #define MMVM_INVALIDATE_ENG4_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 9618 #define MMVM_INVALIDATE_ENG4_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 9619 #define MMVM_INVALIDATE_ENG4_REQ__LOG_REQUEST__SHIFT 0x19 9620 #define MMVM_INVALIDATE_ENG4_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a 9621 #define MMVM_INVALIDATE_ENG4_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL 9622 #define MMVM_INVALIDATE_ENG4_REQ__FLUSH_TYPE_MASK 0x00070000L 9623 #define MMVM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L 9624 #define MMVM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L 9625 #define MMVM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L 9626 #define MMVM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L 9627 #define MMVM_INVALIDATE_ENG4_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L 9628 #define MMVM_INVALIDATE_ENG4_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L 9629 #define MMVM_INVALIDATE_ENG4_REQ__LOG_REQUEST_MASK 0x02000000L 9630 #define MMVM_INVALIDATE_ENG4_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L 9631 //MMVM_INVALIDATE_ENG4_ACK 9632 #define MMVM_INVALIDATE_ENG4_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 9633 #define MMVM_INVALIDATE_ENG4_ACK__SEMAPHORE__SHIFT 0x10 9634 #define MMVM_INVALIDATE_ENG4_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL 9635 #define MMVM_INVALIDATE_ENG4_ACK__SEMAPHORE_MASK 0x00010000L 9636 //MMVM_INVALIDATE_ENG4_ADDR_RANGE_LO32 9637 #define MMVM_INVALIDATE_ENG4_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 9638 #define MMVM_INVALIDATE_ENG4_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 9639 #define MMVM_INVALIDATE_ENG4_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L 9640 #define MMVM_INVALIDATE_ENG4_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL 9641 //MMVM_INVALIDATE_ENG4_ADDR_RANGE_HI32 9642 #define MMVM_INVALIDATE_ENG4_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 9643 #define MMVM_INVALIDATE_ENG4_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL 9644 //MMVM_INVALIDATE_ENG4_RESERVE0 9645 #define MMVM_INVALIDATE_ENG4_RESERVE0__DUMMY__SHIFT 0x0 9646 #define MMVM_INVALIDATE_ENG4_RESERVE0__DUMMY_MASK 0xFFFFFFFFL 9647 //MMVM_INVALIDATE_ENG4_RESERVE1 9648 #define MMVM_INVALIDATE_ENG4_RESERVE1__DUMMY__SHIFT 0x0 9649 #define MMVM_INVALIDATE_ENG4_RESERVE1__DUMMY_MASK 0xFFFFFFFFL 9650 //MMVM_INVALIDATE_ENG4_RESERVE2 9651 #define MMVM_INVALIDATE_ENG4_RESERVE2__DUMMY__SHIFT 0x0 9652 #define MMVM_INVALIDATE_ENG4_RESERVE2__DUMMY_MASK 0xFFFFFFFFL 9653 //MMVM_INVALIDATE_ENG5_SEM 9654 #define MMVM_INVALIDATE_ENG5_SEM__SEMAPHORE__SHIFT 0x0 9655 #define MMVM_INVALIDATE_ENG5_SEM__SEMAPHORE_MASK 0x00000001L 9656 //MMVM_INVALIDATE_ENG5_REQ 9657 #define MMVM_INVALIDATE_ENG5_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 9658 #define MMVM_INVALIDATE_ENG5_REQ__FLUSH_TYPE__SHIFT 0x10 9659 #define MMVM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 9660 #define MMVM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 9661 #define MMVM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 9662 #define MMVM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 9663 #define MMVM_INVALIDATE_ENG5_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 9664 #define MMVM_INVALIDATE_ENG5_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 9665 #define MMVM_INVALIDATE_ENG5_REQ__LOG_REQUEST__SHIFT 0x19 9666 #define MMVM_INVALIDATE_ENG5_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a 9667 #define MMVM_INVALIDATE_ENG5_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL 9668 #define MMVM_INVALIDATE_ENG5_REQ__FLUSH_TYPE_MASK 0x00070000L 9669 #define MMVM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L 9670 #define MMVM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L 9671 #define MMVM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L 9672 #define MMVM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L 9673 #define MMVM_INVALIDATE_ENG5_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L 9674 #define MMVM_INVALIDATE_ENG5_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L 9675 #define MMVM_INVALIDATE_ENG5_REQ__LOG_REQUEST_MASK 0x02000000L 9676 #define MMVM_INVALIDATE_ENG5_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L 9677 //MMVM_INVALIDATE_ENG5_ACK 9678 #define MMVM_INVALIDATE_ENG5_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 9679 #define MMVM_INVALIDATE_ENG5_ACK__SEMAPHORE__SHIFT 0x10 9680 #define MMVM_INVALIDATE_ENG5_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL 9681 #define MMVM_INVALIDATE_ENG5_ACK__SEMAPHORE_MASK 0x00010000L 9682 //MMVM_INVALIDATE_ENG5_ADDR_RANGE_LO32 9683 #define MMVM_INVALIDATE_ENG5_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 9684 #define MMVM_INVALIDATE_ENG5_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 9685 #define MMVM_INVALIDATE_ENG5_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L 9686 #define MMVM_INVALIDATE_ENG5_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL 9687 //MMVM_INVALIDATE_ENG5_ADDR_RANGE_HI32 9688 #define MMVM_INVALIDATE_ENG5_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 9689 #define MMVM_INVALIDATE_ENG5_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL 9690 //MMVM_INVALIDATE_ENG5_RESERVE0 9691 #define MMVM_INVALIDATE_ENG5_RESERVE0__DUMMY__SHIFT 0x0 9692 #define MMVM_INVALIDATE_ENG5_RESERVE0__DUMMY_MASK 0xFFFFFFFFL 9693 //MMVM_INVALIDATE_ENG5_RESERVE1 9694 #define MMVM_INVALIDATE_ENG5_RESERVE1__DUMMY__SHIFT 0x0 9695 #define MMVM_INVALIDATE_ENG5_RESERVE1__DUMMY_MASK 0xFFFFFFFFL 9696 //MMVM_INVALIDATE_ENG5_RESERVE2 9697 #define MMVM_INVALIDATE_ENG5_RESERVE2__DUMMY__SHIFT 0x0 9698 #define MMVM_INVALIDATE_ENG5_RESERVE2__DUMMY_MASK 0xFFFFFFFFL 9699 //MMVM_INVALIDATE_ENG6_SEM 9700 #define MMVM_INVALIDATE_ENG6_SEM__SEMAPHORE__SHIFT 0x0 9701 #define MMVM_INVALIDATE_ENG6_SEM__SEMAPHORE_MASK 0x00000001L 9702 //MMVM_INVALIDATE_ENG6_REQ 9703 #define MMVM_INVALIDATE_ENG6_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 9704 #define MMVM_INVALIDATE_ENG6_REQ__FLUSH_TYPE__SHIFT 0x10 9705 #define MMVM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 9706 #define MMVM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 9707 #define MMVM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 9708 #define MMVM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 9709 #define MMVM_INVALIDATE_ENG6_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 9710 #define MMVM_INVALIDATE_ENG6_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 9711 #define MMVM_INVALIDATE_ENG6_REQ__LOG_REQUEST__SHIFT 0x19 9712 #define MMVM_INVALIDATE_ENG6_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a 9713 #define MMVM_INVALIDATE_ENG6_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL 9714 #define MMVM_INVALIDATE_ENG6_REQ__FLUSH_TYPE_MASK 0x00070000L 9715 #define MMVM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L 9716 #define MMVM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L 9717 #define MMVM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L 9718 #define MMVM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L 9719 #define MMVM_INVALIDATE_ENG6_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L 9720 #define MMVM_INVALIDATE_ENG6_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L 9721 #define MMVM_INVALIDATE_ENG6_REQ__LOG_REQUEST_MASK 0x02000000L 9722 #define MMVM_INVALIDATE_ENG6_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L 9723 //MMVM_INVALIDATE_ENG6_ACK 9724 #define MMVM_INVALIDATE_ENG6_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 9725 #define MMVM_INVALIDATE_ENG6_ACK__SEMAPHORE__SHIFT 0x10 9726 #define MMVM_INVALIDATE_ENG6_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL 9727 #define MMVM_INVALIDATE_ENG6_ACK__SEMAPHORE_MASK 0x00010000L 9728 //MMVM_INVALIDATE_ENG6_ADDR_RANGE_LO32 9729 #define MMVM_INVALIDATE_ENG6_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 9730 #define MMVM_INVALIDATE_ENG6_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 9731 #define MMVM_INVALIDATE_ENG6_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L 9732 #define MMVM_INVALIDATE_ENG6_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL 9733 //MMVM_INVALIDATE_ENG6_ADDR_RANGE_HI32 9734 #define MMVM_INVALIDATE_ENG6_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 9735 #define MMVM_INVALIDATE_ENG6_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL 9736 //MMVM_INVALIDATE_ENG6_RESERVE0 9737 #define MMVM_INVALIDATE_ENG6_RESERVE0__DUMMY__SHIFT 0x0 9738 #define MMVM_INVALIDATE_ENG6_RESERVE0__DUMMY_MASK 0xFFFFFFFFL 9739 //MMVM_INVALIDATE_ENG6_RESERVE1 9740 #define MMVM_INVALIDATE_ENG6_RESERVE1__DUMMY__SHIFT 0x0 9741 #define MMVM_INVALIDATE_ENG6_RESERVE1__DUMMY_MASK 0xFFFFFFFFL 9742 //MMVM_INVALIDATE_ENG6_RESERVE2 9743 #define MMVM_INVALIDATE_ENG6_RESERVE2__DUMMY__SHIFT 0x0 9744 #define MMVM_INVALIDATE_ENG6_RESERVE2__DUMMY_MASK 0xFFFFFFFFL 9745 //MMVM_INVALIDATE_ENG7_SEM 9746 #define MMVM_INVALIDATE_ENG7_SEM__SEMAPHORE__SHIFT 0x0 9747 #define MMVM_INVALIDATE_ENG7_SEM__SEMAPHORE_MASK 0x00000001L 9748 //MMVM_INVALIDATE_ENG7_REQ 9749 #define MMVM_INVALIDATE_ENG7_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 9750 #define MMVM_INVALIDATE_ENG7_REQ__FLUSH_TYPE__SHIFT 0x10 9751 #define MMVM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 9752 #define MMVM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 9753 #define MMVM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 9754 #define MMVM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 9755 #define MMVM_INVALIDATE_ENG7_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 9756 #define MMVM_INVALIDATE_ENG7_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 9757 #define MMVM_INVALIDATE_ENG7_REQ__LOG_REQUEST__SHIFT 0x19 9758 #define MMVM_INVALIDATE_ENG7_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a 9759 #define MMVM_INVALIDATE_ENG7_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL 9760 #define MMVM_INVALIDATE_ENG7_REQ__FLUSH_TYPE_MASK 0x00070000L 9761 #define MMVM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L 9762 #define MMVM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L 9763 #define MMVM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L 9764 #define MMVM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L 9765 #define MMVM_INVALIDATE_ENG7_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L 9766 #define MMVM_INVALIDATE_ENG7_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L 9767 #define MMVM_INVALIDATE_ENG7_REQ__LOG_REQUEST_MASK 0x02000000L 9768 #define MMVM_INVALIDATE_ENG7_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L 9769 //MMVM_INVALIDATE_ENG7_ACK 9770 #define MMVM_INVALIDATE_ENG7_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 9771 #define MMVM_INVALIDATE_ENG7_ACK__SEMAPHORE__SHIFT 0x10 9772 #define MMVM_INVALIDATE_ENG7_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL 9773 #define MMVM_INVALIDATE_ENG7_ACK__SEMAPHORE_MASK 0x00010000L 9774 //MMVM_INVALIDATE_ENG7_ADDR_RANGE_LO32 9775 #define MMVM_INVALIDATE_ENG7_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 9776 #define MMVM_INVALIDATE_ENG7_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 9777 #define MMVM_INVALIDATE_ENG7_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L 9778 #define MMVM_INVALIDATE_ENG7_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL 9779 //MMVM_INVALIDATE_ENG7_ADDR_RANGE_HI32 9780 #define MMVM_INVALIDATE_ENG7_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 9781 #define MMVM_INVALIDATE_ENG7_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL 9782 //MMVM_INVALIDATE_ENG7_RESERVE0 9783 #define MMVM_INVALIDATE_ENG7_RESERVE0__DUMMY__SHIFT 0x0 9784 #define MMVM_INVALIDATE_ENG7_RESERVE0__DUMMY_MASK 0xFFFFFFFFL 9785 //MMVM_INVALIDATE_ENG7_RESERVE1 9786 #define MMVM_INVALIDATE_ENG7_RESERVE1__DUMMY__SHIFT 0x0 9787 #define MMVM_INVALIDATE_ENG7_RESERVE1__DUMMY_MASK 0xFFFFFFFFL 9788 //MMVM_INVALIDATE_ENG7_RESERVE2 9789 #define MMVM_INVALIDATE_ENG7_RESERVE2__DUMMY__SHIFT 0x0 9790 #define MMVM_INVALIDATE_ENG7_RESERVE2__DUMMY_MASK 0xFFFFFFFFL 9791 //MMVM_INVALIDATE_ENG8_SEM 9792 #define MMVM_INVALIDATE_ENG8_SEM__SEMAPHORE__SHIFT 0x0 9793 #define MMVM_INVALIDATE_ENG8_SEM__SEMAPHORE_MASK 0x00000001L 9794 //MMVM_INVALIDATE_ENG8_REQ 9795 #define MMVM_INVALIDATE_ENG8_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 9796 #define MMVM_INVALIDATE_ENG8_REQ__FLUSH_TYPE__SHIFT 0x10 9797 #define MMVM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 9798 #define MMVM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 9799 #define MMVM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 9800 #define MMVM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 9801 #define MMVM_INVALIDATE_ENG8_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 9802 #define MMVM_INVALIDATE_ENG8_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 9803 #define MMVM_INVALIDATE_ENG8_REQ__LOG_REQUEST__SHIFT 0x19 9804 #define MMVM_INVALIDATE_ENG8_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a 9805 #define MMVM_INVALIDATE_ENG8_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL 9806 #define MMVM_INVALIDATE_ENG8_REQ__FLUSH_TYPE_MASK 0x00070000L 9807 #define MMVM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L 9808 #define MMVM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L 9809 #define MMVM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L 9810 #define MMVM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L 9811 #define MMVM_INVALIDATE_ENG8_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L 9812 #define MMVM_INVALIDATE_ENG8_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L 9813 #define MMVM_INVALIDATE_ENG8_REQ__LOG_REQUEST_MASK 0x02000000L 9814 #define MMVM_INVALIDATE_ENG8_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L 9815 //MMVM_INVALIDATE_ENG8_ACK 9816 #define MMVM_INVALIDATE_ENG8_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 9817 #define MMVM_INVALIDATE_ENG8_ACK__SEMAPHORE__SHIFT 0x10 9818 #define MMVM_INVALIDATE_ENG8_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL 9819 #define MMVM_INVALIDATE_ENG8_ACK__SEMAPHORE_MASK 0x00010000L 9820 //MMVM_INVALIDATE_ENG8_ADDR_RANGE_LO32 9821 #define MMVM_INVALIDATE_ENG8_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 9822 #define MMVM_INVALIDATE_ENG8_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 9823 #define MMVM_INVALIDATE_ENG8_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L 9824 #define MMVM_INVALIDATE_ENG8_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL 9825 //MMVM_INVALIDATE_ENG8_ADDR_RANGE_HI32 9826 #define MMVM_INVALIDATE_ENG8_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 9827 #define MMVM_INVALIDATE_ENG8_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL 9828 //MMVM_INVALIDATE_ENG8_RESERVE0 9829 #define MMVM_INVALIDATE_ENG8_RESERVE0__DUMMY__SHIFT 0x0 9830 #define MMVM_INVALIDATE_ENG8_RESERVE0__DUMMY_MASK 0xFFFFFFFFL 9831 //MMVM_INVALIDATE_ENG8_RESERVE1 9832 #define MMVM_INVALIDATE_ENG8_RESERVE1__DUMMY__SHIFT 0x0 9833 #define MMVM_INVALIDATE_ENG8_RESERVE1__DUMMY_MASK 0xFFFFFFFFL 9834 //MMVM_INVALIDATE_ENG8_RESERVE2 9835 #define MMVM_INVALIDATE_ENG8_RESERVE2__DUMMY__SHIFT 0x0 9836 #define MMVM_INVALIDATE_ENG8_RESERVE2__DUMMY_MASK 0xFFFFFFFFL 9837 //MMVM_INVALIDATE_ENG9_SEM 9838 #define MMVM_INVALIDATE_ENG9_SEM__SEMAPHORE__SHIFT 0x0 9839 #define MMVM_INVALIDATE_ENG9_SEM__SEMAPHORE_MASK 0x00000001L 9840 //MMVM_INVALIDATE_ENG9_REQ 9841 #define MMVM_INVALIDATE_ENG9_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 9842 #define MMVM_INVALIDATE_ENG9_REQ__FLUSH_TYPE__SHIFT 0x10 9843 #define MMVM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 9844 #define MMVM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 9845 #define MMVM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 9846 #define MMVM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 9847 #define MMVM_INVALIDATE_ENG9_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 9848 #define MMVM_INVALIDATE_ENG9_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 9849 #define MMVM_INVALIDATE_ENG9_REQ__LOG_REQUEST__SHIFT 0x19 9850 #define MMVM_INVALIDATE_ENG9_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a 9851 #define MMVM_INVALIDATE_ENG9_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL 9852 #define MMVM_INVALIDATE_ENG9_REQ__FLUSH_TYPE_MASK 0x00070000L 9853 #define MMVM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L 9854 #define MMVM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L 9855 #define MMVM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L 9856 #define MMVM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L 9857 #define MMVM_INVALIDATE_ENG9_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L 9858 #define MMVM_INVALIDATE_ENG9_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L 9859 #define MMVM_INVALIDATE_ENG9_REQ__LOG_REQUEST_MASK 0x02000000L 9860 #define MMVM_INVALIDATE_ENG9_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L 9861 //MMVM_INVALIDATE_ENG9_ACK 9862 #define MMVM_INVALIDATE_ENG9_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 9863 #define MMVM_INVALIDATE_ENG9_ACK__SEMAPHORE__SHIFT 0x10 9864 #define MMVM_INVALIDATE_ENG9_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL 9865 #define MMVM_INVALIDATE_ENG9_ACK__SEMAPHORE_MASK 0x00010000L 9866 //MMVM_INVALIDATE_ENG9_ADDR_RANGE_LO32 9867 #define MMVM_INVALIDATE_ENG9_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 9868 #define MMVM_INVALIDATE_ENG9_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 9869 #define MMVM_INVALIDATE_ENG9_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L 9870 #define MMVM_INVALIDATE_ENG9_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL 9871 //MMVM_INVALIDATE_ENG9_ADDR_RANGE_HI32 9872 #define MMVM_INVALIDATE_ENG9_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 9873 #define MMVM_INVALIDATE_ENG9_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL 9874 //MMVM_INVALIDATE_ENG9_RESERVE0 9875 #define MMVM_INVALIDATE_ENG9_RESERVE0__DUMMY__SHIFT 0x0 9876 #define MMVM_INVALIDATE_ENG9_RESERVE0__DUMMY_MASK 0xFFFFFFFFL 9877 //MMVM_INVALIDATE_ENG9_RESERVE1 9878 #define MMVM_INVALIDATE_ENG9_RESERVE1__DUMMY__SHIFT 0x0 9879 #define MMVM_INVALIDATE_ENG9_RESERVE1__DUMMY_MASK 0xFFFFFFFFL 9880 //MMVM_INVALIDATE_ENG9_RESERVE2 9881 #define MMVM_INVALIDATE_ENG9_RESERVE2__DUMMY__SHIFT 0x0 9882 #define MMVM_INVALIDATE_ENG9_RESERVE2__DUMMY_MASK 0xFFFFFFFFL 9883 //MMVM_INVALIDATE_ENG10_SEM 9884 #define MMVM_INVALIDATE_ENG10_SEM__SEMAPHORE__SHIFT 0x0 9885 #define MMVM_INVALIDATE_ENG10_SEM__SEMAPHORE_MASK 0x00000001L 9886 //MMVM_INVALIDATE_ENG10_REQ 9887 #define MMVM_INVALIDATE_ENG10_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 9888 #define MMVM_INVALIDATE_ENG10_REQ__FLUSH_TYPE__SHIFT 0x10 9889 #define MMVM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 9890 #define MMVM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 9891 #define MMVM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 9892 #define MMVM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 9893 #define MMVM_INVALIDATE_ENG10_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 9894 #define MMVM_INVALIDATE_ENG10_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 9895 #define MMVM_INVALIDATE_ENG10_REQ__LOG_REQUEST__SHIFT 0x19 9896 #define MMVM_INVALIDATE_ENG10_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a 9897 #define MMVM_INVALIDATE_ENG10_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL 9898 #define MMVM_INVALIDATE_ENG10_REQ__FLUSH_TYPE_MASK 0x00070000L 9899 #define MMVM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L 9900 #define MMVM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L 9901 #define MMVM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L 9902 #define MMVM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L 9903 #define MMVM_INVALIDATE_ENG10_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L 9904 #define MMVM_INVALIDATE_ENG10_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L 9905 #define MMVM_INVALIDATE_ENG10_REQ__LOG_REQUEST_MASK 0x02000000L 9906 #define MMVM_INVALIDATE_ENG10_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L 9907 //MMVM_INVALIDATE_ENG10_ACK 9908 #define MMVM_INVALIDATE_ENG10_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 9909 #define MMVM_INVALIDATE_ENG10_ACK__SEMAPHORE__SHIFT 0x10 9910 #define MMVM_INVALIDATE_ENG10_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL 9911 #define MMVM_INVALIDATE_ENG10_ACK__SEMAPHORE_MASK 0x00010000L 9912 //MMVM_INVALIDATE_ENG10_ADDR_RANGE_LO32 9913 #define MMVM_INVALIDATE_ENG10_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 9914 #define MMVM_INVALIDATE_ENG10_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 9915 #define MMVM_INVALIDATE_ENG10_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L 9916 #define MMVM_INVALIDATE_ENG10_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL 9917 //MMVM_INVALIDATE_ENG10_ADDR_RANGE_HI32 9918 #define MMVM_INVALIDATE_ENG10_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 9919 #define MMVM_INVALIDATE_ENG10_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL 9920 //MMVM_INVALIDATE_ENG10_RESERVE0 9921 #define MMVM_INVALIDATE_ENG10_RESERVE0__DUMMY__SHIFT 0x0 9922 #define MMVM_INVALIDATE_ENG10_RESERVE0__DUMMY_MASK 0xFFFFFFFFL 9923 //MMVM_INVALIDATE_ENG10_RESERVE1 9924 #define MMVM_INVALIDATE_ENG10_RESERVE1__DUMMY__SHIFT 0x0 9925 #define MMVM_INVALIDATE_ENG10_RESERVE1__DUMMY_MASK 0xFFFFFFFFL 9926 //MMVM_INVALIDATE_ENG10_RESERVE2 9927 #define MMVM_INVALIDATE_ENG10_RESERVE2__DUMMY__SHIFT 0x0 9928 #define MMVM_INVALIDATE_ENG10_RESERVE2__DUMMY_MASK 0xFFFFFFFFL 9929 //MMVM_INVALIDATE_ENG11_SEM 9930 #define MMVM_INVALIDATE_ENG11_SEM__SEMAPHORE__SHIFT 0x0 9931 #define MMVM_INVALIDATE_ENG11_SEM__SEMAPHORE_MASK 0x00000001L 9932 //MMVM_INVALIDATE_ENG11_REQ 9933 #define MMVM_INVALIDATE_ENG11_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 9934 #define MMVM_INVALIDATE_ENG11_REQ__FLUSH_TYPE__SHIFT 0x10 9935 #define MMVM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 9936 #define MMVM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 9937 #define MMVM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 9938 #define MMVM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 9939 #define MMVM_INVALIDATE_ENG11_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 9940 #define MMVM_INVALIDATE_ENG11_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 9941 #define MMVM_INVALIDATE_ENG11_REQ__LOG_REQUEST__SHIFT 0x19 9942 #define MMVM_INVALIDATE_ENG11_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a 9943 #define MMVM_INVALIDATE_ENG11_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL 9944 #define MMVM_INVALIDATE_ENG11_REQ__FLUSH_TYPE_MASK 0x00070000L 9945 #define MMVM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L 9946 #define MMVM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L 9947 #define MMVM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L 9948 #define MMVM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L 9949 #define MMVM_INVALIDATE_ENG11_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L 9950 #define MMVM_INVALIDATE_ENG11_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L 9951 #define MMVM_INVALIDATE_ENG11_REQ__LOG_REQUEST_MASK 0x02000000L 9952 #define MMVM_INVALIDATE_ENG11_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L 9953 //MMVM_INVALIDATE_ENG11_ACK 9954 #define MMVM_INVALIDATE_ENG11_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 9955 #define MMVM_INVALIDATE_ENG11_ACK__SEMAPHORE__SHIFT 0x10 9956 #define MMVM_INVALIDATE_ENG11_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL 9957 #define MMVM_INVALIDATE_ENG11_ACK__SEMAPHORE_MASK 0x00010000L 9958 //MMVM_INVALIDATE_ENG11_ADDR_RANGE_LO32 9959 #define MMVM_INVALIDATE_ENG11_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 9960 #define MMVM_INVALIDATE_ENG11_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 9961 #define MMVM_INVALIDATE_ENG11_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L 9962 #define MMVM_INVALIDATE_ENG11_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL 9963 //MMVM_INVALIDATE_ENG11_ADDR_RANGE_HI32 9964 #define MMVM_INVALIDATE_ENG11_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 9965 #define MMVM_INVALIDATE_ENG11_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL 9966 //MMVM_INVALIDATE_ENG11_RESERVE0 9967 #define MMVM_INVALIDATE_ENG11_RESERVE0__DUMMY__SHIFT 0x0 9968 #define MMVM_INVALIDATE_ENG11_RESERVE0__DUMMY_MASK 0xFFFFFFFFL 9969 //MMVM_INVALIDATE_ENG11_RESERVE1 9970 #define MMVM_INVALIDATE_ENG11_RESERVE1__DUMMY__SHIFT 0x0 9971 #define MMVM_INVALIDATE_ENG11_RESERVE1__DUMMY_MASK 0xFFFFFFFFL 9972 //MMVM_INVALIDATE_ENG11_RESERVE2 9973 #define MMVM_INVALIDATE_ENG11_RESERVE2__DUMMY__SHIFT 0x0 9974 #define MMVM_INVALIDATE_ENG11_RESERVE2__DUMMY_MASK 0xFFFFFFFFL 9975 //MMVM_INVALIDATE_ENG12_SEM 9976 #define MMVM_INVALIDATE_ENG12_SEM__SEMAPHORE__SHIFT 0x0 9977 #define MMVM_INVALIDATE_ENG12_SEM__SEMAPHORE_MASK 0x00000001L 9978 //MMVM_INVALIDATE_ENG12_REQ 9979 #define MMVM_INVALIDATE_ENG12_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 9980 #define MMVM_INVALIDATE_ENG12_REQ__FLUSH_TYPE__SHIFT 0x10 9981 #define MMVM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 9982 #define MMVM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 9983 #define MMVM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 9984 #define MMVM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 9985 #define MMVM_INVALIDATE_ENG12_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 9986 #define MMVM_INVALIDATE_ENG12_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 9987 #define MMVM_INVALIDATE_ENG12_REQ__LOG_REQUEST__SHIFT 0x19 9988 #define MMVM_INVALIDATE_ENG12_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a 9989 #define MMVM_INVALIDATE_ENG12_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL 9990 #define MMVM_INVALIDATE_ENG12_REQ__FLUSH_TYPE_MASK 0x00070000L 9991 #define MMVM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L 9992 #define MMVM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L 9993 #define MMVM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L 9994 #define MMVM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L 9995 #define MMVM_INVALIDATE_ENG12_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L 9996 #define MMVM_INVALIDATE_ENG12_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L 9997 #define MMVM_INVALIDATE_ENG12_REQ__LOG_REQUEST_MASK 0x02000000L 9998 #define MMVM_INVALIDATE_ENG12_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L 9999 //MMVM_INVALIDATE_ENG12_ACK 10000 #define MMVM_INVALIDATE_ENG12_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 10001 #define MMVM_INVALIDATE_ENG12_ACK__SEMAPHORE__SHIFT 0x10 10002 #define MMVM_INVALIDATE_ENG12_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL 10003 #define MMVM_INVALIDATE_ENG12_ACK__SEMAPHORE_MASK 0x00010000L 10004 //MMVM_INVALIDATE_ENG12_ADDR_RANGE_LO32 10005 #define MMVM_INVALIDATE_ENG12_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 10006 #define MMVM_INVALIDATE_ENG12_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 10007 #define MMVM_INVALIDATE_ENG12_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L 10008 #define MMVM_INVALIDATE_ENG12_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL 10009 //MMVM_INVALIDATE_ENG12_ADDR_RANGE_HI32 10010 #define MMVM_INVALIDATE_ENG12_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 10011 #define MMVM_INVALIDATE_ENG12_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL 10012 //MMVM_INVALIDATE_ENG12_RESERVE0 10013 #define MMVM_INVALIDATE_ENG12_RESERVE0__DUMMY__SHIFT 0x0 10014 #define MMVM_INVALIDATE_ENG12_RESERVE0__DUMMY_MASK 0xFFFFFFFFL 10015 //MMVM_INVALIDATE_ENG12_RESERVE1 10016 #define MMVM_INVALIDATE_ENG12_RESERVE1__DUMMY__SHIFT 0x0 10017 #define MMVM_INVALIDATE_ENG12_RESERVE1__DUMMY_MASK 0xFFFFFFFFL 10018 //MMVM_INVALIDATE_ENG12_RESERVE2 10019 #define MMVM_INVALIDATE_ENG12_RESERVE2__DUMMY__SHIFT 0x0 10020 #define MMVM_INVALIDATE_ENG12_RESERVE2__DUMMY_MASK 0xFFFFFFFFL 10021 //MMVM_INVALIDATE_ENG13_SEM 10022 #define MMVM_INVALIDATE_ENG13_SEM__SEMAPHORE__SHIFT 0x0 10023 #define MMVM_INVALIDATE_ENG13_SEM__SEMAPHORE_MASK 0x00000001L 10024 //MMVM_INVALIDATE_ENG13_REQ 10025 #define MMVM_INVALIDATE_ENG13_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 10026 #define MMVM_INVALIDATE_ENG13_REQ__FLUSH_TYPE__SHIFT 0x10 10027 #define MMVM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 10028 #define MMVM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 10029 #define MMVM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 10030 #define MMVM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 10031 #define MMVM_INVALIDATE_ENG13_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 10032 #define MMVM_INVALIDATE_ENG13_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 10033 #define MMVM_INVALIDATE_ENG13_REQ__LOG_REQUEST__SHIFT 0x19 10034 #define MMVM_INVALIDATE_ENG13_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a 10035 #define MMVM_INVALIDATE_ENG13_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL 10036 #define MMVM_INVALIDATE_ENG13_REQ__FLUSH_TYPE_MASK 0x00070000L 10037 #define MMVM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L 10038 #define MMVM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L 10039 #define MMVM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L 10040 #define MMVM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L 10041 #define MMVM_INVALIDATE_ENG13_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L 10042 #define MMVM_INVALIDATE_ENG13_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L 10043 #define MMVM_INVALIDATE_ENG13_REQ__LOG_REQUEST_MASK 0x02000000L 10044 #define MMVM_INVALIDATE_ENG13_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L 10045 //MMVM_INVALIDATE_ENG13_ACK 10046 #define MMVM_INVALIDATE_ENG13_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 10047 #define MMVM_INVALIDATE_ENG13_ACK__SEMAPHORE__SHIFT 0x10 10048 #define MMVM_INVALIDATE_ENG13_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL 10049 #define MMVM_INVALIDATE_ENG13_ACK__SEMAPHORE_MASK 0x00010000L 10050 //MMVM_INVALIDATE_ENG13_ADDR_RANGE_LO32 10051 #define MMVM_INVALIDATE_ENG13_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 10052 #define MMVM_INVALIDATE_ENG13_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 10053 #define MMVM_INVALIDATE_ENG13_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L 10054 #define MMVM_INVALIDATE_ENG13_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL 10055 //MMVM_INVALIDATE_ENG13_ADDR_RANGE_HI32 10056 #define MMVM_INVALIDATE_ENG13_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 10057 #define MMVM_INVALIDATE_ENG13_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL 10058 //MMVM_INVALIDATE_ENG13_RESERVE0 10059 #define MMVM_INVALIDATE_ENG13_RESERVE0__DUMMY__SHIFT 0x0 10060 #define MMVM_INVALIDATE_ENG13_RESERVE0__DUMMY_MASK 0xFFFFFFFFL 10061 //MMVM_INVALIDATE_ENG13_RESERVE1 10062 #define MMVM_INVALIDATE_ENG13_RESERVE1__DUMMY__SHIFT 0x0 10063 #define MMVM_INVALIDATE_ENG13_RESERVE1__DUMMY_MASK 0xFFFFFFFFL 10064 //MMVM_INVALIDATE_ENG13_RESERVE2 10065 #define MMVM_INVALIDATE_ENG13_RESERVE2__DUMMY__SHIFT 0x0 10066 #define MMVM_INVALIDATE_ENG13_RESERVE2__DUMMY_MASK 0xFFFFFFFFL 10067 //MMVM_INVALIDATE_ENG14_SEM 10068 #define MMVM_INVALIDATE_ENG14_SEM__SEMAPHORE__SHIFT 0x0 10069 #define MMVM_INVALIDATE_ENG14_SEM__SEMAPHORE_MASK 0x00000001L 10070 //MMVM_INVALIDATE_ENG14_REQ 10071 #define MMVM_INVALIDATE_ENG14_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 10072 #define MMVM_INVALIDATE_ENG14_REQ__FLUSH_TYPE__SHIFT 0x10 10073 #define MMVM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 10074 #define MMVM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 10075 #define MMVM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 10076 #define MMVM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 10077 #define MMVM_INVALIDATE_ENG14_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 10078 #define MMVM_INVALIDATE_ENG14_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 10079 #define MMVM_INVALIDATE_ENG14_REQ__LOG_REQUEST__SHIFT 0x19 10080 #define MMVM_INVALIDATE_ENG14_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a 10081 #define MMVM_INVALIDATE_ENG14_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL 10082 #define MMVM_INVALIDATE_ENG14_REQ__FLUSH_TYPE_MASK 0x00070000L 10083 #define MMVM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L 10084 #define MMVM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L 10085 #define MMVM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L 10086 #define MMVM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L 10087 #define MMVM_INVALIDATE_ENG14_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L 10088 #define MMVM_INVALIDATE_ENG14_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L 10089 #define MMVM_INVALIDATE_ENG14_REQ__LOG_REQUEST_MASK 0x02000000L 10090 #define MMVM_INVALIDATE_ENG14_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L 10091 //MMVM_INVALIDATE_ENG14_ACK 10092 #define MMVM_INVALIDATE_ENG14_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 10093 #define MMVM_INVALIDATE_ENG14_ACK__SEMAPHORE__SHIFT 0x10 10094 #define MMVM_INVALIDATE_ENG14_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL 10095 #define MMVM_INVALIDATE_ENG14_ACK__SEMAPHORE_MASK 0x00010000L 10096 //MMVM_INVALIDATE_ENG14_ADDR_RANGE_LO32 10097 #define MMVM_INVALIDATE_ENG14_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 10098 #define MMVM_INVALIDATE_ENG14_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 10099 #define MMVM_INVALIDATE_ENG14_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L 10100 #define MMVM_INVALIDATE_ENG14_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL 10101 //MMVM_INVALIDATE_ENG14_ADDR_RANGE_HI32 10102 #define MMVM_INVALIDATE_ENG14_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 10103 #define MMVM_INVALIDATE_ENG14_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL 10104 //MMVM_INVALIDATE_ENG14_RESERVE0 10105 #define MMVM_INVALIDATE_ENG14_RESERVE0__DUMMY__SHIFT 0x0 10106 #define MMVM_INVALIDATE_ENG14_RESERVE0__DUMMY_MASK 0xFFFFFFFFL 10107 //MMVM_INVALIDATE_ENG14_RESERVE1 10108 #define MMVM_INVALIDATE_ENG14_RESERVE1__DUMMY__SHIFT 0x0 10109 #define MMVM_INVALIDATE_ENG14_RESERVE1__DUMMY_MASK 0xFFFFFFFFL 10110 //MMVM_INVALIDATE_ENG14_RESERVE2 10111 #define MMVM_INVALIDATE_ENG14_RESERVE2__DUMMY__SHIFT 0x0 10112 #define MMVM_INVALIDATE_ENG14_RESERVE2__DUMMY_MASK 0xFFFFFFFFL 10113 //MMVM_INVALIDATE_ENG15_SEM 10114 #define MMVM_INVALIDATE_ENG15_SEM__SEMAPHORE__SHIFT 0x0 10115 #define MMVM_INVALIDATE_ENG15_SEM__SEMAPHORE_MASK 0x00000001L 10116 //MMVM_INVALIDATE_ENG15_REQ 10117 #define MMVM_INVALIDATE_ENG15_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 10118 #define MMVM_INVALIDATE_ENG15_REQ__FLUSH_TYPE__SHIFT 0x10 10119 #define MMVM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 10120 #define MMVM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 10121 #define MMVM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 10122 #define MMVM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 10123 #define MMVM_INVALIDATE_ENG15_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 10124 #define MMVM_INVALIDATE_ENG15_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 10125 #define MMVM_INVALIDATE_ENG15_REQ__LOG_REQUEST__SHIFT 0x19 10126 #define MMVM_INVALIDATE_ENG15_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a 10127 #define MMVM_INVALIDATE_ENG15_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL 10128 #define MMVM_INVALIDATE_ENG15_REQ__FLUSH_TYPE_MASK 0x00070000L 10129 #define MMVM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L 10130 #define MMVM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L 10131 #define MMVM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L 10132 #define MMVM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L 10133 #define MMVM_INVALIDATE_ENG15_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L 10134 #define MMVM_INVALIDATE_ENG15_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L 10135 #define MMVM_INVALIDATE_ENG15_REQ__LOG_REQUEST_MASK 0x02000000L 10136 #define MMVM_INVALIDATE_ENG15_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L 10137 //MMVM_INVALIDATE_ENG15_ACK 10138 #define MMVM_INVALIDATE_ENG15_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 10139 #define MMVM_INVALIDATE_ENG15_ACK__SEMAPHORE__SHIFT 0x10 10140 #define MMVM_INVALIDATE_ENG15_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL 10141 #define MMVM_INVALIDATE_ENG15_ACK__SEMAPHORE_MASK 0x00010000L 10142 //MMVM_INVALIDATE_ENG15_ADDR_RANGE_LO32 10143 #define MMVM_INVALIDATE_ENG15_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 10144 #define MMVM_INVALIDATE_ENG15_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 10145 #define MMVM_INVALIDATE_ENG15_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L 10146 #define MMVM_INVALIDATE_ENG15_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL 10147 //MMVM_INVALIDATE_ENG15_ADDR_RANGE_HI32 10148 #define MMVM_INVALIDATE_ENG15_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 10149 #define MMVM_INVALIDATE_ENG15_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL 10150 //MMVM_INVALIDATE_ENG15_RESERVE0 10151 #define MMVM_INVALIDATE_ENG15_RESERVE0__DUMMY__SHIFT 0x0 10152 #define MMVM_INVALIDATE_ENG15_RESERVE0__DUMMY_MASK 0xFFFFFFFFL 10153 //MMVM_INVALIDATE_ENG15_RESERVE1 10154 #define MMVM_INVALIDATE_ENG15_RESERVE1__DUMMY__SHIFT 0x0 10155 #define MMVM_INVALIDATE_ENG15_RESERVE1__DUMMY_MASK 0xFFFFFFFFL 10156 //MMVM_INVALIDATE_ENG15_RESERVE2 10157 #define MMVM_INVALIDATE_ENG15_RESERVE2__DUMMY__SHIFT 0x0 10158 #define MMVM_INVALIDATE_ENG15_RESERVE2__DUMMY_MASK 0xFFFFFFFFL 10159 //MMVM_INVALIDATE_ENG16_SEM 10160 #define MMVM_INVALIDATE_ENG16_SEM__SEMAPHORE__SHIFT 0x0 10161 #define MMVM_INVALIDATE_ENG16_SEM__SEMAPHORE_MASK 0x00000001L 10162 //MMVM_INVALIDATE_ENG16_REQ 10163 #define MMVM_INVALIDATE_ENG16_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 10164 #define MMVM_INVALIDATE_ENG16_REQ__FLUSH_TYPE__SHIFT 0x10 10165 #define MMVM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 10166 #define MMVM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 10167 #define MMVM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 10168 #define MMVM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 10169 #define MMVM_INVALIDATE_ENG16_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 10170 #define MMVM_INVALIDATE_ENG16_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 10171 #define MMVM_INVALIDATE_ENG16_REQ__LOG_REQUEST__SHIFT 0x19 10172 #define MMVM_INVALIDATE_ENG16_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a 10173 #define MMVM_INVALIDATE_ENG16_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL 10174 #define MMVM_INVALIDATE_ENG16_REQ__FLUSH_TYPE_MASK 0x00070000L 10175 #define MMVM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L 10176 #define MMVM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L 10177 #define MMVM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L 10178 #define MMVM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L 10179 #define MMVM_INVALIDATE_ENG16_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L 10180 #define MMVM_INVALIDATE_ENG16_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L 10181 #define MMVM_INVALIDATE_ENG16_REQ__LOG_REQUEST_MASK 0x02000000L 10182 #define MMVM_INVALIDATE_ENG16_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L 10183 //MMVM_INVALIDATE_ENG16_ACK 10184 #define MMVM_INVALIDATE_ENG16_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 10185 #define MMVM_INVALIDATE_ENG16_ACK__SEMAPHORE__SHIFT 0x10 10186 #define MMVM_INVALIDATE_ENG16_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL 10187 #define MMVM_INVALIDATE_ENG16_ACK__SEMAPHORE_MASK 0x00010000L 10188 //MMVM_INVALIDATE_ENG16_ADDR_RANGE_LO32 10189 #define MMVM_INVALIDATE_ENG16_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 10190 #define MMVM_INVALIDATE_ENG16_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 10191 #define MMVM_INVALIDATE_ENG16_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L 10192 #define MMVM_INVALIDATE_ENG16_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL 10193 //MMVM_INVALIDATE_ENG16_ADDR_RANGE_HI32 10194 #define MMVM_INVALIDATE_ENG16_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 10195 #define MMVM_INVALIDATE_ENG16_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL 10196 //MMVM_INVALIDATE_ENG16_RESERVE0 10197 #define MMVM_INVALIDATE_ENG16_RESERVE0__DUMMY__SHIFT 0x0 10198 #define MMVM_INVALIDATE_ENG16_RESERVE0__DUMMY_MASK 0xFFFFFFFFL 10199 //MMVM_INVALIDATE_ENG16_RESERVE1 10200 #define MMVM_INVALIDATE_ENG16_RESERVE1__DUMMY__SHIFT 0x0 10201 #define MMVM_INVALIDATE_ENG16_RESERVE1__DUMMY_MASK 0xFFFFFFFFL 10202 //MMVM_INVALIDATE_ENG16_RESERVE2 10203 #define MMVM_INVALIDATE_ENG16_RESERVE2__DUMMY__SHIFT 0x0 10204 #define MMVM_INVALIDATE_ENG16_RESERVE2__DUMMY_MASK 0xFFFFFFFFL 10205 //MMVM_INVALIDATE_ENG17_SEM 10206 #define MMVM_INVALIDATE_ENG17_SEM__SEMAPHORE__SHIFT 0x0 10207 #define MMVM_INVALIDATE_ENG17_SEM__SEMAPHORE_MASK 0x00000001L 10208 //MMVM_INVALIDATE_ENG17_REQ 10209 #define MMVM_INVALIDATE_ENG17_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 10210 #define MMVM_INVALIDATE_ENG17_REQ__FLUSH_TYPE__SHIFT 0x10 10211 #define MMVM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 10212 #define MMVM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 10213 #define MMVM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 10214 #define MMVM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 10215 #define MMVM_INVALIDATE_ENG17_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 10216 #define MMVM_INVALIDATE_ENG17_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 10217 #define MMVM_INVALIDATE_ENG17_REQ__LOG_REQUEST__SHIFT 0x19 10218 #define MMVM_INVALIDATE_ENG17_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a 10219 #define MMVM_INVALIDATE_ENG17_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL 10220 #define MMVM_INVALIDATE_ENG17_REQ__FLUSH_TYPE_MASK 0x00070000L 10221 #define MMVM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L 10222 #define MMVM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L 10223 #define MMVM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L 10224 #define MMVM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L 10225 #define MMVM_INVALIDATE_ENG17_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L 10226 #define MMVM_INVALIDATE_ENG17_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L 10227 #define MMVM_INVALIDATE_ENG17_REQ__LOG_REQUEST_MASK 0x02000000L 10228 #define MMVM_INVALIDATE_ENG17_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L 10229 //MMVM_INVALIDATE_ENG17_ACK 10230 #define MMVM_INVALIDATE_ENG17_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 10231 #define MMVM_INVALIDATE_ENG17_ACK__SEMAPHORE__SHIFT 0x10 10232 #define MMVM_INVALIDATE_ENG17_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL 10233 #define MMVM_INVALIDATE_ENG17_ACK__SEMAPHORE_MASK 0x00010000L 10234 //MMVM_INVALIDATE_ENG17_ADDR_RANGE_LO32 10235 #define MMVM_INVALIDATE_ENG17_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 10236 #define MMVM_INVALIDATE_ENG17_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 10237 #define MMVM_INVALIDATE_ENG17_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L 10238 #define MMVM_INVALIDATE_ENG17_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL 10239 //MMVM_INVALIDATE_ENG17_ADDR_RANGE_HI32 10240 #define MMVM_INVALIDATE_ENG17_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 10241 #define MMVM_INVALIDATE_ENG17_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL 10242 //MMVM_INVALIDATE_ENG17_RESERVE0 10243 #define MMVM_INVALIDATE_ENG17_RESERVE0__DUMMY__SHIFT 0x0 10244 #define MMVM_INVALIDATE_ENG17_RESERVE0__DUMMY_MASK 0xFFFFFFFFL 10245 //MMVM_INVALIDATE_ENG17_RESERVE1 10246 #define MMVM_INVALIDATE_ENG17_RESERVE1__DUMMY__SHIFT 0x0 10247 #define MMVM_INVALIDATE_ENG17_RESERVE1__DUMMY_MASK 0xFFFFFFFFL 10248 //MMVM_INVALIDATE_ENG17_RESERVE2 10249 #define MMVM_INVALIDATE_ENG17_RESERVE2__DUMMY__SHIFT 0x0 10250 #define MMVM_INVALIDATE_ENG17_RESERVE2__DUMMY_MASK 0xFFFFFFFFL 10251 10252 10253 // addressBlock: mmhub_mmutcl2_mml2tlbpfdec 10254 //MML2TLB_TLB0_STATUS 10255 #define MML2TLB_TLB0_STATUS__BUSY__SHIFT 0x0 10256 #define MML2TLB_TLB0_STATUS__FOUND_PARITY_ERRORS__SHIFT 0x1 10257 #define MML2TLB_TLB0_STATUS__BUSY_MASK 0x00000001L 10258 #define MML2TLB_TLB0_STATUS__FOUND_PARITY_ERRORS_MASK 0x00000002L 10259 10260 10261 // addressBlock: mmhub_mmutcl2_mml2tlbpldec 10262 //MML2TLB_PERFCOUNTER0_CFG 10263 #define MML2TLB_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 10264 #define MML2TLB_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 10265 #define MML2TLB_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 10266 #define MML2TLB_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c 10267 #define MML2TLB_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d 10268 #define MML2TLB_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL 10269 #define MML2TLB_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L 10270 #define MML2TLB_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L 10271 #define MML2TLB_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L 10272 #define MML2TLB_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L 10273 //MML2TLB_PERFCOUNTER1_CFG 10274 #define MML2TLB_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 10275 #define MML2TLB_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 10276 #define MML2TLB_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 10277 #define MML2TLB_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c 10278 #define MML2TLB_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d 10279 #define MML2TLB_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL 10280 #define MML2TLB_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L 10281 #define MML2TLB_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L 10282 #define MML2TLB_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L 10283 #define MML2TLB_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L 10284 //MML2TLB_PERFCOUNTER2_CFG 10285 #define MML2TLB_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0 10286 #define MML2TLB_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8 10287 #define MML2TLB_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18 10288 #define MML2TLB_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c 10289 #define MML2TLB_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d 10290 #define MML2TLB_PERFCOUNTER2_CFG__PERF_SEL_MASK 0x000000FFL 10291 #define MML2TLB_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0x0000FF00L 10292 #define MML2TLB_PERFCOUNTER2_CFG__PERF_MODE_MASK 0x0F000000L 10293 #define MML2TLB_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000L 10294 #define MML2TLB_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000L 10295 //MML2TLB_PERFCOUNTER3_CFG 10296 #define MML2TLB_PERFCOUNTER3_CFG__PERF_SEL__SHIFT 0x0 10297 #define MML2TLB_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT 0x8 10298 #define MML2TLB_PERFCOUNTER3_CFG__PERF_MODE__SHIFT 0x18 10299 #define MML2TLB_PERFCOUNTER3_CFG__ENABLE__SHIFT 0x1c 10300 #define MML2TLB_PERFCOUNTER3_CFG__CLEAR__SHIFT 0x1d 10301 #define MML2TLB_PERFCOUNTER3_CFG__PERF_SEL_MASK 0x000000FFL 10302 #define MML2TLB_PERFCOUNTER3_CFG__PERF_SEL_END_MASK 0x0000FF00L 10303 #define MML2TLB_PERFCOUNTER3_CFG__PERF_MODE_MASK 0x0F000000L 10304 #define MML2TLB_PERFCOUNTER3_CFG__ENABLE_MASK 0x10000000L 10305 #define MML2TLB_PERFCOUNTER3_CFG__CLEAR_MASK 0x20000000L 10306 //MML2TLB_PERFCOUNTER_RSLT_CNTL 10307 #define MML2TLB_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 10308 #define MML2TLB_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 10309 #define MML2TLB_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 10310 #define MML2TLB_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 10311 #define MML2TLB_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 10312 #define MML2TLB_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a 10313 #define MML2TLB_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL 10314 #define MML2TLB_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L 10315 #define MML2TLB_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L 10316 #define MML2TLB_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L 10317 #define MML2TLB_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L 10318 #define MML2TLB_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L 10319 10320 10321 // addressBlock: mmhub_mmutcl2_mml2tlbprdec 10322 //MML2TLB_PERFCOUNTER_LO 10323 #define MML2TLB_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 10324 #define MML2TLB_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL 10325 //MML2TLB_PERFCOUNTER_HI 10326 #define MML2TLB_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 10327 #define MML2TLB_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 10328 #define MML2TLB_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL 10329 #define MML2TLB_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L 10330 10331 #endif 10332