1*81570d6dSHawking Zhang /* 2*81570d6dSHawking Zhang * Copyright 2021 Advanced Micro Devices, Inc. 3*81570d6dSHawking Zhang * 4*81570d6dSHawking Zhang * Permission is hereby granted, free of charge, to any person obtaining a 5*81570d6dSHawking Zhang * copy of this software and associated documentation files (the "Software"), 6*81570d6dSHawking Zhang * to deal in the Software without restriction, including without limitation 7*81570d6dSHawking Zhang * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8*81570d6dSHawking Zhang * and/or sell copies of the Software, and to permit persons to whom the 9*81570d6dSHawking Zhang * Software is furnished to do so, subject to the following conditions: 10*81570d6dSHawking Zhang * 11*81570d6dSHawking Zhang * The above copyright notice and this permission notice shall be included in 12*81570d6dSHawking Zhang * all copies or substantial portions of the Software. 13*81570d6dSHawking Zhang * 14*81570d6dSHawking Zhang * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15*81570d6dSHawking Zhang * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16*81570d6dSHawking Zhang * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17*81570d6dSHawking Zhang * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18*81570d6dSHawking Zhang * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19*81570d6dSHawking Zhang * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20*81570d6dSHawking Zhang * OTHER DEALINGS IN THE SOFTWARE. 21*81570d6dSHawking Zhang * 22*81570d6dSHawking Zhang */ 23*81570d6dSHawking Zhang #ifndef _lsdma_6_0_0_SH_MASK_HEADER 24*81570d6dSHawking Zhang #define _lsdma_6_0_0_SH_MASK_HEADER 25*81570d6dSHawking Zhang 26*81570d6dSHawking Zhang 27*81570d6dSHawking Zhang // addressBlock: lsdma0_lsdma0dec 28*81570d6dSHawking Zhang //LSDMA_UCODE_ADDR 29*81570d6dSHawking Zhang #define LSDMA_UCODE_ADDR__VALUE__SHIFT 0x0 30*81570d6dSHawking Zhang #define LSDMA_UCODE_ADDR__VALUE_MASK 0x00001FFFL 31*81570d6dSHawking Zhang //LSDMA_UCODE_DATA 32*81570d6dSHawking Zhang #define LSDMA_UCODE_DATA__VALUE__SHIFT 0x0 33*81570d6dSHawking Zhang #define LSDMA_UCODE_DATA__VALUE_MASK 0xFFFFFFFFL 34*81570d6dSHawking Zhang //LSDMA_ERROR_INJECT_CNTL 35*81570d6dSHawking Zhang #define LSDMA_ERROR_INJECT_CNTL__ENABLE_IRRITATION__SHIFT 0x0 36*81570d6dSHawking Zhang #define LSDMA_ERROR_INJECT_CNTL__ENABLE_SINGLE_WRITE__SHIFT 0x1 37*81570d6dSHawking Zhang #define LSDMA_ERROR_INJECT_CNTL__ENABLE_ERROR_INJECT__SHIFT 0x2 38*81570d6dSHawking Zhang #define LSDMA_ERROR_INJECT_CNTL__ENABLE_IRRITATION_MASK 0x00000001L 39*81570d6dSHawking Zhang #define LSDMA_ERROR_INJECT_CNTL__ENABLE_SINGLE_WRITE_MASK 0x00000002L 40*81570d6dSHawking Zhang #define LSDMA_ERROR_INJECT_CNTL__ENABLE_ERROR_INJECT_MASK 0x0000000CL 41*81570d6dSHawking Zhang //LSDMA_ERROR_INJECT_SELECT 42*81570d6dSHawking Zhang #define LSDMA_ERROR_INJECT_SELECT__MBANK_DATA_BUF0__SHIFT 0x0 43*81570d6dSHawking Zhang #define LSDMA_ERROR_INJECT_SELECT__MBANK_DATA_BUF1__SHIFT 0x1 44*81570d6dSHawking Zhang #define LSDMA_ERROR_INJECT_SELECT__MBANK_DATA_BUF2__SHIFT 0x2 45*81570d6dSHawking Zhang #define LSDMA_ERROR_INJECT_SELECT__MBANK_DATA_BUF3__SHIFT 0x3 46*81570d6dSHawking Zhang #define LSDMA_ERROR_INJECT_SELECT__MBANK_DATA_BUF4__SHIFT 0x4 47*81570d6dSHawking Zhang #define LSDMA_ERROR_INJECT_SELECT__MBANK_DATA_BUF5__SHIFT 0x5 48*81570d6dSHawking Zhang #define LSDMA_ERROR_INJECT_SELECT__MBANK_DATA_BUF6__SHIFT 0x6 49*81570d6dSHawking Zhang #define LSDMA_ERROR_INJECT_SELECT__MBANK_DATA_BUF7__SHIFT 0x7 50*81570d6dSHawking Zhang #define LSDMA_ERROR_INJECT_SELECT__MBANK_DATA_BUF8__SHIFT 0x8 51*81570d6dSHawking Zhang #define LSDMA_ERROR_INJECT_SELECT__MBANK_DATA_BUF9__SHIFT 0x9 52*81570d6dSHawking Zhang #define LSDMA_ERROR_INJECT_SELECT__MBANK_DATA_BUF10__SHIFT 0xa 53*81570d6dSHawking Zhang #define LSDMA_ERROR_INJECT_SELECT__MBANK_DATA_BUF11__SHIFT 0xb 54*81570d6dSHawking Zhang #define LSDMA_ERROR_INJECT_SELECT__MBANK_DATA_BUF12__SHIFT 0xc 55*81570d6dSHawking Zhang #define LSDMA_ERROR_INJECT_SELECT__MBANK_DATA_BUF13__SHIFT 0xd 56*81570d6dSHawking Zhang #define LSDMA_ERROR_INJECT_SELECT__MBANK_DATA_BUF14__SHIFT 0xe 57*81570d6dSHawking Zhang #define LSDMA_ERROR_INJECT_SELECT__MBANK_DATA_BUF15__SHIFT 0xf 58*81570d6dSHawking Zhang #define LSDMA_ERROR_INJECT_SELECT__UCODE_BUF__SHIFT 0x10 59*81570d6dSHawking Zhang #define LSDMA_ERROR_INJECT_SELECT__RB_CMD_BUF__SHIFT 0x11 60*81570d6dSHawking Zhang #define LSDMA_ERROR_INJECT_SELECT__IB_CMD_BUF__SHIFT 0x12 61*81570d6dSHawking Zhang #define LSDMA_ERROR_INJECT_SELECT__UTCL1_RD_FIFO__SHIFT 0x13 62*81570d6dSHawking Zhang #define LSDMA_ERROR_INJECT_SELECT__UTCL1_RDBST_FIFO__SHIFT 0x14 63*81570d6dSHawking Zhang #define LSDMA_ERROR_INJECT_SELECT__UTCL1_WR_FIFO__SHIFT 0x15 64*81570d6dSHawking Zhang #define LSDMA_ERROR_INJECT_SELECT__DATA_LUT_FIFO__SHIFT 0x16 65*81570d6dSHawking Zhang #define LSDMA_ERROR_INJECT_SELECT__SPLIT_DATA_FIFO__SHIFT 0x17 66*81570d6dSHawking Zhang #define LSDMA_ERROR_INJECT_SELECT__MC_WR_ADDR_FIFO__SHIFT 0x18 67*81570d6dSHawking Zhang #define LSDMA_ERROR_INJECT_SELECT__MC_RDRET_BUF__SHIFT 0x19 68*81570d6dSHawking Zhang #define LSDMA_ERROR_INJECT_SELECT__MBANK_DATA_BUF0_MASK 0x00000001L 69*81570d6dSHawking Zhang #define LSDMA_ERROR_INJECT_SELECT__MBANK_DATA_BUF1_MASK 0x00000002L 70*81570d6dSHawking Zhang #define LSDMA_ERROR_INJECT_SELECT__MBANK_DATA_BUF2_MASK 0x00000004L 71*81570d6dSHawking Zhang #define LSDMA_ERROR_INJECT_SELECT__MBANK_DATA_BUF3_MASK 0x00000008L 72*81570d6dSHawking Zhang #define LSDMA_ERROR_INJECT_SELECT__MBANK_DATA_BUF4_MASK 0x00000010L 73*81570d6dSHawking Zhang #define LSDMA_ERROR_INJECT_SELECT__MBANK_DATA_BUF5_MASK 0x00000020L 74*81570d6dSHawking Zhang #define LSDMA_ERROR_INJECT_SELECT__MBANK_DATA_BUF6_MASK 0x00000040L 75*81570d6dSHawking Zhang #define LSDMA_ERROR_INJECT_SELECT__MBANK_DATA_BUF7_MASK 0x00000080L 76*81570d6dSHawking Zhang #define LSDMA_ERROR_INJECT_SELECT__MBANK_DATA_BUF8_MASK 0x00000100L 77*81570d6dSHawking Zhang #define LSDMA_ERROR_INJECT_SELECT__MBANK_DATA_BUF9_MASK 0x00000200L 78*81570d6dSHawking Zhang #define LSDMA_ERROR_INJECT_SELECT__MBANK_DATA_BUF10_MASK 0x00000400L 79*81570d6dSHawking Zhang #define LSDMA_ERROR_INJECT_SELECT__MBANK_DATA_BUF11_MASK 0x00000800L 80*81570d6dSHawking Zhang #define LSDMA_ERROR_INJECT_SELECT__MBANK_DATA_BUF12_MASK 0x00001000L 81*81570d6dSHawking Zhang #define LSDMA_ERROR_INJECT_SELECT__MBANK_DATA_BUF13_MASK 0x00002000L 82*81570d6dSHawking Zhang #define LSDMA_ERROR_INJECT_SELECT__MBANK_DATA_BUF14_MASK 0x00004000L 83*81570d6dSHawking Zhang #define LSDMA_ERROR_INJECT_SELECT__MBANK_DATA_BUF15_MASK 0x00008000L 84*81570d6dSHawking Zhang #define LSDMA_ERROR_INJECT_SELECT__UCODE_BUF_MASK 0x00010000L 85*81570d6dSHawking Zhang #define LSDMA_ERROR_INJECT_SELECT__RB_CMD_BUF_MASK 0x00020000L 86*81570d6dSHawking Zhang #define LSDMA_ERROR_INJECT_SELECT__IB_CMD_BUF_MASK 0x00040000L 87*81570d6dSHawking Zhang #define LSDMA_ERROR_INJECT_SELECT__UTCL1_RD_FIFO_MASK 0x00080000L 88*81570d6dSHawking Zhang #define LSDMA_ERROR_INJECT_SELECT__UTCL1_RDBST_FIFO_MASK 0x00100000L 89*81570d6dSHawking Zhang #define LSDMA_ERROR_INJECT_SELECT__UTCL1_WR_FIFO_MASK 0x00200000L 90*81570d6dSHawking Zhang #define LSDMA_ERROR_INJECT_SELECT__DATA_LUT_FIFO_MASK 0x00400000L 91*81570d6dSHawking Zhang #define LSDMA_ERROR_INJECT_SELECT__SPLIT_DATA_FIFO_MASK 0x00800000L 92*81570d6dSHawking Zhang #define LSDMA_ERROR_INJECT_SELECT__MC_WR_ADDR_FIFO_MASK 0x01000000L 93*81570d6dSHawking Zhang #define LSDMA_ERROR_INJECT_SELECT__MC_RDRET_BUF_MASK 0x02000000L 94*81570d6dSHawking Zhang #define LSDMA_PUB_REG_TYPE0__LSDMA_UCODE_ADDR__SHIFT 0x0 95*81570d6dSHawking Zhang #define LSDMA_PUB_REG_TYPE0__LSDMA_UCODE_DATA__SHIFT 0x1 96*81570d6dSHawking Zhang #define LSDMA_PUB_REG_TYPE0__LSDMA_UCODE_ADDR_MASK 0x00000001L 97*81570d6dSHawking Zhang #define LSDMA_PUB_REG_TYPE0__LSDMA_UCODE_DATA_MASK 0x00000002L 98*81570d6dSHawking Zhang #define LSDMA_PUB_REG_TYPE3__LSDMA_CLK_CTRL__SHIFT 0x12 99*81570d6dSHawking Zhang #define LSDMA_PUB_REG_TYPE3__LSDMA_CLK_CTRL_MASK 0x00040000L 100*81570d6dSHawking Zhang //LSDMA_CONTEXT_GROUP_BOUNDARY 101*81570d6dSHawking Zhang #define LSDMA_CONTEXT_GROUP_BOUNDARY__RESERVED__SHIFT 0x0 102*81570d6dSHawking Zhang #define LSDMA_CONTEXT_GROUP_BOUNDARY__RESERVED_MASK 0xFFFFFFFFL 103*81570d6dSHawking Zhang //LSDMA_RB_RPTR_FETCH_HI 104*81570d6dSHawking Zhang #define LSDMA_RB_RPTR_FETCH_HI__OFFSET__SHIFT 0x0 105*81570d6dSHawking Zhang #define LSDMA_RB_RPTR_FETCH_HI__OFFSET_MASK 0xFFFFFFFFL 106*81570d6dSHawking Zhang //LSDMA_SEM_WAIT_FAIL_TIMER_CNTL 107*81570d6dSHawking Zhang #define LSDMA_SEM_WAIT_FAIL_TIMER_CNTL__TIMER__SHIFT 0x0 108*81570d6dSHawking Zhang #define LSDMA_SEM_WAIT_FAIL_TIMER_CNTL__TIMER_MASK 0xFFFFFFFFL 109*81570d6dSHawking Zhang //LSDMA_RB_RPTR_FETCH 110*81570d6dSHawking Zhang #define LSDMA_RB_RPTR_FETCH__OFFSET__SHIFT 0x2 111*81570d6dSHawking Zhang #define LSDMA_RB_RPTR_FETCH__OFFSET_MASK 0xFFFFFFFCL 112*81570d6dSHawking Zhang //LSDMA_IB_OFFSET_FETCH 113*81570d6dSHawking Zhang #define LSDMA_IB_OFFSET_FETCH__OFFSET__SHIFT 0x2 114*81570d6dSHawking Zhang #define LSDMA_IB_OFFSET_FETCH__OFFSET_MASK 0x003FFFFCL 115*81570d6dSHawking Zhang //LSDMA_PROGRAM 116*81570d6dSHawking Zhang #define LSDMA_PROGRAM__STREAM__SHIFT 0x0 117*81570d6dSHawking Zhang #define LSDMA_PROGRAM__STREAM_MASK 0xFFFFFFFFL 118*81570d6dSHawking Zhang //LSDMA_STATUS_REG 119*81570d6dSHawking Zhang #define LSDMA_STATUS_REG__IDLE__SHIFT 0x0 120*81570d6dSHawking Zhang #define LSDMA_STATUS_REG__REG_IDLE__SHIFT 0x1 121*81570d6dSHawking Zhang #define LSDMA_STATUS_REG__RB_EMPTY__SHIFT 0x2 122*81570d6dSHawking Zhang #define LSDMA_STATUS_REG__RB_FULL__SHIFT 0x3 123*81570d6dSHawking Zhang #define LSDMA_STATUS_REG__RB_CMD_IDLE__SHIFT 0x4 124*81570d6dSHawking Zhang #define LSDMA_STATUS_REG__RB_CMD_FULL__SHIFT 0x5 125*81570d6dSHawking Zhang #define LSDMA_STATUS_REG__IB_CMD_IDLE__SHIFT 0x6 126*81570d6dSHawking Zhang #define LSDMA_STATUS_REG__IB_CMD_FULL__SHIFT 0x7 127*81570d6dSHawking Zhang #define LSDMA_STATUS_REG__BLOCK_IDLE__SHIFT 0x8 128*81570d6dSHawking Zhang #define LSDMA_STATUS_REG__INSIDE_IB__SHIFT 0x9 129*81570d6dSHawking Zhang #define LSDMA_STATUS_REG__EX_IDLE__SHIFT 0xa 130*81570d6dSHawking Zhang #define LSDMA_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE__SHIFT 0xb 131*81570d6dSHawking Zhang #define LSDMA_STATUS_REG__PACKET_READY__SHIFT 0xc 132*81570d6dSHawking Zhang #define LSDMA_STATUS_REG__MC_WR_IDLE__SHIFT 0xd 133*81570d6dSHawking Zhang #define LSDMA_STATUS_REG__SRBM_IDLE__SHIFT 0xe 134*81570d6dSHawking Zhang #define LSDMA_STATUS_REG__CONTEXT_EMPTY__SHIFT 0xf 135*81570d6dSHawking Zhang #define LSDMA_STATUS_REG__DELTA_RPTR_FULL__SHIFT 0x10 136*81570d6dSHawking Zhang #define LSDMA_STATUS_REG__RB_MC_RREQ_IDLE__SHIFT 0x11 137*81570d6dSHawking Zhang #define LSDMA_STATUS_REG__IB_MC_RREQ_IDLE__SHIFT 0x12 138*81570d6dSHawking Zhang #define LSDMA_STATUS_REG__MC_RD_IDLE__SHIFT 0x13 139*81570d6dSHawking Zhang #define LSDMA_STATUS_REG__DELTA_RPTR_EMPTY__SHIFT 0x14 140*81570d6dSHawking Zhang #define LSDMA_STATUS_REG__MC_RD_RET_STALL__SHIFT 0x15 141*81570d6dSHawking Zhang #define LSDMA_STATUS_REG__MC_RD_NO_POLL_IDLE__SHIFT 0x16 142*81570d6dSHawking Zhang #define LSDMA_STATUS_REG__Reserved__SHIFT 0x18 143*81570d6dSHawking Zhang #define LSDMA_STATUS_REG__PREV_CMD_IDLE__SHIFT 0x19 144*81570d6dSHawking Zhang #define LSDMA_STATUS_REG__SEM_IDLE__SHIFT 0x1a 145*81570d6dSHawking Zhang #define LSDMA_STATUS_REG__SEM_REQ_STALL__SHIFT 0x1b 146*81570d6dSHawking Zhang #define LSDMA_STATUS_REG__SEM_RESP_STATE__SHIFT 0x1c 147*81570d6dSHawking Zhang #define LSDMA_STATUS_REG__INT_IDLE__SHIFT 0x1e 148*81570d6dSHawking Zhang #define LSDMA_STATUS_REG__INT_REQ_STALL__SHIFT 0x1f 149*81570d6dSHawking Zhang #define LSDMA_STATUS_REG__IDLE_MASK 0x00000001L 150*81570d6dSHawking Zhang #define LSDMA_STATUS_REG__REG_IDLE_MASK 0x00000002L 151*81570d6dSHawking Zhang #define LSDMA_STATUS_REG__RB_EMPTY_MASK 0x00000004L 152*81570d6dSHawking Zhang #define LSDMA_STATUS_REG__RB_FULL_MASK 0x00000008L 153*81570d6dSHawking Zhang #define LSDMA_STATUS_REG__RB_CMD_IDLE_MASK 0x00000010L 154*81570d6dSHawking Zhang #define LSDMA_STATUS_REG__RB_CMD_FULL_MASK 0x00000020L 155*81570d6dSHawking Zhang #define LSDMA_STATUS_REG__IB_CMD_IDLE_MASK 0x00000040L 156*81570d6dSHawking Zhang #define LSDMA_STATUS_REG__IB_CMD_FULL_MASK 0x00000080L 157*81570d6dSHawking Zhang #define LSDMA_STATUS_REG__BLOCK_IDLE_MASK 0x00000100L 158*81570d6dSHawking Zhang #define LSDMA_STATUS_REG__INSIDE_IB_MASK 0x00000200L 159*81570d6dSHawking Zhang #define LSDMA_STATUS_REG__EX_IDLE_MASK 0x00000400L 160*81570d6dSHawking Zhang #define LSDMA_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE_MASK 0x00000800L 161*81570d6dSHawking Zhang #define LSDMA_STATUS_REG__PACKET_READY_MASK 0x00001000L 162*81570d6dSHawking Zhang #define LSDMA_STATUS_REG__MC_WR_IDLE_MASK 0x00002000L 163*81570d6dSHawking Zhang #define LSDMA_STATUS_REG__SRBM_IDLE_MASK 0x00004000L 164*81570d6dSHawking Zhang #define LSDMA_STATUS_REG__CONTEXT_EMPTY_MASK 0x00008000L 165*81570d6dSHawking Zhang #define LSDMA_STATUS_REG__DELTA_RPTR_FULL_MASK 0x00010000L 166*81570d6dSHawking Zhang #define LSDMA_STATUS_REG__RB_MC_RREQ_IDLE_MASK 0x00020000L 167*81570d6dSHawking Zhang #define LSDMA_STATUS_REG__IB_MC_RREQ_IDLE_MASK 0x00040000L 168*81570d6dSHawking Zhang #define LSDMA_STATUS_REG__MC_RD_IDLE_MASK 0x00080000L 169*81570d6dSHawking Zhang #define LSDMA_STATUS_REG__DELTA_RPTR_EMPTY_MASK 0x00100000L 170*81570d6dSHawking Zhang #define LSDMA_STATUS_REG__MC_RD_RET_STALL_MASK 0x00200000L 171*81570d6dSHawking Zhang #define LSDMA_STATUS_REG__MC_RD_NO_POLL_IDLE_MASK 0x00400000L 172*81570d6dSHawking Zhang #define LSDMA_STATUS_REG__Reserved_MASK 0x01000000L 173*81570d6dSHawking Zhang #define LSDMA_STATUS_REG__PREV_CMD_IDLE_MASK 0x02000000L 174*81570d6dSHawking Zhang #define LSDMA_STATUS_REG__SEM_IDLE_MASK 0x04000000L 175*81570d6dSHawking Zhang #define LSDMA_STATUS_REG__SEM_REQ_STALL_MASK 0x08000000L 176*81570d6dSHawking Zhang #define LSDMA_STATUS_REG__SEM_RESP_STATE_MASK 0x30000000L 177*81570d6dSHawking Zhang #define LSDMA_STATUS_REG__INT_IDLE_MASK 0x40000000L 178*81570d6dSHawking Zhang #define LSDMA_STATUS_REG__INT_REQ_STALL_MASK 0x80000000L 179*81570d6dSHawking Zhang //LSDMA_STATUS1_REG 180*81570d6dSHawking Zhang #define LSDMA_STATUS1_REG__CE_WREQ_IDLE__SHIFT 0x0 181*81570d6dSHawking Zhang #define LSDMA_STATUS1_REG__CE_WR_IDLE__SHIFT 0x1 182*81570d6dSHawking Zhang #define LSDMA_STATUS1_REG__CE_SPLIT_IDLE__SHIFT 0x2 183*81570d6dSHawking Zhang #define LSDMA_STATUS1_REG__CE_RREQ_IDLE__SHIFT 0x3 184*81570d6dSHawking Zhang #define LSDMA_STATUS1_REG__CE_OUT_IDLE__SHIFT 0x4 185*81570d6dSHawking Zhang #define LSDMA_STATUS1_REG__CE_IN_IDLE__SHIFT 0x5 186*81570d6dSHawking Zhang #define LSDMA_STATUS1_REG__CE_DST_IDLE__SHIFT 0x6 187*81570d6dSHawking Zhang #define LSDMA_STATUS1_REG__CE_CMD_IDLE__SHIFT 0x9 188*81570d6dSHawking Zhang #define LSDMA_STATUS1_REG__CE_AFIFO_FULL__SHIFT 0xa 189*81570d6dSHawking Zhang #define LSDMA_STATUS1_REG__CE_INFO_FULL__SHIFT 0xb 190*81570d6dSHawking Zhang #define LSDMA_STATUS1_REG__CE_INFO1_FULL__SHIFT 0xc 191*81570d6dSHawking Zhang #define LSDMA_STATUS1_REG__EX_START__SHIFT 0xd 192*81570d6dSHawking Zhang #define LSDMA_STATUS1_REG__CE_RD_STALL__SHIFT 0xf 193*81570d6dSHawking Zhang #define LSDMA_STATUS1_REG__CE_WR_STALL__SHIFT 0x10 194*81570d6dSHawking Zhang #define LSDMA_STATUS1_REG__CE_WREQ_IDLE_MASK 0x00000001L 195*81570d6dSHawking Zhang #define LSDMA_STATUS1_REG__CE_WR_IDLE_MASK 0x00000002L 196*81570d6dSHawking Zhang #define LSDMA_STATUS1_REG__CE_SPLIT_IDLE_MASK 0x00000004L 197*81570d6dSHawking Zhang #define LSDMA_STATUS1_REG__CE_RREQ_IDLE_MASK 0x00000008L 198*81570d6dSHawking Zhang #define LSDMA_STATUS1_REG__CE_OUT_IDLE_MASK 0x00000010L 199*81570d6dSHawking Zhang #define LSDMA_STATUS1_REG__CE_IN_IDLE_MASK 0x00000020L 200*81570d6dSHawking Zhang #define LSDMA_STATUS1_REG__CE_DST_IDLE_MASK 0x00000040L 201*81570d6dSHawking Zhang #define LSDMA_STATUS1_REG__CE_CMD_IDLE_MASK 0x00000200L 202*81570d6dSHawking Zhang #define LSDMA_STATUS1_REG__CE_AFIFO_FULL_MASK 0x00000400L 203*81570d6dSHawking Zhang #define LSDMA_STATUS1_REG__CE_INFO_FULL_MASK 0x00000800L 204*81570d6dSHawking Zhang #define LSDMA_STATUS1_REG__CE_INFO1_FULL_MASK 0x00001000L 205*81570d6dSHawking Zhang #define LSDMA_STATUS1_REG__EX_START_MASK 0x00002000L 206*81570d6dSHawking Zhang #define LSDMA_STATUS1_REG__CE_RD_STALL_MASK 0x00008000L 207*81570d6dSHawking Zhang #define LSDMA_STATUS1_REG__CE_WR_STALL_MASK 0x00010000L 208*81570d6dSHawking Zhang //LSDMA_RD_BURST_CNTL 209*81570d6dSHawking Zhang #define LSDMA_RD_BURST_CNTL__RD_BURST__SHIFT 0x0 210*81570d6dSHawking Zhang #define LSDMA_RD_BURST_CNTL__CMD_BUFFER_RD_BURST__SHIFT 0x2 211*81570d6dSHawking Zhang #define LSDMA_RD_BURST_CNTL__RD_BURST_MASK 0x00000003L 212*81570d6dSHawking Zhang #define LSDMA_RD_BURST_CNTL__CMD_BUFFER_RD_BURST_MASK 0x0000000CL 213*81570d6dSHawking Zhang //LSDMA_HBM_PAGE_CONFIG 214*81570d6dSHawking Zhang #define LSDMA_HBM_PAGE_CONFIG__PAGE_SIZE_EXPONENT__SHIFT 0x0 215*81570d6dSHawking Zhang #define LSDMA_HBM_PAGE_CONFIG__PAGE_SIZE_EXPONENT_MASK 0x00000003L 216*81570d6dSHawking Zhang //LSDMA_UCODE_CHECKSUM 217*81570d6dSHawking Zhang #define LSDMA_UCODE_CHECKSUM__DATA__SHIFT 0x0 218*81570d6dSHawking Zhang #define LSDMA_UCODE_CHECKSUM__DATA_MASK 0xFFFFFFFFL 219*81570d6dSHawking Zhang //LSDMA_FREEZE 220*81570d6dSHawking Zhang #define LSDMA_FREEZE__PREEMPT__SHIFT 0x0 221*81570d6dSHawking Zhang #define LSDMA_FREEZE__FREEZE__SHIFT 0x4 222*81570d6dSHawking Zhang #define LSDMA_FREEZE__FROZEN__SHIFT 0x5 223*81570d6dSHawking Zhang #define LSDMA_FREEZE__F32_FREEZE__SHIFT 0x6 224*81570d6dSHawking Zhang #define LSDMA_FREEZE__PREEMPT_MASK 0x00000001L 225*81570d6dSHawking Zhang #define LSDMA_FREEZE__FREEZE_MASK 0x00000010L 226*81570d6dSHawking Zhang #define LSDMA_FREEZE__FROZEN_MASK 0x00000020L 227*81570d6dSHawking Zhang #define LSDMA_FREEZE__F32_FREEZE_MASK 0x00000040L 228*81570d6dSHawking Zhang //LSDMA_PF_PIO_STATUS 229*81570d6dSHawking Zhang #define LSDMA_PF_PIO_STATUS__CMD_IN_FIFO__SHIFT 0x0 230*81570d6dSHawking Zhang #define LSDMA_PF_PIO_STATUS__CMD_PROCESSING__SHIFT 0x3 231*81570d6dSHawking Zhang #define LSDMA_PF_PIO_STATUS__ERROR_VM_HOLE__SHIFT 0x8 232*81570d6dSHawking Zhang #define LSDMA_PF_PIO_STATUS__ERROR_ZERO_COUNT__SHIFT 0x9 233*81570d6dSHawking Zhang #define LSDMA_PF_PIO_STATUS__ERROR_DRAM_ECC__SHIFT 0xa 234*81570d6dSHawking Zhang #define LSDMA_PF_PIO_STATUS__ERROR_SRAM_ECC__SHIFT 0xb 235*81570d6dSHawking Zhang #define LSDMA_PF_PIO_STATUS__ERROR_WRRET_NACK_GEN_ERR__SHIFT 0xf 236*81570d6dSHawking Zhang #define LSDMA_PF_PIO_STATUS__ERROR_RDRET_NACK_GEN_ERR__SHIFT 0x10 237*81570d6dSHawking Zhang #define LSDMA_PF_PIO_STATUS__ERROR_WRRET_NACK_PRT__SHIFT 0x11 238*81570d6dSHawking Zhang #define LSDMA_PF_PIO_STATUS__ERROR_RDRET_NACK_PRT__SHIFT 0x12 239*81570d6dSHawking Zhang #define LSDMA_PF_PIO_STATUS__PIO_FIFO_EMPTY__SHIFT 0x1c 240*81570d6dSHawking Zhang #define LSDMA_PF_PIO_STATUS__PIO_FIFO_FULL__SHIFT 0x1d 241*81570d6dSHawking Zhang #define LSDMA_PF_PIO_STATUS__PIO_IDLE__SHIFT 0x1f 242*81570d6dSHawking Zhang #define LSDMA_PF_PIO_STATUS__CMD_IN_FIFO_MASK 0x00000007L 243*81570d6dSHawking Zhang #define LSDMA_PF_PIO_STATUS__CMD_PROCESSING_MASK 0x000000F8L 244*81570d6dSHawking Zhang #define LSDMA_PF_PIO_STATUS__ERROR_VM_HOLE_MASK 0x00000100L 245*81570d6dSHawking Zhang #define LSDMA_PF_PIO_STATUS__ERROR_ZERO_COUNT_MASK 0x00000200L 246*81570d6dSHawking Zhang #define LSDMA_PF_PIO_STATUS__ERROR_DRAM_ECC_MASK 0x00000400L 247*81570d6dSHawking Zhang #define LSDMA_PF_PIO_STATUS__ERROR_SRAM_ECC_MASK 0x00000800L 248*81570d6dSHawking Zhang #define LSDMA_PF_PIO_STATUS__ERROR_WRRET_NACK_GEN_ERR_MASK 0x00008000L 249*81570d6dSHawking Zhang #define LSDMA_PF_PIO_STATUS__ERROR_RDRET_NACK_GEN_ERR_MASK 0x00010000L 250*81570d6dSHawking Zhang #define LSDMA_PF_PIO_STATUS__ERROR_WRRET_NACK_PRT_MASK 0x00020000L 251*81570d6dSHawking Zhang #define LSDMA_PF_PIO_STATUS__ERROR_RDRET_NACK_PRT_MASK 0x00040000L 252*81570d6dSHawking Zhang #define LSDMA_PF_PIO_STATUS__PIO_FIFO_EMPTY_MASK 0x10000000L 253*81570d6dSHawking Zhang #define LSDMA_PF_PIO_STATUS__PIO_FIFO_FULL_MASK 0x20000000L 254*81570d6dSHawking Zhang #define LSDMA_PF_PIO_STATUS__PIO_IDLE_MASK 0x80000000L 255*81570d6dSHawking Zhang //LSDMA_VF_PIO_STATUS 256*81570d6dSHawking Zhang #define LSDMA_VF_PIO_STATUS__CMD_IN_FIFO__SHIFT 0x0 257*81570d6dSHawking Zhang #define LSDMA_VF_PIO_STATUS__CMD_PROCESSING__SHIFT 0x3 258*81570d6dSHawking Zhang #define LSDMA_VF_PIO_STATUS__ERROR_VM_HOLE__SHIFT 0x8 259*81570d6dSHawking Zhang #define LSDMA_VF_PIO_STATUS__ERROR_ZERO_COUNT__SHIFT 0x9 260*81570d6dSHawking Zhang #define LSDMA_VF_PIO_STATUS__ERROR_DRAM_ECC__SHIFT 0xa 261*81570d6dSHawking Zhang #define LSDMA_VF_PIO_STATUS__ERROR_SRAM_ECC__SHIFT 0xb 262*81570d6dSHawking Zhang #define LSDMA_VF_PIO_STATUS__ERROR_WRRET_NACK_GEN_ERR__SHIFT 0xf 263*81570d6dSHawking Zhang #define LSDMA_VF_PIO_STATUS__ERROR_RDRET_NACK_GEN_ERR__SHIFT 0x10 264*81570d6dSHawking Zhang #define LSDMA_VF_PIO_STATUS__ERROR_WRRET_NACK_PRT__SHIFT 0x11 265*81570d6dSHawking Zhang #define LSDMA_VF_PIO_STATUS__ERROR_RDRET_NACK_PRT__SHIFT 0x12 266*81570d6dSHawking Zhang #define LSDMA_VF_PIO_STATUS__PIO_FIFO_EMPTY__SHIFT 0x1c 267*81570d6dSHawking Zhang #define LSDMA_VF_PIO_STATUS__PIO_FIFO_FULL__SHIFT 0x1d 268*81570d6dSHawking Zhang #define LSDMA_VF_PIO_STATUS__PIO_IDLE__SHIFT 0x1f 269*81570d6dSHawking Zhang #define LSDMA_VF_PIO_STATUS__CMD_IN_FIFO_MASK 0x00000007L 270*81570d6dSHawking Zhang #define LSDMA_VF_PIO_STATUS__CMD_PROCESSING_MASK 0x000000F8L 271*81570d6dSHawking Zhang #define LSDMA_VF_PIO_STATUS__ERROR_VM_HOLE_MASK 0x00000100L 272*81570d6dSHawking Zhang #define LSDMA_VF_PIO_STATUS__ERROR_ZERO_COUNT_MASK 0x00000200L 273*81570d6dSHawking Zhang #define LSDMA_VF_PIO_STATUS__ERROR_DRAM_ECC_MASK 0x00000400L 274*81570d6dSHawking Zhang #define LSDMA_VF_PIO_STATUS__ERROR_SRAM_ECC_MASK 0x00000800L 275*81570d6dSHawking Zhang #define LSDMA_VF_PIO_STATUS__ERROR_WRRET_NACK_GEN_ERR_MASK 0x00008000L 276*81570d6dSHawking Zhang #define LSDMA_VF_PIO_STATUS__ERROR_RDRET_NACK_GEN_ERR_MASK 0x00010000L 277*81570d6dSHawking Zhang #define LSDMA_VF_PIO_STATUS__ERROR_WRRET_NACK_PRT_MASK 0x00020000L 278*81570d6dSHawking Zhang #define LSDMA_VF_PIO_STATUS__ERROR_RDRET_NACK_PRT_MASK 0x00040000L 279*81570d6dSHawking Zhang #define LSDMA_VF_PIO_STATUS__PIO_FIFO_EMPTY_MASK 0x10000000L 280*81570d6dSHawking Zhang #define LSDMA_VF_PIO_STATUS__PIO_FIFO_FULL_MASK 0x20000000L 281*81570d6dSHawking Zhang #define LSDMA_VF_PIO_STATUS__PIO_IDLE_MASK 0x80000000L 282*81570d6dSHawking Zhang //LSDMA_POWER_GATING 283*81570d6dSHawking Zhang #define LSDMA_POWER_GATING__LSDMA_POWER_OFF_CONDITION__SHIFT 0x0 284*81570d6dSHawking Zhang #define LSDMA_POWER_GATING__LSDMA_POWER_ON_CONDITION__SHIFT 0x1 285*81570d6dSHawking Zhang #define LSDMA_POWER_GATING__LSDMA_POWER_OFF_REQ__SHIFT 0x2 286*81570d6dSHawking Zhang #define LSDMA_POWER_GATING__LSDMA_POWER_ON_REQ__SHIFT 0x3 287*81570d6dSHawking Zhang #define LSDMA_POWER_GATING__PG_CNTL_STATUS__SHIFT 0x4 288*81570d6dSHawking Zhang #define LSDMA_POWER_GATING__LSDMA_POWER_OFF_CONDITION_MASK 0x00000001L 289*81570d6dSHawking Zhang #define LSDMA_POWER_GATING__LSDMA_POWER_ON_CONDITION_MASK 0x00000002L 290*81570d6dSHawking Zhang #define LSDMA_POWER_GATING__LSDMA_POWER_OFF_REQ_MASK 0x00000004L 291*81570d6dSHawking Zhang #define LSDMA_POWER_GATING__LSDMA_POWER_ON_REQ_MASK 0x00000008L 292*81570d6dSHawking Zhang #define LSDMA_POWER_GATING__PG_CNTL_STATUS_MASK 0x00000030L 293*81570d6dSHawking Zhang //LSDMA_PGFSM_CONFIG 294*81570d6dSHawking Zhang #define LSDMA_PGFSM_CONFIG__FSM_ADDR__SHIFT 0x0 295*81570d6dSHawking Zhang #define LSDMA_PGFSM_CONFIG__POWER_DOWN__SHIFT 0x8 296*81570d6dSHawking Zhang #define LSDMA_PGFSM_CONFIG__POWER_UP__SHIFT 0x9 297*81570d6dSHawking Zhang #define LSDMA_PGFSM_CONFIG__P1_SELECT__SHIFT 0xa 298*81570d6dSHawking Zhang #define LSDMA_PGFSM_CONFIG__P2_SELECT__SHIFT 0xb 299*81570d6dSHawking Zhang #define LSDMA_PGFSM_CONFIG__WRITE__SHIFT 0xc 300*81570d6dSHawking Zhang #define LSDMA_PGFSM_CONFIG__READ__SHIFT 0xd 301*81570d6dSHawking Zhang #define LSDMA_PGFSM_CONFIG__SRBM_OVERRIDE__SHIFT 0x1b 302*81570d6dSHawking Zhang #define LSDMA_PGFSM_CONFIG__REG_ADDR__SHIFT 0x1c 303*81570d6dSHawking Zhang #define LSDMA_PGFSM_CONFIG__FSM_ADDR_MASK 0x000000FFL 304*81570d6dSHawking Zhang #define LSDMA_PGFSM_CONFIG__POWER_DOWN_MASK 0x00000100L 305*81570d6dSHawking Zhang #define LSDMA_PGFSM_CONFIG__POWER_UP_MASK 0x00000200L 306*81570d6dSHawking Zhang #define LSDMA_PGFSM_CONFIG__P1_SELECT_MASK 0x00000400L 307*81570d6dSHawking Zhang #define LSDMA_PGFSM_CONFIG__P2_SELECT_MASK 0x00000800L 308*81570d6dSHawking Zhang #define LSDMA_PGFSM_CONFIG__WRITE_MASK 0x00001000L 309*81570d6dSHawking Zhang #define LSDMA_PGFSM_CONFIG__READ_MASK 0x00002000L 310*81570d6dSHawking Zhang #define LSDMA_PGFSM_CONFIG__SRBM_OVERRIDE_MASK 0x08000000L 311*81570d6dSHawking Zhang #define LSDMA_PGFSM_CONFIG__REG_ADDR_MASK 0xF0000000L 312*81570d6dSHawking Zhang //LSDMA_PGFSM_WRITE 313*81570d6dSHawking Zhang #define LSDMA_PGFSM_WRITE__VALUE__SHIFT 0x0 314*81570d6dSHawking Zhang #define LSDMA_PGFSM_WRITE__VALUE_MASK 0xFFFFFFFFL 315*81570d6dSHawking Zhang //LSDMA_PGFSM_READ 316*81570d6dSHawking Zhang #define LSDMA_PGFSM_READ__VALUE__SHIFT 0x0 317*81570d6dSHawking Zhang #define LSDMA_PGFSM_READ__VALUE_MASK 0x00FFFFFFL 318*81570d6dSHawking Zhang //LSDMA_PIO_STATUS 319*81570d6dSHawking Zhang #define LSDMA_PIO_STATUS__CMD_IN_FIFO__SHIFT 0x0 320*81570d6dSHawking Zhang #define LSDMA_PIO_STATUS__CMD_PROCESSING__SHIFT 0x3 321*81570d6dSHawking Zhang #define LSDMA_PIO_STATUS__ERROR_VM_HOLE__SHIFT 0x8 322*81570d6dSHawking Zhang #define LSDMA_PIO_STATUS__ERROR_ZERO_COUNT__SHIFT 0x9 323*81570d6dSHawking Zhang #define LSDMA_PIO_STATUS__ERROR_DRAM_ECC__SHIFT 0xa 324*81570d6dSHawking Zhang #define LSDMA_PIO_STATUS__ERROR_SRAM_ECC__SHIFT 0xb 325*81570d6dSHawking Zhang #define LSDMA_PIO_STATUS__ERROR_WRRET_NACK_GEN_ERR__SHIFT 0xf 326*81570d6dSHawking Zhang #define LSDMA_PIO_STATUS__ERROR_RDRET_NACK_GEN_ERR__SHIFT 0x10 327*81570d6dSHawking Zhang #define LSDMA_PIO_STATUS__ERROR_WRRET_NACK_PRT__SHIFT 0x11 328*81570d6dSHawking Zhang #define LSDMA_PIO_STATUS__ERROR_RDRET_NACK_PRT__SHIFT 0x12 329*81570d6dSHawking Zhang #define LSDMA_PIO_STATUS__PIO_FIFO_EMPTY__SHIFT 0x1c 330*81570d6dSHawking Zhang #define LSDMA_PIO_STATUS__PIO_FIFO_FULL__SHIFT 0x1d 331*81570d6dSHawking Zhang #define LSDMA_PIO_STATUS__PIO_IDLE__SHIFT 0x1f 332*81570d6dSHawking Zhang #define LSDMA_PIO_STATUS__CMD_IN_FIFO_MASK 0x00000007L 333*81570d6dSHawking Zhang #define LSDMA_PIO_STATUS__CMD_PROCESSING_MASK 0x000000F8L 334*81570d6dSHawking Zhang #define LSDMA_PIO_STATUS__ERROR_VM_HOLE_MASK 0x00000100L 335*81570d6dSHawking Zhang #define LSDMA_PIO_STATUS__ERROR_ZERO_COUNT_MASK 0x00000200L 336*81570d6dSHawking Zhang #define LSDMA_PIO_STATUS__ERROR_DRAM_ECC_MASK 0x00000400L 337*81570d6dSHawking Zhang #define LSDMA_PIO_STATUS__ERROR_SRAM_ECC_MASK 0x00000800L 338*81570d6dSHawking Zhang #define LSDMA_PIO_STATUS__ERROR_WRRET_NACK_GEN_ERR_MASK 0x00008000L 339*81570d6dSHawking Zhang #define LSDMA_PIO_STATUS__ERROR_RDRET_NACK_GEN_ERR_MASK 0x00010000L 340*81570d6dSHawking Zhang #define LSDMA_PIO_STATUS__ERROR_WRRET_NACK_PRT_MASK 0x00020000L 341*81570d6dSHawking Zhang #define LSDMA_PIO_STATUS__ERROR_RDRET_NACK_PRT_MASK 0x00040000L 342*81570d6dSHawking Zhang #define LSDMA_PIO_STATUS__PIO_FIFO_EMPTY_MASK 0x10000000L 343*81570d6dSHawking Zhang #define LSDMA_PIO_STATUS__PIO_FIFO_FULL_MASK 0x20000000L 344*81570d6dSHawking Zhang #define LSDMA_PIO_STATUS__PIO_IDLE_MASK 0x80000000L 345*81570d6dSHawking Zhang //LSDMA_BA_THRESHOLD 346*81570d6dSHawking Zhang #define LSDMA_BA_THRESHOLD__READ_THRES__SHIFT 0x0 347*81570d6dSHawking Zhang #define LSDMA_BA_THRESHOLD__WRITE_THRES__SHIFT 0x10 348*81570d6dSHawking Zhang #define LSDMA_BA_THRESHOLD__READ_THRES_MASK 0x000003FFL 349*81570d6dSHawking Zhang #define LSDMA_BA_THRESHOLD__WRITE_THRES_MASK 0x03FF0000L 350*81570d6dSHawking Zhang //LSDMA_ID 351*81570d6dSHawking Zhang #define LSDMA_ID__DEVICE_ID__SHIFT 0x0 352*81570d6dSHawking Zhang #define LSDMA_ID__DEVICE_ID_MASK 0x000000FFL 353*81570d6dSHawking Zhang //LSDMA_VERSION 354*81570d6dSHawking Zhang #define LSDMA_VERSION__MINVER__SHIFT 0x0 355*81570d6dSHawking Zhang #define LSDMA_VERSION__MAJVER__SHIFT 0x8 356*81570d6dSHawking Zhang #define LSDMA_VERSION__REV__SHIFT 0x10 357*81570d6dSHawking Zhang #define LSDMA_VERSION__MINVER_MASK 0x0000007FL 358*81570d6dSHawking Zhang #define LSDMA_VERSION__MAJVER_MASK 0x00007F00L 359*81570d6dSHawking Zhang #define LSDMA_VERSION__REV_MASK 0x003F0000L 360*81570d6dSHawking Zhang //LSDMA_EDC_COUNTER 361*81570d6dSHawking Zhang #define LSDMA_EDC_COUNTER__LSDMA_MBANK_DATA_BUF0_SED__SHIFT 0x0 362*81570d6dSHawking Zhang #define LSDMA_EDC_COUNTER__LSDMA_MBANK_DATA_BUF1_SED__SHIFT 0x2 363*81570d6dSHawking Zhang #define LSDMA_EDC_COUNTER__LSDMA_MBANK_DATA_BUF2_SED__SHIFT 0x4 364*81570d6dSHawking Zhang #define LSDMA_EDC_COUNTER__LSDMA_MBANK_DATA_BUF3_SED__SHIFT 0x6 365*81570d6dSHawking Zhang #define LSDMA_EDC_COUNTER__LSDMA_MBANK_DATA_BUF4_SED__SHIFT 0x8 366*81570d6dSHawking Zhang #define LSDMA_EDC_COUNTER__LSDMA_MBANK_DATA_BUF5_SED__SHIFT 0xa 367*81570d6dSHawking Zhang #define LSDMA_EDC_COUNTER__LSDMA_MBANK_DATA_BUF6_SED__SHIFT 0xc 368*81570d6dSHawking Zhang #define LSDMA_EDC_COUNTER__LSDMA_MBANK_DATA_BUF7_SED__SHIFT 0xe 369*81570d6dSHawking Zhang #define LSDMA_EDC_COUNTER__LSDMA_MBANK_DATA_BUF8_SED__SHIFT 0x10 370*81570d6dSHawking Zhang #define LSDMA_EDC_COUNTER__LSDMA_MBANK_DATA_BUF9_SED__SHIFT 0x12 371*81570d6dSHawking Zhang #define LSDMA_EDC_COUNTER__LSDMA_MBANK_DATA_BUF10_SED__SHIFT 0x14 372*81570d6dSHawking Zhang #define LSDMA_EDC_COUNTER__LSDMA_MBANK_DATA_BUF11_SED__SHIFT 0x16 373*81570d6dSHawking Zhang #define LSDMA_EDC_COUNTER__LSDMA_MBANK_DATA_BUF12_SED__SHIFT 0x18 374*81570d6dSHawking Zhang #define LSDMA_EDC_COUNTER__LSDMA_MBANK_DATA_BUF13_SED__SHIFT 0x1a 375*81570d6dSHawking Zhang #define LSDMA_EDC_COUNTER__LSDMA_MBANK_DATA_BUF14_SED__SHIFT 0x1c 376*81570d6dSHawking Zhang #define LSDMA_EDC_COUNTER__LSDMA_MBANK_DATA_BUF15_SED__SHIFT 0x1e 377*81570d6dSHawking Zhang #define LSDMA_EDC_COUNTER__LSDMA_MBANK_DATA_BUF0_SED_MASK 0x00000003L 378*81570d6dSHawking Zhang #define LSDMA_EDC_COUNTER__LSDMA_MBANK_DATA_BUF1_SED_MASK 0x0000000CL 379*81570d6dSHawking Zhang #define LSDMA_EDC_COUNTER__LSDMA_MBANK_DATA_BUF2_SED_MASK 0x00000030L 380*81570d6dSHawking Zhang #define LSDMA_EDC_COUNTER__LSDMA_MBANK_DATA_BUF3_SED_MASK 0x000000C0L 381*81570d6dSHawking Zhang #define LSDMA_EDC_COUNTER__LSDMA_MBANK_DATA_BUF4_SED_MASK 0x00000300L 382*81570d6dSHawking Zhang #define LSDMA_EDC_COUNTER__LSDMA_MBANK_DATA_BUF5_SED_MASK 0x00000C00L 383*81570d6dSHawking Zhang #define LSDMA_EDC_COUNTER__LSDMA_MBANK_DATA_BUF6_SED_MASK 0x00003000L 384*81570d6dSHawking Zhang #define LSDMA_EDC_COUNTER__LSDMA_MBANK_DATA_BUF7_SED_MASK 0x0000C000L 385*81570d6dSHawking Zhang #define LSDMA_EDC_COUNTER__LSDMA_MBANK_DATA_BUF8_SED_MASK 0x00030000L 386*81570d6dSHawking Zhang #define LSDMA_EDC_COUNTER__LSDMA_MBANK_DATA_BUF9_SED_MASK 0x000C0000L 387*81570d6dSHawking Zhang #define LSDMA_EDC_COUNTER__LSDMA_MBANK_DATA_BUF10_SED_MASK 0x00300000L 388*81570d6dSHawking Zhang #define LSDMA_EDC_COUNTER__LSDMA_MBANK_DATA_BUF11_SED_MASK 0x00C00000L 389*81570d6dSHawking Zhang #define LSDMA_EDC_COUNTER__LSDMA_MBANK_DATA_BUF12_SED_MASK 0x03000000L 390*81570d6dSHawking Zhang #define LSDMA_EDC_COUNTER__LSDMA_MBANK_DATA_BUF13_SED_MASK 0x0C000000L 391*81570d6dSHawking Zhang #define LSDMA_EDC_COUNTER__LSDMA_MBANK_DATA_BUF14_SED_MASK 0x30000000L 392*81570d6dSHawking Zhang #define LSDMA_EDC_COUNTER__LSDMA_MBANK_DATA_BUF15_SED_MASK 0xC0000000L 393*81570d6dSHawking Zhang //LSDMA_EDC_COUNTER2 394*81570d6dSHawking Zhang #define LSDMA_EDC_COUNTER2__LSDMA_UCODE_BUF_SED__SHIFT 0x0 395*81570d6dSHawking Zhang #define LSDMA_EDC_COUNTER2__LSDMA_RB_CMD_BUF_SED__SHIFT 0x2 396*81570d6dSHawking Zhang #define LSDMA_EDC_COUNTER2__LSDMA_IB_CMD_BUF_SED__SHIFT 0x4 397*81570d6dSHawking Zhang #define LSDMA_EDC_COUNTER2__LSDMA_UTCL1_RD_FIFO_SED__SHIFT 0x6 398*81570d6dSHawking Zhang #define LSDMA_EDC_COUNTER2__LSDMA_UTCL1_RDBST_FIFO_SED__SHIFT 0x8 399*81570d6dSHawking Zhang #define LSDMA_EDC_COUNTER2__LSDMA_UTCL1_WR_FIFO_SED__SHIFT 0xa 400*81570d6dSHawking Zhang #define LSDMA_EDC_COUNTER2__LSDMA_DATA_LUT_FIFO_SED__SHIFT 0xc 401*81570d6dSHawking Zhang #define LSDMA_EDC_COUNTER2__LSDMA_SPLIT_DATA_BUF_SED__SHIFT 0xe 402*81570d6dSHawking Zhang #define LSDMA_EDC_COUNTER2__LSDMA_MC_WR_ADDR_FIFO_SED__SHIFT 0x10 403*81570d6dSHawking Zhang #define LSDMA_EDC_COUNTER2__LSDMA_MC_RDRET_BUF_SED__SHIFT 0x12 404*81570d6dSHawking Zhang #define LSDMA_EDC_COUNTER2__LSDMA_UCODE_BUF_SED_MASK 0x00000003L 405*81570d6dSHawking Zhang #define LSDMA_EDC_COUNTER2__LSDMA_RB_CMD_BUF_SED_MASK 0x0000000CL 406*81570d6dSHawking Zhang #define LSDMA_EDC_COUNTER2__LSDMA_IB_CMD_BUF_SED_MASK 0x00000030L 407*81570d6dSHawking Zhang #define LSDMA_EDC_COUNTER2__LSDMA_UTCL1_RD_FIFO_SED_MASK 0x000000C0L 408*81570d6dSHawking Zhang #define LSDMA_EDC_COUNTER2__LSDMA_UTCL1_RDBST_FIFO_SED_MASK 0x00000300L 409*81570d6dSHawking Zhang #define LSDMA_EDC_COUNTER2__LSDMA_UTCL1_WR_FIFO_SED_MASK 0x00000C00L 410*81570d6dSHawking Zhang #define LSDMA_EDC_COUNTER2__LSDMA_DATA_LUT_FIFO_SED_MASK 0x00003000L 411*81570d6dSHawking Zhang #define LSDMA_EDC_COUNTER2__LSDMA_SPLIT_DATA_BUF_SED_MASK 0x0000C000L 412*81570d6dSHawking Zhang #define LSDMA_EDC_COUNTER2__LSDMA_MC_WR_ADDR_FIFO_SED_MASK 0x00030000L 413*81570d6dSHawking Zhang #define LSDMA_EDC_COUNTER2__LSDMA_MC_RDRET_BUF_SED_MASK 0x000C0000L 414*81570d6dSHawking Zhang //LSDMA_STATUS2_REG 415*81570d6dSHawking Zhang #define LSDMA_STATUS2_REG__ID__SHIFT 0x0 416*81570d6dSHawking Zhang #define LSDMA_STATUS2_REG__F32_INSTR_PTR__SHIFT 0x3 417*81570d6dSHawking Zhang #define LSDMA_STATUS2_REG__CMD_OP__SHIFT 0x10 418*81570d6dSHawking Zhang #define LSDMA_STATUS2_REG__ID_MASK 0x00000007L 419*81570d6dSHawking Zhang #define LSDMA_STATUS2_REG__F32_INSTR_PTR_MASK 0x0000FFF8L 420*81570d6dSHawking Zhang #define LSDMA_STATUS2_REG__CMD_OP_MASK 0xFFFF0000L 421*81570d6dSHawking Zhang //LSDMA_ATOMIC_CNTL 422*81570d6dSHawking Zhang #define LSDMA_ATOMIC_CNTL__LOOP_TIMER__SHIFT 0x0 423*81570d6dSHawking Zhang #define LSDMA_ATOMIC_CNTL__LOOP_TIMER_MASK 0x7FFFFFFFL 424*81570d6dSHawking Zhang //LSDMA_ATOMIC_PREOP_LO 425*81570d6dSHawking Zhang #define LSDMA_ATOMIC_PREOP_LO__DATA__SHIFT 0x0 426*81570d6dSHawking Zhang #define LSDMA_ATOMIC_PREOP_LO__DATA_MASK 0xFFFFFFFFL 427*81570d6dSHawking Zhang //LSDMA_ATOMIC_PREOP_HI 428*81570d6dSHawking Zhang #define LSDMA_ATOMIC_PREOP_HI__DATA__SHIFT 0x0 429*81570d6dSHawking Zhang #define LSDMA_ATOMIC_PREOP_HI__DATA_MASK 0xFFFFFFFFL 430*81570d6dSHawking Zhang //LSDMA_UTCL1_CNTL 431*81570d6dSHawking Zhang #define LSDMA_UTCL1_CNTL__REDO_ENABLE__SHIFT 0x0 432*81570d6dSHawking Zhang #define LSDMA_UTCL1_CNTL__REDO_DELAY__SHIFT 0x1 433*81570d6dSHawking Zhang #define LSDMA_UTCL1_CNTL__REDO_WATERMK__SHIFT 0xb 434*81570d6dSHawking Zhang #define LSDMA_UTCL1_CNTL__INVACK_DELAY__SHIFT 0xe 435*81570d6dSHawking Zhang #define LSDMA_UTCL1_CNTL__REQL2_CREDIT__SHIFT 0x18 436*81570d6dSHawking Zhang #define LSDMA_UTCL1_CNTL__VADDR_WATERMK__SHIFT 0x1d 437*81570d6dSHawking Zhang #define LSDMA_UTCL1_CNTL__REDO_ENABLE_MASK 0x00000001L 438*81570d6dSHawking Zhang #define LSDMA_UTCL1_CNTL__REDO_DELAY_MASK 0x000007FEL 439*81570d6dSHawking Zhang #define LSDMA_UTCL1_CNTL__REDO_WATERMK_MASK 0x00003800L 440*81570d6dSHawking Zhang #define LSDMA_UTCL1_CNTL__INVACK_DELAY_MASK 0x00FFC000L 441*81570d6dSHawking Zhang #define LSDMA_UTCL1_CNTL__REQL2_CREDIT_MASK 0x1F000000L 442*81570d6dSHawking Zhang #define LSDMA_UTCL1_CNTL__VADDR_WATERMK_MASK 0xE0000000L 443*81570d6dSHawking Zhang //LSDMA_UTCL1_WATERMK 444*81570d6dSHawking Zhang #define LSDMA_UTCL1_WATERMK__REQ_WATERMK__SHIFT 0x0 445*81570d6dSHawking Zhang #define LSDMA_UTCL1_WATERMK__REQ_DEPTH__SHIFT 0x3 446*81570d6dSHawking Zhang #define LSDMA_UTCL1_WATERMK__PAGE_WATERMK__SHIFT 0x5 447*81570d6dSHawking Zhang #define LSDMA_UTCL1_WATERMK__INVREQ_WATERMK__SHIFT 0x8 448*81570d6dSHawking Zhang #define LSDMA_UTCL1_WATERMK__RESERVED__SHIFT 0x10 449*81570d6dSHawking Zhang #define LSDMA_UTCL1_WATERMK__REQ_WATERMK_MASK 0x00000007L 450*81570d6dSHawking Zhang #define LSDMA_UTCL1_WATERMK__REQ_DEPTH_MASK 0x00000018L 451*81570d6dSHawking Zhang #define LSDMA_UTCL1_WATERMK__PAGE_WATERMK_MASK 0x000000E0L 452*81570d6dSHawking Zhang #define LSDMA_UTCL1_WATERMK__INVREQ_WATERMK_MASK 0x0000FF00L 453*81570d6dSHawking Zhang #define LSDMA_UTCL1_WATERMK__RESERVED_MASK 0xFFFF0000L 454*81570d6dSHawking Zhang //LSDMA_UTCL1_RD_STATUS 455*81570d6dSHawking Zhang #define LSDMA_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_EMPTY__SHIFT 0x0 456*81570d6dSHawking Zhang #define LSDMA_UTCL1_RD_STATUS__RQMC_REQ_FIFO_EMPTY__SHIFT 0x1 457*81570d6dSHawking Zhang #define LSDMA_UTCL1_RD_STATUS__RTPG_RET_BUF_EMPTY__SHIFT 0x2 458*81570d6dSHawking Zhang #define LSDMA_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_EMPTY__SHIFT 0x3 459*81570d6dSHawking Zhang #define LSDMA_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY__SHIFT 0x4 460*81570d6dSHawking Zhang #define LSDMA_UTCL1_RD_STATUS__RQPG_REDO_FIFO_EMPTY__SHIFT 0x5 461*81570d6dSHawking Zhang #define LSDMA_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_EMPTY__SHIFT 0x6 462*81570d6dSHawking Zhang #define LSDMA_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_EMPTY__SHIFT 0x7 463*81570d6dSHawking Zhang #define LSDMA_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_EMPTY__SHIFT 0x8 464*81570d6dSHawking Zhang #define LSDMA_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_FULL__SHIFT 0x9 465*81570d6dSHawking Zhang #define LSDMA_UTCL1_RD_STATUS__RQMC_REQ_FIFO_FULL__SHIFT 0xa 466*81570d6dSHawking Zhang #define LSDMA_UTCL1_RD_STATUS__RTPG_RET_BUF_FULL__SHIFT 0xb 467*81570d6dSHawking Zhang #define LSDMA_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_FULL__SHIFT 0xc 468*81570d6dSHawking Zhang #define LSDMA_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_FULL__SHIFT 0xd 469*81570d6dSHawking Zhang #define LSDMA_UTCL1_RD_STATUS__RQPG_REDO_FIFO_FULL__SHIFT 0xe 470*81570d6dSHawking Zhang #define LSDMA_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_FULL__SHIFT 0xf 471*81570d6dSHawking Zhang #define LSDMA_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_FULL__SHIFT 0x10 472*81570d6dSHawking Zhang #define LSDMA_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_FULL__SHIFT 0x11 473*81570d6dSHawking Zhang #define LSDMA_UTCL1_RD_STATUS__PAGE_FAULT__SHIFT 0x12 474*81570d6dSHawking Zhang #define LSDMA_UTCL1_RD_STATUS__PAGE_NULL__SHIFT 0x13 475*81570d6dSHawking Zhang #define LSDMA_UTCL1_RD_STATUS__REQL2_IDLE__SHIFT 0x14 476*81570d6dSHawking Zhang #define LSDMA_UTCL1_RD_STATUS__CE_L1_STALL__SHIFT 0x15 477*81570d6dSHawking Zhang #define LSDMA_UTCL1_RD_STATUS__NEXT_RD_VECTOR__SHIFT 0x16 478*81570d6dSHawking Zhang #define LSDMA_UTCL1_RD_STATUS__MERGE_STATE__SHIFT 0x1a 479*81570d6dSHawking Zhang #define LSDMA_UTCL1_RD_STATUS__ADDR_RD_RTR__SHIFT 0x1d 480*81570d6dSHawking Zhang #define LSDMA_UTCL1_RD_STATUS__WPTR_POLLING__SHIFT 0x1e 481*81570d6dSHawking Zhang #define LSDMA_UTCL1_RD_STATUS__INVREQ_SIZE__SHIFT 0x1f 482*81570d6dSHawking Zhang #define LSDMA_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_EMPTY_MASK 0x00000001L 483*81570d6dSHawking Zhang #define LSDMA_UTCL1_RD_STATUS__RQMC_REQ_FIFO_EMPTY_MASK 0x00000002L 484*81570d6dSHawking Zhang #define LSDMA_UTCL1_RD_STATUS__RTPG_RET_BUF_EMPTY_MASK 0x00000004L 485*81570d6dSHawking Zhang #define LSDMA_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_EMPTY_MASK 0x00000008L 486*81570d6dSHawking Zhang #define LSDMA_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY_MASK 0x00000010L 487*81570d6dSHawking Zhang #define LSDMA_UTCL1_RD_STATUS__RQPG_REDO_FIFO_EMPTY_MASK 0x00000020L 488*81570d6dSHawking Zhang #define LSDMA_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_EMPTY_MASK 0x00000040L 489*81570d6dSHawking Zhang #define LSDMA_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_EMPTY_MASK 0x00000080L 490*81570d6dSHawking Zhang #define LSDMA_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_EMPTY_MASK 0x00000100L 491*81570d6dSHawking Zhang #define LSDMA_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_FULL_MASK 0x00000200L 492*81570d6dSHawking Zhang #define LSDMA_UTCL1_RD_STATUS__RQMC_REQ_FIFO_FULL_MASK 0x00000400L 493*81570d6dSHawking Zhang #define LSDMA_UTCL1_RD_STATUS__RTPG_RET_BUF_FULL_MASK 0x00000800L 494*81570d6dSHawking Zhang #define LSDMA_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_FULL_MASK 0x00001000L 495*81570d6dSHawking Zhang #define LSDMA_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_FULL_MASK 0x00002000L 496*81570d6dSHawking Zhang #define LSDMA_UTCL1_RD_STATUS__RQPG_REDO_FIFO_FULL_MASK 0x00004000L 497*81570d6dSHawking Zhang #define LSDMA_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_FULL_MASK 0x00008000L 498*81570d6dSHawking Zhang #define LSDMA_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_FULL_MASK 0x00010000L 499*81570d6dSHawking Zhang #define LSDMA_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_FULL_MASK 0x00020000L 500*81570d6dSHawking Zhang #define LSDMA_UTCL1_RD_STATUS__PAGE_FAULT_MASK 0x00040000L 501*81570d6dSHawking Zhang #define LSDMA_UTCL1_RD_STATUS__PAGE_NULL_MASK 0x00080000L 502*81570d6dSHawking Zhang #define LSDMA_UTCL1_RD_STATUS__REQL2_IDLE_MASK 0x00100000L 503*81570d6dSHawking Zhang #define LSDMA_UTCL1_RD_STATUS__CE_L1_STALL_MASK 0x00200000L 504*81570d6dSHawking Zhang #define LSDMA_UTCL1_RD_STATUS__NEXT_RD_VECTOR_MASK 0x03C00000L 505*81570d6dSHawking Zhang #define LSDMA_UTCL1_RD_STATUS__MERGE_STATE_MASK 0x1C000000L 506*81570d6dSHawking Zhang #define LSDMA_UTCL1_RD_STATUS__ADDR_RD_RTR_MASK 0x20000000L 507*81570d6dSHawking Zhang #define LSDMA_UTCL1_RD_STATUS__WPTR_POLLING_MASK 0x40000000L 508*81570d6dSHawking Zhang #define LSDMA_UTCL1_RD_STATUS__INVREQ_SIZE_MASK 0x80000000L 509*81570d6dSHawking Zhang //LSDMA_UTCL1_WR_STATUS 510*81570d6dSHawking Zhang #define LSDMA_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_EMPTY__SHIFT 0x0 511*81570d6dSHawking Zhang #define LSDMA_UTCL1_WR_STATUS__RQMC_REQ_FIFO_EMPTY__SHIFT 0x1 512*81570d6dSHawking Zhang #define LSDMA_UTCL1_WR_STATUS__RTPG_RET_BUF_EMPTY__SHIFT 0x2 513*81570d6dSHawking Zhang #define LSDMA_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_EMPTY__SHIFT 0x3 514*81570d6dSHawking Zhang #define LSDMA_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY__SHIFT 0x4 515*81570d6dSHawking Zhang #define LSDMA_UTCL1_WR_STATUS__RQPG_REDO_FIFO_EMPTY__SHIFT 0x5 516*81570d6dSHawking Zhang #define LSDMA_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_EMPTY__SHIFT 0x6 517*81570d6dSHawking Zhang #define LSDMA_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_EMPTY__SHIFT 0x7 518*81570d6dSHawking Zhang #define LSDMA_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_EMPTY__SHIFT 0x8 519*81570d6dSHawking Zhang #define LSDMA_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_FULL__SHIFT 0x9 520*81570d6dSHawking Zhang #define LSDMA_UTCL1_WR_STATUS__RQMC_REQ_FIFO_FULL__SHIFT 0xa 521*81570d6dSHawking Zhang #define LSDMA_UTCL1_WR_STATUS__RTPG_RET_BUF_FULL__SHIFT 0xb 522*81570d6dSHawking Zhang #define LSDMA_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_FULL__SHIFT 0xc 523*81570d6dSHawking Zhang #define LSDMA_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_FULL__SHIFT 0xd 524*81570d6dSHawking Zhang #define LSDMA_UTCL1_WR_STATUS__RQPG_REDO_FIFO_FULL__SHIFT 0xe 525*81570d6dSHawking Zhang #define LSDMA_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_FULL__SHIFT 0xf 526*81570d6dSHawking Zhang #define LSDMA_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_FULL__SHIFT 0x10 527*81570d6dSHawking Zhang #define LSDMA_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_FULL__SHIFT 0x11 528*81570d6dSHawking Zhang #define LSDMA_UTCL1_WR_STATUS__PAGE_FAULT__SHIFT 0x12 529*81570d6dSHawking Zhang #define LSDMA_UTCL1_WR_STATUS__PAGE_NULL__SHIFT 0x13 530*81570d6dSHawking Zhang #define LSDMA_UTCL1_WR_STATUS__REQL2_IDLE__SHIFT 0x14 531*81570d6dSHawking Zhang #define LSDMA_UTCL1_WR_STATUS__F32_WR_RTR__SHIFT 0x15 532*81570d6dSHawking Zhang #define LSDMA_UTCL1_WR_STATUS__NEXT_WR_VECTOR__SHIFT 0x16 533*81570d6dSHawking Zhang #define LSDMA_UTCL1_WR_STATUS__MERGE_STATE__SHIFT 0x19 534*81570d6dSHawking Zhang #define LSDMA_UTCL1_WR_STATUS__RPTR_DATA_FIFO_EMPTY__SHIFT 0x1c 535*81570d6dSHawking Zhang #define LSDMA_UTCL1_WR_STATUS__RPTR_DATA_FIFO_FULL__SHIFT 0x1d 536*81570d6dSHawking Zhang #define LSDMA_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_EMPTY__SHIFT 0x1e 537*81570d6dSHawking Zhang #define LSDMA_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_FULL__SHIFT 0x1f 538*81570d6dSHawking Zhang #define LSDMA_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_EMPTY_MASK 0x00000001L 539*81570d6dSHawking Zhang #define LSDMA_UTCL1_WR_STATUS__RQMC_REQ_FIFO_EMPTY_MASK 0x00000002L 540*81570d6dSHawking Zhang #define LSDMA_UTCL1_WR_STATUS__RTPG_RET_BUF_EMPTY_MASK 0x00000004L 541*81570d6dSHawking Zhang #define LSDMA_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_EMPTY_MASK 0x00000008L 542*81570d6dSHawking Zhang #define LSDMA_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY_MASK 0x00000010L 543*81570d6dSHawking Zhang #define LSDMA_UTCL1_WR_STATUS__RQPG_REDO_FIFO_EMPTY_MASK 0x00000020L 544*81570d6dSHawking Zhang #define LSDMA_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_EMPTY_MASK 0x00000040L 545*81570d6dSHawking Zhang #define LSDMA_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_EMPTY_MASK 0x00000080L 546*81570d6dSHawking Zhang #define LSDMA_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_EMPTY_MASK 0x00000100L 547*81570d6dSHawking Zhang #define LSDMA_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_FULL_MASK 0x00000200L 548*81570d6dSHawking Zhang #define LSDMA_UTCL1_WR_STATUS__RQMC_REQ_FIFO_FULL_MASK 0x00000400L 549*81570d6dSHawking Zhang #define LSDMA_UTCL1_WR_STATUS__RTPG_RET_BUF_FULL_MASK 0x00000800L 550*81570d6dSHawking Zhang #define LSDMA_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_FULL_MASK 0x00001000L 551*81570d6dSHawking Zhang #define LSDMA_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_FULL_MASK 0x00002000L 552*81570d6dSHawking Zhang #define LSDMA_UTCL1_WR_STATUS__RQPG_REDO_FIFO_FULL_MASK 0x00004000L 553*81570d6dSHawking Zhang #define LSDMA_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_FULL_MASK 0x00008000L 554*81570d6dSHawking Zhang #define LSDMA_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_FULL_MASK 0x00010000L 555*81570d6dSHawking Zhang #define LSDMA_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_FULL_MASK 0x00020000L 556*81570d6dSHawking Zhang #define LSDMA_UTCL1_WR_STATUS__PAGE_FAULT_MASK 0x00040000L 557*81570d6dSHawking Zhang #define LSDMA_UTCL1_WR_STATUS__PAGE_NULL_MASK 0x00080000L 558*81570d6dSHawking Zhang #define LSDMA_UTCL1_WR_STATUS__REQL2_IDLE_MASK 0x00100000L 559*81570d6dSHawking Zhang #define LSDMA_UTCL1_WR_STATUS__F32_WR_RTR_MASK 0x00200000L 560*81570d6dSHawking Zhang #define LSDMA_UTCL1_WR_STATUS__NEXT_WR_VECTOR_MASK 0x01C00000L 561*81570d6dSHawking Zhang #define LSDMA_UTCL1_WR_STATUS__MERGE_STATE_MASK 0x0E000000L 562*81570d6dSHawking Zhang #define LSDMA_UTCL1_WR_STATUS__RPTR_DATA_FIFO_EMPTY_MASK 0x10000000L 563*81570d6dSHawking Zhang #define LSDMA_UTCL1_WR_STATUS__RPTR_DATA_FIFO_FULL_MASK 0x20000000L 564*81570d6dSHawking Zhang #define LSDMA_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_EMPTY_MASK 0x40000000L 565*81570d6dSHawking Zhang #define LSDMA_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_FULL_MASK 0x80000000L 566*81570d6dSHawking Zhang //LSDMA_UTCL1_INV0 567*81570d6dSHawking Zhang #define LSDMA_UTCL1_INV0__INV_MIDDLE__SHIFT 0x0 568*81570d6dSHawking Zhang #define LSDMA_UTCL1_INV0__RD_TIMEOUT__SHIFT 0x1 569*81570d6dSHawking Zhang #define LSDMA_UTCL1_INV0__WR_TIMEOUT__SHIFT 0x2 570*81570d6dSHawking Zhang #define LSDMA_UTCL1_INV0__RD_IN_INVADR__SHIFT 0x3 571*81570d6dSHawking Zhang #define LSDMA_UTCL1_INV0__WR_IN_INVADR__SHIFT 0x4 572*81570d6dSHawking Zhang #define LSDMA_UTCL1_INV0__PAGE_NULL_SW__SHIFT 0x5 573*81570d6dSHawking Zhang #define LSDMA_UTCL1_INV0__XNACK_IS_INVADR__SHIFT 0x6 574*81570d6dSHawking Zhang #define LSDMA_UTCL1_INV0__INVREQ_ENABLE__SHIFT 0x7 575*81570d6dSHawking Zhang #define LSDMA_UTCL1_INV0__NACK_TIMEOUT_SW__SHIFT 0x8 576*81570d6dSHawking Zhang #define LSDMA_UTCL1_INV0__NFLUSH_INV_IDLE__SHIFT 0x9 577*81570d6dSHawking Zhang #define LSDMA_UTCL1_INV0__FLUSH_INV_IDLE__SHIFT 0xa 578*81570d6dSHawking Zhang #define LSDMA_UTCL1_INV0__INV_FLUSHTYPE__SHIFT 0xb 579*81570d6dSHawking Zhang #define LSDMA_UTCL1_INV0__INV_VMID_VEC__SHIFT 0xc 580*81570d6dSHawking Zhang #define LSDMA_UTCL1_INV0__INV_ADDR_HI__SHIFT 0x1c 581*81570d6dSHawking Zhang #define LSDMA_UTCL1_INV0__INV_MIDDLE_MASK 0x00000001L 582*81570d6dSHawking Zhang #define LSDMA_UTCL1_INV0__RD_TIMEOUT_MASK 0x00000002L 583*81570d6dSHawking Zhang #define LSDMA_UTCL1_INV0__WR_TIMEOUT_MASK 0x00000004L 584*81570d6dSHawking Zhang #define LSDMA_UTCL1_INV0__RD_IN_INVADR_MASK 0x00000008L 585*81570d6dSHawking Zhang #define LSDMA_UTCL1_INV0__WR_IN_INVADR_MASK 0x00000010L 586*81570d6dSHawking Zhang #define LSDMA_UTCL1_INV0__PAGE_NULL_SW_MASK 0x00000020L 587*81570d6dSHawking Zhang #define LSDMA_UTCL1_INV0__XNACK_IS_INVADR_MASK 0x00000040L 588*81570d6dSHawking Zhang #define LSDMA_UTCL1_INV0__INVREQ_ENABLE_MASK 0x00000080L 589*81570d6dSHawking Zhang #define LSDMA_UTCL1_INV0__NACK_TIMEOUT_SW_MASK 0x00000100L 590*81570d6dSHawking Zhang #define LSDMA_UTCL1_INV0__NFLUSH_INV_IDLE_MASK 0x00000200L 591*81570d6dSHawking Zhang #define LSDMA_UTCL1_INV0__FLUSH_INV_IDLE_MASK 0x00000400L 592*81570d6dSHawking Zhang #define LSDMA_UTCL1_INV0__INV_FLUSHTYPE_MASK 0x00000800L 593*81570d6dSHawking Zhang #define LSDMA_UTCL1_INV0__INV_VMID_VEC_MASK 0x0FFFF000L 594*81570d6dSHawking Zhang #define LSDMA_UTCL1_INV0__INV_ADDR_HI_MASK 0xF0000000L 595*81570d6dSHawking Zhang //LSDMA_UTCL1_INV1 596*81570d6dSHawking Zhang #define LSDMA_UTCL1_INV1__INV_ADDR_LO__SHIFT 0x0 597*81570d6dSHawking Zhang #define LSDMA_UTCL1_INV1__INV_ADDR_LO_MASK 0xFFFFFFFFL 598*81570d6dSHawking Zhang //LSDMA_UTCL1_INV2 599*81570d6dSHawking Zhang #define LSDMA_UTCL1_INV2__INV_NFLUSH_VMID_VEC__SHIFT 0x0 600*81570d6dSHawking Zhang #define LSDMA_UTCL1_INV2__INV_NFLUSH_VMID_VEC_MASK 0xFFFFFFFFL 601*81570d6dSHawking Zhang //LSDMA_UTCL1_RD_XNACK0 602*81570d6dSHawking Zhang #define LSDMA_UTCL1_RD_XNACK0__XNACK_ADDR_LO__SHIFT 0x0 603*81570d6dSHawking Zhang #define LSDMA_UTCL1_RD_XNACK0__XNACK_ADDR_LO_MASK 0xFFFFFFFFL 604*81570d6dSHawking Zhang //LSDMA_UTCL1_RD_XNACK1 605*81570d6dSHawking Zhang #define LSDMA_UTCL1_RD_XNACK1__XNACK_ADDR_HI__SHIFT 0x0 606*81570d6dSHawking Zhang #define LSDMA_UTCL1_RD_XNACK1__XNACK_VMID__SHIFT 0x4 607*81570d6dSHawking Zhang #define LSDMA_UTCL1_RD_XNACK1__XNACK_VECTOR__SHIFT 0x8 608*81570d6dSHawking Zhang #define LSDMA_UTCL1_RD_XNACK1__IS_XNACK__SHIFT 0x1a 609*81570d6dSHawking Zhang #define LSDMA_UTCL1_RD_XNACK1__XNACK_ADDR_HI_MASK 0x0000000FL 610*81570d6dSHawking Zhang #define LSDMA_UTCL1_RD_XNACK1__XNACK_VMID_MASK 0x000000F0L 611*81570d6dSHawking Zhang #define LSDMA_UTCL1_RD_XNACK1__XNACK_VECTOR_MASK 0x03FFFF00L 612*81570d6dSHawking Zhang #define LSDMA_UTCL1_RD_XNACK1__IS_XNACK_MASK 0x0C000000L 613*81570d6dSHawking Zhang //LSDMA_UTCL1_WR_XNACK0 614*81570d6dSHawking Zhang #define LSDMA_UTCL1_WR_XNACK0__XNACK_ADDR_LO__SHIFT 0x0 615*81570d6dSHawking Zhang #define LSDMA_UTCL1_WR_XNACK0__XNACK_ADDR_LO_MASK 0xFFFFFFFFL 616*81570d6dSHawking Zhang //LSDMA_UTCL1_WR_XNACK1 617*81570d6dSHawking Zhang #define LSDMA_UTCL1_WR_XNACK1__XNACK_ADDR_HI__SHIFT 0x0 618*81570d6dSHawking Zhang #define LSDMA_UTCL1_WR_XNACK1__XNACK_VMID__SHIFT 0x4 619*81570d6dSHawking Zhang #define LSDMA_UTCL1_WR_XNACK1__XNACK_VECTOR__SHIFT 0x8 620*81570d6dSHawking Zhang #define LSDMA_UTCL1_WR_XNACK1__IS_XNACK__SHIFT 0x1a 621*81570d6dSHawking Zhang #define LSDMA_UTCL1_WR_XNACK1__XNACK_ADDR_HI_MASK 0x0000000FL 622*81570d6dSHawking Zhang #define LSDMA_UTCL1_WR_XNACK1__XNACK_VMID_MASK 0x000000F0L 623*81570d6dSHawking Zhang #define LSDMA_UTCL1_WR_XNACK1__XNACK_VECTOR_MASK 0x03FFFF00L 624*81570d6dSHawking Zhang #define LSDMA_UTCL1_WR_XNACK1__IS_XNACK_MASK 0x0C000000L 625*81570d6dSHawking Zhang //LSDMA_UTCL1_TIMEOUT 626*81570d6dSHawking Zhang #define LSDMA_UTCL1_TIMEOUT__RD_XNACK_LIMIT__SHIFT 0x0 627*81570d6dSHawking Zhang #define LSDMA_UTCL1_TIMEOUT__WR_XNACK_LIMIT__SHIFT 0x10 628*81570d6dSHawking Zhang #define LSDMA_UTCL1_TIMEOUT__RD_XNACK_LIMIT_MASK 0x0000FFFFL 629*81570d6dSHawking Zhang #define LSDMA_UTCL1_TIMEOUT__WR_XNACK_LIMIT_MASK 0xFFFF0000L 630*81570d6dSHawking Zhang //LSDMA_UTCL1_PAGE 631*81570d6dSHawking Zhang #define LSDMA_UTCL1_PAGE__VM_HOLE__SHIFT 0x0 632*81570d6dSHawking Zhang #define LSDMA_UTCL1_PAGE__REQ_TYPE__SHIFT 0x1 633*81570d6dSHawking Zhang #define LSDMA_UTCL1_PAGE__TMZ_ENABLE__SHIFT 0x5 634*81570d6dSHawking Zhang #define LSDMA_UTCL1_PAGE__USE_MTYPE__SHIFT 0x6 635*81570d6dSHawking Zhang #define LSDMA_UTCL1_PAGE__USE_PT_SNOOP__SHIFT 0x9 636*81570d6dSHawking Zhang #define LSDMA_UTCL1_PAGE__VM_HOLE_MASK 0x00000001L 637*81570d6dSHawking Zhang #define LSDMA_UTCL1_PAGE__REQ_TYPE_MASK 0x0000001EL 638*81570d6dSHawking Zhang #define LSDMA_UTCL1_PAGE__TMZ_ENABLE_MASK 0x00000020L 639*81570d6dSHawking Zhang #define LSDMA_UTCL1_PAGE__USE_MTYPE_MASK 0x000001C0L 640*81570d6dSHawking Zhang #define LSDMA_UTCL1_PAGE__USE_PT_SNOOP_MASK 0x00000200L 641*81570d6dSHawking Zhang //LSDMA_RELAX_ORDERING_LUT 642*81570d6dSHawking Zhang #define LSDMA_RELAX_ORDERING_LUT__RESERVED0__SHIFT 0x0 643*81570d6dSHawking Zhang #define LSDMA_RELAX_ORDERING_LUT__COPY__SHIFT 0x1 644*81570d6dSHawking Zhang #define LSDMA_RELAX_ORDERING_LUT__WRITE__SHIFT 0x2 645*81570d6dSHawking Zhang #define LSDMA_RELAX_ORDERING_LUT__RESERVED3__SHIFT 0x3 646*81570d6dSHawking Zhang #define LSDMA_RELAX_ORDERING_LUT__RESERVED4__SHIFT 0x4 647*81570d6dSHawking Zhang #define LSDMA_RELAX_ORDERING_LUT__FENCE__SHIFT 0x5 648*81570d6dSHawking Zhang #define LSDMA_RELAX_ORDERING_LUT__RESERVED76__SHIFT 0x6 649*81570d6dSHawking Zhang #define LSDMA_RELAX_ORDERING_LUT__POLL_MEM__SHIFT 0x8 650*81570d6dSHawking Zhang #define LSDMA_RELAX_ORDERING_LUT__COND_EXE__SHIFT 0x9 651*81570d6dSHawking Zhang #define LSDMA_RELAX_ORDERING_LUT__ATOMIC__SHIFT 0xa 652*81570d6dSHawking Zhang #define LSDMA_RELAX_ORDERING_LUT__CONST_FILL__SHIFT 0xb 653*81570d6dSHawking Zhang #define LSDMA_RELAX_ORDERING_LUT__PTEPDE__SHIFT 0xc 654*81570d6dSHawking Zhang #define LSDMA_RELAX_ORDERING_LUT__TIMESTAMP__SHIFT 0xd 655*81570d6dSHawking Zhang #define LSDMA_RELAX_ORDERING_LUT__RESERVED__SHIFT 0xe 656*81570d6dSHawking Zhang #define LSDMA_RELAX_ORDERING_LUT__WORLD_SWITCH__SHIFT 0x1b 657*81570d6dSHawking Zhang #define LSDMA_RELAX_ORDERING_LUT__RPTR_WRB__SHIFT 0x1c 658*81570d6dSHawking Zhang #define LSDMA_RELAX_ORDERING_LUT__WPTR_POLL__SHIFT 0x1d 659*81570d6dSHawking Zhang #define LSDMA_RELAX_ORDERING_LUT__IB_FETCH__SHIFT 0x1e 660*81570d6dSHawking Zhang #define LSDMA_RELAX_ORDERING_LUT__RB_FETCH__SHIFT 0x1f 661*81570d6dSHawking Zhang #define LSDMA_RELAX_ORDERING_LUT__RESERVED0_MASK 0x00000001L 662*81570d6dSHawking Zhang #define LSDMA_RELAX_ORDERING_LUT__COPY_MASK 0x00000002L 663*81570d6dSHawking Zhang #define LSDMA_RELAX_ORDERING_LUT__WRITE_MASK 0x00000004L 664*81570d6dSHawking Zhang #define LSDMA_RELAX_ORDERING_LUT__RESERVED3_MASK 0x00000008L 665*81570d6dSHawking Zhang #define LSDMA_RELAX_ORDERING_LUT__RESERVED4_MASK 0x00000010L 666*81570d6dSHawking Zhang #define LSDMA_RELAX_ORDERING_LUT__FENCE_MASK 0x00000020L 667*81570d6dSHawking Zhang #define LSDMA_RELAX_ORDERING_LUT__RESERVED76_MASK 0x000000C0L 668*81570d6dSHawking Zhang #define LSDMA_RELAX_ORDERING_LUT__POLL_MEM_MASK 0x00000100L 669*81570d6dSHawking Zhang #define LSDMA_RELAX_ORDERING_LUT__COND_EXE_MASK 0x00000200L 670*81570d6dSHawking Zhang #define LSDMA_RELAX_ORDERING_LUT__ATOMIC_MASK 0x00000400L 671*81570d6dSHawking Zhang #define LSDMA_RELAX_ORDERING_LUT__CONST_FILL_MASK 0x00000800L 672*81570d6dSHawking Zhang #define LSDMA_RELAX_ORDERING_LUT__PTEPDE_MASK 0x00001000L 673*81570d6dSHawking Zhang #define LSDMA_RELAX_ORDERING_LUT__TIMESTAMP_MASK 0x00002000L 674*81570d6dSHawking Zhang #define LSDMA_RELAX_ORDERING_LUT__RESERVED_MASK 0x07FFC000L 675*81570d6dSHawking Zhang #define LSDMA_RELAX_ORDERING_LUT__WORLD_SWITCH_MASK 0x08000000L 676*81570d6dSHawking Zhang #define LSDMA_RELAX_ORDERING_LUT__RPTR_WRB_MASK 0x10000000L 677*81570d6dSHawking Zhang #define LSDMA_RELAX_ORDERING_LUT__WPTR_POLL_MASK 0x20000000L 678*81570d6dSHawking Zhang #define LSDMA_RELAX_ORDERING_LUT__IB_FETCH_MASK 0x40000000L 679*81570d6dSHawking Zhang #define LSDMA_RELAX_ORDERING_LUT__RB_FETCH_MASK 0x80000000L 680*81570d6dSHawking Zhang //LSDMA_CHICKEN_BITS_2 681*81570d6dSHawking Zhang #define LSDMA_CHICKEN_BITS_2__F32_CMD_PROC_DELAY__SHIFT 0x0 682*81570d6dSHawking Zhang #define LSDMA_CHICKEN_BITS_2__F32_SEND_POSTCODE_EN__SHIFT 0x4 683*81570d6dSHawking Zhang #define LSDMA_CHICKEN_BITS_2__F32_CMD_PROC_DELAY_MASK 0x0000000FL 684*81570d6dSHawking Zhang #define LSDMA_CHICKEN_BITS_2__F32_SEND_POSTCODE_EN_MASK 0x00000010L 685*81570d6dSHawking Zhang //LSDMA_STATUS3_REG 686*81570d6dSHawking Zhang #define LSDMA_STATUS3_REG__CMD_OP_STATUS__SHIFT 0x0 687*81570d6dSHawking Zhang #define LSDMA_STATUS3_REG__PREV_VM_CMD__SHIFT 0x10 688*81570d6dSHawking Zhang #define LSDMA_STATUS3_REG__EXCEPTION_IDLE__SHIFT 0x14 689*81570d6dSHawking Zhang #define LSDMA_STATUS3_REG__QUEUE_ID_MATCH__SHIFT 0x15 690*81570d6dSHawking Zhang #define LSDMA_STATUS3_REG__INT_QUEUE_ID__SHIFT 0x16 691*81570d6dSHawking Zhang #define LSDMA_STATUS3_REG__CMD_OP_STATUS_MASK 0x0000FFFFL 692*81570d6dSHawking Zhang #define LSDMA_STATUS3_REG__PREV_VM_CMD_MASK 0x000F0000L 693*81570d6dSHawking Zhang #define LSDMA_STATUS3_REG__EXCEPTION_IDLE_MASK 0x00100000L 694*81570d6dSHawking Zhang #define LSDMA_STATUS3_REG__QUEUE_ID_MATCH_MASK 0x00200000L 695*81570d6dSHawking Zhang #define LSDMA_STATUS3_REG__INT_QUEUE_ID_MASK 0x03C00000L 696*81570d6dSHawking Zhang //LSDMA_PHYSICAL_ADDR_LO 697*81570d6dSHawking Zhang #define LSDMA_PHYSICAL_ADDR_LO__D_VALID__SHIFT 0x0 698*81570d6dSHawking Zhang #define LSDMA_PHYSICAL_ADDR_LO__DIRTY__SHIFT 0x1 699*81570d6dSHawking Zhang #define LSDMA_PHYSICAL_ADDR_LO__PHY_VALID__SHIFT 0x2 700*81570d6dSHawking Zhang #define LSDMA_PHYSICAL_ADDR_LO__ADDR__SHIFT 0xc 701*81570d6dSHawking Zhang #define LSDMA_PHYSICAL_ADDR_LO__D_VALID_MASK 0x00000001L 702*81570d6dSHawking Zhang #define LSDMA_PHYSICAL_ADDR_LO__DIRTY_MASK 0x00000002L 703*81570d6dSHawking Zhang #define LSDMA_PHYSICAL_ADDR_LO__PHY_VALID_MASK 0x00000004L 704*81570d6dSHawking Zhang #define LSDMA_PHYSICAL_ADDR_LO__ADDR_MASK 0xFFFFF000L 705*81570d6dSHawking Zhang //LSDMA_PHYSICAL_ADDR_HI 706*81570d6dSHawking Zhang #define LSDMA_PHYSICAL_ADDR_HI__ADDR__SHIFT 0x0 707*81570d6dSHawking Zhang #define LSDMA_PHYSICAL_ADDR_HI__ADDR_MASK 0x0000FFFFL 708*81570d6dSHawking Zhang //LSDMA_ECC_CNTL 709*81570d6dSHawking Zhang #define LSDMA_ECC_CNTL__ECC_DISABLE__SHIFT 0x0 710*81570d6dSHawking Zhang #define LSDMA_ECC_CNTL__ECC_DISABLE_MASK 0x00000001L 711*81570d6dSHawking Zhang //LSDMA_ERROR_LOG 712*81570d6dSHawking Zhang #define LSDMA_ERROR_LOG__OVERRIDE__SHIFT 0x0 713*81570d6dSHawking Zhang #define LSDMA_ERROR_LOG__STATUS__SHIFT 0x10 714*81570d6dSHawking Zhang #define LSDMA_ERROR_LOG__OVERRIDE_MASK 0x0000FFFFL 715*81570d6dSHawking Zhang #define LSDMA_ERROR_LOG__STATUS_MASK 0xFFFF0000L 716*81570d6dSHawking Zhang //LSDMA_PUB_DUMMY0 717*81570d6dSHawking Zhang #define LSDMA_PUB_DUMMY0__DUMMY__SHIFT 0x0 718*81570d6dSHawking Zhang #define LSDMA_PUB_DUMMY0__DUMMY_MASK 0xFFFFFFFFL 719*81570d6dSHawking Zhang //LSDMA_PUB_DUMMY1 720*81570d6dSHawking Zhang #define LSDMA_PUB_DUMMY1__DUMMY__SHIFT 0x0 721*81570d6dSHawking Zhang #define LSDMA_PUB_DUMMY1__DUMMY_MASK 0xFFFFFFFFL 722*81570d6dSHawking Zhang //LSDMA_PUB_DUMMY2 723*81570d6dSHawking Zhang #define LSDMA_PUB_DUMMY2__DUMMY__SHIFT 0x0 724*81570d6dSHawking Zhang #define LSDMA_PUB_DUMMY2__DUMMY_MASK 0xFFFFFFFFL 725*81570d6dSHawking Zhang //LSDMA_PUB_DUMMY3 726*81570d6dSHawking Zhang #define LSDMA_PUB_DUMMY3__DUMMY__SHIFT 0x0 727*81570d6dSHawking Zhang #define LSDMA_PUB_DUMMY3__DUMMY_MASK 0xFFFFFFFFL 728*81570d6dSHawking Zhang //LSDMA_F32_COUNTER 729*81570d6dSHawking Zhang #define LSDMA_F32_COUNTER__VALUE__SHIFT 0x0 730*81570d6dSHawking Zhang #define LSDMA_F32_COUNTER__VALUE_MASK 0xFFFFFFFFL 731*81570d6dSHawking Zhang //LSDMA_PERFCNT_PERFCOUNTER0_CFG 732*81570d6dSHawking Zhang #define LSDMA_PERFCNT_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 733*81570d6dSHawking Zhang #define LSDMA_PERFCNT_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 734*81570d6dSHawking Zhang #define LSDMA_PERFCNT_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 735*81570d6dSHawking Zhang #define LSDMA_PERFCNT_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c 736*81570d6dSHawking Zhang #define LSDMA_PERFCNT_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d 737*81570d6dSHawking Zhang #define LSDMA_PERFCNT_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL 738*81570d6dSHawking Zhang #define LSDMA_PERFCNT_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L 739*81570d6dSHawking Zhang #define LSDMA_PERFCNT_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L 740*81570d6dSHawking Zhang #define LSDMA_PERFCNT_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L 741*81570d6dSHawking Zhang #define LSDMA_PERFCNT_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L 742*81570d6dSHawking Zhang //LSDMA_PERFCNT_PERFCOUNTER1_CFG 743*81570d6dSHawking Zhang #define LSDMA_PERFCNT_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 744*81570d6dSHawking Zhang #define LSDMA_PERFCNT_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 745*81570d6dSHawking Zhang #define LSDMA_PERFCNT_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 746*81570d6dSHawking Zhang #define LSDMA_PERFCNT_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c 747*81570d6dSHawking Zhang #define LSDMA_PERFCNT_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d 748*81570d6dSHawking Zhang #define LSDMA_PERFCNT_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL 749*81570d6dSHawking Zhang #define LSDMA_PERFCNT_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L 750*81570d6dSHawking Zhang #define LSDMA_PERFCNT_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L 751*81570d6dSHawking Zhang #define LSDMA_PERFCNT_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L 752*81570d6dSHawking Zhang #define LSDMA_PERFCNT_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L 753*81570d6dSHawking Zhang //LSDMA_PERFCNT_PERFCOUNTER_RSLT_CNTL 754*81570d6dSHawking Zhang #define LSDMA_PERFCNT_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 755*81570d6dSHawking Zhang #define LSDMA_PERFCNT_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 756*81570d6dSHawking Zhang #define LSDMA_PERFCNT_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 757*81570d6dSHawking Zhang #define LSDMA_PERFCNT_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 758*81570d6dSHawking Zhang #define LSDMA_PERFCNT_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 759*81570d6dSHawking Zhang #define LSDMA_PERFCNT_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a 760*81570d6dSHawking Zhang #define LSDMA_PERFCNT_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL 761*81570d6dSHawking Zhang #define LSDMA_PERFCNT_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L 762*81570d6dSHawking Zhang #define LSDMA_PERFCNT_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L 763*81570d6dSHawking Zhang #define LSDMA_PERFCNT_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L 764*81570d6dSHawking Zhang #define LSDMA_PERFCNT_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L 765*81570d6dSHawking Zhang #define LSDMA_PERFCNT_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L 766*81570d6dSHawking Zhang //LSDMA_PERFCNT_MISC_CNTL 767*81570d6dSHawking Zhang #define LSDMA_PERFCNT_MISC_CNTL__CMD_OP__SHIFT 0x0 768*81570d6dSHawking Zhang #define LSDMA_PERFCNT_MISC_CNTL__MMHUB_REQ_EVENT_SELECT__SHIFT 0x10 769*81570d6dSHawking Zhang #define LSDMA_PERFCNT_MISC_CNTL__CMD_OP_MASK 0x0000FFFFL 770*81570d6dSHawking Zhang #define LSDMA_PERFCNT_MISC_CNTL__MMHUB_REQ_EVENT_SELECT_MASK 0x00010000L 771*81570d6dSHawking Zhang //LSDMA_PERFCNT_PERFCOUNTER_LO 772*81570d6dSHawking Zhang #define LSDMA_PERFCNT_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 773*81570d6dSHawking Zhang #define LSDMA_PERFCNT_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL 774*81570d6dSHawking Zhang //LSDMA_PERFCNT_PERFCOUNTER_HI 775*81570d6dSHawking Zhang #define LSDMA_PERFCNT_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 776*81570d6dSHawking Zhang #define LSDMA_PERFCNT_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 777*81570d6dSHawking Zhang #define LSDMA_PERFCNT_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL 778*81570d6dSHawking Zhang #define LSDMA_PERFCNT_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L 779*81570d6dSHawking Zhang //LSDMA_CRD_CNTL 780*81570d6dSHawking Zhang #define LSDMA_CRD_CNTL__MC_WRREQ_CREDIT__SHIFT 0x7 781*81570d6dSHawking Zhang #define LSDMA_CRD_CNTL__MC_RDREQ_CREDIT__SHIFT 0xd 782*81570d6dSHawking Zhang #define LSDMA_CRD_CNTL__MC_WRREQ_CREDIT_MASK 0x00001F80L 783*81570d6dSHawking Zhang #define LSDMA_CRD_CNTL__MC_RDREQ_CREDIT_MASK 0x0007E000L 784*81570d6dSHawking Zhang //LSDMA_ULV_CNTL 785*81570d6dSHawking Zhang #define LSDMA_ULV_CNTL__HYSTERESIS__SHIFT 0x0 786*81570d6dSHawking Zhang #define LSDMA_ULV_CNTL__ENTER_ULV_INT_CLR__SHIFT 0x1b 787*81570d6dSHawking Zhang #define LSDMA_ULV_CNTL__EXIT_ULV_INT_CLR__SHIFT 0x1c 788*81570d6dSHawking Zhang #define LSDMA_ULV_CNTL__ENTER_ULV_INT__SHIFT 0x1d 789*81570d6dSHawking Zhang #define LSDMA_ULV_CNTL__EXIT_ULV_INT__SHIFT 0x1e 790*81570d6dSHawking Zhang #define LSDMA_ULV_CNTL__ULV_STATUS__SHIFT 0x1f 791*81570d6dSHawking Zhang #define LSDMA_ULV_CNTL__HYSTERESIS_MASK 0x0000001FL 792*81570d6dSHawking Zhang #define LSDMA_ULV_CNTL__ENTER_ULV_INT_CLR_MASK 0x08000000L 793*81570d6dSHawking Zhang #define LSDMA_ULV_CNTL__EXIT_ULV_INT_CLR_MASK 0x10000000L 794*81570d6dSHawking Zhang #define LSDMA_ULV_CNTL__ENTER_ULV_INT_MASK 0x20000000L 795*81570d6dSHawking Zhang #define LSDMA_ULV_CNTL__EXIT_ULV_INT_MASK 0x40000000L 796*81570d6dSHawking Zhang #define LSDMA_ULV_CNTL__ULV_STATUS_MASK 0x80000000L 797*81570d6dSHawking Zhang //LSDMA_EA_DBIT_ADDR_DATA 798*81570d6dSHawking Zhang #define LSDMA_EA_DBIT_ADDR_DATA__VALUE__SHIFT 0x0 799*81570d6dSHawking Zhang #define LSDMA_EA_DBIT_ADDR_DATA__VALUE_MASK 0xFFFFFFFFL 800*81570d6dSHawking Zhang //LSDMA_EA_DBIT_ADDR_INDEX 801*81570d6dSHawking Zhang #define LSDMA_EA_DBIT_ADDR_INDEX__VALUE__SHIFT 0x0 802*81570d6dSHawking Zhang #define LSDMA_EA_DBIT_ADDR_INDEX__VALUE_MASK 0x00000007L 803*81570d6dSHawking Zhang //LSDMA_STATUS4_REG 804*81570d6dSHawking Zhang #define LSDMA_STATUS4_REG__IDLE__SHIFT 0x0 805*81570d6dSHawking Zhang #define LSDMA_STATUS4_REG__IH_OUTSTANDING__SHIFT 0x2 806*81570d6dSHawking Zhang #define LSDMA_STATUS4_REG__SEM_OUTSTANDING__SHIFT 0x3 807*81570d6dSHawking Zhang #define LSDMA_STATUS4_REG__MMHUB_RD_OUTSTANDING__SHIFT 0x4 808*81570d6dSHawking Zhang #define LSDMA_STATUS4_REG__MMHUB_WR_OUTSTANDING__SHIFT 0x5 809*81570d6dSHawking Zhang #define LSDMA_STATUS4_REG__UTCL2_RD_OUTSTANDING__SHIFT 0x6 810*81570d6dSHawking Zhang #define LSDMA_STATUS4_REG__UTCL2_WR_OUTSTANDING__SHIFT 0x7 811*81570d6dSHawking Zhang #define LSDMA_STATUS4_REG__REG_POLLING__SHIFT 0x8 812*81570d6dSHawking Zhang #define LSDMA_STATUS4_REG__MEM_POLLING__SHIFT 0x9 813*81570d6dSHawking Zhang #define LSDMA_STATUS4_REG__UTCL2_RD_XNACK__SHIFT 0xa 814*81570d6dSHawking Zhang #define LSDMA_STATUS4_REG__UTCL2_WR_XNACK__SHIFT 0xc 815*81570d6dSHawking Zhang #define LSDMA_STATUS4_REG__ACTIVE_QUEUE_ID__SHIFT 0xe 816*81570d6dSHawking Zhang #define LSDMA_STATUS4_REG__SRIOV_WATING_RLCV_CMD__SHIFT 0x12 817*81570d6dSHawking Zhang #define LSDMA_STATUS4_REG__SRIOV_LSDMA_EXECUTING_CMD__SHIFT 0x13 818*81570d6dSHawking Zhang #define LSDMA_STATUS4_REG__IDLE_MASK 0x00000001L 819*81570d6dSHawking Zhang #define LSDMA_STATUS4_REG__IH_OUTSTANDING_MASK 0x00000004L 820*81570d6dSHawking Zhang #define LSDMA_STATUS4_REG__SEM_OUTSTANDING_MASK 0x00000008L 821*81570d6dSHawking Zhang #define LSDMA_STATUS4_REG__MMHUB_RD_OUTSTANDING_MASK 0x00000010L 822*81570d6dSHawking Zhang #define LSDMA_STATUS4_REG__MMHUB_WR_OUTSTANDING_MASK 0x00000020L 823*81570d6dSHawking Zhang #define LSDMA_STATUS4_REG__UTCL2_RD_OUTSTANDING_MASK 0x00000040L 824*81570d6dSHawking Zhang #define LSDMA_STATUS4_REG__UTCL2_WR_OUTSTANDING_MASK 0x00000080L 825*81570d6dSHawking Zhang #define LSDMA_STATUS4_REG__REG_POLLING_MASK 0x00000100L 826*81570d6dSHawking Zhang #define LSDMA_STATUS4_REG__MEM_POLLING_MASK 0x00000200L 827*81570d6dSHawking Zhang #define LSDMA_STATUS4_REG__UTCL2_RD_XNACK_MASK 0x00000C00L 828*81570d6dSHawking Zhang #define LSDMA_STATUS4_REG__UTCL2_WR_XNACK_MASK 0x00003000L 829*81570d6dSHawking Zhang #define LSDMA_STATUS4_REG__ACTIVE_QUEUE_ID_MASK 0x0003C000L 830*81570d6dSHawking Zhang #define LSDMA_STATUS4_REG__SRIOV_WATING_RLCV_CMD_MASK 0x00040000L 831*81570d6dSHawking Zhang #define LSDMA_STATUS4_REG__SRIOV_LSDMA_EXECUTING_CMD_MASK 0x00080000L 832*81570d6dSHawking Zhang //LSDMA_CE_CTRL 833*81570d6dSHawking Zhang #define LSDMA_CE_CTRL__RD_LUT_WATERMARK__SHIFT 0x0 834*81570d6dSHawking Zhang #define LSDMA_CE_CTRL__RD_LUT_DEPTH__SHIFT 0x3 835*81570d6dSHawking Zhang #define LSDMA_CE_CTRL__RESERVED_7_5__SHIFT 0x5 836*81570d6dSHawking Zhang #define LSDMA_CE_CTRL__RESERVED__SHIFT 0x8 837*81570d6dSHawking Zhang #define LSDMA_CE_CTRL__RD_LUT_WATERMARK_MASK 0x00000007L 838*81570d6dSHawking Zhang #define LSDMA_CE_CTRL__RD_LUT_DEPTH_MASK 0x00000018L 839*81570d6dSHawking Zhang #define LSDMA_CE_CTRL__RESERVED_7_5_MASK 0x000000E0L 840*81570d6dSHawking Zhang #define LSDMA_CE_CTRL__RESERVED_MASK 0xFFFFFF00L 841*81570d6dSHawking Zhang //LSDMA_EXCEPTION_STATUS 842*81570d6dSHawking Zhang #define LSDMA_EXCEPTION_STATUS__RB_FETCH_ECC__SHIFT 0x0 843*81570d6dSHawking Zhang #define LSDMA_EXCEPTION_STATUS__IB_FETCH_ECC__SHIFT 0x1 844*81570d6dSHawking Zhang #define LSDMA_EXCEPTION_STATUS__COPY_CMD_ECC__SHIFT 0x2 845*81570d6dSHawking Zhang #define LSDMA_EXCEPTION_STATUS__NON_COPY_CMD_ECC__SHIFT 0x3 846*81570d6dSHawking Zhang #define LSDMA_EXCEPTION_STATUS__SRAM_ECC__SHIFT 0x6 847*81570d6dSHawking Zhang #define LSDMA_EXCEPTION_STATUS__RB_FETCH_NACK_GEN_ERR__SHIFT 0x8 848*81570d6dSHawking Zhang #define LSDMA_EXCEPTION_STATUS__IB_FETCH_NACK_GEN_ERR__SHIFT 0x9 849*81570d6dSHawking Zhang #define LSDMA_EXCEPTION_STATUS__COPY_CMD_NACK_GEN_ERR__SHIFT 0xa 850*81570d6dSHawking Zhang #define LSDMA_EXCEPTION_STATUS__NON_COPY_CMD_NACK_GEN_ERR__SHIFT 0xb 851*81570d6dSHawking Zhang #define LSDMA_EXCEPTION_STATUS__RPTR_WB_NACK_GEN_ERR__SHIFT 0xd 852*81570d6dSHawking Zhang #define LSDMA_EXCEPTION_STATUS__RB_FETCH_NACK_PRT__SHIFT 0x10 853*81570d6dSHawking Zhang #define LSDMA_EXCEPTION_STATUS__IB_FETCH_NACK_PRT__SHIFT 0x11 854*81570d6dSHawking Zhang #define LSDMA_EXCEPTION_STATUS__COPY_CMD_NACK_PRT__SHIFT 0x12 855*81570d6dSHawking Zhang #define LSDMA_EXCEPTION_STATUS__NON_COPY_CMD_NACK_PRT__SHIFT 0x13 856*81570d6dSHawking Zhang #define LSDMA_EXCEPTION_STATUS__RPTR_WB_NACK_PRT__SHIFT 0x15 857*81570d6dSHawking Zhang #define LSDMA_EXCEPTION_STATUS__VM_HOLE__SHIFT 0x18 858*81570d6dSHawking Zhang #define LSDMA_EXCEPTION_STATUS__RB_FETCH_ECC_MASK 0x00000001L 859*81570d6dSHawking Zhang #define LSDMA_EXCEPTION_STATUS__IB_FETCH_ECC_MASK 0x00000002L 860*81570d6dSHawking Zhang #define LSDMA_EXCEPTION_STATUS__COPY_CMD_ECC_MASK 0x00000004L 861*81570d6dSHawking Zhang #define LSDMA_EXCEPTION_STATUS__NON_COPY_CMD_ECC_MASK 0x00000008L 862*81570d6dSHawking Zhang #define LSDMA_EXCEPTION_STATUS__SRAM_ECC_MASK 0x00000040L 863*81570d6dSHawking Zhang #define LSDMA_EXCEPTION_STATUS__RB_FETCH_NACK_GEN_ERR_MASK 0x00000100L 864*81570d6dSHawking Zhang #define LSDMA_EXCEPTION_STATUS__IB_FETCH_NACK_GEN_ERR_MASK 0x00000200L 865*81570d6dSHawking Zhang #define LSDMA_EXCEPTION_STATUS__COPY_CMD_NACK_GEN_ERR_MASK 0x00000400L 866*81570d6dSHawking Zhang #define LSDMA_EXCEPTION_STATUS__NON_COPY_CMD_NACK_GEN_ERR_MASK 0x00000800L 867*81570d6dSHawking Zhang #define LSDMA_EXCEPTION_STATUS__RPTR_WB_NACK_GEN_ERR_MASK 0x00002000L 868*81570d6dSHawking Zhang #define LSDMA_EXCEPTION_STATUS__RB_FETCH_NACK_PRT_MASK 0x00010000L 869*81570d6dSHawking Zhang #define LSDMA_EXCEPTION_STATUS__IB_FETCH_NACK_PRT_MASK 0x00020000L 870*81570d6dSHawking Zhang #define LSDMA_EXCEPTION_STATUS__COPY_CMD_NACK_PRT_MASK 0x00040000L 871*81570d6dSHawking Zhang #define LSDMA_EXCEPTION_STATUS__NON_COPY_CMD_NACK_PRT_MASK 0x00080000L 872*81570d6dSHawking Zhang #define LSDMA_EXCEPTION_STATUS__RPTR_WB_NACK_PRT_MASK 0x00200000L 873*81570d6dSHawking Zhang #define LSDMA_EXCEPTION_STATUS__VM_HOLE_MASK 0x01000000L 874*81570d6dSHawking Zhang //LSDMA_PIO_SRC_ADDR_LO 875*81570d6dSHawking Zhang #define LSDMA_PIO_SRC_ADDR_LO__SRC_ADDR_LO__SHIFT 0x0 876*81570d6dSHawking Zhang #define LSDMA_PIO_SRC_ADDR_LO__SRC_ADDR_LO_MASK 0xFFFFFFFFL 877*81570d6dSHawking Zhang //LSDMA_PIO_SRC_ADDR_HI 878*81570d6dSHawking Zhang #define LSDMA_PIO_SRC_ADDR_HI__SRC_ADDR_HI__SHIFT 0x0 879*81570d6dSHawking Zhang #define LSDMA_PIO_SRC_ADDR_HI__SRC_ADDR_HI_MASK 0xFFFFFFFFL 880*81570d6dSHawking Zhang //LSDMA_PIO_DST_ADDR_LO 881*81570d6dSHawking Zhang #define LSDMA_PIO_DST_ADDR_LO__DST_ADDR_LO__SHIFT 0x0 882*81570d6dSHawking Zhang #define LSDMA_PIO_DST_ADDR_LO__DST_ADDR_LO_MASK 0xFFFFFFFFL 883*81570d6dSHawking Zhang //LSDMA_PIO_DST_ADDR_HI 884*81570d6dSHawking Zhang #define LSDMA_PIO_DST_ADDR_HI__DST_ADDR_HI__SHIFT 0x0 885*81570d6dSHawking Zhang #define LSDMA_PIO_DST_ADDR_HI__DST_ADDR_HI_MASK 0xFFFFFFFFL 886*81570d6dSHawking Zhang //LSDMA_PIO_COMMAND 887*81570d6dSHawking Zhang #define LSDMA_PIO_COMMAND__BYTE_COUNT__SHIFT 0x0 888*81570d6dSHawking Zhang #define LSDMA_PIO_COMMAND__SRC_LOCATION__SHIFT 0x1a 889*81570d6dSHawking Zhang #define LSDMA_PIO_COMMAND__DST_LOCATION__SHIFT 0x1b 890*81570d6dSHawking Zhang #define LSDMA_PIO_COMMAND__SRC_ADDR_INC__SHIFT 0x1c 891*81570d6dSHawking Zhang #define LSDMA_PIO_COMMAND__DST_ADDR_INC__SHIFT 0x1d 892*81570d6dSHawking Zhang #define LSDMA_PIO_COMMAND__OVERLAP_DISABLE__SHIFT 0x1e 893*81570d6dSHawking Zhang #define LSDMA_PIO_COMMAND__CONSTANT_FILL__SHIFT 0x1f 894*81570d6dSHawking Zhang #define LSDMA_PIO_COMMAND__BYTE_COUNT_MASK 0x03FFFFFFL 895*81570d6dSHawking Zhang #define LSDMA_PIO_COMMAND__SRC_LOCATION_MASK 0x04000000L 896*81570d6dSHawking Zhang #define LSDMA_PIO_COMMAND__DST_LOCATION_MASK 0x08000000L 897*81570d6dSHawking Zhang #define LSDMA_PIO_COMMAND__SRC_ADDR_INC_MASK 0x10000000L 898*81570d6dSHawking Zhang #define LSDMA_PIO_COMMAND__DST_ADDR_INC_MASK 0x20000000L 899*81570d6dSHawking Zhang #define LSDMA_PIO_COMMAND__OVERLAP_DISABLE_MASK 0x40000000L 900*81570d6dSHawking Zhang #define LSDMA_PIO_COMMAND__CONSTANT_FILL_MASK 0x80000000L 901*81570d6dSHawking Zhang //LSDMA_PIO_CONSTFILL_DATA 902*81570d6dSHawking Zhang #define LSDMA_PIO_CONSTFILL_DATA__DATA__SHIFT 0x0 903*81570d6dSHawking Zhang #define LSDMA_PIO_CONSTFILL_DATA__DATA_MASK 0xFFFFFFFFL 904*81570d6dSHawking Zhang //LSDMA_PIO_CONTROL 905*81570d6dSHawking Zhang #define LSDMA_PIO_CONTROL__VMID__SHIFT 0x0 906*81570d6dSHawking Zhang #define LSDMA_PIO_CONTROL__GPA__SHIFT 0x4 907*81570d6dSHawking Zhang #define LSDMA_PIO_CONTROL__SYS__SHIFT 0x5 908*81570d6dSHawking Zhang #define LSDMA_PIO_CONTROL__GCC__SHIFT 0x6 909*81570d6dSHawking Zhang #define LSDMA_PIO_CONTROL__SNOOP__SHIFT 0x7 910*81570d6dSHawking Zhang #define LSDMA_PIO_CONTROL__VMID_MASK 0x0000000FL 911*81570d6dSHawking Zhang #define LSDMA_PIO_CONTROL__GPA_MASK 0x00000010L 912*81570d6dSHawking Zhang #define LSDMA_PIO_CONTROL__SYS_MASK 0x00000020L 913*81570d6dSHawking Zhang #define LSDMA_PIO_CONTROL__GCC_MASK 0x00000040L 914*81570d6dSHawking Zhang #define LSDMA_PIO_CONTROL__SNOOP_MASK 0x00000080L 915*81570d6dSHawking Zhang //LSDMA_INT_CNTL 916*81570d6dSHawking Zhang #define LSDMA_INT_CNTL__ATOMIC_RTN_DONE_INT_ENABLE__SHIFT 0x0 917*81570d6dSHawking Zhang #define LSDMA_INT_CNTL__TRAP_INT_ENABLE__SHIFT 0x1 918*81570d6dSHawking Zhang #define LSDMA_INT_CNTL__SRBM_WRITE_INT_ENABLE__SHIFT 0x2 919*81570d6dSHawking Zhang #define LSDMA_INT_CNTL__CTX_EMPTY_INT_ENABLE__SHIFT 0x3 920*81570d6dSHawking Zhang #define LSDMA_INT_CNTL__FROZEN_INT_ENABLE__SHIFT 0x4 921*81570d6dSHawking Zhang #define LSDMA_INT_CNTL__PREEMPT_INT_ENABLE__SHIFT 0x5 922*81570d6dSHawking Zhang #define LSDMA_INT_CNTL__IB_PREEMPT_INT_ENABLE__SHIFT 0x6 923*81570d6dSHawking Zhang #define LSDMA_INT_CNTL__ATOMIC_TIMEOUT_INT_ENABLE__SHIFT 0x7 924*81570d6dSHawking Zhang #define LSDMA_INT_CNTL__POLL_TIMEOUT_INT_ENABLE__SHIFT 0x8 925*81570d6dSHawking Zhang #define LSDMA_INT_CNTL__VM_HOLE_INT_ENABLE__SHIFT 0x9 926*81570d6dSHawking Zhang #define LSDMA_INT_CNTL__NACK_GEN_ERR_INT_ENABLE__SHIFT 0xa 927*81570d6dSHawking Zhang #define LSDMA_INT_CNTL__NACK_PRT_INT_ENABLE__SHIFT 0xb 928*81570d6dSHawking Zhang #define LSDMA_INT_CNTL__ECC_INT_ENABLE__SHIFT 0xc 929*81570d6dSHawking Zhang #define LSDMA_INT_CNTL__ATOMIC_RTN_DONE_INT_ENABLE_MASK 0x00000001L 930*81570d6dSHawking Zhang #define LSDMA_INT_CNTL__TRAP_INT_ENABLE_MASK 0x00000002L 931*81570d6dSHawking Zhang #define LSDMA_INT_CNTL__SRBM_WRITE_INT_ENABLE_MASK 0x00000004L 932*81570d6dSHawking Zhang #define LSDMA_INT_CNTL__CTX_EMPTY_INT_ENABLE_MASK 0x00000008L 933*81570d6dSHawking Zhang #define LSDMA_INT_CNTL__FROZEN_INT_ENABLE_MASK 0x00000010L 934*81570d6dSHawking Zhang #define LSDMA_INT_CNTL__PREEMPT_INT_ENABLE_MASK 0x00000020L 935*81570d6dSHawking Zhang #define LSDMA_INT_CNTL__IB_PREEMPT_INT_ENABLE_MASK 0x00000040L 936*81570d6dSHawking Zhang #define LSDMA_INT_CNTL__ATOMIC_TIMEOUT_INT_ENABLE_MASK 0x00000080L 937*81570d6dSHawking Zhang #define LSDMA_INT_CNTL__POLL_TIMEOUT_INT_ENABLE_MASK 0x00000100L 938*81570d6dSHawking Zhang #define LSDMA_INT_CNTL__VM_HOLE_INT_ENABLE_MASK 0x00000200L 939*81570d6dSHawking Zhang #define LSDMA_INT_CNTL__NACK_GEN_ERR_INT_ENABLE_MASK 0x00000400L 940*81570d6dSHawking Zhang #define LSDMA_INT_CNTL__NACK_PRT_INT_ENABLE_MASK 0x00000800L 941*81570d6dSHawking Zhang #define LSDMA_INT_CNTL__ECC_INT_ENABLE_MASK 0x00001000L 942*81570d6dSHawking Zhang //LSDMA_MEM_POWER_CTRL 943*81570d6dSHawking Zhang #define LSDMA_MEM_POWER_CTRL__MEM_POWER_CTRL_EN__SHIFT 0x0 944*81570d6dSHawking Zhang #define LSDMA_MEM_POWER_CTRL__MEM_POWER_CTRL_EN_MASK 0x00000001L 945*81570d6dSHawking Zhang //LSDMA_CLK_CTRL 946*81570d6dSHawking Zhang #define LSDMA_CLK_CTRL__SOFT_OVERRIDE_SRAM_FGCG__SHIFT 0x0 947*81570d6dSHawking Zhang #define LSDMA_CLK_CTRL__RESERVED__SHIFT 0x1 948*81570d6dSHawking Zhang #define LSDMA_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18 949*81570d6dSHawking Zhang #define LSDMA_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19 950*81570d6dSHawking Zhang #define LSDMA_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a 951*81570d6dSHawking Zhang #define LSDMA_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b 952*81570d6dSHawking Zhang #define LSDMA_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c 953*81570d6dSHawking Zhang #define LSDMA_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d 954*81570d6dSHawking Zhang #define LSDMA_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e 955*81570d6dSHawking Zhang #define LSDMA_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f 956*81570d6dSHawking Zhang #define LSDMA_CLK_CTRL__SOFT_OVERRIDE_SRAM_FGCG_MASK 0x00000001L 957*81570d6dSHawking Zhang #define LSDMA_CLK_CTRL__RESERVED_MASK 0x00FFFFFEL 958*81570d6dSHawking Zhang #define LSDMA_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L 959*81570d6dSHawking Zhang #define LSDMA_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L 960*81570d6dSHawking Zhang #define LSDMA_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L 961*81570d6dSHawking Zhang #define LSDMA_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L 962*81570d6dSHawking Zhang #define LSDMA_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L 963*81570d6dSHawking Zhang #define LSDMA_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L 964*81570d6dSHawking Zhang #define LSDMA_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L 965*81570d6dSHawking Zhang #define LSDMA_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L 966*81570d6dSHawking Zhang //LSDMA_CNTL 967*81570d6dSHawking Zhang #define LSDMA_CNTL__UTC_L1_ENABLE__SHIFT 0x1 968*81570d6dSHawking Zhang #define LSDMA_CNTL__SEM_WAIT_INT_ENABLE__SHIFT 0x2 969*81570d6dSHawking Zhang #define LSDMA_CNTL__DATA_SWAP_ENABLE__SHIFT 0x3 970*81570d6dSHawking Zhang #define LSDMA_CNTL__FENCE_SWAP_ENABLE__SHIFT 0x4 971*81570d6dSHawking Zhang #define LSDMA_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x5 972*81570d6dSHawking Zhang #define LSDMA_CNTL__MIDCMD_EXPIRE_ENABLE__SHIFT 0x6 973*81570d6dSHawking Zhang #define LSDMA_CNTL__MIDCMD_WORLDSWITCH_ENABLE__SHIFT 0x11 974*81570d6dSHawking Zhang #define LSDMA_CNTL__AUTO_CTXSW_ENABLE__SHIFT 0x12 975*81570d6dSHawking Zhang #define LSDMA_CNTL__UTC_L1_ENABLE_MASK 0x00000002L 976*81570d6dSHawking Zhang #define LSDMA_CNTL__SEM_WAIT_INT_ENABLE_MASK 0x00000004L 977*81570d6dSHawking Zhang #define LSDMA_CNTL__DATA_SWAP_ENABLE_MASK 0x00000008L 978*81570d6dSHawking Zhang #define LSDMA_CNTL__FENCE_SWAP_ENABLE_MASK 0x00000010L 979*81570d6dSHawking Zhang #define LSDMA_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00000020L 980*81570d6dSHawking Zhang #define LSDMA_CNTL__MIDCMD_EXPIRE_ENABLE_MASK 0x00000040L 981*81570d6dSHawking Zhang #define LSDMA_CNTL__MIDCMD_WORLDSWITCH_ENABLE_MASK 0x00020000L 982*81570d6dSHawking Zhang #define LSDMA_CNTL__AUTO_CTXSW_ENABLE_MASK 0x00040000L 983*81570d6dSHawking Zhang //LSDMA_CHICKEN_BITS 984*81570d6dSHawking Zhang #define LSDMA_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE__SHIFT 0x1 985*81570d6dSHawking Zhang #define LSDMA_CHICKEN_BITS__STALL_ON_NO_FREE_DATA_BUFFER_ENABLE__SHIFT 0x2 986*81570d6dSHawking Zhang #define LSDMA_CHICKEN_BITS__F32_MGCG_ENABLE__SHIFT 0x3 987*81570d6dSHawking Zhang #define LSDMA_CHICKEN_BITS__WRITE_BURST_LENGTH__SHIFT 0x8 988*81570d6dSHawking Zhang #define LSDMA_CHICKEN_BITS__WRITE_BURST_WAIT_CYCLE__SHIFT 0xa 989*81570d6dSHawking Zhang #define LSDMA_CHICKEN_BITS__COPY_OVERLAP_ENABLE__SHIFT 0x10 990*81570d6dSHawking Zhang #define LSDMA_CHICKEN_BITS__RAW_CHECK_ENABLE__SHIFT 0x11 991*81570d6dSHawking Zhang #define LSDMA_CHICKEN_BITS__T2L_256B_ENABLE__SHIFT 0x12 992*81570d6dSHawking Zhang #define LSDMA_CHICKEN_BITS__SRBM_POLL_RETRYING__SHIFT 0x14 993*81570d6dSHawking Zhang #define LSDMA_CHICKEN_BITS__CG_STATUS_OUTPUT__SHIFT 0x17 994*81570d6dSHawking Zhang #define LSDMA_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE_MASK 0x00000002L 995*81570d6dSHawking Zhang #define LSDMA_CHICKEN_BITS__STALL_ON_NO_FREE_DATA_BUFFER_ENABLE_MASK 0x00000004L 996*81570d6dSHawking Zhang #define LSDMA_CHICKEN_BITS__F32_MGCG_ENABLE_MASK 0x00000008L 997*81570d6dSHawking Zhang #define LSDMA_CHICKEN_BITS__WRITE_BURST_LENGTH_MASK 0x00000300L 998*81570d6dSHawking Zhang #define LSDMA_CHICKEN_BITS__WRITE_BURST_WAIT_CYCLE_MASK 0x00001C00L 999*81570d6dSHawking Zhang #define LSDMA_CHICKEN_BITS__COPY_OVERLAP_ENABLE_MASK 0x00010000L 1000*81570d6dSHawking Zhang #define LSDMA_CHICKEN_BITS__RAW_CHECK_ENABLE_MASK 0x00020000L 1001*81570d6dSHawking Zhang #define LSDMA_CHICKEN_BITS__T2L_256B_ENABLE_MASK 0x00040000L 1002*81570d6dSHawking Zhang #define LSDMA_CHICKEN_BITS__SRBM_POLL_RETRYING_MASK 0x00100000L 1003*81570d6dSHawking Zhang #define LSDMA_CHICKEN_BITS__CG_STATUS_OUTPUT_MASK 0x00800000L 1004*81570d6dSHawking Zhang //LSDMA_GB_ADDR_CONFIG 1005*81570d6dSHawking Zhang #define LSDMA_GB_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 1006*81570d6dSHawking Zhang #define LSDMA_GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x3 1007*81570d6dSHawking Zhang #define LSDMA_GB_ADDR_CONFIG__MAX_COMPRESSED_FRAGS__SHIFT 0x6 1008*81570d6dSHawking Zhang #define LSDMA_GB_ADDR_CONFIG__NUM_PKRS__SHIFT 0x8 1009*81570d6dSHawking Zhang #define LSDMA_GB_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0x13 1010*81570d6dSHawking Zhang #define LSDMA_GB_ADDR_CONFIG__NUM_RB_PER_SE__SHIFT 0x1a 1011*81570d6dSHawking Zhang #define LSDMA_GB_ADDR_CONFIG__NUM_PIPES_MASK 0x00000007L 1012*81570d6dSHawking Zhang #define LSDMA_GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L 1013*81570d6dSHawking Zhang #define LSDMA_GB_ADDR_CONFIG__MAX_COMPRESSED_FRAGS_MASK 0x000000C0L 1014*81570d6dSHawking Zhang #define LSDMA_GB_ADDR_CONFIG__NUM_PKRS_MASK 0x00000700L 1015*81570d6dSHawking Zhang #define LSDMA_GB_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x00180000L 1016*81570d6dSHawking Zhang #define LSDMA_GB_ADDR_CONFIG__NUM_RB_PER_SE_MASK 0x0C000000L 1017*81570d6dSHawking Zhang //LSDMA_GB_ADDR_CONFIG_READ 1018*81570d6dSHawking Zhang #define LSDMA_GB_ADDR_CONFIG_READ__NUM_PIPES__SHIFT 0x0 1019*81570d6dSHawking Zhang #define LSDMA_GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE__SHIFT 0x3 1020*81570d6dSHawking Zhang #define LSDMA_GB_ADDR_CONFIG_READ__MAX_COMPRESSED_FRAGS__SHIFT 0x6 1021*81570d6dSHawking Zhang #define LSDMA_GB_ADDR_CONFIG_READ__NUM_PKRS__SHIFT 0x8 1022*81570d6dSHawking Zhang #define LSDMA_GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES__SHIFT 0x13 1023*81570d6dSHawking Zhang #define LSDMA_GB_ADDR_CONFIG_READ__NUM_RB_PER_SE__SHIFT 0x1a 1024*81570d6dSHawking Zhang #define LSDMA_GB_ADDR_CONFIG_READ__NUM_PIPES_MASK 0x00000007L 1025*81570d6dSHawking Zhang #define LSDMA_GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L 1026*81570d6dSHawking Zhang #define LSDMA_GB_ADDR_CONFIG_READ__MAX_COMPRESSED_FRAGS_MASK 0x000000C0L 1027*81570d6dSHawking Zhang #define LSDMA_GB_ADDR_CONFIG_READ__NUM_PKRS_MASK 0x00000700L 1028*81570d6dSHawking Zhang #define LSDMA_GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES_MASK 0x00180000L 1029*81570d6dSHawking Zhang #define LSDMA_GB_ADDR_CONFIG_READ__NUM_RB_PER_SE_MASK 0x0C000000L 1030*81570d6dSHawking Zhang //LSDMA_QUEUE0_RB_CNTL 1031*81570d6dSHawking Zhang #define LSDMA_QUEUE0_RB_CNTL__RB_ENABLE__SHIFT 0x0 1032*81570d6dSHawking Zhang #define LSDMA_QUEUE0_RB_CNTL__RB_SIZE__SHIFT 0x1 1033*81570d6dSHawking Zhang #define LSDMA_QUEUE0_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 1034*81570d6dSHawking Zhang #define LSDMA_QUEUE0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc 1035*81570d6dSHawking Zhang #define LSDMA_QUEUE0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd 1036*81570d6dSHawking Zhang #define LSDMA_QUEUE0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 1037*81570d6dSHawking Zhang #define LSDMA_QUEUE0_RB_CNTL__RB_VMID__SHIFT 0x18 1038*81570d6dSHawking Zhang #define LSDMA_QUEUE0_RB_CNTL__RB_ENABLE_MASK 0x00000001L 1039*81570d6dSHawking Zhang #define LSDMA_QUEUE0_RB_CNTL__RB_SIZE_MASK 0x0000003EL 1040*81570d6dSHawking Zhang #define LSDMA_QUEUE0_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L 1041*81570d6dSHawking Zhang #define LSDMA_QUEUE0_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L 1042*81570d6dSHawking Zhang #define LSDMA_QUEUE0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L 1043*81570d6dSHawking Zhang #define LSDMA_QUEUE0_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L 1044*81570d6dSHawking Zhang #define LSDMA_QUEUE0_RB_CNTL__RB_VMID_MASK 0x0F000000L 1045*81570d6dSHawking Zhang //LSDMA_QUEUE0_RB_BASE 1046*81570d6dSHawking Zhang #define LSDMA_QUEUE0_RB_BASE__ADDR__SHIFT 0x0 1047*81570d6dSHawking Zhang #define LSDMA_QUEUE0_RB_BASE__ADDR_MASK 0xFFFFFFFFL 1048*81570d6dSHawking Zhang //LSDMA_QUEUE0_RB_BASE_HI 1049*81570d6dSHawking Zhang #define LSDMA_QUEUE0_RB_BASE_HI__ADDR__SHIFT 0x0 1050*81570d6dSHawking Zhang #define LSDMA_QUEUE0_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL 1051*81570d6dSHawking Zhang //LSDMA_QUEUE0_RB_RPTR 1052*81570d6dSHawking Zhang #define LSDMA_QUEUE0_RB_RPTR__OFFSET__SHIFT 0x0 1053*81570d6dSHawking Zhang #define LSDMA_QUEUE0_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL 1054*81570d6dSHawking Zhang //LSDMA_QUEUE0_RB_RPTR_HI 1055*81570d6dSHawking Zhang #define LSDMA_QUEUE0_RB_RPTR_HI__OFFSET__SHIFT 0x0 1056*81570d6dSHawking Zhang #define LSDMA_QUEUE0_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL 1057*81570d6dSHawking Zhang //LSDMA_QUEUE0_RB_WPTR 1058*81570d6dSHawking Zhang #define LSDMA_QUEUE0_RB_WPTR__OFFSET__SHIFT 0x0 1059*81570d6dSHawking Zhang #define LSDMA_QUEUE0_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL 1060*81570d6dSHawking Zhang //LSDMA_QUEUE0_RB_WPTR_HI 1061*81570d6dSHawking Zhang #define LSDMA_QUEUE0_RB_WPTR_HI__OFFSET__SHIFT 0x0 1062*81570d6dSHawking Zhang #define LSDMA_QUEUE0_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL 1063*81570d6dSHawking Zhang //LSDMA_QUEUE0_RB_WPTR_POLL_CNTL 1064*81570d6dSHawking Zhang #define LSDMA_QUEUE0_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 1065*81570d6dSHawking Zhang #define LSDMA_QUEUE0_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 1066*81570d6dSHawking Zhang #define LSDMA_QUEUE0_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 1067*81570d6dSHawking Zhang #define LSDMA_QUEUE0_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 1068*81570d6dSHawking Zhang #define LSDMA_QUEUE0_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 1069*81570d6dSHawking Zhang #define LSDMA_QUEUE0_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L 1070*81570d6dSHawking Zhang #define LSDMA_QUEUE0_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L 1071*81570d6dSHawking Zhang #define LSDMA_QUEUE0_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L 1072*81570d6dSHawking Zhang #define LSDMA_QUEUE0_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L 1073*81570d6dSHawking Zhang #define LSDMA_QUEUE0_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L 1074*81570d6dSHawking Zhang //LSDMA_QUEUE0_RB_RPTR_ADDR_HI 1075*81570d6dSHawking Zhang #define LSDMA_QUEUE0_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 1076*81570d6dSHawking Zhang #define LSDMA_QUEUE0_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1077*81570d6dSHawking Zhang //LSDMA_QUEUE0_RB_RPTR_ADDR_LO 1078*81570d6dSHawking Zhang #define LSDMA_QUEUE0_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 1079*81570d6dSHawking Zhang #define LSDMA_QUEUE0_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 1080*81570d6dSHawking Zhang #define LSDMA_QUEUE0_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L 1081*81570d6dSHawking Zhang #define LSDMA_QUEUE0_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1082*81570d6dSHawking Zhang //LSDMA_QUEUE0_IB_CNTL 1083*81570d6dSHawking Zhang #define LSDMA_QUEUE0_IB_CNTL__IB_ENABLE__SHIFT 0x0 1084*81570d6dSHawking Zhang #define LSDMA_QUEUE0_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 1085*81570d6dSHawking Zhang #define LSDMA_QUEUE0_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 1086*81570d6dSHawking Zhang #define LSDMA_QUEUE0_IB_CNTL__CMD_VMID__SHIFT 0x10 1087*81570d6dSHawking Zhang #define LSDMA_QUEUE0_IB_CNTL__IB_ENABLE_MASK 0x00000001L 1088*81570d6dSHawking Zhang #define LSDMA_QUEUE0_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L 1089*81570d6dSHawking Zhang #define LSDMA_QUEUE0_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L 1090*81570d6dSHawking Zhang #define LSDMA_QUEUE0_IB_CNTL__CMD_VMID_MASK 0x000F0000L 1091*81570d6dSHawking Zhang //LSDMA_QUEUE0_IB_RPTR 1092*81570d6dSHawking Zhang #define LSDMA_QUEUE0_IB_RPTR__OFFSET__SHIFT 0x2 1093*81570d6dSHawking Zhang #define LSDMA_QUEUE0_IB_RPTR__OFFSET_MASK 0x003FFFFCL 1094*81570d6dSHawking Zhang //LSDMA_QUEUE0_IB_OFFSET 1095*81570d6dSHawking Zhang #define LSDMA_QUEUE0_IB_OFFSET__OFFSET__SHIFT 0x2 1096*81570d6dSHawking Zhang #define LSDMA_QUEUE0_IB_OFFSET__OFFSET_MASK 0x003FFFFCL 1097*81570d6dSHawking Zhang //LSDMA_QUEUE0_IB_BASE_LO 1098*81570d6dSHawking Zhang #define LSDMA_QUEUE0_IB_BASE_LO__ADDR__SHIFT 0x5 1099*81570d6dSHawking Zhang #define LSDMA_QUEUE0_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L 1100*81570d6dSHawking Zhang //LSDMA_QUEUE0_IB_BASE_HI 1101*81570d6dSHawking Zhang #define LSDMA_QUEUE0_IB_BASE_HI__ADDR__SHIFT 0x0 1102*81570d6dSHawking Zhang #define LSDMA_QUEUE0_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL 1103*81570d6dSHawking Zhang //LSDMA_QUEUE0_IB_SIZE 1104*81570d6dSHawking Zhang #define LSDMA_QUEUE0_IB_SIZE__SIZE__SHIFT 0x0 1105*81570d6dSHawking Zhang #define LSDMA_QUEUE0_IB_SIZE__SIZE_MASK 0x000FFFFFL 1106*81570d6dSHawking Zhang //LSDMA_QUEUE0_SKIP_CNTL 1107*81570d6dSHawking Zhang #define LSDMA_QUEUE0_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 1108*81570d6dSHawking Zhang #define LSDMA_QUEUE0_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL 1109*81570d6dSHawking Zhang //LSDMA_QUEUE0_CONTEXT_STATUS 1110*81570d6dSHawking Zhang #define LSDMA_QUEUE0_CONTEXT_STATUS__SELECTED__SHIFT 0x0 1111*81570d6dSHawking Zhang #define LSDMA_QUEUE0_CONTEXT_STATUS__IDLE__SHIFT 0x2 1112*81570d6dSHawking Zhang #define LSDMA_QUEUE0_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 1113*81570d6dSHawking Zhang #define LSDMA_QUEUE0_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 1114*81570d6dSHawking Zhang #define LSDMA_QUEUE0_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 1115*81570d6dSHawking Zhang #define LSDMA_QUEUE0_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 1116*81570d6dSHawking Zhang #define LSDMA_QUEUE0_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 1117*81570d6dSHawking Zhang #define LSDMA_QUEUE0_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa 1118*81570d6dSHawking Zhang #define LSDMA_QUEUE0_CONTEXT_STATUS__SELECTED_MASK 0x00000001L 1119*81570d6dSHawking Zhang #define LSDMA_QUEUE0_CONTEXT_STATUS__IDLE_MASK 0x00000004L 1120*81570d6dSHawking Zhang #define LSDMA_QUEUE0_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L 1121*81570d6dSHawking Zhang #define LSDMA_QUEUE0_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L 1122*81570d6dSHawking Zhang #define LSDMA_QUEUE0_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L 1123*81570d6dSHawking Zhang #define LSDMA_QUEUE0_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L 1124*81570d6dSHawking Zhang #define LSDMA_QUEUE0_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L 1125*81570d6dSHawking Zhang #define LSDMA_QUEUE0_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L 1126*81570d6dSHawking Zhang //LSDMA_QUEUE0_DOORBELL 1127*81570d6dSHawking Zhang #define LSDMA_QUEUE0_DOORBELL__ENABLE__SHIFT 0x1c 1128*81570d6dSHawking Zhang #define LSDMA_QUEUE0_DOORBELL__CAPTURED__SHIFT 0x1e 1129*81570d6dSHawking Zhang #define LSDMA_QUEUE0_DOORBELL__ENABLE_MASK 0x10000000L 1130*81570d6dSHawking Zhang #define LSDMA_QUEUE0_DOORBELL__CAPTURED_MASK 0x40000000L 1131*81570d6dSHawking Zhang //LSDMA_QUEUE0_STATUS 1132*81570d6dSHawking Zhang #define LSDMA_QUEUE0_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 1133*81570d6dSHawking Zhang #define LSDMA_QUEUE0_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 1134*81570d6dSHawking Zhang #define LSDMA_QUEUE0_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL 1135*81570d6dSHawking Zhang #define LSDMA_QUEUE0_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L 1136*81570d6dSHawking Zhang //LSDMA_QUEUE0_DOORBELL_LOG 1137*81570d6dSHawking Zhang #define LSDMA_QUEUE0_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 1138*81570d6dSHawking Zhang #define LSDMA_QUEUE0_DOORBELL_LOG__DATA__SHIFT 0x2 1139*81570d6dSHawking Zhang #define LSDMA_QUEUE0_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L 1140*81570d6dSHawking Zhang #define LSDMA_QUEUE0_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL 1141*81570d6dSHawking Zhang //LSDMA_QUEUE0_WATERMARK 1142*81570d6dSHawking Zhang #define LSDMA_QUEUE0_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 1143*81570d6dSHawking Zhang #define LSDMA_QUEUE0_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 1144*81570d6dSHawking Zhang #define LSDMA_QUEUE0_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL 1145*81570d6dSHawking Zhang #define LSDMA_QUEUE0_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L 1146*81570d6dSHawking Zhang //LSDMA_QUEUE0_DOORBELL_OFFSET 1147*81570d6dSHawking Zhang #define LSDMA_QUEUE0_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 1148*81570d6dSHawking Zhang #define LSDMA_QUEUE0_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL 1149*81570d6dSHawking Zhang //LSDMA_QUEUE0_CSA_ADDR_LO 1150*81570d6dSHawking Zhang #define LSDMA_QUEUE0_CSA_ADDR_LO__ADDR__SHIFT 0x2 1151*81570d6dSHawking Zhang #define LSDMA_QUEUE0_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1152*81570d6dSHawking Zhang //LSDMA_QUEUE0_CSA_ADDR_HI 1153*81570d6dSHawking Zhang #define LSDMA_QUEUE0_CSA_ADDR_HI__ADDR__SHIFT 0x0 1154*81570d6dSHawking Zhang #define LSDMA_QUEUE0_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1155*81570d6dSHawking Zhang //LSDMA_QUEUE0_RB_PREEMPT 1156*81570d6dSHawking Zhang #define LSDMA_QUEUE0_RB_PREEMPT__PREEMPT_REQ__SHIFT 0x0 1157*81570d6dSHawking Zhang #define LSDMA_QUEUE0_RB_PREEMPT__PREEMPT_REQ_MASK 0x00000001L 1158*81570d6dSHawking Zhang //LSDMA_QUEUE0_IB_SUB_REMAIN 1159*81570d6dSHawking Zhang #define LSDMA_QUEUE0_IB_SUB_REMAIN__SIZE__SHIFT 0x0 1160*81570d6dSHawking Zhang #define LSDMA_QUEUE0_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL 1161*81570d6dSHawking Zhang //LSDMA_QUEUE0_PREEMPT 1162*81570d6dSHawking Zhang #define LSDMA_QUEUE0_PREEMPT__IB_PREEMPT__SHIFT 0x0 1163*81570d6dSHawking Zhang #define LSDMA_QUEUE0_PREEMPT__IB_PREEMPT_MASK 0x00000001L 1164*81570d6dSHawking Zhang //LSDMA_QUEUE0_DUMMY0 1165*81570d6dSHawking Zhang #define LSDMA_QUEUE0_DUMMY0__DUMMY__SHIFT 0x0 1166*81570d6dSHawking Zhang #define LSDMA_QUEUE0_DUMMY0__DUMMY_MASK 0xFFFFFFFFL 1167*81570d6dSHawking Zhang //LSDMA_QUEUE0_RB_WPTR_POLL_ADDR_HI 1168*81570d6dSHawking Zhang #define LSDMA_QUEUE0_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 1169*81570d6dSHawking Zhang #define LSDMA_QUEUE0_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1170*81570d6dSHawking Zhang //LSDMA_QUEUE0_RB_WPTR_POLL_ADDR_LO 1171*81570d6dSHawking Zhang #define LSDMA_QUEUE0_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 1172*81570d6dSHawking Zhang #define LSDMA_QUEUE0_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1173*81570d6dSHawking Zhang //LSDMA_QUEUE0_RB_AQL_CNTL 1174*81570d6dSHawking Zhang #define LSDMA_QUEUE0_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 1175*81570d6dSHawking Zhang #define LSDMA_QUEUE0_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 1176*81570d6dSHawking Zhang #define LSDMA_QUEUE0_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 1177*81570d6dSHawking Zhang #define LSDMA_QUEUE0_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L 1178*81570d6dSHawking Zhang #define LSDMA_QUEUE0_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL 1179*81570d6dSHawking Zhang #define LSDMA_QUEUE0_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L 1180*81570d6dSHawking Zhang //LSDMA_QUEUE0_MINOR_PTR_UPDATE 1181*81570d6dSHawking Zhang #define LSDMA_QUEUE0_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 1182*81570d6dSHawking Zhang #define LSDMA_QUEUE0_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L 1183*81570d6dSHawking Zhang //LSDMA_QUEUE0_CNTL 1184*81570d6dSHawking Zhang #define LSDMA_QUEUE0_CNTL__QUANTUM__SHIFT 0x0 1185*81570d6dSHawking Zhang #define LSDMA_QUEUE0_CNTL__QUANTUM_MASK 0x000000FFL 1186*81570d6dSHawking Zhang //LSDMA_QUEUE0_DUMMY1 1187*81570d6dSHawking Zhang #define LSDMA_QUEUE0_DUMMY1__DUMMY__SHIFT 0x0 1188*81570d6dSHawking Zhang #define LSDMA_QUEUE0_DUMMY1__DUMMY_MASK 0xFFFFFFFFL 1189*81570d6dSHawking Zhang //LSDMA_QUEUE0_DUMMY2 1190*81570d6dSHawking Zhang #define LSDMA_QUEUE0_DUMMY2__DUMMY__SHIFT 0x0 1191*81570d6dSHawking Zhang #define LSDMA_QUEUE0_DUMMY2__DUMMY_MASK 0xFFFFFFFFL 1192*81570d6dSHawking Zhang //LSDMA_QUEUE0_MIDCMD_DATA0 1193*81570d6dSHawking Zhang #define LSDMA_QUEUE0_MIDCMD_DATA0__DATA0__SHIFT 0x0 1194*81570d6dSHawking Zhang #define LSDMA_QUEUE0_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL 1195*81570d6dSHawking Zhang //LSDMA_QUEUE0_MIDCMD_DATA1 1196*81570d6dSHawking Zhang #define LSDMA_QUEUE0_MIDCMD_DATA1__DATA1__SHIFT 0x0 1197*81570d6dSHawking Zhang #define LSDMA_QUEUE0_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL 1198*81570d6dSHawking Zhang //LSDMA_QUEUE0_MIDCMD_DATA2 1199*81570d6dSHawking Zhang #define LSDMA_QUEUE0_MIDCMD_DATA2__DATA2__SHIFT 0x0 1200*81570d6dSHawking Zhang #define LSDMA_QUEUE0_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL 1201*81570d6dSHawking Zhang //LSDMA_QUEUE0_MIDCMD_DATA3 1202*81570d6dSHawking Zhang #define LSDMA_QUEUE0_MIDCMD_DATA3__DATA3__SHIFT 0x0 1203*81570d6dSHawking Zhang #define LSDMA_QUEUE0_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL 1204*81570d6dSHawking Zhang //LSDMA_QUEUE0_MIDCMD_DATA4 1205*81570d6dSHawking Zhang #define LSDMA_QUEUE0_MIDCMD_DATA4__DATA4__SHIFT 0x0 1206*81570d6dSHawking Zhang #define LSDMA_QUEUE0_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL 1207*81570d6dSHawking Zhang //LSDMA_QUEUE0_MIDCMD_DATA5 1208*81570d6dSHawking Zhang #define LSDMA_QUEUE0_MIDCMD_DATA5__DATA5__SHIFT 0x0 1209*81570d6dSHawking Zhang #define LSDMA_QUEUE0_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL 1210*81570d6dSHawking Zhang //LSDMA_QUEUE0_MIDCMD_DATA6 1211*81570d6dSHawking Zhang #define LSDMA_QUEUE0_MIDCMD_DATA6__DATA6__SHIFT 0x0 1212*81570d6dSHawking Zhang #define LSDMA_QUEUE0_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL 1213*81570d6dSHawking Zhang //LSDMA_QUEUE0_MIDCMD_DATA7 1214*81570d6dSHawking Zhang #define LSDMA_QUEUE0_MIDCMD_DATA7__DATA7__SHIFT 0x0 1215*81570d6dSHawking Zhang #define LSDMA_QUEUE0_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL 1216*81570d6dSHawking Zhang //LSDMA_QUEUE0_MIDCMD_DATA8 1217*81570d6dSHawking Zhang #define LSDMA_QUEUE0_MIDCMD_DATA8__DATA8__SHIFT 0x0 1218*81570d6dSHawking Zhang #define LSDMA_QUEUE0_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL 1219*81570d6dSHawking Zhang //LSDMA_QUEUE0_MIDCMD_DATA9 1220*81570d6dSHawking Zhang #define LSDMA_QUEUE0_MIDCMD_DATA9__DATA9__SHIFT 0x0 1221*81570d6dSHawking Zhang #define LSDMA_QUEUE0_MIDCMD_DATA9__DATA9_MASK 0xFFFFFFFFL 1222*81570d6dSHawking Zhang //LSDMA_QUEUE0_MIDCMD_DATA10 1223*81570d6dSHawking Zhang #define LSDMA_QUEUE0_MIDCMD_DATA10__DATA10__SHIFT 0x0 1224*81570d6dSHawking Zhang #define LSDMA_QUEUE0_MIDCMD_DATA10__DATA10_MASK 0xFFFFFFFFL 1225*81570d6dSHawking Zhang //LSDMA_QUEUE0_MIDCMD_CNTL 1226*81570d6dSHawking Zhang #define LSDMA_QUEUE0_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 1227*81570d6dSHawking Zhang #define LSDMA_QUEUE0_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 1228*81570d6dSHawking Zhang #define LSDMA_QUEUE0_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 1229*81570d6dSHawking Zhang #define LSDMA_QUEUE0_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 1230*81570d6dSHawking Zhang #define LSDMA_QUEUE0_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L 1231*81570d6dSHawking Zhang #define LSDMA_QUEUE0_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L 1232*81570d6dSHawking Zhang #define LSDMA_QUEUE0_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L 1233*81570d6dSHawking Zhang #define LSDMA_QUEUE0_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L 1234*81570d6dSHawking Zhang //LSDMA_QUEUE1_RB_CNTL 1235*81570d6dSHawking Zhang #define LSDMA_QUEUE1_RB_CNTL__RB_ENABLE__SHIFT 0x0 1236*81570d6dSHawking Zhang #define LSDMA_QUEUE1_RB_CNTL__RB_SIZE__SHIFT 0x1 1237*81570d6dSHawking Zhang #define LSDMA_QUEUE1_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 1238*81570d6dSHawking Zhang #define LSDMA_QUEUE1_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc 1239*81570d6dSHawking Zhang #define LSDMA_QUEUE1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd 1240*81570d6dSHawking Zhang #define LSDMA_QUEUE1_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 1241*81570d6dSHawking Zhang #define LSDMA_QUEUE1_RB_CNTL__RB_VMID__SHIFT 0x18 1242*81570d6dSHawking Zhang #define LSDMA_QUEUE1_RB_CNTL__RB_ENABLE_MASK 0x00000001L 1243*81570d6dSHawking Zhang #define LSDMA_QUEUE1_RB_CNTL__RB_SIZE_MASK 0x0000003EL 1244*81570d6dSHawking Zhang #define LSDMA_QUEUE1_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L 1245*81570d6dSHawking Zhang #define LSDMA_QUEUE1_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L 1246*81570d6dSHawking Zhang #define LSDMA_QUEUE1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L 1247*81570d6dSHawking Zhang #define LSDMA_QUEUE1_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L 1248*81570d6dSHawking Zhang #define LSDMA_QUEUE1_RB_CNTL__RB_VMID_MASK 0x0F000000L 1249*81570d6dSHawking Zhang //LSDMA_QUEUE1_RB_BASE 1250*81570d6dSHawking Zhang #define LSDMA_QUEUE1_RB_BASE__ADDR__SHIFT 0x0 1251*81570d6dSHawking Zhang #define LSDMA_QUEUE1_RB_BASE__ADDR_MASK 0xFFFFFFFFL 1252*81570d6dSHawking Zhang //LSDMA_QUEUE1_RB_BASE_HI 1253*81570d6dSHawking Zhang #define LSDMA_QUEUE1_RB_BASE_HI__ADDR__SHIFT 0x0 1254*81570d6dSHawking Zhang #define LSDMA_QUEUE1_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL 1255*81570d6dSHawking Zhang //LSDMA_QUEUE1_RB_RPTR 1256*81570d6dSHawking Zhang #define LSDMA_QUEUE1_RB_RPTR__OFFSET__SHIFT 0x0 1257*81570d6dSHawking Zhang #define LSDMA_QUEUE1_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL 1258*81570d6dSHawking Zhang //LSDMA_QUEUE1_RB_RPTR_HI 1259*81570d6dSHawking Zhang #define LSDMA_QUEUE1_RB_RPTR_HI__OFFSET__SHIFT 0x0 1260*81570d6dSHawking Zhang #define LSDMA_QUEUE1_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL 1261*81570d6dSHawking Zhang //LSDMA_QUEUE1_RB_WPTR 1262*81570d6dSHawking Zhang #define LSDMA_QUEUE1_RB_WPTR__OFFSET__SHIFT 0x0 1263*81570d6dSHawking Zhang #define LSDMA_QUEUE1_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL 1264*81570d6dSHawking Zhang //LSDMA_QUEUE1_RB_WPTR_HI 1265*81570d6dSHawking Zhang #define LSDMA_QUEUE1_RB_WPTR_HI__OFFSET__SHIFT 0x0 1266*81570d6dSHawking Zhang #define LSDMA_QUEUE1_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL 1267*81570d6dSHawking Zhang //LSDMA_QUEUE1_RB_WPTR_POLL_CNTL 1268*81570d6dSHawking Zhang #define LSDMA_QUEUE1_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 1269*81570d6dSHawking Zhang #define LSDMA_QUEUE1_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 1270*81570d6dSHawking Zhang #define LSDMA_QUEUE1_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 1271*81570d6dSHawking Zhang #define LSDMA_QUEUE1_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 1272*81570d6dSHawking Zhang #define LSDMA_QUEUE1_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 1273*81570d6dSHawking Zhang #define LSDMA_QUEUE1_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L 1274*81570d6dSHawking Zhang #define LSDMA_QUEUE1_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L 1275*81570d6dSHawking Zhang #define LSDMA_QUEUE1_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L 1276*81570d6dSHawking Zhang #define LSDMA_QUEUE1_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L 1277*81570d6dSHawking Zhang #define LSDMA_QUEUE1_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L 1278*81570d6dSHawking Zhang //LSDMA_QUEUE1_RB_RPTR_ADDR_HI 1279*81570d6dSHawking Zhang #define LSDMA_QUEUE1_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 1280*81570d6dSHawking Zhang #define LSDMA_QUEUE1_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1281*81570d6dSHawking Zhang //LSDMA_QUEUE1_RB_RPTR_ADDR_LO 1282*81570d6dSHawking Zhang #define LSDMA_QUEUE1_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 1283*81570d6dSHawking Zhang #define LSDMA_QUEUE1_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 1284*81570d6dSHawking Zhang #define LSDMA_QUEUE1_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L 1285*81570d6dSHawking Zhang #define LSDMA_QUEUE1_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1286*81570d6dSHawking Zhang //LSDMA_QUEUE1_IB_CNTL 1287*81570d6dSHawking Zhang #define LSDMA_QUEUE1_IB_CNTL__IB_ENABLE__SHIFT 0x0 1288*81570d6dSHawking Zhang #define LSDMA_QUEUE1_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 1289*81570d6dSHawking Zhang #define LSDMA_QUEUE1_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 1290*81570d6dSHawking Zhang #define LSDMA_QUEUE1_IB_CNTL__CMD_VMID__SHIFT 0x10 1291*81570d6dSHawking Zhang #define LSDMA_QUEUE1_IB_CNTL__IB_ENABLE_MASK 0x00000001L 1292*81570d6dSHawking Zhang #define LSDMA_QUEUE1_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L 1293*81570d6dSHawking Zhang #define LSDMA_QUEUE1_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L 1294*81570d6dSHawking Zhang #define LSDMA_QUEUE1_IB_CNTL__CMD_VMID_MASK 0x000F0000L 1295*81570d6dSHawking Zhang //LSDMA_QUEUE1_IB_RPTR 1296*81570d6dSHawking Zhang #define LSDMA_QUEUE1_IB_RPTR__OFFSET__SHIFT 0x2 1297*81570d6dSHawking Zhang #define LSDMA_QUEUE1_IB_RPTR__OFFSET_MASK 0x003FFFFCL 1298*81570d6dSHawking Zhang //LSDMA_QUEUE1_IB_OFFSET 1299*81570d6dSHawking Zhang #define LSDMA_QUEUE1_IB_OFFSET__OFFSET__SHIFT 0x2 1300*81570d6dSHawking Zhang #define LSDMA_QUEUE1_IB_OFFSET__OFFSET_MASK 0x003FFFFCL 1301*81570d6dSHawking Zhang //LSDMA_QUEUE1_IB_BASE_LO 1302*81570d6dSHawking Zhang #define LSDMA_QUEUE1_IB_BASE_LO__ADDR__SHIFT 0x5 1303*81570d6dSHawking Zhang #define LSDMA_QUEUE1_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L 1304*81570d6dSHawking Zhang //LSDMA_QUEUE1_IB_BASE_HI 1305*81570d6dSHawking Zhang #define LSDMA_QUEUE1_IB_BASE_HI__ADDR__SHIFT 0x0 1306*81570d6dSHawking Zhang #define LSDMA_QUEUE1_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL 1307*81570d6dSHawking Zhang //LSDMA_QUEUE1_IB_SIZE 1308*81570d6dSHawking Zhang #define LSDMA_QUEUE1_IB_SIZE__SIZE__SHIFT 0x0 1309*81570d6dSHawking Zhang #define LSDMA_QUEUE1_IB_SIZE__SIZE_MASK 0x000FFFFFL 1310*81570d6dSHawking Zhang //LSDMA_QUEUE1_SKIP_CNTL 1311*81570d6dSHawking Zhang #define LSDMA_QUEUE1_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 1312*81570d6dSHawking Zhang #define LSDMA_QUEUE1_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL 1313*81570d6dSHawking Zhang //LSDMA_QUEUE1_CONTEXT_STATUS 1314*81570d6dSHawking Zhang #define LSDMA_QUEUE1_CONTEXT_STATUS__SELECTED__SHIFT 0x0 1315*81570d6dSHawking Zhang #define LSDMA_QUEUE1_CONTEXT_STATUS__IDLE__SHIFT 0x2 1316*81570d6dSHawking Zhang #define LSDMA_QUEUE1_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 1317*81570d6dSHawking Zhang #define LSDMA_QUEUE1_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 1318*81570d6dSHawking Zhang #define LSDMA_QUEUE1_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 1319*81570d6dSHawking Zhang #define LSDMA_QUEUE1_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 1320*81570d6dSHawking Zhang #define LSDMA_QUEUE1_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 1321*81570d6dSHawking Zhang #define LSDMA_QUEUE1_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa 1322*81570d6dSHawking Zhang #define LSDMA_QUEUE1_CONTEXT_STATUS__SELECTED_MASK 0x00000001L 1323*81570d6dSHawking Zhang #define LSDMA_QUEUE1_CONTEXT_STATUS__IDLE_MASK 0x00000004L 1324*81570d6dSHawking Zhang #define LSDMA_QUEUE1_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L 1325*81570d6dSHawking Zhang #define LSDMA_QUEUE1_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L 1326*81570d6dSHawking Zhang #define LSDMA_QUEUE1_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L 1327*81570d6dSHawking Zhang #define LSDMA_QUEUE1_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L 1328*81570d6dSHawking Zhang #define LSDMA_QUEUE1_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L 1329*81570d6dSHawking Zhang #define LSDMA_QUEUE1_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L 1330*81570d6dSHawking Zhang //LSDMA_QUEUE1_DOORBELL 1331*81570d6dSHawking Zhang #define LSDMA_QUEUE1_DOORBELL__ENABLE__SHIFT 0x1c 1332*81570d6dSHawking Zhang #define LSDMA_QUEUE1_DOORBELL__CAPTURED__SHIFT 0x1e 1333*81570d6dSHawking Zhang #define LSDMA_QUEUE1_DOORBELL__ENABLE_MASK 0x10000000L 1334*81570d6dSHawking Zhang #define LSDMA_QUEUE1_DOORBELL__CAPTURED_MASK 0x40000000L 1335*81570d6dSHawking Zhang //LSDMA_QUEUE1_STATUS 1336*81570d6dSHawking Zhang #define LSDMA_QUEUE1_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 1337*81570d6dSHawking Zhang #define LSDMA_QUEUE1_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 1338*81570d6dSHawking Zhang #define LSDMA_QUEUE1_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL 1339*81570d6dSHawking Zhang #define LSDMA_QUEUE1_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L 1340*81570d6dSHawking Zhang //LSDMA_QUEUE1_DOORBELL_LOG 1341*81570d6dSHawking Zhang #define LSDMA_QUEUE1_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 1342*81570d6dSHawking Zhang #define LSDMA_QUEUE1_DOORBELL_LOG__DATA__SHIFT 0x2 1343*81570d6dSHawking Zhang #define LSDMA_QUEUE1_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L 1344*81570d6dSHawking Zhang #define LSDMA_QUEUE1_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL 1345*81570d6dSHawking Zhang //LSDMA_QUEUE1_WATERMARK 1346*81570d6dSHawking Zhang #define LSDMA_QUEUE1_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 1347*81570d6dSHawking Zhang #define LSDMA_QUEUE1_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 1348*81570d6dSHawking Zhang #define LSDMA_QUEUE1_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL 1349*81570d6dSHawking Zhang #define LSDMA_QUEUE1_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L 1350*81570d6dSHawking Zhang //LSDMA_QUEUE1_DOORBELL_OFFSET 1351*81570d6dSHawking Zhang #define LSDMA_QUEUE1_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 1352*81570d6dSHawking Zhang #define LSDMA_QUEUE1_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL 1353*81570d6dSHawking Zhang //LSDMA_QUEUE1_CSA_ADDR_LO 1354*81570d6dSHawking Zhang #define LSDMA_QUEUE1_CSA_ADDR_LO__ADDR__SHIFT 0x2 1355*81570d6dSHawking Zhang #define LSDMA_QUEUE1_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1356*81570d6dSHawking Zhang //LSDMA_QUEUE1_CSA_ADDR_HI 1357*81570d6dSHawking Zhang #define LSDMA_QUEUE1_CSA_ADDR_HI__ADDR__SHIFT 0x0 1358*81570d6dSHawking Zhang #define LSDMA_QUEUE1_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1359*81570d6dSHawking Zhang //LSDMA_QUEUE1_RB_PREEMPT 1360*81570d6dSHawking Zhang #define LSDMA_QUEUE1_RB_PREEMPT__PREEMPT_REQ__SHIFT 0x0 1361*81570d6dSHawking Zhang #define LSDMA_QUEUE1_RB_PREEMPT__PREEMPT_REQ_MASK 0x00000001L 1362*81570d6dSHawking Zhang //LSDMA_QUEUE1_IB_SUB_REMAIN 1363*81570d6dSHawking Zhang #define LSDMA_QUEUE1_IB_SUB_REMAIN__SIZE__SHIFT 0x0 1364*81570d6dSHawking Zhang #define LSDMA_QUEUE1_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL 1365*81570d6dSHawking Zhang //LSDMA_QUEUE1_PREEMPT 1366*81570d6dSHawking Zhang #define LSDMA_QUEUE1_PREEMPT__IB_PREEMPT__SHIFT 0x0 1367*81570d6dSHawking Zhang #define LSDMA_QUEUE1_PREEMPT__IB_PREEMPT_MASK 0x00000001L 1368*81570d6dSHawking Zhang //LSDMA_QUEUE1_DUMMY0 1369*81570d6dSHawking Zhang #define LSDMA_QUEUE1_DUMMY0__DUMMY__SHIFT 0x0 1370*81570d6dSHawking Zhang #define LSDMA_QUEUE1_DUMMY0__DUMMY_MASK 0xFFFFFFFFL 1371*81570d6dSHawking Zhang //LSDMA_QUEUE1_RB_WPTR_POLL_ADDR_HI 1372*81570d6dSHawking Zhang #define LSDMA_QUEUE1_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 1373*81570d6dSHawking Zhang #define LSDMA_QUEUE1_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1374*81570d6dSHawking Zhang //LSDMA_QUEUE1_RB_WPTR_POLL_ADDR_LO 1375*81570d6dSHawking Zhang #define LSDMA_QUEUE1_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 1376*81570d6dSHawking Zhang #define LSDMA_QUEUE1_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1377*81570d6dSHawking Zhang //LSDMA_QUEUE1_RB_AQL_CNTL 1378*81570d6dSHawking Zhang #define LSDMA_QUEUE1_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 1379*81570d6dSHawking Zhang #define LSDMA_QUEUE1_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 1380*81570d6dSHawking Zhang #define LSDMA_QUEUE1_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 1381*81570d6dSHawking Zhang #define LSDMA_QUEUE1_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L 1382*81570d6dSHawking Zhang #define LSDMA_QUEUE1_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL 1383*81570d6dSHawking Zhang #define LSDMA_QUEUE1_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L 1384*81570d6dSHawking Zhang //LSDMA_QUEUE1_MINOR_PTR_UPDATE 1385*81570d6dSHawking Zhang #define LSDMA_QUEUE1_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 1386*81570d6dSHawking Zhang #define LSDMA_QUEUE1_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L 1387*81570d6dSHawking Zhang //LSDMA_QUEUE1_CNTL 1388*81570d6dSHawking Zhang #define LSDMA_QUEUE1_CNTL__QUANTUM__SHIFT 0x0 1389*81570d6dSHawking Zhang #define LSDMA_QUEUE1_CNTL__QUANTUM_MASK 0x000000FFL 1390*81570d6dSHawking Zhang //LSDMA_QUEUE1_DUMMY1 1391*81570d6dSHawking Zhang #define LSDMA_QUEUE1_DUMMY1__DUMMY__SHIFT 0x0 1392*81570d6dSHawking Zhang #define LSDMA_QUEUE1_DUMMY1__DUMMY_MASK 0xFFFFFFFFL 1393*81570d6dSHawking Zhang //LSDMA_QUEUE1_DUMMY2 1394*81570d6dSHawking Zhang #define LSDMA_QUEUE1_DUMMY2__DUMMY__SHIFT 0x0 1395*81570d6dSHawking Zhang #define LSDMA_QUEUE1_DUMMY2__DUMMY_MASK 0xFFFFFFFFL 1396*81570d6dSHawking Zhang //LSDMA_QUEUE1_MIDCMD_DATA0 1397*81570d6dSHawking Zhang #define LSDMA_QUEUE1_MIDCMD_DATA0__DATA0__SHIFT 0x0 1398*81570d6dSHawking Zhang #define LSDMA_QUEUE1_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL 1399*81570d6dSHawking Zhang //LSDMA_QUEUE1_MIDCMD_DATA1 1400*81570d6dSHawking Zhang #define LSDMA_QUEUE1_MIDCMD_DATA1__DATA1__SHIFT 0x0 1401*81570d6dSHawking Zhang #define LSDMA_QUEUE1_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL 1402*81570d6dSHawking Zhang //LSDMA_QUEUE1_MIDCMD_DATA2 1403*81570d6dSHawking Zhang #define LSDMA_QUEUE1_MIDCMD_DATA2__DATA2__SHIFT 0x0 1404*81570d6dSHawking Zhang #define LSDMA_QUEUE1_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL 1405*81570d6dSHawking Zhang //LSDMA_QUEUE1_MIDCMD_DATA3 1406*81570d6dSHawking Zhang #define LSDMA_QUEUE1_MIDCMD_DATA3__DATA3__SHIFT 0x0 1407*81570d6dSHawking Zhang #define LSDMA_QUEUE1_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL 1408*81570d6dSHawking Zhang //LSDMA_QUEUE1_MIDCMD_DATA4 1409*81570d6dSHawking Zhang #define LSDMA_QUEUE1_MIDCMD_DATA4__DATA4__SHIFT 0x0 1410*81570d6dSHawking Zhang #define LSDMA_QUEUE1_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL 1411*81570d6dSHawking Zhang //LSDMA_QUEUE1_MIDCMD_DATA5 1412*81570d6dSHawking Zhang #define LSDMA_QUEUE1_MIDCMD_DATA5__DATA5__SHIFT 0x0 1413*81570d6dSHawking Zhang #define LSDMA_QUEUE1_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL 1414*81570d6dSHawking Zhang //LSDMA_QUEUE1_MIDCMD_DATA6 1415*81570d6dSHawking Zhang #define LSDMA_QUEUE1_MIDCMD_DATA6__DATA6__SHIFT 0x0 1416*81570d6dSHawking Zhang #define LSDMA_QUEUE1_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL 1417*81570d6dSHawking Zhang //LSDMA_QUEUE1_MIDCMD_DATA7 1418*81570d6dSHawking Zhang #define LSDMA_QUEUE1_MIDCMD_DATA7__DATA7__SHIFT 0x0 1419*81570d6dSHawking Zhang #define LSDMA_QUEUE1_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL 1420*81570d6dSHawking Zhang //LSDMA_QUEUE1_MIDCMD_DATA8 1421*81570d6dSHawking Zhang #define LSDMA_QUEUE1_MIDCMD_DATA8__DATA8__SHIFT 0x0 1422*81570d6dSHawking Zhang #define LSDMA_QUEUE1_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL 1423*81570d6dSHawking Zhang //LSDMA_QUEUE1_MIDCMD_DATA9 1424*81570d6dSHawking Zhang #define LSDMA_QUEUE1_MIDCMD_DATA9__DATA9__SHIFT 0x0 1425*81570d6dSHawking Zhang #define LSDMA_QUEUE1_MIDCMD_DATA9__DATA9_MASK 0xFFFFFFFFL 1426*81570d6dSHawking Zhang //LSDMA_QUEUE1_MIDCMD_DATA10 1427*81570d6dSHawking Zhang #define LSDMA_QUEUE1_MIDCMD_DATA10__DATA10__SHIFT 0x0 1428*81570d6dSHawking Zhang #define LSDMA_QUEUE1_MIDCMD_DATA10__DATA10_MASK 0xFFFFFFFFL 1429*81570d6dSHawking Zhang //LSDMA_QUEUE1_MIDCMD_CNTL 1430*81570d6dSHawking Zhang #define LSDMA_QUEUE1_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 1431*81570d6dSHawking Zhang #define LSDMA_QUEUE1_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 1432*81570d6dSHawking Zhang #define LSDMA_QUEUE1_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 1433*81570d6dSHawking Zhang #define LSDMA_QUEUE1_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 1434*81570d6dSHawking Zhang #define LSDMA_QUEUE1_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L 1435*81570d6dSHawking Zhang #define LSDMA_QUEUE1_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L 1436*81570d6dSHawking Zhang #define LSDMA_QUEUE1_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L 1437*81570d6dSHawking Zhang #define LSDMA_QUEUE1_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L 1438*81570d6dSHawking Zhang 1439*81570d6dSHawking Zhang #endif 1440