1*81570d6dSHawking Zhang /* 2*81570d6dSHawking Zhang * Copyright 2021 Advanced Micro Devices, Inc. 3*81570d6dSHawking Zhang * 4*81570d6dSHawking Zhang * Permission is hereby granted, free of charge, to any person obtaining a 5*81570d6dSHawking Zhang * copy of this software and associated documentation files (the "Software"), 6*81570d6dSHawking Zhang * to deal in the Software without restriction, including without limitation 7*81570d6dSHawking Zhang * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8*81570d6dSHawking Zhang * and/or sell copies of the Software, and to permit persons to whom the 9*81570d6dSHawking Zhang * Software is furnished to do so, subject to the following conditions: 10*81570d6dSHawking Zhang * 11*81570d6dSHawking Zhang * The above copyright notice and this permission notice shall be included in 12*81570d6dSHawking Zhang * all copies or substantial portions of the Software. 13*81570d6dSHawking Zhang * 14*81570d6dSHawking Zhang * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15*81570d6dSHawking Zhang * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16*81570d6dSHawking Zhang * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17*81570d6dSHawking Zhang * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18*81570d6dSHawking Zhang * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19*81570d6dSHawking Zhang * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20*81570d6dSHawking Zhang * OTHER DEALINGS IN THE SOFTWARE. 21*81570d6dSHawking Zhang * 22*81570d6dSHawking Zhang */ 23*81570d6dSHawking Zhang #ifndef _lsdma_6_0_0_OFFSET_HEADER 24*81570d6dSHawking Zhang #define _lsdma_6_0_0_OFFSET_HEADER 25*81570d6dSHawking Zhang 26*81570d6dSHawking Zhang 27*81570d6dSHawking Zhang 28*81570d6dSHawking Zhang // addressBlock: lsdma0_lsdma0dec 29*81570d6dSHawking Zhang // base address: 0x45000 30*81570d6dSHawking Zhang #define regLSDMA_UCODE_ADDR 0x0000 31*81570d6dSHawking Zhang #define regLSDMA_UCODE_ADDR_BASE_IDX 0 32*81570d6dSHawking Zhang #define regLSDMA_UCODE_DATA 0x0001 33*81570d6dSHawking Zhang #define regLSDMA_UCODE_DATA_BASE_IDX 0 34*81570d6dSHawking Zhang #define regLSDMA_ERROR_INJECT_CNTL 0x0004 35*81570d6dSHawking Zhang #define regLSDMA_ERROR_INJECT_CNTL_BASE_IDX 0 36*81570d6dSHawking Zhang #define regLSDMA_ERROR_INJECT_SELECT 0x0005 37*81570d6dSHawking Zhang #define regLSDMA_ERROR_INJECT_SELECT_BASE_IDX 0 38*81570d6dSHawking Zhang #define regLSDMA_CONTEXT_GROUP_BOUNDARY 0x001f 39*81570d6dSHawking Zhang #define regLSDMA_CONTEXT_GROUP_BOUNDARY_BASE_IDX 0 40*81570d6dSHawking Zhang #define regLSDMA_RB_RPTR_FETCH_HI 0x0020 41*81570d6dSHawking Zhang #define regLSDMA_RB_RPTR_FETCH_HI_BASE_IDX 0 42*81570d6dSHawking Zhang #define regLSDMA_SEM_WAIT_FAIL_TIMER_CNTL 0x0021 43*81570d6dSHawking Zhang #define regLSDMA_SEM_WAIT_FAIL_TIMER_CNTL_BASE_IDX 0 44*81570d6dSHawking Zhang #define regLSDMA_RB_RPTR_FETCH 0x0022 45*81570d6dSHawking Zhang #define regLSDMA_RB_RPTR_FETCH_BASE_IDX 0 46*81570d6dSHawking Zhang #define regLSDMA_IB_OFFSET_FETCH 0x0023 47*81570d6dSHawking Zhang #define regLSDMA_IB_OFFSET_FETCH_BASE_IDX 0 48*81570d6dSHawking Zhang #define regLSDMA_PROGRAM 0x0024 49*81570d6dSHawking Zhang #define regLSDMA_PROGRAM_BASE_IDX 0 50*81570d6dSHawking Zhang #define regLSDMA_STATUS_REG 0x0025 51*81570d6dSHawking Zhang #define regLSDMA_STATUS_REG_BASE_IDX 0 52*81570d6dSHawking Zhang #define regLSDMA_STATUS1_REG 0x0026 53*81570d6dSHawking Zhang #define regLSDMA_STATUS1_REG_BASE_IDX 0 54*81570d6dSHawking Zhang #define regLSDMA_RD_BURST_CNTL 0x0027 55*81570d6dSHawking Zhang #define regLSDMA_RD_BURST_CNTL_BASE_IDX 0 56*81570d6dSHawking Zhang #define regLSDMA_HBM_PAGE_CONFIG 0x0028 57*81570d6dSHawking Zhang #define regLSDMA_HBM_PAGE_CONFIG_BASE_IDX 0 58*81570d6dSHawking Zhang #define regLSDMA_UCODE_CHECKSUM 0x0029 59*81570d6dSHawking Zhang #define regLSDMA_UCODE_CHECKSUM_BASE_IDX 0 60*81570d6dSHawking Zhang #define regLSDMA_FREEZE 0x002b 61*81570d6dSHawking Zhang #define regLSDMA_FREEZE_BASE_IDX 0 62*81570d6dSHawking Zhang #define regLSDMA_PF_PIO_STATUS 0x002c 63*81570d6dSHawking Zhang #define regLSDMA_PF_PIO_STATUS_BASE_IDX 0 64*81570d6dSHawking Zhang #define regLSDMA_VF_PIO_STATUS 0x002d 65*81570d6dSHawking Zhang #define regLSDMA_VF_PIO_STATUS_BASE_IDX 0 66*81570d6dSHawking Zhang #define regLSDMA_POWER_GATING 0x002e 67*81570d6dSHawking Zhang #define regLSDMA_POWER_GATING_BASE_IDX 0 68*81570d6dSHawking Zhang #define regLSDMA_PGFSM_CONFIG 0x002f 69*81570d6dSHawking Zhang #define regLSDMA_PGFSM_CONFIG_BASE_IDX 0 70*81570d6dSHawking Zhang #define regLSDMA_PGFSM_WRITE 0x0030 71*81570d6dSHawking Zhang #define regLSDMA_PGFSM_WRITE_BASE_IDX 0 72*81570d6dSHawking Zhang #define regLSDMA_PGFSM_READ 0x0031 73*81570d6dSHawking Zhang #define regLSDMA_PGFSM_READ_BASE_IDX 0 74*81570d6dSHawking Zhang #define regLSDMA_PIO_STATUS 0x0032 75*81570d6dSHawking Zhang #define regLSDMA_PIO_STATUS_BASE_IDX 0 76*81570d6dSHawking Zhang #define regLSDMA_BA_THRESHOLD 0x0033 77*81570d6dSHawking Zhang #define regLSDMA_BA_THRESHOLD_BASE_IDX 0 78*81570d6dSHawking Zhang #define regLSDMA_ID 0x0034 79*81570d6dSHawking Zhang #define regLSDMA_ID_BASE_IDX 0 80*81570d6dSHawking Zhang #define regLSDMA_VERSION 0x0035 81*81570d6dSHawking Zhang #define regLSDMA_VERSION_BASE_IDX 0 82*81570d6dSHawking Zhang #define regLSDMA_EDC_COUNTER 0x0036 83*81570d6dSHawking Zhang #define regLSDMA_EDC_COUNTER_BASE_IDX 0 84*81570d6dSHawking Zhang #define regLSDMA_EDC_COUNTER2 0x0037 85*81570d6dSHawking Zhang #define regLSDMA_EDC_COUNTER2_BASE_IDX 0 86*81570d6dSHawking Zhang #define regLSDMA_STATUS2_REG 0x0038 87*81570d6dSHawking Zhang #define regLSDMA_STATUS2_REG_BASE_IDX 0 88*81570d6dSHawking Zhang #define regLSDMA_ATOMIC_CNTL 0x0039 89*81570d6dSHawking Zhang #define regLSDMA_ATOMIC_CNTL_BASE_IDX 0 90*81570d6dSHawking Zhang #define regLSDMA_ATOMIC_PREOP_LO 0x003a 91*81570d6dSHawking Zhang #define regLSDMA_ATOMIC_PREOP_LO_BASE_IDX 0 92*81570d6dSHawking Zhang #define regLSDMA_ATOMIC_PREOP_HI 0x003b 93*81570d6dSHawking Zhang #define regLSDMA_ATOMIC_PREOP_HI_BASE_IDX 0 94*81570d6dSHawking Zhang #define regLSDMA_UTCL1_CNTL 0x003c 95*81570d6dSHawking Zhang #define regLSDMA_UTCL1_CNTL_BASE_IDX 0 96*81570d6dSHawking Zhang #define regLSDMA_UTCL1_WATERMK 0x003d 97*81570d6dSHawking Zhang #define regLSDMA_UTCL1_WATERMK_BASE_IDX 0 98*81570d6dSHawking Zhang #define regLSDMA_UTCL1_RD_STATUS 0x003e 99*81570d6dSHawking Zhang #define regLSDMA_UTCL1_RD_STATUS_BASE_IDX 0 100*81570d6dSHawking Zhang #define regLSDMA_UTCL1_WR_STATUS 0x003f 101*81570d6dSHawking Zhang #define regLSDMA_UTCL1_WR_STATUS_BASE_IDX 0 102*81570d6dSHawking Zhang #define regLSDMA_UTCL1_INV0 0x0040 103*81570d6dSHawking Zhang #define regLSDMA_UTCL1_INV0_BASE_IDX 0 104*81570d6dSHawking Zhang #define regLSDMA_UTCL1_INV1 0x0041 105*81570d6dSHawking Zhang #define regLSDMA_UTCL1_INV1_BASE_IDX 0 106*81570d6dSHawking Zhang #define regLSDMA_UTCL1_INV2 0x0042 107*81570d6dSHawking Zhang #define regLSDMA_UTCL1_INV2_BASE_IDX 0 108*81570d6dSHawking Zhang #define regLSDMA_UTCL1_RD_XNACK0 0x0043 109*81570d6dSHawking Zhang #define regLSDMA_UTCL1_RD_XNACK0_BASE_IDX 0 110*81570d6dSHawking Zhang #define regLSDMA_UTCL1_RD_XNACK1 0x0044 111*81570d6dSHawking Zhang #define regLSDMA_UTCL1_RD_XNACK1_BASE_IDX 0 112*81570d6dSHawking Zhang #define regLSDMA_UTCL1_WR_XNACK0 0x0045 113*81570d6dSHawking Zhang #define regLSDMA_UTCL1_WR_XNACK0_BASE_IDX 0 114*81570d6dSHawking Zhang #define regLSDMA_UTCL1_WR_XNACK1 0x0046 115*81570d6dSHawking Zhang #define regLSDMA_UTCL1_WR_XNACK1_BASE_IDX 0 116*81570d6dSHawking Zhang #define regLSDMA_UTCL1_TIMEOUT 0x0047 117*81570d6dSHawking Zhang #define regLSDMA_UTCL1_TIMEOUT_BASE_IDX 0 118*81570d6dSHawking Zhang #define regLSDMA_UTCL1_PAGE 0x0048 119*81570d6dSHawking Zhang #define regLSDMA_UTCL1_PAGE_BASE_IDX 0 120*81570d6dSHawking Zhang #define regLSDMA_RELAX_ORDERING_LUT 0x004a 121*81570d6dSHawking Zhang #define regLSDMA_RELAX_ORDERING_LUT_BASE_IDX 0 122*81570d6dSHawking Zhang #define regLSDMA_CHICKEN_BITS_2 0x004b 123*81570d6dSHawking Zhang #define regLSDMA_CHICKEN_BITS_2_BASE_IDX 0 124*81570d6dSHawking Zhang #define regLSDMA_STATUS3_REG 0x004c 125*81570d6dSHawking Zhang #define regLSDMA_STATUS3_REG_BASE_IDX 0 126*81570d6dSHawking Zhang #define regLSDMA_PHYSICAL_ADDR_LO 0x004d 127*81570d6dSHawking Zhang #define regLSDMA_PHYSICAL_ADDR_LO_BASE_IDX 0 128*81570d6dSHawking Zhang #define regLSDMA_PHYSICAL_ADDR_HI 0x004e 129*81570d6dSHawking Zhang #define regLSDMA_PHYSICAL_ADDR_HI_BASE_IDX 0 130*81570d6dSHawking Zhang #define regLSDMA_ECC_CNTL 0x004f 131*81570d6dSHawking Zhang #define regLSDMA_ECC_CNTL_BASE_IDX 0 132*81570d6dSHawking Zhang #define regLSDMA_ERROR_LOG 0x0050 133*81570d6dSHawking Zhang #define regLSDMA_ERROR_LOG_BASE_IDX 0 134*81570d6dSHawking Zhang #define regLSDMA_PUB_DUMMY0 0x0051 135*81570d6dSHawking Zhang #define regLSDMA_PUB_DUMMY0_BASE_IDX 0 136*81570d6dSHawking Zhang #define regLSDMA_PUB_DUMMY1 0x0052 137*81570d6dSHawking Zhang #define regLSDMA_PUB_DUMMY1_BASE_IDX 0 138*81570d6dSHawking Zhang #define regLSDMA_PUB_DUMMY2 0x0053 139*81570d6dSHawking Zhang #define regLSDMA_PUB_DUMMY2_BASE_IDX 0 140*81570d6dSHawking Zhang #define regLSDMA_PUB_DUMMY3 0x0054 141*81570d6dSHawking Zhang #define regLSDMA_PUB_DUMMY3_BASE_IDX 0 142*81570d6dSHawking Zhang #define regLSDMA_F32_COUNTER 0x0055 143*81570d6dSHawking Zhang #define regLSDMA_F32_COUNTER_BASE_IDX 0 144*81570d6dSHawking Zhang #define regLSDMA_PERFCNT_PERFCOUNTER0_CFG 0x0057 145*81570d6dSHawking Zhang #define regLSDMA_PERFCNT_PERFCOUNTER0_CFG_BASE_IDX 0 146*81570d6dSHawking Zhang #define regLSDMA_PERFCNT_PERFCOUNTER1_CFG 0x0058 147*81570d6dSHawking Zhang #define regLSDMA_PERFCNT_PERFCOUNTER1_CFG_BASE_IDX 0 148*81570d6dSHawking Zhang #define regLSDMA_PERFCNT_PERFCOUNTER_RSLT_CNTL 0x0059 149*81570d6dSHawking Zhang #define regLSDMA_PERFCNT_PERFCOUNTER_RSLT_CNTL_BASE_IDX 0 150*81570d6dSHawking Zhang #define regLSDMA_PERFCNT_MISC_CNTL 0x005a 151*81570d6dSHawking Zhang #define regLSDMA_PERFCNT_MISC_CNTL_BASE_IDX 0 152*81570d6dSHawking Zhang #define regLSDMA_PERFCNT_PERFCOUNTER_LO 0x005b 153*81570d6dSHawking Zhang #define regLSDMA_PERFCNT_PERFCOUNTER_LO_BASE_IDX 0 154*81570d6dSHawking Zhang #define regLSDMA_PERFCNT_PERFCOUNTER_HI 0x005c 155*81570d6dSHawking Zhang #define regLSDMA_PERFCNT_PERFCOUNTER_HI_BASE_IDX 0 156*81570d6dSHawking Zhang #define regLSDMA_CRD_CNTL 0x005d 157*81570d6dSHawking Zhang #define regLSDMA_CRD_CNTL_BASE_IDX 0 158*81570d6dSHawking Zhang #define regLSDMA_ULV_CNTL 0x005f 159*81570d6dSHawking Zhang #define regLSDMA_ULV_CNTL_BASE_IDX 0 160*81570d6dSHawking Zhang #define regLSDMA_EA_DBIT_ADDR_DATA 0x0060 161*81570d6dSHawking Zhang #define regLSDMA_EA_DBIT_ADDR_DATA_BASE_IDX 0 162*81570d6dSHawking Zhang #define regLSDMA_EA_DBIT_ADDR_INDEX 0x0061 163*81570d6dSHawking Zhang #define regLSDMA_EA_DBIT_ADDR_INDEX_BASE_IDX 0 164*81570d6dSHawking Zhang #define regLSDMA_STATUS4_REG 0x0063 165*81570d6dSHawking Zhang #define regLSDMA_STATUS4_REG_BASE_IDX 0 166*81570d6dSHawking Zhang #define regLSDMA_CE_CTRL 0x0066 167*81570d6dSHawking Zhang #define regLSDMA_CE_CTRL_BASE_IDX 0 168*81570d6dSHawking Zhang #define regLSDMA_EXCEPTION_STATUS 0x0067 169*81570d6dSHawking Zhang #define regLSDMA_EXCEPTION_STATUS_BASE_IDX 0 170*81570d6dSHawking Zhang #define regLSDMA_PIO_SRC_ADDR_LO 0x0069 171*81570d6dSHawking Zhang #define regLSDMA_PIO_SRC_ADDR_LO_BASE_IDX 0 172*81570d6dSHawking Zhang #define regLSDMA_PIO_SRC_ADDR_HI 0x006a 173*81570d6dSHawking Zhang #define regLSDMA_PIO_SRC_ADDR_HI_BASE_IDX 0 174*81570d6dSHawking Zhang #define regLSDMA_PIO_DST_ADDR_LO 0x006b 175*81570d6dSHawking Zhang #define regLSDMA_PIO_DST_ADDR_LO_BASE_IDX 0 176*81570d6dSHawking Zhang #define regLSDMA_PIO_DST_ADDR_HI 0x006c 177*81570d6dSHawking Zhang #define regLSDMA_PIO_DST_ADDR_HI_BASE_IDX 0 178*81570d6dSHawking Zhang #define regLSDMA_PIO_COMMAND 0x006d 179*81570d6dSHawking Zhang #define regLSDMA_PIO_COMMAND_BASE_IDX 0 180*81570d6dSHawking Zhang #define regLSDMA_PIO_CONSTFILL_DATA 0x006e 181*81570d6dSHawking Zhang #define regLSDMA_PIO_CONSTFILL_DATA_BASE_IDX 0 182*81570d6dSHawking Zhang #define regLSDMA_PIO_CONTROL 0x006f 183*81570d6dSHawking Zhang #define regLSDMA_PIO_CONTROL_BASE_IDX 0 184*81570d6dSHawking Zhang #define regLSDMA_INT_CNTL 0x0070 185*81570d6dSHawking Zhang #define regLSDMA_INT_CNTL_BASE_IDX 0 186*81570d6dSHawking Zhang #define regLSDMA_MEM_POWER_CTRL 0x0071 187*81570d6dSHawking Zhang #define regLSDMA_MEM_POWER_CTRL_BASE_IDX 0 188*81570d6dSHawking Zhang #define regLSDMA_CLK_CTRL 0x0072 189*81570d6dSHawking Zhang #define regLSDMA_CLK_CTRL_BASE_IDX 0 190*81570d6dSHawking Zhang #define regLSDMA_CNTL 0x0073 191*81570d6dSHawking Zhang #define regLSDMA_CNTL_BASE_IDX 0 192*81570d6dSHawking Zhang #define regLSDMA_CHICKEN_BITS 0x0074 193*81570d6dSHawking Zhang #define regLSDMA_CHICKEN_BITS_BASE_IDX 0 194*81570d6dSHawking Zhang #define regLSDMA_GB_ADDR_CONFIG 0x0075 195*81570d6dSHawking Zhang #define regLSDMA_GB_ADDR_CONFIG_BASE_IDX 0 196*81570d6dSHawking Zhang #define regLSDMA_GB_ADDR_CONFIG_READ 0x0076 197*81570d6dSHawking Zhang #define regLSDMA_GB_ADDR_CONFIG_READ_BASE_IDX 0 198*81570d6dSHawking Zhang #define regLSDMA_QUEUE0_RB_CNTL 0x0080 199*81570d6dSHawking Zhang #define regLSDMA_QUEUE0_RB_CNTL_BASE_IDX 0 200*81570d6dSHawking Zhang #define regLSDMA_QUEUE0_RB_BASE 0x0081 201*81570d6dSHawking Zhang #define regLSDMA_QUEUE0_RB_BASE_BASE_IDX 0 202*81570d6dSHawking Zhang #define regLSDMA_QUEUE0_RB_BASE_HI 0x0082 203*81570d6dSHawking Zhang #define regLSDMA_QUEUE0_RB_BASE_HI_BASE_IDX 0 204*81570d6dSHawking Zhang #define regLSDMA_QUEUE0_RB_RPTR 0x0083 205*81570d6dSHawking Zhang #define regLSDMA_QUEUE0_RB_RPTR_BASE_IDX 0 206*81570d6dSHawking Zhang #define regLSDMA_QUEUE0_RB_RPTR_HI 0x0084 207*81570d6dSHawking Zhang #define regLSDMA_QUEUE0_RB_RPTR_HI_BASE_IDX 0 208*81570d6dSHawking Zhang #define regLSDMA_QUEUE0_RB_WPTR 0x0085 209*81570d6dSHawking Zhang #define regLSDMA_QUEUE0_RB_WPTR_BASE_IDX 0 210*81570d6dSHawking Zhang #define regLSDMA_QUEUE0_RB_WPTR_HI 0x0086 211*81570d6dSHawking Zhang #define regLSDMA_QUEUE0_RB_WPTR_HI_BASE_IDX 0 212*81570d6dSHawking Zhang #define regLSDMA_QUEUE0_RB_WPTR_POLL_CNTL 0x0087 213*81570d6dSHawking Zhang #define regLSDMA_QUEUE0_RB_WPTR_POLL_CNTL_BASE_IDX 0 214*81570d6dSHawking Zhang #define regLSDMA_QUEUE0_RB_RPTR_ADDR_HI 0x0088 215*81570d6dSHawking Zhang #define regLSDMA_QUEUE0_RB_RPTR_ADDR_HI_BASE_IDX 0 216*81570d6dSHawking Zhang #define regLSDMA_QUEUE0_RB_RPTR_ADDR_LO 0x0089 217*81570d6dSHawking Zhang #define regLSDMA_QUEUE0_RB_RPTR_ADDR_LO_BASE_IDX 0 218*81570d6dSHawking Zhang #define regLSDMA_QUEUE0_IB_CNTL 0x008a 219*81570d6dSHawking Zhang #define regLSDMA_QUEUE0_IB_CNTL_BASE_IDX 0 220*81570d6dSHawking Zhang #define regLSDMA_QUEUE0_IB_RPTR 0x008b 221*81570d6dSHawking Zhang #define regLSDMA_QUEUE0_IB_RPTR_BASE_IDX 0 222*81570d6dSHawking Zhang #define regLSDMA_QUEUE0_IB_OFFSET 0x008c 223*81570d6dSHawking Zhang #define regLSDMA_QUEUE0_IB_OFFSET_BASE_IDX 0 224*81570d6dSHawking Zhang #define regLSDMA_QUEUE0_IB_BASE_LO 0x008d 225*81570d6dSHawking Zhang #define regLSDMA_QUEUE0_IB_BASE_LO_BASE_IDX 0 226*81570d6dSHawking Zhang #define regLSDMA_QUEUE0_IB_BASE_HI 0x008e 227*81570d6dSHawking Zhang #define regLSDMA_QUEUE0_IB_BASE_HI_BASE_IDX 0 228*81570d6dSHawking Zhang #define regLSDMA_QUEUE0_IB_SIZE 0x008f 229*81570d6dSHawking Zhang #define regLSDMA_QUEUE0_IB_SIZE_BASE_IDX 0 230*81570d6dSHawking Zhang #define regLSDMA_QUEUE0_SKIP_CNTL 0x0090 231*81570d6dSHawking Zhang #define regLSDMA_QUEUE0_SKIP_CNTL_BASE_IDX 0 232*81570d6dSHawking Zhang #define regLSDMA_QUEUE0_CONTEXT_STATUS 0x0091 233*81570d6dSHawking Zhang #define regLSDMA_QUEUE0_CONTEXT_STATUS_BASE_IDX 0 234*81570d6dSHawking Zhang #define regLSDMA_QUEUE0_DOORBELL 0x0092 235*81570d6dSHawking Zhang #define regLSDMA_QUEUE0_DOORBELL_BASE_IDX 0 236*81570d6dSHawking Zhang #define regLSDMA_QUEUE0_STATUS 0x00a8 237*81570d6dSHawking Zhang #define regLSDMA_QUEUE0_STATUS_BASE_IDX 0 238*81570d6dSHawking Zhang #define regLSDMA_QUEUE0_DOORBELL_LOG 0x00a9 239*81570d6dSHawking Zhang #define regLSDMA_QUEUE0_DOORBELL_LOG_BASE_IDX 0 240*81570d6dSHawking Zhang #define regLSDMA_QUEUE0_WATERMARK 0x00aa 241*81570d6dSHawking Zhang #define regLSDMA_QUEUE0_WATERMARK_BASE_IDX 0 242*81570d6dSHawking Zhang #define regLSDMA_QUEUE0_DOORBELL_OFFSET 0x00ab 243*81570d6dSHawking Zhang #define regLSDMA_QUEUE0_DOORBELL_OFFSET_BASE_IDX 0 244*81570d6dSHawking Zhang #define regLSDMA_QUEUE0_CSA_ADDR_LO 0x00ac 245*81570d6dSHawking Zhang #define regLSDMA_QUEUE0_CSA_ADDR_LO_BASE_IDX 0 246*81570d6dSHawking Zhang #define regLSDMA_QUEUE0_CSA_ADDR_HI 0x00ad 247*81570d6dSHawking Zhang #define regLSDMA_QUEUE0_CSA_ADDR_HI_BASE_IDX 0 248*81570d6dSHawking Zhang #define regLSDMA_QUEUE0_RB_PREEMPT 0x00ae 249*81570d6dSHawking Zhang #define regLSDMA_QUEUE0_RB_PREEMPT_BASE_IDX 0 250*81570d6dSHawking Zhang #define regLSDMA_QUEUE0_IB_SUB_REMAIN 0x00af 251*81570d6dSHawking Zhang #define regLSDMA_QUEUE0_IB_SUB_REMAIN_BASE_IDX 0 252*81570d6dSHawking Zhang #define regLSDMA_QUEUE0_PREEMPT 0x00b0 253*81570d6dSHawking Zhang #define regLSDMA_QUEUE0_PREEMPT_BASE_IDX 0 254*81570d6dSHawking Zhang #define regLSDMA_QUEUE0_DUMMY0 0x00b1 255*81570d6dSHawking Zhang #define regLSDMA_QUEUE0_DUMMY0_BASE_IDX 0 256*81570d6dSHawking Zhang #define regLSDMA_QUEUE0_RB_WPTR_POLL_ADDR_HI 0x00b2 257*81570d6dSHawking Zhang #define regLSDMA_QUEUE0_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 258*81570d6dSHawking Zhang #define regLSDMA_QUEUE0_RB_WPTR_POLL_ADDR_LO 0x00b3 259*81570d6dSHawking Zhang #define regLSDMA_QUEUE0_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 260*81570d6dSHawking Zhang #define regLSDMA_QUEUE0_RB_AQL_CNTL 0x00b4 261*81570d6dSHawking Zhang #define regLSDMA_QUEUE0_RB_AQL_CNTL_BASE_IDX 0 262*81570d6dSHawking Zhang #define regLSDMA_QUEUE0_MINOR_PTR_UPDATE 0x00b5 263*81570d6dSHawking Zhang #define regLSDMA_QUEUE0_MINOR_PTR_UPDATE_BASE_IDX 0 264*81570d6dSHawking Zhang #define regLSDMA_QUEUE0_CNTL 0x00b6 265*81570d6dSHawking Zhang #define regLSDMA_QUEUE0_CNTL_BASE_IDX 0 266*81570d6dSHawking Zhang #define regLSDMA_QUEUE0_DUMMY1 0x00b8 267*81570d6dSHawking Zhang #define regLSDMA_QUEUE0_DUMMY1_BASE_IDX 0 268*81570d6dSHawking Zhang #define regLSDMA_QUEUE0_DUMMY2 0x00b9 269*81570d6dSHawking Zhang #define regLSDMA_QUEUE0_DUMMY2_BASE_IDX 0 270*81570d6dSHawking Zhang #define regLSDMA_QUEUE0_MIDCMD_DATA0 0x00c0 271*81570d6dSHawking Zhang #define regLSDMA_QUEUE0_MIDCMD_DATA0_BASE_IDX 0 272*81570d6dSHawking Zhang #define regLSDMA_QUEUE0_MIDCMD_DATA1 0x00c1 273*81570d6dSHawking Zhang #define regLSDMA_QUEUE0_MIDCMD_DATA1_BASE_IDX 0 274*81570d6dSHawking Zhang #define regLSDMA_QUEUE0_MIDCMD_DATA2 0x00c2 275*81570d6dSHawking Zhang #define regLSDMA_QUEUE0_MIDCMD_DATA2_BASE_IDX 0 276*81570d6dSHawking Zhang #define regLSDMA_QUEUE0_MIDCMD_DATA3 0x00c3 277*81570d6dSHawking Zhang #define regLSDMA_QUEUE0_MIDCMD_DATA3_BASE_IDX 0 278*81570d6dSHawking Zhang #define regLSDMA_QUEUE0_MIDCMD_DATA4 0x00c4 279*81570d6dSHawking Zhang #define regLSDMA_QUEUE0_MIDCMD_DATA4_BASE_IDX 0 280*81570d6dSHawking Zhang #define regLSDMA_QUEUE0_MIDCMD_DATA5 0x00c5 281*81570d6dSHawking Zhang #define regLSDMA_QUEUE0_MIDCMD_DATA5_BASE_IDX 0 282*81570d6dSHawking Zhang #define regLSDMA_QUEUE0_MIDCMD_DATA6 0x00c6 283*81570d6dSHawking Zhang #define regLSDMA_QUEUE0_MIDCMD_DATA6_BASE_IDX 0 284*81570d6dSHawking Zhang #define regLSDMA_QUEUE0_MIDCMD_DATA7 0x00c7 285*81570d6dSHawking Zhang #define regLSDMA_QUEUE0_MIDCMD_DATA7_BASE_IDX 0 286*81570d6dSHawking Zhang #define regLSDMA_QUEUE0_MIDCMD_DATA8 0x00c8 287*81570d6dSHawking Zhang #define regLSDMA_QUEUE0_MIDCMD_DATA8_BASE_IDX 0 288*81570d6dSHawking Zhang #define regLSDMA_QUEUE0_MIDCMD_DATA9 0x00c9 289*81570d6dSHawking Zhang #define regLSDMA_QUEUE0_MIDCMD_DATA9_BASE_IDX 0 290*81570d6dSHawking Zhang #define regLSDMA_QUEUE0_MIDCMD_DATA10 0x00ca 291*81570d6dSHawking Zhang #define regLSDMA_QUEUE0_MIDCMD_DATA10_BASE_IDX 0 292*81570d6dSHawking Zhang #define regLSDMA_QUEUE0_MIDCMD_CNTL 0x00cb 293*81570d6dSHawking Zhang #define regLSDMA_QUEUE0_MIDCMD_CNTL_BASE_IDX 0 294*81570d6dSHawking Zhang #define regLSDMA_QUEUE1_RB_CNTL 0x00d8 295*81570d6dSHawking Zhang #define regLSDMA_QUEUE1_RB_CNTL_BASE_IDX 0 296*81570d6dSHawking Zhang #define regLSDMA_QUEUE1_RB_BASE 0x00d9 297*81570d6dSHawking Zhang #define regLSDMA_QUEUE1_RB_BASE_BASE_IDX 0 298*81570d6dSHawking Zhang #define regLSDMA_QUEUE1_RB_BASE_HI 0x00da 299*81570d6dSHawking Zhang #define regLSDMA_QUEUE1_RB_BASE_HI_BASE_IDX 0 300*81570d6dSHawking Zhang #define regLSDMA_QUEUE1_RB_RPTR 0x00db 301*81570d6dSHawking Zhang #define regLSDMA_QUEUE1_RB_RPTR_BASE_IDX 0 302*81570d6dSHawking Zhang #define regLSDMA_QUEUE1_RB_RPTR_HI 0x00dc 303*81570d6dSHawking Zhang #define regLSDMA_QUEUE1_RB_RPTR_HI_BASE_IDX 0 304*81570d6dSHawking Zhang #define regLSDMA_QUEUE1_RB_WPTR 0x00dd 305*81570d6dSHawking Zhang #define regLSDMA_QUEUE1_RB_WPTR_BASE_IDX 0 306*81570d6dSHawking Zhang #define regLSDMA_QUEUE1_RB_WPTR_HI 0x00de 307*81570d6dSHawking Zhang #define regLSDMA_QUEUE1_RB_WPTR_HI_BASE_IDX 0 308*81570d6dSHawking Zhang #define regLSDMA_QUEUE1_RB_WPTR_POLL_CNTL 0x00df 309*81570d6dSHawking Zhang #define regLSDMA_QUEUE1_RB_WPTR_POLL_CNTL_BASE_IDX 0 310*81570d6dSHawking Zhang #define regLSDMA_QUEUE1_RB_RPTR_ADDR_HI 0x00e0 311*81570d6dSHawking Zhang #define regLSDMA_QUEUE1_RB_RPTR_ADDR_HI_BASE_IDX 0 312*81570d6dSHawking Zhang #define regLSDMA_QUEUE1_RB_RPTR_ADDR_LO 0x00e1 313*81570d6dSHawking Zhang #define regLSDMA_QUEUE1_RB_RPTR_ADDR_LO_BASE_IDX 0 314*81570d6dSHawking Zhang #define regLSDMA_QUEUE1_IB_CNTL 0x00e2 315*81570d6dSHawking Zhang #define regLSDMA_QUEUE1_IB_CNTL_BASE_IDX 0 316*81570d6dSHawking Zhang #define regLSDMA_QUEUE1_IB_RPTR 0x00e3 317*81570d6dSHawking Zhang #define regLSDMA_QUEUE1_IB_RPTR_BASE_IDX 0 318*81570d6dSHawking Zhang #define regLSDMA_QUEUE1_IB_OFFSET 0x00e4 319*81570d6dSHawking Zhang #define regLSDMA_QUEUE1_IB_OFFSET_BASE_IDX 0 320*81570d6dSHawking Zhang #define regLSDMA_QUEUE1_IB_BASE_LO 0x00e5 321*81570d6dSHawking Zhang #define regLSDMA_QUEUE1_IB_BASE_LO_BASE_IDX 0 322*81570d6dSHawking Zhang #define regLSDMA_QUEUE1_IB_BASE_HI 0x00e6 323*81570d6dSHawking Zhang #define regLSDMA_QUEUE1_IB_BASE_HI_BASE_IDX 0 324*81570d6dSHawking Zhang #define regLSDMA_QUEUE1_IB_SIZE 0x00e7 325*81570d6dSHawking Zhang #define regLSDMA_QUEUE1_IB_SIZE_BASE_IDX 0 326*81570d6dSHawking Zhang #define regLSDMA_QUEUE1_SKIP_CNTL 0x00e8 327*81570d6dSHawking Zhang #define regLSDMA_QUEUE1_SKIP_CNTL_BASE_IDX 0 328*81570d6dSHawking Zhang #define regLSDMA_QUEUE1_CONTEXT_STATUS 0x00e9 329*81570d6dSHawking Zhang #define regLSDMA_QUEUE1_CONTEXT_STATUS_BASE_IDX 0 330*81570d6dSHawking Zhang #define regLSDMA_QUEUE1_DOORBELL 0x00ea 331*81570d6dSHawking Zhang #define regLSDMA_QUEUE1_DOORBELL_BASE_IDX 0 332*81570d6dSHawking Zhang #define regLSDMA_QUEUE1_STATUS 0x0100 333*81570d6dSHawking Zhang #define regLSDMA_QUEUE1_STATUS_BASE_IDX 0 334*81570d6dSHawking Zhang #define regLSDMA_QUEUE1_DOORBELL_LOG 0x0101 335*81570d6dSHawking Zhang #define regLSDMA_QUEUE1_DOORBELL_LOG_BASE_IDX 0 336*81570d6dSHawking Zhang #define regLSDMA_QUEUE1_WATERMARK 0x0102 337*81570d6dSHawking Zhang #define regLSDMA_QUEUE1_WATERMARK_BASE_IDX 0 338*81570d6dSHawking Zhang #define regLSDMA_QUEUE1_DOORBELL_OFFSET 0x0103 339*81570d6dSHawking Zhang #define regLSDMA_QUEUE1_DOORBELL_OFFSET_BASE_IDX 0 340*81570d6dSHawking Zhang #define regLSDMA_QUEUE1_CSA_ADDR_LO 0x0104 341*81570d6dSHawking Zhang #define regLSDMA_QUEUE1_CSA_ADDR_LO_BASE_IDX 0 342*81570d6dSHawking Zhang #define regLSDMA_QUEUE1_CSA_ADDR_HI 0x0105 343*81570d6dSHawking Zhang #define regLSDMA_QUEUE1_CSA_ADDR_HI_BASE_IDX 0 344*81570d6dSHawking Zhang #define regLSDMA_QUEUE1_RB_PREEMPT 0x0106 345*81570d6dSHawking Zhang #define regLSDMA_QUEUE1_RB_PREEMPT_BASE_IDX 0 346*81570d6dSHawking Zhang #define regLSDMA_QUEUE1_IB_SUB_REMAIN 0x0107 347*81570d6dSHawking Zhang #define regLSDMA_QUEUE1_IB_SUB_REMAIN_BASE_IDX 0 348*81570d6dSHawking Zhang #define regLSDMA_QUEUE1_PREEMPT 0x0108 349*81570d6dSHawking Zhang #define regLSDMA_QUEUE1_PREEMPT_BASE_IDX 0 350*81570d6dSHawking Zhang #define regLSDMA_QUEUE1_DUMMY0 0x0109 351*81570d6dSHawking Zhang #define regLSDMA_QUEUE1_DUMMY0_BASE_IDX 0 352*81570d6dSHawking Zhang #define regLSDMA_QUEUE1_RB_WPTR_POLL_ADDR_HI 0x010a 353*81570d6dSHawking Zhang #define regLSDMA_QUEUE1_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 354*81570d6dSHawking Zhang #define regLSDMA_QUEUE1_RB_WPTR_POLL_ADDR_LO 0x010b 355*81570d6dSHawking Zhang #define regLSDMA_QUEUE1_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 356*81570d6dSHawking Zhang #define regLSDMA_QUEUE1_RB_AQL_CNTL 0x010c 357*81570d6dSHawking Zhang #define regLSDMA_QUEUE1_RB_AQL_CNTL_BASE_IDX 0 358*81570d6dSHawking Zhang #define regLSDMA_QUEUE1_MINOR_PTR_UPDATE 0x010d 359*81570d6dSHawking Zhang #define regLSDMA_QUEUE1_MINOR_PTR_UPDATE_BASE_IDX 0 360*81570d6dSHawking Zhang #define regLSDMA_QUEUE1_CNTL 0x010e 361*81570d6dSHawking Zhang #define regLSDMA_QUEUE1_CNTL_BASE_IDX 0 362*81570d6dSHawking Zhang #define regLSDMA_QUEUE1_DUMMY1 0x0110 363*81570d6dSHawking Zhang #define regLSDMA_QUEUE1_DUMMY1_BASE_IDX 0 364*81570d6dSHawking Zhang #define regLSDMA_QUEUE1_DUMMY2 0x0111 365*81570d6dSHawking Zhang #define regLSDMA_QUEUE1_DUMMY2_BASE_IDX 0 366*81570d6dSHawking Zhang #define regLSDMA_QUEUE1_MIDCMD_DATA0 0x0118 367*81570d6dSHawking Zhang #define regLSDMA_QUEUE1_MIDCMD_DATA0_BASE_IDX 0 368*81570d6dSHawking Zhang #define regLSDMA_QUEUE1_MIDCMD_DATA1 0x0119 369*81570d6dSHawking Zhang #define regLSDMA_QUEUE1_MIDCMD_DATA1_BASE_IDX 0 370*81570d6dSHawking Zhang #define regLSDMA_QUEUE1_MIDCMD_DATA2 0x011a 371*81570d6dSHawking Zhang #define regLSDMA_QUEUE1_MIDCMD_DATA2_BASE_IDX 0 372*81570d6dSHawking Zhang #define regLSDMA_QUEUE1_MIDCMD_DATA3 0x011b 373*81570d6dSHawking Zhang #define regLSDMA_QUEUE1_MIDCMD_DATA3_BASE_IDX 0 374*81570d6dSHawking Zhang #define regLSDMA_QUEUE1_MIDCMD_DATA4 0x011c 375*81570d6dSHawking Zhang #define regLSDMA_QUEUE1_MIDCMD_DATA4_BASE_IDX 0 376*81570d6dSHawking Zhang #define regLSDMA_QUEUE1_MIDCMD_DATA5 0x011d 377*81570d6dSHawking Zhang #define regLSDMA_QUEUE1_MIDCMD_DATA5_BASE_IDX 0 378*81570d6dSHawking Zhang #define regLSDMA_QUEUE1_MIDCMD_DATA6 0x011e 379*81570d6dSHawking Zhang #define regLSDMA_QUEUE1_MIDCMD_DATA6_BASE_IDX 0 380*81570d6dSHawking Zhang #define regLSDMA_QUEUE1_MIDCMD_DATA7 0x011f 381*81570d6dSHawking Zhang #define regLSDMA_QUEUE1_MIDCMD_DATA7_BASE_IDX 0 382*81570d6dSHawking Zhang #define regLSDMA_QUEUE1_MIDCMD_DATA8 0x0120 383*81570d6dSHawking Zhang #define regLSDMA_QUEUE1_MIDCMD_DATA8_BASE_IDX 0 384*81570d6dSHawking Zhang #define regLSDMA_QUEUE1_MIDCMD_DATA9 0x0121 385*81570d6dSHawking Zhang #define regLSDMA_QUEUE1_MIDCMD_DATA9_BASE_IDX 0 386*81570d6dSHawking Zhang #define regLSDMA_QUEUE1_MIDCMD_DATA10 0x0122 387*81570d6dSHawking Zhang #define regLSDMA_QUEUE1_MIDCMD_DATA10_BASE_IDX 0 388*81570d6dSHawking Zhang #define regLSDMA_QUEUE1_MIDCMD_CNTL 0x0123 389*81570d6dSHawking Zhang #define regLSDMA_QUEUE1_MIDCMD_CNTL_BASE_IDX 0 390*81570d6dSHawking Zhang 391*81570d6dSHawking Zhang #endif 392