1*11c4328aSHawking Zhang /* 2*11c4328aSHawking Zhang * Copyright 2021 Advanced Micro Devices, Inc. 3*11c4328aSHawking Zhang * 4*11c4328aSHawking Zhang * Permission is hereby granted, free of charge, to any person obtaining a 5*11c4328aSHawking Zhang * copy of this software and associated documentation files (the "Software"), 6*11c4328aSHawking Zhang * to deal in the Software without restriction, including without limitation 7*11c4328aSHawking Zhang * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8*11c4328aSHawking Zhang * and/or sell copies of the Software, and to permit persons to whom the 9*11c4328aSHawking Zhang * Software is furnished to do so, subject to the following conditions: 10*11c4328aSHawking Zhang * 11*11c4328aSHawking Zhang * The above copyright notice and this permission notice shall be included in 12*11c4328aSHawking Zhang * all copies or substantial portions of the Software. 13*11c4328aSHawking Zhang * 14*11c4328aSHawking Zhang * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15*11c4328aSHawking Zhang * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16*11c4328aSHawking Zhang * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17*11c4328aSHawking Zhang * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18*11c4328aSHawking Zhang * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19*11c4328aSHawking Zhang * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20*11c4328aSHawking Zhang * OTHER DEALINGS IN THE SOFTWARE. 21*11c4328aSHawking Zhang * 22*11c4328aSHawking Zhang */ 23*11c4328aSHawking Zhang #ifndef _hdp_6_0_0_OFFSET_HEADER 24*11c4328aSHawking Zhang #define _hdp_6_0_0_OFFSET_HEADER 25*11c4328aSHawking Zhang 26*11c4328aSHawking Zhang 27*11c4328aSHawking Zhang 28*11c4328aSHawking Zhang // addressBlock: hdp_hdpdec 29*11c4328aSHawking Zhang // base address: 0x3c80 30*11c4328aSHawking Zhang #define regHDP_NONSURFACE_BASE 0x0040 31*11c4328aSHawking Zhang #define regHDP_NONSURFACE_BASE_BASE_IDX 0 32*11c4328aSHawking Zhang #define regHDP_NONSURFACE_INFO 0x0041 33*11c4328aSHawking Zhang #define regHDP_NONSURFACE_INFO_BASE_IDX 0 34*11c4328aSHawking Zhang #define regHDP_NONSURFACE_BASE_HI 0x0042 35*11c4328aSHawking Zhang #define regHDP_NONSURFACE_BASE_HI_BASE_IDX 0 36*11c4328aSHawking Zhang #define regHDP_SURFACE_WRITE_FLAGS 0x00c4 37*11c4328aSHawking Zhang #define regHDP_SURFACE_WRITE_FLAGS_BASE_IDX 0 38*11c4328aSHawking Zhang #define regHDP_SURFACE_READ_FLAGS 0x00c5 39*11c4328aSHawking Zhang #define regHDP_SURFACE_READ_FLAGS_BASE_IDX 0 40*11c4328aSHawking Zhang #define regHDP_SURFACE_WRITE_FLAGS_CLR 0x00c6 41*11c4328aSHawking Zhang #define regHDP_SURFACE_WRITE_FLAGS_CLR_BASE_IDX 0 42*11c4328aSHawking Zhang #define regHDP_SURFACE_READ_FLAGS_CLR 0x00c7 43*11c4328aSHawking Zhang #define regHDP_SURFACE_READ_FLAGS_CLR_BASE_IDX 0 44*11c4328aSHawking Zhang #define regHDP_NONSURF_FLAGS 0x00c8 45*11c4328aSHawking Zhang #define regHDP_NONSURF_FLAGS_BASE_IDX 0 46*11c4328aSHawking Zhang #define regHDP_NONSURF_FLAGS_CLR 0x00c9 47*11c4328aSHawking Zhang #define regHDP_NONSURF_FLAGS_CLR_BASE_IDX 0 48*11c4328aSHawking Zhang #define regHDP_HOST_PATH_CNTL 0x00cc 49*11c4328aSHawking Zhang #define regHDP_HOST_PATH_CNTL_BASE_IDX 0 50*11c4328aSHawking Zhang #define regHDP_SW_SEMAPHORE 0x00cd 51*11c4328aSHawking Zhang #define regHDP_SW_SEMAPHORE_BASE_IDX 0 52*11c4328aSHawking Zhang #define regHDP_DEBUG0 0x00ce 53*11c4328aSHawking Zhang #define regHDP_DEBUG0_BASE_IDX 0 54*11c4328aSHawking Zhang #define regHDP_LAST_SURFACE_HIT 0x00d0 55*11c4328aSHawking Zhang #define regHDP_LAST_SURFACE_HIT_BASE_IDX 0 56*11c4328aSHawking Zhang #define regHDP_OUTSTANDING_REQ 0x00d2 57*11c4328aSHawking Zhang #define regHDP_OUTSTANDING_REQ_BASE_IDX 0 58*11c4328aSHawking Zhang #define regHDP_MISC_CNTL 0x00d3 59*11c4328aSHawking Zhang #define regHDP_MISC_CNTL_BASE_IDX 0 60*11c4328aSHawking Zhang #define regHDP_MEM_POWER_CTRL 0x00d4 61*11c4328aSHawking Zhang #define regHDP_MEM_POWER_CTRL_BASE_IDX 0 62*11c4328aSHawking Zhang #define regHDP_MMHUB_CNTL 0x00d5 63*11c4328aSHawking Zhang #define regHDP_MMHUB_CNTL_BASE_IDX 0 64*11c4328aSHawking Zhang #define regHDP_VERSION 0x00d7 65*11c4328aSHawking Zhang #define regHDP_VERSION_BASE_IDX 0 66*11c4328aSHawking Zhang #define regHDP_CLK_CNTL 0x00d8 67*11c4328aSHawking Zhang #define regHDP_CLK_CNTL_BASE_IDX 0 68*11c4328aSHawking Zhang #define regHDP_MEMIO_CNTL 0x00f6 69*11c4328aSHawking Zhang #define regHDP_MEMIO_CNTL_BASE_IDX 0 70*11c4328aSHawking Zhang #define regHDP_MEMIO_ADDR 0x00f7 71*11c4328aSHawking Zhang #define regHDP_MEMIO_ADDR_BASE_IDX 0 72*11c4328aSHawking Zhang #define regHDP_MEMIO_STATUS 0x00f8 73*11c4328aSHawking Zhang #define regHDP_MEMIO_STATUS_BASE_IDX 0 74*11c4328aSHawking Zhang #define regHDP_MEMIO_WR_DATA 0x00f9 75*11c4328aSHawking Zhang #define regHDP_MEMIO_WR_DATA_BASE_IDX 0 76*11c4328aSHawking Zhang #define regHDP_MEMIO_RD_DATA 0x00fa 77*11c4328aSHawking Zhang #define regHDP_MEMIO_RD_DATA_BASE_IDX 0 78*11c4328aSHawking Zhang #define regHDP_XDP_DIRECT2HDP_FIRST 0x0100 79*11c4328aSHawking Zhang #define regHDP_XDP_DIRECT2HDP_FIRST_BASE_IDX 0 80*11c4328aSHawking Zhang #define regHDP_XDP_D2H_FLUSH 0x0101 81*11c4328aSHawking Zhang #define regHDP_XDP_D2H_FLUSH_BASE_IDX 0 82*11c4328aSHawking Zhang #define regHDP_XDP_D2H_BAR_UPDATE 0x0102 83*11c4328aSHawking Zhang #define regHDP_XDP_D2H_BAR_UPDATE_BASE_IDX 0 84*11c4328aSHawking Zhang #define regHDP_XDP_D2H_RSVD_3 0x0103 85*11c4328aSHawking Zhang #define regHDP_XDP_D2H_RSVD_3_BASE_IDX 0 86*11c4328aSHawking Zhang #define regHDP_XDP_D2H_RSVD_4 0x0104 87*11c4328aSHawking Zhang #define regHDP_XDP_D2H_RSVD_4_BASE_IDX 0 88*11c4328aSHawking Zhang #define regHDP_XDP_D2H_RSVD_5 0x0105 89*11c4328aSHawking Zhang #define regHDP_XDP_D2H_RSVD_5_BASE_IDX 0 90*11c4328aSHawking Zhang #define regHDP_XDP_D2H_RSVD_6 0x0106 91*11c4328aSHawking Zhang #define regHDP_XDP_D2H_RSVD_6_BASE_IDX 0 92*11c4328aSHawking Zhang #define regHDP_XDP_D2H_RSVD_7 0x0107 93*11c4328aSHawking Zhang #define regHDP_XDP_D2H_RSVD_7_BASE_IDX 0 94*11c4328aSHawking Zhang #define regHDP_XDP_D2H_RSVD_8 0x0108 95*11c4328aSHawking Zhang #define regHDP_XDP_D2H_RSVD_8_BASE_IDX 0 96*11c4328aSHawking Zhang #define regHDP_XDP_D2H_RSVD_9 0x0109 97*11c4328aSHawking Zhang #define regHDP_XDP_D2H_RSVD_9_BASE_IDX 0 98*11c4328aSHawking Zhang #define regHDP_XDP_D2H_RSVD_10 0x010a 99*11c4328aSHawking Zhang #define regHDP_XDP_D2H_RSVD_10_BASE_IDX 0 100*11c4328aSHawking Zhang #define regHDP_XDP_D2H_RSVD_11 0x010b 101*11c4328aSHawking Zhang #define regHDP_XDP_D2H_RSVD_11_BASE_IDX 0 102*11c4328aSHawking Zhang #define regHDP_XDP_D2H_RSVD_12 0x010c 103*11c4328aSHawking Zhang #define regHDP_XDP_D2H_RSVD_12_BASE_IDX 0 104*11c4328aSHawking Zhang #define regHDP_XDP_D2H_RSVD_13 0x010d 105*11c4328aSHawking Zhang #define regHDP_XDP_D2H_RSVD_13_BASE_IDX 0 106*11c4328aSHawking Zhang #define regHDP_XDP_D2H_RSVD_14 0x010e 107*11c4328aSHawking Zhang #define regHDP_XDP_D2H_RSVD_14_BASE_IDX 0 108*11c4328aSHawking Zhang #define regHDP_XDP_D2H_RSVD_15 0x010f 109*11c4328aSHawking Zhang #define regHDP_XDP_D2H_RSVD_15_BASE_IDX 0 110*11c4328aSHawking Zhang #define regHDP_XDP_D2H_RSVD_16 0x0110 111*11c4328aSHawking Zhang #define regHDP_XDP_D2H_RSVD_16_BASE_IDX 0 112*11c4328aSHawking Zhang #define regHDP_XDP_D2H_RSVD_17 0x0111 113*11c4328aSHawking Zhang #define regHDP_XDP_D2H_RSVD_17_BASE_IDX 0 114*11c4328aSHawking Zhang #define regHDP_XDP_D2H_RSVD_18 0x0112 115*11c4328aSHawking Zhang #define regHDP_XDP_D2H_RSVD_18_BASE_IDX 0 116*11c4328aSHawking Zhang #define regHDP_XDP_D2H_RSVD_19 0x0113 117*11c4328aSHawking Zhang #define regHDP_XDP_D2H_RSVD_19_BASE_IDX 0 118*11c4328aSHawking Zhang #define regHDP_XDP_D2H_RSVD_20 0x0114 119*11c4328aSHawking Zhang #define regHDP_XDP_D2H_RSVD_20_BASE_IDX 0 120*11c4328aSHawking Zhang #define regHDP_XDP_D2H_RSVD_21 0x0115 121*11c4328aSHawking Zhang #define regHDP_XDP_D2H_RSVD_21_BASE_IDX 0 122*11c4328aSHawking Zhang #define regHDP_XDP_D2H_RSVD_22 0x0116 123*11c4328aSHawking Zhang #define regHDP_XDP_D2H_RSVD_22_BASE_IDX 0 124*11c4328aSHawking Zhang #define regHDP_XDP_D2H_RSVD_23 0x0117 125*11c4328aSHawking Zhang #define regHDP_XDP_D2H_RSVD_23_BASE_IDX 0 126*11c4328aSHawking Zhang #define regHDP_XDP_D2H_RSVD_24 0x0118 127*11c4328aSHawking Zhang #define regHDP_XDP_D2H_RSVD_24_BASE_IDX 0 128*11c4328aSHawking Zhang #define regHDP_XDP_D2H_RSVD_25 0x0119 129*11c4328aSHawking Zhang #define regHDP_XDP_D2H_RSVD_25_BASE_IDX 0 130*11c4328aSHawking Zhang #define regHDP_XDP_D2H_RSVD_26 0x011a 131*11c4328aSHawking Zhang #define regHDP_XDP_D2H_RSVD_26_BASE_IDX 0 132*11c4328aSHawking Zhang #define regHDP_XDP_D2H_RSVD_27 0x011b 133*11c4328aSHawking Zhang #define regHDP_XDP_D2H_RSVD_27_BASE_IDX 0 134*11c4328aSHawking Zhang #define regHDP_XDP_D2H_RSVD_28 0x011c 135*11c4328aSHawking Zhang #define regHDP_XDP_D2H_RSVD_28_BASE_IDX 0 136*11c4328aSHawking Zhang #define regHDP_XDP_D2H_RSVD_29 0x011d 137*11c4328aSHawking Zhang #define regHDP_XDP_D2H_RSVD_29_BASE_IDX 0 138*11c4328aSHawking Zhang #define regHDP_XDP_D2H_RSVD_30 0x011e 139*11c4328aSHawking Zhang #define regHDP_XDP_D2H_RSVD_30_BASE_IDX 0 140*11c4328aSHawking Zhang #define regHDP_XDP_D2H_RSVD_31 0x011f 141*11c4328aSHawking Zhang #define regHDP_XDP_D2H_RSVD_31_BASE_IDX 0 142*11c4328aSHawking Zhang #define regHDP_XDP_D2H_RSVD_32 0x0120 143*11c4328aSHawking Zhang #define regHDP_XDP_D2H_RSVD_32_BASE_IDX 0 144*11c4328aSHawking Zhang #define regHDP_XDP_D2H_RSVD_33 0x0121 145*11c4328aSHawking Zhang #define regHDP_XDP_D2H_RSVD_33_BASE_IDX 0 146*11c4328aSHawking Zhang #define regHDP_XDP_D2H_RSVD_34 0x0122 147*11c4328aSHawking Zhang #define regHDP_XDP_D2H_RSVD_34_BASE_IDX 0 148*11c4328aSHawking Zhang #define regHDP_XDP_DIRECT2HDP_LAST 0x0123 149*11c4328aSHawking Zhang #define regHDP_XDP_DIRECT2HDP_LAST_BASE_IDX 0 150*11c4328aSHawking Zhang #define regHDP_XDP_P2P_BAR_CFG 0x0124 151*11c4328aSHawking Zhang #define regHDP_XDP_P2P_BAR_CFG_BASE_IDX 0 152*11c4328aSHawking Zhang #define regHDP_XDP_P2P_MBX_OFFSET 0x0125 153*11c4328aSHawking Zhang #define regHDP_XDP_P2P_MBX_OFFSET_BASE_IDX 0 154*11c4328aSHawking Zhang #define regHDP_XDP_P2P_MBX_ADDR0 0x0126 155*11c4328aSHawking Zhang #define regHDP_XDP_P2P_MBX_ADDR0_BASE_IDX 0 156*11c4328aSHawking Zhang #define regHDP_XDP_P2P_MBX_ADDR1 0x0127 157*11c4328aSHawking Zhang #define regHDP_XDP_P2P_MBX_ADDR1_BASE_IDX 0 158*11c4328aSHawking Zhang #define regHDP_XDP_P2P_MBX_ADDR2 0x0128 159*11c4328aSHawking Zhang #define regHDP_XDP_P2P_MBX_ADDR2_BASE_IDX 0 160*11c4328aSHawking Zhang #define regHDP_XDP_P2P_MBX_ADDR3 0x0129 161*11c4328aSHawking Zhang #define regHDP_XDP_P2P_MBX_ADDR3_BASE_IDX 0 162*11c4328aSHawking Zhang #define regHDP_XDP_P2P_MBX_ADDR4 0x012a 163*11c4328aSHawking Zhang #define regHDP_XDP_P2P_MBX_ADDR4_BASE_IDX 0 164*11c4328aSHawking Zhang #define regHDP_XDP_P2P_MBX_ADDR5 0x012b 165*11c4328aSHawking Zhang #define regHDP_XDP_P2P_MBX_ADDR5_BASE_IDX 0 166*11c4328aSHawking Zhang #define regHDP_XDP_P2P_MBX_ADDR6 0x012c 167*11c4328aSHawking Zhang #define regHDP_XDP_P2P_MBX_ADDR6_BASE_IDX 0 168*11c4328aSHawking Zhang #define regHDP_XDP_HDP_MBX_MC_CFG 0x012d 169*11c4328aSHawking Zhang #define regHDP_XDP_HDP_MBX_MC_CFG_BASE_IDX 0 170*11c4328aSHawking Zhang #define regHDP_XDP_HDP_MC_CFG 0x012e 171*11c4328aSHawking Zhang #define regHDP_XDP_HDP_MC_CFG_BASE_IDX 0 172*11c4328aSHawking Zhang #define regHDP_XDP_HST_CFG 0x012f 173*11c4328aSHawking Zhang #define regHDP_XDP_HST_CFG_BASE_IDX 0 174*11c4328aSHawking Zhang #define regHDP_XDP_HDP_IPH_CFG 0x0131 175*11c4328aSHawking Zhang #define regHDP_XDP_HDP_IPH_CFG_BASE_IDX 0 176*11c4328aSHawking Zhang #define regHDP_XDP_P2P_BAR0 0x0134 177*11c4328aSHawking Zhang #define regHDP_XDP_P2P_BAR0_BASE_IDX 0 178*11c4328aSHawking Zhang #define regHDP_XDP_P2P_BAR1 0x0135 179*11c4328aSHawking Zhang #define regHDP_XDP_P2P_BAR1_BASE_IDX 0 180*11c4328aSHawking Zhang #define regHDP_XDP_P2P_BAR2 0x0136 181*11c4328aSHawking Zhang #define regHDP_XDP_P2P_BAR2_BASE_IDX 0 182*11c4328aSHawking Zhang #define regHDP_XDP_P2P_BAR3 0x0137 183*11c4328aSHawking Zhang #define regHDP_XDP_P2P_BAR3_BASE_IDX 0 184*11c4328aSHawking Zhang #define regHDP_XDP_P2P_BAR4 0x0138 185*11c4328aSHawking Zhang #define regHDP_XDP_P2P_BAR4_BASE_IDX 0 186*11c4328aSHawking Zhang #define regHDP_XDP_P2P_BAR5 0x0139 187*11c4328aSHawking Zhang #define regHDP_XDP_P2P_BAR5_BASE_IDX 0 188*11c4328aSHawking Zhang #define regHDP_XDP_P2P_BAR6 0x013a 189*11c4328aSHawking Zhang #define regHDP_XDP_P2P_BAR6_BASE_IDX 0 190*11c4328aSHawking Zhang #define regHDP_XDP_P2P_BAR7 0x013b 191*11c4328aSHawking Zhang #define regHDP_XDP_P2P_BAR7_BASE_IDX 0 192*11c4328aSHawking Zhang #define regHDP_XDP_FLUSH_ARMED_STS 0x013c 193*11c4328aSHawking Zhang #define regHDP_XDP_FLUSH_ARMED_STS_BASE_IDX 0 194*11c4328aSHawking Zhang #define regHDP_XDP_FLUSH_CNTR0_STS 0x013d 195*11c4328aSHawking Zhang #define regHDP_XDP_FLUSH_CNTR0_STS_BASE_IDX 0 196*11c4328aSHawking Zhang #define regHDP_XDP_BUSY_STS 0x013e 197*11c4328aSHawking Zhang #define regHDP_XDP_BUSY_STS_BASE_IDX 0 198*11c4328aSHawking Zhang #define regHDP_XDP_STICKY 0x013f 199*11c4328aSHawking Zhang #define regHDP_XDP_STICKY_BASE_IDX 0 200*11c4328aSHawking Zhang #define regHDP_XDP_CHKN 0x0140 201*11c4328aSHawking Zhang #define regHDP_XDP_CHKN_BASE_IDX 0 202*11c4328aSHawking Zhang #define regHDP_XDP_BARS_ADDR_39_36 0x0144 203*11c4328aSHawking Zhang #define regHDP_XDP_BARS_ADDR_39_36_BASE_IDX 0 204*11c4328aSHawking Zhang #define regHDP_XDP_MC_VM_FB_LOCATION_BASE 0x0145 205*11c4328aSHawking Zhang #define regHDP_XDP_MC_VM_FB_LOCATION_BASE_BASE_IDX 0 206*11c4328aSHawking Zhang #define regHDP_XDP_MMHUB_ERROR 0x014a 207*11c4328aSHawking Zhang #define regHDP_XDP_MMHUB_ERROR_BASE_IDX 0 208*11c4328aSHawking Zhang 209*11c4328aSHawking Zhang #endif 210