1 /*
2  * Copyright 2021 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  */
23 #ifndef _gc_11_0_0_OFFSET_HEADER
24 #define _gc_11_0_0_OFFSET_HEADER
25 
26 
27 
28 // addressBlock: gc_sdma0_sdma0dec
29 // base address: 0x4980
30 #define regSDMA0_DEC_START                                                                              0x0000
31 #define regSDMA0_DEC_START_BASE_IDX                                                                     0
32 #define regSDMA0_F32_MISC_CNTL                                                                          0x000b
33 #define regSDMA0_F32_MISC_CNTL_BASE_IDX                                                                 0
34 #define regSDMA0_GLOBAL_TIMESTAMP_LO                                                                    0x000f
35 #define regSDMA0_GLOBAL_TIMESTAMP_LO_BASE_IDX                                                           0
36 #define regSDMA0_GLOBAL_TIMESTAMP_HI                                                                    0x0010
37 #define regSDMA0_GLOBAL_TIMESTAMP_HI_BASE_IDX                                                           0
38 #define regSDMA0_POWER_CNTL                                                                             0x001a
39 #define regSDMA0_POWER_CNTL_BASE_IDX                                                                    0
40 #define regSDMA0_CNTL                                                                                   0x001c
41 #define regSDMA0_CNTL_BASE_IDX                                                                          0
42 #define regSDMA0_CHICKEN_BITS                                                                           0x001d
43 #define regSDMA0_CHICKEN_BITS_BASE_IDX                                                                  0
44 #define regSDMA0_GB_ADDR_CONFIG                                                                         0x001e
45 #define regSDMA0_GB_ADDR_CONFIG_BASE_IDX                                                                0
46 #define regSDMA0_GB_ADDR_CONFIG_READ                                                                    0x001f
47 #define regSDMA0_GB_ADDR_CONFIG_READ_BASE_IDX                                                           0
48 #define regSDMA0_RB_RPTR_FETCH                                                                          0x0020
49 #define regSDMA0_RB_RPTR_FETCH_BASE_IDX                                                                 0
50 #define regSDMA0_RB_RPTR_FETCH_HI                                                                       0x0021
51 #define regSDMA0_RB_RPTR_FETCH_HI_BASE_IDX                                                              0
52 #define regSDMA0_SEM_WAIT_FAIL_TIMER_CNTL                                                               0x0022
53 #define regSDMA0_SEM_WAIT_FAIL_TIMER_CNTL_BASE_IDX                                                      0
54 #define regSDMA0_IB_OFFSET_FETCH                                                                        0x0023
55 #define regSDMA0_IB_OFFSET_FETCH_BASE_IDX                                                               0
56 #define regSDMA0_PROGRAM                                                                                0x0024
57 #define regSDMA0_PROGRAM_BASE_IDX                                                                       0
58 #define regSDMA0_STATUS_REG                                                                             0x0025
59 #define regSDMA0_STATUS_REG_BASE_IDX                                                                    0
60 #define regSDMA0_STATUS1_REG                                                                            0x0026
61 #define regSDMA0_STATUS1_REG_BASE_IDX                                                                   0
62 #define regSDMA0_CNTL1                                                                                  0x0027
63 #define regSDMA0_CNTL1_BASE_IDX                                                                         0
64 #define regSDMA0_HBM_PAGE_CONFIG                                                                        0x0028
65 #define regSDMA0_HBM_PAGE_CONFIG_BASE_IDX                                                               0
66 #define regSDMA0_UCODE_CHECKSUM                                                                         0x0029
67 #define regSDMA0_UCODE_CHECKSUM_BASE_IDX                                                                0
68 #define regSDMA0_FREEZE                                                                                 0x002b
69 #define regSDMA0_FREEZE_BASE_IDX                                                                        0
70 #define regSDMA0_PROCESS_QUANTUM0                                                                       0x002c
71 #define regSDMA0_PROCESS_QUANTUM0_BASE_IDX                                                              0
72 #define regSDMA0_PROCESS_QUANTUM1                                                                       0x002d
73 #define regSDMA0_PROCESS_QUANTUM1_BASE_IDX                                                              0
74 #define regSDMA0_WATCHDOG_CNTL                                                                          0x002e
75 #define regSDMA0_WATCHDOG_CNTL_BASE_IDX                                                                 0
76 #define regSDMA0_QUEUE_STATUS0                                                                          0x002f
77 #define regSDMA0_QUEUE_STATUS0_BASE_IDX                                                                 0
78 #define regSDMA0_EDC_CONFIG                                                                             0x0032
79 #define regSDMA0_EDC_CONFIG_BASE_IDX                                                                    0
80 #define regSDMA0_BA_THRESHOLD                                                                           0x0033
81 #define regSDMA0_BA_THRESHOLD_BASE_IDX                                                                  0
82 #define regSDMA0_ID                                                                                     0x0034
83 #define regSDMA0_ID_BASE_IDX                                                                            0
84 #define regSDMA0_VERSION                                                                                0x0035
85 #define regSDMA0_VERSION_BASE_IDX                                                                       0
86 #define regSDMA0_EDC_COUNTER                                                                            0x0036
87 #define regSDMA0_EDC_COUNTER_BASE_IDX                                                                   0
88 #define regSDMA0_EDC_COUNTER_CLEAR                                                                      0x0037
89 #define regSDMA0_EDC_COUNTER_CLEAR_BASE_IDX                                                             0
90 #define regSDMA0_STATUS2_REG                                                                            0x0038
91 #define regSDMA0_STATUS2_REG_BASE_IDX                                                                   0
92 #define regSDMA0_ATOMIC_CNTL                                                                            0x0039
93 #define regSDMA0_ATOMIC_CNTL_BASE_IDX                                                                   0
94 #define regSDMA0_ATOMIC_PREOP_LO                                                                        0x003a
95 #define regSDMA0_ATOMIC_PREOP_LO_BASE_IDX                                                               0
96 #define regSDMA0_ATOMIC_PREOP_HI                                                                        0x003b
97 #define regSDMA0_ATOMIC_PREOP_HI_BASE_IDX                                                               0
98 #define regSDMA0_UTCL1_CNTL                                                                             0x003c
99 #define regSDMA0_UTCL1_CNTL_BASE_IDX                                                                    0
100 #define regSDMA0_UTCL1_WATERMK                                                                          0x003d
101 #define regSDMA0_UTCL1_WATERMK_BASE_IDX                                                                 0
102 #define regSDMA0_UTCL1_TIMEOUT                                                                          0x003e
103 #define regSDMA0_UTCL1_TIMEOUT_BASE_IDX                                                                 0
104 #define regSDMA0_UTCL1_PAGE                                                                             0x003f
105 #define regSDMA0_UTCL1_PAGE_BASE_IDX                                                                    0
106 #define regSDMA0_UTCL1_RD_STATUS                                                                        0x0040
107 #define regSDMA0_UTCL1_RD_STATUS_BASE_IDX                                                               0
108 #define regSDMA0_UTCL1_WR_STATUS                                                                        0x0041
109 #define regSDMA0_UTCL1_WR_STATUS_BASE_IDX                                                               0
110 #define regSDMA0_UTCL1_INV0                                                                             0x0042
111 #define regSDMA0_UTCL1_INV0_BASE_IDX                                                                    0
112 #define regSDMA0_UTCL1_INV1                                                                             0x0043
113 #define regSDMA0_UTCL1_INV1_BASE_IDX                                                                    0
114 #define regSDMA0_UTCL1_INV2                                                                             0x0044
115 #define regSDMA0_UTCL1_INV2_BASE_IDX                                                                    0
116 #define regSDMA0_UTCL1_RD_XNACK0                                                                        0x0045
117 #define regSDMA0_UTCL1_RD_XNACK0_BASE_IDX                                                               0
118 #define regSDMA0_UTCL1_RD_XNACK1                                                                        0x0046
119 #define regSDMA0_UTCL1_RD_XNACK1_BASE_IDX                                                               0
120 #define regSDMA0_UTCL1_WR_XNACK0                                                                        0x0047
121 #define regSDMA0_UTCL1_WR_XNACK0_BASE_IDX                                                               0
122 #define regSDMA0_UTCL1_WR_XNACK1                                                                        0x0048
123 #define regSDMA0_UTCL1_WR_XNACK1_BASE_IDX                                                               0
124 #define regSDMA0_RELAX_ORDERING_LUT                                                                     0x004a
125 #define regSDMA0_RELAX_ORDERING_LUT_BASE_IDX                                                            0
126 #define regSDMA0_CHICKEN_BITS_2                                                                         0x004b
127 #define regSDMA0_CHICKEN_BITS_2_BASE_IDX                                                                0
128 #define regSDMA0_STATUS3_REG                                                                            0x004c
129 #define regSDMA0_STATUS3_REG_BASE_IDX                                                                   0
130 #define regSDMA0_PHYSICAL_ADDR_LO                                                                       0x004d
131 #define regSDMA0_PHYSICAL_ADDR_LO_BASE_IDX                                                              0
132 #define regSDMA0_PHYSICAL_ADDR_HI                                                                       0x004e
133 #define regSDMA0_PHYSICAL_ADDR_HI_BASE_IDX                                                              0
134 #define regSDMA0_GLOBAL_QUANTUM                                                                         0x004f
135 #define regSDMA0_GLOBAL_QUANTUM_BASE_IDX                                                                0
136 #define regSDMA0_ERROR_LOG                                                                              0x0050
137 #define regSDMA0_ERROR_LOG_BASE_IDX                                                                     0
138 #define regSDMA0_PUB_DUMMY_REG0                                                                         0x0051
139 #define regSDMA0_PUB_DUMMY_REG0_BASE_IDX                                                                0
140 #define regSDMA0_PUB_DUMMY_REG1                                                                         0x0052
141 #define regSDMA0_PUB_DUMMY_REG1_BASE_IDX                                                                0
142 #define regSDMA0_PUB_DUMMY_REG2                                                                         0x0053
143 #define regSDMA0_PUB_DUMMY_REG2_BASE_IDX                                                                0
144 #define regSDMA0_PUB_DUMMY_REG3                                                                         0x0054
145 #define regSDMA0_PUB_DUMMY_REG3_BASE_IDX                                                                0
146 #define regSDMA0_F32_COUNTER                                                                            0x0055
147 #define regSDMA0_F32_COUNTER_BASE_IDX                                                                   0
148 #define regSDMA0_CRD_CNTL                                                                               0x005b
149 #define regSDMA0_CRD_CNTL_BASE_IDX                                                                      0
150 #define regSDMA0_RLC_CGCG_CTRL                                                                          0x005c
151 #define regSDMA0_RLC_CGCG_CTRL_BASE_IDX                                                                 0
152 #define regSDMA0_AQL_STATUS                                                                             0x005f
153 #define regSDMA0_AQL_STATUS_BASE_IDX                                                                    0
154 #define regSDMA0_EA_DBIT_ADDR_DATA                                                                      0x0060
155 #define regSDMA0_EA_DBIT_ADDR_DATA_BASE_IDX                                                             0
156 #define regSDMA0_EA_DBIT_ADDR_INDEX                                                                     0x0061
157 #define regSDMA0_EA_DBIT_ADDR_INDEX_BASE_IDX                                                            0
158 #define regSDMA0_TLBI_GCR_CNTL                                                                          0x0062
159 #define regSDMA0_TLBI_GCR_CNTL_BASE_IDX                                                                 0
160 #define regSDMA0_TILING_CONFIG                                                                          0x0063
161 #define regSDMA0_TILING_CONFIG_BASE_IDX                                                                 0
162 #define regSDMA0_INT_STATUS                                                                             0x0070
163 #define regSDMA0_INT_STATUS_BASE_IDX                                                                    0
164 #define regSDMA0_HOLE_ADDR_LO                                                                           0x0072
165 #define regSDMA0_HOLE_ADDR_LO_BASE_IDX                                                                  0
166 #define regSDMA0_HOLE_ADDR_HI                                                                           0x0073
167 #define regSDMA0_HOLE_ADDR_HI_BASE_IDX                                                                  0
168 #define regSDMA0_CLOCK_GATING_STATUS                                                                    0x0075
169 #define regSDMA0_CLOCK_GATING_STATUS_BASE_IDX                                                           0
170 #define regSDMA0_STATUS4_REG                                                                            0x0076
171 #define regSDMA0_STATUS4_REG_BASE_IDX                                                                   0
172 #define regSDMA0_SCRATCH_RAM_DATA                                                                       0x0077
173 #define regSDMA0_SCRATCH_RAM_DATA_BASE_IDX                                                              0
174 #define regSDMA0_SCRATCH_RAM_ADDR                                                                       0x0078
175 #define regSDMA0_SCRATCH_RAM_ADDR_BASE_IDX                                                              0
176 #define regSDMA0_TIMESTAMP_CNTL                                                                         0x0079
177 #define regSDMA0_TIMESTAMP_CNTL_BASE_IDX                                                                0
178 #define regSDMA0_STATUS5_REG                                                                            0x007a
179 #define regSDMA0_STATUS5_REG_BASE_IDX                                                                   0
180 #define regSDMA0_QUEUE_RESET_REQ                                                                        0x007b
181 #define regSDMA0_QUEUE_RESET_REQ_BASE_IDX                                                               0
182 #define regSDMA0_STATUS6_REG                                                                            0x007c
183 #define regSDMA0_STATUS6_REG_BASE_IDX                                                                   0
184 #define regSDMA0_UCODE1_CHECKSUM                                                                        0x007d
185 #define regSDMA0_UCODE1_CHECKSUM_BASE_IDX                                                               0
186 #define regSDMA0_CE_CTRL                                                                                0x007e
187 #define regSDMA0_CE_CTRL_BASE_IDX                                                                       0
188 #define regSDMA0_FED_STATUS                                                                             0x007f
189 #define regSDMA0_FED_STATUS_BASE_IDX                                                                    0
190 #define regSDMA0_QUEUE0_RB_CNTL                                                                         0x0080
191 #define regSDMA0_QUEUE0_RB_CNTL_BASE_IDX                                                                0
192 #define regSDMA0_QUEUE0_RB_BASE                                                                         0x0081
193 #define regSDMA0_QUEUE0_RB_BASE_BASE_IDX                                                                0
194 #define regSDMA0_QUEUE0_RB_BASE_HI                                                                      0x0082
195 #define regSDMA0_QUEUE0_RB_BASE_HI_BASE_IDX                                                             0
196 #define regSDMA0_QUEUE0_RB_RPTR                                                                         0x0083
197 #define regSDMA0_QUEUE0_RB_RPTR_BASE_IDX                                                                0
198 #define regSDMA0_QUEUE0_RB_RPTR_HI                                                                      0x0084
199 #define regSDMA0_QUEUE0_RB_RPTR_HI_BASE_IDX                                                             0
200 #define regSDMA0_QUEUE0_RB_WPTR                                                                         0x0085
201 #define regSDMA0_QUEUE0_RB_WPTR_BASE_IDX                                                                0
202 #define regSDMA0_QUEUE0_RB_WPTR_HI                                                                      0x0086
203 #define regSDMA0_QUEUE0_RB_WPTR_HI_BASE_IDX                                                             0
204 #define regSDMA0_QUEUE0_RB_RPTR_ADDR_HI                                                                 0x0088
205 #define regSDMA0_QUEUE0_RB_RPTR_ADDR_HI_BASE_IDX                                                        0
206 #define regSDMA0_QUEUE0_RB_RPTR_ADDR_LO                                                                 0x0089
207 #define regSDMA0_QUEUE0_RB_RPTR_ADDR_LO_BASE_IDX                                                        0
208 #define regSDMA0_QUEUE0_IB_CNTL                                                                         0x008a
209 #define regSDMA0_QUEUE0_IB_CNTL_BASE_IDX                                                                0
210 #define regSDMA0_QUEUE0_IB_RPTR                                                                         0x008b
211 #define regSDMA0_QUEUE0_IB_RPTR_BASE_IDX                                                                0
212 #define regSDMA0_QUEUE0_IB_OFFSET                                                                       0x008c
213 #define regSDMA0_QUEUE0_IB_OFFSET_BASE_IDX                                                              0
214 #define regSDMA0_QUEUE0_IB_BASE_LO                                                                      0x008d
215 #define regSDMA0_QUEUE0_IB_BASE_LO_BASE_IDX                                                             0
216 #define regSDMA0_QUEUE0_IB_BASE_HI                                                                      0x008e
217 #define regSDMA0_QUEUE0_IB_BASE_HI_BASE_IDX                                                             0
218 #define regSDMA0_QUEUE0_IB_SIZE                                                                         0x008f
219 #define regSDMA0_QUEUE0_IB_SIZE_BASE_IDX                                                                0
220 #define regSDMA0_QUEUE0_SKIP_CNTL                                                                       0x0090
221 #define regSDMA0_QUEUE0_SKIP_CNTL_BASE_IDX                                                              0
222 #define regSDMA0_QUEUE0_CONTEXT_STATUS                                                                  0x0091
223 #define regSDMA0_QUEUE0_CONTEXT_STATUS_BASE_IDX                                                         0
224 #define regSDMA0_QUEUE0_DOORBELL                                                                        0x0092
225 #define regSDMA0_QUEUE0_DOORBELL_BASE_IDX                                                               0
226 #define regSDMA0_QUEUE0_DOORBELL_LOG                                                                    0x00a9
227 #define regSDMA0_QUEUE0_DOORBELL_LOG_BASE_IDX                                                           0
228 #define regSDMA0_QUEUE0_DOORBELL_OFFSET                                                                 0x00ab
229 #define regSDMA0_QUEUE0_DOORBELL_OFFSET_BASE_IDX                                                        0
230 #define regSDMA0_QUEUE0_CSA_ADDR_LO                                                                     0x00ac
231 #define regSDMA0_QUEUE0_CSA_ADDR_LO_BASE_IDX                                                            0
232 #define regSDMA0_QUEUE0_CSA_ADDR_HI                                                                     0x00ad
233 #define regSDMA0_QUEUE0_CSA_ADDR_HI_BASE_IDX                                                            0
234 #define regSDMA0_QUEUE0_SCHEDULE_CNTL                                                                   0x00ae
235 #define regSDMA0_QUEUE0_SCHEDULE_CNTL_BASE_IDX                                                          0
236 #define regSDMA0_QUEUE0_IB_SUB_REMAIN                                                                   0x00af
237 #define regSDMA0_QUEUE0_IB_SUB_REMAIN_BASE_IDX                                                          0
238 #define regSDMA0_QUEUE0_PREEMPT                                                                         0x00b0
239 #define regSDMA0_QUEUE0_PREEMPT_BASE_IDX                                                                0
240 #define regSDMA0_QUEUE0_DUMMY_REG                                                                       0x00b1
241 #define regSDMA0_QUEUE0_DUMMY_REG_BASE_IDX                                                              0
242 #define regSDMA0_QUEUE0_RB_WPTR_POLL_ADDR_HI                                                            0x00b2
243 #define regSDMA0_QUEUE0_RB_WPTR_POLL_ADDR_HI_BASE_IDX                                                   0
244 #define regSDMA0_QUEUE0_RB_WPTR_POLL_ADDR_LO                                                            0x00b3
245 #define regSDMA0_QUEUE0_RB_WPTR_POLL_ADDR_LO_BASE_IDX                                                   0
246 #define regSDMA0_QUEUE0_RB_AQL_CNTL                                                                     0x00b4
247 #define regSDMA0_QUEUE0_RB_AQL_CNTL_BASE_IDX                                                            0
248 #define regSDMA0_QUEUE0_MINOR_PTR_UPDATE                                                                0x00b5
249 #define regSDMA0_QUEUE0_MINOR_PTR_UPDATE_BASE_IDX                                                       0
250 #define regSDMA0_QUEUE0_RB_PREEMPT                                                                      0x00b6
251 #define regSDMA0_QUEUE0_RB_PREEMPT_BASE_IDX                                                             0
252 #define regSDMA0_QUEUE0_MIDCMD_DATA0                                                                    0x00c0
253 #define regSDMA0_QUEUE0_MIDCMD_DATA0_BASE_IDX                                                           0
254 #define regSDMA0_QUEUE0_MIDCMD_DATA1                                                                    0x00c1
255 #define regSDMA0_QUEUE0_MIDCMD_DATA1_BASE_IDX                                                           0
256 #define regSDMA0_QUEUE0_MIDCMD_DATA2                                                                    0x00c2
257 #define regSDMA0_QUEUE0_MIDCMD_DATA2_BASE_IDX                                                           0
258 #define regSDMA0_QUEUE0_MIDCMD_DATA3                                                                    0x00c3
259 #define regSDMA0_QUEUE0_MIDCMD_DATA3_BASE_IDX                                                           0
260 #define regSDMA0_QUEUE0_MIDCMD_DATA4                                                                    0x00c4
261 #define regSDMA0_QUEUE0_MIDCMD_DATA4_BASE_IDX                                                           0
262 #define regSDMA0_QUEUE0_MIDCMD_DATA5                                                                    0x00c5
263 #define regSDMA0_QUEUE0_MIDCMD_DATA5_BASE_IDX                                                           0
264 #define regSDMA0_QUEUE0_MIDCMD_DATA6                                                                    0x00c6
265 #define regSDMA0_QUEUE0_MIDCMD_DATA6_BASE_IDX                                                           0
266 #define regSDMA0_QUEUE0_MIDCMD_DATA7                                                                    0x00c7
267 #define regSDMA0_QUEUE0_MIDCMD_DATA7_BASE_IDX                                                           0
268 #define regSDMA0_QUEUE0_MIDCMD_DATA8                                                                    0x00c8
269 #define regSDMA0_QUEUE0_MIDCMD_DATA8_BASE_IDX                                                           0
270 #define regSDMA0_QUEUE0_MIDCMD_DATA9                                                                    0x00c9
271 #define regSDMA0_QUEUE0_MIDCMD_DATA9_BASE_IDX                                                           0
272 #define regSDMA0_QUEUE0_MIDCMD_DATA10                                                                   0x00ca
273 #define regSDMA0_QUEUE0_MIDCMD_DATA10_BASE_IDX                                                          0
274 #define regSDMA0_QUEUE0_MIDCMD_CNTL                                                                     0x00cb
275 #define regSDMA0_QUEUE0_MIDCMD_CNTL_BASE_IDX                                                            0
276 #define regSDMA0_QUEUE1_RB_CNTL                                                                         0x00d8
277 #define regSDMA0_QUEUE1_RB_CNTL_BASE_IDX                                                                0
278 #define regSDMA0_QUEUE1_RB_BASE                                                                         0x00d9
279 #define regSDMA0_QUEUE1_RB_BASE_BASE_IDX                                                                0
280 #define regSDMA0_QUEUE1_RB_BASE_HI                                                                      0x00da
281 #define regSDMA0_QUEUE1_RB_BASE_HI_BASE_IDX                                                             0
282 #define regSDMA0_QUEUE1_RB_RPTR                                                                         0x00db
283 #define regSDMA0_QUEUE1_RB_RPTR_BASE_IDX                                                                0
284 #define regSDMA0_QUEUE1_RB_RPTR_HI                                                                      0x00dc
285 #define regSDMA0_QUEUE1_RB_RPTR_HI_BASE_IDX                                                             0
286 #define regSDMA0_QUEUE1_RB_WPTR                                                                         0x00dd
287 #define regSDMA0_QUEUE1_RB_WPTR_BASE_IDX                                                                0
288 #define regSDMA0_QUEUE1_RB_WPTR_HI                                                                      0x00de
289 #define regSDMA0_QUEUE1_RB_WPTR_HI_BASE_IDX                                                             0
290 #define regSDMA0_QUEUE1_RB_RPTR_ADDR_HI                                                                 0x00e0
291 #define regSDMA0_QUEUE1_RB_RPTR_ADDR_HI_BASE_IDX                                                        0
292 #define regSDMA0_QUEUE1_RB_RPTR_ADDR_LO                                                                 0x00e1
293 #define regSDMA0_QUEUE1_RB_RPTR_ADDR_LO_BASE_IDX                                                        0
294 #define regSDMA0_QUEUE1_IB_CNTL                                                                         0x00e2
295 #define regSDMA0_QUEUE1_IB_CNTL_BASE_IDX                                                                0
296 #define regSDMA0_QUEUE1_IB_RPTR                                                                         0x00e3
297 #define regSDMA0_QUEUE1_IB_RPTR_BASE_IDX                                                                0
298 #define regSDMA0_QUEUE1_IB_OFFSET                                                                       0x00e4
299 #define regSDMA0_QUEUE1_IB_OFFSET_BASE_IDX                                                              0
300 #define regSDMA0_QUEUE1_IB_BASE_LO                                                                      0x00e5
301 #define regSDMA0_QUEUE1_IB_BASE_LO_BASE_IDX                                                             0
302 #define regSDMA0_QUEUE1_IB_BASE_HI                                                                      0x00e6
303 #define regSDMA0_QUEUE1_IB_BASE_HI_BASE_IDX                                                             0
304 #define regSDMA0_QUEUE1_IB_SIZE                                                                         0x00e7
305 #define regSDMA0_QUEUE1_IB_SIZE_BASE_IDX                                                                0
306 #define regSDMA0_QUEUE1_SKIP_CNTL                                                                       0x00e8
307 #define regSDMA0_QUEUE1_SKIP_CNTL_BASE_IDX                                                              0
308 #define regSDMA0_QUEUE1_CONTEXT_STATUS                                                                  0x00e9
309 #define regSDMA0_QUEUE1_CONTEXT_STATUS_BASE_IDX                                                         0
310 #define regSDMA0_QUEUE1_DOORBELL                                                                        0x00ea
311 #define regSDMA0_QUEUE1_DOORBELL_BASE_IDX                                                               0
312 #define regSDMA0_QUEUE1_DOORBELL_LOG                                                                    0x0101
313 #define regSDMA0_QUEUE1_DOORBELL_LOG_BASE_IDX                                                           0
314 #define regSDMA0_QUEUE1_DOORBELL_OFFSET                                                                 0x0103
315 #define regSDMA0_QUEUE1_DOORBELL_OFFSET_BASE_IDX                                                        0
316 #define regSDMA0_QUEUE1_CSA_ADDR_LO                                                                     0x0104
317 #define regSDMA0_QUEUE1_CSA_ADDR_LO_BASE_IDX                                                            0
318 #define regSDMA0_QUEUE1_CSA_ADDR_HI                                                                     0x0105
319 #define regSDMA0_QUEUE1_CSA_ADDR_HI_BASE_IDX                                                            0
320 #define regSDMA0_QUEUE1_SCHEDULE_CNTL                                                                   0x0106
321 #define regSDMA0_QUEUE1_SCHEDULE_CNTL_BASE_IDX                                                          0
322 #define regSDMA0_QUEUE1_IB_SUB_REMAIN                                                                   0x0107
323 #define regSDMA0_QUEUE1_IB_SUB_REMAIN_BASE_IDX                                                          0
324 #define regSDMA0_QUEUE1_PREEMPT                                                                         0x0108
325 #define regSDMA0_QUEUE1_PREEMPT_BASE_IDX                                                                0
326 #define regSDMA0_QUEUE1_DUMMY_REG                                                                       0x0109
327 #define regSDMA0_QUEUE1_DUMMY_REG_BASE_IDX                                                              0
328 #define regSDMA0_QUEUE1_RB_WPTR_POLL_ADDR_HI                                                            0x010a
329 #define regSDMA0_QUEUE1_RB_WPTR_POLL_ADDR_HI_BASE_IDX                                                   0
330 #define regSDMA0_QUEUE1_RB_WPTR_POLL_ADDR_LO                                                            0x010b
331 #define regSDMA0_QUEUE1_RB_WPTR_POLL_ADDR_LO_BASE_IDX                                                   0
332 #define regSDMA0_QUEUE1_RB_AQL_CNTL                                                                     0x010c
333 #define regSDMA0_QUEUE1_RB_AQL_CNTL_BASE_IDX                                                            0
334 #define regSDMA0_QUEUE1_MINOR_PTR_UPDATE                                                                0x010d
335 #define regSDMA0_QUEUE1_MINOR_PTR_UPDATE_BASE_IDX                                                       0
336 #define regSDMA0_QUEUE1_RB_PREEMPT                                                                      0x010e
337 #define regSDMA0_QUEUE1_RB_PREEMPT_BASE_IDX                                                             0
338 #define regSDMA0_QUEUE1_MIDCMD_DATA0                                                                    0x0118
339 #define regSDMA0_QUEUE1_MIDCMD_DATA0_BASE_IDX                                                           0
340 #define regSDMA0_QUEUE1_MIDCMD_DATA1                                                                    0x0119
341 #define regSDMA0_QUEUE1_MIDCMD_DATA1_BASE_IDX                                                           0
342 #define regSDMA0_QUEUE1_MIDCMD_DATA2                                                                    0x011a
343 #define regSDMA0_QUEUE1_MIDCMD_DATA2_BASE_IDX                                                           0
344 #define regSDMA0_QUEUE1_MIDCMD_DATA3                                                                    0x011b
345 #define regSDMA0_QUEUE1_MIDCMD_DATA3_BASE_IDX                                                           0
346 #define regSDMA0_QUEUE1_MIDCMD_DATA4                                                                    0x011c
347 #define regSDMA0_QUEUE1_MIDCMD_DATA4_BASE_IDX                                                           0
348 #define regSDMA0_QUEUE1_MIDCMD_DATA5                                                                    0x011d
349 #define regSDMA0_QUEUE1_MIDCMD_DATA5_BASE_IDX                                                           0
350 #define regSDMA0_QUEUE1_MIDCMD_DATA6                                                                    0x011e
351 #define regSDMA0_QUEUE1_MIDCMD_DATA6_BASE_IDX                                                           0
352 #define regSDMA0_QUEUE1_MIDCMD_DATA7                                                                    0x011f
353 #define regSDMA0_QUEUE1_MIDCMD_DATA7_BASE_IDX                                                           0
354 #define regSDMA0_QUEUE1_MIDCMD_DATA8                                                                    0x0120
355 #define regSDMA0_QUEUE1_MIDCMD_DATA8_BASE_IDX                                                           0
356 #define regSDMA0_QUEUE1_MIDCMD_DATA9                                                                    0x0121
357 #define regSDMA0_QUEUE1_MIDCMD_DATA9_BASE_IDX                                                           0
358 #define regSDMA0_QUEUE1_MIDCMD_DATA10                                                                   0x0122
359 #define regSDMA0_QUEUE1_MIDCMD_DATA10_BASE_IDX                                                          0
360 #define regSDMA0_QUEUE1_MIDCMD_CNTL                                                                     0x0123
361 #define regSDMA0_QUEUE1_MIDCMD_CNTL_BASE_IDX                                                            0
362 #define regSDMA0_QUEUE2_RB_CNTL                                                                         0x0130
363 #define regSDMA0_QUEUE2_RB_CNTL_BASE_IDX                                                                0
364 #define regSDMA0_QUEUE2_RB_BASE                                                                         0x0131
365 #define regSDMA0_QUEUE2_RB_BASE_BASE_IDX                                                                0
366 #define regSDMA0_QUEUE2_RB_BASE_HI                                                                      0x0132
367 #define regSDMA0_QUEUE2_RB_BASE_HI_BASE_IDX                                                             0
368 #define regSDMA0_QUEUE2_RB_RPTR                                                                         0x0133
369 #define regSDMA0_QUEUE2_RB_RPTR_BASE_IDX                                                                0
370 #define regSDMA0_QUEUE2_RB_RPTR_HI                                                                      0x0134
371 #define regSDMA0_QUEUE2_RB_RPTR_HI_BASE_IDX                                                             0
372 #define regSDMA0_QUEUE2_RB_WPTR                                                                         0x0135
373 #define regSDMA0_QUEUE2_RB_WPTR_BASE_IDX                                                                0
374 #define regSDMA0_QUEUE2_RB_WPTR_HI                                                                      0x0136
375 #define regSDMA0_QUEUE2_RB_WPTR_HI_BASE_IDX                                                             0
376 #define regSDMA0_QUEUE2_RB_RPTR_ADDR_HI                                                                 0x0138
377 #define regSDMA0_QUEUE2_RB_RPTR_ADDR_HI_BASE_IDX                                                        0
378 #define regSDMA0_QUEUE2_RB_RPTR_ADDR_LO                                                                 0x0139
379 #define regSDMA0_QUEUE2_RB_RPTR_ADDR_LO_BASE_IDX                                                        0
380 #define regSDMA0_QUEUE2_IB_CNTL                                                                         0x013a
381 #define regSDMA0_QUEUE2_IB_CNTL_BASE_IDX                                                                0
382 #define regSDMA0_QUEUE2_IB_RPTR                                                                         0x013b
383 #define regSDMA0_QUEUE2_IB_RPTR_BASE_IDX                                                                0
384 #define regSDMA0_QUEUE2_IB_OFFSET                                                                       0x013c
385 #define regSDMA0_QUEUE2_IB_OFFSET_BASE_IDX                                                              0
386 #define regSDMA0_QUEUE2_IB_BASE_LO                                                                      0x013d
387 #define regSDMA0_QUEUE2_IB_BASE_LO_BASE_IDX                                                             0
388 #define regSDMA0_QUEUE2_IB_BASE_HI                                                                      0x013e
389 #define regSDMA0_QUEUE2_IB_BASE_HI_BASE_IDX                                                             0
390 #define regSDMA0_QUEUE2_IB_SIZE                                                                         0x013f
391 #define regSDMA0_QUEUE2_IB_SIZE_BASE_IDX                                                                0
392 #define regSDMA0_QUEUE2_SKIP_CNTL                                                                       0x0140
393 #define regSDMA0_QUEUE2_SKIP_CNTL_BASE_IDX                                                              0
394 #define regSDMA0_QUEUE2_CONTEXT_STATUS                                                                  0x0141
395 #define regSDMA0_QUEUE2_CONTEXT_STATUS_BASE_IDX                                                         0
396 #define regSDMA0_QUEUE2_DOORBELL                                                                        0x0142
397 #define regSDMA0_QUEUE2_DOORBELL_BASE_IDX                                                               0
398 #define regSDMA0_QUEUE2_DOORBELL_LOG                                                                    0x0159
399 #define regSDMA0_QUEUE2_DOORBELL_LOG_BASE_IDX                                                           0
400 #define regSDMA0_QUEUE2_DOORBELL_OFFSET                                                                 0x015b
401 #define regSDMA0_QUEUE2_DOORBELL_OFFSET_BASE_IDX                                                        0
402 #define regSDMA0_QUEUE2_CSA_ADDR_LO                                                                     0x015c
403 #define regSDMA0_QUEUE2_CSA_ADDR_LO_BASE_IDX                                                            0
404 #define regSDMA0_QUEUE2_CSA_ADDR_HI                                                                     0x015d
405 #define regSDMA0_QUEUE2_CSA_ADDR_HI_BASE_IDX                                                            0
406 #define regSDMA0_QUEUE2_SCHEDULE_CNTL                                                                   0x015e
407 #define regSDMA0_QUEUE2_SCHEDULE_CNTL_BASE_IDX                                                          0
408 #define regSDMA0_QUEUE2_IB_SUB_REMAIN                                                                   0x015f
409 #define regSDMA0_QUEUE2_IB_SUB_REMAIN_BASE_IDX                                                          0
410 #define regSDMA0_QUEUE2_PREEMPT                                                                         0x0160
411 #define regSDMA0_QUEUE2_PREEMPT_BASE_IDX                                                                0
412 #define regSDMA0_QUEUE2_DUMMY_REG                                                                       0x0161
413 #define regSDMA0_QUEUE2_DUMMY_REG_BASE_IDX                                                              0
414 #define regSDMA0_QUEUE2_RB_WPTR_POLL_ADDR_HI                                                            0x0162
415 #define regSDMA0_QUEUE2_RB_WPTR_POLL_ADDR_HI_BASE_IDX                                                   0
416 #define regSDMA0_QUEUE2_RB_WPTR_POLL_ADDR_LO                                                            0x0163
417 #define regSDMA0_QUEUE2_RB_WPTR_POLL_ADDR_LO_BASE_IDX                                                   0
418 #define regSDMA0_QUEUE2_RB_AQL_CNTL                                                                     0x0164
419 #define regSDMA0_QUEUE2_RB_AQL_CNTL_BASE_IDX                                                            0
420 #define regSDMA0_QUEUE2_MINOR_PTR_UPDATE                                                                0x0165
421 #define regSDMA0_QUEUE2_MINOR_PTR_UPDATE_BASE_IDX                                                       0
422 #define regSDMA0_QUEUE2_RB_PREEMPT                                                                      0x0166
423 #define regSDMA0_QUEUE2_RB_PREEMPT_BASE_IDX                                                             0
424 #define regSDMA0_QUEUE2_MIDCMD_DATA0                                                                    0x0170
425 #define regSDMA0_QUEUE2_MIDCMD_DATA0_BASE_IDX                                                           0
426 #define regSDMA0_QUEUE2_MIDCMD_DATA1                                                                    0x0171
427 #define regSDMA0_QUEUE2_MIDCMD_DATA1_BASE_IDX                                                           0
428 #define regSDMA0_QUEUE2_MIDCMD_DATA2                                                                    0x0172
429 #define regSDMA0_QUEUE2_MIDCMD_DATA2_BASE_IDX                                                           0
430 #define regSDMA0_QUEUE2_MIDCMD_DATA3                                                                    0x0173
431 #define regSDMA0_QUEUE2_MIDCMD_DATA3_BASE_IDX                                                           0
432 #define regSDMA0_QUEUE2_MIDCMD_DATA4                                                                    0x0174
433 #define regSDMA0_QUEUE2_MIDCMD_DATA4_BASE_IDX                                                           0
434 #define regSDMA0_QUEUE2_MIDCMD_DATA5                                                                    0x0175
435 #define regSDMA0_QUEUE2_MIDCMD_DATA5_BASE_IDX                                                           0
436 #define regSDMA0_QUEUE2_MIDCMD_DATA6                                                                    0x0176
437 #define regSDMA0_QUEUE2_MIDCMD_DATA6_BASE_IDX                                                           0
438 #define regSDMA0_QUEUE2_MIDCMD_DATA7                                                                    0x0177
439 #define regSDMA0_QUEUE2_MIDCMD_DATA7_BASE_IDX                                                           0
440 #define regSDMA0_QUEUE2_MIDCMD_DATA8                                                                    0x0178
441 #define regSDMA0_QUEUE2_MIDCMD_DATA8_BASE_IDX                                                           0
442 #define regSDMA0_QUEUE2_MIDCMD_DATA9                                                                    0x0179
443 #define regSDMA0_QUEUE2_MIDCMD_DATA9_BASE_IDX                                                           0
444 #define regSDMA0_QUEUE2_MIDCMD_DATA10                                                                   0x017a
445 #define regSDMA0_QUEUE2_MIDCMD_DATA10_BASE_IDX                                                          0
446 #define regSDMA0_QUEUE2_MIDCMD_CNTL                                                                     0x017b
447 #define regSDMA0_QUEUE2_MIDCMD_CNTL_BASE_IDX                                                            0
448 #define regSDMA0_QUEUE3_RB_CNTL                                                                         0x0188
449 #define regSDMA0_QUEUE3_RB_CNTL_BASE_IDX                                                                0
450 #define regSDMA0_QUEUE3_RB_BASE                                                                         0x0189
451 #define regSDMA0_QUEUE3_RB_BASE_BASE_IDX                                                                0
452 #define regSDMA0_QUEUE3_RB_BASE_HI                                                                      0x018a
453 #define regSDMA0_QUEUE3_RB_BASE_HI_BASE_IDX                                                             0
454 #define regSDMA0_QUEUE3_RB_RPTR                                                                         0x018b
455 #define regSDMA0_QUEUE3_RB_RPTR_BASE_IDX                                                                0
456 #define regSDMA0_QUEUE3_RB_RPTR_HI                                                                      0x018c
457 #define regSDMA0_QUEUE3_RB_RPTR_HI_BASE_IDX                                                             0
458 #define regSDMA0_QUEUE3_RB_WPTR                                                                         0x018d
459 #define regSDMA0_QUEUE3_RB_WPTR_BASE_IDX                                                                0
460 #define regSDMA0_QUEUE3_RB_WPTR_HI                                                                      0x018e
461 #define regSDMA0_QUEUE3_RB_WPTR_HI_BASE_IDX                                                             0
462 #define regSDMA0_QUEUE3_RB_RPTR_ADDR_HI                                                                 0x0190
463 #define regSDMA0_QUEUE3_RB_RPTR_ADDR_HI_BASE_IDX                                                        0
464 #define regSDMA0_QUEUE3_RB_RPTR_ADDR_LO                                                                 0x0191
465 #define regSDMA0_QUEUE3_RB_RPTR_ADDR_LO_BASE_IDX                                                        0
466 #define regSDMA0_QUEUE3_IB_CNTL                                                                         0x0192
467 #define regSDMA0_QUEUE3_IB_CNTL_BASE_IDX                                                                0
468 #define regSDMA0_QUEUE3_IB_RPTR                                                                         0x0193
469 #define regSDMA0_QUEUE3_IB_RPTR_BASE_IDX                                                                0
470 #define regSDMA0_QUEUE3_IB_OFFSET                                                                       0x0194
471 #define regSDMA0_QUEUE3_IB_OFFSET_BASE_IDX                                                              0
472 #define regSDMA0_QUEUE3_IB_BASE_LO                                                                      0x0195
473 #define regSDMA0_QUEUE3_IB_BASE_LO_BASE_IDX                                                             0
474 #define regSDMA0_QUEUE3_IB_BASE_HI                                                                      0x0196
475 #define regSDMA0_QUEUE3_IB_BASE_HI_BASE_IDX                                                             0
476 #define regSDMA0_QUEUE3_IB_SIZE                                                                         0x0197
477 #define regSDMA0_QUEUE3_IB_SIZE_BASE_IDX                                                                0
478 #define regSDMA0_QUEUE3_SKIP_CNTL                                                                       0x0198
479 #define regSDMA0_QUEUE3_SKIP_CNTL_BASE_IDX                                                              0
480 #define regSDMA0_QUEUE3_CONTEXT_STATUS                                                                  0x0199
481 #define regSDMA0_QUEUE3_CONTEXT_STATUS_BASE_IDX                                                         0
482 #define regSDMA0_QUEUE3_DOORBELL                                                                        0x019a
483 #define regSDMA0_QUEUE3_DOORBELL_BASE_IDX                                                               0
484 #define regSDMA0_QUEUE3_DOORBELL_LOG                                                                    0x01b1
485 #define regSDMA0_QUEUE3_DOORBELL_LOG_BASE_IDX                                                           0
486 #define regSDMA0_QUEUE3_DOORBELL_OFFSET                                                                 0x01b3
487 #define regSDMA0_QUEUE3_DOORBELL_OFFSET_BASE_IDX                                                        0
488 #define regSDMA0_QUEUE3_CSA_ADDR_LO                                                                     0x01b4
489 #define regSDMA0_QUEUE3_CSA_ADDR_LO_BASE_IDX                                                            0
490 #define regSDMA0_QUEUE3_CSA_ADDR_HI                                                                     0x01b5
491 #define regSDMA0_QUEUE3_CSA_ADDR_HI_BASE_IDX                                                            0
492 #define regSDMA0_QUEUE3_SCHEDULE_CNTL                                                                   0x01b6
493 #define regSDMA0_QUEUE3_SCHEDULE_CNTL_BASE_IDX                                                          0
494 #define regSDMA0_QUEUE3_IB_SUB_REMAIN                                                                   0x01b7
495 #define regSDMA0_QUEUE3_IB_SUB_REMAIN_BASE_IDX                                                          0
496 #define regSDMA0_QUEUE3_PREEMPT                                                                         0x01b8
497 #define regSDMA0_QUEUE3_PREEMPT_BASE_IDX                                                                0
498 #define regSDMA0_QUEUE3_DUMMY_REG                                                                       0x01b9
499 #define regSDMA0_QUEUE3_DUMMY_REG_BASE_IDX                                                              0
500 #define regSDMA0_QUEUE3_RB_WPTR_POLL_ADDR_HI                                                            0x01ba
501 #define regSDMA0_QUEUE3_RB_WPTR_POLL_ADDR_HI_BASE_IDX                                                   0
502 #define regSDMA0_QUEUE3_RB_WPTR_POLL_ADDR_LO                                                            0x01bb
503 #define regSDMA0_QUEUE3_RB_WPTR_POLL_ADDR_LO_BASE_IDX                                                   0
504 #define regSDMA0_QUEUE3_RB_AQL_CNTL                                                                     0x01bc
505 #define regSDMA0_QUEUE3_RB_AQL_CNTL_BASE_IDX                                                            0
506 #define regSDMA0_QUEUE3_MINOR_PTR_UPDATE                                                                0x01bd
507 #define regSDMA0_QUEUE3_MINOR_PTR_UPDATE_BASE_IDX                                                       0
508 #define regSDMA0_QUEUE3_RB_PREEMPT                                                                      0x01be
509 #define regSDMA0_QUEUE3_RB_PREEMPT_BASE_IDX                                                             0
510 #define regSDMA0_QUEUE3_MIDCMD_DATA0                                                                    0x01c8
511 #define regSDMA0_QUEUE3_MIDCMD_DATA0_BASE_IDX                                                           0
512 #define regSDMA0_QUEUE3_MIDCMD_DATA1                                                                    0x01c9
513 #define regSDMA0_QUEUE3_MIDCMD_DATA1_BASE_IDX                                                           0
514 #define regSDMA0_QUEUE3_MIDCMD_DATA2                                                                    0x01ca
515 #define regSDMA0_QUEUE3_MIDCMD_DATA2_BASE_IDX                                                           0
516 #define regSDMA0_QUEUE3_MIDCMD_DATA3                                                                    0x01cb
517 #define regSDMA0_QUEUE3_MIDCMD_DATA3_BASE_IDX                                                           0
518 #define regSDMA0_QUEUE3_MIDCMD_DATA4                                                                    0x01cc
519 #define regSDMA0_QUEUE3_MIDCMD_DATA4_BASE_IDX                                                           0
520 #define regSDMA0_QUEUE3_MIDCMD_DATA5                                                                    0x01cd
521 #define regSDMA0_QUEUE3_MIDCMD_DATA5_BASE_IDX                                                           0
522 #define regSDMA0_QUEUE3_MIDCMD_DATA6                                                                    0x01ce
523 #define regSDMA0_QUEUE3_MIDCMD_DATA6_BASE_IDX                                                           0
524 #define regSDMA0_QUEUE3_MIDCMD_DATA7                                                                    0x01cf
525 #define regSDMA0_QUEUE3_MIDCMD_DATA7_BASE_IDX                                                           0
526 #define regSDMA0_QUEUE3_MIDCMD_DATA8                                                                    0x01d0
527 #define regSDMA0_QUEUE3_MIDCMD_DATA8_BASE_IDX                                                           0
528 #define regSDMA0_QUEUE3_MIDCMD_DATA9                                                                    0x01d1
529 #define regSDMA0_QUEUE3_MIDCMD_DATA9_BASE_IDX                                                           0
530 #define regSDMA0_QUEUE3_MIDCMD_DATA10                                                                   0x01d2
531 #define regSDMA0_QUEUE3_MIDCMD_DATA10_BASE_IDX                                                          0
532 #define regSDMA0_QUEUE3_MIDCMD_CNTL                                                                     0x01d3
533 #define regSDMA0_QUEUE3_MIDCMD_CNTL_BASE_IDX                                                            0
534 #define regSDMA0_QUEUE4_RB_CNTL                                                                         0x01e0
535 #define regSDMA0_QUEUE4_RB_CNTL_BASE_IDX                                                                0
536 #define regSDMA0_QUEUE4_RB_BASE                                                                         0x01e1
537 #define regSDMA0_QUEUE4_RB_BASE_BASE_IDX                                                                0
538 #define regSDMA0_QUEUE4_RB_BASE_HI                                                                      0x01e2
539 #define regSDMA0_QUEUE4_RB_BASE_HI_BASE_IDX                                                             0
540 #define regSDMA0_QUEUE4_RB_RPTR                                                                         0x01e3
541 #define regSDMA0_QUEUE4_RB_RPTR_BASE_IDX                                                                0
542 #define regSDMA0_QUEUE4_RB_RPTR_HI                                                                      0x01e4
543 #define regSDMA0_QUEUE4_RB_RPTR_HI_BASE_IDX                                                             0
544 #define regSDMA0_QUEUE4_RB_WPTR                                                                         0x01e5
545 #define regSDMA0_QUEUE4_RB_WPTR_BASE_IDX                                                                0
546 #define regSDMA0_QUEUE4_RB_WPTR_HI                                                                      0x01e6
547 #define regSDMA0_QUEUE4_RB_WPTR_HI_BASE_IDX                                                             0
548 #define regSDMA0_QUEUE4_RB_RPTR_ADDR_HI                                                                 0x01e8
549 #define regSDMA0_QUEUE4_RB_RPTR_ADDR_HI_BASE_IDX                                                        0
550 #define regSDMA0_QUEUE4_RB_RPTR_ADDR_LO                                                                 0x01e9
551 #define regSDMA0_QUEUE4_RB_RPTR_ADDR_LO_BASE_IDX                                                        0
552 #define regSDMA0_QUEUE4_IB_CNTL                                                                         0x01ea
553 #define regSDMA0_QUEUE4_IB_CNTL_BASE_IDX                                                                0
554 #define regSDMA0_QUEUE4_IB_RPTR                                                                         0x01eb
555 #define regSDMA0_QUEUE4_IB_RPTR_BASE_IDX                                                                0
556 #define regSDMA0_QUEUE4_IB_OFFSET                                                                       0x01ec
557 #define regSDMA0_QUEUE4_IB_OFFSET_BASE_IDX                                                              0
558 #define regSDMA0_QUEUE4_IB_BASE_LO                                                                      0x01ed
559 #define regSDMA0_QUEUE4_IB_BASE_LO_BASE_IDX                                                             0
560 #define regSDMA0_QUEUE4_IB_BASE_HI                                                                      0x01ee
561 #define regSDMA0_QUEUE4_IB_BASE_HI_BASE_IDX                                                             0
562 #define regSDMA0_QUEUE4_IB_SIZE                                                                         0x01ef
563 #define regSDMA0_QUEUE4_IB_SIZE_BASE_IDX                                                                0
564 #define regSDMA0_QUEUE4_SKIP_CNTL                                                                       0x01f0
565 #define regSDMA0_QUEUE4_SKIP_CNTL_BASE_IDX                                                              0
566 #define regSDMA0_QUEUE4_CONTEXT_STATUS                                                                  0x01f1
567 #define regSDMA0_QUEUE4_CONTEXT_STATUS_BASE_IDX                                                         0
568 #define regSDMA0_QUEUE4_DOORBELL                                                                        0x01f2
569 #define regSDMA0_QUEUE4_DOORBELL_BASE_IDX                                                               0
570 #define regSDMA0_QUEUE4_DOORBELL_LOG                                                                    0x0209
571 #define regSDMA0_QUEUE4_DOORBELL_LOG_BASE_IDX                                                           0
572 #define regSDMA0_QUEUE4_DOORBELL_OFFSET                                                                 0x020b
573 #define regSDMA0_QUEUE4_DOORBELL_OFFSET_BASE_IDX                                                        0
574 #define regSDMA0_QUEUE4_CSA_ADDR_LO                                                                     0x020c
575 #define regSDMA0_QUEUE4_CSA_ADDR_LO_BASE_IDX                                                            0
576 #define regSDMA0_QUEUE4_CSA_ADDR_HI                                                                     0x020d
577 #define regSDMA0_QUEUE4_CSA_ADDR_HI_BASE_IDX                                                            0
578 #define regSDMA0_QUEUE4_SCHEDULE_CNTL                                                                   0x020e
579 #define regSDMA0_QUEUE4_SCHEDULE_CNTL_BASE_IDX                                                          0
580 #define regSDMA0_QUEUE4_IB_SUB_REMAIN                                                                   0x020f
581 #define regSDMA0_QUEUE4_IB_SUB_REMAIN_BASE_IDX                                                          0
582 #define regSDMA0_QUEUE4_PREEMPT                                                                         0x0210
583 #define regSDMA0_QUEUE4_PREEMPT_BASE_IDX                                                                0
584 #define regSDMA0_QUEUE4_DUMMY_REG                                                                       0x0211
585 #define regSDMA0_QUEUE4_DUMMY_REG_BASE_IDX                                                              0
586 #define regSDMA0_QUEUE4_RB_WPTR_POLL_ADDR_HI                                                            0x0212
587 #define regSDMA0_QUEUE4_RB_WPTR_POLL_ADDR_HI_BASE_IDX                                                   0
588 #define regSDMA0_QUEUE4_RB_WPTR_POLL_ADDR_LO                                                            0x0213
589 #define regSDMA0_QUEUE4_RB_WPTR_POLL_ADDR_LO_BASE_IDX                                                   0
590 #define regSDMA0_QUEUE4_RB_AQL_CNTL                                                                     0x0214
591 #define regSDMA0_QUEUE4_RB_AQL_CNTL_BASE_IDX                                                            0
592 #define regSDMA0_QUEUE4_MINOR_PTR_UPDATE                                                                0x0215
593 #define regSDMA0_QUEUE4_MINOR_PTR_UPDATE_BASE_IDX                                                       0
594 #define regSDMA0_QUEUE4_RB_PREEMPT                                                                      0x0216
595 #define regSDMA0_QUEUE4_RB_PREEMPT_BASE_IDX                                                             0
596 #define regSDMA0_QUEUE4_MIDCMD_DATA0                                                                    0x0220
597 #define regSDMA0_QUEUE4_MIDCMD_DATA0_BASE_IDX                                                           0
598 #define regSDMA0_QUEUE4_MIDCMD_DATA1                                                                    0x0221
599 #define regSDMA0_QUEUE4_MIDCMD_DATA1_BASE_IDX                                                           0
600 #define regSDMA0_QUEUE4_MIDCMD_DATA2                                                                    0x0222
601 #define regSDMA0_QUEUE4_MIDCMD_DATA2_BASE_IDX                                                           0
602 #define regSDMA0_QUEUE4_MIDCMD_DATA3                                                                    0x0223
603 #define regSDMA0_QUEUE4_MIDCMD_DATA3_BASE_IDX                                                           0
604 #define regSDMA0_QUEUE4_MIDCMD_DATA4                                                                    0x0224
605 #define regSDMA0_QUEUE4_MIDCMD_DATA4_BASE_IDX                                                           0
606 #define regSDMA0_QUEUE4_MIDCMD_DATA5                                                                    0x0225
607 #define regSDMA0_QUEUE4_MIDCMD_DATA5_BASE_IDX                                                           0
608 #define regSDMA0_QUEUE4_MIDCMD_DATA6                                                                    0x0226
609 #define regSDMA0_QUEUE4_MIDCMD_DATA6_BASE_IDX                                                           0
610 #define regSDMA0_QUEUE4_MIDCMD_DATA7                                                                    0x0227
611 #define regSDMA0_QUEUE4_MIDCMD_DATA7_BASE_IDX                                                           0
612 #define regSDMA0_QUEUE4_MIDCMD_DATA8                                                                    0x0228
613 #define regSDMA0_QUEUE4_MIDCMD_DATA8_BASE_IDX                                                           0
614 #define regSDMA0_QUEUE4_MIDCMD_DATA9                                                                    0x0229
615 #define regSDMA0_QUEUE4_MIDCMD_DATA9_BASE_IDX                                                           0
616 #define regSDMA0_QUEUE4_MIDCMD_DATA10                                                                   0x022a
617 #define regSDMA0_QUEUE4_MIDCMD_DATA10_BASE_IDX                                                          0
618 #define regSDMA0_QUEUE4_MIDCMD_CNTL                                                                     0x022b
619 #define regSDMA0_QUEUE4_MIDCMD_CNTL_BASE_IDX                                                            0
620 #define regSDMA0_QUEUE5_RB_CNTL                                                                         0x0238
621 #define regSDMA0_QUEUE5_RB_CNTL_BASE_IDX                                                                0
622 #define regSDMA0_QUEUE5_RB_BASE                                                                         0x0239
623 #define regSDMA0_QUEUE5_RB_BASE_BASE_IDX                                                                0
624 #define regSDMA0_QUEUE5_RB_BASE_HI                                                                      0x023a
625 #define regSDMA0_QUEUE5_RB_BASE_HI_BASE_IDX                                                             0
626 #define regSDMA0_QUEUE5_RB_RPTR                                                                         0x023b
627 #define regSDMA0_QUEUE5_RB_RPTR_BASE_IDX                                                                0
628 #define regSDMA0_QUEUE5_RB_RPTR_HI                                                                      0x023c
629 #define regSDMA0_QUEUE5_RB_RPTR_HI_BASE_IDX                                                             0
630 #define regSDMA0_QUEUE5_RB_WPTR                                                                         0x023d
631 #define regSDMA0_QUEUE5_RB_WPTR_BASE_IDX                                                                0
632 #define regSDMA0_QUEUE5_RB_WPTR_HI                                                                      0x023e
633 #define regSDMA0_QUEUE5_RB_WPTR_HI_BASE_IDX                                                             0
634 #define regSDMA0_QUEUE5_RB_RPTR_ADDR_HI                                                                 0x0240
635 #define regSDMA0_QUEUE5_RB_RPTR_ADDR_HI_BASE_IDX                                                        0
636 #define regSDMA0_QUEUE5_RB_RPTR_ADDR_LO                                                                 0x0241
637 #define regSDMA0_QUEUE5_RB_RPTR_ADDR_LO_BASE_IDX                                                        0
638 #define regSDMA0_QUEUE5_IB_CNTL                                                                         0x0242
639 #define regSDMA0_QUEUE5_IB_CNTL_BASE_IDX                                                                0
640 #define regSDMA0_QUEUE5_IB_RPTR                                                                         0x0243
641 #define regSDMA0_QUEUE5_IB_RPTR_BASE_IDX                                                                0
642 #define regSDMA0_QUEUE5_IB_OFFSET                                                                       0x0244
643 #define regSDMA0_QUEUE5_IB_OFFSET_BASE_IDX                                                              0
644 #define regSDMA0_QUEUE5_IB_BASE_LO                                                                      0x0245
645 #define regSDMA0_QUEUE5_IB_BASE_LO_BASE_IDX                                                             0
646 #define regSDMA0_QUEUE5_IB_BASE_HI                                                                      0x0246
647 #define regSDMA0_QUEUE5_IB_BASE_HI_BASE_IDX                                                             0
648 #define regSDMA0_QUEUE5_IB_SIZE                                                                         0x0247
649 #define regSDMA0_QUEUE5_IB_SIZE_BASE_IDX                                                                0
650 #define regSDMA0_QUEUE5_SKIP_CNTL                                                                       0x0248
651 #define regSDMA0_QUEUE5_SKIP_CNTL_BASE_IDX                                                              0
652 #define regSDMA0_QUEUE5_CONTEXT_STATUS                                                                  0x0249
653 #define regSDMA0_QUEUE5_CONTEXT_STATUS_BASE_IDX                                                         0
654 #define regSDMA0_QUEUE5_DOORBELL                                                                        0x024a
655 #define regSDMA0_QUEUE5_DOORBELL_BASE_IDX                                                               0
656 #define regSDMA0_QUEUE5_DOORBELL_LOG                                                                    0x0261
657 #define regSDMA0_QUEUE5_DOORBELL_LOG_BASE_IDX                                                           0
658 #define regSDMA0_QUEUE5_DOORBELL_OFFSET                                                                 0x0263
659 #define regSDMA0_QUEUE5_DOORBELL_OFFSET_BASE_IDX                                                        0
660 #define regSDMA0_QUEUE5_CSA_ADDR_LO                                                                     0x0264
661 #define regSDMA0_QUEUE5_CSA_ADDR_LO_BASE_IDX                                                            0
662 #define regSDMA0_QUEUE5_CSA_ADDR_HI                                                                     0x0265
663 #define regSDMA0_QUEUE5_CSA_ADDR_HI_BASE_IDX                                                            0
664 #define regSDMA0_QUEUE5_SCHEDULE_CNTL                                                                   0x0266
665 #define regSDMA0_QUEUE5_SCHEDULE_CNTL_BASE_IDX                                                          0
666 #define regSDMA0_QUEUE5_IB_SUB_REMAIN                                                                   0x0267
667 #define regSDMA0_QUEUE5_IB_SUB_REMAIN_BASE_IDX                                                          0
668 #define regSDMA0_QUEUE5_PREEMPT                                                                         0x0268
669 #define regSDMA0_QUEUE5_PREEMPT_BASE_IDX                                                                0
670 #define regSDMA0_QUEUE5_DUMMY_REG                                                                       0x0269
671 #define regSDMA0_QUEUE5_DUMMY_REG_BASE_IDX                                                              0
672 #define regSDMA0_QUEUE5_RB_WPTR_POLL_ADDR_HI                                                            0x026a
673 #define regSDMA0_QUEUE5_RB_WPTR_POLL_ADDR_HI_BASE_IDX                                                   0
674 #define regSDMA0_QUEUE5_RB_WPTR_POLL_ADDR_LO                                                            0x026b
675 #define regSDMA0_QUEUE5_RB_WPTR_POLL_ADDR_LO_BASE_IDX                                                   0
676 #define regSDMA0_QUEUE5_RB_AQL_CNTL                                                                     0x026c
677 #define regSDMA0_QUEUE5_RB_AQL_CNTL_BASE_IDX                                                            0
678 #define regSDMA0_QUEUE5_MINOR_PTR_UPDATE                                                                0x026d
679 #define regSDMA0_QUEUE5_MINOR_PTR_UPDATE_BASE_IDX                                                       0
680 #define regSDMA0_QUEUE5_RB_PREEMPT                                                                      0x026e
681 #define regSDMA0_QUEUE5_RB_PREEMPT_BASE_IDX                                                             0
682 #define regSDMA0_QUEUE5_MIDCMD_DATA0                                                                    0x0278
683 #define regSDMA0_QUEUE5_MIDCMD_DATA0_BASE_IDX                                                           0
684 #define regSDMA0_QUEUE5_MIDCMD_DATA1                                                                    0x0279
685 #define regSDMA0_QUEUE5_MIDCMD_DATA1_BASE_IDX                                                           0
686 #define regSDMA0_QUEUE5_MIDCMD_DATA2                                                                    0x027a
687 #define regSDMA0_QUEUE5_MIDCMD_DATA2_BASE_IDX                                                           0
688 #define regSDMA0_QUEUE5_MIDCMD_DATA3                                                                    0x027b
689 #define regSDMA0_QUEUE5_MIDCMD_DATA3_BASE_IDX                                                           0
690 #define regSDMA0_QUEUE5_MIDCMD_DATA4                                                                    0x027c
691 #define regSDMA0_QUEUE5_MIDCMD_DATA4_BASE_IDX                                                           0
692 #define regSDMA0_QUEUE5_MIDCMD_DATA5                                                                    0x027d
693 #define regSDMA0_QUEUE5_MIDCMD_DATA5_BASE_IDX                                                           0
694 #define regSDMA0_QUEUE5_MIDCMD_DATA6                                                                    0x027e
695 #define regSDMA0_QUEUE5_MIDCMD_DATA6_BASE_IDX                                                           0
696 #define regSDMA0_QUEUE5_MIDCMD_DATA7                                                                    0x027f
697 #define regSDMA0_QUEUE5_MIDCMD_DATA7_BASE_IDX                                                           0
698 #define regSDMA0_QUEUE5_MIDCMD_DATA8                                                                    0x0280
699 #define regSDMA0_QUEUE5_MIDCMD_DATA8_BASE_IDX                                                           0
700 #define regSDMA0_QUEUE5_MIDCMD_DATA9                                                                    0x0281
701 #define regSDMA0_QUEUE5_MIDCMD_DATA9_BASE_IDX                                                           0
702 #define regSDMA0_QUEUE5_MIDCMD_DATA10                                                                   0x0282
703 #define regSDMA0_QUEUE5_MIDCMD_DATA10_BASE_IDX                                                          0
704 #define regSDMA0_QUEUE5_MIDCMD_CNTL                                                                     0x0283
705 #define regSDMA0_QUEUE5_MIDCMD_CNTL_BASE_IDX                                                            0
706 #define regSDMA0_QUEUE6_RB_CNTL                                                                         0x0290
707 #define regSDMA0_QUEUE6_RB_CNTL_BASE_IDX                                                                0
708 #define regSDMA0_QUEUE6_RB_BASE                                                                         0x0291
709 #define regSDMA0_QUEUE6_RB_BASE_BASE_IDX                                                                0
710 #define regSDMA0_QUEUE6_RB_BASE_HI                                                                      0x0292
711 #define regSDMA0_QUEUE6_RB_BASE_HI_BASE_IDX                                                             0
712 #define regSDMA0_QUEUE6_RB_RPTR                                                                         0x0293
713 #define regSDMA0_QUEUE6_RB_RPTR_BASE_IDX                                                                0
714 #define regSDMA0_QUEUE6_RB_RPTR_HI                                                                      0x0294
715 #define regSDMA0_QUEUE6_RB_RPTR_HI_BASE_IDX                                                             0
716 #define regSDMA0_QUEUE6_RB_WPTR                                                                         0x0295
717 #define regSDMA0_QUEUE6_RB_WPTR_BASE_IDX                                                                0
718 #define regSDMA0_QUEUE6_RB_WPTR_HI                                                                      0x0296
719 #define regSDMA0_QUEUE6_RB_WPTR_HI_BASE_IDX                                                             0
720 #define regSDMA0_QUEUE6_RB_RPTR_ADDR_HI                                                                 0x0298
721 #define regSDMA0_QUEUE6_RB_RPTR_ADDR_HI_BASE_IDX                                                        0
722 #define regSDMA0_QUEUE6_RB_RPTR_ADDR_LO                                                                 0x0299
723 #define regSDMA0_QUEUE6_RB_RPTR_ADDR_LO_BASE_IDX                                                        0
724 #define regSDMA0_QUEUE6_IB_CNTL                                                                         0x029a
725 #define regSDMA0_QUEUE6_IB_CNTL_BASE_IDX                                                                0
726 #define regSDMA0_QUEUE6_IB_RPTR                                                                         0x029b
727 #define regSDMA0_QUEUE6_IB_RPTR_BASE_IDX                                                                0
728 #define regSDMA0_QUEUE6_IB_OFFSET                                                                       0x029c
729 #define regSDMA0_QUEUE6_IB_OFFSET_BASE_IDX                                                              0
730 #define regSDMA0_QUEUE6_IB_BASE_LO                                                                      0x029d
731 #define regSDMA0_QUEUE6_IB_BASE_LO_BASE_IDX                                                             0
732 #define regSDMA0_QUEUE6_IB_BASE_HI                                                                      0x029e
733 #define regSDMA0_QUEUE6_IB_BASE_HI_BASE_IDX                                                             0
734 #define regSDMA0_QUEUE6_IB_SIZE                                                                         0x029f
735 #define regSDMA0_QUEUE6_IB_SIZE_BASE_IDX                                                                0
736 #define regSDMA0_QUEUE6_SKIP_CNTL                                                                       0x02a0
737 #define regSDMA0_QUEUE6_SKIP_CNTL_BASE_IDX                                                              0
738 #define regSDMA0_QUEUE6_CONTEXT_STATUS                                                                  0x02a1
739 #define regSDMA0_QUEUE6_CONTEXT_STATUS_BASE_IDX                                                         0
740 #define regSDMA0_QUEUE6_DOORBELL                                                                        0x02a2
741 #define regSDMA0_QUEUE6_DOORBELL_BASE_IDX                                                               0
742 #define regSDMA0_QUEUE6_DOORBELL_LOG                                                                    0x02b9
743 #define regSDMA0_QUEUE6_DOORBELL_LOG_BASE_IDX                                                           0
744 #define regSDMA0_QUEUE6_DOORBELL_OFFSET                                                                 0x02bb
745 #define regSDMA0_QUEUE6_DOORBELL_OFFSET_BASE_IDX                                                        0
746 #define regSDMA0_QUEUE6_CSA_ADDR_LO                                                                     0x02bc
747 #define regSDMA0_QUEUE6_CSA_ADDR_LO_BASE_IDX                                                            0
748 #define regSDMA0_QUEUE6_CSA_ADDR_HI                                                                     0x02bd
749 #define regSDMA0_QUEUE6_CSA_ADDR_HI_BASE_IDX                                                            0
750 #define regSDMA0_QUEUE6_SCHEDULE_CNTL                                                                   0x02be
751 #define regSDMA0_QUEUE6_SCHEDULE_CNTL_BASE_IDX                                                          0
752 #define regSDMA0_QUEUE6_IB_SUB_REMAIN                                                                   0x02bf
753 #define regSDMA0_QUEUE6_IB_SUB_REMAIN_BASE_IDX                                                          0
754 #define regSDMA0_QUEUE6_PREEMPT                                                                         0x02c0
755 #define regSDMA0_QUEUE6_PREEMPT_BASE_IDX                                                                0
756 #define regSDMA0_QUEUE6_DUMMY_REG                                                                       0x02c1
757 #define regSDMA0_QUEUE6_DUMMY_REG_BASE_IDX                                                              0
758 #define regSDMA0_QUEUE6_RB_WPTR_POLL_ADDR_HI                                                            0x02c2
759 #define regSDMA0_QUEUE6_RB_WPTR_POLL_ADDR_HI_BASE_IDX                                                   0
760 #define regSDMA0_QUEUE6_RB_WPTR_POLL_ADDR_LO                                                            0x02c3
761 #define regSDMA0_QUEUE6_RB_WPTR_POLL_ADDR_LO_BASE_IDX                                                   0
762 #define regSDMA0_QUEUE6_RB_AQL_CNTL                                                                     0x02c4
763 #define regSDMA0_QUEUE6_RB_AQL_CNTL_BASE_IDX                                                            0
764 #define regSDMA0_QUEUE6_MINOR_PTR_UPDATE                                                                0x02c5
765 #define regSDMA0_QUEUE6_MINOR_PTR_UPDATE_BASE_IDX                                                       0
766 #define regSDMA0_QUEUE6_RB_PREEMPT                                                                      0x02c6
767 #define regSDMA0_QUEUE6_RB_PREEMPT_BASE_IDX                                                             0
768 #define regSDMA0_QUEUE6_MIDCMD_DATA0                                                                    0x02d0
769 #define regSDMA0_QUEUE6_MIDCMD_DATA0_BASE_IDX                                                           0
770 #define regSDMA0_QUEUE6_MIDCMD_DATA1                                                                    0x02d1
771 #define regSDMA0_QUEUE6_MIDCMD_DATA1_BASE_IDX                                                           0
772 #define regSDMA0_QUEUE6_MIDCMD_DATA2                                                                    0x02d2
773 #define regSDMA0_QUEUE6_MIDCMD_DATA2_BASE_IDX                                                           0
774 #define regSDMA0_QUEUE6_MIDCMD_DATA3                                                                    0x02d3
775 #define regSDMA0_QUEUE6_MIDCMD_DATA3_BASE_IDX                                                           0
776 #define regSDMA0_QUEUE6_MIDCMD_DATA4                                                                    0x02d4
777 #define regSDMA0_QUEUE6_MIDCMD_DATA4_BASE_IDX                                                           0
778 #define regSDMA0_QUEUE6_MIDCMD_DATA5                                                                    0x02d5
779 #define regSDMA0_QUEUE6_MIDCMD_DATA5_BASE_IDX                                                           0
780 #define regSDMA0_QUEUE6_MIDCMD_DATA6                                                                    0x02d6
781 #define regSDMA0_QUEUE6_MIDCMD_DATA6_BASE_IDX                                                           0
782 #define regSDMA0_QUEUE6_MIDCMD_DATA7                                                                    0x02d7
783 #define regSDMA0_QUEUE6_MIDCMD_DATA7_BASE_IDX                                                           0
784 #define regSDMA0_QUEUE6_MIDCMD_DATA8                                                                    0x02d8
785 #define regSDMA0_QUEUE6_MIDCMD_DATA8_BASE_IDX                                                           0
786 #define regSDMA0_QUEUE6_MIDCMD_DATA9                                                                    0x02d9
787 #define regSDMA0_QUEUE6_MIDCMD_DATA9_BASE_IDX                                                           0
788 #define regSDMA0_QUEUE6_MIDCMD_DATA10                                                                   0x02da
789 #define regSDMA0_QUEUE6_MIDCMD_DATA10_BASE_IDX                                                          0
790 #define regSDMA0_QUEUE6_MIDCMD_CNTL                                                                     0x02db
791 #define regSDMA0_QUEUE6_MIDCMD_CNTL_BASE_IDX                                                            0
792 #define regSDMA0_QUEUE7_RB_CNTL                                                                         0x02e8
793 #define regSDMA0_QUEUE7_RB_CNTL_BASE_IDX                                                                0
794 #define regSDMA0_QUEUE7_RB_BASE                                                                         0x02e9
795 #define regSDMA0_QUEUE7_RB_BASE_BASE_IDX                                                                0
796 #define regSDMA0_QUEUE7_RB_BASE_HI                                                                      0x02ea
797 #define regSDMA0_QUEUE7_RB_BASE_HI_BASE_IDX                                                             0
798 #define regSDMA0_QUEUE7_RB_RPTR                                                                         0x02eb
799 #define regSDMA0_QUEUE7_RB_RPTR_BASE_IDX                                                                0
800 #define regSDMA0_QUEUE7_RB_RPTR_HI                                                                      0x02ec
801 #define regSDMA0_QUEUE7_RB_RPTR_HI_BASE_IDX                                                             0
802 #define regSDMA0_QUEUE7_RB_WPTR                                                                         0x02ed
803 #define regSDMA0_QUEUE7_RB_WPTR_BASE_IDX                                                                0
804 #define regSDMA0_QUEUE7_RB_WPTR_HI                                                                      0x02ee
805 #define regSDMA0_QUEUE7_RB_WPTR_HI_BASE_IDX                                                             0
806 #define regSDMA0_QUEUE7_RB_RPTR_ADDR_HI                                                                 0x02f0
807 #define regSDMA0_QUEUE7_RB_RPTR_ADDR_HI_BASE_IDX                                                        0
808 #define regSDMA0_QUEUE7_RB_RPTR_ADDR_LO                                                                 0x02f1
809 #define regSDMA0_QUEUE7_RB_RPTR_ADDR_LO_BASE_IDX                                                        0
810 #define regSDMA0_QUEUE7_IB_CNTL                                                                         0x02f2
811 #define regSDMA0_QUEUE7_IB_CNTL_BASE_IDX                                                                0
812 #define regSDMA0_QUEUE7_IB_RPTR                                                                         0x02f3
813 #define regSDMA0_QUEUE7_IB_RPTR_BASE_IDX                                                                0
814 #define regSDMA0_QUEUE7_IB_OFFSET                                                                       0x02f4
815 #define regSDMA0_QUEUE7_IB_OFFSET_BASE_IDX                                                              0
816 #define regSDMA0_QUEUE7_IB_BASE_LO                                                                      0x02f5
817 #define regSDMA0_QUEUE7_IB_BASE_LO_BASE_IDX                                                             0
818 #define regSDMA0_QUEUE7_IB_BASE_HI                                                                      0x02f6
819 #define regSDMA0_QUEUE7_IB_BASE_HI_BASE_IDX                                                             0
820 #define regSDMA0_QUEUE7_IB_SIZE                                                                         0x02f7
821 #define regSDMA0_QUEUE7_IB_SIZE_BASE_IDX                                                                0
822 #define regSDMA0_QUEUE7_SKIP_CNTL                                                                       0x02f8
823 #define regSDMA0_QUEUE7_SKIP_CNTL_BASE_IDX                                                              0
824 #define regSDMA0_QUEUE7_CONTEXT_STATUS                                                                  0x02f9
825 #define regSDMA0_QUEUE7_CONTEXT_STATUS_BASE_IDX                                                         0
826 #define regSDMA0_QUEUE7_DOORBELL                                                                        0x02fa
827 #define regSDMA0_QUEUE7_DOORBELL_BASE_IDX                                                               0
828 #define regSDMA0_QUEUE7_DOORBELL_LOG                                                                    0x0311
829 #define regSDMA0_QUEUE7_DOORBELL_LOG_BASE_IDX                                                           0
830 #define regSDMA0_QUEUE7_DOORBELL_OFFSET                                                                 0x0313
831 #define regSDMA0_QUEUE7_DOORBELL_OFFSET_BASE_IDX                                                        0
832 #define regSDMA0_QUEUE7_CSA_ADDR_LO                                                                     0x0314
833 #define regSDMA0_QUEUE7_CSA_ADDR_LO_BASE_IDX                                                            0
834 #define regSDMA0_QUEUE7_CSA_ADDR_HI                                                                     0x0315
835 #define regSDMA0_QUEUE7_CSA_ADDR_HI_BASE_IDX                                                            0
836 #define regSDMA0_QUEUE7_SCHEDULE_CNTL                                                                   0x0316
837 #define regSDMA0_QUEUE7_SCHEDULE_CNTL_BASE_IDX                                                          0
838 #define regSDMA0_QUEUE7_IB_SUB_REMAIN                                                                   0x0317
839 #define regSDMA0_QUEUE7_IB_SUB_REMAIN_BASE_IDX                                                          0
840 #define regSDMA0_QUEUE7_PREEMPT                                                                         0x0318
841 #define regSDMA0_QUEUE7_PREEMPT_BASE_IDX                                                                0
842 #define regSDMA0_QUEUE7_DUMMY_REG                                                                       0x0319
843 #define regSDMA0_QUEUE7_DUMMY_REG_BASE_IDX                                                              0
844 #define regSDMA0_QUEUE7_RB_WPTR_POLL_ADDR_HI                                                            0x031a
845 #define regSDMA0_QUEUE7_RB_WPTR_POLL_ADDR_HI_BASE_IDX                                                   0
846 #define regSDMA0_QUEUE7_RB_WPTR_POLL_ADDR_LO                                                            0x031b
847 #define regSDMA0_QUEUE7_RB_WPTR_POLL_ADDR_LO_BASE_IDX                                                   0
848 #define regSDMA0_QUEUE7_RB_AQL_CNTL                                                                     0x031c
849 #define regSDMA0_QUEUE7_RB_AQL_CNTL_BASE_IDX                                                            0
850 #define regSDMA0_QUEUE7_MINOR_PTR_UPDATE                                                                0x031d
851 #define regSDMA0_QUEUE7_MINOR_PTR_UPDATE_BASE_IDX                                                       0
852 #define regSDMA0_QUEUE7_RB_PREEMPT                                                                      0x031e
853 #define regSDMA0_QUEUE7_RB_PREEMPT_BASE_IDX                                                             0
854 #define regSDMA0_QUEUE7_MIDCMD_DATA0                                                                    0x0328
855 #define regSDMA0_QUEUE7_MIDCMD_DATA0_BASE_IDX                                                           0
856 #define regSDMA0_QUEUE7_MIDCMD_DATA1                                                                    0x0329
857 #define regSDMA0_QUEUE7_MIDCMD_DATA1_BASE_IDX                                                           0
858 #define regSDMA0_QUEUE7_MIDCMD_DATA2                                                                    0x032a
859 #define regSDMA0_QUEUE7_MIDCMD_DATA2_BASE_IDX                                                           0
860 #define regSDMA0_QUEUE7_MIDCMD_DATA3                                                                    0x032b
861 #define regSDMA0_QUEUE7_MIDCMD_DATA3_BASE_IDX                                                           0
862 #define regSDMA0_QUEUE7_MIDCMD_DATA4                                                                    0x032c
863 #define regSDMA0_QUEUE7_MIDCMD_DATA4_BASE_IDX                                                           0
864 #define regSDMA0_QUEUE7_MIDCMD_DATA5                                                                    0x032d
865 #define regSDMA0_QUEUE7_MIDCMD_DATA5_BASE_IDX                                                           0
866 #define regSDMA0_QUEUE7_MIDCMD_DATA6                                                                    0x032e
867 #define regSDMA0_QUEUE7_MIDCMD_DATA6_BASE_IDX                                                           0
868 #define regSDMA0_QUEUE7_MIDCMD_DATA7                                                                    0x032f
869 #define regSDMA0_QUEUE7_MIDCMD_DATA7_BASE_IDX                                                           0
870 #define regSDMA0_QUEUE7_MIDCMD_DATA8                                                                    0x0330
871 #define regSDMA0_QUEUE7_MIDCMD_DATA8_BASE_IDX                                                           0
872 #define regSDMA0_QUEUE7_MIDCMD_DATA9                                                                    0x0331
873 #define regSDMA0_QUEUE7_MIDCMD_DATA9_BASE_IDX                                                           0
874 #define regSDMA0_QUEUE7_MIDCMD_DATA10                                                                   0x0332
875 #define regSDMA0_QUEUE7_MIDCMD_DATA10_BASE_IDX                                                          0
876 #define regSDMA0_QUEUE7_MIDCMD_CNTL                                                                     0x0333
877 #define regSDMA0_QUEUE7_MIDCMD_CNTL_BASE_IDX                                                            0
878 
879 
880 // addressBlock: gc_sdma0_sdma1dec
881 // base address: 0x6180
882 #define regSDMA1_DEC_START                                                                              0x0600
883 #define regSDMA1_DEC_START_BASE_IDX                                                                     0
884 #define regSDMA1_F32_MISC_CNTL                                                                          0x060b
885 #define regSDMA1_F32_MISC_CNTL_BASE_IDX                                                                 0
886 #define regSDMA1_GLOBAL_TIMESTAMP_LO                                                                    0x060f
887 #define regSDMA1_GLOBAL_TIMESTAMP_LO_BASE_IDX                                                           0
888 #define regSDMA1_GLOBAL_TIMESTAMP_HI                                                                    0x0610
889 #define regSDMA1_GLOBAL_TIMESTAMP_HI_BASE_IDX                                                           0
890 #define regSDMA1_POWER_CNTL                                                                             0x061a
891 #define regSDMA1_POWER_CNTL_BASE_IDX                                                                    0
892 #define regSDMA1_CNTL                                                                                   0x061c
893 #define regSDMA1_CNTL_BASE_IDX                                                                          0
894 #define regSDMA1_CHICKEN_BITS                                                                           0x061d
895 #define regSDMA1_CHICKEN_BITS_BASE_IDX                                                                  0
896 #define regSDMA1_GB_ADDR_CONFIG                                                                         0x061e
897 #define regSDMA1_GB_ADDR_CONFIG_BASE_IDX                                                                0
898 #define regSDMA1_GB_ADDR_CONFIG_READ                                                                    0x061f
899 #define regSDMA1_GB_ADDR_CONFIG_READ_BASE_IDX                                                           0
900 #define regSDMA1_RB_RPTR_FETCH                                                                          0x0620
901 #define regSDMA1_RB_RPTR_FETCH_BASE_IDX                                                                 0
902 #define regSDMA1_RB_RPTR_FETCH_HI                                                                       0x0621
903 #define regSDMA1_RB_RPTR_FETCH_HI_BASE_IDX                                                              0
904 #define regSDMA1_SEM_WAIT_FAIL_TIMER_CNTL                                                               0x0622
905 #define regSDMA1_SEM_WAIT_FAIL_TIMER_CNTL_BASE_IDX                                                      0
906 #define regSDMA1_IB_OFFSET_FETCH                                                                        0x0623
907 #define regSDMA1_IB_OFFSET_FETCH_BASE_IDX                                                               0
908 #define regSDMA1_PROGRAM                                                                                0x0624
909 #define regSDMA1_PROGRAM_BASE_IDX                                                                       0
910 #define regSDMA1_STATUS_REG                                                                             0x0625
911 #define regSDMA1_STATUS_REG_BASE_IDX                                                                    0
912 #define regSDMA1_STATUS1_REG                                                                            0x0626
913 #define regSDMA1_STATUS1_REG_BASE_IDX                                                                   0
914 #define regSDMA1_CNTL1                                                                                  0x0627
915 #define regSDMA1_CNTL1_BASE_IDX                                                                         0
916 #define regSDMA1_HBM_PAGE_CONFIG                                                                        0x0628
917 #define regSDMA1_HBM_PAGE_CONFIG_BASE_IDX                                                               0
918 #define regSDMA1_UCODE_CHECKSUM                                                                         0x0629
919 #define regSDMA1_UCODE_CHECKSUM_BASE_IDX                                                                0
920 #define regSDMA1_FREEZE                                                                                 0x062b
921 #define regSDMA1_FREEZE_BASE_IDX                                                                        0
922 #define regSDMA1_PROCESS_QUANTUM0                                                                       0x062c
923 #define regSDMA1_PROCESS_QUANTUM0_BASE_IDX                                                              0
924 #define regSDMA1_PROCESS_QUANTUM1                                                                       0x062d
925 #define regSDMA1_PROCESS_QUANTUM1_BASE_IDX                                                              0
926 #define regSDMA1_WATCHDOG_CNTL                                                                          0x062e
927 #define regSDMA1_WATCHDOG_CNTL_BASE_IDX                                                                 0
928 #define regSDMA1_QUEUE_STATUS0                                                                          0x062f
929 #define regSDMA1_QUEUE_STATUS0_BASE_IDX                                                                 0
930 #define regSDMA1_EDC_CONFIG                                                                             0x0632
931 #define regSDMA1_EDC_CONFIG_BASE_IDX                                                                    0
932 #define regSDMA1_BA_THRESHOLD                                                                           0x0633
933 #define regSDMA1_BA_THRESHOLD_BASE_IDX                                                                  0
934 #define regSDMA1_ID                                                                                     0x0634
935 #define regSDMA1_ID_BASE_IDX                                                                            0
936 #define regSDMA1_VERSION                                                                                0x0635
937 #define regSDMA1_VERSION_BASE_IDX                                                                       0
938 #define regSDMA1_EDC_COUNTER                                                                            0x0636
939 #define regSDMA1_EDC_COUNTER_BASE_IDX                                                                   0
940 #define regSDMA1_EDC_COUNTER_CLEAR                                                                      0x0637
941 #define regSDMA1_EDC_COUNTER_CLEAR_BASE_IDX                                                             0
942 #define regSDMA1_STATUS2_REG                                                                            0x0638
943 #define regSDMA1_STATUS2_REG_BASE_IDX                                                                   0
944 #define regSDMA1_ATOMIC_CNTL                                                                            0x0639
945 #define regSDMA1_ATOMIC_CNTL_BASE_IDX                                                                   0
946 #define regSDMA1_ATOMIC_PREOP_LO                                                                        0x063a
947 #define regSDMA1_ATOMIC_PREOP_LO_BASE_IDX                                                               0
948 #define regSDMA1_ATOMIC_PREOP_HI                                                                        0x063b
949 #define regSDMA1_ATOMIC_PREOP_HI_BASE_IDX                                                               0
950 #define regSDMA1_UTCL1_CNTL                                                                             0x063c
951 #define regSDMA1_UTCL1_CNTL_BASE_IDX                                                                    0
952 #define regSDMA1_UTCL1_WATERMK                                                                          0x063d
953 #define regSDMA1_UTCL1_WATERMK_BASE_IDX                                                                 0
954 #define regSDMA1_UTCL1_TIMEOUT                                                                          0x063e
955 #define regSDMA1_UTCL1_TIMEOUT_BASE_IDX                                                                 0
956 #define regSDMA1_UTCL1_PAGE                                                                             0x063f
957 #define regSDMA1_UTCL1_PAGE_BASE_IDX                                                                    0
958 #define regSDMA1_UTCL1_RD_STATUS                                                                        0x0640
959 #define regSDMA1_UTCL1_RD_STATUS_BASE_IDX                                                               0
960 #define regSDMA1_UTCL1_WR_STATUS                                                                        0x0641
961 #define regSDMA1_UTCL1_WR_STATUS_BASE_IDX                                                               0
962 #define regSDMA1_UTCL1_INV0                                                                             0x0642
963 #define regSDMA1_UTCL1_INV0_BASE_IDX                                                                    0
964 #define regSDMA1_UTCL1_INV1                                                                             0x0643
965 #define regSDMA1_UTCL1_INV1_BASE_IDX                                                                    0
966 #define regSDMA1_UTCL1_INV2                                                                             0x0644
967 #define regSDMA1_UTCL1_INV2_BASE_IDX                                                                    0
968 #define regSDMA1_UTCL1_RD_XNACK0                                                                        0x0645
969 #define regSDMA1_UTCL1_RD_XNACK0_BASE_IDX                                                               0
970 #define regSDMA1_UTCL1_RD_XNACK1                                                                        0x0646
971 #define regSDMA1_UTCL1_RD_XNACK1_BASE_IDX                                                               0
972 #define regSDMA1_UTCL1_WR_XNACK0                                                                        0x0647
973 #define regSDMA1_UTCL1_WR_XNACK0_BASE_IDX                                                               0
974 #define regSDMA1_UTCL1_WR_XNACK1                                                                        0x0648
975 #define regSDMA1_UTCL1_WR_XNACK1_BASE_IDX                                                               0
976 #define regSDMA1_RELAX_ORDERING_LUT                                                                     0x064a
977 #define regSDMA1_RELAX_ORDERING_LUT_BASE_IDX                                                            0
978 #define regSDMA1_CHICKEN_BITS_2                                                                         0x064b
979 #define regSDMA1_CHICKEN_BITS_2_BASE_IDX                                                                0
980 #define regSDMA1_STATUS3_REG                                                                            0x064c
981 #define regSDMA1_STATUS3_REG_BASE_IDX                                                                   0
982 #define regSDMA1_PHYSICAL_ADDR_LO                                                                       0x064d
983 #define regSDMA1_PHYSICAL_ADDR_LO_BASE_IDX                                                              0
984 #define regSDMA1_PHYSICAL_ADDR_HI                                                                       0x064e
985 #define regSDMA1_PHYSICAL_ADDR_HI_BASE_IDX                                                              0
986 #define regSDMA1_GLOBAL_QUANTUM                                                                         0x064f
987 #define regSDMA1_GLOBAL_QUANTUM_BASE_IDX                                                                0
988 #define regSDMA1_ERROR_LOG                                                                              0x0650
989 #define regSDMA1_ERROR_LOG_BASE_IDX                                                                     0
990 #define regSDMA1_PUB_DUMMY_REG0                                                                         0x0651
991 #define regSDMA1_PUB_DUMMY_REG0_BASE_IDX                                                                0
992 #define regSDMA1_PUB_DUMMY_REG1                                                                         0x0652
993 #define regSDMA1_PUB_DUMMY_REG1_BASE_IDX                                                                0
994 #define regSDMA1_PUB_DUMMY_REG2                                                                         0x0653
995 #define regSDMA1_PUB_DUMMY_REG2_BASE_IDX                                                                0
996 #define regSDMA1_PUB_DUMMY_REG3                                                                         0x0654
997 #define regSDMA1_PUB_DUMMY_REG3_BASE_IDX                                                                0
998 #define regSDMA1_F32_COUNTER                                                                            0x0655
999 #define regSDMA1_F32_COUNTER_BASE_IDX                                                                   0
1000 #define regSDMA1_CRD_CNTL                                                                               0x065b
1001 #define regSDMA1_CRD_CNTL_BASE_IDX                                                                      0
1002 #define regSDMA1_RLC_CGCG_CTRL                                                                          0x065c
1003 #define regSDMA1_RLC_CGCG_CTRL_BASE_IDX                                                                 0
1004 #define regSDMA1_AQL_STATUS                                                                             0x065f
1005 #define regSDMA1_AQL_STATUS_BASE_IDX                                                                    0
1006 #define regSDMA1_EA_DBIT_ADDR_DATA                                                                      0x0660
1007 #define regSDMA1_EA_DBIT_ADDR_DATA_BASE_IDX                                                             0
1008 #define regSDMA1_EA_DBIT_ADDR_INDEX                                                                     0x0661
1009 #define regSDMA1_EA_DBIT_ADDR_INDEX_BASE_IDX                                                            0
1010 #define regSDMA1_TLBI_GCR_CNTL                                                                          0x0662
1011 #define regSDMA1_TLBI_GCR_CNTL_BASE_IDX                                                                 0
1012 #define regSDMA1_TILING_CONFIG                                                                          0x0663
1013 #define regSDMA1_TILING_CONFIG_BASE_IDX                                                                 0
1014 #define regSDMA1_INT_STATUS                                                                             0x0670
1015 #define regSDMA1_INT_STATUS_BASE_IDX                                                                    0
1016 #define regSDMA1_HOLE_ADDR_LO                                                                           0x0672
1017 #define regSDMA1_HOLE_ADDR_LO_BASE_IDX                                                                  0
1018 #define regSDMA1_HOLE_ADDR_HI                                                                           0x0673
1019 #define regSDMA1_HOLE_ADDR_HI_BASE_IDX                                                                  0
1020 #define regSDMA1_CLOCK_GATING_STATUS                                                                    0x0675
1021 #define regSDMA1_CLOCK_GATING_STATUS_BASE_IDX                                                           0
1022 #define regSDMA1_STATUS4_REG                                                                            0x0676
1023 #define regSDMA1_STATUS4_REG_BASE_IDX                                                                   0
1024 #define regSDMA1_SCRATCH_RAM_DATA                                                                       0x0677
1025 #define regSDMA1_SCRATCH_RAM_DATA_BASE_IDX                                                              0
1026 #define regSDMA1_SCRATCH_RAM_ADDR                                                                       0x0678
1027 #define regSDMA1_SCRATCH_RAM_ADDR_BASE_IDX                                                              0
1028 #define regSDMA1_TIMESTAMP_CNTL                                                                         0x0679
1029 #define regSDMA1_TIMESTAMP_CNTL_BASE_IDX                                                                0
1030 #define regSDMA1_STATUS5_REG                                                                            0x067a
1031 #define regSDMA1_STATUS5_REG_BASE_IDX                                                                   0
1032 #define regSDMA1_QUEUE_RESET_REQ                                                                        0x067b
1033 #define regSDMA1_QUEUE_RESET_REQ_BASE_IDX                                                               0
1034 #define regSDMA1_STATUS6_REG                                                                            0x067c
1035 #define regSDMA1_STATUS6_REG_BASE_IDX                                                                   0
1036 #define regSDMA1_UCODE1_CHECKSUM                                                                        0x067d
1037 #define regSDMA1_UCODE1_CHECKSUM_BASE_IDX                                                               0
1038 #define regSDMA1_CE_CTRL                                                                                0x067e
1039 #define regSDMA1_CE_CTRL_BASE_IDX                                                                       0
1040 #define regSDMA1_FED_STATUS                                                                             0x067f
1041 #define regSDMA1_FED_STATUS_BASE_IDX                                                                    0
1042 #define regSDMA1_QUEUE0_RB_CNTL                                                                         0x0680
1043 #define regSDMA1_QUEUE0_RB_CNTL_BASE_IDX                                                                0
1044 #define regSDMA1_QUEUE0_RB_BASE                                                                         0x0681
1045 #define regSDMA1_QUEUE0_RB_BASE_BASE_IDX                                                                0
1046 #define regSDMA1_QUEUE0_RB_BASE_HI                                                                      0x0682
1047 #define regSDMA1_QUEUE0_RB_BASE_HI_BASE_IDX                                                             0
1048 #define regSDMA1_QUEUE0_RB_RPTR                                                                         0x0683
1049 #define regSDMA1_QUEUE0_RB_RPTR_BASE_IDX                                                                0
1050 #define regSDMA1_QUEUE0_RB_RPTR_HI                                                                      0x0684
1051 #define regSDMA1_QUEUE0_RB_RPTR_HI_BASE_IDX                                                             0
1052 #define regSDMA1_QUEUE0_RB_WPTR                                                                         0x0685
1053 #define regSDMA1_QUEUE0_RB_WPTR_BASE_IDX                                                                0
1054 #define regSDMA1_QUEUE0_RB_WPTR_HI                                                                      0x0686
1055 #define regSDMA1_QUEUE0_RB_WPTR_HI_BASE_IDX                                                             0
1056 #define regSDMA1_QUEUE0_RB_RPTR_ADDR_HI                                                                 0x0688
1057 #define regSDMA1_QUEUE0_RB_RPTR_ADDR_HI_BASE_IDX                                                        0
1058 #define regSDMA1_QUEUE0_RB_RPTR_ADDR_LO                                                                 0x0689
1059 #define regSDMA1_QUEUE0_RB_RPTR_ADDR_LO_BASE_IDX                                                        0
1060 #define regSDMA1_QUEUE0_IB_CNTL                                                                         0x068a
1061 #define regSDMA1_QUEUE0_IB_CNTL_BASE_IDX                                                                0
1062 #define regSDMA1_QUEUE0_IB_RPTR                                                                         0x068b
1063 #define regSDMA1_QUEUE0_IB_RPTR_BASE_IDX                                                                0
1064 #define regSDMA1_QUEUE0_IB_OFFSET                                                                       0x068c
1065 #define regSDMA1_QUEUE0_IB_OFFSET_BASE_IDX                                                              0
1066 #define regSDMA1_QUEUE0_IB_BASE_LO                                                                      0x068d
1067 #define regSDMA1_QUEUE0_IB_BASE_LO_BASE_IDX                                                             0
1068 #define regSDMA1_QUEUE0_IB_BASE_HI                                                                      0x068e
1069 #define regSDMA1_QUEUE0_IB_BASE_HI_BASE_IDX                                                             0
1070 #define regSDMA1_QUEUE0_IB_SIZE                                                                         0x068f
1071 #define regSDMA1_QUEUE0_IB_SIZE_BASE_IDX                                                                0
1072 #define regSDMA1_QUEUE0_SKIP_CNTL                                                                       0x0690
1073 #define regSDMA1_QUEUE0_SKIP_CNTL_BASE_IDX                                                              0
1074 #define regSDMA1_QUEUE0_CONTEXT_STATUS                                                                  0x0691
1075 #define regSDMA1_QUEUE0_CONTEXT_STATUS_BASE_IDX                                                         0
1076 #define regSDMA1_QUEUE0_DOORBELL                                                                        0x0692
1077 #define regSDMA1_QUEUE0_DOORBELL_BASE_IDX                                                               0
1078 #define regSDMA1_QUEUE0_DOORBELL_LOG                                                                    0x06a9
1079 #define regSDMA1_QUEUE0_DOORBELL_LOG_BASE_IDX                                                           0
1080 #define regSDMA1_QUEUE0_DOORBELL_OFFSET                                                                 0x06ab
1081 #define regSDMA1_QUEUE0_DOORBELL_OFFSET_BASE_IDX                                                        0
1082 #define regSDMA1_QUEUE0_CSA_ADDR_LO                                                                     0x06ac
1083 #define regSDMA1_QUEUE0_CSA_ADDR_LO_BASE_IDX                                                            0
1084 #define regSDMA1_QUEUE0_CSA_ADDR_HI                                                                     0x06ad
1085 #define regSDMA1_QUEUE0_CSA_ADDR_HI_BASE_IDX                                                            0
1086 #define regSDMA1_QUEUE0_SCHEDULE_CNTL                                                                   0x06ae
1087 #define regSDMA1_QUEUE0_SCHEDULE_CNTL_BASE_IDX                                                          0
1088 #define regSDMA1_QUEUE0_IB_SUB_REMAIN                                                                   0x06af
1089 #define regSDMA1_QUEUE0_IB_SUB_REMAIN_BASE_IDX                                                          0
1090 #define regSDMA1_QUEUE0_PREEMPT                                                                         0x06b0
1091 #define regSDMA1_QUEUE0_PREEMPT_BASE_IDX                                                                0
1092 #define regSDMA1_QUEUE0_DUMMY_REG                                                                       0x06b1
1093 #define regSDMA1_QUEUE0_DUMMY_REG_BASE_IDX                                                              0
1094 #define regSDMA1_QUEUE0_RB_WPTR_POLL_ADDR_HI                                                            0x06b2
1095 #define regSDMA1_QUEUE0_RB_WPTR_POLL_ADDR_HI_BASE_IDX                                                   0
1096 #define regSDMA1_QUEUE0_RB_WPTR_POLL_ADDR_LO                                                            0x06b3
1097 #define regSDMA1_QUEUE0_RB_WPTR_POLL_ADDR_LO_BASE_IDX                                                   0
1098 #define regSDMA1_QUEUE0_RB_AQL_CNTL                                                                     0x06b4
1099 #define regSDMA1_QUEUE0_RB_AQL_CNTL_BASE_IDX                                                            0
1100 #define regSDMA1_QUEUE0_MINOR_PTR_UPDATE                                                                0x06b5
1101 #define regSDMA1_QUEUE0_MINOR_PTR_UPDATE_BASE_IDX                                                       0
1102 #define regSDMA1_QUEUE0_RB_PREEMPT                                                                      0x06b6
1103 #define regSDMA1_QUEUE0_RB_PREEMPT_BASE_IDX                                                             0
1104 #define regSDMA1_QUEUE0_MIDCMD_DATA0                                                                    0x06c0
1105 #define regSDMA1_QUEUE0_MIDCMD_DATA0_BASE_IDX                                                           0
1106 #define regSDMA1_QUEUE0_MIDCMD_DATA1                                                                    0x06c1
1107 #define regSDMA1_QUEUE0_MIDCMD_DATA1_BASE_IDX                                                           0
1108 #define regSDMA1_QUEUE0_MIDCMD_DATA2                                                                    0x06c2
1109 #define regSDMA1_QUEUE0_MIDCMD_DATA2_BASE_IDX                                                           0
1110 #define regSDMA1_QUEUE0_MIDCMD_DATA3                                                                    0x06c3
1111 #define regSDMA1_QUEUE0_MIDCMD_DATA3_BASE_IDX                                                           0
1112 #define regSDMA1_QUEUE0_MIDCMD_DATA4                                                                    0x06c4
1113 #define regSDMA1_QUEUE0_MIDCMD_DATA4_BASE_IDX                                                           0
1114 #define regSDMA1_QUEUE0_MIDCMD_DATA5                                                                    0x06c5
1115 #define regSDMA1_QUEUE0_MIDCMD_DATA5_BASE_IDX                                                           0
1116 #define regSDMA1_QUEUE0_MIDCMD_DATA6                                                                    0x06c6
1117 #define regSDMA1_QUEUE0_MIDCMD_DATA6_BASE_IDX                                                           0
1118 #define regSDMA1_QUEUE0_MIDCMD_DATA7                                                                    0x06c7
1119 #define regSDMA1_QUEUE0_MIDCMD_DATA7_BASE_IDX                                                           0
1120 #define regSDMA1_QUEUE0_MIDCMD_DATA8                                                                    0x06c8
1121 #define regSDMA1_QUEUE0_MIDCMD_DATA8_BASE_IDX                                                           0
1122 #define regSDMA1_QUEUE0_MIDCMD_DATA9                                                                    0x06c9
1123 #define regSDMA1_QUEUE0_MIDCMD_DATA9_BASE_IDX                                                           0
1124 #define regSDMA1_QUEUE0_MIDCMD_DATA10                                                                   0x06ca
1125 #define regSDMA1_QUEUE0_MIDCMD_DATA10_BASE_IDX                                                          0
1126 #define regSDMA1_QUEUE0_MIDCMD_CNTL                                                                     0x06cb
1127 #define regSDMA1_QUEUE0_MIDCMD_CNTL_BASE_IDX                                                            0
1128 #define regSDMA1_QUEUE1_RB_CNTL                                                                         0x06d8
1129 #define regSDMA1_QUEUE1_RB_CNTL_BASE_IDX                                                                0
1130 #define regSDMA1_QUEUE1_RB_BASE                                                                         0x06d9
1131 #define regSDMA1_QUEUE1_RB_BASE_BASE_IDX                                                                0
1132 #define regSDMA1_QUEUE1_RB_BASE_HI                                                                      0x06da
1133 #define regSDMA1_QUEUE1_RB_BASE_HI_BASE_IDX                                                             0
1134 #define regSDMA1_QUEUE1_RB_RPTR                                                                         0x06db
1135 #define regSDMA1_QUEUE1_RB_RPTR_BASE_IDX                                                                0
1136 #define regSDMA1_QUEUE1_RB_RPTR_HI                                                                      0x06dc
1137 #define regSDMA1_QUEUE1_RB_RPTR_HI_BASE_IDX                                                             0
1138 #define regSDMA1_QUEUE1_RB_WPTR                                                                         0x06dd
1139 #define regSDMA1_QUEUE1_RB_WPTR_BASE_IDX                                                                0
1140 #define regSDMA1_QUEUE1_RB_WPTR_HI                                                                      0x06de
1141 #define regSDMA1_QUEUE1_RB_WPTR_HI_BASE_IDX                                                             0
1142 #define regSDMA1_QUEUE1_RB_RPTR_ADDR_HI                                                                 0x06e0
1143 #define regSDMA1_QUEUE1_RB_RPTR_ADDR_HI_BASE_IDX                                                        0
1144 #define regSDMA1_QUEUE1_RB_RPTR_ADDR_LO                                                                 0x06e1
1145 #define regSDMA1_QUEUE1_RB_RPTR_ADDR_LO_BASE_IDX                                                        0
1146 #define regSDMA1_QUEUE1_IB_CNTL                                                                         0x06e2
1147 #define regSDMA1_QUEUE1_IB_CNTL_BASE_IDX                                                                0
1148 #define regSDMA1_QUEUE1_IB_RPTR                                                                         0x06e3
1149 #define regSDMA1_QUEUE1_IB_RPTR_BASE_IDX                                                                0
1150 #define regSDMA1_QUEUE1_IB_OFFSET                                                                       0x06e4
1151 #define regSDMA1_QUEUE1_IB_OFFSET_BASE_IDX                                                              0
1152 #define regSDMA1_QUEUE1_IB_BASE_LO                                                                      0x06e5
1153 #define regSDMA1_QUEUE1_IB_BASE_LO_BASE_IDX                                                             0
1154 #define regSDMA1_QUEUE1_IB_BASE_HI                                                                      0x06e6
1155 #define regSDMA1_QUEUE1_IB_BASE_HI_BASE_IDX                                                             0
1156 #define regSDMA1_QUEUE1_IB_SIZE                                                                         0x06e7
1157 #define regSDMA1_QUEUE1_IB_SIZE_BASE_IDX                                                                0
1158 #define regSDMA1_QUEUE1_SKIP_CNTL                                                                       0x06e8
1159 #define regSDMA1_QUEUE1_SKIP_CNTL_BASE_IDX                                                              0
1160 #define regSDMA1_QUEUE1_CONTEXT_STATUS                                                                  0x06e9
1161 #define regSDMA1_QUEUE1_CONTEXT_STATUS_BASE_IDX                                                         0
1162 #define regSDMA1_QUEUE1_DOORBELL                                                                        0x06ea
1163 #define regSDMA1_QUEUE1_DOORBELL_BASE_IDX                                                               0
1164 #define regSDMA1_QUEUE1_DOORBELL_LOG                                                                    0x0701
1165 #define regSDMA1_QUEUE1_DOORBELL_LOG_BASE_IDX                                                           0
1166 #define regSDMA1_QUEUE1_DOORBELL_OFFSET                                                                 0x0703
1167 #define regSDMA1_QUEUE1_DOORBELL_OFFSET_BASE_IDX                                                        0
1168 #define regSDMA1_QUEUE1_CSA_ADDR_LO                                                                     0x0704
1169 #define regSDMA1_QUEUE1_CSA_ADDR_LO_BASE_IDX                                                            0
1170 #define regSDMA1_QUEUE1_CSA_ADDR_HI                                                                     0x0705
1171 #define regSDMA1_QUEUE1_CSA_ADDR_HI_BASE_IDX                                                            0
1172 #define regSDMA1_QUEUE1_SCHEDULE_CNTL                                                                   0x0706
1173 #define regSDMA1_QUEUE1_SCHEDULE_CNTL_BASE_IDX                                                          0
1174 #define regSDMA1_QUEUE1_IB_SUB_REMAIN                                                                   0x0707
1175 #define regSDMA1_QUEUE1_IB_SUB_REMAIN_BASE_IDX                                                          0
1176 #define regSDMA1_QUEUE1_PREEMPT                                                                         0x0708
1177 #define regSDMA1_QUEUE1_PREEMPT_BASE_IDX                                                                0
1178 #define regSDMA1_QUEUE1_DUMMY_REG                                                                       0x0709
1179 #define regSDMA1_QUEUE1_DUMMY_REG_BASE_IDX                                                              0
1180 #define regSDMA1_QUEUE1_RB_WPTR_POLL_ADDR_HI                                                            0x070a
1181 #define regSDMA1_QUEUE1_RB_WPTR_POLL_ADDR_HI_BASE_IDX                                                   0
1182 #define regSDMA1_QUEUE1_RB_WPTR_POLL_ADDR_LO                                                            0x070b
1183 #define regSDMA1_QUEUE1_RB_WPTR_POLL_ADDR_LO_BASE_IDX                                                   0
1184 #define regSDMA1_QUEUE1_RB_AQL_CNTL                                                                     0x070c
1185 #define regSDMA1_QUEUE1_RB_AQL_CNTL_BASE_IDX                                                            0
1186 #define regSDMA1_QUEUE1_MINOR_PTR_UPDATE                                                                0x070d
1187 #define regSDMA1_QUEUE1_MINOR_PTR_UPDATE_BASE_IDX                                                       0
1188 #define regSDMA1_QUEUE1_RB_PREEMPT                                                                      0x070e
1189 #define regSDMA1_QUEUE1_RB_PREEMPT_BASE_IDX                                                             0
1190 #define regSDMA1_QUEUE1_MIDCMD_DATA0                                                                    0x0718
1191 #define regSDMA1_QUEUE1_MIDCMD_DATA0_BASE_IDX                                                           0
1192 #define regSDMA1_QUEUE1_MIDCMD_DATA1                                                                    0x0719
1193 #define regSDMA1_QUEUE1_MIDCMD_DATA1_BASE_IDX                                                           0
1194 #define regSDMA1_QUEUE1_MIDCMD_DATA2                                                                    0x071a
1195 #define regSDMA1_QUEUE1_MIDCMD_DATA2_BASE_IDX                                                           0
1196 #define regSDMA1_QUEUE1_MIDCMD_DATA3                                                                    0x071b
1197 #define regSDMA1_QUEUE1_MIDCMD_DATA3_BASE_IDX                                                           0
1198 #define regSDMA1_QUEUE1_MIDCMD_DATA4                                                                    0x071c
1199 #define regSDMA1_QUEUE1_MIDCMD_DATA4_BASE_IDX                                                           0
1200 #define regSDMA1_QUEUE1_MIDCMD_DATA5                                                                    0x071d
1201 #define regSDMA1_QUEUE1_MIDCMD_DATA5_BASE_IDX                                                           0
1202 #define regSDMA1_QUEUE1_MIDCMD_DATA6                                                                    0x071e
1203 #define regSDMA1_QUEUE1_MIDCMD_DATA6_BASE_IDX                                                           0
1204 #define regSDMA1_QUEUE1_MIDCMD_DATA7                                                                    0x071f
1205 #define regSDMA1_QUEUE1_MIDCMD_DATA7_BASE_IDX                                                           0
1206 #define regSDMA1_QUEUE1_MIDCMD_DATA8                                                                    0x0720
1207 #define regSDMA1_QUEUE1_MIDCMD_DATA8_BASE_IDX                                                           0
1208 #define regSDMA1_QUEUE1_MIDCMD_DATA9                                                                    0x0721
1209 #define regSDMA1_QUEUE1_MIDCMD_DATA9_BASE_IDX                                                           0
1210 #define regSDMA1_QUEUE1_MIDCMD_DATA10                                                                   0x0722
1211 #define regSDMA1_QUEUE1_MIDCMD_DATA10_BASE_IDX                                                          0
1212 #define regSDMA1_QUEUE1_MIDCMD_CNTL                                                                     0x0723
1213 #define regSDMA1_QUEUE1_MIDCMD_CNTL_BASE_IDX                                                            0
1214 #define regSDMA1_QUEUE2_RB_CNTL                                                                         0x0730
1215 #define regSDMA1_QUEUE2_RB_CNTL_BASE_IDX                                                                0
1216 #define regSDMA1_QUEUE2_RB_BASE                                                                         0x0731
1217 #define regSDMA1_QUEUE2_RB_BASE_BASE_IDX                                                                0
1218 #define regSDMA1_QUEUE2_RB_BASE_HI                                                                      0x0732
1219 #define regSDMA1_QUEUE2_RB_BASE_HI_BASE_IDX                                                             0
1220 #define regSDMA1_QUEUE2_RB_RPTR                                                                         0x0733
1221 #define regSDMA1_QUEUE2_RB_RPTR_BASE_IDX                                                                0
1222 #define regSDMA1_QUEUE2_RB_RPTR_HI                                                                      0x0734
1223 #define regSDMA1_QUEUE2_RB_RPTR_HI_BASE_IDX                                                             0
1224 #define regSDMA1_QUEUE2_RB_WPTR                                                                         0x0735
1225 #define regSDMA1_QUEUE2_RB_WPTR_BASE_IDX                                                                0
1226 #define regSDMA1_QUEUE2_RB_WPTR_HI                                                                      0x0736
1227 #define regSDMA1_QUEUE2_RB_WPTR_HI_BASE_IDX                                                             0
1228 #define regSDMA1_QUEUE2_RB_RPTR_ADDR_HI                                                                 0x0738
1229 #define regSDMA1_QUEUE2_RB_RPTR_ADDR_HI_BASE_IDX                                                        0
1230 #define regSDMA1_QUEUE2_RB_RPTR_ADDR_LO                                                                 0x0739
1231 #define regSDMA1_QUEUE2_RB_RPTR_ADDR_LO_BASE_IDX                                                        0
1232 #define regSDMA1_QUEUE2_IB_CNTL                                                                         0x073a
1233 #define regSDMA1_QUEUE2_IB_CNTL_BASE_IDX                                                                0
1234 #define regSDMA1_QUEUE2_IB_RPTR                                                                         0x073b
1235 #define regSDMA1_QUEUE2_IB_RPTR_BASE_IDX                                                                0
1236 #define regSDMA1_QUEUE2_IB_OFFSET                                                                       0x073c
1237 #define regSDMA1_QUEUE2_IB_OFFSET_BASE_IDX                                                              0
1238 #define regSDMA1_QUEUE2_IB_BASE_LO                                                                      0x073d
1239 #define regSDMA1_QUEUE2_IB_BASE_LO_BASE_IDX                                                             0
1240 #define regSDMA1_QUEUE2_IB_BASE_HI                                                                      0x073e
1241 #define regSDMA1_QUEUE2_IB_BASE_HI_BASE_IDX                                                             0
1242 #define regSDMA1_QUEUE2_IB_SIZE                                                                         0x073f
1243 #define regSDMA1_QUEUE2_IB_SIZE_BASE_IDX                                                                0
1244 #define regSDMA1_QUEUE2_SKIP_CNTL                                                                       0x0740
1245 #define regSDMA1_QUEUE2_SKIP_CNTL_BASE_IDX                                                              0
1246 #define regSDMA1_QUEUE2_CONTEXT_STATUS                                                                  0x0741
1247 #define regSDMA1_QUEUE2_CONTEXT_STATUS_BASE_IDX                                                         0
1248 #define regSDMA1_QUEUE2_DOORBELL                                                                        0x0742
1249 #define regSDMA1_QUEUE2_DOORBELL_BASE_IDX                                                               0
1250 #define regSDMA1_QUEUE2_DOORBELL_LOG                                                                    0x0759
1251 #define regSDMA1_QUEUE2_DOORBELL_LOG_BASE_IDX                                                           0
1252 #define regSDMA1_QUEUE2_DOORBELL_OFFSET                                                                 0x075b
1253 #define regSDMA1_QUEUE2_DOORBELL_OFFSET_BASE_IDX                                                        0
1254 #define regSDMA1_QUEUE2_CSA_ADDR_LO                                                                     0x075c
1255 #define regSDMA1_QUEUE2_CSA_ADDR_LO_BASE_IDX                                                            0
1256 #define regSDMA1_QUEUE2_CSA_ADDR_HI                                                                     0x075d
1257 #define regSDMA1_QUEUE2_CSA_ADDR_HI_BASE_IDX                                                            0
1258 #define regSDMA1_QUEUE2_SCHEDULE_CNTL                                                                   0x075e
1259 #define regSDMA1_QUEUE2_SCHEDULE_CNTL_BASE_IDX                                                          0
1260 #define regSDMA1_QUEUE2_IB_SUB_REMAIN                                                                   0x075f
1261 #define regSDMA1_QUEUE2_IB_SUB_REMAIN_BASE_IDX                                                          0
1262 #define regSDMA1_QUEUE2_PREEMPT                                                                         0x0760
1263 #define regSDMA1_QUEUE2_PREEMPT_BASE_IDX                                                                0
1264 #define regSDMA1_QUEUE2_DUMMY_REG                                                                       0x0761
1265 #define regSDMA1_QUEUE2_DUMMY_REG_BASE_IDX                                                              0
1266 #define regSDMA1_QUEUE2_RB_WPTR_POLL_ADDR_HI                                                            0x0762
1267 #define regSDMA1_QUEUE2_RB_WPTR_POLL_ADDR_HI_BASE_IDX                                                   0
1268 #define regSDMA1_QUEUE2_RB_WPTR_POLL_ADDR_LO                                                            0x0763
1269 #define regSDMA1_QUEUE2_RB_WPTR_POLL_ADDR_LO_BASE_IDX                                                   0
1270 #define regSDMA1_QUEUE2_RB_AQL_CNTL                                                                     0x0764
1271 #define regSDMA1_QUEUE2_RB_AQL_CNTL_BASE_IDX                                                            0
1272 #define regSDMA1_QUEUE2_MINOR_PTR_UPDATE                                                                0x0765
1273 #define regSDMA1_QUEUE2_MINOR_PTR_UPDATE_BASE_IDX                                                       0
1274 #define regSDMA1_QUEUE2_RB_PREEMPT                                                                      0x0766
1275 #define regSDMA1_QUEUE2_RB_PREEMPT_BASE_IDX                                                             0
1276 #define regSDMA1_QUEUE2_MIDCMD_DATA0                                                                    0x0770
1277 #define regSDMA1_QUEUE2_MIDCMD_DATA0_BASE_IDX                                                           0
1278 #define regSDMA1_QUEUE2_MIDCMD_DATA1                                                                    0x0771
1279 #define regSDMA1_QUEUE2_MIDCMD_DATA1_BASE_IDX                                                           0
1280 #define regSDMA1_QUEUE2_MIDCMD_DATA2                                                                    0x0772
1281 #define regSDMA1_QUEUE2_MIDCMD_DATA2_BASE_IDX                                                           0
1282 #define regSDMA1_QUEUE2_MIDCMD_DATA3                                                                    0x0773
1283 #define regSDMA1_QUEUE2_MIDCMD_DATA3_BASE_IDX                                                           0
1284 #define regSDMA1_QUEUE2_MIDCMD_DATA4                                                                    0x0774
1285 #define regSDMA1_QUEUE2_MIDCMD_DATA4_BASE_IDX                                                           0
1286 #define regSDMA1_QUEUE2_MIDCMD_DATA5                                                                    0x0775
1287 #define regSDMA1_QUEUE2_MIDCMD_DATA5_BASE_IDX                                                           0
1288 #define regSDMA1_QUEUE2_MIDCMD_DATA6                                                                    0x0776
1289 #define regSDMA1_QUEUE2_MIDCMD_DATA6_BASE_IDX                                                           0
1290 #define regSDMA1_QUEUE2_MIDCMD_DATA7                                                                    0x0777
1291 #define regSDMA1_QUEUE2_MIDCMD_DATA7_BASE_IDX                                                           0
1292 #define regSDMA1_QUEUE2_MIDCMD_DATA8                                                                    0x0778
1293 #define regSDMA1_QUEUE2_MIDCMD_DATA8_BASE_IDX                                                           0
1294 #define regSDMA1_QUEUE2_MIDCMD_DATA9                                                                    0x0779
1295 #define regSDMA1_QUEUE2_MIDCMD_DATA9_BASE_IDX                                                           0
1296 #define regSDMA1_QUEUE2_MIDCMD_DATA10                                                                   0x077a
1297 #define regSDMA1_QUEUE2_MIDCMD_DATA10_BASE_IDX                                                          0
1298 #define regSDMA1_QUEUE2_MIDCMD_CNTL                                                                     0x077b
1299 #define regSDMA1_QUEUE2_MIDCMD_CNTL_BASE_IDX                                                            0
1300 #define regSDMA1_QUEUE3_RB_CNTL                                                                         0x0788
1301 #define regSDMA1_QUEUE3_RB_CNTL_BASE_IDX                                                                0
1302 #define regSDMA1_QUEUE3_RB_BASE                                                                         0x0789
1303 #define regSDMA1_QUEUE3_RB_BASE_BASE_IDX                                                                0
1304 #define regSDMA1_QUEUE3_RB_BASE_HI                                                                      0x078a
1305 #define regSDMA1_QUEUE3_RB_BASE_HI_BASE_IDX                                                             0
1306 #define regSDMA1_QUEUE3_RB_RPTR                                                                         0x078b
1307 #define regSDMA1_QUEUE3_RB_RPTR_BASE_IDX                                                                0
1308 #define regSDMA1_QUEUE3_RB_RPTR_HI                                                                      0x078c
1309 #define regSDMA1_QUEUE3_RB_RPTR_HI_BASE_IDX                                                             0
1310 #define regSDMA1_QUEUE3_RB_WPTR                                                                         0x078d
1311 #define regSDMA1_QUEUE3_RB_WPTR_BASE_IDX                                                                0
1312 #define regSDMA1_QUEUE3_RB_WPTR_HI                                                                      0x078e
1313 #define regSDMA1_QUEUE3_RB_WPTR_HI_BASE_IDX                                                             0
1314 #define regSDMA1_QUEUE3_RB_RPTR_ADDR_HI                                                                 0x0790
1315 #define regSDMA1_QUEUE3_RB_RPTR_ADDR_HI_BASE_IDX                                                        0
1316 #define regSDMA1_QUEUE3_RB_RPTR_ADDR_LO                                                                 0x0791
1317 #define regSDMA1_QUEUE3_RB_RPTR_ADDR_LO_BASE_IDX                                                        0
1318 #define regSDMA1_QUEUE3_IB_CNTL                                                                         0x0792
1319 #define regSDMA1_QUEUE3_IB_CNTL_BASE_IDX                                                                0
1320 #define regSDMA1_QUEUE3_IB_RPTR                                                                         0x0793
1321 #define regSDMA1_QUEUE3_IB_RPTR_BASE_IDX                                                                0
1322 #define regSDMA1_QUEUE3_IB_OFFSET                                                                       0x0794
1323 #define regSDMA1_QUEUE3_IB_OFFSET_BASE_IDX                                                              0
1324 #define regSDMA1_QUEUE3_IB_BASE_LO                                                                      0x0795
1325 #define regSDMA1_QUEUE3_IB_BASE_LO_BASE_IDX                                                             0
1326 #define regSDMA1_QUEUE3_IB_BASE_HI                                                                      0x0796
1327 #define regSDMA1_QUEUE3_IB_BASE_HI_BASE_IDX                                                             0
1328 #define regSDMA1_QUEUE3_IB_SIZE                                                                         0x0797
1329 #define regSDMA1_QUEUE3_IB_SIZE_BASE_IDX                                                                0
1330 #define regSDMA1_QUEUE3_SKIP_CNTL                                                                       0x0798
1331 #define regSDMA1_QUEUE3_SKIP_CNTL_BASE_IDX                                                              0
1332 #define regSDMA1_QUEUE3_CONTEXT_STATUS                                                                  0x0799
1333 #define regSDMA1_QUEUE3_CONTEXT_STATUS_BASE_IDX                                                         0
1334 #define regSDMA1_QUEUE3_DOORBELL                                                                        0x079a
1335 #define regSDMA1_QUEUE3_DOORBELL_BASE_IDX                                                               0
1336 #define regSDMA1_QUEUE3_DOORBELL_LOG                                                                    0x07b1
1337 #define regSDMA1_QUEUE3_DOORBELL_LOG_BASE_IDX                                                           0
1338 #define regSDMA1_QUEUE3_DOORBELL_OFFSET                                                                 0x07b3
1339 #define regSDMA1_QUEUE3_DOORBELL_OFFSET_BASE_IDX                                                        0
1340 #define regSDMA1_QUEUE3_CSA_ADDR_LO                                                                     0x07b4
1341 #define regSDMA1_QUEUE3_CSA_ADDR_LO_BASE_IDX                                                            0
1342 #define regSDMA1_QUEUE3_CSA_ADDR_HI                                                                     0x07b5
1343 #define regSDMA1_QUEUE3_CSA_ADDR_HI_BASE_IDX                                                            0
1344 #define regSDMA1_QUEUE3_SCHEDULE_CNTL                                                                   0x07b6
1345 #define regSDMA1_QUEUE3_SCHEDULE_CNTL_BASE_IDX                                                          0
1346 #define regSDMA1_QUEUE3_IB_SUB_REMAIN                                                                   0x07b7
1347 #define regSDMA1_QUEUE3_IB_SUB_REMAIN_BASE_IDX                                                          0
1348 #define regSDMA1_QUEUE3_PREEMPT                                                                         0x07b8
1349 #define regSDMA1_QUEUE3_PREEMPT_BASE_IDX                                                                0
1350 #define regSDMA1_QUEUE3_DUMMY_REG                                                                       0x07b9
1351 #define regSDMA1_QUEUE3_DUMMY_REG_BASE_IDX                                                              0
1352 #define regSDMA1_QUEUE3_RB_WPTR_POLL_ADDR_HI                                                            0x07ba
1353 #define regSDMA1_QUEUE3_RB_WPTR_POLL_ADDR_HI_BASE_IDX                                                   0
1354 #define regSDMA1_QUEUE3_RB_WPTR_POLL_ADDR_LO                                                            0x07bb
1355 #define regSDMA1_QUEUE3_RB_WPTR_POLL_ADDR_LO_BASE_IDX                                                   0
1356 #define regSDMA1_QUEUE3_RB_AQL_CNTL                                                                     0x07bc
1357 #define regSDMA1_QUEUE3_RB_AQL_CNTL_BASE_IDX                                                            0
1358 #define regSDMA1_QUEUE3_MINOR_PTR_UPDATE                                                                0x07bd
1359 #define regSDMA1_QUEUE3_MINOR_PTR_UPDATE_BASE_IDX                                                       0
1360 #define regSDMA1_QUEUE3_RB_PREEMPT                                                                      0x07be
1361 #define regSDMA1_QUEUE3_RB_PREEMPT_BASE_IDX                                                             0
1362 #define regSDMA1_QUEUE3_MIDCMD_DATA0                                                                    0x07c8
1363 #define regSDMA1_QUEUE3_MIDCMD_DATA0_BASE_IDX                                                           0
1364 #define regSDMA1_QUEUE3_MIDCMD_DATA1                                                                    0x07c9
1365 #define regSDMA1_QUEUE3_MIDCMD_DATA1_BASE_IDX                                                           0
1366 #define regSDMA1_QUEUE3_MIDCMD_DATA2                                                                    0x07ca
1367 #define regSDMA1_QUEUE3_MIDCMD_DATA2_BASE_IDX                                                           0
1368 #define regSDMA1_QUEUE3_MIDCMD_DATA3                                                                    0x07cb
1369 #define regSDMA1_QUEUE3_MIDCMD_DATA3_BASE_IDX                                                           0
1370 #define regSDMA1_QUEUE3_MIDCMD_DATA4                                                                    0x07cc
1371 #define regSDMA1_QUEUE3_MIDCMD_DATA4_BASE_IDX                                                           0
1372 #define regSDMA1_QUEUE3_MIDCMD_DATA5                                                                    0x07cd
1373 #define regSDMA1_QUEUE3_MIDCMD_DATA5_BASE_IDX                                                           0
1374 #define regSDMA1_QUEUE3_MIDCMD_DATA6                                                                    0x07ce
1375 #define regSDMA1_QUEUE3_MIDCMD_DATA6_BASE_IDX                                                           0
1376 #define regSDMA1_QUEUE3_MIDCMD_DATA7                                                                    0x07cf
1377 #define regSDMA1_QUEUE3_MIDCMD_DATA7_BASE_IDX                                                           0
1378 #define regSDMA1_QUEUE3_MIDCMD_DATA8                                                                    0x07d0
1379 #define regSDMA1_QUEUE3_MIDCMD_DATA8_BASE_IDX                                                           0
1380 #define regSDMA1_QUEUE3_MIDCMD_DATA9                                                                    0x07d1
1381 #define regSDMA1_QUEUE3_MIDCMD_DATA9_BASE_IDX                                                           0
1382 #define regSDMA1_QUEUE3_MIDCMD_DATA10                                                                   0x07d2
1383 #define regSDMA1_QUEUE3_MIDCMD_DATA10_BASE_IDX                                                          0
1384 #define regSDMA1_QUEUE3_MIDCMD_CNTL                                                                     0x07d3
1385 #define regSDMA1_QUEUE3_MIDCMD_CNTL_BASE_IDX                                                            0
1386 #define regSDMA1_QUEUE4_RB_CNTL                                                                         0x07e0
1387 #define regSDMA1_QUEUE4_RB_CNTL_BASE_IDX                                                                0
1388 #define regSDMA1_QUEUE4_RB_BASE                                                                         0x07e1
1389 #define regSDMA1_QUEUE4_RB_BASE_BASE_IDX                                                                0
1390 #define regSDMA1_QUEUE4_RB_BASE_HI                                                                      0x07e2
1391 #define regSDMA1_QUEUE4_RB_BASE_HI_BASE_IDX                                                             0
1392 #define regSDMA1_QUEUE4_RB_RPTR                                                                         0x07e3
1393 #define regSDMA1_QUEUE4_RB_RPTR_BASE_IDX                                                                0
1394 #define regSDMA1_QUEUE4_RB_RPTR_HI                                                                      0x07e4
1395 #define regSDMA1_QUEUE4_RB_RPTR_HI_BASE_IDX                                                             0
1396 #define regSDMA1_QUEUE4_RB_WPTR                                                                         0x07e5
1397 #define regSDMA1_QUEUE4_RB_WPTR_BASE_IDX                                                                0
1398 #define regSDMA1_QUEUE4_RB_WPTR_HI                                                                      0x07e6
1399 #define regSDMA1_QUEUE4_RB_WPTR_HI_BASE_IDX                                                             0
1400 #define regSDMA1_QUEUE4_RB_RPTR_ADDR_HI                                                                 0x07e8
1401 #define regSDMA1_QUEUE4_RB_RPTR_ADDR_HI_BASE_IDX                                                        0
1402 #define regSDMA1_QUEUE4_RB_RPTR_ADDR_LO                                                                 0x07e9
1403 #define regSDMA1_QUEUE4_RB_RPTR_ADDR_LO_BASE_IDX                                                        0
1404 #define regSDMA1_QUEUE4_IB_CNTL                                                                         0x07ea
1405 #define regSDMA1_QUEUE4_IB_CNTL_BASE_IDX                                                                0
1406 #define regSDMA1_QUEUE4_IB_RPTR                                                                         0x07eb
1407 #define regSDMA1_QUEUE4_IB_RPTR_BASE_IDX                                                                0
1408 #define regSDMA1_QUEUE4_IB_OFFSET                                                                       0x07ec
1409 #define regSDMA1_QUEUE4_IB_OFFSET_BASE_IDX                                                              0
1410 #define regSDMA1_QUEUE4_IB_BASE_LO                                                                      0x07ed
1411 #define regSDMA1_QUEUE4_IB_BASE_LO_BASE_IDX                                                             0
1412 #define regSDMA1_QUEUE4_IB_BASE_HI                                                                      0x07ee
1413 #define regSDMA1_QUEUE4_IB_BASE_HI_BASE_IDX                                                             0
1414 #define regSDMA1_QUEUE4_IB_SIZE                                                                         0x07ef
1415 #define regSDMA1_QUEUE4_IB_SIZE_BASE_IDX                                                                0
1416 #define regSDMA1_QUEUE4_SKIP_CNTL                                                                       0x07f0
1417 #define regSDMA1_QUEUE4_SKIP_CNTL_BASE_IDX                                                              0
1418 #define regSDMA1_QUEUE4_CONTEXT_STATUS                                                                  0x07f1
1419 #define regSDMA1_QUEUE4_CONTEXT_STATUS_BASE_IDX                                                         0
1420 #define regSDMA1_QUEUE4_DOORBELL                                                                        0x07f2
1421 #define regSDMA1_QUEUE4_DOORBELL_BASE_IDX                                                               0
1422 #define regSDMA1_QUEUE4_DOORBELL_LOG                                                                    0x0809
1423 #define regSDMA1_QUEUE4_DOORBELL_LOG_BASE_IDX                                                           0
1424 #define regSDMA1_QUEUE4_DOORBELL_OFFSET                                                                 0x080b
1425 #define regSDMA1_QUEUE4_DOORBELL_OFFSET_BASE_IDX                                                        0
1426 #define regSDMA1_QUEUE4_CSA_ADDR_LO                                                                     0x080c
1427 #define regSDMA1_QUEUE4_CSA_ADDR_LO_BASE_IDX                                                            0
1428 #define regSDMA1_QUEUE4_CSA_ADDR_HI                                                                     0x080d
1429 #define regSDMA1_QUEUE4_CSA_ADDR_HI_BASE_IDX                                                            0
1430 #define regSDMA1_QUEUE4_SCHEDULE_CNTL                                                                   0x080e
1431 #define regSDMA1_QUEUE4_SCHEDULE_CNTL_BASE_IDX                                                          0
1432 #define regSDMA1_QUEUE4_IB_SUB_REMAIN                                                                   0x080f
1433 #define regSDMA1_QUEUE4_IB_SUB_REMAIN_BASE_IDX                                                          0
1434 #define regSDMA1_QUEUE4_PREEMPT                                                                         0x0810
1435 #define regSDMA1_QUEUE4_PREEMPT_BASE_IDX                                                                0
1436 #define regSDMA1_QUEUE4_DUMMY_REG                                                                       0x0811
1437 #define regSDMA1_QUEUE4_DUMMY_REG_BASE_IDX                                                              0
1438 #define regSDMA1_QUEUE4_RB_WPTR_POLL_ADDR_HI                                                            0x0812
1439 #define regSDMA1_QUEUE4_RB_WPTR_POLL_ADDR_HI_BASE_IDX                                                   0
1440 #define regSDMA1_QUEUE4_RB_WPTR_POLL_ADDR_LO                                                            0x0813
1441 #define regSDMA1_QUEUE4_RB_WPTR_POLL_ADDR_LO_BASE_IDX                                                   0
1442 #define regSDMA1_QUEUE4_RB_AQL_CNTL                                                                     0x0814
1443 #define regSDMA1_QUEUE4_RB_AQL_CNTL_BASE_IDX                                                            0
1444 #define regSDMA1_QUEUE4_MINOR_PTR_UPDATE                                                                0x0815
1445 #define regSDMA1_QUEUE4_MINOR_PTR_UPDATE_BASE_IDX                                                       0
1446 #define regSDMA1_QUEUE4_RB_PREEMPT                                                                      0x0816
1447 #define regSDMA1_QUEUE4_RB_PREEMPT_BASE_IDX                                                             0
1448 #define regSDMA1_QUEUE4_MIDCMD_DATA0                                                                    0x0820
1449 #define regSDMA1_QUEUE4_MIDCMD_DATA0_BASE_IDX                                                           0
1450 #define regSDMA1_QUEUE4_MIDCMD_DATA1                                                                    0x0821
1451 #define regSDMA1_QUEUE4_MIDCMD_DATA1_BASE_IDX                                                           0
1452 #define regSDMA1_QUEUE4_MIDCMD_DATA2                                                                    0x0822
1453 #define regSDMA1_QUEUE4_MIDCMD_DATA2_BASE_IDX                                                           0
1454 #define regSDMA1_QUEUE4_MIDCMD_DATA3                                                                    0x0823
1455 #define regSDMA1_QUEUE4_MIDCMD_DATA3_BASE_IDX                                                           0
1456 #define regSDMA1_QUEUE4_MIDCMD_DATA4                                                                    0x0824
1457 #define regSDMA1_QUEUE4_MIDCMD_DATA4_BASE_IDX                                                           0
1458 #define regSDMA1_QUEUE4_MIDCMD_DATA5                                                                    0x0825
1459 #define regSDMA1_QUEUE4_MIDCMD_DATA5_BASE_IDX                                                           0
1460 #define regSDMA1_QUEUE4_MIDCMD_DATA6                                                                    0x0826
1461 #define regSDMA1_QUEUE4_MIDCMD_DATA6_BASE_IDX                                                           0
1462 #define regSDMA1_QUEUE4_MIDCMD_DATA7                                                                    0x0827
1463 #define regSDMA1_QUEUE4_MIDCMD_DATA7_BASE_IDX                                                           0
1464 #define regSDMA1_QUEUE4_MIDCMD_DATA8                                                                    0x0828
1465 #define regSDMA1_QUEUE4_MIDCMD_DATA8_BASE_IDX                                                           0
1466 #define regSDMA1_QUEUE4_MIDCMD_DATA9                                                                    0x0829
1467 #define regSDMA1_QUEUE4_MIDCMD_DATA9_BASE_IDX                                                           0
1468 #define regSDMA1_QUEUE4_MIDCMD_DATA10                                                                   0x082a
1469 #define regSDMA1_QUEUE4_MIDCMD_DATA10_BASE_IDX                                                          0
1470 #define regSDMA1_QUEUE4_MIDCMD_CNTL                                                                     0x082b
1471 #define regSDMA1_QUEUE4_MIDCMD_CNTL_BASE_IDX                                                            0
1472 #define regSDMA1_QUEUE5_RB_CNTL                                                                         0x0838
1473 #define regSDMA1_QUEUE5_RB_CNTL_BASE_IDX                                                                0
1474 #define regSDMA1_QUEUE5_RB_BASE                                                                         0x0839
1475 #define regSDMA1_QUEUE5_RB_BASE_BASE_IDX                                                                0
1476 #define regSDMA1_QUEUE5_RB_BASE_HI                                                                      0x083a
1477 #define regSDMA1_QUEUE5_RB_BASE_HI_BASE_IDX                                                             0
1478 #define regSDMA1_QUEUE5_RB_RPTR                                                                         0x083b
1479 #define regSDMA1_QUEUE5_RB_RPTR_BASE_IDX                                                                0
1480 #define regSDMA1_QUEUE5_RB_RPTR_HI                                                                      0x083c
1481 #define regSDMA1_QUEUE5_RB_RPTR_HI_BASE_IDX                                                             0
1482 #define regSDMA1_QUEUE5_RB_WPTR                                                                         0x083d
1483 #define regSDMA1_QUEUE5_RB_WPTR_BASE_IDX                                                                0
1484 #define regSDMA1_QUEUE5_RB_WPTR_HI                                                                      0x083e
1485 #define regSDMA1_QUEUE5_RB_WPTR_HI_BASE_IDX                                                             0
1486 #define regSDMA1_QUEUE5_RB_RPTR_ADDR_HI                                                                 0x0840
1487 #define regSDMA1_QUEUE5_RB_RPTR_ADDR_HI_BASE_IDX                                                        0
1488 #define regSDMA1_QUEUE5_RB_RPTR_ADDR_LO                                                                 0x0841
1489 #define regSDMA1_QUEUE5_RB_RPTR_ADDR_LO_BASE_IDX                                                        0
1490 #define regSDMA1_QUEUE5_IB_CNTL                                                                         0x0842
1491 #define regSDMA1_QUEUE5_IB_CNTL_BASE_IDX                                                                0
1492 #define regSDMA1_QUEUE5_IB_RPTR                                                                         0x0843
1493 #define regSDMA1_QUEUE5_IB_RPTR_BASE_IDX                                                                0
1494 #define regSDMA1_QUEUE5_IB_OFFSET                                                                       0x0844
1495 #define regSDMA1_QUEUE5_IB_OFFSET_BASE_IDX                                                              0
1496 #define regSDMA1_QUEUE5_IB_BASE_LO                                                                      0x0845
1497 #define regSDMA1_QUEUE5_IB_BASE_LO_BASE_IDX                                                             0
1498 #define regSDMA1_QUEUE5_IB_BASE_HI                                                                      0x0846
1499 #define regSDMA1_QUEUE5_IB_BASE_HI_BASE_IDX                                                             0
1500 #define regSDMA1_QUEUE5_IB_SIZE                                                                         0x0847
1501 #define regSDMA1_QUEUE5_IB_SIZE_BASE_IDX                                                                0
1502 #define regSDMA1_QUEUE5_SKIP_CNTL                                                                       0x0848
1503 #define regSDMA1_QUEUE5_SKIP_CNTL_BASE_IDX                                                              0
1504 #define regSDMA1_QUEUE5_CONTEXT_STATUS                                                                  0x0849
1505 #define regSDMA1_QUEUE5_CONTEXT_STATUS_BASE_IDX                                                         0
1506 #define regSDMA1_QUEUE5_DOORBELL                                                                        0x084a
1507 #define regSDMA1_QUEUE5_DOORBELL_BASE_IDX                                                               0
1508 #define regSDMA1_QUEUE5_DOORBELL_LOG                                                                    0x0861
1509 #define regSDMA1_QUEUE5_DOORBELL_LOG_BASE_IDX                                                           0
1510 #define regSDMA1_QUEUE5_DOORBELL_OFFSET                                                                 0x0863
1511 #define regSDMA1_QUEUE5_DOORBELL_OFFSET_BASE_IDX                                                        0
1512 #define regSDMA1_QUEUE5_CSA_ADDR_LO                                                                     0x0864
1513 #define regSDMA1_QUEUE5_CSA_ADDR_LO_BASE_IDX                                                            0
1514 #define regSDMA1_QUEUE5_CSA_ADDR_HI                                                                     0x0865
1515 #define regSDMA1_QUEUE5_CSA_ADDR_HI_BASE_IDX                                                            0
1516 #define regSDMA1_QUEUE5_SCHEDULE_CNTL                                                                   0x0866
1517 #define regSDMA1_QUEUE5_SCHEDULE_CNTL_BASE_IDX                                                          0
1518 #define regSDMA1_QUEUE5_IB_SUB_REMAIN                                                                   0x0867
1519 #define regSDMA1_QUEUE5_IB_SUB_REMAIN_BASE_IDX                                                          0
1520 #define regSDMA1_QUEUE5_PREEMPT                                                                         0x0868
1521 #define regSDMA1_QUEUE5_PREEMPT_BASE_IDX                                                                0
1522 #define regSDMA1_QUEUE5_DUMMY_REG                                                                       0x0869
1523 #define regSDMA1_QUEUE5_DUMMY_REG_BASE_IDX                                                              0
1524 #define regSDMA1_QUEUE5_RB_WPTR_POLL_ADDR_HI                                                            0x086a
1525 #define regSDMA1_QUEUE5_RB_WPTR_POLL_ADDR_HI_BASE_IDX                                                   0
1526 #define regSDMA1_QUEUE5_RB_WPTR_POLL_ADDR_LO                                                            0x086b
1527 #define regSDMA1_QUEUE5_RB_WPTR_POLL_ADDR_LO_BASE_IDX                                                   0
1528 #define regSDMA1_QUEUE5_RB_AQL_CNTL                                                                     0x086c
1529 #define regSDMA1_QUEUE5_RB_AQL_CNTL_BASE_IDX                                                            0
1530 #define regSDMA1_QUEUE5_MINOR_PTR_UPDATE                                                                0x086d
1531 #define regSDMA1_QUEUE5_MINOR_PTR_UPDATE_BASE_IDX                                                       0
1532 #define regSDMA1_QUEUE5_RB_PREEMPT                                                                      0x086e
1533 #define regSDMA1_QUEUE5_RB_PREEMPT_BASE_IDX                                                             0
1534 #define regSDMA1_QUEUE5_MIDCMD_DATA0                                                                    0x0878
1535 #define regSDMA1_QUEUE5_MIDCMD_DATA0_BASE_IDX                                                           0
1536 #define regSDMA1_QUEUE5_MIDCMD_DATA1                                                                    0x0879
1537 #define regSDMA1_QUEUE5_MIDCMD_DATA1_BASE_IDX                                                           0
1538 #define regSDMA1_QUEUE5_MIDCMD_DATA2                                                                    0x087a
1539 #define regSDMA1_QUEUE5_MIDCMD_DATA2_BASE_IDX                                                           0
1540 #define regSDMA1_QUEUE5_MIDCMD_DATA3                                                                    0x087b
1541 #define regSDMA1_QUEUE5_MIDCMD_DATA3_BASE_IDX                                                           0
1542 #define regSDMA1_QUEUE5_MIDCMD_DATA4                                                                    0x087c
1543 #define regSDMA1_QUEUE5_MIDCMD_DATA4_BASE_IDX                                                           0
1544 #define regSDMA1_QUEUE5_MIDCMD_DATA5                                                                    0x087d
1545 #define regSDMA1_QUEUE5_MIDCMD_DATA5_BASE_IDX                                                           0
1546 #define regSDMA1_QUEUE5_MIDCMD_DATA6                                                                    0x087e
1547 #define regSDMA1_QUEUE5_MIDCMD_DATA6_BASE_IDX                                                           0
1548 #define regSDMA1_QUEUE5_MIDCMD_DATA7                                                                    0x087f
1549 #define regSDMA1_QUEUE5_MIDCMD_DATA7_BASE_IDX                                                           0
1550 #define regSDMA1_QUEUE5_MIDCMD_DATA8                                                                    0x0880
1551 #define regSDMA1_QUEUE5_MIDCMD_DATA8_BASE_IDX                                                           0
1552 #define regSDMA1_QUEUE5_MIDCMD_DATA9                                                                    0x0881
1553 #define regSDMA1_QUEUE5_MIDCMD_DATA9_BASE_IDX                                                           0
1554 #define regSDMA1_QUEUE5_MIDCMD_DATA10                                                                   0x0882
1555 #define regSDMA1_QUEUE5_MIDCMD_DATA10_BASE_IDX                                                          0
1556 #define regSDMA1_QUEUE5_MIDCMD_CNTL                                                                     0x0883
1557 #define regSDMA1_QUEUE5_MIDCMD_CNTL_BASE_IDX                                                            0
1558 #define regSDMA1_QUEUE6_RB_CNTL                                                                         0x0890
1559 #define regSDMA1_QUEUE6_RB_CNTL_BASE_IDX                                                                0
1560 #define regSDMA1_QUEUE6_RB_BASE                                                                         0x0891
1561 #define regSDMA1_QUEUE6_RB_BASE_BASE_IDX                                                                0
1562 #define regSDMA1_QUEUE6_RB_BASE_HI                                                                      0x0892
1563 #define regSDMA1_QUEUE6_RB_BASE_HI_BASE_IDX                                                             0
1564 #define regSDMA1_QUEUE6_RB_RPTR                                                                         0x0893
1565 #define regSDMA1_QUEUE6_RB_RPTR_BASE_IDX                                                                0
1566 #define regSDMA1_QUEUE6_RB_RPTR_HI                                                                      0x0894
1567 #define regSDMA1_QUEUE6_RB_RPTR_HI_BASE_IDX                                                             0
1568 #define regSDMA1_QUEUE6_RB_WPTR                                                                         0x0895
1569 #define regSDMA1_QUEUE6_RB_WPTR_BASE_IDX                                                                0
1570 #define regSDMA1_QUEUE6_RB_WPTR_HI                                                                      0x0896
1571 #define regSDMA1_QUEUE6_RB_WPTR_HI_BASE_IDX                                                             0
1572 #define regSDMA1_QUEUE6_RB_RPTR_ADDR_HI                                                                 0x0898
1573 #define regSDMA1_QUEUE6_RB_RPTR_ADDR_HI_BASE_IDX                                                        0
1574 #define regSDMA1_QUEUE6_RB_RPTR_ADDR_LO                                                                 0x0899
1575 #define regSDMA1_QUEUE6_RB_RPTR_ADDR_LO_BASE_IDX                                                        0
1576 #define regSDMA1_QUEUE6_IB_CNTL                                                                         0x089a
1577 #define regSDMA1_QUEUE6_IB_CNTL_BASE_IDX                                                                0
1578 #define regSDMA1_QUEUE6_IB_RPTR                                                                         0x089b
1579 #define regSDMA1_QUEUE6_IB_RPTR_BASE_IDX                                                                0
1580 #define regSDMA1_QUEUE6_IB_OFFSET                                                                       0x089c
1581 #define regSDMA1_QUEUE6_IB_OFFSET_BASE_IDX                                                              0
1582 #define regSDMA1_QUEUE6_IB_BASE_LO                                                                      0x089d
1583 #define regSDMA1_QUEUE6_IB_BASE_LO_BASE_IDX                                                             0
1584 #define regSDMA1_QUEUE6_IB_BASE_HI                                                                      0x089e
1585 #define regSDMA1_QUEUE6_IB_BASE_HI_BASE_IDX                                                             0
1586 #define regSDMA1_QUEUE6_IB_SIZE                                                                         0x089f
1587 #define regSDMA1_QUEUE6_IB_SIZE_BASE_IDX                                                                0
1588 #define regSDMA1_QUEUE6_SKIP_CNTL                                                                       0x08a0
1589 #define regSDMA1_QUEUE6_SKIP_CNTL_BASE_IDX                                                              0
1590 #define regSDMA1_QUEUE6_CONTEXT_STATUS                                                                  0x08a1
1591 #define regSDMA1_QUEUE6_CONTEXT_STATUS_BASE_IDX                                                         0
1592 #define regSDMA1_QUEUE6_DOORBELL                                                                        0x08a2
1593 #define regSDMA1_QUEUE6_DOORBELL_BASE_IDX                                                               0
1594 #define regSDMA1_QUEUE6_DOORBELL_LOG                                                                    0x08b9
1595 #define regSDMA1_QUEUE6_DOORBELL_LOG_BASE_IDX                                                           0
1596 #define regSDMA1_QUEUE6_DOORBELL_OFFSET                                                                 0x08bb
1597 #define regSDMA1_QUEUE6_DOORBELL_OFFSET_BASE_IDX                                                        0
1598 #define regSDMA1_QUEUE6_CSA_ADDR_LO                                                                     0x08bc
1599 #define regSDMA1_QUEUE6_CSA_ADDR_LO_BASE_IDX                                                            0
1600 #define regSDMA1_QUEUE6_CSA_ADDR_HI                                                                     0x08bd
1601 #define regSDMA1_QUEUE6_CSA_ADDR_HI_BASE_IDX                                                            0
1602 #define regSDMA1_QUEUE6_SCHEDULE_CNTL                                                                   0x08be
1603 #define regSDMA1_QUEUE6_SCHEDULE_CNTL_BASE_IDX                                                          0
1604 #define regSDMA1_QUEUE6_IB_SUB_REMAIN                                                                   0x08bf
1605 #define regSDMA1_QUEUE6_IB_SUB_REMAIN_BASE_IDX                                                          0
1606 #define regSDMA1_QUEUE6_PREEMPT                                                                         0x08c0
1607 #define regSDMA1_QUEUE6_PREEMPT_BASE_IDX                                                                0
1608 #define regSDMA1_QUEUE6_DUMMY_REG                                                                       0x08c1
1609 #define regSDMA1_QUEUE6_DUMMY_REG_BASE_IDX                                                              0
1610 #define regSDMA1_QUEUE6_RB_WPTR_POLL_ADDR_HI                                                            0x08c2
1611 #define regSDMA1_QUEUE6_RB_WPTR_POLL_ADDR_HI_BASE_IDX                                                   0
1612 #define regSDMA1_QUEUE6_RB_WPTR_POLL_ADDR_LO                                                            0x08c3
1613 #define regSDMA1_QUEUE6_RB_WPTR_POLL_ADDR_LO_BASE_IDX                                                   0
1614 #define regSDMA1_QUEUE6_RB_AQL_CNTL                                                                     0x08c4
1615 #define regSDMA1_QUEUE6_RB_AQL_CNTL_BASE_IDX                                                            0
1616 #define regSDMA1_QUEUE6_MINOR_PTR_UPDATE                                                                0x08c5
1617 #define regSDMA1_QUEUE6_MINOR_PTR_UPDATE_BASE_IDX                                                       0
1618 #define regSDMA1_QUEUE6_RB_PREEMPT                                                                      0x08c6
1619 #define regSDMA1_QUEUE6_RB_PREEMPT_BASE_IDX                                                             0
1620 #define regSDMA1_QUEUE6_MIDCMD_DATA0                                                                    0x08d0
1621 #define regSDMA1_QUEUE6_MIDCMD_DATA0_BASE_IDX                                                           0
1622 #define regSDMA1_QUEUE6_MIDCMD_DATA1                                                                    0x08d1
1623 #define regSDMA1_QUEUE6_MIDCMD_DATA1_BASE_IDX                                                           0
1624 #define regSDMA1_QUEUE6_MIDCMD_DATA2                                                                    0x08d2
1625 #define regSDMA1_QUEUE6_MIDCMD_DATA2_BASE_IDX                                                           0
1626 #define regSDMA1_QUEUE6_MIDCMD_DATA3                                                                    0x08d3
1627 #define regSDMA1_QUEUE6_MIDCMD_DATA3_BASE_IDX                                                           0
1628 #define regSDMA1_QUEUE6_MIDCMD_DATA4                                                                    0x08d4
1629 #define regSDMA1_QUEUE6_MIDCMD_DATA4_BASE_IDX                                                           0
1630 #define regSDMA1_QUEUE6_MIDCMD_DATA5                                                                    0x08d5
1631 #define regSDMA1_QUEUE6_MIDCMD_DATA5_BASE_IDX                                                           0
1632 #define regSDMA1_QUEUE6_MIDCMD_DATA6                                                                    0x08d6
1633 #define regSDMA1_QUEUE6_MIDCMD_DATA6_BASE_IDX                                                           0
1634 #define regSDMA1_QUEUE6_MIDCMD_DATA7                                                                    0x08d7
1635 #define regSDMA1_QUEUE6_MIDCMD_DATA7_BASE_IDX                                                           0
1636 #define regSDMA1_QUEUE6_MIDCMD_DATA8                                                                    0x08d8
1637 #define regSDMA1_QUEUE6_MIDCMD_DATA8_BASE_IDX                                                           0
1638 #define regSDMA1_QUEUE6_MIDCMD_DATA9                                                                    0x08d9
1639 #define regSDMA1_QUEUE6_MIDCMD_DATA9_BASE_IDX                                                           0
1640 #define regSDMA1_QUEUE6_MIDCMD_DATA10                                                                   0x08da
1641 #define regSDMA1_QUEUE6_MIDCMD_DATA10_BASE_IDX                                                          0
1642 #define regSDMA1_QUEUE6_MIDCMD_CNTL                                                                     0x08db
1643 #define regSDMA1_QUEUE6_MIDCMD_CNTL_BASE_IDX                                                            0
1644 #define regSDMA1_QUEUE7_RB_CNTL                                                                         0x08e8
1645 #define regSDMA1_QUEUE7_RB_CNTL_BASE_IDX                                                                0
1646 #define regSDMA1_QUEUE7_RB_BASE                                                                         0x08e9
1647 #define regSDMA1_QUEUE7_RB_BASE_BASE_IDX                                                                0
1648 #define regSDMA1_QUEUE7_RB_BASE_HI                                                                      0x08ea
1649 #define regSDMA1_QUEUE7_RB_BASE_HI_BASE_IDX                                                             0
1650 #define regSDMA1_QUEUE7_RB_RPTR                                                                         0x08eb
1651 #define regSDMA1_QUEUE7_RB_RPTR_BASE_IDX                                                                0
1652 #define regSDMA1_QUEUE7_RB_RPTR_HI                                                                      0x08ec
1653 #define regSDMA1_QUEUE7_RB_RPTR_HI_BASE_IDX                                                             0
1654 #define regSDMA1_QUEUE7_RB_WPTR                                                                         0x08ed
1655 #define regSDMA1_QUEUE7_RB_WPTR_BASE_IDX                                                                0
1656 #define regSDMA1_QUEUE7_RB_WPTR_HI                                                                      0x08ee
1657 #define regSDMA1_QUEUE7_RB_WPTR_HI_BASE_IDX                                                             0
1658 #define regSDMA1_QUEUE7_RB_RPTR_ADDR_HI                                                                 0x08f0
1659 #define regSDMA1_QUEUE7_RB_RPTR_ADDR_HI_BASE_IDX                                                        0
1660 #define regSDMA1_QUEUE7_RB_RPTR_ADDR_LO                                                                 0x08f1
1661 #define regSDMA1_QUEUE7_RB_RPTR_ADDR_LO_BASE_IDX                                                        0
1662 #define regSDMA1_QUEUE7_IB_CNTL                                                                         0x08f2
1663 #define regSDMA1_QUEUE7_IB_CNTL_BASE_IDX                                                                0
1664 #define regSDMA1_QUEUE7_IB_RPTR                                                                         0x08f3
1665 #define regSDMA1_QUEUE7_IB_RPTR_BASE_IDX                                                                0
1666 #define regSDMA1_QUEUE7_IB_OFFSET                                                                       0x08f4
1667 #define regSDMA1_QUEUE7_IB_OFFSET_BASE_IDX                                                              0
1668 #define regSDMA1_QUEUE7_IB_BASE_LO                                                                      0x08f5
1669 #define regSDMA1_QUEUE7_IB_BASE_LO_BASE_IDX                                                             0
1670 #define regSDMA1_QUEUE7_IB_BASE_HI                                                                      0x08f6
1671 #define regSDMA1_QUEUE7_IB_BASE_HI_BASE_IDX                                                             0
1672 #define regSDMA1_QUEUE7_IB_SIZE                                                                         0x08f7
1673 #define regSDMA1_QUEUE7_IB_SIZE_BASE_IDX                                                                0
1674 #define regSDMA1_QUEUE7_SKIP_CNTL                                                                       0x08f8
1675 #define regSDMA1_QUEUE7_SKIP_CNTL_BASE_IDX                                                              0
1676 #define regSDMA1_QUEUE7_CONTEXT_STATUS                                                                  0x08f9
1677 #define regSDMA1_QUEUE7_CONTEXT_STATUS_BASE_IDX                                                         0
1678 #define regSDMA1_QUEUE7_DOORBELL                                                                        0x08fa
1679 #define regSDMA1_QUEUE7_DOORBELL_BASE_IDX                                                               0
1680 #define regSDMA1_QUEUE7_DOORBELL_LOG                                                                    0x0911
1681 #define regSDMA1_QUEUE7_DOORBELL_LOG_BASE_IDX                                                           0
1682 #define regSDMA1_QUEUE7_DOORBELL_OFFSET                                                                 0x0913
1683 #define regSDMA1_QUEUE7_DOORBELL_OFFSET_BASE_IDX                                                        0
1684 #define regSDMA1_QUEUE7_CSA_ADDR_LO                                                                     0x0914
1685 #define regSDMA1_QUEUE7_CSA_ADDR_LO_BASE_IDX                                                            0
1686 #define regSDMA1_QUEUE7_CSA_ADDR_HI                                                                     0x0915
1687 #define regSDMA1_QUEUE7_CSA_ADDR_HI_BASE_IDX                                                            0
1688 #define regSDMA1_QUEUE7_SCHEDULE_CNTL                                                                   0x0916
1689 #define regSDMA1_QUEUE7_SCHEDULE_CNTL_BASE_IDX                                                          0
1690 #define regSDMA1_QUEUE7_IB_SUB_REMAIN                                                                   0x0917
1691 #define regSDMA1_QUEUE7_IB_SUB_REMAIN_BASE_IDX                                                          0
1692 #define regSDMA1_QUEUE7_PREEMPT                                                                         0x0918
1693 #define regSDMA1_QUEUE7_PREEMPT_BASE_IDX                                                                0
1694 #define regSDMA1_QUEUE7_DUMMY_REG                                                                       0x0919
1695 #define regSDMA1_QUEUE7_DUMMY_REG_BASE_IDX                                                              0
1696 #define regSDMA1_QUEUE7_RB_WPTR_POLL_ADDR_HI                                                            0x091a
1697 #define regSDMA1_QUEUE7_RB_WPTR_POLL_ADDR_HI_BASE_IDX                                                   0
1698 #define regSDMA1_QUEUE7_RB_WPTR_POLL_ADDR_LO                                                            0x091b
1699 #define regSDMA1_QUEUE7_RB_WPTR_POLL_ADDR_LO_BASE_IDX                                                   0
1700 #define regSDMA1_QUEUE7_RB_AQL_CNTL                                                                     0x091c
1701 #define regSDMA1_QUEUE7_RB_AQL_CNTL_BASE_IDX                                                            0
1702 #define regSDMA1_QUEUE7_MINOR_PTR_UPDATE                                                                0x091d
1703 #define regSDMA1_QUEUE7_MINOR_PTR_UPDATE_BASE_IDX                                                       0
1704 #define regSDMA1_QUEUE7_RB_PREEMPT                                                                      0x091e
1705 #define regSDMA1_QUEUE7_RB_PREEMPT_BASE_IDX                                                             0
1706 #define regSDMA1_QUEUE7_MIDCMD_DATA0                                                                    0x0928
1707 #define regSDMA1_QUEUE7_MIDCMD_DATA0_BASE_IDX                                                           0
1708 #define regSDMA1_QUEUE7_MIDCMD_DATA1                                                                    0x0929
1709 #define regSDMA1_QUEUE7_MIDCMD_DATA1_BASE_IDX                                                           0
1710 #define regSDMA1_QUEUE7_MIDCMD_DATA2                                                                    0x092a
1711 #define regSDMA1_QUEUE7_MIDCMD_DATA2_BASE_IDX                                                           0
1712 #define regSDMA1_QUEUE7_MIDCMD_DATA3                                                                    0x092b
1713 #define regSDMA1_QUEUE7_MIDCMD_DATA3_BASE_IDX                                                           0
1714 #define regSDMA1_QUEUE7_MIDCMD_DATA4                                                                    0x092c
1715 #define regSDMA1_QUEUE7_MIDCMD_DATA4_BASE_IDX                                                           0
1716 #define regSDMA1_QUEUE7_MIDCMD_DATA5                                                                    0x092d
1717 #define regSDMA1_QUEUE7_MIDCMD_DATA5_BASE_IDX                                                           0
1718 #define regSDMA1_QUEUE7_MIDCMD_DATA6                                                                    0x092e
1719 #define regSDMA1_QUEUE7_MIDCMD_DATA6_BASE_IDX                                                           0
1720 #define regSDMA1_QUEUE7_MIDCMD_DATA7                                                                    0x092f
1721 #define regSDMA1_QUEUE7_MIDCMD_DATA7_BASE_IDX                                                           0
1722 #define regSDMA1_QUEUE7_MIDCMD_DATA8                                                                    0x0930
1723 #define regSDMA1_QUEUE7_MIDCMD_DATA8_BASE_IDX                                                           0
1724 #define regSDMA1_QUEUE7_MIDCMD_DATA9                                                                    0x0931
1725 #define regSDMA1_QUEUE7_MIDCMD_DATA9_BASE_IDX                                                           0
1726 #define regSDMA1_QUEUE7_MIDCMD_DATA10                                                                   0x0932
1727 #define regSDMA1_QUEUE7_MIDCMD_DATA10_BASE_IDX                                                          0
1728 #define regSDMA1_QUEUE7_MIDCMD_CNTL                                                                     0x0933
1729 #define regSDMA1_QUEUE7_MIDCMD_CNTL_BASE_IDX                                                            0
1730 
1731 
1732 // addressBlock: gc_sdma0_sdma0hypdec
1733 // base address: 0x3e200
1734 #define regSDMA0_UCODE_ADDR                                                                             0x5880
1735 #define regSDMA0_UCODE_ADDR_BASE_IDX                                                                    1
1736 #define regSDMA0_UCODE_DATA                                                                             0x5881
1737 #define regSDMA0_UCODE_DATA_BASE_IDX                                                                    1
1738 #define regSDMA0_UCODE_SELFLOAD_CONTROL                                                                 0x5882
1739 #define regSDMA0_UCODE_SELFLOAD_CONTROL_BASE_IDX                                                        1
1740 #define regSDMA0_BROADCAST_UCODE_ADDR                                                                   0x5886
1741 #define regSDMA0_BROADCAST_UCODE_ADDR_BASE_IDX                                                          1
1742 #define regSDMA0_BROADCAST_UCODE_DATA                                                                   0x5887
1743 #define regSDMA0_BROADCAST_UCODE_DATA_BASE_IDX                                                          1
1744 #define regSDMA0_F32_CNTL                                                                               0x589a
1745 #define regSDMA0_F32_CNTL_BASE_IDX                                                                      1
1746 
1747 
1748 // addressBlock: gc_sdma0_sdma1hypdec
1749 // base address: 0x3e280
1750 #define regSDMA1_UCODE_ADDR                                                                             0x58a0
1751 #define regSDMA1_UCODE_ADDR_BASE_IDX                                                                    1
1752 #define regSDMA1_UCODE_DATA                                                                             0x58a1
1753 #define regSDMA1_UCODE_DATA_BASE_IDX                                                                    1
1754 #define regSDMA1_UCODE_SELFLOAD_CONTROL                                                                 0x58a2
1755 #define regSDMA1_UCODE_SELFLOAD_CONTROL_BASE_IDX                                                        1
1756 #define regSDMA1_BROADCAST_UCODE_ADDR                                                                   0x58a6
1757 #define regSDMA1_BROADCAST_UCODE_ADDR_BASE_IDX                                                          1
1758 #define regSDMA1_BROADCAST_UCODE_DATA                                                                   0x58a7
1759 #define regSDMA1_BROADCAST_UCODE_DATA_BASE_IDX                                                          1
1760 #define regSDMA1_F32_CNTL                                                                               0x58ba
1761 #define regSDMA1_F32_CNTL_BASE_IDX                                                                      1
1762 
1763 
1764 // addressBlock: gc_sdma0_sdma0perfsdec
1765 // base address: 0x37880
1766 #define regSDMA0_PERFCNT_PERFCOUNTER0_CFG                                                               0x3e20
1767 #define regSDMA0_PERFCNT_PERFCOUNTER0_CFG_BASE_IDX                                                      1
1768 #define regSDMA0_PERFCNT_PERFCOUNTER1_CFG                                                               0x3e21
1769 #define regSDMA0_PERFCNT_PERFCOUNTER1_CFG_BASE_IDX                                                      1
1770 #define regSDMA0_PERFCNT_PERFCOUNTER_RSLT_CNTL                                                          0x3e22
1771 #define regSDMA0_PERFCNT_PERFCOUNTER_RSLT_CNTL_BASE_IDX                                                 1
1772 #define regSDMA0_PERFCNT_MISC_CNTL                                                                      0x3e23
1773 #define regSDMA0_PERFCNT_MISC_CNTL_BASE_IDX                                                             1
1774 #define regSDMA0_PERFCOUNTER0_SELECT                                                                    0x3e24
1775 #define regSDMA0_PERFCOUNTER0_SELECT_BASE_IDX                                                           1
1776 #define regSDMA0_PERFCOUNTER0_SELECT1                                                                   0x3e25
1777 #define regSDMA0_PERFCOUNTER0_SELECT1_BASE_IDX                                                          1
1778 #define regSDMA0_PERFCOUNTER1_SELECT                                                                    0x3e26
1779 #define regSDMA0_PERFCOUNTER1_SELECT_BASE_IDX                                                           1
1780 #define regSDMA0_PERFCOUNTER1_SELECT1                                                                   0x3e27
1781 #define regSDMA0_PERFCOUNTER1_SELECT1_BASE_IDX                                                          1
1782 
1783 
1784 // addressBlock: gc_sdma0_sdma1perfsdec
1785 // base address: 0x378b0
1786 #define regSDMA1_PERFCNT_PERFCOUNTER0_CFG                                                               0x3e2c
1787 #define regSDMA1_PERFCNT_PERFCOUNTER0_CFG_BASE_IDX                                                      1
1788 #define regSDMA1_PERFCNT_PERFCOUNTER1_CFG                                                               0x3e2d
1789 #define regSDMA1_PERFCNT_PERFCOUNTER1_CFG_BASE_IDX                                                      1
1790 #define regSDMA1_PERFCNT_PERFCOUNTER_RSLT_CNTL                                                          0x3e2e
1791 #define regSDMA1_PERFCNT_PERFCOUNTER_RSLT_CNTL_BASE_IDX                                                 1
1792 #define regSDMA1_PERFCNT_MISC_CNTL                                                                      0x3e2f
1793 #define regSDMA1_PERFCNT_MISC_CNTL_BASE_IDX                                                             1
1794 #define regSDMA1_PERFCOUNTER0_SELECT                                                                    0x3e30
1795 #define regSDMA1_PERFCOUNTER0_SELECT_BASE_IDX                                                           1
1796 #define regSDMA1_PERFCOUNTER0_SELECT1                                                                   0x3e31
1797 #define regSDMA1_PERFCOUNTER0_SELECT1_BASE_IDX                                                          1
1798 #define regSDMA1_PERFCOUNTER1_SELECT                                                                    0x3e32
1799 #define regSDMA1_PERFCOUNTER1_SELECT_BASE_IDX                                                           1
1800 #define regSDMA1_PERFCOUNTER1_SELECT1                                                                   0x3e33
1801 #define regSDMA1_PERFCOUNTER1_SELECT1_BASE_IDX                                                          1
1802 
1803 
1804 // addressBlock: gc_sdma0_sdma0perfddec
1805 // base address: 0x35980
1806 #define regSDMA0_PERFCNT_PERFCOUNTER_LO                                                                 0x3660
1807 #define regSDMA0_PERFCNT_PERFCOUNTER_LO_BASE_IDX                                                        1
1808 #define regSDMA0_PERFCNT_PERFCOUNTER_HI                                                                 0x3661
1809 #define regSDMA0_PERFCNT_PERFCOUNTER_HI_BASE_IDX                                                        1
1810 #define regSDMA0_PERFCOUNTER0_LO                                                                        0x3662
1811 #define regSDMA0_PERFCOUNTER0_LO_BASE_IDX                                                               1
1812 #define regSDMA0_PERFCOUNTER0_HI                                                                        0x3663
1813 #define regSDMA0_PERFCOUNTER0_HI_BASE_IDX                                                               1
1814 #define regSDMA0_PERFCOUNTER1_LO                                                                        0x3664
1815 #define regSDMA0_PERFCOUNTER1_LO_BASE_IDX                                                               1
1816 #define regSDMA0_PERFCOUNTER1_HI                                                                        0x3665
1817 #define regSDMA0_PERFCOUNTER1_HI_BASE_IDX                                                               1
1818 
1819 
1820 // addressBlock: gc_sdma0_sdma1perfddec
1821 // base address: 0x359b0
1822 #define regSDMA1_PERFCNT_PERFCOUNTER_LO                                                                 0x366c
1823 #define regSDMA1_PERFCNT_PERFCOUNTER_LO_BASE_IDX                                                        1
1824 #define regSDMA1_PERFCNT_PERFCOUNTER_HI                                                                 0x366d
1825 #define regSDMA1_PERFCNT_PERFCOUNTER_HI_BASE_IDX                                                        1
1826 #define regSDMA1_PERFCOUNTER0_LO                                                                        0x366e
1827 #define regSDMA1_PERFCOUNTER0_LO_BASE_IDX                                                               1
1828 #define regSDMA1_PERFCOUNTER0_HI                                                                        0x366f
1829 #define regSDMA1_PERFCOUNTER0_HI_BASE_IDX                                                               1
1830 #define regSDMA1_PERFCOUNTER1_LO                                                                        0x3670
1831 #define regSDMA1_PERFCOUNTER1_LO_BASE_IDX                                                               1
1832 #define regSDMA1_PERFCOUNTER1_HI                                                                        0x3671
1833 #define regSDMA1_PERFCOUNTER1_HI_BASE_IDX                                                               1
1834 
1835 
1836 // addressBlock: gc_grbmdec
1837 // base address: 0x8000
1838 #define regGRBM_CNTL                                                                                    0x0da0
1839 #define regGRBM_CNTL_BASE_IDX                                                                           0
1840 #define regGRBM_SKEW_CNTL                                                                               0x0da1
1841 #define regGRBM_SKEW_CNTL_BASE_IDX                                                                      0
1842 #define regGRBM_STATUS2                                                                                 0x0da2
1843 #define regGRBM_STATUS2_BASE_IDX                                                                        0
1844 #define regGRBM_PWR_CNTL                                                                                0x0da3
1845 #define regGRBM_PWR_CNTL_BASE_IDX                                                                       0
1846 #define regGRBM_STATUS                                                                                  0x0da4
1847 #define regGRBM_STATUS_BASE_IDX                                                                         0
1848 #define regGRBM_STATUS_SE0                                                                              0x0da5
1849 #define regGRBM_STATUS_SE0_BASE_IDX                                                                     0
1850 #define regGRBM_STATUS_SE1                                                                              0x0da6
1851 #define regGRBM_STATUS_SE1_BASE_IDX                                                                     0
1852 #define regGRBM_STATUS3                                                                                 0x0da7
1853 #define regGRBM_STATUS3_BASE_IDX                                                                        0
1854 #define regGRBM_SOFT_RESET                                                                              0x0da8
1855 #define regGRBM_SOFT_RESET_BASE_IDX                                                                     0
1856 #define regGRBM_GFX_CLKEN_CNTL                                                                          0x0dac
1857 #define regGRBM_GFX_CLKEN_CNTL_BASE_IDX                                                                 0
1858 #define regGRBM_WAIT_IDLE_CLOCKS                                                                        0x0dad
1859 #define regGRBM_WAIT_IDLE_CLOCKS_BASE_IDX                                                               0
1860 #define regGRBM_STATUS_SE2                                                                              0x0dae
1861 #define regGRBM_STATUS_SE2_BASE_IDX                                                                     0
1862 #define regGRBM_STATUS_SE3                                                                              0x0daf
1863 #define regGRBM_STATUS_SE3_BASE_IDX                                                                     0
1864 #define regGRBM_STATUS_SE4                                                                              0x0db0
1865 #define regGRBM_STATUS_SE4_BASE_IDX                                                                     0
1866 #define regGRBM_STATUS_SE5                                                                              0x0db1
1867 #define regGRBM_STATUS_SE5_BASE_IDX                                                                     0
1868 #define regGRBM_READ_ERROR                                                                              0x0db6
1869 #define regGRBM_READ_ERROR_BASE_IDX                                                                     0
1870 #define regGRBM_READ_ERROR2                                                                             0x0db7
1871 #define regGRBM_READ_ERROR2_BASE_IDX                                                                    0
1872 #define regGRBM_INT_CNTL                                                                                0x0db8
1873 #define regGRBM_INT_CNTL_BASE_IDX                                                                       0
1874 #define regGRBM_TRAP_OP                                                                                 0x0db9
1875 #define regGRBM_TRAP_OP_BASE_IDX                                                                        0
1876 #define regGRBM_TRAP_ADDR                                                                               0x0dba
1877 #define regGRBM_TRAP_ADDR_BASE_IDX                                                                      0
1878 #define regGRBM_TRAP_ADDR_MSK                                                                           0x0dbb
1879 #define regGRBM_TRAP_ADDR_MSK_BASE_IDX                                                                  0
1880 #define regGRBM_TRAP_WD                                                                                 0x0dbc
1881 #define regGRBM_TRAP_WD_BASE_IDX                                                                        0
1882 #define regGRBM_TRAP_WD_MSK                                                                             0x0dbd
1883 #define regGRBM_TRAP_WD_MSK_BASE_IDX                                                                    0
1884 #define regGRBM_DSM_BYPASS                                                                              0x0dbe
1885 #define regGRBM_DSM_BYPASS_BASE_IDX                                                                     0
1886 #define regGRBM_WRITE_ERROR                                                                             0x0dbf
1887 #define regGRBM_WRITE_ERROR_BASE_IDX                                                                    0
1888 #define regGRBM_CHIP_REVISION                                                                           0x0dc1
1889 #define regGRBM_CHIP_REVISION_BASE_IDX                                                                  0
1890 #define regGRBM_IH_CREDIT                                                                               0x0dc4
1891 #define regGRBM_IH_CREDIT_BASE_IDX                                                                      0
1892 #define regGRBM_PWR_CNTL2                                                                               0x0dc5
1893 #define regGRBM_PWR_CNTL2_BASE_IDX                                                                      0
1894 #define regGRBM_UTCL2_INVAL_RANGE_START                                                                 0x0dc6
1895 #define regGRBM_UTCL2_INVAL_RANGE_START_BASE_IDX                                                        0
1896 #define regGRBM_UTCL2_INVAL_RANGE_END                                                                   0x0dc7
1897 #define regGRBM_UTCL2_INVAL_RANGE_END_BASE_IDX                                                          0
1898 #define regGRBM_INVALID_PIPE                                                                            0x0dc9
1899 #define regGRBM_INVALID_PIPE_BASE_IDX                                                                   0
1900 #define regGRBM_FENCE_RANGE0                                                                            0x0dca
1901 #define regGRBM_FENCE_RANGE0_BASE_IDX                                                                   0
1902 #define regGRBM_FENCE_RANGE1                                                                            0x0dcb
1903 #define regGRBM_FENCE_RANGE1_BASE_IDX                                                                   0
1904 #define regGRBM_SCRATCH_REG0                                                                            0x0de0
1905 #define regGRBM_SCRATCH_REG0_BASE_IDX                                                                   0
1906 #define regGRBM_SCRATCH_REG1                                                                            0x0de1
1907 #define regGRBM_SCRATCH_REG1_BASE_IDX                                                                   0
1908 #define regGRBM_SCRATCH_REG2                                                                            0x0de2
1909 #define regGRBM_SCRATCH_REG2_BASE_IDX                                                                   0
1910 #define regGRBM_SCRATCH_REG3                                                                            0x0de3
1911 #define regGRBM_SCRATCH_REG3_BASE_IDX                                                                   0
1912 #define regGRBM_SCRATCH_REG4                                                                            0x0de4
1913 #define regGRBM_SCRATCH_REG4_BASE_IDX                                                                   0
1914 #define regGRBM_SCRATCH_REG5                                                                            0x0de5
1915 #define regGRBM_SCRATCH_REG5_BASE_IDX                                                                   0
1916 #define regGRBM_SCRATCH_REG6                                                                            0x0de6
1917 #define regGRBM_SCRATCH_REG6_BASE_IDX                                                                   0
1918 #define regGRBM_SCRATCH_REG7                                                                            0x0de7
1919 #define regGRBM_SCRATCH_REG7_BASE_IDX                                                                   0
1920 #define regVIOLATION_DATA_ASYNC_VF_PROG                                                                 0x0df1
1921 #define regVIOLATION_DATA_ASYNC_VF_PROG_BASE_IDX                                                        0
1922 
1923 
1924 // addressBlock: gc_cpdec
1925 // base address: 0x8200
1926 #define regCP_CPC_DEBUG_CNTL                                                                            0x0e20
1927 #define regCP_CPC_DEBUG_CNTL_BASE_IDX                                                                   0
1928 #define regCP_CPC_DEBUG_DATA                                                                            0x0e21
1929 #define regCP_CPC_DEBUG_DATA_BASE_IDX                                                                   0
1930 #define regCP_CPC_STATUS                                                                                0x0e24
1931 #define regCP_CPC_STATUS_BASE_IDX                                                                       0
1932 #define regCP_CPC_BUSY_STAT                                                                             0x0e25
1933 #define regCP_CPC_BUSY_STAT_BASE_IDX                                                                    0
1934 #define regCP_CPC_STALLED_STAT1                                                                         0x0e26
1935 #define regCP_CPC_STALLED_STAT1_BASE_IDX                                                                0
1936 #define regCP_CPF_STATUS                                                                                0x0e27
1937 #define regCP_CPF_STATUS_BASE_IDX                                                                       0
1938 #define regCP_CPF_BUSY_STAT                                                                             0x0e28
1939 #define regCP_CPF_BUSY_STAT_BASE_IDX                                                                    0
1940 #define regCP_CPF_STALLED_STAT1                                                                         0x0e29
1941 #define regCP_CPF_STALLED_STAT1_BASE_IDX                                                                0
1942 #define regCP_CPC_BUSY_STAT2                                                                            0x0e2a
1943 #define regCP_CPC_BUSY_STAT2_BASE_IDX                                                                   0
1944 #define regCP_CPC_GRBM_FREE_COUNT                                                                       0x0e2b
1945 #define regCP_CPC_GRBM_FREE_COUNT_BASE_IDX                                                              0
1946 #define regCP_CPC_PRIV_VIOLATION_ADDR                                                                   0x0e2c
1947 #define regCP_CPC_PRIV_VIOLATION_ADDR_BASE_IDX                                                          0
1948 #define regCP_MEC_ME1_HEADER_DUMP                                                                       0x0e2e
1949 #define regCP_MEC_ME1_HEADER_DUMP_BASE_IDX                                                              0
1950 #define regCP_MEC_ME2_HEADER_DUMP                                                                       0x0e2f
1951 #define regCP_MEC_ME2_HEADER_DUMP_BASE_IDX                                                              0
1952 #define regCP_CPC_SCRATCH_INDEX                                                                         0x0e30
1953 #define regCP_CPC_SCRATCH_INDEX_BASE_IDX                                                                0
1954 #define regCP_CPC_SCRATCH_DATA                                                                          0x0e31
1955 #define regCP_CPC_SCRATCH_DATA_BASE_IDX                                                                 0
1956 #define regCP_CPF_GRBM_FREE_COUNT                                                                       0x0e32
1957 #define regCP_CPF_GRBM_FREE_COUNT_BASE_IDX                                                              0
1958 #define regCP_CPF_BUSY_STAT2                                                                            0x0e33
1959 #define regCP_CPF_BUSY_STAT2_BASE_IDX                                                                   0
1960 #define regCP_CPC_HALT_HYST_COUNT                                                                       0x0e47
1961 #define regCP_CPC_HALT_HYST_COUNT_BASE_IDX                                                              0
1962 #define regCP_STALLED_STAT3                                                                             0x0f3c
1963 #define regCP_STALLED_STAT3_BASE_IDX                                                                    0
1964 #define regCP_STALLED_STAT1                                                                             0x0f3d
1965 #define regCP_STALLED_STAT1_BASE_IDX                                                                    0
1966 #define regCP_STALLED_STAT2                                                                             0x0f3e
1967 #define regCP_STALLED_STAT2_BASE_IDX                                                                    0
1968 #define regCP_BUSY_STAT                                                                                 0x0f3f
1969 #define regCP_BUSY_STAT_BASE_IDX                                                                        0
1970 #define regCP_STAT                                                                                      0x0f40
1971 #define regCP_STAT_BASE_IDX                                                                             0
1972 #define regCP_ME_HEADER_DUMP                                                                            0x0f41
1973 #define regCP_ME_HEADER_DUMP_BASE_IDX                                                                   0
1974 #define regCP_PFP_HEADER_DUMP                                                                           0x0f42
1975 #define regCP_PFP_HEADER_DUMP_BASE_IDX                                                                  0
1976 #define regCP_GRBM_FREE_COUNT                                                                           0x0f43
1977 #define regCP_GRBM_FREE_COUNT_BASE_IDX                                                                  0
1978 #define regCP_PFP_INSTR_PNTR                                                                            0x0f45
1979 #define regCP_PFP_INSTR_PNTR_BASE_IDX                                                                   0
1980 #define regCP_ME_INSTR_PNTR                                                                             0x0f46
1981 #define regCP_ME_INSTR_PNTR_BASE_IDX                                                                    0
1982 #define regCP_MEC1_INSTR_PNTR                                                                           0x0f48
1983 #define regCP_MEC1_INSTR_PNTR_BASE_IDX                                                                  0
1984 #define regCP_MEC2_INSTR_PNTR                                                                           0x0f49
1985 #define regCP_MEC2_INSTR_PNTR_BASE_IDX                                                                  0
1986 #define regCP_CSF_STAT                                                                                  0x0f54
1987 #define regCP_CSF_STAT_BASE_IDX                                                                         0
1988 #define regCP_CNTX_STAT                                                                                 0x0f58
1989 #define regCP_CNTX_STAT_BASE_IDX                                                                        0
1990 #define regCP_ME_PREEMPTION                                                                             0x0f59
1991 #define regCP_ME_PREEMPTION_BASE_IDX                                                                    0
1992 #define regCP_RB1_RPTR                                                                                  0x0f5f
1993 #define regCP_RB1_RPTR_BASE_IDX                                                                         0
1994 #define regCP_RB0_RPTR                                                                                  0x0f60
1995 #define regCP_RB0_RPTR_BASE_IDX                                                                         0
1996 #define regCP_RB_RPTR                                                                                   0x0f60
1997 #define regCP_RB_RPTR_BASE_IDX                                                                          0
1998 #define regCP_RB_WPTR_DELAY                                                                             0x0f61
1999 #define regCP_RB_WPTR_DELAY_BASE_IDX                                                                    0
2000 #define regCP_RB_WPTR_POLL_CNTL                                                                         0x0f62
2001 #define regCP_RB_WPTR_POLL_CNTL_BASE_IDX                                                                0
2002 #define regCP_ROQ1_THRESHOLDS                                                                           0x0f75
2003 #define regCP_ROQ1_THRESHOLDS_BASE_IDX                                                                  0
2004 #define regCP_ROQ2_THRESHOLDS                                                                           0x0f76
2005 #define regCP_ROQ2_THRESHOLDS_BASE_IDX                                                                  0
2006 #define regCP_STQ_THRESHOLDS                                                                            0x0f77
2007 #define regCP_STQ_THRESHOLDS_BASE_IDX                                                                   0
2008 #define regCP_MEQ_THRESHOLDS                                                                            0x0f79
2009 #define regCP_MEQ_THRESHOLDS_BASE_IDX                                                                   0
2010 #define regCP_ROQ_AVAIL                                                                                 0x0f7a
2011 #define regCP_ROQ_AVAIL_BASE_IDX                                                                        0
2012 #define regCP_STQ_AVAIL                                                                                 0x0f7b
2013 #define regCP_STQ_AVAIL_BASE_IDX                                                                        0
2014 #define regCP_ROQ2_AVAIL                                                                                0x0f7c
2015 #define regCP_ROQ2_AVAIL_BASE_IDX                                                                       0
2016 #define regCP_MEQ_AVAIL                                                                                 0x0f7d
2017 #define regCP_MEQ_AVAIL_BASE_IDX                                                                        0
2018 #define regCP_CMD_INDEX                                                                                 0x0f7e
2019 #define regCP_CMD_INDEX_BASE_IDX                                                                        0
2020 #define regCP_CMD_DATA                                                                                  0x0f7f
2021 #define regCP_CMD_DATA_BASE_IDX                                                                         0
2022 #define regCP_ROQ_RB_STAT                                                                               0x0f80
2023 #define regCP_ROQ_RB_STAT_BASE_IDX                                                                      0
2024 #define regCP_ROQ_IB1_STAT                                                                              0x0f81
2025 #define regCP_ROQ_IB1_STAT_BASE_IDX                                                                     0
2026 #define regCP_ROQ_IB2_STAT                                                                              0x0f82
2027 #define regCP_ROQ_IB2_STAT_BASE_IDX                                                                     0
2028 #define regCP_STQ_STAT                                                                                  0x0f83
2029 #define regCP_STQ_STAT_BASE_IDX                                                                         0
2030 #define regCP_STQ_WR_STAT                                                                               0x0f84
2031 #define regCP_STQ_WR_STAT_BASE_IDX                                                                      0
2032 #define regCP_MEQ_STAT                                                                                  0x0f85
2033 #define regCP_MEQ_STAT_BASE_IDX                                                                         0
2034 #define regCP_ROQ3_THRESHOLDS                                                                           0x0f8c
2035 #define regCP_ROQ3_THRESHOLDS_BASE_IDX                                                                  0
2036 #define regCP_ROQ_DB_STAT                                                                               0x0f8d
2037 #define regCP_ROQ_DB_STAT_BASE_IDX                                                                      0
2038 #define regCP_DEBUG_CNTL                                                                                0x0f98
2039 #define regCP_DEBUG_CNTL_BASE_IDX                                                                       0
2040 #define regCP_DEBUG_DATA                                                                                0x0f99
2041 #define regCP_DEBUG_DATA_BASE_IDX                                                                       0
2042 #define regCP_PRIV_VIOLATION_ADDR                                                                       0x0f9a
2043 #define regCP_PRIV_VIOLATION_ADDR_BASE_IDX                                                              0
2044 
2045 
2046 // addressBlock: gc_padec
2047 // base address: 0x8800
2048 #define regVGT_DMA_DATA_FIFO_DEPTH                                                                      0x0fcd
2049 #define regVGT_DMA_DATA_FIFO_DEPTH_BASE_IDX                                                             0
2050 #define regVGT_DMA_REQ_FIFO_DEPTH                                                                       0x0fce
2051 #define regVGT_DMA_REQ_FIFO_DEPTH_BASE_IDX                                                              0
2052 #define regVGT_DRAW_INIT_FIFO_DEPTH                                                                     0x0fcf
2053 #define regVGT_DRAW_INIT_FIFO_DEPTH_BASE_IDX                                                            0
2054 #define regVGT_MC_LAT_CNTL                                                                              0x0fd6
2055 #define regVGT_MC_LAT_CNTL_BASE_IDX                                                                     0
2056 #define regIA_UTCL1_STATUS_2                                                                            0x0fd7
2057 #define regIA_UTCL1_STATUS_2_BASE_IDX                                                                   0
2058 #define regWD_CNTL_STATUS                                                                               0x0fdf
2059 #define regWD_CNTL_STATUS_BASE_IDX                                                                      0
2060 #define regCC_GC_PRIM_CONFIG                                                                            0x0fe0
2061 #define regCC_GC_PRIM_CONFIG_BASE_IDX                                                                   0
2062 #define regWD_QOS                                                                                       0x0fe2
2063 #define regWD_QOS_BASE_IDX                                                                              0
2064 #define regWD_UTCL1_CNTL                                                                                0x0fe3
2065 #define regWD_UTCL1_CNTL_BASE_IDX                                                                       0
2066 #define regWD_UTCL1_STATUS                                                                              0x0fe4
2067 #define regWD_UTCL1_STATUS_BASE_IDX                                                                     0
2068 #define regIA_UTCL1_CNTL                                                                                0x0fe6
2069 #define regIA_UTCL1_CNTL_BASE_IDX                                                                       0
2070 #define regIA_UTCL1_STATUS                                                                              0x0fe7
2071 #define regIA_UTCL1_STATUS_BASE_IDX                                                                     0
2072 #define regCC_GC_SA_UNIT_DISABLE                                                                        0x0fe9
2073 #define regCC_GC_SA_UNIT_DISABLE_BASE_IDX                                                               0
2074 #define regGE_RATE_CNTL_1                                                                               0x0ff4
2075 #define regGE_RATE_CNTL_1_BASE_IDX                                                                      0
2076 #define regGE_RATE_CNTL_2                                                                               0x0ff5
2077 #define regGE_RATE_CNTL_2_BASE_IDX                                                                      0
2078 #define regVGT_SYS_CONFIG                                                                               0x1003
2079 #define regVGT_SYS_CONFIG_BASE_IDX                                                                      0
2080 #define regGE_PRIV_CONTROL                                                                              0x1004
2081 #define regGE_PRIV_CONTROL_BASE_IDX                                                                     0
2082 #define regGE_STATUS                                                                                    0x1005
2083 #define regGE_STATUS_BASE_IDX                                                                           0
2084 #define regVGT_GS_MAX_WAVE_ID                                                                           0x1009
2085 #define regVGT_GS_MAX_WAVE_ID_BASE_IDX                                                                  0
2086 #define regGFX_PIPE_CONTROL                                                                             0x100d
2087 #define regGFX_PIPE_CONTROL_BASE_IDX                                                                    0
2088 #define regCC_GC_SHADER_ARRAY_CONFIG                                                                    0x100f
2089 #define regCC_GC_SHADER_ARRAY_CONFIG_BASE_IDX                                                           0
2090 #define regGE2_SE_CNTL_STATUS                                                                           0x1011
2091 #define regGE2_SE_CNTL_STATUS_BASE_IDX                                                                  0
2092 #define regGE_SPI_IF_SAFE_REG                                                                           0x1018
2093 #define regGE_SPI_IF_SAFE_REG_BASE_IDX                                                                  0
2094 #define regGE_PA_IF_SAFE_REG                                                                            0x1019
2095 #define regGE_PA_IF_SAFE_REG_BASE_IDX                                                                   0
2096 #define regPA_CL_CNTL_STATUS                                                                            0x1024
2097 #define regPA_CL_CNTL_STATUS_BASE_IDX                                                                   0
2098 #define regPA_CL_ENHANCE                                                                                0x1025
2099 #define regPA_CL_ENHANCE_BASE_IDX                                                                       0
2100 #define regPA_SU_CNTL_STATUS                                                                            0x1034
2101 #define regPA_SU_CNTL_STATUS_BASE_IDX                                                                   0
2102 #define regPA_SC_FIFO_DEPTH_CNTL                                                                        0x1035
2103 #define regPA_SC_FIFO_DEPTH_CNTL_BASE_IDX                                                               0
2104 
2105 
2106 // addressBlock: gc_sqdec
2107 // base address: 0x8c00
2108 #define regSQ_CONFIG                                                                                    0x10a0
2109 #define regSQ_CONFIG_BASE_IDX                                                                           0
2110 #define regSQC_CONFIG                                                                                   0x10a1
2111 #define regSQC_CONFIG_BASE_IDX                                                                          0
2112 #define regLDS_CONFIG                                                                                   0x10a2
2113 #define regLDS_CONFIG_BASE_IDX                                                                          0
2114 #define regSQ_RANDOM_WAVE_PRI                                                                           0x10a3
2115 #define regSQ_RANDOM_WAVE_PRI_BASE_IDX                                                                  0
2116 #define regSQG_STATUS                                                                                   0x10a4
2117 #define regSQG_STATUS_BASE_IDX                                                                          0
2118 #define regSQ_FIFO_SIZES                                                                                0x10a5
2119 #define regSQ_FIFO_SIZES_BASE_IDX                                                                       0
2120 #define regSQ_DSM_CNTL                                                                                  0x10a6
2121 #define regSQ_DSM_CNTL_BASE_IDX                                                                         0
2122 #define regSQ_DSM_CNTL2                                                                                 0x10a7
2123 #define regSQ_DSM_CNTL2_BASE_IDX                                                                        0
2124 #define regSP_CONFIG                                                                                    0x10ab
2125 #define regSP_CONFIG_BASE_IDX                                                                           0
2126 #define regSQ_ARB_CONFIG                                                                                0x10ac
2127 #define regSQ_ARB_CONFIG_BASE_IDX                                                                       0
2128 #define regSQ_DEBUG_HOST_TRAP_STATUS                                                                    0x10b6
2129 #define regSQ_DEBUG_HOST_TRAP_STATUS_BASE_IDX                                                           0
2130 #define regSQG_GL1H_STATUS                                                                              0x10b9
2131 #define regSQG_GL1H_STATUS_BASE_IDX                                                                     0
2132 #define regSQG_CONFIG                                                                                   0x10ba
2133 #define regSQG_CONFIG_BASE_IDX                                                                          0
2134 #define regSQ_PERF_SNAPSHOT_CTRL                                                                        0x10bb
2135 #define regSQ_PERF_SNAPSHOT_CTRL_BASE_IDX                                                               0
2136 #define regCC_GC_SHADER_RATE_CONFIG                                                                     0x10bc
2137 #define regCC_GC_SHADER_RATE_CONFIG_BASE_IDX                                                            0
2138 #define regSQ_INTERRUPT_AUTO_MASK                                                                       0x10be
2139 #define regSQ_INTERRUPT_AUTO_MASK_BASE_IDX                                                              0
2140 #define regSQ_INTERRUPT_MSG_CTRL                                                                        0x10bf
2141 #define regSQ_INTERRUPT_MSG_CTRL_BASE_IDX                                                               0
2142 #define regSQ_WATCH0_ADDR_H                                                                             0x10d0
2143 #define regSQ_WATCH0_ADDR_H_BASE_IDX                                                                    0
2144 #define regSQ_WATCH0_ADDR_L                                                                             0x10d1
2145 #define regSQ_WATCH0_ADDR_L_BASE_IDX                                                                    0
2146 #define regSQ_WATCH0_CNTL                                                                               0x10d2
2147 #define regSQ_WATCH0_CNTL_BASE_IDX                                                                      0
2148 #define regSQ_WATCH1_ADDR_H                                                                             0x10d3
2149 #define regSQ_WATCH1_ADDR_H_BASE_IDX                                                                    0
2150 #define regSQ_WATCH1_ADDR_L                                                                             0x10d4
2151 #define regSQ_WATCH1_ADDR_L_BASE_IDX                                                                    0
2152 #define regSQ_WATCH1_CNTL                                                                               0x10d5
2153 #define regSQ_WATCH1_CNTL_BASE_IDX                                                                      0
2154 #define regSQ_WATCH2_ADDR_H                                                                             0x10d6
2155 #define regSQ_WATCH2_ADDR_H_BASE_IDX                                                                    0
2156 #define regSQ_WATCH2_ADDR_L                                                                             0x10d7
2157 #define regSQ_WATCH2_ADDR_L_BASE_IDX                                                                    0
2158 #define regSQ_WATCH2_CNTL                                                                               0x10d8
2159 #define regSQ_WATCH2_CNTL_BASE_IDX                                                                      0
2160 #define regSQ_WATCH3_ADDR_H                                                                             0x10d9
2161 #define regSQ_WATCH3_ADDR_H_BASE_IDX                                                                    0
2162 #define regSQ_WATCH3_ADDR_L                                                                             0x10da
2163 #define regSQ_WATCH3_ADDR_L_BASE_IDX                                                                    0
2164 #define regSQ_WATCH3_CNTL                                                                               0x10db
2165 #define regSQ_WATCH3_CNTL_BASE_IDX                                                                      0
2166 #define regSQ_IND_INDEX                                                                                 0x1118
2167 #define regSQ_IND_INDEX_BASE_IDX                                                                        0
2168 #define regSQ_IND_DATA                                                                                  0x1119
2169 #define regSQ_IND_DATA_BASE_IDX                                                                         0
2170 #define regSQ_CMD                                                                                       0x111b
2171 #define regSQ_CMD_BASE_IDX                                                                              0
2172 
2173 
2174 // addressBlock: gc_shsdec
2175 // base address: 0x9000
2176 #define regSX_DEBUG_1                                                                                   0x11b8
2177 #define regSX_DEBUG_1_BASE_IDX                                                                          0
2178 #define regSPI_PS_MAX_WAVE_ID                                                                           0x11da
2179 #define regSPI_PS_MAX_WAVE_ID_BASE_IDX                                                                  0
2180 #define regSPI_GFX_CNTL                                                                                 0x11dc
2181 #define regSPI_GFX_CNTL_BASE_IDX                                                                        0
2182 #define regSPI_DSM_CNTL                                                                                 0x11e3
2183 #define regSPI_DSM_CNTL_BASE_IDX                                                                        0
2184 #define regSPI_DSM_CNTL2                                                                                0x11e4
2185 #define regSPI_DSM_CNTL2_BASE_IDX                                                                       0
2186 #define regSPI_EDC_CNT                                                                                  0x11e5
2187 #define regSPI_EDC_CNT_BASE_IDX                                                                         0
2188 #define regSPI_CONFIG_PS_CU_EN                                                                          0x11f2
2189 #define regSPI_CONFIG_PS_CU_EN_BASE_IDX                                                                 0
2190 #define regSPI_WF_LIFETIME_CNTL                                                                         0x124a
2191 #define regSPI_WF_LIFETIME_CNTL_BASE_IDX                                                                0
2192 #define regSPI_WF_LIFETIME_LIMIT_0                                                                      0x124b
2193 #define regSPI_WF_LIFETIME_LIMIT_0_BASE_IDX                                                             0
2194 #define regSPI_WF_LIFETIME_LIMIT_1                                                                      0x124c
2195 #define regSPI_WF_LIFETIME_LIMIT_1_BASE_IDX                                                             0
2196 #define regSPI_WF_LIFETIME_LIMIT_2                                                                      0x124d
2197 #define regSPI_WF_LIFETIME_LIMIT_2_BASE_IDX                                                             0
2198 #define regSPI_WF_LIFETIME_LIMIT_3                                                                      0x124e
2199 #define regSPI_WF_LIFETIME_LIMIT_3_BASE_IDX                                                             0
2200 #define regSPI_WF_LIFETIME_LIMIT_4                                                                      0x124f
2201 #define regSPI_WF_LIFETIME_LIMIT_4_BASE_IDX                                                             0
2202 #define regSPI_WF_LIFETIME_LIMIT_5                                                                      0x1250
2203 #define regSPI_WF_LIFETIME_LIMIT_5_BASE_IDX                                                             0
2204 #define regSPI_WF_LIFETIME_STATUS_0                                                                     0x1255
2205 #define regSPI_WF_LIFETIME_STATUS_0_BASE_IDX                                                            0
2206 #define regSPI_WF_LIFETIME_STATUS_2                                                                     0x1257
2207 #define regSPI_WF_LIFETIME_STATUS_2_BASE_IDX                                                            0
2208 #define regSPI_WF_LIFETIME_STATUS_4                                                                     0x1259
2209 #define regSPI_WF_LIFETIME_STATUS_4_BASE_IDX                                                            0
2210 #define regSPI_WF_LIFETIME_STATUS_6                                                                     0x125b
2211 #define regSPI_WF_LIFETIME_STATUS_6_BASE_IDX                                                            0
2212 #define regSPI_WF_LIFETIME_STATUS_7                                                                     0x125c
2213 #define regSPI_WF_LIFETIME_STATUS_7_BASE_IDX                                                            0
2214 #define regSPI_WF_LIFETIME_STATUS_9                                                                     0x125e
2215 #define regSPI_WF_LIFETIME_STATUS_9_BASE_IDX                                                            0
2216 #define regSPI_WF_LIFETIME_STATUS_11                                                                    0x1260
2217 #define regSPI_WF_LIFETIME_STATUS_11_BASE_IDX                                                           0
2218 #define regSPI_WF_LIFETIME_STATUS_13                                                                    0x1262
2219 #define regSPI_WF_LIFETIME_STATUS_13_BASE_IDX                                                           0
2220 #define regSPI_WF_LIFETIME_STATUS_14                                                                    0x1263
2221 #define regSPI_WF_LIFETIME_STATUS_14_BASE_IDX                                                           0
2222 #define regSPI_WF_LIFETIME_STATUS_15                                                                    0x1264
2223 #define regSPI_WF_LIFETIME_STATUS_15_BASE_IDX                                                           0
2224 #define regSPI_WF_LIFETIME_STATUS_16                                                                    0x1265
2225 #define regSPI_WF_LIFETIME_STATUS_16_BASE_IDX                                                           0
2226 #define regSPI_WF_LIFETIME_STATUS_17                                                                    0x1266
2227 #define regSPI_WF_LIFETIME_STATUS_17_BASE_IDX                                                           0
2228 #define regSPI_WF_LIFETIME_STATUS_18                                                                    0x1267
2229 #define regSPI_WF_LIFETIME_STATUS_18_BASE_IDX                                                           0
2230 #define regSPI_WF_LIFETIME_STATUS_19                                                                    0x1268
2231 #define regSPI_WF_LIFETIME_STATUS_19_BASE_IDX                                                           0
2232 #define regSPI_WF_LIFETIME_STATUS_20                                                                    0x1269
2233 #define regSPI_WF_LIFETIME_STATUS_20_BASE_IDX                                                           0
2234 #define regSPI_WF_LIFETIME_STATUS_21                                                                    0x126b
2235 #define regSPI_WF_LIFETIME_STATUS_21_BASE_IDX                                                           0
2236 #define regSPI_LB_CTR_CTRL                                                                              0x1274
2237 #define regSPI_LB_CTR_CTRL_BASE_IDX                                                                     0
2238 #define regSPI_LB_WGP_MASK                                                                              0x1275
2239 #define regSPI_LB_WGP_MASK_BASE_IDX                                                                     0
2240 #define regSPI_LB_DATA_REG                                                                              0x1276
2241 #define regSPI_LB_DATA_REG_BASE_IDX                                                                     0
2242 #define regSPI_PG_ENABLE_STATIC_WGP_MASK                                                                0x1277
2243 #define regSPI_PG_ENABLE_STATIC_WGP_MASK_BASE_IDX                                                       0
2244 #define regSPI_GDS_CREDITS                                                                              0x1278
2245 #define regSPI_GDS_CREDITS_BASE_IDX                                                                     0
2246 #define regSPI_SX_EXPORT_BUFFER_SIZES                                                                   0x1279
2247 #define regSPI_SX_EXPORT_BUFFER_SIZES_BASE_IDX                                                          0
2248 #define regSPI_SX_SCOREBOARD_BUFFER_SIZES                                                               0x127a
2249 #define regSPI_SX_SCOREBOARD_BUFFER_SIZES_BASE_IDX                                                      0
2250 #define regSPI_CSQ_WF_ACTIVE_STATUS                                                                     0x127b
2251 #define regSPI_CSQ_WF_ACTIVE_STATUS_BASE_IDX                                                            0
2252 #define regSPI_CSQ_WF_ACTIVE_COUNT_0                                                                    0x127c
2253 #define regSPI_CSQ_WF_ACTIVE_COUNT_0_BASE_IDX                                                           0
2254 #define regSPI_CSQ_WF_ACTIVE_COUNT_1                                                                    0x127d
2255 #define regSPI_CSQ_WF_ACTIVE_COUNT_1_BASE_IDX                                                           0
2256 #define regSPI_CSQ_WF_ACTIVE_COUNT_2                                                                    0x127e
2257 #define regSPI_CSQ_WF_ACTIVE_COUNT_2_BASE_IDX                                                           0
2258 #define regSPI_CSQ_WF_ACTIVE_COUNT_3                                                                    0x127f
2259 #define regSPI_CSQ_WF_ACTIVE_COUNT_3_BASE_IDX                                                           0
2260 #define regSPI_LB_DATA_WAVES                                                                            0x1284
2261 #define regSPI_LB_DATA_WAVES_BASE_IDX                                                                   0
2262 #define regSPI_P0_TRAP_SCREEN_PSBA_LO                                                                   0x128c
2263 #define regSPI_P0_TRAP_SCREEN_PSBA_LO_BASE_IDX                                                          0
2264 #define regSPI_P0_TRAP_SCREEN_PSBA_HI                                                                   0x128d
2265 #define regSPI_P0_TRAP_SCREEN_PSBA_HI_BASE_IDX                                                          0
2266 #define regSPI_P0_TRAP_SCREEN_PSMA_LO                                                                   0x128e
2267 #define regSPI_P0_TRAP_SCREEN_PSMA_LO_BASE_IDX                                                          0
2268 #define regSPI_P0_TRAP_SCREEN_PSMA_HI                                                                   0x128f
2269 #define regSPI_P0_TRAP_SCREEN_PSMA_HI_BASE_IDX                                                          0
2270 #define regSPI_P0_TRAP_SCREEN_GPR_MIN                                                                   0x1290
2271 #define regSPI_P0_TRAP_SCREEN_GPR_MIN_BASE_IDX                                                          0
2272 #define regSPI_P1_TRAP_SCREEN_PSBA_LO                                                                   0x1291
2273 #define regSPI_P1_TRAP_SCREEN_PSBA_LO_BASE_IDX                                                          0
2274 #define regSPI_P1_TRAP_SCREEN_PSBA_HI                                                                   0x1292
2275 #define regSPI_P1_TRAP_SCREEN_PSBA_HI_BASE_IDX                                                          0
2276 #define regSPI_P1_TRAP_SCREEN_PSMA_LO                                                                   0x1293
2277 #define regSPI_P1_TRAP_SCREEN_PSMA_LO_BASE_IDX                                                          0
2278 #define regSPI_P1_TRAP_SCREEN_PSMA_HI                                                                   0x1294
2279 #define regSPI_P1_TRAP_SCREEN_PSMA_HI_BASE_IDX                                                          0
2280 #define regSPI_P1_TRAP_SCREEN_GPR_MIN                                                                   0x1295
2281 #define regSPI_P1_TRAP_SCREEN_GPR_MIN_BASE_IDX                                                          0
2282 
2283 
2284 // addressBlock: gc_tpdec
2285 // base address: 0x9400
2286 #define regTD_STATUS                                                                                    0x12c6
2287 #define regTD_STATUS_BASE_IDX                                                                           0
2288 #define regTD_DSM_CNTL                                                                                  0x12cf
2289 #define regTD_DSM_CNTL_BASE_IDX                                                                         0
2290 #define regTD_DSM_CNTL2                                                                                 0x12d0
2291 #define regTD_DSM_CNTL2_BASE_IDX                                                                        0
2292 #define regTD_SCRATCH                                                                                   0x12d3
2293 #define regTD_SCRATCH_BASE_IDX                                                                          0
2294 #define regTA_CNTL                                                                                      0x12e1
2295 #define regTA_CNTL_BASE_IDX                                                                             0
2296 #define regTA_CNTL_AUX                                                                                  0x12e2
2297 #define regTA_CNTL_AUX_BASE_IDX                                                                         0
2298 #define regTA_CNTL2                                                                                     0x12e5
2299 #define regTA_CNTL2_BASE_IDX                                                                            0
2300 #define regTA_STATUS                                                                                    0x12e8
2301 #define regTA_STATUS_BASE_IDX                                                                           0
2302 #define regTA_SCRATCH                                                                                   0x1304
2303 #define regTA_SCRATCH_BASE_IDX                                                                          0
2304 
2305 
2306 // addressBlock: gc_gdsdec
2307 // base address: 0x9700
2308 #define regGDS_CONFIG                                                                                   0x1360
2309 #define regGDS_CONFIG_BASE_IDX                                                                          0
2310 #define regGDS_CNTL_STATUS                                                                              0x1361
2311 #define regGDS_CNTL_STATUS_BASE_IDX                                                                     0
2312 #define regGDS_ENHANCE                                                                                  0x1362
2313 #define regGDS_ENHANCE_BASE_IDX                                                                         0
2314 #define regGDS_PROTECTION_FAULT                                                                         0x1363
2315 #define regGDS_PROTECTION_FAULT_BASE_IDX                                                                0
2316 #define regGDS_VM_PROTECTION_FAULT                                                                      0x1364
2317 #define regGDS_VM_PROTECTION_FAULT_BASE_IDX                                                             0
2318 #define regGDS_EDC_CNT                                                                                  0x1365
2319 #define regGDS_EDC_CNT_BASE_IDX                                                                         0
2320 #define regGDS_EDC_GRBM_CNT                                                                             0x1366
2321 #define regGDS_EDC_GRBM_CNT_BASE_IDX                                                                    0
2322 #define regGDS_EDC_OA_DED                                                                               0x1367
2323 #define regGDS_EDC_OA_DED_BASE_IDX                                                                      0
2324 #define regGDS_DSM_CNTL                                                                                 0x136a
2325 #define regGDS_DSM_CNTL_BASE_IDX                                                                        0
2326 #define regGDS_EDC_OA_PHY_CNT                                                                           0x136b
2327 #define regGDS_EDC_OA_PHY_CNT_BASE_IDX                                                                  0
2328 #define regGDS_EDC_OA_PIPE_CNT                                                                          0x136c
2329 #define regGDS_EDC_OA_PIPE_CNT_BASE_IDX                                                                 0
2330 #define regGDS_DSM_CNTL2                                                                                0x136d
2331 #define regGDS_DSM_CNTL2_BASE_IDX                                                                       0
2332 
2333 
2334 // addressBlock: gc_rbdec
2335 // base address: 0x9800
2336 #define regDB_DEBUG                                                                                     0x13ac
2337 #define regDB_DEBUG_BASE_IDX                                                                            0
2338 #define regDB_DEBUG2                                                                                    0x13ad
2339 #define regDB_DEBUG2_BASE_IDX                                                                           0
2340 #define regDB_DEBUG3                                                                                    0x13ae
2341 #define regDB_DEBUG3_BASE_IDX                                                                           0
2342 #define regDB_DEBUG4                                                                                    0x13af
2343 #define regDB_DEBUG4_BASE_IDX                                                                           0
2344 #define regDB_ETILE_STUTTER_CONTROL                                                                     0x13b0
2345 #define regDB_ETILE_STUTTER_CONTROL_BASE_IDX                                                            0
2346 #define regDB_LTILE_STUTTER_CONTROL                                                                     0x13b1
2347 #define regDB_LTILE_STUTTER_CONTROL_BASE_IDX                                                            0
2348 #define regDB_EQUAD_STUTTER_CONTROL                                                                     0x13b2
2349 #define regDB_EQUAD_STUTTER_CONTROL_BASE_IDX                                                            0
2350 #define regDB_LQUAD_STUTTER_CONTROL                                                                     0x13b3
2351 #define regDB_LQUAD_STUTTER_CONTROL_BASE_IDX                                                            0
2352 #define regDB_CREDIT_LIMIT                                                                              0x13b4
2353 #define regDB_CREDIT_LIMIT_BASE_IDX                                                                     0
2354 #define regDB_WATERMARKS                                                                                0x13b5
2355 #define regDB_WATERMARKS_BASE_IDX                                                                       0
2356 #define regDB_SUBTILE_CONTROL                                                                           0x13b6
2357 #define regDB_SUBTILE_CONTROL_BASE_IDX                                                                  0
2358 #define regDB_FREE_CACHELINES                                                                           0x13b7
2359 #define regDB_FREE_CACHELINES_BASE_IDX                                                                  0
2360 #define regDB_FIFO_DEPTH1                                                                               0x13b8
2361 #define regDB_FIFO_DEPTH1_BASE_IDX                                                                      0
2362 #define regDB_FIFO_DEPTH2                                                                               0x13b9
2363 #define regDB_FIFO_DEPTH2_BASE_IDX                                                                      0
2364 #define regDB_LAST_OF_BURST_CONFIG                                                                      0x13ba
2365 #define regDB_LAST_OF_BURST_CONFIG_BASE_IDX                                                             0
2366 #define regDB_RING_CONTROL                                                                              0x13bb
2367 #define regDB_RING_CONTROL_BASE_IDX                                                                     0
2368 #define regDB_MEM_ARB_WATERMARKS                                                                        0x13bc
2369 #define regDB_MEM_ARB_WATERMARKS_BASE_IDX                                                               0
2370 #define regDB_FIFO_DEPTH3                                                                               0x13bd
2371 #define regDB_FIFO_DEPTH3_BASE_IDX                                                                      0
2372 #define regDB_DEBUG6                                                                                    0x13be
2373 #define regDB_DEBUG6_BASE_IDX                                                                           0
2374 #define regDB_EXCEPTION_CONTROL                                                                         0x13bf
2375 #define regDB_EXCEPTION_CONTROL_BASE_IDX                                                                0
2376 #define regDB_DEBUG7                                                                                    0x13d0
2377 #define regDB_DEBUG7_BASE_IDX                                                                           0
2378 #define regDB_DEBUG5                                                                                    0x13d1
2379 #define regDB_DEBUG5_BASE_IDX                                                                           0
2380 #define regDB_FGCG_SRAMS_CLK_CTRL                                                                       0x13d7
2381 #define regDB_FGCG_SRAMS_CLK_CTRL_BASE_IDX                                                              0
2382 #define regDB_FGCG_INTERFACES_CLK_CTRL                                                                  0x13d8
2383 #define regDB_FGCG_INTERFACES_CLK_CTRL_BASE_IDX                                                         0
2384 #define regDB_FIFO_DEPTH4                                                                               0x13d9
2385 #define regDB_FIFO_DEPTH4_BASE_IDX                                                                      0
2386 #define regCC_RB_REDUNDANCY                                                                             0x13dc
2387 #define regCC_RB_REDUNDANCY_BASE_IDX                                                                    0
2388 #define regCC_RB_BACKEND_DISABLE                                                                        0x13dd
2389 #define regCC_RB_BACKEND_DISABLE_BASE_IDX                                                               0
2390 #define regGB_ADDR_CONFIG                                                                               0x13de
2391 #define regGB_ADDR_CONFIG_BASE_IDX                                                                      0
2392 #define regGB_BACKEND_MAP                                                                               0x13df
2393 #define regGB_BACKEND_MAP_BASE_IDX                                                                      0
2394 #define regGB_GPU_ID                                                                                    0x13e0
2395 #define regGB_GPU_ID_BASE_IDX                                                                           0
2396 #define regCC_RB_DAISY_CHAIN                                                                            0x13e1
2397 #define regCC_RB_DAISY_CHAIN_BASE_IDX                                                                   0
2398 #define regGB_ADDR_CONFIG_READ                                                                          0x13e2
2399 #define regGB_ADDR_CONFIG_READ_BASE_IDX                                                                 0
2400 #define regCB_HW_CONTROL_4                                                                              0x1422
2401 #define regCB_HW_CONTROL_4_BASE_IDX                                                                     0
2402 #define regCB_HW_CONTROL_3                                                                              0x1423
2403 #define regCB_HW_CONTROL_3_BASE_IDX                                                                     0
2404 #define regCB_HW_CONTROL                                                                                0x1424
2405 #define regCB_HW_CONTROL_BASE_IDX                                                                       0
2406 #define regCB_HW_CONTROL_1                                                                              0x1425
2407 #define regCB_HW_CONTROL_1_BASE_IDX                                                                     0
2408 #define regCB_HW_CONTROL_2                                                                              0x1426
2409 #define regCB_HW_CONTROL_2_BASE_IDX                                                                     0
2410 #define regCB_DCC_CONFIG                                                                                0x1427
2411 #define regCB_DCC_CONFIG_BASE_IDX                                                                       0
2412 #define regCB_HW_MEM_ARBITER_RD                                                                         0x1428
2413 #define regCB_HW_MEM_ARBITER_RD_BASE_IDX                                                                0
2414 #define regCB_HW_MEM_ARBITER_WR                                                                         0x1429
2415 #define regCB_HW_MEM_ARBITER_WR_BASE_IDX                                                                0
2416 #define regCB_FGCG_SRAM_OVERRIDE                                                                        0x142a
2417 #define regCB_FGCG_SRAM_OVERRIDE_BASE_IDX                                                               0
2418 #define regCB_DCC_CONFIG2                                                                               0x142b
2419 #define regCB_DCC_CONFIG2_BASE_IDX                                                                      0
2420 #define regCHICKEN_BITS                                                                                 0x142d
2421 #define regCHICKEN_BITS_BASE_IDX                                                                        0
2422 #define regCB_CACHE_EVICT_POINTS                                                                        0x142e
2423 #define regCB_CACHE_EVICT_POINTS_BASE_IDX                                                               0
2424 
2425 
2426 // addressBlock: gc_gceadec
2427 // base address: 0xa800
2428 #define regGCEA_DRAM_RD_CLI2GRP_MAP0                                                                    0x17a0
2429 #define regGCEA_DRAM_RD_CLI2GRP_MAP0_BASE_IDX                                                           0
2430 #define regGCEA_DRAM_RD_CLI2GRP_MAP1                                                                    0x17a1
2431 #define regGCEA_DRAM_RD_CLI2GRP_MAP1_BASE_IDX                                                           0
2432 #define regGCEA_DRAM_WR_CLI2GRP_MAP0                                                                    0x17a2
2433 #define regGCEA_DRAM_WR_CLI2GRP_MAP0_BASE_IDX                                                           0
2434 #define regGCEA_DRAM_WR_CLI2GRP_MAP1                                                                    0x17a3
2435 #define regGCEA_DRAM_WR_CLI2GRP_MAP1_BASE_IDX                                                           0
2436 #define regGCEA_DRAM_RD_GRP2VC_MAP                                                                      0x17a4
2437 #define regGCEA_DRAM_RD_GRP2VC_MAP_BASE_IDX                                                             0
2438 #define regGCEA_DRAM_WR_GRP2VC_MAP                                                                      0x17a5
2439 #define regGCEA_DRAM_WR_GRP2VC_MAP_BASE_IDX                                                             0
2440 #define regGCEA_DRAM_RD_LAZY                                                                            0x17a6
2441 #define regGCEA_DRAM_RD_LAZY_BASE_IDX                                                                   0
2442 #define regGCEA_DRAM_WR_LAZY                                                                            0x17a7
2443 #define regGCEA_DRAM_WR_LAZY_BASE_IDX                                                                   0
2444 #define regGCEA_DRAM_RD_CAM_CNTL                                                                        0x17a8
2445 #define regGCEA_DRAM_RD_CAM_CNTL_BASE_IDX                                                               0
2446 #define regGCEA_DRAM_WR_CAM_CNTL                                                                        0x17a9
2447 #define regGCEA_DRAM_WR_CAM_CNTL_BASE_IDX                                                               0
2448 #define regGCEA_DRAM_PAGE_BURST                                                                         0x17aa
2449 #define regGCEA_DRAM_PAGE_BURST_BASE_IDX                                                                0
2450 #define regGCEA_DRAM_RD_PRI_AGE                                                                         0x17ab
2451 #define regGCEA_DRAM_RD_PRI_AGE_BASE_IDX                                                                0
2452 #define regGCEA_DRAM_WR_PRI_AGE                                                                         0x17ac
2453 #define regGCEA_DRAM_WR_PRI_AGE_BASE_IDX                                                                0
2454 #define regGCEA_DRAM_RD_PRI_QUEUING                                                                     0x17ad
2455 #define regGCEA_DRAM_RD_PRI_QUEUING_BASE_IDX                                                            0
2456 #define regGCEA_DRAM_WR_PRI_QUEUING                                                                     0x17ae
2457 #define regGCEA_DRAM_WR_PRI_QUEUING_BASE_IDX                                                            0
2458 #define regGCEA_DRAM_RD_PRI_FIXED                                                                       0x17af
2459 #define regGCEA_DRAM_RD_PRI_FIXED_BASE_IDX                                                              0
2460 #define regGCEA_DRAM_WR_PRI_FIXED                                                                       0x17b0
2461 #define regGCEA_DRAM_WR_PRI_FIXED_BASE_IDX                                                              0
2462 #define regGCEA_DRAM_RD_PRI_URGENCY                                                                     0x17b1
2463 #define regGCEA_DRAM_RD_PRI_URGENCY_BASE_IDX                                                            0
2464 #define regGCEA_DRAM_WR_PRI_URGENCY                                                                     0x17b2
2465 #define regGCEA_DRAM_WR_PRI_URGENCY_BASE_IDX                                                            0
2466 #define regGCEA_DRAM_RD_PRI_QUANT_PRI1                                                                  0x17b3
2467 #define regGCEA_DRAM_RD_PRI_QUANT_PRI1_BASE_IDX                                                         0
2468 #define regGCEA_DRAM_RD_PRI_QUANT_PRI2                                                                  0x17b4
2469 #define regGCEA_DRAM_RD_PRI_QUANT_PRI2_BASE_IDX                                                         0
2470 #define regGCEA_DRAM_RD_PRI_QUANT_PRI3                                                                  0x17b5
2471 #define regGCEA_DRAM_RD_PRI_QUANT_PRI3_BASE_IDX                                                         0
2472 #define regGCEA_DRAM_WR_PRI_QUANT_PRI1                                                                  0x17b6
2473 #define regGCEA_DRAM_WR_PRI_QUANT_PRI1_BASE_IDX                                                         0
2474 #define regGCEA_DRAM_WR_PRI_QUANT_PRI2                                                                  0x17b7
2475 #define regGCEA_DRAM_WR_PRI_QUANT_PRI2_BASE_IDX                                                         0
2476 #define regGCEA_DRAM_WR_PRI_QUANT_PRI3                                                                  0x17b8
2477 #define regGCEA_DRAM_WR_PRI_QUANT_PRI3_BASE_IDX                                                         0
2478 #define regGCEA_IO_RD_CLI2GRP_MAP0                                                                      0x187d
2479 #define regGCEA_IO_RD_CLI2GRP_MAP0_BASE_IDX                                                             0
2480 #define regGCEA_IO_RD_CLI2GRP_MAP1                                                                      0x187e
2481 #define regGCEA_IO_RD_CLI2GRP_MAP1_BASE_IDX                                                             0
2482 #define regGCEA_IO_WR_CLI2GRP_MAP0                                                                      0x187f
2483 #define regGCEA_IO_WR_CLI2GRP_MAP0_BASE_IDX                                                             0
2484 #define regGCEA_IO_WR_CLI2GRP_MAP1                                                                      0x1880
2485 #define regGCEA_IO_WR_CLI2GRP_MAP1_BASE_IDX                                                             0
2486 #define regGCEA_IO_RD_COMBINE_FLUSH                                                                     0x1881
2487 #define regGCEA_IO_RD_COMBINE_FLUSH_BASE_IDX                                                            0
2488 #define regGCEA_IO_WR_COMBINE_FLUSH                                                                     0x1882
2489 #define regGCEA_IO_WR_COMBINE_FLUSH_BASE_IDX                                                            0
2490 #define regGCEA_IO_GROUP_BURST                                                                          0x1883
2491 #define regGCEA_IO_GROUP_BURST_BASE_IDX                                                                 0
2492 #define regGCEA_IO_RD_PRI_AGE                                                                           0x1884
2493 #define regGCEA_IO_RD_PRI_AGE_BASE_IDX                                                                  0
2494 #define regGCEA_IO_WR_PRI_AGE                                                                           0x1885
2495 #define regGCEA_IO_WR_PRI_AGE_BASE_IDX                                                                  0
2496 #define regGCEA_IO_RD_PRI_QUEUING                                                                       0x1886
2497 #define regGCEA_IO_RD_PRI_QUEUING_BASE_IDX                                                              0
2498 #define regGCEA_IO_WR_PRI_QUEUING                                                                       0x1887
2499 #define regGCEA_IO_WR_PRI_QUEUING_BASE_IDX                                                              0
2500 #define regGCEA_IO_RD_PRI_FIXED                                                                         0x1888
2501 #define regGCEA_IO_RD_PRI_FIXED_BASE_IDX                                                                0
2502 #define regGCEA_IO_WR_PRI_FIXED                                                                         0x1889
2503 #define regGCEA_IO_WR_PRI_FIXED_BASE_IDX                                                                0
2504 #define regGCEA_IO_RD_PRI_URGENCY                                                                       0x188a
2505 #define regGCEA_IO_RD_PRI_URGENCY_BASE_IDX                                                              0
2506 #define regGCEA_IO_WR_PRI_URGENCY                                                                       0x188b
2507 #define regGCEA_IO_WR_PRI_URGENCY_BASE_IDX                                                              0
2508 #define regGCEA_IO_RD_PRI_URGENCY_MASKING                                                               0x188c
2509 #define regGCEA_IO_RD_PRI_URGENCY_MASKING_BASE_IDX                                                      0
2510 #define regGCEA_IO_WR_PRI_URGENCY_MASKING                                                               0x188d
2511 #define regGCEA_IO_WR_PRI_URGENCY_MASKING_BASE_IDX                                                      0
2512 #define regGCEA_IO_RD_PRI_QUANT_PRI1                                                                    0x188e
2513 #define regGCEA_IO_RD_PRI_QUANT_PRI1_BASE_IDX                                                           0
2514 #define regGCEA_IO_RD_PRI_QUANT_PRI2                                                                    0x188f
2515 #define regGCEA_IO_RD_PRI_QUANT_PRI2_BASE_IDX                                                           0
2516 #define regGCEA_IO_RD_PRI_QUANT_PRI3                                                                    0x1890
2517 #define regGCEA_IO_RD_PRI_QUANT_PRI3_BASE_IDX                                                           0
2518 #define regGCEA_IO_WR_PRI_QUANT_PRI1                                                                    0x1891
2519 #define regGCEA_IO_WR_PRI_QUANT_PRI1_BASE_IDX                                                           0
2520 #define regGCEA_IO_WR_PRI_QUANT_PRI2                                                                    0x1892
2521 #define regGCEA_IO_WR_PRI_QUANT_PRI2_BASE_IDX                                                           0
2522 #define regGCEA_IO_WR_PRI_QUANT_PRI3                                                                    0x1893
2523 #define regGCEA_IO_WR_PRI_QUANT_PRI3_BASE_IDX                                                           0
2524 #define regGCEA_SDP_ARB_FINAL                                                                           0x1896
2525 #define regGCEA_SDP_ARB_FINAL_BASE_IDX                                                                  0
2526 #define regGCEA_SDP_IO_PRIORITY                                                                         0x1899
2527 #define regGCEA_SDP_IO_PRIORITY_BASE_IDX                                                                0
2528 #define regGCEA_SDP_CREDITS                                                                             0x189a
2529 #define regGCEA_SDP_CREDITS_BASE_IDX                                                                    0
2530 #define regGCEA_SDP_TAG_RESERVE0                                                                        0x189b
2531 #define regGCEA_SDP_TAG_RESERVE0_BASE_IDX                                                               0
2532 #define regGCEA_SDP_TAG_RESERVE1                                                                        0x189c
2533 #define regGCEA_SDP_TAG_RESERVE1_BASE_IDX                                                               0
2534 #define regGCEA_SDP_VCC_RESERVE0                                                                        0x189d
2535 #define regGCEA_SDP_VCC_RESERVE0_BASE_IDX                                                               0
2536 #define regGCEA_SDP_VCC_RESERVE1                                                                        0x189e
2537 #define regGCEA_SDP_VCC_RESERVE1_BASE_IDX                                                               0
2538 
2539 
2540 // addressBlock: gc_gceadec2
2541 // base address: 0x9c00
2542 #define regGCEA_MISC                                                                                    0x14a2
2543 #define regGCEA_MISC_BASE_IDX                                                                           0
2544 #define regGCEA_LATENCY_SAMPLING                                                                        0x14a3
2545 #define regGCEA_LATENCY_SAMPLING_BASE_IDX                                                               0
2546 #define regGCEA_MAM_CTRL2                                                                               0x14a9
2547 #define regGCEA_MAM_CTRL2_BASE_IDX                                                                      0
2548 #define regGCEA_MAM_CTRL                                                                                0x14ab
2549 #define regGCEA_MAM_CTRL_BASE_IDX                                                                       0
2550 #define regGCEA_EDC_CNT                                                                                 0x14b2
2551 #define regGCEA_EDC_CNT_BASE_IDX                                                                        0
2552 #define regGCEA_EDC_CNT2                                                                                0x14b3
2553 #define regGCEA_EDC_CNT2_BASE_IDX                                                                       0
2554 #define regGCEA_DSM_CNTL                                                                                0x14b4
2555 #define regGCEA_DSM_CNTL_BASE_IDX                                                                       0
2556 #define regGCEA_DSM_CNTLA                                                                               0x14b5
2557 #define regGCEA_DSM_CNTLA_BASE_IDX                                                                      0
2558 #define regGCEA_DSM_CNTLB                                                                               0x14b6
2559 #define regGCEA_DSM_CNTLB_BASE_IDX                                                                      0
2560 #define regGCEA_DSM_CNTL2                                                                               0x14b7
2561 #define regGCEA_DSM_CNTL2_BASE_IDX                                                                      0
2562 #define regGCEA_DSM_CNTL2A                                                                              0x14b8
2563 #define regGCEA_DSM_CNTL2A_BASE_IDX                                                                     0
2564 #define regGCEA_DSM_CNTL2B                                                                              0x14b9
2565 #define regGCEA_DSM_CNTL2B_BASE_IDX                                                                     0
2566 #define regGCEA_GL2C_XBR_CREDITS                                                                        0x14ba
2567 #define regGCEA_GL2C_XBR_CREDITS_BASE_IDX                                                               0
2568 #define regGCEA_GL2C_XBR_MAXBURST                                                                       0x14bb
2569 #define regGCEA_GL2C_XBR_MAXBURST_BASE_IDX                                                              0
2570 #define regGCEA_PROBE_CNTL                                                                              0x14bc
2571 #define regGCEA_PROBE_CNTL_BASE_IDX                                                                     0
2572 #define regGCEA_PROBE_MAP                                                                               0x14bd
2573 #define regGCEA_PROBE_MAP_BASE_IDX                                                                      0
2574 #define regGCEA_ERR_STATUS                                                                              0x14be
2575 #define regGCEA_ERR_STATUS_BASE_IDX                                                                     0
2576 #define regGCEA_MISC2                                                                                   0x14bf
2577 #define regGCEA_MISC2_BASE_IDX                                                                          0
2578 
2579 
2580 // addressBlock: gc_gceadec3
2581 // base address: 0x9dc0
2582 #define regGCEA_RRET_MEM_RESERVE                                                                        0x1518
2583 #define regGCEA_RRET_MEM_RESERVE_BASE_IDX                                                               0
2584 #define regGCEA_EDC_CNT3                                                                                0x151a
2585 #define regGCEA_EDC_CNT3_BASE_IDX                                                                       0
2586 #define regGCEA_SDP_ENABLE                                                                              0x151e
2587 #define regGCEA_SDP_ENABLE_BASE_IDX                                                                     0
2588 
2589 
2590 // addressBlock: gc_spipdec2
2591 // base address: 0x9c80
2592 #define regSPI_PQEV_CTRL                                                                                0x14c0
2593 #define regSPI_PQEV_CTRL_BASE_IDX                                                                       0
2594 #define regSPI_EXP_THROTTLE_CTRL                                                                        0x14c3
2595 #define regSPI_EXP_THROTTLE_CTRL_BASE_IDX                                                               0
2596 
2597 
2598 // addressBlock: gc_rmi_rmidec
2599 // base address: 0x2e200
2600 #define regRMI_GENERAL_CNTL                                                                             0x1880
2601 #define regRMI_GENERAL_CNTL_BASE_IDX                                                                    1
2602 #define regRMI_GENERAL_CNTL1                                                                            0x1881
2603 #define regRMI_GENERAL_CNTL1_BASE_IDX                                                                   1
2604 #define regRMI_GENERAL_STATUS                                                                           0x1882
2605 #define regRMI_GENERAL_STATUS_BASE_IDX                                                                  1
2606 #define regRMI_SUBBLOCK_STATUS0                                                                         0x1883
2607 #define regRMI_SUBBLOCK_STATUS0_BASE_IDX                                                                1
2608 #define regRMI_SUBBLOCK_STATUS1                                                                         0x1884
2609 #define regRMI_SUBBLOCK_STATUS1_BASE_IDX                                                                1
2610 #define regRMI_SUBBLOCK_STATUS2                                                                         0x1885
2611 #define regRMI_SUBBLOCK_STATUS2_BASE_IDX                                                                1
2612 #define regRMI_SUBBLOCK_STATUS3                                                                         0x1886
2613 #define regRMI_SUBBLOCK_STATUS3_BASE_IDX                                                                1
2614 #define regRMI_XBAR_CONFIG                                                                              0x1887
2615 #define regRMI_XBAR_CONFIG_BASE_IDX                                                                     1
2616 #define regRMI_PROBE_POP_LOGIC_CNTL                                                                     0x1888
2617 #define regRMI_PROBE_POP_LOGIC_CNTL_BASE_IDX                                                            1
2618 #define regRMI_UTC_XNACK_N_MISC_CNTL                                                                    0x1889
2619 #define regRMI_UTC_XNACK_N_MISC_CNTL_BASE_IDX                                                           1
2620 #define regRMI_DEMUX_CNTL                                                                               0x188a
2621 #define regRMI_DEMUX_CNTL_BASE_IDX                                                                      1
2622 #define regRMI_UTCL1_CNTL1                                                                              0x188b
2623 #define regRMI_UTCL1_CNTL1_BASE_IDX                                                                     1
2624 #define regRMI_UTCL1_CNTL2                                                                              0x188c
2625 #define regRMI_UTCL1_CNTL2_BASE_IDX                                                                     1
2626 #define regRMI_UTC_UNIT_CONFIG                                                                          0x188d
2627 #define regRMI_UTC_UNIT_CONFIG_BASE_IDX                                                                 1
2628 #define regRMI_TCIW_FORMATTER0_CNTL                                                                     0x188e
2629 #define regRMI_TCIW_FORMATTER0_CNTL_BASE_IDX                                                            1
2630 #define regRMI_TCIW_FORMATTER1_CNTL                                                                     0x188f
2631 #define regRMI_TCIW_FORMATTER1_CNTL_BASE_IDX                                                            1
2632 #define regRMI_SCOREBOARD_CNTL                                                                          0x1890
2633 #define regRMI_SCOREBOARD_CNTL_BASE_IDX                                                                 1
2634 #define regRMI_SCOREBOARD_STATUS0                                                                       0x1891
2635 #define regRMI_SCOREBOARD_STATUS0_BASE_IDX                                                              1
2636 #define regRMI_SCOREBOARD_STATUS1                                                                       0x1892
2637 #define regRMI_SCOREBOARD_STATUS1_BASE_IDX                                                              1
2638 #define regRMI_SCOREBOARD_STATUS2                                                                       0x1893
2639 #define regRMI_SCOREBOARD_STATUS2_BASE_IDX                                                              1
2640 #define regRMI_XBAR_ARBITER_CONFIG                                                                      0x1894
2641 #define regRMI_XBAR_ARBITER_CONFIG_BASE_IDX                                                             1
2642 #define regRMI_XBAR_ARBITER_CONFIG_1                                                                    0x1895
2643 #define regRMI_XBAR_ARBITER_CONFIG_1_BASE_IDX                                                           1
2644 #define regRMI_CLOCK_CNTRL                                                                              0x1896
2645 #define regRMI_CLOCK_CNTRL_BASE_IDX                                                                     1
2646 #define regRMI_UTCL1_STATUS                                                                             0x1897
2647 #define regRMI_UTCL1_STATUS_BASE_IDX                                                                    1
2648 #define regRMI_RB_GLX_CID_MAP                                                                           0x1898
2649 #define regRMI_RB_GLX_CID_MAP_BASE_IDX                                                                  1
2650 #define regRMI_SPARE                                                                                    0x189f
2651 #define regRMI_SPARE_BASE_IDX                                                                           1
2652 #define regRMI_SPARE_1                                                                                  0x18a0
2653 #define regRMI_SPARE_1_BASE_IDX                                                                         1
2654 #define regRMI_SPARE_2                                                                                  0x18a1
2655 #define regRMI_SPARE_2_BASE_IDX                                                                         1
2656 #define regCC_RMI_REDUNDANCY                                                                            0x18a2
2657 #define regCC_RMI_REDUNDANCY_BASE_IDX                                                                   1
2658 
2659 
2660 // addressBlock: gc_pmmdec
2661 // base address: 0x9f80
2662 #define regGCR_PIO_CNTL                                                                                 0x1580
2663 #define regGCR_PIO_CNTL_BASE_IDX                                                                        0
2664 #define regGCR_PIO_DATA                                                                                 0x1581
2665 #define regGCR_PIO_DATA_BASE_IDX                                                                        0
2666 #define regPMM_CNTL                                                                                     0x1582
2667 #define regPMM_CNTL_BASE_IDX                                                                            0
2668 #define regPMM_STATUS                                                                                   0x1583
2669 #define regPMM_STATUS_BASE_IDX                                                                          0
2670 
2671 
2672 // addressBlock: gc_utcl1dec
2673 // base address: 0x9fb0
2674 #define regUTCL1_CTRL_1                                                                                 0x158c
2675 #define regUTCL1_CTRL_1_BASE_IDX                                                                        0
2676 #define regUTCL1_ALOG                                                                                   0x158f
2677 #define regUTCL1_ALOG_BASE_IDX                                                                          0
2678 #define regUTCL1_STATUS                                                                                 0x1594
2679 #define regUTCL1_STATUS_BASE_IDX                                                                        0
2680 
2681 
2682 // addressBlock: gc_gcvmsharedpfdec
2683 // base address: 0xa000
2684 #define regGCMC_VM_NB_TOP_OF_DRAM_SLOT1                                                                 0x15a4
2685 #define regGCMC_VM_NB_TOP_OF_DRAM_SLOT1_BASE_IDX                                                        0
2686 #define regGCMC_VM_NB_LOWER_TOP_OF_DRAM2                                                                0x15a5
2687 #define regGCMC_VM_NB_LOWER_TOP_OF_DRAM2_BASE_IDX                                                       0
2688 #define regGCMC_VM_NB_UPPER_TOP_OF_DRAM2                                                                0x15a6
2689 #define regGCMC_VM_NB_UPPER_TOP_OF_DRAM2_BASE_IDX                                                       0
2690 #define regGCMC_VM_FB_OFFSET                                                                            0x15a7
2691 #define regGCMC_VM_FB_OFFSET_BASE_IDX                                                                   0
2692 #define regGCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB                                                     0x15a8
2693 #define regGCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB_BASE_IDX                                            0
2694 #define regGCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB                                                     0x15a9
2695 #define regGCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB_BASE_IDX                                            0
2696 #define regGCMC_VM_STEERING                                                                             0x15aa
2697 #define regGCMC_VM_STEERING_BASE_IDX                                                                    0
2698 #define regGCMC_MEM_POWER_LS                                                                            0x15ac
2699 #define regGCMC_MEM_POWER_LS_BASE_IDX                                                                   0
2700 #define regGCMC_VM_CACHEABLE_DRAM_ADDRESS_START                                                         0x15ad
2701 #define regGCMC_VM_CACHEABLE_DRAM_ADDRESS_START_BASE_IDX                                                0
2702 #define regGCMC_VM_CACHEABLE_DRAM_ADDRESS_END                                                           0x15ae
2703 #define regGCMC_VM_CACHEABLE_DRAM_ADDRESS_END_BASE_IDX                                                  0
2704 #define regGCMC_VM_LOCAL_SYSMEM_ADDRESS_START                                                           0x15af
2705 #define regGCMC_VM_LOCAL_SYSMEM_ADDRESS_START_BASE_IDX                                                  0
2706 #define regGCMC_VM_LOCAL_SYSMEM_ADDRESS_END                                                             0x15b0
2707 #define regGCMC_VM_LOCAL_SYSMEM_ADDRESS_END_BASE_IDX                                                    0
2708 #define regGCMC_VM_APT_CNTL                                                                             0x15b1
2709 #define regGCMC_VM_APT_CNTL_BASE_IDX                                                                    0
2710 #define regGCMC_VM_LOCAL_FB_ADDRESS_START                                                               0x15b2
2711 #define regGCMC_VM_LOCAL_FB_ADDRESS_START_BASE_IDX                                                      0
2712 #define regGCMC_VM_LOCAL_FB_ADDRESS_END                                                                 0x15b3
2713 #define regGCMC_VM_LOCAL_FB_ADDRESS_END_BASE_IDX                                                        0
2714 #define regGCMC_VM_LOCAL_FB_ADDRESS_LOCK_CNTL                                                           0x15b4
2715 #define regGCMC_VM_LOCAL_FB_ADDRESS_LOCK_CNTL_BASE_IDX                                                  0
2716 #define regGCUTCL2_ICG_CTRL                                                                             0x15b5
2717 #define regGCUTCL2_ICG_CTRL_BASE_IDX                                                                    0
2718 #define regGCUTCL2_CGTT_BUSY_CTRL                                                                       0x15b7
2719 #define regGCUTCL2_CGTT_BUSY_CTRL_BASE_IDX                                                              0
2720 #define regGCMC_VM_FB_NOALLOC_CNTL                                                                      0x15b8
2721 #define regGCMC_VM_FB_NOALLOC_CNTL_BASE_IDX                                                             0
2722 #define regGCUTCL2_HARVEST_BYPASS_GROUPS                                                                0x15b9
2723 #define regGCUTCL2_HARVEST_BYPASS_GROUPS_BASE_IDX                                                       0
2724 #define regGCUTCL2_GROUP_RET_FAULT_STATUS                                                               0x15bb
2725 #define regGCUTCL2_GROUP_RET_FAULT_STATUS_BASE_IDX                                                      0
2726 
2727 
2728 // addressBlock: gc_gcvml2pfdec
2729 // base address: 0xa070
2730 #define regGCVM_L2_CNTL                                                                                 0x15bc
2731 #define regGCVM_L2_CNTL_BASE_IDX                                                                        0
2732 #define regGCVM_L2_CNTL2                                                                                0x15bd
2733 #define regGCVM_L2_CNTL2_BASE_IDX                                                                       0
2734 #define regGCVM_L2_CNTL3                                                                                0x15be
2735 #define regGCVM_L2_CNTL3_BASE_IDX                                                                       0
2736 #define regGCVM_L2_STATUS                                                                               0x15bf
2737 #define regGCVM_L2_STATUS_BASE_IDX                                                                      0
2738 #define regGCVM_DUMMY_PAGE_FAULT_CNTL                                                                   0x15c0
2739 #define regGCVM_DUMMY_PAGE_FAULT_CNTL_BASE_IDX                                                          0
2740 #define regGCVM_DUMMY_PAGE_FAULT_ADDR_LO32                                                              0x15c1
2741 #define regGCVM_DUMMY_PAGE_FAULT_ADDR_LO32_BASE_IDX                                                     0
2742 #define regGCVM_DUMMY_PAGE_FAULT_ADDR_HI32                                                              0x15c2
2743 #define regGCVM_DUMMY_PAGE_FAULT_ADDR_HI32_BASE_IDX                                                     0
2744 #define regGCVM_INVALIDATE_CNTL                                                                         0x15c3
2745 #define regGCVM_INVALIDATE_CNTL_BASE_IDX                                                                0
2746 #define regGCVM_L2_PROTECTION_FAULT_CNTL                                                                0x15c4
2747 #define regGCVM_L2_PROTECTION_FAULT_CNTL_BASE_IDX                                                       0
2748 #define regGCVM_L2_PROTECTION_FAULT_CNTL2                                                               0x15c5
2749 #define regGCVM_L2_PROTECTION_FAULT_CNTL2_BASE_IDX                                                      0
2750 #define regGCVM_L2_PROTECTION_FAULT_MM_CNTL3                                                            0x15c6
2751 #define regGCVM_L2_PROTECTION_FAULT_MM_CNTL3_BASE_IDX                                                   0
2752 #define regGCVM_L2_PROTECTION_FAULT_MM_CNTL4                                                            0x15c7
2753 #define regGCVM_L2_PROTECTION_FAULT_MM_CNTL4_BASE_IDX                                                   0
2754 #define regGCVM_L2_PROTECTION_FAULT_STATUS                                                              0x15c8
2755 #define regGCVM_L2_PROTECTION_FAULT_STATUS_BASE_IDX                                                     0
2756 #define regGCVM_L2_PROTECTION_FAULT_ADDR_LO32                                                           0x15c9
2757 #define regGCVM_L2_PROTECTION_FAULT_ADDR_LO32_BASE_IDX                                                  0
2758 #define regGCVM_L2_PROTECTION_FAULT_ADDR_HI32                                                           0x15ca
2759 #define regGCVM_L2_PROTECTION_FAULT_ADDR_HI32_BASE_IDX                                                  0
2760 #define regGCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32                                                   0x15cb
2761 #define regGCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32_BASE_IDX                                          0
2762 #define regGCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32                                                   0x15cc
2763 #define regGCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32_BASE_IDX                                          0
2764 #define regGCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32                                             0x15ce
2765 #define regGCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32_BASE_IDX                                    0
2766 #define regGCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32                                             0x15cf
2767 #define regGCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32_BASE_IDX                                    0
2768 #define regGCVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32                                            0x15d0
2769 #define regGCVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32_BASE_IDX                                   0
2770 #define regGCVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32                                            0x15d1
2771 #define regGCVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32_BASE_IDX                                   0
2772 #define regGCVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32                                                0x15d2
2773 #define regGCVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32_BASE_IDX                                       0
2774 #define regGCVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32                                                0x15d3
2775 #define regGCVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32_BASE_IDX                                       0
2776 #define regGCVM_L2_CNTL4                                                                                0x15d4
2777 #define regGCVM_L2_CNTL4_BASE_IDX                                                                       0
2778 #define regGCVM_L2_MM_GROUP_RT_CLASSES                                                                  0x15d5
2779 #define regGCVM_L2_MM_GROUP_RT_CLASSES_BASE_IDX                                                         0
2780 #define regGCVM_L2_BANK_SELECT_RESERVED_CID                                                             0x15d6
2781 #define regGCVM_L2_BANK_SELECT_RESERVED_CID_BASE_IDX                                                    0
2782 #define regGCVM_L2_BANK_SELECT_RESERVED_CID2                                                            0x15d7
2783 #define regGCVM_L2_BANK_SELECT_RESERVED_CID2_BASE_IDX                                                   0
2784 #define regGCVM_L2_CACHE_PARITY_CNTL                                                                    0x15d8
2785 #define regGCVM_L2_CACHE_PARITY_CNTL_BASE_IDX                                                           0
2786 #define regGCVM_L2_ICG_CTRL                                                                             0x15d9
2787 #define regGCVM_L2_ICG_CTRL_BASE_IDX                                                                    0
2788 #define regGCVM_L2_CNTL5                                                                                0x15da
2789 #define regGCVM_L2_CNTL5_BASE_IDX                                                                       0
2790 #define regGCVM_L2_GCR_CNTL                                                                             0x15db
2791 #define regGCVM_L2_GCR_CNTL_BASE_IDX                                                                    0
2792 #define regGCVML2_WALKER_MACRO_THROTTLE_TIME                                                            0x15dc
2793 #define regGCVML2_WALKER_MACRO_THROTTLE_TIME_BASE_IDX                                                   0
2794 #define regGCVML2_WALKER_MACRO_THROTTLE_FETCH_LIMIT                                                     0x15dd
2795 #define regGCVML2_WALKER_MACRO_THROTTLE_FETCH_LIMIT_BASE_IDX                                            0
2796 #define regGCVML2_WALKER_MICRO_THROTTLE_TIME                                                            0x15de
2797 #define regGCVML2_WALKER_MICRO_THROTTLE_TIME_BASE_IDX                                                   0
2798 #define regGCVML2_WALKER_MICRO_THROTTLE_FETCH_LIMIT                                                     0x15df
2799 #define regGCVML2_WALKER_MICRO_THROTTLE_FETCH_LIMIT_BASE_IDX                                            0
2800 #define regGCVM_L2_CGTT_BUSY_CTRL                                                                       0x15e0
2801 #define regGCVM_L2_CGTT_BUSY_CTRL_BASE_IDX                                                              0
2802 #define regGCVM_L2_PTE_CACHE_DUMP_CNTL                                                                  0x15e1
2803 #define regGCVM_L2_PTE_CACHE_DUMP_CNTL_BASE_IDX                                                         0
2804 #define regGCVM_L2_PTE_CACHE_DUMP_READ                                                                  0x15e2
2805 #define regGCVM_L2_PTE_CACHE_DUMP_READ_BASE_IDX                                                         0
2806 #define regGCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_LO                                               0x15e5
2807 #define regGCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_LO_BASE_IDX                                      0
2808 #define regGCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI                                               0x15e6
2809 #define regGCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI_BASE_IDX                                      0
2810 #define regGCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_LO                                              0x15e7
2811 #define regGCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_LO_BASE_IDX                                     0
2812 #define regGCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI                                              0x15e8
2813 #define regGCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI_BASE_IDX                                     0
2814 #define regGCVM_L2_BANK_SELECT_MASKS                                                                    0x15e9
2815 #define regGCVM_L2_BANK_SELECT_MASKS_BASE_IDX                                                           0
2816 #define regGCUTCL2_CREDIT_SAFETY_GROUP_RET_CDC                                                          0x15ea
2817 #define regGCUTCL2_CREDIT_SAFETY_GROUP_RET_CDC_BASE_IDX                                                 0
2818 #define regGCUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_CDC                                               0x15eb
2819 #define regGCUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_CDC_BASE_IDX                                      0
2820 #define regGCUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_NOCDC                                             0x15ec
2821 #define regGCUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_NOCDC_BASE_IDX                                    0
2822 #define regGCVML2_CREDIT_SAFETY_IH_FAULT_INTERRUPT                                                      0x15ed
2823 #define regGCVML2_CREDIT_SAFETY_IH_FAULT_INTERRUPT_BASE_IDX                                             0
2824 #define regGCVML2_WALKER_CREDIT_SAFETY_FETCH_RDREQ                                                      0x15ee
2825 #define regGCVML2_WALKER_CREDIT_SAFETY_FETCH_RDREQ_BASE_IDX                                             0
2826 
2827 
2828 // addressBlock: gc_gcvmsharedvcdec
2829 // base address: 0xa360
2830 #define regGCMC_VM_FB_LOCATION_BASE                                                                     0x1678
2831 #define regGCMC_VM_FB_LOCATION_BASE_BASE_IDX                                                            0
2832 #define regGCMC_VM_FB_LOCATION_TOP                                                                      0x1679
2833 #define regGCMC_VM_FB_LOCATION_TOP_BASE_IDX                                                             0
2834 #define regGCMC_VM_AGP_TOP                                                                              0x167a
2835 #define regGCMC_VM_AGP_TOP_BASE_IDX                                                                     0
2836 #define regGCMC_VM_AGP_BOT                                                                              0x167b
2837 #define regGCMC_VM_AGP_BOT_BASE_IDX                                                                     0
2838 #define regGCMC_VM_AGP_BASE                                                                             0x167c
2839 #define regGCMC_VM_AGP_BASE_BASE_IDX                                                                    0
2840 #define regGCMC_VM_SYSTEM_APERTURE_LOW_ADDR                                                             0x167d
2841 #define regGCMC_VM_SYSTEM_APERTURE_LOW_ADDR_BASE_IDX                                                    0
2842 #define regGCMC_VM_SYSTEM_APERTURE_HIGH_ADDR                                                            0x167e
2843 #define regGCMC_VM_SYSTEM_APERTURE_HIGH_ADDR_BASE_IDX                                                   0
2844 #define regGCMC_VM_MX_L1_TLB_CNTL                                                                       0x167f
2845 #define regGCMC_VM_MX_L1_TLB_CNTL_BASE_IDX                                                              0
2846 
2847 
2848 // addressBlock: gc_gcvml2vcdec
2849 // base address: 0xa3a0
2850 #define regGCVM_CONTEXT0_CNTL                                                                           0x1688
2851 #define regGCVM_CONTEXT0_CNTL_BASE_IDX                                                                  0
2852 #define regGCVM_CONTEXT1_CNTL                                                                           0x1689
2853 #define regGCVM_CONTEXT1_CNTL_BASE_IDX                                                                  0
2854 #define regGCVM_CONTEXT2_CNTL                                                                           0x168a
2855 #define regGCVM_CONTEXT2_CNTL_BASE_IDX                                                                  0
2856 #define regGCVM_CONTEXT3_CNTL                                                                           0x168b
2857 #define regGCVM_CONTEXT3_CNTL_BASE_IDX                                                                  0
2858 #define regGCVM_CONTEXT4_CNTL                                                                           0x168c
2859 #define regGCVM_CONTEXT4_CNTL_BASE_IDX                                                                  0
2860 #define regGCVM_CONTEXT5_CNTL                                                                           0x168d
2861 #define regGCVM_CONTEXT5_CNTL_BASE_IDX                                                                  0
2862 #define regGCVM_CONTEXT6_CNTL                                                                           0x168e
2863 #define regGCVM_CONTEXT6_CNTL_BASE_IDX                                                                  0
2864 #define regGCVM_CONTEXT7_CNTL                                                                           0x168f
2865 #define regGCVM_CONTEXT7_CNTL_BASE_IDX                                                                  0
2866 #define regGCVM_CONTEXT8_CNTL                                                                           0x1690
2867 #define regGCVM_CONTEXT8_CNTL_BASE_IDX                                                                  0
2868 #define regGCVM_CONTEXT9_CNTL                                                                           0x1691
2869 #define regGCVM_CONTEXT9_CNTL_BASE_IDX                                                                  0
2870 #define regGCVM_CONTEXT10_CNTL                                                                          0x1692
2871 #define regGCVM_CONTEXT10_CNTL_BASE_IDX                                                                 0
2872 #define regGCVM_CONTEXT11_CNTL                                                                          0x1693
2873 #define regGCVM_CONTEXT11_CNTL_BASE_IDX                                                                 0
2874 #define regGCVM_CONTEXT12_CNTL                                                                          0x1694
2875 #define regGCVM_CONTEXT12_CNTL_BASE_IDX                                                                 0
2876 #define regGCVM_CONTEXT13_CNTL                                                                          0x1695
2877 #define regGCVM_CONTEXT13_CNTL_BASE_IDX                                                                 0
2878 #define regGCVM_CONTEXT14_CNTL                                                                          0x1696
2879 #define regGCVM_CONTEXT14_CNTL_BASE_IDX                                                                 0
2880 #define regGCVM_CONTEXT15_CNTL                                                                          0x1697
2881 #define regGCVM_CONTEXT15_CNTL_BASE_IDX                                                                 0
2882 #define regGCVM_CONTEXTS_DISABLE                                                                        0x1698
2883 #define regGCVM_CONTEXTS_DISABLE_BASE_IDX                                                               0
2884 #define regGCVM_INVALIDATE_ENG0_SEM                                                                     0x1699
2885 #define regGCVM_INVALIDATE_ENG0_SEM_BASE_IDX                                                            0
2886 #define regGCVM_INVALIDATE_ENG1_SEM                                                                     0x169a
2887 #define regGCVM_INVALIDATE_ENG1_SEM_BASE_IDX                                                            0
2888 #define regGCVM_INVALIDATE_ENG2_SEM                                                                     0x169b
2889 #define regGCVM_INVALIDATE_ENG2_SEM_BASE_IDX                                                            0
2890 #define regGCVM_INVALIDATE_ENG3_SEM                                                                     0x169c
2891 #define regGCVM_INVALIDATE_ENG3_SEM_BASE_IDX                                                            0
2892 #define regGCVM_INVALIDATE_ENG4_SEM                                                                     0x169d
2893 #define regGCVM_INVALIDATE_ENG4_SEM_BASE_IDX                                                            0
2894 #define regGCVM_INVALIDATE_ENG5_SEM                                                                     0x169e
2895 #define regGCVM_INVALIDATE_ENG5_SEM_BASE_IDX                                                            0
2896 #define regGCVM_INVALIDATE_ENG6_SEM                                                                     0x169f
2897 #define regGCVM_INVALIDATE_ENG6_SEM_BASE_IDX                                                            0
2898 #define regGCVM_INVALIDATE_ENG7_SEM                                                                     0x16a0
2899 #define regGCVM_INVALIDATE_ENG7_SEM_BASE_IDX                                                            0
2900 #define regGCVM_INVALIDATE_ENG8_SEM                                                                     0x16a1
2901 #define regGCVM_INVALIDATE_ENG8_SEM_BASE_IDX                                                            0
2902 #define regGCVM_INVALIDATE_ENG9_SEM                                                                     0x16a2
2903 #define regGCVM_INVALIDATE_ENG9_SEM_BASE_IDX                                                            0
2904 #define regGCVM_INVALIDATE_ENG10_SEM                                                                    0x16a3
2905 #define regGCVM_INVALIDATE_ENG10_SEM_BASE_IDX                                                           0
2906 #define regGCVM_INVALIDATE_ENG11_SEM                                                                    0x16a4
2907 #define regGCVM_INVALIDATE_ENG11_SEM_BASE_IDX                                                           0
2908 #define regGCVM_INVALIDATE_ENG12_SEM                                                                    0x16a5
2909 #define regGCVM_INVALIDATE_ENG12_SEM_BASE_IDX                                                           0
2910 #define regGCVM_INVALIDATE_ENG13_SEM                                                                    0x16a6
2911 #define regGCVM_INVALIDATE_ENG13_SEM_BASE_IDX                                                           0
2912 #define regGCVM_INVALIDATE_ENG14_SEM                                                                    0x16a7
2913 #define regGCVM_INVALIDATE_ENG14_SEM_BASE_IDX                                                           0
2914 #define regGCVM_INVALIDATE_ENG15_SEM                                                                    0x16a8
2915 #define regGCVM_INVALIDATE_ENG15_SEM_BASE_IDX                                                           0
2916 #define regGCVM_INVALIDATE_ENG16_SEM                                                                    0x16a9
2917 #define regGCVM_INVALIDATE_ENG16_SEM_BASE_IDX                                                           0
2918 #define regGCVM_INVALIDATE_ENG17_SEM                                                                    0x16aa
2919 #define regGCVM_INVALIDATE_ENG17_SEM_BASE_IDX                                                           0
2920 #define regGCVM_INVALIDATE_ENG0_REQ                                                                     0x16ab
2921 #define regGCVM_INVALIDATE_ENG0_REQ_BASE_IDX                                                            0
2922 #define regGCVM_INVALIDATE_ENG1_REQ                                                                     0x16ac
2923 #define regGCVM_INVALIDATE_ENG1_REQ_BASE_IDX                                                            0
2924 #define regGCVM_INVALIDATE_ENG2_REQ                                                                     0x16ad
2925 #define regGCVM_INVALIDATE_ENG2_REQ_BASE_IDX                                                            0
2926 #define regGCVM_INVALIDATE_ENG3_REQ                                                                     0x16ae
2927 #define regGCVM_INVALIDATE_ENG3_REQ_BASE_IDX                                                            0
2928 #define regGCVM_INVALIDATE_ENG4_REQ                                                                     0x16af
2929 #define regGCVM_INVALIDATE_ENG4_REQ_BASE_IDX                                                            0
2930 #define regGCVM_INVALIDATE_ENG5_REQ                                                                     0x16b0
2931 #define regGCVM_INVALIDATE_ENG5_REQ_BASE_IDX                                                            0
2932 #define regGCVM_INVALIDATE_ENG6_REQ                                                                     0x16b1
2933 #define regGCVM_INVALIDATE_ENG6_REQ_BASE_IDX                                                            0
2934 #define regGCVM_INVALIDATE_ENG7_REQ                                                                     0x16b2
2935 #define regGCVM_INVALIDATE_ENG7_REQ_BASE_IDX                                                            0
2936 #define regGCVM_INVALIDATE_ENG8_REQ                                                                     0x16b3
2937 #define regGCVM_INVALIDATE_ENG8_REQ_BASE_IDX                                                            0
2938 #define regGCVM_INVALIDATE_ENG9_REQ                                                                     0x16b4
2939 #define regGCVM_INVALIDATE_ENG9_REQ_BASE_IDX                                                            0
2940 #define regGCVM_INVALIDATE_ENG10_REQ                                                                    0x16b5
2941 #define regGCVM_INVALIDATE_ENG10_REQ_BASE_IDX                                                           0
2942 #define regGCVM_INVALIDATE_ENG11_REQ                                                                    0x16b6
2943 #define regGCVM_INVALIDATE_ENG11_REQ_BASE_IDX                                                           0
2944 #define regGCVM_INVALIDATE_ENG12_REQ                                                                    0x16b7
2945 #define regGCVM_INVALIDATE_ENG12_REQ_BASE_IDX                                                           0
2946 #define regGCVM_INVALIDATE_ENG13_REQ                                                                    0x16b8
2947 #define regGCVM_INVALIDATE_ENG13_REQ_BASE_IDX                                                           0
2948 #define regGCVM_INVALIDATE_ENG14_REQ                                                                    0x16b9
2949 #define regGCVM_INVALIDATE_ENG14_REQ_BASE_IDX                                                           0
2950 #define regGCVM_INVALIDATE_ENG15_REQ                                                                    0x16ba
2951 #define regGCVM_INVALIDATE_ENG15_REQ_BASE_IDX                                                           0
2952 #define regGCVM_INVALIDATE_ENG16_REQ                                                                    0x16bb
2953 #define regGCVM_INVALIDATE_ENG16_REQ_BASE_IDX                                                           0
2954 #define regGCVM_INVALIDATE_ENG17_REQ                                                                    0x16bc
2955 #define regGCVM_INVALIDATE_ENG17_REQ_BASE_IDX                                                           0
2956 #define regGCVM_INVALIDATE_ENG0_ACK                                                                     0x16bd
2957 #define regGCVM_INVALIDATE_ENG0_ACK_BASE_IDX                                                            0
2958 #define regGCVM_INVALIDATE_ENG1_ACK                                                                     0x16be
2959 #define regGCVM_INVALIDATE_ENG1_ACK_BASE_IDX                                                            0
2960 #define regGCVM_INVALIDATE_ENG2_ACK                                                                     0x16bf
2961 #define regGCVM_INVALIDATE_ENG2_ACK_BASE_IDX                                                            0
2962 #define regGCVM_INVALIDATE_ENG3_ACK                                                                     0x16c0
2963 #define regGCVM_INVALIDATE_ENG3_ACK_BASE_IDX                                                            0
2964 #define regGCVM_INVALIDATE_ENG4_ACK                                                                     0x16c1
2965 #define regGCVM_INVALIDATE_ENG4_ACK_BASE_IDX                                                            0
2966 #define regGCVM_INVALIDATE_ENG5_ACK                                                                     0x16c2
2967 #define regGCVM_INVALIDATE_ENG5_ACK_BASE_IDX                                                            0
2968 #define regGCVM_INVALIDATE_ENG6_ACK                                                                     0x16c3
2969 #define regGCVM_INVALIDATE_ENG6_ACK_BASE_IDX                                                            0
2970 #define regGCVM_INVALIDATE_ENG7_ACK                                                                     0x16c4
2971 #define regGCVM_INVALIDATE_ENG7_ACK_BASE_IDX                                                            0
2972 #define regGCVM_INVALIDATE_ENG8_ACK                                                                     0x16c5
2973 #define regGCVM_INVALIDATE_ENG8_ACK_BASE_IDX                                                            0
2974 #define regGCVM_INVALIDATE_ENG9_ACK                                                                     0x16c6
2975 #define regGCVM_INVALIDATE_ENG9_ACK_BASE_IDX                                                            0
2976 #define regGCVM_INVALIDATE_ENG10_ACK                                                                    0x16c7
2977 #define regGCVM_INVALIDATE_ENG10_ACK_BASE_IDX                                                           0
2978 #define regGCVM_INVALIDATE_ENG11_ACK                                                                    0x16c8
2979 #define regGCVM_INVALIDATE_ENG11_ACK_BASE_IDX                                                           0
2980 #define regGCVM_INVALIDATE_ENG12_ACK                                                                    0x16c9
2981 #define regGCVM_INVALIDATE_ENG12_ACK_BASE_IDX                                                           0
2982 #define regGCVM_INVALIDATE_ENG13_ACK                                                                    0x16ca
2983 #define regGCVM_INVALIDATE_ENG13_ACK_BASE_IDX                                                           0
2984 #define regGCVM_INVALIDATE_ENG14_ACK                                                                    0x16cb
2985 #define regGCVM_INVALIDATE_ENG14_ACK_BASE_IDX                                                           0
2986 #define regGCVM_INVALIDATE_ENG15_ACK                                                                    0x16cc
2987 #define regGCVM_INVALIDATE_ENG15_ACK_BASE_IDX                                                           0
2988 #define regGCVM_INVALIDATE_ENG16_ACK                                                                    0x16cd
2989 #define regGCVM_INVALIDATE_ENG16_ACK_BASE_IDX                                                           0
2990 #define regGCVM_INVALIDATE_ENG17_ACK                                                                    0x16ce
2991 #define regGCVM_INVALIDATE_ENG17_ACK_BASE_IDX                                                           0
2992 #define regGCVM_INVALIDATE_ENG0_ADDR_RANGE_LO32                                                         0x16cf
2993 #define regGCVM_INVALIDATE_ENG0_ADDR_RANGE_LO32_BASE_IDX                                                0
2994 #define regGCVM_INVALIDATE_ENG0_ADDR_RANGE_HI32                                                         0x16d0
2995 #define regGCVM_INVALIDATE_ENG0_ADDR_RANGE_HI32_BASE_IDX                                                0
2996 #define regGCVM_INVALIDATE_ENG1_ADDR_RANGE_LO32                                                         0x16d1
2997 #define regGCVM_INVALIDATE_ENG1_ADDR_RANGE_LO32_BASE_IDX                                                0
2998 #define regGCVM_INVALIDATE_ENG1_ADDR_RANGE_HI32                                                         0x16d2
2999 #define regGCVM_INVALIDATE_ENG1_ADDR_RANGE_HI32_BASE_IDX                                                0
3000 #define regGCVM_INVALIDATE_ENG2_ADDR_RANGE_LO32                                                         0x16d3
3001 #define regGCVM_INVALIDATE_ENG2_ADDR_RANGE_LO32_BASE_IDX                                                0
3002 #define regGCVM_INVALIDATE_ENG2_ADDR_RANGE_HI32                                                         0x16d4
3003 #define regGCVM_INVALIDATE_ENG2_ADDR_RANGE_HI32_BASE_IDX                                                0
3004 #define regGCVM_INVALIDATE_ENG3_ADDR_RANGE_LO32                                                         0x16d5
3005 #define regGCVM_INVALIDATE_ENG3_ADDR_RANGE_LO32_BASE_IDX                                                0
3006 #define regGCVM_INVALIDATE_ENG3_ADDR_RANGE_HI32                                                         0x16d6
3007 #define regGCVM_INVALIDATE_ENG3_ADDR_RANGE_HI32_BASE_IDX                                                0
3008 #define regGCVM_INVALIDATE_ENG4_ADDR_RANGE_LO32                                                         0x16d7
3009 #define regGCVM_INVALIDATE_ENG4_ADDR_RANGE_LO32_BASE_IDX                                                0
3010 #define regGCVM_INVALIDATE_ENG4_ADDR_RANGE_HI32                                                         0x16d8
3011 #define regGCVM_INVALIDATE_ENG4_ADDR_RANGE_HI32_BASE_IDX                                                0
3012 #define regGCVM_INVALIDATE_ENG5_ADDR_RANGE_LO32                                                         0x16d9
3013 #define regGCVM_INVALIDATE_ENG5_ADDR_RANGE_LO32_BASE_IDX                                                0
3014 #define regGCVM_INVALIDATE_ENG5_ADDR_RANGE_HI32                                                         0x16da
3015 #define regGCVM_INVALIDATE_ENG5_ADDR_RANGE_HI32_BASE_IDX                                                0
3016 #define regGCVM_INVALIDATE_ENG6_ADDR_RANGE_LO32                                                         0x16db
3017 #define regGCVM_INVALIDATE_ENG6_ADDR_RANGE_LO32_BASE_IDX                                                0
3018 #define regGCVM_INVALIDATE_ENG6_ADDR_RANGE_HI32                                                         0x16dc
3019 #define regGCVM_INVALIDATE_ENG6_ADDR_RANGE_HI32_BASE_IDX                                                0
3020 #define regGCVM_INVALIDATE_ENG7_ADDR_RANGE_LO32                                                         0x16dd
3021 #define regGCVM_INVALIDATE_ENG7_ADDR_RANGE_LO32_BASE_IDX                                                0
3022 #define regGCVM_INVALIDATE_ENG7_ADDR_RANGE_HI32                                                         0x16de
3023 #define regGCVM_INVALIDATE_ENG7_ADDR_RANGE_HI32_BASE_IDX                                                0
3024 #define regGCVM_INVALIDATE_ENG8_ADDR_RANGE_LO32                                                         0x16df
3025 #define regGCVM_INVALIDATE_ENG8_ADDR_RANGE_LO32_BASE_IDX                                                0
3026 #define regGCVM_INVALIDATE_ENG8_ADDR_RANGE_HI32                                                         0x16e0
3027 #define regGCVM_INVALIDATE_ENG8_ADDR_RANGE_HI32_BASE_IDX                                                0
3028 #define regGCVM_INVALIDATE_ENG9_ADDR_RANGE_LO32                                                         0x16e1
3029 #define regGCVM_INVALIDATE_ENG9_ADDR_RANGE_LO32_BASE_IDX                                                0
3030 #define regGCVM_INVALIDATE_ENG9_ADDR_RANGE_HI32                                                         0x16e2
3031 #define regGCVM_INVALIDATE_ENG9_ADDR_RANGE_HI32_BASE_IDX                                                0
3032 #define regGCVM_INVALIDATE_ENG10_ADDR_RANGE_LO32                                                        0x16e3
3033 #define regGCVM_INVALIDATE_ENG10_ADDR_RANGE_LO32_BASE_IDX                                               0
3034 #define regGCVM_INVALIDATE_ENG10_ADDR_RANGE_HI32                                                        0x16e4
3035 #define regGCVM_INVALIDATE_ENG10_ADDR_RANGE_HI32_BASE_IDX                                               0
3036 #define regGCVM_INVALIDATE_ENG11_ADDR_RANGE_LO32                                                        0x16e5
3037 #define regGCVM_INVALIDATE_ENG11_ADDR_RANGE_LO32_BASE_IDX                                               0
3038 #define regGCVM_INVALIDATE_ENG11_ADDR_RANGE_HI32                                                        0x16e6
3039 #define regGCVM_INVALIDATE_ENG11_ADDR_RANGE_HI32_BASE_IDX                                               0
3040 #define regGCVM_INVALIDATE_ENG12_ADDR_RANGE_LO32                                                        0x16e7
3041 #define regGCVM_INVALIDATE_ENG12_ADDR_RANGE_LO32_BASE_IDX                                               0
3042 #define regGCVM_INVALIDATE_ENG12_ADDR_RANGE_HI32                                                        0x16e8
3043 #define regGCVM_INVALIDATE_ENG12_ADDR_RANGE_HI32_BASE_IDX                                               0
3044 #define regGCVM_INVALIDATE_ENG13_ADDR_RANGE_LO32                                                        0x16e9
3045 #define regGCVM_INVALIDATE_ENG13_ADDR_RANGE_LO32_BASE_IDX                                               0
3046 #define regGCVM_INVALIDATE_ENG13_ADDR_RANGE_HI32                                                        0x16ea
3047 #define regGCVM_INVALIDATE_ENG13_ADDR_RANGE_HI32_BASE_IDX                                               0
3048 #define regGCVM_INVALIDATE_ENG14_ADDR_RANGE_LO32                                                        0x16eb
3049 #define regGCVM_INVALIDATE_ENG14_ADDR_RANGE_LO32_BASE_IDX                                               0
3050 #define regGCVM_INVALIDATE_ENG14_ADDR_RANGE_HI32                                                        0x16ec
3051 #define regGCVM_INVALIDATE_ENG14_ADDR_RANGE_HI32_BASE_IDX                                               0
3052 #define regGCVM_INVALIDATE_ENG15_ADDR_RANGE_LO32                                                        0x16ed
3053 #define regGCVM_INVALIDATE_ENG15_ADDR_RANGE_LO32_BASE_IDX                                               0
3054 #define regGCVM_INVALIDATE_ENG15_ADDR_RANGE_HI32                                                        0x16ee
3055 #define regGCVM_INVALIDATE_ENG15_ADDR_RANGE_HI32_BASE_IDX                                               0
3056 #define regGCVM_INVALIDATE_ENG16_ADDR_RANGE_LO32                                                        0x16ef
3057 #define regGCVM_INVALIDATE_ENG16_ADDR_RANGE_LO32_BASE_IDX                                               0
3058 #define regGCVM_INVALIDATE_ENG16_ADDR_RANGE_HI32                                                        0x16f0
3059 #define regGCVM_INVALIDATE_ENG16_ADDR_RANGE_HI32_BASE_IDX                                               0
3060 #define regGCVM_INVALIDATE_ENG17_ADDR_RANGE_LO32                                                        0x16f1
3061 #define regGCVM_INVALIDATE_ENG17_ADDR_RANGE_LO32_BASE_IDX                                               0
3062 #define regGCVM_INVALIDATE_ENG17_ADDR_RANGE_HI32                                                        0x16f2
3063 #define regGCVM_INVALIDATE_ENG17_ADDR_RANGE_HI32_BASE_IDX                                               0
3064 #define regGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32                                                      0x16f3
3065 #define regGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                             0
3066 #define regGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32                                                      0x16f4
3067 #define regGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                             0
3068 #define regGCVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32                                                      0x16f5
3069 #define regGCVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                             0
3070 #define regGCVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32                                                      0x16f6
3071 #define regGCVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                             0
3072 #define regGCVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32                                                      0x16f7
3073 #define regGCVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                             0
3074 #define regGCVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32                                                      0x16f8
3075 #define regGCVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                             0
3076 #define regGCVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32                                                      0x16f9
3077 #define regGCVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                             0
3078 #define regGCVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32                                                      0x16fa
3079 #define regGCVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                             0
3080 #define regGCVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32                                                      0x16fb
3081 #define regGCVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                             0
3082 #define regGCVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32                                                      0x16fc
3083 #define regGCVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                             0
3084 #define regGCVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32                                                      0x16fd
3085 #define regGCVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                             0
3086 #define regGCVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32                                                      0x16fe
3087 #define regGCVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                             0
3088 #define regGCVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32                                                      0x16ff
3089 #define regGCVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                             0
3090 #define regGCVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32                                                      0x1700
3091 #define regGCVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                             0
3092 #define regGCVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32                                                      0x1701
3093 #define regGCVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                             0
3094 #define regGCVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32                                                      0x1702
3095 #define regGCVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                             0
3096 #define regGCVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32                                                      0x1703
3097 #define regGCVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                             0
3098 #define regGCVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32                                                      0x1704
3099 #define regGCVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                             0
3100 #define regGCVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32                                                      0x1705
3101 #define regGCVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                             0
3102 #define regGCVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32                                                      0x1706
3103 #define regGCVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                             0
3104 #define regGCVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32                                                     0x1707
3105 #define regGCVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                            0
3106 #define regGCVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32                                                     0x1708
3107 #define regGCVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                            0
3108 #define regGCVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32                                                     0x1709
3109 #define regGCVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                            0
3110 #define regGCVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32                                                     0x170a
3111 #define regGCVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                            0
3112 #define regGCVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32                                                     0x170b
3113 #define regGCVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                            0
3114 #define regGCVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32                                                     0x170c
3115 #define regGCVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                            0
3116 #define regGCVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32                                                     0x170d
3117 #define regGCVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                            0
3118 #define regGCVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32                                                     0x170e
3119 #define regGCVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                            0
3120 #define regGCVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32                                                     0x170f
3121 #define regGCVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                            0
3122 #define regGCVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32                                                     0x1710
3123 #define regGCVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                            0
3124 #define regGCVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32                                                     0x1711
3125 #define regGCVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                            0
3126 #define regGCVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32                                                     0x1712
3127 #define regGCVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                            0
3128 #define regGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32                                                     0x1713
3129 #define regGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                            0
3130 #define regGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32                                                     0x1714
3131 #define regGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                            0
3132 #define regGCVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32                                                     0x1715
3133 #define regGCVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                            0
3134 #define regGCVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32                                                     0x1716
3135 #define regGCVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                            0
3136 #define regGCVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32                                                     0x1717
3137 #define regGCVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                            0
3138 #define regGCVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32                                                     0x1718
3139 #define regGCVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                            0
3140 #define regGCVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32                                                     0x1719
3141 #define regGCVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                            0
3142 #define regGCVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32                                                     0x171a
3143 #define regGCVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                            0
3144 #define regGCVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32                                                     0x171b
3145 #define regGCVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                            0
3146 #define regGCVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32                                                     0x171c
3147 #define regGCVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                            0
3148 #define regGCVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32                                                     0x171d
3149 #define regGCVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                            0
3150 #define regGCVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32                                                     0x171e
3151 #define regGCVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                            0
3152 #define regGCVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32                                                     0x171f
3153 #define regGCVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                            0
3154 #define regGCVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32                                                     0x1720
3155 #define regGCVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                            0
3156 #define regGCVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32                                                     0x1721
3157 #define regGCVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                            0
3158 #define regGCVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32                                                     0x1722
3159 #define regGCVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                            0
3160 #define regGCVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32                                                     0x1723
3161 #define regGCVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                            0
3162 #define regGCVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32                                                     0x1724
3163 #define regGCVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                            0
3164 #define regGCVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32                                                     0x1725
3165 #define regGCVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                            0
3166 #define regGCVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32                                                     0x1726
3167 #define regGCVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                            0
3168 #define regGCVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32                                                    0x1727
3169 #define regGCVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                           0
3170 #define regGCVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32                                                    0x1728
3171 #define regGCVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                           0
3172 #define regGCVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32                                                    0x1729
3173 #define regGCVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                           0
3174 #define regGCVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32                                                    0x172a
3175 #define regGCVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                           0
3176 #define regGCVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32                                                    0x172b
3177 #define regGCVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                           0
3178 #define regGCVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32                                                    0x172c
3179 #define regGCVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                           0
3180 #define regGCVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32                                                    0x172d
3181 #define regGCVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                           0
3182 #define regGCVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32                                                    0x172e
3183 #define regGCVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                           0
3184 #define regGCVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32                                                    0x172f
3185 #define regGCVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                           0
3186 #define regGCVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32                                                    0x1730
3187 #define regGCVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                           0
3188 #define regGCVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32                                                    0x1731
3189 #define regGCVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                           0
3190 #define regGCVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32                                                    0x1732
3191 #define regGCVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                           0
3192 #define regGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32                                                       0x1733
3193 #define regGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                              0
3194 #define regGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32                                                       0x1734
3195 #define regGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                              0
3196 #define regGCVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32                                                       0x1735
3197 #define regGCVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                              0
3198 #define regGCVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32                                                       0x1736
3199 #define regGCVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                              0
3200 #define regGCVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32                                                       0x1737
3201 #define regGCVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                              0
3202 #define regGCVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32                                                       0x1738
3203 #define regGCVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                              0
3204 #define regGCVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32                                                       0x1739
3205 #define regGCVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                              0
3206 #define regGCVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32                                                       0x173a
3207 #define regGCVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                              0
3208 #define regGCVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32                                                       0x173b
3209 #define regGCVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                              0
3210 #define regGCVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32                                                       0x173c
3211 #define regGCVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                              0
3212 #define regGCVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32                                                       0x173d
3213 #define regGCVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                              0
3214 #define regGCVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32                                                       0x173e
3215 #define regGCVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                              0
3216 #define regGCVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32                                                       0x173f
3217 #define regGCVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                              0
3218 #define regGCVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32                                                       0x1740
3219 #define regGCVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                              0
3220 #define regGCVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32                                                       0x1741
3221 #define regGCVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                              0
3222 #define regGCVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32                                                       0x1742
3223 #define regGCVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                              0
3224 #define regGCVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32                                                       0x1743
3225 #define regGCVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                              0
3226 #define regGCVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32                                                       0x1744
3227 #define regGCVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                              0
3228 #define regGCVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32                                                       0x1745
3229 #define regGCVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                              0
3230 #define regGCVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32                                                       0x1746
3231 #define regGCVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                              0
3232 #define regGCVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32                                                      0x1747
3233 #define regGCVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                             0
3234 #define regGCVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32                                                      0x1748
3235 #define regGCVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                             0
3236 #define regGCVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32                                                      0x1749
3237 #define regGCVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                             0
3238 #define regGCVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32                                                      0x174a
3239 #define regGCVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                             0
3240 #define regGCVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32                                                      0x174b
3241 #define regGCVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                             0
3242 #define regGCVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32                                                      0x174c
3243 #define regGCVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                             0
3244 #define regGCVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32                                                      0x174d
3245 #define regGCVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                             0
3246 #define regGCVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32                                                      0x174e
3247 #define regGCVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                             0
3248 #define regGCVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32                                                      0x174f
3249 #define regGCVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                             0
3250 #define regGCVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32                                                      0x1750
3251 #define regGCVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                             0
3252 #define regGCVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32                                                      0x1751
3253 #define regGCVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                             0
3254 #define regGCVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32                                                      0x1752
3255 #define regGCVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                             0
3256 #define regGCVM_L2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES                                                    0x1753
3257 #define regGCVM_L2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX                                           0
3258 #define regGCVM_L2_CONTEXT0_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES                                           0x1754
3259 #define regGCVM_L2_CONTEXT0_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX                                  0
3260 #define regGCVM_L2_CONTEXT1_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES                                           0x1755
3261 #define regGCVM_L2_CONTEXT1_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX                                  0
3262 #define regGCVM_L2_CONTEXT2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES                                           0x1756
3263 #define regGCVM_L2_CONTEXT2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX                                  0
3264 #define regGCVM_L2_CONTEXT3_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES                                           0x1757
3265 #define regGCVM_L2_CONTEXT3_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX                                  0
3266 #define regGCVM_L2_CONTEXT4_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES                                           0x1758
3267 #define regGCVM_L2_CONTEXT4_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX                                  0
3268 #define regGCVM_L2_CONTEXT5_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES                                           0x1759
3269 #define regGCVM_L2_CONTEXT5_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX                                  0
3270 #define regGCVM_L2_CONTEXT6_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES                                           0x175a
3271 #define regGCVM_L2_CONTEXT6_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX                                  0
3272 #define regGCVM_L2_CONTEXT7_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES                                           0x175b
3273 #define regGCVM_L2_CONTEXT7_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX                                  0
3274 #define regGCVM_L2_CONTEXT8_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES                                           0x175c
3275 #define regGCVM_L2_CONTEXT8_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX                                  0
3276 #define regGCVM_L2_CONTEXT9_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES                                           0x175d
3277 #define regGCVM_L2_CONTEXT9_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX                                  0
3278 #define regGCVM_L2_CONTEXT10_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES                                          0x175e
3279 #define regGCVM_L2_CONTEXT10_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX                                 0
3280 #define regGCVM_L2_CONTEXT11_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES                                          0x175f
3281 #define regGCVM_L2_CONTEXT11_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX                                 0
3282 #define regGCVM_L2_CONTEXT12_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES                                          0x1760
3283 #define regGCVM_L2_CONTEXT12_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX                                 0
3284 #define regGCVM_L2_CONTEXT13_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES                                          0x1761
3285 #define regGCVM_L2_CONTEXT13_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX                                 0
3286 #define regGCVM_L2_CONTEXT14_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES                                          0x1762
3287 #define regGCVM_L2_CONTEXT14_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX                                 0
3288 #define regGCVM_L2_CONTEXT15_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES                                          0x1763
3289 #define regGCVM_L2_CONTEXT15_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX                                 0
3290 
3291 
3292 // addressBlock: gc_gcvml2perfddec
3293 // base address: 0x35380
3294 #define regGCVML2_PERFCOUNTER2_0_LO                                                                     0x34e0
3295 #define regGCVML2_PERFCOUNTER2_0_LO_BASE_IDX                                                            1
3296 #define regGCVML2_PERFCOUNTER2_1_LO                                                                     0x34e1
3297 #define regGCVML2_PERFCOUNTER2_1_LO_BASE_IDX                                                            1
3298 #define regGCVML2_PERFCOUNTER2_0_HI                                                                     0x34e2
3299 #define regGCVML2_PERFCOUNTER2_0_HI_BASE_IDX                                                            1
3300 #define regGCVML2_PERFCOUNTER2_1_HI                                                                     0x34e3
3301 #define regGCVML2_PERFCOUNTER2_1_HI_BASE_IDX                                                            1
3302 
3303 
3304 // addressBlock: gc_gcvml2prdec
3305 // base address: 0x35390
3306 #define regGCMC_VM_L2_PERFCOUNTER_LO                                                                    0x34e4
3307 #define regGCMC_VM_L2_PERFCOUNTER_LO_BASE_IDX                                                           1
3308 #define regGCMC_VM_L2_PERFCOUNTER_HI                                                                    0x34e5
3309 #define regGCMC_VM_L2_PERFCOUNTER_HI_BASE_IDX                                                           1
3310 #define regGCUTCL2_PERFCOUNTER_LO                                                                       0x34e6
3311 #define regGCUTCL2_PERFCOUNTER_LO_BASE_IDX                                                              1
3312 #define regGCUTCL2_PERFCOUNTER_HI                                                                       0x34e7
3313 #define regGCUTCL2_PERFCOUNTER_HI_BASE_IDX                                                              1
3314 
3315 
3316 // addressBlock: gc_gcvml2perfsdec
3317 // base address: 0x37480
3318 #define regGCVML2_PERFCOUNTER2_0_SELECT                                                                 0x3d20
3319 #define regGCVML2_PERFCOUNTER2_0_SELECT_BASE_IDX                                                        1
3320 #define regGCVML2_PERFCOUNTER2_1_SELECT                                                                 0x3d21
3321 #define regGCVML2_PERFCOUNTER2_1_SELECT_BASE_IDX                                                        1
3322 #define regGCVML2_PERFCOUNTER2_0_SELECT1                                                                0x3d22
3323 #define regGCVML2_PERFCOUNTER2_0_SELECT1_BASE_IDX                                                       1
3324 #define regGCVML2_PERFCOUNTER2_1_SELECT1                                                                0x3d23
3325 #define regGCVML2_PERFCOUNTER2_1_SELECT1_BASE_IDX                                                       1
3326 #define regGCVML2_PERFCOUNTER2_0_MODE                                                                   0x3d24
3327 #define regGCVML2_PERFCOUNTER2_0_MODE_BASE_IDX                                                          1
3328 #define regGCVML2_PERFCOUNTER2_1_MODE                                                                   0x3d25
3329 #define regGCVML2_PERFCOUNTER2_1_MODE_BASE_IDX                                                          1
3330 
3331 
3332 // addressBlock: gc_gcvml2pldec
3333 // base address: 0x374c0
3334 #define regGCMC_VM_L2_PERFCOUNTER0_CFG                                                                  0x3d30
3335 #define regGCMC_VM_L2_PERFCOUNTER0_CFG_BASE_IDX                                                         1
3336 #define regGCMC_VM_L2_PERFCOUNTER1_CFG                                                                  0x3d31
3337 #define regGCMC_VM_L2_PERFCOUNTER1_CFG_BASE_IDX                                                         1
3338 #define regGCMC_VM_L2_PERFCOUNTER2_CFG                                                                  0x3d32
3339 #define regGCMC_VM_L2_PERFCOUNTER2_CFG_BASE_IDX                                                         1
3340 #define regGCMC_VM_L2_PERFCOUNTER3_CFG                                                                  0x3d33
3341 #define regGCMC_VM_L2_PERFCOUNTER3_CFG_BASE_IDX                                                         1
3342 #define regGCMC_VM_L2_PERFCOUNTER4_CFG                                                                  0x3d34
3343 #define regGCMC_VM_L2_PERFCOUNTER4_CFG_BASE_IDX                                                         1
3344 #define regGCMC_VM_L2_PERFCOUNTER5_CFG                                                                  0x3d35
3345 #define regGCMC_VM_L2_PERFCOUNTER5_CFG_BASE_IDX                                                         1
3346 #define regGCMC_VM_L2_PERFCOUNTER6_CFG                                                                  0x3d36
3347 #define regGCMC_VM_L2_PERFCOUNTER6_CFG_BASE_IDX                                                         1
3348 #define regGCMC_VM_L2_PERFCOUNTER7_CFG                                                                  0x3d37
3349 #define regGCMC_VM_L2_PERFCOUNTER7_CFG_BASE_IDX                                                         1
3350 #define regGCMC_VM_L2_PERFCOUNTER_RSLT_CNTL                                                             0x3d38
3351 #define regGCMC_VM_L2_PERFCOUNTER_RSLT_CNTL_BASE_IDX                                                    1
3352 #define regGCUTCL2_PERFCOUNTER0_CFG                                                                     0x3d39
3353 #define regGCUTCL2_PERFCOUNTER0_CFG_BASE_IDX                                                            1
3354 #define regGCUTCL2_PERFCOUNTER1_CFG                                                                     0x3d3a
3355 #define regGCUTCL2_PERFCOUNTER1_CFG_BASE_IDX                                                            1
3356 #define regGCUTCL2_PERFCOUNTER2_CFG                                                                     0x3d3b
3357 #define regGCUTCL2_PERFCOUNTER2_CFG_BASE_IDX                                                            1
3358 #define regGCUTCL2_PERFCOUNTER3_CFG                                                                     0x3d3c
3359 #define regGCUTCL2_PERFCOUNTER3_CFG_BASE_IDX                                                            1
3360 #define regGCUTCL2_PERFCOUNTER_RSLT_CNTL                                                                0x3d3d
3361 #define regGCUTCL2_PERFCOUNTER_RSLT_CNTL_BASE_IDX                                                       1
3362 
3363 
3364 // addressBlock: gc_gcvmsharedhvdec
3365 // base address: 0x3ea00
3366 #define regGCMC_VM_FB_SIZE_OFFSET_VF0                                                                   0x5a80
3367 #define regGCMC_VM_FB_SIZE_OFFSET_VF0_BASE_IDX                                                          1
3368 #define regGCMC_VM_FB_SIZE_OFFSET_VF1                                                                   0x5a81
3369 #define regGCMC_VM_FB_SIZE_OFFSET_VF1_BASE_IDX                                                          1
3370 #define regGCMC_VM_FB_SIZE_OFFSET_VF2                                                                   0x5a82
3371 #define regGCMC_VM_FB_SIZE_OFFSET_VF2_BASE_IDX                                                          1
3372 #define regGCMC_VM_FB_SIZE_OFFSET_VF3                                                                   0x5a83
3373 #define regGCMC_VM_FB_SIZE_OFFSET_VF3_BASE_IDX                                                          1
3374 #define regGCMC_VM_FB_SIZE_OFFSET_VF4                                                                   0x5a84
3375 #define regGCMC_VM_FB_SIZE_OFFSET_VF4_BASE_IDX                                                          1
3376 #define regGCMC_VM_FB_SIZE_OFFSET_VF5                                                                   0x5a85
3377 #define regGCMC_VM_FB_SIZE_OFFSET_VF5_BASE_IDX                                                          1
3378 #define regGCMC_VM_FB_SIZE_OFFSET_VF6                                                                   0x5a86
3379 #define regGCMC_VM_FB_SIZE_OFFSET_VF6_BASE_IDX                                                          1
3380 #define regGCMC_VM_FB_SIZE_OFFSET_VF7                                                                   0x5a87
3381 #define regGCMC_VM_FB_SIZE_OFFSET_VF7_BASE_IDX                                                          1
3382 #define regGCMC_VM_FB_SIZE_OFFSET_VF8                                                                   0x5a88
3383 #define regGCMC_VM_FB_SIZE_OFFSET_VF8_BASE_IDX                                                          1
3384 #define regGCMC_VM_FB_SIZE_OFFSET_VF9                                                                   0x5a89
3385 #define regGCMC_VM_FB_SIZE_OFFSET_VF9_BASE_IDX                                                          1
3386 #define regGCMC_VM_FB_SIZE_OFFSET_VF10                                                                  0x5a8a
3387 #define regGCMC_VM_FB_SIZE_OFFSET_VF10_BASE_IDX                                                         1
3388 #define regGCMC_VM_FB_SIZE_OFFSET_VF11                                                                  0x5a8b
3389 #define regGCMC_VM_FB_SIZE_OFFSET_VF11_BASE_IDX                                                         1
3390 #define regGCMC_VM_FB_SIZE_OFFSET_VF12                                                                  0x5a8c
3391 #define regGCMC_VM_FB_SIZE_OFFSET_VF12_BASE_IDX                                                         1
3392 #define regGCMC_VM_FB_SIZE_OFFSET_VF13                                                                  0x5a8d
3393 #define regGCMC_VM_FB_SIZE_OFFSET_VF13_BASE_IDX                                                         1
3394 #define regGCMC_VM_FB_SIZE_OFFSET_VF14                                                                  0x5a8e
3395 #define regGCMC_VM_FB_SIZE_OFFSET_VF14_BASE_IDX                                                         1
3396 #define regGCMC_VM_FB_SIZE_OFFSET_VF15                                                                  0x5a8f
3397 #define regGCMC_VM_FB_SIZE_OFFSET_VF15_BASE_IDX                                                         1
3398 
3399 
3400 // addressBlock: gc_gcvml2pspdec
3401 // base address: 0x3f900
3402 #define regGCUTCL2_TRANSLATION_BYPASS_BY_VMID                                                           0x5e41
3403 #define regGCUTCL2_TRANSLATION_BYPASS_BY_VMID_BASE_IDX                                                  1
3404 #define regGCUTC_GPUVA_VMID_TRANSLATION_ASSIST_CNTL                                                     0x5e44
3405 #define regGCUTC_GPUVA_VMID_TRANSLATION_ASSIST_CNTL_BASE_IDX                                            1
3406 #define regGCMC_VM_MARC_BASE_LO_0                                                                       0x5e48
3407 #define regGCMC_VM_MARC_BASE_LO_0_BASE_IDX                                                              1
3408 #define regGCMC_VM_MARC_BASE_LO_1                                                                       0x5e49
3409 #define regGCMC_VM_MARC_BASE_LO_1_BASE_IDX                                                              1
3410 #define regGCMC_VM_MARC_BASE_LO_2                                                                       0x5e4a
3411 #define regGCMC_VM_MARC_BASE_LO_2_BASE_IDX                                                              1
3412 #define regGCMC_VM_MARC_BASE_LO_3                                                                       0x5e4b
3413 #define regGCMC_VM_MARC_BASE_LO_3_BASE_IDX                                                              1
3414 #define regGCMC_VM_MARC_BASE_LO_4                                                                       0x5e4c
3415 #define regGCMC_VM_MARC_BASE_LO_4_BASE_IDX                                                              1
3416 #define regGCMC_VM_MARC_BASE_LO_5                                                                       0x5e4d
3417 #define regGCMC_VM_MARC_BASE_LO_5_BASE_IDX                                                              1
3418 #define regGCMC_VM_MARC_BASE_LO_6                                                                       0x5e4e
3419 #define regGCMC_VM_MARC_BASE_LO_6_BASE_IDX                                                              1
3420 #define regGCMC_VM_MARC_BASE_LO_7                                                                       0x5e4f
3421 #define regGCMC_VM_MARC_BASE_LO_7_BASE_IDX                                                              1
3422 #define regGCMC_VM_MARC_BASE_LO_8                                                                       0x5e50
3423 #define regGCMC_VM_MARC_BASE_LO_8_BASE_IDX                                                              1
3424 #define regGCMC_VM_MARC_BASE_LO_9                                                                       0x5e51
3425 #define regGCMC_VM_MARC_BASE_LO_9_BASE_IDX                                                              1
3426 #define regGCMC_VM_MARC_BASE_LO_10                                                                      0x5e52
3427 #define regGCMC_VM_MARC_BASE_LO_10_BASE_IDX                                                             1
3428 #define regGCMC_VM_MARC_BASE_LO_11                                                                      0x5e53
3429 #define regGCMC_VM_MARC_BASE_LO_11_BASE_IDX                                                             1
3430 #define regGCMC_VM_MARC_BASE_LO_12                                                                      0x5e54
3431 #define regGCMC_VM_MARC_BASE_LO_12_BASE_IDX                                                             1
3432 #define regGCMC_VM_MARC_BASE_LO_13                                                                      0x5e55
3433 #define regGCMC_VM_MARC_BASE_LO_13_BASE_IDX                                                             1
3434 #define regGCMC_VM_MARC_BASE_LO_14                                                                      0x5e56
3435 #define regGCMC_VM_MARC_BASE_LO_14_BASE_IDX                                                             1
3436 #define regGCMC_VM_MARC_BASE_LO_15                                                                      0x5e57
3437 #define regGCMC_VM_MARC_BASE_LO_15_BASE_IDX                                                             1
3438 #define regGCMC_VM_MARC_BASE_HI_0                                                                       0x5e58
3439 #define regGCMC_VM_MARC_BASE_HI_0_BASE_IDX                                                              1
3440 #define regGCMC_VM_MARC_BASE_HI_1                                                                       0x5e59
3441 #define regGCMC_VM_MARC_BASE_HI_1_BASE_IDX                                                              1
3442 #define regGCMC_VM_MARC_BASE_HI_2                                                                       0x5e5a
3443 #define regGCMC_VM_MARC_BASE_HI_2_BASE_IDX                                                              1
3444 #define regGCMC_VM_MARC_BASE_HI_3                                                                       0x5e5b
3445 #define regGCMC_VM_MARC_BASE_HI_3_BASE_IDX                                                              1
3446 #define regGCMC_VM_MARC_BASE_HI_4                                                                       0x5e5c
3447 #define regGCMC_VM_MARC_BASE_HI_4_BASE_IDX                                                              1
3448 #define regGCMC_VM_MARC_BASE_HI_5                                                                       0x5e5d
3449 #define regGCMC_VM_MARC_BASE_HI_5_BASE_IDX                                                              1
3450 #define regGCMC_VM_MARC_BASE_HI_6                                                                       0x5e5e
3451 #define regGCMC_VM_MARC_BASE_HI_6_BASE_IDX                                                              1
3452 #define regGCMC_VM_MARC_BASE_HI_7                                                                       0x5e5f
3453 #define regGCMC_VM_MARC_BASE_HI_7_BASE_IDX                                                              1
3454 #define regGCMC_VM_MARC_BASE_HI_8                                                                       0x5e60
3455 #define regGCMC_VM_MARC_BASE_HI_8_BASE_IDX                                                              1
3456 #define regGCMC_VM_MARC_BASE_HI_9                                                                       0x5e61
3457 #define regGCMC_VM_MARC_BASE_HI_9_BASE_IDX                                                              1
3458 #define regGCMC_VM_MARC_BASE_HI_10                                                                      0x5e62
3459 #define regGCMC_VM_MARC_BASE_HI_10_BASE_IDX                                                             1
3460 #define regGCMC_VM_MARC_BASE_HI_11                                                                      0x5e63
3461 #define regGCMC_VM_MARC_BASE_HI_11_BASE_IDX                                                             1
3462 #define regGCMC_VM_MARC_BASE_HI_12                                                                      0x5e64
3463 #define regGCMC_VM_MARC_BASE_HI_12_BASE_IDX                                                             1
3464 #define regGCMC_VM_MARC_BASE_HI_13                                                                      0x5e65
3465 #define regGCMC_VM_MARC_BASE_HI_13_BASE_IDX                                                             1
3466 #define regGCMC_VM_MARC_BASE_HI_14                                                                      0x5e66
3467 #define regGCMC_VM_MARC_BASE_HI_14_BASE_IDX                                                             1
3468 #define regGCMC_VM_MARC_BASE_HI_15                                                                      0x5e67
3469 #define regGCMC_VM_MARC_BASE_HI_15_BASE_IDX                                                             1
3470 #define regGCMC_VM_MARC_RELOC_LO_0                                                                      0x5e68
3471 #define regGCMC_VM_MARC_RELOC_LO_0_BASE_IDX                                                             1
3472 #define regGCMC_VM_MARC_RELOC_LO_1                                                                      0x5e69
3473 #define regGCMC_VM_MARC_RELOC_LO_1_BASE_IDX                                                             1
3474 #define regGCMC_VM_MARC_RELOC_LO_2                                                                      0x5e6a
3475 #define regGCMC_VM_MARC_RELOC_LO_2_BASE_IDX                                                             1
3476 #define regGCMC_VM_MARC_RELOC_LO_3                                                                      0x5e6b
3477 #define regGCMC_VM_MARC_RELOC_LO_3_BASE_IDX                                                             1
3478 #define regGCMC_VM_MARC_RELOC_LO_4                                                                      0x5e6c
3479 #define regGCMC_VM_MARC_RELOC_LO_4_BASE_IDX                                                             1
3480 #define regGCMC_VM_MARC_RELOC_LO_5                                                                      0x5e6d
3481 #define regGCMC_VM_MARC_RELOC_LO_5_BASE_IDX                                                             1
3482 #define regGCMC_VM_MARC_RELOC_LO_6                                                                      0x5e6e
3483 #define regGCMC_VM_MARC_RELOC_LO_6_BASE_IDX                                                             1
3484 #define regGCMC_VM_MARC_RELOC_LO_7                                                                      0x5e6f
3485 #define regGCMC_VM_MARC_RELOC_LO_7_BASE_IDX                                                             1
3486 #define regGCMC_VM_MARC_RELOC_LO_8                                                                      0x5e70
3487 #define regGCMC_VM_MARC_RELOC_LO_8_BASE_IDX                                                             1
3488 #define regGCMC_VM_MARC_RELOC_LO_9                                                                      0x5e71
3489 #define regGCMC_VM_MARC_RELOC_LO_9_BASE_IDX                                                             1
3490 #define regGCMC_VM_MARC_RELOC_LO_10                                                                     0x5e72
3491 #define regGCMC_VM_MARC_RELOC_LO_10_BASE_IDX                                                            1
3492 #define regGCMC_VM_MARC_RELOC_LO_11                                                                     0x5e73
3493 #define regGCMC_VM_MARC_RELOC_LO_11_BASE_IDX                                                            1
3494 #define regGCMC_VM_MARC_RELOC_LO_12                                                                     0x5e74
3495 #define regGCMC_VM_MARC_RELOC_LO_12_BASE_IDX                                                            1
3496 #define regGCMC_VM_MARC_RELOC_LO_13                                                                     0x5e75
3497 #define regGCMC_VM_MARC_RELOC_LO_13_BASE_IDX                                                            1
3498 #define regGCMC_VM_MARC_RELOC_LO_14                                                                     0x5e76
3499 #define regGCMC_VM_MARC_RELOC_LO_14_BASE_IDX                                                            1
3500 #define regGCMC_VM_MARC_RELOC_LO_15                                                                     0x5e77
3501 #define regGCMC_VM_MARC_RELOC_LO_15_BASE_IDX                                                            1
3502 #define regGCMC_VM_MARC_RELOC_HI_0                                                                      0x5e78
3503 #define regGCMC_VM_MARC_RELOC_HI_0_BASE_IDX                                                             1
3504 #define regGCMC_VM_MARC_RELOC_HI_1                                                                      0x5e79
3505 #define regGCMC_VM_MARC_RELOC_HI_1_BASE_IDX                                                             1
3506 #define regGCMC_VM_MARC_RELOC_HI_2                                                                      0x5e7a
3507 #define regGCMC_VM_MARC_RELOC_HI_2_BASE_IDX                                                             1
3508 #define regGCMC_VM_MARC_RELOC_HI_3                                                                      0x5e7b
3509 #define regGCMC_VM_MARC_RELOC_HI_3_BASE_IDX                                                             1
3510 #define regGCMC_VM_MARC_RELOC_HI_4                                                                      0x5e7c
3511 #define regGCMC_VM_MARC_RELOC_HI_4_BASE_IDX                                                             1
3512 #define regGCMC_VM_MARC_RELOC_HI_5                                                                      0x5e7d
3513 #define regGCMC_VM_MARC_RELOC_HI_5_BASE_IDX                                                             1
3514 #define regGCMC_VM_MARC_RELOC_HI_6                                                                      0x5e7e
3515 #define regGCMC_VM_MARC_RELOC_HI_6_BASE_IDX                                                             1
3516 #define regGCMC_VM_MARC_RELOC_HI_7                                                                      0x5e7f
3517 #define regGCMC_VM_MARC_RELOC_HI_7_BASE_IDX                                                             1
3518 #define regGCMC_VM_MARC_RELOC_HI_8                                                                      0x5e80
3519 #define regGCMC_VM_MARC_RELOC_HI_8_BASE_IDX                                                             1
3520 #define regGCMC_VM_MARC_RELOC_HI_9                                                                      0x5e81
3521 #define regGCMC_VM_MARC_RELOC_HI_9_BASE_IDX                                                             1
3522 #define regGCMC_VM_MARC_RELOC_HI_10                                                                     0x5e82
3523 #define regGCMC_VM_MARC_RELOC_HI_10_BASE_IDX                                                            1
3524 #define regGCMC_VM_MARC_RELOC_HI_11                                                                     0x5e83
3525 #define regGCMC_VM_MARC_RELOC_HI_11_BASE_IDX                                                            1
3526 #define regGCMC_VM_MARC_RELOC_HI_12                                                                     0x5e84
3527 #define regGCMC_VM_MARC_RELOC_HI_12_BASE_IDX                                                            1
3528 #define regGCMC_VM_MARC_RELOC_HI_13                                                                     0x5e85
3529 #define regGCMC_VM_MARC_RELOC_HI_13_BASE_IDX                                                            1
3530 #define regGCMC_VM_MARC_RELOC_HI_14                                                                     0x5e86
3531 #define regGCMC_VM_MARC_RELOC_HI_14_BASE_IDX                                                            1
3532 #define regGCMC_VM_MARC_RELOC_HI_15                                                                     0x5e87
3533 #define regGCMC_VM_MARC_RELOC_HI_15_BASE_IDX                                                            1
3534 #define regGCMC_VM_MARC_LEN_LO_0                                                                        0x5e88
3535 #define regGCMC_VM_MARC_LEN_LO_0_BASE_IDX                                                               1
3536 #define regGCMC_VM_MARC_LEN_LO_1                                                                        0x5e89
3537 #define regGCMC_VM_MARC_LEN_LO_1_BASE_IDX                                                               1
3538 #define regGCMC_VM_MARC_LEN_LO_2                                                                        0x5e8a
3539 #define regGCMC_VM_MARC_LEN_LO_2_BASE_IDX                                                               1
3540 #define regGCMC_VM_MARC_LEN_LO_3                                                                        0x5e8b
3541 #define regGCMC_VM_MARC_LEN_LO_3_BASE_IDX                                                               1
3542 #define regGCMC_VM_MARC_LEN_LO_4                                                                        0x5e8c
3543 #define regGCMC_VM_MARC_LEN_LO_4_BASE_IDX                                                               1
3544 #define regGCMC_VM_MARC_LEN_LO_5                                                                        0x5e8d
3545 #define regGCMC_VM_MARC_LEN_LO_5_BASE_IDX                                                               1
3546 #define regGCMC_VM_MARC_LEN_LO_6                                                                        0x5e8e
3547 #define regGCMC_VM_MARC_LEN_LO_6_BASE_IDX                                                               1
3548 #define regGCMC_VM_MARC_LEN_LO_7                                                                        0x5e8f
3549 #define regGCMC_VM_MARC_LEN_LO_7_BASE_IDX                                                               1
3550 #define regGCMC_VM_MARC_LEN_LO_8                                                                        0x5e90
3551 #define regGCMC_VM_MARC_LEN_LO_8_BASE_IDX                                                               1
3552 #define regGCMC_VM_MARC_LEN_LO_9                                                                        0x5e91
3553 #define regGCMC_VM_MARC_LEN_LO_9_BASE_IDX                                                               1
3554 #define regGCMC_VM_MARC_LEN_LO_10                                                                       0x5e92
3555 #define regGCMC_VM_MARC_LEN_LO_10_BASE_IDX                                                              1
3556 #define regGCMC_VM_MARC_LEN_LO_11                                                                       0x5e93
3557 #define regGCMC_VM_MARC_LEN_LO_11_BASE_IDX                                                              1
3558 #define regGCMC_VM_MARC_LEN_LO_12                                                                       0x5e94
3559 #define regGCMC_VM_MARC_LEN_LO_12_BASE_IDX                                                              1
3560 #define regGCMC_VM_MARC_LEN_LO_13                                                                       0x5e95
3561 #define regGCMC_VM_MARC_LEN_LO_13_BASE_IDX                                                              1
3562 #define regGCMC_VM_MARC_LEN_LO_14                                                                       0x5e96
3563 #define regGCMC_VM_MARC_LEN_LO_14_BASE_IDX                                                              1
3564 #define regGCMC_VM_MARC_LEN_LO_15                                                                       0x5e97
3565 #define regGCMC_VM_MARC_LEN_LO_15_BASE_IDX                                                              1
3566 #define regGCMC_VM_MARC_LEN_HI_0                                                                        0x5e98
3567 #define regGCMC_VM_MARC_LEN_HI_0_BASE_IDX                                                               1
3568 #define regGCMC_VM_MARC_LEN_HI_1                                                                        0x5e99
3569 #define regGCMC_VM_MARC_LEN_HI_1_BASE_IDX                                                               1
3570 #define regGCMC_VM_MARC_LEN_HI_2                                                                        0x5e9a
3571 #define regGCMC_VM_MARC_LEN_HI_2_BASE_IDX                                                               1
3572 #define regGCMC_VM_MARC_LEN_HI_3                                                                        0x5e9b
3573 #define regGCMC_VM_MARC_LEN_HI_3_BASE_IDX                                                               1
3574 #define regGCMC_VM_MARC_LEN_HI_4                                                                        0x5e9c
3575 #define regGCMC_VM_MARC_LEN_HI_4_BASE_IDX                                                               1
3576 #define regGCMC_VM_MARC_LEN_HI_5                                                                        0x5e9d
3577 #define regGCMC_VM_MARC_LEN_HI_5_BASE_IDX                                                               1
3578 #define regGCMC_VM_MARC_LEN_HI_6                                                                        0x5e9e
3579 #define regGCMC_VM_MARC_LEN_HI_6_BASE_IDX                                                               1
3580 #define regGCMC_VM_MARC_LEN_HI_7                                                                        0x5e9f
3581 #define regGCMC_VM_MARC_LEN_HI_7_BASE_IDX                                                               1
3582 #define regGCMC_VM_MARC_LEN_HI_8                                                                        0x5ea0
3583 #define regGCMC_VM_MARC_LEN_HI_8_BASE_IDX                                                               1
3584 #define regGCMC_VM_MARC_LEN_HI_9                                                                        0x5ea1
3585 #define regGCMC_VM_MARC_LEN_HI_9_BASE_IDX                                                               1
3586 #define regGCMC_VM_MARC_LEN_HI_10                                                                       0x5ea2
3587 #define regGCMC_VM_MARC_LEN_HI_10_BASE_IDX                                                              1
3588 #define regGCMC_VM_MARC_LEN_HI_11                                                                       0x5ea3
3589 #define regGCMC_VM_MARC_LEN_HI_11_BASE_IDX                                                              1
3590 #define regGCMC_VM_MARC_LEN_HI_12                                                                       0x5ea4
3591 #define regGCMC_VM_MARC_LEN_HI_12_BASE_IDX                                                              1
3592 #define regGCMC_VM_MARC_LEN_HI_13                                                                       0x5ea5
3593 #define regGCMC_VM_MARC_LEN_HI_13_BASE_IDX                                                              1
3594 #define regGCMC_VM_MARC_LEN_HI_14                                                                       0x5ea6
3595 #define regGCMC_VM_MARC_LEN_HI_14_BASE_IDX                                                              1
3596 #define regGCMC_VM_MARC_LEN_HI_15                                                                       0x5ea7
3597 #define regGCMC_VM_MARC_LEN_HI_15_BASE_IDX                                                              1
3598 #define regGCMC_VM_MARC_PFVF_MAPPING_0                                                                  0x5ea8
3599 #define regGCMC_VM_MARC_PFVF_MAPPING_0_BASE_IDX                                                         1
3600 #define regGCMC_VM_MARC_PFVF_MAPPING_1                                                                  0x5ea9
3601 #define regGCMC_VM_MARC_PFVF_MAPPING_1_BASE_IDX                                                         1
3602 #define regGCMC_VM_MARC_PFVF_MAPPING_2                                                                  0x5eaa
3603 #define regGCMC_VM_MARC_PFVF_MAPPING_2_BASE_IDX                                                         1
3604 #define regGCMC_VM_MARC_PFVF_MAPPING_3                                                                  0x5eab
3605 #define regGCMC_VM_MARC_PFVF_MAPPING_3_BASE_IDX                                                         1
3606 #define regGCMC_VM_MARC_PFVF_MAPPING_4                                                                  0x5eac
3607 #define regGCMC_VM_MARC_PFVF_MAPPING_4_BASE_IDX                                                         1
3608 #define regGCMC_VM_MARC_PFVF_MAPPING_5                                                                  0x5ead
3609 #define regGCMC_VM_MARC_PFVF_MAPPING_5_BASE_IDX                                                         1
3610 #define regGCMC_VM_MARC_PFVF_MAPPING_6                                                                  0x5eae
3611 #define regGCMC_VM_MARC_PFVF_MAPPING_6_BASE_IDX                                                         1
3612 #define regGCMC_VM_MARC_PFVF_MAPPING_7                                                                  0x5eaf
3613 #define regGCMC_VM_MARC_PFVF_MAPPING_7_BASE_IDX                                                         1
3614 #define regGCMC_VM_MARC_PFVF_MAPPING_8                                                                  0x5eb0
3615 #define regGCMC_VM_MARC_PFVF_MAPPING_8_BASE_IDX                                                         1
3616 #define regGCMC_VM_MARC_PFVF_MAPPING_9                                                                  0x5eb1
3617 #define regGCMC_VM_MARC_PFVF_MAPPING_9_BASE_IDX                                                         1
3618 #define regGCMC_VM_MARC_PFVF_MAPPING_10                                                                 0x5eb2
3619 #define regGCMC_VM_MARC_PFVF_MAPPING_10_BASE_IDX                                                        1
3620 #define regGCMC_VM_MARC_PFVF_MAPPING_11                                                                 0x5eb3
3621 #define regGCMC_VM_MARC_PFVF_MAPPING_11_BASE_IDX                                                        1
3622 #define regGCMC_VM_MARC_PFVF_MAPPING_12                                                                 0x5eb4
3623 #define regGCMC_VM_MARC_PFVF_MAPPING_12_BASE_IDX                                                        1
3624 #define regGCMC_VM_MARC_PFVF_MAPPING_13                                                                 0x5eb5
3625 #define regGCMC_VM_MARC_PFVF_MAPPING_13_BASE_IDX                                                        1
3626 #define regGCMC_VM_MARC_PFVF_MAPPING_14                                                                 0x5eb6
3627 #define regGCMC_VM_MARC_PFVF_MAPPING_14_BASE_IDX                                                        1
3628 #define regGCMC_VM_MARC_PFVF_MAPPING_15                                                                 0x5eb7
3629 #define regGCMC_VM_MARC_PFVF_MAPPING_15_BASE_IDX                                                        1
3630 #define regGCUTC_TRANSLATION_FAULT_CNTL0                                                                0x5eb8
3631 #define regGCUTC_TRANSLATION_FAULT_CNTL0_BASE_IDX                                                       1
3632 #define regGCUTC_TRANSLATION_FAULT_CNTL1                                                                0x5eb9
3633 #define regGCUTC_TRANSLATION_FAULT_CNTL1_BASE_IDX                                                       1
3634 
3635 
3636 // addressBlock: gc_shdec
3637 // base address: 0xb000
3638 #define regSPI_SHADER_PGM_RSRC4_PS                                                                      0x19a1
3639 #define regSPI_SHADER_PGM_RSRC4_PS_BASE_IDX                                                             0
3640 #define regSPI_SHADER_PGM_CHKSUM_PS                                                                     0x19a6
3641 #define regSPI_SHADER_PGM_CHKSUM_PS_BASE_IDX                                                            0
3642 #define regSPI_SHADER_PGM_RSRC3_PS                                                                      0x19a7
3643 #define regSPI_SHADER_PGM_RSRC3_PS_BASE_IDX                                                             0
3644 #define regSPI_SHADER_PGM_LO_PS                                                                         0x19a8
3645 #define regSPI_SHADER_PGM_LO_PS_BASE_IDX                                                                0
3646 #define regSPI_SHADER_PGM_HI_PS                                                                         0x19a9
3647 #define regSPI_SHADER_PGM_HI_PS_BASE_IDX                                                                0
3648 #define regSPI_SHADER_PGM_RSRC1_PS                                                                      0x19aa
3649 #define regSPI_SHADER_PGM_RSRC1_PS_BASE_IDX                                                             0
3650 #define regSPI_SHADER_PGM_RSRC2_PS                                                                      0x19ab
3651 #define regSPI_SHADER_PGM_RSRC2_PS_BASE_IDX                                                             0
3652 #define regSPI_SHADER_USER_DATA_PS_0                                                                    0x19ac
3653 #define regSPI_SHADER_USER_DATA_PS_0_BASE_IDX                                                           0
3654 #define regSPI_SHADER_USER_DATA_PS_1                                                                    0x19ad
3655 #define regSPI_SHADER_USER_DATA_PS_1_BASE_IDX                                                           0
3656 #define regSPI_SHADER_USER_DATA_PS_2                                                                    0x19ae
3657 #define regSPI_SHADER_USER_DATA_PS_2_BASE_IDX                                                           0
3658 #define regSPI_SHADER_USER_DATA_PS_3                                                                    0x19af
3659 #define regSPI_SHADER_USER_DATA_PS_3_BASE_IDX                                                           0
3660 #define regSPI_SHADER_USER_DATA_PS_4                                                                    0x19b0
3661 #define regSPI_SHADER_USER_DATA_PS_4_BASE_IDX                                                           0
3662 #define regSPI_SHADER_USER_DATA_PS_5                                                                    0x19b1
3663 #define regSPI_SHADER_USER_DATA_PS_5_BASE_IDX                                                           0
3664 #define regSPI_SHADER_USER_DATA_PS_6                                                                    0x19b2
3665 #define regSPI_SHADER_USER_DATA_PS_6_BASE_IDX                                                           0
3666 #define regSPI_SHADER_USER_DATA_PS_7                                                                    0x19b3
3667 #define regSPI_SHADER_USER_DATA_PS_7_BASE_IDX                                                           0
3668 #define regSPI_SHADER_USER_DATA_PS_8                                                                    0x19b4
3669 #define regSPI_SHADER_USER_DATA_PS_8_BASE_IDX                                                           0
3670 #define regSPI_SHADER_USER_DATA_PS_9                                                                    0x19b5
3671 #define regSPI_SHADER_USER_DATA_PS_9_BASE_IDX                                                           0
3672 #define regSPI_SHADER_USER_DATA_PS_10                                                                   0x19b6
3673 #define regSPI_SHADER_USER_DATA_PS_10_BASE_IDX                                                          0
3674 #define regSPI_SHADER_USER_DATA_PS_11                                                                   0x19b7
3675 #define regSPI_SHADER_USER_DATA_PS_11_BASE_IDX                                                          0
3676 #define regSPI_SHADER_USER_DATA_PS_12                                                                   0x19b8
3677 #define regSPI_SHADER_USER_DATA_PS_12_BASE_IDX                                                          0
3678 #define regSPI_SHADER_USER_DATA_PS_13                                                                   0x19b9
3679 #define regSPI_SHADER_USER_DATA_PS_13_BASE_IDX                                                          0
3680 #define regSPI_SHADER_USER_DATA_PS_14                                                                   0x19ba
3681 #define regSPI_SHADER_USER_DATA_PS_14_BASE_IDX                                                          0
3682 #define regSPI_SHADER_USER_DATA_PS_15                                                                   0x19bb
3683 #define regSPI_SHADER_USER_DATA_PS_15_BASE_IDX                                                          0
3684 #define regSPI_SHADER_USER_DATA_PS_16                                                                   0x19bc
3685 #define regSPI_SHADER_USER_DATA_PS_16_BASE_IDX                                                          0
3686 #define regSPI_SHADER_USER_DATA_PS_17                                                                   0x19bd
3687 #define regSPI_SHADER_USER_DATA_PS_17_BASE_IDX                                                          0
3688 #define regSPI_SHADER_USER_DATA_PS_18                                                                   0x19be
3689 #define regSPI_SHADER_USER_DATA_PS_18_BASE_IDX                                                          0
3690 #define regSPI_SHADER_USER_DATA_PS_19                                                                   0x19bf
3691 #define regSPI_SHADER_USER_DATA_PS_19_BASE_IDX                                                          0
3692 #define regSPI_SHADER_USER_DATA_PS_20                                                                   0x19c0
3693 #define regSPI_SHADER_USER_DATA_PS_20_BASE_IDX                                                          0
3694 #define regSPI_SHADER_USER_DATA_PS_21                                                                   0x19c1
3695 #define regSPI_SHADER_USER_DATA_PS_21_BASE_IDX                                                          0
3696 #define regSPI_SHADER_USER_DATA_PS_22                                                                   0x19c2
3697 #define regSPI_SHADER_USER_DATA_PS_22_BASE_IDX                                                          0
3698 #define regSPI_SHADER_USER_DATA_PS_23                                                                   0x19c3
3699 #define regSPI_SHADER_USER_DATA_PS_23_BASE_IDX                                                          0
3700 #define regSPI_SHADER_USER_DATA_PS_24                                                                   0x19c4
3701 #define regSPI_SHADER_USER_DATA_PS_24_BASE_IDX                                                          0
3702 #define regSPI_SHADER_USER_DATA_PS_25                                                                   0x19c5
3703 #define regSPI_SHADER_USER_DATA_PS_25_BASE_IDX                                                          0
3704 #define regSPI_SHADER_USER_DATA_PS_26                                                                   0x19c6
3705 #define regSPI_SHADER_USER_DATA_PS_26_BASE_IDX                                                          0
3706 #define regSPI_SHADER_USER_DATA_PS_27                                                                   0x19c7
3707 #define regSPI_SHADER_USER_DATA_PS_27_BASE_IDX                                                          0
3708 #define regSPI_SHADER_USER_DATA_PS_28                                                                   0x19c8
3709 #define regSPI_SHADER_USER_DATA_PS_28_BASE_IDX                                                          0
3710 #define regSPI_SHADER_USER_DATA_PS_29                                                                   0x19c9
3711 #define regSPI_SHADER_USER_DATA_PS_29_BASE_IDX                                                          0
3712 #define regSPI_SHADER_USER_DATA_PS_30                                                                   0x19ca
3713 #define regSPI_SHADER_USER_DATA_PS_30_BASE_IDX                                                          0
3714 #define regSPI_SHADER_USER_DATA_PS_31                                                                   0x19cb
3715 #define regSPI_SHADER_USER_DATA_PS_31_BASE_IDX                                                          0
3716 #define regSPI_SHADER_REQ_CTRL_PS                                                                       0x19d0
3717 #define regSPI_SHADER_REQ_CTRL_PS_BASE_IDX                                                              0
3718 #define regSPI_SHADER_USER_ACCUM_PS_0                                                                   0x19d2
3719 #define regSPI_SHADER_USER_ACCUM_PS_0_BASE_IDX                                                          0
3720 #define regSPI_SHADER_USER_ACCUM_PS_1                                                                   0x19d3
3721 #define regSPI_SHADER_USER_ACCUM_PS_1_BASE_IDX                                                          0
3722 #define regSPI_SHADER_USER_ACCUM_PS_2                                                                   0x19d4
3723 #define regSPI_SHADER_USER_ACCUM_PS_2_BASE_IDX                                                          0
3724 #define regSPI_SHADER_USER_ACCUM_PS_3                                                                   0x19d5
3725 #define regSPI_SHADER_USER_ACCUM_PS_3_BASE_IDX                                                          0
3726 #define regSPI_SHADER_PGM_CHKSUM_GS                                                                     0x1a20
3727 #define regSPI_SHADER_PGM_CHKSUM_GS_BASE_IDX                                                            0
3728 #define regSPI_SHADER_PGM_RSRC4_GS                                                                      0x1a21
3729 #define regSPI_SHADER_PGM_RSRC4_GS_BASE_IDX                                                             0
3730 #define regSPI_SHADER_USER_DATA_ADDR_LO_GS                                                              0x1a22
3731 #define regSPI_SHADER_USER_DATA_ADDR_LO_GS_BASE_IDX                                                     0
3732 #define regSPI_SHADER_USER_DATA_ADDR_HI_GS                                                              0x1a23
3733 #define regSPI_SHADER_USER_DATA_ADDR_HI_GS_BASE_IDX                                                     0
3734 #define regSPI_SHADER_PGM_LO_ES_GS                                                                      0x1a24
3735 #define regSPI_SHADER_PGM_LO_ES_GS_BASE_IDX                                                             0
3736 #define regSPI_SHADER_PGM_HI_ES_GS                                                                      0x1a25
3737 #define regSPI_SHADER_PGM_HI_ES_GS_BASE_IDX                                                             0
3738 #define regSPI_SHADER_PGM_RSRC3_GS                                                                      0x1a27
3739 #define regSPI_SHADER_PGM_RSRC3_GS_BASE_IDX                                                             0
3740 #define regSPI_SHADER_PGM_LO_GS                                                                         0x1a28
3741 #define regSPI_SHADER_PGM_LO_GS_BASE_IDX                                                                0
3742 #define regSPI_SHADER_PGM_HI_GS                                                                         0x1a29
3743 #define regSPI_SHADER_PGM_HI_GS_BASE_IDX                                                                0
3744 #define regSPI_SHADER_PGM_RSRC1_GS                                                                      0x1a2a
3745 #define regSPI_SHADER_PGM_RSRC1_GS_BASE_IDX                                                             0
3746 #define regSPI_SHADER_PGM_RSRC2_GS                                                                      0x1a2b
3747 #define regSPI_SHADER_PGM_RSRC2_GS_BASE_IDX                                                             0
3748 #define regSPI_SHADER_USER_DATA_GS_0                                                                    0x1a2c
3749 #define regSPI_SHADER_USER_DATA_GS_0_BASE_IDX                                                           0
3750 #define regSPI_SHADER_USER_DATA_GS_1                                                                    0x1a2d
3751 #define regSPI_SHADER_USER_DATA_GS_1_BASE_IDX                                                           0
3752 #define regSPI_SHADER_USER_DATA_GS_2                                                                    0x1a2e
3753 #define regSPI_SHADER_USER_DATA_GS_2_BASE_IDX                                                           0
3754 #define regSPI_SHADER_USER_DATA_GS_3                                                                    0x1a2f
3755 #define regSPI_SHADER_USER_DATA_GS_3_BASE_IDX                                                           0
3756 #define regSPI_SHADER_USER_DATA_GS_4                                                                    0x1a30
3757 #define regSPI_SHADER_USER_DATA_GS_4_BASE_IDX                                                           0
3758 #define regSPI_SHADER_USER_DATA_GS_5                                                                    0x1a31
3759 #define regSPI_SHADER_USER_DATA_GS_5_BASE_IDX                                                           0
3760 #define regSPI_SHADER_USER_DATA_GS_6                                                                    0x1a32
3761 #define regSPI_SHADER_USER_DATA_GS_6_BASE_IDX                                                           0
3762 #define regSPI_SHADER_USER_DATA_GS_7                                                                    0x1a33
3763 #define regSPI_SHADER_USER_DATA_GS_7_BASE_IDX                                                           0
3764 #define regSPI_SHADER_USER_DATA_GS_8                                                                    0x1a34
3765 #define regSPI_SHADER_USER_DATA_GS_8_BASE_IDX                                                           0
3766 #define regSPI_SHADER_USER_DATA_GS_9                                                                    0x1a35
3767 #define regSPI_SHADER_USER_DATA_GS_9_BASE_IDX                                                           0
3768 #define regSPI_SHADER_USER_DATA_GS_10                                                                   0x1a36
3769 #define regSPI_SHADER_USER_DATA_GS_10_BASE_IDX                                                          0
3770 #define regSPI_SHADER_USER_DATA_GS_11                                                                   0x1a37
3771 #define regSPI_SHADER_USER_DATA_GS_11_BASE_IDX                                                          0
3772 #define regSPI_SHADER_USER_DATA_GS_12                                                                   0x1a38
3773 #define regSPI_SHADER_USER_DATA_GS_12_BASE_IDX                                                          0
3774 #define regSPI_SHADER_USER_DATA_GS_13                                                                   0x1a39
3775 #define regSPI_SHADER_USER_DATA_GS_13_BASE_IDX                                                          0
3776 #define regSPI_SHADER_USER_DATA_GS_14                                                                   0x1a3a
3777 #define regSPI_SHADER_USER_DATA_GS_14_BASE_IDX                                                          0
3778 #define regSPI_SHADER_USER_DATA_GS_15                                                                   0x1a3b
3779 #define regSPI_SHADER_USER_DATA_GS_15_BASE_IDX                                                          0
3780 #define regSPI_SHADER_USER_DATA_GS_16                                                                   0x1a3c
3781 #define regSPI_SHADER_USER_DATA_GS_16_BASE_IDX                                                          0
3782 #define regSPI_SHADER_USER_DATA_GS_17                                                                   0x1a3d
3783 #define regSPI_SHADER_USER_DATA_GS_17_BASE_IDX                                                          0
3784 #define regSPI_SHADER_USER_DATA_GS_18                                                                   0x1a3e
3785 #define regSPI_SHADER_USER_DATA_GS_18_BASE_IDX                                                          0
3786 #define regSPI_SHADER_USER_DATA_GS_19                                                                   0x1a3f
3787 #define regSPI_SHADER_USER_DATA_GS_19_BASE_IDX                                                          0
3788 #define regSPI_SHADER_USER_DATA_GS_20                                                                   0x1a40
3789 #define regSPI_SHADER_USER_DATA_GS_20_BASE_IDX                                                          0
3790 #define regSPI_SHADER_USER_DATA_GS_21                                                                   0x1a41
3791 #define regSPI_SHADER_USER_DATA_GS_21_BASE_IDX                                                          0
3792 #define regSPI_SHADER_USER_DATA_GS_22                                                                   0x1a42
3793 #define regSPI_SHADER_USER_DATA_GS_22_BASE_IDX                                                          0
3794 #define regSPI_SHADER_USER_DATA_GS_23                                                                   0x1a43
3795 #define regSPI_SHADER_USER_DATA_GS_23_BASE_IDX                                                          0
3796 #define regSPI_SHADER_USER_DATA_GS_24                                                                   0x1a44
3797 #define regSPI_SHADER_USER_DATA_GS_24_BASE_IDX                                                          0
3798 #define regSPI_SHADER_USER_DATA_GS_25                                                                   0x1a45
3799 #define regSPI_SHADER_USER_DATA_GS_25_BASE_IDX                                                          0
3800 #define regSPI_SHADER_USER_DATA_GS_26                                                                   0x1a46
3801 #define regSPI_SHADER_USER_DATA_GS_26_BASE_IDX                                                          0
3802 #define regSPI_SHADER_USER_DATA_GS_27                                                                   0x1a47
3803 #define regSPI_SHADER_USER_DATA_GS_27_BASE_IDX                                                          0
3804 #define regSPI_SHADER_USER_DATA_GS_28                                                                   0x1a48
3805 #define regSPI_SHADER_USER_DATA_GS_28_BASE_IDX                                                          0
3806 #define regSPI_SHADER_USER_DATA_GS_29                                                                   0x1a49
3807 #define regSPI_SHADER_USER_DATA_GS_29_BASE_IDX                                                          0
3808 #define regSPI_SHADER_USER_DATA_GS_30                                                                   0x1a4a
3809 #define regSPI_SHADER_USER_DATA_GS_30_BASE_IDX                                                          0
3810 #define regSPI_SHADER_USER_DATA_GS_31                                                                   0x1a4b
3811 #define regSPI_SHADER_USER_DATA_GS_31_BASE_IDX                                                          0
3812 #define regSPI_SHADER_GS_MESHLET_DIM                                                                    0x1a4c
3813 #define regSPI_SHADER_GS_MESHLET_DIM_BASE_IDX                                                           0
3814 #define regSPI_SHADER_GS_MESHLET_EXP_ALLOC                                                              0x1a4d
3815 #define regSPI_SHADER_GS_MESHLET_EXP_ALLOC_BASE_IDX                                                     0
3816 #define regSPI_SHADER_REQ_CTRL_ESGS                                                                     0x1a50
3817 #define regSPI_SHADER_REQ_CTRL_ESGS_BASE_IDX                                                            0
3818 #define regSPI_SHADER_USER_ACCUM_ESGS_0                                                                 0x1a52
3819 #define regSPI_SHADER_USER_ACCUM_ESGS_0_BASE_IDX                                                        0
3820 #define regSPI_SHADER_USER_ACCUM_ESGS_1                                                                 0x1a53
3821 #define regSPI_SHADER_USER_ACCUM_ESGS_1_BASE_IDX                                                        0
3822 #define regSPI_SHADER_USER_ACCUM_ESGS_2                                                                 0x1a54
3823 #define regSPI_SHADER_USER_ACCUM_ESGS_2_BASE_IDX                                                        0
3824 #define regSPI_SHADER_USER_ACCUM_ESGS_3                                                                 0x1a55
3825 #define regSPI_SHADER_USER_ACCUM_ESGS_3_BASE_IDX                                                        0
3826 #define regSPI_SHADER_PGM_LO_ES                                                                         0x1a68
3827 #define regSPI_SHADER_PGM_LO_ES_BASE_IDX                                                                0
3828 #define regSPI_SHADER_PGM_HI_ES                                                                         0x1a69
3829 #define regSPI_SHADER_PGM_HI_ES_BASE_IDX                                                                0
3830 #define regSPI_SHADER_PGM_CHKSUM_HS                                                                     0x1aa0
3831 #define regSPI_SHADER_PGM_CHKSUM_HS_BASE_IDX                                                            0
3832 #define regSPI_SHADER_PGM_RSRC4_HS                                                                      0x1aa1
3833 #define regSPI_SHADER_PGM_RSRC4_HS_BASE_IDX                                                             0
3834 #define regSPI_SHADER_USER_DATA_ADDR_LO_HS                                                              0x1aa2
3835 #define regSPI_SHADER_USER_DATA_ADDR_LO_HS_BASE_IDX                                                     0
3836 #define regSPI_SHADER_USER_DATA_ADDR_HI_HS                                                              0x1aa3
3837 #define regSPI_SHADER_USER_DATA_ADDR_HI_HS_BASE_IDX                                                     0
3838 #define regSPI_SHADER_PGM_LO_LS_HS                                                                      0x1aa4
3839 #define regSPI_SHADER_PGM_LO_LS_HS_BASE_IDX                                                             0
3840 #define regSPI_SHADER_PGM_HI_LS_HS                                                                      0x1aa5
3841 #define regSPI_SHADER_PGM_HI_LS_HS_BASE_IDX                                                             0
3842 #define regSPI_SHADER_PGM_RSRC3_HS                                                                      0x1aa7
3843 #define regSPI_SHADER_PGM_RSRC3_HS_BASE_IDX                                                             0
3844 #define regSPI_SHADER_PGM_LO_HS                                                                         0x1aa8
3845 #define regSPI_SHADER_PGM_LO_HS_BASE_IDX                                                                0
3846 #define regSPI_SHADER_PGM_HI_HS                                                                         0x1aa9
3847 #define regSPI_SHADER_PGM_HI_HS_BASE_IDX                                                                0
3848 #define regSPI_SHADER_PGM_RSRC1_HS                                                                      0x1aaa
3849 #define regSPI_SHADER_PGM_RSRC1_HS_BASE_IDX                                                             0
3850 #define regSPI_SHADER_PGM_RSRC2_HS                                                                      0x1aab
3851 #define regSPI_SHADER_PGM_RSRC2_HS_BASE_IDX                                                             0
3852 #define regSPI_SHADER_USER_DATA_HS_0                                                                    0x1aac
3853 #define regSPI_SHADER_USER_DATA_HS_0_BASE_IDX                                                           0
3854 #define regSPI_SHADER_USER_DATA_HS_1                                                                    0x1aad
3855 #define regSPI_SHADER_USER_DATA_HS_1_BASE_IDX                                                           0
3856 #define regSPI_SHADER_USER_DATA_HS_2                                                                    0x1aae
3857 #define regSPI_SHADER_USER_DATA_HS_2_BASE_IDX                                                           0
3858 #define regSPI_SHADER_USER_DATA_HS_3                                                                    0x1aaf
3859 #define regSPI_SHADER_USER_DATA_HS_3_BASE_IDX                                                           0
3860 #define regSPI_SHADER_USER_DATA_HS_4                                                                    0x1ab0
3861 #define regSPI_SHADER_USER_DATA_HS_4_BASE_IDX                                                           0
3862 #define regSPI_SHADER_USER_DATA_HS_5                                                                    0x1ab1
3863 #define regSPI_SHADER_USER_DATA_HS_5_BASE_IDX                                                           0
3864 #define regSPI_SHADER_USER_DATA_HS_6                                                                    0x1ab2
3865 #define regSPI_SHADER_USER_DATA_HS_6_BASE_IDX                                                           0
3866 #define regSPI_SHADER_USER_DATA_HS_7                                                                    0x1ab3
3867 #define regSPI_SHADER_USER_DATA_HS_7_BASE_IDX                                                           0
3868 #define regSPI_SHADER_USER_DATA_HS_8                                                                    0x1ab4
3869 #define regSPI_SHADER_USER_DATA_HS_8_BASE_IDX                                                           0
3870 #define regSPI_SHADER_USER_DATA_HS_9                                                                    0x1ab5
3871 #define regSPI_SHADER_USER_DATA_HS_9_BASE_IDX                                                           0
3872 #define regSPI_SHADER_USER_DATA_HS_10                                                                   0x1ab6
3873 #define regSPI_SHADER_USER_DATA_HS_10_BASE_IDX                                                          0
3874 #define regSPI_SHADER_USER_DATA_HS_11                                                                   0x1ab7
3875 #define regSPI_SHADER_USER_DATA_HS_11_BASE_IDX                                                          0
3876 #define regSPI_SHADER_USER_DATA_HS_12                                                                   0x1ab8
3877 #define regSPI_SHADER_USER_DATA_HS_12_BASE_IDX                                                          0
3878 #define regSPI_SHADER_USER_DATA_HS_13                                                                   0x1ab9
3879 #define regSPI_SHADER_USER_DATA_HS_13_BASE_IDX                                                          0
3880 #define regSPI_SHADER_USER_DATA_HS_14                                                                   0x1aba
3881 #define regSPI_SHADER_USER_DATA_HS_14_BASE_IDX                                                          0
3882 #define regSPI_SHADER_USER_DATA_HS_15                                                                   0x1abb
3883 #define regSPI_SHADER_USER_DATA_HS_15_BASE_IDX                                                          0
3884 #define regSPI_SHADER_USER_DATA_HS_16                                                                   0x1abc
3885 #define regSPI_SHADER_USER_DATA_HS_16_BASE_IDX                                                          0
3886 #define regSPI_SHADER_USER_DATA_HS_17                                                                   0x1abd
3887 #define regSPI_SHADER_USER_DATA_HS_17_BASE_IDX                                                          0
3888 #define regSPI_SHADER_USER_DATA_HS_18                                                                   0x1abe
3889 #define regSPI_SHADER_USER_DATA_HS_18_BASE_IDX                                                          0
3890 #define regSPI_SHADER_USER_DATA_HS_19                                                                   0x1abf
3891 #define regSPI_SHADER_USER_DATA_HS_19_BASE_IDX                                                          0
3892 #define regSPI_SHADER_USER_DATA_HS_20                                                                   0x1ac0
3893 #define regSPI_SHADER_USER_DATA_HS_20_BASE_IDX                                                          0
3894 #define regSPI_SHADER_USER_DATA_HS_21                                                                   0x1ac1
3895 #define regSPI_SHADER_USER_DATA_HS_21_BASE_IDX                                                          0
3896 #define regSPI_SHADER_USER_DATA_HS_22                                                                   0x1ac2
3897 #define regSPI_SHADER_USER_DATA_HS_22_BASE_IDX                                                          0
3898 #define regSPI_SHADER_USER_DATA_HS_23                                                                   0x1ac3
3899 #define regSPI_SHADER_USER_DATA_HS_23_BASE_IDX                                                          0
3900 #define regSPI_SHADER_USER_DATA_HS_24                                                                   0x1ac4
3901 #define regSPI_SHADER_USER_DATA_HS_24_BASE_IDX                                                          0
3902 #define regSPI_SHADER_USER_DATA_HS_25                                                                   0x1ac5
3903 #define regSPI_SHADER_USER_DATA_HS_25_BASE_IDX                                                          0
3904 #define regSPI_SHADER_USER_DATA_HS_26                                                                   0x1ac6
3905 #define regSPI_SHADER_USER_DATA_HS_26_BASE_IDX                                                          0
3906 #define regSPI_SHADER_USER_DATA_HS_27                                                                   0x1ac7
3907 #define regSPI_SHADER_USER_DATA_HS_27_BASE_IDX                                                          0
3908 #define regSPI_SHADER_USER_DATA_HS_28                                                                   0x1ac8
3909 #define regSPI_SHADER_USER_DATA_HS_28_BASE_IDX                                                          0
3910 #define regSPI_SHADER_USER_DATA_HS_29                                                                   0x1ac9
3911 #define regSPI_SHADER_USER_DATA_HS_29_BASE_IDX                                                          0
3912 #define regSPI_SHADER_USER_DATA_HS_30                                                                   0x1aca
3913 #define regSPI_SHADER_USER_DATA_HS_30_BASE_IDX                                                          0
3914 #define regSPI_SHADER_USER_DATA_HS_31                                                                   0x1acb
3915 #define regSPI_SHADER_USER_DATA_HS_31_BASE_IDX                                                          0
3916 #define regSPI_SHADER_REQ_CTRL_LSHS                                                                     0x1ad0
3917 #define regSPI_SHADER_REQ_CTRL_LSHS_BASE_IDX                                                            0
3918 #define regSPI_SHADER_USER_ACCUM_LSHS_0                                                                 0x1ad2
3919 #define regSPI_SHADER_USER_ACCUM_LSHS_0_BASE_IDX                                                        0
3920 #define regSPI_SHADER_USER_ACCUM_LSHS_1                                                                 0x1ad3
3921 #define regSPI_SHADER_USER_ACCUM_LSHS_1_BASE_IDX                                                        0
3922 #define regSPI_SHADER_USER_ACCUM_LSHS_2                                                                 0x1ad4
3923 #define regSPI_SHADER_USER_ACCUM_LSHS_2_BASE_IDX                                                        0
3924 #define regSPI_SHADER_USER_ACCUM_LSHS_3                                                                 0x1ad5
3925 #define regSPI_SHADER_USER_ACCUM_LSHS_3_BASE_IDX                                                        0
3926 #define regSPI_SHADER_PGM_LO_LS                                                                         0x1ae8
3927 #define regSPI_SHADER_PGM_LO_LS_BASE_IDX                                                                0
3928 #define regSPI_SHADER_PGM_HI_LS                                                                         0x1ae9
3929 #define regSPI_SHADER_PGM_HI_LS_BASE_IDX                                                                0
3930 #define regCOMPUTE_DISPATCH_INITIATOR                                                                   0x1ba0
3931 #define regCOMPUTE_DISPATCH_INITIATOR_BASE_IDX                                                          0
3932 #define regCOMPUTE_DIM_X                                                                                0x1ba1
3933 #define regCOMPUTE_DIM_X_BASE_IDX                                                                       0
3934 #define regCOMPUTE_DIM_Y                                                                                0x1ba2
3935 #define regCOMPUTE_DIM_Y_BASE_IDX                                                                       0
3936 #define regCOMPUTE_DIM_Z                                                                                0x1ba3
3937 #define regCOMPUTE_DIM_Z_BASE_IDX                                                                       0
3938 #define regCOMPUTE_START_X                                                                              0x1ba4
3939 #define regCOMPUTE_START_X_BASE_IDX                                                                     0
3940 #define regCOMPUTE_START_Y                                                                              0x1ba5
3941 #define regCOMPUTE_START_Y_BASE_IDX                                                                     0
3942 #define regCOMPUTE_START_Z                                                                              0x1ba6
3943 #define regCOMPUTE_START_Z_BASE_IDX                                                                     0
3944 #define regCOMPUTE_NUM_THREAD_X                                                                         0x1ba7
3945 #define regCOMPUTE_NUM_THREAD_X_BASE_IDX                                                                0
3946 #define regCOMPUTE_NUM_THREAD_Y                                                                         0x1ba8
3947 #define regCOMPUTE_NUM_THREAD_Y_BASE_IDX                                                                0
3948 #define regCOMPUTE_NUM_THREAD_Z                                                                         0x1ba9
3949 #define regCOMPUTE_NUM_THREAD_Z_BASE_IDX                                                                0
3950 #define regCOMPUTE_PIPELINESTAT_ENABLE                                                                  0x1baa
3951 #define regCOMPUTE_PIPELINESTAT_ENABLE_BASE_IDX                                                         0
3952 #define regCOMPUTE_PERFCOUNT_ENABLE                                                                     0x1bab
3953 #define regCOMPUTE_PERFCOUNT_ENABLE_BASE_IDX                                                            0
3954 #define regCOMPUTE_PGM_LO                                                                               0x1bac
3955 #define regCOMPUTE_PGM_LO_BASE_IDX                                                                      0
3956 #define regCOMPUTE_PGM_HI                                                                               0x1bad
3957 #define regCOMPUTE_PGM_HI_BASE_IDX                                                                      0
3958 #define regCOMPUTE_DISPATCH_PKT_ADDR_LO                                                                 0x1bae
3959 #define regCOMPUTE_DISPATCH_PKT_ADDR_LO_BASE_IDX                                                        0
3960 #define regCOMPUTE_DISPATCH_PKT_ADDR_HI                                                                 0x1baf
3961 #define regCOMPUTE_DISPATCH_PKT_ADDR_HI_BASE_IDX                                                        0
3962 #define regCOMPUTE_DISPATCH_SCRATCH_BASE_LO                                                             0x1bb0
3963 #define regCOMPUTE_DISPATCH_SCRATCH_BASE_LO_BASE_IDX                                                    0
3964 #define regCOMPUTE_DISPATCH_SCRATCH_BASE_HI                                                             0x1bb1
3965 #define regCOMPUTE_DISPATCH_SCRATCH_BASE_HI_BASE_IDX                                                    0
3966 #define regCOMPUTE_PGM_RSRC1                                                                            0x1bb2
3967 #define regCOMPUTE_PGM_RSRC1_BASE_IDX                                                                   0
3968 #define regCOMPUTE_PGM_RSRC2                                                                            0x1bb3
3969 #define regCOMPUTE_PGM_RSRC2_BASE_IDX                                                                   0
3970 #define regCOMPUTE_VMID                                                                                 0x1bb4
3971 #define regCOMPUTE_VMID_BASE_IDX                                                                        0
3972 #define regCOMPUTE_RESOURCE_LIMITS                                                                      0x1bb5
3973 #define regCOMPUTE_RESOURCE_LIMITS_BASE_IDX                                                             0
3974 #define regCOMPUTE_DESTINATION_EN_SE0                                                                   0x1bb6
3975 #define regCOMPUTE_DESTINATION_EN_SE0_BASE_IDX                                                          0
3976 #define regCOMPUTE_STATIC_THREAD_MGMT_SE0                                                               0x1bb6
3977 #define regCOMPUTE_STATIC_THREAD_MGMT_SE0_BASE_IDX                                                      0
3978 #define regCOMPUTE_DESTINATION_EN_SE1                                                                   0x1bb7
3979 #define regCOMPUTE_DESTINATION_EN_SE1_BASE_IDX                                                          0
3980 #define regCOMPUTE_STATIC_THREAD_MGMT_SE1                                                               0x1bb7
3981 #define regCOMPUTE_STATIC_THREAD_MGMT_SE1_BASE_IDX                                                      0
3982 #define regCOMPUTE_TMPRING_SIZE                                                                         0x1bb8
3983 #define regCOMPUTE_TMPRING_SIZE_BASE_IDX                                                                0
3984 #define regCOMPUTE_DESTINATION_EN_SE2                                                                   0x1bb9
3985 #define regCOMPUTE_DESTINATION_EN_SE2_BASE_IDX                                                          0
3986 #define regCOMPUTE_STATIC_THREAD_MGMT_SE2                                                               0x1bb9
3987 #define regCOMPUTE_STATIC_THREAD_MGMT_SE2_BASE_IDX                                                      0
3988 #define regCOMPUTE_DESTINATION_EN_SE3                                                                   0x1bba
3989 #define regCOMPUTE_DESTINATION_EN_SE3_BASE_IDX                                                          0
3990 #define regCOMPUTE_STATIC_THREAD_MGMT_SE3                                                               0x1bba
3991 #define regCOMPUTE_STATIC_THREAD_MGMT_SE3_BASE_IDX                                                      0
3992 #define regCOMPUTE_RESTART_X                                                                            0x1bbb
3993 #define regCOMPUTE_RESTART_X_BASE_IDX                                                                   0
3994 #define regCOMPUTE_RESTART_Y                                                                            0x1bbc
3995 #define regCOMPUTE_RESTART_Y_BASE_IDX                                                                   0
3996 #define regCOMPUTE_RESTART_Z                                                                            0x1bbd
3997 #define regCOMPUTE_RESTART_Z_BASE_IDX                                                                   0
3998 #define regCOMPUTE_THREAD_TRACE_ENABLE                                                                  0x1bbe
3999 #define regCOMPUTE_THREAD_TRACE_ENABLE_BASE_IDX                                                         0
4000 #define regCOMPUTE_MISC_RESERVED                                                                        0x1bbf
4001 #define regCOMPUTE_MISC_RESERVED_BASE_IDX                                                               0
4002 #define regCOMPUTE_DISPATCH_ID                                                                          0x1bc0
4003 #define regCOMPUTE_DISPATCH_ID_BASE_IDX                                                                 0
4004 #define regCOMPUTE_THREADGROUP_ID                                                                       0x1bc1
4005 #define regCOMPUTE_THREADGROUP_ID_BASE_IDX                                                              0
4006 #define regCOMPUTE_REQ_CTRL                                                                             0x1bc2
4007 #define regCOMPUTE_REQ_CTRL_BASE_IDX                                                                    0
4008 #define regCOMPUTE_USER_ACCUM_0                                                                         0x1bc4
4009 #define regCOMPUTE_USER_ACCUM_0_BASE_IDX                                                                0
4010 #define regCOMPUTE_USER_ACCUM_1                                                                         0x1bc5
4011 #define regCOMPUTE_USER_ACCUM_1_BASE_IDX                                                                0
4012 #define regCOMPUTE_USER_ACCUM_2                                                                         0x1bc6
4013 #define regCOMPUTE_USER_ACCUM_2_BASE_IDX                                                                0
4014 #define regCOMPUTE_USER_ACCUM_3                                                                         0x1bc7
4015 #define regCOMPUTE_USER_ACCUM_3_BASE_IDX                                                                0
4016 #define regCOMPUTE_PGM_RSRC3                                                                            0x1bc8
4017 #define regCOMPUTE_PGM_RSRC3_BASE_IDX                                                                   0
4018 #define regCOMPUTE_DDID_INDEX                                                                           0x1bc9
4019 #define regCOMPUTE_DDID_INDEX_BASE_IDX                                                                  0
4020 #define regCOMPUTE_SHADER_CHKSUM                                                                        0x1bca
4021 #define regCOMPUTE_SHADER_CHKSUM_BASE_IDX                                                               0
4022 #define regCOMPUTE_STATIC_THREAD_MGMT_SE4                                                               0x1bcb
4023 #define regCOMPUTE_STATIC_THREAD_MGMT_SE4_BASE_IDX                                                      0
4024 #define regCOMPUTE_STATIC_THREAD_MGMT_SE5                                                               0x1bcc
4025 #define regCOMPUTE_STATIC_THREAD_MGMT_SE5_BASE_IDX                                                      0
4026 #define regCOMPUTE_STATIC_THREAD_MGMT_SE6                                                               0x1bcd
4027 #define regCOMPUTE_STATIC_THREAD_MGMT_SE6_BASE_IDX                                                      0
4028 #define regCOMPUTE_STATIC_THREAD_MGMT_SE7                                                               0x1bce
4029 #define regCOMPUTE_STATIC_THREAD_MGMT_SE7_BASE_IDX                                                      0
4030 #define regCOMPUTE_DISPATCH_INTERLEAVE                                                                  0x1bcf
4031 #define regCOMPUTE_DISPATCH_INTERLEAVE_BASE_IDX                                                         0
4032 #define regCOMPUTE_RELAUNCH                                                                             0x1bd0
4033 #define regCOMPUTE_RELAUNCH_BASE_IDX                                                                    0
4034 #define regCOMPUTE_WAVE_RESTORE_ADDR_LO                                                                 0x1bd1
4035 #define regCOMPUTE_WAVE_RESTORE_ADDR_LO_BASE_IDX                                                        0
4036 #define regCOMPUTE_WAVE_RESTORE_ADDR_HI                                                                 0x1bd2
4037 #define regCOMPUTE_WAVE_RESTORE_ADDR_HI_BASE_IDX                                                        0
4038 #define regCOMPUTE_RELAUNCH2                                                                            0x1bd3
4039 #define regCOMPUTE_RELAUNCH2_BASE_IDX                                                                   0
4040 #define regCOMPUTE_USER_DATA_0                                                                          0x1be0
4041 #define regCOMPUTE_USER_DATA_0_BASE_IDX                                                                 0
4042 #define regCOMPUTE_USER_DATA_1                                                                          0x1be1
4043 #define regCOMPUTE_USER_DATA_1_BASE_IDX                                                                 0
4044 #define regCOMPUTE_USER_DATA_2                                                                          0x1be2
4045 #define regCOMPUTE_USER_DATA_2_BASE_IDX                                                                 0
4046 #define regCOMPUTE_USER_DATA_3                                                                          0x1be3
4047 #define regCOMPUTE_USER_DATA_3_BASE_IDX                                                                 0
4048 #define regCOMPUTE_USER_DATA_4                                                                          0x1be4
4049 #define regCOMPUTE_USER_DATA_4_BASE_IDX                                                                 0
4050 #define regCOMPUTE_USER_DATA_5                                                                          0x1be5
4051 #define regCOMPUTE_USER_DATA_5_BASE_IDX                                                                 0
4052 #define regCOMPUTE_USER_DATA_6                                                                          0x1be6
4053 #define regCOMPUTE_USER_DATA_6_BASE_IDX                                                                 0
4054 #define regCOMPUTE_USER_DATA_7                                                                          0x1be7
4055 #define regCOMPUTE_USER_DATA_7_BASE_IDX                                                                 0
4056 #define regCOMPUTE_USER_DATA_8                                                                          0x1be8
4057 #define regCOMPUTE_USER_DATA_8_BASE_IDX                                                                 0
4058 #define regCOMPUTE_USER_DATA_9                                                                          0x1be9
4059 #define regCOMPUTE_USER_DATA_9_BASE_IDX                                                                 0
4060 #define regCOMPUTE_USER_DATA_10                                                                         0x1bea
4061 #define regCOMPUTE_USER_DATA_10_BASE_IDX                                                                0
4062 #define regCOMPUTE_USER_DATA_11                                                                         0x1beb
4063 #define regCOMPUTE_USER_DATA_11_BASE_IDX                                                                0
4064 #define regCOMPUTE_USER_DATA_12                                                                         0x1bec
4065 #define regCOMPUTE_USER_DATA_12_BASE_IDX                                                                0
4066 #define regCOMPUTE_USER_DATA_13                                                                         0x1bed
4067 #define regCOMPUTE_USER_DATA_13_BASE_IDX                                                                0
4068 #define regCOMPUTE_USER_DATA_14                                                                         0x1bee
4069 #define regCOMPUTE_USER_DATA_14_BASE_IDX                                                                0
4070 #define regCOMPUTE_USER_DATA_15                                                                         0x1bef
4071 #define regCOMPUTE_USER_DATA_15_BASE_IDX                                                                0
4072 #define regCOMPUTE_DISPATCH_TUNNEL                                                                      0x1c1d
4073 #define regCOMPUTE_DISPATCH_TUNNEL_BASE_IDX                                                             0
4074 #define regCOMPUTE_DISPATCH_END                                                                         0x1c1e
4075 #define regCOMPUTE_DISPATCH_END_BASE_IDX                                                                0
4076 #define regCOMPUTE_NOWHERE                                                                              0x1c1f
4077 #define regCOMPUTE_NOWHERE_BASE_IDX                                                                     0
4078 #define regSH_RESERVED_REG0                                                                             0x1c20
4079 #define regSH_RESERVED_REG0_BASE_IDX                                                                    0
4080 #define regSH_RESERVED_REG1                                                                             0x1c21
4081 #define regSH_RESERVED_REG1_BASE_IDX                                                                    0
4082 
4083 
4084 // addressBlock: gc_cppdec
4085 // base address: 0xc080
4086 #define regCP_CU_MASK_ADDR_LO                                                                           0x1dd2
4087 #define regCP_CU_MASK_ADDR_LO_BASE_IDX                                                                  0
4088 #define regCP_CU_MASK_ADDR_HI                                                                           0x1dd3
4089 #define regCP_CU_MASK_ADDR_HI_BASE_IDX                                                                  0
4090 #define regCP_CU_MASK_CNTL                                                                              0x1dd4
4091 #define regCP_CU_MASK_CNTL_BASE_IDX                                                                     0
4092 #define regCP_EOPQ_WAIT_TIME                                                                            0x1dd5
4093 #define regCP_EOPQ_WAIT_TIME_BASE_IDX                                                                   0
4094 #define regCP_CPC_MGCG_SYNC_CNTL                                                                        0x1dd6
4095 #define regCP_CPC_MGCG_SYNC_CNTL_BASE_IDX                                                               0
4096 #define regCPC_INT_INFO                                                                                 0x1dd7
4097 #define regCPC_INT_INFO_BASE_IDX                                                                        0
4098 #define regCP_VIRT_STATUS                                                                               0x1dd8
4099 #define regCP_VIRT_STATUS_BASE_IDX                                                                      0
4100 #define regCPC_INT_ADDR                                                                                 0x1dd9
4101 #define regCPC_INT_ADDR_BASE_IDX                                                                        0
4102 #define regCPC_INT_PASID                                                                                0x1dda
4103 #define regCPC_INT_PASID_BASE_IDX                                                                       0
4104 #define regCP_GFX_ERROR                                                                                 0x1ddb
4105 #define regCP_GFX_ERROR_BASE_IDX                                                                        0
4106 #define regCPG_UTCL1_CNTL                                                                               0x1ddc
4107 #define regCPG_UTCL1_CNTL_BASE_IDX                                                                      0
4108 #define regCPC_UTCL1_CNTL                                                                               0x1ddd
4109 #define regCPC_UTCL1_CNTL_BASE_IDX                                                                      0
4110 #define regCPF_UTCL1_CNTL                                                                               0x1dde
4111 #define regCPF_UTCL1_CNTL_BASE_IDX                                                                      0
4112 #define regCP_AQL_SMM_STATUS                                                                            0x1ddf
4113 #define regCP_AQL_SMM_STATUS_BASE_IDX                                                                   0
4114 #define regCP_RB0_BASE                                                                                  0x1de0
4115 #define regCP_RB0_BASE_BASE_IDX                                                                         0
4116 #define regCP_RB_BASE                                                                                   0x1de0
4117 #define regCP_RB_BASE_BASE_IDX                                                                          0
4118 #define regCP_RB0_CNTL                                                                                  0x1de1
4119 #define regCP_RB0_CNTL_BASE_IDX                                                                         0
4120 #define regCP_RB_CNTL                                                                                   0x1de1
4121 #define regCP_RB_CNTL_BASE_IDX                                                                          0
4122 #define regCP_RB_RPTR_WR                                                                                0x1de2
4123 #define regCP_RB_RPTR_WR_BASE_IDX                                                                       0
4124 #define regCP_RB0_RPTR_ADDR                                                                             0x1de3
4125 #define regCP_RB0_RPTR_ADDR_BASE_IDX                                                                    0
4126 #define regCP_RB_RPTR_ADDR                                                                              0x1de3
4127 #define regCP_RB_RPTR_ADDR_BASE_IDX                                                                     0
4128 #define regCP_RB0_RPTR_ADDR_HI                                                                          0x1de4
4129 #define regCP_RB0_RPTR_ADDR_HI_BASE_IDX                                                                 0
4130 #define regCP_RB_RPTR_ADDR_HI                                                                           0x1de4
4131 #define regCP_RB_RPTR_ADDR_HI_BASE_IDX                                                                  0
4132 #define regCP_RB0_BUFSZ_MASK                                                                            0x1de5
4133 #define regCP_RB0_BUFSZ_MASK_BASE_IDX                                                                   0
4134 #define regCP_RB_BUFSZ_MASK                                                                             0x1de5
4135 #define regCP_RB_BUFSZ_MASK_BASE_IDX                                                                    0
4136 #define regCP_INT_CNTL                                                                                  0x1de9
4137 #define regCP_INT_CNTL_BASE_IDX                                                                         0
4138 #define regCP_INT_STATUS                                                                                0x1dea
4139 #define regCP_INT_STATUS_BASE_IDX                                                                       0
4140 #define regCP_DEVICE_ID                                                                                 0x1deb
4141 #define regCP_DEVICE_ID_BASE_IDX                                                                        0
4142 #define regCP_ME0_PIPE_PRIORITY_CNTS                                                                    0x1dec
4143 #define regCP_ME0_PIPE_PRIORITY_CNTS_BASE_IDX                                                           0
4144 #define regCP_RING_PRIORITY_CNTS                                                                        0x1dec
4145 #define regCP_RING_PRIORITY_CNTS_BASE_IDX                                                               0
4146 #define regCP_ME0_PIPE0_PRIORITY                                                                        0x1ded
4147 #define regCP_ME0_PIPE0_PRIORITY_BASE_IDX                                                               0
4148 #define regCP_RING0_PRIORITY                                                                            0x1ded
4149 #define regCP_RING0_PRIORITY_BASE_IDX                                                                   0
4150 #define regCP_ME0_PIPE1_PRIORITY                                                                        0x1dee
4151 #define regCP_ME0_PIPE1_PRIORITY_BASE_IDX                                                               0
4152 #define regCP_RING1_PRIORITY                                                                            0x1dee
4153 #define regCP_RING1_PRIORITY_BASE_IDX                                                                   0
4154 #define regCP_FATAL_ERROR                                                                               0x1df0
4155 #define regCP_FATAL_ERROR_BASE_IDX                                                                      0
4156 #define regCP_RB_VMID                                                                                   0x1df1
4157 #define regCP_RB_VMID_BASE_IDX                                                                          0
4158 #define regCP_ME0_PIPE0_VMID                                                                            0x1df2
4159 #define regCP_ME0_PIPE0_VMID_BASE_IDX                                                                   0
4160 #define regCP_ME0_PIPE1_VMID                                                                            0x1df3
4161 #define regCP_ME0_PIPE1_VMID_BASE_IDX                                                                   0
4162 #define regCP_RB0_WPTR                                                                                  0x1df4
4163 #define regCP_RB0_WPTR_BASE_IDX                                                                         0
4164 #define regCP_RB_WPTR                                                                                   0x1df4
4165 #define regCP_RB_WPTR_BASE_IDX                                                                          0
4166 #define regCP_RB0_WPTR_HI                                                                               0x1df5
4167 #define regCP_RB0_WPTR_HI_BASE_IDX                                                                      0
4168 #define regCP_RB_WPTR_HI                                                                                0x1df5
4169 #define regCP_RB_WPTR_HI_BASE_IDX                                                                       0
4170 #define regCP_RB1_WPTR                                                                                  0x1df6
4171 #define regCP_RB1_WPTR_BASE_IDX                                                                         0
4172 #define regCP_RB1_WPTR_HI                                                                               0x1df7
4173 #define regCP_RB1_WPTR_HI_BASE_IDX                                                                      0
4174 #define regCP_PROCESS_QUANTUM                                                                           0x1df9
4175 #define regCP_PROCESS_QUANTUM_BASE_IDX                                                                  0
4176 #define regCP_RB_DOORBELL_RANGE_LOWER                                                                   0x1dfa
4177 #define regCP_RB_DOORBELL_RANGE_LOWER_BASE_IDX                                                          0
4178 #define regCP_RB_DOORBELL_RANGE_UPPER                                                                   0x1dfb
4179 #define regCP_RB_DOORBELL_RANGE_UPPER_BASE_IDX                                                          0
4180 #define regCP_MEC_DOORBELL_RANGE_LOWER                                                                  0x1dfc
4181 #define regCP_MEC_DOORBELL_RANGE_LOWER_BASE_IDX                                                         0
4182 #define regCP_MEC_DOORBELL_RANGE_UPPER                                                                  0x1dfd
4183 #define regCP_MEC_DOORBELL_RANGE_UPPER_BASE_IDX                                                         0
4184 #define regCPG_UTCL1_ERROR                                                                              0x1dfe
4185 #define regCPG_UTCL1_ERROR_BASE_IDX                                                                     0
4186 #define regCPC_UTCL1_ERROR                                                                              0x1dff
4187 #define regCPC_UTCL1_ERROR_BASE_IDX                                                                     0
4188 #define regCP_RB1_BASE                                                                                  0x1e00
4189 #define regCP_RB1_BASE_BASE_IDX                                                                         0
4190 #define regCP_RB1_CNTL                                                                                  0x1e01
4191 #define regCP_RB1_CNTL_BASE_IDX                                                                         0
4192 #define regCP_RB1_RPTR_ADDR                                                                             0x1e02
4193 #define regCP_RB1_RPTR_ADDR_BASE_IDX                                                                    0
4194 #define regCP_RB1_RPTR_ADDR_HI                                                                          0x1e03
4195 #define regCP_RB1_RPTR_ADDR_HI_BASE_IDX                                                                 0
4196 #define regCP_RB1_BUFSZ_MASK                                                                            0x1e04
4197 #define regCP_RB1_BUFSZ_MASK_BASE_IDX                                                                   0
4198 #define regCP_INT_CNTL_RING0                                                                            0x1e0a
4199 #define regCP_INT_CNTL_RING0_BASE_IDX                                                                   0
4200 #define regCP_INT_CNTL_RING1                                                                            0x1e0b
4201 #define regCP_INT_CNTL_RING1_BASE_IDX                                                                   0
4202 #define regCP_INT_STATUS_RING0                                                                          0x1e0d
4203 #define regCP_INT_STATUS_RING0_BASE_IDX                                                                 0
4204 #define regCP_INT_STATUS_RING1                                                                          0x1e0e
4205 #define regCP_INT_STATUS_RING1_BASE_IDX                                                                 0
4206 #define regCP_ME_F32_INTERRUPT                                                                          0x1e13
4207 #define regCP_ME_F32_INTERRUPT_BASE_IDX                                                                 0
4208 #define regCP_PFP_F32_INTERRUPT                                                                         0x1e14
4209 #define regCP_PFP_F32_INTERRUPT_BASE_IDX                                                                0
4210 #define regCP_MEC1_F32_INTERRUPT                                                                        0x1e16
4211 #define regCP_MEC1_F32_INTERRUPT_BASE_IDX                                                               0
4212 #define regCP_MEC2_F32_INTERRUPT                                                                        0x1e17
4213 #define regCP_MEC2_F32_INTERRUPT_BASE_IDX                                                               0
4214 #define regCP_PWR_CNTL                                                                                  0x1e18
4215 #define regCP_PWR_CNTL_BASE_IDX                                                                         0
4216 #define regCP_ECC_FIRSTOCCURRENCE                                                                       0x1e1a
4217 #define regCP_ECC_FIRSTOCCURRENCE_BASE_IDX                                                              0
4218 #define regCP_ECC_FIRSTOCCURRENCE_RING0                                                                 0x1e1b
4219 #define regCP_ECC_FIRSTOCCURRENCE_RING0_BASE_IDX                                                        0
4220 #define regCP_ECC_FIRSTOCCURRENCE_RING1                                                                 0x1e1c
4221 #define regCP_ECC_FIRSTOCCURRENCE_RING1_BASE_IDX                                                        0
4222 #define regGB_EDC_MODE                                                                                  0x1e1e
4223 #define regGB_EDC_MODE_BASE_IDX                                                                         0
4224 #define regCP_DEBUG                                                                                     0x1e1f
4225 #define regCP_DEBUG_BASE_IDX                                                                            0
4226 #define regCP_CPC_DEBUG                                                                                 0x1e21
4227 #define regCP_CPC_DEBUG_BASE_IDX                                                                        0
4228 #define regCP_PQ_WPTR_POLL_CNTL                                                                         0x1e23
4229 #define regCP_PQ_WPTR_POLL_CNTL_BASE_IDX                                                                0
4230 #define regCP_PQ_WPTR_POLL_CNTL1                                                                        0x1e24
4231 #define regCP_PQ_WPTR_POLL_CNTL1_BASE_IDX                                                               0
4232 #define regCP_ME1_PIPE0_INT_CNTL                                                                        0x1e25
4233 #define regCP_ME1_PIPE0_INT_CNTL_BASE_IDX                                                               0
4234 #define regCP_ME1_PIPE1_INT_CNTL                                                                        0x1e26
4235 #define regCP_ME1_PIPE1_INT_CNTL_BASE_IDX                                                               0
4236 #define regCP_ME1_PIPE2_INT_CNTL                                                                        0x1e27
4237 #define regCP_ME1_PIPE2_INT_CNTL_BASE_IDX                                                               0
4238 #define regCP_ME1_PIPE3_INT_CNTL                                                                        0x1e28
4239 #define regCP_ME1_PIPE3_INT_CNTL_BASE_IDX                                                               0
4240 #define regCP_ME2_PIPE0_INT_CNTL                                                                        0x1e29
4241 #define regCP_ME2_PIPE0_INT_CNTL_BASE_IDX                                                               0
4242 #define regCP_ME2_PIPE1_INT_CNTL                                                                        0x1e2a
4243 #define regCP_ME2_PIPE1_INT_CNTL_BASE_IDX                                                               0
4244 #define regCP_ME2_PIPE2_INT_CNTL                                                                        0x1e2b
4245 #define regCP_ME2_PIPE2_INT_CNTL_BASE_IDX                                                               0
4246 #define regCP_ME2_PIPE3_INT_CNTL                                                                        0x1e2c
4247 #define regCP_ME2_PIPE3_INT_CNTL_BASE_IDX                                                               0
4248 #define regCP_ME1_PIPE0_INT_STATUS                                                                      0x1e2d
4249 #define regCP_ME1_PIPE0_INT_STATUS_BASE_IDX                                                             0
4250 #define regCP_ME1_PIPE1_INT_STATUS                                                                      0x1e2e
4251 #define regCP_ME1_PIPE1_INT_STATUS_BASE_IDX                                                             0
4252 #define regCP_ME1_PIPE2_INT_STATUS                                                                      0x1e2f
4253 #define regCP_ME1_PIPE2_INT_STATUS_BASE_IDX                                                             0
4254 #define regCP_ME1_PIPE3_INT_STATUS                                                                      0x1e30
4255 #define regCP_ME1_PIPE3_INT_STATUS_BASE_IDX                                                             0
4256 #define regCP_ME2_PIPE0_INT_STATUS                                                                      0x1e31
4257 #define regCP_ME2_PIPE0_INT_STATUS_BASE_IDX                                                             0
4258 #define regCP_ME2_PIPE1_INT_STATUS                                                                      0x1e32
4259 #define regCP_ME2_PIPE1_INT_STATUS_BASE_IDX                                                             0
4260 #define regCP_ME2_PIPE2_INT_STATUS                                                                      0x1e33
4261 #define regCP_ME2_PIPE2_INT_STATUS_BASE_IDX                                                             0
4262 #define regCP_ME2_PIPE3_INT_STATUS                                                                      0x1e34
4263 #define regCP_ME2_PIPE3_INT_STATUS_BASE_IDX                                                             0
4264 #define regCP_GFX_QUEUE_INDEX                                                                           0x1e37
4265 #define regCP_GFX_QUEUE_INDEX_BASE_IDX                                                                  0
4266 #define regCC_GC_EDC_CONFIG                                                                             0x1e38
4267 #define regCC_GC_EDC_CONFIG_BASE_IDX                                                                    0
4268 #define regCP_ME1_PIPE_PRIORITY_CNTS                                                                    0x1e39
4269 #define regCP_ME1_PIPE_PRIORITY_CNTS_BASE_IDX                                                           0
4270 #define regCP_ME1_PIPE0_PRIORITY                                                                        0x1e3a
4271 #define regCP_ME1_PIPE0_PRIORITY_BASE_IDX                                                               0
4272 #define regCP_ME1_PIPE1_PRIORITY                                                                        0x1e3b
4273 #define regCP_ME1_PIPE1_PRIORITY_BASE_IDX                                                               0
4274 #define regCP_ME1_PIPE2_PRIORITY                                                                        0x1e3c
4275 #define regCP_ME1_PIPE2_PRIORITY_BASE_IDX                                                               0
4276 #define regCP_ME1_PIPE3_PRIORITY                                                                        0x1e3d
4277 #define regCP_ME1_PIPE3_PRIORITY_BASE_IDX                                                               0
4278 #define regCP_ME2_PIPE_PRIORITY_CNTS                                                                    0x1e3e
4279 #define regCP_ME2_PIPE_PRIORITY_CNTS_BASE_IDX                                                           0
4280 #define regCP_ME2_PIPE0_PRIORITY                                                                        0x1e3f
4281 #define regCP_ME2_PIPE0_PRIORITY_BASE_IDX                                                               0
4282 #define regCP_ME2_PIPE1_PRIORITY                                                                        0x1e40
4283 #define regCP_ME2_PIPE1_PRIORITY_BASE_IDX                                                               0
4284 #define regCP_ME2_PIPE2_PRIORITY                                                                        0x1e41
4285 #define regCP_ME2_PIPE2_PRIORITY_BASE_IDX                                                               0
4286 #define regCP_ME2_PIPE3_PRIORITY                                                                        0x1e42
4287 #define regCP_ME2_PIPE3_PRIORITY_BASE_IDX                                                               0
4288 #define regCP_PFP_PRGRM_CNTR_START                                                                      0x1e44
4289 #define regCP_PFP_PRGRM_CNTR_START_BASE_IDX                                                             0
4290 #define regCP_ME_PRGRM_CNTR_START                                                                       0x1e45
4291 #define regCP_ME_PRGRM_CNTR_START_BASE_IDX                                                              0
4292 #define regCP_MEC1_PRGRM_CNTR_START                                                                     0x1e46
4293 #define regCP_MEC1_PRGRM_CNTR_START_BASE_IDX                                                            0
4294 #define regCP_MEC2_PRGRM_CNTR_START                                                                     0x1e47
4295 #define regCP_MEC2_PRGRM_CNTR_START_BASE_IDX                                                            0
4296 #define regCP_PFP_INTR_ROUTINE_START                                                                    0x1e49
4297 #define regCP_PFP_INTR_ROUTINE_START_BASE_IDX                                                           0
4298 #define regCP_ME_INTR_ROUTINE_START                                                                     0x1e4a
4299 #define regCP_ME_INTR_ROUTINE_START_BASE_IDX                                                            0
4300 #define regCP_MEC1_INTR_ROUTINE_START                                                                   0x1e4b
4301 #define regCP_MEC1_INTR_ROUTINE_START_BASE_IDX                                                          0
4302 #define regCP_MEC2_INTR_ROUTINE_START                                                                   0x1e4c
4303 #define regCP_MEC2_INTR_ROUTINE_START_BASE_IDX                                                          0
4304 #define regCP_CONTEXT_CNTL                                                                              0x1e4d
4305 #define regCP_CONTEXT_CNTL_BASE_IDX                                                                     0
4306 #define regCP_MAX_CONTEXT                                                                               0x1e4e
4307 #define regCP_MAX_CONTEXT_BASE_IDX                                                                      0
4308 #define regCP_IQ_WAIT_TIME1                                                                             0x1e4f
4309 #define regCP_IQ_WAIT_TIME1_BASE_IDX                                                                    0
4310 #define regCP_IQ_WAIT_TIME2                                                                             0x1e50
4311 #define regCP_IQ_WAIT_TIME2_BASE_IDX                                                                    0
4312 #define regCP_RB0_BASE_HI                                                                               0x1e51
4313 #define regCP_RB0_BASE_HI_BASE_IDX                                                                      0
4314 #define regCP_RB1_BASE_HI                                                                               0x1e52
4315 #define regCP_RB1_BASE_HI_BASE_IDX                                                                      0
4316 #define regCP_VMID_RESET                                                                                0x1e53
4317 #define regCP_VMID_RESET_BASE_IDX                                                                       0
4318 #define regCPC_INT_CNTL                                                                                 0x1e54
4319 #define regCPC_INT_CNTL_BASE_IDX                                                                        0
4320 #define regCPC_INT_STATUS                                                                               0x1e55
4321 #define regCPC_INT_STATUS_BASE_IDX                                                                      0
4322 #define regCP_VMID_PREEMPT                                                                              0x1e56
4323 #define regCP_VMID_PREEMPT_BASE_IDX                                                                     0
4324 #define regCPC_INT_CNTX_ID                                                                              0x1e57
4325 #define regCPC_INT_CNTX_ID_BASE_IDX                                                                     0
4326 #define regCP_PQ_STATUS                                                                                 0x1e58
4327 #define regCP_PQ_STATUS_BASE_IDX                                                                        0
4328 #define regCP_PFP_PRGRM_CNTR_START_HI                                                                   0x1e59
4329 #define regCP_PFP_PRGRM_CNTR_START_HI_BASE_IDX                                                          0
4330 #define regCP_MAX_DRAW_COUNT                                                                            0x1e5c
4331 #define regCP_MAX_DRAW_COUNT_BASE_IDX                                                                   0
4332 #define regCP_MEC1_F32_INT_DIS                                                                          0x1e5d
4333 #define regCP_MEC1_F32_INT_DIS_BASE_IDX                                                                 0
4334 #define regCP_MEC2_F32_INT_DIS                                                                          0x1e5e
4335 #define regCP_MEC2_F32_INT_DIS_BASE_IDX                                                                 0
4336 #define regCP_VMID_STATUS                                                                               0x1e5f
4337 #define regCP_VMID_STATUS_BASE_IDX                                                                      0
4338 #define regCPC_SUSPEND_CTX_SAVE_BASE_ADDR_LO                                                            0x1e60
4339 #define regCPC_SUSPEND_CTX_SAVE_BASE_ADDR_LO_BASE_IDX                                                   0
4340 #define regCPC_SUSPEND_CTX_SAVE_BASE_ADDR_HI                                                            0x1e61
4341 #define regCPC_SUSPEND_CTX_SAVE_BASE_ADDR_HI_BASE_IDX                                                   0
4342 #define regCPC_SUSPEND_CTX_SAVE_CONTROL                                                                 0x1e62
4343 #define regCPC_SUSPEND_CTX_SAVE_CONTROL_BASE_IDX                                                        0
4344 #define regCPC_SUSPEND_CNTL_STACK_OFFSET                                                                0x1e63
4345 #define regCPC_SUSPEND_CNTL_STACK_OFFSET_BASE_IDX                                                       0
4346 #define regCPC_SUSPEND_CNTL_STACK_SIZE                                                                  0x1e64
4347 #define regCPC_SUSPEND_CNTL_STACK_SIZE_BASE_IDX                                                         0
4348 #define regCPC_SUSPEND_WG_STATE_OFFSET                                                                  0x1e65
4349 #define regCPC_SUSPEND_WG_STATE_OFFSET_BASE_IDX                                                         0
4350 #define regCPC_SUSPEND_CTX_SAVE_SIZE                                                                    0x1e66
4351 #define regCPC_SUSPEND_CTX_SAVE_SIZE_BASE_IDX                                                           0
4352 #define regCPC_OS_PIPES                                                                                 0x1e67
4353 #define regCPC_OS_PIPES_BASE_IDX                                                                        0
4354 #define regCP_SUSPEND_RESUME_REQ                                                                        0x1e68
4355 #define regCP_SUSPEND_RESUME_REQ_BASE_IDX                                                               0
4356 #define regCP_SUSPEND_CNTL                                                                              0x1e69
4357 #define regCP_SUSPEND_CNTL_BASE_IDX                                                                     0
4358 #define regCP_IQ_WAIT_TIME3                                                                             0x1e6a
4359 #define regCP_IQ_WAIT_TIME3_BASE_IDX                                                                    0
4360 #define regCPC_DDID_BASE_ADDR_LO                                                                        0x1e6b
4361 #define regCPC_DDID_BASE_ADDR_LO_BASE_IDX                                                               0
4362 #define regCP_DDID_BASE_ADDR_LO                                                                         0x1e6b
4363 #define regCP_DDID_BASE_ADDR_LO_BASE_IDX                                                                0
4364 #define regCPC_DDID_BASE_ADDR_HI                                                                        0x1e6c
4365 #define regCPC_DDID_BASE_ADDR_HI_BASE_IDX                                                               0
4366 #define regCP_DDID_BASE_ADDR_HI                                                                         0x1e6c
4367 #define regCP_DDID_BASE_ADDR_HI_BASE_IDX                                                                0
4368 #define regCPC_DDID_CNTL                                                                                0x1e6d
4369 #define regCPC_DDID_CNTL_BASE_IDX                                                                       0
4370 #define regCP_DDID_CNTL                                                                                 0x1e6d
4371 #define regCP_DDID_CNTL_BASE_IDX                                                                        0
4372 #define regCP_GFX_DDID_INFLIGHT_COUNT                                                                   0x1e6e
4373 #define regCP_GFX_DDID_INFLIGHT_COUNT_BASE_IDX                                                          0
4374 #define regCP_GFX_DDID_WPTR                                                                             0x1e6f
4375 #define regCP_GFX_DDID_WPTR_BASE_IDX                                                                    0
4376 #define regCP_GFX_DDID_RPTR                                                                             0x1e70
4377 #define regCP_GFX_DDID_RPTR_BASE_IDX                                                                    0
4378 #define regCP_GFX_DDID_DELTA_RPT_COUNT                                                                  0x1e71
4379 #define regCP_GFX_DDID_DELTA_RPT_COUNT_BASE_IDX                                                         0
4380 #define regCP_GFX_HPD_STATUS0                                                                           0x1e72
4381 #define regCP_GFX_HPD_STATUS0_BASE_IDX                                                                  0
4382 #define regCP_GFX_HPD_CONTROL0                                                                          0x1e73
4383 #define regCP_GFX_HPD_CONTROL0_BASE_IDX                                                                 0
4384 #define regCP_GFX_HPD_OSPRE_FENCE_ADDR_LO                                                               0x1e74
4385 #define regCP_GFX_HPD_OSPRE_FENCE_ADDR_LO_BASE_IDX                                                      0
4386 #define regCP_GFX_HPD_OSPRE_FENCE_ADDR_HI                                                               0x1e75
4387 #define regCP_GFX_HPD_OSPRE_FENCE_ADDR_HI_BASE_IDX                                                      0
4388 #define regCP_GFX_HPD_OSPRE_FENCE_DATA_LO                                                               0x1e76
4389 #define regCP_GFX_HPD_OSPRE_FENCE_DATA_LO_BASE_IDX                                                      0
4390 #define regCP_GFX_HPD_OSPRE_FENCE_DATA_HI                                                               0x1e77
4391 #define regCP_GFX_HPD_OSPRE_FENCE_DATA_HI_BASE_IDX                                                      0
4392 #define regCP_GFX_INDEX_MUTEX                                                                           0x1e78
4393 #define regCP_GFX_INDEX_MUTEX_BASE_IDX                                                                  0
4394 #define regCP_ME_PRGRM_CNTR_START_HI                                                                    0x1e79
4395 #define regCP_ME_PRGRM_CNTR_START_HI_BASE_IDX                                                           0
4396 #define regCP_PFP_INTR_ROUTINE_START_HI                                                                 0x1e7a
4397 #define regCP_PFP_INTR_ROUTINE_START_HI_BASE_IDX                                                        0
4398 #define regCP_ME_INTR_ROUTINE_START_HI                                                                  0x1e7b
4399 #define regCP_ME_INTR_ROUTINE_START_HI_BASE_IDX                                                         0
4400 #define regCP_GFX_MQD_BASE_ADDR                                                                         0x1e7e
4401 #define regCP_GFX_MQD_BASE_ADDR_BASE_IDX                                                                0
4402 #define regCP_GFX_MQD_BASE_ADDR_HI                                                                      0x1e7f
4403 #define regCP_GFX_MQD_BASE_ADDR_HI_BASE_IDX                                                             0
4404 #define regCP_GFX_HQD_ACTIVE                                                                            0x1e80
4405 #define regCP_GFX_HQD_ACTIVE_BASE_IDX                                                                   0
4406 #define regCP_GFX_HQD_VMID                                                                              0x1e81
4407 #define regCP_GFX_HQD_VMID_BASE_IDX                                                                     0
4408 #define regCP_GFX_HQD_QUEUE_PRIORITY                                                                    0x1e84
4409 #define regCP_GFX_HQD_QUEUE_PRIORITY_BASE_IDX                                                           0
4410 #define regCP_GFX_HQD_QUANTUM                                                                           0x1e85
4411 #define regCP_GFX_HQD_QUANTUM_BASE_IDX                                                                  0
4412 #define regCP_GFX_HQD_BASE                                                                              0x1e86
4413 #define regCP_GFX_HQD_BASE_BASE_IDX                                                                     0
4414 #define regCP_GFX_HQD_BASE_HI                                                                           0x1e87
4415 #define regCP_GFX_HQD_BASE_HI_BASE_IDX                                                                  0
4416 #define regCP_GFX_HQD_RPTR                                                                              0x1e88
4417 #define regCP_GFX_HQD_RPTR_BASE_IDX                                                                     0
4418 #define regCP_GFX_HQD_RPTR_ADDR                                                                         0x1e89
4419 #define regCP_GFX_HQD_RPTR_ADDR_BASE_IDX                                                                0
4420 #define regCP_GFX_HQD_RPTR_ADDR_HI                                                                      0x1e8a
4421 #define regCP_GFX_HQD_RPTR_ADDR_HI_BASE_IDX                                                             0
4422 #define regCP_RB_WPTR_POLL_ADDR_LO                                                                      0x1e8b
4423 #define regCP_RB_WPTR_POLL_ADDR_LO_BASE_IDX                                                             0
4424 #define regCP_RB_WPTR_POLL_ADDR_HI                                                                      0x1e8c
4425 #define regCP_RB_WPTR_POLL_ADDR_HI_BASE_IDX                                                             0
4426 #define regCP_RB_DOORBELL_CONTROL                                                                       0x1e8d
4427 #define regCP_RB_DOORBELL_CONTROL_BASE_IDX                                                              0
4428 #define regCP_GFX_HQD_OFFSET                                                                            0x1e8e
4429 #define regCP_GFX_HQD_OFFSET_BASE_IDX                                                                   0
4430 #define regCP_GFX_HQD_CNTL                                                                              0x1e8f
4431 #define regCP_GFX_HQD_CNTL_BASE_IDX                                                                     0
4432 #define regCP_GFX_HQD_CSMD_RPTR                                                                         0x1e90
4433 #define regCP_GFX_HQD_CSMD_RPTR_BASE_IDX                                                                0
4434 #define regCP_GFX_HQD_WPTR                                                                              0x1e91
4435 #define regCP_GFX_HQD_WPTR_BASE_IDX                                                                     0
4436 #define regCP_GFX_HQD_WPTR_HI                                                                           0x1e92
4437 #define regCP_GFX_HQD_WPTR_HI_BASE_IDX                                                                  0
4438 #define regCP_GFX_HQD_DEQUEUE_REQUEST                                                                   0x1e93
4439 #define regCP_GFX_HQD_DEQUEUE_REQUEST_BASE_IDX                                                          0
4440 #define regCP_GFX_HQD_MAPPED                                                                            0x1e94
4441 #define regCP_GFX_HQD_MAPPED_BASE_IDX                                                                   0
4442 #define regCP_GFX_HQD_QUE_MGR_CONTROL                                                                   0x1e95
4443 #define regCP_GFX_HQD_QUE_MGR_CONTROL_BASE_IDX                                                          0
4444 #define regCP_GFX_HQD_IQ_TIMER                                                                          0x1e96
4445 #define regCP_GFX_HQD_IQ_TIMER_BASE_IDX                                                                 0
4446 #define regCP_GFX_HQD_HQ_STATUS0                                                                        0x1e98
4447 #define regCP_GFX_HQD_HQ_STATUS0_BASE_IDX                                                               0
4448 #define regCP_GFX_HQD_HQ_CONTROL0                                                                       0x1e99
4449 #define regCP_GFX_HQD_HQ_CONTROL0_BASE_IDX                                                              0
4450 #define regCP_GFX_MQD_CONTROL                                                                           0x1e9a
4451 #define regCP_GFX_MQD_CONTROL_BASE_IDX                                                                  0
4452 #define regCP_HQD_GFX_CONTROL                                                                           0x1e9f
4453 #define regCP_HQD_GFX_CONTROL_BASE_IDX                                                                  0
4454 #define regCP_HQD_GFX_STATUS                                                                            0x1ea0
4455 #define regCP_HQD_GFX_STATUS_BASE_IDX                                                                   0
4456 #define regCP_DMA_WATCH0_ADDR_LO                                                                        0x1ec0
4457 #define regCP_DMA_WATCH0_ADDR_LO_BASE_IDX                                                               0
4458 #define regCP_DMA_WATCH0_ADDR_HI                                                                        0x1ec1
4459 #define regCP_DMA_WATCH0_ADDR_HI_BASE_IDX                                                               0
4460 #define regCP_DMA_WATCH0_MASK                                                                           0x1ec2
4461 #define regCP_DMA_WATCH0_MASK_BASE_IDX                                                                  0
4462 #define regCP_DMA_WATCH0_CNTL                                                                           0x1ec3
4463 #define regCP_DMA_WATCH0_CNTL_BASE_IDX                                                                  0
4464 #define regCP_DMA_WATCH1_ADDR_LO                                                                        0x1ec4
4465 #define regCP_DMA_WATCH1_ADDR_LO_BASE_IDX                                                               0
4466 #define regCP_DMA_WATCH1_ADDR_HI                                                                        0x1ec5
4467 #define regCP_DMA_WATCH1_ADDR_HI_BASE_IDX                                                               0
4468 #define regCP_DMA_WATCH1_MASK                                                                           0x1ec6
4469 #define regCP_DMA_WATCH1_MASK_BASE_IDX                                                                  0
4470 #define regCP_DMA_WATCH1_CNTL                                                                           0x1ec7
4471 #define regCP_DMA_WATCH1_CNTL_BASE_IDX                                                                  0
4472 #define regCP_DMA_WATCH2_ADDR_LO                                                                        0x1ec8
4473 #define regCP_DMA_WATCH2_ADDR_LO_BASE_IDX                                                               0
4474 #define regCP_DMA_WATCH2_ADDR_HI                                                                        0x1ec9
4475 #define regCP_DMA_WATCH2_ADDR_HI_BASE_IDX                                                               0
4476 #define regCP_DMA_WATCH2_MASK                                                                           0x1eca
4477 #define regCP_DMA_WATCH2_MASK_BASE_IDX                                                                  0
4478 #define regCP_DMA_WATCH2_CNTL                                                                           0x1ecb
4479 #define regCP_DMA_WATCH2_CNTL_BASE_IDX                                                                  0
4480 #define regCP_DMA_WATCH3_ADDR_LO                                                                        0x1ecc
4481 #define regCP_DMA_WATCH3_ADDR_LO_BASE_IDX                                                               0
4482 #define regCP_DMA_WATCH3_ADDR_HI                                                                        0x1ecd
4483 #define regCP_DMA_WATCH3_ADDR_HI_BASE_IDX                                                               0
4484 #define regCP_DMA_WATCH3_MASK                                                                           0x1ece
4485 #define regCP_DMA_WATCH3_MASK_BASE_IDX                                                                  0
4486 #define regCP_DMA_WATCH3_CNTL                                                                           0x1ecf
4487 #define regCP_DMA_WATCH3_CNTL_BASE_IDX                                                                  0
4488 #define regCP_DMA_WATCH_STAT_ADDR_LO                                                                    0x1ed0
4489 #define regCP_DMA_WATCH_STAT_ADDR_LO_BASE_IDX                                                           0
4490 #define regCP_DMA_WATCH_STAT_ADDR_HI                                                                    0x1ed1
4491 #define regCP_DMA_WATCH_STAT_ADDR_HI_BASE_IDX                                                           0
4492 #define regCP_DMA_WATCH_STAT                                                                            0x1ed2
4493 #define regCP_DMA_WATCH_STAT_BASE_IDX                                                                   0
4494 #define regCP_PFP_JT_STAT                                                                               0x1ed3
4495 #define regCP_PFP_JT_STAT_BASE_IDX                                                                      0
4496 #define regCP_MEC_JT_STAT                                                                               0x1ed5
4497 #define regCP_MEC_JT_STAT_BASE_IDX                                                                      0
4498 #define regCP_CPC_BUSY_HYSTERESIS                                                                       0x1edb
4499 #define regCP_CPC_BUSY_HYSTERESIS_BASE_IDX                                                              0
4500 #define regCP_CPF_BUSY_HYSTERESIS1                                                                      0x1edc
4501 #define regCP_CPF_BUSY_HYSTERESIS1_BASE_IDX                                                             0
4502 #define regCP_CPF_BUSY_HYSTERESIS2                                                                      0x1edd
4503 #define regCP_CPF_BUSY_HYSTERESIS2_BASE_IDX                                                             0
4504 #define regCP_CPG_BUSY_HYSTERESIS1                                                                      0x1ede
4505 #define regCP_CPG_BUSY_HYSTERESIS1_BASE_IDX                                                             0
4506 #define regCP_CPG_BUSY_HYSTERESIS2                                                                      0x1edf
4507 #define regCP_CPG_BUSY_HYSTERESIS2_BASE_IDX                                                             0
4508 #define regCP_RB_DOORBELL_CLEAR                                                                         0x1f28
4509 #define regCP_RB_DOORBELL_CLEAR_BASE_IDX                                                                0
4510 #define regCP_RB0_ACTIVE                                                                                0x1f40
4511 #define regCP_RB0_ACTIVE_BASE_IDX                                                                       0
4512 #define regCP_RB_ACTIVE                                                                                 0x1f40
4513 #define regCP_RB_ACTIVE_BASE_IDX                                                                        0
4514 #define regCP_RB1_ACTIVE                                                                                0x1f41
4515 #define regCP_RB1_ACTIVE_BASE_IDX                                                                       0
4516 #define regCP_RB_STATUS                                                                                 0x1f43
4517 #define regCP_RB_STATUS_BASE_IDX                                                                        0
4518 #define regCPG_RCIU_CAM_INDEX                                                                           0x1f44
4519 #define regCPG_RCIU_CAM_INDEX_BASE_IDX                                                                  0
4520 #define regCPG_RCIU_CAM_DATA                                                                            0x1f45
4521 #define regCPG_RCIU_CAM_DATA_BASE_IDX                                                                   0
4522 #define regCPG_RCIU_CAM_DATA_PHASE0                                                                     0x1f45
4523 #define regCPG_RCIU_CAM_DATA_PHASE0_BASE_IDX                                                            0
4524 #define regCPG_RCIU_CAM_DATA_PHASE1                                                                     0x1f45
4525 #define regCPG_RCIU_CAM_DATA_PHASE1_BASE_IDX                                                            0
4526 #define regCPG_RCIU_CAM_DATA_PHASE2                                                                     0x1f45
4527 #define regCPG_RCIU_CAM_DATA_PHASE2_BASE_IDX                                                            0
4528 #define regCP_GPU_TIMESTAMP_OFFSET_LO                                                                   0x1f4c
4529 #define regCP_GPU_TIMESTAMP_OFFSET_LO_BASE_IDX                                                          0
4530 #define regCP_GPU_TIMESTAMP_OFFSET_HI                                                                   0x1f4d
4531 #define regCP_GPU_TIMESTAMP_OFFSET_HI_BASE_IDX                                                          0
4532 #define regCP_SDMA_DMA_DONE                                                                             0x1f4e
4533 #define regCP_SDMA_DMA_DONE_BASE_IDX                                                                    0
4534 #define regCP_PFP_SDMA_CS                                                                               0x1f4f
4535 #define regCP_PFP_SDMA_CS_BASE_IDX                                                                      0
4536 #define regCP_ME_SDMA_CS                                                                                0x1f50
4537 #define regCP_ME_SDMA_CS_BASE_IDX                                                                       0
4538 #define regCPF_GCR_CNTL                                                                                 0x1f53
4539 #define regCPF_GCR_CNTL_BASE_IDX                                                                        0
4540 #define regCPG_UTCL1_STATUS                                                                             0x1f54
4541 #define regCPG_UTCL1_STATUS_BASE_IDX                                                                    0
4542 #define regCPC_UTCL1_STATUS                                                                             0x1f55
4543 #define regCPC_UTCL1_STATUS_BASE_IDX                                                                    0
4544 #define regCPF_UTCL1_STATUS                                                                             0x1f56
4545 #define regCPF_UTCL1_STATUS_BASE_IDX                                                                    0
4546 #define regCP_SD_CNTL                                                                                   0x1f57
4547 #define regCP_SD_CNTL_BASE_IDX                                                                          0
4548 #define regCP_SOFT_RESET_CNTL                                                                           0x1f59
4549 #define regCP_SOFT_RESET_CNTL_BASE_IDX                                                                  0
4550 #define regCP_CPC_GFX_CNTL                                                                              0x1f5a
4551 #define regCP_CPC_GFX_CNTL_BASE_IDX                                                                     0
4552 
4553 
4554 // addressBlock: gc_spipdec
4555 // base address: 0xc700
4556 #define regSPI_ARB_PRIORITY                                                                             0x1f60
4557 #define regSPI_ARB_PRIORITY_BASE_IDX                                                                    0
4558 #define regSPI_ARB_CYCLES_0                                                                             0x1f61
4559 #define regSPI_ARB_CYCLES_0_BASE_IDX                                                                    0
4560 #define regSPI_ARB_CYCLES_1                                                                             0x1f62
4561 #define regSPI_ARB_CYCLES_1_BASE_IDX                                                                    0
4562 #define regSPI_WCL_PIPE_PERCENT_GFX                                                                     0x1f67
4563 #define regSPI_WCL_PIPE_PERCENT_GFX_BASE_IDX                                                            0
4564 #define regSPI_WCL_PIPE_PERCENT_HP3D                                                                    0x1f68
4565 #define regSPI_WCL_PIPE_PERCENT_HP3D_BASE_IDX                                                           0
4566 #define regSPI_WCL_PIPE_PERCENT_CS0                                                                     0x1f69
4567 #define regSPI_WCL_PIPE_PERCENT_CS0_BASE_IDX                                                            0
4568 #define regSPI_WCL_PIPE_PERCENT_CS1                                                                     0x1f6a
4569 #define regSPI_WCL_PIPE_PERCENT_CS1_BASE_IDX                                                            0
4570 #define regSPI_WCL_PIPE_PERCENT_CS2                                                                     0x1f6b
4571 #define regSPI_WCL_PIPE_PERCENT_CS2_BASE_IDX                                                            0
4572 #define regSPI_WCL_PIPE_PERCENT_CS3                                                                     0x1f6c
4573 #define regSPI_WCL_PIPE_PERCENT_CS3_BASE_IDX                                                            0
4574 #define regSPI_WCL_PIPE_PERCENT_CS4                                                                     0x1f6d
4575 #define regSPI_WCL_PIPE_PERCENT_CS4_BASE_IDX                                                            0
4576 #define regSPI_WCL_PIPE_PERCENT_CS5                                                                     0x1f6e
4577 #define regSPI_WCL_PIPE_PERCENT_CS5_BASE_IDX                                                            0
4578 #define regSPI_WCL_PIPE_PERCENT_CS6                                                                     0x1f6f
4579 #define regSPI_WCL_PIPE_PERCENT_CS6_BASE_IDX                                                            0
4580 #define regSPI_WCL_PIPE_PERCENT_CS7                                                                     0x1f70
4581 #define regSPI_WCL_PIPE_PERCENT_CS7_BASE_IDX                                                            0
4582 #define regSPI_USER_ACCUM_VMID_CNTL                                                                     0x1f71
4583 #define regSPI_USER_ACCUM_VMID_CNTL_BASE_IDX                                                            0
4584 #define regSPI_GDBG_PER_VMID_CNTL                                                                       0x1f72
4585 #define regSPI_GDBG_PER_VMID_CNTL_BASE_IDX                                                              0
4586 #define regSPI_COMPUTE_QUEUE_RESET                                                                      0x1f73
4587 #define regSPI_COMPUTE_QUEUE_RESET_BASE_IDX                                                             0
4588 #define regSPI_COMPUTE_WF_CTX_SAVE                                                                      0x1f74
4589 #define regSPI_COMPUTE_WF_CTX_SAVE_BASE_IDX                                                             0
4590 
4591 
4592 // addressBlock: gc_cpphqddec
4593 // base address: 0xc800
4594 #define regCP_HPD_UTCL1_CNTL                                                                            0x1fa3
4595 #define regCP_HPD_UTCL1_CNTL_BASE_IDX                                                                   0
4596 #define regCP_HPD_UTCL1_ERROR                                                                           0x1fa7
4597 #define regCP_HPD_UTCL1_ERROR_BASE_IDX                                                                  0
4598 #define regCP_HPD_UTCL1_ERROR_ADDR                                                                      0x1fa8
4599 #define regCP_HPD_UTCL1_ERROR_ADDR_BASE_IDX                                                             0
4600 #define regCP_MQD_BASE_ADDR                                                                             0x1fa9
4601 #define regCP_MQD_BASE_ADDR_BASE_IDX                                                                    0
4602 #define regCP_MQD_BASE_ADDR_HI                                                                          0x1faa
4603 #define regCP_MQD_BASE_ADDR_HI_BASE_IDX                                                                 0
4604 #define regCP_HQD_ACTIVE                                                                                0x1fab
4605 #define regCP_HQD_ACTIVE_BASE_IDX                                                                       0
4606 #define regCP_HQD_VMID                                                                                  0x1fac
4607 #define regCP_HQD_VMID_BASE_IDX                                                                         0
4608 #define regCP_HQD_PERSISTENT_STATE                                                                      0x1fad
4609 #define regCP_HQD_PERSISTENT_STATE_BASE_IDX                                                             0
4610 #define regCP_HQD_PIPE_PRIORITY                                                                         0x1fae
4611 #define regCP_HQD_PIPE_PRIORITY_BASE_IDX                                                                0
4612 #define regCP_HQD_QUEUE_PRIORITY                                                                        0x1faf
4613 #define regCP_HQD_QUEUE_PRIORITY_BASE_IDX                                                               0
4614 #define regCP_HQD_QUANTUM                                                                               0x1fb0
4615 #define regCP_HQD_QUANTUM_BASE_IDX                                                                      0
4616 #define regCP_HQD_PQ_BASE                                                                               0x1fb1
4617 #define regCP_HQD_PQ_BASE_BASE_IDX                                                                      0
4618 #define regCP_HQD_PQ_BASE_HI                                                                            0x1fb2
4619 #define regCP_HQD_PQ_BASE_HI_BASE_IDX                                                                   0
4620 #define regCP_HQD_PQ_RPTR                                                                               0x1fb3
4621 #define regCP_HQD_PQ_RPTR_BASE_IDX                                                                      0
4622 #define regCP_HQD_PQ_RPTR_REPORT_ADDR                                                                   0x1fb4
4623 #define regCP_HQD_PQ_RPTR_REPORT_ADDR_BASE_IDX                                                          0
4624 #define regCP_HQD_PQ_RPTR_REPORT_ADDR_HI                                                                0x1fb5
4625 #define regCP_HQD_PQ_RPTR_REPORT_ADDR_HI_BASE_IDX                                                       0
4626 #define regCP_HQD_PQ_WPTR_POLL_ADDR                                                                     0x1fb6
4627 #define regCP_HQD_PQ_WPTR_POLL_ADDR_BASE_IDX                                                            0
4628 #define regCP_HQD_PQ_WPTR_POLL_ADDR_HI                                                                  0x1fb7
4629 #define regCP_HQD_PQ_WPTR_POLL_ADDR_HI_BASE_IDX                                                         0
4630 #define regCP_HQD_PQ_DOORBELL_CONTROL                                                                   0x1fb8
4631 #define regCP_HQD_PQ_DOORBELL_CONTROL_BASE_IDX                                                          0
4632 #define regCP_HQD_PQ_CONTROL                                                                            0x1fba
4633 #define regCP_HQD_PQ_CONTROL_BASE_IDX                                                                   0
4634 #define regCP_HQD_IB_BASE_ADDR                                                                          0x1fbb
4635 #define regCP_HQD_IB_BASE_ADDR_BASE_IDX                                                                 0
4636 #define regCP_HQD_IB_BASE_ADDR_HI                                                                       0x1fbc
4637 #define regCP_HQD_IB_BASE_ADDR_HI_BASE_IDX                                                              0
4638 #define regCP_HQD_IB_RPTR                                                                               0x1fbd
4639 #define regCP_HQD_IB_RPTR_BASE_IDX                                                                      0
4640 #define regCP_HQD_IB_CONTROL                                                                            0x1fbe
4641 #define regCP_HQD_IB_CONTROL_BASE_IDX                                                                   0
4642 #define regCP_HQD_IQ_TIMER                                                                              0x1fbf
4643 #define regCP_HQD_IQ_TIMER_BASE_IDX                                                                     0
4644 #define regCP_HQD_IQ_RPTR                                                                               0x1fc0
4645 #define regCP_HQD_IQ_RPTR_BASE_IDX                                                                      0
4646 #define regCP_HQD_DEQUEUE_REQUEST                                                                       0x1fc1
4647 #define regCP_HQD_DEQUEUE_REQUEST_BASE_IDX                                                              0
4648 #define regCP_HQD_DMA_OFFLOAD                                                                           0x1fc2
4649 #define regCP_HQD_DMA_OFFLOAD_BASE_IDX                                                                  0
4650 #define regCP_HQD_OFFLOAD                                                                               0x1fc2
4651 #define regCP_HQD_OFFLOAD_BASE_IDX                                                                      0
4652 #define regCP_HQD_SEMA_CMD                                                                              0x1fc3
4653 #define regCP_HQD_SEMA_CMD_BASE_IDX                                                                     0
4654 #define regCP_HQD_MSG_TYPE                                                                              0x1fc4
4655 #define regCP_HQD_MSG_TYPE_BASE_IDX                                                                     0
4656 #define regCP_HQD_ATOMIC0_PREOP_LO                                                                      0x1fc5
4657 #define regCP_HQD_ATOMIC0_PREOP_LO_BASE_IDX                                                             0
4658 #define regCP_HQD_ATOMIC0_PREOP_HI                                                                      0x1fc6
4659 #define regCP_HQD_ATOMIC0_PREOP_HI_BASE_IDX                                                             0
4660 #define regCP_HQD_ATOMIC1_PREOP_LO                                                                      0x1fc7
4661 #define regCP_HQD_ATOMIC1_PREOP_LO_BASE_IDX                                                             0
4662 #define regCP_HQD_ATOMIC1_PREOP_HI                                                                      0x1fc8
4663 #define regCP_HQD_ATOMIC1_PREOP_HI_BASE_IDX                                                             0
4664 #define regCP_HQD_HQ_SCHEDULER0                                                                         0x1fc9
4665 #define regCP_HQD_HQ_SCHEDULER0_BASE_IDX                                                                0
4666 #define regCP_HQD_HQ_STATUS0                                                                            0x1fc9
4667 #define regCP_HQD_HQ_STATUS0_BASE_IDX                                                                   0
4668 #define regCP_HQD_HQ_CONTROL0                                                                           0x1fca
4669 #define regCP_HQD_HQ_CONTROL0_BASE_IDX                                                                  0
4670 #define regCP_HQD_HQ_SCHEDULER1                                                                         0x1fca
4671 #define regCP_HQD_HQ_SCHEDULER1_BASE_IDX                                                                0
4672 #define regCP_MQD_CONTROL                                                                               0x1fcb
4673 #define regCP_MQD_CONTROL_BASE_IDX                                                                      0
4674 #define regCP_HQD_HQ_STATUS1                                                                            0x1fcc
4675 #define regCP_HQD_HQ_STATUS1_BASE_IDX                                                                   0
4676 #define regCP_HQD_HQ_CONTROL1                                                                           0x1fcd
4677 #define regCP_HQD_HQ_CONTROL1_BASE_IDX                                                                  0
4678 #define regCP_HQD_EOP_BASE_ADDR                                                                         0x1fce
4679 #define regCP_HQD_EOP_BASE_ADDR_BASE_IDX                                                                0
4680 #define regCP_HQD_EOP_BASE_ADDR_HI                                                                      0x1fcf
4681 #define regCP_HQD_EOP_BASE_ADDR_HI_BASE_IDX                                                             0
4682 #define regCP_HQD_EOP_CONTROL                                                                           0x1fd0
4683 #define regCP_HQD_EOP_CONTROL_BASE_IDX                                                                  0
4684 #define regCP_HQD_EOP_RPTR                                                                              0x1fd1
4685 #define regCP_HQD_EOP_RPTR_BASE_IDX                                                                     0
4686 #define regCP_HQD_EOP_WPTR                                                                              0x1fd2
4687 #define regCP_HQD_EOP_WPTR_BASE_IDX                                                                     0
4688 #define regCP_HQD_EOP_EVENTS                                                                            0x1fd3
4689 #define regCP_HQD_EOP_EVENTS_BASE_IDX                                                                   0
4690 #define regCP_HQD_CTX_SAVE_BASE_ADDR_LO                                                                 0x1fd4
4691 #define regCP_HQD_CTX_SAVE_BASE_ADDR_LO_BASE_IDX                                                        0
4692 #define regCP_HQD_CTX_SAVE_BASE_ADDR_HI                                                                 0x1fd5
4693 #define regCP_HQD_CTX_SAVE_BASE_ADDR_HI_BASE_IDX                                                        0
4694 #define regCP_HQD_CTX_SAVE_CONTROL                                                                      0x1fd6
4695 #define regCP_HQD_CTX_SAVE_CONTROL_BASE_IDX                                                             0
4696 #define regCP_HQD_CNTL_STACK_OFFSET                                                                     0x1fd7
4697 #define regCP_HQD_CNTL_STACK_OFFSET_BASE_IDX                                                            0
4698 #define regCP_HQD_CNTL_STACK_SIZE                                                                       0x1fd8
4699 #define regCP_HQD_CNTL_STACK_SIZE_BASE_IDX                                                              0
4700 #define regCP_HQD_WG_STATE_OFFSET                                                                       0x1fd9
4701 #define regCP_HQD_WG_STATE_OFFSET_BASE_IDX                                                              0
4702 #define regCP_HQD_CTX_SAVE_SIZE                                                                         0x1fda
4703 #define regCP_HQD_CTX_SAVE_SIZE_BASE_IDX                                                                0
4704 #define regCP_HQD_GDS_RESOURCE_STATE                                                                    0x1fdb
4705 #define regCP_HQD_GDS_RESOURCE_STATE_BASE_IDX                                                           0
4706 #define regCP_HQD_ERROR                                                                                 0x1fdc
4707 #define regCP_HQD_ERROR_BASE_IDX                                                                        0
4708 #define regCP_HQD_EOP_WPTR_MEM                                                                          0x1fdd
4709 #define regCP_HQD_EOP_WPTR_MEM_BASE_IDX                                                                 0
4710 #define regCP_HQD_AQL_CONTROL                                                                           0x1fde
4711 #define regCP_HQD_AQL_CONTROL_BASE_IDX                                                                  0
4712 #define regCP_HQD_PQ_WPTR_LO                                                                            0x1fdf
4713 #define regCP_HQD_PQ_WPTR_LO_BASE_IDX                                                                   0
4714 #define regCP_HQD_PQ_WPTR_HI                                                                            0x1fe0
4715 #define regCP_HQD_PQ_WPTR_HI_BASE_IDX                                                                   0
4716 #define regCP_HQD_SUSPEND_CNTL_STACK_OFFSET                                                             0x1fe1
4717 #define regCP_HQD_SUSPEND_CNTL_STACK_OFFSET_BASE_IDX                                                    0
4718 #define regCP_HQD_SUSPEND_CNTL_STACK_DW_CNT                                                             0x1fe2
4719 #define regCP_HQD_SUSPEND_CNTL_STACK_DW_CNT_BASE_IDX                                                    0
4720 #define regCP_HQD_SUSPEND_WG_STATE_OFFSET                                                               0x1fe3
4721 #define regCP_HQD_SUSPEND_WG_STATE_OFFSET_BASE_IDX                                                      0
4722 #define regCP_HQD_DDID_RPTR                                                                             0x1fe4
4723 #define regCP_HQD_DDID_RPTR_BASE_IDX                                                                    0
4724 #define regCP_HQD_DDID_WPTR                                                                             0x1fe5
4725 #define regCP_HQD_DDID_WPTR_BASE_IDX                                                                    0
4726 #define regCP_HQD_DDID_INFLIGHT_COUNT                                                                   0x1fe6
4727 #define regCP_HQD_DDID_INFLIGHT_COUNT_BASE_IDX                                                          0
4728 #define regCP_HQD_DDID_DELTA_RPT_COUNT                                                                  0x1fe7
4729 #define regCP_HQD_DDID_DELTA_RPT_COUNT_BASE_IDX                                                         0
4730 #define regCP_HQD_DEQUEUE_STATUS                                                                        0x1fe8
4731 #define regCP_HQD_DEQUEUE_STATUS_BASE_IDX                                                               0
4732 
4733 
4734 // addressBlock: gc_tcpdec
4735 // base address: 0xca80
4736 #define regTCP_WATCH0_ADDR_H                                                                            0x2048
4737 #define regTCP_WATCH0_ADDR_H_BASE_IDX                                                                   0
4738 #define regTCP_WATCH0_ADDR_L                                                                            0x2049
4739 #define regTCP_WATCH0_ADDR_L_BASE_IDX                                                                   0
4740 #define regTCP_WATCH0_CNTL                                                                              0x204a
4741 #define regTCP_WATCH0_CNTL_BASE_IDX                                                                     0
4742 #define regTCP_WATCH1_ADDR_H                                                                            0x204b
4743 #define regTCP_WATCH1_ADDR_H_BASE_IDX                                                                   0
4744 #define regTCP_WATCH1_ADDR_L                                                                            0x204c
4745 #define regTCP_WATCH1_ADDR_L_BASE_IDX                                                                   0
4746 #define regTCP_WATCH1_CNTL                                                                              0x204d
4747 #define regTCP_WATCH1_CNTL_BASE_IDX                                                                     0
4748 #define regTCP_WATCH2_ADDR_H                                                                            0x204e
4749 #define regTCP_WATCH2_ADDR_H_BASE_IDX                                                                   0
4750 #define regTCP_WATCH2_ADDR_L                                                                            0x204f
4751 #define regTCP_WATCH2_ADDR_L_BASE_IDX                                                                   0
4752 #define regTCP_WATCH2_CNTL                                                                              0x2050
4753 #define regTCP_WATCH2_CNTL_BASE_IDX                                                                     0
4754 #define regTCP_WATCH3_ADDR_H                                                                            0x2051
4755 #define regTCP_WATCH3_ADDR_H_BASE_IDX                                                                   0
4756 #define regTCP_WATCH3_ADDR_L                                                                            0x2052
4757 #define regTCP_WATCH3_ADDR_L_BASE_IDX                                                                   0
4758 #define regTCP_WATCH3_CNTL                                                                              0x2053
4759 #define regTCP_WATCH3_CNTL_BASE_IDX                                                                     0
4760 
4761 
4762 // addressBlock: gc_gdspdec
4763 // base address: 0xcc00
4764 #define regGDS_VMID0_BASE                                                                               0x20a0
4765 #define regGDS_VMID0_BASE_BASE_IDX                                                                      0
4766 #define regGDS_VMID0_SIZE                                                                               0x20a1
4767 #define regGDS_VMID0_SIZE_BASE_IDX                                                                      0
4768 #define regGDS_VMID1_BASE                                                                               0x20a2
4769 #define regGDS_VMID1_BASE_BASE_IDX                                                                      0
4770 #define regGDS_VMID1_SIZE                                                                               0x20a3
4771 #define regGDS_VMID1_SIZE_BASE_IDX                                                                      0
4772 #define regGDS_VMID2_BASE                                                                               0x20a4
4773 #define regGDS_VMID2_BASE_BASE_IDX                                                                      0
4774 #define regGDS_VMID2_SIZE                                                                               0x20a5
4775 #define regGDS_VMID2_SIZE_BASE_IDX                                                                      0
4776 #define regGDS_VMID3_BASE                                                                               0x20a6
4777 #define regGDS_VMID3_BASE_BASE_IDX                                                                      0
4778 #define regGDS_VMID3_SIZE                                                                               0x20a7
4779 #define regGDS_VMID3_SIZE_BASE_IDX                                                                      0
4780 #define regGDS_VMID4_BASE                                                                               0x20a8
4781 #define regGDS_VMID4_BASE_BASE_IDX                                                                      0
4782 #define regGDS_VMID4_SIZE                                                                               0x20a9
4783 #define regGDS_VMID4_SIZE_BASE_IDX                                                                      0
4784 #define regGDS_VMID5_BASE                                                                               0x20aa
4785 #define regGDS_VMID5_BASE_BASE_IDX                                                                      0
4786 #define regGDS_VMID5_SIZE                                                                               0x20ab
4787 #define regGDS_VMID5_SIZE_BASE_IDX                                                                      0
4788 #define regGDS_VMID6_BASE                                                                               0x20ac
4789 #define regGDS_VMID6_BASE_BASE_IDX                                                                      0
4790 #define regGDS_VMID6_SIZE                                                                               0x20ad
4791 #define regGDS_VMID6_SIZE_BASE_IDX                                                                      0
4792 #define regGDS_VMID7_BASE                                                                               0x20ae
4793 #define regGDS_VMID7_BASE_BASE_IDX                                                                      0
4794 #define regGDS_VMID7_SIZE                                                                               0x20af
4795 #define regGDS_VMID7_SIZE_BASE_IDX                                                                      0
4796 #define regGDS_VMID8_BASE                                                                               0x20b0
4797 #define regGDS_VMID8_BASE_BASE_IDX                                                                      0
4798 #define regGDS_VMID8_SIZE                                                                               0x20b1
4799 #define regGDS_VMID8_SIZE_BASE_IDX                                                                      0
4800 #define regGDS_VMID9_BASE                                                                               0x20b2
4801 #define regGDS_VMID9_BASE_BASE_IDX                                                                      0
4802 #define regGDS_VMID9_SIZE                                                                               0x20b3
4803 #define regGDS_VMID9_SIZE_BASE_IDX                                                                      0
4804 #define regGDS_VMID10_BASE                                                                              0x20b4
4805 #define regGDS_VMID10_BASE_BASE_IDX                                                                     0
4806 #define regGDS_VMID10_SIZE                                                                              0x20b5
4807 #define regGDS_VMID10_SIZE_BASE_IDX                                                                     0
4808 #define regGDS_VMID11_BASE                                                                              0x20b6
4809 #define regGDS_VMID11_BASE_BASE_IDX                                                                     0
4810 #define regGDS_VMID11_SIZE                                                                              0x20b7
4811 #define regGDS_VMID11_SIZE_BASE_IDX                                                                     0
4812 #define regGDS_VMID12_BASE                                                                              0x20b8
4813 #define regGDS_VMID12_BASE_BASE_IDX                                                                     0
4814 #define regGDS_VMID12_SIZE                                                                              0x20b9
4815 #define regGDS_VMID12_SIZE_BASE_IDX                                                                     0
4816 #define regGDS_VMID13_BASE                                                                              0x20ba
4817 #define regGDS_VMID13_BASE_BASE_IDX                                                                     0
4818 #define regGDS_VMID13_SIZE                                                                              0x20bb
4819 #define regGDS_VMID13_SIZE_BASE_IDX                                                                     0
4820 #define regGDS_VMID14_BASE                                                                              0x20bc
4821 #define regGDS_VMID14_BASE_BASE_IDX                                                                     0
4822 #define regGDS_VMID14_SIZE                                                                              0x20bd
4823 #define regGDS_VMID14_SIZE_BASE_IDX                                                                     0
4824 #define regGDS_VMID15_BASE                                                                              0x20be
4825 #define regGDS_VMID15_BASE_BASE_IDX                                                                     0
4826 #define regGDS_VMID15_SIZE                                                                              0x20bf
4827 #define regGDS_VMID15_SIZE_BASE_IDX                                                                     0
4828 #define regGDS_GWS_VMID0                                                                                0x20c0
4829 #define regGDS_GWS_VMID0_BASE_IDX                                                                       0
4830 #define regGDS_GWS_VMID1                                                                                0x20c1
4831 #define regGDS_GWS_VMID1_BASE_IDX                                                                       0
4832 #define regGDS_GWS_VMID2                                                                                0x20c2
4833 #define regGDS_GWS_VMID2_BASE_IDX                                                                       0
4834 #define regGDS_GWS_VMID3                                                                                0x20c3
4835 #define regGDS_GWS_VMID3_BASE_IDX                                                                       0
4836 #define regGDS_GWS_VMID4                                                                                0x20c4
4837 #define regGDS_GWS_VMID4_BASE_IDX                                                                       0
4838 #define regGDS_GWS_VMID5                                                                                0x20c5
4839 #define regGDS_GWS_VMID5_BASE_IDX                                                                       0
4840 #define regGDS_GWS_VMID6                                                                                0x20c6
4841 #define regGDS_GWS_VMID6_BASE_IDX                                                                       0
4842 #define regGDS_GWS_VMID7                                                                                0x20c7
4843 #define regGDS_GWS_VMID7_BASE_IDX                                                                       0
4844 #define regGDS_GWS_VMID8                                                                                0x20c8
4845 #define regGDS_GWS_VMID8_BASE_IDX                                                                       0
4846 #define regGDS_GWS_VMID9                                                                                0x20c9
4847 #define regGDS_GWS_VMID9_BASE_IDX                                                                       0
4848 #define regGDS_GWS_VMID10                                                                               0x20ca
4849 #define regGDS_GWS_VMID10_BASE_IDX                                                                      0
4850 #define regGDS_GWS_VMID11                                                                               0x20cb
4851 #define regGDS_GWS_VMID11_BASE_IDX                                                                      0
4852 #define regGDS_GWS_VMID12                                                                               0x20cc
4853 #define regGDS_GWS_VMID12_BASE_IDX                                                                      0
4854 #define regGDS_GWS_VMID13                                                                               0x20cd
4855 #define regGDS_GWS_VMID13_BASE_IDX                                                                      0
4856 #define regGDS_GWS_VMID14                                                                               0x20ce
4857 #define regGDS_GWS_VMID14_BASE_IDX                                                                      0
4858 #define regGDS_GWS_VMID15                                                                               0x20cf
4859 #define regGDS_GWS_VMID15_BASE_IDX                                                                      0
4860 #define regGDS_OA_VMID0                                                                                 0x20d0
4861 #define regGDS_OA_VMID0_BASE_IDX                                                                        0
4862 #define regGDS_OA_VMID1                                                                                 0x20d1
4863 #define regGDS_OA_VMID1_BASE_IDX                                                                        0
4864 #define regGDS_OA_VMID2                                                                                 0x20d2
4865 #define regGDS_OA_VMID2_BASE_IDX                                                                        0
4866 #define regGDS_OA_VMID3                                                                                 0x20d3
4867 #define regGDS_OA_VMID3_BASE_IDX                                                                        0
4868 #define regGDS_OA_VMID4                                                                                 0x20d4
4869 #define regGDS_OA_VMID4_BASE_IDX                                                                        0
4870 #define regGDS_OA_VMID5                                                                                 0x20d5
4871 #define regGDS_OA_VMID5_BASE_IDX                                                                        0
4872 #define regGDS_OA_VMID6                                                                                 0x20d6
4873 #define regGDS_OA_VMID6_BASE_IDX                                                                        0
4874 #define regGDS_OA_VMID7                                                                                 0x20d7
4875 #define regGDS_OA_VMID7_BASE_IDX                                                                        0
4876 #define regGDS_OA_VMID8                                                                                 0x20d8
4877 #define regGDS_OA_VMID8_BASE_IDX                                                                        0
4878 #define regGDS_OA_VMID9                                                                                 0x20d9
4879 #define regGDS_OA_VMID9_BASE_IDX                                                                        0
4880 #define regGDS_OA_VMID10                                                                                0x20da
4881 #define regGDS_OA_VMID10_BASE_IDX                                                                       0
4882 #define regGDS_OA_VMID11                                                                                0x20db
4883 #define regGDS_OA_VMID11_BASE_IDX                                                                       0
4884 #define regGDS_OA_VMID12                                                                                0x20dc
4885 #define regGDS_OA_VMID12_BASE_IDX                                                                       0
4886 #define regGDS_OA_VMID13                                                                                0x20dd
4887 #define regGDS_OA_VMID13_BASE_IDX                                                                       0
4888 #define regGDS_OA_VMID14                                                                                0x20de
4889 #define regGDS_OA_VMID14_BASE_IDX                                                                       0
4890 #define regGDS_OA_VMID15                                                                                0x20df
4891 #define regGDS_OA_VMID15_BASE_IDX                                                                       0
4892 #define regGDS_GWS_RESET0                                                                               0x20e4
4893 #define regGDS_GWS_RESET0_BASE_IDX                                                                      0
4894 #define regGDS_GWS_RESET1                                                                               0x20e5
4895 #define regGDS_GWS_RESET1_BASE_IDX                                                                      0
4896 #define regGDS_GWS_RESOURCE_RESET                                                                       0x20e6
4897 #define regGDS_GWS_RESOURCE_RESET_BASE_IDX                                                              0
4898 #define regGDS_COMPUTE_MAX_WAVE_ID                                                                      0x20e8
4899 #define regGDS_COMPUTE_MAX_WAVE_ID_BASE_IDX                                                             0
4900 #define regGDS_OA_RESET_MASK                                                                            0x20e9
4901 #define regGDS_OA_RESET_MASK_BASE_IDX                                                                   0
4902 #define regGDS_OA_RESET                                                                                 0x20ea
4903 #define regGDS_OA_RESET_BASE_IDX                                                                        0
4904 #define regGDS_CS_CTXSW_STATUS                                                                          0x20ed
4905 #define regGDS_CS_CTXSW_STATUS_BASE_IDX                                                                 0
4906 #define regGDS_CS_CTXSW_CNT0                                                                            0x20ee
4907 #define regGDS_CS_CTXSW_CNT0_BASE_IDX                                                                   0
4908 #define regGDS_CS_CTXSW_CNT1                                                                            0x20ef
4909 #define regGDS_CS_CTXSW_CNT1_BASE_IDX                                                                   0
4910 #define regGDS_CS_CTXSW_CNT2                                                                            0x20f0
4911 #define regGDS_CS_CTXSW_CNT2_BASE_IDX                                                                   0
4912 #define regGDS_CS_CTXSW_CNT3                                                                            0x20f1
4913 #define regGDS_CS_CTXSW_CNT3_BASE_IDX                                                                   0
4914 #define regGDS_GFX_CTXSW_STATUS                                                                         0x20f2
4915 #define regGDS_GFX_CTXSW_STATUS_BASE_IDX                                                                0
4916 #define regGDS_PS_CTXSW_CNT0                                                                            0x20f7
4917 #define regGDS_PS_CTXSW_CNT0_BASE_IDX                                                                   0
4918 #define regGDS_PS_CTXSW_CNT1                                                                            0x20f8
4919 #define regGDS_PS_CTXSW_CNT1_BASE_IDX                                                                   0
4920 #define regGDS_PS_CTXSW_CNT2                                                                            0x20f9
4921 #define regGDS_PS_CTXSW_CNT2_BASE_IDX                                                                   0
4922 #define regGDS_PS_CTXSW_CNT3                                                                            0x20fa
4923 #define regGDS_PS_CTXSW_CNT3_BASE_IDX                                                                   0
4924 #define regGDS_PS_CTXSW_IDX                                                                             0x20fb
4925 #define regGDS_PS_CTXSW_IDX_BASE_IDX                                                                    0
4926 #define regGDS_GS_CTXSW_CNT0                                                                            0x2117
4927 #define regGDS_GS_CTXSW_CNT0_BASE_IDX                                                                   0
4928 #define regGDS_GS_CTXSW_CNT1                                                                            0x2118
4929 #define regGDS_GS_CTXSW_CNT1_BASE_IDX                                                                   0
4930 #define regGDS_GS_CTXSW_CNT2                                                                            0x2119
4931 #define regGDS_GS_CTXSW_CNT2_BASE_IDX                                                                   0
4932 #define regGDS_GS_CTXSW_CNT3                                                                            0x211a
4933 #define regGDS_GS_CTXSW_CNT3_BASE_IDX                                                                   0
4934 #define regGDS_MEMORY_CLEAN                                                                             0x211f
4935 #define regGDS_MEMORY_CLEAN_BASE_IDX                                                                    0
4936 
4937 
4938 // addressBlock: gc_gusdec
4939 // base address: 0x33000
4940 #define regGUS_IO_RD_COMBINE_FLUSH                                                                      0x2c00
4941 #define regGUS_IO_RD_COMBINE_FLUSH_BASE_IDX                                                             1
4942 #define regGUS_IO_WR_COMBINE_FLUSH                                                                      0x2c01
4943 #define regGUS_IO_WR_COMBINE_FLUSH_BASE_IDX                                                             1
4944 #define regGUS_IO_RD_PRI_AGE_RATE                                                                       0x2c02
4945 #define regGUS_IO_RD_PRI_AGE_RATE_BASE_IDX                                                              1
4946 #define regGUS_IO_WR_PRI_AGE_RATE                                                                       0x2c03
4947 #define regGUS_IO_WR_PRI_AGE_RATE_BASE_IDX                                                              1
4948 #define regGUS_IO_RD_PRI_AGE_COEFF                                                                      0x2c04
4949 #define regGUS_IO_RD_PRI_AGE_COEFF_BASE_IDX                                                             1
4950 #define regGUS_IO_WR_PRI_AGE_COEFF                                                                      0x2c05
4951 #define regGUS_IO_WR_PRI_AGE_COEFF_BASE_IDX                                                             1
4952 #define regGUS_IO_RD_PRI_QUEUING                                                                        0x2c06
4953 #define regGUS_IO_RD_PRI_QUEUING_BASE_IDX                                                               1
4954 #define regGUS_IO_WR_PRI_QUEUING                                                                        0x2c07
4955 #define regGUS_IO_WR_PRI_QUEUING_BASE_IDX                                                               1
4956 #define regGUS_IO_RD_PRI_FIXED                                                                          0x2c08
4957 #define regGUS_IO_RD_PRI_FIXED_BASE_IDX                                                                 1
4958 #define regGUS_IO_WR_PRI_FIXED                                                                          0x2c09
4959 #define regGUS_IO_WR_PRI_FIXED_BASE_IDX                                                                 1
4960 #define regGUS_IO_RD_PRI_URGENCY_COEFF                                                                  0x2c0a
4961 #define regGUS_IO_RD_PRI_URGENCY_COEFF_BASE_IDX                                                         1
4962 #define regGUS_IO_WR_PRI_URGENCY_COEFF                                                                  0x2c0b
4963 #define regGUS_IO_WR_PRI_URGENCY_COEFF_BASE_IDX                                                         1
4964 #define regGUS_IO_RD_PRI_URGENCY_MODE                                                                   0x2c0c
4965 #define regGUS_IO_RD_PRI_URGENCY_MODE_BASE_IDX                                                          1
4966 #define regGUS_IO_WR_PRI_URGENCY_MODE                                                                   0x2c0d
4967 #define regGUS_IO_WR_PRI_URGENCY_MODE_BASE_IDX                                                          1
4968 #define regGUS_IO_RD_PRI_QUANT_PRI1                                                                     0x2c0e
4969 #define regGUS_IO_RD_PRI_QUANT_PRI1_BASE_IDX                                                            1
4970 #define regGUS_IO_RD_PRI_QUANT_PRI2                                                                     0x2c0f
4971 #define regGUS_IO_RD_PRI_QUANT_PRI2_BASE_IDX                                                            1
4972 #define regGUS_IO_RD_PRI_QUANT_PRI3                                                                     0x2c10
4973 #define regGUS_IO_RD_PRI_QUANT_PRI3_BASE_IDX                                                            1
4974 #define regGUS_IO_RD_PRI_QUANT_PRI4                                                                     0x2c11
4975 #define regGUS_IO_RD_PRI_QUANT_PRI4_BASE_IDX                                                            1
4976 #define regGUS_IO_WR_PRI_QUANT_PRI1                                                                     0x2c12
4977 #define regGUS_IO_WR_PRI_QUANT_PRI1_BASE_IDX                                                            1
4978 #define regGUS_IO_WR_PRI_QUANT_PRI2                                                                     0x2c13
4979 #define regGUS_IO_WR_PRI_QUANT_PRI2_BASE_IDX                                                            1
4980 #define regGUS_IO_WR_PRI_QUANT_PRI3                                                                     0x2c14
4981 #define regGUS_IO_WR_PRI_QUANT_PRI3_BASE_IDX                                                            1
4982 #define regGUS_IO_WR_PRI_QUANT_PRI4                                                                     0x2c15
4983 #define regGUS_IO_WR_PRI_QUANT_PRI4_BASE_IDX                                                            1
4984 #define regGUS_IO_RD_PRI_QUANT1_PRI1                                                                    0x2c16
4985 #define regGUS_IO_RD_PRI_QUANT1_PRI1_BASE_IDX                                                           1
4986 #define regGUS_IO_RD_PRI_QUANT1_PRI2                                                                    0x2c17
4987 #define regGUS_IO_RD_PRI_QUANT1_PRI2_BASE_IDX                                                           1
4988 #define regGUS_IO_RD_PRI_QUANT1_PRI3                                                                    0x2c18
4989 #define regGUS_IO_RD_PRI_QUANT1_PRI3_BASE_IDX                                                           1
4990 #define regGUS_IO_RD_PRI_QUANT1_PRI4                                                                    0x2c19
4991 #define regGUS_IO_RD_PRI_QUANT1_PRI4_BASE_IDX                                                           1
4992 #define regGUS_IO_WR_PRI_QUANT1_PRI1                                                                    0x2c1a
4993 #define regGUS_IO_WR_PRI_QUANT1_PRI1_BASE_IDX                                                           1
4994 #define regGUS_IO_WR_PRI_QUANT1_PRI2                                                                    0x2c1b
4995 #define regGUS_IO_WR_PRI_QUANT1_PRI2_BASE_IDX                                                           1
4996 #define regGUS_IO_WR_PRI_QUANT1_PRI3                                                                    0x2c1c
4997 #define regGUS_IO_WR_PRI_QUANT1_PRI3_BASE_IDX                                                           1
4998 #define regGUS_IO_WR_PRI_QUANT1_PRI4                                                                    0x2c1d
4999 #define regGUS_IO_WR_PRI_QUANT1_PRI4_BASE_IDX                                                           1
5000 #define regGUS_DRAM_COMBINE_FLUSH                                                                       0x2c1e
5001 #define regGUS_DRAM_COMBINE_FLUSH_BASE_IDX                                                              1
5002 #define regGUS_DRAM_COMBINE_RD_WR_EN                                                                    0x2c1f
5003 #define regGUS_DRAM_COMBINE_RD_WR_EN_BASE_IDX                                                           1
5004 #define regGUS_DRAM_PRI_AGE_RATE                                                                        0x2c20
5005 #define regGUS_DRAM_PRI_AGE_RATE_BASE_IDX                                                               1
5006 #define regGUS_DRAM_PRI_AGE_COEFF                                                                       0x2c21
5007 #define regGUS_DRAM_PRI_AGE_COEFF_BASE_IDX                                                              1
5008 #define regGUS_DRAM_PRI_QUEUING                                                                         0x2c22
5009 #define regGUS_DRAM_PRI_QUEUING_BASE_IDX                                                                1
5010 #define regGUS_DRAM_PRI_FIXED                                                                           0x2c23
5011 #define regGUS_DRAM_PRI_FIXED_BASE_IDX                                                                  1
5012 #define regGUS_DRAM_PRI_URGENCY_COEFF                                                                   0x2c24
5013 #define regGUS_DRAM_PRI_URGENCY_COEFF_BASE_IDX                                                          1
5014 #define regGUS_DRAM_PRI_URGENCY_MODE                                                                    0x2c25
5015 #define regGUS_DRAM_PRI_URGENCY_MODE_BASE_IDX                                                           1
5016 #define regGUS_DRAM_PRI_QUANT_PRI1                                                                      0x2c26
5017 #define regGUS_DRAM_PRI_QUANT_PRI1_BASE_IDX                                                             1
5018 #define regGUS_DRAM_PRI_QUANT_PRI2                                                                      0x2c27
5019 #define regGUS_DRAM_PRI_QUANT_PRI2_BASE_IDX                                                             1
5020 #define regGUS_DRAM_PRI_QUANT_PRI3                                                                      0x2c28
5021 #define regGUS_DRAM_PRI_QUANT_PRI3_BASE_IDX                                                             1
5022 #define regGUS_DRAM_PRI_QUANT_PRI4                                                                      0x2c29
5023 #define regGUS_DRAM_PRI_QUANT_PRI4_BASE_IDX                                                             1
5024 #define regGUS_DRAM_PRI_QUANT_PRI5                                                                      0x2c2a
5025 #define regGUS_DRAM_PRI_QUANT_PRI5_BASE_IDX                                                             1
5026 #define regGUS_DRAM_PRI_QUANT1_PRI1                                                                     0x2c2b
5027 #define regGUS_DRAM_PRI_QUANT1_PRI1_BASE_IDX                                                            1
5028 #define regGUS_DRAM_PRI_QUANT1_PRI2                                                                     0x2c2c
5029 #define regGUS_DRAM_PRI_QUANT1_PRI2_BASE_IDX                                                            1
5030 #define regGUS_DRAM_PRI_QUANT1_PRI3                                                                     0x2c2d
5031 #define regGUS_DRAM_PRI_QUANT1_PRI3_BASE_IDX                                                            1
5032 #define regGUS_DRAM_PRI_QUANT1_PRI4                                                                     0x2c2e
5033 #define regGUS_DRAM_PRI_QUANT1_PRI4_BASE_IDX                                                            1
5034 #define regGUS_DRAM_PRI_QUANT1_PRI5                                                                     0x2c2f
5035 #define regGUS_DRAM_PRI_QUANT1_PRI5_BASE_IDX                                                            1
5036 #define regGUS_IO_GROUP_BURST                                                                           0x2c30
5037 #define regGUS_IO_GROUP_BURST_BASE_IDX                                                                  1
5038 #define regGUS_DRAM_GROUP_BURST                                                                         0x2c31
5039 #define regGUS_DRAM_GROUP_BURST_BASE_IDX                                                                1
5040 #define regGUS_SDP_ARB_FINAL                                                                            0x2c32
5041 #define regGUS_SDP_ARB_FINAL_BASE_IDX                                                                   1
5042 #define regGUS_SDP_QOS_VC_PRIORITY                                                                      0x2c33
5043 #define regGUS_SDP_QOS_VC_PRIORITY_BASE_IDX                                                             1
5044 #define regGUS_SDP_CREDITS                                                                              0x2c34
5045 #define regGUS_SDP_CREDITS_BASE_IDX                                                                     1
5046 #define regGUS_SDP_TAG_RESERVE0                                                                         0x2c35
5047 #define regGUS_SDP_TAG_RESERVE0_BASE_IDX                                                                1
5048 #define regGUS_SDP_TAG_RESERVE1                                                                         0x2c36
5049 #define regGUS_SDP_TAG_RESERVE1_BASE_IDX                                                                1
5050 #define regGUS_SDP_VCC_RESERVE0                                                                         0x2c37
5051 #define regGUS_SDP_VCC_RESERVE0_BASE_IDX                                                                1
5052 #define regGUS_SDP_VCC_RESERVE1                                                                         0x2c38
5053 #define regGUS_SDP_VCC_RESERVE1_BASE_IDX                                                                1
5054 #define regGUS_SDP_VCD_RESERVE0                                                                         0x2c39
5055 #define regGUS_SDP_VCD_RESERVE0_BASE_IDX                                                                1
5056 #define regGUS_SDP_VCD_RESERVE1                                                                         0x2c3a
5057 #define regGUS_SDP_VCD_RESERVE1_BASE_IDX                                                                1
5058 #define regGUS_SDP_REQ_CNTL                                                                             0x2c3b
5059 #define regGUS_SDP_REQ_CNTL_BASE_IDX                                                                    1
5060 #define regGUS_MISC                                                                                     0x2c3c
5061 #define regGUS_MISC_BASE_IDX                                                                            1
5062 #define regGUS_LATENCY_SAMPLING                                                                         0x2c3d
5063 #define regGUS_LATENCY_SAMPLING_BASE_IDX                                                                1
5064 #define regGUS_ERR_STATUS                                                                               0x2c3e
5065 #define regGUS_ERR_STATUS_BASE_IDX                                                                      1
5066 #define regGUS_MISC2                                                                                    0x2c3f
5067 #define regGUS_MISC2_BASE_IDX                                                                           1
5068 #define regGUS_SDP_ENABLE                                                                               0x2c45
5069 #define regGUS_SDP_ENABLE_BASE_IDX                                                                      1
5070 #define regGUS_L1_CH0_CMD_IN                                                                            0x2c46
5071 #define regGUS_L1_CH0_CMD_IN_BASE_IDX                                                                   1
5072 #define regGUS_L1_CH0_CMD_OUT                                                                           0x2c47
5073 #define regGUS_L1_CH0_CMD_OUT_BASE_IDX                                                                  1
5074 #define regGUS_L1_CH0_DATA_IN                                                                           0x2c48
5075 #define regGUS_L1_CH0_DATA_IN_BASE_IDX                                                                  1
5076 #define regGUS_L1_CH0_DATA_OUT                                                                          0x2c49
5077 #define regGUS_L1_CH0_DATA_OUT_BASE_IDX                                                                 1
5078 #define regGUS_L1_CH0_DATA_U_IN                                                                         0x2c4a
5079 #define regGUS_L1_CH0_DATA_U_IN_BASE_IDX                                                                1
5080 #define regGUS_L1_CH0_DATA_U_OUT                                                                        0x2c4b
5081 #define regGUS_L1_CH0_DATA_U_OUT_BASE_IDX                                                               1
5082 #define regGUS_L1_CH1_CMD_IN                                                                            0x2c4c
5083 #define regGUS_L1_CH1_CMD_IN_BASE_IDX                                                                   1
5084 #define regGUS_L1_CH1_CMD_OUT                                                                           0x2c4d
5085 #define regGUS_L1_CH1_CMD_OUT_BASE_IDX                                                                  1
5086 #define regGUS_L1_CH1_DATA_IN                                                                           0x2c4e
5087 #define regGUS_L1_CH1_DATA_IN_BASE_IDX                                                                  1
5088 #define regGUS_L1_CH1_DATA_OUT                                                                          0x2c4f
5089 #define regGUS_L1_CH1_DATA_OUT_BASE_IDX                                                                 1
5090 #define regGUS_L1_CH1_DATA_U_IN                                                                         0x2c50
5091 #define regGUS_L1_CH1_DATA_U_IN_BASE_IDX                                                                1
5092 #define regGUS_L1_CH1_DATA_U_OUT                                                                        0x2c51
5093 #define regGUS_L1_CH1_DATA_U_OUT_BASE_IDX                                                               1
5094 #define regGUS_L1_SA0_CMD_IN                                                                            0x2c52
5095 #define regGUS_L1_SA0_CMD_IN_BASE_IDX                                                                   1
5096 #define regGUS_L1_SA0_CMD_OUT                                                                           0x2c53
5097 #define regGUS_L1_SA0_CMD_OUT_BASE_IDX                                                                  1
5098 #define regGUS_L1_SA0_DATA_IN                                                                           0x2c54
5099 #define regGUS_L1_SA0_DATA_IN_BASE_IDX                                                                  1
5100 #define regGUS_L1_SA0_DATA_OUT                                                                          0x2c55
5101 #define regGUS_L1_SA0_DATA_OUT_BASE_IDX                                                                 1
5102 #define regGUS_L1_SA0_DATA_U_IN                                                                         0x2c56
5103 #define regGUS_L1_SA0_DATA_U_IN_BASE_IDX                                                                1
5104 #define regGUS_L1_SA0_DATA_U_OUT                                                                        0x2c57
5105 #define regGUS_L1_SA0_DATA_U_OUT_BASE_IDX                                                               1
5106 #define regGUS_L1_SA1_CMD_IN                                                                            0x2c58
5107 #define regGUS_L1_SA1_CMD_IN_BASE_IDX                                                                   1
5108 #define regGUS_L1_SA1_CMD_OUT                                                                           0x2c59
5109 #define regGUS_L1_SA1_CMD_OUT_BASE_IDX                                                                  1
5110 #define regGUS_L1_SA1_DATA_IN                                                                           0x2c5a
5111 #define regGUS_L1_SA1_DATA_IN_BASE_IDX                                                                  1
5112 #define regGUS_L1_SA1_DATA_OUT                                                                          0x2c5b
5113 #define regGUS_L1_SA1_DATA_OUT_BASE_IDX                                                                 1
5114 #define regGUS_L1_SA1_DATA_U_IN                                                                         0x2c5c
5115 #define regGUS_L1_SA1_DATA_U_IN_BASE_IDX                                                                1
5116 #define regGUS_L1_SA1_DATA_U_OUT                                                                        0x2c5d
5117 #define regGUS_L1_SA1_DATA_U_OUT_BASE_IDX                                                               1
5118 #define regGUS_L1_SA2_CMD_IN                                                                            0x2c5e
5119 #define regGUS_L1_SA2_CMD_IN_BASE_IDX                                                                   1
5120 #define regGUS_L1_SA2_CMD_OUT                                                                           0x2c5f
5121 #define regGUS_L1_SA2_CMD_OUT_BASE_IDX                                                                  1
5122 #define regGUS_L1_SA2_DATA_IN                                                                           0x2c60
5123 #define regGUS_L1_SA2_DATA_IN_BASE_IDX                                                                  1
5124 #define regGUS_L1_SA2_DATA_OUT                                                                          0x2c61
5125 #define regGUS_L1_SA2_DATA_OUT_BASE_IDX                                                                 1
5126 #define regGUS_L1_SA2_DATA_U_IN                                                                         0x2c62
5127 #define regGUS_L1_SA2_DATA_U_IN_BASE_IDX                                                                1
5128 #define regGUS_L1_SA2_DATA_U_OUT                                                                        0x2c63
5129 #define regGUS_L1_SA2_DATA_U_OUT_BASE_IDX                                                               1
5130 #define regGUS_L1_SA3_CMD_IN                                                                            0x2c64
5131 #define regGUS_L1_SA3_CMD_IN_BASE_IDX                                                                   1
5132 #define regGUS_L1_SA3_CMD_OUT                                                                           0x2c65
5133 #define regGUS_L1_SA3_CMD_OUT_BASE_IDX                                                                  1
5134 #define regGUS_L1_SA3_DATA_IN                                                                           0x2c66
5135 #define regGUS_L1_SA3_DATA_IN_BASE_IDX                                                                  1
5136 #define regGUS_L1_SA3_DATA_OUT                                                                          0x2c67
5137 #define regGUS_L1_SA3_DATA_OUT_BASE_IDX                                                                 1
5138 #define regGUS_L1_SA3_DATA_U_IN                                                                         0x2c68
5139 #define regGUS_L1_SA3_DATA_U_IN_BASE_IDX                                                                1
5140 #define regGUS_L1_SA3_DATA_U_OUT                                                                        0x2c69
5141 #define regGUS_L1_SA3_DATA_U_OUT_BASE_IDX                                                               1
5142 #define regGUS_MISC3                                                                                    0x2c6a
5143 #define regGUS_MISC3_BASE_IDX                                                                           1
5144 #define regGUS_WRRSP_FIFO_CNTL                                                                          0x2c6b
5145 #define regGUS_WRRSP_FIFO_CNTL_BASE_IDX                                                                 1
5146 
5147 
5148 // addressBlock: gc_gfxdec0
5149 // base address: 0x28000
5150 #define regDB_RENDER_CONTROL                                                                            0x0000
5151 #define regDB_RENDER_CONTROL_BASE_IDX                                                                   1
5152 #define regDB_COUNT_CONTROL                                                                             0x0001
5153 #define regDB_COUNT_CONTROL_BASE_IDX                                                                    1
5154 #define regDB_DEPTH_VIEW                                                                                0x0002
5155 #define regDB_DEPTH_VIEW_BASE_IDX                                                                       1
5156 #define regDB_RENDER_OVERRIDE                                                                           0x0003
5157 #define regDB_RENDER_OVERRIDE_BASE_IDX                                                                  1
5158 #define regDB_RENDER_OVERRIDE2                                                                          0x0004
5159 #define regDB_RENDER_OVERRIDE2_BASE_IDX                                                                 1
5160 #define regDB_HTILE_DATA_BASE                                                                           0x0005
5161 #define regDB_HTILE_DATA_BASE_BASE_IDX                                                                  1
5162 #define regDB_DEPTH_SIZE_XY                                                                             0x0007
5163 #define regDB_DEPTH_SIZE_XY_BASE_IDX                                                                    1
5164 #define regDB_DEPTH_BOUNDS_MIN                                                                          0x0008
5165 #define regDB_DEPTH_BOUNDS_MIN_BASE_IDX                                                                 1
5166 #define regDB_DEPTH_BOUNDS_MAX                                                                          0x0009
5167 #define regDB_DEPTH_BOUNDS_MAX_BASE_IDX                                                                 1
5168 #define regDB_STENCIL_CLEAR                                                                             0x000a
5169 #define regDB_STENCIL_CLEAR_BASE_IDX                                                                    1
5170 #define regDB_DEPTH_CLEAR                                                                               0x000b
5171 #define regDB_DEPTH_CLEAR_BASE_IDX                                                                      1
5172 #define regPA_SC_SCREEN_SCISSOR_TL                                                                      0x000c
5173 #define regPA_SC_SCREEN_SCISSOR_TL_BASE_IDX                                                             1
5174 #define regPA_SC_SCREEN_SCISSOR_BR                                                                      0x000d
5175 #define regPA_SC_SCREEN_SCISSOR_BR_BASE_IDX                                                             1
5176 #define regDB_RESERVED_REG_2                                                                            0x000f
5177 #define regDB_RESERVED_REG_2_BASE_IDX                                                                   1
5178 #define regDB_Z_INFO                                                                                    0x0010
5179 #define regDB_Z_INFO_BASE_IDX                                                                           1
5180 #define regDB_STENCIL_INFO                                                                              0x0011
5181 #define regDB_STENCIL_INFO_BASE_IDX                                                                     1
5182 #define regDB_Z_READ_BASE                                                                               0x0012
5183 #define regDB_Z_READ_BASE_BASE_IDX                                                                      1
5184 #define regDB_STENCIL_READ_BASE                                                                         0x0013
5185 #define regDB_STENCIL_READ_BASE_BASE_IDX                                                                1
5186 #define regDB_Z_WRITE_BASE                                                                              0x0014
5187 #define regDB_Z_WRITE_BASE_BASE_IDX                                                                     1
5188 #define regDB_STENCIL_WRITE_BASE                                                                        0x0015
5189 #define regDB_STENCIL_WRITE_BASE_BASE_IDX                                                               1
5190 #define regDB_RESERVED_REG_1                                                                            0x0016
5191 #define regDB_RESERVED_REG_1_BASE_IDX                                                                   1
5192 #define regDB_RESERVED_REG_3                                                                            0x0017
5193 #define regDB_RESERVED_REG_3_BASE_IDX                                                                   1
5194 #define regDB_Z_READ_BASE_HI                                                                            0x001a
5195 #define regDB_Z_READ_BASE_HI_BASE_IDX                                                                   1
5196 #define regDB_STENCIL_READ_BASE_HI                                                                      0x001b
5197 #define regDB_STENCIL_READ_BASE_HI_BASE_IDX                                                             1
5198 #define regDB_Z_WRITE_BASE_HI                                                                           0x001c
5199 #define regDB_Z_WRITE_BASE_HI_BASE_IDX                                                                  1
5200 #define regDB_STENCIL_WRITE_BASE_HI                                                                     0x001d
5201 #define regDB_STENCIL_WRITE_BASE_HI_BASE_IDX                                                            1
5202 #define regDB_HTILE_DATA_BASE_HI                                                                        0x001e
5203 #define regDB_HTILE_DATA_BASE_HI_BASE_IDX                                                               1
5204 #define regDB_RMI_L2_CACHE_CONTROL                                                                      0x001f
5205 #define regDB_RMI_L2_CACHE_CONTROL_BASE_IDX                                                             1
5206 #define regTA_BC_BASE_ADDR                                                                              0x0020
5207 #define regTA_BC_BASE_ADDR_BASE_IDX                                                                     1
5208 #define regTA_BC_BASE_ADDR_HI                                                                           0x0021
5209 #define regTA_BC_BASE_ADDR_HI_BASE_IDX                                                                  1
5210 #define regCOHER_DEST_BASE_HI_0                                                                         0x007a
5211 #define regCOHER_DEST_BASE_HI_0_BASE_IDX                                                                1
5212 #define regCOHER_DEST_BASE_HI_1                                                                         0x007b
5213 #define regCOHER_DEST_BASE_HI_1_BASE_IDX                                                                1
5214 #define regCOHER_DEST_BASE_HI_2                                                                         0x007c
5215 #define regCOHER_DEST_BASE_HI_2_BASE_IDX                                                                1
5216 #define regCOHER_DEST_BASE_HI_3                                                                         0x007d
5217 #define regCOHER_DEST_BASE_HI_3_BASE_IDX                                                                1
5218 #define regCOHER_DEST_BASE_2                                                                            0x007e
5219 #define regCOHER_DEST_BASE_2_BASE_IDX                                                                   1
5220 #define regCOHER_DEST_BASE_3                                                                            0x007f
5221 #define regCOHER_DEST_BASE_3_BASE_IDX                                                                   1
5222 #define regPA_SC_WINDOW_OFFSET                                                                          0x0080
5223 #define regPA_SC_WINDOW_OFFSET_BASE_IDX                                                                 1
5224 #define regPA_SC_WINDOW_SCISSOR_TL                                                                      0x0081
5225 #define regPA_SC_WINDOW_SCISSOR_TL_BASE_IDX                                                             1
5226 #define regPA_SC_WINDOW_SCISSOR_BR                                                                      0x0082
5227 #define regPA_SC_WINDOW_SCISSOR_BR_BASE_IDX                                                             1
5228 #define regPA_SC_CLIPRECT_RULE                                                                          0x0083
5229 #define regPA_SC_CLIPRECT_RULE_BASE_IDX                                                                 1
5230 #define regPA_SC_CLIPRECT_0_TL                                                                          0x0084
5231 #define regPA_SC_CLIPRECT_0_TL_BASE_IDX                                                                 1
5232 #define regPA_SC_CLIPRECT_0_BR                                                                          0x0085
5233 #define regPA_SC_CLIPRECT_0_BR_BASE_IDX                                                                 1
5234 #define regPA_SC_CLIPRECT_1_TL                                                                          0x0086
5235 #define regPA_SC_CLIPRECT_1_TL_BASE_IDX                                                                 1
5236 #define regPA_SC_CLIPRECT_1_BR                                                                          0x0087
5237 #define regPA_SC_CLIPRECT_1_BR_BASE_IDX                                                                 1
5238 #define regPA_SC_CLIPRECT_2_TL                                                                          0x0088
5239 #define regPA_SC_CLIPRECT_2_TL_BASE_IDX                                                                 1
5240 #define regPA_SC_CLIPRECT_2_BR                                                                          0x0089
5241 #define regPA_SC_CLIPRECT_2_BR_BASE_IDX                                                                 1
5242 #define regPA_SC_CLIPRECT_3_TL                                                                          0x008a
5243 #define regPA_SC_CLIPRECT_3_TL_BASE_IDX                                                                 1
5244 #define regPA_SC_CLIPRECT_3_BR                                                                          0x008b
5245 #define regPA_SC_CLIPRECT_3_BR_BASE_IDX                                                                 1
5246 #define regPA_SC_EDGERULE                                                                               0x008c
5247 #define regPA_SC_EDGERULE_BASE_IDX                                                                      1
5248 #define regPA_SU_HARDWARE_SCREEN_OFFSET                                                                 0x008d
5249 #define regPA_SU_HARDWARE_SCREEN_OFFSET_BASE_IDX                                                        1
5250 #define regCB_TARGET_MASK                                                                               0x008e
5251 #define regCB_TARGET_MASK_BASE_IDX                                                                      1
5252 #define regCB_SHADER_MASK                                                                               0x008f
5253 #define regCB_SHADER_MASK_BASE_IDX                                                                      1
5254 #define regPA_SC_GENERIC_SCISSOR_TL                                                                     0x0090
5255 #define regPA_SC_GENERIC_SCISSOR_TL_BASE_IDX                                                            1
5256 #define regPA_SC_GENERIC_SCISSOR_BR                                                                     0x0091
5257 #define regPA_SC_GENERIC_SCISSOR_BR_BASE_IDX                                                            1
5258 #define regCOHER_DEST_BASE_0                                                                            0x0092
5259 #define regCOHER_DEST_BASE_0_BASE_IDX                                                                   1
5260 #define regCOHER_DEST_BASE_1                                                                            0x0093
5261 #define regCOHER_DEST_BASE_1_BASE_IDX                                                                   1
5262 #define regPA_SC_VPORT_SCISSOR_0_TL                                                                     0x0094
5263 #define regPA_SC_VPORT_SCISSOR_0_TL_BASE_IDX                                                            1
5264 #define regPA_SC_VPORT_SCISSOR_0_BR                                                                     0x0095
5265 #define regPA_SC_VPORT_SCISSOR_0_BR_BASE_IDX                                                            1
5266 #define regPA_SC_VPORT_SCISSOR_1_TL                                                                     0x0096
5267 #define regPA_SC_VPORT_SCISSOR_1_TL_BASE_IDX                                                            1
5268 #define regPA_SC_VPORT_SCISSOR_1_BR                                                                     0x0097
5269 #define regPA_SC_VPORT_SCISSOR_1_BR_BASE_IDX                                                            1
5270 #define regPA_SC_VPORT_SCISSOR_2_TL                                                                     0x0098
5271 #define regPA_SC_VPORT_SCISSOR_2_TL_BASE_IDX                                                            1
5272 #define regPA_SC_VPORT_SCISSOR_2_BR                                                                     0x0099
5273 #define regPA_SC_VPORT_SCISSOR_2_BR_BASE_IDX                                                            1
5274 #define regPA_SC_VPORT_SCISSOR_3_TL                                                                     0x009a
5275 #define regPA_SC_VPORT_SCISSOR_3_TL_BASE_IDX                                                            1
5276 #define regPA_SC_VPORT_SCISSOR_3_BR                                                                     0x009b
5277 #define regPA_SC_VPORT_SCISSOR_3_BR_BASE_IDX                                                            1
5278 #define regPA_SC_VPORT_SCISSOR_4_TL                                                                     0x009c
5279 #define regPA_SC_VPORT_SCISSOR_4_TL_BASE_IDX                                                            1
5280 #define regPA_SC_VPORT_SCISSOR_4_BR                                                                     0x009d
5281 #define regPA_SC_VPORT_SCISSOR_4_BR_BASE_IDX                                                            1
5282 #define regPA_SC_VPORT_SCISSOR_5_TL                                                                     0x009e
5283 #define regPA_SC_VPORT_SCISSOR_5_TL_BASE_IDX                                                            1
5284 #define regPA_SC_VPORT_SCISSOR_5_BR                                                                     0x009f
5285 #define regPA_SC_VPORT_SCISSOR_5_BR_BASE_IDX                                                            1
5286 #define regPA_SC_VPORT_SCISSOR_6_TL                                                                     0x00a0
5287 #define regPA_SC_VPORT_SCISSOR_6_TL_BASE_IDX                                                            1
5288 #define regPA_SC_VPORT_SCISSOR_6_BR                                                                     0x00a1
5289 #define regPA_SC_VPORT_SCISSOR_6_BR_BASE_IDX                                                            1
5290 #define regPA_SC_VPORT_SCISSOR_7_TL                                                                     0x00a2
5291 #define regPA_SC_VPORT_SCISSOR_7_TL_BASE_IDX                                                            1
5292 #define regPA_SC_VPORT_SCISSOR_7_BR                                                                     0x00a3
5293 #define regPA_SC_VPORT_SCISSOR_7_BR_BASE_IDX                                                            1
5294 #define regPA_SC_VPORT_SCISSOR_8_TL                                                                     0x00a4
5295 #define regPA_SC_VPORT_SCISSOR_8_TL_BASE_IDX                                                            1
5296 #define regPA_SC_VPORT_SCISSOR_8_BR                                                                     0x00a5
5297 #define regPA_SC_VPORT_SCISSOR_8_BR_BASE_IDX                                                            1
5298 #define regPA_SC_VPORT_SCISSOR_9_TL                                                                     0x00a6
5299 #define regPA_SC_VPORT_SCISSOR_9_TL_BASE_IDX                                                            1
5300 #define regPA_SC_VPORT_SCISSOR_9_BR                                                                     0x00a7
5301 #define regPA_SC_VPORT_SCISSOR_9_BR_BASE_IDX                                                            1
5302 #define regPA_SC_VPORT_SCISSOR_10_TL                                                                    0x00a8
5303 #define regPA_SC_VPORT_SCISSOR_10_TL_BASE_IDX                                                           1
5304 #define regPA_SC_VPORT_SCISSOR_10_BR                                                                    0x00a9
5305 #define regPA_SC_VPORT_SCISSOR_10_BR_BASE_IDX                                                           1
5306 #define regPA_SC_VPORT_SCISSOR_11_TL                                                                    0x00aa
5307 #define regPA_SC_VPORT_SCISSOR_11_TL_BASE_IDX                                                           1
5308 #define regPA_SC_VPORT_SCISSOR_11_BR                                                                    0x00ab
5309 #define regPA_SC_VPORT_SCISSOR_11_BR_BASE_IDX                                                           1
5310 #define regPA_SC_VPORT_SCISSOR_12_TL                                                                    0x00ac
5311 #define regPA_SC_VPORT_SCISSOR_12_TL_BASE_IDX                                                           1
5312 #define regPA_SC_VPORT_SCISSOR_12_BR                                                                    0x00ad
5313 #define regPA_SC_VPORT_SCISSOR_12_BR_BASE_IDX                                                           1
5314 #define regPA_SC_VPORT_SCISSOR_13_TL                                                                    0x00ae
5315 #define regPA_SC_VPORT_SCISSOR_13_TL_BASE_IDX                                                           1
5316 #define regPA_SC_VPORT_SCISSOR_13_BR                                                                    0x00af
5317 #define regPA_SC_VPORT_SCISSOR_13_BR_BASE_IDX                                                           1
5318 #define regPA_SC_VPORT_SCISSOR_14_TL                                                                    0x00b0
5319 #define regPA_SC_VPORT_SCISSOR_14_TL_BASE_IDX                                                           1
5320 #define regPA_SC_VPORT_SCISSOR_14_BR                                                                    0x00b1
5321 #define regPA_SC_VPORT_SCISSOR_14_BR_BASE_IDX                                                           1
5322 #define regPA_SC_VPORT_SCISSOR_15_TL                                                                    0x00b2
5323 #define regPA_SC_VPORT_SCISSOR_15_TL_BASE_IDX                                                           1
5324 #define regPA_SC_VPORT_SCISSOR_15_BR                                                                    0x00b3
5325 #define regPA_SC_VPORT_SCISSOR_15_BR_BASE_IDX                                                           1
5326 #define regPA_SC_VPORT_ZMIN_0                                                                           0x00b4
5327 #define regPA_SC_VPORT_ZMIN_0_BASE_IDX                                                                  1
5328 #define regPA_SC_VPORT_ZMAX_0                                                                           0x00b5
5329 #define regPA_SC_VPORT_ZMAX_0_BASE_IDX                                                                  1
5330 #define regPA_SC_VPORT_ZMIN_1                                                                           0x00b6
5331 #define regPA_SC_VPORT_ZMIN_1_BASE_IDX                                                                  1
5332 #define regPA_SC_VPORT_ZMAX_1                                                                           0x00b7
5333 #define regPA_SC_VPORT_ZMAX_1_BASE_IDX                                                                  1
5334 #define regPA_SC_VPORT_ZMIN_2                                                                           0x00b8
5335 #define regPA_SC_VPORT_ZMIN_2_BASE_IDX                                                                  1
5336 #define regPA_SC_VPORT_ZMAX_2                                                                           0x00b9
5337 #define regPA_SC_VPORT_ZMAX_2_BASE_IDX                                                                  1
5338 #define regPA_SC_VPORT_ZMIN_3                                                                           0x00ba
5339 #define regPA_SC_VPORT_ZMIN_3_BASE_IDX                                                                  1
5340 #define regPA_SC_VPORT_ZMAX_3                                                                           0x00bb
5341 #define regPA_SC_VPORT_ZMAX_3_BASE_IDX                                                                  1
5342 #define regPA_SC_VPORT_ZMIN_4                                                                           0x00bc
5343 #define regPA_SC_VPORT_ZMIN_4_BASE_IDX                                                                  1
5344 #define regPA_SC_VPORT_ZMAX_4                                                                           0x00bd
5345 #define regPA_SC_VPORT_ZMAX_4_BASE_IDX                                                                  1
5346 #define regPA_SC_VPORT_ZMIN_5                                                                           0x00be
5347 #define regPA_SC_VPORT_ZMIN_5_BASE_IDX                                                                  1
5348 #define regPA_SC_VPORT_ZMAX_5                                                                           0x00bf
5349 #define regPA_SC_VPORT_ZMAX_5_BASE_IDX                                                                  1
5350 #define regPA_SC_VPORT_ZMIN_6                                                                           0x00c0
5351 #define regPA_SC_VPORT_ZMIN_6_BASE_IDX                                                                  1
5352 #define regPA_SC_VPORT_ZMAX_6                                                                           0x00c1
5353 #define regPA_SC_VPORT_ZMAX_6_BASE_IDX                                                                  1
5354 #define regPA_SC_VPORT_ZMIN_7                                                                           0x00c2
5355 #define regPA_SC_VPORT_ZMIN_7_BASE_IDX                                                                  1
5356 #define regPA_SC_VPORT_ZMAX_7                                                                           0x00c3
5357 #define regPA_SC_VPORT_ZMAX_7_BASE_IDX                                                                  1
5358 #define regPA_SC_VPORT_ZMIN_8                                                                           0x00c4
5359 #define regPA_SC_VPORT_ZMIN_8_BASE_IDX                                                                  1
5360 #define regPA_SC_VPORT_ZMAX_8                                                                           0x00c5
5361 #define regPA_SC_VPORT_ZMAX_8_BASE_IDX                                                                  1
5362 #define regPA_SC_VPORT_ZMIN_9                                                                           0x00c6
5363 #define regPA_SC_VPORT_ZMIN_9_BASE_IDX                                                                  1
5364 #define regPA_SC_VPORT_ZMAX_9                                                                           0x00c7
5365 #define regPA_SC_VPORT_ZMAX_9_BASE_IDX                                                                  1
5366 #define regPA_SC_VPORT_ZMIN_10                                                                          0x00c8
5367 #define regPA_SC_VPORT_ZMIN_10_BASE_IDX                                                                 1
5368 #define regPA_SC_VPORT_ZMAX_10                                                                          0x00c9
5369 #define regPA_SC_VPORT_ZMAX_10_BASE_IDX                                                                 1
5370 #define regPA_SC_VPORT_ZMIN_11                                                                          0x00ca
5371 #define regPA_SC_VPORT_ZMIN_11_BASE_IDX                                                                 1
5372 #define regPA_SC_VPORT_ZMAX_11                                                                          0x00cb
5373 #define regPA_SC_VPORT_ZMAX_11_BASE_IDX                                                                 1
5374 #define regPA_SC_VPORT_ZMIN_12                                                                          0x00cc
5375 #define regPA_SC_VPORT_ZMIN_12_BASE_IDX                                                                 1
5376 #define regPA_SC_VPORT_ZMAX_12                                                                          0x00cd
5377 #define regPA_SC_VPORT_ZMAX_12_BASE_IDX                                                                 1
5378 #define regPA_SC_VPORT_ZMIN_13                                                                          0x00ce
5379 #define regPA_SC_VPORT_ZMIN_13_BASE_IDX                                                                 1
5380 #define regPA_SC_VPORT_ZMAX_13                                                                          0x00cf
5381 #define regPA_SC_VPORT_ZMAX_13_BASE_IDX                                                                 1
5382 #define regPA_SC_VPORT_ZMIN_14                                                                          0x00d0
5383 #define regPA_SC_VPORT_ZMIN_14_BASE_IDX                                                                 1
5384 #define regPA_SC_VPORT_ZMAX_14                                                                          0x00d1
5385 #define regPA_SC_VPORT_ZMAX_14_BASE_IDX                                                                 1
5386 #define regPA_SC_VPORT_ZMIN_15                                                                          0x00d2
5387 #define regPA_SC_VPORT_ZMIN_15_BASE_IDX                                                                 1
5388 #define regPA_SC_VPORT_ZMAX_15                                                                          0x00d3
5389 #define regPA_SC_VPORT_ZMAX_15_BASE_IDX                                                                 1
5390 #define regPA_SC_RASTER_CONFIG                                                                          0x00d4
5391 #define regPA_SC_RASTER_CONFIG_BASE_IDX                                                                 1
5392 #define regPA_SC_RASTER_CONFIG_1                                                                        0x00d5
5393 #define regPA_SC_RASTER_CONFIG_1_BASE_IDX                                                               1
5394 #define regPA_SC_SCREEN_EXTENT_CONTROL                                                                  0x00d6
5395 #define regPA_SC_SCREEN_EXTENT_CONTROL_BASE_IDX                                                         1
5396 #define regPA_SC_TILE_STEERING_OVERRIDE                                                                 0x00d7
5397 #define regPA_SC_TILE_STEERING_OVERRIDE_BASE_IDX                                                        1
5398 #define regCP_PERFMON_CNTX_CNTL                                                                         0x00d8
5399 #define regCP_PERFMON_CNTX_CNTL_BASE_IDX                                                                1
5400 #define regCP_PIPEID                                                                                    0x00d9
5401 #define regCP_PIPEID_BASE_IDX                                                                           1
5402 #define regCP_RINGID                                                                                    0x00d9
5403 #define regCP_RINGID_BASE_IDX                                                                           1
5404 #define regCP_VMID                                                                                      0x00da
5405 #define regCP_VMID_BASE_IDX                                                                             1
5406 #define regCONTEXT_RESERVED_REG0                                                                        0x00db
5407 #define regCONTEXT_RESERVED_REG0_BASE_IDX                                                               1
5408 #define regCONTEXT_RESERVED_REG1                                                                        0x00dc
5409 #define regCONTEXT_RESERVED_REG1_BASE_IDX                                                               1
5410 #define regPA_SC_VRS_OVERRIDE_CNTL                                                                      0x00f4
5411 #define regPA_SC_VRS_OVERRIDE_CNTL_BASE_IDX                                                             1
5412 #define regPA_SC_VRS_RATE_FEEDBACK_BASE                                                                 0x00f5
5413 #define regPA_SC_VRS_RATE_FEEDBACK_BASE_BASE_IDX                                                        1
5414 #define regPA_SC_VRS_RATE_FEEDBACK_BASE_EXT                                                             0x00f6
5415 #define regPA_SC_VRS_RATE_FEEDBACK_BASE_EXT_BASE_IDX                                                    1
5416 #define regPA_SC_VRS_RATE_FEEDBACK_SIZE_XY                                                              0x00f7
5417 #define regPA_SC_VRS_RATE_FEEDBACK_SIZE_XY_BASE_IDX                                                     1
5418 #define regPA_SC_VRS_RATE_CACHE_CNTL                                                                    0x00f9
5419 #define regPA_SC_VRS_RATE_CACHE_CNTL_BASE_IDX                                                           1
5420 #define regPA_SC_VRS_RATE_BASE                                                                          0x00fc
5421 #define regPA_SC_VRS_RATE_BASE_BASE_IDX                                                                 1
5422 #define regPA_SC_VRS_RATE_BASE_EXT                                                                      0x00fd
5423 #define regPA_SC_VRS_RATE_BASE_EXT_BASE_IDX                                                             1
5424 #define regPA_SC_VRS_RATE_SIZE_XY                                                                       0x00fe
5425 #define regPA_SC_VRS_RATE_SIZE_XY_BASE_IDX                                                              1
5426 #define regVGT_MULTI_PRIM_IB_RESET_INDX                                                                 0x0103
5427 #define regVGT_MULTI_PRIM_IB_RESET_INDX_BASE_IDX                                                        1
5428 #define regCB_RMI_GL2_CACHE_CONTROL                                                                     0x0104
5429 #define regCB_RMI_GL2_CACHE_CONTROL_BASE_IDX                                                            1
5430 #define regCB_BLEND_RED                                                                                 0x0105
5431 #define regCB_BLEND_RED_BASE_IDX                                                                        1
5432 #define regCB_BLEND_GREEN                                                                               0x0106
5433 #define regCB_BLEND_GREEN_BASE_IDX                                                                      1
5434 #define regCB_BLEND_BLUE                                                                                0x0107
5435 #define regCB_BLEND_BLUE_BASE_IDX                                                                       1
5436 #define regCB_BLEND_ALPHA                                                                               0x0108
5437 #define regCB_BLEND_ALPHA_BASE_IDX                                                                      1
5438 #define regCB_FDCC_CONTROL                                                                              0x0109
5439 #define regCB_FDCC_CONTROL_BASE_IDX                                                                     1
5440 #define regCB_COVERAGE_OUT_CONTROL                                                                      0x010a
5441 #define regCB_COVERAGE_OUT_CONTROL_BASE_IDX                                                             1
5442 #define regDB_STENCIL_CONTROL                                                                           0x010b
5443 #define regDB_STENCIL_CONTROL_BASE_IDX                                                                  1
5444 #define regDB_STENCILREFMASK                                                                            0x010c
5445 #define regDB_STENCILREFMASK_BASE_IDX                                                                   1
5446 #define regDB_STENCILREFMASK_BF                                                                         0x010d
5447 #define regDB_STENCILREFMASK_BF_BASE_IDX                                                                1
5448 #define regPA_CL_VPORT_XSCALE                                                                           0x010f
5449 #define regPA_CL_VPORT_XSCALE_BASE_IDX                                                                  1
5450 #define regPA_CL_VPORT_XOFFSET                                                                          0x0110
5451 #define regPA_CL_VPORT_XOFFSET_BASE_IDX                                                                 1
5452 #define regPA_CL_VPORT_YSCALE                                                                           0x0111
5453 #define regPA_CL_VPORT_YSCALE_BASE_IDX                                                                  1
5454 #define regPA_CL_VPORT_YOFFSET                                                                          0x0112
5455 #define regPA_CL_VPORT_YOFFSET_BASE_IDX                                                                 1
5456 #define regPA_CL_VPORT_ZSCALE                                                                           0x0113
5457 #define regPA_CL_VPORT_ZSCALE_BASE_IDX                                                                  1
5458 #define regPA_CL_VPORT_ZOFFSET                                                                          0x0114
5459 #define regPA_CL_VPORT_ZOFFSET_BASE_IDX                                                                 1
5460 #define regPA_CL_VPORT_XSCALE_1                                                                         0x0115
5461 #define regPA_CL_VPORT_XSCALE_1_BASE_IDX                                                                1
5462 #define regPA_CL_VPORT_XOFFSET_1                                                                        0x0116
5463 #define regPA_CL_VPORT_XOFFSET_1_BASE_IDX                                                               1
5464 #define regPA_CL_VPORT_YSCALE_1                                                                         0x0117
5465 #define regPA_CL_VPORT_YSCALE_1_BASE_IDX                                                                1
5466 #define regPA_CL_VPORT_YOFFSET_1                                                                        0x0118
5467 #define regPA_CL_VPORT_YOFFSET_1_BASE_IDX                                                               1
5468 #define regPA_CL_VPORT_ZSCALE_1                                                                         0x0119
5469 #define regPA_CL_VPORT_ZSCALE_1_BASE_IDX                                                                1
5470 #define regPA_CL_VPORT_ZOFFSET_1                                                                        0x011a
5471 #define regPA_CL_VPORT_ZOFFSET_1_BASE_IDX                                                               1
5472 #define regPA_CL_VPORT_XSCALE_2                                                                         0x011b
5473 #define regPA_CL_VPORT_XSCALE_2_BASE_IDX                                                                1
5474 #define regPA_CL_VPORT_XOFFSET_2                                                                        0x011c
5475 #define regPA_CL_VPORT_XOFFSET_2_BASE_IDX                                                               1
5476 #define regPA_CL_VPORT_YSCALE_2                                                                         0x011d
5477 #define regPA_CL_VPORT_YSCALE_2_BASE_IDX                                                                1
5478 #define regPA_CL_VPORT_YOFFSET_2                                                                        0x011e
5479 #define regPA_CL_VPORT_YOFFSET_2_BASE_IDX                                                               1
5480 #define regPA_CL_VPORT_ZSCALE_2                                                                         0x011f
5481 #define regPA_CL_VPORT_ZSCALE_2_BASE_IDX                                                                1
5482 #define regPA_CL_VPORT_ZOFFSET_2                                                                        0x0120
5483 #define regPA_CL_VPORT_ZOFFSET_2_BASE_IDX                                                               1
5484 #define regPA_CL_VPORT_XSCALE_3                                                                         0x0121
5485 #define regPA_CL_VPORT_XSCALE_3_BASE_IDX                                                                1
5486 #define regPA_CL_VPORT_XOFFSET_3                                                                        0x0122
5487 #define regPA_CL_VPORT_XOFFSET_3_BASE_IDX                                                               1
5488 #define regPA_CL_VPORT_YSCALE_3                                                                         0x0123
5489 #define regPA_CL_VPORT_YSCALE_3_BASE_IDX                                                                1
5490 #define regPA_CL_VPORT_YOFFSET_3                                                                        0x0124
5491 #define regPA_CL_VPORT_YOFFSET_3_BASE_IDX                                                               1
5492 #define regPA_CL_VPORT_ZSCALE_3                                                                         0x0125
5493 #define regPA_CL_VPORT_ZSCALE_3_BASE_IDX                                                                1
5494 #define regPA_CL_VPORT_ZOFFSET_3                                                                        0x0126
5495 #define regPA_CL_VPORT_ZOFFSET_3_BASE_IDX                                                               1
5496 #define regPA_CL_VPORT_XSCALE_4                                                                         0x0127
5497 #define regPA_CL_VPORT_XSCALE_4_BASE_IDX                                                                1
5498 #define regPA_CL_VPORT_XOFFSET_4                                                                        0x0128
5499 #define regPA_CL_VPORT_XOFFSET_4_BASE_IDX                                                               1
5500 #define regPA_CL_VPORT_YSCALE_4                                                                         0x0129
5501 #define regPA_CL_VPORT_YSCALE_4_BASE_IDX                                                                1
5502 #define regPA_CL_VPORT_YOFFSET_4                                                                        0x012a
5503 #define regPA_CL_VPORT_YOFFSET_4_BASE_IDX                                                               1
5504 #define regPA_CL_VPORT_ZSCALE_4                                                                         0x012b
5505 #define regPA_CL_VPORT_ZSCALE_4_BASE_IDX                                                                1
5506 #define regPA_CL_VPORT_ZOFFSET_4                                                                        0x012c
5507 #define regPA_CL_VPORT_ZOFFSET_4_BASE_IDX                                                               1
5508 #define regPA_CL_VPORT_XSCALE_5                                                                         0x012d
5509 #define regPA_CL_VPORT_XSCALE_5_BASE_IDX                                                                1
5510 #define regPA_CL_VPORT_XOFFSET_5                                                                        0x012e
5511 #define regPA_CL_VPORT_XOFFSET_5_BASE_IDX                                                               1
5512 #define regPA_CL_VPORT_YSCALE_5                                                                         0x012f
5513 #define regPA_CL_VPORT_YSCALE_5_BASE_IDX                                                                1
5514 #define regPA_CL_VPORT_YOFFSET_5                                                                        0x0130
5515 #define regPA_CL_VPORT_YOFFSET_5_BASE_IDX                                                               1
5516 #define regPA_CL_VPORT_ZSCALE_5                                                                         0x0131
5517 #define regPA_CL_VPORT_ZSCALE_5_BASE_IDX                                                                1
5518 #define regPA_CL_VPORT_ZOFFSET_5                                                                        0x0132
5519 #define regPA_CL_VPORT_ZOFFSET_5_BASE_IDX                                                               1
5520 #define regPA_CL_VPORT_XSCALE_6                                                                         0x0133
5521 #define regPA_CL_VPORT_XSCALE_6_BASE_IDX                                                                1
5522 #define regPA_CL_VPORT_XOFFSET_6                                                                        0x0134
5523 #define regPA_CL_VPORT_XOFFSET_6_BASE_IDX                                                               1
5524 #define regPA_CL_VPORT_YSCALE_6                                                                         0x0135
5525 #define regPA_CL_VPORT_YSCALE_6_BASE_IDX                                                                1
5526 #define regPA_CL_VPORT_YOFFSET_6                                                                        0x0136
5527 #define regPA_CL_VPORT_YOFFSET_6_BASE_IDX                                                               1
5528 #define regPA_CL_VPORT_ZSCALE_6                                                                         0x0137
5529 #define regPA_CL_VPORT_ZSCALE_6_BASE_IDX                                                                1
5530 #define regPA_CL_VPORT_ZOFFSET_6                                                                        0x0138
5531 #define regPA_CL_VPORT_ZOFFSET_6_BASE_IDX                                                               1
5532 #define regPA_CL_VPORT_XSCALE_7                                                                         0x0139
5533 #define regPA_CL_VPORT_XSCALE_7_BASE_IDX                                                                1
5534 #define regPA_CL_VPORT_XOFFSET_7                                                                        0x013a
5535 #define regPA_CL_VPORT_XOFFSET_7_BASE_IDX                                                               1
5536 #define regPA_CL_VPORT_YSCALE_7                                                                         0x013b
5537 #define regPA_CL_VPORT_YSCALE_7_BASE_IDX                                                                1
5538 #define regPA_CL_VPORT_YOFFSET_7                                                                        0x013c
5539 #define regPA_CL_VPORT_YOFFSET_7_BASE_IDX                                                               1
5540 #define regPA_CL_VPORT_ZSCALE_7                                                                         0x013d
5541 #define regPA_CL_VPORT_ZSCALE_7_BASE_IDX                                                                1
5542 #define regPA_CL_VPORT_ZOFFSET_7                                                                        0x013e
5543 #define regPA_CL_VPORT_ZOFFSET_7_BASE_IDX                                                               1
5544 #define regPA_CL_VPORT_XSCALE_8                                                                         0x013f
5545 #define regPA_CL_VPORT_XSCALE_8_BASE_IDX                                                                1
5546 #define regPA_CL_VPORT_XOFFSET_8                                                                        0x0140
5547 #define regPA_CL_VPORT_XOFFSET_8_BASE_IDX                                                               1
5548 #define regPA_CL_VPORT_YSCALE_8                                                                         0x0141
5549 #define regPA_CL_VPORT_YSCALE_8_BASE_IDX                                                                1
5550 #define regPA_CL_VPORT_YOFFSET_8                                                                        0x0142
5551 #define regPA_CL_VPORT_YOFFSET_8_BASE_IDX                                                               1
5552 #define regPA_CL_VPORT_ZSCALE_8                                                                         0x0143
5553 #define regPA_CL_VPORT_ZSCALE_8_BASE_IDX                                                                1
5554 #define regPA_CL_VPORT_ZOFFSET_8                                                                        0x0144
5555 #define regPA_CL_VPORT_ZOFFSET_8_BASE_IDX                                                               1
5556 #define regPA_CL_VPORT_XSCALE_9                                                                         0x0145
5557 #define regPA_CL_VPORT_XSCALE_9_BASE_IDX                                                                1
5558 #define regPA_CL_VPORT_XOFFSET_9                                                                        0x0146
5559 #define regPA_CL_VPORT_XOFFSET_9_BASE_IDX                                                               1
5560 #define regPA_CL_VPORT_YSCALE_9                                                                         0x0147
5561 #define regPA_CL_VPORT_YSCALE_9_BASE_IDX                                                                1
5562 #define regPA_CL_VPORT_YOFFSET_9                                                                        0x0148
5563 #define regPA_CL_VPORT_YOFFSET_9_BASE_IDX                                                               1
5564 #define regPA_CL_VPORT_ZSCALE_9                                                                         0x0149
5565 #define regPA_CL_VPORT_ZSCALE_9_BASE_IDX                                                                1
5566 #define regPA_CL_VPORT_ZOFFSET_9                                                                        0x014a
5567 #define regPA_CL_VPORT_ZOFFSET_9_BASE_IDX                                                               1
5568 #define regPA_CL_VPORT_XSCALE_10                                                                        0x014b
5569 #define regPA_CL_VPORT_XSCALE_10_BASE_IDX                                                               1
5570 #define regPA_CL_VPORT_XOFFSET_10                                                                       0x014c
5571 #define regPA_CL_VPORT_XOFFSET_10_BASE_IDX                                                              1
5572 #define regPA_CL_VPORT_YSCALE_10                                                                        0x014d
5573 #define regPA_CL_VPORT_YSCALE_10_BASE_IDX                                                               1
5574 #define regPA_CL_VPORT_YOFFSET_10                                                                       0x014e
5575 #define regPA_CL_VPORT_YOFFSET_10_BASE_IDX                                                              1
5576 #define regPA_CL_VPORT_ZSCALE_10                                                                        0x014f
5577 #define regPA_CL_VPORT_ZSCALE_10_BASE_IDX                                                               1
5578 #define regPA_CL_VPORT_ZOFFSET_10                                                                       0x0150
5579 #define regPA_CL_VPORT_ZOFFSET_10_BASE_IDX                                                              1
5580 #define regPA_CL_VPORT_XSCALE_11                                                                        0x0151
5581 #define regPA_CL_VPORT_XSCALE_11_BASE_IDX                                                               1
5582 #define regPA_CL_VPORT_XOFFSET_11                                                                       0x0152
5583 #define regPA_CL_VPORT_XOFFSET_11_BASE_IDX                                                              1
5584 #define regPA_CL_VPORT_YSCALE_11                                                                        0x0153
5585 #define regPA_CL_VPORT_YSCALE_11_BASE_IDX                                                               1
5586 #define regPA_CL_VPORT_YOFFSET_11                                                                       0x0154
5587 #define regPA_CL_VPORT_YOFFSET_11_BASE_IDX                                                              1
5588 #define regPA_CL_VPORT_ZSCALE_11                                                                        0x0155
5589 #define regPA_CL_VPORT_ZSCALE_11_BASE_IDX                                                               1
5590 #define regPA_CL_VPORT_ZOFFSET_11                                                                       0x0156
5591 #define regPA_CL_VPORT_ZOFFSET_11_BASE_IDX                                                              1
5592 #define regPA_CL_VPORT_XSCALE_12                                                                        0x0157
5593 #define regPA_CL_VPORT_XSCALE_12_BASE_IDX                                                               1
5594 #define regPA_CL_VPORT_XOFFSET_12                                                                       0x0158
5595 #define regPA_CL_VPORT_XOFFSET_12_BASE_IDX                                                              1
5596 #define regPA_CL_VPORT_YSCALE_12                                                                        0x0159
5597 #define regPA_CL_VPORT_YSCALE_12_BASE_IDX                                                               1
5598 #define regPA_CL_VPORT_YOFFSET_12                                                                       0x015a
5599 #define regPA_CL_VPORT_YOFFSET_12_BASE_IDX                                                              1
5600 #define regPA_CL_VPORT_ZSCALE_12                                                                        0x015b
5601 #define regPA_CL_VPORT_ZSCALE_12_BASE_IDX                                                               1
5602 #define regPA_CL_VPORT_ZOFFSET_12                                                                       0x015c
5603 #define regPA_CL_VPORT_ZOFFSET_12_BASE_IDX                                                              1
5604 #define regPA_CL_VPORT_XSCALE_13                                                                        0x015d
5605 #define regPA_CL_VPORT_XSCALE_13_BASE_IDX                                                               1
5606 #define regPA_CL_VPORT_XOFFSET_13                                                                       0x015e
5607 #define regPA_CL_VPORT_XOFFSET_13_BASE_IDX                                                              1
5608 #define regPA_CL_VPORT_YSCALE_13                                                                        0x015f
5609 #define regPA_CL_VPORT_YSCALE_13_BASE_IDX                                                               1
5610 #define regPA_CL_VPORT_YOFFSET_13                                                                       0x0160
5611 #define regPA_CL_VPORT_YOFFSET_13_BASE_IDX                                                              1
5612 #define regPA_CL_VPORT_ZSCALE_13                                                                        0x0161
5613 #define regPA_CL_VPORT_ZSCALE_13_BASE_IDX                                                               1
5614 #define regPA_CL_VPORT_ZOFFSET_13                                                                       0x0162
5615 #define regPA_CL_VPORT_ZOFFSET_13_BASE_IDX                                                              1
5616 #define regPA_CL_VPORT_XSCALE_14                                                                        0x0163
5617 #define regPA_CL_VPORT_XSCALE_14_BASE_IDX                                                               1
5618 #define regPA_CL_VPORT_XOFFSET_14                                                                       0x0164
5619 #define regPA_CL_VPORT_XOFFSET_14_BASE_IDX                                                              1
5620 #define regPA_CL_VPORT_YSCALE_14                                                                        0x0165
5621 #define regPA_CL_VPORT_YSCALE_14_BASE_IDX                                                               1
5622 #define regPA_CL_VPORT_YOFFSET_14                                                                       0x0166
5623 #define regPA_CL_VPORT_YOFFSET_14_BASE_IDX                                                              1
5624 #define regPA_CL_VPORT_ZSCALE_14                                                                        0x0167
5625 #define regPA_CL_VPORT_ZSCALE_14_BASE_IDX                                                               1
5626 #define regPA_CL_VPORT_ZOFFSET_14                                                                       0x0168
5627 #define regPA_CL_VPORT_ZOFFSET_14_BASE_IDX                                                              1
5628 #define regPA_CL_VPORT_XSCALE_15                                                                        0x0169
5629 #define regPA_CL_VPORT_XSCALE_15_BASE_IDX                                                               1
5630 #define regPA_CL_VPORT_XOFFSET_15                                                                       0x016a
5631 #define regPA_CL_VPORT_XOFFSET_15_BASE_IDX                                                              1
5632 #define regPA_CL_VPORT_YSCALE_15                                                                        0x016b
5633 #define regPA_CL_VPORT_YSCALE_15_BASE_IDX                                                               1
5634 #define regPA_CL_VPORT_YOFFSET_15                                                                       0x016c
5635 #define regPA_CL_VPORT_YOFFSET_15_BASE_IDX                                                              1
5636 #define regPA_CL_VPORT_ZSCALE_15                                                                        0x016d
5637 #define regPA_CL_VPORT_ZSCALE_15_BASE_IDX                                                               1
5638 #define regPA_CL_VPORT_ZOFFSET_15                                                                       0x016e
5639 #define regPA_CL_VPORT_ZOFFSET_15_BASE_IDX                                                              1
5640 #define regPA_CL_UCP_0_X                                                                                0x016f
5641 #define regPA_CL_UCP_0_X_BASE_IDX                                                                       1
5642 #define regPA_CL_UCP_0_Y                                                                                0x0170
5643 #define regPA_CL_UCP_0_Y_BASE_IDX                                                                       1
5644 #define regPA_CL_UCP_0_Z                                                                                0x0171
5645 #define regPA_CL_UCP_0_Z_BASE_IDX                                                                       1
5646 #define regPA_CL_UCP_0_W                                                                                0x0172
5647 #define regPA_CL_UCP_0_W_BASE_IDX                                                                       1
5648 #define regPA_CL_UCP_1_X                                                                                0x0173
5649 #define regPA_CL_UCP_1_X_BASE_IDX                                                                       1
5650 #define regPA_CL_UCP_1_Y                                                                                0x0174
5651 #define regPA_CL_UCP_1_Y_BASE_IDX                                                                       1
5652 #define regPA_CL_UCP_1_Z                                                                                0x0175
5653 #define regPA_CL_UCP_1_Z_BASE_IDX                                                                       1
5654 #define regPA_CL_UCP_1_W                                                                                0x0176
5655 #define regPA_CL_UCP_1_W_BASE_IDX                                                                       1
5656 #define regPA_CL_UCP_2_X                                                                                0x0177
5657 #define regPA_CL_UCP_2_X_BASE_IDX                                                                       1
5658 #define regPA_CL_UCP_2_Y                                                                                0x0178
5659 #define regPA_CL_UCP_2_Y_BASE_IDX                                                                       1
5660 #define regPA_CL_UCP_2_Z                                                                                0x0179
5661 #define regPA_CL_UCP_2_Z_BASE_IDX                                                                       1
5662 #define regPA_CL_UCP_2_W                                                                                0x017a
5663 #define regPA_CL_UCP_2_W_BASE_IDX                                                                       1
5664 #define regPA_CL_UCP_3_X                                                                                0x017b
5665 #define regPA_CL_UCP_3_X_BASE_IDX                                                                       1
5666 #define regPA_CL_UCP_3_Y                                                                                0x017c
5667 #define regPA_CL_UCP_3_Y_BASE_IDX                                                                       1
5668 #define regPA_CL_UCP_3_Z                                                                                0x017d
5669 #define regPA_CL_UCP_3_Z_BASE_IDX                                                                       1
5670 #define regPA_CL_UCP_3_W                                                                                0x017e
5671 #define regPA_CL_UCP_3_W_BASE_IDX                                                                       1
5672 #define regPA_CL_UCP_4_X                                                                                0x017f
5673 #define regPA_CL_UCP_4_X_BASE_IDX                                                                       1
5674 #define regPA_CL_UCP_4_Y                                                                                0x0180
5675 #define regPA_CL_UCP_4_Y_BASE_IDX                                                                       1
5676 #define regPA_CL_UCP_4_Z                                                                                0x0181
5677 #define regPA_CL_UCP_4_Z_BASE_IDX                                                                       1
5678 #define regPA_CL_UCP_4_W                                                                                0x0182
5679 #define regPA_CL_UCP_4_W_BASE_IDX                                                                       1
5680 #define regPA_CL_UCP_5_X                                                                                0x0183
5681 #define regPA_CL_UCP_5_X_BASE_IDX                                                                       1
5682 #define regPA_CL_UCP_5_Y                                                                                0x0184
5683 #define regPA_CL_UCP_5_Y_BASE_IDX                                                                       1
5684 #define regPA_CL_UCP_5_Z                                                                                0x0185
5685 #define regPA_CL_UCP_5_Z_BASE_IDX                                                                       1
5686 #define regPA_CL_UCP_5_W                                                                                0x0186
5687 #define regPA_CL_UCP_5_W_BASE_IDX                                                                       1
5688 #define regPA_CL_PROG_NEAR_CLIP_Z                                                                       0x0187
5689 #define regPA_CL_PROG_NEAR_CLIP_Z_BASE_IDX                                                              1
5690 #define regPA_RATE_CNTL                                                                                 0x0188
5691 #define regPA_RATE_CNTL_BASE_IDX                                                                        1
5692 #define regSPI_PS_INPUT_CNTL_0                                                                          0x0191
5693 #define regSPI_PS_INPUT_CNTL_0_BASE_IDX                                                                 1
5694 #define regSPI_PS_INPUT_CNTL_1                                                                          0x0192
5695 #define regSPI_PS_INPUT_CNTL_1_BASE_IDX                                                                 1
5696 #define regSPI_PS_INPUT_CNTL_2                                                                          0x0193
5697 #define regSPI_PS_INPUT_CNTL_2_BASE_IDX                                                                 1
5698 #define regSPI_PS_INPUT_CNTL_3                                                                          0x0194
5699 #define regSPI_PS_INPUT_CNTL_3_BASE_IDX                                                                 1
5700 #define regSPI_PS_INPUT_CNTL_4                                                                          0x0195
5701 #define regSPI_PS_INPUT_CNTL_4_BASE_IDX                                                                 1
5702 #define regSPI_PS_INPUT_CNTL_5                                                                          0x0196
5703 #define regSPI_PS_INPUT_CNTL_5_BASE_IDX                                                                 1
5704 #define regSPI_PS_INPUT_CNTL_6                                                                          0x0197
5705 #define regSPI_PS_INPUT_CNTL_6_BASE_IDX                                                                 1
5706 #define regSPI_PS_INPUT_CNTL_7                                                                          0x0198
5707 #define regSPI_PS_INPUT_CNTL_7_BASE_IDX                                                                 1
5708 #define regSPI_PS_INPUT_CNTL_8                                                                          0x0199
5709 #define regSPI_PS_INPUT_CNTL_8_BASE_IDX                                                                 1
5710 #define regSPI_PS_INPUT_CNTL_9                                                                          0x019a
5711 #define regSPI_PS_INPUT_CNTL_9_BASE_IDX                                                                 1
5712 #define regSPI_PS_INPUT_CNTL_10                                                                         0x019b
5713 #define regSPI_PS_INPUT_CNTL_10_BASE_IDX                                                                1
5714 #define regSPI_PS_INPUT_CNTL_11                                                                         0x019c
5715 #define regSPI_PS_INPUT_CNTL_11_BASE_IDX                                                                1
5716 #define regSPI_PS_INPUT_CNTL_12                                                                         0x019d
5717 #define regSPI_PS_INPUT_CNTL_12_BASE_IDX                                                                1
5718 #define regSPI_PS_INPUT_CNTL_13                                                                         0x019e
5719 #define regSPI_PS_INPUT_CNTL_13_BASE_IDX                                                                1
5720 #define regSPI_PS_INPUT_CNTL_14                                                                         0x019f
5721 #define regSPI_PS_INPUT_CNTL_14_BASE_IDX                                                                1
5722 #define regSPI_PS_INPUT_CNTL_15                                                                         0x01a0
5723 #define regSPI_PS_INPUT_CNTL_15_BASE_IDX                                                                1
5724 #define regSPI_PS_INPUT_CNTL_16                                                                         0x01a1
5725 #define regSPI_PS_INPUT_CNTL_16_BASE_IDX                                                                1
5726 #define regSPI_PS_INPUT_CNTL_17                                                                         0x01a2
5727 #define regSPI_PS_INPUT_CNTL_17_BASE_IDX                                                                1
5728 #define regSPI_PS_INPUT_CNTL_18                                                                         0x01a3
5729 #define regSPI_PS_INPUT_CNTL_18_BASE_IDX                                                                1
5730 #define regSPI_PS_INPUT_CNTL_19                                                                         0x01a4
5731 #define regSPI_PS_INPUT_CNTL_19_BASE_IDX                                                                1
5732 #define regSPI_PS_INPUT_CNTL_20                                                                         0x01a5
5733 #define regSPI_PS_INPUT_CNTL_20_BASE_IDX                                                                1
5734 #define regSPI_PS_INPUT_CNTL_21                                                                         0x01a6
5735 #define regSPI_PS_INPUT_CNTL_21_BASE_IDX                                                                1
5736 #define regSPI_PS_INPUT_CNTL_22                                                                         0x01a7
5737 #define regSPI_PS_INPUT_CNTL_22_BASE_IDX                                                                1
5738 #define regSPI_PS_INPUT_CNTL_23                                                                         0x01a8
5739 #define regSPI_PS_INPUT_CNTL_23_BASE_IDX                                                                1
5740 #define regSPI_PS_INPUT_CNTL_24                                                                         0x01a9
5741 #define regSPI_PS_INPUT_CNTL_24_BASE_IDX                                                                1
5742 #define regSPI_PS_INPUT_CNTL_25                                                                         0x01aa
5743 #define regSPI_PS_INPUT_CNTL_25_BASE_IDX                                                                1
5744 #define regSPI_PS_INPUT_CNTL_26                                                                         0x01ab
5745 #define regSPI_PS_INPUT_CNTL_26_BASE_IDX                                                                1
5746 #define regSPI_PS_INPUT_CNTL_27                                                                         0x01ac
5747 #define regSPI_PS_INPUT_CNTL_27_BASE_IDX                                                                1
5748 #define regSPI_PS_INPUT_CNTL_28                                                                         0x01ad
5749 #define regSPI_PS_INPUT_CNTL_28_BASE_IDX                                                                1
5750 #define regSPI_PS_INPUT_CNTL_29                                                                         0x01ae
5751 #define regSPI_PS_INPUT_CNTL_29_BASE_IDX                                                                1
5752 #define regSPI_PS_INPUT_CNTL_30                                                                         0x01af
5753 #define regSPI_PS_INPUT_CNTL_30_BASE_IDX                                                                1
5754 #define regSPI_PS_INPUT_CNTL_31                                                                         0x01b0
5755 #define regSPI_PS_INPUT_CNTL_31_BASE_IDX                                                                1
5756 #define regSPI_VS_OUT_CONFIG                                                                            0x01b1
5757 #define regSPI_VS_OUT_CONFIG_BASE_IDX                                                                   1
5758 #define regSPI_PS_INPUT_ENA                                                                             0x01b3
5759 #define regSPI_PS_INPUT_ENA_BASE_IDX                                                                    1
5760 #define regSPI_PS_INPUT_ADDR                                                                            0x01b4
5761 #define regSPI_PS_INPUT_ADDR_BASE_IDX                                                                   1
5762 #define regSPI_INTERP_CONTROL_0                                                                         0x01b5
5763 #define regSPI_INTERP_CONTROL_0_BASE_IDX                                                                1
5764 #define regSPI_PS_IN_CONTROL                                                                            0x01b6
5765 #define regSPI_PS_IN_CONTROL_BASE_IDX                                                                   1
5766 #define regSPI_BARYC_CNTL                                                                               0x01b8
5767 #define regSPI_BARYC_CNTL_BASE_IDX                                                                      1
5768 #define regSPI_TMPRING_SIZE                                                                             0x01ba
5769 #define regSPI_TMPRING_SIZE_BASE_IDX                                                                    1
5770 #define regSPI_GFX_SCRATCH_BASE_LO                                                                      0x01bb
5771 #define regSPI_GFX_SCRATCH_BASE_LO_BASE_IDX                                                             1
5772 #define regSPI_GFX_SCRATCH_BASE_HI                                                                      0x01bc
5773 #define regSPI_GFX_SCRATCH_BASE_HI_BASE_IDX                                                             1
5774 #define regSPI_SHADER_IDX_FORMAT                                                                        0x01c2
5775 #define regSPI_SHADER_IDX_FORMAT_BASE_IDX                                                               1
5776 #define regSPI_SHADER_POS_FORMAT                                                                        0x01c3
5777 #define regSPI_SHADER_POS_FORMAT_BASE_IDX                                                               1
5778 #define regSPI_SHADER_Z_FORMAT                                                                          0x01c4
5779 #define regSPI_SHADER_Z_FORMAT_BASE_IDX                                                                 1
5780 #define regSPI_SHADER_COL_FORMAT                                                                        0x01c5
5781 #define regSPI_SHADER_COL_FORMAT_BASE_IDX                                                               1
5782 #define regSX_PS_DOWNCONVERT_CONTROL                                                                    0x01d4
5783 #define regSX_PS_DOWNCONVERT_CONTROL_BASE_IDX                                                           1
5784 #define regSX_PS_DOWNCONVERT                                                                            0x01d5
5785 #define regSX_PS_DOWNCONVERT_BASE_IDX                                                                   1
5786 #define regSX_BLEND_OPT_EPSILON                                                                         0x01d6
5787 #define regSX_BLEND_OPT_EPSILON_BASE_IDX                                                                1
5788 #define regSX_BLEND_OPT_CONTROL                                                                         0x01d7
5789 #define regSX_BLEND_OPT_CONTROL_BASE_IDX                                                                1
5790 #define regSX_MRT0_BLEND_OPT                                                                            0x01d8
5791 #define regSX_MRT0_BLEND_OPT_BASE_IDX                                                                   1
5792 #define regSX_MRT1_BLEND_OPT                                                                            0x01d9
5793 #define regSX_MRT1_BLEND_OPT_BASE_IDX                                                                   1
5794 #define regSX_MRT2_BLEND_OPT                                                                            0x01da
5795 #define regSX_MRT2_BLEND_OPT_BASE_IDX                                                                   1
5796 #define regSX_MRT3_BLEND_OPT                                                                            0x01db
5797 #define regSX_MRT3_BLEND_OPT_BASE_IDX                                                                   1
5798 #define regSX_MRT4_BLEND_OPT                                                                            0x01dc
5799 #define regSX_MRT4_BLEND_OPT_BASE_IDX                                                                   1
5800 #define regSX_MRT5_BLEND_OPT                                                                            0x01dd
5801 #define regSX_MRT5_BLEND_OPT_BASE_IDX                                                                   1
5802 #define regSX_MRT6_BLEND_OPT                                                                            0x01de
5803 #define regSX_MRT6_BLEND_OPT_BASE_IDX                                                                   1
5804 #define regSX_MRT7_BLEND_OPT                                                                            0x01df
5805 #define regSX_MRT7_BLEND_OPT_BASE_IDX                                                                   1
5806 #define regCB_BLEND0_CONTROL                                                                            0x01e0
5807 #define regCB_BLEND0_CONTROL_BASE_IDX                                                                   1
5808 #define regCB_BLEND1_CONTROL                                                                            0x01e1
5809 #define regCB_BLEND1_CONTROL_BASE_IDX                                                                   1
5810 #define regCB_BLEND2_CONTROL                                                                            0x01e2
5811 #define regCB_BLEND2_CONTROL_BASE_IDX                                                                   1
5812 #define regCB_BLEND3_CONTROL                                                                            0x01e3
5813 #define regCB_BLEND3_CONTROL_BASE_IDX                                                                   1
5814 #define regCB_BLEND4_CONTROL                                                                            0x01e4
5815 #define regCB_BLEND4_CONTROL_BASE_IDX                                                                   1
5816 #define regCB_BLEND5_CONTROL                                                                            0x01e5
5817 #define regCB_BLEND5_CONTROL_BASE_IDX                                                                   1
5818 #define regCB_BLEND6_CONTROL                                                                            0x01e6
5819 #define regCB_BLEND6_CONTROL_BASE_IDX                                                                   1
5820 #define regCB_BLEND7_CONTROL                                                                            0x01e7
5821 #define regCB_BLEND7_CONTROL_BASE_IDX                                                                   1
5822 #define regGFX_COPY_STATE                                                                               0x01f4
5823 #define regGFX_COPY_STATE_BASE_IDX                                                                      1
5824 #define regPA_CL_POINT_X_RAD                                                                            0x01f5
5825 #define regPA_CL_POINT_X_RAD_BASE_IDX                                                                   1
5826 #define regPA_CL_POINT_Y_RAD                                                                            0x01f6
5827 #define regPA_CL_POINT_Y_RAD_BASE_IDX                                                                   1
5828 #define regPA_CL_POINT_SIZE                                                                             0x01f7
5829 #define regPA_CL_POINT_SIZE_BASE_IDX                                                                    1
5830 #define regPA_CL_POINT_CULL_RAD                                                                         0x01f8
5831 #define regPA_CL_POINT_CULL_RAD_BASE_IDX                                                                1
5832 #define regVGT_DMA_BASE_HI                                                                              0x01f9
5833 #define regVGT_DMA_BASE_HI_BASE_IDX                                                                     1
5834 #define regVGT_DMA_BASE                                                                                 0x01fa
5835 #define regVGT_DMA_BASE_BASE_IDX                                                                        1
5836 #define regVGT_DRAW_INITIATOR                                                                           0x01fc
5837 #define regVGT_DRAW_INITIATOR_BASE_IDX                                                                  1
5838 #define regVGT_EVENT_ADDRESS_REG                                                                        0x01fe
5839 #define regVGT_EVENT_ADDRESS_REG_BASE_IDX                                                               1
5840 #define regGE_MAX_OUTPUT_PER_SUBGROUP                                                                   0x01ff
5841 #define regGE_MAX_OUTPUT_PER_SUBGROUP_BASE_IDX                                                          1
5842 #define regDB_DEPTH_CONTROL                                                                             0x0200
5843 #define regDB_DEPTH_CONTROL_BASE_IDX                                                                    1
5844 #define regDB_EQAA                                                                                      0x0201
5845 #define regDB_EQAA_BASE_IDX                                                                             1
5846 #define regCB_COLOR_CONTROL                                                                             0x0202
5847 #define regCB_COLOR_CONTROL_BASE_IDX                                                                    1
5848 #define regDB_SHADER_CONTROL                                                                            0x0203
5849 #define regDB_SHADER_CONTROL_BASE_IDX                                                                   1
5850 #define regPA_CL_CLIP_CNTL                                                                              0x0204
5851 #define regPA_CL_CLIP_CNTL_BASE_IDX                                                                     1
5852 #define regPA_SU_SC_MODE_CNTL                                                                           0x0205
5853 #define regPA_SU_SC_MODE_CNTL_BASE_IDX                                                                  1
5854 #define regPA_CL_VTE_CNTL                                                                               0x0206
5855 #define regPA_CL_VTE_CNTL_BASE_IDX                                                                      1
5856 #define regPA_CL_VS_OUT_CNTL                                                                            0x0207
5857 #define regPA_CL_VS_OUT_CNTL_BASE_IDX                                                                   1
5858 #define regPA_CL_NANINF_CNTL                                                                            0x0208
5859 #define regPA_CL_NANINF_CNTL_BASE_IDX                                                                   1
5860 #define regPA_SU_LINE_STIPPLE_CNTL                                                                      0x0209
5861 #define regPA_SU_LINE_STIPPLE_CNTL_BASE_IDX                                                             1
5862 #define regPA_SU_LINE_STIPPLE_SCALE                                                                     0x020a
5863 #define regPA_SU_LINE_STIPPLE_SCALE_BASE_IDX                                                            1
5864 #define regPA_SU_PRIM_FILTER_CNTL                                                                       0x020b
5865 #define regPA_SU_PRIM_FILTER_CNTL_BASE_IDX                                                              1
5866 #define regPA_SU_SMALL_PRIM_FILTER_CNTL                                                                 0x020c
5867 #define regPA_SU_SMALL_PRIM_FILTER_CNTL_BASE_IDX                                                        1
5868 #define regPA_CL_NGG_CNTL                                                                               0x020e
5869 #define regPA_CL_NGG_CNTL_BASE_IDX                                                                      1
5870 #define regPA_SU_OVER_RASTERIZATION_CNTL                                                                0x020f
5871 #define regPA_SU_OVER_RASTERIZATION_CNTL_BASE_IDX                                                       1
5872 #define regPA_STEREO_CNTL                                                                               0x0210
5873 #define regPA_STEREO_CNTL_BASE_IDX                                                                      1
5874 #define regPA_STATE_STEREO_X                                                                            0x0211
5875 #define regPA_STATE_STEREO_X_BASE_IDX                                                                   1
5876 #define regPA_CL_VRS_CNTL                                                                               0x0212
5877 #define regPA_CL_VRS_CNTL_BASE_IDX                                                                      1
5878 #define regPA_SU_POINT_SIZE                                                                             0x0280
5879 #define regPA_SU_POINT_SIZE_BASE_IDX                                                                    1
5880 #define regPA_SU_POINT_MINMAX                                                                           0x0281
5881 #define regPA_SU_POINT_MINMAX_BASE_IDX                                                                  1
5882 #define regPA_SU_LINE_CNTL                                                                              0x0282
5883 #define regPA_SU_LINE_CNTL_BASE_IDX                                                                     1
5884 #define regPA_SC_LINE_STIPPLE                                                                           0x0283
5885 #define regPA_SC_LINE_STIPPLE_BASE_IDX                                                                  1
5886 #define regVGT_HOS_MAX_TESS_LEVEL                                                                       0x0286
5887 #define regVGT_HOS_MAX_TESS_LEVEL_BASE_IDX                                                              1
5888 #define regVGT_HOS_MIN_TESS_LEVEL                                                                       0x0287
5889 #define regVGT_HOS_MIN_TESS_LEVEL_BASE_IDX                                                              1
5890 #define regPA_SC_MODE_CNTL_0                                                                            0x0292
5891 #define regPA_SC_MODE_CNTL_0_BASE_IDX                                                                   1
5892 #define regPA_SC_MODE_CNTL_1                                                                            0x0293
5893 #define regPA_SC_MODE_CNTL_1_BASE_IDX                                                                   1
5894 #define regVGT_ENHANCE                                                                                  0x0294
5895 #define regVGT_ENHANCE_BASE_IDX                                                                         1
5896 #define regIA_ENHANCE                                                                                   0x029c
5897 #define regIA_ENHANCE_BASE_IDX                                                                          1
5898 #define regVGT_DMA_SIZE                                                                                 0x029d
5899 #define regVGT_DMA_SIZE_BASE_IDX                                                                        1
5900 #define regVGT_DMA_MAX_SIZE                                                                             0x029e
5901 #define regVGT_DMA_MAX_SIZE_BASE_IDX                                                                    1
5902 #define regVGT_DMA_INDEX_TYPE                                                                           0x029f
5903 #define regVGT_DMA_INDEX_TYPE_BASE_IDX                                                                  1
5904 #define regWD_ENHANCE                                                                                   0x02a0
5905 #define regWD_ENHANCE_BASE_IDX                                                                          1
5906 #define regVGT_PRIMITIVEID_EN                                                                           0x02a1
5907 #define regVGT_PRIMITIVEID_EN_BASE_IDX                                                                  1
5908 #define regVGT_DMA_NUM_INSTANCES                                                                        0x02a2
5909 #define regVGT_DMA_NUM_INSTANCES_BASE_IDX                                                               1
5910 #define regVGT_PRIMITIVEID_RESET                                                                        0x02a3
5911 #define regVGT_PRIMITIVEID_RESET_BASE_IDX                                                               1
5912 #define regVGT_EVENT_INITIATOR                                                                          0x02a4
5913 #define regVGT_EVENT_INITIATOR_BASE_IDX                                                                 1
5914 #define regVGT_DRAW_PAYLOAD_CNTL                                                                        0x02a6
5915 #define regVGT_DRAW_PAYLOAD_CNTL_BASE_IDX                                                               1
5916 #define regVGT_ESGS_RING_ITEMSIZE                                                                       0x02ab
5917 #define regVGT_ESGS_RING_ITEMSIZE_BASE_IDX                                                              1
5918 #define regVGT_REUSE_OFF                                                                                0x02ad
5919 #define regVGT_REUSE_OFF_BASE_IDX                                                                       1
5920 #define regDB_HTILE_SURFACE                                                                             0x02af
5921 #define regDB_HTILE_SURFACE_BASE_IDX                                                                    1
5922 #define regDB_SRESULTS_COMPARE_STATE0                                                                   0x02b0
5923 #define regDB_SRESULTS_COMPARE_STATE0_BASE_IDX                                                          1
5924 #define regDB_SRESULTS_COMPARE_STATE1                                                                   0x02b1
5925 #define regDB_SRESULTS_COMPARE_STATE1_BASE_IDX                                                          1
5926 #define regDB_PRELOAD_CONTROL                                                                           0x02b2
5927 #define regDB_PRELOAD_CONTROL_BASE_IDX                                                                  1
5928 #define regVGT_STRMOUT_DRAW_OPAQUE_OFFSET                                                               0x02ca
5929 #define regVGT_STRMOUT_DRAW_OPAQUE_OFFSET_BASE_IDX                                                      1
5930 #define regVGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE                                                   0x02cb
5931 #define regVGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE_BASE_IDX                                          1
5932 #define regVGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE                                                        0x02cc
5933 #define regVGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE_BASE_IDX                                               1
5934 #define regVGT_GS_MAX_VERT_OUT                                                                          0x02ce
5935 #define regVGT_GS_MAX_VERT_OUT_BASE_IDX                                                                 1
5936 #define regGE_NGG_SUBGRP_CNTL                                                                           0x02d3
5937 #define regGE_NGG_SUBGRP_CNTL_BASE_IDX                                                                  1
5938 #define regVGT_TESS_DISTRIBUTION                                                                        0x02d4
5939 #define regVGT_TESS_DISTRIBUTION_BASE_IDX                                                               1
5940 #define regVGT_SHADER_STAGES_EN                                                                         0x02d5
5941 #define regVGT_SHADER_STAGES_EN_BASE_IDX                                                                1
5942 #define regVGT_LS_HS_CONFIG                                                                             0x02d6
5943 #define regVGT_LS_HS_CONFIG_BASE_IDX                                                                    1
5944 #define regVGT_TF_PARAM                                                                                 0x02db
5945 #define regVGT_TF_PARAM_BASE_IDX                                                                        1
5946 #define regDB_ALPHA_TO_MASK                                                                             0x02dc
5947 #define regDB_ALPHA_TO_MASK_BASE_IDX                                                                    1
5948 #define regPA_SU_POLY_OFFSET_DB_FMT_CNTL                                                                0x02de
5949 #define regPA_SU_POLY_OFFSET_DB_FMT_CNTL_BASE_IDX                                                       1
5950 #define regPA_SU_POLY_OFFSET_CLAMP                                                                      0x02df
5951 #define regPA_SU_POLY_OFFSET_CLAMP_BASE_IDX                                                             1
5952 #define regPA_SU_POLY_OFFSET_FRONT_SCALE                                                                0x02e0
5953 #define regPA_SU_POLY_OFFSET_FRONT_SCALE_BASE_IDX                                                       1
5954 #define regPA_SU_POLY_OFFSET_FRONT_OFFSET                                                               0x02e1
5955 #define regPA_SU_POLY_OFFSET_FRONT_OFFSET_BASE_IDX                                                      1
5956 #define regPA_SU_POLY_OFFSET_BACK_SCALE                                                                 0x02e2
5957 #define regPA_SU_POLY_OFFSET_BACK_SCALE_BASE_IDX                                                        1
5958 #define regPA_SU_POLY_OFFSET_BACK_OFFSET                                                                0x02e3
5959 #define regPA_SU_POLY_OFFSET_BACK_OFFSET_BASE_IDX                                                       1
5960 #define regVGT_GS_INSTANCE_CNT                                                                          0x02e4
5961 #define regVGT_GS_INSTANCE_CNT_BASE_IDX                                                                 1
5962 #define regPA_SC_CENTROID_PRIORITY_0                                                                    0x02f5
5963 #define regPA_SC_CENTROID_PRIORITY_0_BASE_IDX                                                           1
5964 #define regPA_SC_CENTROID_PRIORITY_1                                                                    0x02f6
5965 #define regPA_SC_CENTROID_PRIORITY_1_BASE_IDX                                                           1
5966 #define regPA_SC_LINE_CNTL                                                                              0x02f7
5967 #define regPA_SC_LINE_CNTL_BASE_IDX                                                                     1
5968 #define regPA_SC_AA_CONFIG                                                                              0x02f8
5969 #define regPA_SC_AA_CONFIG_BASE_IDX                                                                     1
5970 #define regPA_SU_VTX_CNTL                                                                               0x02f9
5971 #define regPA_SU_VTX_CNTL_BASE_IDX                                                                      1
5972 #define regPA_CL_GB_VERT_CLIP_ADJ                                                                       0x02fa
5973 #define regPA_CL_GB_VERT_CLIP_ADJ_BASE_IDX                                                              1
5974 #define regPA_CL_GB_VERT_DISC_ADJ                                                                       0x02fb
5975 #define regPA_CL_GB_VERT_DISC_ADJ_BASE_IDX                                                              1
5976 #define regPA_CL_GB_HORZ_CLIP_ADJ                                                                       0x02fc
5977 #define regPA_CL_GB_HORZ_CLIP_ADJ_BASE_IDX                                                              1
5978 #define regPA_CL_GB_HORZ_DISC_ADJ                                                                       0x02fd
5979 #define regPA_CL_GB_HORZ_DISC_ADJ_BASE_IDX                                                              1
5980 #define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0                                                            0x02fe
5981 #define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0_BASE_IDX                                                   1
5982 #define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1                                                            0x02ff
5983 #define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1_BASE_IDX                                                   1
5984 #define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2                                                            0x0300
5985 #define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2_BASE_IDX                                                   1
5986 #define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3                                                            0x0301
5987 #define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3_BASE_IDX                                                   1
5988 #define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0                                                            0x0302
5989 #define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0_BASE_IDX                                                   1
5990 #define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1                                                            0x0303
5991 #define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1_BASE_IDX                                                   1
5992 #define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2                                                            0x0304
5993 #define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2_BASE_IDX                                                   1
5994 #define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3                                                            0x0305
5995 #define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3_BASE_IDX                                                   1
5996 #define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0                                                            0x0306
5997 #define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0_BASE_IDX                                                   1
5998 #define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1                                                            0x0307
5999 #define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1_BASE_IDX                                                   1
6000 #define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2                                                            0x0308
6001 #define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2_BASE_IDX                                                   1
6002 #define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3                                                            0x0309
6003 #define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3_BASE_IDX                                                   1
6004 #define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0                                                            0x030a
6005 #define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0_BASE_IDX                                                   1
6006 #define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1                                                            0x030b
6007 #define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1_BASE_IDX                                                   1
6008 #define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2                                                            0x030c
6009 #define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2_BASE_IDX                                                   1
6010 #define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3                                                            0x030d
6011 #define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3_BASE_IDX                                                   1
6012 #define regPA_SC_AA_MASK_X0Y0_X1Y0                                                                      0x030e
6013 #define regPA_SC_AA_MASK_X0Y0_X1Y0_BASE_IDX                                                             1
6014 #define regPA_SC_AA_MASK_X0Y1_X1Y1                                                                      0x030f
6015 #define regPA_SC_AA_MASK_X0Y1_X1Y1_BASE_IDX                                                             1
6016 #define regPA_SC_SHADER_CONTROL                                                                         0x0310
6017 #define regPA_SC_SHADER_CONTROL_BASE_IDX                                                                1
6018 #define regPA_SC_BINNER_CNTL_0                                                                          0x0311
6019 #define regPA_SC_BINNER_CNTL_0_BASE_IDX                                                                 1
6020 #define regPA_SC_BINNER_CNTL_1                                                                          0x0312
6021 #define regPA_SC_BINNER_CNTL_1_BASE_IDX                                                                 1
6022 #define regPA_SC_CONSERVATIVE_RASTERIZATION_CNTL                                                        0x0313
6023 #define regPA_SC_CONSERVATIVE_RASTERIZATION_CNTL_BASE_IDX                                               1
6024 #define regPA_SC_NGG_MODE_CNTL                                                                          0x0314
6025 #define regPA_SC_NGG_MODE_CNTL_BASE_IDX                                                                 1
6026 #define regPA_SC_BINNER_CNTL_2                                                                          0x0315
6027 #define regPA_SC_BINNER_CNTL_2_BASE_IDX                                                                 1
6028 #define regCB_COLOR0_BASE                                                                               0x0318
6029 #define regCB_COLOR0_BASE_BASE_IDX                                                                      1
6030 #define regCB_COLOR0_VIEW                                                                               0x031b
6031 #define regCB_COLOR0_VIEW_BASE_IDX                                                                      1
6032 #define regCB_COLOR0_INFO                                                                               0x031c
6033 #define regCB_COLOR0_INFO_BASE_IDX                                                                      1
6034 #define regCB_COLOR0_ATTRIB                                                                             0x031d
6035 #define regCB_COLOR0_ATTRIB_BASE_IDX                                                                    1
6036 #define regCB_COLOR0_FDCC_CONTROL                                                                       0x031e
6037 #define regCB_COLOR0_FDCC_CONTROL_BASE_IDX                                                              1
6038 #define regCB_COLOR0_DCC_BASE                                                                           0x0325
6039 #define regCB_COLOR0_DCC_BASE_BASE_IDX                                                                  1
6040 #define regCB_COLOR1_BASE                                                                               0x0327
6041 #define regCB_COLOR1_BASE_BASE_IDX                                                                      1
6042 #define regCB_COLOR1_VIEW                                                                               0x032a
6043 #define regCB_COLOR1_VIEW_BASE_IDX                                                                      1
6044 #define regCB_COLOR1_INFO                                                                               0x032b
6045 #define regCB_COLOR1_INFO_BASE_IDX                                                                      1
6046 #define regCB_COLOR1_ATTRIB                                                                             0x032c
6047 #define regCB_COLOR1_ATTRIB_BASE_IDX                                                                    1
6048 #define regCB_COLOR1_FDCC_CONTROL                                                                       0x032d
6049 #define regCB_COLOR1_FDCC_CONTROL_BASE_IDX                                                              1
6050 #define regCB_COLOR1_DCC_BASE                                                                           0x0334
6051 #define regCB_COLOR1_DCC_BASE_BASE_IDX                                                                  1
6052 #define regCB_COLOR2_BASE                                                                               0x0336
6053 #define regCB_COLOR2_BASE_BASE_IDX                                                                      1
6054 #define regCB_COLOR2_VIEW                                                                               0x0339
6055 #define regCB_COLOR2_VIEW_BASE_IDX                                                                      1
6056 #define regCB_COLOR2_INFO                                                                               0x033a
6057 #define regCB_COLOR2_INFO_BASE_IDX                                                                      1
6058 #define regCB_COLOR2_ATTRIB                                                                             0x033b
6059 #define regCB_COLOR2_ATTRIB_BASE_IDX                                                                    1
6060 #define regCB_COLOR2_FDCC_CONTROL                                                                       0x033c
6061 #define regCB_COLOR2_FDCC_CONTROL_BASE_IDX                                                              1
6062 #define regCB_COLOR2_DCC_BASE                                                                           0x0343
6063 #define regCB_COLOR2_DCC_BASE_BASE_IDX                                                                  1
6064 #define regCB_COLOR3_BASE                                                                               0x0345
6065 #define regCB_COLOR3_BASE_BASE_IDX                                                                      1
6066 #define regCB_COLOR3_VIEW                                                                               0x0348
6067 #define regCB_COLOR3_VIEW_BASE_IDX                                                                      1
6068 #define regCB_COLOR3_INFO                                                                               0x0349
6069 #define regCB_COLOR3_INFO_BASE_IDX                                                                      1
6070 #define regCB_COLOR3_ATTRIB                                                                             0x034a
6071 #define regCB_COLOR3_ATTRIB_BASE_IDX                                                                    1
6072 #define regCB_COLOR3_FDCC_CONTROL                                                                       0x034b
6073 #define regCB_COLOR3_FDCC_CONTROL_BASE_IDX                                                              1
6074 #define regCB_COLOR3_DCC_BASE                                                                           0x0352
6075 #define regCB_COLOR3_DCC_BASE_BASE_IDX                                                                  1
6076 #define regCB_COLOR4_BASE                                                                               0x0354
6077 #define regCB_COLOR4_BASE_BASE_IDX                                                                      1
6078 #define regCB_COLOR4_VIEW                                                                               0x0357
6079 #define regCB_COLOR4_VIEW_BASE_IDX                                                                      1
6080 #define regCB_COLOR4_INFO                                                                               0x0358
6081 #define regCB_COLOR4_INFO_BASE_IDX                                                                      1
6082 #define regCB_COLOR4_ATTRIB                                                                             0x0359
6083 #define regCB_COLOR4_ATTRIB_BASE_IDX                                                                    1
6084 #define regCB_COLOR4_FDCC_CONTROL                                                                       0x035a
6085 #define regCB_COLOR4_FDCC_CONTROL_BASE_IDX                                                              1
6086 #define regCB_COLOR4_DCC_BASE                                                                           0x0361
6087 #define regCB_COLOR4_DCC_BASE_BASE_IDX                                                                  1
6088 #define regCB_COLOR5_BASE                                                                               0x0363
6089 #define regCB_COLOR5_BASE_BASE_IDX                                                                      1
6090 #define regCB_COLOR5_VIEW                                                                               0x0366
6091 #define regCB_COLOR5_VIEW_BASE_IDX                                                                      1
6092 #define regCB_COLOR5_INFO                                                                               0x0367
6093 #define regCB_COLOR5_INFO_BASE_IDX                                                                      1
6094 #define regCB_COLOR5_ATTRIB                                                                             0x0368
6095 #define regCB_COLOR5_ATTRIB_BASE_IDX                                                                    1
6096 #define regCB_COLOR5_FDCC_CONTROL                                                                       0x0369
6097 #define regCB_COLOR5_FDCC_CONTROL_BASE_IDX                                                              1
6098 #define regCB_COLOR5_DCC_BASE                                                                           0x0370
6099 #define regCB_COLOR5_DCC_BASE_BASE_IDX                                                                  1
6100 #define regCB_COLOR6_BASE                                                                               0x0372
6101 #define regCB_COLOR6_BASE_BASE_IDX                                                                      1
6102 #define regCB_COLOR6_VIEW                                                                               0x0375
6103 #define regCB_COLOR6_VIEW_BASE_IDX                                                                      1
6104 #define regCB_COLOR6_INFO                                                                               0x0376
6105 #define regCB_COLOR6_INFO_BASE_IDX                                                                      1
6106 #define regCB_COLOR6_ATTRIB                                                                             0x0377
6107 #define regCB_COLOR6_ATTRIB_BASE_IDX                                                                    1
6108 #define regCB_COLOR6_FDCC_CONTROL                                                                       0x0378
6109 #define regCB_COLOR6_FDCC_CONTROL_BASE_IDX                                                              1
6110 #define regCB_COLOR6_DCC_BASE                                                                           0x037f
6111 #define regCB_COLOR6_DCC_BASE_BASE_IDX                                                                  1
6112 #define regCB_COLOR7_BASE                                                                               0x0381
6113 #define regCB_COLOR7_BASE_BASE_IDX                                                                      1
6114 #define regCB_COLOR7_VIEW                                                                               0x0384
6115 #define regCB_COLOR7_VIEW_BASE_IDX                                                                      1
6116 #define regCB_COLOR7_INFO                                                                               0x0385
6117 #define regCB_COLOR7_INFO_BASE_IDX                                                                      1
6118 #define regCB_COLOR7_ATTRIB                                                                             0x0386
6119 #define regCB_COLOR7_ATTRIB_BASE_IDX                                                                    1
6120 #define regCB_COLOR7_FDCC_CONTROL                                                                       0x0387
6121 #define regCB_COLOR7_FDCC_CONTROL_BASE_IDX                                                              1
6122 #define regCB_COLOR7_DCC_BASE                                                                           0x038e
6123 #define regCB_COLOR7_DCC_BASE_BASE_IDX                                                                  1
6124 #define regCB_COLOR0_BASE_EXT                                                                           0x0390
6125 #define regCB_COLOR0_BASE_EXT_BASE_IDX                                                                  1
6126 #define regCB_COLOR1_BASE_EXT                                                                           0x0391
6127 #define regCB_COLOR1_BASE_EXT_BASE_IDX                                                                  1
6128 #define regCB_COLOR2_BASE_EXT                                                                           0x0392
6129 #define regCB_COLOR2_BASE_EXT_BASE_IDX                                                                  1
6130 #define regCB_COLOR3_BASE_EXT                                                                           0x0393
6131 #define regCB_COLOR3_BASE_EXT_BASE_IDX                                                                  1
6132 #define regCB_COLOR4_BASE_EXT                                                                           0x0394
6133 #define regCB_COLOR4_BASE_EXT_BASE_IDX                                                                  1
6134 #define regCB_COLOR5_BASE_EXT                                                                           0x0395
6135 #define regCB_COLOR5_BASE_EXT_BASE_IDX                                                                  1
6136 #define regCB_COLOR6_BASE_EXT                                                                           0x0396
6137 #define regCB_COLOR6_BASE_EXT_BASE_IDX                                                                  1
6138 #define regCB_COLOR7_BASE_EXT                                                                           0x0397
6139 #define regCB_COLOR7_BASE_EXT_BASE_IDX                                                                  1
6140 #define regCB_COLOR0_DCC_BASE_EXT                                                                       0x03a8
6141 #define regCB_COLOR0_DCC_BASE_EXT_BASE_IDX                                                              1
6142 #define regCB_COLOR1_DCC_BASE_EXT                                                                       0x03a9
6143 #define regCB_COLOR1_DCC_BASE_EXT_BASE_IDX                                                              1
6144 #define regCB_COLOR2_DCC_BASE_EXT                                                                       0x03aa
6145 #define regCB_COLOR2_DCC_BASE_EXT_BASE_IDX                                                              1
6146 #define regCB_COLOR3_DCC_BASE_EXT                                                                       0x03ab
6147 #define regCB_COLOR3_DCC_BASE_EXT_BASE_IDX                                                              1
6148 #define regCB_COLOR4_DCC_BASE_EXT                                                                       0x03ac
6149 #define regCB_COLOR4_DCC_BASE_EXT_BASE_IDX                                                              1
6150 #define regCB_COLOR5_DCC_BASE_EXT                                                                       0x03ad
6151 #define regCB_COLOR5_DCC_BASE_EXT_BASE_IDX                                                              1
6152 #define regCB_COLOR6_DCC_BASE_EXT                                                                       0x03ae
6153 #define regCB_COLOR6_DCC_BASE_EXT_BASE_IDX                                                              1
6154 #define regCB_COLOR7_DCC_BASE_EXT                                                                       0x03af
6155 #define regCB_COLOR7_DCC_BASE_EXT_BASE_IDX                                                              1
6156 #define regCB_COLOR0_ATTRIB2                                                                            0x03b0
6157 #define regCB_COLOR0_ATTRIB2_BASE_IDX                                                                   1
6158 #define regCB_COLOR1_ATTRIB2                                                                            0x03b1
6159 #define regCB_COLOR1_ATTRIB2_BASE_IDX                                                                   1
6160 #define regCB_COLOR2_ATTRIB2                                                                            0x03b2
6161 #define regCB_COLOR2_ATTRIB2_BASE_IDX                                                                   1
6162 #define regCB_COLOR3_ATTRIB2                                                                            0x03b3
6163 #define regCB_COLOR3_ATTRIB2_BASE_IDX                                                                   1
6164 #define regCB_COLOR4_ATTRIB2                                                                            0x03b4
6165 #define regCB_COLOR4_ATTRIB2_BASE_IDX                                                                   1
6166 #define regCB_COLOR5_ATTRIB2                                                                            0x03b5
6167 #define regCB_COLOR5_ATTRIB2_BASE_IDX                                                                   1
6168 #define regCB_COLOR6_ATTRIB2                                                                            0x03b6
6169 #define regCB_COLOR6_ATTRIB2_BASE_IDX                                                                   1
6170 #define regCB_COLOR7_ATTRIB2                                                                            0x03b7
6171 #define regCB_COLOR7_ATTRIB2_BASE_IDX                                                                   1
6172 #define regCB_COLOR0_ATTRIB3                                                                            0x03b8
6173 #define regCB_COLOR0_ATTRIB3_BASE_IDX                                                                   1
6174 #define regCB_COLOR1_ATTRIB3                                                                            0x03b9
6175 #define regCB_COLOR1_ATTRIB3_BASE_IDX                                                                   1
6176 #define regCB_COLOR2_ATTRIB3                                                                            0x03ba
6177 #define regCB_COLOR2_ATTRIB3_BASE_IDX                                                                   1
6178 #define regCB_COLOR3_ATTRIB3                                                                            0x03bb
6179 #define regCB_COLOR3_ATTRIB3_BASE_IDX                                                                   1
6180 #define regCB_COLOR4_ATTRIB3                                                                            0x03bc
6181 #define regCB_COLOR4_ATTRIB3_BASE_IDX                                                                   1
6182 #define regCB_COLOR5_ATTRIB3                                                                            0x03bd
6183 #define regCB_COLOR5_ATTRIB3_BASE_IDX                                                                   1
6184 #define regCB_COLOR6_ATTRIB3                                                                            0x03be
6185 #define regCB_COLOR6_ATTRIB3_BASE_IDX                                                                   1
6186 #define regCB_COLOR7_ATTRIB3                                                                            0x03bf
6187 #define regCB_COLOR7_ATTRIB3_BASE_IDX                                                                   1
6188 
6189 
6190 // addressBlock: gc_pfvf_cpdec
6191 // base address: 0x2a000
6192 #define regCONFIG_RESERVED_REG0                                                                         0x0800
6193 #define regCONFIG_RESERVED_REG0_BASE_IDX                                                                1
6194 #define regCONFIG_RESERVED_REG1                                                                         0x0801
6195 #define regCONFIG_RESERVED_REG1_BASE_IDX                                                                1
6196 #define regCP_MEC_CNTL                                                                                  0x0802
6197 #define regCP_MEC_CNTL_BASE_IDX                                                                         1
6198 #define regCP_ME_CNTL                                                                                   0x0803
6199 #define regCP_ME_CNTL_BASE_IDX                                                                          1
6200 
6201 
6202 // addressBlock: gc_pfvf_grbmdec
6203 // base address: 0x2a400
6204 #define regGRBM_GFX_CNTL                                                                                0x0900
6205 #define regGRBM_GFX_CNTL_BASE_IDX                                                                       1
6206 #define regGRBM_NOWHERE                                                                                 0x0901
6207 #define regGRBM_NOWHERE_BASE_IDX                                                                        1
6208 
6209 
6210 // addressBlock: gc_pfvf_padec
6211 // base address: 0x2a500
6212 #define regPA_SC_VRS_SURFACE_CNTL                                                                       0x0940
6213 #define regPA_SC_VRS_SURFACE_CNTL_BASE_IDX                                                              1
6214 #define regPA_SC_ENHANCE                                                                                0x0941
6215 #define regPA_SC_ENHANCE_BASE_IDX                                                                       1
6216 #define regPA_SC_ENHANCE_1                                                                              0x0942
6217 #define regPA_SC_ENHANCE_1_BASE_IDX                                                                     1
6218 #define regPA_SC_ENHANCE_2                                                                              0x0943
6219 #define regPA_SC_ENHANCE_2_BASE_IDX                                                                     1
6220 #define regPA_SC_ENHANCE_3                                                                              0x0944
6221 #define regPA_SC_ENHANCE_3_BASE_IDX                                                                     1
6222 #define regPA_SC_BINNER_CNTL_OVERRIDE                                                                   0x0946
6223 #define regPA_SC_BINNER_CNTL_OVERRIDE_BASE_IDX                                                          1
6224 #define regPA_SC_PBB_OVERRIDE_FLAG                                                                      0x0947
6225 #define regPA_SC_PBB_OVERRIDE_FLAG_BASE_IDX                                                             1
6226 #define regPA_SC_DSM_CNTL                                                                               0x0948
6227 #define regPA_SC_DSM_CNTL_BASE_IDX                                                                      1
6228 #define regPA_SC_TILE_STEERING_CREST_OVERRIDE                                                           0x0949
6229 #define regPA_SC_TILE_STEERING_CREST_OVERRIDE_BASE_IDX                                                  1
6230 #define regPA_SC_FIFO_SIZE                                                                              0x094a
6231 #define regPA_SC_FIFO_SIZE_BASE_IDX                                                                     1
6232 #define regPA_SC_IF_FIFO_SIZE                                                                           0x094b
6233 #define regPA_SC_IF_FIFO_SIZE_BASE_IDX                                                                  1
6234 #define regPA_SC_PACKER_WAVE_ID_CNTL                                                                    0x094c
6235 #define regPA_SC_PACKER_WAVE_ID_CNTL_BASE_IDX                                                           1
6236 #define regPA_SC_ATM_CNTL                                                                               0x094d
6237 #define regPA_SC_ATM_CNTL_BASE_IDX                                                                      1
6238 #define regPA_SC_PKR_WAVE_TABLE_CNTL                                                                    0x094e
6239 #define regPA_SC_PKR_WAVE_TABLE_CNTL_BASE_IDX                                                           1
6240 #define regPA_SC_FORCE_EOV_MAX_CNTS                                                                     0x094f
6241 #define regPA_SC_FORCE_EOV_MAX_CNTS_BASE_IDX                                                            1
6242 #define regPA_SC_BINNER_EVENT_CNTL_0                                                                    0x0950
6243 #define regPA_SC_BINNER_EVENT_CNTL_0_BASE_IDX                                                           1
6244 #define regPA_SC_BINNER_EVENT_CNTL_1                                                                    0x0951
6245 #define regPA_SC_BINNER_EVENT_CNTL_1_BASE_IDX                                                           1
6246 #define regPA_SC_BINNER_EVENT_CNTL_2                                                                    0x0952
6247 #define regPA_SC_BINNER_EVENT_CNTL_2_BASE_IDX                                                           1
6248 #define regPA_SC_BINNER_EVENT_CNTL_3                                                                    0x0953
6249 #define regPA_SC_BINNER_EVENT_CNTL_3_BASE_IDX                                                           1
6250 #define regPA_SC_BINNER_TIMEOUT_COUNTER                                                                 0x0954
6251 #define regPA_SC_BINNER_TIMEOUT_COUNTER_BASE_IDX                                                        1
6252 #define regPA_SC_BINNER_PERF_CNTL_0                                                                     0x0955
6253 #define regPA_SC_BINNER_PERF_CNTL_0_BASE_IDX                                                            1
6254 #define regPA_SC_BINNER_PERF_CNTL_1                                                                     0x0956
6255 #define regPA_SC_BINNER_PERF_CNTL_1_BASE_IDX                                                            1
6256 #define regPA_SC_BINNER_PERF_CNTL_2                                                                     0x0957
6257 #define regPA_SC_BINNER_PERF_CNTL_2_BASE_IDX                                                            1
6258 #define regPA_SC_BINNER_PERF_CNTL_3                                                                     0x0958
6259 #define regPA_SC_BINNER_PERF_CNTL_3_BASE_IDX                                                            1
6260 #define regPA_SC_P3D_TRAP_SCREEN_HV_LOCK                                                                0x095b
6261 #define regPA_SC_P3D_TRAP_SCREEN_HV_LOCK_BASE_IDX                                                       1
6262 #define regPA_SC_HP3D_TRAP_SCREEN_HV_LOCK                                                               0x095c
6263 #define regPA_SC_HP3D_TRAP_SCREEN_HV_LOCK_BASE_IDX                                                      1
6264 #define regPA_SC_TRAP_SCREEN_HV_LOCK                                                                    0x095d
6265 #define regPA_SC_TRAP_SCREEN_HV_LOCK_BASE_IDX                                                           1
6266 #define regPA_PH_INTERFACE_FIFO_SIZE                                                                    0x095e
6267 #define regPA_PH_INTERFACE_FIFO_SIZE_BASE_IDX                                                           1
6268 #define regPA_PH_ENHANCE                                                                                0x095f
6269 #define regPA_PH_ENHANCE_BASE_IDX                                                                       1
6270 #define regPA_SC_VRS_SURFACE_CNTL_1                                                                     0x0960
6271 #define regPA_SC_VRS_SURFACE_CNTL_1_BASE_IDX                                                            1
6272 
6273 
6274 // addressBlock: gc_pfvf_sqdec
6275 // base address: 0x2a780
6276 #define regSQ_RUNTIME_CONFIG                                                                            0x09e0
6277 #define regSQ_RUNTIME_CONFIG_BASE_IDX                                                                   1
6278 #define regSQ_DEBUG_STS_GLOBAL                                                                          0x09e1
6279 #define regSQ_DEBUG_STS_GLOBAL_BASE_IDX                                                                 1
6280 #define regSQ_DEBUG_STS_GLOBAL2                                                                         0x09e2
6281 #define regSQ_DEBUG_STS_GLOBAL2_BASE_IDX                                                                1
6282 #define regSH_MEM_BASES                                                                                 0x09e3
6283 #define regSH_MEM_BASES_BASE_IDX                                                                        1
6284 #define regSH_MEM_CONFIG                                                                                0x09e4
6285 #define regSH_MEM_CONFIG_BASE_IDX                                                                       1
6286 #define regSQ_DEBUG                                                                                     0x09e5
6287 #define regSQ_DEBUG_BASE_IDX                                                                            1
6288 #define regSQ_SHADER_TBA_LO                                                                             0x09e6
6289 #define regSQ_SHADER_TBA_LO_BASE_IDX                                                                    1
6290 #define regSQ_SHADER_TBA_HI                                                                             0x09e7
6291 #define regSQ_SHADER_TBA_HI_BASE_IDX                                                                    1
6292 #define regSQ_SHADER_TMA_LO                                                                             0x09e8
6293 #define regSQ_SHADER_TMA_LO_BASE_IDX                                                                    1
6294 #define regSQ_SHADER_TMA_HI                                                                             0x09e9
6295 #define regSQ_SHADER_TMA_HI_BASE_IDX                                                                    1
6296 
6297 
6298 // addressBlock: gc_pfonly_cpdec
6299 // base address: 0x2e000
6300 #define regCP_DEBUG_2                                                                                   0x1800
6301 #define regCP_DEBUG_2_BASE_IDX                                                                          1
6302 #define regCP_FETCHER_SOURCE                                                                            0x1801
6303 #define regCP_FETCHER_SOURCE_BASE_IDX                                                                   1
6304 
6305 
6306 // addressBlock: gc_pfonly_cpphqddec
6307 // base address: 0x2e080
6308 #define regCP_HPD_MES_ROQ_OFFSETS                                                                       0x1821
6309 #define regCP_HPD_MES_ROQ_OFFSETS_BASE_IDX                                                              1
6310 #define regCP_HPD_ROQ_OFFSETS                                                                           0x1821
6311 #define regCP_HPD_ROQ_OFFSETS_BASE_IDX                                                                  1
6312 #define regCP_HPD_STATUS0                                                                               0x1822
6313 #define regCP_HPD_STATUS0_BASE_IDX                                                                      1
6314 
6315 
6316 // addressBlock: gc_pfonly_didtdec
6317 // base address: 0x2e400
6318 #define regDIDT_INDEX_AUTO_INCR_EN                                                                      0x1900
6319 #define regDIDT_INDEX_AUTO_INCR_EN_BASE_IDX                                                             1
6320 #define regDIDT_EDC_CTRL                                                                                0x1901
6321 #define regDIDT_EDC_CTRL_BASE_IDX                                                                       1
6322 #define regDIDT_EDC_THROTTLE_CTRL                                                                       0x1902
6323 #define regDIDT_EDC_THROTTLE_CTRL_BASE_IDX                                                              1
6324 #define regDIDT_EDC_THRESHOLD                                                                           0x1903
6325 #define regDIDT_EDC_THRESHOLD_BASE_IDX                                                                  1
6326 #define regDIDT_EDC_STALL_PATTERN_1_2                                                                   0x1904
6327 #define regDIDT_EDC_STALL_PATTERN_1_2_BASE_IDX                                                          1
6328 #define regDIDT_EDC_STALL_PATTERN_3_4                                                                   0x1905
6329 #define regDIDT_EDC_STALL_PATTERN_3_4_BASE_IDX                                                          1
6330 #define regDIDT_EDC_STALL_PATTERN_5_6                                                                   0x1906
6331 #define regDIDT_EDC_STALL_PATTERN_5_6_BASE_IDX                                                          1
6332 #define regDIDT_EDC_STALL_PATTERN_7                                                                     0x1907
6333 #define regDIDT_EDC_STALL_PATTERN_7_BASE_IDX                                                            1
6334 #define regDIDT_EDC_STATUS                                                                              0x1908
6335 #define regDIDT_EDC_STATUS_BASE_IDX                                                                     1
6336 #define regDIDT_EDC_DYNAMIC_THRESHOLD_RO                                                                0x1909
6337 #define regDIDT_EDC_DYNAMIC_THRESHOLD_RO_BASE_IDX                                                       1
6338 #define regDIDT_EDC_OVERFLOW                                                                            0x190a
6339 #define regDIDT_EDC_OVERFLOW_BASE_IDX                                                                   1
6340 #define regDIDT_EDC_ROLLING_POWER_DELTA                                                                 0x190b
6341 #define regDIDT_EDC_ROLLING_POWER_DELTA_BASE_IDX                                                        1
6342 #define regDIDT_IND_INDEX                                                                               0x190c
6343 #define regDIDT_IND_INDEX_BASE_IDX                                                                      1
6344 #define regDIDT_IND_DATA                                                                                0x190d
6345 #define regDIDT_IND_DATA_BASE_IDX                                                                       1
6346 
6347 
6348 // addressBlock: gc_pfonly_spidec
6349 // base address: 0x2e500
6350 #define regSPI_GDBG_WAVE_CNTL                                                                           0x1943
6351 #define regSPI_GDBG_WAVE_CNTL_BASE_IDX                                                                  1
6352 #define regSPI_GDBG_TRAP_CONFIG                                                                         0x1944
6353 #define regSPI_GDBG_TRAP_CONFIG_BASE_IDX                                                                1
6354 #define regSPI_GDBG_WAVE_CNTL3                                                                          0x1945
6355 #define regSPI_GDBG_WAVE_CNTL3_BASE_IDX                                                                 1
6356 #define regSPI_ARB_CNTL_0                                                                               0x1949
6357 #define regSPI_ARB_CNTL_0_BASE_IDX                                                                      1
6358 #define regSPI_FEATURE_CTRL                                                                             0x194a
6359 #define regSPI_FEATURE_CTRL_BASE_IDX                                                                    1
6360 #define regSPI_SHADER_RSRC_LIMIT_CTRL                                                                   0x194b
6361 #define regSPI_SHADER_RSRC_LIMIT_CTRL_BASE_IDX                                                          1
6362 #define regSPI_COMPUTE_WF_CTX_SAVE_STATUS                                                               0x194e
6363 #define regSPI_COMPUTE_WF_CTX_SAVE_STATUS_BASE_IDX                                                      1
6364 
6365 
6366 // addressBlock: gc_pfonly_tcpdec
6367 // base address: 0x2e680
6368 #define regTCP_INVALIDATE                                                                               0x19a0
6369 #define regTCP_INVALIDATE_BASE_IDX                                                                      1
6370 #define regTCP_STATUS                                                                                   0x19a1
6371 #define regTCP_STATUS_BASE_IDX                                                                          1
6372 #define regTCP_CNTL2                                                                                    0x19a3
6373 #define regTCP_CNTL2_BASE_IDX                                                                           1
6374 #define regTCP_DEBUG_INDEX                                                                              0x19a5
6375 #define regTCP_DEBUG_INDEX_BASE_IDX                                                                     1
6376 #define regTCP_DEBUG_DATA                                                                               0x19a6
6377 #define regTCP_DEBUG_DATA_BASE_IDX                                                                      1
6378 
6379 
6380 // addressBlock: gc_pfonly_gdsdec
6381 // base address: 0x2e6c0
6382 #define regGDS_ENHANCE2                                                                                 0x19b0
6383 #define regGDS_ENHANCE2_BASE_IDX                                                                        1
6384 #define regGDS_OA_CGPG_RESTORE                                                                          0x19b1
6385 #define regGDS_OA_CGPG_RESTORE_BASE_IDX                                                                 1
6386 
6387 
6388 // addressBlock: gc_pfonly_utcl1dec
6389 // base address: 0x2e600
6390 #define regUTCL1_CTRL_0                                                                                 0x1980
6391 #define regUTCL1_CTRL_0_BASE_IDX                                                                        1
6392 #define regUTCL1_UTCL0_INVREQ_DISABLE                                                                   0x1984
6393 #define regUTCL1_UTCL0_INVREQ_DISABLE_BASE_IDX                                                          1
6394 #define regUTCL1_CTRL_2                                                                                 0x1985
6395 #define regUTCL1_CTRL_2_BASE_IDX                                                                        1
6396 #define regUTCL1_FIFO_SIZING                                                                            0x1986
6397 #define regUTCL1_FIFO_SIZING_BASE_IDX                                                                   1
6398 #define regGCRD_SA0_TARGETS_DISABLE                                                                     0x1987
6399 #define regGCRD_SA0_TARGETS_DISABLE_BASE_IDX                                                            1
6400 #define regGCRD_SA1_TARGETS_DISABLE                                                                     0x1989
6401 #define regGCRD_SA1_TARGETS_DISABLE_BASE_IDX                                                            1
6402 #define regGCRD_CREDIT_SAFE                                                                             0x198a
6403 #define regGCRD_CREDIT_SAFE_BASE_IDX                                                                    1
6404 
6405 
6406 // addressBlock: gc_pfonly_pmmdec
6407 // base address: 0x2e640
6408 #define regGCR_GENERAL_CNTL                                                                             0x1990
6409 #define regGCR_GENERAL_CNTL_BASE_IDX                                                                    1
6410 #define regGCR_CMD_STATUS                                                                               0x1992
6411 #define regGCR_CMD_STATUS_BASE_IDX                                                                      1
6412 #define regGCR_SPARE                                                                                    0x1993
6413 #define regGCR_SPARE_BASE_IDX                                                                           1
6414 #define regPMM_CNTL2                                                                                    0x1999
6415 #define regPMM_CNTL2_BASE_IDX                                                                           1
6416 
6417 
6418 // addressBlock: gc_sedcdec
6419 // base address: 0x2eb00
6420 #define regSEDC_GL1_GL2_OVERRIDES                                                                       0x1ac0
6421 #define regSEDC_GL1_GL2_OVERRIDES_BASE_IDX                                                              1
6422 
6423 
6424 // addressBlock: gc_pfonly_gccacdec
6425 // base address: 0x2eb40
6426 #define regGC_CAC_CTRL_1                                                                                0x1ad0
6427 #define regGC_CAC_CTRL_1_BASE_IDX                                                                       1
6428 #define regGC_CAC_CTRL_2                                                                                0x1ad1
6429 #define regGC_CAC_CTRL_2_BASE_IDX                                                                       1
6430 #define regGC_CAC_AGGR_LOWER                                                                            0x1ad2
6431 #define regGC_CAC_AGGR_LOWER_BASE_IDX                                                                   1
6432 #define regGC_CAC_AGGR_UPPER                                                                            0x1ad3
6433 #define regGC_CAC_AGGR_UPPER_BASE_IDX                                                                   1
6434 #define regSE0_CAC_AGGR_LOWER                                                                           0x1ad4
6435 #define regSE0_CAC_AGGR_LOWER_BASE_IDX                                                                  1
6436 #define regSE0_CAC_AGGR_UPPER                                                                           0x1ad5
6437 #define regSE0_CAC_AGGR_UPPER_BASE_IDX                                                                  1
6438 #define regSE1_CAC_AGGR_LOWER                                                                           0x1ad6
6439 #define regSE1_CAC_AGGR_LOWER_BASE_IDX                                                                  1
6440 #define regSE1_CAC_AGGR_UPPER                                                                           0x1ad7
6441 #define regSE1_CAC_AGGR_UPPER_BASE_IDX                                                                  1
6442 #define regSE2_CAC_AGGR_LOWER                                                                           0x1ad8
6443 #define regSE2_CAC_AGGR_LOWER_BASE_IDX                                                                  1
6444 #define regSE2_CAC_AGGR_UPPER                                                                           0x1ad9
6445 #define regSE2_CAC_AGGR_UPPER_BASE_IDX                                                                  1
6446 #define regSE3_CAC_AGGR_LOWER                                                                           0x1ada
6447 #define regSE3_CAC_AGGR_LOWER_BASE_IDX                                                                  1
6448 #define regSE3_CAC_AGGR_UPPER                                                                           0x1adb
6449 #define regSE3_CAC_AGGR_UPPER_BASE_IDX                                                                  1
6450 #define regSE4_CAC_AGGR_LOWER                                                                           0x1adc
6451 #define regSE4_CAC_AGGR_LOWER_BASE_IDX                                                                  1
6452 #define regSE4_CAC_AGGR_UPPER                                                                           0x1add
6453 #define regSE4_CAC_AGGR_UPPER_BASE_IDX                                                                  1
6454 #define regSE5_CAC_AGGR_LOWER                                                                           0x1ade
6455 #define regSE5_CAC_AGGR_LOWER_BASE_IDX                                                                  1
6456 #define regSE5_CAC_AGGR_UPPER                                                                           0x1adf
6457 #define regSE5_CAC_AGGR_UPPER_BASE_IDX                                                                  1
6458 #define regGC_CAC_AGGR_GFXCLK_CYCLE                                                                     0x1ae4
6459 #define regGC_CAC_AGGR_GFXCLK_CYCLE_BASE_IDX                                                            1
6460 #define regSE0_CAC_AGGR_GFXCLK_CYCLE                                                                    0x1ae5
6461 #define regSE0_CAC_AGGR_GFXCLK_CYCLE_BASE_IDX                                                           1
6462 #define regSE1_CAC_AGGR_GFXCLK_CYCLE                                                                    0x1ae6
6463 #define regSE1_CAC_AGGR_GFXCLK_CYCLE_BASE_IDX                                                           1
6464 #define regSE2_CAC_AGGR_GFXCLK_CYCLE                                                                    0x1ae7
6465 #define regSE2_CAC_AGGR_GFXCLK_CYCLE_BASE_IDX                                                           1
6466 #define regSE3_CAC_AGGR_GFXCLK_CYCLE                                                                    0x1ae8
6467 #define regSE3_CAC_AGGR_GFXCLK_CYCLE_BASE_IDX                                                           1
6468 #define regSE4_CAC_AGGR_GFXCLK_CYCLE                                                                    0x1ae9
6469 #define regSE4_CAC_AGGR_GFXCLK_CYCLE_BASE_IDX                                                           1
6470 #define regSE5_CAC_AGGR_GFXCLK_CYCLE                                                                    0x1aea
6471 #define regSE5_CAC_AGGR_GFXCLK_CYCLE_BASE_IDX                                                           1
6472 #define regGC_EDC_CTRL                                                                                  0x1aed
6473 #define regGC_EDC_CTRL_BASE_IDX                                                                         1
6474 #define regGC_EDC_THRESHOLD                                                                             0x1aee
6475 #define regGC_EDC_THRESHOLD_BASE_IDX                                                                    1
6476 #define regGC_EDC_STRETCH_CTRL                                                                          0x1aef
6477 #define regGC_EDC_STRETCH_CTRL_BASE_IDX                                                                 1
6478 #define regGC_EDC_STRETCH_THRESHOLD                                                                     0x1af0
6479 #define regGC_EDC_STRETCH_THRESHOLD_BASE_IDX                                                            1
6480 #define regEDC_HYSTERESIS_CNTL                                                                          0x1af1
6481 #define regEDC_HYSTERESIS_CNTL_BASE_IDX                                                                 1
6482 #define regGC_THROTTLE_CTRL                                                                             0x1af2
6483 #define regGC_THROTTLE_CTRL_BASE_IDX                                                                    1
6484 #define regGC_THROTTLE_CTRL1                                                                            0x1af3
6485 #define regGC_THROTTLE_CTRL1_BASE_IDX                                                                   1
6486 #define regPCC_STALL_PATTERN_CTRL                                                                       0x1af4
6487 #define regPCC_STALL_PATTERN_CTRL_BASE_IDX                                                              1
6488 #define regPWRBRK_STALL_PATTERN_CTRL                                                                    0x1af5
6489 #define regPWRBRK_STALL_PATTERN_CTRL_BASE_IDX                                                           1
6490 #define regPCC_STALL_PATTERN_1_2                                                                        0x1af6
6491 #define regPCC_STALL_PATTERN_1_2_BASE_IDX                                                               1
6492 #define regPCC_STALL_PATTERN_3_4                                                                        0x1af7
6493 #define regPCC_STALL_PATTERN_3_4_BASE_IDX                                                               1
6494 #define regPCC_STALL_PATTERN_5_6                                                                        0x1af8
6495 #define regPCC_STALL_PATTERN_5_6_BASE_IDX                                                               1
6496 #define regPCC_STALL_PATTERN_7                                                                          0x1af9
6497 #define regPCC_STALL_PATTERN_7_BASE_IDX                                                                 1
6498 #define regPWRBRK_STALL_PATTERN_1_2                                                                     0x1afa
6499 #define regPWRBRK_STALL_PATTERN_1_2_BASE_IDX                                                            1
6500 #define regPWRBRK_STALL_PATTERN_3_4                                                                     0x1afb
6501 #define regPWRBRK_STALL_PATTERN_3_4_BASE_IDX                                                            1
6502 #define regPWRBRK_STALL_PATTERN_5_6                                                                     0x1afc
6503 #define regPWRBRK_STALL_PATTERN_5_6_BASE_IDX                                                            1
6504 #define regPWRBRK_STALL_PATTERN_7                                                                       0x1afd
6505 #define regPWRBRK_STALL_PATTERN_7_BASE_IDX                                                              1
6506 #define regDIDT_STALL_PATTERN_CTRL                                                                      0x1afe
6507 #define regDIDT_STALL_PATTERN_CTRL_BASE_IDX                                                             1
6508 #define regDIDT_STALL_PATTERN_1_2                                                                       0x1aff
6509 #define regDIDT_STALL_PATTERN_1_2_BASE_IDX                                                              1
6510 #define regDIDT_STALL_PATTERN_3_4                                                                       0x1b00
6511 #define regDIDT_STALL_PATTERN_3_4_BASE_IDX                                                              1
6512 #define regDIDT_STALL_PATTERN_5_6                                                                       0x1b01
6513 #define regDIDT_STALL_PATTERN_5_6_BASE_IDX                                                              1
6514 #define regDIDT_STALL_PATTERN_7                                                                         0x1b02
6515 #define regDIDT_STALL_PATTERN_7_BASE_IDX                                                                1
6516 #define regPCC_PWRBRK_HYSTERESIS_CTRL                                                                   0x1b03
6517 #define regPCC_PWRBRK_HYSTERESIS_CTRL_BASE_IDX                                                          1
6518 #define regEDC_STRETCH_PERF_COUNTER                                                                     0x1b04
6519 #define regEDC_STRETCH_PERF_COUNTER_BASE_IDX                                                            1
6520 #define regEDC_UNSTRETCH_PERF_COUNTER                                                                   0x1b05
6521 #define regEDC_UNSTRETCH_PERF_COUNTER_BASE_IDX                                                          1
6522 #define regEDC_STRETCH_NUM_PERF_COUNTER                                                                 0x1b06
6523 #define regEDC_STRETCH_NUM_PERF_COUNTER_BASE_IDX                                                        1
6524 #define regGC_EDC_STATUS                                                                                0x1b07
6525 #define regGC_EDC_STATUS_BASE_IDX                                                                       1
6526 #define regGC_EDC_OVERFLOW                                                                              0x1b08
6527 #define regGC_EDC_OVERFLOW_BASE_IDX                                                                     1
6528 #define regGC_EDC_ROLLING_POWER_DELTA                                                                   0x1b09
6529 #define regGC_EDC_ROLLING_POWER_DELTA_BASE_IDX                                                          1
6530 #define regGC_THROTTLE_STATUS                                                                           0x1b0a
6531 #define regGC_THROTTLE_STATUS_BASE_IDX                                                                  1
6532 #define regEDC_PERF_COUNTER                                                                             0x1b0b
6533 #define regEDC_PERF_COUNTER_BASE_IDX                                                                    1
6534 #define regPCC_PERF_COUNTER                                                                             0x1b0c
6535 #define regPCC_PERF_COUNTER_BASE_IDX                                                                    1
6536 #define regPWRBRK_PERF_COUNTER                                                                          0x1b0d
6537 #define regPWRBRK_PERF_COUNTER_BASE_IDX                                                                 1
6538 #define regEDC_HYSTERESIS_STAT                                                                          0x1b0e
6539 #define regEDC_HYSTERESIS_STAT_BASE_IDX                                                                 1
6540 #define regGC_CAC_WEIGHT_CP_0                                                                           0x1b10
6541 #define regGC_CAC_WEIGHT_CP_0_BASE_IDX                                                                  1
6542 #define regGC_CAC_WEIGHT_CP_1                                                                           0x1b11
6543 #define regGC_CAC_WEIGHT_CP_1_BASE_IDX                                                                  1
6544 #define regGC_CAC_WEIGHT_EA_0                                                                           0x1b12
6545 #define regGC_CAC_WEIGHT_EA_0_BASE_IDX                                                                  1
6546 #define regGC_CAC_WEIGHT_EA_1                                                                           0x1b13
6547 #define regGC_CAC_WEIGHT_EA_1_BASE_IDX                                                                  1
6548 #define regGC_CAC_WEIGHT_EA_2                                                                           0x1b14
6549 #define regGC_CAC_WEIGHT_EA_2_BASE_IDX                                                                  1
6550 #define regGC_CAC_WEIGHT_UTCL2_ROUTER_0                                                                 0x1b15
6551 #define regGC_CAC_WEIGHT_UTCL2_ROUTER_0_BASE_IDX                                                        1
6552 #define regGC_CAC_WEIGHT_UTCL2_ROUTER_1                                                                 0x1b16
6553 #define regGC_CAC_WEIGHT_UTCL2_ROUTER_1_BASE_IDX                                                        1
6554 #define regGC_CAC_WEIGHT_UTCL2_ROUTER_2                                                                 0x1b17
6555 #define regGC_CAC_WEIGHT_UTCL2_ROUTER_2_BASE_IDX                                                        1
6556 #define regGC_CAC_WEIGHT_UTCL2_ROUTER_3                                                                 0x1b18
6557 #define regGC_CAC_WEIGHT_UTCL2_ROUTER_3_BASE_IDX                                                        1
6558 #define regGC_CAC_WEIGHT_UTCL2_ROUTER_4                                                                 0x1b19
6559 #define regGC_CAC_WEIGHT_UTCL2_ROUTER_4_BASE_IDX                                                        1
6560 #define regGC_CAC_WEIGHT_UTCL2_VML2_0                                                                   0x1b1a
6561 #define regGC_CAC_WEIGHT_UTCL2_VML2_0_BASE_IDX                                                          1
6562 #define regGC_CAC_WEIGHT_UTCL2_VML2_1                                                                   0x1b1b
6563 #define regGC_CAC_WEIGHT_UTCL2_VML2_1_BASE_IDX                                                          1
6564 #define regGC_CAC_WEIGHT_UTCL2_VML2_2                                                                   0x1b1c
6565 #define regGC_CAC_WEIGHT_UTCL2_VML2_2_BASE_IDX                                                          1
6566 #define regGC_CAC_WEIGHT_UTCL2_WALKER_0                                                                 0x1b1d
6567 #define regGC_CAC_WEIGHT_UTCL2_WALKER_0_BASE_IDX                                                        1
6568 #define regGC_CAC_WEIGHT_UTCL2_WALKER_1                                                                 0x1b1e
6569 #define regGC_CAC_WEIGHT_UTCL2_WALKER_1_BASE_IDX                                                        1
6570 #define regGC_CAC_WEIGHT_UTCL2_WALKER_2                                                                 0x1b1f
6571 #define regGC_CAC_WEIGHT_UTCL2_WALKER_2_BASE_IDX                                                        1
6572 #define regGC_CAC_WEIGHT_GDS_0                                                                          0x1b20
6573 #define regGC_CAC_WEIGHT_GDS_0_BASE_IDX                                                                 1
6574 #define regGC_CAC_WEIGHT_GDS_1                                                                          0x1b21
6575 #define regGC_CAC_WEIGHT_GDS_1_BASE_IDX                                                                 1
6576 #define regGC_CAC_WEIGHT_GDS_2                                                                          0x1b22
6577 #define regGC_CAC_WEIGHT_GDS_2_BASE_IDX                                                                 1
6578 #define regGC_CAC_WEIGHT_GE_0                                                                           0x1b23
6579 #define regGC_CAC_WEIGHT_GE_0_BASE_IDX                                                                  1
6580 #define regGC_CAC_WEIGHT_GE_1                                                                           0x1b24
6581 #define regGC_CAC_WEIGHT_GE_1_BASE_IDX                                                                  1
6582 #define regGC_CAC_WEIGHT_GE_2                                                                           0x1b25
6583 #define regGC_CAC_WEIGHT_GE_2_BASE_IDX                                                                  1
6584 #define regGC_CAC_WEIGHT_GE_3                                                                           0x1b26
6585 #define regGC_CAC_WEIGHT_GE_3_BASE_IDX                                                                  1
6586 #define regGC_CAC_WEIGHT_GE_4                                                                           0x1b27
6587 #define regGC_CAC_WEIGHT_GE_4_BASE_IDX                                                                  1
6588 #define regGC_CAC_WEIGHT_GE_5                                                                           0x1b28
6589 #define regGC_CAC_WEIGHT_GE_5_BASE_IDX                                                                  1
6590 #define regGC_CAC_WEIGHT_GE_6                                                                           0x1b29
6591 #define regGC_CAC_WEIGHT_GE_6_BASE_IDX                                                                  1
6592 #define regGC_CAC_WEIGHT_PMM_0                                                                          0x1b2e
6593 #define regGC_CAC_WEIGHT_PMM_0_BASE_IDX                                                                 1
6594 #define regGC_CAC_WEIGHT_GL2C_0                                                                         0x1b2f
6595 #define regGC_CAC_WEIGHT_GL2C_0_BASE_IDX                                                                1
6596 #define regGC_CAC_WEIGHT_GL2C_1                                                                         0x1b30
6597 #define regGC_CAC_WEIGHT_GL2C_1_BASE_IDX                                                                1
6598 #define regGC_CAC_WEIGHT_GL2C_2                                                                         0x1b31
6599 #define regGC_CAC_WEIGHT_GL2C_2_BASE_IDX                                                                1
6600 #define regGC_CAC_WEIGHT_PH_0                                                                           0x1b32
6601 #define regGC_CAC_WEIGHT_PH_0_BASE_IDX                                                                  1
6602 #define regGC_CAC_WEIGHT_PH_1                                                                           0x1b33
6603 #define regGC_CAC_WEIGHT_PH_1_BASE_IDX                                                                  1
6604 #define regGC_CAC_WEIGHT_PH_2                                                                           0x1b34
6605 #define regGC_CAC_WEIGHT_PH_2_BASE_IDX                                                                  1
6606 #define regGC_CAC_WEIGHT_PH_3                                                                           0x1b35
6607 #define regGC_CAC_WEIGHT_PH_3_BASE_IDX                                                                  1
6608 #define regGC_CAC_WEIGHT_SDMA_0                                                                         0x1b36
6609 #define regGC_CAC_WEIGHT_SDMA_0_BASE_IDX                                                                1
6610 #define regGC_CAC_WEIGHT_SDMA_1                                                                         0x1b37
6611 #define regGC_CAC_WEIGHT_SDMA_1_BASE_IDX                                                                1
6612 #define regGC_CAC_WEIGHT_SDMA_2                                                                         0x1b38
6613 #define regGC_CAC_WEIGHT_SDMA_2_BASE_IDX                                                                1
6614 #define regGC_CAC_WEIGHT_SDMA_3                                                                         0x1b39
6615 #define regGC_CAC_WEIGHT_SDMA_3_BASE_IDX                                                                1
6616 #define regGC_CAC_WEIGHT_SDMA_4                                                                         0x1b3a
6617 #define regGC_CAC_WEIGHT_SDMA_4_BASE_IDX                                                                1
6618 #define regGC_CAC_WEIGHT_SDMA_5                                                                         0x1b3b
6619 #define regGC_CAC_WEIGHT_SDMA_5_BASE_IDX                                                                1
6620 #define regGC_CAC_WEIGHT_CHC_0                                                                          0x1b3c
6621 #define regGC_CAC_WEIGHT_CHC_0_BASE_IDX                                                                 1
6622 #define regGC_CAC_WEIGHT_CHC_1                                                                          0x1b3d
6623 #define regGC_CAC_WEIGHT_CHC_1_BASE_IDX                                                                 1
6624 #define regGC_CAC_WEIGHT_GUS_0                                                                          0x1b3e
6625 #define regGC_CAC_WEIGHT_GUS_0_BASE_IDX                                                                 1
6626 #define regGC_CAC_WEIGHT_GUS_1                                                                          0x1b3f
6627 #define regGC_CAC_WEIGHT_GUS_1_BASE_IDX                                                                 1
6628 #define regGC_CAC_WEIGHT_RLC_0                                                                          0x1b40
6629 #define regGC_CAC_WEIGHT_RLC_0_BASE_IDX                                                                 1
6630 #define regGC_CAC_WEIGHT_GRBM_0                                                                         0x1b44
6631 #define regGC_CAC_WEIGHT_GRBM_0_BASE_IDX                                                                1
6632 #define regGC_EDC_CLK_MONITOR_CTRL                                                                      0x1b56
6633 #define regGC_EDC_CLK_MONITOR_CTRL_BASE_IDX                                                             1
6634 #define regGC_CAC_IND_INDEX                                                                             0x1b58
6635 #define regGC_CAC_IND_INDEX_BASE_IDX                                                                    1
6636 #define regGC_CAC_IND_DATA                                                                              0x1b59
6637 #define regGC_CAC_IND_DATA_BASE_IDX                                                                     1
6638 #define regSE_CAC_CTRL_1                                                                                0x1b70
6639 #define regSE_CAC_CTRL_1_BASE_IDX                                                                       1
6640 #define regSE_CAC_CTRL_2                                                                                0x1b71
6641 #define regSE_CAC_CTRL_2_BASE_IDX                                                                       1
6642 #define regSE_CAC_WEIGHT_TA_0                                                                           0x1b72
6643 #define regSE_CAC_WEIGHT_TA_0_BASE_IDX                                                                  1
6644 #define regSE_CAC_WEIGHT_TD_0                                                                           0x1b73
6645 #define regSE_CAC_WEIGHT_TD_0_BASE_IDX                                                                  1
6646 #define regSE_CAC_WEIGHT_TD_1                                                                           0x1b74
6647 #define regSE_CAC_WEIGHT_TD_1_BASE_IDX                                                                  1
6648 #define regSE_CAC_WEIGHT_TD_2                                                                           0x1b75
6649 #define regSE_CAC_WEIGHT_TD_2_BASE_IDX                                                                  1
6650 #define regSE_CAC_WEIGHT_TD_3                                                                           0x1b76
6651 #define regSE_CAC_WEIGHT_TD_3_BASE_IDX                                                                  1
6652 #define regSE_CAC_WEIGHT_TD_4                                                                           0x1b77
6653 #define regSE_CAC_WEIGHT_TD_4_BASE_IDX                                                                  1
6654 #define regSE_CAC_WEIGHT_TD_5                                                                           0x1b78
6655 #define regSE_CAC_WEIGHT_TD_5_BASE_IDX                                                                  1
6656 #define regSE_CAC_WEIGHT_TCP_0                                                                          0x1b79
6657 #define regSE_CAC_WEIGHT_TCP_0_BASE_IDX                                                                 1
6658 #define regSE_CAC_WEIGHT_TCP_1                                                                          0x1b7a
6659 #define regSE_CAC_WEIGHT_TCP_1_BASE_IDX                                                                 1
6660 #define regSE_CAC_WEIGHT_TCP_2                                                                          0x1b7b
6661 #define regSE_CAC_WEIGHT_TCP_2_BASE_IDX                                                                 1
6662 #define regSE_CAC_WEIGHT_TCP_3                                                                          0x1b7c
6663 #define regSE_CAC_WEIGHT_TCP_3_BASE_IDX                                                                 1
6664 #define regSE_CAC_WEIGHT_SQ_0                                                                           0x1b7d
6665 #define regSE_CAC_WEIGHT_SQ_0_BASE_IDX                                                                  1
6666 #define regSE_CAC_WEIGHT_SQ_1                                                                           0x1b7e
6667 #define regSE_CAC_WEIGHT_SQ_1_BASE_IDX                                                                  1
6668 #define regSE_CAC_WEIGHT_SQ_2                                                                           0x1b7f
6669 #define regSE_CAC_WEIGHT_SQ_2_BASE_IDX                                                                  1
6670 #define regSE_CAC_WEIGHT_SP_0                                                                           0x1b80
6671 #define regSE_CAC_WEIGHT_SP_0_BASE_IDX                                                                  1
6672 #define regSE_CAC_WEIGHT_SP_1                                                                           0x1b81
6673 #define regSE_CAC_WEIGHT_SP_1_BASE_IDX                                                                  1
6674 #define regSE_CAC_WEIGHT_LDS_0                                                                          0x1b82
6675 #define regSE_CAC_WEIGHT_LDS_0_BASE_IDX                                                                 1
6676 #define regSE_CAC_WEIGHT_LDS_1                                                                          0x1b83
6677 #define regSE_CAC_WEIGHT_LDS_1_BASE_IDX                                                                 1
6678 #define regSE_CAC_WEIGHT_LDS_2                                                                          0x1b84
6679 #define regSE_CAC_WEIGHT_LDS_2_BASE_IDX                                                                 1
6680 #define regSE_CAC_WEIGHT_LDS_3                                                                          0x1b85
6681 #define regSE_CAC_WEIGHT_LDS_3_BASE_IDX                                                                 1
6682 #define regSE_CAC_WEIGHT_SQC_0                                                                          0x1b87
6683 #define regSE_CAC_WEIGHT_SQC_0_BASE_IDX                                                                 1
6684 #define regSE_CAC_WEIGHT_SQC_1                                                                          0x1b88
6685 #define regSE_CAC_WEIGHT_SQC_1_BASE_IDX                                                                 1
6686 #define regSE_CAC_WEIGHT_CU_0                                                                           0x1b89
6687 #define regSE_CAC_WEIGHT_CU_0_BASE_IDX                                                                  1
6688 #define regSE_CAC_WEIGHT_BCI_0                                                                          0x1b8a
6689 #define regSE_CAC_WEIGHT_BCI_0_BASE_IDX                                                                 1
6690 #define regSE_CAC_WEIGHT_CB_0                                                                           0x1b8b
6691 #define regSE_CAC_WEIGHT_CB_0_BASE_IDX                                                                  1
6692 #define regSE_CAC_WEIGHT_CB_1                                                                           0x1b8c
6693 #define regSE_CAC_WEIGHT_CB_1_BASE_IDX                                                                  1
6694 #define regSE_CAC_WEIGHT_CB_2                                                                           0x1b8d
6695 #define regSE_CAC_WEIGHT_CB_2_BASE_IDX                                                                  1
6696 #define regSE_CAC_WEIGHT_CB_3                                                                           0x1b8e
6697 #define regSE_CAC_WEIGHT_CB_3_BASE_IDX                                                                  1
6698 #define regSE_CAC_WEIGHT_CB_4                                                                           0x1b8f
6699 #define regSE_CAC_WEIGHT_CB_4_BASE_IDX                                                                  1
6700 #define regSE_CAC_WEIGHT_CB_5                                                                           0x1b90
6701 #define regSE_CAC_WEIGHT_CB_5_BASE_IDX                                                                  1
6702 #define regSE_CAC_WEIGHT_CB_6                                                                           0x1b91
6703 #define regSE_CAC_WEIGHT_CB_6_BASE_IDX                                                                  1
6704 #define regSE_CAC_WEIGHT_CB_7                                                                           0x1b92
6705 #define regSE_CAC_WEIGHT_CB_7_BASE_IDX                                                                  1
6706 #define regSE_CAC_WEIGHT_CB_8                                                                           0x1b93
6707 #define regSE_CAC_WEIGHT_CB_8_BASE_IDX                                                                  1
6708 #define regSE_CAC_WEIGHT_CB_9                                                                           0x1b94
6709 #define regSE_CAC_WEIGHT_CB_9_BASE_IDX                                                                  1
6710 #define regSE_CAC_WEIGHT_CB_10                                                                          0x1b95
6711 #define regSE_CAC_WEIGHT_CB_10_BASE_IDX                                                                 1
6712 #define regSE_CAC_WEIGHT_CB_11                                                                          0x1b96
6713 #define regSE_CAC_WEIGHT_CB_11_BASE_IDX                                                                 1
6714 #define regSE_CAC_WEIGHT_DB_0                                                                           0x1b97
6715 #define regSE_CAC_WEIGHT_DB_0_BASE_IDX                                                                  1
6716 #define regSE_CAC_WEIGHT_DB_1                                                                           0x1b98
6717 #define regSE_CAC_WEIGHT_DB_1_BASE_IDX                                                                  1
6718 #define regSE_CAC_WEIGHT_DB_2                                                                           0x1b99
6719 #define regSE_CAC_WEIGHT_DB_2_BASE_IDX                                                                  1
6720 #define regSE_CAC_WEIGHT_DB_3                                                                           0x1b9a
6721 #define regSE_CAC_WEIGHT_DB_3_BASE_IDX                                                                  1
6722 #define regSE_CAC_WEIGHT_DB_4                                                                           0x1b9b
6723 #define regSE_CAC_WEIGHT_DB_4_BASE_IDX                                                                  1
6724 #define regSE_CAC_WEIGHT_RMI_0                                                                          0x1b9c
6725 #define regSE_CAC_WEIGHT_RMI_0_BASE_IDX                                                                 1
6726 #define regSE_CAC_WEIGHT_RMI_1                                                                          0x1b9d
6727 #define regSE_CAC_WEIGHT_RMI_1_BASE_IDX                                                                 1
6728 #define regSE_CAC_WEIGHT_SX_0                                                                           0x1b9e
6729 #define regSE_CAC_WEIGHT_SX_0_BASE_IDX                                                                  1
6730 #define regSE_CAC_WEIGHT_SXRB_0                                                                         0x1b9f
6731 #define regSE_CAC_WEIGHT_SXRB_0_BASE_IDX                                                                1
6732 #define regSE_CAC_WEIGHT_UTCL1_0                                                                        0x1ba0
6733 #define regSE_CAC_WEIGHT_UTCL1_0_BASE_IDX                                                               1
6734 #define regSE_CAC_WEIGHT_GL1C_0                                                                         0x1ba1
6735 #define regSE_CAC_WEIGHT_GL1C_0_BASE_IDX                                                                1
6736 #define regSE_CAC_WEIGHT_GL1C_1                                                                         0x1ba2
6737 #define regSE_CAC_WEIGHT_GL1C_1_BASE_IDX                                                                1
6738 #define regSE_CAC_WEIGHT_GL1C_2                                                                         0x1ba3
6739 #define regSE_CAC_WEIGHT_GL1C_2_BASE_IDX                                                                1
6740 #define regSE_CAC_WEIGHT_SPI_0                                                                          0x1ba4
6741 #define regSE_CAC_WEIGHT_SPI_0_BASE_IDX                                                                 1
6742 #define regSE_CAC_WEIGHT_SPI_1                                                                          0x1ba5
6743 #define regSE_CAC_WEIGHT_SPI_1_BASE_IDX                                                                 1
6744 #define regSE_CAC_WEIGHT_SPI_2                                                                          0x1ba6
6745 #define regSE_CAC_WEIGHT_SPI_2_BASE_IDX                                                                 1
6746 #define regSE_CAC_WEIGHT_PC_0                                                                           0x1ba7
6747 #define regSE_CAC_WEIGHT_PC_0_BASE_IDX                                                                  1
6748 #define regSE_CAC_WEIGHT_PA_0                                                                           0x1ba8
6749 #define regSE_CAC_WEIGHT_PA_0_BASE_IDX                                                                  1
6750 #define regSE_CAC_WEIGHT_PA_1                                                                           0x1ba9
6751 #define regSE_CAC_WEIGHT_PA_1_BASE_IDX                                                                  1
6752 #define regSE_CAC_WEIGHT_PA_2                                                                           0x1baa
6753 #define regSE_CAC_WEIGHT_PA_2_BASE_IDX                                                                  1
6754 #define regSE_CAC_WEIGHT_PA_3                                                                           0x1bab
6755 #define regSE_CAC_WEIGHT_PA_3_BASE_IDX                                                                  1
6756 #define regSE_CAC_WEIGHT_SC_0                                                                           0x1bac
6757 #define regSE_CAC_WEIGHT_SC_0_BASE_IDX                                                                  1
6758 #define regSE_CAC_WEIGHT_SC_1                                                                           0x1bad
6759 #define regSE_CAC_WEIGHT_SC_1_BASE_IDX                                                                  1
6760 #define regSE_CAC_WEIGHT_SC_2                                                                           0x1bae
6761 #define regSE_CAC_WEIGHT_SC_2_BASE_IDX                                                                  1
6762 #define regSE_CAC_WEIGHT_SC_3                                                                           0x1baf
6763 #define regSE_CAC_WEIGHT_SC_3_BASE_IDX                                                                  1
6764 #define regSE_CAC_WINDOW_AGGR_VALUE                                                                     0x1bb0
6765 #define regSE_CAC_WINDOW_AGGR_VALUE_BASE_IDX                                                            1
6766 #define regSE_CAC_WINDOW_GFXCLK_CYCLE                                                                   0x1bb1
6767 #define regSE_CAC_WINDOW_GFXCLK_CYCLE_BASE_IDX                                                          1
6768 #define regSE_CAC_IND_INDEX                                                                             0x1bce
6769 #define regSE_CAC_IND_INDEX_BASE_IDX                                                                    1
6770 #define regSE_CAC_IND_DATA                                                                              0x1bcf
6771 #define regSE_CAC_IND_DATA_BASE_IDX                                                                     1
6772 
6773 
6774 // addressBlock: gc_pfonly2_spidec
6775 // base address: 0x2f000
6776 #define regSPI_RESOURCE_RESERVE_CU_0                                                                    0x1c00
6777 #define regSPI_RESOURCE_RESERVE_CU_0_BASE_IDX                                                           1
6778 #define regSPI_RESOURCE_RESERVE_CU_1                                                                    0x1c01
6779 #define regSPI_RESOURCE_RESERVE_CU_1_BASE_IDX                                                           1
6780 #define regSPI_RESOURCE_RESERVE_CU_2                                                                    0x1c02
6781 #define regSPI_RESOURCE_RESERVE_CU_2_BASE_IDX                                                           1
6782 #define regSPI_RESOURCE_RESERVE_CU_3                                                                    0x1c03
6783 #define regSPI_RESOURCE_RESERVE_CU_3_BASE_IDX                                                           1
6784 #define regSPI_RESOURCE_RESERVE_CU_4                                                                    0x1c04
6785 #define regSPI_RESOURCE_RESERVE_CU_4_BASE_IDX                                                           1
6786 #define regSPI_RESOURCE_RESERVE_CU_5                                                                    0x1c05
6787 #define regSPI_RESOURCE_RESERVE_CU_5_BASE_IDX                                                           1
6788 #define regSPI_RESOURCE_RESERVE_CU_6                                                                    0x1c06
6789 #define regSPI_RESOURCE_RESERVE_CU_6_BASE_IDX                                                           1
6790 #define regSPI_RESOURCE_RESERVE_CU_7                                                                    0x1c07
6791 #define regSPI_RESOURCE_RESERVE_CU_7_BASE_IDX                                                           1
6792 #define regSPI_RESOURCE_RESERVE_CU_8                                                                    0x1c08
6793 #define regSPI_RESOURCE_RESERVE_CU_8_BASE_IDX                                                           1
6794 #define regSPI_RESOURCE_RESERVE_CU_9                                                                    0x1c09
6795 #define regSPI_RESOURCE_RESERVE_CU_9_BASE_IDX                                                           1
6796 #define regSPI_RESOURCE_RESERVE_CU_10                                                                   0x1c0a
6797 #define regSPI_RESOURCE_RESERVE_CU_10_BASE_IDX                                                          1
6798 #define regSPI_RESOURCE_RESERVE_CU_11                                                                   0x1c0b
6799 #define regSPI_RESOURCE_RESERVE_CU_11_BASE_IDX                                                          1
6800 #define regSPI_RESOURCE_RESERVE_CU_12                                                                   0x1c0c
6801 #define regSPI_RESOURCE_RESERVE_CU_12_BASE_IDX                                                          1
6802 #define regSPI_RESOURCE_RESERVE_CU_13                                                                   0x1c0d
6803 #define regSPI_RESOURCE_RESERVE_CU_13_BASE_IDX                                                          1
6804 #define regSPI_RESOURCE_RESERVE_CU_14                                                                   0x1c0e
6805 #define regSPI_RESOURCE_RESERVE_CU_14_BASE_IDX                                                          1
6806 #define regSPI_RESOURCE_RESERVE_CU_15                                                                   0x1c0f
6807 #define regSPI_RESOURCE_RESERVE_CU_15_BASE_IDX                                                          1
6808 #define regSPI_RESOURCE_RESERVE_EN_CU_0                                                                 0x1c10
6809 #define regSPI_RESOURCE_RESERVE_EN_CU_0_BASE_IDX                                                        1
6810 #define regSPI_RESOURCE_RESERVE_EN_CU_1                                                                 0x1c11
6811 #define regSPI_RESOURCE_RESERVE_EN_CU_1_BASE_IDX                                                        1
6812 #define regSPI_RESOURCE_RESERVE_EN_CU_2                                                                 0x1c12
6813 #define regSPI_RESOURCE_RESERVE_EN_CU_2_BASE_IDX                                                        1
6814 #define regSPI_RESOURCE_RESERVE_EN_CU_3                                                                 0x1c13
6815 #define regSPI_RESOURCE_RESERVE_EN_CU_3_BASE_IDX                                                        1
6816 #define regSPI_RESOURCE_RESERVE_EN_CU_4                                                                 0x1c14
6817 #define regSPI_RESOURCE_RESERVE_EN_CU_4_BASE_IDX                                                        1
6818 #define regSPI_RESOURCE_RESERVE_EN_CU_5                                                                 0x1c15
6819 #define regSPI_RESOURCE_RESERVE_EN_CU_5_BASE_IDX                                                        1
6820 #define regSPI_RESOURCE_RESERVE_EN_CU_6                                                                 0x1c16
6821 #define regSPI_RESOURCE_RESERVE_EN_CU_6_BASE_IDX                                                        1
6822 #define regSPI_RESOURCE_RESERVE_EN_CU_7                                                                 0x1c17
6823 #define regSPI_RESOURCE_RESERVE_EN_CU_7_BASE_IDX                                                        1
6824 #define regSPI_RESOURCE_RESERVE_EN_CU_8                                                                 0x1c18
6825 #define regSPI_RESOURCE_RESERVE_EN_CU_8_BASE_IDX                                                        1
6826 #define regSPI_RESOURCE_RESERVE_EN_CU_9                                                                 0x1c19
6827 #define regSPI_RESOURCE_RESERVE_EN_CU_9_BASE_IDX                                                        1
6828 #define regSPI_RESOURCE_RESERVE_EN_CU_10                                                                0x1c1a
6829 #define regSPI_RESOURCE_RESERVE_EN_CU_10_BASE_IDX                                                       1
6830 #define regSPI_RESOURCE_RESERVE_EN_CU_11                                                                0x1c1b
6831 #define regSPI_RESOURCE_RESERVE_EN_CU_11_BASE_IDX                                                       1
6832 #define regSPI_RESOURCE_RESERVE_EN_CU_12                                                                0x1c1c
6833 #define regSPI_RESOURCE_RESERVE_EN_CU_12_BASE_IDX                                                       1
6834 #define regSPI_RESOURCE_RESERVE_EN_CU_13                                                                0x1c1d
6835 #define regSPI_RESOURCE_RESERVE_EN_CU_13_BASE_IDX                                                       1
6836 #define regSPI_RESOURCE_RESERVE_EN_CU_14                                                                0x1c1e
6837 #define regSPI_RESOURCE_RESERVE_EN_CU_14_BASE_IDX                                                       1
6838 #define regSPI_RESOURCE_RESERVE_EN_CU_15                                                                0x1c1f
6839 #define regSPI_RESOURCE_RESERVE_EN_CU_15_BASE_IDX                                                       1
6840 
6841 
6842 // addressBlock: gc_gfxudec
6843 // base address: 0x30000
6844 #define regCP_EOP_DONE_ADDR_LO                                                                          0x2000
6845 #define regCP_EOP_DONE_ADDR_LO_BASE_IDX                                                                 1
6846 #define regCP_EOP_DONE_ADDR_HI                                                                          0x2001
6847 #define regCP_EOP_DONE_ADDR_HI_BASE_IDX                                                                 1
6848 #define regCP_EOP_DONE_DATA_LO                                                                          0x2002
6849 #define regCP_EOP_DONE_DATA_LO_BASE_IDX                                                                 1
6850 #define regCP_EOP_DONE_DATA_HI                                                                          0x2003
6851 #define regCP_EOP_DONE_DATA_HI_BASE_IDX                                                                 1
6852 #define regCP_EOP_LAST_FENCE_LO                                                                         0x2004
6853 #define regCP_EOP_LAST_FENCE_LO_BASE_IDX                                                                1
6854 #define regCP_EOP_LAST_FENCE_HI                                                                         0x2005
6855 #define regCP_EOP_LAST_FENCE_HI_BASE_IDX                                                                1
6856 #define regCP_PIPE_STATS_ADDR_LO                                                                        0x2018
6857 #define regCP_PIPE_STATS_ADDR_LO_BASE_IDX                                                               1
6858 #define regCP_PIPE_STATS_ADDR_HI                                                                        0x2019
6859 #define regCP_PIPE_STATS_ADDR_HI_BASE_IDX                                                               1
6860 #define regCP_VGT_IAVERT_COUNT_LO                                                                       0x201a
6861 #define regCP_VGT_IAVERT_COUNT_LO_BASE_IDX                                                              1
6862 #define regCP_VGT_IAVERT_COUNT_HI                                                                       0x201b
6863 #define regCP_VGT_IAVERT_COUNT_HI_BASE_IDX                                                              1
6864 #define regCP_VGT_IAPRIM_COUNT_LO                                                                       0x201c
6865 #define regCP_VGT_IAPRIM_COUNT_LO_BASE_IDX                                                              1
6866 #define regCP_VGT_IAPRIM_COUNT_HI                                                                       0x201d
6867 #define regCP_VGT_IAPRIM_COUNT_HI_BASE_IDX                                                              1
6868 #define regCP_VGT_GSPRIM_COUNT_LO                                                                       0x201e
6869 #define regCP_VGT_GSPRIM_COUNT_LO_BASE_IDX                                                              1
6870 #define regCP_VGT_GSPRIM_COUNT_HI                                                                       0x201f
6871 #define regCP_VGT_GSPRIM_COUNT_HI_BASE_IDX                                                              1
6872 #define regCP_VGT_VSINVOC_COUNT_LO                                                                      0x2020
6873 #define regCP_VGT_VSINVOC_COUNT_LO_BASE_IDX                                                             1
6874 #define regCP_VGT_VSINVOC_COUNT_HI                                                                      0x2021
6875 #define regCP_VGT_VSINVOC_COUNT_HI_BASE_IDX                                                             1
6876 #define regCP_VGT_GSINVOC_COUNT_LO                                                                      0x2022
6877 #define regCP_VGT_GSINVOC_COUNT_LO_BASE_IDX                                                             1
6878 #define regCP_VGT_GSINVOC_COUNT_HI                                                                      0x2023
6879 #define regCP_VGT_GSINVOC_COUNT_HI_BASE_IDX                                                             1
6880 #define regCP_VGT_HSINVOC_COUNT_LO                                                                      0x2024
6881 #define regCP_VGT_HSINVOC_COUNT_LO_BASE_IDX                                                             1
6882 #define regCP_VGT_HSINVOC_COUNT_HI                                                                      0x2025
6883 #define regCP_VGT_HSINVOC_COUNT_HI_BASE_IDX                                                             1
6884 #define regCP_VGT_DSINVOC_COUNT_LO                                                                      0x2026
6885 #define regCP_VGT_DSINVOC_COUNT_LO_BASE_IDX                                                             1
6886 #define regCP_VGT_DSINVOC_COUNT_HI                                                                      0x2027
6887 #define regCP_VGT_DSINVOC_COUNT_HI_BASE_IDX                                                             1
6888 #define regCP_PA_CINVOC_COUNT_LO                                                                        0x2028
6889 #define regCP_PA_CINVOC_COUNT_LO_BASE_IDX                                                               1
6890 #define regCP_PA_CINVOC_COUNT_HI                                                                        0x2029
6891 #define regCP_PA_CINVOC_COUNT_HI_BASE_IDX                                                               1
6892 #define regCP_PA_CPRIM_COUNT_LO                                                                         0x202a
6893 #define regCP_PA_CPRIM_COUNT_LO_BASE_IDX                                                                1
6894 #define regCP_PA_CPRIM_COUNT_HI                                                                         0x202b
6895 #define regCP_PA_CPRIM_COUNT_HI_BASE_IDX                                                                1
6896 #define regCP_SC_PSINVOC_COUNT0_LO                                                                      0x202c
6897 #define regCP_SC_PSINVOC_COUNT0_LO_BASE_IDX                                                             1
6898 #define regCP_SC_PSINVOC_COUNT0_HI                                                                      0x202d
6899 #define regCP_SC_PSINVOC_COUNT0_HI_BASE_IDX                                                             1
6900 #define regCP_SC_PSINVOC_COUNT1_LO                                                                      0x202e
6901 #define regCP_SC_PSINVOC_COUNT1_LO_BASE_IDX                                                             1
6902 #define regCP_SC_PSINVOC_COUNT1_HI                                                                      0x202f
6903 #define regCP_SC_PSINVOC_COUNT1_HI_BASE_IDX                                                             1
6904 #define regCP_VGT_CSINVOC_COUNT_LO                                                                      0x2030
6905 #define regCP_VGT_CSINVOC_COUNT_LO_BASE_IDX                                                             1
6906 #define regCP_VGT_CSINVOC_COUNT_HI                                                                      0x2031
6907 #define regCP_VGT_CSINVOC_COUNT_HI_BASE_IDX                                                             1
6908 #define regCP_VGT_ASINVOC_COUNT_LO                                                                      0x2032
6909 #define regCP_VGT_ASINVOC_COUNT_LO_BASE_IDX                                                             1
6910 #define regCP_VGT_ASINVOC_COUNT_HI                                                                      0x2033
6911 #define regCP_VGT_ASINVOC_COUNT_HI_BASE_IDX                                                             1
6912 #define regCP_PIPE_STATS_CONTROL                                                                        0x203d
6913 #define regCP_PIPE_STATS_CONTROL_BASE_IDX                                                               1
6914 #define regSCRATCH_REG0                                                                                 0x2040
6915 #define regSCRATCH_REG0_BASE_IDX                                                                        1
6916 #define regSCRATCH_REG1                                                                                 0x2041
6917 #define regSCRATCH_REG1_BASE_IDX                                                                        1
6918 #define regSCRATCH_REG2                                                                                 0x2042
6919 #define regSCRATCH_REG2_BASE_IDX                                                                        1
6920 #define regSCRATCH_REG3                                                                                 0x2043
6921 #define regSCRATCH_REG3_BASE_IDX                                                                        1
6922 #define regSCRATCH_REG4                                                                                 0x2044
6923 #define regSCRATCH_REG4_BASE_IDX                                                                        1
6924 #define regSCRATCH_REG5                                                                                 0x2045
6925 #define regSCRATCH_REG5_BASE_IDX                                                                        1
6926 #define regSCRATCH_REG6                                                                                 0x2046
6927 #define regSCRATCH_REG6_BASE_IDX                                                                        1
6928 #define regSCRATCH_REG7                                                                                 0x2047
6929 #define regSCRATCH_REG7_BASE_IDX                                                                        1
6930 #define regSCRATCH_REG_ATOMIC                                                                           0x2048
6931 #define regSCRATCH_REG_ATOMIC_BASE_IDX                                                                  1
6932 #define regSCRATCH_REG_CMPSWAP_ATOMIC                                                                   0x2048
6933 #define regSCRATCH_REG_CMPSWAP_ATOMIC_BASE_IDX                                                          1
6934 #define regCP_APPEND_DDID_CNT                                                                           0x204b
6935 #define regCP_APPEND_DDID_CNT_BASE_IDX                                                                  1
6936 #define regCP_APPEND_DATA_HI                                                                            0x204c
6937 #define regCP_APPEND_DATA_HI_BASE_IDX                                                                   1
6938 #define regCP_APPEND_LAST_CS_FENCE_HI                                                                   0x204d
6939 #define regCP_APPEND_LAST_CS_FENCE_HI_BASE_IDX                                                          1
6940 #define regCP_APPEND_LAST_PS_FENCE_HI                                                                   0x204e
6941 #define regCP_APPEND_LAST_PS_FENCE_HI_BASE_IDX                                                          1
6942 #define regCP_PFP_ATOMIC_PREOP_LO                                                                       0x2052
6943 #define regCP_PFP_ATOMIC_PREOP_LO_BASE_IDX                                                              1
6944 #define regCP_PFP_ATOMIC_PREOP_HI                                                                       0x2053
6945 #define regCP_PFP_ATOMIC_PREOP_HI_BASE_IDX                                                              1
6946 #define regCP_PFP_GDS_ATOMIC0_PREOP_LO                                                                  0x2054
6947 #define regCP_PFP_GDS_ATOMIC0_PREOP_LO_BASE_IDX                                                         1
6948 #define regCP_PFP_GDS_ATOMIC0_PREOP_HI                                                                  0x2055
6949 #define regCP_PFP_GDS_ATOMIC0_PREOP_HI_BASE_IDX                                                         1
6950 #define regCP_PFP_GDS_ATOMIC1_PREOP_LO                                                                  0x2056
6951 #define regCP_PFP_GDS_ATOMIC1_PREOP_LO_BASE_IDX                                                         1
6952 #define regCP_PFP_GDS_ATOMIC1_PREOP_HI                                                                  0x2057
6953 #define regCP_PFP_GDS_ATOMIC1_PREOP_HI_BASE_IDX                                                         1
6954 #define regCP_APPEND_ADDR_LO                                                                            0x2058
6955 #define regCP_APPEND_ADDR_LO_BASE_IDX                                                                   1
6956 #define regCP_APPEND_ADDR_HI                                                                            0x2059
6957 #define regCP_APPEND_ADDR_HI_BASE_IDX                                                                   1
6958 #define regCP_APPEND_DATA                                                                               0x205a
6959 #define regCP_APPEND_DATA_BASE_IDX                                                                      1
6960 #define regCP_APPEND_DATA_LO                                                                            0x205a
6961 #define regCP_APPEND_DATA_LO_BASE_IDX                                                                   1
6962 #define regCP_APPEND_LAST_CS_FENCE                                                                      0x205b
6963 #define regCP_APPEND_LAST_CS_FENCE_BASE_IDX                                                             1
6964 #define regCP_APPEND_LAST_CS_FENCE_LO                                                                   0x205b
6965 #define regCP_APPEND_LAST_CS_FENCE_LO_BASE_IDX                                                          1
6966 #define regCP_APPEND_LAST_PS_FENCE                                                                      0x205c
6967 #define regCP_APPEND_LAST_PS_FENCE_BASE_IDX                                                             1
6968 #define regCP_APPEND_LAST_PS_FENCE_LO                                                                   0x205c
6969 #define regCP_APPEND_LAST_PS_FENCE_LO_BASE_IDX                                                          1
6970 #define regCP_ATOMIC_PREOP_LO                                                                           0x205d
6971 #define regCP_ATOMIC_PREOP_LO_BASE_IDX                                                                  1
6972 #define regCP_ME_ATOMIC_PREOP_LO                                                                        0x205d
6973 #define regCP_ME_ATOMIC_PREOP_LO_BASE_IDX                                                               1
6974 #define regCP_ATOMIC_PREOP_HI                                                                           0x205e
6975 #define regCP_ATOMIC_PREOP_HI_BASE_IDX                                                                  1
6976 #define regCP_ME_ATOMIC_PREOP_HI                                                                        0x205e
6977 #define regCP_ME_ATOMIC_PREOP_HI_BASE_IDX                                                               1
6978 #define regCP_GDS_ATOMIC0_PREOP_LO                                                                      0x205f
6979 #define regCP_GDS_ATOMIC0_PREOP_LO_BASE_IDX                                                             1
6980 #define regCP_ME_GDS_ATOMIC0_PREOP_LO                                                                   0x205f
6981 #define regCP_ME_GDS_ATOMIC0_PREOP_LO_BASE_IDX                                                          1
6982 #define regCP_GDS_ATOMIC0_PREOP_HI                                                                      0x2060
6983 #define regCP_GDS_ATOMIC0_PREOP_HI_BASE_IDX                                                             1
6984 #define regCP_ME_GDS_ATOMIC0_PREOP_HI                                                                   0x2060
6985 #define regCP_ME_GDS_ATOMIC0_PREOP_HI_BASE_IDX                                                          1
6986 #define regCP_GDS_ATOMIC1_PREOP_LO                                                                      0x2061
6987 #define regCP_GDS_ATOMIC1_PREOP_LO_BASE_IDX                                                             1
6988 #define regCP_ME_GDS_ATOMIC1_PREOP_LO                                                                   0x2061
6989 #define regCP_ME_GDS_ATOMIC1_PREOP_LO_BASE_IDX                                                          1
6990 #define regCP_GDS_ATOMIC1_PREOP_HI                                                                      0x2062
6991 #define regCP_GDS_ATOMIC1_PREOP_HI_BASE_IDX                                                             1
6992 #define regCP_ME_GDS_ATOMIC1_PREOP_HI                                                                   0x2062
6993 #define regCP_ME_GDS_ATOMIC1_PREOP_HI_BASE_IDX                                                          1
6994 #define regCP_ME_MC_WADDR_LO                                                                            0x2069
6995 #define regCP_ME_MC_WADDR_LO_BASE_IDX                                                                   1
6996 #define regCP_ME_MC_WADDR_HI                                                                            0x206a
6997 #define regCP_ME_MC_WADDR_HI_BASE_IDX                                                                   1
6998 #define regCP_ME_MC_WDATA_LO                                                                            0x206b
6999 #define regCP_ME_MC_WDATA_LO_BASE_IDX                                                                   1
7000 #define regCP_ME_MC_WDATA_HI                                                                            0x206c
7001 #define regCP_ME_MC_WDATA_HI_BASE_IDX                                                                   1
7002 #define regCP_ME_MC_RADDR_LO                                                                            0x206d
7003 #define regCP_ME_MC_RADDR_LO_BASE_IDX                                                                   1
7004 #define regCP_ME_MC_RADDR_HI                                                                            0x206e
7005 #define regCP_ME_MC_RADDR_HI_BASE_IDX                                                                   1
7006 #define regCP_SEM_WAIT_TIMER                                                                            0x206f
7007 #define regCP_SEM_WAIT_TIMER_BASE_IDX                                                                   1
7008 #define regCP_SIG_SEM_ADDR_LO                                                                           0x2070
7009 #define regCP_SIG_SEM_ADDR_LO_BASE_IDX                                                                  1
7010 #define regCP_SIG_SEM_ADDR_HI                                                                           0x2071
7011 #define regCP_SIG_SEM_ADDR_HI_BASE_IDX                                                                  1
7012 #define regCP_WAIT_REG_MEM_TIMEOUT                                                                      0x2074
7013 #define regCP_WAIT_REG_MEM_TIMEOUT_BASE_IDX                                                             1
7014 #define regCP_WAIT_SEM_ADDR_LO                                                                          0x2075
7015 #define regCP_WAIT_SEM_ADDR_LO_BASE_IDX                                                                 1
7016 #define regCP_WAIT_SEM_ADDR_HI                                                                          0x2076
7017 #define regCP_WAIT_SEM_ADDR_HI_BASE_IDX                                                                 1
7018 #define regCP_DMA_PFP_CONTROL                                                                           0x2077
7019 #define regCP_DMA_PFP_CONTROL_BASE_IDX                                                                  1
7020 #define regCP_DMA_ME_CONTROL                                                                            0x2078
7021 #define regCP_DMA_ME_CONTROL_BASE_IDX                                                                   1
7022 #define regCP_DMA_ME_SRC_ADDR                                                                           0x2080
7023 #define regCP_DMA_ME_SRC_ADDR_BASE_IDX                                                                  1
7024 #define regCP_DMA_ME_SRC_ADDR_HI                                                                        0x2081
7025 #define regCP_DMA_ME_SRC_ADDR_HI_BASE_IDX                                                               1
7026 #define regCP_DMA_ME_DST_ADDR                                                                           0x2082
7027 #define regCP_DMA_ME_DST_ADDR_BASE_IDX                                                                  1
7028 #define regCP_DMA_ME_DST_ADDR_HI                                                                        0x2083
7029 #define regCP_DMA_ME_DST_ADDR_HI_BASE_IDX                                                               1
7030 #define regCP_DMA_ME_COMMAND                                                                            0x2084
7031 #define regCP_DMA_ME_COMMAND_BASE_IDX                                                                   1
7032 #define regCP_DMA_PFP_SRC_ADDR                                                                          0x2085
7033 #define regCP_DMA_PFP_SRC_ADDR_BASE_IDX                                                                 1
7034 #define regCP_DMA_PFP_SRC_ADDR_HI                                                                       0x2086
7035 #define regCP_DMA_PFP_SRC_ADDR_HI_BASE_IDX                                                              1
7036 #define regCP_DMA_PFP_DST_ADDR                                                                          0x2087
7037 #define regCP_DMA_PFP_DST_ADDR_BASE_IDX                                                                 1
7038 #define regCP_DMA_PFP_DST_ADDR_HI                                                                       0x2088
7039 #define regCP_DMA_PFP_DST_ADDR_HI_BASE_IDX                                                              1
7040 #define regCP_DMA_PFP_COMMAND                                                                           0x2089
7041 #define regCP_DMA_PFP_COMMAND_BASE_IDX                                                                  1
7042 #define regCP_DMA_CNTL                                                                                  0x208a
7043 #define regCP_DMA_CNTL_BASE_IDX                                                                         1
7044 #define regCP_DMA_READ_TAGS                                                                             0x208b
7045 #define regCP_DMA_READ_TAGS_BASE_IDX                                                                    1
7046 #define regCP_PFP_IB_CONTROL                                                                            0x208d
7047 #define regCP_PFP_IB_CONTROL_BASE_IDX                                                                   1
7048 #define regCP_PFP_LOAD_CONTROL                                                                          0x208e
7049 #define regCP_PFP_LOAD_CONTROL_BASE_IDX                                                                 1
7050 #define regCP_SCRATCH_INDEX                                                                             0x208f
7051 #define regCP_SCRATCH_INDEX_BASE_IDX                                                                    1
7052 #define regCP_SCRATCH_DATA                                                                              0x2090
7053 #define regCP_SCRATCH_DATA_BASE_IDX                                                                     1
7054 #define regCP_RB_OFFSET                                                                                 0x2091
7055 #define regCP_RB_OFFSET_BASE_IDX                                                                        1
7056 #define regCP_IB2_OFFSET                                                                                0x2093
7057 #define regCP_IB2_OFFSET_BASE_IDX                                                                       1
7058 #define regCP_IB2_PREAMBLE_BEGIN                                                                        0x2096
7059 #define regCP_IB2_PREAMBLE_BEGIN_BASE_IDX                                                               1
7060 #define regCP_IB2_PREAMBLE_END                                                                          0x2097
7061 #define regCP_IB2_PREAMBLE_END_BASE_IDX                                                                 1
7062 #define regCP_DMA_ME_CMD_ADDR_LO                                                                        0x209c
7063 #define regCP_DMA_ME_CMD_ADDR_LO_BASE_IDX                                                               1
7064 #define regCP_DMA_ME_CMD_ADDR_HI                                                                        0x209d
7065 #define regCP_DMA_ME_CMD_ADDR_HI_BASE_IDX                                                               1
7066 #define regCP_DMA_PFP_CMD_ADDR_LO                                                                       0x209e
7067 #define regCP_DMA_PFP_CMD_ADDR_LO_BASE_IDX                                                              1
7068 #define regCP_DMA_PFP_CMD_ADDR_HI                                                                       0x209f
7069 #define regCP_DMA_PFP_CMD_ADDR_HI_BASE_IDX                                                              1
7070 #define regCP_APPEND_CMD_ADDR_LO                                                                        0x20a0
7071 #define regCP_APPEND_CMD_ADDR_LO_BASE_IDX                                                               1
7072 #define regCP_APPEND_CMD_ADDR_HI                                                                        0x20a1
7073 #define regCP_APPEND_CMD_ADDR_HI_BASE_IDX                                                               1
7074 #define regUCONFIG_RESERVED_REG0                                                                        0x20a2
7075 #define regUCONFIG_RESERVED_REG0_BASE_IDX                                                               1
7076 #define regUCONFIG_RESERVED_REG1                                                                        0x20a3
7077 #define regUCONFIG_RESERVED_REG1_BASE_IDX                                                               1
7078 #define regCP_PA_MSPRIM_COUNT_LO                                                                        0x20a4
7079 #define regCP_PA_MSPRIM_COUNT_LO_BASE_IDX                                                               1
7080 #define regCP_PA_MSPRIM_COUNT_HI                                                                        0x20a5
7081 #define regCP_PA_MSPRIM_COUNT_HI_BASE_IDX                                                               1
7082 #define regCP_GE_MSINVOC_COUNT_LO                                                                       0x20a6
7083 #define regCP_GE_MSINVOC_COUNT_LO_BASE_IDX                                                              1
7084 #define regCP_GE_MSINVOC_COUNT_HI                                                                       0x20a7
7085 #define regCP_GE_MSINVOC_COUNT_HI_BASE_IDX                                                              1
7086 #define regCP_IB2_CMD_BUFSZ                                                                             0x20c1
7087 #define regCP_IB2_CMD_BUFSZ_BASE_IDX                                                                    1
7088 #define regCP_ST_CMD_BUFSZ                                                                              0x20c2
7089 #define regCP_ST_CMD_BUFSZ_BASE_IDX                                                                     1
7090 #define regCP_IB2_BASE_LO                                                                               0x20cf
7091 #define regCP_IB2_BASE_LO_BASE_IDX                                                                      1
7092 #define regCP_IB2_BASE_HI                                                                               0x20d0
7093 #define regCP_IB2_BASE_HI_BASE_IDX                                                                      1
7094 #define regCP_IB2_BUFSZ                                                                                 0x20d1
7095 #define regCP_IB2_BUFSZ_BASE_IDX                                                                        1
7096 #define regCP_ST_BASE_LO                                                                                0x20d2
7097 #define regCP_ST_BASE_LO_BASE_IDX                                                                       1
7098 #define regCP_ST_BASE_HI                                                                                0x20d3
7099 #define regCP_ST_BASE_HI_BASE_IDX                                                                       1
7100 #define regCP_ST_BUFSZ                                                                                  0x20d4
7101 #define regCP_ST_BUFSZ_BASE_IDX                                                                         1
7102 #define regCP_EOP_DONE_EVENT_CNTL                                                                       0x20d5
7103 #define regCP_EOP_DONE_EVENT_CNTL_BASE_IDX                                                              1
7104 #define regCP_EOP_DONE_DATA_CNTL                                                                        0x20d6
7105 #define regCP_EOP_DONE_DATA_CNTL_BASE_IDX                                                               1
7106 #define regCP_EOP_DONE_CNTX_ID                                                                          0x20d7
7107 #define regCP_EOP_DONE_CNTX_ID_BASE_IDX                                                                 1
7108 #define regCP_DB_BASE_LO                                                                                0x20d8
7109 #define regCP_DB_BASE_LO_BASE_IDX                                                                       1
7110 #define regCP_DB_BASE_HI                                                                                0x20d9
7111 #define regCP_DB_BASE_HI_BASE_IDX                                                                       1
7112 #define regCP_DB_BUFSZ                                                                                  0x20da
7113 #define regCP_DB_BUFSZ_BASE_IDX                                                                         1
7114 #define regCP_DB_CMD_BUFSZ                                                                              0x20db
7115 #define regCP_DB_CMD_BUFSZ_BASE_IDX                                                                     1
7116 #define regCP_PFP_COMPLETION_STATUS                                                                     0x20ec
7117 #define regCP_PFP_COMPLETION_STATUS_BASE_IDX                                                            1
7118 #define regCP_PRED_NOT_VISIBLE                                                                          0x20ee
7119 #define regCP_PRED_NOT_VISIBLE_BASE_IDX                                                                 1
7120 #define regCP_PFP_METADATA_BASE_ADDR                                                                    0x20f0
7121 #define regCP_PFP_METADATA_BASE_ADDR_BASE_IDX                                                           1
7122 #define regCP_PFP_METADATA_BASE_ADDR_HI                                                                 0x20f1
7123 #define regCP_PFP_METADATA_BASE_ADDR_HI_BASE_IDX                                                        1
7124 #define regCP_DRAW_INDX_INDR_ADDR                                                                       0x20f4
7125 #define regCP_DRAW_INDX_INDR_ADDR_BASE_IDX                                                              1
7126 #define regCP_DRAW_INDX_INDR_ADDR_HI                                                                    0x20f5
7127 #define regCP_DRAW_INDX_INDR_ADDR_HI_BASE_IDX                                                           1
7128 #define regCP_DISPATCH_INDR_ADDR                                                                        0x20f6
7129 #define regCP_DISPATCH_INDR_ADDR_BASE_IDX                                                               1
7130 #define regCP_DISPATCH_INDR_ADDR_HI                                                                     0x20f7
7131 #define regCP_DISPATCH_INDR_ADDR_HI_BASE_IDX                                                            1
7132 #define regCP_INDEX_BASE_ADDR                                                                           0x20f8
7133 #define regCP_INDEX_BASE_ADDR_BASE_IDX                                                                  1
7134 #define regCP_INDEX_BASE_ADDR_HI                                                                        0x20f9
7135 #define regCP_INDEX_BASE_ADDR_HI_BASE_IDX                                                               1
7136 #define regCP_INDEX_TYPE                                                                                0x20fa
7137 #define regCP_INDEX_TYPE_BASE_IDX                                                                       1
7138 #define regCP_GDS_BKUP_ADDR                                                                             0x20fb
7139 #define regCP_GDS_BKUP_ADDR_BASE_IDX                                                                    1
7140 #define regCP_GDS_BKUP_ADDR_HI                                                                          0x20fc
7141 #define regCP_GDS_BKUP_ADDR_HI_BASE_IDX                                                                 1
7142 #define regCP_SAMPLE_STATUS                                                                             0x20fd
7143 #define regCP_SAMPLE_STATUS_BASE_IDX                                                                    1
7144 #define regCP_ME_COHER_CNTL                                                                             0x20fe
7145 #define regCP_ME_COHER_CNTL_BASE_IDX                                                                    1
7146 #define regCP_ME_COHER_SIZE                                                                             0x20ff
7147 #define regCP_ME_COHER_SIZE_BASE_IDX                                                                    1
7148 #define regCP_ME_COHER_SIZE_HI                                                                          0x2100
7149 #define regCP_ME_COHER_SIZE_HI_BASE_IDX                                                                 1
7150 #define regCP_ME_COHER_BASE                                                                             0x2101
7151 #define regCP_ME_COHER_BASE_BASE_IDX                                                                    1
7152 #define regCP_ME_COHER_BASE_HI                                                                          0x2102
7153 #define regCP_ME_COHER_BASE_HI_BASE_IDX                                                                 1
7154 #define regCP_ME_COHER_STATUS                                                                           0x2103
7155 #define regCP_ME_COHER_STATUS_BASE_IDX                                                                  1
7156 #define regRLC_GPM_PERF_COUNT_0                                                                         0x2140
7157 #define regRLC_GPM_PERF_COUNT_0_BASE_IDX                                                                1
7158 #define regRLC_GPM_PERF_COUNT_1                                                                         0x2141
7159 #define regRLC_GPM_PERF_COUNT_1_BASE_IDX                                                                1
7160 #define regGRBM_GFX_INDEX                                                                               0x2200
7161 #define regGRBM_GFX_INDEX_BASE_IDX                                                                      1
7162 #define regVGT_PRIMITIVE_TYPE                                                                           0x2242
7163 #define regVGT_PRIMITIVE_TYPE_BASE_IDX                                                                  1
7164 #define regVGT_INDEX_TYPE                                                                               0x2243
7165 #define regVGT_INDEX_TYPE_BASE_IDX                                                                      1
7166 #define regGE_MIN_VTX_INDX                                                                              0x2249
7167 #define regGE_MIN_VTX_INDX_BASE_IDX                                                                     1
7168 #define regGE_INDX_OFFSET                                                                               0x224a
7169 #define regGE_INDX_OFFSET_BASE_IDX                                                                      1
7170 #define regGE_MULTI_PRIM_IB_RESET_EN                                                                    0x224b
7171 #define regGE_MULTI_PRIM_IB_RESET_EN_BASE_IDX                                                           1
7172 #define regVGT_NUM_INDICES                                                                              0x224c
7173 #define regVGT_NUM_INDICES_BASE_IDX                                                                     1
7174 #define regVGT_NUM_INSTANCES                                                                            0x224d
7175 #define regVGT_NUM_INSTANCES_BASE_IDX                                                                   1
7176 #define regVGT_TF_RING_SIZE                                                                             0x224e
7177 #define regVGT_TF_RING_SIZE_BASE_IDX                                                                    1
7178 #define regVGT_HS_OFFCHIP_PARAM                                                                         0x224f
7179 #define regVGT_HS_OFFCHIP_PARAM_BASE_IDX                                                                1
7180 #define regVGT_TF_MEMORY_BASE                                                                           0x2250
7181 #define regVGT_TF_MEMORY_BASE_BASE_IDX                                                                  1
7182 #define regGE_MAX_VTX_INDX                                                                              0x2259
7183 #define regGE_MAX_VTX_INDX_BASE_IDX                                                                     1
7184 #define regVGT_INSTANCE_BASE_ID                                                                         0x225a
7185 #define regVGT_INSTANCE_BASE_ID_BASE_IDX                                                                1
7186 #define regGE_CNTL                                                                                      0x225b
7187 #define regGE_CNTL_BASE_IDX                                                                             1
7188 #define regGE_USER_VGPR1                                                                                0x225c
7189 #define regGE_USER_VGPR1_BASE_IDX                                                                       1
7190 #define regGE_USER_VGPR2                                                                                0x225d
7191 #define regGE_USER_VGPR2_BASE_IDX                                                                       1
7192 #define regGE_USER_VGPR3                                                                                0x225e
7193 #define regGE_USER_VGPR3_BASE_IDX                                                                       1
7194 #define regGE_STEREO_CNTL                                                                               0x225f
7195 #define regGE_STEREO_CNTL_BASE_IDX                                                                      1
7196 #define regGE_PC_ALLOC                                                                                  0x2260
7197 #define regGE_PC_ALLOC_BASE_IDX                                                                         1
7198 #define regVGT_TF_MEMORY_BASE_HI                                                                        0x2261
7199 #define regVGT_TF_MEMORY_BASE_HI_BASE_IDX                                                               1
7200 #define regGE_USER_VGPR_EN                                                                              0x2262
7201 #define regGE_USER_VGPR_EN_BASE_IDX                                                                     1
7202 #define regGE_GS_FAST_LAUNCH_WG_DIM                                                                     0x2264
7203 #define regGE_GS_FAST_LAUNCH_WG_DIM_BASE_IDX                                                            1
7204 #define regGE_GS_FAST_LAUNCH_WG_DIM_1                                                                   0x2265
7205 #define regGE_GS_FAST_LAUNCH_WG_DIM_1_BASE_IDX                                                          1
7206 #define regVGT_GS_OUT_PRIM_TYPE                                                                         0x2266
7207 #define regVGT_GS_OUT_PRIM_TYPE_BASE_IDX                                                                1
7208 #define regPA_SU_LINE_STIPPLE_VALUE                                                                     0x2280
7209 #define regPA_SU_LINE_STIPPLE_VALUE_BASE_IDX                                                            1
7210 #define regPA_SC_LINE_STIPPLE_STATE                                                                     0x2281
7211 #define regPA_SC_LINE_STIPPLE_STATE_BASE_IDX                                                            1
7212 #define regPA_SC_SCREEN_EXTENT_MIN_0                                                                    0x2284
7213 #define regPA_SC_SCREEN_EXTENT_MIN_0_BASE_IDX                                                           1
7214 #define regPA_SC_SCREEN_EXTENT_MAX_0                                                                    0x2285
7215 #define regPA_SC_SCREEN_EXTENT_MAX_0_BASE_IDX                                                           1
7216 #define regPA_SC_SCREEN_EXTENT_MIN_1                                                                    0x2286
7217 #define regPA_SC_SCREEN_EXTENT_MIN_1_BASE_IDX                                                           1
7218 #define regPA_SC_SCREEN_EXTENT_MAX_1                                                                    0x228b
7219 #define regPA_SC_SCREEN_EXTENT_MAX_1_BASE_IDX                                                           1
7220 #define regPA_SC_P3D_TRAP_SCREEN_HV_EN                                                                  0x22a0
7221 #define regPA_SC_P3D_TRAP_SCREEN_HV_EN_BASE_IDX                                                         1
7222 #define regPA_SC_P3D_TRAP_SCREEN_H                                                                      0x22a1
7223 #define regPA_SC_P3D_TRAP_SCREEN_H_BASE_IDX                                                             1
7224 #define regPA_SC_P3D_TRAP_SCREEN_V                                                                      0x22a2
7225 #define regPA_SC_P3D_TRAP_SCREEN_V_BASE_IDX                                                             1
7226 #define regPA_SC_P3D_TRAP_SCREEN_OCCURRENCE                                                             0x22a3
7227 #define regPA_SC_P3D_TRAP_SCREEN_OCCURRENCE_BASE_IDX                                                    1
7228 #define regPA_SC_P3D_TRAP_SCREEN_COUNT                                                                  0x22a4
7229 #define regPA_SC_P3D_TRAP_SCREEN_COUNT_BASE_IDX                                                         1
7230 #define regPA_SC_HP3D_TRAP_SCREEN_HV_EN                                                                 0x22a8
7231 #define regPA_SC_HP3D_TRAP_SCREEN_HV_EN_BASE_IDX                                                        1
7232 #define regPA_SC_HP3D_TRAP_SCREEN_H                                                                     0x22a9
7233 #define regPA_SC_HP3D_TRAP_SCREEN_H_BASE_IDX                                                            1
7234 #define regPA_SC_HP3D_TRAP_SCREEN_V                                                                     0x22aa
7235 #define regPA_SC_HP3D_TRAP_SCREEN_V_BASE_IDX                                                            1
7236 #define regPA_SC_HP3D_TRAP_SCREEN_OCCURRENCE                                                            0x22ab
7237 #define regPA_SC_HP3D_TRAP_SCREEN_OCCURRENCE_BASE_IDX                                                   1
7238 #define regPA_SC_HP3D_TRAP_SCREEN_COUNT                                                                 0x22ac
7239 #define regPA_SC_HP3D_TRAP_SCREEN_COUNT_BASE_IDX                                                        1
7240 #define regPA_SC_TRAP_SCREEN_HV_EN                                                                      0x22b0
7241 #define regPA_SC_TRAP_SCREEN_HV_EN_BASE_IDX                                                             1
7242 #define regPA_SC_TRAP_SCREEN_H                                                                          0x22b1
7243 #define regPA_SC_TRAP_SCREEN_H_BASE_IDX                                                                 1
7244 #define regPA_SC_TRAP_SCREEN_V                                                                          0x22b2
7245 #define regPA_SC_TRAP_SCREEN_V_BASE_IDX                                                                 1
7246 #define regPA_SC_TRAP_SCREEN_OCCURRENCE                                                                 0x22b3
7247 #define regPA_SC_TRAP_SCREEN_OCCURRENCE_BASE_IDX                                                        1
7248 #define regPA_SC_TRAP_SCREEN_COUNT                                                                      0x22b4
7249 #define regPA_SC_TRAP_SCREEN_COUNT_BASE_IDX                                                             1
7250 #define regSQ_THREAD_TRACE_USERDATA_0                                                                   0x2340
7251 #define regSQ_THREAD_TRACE_USERDATA_0_BASE_IDX                                                          1
7252 #define regSQ_THREAD_TRACE_USERDATA_1                                                                   0x2341
7253 #define regSQ_THREAD_TRACE_USERDATA_1_BASE_IDX                                                          1
7254 #define regSQ_THREAD_TRACE_USERDATA_2                                                                   0x2342
7255 #define regSQ_THREAD_TRACE_USERDATA_2_BASE_IDX                                                          1
7256 #define regSQ_THREAD_TRACE_USERDATA_3                                                                   0x2343
7257 #define regSQ_THREAD_TRACE_USERDATA_3_BASE_IDX                                                          1
7258 #define regSQ_THREAD_TRACE_USERDATA_4                                                                   0x2344
7259 #define regSQ_THREAD_TRACE_USERDATA_4_BASE_IDX                                                          1
7260 #define regSQ_THREAD_TRACE_USERDATA_5                                                                   0x2345
7261 #define regSQ_THREAD_TRACE_USERDATA_5_BASE_IDX                                                          1
7262 #define regSQ_THREAD_TRACE_USERDATA_6                                                                   0x2346
7263 #define regSQ_THREAD_TRACE_USERDATA_6_BASE_IDX                                                          1
7264 #define regSQ_THREAD_TRACE_USERDATA_7                                                                   0x2347
7265 #define regSQ_THREAD_TRACE_USERDATA_7_BASE_IDX                                                          1
7266 #define regSQC_CACHES                                                                                   0x2348
7267 #define regSQC_CACHES_BASE_IDX                                                                          1
7268 #define regTA_CS_BC_BASE_ADDR                                                                           0x2380
7269 #define regTA_CS_BC_BASE_ADDR_BASE_IDX                                                                  1
7270 #define regTA_CS_BC_BASE_ADDR_HI                                                                        0x2381
7271 #define regTA_CS_BC_BASE_ADDR_HI_BASE_IDX                                                               1
7272 #define regDB_OCCLUSION_COUNT0_LOW                                                                      0x23c0
7273 #define regDB_OCCLUSION_COUNT0_LOW_BASE_IDX                                                             1
7274 #define regDB_OCCLUSION_COUNT0_HI                                                                       0x23c1
7275 #define regDB_OCCLUSION_COUNT0_HI_BASE_IDX                                                              1
7276 #define regDB_OCCLUSION_COUNT1_LOW                                                                      0x23c2
7277 #define regDB_OCCLUSION_COUNT1_LOW_BASE_IDX                                                             1
7278 #define regDB_OCCLUSION_COUNT1_HI                                                                       0x23c3
7279 #define regDB_OCCLUSION_COUNT1_HI_BASE_IDX                                                              1
7280 #define regDB_OCCLUSION_COUNT2_LOW                                                                      0x23c4
7281 #define regDB_OCCLUSION_COUNT2_LOW_BASE_IDX                                                             1
7282 #define regDB_OCCLUSION_COUNT2_HI                                                                       0x23c5
7283 #define regDB_OCCLUSION_COUNT2_HI_BASE_IDX                                                              1
7284 #define regDB_OCCLUSION_COUNT3_LOW                                                                      0x23c6
7285 #define regDB_OCCLUSION_COUNT3_LOW_BASE_IDX                                                             1
7286 #define regDB_OCCLUSION_COUNT3_HI                                                                       0x23c7
7287 #define regDB_OCCLUSION_COUNT3_HI_BASE_IDX                                                              1
7288 #define regGDS_RD_ADDR                                                                                  0x2400
7289 #define regGDS_RD_ADDR_BASE_IDX                                                                         1
7290 #define regGDS_RD_DATA                                                                                  0x2401
7291 #define regGDS_RD_DATA_BASE_IDX                                                                         1
7292 #define regGDS_RD_BURST_ADDR                                                                            0x2402
7293 #define regGDS_RD_BURST_ADDR_BASE_IDX                                                                   1
7294 #define regGDS_RD_BURST_COUNT                                                                           0x2403
7295 #define regGDS_RD_BURST_COUNT_BASE_IDX                                                                  1
7296 #define regGDS_RD_BURST_DATA                                                                            0x2404
7297 #define regGDS_RD_BURST_DATA_BASE_IDX                                                                   1
7298 #define regGDS_WR_ADDR                                                                                  0x2405
7299 #define regGDS_WR_ADDR_BASE_IDX                                                                         1
7300 #define regGDS_WR_DATA                                                                                  0x2406
7301 #define regGDS_WR_DATA_BASE_IDX                                                                         1
7302 #define regGDS_WR_BURST_ADDR                                                                            0x2407
7303 #define regGDS_WR_BURST_ADDR_BASE_IDX                                                                   1
7304 #define regGDS_WR_BURST_DATA                                                                            0x2408
7305 #define regGDS_WR_BURST_DATA_BASE_IDX                                                                   1
7306 #define regGDS_WRITE_COMPLETE                                                                           0x2409
7307 #define regGDS_WRITE_COMPLETE_BASE_IDX                                                                  1
7308 #define regGDS_ATOM_CNTL                                                                                0x240a
7309 #define regGDS_ATOM_CNTL_BASE_IDX                                                                       1
7310 #define regGDS_ATOM_COMPLETE                                                                            0x240b
7311 #define regGDS_ATOM_COMPLETE_BASE_IDX                                                                   1
7312 #define regGDS_ATOM_BASE                                                                                0x240c
7313 #define regGDS_ATOM_BASE_BASE_IDX                                                                       1
7314 #define regGDS_ATOM_SIZE                                                                                0x240d
7315 #define regGDS_ATOM_SIZE_BASE_IDX                                                                       1
7316 #define regGDS_ATOM_OFFSET0                                                                             0x240e
7317 #define regGDS_ATOM_OFFSET0_BASE_IDX                                                                    1
7318 #define regGDS_ATOM_OFFSET1                                                                             0x240f
7319 #define regGDS_ATOM_OFFSET1_BASE_IDX                                                                    1
7320 #define regGDS_ATOM_DST                                                                                 0x2410
7321 #define regGDS_ATOM_DST_BASE_IDX                                                                        1
7322 #define regGDS_ATOM_OP                                                                                  0x2411
7323 #define regGDS_ATOM_OP_BASE_IDX                                                                         1
7324 #define regGDS_ATOM_SRC0                                                                                0x2412
7325 #define regGDS_ATOM_SRC0_BASE_IDX                                                                       1
7326 #define regGDS_ATOM_SRC0_U                                                                              0x2413
7327 #define regGDS_ATOM_SRC0_U_BASE_IDX                                                                     1
7328 #define regGDS_ATOM_SRC1                                                                                0x2414
7329 #define regGDS_ATOM_SRC1_BASE_IDX                                                                       1
7330 #define regGDS_ATOM_SRC1_U                                                                              0x2415
7331 #define regGDS_ATOM_SRC1_U_BASE_IDX                                                                     1
7332 #define regGDS_ATOM_READ0                                                                               0x2416
7333 #define regGDS_ATOM_READ0_BASE_IDX                                                                      1
7334 #define regGDS_ATOM_READ0_U                                                                             0x2417
7335 #define regGDS_ATOM_READ0_U_BASE_IDX                                                                    1
7336 #define regGDS_ATOM_READ1                                                                               0x2418
7337 #define regGDS_ATOM_READ1_BASE_IDX                                                                      1
7338 #define regGDS_ATOM_READ1_U                                                                             0x2419
7339 #define regGDS_ATOM_READ1_U_BASE_IDX                                                                    1
7340 #define regGDS_GWS_RESOURCE_CNTL                                                                        0x241a
7341 #define regGDS_GWS_RESOURCE_CNTL_BASE_IDX                                                               1
7342 #define regGDS_GWS_RESOURCE                                                                             0x241b
7343 #define regGDS_GWS_RESOURCE_BASE_IDX                                                                    1
7344 #define regGDS_GWS_RESOURCE_CNT                                                                         0x241c
7345 #define regGDS_GWS_RESOURCE_CNT_BASE_IDX                                                                1
7346 #define regGDS_OA_CNTL                                                                                  0x241d
7347 #define regGDS_OA_CNTL_BASE_IDX                                                                         1
7348 #define regGDS_OA_COUNTER                                                                               0x241e
7349 #define regGDS_OA_COUNTER_BASE_IDX                                                                      1
7350 #define regGDS_OA_ADDRESS                                                                               0x241f
7351 #define regGDS_OA_ADDRESS_BASE_IDX                                                                      1
7352 #define regGDS_OA_INCDEC                                                                                0x2420
7353 #define regGDS_OA_INCDEC_BASE_IDX                                                                       1
7354 #define regGDS_OA_RING_SIZE                                                                             0x2421
7355 #define regGDS_OA_RING_SIZE_BASE_IDX                                                                    1
7356 #define regGDS_STRMOUT_DWORDS_WRITTEN_0                                                                 0x2422
7357 #define regGDS_STRMOUT_DWORDS_WRITTEN_0_BASE_IDX                                                        1
7358 #define regGDS_STRMOUT_DWORDS_WRITTEN_1                                                                 0x2423
7359 #define regGDS_STRMOUT_DWORDS_WRITTEN_1_BASE_IDX                                                        1
7360 #define regGDS_STRMOUT_DWORDS_WRITTEN_2                                                                 0x2424
7361 #define regGDS_STRMOUT_DWORDS_WRITTEN_2_BASE_IDX                                                        1
7362 #define regGDS_STRMOUT_DWORDS_WRITTEN_3                                                                 0x2425
7363 #define regGDS_STRMOUT_DWORDS_WRITTEN_3_BASE_IDX                                                        1
7364 #define regGDS_GS_0                                                                                     0x2426
7365 #define regGDS_GS_0_BASE_IDX                                                                            1
7366 #define regGDS_GS_1                                                                                     0x2427
7367 #define regGDS_GS_1_BASE_IDX                                                                            1
7368 #define regGDS_GS_2                                                                                     0x2428
7369 #define regGDS_GS_2_BASE_IDX                                                                            1
7370 #define regGDS_GS_3                                                                                     0x2429
7371 #define regGDS_GS_3_BASE_IDX                                                                            1
7372 #define regGDS_STRMOUT_PRIMS_NEEDED_0_LO                                                                0x242a
7373 #define regGDS_STRMOUT_PRIMS_NEEDED_0_LO_BASE_IDX                                                       1
7374 #define regGDS_STRMOUT_PRIMS_NEEDED_0_HI                                                                0x242b
7375 #define regGDS_STRMOUT_PRIMS_NEEDED_0_HI_BASE_IDX                                                       1
7376 #define regGDS_STRMOUT_PRIMS_WRITTEN_0_LO                                                               0x242c
7377 #define regGDS_STRMOUT_PRIMS_WRITTEN_0_LO_BASE_IDX                                                      1
7378 #define regGDS_STRMOUT_PRIMS_WRITTEN_0_HI                                                               0x242d
7379 #define regGDS_STRMOUT_PRIMS_WRITTEN_0_HI_BASE_IDX                                                      1
7380 #define regGDS_STRMOUT_PRIMS_NEEDED_1_LO                                                                0x242e
7381 #define regGDS_STRMOUT_PRIMS_NEEDED_1_LO_BASE_IDX                                                       1
7382 #define regGDS_STRMOUT_PRIMS_NEEDED_1_HI                                                                0x242f
7383 #define regGDS_STRMOUT_PRIMS_NEEDED_1_HI_BASE_IDX                                                       1
7384 #define regGDS_STRMOUT_PRIMS_WRITTEN_1_LO                                                               0x2430
7385 #define regGDS_STRMOUT_PRIMS_WRITTEN_1_LO_BASE_IDX                                                      1
7386 #define regGDS_STRMOUT_PRIMS_WRITTEN_1_HI                                                               0x2431
7387 #define regGDS_STRMOUT_PRIMS_WRITTEN_1_HI_BASE_IDX                                                      1
7388 #define regGDS_STRMOUT_PRIMS_NEEDED_2_LO                                                                0x2432
7389 #define regGDS_STRMOUT_PRIMS_NEEDED_2_LO_BASE_IDX                                                       1
7390 #define regGDS_STRMOUT_PRIMS_NEEDED_2_HI                                                                0x2433
7391 #define regGDS_STRMOUT_PRIMS_NEEDED_2_HI_BASE_IDX                                                       1
7392 #define regGDS_STRMOUT_PRIMS_WRITTEN_2_LO                                                               0x2434
7393 #define regGDS_STRMOUT_PRIMS_WRITTEN_2_LO_BASE_IDX                                                      1
7394 #define regGDS_STRMOUT_PRIMS_WRITTEN_2_HI                                                               0x2435
7395 #define regGDS_STRMOUT_PRIMS_WRITTEN_2_HI_BASE_IDX                                                      1
7396 #define regGDS_STRMOUT_PRIMS_NEEDED_3_LO                                                                0x2436
7397 #define regGDS_STRMOUT_PRIMS_NEEDED_3_LO_BASE_IDX                                                       1
7398 #define regGDS_STRMOUT_PRIMS_NEEDED_3_HI                                                                0x2437
7399 #define regGDS_STRMOUT_PRIMS_NEEDED_3_HI_BASE_IDX                                                       1
7400 #define regGDS_STRMOUT_PRIMS_WRITTEN_3_LO                                                               0x2438
7401 #define regGDS_STRMOUT_PRIMS_WRITTEN_3_LO_BASE_IDX                                                      1
7402 #define regGDS_STRMOUT_PRIMS_WRITTEN_3_HI                                                               0x2439
7403 #define regGDS_STRMOUT_PRIMS_WRITTEN_3_HI_BASE_IDX                                                      1
7404 #define regSPI_CONFIG_CNTL                                                                              0x2440
7405 #define regSPI_CONFIG_CNTL_BASE_IDX                                                                     1
7406 #define regSPI_CONFIG_CNTL_1                                                                            0x2441
7407 #define regSPI_CONFIG_CNTL_1_BASE_IDX                                                                   1
7408 #define regSPI_CONFIG_CNTL_2                                                                            0x2442
7409 #define regSPI_CONFIG_CNTL_2_BASE_IDX                                                                   1
7410 #define regSPI_WAVE_LIMIT_CNTL                                                                          0x2443
7411 #define regSPI_WAVE_LIMIT_CNTL_BASE_IDX                                                                 1
7412 #define regSPI_GS_THROTTLE_CNTL1                                                                        0x2444
7413 #define regSPI_GS_THROTTLE_CNTL1_BASE_IDX                                                               1
7414 #define regSPI_GS_THROTTLE_CNTL2                                                                        0x2445
7415 #define regSPI_GS_THROTTLE_CNTL2_BASE_IDX                                                               1
7416 #define regSPI_ATTRIBUTE_RING_BASE                                                                      0x2446
7417 #define regSPI_ATTRIBUTE_RING_BASE_BASE_IDX                                                             1
7418 #define regSPI_ATTRIBUTE_RING_SIZE                                                                      0x2447
7419 #define regSPI_ATTRIBUTE_RING_SIZE_BASE_IDX                                                             1
7420 
7421 
7422 // addressBlock: gc_cprs64dec
7423 // base address: 0x32000
7424 #define regCP_MES_PRGRM_CNTR_START                                                                      0x2800
7425 #define regCP_MES_PRGRM_CNTR_START_BASE_IDX                                                             1
7426 #define regCP_MES_INTR_ROUTINE_START                                                                    0x2801
7427 #define regCP_MES_INTR_ROUTINE_START_BASE_IDX                                                           1
7428 #define regCP_MES_MTVEC_LO                                                                              0x2801
7429 #define regCP_MES_MTVEC_LO_BASE_IDX                                                                     1
7430 #define regCP_MES_INTR_ROUTINE_START_HI                                                                 0x2802
7431 #define regCP_MES_INTR_ROUTINE_START_HI_BASE_IDX                                                        1
7432 #define regCP_MES_MTVEC_HI                                                                              0x2802
7433 #define regCP_MES_MTVEC_HI_BASE_IDX                                                                     1
7434 #define regCP_MES_CNTL                                                                                  0x2807
7435 #define regCP_MES_CNTL_BASE_IDX                                                                         1
7436 #define regCP_MES_PIPE_PRIORITY_CNTS                                                                    0x2808
7437 #define regCP_MES_PIPE_PRIORITY_CNTS_BASE_IDX                                                           1
7438 #define regCP_MES_PIPE0_PRIORITY                                                                        0x2809
7439 #define regCP_MES_PIPE0_PRIORITY_BASE_IDX                                                               1
7440 #define regCP_MES_PIPE1_PRIORITY                                                                        0x280a
7441 #define regCP_MES_PIPE1_PRIORITY_BASE_IDX                                                               1
7442 #define regCP_MES_PIPE2_PRIORITY                                                                        0x280b
7443 #define regCP_MES_PIPE2_PRIORITY_BASE_IDX                                                               1
7444 #define regCP_MES_PIPE3_PRIORITY                                                                        0x280c
7445 #define regCP_MES_PIPE3_PRIORITY_BASE_IDX                                                               1
7446 #define regCP_MES_HEADER_DUMP                                                                           0x280d
7447 #define regCP_MES_HEADER_DUMP_BASE_IDX                                                                  1
7448 #define regCP_MES_MIE_LO                                                                                0x280e
7449 #define regCP_MES_MIE_LO_BASE_IDX                                                                       1
7450 #define regCP_MES_MIE_HI                                                                                0x280f
7451 #define regCP_MES_MIE_HI_BASE_IDX                                                                       1
7452 #define regCP_MES_INTERRUPT                                                                             0x2810
7453 #define regCP_MES_INTERRUPT_BASE_IDX                                                                    1
7454 #define regCP_MES_SCRATCH_INDEX                                                                         0x2811
7455 #define regCP_MES_SCRATCH_INDEX_BASE_IDX                                                                1
7456 #define regCP_MES_SCRATCH_DATA                                                                          0x2812
7457 #define regCP_MES_SCRATCH_DATA_BASE_IDX                                                                 1
7458 #define regCP_MES_INSTR_PNTR                                                                            0x2813
7459 #define regCP_MES_INSTR_PNTR_BASE_IDX                                                                   1
7460 #define regCP_MES_MSCRATCH_HI                                                                           0x2814
7461 #define regCP_MES_MSCRATCH_HI_BASE_IDX                                                                  1
7462 #define regCP_MES_MSCRATCH_LO                                                                           0x2815
7463 #define regCP_MES_MSCRATCH_LO_BASE_IDX                                                                  1
7464 #define regCP_MES_MSTATUS_LO                                                                            0x2816
7465 #define regCP_MES_MSTATUS_LO_BASE_IDX                                                                   1
7466 #define regCP_MES_MSTATUS_HI                                                                            0x2817
7467 #define regCP_MES_MSTATUS_HI_BASE_IDX                                                                   1
7468 #define regCP_MES_MEPC_LO                                                                               0x2818
7469 #define regCP_MES_MEPC_LO_BASE_IDX                                                                      1
7470 #define regCP_MES_MEPC_HI                                                                               0x2819
7471 #define regCP_MES_MEPC_HI_BASE_IDX                                                                      1
7472 #define regCP_MES_MCAUSE_LO                                                                             0x281a
7473 #define regCP_MES_MCAUSE_LO_BASE_IDX                                                                    1
7474 #define regCP_MES_MCAUSE_HI                                                                             0x281b
7475 #define regCP_MES_MCAUSE_HI_BASE_IDX                                                                    1
7476 #define regCP_MES_MBADADDR_LO                                                                           0x281c
7477 #define regCP_MES_MBADADDR_LO_BASE_IDX                                                                  1
7478 #define regCP_MES_MBADADDR_HI                                                                           0x281d
7479 #define regCP_MES_MBADADDR_HI_BASE_IDX                                                                  1
7480 #define regCP_MES_MIP_LO                                                                                0x281e
7481 #define regCP_MES_MIP_LO_BASE_IDX                                                                       1
7482 #define regCP_MES_MIP_HI                                                                                0x281f
7483 #define regCP_MES_MIP_HI_BASE_IDX                                                                       1
7484 #define regCP_MES_IC_OP_CNTL                                                                            0x2820
7485 #define regCP_MES_IC_OP_CNTL_BASE_IDX                                                                   1
7486 #define regCP_MES_MCYCLE_LO                                                                             0x2826
7487 #define regCP_MES_MCYCLE_LO_BASE_IDX                                                                    1
7488 #define regCP_MES_MCYCLE_HI                                                                             0x2827
7489 #define regCP_MES_MCYCLE_HI_BASE_IDX                                                                    1
7490 #define regCP_MES_MTIME_LO                                                                              0x2828
7491 #define regCP_MES_MTIME_LO_BASE_IDX                                                                     1
7492 #define regCP_MES_MTIME_HI                                                                              0x2829
7493 #define regCP_MES_MTIME_HI_BASE_IDX                                                                     1
7494 #define regCP_MES_MINSTRET_LO                                                                           0x282a
7495 #define regCP_MES_MINSTRET_LO_BASE_IDX                                                                  1
7496 #define regCP_MES_MINSTRET_HI                                                                           0x282b
7497 #define regCP_MES_MINSTRET_HI_BASE_IDX                                                                  1
7498 #define regCP_MES_MISA_LO                                                                               0x282c
7499 #define regCP_MES_MISA_LO_BASE_IDX                                                                      1
7500 #define regCP_MES_MISA_HI                                                                               0x282d
7501 #define regCP_MES_MISA_HI_BASE_IDX                                                                      1
7502 #define regCP_MES_MVENDORID_LO                                                                          0x282e
7503 #define regCP_MES_MVENDORID_LO_BASE_IDX                                                                 1
7504 #define regCP_MES_MVENDORID_HI                                                                          0x282f
7505 #define regCP_MES_MVENDORID_HI_BASE_IDX                                                                 1
7506 #define regCP_MES_MARCHID_LO                                                                            0x2830
7507 #define regCP_MES_MARCHID_LO_BASE_IDX                                                                   1
7508 #define regCP_MES_MARCHID_HI                                                                            0x2831
7509 #define regCP_MES_MARCHID_HI_BASE_IDX                                                                   1
7510 #define regCP_MES_MIMPID_LO                                                                             0x2832
7511 #define regCP_MES_MIMPID_LO_BASE_IDX                                                                    1
7512 #define regCP_MES_MIMPID_HI                                                                             0x2833
7513 #define regCP_MES_MIMPID_HI_BASE_IDX                                                                    1
7514 #define regCP_MES_MHARTID_LO                                                                            0x2834
7515 #define regCP_MES_MHARTID_LO_BASE_IDX                                                                   1
7516 #define regCP_MES_MHARTID_HI                                                                            0x2835
7517 #define regCP_MES_MHARTID_HI_BASE_IDX                                                                   1
7518 #define regCP_MES_DC_BASE_CNTL                                                                          0x2836
7519 #define regCP_MES_DC_BASE_CNTL_BASE_IDX                                                                 1
7520 #define regCP_MES_DC_OP_CNTL                                                                            0x2837
7521 #define regCP_MES_DC_OP_CNTL_BASE_IDX                                                                   1
7522 #define regCP_MES_MTIMECMP_LO                                                                           0x2838
7523 #define regCP_MES_MTIMECMP_LO_BASE_IDX                                                                  1
7524 #define regCP_MES_MTIMECMP_HI                                                                           0x2839
7525 #define regCP_MES_MTIMECMP_HI_BASE_IDX                                                                  1
7526 #define regCP_MES_PROCESS_QUANTUM_PIPE0                                                                 0x283a
7527 #define regCP_MES_PROCESS_QUANTUM_PIPE0_BASE_IDX                                                        1
7528 #define regCP_MES_PROCESS_QUANTUM_PIPE1                                                                 0x283b
7529 #define regCP_MES_PROCESS_QUANTUM_PIPE1_BASE_IDX                                                        1
7530 #define regCP_MES_DOORBELL_CONTROL1                                                                     0x283c
7531 #define regCP_MES_DOORBELL_CONTROL1_BASE_IDX                                                            1
7532 #define regCP_MES_DOORBELL_CONTROL2                                                                     0x283d
7533 #define regCP_MES_DOORBELL_CONTROL2_BASE_IDX                                                            1
7534 #define regCP_MES_DOORBELL_CONTROL3                                                                     0x283e
7535 #define regCP_MES_DOORBELL_CONTROL3_BASE_IDX                                                            1
7536 #define regCP_MES_DOORBELL_CONTROL4                                                                     0x283f
7537 #define regCP_MES_DOORBELL_CONTROL4_BASE_IDX                                                            1
7538 #define regCP_MES_DOORBELL_CONTROL5                                                                     0x2840
7539 #define regCP_MES_DOORBELL_CONTROL5_BASE_IDX                                                            1
7540 #define regCP_MES_DOORBELL_CONTROL6                                                                     0x2841
7541 #define regCP_MES_DOORBELL_CONTROL6_BASE_IDX                                                            1
7542 #define regCP_MES_GP0_LO                                                                                0x2843
7543 #define regCP_MES_GP0_LO_BASE_IDX                                                                       1
7544 #define regCP_MES_GP0_HI                                                                                0x2844
7545 #define regCP_MES_GP0_HI_BASE_IDX                                                                       1
7546 #define regCP_MES_GP1_LO                                                                                0x2845
7547 #define regCP_MES_GP1_LO_BASE_IDX                                                                       1
7548 #define regCP_MES_GP1_HI                                                                                0x2846
7549 #define regCP_MES_GP1_HI_BASE_IDX                                                                       1
7550 #define regCP_MES_GP2_LO                                                                                0x2847
7551 #define regCP_MES_GP2_LO_BASE_IDX                                                                       1
7552 #define regCP_MES_GP2_HI                                                                                0x2848
7553 #define regCP_MES_GP2_HI_BASE_IDX                                                                       1
7554 #define regCP_MES_GP3_LO                                                                                0x2849
7555 #define regCP_MES_GP3_LO_BASE_IDX                                                                       1
7556 #define regCP_MES_GP3_HI                                                                                0x284a
7557 #define regCP_MES_GP3_HI_BASE_IDX                                                                       1
7558 #define regCP_MES_GP4_LO                                                                                0x284b
7559 #define regCP_MES_GP4_LO_BASE_IDX                                                                       1
7560 #define regCP_MES_GP4_HI                                                                                0x284c
7561 #define regCP_MES_GP4_HI_BASE_IDX                                                                       1
7562 #define regCP_MES_GP5_LO                                                                                0x284d
7563 #define regCP_MES_GP5_LO_BASE_IDX                                                                       1
7564 #define regCP_MES_GP5_HI                                                                                0x284e
7565 #define regCP_MES_GP5_HI_BASE_IDX                                                                       1
7566 #define regCP_MES_GP6_LO                                                                                0x284f
7567 #define regCP_MES_GP6_LO_BASE_IDX                                                                       1
7568 #define regCP_MES_GP6_HI                                                                                0x2850
7569 #define regCP_MES_GP6_HI_BASE_IDX                                                                       1
7570 #define regCP_MES_GP7_LO                                                                                0x2851
7571 #define regCP_MES_GP7_LO_BASE_IDX                                                                       1
7572 #define regCP_MES_GP7_HI                                                                                0x2852
7573 #define regCP_MES_GP7_HI_BASE_IDX                                                                       1
7574 #define regCP_MES_GP8_LO                                                                                0x2853
7575 #define regCP_MES_GP8_LO_BASE_IDX                                                                       1
7576 #define regCP_MES_GP8_HI                                                                                0x2854
7577 #define regCP_MES_GP8_HI_BASE_IDX                                                                       1
7578 #define regCP_MES_GP9_LO                                                                                0x2855
7579 #define regCP_MES_GP9_LO_BASE_IDX                                                                       1
7580 #define regCP_MES_GP9_HI                                                                                0x2856
7581 #define regCP_MES_GP9_HI_BASE_IDX                                                                       1
7582 #define regCP_MES_LOCAL_BASE0_LO                                                                        0x2883
7583 #define regCP_MES_LOCAL_BASE0_LO_BASE_IDX                                                               1
7584 #define regCP_MES_LOCAL_BASE0_HI                                                                        0x2884
7585 #define regCP_MES_LOCAL_BASE0_HI_BASE_IDX                                                               1
7586 #define regCP_MES_LOCAL_MASK0_LO                                                                        0x2885
7587 #define regCP_MES_LOCAL_MASK0_LO_BASE_IDX                                                               1
7588 #define regCP_MES_LOCAL_MASK0_HI                                                                        0x2886
7589 #define regCP_MES_LOCAL_MASK0_HI_BASE_IDX                                                               1
7590 #define regCP_MES_LOCAL_APERTURE                                                                        0x2887
7591 #define regCP_MES_LOCAL_APERTURE_BASE_IDX                                                               1
7592 #define regCP_MES_LOCAL_INSTR_BASE_LO                                                                   0x2888
7593 #define regCP_MES_LOCAL_INSTR_BASE_LO_BASE_IDX                                                          1
7594 #define regCP_MES_LOCAL_INSTR_BASE_HI                                                                   0x2889
7595 #define regCP_MES_LOCAL_INSTR_BASE_HI_BASE_IDX                                                          1
7596 #define regCP_MES_LOCAL_INSTR_MASK_LO                                                                   0x288a
7597 #define regCP_MES_LOCAL_INSTR_MASK_LO_BASE_IDX                                                          1
7598 #define regCP_MES_LOCAL_INSTR_MASK_HI                                                                   0x288b
7599 #define regCP_MES_LOCAL_INSTR_MASK_HI_BASE_IDX                                                          1
7600 #define regCP_MES_LOCAL_INSTR_APERTURE                                                                  0x288c
7601 #define regCP_MES_LOCAL_INSTR_APERTURE_BASE_IDX                                                         1
7602 #define regCP_MES_LOCAL_SCRATCH_APERTURE                                                                0x288d
7603 #define regCP_MES_LOCAL_SCRATCH_APERTURE_BASE_IDX                                                       1
7604 #define regCP_MES_LOCAL_SCRATCH_BASE_LO                                                                 0x288e
7605 #define regCP_MES_LOCAL_SCRATCH_BASE_LO_BASE_IDX                                                        1
7606 #define regCP_MES_LOCAL_SCRATCH_BASE_HI                                                                 0x288f
7607 #define regCP_MES_LOCAL_SCRATCH_BASE_HI_BASE_IDX                                                        1
7608 #define regCP_MES_PERFCOUNT_CNTL                                                                        0x2899
7609 #define regCP_MES_PERFCOUNT_CNTL_BASE_IDX                                                               1
7610 #define regCP_MES_PENDING_INTERRUPT                                                                     0x289a
7611 #define regCP_MES_PENDING_INTERRUPT_BASE_IDX                                                            1
7612 #define regCP_MES_PRGRM_CNTR_START_HI                                                                   0x289d
7613 #define regCP_MES_PRGRM_CNTR_START_HI_BASE_IDX                                                          1
7614 #define regCP_MES_INTERRUPT_DATA_16                                                                     0x289f
7615 #define regCP_MES_INTERRUPT_DATA_16_BASE_IDX                                                            1
7616 #define regCP_MES_INTERRUPT_DATA_17                                                                     0x28a0
7617 #define regCP_MES_INTERRUPT_DATA_17_BASE_IDX                                                            1
7618 #define regCP_MES_INTERRUPT_DATA_18                                                                     0x28a1
7619 #define regCP_MES_INTERRUPT_DATA_18_BASE_IDX                                                            1
7620 #define regCP_MES_INTERRUPT_DATA_19                                                                     0x28a2
7621 #define regCP_MES_INTERRUPT_DATA_19_BASE_IDX                                                            1
7622 #define regCP_MES_INTERRUPT_DATA_20                                                                     0x28a3
7623 #define regCP_MES_INTERRUPT_DATA_20_BASE_IDX                                                            1
7624 #define regCP_MES_INTERRUPT_DATA_21                                                                     0x28a4
7625 #define regCP_MES_INTERRUPT_DATA_21_BASE_IDX                                                            1
7626 #define regCP_MES_INTERRUPT_DATA_22                                                                     0x28a5
7627 #define regCP_MES_INTERRUPT_DATA_22_BASE_IDX                                                            1
7628 #define regCP_MES_INTERRUPT_DATA_23                                                                     0x28a6
7629 #define regCP_MES_INTERRUPT_DATA_23_BASE_IDX                                                            1
7630 #define regCP_MES_INTERRUPT_DATA_24                                                                     0x28a7
7631 #define regCP_MES_INTERRUPT_DATA_24_BASE_IDX                                                            1
7632 #define regCP_MES_INTERRUPT_DATA_25                                                                     0x28a8
7633 #define regCP_MES_INTERRUPT_DATA_25_BASE_IDX                                                            1
7634 #define regCP_MES_INTERRUPT_DATA_26                                                                     0x28a9
7635 #define regCP_MES_INTERRUPT_DATA_26_BASE_IDX                                                            1
7636 #define regCP_MES_INTERRUPT_DATA_27                                                                     0x28aa
7637 #define regCP_MES_INTERRUPT_DATA_27_BASE_IDX                                                            1
7638 #define regCP_MES_INTERRUPT_DATA_28                                                                     0x28ab
7639 #define regCP_MES_INTERRUPT_DATA_28_BASE_IDX                                                            1
7640 #define regCP_MES_INTERRUPT_DATA_29                                                                     0x28ac
7641 #define regCP_MES_INTERRUPT_DATA_29_BASE_IDX                                                            1
7642 #define regCP_MES_INTERRUPT_DATA_30                                                                     0x28ad
7643 #define regCP_MES_INTERRUPT_DATA_30_BASE_IDX                                                            1
7644 #define regCP_MES_INTERRUPT_DATA_31                                                                     0x28ae
7645 #define regCP_MES_INTERRUPT_DATA_31_BASE_IDX                                                            1
7646 #define regCP_MES_DC_APERTURE0_BASE                                                                     0x28af
7647 #define regCP_MES_DC_APERTURE0_BASE_BASE_IDX                                                            1
7648 #define regCP_MES_DC_APERTURE0_MASK                                                                     0x28b0
7649 #define regCP_MES_DC_APERTURE0_MASK_BASE_IDX                                                            1
7650 #define regCP_MES_DC_APERTURE0_CNTL                                                                     0x28b1
7651 #define regCP_MES_DC_APERTURE0_CNTL_BASE_IDX                                                            1
7652 #define regCP_MES_DC_APERTURE1_BASE                                                                     0x28b2
7653 #define regCP_MES_DC_APERTURE1_BASE_BASE_IDX                                                            1
7654 #define regCP_MES_DC_APERTURE1_MASK                                                                     0x28b3
7655 #define regCP_MES_DC_APERTURE1_MASK_BASE_IDX                                                            1
7656 #define regCP_MES_DC_APERTURE1_CNTL                                                                     0x28b4
7657 #define regCP_MES_DC_APERTURE1_CNTL_BASE_IDX                                                            1
7658 #define regCP_MES_DC_APERTURE2_BASE                                                                     0x28b5
7659 #define regCP_MES_DC_APERTURE2_BASE_BASE_IDX                                                            1
7660 #define regCP_MES_DC_APERTURE2_MASK                                                                     0x28b6
7661 #define regCP_MES_DC_APERTURE2_MASK_BASE_IDX                                                            1
7662 #define regCP_MES_DC_APERTURE2_CNTL                                                                     0x28b7
7663 #define regCP_MES_DC_APERTURE2_CNTL_BASE_IDX                                                            1
7664 #define regCP_MES_DC_APERTURE3_BASE                                                                     0x28b8
7665 #define regCP_MES_DC_APERTURE3_BASE_BASE_IDX                                                            1
7666 #define regCP_MES_DC_APERTURE3_MASK                                                                     0x28b9
7667 #define regCP_MES_DC_APERTURE3_MASK_BASE_IDX                                                            1
7668 #define regCP_MES_DC_APERTURE3_CNTL                                                                     0x28ba
7669 #define regCP_MES_DC_APERTURE3_CNTL_BASE_IDX                                                            1
7670 #define regCP_MES_DC_APERTURE4_BASE                                                                     0x28bb
7671 #define regCP_MES_DC_APERTURE4_BASE_BASE_IDX                                                            1
7672 #define regCP_MES_DC_APERTURE4_MASK                                                                     0x28bc
7673 #define regCP_MES_DC_APERTURE4_MASK_BASE_IDX                                                            1
7674 #define regCP_MES_DC_APERTURE4_CNTL                                                                     0x28bd
7675 #define regCP_MES_DC_APERTURE4_CNTL_BASE_IDX                                                            1
7676 #define regCP_MES_DC_APERTURE5_BASE                                                                     0x28be
7677 #define regCP_MES_DC_APERTURE5_BASE_BASE_IDX                                                            1
7678 #define regCP_MES_DC_APERTURE5_MASK                                                                     0x28bf
7679 #define regCP_MES_DC_APERTURE5_MASK_BASE_IDX                                                            1
7680 #define regCP_MES_DC_APERTURE5_CNTL                                                                     0x28c0
7681 #define regCP_MES_DC_APERTURE5_CNTL_BASE_IDX                                                            1
7682 #define regCP_MES_DC_APERTURE6_BASE                                                                     0x28c1
7683 #define regCP_MES_DC_APERTURE6_BASE_BASE_IDX                                                            1
7684 #define regCP_MES_DC_APERTURE6_MASK                                                                     0x28c2
7685 #define regCP_MES_DC_APERTURE6_MASK_BASE_IDX                                                            1
7686 #define regCP_MES_DC_APERTURE6_CNTL                                                                     0x28c3
7687 #define regCP_MES_DC_APERTURE6_CNTL_BASE_IDX                                                            1
7688 #define regCP_MES_DC_APERTURE7_BASE                                                                     0x28c4
7689 #define regCP_MES_DC_APERTURE7_BASE_BASE_IDX                                                            1
7690 #define regCP_MES_DC_APERTURE7_MASK                                                                     0x28c5
7691 #define regCP_MES_DC_APERTURE7_MASK_BASE_IDX                                                            1
7692 #define regCP_MES_DC_APERTURE7_CNTL                                                                     0x28c6
7693 #define regCP_MES_DC_APERTURE7_CNTL_BASE_IDX                                                            1
7694 #define regCP_MES_DC_APERTURE8_BASE                                                                     0x28c7
7695 #define regCP_MES_DC_APERTURE8_BASE_BASE_IDX                                                            1
7696 #define regCP_MES_DC_APERTURE8_MASK                                                                     0x28c8
7697 #define regCP_MES_DC_APERTURE8_MASK_BASE_IDX                                                            1
7698 #define regCP_MES_DC_APERTURE8_CNTL                                                                     0x28c9
7699 #define regCP_MES_DC_APERTURE8_CNTL_BASE_IDX                                                            1
7700 #define regCP_MES_DC_APERTURE9_BASE                                                                     0x28ca
7701 #define regCP_MES_DC_APERTURE9_BASE_BASE_IDX                                                            1
7702 #define regCP_MES_DC_APERTURE9_MASK                                                                     0x28cb
7703 #define regCP_MES_DC_APERTURE9_MASK_BASE_IDX                                                            1
7704 #define regCP_MES_DC_APERTURE9_CNTL                                                                     0x28cc
7705 #define regCP_MES_DC_APERTURE9_CNTL_BASE_IDX                                                            1
7706 #define regCP_MES_DC_APERTURE10_BASE                                                                    0x28cd
7707 #define regCP_MES_DC_APERTURE10_BASE_BASE_IDX                                                           1
7708 #define regCP_MES_DC_APERTURE10_MASK                                                                    0x28ce
7709 #define regCP_MES_DC_APERTURE10_MASK_BASE_IDX                                                           1
7710 #define regCP_MES_DC_APERTURE10_CNTL                                                                    0x28cf
7711 #define regCP_MES_DC_APERTURE10_CNTL_BASE_IDX                                                           1
7712 #define regCP_MES_DC_APERTURE11_BASE                                                                    0x28d0
7713 #define regCP_MES_DC_APERTURE11_BASE_BASE_IDX                                                           1
7714 #define regCP_MES_DC_APERTURE11_MASK                                                                    0x28d1
7715 #define regCP_MES_DC_APERTURE11_MASK_BASE_IDX                                                           1
7716 #define regCP_MES_DC_APERTURE11_CNTL                                                                    0x28d2
7717 #define regCP_MES_DC_APERTURE11_CNTL_BASE_IDX                                                           1
7718 #define regCP_MES_DC_APERTURE12_BASE                                                                    0x28d3
7719 #define regCP_MES_DC_APERTURE12_BASE_BASE_IDX                                                           1
7720 #define regCP_MES_DC_APERTURE12_MASK                                                                    0x28d4
7721 #define regCP_MES_DC_APERTURE12_MASK_BASE_IDX                                                           1
7722 #define regCP_MES_DC_APERTURE12_CNTL                                                                    0x28d5
7723 #define regCP_MES_DC_APERTURE12_CNTL_BASE_IDX                                                           1
7724 #define regCP_MES_DC_APERTURE13_BASE                                                                    0x28d6
7725 #define regCP_MES_DC_APERTURE13_BASE_BASE_IDX                                                           1
7726 #define regCP_MES_DC_APERTURE13_MASK                                                                    0x28d7
7727 #define regCP_MES_DC_APERTURE13_MASK_BASE_IDX                                                           1
7728 #define regCP_MES_DC_APERTURE13_CNTL                                                                    0x28d8
7729 #define regCP_MES_DC_APERTURE13_CNTL_BASE_IDX                                                           1
7730 #define regCP_MES_DC_APERTURE14_BASE                                                                    0x28d9
7731 #define regCP_MES_DC_APERTURE14_BASE_BASE_IDX                                                           1
7732 #define regCP_MES_DC_APERTURE14_MASK                                                                    0x28da
7733 #define regCP_MES_DC_APERTURE14_MASK_BASE_IDX                                                           1
7734 #define regCP_MES_DC_APERTURE14_CNTL                                                                    0x28db
7735 #define regCP_MES_DC_APERTURE14_CNTL_BASE_IDX                                                           1
7736 #define regCP_MES_DC_APERTURE15_BASE                                                                    0x28dc
7737 #define regCP_MES_DC_APERTURE15_BASE_BASE_IDX                                                           1
7738 #define regCP_MES_DC_APERTURE15_MASK                                                                    0x28dd
7739 #define regCP_MES_DC_APERTURE15_MASK_BASE_IDX                                                           1
7740 #define regCP_MES_DC_APERTURE15_CNTL                                                                    0x28de
7741 #define regCP_MES_DC_APERTURE15_CNTL_BASE_IDX                                                           1
7742 #define regCP_MEC_RS64_PRGRM_CNTR_START                                                                 0x2900
7743 #define regCP_MEC_RS64_PRGRM_CNTR_START_BASE_IDX                                                        1
7744 #define regCP_MEC_MTVEC_LO                                                                              0x2901
7745 #define regCP_MEC_MTVEC_LO_BASE_IDX                                                                     1
7746 #define regCP_MEC_MTVEC_HI                                                                              0x2902
7747 #define regCP_MEC_MTVEC_HI_BASE_IDX                                                                     1
7748 #define regCP_MEC_ISA_CNTL                                                                              0x2903
7749 #define regCP_MEC_ISA_CNTL_BASE_IDX                                                                     1
7750 #define regCP_MEC_RS64_CNTL                                                                             0x2904
7751 #define regCP_MEC_RS64_CNTL_BASE_IDX                                                                    1
7752 #define regCP_MEC_MIE_LO                                                                                0x2905
7753 #define regCP_MEC_MIE_LO_BASE_IDX                                                                       1
7754 #define regCP_MEC_MIE_HI                                                                                0x2906
7755 #define regCP_MEC_MIE_HI_BASE_IDX                                                                       1
7756 #define regCP_MEC_RS64_INTERRUPT                                                                        0x2907
7757 #define regCP_MEC_RS64_INTERRUPT_BASE_IDX                                                               1
7758 #define regCP_MEC_RS64_INSTR_PNTR                                                                       0x2908
7759 #define regCP_MEC_RS64_INSTR_PNTR_BASE_IDX                                                              1
7760 #define regCP_MEC_MIP_LO                                                                                0x2909
7761 #define regCP_MEC_MIP_LO_BASE_IDX                                                                       1
7762 #define regCP_MEC_MIP_HI                                                                                0x290a
7763 #define regCP_MEC_MIP_HI_BASE_IDX                                                                       1
7764 #define regCP_MEC_DC_BASE_CNTL                                                                          0x290b
7765 #define regCP_MEC_DC_BASE_CNTL_BASE_IDX                                                                 1
7766 #define regCP_MEC_DC_OP_CNTL                                                                            0x290c
7767 #define regCP_MEC_DC_OP_CNTL_BASE_IDX                                                                   1
7768 #define regCP_MEC_MTIMECMP_LO                                                                           0x290d
7769 #define regCP_MEC_MTIMECMP_LO_BASE_IDX                                                                  1
7770 #define regCP_MEC_MTIMECMP_HI                                                                           0x290e
7771 #define regCP_MEC_MTIMECMP_HI_BASE_IDX                                                                  1
7772 #define regCP_MEC_GP0_LO                                                                                0x2910
7773 #define regCP_MEC_GP0_LO_BASE_IDX                                                                       1
7774 #define regCP_MEC_GP0_HI                                                                                0x2911
7775 #define regCP_MEC_GP0_HI_BASE_IDX                                                                       1
7776 #define regCP_MEC_GP1_LO                                                                                0x2912
7777 #define regCP_MEC_GP1_LO_BASE_IDX                                                                       1
7778 #define regCP_MEC_GP1_HI                                                                                0x2913
7779 #define regCP_MEC_GP1_HI_BASE_IDX                                                                       1
7780 #define regCP_MEC_GP2_LO                                                                                0x2914
7781 #define regCP_MEC_GP2_LO_BASE_IDX                                                                       1
7782 #define regCP_MEC_GP2_HI                                                                                0x2915
7783 #define regCP_MEC_GP2_HI_BASE_IDX                                                                       1
7784 #define regCP_MEC_GP3_LO                                                                                0x2916
7785 #define regCP_MEC_GP3_LO_BASE_IDX                                                                       1
7786 #define regCP_MEC_GP3_HI                                                                                0x2917
7787 #define regCP_MEC_GP3_HI_BASE_IDX                                                                       1
7788 #define regCP_MEC_GP4_LO                                                                                0x2918
7789 #define regCP_MEC_GP4_LO_BASE_IDX                                                                       1
7790 #define regCP_MEC_GP4_HI                                                                                0x2919
7791 #define regCP_MEC_GP4_HI_BASE_IDX                                                                       1
7792 #define regCP_MEC_GP5_LO                                                                                0x291a
7793 #define regCP_MEC_GP5_LO_BASE_IDX                                                                       1
7794 #define regCP_MEC_GP5_HI                                                                                0x291b
7795 #define regCP_MEC_GP5_HI_BASE_IDX                                                                       1
7796 #define regCP_MEC_GP6_LO                                                                                0x291c
7797 #define regCP_MEC_GP6_LO_BASE_IDX                                                                       1
7798 #define regCP_MEC_GP6_HI                                                                                0x291d
7799 #define regCP_MEC_GP6_HI_BASE_IDX                                                                       1
7800 #define regCP_MEC_GP7_LO                                                                                0x291e
7801 #define regCP_MEC_GP7_LO_BASE_IDX                                                                       1
7802 #define regCP_MEC_GP7_HI                                                                                0x291f
7803 #define regCP_MEC_GP7_HI_BASE_IDX                                                                       1
7804 #define regCP_MEC_GP8_LO                                                                                0x2920
7805 #define regCP_MEC_GP8_LO_BASE_IDX                                                                       1
7806 #define regCP_MEC_GP8_HI                                                                                0x2921
7807 #define regCP_MEC_GP8_HI_BASE_IDX                                                                       1
7808 #define regCP_MEC_GP9_LO                                                                                0x2922
7809 #define regCP_MEC_GP9_LO_BASE_IDX                                                                       1
7810 #define regCP_MEC_GP9_HI                                                                                0x2923
7811 #define regCP_MEC_GP9_HI_BASE_IDX                                                                       1
7812 #define regCP_MEC_LOCAL_BASE0_LO                                                                        0x2927
7813 #define regCP_MEC_LOCAL_BASE0_LO_BASE_IDX                                                               1
7814 #define regCP_MEC_LOCAL_BASE0_HI                                                                        0x2928
7815 #define regCP_MEC_LOCAL_BASE0_HI_BASE_IDX                                                               1
7816 #define regCP_MEC_LOCAL_MASK0_LO                                                                        0x2929
7817 #define regCP_MEC_LOCAL_MASK0_LO_BASE_IDX                                                               1
7818 #define regCP_MEC_LOCAL_MASK0_HI                                                                        0x292a
7819 #define regCP_MEC_LOCAL_MASK0_HI_BASE_IDX                                                               1
7820 #define regCP_MEC_LOCAL_APERTURE                                                                        0x292b
7821 #define regCP_MEC_LOCAL_APERTURE_BASE_IDX                                                               1
7822 #define regCP_MEC_LOCAL_INSTR_BASE_LO                                                                   0x292c
7823 #define regCP_MEC_LOCAL_INSTR_BASE_LO_BASE_IDX                                                          1
7824 #define regCP_MEC_LOCAL_INSTR_BASE_HI                                                                   0x292d
7825 #define regCP_MEC_LOCAL_INSTR_BASE_HI_BASE_IDX                                                          1
7826 #define regCP_MEC_LOCAL_INSTR_MASK_LO                                                                   0x292e
7827 #define regCP_MEC_LOCAL_INSTR_MASK_LO_BASE_IDX                                                          1
7828 #define regCP_MEC_LOCAL_INSTR_MASK_HI                                                                   0x292f
7829 #define regCP_MEC_LOCAL_INSTR_MASK_HI_BASE_IDX                                                          1
7830 #define regCP_MEC_LOCAL_INSTR_APERTURE                                                                  0x2930
7831 #define regCP_MEC_LOCAL_INSTR_APERTURE_BASE_IDX                                                         1
7832 #define regCP_MEC_LOCAL_SCRATCH_APERTURE                                                                0x2931
7833 #define regCP_MEC_LOCAL_SCRATCH_APERTURE_BASE_IDX                                                       1
7834 #define regCP_MEC_LOCAL_SCRATCH_BASE_LO                                                                 0x2932
7835 #define regCP_MEC_LOCAL_SCRATCH_BASE_LO_BASE_IDX                                                        1
7836 #define regCP_MEC_LOCAL_SCRATCH_BASE_HI                                                                 0x2933
7837 #define regCP_MEC_LOCAL_SCRATCH_BASE_HI_BASE_IDX                                                        1
7838 #define regCP_MEC_RS64_PERFCOUNT_CNTL                                                                   0x2934
7839 #define regCP_MEC_RS64_PERFCOUNT_CNTL_BASE_IDX                                                          1
7840 #define regCP_MEC_RS64_PENDING_INTERRUPT                                                                0x2935
7841 #define regCP_MEC_RS64_PENDING_INTERRUPT_BASE_IDX                                                       1
7842 #define regCP_MEC_RS64_PRGRM_CNTR_START_HI                                                              0x2938
7843 #define regCP_MEC_RS64_PRGRM_CNTR_START_HI_BASE_IDX                                                     1
7844 #define regCP_MEC_RS64_INTERRUPT_DATA_16                                                                0x293a
7845 #define regCP_MEC_RS64_INTERRUPT_DATA_16_BASE_IDX                                                       1
7846 #define regCP_MEC_RS64_INTERRUPT_DATA_17                                                                0x293b
7847 #define regCP_MEC_RS64_INTERRUPT_DATA_17_BASE_IDX                                                       1
7848 #define regCP_MEC_RS64_INTERRUPT_DATA_18                                                                0x293c
7849 #define regCP_MEC_RS64_INTERRUPT_DATA_18_BASE_IDX                                                       1
7850 #define regCP_MEC_RS64_INTERRUPT_DATA_19                                                                0x293d
7851 #define regCP_MEC_RS64_INTERRUPT_DATA_19_BASE_IDX                                                       1
7852 #define regCP_MEC_RS64_INTERRUPT_DATA_20                                                                0x293e
7853 #define regCP_MEC_RS64_INTERRUPT_DATA_20_BASE_IDX                                                       1
7854 #define regCP_MEC_RS64_INTERRUPT_DATA_21                                                                0x293f
7855 #define regCP_MEC_RS64_INTERRUPT_DATA_21_BASE_IDX                                                       1
7856 #define regCP_MEC_RS64_INTERRUPT_DATA_22                                                                0x2940
7857 #define regCP_MEC_RS64_INTERRUPT_DATA_22_BASE_IDX                                                       1
7858 #define regCP_MEC_RS64_INTERRUPT_DATA_23                                                                0x2941
7859 #define regCP_MEC_RS64_INTERRUPT_DATA_23_BASE_IDX                                                       1
7860 #define regCP_MEC_RS64_INTERRUPT_DATA_24                                                                0x2942
7861 #define regCP_MEC_RS64_INTERRUPT_DATA_24_BASE_IDX                                                       1
7862 #define regCP_MEC_RS64_INTERRUPT_DATA_25                                                                0x2943
7863 #define regCP_MEC_RS64_INTERRUPT_DATA_25_BASE_IDX                                                       1
7864 #define regCP_MEC_RS64_INTERRUPT_DATA_26                                                                0x2944
7865 #define regCP_MEC_RS64_INTERRUPT_DATA_26_BASE_IDX                                                       1
7866 #define regCP_MEC_RS64_INTERRUPT_DATA_27                                                                0x2945
7867 #define regCP_MEC_RS64_INTERRUPT_DATA_27_BASE_IDX                                                       1
7868 #define regCP_MEC_RS64_INTERRUPT_DATA_28                                                                0x2946
7869 #define regCP_MEC_RS64_INTERRUPT_DATA_28_BASE_IDX                                                       1
7870 #define regCP_MEC_RS64_INTERRUPT_DATA_29                                                                0x2947
7871 #define regCP_MEC_RS64_INTERRUPT_DATA_29_BASE_IDX                                                       1
7872 #define regCP_MEC_RS64_INTERRUPT_DATA_30                                                                0x2948
7873 #define regCP_MEC_RS64_INTERRUPT_DATA_30_BASE_IDX                                                       1
7874 #define regCP_MEC_RS64_INTERRUPT_DATA_31                                                                0x2949
7875 #define regCP_MEC_RS64_INTERRUPT_DATA_31_BASE_IDX                                                       1
7876 #define regCP_MEC_DC_APERTURE0_BASE                                                                     0x294a
7877 #define regCP_MEC_DC_APERTURE0_BASE_BASE_IDX                                                            1
7878 #define regCP_MEC_DC_APERTURE0_MASK                                                                     0x294b
7879 #define regCP_MEC_DC_APERTURE0_MASK_BASE_IDX                                                            1
7880 #define regCP_MEC_DC_APERTURE0_CNTL                                                                     0x294c
7881 #define regCP_MEC_DC_APERTURE0_CNTL_BASE_IDX                                                            1
7882 #define regCP_MEC_DC_APERTURE1_BASE                                                                     0x294d
7883 #define regCP_MEC_DC_APERTURE1_BASE_BASE_IDX                                                            1
7884 #define regCP_MEC_DC_APERTURE1_MASK                                                                     0x294e
7885 #define regCP_MEC_DC_APERTURE1_MASK_BASE_IDX                                                            1
7886 #define regCP_MEC_DC_APERTURE1_CNTL                                                                     0x294f
7887 #define regCP_MEC_DC_APERTURE1_CNTL_BASE_IDX                                                            1
7888 #define regCP_MEC_DC_APERTURE2_BASE                                                                     0x2950
7889 #define regCP_MEC_DC_APERTURE2_BASE_BASE_IDX                                                            1
7890 #define regCP_MEC_DC_APERTURE2_MASK                                                                     0x2951
7891 #define regCP_MEC_DC_APERTURE2_MASK_BASE_IDX                                                            1
7892 #define regCP_MEC_DC_APERTURE2_CNTL                                                                     0x2952
7893 #define regCP_MEC_DC_APERTURE2_CNTL_BASE_IDX                                                            1
7894 #define regCP_MEC_DC_APERTURE3_BASE                                                                     0x2953
7895 #define regCP_MEC_DC_APERTURE3_BASE_BASE_IDX                                                            1
7896 #define regCP_MEC_DC_APERTURE3_MASK                                                                     0x2954
7897 #define regCP_MEC_DC_APERTURE3_MASK_BASE_IDX                                                            1
7898 #define regCP_MEC_DC_APERTURE3_CNTL                                                                     0x2955
7899 #define regCP_MEC_DC_APERTURE3_CNTL_BASE_IDX                                                            1
7900 #define regCP_MEC_DC_APERTURE4_BASE                                                                     0x2956
7901 #define regCP_MEC_DC_APERTURE4_BASE_BASE_IDX                                                            1
7902 #define regCP_MEC_DC_APERTURE4_MASK                                                                     0x2957
7903 #define regCP_MEC_DC_APERTURE4_MASK_BASE_IDX                                                            1
7904 #define regCP_MEC_DC_APERTURE4_CNTL                                                                     0x2958
7905 #define regCP_MEC_DC_APERTURE4_CNTL_BASE_IDX                                                            1
7906 #define regCP_MEC_DC_APERTURE5_BASE                                                                     0x2959
7907 #define regCP_MEC_DC_APERTURE5_BASE_BASE_IDX                                                            1
7908 #define regCP_MEC_DC_APERTURE5_MASK                                                                     0x295a
7909 #define regCP_MEC_DC_APERTURE5_MASK_BASE_IDX                                                            1
7910 #define regCP_MEC_DC_APERTURE5_CNTL                                                                     0x295b
7911 #define regCP_MEC_DC_APERTURE5_CNTL_BASE_IDX                                                            1
7912 #define regCP_MEC_DC_APERTURE6_BASE                                                                     0x295c
7913 #define regCP_MEC_DC_APERTURE6_BASE_BASE_IDX                                                            1
7914 #define regCP_MEC_DC_APERTURE6_MASK                                                                     0x295d
7915 #define regCP_MEC_DC_APERTURE6_MASK_BASE_IDX                                                            1
7916 #define regCP_MEC_DC_APERTURE6_CNTL                                                                     0x295e
7917 #define regCP_MEC_DC_APERTURE6_CNTL_BASE_IDX                                                            1
7918 #define regCP_MEC_DC_APERTURE7_BASE                                                                     0x295f
7919 #define regCP_MEC_DC_APERTURE7_BASE_BASE_IDX                                                            1
7920 #define regCP_MEC_DC_APERTURE7_MASK                                                                     0x2960
7921 #define regCP_MEC_DC_APERTURE7_MASK_BASE_IDX                                                            1
7922 #define regCP_MEC_DC_APERTURE7_CNTL                                                                     0x2961
7923 #define regCP_MEC_DC_APERTURE7_CNTL_BASE_IDX                                                            1
7924 #define regCP_MEC_DC_APERTURE8_BASE                                                                     0x2962
7925 #define regCP_MEC_DC_APERTURE8_BASE_BASE_IDX                                                            1
7926 #define regCP_MEC_DC_APERTURE8_MASK                                                                     0x2963
7927 #define regCP_MEC_DC_APERTURE8_MASK_BASE_IDX                                                            1
7928 #define regCP_MEC_DC_APERTURE8_CNTL                                                                     0x2964
7929 #define regCP_MEC_DC_APERTURE8_CNTL_BASE_IDX                                                            1
7930 #define regCP_MEC_DC_APERTURE9_BASE                                                                     0x2965
7931 #define regCP_MEC_DC_APERTURE9_BASE_BASE_IDX                                                            1
7932 #define regCP_MEC_DC_APERTURE9_MASK                                                                     0x2966
7933 #define regCP_MEC_DC_APERTURE9_MASK_BASE_IDX                                                            1
7934 #define regCP_MEC_DC_APERTURE9_CNTL                                                                     0x2967
7935 #define regCP_MEC_DC_APERTURE9_CNTL_BASE_IDX                                                            1
7936 #define regCP_MEC_DC_APERTURE10_BASE                                                                    0x2968
7937 #define regCP_MEC_DC_APERTURE10_BASE_BASE_IDX                                                           1
7938 #define regCP_MEC_DC_APERTURE10_MASK                                                                    0x2969
7939 #define regCP_MEC_DC_APERTURE10_MASK_BASE_IDX                                                           1
7940 #define regCP_MEC_DC_APERTURE10_CNTL                                                                    0x296a
7941 #define regCP_MEC_DC_APERTURE10_CNTL_BASE_IDX                                                           1
7942 #define regCP_MEC_DC_APERTURE11_BASE                                                                    0x296b
7943 #define regCP_MEC_DC_APERTURE11_BASE_BASE_IDX                                                           1
7944 #define regCP_MEC_DC_APERTURE11_MASK                                                                    0x296c
7945 #define regCP_MEC_DC_APERTURE11_MASK_BASE_IDX                                                           1
7946 #define regCP_MEC_DC_APERTURE11_CNTL                                                                    0x296d
7947 #define regCP_MEC_DC_APERTURE11_CNTL_BASE_IDX                                                           1
7948 #define regCP_MEC_DC_APERTURE12_BASE                                                                    0x296e
7949 #define regCP_MEC_DC_APERTURE12_BASE_BASE_IDX                                                           1
7950 #define regCP_MEC_DC_APERTURE12_MASK                                                                    0x296f
7951 #define regCP_MEC_DC_APERTURE12_MASK_BASE_IDX                                                           1
7952 #define regCP_MEC_DC_APERTURE12_CNTL                                                                    0x2970
7953 #define regCP_MEC_DC_APERTURE12_CNTL_BASE_IDX                                                           1
7954 #define regCP_MEC_DC_APERTURE13_BASE                                                                    0x2971
7955 #define regCP_MEC_DC_APERTURE13_BASE_BASE_IDX                                                           1
7956 #define regCP_MEC_DC_APERTURE13_MASK                                                                    0x2972
7957 #define regCP_MEC_DC_APERTURE13_MASK_BASE_IDX                                                           1
7958 #define regCP_MEC_DC_APERTURE13_CNTL                                                                    0x2973
7959 #define regCP_MEC_DC_APERTURE13_CNTL_BASE_IDX                                                           1
7960 #define regCP_MEC_DC_APERTURE14_BASE                                                                    0x2974
7961 #define regCP_MEC_DC_APERTURE14_BASE_BASE_IDX                                                           1
7962 #define regCP_MEC_DC_APERTURE14_MASK                                                                    0x2975
7963 #define regCP_MEC_DC_APERTURE14_MASK_BASE_IDX                                                           1
7964 #define regCP_MEC_DC_APERTURE14_CNTL                                                                    0x2976
7965 #define regCP_MEC_DC_APERTURE14_CNTL_BASE_IDX                                                           1
7966 #define regCP_MEC_DC_APERTURE15_BASE                                                                    0x2977
7967 #define regCP_MEC_DC_APERTURE15_BASE_BASE_IDX                                                           1
7968 #define regCP_MEC_DC_APERTURE15_MASK                                                                    0x2978
7969 #define regCP_MEC_DC_APERTURE15_MASK_BASE_IDX                                                           1
7970 #define regCP_MEC_DC_APERTURE15_CNTL                                                                    0x2979
7971 #define regCP_MEC_DC_APERTURE15_CNTL_BASE_IDX                                                           1
7972 #define regCP_CPC_IC_OP_CNTL                                                                            0x297a
7973 #define regCP_CPC_IC_OP_CNTL_BASE_IDX                                                                   1
7974 #define regCP_GFX_CNTL                                                                                  0x2a00
7975 #define regCP_GFX_CNTL_BASE_IDX                                                                         1
7976 #define regCP_GFX_RS64_INTERRUPT0                                                                       0x2a01
7977 #define regCP_GFX_RS64_INTERRUPT0_BASE_IDX                                                              1
7978 #define regCP_GFX_RS64_INTR_EN0                                                                         0x2a02
7979 #define regCP_GFX_RS64_INTR_EN0_BASE_IDX                                                                1
7980 #define regCP_GFX_RS64_INTR_EN1                                                                         0x2a03
7981 #define regCP_GFX_RS64_INTR_EN1_BASE_IDX                                                                1
7982 #define regCP_GFX_RS64_DC_BASE_CNTL                                                                     0x2a08
7983 #define regCP_GFX_RS64_DC_BASE_CNTL_BASE_IDX                                                            1
7984 #define regCP_GFX_RS64_DC_OP_CNTL                                                                       0x2a09
7985 #define regCP_GFX_RS64_DC_OP_CNTL_BASE_IDX                                                              1
7986 #define regCP_GFX_RS64_LOCAL_BASE0_LO                                                                   0x2a0a
7987 #define regCP_GFX_RS64_LOCAL_BASE0_LO_BASE_IDX                                                          1
7988 #define regCP_GFX_RS64_LOCAL_BASE0_HI                                                                   0x2a0b
7989 #define regCP_GFX_RS64_LOCAL_BASE0_HI_BASE_IDX                                                          1
7990 #define regCP_GFX_RS64_LOCAL_MASK0_LO                                                                   0x2a0c
7991 #define regCP_GFX_RS64_LOCAL_MASK0_LO_BASE_IDX                                                          1
7992 #define regCP_GFX_RS64_LOCAL_MASK0_HI                                                                   0x2a0d
7993 #define regCP_GFX_RS64_LOCAL_MASK0_HI_BASE_IDX                                                          1
7994 #define regCP_GFX_RS64_LOCAL_APERTURE                                                                   0x2a0e
7995 #define regCP_GFX_RS64_LOCAL_APERTURE_BASE_IDX                                                          1
7996 #define regCP_GFX_RS64_LOCAL_INSTR_BASE_LO                                                              0x2a0f
7997 #define regCP_GFX_RS64_LOCAL_INSTR_BASE_LO_BASE_IDX                                                     1
7998 #define regCP_GFX_RS64_LOCAL_INSTR_BASE_HI                                                              0x2a10
7999 #define regCP_GFX_RS64_LOCAL_INSTR_BASE_HI_BASE_IDX                                                     1
8000 #define regCP_GFX_RS64_LOCAL_INSTR_MASK_LO                                                              0x2a11
8001 #define regCP_GFX_RS64_LOCAL_INSTR_MASK_LO_BASE_IDX                                                     1
8002 #define regCP_GFX_RS64_LOCAL_INSTR_MASK_HI                                                              0x2a12
8003 #define regCP_GFX_RS64_LOCAL_INSTR_MASK_HI_BASE_IDX                                                     1
8004 #define regCP_GFX_RS64_LOCAL_INSTR_APERTURE                                                             0x2a13
8005 #define regCP_GFX_RS64_LOCAL_INSTR_APERTURE_BASE_IDX                                                    1
8006 #define regCP_GFX_RS64_LOCAL_SCRATCH_APERTURE                                                           0x2a14
8007 #define regCP_GFX_RS64_LOCAL_SCRATCH_APERTURE_BASE_IDX                                                  1
8008 #define regCP_GFX_RS64_LOCAL_SCRATCH_BASE_LO                                                            0x2a15
8009 #define regCP_GFX_RS64_LOCAL_SCRATCH_BASE_LO_BASE_IDX                                                   1
8010 #define regCP_GFX_RS64_LOCAL_SCRATCH_BASE_HI                                                            0x2a16
8011 #define regCP_GFX_RS64_LOCAL_SCRATCH_BASE_HI_BASE_IDX                                                   1
8012 #define regCP_GFX_RS64_PERFCOUNT_CNTL0                                                                  0x2a1a
8013 #define regCP_GFX_RS64_PERFCOUNT_CNTL0_BASE_IDX                                                         1
8014 #define regCP_GFX_RS64_PERFCOUNT_CNTL1                                                                  0x2a1b
8015 #define regCP_GFX_RS64_PERFCOUNT_CNTL1_BASE_IDX                                                         1
8016 #define regCP_GFX_RS64_MIP_LO0                                                                          0x2a1c
8017 #define regCP_GFX_RS64_MIP_LO0_BASE_IDX                                                                 1
8018 #define regCP_GFX_RS64_MIP_LO1                                                                          0x2a1d
8019 #define regCP_GFX_RS64_MIP_LO1_BASE_IDX                                                                 1
8020 #define regCP_GFX_RS64_MIP_HI0                                                                          0x2a1e
8021 #define regCP_GFX_RS64_MIP_HI0_BASE_IDX                                                                 1
8022 #define regCP_GFX_RS64_MIP_HI1                                                                          0x2a1f
8023 #define regCP_GFX_RS64_MIP_HI1_BASE_IDX                                                                 1
8024 #define regCP_GFX_RS64_MTIMECMP_LO0                                                                     0x2a20
8025 #define regCP_GFX_RS64_MTIMECMP_LO0_BASE_IDX                                                            1
8026 #define regCP_GFX_RS64_MTIMECMP_LO1                                                                     0x2a21
8027 #define regCP_GFX_RS64_MTIMECMP_LO1_BASE_IDX                                                            1
8028 #define regCP_GFX_RS64_MTIMECMP_HI0                                                                     0x2a22
8029 #define regCP_GFX_RS64_MTIMECMP_HI0_BASE_IDX                                                            1
8030 #define regCP_GFX_RS64_MTIMECMP_HI1                                                                     0x2a23
8031 #define regCP_GFX_RS64_MTIMECMP_HI1_BASE_IDX                                                            1
8032 #define regCP_GFX_RS64_GP0_LO0                                                                          0x2a24
8033 #define regCP_GFX_RS64_GP0_LO0_BASE_IDX                                                                 1
8034 #define regCP_GFX_RS64_GP0_LO1                                                                          0x2a25
8035 #define regCP_GFX_RS64_GP0_LO1_BASE_IDX                                                                 1
8036 #define regCP_GFX_RS64_GP0_HI0                                                                          0x2a26
8037 #define regCP_GFX_RS64_GP0_HI0_BASE_IDX                                                                 1
8038 #define regCP_GFX_RS64_GP0_HI1                                                                          0x2a27
8039 #define regCP_GFX_RS64_GP0_HI1_BASE_IDX                                                                 1
8040 #define regCP_GFX_RS64_GP1_LO0                                                                          0x2a28
8041 #define regCP_GFX_RS64_GP1_LO0_BASE_IDX                                                                 1
8042 #define regCP_GFX_RS64_GP1_LO1                                                                          0x2a29
8043 #define regCP_GFX_RS64_GP1_LO1_BASE_IDX                                                                 1
8044 #define regCP_GFX_RS64_GP1_HI0                                                                          0x2a2a
8045 #define regCP_GFX_RS64_GP1_HI0_BASE_IDX                                                                 1
8046 #define regCP_GFX_RS64_GP1_HI1                                                                          0x2a2b
8047 #define regCP_GFX_RS64_GP1_HI1_BASE_IDX                                                                 1
8048 #define regCP_GFX_RS64_GP2_LO0                                                                          0x2a2c
8049 #define regCP_GFX_RS64_GP2_LO0_BASE_IDX                                                                 1
8050 #define regCP_GFX_RS64_GP2_LO1                                                                          0x2a2d
8051 #define regCP_GFX_RS64_GP2_LO1_BASE_IDX                                                                 1
8052 #define regCP_GFX_RS64_GP2_HI0                                                                          0x2a2e
8053 #define regCP_GFX_RS64_GP2_HI0_BASE_IDX                                                                 1
8054 #define regCP_GFX_RS64_GP2_HI1                                                                          0x2a2f
8055 #define regCP_GFX_RS64_GP2_HI1_BASE_IDX                                                                 1
8056 #define regCP_GFX_RS64_GP3_LO0                                                                          0x2a30
8057 #define regCP_GFX_RS64_GP3_LO0_BASE_IDX                                                                 1
8058 #define regCP_GFX_RS64_GP3_LO1                                                                          0x2a31
8059 #define regCP_GFX_RS64_GP3_LO1_BASE_IDX                                                                 1
8060 #define regCP_GFX_RS64_GP3_HI0                                                                          0x2a32
8061 #define regCP_GFX_RS64_GP3_HI0_BASE_IDX                                                                 1
8062 #define regCP_GFX_RS64_GP3_HI1                                                                          0x2a33
8063 #define regCP_GFX_RS64_GP3_HI1_BASE_IDX                                                                 1
8064 #define regCP_GFX_RS64_GP4_LO0                                                                          0x2a34
8065 #define regCP_GFX_RS64_GP4_LO0_BASE_IDX                                                                 1
8066 #define regCP_GFX_RS64_GP4_LO1                                                                          0x2a35
8067 #define regCP_GFX_RS64_GP4_LO1_BASE_IDX                                                                 1
8068 #define regCP_GFX_RS64_GP4_HI0                                                                          0x2a36
8069 #define regCP_GFX_RS64_GP4_HI0_BASE_IDX                                                                 1
8070 #define regCP_GFX_RS64_GP4_HI1                                                                          0x2a37
8071 #define regCP_GFX_RS64_GP4_HI1_BASE_IDX                                                                 1
8072 #define regCP_GFX_RS64_GP5_LO0                                                                          0x2a38
8073 #define regCP_GFX_RS64_GP5_LO0_BASE_IDX                                                                 1
8074 #define regCP_GFX_RS64_GP5_LO1                                                                          0x2a39
8075 #define regCP_GFX_RS64_GP5_LO1_BASE_IDX                                                                 1
8076 #define regCP_GFX_RS64_GP5_HI0                                                                          0x2a3a
8077 #define regCP_GFX_RS64_GP5_HI0_BASE_IDX                                                                 1
8078 #define regCP_GFX_RS64_GP5_HI1                                                                          0x2a3b
8079 #define regCP_GFX_RS64_GP5_HI1_BASE_IDX                                                                 1
8080 #define regCP_GFX_RS64_GP6_LO                                                                           0x2a3c
8081 #define regCP_GFX_RS64_GP6_LO_BASE_IDX                                                                  1
8082 #define regCP_GFX_RS64_GP6_HI                                                                           0x2a3d
8083 #define regCP_GFX_RS64_GP6_HI_BASE_IDX                                                                  1
8084 #define regCP_GFX_RS64_GP7_LO                                                                           0x2a3e
8085 #define regCP_GFX_RS64_GP7_LO_BASE_IDX                                                                  1
8086 #define regCP_GFX_RS64_GP7_HI                                                                           0x2a3f
8087 #define regCP_GFX_RS64_GP7_HI_BASE_IDX                                                                  1
8088 #define regCP_GFX_RS64_GP8_LO                                                                           0x2a40
8089 #define regCP_GFX_RS64_GP8_LO_BASE_IDX                                                                  1
8090 #define regCP_GFX_RS64_GP8_HI                                                                           0x2a41
8091 #define regCP_GFX_RS64_GP8_HI_BASE_IDX                                                                  1
8092 #define regCP_GFX_RS64_GP9_LO                                                                           0x2a42
8093 #define regCP_GFX_RS64_GP9_LO_BASE_IDX                                                                  1
8094 #define regCP_GFX_RS64_GP9_HI                                                                           0x2a43
8095 #define regCP_GFX_RS64_GP9_HI_BASE_IDX                                                                  1
8096 #define regCP_GFX_RS64_INSTR_PNTR0                                                                      0x2a44
8097 #define regCP_GFX_RS64_INSTR_PNTR0_BASE_IDX                                                             1
8098 #define regCP_GFX_RS64_INSTR_PNTR1                                                                      0x2a45
8099 #define regCP_GFX_RS64_INSTR_PNTR1_BASE_IDX                                                             1
8100 #define regCP_GFX_RS64_PENDING_INTERRUPT0                                                               0x2a46
8101 #define regCP_GFX_RS64_PENDING_INTERRUPT0_BASE_IDX                                                      1
8102 #define regCP_GFX_RS64_PENDING_INTERRUPT1                                                               0x2a47
8103 #define regCP_GFX_RS64_PENDING_INTERRUPT1_BASE_IDX                                                      1
8104 #define regCP_GFX_RS64_DC_APERTURE0_BASE0                                                               0x2a49
8105 #define regCP_GFX_RS64_DC_APERTURE0_BASE0_BASE_IDX                                                      1
8106 #define regCP_GFX_RS64_DC_APERTURE0_MASK0                                                               0x2a4a
8107 #define regCP_GFX_RS64_DC_APERTURE0_MASK0_BASE_IDX                                                      1
8108 #define regCP_GFX_RS64_DC_APERTURE0_CNTL0                                                               0x2a4b
8109 #define regCP_GFX_RS64_DC_APERTURE0_CNTL0_BASE_IDX                                                      1
8110 #define regCP_GFX_RS64_DC_APERTURE1_BASE0                                                               0x2a4c
8111 #define regCP_GFX_RS64_DC_APERTURE1_BASE0_BASE_IDX                                                      1
8112 #define regCP_GFX_RS64_DC_APERTURE1_MASK0                                                               0x2a4d
8113 #define regCP_GFX_RS64_DC_APERTURE1_MASK0_BASE_IDX                                                      1
8114 #define regCP_GFX_RS64_DC_APERTURE1_CNTL0                                                               0x2a4e
8115 #define regCP_GFX_RS64_DC_APERTURE1_CNTL0_BASE_IDX                                                      1
8116 #define regCP_GFX_RS64_DC_APERTURE2_BASE0                                                               0x2a4f
8117 #define regCP_GFX_RS64_DC_APERTURE2_BASE0_BASE_IDX                                                      1
8118 #define regCP_GFX_RS64_DC_APERTURE2_MASK0                                                               0x2a50
8119 #define regCP_GFX_RS64_DC_APERTURE2_MASK0_BASE_IDX                                                      1
8120 #define regCP_GFX_RS64_DC_APERTURE2_CNTL0                                                               0x2a51
8121 #define regCP_GFX_RS64_DC_APERTURE2_CNTL0_BASE_IDX                                                      1
8122 #define regCP_GFX_RS64_DC_APERTURE3_BASE0                                                               0x2a52
8123 #define regCP_GFX_RS64_DC_APERTURE3_BASE0_BASE_IDX                                                      1
8124 #define regCP_GFX_RS64_DC_APERTURE3_MASK0                                                               0x2a53
8125 #define regCP_GFX_RS64_DC_APERTURE3_MASK0_BASE_IDX                                                      1
8126 #define regCP_GFX_RS64_DC_APERTURE3_CNTL0                                                               0x2a54
8127 #define regCP_GFX_RS64_DC_APERTURE3_CNTL0_BASE_IDX                                                      1
8128 #define regCP_GFX_RS64_DC_APERTURE4_BASE0                                                               0x2a55
8129 #define regCP_GFX_RS64_DC_APERTURE4_BASE0_BASE_IDX                                                      1
8130 #define regCP_GFX_RS64_DC_APERTURE4_MASK0                                                               0x2a56
8131 #define regCP_GFX_RS64_DC_APERTURE4_MASK0_BASE_IDX                                                      1
8132 #define regCP_GFX_RS64_DC_APERTURE4_CNTL0                                                               0x2a57
8133 #define regCP_GFX_RS64_DC_APERTURE4_CNTL0_BASE_IDX                                                      1
8134 #define regCP_GFX_RS64_DC_APERTURE5_BASE0                                                               0x2a58
8135 #define regCP_GFX_RS64_DC_APERTURE5_BASE0_BASE_IDX                                                      1
8136 #define regCP_GFX_RS64_DC_APERTURE5_MASK0                                                               0x2a59
8137 #define regCP_GFX_RS64_DC_APERTURE5_MASK0_BASE_IDX                                                      1
8138 #define regCP_GFX_RS64_DC_APERTURE5_CNTL0                                                               0x2a5a
8139 #define regCP_GFX_RS64_DC_APERTURE5_CNTL0_BASE_IDX                                                      1
8140 #define regCP_GFX_RS64_DC_APERTURE6_BASE0                                                               0x2a5b
8141 #define regCP_GFX_RS64_DC_APERTURE6_BASE0_BASE_IDX                                                      1
8142 #define regCP_GFX_RS64_DC_APERTURE6_MASK0                                                               0x2a5c
8143 #define regCP_GFX_RS64_DC_APERTURE6_MASK0_BASE_IDX                                                      1
8144 #define regCP_GFX_RS64_DC_APERTURE6_CNTL0                                                               0x2a5d
8145 #define regCP_GFX_RS64_DC_APERTURE6_CNTL0_BASE_IDX                                                      1
8146 #define regCP_GFX_RS64_DC_APERTURE7_BASE0                                                               0x2a5e
8147 #define regCP_GFX_RS64_DC_APERTURE7_BASE0_BASE_IDX                                                      1
8148 #define regCP_GFX_RS64_DC_APERTURE7_MASK0                                                               0x2a5f
8149 #define regCP_GFX_RS64_DC_APERTURE7_MASK0_BASE_IDX                                                      1
8150 #define regCP_GFX_RS64_DC_APERTURE7_CNTL0                                                               0x2a60
8151 #define regCP_GFX_RS64_DC_APERTURE7_CNTL0_BASE_IDX                                                      1
8152 #define regCP_GFX_RS64_DC_APERTURE8_BASE0                                                               0x2a61
8153 #define regCP_GFX_RS64_DC_APERTURE8_BASE0_BASE_IDX                                                      1
8154 #define regCP_GFX_RS64_DC_APERTURE8_MASK0                                                               0x2a62
8155 #define regCP_GFX_RS64_DC_APERTURE8_MASK0_BASE_IDX                                                      1
8156 #define regCP_GFX_RS64_DC_APERTURE8_CNTL0                                                               0x2a63
8157 #define regCP_GFX_RS64_DC_APERTURE8_CNTL0_BASE_IDX                                                      1
8158 #define regCP_GFX_RS64_DC_APERTURE9_BASE0                                                               0x2a64
8159 #define regCP_GFX_RS64_DC_APERTURE9_BASE0_BASE_IDX                                                      1
8160 #define regCP_GFX_RS64_DC_APERTURE9_MASK0                                                               0x2a65
8161 #define regCP_GFX_RS64_DC_APERTURE9_MASK0_BASE_IDX                                                      1
8162 #define regCP_GFX_RS64_DC_APERTURE9_CNTL0                                                               0x2a66
8163 #define regCP_GFX_RS64_DC_APERTURE9_CNTL0_BASE_IDX                                                      1
8164 #define regCP_GFX_RS64_DC_APERTURE10_BASE0                                                              0x2a67
8165 #define regCP_GFX_RS64_DC_APERTURE10_BASE0_BASE_IDX                                                     1
8166 #define regCP_GFX_RS64_DC_APERTURE10_MASK0                                                              0x2a68
8167 #define regCP_GFX_RS64_DC_APERTURE10_MASK0_BASE_IDX                                                     1
8168 #define regCP_GFX_RS64_DC_APERTURE10_CNTL0                                                              0x2a69
8169 #define regCP_GFX_RS64_DC_APERTURE10_CNTL0_BASE_IDX                                                     1
8170 #define regCP_GFX_RS64_DC_APERTURE11_BASE0                                                              0x2a6a
8171 #define regCP_GFX_RS64_DC_APERTURE11_BASE0_BASE_IDX                                                     1
8172 #define regCP_GFX_RS64_DC_APERTURE11_MASK0                                                              0x2a6b
8173 #define regCP_GFX_RS64_DC_APERTURE11_MASK0_BASE_IDX                                                     1
8174 #define regCP_GFX_RS64_DC_APERTURE11_CNTL0                                                              0x2a6c
8175 #define regCP_GFX_RS64_DC_APERTURE11_CNTL0_BASE_IDX                                                     1
8176 #define regCP_GFX_RS64_DC_APERTURE12_BASE0                                                              0x2a6d
8177 #define regCP_GFX_RS64_DC_APERTURE12_BASE0_BASE_IDX                                                     1
8178 #define regCP_GFX_RS64_DC_APERTURE12_MASK0                                                              0x2a6e
8179 #define regCP_GFX_RS64_DC_APERTURE12_MASK0_BASE_IDX                                                     1
8180 #define regCP_GFX_RS64_DC_APERTURE12_CNTL0                                                              0x2a6f
8181 #define regCP_GFX_RS64_DC_APERTURE12_CNTL0_BASE_IDX                                                     1
8182 #define regCP_GFX_RS64_DC_APERTURE13_BASE0                                                              0x2a70
8183 #define regCP_GFX_RS64_DC_APERTURE13_BASE0_BASE_IDX                                                     1
8184 #define regCP_GFX_RS64_DC_APERTURE13_MASK0                                                              0x2a71
8185 #define regCP_GFX_RS64_DC_APERTURE13_MASK0_BASE_IDX                                                     1
8186 #define regCP_GFX_RS64_DC_APERTURE13_CNTL0                                                              0x2a72
8187 #define regCP_GFX_RS64_DC_APERTURE13_CNTL0_BASE_IDX                                                     1
8188 #define regCP_GFX_RS64_DC_APERTURE14_BASE0                                                              0x2a73
8189 #define regCP_GFX_RS64_DC_APERTURE14_BASE0_BASE_IDX                                                     1
8190 #define regCP_GFX_RS64_DC_APERTURE14_MASK0                                                              0x2a74
8191 #define regCP_GFX_RS64_DC_APERTURE14_MASK0_BASE_IDX                                                     1
8192 #define regCP_GFX_RS64_DC_APERTURE14_CNTL0                                                              0x2a75
8193 #define regCP_GFX_RS64_DC_APERTURE14_CNTL0_BASE_IDX                                                     1
8194 #define regCP_GFX_RS64_DC_APERTURE15_BASE0                                                              0x2a76
8195 #define regCP_GFX_RS64_DC_APERTURE15_BASE0_BASE_IDX                                                     1
8196 #define regCP_GFX_RS64_DC_APERTURE15_MASK0                                                              0x2a77
8197 #define regCP_GFX_RS64_DC_APERTURE15_MASK0_BASE_IDX                                                     1
8198 #define regCP_GFX_RS64_DC_APERTURE15_CNTL0                                                              0x2a78
8199 #define regCP_GFX_RS64_DC_APERTURE15_CNTL0_BASE_IDX                                                     1
8200 #define regCP_GFX_RS64_DC_APERTURE0_BASE1                                                               0x2a79
8201 #define regCP_GFX_RS64_DC_APERTURE0_BASE1_BASE_IDX                                                      1
8202 #define regCP_GFX_RS64_DC_APERTURE0_MASK1                                                               0x2a7a
8203 #define regCP_GFX_RS64_DC_APERTURE0_MASK1_BASE_IDX                                                      1
8204 #define regCP_GFX_RS64_DC_APERTURE0_CNTL1                                                               0x2a7b
8205 #define regCP_GFX_RS64_DC_APERTURE0_CNTL1_BASE_IDX                                                      1
8206 #define regCP_GFX_RS64_DC_APERTURE1_BASE1                                                               0x2a7c
8207 #define regCP_GFX_RS64_DC_APERTURE1_BASE1_BASE_IDX                                                      1
8208 #define regCP_GFX_RS64_DC_APERTURE1_MASK1                                                               0x2a7d
8209 #define regCP_GFX_RS64_DC_APERTURE1_MASK1_BASE_IDX                                                      1
8210 #define regCP_GFX_RS64_DC_APERTURE1_CNTL1                                                               0x2a7e
8211 #define regCP_GFX_RS64_DC_APERTURE1_CNTL1_BASE_IDX                                                      1
8212 #define regCP_GFX_RS64_DC_APERTURE2_BASE1                                                               0x2a7f
8213 #define regCP_GFX_RS64_DC_APERTURE2_BASE1_BASE_IDX                                                      1
8214 #define regCP_GFX_RS64_DC_APERTURE2_MASK1                                                               0x2a80
8215 #define regCP_GFX_RS64_DC_APERTURE2_MASK1_BASE_IDX                                                      1
8216 #define regCP_GFX_RS64_DC_APERTURE2_CNTL1                                                               0x2a81
8217 #define regCP_GFX_RS64_DC_APERTURE2_CNTL1_BASE_IDX                                                      1
8218 #define regCP_GFX_RS64_DC_APERTURE3_BASE1                                                               0x2a82
8219 #define regCP_GFX_RS64_DC_APERTURE3_BASE1_BASE_IDX                                                      1
8220 #define regCP_GFX_RS64_DC_APERTURE3_MASK1                                                               0x2a83
8221 #define regCP_GFX_RS64_DC_APERTURE3_MASK1_BASE_IDX                                                      1
8222 #define regCP_GFX_RS64_DC_APERTURE3_CNTL1                                                               0x2a84
8223 #define regCP_GFX_RS64_DC_APERTURE3_CNTL1_BASE_IDX                                                      1
8224 #define regCP_GFX_RS64_DC_APERTURE4_BASE1                                                               0x2a85
8225 #define regCP_GFX_RS64_DC_APERTURE4_BASE1_BASE_IDX                                                      1
8226 #define regCP_GFX_RS64_DC_APERTURE4_MASK1                                                               0x2a86
8227 #define regCP_GFX_RS64_DC_APERTURE4_MASK1_BASE_IDX                                                      1
8228 #define regCP_GFX_RS64_DC_APERTURE4_CNTL1                                                               0x2a87
8229 #define regCP_GFX_RS64_DC_APERTURE4_CNTL1_BASE_IDX                                                      1
8230 #define regCP_GFX_RS64_DC_APERTURE5_BASE1                                                               0x2a88
8231 #define regCP_GFX_RS64_DC_APERTURE5_BASE1_BASE_IDX                                                      1
8232 #define regCP_GFX_RS64_DC_APERTURE5_MASK1                                                               0x2a89
8233 #define regCP_GFX_RS64_DC_APERTURE5_MASK1_BASE_IDX                                                      1
8234 #define regCP_GFX_RS64_DC_APERTURE5_CNTL1                                                               0x2a8a
8235 #define regCP_GFX_RS64_DC_APERTURE5_CNTL1_BASE_IDX                                                      1
8236 #define regCP_GFX_RS64_DC_APERTURE6_BASE1                                                               0x2a8b
8237 #define regCP_GFX_RS64_DC_APERTURE6_BASE1_BASE_IDX                                                      1
8238 #define regCP_GFX_RS64_DC_APERTURE6_MASK1                                                               0x2a8c
8239 #define regCP_GFX_RS64_DC_APERTURE6_MASK1_BASE_IDX                                                      1
8240 #define regCP_GFX_RS64_DC_APERTURE6_CNTL1                                                               0x2a8d
8241 #define regCP_GFX_RS64_DC_APERTURE6_CNTL1_BASE_IDX                                                      1
8242 #define regCP_GFX_RS64_DC_APERTURE7_BASE1                                                               0x2a8e
8243 #define regCP_GFX_RS64_DC_APERTURE7_BASE1_BASE_IDX                                                      1
8244 #define regCP_GFX_RS64_DC_APERTURE7_MASK1                                                               0x2a8f
8245 #define regCP_GFX_RS64_DC_APERTURE7_MASK1_BASE_IDX                                                      1
8246 #define regCP_GFX_RS64_DC_APERTURE7_CNTL1                                                               0x2a90
8247 #define regCP_GFX_RS64_DC_APERTURE7_CNTL1_BASE_IDX                                                      1
8248 #define regCP_GFX_RS64_DC_APERTURE8_BASE1                                                               0x2a91
8249 #define regCP_GFX_RS64_DC_APERTURE8_BASE1_BASE_IDX                                                      1
8250 #define regCP_GFX_RS64_DC_APERTURE8_MASK1                                                               0x2a92
8251 #define regCP_GFX_RS64_DC_APERTURE8_MASK1_BASE_IDX                                                      1
8252 #define regCP_GFX_RS64_DC_APERTURE8_CNTL1                                                               0x2a93
8253 #define regCP_GFX_RS64_DC_APERTURE8_CNTL1_BASE_IDX                                                      1
8254 #define regCP_GFX_RS64_DC_APERTURE9_BASE1                                                               0x2a94
8255 #define regCP_GFX_RS64_DC_APERTURE9_BASE1_BASE_IDX                                                      1
8256 #define regCP_GFX_RS64_DC_APERTURE9_MASK1                                                               0x2a95
8257 #define regCP_GFX_RS64_DC_APERTURE9_MASK1_BASE_IDX                                                      1
8258 #define regCP_GFX_RS64_DC_APERTURE9_CNTL1                                                               0x2a96
8259 #define regCP_GFX_RS64_DC_APERTURE9_CNTL1_BASE_IDX                                                      1
8260 #define regCP_GFX_RS64_DC_APERTURE10_BASE1                                                              0x2a97
8261 #define regCP_GFX_RS64_DC_APERTURE10_BASE1_BASE_IDX                                                     1
8262 #define regCP_GFX_RS64_DC_APERTURE10_MASK1                                                              0x2a98
8263 #define regCP_GFX_RS64_DC_APERTURE10_MASK1_BASE_IDX                                                     1
8264 #define regCP_GFX_RS64_DC_APERTURE10_CNTL1                                                              0x2a99
8265 #define regCP_GFX_RS64_DC_APERTURE10_CNTL1_BASE_IDX                                                     1
8266 #define regCP_GFX_RS64_DC_APERTURE11_BASE1                                                              0x2a9a
8267 #define regCP_GFX_RS64_DC_APERTURE11_BASE1_BASE_IDX                                                     1
8268 #define regCP_GFX_RS64_DC_APERTURE11_MASK1                                                              0x2a9b
8269 #define regCP_GFX_RS64_DC_APERTURE11_MASK1_BASE_IDX                                                     1
8270 #define regCP_GFX_RS64_DC_APERTURE11_CNTL1                                                              0x2a9c
8271 #define regCP_GFX_RS64_DC_APERTURE11_CNTL1_BASE_IDX                                                     1
8272 #define regCP_GFX_RS64_DC_APERTURE12_BASE1                                                              0x2a9d
8273 #define regCP_GFX_RS64_DC_APERTURE12_BASE1_BASE_IDX                                                     1
8274 #define regCP_GFX_RS64_DC_APERTURE12_MASK1                                                              0x2a9e
8275 #define regCP_GFX_RS64_DC_APERTURE12_MASK1_BASE_IDX                                                     1
8276 #define regCP_GFX_RS64_DC_APERTURE12_CNTL1                                                              0x2a9f
8277 #define regCP_GFX_RS64_DC_APERTURE12_CNTL1_BASE_IDX                                                     1
8278 #define regCP_GFX_RS64_DC_APERTURE13_BASE1                                                              0x2aa0
8279 #define regCP_GFX_RS64_DC_APERTURE13_BASE1_BASE_IDX                                                     1
8280 #define regCP_GFX_RS64_DC_APERTURE13_MASK1                                                              0x2aa1
8281 #define regCP_GFX_RS64_DC_APERTURE13_MASK1_BASE_IDX                                                     1
8282 #define regCP_GFX_RS64_DC_APERTURE13_CNTL1                                                              0x2aa2
8283 #define regCP_GFX_RS64_DC_APERTURE13_CNTL1_BASE_IDX                                                     1
8284 #define regCP_GFX_RS64_DC_APERTURE14_BASE1                                                              0x2aa3
8285 #define regCP_GFX_RS64_DC_APERTURE14_BASE1_BASE_IDX                                                     1
8286 #define regCP_GFX_RS64_DC_APERTURE14_MASK1                                                              0x2aa4
8287 #define regCP_GFX_RS64_DC_APERTURE14_MASK1_BASE_IDX                                                     1
8288 #define regCP_GFX_RS64_DC_APERTURE14_CNTL1                                                              0x2aa5
8289 #define regCP_GFX_RS64_DC_APERTURE14_CNTL1_BASE_IDX                                                     1
8290 #define regCP_GFX_RS64_DC_APERTURE15_BASE1                                                              0x2aa6
8291 #define regCP_GFX_RS64_DC_APERTURE15_BASE1_BASE_IDX                                                     1
8292 #define regCP_GFX_RS64_DC_APERTURE15_MASK1                                                              0x2aa7
8293 #define regCP_GFX_RS64_DC_APERTURE15_MASK1_BASE_IDX                                                     1
8294 #define regCP_GFX_RS64_DC_APERTURE15_CNTL1                                                              0x2aa8
8295 #define regCP_GFX_RS64_DC_APERTURE15_CNTL1_BASE_IDX                                                     1
8296 #define regCP_GFX_RS64_INTERRUPT1                                                                       0x2aac
8297 #define regCP_GFX_RS64_INTERRUPT1_BASE_IDX                                                              1
8298 
8299 
8300 // addressBlock: gc_gl1dec
8301 // base address: 0x33400
8302 #define regGL1_DRAM_BURST_MASK                                                                          0x2d02
8303 #define regGL1_DRAM_BURST_MASK_BASE_IDX                                                                 1
8304 #define regGL1_ARB_STATUS                                                                               0x2d03
8305 #define regGL1_ARB_STATUS_BASE_IDX                                                                      1
8306 #define regGL1I_GL1R_REP_FGCG_OVERRIDE                                                                  0x2d05
8307 #define regGL1I_GL1R_REP_FGCG_OVERRIDE_BASE_IDX                                                         1
8308 #define regGL1C_STATUS                                                                                  0x2d41
8309 #define regGL1C_STATUS_BASE_IDX                                                                         1
8310 #define regGL1C_UTCL0_CNTL1                                                                             0x2d42
8311 #define regGL1C_UTCL0_CNTL1_BASE_IDX                                                                    1
8312 #define regGL1C_UTCL0_CNTL2                                                                             0x2d43
8313 #define regGL1C_UTCL0_CNTL2_BASE_IDX                                                                    1
8314 #define regGL1C_UTCL0_STATUS                                                                            0x2d44
8315 #define regGL1C_UTCL0_STATUS_BASE_IDX                                                                   1
8316 #define regGL1C_UTCL0_RETRY                                                                             0x2d45
8317 #define regGL1C_UTCL0_RETRY_BASE_IDX                                                                    1
8318 
8319 
8320 // addressBlock: gc_chdec
8321 // base address: 0x33600
8322 #define regCH_ARB_CTRL                                                                                  0x2d80
8323 #define regCH_ARB_CTRL_BASE_IDX                                                                         1
8324 #define regCH_DRAM_BURST_MASK                                                                           0x2d82
8325 #define regCH_DRAM_BURST_MASK_BASE_IDX                                                                  1
8326 #define regCH_ARB_STATUS                                                                                0x2d83
8327 #define regCH_ARB_STATUS_BASE_IDX                                                                       1
8328 #define regCH_DRAM_BURST_CTRL                                                                           0x2d84
8329 #define regCH_DRAM_BURST_CTRL_BASE_IDX                                                                  1
8330 #define regCHA_CHC_CREDITS                                                                              0x2d88
8331 #define regCHA_CHC_CREDITS_BASE_IDX                                                                     1
8332 #define regCHA_CLIENT_FREE_DELAY                                                                        0x2d89
8333 #define regCHA_CLIENT_FREE_DELAY_BASE_IDX                                                               1
8334 #define regCHI_CHR_REP_FGCG_OVERRIDE                                                                    0x2d8c
8335 #define regCHI_CHR_REP_FGCG_OVERRIDE_BASE_IDX                                                           1
8336 #define regCH_VC5_ENABLE                                                                                0x2d94
8337 #define regCH_VC5_ENABLE_BASE_IDX                                                                       1
8338 #define regCHC_CTRL                                                                                     0x2dc0
8339 #define regCHC_CTRL_BASE_IDX                                                                            1
8340 #define regCHC_STATUS                                                                                   0x2dc1
8341 #define regCHC_STATUS_BASE_IDX                                                                          1
8342 #define regCHCG_CTRL                                                                                    0x2dc2
8343 #define regCHCG_CTRL_BASE_IDX                                                                           1
8344 #define regCHCG_STATUS                                                                                  0x2dc3
8345 #define regCHCG_STATUS_BASE_IDX                                                                         1
8346 
8347 
8348 // addressBlock: gc_gl2dec
8349 // base address: 0x33800
8350 #define regGL2C_CTRL                                                                                    0x2e00
8351 #define regGL2C_CTRL_BASE_IDX                                                                           1
8352 #define regGL2C_CTRL2                                                                                   0x2e01
8353 #define regGL2C_CTRL2_BASE_IDX                                                                          1
8354 #define regGL2C_ADDR_MATCH_MASK                                                                         0x2e03
8355 #define regGL2C_ADDR_MATCH_MASK_BASE_IDX                                                                1
8356 #define regGL2C_ADDR_MATCH_SIZE                                                                         0x2e04
8357 #define regGL2C_ADDR_MATCH_SIZE_BASE_IDX                                                                1
8358 #define regGL2C_WBINVL2                                                                                 0x2e05
8359 #define regGL2C_WBINVL2_BASE_IDX                                                                        1
8360 #define regGL2C_SOFT_RESET                                                                              0x2e06
8361 #define regGL2C_SOFT_RESET_BASE_IDX                                                                     1
8362 #define regGL2C_CM_CTRL0                                                                                0x2e07
8363 #define regGL2C_CM_CTRL0_BASE_IDX                                                                       1
8364 #define regGL2C_CM_CTRL1                                                                                0x2e08
8365 #define regGL2C_CM_CTRL1_BASE_IDX                                                                       1
8366 #define regGL2C_CM_STALL                                                                                0x2e09
8367 #define regGL2C_CM_STALL_BASE_IDX                                                                       1
8368 #define regGL2C_CTRL3                                                                                   0x2e0c
8369 #define regGL2C_CTRL3_BASE_IDX                                                                          1
8370 #define regGL2C_LB_CTR_CTRL                                                                             0x2e0d
8371 #define regGL2C_LB_CTR_CTRL_BASE_IDX                                                                    1
8372 #define regGL2C_LB_DATA0                                                                                0x2e0e
8373 #define regGL2C_LB_DATA0_BASE_IDX                                                                       1
8374 #define regGL2C_LB_DATA1                                                                                0x2e0f
8375 #define regGL2C_LB_DATA1_BASE_IDX                                                                       1
8376 #define regGL2C_LB_DATA2                                                                                0x2e10
8377 #define regGL2C_LB_DATA2_BASE_IDX                                                                       1
8378 #define regGL2C_LB_DATA3                                                                                0x2e11
8379 #define regGL2C_LB_DATA3_BASE_IDX                                                                       1
8380 #define regGL2C_LB_CTR_SEL0                                                                             0x2e12
8381 #define regGL2C_LB_CTR_SEL0_BASE_IDX                                                                    1
8382 #define regGL2C_LB_CTR_SEL1                                                                             0x2e13
8383 #define regGL2C_LB_CTR_SEL1_BASE_IDX                                                                    1
8384 #define regGL2C_CTRL4                                                                                   0x2e17
8385 #define regGL2C_CTRL4_BASE_IDX                                                                          1
8386 #define regGL2C_DISCARD_STALL_CTRL                                                                      0x2e18
8387 #define regGL2C_DISCARD_STALL_CTRL_BASE_IDX                                                             1
8388 #define regGL2A_ADDR_MATCH_CTRL                                                                         0x2e20
8389 #define regGL2A_ADDR_MATCH_CTRL_BASE_IDX                                                                1
8390 #define regGL2A_ADDR_MATCH_MASK                                                                         0x2e21
8391 #define regGL2A_ADDR_MATCH_MASK_BASE_IDX                                                                1
8392 #define regGL2A_ADDR_MATCH_SIZE                                                                         0x2e22
8393 #define regGL2A_ADDR_MATCH_SIZE_BASE_IDX                                                                1
8394 #define regGL2A_PRIORITY_CTRL                                                                           0x2e23
8395 #define regGL2A_PRIORITY_CTRL_BASE_IDX                                                                  1
8396 #define regGL2A_RESP_THROTTLE_CTRL                                                                      0x2e2a
8397 #define regGL2A_RESP_THROTTLE_CTRL_BASE_IDX                                                             1
8398 
8399 
8400 // addressBlock: gc_gl1hdec
8401 // base address: 0x33900
8402 #define regGL1H_ARB_CTRL                                                                                0x2e40
8403 #define regGL1H_ARB_CTRL_BASE_IDX                                                                       1
8404 #define regGL1H_GL1_CREDITS                                                                             0x2e41
8405 #define regGL1H_GL1_CREDITS_BASE_IDX                                                                    1
8406 #define regGL1H_BURST_MASK                                                                              0x2e42
8407 #define regGL1H_BURST_MASK_BASE_IDX                                                                     1
8408 #define regGL1H_BURST_CTRL                                                                              0x2e43
8409 #define regGL1H_BURST_CTRL_BASE_IDX                                                                     1
8410 #define regGL1H_ARB_STATUS                                                                              0x2e44
8411 #define regGL1H_ARB_STATUS_BASE_IDX                                                                     1
8412 
8413 
8414 // addressBlock: gc_perfddec
8415 // base address: 0x34000
8416 #define regCPG_PERFCOUNTER1_LO                                                                          0x3000
8417 #define regCPG_PERFCOUNTER1_LO_BASE_IDX                                                                 1
8418 #define regCPG_PERFCOUNTER1_HI                                                                          0x3001
8419 #define regCPG_PERFCOUNTER1_HI_BASE_IDX                                                                 1
8420 #define regCPG_PERFCOUNTER0_LO                                                                          0x3002
8421 #define regCPG_PERFCOUNTER0_LO_BASE_IDX                                                                 1
8422 #define regCPG_PERFCOUNTER0_HI                                                                          0x3003
8423 #define regCPG_PERFCOUNTER0_HI_BASE_IDX                                                                 1
8424 #define regCPC_PERFCOUNTER1_LO                                                                          0x3004
8425 #define regCPC_PERFCOUNTER1_LO_BASE_IDX                                                                 1
8426 #define regCPC_PERFCOUNTER1_HI                                                                          0x3005
8427 #define regCPC_PERFCOUNTER1_HI_BASE_IDX                                                                 1
8428 #define regCPC_PERFCOUNTER0_LO                                                                          0x3006
8429 #define regCPC_PERFCOUNTER0_LO_BASE_IDX                                                                 1
8430 #define regCPC_PERFCOUNTER0_HI                                                                          0x3007
8431 #define regCPC_PERFCOUNTER0_HI_BASE_IDX                                                                 1
8432 #define regCPF_PERFCOUNTER1_LO                                                                          0x3008
8433 #define regCPF_PERFCOUNTER1_LO_BASE_IDX                                                                 1
8434 #define regCPF_PERFCOUNTER1_HI                                                                          0x3009
8435 #define regCPF_PERFCOUNTER1_HI_BASE_IDX                                                                 1
8436 #define regCPF_PERFCOUNTER0_LO                                                                          0x300a
8437 #define regCPF_PERFCOUNTER0_LO_BASE_IDX                                                                 1
8438 #define regCPF_PERFCOUNTER0_HI                                                                          0x300b
8439 #define regCPF_PERFCOUNTER0_HI_BASE_IDX                                                                 1
8440 #define regCPF_LATENCY_STATS_DATA                                                                       0x300c
8441 #define regCPF_LATENCY_STATS_DATA_BASE_IDX                                                              1
8442 #define regCPG_LATENCY_STATS_DATA                                                                       0x300d
8443 #define regCPG_LATENCY_STATS_DATA_BASE_IDX                                                              1
8444 #define regCPC_LATENCY_STATS_DATA                                                                       0x300e
8445 #define regCPC_LATENCY_STATS_DATA_BASE_IDX                                                              1
8446 #define regGRBM_PERFCOUNTER0_LO                                                                         0x3040
8447 #define regGRBM_PERFCOUNTER0_LO_BASE_IDX                                                                1
8448 #define regGRBM_PERFCOUNTER0_HI                                                                         0x3041
8449 #define regGRBM_PERFCOUNTER0_HI_BASE_IDX                                                                1
8450 #define regGRBM_PERFCOUNTER1_LO                                                                         0x3043
8451 #define regGRBM_PERFCOUNTER1_LO_BASE_IDX                                                                1
8452 #define regGRBM_PERFCOUNTER1_HI                                                                         0x3044
8453 #define regGRBM_PERFCOUNTER1_HI_BASE_IDX                                                                1
8454 #define regGRBM_SE0_PERFCOUNTER_LO                                                                      0x3045
8455 #define regGRBM_SE0_PERFCOUNTER_LO_BASE_IDX                                                             1
8456 #define regGRBM_SE0_PERFCOUNTER_HI                                                                      0x3046
8457 #define regGRBM_SE0_PERFCOUNTER_HI_BASE_IDX                                                             1
8458 #define regGRBM_SE1_PERFCOUNTER_LO                                                                      0x3047
8459 #define regGRBM_SE1_PERFCOUNTER_LO_BASE_IDX                                                             1
8460 #define regGRBM_SE1_PERFCOUNTER_HI                                                                      0x3048
8461 #define regGRBM_SE1_PERFCOUNTER_HI_BASE_IDX                                                             1
8462 #define regGRBM_SE2_PERFCOUNTER_LO                                                                      0x3049
8463 #define regGRBM_SE2_PERFCOUNTER_LO_BASE_IDX                                                             1
8464 #define regGRBM_SE2_PERFCOUNTER_HI                                                                      0x304a
8465 #define regGRBM_SE2_PERFCOUNTER_HI_BASE_IDX                                                             1
8466 #define regGRBM_SE3_PERFCOUNTER_LO                                                                      0x304b
8467 #define regGRBM_SE3_PERFCOUNTER_LO_BASE_IDX                                                             1
8468 #define regGRBM_SE3_PERFCOUNTER_HI                                                                      0x304c
8469 #define regGRBM_SE3_PERFCOUNTER_HI_BASE_IDX                                                             1
8470 #define regGRBM_SE4_PERFCOUNTER_LO                                                                      0x304d
8471 #define regGRBM_SE4_PERFCOUNTER_LO_BASE_IDX                                                             1
8472 #define regGRBM_SE4_PERFCOUNTER_HI                                                                      0x304e
8473 #define regGRBM_SE4_PERFCOUNTER_HI_BASE_IDX                                                             1
8474 #define regGRBM_SE5_PERFCOUNTER_LO                                                                      0x304f
8475 #define regGRBM_SE5_PERFCOUNTER_LO_BASE_IDX                                                             1
8476 #define regGRBM_SE5_PERFCOUNTER_HI                                                                      0x3050
8477 #define regGRBM_SE5_PERFCOUNTER_HI_BASE_IDX                                                             1
8478 #define regGRBM_SE6_PERFCOUNTER_LO                                                                      0x3051
8479 #define regGRBM_SE6_PERFCOUNTER_LO_BASE_IDX                                                             1
8480 #define regGRBM_SE6_PERFCOUNTER_HI                                                                      0x3052
8481 #define regGRBM_SE6_PERFCOUNTER_HI_BASE_IDX                                                             1
8482 #define regGE1_PERFCOUNTER0_LO                                                                          0x30a4
8483 #define regGE1_PERFCOUNTER0_LO_BASE_IDX                                                                 1
8484 #define regGE1_PERFCOUNTER0_HI                                                                          0x30a5
8485 #define regGE1_PERFCOUNTER0_HI_BASE_IDX                                                                 1
8486 #define regGE1_PERFCOUNTER1_LO                                                                          0x30a6
8487 #define regGE1_PERFCOUNTER1_LO_BASE_IDX                                                                 1
8488 #define regGE1_PERFCOUNTER1_HI                                                                          0x30a7
8489 #define regGE1_PERFCOUNTER1_HI_BASE_IDX                                                                 1
8490 #define regGE1_PERFCOUNTER2_LO                                                                          0x30a8
8491 #define regGE1_PERFCOUNTER2_LO_BASE_IDX                                                                 1
8492 #define regGE1_PERFCOUNTER2_HI                                                                          0x30a9
8493 #define regGE1_PERFCOUNTER2_HI_BASE_IDX                                                                 1
8494 #define regGE1_PERFCOUNTER3_LO                                                                          0x30aa
8495 #define regGE1_PERFCOUNTER3_LO_BASE_IDX                                                                 1
8496 #define regGE1_PERFCOUNTER3_HI                                                                          0x30ab
8497 #define regGE1_PERFCOUNTER3_HI_BASE_IDX                                                                 1
8498 #define regGE2_DIST_PERFCOUNTER0_LO                                                                     0x30ac
8499 #define regGE2_DIST_PERFCOUNTER0_LO_BASE_IDX                                                            1
8500 #define regGE2_DIST_PERFCOUNTER0_HI                                                                     0x30ad
8501 #define regGE2_DIST_PERFCOUNTER0_HI_BASE_IDX                                                            1
8502 #define regGE2_DIST_PERFCOUNTER1_LO                                                                     0x30ae
8503 #define regGE2_DIST_PERFCOUNTER1_LO_BASE_IDX                                                            1
8504 #define regGE2_DIST_PERFCOUNTER1_HI                                                                     0x30af
8505 #define regGE2_DIST_PERFCOUNTER1_HI_BASE_IDX                                                            1
8506 #define regGE2_DIST_PERFCOUNTER2_LO                                                                     0x30b0
8507 #define regGE2_DIST_PERFCOUNTER2_LO_BASE_IDX                                                            1
8508 #define regGE2_DIST_PERFCOUNTER2_HI                                                                     0x30b1
8509 #define regGE2_DIST_PERFCOUNTER2_HI_BASE_IDX                                                            1
8510 #define regGE2_DIST_PERFCOUNTER3_LO                                                                     0x30b2
8511 #define regGE2_DIST_PERFCOUNTER3_LO_BASE_IDX                                                            1
8512 #define regGE2_DIST_PERFCOUNTER3_HI                                                                     0x30b3
8513 #define regGE2_DIST_PERFCOUNTER3_HI_BASE_IDX                                                            1
8514 #define regGE2_SE_PERFCOUNTER0_LO                                                                       0x30b4
8515 #define regGE2_SE_PERFCOUNTER0_LO_BASE_IDX                                                              1
8516 #define regGE2_SE_PERFCOUNTER0_HI                                                                       0x30b5
8517 #define regGE2_SE_PERFCOUNTER0_HI_BASE_IDX                                                              1
8518 #define regGE2_SE_PERFCOUNTER1_LO                                                                       0x30b6
8519 #define regGE2_SE_PERFCOUNTER1_LO_BASE_IDX                                                              1
8520 #define regGE2_SE_PERFCOUNTER1_HI                                                                       0x30b7
8521 #define regGE2_SE_PERFCOUNTER1_HI_BASE_IDX                                                              1
8522 #define regGE2_SE_PERFCOUNTER2_LO                                                                       0x30b8
8523 #define regGE2_SE_PERFCOUNTER2_LO_BASE_IDX                                                              1
8524 #define regGE2_SE_PERFCOUNTER2_HI                                                                       0x30b9
8525 #define regGE2_SE_PERFCOUNTER2_HI_BASE_IDX                                                              1
8526 #define regGE2_SE_PERFCOUNTER3_LO                                                                       0x30ba
8527 #define regGE2_SE_PERFCOUNTER3_LO_BASE_IDX                                                              1
8528 #define regGE2_SE_PERFCOUNTER3_HI                                                                       0x30bb
8529 #define regGE2_SE_PERFCOUNTER3_HI_BASE_IDX                                                              1
8530 #define regPA_SU_PERFCOUNTER0_LO                                                                        0x3100
8531 #define regPA_SU_PERFCOUNTER0_LO_BASE_IDX                                                               1
8532 #define regPA_SU_PERFCOUNTER0_HI                                                                        0x3101
8533 #define regPA_SU_PERFCOUNTER0_HI_BASE_IDX                                                               1
8534 #define regPA_SU_PERFCOUNTER1_LO                                                                        0x3102
8535 #define regPA_SU_PERFCOUNTER1_LO_BASE_IDX                                                               1
8536 #define regPA_SU_PERFCOUNTER1_HI                                                                        0x3103
8537 #define regPA_SU_PERFCOUNTER1_HI_BASE_IDX                                                               1
8538 #define regPA_SU_PERFCOUNTER2_LO                                                                        0x3104
8539 #define regPA_SU_PERFCOUNTER2_LO_BASE_IDX                                                               1
8540 #define regPA_SU_PERFCOUNTER2_HI                                                                        0x3105
8541 #define regPA_SU_PERFCOUNTER2_HI_BASE_IDX                                                               1
8542 #define regPA_SU_PERFCOUNTER3_LO                                                                        0x3106
8543 #define regPA_SU_PERFCOUNTER3_LO_BASE_IDX                                                               1
8544 #define regPA_SU_PERFCOUNTER3_HI                                                                        0x3107
8545 #define regPA_SU_PERFCOUNTER3_HI_BASE_IDX                                                               1
8546 #define regPA_SC_PERFCOUNTER0_LO                                                                        0x3140
8547 #define regPA_SC_PERFCOUNTER0_LO_BASE_IDX                                                               1
8548 #define regPA_SC_PERFCOUNTER0_HI                                                                        0x3141
8549 #define regPA_SC_PERFCOUNTER0_HI_BASE_IDX                                                               1
8550 #define regPA_SC_PERFCOUNTER1_LO                                                                        0x3142
8551 #define regPA_SC_PERFCOUNTER1_LO_BASE_IDX                                                               1
8552 #define regPA_SC_PERFCOUNTER1_HI                                                                        0x3143
8553 #define regPA_SC_PERFCOUNTER1_HI_BASE_IDX                                                               1
8554 #define regPA_SC_PERFCOUNTER2_LO                                                                        0x3144
8555 #define regPA_SC_PERFCOUNTER2_LO_BASE_IDX                                                               1
8556 #define regPA_SC_PERFCOUNTER2_HI                                                                        0x3145
8557 #define regPA_SC_PERFCOUNTER2_HI_BASE_IDX                                                               1
8558 #define regPA_SC_PERFCOUNTER3_LO                                                                        0x3146
8559 #define regPA_SC_PERFCOUNTER3_LO_BASE_IDX                                                               1
8560 #define regPA_SC_PERFCOUNTER3_HI                                                                        0x3147
8561 #define regPA_SC_PERFCOUNTER3_HI_BASE_IDX                                                               1
8562 #define regPA_SC_PERFCOUNTER4_LO                                                                        0x3148
8563 #define regPA_SC_PERFCOUNTER4_LO_BASE_IDX                                                               1
8564 #define regPA_SC_PERFCOUNTER4_HI                                                                        0x3149
8565 #define regPA_SC_PERFCOUNTER4_HI_BASE_IDX                                                               1
8566 #define regPA_SC_PERFCOUNTER5_LO                                                                        0x314a
8567 #define regPA_SC_PERFCOUNTER5_LO_BASE_IDX                                                               1
8568 #define regPA_SC_PERFCOUNTER5_HI                                                                        0x314b
8569 #define regPA_SC_PERFCOUNTER5_HI_BASE_IDX                                                               1
8570 #define regPA_SC_PERFCOUNTER6_LO                                                                        0x314c
8571 #define regPA_SC_PERFCOUNTER6_LO_BASE_IDX                                                               1
8572 #define regPA_SC_PERFCOUNTER6_HI                                                                        0x314d
8573 #define regPA_SC_PERFCOUNTER6_HI_BASE_IDX                                                               1
8574 #define regPA_SC_PERFCOUNTER7_LO                                                                        0x314e
8575 #define regPA_SC_PERFCOUNTER7_LO_BASE_IDX                                                               1
8576 #define regPA_SC_PERFCOUNTER7_HI                                                                        0x314f
8577 #define regPA_SC_PERFCOUNTER7_HI_BASE_IDX                                                               1
8578 #define regSPI_PERFCOUNTER0_HI                                                                          0x3180
8579 #define regSPI_PERFCOUNTER0_HI_BASE_IDX                                                                 1
8580 #define regSPI_PERFCOUNTER0_LO                                                                          0x3181
8581 #define regSPI_PERFCOUNTER0_LO_BASE_IDX                                                                 1
8582 #define regSPI_PERFCOUNTER1_HI                                                                          0x3182
8583 #define regSPI_PERFCOUNTER1_HI_BASE_IDX                                                                 1
8584 #define regSPI_PERFCOUNTER1_LO                                                                          0x3183
8585 #define regSPI_PERFCOUNTER1_LO_BASE_IDX                                                                 1
8586 #define regSPI_PERFCOUNTER2_HI                                                                          0x3184
8587 #define regSPI_PERFCOUNTER2_HI_BASE_IDX                                                                 1
8588 #define regSPI_PERFCOUNTER2_LO                                                                          0x3185
8589 #define regSPI_PERFCOUNTER2_LO_BASE_IDX                                                                 1
8590 #define regSPI_PERFCOUNTER3_HI                                                                          0x3186
8591 #define regSPI_PERFCOUNTER3_HI_BASE_IDX                                                                 1
8592 #define regSPI_PERFCOUNTER3_LO                                                                          0x3187
8593 #define regSPI_PERFCOUNTER3_LO_BASE_IDX                                                                 1
8594 #define regSPI_PERFCOUNTER4_HI                                                                          0x3188
8595 #define regSPI_PERFCOUNTER4_HI_BASE_IDX                                                                 1
8596 #define regSPI_PERFCOUNTER4_LO                                                                          0x3189
8597 #define regSPI_PERFCOUNTER4_LO_BASE_IDX                                                                 1
8598 #define regSPI_PERFCOUNTER5_HI                                                                          0x318a
8599 #define regSPI_PERFCOUNTER5_HI_BASE_IDX                                                                 1
8600 #define regSPI_PERFCOUNTER5_LO                                                                          0x318b
8601 #define regSPI_PERFCOUNTER5_LO_BASE_IDX                                                                 1
8602 #define regPC_PERFCOUNTER0_HI                                                                           0x318c
8603 #define regPC_PERFCOUNTER0_HI_BASE_IDX                                                                  1
8604 #define regPC_PERFCOUNTER0_LO                                                                           0x318d
8605 #define regPC_PERFCOUNTER0_LO_BASE_IDX                                                                  1
8606 #define regPC_PERFCOUNTER1_HI                                                                           0x318e
8607 #define regPC_PERFCOUNTER1_HI_BASE_IDX                                                                  1
8608 #define regPC_PERFCOUNTER1_LO                                                                           0x318f
8609 #define regPC_PERFCOUNTER1_LO_BASE_IDX                                                                  1
8610 #define regPC_PERFCOUNTER2_HI                                                                           0x3190
8611 #define regPC_PERFCOUNTER2_HI_BASE_IDX                                                                  1
8612 #define regPC_PERFCOUNTER2_LO                                                                           0x3191
8613 #define regPC_PERFCOUNTER2_LO_BASE_IDX                                                                  1
8614 #define regPC_PERFCOUNTER3_HI                                                                           0x3192
8615 #define regPC_PERFCOUNTER3_HI_BASE_IDX                                                                  1
8616 #define regPC_PERFCOUNTER3_LO                                                                           0x3193
8617 #define regPC_PERFCOUNTER3_LO_BASE_IDX                                                                  1
8618 #define regSQ_PERFCOUNTER0_LO                                                                           0x31c0
8619 #define regSQ_PERFCOUNTER0_LO_BASE_IDX                                                                  1
8620 #define regSQ_PERFCOUNTER1_LO                                                                           0x31c2
8621 #define regSQ_PERFCOUNTER1_LO_BASE_IDX                                                                  1
8622 #define regSQ_PERFCOUNTER2_LO                                                                           0x31c4
8623 #define regSQ_PERFCOUNTER2_LO_BASE_IDX                                                                  1
8624 #define regSQ_PERFCOUNTER3_LO                                                                           0x31c6
8625 #define regSQ_PERFCOUNTER3_LO_BASE_IDX                                                                  1
8626 #define regSQ_PERFCOUNTER4_LO                                                                           0x31c8
8627 #define regSQ_PERFCOUNTER4_LO_BASE_IDX                                                                  1
8628 #define regSQ_PERFCOUNTER5_LO                                                                           0x31ca
8629 #define regSQ_PERFCOUNTER5_LO_BASE_IDX                                                                  1
8630 #define regSQ_PERFCOUNTER6_LO                                                                           0x31cc
8631 #define regSQ_PERFCOUNTER6_LO_BASE_IDX                                                                  1
8632 #define regSQ_PERFCOUNTER7_LO                                                                           0x31ce
8633 #define regSQ_PERFCOUNTER7_LO_BASE_IDX                                                                  1
8634 #define regSQG_PERFCOUNTER0_LO                                                                          0x31e4
8635 #define regSQG_PERFCOUNTER0_LO_BASE_IDX                                                                 1
8636 #define regSQG_PERFCOUNTER0_HI                                                                          0x31e5
8637 #define regSQG_PERFCOUNTER0_HI_BASE_IDX                                                                 1
8638 #define regSQG_PERFCOUNTER1_LO                                                                          0x31e6
8639 #define regSQG_PERFCOUNTER1_LO_BASE_IDX                                                                 1
8640 #define regSQG_PERFCOUNTER1_HI                                                                          0x31e7
8641 #define regSQG_PERFCOUNTER1_HI_BASE_IDX                                                                 1
8642 #define regSQG_PERFCOUNTER2_LO                                                                          0x31e8
8643 #define regSQG_PERFCOUNTER2_LO_BASE_IDX                                                                 1
8644 #define regSQG_PERFCOUNTER2_HI                                                                          0x31e9
8645 #define regSQG_PERFCOUNTER2_HI_BASE_IDX                                                                 1
8646 #define regSQG_PERFCOUNTER3_LO                                                                          0x31ea
8647 #define regSQG_PERFCOUNTER3_LO_BASE_IDX                                                                 1
8648 #define regSQG_PERFCOUNTER3_HI                                                                          0x31eb
8649 #define regSQG_PERFCOUNTER3_HI_BASE_IDX                                                                 1
8650 #define regSQG_PERFCOUNTER4_LO                                                                          0x31ec
8651 #define regSQG_PERFCOUNTER4_LO_BASE_IDX                                                                 1
8652 #define regSQG_PERFCOUNTER4_HI                                                                          0x31ed
8653 #define regSQG_PERFCOUNTER4_HI_BASE_IDX                                                                 1
8654 #define regSQG_PERFCOUNTER5_LO                                                                          0x31ee
8655 #define regSQG_PERFCOUNTER5_LO_BASE_IDX                                                                 1
8656 #define regSQG_PERFCOUNTER5_HI                                                                          0x31ef
8657 #define regSQG_PERFCOUNTER5_HI_BASE_IDX                                                                 1
8658 #define regSQG_PERFCOUNTER6_LO                                                                          0x31f0
8659 #define regSQG_PERFCOUNTER6_LO_BASE_IDX                                                                 1
8660 #define regSQG_PERFCOUNTER6_HI                                                                          0x31f1
8661 #define regSQG_PERFCOUNTER6_HI_BASE_IDX                                                                 1
8662 #define regSQG_PERFCOUNTER7_LO                                                                          0x31f2
8663 #define regSQG_PERFCOUNTER7_LO_BASE_IDX                                                                 1
8664 #define regSQG_PERFCOUNTER7_HI                                                                          0x31f3
8665 #define regSQG_PERFCOUNTER7_HI_BASE_IDX                                                                 1
8666 #define regSX_PERFCOUNTER0_LO                                                                           0x3240
8667 #define regSX_PERFCOUNTER0_LO_BASE_IDX                                                                  1
8668 #define regSX_PERFCOUNTER0_HI                                                                           0x3241
8669 #define regSX_PERFCOUNTER0_HI_BASE_IDX                                                                  1
8670 #define regSX_PERFCOUNTER1_LO                                                                           0x3242
8671 #define regSX_PERFCOUNTER1_LO_BASE_IDX                                                                  1
8672 #define regSX_PERFCOUNTER1_HI                                                                           0x3243
8673 #define regSX_PERFCOUNTER1_HI_BASE_IDX                                                                  1
8674 #define regSX_PERFCOUNTER2_LO                                                                           0x3244
8675 #define regSX_PERFCOUNTER2_LO_BASE_IDX                                                                  1
8676 #define regSX_PERFCOUNTER2_HI                                                                           0x3245
8677 #define regSX_PERFCOUNTER2_HI_BASE_IDX                                                                  1
8678 #define regSX_PERFCOUNTER3_LO                                                                           0x3246
8679 #define regSX_PERFCOUNTER3_LO_BASE_IDX                                                                  1
8680 #define regSX_PERFCOUNTER3_HI                                                                           0x3247
8681 #define regSX_PERFCOUNTER3_HI_BASE_IDX                                                                  1
8682 #define regGCEA_PERFCOUNTER2_LO                                                                         0x3260
8683 #define regGCEA_PERFCOUNTER2_LO_BASE_IDX                                                                1
8684 #define regGCEA_PERFCOUNTER2_HI                                                                         0x3261
8685 #define regGCEA_PERFCOUNTER2_HI_BASE_IDX                                                                1
8686 #define regGCEA_PERFCOUNTER_LO                                                                          0x3262
8687 #define regGCEA_PERFCOUNTER_LO_BASE_IDX                                                                 1
8688 #define regGCEA_PERFCOUNTER_HI                                                                          0x3263
8689 #define regGCEA_PERFCOUNTER_HI_BASE_IDX                                                                 1
8690 #define regGDS_PERFCOUNTER0_LO                                                                          0x3280
8691 #define regGDS_PERFCOUNTER0_LO_BASE_IDX                                                                 1
8692 #define regGDS_PERFCOUNTER0_HI                                                                          0x3281
8693 #define regGDS_PERFCOUNTER0_HI_BASE_IDX                                                                 1
8694 #define regGDS_PERFCOUNTER1_LO                                                                          0x3282
8695 #define regGDS_PERFCOUNTER1_LO_BASE_IDX                                                                 1
8696 #define regGDS_PERFCOUNTER1_HI                                                                          0x3283
8697 #define regGDS_PERFCOUNTER1_HI_BASE_IDX                                                                 1
8698 #define regGDS_PERFCOUNTER2_LO                                                                          0x3284
8699 #define regGDS_PERFCOUNTER2_LO_BASE_IDX                                                                 1
8700 #define regGDS_PERFCOUNTER2_HI                                                                          0x3285
8701 #define regGDS_PERFCOUNTER2_HI_BASE_IDX                                                                 1
8702 #define regGDS_PERFCOUNTER3_LO                                                                          0x3286
8703 #define regGDS_PERFCOUNTER3_LO_BASE_IDX                                                                 1
8704 #define regGDS_PERFCOUNTER3_HI                                                                          0x3287
8705 #define regGDS_PERFCOUNTER3_HI_BASE_IDX                                                                 1
8706 #define regTA_PERFCOUNTER0_LO                                                                           0x32c0
8707 #define regTA_PERFCOUNTER0_LO_BASE_IDX                                                                  1
8708 #define regTA_PERFCOUNTER0_HI                                                                           0x32c1
8709 #define regTA_PERFCOUNTER0_HI_BASE_IDX                                                                  1
8710 #define regTA_PERFCOUNTER1_LO                                                                           0x32c2
8711 #define regTA_PERFCOUNTER1_LO_BASE_IDX                                                                  1
8712 #define regTA_PERFCOUNTER1_HI                                                                           0x32c3
8713 #define regTA_PERFCOUNTER1_HI_BASE_IDX                                                                  1
8714 #define regTD_PERFCOUNTER0_LO                                                                           0x3300
8715 #define regTD_PERFCOUNTER0_LO_BASE_IDX                                                                  1
8716 #define regTD_PERFCOUNTER0_HI                                                                           0x3301
8717 #define regTD_PERFCOUNTER0_HI_BASE_IDX                                                                  1
8718 #define regTD_PERFCOUNTER1_LO                                                                           0x3302
8719 #define regTD_PERFCOUNTER1_LO_BASE_IDX                                                                  1
8720 #define regTD_PERFCOUNTER1_HI                                                                           0x3303
8721 #define regTD_PERFCOUNTER1_HI_BASE_IDX                                                                  1
8722 #define regTCP_PERFCOUNTER0_LO                                                                          0x3340
8723 #define regTCP_PERFCOUNTER0_LO_BASE_IDX                                                                 1
8724 #define regTCP_PERFCOUNTER0_HI                                                                          0x3341
8725 #define regTCP_PERFCOUNTER0_HI_BASE_IDX                                                                 1
8726 #define regTCP_PERFCOUNTER1_LO                                                                          0x3342
8727 #define regTCP_PERFCOUNTER1_LO_BASE_IDX                                                                 1
8728 #define regTCP_PERFCOUNTER1_HI                                                                          0x3343
8729 #define regTCP_PERFCOUNTER1_HI_BASE_IDX                                                                 1
8730 #define regTCP_PERFCOUNTER2_LO                                                                          0x3344
8731 #define regTCP_PERFCOUNTER2_LO_BASE_IDX                                                                 1
8732 #define regTCP_PERFCOUNTER2_HI                                                                          0x3345
8733 #define regTCP_PERFCOUNTER2_HI_BASE_IDX                                                                 1
8734 #define regTCP_PERFCOUNTER3_LO                                                                          0x3346
8735 #define regTCP_PERFCOUNTER3_LO_BASE_IDX                                                                 1
8736 #define regTCP_PERFCOUNTER3_HI                                                                          0x3347
8737 #define regTCP_PERFCOUNTER3_HI_BASE_IDX                                                                 1
8738 #define regTCP_PERFCOUNTER_FILTER                                                                       0x3348
8739 #define regTCP_PERFCOUNTER_FILTER_BASE_IDX                                                              1
8740 #define regTCP_PERFCOUNTER_FILTER2                                                                      0x3349
8741 #define regTCP_PERFCOUNTER_FILTER2_BASE_IDX                                                             1
8742 #define regTCP_PERFCOUNTER_FILTER_EN                                                                    0x334a
8743 #define regTCP_PERFCOUNTER_FILTER_EN_BASE_IDX                                                           1
8744 #define regGL2C_PERFCOUNTER0_LO                                                                         0x3380
8745 #define regGL2C_PERFCOUNTER0_LO_BASE_IDX                                                                1
8746 #define regGL2C_PERFCOUNTER0_HI                                                                         0x3381
8747 #define regGL2C_PERFCOUNTER0_HI_BASE_IDX                                                                1
8748 #define regGL2C_PERFCOUNTER1_LO                                                                         0x3382
8749 #define regGL2C_PERFCOUNTER1_LO_BASE_IDX                                                                1
8750 #define regGL2C_PERFCOUNTER1_HI                                                                         0x3383
8751 #define regGL2C_PERFCOUNTER1_HI_BASE_IDX                                                                1
8752 #define regGL2C_PERFCOUNTER2_LO                                                                         0x3384
8753 #define regGL2C_PERFCOUNTER2_LO_BASE_IDX                                                                1
8754 #define regGL2C_PERFCOUNTER2_HI                                                                         0x3385
8755 #define regGL2C_PERFCOUNTER2_HI_BASE_IDX                                                                1
8756 #define regGL2C_PERFCOUNTER3_LO                                                                         0x3386
8757 #define regGL2C_PERFCOUNTER3_LO_BASE_IDX                                                                1
8758 #define regGL2C_PERFCOUNTER3_HI                                                                         0x3387
8759 #define regGL2C_PERFCOUNTER3_HI_BASE_IDX                                                                1
8760 #define regGL2A_PERFCOUNTER0_LO                                                                         0x3390
8761 #define regGL2A_PERFCOUNTER0_LO_BASE_IDX                                                                1
8762 #define regGL2A_PERFCOUNTER0_HI                                                                         0x3391
8763 #define regGL2A_PERFCOUNTER0_HI_BASE_IDX                                                                1
8764 #define regGL2A_PERFCOUNTER1_LO                                                                         0x3392
8765 #define regGL2A_PERFCOUNTER1_LO_BASE_IDX                                                                1
8766 #define regGL2A_PERFCOUNTER1_HI                                                                         0x3393
8767 #define regGL2A_PERFCOUNTER1_HI_BASE_IDX                                                                1
8768 #define regGL2A_PERFCOUNTER2_LO                                                                         0x3394
8769 #define regGL2A_PERFCOUNTER2_LO_BASE_IDX                                                                1
8770 #define regGL2A_PERFCOUNTER2_HI                                                                         0x3395
8771 #define regGL2A_PERFCOUNTER2_HI_BASE_IDX                                                                1
8772 #define regGL2A_PERFCOUNTER3_LO                                                                         0x3396
8773 #define regGL2A_PERFCOUNTER3_LO_BASE_IDX                                                                1
8774 #define regGL2A_PERFCOUNTER3_HI                                                                         0x3397
8775 #define regGL2A_PERFCOUNTER3_HI_BASE_IDX                                                                1
8776 #define regGL1C_PERFCOUNTER0_LO                                                                         0x33a0
8777 #define regGL1C_PERFCOUNTER0_LO_BASE_IDX                                                                1
8778 #define regGL1C_PERFCOUNTER0_HI                                                                         0x33a1
8779 #define regGL1C_PERFCOUNTER0_HI_BASE_IDX                                                                1
8780 #define regGL1C_PERFCOUNTER1_LO                                                                         0x33a2
8781 #define regGL1C_PERFCOUNTER1_LO_BASE_IDX                                                                1
8782 #define regGL1C_PERFCOUNTER1_HI                                                                         0x33a3
8783 #define regGL1C_PERFCOUNTER1_HI_BASE_IDX                                                                1
8784 #define regGL1C_PERFCOUNTER2_LO                                                                         0x33a4
8785 #define regGL1C_PERFCOUNTER2_LO_BASE_IDX                                                                1
8786 #define regGL1C_PERFCOUNTER2_HI                                                                         0x33a5
8787 #define regGL1C_PERFCOUNTER2_HI_BASE_IDX                                                                1
8788 #define regGL1C_PERFCOUNTER3_LO                                                                         0x33a6
8789 #define regGL1C_PERFCOUNTER3_LO_BASE_IDX                                                                1
8790 #define regGL1C_PERFCOUNTER3_HI                                                                         0x33a7
8791 #define regGL1C_PERFCOUNTER3_HI_BASE_IDX                                                                1
8792 #define regCHC_PERFCOUNTER0_LO                                                                          0x33c0
8793 #define regCHC_PERFCOUNTER0_LO_BASE_IDX                                                                 1
8794 #define regCHC_PERFCOUNTER0_HI                                                                          0x33c1
8795 #define regCHC_PERFCOUNTER0_HI_BASE_IDX                                                                 1
8796 #define regCHC_PERFCOUNTER1_LO                                                                          0x33c2
8797 #define regCHC_PERFCOUNTER1_LO_BASE_IDX                                                                 1
8798 #define regCHC_PERFCOUNTER1_HI                                                                          0x33c3
8799 #define regCHC_PERFCOUNTER1_HI_BASE_IDX                                                                 1
8800 #define regCHC_PERFCOUNTER2_LO                                                                          0x33c4
8801 #define regCHC_PERFCOUNTER2_LO_BASE_IDX                                                                 1
8802 #define regCHC_PERFCOUNTER2_HI                                                                          0x33c5
8803 #define regCHC_PERFCOUNTER2_HI_BASE_IDX                                                                 1
8804 #define regCHC_PERFCOUNTER3_LO                                                                          0x33c6
8805 #define regCHC_PERFCOUNTER3_LO_BASE_IDX                                                                 1
8806 #define regCHC_PERFCOUNTER3_HI                                                                          0x33c7
8807 #define regCHC_PERFCOUNTER3_HI_BASE_IDX                                                                 1
8808 #define regCHCG_PERFCOUNTER0_LO                                                                         0x33c8
8809 #define regCHCG_PERFCOUNTER0_LO_BASE_IDX                                                                1
8810 #define regCHCG_PERFCOUNTER0_HI                                                                         0x33c9
8811 #define regCHCG_PERFCOUNTER0_HI_BASE_IDX                                                                1
8812 #define regCHCG_PERFCOUNTER1_LO                                                                         0x33ca
8813 #define regCHCG_PERFCOUNTER1_LO_BASE_IDX                                                                1
8814 #define regCHCG_PERFCOUNTER1_HI                                                                         0x33cb
8815 #define regCHCG_PERFCOUNTER1_HI_BASE_IDX                                                                1
8816 #define regCHCG_PERFCOUNTER2_LO                                                                         0x33cc
8817 #define regCHCG_PERFCOUNTER2_LO_BASE_IDX                                                                1
8818 #define regCHCG_PERFCOUNTER2_HI                                                                         0x33cd
8819 #define regCHCG_PERFCOUNTER2_HI_BASE_IDX                                                                1
8820 #define regCHCG_PERFCOUNTER3_LO                                                                         0x33ce
8821 #define regCHCG_PERFCOUNTER3_LO_BASE_IDX                                                                1
8822 #define regCHCG_PERFCOUNTER3_HI                                                                         0x33cf
8823 #define regCHCG_PERFCOUNTER3_HI_BASE_IDX                                                                1
8824 #define regCB_PERFCOUNTER0_LO                                                                           0x3406
8825 #define regCB_PERFCOUNTER0_LO_BASE_IDX                                                                  1
8826 #define regCB_PERFCOUNTER0_HI                                                                           0x3407
8827 #define regCB_PERFCOUNTER0_HI_BASE_IDX                                                                  1
8828 #define regCB_PERFCOUNTER1_LO                                                                           0x3408
8829 #define regCB_PERFCOUNTER1_LO_BASE_IDX                                                                  1
8830 #define regCB_PERFCOUNTER1_HI                                                                           0x3409
8831 #define regCB_PERFCOUNTER1_HI_BASE_IDX                                                                  1
8832 #define regCB_PERFCOUNTER2_LO                                                                           0x340a
8833 #define regCB_PERFCOUNTER2_LO_BASE_IDX                                                                  1
8834 #define regCB_PERFCOUNTER2_HI                                                                           0x340b
8835 #define regCB_PERFCOUNTER2_HI_BASE_IDX                                                                  1
8836 #define regCB_PERFCOUNTER3_LO                                                                           0x340c
8837 #define regCB_PERFCOUNTER3_LO_BASE_IDX                                                                  1
8838 #define regCB_PERFCOUNTER3_HI                                                                           0x340d
8839 #define regCB_PERFCOUNTER3_HI_BASE_IDX                                                                  1
8840 #define regDB_PERFCOUNTER0_LO                                                                           0x3440
8841 #define regDB_PERFCOUNTER0_LO_BASE_IDX                                                                  1
8842 #define regDB_PERFCOUNTER0_HI                                                                           0x3441
8843 #define regDB_PERFCOUNTER0_HI_BASE_IDX                                                                  1
8844 #define regDB_PERFCOUNTER1_LO                                                                           0x3442
8845 #define regDB_PERFCOUNTER1_LO_BASE_IDX                                                                  1
8846 #define regDB_PERFCOUNTER1_HI                                                                           0x3443
8847 #define regDB_PERFCOUNTER1_HI_BASE_IDX                                                                  1
8848 #define regDB_PERFCOUNTER2_LO                                                                           0x3444
8849 #define regDB_PERFCOUNTER2_LO_BASE_IDX                                                                  1
8850 #define regDB_PERFCOUNTER2_HI                                                                           0x3445
8851 #define regDB_PERFCOUNTER2_HI_BASE_IDX                                                                  1
8852 #define regDB_PERFCOUNTER3_LO                                                                           0x3446
8853 #define regDB_PERFCOUNTER3_LO_BASE_IDX                                                                  1
8854 #define regDB_PERFCOUNTER3_HI                                                                           0x3447
8855 #define regDB_PERFCOUNTER3_HI_BASE_IDX                                                                  1
8856 #define regRLC_PERFCOUNTER0_LO                                                                          0x3480
8857 #define regRLC_PERFCOUNTER0_LO_BASE_IDX                                                                 1
8858 #define regRLC_PERFCOUNTER0_HI                                                                          0x3481
8859 #define regRLC_PERFCOUNTER0_HI_BASE_IDX                                                                 1
8860 #define regRLC_PERFCOUNTER1_LO                                                                          0x3482
8861 #define regRLC_PERFCOUNTER1_LO_BASE_IDX                                                                 1
8862 #define regRLC_PERFCOUNTER1_HI                                                                          0x3483
8863 #define regRLC_PERFCOUNTER1_HI_BASE_IDX                                                                 1
8864 #define regRMI_PERFCOUNTER0_LO                                                                          0x34c0
8865 #define regRMI_PERFCOUNTER0_LO_BASE_IDX                                                                 1
8866 #define regRMI_PERFCOUNTER0_HI                                                                          0x34c1
8867 #define regRMI_PERFCOUNTER0_HI_BASE_IDX                                                                 1
8868 #define regRMI_PERFCOUNTER1_LO                                                                          0x34c2
8869 #define regRMI_PERFCOUNTER1_LO_BASE_IDX                                                                 1
8870 #define regRMI_PERFCOUNTER1_HI                                                                          0x34c3
8871 #define regRMI_PERFCOUNTER1_HI_BASE_IDX                                                                 1
8872 #define regRMI_PERFCOUNTER2_LO                                                                          0x34c4
8873 #define regRMI_PERFCOUNTER2_LO_BASE_IDX                                                                 1
8874 #define regRMI_PERFCOUNTER2_HI                                                                          0x34c5
8875 #define regRMI_PERFCOUNTER2_HI_BASE_IDX                                                                 1
8876 #define regRMI_PERFCOUNTER3_LO                                                                          0x34c6
8877 #define regRMI_PERFCOUNTER3_LO_BASE_IDX                                                                 1
8878 #define regRMI_PERFCOUNTER3_HI                                                                          0x34c7
8879 #define regRMI_PERFCOUNTER3_HI_BASE_IDX                                                                 1
8880 #define regGCR_PERFCOUNTER0_LO                                                                          0x3520
8881 #define regGCR_PERFCOUNTER0_LO_BASE_IDX                                                                 1
8882 #define regGCR_PERFCOUNTER0_HI                                                                          0x3521
8883 #define regGCR_PERFCOUNTER0_HI_BASE_IDX                                                                 1
8884 #define regGCR_PERFCOUNTER1_LO                                                                          0x3522
8885 #define regGCR_PERFCOUNTER1_LO_BASE_IDX                                                                 1
8886 #define regGCR_PERFCOUNTER1_HI                                                                          0x3523
8887 #define regGCR_PERFCOUNTER1_HI_BASE_IDX                                                                 1
8888 #define regPA_PH_PERFCOUNTER0_LO                                                                        0x3580
8889 #define regPA_PH_PERFCOUNTER0_LO_BASE_IDX                                                               1
8890 #define regPA_PH_PERFCOUNTER0_HI                                                                        0x3581
8891 #define regPA_PH_PERFCOUNTER0_HI_BASE_IDX                                                               1
8892 #define regPA_PH_PERFCOUNTER1_LO                                                                        0x3582
8893 #define regPA_PH_PERFCOUNTER1_LO_BASE_IDX                                                               1
8894 #define regPA_PH_PERFCOUNTER1_HI                                                                        0x3583
8895 #define regPA_PH_PERFCOUNTER1_HI_BASE_IDX                                                               1
8896 #define regPA_PH_PERFCOUNTER2_LO                                                                        0x3584
8897 #define regPA_PH_PERFCOUNTER2_LO_BASE_IDX                                                               1
8898 #define regPA_PH_PERFCOUNTER2_HI                                                                        0x3585
8899 #define regPA_PH_PERFCOUNTER2_HI_BASE_IDX                                                               1
8900 #define regPA_PH_PERFCOUNTER3_LO                                                                        0x3586
8901 #define regPA_PH_PERFCOUNTER3_LO_BASE_IDX                                                               1
8902 #define regPA_PH_PERFCOUNTER3_HI                                                                        0x3587
8903 #define regPA_PH_PERFCOUNTER3_HI_BASE_IDX                                                               1
8904 #define regPA_PH_PERFCOUNTER4_LO                                                                        0x3588
8905 #define regPA_PH_PERFCOUNTER4_LO_BASE_IDX                                                               1
8906 #define regPA_PH_PERFCOUNTER4_HI                                                                        0x3589
8907 #define regPA_PH_PERFCOUNTER4_HI_BASE_IDX                                                               1
8908 #define regPA_PH_PERFCOUNTER5_LO                                                                        0x358a
8909 #define regPA_PH_PERFCOUNTER5_LO_BASE_IDX                                                               1
8910 #define regPA_PH_PERFCOUNTER5_HI                                                                        0x358b
8911 #define regPA_PH_PERFCOUNTER5_HI_BASE_IDX                                                               1
8912 #define regPA_PH_PERFCOUNTER6_LO                                                                        0x358c
8913 #define regPA_PH_PERFCOUNTER6_LO_BASE_IDX                                                               1
8914 #define regPA_PH_PERFCOUNTER6_HI                                                                        0x358d
8915 #define regPA_PH_PERFCOUNTER6_HI_BASE_IDX                                                               1
8916 #define regPA_PH_PERFCOUNTER7_LO                                                                        0x358e
8917 #define regPA_PH_PERFCOUNTER7_LO_BASE_IDX                                                               1
8918 #define regPA_PH_PERFCOUNTER7_HI                                                                        0x358f
8919 #define regPA_PH_PERFCOUNTER7_HI_BASE_IDX                                                               1
8920 #define regUTCL1_PERFCOUNTER0_LO                                                                        0x35a0
8921 #define regUTCL1_PERFCOUNTER0_LO_BASE_IDX                                                               1
8922 #define regUTCL1_PERFCOUNTER0_HI                                                                        0x35a1
8923 #define regUTCL1_PERFCOUNTER0_HI_BASE_IDX                                                               1
8924 #define regUTCL1_PERFCOUNTER1_LO                                                                        0x35a2
8925 #define regUTCL1_PERFCOUNTER1_LO_BASE_IDX                                                               1
8926 #define regUTCL1_PERFCOUNTER1_HI                                                                        0x35a3
8927 #define regUTCL1_PERFCOUNTER1_HI_BASE_IDX                                                               1
8928 #define regUTCL1_PERFCOUNTER2_LO                                                                        0x35a4
8929 #define regUTCL1_PERFCOUNTER2_LO_BASE_IDX                                                               1
8930 #define regUTCL1_PERFCOUNTER2_HI                                                                        0x35a5
8931 #define regUTCL1_PERFCOUNTER2_HI_BASE_IDX                                                               1
8932 #define regUTCL1_PERFCOUNTER3_LO                                                                        0x35a6
8933 #define regUTCL1_PERFCOUNTER3_LO_BASE_IDX                                                               1
8934 #define regUTCL1_PERFCOUNTER3_HI                                                                        0x35a7
8935 #define regUTCL1_PERFCOUNTER3_HI_BASE_IDX                                                               1
8936 #define regGL1A_PERFCOUNTER0_LO                                                                         0x35c0
8937 #define regGL1A_PERFCOUNTER0_LO_BASE_IDX                                                                1
8938 #define regGL1A_PERFCOUNTER0_HI                                                                         0x35c1
8939 #define regGL1A_PERFCOUNTER0_HI_BASE_IDX                                                                1
8940 #define regGL1A_PERFCOUNTER1_LO                                                                         0x35c2
8941 #define regGL1A_PERFCOUNTER1_LO_BASE_IDX                                                                1
8942 #define regGL1A_PERFCOUNTER1_HI                                                                         0x35c3
8943 #define regGL1A_PERFCOUNTER1_HI_BASE_IDX                                                                1
8944 #define regGL1A_PERFCOUNTER2_LO                                                                         0x35c4
8945 #define regGL1A_PERFCOUNTER2_LO_BASE_IDX                                                                1
8946 #define regGL1A_PERFCOUNTER2_HI                                                                         0x35c5
8947 #define regGL1A_PERFCOUNTER2_HI_BASE_IDX                                                                1
8948 #define regGL1A_PERFCOUNTER3_LO                                                                         0x35c6
8949 #define regGL1A_PERFCOUNTER3_LO_BASE_IDX                                                                1
8950 #define regGL1A_PERFCOUNTER3_HI                                                                         0x35c7
8951 #define regGL1A_PERFCOUNTER3_HI_BASE_IDX                                                                1
8952 #define regGL1H_PERFCOUNTER0_LO                                                                         0x35d0
8953 #define regGL1H_PERFCOUNTER0_LO_BASE_IDX                                                                1
8954 #define regGL1H_PERFCOUNTER0_HI                                                                         0x35d1
8955 #define regGL1H_PERFCOUNTER0_HI_BASE_IDX                                                                1
8956 #define regGL1H_PERFCOUNTER1_LO                                                                         0x35d2
8957 #define regGL1H_PERFCOUNTER1_LO_BASE_IDX                                                                1
8958 #define regGL1H_PERFCOUNTER1_HI                                                                         0x35d3
8959 #define regGL1H_PERFCOUNTER1_HI_BASE_IDX                                                                1
8960 #define regGL1H_PERFCOUNTER2_LO                                                                         0x35d4
8961 #define regGL1H_PERFCOUNTER2_LO_BASE_IDX                                                                1
8962 #define regGL1H_PERFCOUNTER2_HI                                                                         0x35d5
8963 #define regGL1H_PERFCOUNTER2_HI_BASE_IDX                                                                1
8964 #define regGL1H_PERFCOUNTER3_LO                                                                         0x35d6
8965 #define regGL1H_PERFCOUNTER3_LO_BASE_IDX                                                                1
8966 #define regGL1H_PERFCOUNTER3_HI                                                                         0x35d7
8967 #define regGL1H_PERFCOUNTER3_HI_BASE_IDX                                                                1
8968 #define regCHA_PERFCOUNTER0_LO                                                                          0x3600
8969 #define regCHA_PERFCOUNTER0_LO_BASE_IDX                                                                 1
8970 #define regCHA_PERFCOUNTER0_HI                                                                          0x3601
8971 #define regCHA_PERFCOUNTER0_HI_BASE_IDX                                                                 1
8972 #define regCHA_PERFCOUNTER1_LO                                                                          0x3602
8973 #define regCHA_PERFCOUNTER1_LO_BASE_IDX                                                                 1
8974 #define regCHA_PERFCOUNTER1_HI                                                                          0x3603
8975 #define regCHA_PERFCOUNTER1_HI_BASE_IDX                                                                 1
8976 #define regCHA_PERFCOUNTER2_LO                                                                          0x3604
8977 #define regCHA_PERFCOUNTER2_LO_BASE_IDX                                                                 1
8978 #define regCHA_PERFCOUNTER2_HI                                                                          0x3605
8979 #define regCHA_PERFCOUNTER2_HI_BASE_IDX                                                                 1
8980 #define regCHA_PERFCOUNTER3_LO                                                                          0x3606
8981 #define regCHA_PERFCOUNTER3_LO_BASE_IDX                                                                 1
8982 #define regCHA_PERFCOUNTER3_HI                                                                          0x3607
8983 #define regCHA_PERFCOUNTER3_HI_BASE_IDX                                                                 1
8984 #define regGUS_PERFCOUNTER2_LO                                                                          0x3640
8985 #define regGUS_PERFCOUNTER2_LO_BASE_IDX                                                                 1
8986 #define regGUS_PERFCOUNTER2_HI                                                                          0x3641
8987 #define regGUS_PERFCOUNTER2_HI_BASE_IDX                                                                 1
8988 #define regGUS_PERFCOUNTER_LO                                                                           0x3642
8989 #define regGUS_PERFCOUNTER_LO_BASE_IDX                                                                  1
8990 #define regGUS_PERFCOUNTER_HI                                                                           0x3643
8991 #define regGUS_PERFCOUNTER_HI_BASE_IDX                                                                  1
8992 
8993 
8994 // addressBlock: gc_perfsdec
8995 // base address: 0x36000
8996 #define regCPG_PERFCOUNTER1_SELECT                                                                      0x3800
8997 #define regCPG_PERFCOUNTER1_SELECT_BASE_IDX                                                             1
8998 #define regCPG_PERFCOUNTER0_SELECT1                                                                     0x3801
8999 #define regCPG_PERFCOUNTER0_SELECT1_BASE_IDX                                                            1
9000 #define regCPG_PERFCOUNTER0_SELECT                                                                      0x3802
9001 #define regCPG_PERFCOUNTER0_SELECT_BASE_IDX                                                             1
9002 #define regCPC_PERFCOUNTER1_SELECT                                                                      0x3803
9003 #define regCPC_PERFCOUNTER1_SELECT_BASE_IDX                                                             1
9004 #define regCPC_PERFCOUNTER0_SELECT1                                                                     0x3804
9005 #define regCPC_PERFCOUNTER0_SELECT1_BASE_IDX                                                            1
9006 #define regCPF_PERFCOUNTER1_SELECT                                                                      0x3805
9007 #define regCPF_PERFCOUNTER1_SELECT_BASE_IDX                                                             1
9008 #define regCPF_PERFCOUNTER0_SELECT1                                                                     0x3806
9009 #define regCPF_PERFCOUNTER0_SELECT1_BASE_IDX                                                            1
9010 #define regCPF_PERFCOUNTER0_SELECT                                                                      0x3807
9011 #define regCPF_PERFCOUNTER0_SELECT_BASE_IDX                                                             1
9012 #define regCP_PERFMON_CNTL                                                                              0x3808
9013 #define regCP_PERFMON_CNTL_BASE_IDX                                                                     1
9014 #define regCPC_PERFCOUNTER0_SELECT                                                                      0x3809
9015 #define regCPC_PERFCOUNTER0_SELECT_BASE_IDX                                                             1
9016 #define regCPF_TC_PERF_COUNTER_WINDOW_SELECT                                                            0x380a
9017 #define regCPF_TC_PERF_COUNTER_WINDOW_SELECT_BASE_IDX                                                   1
9018 #define regCPG_TC_PERF_COUNTER_WINDOW_SELECT                                                            0x380b
9019 #define regCPG_TC_PERF_COUNTER_WINDOW_SELECT_BASE_IDX                                                   1
9020 #define regCPF_LATENCY_STATS_SELECT                                                                     0x380c
9021 #define regCPF_LATENCY_STATS_SELECT_BASE_IDX                                                            1
9022 #define regCPG_LATENCY_STATS_SELECT                                                                     0x380d
9023 #define regCPG_LATENCY_STATS_SELECT_BASE_IDX                                                            1
9024 #define regCPC_LATENCY_STATS_SELECT                                                                     0x380e
9025 #define regCPC_LATENCY_STATS_SELECT_BASE_IDX                                                            1
9026 #define regCPC_TC_PERF_COUNTER_WINDOW_SELECT                                                            0x380f
9027 #define regCPC_TC_PERF_COUNTER_WINDOW_SELECT_BASE_IDX                                                   1
9028 #define regCP_DRAW_OBJECT                                                                               0x3810
9029 #define regCP_DRAW_OBJECT_BASE_IDX                                                                      1
9030 #define regCP_DRAW_OBJECT_COUNTER                                                                       0x3811
9031 #define regCP_DRAW_OBJECT_COUNTER_BASE_IDX                                                              1
9032 #define regCP_DRAW_WINDOW_MASK_HI                                                                       0x3812
9033 #define regCP_DRAW_WINDOW_MASK_HI_BASE_IDX                                                              1
9034 #define regCP_DRAW_WINDOW_HI                                                                            0x3813
9035 #define regCP_DRAW_WINDOW_HI_BASE_IDX                                                                   1
9036 #define regCP_DRAW_WINDOW_LO                                                                            0x3814
9037 #define regCP_DRAW_WINDOW_LO_BASE_IDX                                                                   1
9038 #define regCP_DRAW_WINDOW_CNTL                                                                          0x3815
9039 #define regCP_DRAW_WINDOW_CNTL_BASE_IDX                                                                 1
9040 #define regGRBM_PERFCOUNTER0_SELECT                                                                     0x3840
9041 #define regGRBM_PERFCOUNTER0_SELECT_BASE_IDX                                                            1
9042 #define regGRBM_PERFCOUNTER1_SELECT                                                                     0x3841
9043 #define regGRBM_PERFCOUNTER1_SELECT_BASE_IDX                                                            1
9044 #define regGRBM_SE0_PERFCOUNTER_SELECT                                                                  0x3842
9045 #define regGRBM_SE0_PERFCOUNTER_SELECT_BASE_IDX                                                         1
9046 #define regGRBM_SE1_PERFCOUNTER_SELECT                                                                  0x3843
9047 #define regGRBM_SE1_PERFCOUNTER_SELECT_BASE_IDX                                                         1
9048 #define regGRBM_SE2_PERFCOUNTER_SELECT                                                                  0x3844
9049 #define regGRBM_SE2_PERFCOUNTER_SELECT_BASE_IDX                                                         1
9050 #define regGRBM_SE3_PERFCOUNTER_SELECT                                                                  0x3845
9051 #define regGRBM_SE3_PERFCOUNTER_SELECT_BASE_IDX                                                         1
9052 #define regGRBM_SE4_PERFCOUNTER_SELECT                                                                  0x3846
9053 #define regGRBM_SE4_PERFCOUNTER_SELECT_BASE_IDX                                                         1
9054 #define regGRBM_SE5_PERFCOUNTER_SELECT                                                                  0x3847
9055 #define regGRBM_SE5_PERFCOUNTER_SELECT_BASE_IDX                                                         1
9056 #define regGRBM_SE6_PERFCOUNTER_SELECT                                                                  0x3848
9057 #define regGRBM_SE6_PERFCOUNTER_SELECT_BASE_IDX                                                         1
9058 #define regGRBM_PERFCOUNTER0_SELECT_HI                                                                  0x384d
9059 #define regGRBM_PERFCOUNTER0_SELECT_HI_BASE_IDX                                                         1
9060 #define regGRBM_PERFCOUNTER1_SELECT_HI                                                                  0x384e
9061 #define regGRBM_PERFCOUNTER1_SELECT_HI_BASE_IDX                                                         1
9062 #define regGE1_PERFCOUNTER0_SELECT                                                                      0x38a4
9063 #define regGE1_PERFCOUNTER0_SELECT_BASE_IDX                                                             1
9064 #define regGE1_PERFCOUNTER0_SELECT1                                                                     0x38a5
9065 #define regGE1_PERFCOUNTER0_SELECT1_BASE_IDX                                                            1
9066 #define regGE1_PERFCOUNTER1_SELECT                                                                      0x38a6
9067 #define regGE1_PERFCOUNTER1_SELECT_BASE_IDX                                                             1
9068 #define regGE1_PERFCOUNTER1_SELECT1                                                                     0x38a7
9069 #define regGE1_PERFCOUNTER1_SELECT1_BASE_IDX                                                            1
9070 #define regGE1_PERFCOUNTER2_SELECT                                                                      0x38a8
9071 #define regGE1_PERFCOUNTER2_SELECT_BASE_IDX                                                             1
9072 #define regGE1_PERFCOUNTER2_SELECT1                                                                     0x38a9
9073 #define regGE1_PERFCOUNTER2_SELECT1_BASE_IDX                                                            1
9074 #define regGE1_PERFCOUNTER3_SELECT                                                                      0x38aa
9075 #define regGE1_PERFCOUNTER3_SELECT_BASE_IDX                                                             1
9076 #define regGE1_PERFCOUNTER3_SELECT1                                                                     0x38ab
9077 #define regGE1_PERFCOUNTER3_SELECT1_BASE_IDX                                                            1
9078 #define regGE2_DIST_PERFCOUNTER0_SELECT                                                                 0x38ac
9079 #define regGE2_DIST_PERFCOUNTER0_SELECT_BASE_IDX                                                        1
9080 #define regGE2_DIST_PERFCOUNTER0_SELECT1                                                                0x38ad
9081 #define regGE2_DIST_PERFCOUNTER0_SELECT1_BASE_IDX                                                       1
9082 #define regGE2_DIST_PERFCOUNTER1_SELECT                                                                 0x38ae
9083 #define regGE2_DIST_PERFCOUNTER1_SELECT_BASE_IDX                                                        1
9084 #define regGE2_DIST_PERFCOUNTER1_SELECT1                                                                0x38af
9085 #define regGE2_DIST_PERFCOUNTER1_SELECT1_BASE_IDX                                                       1
9086 #define regGE2_DIST_PERFCOUNTER2_SELECT                                                                 0x38b0
9087 #define regGE2_DIST_PERFCOUNTER2_SELECT_BASE_IDX                                                        1
9088 #define regGE2_DIST_PERFCOUNTER2_SELECT1                                                                0x38b1
9089 #define regGE2_DIST_PERFCOUNTER2_SELECT1_BASE_IDX                                                       1
9090 #define regGE2_DIST_PERFCOUNTER3_SELECT                                                                 0x38b2
9091 #define regGE2_DIST_PERFCOUNTER3_SELECT_BASE_IDX                                                        1
9092 #define regGE2_DIST_PERFCOUNTER3_SELECT1                                                                0x38b3
9093 #define regGE2_DIST_PERFCOUNTER3_SELECT1_BASE_IDX                                                       1
9094 #define regGE2_SE_PERFCOUNTER0_SELECT                                                                   0x38b4
9095 #define regGE2_SE_PERFCOUNTER0_SELECT_BASE_IDX                                                          1
9096 #define regGE2_SE_PERFCOUNTER0_SELECT1                                                                  0x38b5
9097 #define regGE2_SE_PERFCOUNTER0_SELECT1_BASE_IDX                                                         1
9098 #define regGE2_SE_PERFCOUNTER1_SELECT                                                                   0x38b6
9099 #define regGE2_SE_PERFCOUNTER1_SELECT_BASE_IDX                                                          1
9100 #define regGE2_SE_PERFCOUNTER1_SELECT1                                                                  0x38b7
9101 #define regGE2_SE_PERFCOUNTER1_SELECT1_BASE_IDX                                                         1
9102 #define regGE2_SE_PERFCOUNTER2_SELECT                                                                   0x38b8
9103 #define regGE2_SE_PERFCOUNTER2_SELECT_BASE_IDX                                                          1
9104 #define regGE2_SE_PERFCOUNTER2_SELECT1                                                                  0x38b9
9105 #define regGE2_SE_PERFCOUNTER2_SELECT1_BASE_IDX                                                         1
9106 #define regGE2_SE_PERFCOUNTER3_SELECT                                                                   0x38ba
9107 #define regGE2_SE_PERFCOUNTER3_SELECT_BASE_IDX                                                          1
9108 #define regGE2_SE_PERFCOUNTER3_SELECT1                                                                  0x38bb
9109 #define regGE2_SE_PERFCOUNTER3_SELECT1_BASE_IDX                                                         1
9110 #define regPA_SU_PERFCOUNTER0_SELECT                                                                    0x3900
9111 #define regPA_SU_PERFCOUNTER0_SELECT_BASE_IDX                                                           1
9112 #define regPA_SU_PERFCOUNTER0_SELECT1                                                                   0x3901
9113 #define regPA_SU_PERFCOUNTER0_SELECT1_BASE_IDX                                                          1
9114 #define regPA_SU_PERFCOUNTER1_SELECT                                                                    0x3902
9115 #define regPA_SU_PERFCOUNTER1_SELECT_BASE_IDX                                                           1
9116 #define regPA_SU_PERFCOUNTER1_SELECT1                                                                   0x3903
9117 #define regPA_SU_PERFCOUNTER1_SELECT1_BASE_IDX                                                          1
9118 #define regPA_SU_PERFCOUNTER2_SELECT                                                                    0x3904
9119 #define regPA_SU_PERFCOUNTER2_SELECT_BASE_IDX                                                           1
9120 #define regPA_SU_PERFCOUNTER2_SELECT1                                                                   0x3905
9121 #define regPA_SU_PERFCOUNTER2_SELECT1_BASE_IDX                                                          1
9122 #define regPA_SU_PERFCOUNTER3_SELECT                                                                    0x3906
9123 #define regPA_SU_PERFCOUNTER3_SELECT_BASE_IDX                                                           1
9124 #define regPA_SU_PERFCOUNTER3_SELECT1                                                                   0x3907
9125 #define regPA_SU_PERFCOUNTER3_SELECT1_BASE_IDX                                                          1
9126 #define regPA_SC_PERFCOUNTER0_SELECT                                                                    0x3940
9127 #define regPA_SC_PERFCOUNTER0_SELECT_BASE_IDX                                                           1
9128 #define regPA_SC_PERFCOUNTER0_SELECT1                                                                   0x3941
9129 #define regPA_SC_PERFCOUNTER0_SELECT1_BASE_IDX                                                          1
9130 #define regPA_SC_PERFCOUNTER1_SELECT                                                                    0x3942
9131 #define regPA_SC_PERFCOUNTER1_SELECT_BASE_IDX                                                           1
9132 #define regPA_SC_PERFCOUNTER2_SELECT                                                                    0x3943
9133 #define regPA_SC_PERFCOUNTER2_SELECT_BASE_IDX                                                           1
9134 #define regPA_SC_PERFCOUNTER3_SELECT                                                                    0x3944
9135 #define regPA_SC_PERFCOUNTER3_SELECT_BASE_IDX                                                           1
9136 #define regPA_SC_PERFCOUNTER4_SELECT                                                                    0x3945
9137 #define regPA_SC_PERFCOUNTER4_SELECT_BASE_IDX                                                           1
9138 #define regPA_SC_PERFCOUNTER5_SELECT                                                                    0x3946
9139 #define regPA_SC_PERFCOUNTER5_SELECT_BASE_IDX                                                           1
9140 #define regPA_SC_PERFCOUNTER6_SELECT                                                                    0x3947
9141 #define regPA_SC_PERFCOUNTER6_SELECT_BASE_IDX                                                           1
9142 #define regPA_SC_PERFCOUNTER7_SELECT                                                                    0x3948
9143 #define regPA_SC_PERFCOUNTER7_SELECT_BASE_IDX                                                           1
9144 #define regSPI_PERFCOUNTER0_SELECT                                                                      0x3980
9145 #define regSPI_PERFCOUNTER0_SELECT_BASE_IDX                                                             1
9146 #define regSPI_PERFCOUNTER1_SELECT                                                                      0x3981
9147 #define regSPI_PERFCOUNTER1_SELECT_BASE_IDX                                                             1
9148 #define regSPI_PERFCOUNTER2_SELECT                                                                      0x3982
9149 #define regSPI_PERFCOUNTER2_SELECT_BASE_IDX                                                             1
9150 #define regSPI_PERFCOUNTER3_SELECT                                                                      0x3983
9151 #define regSPI_PERFCOUNTER3_SELECT_BASE_IDX                                                             1
9152 #define regSPI_PERFCOUNTER0_SELECT1                                                                     0x3984
9153 #define regSPI_PERFCOUNTER0_SELECT1_BASE_IDX                                                            1
9154 #define regSPI_PERFCOUNTER1_SELECT1                                                                     0x3985
9155 #define regSPI_PERFCOUNTER1_SELECT1_BASE_IDX                                                            1
9156 #define regSPI_PERFCOUNTER2_SELECT1                                                                     0x3986
9157 #define regSPI_PERFCOUNTER2_SELECT1_BASE_IDX                                                            1
9158 #define regSPI_PERFCOUNTER3_SELECT1                                                                     0x3987
9159 #define regSPI_PERFCOUNTER3_SELECT1_BASE_IDX                                                            1
9160 #define regSPI_PERFCOUNTER4_SELECT                                                                      0x3988
9161 #define regSPI_PERFCOUNTER4_SELECT_BASE_IDX                                                             1
9162 #define regSPI_PERFCOUNTER5_SELECT                                                                      0x3989
9163 #define regSPI_PERFCOUNTER5_SELECT_BASE_IDX                                                             1
9164 #define regSPI_PERFCOUNTER_BINS                                                                         0x398a
9165 #define regSPI_PERFCOUNTER_BINS_BASE_IDX                                                                1
9166 #define regPC_PERFCOUNTER0_SELECT                                                                       0x398c
9167 #define regPC_PERFCOUNTER0_SELECT_BASE_IDX                                                              1
9168 #define regPC_PERFCOUNTER1_SELECT                                                                       0x398d
9169 #define regPC_PERFCOUNTER1_SELECT_BASE_IDX                                                              1
9170 #define regPC_PERFCOUNTER2_SELECT                                                                       0x398e
9171 #define regPC_PERFCOUNTER2_SELECT_BASE_IDX                                                              1
9172 #define regPC_PERFCOUNTER3_SELECT                                                                       0x398f
9173 #define regPC_PERFCOUNTER3_SELECT_BASE_IDX                                                              1
9174 #define regPC_PERFCOUNTER0_SELECT1                                                                      0x3990
9175 #define regPC_PERFCOUNTER0_SELECT1_BASE_IDX                                                             1
9176 #define regPC_PERFCOUNTER1_SELECT1                                                                      0x3991
9177 #define regPC_PERFCOUNTER1_SELECT1_BASE_IDX                                                             1
9178 #define regPC_PERFCOUNTER2_SELECT1                                                                      0x3992
9179 #define regPC_PERFCOUNTER2_SELECT1_BASE_IDX                                                             1
9180 #define regPC_PERFCOUNTER3_SELECT1                                                                      0x3993
9181 #define regPC_PERFCOUNTER3_SELECT1_BASE_IDX                                                             1
9182 #define regSQ_PERFCOUNTER0_SELECT                                                                       0x39c0
9183 #define regSQ_PERFCOUNTER0_SELECT_BASE_IDX                                                              1
9184 #define regSQ_PERFCOUNTER1_SELECT                                                                       0x39c1
9185 #define regSQ_PERFCOUNTER1_SELECT_BASE_IDX                                                              1
9186 #define regSQ_PERFCOUNTER2_SELECT                                                                       0x39c2
9187 #define regSQ_PERFCOUNTER2_SELECT_BASE_IDX                                                              1
9188 #define regSQ_PERFCOUNTER3_SELECT                                                                       0x39c3
9189 #define regSQ_PERFCOUNTER3_SELECT_BASE_IDX                                                              1
9190 #define regSQ_PERFCOUNTER4_SELECT                                                                       0x39c4
9191 #define regSQ_PERFCOUNTER4_SELECT_BASE_IDX                                                              1
9192 #define regSQ_PERFCOUNTER5_SELECT                                                                       0x39c5
9193 #define regSQ_PERFCOUNTER5_SELECT_BASE_IDX                                                              1
9194 #define regSQ_PERFCOUNTER6_SELECT                                                                       0x39c6
9195 #define regSQ_PERFCOUNTER6_SELECT_BASE_IDX                                                              1
9196 #define regSQ_PERFCOUNTER7_SELECT                                                                       0x39c7
9197 #define regSQ_PERFCOUNTER7_SELECT_BASE_IDX                                                              1
9198 #define regSQ_PERFCOUNTER8_SELECT                                                                       0x39c8
9199 #define regSQ_PERFCOUNTER8_SELECT_BASE_IDX                                                              1
9200 #define regSQ_PERFCOUNTER9_SELECT                                                                       0x39c9
9201 #define regSQ_PERFCOUNTER9_SELECT_BASE_IDX                                                              1
9202 #define regSQ_PERFCOUNTER10_SELECT                                                                      0x39ca
9203 #define regSQ_PERFCOUNTER10_SELECT_BASE_IDX                                                             1
9204 #define regSQ_PERFCOUNTER11_SELECT                                                                      0x39cb
9205 #define regSQ_PERFCOUNTER11_SELECT_BASE_IDX                                                             1
9206 #define regSQ_PERFCOUNTER12_SELECT                                                                      0x39cc
9207 #define regSQ_PERFCOUNTER12_SELECT_BASE_IDX                                                             1
9208 #define regSQ_PERFCOUNTER13_SELECT                                                                      0x39cd
9209 #define regSQ_PERFCOUNTER13_SELECT_BASE_IDX                                                             1
9210 #define regSQ_PERFCOUNTER14_SELECT                                                                      0x39ce
9211 #define regSQ_PERFCOUNTER14_SELECT_BASE_IDX                                                             1
9212 #define regSQ_PERFCOUNTER15_SELECT                                                                      0x39cf
9213 #define regSQ_PERFCOUNTER15_SELECT_BASE_IDX                                                             1
9214 #define regSQG_PERFCOUNTER0_SELECT                                                                      0x39d0
9215 #define regSQG_PERFCOUNTER0_SELECT_BASE_IDX                                                             1
9216 #define regSQG_PERFCOUNTER1_SELECT                                                                      0x39d1
9217 #define regSQG_PERFCOUNTER1_SELECT_BASE_IDX                                                             1
9218 #define regSQG_PERFCOUNTER2_SELECT                                                                      0x39d2
9219 #define regSQG_PERFCOUNTER2_SELECT_BASE_IDX                                                             1
9220 #define regSQG_PERFCOUNTER3_SELECT                                                                      0x39d3
9221 #define regSQG_PERFCOUNTER3_SELECT_BASE_IDX                                                             1
9222 #define regSQG_PERFCOUNTER4_SELECT                                                                      0x39d4
9223 #define regSQG_PERFCOUNTER4_SELECT_BASE_IDX                                                             1
9224 #define regSQG_PERFCOUNTER5_SELECT                                                                      0x39d5
9225 #define regSQG_PERFCOUNTER5_SELECT_BASE_IDX                                                             1
9226 #define regSQG_PERFCOUNTER6_SELECT                                                                      0x39d6
9227 #define regSQG_PERFCOUNTER6_SELECT_BASE_IDX                                                             1
9228 #define regSQG_PERFCOUNTER7_SELECT                                                                      0x39d7
9229 #define regSQG_PERFCOUNTER7_SELECT_BASE_IDX                                                             1
9230 #define regSQG_PERFCOUNTER_CTRL                                                                         0x39d8
9231 #define regSQG_PERFCOUNTER_CTRL_BASE_IDX                                                                1
9232 #define regSQG_PERFCOUNTER_CTRL2                                                                        0x39da
9233 #define regSQG_PERFCOUNTER_CTRL2_BASE_IDX                                                               1
9234 #define regSQG_PERF_SAMPLE_FINISH                                                                       0x39db
9235 #define regSQG_PERF_SAMPLE_FINISH_BASE_IDX                                                              1
9236 #define regSQ_PERFCOUNTER_CTRL                                                                          0x39e0
9237 #define regSQ_PERFCOUNTER_CTRL_BASE_IDX                                                                 1
9238 #define regSQ_PERFCOUNTER_CTRL2                                                                         0x39e2
9239 #define regSQ_PERFCOUNTER_CTRL2_BASE_IDX                                                                1
9240 #define regSQ_THREAD_TRACE_BUF0_BASE                                                                    0x39e8
9241 #define regSQ_THREAD_TRACE_BUF0_BASE_BASE_IDX                                                           1
9242 #define regSQ_THREAD_TRACE_BUF0_SIZE                                                                    0x39e9
9243 #define regSQ_THREAD_TRACE_BUF0_SIZE_BASE_IDX                                                           1
9244 #define regSQ_THREAD_TRACE_BUF1_BASE                                                                    0x39ea
9245 #define regSQ_THREAD_TRACE_BUF1_BASE_BASE_IDX                                                           1
9246 #define regSQ_THREAD_TRACE_BUF1_SIZE                                                                    0x39eb
9247 #define regSQ_THREAD_TRACE_BUF1_SIZE_BASE_IDX                                                           1
9248 #define regSQ_THREAD_TRACE_CTRL                                                                         0x39ec
9249 #define regSQ_THREAD_TRACE_CTRL_BASE_IDX                                                                1
9250 #define regSQ_THREAD_TRACE_MASK                                                                         0x39ed
9251 #define regSQ_THREAD_TRACE_MASK_BASE_IDX                                                                1
9252 #define regSQ_THREAD_TRACE_TOKEN_MASK                                                                   0x39ee
9253 #define regSQ_THREAD_TRACE_TOKEN_MASK_BASE_IDX                                                          1
9254 #define regSQ_THREAD_TRACE_WPTR                                                                         0x39ef
9255 #define regSQ_THREAD_TRACE_WPTR_BASE_IDX                                                                1
9256 #define regSQ_THREAD_TRACE_STATUS                                                                       0x39f4
9257 #define regSQ_THREAD_TRACE_STATUS_BASE_IDX                                                              1
9258 #define regSQ_THREAD_TRACE_STATUS2                                                                      0x39f5
9259 #define regSQ_THREAD_TRACE_STATUS2_BASE_IDX                                                             1
9260 #define regSQ_THREAD_TRACE_GFX_DRAW_CNTR                                                                0x39f6
9261 #define regSQ_THREAD_TRACE_GFX_DRAW_CNTR_BASE_IDX                                                       1
9262 #define regSQ_THREAD_TRACE_GFX_MARKER_CNTR                                                              0x39f7
9263 #define regSQ_THREAD_TRACE_GFX_MARKER_CNTR_BASE_IDX                                                     1
9264 #define regSQ_THREAD_TRACE_HP3D_DRAW_CNTR                                                               0x39f8
9265 #define regSQ_THREAD_TRACE_HP3D_DRAW_CNTR_BASE_IDX                                                      1
9266 #define regSQ_THREAD_TRACE_HP3D_MARKER_CNTR                                                             0x39f9
9267 #define regSQ_THREAD_TRACE_HP3D_MARKER_CNTR_BASE_IDX                                                    1
9268 #define regSQ_THREAD_TRACE_DROPPED_CNTR                                                                 0x39fa
9269 #define regSQ_THREAD_TRACE_DROPPED_CNTR_BASE_IDX                                                        1
9270 #define regGCEA_PERFCOUNTER2_SELECT                                                                     0x3a00
9271 #define regGCEA_PERFCOUNTER2_SELECT_BASE_IDX                                                            1
9272 #define regGCEA_PERFCOUNTER2_SELECT1                                                                    0x3a01
9273 #define regGCEA_PERFCOUNTER2_SELECT1_BASE_IDX                                                           1
9274 #define regGCEA_PERFCOUNTER2_MODE                                                                       0x3a02
9275 #define regGCEA_PERFCOUNTER2_MODE_BASE_IDX                                                              1
9276 #define regGCEA_PERFCOUNTER0_CFG                                                                        0x3a03
9277 #define regGCEA_PERFCOUNTER0_CFG_BASE_IDX                                                               1
9278 #define regGCEA_PERFCOUNTER1_CFG                                                                        0x3a04
9279 #define regGCEA_PERFCOUNTER1_CFG_BASE_IDX                                                               1
9280 #define regGCEA_PERFCOUNTER_RSLT_CNTL                                                                   0x3a05
9281 #define regGCEA_PERFCOUNTER_RSLT_CNTL_BASE_IDX                                                          1
9282 #define regSX_PERFCOUNTER0_SELECT                                                                       0x3a40
9283 #define regSX_PERFCOUNTER0_SELECT_BASE_IDX                                                              1
9284 #define regSX_PERFCOUNTER1_SELECT                                                                       0x3a41
9285 #define regSX_PERFCOUNTER1_SELECT_BASE_IDX                                                              1
9286 #define regSX_PERFCOUNTER2_SELECT                                                                       0x3a42
9287 #define regSX_PERFCOUNTER2_SELECT_BASE_IDX                                                              1
9288 #define regSX_PERFCOUNTER3_SELECT                                                                       0x3a43
9289 #define regSX_PERFCOUNTER3_SELECT_BASE_IDX                                                              1
9290 #define regSX_PERFCOUNTER0_SELECT1                                                                      0x3a44
9291 #define regSX_PERFCOUNTER0_SELECT1_BASE_IDX                                                             1
9292 #define regSX_PERFCOUNTER1_SELECT1                                                                      0x3a45
9293 #define regSX_PERFCOUNTER1_SELECT1_BASE_IDX                                                             1
9294 #define regGDS_PERFCOUNTER0_SELECT                                                                      0x3a80
9295 #define regGDS_PERFCOUNTER0_SELECT_BASE_IDX                                                             1
9296 #define regGDS_PERFCOUNTER1_SELECT                                                                      0x3a81
9297 #define regGDS_PERFCOUNTER1_SELECT_BASE_IDX                                                             1
9298 #define regGDS_PERFCOUNTER2_SELECT                                                                      0x3a82
9299 #define regGDS_PERFCOUNTER2_SELECT_BASE_IDX                                                             1
9300 #define regGDS_PERFCOUNTER3_SELECT                                                                      0x3a83
9301 #define regGDS_PERFCOUNTER3_SELECT_BASE_IDX                                                             1
9302 #define regGDS_PERFCOUNTER0_SELECT1                                                                     0x3a84
9303 #define regGDS_PERFCOUNTER0_SELECT1_BASE_IDX                                                            1
9304 #define regGDS_PERFCOUNTER1_SELECT1                                                                     0x3a85
9305 #define regGDS_PERFCOUNTER1_SELECT1_BASE_IDX                                                            1
9306 #define regGDS_PERFCOUNTER2_SELECT1                                                                     0x3a86
9307 #define regGDS_PERFCOUNTER2_SELECT1_BASE_IDX                                                            1
9308 #define regGDS_PERFCOUNTER3_SELECT1                                                                     0x3a87
9309 #define regGDS_PERFCOUNTER3_SELECT1_BASE_IDX                                                            1
9310 #define regTA_PERFCOUNTER0_SELECT                                                                       0x3ac0
9311 #define regTA_PERFCOUNTER0_SELECT_BASE_IDX                                                              1
9312 #define regTA_PERFCOUNTER0_SELECT1                                                                      0x3ac1
9313 #define regTA_PERFCOUNTER0_SELECT1_BASE_IDX                                                             1
9314 #define regTA_PERFCOUNTER1_SELECT                                                                       0x3ac2
9315 #define regTA_PERFCOUNTER1_SELECT_BASE_IDX                                                              1
9316 #define regTD_PERFCOUNTER0_SELECT                                                                       0x3b00
9317 #define regTD_PERFCOUNTER0_SELECT_BASE_IDX                                                              1
9318 #define regTD_PERFCOUNTER0_SELECT1                                                                      0x3b01
9319 #define regTD_PERFCOUNTER0_SELECT1_BASE_IDX                                                             1
9320 #define regTD_PERFCOUNTER1_SELECT                                                                       0x3b02
9321 #define regTD_PERFCOUNTER1_SELECT_BASE_IDX                                                              1
9322 #define regTCP_PERFCOUNTER0_SELECT                                                                      0x3b40
9323 #define regTCP_PERFCOUNTER0_SELECT_BASE_IDX                                                             1
9324 #define regTCP_PERFCOUNTER0_SELECT1                                                                     0x3b41
9325 #define regTCP_PERFCOUNTER0_SELECT1_BASE_IDX                                                            1
9326 #define regTCP_PERFCOUNTER1_SELECT                                                                      0x3b42
9327 #define regTCP_PERFCOUNTER1_SELECT_BASE_IDX                                                             1
9328 #define regTCP_PERFCOUNTER1_SELECT1                                                                     0x3b43
9329 #define regTCP_PERFCOUNTER1_SELECT1_BASE_IDX                                                            1
9330 #define regTCP_PERFCOUNTER2_SELECT                                                                      0x3b44
9331 #define regTCP_PERFCOUNTER2_SELECT_BASE_IDX                                                             1
9332 #define regTCP_PERFCOUNTER3_SELECT                                                                      0x3b45
9333 #define regTCP_PERFCOUNTER3_SELECT_BASE_IDX                                                             1
9334 #define regGL2C_PERFCOUNTER0_SELECT                                                                     0x3b80
9335 #define regGL2C_PERFCOUNTER0_SELECT_BASE_IDX                                                            1
9336 #define regGL2C_PERFCOUNTER0_SELECT1                                                                    0x3b81
9337 #define regGL2C_PERFCOUNTER0_SELECT1_BASE_IDX                                                           1
9338 #define regGL2C_PERFCOUNTER1_SELECT                                                                     0x3b82
9339 #define regGL2C_PERFCOUNTER1_SELECT_BASE_IDX                                                            1
9340 #define regGL2C_PERFCOUNTER1_SELECT1                                                                    0x3b83
9341 #define regGL2C_PERFCOUNTER1_SELECT1_BASE_IDX                                                           1
9342 #define regGL2C_PERFCOUNTER2_SELECT                                                                     0x3b84
9343 #define regGL2C_PERFCOUNTER2_SELECT_BASE_IDX                                                            1
9344 #define regGL2C_PERFCOUNTER3_SELECT                                                                     0x3b85
9345 #define regGL2C_PERFCOUNTER3_SELECT_BASE_IDX                                                            1
9346 #define regGL2A_PERFCOUNTER0_SELECT                                                                     0x3b90
9347 #define regGL2A_PERFCOUNTER0_SELECT_BASE_IDX                                                            1
9348 #define regGL2A_PERFCOUNTER0_SELECT1                                                                    0x3b91
9349 #define regGL2A_PERFCOUNTER0_SELECT1_BASE_IDX                                                           1
9350 #define regGL2A_PERFCOUNTER1_SELECT                                                                     0x3b92
9351 #define regGL2A_PERFCOUNTER1_SELECT_BASE_IDX                                                            1
9352 #define regGL2A_PERFCOUNTER1_SELECT1                                                                    0x3b93
9353 #define regGL2A_PERFCOUNTER1_SELECT1_BASE_IDX                                                           1
9354 #define regGL2A_PERFCOUNTER2_SELECT                                                                     0x3b94
9355 #define regGL2A_PERFCOUNTER2_SELECT_BASE_IDX                                                            1
9356 #define regGL2A_PERFCOUNTER3_SELECT                                                                     0x3b95
9357 #define regGL2A_PERFCOUNTER3_SELECT_BASE_IDX                                                            1
9358 #define regGL1C_PERFCOUNTER0_SELECT                                                                     0x3ba0
9359 #define regGL1C_PERFCOUNTER0_SELECT_BASE_IDX                                                            1
9360 #define regGL1C_PERFCOUNTER0_SELECT1                                                                    0x3ba1
9361 #define regGL1C_PERFCOUNTER0_SELECT1_BASE_IDX                                                           1
9362 #define regGL1C_PERFCOUNTER1_SELECT                                                                     0x3ba2
9363 #define regGL1C_PERFCOUNTER1_SELECT_BASE_IDX                                                            1
9364 #define regGL1C_PERFCOUNTER2_SELECT                                                                     0x3ba3
9365 #define regGL1C_PERFCOUNTER2_SELECT_BASE_IDX                                                            1
9366 #define regGL1C_PERFCOUNTER3_SELECT                                                                     0x3ba4
9367 #define regGL1C_PERFCOUNTER3_SELECT_BASE_IDX                                                            1
9368 #define regCHC_PERFCOUNTER0_SELECT                                                                      0x3bc0
9369 #define regCHC_PERFCOUNTER0_SELECT_BASE_IDX                                                             1
9370 #define regCHC_PERFCOUNTER0_SELECT1                                                                     0x3bc1
9371 #define regCHC_PERFCOUNTER0_SELECT1_BASE_IDX                                                            1
9372 #define regCHC_PERFCOUNTER1_SELECT                                                                      0x3bc2
9373 #define regCHC_PERFCOUNTER1_SELECT_BASE_IDX                                                             1
9374 #define regCHC_PERFCOUNTER2_SELECT                                                                      0x3bc3
9375 #define regCHC_PERFCOUNTER2_SELECT_BASE_IDX                                                             1
9376 #define regCHC_PERFCOUNTER3_SELECT                                                                      0x3bc4
9377 #define regCHC_PERFCOUNTER3_SELECT_BASE_IDX                                                             1
9378 #define regCHCG_PERFCOUNTER0_SELECT                                                                     0x3bc6
9379 #define regCHCG_PERFCOUNTER0_SELECT_BASE_IDX                                                            1
9380 #define regCHCG_PERFCOUNTER0_SELECT1                                                                    0x3bc7
9381 #define regCHCG_PERFCOUNTER0_SELECT1_BASE_IDX                                                           1
9382 #define regCHCG_PERFCOUNTER1_SELECT                                                                     0x3bc8
9383 #define regCHCG_PERFCOUNTER1_SELECT_BASE_IDX                                                            1
9384 #define regCHCG_PERFCOUNTER2_SELECT                                                                     0x3bc9
9385 #define regCHCG_PERFCOUNTER2_SELECT_BASE_IDX                                                            1
9386 #define regCHCG_PERFCOUNTER3_SELECT                                                                     0x3bca
9387 #define regCHCG_PERFCOUNTER3_SELECT_BASE_IDX                                                            1
9388 #define regCB_PERFCOUNTER_FILTER                                                                        0x3c00
9389 #define regCB_PERFCOUNTER_FILTER_BASE_IDX                                                               1
9390 #define regCB_PERFCOUNTER0_SELECT                                                                       0x3c01
9391 #define regCB_PERFCOUNTER0_SELECT_BASE_IDX                                                              1
9392 #define regCB_PERFCOUNTER0_SELECT1                                                                      0x3c02
9393 #define regCB_PERFCOUNTER0_SELECT1_BASE_IDX                                                             1
9394 #define regCB_PERFCOUNTER1_SELECT                                                                       0x3c03
9395 #define regCB_PERFCOUNTER1_SELECT_BASE_IDX                                                              1
9396 #define regCB_PERFCOUNTER2_SELECT                                                                       0x3c04
9397 #define regCB_PERFCOUNTER2_SELECT_BASE_IDX                                                              1
9398 #define regCB_PERFCOUNTER3_SELECT                                                                       0x3c05
9399 #define regCB_PERFCOUNTER3_SELECT_BASE_IDX                                                              1
9400 #define regDB_PERFCOUNTER0_SELECT                                                                       0x3c40
9401 #define regDB_PERFCOUNTER0_SELECT_BASE_IDX                                                              1
9402 #define regDB_PERFCOUNTER0_SELECT1                                                                      0x3c41
9403 #define regDB_PERFCOUNTER0_SELECT1_BASE_IDX                                                             1
9404 #define regDB_PERFCOUNTER1_SELECT                                                                       0x3c42
9405 #define regDB_PERFCOUNTER1_SELECT_BASE_IDX                                                              1
9406 #define regDB_PERFCOUNTER1_SELECT1                                                                      0x3c43
9407 #define regDB_PERFCOUNTER1_SELECT1_BASE_IDX                                                             1
9408 #define regDB_PERFCOUNTER2_SELECT                                                                       0x3c44
9409 #define regDB_PERFCOUNTER2_SELECT_BASE_IDX                                                              1
9410 #define regDB_PERFCOUNTER3_SELECT                                                                       0x3c46
9411 #define regDB_PERFCOUNTER3_SELECT_BASE_IDX                                                              1
9412 #define regRLC_SPM_PERFMON_CNTL                                                                         0x3c80
9413 #define regRLC_SPM_PERFMON_CNTL_BASE_IDX                                                                1
9414 #define regRLC_SPM_PERFMON_RING_BASE_LO                                                                 0x3c81
9415 #define regRLC_SPM_PERFMON_RING_BASE_LO_BASE_IDX                                                        1
9416 #define regRLC_SPM_PERFMON_RING_BASE_HI                                                                 0x3c82
9417 #define regRLC_SPM_PERFMON_RING_BASE_HI_BASE_IDX                                                        1
9418 #define regRLC_SPM_PERFMON_RING_SIZE                                                                    0x3c83
9419 #define regRLC_SPM_PERFMON_RING_SIZE_BASE_IDX                                                           1
9420 #define regRLC_SPM_RING_WRPTR                                                                           0x3c84
9421 #define regRLC_SPM_RING_WRPTR_BASE_IDX                                                                  1
9422 #define regRLC_SPM_RING_RDPTR                                                                           0x3c85
9423 #define regRLC_SPM_RING_RDPTR_BASE_IDX                                                                  1
9424 #define regRLC_SPM_SEGMENT_THRESHOLD                                                                    0x3c86
9425 #define regRLC_SPM_SEGMENT_THRESHOLD_BASE_IDX                                                           1
9426 #define regRLC_SPM_PERFMON_SEGMENT_SIZE                                                                 0x3c87
9427 #define regRLC_SPM_PERFMON_SEGMENT_SIZE_BASE_IDX                                                        1
9428 #define regRLC_SPM_GLOBAL_MUXSEL_ADDR                                                                   0x3c88
9429 #define regRLC_SPM_GLOBAL_MUXSEL_ADDR_BASE_IDX                                                          1
9430 #define regRLC_SPM_GLOBAL_MUXSEL_DATA                                                                   0x3c89
9431 #define regRLC_SPM_GLOBAL_MUXSEL_DATA_BASE_IDX                                                          1
9432 #define regRLC_SPM_SE_MUXSEL_ADDR                                                                       0x3c8a
9433 #define regRLC_SPM_SE_MUXSEL_ADDR_BASE_IDX                                                              1
9434 #define regRLC_SPM_SE_MUXSEL_DATA                                                                       0x3c8b
9435 #define regRLC_SPM_SE_MUXSEL_DATA_BASE_IDX                                                              1
9436 #define regRLC_SPM_ACCUM_DATARAM_ADDR                                                                   0x3c92
9437 #define regRLC_SPM_ACCUM_DATARAM_ADDR_BASE_IDX                                                          1
9438 #define regRLC_SPM_ACCUM_DATARAM_DATA                                                                   0x3c93
9439 #define regRLC_SPM_ACCUM_DATARAM_DATA_BASE_IDX                                                          1
9440 #define regRLC_SPM_ACCUM_SWA_DATARAM_ADDR                                                               0x3c94
9441 #define regRLC_SPM_ACCUM_SWA_DATARAM_ADDR_BASE_IDX                                                      1
9442 #define regRLC_SPM_ACCUM_SWA_DATARAM_DATA                                                               0x3c95
9443 #define regRLC_SPM_ACCUM_SWA_DATARAM_DATA_BASE_IDX                                                      1
9444 #define regRLC_SPM_ACCUM_CTRLRAM_ADDR                                                                   0x3c96
9445 #define regRLC_SPM_ACCUM_CTRLRAM_ADDR_BASE_IDX                                                          1
9446 #define regRLC_SPM_ACCUM_CTRLRAM_DATA                                                                   0x3c97
9447 #define regRLC_SPM_ACCUM_CTRLRAM_DATA_BASE_IDX                                                          1
9448 #define regRLC_SPM_ACCUM_CTRLRAM_ADDR_OFFSET                                                            0x3c98
9449 #define regRLC_SPM_ACCUM_CTRLRAM_ADDR_OFFSET_BASE_IDX                                                   1
9450 #define regRLC_SPM_ACCUM_STATUS                                                                         0x3c99
9451 #define regRLC_SPM_ACCUM_STATUS_BASE_IDX                                                                1
9452 #define regRLC_SPM_ACCUM_CTRL                                                                           0x3c9a
9453 #define regRLC_SPM_ACCUM_CTRL_BASE_IDX                                                                  1
9454 #define regRLC_SPM_ACCUM_MODE                                                                           0x3c9b
9455 #define regRLC_SPM_ACCUM_MODE_BASE_IDX                                                                  1
9456 #define regRLC_SPM_ACCUM_THRESHOLD                                                                      0x3c9c
9457 #define regRLC_SPM_ACCUM_THRESHOLD_BASE_IDX                                                             1
9458 #define regRLC_SPM_ACCUM_SAMPLES_REQUESTED                                                              0x3c9d
9459 #define regRLC_SPM_ACCUM_SAMPLES_REQUESTED_BASE_IDX                                                     1
9460 #define regRLC_SPM_ACCUM_DATARAM_WRCOUNT                                                                0x3c9e
9461 #define regRLC_SPM_ACCUM_DATARAM_WRCOUNT_BASE_IDX                                                       1
9462 #define regRLC_SPM_ACCUM_DATARAM_32BITCNTRS_REGIONS                                                     0x3c9f
9463 #define regRLC_SPM_ACCUM_DATARAM_32BITCNTRS_REGIONS_BASE_IDX                                            1
9464 #define regRLC_SPM_PAUSE                                                                                0x3ca2
9465 #define regRLC_SPM_PAUSE_BASE_IDX                                                                       1
9466 #define regRLC_SPM_STATUS                                                                               0x3ca3
9467 #define regRLC_SPM_STATUS_BASE_IDX                                                                      1
9468 #define regRLC_SPM_GFXCLOCK_LOWCOUNT                                                                    0x3ca4
9469 #define regRLC_SPM_GFXCLOCK_LOWCOUNT_BASE_IDX                                                           1
9470 #define regRLC_SPM_GFXCLOCK_HIGHCOUNT                                                                   0x3ca5
9471 #define regRLC_SPM_GFXCLOCK_HIGHCOUNT_BASE_IDX                                                          1
9472 #define regRLC_SPM_MODE                                                                                 0x3cad
9473 #define regRLC_SPM_MODE_BASE_IDX                                                                        1
9474 #define regRLC_SPM_RSPM_REQ_DATA_LO                                                                     0x3cae
9475 #define regRLC_SPM_RSPM_REQ_DATA_LO_BASE_IDX                                                            1
9476 #define regRLC_SPM_RSPM_REQ_DATA_HI                                                                     0x3caf
9477 #define regRLC_SPM_RSPM_REQ_DATA_HI_BASE_IDX                                                            1
9478 #define regRLC_SPM_RSPM_REQ_OP                                                                          0x3cb0
9479 #define regRLC_SPM_RSPM_REQ_OP_BASE_IDX                                                                 1
9480 #define regRLC_SPM_RSPM_RET_DATA                                                                        0x3cb1
9481 #define regRLC_SPM_RSPM_RET_DATA_BASE_IDX                                                               1
9482 #define regRLC_SPM_RSPM_RET_OP                                                                          0x3cb2
9483 #define regRLC_SPM_RSPM_RET_OP_BASE_IDX                                                                 1
9484 #define regRLC_SPM_SE_RSPM_REQ_DATA_LO                                                                  0x3cb3
9485 #define regRLC_SPM_SE_RSPM_REQ_DATA_LO_BASE_IDX                                                         1
9486 #define regRLC_SPM_SE_RSPM_REQ_DATA_HI                                                                  0x3cb4
9487 #define regRLC_SPM_SE_RSPM_REQ_DATA_HI_BASE_IDX                                                         1
9488 #define regRLC_SPM_SE_RSPM_REQ_OP                                                                       0x3cb5
9489 #define regRLC_SPM_SE_RSPM_REQ_OP_BASE_IDX                                                              1
9490 #define regRLC_SPM_SE_RSPM_RET_DATA                                                                     0x3cb6
9491 #define regRLC_SPM_SE_RSPM_RET_DATA_BASE_IDX                                                            1
9492 #define regRLC_SPM_SE_RSPM_RET_OP                                                                       0x3cb7
9493 #define regRLC_SPM_SE_RSPM_RET_OP_BASE_IDX                                                              1
9494 #define regRLC_SPM_RSPM_CMD                                                                             0x3cb8
9495 #define regRLC_SPM_RSPM_CMD_BASE_IDX                                                                    1
9496 #define regRLC_SPM_RSPM_CMD_ACK                                                                         0x3cb9
9497 #define regRLC_SPM_RSPM_CMD_ACK_BASE_IDX                                                                1
9498 #define regRLC_SPM_SPARE                                                                                0x3cbf
9499 #define regRLC_SPM_SPARE_BASE_IDX                                                                       1
9500 #define regRLC_PERFMON_CNTL                                                                             0x3cc0
9501 #define regRLC_PERFMON_CNTL_BASE_IDX                                                                    1
9502 #define regRLC_PERFCOUNTER0_SELECT                                                                      0x3cc1
9503 #define regRLC_PERFCOUNTER0_SELECT_BASE_IDX                                                             1
9504 #define regRLC_PERFCOUNTER1_SELECT                                                                      0x3cc2
9505 #define regRLC_PERFCOUNTER1_SELECT_BASE_IDX                                                             1
9506 #define regRLC_GPU_IOV_PERF_CNT_CNTL                                                                    0x3cc3
9507 #define regRLC_GPU_IOV_PERF_CNT_CNTL_BASE_IDX                                                           1
9508 #define regRLC_GPU_IOV_PERF_CNT_WR_ADDR                                                                 0x3cc4
9509 #define regRLC_GPU_IOV_PERF_CNT_WR_ADDR_BASE_IDX                                                        1
9510 #define regRLC_GPU_IOV_PERF_CNT_WR_DATA                                                                 0x3cc5
9511 #define regRLC_GPU_IOV_PERF_CNT_WR_DATA_BASE_IDX                                                        1
9512 #define regRLC_GPU_IOV_PERF_CNT_RD_ADDR                                                                 0x3cc6
9513 #define regRLC_GPU_IOV_PERF_CNT_RD_ADDR_BASE_IDX                                                        1
9514 #define regRLC_GPU_IOV_PERF_CNT_RD_DATA                                                                 0x3cc7
9515 #define regRLC_GPU_IOV_PERF_CNT_RD_DATA_BASE_IDX                                                        1
9516 #define regRMI_PERFCOUNTER0_SELECT                                                                      0x3d00
9517 #define regRMI_PERFCOUNTER0_SELECT_BASE_IDX                                                             1
9518 #define regRMI_PERFCOUNTER0_SELECT1                                                                     0x3d01
9519 #define regRMI_PERFCOUNTER0_SELECT1_BASE_IDX                                                            1
9520 #define regRMI_PERFCOUNTER1_SELECT                                                                      0x3d02
9521 #define regRMI_PERFCOUNTER1_SELECT_BASE_IDX                                                             1
9522 #define regRMI_PERFCOUNTER2_SELECT                                                                      0x3d03
9523 #define regRMI_PERFCOUNTER2_SELECT_BASE_IDX                                                             1
9524 #define regRMI_PERFCOUNTER2_SELECT1                                                                     0x3d04
9525 #define regRMI_PERFCOUNTER2_SELECT1_BASE_IDX                                                            1
9526 #define regRMI_PERFCOUNTER3_SELECT                                                                      0x3d05
9527 #define regRMI_PERFCOUNTER3_SELECT_BASE_IDX                                                             1
9528 #define regRMI_PERF_COUNTER_CNTL                                                                        0x3d06
9529 #define regRMI_PERF_COUNTER_CNTL_BASE_IDX                                                               1
9530 #define regGCR_PERFCOUNTER0_SELECT                                                                      0x3d60
9531 #define regGCR_PERFCOUNTER0_SELECT_BASE_IDX                                                             1
9532 #define regGCR_PERFCOUNTER0_SELECT1                                                                     0x3d61
9533 #define regGCR_PERFCOUNTER0_SELECT1_BASE_IDX                                                            1
9534 #define regGCR_PERFCOUNTER1_SELECT                                                                      0x3d62
9535 #define regGCR_PERFCOUNTER1_SELECT_BASE_IDX                                                             1
9536 #define regPA_PH_PERFCOUNTER0_SELECT                                                                    0x3d80
9537 #define regPA_PH_PERFCOUNTER0_SELECT_BASE_IDX                                                           1
9538 #define regPA_PH_PERFCOUNTER0_SELECT1                                                                   0x3d81
9539 #define regPA_PH_PERFCOUNTER0_SELECT1_BASE_IDX                                                          1
9540 #define regPA_PH_PERFCOUNTER1_SELECT                                                                    0x3d82
9541 #define regPA_PH_PERFCOUNTER1_SELECT_BASE_IDX                                                           1
9542 #define regPA_PH_PERFCOUNTER2_SELECT                                                                    0x3d83
9543 #define regPA_PH_PERFCOUNTER2_SELECT_BASE_IDX                                                           1
9544 #define regPA_PH_PERFCOUNTER3_SELECT                                                                    0x3d84
9545 #define regPA_PH_PERFCOUNTER3_SELECT_BASE_IDX                                                           1
9546 #define regPA_PH_PERFCOUNTER4_SELECT                                                                    0x3d85
9547 #define regPA_PH_PERFCOUNTER4_SELECT_BASE_IDX                                                           1
9548 #define regPA_PH_PERFCOUNTER5_SELECT                                                                    0x3d86
9549 #define regPA_PH_PERFCOUNTER5_SELECT_BASE_IDX                                                           1
9550 #define regPA_PH_PERFCOUNTER6_SELECT                                                                    0x3d87
9551 #define regPA_PH_PERFCOUNTER6_SELECT_BASE_IDX                                                           1
9552 #define regPA_PH_PERFCOUNTER7_SELECT                                                                    0x3d88
9553 #define regPA_PH_PERFCOUNTER7_SELECT_BASE_IDX                                                           1
9554 #define regPA_PH_PERFCOUNTER1_SELECT1                                                                   0x3d90
9555 #define regPA_PH_PERFCOUNTER1_SELECT1_BASE_IDX                                                          1
9556 #define regPA_PH_PERFCOUNTER2_SELECT1                                                                   0x3d91
9557 #define regPA_PH_PERFCOUNTER2_SELECT1_BASE_IDX                                                          1
9558 #define regPA_PH_PERFCOUNTER3_SELECT1                                                                   0x3d92
9559 #define regPA_PH_PERFCOUNTER3_SELECT1_BASE_IDX                                                          1
9560 #define regUTCL1_PERFCOUNTER0_SELECT                                                                    0x3da0
9561 #define regUTCL1_PERFCOUNTER0_SELECT_BASE_IDX                                                           1
9562 #define regUTCL1_PERFCOUNTER1_SELECT                                                                    0x3da1
9563 #define regUTCL1_PERFCOUNTER1_SELECT_BASE_IDX                                                           1
9564 #define regUTCL1_PERFCOUNTER2_SELECT                                                                    0x3da2
9565 #define regUTCL1_PERFCOUNTER2_SELECT_BASE_IDX                                                           1
9566 #define regUTCL1_PERFCOUNTER3_SELECT                                                                    0x3da3
9567 #define regUTCL1_PERFCOUNTER3_SELECT_BASE_IDX                                                           1
9568 #define regGL1A_PERFCOUNTER0_SELECT                                                                     0x3dc0
9569 #define regGL1A_PERFCOUNTER0_SELECT_BASE_IDX                                                            1
9570 #define regGL1A_PERFCOUNTER0_SELECT1                                                                    0x3dc1
9571 #define regGL1A_PERFCOUNTER0_SELECT1_BASE_IDX                                                           1
9572 #define regGL1A_PERFCOUNTER1_SELECT                                                                     0x3dc2
9573 #define regGL1A_PERFCOUNTER1_SELECT_BASE_IDX                                                            1
9574 #define regGL1A_PERFCOUNTER2_SELECT                                                                     0x3dc3
9575 #define regGL1A_PERFCOUNTER2_SELECT_BASE_IDX                                                            1
9576 #define regGL1A_PERFCOUNTER3_SELECT                                                                     0x3dc4
9577 #define regGL1A_PERFCOUNTER3_SELECT_BASE_IDX                                                            1
9578 #define regGL1H_PERFCOUNTER0_SELECT                                                                     0x3dd0
9579 #define regGL1H_PERFCOUNTER0_SELECT_BASE_IDX                                                            1
9580 #define regGL1H_PERFCOUNTER0_SELECT1                                                                    0x3dd1
9581 #define regGL1H_PERFCOUNTER0_SELECT1_BASE_IDX                                                           1
9582 #define regGL1H_PERFCOUNTER1_SELECT                                                                     0x3dd2
9583 #define regGL1H_PERFCOUNTER1_SELECT_BASE_IDX                                                            1
9584 #define regGL1H_PERFCOUNTER2_SELECT                                                                     0x3dd3
9585 #define regGL1H_PERFCOUNTER2_SELECT_BASE_IDX                                                            1
9586 #define regGL1H_PERFCOUNTER3_SELECT                                                                     0x3dd4
9587 #define regGL1H_PERFCOUNTER3_SELECT_BASE_IDX                                                            1
9588 #define regCHA_PERFCOUNTER0_SELECT                                                                      0x3de0
9589 #define regCHA_PERFCOUNTER0_SELECT_BASE_IDX                                                             1
9590 #define regCHA_PERFCOUNTER0_SELECT1                                                                     0x3de1
9591 #define regCHA_PERFCOUNTER0_SELECT1_BASE_IDX                                                            1
9592 #define regCHA_PERFCOUNTER1_SELECT                                                                      0x3de2
9593 #define regCHA_PERFCOUNTER1_SELECT_BASE_IDX                                                             1
9594 #define regCHA_PERFCOUNTER2_SELECT                                                                      0x3de3
9595 #define regCHA_PERFCOUNTER2_SELECT_BASE_IDX                                                             1
9596 #define regCHA_PERFCOUNTER3_SELECT                                                                      0x3de4
9597 #define regCHA_PERFCOUNTER3_SELECT_BASE_IDX                                                             1
9598 #define regGUS_PERFCOUNTER2_SELECT                                                                      0x3e00
9599 #define regGUS_PERFCOUNTER2_SELECT_BASE_IDX                                                             1
9600 #define regGUS_PERFCOUNTER2_SELECT1                                                                     0x3e01
9601 #define regGUS_PERFCOUNTER2_SELECT1_BASE_IDX                                                            1
9602 #define regGUS_PERFCOUNTER2_MODE                                                                        0x3e02
9603 #define regGUS_PERFCOUNTER2_MODE_BASE_IDX                                                               1
9604 #define regGUS_PERFCOUNTER0_CFG                                                                         0x3e03
9605 #define regGUS_PERFCOUNTER0_CFG_BASE_IDX                                                                1
9606 #define regGUS_PERFCOUNTER1_CFG                                                                         0x3e04
9607 #define regGUS_PERFCOUNTER1_CFG_BASE_IDX                                                                1
9608 #define regGUS_PERFCOUNTER_RSLT_CNTL                                                                    0x3e05
9609 #define regGUS_PERFCOUNTER_RSLT_CNTL_BASE_IDX                                                           1
9610 
9611 
9612 // addressBlock: gc_grtavfs_grtavfs_dec
9613 // base address: 0x3ac00
9614 #define regGRTAVFS_RTAVFS_REG_ADDR                                                                      0x4b00
9615 #define regGRTAVFS_RTAVFS_REG_ADDR_BASE_IDX                                                             1
9616 #define regGRTAVFS_RTAVFS_WR_DATA                                                                       0x4b01
9617 #define regGRTAVFS_RTAVFS_WR_DATA_BASE_IDX                                                              1
9618 #define regGRTAVFS_GENERAL_0                                                                            0x4b02
9619 #define regGRTAVFS_GENERAL_0_BASE_IDX                                                                   1
9620 #define regGRTAVFS_RTAVFS_RD_DATA                                                                       0x4b03
9621 #define regGRTAVFS_RTAVFS_RD_DATA_BASE_IDX                                                              1
9622 #define regGRTAVFS_RTAVFS_REG_CTRL                                                                      0x4b04
9623 #define regGRTAVFS_RTAVFS_REG_CTRL_BASE_IDX                                                             1
9624 #define regGRTAVFS_RTAVFS_REG_STATUS                                                                    0x4b05
9625 #define regGRTAVFS_RTAVFS_REG_STATUS_BASE_IDX                                                           1
9626 #define regGRTAVFS_TARG_FREQ                                                                            0x4b06
9627 #define regGRTAVFS_TARG_FREQ_BASE_IDX                                                                   1
9628 #define regGRTAVFS_TARG_VOLT                                                                            0x4b07
9629 #define regGRTAVFS_TARG_VOLT_BASE_IDX                                                                   1
9630 #define regGRTAVFS_SOFT_RESET                                                                           0x4b0c
9631 #define regGRTAVFS_SOFT_RESET_BASE_IDX                                                                  1
9632 #define regGRTAVFS_PSM_CNTL                                                                             0x4b0d
9633 #define regGRTAVFS_PSM_CNTL_BASE_IDX                                                                    1
9634 #define regGRTAVFS_CLK_CNTL                                                                             0x4b0e
9635 #define regGRTAVFS_CLK_CNTL_BASE_IDX                                                                    1
9636 
9637 
9638 // addressBlock: gc_grtavfs_se_grtavfs_dec
9639 // base address: 0x3ad00
9640 #define regGRTAVFS_SE_RTAVFS_REG_ADDR                                                                   0x4b40
9641 #define regGRTAVFS_SE_RTAVFS_REG_ADDR_BASE_IDX                                                          1
9642 #define regGRTAVFS_SE_RTAVFS_WR_DATA                                                                    0x4b41
9643 #define regGRTAVFS_SE_RTAVFS_WR_DATA_BASE_IDX                                                           1
9644 #define regGRTAVFS_SE_GENERAL_0                                                                         0x4b42
9645 #define regGRTAVFS_SE_GENERAL_0_BASE_IDX                                                                1
9646 #define regGRTAVFS_SE_RTAVFS_RD_DATA                                                                    0x4b43
9647 #define regGRTAVFS_SE_RTAVFS_RD_DATA_BASE_IDX                                                           1
9648 #define regGRTAVFS_SE_RTAVFS_REG_CTRL                                                                   0x4b44
9649 #define regGRTAVFS_SE_RTAVFS_REG_CTRL_BASE_IDX                                                          1
9650 #define regGRTAVFS_SE_RTAVFS_REG_STATUS                                                                 0x4b45
9651 #define regGRTAVFS_SE_RTAVFS_REG_STATUS_BASE_IDX                                                        1
9652 #define regGRTAVFS_SE_TARG_FREQ                                                                         0x4b46
9653 #define regGRTAVFS_SE_TARG_FREQ_BASE_IDX                                                                1
9654 #define regGRTAVFS_SE_TARG_VOLT                                                                         0x4b47
9655 #define regGRTAVFS_SE_TARG_VOLT_BASE_IDX                                                                1
9656 #define regGRTAVFS_SE_SOFT_RESET                                                                        0x4b4c
9657 #define regGRTAVFS_SE_SOFT_RESET_BASE_IDX                                                               1
9658 #define regGRTAVFS_SE_PSM_CNTL                                                                          0x4b4d
9659 #define regGRTAVFS_SE_PSM_CNTL_BASE_IDX                                                                 1
9660 #define regGRTAVFS_SE_CLK_CNTL                                                                          0x4b4e
9661 #define regGRTAVFS_SE_CLK_CNTL_BASE_IDX                                                                 1
9662 
9663 
9664 // addressBlock: gc_grtavfsdec
9665 // base address: 0x3ac00
9666 #define regRTAVFS_RTAVFS_REG_ADDR                                                                       0x4b00
9667 #define regRTAVFS_RTAVFS_REG_ADDR_BASE_IDX                                                              1
9668 #define regRTAVFS_RTAVFS_WR_DATA                                                                        0x4b01
9669 #define regRTAVFS_RTAVFS_WR_DATA_BASE_IDX                                                               1
9670 
9671 
9672 // addressBlock: gc_cphypdec
9673 // base address: 0x3e000
9674 #define regCP_HYP_PFP_UCODE_ADDR                                                                        0x5814
9675 #define regCP_HYP_PFP_UCODE_ADDR_BASE_IDX                                                               1
9676 #define regCP_PFP_UCODE_ADDR                                                                            0x5814
9677 #define regCP_PFP_UCODE_ADDR_BASE_IDX                                                                   1
9678 #define regCP_HYP_PFP_UCODE_DATA                                                                        0x5815
9679 #define regCP_HYP_PFP_UCODE_DATA_BASE_IDX                                                               1
9680 #define regCP_PFP_UCODE_DATA                                                                            0x5815
9681 #define regCP_PFP_UCODE_DATA_BASE_IDX                                                                   1
9682 #define regCP_HYP_ME_UCODE_ADDR                                                                         0x5816
9683 #define regCP_HYP_ME_UCODE_ADDR_BASE_IDX                                                                1
9684 #define regCP_ME_RAM_RADDR                                                                              0x5816
9685 #define regCP_ME_RAM_RADDR_BASE_IDX                                                                     1
9686 #define regCP_ME_RAM_WADDR                                                                              0x5816
9687 #define regCP_ME_RAM_WADDR_BASE_IDX                                                                     1
9688 #define regCP_HYP_ME_UCODE_DATA                                                                         0x5817
9689 #define regCP_HYP_ME_UCODE_DATA_BASE_IDX                                                                1
9690 #define regCP_ME_RAM_DATA                                                                               0x5817
9691 #define regCP_ME_RAM_DATA_BASE_IDX                                                                      1
9692 #define regCP_HYP_MEC1_UCODE_ADDR                                                                       0x581a
9693 #define regCP_HYP_MEC1_UCODE_ADDR_BASE_IDX                                                              1
9694 #define regCP_MEC_ME1_UCODE_ADDR                                                                        0x581a
9695 #define regCP_MEC_ME1_UCODE_ADDR_BASE_IDX                                                               1
9696 #define regCP_HYP_MEC1_UCODE_DATA                                                                       0x581b
9697 #define regCP_HYP_MEC1_UCODE_DATA_BASE_IDX                                                              1
9698 #define regCP_MEC_ME1_UCODE_DATA                                                                        0x581b
9699 #define regCP_MEC_ME1_UCODE_DATA_BASE_IDX                                                               1
9700 #define regCP_HYP_MEC2_UCODE_ADDR                                                                       0x581c
9701 #define regCP_HYP_MEC2_UCODE_ADDR_BASE_IDX                                                              1
9702 #define regCP_MEC_ME2_UCODE_ADDR                                                                        0x581c
9703 #define regCP_MEC_ME2_UCODE_ADDR_BASE_IDX                                                               1
9704 #define regCP_HYP_MEC2_UCODE_DATA                                                                       0x581d
9705 #define regCP_HYP_MEC2_UCODE_DATA_BASE_IDX                                                              1
9706 #define regCP_MEC_ME2_UCODE_DATA                                                                        0x581d
9707 #define regCP_MEC_ME2_UCODE_DATA_BASE_IDX                                                               1
9708 #define regCP_PFP_IC_BASE_LO                                                                            0x5840
9709 #define regCP_PFP_IC_BASE_LO_BASE_IDX                                                                   1
9710 #define regCP_PFP_IC_BASE_HI                                                                            0x5841
9711 #define regCP_PFP_IC_BASE_HI_BASE_IDX                                                                   1
9712 #define regCP_PFP_IC_BASE_CNTL                                                                          0x5842
9713 #define regCP_PFP_IC_BASE_CNTL_BASE_IDX                                                                 1
9714 #define regCP_PFP_IC_OP_CNTL                                                                            0x5843
9715 #define regCP_PFP_IC_OP_CNTL_BASE_IDX                                                                   1
9716 #define regCP_ME_IC_BASE_LO                                                                             0x5844
9717 #define regCP_ME_IC_BASE_LO_BASE_IDX                                                                    1
9718 #define regCP_ME_IC_BASE_HI                                                                             0x5845
9719 #define regCP_ME_IC_BASE_HI_BASE_IDX                                                                    1
9720 #define regCP_ME_IC_BASE_CNTL                                                                           0x5846
9721 #define regCP_ME_IC_BASE_CNTL_BASE_IDX                                                                  1
9722 #define regCP_ME_IC_OP_CNTL                                                                             0x5847
9723 #define regCP_ME_IC_OP_CNTL_BASE_IDX                                                                    1
9724 #define regCP_CPC_IC_BASE_LO                                                                            0x584c
9725 #define regCP_CPC_IC_BASE_LO_BASE_IDX                                                                   1
9726 #define regCP_CPC_IC_BASE_HI                                                                            0x584d
9727 #define regCP_CPC_IC_BASE_HI_BASE_IDX                                                                   1
9728 #define regCP_CPC_IC_BASE_CNTL                                                                          0x584e
9729 #define regCP_CPC_IC_BASE_CNTL_BASE_IDX                                                                 1
9730 #define regCP_MES_IC_BASE_LO                                                                            0x5850
9731 #define regCP_MES_IC_BASE_LO_BASE_IDX                                                                   1
9732 #define regCP_MES_MIBASE_LO                                                                             0x5850
9733 #define regCP_MES_MIBASE_LO_BASE_IDX                                                                    1
9734 #define regCP_MES_IC_BASE_HI                                                                            0x5851
9735 #define regCP_MES_IC_BASE_HI_BASE_IDX                                                                   1
9736 #define regCP_MES_MIBASE_HI                                                                             0x5851
9737 #define regCP_MES_MIBASE_HI_BASE_IDX                                                                    1
9738 #define regCP_MES_IC_BASE_CNTL                                                                          0x5852
9739 #define regCP_MES_IC_BASE_CNTL_BASE_IDX                                                                 1
9740 #define regCP_MES_DC_BASE_LO                                                                            0x5854
9741 #define regCP_MES_DC_BASE_LO_BASE_IDX                                                                   1
9742 #define regCP_MES_MDBASE_LO                                                                             0x5854
9743 #define regCP_MES_MDBASE_LO_BASE_IDX                                                                    1
9744 #define regCP_MES_DC_BASE_HI                                                                            0x5855
9745 #define regCP_MES_DC_BASE_HI_BASE_IDX                                                                   1
9746 #define regCP_MES_MDBASE_HI                                                                             0x5855
9747 #define regCP_MES_MDBASE_HI_BASE_IDX                                                                    1
9748 #define regCP_MES_MIBOUND_LO                                                                            0x585b
9749 #define regCP_MES_MIBOUND_LO_BASE_IDX                                                                   1
9750 #define regCP_MES_MIBOUND_HI                                                                            0x585c
9751 #define regCP_MES_MIBOUND_HI_BASE_IDX                                                                   1
9752 #define regCP_MES_MDBOUND_LO                                                                            0x585d
9753 #define regCP_MES_MDBOUND_LO_BASE_IDX                                                                   1
9754 #define regCP_MES_MDBOUND_HI                                                                            0x585e
9755 #define regCP_MES_MDBOUND_HI_BASE_IDX                                                                   1
9756 #define regCP_GFX_RS64_DC_BASE0_LO                                                                      0x5863
9757 #define regCP_GFX_RS64_DC_BASE0_LO_BASE_IDX                                                             1
9758 #define regCP_GFX_RS64_DC_BASE1_LO                                                                      0x5864
9759 #define regCP_GFX_RS64_DC_BASE1_LO_BASE_IDX                                                             1
9760 #define regCP_GFX_RS64_DC_BASE0_HI                                                                      0x5865
9761 #define regCP_GFX_RS64_DC_BASE0_HI_BASE_IDX                                                             1
9762 #define regCP_GFX_RS64_DC_BASE1_HI                                                                      0x5866
9763 #define regCP_GFX_RS64_DC_BASE1_HI_BASE_IDX                                                             1
9764 #define regCP_GFX_RS64_MIBOUND_LO                                                                       0x586c
9765 #define regCP_GFX_RS64_MIBOUND_LO_BASE_IDX                                                              1
9766 #define regCP_GFX_RS64_MIBOUND_HI                                                                       0x586d
9767 #define regCP_GFX_RS64_MIBOUND_HI_BASE_IDX                                                              1
9768 #define regCP_MEC_DC_BASE_LO                                                                            0x5870
9769 #define regCP_MEC_DC_BASE_LO_BASE_IDX                                                                   1
9770 #define regCP_MEC_MDBASE_LO                                                                             0x5870
9771 #define regCP_MEC_MDBASE_LO_BASE_IDX                                                                    1
9772 #define regCP_MEC_DC_BASE_HI                                                                            0x5871
9773 #define regCP_MEC_DC_BASE_HI_BASE_IDX                                                                   1
9774 #define regCP_MEC_MDBASE_HI                                                                             0x5871
9775 #define regCP_MEC_MDBASE_HI_BASE_IDX                                                                    1
9776 #define regCP_MEC_MIBOUND_LO                                                                            0x5872
9777 #define regCP_MEC_MIBOUND_LO_BASE_IDX                                                                   1
9778 #define regCP_MEC_MIBOUND_HI                                                                            0x5873
9779 #define regCP_MEC_MIBOUND_HI_BASE_IDX                                                                   1
9780 #define regCP_MEC_MDBOUND_LO                                                                            0x5874
9781 #define regCP_MEC_MDBOUND_LO_BASE_IDX                                                                   1
9782 #define regCP_MEC_MDBOUND_HI                                                                            0x5875
9783 #define regCP_MEC_MDBOUND_HI_BASE_IDX                                                                   1
9784 
9785 
9786 // addressBlock: gc_rlcdec
9787 // base address: 0x3b000
9788 #define regRLC_CNTL                                                                                     0x4c00
9789 #define regRLC_CNTL_BASE_IDX                                                                            1
9790 #define regRLC_F32_UCODE_VERSION                                                                        0x4c03
9791 #define regRLC_F32_UCODE_VERSION_BASE_IDX                                                               1
9792 #define regRLC_STAT                                                                                     0x4c04
9793 #define regRLC_STAT_BASE_IDX                                                                            1
9794 #define regRLC_REFCLOCK_TIMESTAMP_LSB                                                                   0x4c0c
9795 #define regRLC_REFCLOCK_TIMESTAMP_LSB_BASE_IDX                                                          1
9796 #define regRLC_REFCLOCK_TIMESTAMP_MSB                                                                   0x4c0d
9797 #define regRLC_REFCLOCK_TIMESTAMP_MSB_BASE_IDX                                                          1
9798 #define regRLC_GPM_TIMER_INT_0                                                                          0x4c0e
9799 #define regRLC_GPM_TIMER_INT_0_BASE_IDX                                                                 1
9800 #define regRLC_GPM_TIMER_INT_1                                                                          0x4c0f
9801 #define regRLC_GPM_TIMER_INT_1_BASE_IDX                                                                 1
9802 #define regRLC_GPM_TIMER_INT_2                                                                          0x4c10
9803 #define regRLC_GPM_TIMER_INT_2_BASE_IDX                                                                 1
9804 #define regRLC_GPM_TIMER_INT_3                                                                          0x4c11
9805 #define regRLC_GPM_TIMER_INT_3_BASE_IDX                                                                 1
9806 #define regRLC_GPM_TIMER_INT_4                                                                          0x4c12
9807 #define regRLC_GPM_TIMER_INT_4_BASE_IDX                                                                 1
9808 #define regRLC_GPM_TIMER_CTRL                                                                           0x4c13
9809 #define regRLC_GPM_TIMER_CTRL_BASE_IDX                                                                  1
9810 #define regRLC_GPM_TIMER_STAT                                                                           0x4c14
9811 #define regRLC_GPM_TIMER_STAT_BASE_IDX                                                                  1
9812 #define regRLC_GPM_LEGACY_INT_STAT                                                                      0x4c16
9813 #define regRLC_GPM_LEGACY_INT_STAT_BASE_IDX                                                             1
9814 #define regRLC_GPM_LEGACY_INT_CLEAR                                                                     0x4c17
9815 #define regRLC_GPM_LEGACY_INT_CLEAR_BASE_IDX                                                            1
9816 #define regRLC_INT_STAT                                                                                 0x4c18
9817 #define regRLC_INT_STAT_BASE_IDX                                                                        1
9818 #define regRLC_MGCG_CTRL                                                                                0x4c1a
9819 #define regRLC_MGCG_CTRL_BASE_IDX                                                                       1
9820 #define regRLC_JUMP_TABLE_RESTORE                                                                       0x4c1e
9821 #define regRLC_JUMP_TABLE_RESTORE_BASE_IDX                                                              1
9822 #define regRLC_PG_DELAY_2                                                                               0x4c1f
9823 #define regRLC_PG_DELAY_2_BASE_IDX                                                                      1
9824 #define regRLC_GPU_CLOCK_COUNT_LSB                                                                      0x4c24
9825 #define regRLC_GPU_CLOCK_COUNT_LSB_BASE_IDX                                                             1
9826 #define regRLC_GPU_CLOCK_COUNT_MSB                                                                      0x4c25
9827 #define regRLC_GPU_CLOCK_COUNT_MSB_BASE_IDX                                                             1
9828 #define regRLC_CAPTURE_GPU_CLOCK_COUNT                                                                  0x4c26
9829 #define regRLC_CAPTURE_GPU_CLOCK_COUNT_BASE_IDX                                                         1
9830 #define regRLC_UCODE_CNTL                                                                               0x4c27
9831 #define regRLC_UCODE_CNTL_BASE_IDX                                                                      1
9832 #define regRLC_GPM_THREAD_RESET                                                                         0x4c28
9833 #define regRLC_GPM_THREAD_RESET_BASE_IDX                                                                1
9834 #define regRLC_GPM_CP_DMA_COMPLETE_T0                                                                   0x4c29
9835 #define regRLC_GPM_CP_DMA_COMPLETE_T0_BASE_IDX                                                          1
9836 #define regRLC_GPM_CP_DMA_COMPLETE_T1                                                                   0x4c2a
9837 #define regRLC_GPM_CP_DMA_COMPLETE_T1_BASE_IDX                                                          1
9838 #define regRLC_GPM_THREAD_INVALIDATE_CACHE                                                              0x4c2b
9839 #define regRLC_GPM_THREAD_INVALIDATE_CACHE_BASE_IDX                                                     1
9840 #define regRLC_CLK_COUNT_GFXCLK_LSB                                                                     0x4c30
9841 #define regRLC_CLK_COUNT_GFXCLK_LSB_BASE_IDX                                                            1
9842 #define regRLC_CLK_COUNT_GFXCLK_MSB                                                                     0x4c31
9843 #define regRLC_CLK_COUNT_GFXCLK_MSB_BASE_IDX                                                            1
9844 #define regRLC_CLK_COUNT_REFCLK_LSB                                                                     0x4c32
9845 #define regRLC_CLK_COUNT_REFCLK_LSB_BASE_IDX                                                            1
9846 #define regRLC_CLK_COUNT_REFCLK_MSB                                                                     0x4c33
9847 #define regRLC_CLK_COUNT_REFCLK_MSB_BASE_IDX                                                            1
9848 #define regRLC_CLK_COUNT_CTRL                                                                           0x4c34
9849 #define regRLC_CLK_COUNT_CTRL_BASE_IDX                                                                  1
9850 #define regRLC_CLK_COUNT_STAT                                                                           0x4c35
9851 #define regRLC_CLK_COUNT_STAT_BASE_IDX                                                                  1
9852 #define regRLC_RLCG_DOORBELL_CNTL                                                                       0x4c36
9853 #define regRLC_RLCG_DOORBELL_CNTL_BASE_IDX                                                              1
9854 #define regRLC_RLCG_DOORBELL_STAT                                                                       0x4c37
9855 #define regRLC_RLCG_DOORBELL_STAT_BASE_IDX                                                              1
9856 #define regRLC_RLCG_DOORBELL_0_DATA_LO                                                                  0x4c38
9857 #define regRLC_RLCG_DOORBELL_0_DATA_LO_BASE_IDX                                                         1
9858 #define regRLC_RLCG_DOORBELL_0_DATA_HI                                                                  0x4c39
9859 #define regRLC_RLCG_DOORBELL_0_DATA_HI_BASE_IDX                                                         1
9860 #define regRLC_RLCG_DOORBELL_1_DATA_LO                                                                  0x4c3a
9861 #define regRLC_RLCG_DOORBELL_1_DATA_LO_BASE_IDX                                                         1
9862 #define regRLC_RLCG_DOORBELL_1_DATA_HI                                                                  0x4c3b
9863 #define regRLC_RLCG_DOORBELL_1_DATA_HI_BASE_IDX                                                         1
9864 #define regRLC_RLCG_DOORBELL_2_DATA_LO                                                                  0x4c3c
9865 #define regRLC_RLCG_DOORBELL_2_DATA_LO_BASE_IDX                                                         1
9866 #define regRLC_RLCG_DOORBELL_2_DATA_HI                                                                  0x4c3d
9867 #define regRLC_RLCG_DOORBELL_2_DATA_HI_BASE_IDX                                                         1
9868 #define regRLC_RLCG_DOORBELL_3_DATA_LO                                                                  0x4c3e
9869 #define regRLC_RLCG_DOORBELL_3_DATA_LO_BASE_IDX                                                         1
9870 #define regRLC_RLCG_DOORBELL_3_DATA_HI                                                                  0x4c3f
9871 #define regRLC_RLCG_DOORBELL_3_DATA_HI_BASE_IDX                                                         1
9872 #define regRLC_GPU_CLOCK_32_RES_SEL                                                                     0x4c41
9873 #define regRLC_GPU_CLOCK_32_RES_SEL_BASE_IDX                                                            1
9874 #define regRLC_GPU_CLOCK_32                                                                             0x4c42
9875 #define regRLC_GPU_CLOCK_32_BASE_IDX                                                                    1
9876 #define regRLC_PG_CNTL                                                                                  0x4c43
9877 #define regRLC_PG_CNTL_BASE_IDX                                                                         1
9878 #define regRLC_GPM_THREAD_PRIORITY                                                                      0x4c44
9879 #define regRLC_GPM_THREAD_PRIORITY_BASE_IDX                                                             1
9880 #define regRLC_GPM_THREAD_ENABLE                                                                        0x4c45
9881 #define regRLC_GPM_THREAD_ENABLE_BASE_IDX                                                               1
9882 #define regRLC_RLCG_DOORBELL_RANGE                                                                      0x4c47
9883 #define regRLC_RLCG_DOORBELL_RANGE_BASE_IDX                                                             1
9884 #define regRLC_CGTT_MGCG_OVERRIDE                                                                       0x4c48
9885 #define regRLC_CGTT_MGCG_OVERRIDE_BASE_IDX                                                              1
9886 #define regRLC_CGCG_CGLS_CTRL                                                                           0x4c49
9887 #define regRLC_CGCG_CGLS_CTRL_BASE_IDX                                                                  1
9888 #define regRLC_CGCG_RAMP_CTRL                                                                           0x4c4a
9889 #define regRLC_CGCG_RAMP_CTRL_BASE_IDX                                                                  1
9890 #define regRLC_DYN_PG_STATUS                                                                            0x4c4b
9891 #define regRLC_DYN_PG_STATUS_BASE_IDX                                                                   1
9892 #define regRLC_DYN_PG_REQUEST                                                                           0x4c4c
9893 #define regRLC_DYN_PG_REQUEST_BASE_IDX                                                                  1
9894 #define regRLC_PG_DELAY                                                                                 0x4c4d
9895 #define regRLC_PG_DELAY_BASE_IDX                                                                        1
9896 #define regRLC_WGP_STATUS                                                                               0x4c4e
9897 #define regRLC_WGP_STATUS_BASE_IDX                                                                      1
9898 #define regRLC_PG_ALWAYS_ON_WGP_MASK                                                                    0x4c53
9899 #define regRLC_PG_ALWAYS_ON_WGP_MASK_BASE_IDX                                                           1
9900 #define regRLC_MAX_PG_WGP                                                                               0x4c54
9901 #define regRLC_MAX_PG_WGP_BASE_IDX                                                                      1
9902 #define regRLC_AUTO_PG_CTRL                                                                             0x4c55
9903 #define regRLC_AUTO_PG_CTRL_BASE_IDX                                                                    1
9904 #define regRLC_SERDES_RD_INDEX                                                                          0x4c59
9905 #define regRLC_SERDES_RD_INDEX_BASE_IDX                                                                 1
9906 #define regRLC_SERDES_RD_DATA_0                                                                         0x4c5a
9907 #define regRLC_SERDES_RD_DATA_0_BASE_IDX                                                                1
9908 #define regRLC_SERDES_RD_DATA_1                                                                         0x4c5b
9909 #define regRLC_SERDES_RD_DATA_1_BASE_IDX                                                                1
9910 #define regRLC_SERDES_RD_DATA_2                                                                         0x4c5c
9911 #define regRLC_SERDES_RD_DATA_2_BASE_IDX                                                                1
9912 #define regRLC_SERDES_RD_DATA_3                                                                         0x4c5d
9913 #define regRLC_SERDES_RD_DATA_3_BASE_IDX                                                                1
9914 #define regRLC_SERDES_MASK                                                                              0x4c5e
9915 #define regRLC_SERDES_MASK_BASE_IDX                                                                     1
9916 #define regRLC_SERDES_CTRL                                                                              0x4c5f
9917 #define regRLC_SERDES_CTRL_BASE_IDX                                                                     1
9918 #define regRLC_SERDES_DATA                                                                              0x4c60
9919 #define regRLC_SERDES_DATA_BASE_IDX                                                                     1
9920 #define regRLC_SERDES_BUSY                                                                              0x4c61
9921 #define regRLC_SERDES_BUSY_BASE_IDX                                                                     1
9922 #define regRLC_GPM_GENERAL_0                                                                            0x4c63
9923 #define regRLC_GPM_GENERAL_0_BASE_IDX                                                                   1
9924 #define regRLC_GPM_GENERAL_1                                                                            0x4c64
9925 #define regRLC_GPM_GENERAL_1_BASE_IDX                                                                   1
9926 #define regRLC_GPM_GENERAL_2                                                                            0x4c65
9927 #define regRLC_GPM_GENERAL_2_BASE_IDX                                                                   1
9928 #define regRLC_GPM_GENERAL_3                                                                            0x4c66
9929 #define regRLC_GPM_GENERAL_3_BASE_IDX                                                                   1
9930 #define regRLC_GPM_GENERAL_4                                                                            0x4c67
9931 #define regRLC_GPM_GENERAL_4_BASE_IDX                                                                   1
9932 #define regRLC_GPM_GENERAL_5                                                                            0x4c68
9933 #define regRLC_GPM_GENERAL_5_BASE_IDX                                                                   1
9934 #define regRLC_GPM_GENERAL_6                                                                            0x4c69
9935 #define regRLC_GPM_GENERAL_6_BASE_IDX                                                                   1
9936 #define regRLC_GPM_GENERAL_7                                                                            0x4c6a
9937 #define regRLC_GPM_GENERAL_7_BASE_IDX                                                                   1
9938 #define regRLC_STATIC_PG_STATUS                                                                         0x4c6e
9939 #define regRLC_STATIC_PG_STATUS_BASE_IDX                                                                1
9940 #define regRLC_GPM_GENERAL_16                                                                           0x4c76
9941 #define regRLC_GPM_GENERAL_16_BASE_IDX                                                                  1
9942 #define regRLC_PG_DELAY_3                                                                               0x4c78
9943 #define regRLC_PG_DELAY_3_BASE_IDX                                                                      1
9944 #define regRLC_GPR_REG1                                                                                 0x4c79
9945 #define regRLC_GPR_REG1_BASE_IDX                                                                        1
9946 #define regRLC_GPR_REG2                                                                                 0x4c7a
9947 #define regRLC_GPR_REG2_BASE_IDX                                                                        1
9948 #define regRLC_GPM_INT_DISABLE_TH0                                                                      0x4c7c
9949 #define regRLC_GPM_INT_DISABLE_TH0_BASE_IDX                                                             1
9950 #define regRLC_GPM_LEGACY_INT_DISABLE                                                                   0x4c7d
9951 #define regRLC_GPM_LEGACY_INT_DISABLE_BASE_IDX                                                          1
9952 #define regRLC_GPM_INT_FORCE_TH0                                                                        0x4c7e
9953 #define regRLC_GPM_INT_FORCE_TH0_BASE_IDX                                                               1
9954 #define regRLC_SRM_CNTL                                                                                 0x4c80
9955 #define regRLC_SRM_CNTL_BASE_IDX                                                                        1
9956 #define regRLC_SRM_GPM_COMMAND_STATUS                                                                   0x4c88
9957 #define regRLC_SRM_GPM_COMMAND_STATUS_BASE_IDX                                                          1
9958 #define regRLC_SRM_INDEX_CNTL_ADDR_0                                                                    0x4c8b
9959 #define regRLC_SRM_INDEX_CNTL_ADDR_0_BASE_IDX                                                           1
9960 #define regRLC_SRM_INDEX_CNTL_ADDR_1                                                                    0x4c8c
9961 #define regRLC_SRM_INDEX_CNTL_ADDR_1_BASE_IDX                                                           1
9962 #define regRLC_SRM_INDEX_CNTL_ADDR_2                                                                    0x4c8d
9963 #define regRLC_SRM_INDEX_CNTL_ADDR_2_BASE_IDX                                                           1
9964 #define regRLC_SRM_INDEX_CNTL_ADDR_3                                                                    0x4c8e
9965 #define regRLC_SRM_INDEX_CNTL_ADDR_3_BASE_IDX                                                           1
9966 #define regRLC_SRM_INDEX_CNTL_ADDR_4                                                                    0x4c8f
9967 #define regRLC_SRM_INDEX_CNTL_ADDR_4_BASE_IDX                                                           1
9968 #define regRLC_SRM_INDEX_CNTL_ADDR_5                                                                    0x4c90
9969 #define regRLC_SRM_INDEX_CNTL_ADDR_5_BASE_IDX                                                           1
9970 #define regRLC_SRM_INDEX_CNTL_ADDR_6                                                                    0x4c91
9971 #define regRLC_SRM_INDEX_CNTL_ADDR_6_BASE_IDX                                                           1
9972 #define regRLC_SRM_INDEX_CNTL_ADDR_7                                                                    0x4c92
9973 #define regRLC_SRM_INDEX_CNTL_ADDR_7_BASE_IDX                                                           1
9974 #define regRLC_SRM_INDEX_CNTL_DATA_0                                                                    0x4c93
9975 #define regRLC_SRM_INDEX_CNTL_DATA_0_BASE_IDX                                                           1
9976 #define regRLC_SRM_INDEX_CNTL_DATA_1                                                                    0x4c94
9977 #define regRLC_SRM_INDEX_CNTL_DATA_1_BASE_IDX                                                           1
9978 #define regRLC_SRM_INDEX_CNTL_DATA_2                                                                    0x4c95
9979 #define regRLC_SRM_INDEX_CNTL_DATA_2_BASE_IDX                                                           1
9980 #define regRLC_SRM_INDEX_CNTL_DATA_3                                                                    0x4c96
9981 #define regRLC_SRM_INDEX_CNTL_DATA_3_BASE_IDX                                                           1
9982 #define regRLC_SRM_INDEX_CNTL_DATA_4                                                                    0x4c97
9983 #define regRLC_SRM_INDEX_CNTL_DATA_4_BASE_IDX                                                           1
9984 #define regRLC_SRM_INDEX_CNTL_DATA_5                                                                    0x4c98
9985 #define regRLC_SRM_INDEX_CNTL_DATA_5_BASE_IDX                                                           1
9986 #define regRLC_SRM_INDEX_CNTL_DATA_6                                                                    0x4c99
9987 #define regRLC_SRM_INDEX_CNTL_DATA_6_BASE_IDX                                                           1
9988 #define regRLC_SRM_INDEX_CNTL_DATA_7                                                                    0x4c9a
9989 #define regRLC_SRM_INDEX_CNTL_DATA_7_BASE_IDX                                                           1
9990 #define regRLC_SRM_STAT                                                                                 0x4c9b
9991 #define regRLC_SRM_STAT_BASE_IDX                                                                        1
9992 #define regRLC_GPM_GENERAL_8                                                                            0x4cad
9993 #define regRLC_GPM_GENERAL_8_BASE_IDX                                                                   1
9994 #define regRLC_GPM_GENERAL_9                                                                            0x4cae
9995 #define regRLC_GPM_GENERAL_9_BASE_IDX                                                                   1
9996 #define regRLC_GPM_GENERAL_10                                                                           0x4caf
9997 #define regRLC_GPM_GENERAL_10_BASE_IDX                                                                  1
9998 #define regRLC_GPM_GENERAL_11                                                                           0x4cb0
9999 #define regRLC_GPM_GENERAL_11_BASE_IDX                                                                  1
10000 #define regRLC_GPM_GENERAL_12                                                                           0x4cb1
10001 #define regRLC_GPM_GENERAL_12_BASE_IDX                                                                  1
10002 #define regRLC_GPM_UTCL1_CNTL_0                                                                         0x4cb2
10003 #define regRLC_GPM_UTCL1_CNTL_0_BASE_IDX                                                                1
10004 #define regRLC_GPM_UTCL1_CNTL_1                                                                         0x4cb3
10005 #define regRLC_GPM_UTCL1_CNTL_1_BASE_IDX                                                                1
10006 #define regRLC_GPM_UTCL1_CNTL_2                                                                         0x4cb4
10007 #define regRLC_GPM_UTCL1_CNTL_2_BASE_IDX                                                                1
10008 #define regRLC_SPM_UTCL1_CNTL                                                                           0x4cb5
10009 #define regRLC_SPM_UTCL1_CNTL_BASE_IDX                                                                  1
10010 #define regRLC_UTCL1_STATUS_2                                                                           0x4cb6
10011 #define regRLC_UTCL1_STATUS_2_BASE_IDX                                                                  1
10012 #define regRLC_SPM_UTCL1_ERROR_1                                                                        0x4cbc
10013 #define regRLC_SPM_UTCL1_ERROR_1_BASE_IDX                                                               1
10014 #define regRLC_SPM_UTCL1_ERROR_2                                                                        0x4cbd
10015 #define regRLC_SPM_UTCL1_ERROR_2_BASE_IDX                                                               1
10016 #define regRLC_GPM_UTCL1_TH0_ERROR_1                                                                    0x4cbe
10017 #define regRLC_GPM_UTCL1_TH0_ERROR_1_BASE_IDX                                                           1
10018 #define regRLC_GPM_UTCL1_TH0_ERROR_2                                                                    0x4cc0
10019 #define regRLC_GPM_UTCL1_TH0_ERROR_2_BASE_IDX                                                           1
10020 #define regRLC_GPM_UTCL1_TH1_ERROR_1                                                                    0x4cc1
10021 #define regRLC_GPM_UTCL1_TH1_ERROR_1_BASE_IDX                                                           1
10022 #define regRLC_GPM_UTCL1_TH1_ERROR_2                                                                    0x4cc2
10023 #define regRLC_GPM_UTCL1_TH1_ERROR_2_BASE_IDX                                                           1
10024 #define regRLC_GPM_UTCL1_TH2_ERROR_1                                                                    0x4cc3
10025 #define regRLC_GPM_UTCL1_TH2_ERROR_1_BASE_IDX                                                           1
10026 #define regRLC_GPM_UTCL1_TH2_ERROR_2                                                                    0x4cc4
10027 #define regRLC_GPM_UTCL1_TH2_ERROR_2_BASE_IDX                                                           1
10028 #define regRLC_CGCG_CGLS_CTRL_3D                                                                        0x4cc5
10029 #define regRLC_CGCG_CGLS_CTRL_3D_BASE_IDX                                                               1
10030 #define regRLC_CGCG_RAMP_CTRL_3D                                                                        0x4cc6
10031 #define regRLC_CGCG_RAMP_CTRL_3D_BASE_IDX                                                               1
10032 #define regRLC_SEMAPHORE_0                                                                              0x4cc7
10033 #define regRLC_SEMAPHORE_0_BASE_IDX                                                                     1
10034 #define regRLC_SEMAPHORE_1                                                                              0x4cc8
10035 #define regRLC_SEMAPHORE_1_BASE_IDX                                                                     1
10036 #define regRLC_SEMAPHORE_2                                                                              0x4cc9
10037 #define regRLC_SEMAPHORE_2_BASE_IDX                                                                     1
10038 #define regRLC_SEMAPHORE_3                                                                              0x4cca
10039 #define regRLC_SEMAPHORE_3_BASE_IDX                                                                     1
10040 #define regRLC_PACE_INT_STAT                                                                            0x4ccc
10041 #define regRLC_PACE_INT_STAT_BASE_IDX                                                                   1
10042 #define regRLC_UTCL1_STATUS                                                                             0x4cd4
10043 #define regRLC_UTCL1_STATUS_BASE_IDX                                                                    1
10044 #define regRLC_R2I_CNTL_0                                                                               0x4cd5
10045 #define regRLC_R2I_CNTL_0_BASE_IDX                                                                      1
10046 #define regRLC_R2I_CNTL_1                                                                               0x4cd6
10047 #define regRLC_R2I_CNTL_1_BASE_IDX                                                                      1
10048 #define regRLC_R2I_CNTL_2                                                                               0x4cd7
10049 #define regRLC_R2I_CNTL_2_BASE_IDX                                                                      1
10050 #define regRLC_R2I_CNTL_3                                                                               0x4cd8
10051 #define regRLC_R2I_CNTL_3_BASE_IDX                                                                      1
10052 #define regRLC_GPM_INT_STAT_TH0                                                                         0x4cdc
10053 #define regRLC_GPM_INT_STAT_TH0_BASE_IDX                                                                1
10054 #define regRLC_GPM_GENERAL_13                                                                           0x4cdd
10055 #define regRLC_GPM_GENERAL_13_BASE_IDX                                                                  1
10056 #define regRLC_GPM_GENERAL_14                                                                           0x4cde
10057 #define regRLC_GPM_GENERAL_14_BASE_IDX                                                                  1
10058 #define regRLC_GPM_GENERAL_15                                                                           0x4cdf
10059 #define regRLC_GPM_GENERAL_15_BASE_IDX                                                                  1
10060 #define regRLC_CAPTURE_GPU_CLOCK_COUNT_1                                                                0x4cea
10061 #define regRLC_CAPTURE_GPU_CLOCK_COUNT_1_BASE_IDX                                                       1
10062 #define regRLC_GPU_CLOCK_COUNT_LSB_2                                                                    0x4ceb
10063 #define regRLC_GPU_CLOCK_COUNT_LSB_2_BASE_IDX                                                           1
10064 #define regRLC_GPU_CLOCK_COUNT_MSB_2                                                                    0x4cec
10065 #define regRLC_GPU_CLOCK_COUNT_MSB_2_BASE_IDX                                                           1
10066 #define regRLC_PACE_INT_DISABLE                                                                         0x4ced
10067 #define regRLC_PACE_INT_DISABLE_BASE_IDX                                                                1
10068 #define regRLC_CAPTURE_GPU_CLOCK_COUNT_2                                                                0x4cef
10069 #define regRLC_CAPTURE_GPU_CLOCK_COUNT_2_BASE_IDX                                                       1
10070 #define regRLC_RLCV_DOORBELL_RANGE                                                                      0x4cf0
10071 #define regRLC_RLCV_DOORBELL_RANGE_BASE_IDX                                                             1
10072 #define regRLC_RLCV_DOORBELL_CNTL                                                                       0x4cf1
10073 #define regRLC_RLCV_DOORBELL_CNTL_BASE_IDX                                                              1
10074 #define regRLC_RLCV_DOORBELL_STAT                                                                       0x4cf2
10075 #define regRLC_RLCV_DOORBELL_STAT_BASE_IDX                                                              1
10076 #define regRLC_RLCV_DOORBELL_0_DATA_LO                                                                  0x4cf3
10077 #define regRLC_RLCV_DOORBELL_0_DATA_LO_BASE_IDX                                                         1
10078 #define regRLC_RLCV_DOORBELL_0_DATA_HI                                                                  0x4cf4
10079 #define regRLC_RLCV_DOORBELL_0_DATA_HI_BASE_IDX                                                         1
10080 #define regRLC_RLCV_DOORBELL_1_DATA_LO                                                                  0x4cf5
10081 #define regRLC_RLCV_DOORBELL_1_DATA_LO_BASE_IDX                                                         1
10082 #define regRLC_RLCV_DOORBELL_1_DATA_HI                                                                  0x4cf6
10083 #define regRLC_RLCV_DOORBELL_1_DATA_HI_BASE_IDX                                                         1
10084 #define regRLC_RLCV_DOORBELL_2_DATA_LO                                                                  0x4cf7
10085 #define regRLC_RLCV_DOORBELL_2_DATA_LO_BASE_IDX                                                         1
10086 #define regRLC_RLCV_DOORBELL_2_DATA_HI                                                                  0x4cf8
10087 #define regRLC_RLCV_DOORBELL_2_DATA_HI_BASE_IDX                                                         1
10088 #define regRLC_RLCV_DOORBELL_3_DATA_LO                                                                  0x4cf9
10089 #define regRLC_RLCV_DOORBELL_3_DATA_LO_BASE_IDX                                                         1
10090 #define regRLC_RLCV_DOORBELL_3_DATA_HI                                                                  0x4cfa
10091 #define regRLC_RLCV_DOORBELL_3_DATA_HI_BASE_IDX                                                         1
10092 #define regRLC_GPU_CLOCK_COUNT_LSB_1                                                                    0x4cfb
10093 #define regRLC_GPU_CLOCK_COUNT_LSB_1_BASE_IDX                                                           1
10094 #define regRLC_GPU_CLOCK_COUNT_MSB_1                                                                    0x4cfc
10095 #define regRLC_GPU_CLOCK_COUNT_MSB_1_BASE_IDX                                                           1
10096 #define regRLC_RLCV_SPARE_INT                                                                           0x4d00
10097 #define regRLC_RLCV_SPARE_INT_BASE_IDX                                                                  1
10098 #define regRLC_PACE_TIMER_INT_0                                                                         0x4d04
10099 #define regRLC_PACE_TIMER_INT_0_BASE_IDX                                                                1
10100 #define regRLC_PACE_TIMER_INT_1                                                                         0x4d05
10101 #define regRLC_PACE_TIMER_INT_1_BASE_IDX                                                                1
10102 #define regRLC_PACE_TIMER_CTRL                                                                          0x4d06
10103 #define regRLC_PACE_TIMER_CTRL_BASE_IDX                                                                 1
10104 #define regRLC_SMU_CLK_REQ                                                                              0x4d08
10105 #define regRLC_SMU_CLK_REQ_BASE_IDX                                                                     1
10106 #define regRLC_CP_STAT_INVAL_STAT                                                                       0x4d09
10107 #define regRLC_CP_STAT_INVAL_STAT_BASE_IDX                                                              1
10108 #define regRLC_CP_STAT_INVAL_CTRL                                                                       0x4d0a
10109 #define regRLC_CP_STAT_INVAL_CTRL_BASE_IDX                                                              1
10110 #define regRLC_SPARE                                                                                    0x4d0b
10111 #define regRLC_SPARE_BASE_IDX                                                                           1
10112 #define regRLC_SPP_CTRL                                                                                 0x4d0c
10113 #define regRLC_SPP_CTRL_BASE_IDX                                                                        1
10114 #define regRLC_SPP_SHADER_PROFILE_EN                                                                    0x4d0d
10115 #define regRLC_SPP_SHADER_PROFILE_EN_BASE_IDX                                                           1
10116 #define regRLC_SPP_SSF_CAPTURE_EN                                                                       0x4d0e
10117 #define regRLC_SPP_SSF_CAPTURE_EN_BASE_IDX                                                              1
10118 #define regRLC_SPP_SSF_THRESHOLD_0                                                                      0x4d0f
10119 #define regRLC_SPP_SSF_THRESHOLD_0_BASE_IDX                                                             1
10120 #define regRLC_SPP_SSF_THRESHOLD_1                                                                      0x4d10
10121 #define regRLC_SPP_SSF_THRESHOLD_1_BASE_IDX                                                             1
10122 #define regRLC_SPP_SSF_THRESHOLD_2                                                                      0x4d11
10123 #define regRLC_SPP_SSF_THRESHOLD_2_BASE_IDX                                                             1
10124 #define regRLC_SPP_INFLIGHT_RD_ADDR                                                                     0x4d12
10125 #define regRLC_SPP_INFLIGHT_RD_ADDR_BASE_IDX                                                            1
10126 #define regRLC_SPP_INFLIGHT_RD_DATA                                                                     0x4d13
10127 #define regRLC_SPP_INFLIGHT_RD_DATA_BASE_IDX                                                            1
10128 #define regRLC_SPP_PROF_INFO_1                                                                          0x4d18
10129 #define regRLC_SPP_PROF_INFO_1_BASE_IDX                                                                 1
10130 #define regRLC_SPP_PROF_INFO_2                                                                          0x4d19
10131 #define regRLC_SPP_PROF_INFO_2_BASE_IDX                                                                 1
10132 #define regRLC_SPP_GLOBAL_SH_ID                                                                         0x4d1a
10133 #define regRLC_SPP_GLOBAL_SH_ID_BASE_IDX                                                                1
10134 #define regRLC_SPP_GLOBAL_SH_ID_VALID                                                                   0x4d1b
10135 #define regRLC_SPP_GLOBAL_SH_ID_VALID_BASE_IDX                                                          1
10136 #define regRLC_SPP_STATUS                                                                               0x4d1c
10137 #define regRLC_SPP_STATUS_BASE_IDX                                                                      1
10138 #define regRLC_SPP_PVT_STAT_0                                                                           0x4d1d
10139 #define regRLC_SPP_PVT_STAT_0_BASE_IDX                                                                  1
10140 #define regRLC_SPP_PVT_STAT_1                                                                           0x4d1e
10141 #define regRLC_SPP_PVT_STAT_1_BASE_IDX                                                                  1
10142 #define regRLC_SPP_PVT_STAT_2                                                                           0x4d1f
10143 #define regRLC_SPP_PVT_STAT_2_BASE_IDX                                                                  1
10144 #define regRLC_SPP_PVT_STAT_3                                                                           0x4d20
10145 #define regRLC_SPP_PVT_STAT_3_BASE_IDX                                                                  1
10146 #define regRLC_SPP_PVT_LEVEL_MAX                                                                        0x4d21
10147 #define regRLC_SPP_PVT_LEVEL_MAX_BASE_IDX                                                               1
10148 #define regRLC_SPP_STALL_STATE_UPDATE                                                                   0x4d22
10149 #define regRLC_SPP_STALL_STATE_UPDATE_BASE_IDX                                                          1
10150 #define regRLC_SPP_PBB_INFO                                                                             0x4d23
10151 #define regRLC_SPP_PBB_INFO_BASE_IDX                                                                    1
10152 #define regRLC_SPP_RESET                                                                                0x4d24
10153 #define regRLC_SPP_RESET_BASE_IDX                                                                       1
10154 #define regRLC_RLCP_DOORBELL_RANGE                                                                      0x4d26
10155 #define regRLC_RLCP_DOORBELL_RANGE_BASE_IDX                                                             1
10156 #define regRLC_RLCP_DOORBELL_CNTL                                                                       0x4d27
10157 #define regRLC_RLCP_DOORBELL_CNTL_BASE_IDX                                                              1
10158 #define regRLC_RLCP_DOORBELL_STAT                                                                       0x4d28
10159 #define regRLC_RLCP_DOORBELL_STAT_BASE_IDX                                                              1
10160 #define regRLC_RLCP_DOORBELL_0_DATA_LO                                                                  0x4d29
10161 #define regRLC_RLCP_DOORBELL_0_DATA_LO_BASE_IDX                                                         1
10162 #define regRLC_RLCP_DOORBELL_0_DATA_HI                                                                  0x4d2a
10163 #define regRLC_RLCP_DOORBELL_0_DATA_HI_BASE_IDX                                                         1
10164 #define regRLC_RLCP_DOORBELL_1_DATA_LO                                                                  0x4d2b
10165 #define regRLC_RLCP_DOORBELL_1_DATA_LO_BASE_IDX                                                         1
10166 #define regRLC_RLCP_DOORBELL_1_DATA_HI                                                                  0x4d2c
10167 #define regRLC_RLCP_DOORBELL_1_DATA_HI_BASE_IDX                                                         1
10168 #define regRLC_RLCP_DOORBELL_2_DATA_LO                                                                  0x4d2d
10169 #define regRLC_RLCP_DOORBELL_2_DATA_LO_BASE_IDX                                                         1
10170 #define regRLC_RLCP_DOORBELL_2_DATA_HI                                                                  0x4d2e
10171 #define regRLC_RLCP_DOORBELL_2_DATA_HI_BASE_IDX                                                         1
10172 #define regRLC_RLCP_DOORBELL_3_DATA_LO                                                                  0x4d2f
10173 #define regRLC_RLCP_DOORBELL_3_DATA_LO_BASE_IDX                                                         1
10174 #define regRLC_RLCP_DOORBELL_3_DATA_HI                                                                  0x4d30
10175 #define regRLC_RLCP_DOORBELL_3_DATA_HI_BASE_IDX                                                         1
10176 #define regRLC_CAC_MASK_CNTL                                                                            0x4d45
10177 #define regRLC_CAC_MASK_CNTL_BASE_IDX                                                                   1
10178 #define regRLC_POWER_RESIDENCY_CNTR_CTRL                                                                0x4d48
10179 #define regRLC_POWER_RESIDENCY_CNTR_CTRL_BASE_IDX                                                       1
10180 #define regRLC_CLK_RESIDENCY_CNTR_CTRL                                                                  0x4d49
10181 #define regRLC_CLK_RESIDENCY_CNTR_CTRL_BASE_IDX                                                         1
10182 #define regRLC_DS_RESIDENCY_CNTR_CTRL                                                                   0x4d4a
10183 #define regRLC_DS_RESIDENCY_CNTR_CTRL_BASE_IDX                                                          1
10184 #define regRLC_ULV_RESIDENCY_CNTR_CTRL                                                                  0x4d4b
10185 #define regRLC_ULV_RESIDENCY_CNTR_CTRL_BASE_IDX                                                         1
10186 #define regRLC_PCC_RESIDENCY_CNTR_CTRL                                                                  0x4d4c
10187 #define regRLC_PCC_RESIDENCY_CNTR_CTRL_BASE_IDX                                                         1
10188 #define regRLC_GENERAL_RESIDENCY_CNTR_CTRL                                                              0x4d4d
10189 #define regRLC_GENERAL_RESIDENCY_CNTR_CTRL_BASE_IDX                                                     1
10190 #define regRLC_POWER_RESIDENCY_EVENT_CNTR                                                               0x4d50
10191 #define regRLC_POWER_RESIDENCY_EVENT_CNTR_BASE_IDX                                                      1
10192 #define regRLC_CLK_RESIDENCY_EVENT_CNTR                                                                 0x4d51
10193 #define regRLC_CLK_RESIDENCY_EVENT_CNTR_BASE_IDX                                                        1
10194 #define regRLC_DS_RESIDENCY_EVENT_CNTR                                                                  0x4d52
10195 #define regRLC_DS_RESIDENCY_EVENT_CNTR_BASE_IDX                                                         1
10196 #define regRLC_ULV_RESIDENCY_EVENT_CNTR                                                                 0x4d53
10197 #define regRLC_ULV_RESIDENCY_EVENT_CNTR_BASE_IDX                                                        1
10198 #define regRLC_PCC_RESIDENCY_EVENT_CNTR                                                                 0x4d54
10199 #define regRLC_PCC_RESIDENCY_EVENT_CNTR_BASE_IDX                                                        1
10200 #define regRLC_GENERAL_RESIDENCY_EVENT_CNTR                                                             0x4d55
10201 #define regRLC_GENERAL_RESIDENCY_EVENT_CNTR_BASE_IDX                                                    1
10202 #define regRLC_POWER_RESIDENCY_REF_CNTR                                                                 0x4d58
10203 #define regRLC_POWER_RESIDENCY_REF_CNTR_BASE_IDX                                                        1
10204 #define regRLC_CLK_RESIDENCY_REF_CNTR                                                                   0x4d59
10205 #define regRLC_CLK_RESIDENCY_REF_CNTR_BASE_IDX                                                          1
10206 #define regRLC_DS_RESIDENCY_REF_CNTR                                                                    0x4d5a
10207 #define regRLC_DS_RESIDENCY_REF_CNTR_BASE_IDX                                                           1
10208 #define regRLC_ULV_RESIDENCY_REF_CNTR                                                                   0x4d5b
10209 #define regRLC_ULV_RESIDENCY_REF_CNTR_BASE_IDX                                                          1
10210 #define regRLC_PCC_RESIDENCY_REF_CNTR                                                                   0x4d5c
10211 #define regRLC_PCC_RESIDENCY_REF_CNTR_BASE_IDX                                                          1
10212 #define regRLC_GENERAL_RESIDENCY_REF_CNTR                                                               0x4d5d
10213 #define regRLC_GENERAL_RESIDENCY_REF_CNTR_BASE_IDX                                                      1
10214 #define regRLC_GFX_IH_CLIENT_CTRL                                                                       0x4d5e
10215 #define regRLC_GFX_IH_CLIENT_CTRL_BASE_IDX                                                              1
10216 #define regRLC_GFX_IH_ARBITER_STAT                                                                      0x4d5f
10217 #define regRLC_GFX_IH_ARBITER_STAT_BASE_IDX                                                             1
10218 #define regRLC_GFX_IH_CLIENT_SE_STAT_L                                                                  0x4d60
10219 #define regRLC_GFX_IH_CLIENT_SE_STAT_L_BASE_IDX                                                         1
10220 #define regRLC_GFX_IH_CLIENT_SE_STAT_H                                                                  0x4d61
10221 #define regRLC_GFX_IH_CLIENT_SE_STAT_H_BASE_IDX                                                         1
10222 #define regRLC_GFX_IH_CLIENT_SDMA_STAT                                                                  0x4d62
10223 #define regRLC_GFX_IH_CLIENT_SDMA_STAT_BASE_IDX                                                         1
10224 #define regRLC_GFX_IH_CLIENT_OTHER_STAT                                                                 0x4d63
10225 #define regRLC_GFX_IH_CLIENT_OTHER_STAT_BASE_IDX                                                        1
10226 #define regRLC_SPM_GLOBAL_DELAY_IND_ADDR                                                                0x4d64
10227 #define regRLC_SPM_GLOBAL_DELAY_IND_ADDR_BASE_IDX                                                       1
10228 #define regRLC_SPM_GLOBAL_DELAY_IND_DATA                                                                0x4d65
10229 #define regRLC_SPM_GLOBAL_DELAY_IND_DATA_BASE_IDX                                                       1
10230 #define regRLC_SPM_SE_DELAY_IND_ADDR                                                                    0x4d66
10231 #define regRLC_SPM_SE_DELAY_IND_ADDR_BASE_IDX                                                           1
10232 #define regRLC_SPM_SE_DELAY_IND_DATA                                                                    0x4d67
10233 #define regRLC_SPM_SE_DELAY_IND_DATA_BASE_IDX                                                           1
10234 #define regRLC_LX6_CNTL                                                                                 0x4d80
10235 #define regRLC_LX6_CNTL_BASE_IDX                                                                        1
10236 #define regRLC_XT_CORE_STATUS                                                                           0x4dd4
10237 #define regRLC_XT_CORE_STATUS_BASE_IDX                                                                  1
10238 #define regRLC_XT_CORE_INTERRUPT                                                                        0x4dd5
10239 #define regRLC_XT_CORE_INTERRUPT_BASE_IDX                                                               1
10240 #define regRLC_XT_CORE_FAULT_INFO                                                                       0x4dd6
10241 #define regRLC_XT_CORE_FAULT_INFO_BASE_IDX                                                              1
10242 #define regRLC_XT_CORE_ALT_RESET_VEC                                                                    0x4dd7
10243 #define regRLC_XT_CORE_ALT_RESET_VEC_BASE_IDX                                                           1
10244 #define regRLC_XT_CORE_RESERVED                                                                         0x4dd8
10245 #define regRLC_XT_CORE_RESERVED_BASE_IDX                                                                1
10246 #define regRLC_XT_INT_VEC_FORCE                                                                         0x4dd9
10247 #define regRLC_XT_INT_VEC_FORCE_BASE_IDX                                                                1
10248 #define regRLC_XT_INT_VEC_CLEAR                                                                         0x4dda
10249 #define regRLC_XT_INT_VEC_CLEAR_BASE_IDX                                                                1
10250 #define regRLC_XT_INT_VEC_MUX_SEL                                                                       0x4ddb
10251 #define regRLC_XT_INT_VEC_MUX_SEL_BASE_IDX                                                              1
10252 #define regRLC_XT_INT_VEC_MUX_INT_SEL                                                                   0x4ddc
10253 #define regRLC_XT_INT_VEC_MUX_INT_SEL_BASE_IDX                                                          1
10254 #define regRLC_GPU_CLOCK_COUNT_SPM_LSB                                                                  0x4de4
10255 #define regRLC_GPU_CLOCK_COUNT_SPM_LSB_BASE_IDX                                                         1
10256 #define regRLC_GPU_CLOCK_COUNT_SPM_MSB                                                                  0x4de5
10257 #define regRLC_GPU_CLOCK_COUNT_SPM_MSB_BASE_IDX                                                         1
10258 #define regRLC_SPM_THREAD_TRACE_CTRL                                                                    0x4de6
10259 #define regRLC_SPM_THREAD_TRACE_CTRL_BASE_IDX                                                           1
10260 #define regRLC_SPP_CAM_ADDR                                                                             0x4de8
10261 #define regRLC_SPP_CAM_ADDR_BASE_IDX                                                                    1
10262 #define regRLC_SPP_CAM_DATA                                                                             0x4de9
10263 #define regRLC_SPP_CAM_DATA_BASE_IDX                                                                    1
10264 #define regRLC_SPP_CAM_EXT_ADDR                                                                         0x4dea
10265 #define regRLC_SPP_CAM_EXT_ADDR_BASE_IDX                                                                1
10266 #define regRLC_SPP_CAM_EXT_DATA                                                                         0x4deb
10267 #define regRLC_SPP_CAM_EXT_DATA_BASE_IDX                                                                1
10268 #define regRLC_XT_DOORBELL_RANGE                                                                        0x4df5
10269 #define regRLC_XT_DOORBELL_RANGE_BASE_IDX                                                               1
10270 #define regRLC_XT_DOORBELL_CNTL                                                                         0x4df6
10271 #define regRLC_XT_DOORBELL_CNTL_BASE_IDX                                                                1
10272 #define regRLC_XT_DOORBELL_STAT                                                                         0x4df7
10273 #define regRLC_XT_DOORBELL_STAT_BASE_IDX                                                                1
10274 #define regRLC_XT_DOORBELL_0_DATA_LO                                                                    0x4df8
10275 #define regRLC_XT_DOORBELL_0_DATA_LO_BASE_IDX                                                           1
10276 #define regRLC_XT_DOORBELL_0_DATA_HI                                                                    0x4df9
10277 #define regRLC_XT_DOORBELL_0_DATA_HI_BASE_IDX                                                           1
10278 #define regRLC_XT_DOORBELL_1_DATA_LO                                                                    0x4dfa
10279 #define regRLC_XT_DOORBELL_1_DATA_LO_BASE_IDX                                                           1
10280 #define regRLC_XT_DOORBELL_1_DATA_HI                                                                    0x4dfb
10281 #define regRLC_XT_DOORBELL_1_DATA_HI_BASE_IDX                                                           1
10282 #define regRLC_XT_DOORBELL_2_DATA_LO                                                                    0x4dfc
10283 #define regRLC_XT_DOORBELL_2_DATA_LO_BASE_IDX                                                           1
10284 #define regRLC_XT_DOORBELL_2_DATA_HI                                                                    0x4dfd
10285 #define regRLC_XT_DOORBELL_2_DATA_HI_BASE_IDX                                                           1
10286 #define regRLC_XT_DOORBELL_3_DATA_LO                                                                    0x4dfe
10287 #define regRLC_XT_DOORBELL_3_DATA_LO_BASE_IDX                                                           1
10288 #define regRLC_XT_DOORBELL_3_DATA_HI                                                                    0x4dff
10289 #define regRLC_XT_DOORBELL_3_DATA_HI_BASE_IDX                                                           1
10290 #define regRLC_MEM_SLP_CNTL                                                                             0x4e00
10291 #define regRLC_MEM_SLP_CNTL_BASE_IDX                                                                    1
10292 #define regSMU_RLC_RESPONSE                                                                             0x4e01
10293 #define regSMU_RLC_RESPONSE_BASE_IDX                                                                    1
10294 #define regRLC_RLCV_SAFE_MODE                                                                           0x4e02
10295 #define regRLC_RLCV_SAFE_MODE_BASE_IDX                                                                  1
10296 #define regRLC_SMU_SAFE_MODE                                                                            0x4e03
10297 #define regRLC_SMU_SAFE_MODE_BASE_IDX                                                                   1
10298 #define regRLC_RLCV_COMMAND                                                                             0x4e04
10299 #define regRLC_RLCV_COMMAND_BASE_IDX                                                                    1
10300 #define regRLC_SMU_MESSAGE                                                                              0x4e05
10301 #define regRLC_SMU_MESSAGE_BASE_IDX                                                                     1
10302 #define regRLC_SMU_MESSAGE_1                                                                            0x4e06
10303 #define regRLC_SMU_MESSAGE_1_BASE_IDX                                                                   1
10304 #define regRLC_SMU_MESSAGE_2                                                                            0x4e07
10305 #define regRLC_SMU_MESSAGE_2_BASE_IDX                                                                   1
10306 #define regRLC_SRM_GPM_COMMAND                                                                          0x4e08
10307 #define regRLC_SRM_GPM_COMMAND_BASE_IDX                                                                 1
10308 #define regRLC_SRM_GPM_ABORT                                                                            0x4e09
10309 #define regRLC_SRM_GPM_ABORT_BASE_IDX                                                                   1
10310 #define regRLC_SMU_COMMAND                                                                              0x4e0a
10311 #define regRLC_SMU_COMMAND_BASE_IDX                                                                     1
10312 #define regRLC_SMU_ARGUMENT_1                                                                           0x4e0b
10313 #define regRLC_SMU_ARGUMENT_1_BASE_IDX                                                                  1
10314 #define regRLC_SMU_ARGUMENT_2                                                                           0x4e0c
10315 #define regRLC_SMU_ARGUMENT_2_BASE_IDX                                                                  1
10316 #define regRLC_SMU_ARGUMENT_3                                                                           0x4e0d
10317 #define regRLC_SMU_ARGUMENT_3_BASE_IDX                                                                  1
10318 #define regRLC_SMU_ARGUMENT_4                                                                           0x4e0e
10319 #define regRLC_SMU_ARGUMENT_4_BASE_IDX                                                                  1
10320 #define regRLC_SMU_ARGUMENT_5                                                                           0x4e0f
10321 #define regRLC_SMU_ARGUMENT_5_BASE_IDX                                                                  1
10322 #define regRLC_IMU_BOOTLOAD_ADDR_HI                                                                     0x4e10
10323 #define regRLC_IMU_BOOTLOAD_ADDR_HI_BASE_IDX                                                            1
10324 #define regRLC_IMU_BOOTLOAD_ADDR_LO                                                                     0x4e11
10325 #define regRLC_IMU_BOOTLOAD_ADDR_LO_BASE_IDX                                                            1
10326 #define regRLC_IMU_BOOTLOAD_SIZE                                                                        0x4e12
10327 #define regRLC_IMU_BOOTLOAD_SIZE_BASE_IDX                                                               1
10328 #define regRLC_IMU_MISC                                                                                 0x4e16
10329 #define regRLC_IMU_MISC_BASE_IDX                                                                        1
10330 #define regRLC_IMU_RESET_VECTOR                                                                         0x4e17
10331 #define regRLC_IMU_RESET_VECTOR_BASE_IDX                                                                1
10332 
10333 
10334 // addressBlock: gc_rlcsdec
10335 // base address: 0x3b980
10336 #define regRLC_RLCS_DEC_START                                                                           0x4e60
10337 #define regRLC_RLCS_DEC_START_BASE_IDX                                                                  1
10338 #define regRLC_RLCS_DEC_DUMP_ADDR                                                                       0x4e61
10339 #define regRLC_RLCS_DEC_DUMP_ADDR_BASE_IDX                                                              1
10340 #define regRLC_RLCS_EXCEPTION_REG_1                                                                     0x4e62
10341 #define regRLC_RLCS_EXCEPTION_REG_1_BASE_IDX                                                            1
10342 #define regRLC_RLCS_EXCEPTION_REG_2                                                                     0x4e63
10343 #define regRLC_RLCS_EXCEPTION_REG_2_BASE_IDX                                                            1
10344 #define regRLC_RLCS_EXCEPTION_REG_3                                                                     0x4e64
10345 #define regRLC_RLCS_EXCEPTION_REG_3_BASE_IDX                                                            1
10346 #define regRLC_RLCS_EXCEPTION_REG_4                                                                     0x4e65
10347 #define regRLC_RLCS_EXCEPTION_REG_4_BASE_IDX                                                            1
10348 #define regRLC_RLCS_CGCG_REQUEST                                                                        0x4e66
10349 #define regRLC_RLCS_CGCG_REQUEST_BASE_IDX                                                               1
10350 #define regRLC_RLCS_CGCG_STATUS                                                                         0x4e67
10351 #define regRLC_RLCS_CGCG_STATUS_BASE_IDX                                                                1
10352 #define regRLC_RLCS_SOC_DS_CNTL                                                                         0x4e68
10353 #define regRLC_RLCS_SOC_DS_CNTL_BASE_IDX                                                                1
10354 #define regRLC_RLCS_GFX_DS_CNTL                                                                         0x4e69
10355 #define regRLC_RLCS_GFX_DS_CNTL_BASE_IDX                                                                1
10356 #define regRLC_RLCS_GFX_DS_ALLOW_MASK_CNTL                                                              0x4e6a
10357 #define regRLC_RLCS_GFX_DS_ALLOW_MASK_CNTL_BASE_IDX                                                     1
10358 #define regRLC_GPM_STAT                                                                                 0x4e6b
10359 #define regRLC_GPM_STAT_BASE_IDX                                                                        1
10360 #define regRLC_RLCS_GPM_STAT                                                                            0x4e6b
10361 #define regRLC_RLCS_GPM_STAT_BASE_IDX                                                                   1
10362 #define regRLC_RLCS_ABORTED_PD_SEQUENCE                                                                 0x4e6c
10363 #define regRLC_RLCS_ABORTED_PD_SEQUENCE_BASE_IDX                                                        1
10364 #define regRLC_RLCS_DIDT_FORCE_STALL                                                                    0x4e6d
10365 #define regRLC_RLCS_DIDT_FORCE_STALL_BASE_IDX                                                           1
10366 #define regRLC_RLCS_IOV_CMD_STATUS                                                                      0x4e6e
10367 #define regRLC_RLCS_IOV_CMD_STATUS_BASE_IDX                                                             1
10368 #define regRLC_RLCS_IOV_CNTX_LOC_SIZE                                                                   0x4e6f
10369 #define regRLC_RLCS_IOV_CNTX_LOC_SIZE_BASE_IDX                                                          1
10370 #define regRLC_RLCS_IOV_SCH_BLOCK                                                                       0x4e70
10371 #define regRLC_RLCS_IOV_SCH_BLOCK_BASE_IDX                                                              1
10372 #define regRLC_RLCS_IOV_VM_BUSY_STATUS                                                                  0x4e71
10373 #define regRLC_RLCS_IOV_VM_BUSY_STATUS_BASE_IDX                                                         1
10374 #define regRLC_RLCS_GPM_STAT_2                                                                          0x4e72
10375 #define regRLC_RLCS_GPM_STAT_2_BASE_IDX                                                                 1
10376 #define regRLC_RLCS_GRBM_SOFT_RESET                                                                     0x4e73
10377 #define regRLC_RLCS_GRBM_SOFT_RESET_BASE_IDX                                                            1
10378 #define regRLC_RLCS_PG_CHANGE_STATUS                                                                    0x4e74
10379 #define regRLC_RLCS_PG_CHANGE_STATUS_BASE_IDX                                                           1
10380 #define regRLC_RLCS_PG_CHANGE_READ                                                                      0x4e75
10381 #define regRLC_RLCS_PG_CHANGE_READ_BASE_IDX                                                             1
10382 #define regRLC_RLCS_IH_SEMAPHORE                                                                        0x4e76
10383 #define regRLC_RLCS_IH_SEMAPHORE_BASE_IDX                                                               1
10384 #define regRLC_RLCS_IH_COOKIE_SEMAPHORE                                                                 0x4e77
10385 #define regRLC_RLCS_IH_COOKIE_SEMAPHORE_BASE_IDX                                                        1
10386 #define regRLC_RLCS_WGP_STATUS                                                                          0x4e78
10387 #define regRLC_RLCS_WGP_STATUS_BASE_IDX                                                                 1
10388 #define regRLC_RLCS_WGP_READ                                                                            0x4e79
10389 #define regRLC_RLCS_WGP_READ_BASE_IDX                                                                   1
10390 #define regRLC_RLCS_CP_INT_CTRL_1                                                                       0x4e7a
10391 #define regRLC_RLCS_CP_INT_CTRL_1_BASE_IDX                                                              1
10392 #define regRLC_RLCS_CP_INT_CTRL_2                                                                       0x4e7b
10393 #define regRLC_RLCS_CP_INT_CTRL_2_BASE_IDX                                                              1
10394 #define regRLC_RLCS_CP_INT_INFO_1                                                                       0x4e7c
10395 #define regRLC_RLCS_CP_INT_INFO_1_BASE_IDX                                                              1
10396 #define regRLC_RLCS_CP_INT_INFO_2                                                                       0x4e7d
10397 #define regRLC_RLCS_CP_INT_INFO_2_BASE_IDX                                                              1
10398 #define regRLC_RLCS_SPM_INT_CTRL                                                                        0x4e7e
10399 #define regRLC_RLCS_SPM_INT_CTRL_BASE_IDX                                                               1
10400 #define regRLC_RLCS_SPM_INT_INFO_1                                                                      0x4e7f
10401 #define regRLC_RLCS_SPM_INT_INFO_1_BASE_IDX                                                             1
10402 #define regRLC_RLCS_SPM_INT_INFO_2                                                                      0x4e80
10403 #define regRLC_RLCS_SPM_INT_INFO_2_BASE_IDX                                                             1
10404 #define regRLC_RLCS_DSM_TRIG                                                                            0x4e81
10405 #define regRLC_RLCS_DSM_TRIG_BASE_IDX                                                                   1
10406 #define regRLC_RLCS_BOOTLOAD_STATUS                                                                     0x4e82
10407 #define regRLC_RLCS_BOOTLOAD_STATUS_BASE_IDX                                                            1
10408 #define regRLC_RLCS_POWER_BRAKE_CNTL                                                                    0x4e83
10409 #define regRLC_RLCS_POWER_BRAKE_CNTL_BASE_IDX                                                           1
10410 #define regRLC_RLCS_POWER_BRAKE_CNTL_TH1                                                                0x4e84
10411 #define regRLC_RLCS_POWER_BRAKE_CNTL_TH1_BASE_IDX                                                       1
10412 #define regRLC_RLCS_GRBM_IDLE_BUSY_STAT                                                                 0x4e85
10413 #define regRLC_RLCS_GRBM_IDLE_BUSY_STAT_BASE_IDX                                                        1
10414 #define regRLC_RLCS_GRBM_IDLE_BUSY_INT_CNTL                                                             0x4e86
10415 #define regRLC_RLCS_GRBM_IDLE_BUSY_INT_CNTL_BASE_IDX                                                    1
10416 #define regRLC_RLCS_CMP_IDLE_CNTL                                                                       0x4e87
10417 #define regRLC_RLCS_CMP_IDLE_CNTL_BASE_IDX                                                              1
10418 #define regRLC_RLCS_GENERAL_0                                                                           0x4e88
10419 #define regRLC_RLCS_GENERAL_0_BASE_IDX                                                                  1
10420 #define regRLC_RLCS_GENERAL_1                                                                           0x4e89
10421 #define regRLC_RLCS_GENERAL_1_BASE_IDX                                                                  1
10422 #define regRLC_RLCS_GENERAL_2                                                                           0x4e8a
10423 #define regRLC_RLCS_GENERAL_2_BASE_IDX                                                                  1
10424 #define regRLC_RLCS_GENERAL_3                                                                           0x4e8b
10425 #define regRLC_RLCS_GENERAL_3_BASE_IDX                                                                  1
10426 #define regRLC_RLCS_GENERAL_4                                                                           0x4e8c
10427 #define regRLC_RLCS_GENERAL_4_BASE_IDX                                                                  1
10428 #define regRLC_RLCS_GENERAL_5                                                                           0x4e8d
10429 #define regRLC_RLCS_GENERAL_5_BASE_IDX                                                                  1
10430 #define regRLC_RLCS_GENERAL_6                                                                           0x4e8e
10431 #define regRLC_RLCS_GENERAL_6_BASE_IDX                                                                  1
10432 #define regRLC_RLCS_GENERAL_7                                                                           0x4e8f
10433 #define regRLC_RLCS_GENERAL_7_BASE_IDX                                                                  1
10434 #define regRLC_RLCS_GENERAL_8                                                                           0x4e90
10435 #define regRLC_RLCS_GENERAL_8_BASE_IDX                                                                  1
10436 #define regRLC_RLCS_GENERAL_9                                                                           0x4e91
10437 #define regRLC_RLCS_GENERAL_9_BASE_IDX                                                                  1
10438 #define regRLC_RLCS_GENERAL_10                                                                          0x4e92
10439 #define regRLC_RLCS_GENERAL_10_BASE_IDX                                                                 1
10440 #define regRLC_RLCS_GENERAL_11                                                                          0x4e93
10441 #define regRLC_RLCS_GENERAL_11_BASE_IDX                                                                 1
10442 #define regRLC_RLCS_GENERAL_12                                                                          0x4e94
10443 #define regRLC_RLCS_GENERAL_12_BASE_IDX                                                                 1
10444 #define regRLC_RLCS_GENERAL_13                                                                          0x4e95
10445 #define regRLC_RLCS_GENERAL_13_BASE_IDX                                                                 1
10446 #define regRLC_RLCS_GENERAL_14                                                                          0x4e96
10447 #define regRLC_RLCS_GENERAL_14_BASE_IDX                                                                 1
10448 #define regRLC_RLCS_GENERAL_15                                                                          0x4e97
10449 #define regRLC_RLCS_GENERAL_15_BASE_IDX                                                                 1
10450 #define regRLC_RLCS_GENERAL_16                                                                          0x4e98
10451 #define regRLC_RLCS_GENERAL_16_BASE_IDX                                                                 1
10452 #define regRLC_RLCS_AUXILIARY_REG_1                                                                     0x4ec5
10453 #define regRLC_RLCS_AUXILIARY_REG_1_BASE_IDX                                                            1
10454 #define regRLC_RLCS_AUXILIARY_REG_2                                                                     0x4ec6
10455 #define regRLC_RLCS_AUXILIARY_REG_2_BASE_IDX                                                            1
10456 #define regRLC_RLCS_AUXILIARY_REG_3                                                                     0x4ec7
10457 #define regRLC_RLCS_AUXILIARY_REG_3_BASE_IDX                                                            1
10458 #define regRLC_RLCS_AUXILIARY_REG_4                                                                     0x4ec8
10459 #define regRLC_RLCS_AUXILIARY_REG_4_BASE_IDX                                                            1
10460 #define regRLC_RLCS_SPM_SQTT_MODE                                                                       0x4ec9
10461 #define regRLC_RLCS_SPM_SQTT_MODE_BASE_IDX                                                              1
10462 #define regRLC_RLCS_CP_DMA_SRCID_OVER                                                                   0x4eca
10463 #define regRLC_RLCS_CP_DMA_SRCID_OVER_BASE_IDX                                                          1
10464 #define regRLC_RLCS_BOOTLOAD_ID_STATUS1                                                                 0x4ecb
10465 #define regRLC_RLCS_BOOTLOAD_ID_STATUS1_BASE_IDX                                                        1
10466 #define regRLC_RLCS_BOOTLOAD_ID_STATUS2                                                                 0x4ecc
10467 #define regRLC_RLCS_BOOTLOAD_ID_STATUS2_BASE_IDX                                                        1
10468 #define regRLC_RLCS_IMU_VIDCHG_CNTL                                                                     0x4ecd
10469 #define regRLC_RLCS_IMU_VIDCHG_CNTL_BASE_IDX                                                            1
10470 #define regRLC_RLCS_EDC_INT_CNTL                                                                        0x4ece
10471 #define regRLC_RLCS_EDC_INT_CNTL_BASE_IDX                                                               1
10472 #define regRLC_RLCS_KMD_LOG_CNTL1                                                                       0x4ecf
10473 #define regRLC_RLCS_KMD_LOG_CNTL1_BASE_IDX                                                              1
10474 #define regRLC_RLCS_KMD_LOG_CNTL2                                                                       0x4ed0
10475 #define regRLC_RLCS_KMD_LOG_CNTL2_BASE_IDX                                                              1
10476 #define regRLC_RLCS_GPM_LEGACY_INT_STAT                                                                 0x4ed1
10477 #define regRLC_RLCS_GPM_LEGACY_INT_STAT_BASE_IDX                                                        1
10478 #define regRLC_RLCS_GPM_LEGACY_INT_DISABLE                                                              0x4ed2
10479 #define regRLC_RLCS_GPM_LEGACY_INT_DISABLE_BASE_IDX                                                     1
10480 #define regRLC_RLCS_SRM_SRCID_CNTL                                                                      0x4ed3
10481 #define regRLC_RLCS_SRM_SRCID_CNTL_BASE_IDX                                                             1
10482 #define regRLC_RLCS_GCR_DATA_0                                                                          0x4ed4
10483 #define regRLC_RLCS_GCR_DATA_0_BASE_IDX                                                                 1
10484 #define regRLC_RLCS_GCR_DATA_1                                                                          0x4ed5
10485 #define regRLC_RLCS_GCR_DATA_1_BASE_IDX                                                                 1
10486 #define regRLC_RLCS_GCR_DATA_2                                                                          0x4ed6
10487 #define regRLC_RLCS_GCR_DATA_2_BASE_IDX                                                                 1
10488 #define regRLC_RLCS_GCR_DATA_3                                                                          0x4ed7
10489 #define regRLC_RLCS_GCR_DATA_3_BASE_IDX                                                                 1
10490 #define regRLC_RLCS_GCR_STATUS                                                                          0x4ed8
10491 #define regRLC_RLCS_GCR_STATUS_BASE_IDX                                                                 1
10492 #define regRLC_RLCS_PERFMON_CLK_CNTL_UCODE                                                              0x4ed9
10493 #define regRLC_RLCS_PERFMON_CLK_CNTL_UCODE_BASE_IDX                                                     1
10494 #define regRLC_RLCS_UTCL2_CNTL                                                                          0x4eda
10495 #define regRLC_RLCS_UTCL2_CNTL_BASE_IDX                                                                 1
10496 #define regRLC_RLCS_IMU_RLC_MSG_DATA0                                                                   0x4edb
10497 #define regRLC_RLCS_IMU_RLC_MSG_DATA0_BASE_IDX                                                          1
10498 #define regRLC_RLCS_IMU_RLC_MSG_DATA1                                                                   0x4edc
10499 #define regRLC_RLCS_IMU_RLC_MSG_DATA1_BASE_IDX                                                          1
10500 #define regRLC_RLCS_IMU_RLC_MSG_DATA2                                                                   0x4edd
10501 #define regRLC_RLCS_IMU_RLC_MSG_DATA2_BASE_IDX                                                          1
10502 #define regRLC_RLCS_IMU_RLC_MSG_DATA3                                                                   0x4ede
10503 #define regRLC_RLCS_IMU_RLC_MSG_DATA3_BASE_IDX                                                          1
10504 #define regRLC_RLCS_IMU_RLC_MSG_DATA4                                                                   0x4edf
10505 #define regRLC_RLCS_IMU_RLC_MSG_DATA4_BASE_IDX                                                          1
10506 #define regRLC_RLCS_IMU_RLC_MSG_CONTROL                                                                 0x4ee0
10507 #define regRLC_RLCS_IMU_RLC_MSG_CONTROL_BASE_IDX                                                        1
10508 #define regRLC_RLCS_IMU_RLC_MSG_CNTL                                                                    0x4ee1
10509 #define regRLC_RLCS_IMU_RLC_MSG_CNTL_BASE_IDX                                                           1
10510 #define regRLC_RLCS_RLC_IMU_MSG_DATA0                                                                   0x4ee2
10511 #define regRLC_RLCS_RLC_IMU_MSG_DATA0_BASE_IDX                                                          1
10512 #define regRLC_RLCS_RLC_IMU_MSG_CONTROL                                                                 0x4ee3
10513 #define regRLC_RLCS_RLC_IMU_MSG_CONTROL_BASE_IDX                                                        1
10514 #define regRLC_RLCS_RLC_IMU_MSG_CNTL                                                                    0x4ee4
10515 #define regRLC_RLCS_RLC_IMU_MSG_CNTL_BASE_IDX                                                           1
10516 #define regRLC_RLCS_IMU_RLC_TELEMETRY_DATA_0                                                            0x4ee5
10517 #define regRLC_RLCS_IMU_RLC_TELEMETRY_DATA_0_BASE_IDX                                                   1
10518 #define regRLC_RLCS_IMU_RLC_TELEMETRY_DATA_1                                                            0x4ee6
10519 #define regRLC_RLCS_IMU_RLC_TELEMETRY_DATA_1_BASE_IDX                                                   1
10520 #define regRLC_RLCS_IMU_RLC_MUTEX_CNTL                                                                  0x4ee7
10521 #define regRLC_RLCS_IMU_RLC_MUTEX_CNTL_BASE_IDX                                                         1
10522 #define regRLC_RLCS_IMU_RLC_STATUS                                                                      0x4ee8
10523 #define regRLC_RLCS_IMU_RLC_STATUS_BASE_IDX                                                             1
10524 #define regRLC_RLCS_RLC_IMU_STATUS                                                                      0x4ee9
10525 #define regRLC_RLCS_RLC_IMU_STATUS_BASE_IDX                                                             1
10526 #define regRLC_RLCS_IMU_RAM_DATA_1                                                                      0x4eea
10527 #define regRLC_RLCS_IMU_RAM_DATA_1_BASE_IDX                                                             1
10528 #define regRLC_RLCS_IMU_RAM_ADDR_1_LSB                                                                  0x4eeb
10529 #define regRLC_RLCS_IMU_RAM_ADDR_1_LSB_BASE_IDX                                                         1
10530 #define regRLC_RLCS_IMU_RAM_ADDR_1_MSB                                                                  0x4eec
10531 #define regRLC_RLCS_IMU_RAM_ADDR_1_MSB_BASE_IDX                                                         1
10532 #define regRLC_RLCS_IMU_RAM_DATA_0                                                                      0x4eed
10533 #define regRLC_RLCS_IMU_RAM_DATA_0_BASE_IDX                                                             1
10534 #define regRLC_RLCS_IMU_RAM_ADDR_0_LSB                                                                  0x4eee
10535 #define regRLC_RLCS_IMU_RAM_ADDR_0_LSB_BASE_IDX                                                         1
10536 #define regRLC_RLCS_IMU_RAM_ADDR_0_MSB                                                                  0x4eef
10537 #define regRLC_RLCS_IMU_RAM_ADDR_0_MSB_BASE_IDX                                                         1
10538 #define regRLC_RLCS_IMU_RAM_CNTL                                                                        0x4ef0
10539 #define regRLC_RLCS_IMU_RAM_CNTL_BASE_IDX                                                               1
10540 #define regRLC_RLCS_IMU_GFX_DOORBELL_FENCE                                                              0x4ef1
10541 #define regRLC_RLCS_IMU_GFX_DOORBELL_FENCE_BASE_IDX                                                     1
10542 #define regRLC_RLCS_SDMA_INT_CNTL_1                                                                     0x4ef3
10543 #define regRLC_RLCS_SDMA_INT_CNTL_1_BASE_IDX                                                            1
10544 #define regRLC_RLCS_SDMA_INT_CNTL_2                                                                     0x4ef4
10545 #define regRLC_RLCS_SDMA_INT_CNTL_2_BASE_IDX                                                            1
10546 #define regRLC_RLCS_SDMA_INT_STAT                                                                       0x4ef5
10547 #define regRLC_RLCS_SDMA_INT_STAT_BASE_IDX                                                              1
10548 #define regRLC_RLCS_SDMA_INT_INFO                                                                       0x4ef6
10549 #define regRLC_RLCS_SDMA_INT_INFO_BASE_IDX                                                              1
10550 #define regRLC_RLCS_PMM_CGCG_CNTL                                                                       0x4ef7
10551 #define regRLC_RLCS_PMM_CGCG_CNTL_BASE_IDX                                                              1
10552 #define regRLC_RLCS_GFX_MEM_POWER_CTRL_LO                                                               0x4ef8
10553 #define regRLC_RLCS_GFX_MEM_POWER_CTRL_LO_BASE_IDX                                                      1
10554 #define regRLC_RLCS_GFX_RM_CNTL                                                                         0x4efa
10555 #define regRLC_RLCS_GFX_RM_CNTL_BASE_IDX                                                                1
10556 #define regRLC_RLCS_DEC_END                                                                             0x4fff
10557 #define regRLC_RLCS_DEC_END_BASE_IDX                                                                    1
10558 
10559 
10560 // addressBlock: gc_pfvfdec_rlc
10561 // base address: 0x2a600
10562 #define regRLC_SAFE_MODE                                                                                0x0980
10563 #define regRLC_SAFE_MODE_BASE_IDX                                                                       1
10564 #define regRLC_SPM_SAMPLE_CNT                                                                           0x0981
10565 #define regRLC_SPM_SAMPLE_CNT_BASE_IDX                                                                  1
10566 #define regRLC_SPM_MC_CNTL                                                                              0x0982
10567 #define regRLC_SPM_MC_CNTL_BASE_IDX                                                                     1
10568 #define regRLC_SPM_INT_CNTL                                                                             0x0983
10569 #define regRLC_SPM_INT_CNTL_BASE_IDX                                                                    1
10570 #define regRLC_SPM_INT_STATUS                                                                           0x0984
10571 #define regRLC_SPM_INT_STATUS_BASE_IDX                                                                  1
10572 #define regRLC_SPM_INT_INFO_1                                                                           0x0985
10573 #define regRLC_SPM_INT_INFO_1_BASE_IDX                                                                  1
10574 #define regRLC_SPM_INT_INFO_2                                                                           0x0986
10575 #define regRLC_SPM_INT_INFO_2_BASE_IDX                                                                  1
10576 #define regRLC_CSIB_ADDR_LO                                                                             0x0987
10577 #define regRLC_CSIB_ADDR_LO_BASE_IDX                                                                    1
10578 #define regRLC_CSIB_ADDR_HI                                                                             0x0988
10579 #define regRLC_CSIB_ADDR_HI_BASE_IDX                                                                    1
10580 #define regRLC_CSIB_LENGTH                                                                              0x0989
10581 #define regRLC_CSIB_LENGTH_BASE_IDX                                                                     1
10582 #define regRLC_CP_SCHEDULERS                                                                            0x098a
10583 #define regRLC_CP_SCHEDULERS_BASE_IDX                                                                   1
10584 #define regRLC_CP_EOF_INT                                                                               0x098b
10585 #define regRLC_CP_EOF_INT_BASE_IDX                                                                      1
10586 #define regRLC_CP_EOF_INT_CNT                                                                           0x098c
10587 #define regRLC_CP_EOF_INT_CNT_BASE_IDX                                                                  1
10588 #define regRLC_SPARE_INT_0                                                                              0x098d
10589 #define regRLC_SPARE_INT_0_BASE_IDX                                                                     1
10590 #define regRLC_SPARE_INT_1                                                                              0x098e
10591 #define regRLC_SPARE_INT_1_BASE_IDX                                                                     1
10592 #define regRLC_SPARE_INT_2                                                                              0x098f
10593 #define regRLC_SPARE_INT_2_BASE_IDX                                                                     1
10594 #define regRLC_PACE_SPARE_INT                                                                           0x0990
10595 #define regRLC_PACE_SPARE_INT_BASE_IDX                                                                  1
10596 #define regRLC_PACE_SPARE_INT_1                                                                         0x0991
10597 #define regRLC_PACE_SPARE_INT_1_BASE_IDX                                                                1
10598 #define regRLC_RLCV_SPARE_INT_1                                                                         0x0992
10599 #define regRLC_RLCV_SPARE_INT_1_BASE_IDX                                                                1
10600 
10601 
10602 // addressBlock: gc_pwrdec
10603 // base address: 0x3c000
10604 #define regCGTS_TCC_DISABLE                                                                             0x5006
10605 #define regCGTS_TCC_DISABLE_BASE_IDX                                                                    1
10606 #define regCGTT_GS_NGG_CLK_CTRL                                                                         0x5087
10607 #define regCGTT_GS_NGG_CLK_CTRL_BASE_IDX                                                                1
10608 #define regCGTT_PA_CLK_CTRL                                                                             0x5088
10609 #define regCGTT_PA_CLK_CTRL_BASE_IDX                                                                    1
10610 #define regCGTT_SC_CLK_CTRL0                                                                            0x5089
10611 #define regCGTT_SC_CLK_CTRL0_BASE_IDX                                                                   1
10612 #define regCGTT_SC_CLK_CTRL1                                                                            0x508a
10613 #define regCGTT_SC_CLK_CTRL1_BASE_IDX                                                                   1
10614 #define regCGTT_SC_CLK_CTRL2                                                                            0x508b
10615 #define regCGTT_SC_CLK_CTRL2_BASE_IDX                                                                   1
10616 #define regCGTT_SQG_CLK_CTRL                                                                            0x508d
10617 #define regCGTT_SQG_CLK_CTRL_BASE_IDX                                                                   1
10618 #define regSQ_ALU_CLK_CTRL                                                                              0x508e
10619 #define regSQ_ALU_CLK_CTRL_BASE_IDX                                                                     1
10620 #define regSQ_TEX_CLK_CTRL                                                                              0x508f
10621 #define regSQ_TEX_CLK_CTRL_BASE_IDX                                                                     1
10622 #define regSQ_LDS_CLK_CTRL                                                                              0x5090
10623 #define regSQ_LDS_CLK_CTRL_BASE_IDX                                                                     1
10624 #define regICG_SP_CLK_CTRL                                                                              0x5093
10625 #define regICG_SP_CLK_CTRL_BASE_IDX                                                                     1
10626 #define regTA_CGTT_CTRL                                                                                 0x509d
10627 #define regTA_CGTT_CTRL_BASE_IDX                                                                        1
10628 #define regDB_CGTT_CLK_CTRL_0                                                                           0x50a4
10629 #define regDB_CGTT_CLK_CTRL_0_BASE_IDX                                                                  1
10630 #define regCB_CGTT_SCLK_CTRL                                                                            0x50a8
10631 #define regCB_CGTT_SCLK_CTRL_BASE_IDX                                                                   1
10632 #define regCGTT_CP_CLK_CTRL                                                                             0x50b0
10633 #define regCGTT_CP_CLK_CTRL_BASE_IDX                                                                    1
10634 #define regCGTT_CPF_CLK_CTRL                                                                            0x50b1
10635 #define regCGTT_CPF_CLK_CTRL_BASE_IDX                                                                   1
10636 #define regCGTT_CPC_CLK_CTRL                                                                            0x50b2
10637 #define regCGTT_CPC_CLK_CTRL_BASE_IDX                                                                   1
10638 #define regCGTT_RLC_CLK_CTRL                                                                            0x50b5
10639 #define regCGTT_RLC_CLK_CTRL_BASE_IDX                                                                   1
10640 #define regCGTT_SC_CLK_CTRL3                                                                            0x50bc
10641 #define regCGTT_SC_CLK_CTRL3_BASE_IDX                                                                   1
10642 #define regCGTT_SC_CLK_CTRL4                                                                            0x50bd
10643 #define regCGTT_SC_CLK_CTRL4_BASE_IDX                                                                   1
10644 #define regGCEA_ICG_CTRL                                                                                0x50c4
10645 #define regGCEA_ICG_CTRL_BASE_IDX                                                                       1
10646 #define regGL1I_GL1R_MGCG_OVERRIDE                                                                      0x50e4
10647 #define regGL1I_GL1R_MGCG_OVERRIDE_BASE_IDX                                                             1
10648 #define regGL1H_ICG_CTRL                                                                                0x50e8
10649 #define regGL1H_ICG_CTRL_BASE_IDX                                                                       1
10650 #define regCHI_CHR_MGCG_OVERRIDE                                                                        0x50e9
10651 #define regCHI_CHR_MGCG_OVERRIDE_BASE_IDX                                                               1
10652 #define regICG_GL1C_CLK_CTRL                                                                            0x50ec
10653 #define regICG_GL1C_CLK_CTRL_BASE_IDX                                                                   1
10654 #define regICG_GL1A_CTRL                                                                                0x50f0
10655 #define regICG_GL1A_CTRL_BASE_IDX                                                                       1
10656 #define regICG_CHA_CTRL                                                                                 0x50f1
10657 #define regICG_CHA_CTRL_BASE_IDX                                                                        1
10658 #define regGUS_ICG_CTRL                                                                                 0x50f4
10659 #define regGUS_ICG_CTRL_BASE_IDX                                                                        1
10660 #define regCGTT_PH_CLK_CTRL0                                                                            0x50f8
10661 #define regCGTT_PH_CLK_CTRL0_BASE_IDX                                                                   1
10662 #define regCGTT_PH_CLK_CTRL1                                                                            0x50f9
10663 #define regCGTT_PH_CLK_CTRL1_BASE_IDX                                                                   1
10664 #define regCGTT_PH_CLK_CTRL2                                                                            0x50fa
10665 #define regCGTT_PH_CLK_CTRL2_BASE_IDX                                                                   1
10666 #define regCGTT_PH_CLK_CTRL3                                                                            0x50fb
10667 #define regCGTT_PH_CLK_CTRL3_BASE_IDX                                                                   1
10668 #define regGFX_ICG_GL2C_CTRL                                                                            0x50fc
10669 #define regGFX_ICG_GL2C_CTRL_BASE_IDX                                                                   1
10670 #define regGFX_ICG_GL2C_CTRL1                                                                           0x50fd
10671 #define regGFX_ICG_GL2C_CTRL1_BASE_IDX                                                                  1
10672 #define regICG_LDS_CLK_CTRL                                                                             0x5114
10673 #define regICG_LDS_CLK_CTRL_BASE_IDX                                                                    1
10674 #define regICG_CHC_CLK_CTRL                                                                             0x5140
10675 #define regICG_CHC_CLK_CTRL_BASE_IDX                                                                    1
10676 #define regICG_CHCG_CLK_CTRL                                                                            0x5144
10677 #define regICG_CHCG_CLK_CTRL_BASE_IDX                                                                   1
10678 
10679 
10680 // addressBlock: gc_hypdec
10681 // base address: 0x3e000
10682 #define regGFX_PIPE_PRIORITY                                                                            0x587f
10683 #define regGFX_PIPE_PRIORITY_BASE_IDX                                                                   1
10684 #define regGRBM_GFX_INDEX_SR_SELECT                                                                     0x5a00
10685 #define regGRBM_GFX_INDEX_SR_SELECT_BASE_IDX                                                            1
10686 #define regGRBM_GFX_INDEX_SR_DATA                                                                       0x5a01
10687 #define regGRBM_GFX_INDEX_SR_DATA_BASE_IDX                                                              1
10688 #define regGRBM_GFX_CNTL_SR_SELECT                                                                      0x5a02
10689 #define regGRBM_GFX_CNTL_SR_SELECT_BASE_IDX                                                             1
10690 #define regGRBM_GFX_CNTL_SR_DATA                                                                        0x5a03
10691 #define regGRBM_GFX_CNTL_SR_DATA_BASE_IDX                                                               1
10692 #define regGC_IH_COOKIE_0_PTR                                                                           0x5a07
10693 #define regGC_IH_COOKIE_0_PTR_BASE_IDX                                                                  1
10694 #define regGRBM_SE_REMAP_CNTL                                                                           0x5a08
10695 #define regGRBM_SE_REMAP_CNTL_BASE_IDX                                                                  1
10696 #define regRLC_GPU_IOV_VF_ENABLE                                                                        0x5b00
10697 #define regRLC_GPU_IOV_VF_ENABLE_BASE_IDX                                                               1
10698 #define regRLC_GPU_IOV_CFG_REG6                                                                         0x5b06
10699 #define regRLC_GPU_IOV_CFG_REG6_BASE_IDX                                                                1
10700 #define regRLC_SDMA0_STATUS                                                                             0x5b18
10701 #define regRLC_SDMA0_STATUS_BASE_IDX                                                                    1
10702 #define regRLC_SDMA1_STATUS                                                                             0x5b19
10703 #define regRLC_SDMA1_STATUS_BASE_IDX                                                                    1
10704 #define regRLC_SDMA2_STATUS                                                                             0x5b1a
10705 #define regRLC_SDMA2_STATUS_BASE_IDX                                                                    1
10706 #define regRLC_SDMA3_STATUS                                                                             0x5b1b
10707 #define regRLC_SDMA3_STATUS_BASE_IDX                                                                    1
10708 #define regRLC_SDMA0_BUSY_STATUS                                                                        0x5b1c
10709 #define regRLC_SDMA0_BUSY_STATUS_BASE_IDX                                                               1
10710 #define regRLC_SDMA1_BUSY_STATUS                                                                        0x5b1d
10711 #define regRLC_SDMA1_BUSY_STATUS_BASE_IDX                                                               1
10712 #define regRLC_SDMA2_BUSY_STATUS                                                                        0x5b1e
10713 #define regRLC_SDMA2_BUSY_STATUS_BASE_IDX                                                               1
10714 #define regRLC_SDMA3_BUSY_STATUS                                                                        0x5b1f
10715 #define regRLC_SDMA3_BUSY_STATUS_BASE_IDX                                                               1
10716 #define regRLC_GPU_IOV_CFG_REG8                                                                         0x5b20
10717 #define regRLC_GPU_IOV_CFG_REG8_BASE_IDX                                                                1
10718 #define regRLC_RLCV_TIMER_INT_0                                                                         0x5b25
10719 #define regRLC_RLCV_TIMER_INT_0_BASE_IDX                                                                1
10720 #define regRLC_RLCV_TIMER_INT_1                                                                         0x5b26
10721 #define regRLC_RLCV_TIMER_INT_1_BASE_IDX                                                                1
10722 #define regRLC_RLCV_TIMER_CTRL                                                                          0x5b27
10723 #define regRLC_RLCV_TIMER_CTRL_BASE_IDX                                                                 1
10724 #define regRLC_RLCV_TIMER_STAT                                                                          0x5b28
10725 #define regRLC_RLCV_TIMER_STAT_BASE_IDX                                                                 1
10726 #define regRLC_GPU_IOV_VF_DOORBELL_STATUS                                                               0x5b2a
10727 #define regRLC_GPU_IOV_VF_DOORBELL_STATUS_BASE_IDX                                                      1
10728 #define regRLC_GPU_IOV_VF_DOORBELL_STATUS_SET                                                           0x5b2b
10729 #define regRLC_GPU_IOV_VF_DOORBELL_STATUS_SET_BASE_IDX                                                  1
10730 #define regRLC_GPU_IOV_VF_DOORBELL_STATUS_CLR                                                           0x5b2c
10731 #define regRLC_GPU_IOV_VF_DOORBELL_STATUS_CLR_BASE_IDX                                                  1
10732 #define regRLC_GPU_IOV_VF_MASK                                                                          0x5b2d
10733 #define regRLC_GPU_IOV_VF_MASK_BASE_IDX                                                                 1
10734 #define regRLC_HYP_SEMAPHORE_0                                                                          0x5b2e
10735 #define regRLC_HYP_SEMAPHORE_0_BASE_IDX                                                                 1
10736 #define regRLC_HYP_SEMAPHORE_1                                                                          0x5b2f
10737 #define regRLC_HYP_SEMAPHORE_1_BASE_IDX                                                                 1
10738 #define regRLC_BUSY_CLK_CNTL                                                                            0x5b30
10739 #define regRLC_BUSY_CLK_CNTL_BASE_IDX                                                                   1
10740 #define regRLC_CLK_CNTL                                                                                 0x5b31
10741 #define regRLC_CLK_CNTL_BASE_IDX                                                                        1
10742 #define regRLC_PACE_TIMER_STAT                                                                          0x5b33
10743 #define regRLC_PACE_TIMER_STAT_BASE_IDX                                                                 1
10744 #define regRLC_GPU_IOV_SCH_BLOCK                                                                        0x5b34
10745 #define regRLC_GPU_IOV_SCH_BLOCK_BASE_IDX                                                               1
10746 #define regRLC_GPU_IOV_CFG_REG1                                                                         0x5b35
10747 #define regRLC_GPU_IOV_CFG_REG1_BASE_IDX                                                                1
10748 #define regRLC_GPU_IOV_CFG_REG2                                                                         0x5b36
10749 #define regRLC_GPU_IOV_CFG_REG2_BASE_IDX                                                                1
10750 #define regRLC_GPU_IOV_VM_BUSY_STATUS                                                                   0x5b37
10751 #define regRLC_GPU_IOV_VM_BUSY_STATUS_BASE_IDX                                                          1
10752 #define regRLC_GPU_IOV_SCH_0                                                                            0x5b38
10753 #define regRLC_GPU_IOV_SCH_0_BASE_IDX                                                                   1
10754 #define regRLC_GPU_IOV_SCH_3                                                                            0x5b3a
10755 #define regRLC_GPU_IOV_SCH_3_BASE_IDX                                                                   1
10756 #define regRLC_GPU_IOV_SCH_1                                                                            0x5b3b
10757 #define regRLC_GPU_IOV_SCH_1_BASE_IDX                                                                   1
10758 #define regRLC_GPU_IOV_SCH_2                                                                            0x5b3c
10759 #define regRLC_GPU_IOV_SCH_2_BASE_IDX                                                                   1
10760 #define regRLC_PACE_INT_FORCE                                                                           0x5b3d
10761 #define regRLC_PACE_INT_FORCE_BASE_IDX                                                                  1
10762 #define regRLC_PACE_INT_CLEAR                                                                           0x5b3e
10763 #define regRLC_PACE_INT_CLEAR_BASE_IDX                                                                  1
10764 #define regRLC_GPU_IOV_INT_STAT                                                                         0x5b3f
10765 #define regRLC_GPU_IOV_INT_STAT_BASE_IDX                                                                1
10766 #define regRLC_IH_COOKIE                                                                                0x5b41
10767 #define regRLC_IH_COOKIE_BASE_IDX                                                                       1
10768 #define regRLC_IH_COOKIE_CNTL                                                                           0x5b42
10769 #define regRLC_IH_COOKIE_CNTL_BASE_IDX                                                                  1
10770 #define regRLC_HYP_RLCG_UCODE_CHKSUM                                                                    0x5b43
10771 #define regRLC_HYP_RLCG_UCODE_CHKSUM_BASE_IDX                                                           1
10772 #define regRLC_HYP_RLCP_UCODE_CHKSUM                                                                    0x5b44
10773 #define regRLC_HYP_RLCP_UCODE_CHKSUM_BASE_IDX                                                           1
10774 #define regRLC_HYP_RLCV_UCODE_CHKSUM                                                                    0x5b45
10775 #define regRLC_HYP_RLCV_UCODE_CHKSUM_BASE_IDX                                                           1
10776 #define regRLC_GPU_IOV_F32_CNTL                                                                         0x5b46
10777 #define regRLC_GPU_IOV_F32_CNTL_BASE_IDX                                                                1
10778 #define regRLC_GPU_IOV_F32_RESET                                                                        0x5b47
10779 #define regRLC_GPU_IOV_F32_RESET_BASE_IDX                                                               1
10780 #define regRLC_GPU_IOV_UCODE_ADDR                                                                       0x5b48
10781 #define regRLC_GPU_IOV_UCODE_ADDR_BASE_IDX                                                              1
10782 #define regRLC_GPU_IOV_UCODE_DATA                                                                       0x5b49
10783 #define regRLC_GPU_IOV_UCODE_DATA_BASE_IDX                                                              1
10784 #define regRLC_GPU_IOV_SMU_RESPONSE                                                                     0x5b4a
10785 #define regRLC_GPU_IOV_SMU_RESPONSE_BASE_IDX                                                            1
10786 #define regRLC_GPU_IOV_F32_INVALIDATE_CACHE                                                             0x5b4b
10787 #define regRLC_GPU_IOV_F32_INVALIDATE_CACHE_BASE_IDX                                                    1
10788 #define regRLC_GPU_IOV_RLC_RESPONSE                                                                     0x5b4d
10789 #define regRLC_GPU_IOV_RLC_RESPONSE_BASE_IDX                                                            1
10790 #define regRLC_GPU_IOV_INT_DISABLE                                                                      0x5b4e
10791 #define regRLC_GPU_IOV_INT_DISABLE_BASE_IDX                                                             1
10792 #define regRLC_GPU_IOV_INT_FORCE                                                                        0x5b4f
10793 #define regRLC_GPU_IOV_INT_FORCE_BASE_IDX                                                               1
10794 #define regRLC_GPU_IOV_SCRATCH_ADDR                                                                     0x5b50
10795 #define regRLC_GPU_IOV_SCRATCH_ADDR_BASE_IDX                                                            1
10796 #define regRLC_GPU_IOV_SCRATCH_DATA                                                                     0x5b51
10797 #define regRLC_GPU_IOV_SCRATCH_DATA_BASE_IDX                                                            1
10798 #define regRLC_HYP_SEMAPHORE_2                                                                          0x5b52
10799 #define regRLC_HYP_SEMAPHORE_2_BASE_IDX                                                                 1
10800 #define regRLC_HYP_SEMAPHORE_3                                                                          0x5b53
10801 #define regRLC_HYP_SEMAPHORE_3_BASE_IDX                                                                 1
10802 #define regRLC_GPM_UCODE_ADDR                                                                           0x5b60
10803 #define regRLC_GPM_UCODE_ADDR_BASE_IDX                                                                  1
10804 #define regRLC_GPM_UCODE_DATA                                                                           0x5b61
10805 #define regRLC_GPM_UCODE_DATA_BASE_IDX                                                                  1
10806 #define regRLC_GPM_IRAM_ADDR                                                                            0x5b62
10807 #define regRLC_GPM_IRAM_ADDR_BASE_IDX                                                                   1
10808 #define regRLC_GPM_IRAM_DATA                                                                            0x5b63
10809 #define regRLC_GPM_IRAM_DATA_BASE_IDX                                                                   1
10810 #define regRLC_RLCP_IRAM_ADDR                                                                           0x5b64
10811 #define regRLC_RLCP_IRAM_ADDR_BASE_IDX                                                                  1
10812 #define regRLC_RLCP_IRAM_DATA                                                                           0x5b65
10813 #define regRLC_RLCP_IRAM_DATA_BASE_IDX                                                                  1
10814 #define regRLC_RLCV_IRAM_ADDR                                                                           0x5b66
10815 #define regRLC_RLCV_IRAM_ADDR_BASE_IDX                                                                  1
10816 #define regRLC_RLCV_IRAM_DATA                                                                           0x5b67
10817 #define regRLC_RLCV_IRAM_DATA_BASE_IDX                                                                  1
10818 #define regRLC_LX6_DRAM_ADDR                                                                            0x5b68
10819 #define regRLC_LX6_DRAM_ADDR_BASE_IDX                                                                   1
10820 #define regRLC_LX6_DRAM_DATA                                                                            0x5b69
10821 #define regRLC_LX6_DRAM_DATA_BASE_IDX                                                                   1
10822 #define regRLC_LX6_IRAM_ADDR                                                                            0x5b6a
10823 #define regRLC_LX6_IRAM_ADDR_BASE_IDX                                                                   1
10824 #define regRLC_LX6_IRAM_DATA                                                                            0x5b6b
10825 #define regRLC_LX6_IRAM_DATA_BASE_IDX                                                                   1
10826 #define regRLC_PACE_UCODE_ADDR                                                                          0x5b6c
10827 #define regRLC_PACE_UCODE_ADDR_BASE_IDX                                                                 1
10828 #define regRLC_PACE_UCODE_DATA                                                                          0x5b6d
10829 #define regRLC_PACE_UCODE_DATA_BASE_IDX                                                                 1
10830 #define regRLC_GPM_SCRATCH_ADDR                                                                         0x5b6e
10831 #define regRLC_GPM_SCRATCH_ADDR_BASE_IDX                                                                1
10832 #define regRLC_GPM_SCRATCH_DATA                                                                         0x5b6f
10833 #define regRLC_GPM_SCRATCH_DATA_BASE_IDX                                                                1
10834 #define regRLC_SRM_DRAM_ADDR                                                                            0x5b71
10835 #define regRLC_SRM_DRAM_ADDR_BASE_IDX                                                                   1
10836 #define regRLC_SRM_DRAM_DATA                                                                            0x5b72
10837 #define regRLC_SRM_DRAM_DATA_BASE_IDX                                                                   1
10838 #define regRLC_SRM_ARAM_ADDR                                                                            0x5b73
10839 #define regRLC_SRM_ARAM_ADDR_BASE_IDX                                                                   1
10840 #define regRLC_SRM_ARAM_DATA                                                                            0x5b74
10841 #define regRLC_SRM_ARAM_DATA_BASE_IDX                                                                   1
10842 #define regRLC_PACE_SCRATCH_ADDR                                                                        0x5b77
10843 #define regRLC_PACE_SCRATCH_ADDR_BASE_IDX                                                               1
10844 #define regRLC_PACE_SCRATCH_DATA                                                                        0x5b78
10845 #define regRLC_PACE_SCRATCH_DATA_BASE_IDX                                                               1
10846 #define regRLC_GTS_OFFSET_LSB                                                                           0x5b79
10847 #define regRLC_GTS_OFFSET_LSB_BASE_IDX                                                                  1
10848 #define regRLC_GTS_OFFSET_MSB                                                                           0x5b7a
10849 #define regRLC_GTS_OFFSET_MSB_BASE_IDX                                                                  1
10850 #define regGL2_PIPE_STEER_0                                                                             0x5b80
10851 #define regGL2_PIPE_STEER_0_BASE_IDX                                                                    1
10852 #define regGL2_PIPE_STEER_1                                                                             0x5b81
10853 #define regGL2_PIPE_STEER_1_BASE_IDX                                                                    1
10854 #define regGL2_PIPE_STEER_2                                                                             0x5b82
10855 #define regGL2_PIPE_STEER_2_BASE_IDX                                                                    1
10856 #define regGL2_PIPE_STEER_3                                                                             0x5b83
10857 #define regGL2_PIPE_STEER_3_BASE_IDX                                                                    1
10858 #define regGL1_PIPE_STEER                                                                               0x5b84
10859 #define regGL1_PIPE_STEER_BASE_IDX                                                                      1
10860 #define regCH_PIPE_STEER                                                                                0x5b88
10861 #define regCH_PIPE_STEER_BASE_IDX                                                                       1
10862 #define regGC_USER_SHADER_ARRAY_CONFIG                                                                  0x5b90
10863 #define regGC_USER_SHADER_ARRAY_CONFIG_BASE_IDX                                                         1
10864 #define regGC_USER_PRIM_CONFIG                                                                          0x5b91
10865 #define regGC_USER_PRIM_CONFIG_BASE_IDX                                                                 1
10866 #define regGC_USER_SA_UNIT_DISABLE                                                                      0x5b92
10867 #define regGC_USER_SA_UNIT_DISABLE_BASE_IDX                                                             1
10868 #define regGC_USER_RB_REDUNDANCY                                                                        0x5b93
10869 #define regGC_USER_RB_REDUNDANCY_BASE_IDX                                                               1
10870 #define regGC_USER_RB_BACKEND_DISABLE                                                                   0x5b94
10871 #define regGC_USER_RB_BACKEND_DISABLE_BASE_IDX                                                          1
10872 #define regGC_USER_RMI_REDUNDANCY                                                                       0x5b95
10873 #define regGC_USER_RMI_REDUNDANCY_BASE_IDX                                                              1
10874 #define regCGTS_USER_TCC_DISABLE                                                                        0x5b96
10875 #define regCGTS_USER_TCC_DISABLE_BASE_IDX                                                               1
10876 #define regGC_USER_SHADER_RATE_CONFIG                                                                   0x5b97
10877 #define regGC_USER_SHADER_RATE_CONFIG_BASE_IDX                                                          1
10878 #define regRLC_GPU_IOV_SDMA0_STATUS                                                                     0x5bc0
10879 #define regRLC_GPU_IOV_SDMA0_STATUS_BASE_IDX                                                            1
10880 #define regRLC_GPU_IOV_SDMA1_STATUS                                                                     0x5bc1
10881 #define regRLC_GPU_IOV_SDMA1_STATUS_BASE_IDX                                                            1
10882 #define regRLC_GPU_IOV_SDMA2_STATUS                                                                     0x5bc2
10883 #define regRLC_GPU_IOV_SDMA2_STATUS_BASE_IDX                                                            1
10884 #define regRLC_GPU_IOV_SDMA3_STATUS                                                                     0x5bc3
10885 #define regRLC_GPU_IOV_SDMA3_STATUS_BASE_IDX                                                            1
10886 #define regRLC_GPU_IOV_SDMA4_STATUS                                                                     0x5bc4
10887 #define regRLC_GPU_IOV_SDMA4_STATUS_BASE_IDX                                                            1
10888 #define regRLC_GPU_IOV_SDMA5_STATUS                                                                     0x5bc5
10889 #define regRLC_GPU_IOV_SDMA5_STATUS_BASE_IDX                                                            1
10890 #define regRLC_GPU_IOV_SDMA6_STATUS                                                                     0x5bc6
10891 #define regRLC_GPU_IOV_SDMA6_STATUS_BASE_IDX                                                            1
10892 #define regRLC_GPU_IOV_SDMA7_STATUS                                                                     0x5bc7
10893 #define regRLC_GPU_IOV_SDMA7_STATUS_BASE_IDX                                                            1
10894 #define regRLC_GPU_IOV_SDMA0_BUSY_STATUS                                                                0x5bc8
10895 #define regRLC_GPU_IOV_SDMA0_BUSY_STATUS_BASE_IDX                                                       1
10896 #define regRLC_GPU_IOV_SDMA1_BUSY_STATUS                                                                0x5bc9
10897 #define regRLC_GPU_IOV_SDMA1_BUSY_STATUS_BASE_IDX                                                       1
10898 #define regRLC_GPU_IOV_SDMA2_BUSY_STATUS                                                                0x5bca
10899 #define regRLC_GPU_IOV_SDMA2_BUSY_STATUS_BASE_IDX                                                       1
10900 #define regRLC_GPU_IOV_SDMA3_BUSY_STATUS                                                                0x5bcb
10901 #define regRLC_GPU_IOV_SDMA3_BUSY_STATUS_BASE_IDX                                                       1
10902 #define regRLC_GPU_IOV_SDMA4_BUSY_STATUS                                                                0x5bcc
10903 #define regRLC_GPU_IOV_SDMA4_BUSY_STATUS_BASE_IDX                                                       1
10904 #define regRLC_GPU_IOV_SDMA5_BUSY_STATUS                                                                0x5bcd
10905 #define regRLC_GPU_IOV_SDMA5_BUSY_STATUS_BASE_IDX                                                       1
10906 #define regRLC_GPU_IOV_SDMA6_BUSY_STATUS                                                                0x5bce
10907 #define regRLC_GPU_IOV_SDMA6_BUSY_STATUS_BASE_IDX                                                       1
10908 #define regRLC_GPU_IOV_SDMA7_BUSY_STATUS                                                                0x5bcf
10909 #define regRLC_GPU_IOV_SDMA7_BUSY_STATUS_BASE_IDX                                                       1
10910 
10911 
10912 // addressBlock: gc_pspdec
10913 // base address: 0x3f000
10914 #define regCP_MES_DM_INDEX_ADDR                                                                         0x5c00
10915 #define regCP_MES_DM_INDEX_ADDR_BASE_IDX                                                                1
10916 #define regCP_MES_DM_INDEX_DATA                                                                         0x5c01
10917 #define regCP_MES_DM_INDEX_DATA_BASE_IDX                                                                1
10918 #define regCP_MEC_DM_INDEX_ADDR                                                                         0x5c02
10919 #define regCP_MEC_DM_INDEX_ADDR_BASE_IDX                                                                1
10920 #define regCP_MEC_DM_INDEX_DATA                                                                         0x5c03
10921 #define regCP_MEC_DM_INDEX_DATA_BASE_IDX                                                                1
10922 #define regCP_GFX_RS64_DM_INDEX_ADDR                                                                    0x5c04
10923 #define regCP_GFX_RS64_DM_INDEX_ADDR_BASE_IDX                                                           1
10924 #define regCP_GFX_RS64_DM_INDEX_DATA                                                                    0x5c05
10925 #define regCP_GFX_RS64_DM_INDEX_DATA_BASE_IDX                                                           1
10926 #define regCPG_PSP_DEBUG                                                                                0x5c10
10927 #define regCPG_PSP_DEBUG_BASE_IDX                                                                       1
10928 #define regCPC_PSP_DEBUG                                                                                0x5c11
10929 #define regCPC_PSP_DEBUG_BASE_IDX                                                                       1
10930 #define regGRBM_SEC_CNTL                                                                                0x5e0d
10931 #define regGRBM_SEC_CNTL_BASE_IDX                                                                       1
10932 #define regGRBM_CAM_INDEX                                                                               0x5e10
10933 #define regGRBM_CAM_INDEX_BASE_IDX                                                                      1
10934 #define regGRBM_HYP_CAM_INDEX                                                                           0x5e10
10935 #define regGRBM_HYP_CAM_INDEX_BASE_IDX                                                                  1
10936 #define regGRBM_CAM_DATA                                                                                0x5e11
10937 #define regGRBM_CAM_DATA_BASE_IDX                                                                       1
10938 #define regGRBM_HYP_CAM_DATA                                                                            0x5e11
10939 #define regGRBM_HYP_CAM_DATA_BASE_IDX                                                                   1
10940 #define regGRBM_CAM_DATA_UPPER                                                                          0x5e12
10941 #define regGRBM_CAM_DATA_UPPER_BASE_IDX                                                                 1
10942 #define regGRBM_HYP_CAM_DATA_UPPER                                                                      0x5e12
10943 #define regGRBM_HYP_CAM_DATA_UPPER_BASE_IDX                                                             1
10944 #define regRLC_FWL_FIRST_VIOL_ADDR                                                                      0x5f26
10945 #define regRLC_FWL_FIRST_VIOL_ADDR_BASE_IDX                                                             1
10946 
10947 
10948 // addressBlock: gc_gfx_imu_gfx_imudec
10949 // base address: 0x38000
10950 #define regGFX_IMU_C2PMSG_0                                                                             0x4000
10951 #define regGFX_IMU_C2PMSG_0_BASE_IDX                                                                    1
10952 #define regGFX_IMU_C2PMSG_1                                                                             0x4001
10953 #define regGFX_IMU_C2PMSG_1_BASE_IDX                                                                    1
10954 #define regGFX_IMU_C2PMSG_2                                                                             0x4002
10955 #define regGFX_IMU_C2PMSG_2_BASE_IDX                                                                    1
10956 #define regGFX_IMU_C2PMSG_3                                                                             0x4003
10957 #define regGFX_IMU_C2PMSG_3_BASE_IDX                                                                    1
10958 #define regGFX_IMU_C2PMSG_4                                                                             0x4004
10959 #define regGFX_IMU_C2PMSG_4_BASE_IDX                                                                    1
10960 #define regGFX_IMU_C2PMSG_5                                                                             0x4005
10961 #define regGFX_IMU_C2PMSG_5_BASE_IDX                                                                    1
10962 #define regGFX_IMU_C2PMSG_6                                                                             0x4006
10963 #define regGFX_IMU_C2PMSG_6_BASE_IDX                                                                    1
10964 #define regGFX_IMU_C2PMSG_7                                                                             0x4007
10965 #define regGFX_IMU_C2PMSG_7_BASE_IDX                                                                    1
10966 #define regGFX_IMU_C2PMSG_8                                                                             0x4008
10967 #define regGFX_IMU_C2PMSG_8_BASE_IDX                                                                    1
10968 #define regGFX_IMU_C2PMSG_9                                                                             0x4009
10969 #define regGFX_IMU_C2PMSG_9_BASE_IDX                                                                    1
10970 #define regGFX_IMU_C2PMSG_10                                                                            0x400a
10971 #define regGFX_IMU_C2PMSG_10_BASE_IDX                                                                   1
10972 #define regGFX_IMU_C2PMSG_11                                                                            0x400b
10973 #define regGFX_IMU_C2PMSG_11_BASE_IDX                                                                   1
10974 #define regGFX_IMU_C2PMSG_12                                                                            0x400c
10975 #define regGFX_IMU_C2PMSG_12_BASE_IDX                                                                   1
10976 #define regGFX_IMU_C2PMSG_13                                                                            0x400d
10977 #define regGFX_IMU_C2PMSG_13_BASE_IDX                                                                   1
10978 #define regGFX_IMU_C2PMSG_14                                                                            0x400e
10979 #define regGFX_IMU_C2PMSG_14_BASE_IDX                                                                   1
10980 #define regGFX_IMU_C2PMSG_15                                                                            0x400f
10981 #define regGFX_IMU_C2PMSG_15_BASE_IDX                                                                   1
10982 #define regGFX_IMU_C2PMSG_16                                                                            0x4010
10983 #define regGFX_IMU_C2PMSG_16_BASE_IDX                                                                   1
10984 #define regGFX_IMU_C2PMSG_17                                                                            0x4011
10985 #define regGFX_IMU_C2PMSG_17_BASE_IDX                                                                   1
10986 #define regGFX_IMU_C2PMSG_18                                                                            0x4012
10987 #define regGFX_IMU_C2PMSG_18_BASE_IDX                                                                   1
10988 #define regGFX_IMU_C2PMSG_19                                                                            0x4013
10989 #define regGFX_IMU_C2PMSG_19_BASE_IDX                                                                   1
10990 #define regGFX_IMU_C2PMSG_20                                                                            0x4014
10991 #define regGFX_IMU_C2PMSG_20_BASE_IDX                                                                   1
10992 #define regGFX_IMU_C2PMSG_21                                                                            0x4015
10993 #define regGFX_IMU_C2PMSG_21_BASE_IDX                                                                   1
10994 #define regGFX_IMU_C2PMSG_22                                                                            0x4016
10995 #define regGFX_IMU_C2PMSG_22_BASE_IDX                                                                   1
10996 #define regGFX_IMU_C2PMSG_23                                                                            0x4017
10997 #define regGFX_IMU_C2PMSG_23_BASE_IDX                                                                   1
10998 #define regGFX_IMU_C2PMSG_24                                                                            0x4018
10999 #define regGFX_IMU_C2PMSG_24_BASE_IDX                                                                   1
11000 #define regGFX_IMU_C2PMSG_25                                                                            0x4019
11001 #define regGFX_IMU_C2PMSG_25_BASE_IDX                                                                   1
11002 #define regGFX_IMU_C2PMSG_26                                                                            0x401a
11003 #define regGFX_IMU_C2PMSG_26_BASE_IDX                                                                   1
11004 #define regGFX_IMU_C2PMSG_27                                                                            0x401b
11005 #define regGFX_IMU_C2PMSG_27_BASE_IDX                                                                   1
11006 #define regGFX_IMU_C2PMSG_28                                                                            0x401c
11007 #define regGFX_IMU_C2PMSG_28_BASE_IDX                                                                   1
11008 #define regGFX_IMU_C2PMSG_29                                                                            0x401d
11009 #define regGFX_IMU_C2PMSG_29_BASE_IDX                                                                   1
11010 #define regGFX_IMU_C2PMSG_30                                                                            0x401e
11011 #define regGFX_IMU_C2PMSG_30_BASE_IDX                                                                   1
11012 #define regGFX_IMU_C2PMSG_31                                                                            0x401f
11013 #define regGFX_IMU_C2PMSG_31_BASE_IDX                                                                   1
11014 #define regGFX_IMU_C2PMSG_32                                                                            0x4020
11015 #define regGFX_IMU_C2PMSG_32_BASE_IDX                                                                   1
11016 #define regGFX_IMU_C2PMSG_33                                                                            0x4021
11017 #define regGFX_IMU_C2PMSG_33_BASE_IDX                                                                   1
11018 #define regGFX_IMU_C2PMSG_34                                                                            0x4022
11019 #define regGFX_IMU_C2PMSG_34_BASE_IDX                                                                   1
11020 #define regGFX_IMU_C2PMSG_35                                                                            0x4023
11021 #define regGFX_IMU_C2PMSG_35_BASE_IDX                                                                   1
11022 #define regGFX_IMU_C2PMSG_36                                                                            0x4024
11023 #define regGFX_IMU_C2PMSG_36_BASE_IDX                                                                   1
11024 #define regGFX_IMU_C2PMSG_37                                                                            0x4025
11025 #define regGFX_IMU_C2PMSG_37_BASE_IDX                                                                   1
11026 #define regGFX_IMU_C2PMSG_38                                                                            0x4026
11027 #define regGFX_IMU_C2PMSG_38_BASE_IDX                                                                   1
11028 #define regGFX_IMU_C2PMSG_39                                                                            0x4027
11029 #define regGFX_IMU_C2PMSG_39_BASE_IDX                                                                   1
11030 #define regGFX_IMU_C2PMSG_40                                                                            0x4028
11031 #define regGFX_IMU_C2PMSG_40_BASE_IDX                                                                   1
11032 #define regGFX_IMU_C2PMSG_41                                                                            0x4029
11033 #define regGFX_IMU_C2PMSG_41_BASE_IDX                                                                   1
11034 #define regGFX_IMU_C2PMSG_42                                                                            0x402a
11035 #define regGFX_IMU_C2PMSG_42_BASE_IDX                                                                   1
11036 #define regGFX_IMU_C2PMSG_43                                                                            0x402b
11037 #define regGFX_IMU_C2PMSG_43_BASE_IDX                                                                   1
11038 #define regGFX_IMU_C2PMSG_44                                                                            0x402c
11039 #define regGFX_IMU_C2PMSG_44_BASE_IDX                                                                   1
11040 #define regGFX_IMU_C2PMSG_45                                                                            0x402d
11041 #define regGFX_IMU_C2PMSG_45_BASE_IDX                                                                   1
11042 #define regGFX_IMU_C2PMSG_46                                                                            0x402e
11043 #define regGFX_IMU_C2PMSG_46_BASE_IDX                                                                   1
11044 #define regGFX_IMU_C2PMSG_47                                                                            0x402f
11045 #define regGFX_IMU_C2PMSG_47_BASE_IDX                                                                   1
11046 #define regGFX_IMU_MSG_FLAGS                                                                            0x403f
11047 #define regGFX_IMU_MSG_FLAGS_BASE_IDX                                                                   1
11048 #define regGFX_IMU_C2PMSG_ACCESS_CTRL0                                                                  0x4040
11049 #define regGFX_IMU_C2PMSG_ACCESS_CTRL0_BASE_IDX                                                         1
11050 #define regGFX_IMU_C2PMSG_ACCESS_CTRL1                                                                  0x4041
11051 #define regGFX_IMU_C2PMSG_ACCESS_CTRL1_BASE_IDX                                                         1
11052 #define regGFX_IMU_PWRMGT_IRQ_CTRL                                                                      0x4042
11053 #define regGFX_IMU_PWRMGT_IRQ_CTRL_BASE_IDX                                                             1
11054 #define regGFX_IMU_MP1_MUTEX                                                                            0x4043
11055 #define regGFX_IMU_MP1_MUTEX_BASE_IDX                                                                   1
11056 #define regGFX_IMU_RLC_DATA_4                                                                           0x4046
11057 #define regGFX_IMU_RLC_DATA_4_BASE_IDX                                                                  1
11058 #define regGFX_IMU_RLC_DATA_3                                                                           0x4047
11059 #define regGFX_IMU_RLC_DATA_3_BASE_IDX                                                                  1
11060 #define regGFX_IMU_RLC_DATA_2                                                                           0x4048
11061 #define regGFX_IMU_RLC_DATA_2_BASE_IDX                                                                  1
11062 #define regGFX_IMU_RLC_DATA_1                                                                           0x4049
11063 #define regGFX_IMU_RLC_DATA_1_BASE_IDX                                                                  1
11064 #define regGFX_IMU_RLC_DATA_0                                                                           0x404a
11065 #define regGFX_IMU_RLC_DATA_0_BASE_IDX                                                                  1
11066 #define regGFX_IMU_RLC_CMD                                                                              0x404b
11067 #define regGFX_IMU_RLC_CMD_BASE_IDX                                                                     1
11068 #define regGFX_IMU_RLC_MUTEX                                                                            0x404c
11069 #define regGFX_IMU_RLC_MUTEX_BASE_IDX                                                                   1
11070 #define regGFX_IMU_RLC_MSG_STATUS                                                                       0x404f
11071 #define regGFX_IMU_RLC_MSG_STATUS_BASE_IDX                                                              1
11072 #define regRLC_GFX_IMU_DATA_0                                                                           0x4052
11073 #define regRLC_GFX_IMU_DATA_0_BASE_IDX                                                                  1
11074 #define regRLC_GFX_IMU_CMD                                                                              0x4053
11075 #define regRLC_GFX_IMU_CMD_BASE_IDX                                                                     1
11076 #define regGFX_IMU_RLC_STATUS                                                                           0x4054
11077 #define regGFX_IMU_RLC_STATUS_BASE_IDX                                                                  1
11078 #define regGFX_IMU_STATUS                                                                               0x4055
11079 #define regGFX_IMU_STATUS_BASE_IDX                                                                      1
11080 #define regGFX_IMU_SOC_DATA                                                                             0x4059
11081 #define regGFX_IMU_SOC_DATA_BASE_IDX                                                                    1
11082 #define regGFX_IMU_SOC_ADDR                                                                             0x405a
11083 #define regGFX_IMU_SOC_ADDR_BASE_IDX                                                                    1
11084 #define regGFX_IMU_SOC_REQ                                                                              0x405b
11085 #define regGFX_IMU_SOC_REQ_BASE_IDX                                                                     1
11086 #define regGFX_IMU_VF_CTRL                                                                              0x405c
11087 #define regGFX_IMU_VF_CTRL_BASE_IDX                                                                     1
11088 #define regGFX_IMU_TELEMETRY                                                                            0x4060
11089 #define regGFX_IMU_TELEMETRY_BASE_IDX                                                                   1
11090 #define regGFX_IMU_TELEMETRY_DATA                                                                       0x4061
11091 #define regGFX_IMU_TELEMETRY_DATA_BASE_IDX                                                              1
11092 #define regGFX_IMU_TELEMETRY_TEMPERATURE                                                                0x4062
11093 #define regGFX_IMU_TELEMETRY_TEMPERATURE_BASE_IDX                                                       1
11094 #define regGFX_IMU_SCRATCH_0                                                                            0x4068
11095 #define regGFX_IMU_SCRATCH_0_BASE_IDX                                                                   1
11096 #define regGFX_IMU_SCRATCH_1                                                                            0x4069
11097 #define regGFX_IMU_SCRATCH_1_BASE_IDX                                                                   1
11098 #define regGFX_IMU_SCRATCH_2                                                                            0x406a
11099 #define regGFX_IMU_SCRATCH_2_BASE_IDX                                                                   1
11100 #define regGFX_IMU_SCRATCH_3                                                                            0x406b
11101 #define regGFX_IMU_SCRATCH_3_BASE_IDX                                                                   1
11102 #define regGFX_IMU_SCRATCH_4                                                                            0x406c
11103 #define regGFX_IMU_SCRATCH_4_BASE_IDX                                                                   1
11104 #define regGFX_IMU_SCRATCH_5                                                                            0x406d
11105 #define regGFX_IMU_SCRATCH_5_BASE_IDX                                                                   1
11106 #define regGFX_IMU_SCRATCH_6                                                                            0x406e
11107 #define regGFX_IMU_SCRATCH_6_BASE_IDX                                                                   1
11108 #define regGFX_IMU_SCRATCH_7                                                                            0x406f
11109 #define regGFX_IMU_SCRATCH_7_BASE_IDX                                                                   1
11110 #define regGFX_IMU_SCRATCH_8                                                                            0x4070
11111 #define regGFX_IMU_SCRATCH_8_BASE_IDX                                                                   1
11112 #define regGFX_IMU_SCRATCH_9                                                                            0x4071
11113 #define regGFX_IMU_SCRATCH_9_BASE_IDX                                                                   1
11114 #define regGFX_IMU_SCRATCH_10                                                                           0x4072
11115 #define regGFX_IMU_SCRATCH_10_BASE_IDX                                                                  1
11116 #define regGFX_IMU_SCRATCH_11                                                                           0x4073
11117 #define regGFX_IMU_SCRATCH_11_BASE_IDX                                                                  1
11118 #define regGFX_IMU_SCRATCH_12                                                                           0x4074
11119 #define regGFX_IMU_SCRATCH_12_BASE_IDX                                                                  1
11120 #define regGFX_IMU_SCRATCH_13                                                                           0x4075
11121 #define regGFX_IMU_SCRATCH_13_BASE_IDX                                                                  1
11122 #define regGFX_IMU_SCRATCH_14                                                                           0x4076
11123 #define regGFX_IMU_SCRATCH_14_BASE_IDX                                                                  1
11124 #define regGFX_IMU_SCRATCH_15                                                                           0x4077
11125 #define regGFX_IMU_SCRATCH_15_BASE_IDX                                                                  1
11126 #define regGFX_IMU_FW_GTS_LO                                                                            0x4078
11127 #define regGFX_IMU_FW_GTS_LO_BASE_IDX                                                                   1
11128 #define regGFX_IMU_FW_GTS_HI                                                                            0x4079
11129 #define regGFX_IMU_FW_GTS_HI_BASE_IDX                                                                   1
11130 #define regGFX_IMU_GTS_OFFSET_LO                                                                        0x407a
11131 #define regGFX_IMU_GTS_OFFSET_LO_BASE_IDX                                                               1
11132 #define regGFX_IMU_GTS_OFFSET_HI                                                                        0x407b
11133 #define regGFX_IMU_GTS_OFFSET_HI_BASE_IDX                                                               1
11134 #define regGFX_IMU_RLC_GTS_OFFSET_LO                                                                    0x407c
11135 #define regGFX_IMU_RLC_GTS_OFFSET_LO_BASE_IDX                                                           1
11136 #define regGFX_IMU_RLC_GTS_OFFSET_HI                                                                    0x407d
11137 #define regGFX_IMU_RLC_GTS_OFFSET_HI_BASE_IDX                                                           1
11138 #define regGFX_IMU_CORE_INT_STATUS                                                                      0x407f
11139 #define regGFX_IMU_CORE_INT_STATUS_BASE_IDX                                                             1
11140 #define regGFX_IMU_PIC_INT_MASK                                                                         0x4080
11141 #define regGFX_IMU_PIC_INT_MASK_BASE_IDX                                                                1
11142 #define regGFX_IMU_PIC_INT_LVL                                                                          0x4081
11143 #define regGFX_IMU_PIC_INT_LVL_BASE_IDX                                                                 1
11144 #define regGFX_IMU_PIC_INT_EDGE                                                                         0x4082
11145 #define regGFX_IMU_PIC_INT_EDGE_BASE_IDX                                                                1
11146 #define regGFX_IMU_PIC_INT_PRI_0                                                                        0x4083
11147 #define regGFX_IMU_PIC_INT_PRI_0_BASE_IDX                                                               1
11148 #define regGFX_IMU_PIC_INT_PRI_1                                                                        0x4084
11149 #define regGFX_IMU_PIC_INT_PRI_1_BASE_IDX                                                               1
11150 #define regGFX_IMU_PIC_INT_PRI_2                                                                        0x4085
11151 #define regGFX_IMU_PIC_INT_PRI_2_BASE_IDX                                                               1
11152 #define regGFX_IMU_PIC_INT_PRI_3                                                                        0x4086
11153 #define regGFX_IMU_PIC_INT_PRI_3_BASE_IDX                                                               1
11154 #define regGFX_IMU_PIC_INT_PRI_4                                                                        0x4087
11155 #define regGFX_IMU_PIC_INT_PRI_4_BASE_IDX                                                               1
11156 #define regGFX_IMU_PIC_INT_PRI_5                                                                        0x4088
11157 #define regGFX_IMU_PIC_INT_PRI_5_BASE_IDX                                                               1
11158 #define regGFX_IMU_PIC_INT_PRI_6                                                                        0x4089
11159 #define regGFX_IMU_PIC_INT_PRI_6_BASE_IDX                                                               1
11160 #define regGFX_IMU_PIC_INT_PRI_7                                                                        0x408a
11161 #define regGFX_IMU_PIC_INT_PRI_7_BASE_IDX                                                               1
11162 #define regGFX_IMU_PIC_INT_STATUS                                                                       0x408b
11163 #define regGFX_IMU_PIC_INT_STATUS_BASE_IDX                                                              1
11164 #define regGFX_IMU_PIC_INTR                                                                             0x408c
11165 #define regGFX_IMU_PIC_INTR_BASE_IDX                                                                    1
11166 #define regGFX_IMU_PIC_INTR_ID                                                                          0x408d
11167 #define regGFX_IMU_PIC_INTR_ID_BASE_IDX                                                                 1
11168 #define regGFX_IMU_IH_CTRL_1                                                                            0x4090
11169 #define regGFX_IMU_IH_CTRL_1_BASE_IDX                                                                   1
11170 #define regGFX_IMU_IH_CTRL_2                                                                            0x4091
11171 #define regGFX_IMU_IH_CTRL_2_BASE_IDX                                                                   1
11172 #define regGFX_IMU_IH_CTRL_3                                                                            0x4092
11173 #define regGFX_IMU_IH_CTRL_3_BASE_IDX                                                                   1
11174 #define regGFX_IMU_IH_STATUS                                                                            0x4093
11175 #define regGFX_IMU_IH_STATUS_BASE_IDX                                                                   1
11176 #define regGFX_IMU_FUSESTRAP                                                                            0x4094
11177 #define regGFX_IMU_SMUIO_VIDCHG_CTRL                                                                    0x4098
11178 #define regGFX_IMU_SMUIO_VIDCHG_CTRL_BASE_IDX                                                           1
11179 #define regGFX_IMU_GFXCLK_BYPASS_CTRL                                                                   0x409c
11180 #define regGFX_IMU_GFXCLK_BYPASS_CTRL_BASE_IDX                                                          1
11181 #define regGFX_IMU_CLK_CTRL                                                                             0x409d
11182 #define regGFX_IMU_CLK_CTRL_BASE_IDX                                                                    1
11183 #define regGFX_IMU_DOORBELL_CONTROL                                                                     0x409e
11184 #define regGFX_IMU_DOORBELL_CONTROL_BASE_IDX                                                            1
11185 #define regGFX_IMU_RLC_CG_CTRL                                                                          0x40a0
11186 #define regGFX_IMU_RLC_CG_CTRL_BASE_IDX                                                                 1
11187 #define regGFX_IMU_RLC_THROTTLE_GFX                                                                     0x40a1
11188 #define regGFX_IMU_RLC_THROTTLE_GFX_BASE_IDX                                                            1
11189 #define regGFX_IMU_RLC_RESET_VECTOR                                                                     0x40a2
11190 #define regGFX_IMU_RLC_RESET_VECTOR_BASE_IDX                                                            1
11191 #define regGFX_IMU_RLC_OVERRIDE                                                                         0x40a3
11192 #define regGFX_IMU_RLC_OVERRIDE_BASE_IDX                                                                1
11193 #define regGFX_IMU_DPM_CONTROL                                                                          0x40a8
11194 #define regGFX_IMU_DPM_CONTROL_BASE_IDX                                                                 1
11195 #define regGFX_IMU_DPM_ACC                                                                              0x40a9
11196 #define regGFX_IMU_DPM_ACC_BASE_IDX                                                                     1
11197 #define regGFX_IMU_DPM_REF_COUNTER                                                                      0x40aa
11198 #define regGFX_IMU_DPM_REF_COUNTER_BASE_IDX                                                             1
11199 #define regGFX_IMU_RLC_RAM_INDEX                                                                        0x40ac
11200 #define regGFX_IMU_RLC_RAM_INDEX_BASE_IDX                                                               1
11201 #define regGFX_IMU_RLC_RAM_ADDR_HIGH                                                                    0x40ad
11202 #define regGFX_IMU_RLC_RAM_ADDR_HIGH_BASE_IDX                                                           1
11203 #define regGFX_IMU_RLC_RAM_ADDR_LOW                                                                     0x40ae
11204 #define regGFX_IMU_RLC_RAM_ADDR_LOW_BASE_IDX                                                            1
11205 #define regGFX_IMU_RLC_RAM_DATA                                                                         0x40af
11206 #define regGFX_IMU_RLC_RAM_DATA_BASE_IDX                                                                1
11207 #define regGFX_IMU_FENCE_CTRL                                                                           0x40b0
11208 #define regGFX_IMU_FENCE_CTRL_BASE_IDX                                                                  1
11209 #define regGFX_IMU_FENCE_LOG_INIT                                                                       0x40b1
11210 #define regGFX_IMU_FENCE_LOG_INIT_BASE_IDX                                                              1
11211 #define regGFX_IMU_FENCE_LOG_ADDR                                                                       0x40b2
11212 #define regGFX_IMU_FENCE_LOG_ADDR_BASE_IDX                                                              1
11213 #define regGFX_IMU_PROGRAM_CTR                                                                          0x40b5
11214 #define regGFX_IMU_PROGRAM_CTR_BASE_IDX                                                                 1
11215 #define regGFX_IMU_CORE_CTRL                                                                            0x40b6
11216 #define regGFX_IMU_CORE_CTRL_BASE_IDX                                                                   1
11217 #define regGFX_IMU_CORE_STATUS                                                                          0x40b7
11218 #define regGFX_IMU_CORE_STATUS_BASE_IDX                                                                 1
11219 #define regGFX_IMU_PWROKRAW                                                                             0x40b8
11220 #define regGFX_IMU_PWROKRAW_BASE_IDX                                                                    1
11221 #define regGFX_IMU_PWROK                                                                                0x40b9
11222 #define regGFX_IMU_PWROK_BASE_IDX                                                                       1
11223 #define regGFX_IMU_GAP_PWROK                                                                            0x40ba
11224 #define regGFX_IMU_GAP_PWROK_BASE_IDX                                                                   1
11225 #define regGFX_IMU_RESETn                                                                               0x40bb
11226 #define regGFX_IMU_RESETn_BASE_IDX                                                                      1
11227 #define regGFX_IMU_GFX_RESET_CTRL                                                                       0x40bc
11228 #define regGFX_IMU_GFX_RESET_CTRL_BASE_IDX                                                              1
11229 #define regGFX_IMU_AEB_OVERRIDE                                                                         0x40bd
11230 #define regGFX_IMU_AEB_OVERRIDE_BASE_IDX                                                                1
11231 #define regGFX_IMU_VDCI_RESET_CTRL                                                                      0x40be
11232 #define regGFX_IMU_VDCI_RESET_CTRL_BASE_IDX                                                             1
11233 #define regGFX_IMU_GFX_ISO_CTRL                                                                         0x40bf
11234 #define regGFX_IMU_GFX_ISO_CTRL_BASE_IDX                                                                1
11235 #define regGFX_IMU_TIMER0_CTRL0                                                                         0x40c0
11236 #define regGFX_IMU_TIMER0_CTRL0_BASE_IDX                                                                1
11237 #define regGFX_IMU_TIMER0_CTRL1                                                                         0x40c1
11238 #define regGFX_IMU_TIMER0_CTRL1_BASE_IDX                                                                1
11239 #define regGFX_IMU_TIMER0_CMP_AUTOINC                                                                   0x40c2
11240 #define regGFX_IMU_TIMER0_CMP_AUTOINC_BASE_IDX                                                          1
11241 #define regGFX_IMU_TIMER0_CMP_INTEN                                                                     0x40c3
11242 #define regGFX_IMU_TIMER0_CMP_INTEN_BASE_IDX                                                            1
11243 #define regGFX_IMU_TIMER0_CMP0                                                                          0x40c4
11244 #define regGFX_IMU_TIMER0_CMP0_BASE_IDX                                                                 1
11245 #define regGFX_IMU_TIMER0_CMP1                                                                          0x40c5
11246 #define regGFX_IMU_TIMER0_CMP1_BASE_IDX                                                                 1
11247 #define regGFX_IMU_TIMER0_CMP3                                                                          0x40c7
11248 #define regGFX_IMU_TIMER0_CMP3_BASE_IDX                                                                 1
11249 #define regGFX_IMU_TIMER0_VALUE                                                                         0x40c8
11250 #define regGFX_IMU_TIMER0_VALUE_BASE_IDX                                                                1
11251 #define regGFX_IMU_TIMER1_CTRL0                                                                         0x40c9
11252 #define regGFX_IMU_TIMER1_CTRL0_BASE_IDX                                                                1
11253 #define regGFX_IMU_TIMER1_CTRL1                                                                         0x40ca
11254 #define regGFX_IMU_TIMER1_CTRL1_BASE_IDX                                                                1
11255 #define regGFX_IMU_TIMER1_CMP_AUTOINC                                                                   0x40cb
11256 #define regGFX_IMU_TIMER1_CMP_AUTOINC_BASE_IDX                                                          1
11257 #define regGFX_IMU_TIMER1_CMP_INTEN                                                                     0x40cc
11258 #define regGFX_IMU_TIMER1_CMP_INTEN_BASE_IDX                                                            1
11259 #define regGFX_IMU_TIMER1_CMP0                                                                          0x40cd
11260 #define regGFX_IMU_TIMER1_CMP0_BASE_IDX                                                                 1
11261 #define regGFX_IMU_TIMER1_CMP1                                                                          0x40ce
11262 #define regGFX_IMU_TIMER1_CMP1_BASE_IDX                                                                 1
11263 #define regGFX_IMU_TIMER1_CMP3                                                                          0x40d0
11264 #define regGFX_IMU_TIMER1_CMP3_BASE_IDX                                                                 1
11265 #define regGFX_IMU_TIMER1_VALUE                                                                         0x40d1
11266 #define regGFX_IMU_TIMER1_VALUE_BASE_IDX                                                                1
11267 #define regGFX_IMU_TIMER2_CTRL0                                                                         0x40d2
11268 #define regGFX_IMU_TIMER2_CTRL0_BASE_IDX                                                                1
11269 #define regGFX_IMU_TIMER2_CTRL1                                                                         0x40d3
11270 #define regGFX_IMU_TIMER2_CTRL1_BASE_IDX                                                                1
11271 #define regGFX_IMU_TIMER2_CMP_AUTOINC                                                                   0x40d4
11272 #define regGFX_IMU_TIMER2_CMP_AUTOINC_BASE_IDX                                                          1
11273 #define regGFX_IMU_TIMER2_CMP_INTEN                                                                     0x40d5
11274 #define regGFX_IMU_TIMER2_CMP_INTEN_BASE_IDX                                                            1
11275 #define regGFX_IMU_TIMER2_CMP0                                                                          0x40d6
11276 #define regGFX_IMU_TIMER2_CMP0_BASE_IDX                                                                 1
11277 #define regGFX_IMU_TIMER2_CMP1                                                                          0x40d7
11278 #define regGFX_IMU_TIMER2_CMP1_BASE_IDX                                                                 1
11279 #define regGFX_IMU_TIMER2_CMP3                                                                          0x40d9
11280 #define regGFX_IMU_TIMER2_CMP3_BASE_IDX                                                                 1
11281 #define regGFX_IMU_TIMER2_VALUE                                                                         0x40da
11282 #define regGFX_IMU_TIMER2_VALUE_BASE_IDX                                                                1
11283 #define regGFX_IMU_FUSE_CTRL                                                                            0x40e0
11284 #define regGFX_IMU_FUSE_CTRL_BASE_IDX                                                                   1
11285 #define regGFX_IMU_D_RAM_ADDR                                                                           0x40fc
11286 #define regGFX_IMU_D_RAM_ADDR_BASE_IDX                                                                  1
11287 #define regGFX_IMU_D_RAM_DATA                                                                           0x40fd
11288 #define regGFX_IMU_D_RAM_DATA_BASE_IDX                                                                  1
11289 #define regGFX_IMU_GFX_IH_GASKET_CTRL                                                                   0x40ff
11290 #define regGFX_IMU_GFX_IH_GASKET_CTRL_BASE_IDX                                                          1
11291 
11292 
11293 // addressBlock: gc_gfx_imu_gfx_imu_pspdec
11294 // base address: 0x3fe00
11295 #define regGFX_IMU_RLC_BOOTLOADER_ADDR_HI                                                               0x5f81
11296 #define regGFX_IMU_RLC_BOOTLOADER_ADDR_HI_BASE_IDX                                                      1
11297 #define regGFX_IMU_RLC_BOOTLOADER_ADDR_LO                                                               0x5f82
11298 #define regGFX_IMU_RLC_BOOTLOADER_ADDR_LO_BASE_IDX                                                      1
11299 #define regGFX_IMU_RLC_BOOTLOADER_SIZE                                                                  0x5f83
11300 #define regGFX_IMU_RLC_BOOTLOADER_SIZE_BASE_IDX                                                         1
11301 #define regGFX_IMU_I_RAM_ADDR                                                                           0x5f90
11302 #define regGFX_IMU_I_RAM_ADDR_BASE_IDX                                                                  1
11303 #define regGFX_IMU_I_RAM_DATA                                                                           0x5f91
11304 #define regGFX_IMU_I_RAM_DATA_BASE_IDX                                                                  1
11305 
11306 
11307 // addressBlock: gccacind
11308 // base address: 0x0
11309 #define ixGC_CAC_ID                                                                                    0x0000
11310 #define ixGC_CAC_CNTL                                                                                  0x0001
11311 #define ixGC_CAC_ACC_CP0                                                                               0x0010
11312 #define ixGC_CAC_ACC_CP1                                                                               0x0011
11313 #define ixGC_CAC_ACC_CP2                                                                               0x0012
11314 #define ixGC_CAC_ACC_EA0                                                                               0x0013
11315 #define ixGC_CAC_ACC_EA1                                                                               0x0014
11316 #define ixGC_CAC_ACC_EA2                                                                               0x0015
11317 #define ixGC_CAC_ACC_EA3                                                                               0x0016
11318 #define ixGC_CAC_ACC_EA4                                                                               0x0017
11319 #define ixGC_CAC_ACC_EA5                                                                               0x0018
11320 #define ixGC_CAC_ACC_UTCL2_ROUTER0                                                                     0x0019
11321 #define ixGC_CAC_ACC_UTCL2_ROUTER1                                                                     0x001a
11322 #define ixGC_CAC_ACC_UTCL2_ROUTER2                                                                     0x001b
11323 #define ixGC_CAC_ACC_UTCL2_ROUTER3                                                                     0x001c
11324 #define ixGC_CAC_ACC_UTCL2_ROUTER4                                                                     0x001d
11325 #define ixGC_CAC_ACC_UTCL2_ROUTER5                                                                     0x001e
11326 #define ixGC_CAC_ACC_UTCL2_ROUTER6                                                                     0x001f
11327 #define ixGC_CAC_ACC_UTCL2_ROUTER7                                                                     0x0020
11328 #define ixGC_CAC_ACC_UTCL2_ROUTER8                                                                     0x0021
11329 #define ixGC_CAC_ACC_UTCL2_ROUTER9                                                                     0x0022
11330 #define ixGC_CAC_ACC_UTCL2_VML20                                                                       0x0023
11331 #define ixGC_CAC_ACC_UTCL2_VML21                                                                       0x0024
11332 #define ixGC_CAC_ACC_UTCL2_VML22                                                                       0x0025
11333 #define ixGC_CAC_ACC_UTCL2_VML23                                                                       0x0026
11334 #define ixGC_CAC_ACC_UTCL2_VML24                                                                       0x0027
11335 #define ixGC_CAC_ACC_UTCL2_WALKER0                                                                     0x0028
11336 #define ixGC_CAC_ACC_UTCL2_WALKER1                                                                     0x0029
11337 #define ixGC_CAC_ACC_UTCL2_WALKER2                                                                     0x002a
11338 #define ixGC_CAC_ACC_UTCL2_WALKER3                                                                     0x002b
11339 #define ixGC_CAC_ACC_UTCL2_WALKER4                                                                     0x002c
11340 #define ixGC_CAC_ACC_GDS0                                                                              0x002d
11341 #define ixGC_CAC_ACC_GDS1                                                                              0x002e
11342 #define ixGC_CAC_ACC_GDS2                                                                              0x002f
11343 #define ixGC_CAC_ACC_GDS3                                                                              0x0030
11344 #define ixGC_CAC_ACC_GDS4                                                                              0x0031
11345 #define ixGC_CAC_ACC_GE0                                                                               0x0032
11346 #define ixGC_CAC_ACC_GE1                                                                               0x0033
11347 #define ixGC_CAC_ACC_GE2                                                                               0x0034
11348 #define ixGC_CAC_ACC_GE3                                                                               0x0035
11349 #define ixGC_CAC_ACC_GE4                                                                               0x0036
11350 #define ixGC_CAC_ACC_GE5                                                                               0x0037
11351 #define ixGC_CAC_ACC_GE6                                                                               0x0038
11352 #define ixGC_CAC_ACC_GE7                                                                               0x0039
11353 #define ixGC_CAC_ACC_GE8                                                                               0x003a
11354 #define ixGC_CAC_ACC_GE9                                                                               0x003b
11355 #define ixGC_CAC_ACC_GE10                                                                              0x003c
11356 #define ixGC_CAC_ACC_GE11                                                                              0x003d
11357 #define ixGC_CAC_ACC_GE12                                                                              0x003e
11358 #define ixGC_CAC_ACC_GE13                                                                              0x003f
11359 #define ixGC_CAC_ACC_GE14                                                                              0x0040
11360 #define ixGC_CAC_ACC_GE15                                                                              0x0041
11361 #define ixGC_CAC_ACC_GE16                                                                              0x0042
11362 #define ixGC_CAC_ACC_GE17                                                                              0x0043
11363 #define ixGC_CAC_ACC_GE18                                                                              0x0044
11364 #define ixGC_CAC_ACC_GE19                                                                              0x0045
11365 #define ixGC_CAC_ACC_GE20                                                                              0x0046
11366 #define ixGC_CAC_ACC_PMM0                                                                              0x0047
11367 #define ixGC_CAC_ACC_GL2C0                                                                             0x0048
11368 #define ixGC_CAC_ACC_GL2C1                                                                             0x0049
11369 #define ixGC_CAC_ACC_GL2C2                                                                             0x004a
11370 #define ixGC_CAC_ACC_GL2C3                                                                             0x004b
11371 #define ixGC_CAC_ACC_GL2C4                                                                             0x004c
11372 #define ixGC_CAC_ACC_PH0                                                                               0x004d
11373 #define ixGC_CAC_ACC_PH1                                                                               0x004e
11374 #define ixGC_CAC_ACC_PH2                                                                               0x004f
11375 #define ixGC_CAC_ACC_PH3                                                                               0x0050
11376 #define ixGC_CAC_ACC_PH4                                                                               0x0051
11377 #define ixGC_CAC_ACC_PH5                                                                               0x0052
11378 #define ixGC_CAC_ACC_PH6                                                                               0x0053
11379 #define ixGC_CAC_ACC_PH7                                                                               0x0054
11380 #define ixGC_CAC_ACC_SDMA0                                                                             0x0055
11381 #define ixGC_CAC_ACC_SDMA1                                                                             0x0056
11382 #define ixGC_CAC_ACC_SDMA2                                                                             0x0057
11383 #define ixGC_CAC_ACC_SDMA3                                                                             0x0058
11384 #define ixGC_CAC_ACC_SDMA4                                                                             0x0059
11385 #define ixGC_CAC_ACC_SDMA5                                                                             0x005a
11386 #define ixGC_CAC_ACC_SDMA6                                                                             0x005b
11387 #define ixGC_CAC_ACC_SDMA7                                                                             0x005c
11388 #define ixGC_CAC_ACC_SDMA8                                                                             0x005d
11389 #define ixGC_CAC_ACC_SDMA9                                                                             0x005e
11390 #define ixGC_CAC_ACC_SDMA10                                                                            0x005f
11391 #define ixGC_CAC_ACC_SDMA11                                                                            0x0060
11392 #define ixGC_CAC_ACC_CHC0                                                                              0x0061
11393 #define ixGC_CAC_ACC_CHC1                                                                              0x0062
11394 #define ixGC_CAC_ACC_CHC2                                                                              0x0063
11395 #define ixGC_CAC_ACC_GUS0                                                                              0x0064
11396 #define ixGC_CAC_ACC_GUS1                                                                              0x0065
11397 #define ixGC_CAC_ACC_GUS2                                                                              0x0066
11398 #define ixGC_CAC_ACC_RLC0                                                                              0x0067
11399 #define ixRELEASE_TO_STALL_LUT_1_8                                                                     0x0100
11400 #define ixRELEASE_TO_STALL_LUT_9_16                                                                    0x0101
11401 #define ixRELEASE_TO_STALL_LUT_17_20                                                                   0x0102
11402 #define ixSTALL_TO_RELEASE_LUT_1_4                                                                     0x0103
11403 #define ixSTALL_TO_RELEASE_LUT_5_7                                                                     0x0104
11404 #define ixSTALL_TO_PWRBRK_LUT_1_4                                                                      0x0105
11405 #define ixSTALL_TO_PWRBRK_LUT_5_7                                                                      0x0106
11406 #define ixPWRBRK_STALL_TO_RELEASE_LUT_1_4                                                              0x0107
11407 #define ixPWRBRK_STALL_TO_RELEASE_LUT_5_7                                                              0x0108
11408 #define ixPWRBRK_RELEASE_TO_STALL_LUT_1_8                                                              0x0109
11409 #define ixPWRBRK_RELEASE_TO_STALL_LUT_9_16                                                             0x010a
11410 #define ixPWRBRK_RELEASE_TO_STALL_LUT_17_20                                                            0x010b
11411 #define ixFIXED_PATTERN_PERF_COUNTER_1                                                                 0x010c
11412 #define ixFIXED_PATTERN_PERF_COUNTER_2                                                                 0x010d
11413 #define ixFIXED_PATTERN_PERF_COUNTER_3                                                                 0x010e
11414 #define ixFIXED_PATTERN_PERF_COUNTER_4                                                                 0x010f
11415 #define ixFIXED_PATTERN_PERF_COUNTER_5                                                                 0x0110
11416 #define ixFIXED_PATTERN_PERF_COUNTER_6                                                                 0x0111
11417 #define ixFIXED_PATTERN_PERF_COUNTER_7                                                                 0x0112
11418 #define ixFIXED_PATTERN_PERF_COUNTER_8                                                                 0x0113
11419 #define ixFIXED_PATTERN_PERF_COUNTER_9                                                                 0x0114
11420 #define ixFIXED_PATTERN_PERF_COUNTER_10                                                                0x0115
11421 #define ixHW_LUT_UPDATE_STATUS                                                                         0x0116
11422 
11423 
11424 // addressBlock: secacind
11425 // base address: 0x0
11426 #define ixSE_CAC_ID                                                                                    0x0000
11427 #define ixSE_CAC_CNTL                                                                                  0x0001
11428 
11429 
11430 // addressBlock: grtavfsind
11431 // base address: 0x0
11432 #define ixRTAVFS_REG0                                                                                  0x0000
11433 #define ixRTAVFS_REG1                                                                                  0x0001
11434 #define ixRTAVFS_REG2                                                                                  0x0002
11435 #define ixRTAVFS_REG3                                                                                  0x0003
11436 #define ixRTAVFS_REG4                                                                                  0x0004
11437 #define ixRTAVFS_REG5                                                                                  0x0005
11438 #define ixRTAVFS_REG6                                                                                  0x0006
11439 #define ixRTAVFS_REG7                                                                                  0x0007
11440 #define ixRTAVFS_REG8                                                                                  0x0008
11441 #define ixRTAVFS_REG9                                                                                  0x0009
11442 #define ixRTAVFS_REG10                                                                                 0x000a
11443 #define ixRTAVFS_REG11                                                                                 0x000b
11444 #define ixRTAVFS_REG12                                                                                 0x000c
11445 #define ixRTAVFS_REG13                                                                                 0x000d
11446 #define ixRTAVFS_REG14                                                                                 0x000e
11447 #define ixRTAVFS_REG15                                                                                 0x000f
11448 #define ixRTAVFS_REG16                                                                                 0x0010
11449 #define ixRTAVFS_REG17                                                                                 0x0011
11450 #define ixRTAVFS_REG18                                                                                 0x0012
11451 #define ixRTAVFS_REG19                                                                                 0x0013
11452 #define ixRTAVFS_REG20                                                                                 0x0014
11453 #define ixRTAVFS_REG21                                                                                 0x0015
11454 #define ixRTAVFS_REG22                                                                                 0x0016
11455 #define ixRTAVFS_REG23                                                                                 0x0017
11456 #define ixRTAVFS_REG24                                                                                 0x0018
11457 #define ixRTAVFS_REG25                                                                                 0x0019
11458 #define ixRTAVFS_REG26                                                                                 0x001a
11459 #define ixRTAVFS_REG27                                                                                 0x001b
11460 #define ixRTAVFS_REG28                                                                                 0x001c
11461 #define ixRTAVFS_REG29                                                                                 0x001d
11462 #define ixRTAVFS_REG30                                                                                 0x001e
11463 #define ixRTAVFS_REG31                                                                                 0x001f
11464 #define ixRTAVFS_REG32                                                                                 0x0020
11465 #define ixRTAVFS_REG33                                                                                 0x0021
11466 #define ixRTAVFS_REG34                                                                                 0x0022
11467 #define ixRTAVFS_REG35                                                                                 0x0023
11468 #define ixRTAVFS_REG36                                                                                 0x0024
11469 #define ixRTAVFS_REG37                                                                                 0x0025
11470 #define ixRTAVFS_REG38                                                                                 0x0026
11471 #define ixRTAVFS_REG39                                                                                 0x0027
11472 #define ixRTAVFS_REG40                                                                                 0x0028
11473 #define ixRTAVFS_REG41                                                                                 0x0029
11474 #define ixRTAVFS_REG42                                                                                 0x002a
11475 #define ixRTAVFS_REG43                                                                                 0x002b
11476 #define ixRTAVFS_REG44                                                                                 0x002c
11477 #define ixRTAVFS_REG45                                                                                 0x002d
11478 #define ixRTAVFS_REG46                                                                                 0x002e
11479 #define ixRTAVFS_REG47                                                                                 0x002f
11480 #define ixRTAVFS_REG48                                                                                 0x0030
11481 #define ixRTAVFS_REG49                                                                                 0x0031
11482 #define ixRTAVFS_REG50                                                                                 0x0032
11483 #define ixRTAVFS_REG51                                                                                 0x0033
11484 #define ixRTAVFS_REG52                                                                                 0x0034
11485 #define ixRTAVFS_REG53                                                                                 0x0035
11486 #define ixRTAVFS_REG54                                                                                 0x0036
11487 #define ixRTAVFS_REG55                                                                                 0x0037
11488 #define ixRTAVFS_REG56                                                                                 0x0038
11489 #define ixRTAVFS_REG57                                                                                 0x0039
11490 #define ixRTAVFS_REG58                                                                                 0x003a
11491 #define ixRTAVFS_REG59                                                                                 0x003b
11492 #define ixRTAVFS_REG60                                                                                 0x003c
11493 #define ixRTAVFS_REG61                                                                                 0x003d
11494 #define ixRTAVFS_REG62                                                                                 0x003e
11495 #define ixRTAVFS_REG63                                                                                 0x003f
11496 #define ixRTAVFS_REG64                                                                                 0x0040
11497 #define ixRTAVFS_REG65                                                                                 0x0041
11498 #define ixRTAVFS_REG66                                                                                 0x0042
11499 #define ixRTAVFS_REG67                                                                                 0x0043
11500 #define ixRTAVFS_REG68                                                                                 0x0044
11501 #define ixRTAVFS_REG69                                                                                 0x0045
11502 #define ixRTAVFS_REG70                                                                                 0x0046
11503 #define ixRTAVFS_REG71                                                                                 0x0047
11504 #define ixRTAVFS_REG72                                                                                 0x0048
11505 #define ixRTAVFS_REG73                                                                                 0x0049
11506 #define ixRTAVFS_REG74                                                                                 0x004a
11507 #define ixRTAVFS_REG75                                                                                 0x004b
11508 #define ixRTAVFS_REG76                                                                                 0x004c
11509 #define ixRTAVFS_REG77                                                                                 0x004d
11510 #define ixRTAVFS_REG78                                                                                 0x004e
11511 #define ixRTAVFS_REG79                                                                                 0x004f
11512 #define ixRTAVFS_REG80                                                                                 0x0050
11513 #define ixRTAVFS_REG81                                                                                 0x0051
11514 #define ixRTAVFS_REG82                                                                                 0x0052
11515 #define ixRTAVFS_REG83                                                                                 0x0053
11516 #define ixRTAVFS_REG84                                                                                 0x0054
11517 #define ixRTAVFS_REG85                                                                                 0x0055
11518 #define ixRTAVFS_REG86                                                                                 0x0056
11519 #define ixRTAVFS_REG87                                                                                 0x0057
11520 #define ixRTAVFS_REG88                                                                                 0x0058
11521 #define ixRTAVFS_REG89                                                                                 0x0059
11522 #define ixRTAVFS_REG90                                                                                 0x005a
11523 #define ixRTAVFS_REG91                                                                                 0x005b
11524 #define ixRTAVFS_REG92                                                                                 0x005c
11525 #define ixRTAVFS_REG93                                                                                 0x005d
11526 #define ixRTAVFS_REG94                                                                                 0x005e
11527 #define ixRTAVFS_REG95                                                                                 0x005f
11528 #define ixRTAVFS_REG96                                                                                 0x0060
11529 #define ixRTAVFS_REG97                                                                                 0x0061
11530 #define ixRTAVFS_REG98                                                                                 0x0062
11531 #define ixRTAVFS_REG99                                                                                 0x0063
11532 #define ixRTAVFS_REG100                                                                                0x0064
11533 #define ixRTAVFS_REG101                                                                                0x0065
11534 #define ixRTAVFS_REG102                                                                                0x0066
11535 #define ixRTAVFS_REG103                                                                                0x0067
11536 #define ixRTAVFS_REG104                                                                                0x0068
11537 #define ixRTAVFS_REG105                                                                                0x0069
11538 #define ixRTAVFS_REG106                                                                                0x006a
11539 #define ixRTAVFS_REG107                                                                                0x006b
11540 #define ixRTAVFS_REG108                                                                                0x006c
11541 #define ixRTAVFS_REG109                                                                                0x006d
11542 #define ixRTAVFS_REG110                                                                                0x006e
11543 #define ixRTAVFS_REG111                                                                                0x006f
11544 #define ixRTAVFS_REG112                                                                                0x0070
11545 #define ixRTAVFS_REG113                                                                                0x0071
11546 #define ixRTAVFS_REG114                                                                                0x0072
11547 #define ixRTAVFS_REG115                                                                                0x0073
11548 #define ixRTAVFS_REG116                                                                                0x0074
11549 #define ixRTAVFS_REG117                                                                                0x0075
11550 #define ixRTAVFS_REG118                                                                                0x0076
11551 #define ixRTAVFS_REG119                                                                                0x0077
11552 #define ixRTAVFS_REG120                                                                                0x0078
11553 #define ixRTAVFS_REG121                                                                                0x0079
11554 #define ixRTAVFS_REG122                                                                                0x007a
11555 #define ixRTAVFS_REG123                                                                                0x007b
11556 #define ixRTAVFS_REG124                                                                                0x007c
11557 #define ixRTAVFS_REG125                                                                                0x007d
11558 #define ixRTAVFS_REG126                                                                                0x007e
11559 #define ixRTAVFS_REG127                                                                                0x007f
11560 #define ixRTAVFS_REG128                                                                                0x0080
11561 #define ixRTAVFS_REG129                                                                                0x0081
11562 #define ixRTAVFS_REG130                                                                                0x0082
11563 #define ixRTAVFS_REG131                                                                                0x0083
11564 #define ixRTAVFS_REG132                                                                                0x0084
11565 #define ixRTAVFS_REG133                                                                                0x0085
11566 #define ixRTAVFS_REG134                                                                                0x0086
11567 #define ixRTAVFS_REG135                                                                                0x0087
11568 #define ixRTAVFS_REG136                                                                                0x0088
11569 #define ixRTAVFS_REG137                                                                                0x0089
11570 #define ixRTAVFS_REG138                                                                                0x008a
11571 #define ixRTAVFS_REG139                                                                                0x008b
11572 #define ixRTAVFS_REG140                                                                                0x008c
11573 #define ixRTAVFS_REG141                                                                                0x008d
11574 #define ixRTAVFS_REG142                                                                                0x008e
11575 #define ixRTAVFS_REG143                                                                                0x008f
11576 #define ixRTAVFS_REG144                                                                                0x0090
11577 #define ixRTAVFS_REG145                                                                                0x0091
11578 #define ixRTAVFS_REG146                                                                                0x0092
11579 #define ixRTAVFS_REG147                                                                                0x0093
11580 #define ixRTAVFS_REG148                                                                                0x0094
11581 #define ixRTAVFS_REG149                                                                                0x0095
11582 #define ixRTAVFS_REG150                                                                                0x0096
11583 #define ixRTAVFS_REG151                                                                                0x0097
11584 #define ixRTAVFS_REG152                                                                                0x0098
11585 #define ixRTAVFS_REG153                                                                                0x0099
11586 #define ixRTAVFS_REG154                                                                                0x009a
11587 #define ixRTAVFS_REG155                                                                                0x009b
11588 #define ixRTAVFS_REG156                                                                                0x009c
11589 #define ixRTAVFS_REG157                                                                                0x009d
11590 #define ixRTAVFS_REG158                                                                                0x009e
11591 #define ixRTAVFS_REG159                                                                                0x009f
11592 #define ixRTAVFS_REG160                                                                                0x00a0
11593 #define ixRTAVFS_REG161                                                                                0x00a1
11594 #define ixRTAVFS_REG162                                                                                0x00a2
11595 #define ixRTAVFS_REG163                                                                                0x00a3
11596 #define ixRTAVFS_REG164                                                                                0x00a4
11597 #define ixRTAVFS_REG165                                                                                0x00a5
11598 #define ixRTAVFS_REG166                                                                                0x00a6
11599 #define ixRTAVFS_REG167                                                                                0x00a7
11600 #define ixRTAVFS_REG168                                                                                0x00a8
11601 #define ixRTAVFS_REG169                                                                                0x00a9
11602 #define ixRTAVFS_REG170                                                                                0x00aa
11603 #define ixRTAVFS_REG171                                                                                0x00ab
11604 #define ixRTAVFS_REG172                                                                                0x00ac
11605 #define ixRTAVFS_REG173                                                                                0x00ad
11606 #define ixRTAVFS_REG174                                                                                0x00ae
11607 #define ixRTAVFS_REG175                                                                                0x00af
11608 #define ixRTAVFS_REG176                                                                                0x00b0
11609 #define ixRTAVFS_REG177                                                                                0x00b1
11610 #define ixRTAVFS_REG178                                                                                0x00b2
11611 #define ixRTAVFS_REG179                                                                                0x00b3
11612 #define ixRTAVFS_REG180                                                                                0x00b4
11613 #define ixRTAVFS_REG181                                                                                0x00b5
11614 #define ixRTAVFS_REG182                                                                                0x00b6
11615 #define ixRTAVFS_REG183                                                                                0x00b7
11616 #define ixRTAVFS_REG184                                                                                0x00b8
11617 #define ixRTAVFS_REG185                                                                                0x00b9
11618 #define ixRTAVFS_REG186                                                                                0x00ba
11619 #define ixRTAVFS_REG187                                                                                0x00bb
11620 #define ixRTAVFS_REG188                                                                                0x00bc
11621 #define ixRTAVFS_REG189                                                                                0x00bd
11622 #define ixRTAVFS_REG190                                                                                0x00be
11623 #define ixRTAVFS_REG191                                                                                0x00bf
11624 #define ixRTAVFS_REG192                                                                                0x00c0
11625 #define ixRTAVFS_REG193                                                                                0x00c1
11626 #define ixRTAVFS_REG194                                                                                0x00c2
11627 
11628 
11629 // addressBlock: sqind
11630 // base address: 0x0
11631 #define ixSQ_DEBUG_STS_LOCAL                                                                           0x0008
11632 #define ixSQ_DEBUG_CTRL_LOCAL                                                                          0x0009
11633 #define ixSQ_WAVE_ACTIVE                                                                               0x000a
11634 #define ixSQ_WAVE_VALID_AND_IDLE                                                                       0x000b
11635 #define ixSQ_WAVE_MODE                                                                                 0x0101
11636 #define ixSQ_WAVE_STATUS                                                                               0x0102
11637 #define ixSQ_WAVE_TRAPSTS                                                                              0x0103
11638 #define ixSQ_WAVE_GPR_ALLOC                                                                            0x0105
11639 #define ixSQ_WAVE_LDS_ALLOC                                                                            0x0106
11640 #define ixSQ_WAVE_IB_STS                                                                               0x0107
11641 #define ixSQ_WAVE_PC_LO                                                                                0x0108
11642 #define ixSQ_WAVE_PC_HI                                                                                0x0109
11643 #define ixSQ_WAVE_IB_DBG1                                                                              0x010d
11644 #define ixSQ_WAVE_FLUSH_IB                                                                             0x010e
11645 #define ixSQ_WAVE_FLAT_SCRATCH_LO                                                                      0x0114
11646 #define ixSQ_WAVE_FLAT_SCRATCH_HI                                                                      0x0115
11647 #define ixSQ_WAVE_HW_ID1                                                                               0x0117
11648 #define ixSQ_WAVE_HW_ID2                                                                               0x0118
11649 #define ixSQ_WAVE_POPS_PACKER                                                                          0x0119
11650 #define ixSQ_WAVE_SCHED_MODE                                                                           0x011a
11651 #define ixSQ_WAVE_IB_STS2                                                                              0x011c
11652 #define ixSQ_WAVE_SHADER_CYCLES                                                                        0x011d
11653 #define ixSQ_WAVE_TTMP0                                                                                0x026c
11654 #define ixSQ_WAVE_TTMP1                                                                                0x026d
11655 #define ixSQ_WAVE_TTMP3                                                                                0x026f
11656 #define ixSQ_WAVE_TTMP4                                                                                0x0270
11657 #define ixSQ_WAVE_TTMP5                                                                                0x0271
11658 #define ixSQ_WAVE_TTMP6                                                                                0x0272
11659 #define ixSQ_WAVE_TTMP7                                                                                0x0273
11660 #define ixSQ_WAVE_TTMP8                                                                                0x0274
11661 #define ixSQ_WAVE_TTMP9                                                                                0x0275
11662 #define ixSQ_WAVE_TTMP10                                                                               0x0276
11663 #define ixSQ_WAVE_TTMP11                                                                               0x0277
11664 #define ixSQ_WAVE_TTMP12                                                                               0x0278
11665 #define ixSQ_WAVE_TTMP13                                                                               0x0279
11666 #define ixSQ_WAVE_TTMP14                                                                               0x027a
11667 #define ixSQ_WAVE_TTMP15                                                                               0x027b
11668 #define ixSQ_WAVE_M0                                                                                   0x027d
11669 #define ixSQ_WAVE_EXEC_LO                                                                              0x027e
11670 #define ixSQ_WAVE_EXEC_HI                                                                              0x027f
11671 
11672 
11673 #endif
11674