1 /*
2  * Copyright (C) 2019  Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included
12  * in all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
15  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
18  * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
19  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
20  */
21 #ifndef _dpcs_2_1_0_OFFSET_HEADER
22 #define _dpcs_2_1_0_OFFSET_HEADER
23 
24 
25 
26 // addressBlock: dpcssys_dpcs0_dpcstx0_dispdec
27 // base address: 0x0
28 #define mmDPCSTX0_DPCSTX_TX_CLOCK_CNTL                                                                 0x2928
29 #define mmDPCSTX0_DPCSTX_TX_CLOCK_CNTL_BASE_IDX                                                        2
30 #define mmDPCSTX0_DPCSTX_TX_CNTL                                                                       0x2929
31 #define mmDPCSTX0_DPCSTX_TX_CNTL_BASE_IDX                                                              2
32 #define mmDPCSTX0_DPCSTX_CBUS_CNTL                                                                     0x292a
33 #define mmDPCSTX0_DPCSTX_CBUS_CNTL_BASE_IDX                                                            2
34 #define mmDPCSTX0_DPCSTX_INTERRUPT_CNTL                                                                0x292b
35 #define mmDPCSTX0_DPCSTX_INTERRUPT_CNTL_BASE_IDX                                                       2
36 #define mmDPCSTX0_DPCSTX_PLL_UPDATE_ADDR                                                               0x292c
37 #define mmDPCSTX0_DPCSTX_PLL_UPDATE_ADDR_BASE_IDX                                                      2
38 #define mmDPCSTX0_DPCSTX_PLL_UPDATE_DATA                                                               0x292d
39 #define mmDPCSTX0_DPCSTX_PLL_UPDATE_DATA_BASE_IDX                                                      2
40 #define mmDPCSTX0_DPCSTX_DEBUG_CONFIG                                                                  0x292e
41 #define mmDPCSTX0_DPCSTX_DEBUG_CONFIG_BASE_IDX                                                         2
42 
43 
44 // addressBlock: dpcssys_dpcs0_rdpcstx0_dispdec
45 // base address: 0x0
46 #define mmRDPCSTX0_RDPCSTX_CNTL                                                                        0x2930
47 #define mmRDPCSTX0_RDPCSTX_CNTL_BASE_IDX                                                               2
48 #define mmRDPCSTX0_RDPCSTX_CLOCK_CNTL                                                                  0x2931
49 #define mmRDPCSTX0_RDPCSTX_CLOCK_CNTL_BASE_IDX                                                         2
50 #define mmRDPCSTX0_RDPCSTX_INTERRUPT_CONTROL                                                           0x2932
51 #define mmRDPCSTX0_RDPCSTX_INTERRUPT_CONTROL_BASE_IDX                                                  2
52 #define mmRDPCSTX0_RDPCSTX_PLL_UPDATE_DATA                                                             0x2933
53 #define mmRDPCSTX0_RDPCSTX_PLL_UPDATE_DATA_BASE_IDX                                                    2
54 #define mmRDPCSTX0_RDPCS_TX_CR_ADDR                                                                    0x2934
55 #define mmRDPCSTX0_RDPCS_TX_CR_ADDR_BASE_IDX                                                           2
56 #define mmRDPCSTX0_RDPCS_TX_CR_DATA                                                                    0x2935
57 #define mmRDPCSTX0_RDPCS_TX_CR_DATA_BASE_IDX                                                           2
58 #define mmRDPCSTX0_RDPCS_TX_SRAM_CNTL                                                                  0x2936
59 #define mmRDPCSTX0_RDPCS_TX_SRAM_CNTL_BASE_IDX                                                         2
60 #define mmRDPCSTX0_RDPCSTX_SCRATCH                                                                     0x2937
61 #define mmRDPCSTX0_RDPCSTX_SCRATCH_BASE_IDX                                                            2
62 #define mmRDPCSTX0_RDPCSTX_SPARE                                                                       0x2938
63 #define mmRDPCSTX0_RDPCSTX_SPARE_BASE_IDX                                                              2
64 #define mmRDPCSTX0_RDPCSTX_CNTL2                                                                       0x2939
65 #define mmRDPCSTX0_RDPCSTX_CNTL2_BASE_IDX                                                              2
66 #define mmRDPCSTX0_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG                                                    0x293c
67 #define mmRDPCSTX0_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG_BASE_IDX                                           2
68 #define mmRDPCSTX0_RDPCSTX_DEBUG_CONFIG                                                                0x293d
69 #define mmRDPCSTX0_RDPCSTX_DEBUG_CONFIG_BASE_IDX                                                       2
70 #define mmRDPCSTX0_RDPCSTX_PHY_CNTL0                                                                   0x2940
71 #define mmRDPCSTX0_RDPCSTX_PHY_CNTL0_BASE_IDX                                                          2
72 #define mmRDPCSTX0_RDPCSTX_PHY_CNTL1                                                                   0x2941
73 #define mmRDPCSTX0_RDPCSTX_PHY_CNTL1_BASE_IDX                                                          2
74 #define mmRDPCSTX0_RDPCSTX_PHY_CNTL2                                                                   0x2942
75 #define mmRDPCSTX0_RDPCSTX_PHY_CNTL2_BASE_IDX                                                          2
76 #define mmRDPCSTX0_RDPCSTX_PHY_CNTL3                                                                   0x2943
77 #define mmRDPCSTX0_RDPCSTX_PHY_CNTL3_BASE_IDX                                                          2
78 #define mmRDPCSTX0_RDPCSTX_PHY_CNTL4                                                                   0x2944
79 #define mmRDPCSTX0_RDPCSTX_PHY_CNTL4_BASE_IDX                                                          2
80 #define mmRDPCSTX0_RDPCSTX_PHY_CNTL5                                                                   0x2945
81 #define mmRDPCSTX0_RDPCSTX_PHY_CNTL5_BASE_IDX                                                          2
82 #define mmRDPCSTX0_RDPCSTX_PHY_CNTL6                                                                   0x2946
83 #define mmRDPCSTX0_RDPCSTX_PHY_CNTL6_BASE_IDX                                                          2
84 #define mmRDPCSTX0_RDPCSTX_PHY_CNTL7                                                                   0x2947
85 #define mmRDPCSTX0_RDPCSTX_PHY_CNTL7_BASE_IDX                                                          2
86 #define mmRDPCSTX0_RDPCSTX_PHY_CNTL8                                                                   0x2948
87 #define mmRDPCSTX0_RDPCSTX_PHY_CNTL8_BASE_IDX                                                          2
88 #define mmRDPCSTX0_RDPCSTX_PHY_CNTL9                                                                   0x2949
89 #define mmRDPCSTX0_RDPCSTX_PHY_CNTL9_BASE_IDX                                                          2
90 #define mmRDPCSTX0_RDPCSTX_PHY_CNTL10                                                                  0x294a
91 #define mmRDPCSTX0_RDPCSTX_PHY_CNTL10_BASE_IDX                                                         2
92 #define mmRDPCSTX0_RDPCSTX_PHY_CNTL11                                                                  0x294b
93 #define mmRDPCSTX0_RDPCSTX_PHY_CNTL11_BASE_IDX                                                         2
94 #define mmRDPCSTX0_RDPCSTX_PHY_CNTL12                                                                  0x294c
95 #define mmRDPCSTX0_RDPCSTX_PHY_CNTL12_BASE_IDX                                                         2
96 #define mmRDPCSTX0_RDPCSTX_PHY_CNTL13                                                                  0x294d
97 #define mmRDPCSTX0_RDPCSTX_PHY_CNTL13_BASE_IDX                                                         2
98 #define mmRDPCSTX0_RDPCSTX_PHY_CNTL14                                                                  0x294e
99 #define mmRDPCSTX0_RDPCSTX_PHY_CNTL14_BASE_IDX                                                         2
100 #define mmRDPCSTX0_RDPCSTX_PHY_FUSE0                                                                   0x294f
101 #define mmRDPCSTX0_RDPCSTX_PHY_FUSE0_BASE_IDX                                                          2
102 #define mmRDPCSTX0_RDPCSTX_PHY_FUSE1                                                                   0x2950
103 #define mmRDPCSTX0_RDPCSTX_PHY_FUSE1_BASE_IDX                                                          2
104 #define mmRDPCSTX0_RDPCSTX_PHY_FUSE2                                                                   0x2951
105 #define mmRDPCSTX0_RDPCSTX_PHY_FUSE2_BASE_IDX                                                          2
106 #define mmRDPCSTX0_RDPCSTX_PHY_FUSE3                                                                   0x2952
107 #define mmRDPCSTX0_RDPCSTX_PHY_FUSE3_BASE_IDX                                                          2
108 #define mmRDPCSTX0_RDPCSTX_PHY_RX_LD_VAL                                                               0x2953
109 #define mmRDPCSTX0_RDPCSTX_PHY_RX_LD_VAL_BASE_IDX                                                      2
110 #define mmRDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3                                                        0x2954
111 #define mmRDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3_BASE_IDX                                               2
112 #define mmRDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6                                                        0x2955
113 #define mmRDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6_BASE_IDX                                               2
114 #define mmRDPCSTX0_RDPCSTX_DPALT_CONTROL_REG                                                           0x2956
115 #define mmRDPCSTX0_RDPCSTX_DPALT_CONTROL_REG_BASE_IDX                                                  2
116 #define mmRDPCSTX0_RDPCSTX_PHY_CNTL15                                                                  0x2958
117 #define mmRDPCSTX0_RDPCSTX_PHY_CNTL15_BASE_IDX                                                         2
118 #define mmRDPCSTX0_RDPCSTX_PHY_CNTL16                                                                  0x2959
119 #define mmRDPCSTX0_RDPCSTX_PHY_CNTL16_BASE_IDX                                                         2
120 #define mmRDPCSTX0_RDPCSTX_PHY_CNTL17                                                                  0x295a
121 #define mmRDPCSTX0_RDPCSTX_PHY_CNTL17_BASE_IDX                                                         2
122 #define mmRDPCSTX0_RDPCSTX_DEBUG_CONFIG2                                                               0x295b
123 #define mmRDPCSTX0_RDPCSTX_DEBUG_CONFIG2_BASE_IDX                                                      2
124 
125 
126 // addressBlock: dpcssys_dpcssys_cr0_dispdec
127 // base address: 0x0
128 #define mmDPCSSYS_CR0_DPCSSYS_CR_ADDR                                                                  0x2934
129 #define mmDPCSSYS_CR0_DPCSSYS_CR_ADDR_BASE_IDX                                                         2
130 #define mmDPCSSYS_CR0_DPCSSYS_CR_DATA                                                                  0x2935
131 #define mmDPCSSYS_CR0_DPCSSYS_CR_DATA_BASE_IDX                                                         2
132 
133 
134 // addressBlock: dpcssys_dpcs0_dpcstx1_dispdec
135 // base address: 0x360
136 #define mmDPCSTX1_DPCSTX_TX_CLOCK_CNTL                                                                 0x2a00
137 #define mmDPCSTX1_DPCSTX_TX_CLOCK_CNTL_BASE_IDX                                                        2
138 #define mmDPCSTX1_DPCSTX_TX_CNTL                                                                       0x2a01
139 #define mmDPCSTX1_DPCSTX_TX_CNTL_BASE_IDX                                                              2
140 #define mmDPCSTX1_DPCSTX_CBUS_CNTL                                                                     0x2a02
141 #define mmDPCSTX1_DPCSTX_CBUS_CNTL_BASE_IDX                                                            2
142 #define mmDPCSTX1_DPCSTX_INTERRUPT_CNTL                                                                0x2a03
143 #define mmDPCSTX1_DPCSTX_INTERRUPT_CNTL_BASE_IDX                                                       2
144 #define mmDPCSTX1_DPCSTX_PLL_UPDATE_ADDR                                                               0x2a04
145 #define mmDPCSTX1_DPCSTX_PLL_UPDATE_ADDR_BASE_IDX                                                      2
146 #define mmDPCSTX1_DPCSTX_PLL_UPDATE_DATA                                                               0x2a05
147 #define mmDPCSTX1_DPCSTX_PLL_UPDATE_DATA_BASE_IDX                                                      2
148 #define mmDPCSTX1_DPCSTX_DEBUG_CONFIG                                                                  0x2a06
149 #define mmDPCSTX1_DPCSTX_DEBUG_CONFIG_BASE_IDX                                                         2
150 
151 
152 // addressBlock: dpcssys_dpcs0_rdpcstx1_dispdec
153 // base address: 0x360
154 #define mmRDPCSTX1_RDPCSTX_CNTL                                                                        0x2a08
155 #define mmRDPCSTX1_RDPCSTX_CNTL_BASE_IDX                                                               2
156 #define mmRDPCSTX1_RDPCSTX_CLOCK_CNTL                                                                  0x2a09
157 #define mmRDPCSTX1_RDPCSTX_CLOCK_CNTL_BASE_IDX                                                         2
158 #define mmRDPCSTX1_RDPCSTX_INTERRUPT_CONTROL                                                           0x2a0a
159 #define mmRDPCSTX1_RDPCSTX_INTERRUPT_CONTROL_BASE_IDX                                                  2
160 #define mmRDPCSTX1_RDPCSTX_PLL_UPDATE_DATA                                                             0x2a0b
161 #define mmRDPCSTX1_RDPCSTX_PLL_UPDATE_DATA_BASE_IDX                                                    2
162 #define mmRDPCSTX1_RDPCS_TX_CR_ADDR                                                                    0x2a0c
163 #define mmRDPCSTX1_RDPCS_TX_CR_ADDR_BASE_IDX                                                           2
164 #define mmRDPCSTX1_RDPCS_TX_CR_DATA                                                                    0x2a0d
165 #define mmRDPCSTX1_RDPCS_TX_CR_DATA_BASE_IDX                                                           2
166 #define mmRDPCSTX1_RDPCS_TX_SRAM_CNTL                                                                  0x2a0e
167 #define mmRDPCSTX1_RDPCS_TX_SRAM_CNTL_BASE_IDX                                                         2
168 #define mmRDPCSTX1_RDPCSTX_SCRATCH                                                                     0x2a0f
169 #define mmRDPCSTX1_RDPCSTX_SCRATCH_BASE_IDX                                                            2
170 #define mmRDPCSTX1_RDPCSTX_SPARE                                                                       0x2a10
171 #define mmRDPCSTX1_RDPCSTX_SPARE_BASE_IDX                                                              2
172 #define mmRDPCSTX1_RDPCSTX_CNTL2                                                                       0x2a11
173 #define mmRDPCSTX1_RDPCSTX_CNTL2_BASE_IDX                                                              2
174 #define mmRDPCSTX1_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG                                                    0x2a14
175 #define mmRDPCSTX1_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG_BASE_IDX                                           2
176 #define mmRDPCSTX1_RDPCSTX_DEBUG_CONFIG                                                                0x2a15
177 #define mmRDPCSTX1_RDPCSTX_DEBUG_CONFIG_BASE_IDX                                                       2
178 #define mmRDPCSTX1_RDPCSTX_PHY_CNTL0                                                                   0x2a18
179 #define mmRDPCSTX1_RDPCSTX_PHY_CNTL0_BASE_IDX                                                          2
180 #define mmRDPCSTX1_RDPCSTX_PHY_CNTL1                                                                   0x2a19
181 #define mmRDPCSTX1_RDPCSTX_PHY_CNTL1_BASE_IDX                                                          2
182 #define mmRDPCSTX1_RDPCSTX_PHY_CNTL2                                                                   0x2a1a
183 #define mmRDPCSTX1_RDPCSTX_PHY_CNTL2_BASE_IDX                                                          2
184 #define mmRDPCSTX1_RDPCSTX_PHY_CNTL3                                                                   0x2a1b
185 #define mmRDPCSTX1_RDPCSTX_PHY_CNTL3_BASE_IDX                                                          2
186 #define mmRDPCSTX1_RDPCSTX_PHY_CNTL4                                                                   0x2a1c
187 #define mmRDPCSTX1_RDPCSTX_PHY_CNTL4_BASE_IDX                                                          2
188 #define mmRDPCSTX1_RDPCSTX_PHY_CNTL5                                                                   0x2a1d
189 #define mmRDPCSTX1_RDPCSTX_PHY_CNTL5_BASE_IDX                                                          2
190 #define mmRDPCSTX1_RDPCSTX_PHY_CNTL6                                                                   0x2a1e
191 #define mmRDPCSTX1_RDPCSTX_PHY_CNTL6_BASE_IDX                                                          2
192 #define mmRDPCSTX1_RDPCSTX_PHY_CNTL7                                                                   0x2a1f
193 #define mmRDPCSTX1_RDPCSTX_PHY_CNTL7_BASE_IDX                                                          2
194 #define mmRDPCSTX1_RDPCSTX_PHY_CNTL8                                                                   0x2a20
195 #define mmRDPCSTX1_RDPCSTX_PHY_CNTL8_BASE_IDX                                                          2
196 #define mmRDPCSTX1_RDPCSTX_PHY_CNTL9                                                                   0x2a21
197 #define mmRDPCSTX1_RDPCSTX_PHY_CNTL9_BASE_IDX                                                          2
198 #define mmRDPCSTX1_RDPCSTX_PHY_CNTL10                                                                  0x2a22
199 #define mmRDPCSTX1_RDPCSTX_PHY_CNTL10_BASE_IDX                                                         2
200 #define mmRDPCSTX1_RDPCSTX_PHY_CNTL11                                                                  0x2a23
201 #define mmRDPCSTX1_RDPCSTX_PHY_CNTL11_BASE_IDX                                                         2
202 #define mmRDPCSTX1_RDPCSTX_PHY_CNTL12                                                                  0x2a24
203 #define mmRDPCSTX1_RDPCSTX_PHY_CNTL12_BASE_IDX                                                         2
204 #define mmRDPCSTX1_RDPCSTX_PHY_CNTL13                                                                  0x2a25
205 #define mmRDPCSTX1_RDPCSTX_PHY_CNTL13_BASE_IDX                                                         2
206 #define mmRDPCSTX1_RDPCSTX_PHY_CNTL14                                                                  0x2a26
207 #define mmRDPCSTX1_RDPCSTX_PHY_CNTL14_BASE_IDX                                                         2
208 #define mmRDPCSTX1_RDPCSTX_PHY_FUSE0                                                                   0x2a27
209 #define mmRDPCSTX1_RDPCSTX_PHY_FUSE0_BASE_IDX                                                          2
210 #define mmRDPCSTX1_RDPCSTX_PHY_FUSE1                                                                   0x2a28
211 #define mmRDPCSTX1_RDPCSTX_PHY_FUSE1_BASE_IDX                                                          2
212 #define mmRDPCSTX1_RDPCSTX_PHY_FUSE2                                                                   0x2a29
213 #define mmRDPCSTX1_RDPCSTX_PHY_FUSE2_BASE_IDX                                                          2
214 #define mmRDPCSTX1_RDPCSTX_PHY_FUSE3                                                                   0x2a2a
215 #define mmRDPCSTX1_RDPCSTX_PHY_FUSE3_BASE_IDX                                                          2
216 #define mmRDPCSTX1_RDPCSTX_PHY_RX_LD_VAL                                                               0x2a2b
217 #define mmRDPCSTX1_RDPCSTX_PHY_RX_LD_VAL_BASE_IDX                                                      2
218 #define mmRDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3                                                        0x2a2c
219 #define mmRDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3_BASE_IDX                                               2
220 #define mmRDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6                                                        0x2a2d
221 #define mmRDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6_BASE_IDX                                               2
222 #define mmRDPCSTX1_RDPCSTX_DPALT_CONTROL_REG                                                           0x2a2e
223 #define mmRDPCSTX1_RDPCSTX_DPALT_CONTROL_REG_BASE_IDX                                                  2
224 #define mmRDPCSTX1_RDPCSTX_PHY_CNTL15                                                                  0x2a30
225 #define mmRDPCSTX1_RDPCSTX_PHY_CNTL15_BASE_IDX                                                         2
226 #define mmRDPCSTX1_RDPCSTX_PHY_CNTL16                                                                  0x2a31
227 #define mmRDPCSTX1_RDPCSTX_PHY_CNTL16_BASE_IDX                                                         2
228 #define mmRDPCSTX1_RDPCSTX_PHY_CNTL17                                                                  0x2a32
229 #define mmRDPCSTX1_RDPCSTX_PHY_CNTL17_BASE_IDX                                                         2
230 #define mmRDPCSTX1_RDPCSTX_DEBUG_CONFIG2                                                               0x2a33
231 #define mmRDPCSTX1_RDPCSTX_DEBUG_CONFIG2_BASE_IDX                                                      2
232 
233 
234 // addressBlock: dpcssys_dpcssys_cr1_dispdec
235 // base address: 0x360
236 #define mmDPCSSYS_CR1_DPCSSYS_CR_ADDR                                                                  0x2a0c
237 #define mmDPCSSYS_CR1_DPCSSYS_CR_ADDR_BASE_IDX                                                         2
238 #define mmDPCSSYS_CR1_DPCSSYS_CR_DATA                                                                  0x2a0d
239 #define mmDPCSSYS_CR1_DPCSSYS_CR_DATA_BASE_IDX                                                         2
240 
241 
242 // addressBlock: dpcssys_dpcs0_dpcstx2_dispdec
243 // base address: 0x6c0
244 #define mmDPCSTX2_DPCSTX_TX_CLOCK_CNTL                                                                 0x2ad8
245 #define mmDPCSTX2_DPCSTX_TX_CLOCK_CNTL_BASE_IDX                                                        2
246 #define mmDPCSTX2_DPCSTX_TX_CNTL                                                                       0x2ad9
247 #define mmDPCSTX2_DPCSTX_TX_CNTL_BASE_IDX                                                              2
248 #define mmDPCSTX2_DPCSTX_CBUS_CNTL                                                                     0x2ada
249 #define mmDPCSTX2_DPCSTX_CBUS_CNTL_BASE_IDX                                                            2
250 #define mmDPCSTX2_DPCSTX_INTERRUPT_CNTL                                                                0x2adb
251 #define mmDPCSTX2_DPCSTX_INTERRUPT_CNTL_BASE_IDX                                                       2
252 #define mmDPCSTX2_DPCSTX_PLL_UPDATE_ADDR                                                               0x2adc
253 #define mmDPCSTX2_DPCSTX_PLL_UPDATE_ADDR_BASE_IDX                                                      2
254 #define mmDPCSTX2_DPCSTX_PLL_UPDATE_DATA                                                               0x2add
255 #define mmDPCSTX2_DPCSTX_PLL_UPDATE_DATA_BASE_IDX                                                      2
256 #define mmDPCSTX2_DPCSTX_DEBUG_CONFIG                                                                  0x2ade
257 #define mmDPCSTX2_DPCSTX_DEBUG_CONFIG_BASE_IDX                                                         2
258 
259 
260 // addressBlock: dpcssys_dpcs0_rdpcstx2_dispdec
261 // base address: 0x6c0
262 #define mmRDPCSTX2_RDPCSTX_CNTL                                                                        0x2ae0
263 #define mmRDPCSTX2_RDPCSTX_CNTL_BASE_IDX                                                               2
264 #define mmRDPCSTX2_RDPCSTX_CLOCK_CNTL                                                                  0x2ae1
265 #define mmRDPCSTX2_RDPCSTX_CLOCK_CNTL_BASE_IDX                                                         2
266 #define mmRDPCSTX2_RDPCSTX_INTERRUPT_CONTROL                                                           0x2ae2
267 #define mmRDPCSTX2_RDPCSTX_INTERRUPT_CONTROL_BASE_IDX                                                  2
268 #define mmRDPCSTX2_RDPCSTX_PLL_UPDATE_DATA                                                             0x2ae3
269 #define mmRDPCSTX2_RDPCSTX_PLL_UPDATE_DATA_BASE_IDX                                                    2
270 #define mmRDPCSTX2_RDPCS_TX_CR_ADDR                                                                    0x2ae4
271 #define mmRDPCSTX2_RDPCS_TX_CR_ADDR_BASE_IDX                                                           2
272 #define mmRDPCSTX2_RDPCS_TX_CR_DATA                                                                    0x2ae5
273 #define mmRDPCSTX2_RDPCS_TX_CR_DATA_BASE_IDX                                                           2
274 #define mmRDPCSTX2_RDPCS_TX_SRAM_CNTL                                                                  0x2ae6
275 #define mmRDPCSTX2_RDPCS_TX_SRAM_CNTL_BASE_IDX                                                         2
276 #define mmRDPCSTX2_RDPCSTX_SCRATCH                                                                     0x2ae7
277 #define mmRDPCSTX2_RDPCSTX_SCRATCH_BASE_IDX                                                            2
278 #define mmRDPCSTX2_RDPCSTX_SPARE                                                                       0x2ae8
279 #define mmRDPCSTX2_RDPCSTX_SPARE_BASE_IDX                                                              2
280 #define mmRDPCSTX2_RDPCSTX_CNTL2                                                                       0x2ae9
281 #define mmRDPCSTX2_RDPCSTX_CNTL2_BASE_IDX                                                              2
282 #define mmRDPCSTX2_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG                                                    0x2aec
283 #define mmRDPCSTX2_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG_BASE_IDX                                           2
284 #define mmRDPCSTX2_RDPCSTX_DEBUG_CONFIG                                                                0x2aed
285 #define mmRDPCSTX2_RDPCSTX_DEBUG_CONFIG_BASE_IDX                                                       2
286 #define mmRDPCSTX2_RDPCSTX_PHY_CNTL0                                                                   0x2af0
287 #define mmRDPCSTX2_RDPCSTX_PHY_CNTL0_BASE_IDX                                                          2
288 #define mmRDPCSTX2_RDPCSTX_PHY_CNTL1                                                                   0x2af1
289 #define mmRDPCSTX2_RDPCSTX_PHY_CNTL1_BASE_IDX                                                          2
290 #define mmRDPCSTX2_RDPCSTX_PHY_CNTL2                                                                   0x2af2
291 #define mmRDPCSTX2_RDPCSTX_PHY_CNTL2_BASE_IDX                                                          2
292 #define mmRDPCSTX2_RDPCSTX_PHY_CNTL3                                                                   0x2af3
293 #define mmRDPCSTX2_RDPCSTX_PHY_CNTL3_BASE_IDX                                                          2
294 #define mmRDPCSTX2_RDPCSTX_PHY_CNTL4                                                                   0x2af4
295 #define mmRDPCSTX2_RDPCSTX_PHY_CNTL4_BASE_IDX                                                          2
296 #define mmRDPCSTX2_RDPCSTX_PHY_CNTL5                                                                   0x2af5
297 #define mmRDPCSTX2_RDPCSTX_PHY_CNTL5_BASE_IDX                                                          2
298 #define mmRDPCSTX2_RDPCSTX_PHY_CNTL6                                                                   0x2af6
299 #define mmRDPCSTX2_RDPCSTX_PHY_CNTL6_BASE_IDX                                                          2
300 #define mmRDPCSTX2_RDPCSTX_PHY_CNTL7                                                                   0x2af7
301 #define mmRDPCSTX2_RDPCSTX_PHY_CNTL7_BASE_IDX                                                          2
302 #define mmRDPCSTX2_RDPCSTX_PHY_CNTL8                                                                   0x2af8
303 #define mmRDPCSTX2_RDPCSTX_PHY_CNTL8_BASE_IDX                                                          2
304 #define mmRDPCSTX2_RDPCSTX_PHY_CNTL9                                                                   0x2af9
305 #define mmRDPCSTX2_RDPCSTX_PHY_CNTL9_BASE_IDX                                                          2
306 #define mmRDPCSTX2_RDPCSTX_PHY_CNTL10                                                                  0x2afa
307 #define mmRDPCSTX2_RDPCSTX_PHY_CNTL10_BASE_IDX                                                         2
308 #define mmRDPCSTX2_RDPCSTX_PHY_CNTL11                                                                  0x2afb
309 #define mmRDPCSTX2_RDPCSTX_PHY_CNTL11_BASE_IDX                                                         2
310 #define mmRDPCSTX2_RDPCSTX_PHY_CNTL12                                                                  0x2afc
311 #define mmRDPCSTX2_RDPCSTX_PHY_CNTL12_BASE_IDX                                                         2
312 #define mmRDPCSTX2_RDPCSTX_PHY_CNTL13                                                                  0x2afd
313 #define mmRDPCSTX2_RDPCSTX_PHY_CNTL13_BASE_IDX                                                         2
314 #define mmRDPCSTX2_RDPCSTX_PHY_CNTL14                                                                  0x2afe
315 #define mmRDPCSTX2_RDPCSTX_PHY_CNTL14_BASE_IDX                                                         2
316 #define mmRDPCSTX2_RDPCSTX_PHY_FUSE0                                                                   0x2aff
317 #define mmRDPCSTX2_RDPCSTX_PHY_FUSE0_BASE_IDX                                                          2
318 #define mmRDPCSTX2_RDPCSTX_PHY_FUSE1                                                                   0x2b00
319 #define mmRDPCSTX2_RDPCSTX_PHY_FUSE1_BASE_IDX                                                          2
320 #define mmRDPCSTX2_RDPCSTX_PHY_FUSE2                                                                   0x2b01
321 #define mmRDPCSTX2_RDPCSTX_PHY_FUSE2_BASE_IDX                                                          2
322 #define mmRDPCSTX2_RDPCSTX_PHY_FUSE3                                                                   0x2b02
323 #define mmRDPCSTX2_RDPCSTX_PHY_FUSE3_BASE_IDX                                                          2
324 #define mmRDPCSTX2_RDPCSTX_PHY_RX_LD_VAL                                                               0x2b03
325 #define mmRDPCSTX2_RDPCSTX_PHY_RX_LD_VAL_BASE_IDX                                                      2
326 #define mmRDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3                                                        0x2b04
327 #define mmRDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3_BASE_IDX                                               2
328 #define mmRDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL6                                                        0x2b05
329 #define mmRDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL6_BASE_IDX                                               2
330 #define mmRDPCSTX2_RDPCSTX_DPALT_CONTROL_REG                                                           0x2b06
331 #define mmRDPCSTX2_RDPCSTX_DPALT_CONTROL_REG_BASE_IDX                                                  2
332 #define mmRDPCSTX2_RDPCSTX_PHY_CNTL15                                                                  0x2b08
333 #define mmRDPCSTX2_RDPCSTX_PHY_CNTL15_BASE_IDX                                                         2
334 #define mmRDPCSTX2_RDPCSTX_PHY_CNTL16                                                                  0x2b09
335 #define mmRDPCSTX2_RDPCSTX_PHY_CNTL16_BASE_IDX                                                         2
336 #define mmRDPCSTX2_RDPCSTX_PHY_CNTL17                                                                  0x2b0a
337 #define mmRDPCSTX2_RDPCSTX_PHY_CNTL17_BASE_IDX                                                         2
338 #define mmRDPCSTX2_RDPCSTX_DEBUG_CONFIG2                                                               0x2b0b
339 #define mmRDPCSTX2_RDPCSTX_DEBUG_CONFIG2_BASE_IDX                                                      2
340 
341 
342 // addressBlock: dpcssys_dpcssys_cr2_dispdec
343 // base address: 0x6c0
344 #define mmDPCSSYS_CR2_DPCSSYS_CR_ADDR                                                                  0x2ae4
345 #define mmDPCSSYS_CR2_DPCSSYS_CR_ADDR_BASE_IDX                                                         2
346 #define mmDPCSSYS_CR2_DPCSSYS_CR_DATA                                                                  0x2ae5
347 #define mmDPCSSYS_CR2_DPCSSYS_CR_DATA_BASE_IDX                                                         2
348 
349 
350 // addressBlock: dpcssys_dpcs0_dpcstx3_dispdec
351 // base address: 0xa20
352 #define mmDPCSTX3_DPCSTX_TX_CLOCK_CNTL                                                                 0x2bb0
353 #define mmDPCSTX3_DPCSTX_TX_CLOCK_CNTL_BASE_IDX                                                        2
354 #define mmDPCSTX3_DPCSTX_TX_CNTL                                                                       0x2bb1
355 #define mmDPCSTX3_DPCSTX_TX_CNTL_BASE_IDX                                                              2
356 #define mmDPCSTX3_DPCSTX_CBUS_CNTL                                                                     0x2bb2
357 #define mmDPCSTX3_DPCSTX_CBUS_CNTL_BASE_IDX                                                            2
358 #define mmDPCSTX3_DPCSTX_INTERRUPT_CNTL                                                                0x2bb3
359 #define mmDPCSTX3_DPCSTX_INTERRUPT_CNTL_BASE_IDX                                                       2
360 #define mmDPCSTX3_DPCSTX_PLL_UPDATE_ADDR                                                               0x2bb4
361 #define mmDPCSTX3_DPCSTX_PLL_UPDATE_ADDR_BASE_IDX                                                      2
362 #define mmDPCSTX3_DPCSTX_PLL_UPDATE_DATA                                                               0x2bb5
363 #define mmDPCSTX3_DPCSTX_PLL_UPDATE_DATA_BASE_IDX                                                      2
364 #define mmDPCSTX3_DPCSTX_DEBUG_CONFIG                                                                  0x2bb6
365 #define mmDPCSTX3_DPCSTX_DEBUG_CONFIG_BASE_IDX                                                         2
366 
367 
368 // addressBlock: dpcssys_dpcs0_rdpcstx3_dispdec
369 // base address: 0xa20
370 #define mmRDPCSTX3_RDPCSTX_CNTL                                                                        0x2bb8
371 #define mmRDPCSTX3_RDPCSTX_CNTL_BASE_IDX                                                               2
372 #define mmRDPCSTX3_RDPCSTX_CLOCK_CNTL                                                                  0x2bb9
373 #define mmRDPCSTX3_RDPCSTX_CLOCK_CNTL_BASE_IDX                                                         2
374 #define mmRDPCSTX3_RDPCSTX_INTERRUPT_CONTROL                                                           0x2bba
375 #define mmRDPCSTX3_RDPCSTX_INTERRUPT_CONTROL_BASE_IDX                                                  2
376 #define mmRDPCSTX3_RDPCSTX_PLL_UPDATE_DATA                                                             0x2bbb
377 #define mmRDPCSTX3_RDPCSTX_PLL_UPDATE_DATA_BASE_IDX                                                    2
378 #define mmRDPCSTX3_RDPCS_TX_CR_ADDR                                                                    0x2bbc
379 #define mmRDPCSTX3_RDPCS_TX_CR_ADDR_BASE_IDX                                                           2
380 #define mmRDPCSTX3_RDPCS_TX_CR_DATA                                                                    0x2bbd
381 #define mmRDPCSTX3_RDPCS_TX_CR_DATA_BASE_IDX                                                           2
382 #define mmRDPCSTX3_RDPCS_TX_SRAM_CNTL                                                                  0x2bbe
383 #define mmRDPCSTX3_RDPCS_TX_SRAM_CNTL_BASE_IDX                                                         2
384 #define mmRDPCSTX3_RDPCSTX_SCRATCH                                                                     0x2bbf
385 #define mmRDPCSTX3_RDPCSTX_SCRATCH_BASE_IDX                                                            2
386 #define mmRDPCSTX3_RDPCSTX_SPARE                                                                       0x2bc0
387 #define mmRDPCSTX3_RDPCSTX_SPARE_BASE_IDX                                                              2
388 #define mmRDPCSTX3_RDPCSTX_CNTL2                                                                       0x2bc1
389 #define mmRDPCSTX3_RDPCSTX_CNTL2_BASE_IDX                                                              2
390 #define mmRDPCSTX3_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG                                                    0x2bc4
391 #define mmRDPCSTX3_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG_BASE_IDX                                           2
392 #define mmRDPCSTX3_RDPCSTX_DEBUG_CONFIG                                                                0x2bc5
393 #define mmRDPCSTX3_RDPCSTX_DEBUG_CONFIG_BASE_IDX                                                       2
394 #define mmRDPCSTX3_RDPCSTX_PHY_CNTL0                                                                   0x2bc8
395 #define mmRDPCSTX3_RDPCSTX_PHY_CNTL0_BASE_IDX                                                          2
396 #define mmRDPCSTX3_RDPCSTX_PHY_CNTL1                                                                   0x2bc9
397 #define mmRDPCSTX3_RDPCSTX_PHY_CNTL1_BASE_IDX                                                          2
398 #define mmRDPCSTX3_RDPCSTX_PHY_CNTL2                                                                   0x2bca
399 #define mmRDPCSTX3_RDPCSTX_PHY_CNTL2_BASE_IDX                                                          2
400 #define mmRDPCSTX3_RDPCSTX_PHY_CNTL3                                                                   0x2bcb
401 #define mmRDPCSTX3_RDPCSTX_PHY_CNTL3_BASE_IDX                                                          2
402 #define mmRDPCSTX3_RDPCSTX_PHY_CNTL4                                                                   0x2bcc
403 #define mmRDPCSTX3_RDPCSTX_PHY_CNTL4_BASE_IDX                                                          2
404 #define mmRDPCSTX3_RDPCSTX_PHY_CNTL5                                                                   0x2bcd
405 #define mmRDPCSTX3_RDPCSTX_PHY_CNTL5_BASE_IDX                                                          2
406 #define mmRDPCSTX3_RDPCSTX_PHY_CNTL6                                                                   0x2bce
407 #define mmRDPCSTX3_RDPCSTX_PHY_CNTL6_BASE_IDX                                                          2
408 #define mmRDPCSTX3_RDPCSTX_PHY_CNTL7                                                                   0x2bcf
409 #define mmRDPCSTX3_RDPCSTX_PHY_CNTL7_BASE_IDX                                                          2
410 #define mmRDPCSTX3_RDPCSTX_PHY_CNTL8                                                                   0x2bd0
411 #define mmRDPCSTX3_RDPCSTX_PHY_CNTL8_BASE_IDX                                                          2
412 #define mmRDPCSTX3_RDPCSTX_PHY_CNTL9                                                                   0x2bd1
413 #define mmRDPCSTX3_RDPCSTX_PHY_CNTL9_BASE_IDX                                                          2
414 #define mmRDPCSTX3_RDPCSTX_PHY_CNTL10                                                                  0x2bd2
415 #define mmRDPCSTX3_RDPCSTX_PHY_CNTL10_BASE_IDX                                                         2
416 #define mmRDPCSTX3_RDPCSTX_PHY_CNTL11                                                                  0x2bd3
417 #define mmRDPCSTX3_RDPCSTX_PHY_CNTL11_BASE_IDX                                                         2
418 #define mmRDPCSTX3_RDPCSTX_PHY_CNTL12                                                                  0x2bd4
419 #define mmRDPCSTX3_RDPCSTX_PHY_CNTL12_BASE_IDX                                                         2
420 #define mmRDPCSTX3_RDPCSTX_PHY_CNTL13                                                                  0x2bd5
421 #define mmRDPCSTX3_RDPCSTX_PHY_CNTL13_BASE_IDX                                                         2
422 #define mmRDPCSTX3_RDPCSTX_PHY_CNTL14                                                                  0x2bd6
423 #define mmRDPCSTX3_RDPCSTX_PHY_CNTL14_BASE_IDX                                                         2
424 #define mmRDPCSTX3_RDPCSTX_PHY_FUSE0                                                                   0x2bd7
425 #define mmRDPCSTX3_RDPCSTX_PHY_FUSE0_BASE_IDX                                                          2
426 #define mmRDPCSTX3_RDPCSTX_PHY_FUSE1                                                                   0x2bd8
427 #define mmRDPCSTX3_RDPCSTX_PHY_FUSE1_BASE_IDX                                                          2
428 #define mmRDPCSTX3_RDPCSTX_PHY_FUSE2                                                                   0x2bd9
429 #define mmRDPCSTX3_RDPCSTX_PHY_FUSE2_BASE_IDX                                                          2
430 #define mmRDPCSTX3_RDPCSTX_PHY_FUSE3                                                                   0x2bda
431 #define mmRDPCSTX3_RDPCSTX_PHY_FUSE3_BASE_IDX                                                          2
432 #define mmRDPCSTX3_RDPCSTX_PHY_RX_LD_VAL                                                               0x2bdb
433 #define mmRDPCSTX3_RDPCSTX_PHY_RX_LD_VAL_BASE_IDX                                                      2
434 #define mmRDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3                                                        0x2bdc
435 #define mmRDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3_BASE_IDX                                               2
436 #define mmRDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL6                                                        0x2bdd
437 #define mmRDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL6_BASE_IDX                                               2
438 #define mmRDPCSTX3_RDPCSTX_DPALT_CONTROL_REG                                                           0x2bde
439 #define mmRDPCSTX3_RDPCSTX_DPALT_CONTROL_REG_BASE_IDX                                                  2
440 #define mmRDPCSTX3_RDPCSTX_PHY_CNTL15                                                                  0x2be0
441 #define mmRDPCSTX3_RDPCSTX_PHY_CNTL15_BASE_IDX                                                         2
442 #define mmRDPCSTX3_RDPCSTX_PHY_CNTL16                                                                  0x2be1
443 #define mmRDPCSTX3_RDPCSTX_PHY_CNTL16_BASE_IDX                                                         2
444 #define mmRDPCSTX3_RDPCSTX_PHY_CNTL17                                                                  0x2be2
445 #define mmRDPCSTX3_RDPCSTX_PHY_CNTL17_BASE_IDX                                                         2
446 #define mmRDPCSTX3_RDPCSTX_DEBUG_CONFIG2                                                               0x2be3
447 #define mmRDPCSTX3_RDPCSTX_DEBUG_CONFIG2_BASE_IDX                                                      2
448 
449 
450 // addressBlock: dpcssys_dpcssys_cr3_dispdec
451 // base address: 0xa20
452 #define mmDPCSSYS_CR3_DPCSSYS_CR_ADDR                                                                  0x2bbc
453 #define mmDPCSSYS_CR3_DPCSSYS_CR_ADDR_BASE_IDX                                                         2
454 #define mmDPCSSYS_CR3_DPCSSYS_CR_DATA                                                                  0x2bbd
455 #define mmDPCSSYS_CR3_DPCSSYS_CR_DATA_BASE_IDX                                                         2
456 
457 
458 // addressBlock: dpcssys_dpcs0_dpcstx4_dispdec
459 // base address: 0xd80
460 #define mmDPCSTX4_DPCSTX_TX_CLOCK_CNTL                                                                 0x2c88
461 #define mmDPCSTX4_DPCSTX_TX_CLOCK_CNTL_BASE_IDX                                                        2
462 #define mmDPCSTX4_DPCSTX_TX_CNTL                                                                       0x2c89
463 #define mmDPCSTX4_DPCSTX_TX_CNTL_BASE_IDX                                                              2
464 #define mmDPCSTX4_DPCSTX_CBUS_CNTL                                                                     0x2c8a
465 #define mmDPCSTX4_DPCSTX_CBUS_CNTL_BASE_IDX                                                            2
466 #define mmDPCSTX4_DPCSTX_INTERRUPT_CNTL                                                                0x2c8b
467 #define mmDPCSTX4_DPCSTX_INTERRUPT_CNTL_BASE_IDX                                                       2
468 #define mmDPCSTX4_DPCSTX_PLL_UPDATE_ADDR                                                               0x2c8c
469 #define mmDPCSTX4_DPCSTX_PLL_UPDATE_ADDR_BASE_IDX                                                      2
470 #define mmDPCSTX4_DPCSTX_PLL_UPDATE_DATA                                                               0x2c8d
471 #define mmDPCSTX4_DPCSTX_PLL_UPDATE_DATA_BASE_IDX                                                      2
472 #define mmDPCSTX4_DPCSTX_DEBUG_CONFIG                                                                  0x2c8e
473 #define mmDPCSTX4_DPCSTX_DEBUG_CONFIG_BASE_IDX                                                         2
474 
475 
476 // addressBlock: dpcssys_dpcs0_rdpcstx4_dispdec
477 // base address: 0xd80
478 #define mmRDPCSTX4_RDPCSTX_CNTL                                                                        0x2c90
479 #define mmRDPCSTX4_RDPCSTX_CNTL_BASE_IDX                                                               2
480 #define mmRDPCSTX4_RDPCSTX_CLOCK_CNTL                                                                  0x2c91
481 #define mmRDPCSTX4_RDPCSTX_CLOCK_CNTL_BASE_IDX                                                         2
482 #define mmRDPCSTX4_RDPCSTX_INTERRUPT_CONTROL                                                           0x2c92
483 #define mmRDPCSTX4_RDPCSTX_INTERRUPT_CONTROL_BASE_IDX                                                  2
484 #define mmRDPCSTX4_RDPCSTX_PLL_UPDATE_DATA                                                             0x2c93
485 #define mmRDPCSTX4_RDPCSTX_PLL_UPDATE_DATA_BASE_IDX                                                    2
486 #define mmRDPCSTX4_RDPCS_TX_CR_ADDR                                                                    0x2c94
487 #define mmRDPCSTX4_RDPCS_TX_CR_ADDR_BASE_IDX                                                           2
488 #define mmRDPCSTX4_RDPCS_TX_CR_DATA                                                                    0x2c95
489 #define mmRDPCSTX4_RDPCS_TX_CR_DATA_BASE_IDX                                                           2
490 #define mmRDPCSTX4_RDPCS_TX_SRAM_CNTL                                                                  0x2c96
491 #define mmRDPCSTX4_RDPCS_TX_SRAM_CNTL_BASE_IDX                                                         2
492 #define mmRDPCSTX4_RDPCSTX_SCRATCH                                                                     0x2c97
493 #define mmRDPCSTX4_RDPCSTX_SCRATCH_BASE_IDX                                                            2
494 #define mmRDPCSTX4_RDPCSTX_SPARE                                                                       0x2c98
495 #define mmRDPCSTX4_RDPCSTX_SPARE_BASE_IDX                                                              2
496 #define mmRDPCSTX4_RDPCSTX_CNTL2                                                                       0x2c99
497 #define mmRDPCSTX4_RDPCSTX_CNTL2_BASE_IDX                                                              2
498 #define mmRDPCSTX4_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG                                                    0x2c9c
499 #define mmRDPCSTX4_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG_BASE_IDX                                           2
500 #define mmRDPCSTX4_RDPCSTX_DEBUG_CONFIG                                                                0x2c9d
501 #define mmRDPCSTX4_RDPCSTX_DEBUG_CONFIG_BASE_IDX                                                       2
502 #define mmRDPCSTX4_RDPCSTX_PHY_CNTL0                                                                   0x2ca0
503 #define mmRDPCSTX4_RDPCSTX_PHY_CNTL0_BASE_IDX                                                          2
504 #define mmRDPCSTX4_RDPCSTX_PHY_CNTL1                                                                   0x2ca1
505 #define mmRDPCSTX4_RDPCSTX_PHY_CNTL1_BASE_IDX                                                          2
506 #define mmRDPCSTX4_RDPCSTX_PHY_CNTL2                                                                   0x2ca2
507 #define mmRDPCSTX4_RDPCSTX_PHY_CNTL2_BASE_IDX                                                          2
508 #define mmRDPCSTX4_RDPCSTX_PHY_CNTL3                                                                   0x2ca3
509 #define mmRDPCSTX4_RDPCSTX_PHY_CNTL3_BASE_IDX                                                          2
510 #define mmRDPCSTX4_RDPCSTX_PHY_CNTL4                                                                   0x2ca4
511 #define mmRDPCSTX4_RDPCSTX_PHY_CNTL4_BASE_IDX                                                          2
512 #define mmRDPCSTX4_RDPCSTX_PHY_CNTL5                                                                   0x2ca5
513 #define mmRDPCSTX4_RDPCSTX_PHY_CNTL5_BASE_IDX                                                          2
514 #define mmRDPCSTX4_RDPCSTX_PHY_CNTL6                                                                   0x2ca6
515 #define mmRDPCSTX4_RDPCSTX_PHY_CNTL6_BASE_IDX                                                          2
516 #define mmRDPCSTX4_RDPCSTX_PHY_CNTL7                                                                   0x2ca7
517 #define mmRDPCSTX4_RDPCSTX_PHY_CNTL7_BASE_IDX                                                          2
518 #define mmRDPCSTX4_RDPCSTX_PHY_CNTL8                                                                   0x2ca8
519 #define mmRDPCSTX4_RDPCSTX_PHY_CNTL8_BASE_IDX                                                          2
520 #define mmRDPCSTX4_RDPCSTX_PHY_CNTL9                                                                   0x2ca9
521 #define mmRDPCSTX4_RDPCSTX_PHY_CNTL9_BASE_IDX                                                          2
522 #define mmRDPCSTX4_RDPCSTX_PHY_CNTL10                                                                  0x2caa
523 #define mmRDPCSTX4_RDPCSTX_PHY_CNTL10_BASE_IDX                                                         2
524 #define mmRDPCSTX4_RDPCSTX_PHY_CNTL11                                                                  0x2cab
525 #define mmRDPCSTX4_RDPCSTX_PHY_CNTL11_BASE_IDX                                                         2
526 #define mmRDPCSTX4_RDPCSTX_PHY_CNTL12                                                                  0x2cac
527 #define mmRDPCSTX4_RDPCSTX_PHY_CNTL12_BASE_IDX                                                         2
528 #define mmRDPCSTX4_RDPCSTX_PHY_CNTL13                                                                  0x2cad
529 #define mmRDPCSTX4_RDPCSTX_PHY_CNTL13_BASE_IDX                                                         2
530 #define mmRDPCSTX4_RDPCSTX_PHY_CNTL14                                                                  0x2cae
531 #define mmRDPCSTX4_RDPCSTX_PHY_CNTL14_BASE_IDX                                                         2
532 #define mmRDPCSTX4_RDPCSTX_PHY_FUSE0                                                                   0x2caf
533 #define mmRDPCSTX4_RDPCSTX_PHY_FUSE0_BASE_IDX                                                          2
534 #define mmRDPCSTX4_RDPCSTX_PHY_FUSE1                                                                   0x2cb0
535 #define mmRDPCSTX4_RDPCSTX_PHY_FUSE1_BASE_IDX                                                          2
536 #define mmRDPCSTX4_RDPCSTX_PHY_FUSE2                                                                   0x2cb1
537 #define mmRDPCSTX4_RDPCSTX_PHY_FUSE2_BASE_IDX                                                          2
538 #define mmRDPCSTX4_RDPCSTX_PHY_FUSE3                                                                   0x2cb2
539 #define mmRDPCSTX4_RDPCSTX_PHY_FUSE3_BASE_IDX                                                          2
540 #define mmRDPCSTX4_RDPCSTX_PHY_RX_LD_VAL                                                               0x2cb3
541 #define mmRDPCSTX4_RDPCSTX_PHY_RX_LD_VAL_BASE_IDX                                                      2
542 #define mmRDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3                                                        0x2cb4
543 #define mmRDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3_BASE_IDX                                               2
544 #define mmRDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL6                                                        0x2cb5
545 #define mmRDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL6_BASE_IDX                                               2
546 #define mmRDPCSTX4_RDPCSTX_DPALT_CONTROL_REG                                                           0x2cb6
547 #define mmRDPCSTX4_RDPCSTX_DPALT_CONTROL_REG_BASE_IDX                                                  2
548 #define mmRDPCSTX4_RDPCSTX_PHY_CNTL15                                                                  0x2cb8
549 #define mmRDPCSTX4_RDPCSTX_PHY_CNTL15_BASE_IDX                                                         2
550 #define mmRDPCSTX4_RDPCSTX_PHY_CNTL16                                                                  0x2cb9
551 #define mmRDPCSTX4_RDPCSTX_PHY_CNTL16_BASE_IDX                                                         2
552 #define mmRDPCSTX4_RDPCSTX_PHY_CNTL17                                                                  0x2cba
553 #define mmRDPCSTX4_RDPCSTX_PHY_CNTL17_BASE_IDX                                                         2
554 #define mmRDPCSTX4_RDPCSTX_DEBUG_CONFIG2                                                               0x2cbb
555 #define mmRDPCSTX4_RDPCSTX_DEBUG_CONFIG2_BASE_IDX                                                      2
556 
557 
558 // addressBlock: dpcssys_dpcssys_cr4_dispdec
559 // base address: 0xd80
560 #define mmDPCSSYS_CR4_DPCSSYS_CR_ADDR                                                                  0x2c94
561 #define mmDPCSSYS_CR4_DPCSSYS_CR_ADDR_BASE_IDX                                                         2
562 #define mmDPCSSYS_CR4_DPCSSYS_CR_DATA                                                                  0x2c95
563 #define mmDPCSSYS_CR4_DPCSSYS_CR_DATA_BASE_IDX                                                         2
564 
565 #endif
566