16fdcba32SRoman Li /* 26fdcba32SRoman Li * Copyright (C) 2019 Advanced Micro Devices, Inc. 36fdcba32SRoman Li * 46fdcba32SRoman Li * Permission is hereby granted, free of charge, to any person obtaining a 56fdcba32SRoman Li * copy of this software and associated documentation files (the "Software"), 66fdcba32SRoman Li * to deal in the Software without restriction, including without limitation 76fdcba32SRoman Li * the rights to use, copy, modify, merge, publish, distribute, sublicense, 86fdcba32SRoman Li * and/or sell copies of the Software, and to permit persons to whom the 96fdcba32SRoman Li * Software is furnished to do so, subject to the following conditions: 106fdcba32SRoman Li * 116fdcba32SRoman Li * The above copyright notice and this permission notice shall be included 126fdcba32SRoman Li * in all copies or substantial portions of the Software. 136fdcba32SRoman Li * 146fdcba32SRoman Li * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 156fdcba32SRoman Li * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 166fdcba32SRoman Li * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 176fdcba32SRoman Li * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN 186fdcba32SRoman Li * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 196fdcba32SRoman Li * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 206fdcba32SRoman Li */ 216fdcba32SRoman Li #ifndef _dpcs_2_1_0_OFFSET_HEADER 226fdcba32SRoman Li #define _dpcs_2_1_0_OFFSET_HEADER 236fdcba32SRoman Li 246fdcba32SRoman Li 256fdcba32SRoman Li 266fdcba32SRoman Li // addressBlock: dpcssys_dpcs0_dpcstx0_dispdec 276fdcba32SRoman Li // base address: 0x0 286fdcba32SRoman Li #define mmDPCSTX0_DPCSTX_TX_CLOCK_CNTL 0x2928 296fdcba32SRoman Li #define mmDPCSTX0_DPCSTX_TX_CLOCK_CNTL_BASE_IDX 2 306fdcba32SRoman Li #define mmDPCSTX0_DPCSTX_TX_CNTL 0x2929 316fdcba32SRoman Li #define mmDPCSTX0_DPCSTX_TX_CNTL_BASE_IDX 2 326fdcba32SRoman Li #define mmDPCSTX0_DPCSTX_CBUS_CNTL 0x292a 336fdcba32SRoman Li #define mmDPCSTX0_DPCSTX_CBUS_CNTL_BASE_IDX 2 346fdcba32SRoman Li #define mmDPCSTX0_DPCSTX_INTERRUPT_CNTL 0x292b 356fdcba32SRoman Li #define mmDPCSTX0_DPCSTX_INTERRUPT_CNTL_BASE_IDX 2 366fdcba32SRoman Li #define mmDPCSTX0_DPCSTX_PLL_UPDATE_ADDR 0x292c 376fdcba32SRoman Li #define mmDPCSTX0_DPCSTX_PLL_UPDATE_ADDR_BASE_IDX 2 386fdcba32SRoman Li #define mmDPCSTX0_DPCSTX_PLL_UPDATE_DATA 0x292d 396fdcba32SRoman Li #define mmDPCSTX0_DPCSTX_PLL_UPDATE_DATA_BASE_IDX 2 406fdcba32SRoman Li #define mmDPCSTX0_DPCSTX_DEBUG_CONFIG 0x292e 416fdcba32SRoman Li #define mmDPCSTX0_DPCSTX_DEBUG_CONFIG_BASE_IDX 2 426fdcba32SRoman Li 436fdcba32SRoman Li 446fdcba32SRoman Li // addressBlock: dpcssys_dpcs0_rdpcstx0_dispdec 456fdcba32SRoman Li // base address: 0x0 466fdcba32SRoman Li #define mmRDPCSTX0_RDPCSTX_CNTL 0x2930 476fdcba32SRoman Li #define mmRDPCSTX0_RDPCSTX_CNTL_BASE_IDX 2 486fdcba32SRoman Li #define mmRDPCSTX0_RDPCSTX_CLOCK_CNTL 0x2931 496fdcba32SRoman Li #define mmRDPCSTX0_RDPCSTX_CLOCK_CNTL_BASE_IDX 2 506fdcba32SRoman Li #define mmRDPCSTX0_RDPCSTX_INTERRUPT_CONTROL 0x2932 516fdcba32SRoman Li #define mmRDPCSTX0_RDPCSTX_INTERRUPT_CONTROL_BASE_IDX 2 526fdcba32SRoman Li #define mmRDPCSTX0_RDPCSTX_PLL_UPDATE_DATA 0x2933 536fdcba32SRoman Li #define mmRDPCSTX0_RDPCSTX_PLL_UPDATE_DATA_BASE_IDX 2 546fdcba32SRoman Li #define mmRDPCSTX0_RDPCS_TX_CR_ADDR 0x2934 556fdcba32SRoman Li #define mmRDPCSTX0_RDPCS_TX_CR_ADDR_BASE_IDX 2 566fdcba32SRoman Li #define mmRDPCSTX0_RDPCS_TX_CR_DATA 0x2935 576fdcba32SRoman Li #define mmRDPCSTX0_RDPCS_TX_CR_DATA_BASE_IDX 2 586fdcba32SRoman Li #define mmRDPCSTX0_RDPCS_TX_SRAM_CNTL 0x2936 596fdcba32SRoman Li #define mmRDPCSTX0_RDPCS_TX_SRAM_CNTL_BASE_IDX 2 606fdcba32SRoman Li #define mmRDPCSTX0_RDPCSTX_SCRATCH 0x2937 616fdcba32SRoman Li #define mmRDPCSTX0_RDPCSTX_SCRATCH_BASE_IDX 2 626fdcba32SRoman Li #define mmRDPCSTX0_RDPCSTX_SPARE 0x2938 636fdcba32SRoman Li #define mmRDPCSTX0_RDPCSTX_SPARE_BASE_IDX 2 646fdcba32SRoman Li #define mmRDPCSTX0_RDPCSTX_CNTL2 0x2939 656fdcba32SRoman Li #define mmRDPCSTX0_RDPCSTX_CNTL2_BASE_IDX 2 666fdcba32SRoman Li #define mmRDPCSTX0_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG 0x293c 676fdcba32SRoman Li #define mmRDPCSTX0_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG_BASE_IDX 2 686fdcba32SRoman Li #define mmRDPCSTX0_RDPCSTX_DEBUG_CONFIG 0x293d 696fdcba32SRoman Li #define mmRDPCSTX0_RDPCSTX_DEBUG_CONFIG_BASE_IDX 2 706fdcba32SRoman Li #define mmRDPCSTX0_RDPCSTX_PHY_CNTL0 0x2940 716fdcba32SRoman Li #define mmRDPCSTX0_RDPCSTX_PHY_CNTL0_BASE_IDX 2 726fdcba32SRoman Li #define mmRDPCSTX0_RDPCSTX_PHY_CNTL1 0x2941 736fdcba32SRoman Li #define mmRDPCSTX0_RDPCSTX_PHY_CNTL1_BASE_IDX 2 746fdcba32SRoman Li #define mmRDPCSTX0_RDPCSTX_PHY_CNTL2 0x2942 756fdcba32SRoman Li #define mmRDPCSTX0_RDPCSTX_PHY_CNTL2_BASE_IDX 2 766fdcba32SRoman Li #define mmRDPCSTX0_RDPCSTX_PHY_CNTL3 0x2943 776fdcba32SRoman Li #define mmRDPCSTX0_RDPCSTX_PHY_CNTL3_BASE_IDX 2 786fdcba32SRoman Li #define mmRDPCSTX0_RDPCSTX_PHY_CNTL4 0x2944 796fdcba32SRoman Li #define mmRDPCSTX0_RDPCSTX_PHY_CNTL4_BASE_IDX 2 806fdcba32SRoman Li #define mmRDPCSTX0_RDPCSTX_PHY_CNTL5 0x2945 816fdcba32SRoman Li #define mmRDPCSTX0_RDPCSTX_PHY_CNTL5_BASE_IDX 2 826fdcba32SRoman Li #define mmRDPCSTX0_RDPCSTX_PHY_CNTL6 0x2946 836fdcba32SRoman Li #define mmRDPCSTX0_RDPCSTX_PHY_CNTL6_BASE_IDX 2 846fdcba32SRoman Li #define mmRDPCSTX0_RDPCSTX_PHY_CNTL7 0x2947 856fdcba32SRoman Li #define mmRDPCSTX0_RDPCSTX_PHY_CNTL7_BASE_IDX 2 866fdcba32SRoman Li #define mmRDPCSTX0_RDPCSTX_PHY_CNTL8 0x2948 876fdcba32SRoman Li #define mmRDPCSTX0_RDPCSTX_PHY_CNTL8_BASE_IDX 2 886fdcba32SRoman Li #define mmRDPCSTX0_RDPCSTX_PHY_CNTL9 0x2949 896fdcba32SRoman Li #define mmRDPCSTX0_RDPCSTX_PHY_CNTL9_BASE_IDX 2 906fdcba32SRoman Li #define mmRDPCSTX0_RDPCSTX_PHY_CNTL10 0x294a 916fdcba32SRoman Li #define mmRDPCSTX0_RDPCSTX_PHY_CNTL10_BASE_IDX 2 926fdcba32SRoman Li #define mmRDPCSTX0_RDPCSTX_PHY_CNTL11 0x294b 936fdcba32SRoman Li #define mmRDPCSTX0_RDPCSTX_PHY_CNTL11_BASE_IDX 2 946fdcba32SRoman Li #define mmRDPCSTX0_RDPCSTX_PHY_CNTL12 0x294c 956fdcba32SRoman Li #define mmRDPCSTX0_RDPCSTX_PHY_CNTL12_BASE_IDX 2 966fdcba32SRoman Li #define mmRDPCSTX0_RDPCSTX_PHY_CNTL13 0x294d 976fdcba32SRoman Li #define mmRDPCSTX0_RDPCSTX_PHY_CNTL13_BASE_IDX 2 986fdcba32SRoman Li #define mmRDPCSTX0_RDPCSTX_PHY_CNTL14 0x294e 996fdcba32SRoman Li #define mmRDPCSTX0_RDPCSTX_PHY_CNTL14_BASE_IDX 2 1006fdcba32SRoman Li #define mmRDPCSTX0_RDPCSTX_PHY_FUSE0 0x294f 1016fdcba32SRoman Li #define mmRDPCSTX0_RDPCSTX_PHY_FUSE0_BASE_IDX 2 1026fdcba32SRoman Li #define mmRDPCSTX0_RDPCSTX_PHY_FUSE1 0x2950 1036fdcba32SRoman Li #define mmRDPCSTX0_RDPCSTX_PHY_FUSE1_BASE_IDX 2 1046fdcba32SRoman Li #define mmRDPCSTX0_RDPCSTX_PHY_FUSE2 0x2951 1056fdcba32SRoman Li #define mmRDPCSTX0_RDPCSTX_PHY_FUSE2_BASE_IDX 2 1066fdcba32SRoman Li #define mmRDPCSTX0_RDPCSTX_PHY_FUSE3 0x2952 1076fdcba32SRoman Li #define mmRDPCSTX0_RDPCSTX_PHY_FUSE3_BASE_IDX 2 1086fdcba32SRoman Li #define mmRDPCSTX0_RDPCSTX_PHY_RX_LD_VAL 0x2953 1096fdcba32SRoman Li #define mmRDPCSTX0_RDPCSTX_PHY_RX_LD_VAL_BASE_IDX 2 1106fdcba32SRoman Li #define mmRDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3 0x2954 1116fdcba32SRoman Li #define mmRDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3_BASE_IDX 2 1126fdcba32SRoman Li #define mmRDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6 0x2955 1136fdcba32SRoman Li #define mmRDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6_BASE_IDX 2 1146fdcba32SRoman Li #define mmRDPCSTX0_RDPCSTX_DPALT_CONTROL_REG 0x2956 1156fdcba32SRoman Li #define mmRDPCSTX0_RDPCSTX_DPALT_CONTROL_REG_BASE_IDX 2 1166fdcba32SRoman Li #define mmRDPCSTX0_RDPCSTX_PHY_CNTL15 0x2958 1176fdcba32SRoman Li #define mmRDPCSTX0_RDPCSTX_PHY_CNTL15_BASE_IDX 2 1186fdcba32SRoman Li #define mmRDPCSTX0_RDPCSTX_PHY_CNTL16 0x2959 1196fdcba32SRoman Li #define mmRDPCSTX0_RDPCSTX_PHY_CNTL16_BASE_IDX 2 1206fdcba32SRoman Li #define mmRDPCSTX0_RDPCSTX_PHY_CNTL17 0x295a 1216fdcba32SRoman Li #define mmRDPCSTX0_RDPCSTX_PHY_CNTL17_BASE_IDX 2 1226fdcba32SRoman Li #define mmRDPCSTX0_RDPCSTX_DEBUG_CONFIG2 0x295b 1236fdcba32SRoman Li #define mmRDPCSTX0_RDPCSTX_DEBUG_CONFIG2_BASE_IDX 2 1246fdcba32SRoman Li 1256fdcba32SRoman Li 1266fdcba32SRoman Li // addressBlock: dpcssys_dpcssys_cr0_dispdec 1276fdcba32SRoman Li // base address: 0x0 1286fdcba32SRoman Li #define mmDPCSSYS_CR0_DPCSSYS_CR_ADDR 0x2934 1296fdcba32SRoman Li #define mmDPCSSYS_CR0_DPCSSYS_CR_ADDR_BASE_IDX 2 1306fdcba32SRoman Li #define mmDPCSSYS_CR0_DPCSSYS_CR_DATA 0x2935 1316fdcba32SRoman Li #define mmDPCSSYS_CR0_DPCSSYS_CR_DATA_BASE_IDX 2 1326fdcba32SRoman Li 1336fdcba32SRoman Li 1346fdcba32SRoman Li // addressBlock: dpcssys_dpcs0_dpcstx1_dispdec 1356fdcba32SRoman Li // base address: 0x360 1366fdcba32SRoman Li #define mmDPCSTX1_DPCSTX_TX_CLOCK_CNTL 0x2a00 1376fdcba32SRoman Li #define mmDPCSTX1_DPCSTX_TX_CLOCK_CNTL_BASE_IDX 2 1386fdcba32SRoman Li #define mmDPCSTX1_DPCSTX_TX_CNTL 0x2a01 1396fdcba32SRoman Li #define mmDPCSTX1_DPCSTX_TX_CNTL_BASE_IDX 2 1406fdcba32SRoman Li #define mmDPCSTX1_DPCSTX_CBUS_CNTL 0x2a02 1416fdcba32SRoman Li #define mmDPCSTX1_DPCSTX_CBUS_CNTL_BASE_IDX 2 1426fdcba32SRoman Li #define mmDPCSTX1_DPCSTX_INTERRUPT_CNTL 0x2a03 1436fdcba32SRoman Li #define mmDPCSTX1_DPCSTX_INTERRUPT_CNTL_BASE_IDX 2 1446fdcba32SRoman Li #define mmDPCSTX1_DPCSTX_PLL_UPDATE_ADDR 0x2a04 1456fdcba32SRoman Li #define mmDPCSTX1_DPCSTX_PLL_UPDATE_ADDR_BASE_IDX 2 1466fdcba32SRoman Li #define mmDPCSTX1_DPCSTX_PLL_UPDATE_DATA 0x2a05 1476fdcba32SRoman Li #define mmDPCSTX1_DPCSTX_PLL_UPDATE_DATA_BASE_IDX 2 1486fdcba32SRoman Li #define mmDPCSTX1_DPCSTX_DEBUG_CONFIG 0x2a06 1496fdcba32SRoman Li #define mmDPCSTX1_DPCSTX_DEBUG_CONFIG_BASE_IDX 2 1506fdcba32SRoman Li 1516fdcba32SRoman Li 1526fdcba32SRoman Li // addressBlock: dpcssys_dpcs0_rdpcstx1_dispdec 1536fdcba32SRoman Li // base address: 0x360 1546fdcba32SRoman Li #define mmRDPCSTX1_RDPCSTX_CNTL 0x2a08 1556fdcba32SRoman Li #define mmRDPCSTX1_RDPCSTX_CNTL_BASE_IDX 2 1566fdcba32SRoman Li #define mmRDPCSTX1_RDPCSTX_CLOCK_CNTL 0x2a09 1576fdcba32SRoman Li #define mmRDPCSTX1_RDPCSTX_CLOCK_CNTL_BASE_IDX 2 1586fdcba32SRoman Li #define mmRDPCSTX1_RDPCSTX_INTERRUPT_CONTROL 0x2a0a 1596fdcba32SRoman Li #define mmRDPCSTX1_RDPCSTX_INTERRUPT_CONTROL_BASE_IDX 2 1606fdcba32SRoman Li #define mmRDPCSTX1_RDPCSTX_PLL_UPDATE_DATA 0x2a0b 1616fdcba32SRoman Li #define mmRDPCSTX1_RDPCSTX_PLL_UPDATE_DATA_BASE_IDX 2 1626fdcba32SRoman Li #define mmRDPCSTX1_RDPCS_TX_CR_ADDR 0x2a0c 1636fdcba32SRoman Li #define mmRDPCSTX1_RDPCS_TX_CR_ADDR_BASE_IDX 2 1646fdcba32SRoman Li #define mmRDPCSTX1_RDPCS_TX_CR_DATA 0x2a0d 1656fdcba32SRoman Li #define mmRDPCSTX1_RDPCS_TX_CR_DATA_BASE_IDX 2 1666fdcba32SRoman Li #define mmRDPCSTX1_RDPCS_TX_SRAM_CNTL 0x2a0e 1676fdcba32SRoman Li #define mmRDPCSTX1_RDPCS_TX_SRAM_CNTL_BASE_IDX 2 1686fdcba32SRoman Li #define mmRDPCSTX1_RDPCSTX_SCRATCH 0x2a0f 1696fdcba32SRoman Li #define mmRDPCSTX1_RDPCSTX_SCRATCH_BASE_IDX 2 1706fdcba32SRoman Li #define mmRDPCSTX1_RDPCSTX_SPARE 0x2a10 1716fdcba32SRoman Li #define mmRDPCSTX1_RDPCSTX_SPARE_BASE_IDX 2 1726fdcba32SRoman Li #define mmRDPCSTX1_RDPCSTX_CNTL2 0x2a11 1736fdcba32SRoman Li #define mmRDPCSTX1_RDPCSTX_CNTL2_BASE_IDX 2 1746fdcba32SRoman Li #define mmRDPCSTX1_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG 0x2a14 1756fdcba32SRoman Li #define mmRDPCSTX1_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG_BASE_IDX 2 1766fdcba32SRoman Li #define mmRDPCSTX1_RDPCSTX_DEBUG_CONFIG 0x2a15 1776fdcba32SRoman Li #define mmRDPCSTX1_RDPCSTX_DEBUG_CONFIG_BASE_IDX 2 1786fdcba32SRoman Li #define mmRDPCSTX1_RDPCSTX_PHY_CNTL0 0x2a18 1796fdcba32SRoman Li #define mmRDPCSTX1_RDPCSTX_PHY_CNTL0_BASE_IDX 2 1806fdcba32SRoman Li #define mmRDPCSTX1_RDPCSTX_PHY_CNTL1 0x2a19 1816fdcba32SRoman Li #define mmRDPCSTX1_RDPCSTX_PHY_CNTL1_BASE_IDX 2 1826fdcba32SRoman Li #define mmRDPCSTX1_RDPCSTX_PHY_CNTL2 0x2a1a 1836fdcba32SRoman Li #define mmRDPCSTX1_RDPCSTX_PHY_CNTL2_BASE_IDX 2 1846fdcba32SRoman Li #define mmRDPCSTX1_RDPCSTX_PHY_CNTL3 0x2a1b 1856fdcba32SRoman Li #define mmRDPCSTX1_RDPCSTX_PHY_CNTL3_BASE_IDX 2 1866fdcba32SRoman Li #define mmRDPCSTX1_RDPCSTX_PHY_CNTL4 0x2a1c 1876fdcba32SRoman Li #define mmRDPCSTX1_RDPCSTX_PHY_CNTL4_BASE_IDX 2 1886fdcba32SRoman Li #define mmRDPCSTX1_RDPCSTX_PHY_CNTL5 0x2a1d 1896fdcba32SRoman Li #define mmRDPCSTX1_RDPCSTX_PHY_CNTL5_BASE_IDX 2 1906fdcba32SRoman Li #define mmRDPCSTX1_RDPCSTX_PHY_CNTL6 0x2a1e 1916fdcba32SRoman Li #define mmRDPCSTX1_RDPCSTX_PHY_CNTL6_BASE_IDX 2 1926fdcba32SRoman Li #define mmRDPCSTX1_RDPCSTX_PHY_CNTL7 0x2a1f 1936fdcba32SRoman Li #define mmRDPCSTX1_RDPCSTX_PHY_CNTL7_BASE_IDX 2 1946fdcba32SRoman Li #define mmRDPCSTX1_RDPCSTX_PHY_CNTL8 0x2a20 1956fdcba32SRoman Li #define mmRDPCSTX1_RDPCSTX_PHY_CNTL8_BASE_IDX 2 1966fdcba32SRoman Li #define mmRDPCSTX1_RDPCSTX_PHY_CNTL9 0x2a21 1976fdcba32SRoman Li #define mmRDPCSTX1_RDPCSTX_PHY_CNTL9_BASE_IDX 2 1986fdcba32SRoman Li #define mmRDPCSTX1_RDPCSTX_PHY_CNTL10 0x2a22 1996fdcba32SRoman Li #define mmRDPCSTX1_RDPCSTX_PHY_CNTL10_BASE_IDX 2 2006fdcba32SRoman Li #define mmRDPCSTX1_RDPCSTX_PHY_CNTL11 0x2a23 2016fdcba32SRoman Li #define mmRDPCSTX1_RDPCSTX_PHY_CNTL11_BASE_IDX 2 2026fdcba32SRoman Li #define mmRDPCSTX1_RDPCSTX_PHY_CNTL12 0x2a24 2036fdcba32SRoman Li #define mmRDPCSTX1_RDPCSTX_PHY_CNTL12_BASE_IDX 2 2046fdcba32SRoman Li #define mmRDPCSTX1_RDPCSTX_PHY_CNTL13 0x2a25 2056fdcba32SRoman Li #define mmRDPCSTX1_RDPCSTX_PHY_CNTL13_BASE_IDX 2 2066fdcba32SRoman Li #define mmRDPCSTX1_RDPCSTX_PHY_CNTL14 0x2a26 2076fdcba32SRoman Li #define mmRDPCSTX1_RDPCSTX_PHY_CNTL14_BASE_IDX 2 2086fdcba32SRoman Li #define mmRDPCSTX1_RDPCSTX_PHY_FUSE0 0x2a27 2096fdcba32SRoman Li #define mmRDPCSTX1_RDPCSTX_PHY_FUSE0_BASE_IDX 2 2106fdcba32SRoman Li #define mmRDPCSTX1_RDPCSTX_PHY_FUSE1 0x2a28 2116fdcba32SRoman Li #define mmRDPCSTX1_RDPCSTX_PHY_FUSE1_BASE_IDX 2 2126fdcba32SRoman Li #define mmRDPCSTX1_RDPCSTX_PHY_FUSE2 0x2a29 2136fdcba32SRoman Li #define mmRDPCSTX1_RDPCSTX_PHY_FUSE2_BASE_IDX 2 2146fdcba32SRoman Li #define mmRDPCSTX1_RDPCSTX_PHY_FUSE3 0x2a2a 2156fdcba32SRoman Li #define mmRDPCSTX1_RDPCSTX_PHY_FUSE3_BASE_IDX 2 2166fdcba32SRoman Li #define mmRDPCSTX1_RDPCSTX_PHY_RX_LD_VAL 0x2a2b 2176fdcba32SRoman Li #define mmRDPCSTX1_RDPCSTX_PHY_RX_LD_VAL_BASE_IDX 2 2186fdcba32SRoman Li #define mmRDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3 0x2a2c 2196fdcba32SRoman Li #define mmRDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3_BASE_IDX 2 2206fdcba32SRoman Li #define mmRDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6 0x2a2d 2216fdcba32SRoman Li #define mmRDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6_BASE_IDX 2 2226fdcba32SRoman Li #define mmRDPCSTX1_RDPCSTX_DPALT_CONTROL_REG 0x2a2e 2236fdcba32SRoman Li #define mmRDPCSTX1_RDPCSTX_DPALT_CONTROL_REG_BASE_IDX 2 2246fdcba32SRoman Li #define mmRDPCSTX1_RDPCSTX_PHY_CNTL15 0x2a30 2256fdcba32SRoman Li #define mmRDPCSTX1_RDPCSTX_PHY_CNTL15_BASE_IDX 2 2266fdcba32SRoman Li #define mmRDPCSTX1_RDPCSTX_PHY_CNTL16 0x2a31 2276fdcba32SRoman Li #define mmRDPCSTX1_RDPCSTX_PHY_CNTL16_BASE_IDX 2 2286fdcba32SRoman Li #define mmRDPCSTX1_RDPCSTX_PHY_CNTL17 0x2a32 2296fdcba32SRoman Li #define mmRDPCSTX1_RDPCSTX_PHY_CNTL17_BASE_IDX 2 2306fdcba32SRoman Li #define mmRDPCSTX1_RDPCSTX_DEBUG_CONFIG2 0x2a33 2316fdcba32SRoman Li #define mmRDPCSTX1_RDPCSTX_DEBUG_CONFIG2_BASE_IDX 2 2326fdcba32SRoman Li 2336fdcba32SRoman Li 2346fdcba32SRoman Li // addressBlock: dpcssys_dpcssys_cr1_dispdec 2356fdcba32SRoman Li // base address: 0x360 2366fdcba32SRoman Li #define mmDPCSSYS_CR1_DPCSSYS_CR_ADDR 0x2a0c 2376fdcba32SRoman Li #define mmDPCSSYS_CR1_DPCSSYS_CR_ADDR_BASE_IDX 2 2386fdcba32SRoman Li #define mmDPCSSYS_CR1_DPCSSYS_CR_DATA 0x2a0d 2396fdcba32SRoman Li #define mmDPCSSYS_CR1_DPCSSYS_CR_DATA_BASE_IDX 2 2406fdcba32SRoman Li 2416fdcba32SRoman Li 2426fdcba32SRoman Li // addressBlock: dpcssys_dpcs0_dpcstx2_dispdec 2436fdcba32SRoman Li // base address: 0x6c0 2446fdcba32SRoman Li #define mmDPCSTX2_DPCSTX_TX_CLOCK_CNTL 0x2ad8 2456fdcba32SRoman Li #define mmDPCSTX2_DPCSTX_TX_CLOCK_CNTL_BASE_IDX 2 2466fdcba32SRoman Li #define mmDPCSTX2_DPCSTX_TX_CNTL 0x2ad9 2476fdcba32SRoman Li #define mmDPCSTX2_DPCSTX_TX_CNTL_BASE_IDX 2 2486fdcba32SRoman Li #define mmDPCSTX2_DPCSTX_CBUS_CNTL 0x2ada 2496fdcba32SRoman Li #define mmDPCSTX2_DPCSTX_CBUS_CNTL_BASE_IDX 2 2506fdcba32SRoman Li #define mmDPCSTX2_DPCSTX_INTERRUPT_CNTL 0x2adb 2516fdcba32SRoman Li #define mmDPCSTX2_DPCSTX_INTERRUPT_CNTL_BASE_IDX 2 2526fdcba32SRoman Li #define mmDPCSTX2_DPCSTX_PLL_UPDATE_ADDR 0x2adc 2536fdcba32SRoman Li #define mmDPCSTX2_DPCSTX_PLL_UPDATE_ADDR_BASE_IDX 2 2546fdcba32SRoman Li #define mmDPCSTX2_DPCSTX_PLL_UPDATE_DATA 0x2add 2556fdcba32SRoman Li #define mmDPCSTX2_DPCSTX_PLL_UPDATE_DATA_BASE_IDX 2 2566fdcba32SRoman Li #define mmDPCSTX2_DPCSTX_DEBUG_CONFIG 0x2ade 2576fdcba32SRoman Li #define mmDPCSTX2_DPCSTX_DEBUG_CONFIG_BASE_IDX 2 2586fdcba32SRoman Li 2596fdcba32SRoman Li 2606fdcba32SRoman Li // addressBlock: dpcssys_dpcs0_rdpcstx2_dispdec 2616fdcba32SRoman Li // base address: 0x6c0 2626fdcba32SRoman Li #define mmRDPCSTX2_RDPCSTX_CNTL 0x2ae0 2636fdcba32SRoman Li #define mmRDPCSTX2_RDPCSTX_CNTL_BASE_IDX 2 2646fdcba32SRoman Li #define mmRDPCSTX2_RDPCSTX_CLOCK_CNTL 0x2ae1 2656fdcba32SRoman Li #define mmRDPCSTX2_RDPCSTX_CLOCK_CNTL_BASE_IDX 2 2666fdcba32SRoman Li #define mmRDPCSTX2_RDPCSTX_INTERRUPT_CONTROL 0x2ae2 2676fdcba32SRoman Li #define mmRDPCSTX2_RDPCSTX_INTERRUPT_CONTROL_BASE_IDX 2 2686fdcba32SRoman Li #define mmRDPCSTX2_RDPCSTX_PLL_UPDATE_DATA 0x2ae3 2696fdcba32SRoman Li #define mmRDPCSTX2_RDPCSTX_PLL_UPDATE_DATA_BASE_IDX 2 2706fdcba32SRoman Li #define mmRDPCSTX2_RDPCS_TX_CR_ADDR 0x2ae4 2716fdcba32SRoman Li #define mmRDPCSTX2_RDPCS_TX_CR_ADDR_BASE_IDX 2 2726fdcba32SRoman Li #define mmRDPCSTX2_RDPCS_TX_CR_DATA 0x2ae5 2736fdcba32SRoman Li #define mmRDPCSTX2_RDPCS_TX_CR_DATA_BASE_IDX 2 2746fdcba32SRoman Li #define mmRDPCSTX2_RDPCS_TX_SRAM_CNTL 0x2ae6 2756fdcba32SRoman Li #define mmRDPCSTX2_RDPCS_TX_SRAM_CNTL_BASE_IDX 2 2766fdcba32SRoman Li #define mmRDPCSTX2_RDPCSTX_SCRATCH 0x2ae7 2776fdcba32SRoman Li #define mmRDPCSTX2_RDPCSTX_SCRATCH_BASE_IDX 2 2786fdcba32SRoman Li #define mmRDPCSTX2_RDPCSTX_SPARE 0x2ae8 2796fdcba32SRoman Li #define mmRDPCSTX2_RDPCSTX_SPARE_BASE_IDX 2 2806fdcba32SRoman Li #define mmRDPCSTX2_RDPCSTX_CNTL2 0x2ae9 2816fdcba32SRoman Li #define mmRDPCSTX2_RDPCSTX_CNTL2_BASE_IDX 2 2826fdcba32SRoman Li #define mmRDPCSTX2_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG 0x2aec 2836fdcba32SRoman Li #define mmRDPCSTX2_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG_BASE_IDX 2 2846fdcba32SRoman Li #define mmRDPCSTX2_RDPCSTX_DEBUG_CONFIG 0x2aed 2856fdcba32SRoman Li #define mmRDPCSTX2_RDPCSTX_DEBUG_CONFIG_BASE_IDX 2 2866fdcba32SRoman Li #define mmRDPCSTX2_RDPCSTX_PHY_CNTL0 0x2af0 2876fdcba32SRoman Li #define mmRDPCSTX2_RDPCSTX_PHY_CNTL0_BASE_IDX 2 2886fdcba32SRoman Li #define mmRDPCSTX2_RDPCSTX_PHY_CNTL1 0x2af1 2896fdcba32SRoman Li #define mmRDPCSTX2_RDPCSTX_PHY_CNTL1_BASE_IDX 2 2906fdcba32SRoman Li #define mmRDPCSTX2_RDPCSTX_PHY_CNTL2 0x2af2 2916fdcba32SRoman Li #define mmRDPCSTX2_RDPCSTX_PHY_CNTL2_BASE_IDX 2 2926fdcba32SRoman Li #define mmRDPCSTX2_RDPCSTX_PHY_CNTL3 0x2af3 2936fdcba32SRoman Li #define mmRDPCSTX2_RDPCSTX_PHY_CNTL3_BASE_IDX 2 2946fdcba32SRoman Li #define mmRDPCSTX2_RDPCSTX_PHY_CNTL4 0x2af4 2956fdcba32SRoman Li #define mmRDPCSTX2_RDPCSTX_PHY_CNTL4_BASE_IDX 2 2966fdcba32SRoman Li #define mmRDPCSTX2_RDPCSTX_PHY_CNTL5 0x2af5 2976fdcba32SRoman Li #define mmRDPCSTX2_RDPCSTX_PHY_CNTL5_BASE_IDX 2 2986fdcba32SRoman Li #define mmRDPCSTX2_RDPCSTX_PHY_CNTL6 0x2af6 2996fdcba32SRoman Li #define mmRDPCSTX2_RDPCSTX_PHY_CNTL6_BASE_IDX 2 3006fdcba32SRoman Li #define mmRDPCSTX2_RDPCSTX_PHY_CNTL7 0x2af7 3016fdcba32SRoman Li #define mmRDPCSTX2_RDPCSTX_PHY_CNTL7_BASE_IDX 2 3026fdcba32SRoman Li #define mmRDPCSTX2_RDPCSTX_PHY_CNTL8 0x2af8 3036fdcba32SRoman Li #define mmRDPCSTX2_RDPCSTX_PHY_CNTL8_BASE_IDX 2 3046fdcba32SRoman Li #define mmRDPCSTX2_RDPCSTX_PHY_CNTL9 0x2af9 3056fdcba32SRoman Li #define mmRDPCSTX2_RDPCSTX_PHY_CNTL9_BASE_IDX 2 3066fdcba32SRoman Li #define mmRDPCSTX2_RDPCSTX_PHY_CNTL10 0x2afa 3076fdcba32SRoman Li #define mmRDPCSTX2_RDPCSTX_PHY_CNTL10_BASE_IDX 2 3086fdcba32SRoman Li #define mmRDPCSTX2_RDPCSTX_PHY_CNTL11 0x2afb 3096fdcba32SRoman Li #define mmRDPCSTX2_RDPCSTX_PHY_CNTL11_BASE_IDX 2 3106fdcba32SRoman Li #define mmRDPCSTX2_RDPCSTX_PHY_CNTL12 0x2afc 3116fdcba32SRoman Li #define mmRDPCSTX2_RDPCSTX_PHY_CNTL12_BASE_IDX 2 3126fdcba32SRoman Li #define mmRDPCSTX2_RDPCSTX_PHY_CNTL13 0x2afd 3136fdcba32SRoman Li #define mmRDPCSTX2_RDPCSTX_PHY_CNTL13_BASE_IDX 2 3146fdcba32SRoman Li #define mmRDPCSTX2_RDPCSTX_PHY_CNTL14 0x2afe 3156fdcba32SRoman Li #define mmRDPCSTX2_RDPCSTX_PHY_CNTL14_BASE_IDX 2 3166fdcba32SRoman Li #define mmRDPCSTX2_RDPCSTX_PHY_FUSE0 0x2aff 3176fdcba32SRoman Li #define mmRDPCSTX2_RDPCSTX_PHY_FUSE0_BASE_IDX 2 3186fdcba32SRoman Li #define mmRDPCSTX2_RDPCSTX_PHY_FUSE1 0x2b00 3196fdcba32SRoman Li #define mmRDPCSTX2_RDPCSTX_PHY_FUSE1_BASE_IDX 2 3206fdcba32SRoman Li #define mmRDPCSTX2_RDPCSTX_PHY_FUSE2 0x2b01 3216fdcba32SRoman Li #define mmRDPCSTX2_RDPCSTX_PHY_FUSE2_BASE_IDX 2 3226fdcba32SRoman Li #define mmRDPCSTX2_RDPCSTX_PHY_FUSE3 0x2b02 3236fdcba32SRoman Li #define mmRDPCSTX2_RDPCSTX_PHY_FUSE3_BASE_IDX 2 3246fdcba32SRoman Li #define mmRDPCSTX2_RDPCSTX_PHY_RX_LD_VAL 0x2b03 3256fdcba32SRoman Li #define mmRDPCSTX2_RDPCSTX_PHY_RX_LD_VAL_BASE_IDX 2 3266fdcba32SRoman Li #define mmRDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3 0x2b04 3276fdcba32SRoman Li #define mmRDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3_BASE_IDX 2 3286fdcba32SRoman Li #define mmRDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL6 0x2b05 3296fdcba32SRoman Li #define mmRDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL6_BASE_IDX 2 3306fdcba32SRoman Li #define mmRDPCSTX2_RDPCSTX_DPALT_CONTROL_REG 0x2b06 3316fdcba32SRoman Li #define mmRDPCSTX2_RDPCSTX_DPALT_CONTROL_REG_BASE_IDX 2 3326fdcba32SRoman Li #define mmRDPCSTX2_RDPCSTX_PHY_CNTL15 0x2b08 3336fdcba32SRoman Li #define mmRDPCSTX2_RDPCSTX_PHY_CNTL15_BASE_IDX 2 3346fdcba32SRoman Li #define mmRDPCSTX2_RDPCSTX_PHY_CNTL16 0x2b09 3356fdcba32SRoman Li #define mmRDPCSTX2_RDPCSTX_PHY_CNTL16_BASE_IDX 2 3366fdcba32SRoman Li #define mmRDPCSTX2_RDPCSTX_PHY_CNTL17 0x2b0a 3376fdcba32SRoman Li #define mmRDPCSTX2_RDPCSTX_PHY_CNTL17_BASE_IDX 2 3386fdcba32SRoman Li #define mmRDPCSTX2_RDPCSTX_DEBUG_CONFIG2 0x2b0b 3396fdcba32SRoman Li #define mmRDPCSTX2_RDPCSTX_DEBUG_CONFIG2_BASE_IDX 2 3406fdcba32SRoman Li 3416fdcba32SRoman Li 3426fdcba32SRoman Li // addressBlock: dpcssys_dpcssys_cr2_dispdec 3436fdcba32SRoman Li // base address: 0x6c0 3446fdcba32SRoman Li #define mmDPCSSYS_CR2_DPCSSYS_CR_ADDR 0x2ae4 3456fdcba32SRoman Li #define mmDPCSSYS_CR2_DPCSSYS_CR_ADDR_BASE_IDX 2 3466fdcba32SRoman Li #define mmDPCSSYS_CR2_DPCSSYS_CR_DATA 0x2ae5 3476fdcba32SRoman Li #define mmDPCSSYS_CR2_DPCSSYS_CR_DATA_BASE_IDX 2 3486fdcba32SRoman Li 3496fdcba32SRoman Li 3506fdcba32SRoman Li // addressBlock: dpcssys_dpcs0_dpcstx3_dispdec 3516fdcba32SRoman Li // base address: 0xa20 3526fdcba32SRoman Li #define mmDPCSTX3_DPCSTX_TX_CLOCK_CNTL 0x2bb0 3536fdcba32SRoman Li #define mmDPCSTX3_DPCSTX_TX_CLOCK_CNTL_BASE_IDX 2 3546fdcba32SRoman Li #define mmDPCSTX3_DPCSTX_TX_CNTL 0x2bb1 3556fdcba32SRoman Li #define mmDPCSTX3_DPCSTX_TX_CNTL_BASE_IDX 2 3566fdcba32SRoman Li #define mmDPCSTX3_DPCSTX_CBUS_CNTL 0x2bb2 3576fdcba32SRoman Li #define mmDPCSTX3_DPCSTX_CBUS_CNTL_BASE_IDX 2 3586fdcba32SRoman Li #define mmDPCSTX3_DPCSTX_INTERRUPT_CNTL 0x2bb3 3596fdcba32SRoman Li #define mmDPCSTX3_DPCSTX_INTERRUPT_CNTL_BASE_IDX 2 3606fdcba32SRoman Li #define mmDPCSTX3_DPCSTX_PLL_UPDATE_ADDR 0x2bb4 3616fdcba32SRoman Li #define mmDPCSTX3_DPCSTX_PLL_UPDATE_ADDR_BASE_IDX 2 3626fdcba32SRoman Li #define mmDPCSTX3_DPCSTX_PLL_UPDATE_DATA 0x2bb5 3636fdcba32SRoman Li #define mmDPCSTX3_DPCSTX_PLL_UPDATE_DATA_BASE_IDX 2 3646fdcba32SRoman Li #define mmDPCSTX3_DPCSTX_DEBUG_CONFIG 0x2bb6 3656fdcba32SRoman Li #define mmDPCSTX3_DPCSTX_DEBUG_CONFIG_BASE_IDX 2 3666fdcba32SRoman Li 3676fdcba32SRoman Li 3686fdcba32SRoman Li // addressBlock: dpcssys_dpcs0_rdpcstx3_dispdec 3696fdcba32SRoman Li // base address: 0xa20 3706fdcba32SRoman Li #define mmRDPCSTX3_RDPCSTX_CNTL 0x2bb8 3716fdcba32SRoman Li #define mmRDPCSTX3_RDPCSTX_CNTL_BASE_IDX 2 3726fdcba32SRoman Li #define mmRDPCSTX3_RDPCSTX_CLOCK_CNTL 0x2bb9 3736fdcba32SRoman Li #define mmRDPCSTX3_RDPCSTX_CLOCK_CNTL_BASE_IDX 2 3746fdcba32SRoman Li #define mmRDPCSTX3_RDPCSTX_INTERRUPT_CONTROL 0x2bba 3756fdcba32SRoman Li #define mmRDPCSTX3_RDPCSTX_INTERRUPT_CONTROL_BASE_IDX 2 3766fdcba32SRoman Li #define mmRDPCSTX3_RDPCSTX_PLL_UPDATE_DATA 0x2bbb 3776fdcba32SRoman Li #define mmRDPCSTX3_RDPCSTX_PLL_UPDATE_DATA_BASE_IDX 2 3786fdcba32SRoman Li #define mmRDPCSTX3_RDPCS_TX_CR_ADDR 0x2bbc 3796fdcba32SRoman Li #define mmRDPCSTX3_RDPCS_TX_CR_ADDR_BASE_IDX 2 3806fdcba32SRoman Li #define mmRDPCSTX3_RDPCS_TX_CR_DATA 0x2bbd 3816fdcba32SRoman Li #define mmRDPCSTX3_RDPCS_TX_CR_DATA_BASE_IDX 2 3826fdcba32SRoman Li #define mmRDPCSTX3_RDPCS_TX_SRAM_CNTL 0x2bbe 3836fdcba32SRoman Li #define mmRDPCSTX3_RDPCS_TX_SRAM_CNTL_BASE_IDX 2 3846fdcba32SRoman Li #define mmRDPCSTX3_RDPCSTX_SCRATCH 0x2bbf 3856fdcba32SRoman Li #define mmRDPCSTX3_RDPCSTX_SCRATCH_BASE_IDX 2 3866fdcba32SRoman Li #define mmRDPCSTX3_RDPCSTX_SPARE 0x2bc0 3876fdcba32SRoman Li #define mmRDPCSTX3_RDPCSTX_SPARE_BASE_IDX 2 3886fdcba32SRoman Li #define mmRDPCSTX3_RDPCSTX_CNTL2 0x2bc1 3896fdcba32SRoman Li #define mmRDPCSTX3_RDPCSTX_CNTL2_BASE_IDX 2 3906fdcba32SRoman Li #define mmRDPCSTX3_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG 0x2bc4 3916fdcba32SRoman Li #define mmRDPCSTX3_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG_BASE_IDX 2 3926fdcba32SRoman Li #define mmRDPCSTX3_RDPCSTX_DEBUG_CONFIG 0x2bc5 3936fdcba32SRoman Li #define mmRDPCSTX3_RDPCSTX_DEBUG_CONFIG_BASE_IDX 2 3946fdcba32SRoman Li #define mmRDPCSTX3_RDPCSTX_PHY_CNTL0 0x2bc8 3956fdcba32SRoman Li #define mmRDPCSTX3_RDPCSTX_PHY_CNTL0_BASE_IDX 2 3966fdcba32SRoman Li #define mmRDPCSTX3_RDPCSTX_PHY_CNTL1 0x2bc9 3976fdcba32SRoman Li #define mmRDPCSTX3_RDPCSTX_PHY_CNTL1_BASE_IDX 2 3986fdcba32SRoman Li #define mmRDPCSTX3_RDPCSTX_PHY_CNTL2 0x2bca 3996fdcba32SRoman Li #define mmRDPCSTX3_RDPCSTX_PHY_CNTL2_BASE_IDX 2 4006fdcba32SRoman Li #define mmRDPCSTX3_RDPCSTX_PHY_CNTL3 0x2bcb 4016fdcba32SRoman Li #define mmRDPCSTX3_RDPCSTX_PHY_CNTL3_BASE_IDX 2 4026fdcba32SRoman Li #define mmRDPCSTX3_RDPCSTX_PHY_CNTL4 0x2bcc 4036fdcba32SRoman Li #define mmRDPCSTX3_RDPCSTX_PHY_CNTL4_BASE_IDX 2 4046fdcba32SRoman Li #define mmRDPCSTX3_RDPCSTX_PHY_CNTL5 0x2bcd 4056fdcba32SRoman Li #define mmRDPCSTX3_RDPCSTX_PHY_CNTL5_BASE_IDX 2 4066fdcba32SRoman Li #define mmRDPCSTX3_RDPCSTX_PHY_CNTL6 0x2bce 4076fdcba32SRoman Li #define mmRDPCSTX3_RDPCSTX_PHY_CNTL6_BASE_IDX 2 4086fdcba32SRoman Li #define mmRDPCSTX3_RDPCSTX_PHY_CNTL7 0x2bcf 4096fdcba32SRoman Li #define mmRDPCSTX3_RDPCSTX_PHY_CNTL7_BASE_IDX 2 4106fdcba32SRoman Li #define mmRDPCSTX3_RDPCSTX_PHY_CNTL8 0x2bd0 4116fdcba32SRoman Li #define mmRDPCSTX3_RDPCSTX_PHY_CNTL8_BASE_IDX 2 4126fdcba32SRoman Li #define mmRDPCSTX3_RDPCSTX_PHY_CNTL9 0x2bd1 4136fdcba32SRoman Li #define mmRDPCSTX3_RDPCSTX_PHY_CNTL9_BASE_IDX 2 4146fdcba32SRoman Li #define mmRDPCSTX3_RDPCSTX_PHY_CNTL10 0x2bd2 4156fdcba32SRoman Li #define mmRDPCSTX3_RDPCSTX_PHY_CNTL10_BASE_IDX 2 4166fdcba32SRoman Li #define mmRDPCSTX3_RDPCSTX_PHY_CNTL11 0x2bd3 4176fdcba32SRoman Li #define mmRDPCSTX3_RDPCSTX_PHY_CNTL11_BASE_IDX 2 4186fdcba32SRoman Li #define mmRDPCSTX3_RDPCSTX_PHY_CNTL12 0x2bd4 4196fdcba32SRoman Li #define mmRDPCSTX3_RDPCSTX_PHY_CNTL12_BASE_IDX 2 4206fdcba32SRoman Li #define mmRDPCSTX3_RDPCSTX_PHY_CNTL13 0x2bd5 4216fdcba32SRoman Li #define mmRDPCSTX3_RDPCSTX_PHY_CNTL13_BASE_IDX 2 4226fdcba32SRoman Li #define mmRDPCSTX3_RDPCSTX_PHY_CNTL14 0x2bd6 4236fdcba32SRoman Li #define mmRDPCSTX3_RDPCSTX_PHY_CNTL14_BASE_IDX 2 4246fdcba32SRoman Li #define mmRDPCSTX3_RDPCSTX_PHY_FUSE0 0x2bd7 4256fdcba32SRoman Li #define mmRDPCSTX3_RDPCSTX_PHY_FUSE0_BASE_IDX 2 4266fdcba32SRoman Li #define mmRDPCSTX3_RDPCSTX_PHY_FUSE1 0x2bd8 4276fdcba32SRoman Li #define mmRDPCSTX3_RDPCSTX_PHY_FUSE1_BASE_IDX 2 4286fdcba32SRoman Li #define mmRDPCSTX3_RDPCSTX_PHY_FUSE2 0x2bd9 4296fdcba32SRoman Li #define mmRDPCSTX3_RDPCSTX_PHY_FUSE2_BASE_IDX 2 4306fdcba32SRoman Li #define mmRDPCSTX3_RDPCSTX_PHY_FUSE3 0x2bda 4316fdcba32SRoman Li #define mmRDPCSTX3_RDPCSTX_PHY_FUSE3_BASE_IDX 2 4326fdcba32SRoman Li #define mmRDPCSTX3_RDPCSTX_PHY_RX_LD_VAL 0x2bdb 4336fdcba32SRoman Li #define mmRDPCSTX3_RDPCSTX_PHY_RX_LD_VAL_BASE_IDX 2 4346fdcba32SRoman Li #define mmRDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3 0x2bdc 4356fdcba32SRoman Li #define mmRDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3_BASE_IDX 2 4366fdcba32SRoman Li #define mmRDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL6 0x2bdd 4376fdcba32SRoman Li #define mmRDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL6_BASE_IDX 2 4386fdcba32SRoman Li #define mmRDPCSTX3_RDPCSTX_DPALT_CONTROL_REG 0x2bde 4396fdcba32SRoman Li #define mmRDPCSTX3_RDPCSTX_DPALT_CONTROL_REG_BASE_IDX 2 4406fdcba32SRoman Li #define mmRDPCSTX3_RDPCSTX_PHY_CNTL15 0x2be0 4416fdcba32SRoman Li #define mmRDPCSTX3_RDPCSTX_PHY_CNTL15_BASE_IDX 2 4426fdcba32SRoman Li #define mmRDPCSTX3_RDPCSTX_PHY_CNTL16 0x2be1 4436fdcba32SRoman Li #define mmRDPCSTX3_RDPCSTX_PHY_CNTL16_BASE_IDX 2 4446fdcba32SRoman Li #define mmRDPCSTX3_RDPCSTX_PHY_CNTL17 0x2be2 4456fdcba32SRoman Li #define mmRDPCSTX3_RDPCSTX_PHY_CNTL17_BASE_IDX 2 4466fdcba32SRoman Li #define mmRDPCSTX3_RDPCSTX_DEBUG_CONFIG2 0x2be3 4476fdcba32SRoman Li #define mmRDPCSTX3_RDPCSTX_DEBUG_CONFIG2_BASE_IDX 2 4486fdcba32SRoman Li 4496fdcba32SRoman Li 4506fdcba32SRoman Li // addressBlock: dpcssys_dpcssys_cr3_dispdec 4516fdcba32SRoman Li // base address: 0xa20 4526fdcba32SRoman Li #define mmDPCSSYS_CR3_DPCSSYS_CR_ADDR 0x2bbc 4536fdcba32SRoman Li #define mmDPCSSYS_CR3_DPCSSYS_CR_ADDR_BASE_IDX 2 4546fdcba32SRoman Li #define mmDPCSSYS_CR3_DPCSSYS_CR_DATA 0x2bbd 4556fdcba32SRoman Li #define mmDPCSSYS_CR3_DPCSSYS_CR_DATA_BASE_IDX 2 4566fdcba32SRoman Li 4576fdcba32SRoman Li 4586fdcba32SRoman Li // addressBlock: dpcssys_dpcs0_dpcstx4_dispdec 4596fdcba32SRoman Li // base address: 0xd80 4606fdcba32SRoman Li #define mmDPCSTX4_DPCSTX_TX_CLOCK_CNTL 0x2c88 4616fdcba32SRoman Li #define mmDPCSTX4_DPCSTX_TX_CLOCK_CNTL_BASE_IDX 2 4626fdcba32SRoman Li #define mmDPCSTX4_DPCSTX_TX_CNTL 0x2c89 4636fdcba32SRoman Li #define mmDPCSTX4_DPCSTX_TX_CNTL_BASE_IDX 2 4646fdcba32SRoman Li #define mmDPCSTX4_DPCSTX_CBUS_CNTL 0x2c8a 4656fdcba32SRoman Li #define mmDPCSTX4_DPCSTX_CBUS_CNTL_BASE_IDX 2 4666fdcba32SRoman Li #define mmDPCSTX4_DPCSTX_INTERRUPT_CNTL 0x2c8b 4676fdcba32SRoman Li #define mmDPCSTX4_DPCSTX_INTERRUPT_CNTL_BASE_IDX 2 4686fdcba32SRoman Li #define mmDPCSTX4_DPCSTX_PLL_UPDATE_ADDR 0x2c8c 4696fdcba32SRoman Li #define mmDPCSTX4_DPCSTX_PLL_UPDATE_ADDR_BASE_IDX 2 4706fdcba32SRoman Li #define mmDPCSTX4_DPCSTX_PLL_UPDATE_DATA 0x2c8d 4716fdcba32SRoman Li #define mmDPCSTX4_DPCSTX_PLL_UPDATE_DATA_BASE_IDX 2 4726fdcba32SRoman Li #define mmDPCSTX4_DPCSTX_DEBUG_CONFIG 0x2c8e 4736fdcba32SRoman Li #define mmDPCSTX4_DPCSTX_DEBUG_CONFIG_BASE_IDX 2 4746fdcba32SRoman Li 4756fdcba32SRoman Li 4766fdcba32SRoman Li // addressBlock: dpcssys_dpcs0_rdpcstx4_dispdec 4776fdcba32SRoman Li // base address: 0xd80 4786fdcba32SRoman Li #define mmRDPCSTX4_RDPCSTX_CNTL 0x2c90 4796fdcba32SRoman Li #define mmRDPCSTX4_RDPCSTX_CNTL_BASE_IDX 2 4806fdcba32SRoman Li #define mmRDPCSTX4_RDPCSTX_CLOCK_CNTL 0x2c91 4816fdcba32SRoman Li #define mmRDPCSTX4_RDPCSTX_CLOCK_CNTL_BASE_IDX 2 4826fdcba32SRoman Li #define mmRDPCSTX4_RDPCSTX_INTERRUPT_CONTROL 0x2c92 4836fdcba32SRoman Li #define mmRDPCSTX4_RDPCSTX_INTERRUPT_CONTROL_BASE_IDX 2 4846fdcba32SRoman Li #define mmRDPCSTX4_RDPCSTX_PLL_UPDATE_DATA 0x2c93 4856fdcba32SRoman Li #define mmRDPCSTX4_RDPCSTX_PLL_UPDATE_DATA_BASE_IDX 2 4866fdcba32SRoman Li #define mmRDPCSTX4_RDPCS_TX_CR_ADDR 0x2c94 4876fdcba32SRoman Li #define mmRDPCSTX4_RDPCS_TX_CR_ADDR_BASE_IDX 2 4886fdcba32SRoman Li #define mmRDPCSTX4_RDPCS_TX_CR_DATA 0x2c95 4896fdcba32SRoman Li #define mmRDPCSTX4_RDPCS_TX_CR_DATA_BASE_IDX 2 4906fdcba32SRoman Li #define mmRDPCSTX4_RDPCS_TX_SRAM_CNTL 0x2c96 4916fdcba32SRoman Li #define mmRDPCSTX4_RDPCS_TX_SRAM_CNTL_BASE_IDX 2 4926fdcba32SRoman Li #define mmRDPCSTX4_RDPCSTX_SCRATCH 0x2c97 4936fdcba32SRoman Li #define mmRDPCSTX4_RDPCSTX_SCRATCH_BASE_IDX 2 4946fdcba32SRoman Li #define mmRDPCSTX4_RDPCSTX_SPARE 0x2c98 4956fdcba32SRoman Li #define mmRDPCSTX4_RDPCSTX_SPARE_BASE_IDX 2 4966fdcba32SRoman Li #define mmRDPCSTX4_RDPCSTX_CNTL2 0x2c99 4976fdcba32SRoman Li #define mmRDPCSTX4_RDPCSTX_CNTL2_BASE_IDX 2 4986fdcba32SRoman Li #define mmRDPCSTX4_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG 0x2c9c 4996fdcba32SRoman Li #define mmRDPCSTX4_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG_BASE_IDX 2 5006fdcba32SRoman Li #define mmRDPCSTX4_RDPCSTX_DEBUG_CONFIG 0x2c9d 5016fdcba32SRoman Li #define mmRDPCSTX4_RDPCSTX_DEBUG_CONFIG_BASE_IDX 2 5026fdcba32SRoman Li #define mmRDPCSTX4_RDPCSTX_PHY_CNTL0 0x2ca0 5036fdcba32SRoman Li #define mmRDPCSTX4_RDPCSTX_PHY_CNTL0_BASE_IDX 2 5046fdcba32SRoman Li #define mmRDPCSTX4_RDPCSTX_PHY_CNTL1 0x2ca1 5056fdcba32SRoman Li #define mmRDPCSTX4_RDPCSTX_PHY_CNTL1_BASE_IDX 2 5066fdcba32SRoman Li #define mmRDPCSTX4_RDPCSTX_PHY_CNTL2 0x2ca2 5076fdcba32SRoman Li #define mmRDPCSTX4_RDPCSTX_PHY_CNTL2_BASE_IDX 2 5086fdcba32SRoman Li #define mmRDPCSTX4_RDPCSTX_PHY_CNTL3 0x2ca3 5096fdcba32SRoman Li #define mmRDPCSTX4_RDPCSTX_PHY_CNTL3_BASE_IDX 2 5106fdcba32SRoman Li #define mmRDPCSTX4_RDPCSTX_PHY_CNTL4 0x2ca4 5116fdcba32SRoman Li #define mmRDPCSTX4_RDPCSTX_PHY_CNTL4_BASE_IDX 2 5126fdcba32SRoman Li #define mmRDPCSTX4_RDPCSTX_PHY_CNTL5 0x2ca5 5136fdcba32SRoman Li #define mmRDPCSTX4_RDPCSTX_PHY_CNTL5_BASE_IDX 2 5146fdcba32SRoman Li #define mmRDPCSTX4_RDPCSTX_PHY_CNTL6 0x2ca6 5156fdcba32SRoman Li #define mmRDPCSTX4_RDPCSTX_PHY_CNTL6_BASE_IDX 2 5166fdcba32SRoman Li #define mmRDPCSTX4_RDPCSTX_PHY_CNTL7 0x2ca7 5176fdcba32SRoman Li #define mmRDPCSTX4_RDPCSTX_PHY_CNTL7_BASE_IDX 2 5186fdcba32SRoman Li #define mmRDPCSTX4_RDPCSTX_PHY_CNTL8 0x2ca8 5196fdcba32SRoman Li #define mmRDPCSTX4_RDPCSTX_PHY_CNTL8_BASE_IDX 2 5206fdcba32SRoman Li #define mmRDPCSTX4_RDPCSTX_PHY_CNTL9 0x2ca9 5216fdcba32SRoman Li #define mmRDPCSTX4_RDPCSTX_PHY_CNTL9_BASE_IDX 2 5226fdcba32SRoman Li #define mmRDPCSTX4_RDPCSTX_PHY_CNTL10 0x2caa 5236fdcba32SRoman Li #define mmRDPCSTX4_RDPCSTX_PHY_CNTL10_BASE_IDX 2 5246fdcba32SRoman Li #define mmRDPCSTX4_RDPCSTX_PHY_CNTL11 0x2cab 5256fdcba32SRoman Li #define mmRDPCSTX4_RDPCSTX_PHY_CNTL11_BASE_IDX 2 5266fdcba32SRoman Li #define mmRDPCSTX4_RDPCSTX_PHY_CNTL12 0x2cac 5276fdcba32SRoman Li #define mmRDPCSTX4_RDPCSTX_PHY_CNTL12_BASE_IDX 2 5286fdcba32SRoman Li #define mmRDPCSTX4_RDPCSTX_PHY_CNTL13 0x2cad 5296fdcba32SRoman Li #define mmRDPCSTX4_RDPCSTX_PHY_CNTL13_BASE_IDX 2 5306fdcba32SRoman Li #define mmRDPCSTX4_RDPCSTX_PHY_CNTL14 0x2cae 5316fdcba32SRoman Li #define mmRDPCSTX4_RDPCSTX_PHY_CNTL14_BASE_IDX 2 5326fdcba32SRoman Li #define mmRDPCSTX4_RDPCSTX_PHY_FUSE0 0x2caf 5336fdcba32SRoman Li #define mmRDPCSTX4_RDPCSTX_PHY_FUSE0_BASE_IDX 2 5346fdcba32SRoman Li #define mmRDPCSTX4_RDPCSTX_PHY_FUSE1 0x2cb0 5356fdcba32SRoman Li #define mmRDPCSTX4_RDPCSTX_PHY_FUSE1_BASE_IDX 2 5366fdcba32SRoman Li #define mmRDPCSTX4_RDPCSTX_PHY_FUSE2 0x2cb1 5376fdcba32SRoman Li #define mmRDPCSTX4_RDPCSTX_PHY_FUSE2_BASE_IDX 2 5386fdcba32SRoman Li #define mmRDPCSTX4_RDPCSTX_PHY_FUSE3 0x2cb2 5396fdcba32SRoman Li #define mmRDPCSTX4_RDPCSTX_PHY_FUSE3_BASE_IDX 2 5406fdcba32SRoman Li #define mmRDPCSTX4_RDPCSTX_PHY_RX_LD_VAL 0x2cb3 5416fdcba32SRoman Li #define mmRDPCSTX4_RDPCSTX_PHY_RX_LD_VAL_BASE_IDX 2 5426fdcba32SRoman Li #define mmRDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3 0x2cb4 5436fdcba32SRoman Li #define mmRDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3_BASE_IDX 2 5446fdcba32SRoman Li #define mmRDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL6 0x2cb5 5456fdcba32SRoman Li #define mmRDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL6_BASE_IDX 2 5466fdcba32SRoman Li #define mmRDPCSTX4_RDPCSTX_DPALT_CONTROL_REG 0x2cb6 5476fdcba32SRoman Li #define mmRDPCSTX4_RDPCSTX_DPALT_CONTROL_REG_BASE_IDX 2 5486fdcba32SRoman Li #define mmRDPCSTX4_RDPCSTX_PHY_CNTL15 0x2cb8 5496fdcba32SRoman Li #define mmRDPCSTX4_RDPCSTX_PHY_CNTL15_BASE_IDX 2 5506fdcba32SRoman Li #define mmRDPCSTX4_RDPCSTX_PHY_CNTL16 0x2cb9 5516fdcba32SRoman Li #define mmRDPCSTX4_RDPCSTX_PHY_CNTL16_BASE_IDX 2 5526fdcba32SRoman Li #define mmRDPCSTX4_RDPCSTX_PHY_CNTL17 0x2cba 5536fdcba32SRoman Li #define mmRDPCSTX4_RDPCSTX_PHY_CNTL17_BASE_IDX 2 5546fdcba32SRoman Li #define mmRDPCSTX4_RDPCSTX_DEBUG_CONFIG2 0x2cbb 5556fdcba32SRoman Li #define mmRDPCSTX4_RDPCSTX_DEBUG_CONFIG2_BASE_IDX 2 5566fdcba32SRoman Li 5576fdcba32SRoman Li 5586fdcba32SRoman Li // addressBlock: dpcssys_dpcssys_cr4_dispdec 5596fdcba32SRoman Li // base address: 0xd80 5606fdcba32SRoman Li #define mmDPCSSYS_CR4_DPCSSYS_CR_ADDR 0x2c94 5616fdcba32SRoman Li #define mmDPCSSYS_CR4_DPCSSYS_CR_ADDR_BASE_IDX 2 5626fdcba32SRoman Li #define mmDPCSSYS_CR4_DPCSSYS_CR_DATA 0x2c95 5636fdcba32SRoman Li #define mmDPCSSYS_CR4_DPCSSYS_CR_DATA_BASE_IDX 2 5646fdcba32SRoman Li 5656fdcba32SRoman Li #endif 566