1 /* 2 * Copyright (C) 2020 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included 12 * in all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN 18 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 19 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 20 */ 21 #ifndef _dcn_3_1_2_OFFSET_HEADER 22 #define _dcn_3_1_2_OFFSET_HEADER 23 24 25 26 // addressBlock: dce_dc_hda_azcontroller_azdec 27 // base address: 0x1300000 28 #define regAZCONTROLLER0_GLOBAL_CAPABILITIES 0x4b7000 29 #define regAZCONTROLLER0_GLOBAL_CAPABILITIES_BASE_IDX 3 30 #define regAZCONTROLLER0_MINOR_VERSION 0x4b7000 31 #define regAZCONTROLLER0_MINOR_VERSION_BASE_IDX 3 32 #define regAZCONTROLLER0_MAJOR_VERSION 0x4b7000 33 #define regAZCONTROLLER0_MAJOR_VERSION_BASE_IDX 3 34 #define regAZCONTROLLER0_OUTPUT_PAYLOAD_CAPABILITY 0x4b7001 35 #define regAZCONTROLLER0_OUTPUT_PAYLOAD_CAPABILITY_BASE_IDX 3 36 #define regAZCONTROLLER0_INPUT_PAYLOAD_CAPABILITY 0x4b7001 37 #define regAZCONTROLLER0_INPUT_PAYLOAD_CAPABILITY_BASE_IDX 3 38 #define regAZCONTROLLER0_GLOBAL_CONTROL 0x4b7002 39 #define regAZCONTROLLER0_GLOBAL_CONTROL_BASE_IDX 3 40 #define regAZCONTROLLER0_WAKE_ENABLE 0x4b7003 41 #define regAZCONTROLLER0_WAKE_ENABLE_BASE_IDX 3 42 #define regAZCONTROLLER0_STATE_CHANGE_STATUS 0x4b7003 43 #define regAZCONTROLLER0_STATE_CHANGE_STATUS_BASE_IDX 3 44 #define regAZCONTROLLER0_GLOBAL_STATUS 0x4b7004 45 #define regAZCONTROLLER0_GLOBAL_STATUS_BASE_IDX 3 46 #define regAZCONTROLLER0_OUTPUT_STREAM_PAYLOAD_CAPABILITY 0x4b7006 47 #define regAZCONTROLLER0_OUTPUT_STREAM_PAYLOAD_CAPABILITY_BASE_IDX 3 48 #define regAZCONTROLLER0_INPUT_STREAM_PAYLOAD_CAPABILITY 0x4b7006 49 #define regAZCONTROLLER0_INPUT_STREAM_PAYLOAD_CAPABILITY_BASE_IDX 3 50 #define regAZCONTROLLER0_INTERRUPT_CONTROL 0x4b7008 51 #define regAZCONTROLLER0_INTERRUPT_CONTROL_BASE_IDX 3 52 #define regAZCONTROLLER0_INTERRUPT_STATUS 0x4b7009 53 #define regAZCONTROLLER0_INTERRUPT_STATUS_BASE_IDX 3 54 #define regAZCONTROLLER0_WALL_CLOCK_COUNTER 0x4b700c 55 #define regAZCONTROLLER0_WALL_CLOCK_COUNTER_BASE_IDX 3 56 #define regAZCONTROLLER0_STREAM_SYNCHRONIZATION 0x4b700e 57 #define regAZCONTROLLER0_STREAM_SYNCHRONIZATION_BASE_IDX 3 58 #define regAZCONTROLLER0_CORB_LOWER_BASE_ADDRESS 0x4b7010 59 #define regAZCONTROLLER0_CORB_LOWER_BASE_ADDRESS_BASE_IDX 3 60 #define regAZCONTROLLER0_CORB_UPPER_BASE_ADDRESS 0x4b7011 61 #define regAZCONTROLLER0_CORB_UPPER_BASE_ADDRESS_BASE_IDX 3 62 #define regAZCONTROLLER0_CORB_WRITE_POINTER 0x4b7012 63 #define regAZCONTROLLER0_CORB_WRITE_POINTER_BASE_IDX 3 64 #define regAZCONTROLLER0_CORB_READ_POINTER 0x4b7012 65 #define regAZCONTROLLER0_CORB_READ_POINTER_BASE_IDX 3 66 #define regAZCONTROLLER0_CORB_CONTROL 0x4b7013 67 #define regAZCONTROLLER0_CORB_CONTROL_BASE_IDX 3 68 #define regAZCONTROLLER0_CORB_STATUS 0x4b7013 69 #define regAZCONTROLLER0_CORB_STATUS_BASE_IDX 3 70 #define regAZCONTROLLER0_CORB_SIZE 0x4b7013 71 #define regAZCONTROLLER0_CORB_SIZE_BASE_IDX 3 72 #define regAZCONTROLLER0_RIRB_LOWER_BASE_ADDRESS 0x4b7014 73 #define regAZCONTROLLER0_RIRB_LOWER_BASE_ADDRESS_BASE_IDX 3 74 #define regAZCONTROLLER0_RIRB_UPPER_BASE_ADDRESS 0x4b7015 75 #define regAZCONTROLLER0_RIRB_UPPER_BASE_ADDRESS_BASE_IDX 3 76 #define regAZCONTROLLER0_RIRB_WRITE_POINTER 0x4b7016 77 #define regAZCONTROLLER0_RIRB_WRITE_POINTER_BASE_IDX 3 78 #define regAZCONTROLLER0_RESPONSE_INTERRUPT_COUNT 0x4b7016 79 #define regAZCONTROLLER0_RESPONSE_INTERRUPT_COUNT_BASE_IDX 3 80 #define regAZCONTROLLER0_RIRB_CONTROL 0x4b7017 81 #define regAZCONTROLLER0_RIRB_CONTROL_BASE_IDX 3 82 #define regAZCONTROLLER0_RIRB_STATUS 0x4b7017 83 #define regAZCONTROLLER0_RIRB_STATUS_BASE_IDX 3 84 #define regAZCONTROLLER0_RIRB_SIZE 0x4b7017 85 #define regAZCONTROLLER0_RIRB_SIZE_BASE_IDX 3 86 #define regAZCONTROLLER0_IMMEDIATE_COMMAND_OUTPUT_INTERFACE 0x4b7018 87 #define regAZCONTROLLER0_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_BASE_IDX 3 88 #define regAZCONTROLLER0_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA 0x4b7018 89 #define regAZCONTROLLER0_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA_BASE_IDX 3 90 #define regAZCONTROLLER0_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX 0x4b7018 91 #define regAZCONTROLLER0_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX_BASE_IDX 3 92 #define regAZCONTROLLER0_IMMEDIATE_RESPONSE_INPUT_INTERFACE 0x4b7019 93 #define regAZCONTROLLER0_IMMEDIATE_RESPONSE_INPUT_INTERFACE_BASE_IDX 3 94 #define regAZCONTROLLER0_IMMEDIATE_COMMAND_STATUS 0x4b701a 95 #define regAZCONTROLLER0_IMMEDIATE_COMMAND_STATUS_BASE_IDX 3 96 #define regAZCONTROLLER0_DMA_POSITION_LOWER_BASE_ADDRESS 0x4b701c 97 #define regAZCONTROLLER0_DMA_POSITION_LOWER_BASE_ADDRESS_BASE_IDX 3 98 #define regAZCONTROLLER0_DMA_POSITION_UPPER_BASE_ADDRESS 0x4b701d 99 #define regAZCONTROLLER0_DMA_POSITION_UPPER_BASE_ADDRESS_BASE_IDX 3 100 #define regAZCONTROLLER0_WALL_CLOCK_COUNTER_ALIAS 0x4b780c 101 #define regAZCONTROLLER0_WALL_CLOCK_COUNTER_ALIAS_BASE_IDX 3 102 103 104 // addressBlock: dce_dc_hda_azendpoint_azdec 105 // base address: 0x1300000 106 #define regAZENDPOINT0_AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA 0x4b7018 107 #define regAZENDPOINT0_AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA_BASE_IDX 3 108 #define regAZENDPOINT0_AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX 0x4b7018 109 #define regAZENDPOINT0_AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX_BASE_IDX 3 110 111 112 // addressBlock: dce_dc_hda_azinputendpoint_azdec 113 // base address: 0x1300000 114 #define regAZINPUTENDPOINT0_AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA 0x4b7018 115 #define regAZINPUTENDPOINT0_AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA_BASE_IDX 3 116 #define regAZINPUTENDPOINT0_AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX 0x4b7018 117 #define regAZINPUTENDPOINT0_AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX_BASE_IDX 3 118 119 120 // addressBlock: dce_dc_mmhubbub_vga_dispdec[72..76] 121 // base address: 0x48 122 #define regVGA_MEM_WRITE_PAGE_ADDR 0x0000 123 #define regVGA_MEM_WRITE_PAGE_ADDR_BASE_IDX 0 124 #define regVGA_MEM_READ_PAGE_ADDR 0x0001 125 #define regVGA_MEM_READ_PAGE_ADDR_BASE_IDX 0 126 127 128 // addressBlock: dce_dc_mmhubbub_vga_dispdec[948..986] 129 // base address: 0x3b4 130 #define regCRTC8_IDX 0x002d 131 #define regCRTC8_IDX_BASE_IDX 1 132 #define regCRTC8_DATA 0x002d 133 #define regCRTC8_DATA_BASE_IDX 1 134 #define regGENFC_WT 0x002e 135 #define regGENFC_WT_BASE_IDX 1 136 #define regGENS1 0x002e 137 #define regGENS1_BASE_IDX 1 138 #define regATTRDW 0x0030 139 #define regATTRDW_BASE_IDX 1 140 #define regATTRX 0x0030 141 #define regATTRX_BASE_IDX 1 142 #define regATTRDR 0x0030 143 #define regATTRDR_BASE_IDX 1 144 #define regGENMO_WT 0x0030 145 #define regGENMO_WT_BASE_IDX 1 146 #define regGENS0 0x0030 147 #define regGENS0_BASE_IDX 1 148 #define regGENENB 0x0030 149 #define regSEQ8_IDX 0x0031 150 #define regSEQ8_IDX_BASE_IDX 1 151 #define regSEQ8_DATA 0x0031 152 #define regSEQ8_DATA_BASE_IDX 1 153 #define regDAC_MASK 0x0031 154 #define regDAC_MASK_BASE_IDX 1 155 #define regDAC_R_INDEX 0x0031 156 #define regDAC_R_INDEX_BASE_IDX 1 157 #define regDAC_W_INDEX 0x0032 158 #define regDAC_W_INDEX_BASE_IDX 1 159 #define regDAC_DATA 0x0032 160 #define regDAC_DATA_BASE_IDX 1 161 #define regGENFC_RD 0x0032 162 #define regGENFC_RD_BASE_IDX 1 163 #define regGENMO_RD 0x0033 164 #define regGENMO_RD_BASE_IDX 1 165 #define regGRPH8_IDX 0x0033 166 #define regGRPH8_IDX_BASE_IDX 1 167 #define regGRPH8_DATA 0x0033 168 #define regGRPH8_DATA_BASE_IDX 1 169 #define regCRTC8_IDX_1 0x0035 170 #define regCRTC8_IDX_1_BASE_IDX 1 171 #define regCRTC8_DATA_1 0x0035 172 #define regCRTC8_DATA_1_BASE_IDX 1 173 #define regGENFC_WT_1 0x0036 174 #define regGENFC_WT_1_BASE_IDX 1 175 #define regGENS1_1 0x0036 176 #define regGENS1_1_BASE_IDX 1 177 178 179 // addressBlock: dce_dc_hda_azcontroller_azdec 180 // base address: 0x0 181 #define regAZCONTROLLER1_CORB_WRITE_POINTER 0x0000 182 #define regAZCONTROLLER1_CORB_WRITE_POINTER_BASE_IDX 0 183 #define regAZCONTROLLER1_CORB_READ_POINTER 0x0000 184 #define regAZCONTROLLER1_CORB_READ_POINTER_BASE_IDX 0 185 #define regAZCONTROLLER1_CORB_CONTROL 0x0001 186 #define regAZCONTROLLER1_CORB_CONTROL_BASE_IDX 0 187 #define regAZCONTROLLER1_CORB_STATUS 0x0001 188 #define regAZCONTROLLER1_CORB_STATUS_BASE_IDX 0 189 #define regAZCONTROLLER1_CORB_SIZE 0x0001 190 #define regAZCONTROLLER1_CORB_SIZE_BASE_IDX 0 191 #define regAZCONTROLLER1_RIRB_LOWER_BASE_ADDRESS 0x0002 192 #define regAZCONTROLLER1_RIRB_LOWER_BASE_ADDRESS_BASE_IDX 0 193 #define regAZCONTROLLER1_RIRB_UPPER_BASE_ADDRESS 0x0003 194 #define regAZCONTROLLER1_RIRB_UPPER_BASE_ADDRESS_BASE_IDX 0 195 #define regAZCONTROLLER1_RIRB_WRITE_POINTER 0x0004 196 #define regAZCONTROLLER1_RIRB_WRITE_POINTER_BASE_IDX 0 197 #define regAZCONTROLLER1_RESPONSE_INTERRUPT_COUNT 0x0004 198 #define regAZCONTROLLER1_RESPONSE_INTERRUPT_COUNT_BASE_IDX 0 199 #define regAZCONTROLLER1_RIRB_CONTROL 0x0005 200 #define regAZCONTROLLER1_RIRB_CONTROL_BASE_IDX 0 201 #define regAZCONTROLLER1_RIRB_STATUS 0x0005 202 #define regAZCONTROLLER1_RIRB_STATUS_BASE_IDX 0 203 #define regAZCONTROLLER1_RIRB_SIZE 0x0005 204 #define regAZCONTROLLER1_RIRB_SIZE_BASE_IDX 0 205 #define regAZCONTROLLER1_IMMEDIATE_COMMAND_OUTPUT_INTERFACE 0x0006 206 #define regAZCONTROLLER1_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_BASE_IDX 0 207 #define regAZCONTROLLER1_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA 0x0006 208 #define regAZCONTROLLER1_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA_BASE_IDX 0 209 #define regAZCONTROLLER1_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX 0x0006 210 #define regAZCONTROLLER1_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX_BASE_IDX 0 211 #define regAZCONTROLLER1_IMMEDIATE_RESPONSE_INPUT_INTERFACE 0x0007 212 #define regAZCONTROLLER1_IMMEDIATE_RESPONSE_INPUT_INTERFACE_BASE_IDX 0 213 #define regAZCONTROLLER1_IMMEDIATE_COMMAND_STATUS 0x0008 214 #define regAZCONTROLLER1_IMMEDIATE_COMMAND_STATUS_BASE_IDX 0 215 #define regAZCONTROLLER1_DMA_POSITION_LOWER_BASE_ADDRESS 0x000a 216 #define regAZCONTROLLER1_DMA_POSITION_LOWER_BASE_ADDRESS_BASE_IDX 0 217 #define regAZCONTROLLER1_DMA_POSITION_UPPER_BASE_ADDRESS 0x000b 218 #define regAZCONTROLLER1_DMA_POSITION_UPPER_BASE_ADDRESS_BASE_IDX 0 219 #define regAZCONTROLLER1_WALL_CLOCK_COUNTER_ALIAS 0x074c 220 #define regAZCONTROLLER1_WALL_CLOCK_COUNTER_ALIAS_BASE_IDX 1 221 222 223 // addressBlock: dce_dc_hda_azendpoint_azdec 224 // base address: 0x0 225 #define regAZENDPOINT1_AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA 0x0006 226 #define regAZENDPOINT1_AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA_BASE_IDX 0 227 #define regAZENDPOINT1_AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX 0x0006 228 #define regAZENDPOINT1_AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX_BASE_IDX 0 229 230 231 // addressBlock: dce_dc_hda_azinputendpoint_azdec 232 // base address: 0x0 233 #define regAZINPUTENDPOINT1_AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA 0x0006 234 #define regAZINPUTENDPOINT1_AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA_BASE_IDX 0 235 #define regAZINPUTENDPOINT1_AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX 0x0006 236 #define regAZINPUTENDPOINT1_AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX_BASE_IDX 0 237 238 239 // addressBlock: dce_dc_dccg_dccg_dfs_dispdec 240 // base address: 0x0 241 #define regDENTIST_DISPCLK_CNTL 0x0064 242 #define regDENTIST_DISPCLK_CNTL_BASE_IDX 1 243 244 245 // addressBlock: dce_dc_dccg_dccg_dispdec 246 // base address: 0x0 247 #define regPHYPLLA_PIXCLK_RESYNC_CNTL 0x0040 248 #define regPHYPLLA_PIXCLK_RESYNC_CNTL_BASE_IDX 1 249 #define regPHYPLLB_PIXCLK_RESYNC_CNTL 0x0041 250 #define regPHYPLLB_PIXCLK_RESYNC_CNTL_BASE_IDX 1 251 #define regPHYPLLC_PIXCLK_RESYNC_CNTL 0x0042 252 #define regPHYPLLC_PIXCLK_RESYNC_CNTL_BASE_IDX 1 253 #define regPHYPLLD_PIXCLK_RESYNC_CNTL 0x0043 254 #define regPHYPLLD_PIXCLK_RESYNC_CNTL_BASE_IDX 1 255 #define regDP_DTO_DBUF_EN 0x0044 256 #define regDP_DTO_DBUF_EN_BASE_IDX 1 257 #define regDPREFCLK_CGTT_BLK_CTRL_REG 0x0048 258 #define regDPREFCLK_CGTT_BLK_CTRL_REG_BASE_IDX 1 259 #define regDCCG_GATE_DISABLE_CNTL4 0x0049 260 #define regDCCG_GATE_DISABLE_CNTL4_BASE_IDX 1 261 #define regDPSTREAMCLK_CNTL 0x004a 262 #define regDPSTREAMCLK_CNTL_BASE_IDX 1 263 #define regREFCLK_CGTT_BLK_CTRL_REG 0x004b 264 #define regREFCLK_CGTT_BLK_CTRL_REG_BASE_IDX 1 265 #define regPHYPLLE_PIXCLK_RESYNC_CNTL 0x004c 266 #define regPHYPLLE_PIXCLK_RESYNC_CNTL_BASE_IDX 1 267 #define regDCCG_PERFMON_CNTL2 0x004e 268 #define regDCCG_PERFMON_CNTL2_BASE_IDX 1 269 #define regDCCG_DS_DTO_INCR 0x0053 270 #define regDCCG_DS_DTO_INCR_BASE_IDX 1 271 #define regDCCG_DS_DTO_MODULO 0x0054 272 #define regDCCG_DS_DTO_MODULO_BASE_IDX 1 273 #define regDCCG_DS_CNTL 0x0055 274 #define regDCCG_DS_CNTL_BASE_IDX 1 275 #define regDCCG_DS_HW_CAL_INTERVAL 0x0056 276 #define regDCCG_DS_HW_CAL_INTERVAL_BASE_IDX 1 277 #define regDPREFCLK_CNTL 0x0058 278 #define regDPREFCLK_CNTL_BASE_IDX 1 279 #define regDCE_VERSION 0x005e 280 #define regDCE_VERSION_BASE_IDX 1 281 #define regDCCG_GTC_CNTL 0x0060 282 #define regDCCG_GTC_CNTL_BASE_IDX 1 283 #define regDCCG_GTC_DTO_INCR 0x0061 284 #define regDCCG_GTC_DTO_INCR_BASE_IDX 1 285 #define regDCCG_GTC_DTO_MODULO 0x0062 286 #define regDCCG_GTC_DTO_MODULO_BASE_IDX 1 287 #define regDCCG_GTC_CURRENT 0x0063 288 #define regDCCG_GTC_CURRENT_BASE_IDX 1 289 #define regSYMCLK32_SE_CNTL 0x0065 290 #define regSYMCLK32_SE_CNTL_BASE_IDX 1 291 #define regSYMCLK32_LE_CNTL 0x0066 292 #define regSYMCLK32_LE_CNTL_BASE_IDX 1 293 #define regDSCCLK0_DTO_PARAM 0x006c 294 #define regDSCCLK0_DTO_PARAM_BASE_IDX 1 295 #define regDSCCLK1_DTO_PARAM 0x006d 296 #define regDSCCLK1_DTO_PARAM_BASE_IDX 1 297 #define regDSCCLK2_DTO_PARAM 0x006e 298 #define regDSCCLK2_DTO_PARAM_BASE_IDX 1 299 #define regMILLISECOND_TIME_BASE_DIV 0x0070 300 #define regMILLISECOND_TIME_BASE_DIV_BASE_IDX 1 301 #define regDISPCLK_FREQ_CHANGE_CNTL 0x0071 302 #define regDISPCLK_FREQ_CHANGE_CNTL_BASE_IDX 1 303 #define regDC_MEM_GLOBAL_PWR_REQ_CNTL 0x0072 304 #define regDC_MEM_GLOBAL_PWR_REQ_CNTL_BASE_IDX 1 305 #define regDCCG_PERFMON_CNTL 0x0073 306 #define regDCCG_PERFMON_CNTL_BASE_IDX 1 307 #define regDCCG_GATE_DISABLE_CNTL 0x0074 308 #define regDCCG_GATE_DISABLE_CNTL_BASE_IDX 1 309 #define regDISPCLK_CGTT_BLK_CTRL_REG 0x0075 310 #define regDISPCLK_CGTT_BLK_CTRL_REG_BASE_IDX 1 311 #define regSOCCLK_CGTT_BLK_CTRL_REG 0x0076 312 #define regSOCCLK_CGTT_BLK_CTRL_REG_BASE_IDX 1 313 #define regDCCG_CAC_STATUS 0x0077 314 #define regDCCG_CAC_STATUS_BASE_IDX 1 315 #define regMICROSECOND_TIME_BASE_DIV 0x007b 316 #define regMICROSECOND_TIME_BASE_DIV_BASE_IDX 1 317 #define regDCCG_GATE_DISABLE_CNTL2 0x007c 318 #define regDCCG_GATE_DISABLE_CNTL2_BASE_IDX 1 319 #define regSYMCLK_CGTT_BLK_CTRL_REG 0x007d 320 #define regSYMCLK_CGTT_BLK_CTRL_REG_BASE_IDX 1 321 #define regDCCG_DISP_CNTL_REG 0x007f 322 #define regDCCG_DISP_CNTL_REG_BASE_IDX 1 323 #define regOTG0_PIXEL_RATE_CNTL 0x0080 324 #define regOTG0_PIXEL_RATE_CNTL_BASE_IDX 1 325 #define regDP_DTO0_PHASE 0x0081 326 #define regDP_DTO0_PHASE_BASE_IDX 1 327 #define regDP_DTO0_MODULO 0x0082 328 #define regDP_DTO0_MODULO_BASE_IDX 1 329 #define regOTG0_PHYPLL_PIXEL_RATE_CNTL 0x0083 330 #define regOTG0_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX 1 331 #define regOTG1_PIXEL_RATE_CNTL 0x0084 332 #define regOTG1_PIXEL_RATE_CNTL_BASE_IDX 1 333 #define regDP_DTO1_PHASE 0x0085 334 #define regDP_DTO1_PHASE_BASE_IDX 1 335 #define regDP_DTO1_MODULO 0x0086 336 #define regDP_DTO1_MODULO_BASE_IDX 1 337 #define regOTG1_PHYPLL_PIXEL_RATE_CNTL 0x0087 338 #define regOTG1_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX 1 339 #define regOTG2_PIXEL_RATE_CNTL 0x0088 340 #define regOTG2_PIXEL_RATE_CNTL_BASE_IDX 1 341 #define regDP_DTO2_PHASE 0x0089 342 #define regDP_DTO2_PHASE_BASE_IDX 1 343 #define regDP_DTO2_MODULO 0x008a 344 #define regDP_DTO2_MODULO_BASE_IDX 1 345 #define regOTG2_PHYPLL_PIXEL_RATE_CNTL 0x008b 346 #define regOTG2_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX 1 347 #define regOTG3_PIXEL_RATE_CNTL 0x008c 348 #define regOTG3_PIXEL_RATE_CNTL_BASE_IDX 1 349 #define regDP_DTO3_PHASE 0x008d 350 #define regDP_DTO3_PHASE_BASE_IDX 1 351 #define regDP_DTO3_MODULO 0x008e 352 #define regDP_DTO3_MODULO_BASE_IDX 1 353 #define regOTG3_PHYPLL_PIXEL_RATE_CNTL 0x008f 354 #define regOTG3_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX 1 355 #define regDPPCLK_CGTT_BLK_CTRL_REG 0x0098 356 #define regDPPCLK_CGTT_BLK_CTRL_REG_BASE_IDX 1 357 #define regDPPCLK0_DTO_PARAM 0x0099 358 #define regDPPCLK0_DTO_PARAM_BASE_IDX 1 359 #define regDPPCLK1_DTO_PARAM 0x009a 360 #define regDPPCLK1_DTO_PARAM_BASE_IDX 1 361 #define regDPPCLK2_DTO_PARAM 0x009b 362 #define regDPPCLK2_DTO_PARAM_BASE_IDX 1 363 #define regDPPCLK3_DTO_PARAM 0x009c 364 #define regDPPCLK3_DTO_PARAM_BASE_IDX 1 365 #define regDCCG_CAC_STATUS2 0x009f 366 #define regDCCG_CAC_STATUS2_BASE_IDX 1 367 #define regSYMCLKA_CLOCK_ENABLE 0x00a0 368 #define regSYMCLKA_CLOCK_ENABLE_BASE_IDX 1 369 #define regSYMCLKB_CLOCK_ENABLE 0x00a1 370 #define regSYMCLKB_CLOCK_ENABLE_BASE_IDX 1 371 #define regSYMCLKC_CLOCK_ENABLE 0x00a2 372 #define regSYMCLKC_CLOCK_ENABLE_BASE_IDX 1 373 #define regSYMCLKD_CLOCK_ENABLE 0x00a3 374 #define regSYMCLKD_CLOCK_ENABLE_BASE_IDX 1 375 #define regSYMCLKE_CLOCK_ENABLE 0x00a4 376 #define regSYMCLKE_CLOCK_ENABLE_BASE_IDX 1 377 #define regDCCG_SOFT_RESET 0x00a6 378 #define regDCCG_SOFT_RESET_BASE_IDX 1 379 #define regDSCCLK_DTO_CTRL 0x00a7 380 #define regDSCCLK_DTO_CTRL_BASE_IDX 1 381 #define regDCCG_AUDIO_DTO_SOURCE 0x00ab 382 #define regDCCG_AUDIO_DTO_SOURCE_BASE_IDX 1 383 #define regDCCG_AUDIO_DTO0_PHASE 0x00ac 384 #define regDCCG_AUDIO_DTO0_PHASE_BASE_IDX 1 385 #define regDCCG_AUDIO_DTO0_MODULE 0x00ad 386 #define regDCCG_AUDIO_DTO0_MODULE_BASE_IDX 1 387 #define regDCCG_AUDIO_DTO1_PHASE 0x00ae 388 #define regDCCG_AUDIO_DTO1_PHASE_BASE_IDX 1 389 #define regDCCG_AUDIO_DTO1_MODULE 0x00af 390 #define regDCCG_AUDIO_DTO1_MODULE_BASE_IDX 1 391 #define regDCCG_VSYNC_OTG0_LATCH_VALUE 0x00b0 392 #define regDCCG_VSYNC_OTG0_LATCH_VALUE_BASE_IDX 1 393 #define regDCCG_VSYNC_OTG1_LATCH_VALUE 0x00b1 394 #define regDCCG_VSYNC_OTG1_LATCH_VALUE_BASE_IDX 1 395 #define regDCCG_VSYNC_OTG2_LATCH_VALUE 0x00b2 396 #define regDCCG_VSYNC_OTG2_LATCH_VALUE_BASE_IDX 1 397 #define regDCCG_VSYNC_OTG3_LATCH_VALUE 0x00b3 398 #define regDCCG_VSYNC_OTG3_LATCH_VALUE_BASE_IDX 1 399 #define regDCCG_VSYNC_OTG4_LATCH_VALUE 0x00b4 400 #define regDCCG_VSYNC_OTG4_LATCH_VALUE_BASE_IDX 1 401 #define regDCCG_VSYNC_OTG5_LATCH_VALUE 0x00b5 402 #define regDCCG_VSYNC_OTG5_LATCH_VALUE_BASE_IDX 1 403 #define regDPPCLK_DTO_CTRL 0x00b6 404 #define regDPPCLK_DTO_CTRL_BASE_IDX 1 405 #define regDCCG_VSYNC_CNT_CTRL 0x00b8 406 #define regDCCG_VSYNC_CNT_CTRL_BASE_IDX 1 407 #define regDCCG_VSYNC_CNT_INT_CTRL 0x00b9 408 #define regDCCG_VSYNC_CNT_INT_CTRL_BASE_IDX 1 409 #define regFORCE_SYMCLK_DISABLE 0x00ba 410 #define regFORCE_SYMCLK_DISABLE_BASE_IDX 1 411 #define regDTBCLK_DTO0_PHASE 0x0018 412 #define regDTBCLK_DTO0_PHASE_BASE_IDX 2 413 #define regDTBCLK_DTO1_PHASE 0x0019 414 #define regDTBCLK_DTO1_PHASE_BASE_IDX 2 415 #define regDTBCLK_DTO2_PHASE 0x001a 416 #define regDTBCLK_DTO2_PHASE_BASE_IDX 2 417 #define regDTBCLK_DTO3_PHASE 0x001b 418 #define regDTBCLK_DTO3_PHASE_BASE_IDX 2 419 #define regDTBCLK_DTO0_MODULO 0x001f 420 #define regDTBCLK_DTO0_MODULO_BASE_IDX 2 421 #define regDTBCLK_DTO1_MODULO 0x0020 422 #define regDTBCLK_DTO1_MODULO_BASE_IDX 2 423 #define regDTBCLK_DTO2_MODULO 0x0021 424 #define regDTBCLK_DTO2_MODULO_BASE_IDX 2 425 #define regDTBCLK_DTO3_MODULO 0x0022 426 #define regDTBCLK_DTO3_MODULO_BASE_IDX 2 427 #define regPHYASYMCLK_CLOCK_CNTL 0x0052 428 #define regPHYASYMCLK_CLOCK_CNTL_BASE_IDX 2 429 #define regPHYBSYMCLK_CLOCK_CNTL 0x0053 430 #define regPHYBSYMCLK_CLOCK_CNTL_BASE_IDX 2 431 #define regPHYCSYMCLK_CLOCK_CNTL 0x0054 432 #define regPHYCSYMCLK_CLOCK_CNTL_BASE_IDX 2 433 #define regPHYDSYMCLK_CLOCK_CNTL 0x0055 434 #define regPHYDSYMCLK_CLOCK_CNTL_BASE_IDX 2 435 #define regPHYESYMCLK_CLOCK_CNTL 0x0056 436 #define regPHYESYMCLK_CLOCK_CNTL_BASE_IDX 2 437 #define regDCCG_GATE_DISABLE_CNTL3 0x005a 438 #define regDCCG_GATE_DISABLE_CNTL3_BASE_IDX 2 439 #define regDCCG_AUDIO_DTBCLK_DTO_PHASE 0x0061 440 #define regDCCG_AUDIO_DTBCLK_DTO_PHASE_BASE_IDX 2 441 #define regDCCG_AUDIO_DTBCLK_DTO_MODULO 0x0062 442 #define regDCCG_AUDIO_DTBCLK_DTO_MODULO_BASE_IDX 2 443 #define regDTBCLK_DTO_DBUF_EN 0x0063 444 #define regDTBCLK_DTO_DBUF_EN_BASE_IDX 2 445 446 447 // addressBlock: dce_dc_dccg_dccg_dcperfmon0_dc_perfmon_dispdec 448 // base address: 0x0 449 #define regDC_PERFMON0_PERFCOUNTER_CNTL 0x0000 450 #define regDC_PERFMON0_PERFCOUNTER_CNTL_BASE_IDX 2 451 #define regDC_PERFMON0_PERFCOUNTER_CNTL2 0x0001 452 #define regDC_PERFMON0_PERFCOUNTER_CNTL2_BASE_IDX 2 453 #define regDC_PERFMON0_PERFCOUNTER_STATE 0x0002 454 #define regDC_PERFMON0_PERFCOUNTER_STATE_BASE_IDX 2 455 #define regDC_PERFMON0_PERFMON_CNTL 0x0003 456 #define regDC_PERFMON0_PERFMON_CNTL_BASE_IDX 2 457 #define regDC_PERFMON0_PERFMON_CNTL2 0x0004 458 #define regDC_PERFMON0_PERFMON_CNTL2_BASE_IDX 2 459 #define regDC_PERFMON0_PERFMON_CVALUE_INT_MISC 0x0005 460 #define regDC_PERFMON0_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 461 #define regDC_PERFMON0_PERFMON_CVALUE_LOW 0x0006 462 #define regDC_PERFMON0_PERFMON_CVALUE_LOW_BASE_IDX 2 463 #define regDC_PERFMON0_PERFMON_HI 0x0007 464 #define regDC_PERFMON0_PERFMON_HI_BASE_IDX 2 465 #define regDC_PERFMON0_PERFMON_LOW 0x0008 466 #define regDC_PERFMON0_PERFMON_LOW_BASE_IDX 2 467 468 469 // addressBlock: dce_dc_dccg_dccg_dcperfmon1_dc_perfmon_dispdec 470 // base address: 0x30 471 #define regDC_PERFMON1_PERFCOUNTER_CNTL 0x000c 472 #define regDC_PERFMON1_PERFCOUNTER_CNTL_BASE_IDX 2 473 #define regDC_PERFMON1_PERFCOUNTER_CNTL2 0x000d 474 #define regDC_PERFMON1_PERFCOUNTER_CNTL2_BASE_IDX 2 475 #define regDC_PERFMON1_PERFCOUNTER_STATE 0x000e 476 #define regDC_PERFMON1_PERFCOUNTER_STATE_BASE_IDX 2 477 #define regDC_PERFMON1_PERFMON_CNTL 0x000f 478 #define regDC_PERFMON1_PERFMON_CNTL_BASE_IDX 2 479 #define regDC_PERFMON1_PERFMON_CNTL2 0x0010 480 #define regDC_PERFMON1_PERFMON_CNTL2_BASE_IDX 2 481 #define regDC_PERFMON1_PERFMON_CVALUE_INT_MISC 0x0011 482 #define regDC_PERFMON1_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 483 #define regDC_PERFMON1_PERFMON_CVALUE_LOW 0x0012 484 #define regDC_PERFMON1_PERFMON_CVALUE_LOW_BASE_IDX 2 485 #define regDC_PERFMON1_PERFMON_HI 0x0013 486 #define regDC_PERFMON1_PERFMON_HI_BASE_IDX 2 487 #define regDC_PERFMON1_PERFMON_LOW 0x0014 488 #define regDC_PERFMON1_PERFMON_LOW_BASE_IDX 2 489 490 491 // addressBlock: dce_dc_dmu_dmcu_dispdec 492 // base address: 0x0 493 #define regDMCU_CTRL 0x00da 494 #define regDMCU_CTRL_BASE_IDX 2 495 #define regDMCU_STATUS 0x00db 496 #define regDMCU_STATUS_BASE_IDX 2 497 #define regDMCU_PC_START_ADDR 0x00dc 498 #define regDMCU_PC_START_ADDR_BASE_IDX 2 499 #define regDMCU_FW_START_ADDR 0x00dd 500 #define regDMCU_FW_START_ADDR_BASE_IDX 2 501 #define regDMCU_FW_END_ADDR 0x00de 502 #define regDMCU_FW_END_ADDR_BASE_IDX 2 503 #define regDMCU_FW_ISR_START_ADDR 0x00df 504 #define regDMCU_FW_ISR_START_ADDR_BASE_IDX 2 505 #define regDMCU_FW_CS_HI 0x00e0 506 #define regDMCU_FW_CS_HI_BASE_IDX 2 507 #define regDMCU_FW_CS_LO 0x00e1 508 #define regDMCU_FW_CS_LO_BASE_IDX 2 509 #define regDMCU_RAM_ACCESS_CTRL 0x00e2 510 #define regDMCU_RAM_ACCESS_CTRL_BASE_IDX 2 511 #define regDMCU_ERAM_WR_CTRL 0x00e3 512 #define regDMCU_ERAM_WR_CTRL_BASE_IDX 2 513 #define regDMCU_ERAM_WR_DATA 0x00e4 514 #define regDMCU_ERAM_WR_DATA_BASE_IDX 2 515 #define regDMCU_ERAM_RD_CTRL 0x00e5 516 #define regDMCU_ERAM_RD_CTRL_BASE_IDX 2 517 #define regDMCU_ERAM_RD_DATA 0x00e6 518 #define regDMCU_ERAM_RD_DATA_BASE_IDX 2 519 #define regDMCU_IRAM_WR_CTRL 0x00e7 520 #define regDMCU_IRAM_WR_CTRL_BASE_IDX 2 521 #define regDMCU_IRAM_WR_DATA 0x00e8 522 #define regDMCU_IRAM_WR_DATA_BASE_IDX 2 523 #define regDMCU_IRAM_RD_CTRL 0x00e9 524 #define regDMCU_IRAM_RD_CTRL_BASE_IDX 2 525 #define regDMCU_IRAM_RD_DATA 0x00ea 526 #define regDMCU_IRAM_RD_DATA_BASE_IDX 2 527 #define regDMCU_EVENT_TRIGGER 0x00eb 528 #define regDMCU_EVENT_TRIGGER_BASE_IDX 2 529 #define regDMCU_UC_INTERNAL_INT_STATUS 0x00ec 530 #define regDMCU_UC_INTERNAL_INT_STATUS_BASE_IDX 2 531 #define regDMCU_SS_INTERRUPT_CNTL_STATUS 0x00ed 532 #define regDMCU_SS_INTERRUPT_CNTL_STATUS_BASE_IDX 2 533 #define regDMCU_INTERRUPT_STATUS 0x00ee 534 #define regDMCU_INTERRUPT_STATUS_BASE_IDX 2 535 #define regDMCU_INTERRUPT_STATUS_1 0x00ef 536 #define regDMCU_INTERRUPT_STATUS_1_BASE_IDX 2 537 #define regDMCU_INTERRUPT_TO_HOST_EN_MASK 0x00f0 538 #define regDMCU_INTERRUPT_TO_HOST_EN_MASK_BASE_IDX 2 539 #define regDMCU_INTERRUPT_TO_UC_EN_MASK 0x00f1 540 #define regDMCU_INTERRUPT_TO_UC_EN_MASK_BASE_IDX 2 541 #define regDMCU_INTERRUPT_TO_UC_EN_MASK_1 0x00f2 542 #define regDMCU_INTERRUPT_TO_UC_EN_MASK_1_BASE_IDX 2 543 #define regDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL 0x00f3 544 #define regDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_BASE_IDX 2 545 #define regDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1 0x00f4 546 #define regDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1_BASE_IDX 2 547 #define regDC_DMCU_SCRATCH 0x00f5 548 #define regDC_DMCU_SCRATCH_BASE_IDX 2 549 #define regDMCU_INT_CNT 0x00f6 550 #define regDMCU_INT_CNT_BASE_IDX 2 551 #define regDMCU_FW_CHECKSUM_SMPL_BYTE_POS 0x00f7 552 #define regDMCU_FW_CHECKSUM_SMPL_BYTE_POS_BASE_IDX 2 553 #define regDMCU_UC_CLK_GATING_CNTL 0x00f8 554 #define regDMCU_UC_CLK_GATING_CNTL_BASE_IDX 2 555 #define regMASTER_COMM_DATA_REG1 0x00f9 556 #define regMASTER_COMM_DATA_REG1_BASE_IDX 2 557 #define regMASTER_COMM_DATA_REG2 0x00fa 558 #define regMASTER_COMM_DATA_REG2_BASE_IDX 2 559 #define regMASTER_COMM_DATA_REG3 0x00fb 560 #define regMASTER_COMM_DATA_REG3_BASE_IDX 2 561 #define regMASTER_COMM_CMD_REG 0x00fc 562 #define regMASTER_COMM_CMD_REG_BASE_IDX 2 563 #define regMASTER_COMM_CNTL_REG 0x00fd 564 #define regMASTER_COMM_CNTL_REG_BASE_IDX 2 565 #define regSLAVE_COMM_DATA_REG1 0x00fe 566 #define regSLAVE_COMM_DATA_REG1_BASE_IDX 2 567 #define regSLAVE_COMM_DATA_REG2 0x00ff 568 #define regSLAVE_COMM_DATA_REG2_BASE_IDX 2 569 #define regSLAVE_COMM_DATA_REG3 0x0100 570 #define regSLAVE_COMM_DATA_REG3_BASE_IDX 2 571 #define regSLAVE_COMM_CMD_REG 0x0101 572 #define regSLAVE_COMM_CMD_REG_BASE_IDX 2 573 #define regSLAVE_COMM_CNTL_REG 0x0102 574 #define regSLAVE_COMM_CNTL_REG_BASE_IDX 2 575 #define regDMCU_PERFMON_INTERRUPT_STATUS1 0x0105 576 #define regDMCU_PERFMON_INTERRUPT_STATUS1_BASE_IDX 2 577 #define regDMCU_PERFMON_INTERRUPT_STATUS2 0x0106 578 #define regDMCU_PERFMON_INTERRUPT_STATUS2_BASE_IDX 2 579 #define regDMCU_PERFMON_INTERRUPT_STATUS3 0x0107 580 #define regDMCU_PERFMON_INTERRUPT_STATUS3_BASE_IDX 2 581 #define regDMCU_PERFMON_INTERRUPT_STATUS4 0x0108 582 #define regDMCU_PERFMON_INTERRUPT_STATUS4_BASE_IDX 2 583 #define regDMCU_PERFMON_INTERRUPT_STATUS5 0x0109 584 #define regDMCU_PERFMON_INTERRUPT_STATUS5_BASE_IDX 2 585 #define regDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1 0x010a 586 #define regDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1_BASE_IDX 2 587 #define regDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2 0x010b 588 #define regDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2_BASE_IDX 2 589 #define regDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3 0x010c 590 #define regDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3_BASE_IDX 2 591 #define regDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4 0x010d 592 #define regDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4_BASE_IDX 2 593 #define regDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5 0x010e 594 #define regDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5_BASE_IDX 2 595 #define regDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1 0x010f 596 #define regDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1_BASE_IDX 2 597 #define regDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2 0x0110 598 #define regDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2_BASE_IDX 2 599 #define regDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3 0x0111 600 #define regDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3_BASE_IDX 2 601 #define regDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4 0x0112 602 #define regDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4_BASE_IDX 2 603 #define regDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5 0x0113 604 #define regDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5_BASE_IDX 2 605 #define regDMCU_DPRX_INTERRUPT_STATUS1 0x0114 606 #define regDMCU_DPRX_INTERRUPT_STATUS1_BASE_IDX 2 607 #define regDMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1 0x0115 608 #define regDMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1_BASE_IDX 2 609 #define regDMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1 0x0116 610 #define regDMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1_BASE_IDX 2 611 #define regDMCU_INTERRUPT_STATUS_CONTINUE 0x0119 612 #define regDMCU_INTERRUPT_STATUS_CONTINUE_BASE_IDX 2 613 #define regDMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE 0x011a 614 #define regDMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE_BASE_IDX 2 615 #define regDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE 0x011b 616 #define regDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE_BASE_IDX 2 617 #define regDMCU_INT_CNT_CONTINUE 0x011c 618 #define regDMCU_INT_CNT_CONTINUE_BASE_IDX 2 619 #define regDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2 0x011d 620 #define regDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2_BASE_IDX 2 621 #define regDMCU_INTERRUPT_STATUS_2 0x011e 622 #define regDMCU_INTERRUPT_STATUS_2_BASE_IDX 2 623 #define regDMCU_INTERRUPT_TO_UC_EN_MASK_2 0x011f 624 #define regDMCU_INTERRUPT_TO_UC_EN_MASK_2_BASE_IDX 2 625 #define regDMCU_INT_CNT_CONT2 0x0120 626 #define regDMCU_INT_CNT_CONT2_BASE_IDX 2 627 #define regDMCU_INT_CNT_CONT3 0x0121 628 #define regDMCU_INT_CNT_CONT3_BASE_IDX 2 629 630 631 // addressBlock: dce_dc_dmu_fgsec_dispdec 632 // base address: 0x0 633 #define regDMCUB_RBBMIF_SEC_CNTL 0x017a 634 #define regDMCUB_RBBMIF_SEC_CNTL_BASE_IDX 2 635 636 637 // addressBlock: dce_dc_dmu_rbbmif_dispdec 638 // base address: 0x0 639 #define regRBBMIF_TIMEOUT 0x017f 640 #define regRBBMIF_TIMEOUT_BASE_IDX 2 641 #define regRBBMIF_STATUS 0x0180 642 #define regRBBMIF_STATUS_BASE_IDX 2 643 #define regRBBMIF_STATUS_2 0x0181 644 #define regRBBMIF_STATUS_2_BASE_IDX 2 645 #define regRBBMIF_INT_STATUS 0x0182 646 #define regRBBMIF_INT_STATUS_BASE_IDX 2 647 #define regRBBMIF_TIMEOUT_DIS 0x0183 648 #define regRBBMIF_TIMEOUT_DIS_BASE_IDX 2 649 #define regRBBMIF_TIMEOUT_DIS_2 0x0184 650 #define regRBBMIF_TIMEOUT_DIS_2_BASE_IDX 2 651 #define regRBBMIF_STATUS_FLAG 0x0185 652 #define regRBBMIF_STATUS_FLAG_BASE_IDX 2 653 654 655 // addressBlock: dce_dc_dmu_dmu_dcperfmon_dc_perfmon_dispdec 656 // base address: 0x2f8 657 #define regDC_PERFMON2_PERFCOUNTER_CNTL 0x00be 658 #define regDC_PERFMON2_PERFCOUNTER_CNTL_BASE_IDX 2 659 #define regDC_PERFMON2_PERFCOUNTER_CNTL2 0x00bf 660 #define regDC_PERFMON2_PERFCOUNTER_CNTL2_BASE_IDX 2 661 #define regDC_PERFMON2_PERFCOUNTER_STATE 0x00c0 662 #define regDC_PERFMON2_PERFCOUNTER_STATE_BASE_IDX 2 663 #define regDC_PERFMON2_PERFMON_CNTL 0x00c1 664 #define regDC_PERFMON2_PERFMON_CNTL_BASE_IDX 2 665 #define regDC_PERFMON2_PERFMON_CNTL2 0x00c2 666 #define regDC_PERFMON2_PERFMON_CNTL2_BASE_IDX 2 667 #define regDC_PERFMON2_PERFMON_CVALUE_INT_MISC 0x00c3 668 #define regDC_PERFMON2_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 669 #define regDC_PERFMON2_PERFMON_CVALUE_LOW 0x00c4 670 #define regDC_PERFMON2_PERFMON_CVALUE_LOW_BASE_IDX 2 671 #define regDC_PERFMON2_PERFMON_HI 0x00c5 672 #define regDC_PERFMON2_PERFMON_HI_BASE_IDX 2 673 #define regDC_PERFMON2_PERFMON_LOW 0x00c6 674 #define regDC_PERFMON2_PERFMON_LOW_BASE_IDX 2 675 676 677 // addressBlock: dce_dc_dmu_ihc_dispdec 678 // base address: 0x0 679 #define regDC_GPU_TIMER_START_POSITION_V_UPDATE 0x0126 680 #define regDC_GPU_TIMER_START_POSITION_V_UPDATE_BASE_IDX 2 681 #define regDC_GPU_TIMER_START_POSITION_VSTARTUP 0x0127 682 #define regDC_GPU_TIMER_START_POSITION_VSTARTUP_BASE_IDX 2 683 #define regDC_GPU_TIMER_READ 0x0128 684 #define regDC_GPU_TIMER_READ_BASE_IDX 2 685 #define regDC_GPU_TIMER_READ_CNTL 0x0129 686 #define regDC_GPU_TIMER_READ_CNTL_BASE_IDX 2 687 #define regDISP_INTERRUPT_STATUS 0x012a 688 #define regDISP_INTERRUPT_STATUS_BASE_IDX 2 689 #define regDISP_INTERRUPT_STATUS_CONTINUE 0x012b 690 #define regDISP_INTERRUPT_STATUS_CONTINUE_BASE_IDX 2 691 #define regDISP_INTERRUPT_STATUS_CONTINUE2 0x012c 692 #define regDISP_INTERRUPT_STATUS_CONTINUE2_BASE_IDX 2 693 #define regDISP_INTERRUPT_STATUS_CONTINUE3 0x012d 694 #define regDISP_INTERRUPT_STATUS_CONTINUE3_BASE_IDX 2 695 #define regDISP_INTERRUPT_STATUS_CONTINUE4 0x012e 696 #define regDISP_INTERRUPT_STATUS_CONTINUE4_BASE_IDX 2 697 #define regDISP_INTERRUPT_STATUS_CONTINUE5 0x012f 698 #define regDISP_INTERRUPT_STATUS_CONTINUE5_BASE_IDX 2 699 #define regDISP_INTERRUPT_STATUS_CONTINUE6 0x0130 700 #define regDISP_INTERRUPT_STATUS_CONTINUE6_BASE_IDX 2 701 #define regDISP_INTERRUPT_STATUS_CONTINUE7 0x0131 702 #define regDISP_INTERRUPT_STATUS_CONTINUE7_BASE_IDX 2 703 #define regDISP_INTERRUPT_STATUS_CONTINUE8 0x0132 704 #define regDISP_INTERRUPT_STATUS_CONTINUE8_BASE_IDX 2 705 #define regDISP_INTERRUPT_STATUS_CONTINUE9 0x0133 706 #define regDISP_INTERRUPT_STATUS_CONTINUE9_BASE_IDX 2 707 #define regDISP_INTERRUPT_STATUS_CONTINUE10 0x0134 708 #define regDISP_INTERRUPT_STATUS_CONTINUE10_BASE_IDX 2 709 #define regDISP_INTERRUPT_STATUS_CONTINUE11 0x0135 710 #define regDISP_INTERRUPT_STATUS_CONTINUE11_BASE_IDX 2 711 #define regDISP_INTERRUPT_STATUS_CONTINUE12 0x0136 712 #define regDISP_INTERRUPT_STATUS_CONTINUE12_BASE_IDX 2 713 #define regDISP_INTERRUPT_STATUS_CONTINUE13 0x0137 714 #define regDISP_INTERRUPT_STATUS_CONTINUE13_BASE_IDX 2 715 #define regDISP_INTERRUPT_STATUS_CONTINUE14 0x0138 716 #define regDISP_INTERRUPT_STATUS_CONTINUE14_BASE_IDX 2 717 #define regDISP_INTERRUPT_STATUS_CONTINUE15 0x0139 718 #define regDISP_INTERRUPT_STATUS_CONTINUE15_BASE_IDX 2 719 #define regDISP_INTERRUPT_STATUS_CONTINUE16 0x013a 720 #define regDISP_INTERRUPT_STATUS_CONTINUE16_BASE_IDX 2 721 #define regDISP_INTERRUPT_STATUS_CONTINUE17 0x013b 722 #define regDISP_INTERRUPT_STATUS_CONTINUE17_BASE_IDX 2 723 #define regDISP_INTERRUPT_STATUS_CONTINUE18 0x013c 724 #define regDISP_INTERRUPT_STATUS_CONTINUE18_BASE_IDX 2 725 #define regDISP_INTERRUPT_STATUS_CONTINUE19 0x013d 726 #define regDISP_INTERRUPT_STATUS_CONTINUE19_BASE_IDX 2 727 #define regDISP_INTERRUPT_STATUS_CONTINUE20 0x013e 728 #define regDISP_INTERRUPT_STATUS_CONTINUE20_BASE_IDX 2 729 #define regDISP_INTERRUPT_STATUS_CONTINUE21 0x013f 730 #define regDISP_INTERRUPT_STATUS_CONTINUE21_BASE_IDX 2 731 #define regDISP_INTERRUPT_STATUS_CONTINUE22 0x0140 732 #define regDISP_INTERRUPT_STATUS_CONTINUE22_BASE_IDX 2 733 #define regDC_GPU_TIMER_START_POSITION_VREADY 0x0141 734 #define regDC_GPU_TIMER_START_POSITION_VREADY_BASE_IDX 2 735 #define regDC_GPU_TIMER_START_POSITION_FLIP 0x0142 736 #define regDC_GPU_TIMER_START_POSITION_FLIP_BASE_IDX 2 737 #define regDC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK 0x0143 738 #define regDC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK_BASE_IDX 2 739 #define regDC_GPU_TIMER_START_POSITION_FLIP_AWAY 0x0144 740 #define regDC_GPU_TIMER_START_POSITION_FLIP_AWAY_BASE_IDX 2 741 #define regDISP_INTERRUPT_STATUS_CONTINUE23 0x0145 742 #define regDISP_INTERRUPT_STATUS_CONTINUE23_BASE_IDX 2 743 #define regDISP_INTERRUPT_STATUS_CONTINUE24 0x0146 744 #define regDISP_INTERRUPT_STATUS_CONTINUE24_BASE_IDX 2 745 #define regDISP_INTERRUPT_STATUS_CONTINUE25 0x0147 746 #define regDISP_INTERRUPT_STATUS_CONTINUE25_BASE_IDX 2 747 #define regDCCG_INTERRUPT_DEST 0x0148 748 #define regDCCG_INTERRUPT_DEST_BASE_IDX 2 749 #define regDMU_INTERRUPT_DEST 0x0149 750 #define regDMU_INTERRUPT_DEST_BASE_IDX 2 751 #define regDMU_INTERRUPT_DEST2 0x014a 752 #define regDMU_INTERRUPT_DEST2_BASE_IDX 2 753 #define regDCPG_INTERRUPT_DEST 0x014b 754 #define regDCPG_INTERRUPT_DEST_BASE_IDX 2 755 #define regDCPG_INTERRUPT_DEST2 0x014c 756 #define regDCPG_INTERRUPT_DEST2_BASE_IDX 2 757 #define regMMHUBBUB_INTERRUPT_DEST 0x014d 758 #define regMMHUBBUB_INTERRUPT_DEST_BASE_IDX 2 759 #define regWB_INTERRUPT_DEST 0x014e 760 #define regWB_INTERRUPT_DEST_BASE_IDX 2 761 #define regDCHUB_INTERRUPT_DEST 0x014f 762 #define regDCHUB_INTERRUPT_DEST_BASE_IDX 2 763 #define regDCHUB_PERFCOUNTER_INTERRUPT_DEST 0x0150 764 #define regDCHUB_PERFCOUNTER_INTERRUPT_DEST_BASE_IDX 2 765 #define regDCHUB_INTERRUPT_DEST2 0x0151 766 #define regDCHUB_INTERRUPT_DEST2_BASE_IDX 2 767 #define regDPP_PERFCOUNTER_INTERRUPT_DEST 0x0152 768 #define regDPP_PERFCOUNTER_INTERRUPT_DEST_BASE_IDX 2 769 #define regMPC_INTERRUPT_DEST 0x0153 770 #define regMPC_INTERRUPT_DEST_BASE_IDX 2 771 #define regOPP_INTERRUPT_DEST 0x0154 772 #define regOPP_INTERRUPT_DEST_BASE_IDX 2 773 #define regOPTC_INTERRUPT_DEST 0x0155 774 #define regOPTC_INTERRUPT_DEST_BASE_IDX 2 775 #define regOTG0_INTERRUPT_DEST 0x0156 776 #define regOTG0_INTERRUPT_DEST_BASE_IDX 2 777 #define regOTG1_INTERRUPT_DEST 0x0157 778 #define regOTG1_INTERRUPT_DEST_BASE_IDX 2 779 #define regOTG2_INTERRUPT_DEST 0x0158 780 #define regOTG2_INTERRUPT_DEST_BASE_IDX 2 781 #define regOTG3_INTERRUPT_DEST 0x0159 782 #define regOTG3_INTERRUPT_DEST_BASE_IDX 2 783 #define regOTG4_INTERRUPT_DEST 0x015a 784 #define regOTG4_INTERRUPT_DEST_BASE_IDX 2 785 #define regOTG5_INTERRUPT_DEST 0x015b 786 #define regOTG5_INTERRUPT_DEST_BASE_IDX 2 787 #define regDIG_INTERRUPT_DEST 0x015c 788 #define regDIG_INTERRUPT_DEST_BASE_IDX 2 789 #define regI2C_DDC_HPD_INTERRUPT_DEST 0x015d 790 #define regI2C_DDC_HPD_INTERRUPT_DEST_BASE_IDX 2 791 #define regDIO_INTERRUPT_DEST 0x015f 792 #define regDIO_INTERRUPT_DEST_BASE_IDX 2 793 #define regDCIO_INTERRUPT_DEST 0x0160 794 #define regDCIO_INTERRUPT_DEST_BASE_IDX 2 795 #define regHPD_INTERRUPT_DEST 0x0161 796 #define regHPD_INTERRUPT_DEST_BASE_IDX 2 797 #define regAZ_INTERRUPT_DEST 0x0162 798 #define regAZ_INTERRUPT_DEST_BASE_IDX 2 799 #define regAUX_INTERRUPT_DEST 0x0163 800 #define regAUX_INTERRUPT_DEST_BASE_IDX 2 801 #define regDSC_INTERRUPT_DEST 0x0164 802 #define regDSC_INTERRUPT_DEST_BASE_IDX 2 803 #define regHPO_INTERRUPT_DEST 0x0165 804 #define regHPO_INTERRUPT_DEST_BASE_IDX 2 805 806 807 // addressBlock: dce_dc_dmu_dmu_misc_dispdec 808 // base address: 0x0 809 #define regCC_DC_PIPE_DIS 0x00ca 810 #define regCC_DC_PIPE_DIS_BASE_IDX 2 811 #define regDMU_CLK_CNTL 0x00cb 812 #define regDMU_CLK_CNTL_BASE_IDX 2 813 #define regDMU_MEM_PWR_CNTL 0x00cc 814 #define regDMU_MEM_PWR_CNTL_BASE_IDX 2 815 #define regDMCU_SMU_INTERRUPT_CNTL 0x00cd 816 #define regDMCU_SMU_INTERRUPT_CNTL_BASE_IDX 2 817 #define regSMU_INTERRUPT_CONTROL 0x00ce 818 #define regSMU_INTERRUPT_CONTROL_BASE_IDX 2 819 #define regZSC_CNTL 0x00cf 820 #define regZSC_CNTL_BASE_IDX 2 821 #define regZSC_CNTL2 0x00d0 822 #define regZSC_CNTL2_BASE_IDX 2 823 #define regDMU_MISC_ALLOW_DS_FORCE 0x00d6 824 #define regDMU_MISC_ALLOW_DS_FORCE_BASE_IDX 2 825 #define regZSC_STATUS 0x00d7 826 #define regZSC_STATUS_BASE_IDX 2 827 828 829 // addressBlock: dce_dc_dmu_dc_pg_dispdec 830 // base address: 0x0 831 #define regDOMAIN0_PG_CONFIG 0x0080 832 #define regDOMAIN0_PG_CONFIG_BASE_IDX 2 833 #define regDOMAIN0_PG_STATUS 0x0081 834 #define regDOMAIN0_PG_STATUS_BASE_IDX 2 835 #define regDOMAIN1_PG_CONFIG 0x0082 836 #define regDOMAIN1_PG_CONFIG_BASE_IDX 2 837 #define regDOMAIN1_PG_STATUS 0x0083 838 #define regDOMAIN1_PG_STATUS_BASE_IDX 2 839 #define regDOMAIN2_PG_CONFIG 0x0084 840 #define regDOMAIN2_PG_CONFIG_BASE_IDX 2 841 #define regDOMAIN2_PG_STATUS 0x0085 842 #define regDOMAIN2_PG_STATUS_BASE_IDX 2 843 #define regDOMAIN3_PG_CONFIG 0x0086 844 #define regDOMAIN3_PG_CONFIG_BASE_IDX 2 845 #define regDOMAIN3_PG_STATUS 0x0087 846 #define regDOMAIN3_PG_STATUS_BASE_IDX 2 847 #define regDOMAIN16_PG_CONFIG 0x0089 848 #define regDOMAIN16_PG_CONFIG_BASE_IDX 2 849 #define regDOMAIN16_PG_STATUS 0x008a 850 #define regDOMAIN16_PG_STATUS_BASE_IDX 2 851 #define regDOMAIN17_PG_CONFIG 0x008b 852 #define regDOMAIN17_PG_CONFIG_BASE_IDX 2 853 #define regDOMAIN17_PG_STATUS 0x008c 854 #define regDOMAIN17_PG_STATUS_BASE_IDX 2 855 #define regDOMAIN18_PG_CONFIG 0x008d 856 #define regDOMAIN18_PG_CONFIG_BASE_IDX 2 857 #define regDOMAIN18_PG_STATUS 0x008e 858 #define regDOMAIN18_PG_STATUS_BASE_IDX 2 859 #define regDCPG_INTERRUPT_STATUS 0x008f 860 #define regDCPG_INTERRUPT_STATUS_BASE_IDX 2 861 #define regDCPG_INTERRUPT_STATUS_2 0x0090 862 #define regDCPG_INTERRUPT_STATUS_2_BASE_IDX 2 863 #define regDCPG_INTERRUPT_CONTROL_1 0x0091 864 #define regDCPG_INTERRUPT_CONTROL_1_BASE_IDX 2 865 #define regDCPG_INTERRUPT_CONTROL_3 0x0092 866 #define regDCPG_INTERRUPT_CONTROL_3_BASE_IDX 2 867 #define regDC_IP_REQUEST_CNTL 0x0093 868 #define regDC_IP_REQUEST_CNTL_BASE_IDX 2 869 870 871 // addressBlock: dce_dc_dmu_dmcub_dispdec 872 // base address: 0x0 873 #define regDMCUB_REGION0_OFFSET 0x018e 874 #define regDMCUB_REGION0_OFFSET_BASE_IDX 2 875 #define regDMCUB_REGION0_OFFSET_HIGH 0x018f 876 #define regDMCUB_REGION0_OFFSET_HIGH_BASE_IDX 2 877 #define regDMCUB_REGION1_OFFSET 0x0190 878 #define regDMCUB_REGION1_OFFSET_BASE_IDX 2 879 #define regDMCUB_REGION1_OFFSET_HIGH 0x0191 880 #define regDMCUB_REGION1_OFFSET_HIGH_BASE_IDX 2 881 #define regDMCUB_REGION2_OFFSET 0x0192 882 #define regDMCUB_REGION2_OFFSET_BASE_IDX 2 883 #define regDMCUB_REGION2_OFFSET_HIGH 0x0193 884 #define regDMCUB_REGION2_OFFSET_HIGH_BASE_IDX 2 885 #define regDMCUB_REGION4_OFFSET 0x0196 886 #define regDMCUB_REGION4_OFFSET_BASE_IDX 2 887 #define regDMCUB_REGION4_OFFSET_HIGH 0x0197 888 #define regDMCUB_REGION4_OFFSET_HIGH_BASE_IDX 2 889 #define regDMCUB_REGION5_OFFSET 0x0198 890 #define regDMCUB_REGION5_OFFSET_BASE_IDX 2 891 #define regDMCUB_REGION5_OFFSET_HIGH 0x0199 892 #define regDMCUB_REGION5_OFFSET_HIGH_BASE_IDX 2 893 #define regDMCUB_REGION6_OFFSET 0x019a 894 #define regDMCUB_REGION6_OFFSET_BASE_IDX 2 895 #define regDMCUB_REGION6_OFFSET_HIGH 0x019b 896 #define regDMCUB_REGION6_OFFSET_HIGH_BASE_IDX 2 897 #define regDMCUB_REGION7_OFFSET 0x019c 898 #define regDMCUB_REGION7_OFFSET_BASE_IDX 2 899 #define regDMCUB_REGION7_OFFSET_HIGH 0x019d 900 #define regDMCUB_REGION7_OFFSET_HIGH_BASE_IDX 2 901 #define regDMCUB_REGION0_TOP_ADDRESS 0x019e 902 #define regDMCUB_REGION0_TOP_ADDRESS_BASE_IDX 2 903 #define regDMCUB_REGION1_TOP_ADDRESS 0x019f 904 #define regDMCUB_REGION1_TOP_ADDRESS_BASE_IDX 2 905 #define regDMCUB_REGION2_TOP_ADDRESS 0x01a0 906 #define regDMCUB_REGION2_TOP_ADDRESS_BASE_IDX 2 907 #define regDMCUB_REGION4_TOP_ADDRESS 0x01a1 908 #define regDMCUB_REGION4_TOP_ADDRESS_BASE_IDX 2 909 #define regDMCUB_REGION5_TOP_ADDRESS 0x01a2 910 #define regDMCUB_REGION5_TOP_ADDRESS_BASE_IDX 2 911 #define regDMCUB_REGION6_TOP_ADDRESS 0x01a3 912 #define regDMCUB_REGION6_TOP_ADDRESS_BASE_IDX 2 913 #define regDMCUB_REGION7_TOP_ADDRESS 0x01a4 914 #define regDMCUB_REGION7_TOP_ADDRESS_BASE_IDX 2 915 #define regDMCUB_REGION3_CW0_BASE_ADDRESS 0x01a5 916 #define regDMCUB_REGION3_CW0_BASE_ADDRESS_BASE_IDX 2 917 #define regDMCUB_REGION3_CW1_BASE_ADDRESS 0x01a6 918 #define regDMCUB_REGION3_CW1_BASE_ADDRESS_BASE_IDX 2 919 #define regDMCUB_REGION3_CW2_BASE_ADDRESS 0x01a7 920 #define regDMCUB_REGION3_CW2_BASE_ADDRESS_BASE_IDX 2 921 #define regDMCUB_REGION3_CW3_BASE_ADDRESS 0x01a8 922 #define regDMCUB_REGION3_CW3_BASE_ADDRESS_BASE_IDX 2 923 #define regDMCUB_REGION3_CW4_BASE_ADDRESS 0x01a9 924 #define regDMCUB_REGION3_CW4_BASE_ADDRESS_BASE_IDX 2 925 #define regDMCUB_REGION3_CW5_BASE_ADDRESS 0x01aa 926 #define regDMCUB_REGION3_CW5_BASE_ADDRESS_BASE_IDX 2 927 #define regDMCUB_REGION3_CW6_BASE_ADDRESS 0x01ab 928 #define regDMCUB_REGION3_CW6_BASE_ADDRESS_BASE_IDX 2 929 #define regDMCUB_REGION3_CW7_BASE_ADDRESS 0x01ac 930 #define regDMCUB_REGION3_CW7_BASE_ADDRESS_BASE_IDX 2 931 #define regDMCUB_REGION3_CW0_TOP_ADDRESS 0x01ad 932 #define regDMCUB_REGION3_CW0_TOP_ADDRESS_BASE_IDX 2 933 #define regDMCUB_REGION3_CW1_TOP_ADDRESS 0x01ae 934 #define regDMCUB_REGION3_CW1_TOP_ADDRESS_BASE_IDX 2 935 #define regDMCUB_REGION3_CW2_TOP_ADDRESS 0x01af 936 #define regDMCUB_REGION3_CW2_TOP_ADDRESS_BASE_IDX 2 937 #define regDMCUB_REGION3_CW3_TOP_ADDRESS 0x01b0 938 #define regDMCUB_REGION3_CW3_TOP_ADDRESS_BASE_IDX 2 939 #define regDMCUB_REGION3_CW4_TOP_ADDRESS 0x01b1 940 #define regDMCUB_REGION3_CW4_TOP_ADDRESS_BASE_IDX 2 941 #define regDMCUB_REGION3_CW5_TOP_ADDRESS 0x01b2 942 #define regDMCUB_REGION3_CW5_TOP_ADDRESS_BASE_IDX 2 943 #define regDMCUB_REGION3_CW6_TOP_ADDRESS 0x01b3 944 #define regDMCUB_REGION3_CW6_TOP_ADDRESS_BASE_IDX 2 945 #define regDMCUB_REGION3_CW7_TOP_ADDRESS 0x01b4 946 #define regDMCUB_REGION3_CW7_TOP_ADDRESS_BASE_IDX 2 947 #define regDMCUB_REGION3_CW0_OFFSET 0x01b5 948 #define regDMCUB_REGION3_CW0_OFFSET_BASE_IDX 2 949 #define regDMCUB_REGION3_CW0_OFFSET_HIGH 0x01b6 950 #define regDMCUB_REGION3_CW0_OFFSET_HIGH_BASE_IDX 2 951 #define regDMCUB_REGION3_CW1_OFFSET 0x01b7 952 #define regDMCUB_REGION3_CW1_OFFSET_BASE_IDX 2 953 #define regDMCUB_REGION3_CW1_OFFSET_HIGH 0x01b8 954 #define regDMCUB_REGION3_CW1_OFFSET_HIGH_BASE_IDX 2 955 #define regDMCUB_REGION3_CW2_OFFSET 0x01b9 956 #define regDMCUB_REGION3_CW2_OFFSET_BASE_IDX 2 957 #define regDMCUB_REGION3_CW2_OFFSET_HIGH 0x01ba 958 #define regDMCUB_REGION3_CW2_OFFSET_HIGH_BASE_IDX 2 959 #define regDMCUB_REGION3_CW3_OFFSET 0x01bb 960 #define regDMCUB_REGION3_CW3_OFFSET_BASE_IDX 2 961 #define regDMCUB_REGION3_CW3_OFFSET_HIGH 0x01bc 962 #define regDMCUB_REGION3_CW3_OFFSET_HIGH_BASE_IDX 2 963 #define regDMCUB_REGION3_CW4_OFFSET 0x01bd 964 #define regDMCUB_REGION3_CW4_OFFSET_BASE_IDX 2 965 #define regDMCUB_REGION3_CW4_OFFSET_HIGH 0x01be 966 #define regDMCUB_REGION3_CW4_OFFSET_HIGH_BASE_IDX 2 967 #define regDMCUB_REGION3_CW5_OFFSET 0x01bf 968 #define regDMCUB_REGION3_CW5_OFFSET_BASE_IDX 2 969 #define regDMCUB_REGION3_CW5_OFFSET_HIGH 0x01c0 970 #define regDMCUB_REGION3_CW5_OFFSET_HIGH_BASE_IDX 2 971 #define regDMCUB_REGION3_CW6_OFFSET 0x01c1 972 #define regDMCUB_REGION3_CW6_OFFSET_BASE_IDX 2 973 #define regDMCUB_REGION3_CW6_OFFSET_HIGH 0x01c2 974 #define regDMCUB_REGION3_CW6_OFFSET_HIGH_BASE_IDX 2 975 #define regDMCUB_REGION3_CW7_OFFSET 0x01c3 976 #define regDMCUB_REGION3_CW7_OFFSET_BASE_IDX 2 977 #define regDMCUB_REGION3_CW7_OFFSET_HIGH 0x01c4 978 #define regDMCUB_REGION3_CW7_OFFSET_HIGH_BASE_IDX 2 979 #define regDMCUB_INTERRUPT_ENABLE 0x01c5 980 #define regDMCUB_INTERRUPT_ENABLE_BASE_IDX 2 981 #define regDMCUB_INTERRUPT_ACK 0x01c6 982 #define regDMCUB_INTERRUPT_ACK_BASE_IDX 2 983 #define regDMCUB_INTERRUPT_STATUS 0x01c7 984 #define regDMCUB_INTERRUPT_STATUS_BASE_IDX 2 985 #define regDMCUB_INTERRUPT_TYPE 0x01c8 986 #define regDMCUB_INTERRUPT_TYPE_BASE_IDX 2 987 #define regDMCUB_EXT_INTERRUPT_STATUS 0x01c9 988 #define regDMCUB_EXT_INTERRUPT_STATUS_BASE_IDX 2 989 #define regDMCUB_EXT_INTERRUPT_CTXID 0x01ca 990 #define regDMCUB_EXT_INTERRUPT_CTXID_BASE_IDX 2 991 #define regDMCUB_EXT_INTERRUPT_ACK 0x01cb 992 #define regDMCUB_EXT_INTERRUPT_ACK_BASE_IDX 2 993 #define regDMCUB_INST_FETCH_FAULT_ADDR 0x01cc 994 #define regDMCUB_INST_FETCH_FAULT_ADDR_BASE_IDX 2 995 #define regDMCUB_DATA_WRITE_FAULT_ADDR 0x01cd 996 #define regDMCUB_DATA_WRITE_FAULT_ADDR_BASE_IDX 2 997 #define regDMCUB_SEC_CNTL 0x01ce 998 #define regDMCUB_SEC_CNTL_BASE_IDX 2 999 #define regDMCUB_MEM_CNTL 0x01cf 1000 #define regDMCUB_MEM_CNTL_BASE_IDX 2 1001 #define regDMCUB_INBOX0_BASE_ADDRESS 0x01d0 1002 #define regDMCUB_INBOX0_BASE_ADDRESS_BASE_IDX 2 1003 #define regDMCUB_INBOX0_SIZE 0x01d1 1004 #define regDMCUB_INBOX0_SIZE_BASE_IDX 2 1005 #define regDMCUB_INBOX0_WPTR 0x01d2 1006 #define regDMCUB_INBOX0_WPTR_BASE_IDX 2 1007 #define regDMCUB_INBOX0_RPTR 0x01d3 1008 #define regDMCUB_INBOX0_RPTR_BASE_IDX 2 1009 #define regDMCUB_INBOX1_BASE_ADDRESS 0x01d4 1010 #define regDMCUB_INBOX1_BASE_ADDRESS_BASE_IDX 2 1011 #define regDMCUB_INBOX1_SIZE 0x01d5 1012 #define regDMCUB_INBOX1_SIZE_BASE_IDX 2 1013 #define regDMCUB_INBOX1_WPTR 0x01d6 1014 #define regDMCUB_INBOX1_WPTR_BASE_IDX 2 1015 #define regDMCUB_INBOX1_RPTR 0x01d7 1016 #define regDMCUB_INBOX1_RPTR_BASE_IDX 2 1017 #define regDMCUB_OUTBOX0_BASE_ADDRESS 0x01d8 1018 #define regDMCUB_OUTBOX0_BASE_ADDRESS_BASE_IDX 2 1019 #define regDMCUB_OUTBOX0_SIZE 0x01d9 1020 #define regDMCUB_OUTBOX0_SIZE_BASE_IDX 2 1021 #define regDMCUB_OUTBOX0_WPTR 0x01da 1022 #define regDMCUB_OUTBOX0_WPTR_BASE_IDX 2 1023 #define regDMCUB_OUTBOX0_RPTR 0x01db 1024 #define regDMCUB_OUTBOX0_RPTR_BASE_IDX 2 1025 #define regDMCUB_OUTBOX1_BASE_ADDRESS 0x01dc 1026 #define regDMCUB_OUTBOX1_BASE_ADDRESS_BASE_IDX 2 1027 #define regDMCUB_OUTBOX1_SIZE 0x01dd 1028 #define regDMCUB_OUTBOX1_SIZE_BASE_IDX 2 1029 #define regDMCUB_OUTBOX1_WPTR 0x01de 1030 #define regDMCUB_OUTBOX1_WPTR_BASE_IDX 2 1031 #define regDMCUB_OUTBOX1_RPTR 0x01df 1032 #define regDMCUB_OUTBOX1_RPTR_BASE_IDX 2 1033 #define regDMCUB_TIMER_TRIGGER0 0x01e0 1034 #define regDMCUB_TIMER_TRIGGER0_BASE_IDX 2 1035 #define regDMCUB_TIMER_TRIGGER1 0x01e1 1036 #define regDMCUB_TIMER_TRIGGER1_BASE_IDX 2 1037 #define regDMCUB_TIMER_WINDOW 0x01e2 1038 #define regDMCUB_TIMER_WINDOW_BASE_IDX 2 1039 #define regDMCUB_SCRATCH0 0x01e3 1040 #define regDMCUB_SCRATCH0_BASE_IDX 2 1041 #define regDMCUB_SCRATCH1 0x01e4 1042 #define regDMCUB_SCRATCH1_BASE_IDX 2 1043 #define regDMCUB_SCRATCH2 0x01e5 1044 #define regDMCUB_SCRATCH2_BASE_IDX 2 1045 #define regDMCUB_SCRATCH3 0x01e6 1046 #define regDMCUB_SCRATCH3_BASE_IDX 2 1047 #define regDMCUB_SCRATCH4 0x01e7 1048 #define regDMCUB_SCRATCH4_BASE_IDX 2 1049 #define regDMCUB_SCRATCH5 0x01e8 1050 #define regDMCUB_SCRATCH5_BASE_IDX 2 1051 #define regDMCUB_SCRATCH6 0x01e9 1052 #define regDMCUB_SCRATCH6_BASE_IDX 2 1053 #define regDMCUB_SCRATCH7 0x01ea 1054 #define regDMCUB_SCRATCH7_BASE_IDX 2 1055 #define regDMCUB_SCRATCH8 0x01eb 1056 #define regDMCUB_SCRATCH8_BASE_IDX 2 1057 #define regDMCUB_SCRATCH9 0x01ec 1058 #define regDMCUB_SCRATCH9_BASE_IDX 2 1059 #define regDMCUB_SCRATCH10 0x01ed 1060 #define regDMCUB_SCRATCH10_BASE_IDX 2 1061 #define regDMCUB_SCRATCH11 0x01ee 1062 #define regDMCUB_SCRATCH11_BASE_IDX 2 1063 #define regDMCUB_SCRATCH12 0x01ef 1064 #define regDMCUB_SCRATCH12_BASE_IDX 2 1065 #define regDMCUB_SCRATCH13 0x01f0 1066 #define regDMCUB_SCRATCH13_BASE_IDX 2 1067 #define regDMCUB_SCRATCH14 0x01f1 1068 #define regDMCUB_SCRATCH14_BASE_IDX 2 1069 #define regDMCUB_SCRATCH15 0x01f2 1070 #define regDMCUB_SCRATCH15_BASE_IDX 2 1071 #define regDMCUB_CNTL 0x01f6 1072 #define regDMCUB_CNTL_BASE_IDX 2 1073 #define regDMCUB_GPINT_DATAIN0 0x01f7 1074 #define regDMCUB_GPINT_DATAIN0_BASE_IDX 2 1075 #define regDMCUB_GPINT_DATAIN1 0x01f8 1076 #define regDMCUB_GPINT_DATAIN1_BASE_IDX 2 1077 #define regDMCUB_GPINT_DATAOUT 0x01f9 1078 #define regDMCUB_GPINT_DATAOUT_BASE_IDX 2 1079 #define regDMCUB_UNDEFINED_ADDRESS_FAULT_ADDR 0x01fa 1080 #define regDMCUB_UNDEFINED_ADDRESS_FAULT_ADDR_BASE_IDX 2 1081 #define regDMCUB_LS_WAKE_INT_ENABLE 0x01fb 1082 #define regDMCUB_LS_WAKE_INT_ENABLE_BASE_IDX 2 1083 #define regDMCUB_MEM_PWR_CNTL 0x01fc 1084 #define regDMCUB_MEM_PWR_CNTL_BASE_IDX 2 1085 #define regDMCUB_TIMER_CURRENT 0x01fd 1086 #define regDMCUB_TIMER_CURRENT_BASE_IDX 2 1087 #define regDMCUB_PROC_ID 0x01ff 1088 #define regDMCUB_PROC_ID_BASE_IDX 2 1089 #define regDMCUB_CNTL2 0x0200 1090 #define regDMCUB_CNTL2_BASE_IDX 2 1091 1092 1093 // addressBlock: dce_dc_wb0_dispdec_dwb_top_dispdec 1094 // base address: 0x0 1095 #define regDWB_ENABLE_CLK_CTRL 0x3228 1096 #define regDWB_ENABLE_CLK_CTRL_BASE_IDX 2 1097 #define regDWB_MEM_PWR_CTRL 0x3229 1098 #define regDWB_MEM_PWR_CTRL_BASE_IDX 2 1099 #define regFC_MODE_CTRL 0x322a 1100 #define regFC_MODE_CTRL_BASE_IDX 2 1101 #define regFC_FLOW_CTRL 0x322b 1102 #define regFC_FLOW_CTRL_BASE_IDX 2 1103 #define regFC_WINDOW_START 0x322c 1104 #define regFC_WINDOW_START_BASE_IDX 2 1105 #define regFC_WINDOW_SIZE 0x322d 1106 #define regFC_WINDOW_SIZE_BASE_IDX 2 1107 #define regFC_SOURCE_SIZE 0x322e 1108 #define regFC_SOURCE_SIZE_BASE_IDX 2 1109 #define regDWB_UPDATE_CTRL 0x322f 1110 #define regDWB_UPDATE_CTRL_BASE_IDX 2 1111 #define regDWB_CRC_CTRL 0x3230 1112 #define regDWB_CRC_CTRL_BASE_IDX 2 1113 #define regDWB_CRC_MASK_R_G 0x3231 1114 #define regDWB_CRC_MASK_R_G_BASE_IDX 2 1115 #define regDWB_CRC_MASK_B_A 0x3232 1116 #define regDWB_CRC_MASK_B_A_BASE_IDX 2 1117 #define regDWB_CRC_VAL_R_G 0x3233 1118 #define regDWB_CRC_VAL_R_G_BASE_IDX 2 1119 #define regDWB_CRC_VAL_B_A 0x3234 1120 #define regDWB_CRC_VAL_B_A_BASE_IDX 2 1121 #define regDWB_OUT_CTRL 0x3235 1122 #define regDWB_OUT_CTRL_BASE_IDX 2 1123 #define regDWB_MMHUBBUB_BACKPRESSURE_CNT_EN 0x3236 1124 #define regDWB_MMHUBBUB_BACKPRESSURE_CNT_EN_BASE_IDX 2 1125 #define regDWB_MMHUBBUB_BACKPRESSURE_CNT 0x3237 1126 #define regDWB_MMHUBBUB_BACKPRESSURE_CNT_BASE_IDX 2 1127 #define regDWB_HOST_READ_CONTROL 0x3238 1128 #define regDWB_HOST_READ_CONTROL_BASE_IDX 2 1129 #define regDWB_OVERFLOW_STATUS 0x3239 1130 #define regDWB_OVERFLOW_STATUS_BASE_IDX 2 1131 #define regDWB_OVERFLOW_COUNTER 0x323a 1132 #define regDWB_OVERFLOW_COUNTER_BASE_IDX 2 1133 #define regDWB_SOFT_RESET 0x323b 1134 #define regDWB_SOFT_RESET_BASE_IDX 2 1135 #define regDWB_DEBUG_CTRL 0x323c 1136 #define regDWB_DEBUG_CTRL_BASE_IDX 2 1137 1138 1139 // addressBlock: dce_dc_wb0_dispdec_dwbcp_dispdec 1140 // base address: 0x0 1141 #define regDWB_HDR_MULT_COEF 0x3294 1142 #define regDWB_HDR_MULT_COEF_BASE_IDX 2 1143 #define regDWB_GAMUT_REMAP_MODE 0x3295 1144 #define regDWB_GAMUT_REMAP_MODE_BASE_IDX 2 1145 #define regDWB_GAMUT_REMAP_COEF_FORMAT 0x3296 1146 #define regDWB_GAMUT_REMAP_COEF_FORMAT_BASE_IDX 2 1147 #define regDWB_GAMUT_REMAPA_C11_C12 0x3297 1148 #define regDWB_GAMUT_REMAPA_C11_C12_BASE_IDX 2 1149 #define regDWB_GAMUT_REMAPA_C13_C14 0x3298 1150 #define regDWB_GAMUT_REMAPA_C13_C14_BASE_IDX 2 1151 #define regDWB_GAMUT_REMAPA_C21_C22 0x3299 1152 #define regDWB_GAMUT_REMAPA_C21_C22_BASE_IDX 2 1153 #define regDWB_GAMUT_REMAPA_C23_C24 0x329a 1154 #define regDWB_GAMUT_REMAPA_C23_C24_BASE_IDX 2 1155 #define regDWB_GAMUT_REMAPA_C31_C32 0x329b 1156 #define regDWB_GAMUT_REMAPA_C31_C32_BASE_IDX 2 1157 #define regDWB_GAMUT_REMAPA_C33_C34 0x329c 1158 #define regDWB_GAMUT_REMAPA_C33_C34_BASE_IDX 2 1159 #define regDWB_GAMUT_REMAPB_C11_C12 0x329d 1160 #define regDWB_GAMUT_REMAPB_C11_C12_BASE_IDX 2 1161 #define regDWB_GAMUT_REMAPB_C13_C14 0x329e 1162 #define regDWB_GAMUT_REMAPB_C13_C14_BASE_IDX 2 1163 #define regDWB_GAMUT_REMAPB_C21_C22 0x329f 1164 #define regDWB_GAMUT_REMAPB_C21_C22_BASE_IDX 2 1165 #define regDWB_GAMUT_REMAPB_C23_C24 0x32a0 1166 #define regDWB_GAMUT_REMAPB_C23_C24_BASE_IDX 2 1167 #define regDWB_GAMUT_REMAPB_C31_C32 0x32a1 1168 #define regDWB_GAMUT_REMAPB_C31_C32_BASE_IDX 2 1169 #define regDWB_GAMUT_REMAPB_C33_C34 0x32a2 1170 #define regDWB_GAMUT_REMAPB_C33_C34_BASE_IDX 2 1171 #define regDWB_OGAM_CONTROL 0x32a3 1172 #define regDWB_OGAM_CONTROL_BASE_IDX 2 1173 #define regDWB_OGAM_LUT_INDEX 0x32a4 1174 #define regDWB_OGAM_LUT_INDEX_BASE_IDX 2 1175 #define regDWB_OGAM_LUT_DATA 0x32a5 1176 #define regDWB_OGAM_LUT_DATA_BASE_IDX 2 1177 #define regDWB_OGAM_LUT_CONTROL 0x32a6 1178 #define regDWB_OGAM_LUT_CONTROL_BASE_IDX 2 1179 #define regDWB_OGAM_RAMA_START_CNTL_B 0x32a7 1180 #define regDWB_OGAM_RAMA_START_CNTL_B_BASE_IDX 2 1181 #define regDWB_OGAM_RAMA_START_CNTL_G 0x32a8 1182 #define regDWB_OGAM_RAMA_START_CNTL_G_BASE_IDX 2 1183 #define regDWB_OGAM_RAMA_START_CNTL_R 0x32a9 1184 #define regDWB_OGAM_RAMA_START_CNTL_R_BASE_IDX 2 1185 #define regDWB_OGAM_RAMA_START_BASE_CNTL_B 0x32aa 1186 #define regDWB_OGAM_RAMA_START_BASE_CNTL_B_BASE_IDX 2 1187 #define regDWB_OGAM_RAMA_START_SLOPE_CNTL_B 0x32ab 1188 #define regDWB_OGAM_RAMA_START_SLOPE_CNTL_B_BASE_IDX 2 1189 #define regDWB_OGAM_RAMA_START_BASE_CNTL_G 0x32ac 1190 #define regDWB_OGAM_RAMA_START_BASE_CNTL_G_BASE_IDX 2 1191 #define regDWB_OGAM_RAMA_START_SLOPE_CNTL_G 0x32ad 1192 #define regDWB_OGAM_RAMA_START_SLOPE_CNTL_G_BASE_IDX 2 1193 #define regDWB_OGAM_RAMA_START_BASE_CNTL_R 0x32ae 1194 #define regDWB_OGAM_RAMA_START_BASE_CNTL_R_BASE_IDX 2 1195 #define regDWB_OGAM_RAMA_START_SLOPE_CNTL_R 0x32af 1196 #define regDWB_OGAM_RAMA_START_SLOPE_CNTL_R_BASE_IDX 2 1197 #define regDWB_OGAM_RAMA_END_CNTL1_B 0x32b0 1198 #define regDWB_OGAM_RAMA_END_CNTL1_B_BASE_IDX 2 1199 #define regDWB_OGAM_RAMA_END_CNTL2_B 0x32b1 1200 #define regDWB_OGAM_RAMA_END_CNTL2_B_BASE_IDX 2 1201 #define regDWB_OGAM_RAMA_END_CNTL1_G 0x32b2 1202 #define regDWB_OGAM_RAMA_END_CNTL1_G_BASE_IDX 2 1203 #define regDWB_OGAM_RAMA_END_CNTL2_G 0x32b3 1204 #define regDWB_OGAM_RAMA_END_CNTL2_G_BASE_IDX 2 1205 #define regDWB_OGAM_RAMA_END_CNTL1_R 0x32b4 1206 #define regDWB_OGAM_RAMA_END_CNTL1_R_BASE_IDX 2 1207 #define regDWB_OGAM_RAMA_END_CNTL2_R 0x32b5 1208 #define regDWB_OGAM_RAMA_END_CNTL2_R_BASE_IDX 2 1209 #define regDWB_OGAM_RAMA_OFFSET_B 0x32b6 1210 #define regDWB_OGAM_RAMA_OFFSET_B_BASE_IDX 2 1211 #define regDWB_OGAM_RAMA_OFFSET_G 0x32b7 1212 #define regDWB_OGAM_RAMA_OFFSET_G_BASE_IDX 2 1213 #define regDWB_OGAM_RAMA_OFFSET_R 0x32b8 1214 #define regDWB_OGAM_RAMA_OFFSET_R_BASE_IDX 2 1215 #define regDWB_OGAM_RAMA_REGION_0_1 0x32b9 1216 #define regDWB_OGAM_RAMA_REGION_0_1_BASE_IDX 2 1217 #define regDWB_OGAM_RAMA_REGION_2_3 0x32ba 1218 #define regDWB_OGAM_RAMA_REGION_2_3_BASE_IDX 2 1219 #define regDWB_OGAM_RAMA_REGION_4_5 0x32bb 1220 #define regDWB_OGAM_RAMA_REGION_4_5_BASE_IDX 2 1221 #define regDWB_OGAM_RAMA_REGION_6_7 0x32bc 1222 #define regDWB_OGAM_RAMA_REGION_6_7_BASE_IDX 2 1223 #define regDWB_OGAM_RAMA_REGION_8_9 0x32bd 1224 #define regDWB_OGAM_RAMA_REGION_8_9_BASE_IDX 2 1225 #define regDWB_OGAM_RAMA_REGION_10_11 0x32be 1226 #define regDWB_OGAM_RAMA_REGION_10_11_BASE_IDX 2 1227 #define regDWB_OGAM_RAMA_REGION_12_13 0x32bf 1228 #define regDWB_OGAM_RAMA_REGION_12_13_BASE_IDX 2 1229 #define regDWB_OGAM_RAMA_REGION_14_15 0x32c0 1230 #define regDWB_OGAM_RAMA_REGION_14_15_BASE_IDX 2 1231 #define regDWB_OGAM_RAMA_REGION_16_17 0x32c1 1232 #define regDWB_OGAM_RAMA_REGION_16_17_BASE_IDX 2 1233 #define regDWB_OGAM_RAMA_REGION_18_19 0x32c2 1234 #define regDWB_OGAM_RAMA_REGION_18_19_BASE_IDX 2 1235 #define regDWB_OGAM_RAMA_REGION_20_21 0x32c3 1236 #define regDWB_OGAM_RAMA_REGION_20_21_BASE_IDX 2 1237 #define regDWB_OGAM_RAMA_REGION_22_23 0x32c4 1238 #define regDWB_OGAM_RAMA_REGION_22_23_BASE_IDX 2 1239 #define regDWB_OGAM_RAMA_REGION_24_25 0x32c5 1240 #define regDWB_OGAM_RAMA_REGION_24_25_BASE_IDX 2 1241 #define regDWB_OGAM_RAMA_REGION_26_27 0x32c6 1242 #define regDWB_OGAM_RAMA_REGION_26_27_BASE_IDX 2 1243 #define regDWB_OGAM_RAMA_REGION_28_29 0x32c7 1244 #define regDWB_OGAM_RAMA_REGION_28_29_BASE_IDX 2 1245 #define regDWB_OGAM_RAMA_REGION_30_31 0x32c8 1246 #define regDWB_OGAM_RAMA_REGION_30_31_BASE_IDX 2 1247 #define regDWB_OGAM_RAMA_REGION_32_33 0x32c9 1248 #define regDWB_OGAM_RAMA_REGION_32_33_BASE_IDX 2 1249 #define regDWB_OGAM_RAMB_START_CNTL_B 0x32ca 1250 #define regDWB_OGAM_RAMB_START_CNTL_B_BASE_IDX 2 1251 #define regDWB_OGAM_RAMB_START_CNTL_G 0x32cb 1252 #define regDWB_OGAM_RAMB_START_CNTL_G_BASE_IDX 2 1253 #define regDWB_OGAM_RAMB_START_CNTL_R 0x32cc 1254 #define regDWB_OGAM_RAMB_START_CNTL_R_BASE_IDX 2 1255 #define regDWB_OGAM_RAMB_START_BASE_CNTL_B 0x32cd 1256 #define regDWB_OGAM_RAMB_START_BASE_CNTL_B_BASE_IDX 2 1257 #define regDWB_OGAM_RAMB_START_SLOPE_CNTL_B 0x32ce 1258 #define regDWB_OGAM_RAMB_START_SLOPE_CNTL_B_BASE_IDX 2 1259 #define regDWB_OGAM_RAMB_START_BASE_CNTL_G 0x32cf 1260 #define regDWB_OGAM_RAMB_START_BASE_CNTL_G_BASE_IDX 2 1261 #define regDWB_OGAM_RAMB_START_SLOPE_CNTL_G 0x32d0 1262 #define regDWB_OGAM_RAMB_START_SLOPE_CNTL_G_BASE_IDX 2 1263 #define regDWB_OGAM_RAMB_START_BASE_CNTL_R 0x32d1 1264 #define regDWB_OGAM_RAMB_START_BASE_CNTL_R_BASE_IDX 2 1265 #define regDWB_OGAM_RAMB_START_SLOPE_CNTL_R 0x32d2 1266 #define regDWB_OGAM_RAMB_START_SLOPE_CNTL_R_BASE_IDX 2 1267 #define regDWB_OGAM_RAMB_END_CNTL1_B 0x32d3 1268 #define regDWB_OGAM_RAMB_END_CNTL1_B_BASE_IDX 2 1269 #define regDWB_OGAM_RAMB_END_CNTL2_B 0x32d4 1270 #define regDWB_OGAM_RAMB_END_CNTL2_B_BASE_IDX 2 1271 #define regDWB_OGAM_RAMB_END_CNTL1_G 0x32d5 1272 #define regDWB_OGAM_RAMB_END_CNTL1_G_BASE_IDX 2 1273 #define regDWB_OGAM_RAMB_END_CNTL2_G 0x32d6 1274 #define regDWB_OGAM_RAMB_END_CNTL2_G_BASE_IDX 2 1275 #define regDWB_OGAM_RAMB_END_CNTL1_R 0x32d7 1276 #define regDWB_OGAM_RAMB_END_CNTL1_R_BASE_IDX 2 1277 #define regDWB_OGAM_RAMB_END_CNTL2_R 0x32d8 1278 #define regDWB_OGAM_RAMB_END_CNTL2_R_BASE_IDX 2 1279 #define regDWB_OGAM_RAMB_OFFSET_B 0x32d9 1280 #define regDWB_OGAM_RAMB_OFFSET_B_BASE_IDX 2 1281 #define regDWB_OGAM_RAMB_OFFSET_G 0x32da 1282 #define regDWB_OGAM_RAMB_OFFSET_G_BASE_IDX 2 1283 #define regDWB_OGAM_RAMB_OFFSET_R 0x32db 1284 #define regDWB_OGAM_RAMB_OFFSET_R_BASE_IDX 2 1285 #define regDWB_OGAM_RAMB_REGION_0_1 0x32dc 1286 #define regDWB_OGAM_RAMB_REGION_0_1_BASE_IDX 2 1287 #define regDWB_OGAM_RAMB_REGION_2_3 0x32dd 1288 #define regDWB_OGAM_RAMB_REGION_2_3_BASE_IDX 2 1289 #define regDWB_OGAM_RAMB_REGION_4_5 0x32de 1290 #define regDWB_OGAM_RAMB_REGION_4_5_BASE_IDX 2 1291 #define regDWB_OGAM_RAMB_REGION_6_7 0x32df 1292 #define regDWB_OGAM_RAMB_REGION_6_7_BASE_IDX 2 1293 #define regDWB_OGAM_RAMB_REGION_8_9 0x32e0 1294 #define regDWB_OGAM_RAMB_REGION_8_9_BASE_IDX 2 1295 #define regDWB_OGAM_RAMB_REGION_10_11 0x32e1 1296 #define regDWB_OGAM_RAMB_REGION_10_11_BASE_IDX 2 1297 #define regDWB_OGAM_RAMB_REGION_12_13 0x32e2 1298 #define regDWB_OGAM_RAMB_REGION_12_13_BASE_IDX 2 1299 #define regDWB_OGAM_RAMB_REGION_14_15 0x32e3 1300 #define regDWB_OGAM_RAMB_REGION_14_15_BASE_IDX 2 1301 #define regDWB_OGAM_RAMB_REGION_16_17 0x32e4 1302 #define regDWB_OGAM_RAMB_REGION_16_17_BASE_IDX 2 1303 #define regDWB_OGAM_RAMB_REGION_18_19 0x32e5 1304 #define regDWB_OGAM_RAMB_REGION_18_19_BASE_IDX 2 1305 #define regDWB_OGAM_RAMB_REGION_20_21 0x32e6 1306 #define regDWB_OGAM_RAMB_REGION_20_21_BASE_IDX 2 1307 #define regDWB_OGAM_RAMB_REGION_22_23 0x32e7 1308 #define regDWB_OGAM_RAMB_REGION_22_23_BASE_IDX 2 1309 #define regDWB_OGAM_RAMB_REGION_24_25 0x32e8 1310 #define regDWB_OGAM_RAMB_REGION_24_25_BASE_IDX 2 1311 #define regDWB_OGAM_RAMB_REGION_26_27 0x32e9 1312 #define regDWB_OGAM_RAMB_REGION_26_27_BASE_IDX 2 1313 #define regDWB_OGAM_RAMB_REGION_28_29 0x32ea 1314 #define regDWB_OGAM_RAMB_REGION_28_29_BASE_IDX 2 1315 #define regDWB_OGAM_RAMB_REGION_30_31 0x32eb 1316 #define regDWB_OGAM_RAMB_REGION_30_31_BASE_IDX 2 1317 #define regDWB_OGAM_RAMB_REGION_32_33 0x32ec 1318 #define regDWB_OGAM_RAMB_REGION_32_33_BASE_IDX 2 1319 1320 1321 // addressBlock: dce_dc_wb0_dispdec_wb_dcperfmon_dc_perfmon_dispdec 1322 // base address: 0xca20 1323 #define regDC_PERFMON3_PERFCOUNTER_CNTL 0x3288 1324 #define regDC_PERFMON3_PERFCOUNTER_CNTL_BASE_IDX 2 1325 #define regDC_PERFMON3_PERFCOUNTER_CNTL2 0x3289 1326 #define regDC_PERFMON3_PERFCOUNTER_CNTL2_BASE_IDX 2 1327 #define regDC_PERFMON3_PERFCOUNTER_STATE 0x328a 1328 #define regDC_PERFMON3_PERFCOUNTER_STATE_BASE_IDX 2 1329 #define regDC_PERFMON3_PERFMON_CNTL 0x328b 1330 #define regDC_PERFMON3_PERFMON_CNTL_BASE_IDX 2 1331 #define regDC_PERFMON3_PERFMON_CNTL2 0x328c 1332 #define regDC_PERFMON3_PERFMON_CNTL2_BASE_IDX 2 1333 #define regDC_PERFMON3_PERFMON_CVALUE_INT_MISC 0x328d 1334 #define regDC_PERFMON3_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 1335 #define regDC_PERFMON3_PERFMON_CVALUE_LOW 0x328e 1336 #define regDC_PERFMON3_PERFMON_CVALUE_LOW_BASE_IDX 2 1337 #define regDC_PERFMON3_PERFMON_HI 0x328f 1338 #define regDC_PERFMON3_PERFMON_HI_BASE_IDX 2 1339 #define regDC_PERFMON3_PERFMON_LOW 0x3290 1340 #define regDC_PERFMON3_PERFMON_LOW_BASE_IDX 2 1341 1342 1343 // addressBlock: dce_dc_mmhubbub_vga_dispdec 1344 // base address: 0x0 1345 #define regVGA_RENDER_CONTROL 0x0000 1346 #define regVGA_RENDER_CONTROL_BASE_IDX 1 1347 #define regVGA_SEQUENCER_RESET_CONTROL 0x0001 1348 #define regVGA_SEQUENCER_RESET_CONTROL_BASE_IDX 1 1349 #define regVGA_MODE_CONTROL 0x0002 1350 #define regVGA_MODE_CONTROL_BASE_IDX 1 1351 #define regVGA_SURFACE_PITCH_SELECT 0x0003 1352 #define regVGA_SURFACE_PITCH_SELECT_BASE_IDX 1 1353 #define regVGA_MEMORY_BASE_ADDRESS 0x0004 1354 #define regVGA_MEMORY_BASE_ADDRESS_BASE_IDX 1 1355 #define regVGA_DISPBUF1_SURFACE_ADDR 0x0006 1356 #define regVGA_DISPBUF1_SURFACE_ADDR_BASE_IDX 1 1357 #define regVGA_DISPBUF2_SURFACE_ADDR 0x0008 1358 #define regVGA_DISPBUF2_SURFACE_ADDR_BASE_IDX 1 1359 #define regVGA_MEMORY_BASE_ADDRESS_HIGH 0x0009 1360 #define regVGA_MEMORY_BASE_ADDRESS_HIGH_BASE_IDX 1 1361 #define regVGA_HDP_CONTROL 0x000a 1362 #define regVGA_HDP_CONTROL_BASE_IDX 1 1363 #define regVGA_CACHE_CONTROL 0x000b 1364 #define regVGA_CACHE_CONTROL_BASE_IDX 1 1365 #define regD1VGA_CONTROL 0x000c 1366 #define regD1VGA_CONTROL_BASE_IDX 1 1367 #define regD2VGA_CONTROL 0x000e 1368 #define regD2VGA_CONTROL_BASE_IDX 1 1369 #define regVGA_STATUS 0x0010 1370 #define regVGA_STATUS_BASE_IDX 1 1371 #define regVGA_INTERRUPT_CONTROL 0x0011 1372 #define regVGA_INTERRUPT_CONTROL_BASE_IDX 1 1373 #define regVGA_STATUS_CLEAR 0x0012 1374 #define regVGA_STATUS_CLEAR_BASE_IDX 1 1375 #define regVGA_INTERRUPT_STATUS 0x0013 1376 #define regVGA_INTERRUPT_STATUS_BASE_IDX 1 1377 #define regVGA_MAIN_CONTROL 0x0014 1378 #define regVGA_MAIN_CONTROL_BASE_IDX 1 1379 #define regVGA_TEST_CONTROL 0x0015 1380 #define regVGA_TEST_CONTROL_BASE_IDX 1 1381 #define regVGA_QOS_CTRL 0x0018 1382 #define regVGA_QOS_CTRL_BASE_IDX 1 1383 #define regD3VGA_CONTROL 0x0038 1384 #define regD3VGA_CONTROL_BASE_IDX 1 1385 #define regD4VGA_CONTROL 0x0039 1386 #define regD4VGA_CONTROL_BASE_IDX 1 1387 #define regD5VGA_CONTROL 0x003a 1388 #define regD5VGA_CONTROL_BASE_IDX 1 1389 #define regD6VGA_CONTROL 0x003b 1390 #define regD6VGA_CONTROL_BASE_IDX 1 1391 #define regVGA_SOURCE_SELECT 0x003c 1392 #define regVGA_SOURCE_SELECT_BASE_IDX 1 1393 1394 1395 // addressBlock: dce_dc_mmhubbub_vgaif_dispdec 1396 // base address: 0x0 1397 #define regMCIF_CONTROL 0x034a 1398 #define regMCIF_CONTROL_BASE_IDX 2 1399 #define regMCIF_WRITE_COMBINE_CONTROL 0x034b 1400 #define regMCIF_WRITE_COMBINE_CONTROL_BASE_IDX 2 1401 #define regMCIF_PHASE0_OUTSTANDING_COUNTER 0x034e 1402 #define regMCIF_PHASE0_OUTSTANDING_COUNTER_BASE_IDX 2 1403 #define regMCIF_PHASE1_OUTSTANDING_COUNTER 0x034f 1404 #define regMCIF_PHASE1_OUTSTANDING_COUNTER_BASE_IDX 2 1405 #define regMCIF_PHASE2_OUTSTANDING_COUNTER 0x0350 1406 #define regMCIF_PHASE2_OUTSTANDING_COUNTER_BASE_IDX 2 1407 1408 1409 // addressBlock: dce_dc_mmhubbub_mcif_wb0_dispdec 1410 // base address: 0x0 1411 #define regMCIF_WB_BUFMGR_SW_CONTROL 0x0272 1412 #define regMCIF_WB_BUFMGR_SW_CONTROL_BASE_IDX 2 1413 #define regMCIF_WB_BUFMGR_STATUS 0x0274 1414 #define regMCIF_WB_BUFMGR_STATUS_BASE_IDX 2 1415 #define regMCIF_WB_BUF_PITCH 0x0275 1416 #define regMCIF_WB_BUF_PITCH_BASE_IDX 2 1417 #define regMCIF_WB_BUF_1_STATUS 0x0276 1418 #define regMCIF_WB_BUF_1_STATUS_BASE_IDX 2 1419 #define regMCIF_WB_BUF_1_STATUS2 0x0277 1420 #define regMCIF_WB_BUF_1_STATUS2_BASE_IDX 2 1421 #define regMCIF_WB_BUF_2_STATUS 0x0278 1422 #define regMCIF_WB_BUF_2_STATUS_BASE_IDX 2 1423 #define regMCIF_WB_BUF_2_STATUS2 0x0279 1424 #define regMCIF_WB_BUF_2_STATUS2_BASE_IDX 2 1425 #define regMCIF_WB_BUF_3_STATUS 0x027a 1426 #define regMCIF_WB_BUF_3_STATUS_BASE_IDX 2 1427 #define regMCIF_WB_BUF_3_STATUS2 0x027b 1428 #define regMCIF_WB_BUF_3_STATUS2_BASE_IDX 2 1429 #define regMCIF_WB_BUF_4_STATUS 0x027c 1430 #define regMCIF_WB_BUF_4_STATUS_BASE_IDX 2 1431 #define regMCIF_WB_BUF_4_STATUS2 0x027d 1432 #define regMCIF_WB_BUF_4_STATUS2_BASE_IDX 2 1433 #define regMCIF_WB_ARBITRATION_CONTROL 0x027e 1434 #define regMCIF_WB_ARBITRATION_CONTROL_BASE_IDX 2 1435 #define regMCIF_WB_SCLK_CHANGE 0x027f 1436 #define regMCIF_WB_SCLK_CHANGE_BASE_IDX 2 1437 #define regMCIF_WB_TEST_DEBUG_INDEX 0x0280 1438 #define regMCIF_WB_TEST_DEBUG_INDEX_BASE_IDX 2 1439 #define regMCIF_WB_TEST_DEBUG_DATA 0x0281 1440 #define regMCIF_WB_TEST_DEBUG_DATA_BASE_IDX 2 1441 #define regMCIF_WB_BUF_1_ADDR_Y 0x0282 1442 #define regMCIF_WB_BUF_1_ADDR_Y_BASE_IDX 2 1443 #define regMCIF_WB_BUF_1_ADDR_C 0x0284 1444 #define regMCIF_WB_BUF_1_ADDR_C_BASE_IDX 2 1445 #define regMCIF_WB_BUF_2_ADDR_Y 0x0286 1446 #define regMCIF_WB_BUF_2_ADDR_Y_BASE_IDX 2 1447 #define regMCIF_WB_BUF_2_ADDR_C 0x0288 1448 #define regMCIF_WB_BUF_2_ADDR_C_BASE_IDX 2 1449 #define regMCIF_WB_BUF_3_ADDR_Y 0x028a 1450 #define regMCIF_WB_BUF_3_ADDR_Y_BASE_IDX 2 1451 #define regMCIF_WB_BUF_3_ADDR_C 0x028c 1452 #define regMCIF_WB_BUF_3_ADDR_C_BASE_IDX 2 1453 #define regMCIF_WB_BUF_4_ADDR_Y 0x028e 1454 #define regMCIF_WB_BUF_4_ADDR_Y_BASE_IDX 2 1455 #define regMCIF_WB_BUF_4_ADDR_C 0x0290 1456 #define regMCIF_WB_BUF_4_ADDR_C_BASE_IDX 2 1457 #define regMCIF_WB_BUFMGR_VCE_CONTROL 0x0292 1458 #define regMCIF_WB_BUFMGR_VCE_CONTROL_BASE_IDX 2 1459 #define regMCIF_WB_NB_PSTATE_CONTROL 0x0293 1460 #define regMCIF_WB_NB_PSTATE_CONTROL_BASE_IDX 2 1461 #define regMCIF_WB_CLOCK_GATER_CONTROL 0x0294 1462 #define regMCIF_WB_CLOCK_GATER_CONTROL_BASE_IDX 2 1463 #define regMCIF_WB_SELF_REFRESH_CONTROL 0x0296 1464 #define regMCIF_WB_SELF_REFRESH_CONTROL_BASE_IDX 2 1465 #define regMULTI_LEVEL_QOS_CTRL 0x0297 1466 #define regMULTI_LEVEL_QOS_CTRL_BASE_IDX 2 1467 #define regMCIF_WB_BUF_LUMA_SIZE 0x0299 1468 #define regMCIF_WB_BUF_LUMA_SIZE_BASE_IDX 2 1469 #define regMCIF_WB_BUF_CHROMA_SIZE 0x029a 1470 #define regMCIF_WB_BUF_CHROMA_SIZE_BASE_IDX 2 1471 #define regMCIF_WB_BUF_1_ADDR_Y_HIGH 0x029b 1472 #define regMCIF_WB_BUF_1_ADDR_Y_HIGH_BASE_IDX 2 1473 #define regMCIF_WB_BUF_1_ADDR_C_HIGH 0x029c 1474 #define regMCIF_WB_BUF_1_ADDR_C_HIGH_BASE_IDX 2 1475 #define regMCIF_WB_BUF_2_ADDR_Y_HIGH 0x029d 1476 #define regMCIF_WB_BUF_2_ADDR_Y_HIGH_BASE_IDX 2 1477 #define regMCIF_WB_BUF_2_ADDR_C_HIGH 0x029e 1478 #define regMCIF_WB_BUF_2_ADDR_C_HIGH_BASE_IDX 2 1479 #define regMCIF_WB_BUF_3_ADDR_Y_HIGH 0x029f 1480 #define regMCIF_WB_BUF_3_ADDR_Y_HIGH_BASE_IDX 2 1481 #define regMCIF_WB_BUF_3_ADDR_C_HIGH 0x02a0 1482 #define regMCIF_WB_BUF_3_ADDR_C_HIGH_BASE_IDX 2 1483 #define regMCIF_WB_BUF_4_ADDR_Y_HIGH 0x02a1 1484 #define regMCIF_WB_BUF_4_ADDR_Y_HIGH_BASE_IDX 2 1485 #define regMCIF_WB_BUF_4_ADDR_C_HIGH 0x02a2 1486 #define regMCIF_WB_BUF_4_ADDR_C_HIGH_BASE_IDX 2 1487 #define regMCIF_WB_BUF_1_RESOLUTION 0x02a3 1488 #define regMCIF_WB_BUF_1_RESOLUTION_BASE_IDX 2 1489 #define regMCIF_WB_BUF_2_RESOLUTION 0x02a4 1490 #define regMCIF_WB_BUF_2_RESOLUTION_BASE_IDX 2 1491 #define regMCIF_WB_BUF_3_RESOLUTION 0x02a5 1492 #define regMCIF_WB_BUF_3_RESOLUTION_BASE_IDX 2 1493 #define regMCIF_WB_BUF_4_RESOLUTION 0x02a6 1494 #define regMCIF_WB_BUF_4_RESOLUTION_BASE_IDX 2 1495 #define regMCIF_WB_DRAM_SPEED_CHANGE_DURATION_VBI 0x02a7 1496 #define regMCIF_WB_DRAM_SPEED_CHANGE_DURATION_VBI_BASE_IDX 2 1497 #define regMCIF_WB_VMID_CONTROL 0x02a8 1498 #define regMCIF_WB_VMID_CONTROL_BASE_IDX 2 1499 #define regMCIF_WB_MIN_TTO 0x02a9 1500 #define regMCIF_WB_MIN_TTO_BASE_IDX 2 1501 1502 1503 // addressBlock: dce_dc_mmhubbub_mmhubbub_dcperfmon_dc_perfmon_dispdec 1504 // base address: 0xd48 1505 #define regDC_PERFMON4_PERFCOUNTER_CNTL 0x0352 1506 #define regDC_PERFMON4_PERFCOUNTER_CNTL_BASE_IDX 2 1507 #define regDC_PERFMON4_PERFCOUNTER_CNTL2 0x0353 1508 #define regDC_PERFMON4_PERFCOUNTER_CNTL2_BASE_IDX 2 1509 #define regDC_PERFMON4_PERFCOUNTER_STATE 0x0354 1510 #define regDC_PERFMON4_PERFCOUNTER_STATE_BASE_IDX 2 1511 #define regDC_PERFMON4_PERFMON_CNTL 0x0355 1512 #define regDC_PERFMON4_PERFMON_CNTL_BASE_IDX 2 1513 #define regDC_PERFMON4_PERFMON_CNTL2 0x0356 1514 #define regDC_PERFMON4_PERFMON_CNTL2_BASE_IDX 2 1515 #define regDC_PERFMON4_PERFMON_CVALUE_INT_MISC 0x0357 1516 #define regDC_PERFMON4_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 1517 #define regDC_PERFMON4_PERFMON_CVALUE_LOW 0x0358 1518 #define regDC_PERFMON4_PERFMON_CVALUE_LOW_BASE_IDX 2 1519 #define regDC_PERFMON4_PERFMON_HI 0x0359 1520 #define regDC_PERFMON4_PERFMON_HI_BASE_IDX 2 1521 #define regDC_PERFMON4_PERFMON_LOW 0x035a 1522 #define regDC_PERFMON4_PERFMON_LOW_BASE_IDX 2 1523 1524 1525 // addressBlock: dce_dc_mmhubbub_mmhubbub_dispdec 1526 // base address: 0x0 1527 #define regMCIF_WB_NB_PSTATE_LATENCY_WATERMARK 0x02aa 1528 #define regMCIF_WB_NB_PSTATE_LATENCY_WATERMARK_BASE_IDX 2 1529 #define regMCIF_WB_WATERMARK 0x02ab 1530 #define regMCIF_WB_WATERMARK_BASE_IDX 2 1531 #define regMMHUBBUB_WARMUP_CONFIG 0x02ac 1532 #define regMMHUBBUB_WARMUP_CONFIG_BASE_IDX 2 1533 #define regMMHUBBUB_WARMUP_CONTROL_STATUS 0x02ad 1534 #define regMMHUBBUB_WARMUP_CONTROL_STATUS_BASE_IDX 2 1535 #define regMMHUBBUB_WARMUP_BASE_ADDR_LOW 0x02ae 1536 #define regMMHUBBUB_WARMUP_BASE_ADDR_LOW_BASE_IDX 2 1537 #define regMMHUBBUB_WARMUP_BASE_ADDR_HIGH 0x02af 1538 #define regMMHUBBUB_WARMUP_BASE_ADDR_HIGH_BASE_IDX 2 1539 #define regMMHUBBUB_WARMUP_ADDR_REGION 0x02b0 1540 #define regMMHUBBUB_WARMUP_ADDR_REGION_BASE_IDX 2 1541 #define regMMHUBBUB_MIN_TTO 0x02b1 1542 #define regMMHUBBUB_MIN_TTO_BASE_IDX 2 1543 #define regMMHUBBUB_CTRL 0x0333 1544 #define regMMHUBBUB_CTRL_BASE_IDX 2 1545 #define regWBIF_SMU_WM_CONTROL 0x0334 1546 #define regWBIF_SMU_WM_CONTROL_BASE_IDX 2 1547 #define regWBIF0_MISC_CTRL 0x0335 1548 #define regWBIF0_MISC_CTRL_BASE_IDX 2 1549 #define regWBIF0_PHASE0_OUTSTANDING_COUNTER 0x0336 1550 #define regWBIF0_PHASE0_OUTSTANDING_COUNTER_BASE_IDX 2 1551 #define regWBIF0_PHASE1_OUTSTANDING_COUNTER 0x0337 1552 #define regWBIF0_PHASE1_OUTSTANDING_COUNTER_BASE_IDX 2 1553 #define regVGA_SRC_SPLIT_CNTL 0x033e 1554 #define regVGA_SRC_SPLIT_CNTL_BASE_IDX 2 1555 #define regMMHUBBUB_MEM_PWR_STATUS 0x033f 1556 #define regMMHUBBUB_MEM_PWR_STATUS_BASE_IDX 2 1557 #define regMMHUBBUB_MEM_PWR_CNTL 0x0340 1558 #define regMMHUBBUB_MEM_PWR_CNTL_BASE_IDX 2 1559 #define regMMHUBBUB_CLOCK_CNTL 0x0341 1560 #define regMMHUBBUB_CLOCK_CNTL_BASE_IDX 2 1561 #define regMMHUBBUB_SOFT_RESET 0x0342 1562 #define regMMHUBBUB_SOFT_RESET_BASE_IDX 2 1563 #define regDMU_IF_ERR_STATUS 0x0346 1564 #define regDMU_IF_ERR_STATUS_BASE_IDX 2 1565 #define regMMHUBBUB_CLIENT_UNIT_ID 0x0347 1566 #define regMMHUBBUB_CLIENT_UNIT_ID_BASE_IDX 2 1567 #define regMMHUBBUB_WARMUP_VMID_CONTROL 0x0349 1568 #define regMMHUBBUB_WARMUP_VMID_CONTROL_BASE_IDX 2 1569 1570 1571 // addressBlock: dce_dc_hda_azf0controller_dispdec 1572 // base address: 0x0 1573 #define regAZALIA_CONTROLLER_CLOCK_GATING 0x03c2 1574 #define regAZALIA_CONTROLLER_CLOCK_GATING_BASE_IDX 2 1575 #define regAZALIA_AUDIO_DTO 0x03c3 1576 #define regAZALIA_AUDIO_DTO_BASE_IDX 2 1577 #define regAZALIA_AUDIO_DTO_CONTROL 0x03c4 1578 #define regAZALIA_AUDIO_DTO_CONTROL_BASE_IDX 2 1579 #define regAZALIA_SOCCLK_CONTROL 0x03c5 1580 #define regAZALIA_SOCCLK_CONTROL_BASE_IDX 2 1581 #define regAZALIA_UNDERFLOW_FILLER_SAMPLE 0x03c6 1582 #define regAZALIA_UNDERFLOW_FILLER_SAMPLE_BASE_IDX 2 1583 #define regAZALIA_DATA_DMA_CONTROL 0x03c7 1584 #define regAZALIA_DATA_DMA_CONTROL_BASE_IDX 2 1585 #define regAZALIA_BDL_DMA_CONTROL 0x03c8 1586 #define regAZALIA_BDL_DMA_CONTROL_BASE_IDX 2 1587 #define regAZALIA_RIRB_AND_DP_CONTROL 0x03c9 1588 #define regAZALIA_RIRB_AND_DP_CONTROL_BASE_IDX 2 1589 #define regAZALIA_CORB_DMA_CONTROL 0x03ca 1590 #define regAZALIA_CORB_DMA_CONTROL_BASE_IDX 2 1591 #define regAZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER 0x03d1 1592 #define regAZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER_BASE_IDX 2 1593 #define regAZALIA_CYCLIC_BUFFER_SYNC 0x03d2 1594 #define regAZALIA_CYCLIC_BUFFER_SYNC_BASE_IDX 2 1595 #define regAZALIA_GLOBAL_CAPABILITIES 0x03d3 1596 #define regAZALIA_GLOBAL_CAPABILITIES_BASE_IDX 2 1597 #define regAZALIA_OUTPUT_PAYLOAD_CAPABILITY 0x03d4 1598 #define regAZALIA_OUTPUT_PAYLOAD_CAPABILITY_BASE_IDX 2 1599 #define regAZALIA_OUTPUT_STREAM_ARBITER_CONTROL 0x03d5 1600 #define regAZALIA_OUTPUT_STREAM_ARBITER_CONTROL_BASE_IDX 2 1601 #define regAZALIA_INPUT_PAYLOAD_CAPABILITY 0x03d6 1602 #define regAZALIA_INPUT_PAYLOAD_CAPABILITY_BASE_IDX 2 1603 #define regAZALIA_INPUT_CRC0_CONTROL0 0x03d9 1604 #define regAZALIA_INPUT_CRC0_CONTROL0_BASE_IDX 2 1605 #define regAZALIA_INPUT_CRC0_CONTROL1 0x03da 1606 #define regAZALIA_INPUT_CRC0_CONTROL1_BASE_IDX 2 1607 #define regAZALIA_INPUT_CRC0_CONTROL2 0x03db 1608 #define regAZALIA_INPUT_CRC0_CONTROL2_BASE_IDX 2 1609 #define regAZALIA_INPUT_CRC0_CONTROL3 0x03dc 1610 #define regAZALIA_INPUT_CRC0_CONTROL3_BASE_IDX 2 1611 #define regAZALIA_INPUT_CRC0_RESULT 0x03dd 1612 #define regAZALIA_INPUT_CRC0_RESULT_BASE_IDX 2 1613 #define regAZALIA_INPUT_CRC1_CONTROL0 0x03de 1614 #define regAZALIA_INPUT_CRC1_CONTROL0_BASE_IDX 2 1615 #define regAZALIA_INPUT_CRC1_CONTROL1 0x03df 1616 #define regAZALIA_INPUT_CRC1_CONTROL1_BASE_IDX 2 1617 #define regAZALIA_INPUT_CRC1_CONTROL2 0x03e0 1618 #define regAZALIA_INPUT_CRC1_CONTROL2_BASE_IDX 2 1619 #define regAZALIA_INPUT_CRC1_CONTROL3 0x03e1 1620 #define regAZALIA_INPUT_CRC1_CONTROL3_BASE_IDX 2 1621 #define regAZALIA_INPUT_CRC1_RESULT 0x03e2 1622 #define regAZALIA_INPUT_CRC1_RESULT_BASE_IDX 2 1623 #define regAZALIA_CRC0_CONTROL0 0x03e3 1624 #define regAZALIA_CRC0_CONTROL0_BASE_IDX 2 1625 #define regAZALIA_CRC0_CONTROL1 0x03e4 1626 #define regAZALIA_CRC0_CONTROL1_BASE_IDX 2 1627 #define regAZALIA_CRC0_CONTROL2 0x03e5 1628 #define regAZALIA_CRC0_CONTROL2_BASE_IDX 2 1629 #define regAZALIA_CRC0_CONTROL3 0x03e6 1630 #define regAZALIA_CRC0_CONTROL3_BASE_IDX 2 1631 #define regAZALIA_CRC0_RESULT 0x03e7 1632 #define regAZALIA_CRC0_RESULT_BASE_IDX 2 1633 #define regAZALIA_CRC1_CONTROL0 0x03e8 1634 #define regAZALIA_CRC1_CONTROL0_BASE_IDX 2 1635 #define regAZALIA_CRC1_CONTROL1 0x03e9 1636 #define regAZALIA_CRC1_CONTROL1_BASE_IDX 2 1637 #define regAZALIA_CRC1_CONTROL2 0x03ea 1638 #define regAZALIA_CRC1_CONTROL2_BASE_IDX 2 1639 #define regAZALIA_CRC1_CONTROL3 0x03eb 1640 #define regAZALIA_CRC1_CONTROL3_BASE_IDX 2 1641 #define regAZALIA_CRC1_RESULT 0x03ec 1642 #define regAZALIA_CRC1_RESULT_BASE_IDX 2 1643 #define regAZALIA_MEM_PWR_CTRL 0x03ee 1644 #define regAZALIA_MEM_PWR_CTRL_BASE_IDX 2 1645 #define regAZALIA_MEM_PWR_STATUS 0x03ef 1646 #define regAZALIA_MEM_PWR_STATUS_BASE_IDX 2 1647 1648 1649 // addressBlock: dce_dc_hda_azf0root_dispdec 1650 // base address: 0x0 1651 #define regAZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID 0x0406 1652 #define regAZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID_BASE_IDX 2 1653 #define regAZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID 0x0407 1654 #define regAZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID_BASE_IDX 2 1655 #define regAZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL 0x0408 1656 #define regAZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL_BASE_IDX 2 1657 #define regAZALIA_F0_CODEC_RESYNC_FIFO_CONTROL 0x0409 1658 #define regAZALIA_F0_CODEC_RESYNC_FIFO_CONTROL_BASE_IDX 2 1659 #define regAZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE 0x040a 1660 #define regAZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE_BASE_IDX 2 1661 #define regAZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES 0x040b 1662 #define regAZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES_BASE_IDX 2 1663 #define regAZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS 0x040c 1664 #define regAZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS_BASE_IDX 2 1665 #define regAZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES 0x040d 1666 #define regAZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES_BASE_IDX 2 1667 #define regAZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE 0x040e 1668 #define regAZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE_BASE_IDX 2 1669 #define regAZALIA_F0_CODEC_FUNCTION_CONTROL_RESET 0x040f 1670 #define regAZALIA_F0_CODEC_FUNCTION_CONTROL_RESET_BASE_IDX 2 1671 #define regAZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID 0x0410 1672 #define regAZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_BASE_IDX 2 1673 #define regAZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION 0x0411 1674 #define regAZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION_BASE_IDX 2 1675 #define regCC_RCU_DC_AUDIO_PORT_CONNECTIVITY 0x0412 1676 #define regCC_RCU_DC_AUDIO_PORT_CONNECTIVITY_BASE_IDX 2 1677 #define regCC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY 0x0413 1678 #define regCC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_BASE_IDX 2 1679 #define regAZALIA_F0_GTC_GROUP_OFFSET0 0x0415 1680 #define regAZALIA_F0_GTC_GROUP_OFFSET0_BASE_IDX 2 1681 #define regAZALIA_F0_GTC_GROUP_OFFSET1 0x0416 1682 #define regAZALIA_F0_GTC_GROUP_OFFSET1_BASE_IDX 2 1683 #define regAZALIA_F0_GTC_GROUP_OFFSET2 0x0417 1684 #define regAZALIA_F0_GTC_GROUP_OFFSET2_BASE_IDX 2 1685 #define regAZALIA_F0_GTC_GROUP_OFFSET3 0x0418 1686 #define regAZALIA_F0_GTC_GROUP_OFFSET3_BASE_IDX 2 1687 #define regAZALIA_F0_GTC_GROUP_OFFSET4 0x0419 1688 #define regAZALIA_F0_GTC_GROUP_OFFSET4_BASE_IDX 2 1689 #define regAZALIA_F0_GTC_GROUP_OFFSET5 0x041a 1690 #define regAZALIA_F0_GTC_GROUP_OFFSET5_BASE_IDX 2 1691 #define regAZALIA_F0_GTC_GROUP_OFFSET6 0x041b 1692 #define regAZALIA_F0_GTC_GROUP_OFFSET6_BASE_IDX 2 1693 #define regREG_DC_AUDIO_PORT_CONNECTIVITY 0x041c 1694 #define regREG_DC_AUDIO_PORT_CONNECTIVITY_BASE_IDX 2 1695 #define regREG_DC_AUDIO_INPUT_PORT_CONNECTIVITY 0x041d 1696 #define regREG_DC_AUDIO_INPUT_PORT_CONNECTIVITY_BASE_IDX 2 1697 1698 1699 // addressBlock: dce_dc_hda_az_misc_dispdec 1700 // base address: 0x0 1701 #define regAZ_CLOCK_CNTL 0x0372 1702 #define regAZ_CLOCK_CNTL_BASE_IDX 2 1703 1704 1705 // addressBlock: dce_dc_hda_az_dcperfmon_dc_perfmon_dispdec 1706 // base address: 0xde8 1707 #define regDC_PERFMON5_PERFCOUNTER_CNTL 0x037a 1708 #define regDC_PERFMON5_PERFCOUNTER_CNTL_BASE_IDX 2 1709 #define regDC_PERFMON5_PERFCOUNTER_CNTL2 0x037b 1710 #define regDC_PERFMON5_PERFCOUNTER_CNTL2_BASE_IDX 2 1711 #define regDC_PERFMON5_PERFCOUNTER_STATE 0x037c 1712 #define regDC_PERFMON5_PERFCOUNTER_STATE_BASE_IDX 2 1713 #define regDC_PERFMON5_PERFMON_CNTL 0x037d 1714 #define regDC_PERFMON5_PERFMON_CNTL_BASE_IDX 2 1715 #define regDC_PERFMON5_PERFMON_CNTL2 0x037e 1716 #define regDC_PERFMON5_PERFMON_CNTL2_BASE_IDX 2 1717 #define regDC_PERFMON5_PERFMON_CVALUE_INT_MISC 0x037f 1718 #define regDC_PERFMON5_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 1719 #define regDC_PERFMON5_PERFMON_CVALUE_LOW 0x0380 1720 #define regDC_PERFMON5_PERFMON_CVALUE_LOW_BASE_IDX 2 1721 #define regDC_PERFMON5_PERFMON_HI 0x0381 1722 #define regDC_PERFMON5_PERFMON_HI_BASE_IDX 2 1723 #define regDC_PERFMON5_PERFMON_LOW 0x0382 1724 #define regDC_PERFMON5_PERFMON_LOW_BASE_IDX 2 1725 1726 1727 // addressBlock: dce_dc_hda_azf0stream0_dispdec 1728 // base address: 0x0 1729 #define regAZF0STREAM0_AZALIA_STREAM_INDEX 0x035e 1730 #define regAZF0STREAM0_AZALIA_STREAM_INDEX_BASE_IDX 2 1731 #define regAZF0STREAM0_AZALIA_STREAM_DATA 0x035f 1732 #define regAZF0STREAM0_AZALIA_STREAM_DATA_BASE_IDX 2 1733 1734 1735 // addressBlock: dce_dc_hda_azf0stream1_dispdec 1736 // base address: 0x8 1737 #define regAZF0STREAM1_AZALIA_STREAM_INDEX 0x0360 1738 #define regAZF0STREAM1_AZALIA_STREAM_INDEX_BASE_IDX 2 1739 #define regAZF0STREAM1_AZALIA_STREAM_DATA 0x0361 1740 #define regAZF0STREAM1_AZALIA_STREAM_DATA_BASE_IDX 2 1741 1742 1743 // addressBlock: dce_dc_hda_azf0stream2_dispdec 1744 // base address: 0x10 1745 #define regAZF0STREAM2_AZALIA_STREAM_INDEX 0x0362 1746 #define regAZF0STREAM2_AZALIA_STREAM_INDEX_BASE_IDX 2 1747 #define regAZF0STREAM2_AZALIA_STREAM_DATA 0x0363 1748 #define regAZF0STREAM2_AZALIA_STREAM_DATA_BASE_IDX 2 1749 1750 1751 // addressBlock: dce_dc_hda_azf0stream3_dispdec 1752 // base address: 0x18 1753 #define regAZF0STREAM3_AZALIA_STREAM_INDEX 0x0364 1754 #define regAZF0STREAM3_AZALIA_STREAM_INDEX_BASE_IDX 2 1755 #define regAZF0STREAM3_AZALIA_STREAM_DATA 0x0365 1756 #define regAZF0STREAM3_AZALIA_STREAM_DATA_BASE_IDX 2 1757 1758 1759 // addressBlock: dce_dc_hda_azf0stream4_dispdec 1760 // base address: 0x20 1761 #define regAZF0STREAM4_AZALIA_STREAM_INDEX 0x0366 1762 #define regAZF0STREAM4_AZALIA_STREAM_INDEX_BASE_IDX 2 1763 #define regAZF0STREAM4_AZALIA_STREAM_DATA 0x0367 1764 #define regAZF0STREAM4_AZALIA_STREAM_DATA_BASE_IDX 2 1765 1766 1767 // addressBlock: dce_dc_hda_azf0stream5_dispdec 1768 // base address: 0x28 1769 #define regAZF0STREAM5_AZALIA_STREAM_INDEX 0x0368 1770 #define regAZF0STREAM5_AZALIA_STREAM_INDEX_BASE_IDX 2 1771 #define regAZF0STREAM5_AZALIA_STREAM_DATA 0x0369 1772 #define regAZF0STREAM5_AZALIA_STREAM_DATA_BASE_IDX 2 1773 1774 1775 // addressBlock: dce_dc_hda_azf0stream6_dispdec 1776 // base address: 0x30 1777 #define regAZF0STREAM6_AZALIA_STREAM_INDEX 0x036a 1778 #define regAZF0STREAM6_AZALIA_STREAM_INDEX_BASE_IDX 2 1779 #define regAZF0STREAM6_AZALIA_STREAM_DATA 0x036b 1780 #define regAZF0STREAM6_AZALIA_STREAM_DATA_BASE_IDX 2 1781 1782 1783 // addressBlock: dce_dc_hda_azf0stream7_dispdec 1784 // base address: 0x38 1785 #define regAZF0STREAM7_AZALIA_STREAM_INDEX 0x036c 1786 #define regAZF0STREAM7_AZALIA_STREAM_INDEX_BASE_IDX 2 1787 #define regAZF0STREAM7_AZALIA_STREAM_DATA 0x036d 1788 #define regAZF0STREAM7_AZALIA_STREAM_DATA_BASE_IDX 2 1789 1790 1791 // addressBlock: dce_dc_hda_azf0stream8_dispdec 1792 // base address: 0x320 1793 #define regAZF0STREAM8_AZALIA_STREAM_INDEX 0x0426 1794 #define regAZF0STREAM8_AZALIA_STREAM_INDEX_BASE_IDX 2 1795 #define regAZF0STREAM8_AZALIA_STREAM_DATA 0x0427 1796 #define regAZF0STREAM8_AZALIA_STREAM_DATA_BASE_IDX 2 1797 1798 1799 // addressBlock: dce_dc_hda_azf0stream9_dispdec 1800 // base address: 0x328 1801 #define regAZF0STREAM9_AZALIA_STREAM_INDEX 0x0428 1802 #define regAZF0STREAM9_AZALIA_STREAM_INDEX_BASE_IDX 2 1803 #define regAZF0STREAM9_AZALIA_STREAM_DATA 0x0429 1804 #define regAZF0STREAM9_AZALIA_STREAM_DATA_BASE_IDX 2 1805 1806 1807 // addressBlock: dce_dc_hda_azf0stream10_dispdec 1808 // base address: 0x330 1809 #define regAZF0STREAM10_AZALIA_STREAM_INDEX 0x042a 1810 #define regAZF0STREAM10_AZALIA_STREAM_INDEX_BASE_IDX 2 1811 #define regAZF0STREAM10_AZALIA_STREAM_DATA 0x042b 1812 #define regAZF0STREAM10_AZALIA_STREAM_DATA_BASE_IDX 2 1813 1814 1815 // addressBlock: dce_dc_hda_azf0stream11_dispdec 1816 // base address: 0x338 1817 #define regAZF0STREAM11_AZALIA_STREAM_INDEX 0x042c 1818 #define regAZF0STREAM11_AZALIA_STREAM_INDEX_BASE_IDX 2 1819 #define regAZF0STREAM11_AZALIA_STREAM_DATA 0x042d 1820 #define regAZF0STREAM11_AZALIA_STREAM_DATA_BASE_IDX 2 1821 1822 1823 // addressBlock: dce_dc_hda_azf0stream12_dispdec 1824 // base address: 0x340 1825 #define regAZF0STREAM12_AZALIA_STREAM_INDEX 0x042e 1826 #define regAZF0STREAM12_AZALIA_STREAM_INDEX_BASE_IDX 2 1827 #define regAZF0STREAM12_AZALIA_STREAM_DATA 0x042f 1828 #define regAZF0STREAM12_AZALIA_STREAM_DATA_BASE_IDX 2 1829 1830 1831 // addressBlock: dce_dc_hda_azf0stream13_dispdec 1832 // base address: 0x348 1833 #define regAZF0STREAM13_AZALIA_STREAM_INDEX 0x0430 1834 #define regAZF0STREAM13_AZALIA_STREAM_INDEX_BASE_IDX 2 1835 #define regAZF0STREAM13_AZALIA_STREAM_DATA 0x0431 1836 #define regAZF0STREAM13_AZALIA_STREAM_DATA_BASE_IDX 2 1837 1838 1839 // addressBlock: dce_dc_hda_azf0stream14_dispdec 1840 // base address: 0x350 1841 #define regAZF0STREAM14_AZALIA_STREAM_INDEX 0x0432 1842 #define regAZF0STREAM14_AZALIA_STREAM_INDEX_BASE_IDX 2 1843 #define regAZF0STREAM14_AZALIA_STREAM_DATA 0x0433 1844 #define regAZF0STREAM14_AZALIA_STREAM_DATA_BASE_IDX 2 1845 1846 1847 // addressBlock: dce_dc_hda_azf0stream15_dispdec 1848 // base address: 0x358 1849 #define regAZF0STREAM15_AZALIA_STREAM_INDEX 0x0434 1850 #define regAZF0STREAM15_AZALIA_STREAM_INDEX_BASE_IDX 2 1851 #define regAZF0STREAM15_AZALIA_STREAM_DATA 0x0435 1852 #define regAZF0STREAM15_AZALIA_STREAM_DATA_BASE_IDX 2 1853 1854 1855 // addressBlock: dce_dc_hda_azf0endpoint0_dispdec 1856 // base address: 0x0 1857 #define regAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x0386 1858 #define regAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2 1859 #define regAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA 0x0387 1860 #define regAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2 1861 1862 1863 // addressBlock: dce_dc_hda_azf0endpoint1_dispdec 1864 // base address: 0x18 1865 #define regAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x038c 1866 #define regAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2 1867 #define regAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_DATA 0x038d 1868 #define regAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2 1869 1870 1871 // addressBlock: dce_dc_hda_azf0endpoint2_dispdec 1872 // base address: 0x30 1873 #define regAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x0392 1874 #define regAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2 1875 #define regAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_DATA 0x0393 1876 #define regAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2 1877 1878 1879 // addressBlock: dce_dc_hda_azf0endpoint3_dispdec 1880 // base address: 0x48 1881 #define regAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x0398 1882 #define regAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2 1883 #define regAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_DATA 0x0399 1884 #define regAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2 1885 1886 1887 // addressBlock: dce_dc_hda_azf0endpoint4_dispdec 1888 // base address: 0x60 1889 #define regAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x039e 1890 #define regAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2 1891 #define regAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_DATA 0x039f 1892 #define regAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2 1893 1894 1895 // addressBlock: dce_dc_hda_azf0endpoint5_dispdec 1896 // base address: 0x78 1897 #define regAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x03a4 1898 #define regAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2 1899 #define regAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_DATA 0x03a5 1900 #define regAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2 1901 1902 1903 // addressBlock: dce_dc_hda_azf0endpoint6_dispdec 1904 // base address: 0x90 1905 #define regAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x03aa 1906 #define regAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2 1907 #define regAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_DATA 0x03ab 1908 #define regAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2 1909 1910 1911 // addressBlock: dce_dc_hda_azf0endpoint7_dispdec 1912 // base address: 0xa8 1913 #define regAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x03b0 1914 #define regAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2 1915 #define regAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_DATA 0x03b1 1916 #define regAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2 1917 1918 1919 // addressBlock: dce_dc_hda_azf0inputendpoint0_dispdec 1920 // base address: 0x0 1921 #define regAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x043a 1922 #define regAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2 1923 #define regAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x043b 1924 #define regAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2 1925 1926 1927 // addressBlock: dce_dc_hda_azf0inputendpoint1_dispdec 1928 // base address: 0x10 1929 #define regAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x043e 1930 #define regAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2 1931 #define regAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x043f 1932 #define regAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2 1933 1934 1935 // addressBlock: dce_dc_hda_azf0inputendpoint2_dispdec 1936 // base address: 0x20 1937 #define regAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x0442 1938 #define regAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2 1939 #define regAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x0443 1940 #define regAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2 1941 1942 1943 // addressBlock: dce_dc_hda_azf0inputendpoint3_dispdec 1944 // base address: 0x30 1945 #define regAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x0446 1946 #define regAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2 1947 #define regAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x0447 1948 #define regAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2 1949 1950 1951 // addressBlock: dce_dc_hda_azf0inputendpoint4_dispdec 1952 // base address: 0x40 1953 #define regAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x044a 1954 #define regAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2 1955 #define regAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x044b 1956 #define regAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2 1957 1958 1959 // addressBlock: dce_dc_hda_azf0inputendpoint5_dispdec 1960 // base address: 0x50 1961 #define regAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x044e 1962 #define regAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2 1963 #define regAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x044f 1964 #define regAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2 1965 1966 1967 // addressBlock: dce_dc_hda_azf0inputendpoint6_dispdec 1968 // base address: 0x60 1969 #define regAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x0452 1970 #define regAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2 1971 #define regAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x0453 1972 #define regAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2 1973 1974 1975 // addressBlock: dce_dc_hda_azf0inputendpoint7_dispdec 1976 // base address: 0x70 1977 #define regAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x0456 1978 #define regAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2 1979 #define regAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x0457 1980 #define regAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2 1981 1982 1983 // addressBlock: dce_dc_dchubbubl_hubbub_dispdec 1984 // base address: 0x0 1985 #define regDCHUBBUB_ARB_DF_REQ_OUTSTAND 0x04f9 1986 #define regDCHUBBUB_ARB_DF_REQ_OUTSTAND_BASE_IDX 2 1987 #define regDCHUBBUB_ARB_SAT_LEVEL 0x04fa 1988 #define regDCHUBBUB_ARB_SAT_LEVEL_BASE_IDX 2 1989 #define regDCHUBBUB_ARB_QOS_FORCE 0x04fb 1990 #define regDCHUBBUB_ARB_QOS_FORCE_BASE_IDX 2 1991 #define regDCHUBBUB_ARB_DRAM_STATE_CNTL 0x04fc 1992 #define regDCHUBBUB_ARB_DRAM_STATE_CNTL_BASE_IDX 2 1993 #define regDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A 0x04fd 1994 #define regDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A_BASE_IDX 2 1995 #define regDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A 0x04fe 1996 #define regDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A_BASE_IDX 2 1997 #define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A 0x04ff 1998 #define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A_BASE_IDX 2 1999 #define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_A 0x0500 2000 #define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_A_BASE_IDX 2 2001 #define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A 0x0501 2002 #define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A_BASE_IDX 2 2003 #define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_A 0x0502 2004 #define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_A_BASE_IDX 2 2005 #define regDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A 0x0503 2006 #define regDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A_BASE_IDX 2 2007 #define regDCHUBBUB_ARB_FRAC_URG_BW_NOM_A 0x0504 2008 #define regDCHUBBUB_ARB_FRAC_URG_BW_NOM_A_BASE_IDX 2 2009 #define regDCHUBBUB_ARB_FRAC_URG_BW_FLIP_A 0x0505 2010 #define regDCHUBBUB_ARB_FRAC_URG_BW_FLIP_A_BASE_IDX 2 2011 #define regDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B 0x0506 2012 #define regDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B_BASE_IDX 2 2013 #define regDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B 0x0507 2014 #define regDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B_BASE_IDX 2 2015 #define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B 0x0508 2016 #define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B_BASE_IDX 2 2017 #define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_B 0x0509 2018 #define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_B_BASE_IDX 2 2019 #define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B 0x050a 2020 #define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B_BASE_IDX 2 2021 #define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_B 0x050b 2022 #define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_B_BASE_IDX 2 2023 #define regDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B 0x050c 2024 #define regDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B_BASE_IDX 2 2025 #define regDCHUBBUB_ARB_FRAC_URG_BW_NOM_B 0x050d 2026 #define regDCHUBBUB_ARB_FRAC_URG_BW_NOM_B_BASE_IDX 2 2027 #define regDCHUBBUB_ARB_FRAC_URG_BW_FLIP_B 0x050e 2028 #define regDCHUBBUB_ARB_FRAC_URG_BW_FLIP_B_BASE_IDX 2 2029 #define regDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C 0x050f 2030 #define regDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C_BASE_IDX 2 2031 #define regDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C 0x0510 2032 #define regDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C_BASE_IDX 2 2033 #define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C 0x0511 2034 #define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C_BASE_IDX 2 2035 #define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_C 0x0512 2036 #define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_C_BASE_IDX 2 2037 #define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C 0x0513 2038 #define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C_BASE_IDX 2 2039 #define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_C 0x0514 2040 #define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_C_BASE_IDX 2 2041 #define regDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C 0x0515 2042 #define regDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C_BASE_IDX 2 2043 #define regDCHUBBUB_ARB_FRAC_URG_BW_NOM_C 0x0516 2044 #define regDCHUBBUB_ARB_FRAC_URG_BW_NOM_C_BASE_IDX 2 2045 #define regDCHUBBUB_ARB_FRAC_URG_BW_FLIP_C 0x0517 2046 #define regDCHUBBUB_ARB_FRAC_URG_BW_FLIP_C_BASE_IDX 2 2047 #define regDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D 0x0518 2048 #define regDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D_BASE_IDX 2 2049 #define regDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D 0x0519 2050 #define regDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D_BASE_IDX 2 2051 #define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D 0x051a 2052 #define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D_BASE_IDX 2 2053 #define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_D 0x051b 2054 #define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_D_BASE_IDX 2 2055 #define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D 0x051c 2056 #define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D_BASE_IDX 2 2057 #define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_D 0x051d 2058 #define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_D_BASE_IDX 2 2059 #define regDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D 0x051e 2060 #define regDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D_BASE_IDX 2 2061 #define regDCHUBBUB_ARB_FRAC_URG_BW_NOM_D 0x051f 2062 #define regDCHUBBUB_ARB_FRAC_URG_BW_NOM_D_BASE_IDX 2 2063 #define regDCHUBBUB_ARB_FRAC_URG_BW_FLIP_D 0x0520 2064 #define regDCHUBBUB_ARB_FRAC_URG_BW_FLIP_D_BASE_IDX 2 2065 #define regDCHUBBUB_ARB_HOSTVM_CNTL 0x0521 2066 #define regDCHUBBUB_ARB_HOSTVM_CNTL_BASE_IDX 2 2067 #define regDCHUBBUB_ARB_WATERMARK_CHANGE_CNTL 0x0522 2068 #define regDCHUBBUB_ARB_WATERMARK_CHANGE_CNTL_BASE_IDX 2 2069 #define regDCHUBBUB_ARB_TIMEOUT_ENABLE 0x0523 2070 #define regDCHUBBUB_ARB_TIMEOUT_ENABLE_BASE_IDX 2 2071 #define regDCHUBBUB_GLOBAL_TIMER_CNTL 0x0524 2072 #define regDCHUBBUB_GLOBAL_TIMER_CNTL_BASE_IDX 2 2073 #define regSURFACE_CHECK0_ADDRESS_LSB 0x0525 2074 #define regSURFACE_CHECK0_ADDRESS_LSB_BASE_IDX 2 2075 #define regSURFACE_CHECK0_ADDRESS_MSB 0x0526 2076 #define regSURFACE_CHECK0_ADDRESS_MSB_BASE_IDX 2 2077 #define regSURFACE_CHECK1_ADDRESS_LSB 0x0527 2078 #define regSURFACE_CHECK1_ADDRESS_LSB_BASE_IDX 2 2079 #define regSURFACE_CHECK1_ADDRESS_MSB 0x0528 2080 #define regSURFACE_CHECK1_ADDRESS_MSB_BASE_IDX 2 2081 #define regSURFACE_CHECK2_ADDRESS_LSB 0x0529 2082 #define regSURFACE_CHECK2_ADDRESS_LSB_BASE_IDX 2 2083 #define regSURFACE_CHECK2_ADDRESS_MSB 0x052a 2084 #define regSURFACE_CHECK2_ADDRESS_MSB_BASE_IDX 2 2085 #define regSURFACE_CHECK3_ADDRESS_LSB 0x052b 2086 #define regSURFACE_CHECK3_ADDRESS_LSB_BASE_IDX 2 2087 #define regSURFACE_CHECK3_ADDRESS_MSB 0x052c 2088 #define regSURFACE_CHECK3_ADDRESS_MSB_BASE_IDX 2 2089 #define regVTG0_CONTROL 0x052d 2090 #define regVTG0_CONTROL_BASE_IDX 2 2091 #define regVTG1_CONTROL 0x052e 2092 #define regVTG1_CONTROL_BASE_IDX 2 2093 #define regVTG2_CONTROL 0x052f 2094 #define regVTG2_CONTROL_BASE_IDX 2 2095 #define regVTG3_CONTROL 0x0530 2096 #define regVTG3_CONTROL_BASE_IDX 2 2097 #define regDCHUBBUB_SOFT_RESET 0x0531 2098 #define regDCHUBBUB_SOFT_RESET_BASE_IDX 2 2099 #define regDCHUBBUB_CLOCK_CNTL 0x0532 2100 #define regDCHUBBUB_CLOCK_CNTL_BASE_IDX 2 2101 #define regDCFCLK_CNTL 0x0533 2102 #define regDCFCLK_CNTL_BASE_IDX 2 2103 #define regDCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL 0x0534 2104 #define regDCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL_BASE_IDX 2 2105 #define regDCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2 0x0535 2106 #define regDCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2_BASE_IDX 2 2107 #define regDCHUBBUB_VLINE_SNAPSHOT 0x0536 2108 #define regDCHUBBUB_VLINE_SNAPSHOT_BASE_IDX 2 2109 #define regDCHUBBUB_CTRL_STATUS 0x0537 2110 #define regDCHUBBUB_CTRL_STATUS_BASE_IDX 2 2111 #define regDCHUBBUB_TIMEOUT_DETECTION_CTRL1 0x053d 2112 #define regDCHUBBUB_TIMEOUT_DETECTION_CTRL1_BASE_IDX 2 2113 #define regDCHUBBUB_TIMEOUT_DETECTION_CTRL2 0x053e 2114 #define regDCHUBBUB_TIMEOUT_DETECTION_CTRL2_BASE_IDX 2 2115 #define regDCHUBBUB_TIMEOUT_INTERRUPT_STATUS 0x053f 2116 #define regDCHUBBUB_TIMEOUT_INTERRUPT_STATUS_BASE_IDX 2 2117 #define regFMON_CTRL 0x0540 2118 #define regFMON_CTRL_BASE_IDX 2 2119 #define regDCHUBBUB_TEST_DEBUG_INDEX 0x0541 2120 #define regDCHUBBUB_TEST_DEBUG_INDEX_BASE_IDX 2 2121 #define regDCHUBBUB_TEST_DEBUG_DATA 0x0542 2122 #define regDCHUBBUB_TEST_DEBUG_DATA_BASE_IDX 2 2123 2124 2125 // addressBlock: dce_dc_dchubbubl_hubbub_sdpif_dispdec 2126 // base address: 0x0 2127 #define regDCHUBBUB_SDPIF_CFG0 0x046f 2128 #define regDCHUBBUB_SDPIF_CFG0_BASE_IDX 2 2129 #define regDCHUBBUB_SDPIF_CFG1 0x0470 2130 #define regDCHUBBUB_SDPIF_CFG1_BASE_IDX 2 2131 #define regDCHUBBUB_SDPIF_CFG2 0x0471 2132 #define regDCHUBBUB_SDPIF_CFG2_BASE_IDX 2 2133 #define regVM_REQUEST_PHYSICAL 0x0472 2134 #define regVM_REQUEST_PHYSICAL_BASE_IDX 2 2135 #define regDCHUBBUB_FORCE_IO_STATUS_0 0x0473 2136 #define regDCHUBBUB_FORCE_IO_STATUS_0_BASE_IDX 2 2137 #define regDCHUBBUB_FORCE_IO_STATUS_1 0x0474 2138 #define regDCHUBBUB_FORCE_IO_STATUS_1_BASE_IDX 2 2139 #define regDCN_VM_FB_LOCATION_BASE 0x0475 2140 #define regDCN_VM_FB_LOCATION_BASE_BASE_IDX 2 2141 #define regDCN_VM_FB_LOCATION_TOP 0x0476 2142 #define regDCN_VM_FB_LOCATION_TOP_BASE_IDX 2 2143 #define regDCN_VM_FB_OFFSET 0x0477 2144 #define regDCN_VM_FB_OFFSET_BASE_IDX 2 2145 #define regDCN_VM_AGP_BOT 0x0478 2146 #define regDCN_VM_AGP_BOT_BASE_IDX 2 2147 #define regDCN_VM_AGP_TOP 0x0479 2148 #define regDCN_VM_AGP_TOP_BASE_IDX 2 2149 #define regDCN_VM_AGP_BASE 0x047a 2150 #define regDCN_VM_AGP_BASE_BASE_IDX 2 2151 #define regDCN_VM_LOCAL_HBM_ADDRESS_START 0x047b 2152 #define regDCN_VM_LOCAL_HBM_ADDRESS_START_BASE_IDX 2 2153 #define regDCN_VM_LOCAL_HBM_ADDRESS_END 0x047c 2154 #define regDCN_VM_LOCAL_HBM_ADDRESS_END_BASE_IDX 2 2155 #define regDCN_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL 0x047d 2156 #define regDCN_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL_BASE_IDX 2 2157 #define regDCHUBBUB_SDPIF_MEM_PWR_CTRL 0x0483 2158 #define regDCHUBBUB_SDPIF_MEM_PWR_CTRL_BASE_IDX 2 2159 #define regDCHUBBUB_SDPIF_MEM_PWR_STATUS 0x0484 2160 #define regDCHUBBUB_SDPIF_MEM_PWR_STATUS_BASE_IDX 2 2161 2162 2163 // addressBlock: dce_dc_dchubbubl_hubbub_ret_path_dispdec 2164 // base address: 0x0 2165 #define regDCHUBBUB_RET_PATH_DCC_CFG 0x04af 2166 #define regDCHUBBUB_RET_PATH_DCC_CFG_BASE_IDX 2 2167 #define regDCHUBBUB_RET_PATH_DCC_CFG0_0 0x04b0 2168 #define regDCHUBBUB_RET_PATH_DCC_CFG0_0_BASE_IDX 2 2169 #define regDCHUBBUB_RET_PATH_DCC_CFG0_1 0x04b1 2170 #define regDCHUBBUB_RET_PATH_DCC_CFG0_1_BASE_IDX 2 2171 #define regDCHUBBUB_RET_PATH_DCC_CFG1_0 0x04b2 2172 #define regDCHUBBUB_RET_PATH_DCC_CFG1_0_BASE_IDX 2 2173 #define regDCHUBBUB_RET_PATH_DCC_CFG1_1 0x04b3 2174 #define regDCHUBBUB_RET_PATH_DCC_CFG1_1_BASE_IDX 2 2175 #define regDCHUBBUB_RET_PATH_DCC_CFG2_0 0x04b4 2176 #define regDCHUBBUB_RET_PATH_DCC_CFG2_0_BASE_IDX 2 2177 #define regDCHUBBUB_RET_PATH_DCC_CFG2_1 0x04b5 2178 #define regDCHUBBUB_RET_PATH_DCC_CFG2_1_BASE_IDX 2 2179 #define regDCHUBBUB_RET_PATH_DCC_CFG3_0 0x04b6 2180 #define regDCHUBBUB_RET_PATH_DCC_CFG3_0_BASE_IDX 2 2181 #define regDCHUBBUB_RET_PATH_DCC_CFG3_1 0x04b7 2182 #define regDCHUBBUB_RET_PATH_DCC_CFG3_1_BASE_IDX 2 2183 #define regDCHUBBUB_RET_PATH_DCC_CFG4_0 0x04b8 2184 #define regDCHUBBUB_RET_PATH_DCC_CFG4_0_BASE_IDX 2 2185 #define regDCHUBBUB_RET_PATH_DCC_CFG4_1 0x04b9 2186 #define regDCHUBBUB_RET_PATH_DCC_CFG4_1_BASE_IDX 2 2187 #define regDCHUBBUB_RET_PATH_DCC_CFG5_0 0x04ba 2188 #define regDCHUBBUB_RET_PATH_DCC_CFG5_0_BASE_IDX 2 2189 #define regDCHUBBUB_RET_PATH_DCC_CFG5_1 0x04bb 2190 #define regDCHUBBUB_RET_PATH_DCC_CFG5_1_BASE_IDX 2 2191 #define regDCHUBBUB_RET_PATH_DCC_CFG6_0 0x04bc 2192 #define regDCHUBBUB_RET_PATH_DCC_CFG6_0_BASE_IDX 2 2193 #define regDCHUBBUB_RET_PATH_DCC_CFG6_1 0x04bd 2194 #define regDCHUBBUB_RET_PATH_DCC_CFG6_1_BASE_IDX 2 2195 #define regDCHUBBUB_RET_PATH_DCC_CFG7_0 0x04be 2196 #define regDCHUBBUB_RET_PATH_DCC_CFG7_0_BASE_IDX 2 2197 #define regDCHUBBUB_RET_PATH_DCC_CFG7_1 0x04bf 2198 #define regDCHUBBUB_RET_PATH_DCC_CFG7_1_BASE_IDX 2 2199 #define regDCHUBBUB_RET_PATH_MEM_PWR_CTRL 0x04c0 2200 #define regDCHUBBUB_RET_PATH_MEM_PWR_CTRL_BASE_IDX 2 2201 #define regDCHUBBUB_RET_PATH_MEM_PWR_STATUS 0x04c1 2202 #define regDCHUBBUB_RET_PATH_MEM_PWR_STATUS_BASE_IDX 2 2203 #define regDCHUBBUB_CRC_CTRL 0x04c2 2204 #define regDCHUBBUB_CRC_CTRL_BASE_IDX 2 2205 #define regDCHUBBUB_CRC0_VAL_R_G 0x04c3 2206 #define regDCHUBBUB_CRC0_VAL_R_G_BASE_IDX 2 2207 #define regDCHUBBUB_CRC0_VAL_B_A 0x04c4 2208 #define regDCHUBBUB_CRC0_VAL_B_A_BASE_IDX 2 2209 #define regDCHUBBUB_CRC1_VAL_R_G 0x04c5 2210 #define regDCHUBBUB_CRC1_VAL_R_G_BASE_IDX 2 2211 #define regDCHUBBUB_CRC1_VAL_B_A 0x04c6 2212 #define regDCHUBBUB_CRC1_VAL_B_A_BASE_IDX 2 2213 #define regDCHUBBUB_DCC_STAT_CNTL 0x04c7 2214 #define regDCHUBBUB_DCC_STAT_CNTL_BASE_IDX 2 2215 #define regDCHUBBUB_DCC_STAT0 0x04c8 2216 #define regDCHUBBUB_DCC_STAT0_BASE_IDX 2 2217 #define regDCHUBBUB_DCC_STAT1 0x04c9 2218 #define regDCHUBBUB_DCC_STAT1_BASE_IDX 2 2219 #define regDCHUBBUB_DCC_STAT2 0x04ca 2220 #define regDCHUBBUB_DCC_STAT2_BASE_IDX 2 2221 #define regDCHUBBUB_COMPBUF_CTRL 0x04cb 2222 #define regDCHUBBUB_COMPBUF_CTRL_BASE_IDX 2 2223 #define regDCHUBBUB_DET0_CTRL 0x04cc 2224 #define regDCHUBBUB_DET0_CTRL_BASE_IDX 2 2225 #define regDCHUBBUB_DET1_CTRL 0x04cd 2226 #define regDCHUBBUB_DET1_CTRL_BASE_IDX 2 2227 #define regDCHUBBUB_DET2_CTRL 0x04ce 2228 #define regDCHUBBUB_DET2_CTRL_BASE_IDX 2 2229 #define regDCHUBBUB_DET3_CTRL 0x04cf 2230 #define regDCHUBBUB_DET3_CTRL_BASE_IDX 2 2231 #define regDCHUBBUB_MEM_PWR_MODE_CTRL 0x04d1 2232 #define regDCHUBBUB_MEM_PWR_MODE_CTRL_BASE_IDX 2 2233 #define regCOMPBUF_MEM_PWR_CTRL_1 0x04d2 2234 #define regCOMPBUF_MEM_PWR_CTRL_1_BASE_IDX 2 2235 #define regCOMPBUF_MEM_PWR_CTRL_2 0x04d3 2236 #define regCOMPBUF_MEM_PWR_CTRL_2_BASE_IDX 2 2237 #define regDCHUBBUB_MEM_PWR_STATUS 0x04d4 2238 #define regDCHUBBUB_MEM_PWR_STATUS_BASE_IDX 2 2239 #define regCOMPBUF_RESERVED_SPACE 0x04d5 2240 #define regCOMPBUF_RESERVED_SPACE_BASE_IDX 2 2241 2242 2243 // addressBlock: dce_dc_dchubbubl_hubbub_vmrq_if_dispdec 2244 // base address: 0x0 2245 #define regDCN_VM_CONTEXT0_CNTL 0x0559 2246 #define regDCN_VM_CONTEXT0_CNTL_BASE_IDX 2 2247 #define regDCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32 0x055a 2248 #define regDCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 2249 #define regDCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32 0x055b 2250 #define regDCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 2251 #define regDCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32 0x055c 2252 #define regDCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 2253 #define regDCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32 0x055d 2254 #define regDCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 2255 #define regDCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32 0x055e 2256 #define regDCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 2257 #define regDCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32 0x055f 2258 #define regDCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 2259 #define regDCN_VM_CONTEXT1_CNTL 0x0560 2260 #define regDCN_VM_CONTEXT1_CNTL_BASE_IDX 2 2261 #define regDCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32 0x0561 2262 #define regDCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 2263 #define regDCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32 0x0562 2264 #define regDCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 2265 #define regDCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32 0x0563 2266 #define regDCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 2267 #define regDCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32 0x0564 2268 #define regDCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 2269 #define regDCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32 0x0565 2270 #define regDCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 2271 #define regDCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32 0x0566 2272 #define regDCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 2273 #define regDCN_VM_CONTEXT2_CNTL 0x0567 2274 #define regDCN_VM_CONTEXT2_CNTL_BASE_IDX 2 2275 #define regDCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32 0x0568 2276 #define regDCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 2277 #define regDCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32 0x0569 2278 #define regDCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 2279 #define regDCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32 0x056a 2280 #define regDCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 2281 #define regDCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32 0x056b 2282 #define regDCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 2283 #define regDCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32 0x056c 2284 #define regDCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 2285 #define regDCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32 0x056d 2286 #define regDCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 2287 #define regDCN_VM_CONTEXT3_CNTL 0x056e 2288 #define regDCN_VM_CONTEXT3_CNTL_BASE_IDX 2 2289 #define regDCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32 0x056f 2290 #define regDCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 2291 #define regDCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32 0x0570 2292 #define regDCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 2293 #define regDCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32 0x0571 2294 #define regDCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 2295 #define regDCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32 0x0572 2296 #define regDCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 2297 #define regDCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32 0x0573 2298 #define regDCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 2299 #define regDCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32 0x0574 2300 #define regDCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 2301 #define regDCN_VM_CONTEXT4_CNTL 0x0575 2302 #define regDCN_VM_CONTEXT4_CNTL_BASE_IDX 2 2303 #define regDCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32 0x0576 2304 #define regDCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 2305 #define regDCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32 0x0577 2306 #define regDCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 2307 #define regDCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32 0x0578 2308 #define regDCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 2309 #define regDCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32 0x0579 2310 #define regDCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 2311 #define regDCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32 0x057a 2312 #define regDCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 2313 #define regDCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32 0x057b 2314 #define regDCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 2315 #define regDCN_VM_CONTEXT5_CNTL 0x057c 2316 #define regDCN_VM_CONTEXT5_CNTL_BASE_IDX 2 2317 #define regDCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32 0x057d 2318 #define regDCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 2319 #define regDCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32 0x057e 2320 #define regDCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 2321 #define regDCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32 0x057f 2322 #define regDCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 2323 #define regDCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32 0x0580 2324 #define regDCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 2325 #define regDCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32 0x0581 2326 #define regDCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 2327 #define regDCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32 0x0582 2328 #define regDCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 2329 #define regDCN_VM_CONTEXT6_CNTL 0x0583 2330 #define regDCN_VM_CONTEXT6_CNTL_BASE_IDX 2 2331 #define regDCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32 0x0584 2332 #define regDCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 2333 #define regDCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32 0x0585 2334 #define regDCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 2335 #define regDCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32 0x0586 2336 #define regDCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 2337 #define regDCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32 0x0587 2338 #define regDCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 2339 #define regDCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32 0x0588 2340 #define regDCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 2341 #define regDCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32 0x0589 2342 #define regDCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 2343 #define regDCN_VM_CONTEXT7_CNTL 0x058a 2344 #define regDCN_VM_CONTEXT7_CNTL_BASE_IDX 2 2345 #define regDCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32 0x058b 2346 #define regDCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 2347 #define regDCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32 0x058c 2348 #define regDCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 2349 #define regDCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32 0x058d 2350 #define regDCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 2351 #define regDCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32 0x058e 2352 #define regDCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 2353 #define regDCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32 0x058f 2354 #define regDCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 2355 #define regDCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32 0x0590 2356 #define regDCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 2357 #define regDCN_VM_CONTEXT8_CNTL 0x0591 2358 #define regDCN_VM_CONTEXT8_CNTL_BASE_IDX 2 2359 #define regDCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32 0x0592 2360 #define regDCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 2361 #define regDCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32 0x0593 2362 #define regDCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 2363 #define regDCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32 0x0594 2364 #define regDCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 2365 #define regDCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32 0x0595 2366 #define regDCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 2367 #define regDCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32 0x0596 2368 #define regDCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 2369 #define regDCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32 0x0597 2370 #define regDCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 2371 #define regDCN_VM_CONTEXT9_CNTL 0x0598 2372 #define regDCN_VM_CONTEXT9_CNTL_BASE_IDX 2 2373 #define regDCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32 0x0599 2374 #define regDCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 2375 #define regDCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32 0x059a 2376 #define regDCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 2377 #define regDCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32 0x059b 2378 #define regDCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 2379 #define regDCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32 0x059c 2380 #define regDCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 2381 #define regDCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32 0x059d 2382 #define regDCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 2383 #define regDCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32 0x059e 2384 #define regDCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 2385 #define regDCN_VM_CONTEXT10_CNTL 0x059f 2386 #define regDCN_VM_CONTEXT10_CNTL_BASE_IDX 2 2387 #define regDCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32 0x05a0 2388 #define regDCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 2389 #define regDCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32 0x05a1 2390 #define regDCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 2391 #define regDCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32 0x05a2 2392 #define regDCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 2393 #define regDCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32 0x05a3 2394 #define regDCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 2395 #define regDCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32 0x05a4 2396 #define regDCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 2397 #define regDCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32 0x05a5 2398 #define regDCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 2399 #define regDCN_VM_CONTEXT11_CNTL 0x05a6 2400 #define regDCN_VM_CONTEXT11_CNTL_BASE_IDX 2 2401 #define regDCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32 0x05a7 2402 #define regDCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 2403 #define regDCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32 0x05a8 2404 #define regDCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 2405 #define regDCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32 0x05a9 2406 #define regDCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 2407 #define regDCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32 0x05aa 2408 #define regDCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 2409 #define regDCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32 0x05ab 2410 #define regDCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 2411 #define regDCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32 0x05ac 2412 #define regDCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 2413 #define regDCN_VM_CONTEXT12_CNTL 0x05ad 2414 #define regDCN_VM_CONTEXT12_CNTL_BASE_IDX 2 2415 #define regDCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32 0x05ae 2416 #define regDCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 2417 #define regDCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32 0x05af 2418 #define regDCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 2419 #define regDCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32 0x05b0 2420 #define regDCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 2421 #define regDCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32 0x05b1 2422 #define regDCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 2423 #define regDCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32 0x05b2 2424 #define regDCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 2425 #define regDCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32 0x05b3 2426 #define regDCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 2427 #define regDCN_VM_CONTEXT13_CNTL 0x05b4 2428 #define regDCN_VM_CONTEXT13_CNTL_BASE_IDX 2 2429 #define regDCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32 0x05b5 2430 #define regDCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 2431 #define regDCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32 0x05b6 2432 #define regDCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 2433 #define regDCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32 0x05b7 2434 #define regDCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 2435 #define regDCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32 0x05b8 2436 #define regDCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 2437 #define regDCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32 0x05b9 2438 #define regDCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 2439 #define regDCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32 0x05ba 2440 #define regDCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 2441 #define regDCN_VM_CONTEXT14_CNTL 0x05bb 2442 #define regDCN_VM_CONTEXT14_CNTL_BASE_IDX 2 2443 #define regDCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32 0x05bc 2444 #define regDCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 2445 #define regDCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32 0x05bd 2446 #define regDCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 2447 #define regDCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32 0x05be 2448 #define regDCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 2449 #define regDCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32 0x05bf 2450 #define regDCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 2451 #define regDCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32 0x05c0 2452 #define regDCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 2453 #define regDCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32 0x05c1 2454 #define regDCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 2455 #define regDCN_VM_CONTEXT15_CNTL 0x05c2 2456 #define regDCN_VM_CONTEXT15_CNTL_BASE_IDX 2 2457 #define regDCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32 0x05c3 2458 #define regDCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 2459 #define regDCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32 0x05c4 2460 #define regDCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 2461 #define regDCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32 0x05c5 2462 #define regDCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 2463 #define regDCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32 0x05c6 2464 #define regDCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 2465 #define regDCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32 0x05c7 2466 #define regDCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 2467 #define regDCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32 0x05c8 2468 #define regDCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 2469 #define regDCN_VM_DEFAULT_ADDR_MSB 0x05c9 2470 #define regDCN_VM_DEFAULT_ADDR_MSB_BASE_IDX 2 2471 #define regDCN_VM_DEFAULT_ADDR_LSB 0x05ca 2472 #define regDCN_VM_DEFAULT_ADDR_LSB_BASE_IDX 2 2473 #define regDCN_VM_FAULT_CNTL 0x05cb 2474 #define regDCN_VM_FAULT_CNTL_BASE_IDX 2 2475 #define regDCN_VM_FAULT_STATUS 0x05cc 2476 #define regDCN_VM_FAULT_STATUS_BASE_IDX 2 2477 #define regDCN_VM_FAULT_ADDR_MSB 0x05cd 2478 #define regDCN_VM_FAULT_ADDR_MSB_BASE_IDX 2 2479 #define regDCN_VM_FAULT_ADDR_LSB 0x05ce 2480 #define regDCN_VM_FAULT_ADDR_LSB_BASE_IDX 2 2481 2482 2483 // addressBlock: dce_dc_dchubbubl_dchubbub_dcperfmon_dc_perfmon_dispdec 2484 // base address: 0x1534 2485 #define regDC_PERFMON6_PERFCOUNTER_CNTL 0x054d 2486 #define regDC_PERFMON6_PERFCOUNTER_CNTL_BASE_IDX 2 2487 #define regDC_PERFMON6_PERFCOUNTER_CNTL2 0x054e 2488 #define regDC_PERFMON6_PERFCOUNTER_CNTL2_BASE_IDX 2 2489 #define regDC_PERFMON6_PERFCOUNTER_STATE 0x054f 2490 #define regDC_PERFMON6_PERFCOUNTER_STATE_BASE_IDX 2 2491 #define regDC_PERFMON6_PERFMON_CNTL 0x0550 2492 #define regDC_PERFMON6_PERFMON_CNTL_BASE_IDX 2 2493 #define regDC_PERFMON6_PERFMON_CNTL2 0x0551 2494 #define regDC_PERFMON6_PERFMON_CNTL2_BASE_IDX 2 2495 #define regDC_PERFMON6_PERFMON_CVALUE_INT_MISC 0x0552 2496 #define regDC_PERFMON6_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 2497 #define regDC_PERFMON6_PERFMON_CVALUE_LOW 0x0553 2498 #define regDC_PERFMON6_PERFMON_CVALUE_LOW_BASE_IDX 2 2499 #define regDC_PERFMON6_PERFMON_HI 0x0554 2500 #define regDC_PERFMON6_PERFMON_HI_BASE_IDX 2 2501 #define regDC_PERFMON6_PERFMON_LOW 0x0555 2502 #define regDC_PERFMON6_PERFMON_LOW_BASE_IDX 2 2503 2504 2505 // addressBlock: dce_dc_dcbubp0_dispdec_hubp_dispdec 2506 // base address: 0x0 2507 #define regHUBP0_DCSURF_SURFACE_CONFIG 0x05e5 2508 #define regHUBP0_DCSURF_SURFACE_CONFIG_BASE_IDX 2 2509 #define regHUBP0_DCSURF_ADDR_CONFIG 0x05e6 2510 #define regHUBP0_DCSURF_ADDR_CONFIG_BASE_IDX 2 2511 #define regHUBP0_DCSURF_TILING_CONFIG 0x05e7 2512 #define regHUBP0_DCSURF_TILING_CONFIG_BASE_IDX 2 2513 #define regHUBP0_DCSURF_PRI_VIEWPORT_START 0x05e9 2514 #define regHUBP0_DCSURF_PRI_VIEWPORT_START_BASE_IDX 2 2515 #define regHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION 0x05ea 2516 #define regHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX 2 2517 #define regHUBP0_DCSURF_PRI_VIEWPORT_START_C 0x05eb 2518 #define regHUBP0_DCSURF_PRI_VIEWPORT_START_C_BASE_IDX 2 2519 #define regHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C 0x05ec 2520 #define regHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C_BASE_IDX 2 2521 #define regHUBP0_DCSURF_SEC_VIEWPORT_START 0x05ed 2522 #define regHUBP0_DCSURF_SEC_VIEWPORT_START_BASE_IDX 2 2523 #define regHUBP0_DCSURF_SEC_VIEWPORT_DIMENSION 0x05ee 2524 #define regHUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_BASE_IDX 2 2525 #define regHUBP0_DCSURF_SEC_VIEWPORT_START_C 0x05ef 2526 #define regHUBP0_DCSURF_SEC_VIEWPORT_START_C_BASE_IDX 2 2527 #define regHUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_C 0x05f0 2528 #define regHUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_C_BASE_IDX 2 2529 #define regHUBP0_DCHUBP_REQ_SIZE_CONFIG 0x05f1 2530 #define regHUBP0_DCHUBP_REQ_SIZE_CONFIG_BASE_IDX 2 2531 #define regHUBP0_DCHUBP_REQ_SIZE_CONFIG_C 0x05f2 2532 #define regHUBP0_DCHUBP_REQ_SIZE_CONFIG_C_BASE_IDX 2 2533 #define regHUBP0_DCHUBP_CNTL 0x05f3 2534 #define regHUBP0_DCHUBP_CNTL_BASE_IDX 2 2535 #define regHUBP0_HUBP_CLK_CNTL 0x05f4 2536 #define regHUBP0_HUBP_CLK_CNTL_BASE_IDX 2 2537 #define regHUBP0_DCHUBP_VMPG_CONFIG 0x05f5 2538 #define regHUBP0_DCHUBP_VMPG_CONFIG_BASE_IDX 2 2539 #define regHUBP0_HUBPREQ_DEBUG_DB 0x05f6 2540 #define regHUBP0_HUBPREQ_DEBUG_DB_BASE_IDX 2 2541 #define regHUBP0_HUBPREQ_DEBUG 0x05f7 2542 #define regHUBP0_HUBPREQ_DEBUG_BASE_IDX 2 2543 #define regHUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK 0x05fb 2544 #define regHUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK_BASE_IDX 2 2545 #define regHUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK 0x05fc 2546 #define regHUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK_BASE_IDX 2 2547 2548 2549 // addressBlock: dce_dc_dcbubp0_dispdec_hubpreq_dispdec 2550 // base address: 0x0 2551 #define regHUBPREQ0_DCSURF_SURFACE_PITCH 0x0607 2552 #define regHUBPREQ0_DCSURF_SURFACE_PITCH_BASE_IDX 2 2553 #define regHUBPREQ0_DCSURF_SURFACE_PITCH_C 0x0608 2554 #define regHUBPREQ0_DCSURF_SURFACE_PITCH_C_BASE_IDX 2 2555 #define regHUBPREQ0_VMID_SETTINGS_0 0x0609 2556 #define regHUBPREQ0_VMID_SETTINGS_0_BASE_IDX 2 2557 #define regHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS 0x060a 2558 #define regHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_BASE_IDX 2 2559 #define regHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH 0x060b 2560 #define regHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2 2561 #define regHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_C 0x060c 2562 #define regHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_C_BASE_IDX 2 2563 #define regHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C 0x060d 2564 #define regHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 2565 #define regHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS 0x060e 2566 #define regHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_BASE_IDX 2 2567 #define regHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH 0x060f 2568 #define regHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2 2569 #define regHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_C 0x0610 2570 #define regHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_C_BASE_IDX 2 2571 #define regHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C 0x0611 2572 #define regHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 2573 #define regHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS 0x0612 2574 #define regHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_BASE_IDX 2 2575 #define regHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH 0x0613 2576 #define regHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2 2577 #define regHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C 0x0614 2578 #define regHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C_BASE_IDX 2 2579 #define regHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C 0x0615 2580 #define regHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 2581 #define regHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS 0x0616 2582 #define regHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_BASE_IDX 2 2583 #define regHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH 0x0617 2584 #define regHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2 2585 #define regHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C 0x0618 2586 #define regHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C_BASE_IDX 2 2587 #define regHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C 0x0619 2588 #define regHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 2589 #define regHUBPREQ0_DCSURF_SURFACE_CONTROL 0x061a 2590 #define regHUBPREQ0_DCSURF_SURFACE_CONTROL_BASE_IDX 2 2591 #define regHUBPREQ0_DCSURF_FLIP_CONTROL 0x061b 2592 #define regHUBPREQ0_DCSURF_FLIP_CONTROL_BASE_IDX 2 2593 #define regHUBPREQ0_DCSURF_FLIP_CONTROL2 0x061c 2594 #define regHUBPREQ0_DCSURF_FLIP_CONTROL2_BASE_IDX 2 2595 #define regHUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT 0x0620 2596 #define regHUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT_BASE_IDX 2 2597 #define regHUBPREQ0_DCSURF_SURFACE_INUSE 0x0621 2598 #define regHUBPREQ0_DCSURF_SURFACE_INUSE_BASE_IDX 2 2599 #define regHUBPREQ0_DCSURF_SURFACE_INUSE_HIGH 0x0622 2600 #define regHUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_BASE_IDX 2 2601 #define regHUBPREQ0_DCSURF_SURFACE_INUSE_C 0x0623 2602 #define regHUBPREQ0_DCSURF_SURFACE_INUSE_C_BASE_IDX 2 2603 #define regHUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_C 0x0624 2604 #define regHUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_C_BASE_IDX 2 2605 #define regHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE 0x0625 2606 #define regHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_BASE_IDX 2 2607 #define regHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH 0x0626 2608 #define regHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_BASE_IDX 2 2609 #define regHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_C 0x0627 2610 #define regHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_C_BASE_IDX 2 2611 #define regHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C 0x0628 2612 #define regHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C_BASE_IDX 2 2613 #define regHUBPREQ0_DCN_EXPANSION_MODE 0x0629 2614 #define regHUBPREQ0_DCN_EXPANSION_MODE_BASE_IDX 2 2615 #define regHUBPREQ0_DCN_TTU_QOS_WM 0x062a 2616 #define regHUBPREQ0_DCN_TTU_QOS_WM_BASE_IDX 2 2617 #define regHUBPREQ0_DCN_GLOBAL_TTU_CNTL 0x062b 2618 #define regHUBPREQ0_DCN_GLOBAL_TTU_CNTL_BASE_IDX 2 2619 #define regHUBPREQ0_DCN_SURF0_TTU_CNTL0 0x062c 2620 #define regHUBPREQ0_DCN_SURF0_TTU_CNTL0_BASE_IDX 2 2621 #define regHUBPREQ0_DCN_SURF0_TTU_CNTL1 0x062d 2622 #define regHUBPREQ0_DCN_SURF0_TTU_CNTL1_BASE_IDX 2 2623 #define regHUBPREQ0_DCN_SURF1_TTU_CNTL0 0x062e 2624 #define regHUBPREQ0_DCN_SURF1_TTU_CNTL0_BASE_IDX 2 2625 #define regHUBPREQ0_DCN_SURF1_TTU_CNTL1 0x062f 2626 #define regHUBPREQ0_DCN_SURF1_TTU_CNTL1_BASE_IDX 2 2627 #define regHUBPREQ0_DCN_CUR0_TTU_CNTL0 0x0630 2628 #define regHUBPREQ0_DCN_CUR0_TTU_CNTL0_BASE_IDX 2 2629 #define regHUBPREQ0_DCN_CUR0_TTU_CNTL1 0x0631 2630 #define regHUBPREQ0_DCN_CUR0_TTU_CNTL1_BASE_IDX 2 2631 #define regHUBPREQ0_DCN_CUR1_TTU_CNTL0 0x0632 2632 #define regHUBPREQ0_DCN_CUR1_TTU_CNTL0_BASE_IDX 2 2633 #define regHUBPREQ0_DCN_CUR1_TTU_CNTL1 0x0633 2634 #define regHUBPREQ0_DCN_CUR1_TTU_CNTL1_BASE_IDX 2 2635 #define regHUBPREQ0_DCN_DMDATA_VM_CNTL 0x0634 2636 #define regHUBPREQ0_DCN_DMDATA_VM_CNTL_BASE_IDX 2 2637 #define regHUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR 0x0635 2638 #define regHUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_BASE_IDX 2 2639 #define regHUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR 0x0636 2640 #define regHUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_BASE_IDX 2 2641 #define regHUBPREQ0_DCN_VM_MX_L1_TLB_CNTL 0x0643 2642 #define regHUBPREQ0_DCN_VM_MX_L1_TLB_CNTL_BASE_IDX 2 2643 #define regHUBPREQ0_BLANK_OFFSET_0 0x0644 2644 #define regHUBPREQ0_BLANK_OFFSET_0_BASE_IDX 2 2645 #define regHUBPREQ0_BLANK_OFFSET_1 0x0645 2646 #define regHUBPREQ0_BLANK_OFFSET_1_BASE_IDX 2 2647 #define regHUBPREQ0_DST_DIMENSIONS 0x0646 2648 #define regHUBPREQ0_DST_DIMENSIONS_BASE_IDX 2 2649 #define regHUBPREQ0_DST_AFTER_SCALER 0x0647 2650 #define regHUBPREQ0_DST_AFTER_SCALER_BASE_IDX 2 2651 #define regHUBPREQ0_PREFETCH_SETTINGS 0x0648 2652 #define regHUBPREQ0_PREFETCH_SETTINGS_BASE_IDX 2 2653 #define regHUBPREQ0_PREFETCH_SETTINGS_C 0x0649 2654 #define regHUBPREQ0_PREFETCH_SETTINGS_C_BASE_IDX 2 2655 #define regHUBPREQ0_VBLANK_PARAMETERS_0 0x064a 2656 #define regHUBPREQ0_VBLANK_PARAMETERS_0_BASE_IDX 2 2657 #define regHUBPREQ0_VBLANK_PARAMETERS_1 0x064b 2658 #define regHUBPREQ0_VBLANK_PARAMETERS_1_BASE_IDX 2 2659 #define regHUBPREQ0_VBLANK_PARAMETERS_2 0x064c 2660 #define regHUBPREQ0_VBLANK_PARAMETERS_2_BASE_IDX 2 2661 #define regHUBPREQ0_VBLANK_PARAMETERS_3 0x064d 2662 #define regHUBPREQ0_VBLANK_PARAMETERS_3_BASE_IDX 2 2663 #define regHUBPREQ0_VBLANK_PARAMETERS_4 0x064e 2664 #define regHUBPREQ0_VBLANK_PARAMETERS_4_BASE_IDX 2 2665 #define regHUBPREQ0_FLIP_PARAMETERS_0 0x064f 2666 #define regHUBPREQ0_FLIP_PARAMETERS_0_BASE_IDX 2 2667 #define regHUBPREQ0_FLIP_PARAMETERS_1 0x0650 2668 #define regHUBPREQ0_FLIP_PARAMETERS_1_BASE_IDX 2 2669 #define regHUBPREQ0_FLIP_PARAMETERS_2 0x0651 2670 #define regHUBPREQ0_FLIP_PARAMETERS_2_BASE_IDX 2 2671 #define regHUBPREQ0_NOM_PARAMETERS_0 0x0652 2672 #define regHUBPREQ0_NOM_PARAMETERS_0_BASE_IDX 2 2673 #define regHUBPREQ0_NOM_PARAMETERS_1 0x0653 2674 #define regHUBPREQ0_NOM_PARAMETERS_1_BASE_IDX 2 2675 #define regHUBPREQ0_NOM_PARAMETERS_2 0x0654 2676 #define regHUBPREQ0_NOM_PARAMETERS_2_BASE_IDX 2 2677 #define regHUBPREQ0_NOM_PARAMETERS_3 0x0655 2678 #define regHUBPREQ0_NOM_PARAMETERS_3_BASE_IDX 2 2679 #define regHUBPREQ0_NOM_PARAMETERS_4 0x0656 2680 #define regHUBPREQ0_NOM_PARAMETERS_4_BASE_IDX 2 2681 #define regHUBPREQ0_NOM_PARAMETERS_5 0x0657 2682 #define regHUBPREQ0_NOM_PARAMETERS_5_BASE_IDX 2 2683 #define regHUBPREQ0_NOM_PARAMETERS_6 0x0658 2684 #define regHUBPREQ0_NOM_PARAMETERS_6_BASE_IDX 2 2685 #define regHUBPREQ0_NOM_PARAMETERS_7 0x0659 2686 #define regHUBPREQ0_NOM_PARAMETERS_7_BASE_IDX 2 2687 #define regHUBPREQ0_PER_LINE_DELIVERY_PRE 0x065a 2688 #define regHUBPREQ0_PER_LINE_DELIVERY_PRE_BASE_IDX 2 2689 #define regHUBPREQ0_PER_LINE_DELIVERY 0x065b 2690 #define regHUBPREQ0_PER_LINE_DELIVERY_BASE_IDX 2 2691 #define regHUBPREQ0_CURSOR_SETTINGS 0x065c 2692 #define regHUBPREQ0_CURSOR_SETTINGS_BASE_IDX 2 2693 #define regHUBPREQ0_REF_FREQ_TO_PIX_FREQ 0x065d 2694 #define regHUBPREQ0_REF_FREQ_TO_PIX_FREQ_BASE_IDX 2 2695 #define regHUBPREQ0_DST_Y_DELTA_DRQ_LIMIT 0x065e 2696 #define regHUBPREQ0_DST_Y_DELTA_DRQ_LIMIT_BASE_IDX 2 2697 #define regHUBPREQ0_HUBPREQ_MEM_PWR_CTRL 0x065f 2698 #define regHUBPREQ0_HUBPREQ_MEM_PWR_CTRL_BASE_IDX 2 2699 #define regHUBPREQ0_HUBPREQ_MEM_PWR_STATUS 0x0660 2700 #define regHUBPREQ0_HUBPREQ_MEM_PWR_STATUS_BASE_IDX 2 2701 #define regHUBPREQ0_VBLANK_PARAMETERS_5 0x0663 2702 #define regHUBPREQ0_VBLANK_PARAMETERS_5_BASE_IDX 2 2703 #define regHUBPREQ0_VBLANK_PARAMETERS_6 0x0664 2704 #define regHUBPREQ0_VBLANK_PARAMETERS_6_BASE_IDX 2 2705 #define regHUBPREQ0_FLIP_PARAMETERS_3 0x0665 2706 #define regHUBPREQ0_FLIP_PARAMETERS_3_BASE_IDX 2 2707 #define regHUBPREQ0_FLIP_PARAMETERS_4 0x0666 2708 #define regHUBPREQ0_FLIP_PARAMETERS_4_BASE_IDX 2 2709 #define regHUBPREQ0_FLIP_PARAMETERS_5 0x0667 2710 #define regHUBPREQ0_FLIP_PARAMETERS_5_BASE_IDX 2 2711 #define regHUBPREQ0_FLIP_PARAMETERS_6 0x0668 2712 #define regHUBPREQ0_FLIP_PARAMETERS_6_BASE_IDX 2 2713 2714 2715 // addressBlock: dce_dc_dcbubp0_dispdec_hubpret_dispdec 2716 // base address: 0x0 2717 #define regHUBPRET0_HUBPRET_CONTROL 0x066c 2718 #define regHUBPRET0_HUBPRET_CONTROL_BASE_IDX 2 2719 #define regHUBPRET0_HUBPRET_MEM_PWR_CTRL 0x066d 2720 #define regHUBPRET0_HUBPRET_MEM_PWR_CTRL_BASE_IDX 2 2721 #define regHUBPRET0_HUBPRET_MEM_PWR_STATUS 0x066e 2722 #define regHUBPRET0_HUBPRET_MEM_PWR_STATUS_BASE_IDX 2 2723 #define regHUBPRET0_HUBPRET_READ_LINE_CTRL0 0x066f 2724 #define regHUBPRET0_HUBPRET_READ_LINE_CTRL0_BASE_IDX 2 2725 #define regHUBPRET0_HUBPRET_READ_LINE_CTRL1 0x0670 2726 #define regHUBPRET0_HUBPRET_READ_LINE_CTRL1_BASE_IDX 2 2727 #define regHUBPRET0_HUBPRET_READ_LINE0 0x0671 2728 #define regHUBPRET0_HUBPRET_READ_LINE0_BASE_IDX 2 2729 #define regHUBPRET0_HUBPRET_READ_LINE1 0x0672 2730 #define regHUBPRET0_HUBPRET_READ_LINE1_BASE_IDX 2 2731 #define regHUBPRET0_HUBPRET_INTERRUPT 0x0673 2732 #define regHUBPRET0_HUBPRET_INTERRUPT_BASE_IDX 2 2733 #define regHUBPRET0_HUBPRET_READ_LINE_VALUE 0x0674 2734 #define regHUBPRET0_HUBPRET_READ_LINE_VALUE_BASE_IDX 2 2735 #define regHUBPRET0_HUBPRET_READ_LINE_STATUS 0x0675 2736 #define regHUBPRET0_HUBPRET_READ_LINE_STATUS_BASE_IDX 2 2737 2738 2739 // addressBlock: dce_dc_dcbubp0_dispdec_cursor0_dispdec 2740 // base address: 0x0 2741 #define regCURSOR0_0_CURSOR_CONTROL 0x0678 2742 #define regCURSOR0_0_CURSOR_CONTROL_BASE_IDX 2 2743 #define regCURSOR0_0_CURSOR_SURFACE_ADDRESS 0x0679 2744 #define regCURSOR0_0_CURSOR_SURFACE_ADDRESS_BASE_IDX 2 2745 #define regCURSOR0_0_CURSOR_SURFACE_ADDRESS_HIGH 0x067a 2746 #define regCURSOR0_0_CURSOR_SURFACE_ADDRESS_HIGH_BASE_IDX 2 2747 #define regCURSOR0_0_CURSOR_SIZE 0x067b 2748 #define regCURSOR0_0_CURSOR_SIZE_BASE_IDX 2 2749 #define regCURSOR0_0_CURSOR_POSITION 0x067c 2750 #define regCURSOR0_0_CURSOR_POSITION_BASE_IDX 2 2751 #define regCURSOR0_0_CURSOR_HOT_SPOT 0x067d 2752 #define regCURSOR0_0_CURSOR_HOT_SPOT_BASE_IDX 2 2753 #define regCURSOR0_0_CURSOR_STEREO_CONTROL 0x067e 2754 #define regCURSOR0_0_CURSOR_STEREO_CONTROL_BASE_IDX 2 2755 #define regCURSOR0_0_CURSOR_DST_OFFSET 0x067f 2756 #define regCURSOR0_0_CURSOR_DST_OFFSET_BASE_IDX 2 2757 #define regCURSOR0_0_CURSOR_MEM_PWR_CTRL 0x0680 2758 #define regCURSOR0_0_CURSOR_MEM_PWR_CTRL_BASE_IDX 2 2759 #define regCURSOR0_0_CURSOR_MEM_PWR_STATUS 0x0681 2760 #define regCURSOR0_0_CURSOR_MEM_PWR_STATUS_BASE_IDX 2 2761 #define regCURSOR0_0_DMDATA_ADDRESS_HIGH 0x0682 2762 #define regCURSOR0_0_DMDATA_ADDRESS_HIGH_BASE_IDX 2 2763 #define regCURSOR0_0_DMDATA_ADDRESS_LOW 0x0683 2764 #define regCURSOR0_0_DMDATA_ADDRESS_LOW_BASE_IDX 2 2765 #define regCURSOR0_0_DMDATA_CNTL 0x0684 2766 #define regCURSOR0_0_DMDATA_CNTL_BASE_IDX 2 2767 #define regCURSOR0_0_DMDATA_QOS_CNTL 0x0685 2768 #define regCURSOR0_0_DMDATA_QOS_CNTL_BASE_IDX 2 2769 #define regCURSOR0_0_DMDATA_STATUS 0x0686 2770 #define regCURSOR0_0_DMDATA_STATUS_BASE_IDX 2 2771 #define regCURSOR0_0_DMDATA_SW_CNTL 0x0687 2772 #define regCURSOR0_0_DMDATA_SW_CNTL_BASE_IDX 2 2773 #define regCURSOR0_0_DMDATA_SW_DATA 0x0688 2774 #define regCURSOR0_0_DMDATA_SW_DATA_BASE_IDX 2 2775 2776 2777 // addressBlock: dce_dc_dcbubp0_dispdec_hubp_dcperfmon_dc_perfmon_dispdec 2778 // base address: 0x1a74 2779 #define regDC_PERFMON7_PERFCOUNTER_CNTL 0x069d 2780 #define regDC_PERFMON7_PERFCOUNTER_CNTL_BASE_IDX 2 2781 #define regDC_PERFMON7_PERFCOUNTER_CNTL2 0x069e 2782 #define regDC_PERFMON7_PERFCOUNTER_CNTL2_BASE_IDX 2 2783 #define regDC_PERFMON7_PERFCOUNTER_STATE 0x069f 2784 #define regDC_PERFMON7_PERFCOUNTER_STATE_BASE_IDX 2 2785 #define regDC_PERFMON7_PERFMON_CNTL 0x06a0 2786 #define regDC_PERFMON7_PERFMON_CNTL_BASE_IDX 2 2787 #define regDC_PERFMON7_PERFMON_CNTL2 0x06a1 2788 #define regDC_PERFMON7_PERFMON_CNTL2_BASE_IDX 2 2789 #define regDC_PERFMON7_PERFMON_CVALUE_INT_MISC 0x06a2 2790 #define regDC_PERFMON7_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 2791 #define regDC_PERFMON7_PERFMON_CVALUE_LOW 0x06a3 2792 #define regDC_PERFMON7_PERFMON_CVALUE_LOW_BASE_IDX 2 2793 #define regDC_PERFMON7_PERFMON_HI 0x06a4 2794 #define regDC_PERFMON7_PERFMON_HI_BASE_IDX 2 2795 #define regDC_PERFMON7_PERFMON_LOW 0x06a5 2796 #define regDC_PERFMON7_PERFMON_LOW_BASE_IDX 2 2797 2798 2799 // addressBlock: dce_dc_dcbubp1_dispdec_hubp_dispdec 2800 // base address: 0x370 2801 #define regHUBP1_DCSURF_SURFACE_CONFIG 0x06c1 2802 #define regHUBP1_DCSURF_SURFACE_CONFIG_BASE_IDX 2 2803 #define regHUBP1_DCSURF_ADDR_CONFIG 0x06c2 2804 #define regHUBP1_DCSURF_ADDR_CONFIG_BASE_IDX 2 2805 #define regHUBP1_DCSURF_TILING_CONFIG 0x06c3 2806 #define regHUBP1_DCSURF_TILING_CONFIG_BASE_IDX 2 2807 #define regHUBP1_DCSURF_PRI_VIEWPORT_START 0x06c5 2808 #define regHUBP1_DCSURF_PRI_VIEWPORT_START_BASE_IDX 2 2809 #define regHUBP1_DCSURF_PRI_VIEWPORT_DIMENSION 0x06c6 2810 #define regHUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX 2 2811 #define regHUBP1_DCSURF_PRI_VIEWPORT_START_C 0x06c7 2812 #define regHUBP1_DCSURF_PRI_VIEWPORT_START_C_BASE_IDX 2 2813 #define regHUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_C 0x06c8 2814 #define regHUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_C_BASE_IDX 2 2815 #define regHUBP1_DCSURF_SEC_VIEWPORT_START 0x06c9 2816 #define regHUBP1_DCSURF_SEC_VIEWPORT_START_BASE_IDX 2 2817 #define regHUBP1_DCSURF_SEC_VIEWPORT_DIMENSION 0x06ca 2818 #define regHUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_BASE_IDX 2 2819 #define regHUBP1_DCSURF_SEC_VIEWPORT_START_C 0x06cb 2820 #define regHUBP1_DCSURF_SEC_VIEWPORT_START_C_BASE_IDX 2 2821 #define regHUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_C 0x06cc 2822 #define regHUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_C_BASE_IDX 2 2823 #define regHUBP1_DCHUBP_REQ_SIZE_CONFIG 0x06cd 2824 #define regHUBP1_DCHUBP_REQ_SIZE_CONFIG_BASE_IDX 2 2825 #define regHUBP1_DCHUBP_REQ_SIZE_CONFIG_C 0x06ce 2826 #define regHUBP1_DCHUBP_REQ_SIZE_CONFIG_C_BASE_IDX 2 2827 #define regHUBP1_DCHUBP_CNTL 0x06cf 2828 #define regHUBP1_DCHUBP_CNTL_BASE_IDX 2 2829 #define regHUBP1_HUBP_CLK_CNTL 0x06d0 2830 #define regHUBP1_HUBP_CLK_CNTL_BASE_IDX 2 2831 #define regHUBP1_DCHUBP_VMPG_CONFIG 0x06d1 2832 #define regHUBP1_DCHUBP_VMPG_CONFIG_BASE_IDX 2 2833 #define regHUBP1_HUBPREQ_DEBUG_DB 0x06d2 2834 #define regHUBP1_HUBPREQ_DEBUG_DB_BASE_IDX 2 2835 #define regHUBP1_HUBPREQ_DEBUG 0x06d3 2836 #define regHUBP1_HUBPREQ_DEBUG_BASE_IDX 2 2837 #define regHUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK 0x06d7 2838 #define regHUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK_BASE_IDX 2 2839 #define regHUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK 0x06d8 2840 #define regHUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK_BASE_IDX 2 2841 2842 2843 // addressBlock: dce_dc_dcbubp1_dispdec_hubpreq_dispdec 2844 // base address: 0x370 2845 #define regHUBPREQ1_DCSURF_SURFACE_PITCH 0x06e3 2846 #define regHUBPREQ1_DCSURF_SURFACE_PITCH_BASE_IDX 2 2847 #define regHUBPREQ1_DCSURF_SURFACE_PITCH_C 0x06e4 2848 #define regHUBPREQ1_DCSURF_SURFACE_PITCH_C_BASE_IDX 2 2849 #define regHUBPREQ1_VMID_SETTINGS_0 0x06e5 2850 #define regHUBPREQ1_VMID_SETTINGS_0_BASE_IDX 2 2851 #define regHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS 0x06e6 2852 #define regHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_BASE_IDX 2 2853 #define regHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH 0x06e7 2854 #define regHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2 2855 #define regHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_C 0x06e8 2856 #define regHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_C_BASE_IDX 2 2857 #define regHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C 0x06e9 2858 #define regHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 2859 #define regHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS 0x06ea 2860 #define regHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_BASE_IDX 2 2861 #define regHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH 0x06eb 2862 #define regHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2 2863 #define regHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_C 0x06ec 2864 #define regHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_C_BASE_IDX 2 2865 #define regHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C 0x06ed 2866 #define regHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 2867 #define regHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS 0x06ee 2868 #define regHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_BASE_IDX 2 2869 #define regHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH 0x06ef 2870 #define regHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2 2871 #define regHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C 0x06f0 2872 #define regHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C_BASE_IDX 2 2873 #define regHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C 0x06f1 2874 #define regHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 2875 #define regHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS 0x06f2 2876 #define regHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_BASE_IDX 2 2877 #define regHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH 0x06f3 2878 #define regHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2 2879 #define regHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C 0x06f4 2880 #define regHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C_BASE_IDX 2 2881 #define regHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C 0x06f5 2882 #define regHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 2883 #define regHUBPREQ1_DCSURF_SURFACE_CONTROL 0x06f6 2884 #define regHUBPREQ1_DCSURF_SURFACE_CONTROL_BASE_IDX 2 2885 #define regHUBPREQ1_DCSURF_FLIP_CONTROL 0x06f7 2886 #define regHUBPREQ1_DCSURF_FLIP_CONTROL_BASE_IDX 2 2887 #define regHUBPREQ1_DCSURF_FLIP_CONTROL2 0x06f8 2888 #define regHUBPREQ1_DCSURF_FLIP_CONTROL2_BASE_IDX 2 2889 #define regHUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT 0x06fc 2890 #define regHUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT_BASE_IDX 2 2891 #define regHUBPREQ1_DCSURF_SURFACE_INUSE 0x06fd 2892 #define regHUBPREQ1_DCSURF_SURFACE_INUSE_BASE_IDX 2 2893 #define regHUBPREQ1_DCSURF_SURFACE_INUSE_HIGH 0x06fe 2894 #define regHUBPREQ1_DCSURF_SURFACE_INUSE_HIGH_BASE_IDX 2 2895 #define regHUBPREQ1_DCSURF_SURFACE_INUSE_C 0x06ff 2896 #define regHUBPREQ1_DCSURF_SURFACE_INUSE_C_BASE_IDX 2 2897 #define regHUBPREQ1_DCSURF_SURFACE_INUSE_HIGH_C 0x0700 2898 #define regHUBPREQ1_DCSURF_SURFACE_INUSE_HIGH_C_BASE_IDX 2 2899 #define regHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE 0x0701 2900 #define regHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_BASE_IDX 2 2901 #define regHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH 0x0702 2902 #define regHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_BASE_IDX 2 2903 #define regHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_C 0x0703 2904 #define regHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_C_BASE_IDX 2 2905 #define regHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C 0x0704 2906 #define regHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C_BASE_IDX 2 2907 #define regHUBPREQ1_DCN_EXPANSION_MODE 0x0705 2908 #define regHUBPREQ1_DCN_EXPANSION_MODE_BASE_IDX 2 2909 #define regHUBPREQ1_DCN_TTU_QOS_WM 0x0706 2910 #define regHUBPREQ1_DCN_TTU_QOS_WM_BASE_IDX 2 2911 #define regHUBPREQ1_DCN_GLOBAL_TTU_CNTL 0x0707 2912 #define regHUBPREQ1_DCN_GLOBAL_TTU_CNTL_BASE_IDX 2 2913 #define regHUBPREQ1_DCN_SURF0_TTU_CNTL0 0x0708 2914 #define regHUBPREQ1_DCN_SURF0_TTU_CNTL0_BASE_IDX 2 2915 #define regHUBPREQ1_DCN_SURF0_TTU_CNTL1 0x0709 2916 #define regHUBPREQ1_DCN_SURF0_TTU_CNTL1_BASE_IDX 2 2917 #define regHUBPREQ1_DCN_SURF1_TTU_CNTL0 0x070a 2918 #define regHUBPREQ1_DCN_SURF1_TTU_CNTL0_BASE_IDX 2 2919 #define regHUBPREQ1_DCN_SURF1_TTU_CNTL1 0x070b 2920 #define regHUBPREQ1_DCN_SURF1_TTU_CNTL1_BASE_IDX 2 2921 #define regHUBPREQ1_DCN_CUR0_TTU_CNTL0 0x070c 2922 #define regHUBPREQ1_DCN_CUR0_TTU_CNTL0_BASE_IDX 2 2923 #define regHUBPREQ1_DCN_CUR0_TTU_CNTL1 0x070d 2924 #define regHUBPREQ1_DCN_CUR0_TTU_CNTL1_BASE_IDX 2 2925 #define regHUBPREQ1_DCN_CUR1_TTU_CNTL0 0x070e 2926 #define regHUBPREQ1_DCN_CUR1_TTU_CNTL0_BASE_IDX 2 2927 #define regHUBPREQ1_DCN_CUR1_TTU_CNTL1 0x070f 2928 #define regHUBPREQ1_DCN_CUR1_TTU_CNTL1_BASE_IDX 2 2929 #define regHUBPREQ1_DCN_DMDATA_VM_CNTL 0x0710 2930 #define regHUBPREQ1_DCN_DMDATA_VM_CNTL_BASE_IDX 2 2931 #define regHUBPREQ1_DCN_VM_SYSTEM_APERTURE_LOW_ADDR 0x0711 2932 #define regHUBPREQ1_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_BASE_IDX 2 2933 #define regHUBPREQ1_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR 0x0712 2934 #define regHUBPREQ1_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_BASE_IDX 2 2935 #define regHUBPREQ1_DCN_VM_MX_L1_TLB_CNTL 0x071f 2936 #define regHUBPREQ1_DCN_VM_MX_L1_TLB_CNTL_BASE_IDX 2 2937 #define regHUBPREQ1_BLANK_OFFSET_0 0x0720 2938 #define regHUBPREQ1_BLANK_OFFSET_0_BASE_IDX 2 2939 #define regHUBPREQ1_BLANK_OFFSET_1 0x0721 2940 #define regHUBPREQ1_BLANK_OFFSET_1_BASE_IDX 2 2941 #define regHUBPREQ1_DST_DIMENSIONS 0x0722 2942 #define regHUBPREQ1_DST_DIMENSIONS_BASE_IDX 2 2943 #define regHUBPREQ1_DST_AFTER_SCALER 0x0723 2944 #define regHUBPREQ1_DST_AFTER_SCALER_BASE_IDX 2 2945 #define regHUBPREQ1_PREFETCH_SETTINGS 0x0724 2946 #define regHUBPREQ1_PREFETCH_SETTINGS_BASE_IDX 2 2947 #define regHUBPREQ1_PREFETCH_SETTINGS_C 0x0725 2948 #define regHUBPREQ1_PREFETCH_SETTINGS_C_BASE_IDX 2 2949 #define regHUBPREQ1_VBLANK_PARAMETERS_0 0x0726 2950 #define regHUBPREQ1_VBLANK_PARAMETERS_0_BASE_IDX 2 2951 #define regHUBPREQ1_VBLANK_PARAMETERS_1 0x0727 2952 #define regHUBPREQ1_VBLANK_PARAMETERS_1_BASE_IDX 2 2953 #define regHUBPREQ1_VBLANK_PARAMETERS_2 0x0728 2954 #define regHUBPREQ1_VBLANK_PARAMETERS_2_BASE_IDX 2 2955 #define regHUBPREQ1_VBLANK_PARAMETERS_3 0x0729 2956 #define regHUBPREQ1_VBLANK_PARAMETERS_3_BASE_IDX 2 2957 #define regHUBPREQ1_VBLANK_PARAMETERS_4 0x072a 2958 #define regHUBPREQ1_VBLANK_PARAMETERS_4_BASE_IDX 2 2959 #define regHUBPREQ1_FLIP_PARAMETERS_0 0x072b 2960 #define regHUBPREQ1_FLIP_PARAMETERS_0_BASE_IDX 2 2961 #define regHUBPREQ1_FLIP_PARAMETERS_1 0x072c 2962 #define regHUBPREQ1_FLIP_PARAMETERS_1_BASE_IDX 2 2963 #define regHUBPREQ1_FLIP_PARAMETERS_2 0x072d 2964 #define regHUBPREQ1_FLIP_PARAMETERS_2_BASE_IDX 2 2965 #define regHUBPREQ1_NOM_PARAMETERS_0 0x072e 2966 #define regHUBPREQ1_NOM_PARAMETERS_0_BASE_IDX 2 2967 #define regHUBPREQ1_NOM_PARAMETERS_1 0x072f 2968 #define regHUBPREQ1_NOM_PARAMETERS_1_BASE_IDX 2 2969 #define regHUBPREQ1_NOM_PARAMETERS_2 0x0730 2970 #define regHUBPREQ1_NOM_PARAMETERS_2_BASE_IDX 2 2971 #define regHUBPREQ1_NOM_PARAMETERS_3 0x0731 2972 #define regHUBPREQ1_NOM_PARAMETERS_3_BASE_IDX 2 2973 #define regHUBPREQ1_NOM_PARAMETERS_4 0x0732 2974 #define regHUBPREQ1_NOM_PARAMETERS_4_BASE_IDX 2 2975 #define regHUBPREQ1_NOM_PARAMETERS_5 0x0733 2976 #define regHUBPREQ1_NOM_PARAMETERS_5_BASE_IDX 2 2977 #define regHUBPREQ1_NOM_PARAMETERS_6 0x0734 2978 #define regHUBPREQ1_NOM_PARAMETERS_6_BASE_IDX 2 2979 #define regHUBPREQ1_NOM_PARAMETERS_7 0x0735 2980 #define regHUBPREQ1_NOM_PARAMETERS_7_BASE_IDX 2 2981 #define regHUBPREQ1_PER_LINE_DELIVERY_PRE 0x0736 2982 #define regHUBPREQ1_PER_LINE_DELIVERY_PRE_BASE_IDX 2 2983 #define regHUBPREQ1_PER_LINE_DELIVERY 0x0737 2984 #define regHUBPREQ1_PER_LINE_DELIVERY_BASE_IDX 2 2985 #define regHUBPREQ1_CURSOR_SETTINGS 0x0738 2986 #define regHUBPREQ1_CURSOR_SETTINGS_BASE_IDX 2 2987 #define regHUBPREQ1_REF_FREQ_TO_PIX_FREQ 0x0739 2988 #define regHUBPREQ1_REF_FREQ_TO_PIX_FREQ_BASE_IDX 2 2989 #define regHUBPREQ1_DST_Y_DELTA_DRQ_LIMIT 0x073a 2990 #define regHUBPREQ1_DST_Y_DELTA_DRQ_LIMIT_BASE_IDX 2 2991 #define regHUBPREQ1_HUBPREQ_MEM_PWR_CTRL 0x073b 2992 #define regHUBPREQ1_HUBPREQ_MEM_PWR_CTRL_BASE_IDX 2 2993 #define regHUBPREQ1_HUBPREQ_MEM_PWR_STATUS 0x073c 2994 #define regHUBPREQ1_HUBPREQ_MEM_PWR_STATUS_BASE_IDX 2 2995 #define regHUBPREQ1_VBLANK_PARAMETERS_5 0x073f 2996 #define regHUBPREQ1_VBLANK_PARAMETERS_5_BASE_IDX 2 2997 #define regHUBPREQ1_VBLANK_PARAMETERS_6 0x0740 2998 #define regHUBPREQ1_VBLANK_PARAMETERS_6_BASE_IDX 2 2999 #define regHUBPREQ1_FLIP_PARAMETERS_3 0x0741 3000 #define regHUBPREQ1_FLIP_PARAMETERS_3_BASE_IDX 2 3001 #define regHUBPREQ1_FLIP_PARAMETERS_4 0x0742 3002 #define regHUBPREQ1_FLIP_PARAMETERS_4_BASE_IDX 2 3003 #define regHUBPREQ1_FLIP_PARAMETERS_5 0x0743 3004 #define regHUBPREQ1_FLIP_PARAMETERS_5_BASE_IDX 2 3005 #define regHUBPREQ1_FLIP_PARAMETERS_6 0x0744 3006 #define regHUBPREQ1_FLIP_PARAMETERS_6_BASE_IDX 2 3007 3008 3009 // addressBlock: dce_dc_dcbubp1_dispdec_hubpret_dispdec 3010 // base address: 0x370 3011 #define regHUBPRET1_HUBPRET_CONTROL 0x0748 3012 #define regHUBPRET1_HUBPRET_CONTROL_BASE_IDX 2 3013 #define regHUBPRET1_HUBPRET_MEM_PWR_CTRL 0x0749 3014 #define regHUBPRET1_HUBPRET_MEM_PWR_CTRL_BASE_IDX 2 3015 #define regHUBPRET1_HUBPRET_MEM_PWR_STATUS 0x074a 3016 #define regHUBPRET1_HUBPRET_MEM_PWR_STATUS_BASE_IDX 2 3017 #define regHUBPRET1_HUBPRET_READ_LINE_CTRL0 0x074b 3018 #define regHUBPRET1_HUBPRET_READ_LINE_CTRL0_BASE_IDX 2 3019 #define regHUBPRET1_HUBPRET_READ_LINE_CTRL1 0x074c 3020 #define regHUBPRET1_HUBPRET_READ_LINE_CTRL1_BASE_IDX 2 3021 #define regHUBPRET1_HUBPRET_READ_LINE0 0x074d 3022 #define regHUBPRET1_HUBPRET_READ_LINE0_BASE_IDX 2 3023 #define regHUBPRET1_HUBPRET_READ_LINE1 0x074e 3024 #define regHUBPRET1_HUBPRET_READ_LINE1_BASE_IDX 2 3025 #define regHUBPRET1_HUBPRET_INTERRUPT 0x074f 3026 #define regHUBPRET1_HUBPRET_INTERRUPT_BASE_IDX 2 3027 #define regHUBPRET1_HUBPRET_READ_LINE_VALUE 0x0750 3028 #define regHUBPRET1_HUBPRET_READ_LINE_VALUE_BASE_IDX 2 3029 #define regHUBPRET1_HUBPRET_READ_LINE_STATUS 0x0751 3030 #define regHUBPRET1_HUBPRET_READ_LINE_STATUS_BASE_IDX 2 3031 3032 3033 // addressBlock: dce_dc_dcbubp1_dispdec_cursor0_dispdec 3034 // base address: 0x370 3035 #define regCURSOR0_1_CURSOR_CONTROL 0x0754 3036 #define regCURSOR0_1_CURSOR_CONTROL_BASE_IDX 2 3037 #define regCURSOR0_1_CURSOR_SURFACE_ADDRESS 0x0755 3038 #define regCURSOR0_1_CURSOR_SURFACE_ADDRESS_BASE_IDX 2 3039 #define regCURSOR0_1_CURSOR_SURFACE_ADDRESS_HIGH 0x0756 3040 #define regCURSOR0_1_CURSOR_SURFACE_ADDRESS_HIGH_BASE_IDX 2 3041 #define regCURSOR0_1_CURSOR_SIZE 0x0757 3042 #define regCURSOR0_1_CURSOR_SIZE_BASE_IDX 2 3043 #define regCURSOR0_1_CURSOR_POSITION 0x0758 3044 #define regCURSOR0_1_CURSOR_POSITION_BASE_IDX 2 3045 #define regCURSOR0_1_CURSOR_HOT_SPOT 0x0759 3046 #define regCURSOR0_1_CURSOR_HOT_SPOT_BASE_IDX 2 3047 #define regCURSOR0_1_CURSOR_STEREO_CONTROL 0x075a 3048 #define regCURSOR0_1_CURSOR_STEREO_CONTROL_BASE_IDX 2 3049 #define regCURSOR0_1_CURSOR_DST_OFFSET 0x075b 3050 #define regCURSOR0_1_CURSOR_DST_OFFSET_BASE_IDX 2 3051 #define regCURSOR0_1_CURSOR_MEM_PWR_CTRL 0x075c 3052 #define regCURSOR0_1_CURSOR_MEM_PWR_CTRL_BASE_IDX 2 3053 #define regCURSOR0_1_CURSOR_MEM_PWR_STATUS 0x075d 3054 #define regCURSOR0_1_CURSOR_MEM_PWR_STATUS_BASE_IDX 2 3055 #define regCURSOR0_1_DMDATA_ADDRESS_HIGH 0x075e 3056 #define regCURSOR0_1_DMDATA_ADDRESS_HIGH_BASE_IDX 2 3057 #define regCURSOR0_1_DMDATA_ADDRESS_LOW 0x075f 3058 #define regCURSOR0_1_DMDATA_ADDRESS_LOW_BASE_IDX 2 3059 #define regCURSOR0_1_DMDATA_CNTL 0x0760 3060 #define regCURSOR0_1_DMDATA_CNTL_BASE_IDX 2 3061 #define regCURSOR0_1_DMDATA_QOS_CNTL 0x0761 3062 #define regCURSOR0_1_DMDATA_QOS_CNTL_BASE_IDX 2 3063 #define regCURSOR0_1_DMDATA_STATUS 0x0762 3064 #define regCURSOR0_1_DMDATA_STATUS_BASE_IDX 2 3065 #define regCURSOR0_1_DMDATA_SW_CNTL 0x0763 3066 #define regCURSOR0_1_DMDATA_SW_CNTL_BASE_IDX 2 3067 #define regCURSOR0_1_DMDATA_SW_DATA 0x0764 3068 #define regCURSOR0_1_DMDATA_SW_DATA_BASE_IDX 2 3069 3070 3071 // addressBlock: dce_dc_dcbubp1_dispdec_hubp_dcperfmon_dc_perfmon_dispdec 3072 // base address: 0x1de4 3073 #define regDC_PERFMON8_PERFCOUNTER_CNTL 0x0779 3074 #define regDC_PERFMON8_PERFCOUNTER_CNTL_BASE_IDX 2 3075 #define regDC_PERFMON8_PERFCOUNTER_CNTL2 0x077a 3076 #define regDC_PERFMON8_PERFCOUNTER_CNTL2_BASE_IDX 2 3077 #define regDC_PERFMON8_PERFCOUNTER_STATE 0x077b 3078 #define regDC_PERFMON8_PERFCOUNTER_STATE_BASE_IDX 2 3079 #define regDC_PERFMON8_PERFMON_CNTL 0x077c 3080 #define regDC_PERFMON8_PERFMON_CNTL_BASE_IDX 2 3081 #define regDC_PERFMON8_PERFMON_CNTL2 0x077d 3082 #define regDC_PERFMON8_PERFMON_CNTL2_BASE_IDX 2 3083 #define regDC_PERFMON8_PERFMON_CVALUE_INT_MISC 0x077e 3084 #define regDC_PERFMON8_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 3085 #define regDC_PERFMON8_PERFMON_CVALUE_LOW 0x077f 3086 #define regDC_PERFMON8_PERFMON_CVALUE_LOW_BASE_IDX 2 3087 #define regDC_PERFMON8_PERFMON_HI 0x0780 3088 #define regDC_PERFMON8_PERFMON_HI_BASE_IDX 2 3089 #define regDC_PERFMON8_PERFMON_LOW 0x0781 3090 #define regDC_PERFMON8_PERFMON_LOW_BASE_IDX 2 3091 3092 3093 // addressBlock: dce_dc_dcbubp2_dispdec_hubp_dispdec 3094 // base address: 0x6e0 3095 #define regHUBP2_DCSURF_SURFACE_CONFIG 0x079d 3096 #define regHUBP2_DCSURF_SURFACE_CONFIG_BASE_IDX 2 3097 #define regHUBP2_DCSURF_ADDR_CONFIG 0x079e 3098 #define regHUBP2_DCSURF_ADDR_CONFIG_BASE_IDX 2 3099 #define regHUBP2_DCSURF_TILING_CONFIG 0x079f 3100 #define regHUBP2_DCSURF_TILING_CONFIG_BASE_IDX 2 3101 #define regHUBP2_DCSURF_PRI_VIEWPORT_START 0x07a1 3102 #define regHUBP2_DCSURF_PRI_VIEWPORT_START_BASE_IDX 2 3103 #define regHUBP2_DCSURF_PRI_VIEWPORT_DIMENSION 0x07a2 3104 #define regHUBP2_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX 2 3105 #define regHUBP2_DCSURF_PRI_VIEWPORT_START_C 0x07a3 3106 #define regHUBP2_DCSURF_PRI_VIEWPORT_START_C_BASE_IDX 2 3107 #define regHUBP2_DCSURF_PRI_VIEWPORT_DIMENSION_C 0x07a4 3108 #define regHUBP2_DCSURF_PRI_VIEWPORT_DIMENSION_C_BASE_IDX 2 3109 #define regHUBP2_DCSURF_SEC_VIEWPORT_START 0x07a5 3110 #define regHUBP2_DCSURF_SEC_VIEWPORT_START_BASE_IDX 2 3111 #define regHUBP2_DCSURF_SEC_VIEWPORT_DIMENSION 0x07a6 3112 #define regHUBP2_DCSURF_SEC_VIEWPORT_DIMENSION_BASE_IDX 2 3113 #define regHUBP2_DCSURF_SEC_VIEWPORT_START_C 0x07a7 3114 #define regHUBP2_DCSURF_SEC_VIEWPORT_START_C_BASE_IDX 2 3115 #define regHUBP2_DCSURF_SEC_VIEWPORT_DIMENSION_C 0x07a8 3116 #define regHUBP2_DCSURF_SEC_VIEWPORT_DIMENSION_C_BASE_IDX 2 3117 #define regHUBP2_DCHUBP_REQ_SIZE_CONFIG 0x07a9 3118 #define regHUBP2_DCHUBP_REQ_SIZE_CONFIG_BASE_IDX 2 3119 #define regHUBP2_DCHUBP_REQ_SIZE_CONFIG_C 0x07aa 3120 #define regHUBP2_DCHUBP_REQ_SIZE_CONFIG_C_BASE_IDX 2 3121 #define regHUBP2_DCHUBP_CNTL 0x07ab 3122 #define regHUBP2_DCHUBP_CNTL_BASE_IDX 2 3123 #define regHUBP2_HUBP_CLK_CNTL 0x07ac 3124 #define regHUBP2_HUBP_CLK_CNTL_BASE_IDX 2 3125 #define regHUBP2_DCHUBP_VMPG_CONFIG 0x07ad 3126 #define regHUBP2_DCHUBP_VMPG_CONFIG_BASE_IDX 2 3127 #define regHUBP2_HUBPREQ_DEBUG_DB 0x07ae 3128 #define regHUBP2_HUBPREQ_DEBUG_DB_BASE_IDX 2 3129 #define regHUBP2_HUBPREQ_DEBUG 0x07af 3130 #define regHUBP2_HUBPREQ_DEBUG_BASE_IDX 2 3131 #define regHUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK 0x07b3 3132 #define regHUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK_BASE_IDX 2 3133 #define regHUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK 0x07b4 3134 #define regHUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK_BASE_IDX 2 3135 3136 3137 // addressBlock: dce_dc_dcbubp2_dispdec_hubpreq_dispdec 3138 // base address: 0x6e0 3139 #define regHUBPREQ2_DCSURF_SURFACE_PITCH 0x07bf 3140 #define regHUBPREQ2_DCSURF_SURFACE_PITCH_BASE_IDX 2 3141 #define regHUBPREQ2_DCSURF_SURFACE_PITCH_C 0x07c0 3142 #define regHUBPREQ2_DCSURF_SURFACE_PITCH_C_BASE_IDX 2 3143 #define regHUBPREQ2_VMID_SETTINGS_0 0x07c1 3144 #define regHUBPREQ2_VMID_SETTINGS_0_BASE_IDX 2 3145 #define regHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS 0x07c2 3146 #define regHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_BASE_IDX 2 3147 #define regHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH 0x07c3 3148 #define regHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2 3149 #define regHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_C 0x07c4 3150 #define regHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_C_BASE_IDX 2 3151 #define regHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C 0x07c5 3152 #define regHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 3153 #define regHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS 0x07c6 3154 #define regHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_BASE_IDX 2 3155 #define regHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH 0x07c7 3156 #define regHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2 3157 #define regHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_C 0x07c8 3158 #define regHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_C_BASE_IDX 2 3159 #define regHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C 0x07c9 3160 #define regHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 3161 #define regHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS 0x07ca 3162 #define regHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_BASE_IDX 2 3163 #define regHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH 0x07cb 3164 #define regHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2 3165 #define regHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C 0x07cc 3166 #define regHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C_BASE_IDX 2 3167 #define regHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C 0x07cd 3168 #define regHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 3169 #define regHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS 0x07ce 3170 #define regHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_BASE_IDX 2 3171 #define regHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH 0x07cf 3172 #define regHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2 3173 #define regHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C 0x07d0 3174 #define regHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C_BASE_IDX 2 3175 #define regHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C 0x07d1 3176 #define regHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 3177 #define regHUBPREQ2_DCSURF_SURFACE_CONTROL 0x07d2 3178 #define regHUBPREQ2_DCSURF_SURFACE_CONTROL_BASE_IDX 2 3179 #define regHUBPREQ2_DCSURF_FLIP_CONTROL 0x07d3 3180 #define regHUBPREQ2_DCSURF_FLIP_CONTROL_BASE_IDX 2 3181 #define regHUBPREQ2_DCSURF_FLIP_CONTROL2 0x07d4 3182 #define regHUBPREQ2_DCSURF_FLIP_CONTROL2_BASE_IDX 2 3183 #define regHUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT 0x07d8 3184 #define regHUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT_BASE_IDX 2 3185 #define regHUBPREQ2_DCSURF_SURFACE_INUSE 0x07d9 3186 #define regHUBPREQ2_DCSURF_SURFACE_INUSE_BASE_IDX 2 3187 #define regHUBPREQ2_DCSURF_SURFACE_INUSE_HIGH 0x07da 3188 #define regHUBPREQ2_DCSURF_SURFACE_INUSE_HIGH_BASE_IDX 2 3189 #define regHUBPREQ2_DCSURF_SURFACE_INUSE_C 0x07db 3190 #define regHUBPREQ2_DCSURF_SURFACE_INUSE_C_BASE_IDX 2 3191 #define regHUBPREQ2_DCSURF_SURFACE_INUSE_HIGH_C 0x07dc 3192 #define regHUBPREQ2_DCSURF_SURFACE_INUSE_HIGH_C_BASE_IDX 2 3193 #define regHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE 0x07dd 3194 #define regHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_BASE_IDX 2 3195 #define regHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH 0x07de 3196 #define regHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_BASE_IDX 2 3197 #define regHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_C 0x07df 3198 #define regHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_C_BASE_IDX 2 3199 #define regHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C 0x07e0 3200 #define regHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C_BASE_IDX 2 3201 #define regHUBPREQ2_DCN_EXPANSION_MODE 0x07e1 3202 #define regHUBPREQ2_DCN_EXPANSION_MODE_BASE_IDX 2 3203 #define regHUBPREQ2_DCN_TTU_QOS_WM 0x07e2 3204 #define regHUBPREQ2_DCN_TTU_QOS_WM_BASE_IDX 2 3205 #define regHUBPREQ2_DCN_GLOBAL_TTU_CNTL 0x07e3 3206 #define regHUBPREQ2_DCN_GLOBAL_TTU_CNTL_BASE_IDX 2 3207 #define regHUBPREQ2_DCN_SURF0_TTU_CNTL0 0x07e4 3208 #define regHUBPREQ2_DCN_SURF0_TTU_CNTL0_BASE_IDX 2 3209 #define regHUBPREQ2_DCN_SURF0_TTU_CNTL1 0x07e5 3210 #define regHUBPREQ2_DCN_SURF0_TTU_CNTL1_BASE_IDX 2 3211 #define regHUBPREQ2_DCN_SURF1_TTU_CNTL0 0x07e6 3212 #define regHUBPREQ2_DCN_SURF1_TTU_CNTL0_BASE_IDX 2 3213 #define regHUBPREQ2_DCN_SURF1_TTU_CNTL1 0x07e7 3214 #define regHUBPREQ2_DCN_SURF1_TTU_CNTL1_BASE_IDX 2 3215 #define regHUBPREQ2_DCN_CUR0_TTU_CNTL0 0x07e8 3216 #define regHUBPREQ2_DCN_CUR0_TTU_CNTL0_BASE_IDX 2 3217 #define regHUBPREQ2_DCN_CUR0_TTU_CNTL1 0x07e9 3218 #define regHUBPREQ2_DCN_CUR0_TTU_CNTL1_BASE_IDX 2 3219 #define regHUBPREQ2_DCN_CUR1_TTU_CNTL0 0x07ea 3220 #define regHUBPREQ2_DCN_CUR1_TTU_CNTL0_BASE_IDX 2 3221 #define regHUBPREQ2_DCN_CUR1_TTU_CNTL1 0x07eb 3222 #define regHUBPREQ2_DCN_CUR1_TTU_CNTL1_BASE_IDX 2 3223 #define regHUBPREQ2_DCN_DMDATA_VM_CNTL 0x07ec 3224 #define regHUBPREQ2_DCN_DMDATA_VM_CNTL_BASE_IDX 2 3225 #define regHUBPREQ2_DCN_VM_SYSTEM_APERTURE_LOW_ADDR 0x07ed 3226 #define regHUBPREQ2_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_BASE_IDX 2 3227 #define regHUBPREQ2_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR 0x07ee 3228 #define regHUBPREQ2_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_BASE_IDX 2 3229 #define regHUBPREQ2_DCN_VM_MX_L1_TLB_CNTL 0x07fb 3230 #define regHUBPREQ2_DCN_VM_MX_L1_TLB_CNTL_BASE_IDX 2 3231 #define regHUBPREQ2_BLANK_OFFSET_0 0x07fc 3232 #define regHUBPREQ2_BLANK_OFFSET_0_BASE_IDX 2 3233 #define regHUBPREQ2_BLANK_OFFSET_1 0x07fd 3234 #define regHUBPREQ2_BLANK_OFFSET_1_BASE_IDX 2 3235 #define regHUBPREQ2_DST_DIMENSIONS 0x07fe 3236 #define regHUBPREQ2_DST_DIMENSIONS_BASE_IDX 2 3237 #define regHUBPREQ2_DST_AFTER_SCALER 0x07ff 3238 #define regHUBPREQ2_DST_AFTER_SCALER_BASE_IDX 2 3239 #define regHUBPREQ2_PREFETCH_SETTINGS 0x0800 3240 #define regHUBPREQ2_PREFETCH_SETTINGS_BASE_IDX 2 3241 #define regHUBPREQ2_PREFETCH_SETTINGS_C 0x0801 3242 #define regHUBPREQ2_PREFETCH_SETTINGS_C_BASE_IDX 2 3243 #define regHUBPREQ2_VBLANK_PARAMETERS_0 0x0802 3244 #define regHUBPREQ2_VBLANK_PARAMETERS_0_BASE_IDX 2 3245 #define regHUBPREQ2_VBLANK_PARAMETERS_1 0x0803 3246 #define regHUBPREQ2_VBLANK_PARAMETERS_1_BASE_IDX 2 3247 #define regHUBPREQ2_VBLANK_PARAMETERS_2 0x0804 3248 #define regHUBPREQ2_VBLANK_PARAMETERS_2_BASE_IDX 2 3249 #define regHUBPREQ2_VBLANK_PARAMETERS_3 0x0805 3250 #define regHUBPREQ2_VBLANK_PARAMETERS_3_BASE_IDX 2 3251 #define regHUBPREQ2_VBLANK_PARAMETERS_4 0x0806 3252 #define regHUBPREQ2_VBLANK_PARAMETERS_4_BASE_IDX 2 3253 #define regHUBPREQ2_FLIP_PARAMETERS_0 0x0807 3254 #define regHUBPREQ2_FLIP_PARAMETERS_0_BASE_IDX 2 3255 #define regHUBPREQ2_FLIP_PARAMETERS_1 0x0808 3256 #define regHUBPREQ2_FLIP_PARAMETERS_1_BASE_IDX 2 3257 #define regHUBPREQ2_FLIP_PARAMETERS_2 0x0809 3258 #define regHUBPREQ2_FLIP_PARAMETERS_2_BASE_IDX 2 3259 #define regHUBPREQ2_NOM_PARAMETERS_0 0x080a 3260 #define regHUBPREQ2_NOM_PARAMETERS_0_BASE_IDX 2 3261 #define regHUBPREQ2_NOM_PARAMETERS_1 0x080b 3262 #define regHUBPREQ2_NOM_PARAMETERS_1_BASE_IDX 2 3263 #define regHUBPREQ2_NOM_PARAMETERS_2 0x080c 3264 #define regHUBPREQ2_NOM_PARAMETERS_2_BASE_IDX 2 3265 #define regHUBPREQ2_NOM_PARAMETERS_3 0x080d 3266 #define regHUBPREQ2_NOM_PARAMETERS_3_BASE_IDX 2 3267 #define regHUBPREQ2_NOM_PARAMETERS_4 0x080e 3268 #define regHUBPREQ2_NOM_PARAMETERS_4_BASE_IDX 2 3269 #define regHUBPREQ2_NOM_PARAMETERS_5 0x080f 3270 #define regHUBPREQ2_NOM_PARAMETERS_5_BASE_IDX 2 3271 #define regHUBPREQ2_NOM_PARAMETERS_6 0x0810 3272 #define regHUBPREQ2_NOM_PARAMETERS_6_BASE_IDX 2 3273 #define regHUBPREQ2_NOM_PARAMETERS_7 0x0811 3274 #define regHUBPREQ2_NOM_PARAMETERS_7_BASE_IDX 2 3275 #define regHUBPREQ2_PER_LINE_DELIVERY_PRE 0x0812 3276 #define regHUBPREQ2_PER_LINE_DELIVERY_PRE_BASE_IDX 2 3277 #define regHUBPREQ2_PER_LINE_DELIVERY 0x0813 3278 #define regHUBPREQ2_PER_LINE_DELIVERY_BASE_IDX 2 3279 #define regHUBPREQ2_CURSOR_SETTINGS 0x0814 3280 #define regHUBPREQ2_CURSOR_SETTINGS_BASE_IDX 2 3281 #define regHUBPREQ2_REF_FREQ_TO_PIX_FREQ 0x0815 3282 #define regHUBPREQ2_REF_FREQ_TO_PIX_FREQ_BASE_IDX 2 3283 #define regHUBPREQ2_DST_Y_DELTA_DRQ_LIMIT 0x0816 3284 #define regHUBPREQ2_DST_Y_DELTA_DRQ_LIMIT_BASE_IDX 2 3285 #define regHUBPREQ2_HUBPREQ_MEM_PWR_CTRL 0x0817 3286 #define regHUBPREQ2_HUBPREQ_MEM_PWR_CTRL_BASE_IDX 2 3287 #define regHUBPREQ2_HUBPREQ_MEM_PWR_STATUS 0x0818 3288 #define regHUBPREQ2_HUBPREQ_MEM_PWR_STATUS_BASE_IDX 2 3289 #define regHUBPREQ2_VBLANK_PARAMETERS_5 0x081b 3290 #define regHUBPREQ2_VBLANK_PARAMETERS_5_BASE_IDX 2 3291 #define regHUBPREQ2_VBLANK_PARAMETERS_6 0x081c 3292 #define regHUBPREQ2_VBLANK_PARAMETERS_6_BASE_IDX 2 3293 #define regHUBPREQ2_FLIP_PARAMETERS_3 0x081d 3294 #define regHUBPREQ2_FLIP_PARAMETERS_3_BASE_IDX 2 3295 #define regHUBPREQ2_FLIP_PARAMETERS_4 0x081e 3296 #define regHUBPREQ2_FLIP_PARAMETERS_4_BASE_IDX 2 3297 #define regHUBPREQ2_FLIP_PARAMETERS_5 0x081f 3298 #define regHUBPREQ2_FLIP_PARAMETERS_5_BASE_IDX 2 3299 #define regHUBPREQ2_FLIP_PARAMETERS_6 0x0820 3300 #define regHUBPREQ2_FLIP_PARAMETERS_6_BASE_IDX 2 3301 3302 3303 // addressBlock: dce_dc_dcbubp2_dispdec_hubpret_dispdec 3304 // base address: 0x6e0 3305 #define regHUBPRET2_HUBPRET_CONTROL 0x0824 3306 #define regHUBPRET2_HUBPRET_CONTROL_BASE_IDX 2 3307 #define regHUBPRET2_HUBPRET_MEM_PWR_CTRL 0x0825 3308 #define regHUBPRET2_HUBPRET_MEM_PWR_CTRL_BASE_IDX 2 3309 #define regHUBPRET2_HUBPRET_MEM_PWR_STATUS 0x0826 3310 #define regHUBPRET2_HUBPRET_MEM_PWR_STATUS_BASE_IDX 2 3311 #define regHUBPRET2_HUBPRET_READ_LINE_CTRL0 0x0827 3312 #define regHUBPRET2_HUBPRET_READ_LINE_CTRL0_BASE_IDX 2 3313 #define regHUBPRET2_HUBPRET_READ_LINE_CTRL1 0x0828 3314 #define regHUBPRET2_HUBPRET_READ_LINE_CTRL1_BASE_IDX 2 3315 #define regHUBPRET2_HUBPRET_READ_LINE0 0x0829 3316 #define regHUBPRET2_HUBPRET_READ_LINE0_BASE_IDX 2 3317 #define regHUBPRET2_HUBPRET_READ_LINE1 0x082a 3318 #define regHUBPRET2_HUBPRET_READ_LINE1_BASE_IDX 2 3319 #define regHUBPRET2_HUBPRET_INTERRUPT 0x082b 3320 #define regHUBPRET2_HUBPRET_INTERRUPT_BASE_IDX 2 3321 #define regHUBPRET2_HUBPRET_READ_LINE_VALUE 0x082c 3322 #define regHUBPRET2_HUBPRET_READ_LINE_VALUE_BASE_IDX 2 3323 #define regHUBPRET2_HUBPRET_READ_LINE_STATUS 0x082d 3324 #define regHUBPRET2_HUBPRET_READ_LINE_STATUS_BASE_IDX 2 3325 3326 3327 // addressBlock: dce_dc_dcbubp2_dispdec_cursor0_dispdec 3328 // base address: 0x6e0 3329 #define regCURSOR0_2_CURSOR_CONTROL 0x0830 3330 #define regCURSOR0_2_CURSOR_CONTROL_BASE_IDX 2 3331 #define regCURSOR0_2_CURSOR_SURFACE_ADDRESS 0x0831 3332 #define regCURSOR0_2_CURSOR_SURFACE_ADDRESS_BASE_IDX 2 3333 #define regCURSOR0_2_CURSOR_SURFACE_ADDRESS_HIGH 0x0832 3334 #define regCURSOR0_2_CURSOR_SURFACE_ADDRESS_HIGH_BASE_IDX 2 3335 #define regCURSOR0_2_CURSOR_SIZE 0x0833 3336 #define regCURSOR0_2_CURSOR_SIZE_BASE_IDX 2 3337 #define regCURSOR0_2_CURSOR_POSITION 0x0834 3338 #define regCURSOR0_2_CURSOR_POSITION_BASE_IDX 2 3339 #define regCURSOR0_2_CURSOR_HOT_SPOT 0x0835 3340 #define regCURSOR0_2_CURSOR_HOT_SPOT_BASE_IDX 2 3341 #define regCURSOR0_2_CURSOR_STEREO_CONTROL 0x0836 3342 #define regCURSOR0_2_CURSOR_STEREO_CONTROL_BASE_IDX 2 3343 #define regCURSOR0_2_CURSOR_DST_OFFSET 0x0837 3344 #define regCURSOR0_2_CURSOR_DST_OFFSET_BASE_IDX 2 3345 #define regCURSOR0_2_CURSOR_MEM_PWR_CTRL 0x0838 3346 #define regCURSOR0_2_CURSOR_MEM_PWR_CTRL_BASE_IDX 2 3347 #define regCURSOR0_2_CURSOR_MEM_PWR_STATUS 0x0839 3348 #define regCURSOR0_2_CURSOR_MEM_PWR_STATUS_BASE_IDX 2 3349 #define regCURSOR0_2_DMDATA_ADDRESS_HIGH 0x083a 3350 #define regCURSOR0_2_DMDATA_ADDRESS_HIGH_BASE_IDX 2 3351 #define regCURSOR0_2_DMDATA_ADDRESS_LOW 0x083b 3352 #define regCURSOR0_2_DMDATA_ADDRESS_LOW_BASE_IDX 2 3353 #define regCURSOR0_2_DMDATA_CNTL 0x083c 3354 #define regCURSOR0_2_DMDATA_CNTL_BASE_IDX 2 3355 #define regCURSOR0_2_DMDATA_QOS_CNTL 0x083d 3356 #define regCURSOR0_2_DMDATA_QOS_CNTL_BASE_IDX 2 3357 #define regCURSOR0_2_DMDATA_STATUS 0x083e 3358 #define regCURSOR0_2_DMDATA_STATUS_BASE_IDX 2 3359 #define regCURSOR0_2_DMDATA_SW_CNTL 0x083f 3360 #define regCURSOR0_2_DMDATA_SW_CNTL_BASE_IDX 2 3361 #define regCURSOR0_2_DMDATA_SW_DATA 0x0840 3362 #define regCURSOR0_2_DMDATA_SW_DATA_BASE_IDX 2 3363 3364 3365 // addressBlock: dce_dc_dcbubp2_dispdec_hubp_dcperfmon_dc_perfmon_dispdec 3366 // base address: 0x2154 3367 #define regDC_PERFMON9_PERFCOUNTER_CNTL 0x0855 3368 #define regDC_PERFMON9_PERFCOUNTER_CNTL_BASE_IDX 2 3369 #define regDC_PERFMON9_PERFCOUNTER_CNTL2 0x0856 3370 #define regDC_PERFMON9_PERFCOUNTER_CNTL2_BASE_IDX 2 3371 #define regDC_PERFMON9_PERFCOUNTER_STATE 0x0857 3372 #define regDC_PERFMON9_PERFCOUNTER_STATE_BASE_IDX 2 3373 #define regDC_PERFMON9_PERFMON_CNTL 0x0858 3374 #define regDC_PERFMON9_PERFMON_CNTL_BASE_IDX 2 3375 #define regDC_PERFMON9_PERFMON_CNTL2 0x0859 3376 #define regDC_PERFMON9_PERFMON_CNTL2_BASE_IDX 2 3377 #define regDC_PERFMON9_PERFMON_CVALUE_INT_MISC 0x085a 3378 #define regDC_PERFMON9_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 3379 #define regDC_PERFMON9_PERFMON_CVALUE_LOW 0x085b 3380 #define regDC_PERFMON9_PERFMON_CVALUE_LOW_BASE_IDX 2 3381 #define regDC_PERFMON9_PERFMON_HI 0x085c 3382 #define regDC_PERFMON9_PERFMON_HI_BASE_IDX 2 3383 #define regDC_PERFMON9_PERFMON_LOW 0x085d 3384 #define regDC_PERFMON9_PERFMON_LOW_BASE_IDX 2 3385 3386 3387 // addressBlock: dce_dc_dcbubp3_dispdec_hubp_dispdec 3388 // base address: 0xa50 3389 #define regHUBP3_DCSURF_SURFACE_CONFIG 0x0879 3390 #define regHUBP3_DCSURF_SURFACE_CONFIG_BASE_IDX 2 3391 #define regHUBP3_DCSURF_ADDR_CONFIG 0x087a 3392 #define regHUBP3_DCSURF_ADDR_CONFIG_BASE_IDX 2 3393 #define regHUBP3_DCSURF_TILING_CONFIG 0x087b 3394 #define regHUBP3_DCSURF_TILING_CONFIG_BASE_IDX 2 3395 #define regHUBP3_DCSURF_PRI_VIEWPORT_START 0x087d 3396 #define regHUBP3_DCSURF_PRI_VIEWPORT_START_BASE_IDX 2 3397 #define regHUBP3_DCSURF_PRI_VIEWPORT_DIMENSION 0x087e 3398 #define regHUBP3_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX 2 3399 #define regHUBP3_DCSURF_PRI_VIEWPORT_START_C 0x087f 3400 #define regHUBP3_DCSURF_PRI_VIEWPORT_START_C_BASE_IDX 2 3401 #define regHUBP3_DCSURF_PRI_VIEWPORT_DIMENSION_C 0x0880 3402 #define regHUBP3_DCSURF_PRI_VIEWPORT_DIMENSION_C_BASE_IDX 2 3403 #define regHUBP3_DCSURF_SEC_VIEWPORT_START 0x0881 3404 #define regHUBP3_DCSURF_SEC_VIEWPORT_START_BASE_IDX 2 3405 #define regHUBP3_DCSURF_SEC_VIEWPORT_DIMENSION 0x0882 3406 #define regHUBP3_DCSURF_SEC_VIEWPORT_DIMENSION_BASE_IDX 2 3407 #define regHUBP3_DCSURF_SEC_VIEWPORT_START_C 0x0883 3408 #define regHUBP3_DCSURF_SEC_VIEWPORT_START_C_BASE_IDX 2 3409 #define regHUBP3_DCSURF_SEC_VIEWPORT_DIMENSION_C 0x0884 3410 #define regHUBP3_DCSURF_SEC_VIEWPORT_DIMENSION_C_BASE_IDX 2 3411 #define regHUBP3_DCHUBP_REQ_SIZE_CONFIG 0x0885 3412 #define regHUBP3_DCHUBP_REQ_SIZE_CONFIG_BASE_IDX 2 3413 #define regHUBP3_DCHUBP_REQ_SIZE_CONFIG_C 0x0886 3414 #define regHUBP3_DCHUBP_REQ_SIZE_CONFIG_C_BASE_IDX 2 3415 #define regHUBP3_DCHUBP_CNTL 0x0887 3416 #define regHUBP3_DCHUBP_CNTL_BASE_IDX 2 3417 #define regHUBP3_HUBP_CLK_CNTL 0x0888 3418 #define regHUBP3_HUBP_CLK_CNTL_BASE_IDX 2 3419 #define regHUBP3_DCHUBP_VMPG_CONFIG 0x0889 3420 #define regHUBP3_DCHUBP_VMPG_CONFIG_BASE_IDX 2 3421 #define regHUBP3_HUBPREQ_DEBUG_DB 0x088a 3422 #define regHUBP3_HUBPREQ_DEBUG_DB_BASE_IDX 2 3423 #define regHUBP3_HUBPREQ_DEBUG 0x088b 3424 #define regHUBP3_HUBPREQ_DEBUG_BASE_IDX 2 3425 #define regHUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK 0x088f 3426 #define regHUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK_BASE_IDX 2 3427 #define regHUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK 0x0890 3428 #define regHUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK_BASE_IDX 2 3429 3430 3431 // addressBlock: dce_dc_dcbubp3_dispdec_hubpreq_dispdec 3432 // base address: 0xa50 3433 #define regHUBPREQ3_DCSURF_SURFACE_PITCH 0x089b 3434 #define regHUBPREQ3_DCSURF_SURFACE_PITCH_BASE_IDX 2 3435 #define regHUBPREQ3_DCSURF_SURFACE_PITCH_C 0x089c 3436 #define regHUBPREQ3_DCSURF_SURFACE_PITCH_C_BASE_IDX 2 3437 #define regHUBPREQ3_VMID_SETTINGS_0 0x089d 3438 #define regHUBPREQ3_VMID_SETTINGS_0_BASE_IDX 2 3439 #define regHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS 0x089e 3440 #define regHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_BASE_IDX 2 3441 #define regHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH 0x089f 3442 #define regHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2 3443 #define regHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_C 0x08a0 3444 #define regHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_C_BASE_IDX 2 3445 #define regHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C 0x08a1 3446 #define regHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 3447 #define regHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS 0x08a2 3448 #define regHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_BASE_IDX 2 3449 #define regHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH 0x08a3 3450 #define regHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2 3451 #define regHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_C 0x08a4 3452 #define regHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_C_BASE_IDX 2 3453 #define regHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C 0x08a5 3454 #define regHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 3455 #define regHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS 0x08a6 3456 #define regHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_BASE_IDX 2 3457 #define regHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH 0x08a7 3458 #define regHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2 3459 #define regHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C 0x08a8 3460 #define regHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C_BASE_IDX 2 3461 #define regHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C 0x08a9 3462 #define regHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 3463 #define regHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS 0x08aa 3464 #define regHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_BASE_IDX 2 3465 #define regHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH 0x08ab 3466 #define regHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2 3467 #define regHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C 0x08ac 3468 #define regHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C_BASE_IDX 2 3469 #define regHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C 0x08ad 3470 #define regHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 3471 #define regHUBPREQ3_DCSURF_SURFACE_CONTROL 0x08ae 3472 #define regHUBPREQ3_DCSURF_SURFACE_CONTROL_BASE_IDX 2 3473 #define regHUBPREQ3_DCSURF_FLIP_CONTROL 0x08af 3474 #define regHUBPREQ3_DCSURF_FLIP_CONTROL_BASE_IDX 2 3475 #define regHUBPREQ3_DCSURF_FLIP_CONTROL2 0x08b0 3476 #define regHUBPREQ3_DCSURF_FLIP_CONTROL2_BASE_IDX 2 3477 #define regHUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT 0x08b4 3478 #define regHUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT_BASE_IDX 2 3479 #define regHUBPREQ3_DCSURF_SURFACE_INUSE 0x08b5 3480 #define regHUBPREQ3_DCSURF_SURFACE_INUSE_BASE_IDX 2 3481 #define regHUBPREQ3_DCSURF_SURFACE_INUSE_HIGH 0x08b6 3482 #define regHUBPREQ3_DCSURF_SURFACE_INUSE_HIGH_BASE_IDX 2 3483 #define regHUBPREQ3_DCSURF_SURFACE_INUSE_C 0x08b7 3484 #define regHUBPREQ3_DCSURF_SURFACE_INUSE_C_BASE_IDX 2 3485 #define regHUBPREQ3_DCSURF_SURFACE_INUSE_HIGH_C 0x08b8 3486 #define regHUBPREQ3_DCSURF_SURFACE_INUSE_HIGH_C_BASE_IDX 2 3487 #define regHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE 0x08b9 3488 #define regHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_BASE_IDX 2 3489 #define regHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH 0x08ba 3490 #define regHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_BASE_IDX 2 3491 #define regHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_C 0x08bb 3492 #define regHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_C_BASE_IDX 2 3493 #define regHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C 0x08bc 3494 #define regHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C_BASE_IDX 2 3495 #define regHUBPREQ3_DCN_EXPANSION_MODE 0x08bd 3496 #define regHUBPREQ3_DCN_EXPANSION_MODE_BASE_IDX 2 3497 #define regHUBPREQ3_DCN_TTU_QOS_WM 0x08be 3498 #define regHUBPREQ3_DCN_TTU_QOS_WM_BASE_IDX 2 3499 #define regHUBPREQ3_DCN_GLOBAL_TTU_CNTL 0x08bf 3500 #define regHUBPREQ3_DCN_GLOBAL_TTU_CNTL_BASE_IDX 2 3501 #define regHUBPREQ3_DCN_SURF0_TTU_CNTL0 0x08c0 3502 #define regHUBPREQ3_DCN_SURF0_TTU_CNTL0_BASE_IDX 2 3503 #define regHUBPREQ3_DCN_SURF0_TTU_CNTL1 0x08c1 3504 #define regHUBPREQ3_DCN_SURF0_TTU_CNTL1_BASE_IDX 2 3505 #define regHUBPREQ3_DCN_SURF1_TTU_CNTL0 0x08c2 3506 #define regHUBPREQ3_DCN_SURF1_TTU_CNTL0_BASE_IDX 2 3507 #define regHUBPREQ3_DCN_SURF1_TTU_CNTL1 0x08c3 3508 #define regHUBPREQ3_DCN_SURF1_TTU_CNTL1_BASE_IDX 2 3509 #define regHUBPREQ3_DCN_CUR0_TTU_CNTL0 0x08c4 3510 #define regHUBPREQ3_DCN_CUR0_TTU_CNTL0_BASE_IDX 2 3511 #define regHUBPREQ3_DCN_CUR0_TTU_CNTL1 0x08c5 3512 #define regHUBPREQ3_DCN_CUR0_TTU_CNTL1_BASE_IDX 2 3513 #define regHUBPREQ3_DCN_CUR1_TTU_CNTL0 0x08c6 3514 #define regHUBPREQ3_DCN_CUR1_TTU_CNTL0_BASE_IDX 2 3515 #define regHUBPREQ3_DCN_CUR1_TTU_CNTL1 0x08c7 3516 #define regHUBPREQ3_DCN_CUR1_TTU_CNTL1_BASE_IDX 2 3517 #define regHUBPREQ3_DCN_DMDATA_VM_CNTL 0x08c8 3518 #define regHUBPREQ3_DCN_DMDATA_VM_CNTL_BASE_IDX 2 3519 #define regHUBPREQ3_DCN_VM_SYSTEM_APERTURE_LOW_ADDR 0x08c9 3520 #define regHUBPREQ3_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_BASE_IDX 2 3521 #define regHUBPREQ3_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR 0x08ca 3522 #define regHUBPREQ3_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_BASE_IDX 2 3523 #define regHUBPREQ3_DCN_VM_MX_L1_TLB_CNTL 0x08d7 3524 #define regHUBPREQ3_DCN_VM_MX_L1_TLB_CNTL_BASE_IDX 2 3525 #define regHUBPREQ3_BLANK_OFFSET_0 0x08d8 3526 #define regHUBPREQ3_BLANK_OFFSET_0_BASE_IDX 2 3527 #define regHUBPREQ3_BLANK_OFFSET_1 0x08d9 3528 #define regHUBPREQ3_BLANK_OFFSET_1_BASE_IDX 2 3529 #define regHUBPREQ3_DST_DIMENSIONS 0x08da 3530 #define regHUBPREQ3_DST_DIMENSIONS_BASE_IDX 2 3531 #define regHUBPREQ3_DST_AFTER_SCALER 0x08db 3532 #define regHUBPREQ3_DST_AFTER_SCALER_BASE_IDX 2 3533 #define regHUBPREQ3_PREFETCH_SETTINGS 0x08dc 3534 #define regHUBPREQ3_PREFETCH_SETTINGS_BASE_IDX 2 3535 #define regHUBPREQ3_PREFETCH_SETTINGS_C 0x08dd 3536 #define regHUBPREQ3_PREFETCH_SETTINGS_C_BASE_IDX 2 3537 #define regHUBPREQ3_VBLANK_PARAMETERS_0 0x08de 3538 #define regHUBPREQ3_VBLANK_PARAMETERS_0_BASE_IDX 2 3539 #define regHUBPREQ3_VBLANK_PARAMETERS_1 0x08df 3540 #define regHUBPREQ3_VBLANK_PARAMETERS_1_BASE_IDX 2 3541 #define regHUBPREQ3_VBLANK_PARAMETERS_2 0x08e0 3542 #define regHUBPREQ3_VBLANK_PARAMETERS_2_BASE_IDX 2 3543 #define regHUBPREQ3_VBLANK_PARAMETERS_3 0x08e1 3544 #define regHUBPREQ3_VBLANK_PARAMETERS_3_BASE_IDX 2 3545 #define regHUBPREQ3_VBLANK_PARAMETERS_4 0x08e2 3546 #define regHUBPREQ3_VBLANK_PARAMETERS_4_BASE_IDX 2 3547 #define regHUBPREQ3_FLIP_PARAMETERS_0 0x08e3 3548 #define regHUBPREQ3_FLIP_PARAMETERS_0_BASE_IDX 2 3549 #define regHUBPREQ3_FLIP_PARAMETERS_1 0x08e4 3550 #define regHUBPREQ3_FLIP_PARAMETERS_1_BASE_IDX 2 3551 #define regHUBPREQ3_FLIP_PARAMETERS_2 0x08e5 3552 #define regHUBPREQ3_FLIP_PARAMETERS_2_BASE_IDX 2 3553 #define regHUBPREQ3_NOM_PARAMETERS_0 0x08e6 3554 #define regHUBPREQ3_NOM_PARAMETERS_0_BASE_IDX 2 3555 #define regHUBPREQ3_NOM_PARAMETERS_1 0x08e7 3556 #define regHUBPREQ3_NOM_PARAMETERS_1_BASE_IDX 2 3557 #define regHUBPREQ3_NOM_PARAMETERS_2 0x08e8 3558 #define regHUBPREQ3_NOM_PARAMETERS_2_BASE_IDX 2 3559 #define regHUBPREQ3_NOM_PARAMETERS_3 0x08e9 3560 #define regHUBPREQ3_NOM_PARAMETERS_3_BASE_IDX 2 3561 #define regHUBPREQ3_NOM_PARAMETERS_4 0x08ea 3562 #define regHUBPREQ3_NOM_PARAMETERS_4_BASE_IDX 2 3563 #define regHUBPREQ3_NOM_PARAMETERS_5 0x08eb 3564 #define regHUBPREQ3_NOM_PARAMETERS_5_BASE_IDX 2 3565 #define regHUBPREQ3_NOM_PARAMETERS_6 0x08ec 3566 #define regHUBPREQ3_NOM_PARAMETERS_6_BASE_IDX 2 3567 #define regHUBPREQ3_NOM_PARAMETERS_7 0x08ed 3568 #define regHUBPREQ3_NOM_PARAMETERS_7_BASE_IDX 2 3569 #define regHUBPREQ3_PER_LINE_DELIVERY_PRE 0x08ee 3570 #define regHUBPREQ3_PER_LINE_DELIVERY_PRE_BASE_IDX 2 3571 #define regHUBPREQ3_PER_LINE_DELIVERY 0x08ef 3572 #define regHUBPREQ3_PER_LINE_DELIVERY_BASE_IDX 2 3573 #define regHUBPREQ3_CURSOR_SETTINGS 0x08f0 3574 #define regHUBPREQ3_CURSOR_SETTINGS_BASE_IDX 2 3575 #define regHUBPREQ3_REF_FREQ_TO_PIX_FREQ 0x08f1 3576 #define regHUBPREQ3_REF_FREQ_TO_PIX_FREQ_BASE_IDX 2 3577 #define regHUBPREQ3_DST_Y_DELTA_DRQ_LIMIT 0x08f2 3578 #define regHUBPREQ3_DST_Y_DELTA_DRQ_LIMIT_BASE_IDX 2 3579 #define regHUBPREQ3_HUBPREQ_MEM_PWR_CTRL 0x08f3 3580 #define regHUBPREQ3_HUBPREQ_MEM_PWR_CTRL_BASE_IDX 2 3581 #define regHUBPREQ3_HUBPREQ_MEM_PWR_STATUS 0x08f4 3582 #define regHUBPREQ3_HUBPREQ_MEM_PWR_STATUS_BASE_IDX 2 3583 #define regHUBPREQ3_VBLANK_PARAMETERS_5 0x08f7 3584 #define regHUBPREQ3_VBLANK_PARAMETERS_5_BASE_IDX 2 3585 #define regHUBPREQ3_VBLANK_PARAMETERS_6 0x08f8 3586 #define regHUBPREQ3_VBLANK_PARAMETERS_6_BASE_IDX 2 3587 #define regHUBPREQ3_FLIP_PARAMETERS_3 0x08f9 3588 #define regHUBPREQ3_FLIP_PARAMETERS_3_BASE_IDX 2 3589 #define regHUBPREQ3_FLIP_PARAMETERS_4 0x08fa 3590 #define regHUBPREQ3_FLIP_PARAMETERS_4_BASE_IDX 2 3591 #define regHUBPREQ3_FLIP_PARAMETERS_5 0x08fb 3592 #define regHUBPREQ3_FLIP_PARAMETERS_5_BASE_IDX 2 3593 #define regHUBPREQ3_FLIP_PARAMETERS_6 0x08fc 3594 #define regHUBPREQ3_FLIP_PARAMETERS_6_BASE_IDX 2 3595 3596 3597 // addressBlock: dce_dc_dcbubp3_dispdec_hubpret_dispdec 3598 // base address: 0xa50 3599 #define regHUBPRET3_HUBPRET_CONTROL 0x0900 3600 #define regHUBPRET3_HUBPRET_CONTROL_BASE_IDX 2 3601 #define regHUBPRET3_HUBPRET_MEM_PWR_CTRL 0x0901 3602 #define regHUBPRET3_HUBPRET_MEM_PWR_CTRL_BASE_IDX 2 3603 #define regHUBPRET3_HUBPRET_MEM_PWR_STATUS 0x0902 3604 #define regHUBPRET3_HUBPRET_MEM_PWR_STATUS_BASE_IDX 2 3605 #define regHUBPRET3_HUBPRET_READ_LINE_CTRL0 0x0903 3606 #define regHUBPRET3_HUBPRET_READ_LINE_CTRL0_BASE_IDX 2 3607 #define regHUBPRET3_HUBPRET_READ_LINE_CTRL1 0x0904 3608 #define regHUBPRET3_HUBPRET_READ_LINE_CTRL1_BASE_IDX 2 3609 #define regHUBPRET3_HUBPRET_READ_LINE0 0x0905 3610 #define regHUBPRET3_HUBPRET_READ_LINE0_BASE_IDX 2 3611 #define regHUBPRET3_HUBPRET_READ_LINE1 0x0906 3612 #define regHUBPRET3_HUBPRET_READ_LINE1_BASE_IDX 2 3613 #define regHUBPRET3_HUBPRET_INTERRUPT 0x0907 3614 #define regHUBPRET3_HUBPRET_INTERRUPT_BASE_IDX 2 3615 #define regHUBPRET3_HUBPRET_READ_LINE_VALUE 0x0908 3616 #define regHUBPRET3_HUBPRET_READ_LINE_VALUE_BASE_IDX 2 3617 #define regHUBPRET3_HUBPRET_READ_LINE_STATUS 0x0909 3618 #define regHUBPRET3_HUBPRET_READ_LINE_STATUS_BASE_IDX 2 3619 3620 3621 // addressBlock: dce_dc_dcbubp3_dispdec_cursor0_dispdec 3622 // base address: 0xa50 3623 #define regCURSOR0_3_CURSOR_CONTROL 0x090c 3624 #define regCURSOR0_3_CURSOR_CONTROL_BASE_IDX 2 3625 #define regCURSOR0_3_CURSOR_SURFACE_ADDRESS 0x090d 3626 #define regCURSOR0_3_CURSOR_SURFACE_ADDRESS_BASE_IDX 2 3627 #define regCURSOR0_3_CURSOR_SURFACE_ADDRESS_HIGH 0x090e 3628 #define regCURSOR0_3_CURSOR_SURFACE_ADDRESS_HIGH_BASE_IDX 2 3629 #define regCURSOR0_3_CURSOR_SIZE 0x090f 3630 #define regCURSOR0_3_CURSOR_SIZE_BASE_IDX 2 3631 #define regCURSOR0_3_CURSOR_POSITION 0x0910 3632 #define regCURSOR0_3_CURSOR_POSITION_BASE_IDX 2 3633 #define regCURSOR0_3_CURSOR_HOT_SPOT 0x0911 3634 #define regCURSOR0_3_CURSOR_HOT_SPOT_BASE_IDX 2 3635 #define regCURSOR0_3_CURSOR_STEREO_CONTROL 0x0912 3636 #define regCURSOR0_3_CURSOR_STEREO_CONTROL_BASE_IDX 2 3637 #define regCURSOR0_3_CURSOR_DST_OFFSET 0x0913 3638 #define regCURSOR0_3_CURSOR_DST_OFFSET_BASE_IDX 2 3639 #define regCURSOR0_3_CURSOR_MEM_PWR_CTRL 0x0914 3640 #define regCURSOR0_3_CURSOR_MEM_PWR_CTRL_BASE_IDX 2 3641 #define regCURSOR0_3_CURSOR_MEM_PWR_STATUS 0x0915 3642 #define regCURSOR0_3_CURSOR_MEM_PWR_STATUS_BASE_IDX 2 3643 #define regCURSOR0_3_DMDATA_ADDRESS_HIGH 0x0916 3644 #define regCURSOR0_3_DMDATA_ADDRESS_HIGH_BASE_IDX 2 3645 #define regCURSOR0_3_DMDATA_ADDRESS_LOW 0x0917 3646 #define regCURSOR0_3_DMDATA_ADDRESS_LOW_BASE_IDX 2 3647 #define regCURSOR0_3_DMDATA_CNTL 0x0918 3648 #define regCURSOR0_3_DMDATA_CNTL_BASE_IDX 2 3649 #define regCURSOR0_3_DMDATA_QOS_CNTL 0x0919 3650 #define regCURSOR0_3_DMDATA_QOS_CNTL_BASE_IDX 2 3651 #define regCURSOR0_3_DMDATA_STATUS 0x091a 3652 #define regCURSOR0_3_DMDATA_STATUS_BASE_IDX 2 3653 #define regCURSOR0_3_DMDATA_SW_CNTL 0x091b 3654 #define regCURSOR0_3_DMDATA_SW_CNTL_BASE_IDX 2 3655 #define regCURSOR0_3_DMDATA_SW_DATA 0x091c 3656 #define regCURSOR0_3_DMDATA_SW_DATA_BASE_IDX 2 3657 3658 3659 // addressBlock: dce_dc_dcbubp3_dispdec_hubp_dcperfmon_dc_perfmon_dispdec 3660 // base address: 0x24c4 3661 #define regDC_PERFMON10_PERFCOUNTER_CNTL 0x0931 3662 #define regDC_PERFMON10_PERFCOUNTER_CNTL_BASE_IDX 2 3663 #define regDC_PERFMON10_PERFCOUNTER_CNTL2 0x0932 3664 #define regDC_PERFMON10_PERFCOUNTER_CNTL2_BASE_IDX 2 3665 #define regDC_PERFMON10_PERFCOUNTER_STATE 0x0933 3666 #define regDC_PERFMON10_PERFCOUNTER_STATE_BASE_IDX 2 3667 #define regDC_PERFMON10_PERFMON_CNTL 0x0934 3668 #define regDC_PERFMON10_PERFMON_CNTL_BASE_IDX 2 3669 #define regDC_PERFMON10_PERFMON_CNTL2 0x0935 3670 #define regDC_PERFMON10_PERFMON_CNTL2_BASE_IDX 2 3671 #define regDC_PERFMON10_PERFMON_CVALUE_INT_MISC 0x0936 3672 #define regDC_PERFMON10_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 3673 #define regDC_PERFMON10_PERFMON_CVALUE_LOW 0x0937 3674 #define regDC_PERFMON10_PERFMON_CVALUE_LOW_BASE_IDX 2 3675 #define regDC_PERFMON10_PERFMON_HI 0x0938 3676 #define regDC_PERFMON10_PERFMON_HI_BASE_IDX 2 3677 #define regDC_PERFMON10_PERFMON_LOW 0x0939 3678 #define regDC_PERFMON10_PERFMON_LOW_BASE_IDX 2 3679 3680 3681 // addressBlock: dce_dc_dpp0_dispdec_cnvc_cfg_dispdec 3682 // base address: 0x0 3683 #define regCNVC_CFG0_CNVC_SURFACE_PIXEL_FORMAT 0x0ccf 3684 #define regCNVC_CFG0_CNVC_SURFACE_PIXEL_FORMAT_BASE_IDX 2 3685 #define regCNVC_CFG0_FORMAT_CONTROL 0x0cd0 3686 #define regCNVC_CFG0_FORMAT_CONTROL_BASE_IDX 2 3687 #define regCNVC_CFG0_FCNV_FP_BIAS_R 0x0cd1 3688 #define regCNVC_CFG0_FCNV_FP_BIAS_R_BASE_IDX 2 3689 #define regCNVC_CFG0_FCNV_FP_BIAS_G 0x0cd2 3690 #define regCNVC_CFG0_FCNV_FP_BIAS_G_BASE_IDX 2 3691 #define regCNVC_CFG0_FCNV_FP_BIAS_B 0x0cd3 3692 #define regCNVC_CFG0_FCNV_FP_BIAS_B_BASE_IDX 2 3693 #define regCNVC_CFG0_FCNV_FP_SCALE_R 0x0cd4 3694 #define regCNVC_CFG0_FCNV_FP_SCALE_R_BASE_IDX 2 3695 #define regCNVC_CFG0_FCNV_FP_SCALE_G 0x0cd5 3696 #define regCNVC_CFG0_FCNV_FP_SCALE_G_BASE_IDX 2 3697 #define regCNVC_CFG0_FCNV_FP_SCALE_B 0x0cd6 3698 #define regCNVC_CFG0_FCNV_FP_SCALE_B_BASE_IDX 2 3699 #define regCNVC_CFG0_COLOR_KEYER_CONTROL 0x0cd7 3700 #define regCNVC_CFG0_COLOR_KEYER_CONTROL_BASE_IDX 2 3701 #define regCNVC_CFG0_COLOR_KEYER_ALPHA 0x0cd8 3702 #define regCNVC_CFG0_COLOR_KEYER_ALPHA_BASE_IDX 2 3703 #define regCNVC_CFG0_COLOR_KEYER_RED 0x0cd9 3704 #define regCNVC_CFG0_COLOR_KEYER_RED_BASE_IDX 2 3705 #define regCNVC_CFG0_COLOR_KEYER_GREEN 0x0cda 3706 #define regCNVC_CFG0_COLOR_KEYER_GREEN_BASE_IDX 2 3707 #define regCNVC_CFG0_COLOR_KEYER_BLUE 0x0cdb 3708 #define regCNVC_CFG0_COLOR_KEYER_BLUE_BASE_IDX 2 3709 #define regCNVC_CFG0_ALPHA_2BIT_LUT 0x0cdd 3710 #define regCNVC_CFG0_ALPHA_2BIT_LUT_BASE_IDX 2 3711 #define regCNVC_CFG0_PRE_DEALPHA 0x0cde 3712 #define regCNVC_CFG0_PRE_DEALPHA_BASE_IDX 2 3713 #define regCNVC_CFG0_PRE_CSC_MODE 0x0cdf 3714 #define regCNVC_CFG0_PRE_CSC_MODE_BASE_IDX 2 3715 #define regCNVC_CFG0_PRE_CSC_C11_C12 0x0ce0 3716 #define regCNVC_CFG0_PRE_CSC_C11_C12_BASE_IDX 2 3717 #define regCNVC_CFG0_PRE_CSC_C13_C14 0x0ce1 3718 #define regCNVC_CFG0_PRE_CSC_C13_C14_BASE_IDX 2 3719 #define regCNVC_CFG0_PRE_CSC_C21_C22 0x0ce2 3720 #define regCNVC_CFG0_PRE_CSC_C21_C22_BASE_IDX 2 3721 #define regCNVC_CFG0_PRE_CSC_C23_C24 0x0ce3 3722 #define regCNVC_CFG0_PRE_CSC_C23_C24_BASE_IDX 2 3723 #define regCNVC_CFG0_PRE_CSC_C31_C32 0x0ce4 3724 #define regCNVC_CFG0_PRE_CSC_C31_C32_BASE_IDX 2 3725 #define regCNVC_CFG0_PRE_CSC_C33_C34 0x0ce5 3726 #define regCNVC_CFG0_PRE_CSC_C33_C34_BASE_IDX 2 3727 #define regCNVC_CFG0_PRE_CSC_B_C11_C12 0x0ce6 3728 #define regCNVC_CFG0_PRE_CSC_B_C11_C12_BASE_IDX 2 3729 #define regCNVC_CFG0_PRE_CSC_B_C13_C14 0x0ce7 3730 #define regCNVC_CFG0_PRE_CSC_B_C13_C14_BASE_IDX 2 3731 #define regCNVC_CFG0_PRE_CSC_B_C21_C22 0x0ce8 3732 #define regCNVC_CFG0_PRE_CSC_B_C21_C22_BASE_IDX 2 3733 #define regCNVC_CFG0_PRE_CSC_B_C23_C24 0x0ce9 3734 #define regCNVC_CFG0_PRE_CSC_B_C23_C24_BASE_IDX 2 3735 #define regCNVC_CFG0_PRE_CSC_B_C31_C32 0x0cea 3736 #define regCNVC_CFG0_PRE_CSC_B_C31_C32_BASE_IDX 2 3737 #define regCNVC_CFG0_PRE_CSC_B_C33_C34 0x0ceb 3738 #define regCNVC_CFG0_PRE_CSC_B_C33_C34_BASE_IDX 2 3739 #define regCNVC_CFG0_CNVC_COEF_FORMAT 0x0cec 3740 #define regCNVC_CFG0_CNVC_COEF_FORMAT_BASE_IDX 2 3741 #define regCNVC_CFG0_PRE_DEGAM 0x0ced 3742 #define regCNVC_CFG0_PRE_DEGAM_BASE_IDX 2 3743 #define regCNVC_CFG0_PRE_REALPHA 0x0cee 3744 #define regCNVC_CFG0_PRE_REALPHA_BASE_IDX 2 3745 3746 3747 // addressBlock: dce_dc_dpp0_dispdec_cnvc_cur_dispdec 3748 // base address: 0x0 3749 #define regCNVC_CUR0_CURSOR0_CONTROL 0x0cf1 3750 #define regCNVC_CUR0_CURSOR0_CONTROL_BASE_IDX 2 3751 #define regCNVC_CUR0_CURSOR0_COLOR0 0x0cf2 3752 #define regCNVC_CUR0_CURSOR0_COLOR0_BASE_IDX 2 3753 #define regCNVC_CUR0_CURSOR0_COLOR1 0x0cf3 3754 #define regCNVC_CUR0_CURSOR0_COLOR1_BASE_IDX 2 3755 #define regCNVC_CUR0_CURSOR0_FP_SCALE_BIAS 0x0cf4 3756 #define regCNVC_CUR0_CURSOR0_FP_SCALE_BIAS_BASE_IDX 2 3757 3758 3759 // addressBlock: dce_dc_dpp0_dispdec_dscl_dispdec 3760 // base address: 0x0 3761 #define regDSCL0_SCL_COEF_RAM_TAP_SELECT 0x0cf9 3762 #define regDSCL0_SCL_COEF_RAM_TAP_SELECT_BASE_IDX 2 3763 #define regDSCL0_SCL_COEF_RAM_TAP_DATA 0x0cfa 3764 #define regDSCL0_SCL_COEF_RAM_TAP_DATA_BASE_IDX 2 3765 #define regDSCL0_SCL_MODE 0x0cfb 3766 #define regDSCL0_SCL_MODE_BASE_IDX 2 3767 #define regDSCL0_SCL_TAP_CONTROL 0x0cfc 3768 #define regDSCL0_SCL_TAP_CONTROL_BASE_IDX 2 3769 #define regDSCL0_DSCL_CONTROL 0x0cfd 3770 #define regDSCL0_DSCL_CONTROL_BASE_IDX 2 3771 #define regDSCL0_DSCL_2TAP_CONTROL 0x0cfe 3772 #define regDSCL0_DSCL_2TAP_CONTROL_BASE_IDX 2 3773 #define regDSCL0_SCL_MANUAL_REPLICATE_CONTROL 0x0cff 3774 #define regDSCL0_SCL_MANUAL_REPLICATE_CONTROL_BASE_IDX 2 3775 #define regDSCL0_SCL_HORZ_FILTER_SCALE_RATIO 0x0d00 3776 #define regDSCL0_SCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX 2 3777 #define regDSCL0_SCL_HORZ_FILTER_INIT 0x0d01 3778 #define regDSCL0_SCL_HORZ_FILTER_INIT_BASE_IDX 2 3779 #define regDSCL0_SCL_HORZ_FILTER_SCALE_RATIO_C 0x0d02 3780 #define regDSCL0_SCL_HORZ_FILTER_SCALE_RATIO_C_BASE_IDX 2 3781 #define regDSCL0_SCL_HORZ_FILTER_INIT_C 0x0d03 3782 #define regDSCL0_SCL_HORZ_FILTER_INIT_C_BASE_IDX 2 3783 #define regDSCL0_SCL_VERT_FILTER_SCALE_RATIO 0x0d04 3784 #define regDSCL0_SCL_VERT_FILTER_SCALE_RATIO_BASE_IDX 2 3785 #define regDSCL0_SCL_VERT_FILTER_INIT 0x0d05 3786 #define regDSCL0_SCL_VERT_FILTER_INIT_BASE_IDX 2 3787 #define regDSCL0_SCL_VERT_FILTER_INIT_BOT 0x0d06 3788 #define regDSCL0_SCL_VERT_FILTER_INIT_BOT_BASE_IDX 2 3789 #define regDSCL0_SCL_VERT_FILTER_SCALE_RATIO_C 0x0d07 3790 #define regDSCL0_SCL_VERT_FILTER_SCALE_RATIO_C_BASE_IDX 2 3791 #define regDSCL0_SCL_VERT_FILTER_INIT_C 0x0d08 3792 #define regDSCL0_SCL_VERT_FILTER_INIT_C_BASE_IDX 2 3793 #define regDSCL0_SCL_VERT_FILTER_INIT_BOT_C 0x0d09 3794 #define regDSCL0_SCL_VERT_FILTER_INIT_BOT_C_BASE_IDX 2 3795 #define regDSCL0_SCL_BLACK_COLOR 0x0d0a 3796 #define regDSCL0_SCL_BLACK_COLOR_BASE_IDX 2 3797 #define regDSCL0_DSCL_UPDATE 0x0d0b 3798 #define regDSCL0_DSCL_UPDATE_BASE_IDX 2 3799 #define regDSCL0_DSCL_AUTOCAL 0x0d0c 3800 #define regDSCL0_DSCL_AUTOCAL_BASE_IDX 2 3801 #define regDSCL0_DSCL_EXT_OVERSCAN_LEFT_RIGHT 0x0d0d 3802 #define regDSCL0_DSCL_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX 2 3803 #define regDSCL0_DSCL_EXT_OVERSCAN_TOP_BOTTOM 0x0d0e 3804 #define regDSCL0_DSCL_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX 2 3805 #define regDSCL0_OTG_H_BLANK 0x0d0f 3806 #define regDSCL0_OTG_H_BLANK_BASE_IDX 2 3807 #define regDSCL0_OTG_V_BLANK 0x0d10 3808 #define regDSCL0_OTG_V_BLANK_BASE_IDX 2 3809 #define regDSCL0_RECOUT_START 0x0d11 3810 #define regDSCL0_RECOUT_START_BASE_IDX 2 3811 #define regDSCL0_RECOUT_SIZE 0x0d12 3812 #define regDSCL0_RECOUT_SIZE_BASE_IDX 2 3813 #define regDSCL0_MPC_SIZE 0x0d13 3814 #define regDSCL0_MPC_SIZE_BASE_IDX 2 3815 #define regDSCL0_LB_DATA_FORMAT 0x0d14 3816 #define regDSCL0_LB_DATA_FORMAT_BASE_IDX 2 3817 #define regDSCL0_LB_MEMORY_CTRL 0x0d15 3818 #define regDSCL0_LB_MEMORY_CTRL_BASE_IDX 2 3819 #define regDSCL0_LB_V_COUNTER 0x0d16 3820 #define regDSCL0_LB_V_COUNTER_BASE_IDX 2 3821 #define regDSCL0_DSCL_MEM_PWR_CTRL 0x0d17 3822 #define regDSCL0_DSCL_MEM_PWR_CTRL_BASE_IDX 2 3823 #define regDSCL0_DSCL_MEM_PWR_STATUS 0x0d18 3824 #define regDSCL0_DSCL_MEM_PWR_STATUS_BASE_IDX 2 3825 #define regDSCL0_OBUF_CONTROL 0x0d19 3826 #define regDSCL0_OBUF_CONTROL_BASE_IDX 2 3827 #define regDSCL0_OBUF_MEM_PWR_CTRL 0x0d1a 3828 #define regDSCL0_OBUF_MEM_PWR_CTRL_BASE_IDX 2 3829 3830 3831 // addressBlock: dce_dc_dpp0_dispdec_cm_dispdec 3832 // base address: 0x0 3833 #define regCM0_CM_CONTROL 0x0d20 3834 #define regCM0_CM_CONTROL_BASE_IDX 2 3835 #define regCM0_CM_POST_CSC_CONTROL 0x0d21 3836 #define regCM0_CM_POST_CSC_CONTROL_BASE_IDX 2 3837 #define regCM0_CM_POST_CSC_C11_C12 0x0d22 3838 #define regCM0_CM_POST_CSC_C11_C12_BASE_IDX 2 3839 #define regCM0_CM_POST_CSC_C13_C14 0x0d23 3840 #define regCM0_CM_POST_CSC_C13_C14_BASE_IDX 2 3841 #define regCM0_CM_POST_CSC_C21_C22 0x0d24 3842 #define regCM0_CM_POST_CSC_C21_C22_BASE_IDX 2 3843 #define regCM0_CM_POST_CSC_C23_C24 0x0d25 3844 #define regCM0_CM_POST_CSC_C23_C24_BASE_IDX 2 3845 #define regCM0_CM_POST_CSC_C31_C32 0x0d26 3846 #define regCM0_CM_POST_CSC_C31_C32_BASE_IDX 2 3847 #define regCM0_CM_POST_CSC_C33_C34 0x0d27 3848 #define regCM0_CM_POST_CSC_C33_C34_BASE_IDX 2 3849 #define regCM0_CM_POST_CSC_B_C11_C12 0x0d28 3850 #define regCM0_CM_POST_CSC_B_C11_C12_BASE_IDX 2 3851 #define regCM0_CM_POST_CSC_B_C13_C14 0x0d29 3852 #define regCM0_CM_POST_CSC_B_C13_C14_BASE_IDX 2 3853 #define regCM0_CM_POST_CSC_B_C21_C22 0x0d2a 3854 #define regCM0_CM_POST_CSC_B_C21_C22_BASE_IDX 2 3855 #define regCM0_CM_POST_CSC_B_C23_C24 0x0d2b 3856 #define regCM0_CM_POST_CSC_B_C23_C24_BASE_IDX 2 3857 #define regCM0_CM_POST_CSC_B_C31_C32 0x0d2c 3858 #define regCM0_CM_POST_CSC_B_C31_C32_BASE_IDX 2 3859 #define regCM0_CM_POST_CSC_B_C33_C34 0x0d2d 3860 #define regCM0_CM_POST_CSC_B_C33_C34_BASE_IDX 2 3861 #define regCM0_CM_GAMUT_REMAP_CONTROL 0x0d2e 3862 #define regCM0_CM_GAMUT_REMAP_CONTROL_BASE_IDX 2 3863 #define regCM0_CM_GAMUT_REMAP_C11_C12 0x0d2f 3864 #define regCM0_CM_GAMUT_REMAP_C11_C12_BASE_IDX 2 3865 #define regCM0_CM_GAMUT_REMAP_C13_C14 0x0d30 3866 #define regCM0_CM_GAMUT_REMAP_C13_C14_BASE_IDX 2 3867 #define regCM0_CM_GAMUT_REMAP_C21_C22 0x0d31 3868 #define regCM0_CM_GAMUT_REMAP_C21_C22_BASE_IDX 2 3869 #define regCM0_CM_GAMUT_REMAP_C23_C24 0x0d32 3870 #define regCM0_CM_GAMUT_REMAP_C23_C24_BASE_IDX 2 3871 #define regCM0_CM_GAMUT_REMAP_C31_C32 0x0d33 3872 #define regCM0_CM_GAMUT_REMAP_C31_C32_BASE_IDX 2 3873 #define regCM0_CM_GAMUT_REMAP_C33_C34 0x0d34 3874 #define regCM0_CM_GAMUT_REMAP_C33_C34_BASE_IDX 2 3875 #define regCM0_CM_GAMUT_REMAP_B_C11_C12 0x0d35 3876 #define regCM0_CM_GAMUT_REMAP_B_C11_C12_BASE_IDX 2 3877 #define regCM0_CM_GAMUT_REMAP_B_C13_C14 0x0d36 3878 #define regCM0_CM_GAMUT_REMAP_B_C13_C14_BASE_IDX 2 3879 #define regCM0_CM_GAMUT_REMAP_B_C21_C22 0x0d37 3880 #define regCM0_CM_GAMUT_REMAP_B_C21_C22_BASE_IDX 2 3881 #define regCM0_CM_GAMUT_REMAP_B_C23_C24 0x0d38 3882 #define regCM0_CM_GAMUT_REMAP_B_C23_C24_BASE_IDX 2 3883 #define regCM0_CM_GAMUT_REMAP_B_C31_C32 0x0d39 3884 #define regCM0_CM_GAMUT_REMAP_B_C31_C32_BASE_IDX 2 3885 #define regCM0_CM_GAMUT_REMAP_B_C33_C34 0x0d3a 3886 #define regCM0_CM_GAMUT_REMAP_B_C33_C34_BASE_IDX 2 3887 #define regCM0_CM_BIAS_CR_R 0x0d3b 3888 #define regCM0_CM_BIAS_CR_R_BASE_IDX 2 3889 #define regCM0_CM_BIAS_Y_G_CB_B 0x0d3c 3890 #define regCM0_CM_BIAS_Y_G_CB_B_BASE_IDX 2 3891 #define regCM0_CM_GAMCOR_CONTROL 0x0d3d 3892 #define regCM0_CM_GAMCOR_CONTROL_BASE_IDX 2 3893 #define regCM0_CM_GAMCOR_LUT_INDEX 0x0d3e 3894 #define regCM0_CM_GAMCOR_LUT_INDEX_BASE_IDX 2 3895 #define regCM0_CM_GAMCOR_LUT_DATA 0x0d3f 3896 #define regCM0_CM_GAMCOR_LUT_DATA_BASE_IDX 2 3897 #define regCM0_CM_GAMCOR_LUT_CONTROL 0x0d40 3898 #define regCM0_CM_GAMCOR_LUT_CONTROL_BASE_IDX 2 3899 #define regCM0_CM_GAMCOR_RAMA_START_CNTL_B 0x0d41 3900 #define regCM0_CM_GAMCOR_RAMA_START_CNTL_B_BASE_IDX 2 3901 #define regCM0_CM_GAMCOR_RAMA_START_CNTL_G 0x0d42 3902 #define regCM0_CM_GAMCOR_RAMA_START_CNTL_G_BASE_IDX 2 3903 #define regCM0_CM_GAMCOR_RAMA_START_CNTL_R 0x0d43 3904 #define regCM0_CM_GAMCOR_RAMA_START_CNTL_R_BASE_IDX 2 3905 #define regCM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B 0x0d44 3906 #define regCM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B_BASE_IDX 2 3907 #define regCM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G 0x0d45 3908 #define regCM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G_BASE_IDX 2 3909 #define regCM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R 0x0d46 3910 #define regCM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R_BASE_IDX 2 3911 #define regCM0_CM_GAMCOR_RAMA_START_BASE_CNTL_B 0x0d47 3912 #define regCM0_CM_GAMCOR_RAMA_START_BASE_CNTL_B_BASE_IDX 2 3913 #define regCM0_CM_GAMCOR_RAMA_START_BASE_CNTL_G 0x0d48 3914 #define regCM0_CM_GAMCOR_RAMA_START_BASE_CNTL_G_BASE_IDX 2 3915 #define regCM0_CM_GAMCOR_RAMA_START_BASE_CNTL_R 0x0d49 3916 #define regCM0_CM_GAMCOR_RAMA_START_BASE_CNTL_R_BASE_IDX 2 3917 #define regCM0_CM_GAMCOR_RAMA_END_CNTL1_B 0x0d4a 3918 #define regCM0_CM_GAMCOR_RAMA_END_CNTL1_B_BASE_IDX 2 3919 #define regCM0_CM_GAMCOR_RAMA_END_CNTL2_B 0x0d4b 3920 #define regCM0_CM_GAMCOR_RAMA_END_CNTL2_B_BASE_IDX 2 3921 #define regCM0_CM_GAMCOR_RAMA_END_CNTL1_G 0x0d4c 3922 #define regCM0_CM_GAMCOR_RAMA_END_CNTL1_G_BASE_IDX 2 3923 #define regCM0_CM_GAMCOR_RAMA_END_CNTL2_G 0x0d4d 3924 #define regCM0_CM_GAMCOR_RAMA_END_CNTL2_G_BASE_IDX 2 3925 #define regCM0_CM_GAMCOR_RAMA_END_CNTL1_R 0x0d4e 3926 #define regCM0_CM_GAMCOR_RAMA_END_CNTL1_R_BASE_IDX 2 3927 #define regCM0_CM_GAMCOR_RAMA_END_CNTL2_R 0x0d4f 3928 #define regCM0_CM_GAMCOR_RAMA_END_CNTL2_R_BASE_IDX 2 3929 #define regCM0_CM_GAMCOR_RAMA_OFFSET_B 0x0d50 3930 #define regCM0_CM_GAMCOR_RAMA_OFFSET_B_BASE_IDX 2 3931 #define regCM0_CM_GAMCOR_RAMA_OFFSET_G 0x0d51 3932 #define regCM0_CM_GAMCOR_RAMA_OFFSET_G_BASE_IDX 2 3933 #define regCM0_CM_GAMCOR_RAMA_OFFSET_R 0x0d52 3934 #define regCM0_CM_GAMCOR_RAMA_OFFSET_R_BASE_IDX 2 3935 #define regCM0_CM_GAMCOR_RAMA_REGION_0_1 0x0d53 3936 #define regCM0_CM_GAMCOR_RAMA_REGION_0_1_BASE_IDX 2 3937 #define regCM0_CM_GAMCOR_RAMA_REGION_2_3 0x0d54 3938 #define regCM0_CM_GAMCOR_RAMA_REGION_2_3_BASE_IDX 2 3939 #define regCM0_CM_GAMCOR_RAMA_REGION_4_5 0x0d55 3940 #define regCM0_CM_GAMCOR_RAMA_REGION_4_5_BASE_IDX 2 3941 #define regCM0_CM_GAMCOR_RAMA_REGION_6_7 0x0d56 3942 #define regCM0_CM_GAMCOR_RAMA_REGION_6_7_BASE_IDX 2 3943 #define regCM0_CM_GAMCOR_RAMA_REGION_8_9 0x0d57 3944 #define regCM0_CM_GAMCOR_RAMA_REGION_8_9_BASE_IDX 2 3945 #define regCM0_CM_GAMCOR_RAMA_REGION_10_11 0x0d58 3946 #define regCM0_CM_GAMCOR_RAMA_REGION_10_11_BASE_IDX 2 3947 #define regCM0_CM_GAMCOR_RAMA_REGION_12_13 0x0d59 3948 #define regCM0_CM_GAMCOR_RAMA_REGION_12_13_BASE_IDX 2 3949 #define regCM0_CM_GAMCOR_RAMA_REGION_14_15 0x0d5a 3950 #define regCM0_CM_GAMCOR_RAMA_REGION_14_15_BASE_IDX 2 3951 #define regCM0_CM_GAMCOR_RAMA_REGION_16_17 0x0d5b 3952 #define regCM0_CM_GAMCOR_RAMA_REGION_16_17_BASE_IDX 2 3953 #define regCM0_CM_GAMCOR_RAMA_REGION_18_19 0x0d5c 3954 #define regCM0_CM_GAMCOR_RAMA_REGION_18_19_BASE_IDX 2 3955 #define regCM0_CM_GAMCOR_RAMA_REGION_20_21 0x0d5d 3956 #define regCM0_CM_GAMCOR_RAMA_REGION_20_21_BASE_IDX 2 3957 #define regCM0_CM_GAMCOR_RAMA_REGION_22_23 0x0d5e 3958 #define regCM0_CM_GAMCOR_RAMA_REGION_22_23_BASE_IDX 2 3959 #define regCM0_CM_GAMCOR_RAMA_REGION_24_25 0x0d5f 3960 #define regCM0_CM_GAMCOR_RAMA_REGION_24_25_BASE_IDX 2 3961 #define regCM0_CM_GAMCOR_RAMA_REGION_26_27 0x0d60 3962 #define regCM0_CM_GAMCOR_RAMA_REGION_26_27_BASE_IDX 2 3963 #define regCM0_CM_GAMCOR_RAMA_REGION_28_29 0x0d61 3964 #define regCM0_CM_GAMCOR_RAMA_REGION_28_29_BASE_IDX 2 3965 #define regCM0_CM_GAMCOR_RAMA_REGION_30_31 0x0d62 3966 #define regCM0_CM_GAMCOR_RAMA_REGION_30_31_BASE_IDX 2 3967 #define regCM0_CM_GAMCOR_RAMA_REGION_32_33 0x0d63 3968 #define regCM0_CM_GAMCOR_RAMA_REGION_32_33_BASE_IDX 2 3969 #define regCM0_CM_GAMCOR_RAMB_START_CNTL_B 0x0d64 3970 #define regCM0_CM_GAMCOR_RAMB_START_CNTL_B_BASE_IDX 2 3971 #define regCM0_CM_GAMCOR_RAMB_START_CNTL_G 0x0d65 3972 #define regCM0_CM_GAMCOR_RAMB_START_CNTL_G_BASE_IDX 2 3973 #define regCM0_CM_GAMCOR_RAMB_START_CNTL_R 0x0d66 3974 #define regCM0_CM_GAMCOR_RAMB_START_CNTL_R_BASE_IDX 2 3975 #define regCM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B 0x0d67 3976 #define regCM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B_BASE_IDX 2 3977 #define regCM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G 0x0d68 3978 #define regCM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G_BASE_IDX 2 3979 #define regCM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R 0x0d69 3980 #define regCM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R_BASE_IDX 2 3981 #define regCM0_CM_GAMCOR_RAMB_START_BASE_CNTL_B 0x0d6a 3982 #define regCM0_CM_GAMCOR_RAMB_START_BASE_CNTL_B_BASE_IDX 2 3983 #define regCM0_CM_GAMCOR_RAMB_START_BASE_CNTL_G 0x0d6b 3984 #define regCM0_CM_GAMCOR_RAMB_START_BASE_CNTL_G_BASE_IDX 2 3985 #define regCM0_CM_GAMCOR_RAMB_START_BASE_CNTL_R 0x0d6c 3986 #define regCM0_CM_GAMCOR_RAMB_START_BASE_CNTL_R_BASE_IDX 2 3987 #define regCM0_CM_GAMCOR_RAMB_END_CNTL1_B 0x0d6d 3988 #define regCM0_CM_GAMCOR_RAMB_END_CNTL1_B_BASE_IDX 2 3989 #define regCM0_CM_GAMCOR_RAMB_END_CNTL2_B 0x0d6e 3990 #define regCM0_CM_GAMCOR_RAMB_END_CNTL2_B_BASE_IDX 2 3991 #define regCM0_CM_GAMCOR_RAMB_END_CNTL1_G 0x0d6f 3992 #define regCM0_CM_GAMCOR_RAMB_END_CNTL1_G_BASE_IDX 2 3993 #define regCM0_CM_GAMCOR_RAMB_END_CNTL2_G 0x0d70 3994 #define regCM0_CM_GAMCOR_RAMB_END_CNTL2_G_BASE_IDX 2 3995 #define regCM0_CM_GAMCOR_RAMB_END_CNTL1_R 0x0d71 3996 #define regCM0_CM_GAMCOR_RAMB_END_CNTL1_R_BASE_IDX 2 3997 #define regCM0_CM_GAMCOR_RAMB_END_CNTL2_R 0x0d72 3998 #define regCM0_CM_GAMCOR_RAMB_END_CNTL2_R_BASE_IDX 2 3999 #define regCM0_CM_GAMCOR_RAMB_OFFSET_B 0x0d73 4000 #define regCM0_CM_GAMCOR_RAMB_OFFSET_B_BASE_IDX 2 4001 #define regCM0_CM_GAMCOR_RAMB_OFFSET_G 0x0d74 4002 #define regCM0_CM_GAMCOR_RAMB_OFFSET_G_BASE_IDX 2 4003 #define regCM0_CM_GAMCOR_RAMB_OFFSET_R 0x0d75 4004 #define regCM0_CM_GAMCOR_RAMB_OFFSET_R_BASE_IDX 2 4005 #define regCM0_CM_GAMCOR_RAMB_REGION_0_1 0x0d76 4006 #define regCM0_CM_GAMCOR_RAMB_REGION_0_1_BASE_IDX 2 4007 #define regCM0_CM_GAMCOR_RAMB_REGION_2_3 0x0d77 4008 #define regCM0_CM_GAMCOR_RAMB_REGION_2_3_BASE_IDX 2 4009 #define regCM0_CM_GAMCOR_RAMB_REGION_4_5 0x0d78 4010 #define regCM0_CM_GAMCOR_RAMB_REGION_4_5_BASE_IDX 2 4011 #define regCM0_CM_GAMCOR_RAMB_REGION_6_7 0x0d79 4012 #define regCM0_CM_GAMCOR_RAMB_REGION_6_7_BASE_IDX 2 4013 #define regCM0_CM_GAMCOR_RAMB_REGION_8_9 0x0d7a 4014 #define regCM0_CM_GAMCOR_RAMB_REGION_8_9_BASE_IDX 2 4015 #define regCM0_CM_GAMCOR_RAMB_REGION_10_11 0x0d7b 4016 #define regCM0_CM_GAMCOR_RAMB_REGION_10_11_BASE_IDX 2 4017 #define regCM0_CM_GAMCOR_RAMB_REGION_12_13 0x0d7c 4018 #define regCM0_CM_GAMCOR_RAMB_REGION_12_13_BASE_IDX 2 4019 #define regCM0_CM_GAMCOR_RAMB_REGION_14_15 0x0d7d 4020 #define regCM0_CM_GAMCOR_RAMB_REGION_14_15_BASE_IDX 2 4021 #define regCM0_CM_GAMCOR_RAMB_REGION_16_17 0x0d7e 4022 #define regCM0_CM_GAMCOR_RAMB_REGION_16_17_BASE_IDX 2 4023 #define regCM0_CM_GAMCOR_RAMB_REGION_18_19 0x0d7f 4024 #define regCM0_CM_GAMCOR_RAMB_REGION_18_19_BASE_IDX 2 4025 #define regCM0_CM_GAMCOR_RAMB_REGION_20_21 0x0d80 4026 #define regCM0_CM_GAMCOR_RAMB_REGION_20_21_BASE_IDX 2 4027 #define regCM0_CM_GAMCOR_RAMB_REGION_22_23 0x0d81 4028 #define regCM0_CM_GAMCOR_RAMB_REGION_22_23_BASE_IDX 2 4029 #define regCM0_CM_GAMCOR_RAMB_REGION_24_25 0x0d82 4030 #define regCM0_CM_GAMCOR_RAMB_REGION_24_25_BASE_IDX 2 4031 #define regCM0_CM_GAMCOR_RAMB_REGION_26_27 0x0d83 4032 #define regCM0_CM_GAMCOR_RAMB_REGION_26_27_BASE_IDX 2 4033 #define regCM0_CM_GAMCOR_RAMB_REGION_28_29 0x0d84 4034 #define regCM0_CM_GAMCOR_RAMB_REGION_28_29_BASE_IDX 2 4035 #define regCM0_CM_GAMCOR_RAMB_REGION_30_31 0x0d85 4036 #define regCM0_CM_GAMCOR_RAMB_REGION_30_31_BASE_IDX 2 4037 #define regCM0_CM_GAMCOR_RAMB_REGION_32_33 0x0d86 4038 #define regCM0_CM_GAMCOR_RAMB_REGION_32_33_BASE_IDX 2 4039 #define regCM0_CM_BLNDGAM_CONTROL 0x0d87 4040 #define regCM0_CM_BLNDGAM_CONTROL_BASE_IDX 2 4041 #define regCM0_CM_BLNDGAM_LUT_INDEX 0x0d88 4042 #define regCM0_CM_BLNDGAM_LUT_INDEX_BASE_IDX 2 4043 #define regCM0_CM_BLNDGAM_LUT_DATA 0x0d89 4044 #define regCM0_CM_BLNDGAM_LUT_DATA_BASE_IDX 2 4045 #define regCM0_CM_BLNDGAM_LUT_CONTROL 0x0d8a 4046 #define regCM0_CM_BLNDGAM_LUT_CONTROL_BASE_IDX 2 4047 #define regCM0_CM_BLNDGAM_RAMA_START_CNTL_B 0x0d8b 4048 #define regCM0_CM_BLNDGAM_RAMA_START_CNTL_B_BASE_IDX 2 4049 #define regCM0_CM_BLNDGAM_RAMA_START_CNTL_G 0x0d8c 4050 #define regCM0_CM_BLNDGAM_RAMA_START_CNTL_G_BASE_IDX 2 4051 #define regCM0_CM_BLNDGAM_RAMA_START_CNTL_R 0x0d8d 4052 #define regCM0_CM_BLNDGAM_RAMA_START_CNTL_R_BASE_IDX 2 4053 #define regCM0_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_B 0x0d8e 4054 #define regCM0_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_B_BASE_IDX 2 4055 #define regCM0_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_G 0x0d8f 4056 #define regCM0_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_G_BASE_IDX 2 4057 #define regCM0_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_R 0x0d90 4058 #define regCM0_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_R_BASE_IDX 2 4059 #define regCM0_CM_BLNDGAM_RAMA_START_BASE_CNTL_B 0x0d91 4060 #define regCM0_CM_BLNDGAM_RAMA_START_BASE_CNTL_B_BASE_IDX 2 4061 #define regCM0_CM_BLNDGAM_RAMA_START_BASE_CNTL_G 0x0d92 4062 #define regCM0_CM_BLNDGAM_RAMA_START_BASE_CNTL_G_BASE_IDX 2 4063 #define regCM0_CM_BLNDGAM_RAMA_START_BASE_CNTL_R 0x0d93 4064 #define regCM0_CM_BLNDGAM_RAMA_START_BASE_CNTL_R_BASE_IDX 2 4065 #define regCM0_CM_BLNDGAM_RAMA_END_CNTL1_B 0x0d94 4066 #define regCM0_CM_BLNDGAM_RAMA_END_CNTL1_B_BASE_IDX 2 4067 #define regCM0_CM_BLNDGAM_RAMA_END_CNTL2_B 0x0d95 4068 #define regCM0_CM_BLNDGAM_RAMA_END_CNTL2_B_BASE_IDX 2 4069 #define regCM0_CM_BLNDGAM_RAMA_END_CNTL1_G 0x0d96 4070 #define regCM0_CM_BLNDGAM_RAMA_END_CNTL1_G_BASE_IDX 2 4071 #define regCM0_CM_BLNDGAM_RAMA_END_CNTL2_G 0x0d97 4072 #define regCM0_CM_BLNDGAM_RAMA_END_CNTL2_G_BASE_IDX 2 4073 #define regCM0_CM_BLNDGAM_RAMA_END_CNTL1_R 0x0d98 4074 #define regCM0_CM_BLNDGAM_RAMA_END_CNTL1_R_BASE_IDX 2 4075 #define regCM0_CM_BLNDGAM_RAMA_END_CNTL2_R 0x0d99 4076 #define regCM0_CM_BLNDGAM_RAMA_END_CNTL2_R_BASE_IDX 2 4077 #define regCM0_CM_BLNDGAM_RAMA_OFFSET_B 0x0d9a 4078 #define regCM0_CM_BLNDGAM_RAMA_OFFSET_B_BASE_IDX 2 4079 #define regCM0_CM_BLNDGAM_RAMA_OFFSET_G 0x0d9b 4080 #define regCM0_CM_BLNDGAM_RAMA_OFFSET_G_BASE_IDX 2 4081 #define regCM0_CM_BLNDGAM_RAMA_OFFSET_R 0x0d9c 4082 #define regCM0_CM_BLNDGAM_RAMA_OFFSET_R_BASE_IDX 2 4083 #define regCM0_CM_BLNDGAM_RAMA_REGION_0_1 0x0d9d 4084 #define regCM0_CM_BLNDGAM_RAMA_REGION_0_1_BASE_IDX 2 4085 #define regCM0_CM_BLNDGAM_RAMA_REGION_2_3 0x0d9e 4086 #define regCM0_CM_BLNDGAM_RAMA_REGION_2_3_BASE_IDX 2 4087 #define regCM0_CM_BLNDGAM_RAMA_REGION_4_5 0x0d9f 4088 #define regCM0_CM_BLNDGAM_RAMA_REGION_4_5_BASE_IDX 2 4089 #define regCM0_CM_BLNDGAM_RAMA_REGION_6_7 0x0da0 4090 #define regCM0_CM_BLNDGAM_RAMA_REGION_6_7_BASE_IDX 2 4091 #define regCM0_CM_BLNDGAM_RAMA_REGION_8_9 0x0da1 4092 #define regCM0_CM_BLNDGAM_RAMA_REGION_8_9_BASE_IDX 2 4093 #define regCM0_CM_BLNDGAM_RAMA_REGION_10_11 0x0da2 4094 #define regCM0_CM_BLNDGAM_RAMA_REGION_10_11_BASE_IDX 2 4095 #define regCM0_CM_BLNDGAM_RAMA_REGION_12_13 0x0da3 4096 #define regCM0_CM_BLNDGAM_RAMA_REGION_12_13_BASE_IDX 2 4097 #define regCM0_CM_BLNDGAM_RAMA_REGION_14_15 0x0da4 4098 #define regCM0_CM_BLNDGAM_RAMA_REGION_14_15_BASE_IDX 2 4099 #define regCM0_CM_BLNDGAM_RAMA_REGION_16_17 0x0da5 4100 #define regCM0_CM_BLNDGAM_RAMA_REGION_16_17_BASE_IDX 2 4101 #define regCM0_CM_BLNDGAM_RAMA_REGION_18_19 0x0da6 4102 #define regCM0_CM_BLNDGAM_RAMA_REGION_18_19_BASE_IDX 2 4103 #define regCM0_CM_BLNDGAM_RAMA_REGION_20_21 0x0da7 4104 #define regCM0_CM_BLNDGAM_RAMA_REGION_20_21_BASE_IDX 2 4105 #define regCM0_CM_BLNDGAM_RAMA_REGION_22_23 0x0da8 4106 #define regCM0_CM_BLNDGAM_RAMA_REGION_22_23_BASE_IDX 2 4107 #define regCM0_CM_BLNDGAM_RAMA_REGION_24_25 0x0da9 4108 #define regCM0_CM_BLNDGAM_RAMA_REGION_24_25_BASE_IDX 2 4109 #define regCM0_CM_BLNDGAM_RAMA_REGION_26_27 0x0daa 4110 #define regCM0_CM_BLNDGAM_RAMA_REGION_26_27_BASE_IDX 2 4111 #define regCM0_CM_BLNDGAM_RAMA_REGION_28_29 0x0dab 4112 #define regCM0_CM_BLNDGAM_RAMA_REGION_28_29_BASE_IDX 2 4113 #define regCM0_CM_BLNDGAM_RAMA_REGION_30_31 0x0dac 4114 #define regCM0_CM_BLNDGAM_RAMA_REGION_30_31_BASE_IDX 2 4115 #define regCM0_CM_BLNDGAM_RAMA_REGION_32_33 0x0dad 4116 #define regCM0_CM_BLNDGAM_RAMA_REGION_32_33_BASE_IDX 2 4117 #define regCM0_CM_BLNDGAM_RAMB_START_CNTL_B 0x0dae 4118 #define regCM0_CM_BLNDGAM_RAMB_START_CNTL_B_BASE_IDX 2 4119 #define regCM0_CM_BLNDGAM_RAMB_START_CNTL_G 0x0daf 4120 #define regCM0_CM_BLNDGAM_RAMB_START_CNTL_G_BASE_IDX 2 4121 #define regCM0_CM_BLNDGAM_RAMB_START_CNTL_R 0x0db0 4122 #define regCM0_CM_BLNDGAM_RAMB_START_CNTL_R_BASE_IDX 2 4123 #define regCM0_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_B 0x0db1 4124 #define regCM0_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_B_BASE_IDX 2 4125 #define regCM0_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_G 0x0db2 4126 #define regCM0_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_G_BASE_IDX 2 4127 #define regCM0_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_R 0x0db3 4128 #define regCM0_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_R_BASE_IDX 2 4129 #define regCM0_CM_BLNDGAM_RAMB_START_BASE_CNTL_B 0x0db4 4130 #define regCM0_CM_BLNDGAM_RAMB_START_BASE_CNTL_B_BASE_IDX 2 4131 #define regCM0_CM_BLNDGAM_RAMB_START_BASE_CNTL_G 0x0db5 4132 #define regCM0_CM_BLNDGAM_RAMB_START_BASE_CNTL_G_BASE_IDX 2 4133 #define regCM0_CM_BLNDGAM_RAMB_START_BASE_CNTL_R 0x0db6 4134 #define regCM0_CM_BLNDGAM_RAMB_START_BASE_CNTL_R_BASE_IDX 2 4135 #define regCM0_CM_BLNDGAM_RAMB_END_CNTL1_B 0x0db7 4136 #define regCM0_CM_BLNDGAM_RAMB_END_CNTL1_B_BASE_IDX 2 4137 #define regCM0_CM_BLNDGAM_RAMB_END_CNTL2_B 0x0db8 4138 #define regCM0_CM_BLNDGAM_RAMB_END_CNTL2_B_BASE_IDX 2 4139 #define regCM0_CM_BLNDGAM_RAMB_END_CNTL1_G 0x0db9 4140 #define regCM0_CM_BLNDGAM_RAMB_END_CNTL1_G_BASE_IDX 2 4141 #define regCM0_CM_BLNDGAM_RAMB_END_CNTL2_G 0x0dba 4142 #define regCM0_CM_BLNDGAM_RAMB_END_CNTL2_G_BASE_IDX 2 4143 #define regCM0_CM_BLNDGAM_RAMB_END_CNTL1_R 0x0dbb 4144 #define regCM0_CM_BLNDGAM_RAMB_END_CNTL1_R_BASE_IDX 2 4145 #define regCM0_CM_BLNDGAM_RAMB_END_CNTL2_R 0x0dbc 4146 #define regCM0_CM_BLNDGAM_RAMB_END_CNTL2_R_BASE_IDX 2 4147 #define regCM0_CM_BLNDGAM_RAMB_OFFSET_B 0x0dbd 4148 #define regCM0_CM_BLNDGAM_RAMB_OFFSET_B_BASE_IDX 2 4149 #define regCM0_CM_BLNDGAM_RAMB_OFFSET_G 0x0dbe 4150 #define regCM0_CM_BLNDGAM_RAMB_OFFSET_G_BASE_IDX 2 4151 #define regCM0_CM_BLNDGAM_RAMB_OFFSET_R 0x0dbf 4152 #define regCM0_CM_BLNDGAM_RAMB_OFFSET_R_BASE_IDX 2 4153 #define regCM0_CM_BLNDGAM_RAMB_REGION_0_1 0x0dc0 4154 #define regCM0_CM_BLNDGAM_RAMB_REGION_0_1_BASE_IDX 2 4155 #define regCM0_CM_BLNDGAM_RAMB_REGION_2_3 0x0dc1 4156 #define regCM0_CM_BLNDGAM_RAMB_REGION_2_3_BASE_IDX 2 4157 #define regCM0_CM_BLNDGAM_RAMB_REGION_4_5 0x0dc2 4158 #define regCM0_CM_BLNDGAM_RAMB_REGION_4_5_BASE_IDX 2 4159 #define regCM0_CM_BLNDGAM_RAMB_REGION_6_7 0x0dc3 4160 #define regCM0_CM_BLNDGAM_RAMB_REGION_6_7_BASE_IDX 2 4161 #define regCM0_CM_BLNDGAM_RAMB_REGION_8_9 0x0dc4 4162 #define regCM0_CM_BLNDGAM_RAMB_REGION_8_9_BASE_IDX 2 4163 #define regCM0_CM_BLNDGAM_RAMB_REGION_10_11 0x0dc5 4164 #define regCM0_CM_BLNDGAM_RAMB_REGION_10_11_BASE_IDX 2 4165 #define regCM0_CM_BLNDGAM_RAMB_REGION_12_13 0x0dc6 4166 #define regCM0_CM_BLNDGAM_RAMB_REGION_12_13_BASE_IDX 2 4167 #define regCM0_CM_BLNDGAM_RAMB_REGION_14_15 0x0dc7 4168 #define regCM0_CM_BLNDGAM_RAMB_REGION_14_15_BASE_IDX 2 4169 #define regCM0_CM_BLNDGAM_RAMB_REGION_16_17 0x0dc8 4170 #define regCM0_CM_BLNDGAM_RAMB_REGION_16_17_BASE_IDX 2 4171 #define regCM0_CM_BLNDGAM_RAMB_REGION_18_19 0x0dc9 4172 #define regCM0_CM_BLNDGAM_RAMB_REGION_18_19_BASE_IDX 2 4173 #define regCM0_CM_BLNDGAM_RAMB_REGION_20_21 0x0dca 4174 #define regCM0_CM_BLNDGAM_RAMB_REGION_20_21_BASE_IDX 2 4175 #define regCM0_CM_BLNDGAM_RAMB_REGION_22_23 0x0dcb 4176 #define regCM0_CM_BLNDGAM_RAMB_REGION_22_23_BASE_IDX 2 4177 #define regCM0_CM_BLNDGAM_RAMB_REGION_24_25 0x0dcc 4178 #define regCM0_CM_BLNDGAM_RAMB_REGION_24_25_BASE_IDX 2 4179 #define regCM0_CM_BLNDGAM_RAMB_REGION_26_27 0x0dcd 4180 #define regCM0_CM_BLNDGAM_RAMB_REGION_26_27_BASE_IDX 2 4181 #define regCM0_CM_BLNDGAM_RAMB_REGION_28_29 0x0dce 4182 #define regCM0_CM_BLNDGAM_RAMB_REGION_28_29_BASE_IDX 2 4183 #define regCM0_CM_BLNDGAM_RAMB_REGION_30_31 0x0dcf 4184 #define regCM0_CM_BLNDGAM_RAMB_REGION_30_31_BASE_IDX 2 4185 #define regCM0_CM_BLNDGAM_RAMB_REGION_32_33 0x0dd0 4186 #define regCM0_CM_BLNDGAM_RAMB_REGION_32_33_BASE_IDX 2 4187 #define regCM0_CM_HDR_MULT_COEF 0x0dd1 4188 #define regCM0_CM_HDR_MULT_COEF_BASE_IDX 2 4189 #define regCM0_CM_MEM_PWR_CTRL 0x0dd2 4190 #define regCM0_CM_MEM_PWR_CTRL_BASE_IDX 2 4191 #define regCM0_CM_MEM_PWR_STATUS 0x0dd3 4192 #define regCM0_CM_MEM_PWR_STATUS_BASE_IDX 2 4193 #define regCM0_CM_DEALPHA 0x0dd5 4194 #define regCM0_CM_DEALPHA_BASE_IDX 2 4195 #define regCM0_CM_COEF_FORMAT 0x0dd6 4196 #define regCM0_CM_COEF_FORMAT_BASE_IDX 2 4197 #define regCM0_CM_SHAPER_CONTROL 0x0dd7 4198 #define regCM0_CM_SHAPER_CONTROL_BASE_IDX 2 4199 #define regCM0_CM_SHAPER_OFFSET_R 0x0dd8 4200 #define regCM0_CM_SHAPER_OFFSET_R_BASE_IDX 2 4201 #define regCM0_CM_SHAPER_OFFSET_G 0x0dd9 4202 #define regCM0_CM_SHAPER_OFFSET_G_BASE_IDX 2 4203 #define regCM0_CM_SHAPER_OFFSET_B 0x0dda 4204 #define regCM0_CM_SHAPER_OFFSET_B_BASE_IDX 2 4205 #define regCM0_CM_SHAPER_SCALE_R 0x0ddb 4206 #define regCM0_CM_SHAPER_SCALE_R_BASE_IDX 2 4207 #define regCM0_CM_SHAPER_SCALE_G_B 0x0ddc 4208 #define regCM0_CM_SHAPER_SCALE_G_B_BASE_IDX 2 4209 #define regCM0_CM_SHAPER_LUT_INDEX 0x0ddd 4210 #define regCM0_CM_SHAPER_LUT_INDEX_BASE_IDX 2 4211 #define regCM0_CM_SHAPER_LUT_DATA 0x0dde 4212 #define regCM0_CM_SHAPER_LUT_DATA_BASE_IDX 2 4213 #define regCM0_CM_SHAPER_LUT_WRITE_EN_MASK 0x0ddf 4214 #define regCM0_CM_SHAPER_LUT_WRITE_EN_MASK_BASE_IDX 2 4215 #define regCM0_CM_SHAPER_RAMA_START_CNTL_B 0x0de0 4216 #define regCM0_CM_SHAPER_RAMA_START_CNTL_B_BASE_IDX 2 4217 #define regCM0_CM_SHAPER_RAMA_START_CNTL_G 0x0de1 4218 #define regCM0_CM_SHAPER_RAMA_START_CNTL_G_BASE_IDX 2 4219 #define regCM0_CM_SHAPER_RAMA_START_CNTL_R 0x0de2 4220 #define regCM0_CM_SHAPER_RAMA_START_CNTL_R_BASE_IDX 2 4221 #define regCM0_CM_SHAPER_RAMA_END_CNTL_B 0x0de3 4222 #define regCM0_CM_SHAPER_RAMA_END_CNTL_B_BASE_IDX 2 4223 #define regCM0_CM_SHAPER_RAMA_END_CNTL_G 0x0de4 4224 #define regCM0_CM_SHAPER_RAMA_END_CNTL_G_BASE_IDX 2 4225 #define regCM0_CM_SHAPER_RAMA_END_CNTL_R 0x0de5 4226 #define regCM0_CM_SHAPER_RAMA_END_CNTL_R_BASE_IDX 2 4227 #define regCM0_CM_SHAPER_RAMA_REGION_0_1 0x0de6 4228 #define regCM0_CM_SHAPER_RAMA_REGION_0_1_BASE_IDX 2 4229 #define regCM0_CM_SHAPER_RAMA_REGION_2_3 0x0de7 4230 #define regCM0_CM_SHAPER_RAMA_REGION_2_3_BASE_IDX 2 4231 #define regCM0_CM_SHAPER_RAMA_REGION_4_5 0x0de8 4232 #define regCM0_CM_SHAPER_RAMA_REGION_4_5_BASE_IDX 2 4233 #define regCM0_CM_SHAPER_RAMA_REGION_6_7 0x0de9 4234 #define regCM0_CM_SHAPER_RAMA_REGION_6_7_BASE_IDX 2 4235 #define regCM0_CM_SHAPER_RAMA_REGION_8_9 0x0dea 4236 #define regCM0_CM_SHAPER_RAMA_REGION_8_9_BASE_IDX 2 4237 #define regCM0_CM_SHAPER_RAMA_REGION_10_11 0x0deb 4238 #define regCM0_CM_SHAPER_RAMA_REGION_10_11_BASE_IDX 2 4239 #define regCM0_CM_SHAPER_RAMA_REGION_12_13 0x0dec 4240 #define regCM0_CM_SHAPER_RAMA_REGION_12_13_BASE_IDX 2 4241 #define regCM0_CM_SHAPER_RAMA_REGION_14_15 0x0ded 4242 #define regCM0_CM_SHAPER_RAMA_REGION_14_15_BASE_IDX 2 4243 #define regCM0_CM_SHAPER_RAMA_REGION_16_17 0x0dee 4244 #define regCM0_CM_SHAPER_RAMA_REGION_16_17_BASE_IDX 2 4245 #define regCM0_CM_SHAPER_RAMA_REGION_18_19 0x0def 4246 #define regCM0_CM_SHAPER_RAMA_REGION_18_19_BASE_IDX 2 4247 #define regCM0_CM_SHAPER_RAMA_REGION_20_21 0x0df0 4248 #define regCM0_CM_SHAPER_RAMA_REGION_20_21_BASE_IDX 2 4249 #define regCM0_CM_SHAPER_RAMA_REGION_22_23 0x0df1 4250 #define regCM0_CM_SHAPER_RAMA_REGION_22_23_BASE_IDX 2 4251 #define regCM0_CM_SHAPER_RAMA_REGION_24_25 0x0df2 4252 #define regCM0_CM_SHAPER_RAMA_REGION_24_25_BASE_IDX 2 4253 #define regCM0_CM_SHAPER_RAMA_REGION_26_27 0x0df3 4254 #define regCM0_CM_SHAPER_RAMA_REGION_26_27_BASE_IDX 2 4255 #define regCM0_CM_SHAPER_RAMA_REGION_28_29 0x0df4 4256 #define regCM0_CM_SHAPER_RAMA_REGION_28_29_BASE_IDX 2 4257 #define regCM0_CM_SHAPER_RAMA_REGION_30_31 0x0df5 4258 #define regCM0_CM_SHAPER_RAMA_REGION_30_31_BASE_IDX 2 4259 #define regCM0_CM_SHAPER_RAMA_REGION_32_33 0x0df6 4260 #define regCM0_CM_SHAPER_RAMA_REGION_32_33_BASE_IDX 2 4261 #define regCM0_CM_SHAPER_RAMB_START_CNTL_B 0x0df7 4262 #define regCM0_CM_SHAPER_RAMB_START_CNTL_B_BASE_IDX 2 4263 #define regCM0_CM_SHAPER_RAMB_START_CNTL_G 0x0df8 4264 #define regCM0_CM_SHAPER_RAMB_START_CNTL_G_BASE_IDX 2 4265 #define regCM0_CM_SHAPER_RAMB_START_CNTL_R 0x0df9 4266 #define regCM0_CM_SHAPER_RAMB_START_CNTL_R_BASE_IDX 2 4267 #define regCM0_CM_SHAPER_RAMB_END_CNTL_B 0x0dfa 4268 #define regCM0_CM_SHAPER_RAMB_END_CNTL_B_BASE_IDX 2 4269 #define regCM0_CM_SHAPER_RAMB_END_CNTL_G 0x0dfb 4270 #define regCM0_CM_SHAPER_RAMB_END_CNTL_G_BASE_IDX 2 4271 #define regCM0_CM_SHAPER_RAMB_END_CNTL_R 0x0dfc 4272 #define regCM0_CM_SHAPER_RAMB_END_CNTL_R_BASE_IDX 2 4273 #define regCM0_CM_SHAPER_RAMB_REGION_0_1 0x0dfd 4274 #define regCM0_CM_SHAPER_RAMB_REGION_0_1_BASE_IDX 2 4275 #define regCM0_CM_SHAPER_RAMB_REGION_2_3 0x0dfe 4276 #define regCM0_CM_SHAPER_RAMB_REGION_2_3_BASE_IDX 2 4277 #define regCM0_CM_SHAPER_RAMB_REGION_4_5 0x0dff 4278 #define regCM0_CM_SHAPER_RAMB_REGION_4_5_BASE_IDX 2 4279 #define regCM0_CM_SHAPER_RAMB_REGION_6_7 0x0e00 4280 #define regCM0_CM_SHAPER_RAMB_REGION_6_7_BASE_IDX 2 4281 #define regCM0_CM_SHAPER_RAMB_REGION_8_9 0x0e01 4282 #define regCM0_CM_SHAPER_RAMB_REGION_8_9_BASE_IDX 2 4283 #define regCM0_CM_SHAPER_RAMB_REGION_10_11 0x0e02 4284 #define regCM0_CM_SHAPER_RAMB_REGION_10_11_BASE_IDX 2 4285 #define regCM0_CM_SHAPER_RAMB_REGION_12_13 0x0e03 4286 #define regCM0_CM_SHAPER_RAMB_REGION_12_13_BASE_IDX 2 4287 #define regCM0_CM_SHAPER_RAMB_REGION_14_15 0x0e04 4288 #define regCM0_CM_SHAPER_RAMB_REGION_14_15_BASE_IDX 2 4289 #define regCM0_CM_SHAPER_RAMB_REGION_16_17 0x0e05 4290 #define regCM0_CM_SHAPER_RAMB_REGION_16_17_BASE_IDX 2 4291 #define regCM0_CM_SHAPER_RAMB_REGION_18_19 0x0e06 4292 #define regCM0_CM_SHAPER_RAMB_REGION_18_19_BASE_IDX 2 4293 #define regCM0_CM_SHAPER_RAMB_REGION_20_21 0x0e07 4294 #define regCM0_CM_SHAPER_RAMB_REGION_20_21_BASE_IDX 2 4295 #define regCM0_CM_SHAPER_RAMB_REGION_22_23 0x0e08 4296 #define regCM0_CM_SHAPER_RAMB_REGION_22_23_BASE_IDX 2 4297 #define regCM0_CM_SHAPER_RAMB_REGION_24_25 0x0e09 4298 #define regCM0_CM_SHAPER_RAMB_REGION_24_25_BASE_IDX 2 4299 #define regCM0_CM_SHAPER_RAMB_REGION_26_27 0x0e0a 4300 #define regCM0_CM_SHAPER_RAMB_REGION_26_27_BASE_IDX 2 4301 #define regCM0_CM_SHAPER_RAMB_REGION_28_29 0x0e0b 4302 #define regCM0_CM_SHAPER_RAMB_REGION_28_29_BASE_IDX 2 4303 #define regCM0_CM_SHAPER_RAMB_REGION_30_31 0x0e0c 4304 #define regCM0_CM_SHAPER_RAMB_REGION_30_31_BASE_IDX 2 4305 #define regCM0_CM_SHAPER_RAMB_REGION_32_33 0x0e0d 4306 #define regCM0_CM_SHAPER_RAMB_REGION_32_33_BASE_IDX 2 4307 #define regCM0_CM_MEM_PWR_CTRL2 0x0e0e 4308 #define regCM0_CM_MEM_PWR_CTRL2_BASE_IDX 2 4309 #define regCM0_CM_MEM_PWR_STATUS2 0x0e0f 4310 #define regCM0_CM_MEM_PWR_STATUS2_BASE_IDX 2 4311 #define regCM0_CM_3DLUT_MODE 0x0e10 4312 #define regCM0_CM_3DLUT_MODE_BASE_IDX 2 4313 #define regCM0_CM_3DLUT_INDEX 0x0e11 4314 #define regCM0_CM_3DLUT_INDEX_BASE_IDX 2 4315 #define regCM0_CM_3DLUT_DATA 0x0e12 4316 #define regCM0_CM_3DLUT_DATA_BASE_IDX 2 4317 #define regCM0_CM_3DLUT_DATA_30BIT 0x0e13 4318 #define regCM0_CM_3DLUT_DATA_30BIT_BASE_IDX 2 4319 #define regCM0_CM_3DLUT_READ_WRITE_CONTROL 0x0e14 4320 #define regCM0_CM_3DLUT_READ_WRITE_CONTROL_BASE_IDX 2 4321 #define regCM0_CM_3DLUT_OUT_NORM_FACTOR 0x0e15 4322 #define regCM0_CM_3DLUT_OUT_NORM_FACTOR_BASE_IDX 2 4323 #define regCM0_CM_3DLUT_OUT_OFFSET_R 0x0e16 4324 #define regCM0_CM_3DLUT_OUT_OFFSET_R_BASE_IDX 2 4325 #define regCM0_CM_3DLUT_OUT_OFFSET_G 0x0e17 4326 #define regCM0_CM_3DLUT_OUT_OFFSET_G_BASE_IDX 2 4327 #define regCM0_CM_3DLUT_OUT_OFFSET_B 0x0e18 4328 #define regCM0_CM_3DLUT_OUT_OFFSET_B_BASE_IDX 2 4329 #define regCM0_CM_TEST_DEBUG_INDEX 0x0e19 4330 #define regCM0_CM_TEST_DEBUG_INDEX_BASE_IDX 2 4331 #define regCM0_CM_TEST_DEBUG_DATA 0x0e1a 4332 #define regCM0_CM_TEST_DEBUG_DATA_BASE_IDX 2 4333 4334 4335 // addressBlock: dce_dc_dpp0_dispdec_dpp_top_dispdec 4336 // base address: 0x0 4337 #define regDPP_TOP0_DPP_CONTROL 0x0cc5 4338 #define regDPP_TOP0_DPP_CONTROL_BASE_IDX 2 4339 #define regDPP_TOP0_DPP_SOFT_RESET 0x0cc6 4340 #define regDPP_TOP0_DPP_SOFT_RESET_BASE_IDX 2 4341 #define regDPP_TOP0_DPP_CRC_VAL_R_G 0x0cc7 4342 #define regDPP_TOP0_DPP_CRC_VAL_R_G_BASE_IDX 2 4343 #define regDPP_TOP0_DPP_CRC_VAL_B_A 0x0cc8 4344 #define regDPP_TOP0_DPP_CRC_VAL_B_A_BASE_IDX 2 4345 #define regDPP_TOP0_DPP_CRC_CTRL 0x0cc9 4346 #define regDPP_TOP0_DPP_CRC_CTRL_BASE_IDX 2 4347 #define regDPP_TOP0_HOST_READ_CONTROL 0x0cca 4348 #define regDPP_TOP0_HOST_READ_CONTROL_BASE_IDX 2 4349 4350 4351 // addressBlock: dce_dc_dpp0_dispdec_dpp_dcperfmon_dc_perfmon_dispdec 4352 // base address: 0x3890 4353 #define regDC_PERFMON11_PERFCOUNTER_CNTL 0x0e24 4354 #define regDC_PERFMON11_PERFCOUNTER_CNTL_BASE_IDX 2 4355 #define regDC_PERFMON11_PERFCOUNTER_CNTL2 0x0e25 4356 #define regDC_PERFMON11_PERFCOUNTER_CNTL2_BASE_IDX 2 4357 #define regDC_PERFMON11_PERFCOUNTER_STATE 0x0e26 4358 #define regDC_PERFMON11_PERFCOUNTER_STATE_BASE_IDX 2 4359 #define regDC_PERFMON11_PERFMON_CNTL 0x0e27 4360 #define regDC_PERFMON11_PERFMON_CNTL_BASE_IDX 2 4361 #define regDC_PERFMON11_PERFMON_CNTL2 0x0e28 4362 #define regDC_PERFMON11_PERFMON_CNTL2_BASE_IDX 2 4363 #define regDC_PERFMON11_PERFMON_CVALUE_INT_MISC 0x0e29 4364 #define regDC_PERFMON11_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 4365 #define regDC_PERFMON11_PERFMON_CVALUE_LOW 0x0e2a 4366 #define regDC_PERFMON11_PERFMON_CVALUE_LOW_BASE_IDX 2 4367 #define regDC_PERFMON11_PERFMON_HI 0x0e2b 4368 #define regDC_PERFMON11_PERFMON_HI_BASE_IDX 2 4369 #define regDC_PERFMON11_PERFMON_LOW 0x0e2c 4370 #define regDC_PERFMON11_PERFMON_LOW_BASE_IDX 2 4371 4372 4373 // addressBlock: dce_dc_dpp1_dispdec_cnvc_cfg_dispdec 4374 // base address: 0x5ac 4375 #define regCNVC_CFG1_CNVC_SURFACE_PIXEL_FORMAT 0x0e3a 4376 #define regCNVC_CFG1_CNVC_SURFACE_PIXEL_FORMAT_BASE_IDX 2 4377 #define regCNVC_CFG1_FORMAT_CONTROL 0x0e3b 4378 #define regCNVC_CFG1_FORMAT_CONTROL_BASE_IDX 2 4379 #define regCNVC_CFG1_FCNV_FP_BIAS_R 0x0e3c 4380 #define regCNVC_CFG1_FCNV_FP_BIAS_R_BASE_IDX 2 4381 #define regCNVC_CFG1_FCNV_FP_BIAS_G 0x0e3d 4382 #define regCNVC_CFG1_FCNV_FP_BIAS_G_BASE_IDX 2 4383 #define regCNVC_CFG1_FCNV_FP_BIAS_B 0x0e3e 4384 #define regCNVC_CFG1_FCNV_FP_BIAS_B_BASE_IDX 2 4385 #define regCNVC_CFG1_FCNV_FP_SCALE_R 0x0e3f 4386 #define regCNVC_CFG1_FCNV_FP_SCALE_R_BASE_IDX 2 4387 #define regCNVC_CFG1_FCNV_FP_SCALE_G 0x0e40 4388 #define regCNVC_CFG1_FCNV_FP_SCALE_G_BASE_IDX 2 4389 #define regCNVC_CFG1_FCNV_FP_SCALE_B 0x0e41 4390 #define regCNVC_CFG1_FCNV_FP_SCALE_B_BASE_IDX 2 4391 #define regCNVC_CFG1_COLOR_KEYER_CONTROL 0x0e42 4392 #define regCNVC_CFG1_COLOR_KEYER_CONTROL_BASE_IDX 2 4393 #define regCNVC_CFG1_COLOR_KEYER_ALPHA 0x0e43 4394 #define regCNVC_CFG1_COLOR_KEYER_ALPHA_BASE_IDX 2 4395 #define regCNVC_CFG1_COLOR_KEYER_RED 0x0e44 4396 #define regCNVC_CFG1_COLOR_KEYER_RED_BASE_IDX 2 4397 #define regCNVC_CFG1_COLOR_KEYER_GREEN 0x0e45 4398 #define regCNVC_CFG1_COLOR_KEYER_GREEN_BASE_IDX 2 4399 #define regCNVC_CFG1_COLOR_KEYER_BLUE 0x0e46 4400 #define regCNVC_CFG1_COLOR_KEYER_BLUE_BASE_IDX 2 4401 #define regCNVC_CFG1_ALPHA_2BIT_LUT 0x0e48 4402 #define regCNVC_CFG1_ALPHA_2BIT_LUT_BASE_IDX 2 4403 #define regCNVC_CFG1_PRE_DEALPHA 0x0e49 4404 #define regCNVC_CFG1_PRE_DEALPHA_BASE_IDX 2 4405 #define regCNVC_CFG1_PRE_CSC_MODE 0x0e4a 4406 #define regCNVC_CFG1_PRE_CSC_MODE_BASE_IDX 2 4407 #define regCNVC_CFG1_PRE_CSC_C11_C12 0x0e4b 4408 #define regCNVC_CFG1_PRE_CSC_C11_C12_BASE_IDX 2 4409 #define regCNVC_CFG1_PRE_CSC_C13_C14 0x0e4c 4410 #define regCNVC_CFG1_PRE_CSC_C13_C14_BASE_IDX 2 4411 #define regCNVC_CFG1_PRE_CSC_C21_C22 0x0e4d 4412 #define regCNVC_CFG1_PRE_CSC_C21_C22_BASE_IDX 2 4413 #define regCNVC_CFG1_PRE_CSC_C23_C24 0x0e4e 4414 #define regCNVC_CFG1_PRE_CSC_C23_C24_BASE_IDX 2 4415 #define regCNVC_CFG1_PRE_CSC_C31_C32 0x0e4f 4416 #define regCNVC_CFG1_PRE_CSC_C31_C32_BASE_IDX 2 4417 #define regCNVC_CFG1_PRE_CSC_C33_C34 0x0e50 4418 #define regCNVC_CFG1_PRE_CSC_C33_C34_BASE_IDX 2 4419 #define regCNVC_CFG1_PRE_CSC_B_C11_C12 0x0e51 4420 #define regCNVC_CFG1_PRE_CSC_B_C11_C12_BASE_IDX 2 4421 #define regCNVC_CFG1_PRE_CSC_B_C13_C14 0x0e52 4422 #define regCNVC_CFG1_PRE_CSC_B_C13_C14_BASE_IDX 2 4423 #define regCNVC_CFG1_PRE_CSC_B_C21_C22 0x0e53 4424 #define regCNVC_CFG1_PRE_CSC_B_C21_C22_BASE_IDX 2 4425 #define regCNVC_CFG1_PRE_CSC_B_C23_C24 0x0e54 4426 #define regCNVC_CFG1_PRE_CSC_B_C23_C24_BASE_IDX 2 4427 #define regCNVC_CFG1_PRE_CSC_B_C31_C32 0x0e55 4428 #define regCNVC_CFG1_PRE_CSC_B_C31_C32_BASE_IDX 2 4429 #define regCNVC_CFG1_PRE_CSC_B_C33_C34 0x0e56 4430 #define regCNVC_CFG1_PRE_CSC_B_C33_C34_BASE_IDX 2 4431 #define regCNVC_CFG1_CNVC_COEF_FORMAT 0x0e57 4432 #define regCNVC_CFG1_CNVC_COEF_FORMAT_BASE_IDX 2 4433 #define regCNVC_CFG1_PRE_DEGAM 0x0e58 4434 #define regCNVC_CFG1_PRE_DEGAM_BASE_IDX 2 4435 #define regCNVC_CFG1_PRE_REALPHA 0x0e59 4436 #define regCNVC_CFG1_PRE_REALPHA_BASE_IDX 2 4437 4438 4439 // addressBlock: dce_dc_dpp1_dispdec_cnvc_cur_dispdec 4440 // base address: 0x5ac 4441 #define regCNVC_CUR1_CURSOR0_CONTROL 0x0e5c 4442 #define regCNVC_CUR1_CURSOR0_CONTROL_BASE_IDX 2 4443 #define regCNVC_CUR1_CURSOR0_COLOR0 0x0e5d 4444 #define regCNVC_CUR1_CURSOR0_COLOR0_BASE_IDX 2 4445 #define regCNVC_CUR1_CURSOR0_COLOR1 0x0e5e 4446 #define regCNVC_CUR1_CURSOR0_COLOR1_BASE_IDX 2 4447 #define regCNVC_CUR1_CURSOR0_FP_SCALE_BIAS 0x0e5f 4448 #define regCNVC_CUR1_CURSOR0_FP_SCALE_BIAS_BASE_IDX 2 4449 4450 4451 // addressBlock: dce_dc_dpp1_dispdec_dscl_dispdec 4452 // base address: 0x5ac 4453 #define regDSCL1_SCL_COEF_RAM_TAP_SELECT 0x0e64 4454 #define regDSCL1_SCL_COEF_RAM_TAP_SELECT_BASE_IDX 2 4455 #define regDSCL1_SCL_COEF_RAM_TAP_DATA 0x0e65 4456 #define regDSCL1_SCL_COEF_RAM_TAP_DATA_BASE_IDX 2 4457 #define regDSCL1_SCL_MODE 0x0e66 4458 #define regDSCL1_SCL_MODE_BASE_IDX 2 4459 #define regDSCL1_SCL_TAP_CONTROL 0x0e67 4460 #define regDSCL1_SCL_TAP_CONTROL_BASE_IDX 2 4461 #define regDSCL1_DSCL_CONTROL 0x0e68 4462 #define regDSCL1_DSCL_CONTROL_BASE_IDX 2 4463 #define regDSCL1_DSCL_2TAP_CONTROL 0x0e69 4464 #define regDSCL1_DSCL_2TAP_CONTROL_BASE_IDX 2 4465 #define regDSCL1_SCL_MANUAL_REPLICATE_CONTROL 0x0e6a 4466 #define regDSCL1_SCL_MANUAL_REPLICATE_CONTROL_BASE_IDX 2 4467 #define regDSCL1_SCL_HORZ_FILTER_SCALE_RATIO 0x0e6b 4468 #define regDSCL1_SCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX 2 4469 #define regDSCL1_SCL_HORZ_FILTER_INIT 0x0e6c 4470 #define regDSCL1_SCL_HORZ_FILTER_INIT_BASE_IDX 2 4471 #define regDSCL1_SCL_HORZ_FILTER_SCALE_RATIO_C 0x0e6d 4472 #define regDSCL1_SCL_HORZ_FILTER_SCALE_RATIO_C_BASE_IDX 2 4473 #define regDSCL1_SCL_HORZ_FILTER_INIT_C 0x0e6e 4474 #define regDSCL1_SCL_HORZ_FILTER_INIT_C_BASE_IDX 2 4475 #define regDSCL1_SCL_VERT_FILTER_SCALE_RATIO 0x0e6f 4476 #define regDSCL1_SCL_VERT_FILTER_SCALE_RATIO_BASE_IDX 2 4477 #define regDSCL1_SCL_VERT_FILTER_INIT 0x0e70 4478 #define regDSCL1_SCL_VERT_FILTER_INIT_BASE_IDX 2 4479 #define regDSCL1_SCL_VERT_FILTER_INIT_BOT 0x0e71 4480 #define regDSCL1_SCL_VERT_FILTER_INIT_BOT_BASE_IDX 2 4481 #define regDSCL1_SCL_VERT_FILTER_SCALE_RATIO_C 0x0e72 4482 #define regDSCL1_SCL_VERT_FILTER_SCALE_RATIO_C_BASE_IDX 2 4483 #define regDSCL1_SCL_VERT_FILTER_INIT_C 0x0e73 4484 #define regDSCL1_SCL_VERT_FILTER_INIT_C_BASE_IDX 2 4485 #define regDSCL1_SCL_VERT_FILTER_INIT_BOT_C 0x0e74 4486 #define regDSCL1_SCL_VERT_FILTER_INIT_BOT_C_BASE_IDX 2 4487 #define regDSCL1_SCL_BLACK_COLOR 0x0e75 4488 #define regDSCL1_SCL_BLACK_COLOR_BASE_IDX 2 4489 #define regDSCL1_DSCL_UPDATE 0x0e76 4490 #define regDSCL1_DSCL_UPDATE_BASE_IDX 2 4491 #define regDSCL1_DSCL_AUTOCAL 0x0e77 4492 #define regDSCL1_DSCL_AUTOCAL_BASE_IDX 2 4493 #define regDSCL1_DSCL_EXT_OVERSCAN_LEFT_RIGHT 0x0e78 4494 #define regDSCL1_DSCL_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX 2 4495 #define regDSCL1_DSCL_EXT_OVERSCAN_TOP_BOTTOM 0x0e79 4496 #define regDSCL1_DSCL_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX 2 4497 #define regDSCL1_OTG_H_BLANK 0x0e7a 4498 #define regDSCL1_OTG_H_BLANK_BASE_IDX 2 4499 #define regDSCL1_OTG_V_BLANK 0x0e7b 4500 #define regDSCL1_OTG_V_BLANK_BASE_IDX 2 4501 #define regDSCL1_RECOUT_START 0x0e7c 4502 #define regDSCL1_RECOUT_START_BASE_IDX 2 4503 #define regDSCL1_RECOUT_SIZE 0x0e7d 4504 #define regDSCL1_RECOUT_SIZE_BASE_IDX 2 4505 #define regDSCL1_MPC_SIZE 0x0e7e 4506 #define regDSCL1_MPC_SIZE_BASE_IDX 2 4507 #define regDSCL1_LB_DATA_FORMAT 0x0e7f 4508 #define regDSCL1_LB_DATA_FORMAT_BASE_IDX 2 4509 #define regDSCL1_LB_MEMORY_CTRL 0x0e80 4510 #define regDSCL1_LB_MEMORY_CTRL_BASE_IDX 2 4511 #define regDSCL1_LB_V_COUNTER 0x0e81 4512 #define regDSCL1_LB_V_COUNTER_BASE_IDX 2 4513 #define regDSCL1_DSCL_MEM_PWR_CTRL 0x0e82 4514 #define regDSCL1_DSCL_MEM_PWR_CTRL_BASE_IDX 2 4515 #define regDSCL1_DSCL_MEM_PWR_STATUS 0x0e83 4516 #define regDSCL1_DSCL_MEM_PWR_STATUS_BASE_IDX 2 4517 #define regDSCL1_OBUF_CONTROL 0x0e84 4518 #define regDSCL1_OBUF_CONTROL_BASE_IDX 2 4519 #define regDSCL1_OBUF_MEM_PWR_CTRL 0x0e85 4520 #define regDSCL1_OBUF_MEM_PWR_CTRL_BASE_IDX 2 4521 4522 4523 // addressBlock: dce_dc_dpp1_dispdec_cm_dispdec 4524 // base address: 0x5ac 4525 #define regCM1_CM_CONTROL 0x0e8b 4526 #define regCM1_CM_CONTROL_BASE_IDX 2 4527 #define regCM1_CM_POST_CSC_CONTROL 0x0e8c 4528 #define regCM1_CM_POST_CSC_CONTROL_BASE_IDX 2 4529 #define regCM1_CM_POST_CSC_C11_C12 0x0e8d 4530 #define regCM1_CM_POST_CSC_C11_C12_BASE_IDX 2 4531 #define regCM1_CM_POST_CSC_C13_C14 0x0e8e 4532 #define regCM1_CM_POST_CSC_C13_C14_BASE_IDX 2 4533 #define regCM1_CM_POST_CSC_C21_C22 0x0e8f 4534 #define regCM1_CM_POST_CSC_C21_C22_BASE_IDX 2 4535 #define regCM1_CM_POST_CSC_C23_C24 0x0e90 4536 #define regCM1_CM_POST_CSC_C23_C24_BASE_IDX 2 4537 #define regCM1_CM_POST_CSC_C31_C32 0x0e91 4538 #define regCM1_CM_POST_CSC_C31_C32_BASE_IDX 2 4539 #define regCM1_CM_POST_CSC_C33_C34 0x0e92 4540 #define regCM1_CM_POST_CSC_C33_C34_BASE_IDX 2 4541 #define regCM1_CM_POST_CSC_B_C11_C12 0x0e93 4542 #define regCM1_CM_POST_CSC_B_C11_C12_BASE_IDX 2 4543 #define regCM1_CM_POST_CSC_B_C13_C14 0x0e94 4544 #define regCM1_CM_POST_CSC_B_C13_C14_BASE_IDX 2 4545 #define regCM1_CM_POST_CSC_B_C21_C22 0x0e95 4546 #define regCM1_CM_POST_CSC_B_C21_C22_BASE_IDX 2 4547 #define regCM1_CM_POST_CSC_B_C23_C24 0x0e96 4548 #define regCM1_CM_POST_CSC_B_C23_C24_BASE_IDX 2 4549 #define regCM1_CM_POST_CSC_B_C31_C32 0x0e97 4550 #define regCM1_CM_POST_CSC_B_C31_C32_BASE_IDX 2 4551 #define regCM1_CM_POST_CSC_B_C33_C34 0x0e98 4552 #define regCM1_CM_POST_CSC_B_C33_C34_BASE_IDX 2 4553 #define regCM1_CM_GAMUT_REMAP_CONTROL 0x0e99 4554 #define regCM1_CM_GAMUT_REMAP_CONTROL_BASE_IDX 2 4555 #define regCM1_CM_GAMUT_REMAP_C11_C12 0x0e9a 4556 #define regCM1_CM_GAMUT_REMAP_C11_C12_BASE_IDX 2 4557 #define regCM1_CM_GAMUT_REMAP_C13_C14 0x0e9b 4558 #define regCM1_CM_GAMUT_REMAP_C13_C14_BASE_IDX 2 4559 #define regCM1_CM_GAMUT_REMAP_C21_C22 0x0e9c 4560 #define regCM1_CM_GAMUT_REMAP_C21_C22_BASE_IDX 2 4561 #define regCM1_CM_GAMUT_REMAP_C23_C24 0x0e9d 4562 #define regCM1_CM_GAMUT_REMAP_C23_C24_BASE_IDX 2 4563 #define regCM1_CM_GAMUT_REMAP_C31_C32 0x0e9e 4564 #define regCM1_CM_GAMUT_REMAP_C31_C32_BASE_IDX 2 4565 #define regCM1_CM_GAMUT_REMAP_C33_C34 0x0e9f 4566 #define regCM1_CM_GAMUT_REMAP_C33_C34_BASE_IDX 2 4567 #define regCM1_CM_GAMUT_REMAP_B_C11_C12 0x0ea0 4568 #define regCM1_CM_GAMUT_REMAP_B_C11_C12_BASE_IDX 2 4569 #define regCM1_CM_GAMUT_REMAP_B_C13_C14 0x0ea1 4570 #define regCM1_CM_GAMUT_REMAP_B_C13_C14_BASE_IDX 2 4571 #define regCM1_CM_GAMUT_REMAP_B_C21_C22 0x0ea2 4572 #define regCM1_CM_GAMUT_REMAP_B_C21_C22_BASE_IDX 2 4573 #define regCM1_CM_GAMUT_REMAP_B_C23_C24 0x0ea3 4574 #define regCM1_CM_GAMUT_REMAP_B_C23_C24_BASE_IDX 2 4575 #define regCM1_CM_GAMUT_REMAP_B_C31_C32 0x0ea4 4576 #define regCM1_CM_GAMUT_REMAP_B_C31_C32_BASE_IDX 2 4577 #define regCM1_CM_GAMUT_REMAP_B_C33_C34 0x0ea5 4578 #define regCM1_CM_GAMUT_REMAP_B_C33_C34_BASE_IDX 2 4579 #define regCM1_CM_BIAS_CR_R 0x0ea6 4580 #define regCM1_CM_BIAS_CR_R_BASE_IDX 2 4581 #define regCM1_CM_BIAS_Y_G_CB_B 0x0ea7 4582 #define regCM1_CM_BIAS_Y_G_CB_B_BASE_IDX 2 4583 #define regCM1_CM_GAMCOR_CONTROL 0x0ea8 4584 #define regCM1_CM_GAMCOR_CONTROL_BASE_IDX 2 4585 #define regCM1_CM_GAMCOR_LUT_INDEX 0x0ea9 4586 #define regCM1_CM_GAMCOR_LUT_INDEX_BASE_IDX 2 4587 #define regCM1_CM_GAMCOR_LUT_DATA 0x0eaa 4588 #define regCM1_CM_GAMCOR_LUT_DATA_BASE_IDX 2 4589 #define regCM1_CM_GAMCOR_LUT_CONTROL 0x0eab 4590 #define regCM1_CM_GAMCOR_LUT_CONTROL_BASE_IDX 2 4591 #define regCM1_CM_GAMCOR_RAMA_START_CNTL_B 0x0eac 4592 #define regCM1_CM_GAMCOR_RAMA_START_CNTL_B_BASE_IDX 2 4593 #define regCM1_CM_GAMCOR_RAMA_START_CNTL_G 0x0ead 4594 #define regCM1_CM_GAMCOR_RAMA_START_CNTL_G_BASE_IDX 2 4595 #define regCM1_CM_GAMCOR_RAMA_START_CNTL_R 0x0eae 4596 #define regCM1_CM_GAMCOR_RAMA_START_CNTL_R_BASE_IDX 2 4597 #define regCM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B 0x0eaf 4598 #define regCM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B_BASE_IDX 2 4599 #define regCM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G 0x0eb0 4600 #define regCM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G_BASE_IDX 2 4601 #define regCM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R 0x0eb1 4602 #define regCM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R_BASE_IDX 2 4603 #define regCM1_CM_GAMCOR_RAMA_START_BASE_CNTL_B 0x0eb2 4604 #define regCM1_CM_GAMCOR_RAMA_START_BASE_CNTL_B_BASE_IDX 2 4605 #define regCM1_CM_GAMCOR_RAMA_START_BASE_CNTL_G 0x0eb3 4606 #define regCM1_CM_GAMCOR_RAMA_START_BASE_CNTL_G_BASE_IDX 2 4607 #define regCM1_CM_GAMCOR_RAMA_START_BASE_CNTL_R 0x0eb4 4608 #define regCM1_CM_GAMCOR_RAMA_START_BASE_CNTL_R_BASE_IDX 2 4609 #define regCM1_CM_GAMCOR_RAMA_END_CNTL1_B 0x0eb5 4610 #define regCM1_CM_GAMCOR_RAMA_END_CNTL1_B_BASE_IDX 2 4611 #define regCM1_CM_GAMCOR_RAMA_END_CNTL2_B 0x0eb6 4612 #define regCM1_CM_GAMCOR_RAMA_END_CNTL2_B_BASE_IDX 2 4613 #define regCM1_CM_GAMCOR_RAMA_END_CNTL1_G 0x0eb7 4614 #define regCM1_CM_GAMCOR_RAMA_END_CNTL1_G_BASE_IDX 2 4615 #define regCM1_CM_GAMCOR_RAMA_END_CNTL2_G 0x0eb8 4616 #define regCM1_CM_GAMCOR_RAMA_END_CNTL2_G_BASE_IDX 2 4617 #define regCM1_CM_GAMCOR_RAMA_END_CNTL1_R 0x0eb9 4618 #define regCM1_CM_GAMCOR_RAMA_END_CNTL1_R_BASE_IDX 2 4619 #define regCM1_CM_GAMCOR_RAMA_END_CNTL2_R 0x0eba 4620 #define regCM1_CM_GAMCOR_RAMA_END_CNTL2_R_BASE_IDX 2 4621 #define regCM1_CM_GAMCOR_RAMA_OFFSET_B 0x0ebb 4622 #define regCM1_CM_GAMCOR_RAMA_OFFSET_B_BASE_IDX 2 4623 #define regCM1_CM_GAMCOR_RAMA_OFFSET_G 0x0ebc 4624 #define regCM1_CM_GAMCOR_RAMA_OFFSET_G_BASE_IDX 2 4625 #define regCM1_CM_GAMCOR_RAMA_OFFSET_R 0x0ebd 4626 #define regCM1_CM_GAMCOR_RAMA_OFFSET_R_BASE_IDX 2 4627 #define regCM1_CM_GAMCOR_RAMA_REGION_0_1 0x0ebe 4628 #define regCM1_CM_GAMCOR_RAMA_REGION_0_1_BASE_IDX 2 4629 #define regCM1_CM_GAMCOR_RAMA_REGION_2_3 0x0ebf 4630 #define regCM1_CM_GAMCOR_RAMA_REGION_2_3_BASE_IDX 2 4631 #define regCM1_CM_GAMCOR_RAMA_REGION_4_5 0x0ec0 4632 #define regCM1_CM_GAMCOR_RAMA_REGION_4_5_BASE_IDX 2 4633 #define regCM1_CM_GAMCOR_RAMA_REGION_6_7 0x0ec1 4634 #define regCM1_CM_GAMCOR_RAMA_REGION_6_7_BASE_IDX 2 4635 #define regCM1_CM_GAMCOR_RAMA_REGION_8_9 0x0ec2 4636 #define regCM1_CM_GAMCOR_RAMA_REGION_8_9_BASE_IDX 2 4637 #define regCM1_CM_GAMCOR_RAMA_REGION_10_11 0x0ec3 4638 #define regCM1_CM_GAMCOR_RAMA_REGION_10_11_BASE_IDX 2 4639 #define regCM1_CM_GAMCOR_RAMA_REGION_12_13 0x0ec4 4640 #define regCM1_CM_GAMCOR_RAMA_REGION_12_13_BASE_IDX 2 4641 #define regCM1_CM_GAMCOR_RAMA_REGION_14_15 0x0ec5 4642 #define regCM1_CM_GAMCOR_RAMA_REGION_14_15_BASE_IDX 2 4643 #define regCM1_CM_GAMCOR_RAMA_REGION_16_17 0x0ec6 4644 #define regCM1_CM_GAMCOR_RAMA_REGION_16_17_BASE_IDX 2 4645 #define regCM1_CM_GAMCOR_RAMA_REGION_18_19 0x0ec7 4646 #define regCM1_CM_GAMCOR_RAMA_REGION_18_19_BASE_IDX 2 4647 #define regCM1_CM_GAMCOR_RAMA_REGION_20_21 0x0ec8 4648 #define regCM1_CM_GAMCOR_RAMA_REGION_20_21_BASE_IDX 2 4649 #define regCM1_CM_GAMCOR_RAMA_REGION_22_23 0x0ec9 4650 #define regCM1_CM_GAMCOR_RAMA_REGION_22_23_BASE_IDX 2 4651 #define regCM1_CM_GAMCOR_RAMA_REGION_24_25 0x0eca 4652 #define regCM1_CM_GAMCOR_RAMA_REGION_24_25_BASE_IDX 2 4653 #define regCM1_CM_GAMCOR_RAMA_REGION_26_27 0x0ecb 4654 #define regCM1_CM_GAMCOR_RAMA_REGION_26_27_BASE_IDX 2 4655 #define regCM1_CM_GAMCOR_RAMA_REGION_28_29 0x0ecc 4656 #define regCM1_CM_GAMCOR_RAMA_REGION_28_29_BASE_IDX 2 4657 #define regCM1_CM_GAMCOR_RAMA_REGION_30_31 0x0ecd 4658 #define regCM1_CM_GAMCOR_RAMA_REGION_30_31_BASE_IDX 2 4659 #define regCM1_CM_GAMCOR_RAMA_REGION_32_33 0x0ece 4660 #define regCM1_CM_GAMCOR_RAMA_REGION_32_33_BASE_IDX 2 4661 #define regCM1_CM_GAMCOR_RAMB_START_CNTL_B 0x0ecf 4662 #define regCM1_CM_GAMCOR_RAMB_START_CNTL_B_BASE_IDX 2 4663 #define regCM1_CM_GAMCOR_RAMB_START_CNTL_G 0x0ed0 4664 #define regCM1_CM_GAMCOR_RAMB_START_CNTL_G_BASE_IDX 2 4665 #define regCM1_CM_GAMCOR_RAMB_START_CNTL_R 0x0ed1 4666 #define regCM1_CM_GAMCOR_RAMB_START_CNTL_R_BASE_IDX 2 4667 #define regCM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B 0x0ed2 4668 #define regCM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B_BASE_IDX 2 4669 #define regCM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G 0x0ed3 4670 #define regCM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G_BASE_IDX 2 4671 #define regCM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R 0x0ed4 4672 #define regCM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R_BASE_IDX 2 4673 #define regCM1_CM_GAMCOR_RAMB_START_BASE_CNTL_B 0x0ed5 4674 #define regCM1_CM_GAMCOR_RAMB_START_BASE_CNTL_B_BASE_IDX 2 4675 #define regCM1_CM_GAMCOR_RAMB_START_BASE_CNTL_G 0x0ed6 4676 #define regCM1_CM_GAMCOR_RAMB_START_BASE_CNTL_G_BASE_IDX 2 4677 #define regCM1_CM_GAMCOR_RAMB_START_BASE_CNTL_R 0x0ed7 4678 #define regCM1_CM_GAMCOR_RAMB_START_BASE_CNTL_R_BASE_IDX 2 4679 #define regCM1_CM_GAMCOR_RAMB_END_CNTL1_B 0x0ed8 4680 #define regCM1_CM_GAMCOR_RAMB_END_CNTL1_B_BASE_IDX 2 4681 #define regCM1_CM_GAMCOR_RAMB_END_CNTL2_B 0x0ed9 4682 #define regCM1_CM_GAMCOR_RAMB_END_CNTL2_B_BASE_IDX 2 4683 #define regCM1_CM_GAMCOR_RAMB_END_CNTL1_G 0x0eda 4684 #define regCM1_CM_GAMCOR_RAMB_END_CNTL1_G_BASE_IDX 2 4685 #define regCM1_CM_GAMCOR_RAMB_END_CNTL2_G 0x0edb 4686 #define regCM1_CM_GAMCOR_RAMB_END_CNTL2_G_BASE_IDX 2 4687 #define regCM1_CM_GAMCOR_RAMB_END_CNTL1_R 0x0edc 4688 #define regCM1_CM_GAMCOR_RAMB_END_CNTL1_R_BASE_IDX 2 4689 #define regCM1_CM_GAMCOR_RAMB_END_CNTL2_R 0x0edd 4690 #define regCM1_CM_GAMCOR_RAMB_END_CNTL2_R_BASE_IDX 2 4691 #define regCM1_CM_GAMCOR_RAMB_OFFSET_B 0x0ede 4692 #define regCM1_CM_GAMCOR_RAMB_OFFSET_B_BASE_IDX 2 4693 #define regCM1_CM_GAMCOR_RAMB_OFFSET_G 0x0edf 4694 #define regCM1_CM_GAMCOR_RAMB_OFFSET_G_BASE_IDX 2 4695 #define regCM1_CM_GAMCOR_RAMB_OFFSET_R 0x0ee0 4696 #define regCM1_CM_GAMCOR_RAMB_OFFSET_R_BASE_IDX 2 4697 #define regCM1_CM_GAMCOR_RAMB_REGION_0_1 0x0ee1 4698 #define regCM1_CM_GAMCOR_RAMB_REGION_0_1_BASE_IDX 2 4699 #define regCM1_CM_GAMCOR_RAMB_REGION_2_3 0x0ee2 4700 #define regCM1_CM_GAMCOR_RAMB_REGION_2_3_BASE_IDX 2 4701 #define regCM1_CM_GAMCOR_RAMB_REGION_4_5 0x0ee3 4702 #define regCM1_CM_GAMCOR_RAMB_REGION_4_5_BASE_IDX 2 4703 #define regCM1_CM_GAMCOR_RAMB_REGION_6_7 0x0ee4 4704 #define regCM1_CM_GAMCOR_RAMB_REGION_6_7_BASE_IDX 2 4705 #define regCM1_CM_GAMCOR_RAMB_REGION_8_9 0x0ee5 4706 #define regCM1_CM_GAMCOR_RAMB_REGION_8_9_BASE_IDX 2 4707 #define regCM1_CM_GAMCOR_RAMB_REGION_10_11 0x0ee6 4708 #define regCM1_CM_GAMCOR_RAMB_REGION_10_11_BASE_IDX 2 4709 #define regCM1_CM_GAMCOR_RAMB_REGION_12_13 0x0ee7 4710 #define regCM1_CM_GAMCOR_RAMB_REGION_12_13_BASE_IDX 2 4711 #define regCM1_CM_GAMCOR_RAMB_REGION_14_15 0x0ee8 4712 #define regCM1_CM_GAMCOR_RAMB_REGION_14_15_BASE_IDX 2 4713 #define regCM1_CM_GAMCOR_RAMB_REGION_16_17 0x0ee9 4714 #define regCM1_CM_GAMCOR_RAMB_REGION_16_17_BASE_IDX 2 4715 #define regCM1_CM_GAMCOR_RAMB_REGION_18_19 0x0eea 4716 #define regCM1_CM_GAMCOR_RAMB_REGION_18_19_BASE_IDX 2 4717 #define regCM1_CM_GAMCOR_RAMB_REGION_20_21 0x0eeb 4718 #define regCM1_CM_GAMCOR_RAMB_REGION_20_21_BASE_IDX 2 4719 #define regCM1_CM_GAMCOR_RAMB_REGION_22_23 0x0eec 4720 #define regCM1_CM_GAMCOR_RAMB_REGION_22_23_BASE_IDX 2 4721 #define regCM1_CM_GAMCOR_RAMB_REGION_24_25 0x0eed 4722 #define regCM1_CM_GAMCOR_RAMB_REGION_24_25_BASE_IDX 2 4723 #define regCM1_CM_GAMCOR_RAMB_REGION_26_27 0x0eee 4724 #define regCM1_CM_GAMCOR_RAMB_REGION_26_27_BASE_IDX 2 4725 #define regCM1_CM_GAMCOR_RAMB_REGION_28_29 0x0eef 4726 #define regCM1_CM_GAMCOR_RAMB_REGION_28_29_BASE_IDX 2 4727 #define regCM1_CM_GAMCOR_RAMB_REGION_30_31 0x0ef0 4728 #define regCM1_CM_GAMCOR_RAMB_REGION_30_31_BASE_IDX 2 4729 #define regCM1_CM_GAMCOR_RAMB_REGION_32_33 0x0ef1 4730 #define regCM1_CM_GAMCOR_RAMB_REGION_32_33_BASE_IDX 2 4731 #define regCM1_CM_BLNDGAM_CONTROL 0x0ef2 4732 #define regCM1_CM_BLNDGAM_CONTROL_BASE_IDX 2 4733 #define regCM1_CM_BLNDGAM_LUT_INDEX 0x0ef3 4734 #define regCM1_CM_BLNDGAM_LUT_INDEX_BASE_IDX 2 4735 #define regCM1_CM_BLNDGAM_LUT_DATA 0x0ef4 4736 #define regCM1_CM_BLNDGAM_LUT_DATA_BASE_IDX 2 4737 #define regCM1_CM_BLNDGAM_LUT_CONTROL 0x0ef5 4738 #define regCM1_CM_BLNDGAM_LUT_CONTROL_BASE_IDX 2 4739 #define regCM1_CM_BLNDGAM_RAMA_START_CNTL_B 0x0ef6 4740 #define regCM1_CM_BLNDGAM_RAMA_START_CNTL_B_BASE_IDX 2 4741 #define regCM1_CM_BLNDGAM_RAMA_START_CNTL_G 0x0ef7 4742 #define regCM1_CM_BLNDGAM_RAMA_START_CNTL_G_BASE_IDX 2 4743 #define regCM1_CM_BLNDGAM_RAMA_START_CNTL_R 0x0ef8 4744 #define regCM1_CM_BLNDGAM_RAMA_START_CNTL_R_BASE_IDX 2 4745 #define regCM1_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_B 0x0ef9 4746 #define regCM1_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_B_BASE_IDX 2 4747 #define regCM1_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_G 0x0efa 4748 #define regCM1_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_G_BASE_IDX 2 4749 #define regCM1_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_R 0x0efb 4750 #define regCM1_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_R_BASE_IDX 2 4751 #define regCM1_CM_BLNDGAM_RAMA_START_BASE_CNTL_B 0x0efc 4752 #define regCM1_CM_BLNDGAM_RAMA_START_BASE_CNTL_B_BASE_IDX 2 4753 #define regCM1_CM_BLNDGAM_RAMA_START_BASE_CNTL_G 0x0efd 4754 #define regCM1_CM_BLNDGAM_RAMA_START_BASE_CNTL_G_BASE_IDX 2 4755 #define regCM1_CM_BLNDGAM_RAMA_START_BASE_CNTL_R 0x0efe 4756 #define regCM1_CM_BLNDGAM_RAMA_START_BASE_CNTL_R_BASE_IDX 2 4757 #define regCM1_CM_BLNDGAM_RAMA_END_CNTL1_B 0x0eff 4758 #define regCM1_CM_BLNDGAM_RAMA_END_CNTL1_B_BASE_IDX 2 4759 #define regCM1_CM_BLNDGAM_RAMA_END_CNTL2_B 0x0f00 4760 #define regCM1_CM_BLNDGAM_RAMA_END_CNTL2_B_BASE_IDX 2 4761 #define regCM1_CM_BLNDGAM_RAMA_END_CNTL1_G 0x0f01 4762 #define regCM1_CM_BLNDGAM_RAMA_END_CNTL1_G_BASE_IDX 2 4763 #define regCM1_CM_BLNDGAM_RAMA_END_CNTL2_G 0x0f02 4764 #define regCM1_CM_BLNDGAM_RAMA_END_CNTL2_G_BASE_IDX 2 4765 #define regCM1_CM_BLNDGAM_RAMA_END_CNTL1_R 0x0f03 4766 #define regCM1_CM_BLNDGAM_RAMA_END_CNTL1_R_BASE_IDX 2 4767 #define regCM1_CM_BLNDGAM_RAMA_END_CNTL2_R 0x0f04 4768 #define regCM1_CM_BLNDGAM_RAMA_END_CNTL2_R_BASE_IDX 2 4769 #define regCM1_CM_BLNDGAM_RAMA_OFFSET_B 0x0f05 4770 #define regCM1_CM_BLNDGAM_RAMA_OFFSET_B_BASE_IDX 2 4771 #define regCM1_CM_BLNDGAM_RAMA_OFFSET_G 0x0f06 4772 #define regCM1_CM_BLNDGAM_RAMA_OFFSET_G_BASE_IDX 2 4773 #define regCM1_CM_BLNDGAM_RAMA_OFFSET_R 0x0f07 4774 #define regCM1_CM_BLNDGAM_RAMA_OFFSET_R_BASE_IDX 2 4775 #define regCM1_CM_BLNDGAM_RAMA_REGION_0_1 0x0f08 4776 #define regCM1_CM_BLNDGAM_RAMA_REGION_0_1_BASE_IDX 2 4777 #define regCM1_CM_BLNDGAM_RAMA_REGION_2_3 0x0f09 4778 #define regCM1_CM_BLNDGAM_RAMA_REGION_2_3_BASE_IDX 2 4779 #define regCM1_CM_BLNDGAM_RAMA_REGION_4_5 0x0f0a 4780 #define regCM1_CM_BLNDGAM_RAMA_REGION_4_5_BASE_IDX 2 4781 #define regCM1_CM_BLNDGAM_RAMA_REGION_6_7 0x0f0b 4782 #define regCM1_CM_BLNDGAM_RAMA_REGION_6_7_BASE_IDX 2 4783 #define regCM1_CM_BLNDGAM_RAMA_REGION_8_9 0x0f0c 4784 #define regCM1_CM_BLNDGAM_RAMA_REGION_8_9_BASE_IDX 2 4785 #define regCM1_CM_BLNDGAM_RAMA_REGION_10_11 0x0f0d 4786 #define regCM1_CM_BLNDGAM_RAMA_REGION_10_11_BASE_IDX 2 4787 #define regCM1_CM_BLNDGAM_RAMA_REGION_12_13 0x0f0e 4788 #define regCM1_CM_BLNDGAM_RAMA_REGION_12_13_BASE_IDX 2 4789 #define regCM1_CM_BLNDGAM_RAMA_REGION_14_15 0x0f0f 4790 #define regCM1_CM_BLNDGAM_RAMA_REGION_14_15_BASE_IDX 2 4791 #define regCM1_CM_BLNDGAM_RAMA_REGION_16_17 0x0f10 4792 #define regCM1_CM_BLNDGAM_RAMA_REGION_16_17_BASE_IDX 2 4793 #define regCM1_CM_BLNDGAM_RAMA_REGION_18_19 0x0f11 4794 #define regCM1_CM_BLNDGAM_RAMA_REGION_18_19_BASE_IDX 2 4795 #define regCM1_CM_BLNDGAM_RAMA_REGION_20_21 0x0f12 4796 #define regCM1_CM_BLNDGAM_RAMA_REGION_20_21_BASE_IDX 2 4797 #define regCM1_CM_BLNDGAM_RAMA_REGION_22_23 0x0f13 4798 #define regCM1_CM_BLNDGAM_RAMA_REGION_22_23_BASE_IDX 2 4799 #define regCM1_CM_BLNDGAM_RAMA_REGION_24_25 0x0f14 4800 #define regCM1_CM_BLNDGAM_RAMA_REGION_24_25_BASE_IDX 2 4801 #define regCM1_CM_BLNDGAM_RAMA_REGION_26_27 0x0f15 4802 #define regCM1_CM_BLNDGAM_RAMA_REGION_26_27_BASE_IDX 2 4803 #define regCM1_CM_BLNDGAM_RAMA_REGION_28_29 0x0f16 4804 #define regCM1_CM_BLNDGAM_RAMA_REGION_28_29_BASE_IDX 2 4805 #define regCM1_CM_BLNDGAM_RAMA_REGION_30_31 0x0f17 4806 #define regCM1_CM_BLNDGAM_RAMA_REGION_30_31_BASE_IDX 2 4807 #define regCM1_CM_BLNDGAM_RAMA_REGION_32_33 0x0f18 4808 #define regCM1_CM_BLNDGAM_RAMA_REGION_32_33_BASE_IDX 2 4809 #define regCM1_CM_BLNDGAM_RAMB_START_CNTL_B 0x0f19 4810 #define regCM1_CM_BLNDGAM_RAMB_START_CNTL_B_BASE_IDX 2 4811 #define regCM1_CM_BLNDGAM_RAMB_START_CNTL_G 0x0f1a 4812 #define regCM1_CM_BLNDGAM_RAMB_START_CNTL_G_BASE_IDX 2 4813 #define regCM1_CM_BLNDGAM_RAMB_START_CNTL_R 0x0f1b 4814 #define regCM1_CM_BLNDGAM_RAMB_START_CNTL_R_BASE_IDX 2 4815 #define regCM1_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_B 0x0f1c 4816 #define regCM1_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_B_BASE_IDX 2 4817 #define regCM1_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_G 0x0f1d 4818 #define regCM1_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_G_BASE_IDX 2 4819 #define regCM1_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_R 0x0f1e 4820 #define regCM1_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_R_BASE_IDX 2 4821 #define regCM1_CM_BLNDGAM_RAMB_START_BASE_CNTL_B 0x0f1f 4822 #define regCM1_CM_BLNDGAM_RAMB_START_BASE_CNTL_B_BASE_IDX 2 4823 #define regCM1_CM_BLNDGAM_RAMB_START_BASE_CNTL_G 0x0f20 4824 #define regCM1_CM_BLNDGAM_RAMB_START_BASE_CNTL_G_BASE_IDX 2 4825 #define regCM1_CM_BLNDGAM_RAMB_START_BASE_CNTL_R 0x0f21 4826 #define regCM1_CM_BLNDGAM_RAMB_START_BASE_CNTL_R_BASE_IDX 2 4827 #define regCM1_CM_BLNDGAM_RAMB_END_CNTL1_B 0x0f22 4828 #define regCM1_CM_BLNDGAM_RAMB_END_CNTL1_B_BASE_IDX 2 4829 #define regCM1_CM_BLNDGAM_RAMB_END_CNTL2_B 0x0f23 4830 #define regCM1_CM_BLNDGAM_RAMB_END_CNTL2_B_BASE_IDX 2 4831 #define regCM1_CM_BLNDGAM_RAMB_END_CNTL1_G 0x0f24 4832 #define regCM1_CM_BLNDGAM_RAMB_END_CNTL1_G_BASE_IDX 2 4833 #define regCM1_CM_BLNDGAM_RAMB_END_CNTL2_G 0x0f25 4834 #define regCM1_CM_BLNDGAM_RAMB_END_CNTL2_G_BASE_IDX 2 4835 #define regCM1_CM_BLNDGAM_RAMB_END_CNTL1_R 0x0f26 4836 #define regCM1_CM_BLNDGAM_RAMB_END_CNTL1_R_BASE_IDX 2 4837 #define regCM1_CM_BLNDGAM_RAMB_END_CNTL2_R 0x0f27 4838 #define regCM1_CM_BLNDGAM_RAMB_END_CNTL2_R_BASE_IDX 2 4839 #define regCM1_CM_BLNDGAM_RAMB_OFFSET_B 0x0f28 4840 #define regCM1_CM_BLNDGAM_RAMB_OFFSET_B_BASE_IDX 2 4841 #define regCM1_CM_BLNDGAM_RAMB_OFFSET_G 0x0f29 4842 #define regCM1_CM_BLNDGAM_RAMB_OFFSET_G_BASE_IDX 2 4843 #define regCM1_CM_BLNDGAM_RAMB_OFFSET_R 0x0f2a 4844 #define regCM1_CM_BLNDGAM_RAMB_OFFSET_R_BASE_IDX 2 4845 #define regCM1_CM_BLNDGAM_RAMB_REGION_0_1 0x0f2b 4846 #define regCM1_CM_BLNDGAM_RAMB_REGION_0_1_BASE_IDX 2 4847 #define regCM1_CM_BLNDGAM_RAMB_REGION_2_3 0x0f2c 4848 #define regCM1_CM_BLNDGAM_RAMB_REGION_2_3_BASE_IDX 2 4849 #define regCM1_CM_BLNDGAM_RAMB_REGION_4_5 0x0f2d 4850 #define regCM1_CM_BLNDGAM_RAMB_REGION_4_5_BASE_IDX 2 4851 #define regCM1_CM_BLNDGAM_RAMB_REGION_6_7 0x0f2e 4852 #define regCM1_CM_BLNDGAM_RAMB_REGION_6_7_BASE_IDX 2 4853 #define regCM1_CM_BLNDGAM_RAMB_REGION_8_9 0x0f2f 4854 #define regCM1_CM_BLNDGAM_RAMB_REGION_8_9_BASE_IDX 2 4855 #define regCM1_CM_BLNDGAM_RAMB_REGION_10_11 0x0f30 4856 #define regCM1_CM_BLNDGAM_RAMB_REGION_10_11_BASE_IDX 2 4857 #define regCM1_CM_BLNDGAM_RAMB_REGION_12_13 0x0f31 4858 #define regCM1_CM_BLNDGAM_RAMB_REGION_12_13_BASE_IDX 2 4859 #define regCM1_CM_BLNDGAM_RAMB_REGION_14_15 0x0f32 4860 #define regCM1_CM_BLNDGAM_RAMB_REGION_14_15_BASE_IDX 2 4861 #define regCM1_CM_BLNDGAM_RAMB_REGION_16_17 0x0f33 4862 #define regCM1_CM_BLNDGAM_RAMB_REGION_16_17_BASE_IDX 2 4863 #define regCM1_CM_BLNDGAM_RAMB_REGION_18_19 0x0f34 4864 #define regCM1_CM_BLNDGAM_RAMB_REGION_18_19_BASE_IDX 2 4865 #define regCM1_CM_BLNDGAM_RAMB_REGION_20_21 0x0f35 4866 #define regCM1_CM_BLNDGAM_RAMB_REGION_20_21_BASE_IDX 2 4867 #define regCM1_CM_BLNDGAM_RAMB_REGION_22_23 0x0f36 4868 #define regCM1_CM_BLNDGAM_RAMB_REGION_22_23_BASE_IDX 2 4869 #define regCM1_CM_BLNDGAM_RAMB_REGION_24_25 0x0f37 4870 #define regCM1_CM_BLNDGAM_RAMB_REGION_24_25_BASE_IDX 2 4871 #define regCM1_CM_BLNDGAM_RAMB_REGION_26_27 0x0f38 4872 #define regCM1_CM_BLNDGAM_RAMB_REGION_26_27_BASE_IDX 2 4873 #define regCM1_CM_BLNDGAM_RAMB_REGION_28_29 0x0f39 4874 #define regCM1_CM_BLNDGAM_RAMB_REGION_28_29_BASE_IDX 2 4875 #define regCM1_CM_BLNDGAM_RAMB_REGION_30_31 0x0f3a 4876 #define regCM1_CM_BLNDGAM_RAMB_REGION_30_31_BASE_IDX 2 4877 #define regCM1_CM_BLNDGAM_RAMB_REGION_32_33 0x0f3b 4878 #define regCM1_CM_BLNDGAM_RAMB_REGION_32_33_BASE_IDX 2 4879 #define regCM1_CM_HDR_MULT_COEF 0x0f3c 4880 #define regCM1_CM_HDR_MULT_COEF_BASE_IDX 2 4881 #define regCM1_CM_MEM_PWR_CTRL 0x0f3d 4882 #define regCM1_CM_MEM_PWR_CTRL_BASE_IDX 2 4883 #define regCM1_CM_MEM_PWR_STATUS 0x0f3e 4884 #define regCM1_CM_MEM_PWR_STATUS_BASE_IDX 2 4885 #define regCM1_CM_DEALPHA 0x0f40 4886 #define regCM1_CM_DEALPHA_BASE_IDX 2 4887 #define regCM1_CM_COEF_FORMAT 0x0f41 4888 #define regCM1_CM_COEF_FORMAT_BASE_IDX 2 4889 #define regCM1_CM_SHAPER_CONTROL 0x0f42 4890 #define regCM1_CM_SHAPER_CONTROL_BASE_IDX 2 4891 #define regCM1_CM_SHAPER_OFFSET_R 0x0f43 4892 #define regCM1_CM_SHAPER_OFFSET_R_BASE_IDX 2 4893 #define regCM1_CM_SHAPER_OFFSET_G 0x0f44 4894 #define regCM1_CM_SHAPER_OFFSET_G_BASE_IDX 2 4895 #define regCM1_CM_SHAPER_OFFSET_B 0x0f45 4896 #define regCM1_CM_SHAPER_OFFSET_B_BASE_IDX 2 4897 #define regCM1_CM_SHAPER_SCALE_R 0x0f46 4898 #define regCM1_CM_SHAPER_SCALE_R_BASE_IDX 2 4899 #define regCM1_CM_SHAPER_SCALE_G_B 0x0f47 4900 #define regCM1_CM_SHAPER_SCALE_G_B_BASE_IDX 2 4901 #define regCM1_CM_SHAPER_LUT_INDEX 0x0f48 4902 #define regCM1_CM_SHAPER_LUT_INDEX_BASE_IDX 2 4903 #define regCM1_CM_SHAPER_LUT_DATA 0x0f49 4904 #define regCM1_CM_SHAPER_LUT_DATA_BASE_IDX 2 4905 #define regCM1_CM_SHAPER_LUT_WRITE_EN_MASK 0x0f4a 4906 #define regCM1_CM_SHAPER_LUT_WRITE_EN_MASK_BASE_IDX 2 4907 #define regCM1_CM_SHAPER_RAMA_START_CNTL_B 0x0f4b 4908 #define regCM1_CM_SHAPER_RAMA_START_CNTL_B_BASE_IDX 2 4909 #define regCM1_CM_SHAPER_RAMA_START_CNTL_G 0x0f4c 4910 #define regCM1_CM_SHAPER_RAMA_START_CNTL_G_BASE_IDX 2 4911 #define regCM1_CM_SHAPER_RAMA_START_CNTL_R 0x0f4d 4912 #define regCM1_CM_SHAPER_RAMA_START_CNTL_R_BASE_IDX 2 4913 #define regCM1_CM_SHAPER_RAMA_END_CNTL_B 0x0f4e 4914 #define regCM1_CM_SHAPER_RAMA_END_CNTL_B_BASE_IDX 2 4915 #define regCM1_CM_SHAPER_RAMA_END_CNTL_G 0x0f4f 4916 #define regCM1_CM_SHAPER_RAMA_END_CNTL_G_BASE_IDX 2 4917 #define regCM1_CM_SHAPER_RAMA_END_CNTL_R 0x0f50 4918 #define regCM1_CM_SHAPER_RAMA_END_CNTL_R_BASE_IDX 2 4919 #define regCM1_CM_SHAPER_RAMA_REGION_0_1 0x0f51 4920 #define regCM1_CM_SHAPER_RAMA_REGION_0_1_BASE_IDX 2 4921 #define regCM1_CM_SHAPER_RAMA_REGION_2_3 0x0f52 4922 #define regCM1_CM_SHAPER_RAMA_REGION_2_3_BASE_IDX 2 4923 #define regCM1_CM_SHAPER_RAMA_REGION_4_5 0x0f53 4924 #define regCM1_CM_SHAPER_RAMA_REGION_4_5_BASE_IDX 2 4925 #define regCM1_CM_SHAPER_RAMA_REGION_6_7 0x0f54 4926 #define regCM1_CM_SHAPER_RAMA_REGION_6_7_BASE_IDX 2 4927 #define regCM1_CM_SHAPER_RAMA_REGION_8_9 0x0f55 4928 #define regCM1_CM_SHAPER_RAMA_REGION_8_9_BASE_IDX 2 4929 #define regCM1_CM_SHAPER_RAMA_REGION_10_11 0x0f56 4930 #define regCM1_CM_SHAPER_RAMA_REGION_10_11_BASE_IDX 2 4931 #define regCM1_CM_SHAPER_RAMA_REGION_12_13 0x0f57 4932 #define regCM1_CM_SHAPER_RAMA_REGION_12_13_BASE_IDX 2 4933 #define regCM1_CM_SHAPER_RAMA_REGION_14_15 0x0f58 4934 #define regCM1_CM_SHAPER_RAMA_REGION_14_15_BASE_IDX 2 4935 #define regCM1_CM_SHAPER_RAMA_REGION_16_17 0x0f59 4936 #define regCM1_CM_SHAPER_RAMA_REGION_16_17_BASE_IDX 2 4937 #define regCM1_CM_SHAPER_RAMA_REGION_18_19 0x0f5a 4938 #define regCM1_CM_SHAPER_RAMA_REGION_18_19_BASE_IDX 2 4939 #define regCM1_CM_SHAPER_RAMA_REGION_20_21 0x0f5b 4940 #define regCM1_CM_SHAPER_RAMA_REGION_20_21_BASE_IDX 2 4941 #define regCM1_CM_SHAPER_RAMA_REGION_22_23 0x0f5c 4942 #define regCM1_CM_SHAPER_RAMA_REGION_22_23_BASE_IDX 2 4943 #define regCM1_CM_SHAPER_RAMA_REGION_24_25 0x0f5d 4944 #define regCM1_CM_SHAPER_RAMA_REGION_24_25_BASE_IDX 2 4945 #define regCM1_CM_SHAPER_RAMA_REGION_26_27 0x0f5e 4946 #define regCM1_CM_SHAPER_RAMA_REGION_26_27_BASE_IDX 2 4947 #define regCM1_CM_SHAPER_RAMA_REGION_28_29 0x0f5f 4948 #define regCM1_CM_SHAPER_RAMA_REGION_28_29_BASE_IDX 2 4949 #define regCM1_CM_SHAPER_RAMA_REGION_30_31 0x0f60 4950 #define regCM1_CM_SHAPER_RAMA_REGION_30_31_BASE_IDX 2 4951 #define regCM1_CM_SHAPER_RAMA_REGION_32_33 0x0f61 4952 #define regCM1_CM_SHAPER_RAMA_REGION_32_33_BASE_IDX 2 4953 #define regCM1_CM_SHAPER_RAMB_START_CNTL_B 0x0f62 4954 #define regCM1_CM_SHAPER_RAMB_START_CNTL_B_BASE_IDX 2 4955 #define regCM1_CM_SHAPER_RAMB_START_CNTL_G 0x0f63 4956 #define regCM1_CM_SHAPER_RAMB_START_CNTL_G_BASE_IDX 2 4957 #define regCM1_CM_SHAPER_RAMB_START_CNTL_R 0x0f64 4958 #define regCM1_CM_SHAPER_RAMB_START_CNTL_R_BASE_IDX 2 4959 #define regCM1_CM_SHAPER_RAMB_END_CNTL_B 0x0f65 4960 #define regCM1_CM_SHAPER_RAMB_END_CNTL_B_BASE_IDX 2 4961 #define regCM1_CM_SHAPER_RAMB_END_CNTL_G 0x0f66 4962 #define regCM1_CM_SHAPER_RAMB_END_CNTL_G_BASE_IDX 2 4963 #define regCM1_CM_SHAPER_RAMB_END_CNTL_R 0x0f67 4964 #define regCM1_CM_SHAPER_RAMB_END_CNTL_R_BASE_IDX 2 4965 #define regCM1_CM_SHAPER_RAMB_REGION_0_1 0x0f68 4966 #define regCM1_CM_SHAPER_RAMB_REGION_0_1_BASE_IDX 2 4967 #define regCM1_CM_SHAPER_RAMB_REGION_2_3 0x0f69 4968 #define regCM1_CM_SHAPER_RAMB_REGION_2_3_BASE_IDX 2 4969 #define regCM1_CM_SHAPER_RAMB_REGION_4_5 0x0f6a 4970 #define regCM1_CM_SHAPER_RAMB_REGION_4_5_BASE_IDX 2 4971 #define regCM1_CM_SHAPER_RAMB_REGION_6_7 0x0f6b 4972 #define regCM1_CM_SHAPER_RAMB_REGION_6_7_BASE_IDX 2 4973 #define regCM1_CM_SHAPER_RAMB_REGION_8_9 0x0f6c 4974 #define regCM1_CM_SHAPER_RAMB_REGION_8_9_BASE_IDX 2 4975 #define regCM1_CM_SHAPER_RAMB_REGION_10_11 0x0f6d 4976 #define regCM1_CM_SHAPER_RAMB_REGION_10_11_BASE_IDX 2 4977 #define regCM1_CM_SHAPER_RAMB_REGION_12_13 0x0f6e 4978 #define regCM1_CM_SHAPER_RAMB_REGION_12_13_BASE_IDX 2 4979 #define regCM1_CM_SHAPER_RAMB_REGION_14_15 0x0f6f 4980 #define regCM1_CM_SHAPER_RAMB_REGION_14_15_BASE_IDX 2 4981 #define regCM1_CM_SHAPER_RAMB_REGION_16_17 0x0f70 4982 #define regCM1_CM_SHAPER_RAMB_REGION_16_17_BASE_IDX 2 4983 #define regCM1_CM_SHAPER_RAMB_REGION_18_19 0x0f71 4984 #define regCM1_CM_SHAPER_RAMB_REGION_18_19_BASE_IDX 2 4985 #define regCM1_CM_SHAPER_RAMB_REGION_20_21 0x0f72 4986 #define regCM1_CM_SHAPER_RAMB_REGION_20_21_BASE_IDX 2 4987 #define regCM1_CM_SHAPER_RAMB_REGION_22_23 0x0f73 4988 #define regCM1_CM_SHAPER_RAMB_REGION_22_23_BASE_IDX 2 4989 #define regCM1_CM_SHAPER_RAMB_REGION_24_25 0x0f74 4990 #define regCM1_CM_SHAPER_RAMB_REGION_24_25_BASE_IDX 2 4991 #define regCM1_CM_SHAPER_RAMB_REGION_26_27 0x0f75 4992 #define regCM1_CM_SHAPER_RAMB_REGION_26_27_BASE_IDX 2 4993 #define regCM1_CM_SHAPER_RAMB_REGION_28_29 0x0f76 4994 #define regCM1_CM_SHAPER_RAMB_REGION_28_29_BASE_IDX 2 4995 #define regCM1_CM_SHAPER_RAMB_REGION_30_31 0x0f77 4996 #define regCM1_CM_SHAPER_RAMB_REGION_30_31_BASE_IDX 2 4997 #define regCM1_CM_SHAPER_RAMB_REGION_32_33 0x0f78 4998 #define regCM1_CM_SHAPER_RAMB_REGION_32_33_BASE_IDX 2 4999 #define regCM1_CM_MEM_PWR_CTRL2 0x0f79 5000 #define regCM1_CM_MEM_PWR_CTRL2_BASE_IDX 2 5001 #define regCM1_CM_MEM_PWR_STATUS2 0x0f7a 5002 #define regCM1_CM_MEM_PWR_STATUS2_BASE_IDX 2 5003 #define regCM1_CM_3DLUT_MODE 0x0f7b 5004 #define regCM1_CM_3DLUT_MODE_BASE_IDX 2 5005 #define regCM1_CM_3DLUT_INDEX 0x0f7c 5006 #define regCM1_CM_3DLUT_INDEX_BASE_IDX 2 5007 #define regCM1_CM_3DLUT_DATA 0x0f7d 5008 #define regCM1_CM_3DLUT_DATA_BASE_IDX 2 5009 #define regCM1_CM_3DLUT_DATA_30BIT 0x0f7e 5010 #define regCM1_CM_3DLUT_DATA_30BIT_BASE_IDX 2 5011 #define regCM1_CM_3DLUT_READ_WRITE_CONTROL 0x0f7f 5012 #define regCM1_CM_3DLUT_READ_WRITE_CONTROL_BASE_IDX 2 5013 #define regCM1_CM_3DLUT_OUT_NORM_FACTOR 0x0f80 5014 #define regCM1_CM_3DLUT_OUT_NORM_FACTOR_BASE_IDX 2 5015 #define regCM1_CM_3DLUT_OUT_OFFSET_R 0x0f81 5016 #define regCM1_CM_3DLUT_OUT_OFFSET_R_BASE_IDX 2 5017 #define regCM1_CM_3DLUT_OUT_OFFSET_G 0x0f82 5018 #define regCM1_CM_3DLUT_OUT_OFFSET_G_BASE_IDX 2 5019 #define regCM1_CM_3DLUT_OUT_OFFSET_B 0x0f83 5020 #define regCM1_CM_3DLUT_OUT_OFFSET_B_BASE_IDX 2 5021 #define regCM1_CM_TEST_DEBUG_INDEX 0x0f84 5022 #define regCM1_CM_TEST_DEBUG_INDEX_BASE_IDX 2 5023 #define regCM1_CM_TEST_DEBUG_DATA 0x0f85 5024 #define regCM1_CM_TEST_DEBUG_DATA_BASE_IDX 2 5025 5026 5027 // addressBlock: dce_dc_dpp1_dispdec_dpp_top_dispdec 5028 // base address: 0x5ac 5029 #define regDPP_TOP1_DPP_CONTROL 0x0e30 5030 #define regDPP_TOP1_DPP_CONTROL_BASE_IDX 2 5031 #define regDPP_TOP1_DPP_SOFT_RESET 0x0e31 5032 #define regDPP_TOP1_DPP_SOFT_RESET_BASE_IDX 2 5033 #define regDPP_TOP1_DPP_CRC_VAL_R_G 0x0e32 5034 #define regDPP_TOP1_DPP_CRC_VAL_R_G_BASE_IDX 2 5035 #define regDPP_TOP1_DPP_CRC_VAL_B_A 0x0e33 5036 #define regDPP_TOP1_DPP_CRC_VAL_B_A_BASE_IDX 2 5037 #define regDPP_TOP1_DPP_CRC_CTRL 0x0e34 5038 #define regDPP_TOP1_DPP_CRC_CTRL_BASE_IDX 2 5039 #define regDPP_TOP1_HOST_READ_CONTROL 0x0e35 5040 #define regDPP_TOP1_HOST_READ_CONTROL_BASE_IDX 2 5041 5042 5043 // addressBlock: dce_dc_dpp1_dispdec_dpp_dcperfmon_dc_perfmon_dispdec 5044 // base address: 0x3e3c 5045 #define regDC_PERFMON12_PERFCOUNTER_CNTL 0x0f8f 5046 #define regDC_PERFMON12_PERFCOUNTER_CNTL_BASE_IDX 2 5047 #define regDC_PERFMON12_PERFCOUNTER_CNTL2 0x0f90 5048 #define regDC_PERFMON12_PERFCOUNTER_CNTL2_BASE_IDX 2 5049 #define regDC_PERFMON12_PERFCOUNTER_STATE 0x0f91 5050 #define regDC_PERFMON12_PERFCOUNTER_STATE_BASE_IDX 2 5051 #define regDC_PERFMON12_PERFMON_CNTL 0x0f92 5052 #define regDC_PERFMON12_PERFMON_CNTL_BASE_IDX 2 5053 #define regDC_PERFMON12_PERFMON_CNTL2 0x0f93 5054 #define regDC_PERFMON12_PERFMON_CNTL2_BASE_IDX 2 5055 #define regDC_PERFMON12_PERFMON_CVALUE_INT_MISC 0x0f94 5056 #define regDC_PERFMON12_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 5057 #define regDC_PERFMON12_PERFMON_CVALUE_LOW 0x0f95 5058 #define regDC_PERFMON12_PERFMON_CVALUE_LOW_BASE_IDX 2 5059 #define regDC_PERFMON12_PERFMON_HI 0x0f96 5060 #define regDC_PERFMON12_PERFMON_HI_BASE_IDX 2 5061 #define regDC_PERFMON12_PERFMON_LOW 0x0f97 5062 #define regDC_PERFMON12_PERFMON_LOW_BASE_IDX 2 5063 5064 5065 // addressBlock: dce_dc_dpp2_dispdec_cnvc_cfg_dispdec 5066 // base address: 0xb58 5067 #define regCNVC_CFG2_CNVC_SURFACE_PIXEL_FORMAT 0x0fa5 5068 #define regCNVC_CFG2_CNVC_SURFACE_PIXEL_FORMAT_BASE_IDX 2 5069 #define regCNVC_CFG2_FORMAT_CONTROL 0x0fa6 5070 #define regCNVC_CFG2_FORMAT_CONTROL_BASE_IDX 2 5071 #define regCNVC_CFG2_FCNV_FP_BIAS_R 0x0fa7 5072 #define regCNVC_CFG2_FCNV_FP_BIAS_R_BASE_IDX 2 5073 #define regCNVC_CFG2_FCNV_FP_BIAS_G 0x0fa8 5074 #define regCNVC_CFG2_FCNV_FP_BIAS_G_BASE_IDX 2 5075 #define regCNVC_CFG2_FCNV_FP_BIAS_B 0x0fa9 5076 #define regCNVC_CFG2_FCNV_FP_BIAS_B_BASE_IDX 2 5077 #define regCNVC_CFG2_FCNV_FP_SCALE_R 0x0faa 5078 #define regCNVC_CFG2_FCNV_FP_SCALE_R_BASE_IDX 2 5079 #define regCNVC_CFG2_FCNV_FP_SCALE_G 0x0fab 5080 #define regCNVC_CFG2_FCNV_FP_SCALE_G_BASE_IDX 2 5081 #define regCNVC_CFG2_FCNV_FP_SCALE_B 0x0fac 5082 #define regCNVC_CFG2_FCNV_FP_SCALE_B_BASE_IDX 2 5083 #define regCNVC_CFG2_COLOR_KEYER_CONTROL 0x0fad 5084 #define regCNVC_CFG2_COLOR_KEYER_CONTROL_BASE_IDX 2 5085 #define regCNVC_CFG2_COLOR_KEYER_ALPHA 0x0fae 5086 #define regCNVC_CFG2_COLOR_KEYER_ALPHA_BASE_IDX 2 5087 #define regCNVC_CFG2_COLOR_KEYER_RED 0x0faf 5088 #define regCNVC_CFG2_COLOR_KEYER_RED_BASE_IDX 2 5089 #define regCNVC_CFG2_COLOR_KEYER_GREEN 0x0fb0 5090 #define regCNVC_CFG2_COLOR_KEYER_GREEN_BASE_IDX 2 5091 #define regCNVC_CFG2_COLOR_KEYER_BLUE 0x0fb1 5092 #define regCNVC_CFG2_COLOR_KEYER_BLUE_BASE_IDX 2 5093 #define regCNVC_CFG2_ALPHA_2BIT_LUT 0x0fb3 5094 #define regCNVC_CFG2_ALPHA_2BIT_LUT_BASE_IDX 2 5095 #define regCNVC_CFG2_PRE_DEALPHA 0x0fb4 5096 #define regCNVC_CFG2_PRE_DEALPHA_BASE_IDX 2 5097 #define regCNVC_CFG2_PRE_CSC_MODE 0x0fb5 5098 #define regCNVC_CFG2_PRE_CSC_MODE_BASE_IDX 2 5099 #define regCNVC_CFG2_PRE_CSC_C11_C12 0x0fb6 5100 #define regCNVC_CFG2_PRE_CSC_C11_C12_BASE_IDX 2 5101 #define regCNVC_CFG2_PRE_CSC_C13_C14 0x0fb7 5102 #define regCNVC_CFG2_PRE_CSC_C13_C14_BASE_IDX 2 5103 #define regCNVC_CFG2_PRE_CSC_C21_C22 0x0fb8 5104 #define regCNVC_CFG2_PRE_CSC_C21_C22_BASE_IDX 2 5105 #define regCNVC_CFG2_PRE_CSC_C23_C24 0x0fb9 5106 #define regCNVC_CFG2_PRE_CSC_C23_C24_BASE_IDX 2 5107 #define regCNVC_CFG2_PRE_CSC_C31_C32 0x0fba 5108 #define regCNVC_CFG2_PRE_CSC_C31_C32_BASE_IDX 2 5109 #define regCNVC_CFG2_PRE_CSC_C33_C34 0x0fbb 5110 #define regCNVC_CFG2_PRE_CSC_C33_C34_BASE_IDX 2 5111 #define regCNVC_CFG2_PRE_CSC_B_C11_C12 0x0fbc 5112 #define regCNVC_CFG2_PRE_CSC_B_C11_C12_BASE_IDX 2 5113 #define regCNVC_CFG2_PRE_CSC_B_C13_C14 0x0fbd 5114 #define regCNVC_CFG2_PRE_CSC_B_C13_C14_BASE_IDX 2 5115 #define regCNVC_CFG2_PRE_CSC_B_C21_C22 0x0fbe 5116 #define regCNVC_CFG2_PRE_CSC_B_C21_C22_BASE_IDX 2 5117 #define regCNVC_CFG2_PRE_CSC_B_C23_C24 0x0fbf 5118 #define regCNVC_CFG2_PRE_CSC_B_C23_C24_BASE_IDX 2 5119 #define regCNVC_CFG2_PRE_CSC_B_C31_C32 0x0fc0 5120 #define regCNVC_CFG2_PRE_CSC_B_C31_C32_BASE_IDX 2 5121 #define regCNVC_CFG2_PRE_CSC_B_C33_C34 0x0fc1 5122 #define regCNVC_CFG2_PRE_CSC_B_C33_C34_BASE_IDX 2 5123 #define regCNVC_CFG2_CNVC_COEF_FORMAT 0x0fc2 5124 #define regCNVC_CFG2_CNVC_COEF_FORMAT_BASE_IDX 2 5125 #define regCNVC_CFG2_PRE_DEGAM 0x0fc3 5126 #define regCNVC_CFG2_PRE_DEGAM_BASE_IDX 2 5127 #define regCNVC_CFG2_PRE_REALPHA 0x0fc4 5128 #define regCNVC_CFG2_PRE_REALPHA_BASE_IDX 2 5129 5130 5131 // addressBlock: dce_dc_dpp2_dispdec_cnvc_cur_dispdec 5132 // base address: 0xb58 5133 #define regCNVC_CUR2_CURSOR0_CONTROL 0x0fc7 5134 #define regCNVC_CUR2_CURSOR0_CONTROL_BASE_IDX 2 5135 #define regCNVC_CUR2_CURSOR0_COLOR0 0x0fc8 5136 #define regCNVC_CUR2_CURSOR0_COLOR0_BASE_IDX 2 5137 #define regCNVC_CUR2_CURSOR0_COLOR1 0x0fc9 5138 #define regCNVC_CUR2_CURSOR0_COLOR1_BASE_IDX 2 5139 #define regCNVC_CUR2_CURSOR0_FP_SCALE_BIAS 0x0fca 5140 #define regCNVC_CUR2_CURSOR0_FP_SCALE_BIAS_BASE_IDX 2 5141 5142 5143 // addressBlock: dce_dc_dpp2_dispdec_dscl_dispdec 5144 // base address: 0xb58 5145 #define regDSCL2_SCL_COEF_RAM_TAP_SELECT 0x0fcf 5146 #define regDSCL2_SCL_COEF_RAM_TAP_SELECT_BASE_IDX 2 5147 #define regDSCL2_SCL_COEF_RAM_TAP_DATA 0x0fd0 5148 #define regDSCL2_SCL_COEF_RAM_TAP_DATA_BASE_IDX 2 5149 #define regDSCL2_SCL_MODE 0x0fd1 5150 #define regDSCL2_SCL_MODE_BASE_IDX 2 5151 #define regDSCL2_SCL_TAP_CONTROL 0x0fd2 5152 #define regDSCL2_SCL_TAP_CONTROL_BASE_IDX 2 5153 #define regDSCL2_DSCL_CONTROL 0x0fd3 5154 #define regDSCL2_DSCL_CONTROL_BASE_IDX 2 5155 #define regDSCL2_DSCL_2TAP_CONTROL 0x0fd4 5156 #define regDSCL2_DSCL_2TAP_CONTROL_BASE_IDX 2 5157 #define regDSCL2_SCL_MANUAL_REPLICATE_CONTROL 0x0fd5 5158 #define regDSCL2_SCL_MANUAL_REPLICATE_CONTROL_BASE_IDX 2 5159 #define regDSCL2_SCL_HORZ_FILTER_SCALE_RATIO 0x0fd6 5160 #define regDSCL2_SCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX 2 5161 #define regDSCL2_SCL_HORZ_FILTER_INIT 0x0fd7 5162 #define regDSCL2_SCL_HORZ_FILTER_INIT_BASE_IDX 2 5163 #define regDSCL2_SCL_HORZ_FILTER_SCALE_RATIO_C 0x0fd8 5164 #define regDSCL2_SCL_HORZ_FILTER_SCALE_RATIO_C_BASE_IDX 2 5165 #define regDSCL2_SCL_HORZ_FILTER_INIT_C 0x0fd9 5166 #define regDSCL2_SCL_HORZ_FILTER_INIT_C_BASE_IDX 2 5167 #define regDSCL2_SCL_VERT_FILTER_SCALE_RATIO 0x0fda 5168 #define regDSCL2_SCL_VERT_FILTER_SCALE_RATIO_BASE_IDX 2 5169 #define regDSCL2_SCL_VERT_FILTER_INIT 0x0fdb 5170 #define regDSCL2_SCL_VERT_FILTER_INIT_BASE_IDX 2 5171 #define regDSCL2_SCL_VERT_FILTER_INIT_BOT 0x0fdc 5172 #define regDSCL2_SCL_VERT_FILTER_INIT_BOT_BASE_IDX 2 5173 #define regDSCL2_SCL_VERT_FILTER_SCALE_RATIO_C 0x0fdd 5174 #define regDSCL2_SCL_VERT_FILTER_SCALE_RATIO_C_BASE_IDX 2 5175 #define regDSCL2_SCL_VERT_FILTER_INIT_C 0x0fde 5176 #define regDSCL2_SCL_VERT_FILTER_INIT_C_BASE_IDX 2 5177 #define regDSCL2_SCL_VERT_FILTER_INIT_BOT_C 0x0fdf 5178 #define regDSCL2_SCL_VERT_FILTER_INIT_BOT_C_BASE_IDX 2 5179 #define regDSCL2_SCL_BLACK_COLOR 0x0fe0 5180 #define regDSCL2_SCL_BLACK_COLOR_BASE_IDX 2 5181 #define regDSCL2_DSCL_UPDATE 0x0fe1 5182 #define regDSCL2_DSCL_UPDATE_BASE_IDX 2 5183 #define regDSCL2_DSCL_AUTOCAL 0x0fe2 5184 #define regDSCL2_DSCL_AUTOCAL_BASE_IDX 2 5185 #define regDSCL2_DSCL_EXT_OVERSCAN_LEFT_RIGHT 0x0fe3 5186 #define regDSCL2_DSCL_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX 2 5187 #define regDSCL2_DSCL_EXT_OVERSCAN_TOP_BOTTOM 0x0fe4 5188 #define regDSCL2_DSCL_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX 2 5189 #define regDSCL2_OTG_H_BLANK 0x0fe5 5190 #define regDSCL2_OTG_H_BLANK_BASE_IDX 2 5191 #define regDSCL2_OTG_V_BLANK 0x0fe6 5192 #define regDSCL2_OTG_V_BLANK_BASE_IDX 2 5193 #define regDSCL2_RECOUT_START 0x0fe7 5194 #define regDSCL2_RECOUT_START_BASE_IDX 2 5195 #define regDSCL2_RECOUT_SIZE 0x0fe8 5196 #define regDSCL2_RECOUT_SIZE_BASE_IDX 2 5197 #define regDSCL2_MPC_SIZE 0x0fe9 5198 #define regDSCL2_MPC_SIZE_BASE_IDX 2 5199 #define regDSCL2_LB_DATA_FORMAT 0x0fea 5200 #define regDSCL2_LB_DATA_FORMAT_BASE_IDX 2 5201 #define regDSCL2_LB_MEMORY_CTRL 0x0feb 5202 #define regDSCL2_LB_MEMORY_CTRL_BASE_IDX 2 5203 #define regDSCL2_LB_V_COUNTER 0x0fec 5204 #define regDSCL2_LB_V_COUNTER_BASE_IDX 2 5205 #define regDSCL2_DSCL_MEM_PWR_CTRL 0x0fed 5206 #define regDSCL2_DSCL_MEM_PWR_CTRL_BASE_IDX 2 5207 #define regDSCL2_DSCL_MEM_PWR_STATUS 0x0fee 5208 #define regDSCL2_DSCL_MEM_PWR_STATUS_BASE_IDX 2 5209 #define regDSCL2_OBUF_CONTROL 0x0fef 5210 #define regDSCL2_OBUF_CONTROL_BASE_IDX 2 5211 #define regDSCL2_OBUF_MEM_PWR_CTRL 0x0ff0 5212 #define regDSCL2_OBUF_MEM_PWR_CTRL_BASE_IDX 2 5213 5214 5215 // addressBlock: dce_dc_dpp2_dispdec_cm_dispdec 5216 // base address: 0xb58 5217 #define regCM2_CM_CONTROL 0x0ff6 5218 #define regCM2_CM_CONTROL_BASE_IDX 2 5219 #define regCM2_CM_POST_CSC_CONTROL 0x0ff7 5220 #define regCM2_CM_POST_CSC_CONTROL_BASE_IDX 2 5221 #define regCM2_CM_POST_CSC_C11_C12 0x0ff8 5222 #define regCM2_CM_POST_CSC_C11_C12_BASE_IDX 2 5223 #define regCM2_CM_POST_CSC_C13_C14 0x0ff9 5224 #define regCM2_CM_POST_CSC_C13_C14_BASE_IDX 2 5225 #define regCM2_CM_POST_CSC_C21_C22 0x0ffa 5226 #define regCM2_CM_POST_CSC_C21_C22_BASE_IDX 2 5227 #define regCM2_CM_POST_CSC_C23_C24 0x0ffb 5228 #define regCM2_CM_POST_CSC_C23_C24_BASE_IDX 2 5229 #define regCM2_CM_POST_CSC_C31_C32 0x0ffc 5230 #define regCM2_CM_POST_CSC_C31_C32_BASE_IDX 2 5231 #define regCM2_CM_POST_CSC_C33_C34 0x0ffd 5232 #define regCM2_CM_POST_CSC_C33_C34_BASE_IDX 2 5233 #define regCM2_CM_POST_CSC_B_C11_C12 0x0ffe 5234 #define regCM2_CM_POST_CSC_B_C11_C12_BASE_IDX 2 5235 #define regCM2_CM_POST_CSC_B_C13_C14 0x0fff 5236 #define regCM2_CM_POST_CSC_B_C13_C14_BASE_IDX 2 5237 #define regCM2_CM_POST_CSC_B_C21_C22 0x1000 5238 #define regCM2_CM_POST_CSC_B_C21_C22_BASE_IDX 2 5239 #define regCM2_CM_POST_CSC_B_C23_C24 0x1001 5240 #define regCM2_CM_POST_CSC_B_C23_C24_BASE_IDX 2 5241 #define regCM2_CM_POST_CSC_B_C31_C32 0x1002 5242 #define regCM2_CM_POST_CSC_B_C31_C32_BASE_IDX 2 5243 #define regCM2_CM_POST_CSC_B_C33_C34 0x1003 5244 #define regCM2_CM_POST_CSC_B_C33_C34_BASE_IDX 2 5245 #define regCM2_CM_GAMUT_REMAP_CONTROL 0x1004 5246 #define regCM2_CM_GAMUT_REMAP_CONTROL_BASE_IDX 2 5247 #define regCM2_CM_GAMUT_REMAP_C11_C12 0x1005 5248 #define regCM2_CM_GAMUT_REMAP_C11_C12_BASE_IDX 2 5249 #define regCM2_CM_GAMUT_REMAP_C13_C14 0x1006 5250 #define regCM2_CM_GAMUT_REMAP_C13_C14_BASE_IDX 2 5251 #define regCM2_CM_GAMUT_REMAP_C21_C22 0x1007 5252 #define regCM2_CM_GAMUT_REMAP_C21_C22_BASE_IDX 2 5253 #define regCM2_CM_GAMUT_REMAP_C23_C24 0x1008 5254 #define regCM2_CM_GAMUT_REMAP_C23_C24_BASE_IDX 2 5255 #define regCM2_CM_GAMUT_REMAP_C31_C32 0x1009 5256 #define regCM2_CM_GAMUT_REMAP_C31_C32_BASE_IDX 2 5257 #define regCM2_CM_GAMUT_REMAP_C33_C34 0x100a 5258 #define regCM2_CM_GAMUT_REMAP_C33_C34_BASE_IDX 2 5259 #define regCM2_CM_GAMUT_REMAP_B_C11_C12 0x100b 5260 #define regCM2_CM_GAMUT_REMAP_B_C11_C12_BASE_IDX 2 5261 #define regCM2_CM_GAMUT_REMAP_B_C13_C14 0x100c 5262 #define regCM2_CM_GAMUT_REMAP_B_C13_C14_BASE_IDX 2 5263 #define regCM2_CM_GAMUT_REMAP_B_C21_C22 0x100d 5264 #define regCM2_CM_GAMUT_REMAP_B_C21_C22_BASE_IDX 2 5265 #define regCM2_CM_GAMUT_REMAP_B_C23_C24 0x100e 5266 #define regCM2_CM_GAMUT_REMAP_B_C23_C24_BASE_IDX 2 5267 #define regCM2_CM_GAMUT_REMAP_B_C31_C32 0x100f 5268 #define regCM2_CM_GAMUT_REMAP_B_C31_C32_BASE_IDX 2 5269 #define regCM2_CM_GAMUT_REMAP_B_C33_C34 0x1010 5270 #define regCM2_CM_GAMUT_REMAP_B_C33_C34_BASE_IDX 2 5271 #define regCM2_CM_BIAS_CR_R 0x1011 5272 #define regCM2_CM_BIAS_CR_R_BASE_IDX 2 5273 #define regCM2_CM_BIAS_Y_G_CB_B 0x1012 5274 #define regCM2_CM_BIAS_Y_G_CB_B_BASE_IDX 2 5275 #define regCM2_CM_GAMCOR_CONTROL 0x1013 5276 #define regCM2_CM_GAMCOR_CONTROL_BASE_IDX 2 5277 #define regCM2_CM_GAMCOR_LUT_INDEX 0x1014 5278 #define regCM2_CM_GAMCOR_LUT_INDEX_BASE_IDX 2 5279 #define regCM2_CM_GAMCOR_LUT_DATA 0x1015 5280 #define regCM2_CM_GAMCOR_LUT_DATA_BASE_IDX 2 5281 #define regCM2_CM_GAMCOR_LUT_CONTROL 0x1016 5282 #define regCM2_CM_GAMCOR_LUT_CONTROL_BASE_IDX 2 5283 #define regCM2_CM_GAMCOR_RAMA_START_CNTL_B 0x1017 5284 #define regCM2_CM_GAMCOR_RAMA_START_CNTL_B_BASE_IDX 2 5285 #define regCM2_CM_GAMCOR_RAMA_START_CNTL_G 0x1018 5286 #define regCM2_CM_GAMCOR_RAMA_START_CNTL_G_BASE_IDX 2 5287 #define regCM2_CM_GAMCOR_RAMA_START_CNTL_R 0x1019 5288 #define regCM2_CM_GAMCOR_RAMA_START_CNTL_R_BASE_IDX 2 5289 #define regCM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B 0x101a 5290 #define regCM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B_BASE_IDX 2 5291 #define regCM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G 0x101b 5292 #define regCM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G_BASE_IDX 2 5293 #define regCM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R 0x101c 5294 #define regCM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R_BASE_IDX 2 5295 #define regCM2_CM_GAMCOR_RAMA_START_BASE_CNTL_B 0x101d 5296 #define regCM2_CM_GAMCOR_RAMA_START_BASE_CNTL_B_BASE_IDX 2 5297 #define regCM2_CM_GAMCOR_RAMA_START_BASE_CNTL_G 0x101e 5298 #define regCM2_CM_GAMCOR_RAMA_START_BASE_CNTL_G_BASE_IDX 2 5299 #define regCM2_CM_GAMCOR_RAMA_START_BASE_CNTL_R 0x101f 5300 #define regCM2_CM_GAMCOR_RAMA_START_BASE_CNTL_R_BASE_IDX 2 5301 #define regCM2_CM_GAMCOR_RAMA_END_CNTL1_B 0x1020 5302 #define regCM2_CM_GAMCOR_RAMA_END_CNTL1_B_BASE_IDX 2 5303 #define regCM2_CM_GAMCOR_RAMA_END_CNTL2_B 0x1021 5304 #define regCM2_CM_GAMCOR_RAMA_END_CNTL2_B_BASE_IDX 2 5305 #define regCM2_CM_GAMCOR_RAMA_END_CNTL1_G 0x1022 5306 #define regCM2_CM_GAMCOR_RAMA_END_CNTL1_G_BASE_IDX 2 5307 #define regCM2_CM_GAMCOR_RAMA_END_CNTL2_G 0x1023 5308 #define regCM2_CM_GAMCOR_RAMA_END_CNTL2_G_BASE_IDX 2 5309 #define regCM2_CM_GAMCOR_RAMA_END_CNTL1_R 0x1024 5310 #define regCM2_CM_GAMCOR_RAMA_END_CNTL1_R_BASE_IDX 2 5311 #define regCM2_CM_GAMCOR_RAMA_END_CNTL2_R 0x1025 5312 #define regCM2_CM_GAMCOR_RAMA_END_CNTL2_R_BASE_IDX 2 5313 #define regCM2_CM_GAMCOR_RAMA_OFFSET_B 0x1026 5314 #define regCM2_CM_GAMCOR_RAMA_OFFSET_B_BASE_IDX 2 5315 #define regCM2_CM_GAMCOR_RAMA_OFFSET_G 0x1027 5316 #define regCM2_CM_GAMCOR_RAMA_OFFSET_G_BASE_IDX 2 5317 #define regCM2_CM_GAMCOR_RAMA_OFFSET_R 0x1028 5318 #define regCM2_CM_GAMCOR_RAMA_OFFSET_R_BASE_IDX 2 5319 #define regCM2_CM_GAMCOR_RAMA_REGION_0_1 0x1029 5320 #define regCM2_CM_GAMCOR_RAMA_REGION_0_1_BASE_IDX 2 5321 #define regCM2_CM_GAMCOR_RAMA_REGION_2_3 0x102a 5322 #define regCM2_CM_GAMCOR_RAMA_REGION_2_3_BASE_IDX 2 5323 #define regCM2_CM_GAMCOR_RAMA_REGION_4_5 0x102b 5324 #define regCM2_CM_GAMCOR_RAMA_REGION_4_5_BASE_IDX 2 5325 #define regCM2_CM_GAMCOR_RAMA_REGION_6_7 0x102c 5326 #define regCM2_CM_GAMCOR_RAMA_REGION_6_7_BASE_IDX 2 5327 #define regCM2_CM_GAMCOR_RAMA_REGION_8_9 0x102d 5328 #define regCM2_CM_GAMCOR_RAMA_REGION_8_9_BASE_IDX 2 5329 #define regCM2_CM_GAMCOR_RAMA_REGION_10_11 0x102e 5330 #define regCM2_CM_GAMCOR_RAMA_REGION_10_11_BASE_IDX 2 5331 #define regCM2_CM_GAMCOR_RAMA_REGION_12_13 0x102f 5332 #define regCM2_CM_GAMCOR_RAMA_REGION_12_13_BASE_IDX 2 5333 #define regCM2_CM_GAMCOR_RAMA_REGION_14_15 0x1030 5334 #define regCM2_CM_GAMCOR_RAMA_REGION_14_15_BASE_IDX 2 5335 #define regCM2_CM_GAMCOR_RAMA_REGION_16_17 0x1031 5336 #define regCM2_CM_GAMCOR_RAMA_REGION_16_17_BASE_IDX 2 5337 #define regCM2_CM_GAMCOR_RAMA_REGION_18_19 0x1032 5338 #define regCM2_CM_GAMCOR_RAMA_REGION_18_19_BASE_IDX 2 5339 #define regCM2_CM_GAMCOR_RAMA_REGION_20_21 0x1033 5340 #define regCM2_CM_GAMCOR_RAMA_REGION_20_21_BASE_IDX 2 5341 #define regCM2_CM_GAMCOR_RAMA_REGION_22_23 0x1034 5342 #define regCM2_CM_GAMCOR_RAMA_REGION_22_23_BASE_IDX 2 5343 #define regCM2_CM_GAMCOR_RAMA_REGION_24_25 0x1035 5344 #define regCM2_CM_GAMCOR_RAMA_REGION_24_25_BASE_IDX 2 5345 #define regCM2_CM_GAMCOR_RAMA_REGION_26_27 0x1036 5346 #define regCM2_CM_GAMCOR_RAMA_REGION_26_27_BASE_IDX 2 5347 #define regCM2_CM_GAMCOR_RAMA_REGION_28_29 0x1037 5348 #define regCM2_CM_GAMCOR_RAMA_REGION_28_29_BASE_IDX 2 5349 #define regCM2_CM_GAMCOR_RAMA_REGION_30_31 0x1038 5350 #define regCM2_CM_GAMCOR_RAMA_REGION_30_31_BASE_IDX 2 5351 #define regCM2_CM_GAMCOR_RAMA_REGION_32_33 0x1039 5352 #define regCM2_CM_GAMCOR_RAMA_REGION_32_33_BASE_IDX 2 5353 #define regCM2_CM_GAMCOR_RAMB_START_CNTL_B 0x103a 5354 #define regCM2_CM_GAMCOR_RAMB_START_CNTL_B_BASE_IDX 2 5355 #define regCM2_CM_GAMCOR_RAMB_START_CNTL_G 0x103b 5356 #define regCM2_CM_GAMCOR_RAMB_START_CNTL_G_BASE_IDX 2 5357 #define regCM2_CM_GAMCOR_RAMB_START_CNTL_R 0x103c 5358 #define regCM2_CM_GAMCOR_RAMB_START_CNTL_R_BASE_IDX 2 5359 #define regCM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B 0x103d 5360 #define regCM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B_BASE_IDX 2 5361 #define regCM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G 0x103e 5362 #define regCM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G_BASE_IDX 2 5363 #define regCM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R 0x103f 5364 #define regCM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R_BASE_IDX 2 5365 #define regCM2_CM_GAMCOR_RAMB_START_BASE_CNTL_B 0x1040 5366 #define regCM2_CM_GAMCOR_RAMB_START_BASE_CNTL_B_BASE_IDX 2 5367 #define regCM2_CM_GAMCOR_RAMB_START_BASE_CNTL_G 0x1041 5368 #define regCM2_CM_GAMCOR_RAMB_START_BASE_CNTL_G_BASE_IDX 2 5369 #define regCM2_CM_GAMCOR_RAMB_START_BASE_CNTL_R 0x1042 5370 #define regCM2_CM_GAMCOR_RAMB_START_BASE_CNTL_R_BASE_IDX 2 5371 #define regCM2_CM_GAMCOR_RAMB_END_CNTL1_B 0x1043 5372 #define regCM2_CM_GAMCOR_RAMB_END_CNTL1_B_BASE_IDX 2 5373 #define regCM2_CM_GAMCOR_RAMB_END_CNTL2_B 0x1044 5374 #define regCM2_CM_GAMCOR_RAMB_END_CNTL2_B_BASE_IDX 2 5375 #define regCM2_CM_GAMCOR_RAMB_END_CNTL1_G 0x1045 5376 #define regCM2_CM_GAMCOR_RAMB_END_CNTL1_G_BASE_IDX 2 5377 #define regCM2_CM_GAMCOR_RAMB_END_CNTL2_G 0x1046 5378 #define regCM2_CM_GAMCOR_RAMB_END_CNTL2_G_BASE_IDX 2 5379 #define regCM2_CM_GAMCOR_RAMB_END_CNTL1_R 0x1047 5380 #define regCM2_CM_GAMCOR_RAMB_END_CNTL1_R_BASE_IDX 2 5381 #define regCM2_CM_GAMCOR_RAMB_END_CNTL2_R 0x1048 5382 #define regCM2_CM_GAMCOR_RAMB_END_CNTL2_R_BASE_IDX 2 5383 #define regCM2_CM_GAMCOR_RAMB_OFFSET_B 0x1049 5384 #define regCM2_CM_GAMCOR_RAMB_OFFSET_B_BASE_IDX 2 5385 #define regCM2_CM_GAMCOR_RAMB_OFFSET_G 0x104a 5386 #define regCM2_CM_GAMCOR_RAMB_OFFSET_G_BASE_IDX 2 5387 #define regCM2_CM_GAMCOR_RAMB_OFFSET_R 0x104b 5388 #define regCM2_CM_GAMCOR_RAMB_OFFSET_R_BASE_IDX 2 5389 #define regCM2_CM_GAMCOR_RAMB_REGION_0_1 0x104c 5390 #define regCM2_CM_GAMCOR_RAMB_REGION_0_1_BASE_IDX 2 5391 #define regCM2_CM_GAMCOR_RAMB_REGION_2_3 0x104d 5392 #define regCM2_CM_GAMCOR_RAMB_REGION_2_3_BASE_IDX 2 5393 #define regCM2_CM_GAMCOR_RAMB_REGION_4_5 0x104e 5394 #define regCM2_CM_GAMCOR_RAMB_REGION_4_5_BASE_IDX 2 5395 #define regCM2_CM_GAMCOR_RAMB_REGION_6_7 0x104f 5396 #define regCM2_CM_GAMCOR_RAMB_REGION_6_7_BASE_IDX 2 5397 #define regCM2_CM_GAMCOR_RAMB_REGION_8_9 0x1050 5398 #define regCM2_CM_GAMCOR_RAMB_REGION_8_9_BASE_IDX 2 5399 #define regCM2_CM_GAMCOR_RAMB_REGION_10_11 0x1051 5400 #define regCM2_CM_GAMCOR_RAMB_REGION_10_11_BASE_IDX 2 5401 #define regCM2_CM_GAMCOR_RAMB_REGION_12_13 0x1052 5402 #define regCM2_CM_GAMCOR_RAMB_REGION_12_13_BASE_IDX 2 5403 #define regCM2_CM_GAMCOR_RAMB_REGION_14_15 0x1053 5404 #define regCM2_CM_GAMCOR_RAMB_REGION_14_15_BASE_IDX 2 5405 #define regCM2_CM_GAMCOR_RAMB_REGION_16_17 0x1054 5406 #define regCM2_CM_GAMCOR_RAMB_REGION_16_17_BASE_IDX 2 5407 #define regCM2_CM_GAMCOR_RAMB_REGION_18_19 0x1055 5408 #define regCM2_CM_GAMCOR_RAMB_REGION_18_19_BASE_IDX 2 5409 #define regCM2_CM_GAMCOR_RAMB_REGION_20_21 0x1056 5410 #define regCM2_CM_GAMCOR_RAMB_REGION_20_21_BASE_IDX 2 5411 #define regCM2_CM_GAMCOR_RAMB_REGION_22_23 0x1057 5412 #define regCM2_CM_GAMCOR_RAMB_REGION_22_23_BASE_IDX 2 5413 #define regCM2_CM_GAMCOR_RAMB_REGION_24_25 0x1058 5414 #define regCM2_CM_GAMCOR_RAMB_REGION_24_25_BASE_IDX 2 5415 #define regCM2_CM_GAMCOR_RAMB_REGION_26_27 0x1059 5416 #define regCM2_CM_GAMCOR_RAMB_REGION_26_27_BASE_IDX 2 5417 #define regCM2_CM_GAMCOR_RAMB_REGION_28_29 0x105a 5418 #define regCM2_CM_GAMCOR_RAMB_REGION_28_29_BASE_IDX 2 5419 #define regCM2_CM_GAMCOR_RAMB_REGION_30_31 0x105b 5420 #define regCM2_CM_GAMCOR_RAMB_REGION_30_31_BASE_IDX 2 5421 #define regCM2_CM_GAMCOR_RAMB_REGION_32_33 0x105c 5422 #define regCM2_CM_GAMCOR_RAMB_REGION_32_33_BASE_IDX 2 5423 #define regCM2_CM_BLNDGAM_CONTROL 0x105d 5424 #define regCM2_CM_BLNDGAM_CONTROL_BASE_IDX 2 5425 #define regCM2_CM_BLNDGAM_LUT_INDEX 0x105e 5426 #define regCM2_CM_BLNDGAM_LUT_INDEX_BASE_IDX 2 5427 #define regCM2_CM_BLNDGAM_LUT_DATA 0x105f 5428 #define regCM2_CM_BLNDGAM_LUT_DATA_BASE_IDX 2 5429 #define regCM2_CM_BLNDGAM_LUT_CONTROL 0x1060 5430 #define regCM2_CM_BLNDGAM_LUT_CONTROL_BASE_IDX 2 5431 #define regCM2_CM_BLNDGAM_RAMA_START_CNTL_B 0x1061 5432 #define regCM2_CM_BLNDGAM_RAMA_START_CNTL_B_BASE_IDX 2 5433 #define regCM2_CM_BLNDGAM_RAMA_START_CNTL_G 0x1062 5434 #define regCM2_CM_BLNDGAM_RAMA_START_CNTL_G_BASE_IDX 2 5435 #define regCM2_CM_BLNDGAM_RAMA_START_CNTL_R 0x1063 5436 #define regCM2_CM_BLNDGAM_RAMA_START_CNTL_R_BASE_IDX 2 5437 #define regCM2_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_B 0x1064 5438 #define regCM2_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_B_BASE_IDX 2 5439 #define regCM2_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_G 0x1065 5440 #define regCM2_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_G_BASE_IDX 2 5441 #define regCM2_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_R 0x1066 5442 #define regCM2_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_R_BASE_IDX 2 5443 #define regCM2_CM_BLNDGAM_RAMA_START_BASE_CNTL_B 0x1067 5444 #define regCM2_CM_BLNDGAM_RAMA_START_BASE_CNTL_B_BASE_IDX 2 5445 #define regCM2_CM_BLNDGAM_RAMA_START_BASE_CNTL_G 0x1068 5446 #define regCM2_CM_BLNDGAM_RAMA_START_BASE_CNTL_G_BASE_IDX 2 5447 #define regCM2_CM_BLNDGAM_RAMA_START_BASE_CNTL_R 0x1069 5448 #define regCM2_CM_BLNDGAM_RAMA_START_BASE_CNTL_R_BASE_IDX 2 5449 #define regCM2_CM_BLNDGAM_RAMA_END_CNTL1_B 0x106a 5450 #define regCM2_CM_BLNDGAM_RAMA_END_CNTL1_B_BASE_IDX 2 5451 #define regCM2_CM_BLNDGAM_RAMA_END_CNTL2_B 0x106b 5452 #define regCM2_CM_BLNDGAM_RAMA_END_CNTL2_B_BASE_IDX 2 5453 #define regCM2_CM_BLNDGAM_RAMA_END_CNTL1_G 0x106c 5454 #define regCM2_CM_BLNDGAM_RAMA_END_CNTL1_G_BASE_IDX 2 5455 #define regCM2_CM_BLNDGAM_RAMA_END_CNTL2_G 0x106d 5456 #define regCM2_CM_BLNDGAM_RAMA_END_CNTL2_G_BASE_IDX 2 5457 #define regCM2_CM_BLNDGAM_RAMA_END_CNTL1_R 0x106e 5458 #define regCM2_CM_BLNDGAM_RAMA_END_CNTL1_R_BASE_IDX 2 5459 #define regCM2_CM_BLNDGAM_RAMA_END_CNTL2_R 0x106f 5460 #define regCM2_CM_BLNDGAM_RAMA_END_CNTL2_R_BASE_IDX 2 5461 #define regCM2_CM_BLNDGAM_RAMA_OFFSET_B 0x1070 5462 #define regCM2_CM_BLNDGAM_RAMA_OFFSET_B_BASE_IDX 2 5463 #define regCM2_CM_BLNDGAM_RAMA_OFFSET_G 0x1071 5464 #define regCM2_CM_BLNDGAM_RAMA_OFFSET_G_BASE_IDX 2 5465 #define regCM2_CM_BLNDGAM_RAMA_OFFSET_R 0x1072 5466 #define regCM2_CM_BLNDGAM_RAMA_OFFSET_R_BASE_IDX 2 5467 #define regCM2_CM_BLNDGAM_RAMA_REGION_0_1 0x1073 5468 #define regCM2_CM_BLNDGAM_RAMA_REGION_0_1_BASE_IDX 2 5469 #define regCM2_CM_BLNDGAM_RAMA_REGION_2_3 0x1074 5470 #define regCM2_CM_BLNDGAM_RAMA_REGION_2_3_BASE_IDX 2 5471 #define regCM2_CM_BLNDGAM_RAMA_REGION_4_5 0x1075 5472 #define regCM2_CM_BLNDGAM_RAMA_REGION_4_5_BASE_IDX 2 5473 #define regCM2_CM_BLNDGAM_RAMA_REGION_6_7 0x1076 5474 #define regCM2_CM_BLNDGAM_RAMA_REGION_6_7_BASE_IDX 2 5475 #define regCM2_CM_BLNDGAM_RAMA_REGION_8_9 0x1077 5476 #define regCM2_CM_BLNDGAM_RAMA_REGION_8_9_BASE_IDX 2 5477 #define regCM2_CM_BLNDGAM_RAMA_REGION_10_11 0x1078 5478 #define regCM2_CM_BLNDGAM_RAMA_REGION_10_11_BASE_IDX 2 5479 #define regCM2_CM_BLNDGAM_RAMA_REGION_12_13 0x1079 5480 #define regCM2_CM_BLNDGAM_RAMA_REGION_12_13_BASE_IDX 2 5481 #define regCM2_CM_BLNDGAM_RAMA_REGION_14_15 0x107a 5482 #define regCM2_CM_BLNDGAM_RAMA_REGION_14_15_BASE_IDX 2 5483 #define regCM2_CM_BLNDGAM_RAMA_REGION_16_17 0x107b 5484 #define regCM2_CM_BLNDGAM_RAMA_REGION_16_17_BASE_IDX 2 5485 #define regCM2_CM_BLNDGAM_RAMA_REGION_18_19 0x107c 5486 #define regCM2_CM_BLNDGAM_RAMA_REGION_18_19_BASE_IDX 2 5487 #define regCM2_CM_BLNDGAM_RAMA_REGION_20_21 0x107d 5488 #define regCM2_CM_BLNDGAM_RAMA_REGION_20_21_BASE_IDX 2 5489 #define regCM2_CM_BLNDGAM_RAMA_REGION_22_23 0x107e 5490 #define regCM2_CM_BLNDGAM_RAMA_REGION_22_23_BASE_IDX 2 5491 #define regCM2_CM_BLNDGAM_RAMA_REGION_24_25 0x107f 5492 #define regCM2_CM_BLNDGAM_RAMA_REGION_24_25_BASE_IDX 2 5493 #define regCM2_CM_BLNDGAM_RAMA_REGION_26_27 0x1080 5494 #define regCM2_CM_BLNDGAM_RAMA_REGION_26_27_BASE_IDX 2 5495 #define regCM2_CM_BLNDGAM_RAMA_REGION_28_29 0x1081 5496 #define regCM2_CM_BLNDGAM_RAMA_REGION_28_29_BASE_IDX 2 5497 #define regCM2_CM_BLNDGAM_RAMA_REGION_30_31 0x1082 5498 #define regCM2_CM_BLNDGAM_RAMA_REGION_30_31_BASE_IDX 2 5499 #define regCM2_CM_BLNDGAM_RAMA_REGION_32_33 0x1083 5500 #define regCM2_CM_BLNDGAM_RAMA_REGION_32_33_BASE_IDX 2 5501 #define regCM2_CM_BLNDGAM_RAMB_START_CNTL_B 0x1084 5502 #define regCM2_CM_BLNDGAM_RAMB_START_CNTL_B_BASE_IDX 2 5503 #define regCM2_CM_BLNDGAM_RAMB_START_CNTL_G 0x1085 5504 #define regCM2_CM_BLNDGAM_RAMB_START_CNTL_G_BASE_IDX 2 5505 #define regCM2_CM_BLNDGAM_RAMB_START_CNTL_R 0x1086 5506 #define regCM2_CM_BLNDGAM_RAMB_START_CNTL_R_BASE_IDX 2 5507 #define regCM2_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_B 0x1087 5508 #define regCM2_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_B_BASE_IDX 2 5509 #define regCM2_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_G 0x1088 5510 #define regCM2_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_G_BASE_IDX 2 5511 #define regCM2_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_R 0x1089 5512 #define regCM2_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_R_BASE_IDX 2 5513 #define regCM2_CM_BLNDGAM_RAMB_START_BASE_CNTL_B 0x108a 5514 #define regCM2_CM_BLNDGAM_RAMB_START_BASE_CNTL_B_BASE_IDX 2 5515 #define regCM2_CM_BLNDGAM_RAMB_START_BASE_CNTL_G 0x108b 5516 #define regCM2_CM_BLNDGAM_RAMB_START_BASE_CNTL_G_BASE_IDX 2 5517 #define regCM2_CM_BLNDGAM_RAMB_START_BASE_CNTL_R 0x108c 5518 #define regCM2_CM_BLNDGAM_RAMB_START_BASE_CNTL_R_BASE_IDX 2 5519 #define regCM2_CM_BLNDGAM_RAMB_END_CNTL1_B 0x108d 5520 #define regCM2_CM_BLNDGAM_RAMB_END_CNTL1_B_BASE_IDX 2 5521 #define regCM2_CM_BLNDGAM_RAMB_END_CNTL2_B 0x108e 5522 #define regCM2_CM_BLNDGAM_RAMB_END_CNTL2_B_BASE_IDX 2 5523 #define regCM2_CM_BLNDGAM_RAMB_END_CNTL1_G 0x108f 5524 #define regCM2_CM_BLNDGAM_RAMB_END_CNTL1_G_BASE_IDX 2 5525 #define regCM2_CM_BLNDGAM_RAMB_END_CNTL2_G 0x1090 5526 #define regCM2_CM_BLNDGAM_RAMB_END_CNTL2_G_BASE_IDX 2 5527 #define regCM2_CM_BLNDGAM_RAMB_END_CNTL1_R 0x1091 5528 #define regCM2_CM_BLNDGAM_RAMB_END_CNTL1_R_BASE_IDX 2 5529 #define regCM2_CM_BLNDGAM_RAMB_END_CNTL2_R 0x1092 5530 #define regCM2_CM_BLNDGAM_RAMB_END_CNTL2_R_BASE_IDX 2 5531 #define regCM2_CM_BLNDGAM_RAMB_OFFSET_B 0x1093 5532 #define regCM2_CM_BLNDGAM_RAMB_OFFSET_B_BASE_IDX 2 5533 #define regCM2_CM_BLNDGAM_RAMB_OFFSET_G 0x1094 5534 #define regCM2_CM_BLNDGAM_RAMB_OFFSET_G_BASE_IDX 2 5535 #define regCM2_CM_BLNDGAM_RAMB_OFFSET_R 0x1095 5536 #define regCM2_CM_BLNDGAM_RAMB_OFFSET_R_BASE_IDX 2 5537 #define regCM2_CM_BLNDGAM_RAMB_REGION_0_1 0x1096 5538 #define regCM2_CM_BLNDGAM_RAMB_REGION_0_1_BASE_IDX 2 5539 #define regCM2_CM_BLNDGAM_RAMB_REGION_2_3 0x1097 5540 #define regCM2_CM_BLNDGAM_RAMB_REGION_2_3_BASE_IDX 2 5541 #define regCM2_CM_BLNDGAM_RAMB_REGION_4_5 0x1098 5542 #define regCM2_CM_BLNDGAM_RAMB_REGION_4_5_BASE_IDX 2 5543 #define regCM2_CM_BLNDGAM_RAMB_REGION_6_7 0x1099 5544 #define regCM2_CM_BLNDGAM_RAMB_REGION_6_7_BASE_IDX 2 5545 #define regCM2_CM_BLNDGAM_RAMB_REGION_8_9 0x109a 5546 #define regCM2_CM_BLNDGAM_RAMB_REGION_8_9_BASE_IDX 2 5547 #define regCM2_CM_BLNDGAM_RAMB_REGION_10_11 0x109b 5548 #define regCM2_CM_BLNDGAM_RAMB_REGION_10_11_BASE_IDX 2 5549 #define regCM2_CM_BLNDGAM_RAMB_REGION_12_13 0x109c 5550 #define regCM2_CM_BLNDGAM_RAMB_REGION_12_13_BASE_IDX 2 5551 #define regCM2_CM_BLNDGAM_RAMB_REGION_14_15 0x109d 5552 #define regCM2_CM_BLNDGAM_RAMB_REGION_14_15_BASE_IDX 2 5553 #define regCM2_CM_BLNDGAM_RAMB_REGION_16_17 0x109e 5554 #define regCM2_CM_BLNDGAM_RAMB_REGION_16_17_BASE_IDX 2 5555 #define regCM2_CM_BLNDGAM_RAMB_REGION_18_19 0x109f 5556 #define regCM2_CM_BLNDGAM_RAMB_REGION_18_19_BASE_IDX 2 5557 #define regCM2_CM_BLNDGAM_RAMB_REGION_20_21 0x10a0 5558 #define regCM2_CM_BLNDGAM_RAMB_REGION_20_21_BASE_IDX 2 5559 #define regCM2_CM_BLNDGAM_RAMB_REGION_22_23 0x10a1 5560 #define regCM2_CM_BLNDGAM_RAMB_REGION_22_23_BASE_IDX 2 5561 #define regCM2_CM_BLNDGAM_RAMB_REGION_24_25 0x10a2 5562 #define regCM2_CM_BLNDGAM_RAMB_REGION_24_25_BASE_IDX 2 5563 #define regCM2_CM_BLNDGAM_RAMB_REGION_26_27 0x10a3 5564 #define regCM2_CM_BLNDGAM_RAMB_REGION_26_27_BASE_IDX 2 5565 #define regCM2_CM_BLNDGAM_RAMB_REGION_28_29 0x10a4 5566 #define regCM2_CM_BLNDGAM_RAMB_REGION_28_29_BASE_IDX 2 5567 #define regCM2_CM_BLNDGAM_RAMB_REGION_30_31 0x10a5 5568 #define regCM2_CM_BLNDGAM_RAMB_REGION_30_31_BASE_IDX 2 5569 #define regCM2_CM_BLNDGAM_RAMB_REGION_32_33 0x10a6 5570 #define regCM2_CM_BLNDGAM_RAMB_REGION_32_33_BASE_IDX 2 5571 #define regCM2_CM_HDR_MULT_COEF 0x10a7 5572 #define regCM2_CM_HDR_MULT_COEF_BASE_IDX 2 5573 #define regCM2_CM_MEM_PWR_CTRL 0x10a8 5574 #define regCM2_CM_MEM_PWR_CTRL_BASE_IDX 2 5575 #define regCM2_CM_MEM_PWR_STATUS 0x10a9 5576 #define regCM2_CM_MEM_PWR_STATUS_BASE_IDX 2 5577 #define regCM2_CM_DEALPHA 0x10ab 5578 #define regCM2_CM_DEALPHA_BASE_IDX 2 5579 #define regCM2_CM_COEF_FORMAT 0x10ac 5580 #define regCM2_CM_COEF_FORMAT_BASE_IDX 2 5581 #define regCM2_CM_SHAPER_CONTROL 0x10ad 5582 #define regCM2_CM_SHAPER_CONTROL_BASE_IDX 2 5583 #define regCM2_CM_SHAPER_OFFSET_R 0x10ae 5584 #define regCM2_CM_SHAPER_OFFSET_R_BASE_IDX 2 5585 #define regCM2_CM_SHAPER_OFFSET_G 0x10af 5586 #define regCM2_CM_SHAPER_OFFSET_G_BASE_IDX 2 5587 #define regCM2_CM_SHAPER_OFFSET_B 0x10b0 5588 #define regCM2_CM_SHAPER_OFFSET_B_BASE_IDX 2 5589 #define regCM2_CM_SHAPER_SCALE_R 0x10b1 5590 #define regCM2_CM_SHAPER_SCALE_R_BASE_IDX 2 5591 #define regCM2_CM_SHAPER_SCALE_G_B 0x10b2 5592 #define regCM2_CM_SHAPER_SCALE_G_B_BASE_IDX 2 5593 #define regCM2_CM_SHAPER_LUT_INDEX 0x10b3 5594 #define regCM2_CM_SHAPER_LUT_INDEX_BASE_IDX 2 5595 #define regCM2_CM_SHAPER_LUT_DATA 0x10b4 5596 #define regCM2_CM_SHAPER_LUT_DATA_BASE_IDX 2 5597 #define regCM2_CM_SHAPER_LUT_WRITE_EN_MASK 0x10b5 5598 #define regCM2_CM_SHAPER_LUT_WRITE_EN_MASK_BASE_IDX 2 5599 #define regCM2_CM_SHAPER_RAMA_START_CNTL_B 0x10b6 5600 #define regCM2_CM_SHAPER_RAMA_START_CNTL_B_BASE_IDX 2 5601 #define regCM2_CM_SHAPER_RAMA_START_CNTL_G 0x10b7 5602 #define regCM2_CM_SHAPER_RAMA_START_CNTL_G_BASE_IDX 2 5603 #define regCM2_CM_SHAPER_RAMA_START_CNTL_R 0x10b8 5604 #define regCM2_CM_SHAPER_RAMA_START_CNTL_R_BASE_IDX 2 5605 #define regCM2_CM_SHAPER_RAMA_END_CNTL_B 0x10b9 5606 #define regCM2_CM_SHAPER_RAMA_END_CNTL_B_BASE_IDX 2 5607 #define regCM2_CM_SHAPER_RAMA_END_CNTL_G 0x10ba 5608 #define regCM2_CM_SHAPER_RAMA_END_CNTL_G_BASE_IDX 2 5609 #define regCM2_CM_SHAPER_RAMA_END_CNTL_R 0x10bb 5610 #define regCM2_CM_SHAPER_RAMA_END_CNTL_R_BASE_IDX 2 5611 #define regCM2_CM_SHAPER_RAMA_REGION_0_1 0x10bc 5612 #define regCM2_CM_SHAPER_RAMA_REGION_0_1_BASE_IDX 2 5613 #define regCM2_CM_SHAPER_RAMA_REGION_2_3 0x10bd 5614 #define regCM2_CM_SHAPER_RAMA_REGION_2_3_BASE_IDX 2 5615 #define regCM2_CM_SHAPER_RAMA_REGION_4_5 0x10be 5616 #define regCM2_CM_SHAPER_RAMA_REGION_4_5_BASE_IDX 2 5617 #define regCM2_CM_SHAPER_RAMA_REGION_6_7 0x10bf 5618 #define regCM2_CM_SHAPER_RAMA_REGION_6_7_BASE_IDX 2 5619 #define regCM2_CM_SHAPER_RAMA_REGION_8_9 0x10c0 5620 #define regCM2_CM_SHAPER_RAMA_REGION_8_9_BASE_IDX 2 5621 #define regCM2_CM_SHAPER_RAMA_REGION_10_11 0x10c1 5622 #define regCM2_CM_SHAPER_RAMA_REGION_10_11_BASE_IDX 2 5623 #define regCM2_CM_SHAPER_RAMA_REGION_12_13 0x10c2 5624 #define regCM2_CM_SHAPER_RAMA_REGION_12_13_BASE_IDX 2 5625 #define regCM2_CM_SHAPER_RAMA_REGION_14_15 0x10c3 5626 #define regCM2_CM_SHAPER_RAMA_REGION_14_15_BASE_IDX 2 5627 #define regCM2_CM_SHAPER_RAMA_REGION_16_17 0x10c4 5628 #define regCM2_CM_SHAPER_RAMA_REGION_16_17_BASE_IDX 2 5629 #define regCM2_CM_SHAPER_RAMA_REGION_18_19 0x10c5 5630 #define regCM2_CM_SHAPER_RAMA_REGION_18_19_BASE_IDX 2 5631 #define regCM2_CM_SHAPER_RAMA_REGION_20_21 0x10c6 5632 #define regCM2_CM_SHAPER_RAMA_REGION_20_21_BASE_IDX 2 5633 #define regCM2_CM_SHAPER_RAMA_REGION_22_23 0x10c7 5634 #define regCM2_CM_SHAPER_RAMA_REGION_22_23_BASE_IDX 2 5635 #define regCM2_CM_SHAPER_RAMA_REGION_24_25 0x10c8 5636 #define regCM2_CM_SHAPER_RAMA_REGION_24_25_BASE_IDX 2 5637 #define regCM2_CM_SHAPER_RAMA_REGION_26_27 0x10c9 5638 #define regCM2_CM_SHAPER_RAMA_REGION_26_27_BASE_IDX 2 5639 #define regCM2_CM_SHAPER_RAMA_REGION_28_29 0x10ca 5640 #define regCM2_CM_SHAPER_RAMA_REGION_28_29_BASE_IDX 2 5641 #define regCM2_CM_SHAPER_RAMA_REGION_30_31 0x10cb 5642 #define regCM2_CM_SHAPER_RAMA_REGION_30_31_BASE_IDX 2 5643 #define regCM2_CM_SHAPER_RAMA_REGION_32_33 0x10cc 5644 #define regCM2_CM_SHAPER_RAMA_REGION_32_33_BASE_IDX 2 5645 #define regCM2_CM_SHAPER_RAMB_START_CNTL_B 0x10cd 5646 #define regCM2_CM_SHAPER_RAMB_START_CNTL_B_BASE_IDX 2 5647 #define regCM2_CM_SHAPER_RAMB_START_CNTL_G 0x10ce 5648 #define regCM2_CM_SHAPER_RAMB_START_CNTL_G_BASE_IDX 2 5649 #define regCM2_CM_SHAPER_RAMB_START_CNTL_R 0x10cf 5650 #define regCM2_CM_SHAPER_RAMB_START_CNTL_R_BASE_IDX 2 5651 #define regCM2_CM_SHAPER_RAMB_END_CNTL_B 0x10d0 5652 #define regCM2_CM_SHAPER_RAMB_END_CNTL_B_BASE_IDX 2 5653 #define regCM2_CM_SHAPER_RAMB_END_CNTL_G 0x10d1 5654 #define regCM2_CM_SHAPER_RAMB_END_CNTL_G_BASE_IDX 2 5655 #define regCM2_CM_SHAPER_RAMB_END_CNTL_R 0x10d2 5656 #define regCM2_CM_SHAPER_RAMB_END_CNTL_R_BASE_IDX 2 5657 #define regCM2_CM_SHAPER_RAMB_REGION_0_1 0x10d3 5658 #define regCM2_CM_SHAPER_RAMB_REGION_0_1_BASE_IDX 2 5659 #define regCM2_CM_SHAPER_RAMB_REGION_2_3 0x10d4 5660 #define regCM2_CM_SHAPER_RAMB_REGION_2_3_BASE_IDX 2 5661 #define regCM2_CM_SHAPER_RAMB_REGION_4_5 0x10d5 5662 #define regCM2_CM_SHAPER_RAMB_REGION_4_5_BASE_IDX 2 5663 #define regCM2_CM_SHAPER_RAMB_REGION_6_7 0x10d6 5664 #define regCM2_CM_SHAPER_RAMB_REGION_6_7_BASE_IDX 2 5665 #define regCM2_CM_SHAPER_RAMB_REGION_8_9 0x10d7 5666 #define regCM2_CM_SHAPER_RAMB_REGION_8_9_BASE_IDX 2 5667 #define regCM2_CM_SHAPER_RAMB_REGION_10_11 0x10d8 5668 #define regCM2_CM_SHAPER_RAMB_REGION_10_11_BASE_IDX 2 5669 #define regCM2_CM_SHAPER_RAMB_REGION_12_13 0x10d9 5670 #define regCM2_CM_SHAPER_RAMB_REGION_12_13_BASE_IDX 2 5671 #define regCM2_CM_SHAPER_RAMB_REGION_14_15 0x10da 5672 #define regCM2_CM_SHAPER_RAMB_REGION_14_15_BASE_IDX 2 5673 #define regCM2_CM_SHAPER_RAMB_REGION_16_17 0x10db 5674 #define regCM2_CM_SHAPER_RAMB_REGION_16_17_BASE_IDX 2 5675 #define regCM2_CM_SHAPER_RAMB_REGION_18_19 0x10dc 5676 #define regCM2_CM_SHAPER_RAMB_REGION_18_19_BASE_IDX 2 5677 #define regCM2_CM_SHAPER_RAMB_REGION_20_21 0x10dd 5678 #define regCM2_CM_SHAPER_RAMB_REGION_20_21_BASE_IDX 2 5679 #define regCM2_CM_SHAPER_RAMB_REGION_22_23 0x10de 5680 #define regCM2_CM_SHAPER_RAMB_REGION_22_23_BASE_IDX 2 5681 #define regCM2_CM_SHAPER_RAMB_REGION_24_25 0x10df 5682 #define regCM2_CM_SHAPER_RAMB_REGION_24_25_BASE_IDX 2 5683 #define regCM2_CM_SHAPER_RAMB_REGION_26_27 0x10e0 5684 #define regCM2_CM_SHAPER_RAMB_REGION_26_27_BASE_IDX 2 5685 #define regCM2_CM_SHAPER_RAMB_REGION_28_29 0x10e1 5686 #define regCM2_CM_SHAPER_RAMB_REGION_28_29_BASE_IDX 2 5687 #define regCM2_CM_SHAPER_RAMB_REGION_30_31 0x10e2 5688 #define regCM2_CM_SHAPER_RAMB_REGION_30_31_BASE_IDX 2 5689 #define regCM2_CM_SHAPER_RAMB_REGION_32_33 0x10e3 5690 #define regCM2_CM_SHAPER_RAMB_REGION_32_33_BASE_IDX 2 5691 #define regCM2_CM_MEM_PWR_CTRL2 0x10e4 5692 #define regCM2_CM_MEM_PWR_CTRL2_BASE_IDX 2 5693 #define regCM2_CM_MEM_PWR_STATUS2 0x10e5 5694 #define regCM2_CM_MEM_PWR_STATUS2_BASE_IDX 2 5695 #define regCM2_CM_3DLUT_MODE 0x10e6 5696 #define regCM2_CM_3DLUT_MODE_BASE_IDX 2 5697 #define regCM2_CM_3DLUT_INDEX 0x10e7 5698 #define regCM2_CM_3DLUT_INDEX_BASE_IDX 2 5699 #define regCM2_CM_3DLUT_DATA 0x10e8 5700 #define regCM2_CM_3DLUT_DATA_BASE_IDX 2 5701 #define regCM2_CM_3DLUT_DATA_30BIT 0x10e9 5702 #define regCM2_CM_3DLUT_DATA_30BIT_BASE_IDX 2 5703 #define regCM2_CM_3DLUT_READ_WRITE_CONTROL 0x10ea 5704 #define regCM2_CM_3DLUT_READ_WRITE_CONTROL_BASE_IDX 2 5705 #define regCM2_CM_3DLUT_OUT_NORM_FACTOR 0x10eb 5706 #define regCM2_CM_3DLUT_OUT_NORM_FACTOR_BASE_IDX 2 5707 #define regCM2_CM_3DLUT_OUT_OFFSET_R 0x10ec 5708 #define regCM2_CM_3DLUT_OUT_OFFSET_R_BASE_IDX 2 5709 #define regCM2_CM_3DLUT_OUT_OFFSET_G 0x10ed 5710 #define regCM2_CM_3DLUT_OUT_OFFSET_G_BASE_IDX 2 5711 #define regCM2_CM_3DLUT_OUT_OFFSET_B 0x10ee 5712 #define regCM2_CM_3DLUT_OUT_OFFSET_B_BASE_IDX 2 5713 #define regCM2_CM_TEST_DEBUG_INDEX 0x10ef 5714 #define regCM2_CM_TEST_DEBUG_INDEX_BASE_IDX 2 5715 #define regCM2_CM_TEST_DEBUG_DATA 0x10f0 5716 #define regCM2_CM_TEST_DEBUG_DATA_BASE_IDX 2 5717 5718 5719 // addressBlock: dce_dc_dpp2_dispdec_dpp_top_dispdec 5720 // base address: 0xb58 5721 #define regDPP_TOP2_DPP_CONTROL 0x0f9b 5722 #define regDPP_TOP2_DPP_CONTROL_BASE_IDX 2 5723 #define regDPP_TOP2_DPP_SOFT_RESET 0x0f9c 5724 #define regDPP_TOP2_DPP_SOFT_RESET_BASE_IDX 2 5725 #define regDPP_TOP2_DPP_CRC_VAL_R_G 0x0f9d 5726 #define regDPP_TOP2_DPP_CRC_VAL_R_G_BASE_IDX 2 5727 #define regDPP_TOP2_DPP_CRC_VAL_B_A 0x0f9e 5728 #define regDPP_TOP2_DPP_CRC_VAL_B_A_BASE_IDX 2 5729 #define regDPP_TOP2_DPP_CRC_CTRL 0x0f9f 5730 #define regDPP_TOP2_DPP_CRC_CTRL_BASE_IDX 2 5731 #define regDPP_TOP2_HOST_READ_CONTROL 0x0fa0 5732 #define regDPP_TOP2_HOST_READ_CONTROL_BASE_IDX 2 5733 5734 5735 // addressBlock: dce_dc_dpp2_dispdec_dpp_dcperfmon_dc_perfmon_dispdec 5736 // base address: 0x43e8 5737 #define regDC_PERFMON13_PERFCOUNTER_CNTL 0x10fa 5738 #define regDC_PERFMON13_PERFCOUNTER_CNTL_BASE_IDX 2 5739 #define regDC_PERFMON13_PERFCOUNTER_CNTL2 0x10fb 5740 #define regDC_PERFMON13_PERFCOUNTER_CNTL2_BASE_IDX 2 5741 #define regDC_PERFMON13_PERFCOUNTER_STATE 0x10fc 5742 #define regDC_PERFMON13_PERFCOUNTER_STATE_BASE_IDX 2 5743 #define regDC_PERFMON13_PERFMON_CNTL 0x10fd 5744 #define regDC_PERFMON13_PERFMON_CNTL_BASE_IDX 2 5745 #define regDC_PERFMON13_PERFMON_CNTL2 0x10fe 5746 #define regDC_PERFMON13_PERFMON_CNTL2_BASE_IDX 2 5747 #define regDC_PERFMON13_PERFMON_CVALUE_INT_MISC 0x10ff 5748 #define regDC_PERFMON13_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 5749 #define regDC_PERFMON13_PERFMON_CVALUE_LOW 0x1100 5750 #define regDC_PERFMON13_PERFMON_CVALUE_LOW_BASE_IDX 2 5751 #define regDC_PERFMON13_PERFMON_HI 0x1101 5752 #define regDC_PERFMON13_PERFMON_HI_BASE_IDX 2 5753 #define regDC_PERFMON13_PERFMON_LOW 0x1102 5754 #define regDC_PERFMON13_PERFMON_LOW_BASE_IDX 2 5755 5756 5757 // addressBlock: dce_dc_dpp3_dispdec_cnvc_cfg_dispdec 5758 // base address: 0x1104 5759 #define regCNVC_CFG3_CNVC_SURFACE_PIXEL_FORMAT 0x1110 5760 #define regCNVC_CFG3_CNVC_SURFACE_PIXEL_FORMAT_BASE_IDX 2 5761 #define regCNVC_CFG3_FORMAT_CONTROL 0x1111 5762 #define regCNVC_CFG3_FORMAT_CONTROL_BASE_IDX 2 5763 #define regCNVC_CFG3_FCNV_FP_BIAS_R 0x1112 5764 #define regCNVC_CFG3_FCNV_FP_BIAS_R_BASE_IDX 2 5765 #define regCNVC_CFG3_FCNV_FP_BIAS_G 0x1113 5766 #define regCNVC_CFG3_FCNV_FP_BIAS_G_BASE_IDX 2 5767 #define regCNVC_CFG3_FCNV_FP_BIAS_B 0x1114 5768 #define regCNVC_CFG3_FCNV_FP_BIAS_B_BASE_IDX 2 5769 #define regCNVC_CFG3_FCNV_FP_SCALE_R 0x1115 5770 #define regCNVC_CFG3_FCNV_FP_SCALE_R_BASE_IDX 2 5771 #define regCNVC_CFG3_FCNV_FP_SCALE_G 0x1116 5772 #define regCNVC_CFG3_FCNV_FP_SCALE_G_BASE_IDX 2 5773 #define regCNVC_CFG3_FCNV_FP_SCALE_B 0x1117 5774 #define regCNVC_CFG3_FCNV_FP_SCALE_B_BASE_IDX 2 5775 #define regCNVC_CFG3_COLOR_KEYER_CONTROL 0x1118 5776 #define regCNVC_CFG3_COLOR_KEYER_CONTROL_BASE_IDX 2 5777 #define regCNVC_CFG3_COLOR_KEYER_ALPHA 0x1119 5778 #define regCNVC_CFG3_COLOR_KEYER_ALPHA_BASE_IDX 2 5779 #define regCNVC_CFG3_COLOR_KEYER_RED 0x111a 5780 #define regCNVC_CFG3_COLOR_KEYER_RED_BASE_IDX 2 5781 #define regCNVC_CFG3_COLOR_KEYER_GREEN 0x111b 5782 #define regCNVC_CFG3_COLOR_KEYER_GREEN_BASE_IDX 2 5783 #define regCNVC_CFG3_COLOR_KEYER_BLUE 0x111c 5784 #define regCNVC_CFG3_COLOR_KEYER_BLUE_BASE_IDX 2 5785 #define regCNVC_CFG3_ALPHA_2BIT_LUT 0x111e 5786 #define regCNVC_CFG3_ALPHA_2BIT_LUT_BASE_IDX 2 5787 #define regCNVC_CFG3_PRE_DEALPHA 0x111f 5788 #define regCNVC_CFG3_PRE_DEALPHA_BASE_IDX 2 5789 #define regCNVC_CFG3_PRE_CSC_MODE 0x1120 5790 #define regCNVC_CFG3_PRE_CSC_MODE_BASE_IDX 2 5791 #define regCNVC_CFG3_PRE_CSC_C11_C12 0x1121 5792 #define regCNVC_CFG3_PRE_CSC_C11_C12_BASE_IDX 2 5793 #define regCNVC_CFG3_PRE_CSC_C13_C14 0x1122 5794 #define regCNVC_CFG3_PRE_CSC_C13_C14_BASE_IDX 2 5795 #define regCNVC_CFG3_PRE_CSC_C21_C22 0x1123 5796 #define regCNVC_CFG3_PRE_CSC_C21_C22_BASE_IDX 2 5797 #define regCNVC_CFG3_PRE_CSC_C23_C24 0x1124 5798 #define regCNVC_CFG3_PRE_CSC_C23_C24_BASE_IDX 2 5799 #define regCNVC_CFG3_PRE_CSC_C31_C32 0x1125 5800 #define regCNVC_CFG3_PRE_CSC_C31_C32_BASE_IDX 2 5801 #define regCNVC_CFG3_PRE_CSC_C33_C34 0x1126 5802 #define regCNVC_CFG3_PRE_CSC_C33_C34_BASE_IDX 2 5803 #define regCNVC_CFG3_PRE_CSC_B_C11_C12 0x1127 5804 #define regCNVC_CFG3_PRE_CSC_B_C11_C12_BASE_IDX 2 5805 #define regCNVC_CFG3_PRE_CSC_B_C13_C14 0x1128 5806 #define regCNVC_CFG3_PRE_CSC_B_C13_C14_BASE_IDX 2 5807 #define regCNVC_CFG3_PRE_CSC_B_C21_C22 0x1129 5808 #define regCNVC_CFG3_PRE_CSC_B_C21_C22_BASE_IDX 2 5809 #define regCNVC_CFG3_PRE_CSC_B_C23_C24 0x112a 5810 #define regCNVC_CFG3_PRE_CSC_B_C23_C24_BASE_IDX 2 5811 #define regCNVC_CFG3_PRE_CSC_B_C31_C32 0x112b 5812 #define regCNVC_CFG3_PRE_CSC_B_C31_C32_BASE_IDX 2 5813 #define regCNVC_CFG3_PRE_CSC_B_C33_C34 0x112c 5814 #define regCNVC_CFG3_PRE_CSC_B_C33_C34_BASE_IDX 2 5815 #define regCNVC_CFG3_CNVC_COEF_FORMAT 0x112d 5816 #define regCNVC_CFG3_CNVC_COEF_FORMAT_BASE_IDX 2 5817 #define regCNVC_CFG3_PRE_DEGAM 0x112e 5818 #define regCNVC_CFG3_PRE_DEGAM_BASE_IDX 2 5819 #define regCNVC_CFG3_PRE_REALPHA 0x112f 5820 #define regCNVC_CFG3_PRE_REALPHA_BASE_IDX 2 5821 5822 5823 // addressBlock: dce_dc_dpp3_dispdec_cnvc_cur_dispdec 5824 // base address: 0x1104 5825 #define regCNVC_CUR3_CURSOR0_CONTROL 0x1132 5826 #define regCNVC_CUR3_CURSOR0_CONTROL_BASE_IDX 2 5827 #define regCNVC_CUR3_CURSOR0_COLOR0 0x1133 5828 #define regCNVC_CUR3_CURSOR0_COLOR0_BASE_IDX 2 5829 #define regCNVC_CUR3_CURSOR0_COLOR1 0x1134 5830 #define regCNVC_CUR3_CURSOR0_COLOR1_BASE_IDX 2 5831 #define regCNVC_CUR3_CURSOR0_FP_SCALE_BIAS 0x1135 5832 #define regCNVC_CUR3_CURSOR0_FP_SCALE_BIAS_BASE_IDX 2 5833 5834 5835 // addressBlock: dce_dc_dpp3_dispdec_dscl_dispdec 5836 // base address: 0x1104 5837 #define regDSCL3_SCL_COEF_RAM_TAP_SELECT 0x113a 5838 #define regDSCL3_SCL_COEF_RAM_TAP_SELECT_BASE_IDX 2 5839 #define regDSCL3_SCL_COEF_RAM_TAP_DATA 0x113b 5840 #define regDSCL3_SCL_COEF_RAM_TAP_DATA_BASE_IDX 2 5841 #define regDSCL3_SCL_MODE 0x113c 5842 #define regDSCL3_SCL_MODE_BASE_IDX 2 5843 #define regDSCL3_SCL_TAP_CONTROL 0x113d 5844 #define regDSCL3_SCL_TAP_CONTROL_BASE_IDX 2 5845 #define regDSCL3_DSCL_CONTROL 0x113e 5846 #define regDSCL3_DSCL_CONTROL_BASE_IDX 2 5847 #define regDSCL3_DSCL_2TAP_CONTROL 0x113f 5848 #define regDSCL3_DSCL_2TAP_CONTROL_BASE_IDX 2 5849 #define regDSCL3_SCL_MANUAL_REPLICATE_CONTROL 0x1140 5850 #define regDSCL3_SCL_MANUAL_REPLICATE_CONTROL_BASE_IDX 2 5851 #define regDSCL3_SCL_HORZ_FILTER_SCALE_RATIO 0x1141 5852 #define regDSCL3_SCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX 2 5853 #define regDSCL3_SCL_HORZ_FILTER_INIT 0x1142 5854 #define regDSCL3_SCL_HORZ_FILTER_INIT_BASE_IDX 2 5855 #define regDSCL3_SCL_HORZ_FILTER_SCALE_RATIO_C 0x1143 5856 #define regDSCL3_SCL_HORZ_FILTER_SCALE_RATIO_C_BASE_IDX 2 5857 #define regDSCL3_SCL_HORZ_FILTER_INIT_C 0x1144 5858 #define regDSCL3_SCL_HORZ_FILTER_INIT_C_BASE_IDX 2 5859 #define regDSCL3_SCL_VERT_FILTER_SCALE_RATIO 0x1145 5860 #define regDSCL3_SCL_VERT_FILTER_SCALE_RATIO_BASE_IDX 2 5861 #define regDSCL3_SCL_VERT_FILTER_INIT 0x1146 5862 #define regDSCL3_SCL_VERT_FILTER_INIT_BASE_IDX 2 5863 #define regDSCL3_SCL_VERT_FILTER_INIT_BOT 0x1147 5864 #define regDSCL3_SCL_VERT_FILTER_INIT_BOT_BASE_IDX 2 5865 #define regDSCL3_SCL_VERT_FILTER_SCALE_RATIO_C 0x1148 5866 #define regDSCL3_SCL_VERT_FILTER_SCALE_RATIO_C_BASE_IDX 2 5867 #define regDSCL3_SCL_VERT_FILTER_INIT_C 0x1149 5868 #define regDSCL3_SCL_VERT_FILTER_INIT_C_BASE_IDX 2 5869 #define regDSCL3_SCL_VERT_FILTER_INIT_BOT_C 0x114a 5870 #define regDSCL3_SCL_VERT_FILTER_INIT_BOT_C_BASE_IDX 2 5871 #define regDSCL3_SCL_BLACK_COLOR 0x114b 5872 #define regDSCL3_SCL_BLACK_COLOR_BASE_IDX 2 5873 #define regDSCL3_DSCL_UPDATE 0x114c 5874 #define regDSCL3_DSCL_UPDATE_BASE_IDX 2 5875 #define regDSCL3_DSCL_AUTOCAL 0x114d 5876 #define regDSCL3_DSCL_AUTOCAL_BASE_IDX 2 5877 #define regDSCL3_DSCL_EXT_OVERSCAN_LEFT_RIGHT 0x114e 5878 #define regDSCL3_DSCL_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX 2 5879 #define regDSCL3_DSCL_EXT_OVERSCAN_TOP_BOTTOM 0x114f 5880 #define regDSCL3_DSCL_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX 2 5881 #define regDSCL3_OTG_H_BLANK 0x1150 5882 #define regDSCL3_OTG_H_BLANK_BASE_IDX 2 5883 #define regDSCL3_OTG_V_BLANK 0x1151 5884 #define regDSCL3_OTG_V_BLANK_BASE_IDX 2 5885 #define regDSCL3_RECOUT_START 0x1152 5886 #define regDSCL3_RECOUT_START_BASE_IDX 2 5887 #define regDSCL3_RECOUT_SIZE 0x1153 5888 #define regDSCL3_RECOUT_SIZE_BASE_IDX 2 5889 #define regDSCL3_MPC_SIZE 0x1154 5890 #define regDSCL3_MPC_SIZE_BASE_IDX 2 5891 #define regDSCL3_LB_DATA_FORMAT 0x1155 5892 #define regDSCL3_LB_DATA_FORMAT_BASE_IDX 2 5893 #define regDSCL3_LB_MEMORY_CTRL 0x1156 5894 #define regDSCL3_LB_MEMORY_CTRL_BASE_IDX 2 5895 #define regDSCL3_LB_V_COUNTER 0x1157 5896 #define regDSCL3_LB_V_COUNTER_BASE_IDX 2 5897 #define regDSCL3_DSCL_MEM_PWR_CTRL 0x1158 5898 #define regDSCL3_DSCL_MEM_PWR_CTRL_BASE_IDX 2 5899 #define regDSCL3_DSCL_MEM_PWR_STATUS 0x1159 5900 #define regDSCL3_DSCL_MEM_PWR_STATUS_BASE_IDX 2 5901 #define regDSCL3_OBUF_CONTROL 0x115a 5902 #define regDSCL3_OBUF_CONTROL_BASE_IDX 2 5903 #define regDSCL3_OBUF_MEM_PWR_CTRL 0x115b 5904 #define regDSCL3_OBUF_MEM_PWR_CTRL_BASE_IDX 2 5905 5906 5907 // addressBlock: dce_dc_dpp3_dispdec_cm_dispdec 5908 // base address: 0x1104 5909 #define regCM3_CM_CONTROL 0x1161 5910 #define regCM3_CM_CONTROL_BASE_IDX 2 5911 #define regCM3_CM_POST_CSC_CONTROL 0x1162 5912 #define regCM3_CM_POST_CSC_CONTROL_BASE_IDX 2 5913 #define regCM3_CM_POST_CSC_C11_C12 0x1163 5914 #define regCM3_CM_POST_CSC_C11_C12_BASE_IDX 2 5915 #define regCM3_CM_POST_CSC_C13_C14 0x1164 5916 #define regCM3_CM_POST_CSC_C13_C14_BASE_IDX 2 5917 #define regCM3_CM_POST_CSC_C21_C22 0x1165 5918 #define regCM3_CM_POST_CSC_C21_C22_BASE_IDX 2 5919 #define regCM3_CM_POST_CSC_C23_C24 0x1166 5920 #define regCM3_CM_POST_CSC_C23_C24_BASE_IDX 2 5921 #define regCM3_CM_POST_CSC_C31_C32 0x1167 5922 #define regCM3_CM_POST_CSC_C31_C32_BASE_IDX 2 5923 #define regCM3_CM_POST_CSC_C33_C34 0x1168 5924 #define regCM3_CM_POST_CSC_C33_C34_BASE_IDX 2 5925 #define regCM3_CM_POST_CSC_B_C11_C12 0x1169 5926 #define regCM3_CM_POST_CSC_B_C11_C12_BASE_IDX 2 5927 #define regCM3_CM_POST_CSC_B_C13_C14 0x116a 5928 #define regCM3_CM_POST_CSC_B_C13_C14_BASE_IDX 2 5929 #define regCM3_CM_POST_CSC_B_C21_C22 0x116b 5930 #define regCM3_CM_POST_CSC_B_C21_C22_BASE_IDX 2 5931 #define regCM3_CM_POST_CSC_B_C23_C24 0x116c 5932 #define regCM3_CM_POST_CSC_B_C23_C24_BASE_IDX 2 5933 #define regCM3_CM_POST_CSC_B_C31_C32 0x116d 5934 #define regCM3_CM_POST_CSC_B_C31_C32_BASE_IDX 2 5935 #define regCM3_CM_POST_CSC_B_C33_C34 0x116e 5936 #define regCM3_CM_POST_CSC_B_C33_C34_BASE_IDX 2 5937 #define regCM3_CM_GAMUT_REMAP_CONTROL 0x116f 5938 #define regCM3_CM_GAMUT_REMAP_CONTROL_BASE_IDX 2 5939 #define regCM3_CM_GAMUT_REMAP_C11_C12 0x1170 5940 #define regCM3_CM_GAMUT_REMAP_C11_C12_BASE_IDX 2 5941 #define regCM3_CM_GAMUT_REMAP_C13_C14 0x1171 5942 #define regCM3_CM_GAMUT_REMAP_C13_C14_BASE_IDX 2 5943 #define regCM3_CM_GAMUT_REMAP_C21_C22 0x1172 5944 #define regCM3_CM_GAMUT_REMAP_C21_C22_BASE_IDX 2 5945 #define regCM3_CM_GAMUT_REMAP_C23_C24 0x1173 5946 #define regCM3_CM_GAMUT_REMAP_C23_C24_BASE_IDX 2 5947 #define regCM3_CM_GAMUT_REMAP_C31_C32 0x1174 5948 #define regCM3_CM_GAMUT_REMAP_C31_C32_BASE_IDX 2 5949 #define regCM3_CM_GAMUT_REMAP_C33_C34 0x1175 5950 #define regCM3_CM_GAMUT_REMAP_C33_C34_BASE_IDX 2 5951 #define regCM3_CM_GAMUT_REMAP_B_C11_C12 0x1176 5952 #define regCM3_CM_GAMUT_REMAP_B_C11_C12_BASE_IDX 2 5953 #define regCM3_CM_GAMUT_REMAP_B_C13_C14 0x1177 5954 #define regCM3_CM_GAMUT_REMAP_B_C13_C14_BASE_IDX 2 5955 #define regCM3_CM_GAMUT_REMAP_B_C21_C22 0x1178 5956 #define regCM3_CM_GAMUT_REMAP_B_C21_C22_BASE_IDX 2 5957 #define regCM3_CM_GAMUT_REMAP_B_C23_C24 0x1179 5958 #define regCM3_CM_GAMUT_REMAP_B_C23_C24_BASE_IDX 2 5959 #define regCM3_CM_GAMUT_REMAP_B_C31_C32 0x117a 5960 #define regCM3_CM_GAMUT_REMAP_B_C31_C32_BASE_IDX 2 5961 #define regCM3_CM_GAMUT_REMAP_B_C33_C34 0x117b 5962 #define regCM3_CM_GAMUT_REMAP_B_C33_C34_BASE_IDX 2 5963 #define regCM3_CM_BIAS_CR_R 0x117c 5964 #define regCM3_CM_BIAS_CR_R_BASE_IDX 2 5965 #define regCM3_CM_BIAS_Y_G_CB_B 0x117d 5966 #define regCM3_CM_BIAS_Y_G_CB_B_BASE_IDX 2 5967 #define regCM3_CM_GAMCOR_CONTROL 0x117e 5968 #define regCM3_CM_GAMCOR_CONTROL_BASE_IDX 2 5969 #define regCM3_CM_GAMCOR_LUT_INDEX 0x117f 5970 #define regCM3_CM_GAMCOR_LUT_INDEX_BASE_IDX 2 5971 #define regCM3_CM_GAMCOR_LUT_DATA 0x1180 5972 #define regCM3_CM_GAMCOR_LUT_DATA_BASE_IDX 2 5973 #define regCM3_CM_GAMCOR_LUT_CONTROL 0x1181 5974 #define regCM3_CM_GAMCOR_LUT_CONTROL_BASE_IDX 2 5975 #define regCM3_CM_GAMCOR_RAMA_START_CNTL_B 0x1182 5976 #define regCM3_CM_GAMCOR_RAMA_START_CNTL_B_BASE_IDX 2 5977 #define regCM3_CM_GAMCOR_RAMA_START_CNTL_G 0x1183 5978 #define regCM3_CM_GAMCOR_RAMA_START_CNTL_G_BASE_IDX 2 5979 #define regCM3_CM_GAMCOR_RAMA_START_CNTL_R 0x1184 5980 #define regCM3_CM_GAMCOR_RAMA_START_CNTL_R_BASE_IDX 2 5981 #define regCM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B 0x1185 5982 #define regCM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B_BASE_IDX 2 5983 #define regCM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G 0x1186 5984 #define regCM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G_BASE_IDX 2 5985 #define regCM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R 0x1187 5986 #define regCM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R_BASE_IDX 2 5987 #define regCM3_CM_GAMCOR_RAMA_START_BASE_CNTL_B 0x1188 5988 #define regCM3_CM_GAMCOR_RAMA_START_BASE_CNTL_B_BASE_IDX 2 5989 #define regCM3_CM_GAMCOR_RAMA_START_BASE_CNTL_G 0x1189 5990 #define regCM3_CM_GAMCOR_RAMA_START_BASE_CNTL_G_BASE_IDX 2 5991 #define regCM3_CM_GAMCOR_RAMA_START_BASE_CNTL_R 0x118a 5992 #define regCM3_CM_GAMCOR_RAMA_START_BASE_CNTL_R_BASE_IDX 2 5993 #define regCM3_CM_GAMCOR_RAMA_END_CNTL1_B 0x118b 5994 #define regCM3_CM_GAMCOR_RAMA_END_CNTL1_B_BASE_IDX 2 5995 #define regCM3_CM_GAMCOR_RAMA_END_CNTL2_B 0x118c 5996 #define regCM3_CM_GAMCOR_RAMA_END_CNTL2_B_BASE_IDX 2 5997 #define regCM3_CM_GAMCOR_RAMA_END_CNTL1_G 0x118d 5998 #define regCM3_CM_GAMCOR_RAMA_END_CNTL1_G_BASE_IDX 2 5999 #define regCM3_CM_GAMCOR_RAMA_END_CNTL2_G 0x118e 6000 #define regCM3_CM_GAMCOR_RAMA_END_CNTL2_G_BASE_IDX 2 6001 #define regCM3_CM_GAMCOR_RAMA_END_CNTL1_R 0x118f 6002 #define regCM3_CM_GAMCOR_RAMA_END_CNTL1_R_BASE_IDX 2 6003 #define regCM3_CM_GAMCOR_RAMA_END_CNTL2_R 0x1190 6004 #define regCM3_CM_GAMCOR_RAMA_END_CNTL2_R_BASE_IDX 2 6005 #define regCM3_CM_GAMCOR_RAMA_OFFSET_B 0x1191 6006 #define regCM3_CM_GAMCOR_RAMA_OFFSET_B_BASE_IDX 2 6007 #define regCM3_CM_GAMCOR_RAMA_OFFSET_G 0x1192 6008 #define regCM3_CM_GAMCOR_RAMA_OFFSET_G_BASE_IDX 2 6009 #define regCM3_CM_GAMCOR_RAMA_OFFSET_R 0x1193 6010 #define regCM3_CM_GAMCOR_RAMA_OFFSET_R_BASE_IDX 2 6011 #define regCM3_CM_GAMCOR_RAMA_REGION_0_1 0x1194 6012 #define regCM3_CM_GAMCOR_RAMA_REGION_0_1_BASE_IDX 2 6013 #define regCM3_CM_GAMCOR_RAMA_REGION_2_3 0x1195 6014 #define regCM3_CM_GAMCOR_RAMA_REGION_2_3_BASE_IDX 2 6015 #define regCM3_CM_GAMCOR_RAMA_REGION_4_5 0x1196 6016 #define regCM3_CM_GAMCOR_RAMA_REGION_4_5_BASE_IDX 2 6017 #define regCM3_CM_GAMCOR_RAMA_REGION_6_7 0x1197 6018 #define regCM3_CM_GAMCOR_RAMA_REGION_6_7_BASE_IDX 2 6019 #define regCM3_CM_GAMCOR_RAMA_REGION_8_9 0x1198 6020 #define regCM3_CM_GAMCOR_RAMA_REGION_8_9_BASE_IDX 2 6021 #define regCM3_CM_GAMCOR_RAMA_REGION_10_11 0x1199 6022 #define regCM3_CM_GAMCOR_RAMA_REGION_10_11_BASE_IDX 2 6023 #define regCM3_CM_GAMCOR_RAMA_REGION_12_13 0x119a 6024 #define regCM3_CM_GAMCOR_RAMA_REGION_12_13_BASE_IDX 2 6025 #define regCM3_CM_GAMCOR_RAMA_REGION_14_15 0x119b 6026 #define regCM3_CM_GAMCOR_RAMA_REGION_14_15_BASE_IDX 2 6027 #define regCM3_CM_GAMCOR_RAMA_REGION_16_17 0x119c 6028 #define regCM3_CM_GAMCOR_RAMA_REGION_16_17_BASE_IDX 2 6029 #define regCM3_CM_GAMCOR_RAMA_REGION_18_19 0x119d 6030 #define regCM3_CM_GAMCOR_RAMA_REGION_18_19_BASE_IDX 2 6031 #define regCM3_CM_GAMCOR_RAMA_REGION_20_21 0x119e 6032 #define regCM3_CM_GAMCOR_RAMA_REGION_20_21_BASE_IDX 2 6033 #define regCM3_CM_GAMCOR_RAMA_REGION_22_23 0x119f 6034 #define regCM3_CM_GAMCOR_RAMA_REGION_22_23_BASE_IDX 2 6035 #define regCM3_CM_GAMCOR_RAMA_REGION_24_25 0x11a0 6036 #define regCM3_CM_GAMCOR_RAMA_REGION_24_25_BASE_IDX 2 6037 #define regCM3_CM_GAMCOR_RAMA_REGION_26_27 0x11a1 6038 #define regCM3_CM_GAMCOR_RAMA_REGION_26_27_BASE_IDX 2 6039 #define regCM3_CM_GAMCOR_RAMA_REGION_28_29 0x11a2 6040 #define regCM3_CM_GAMCOR_RAMA_REGION_28_29_BASE_IDX 2 6041 #define regCM3_CM_GAMCOR_RAMA_REGION_30_31 0x11a3 6042 #define regCM3_CM_GAMCOR_RAMA_REGION_30_31_BASE_IDX 2 6043 #define regCM3_CM_GAMCOR_RAMA_REGION_32_33 0x11a4 6044 #define regCM3_CM_GAMCOR_RAMA_REGION_32_33_BASE_IDX 2 6045 #define regCM3_CM_GAMCOR_RAMB_START_CNTL_B 0x11a5 6046 #define regCM3_CM_GAMCOR_RAMB_START_CNTL_B_BASE_IDX 2 6047 #define regCM3_CM_GAMCOR_RAMB_START_CNTL_G 0x11a6 6048 #define regCM3_CM_GAMCOR_RAMB_START_CNTL_G_BASE_IDX 2 6049 #define regCM3_CM_GAMCOR_RAMB_START_CNTL_R 0x11a7 6050 #define regCM3_CM_GAMCOR_RAMB_START_CNTL_R_BASE_IDX 2 6051 #define regCM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B 0x11a8 6052 #define regCM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B_BASE_IDX 2 6053 #define regCM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G 0x11a9 6054 #define regCM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G_BASE_IDX 2 6055 #define regCM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R 0x11aa 6056 #define regCM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R_BASE_IDX 2 6057 #define regCM3_CM_GAMCOR_RAMB_START_BASE_CNTL_B 0x11ab 6058 #define regCM3_CM_GAMCOR_RAMB_START_BASE_CNTL_B_BASE_IDX 2 6059 #define regCM3_CM_GAMCOR_RAMB_START_BASE_CNTL_G 0x11ac 6060 #define regCM3_CM_GAMCOR_RAMB_START_BASE_CNTL_G_BASE_IDX 2 6061 #define regCM3_CM_GAMCOR_RAMB_START_BASE_CNTL_R 0x11ad 6062 #define regCM3_CM_GAMCOR_RAMB_START_BASE_CNTL_R_BASE_IDX 2 6063 #define regCM3_CM_GAMCOR_RAMB_END_CNTL1_B 0x11ae 6064 #define regCM3_CM_GAMCOR_RAMB_END_CNTL1_B_BASE_IDX 2 6065 #define regCM3_CM_GAMCOR_RAMB_END_CNTL2_B 0x11af 6066 #define regCM3_CM_GAMCOR_RAMB_END_CNTL2_B_BASE_IDX 2 6067 #define regCM3_CM_GAMCOR_RAMB_END_CNTL1_G 0x11b0 6068 #define regCM3_CM_GAMCOR_RAMB_END_CNTL1_G_BASE_IDX 2 6069 #define regCM3_CM_GAMCOR_RAMB_END_CNTL2_G 0x11b1 6070 #define regCM3_CM_GAMCOR_RAMB_END_CNTL2_G_BASE_IDX 2 6071 #define regCM3_CM_GAMCOR_RAMB_END_CNTL1_R 0x11b2 6072 #define regCM3_CM_GAMCOR_RAMB_END_CNTL1_R_BASE_IDX 2 6073 #define regCM3_CM_GAMCOR_RAMB_END_CNTL2_R 0x11b3 6074 #define regCM3_CM_GAMCOR_RAMB_END_CNTL2_R_BASE_IDX 2 6075 #define regCM3_CM_GAMCOR_RAMB_OFFSET_B 0x11b4 6076 #define regCM3_CM_GAMCOR_RAMB_OFFSET_B_BASE_IDX 2 6077 #define regCM3_CM_GAMCOR_RAMB_OFFSET_G 0x11b5 6078 #define regCM3_CM_GAMCOR_RAMB_OFFSET_G_BASE_IDX 2 6079 #define regCM3_CM_GAMCOR_RAMB_OFFSET_R 0x11b6 6080 #define regCM3_CM_GAMCOR_RAMB_OFFSET_R_BASE_IDX 2 6081 #define regCM3_CM_GAMCOR_RAMB_REGION_0_1 0x11b7 6082 #define regCM3_CM_GAMCOR_RAMB_REGION_0_1_BASE_IDX 2 6083 #define regCM3_CM_GAMCOR_RAMB_REGION_2_3 0x11b8 6084 #define regCM3_CM_GAMCOR_RAMB_REGION_2_3_BASE_IDX 2 6085 #define regCM3_CM_GAMCOR_RAMB_REGION_4_5 0x11b9 6086 #define regCM3_CM_GAMCOR_RAMB_REGION_4_5_BASE_IDX 2 6087 #define regCM3_CM_GAMCOR_RAMB_REGION_6_7 0x11ba 6088 #define regCM3_CM_GAMCOR_RAMB_REGION_6_7_BASE_IDX 2 6089 #define regCM3_CM_GAMCOR_RAMB_REGION_8_9 0x11bb 6090 #define regCM3_CM_GAMCOR_RAMB_REGION_8_9_BASE_IDX 2 6091 #define regCM3_CM_GAMCOR_RAMB_REGION_10_11 0x11bc 6092 #define regCM3_CM_GAMCOR_RAMB_REGION_10_11_BASE_IDX 2 6093 #define regCM3_CM_GAMCOR_RAMB_REGION_12_13 0x11bd 6094 #define regCM3_CM_GAMCOR_RAMB_REGION_12_13_BASE_IDX 2 6095 #define regCM3_CM_GAMCOR_RAMB_REGION_14_15 0x11be 6096 #define regCM3_CM_GAMCOR_RAMB_REGION_14_15_BASE_IDX 2 6097 #define regCM3_CM_GAMCOR_RAMB_REGION_16_17 0x11bf 6098 #define regCM3_CM_GAMCOR_RAMB_REGION_16_17_BASE_IDX 2 6099 #define regCM3_CM_GAMCOR_RAMB_REGION_18_19 0x11c0 6100 #define regCM3_CM_GAMCOR_RAMB_REGION_18_19_BASE_IDX 2 6101 #define regCM3_CM_GAMCOR_RAMB_REGION_20_21 0x11c1 6102 #define regCM3_CM_GAMCOR_RAMB_REGION_20_21_BASE_IDX 2 6103 #define regCM3_CM_GAMCOR_RAMB_REGION_22_23 0x11c2 6104 #define regCM3_CM_GAMCOR_RAMB_REGION_22_23_BASE_IDX 2 6105 #define regCM3_CM_GAMCOR_RAMB_REGION_24_25 0x11c3 6106 #define regCM3_CM_GAMCOR_RAMB_REGION_24_25_BASE_IDX 2 6107 #define regCM3_CM_GAMCOR_RAMB_REGION_26_27 0x11c4 6108 #define regCM3_CM_GAMCOR_RAMB_REGION_26_27_BASE_IDX 2 6109 #define regCM3_CM_GAMCOR_RAMB_REGION_28_29 0x11c5 6110 #define regCM3_CM_GAMCOR_RAMB_REGION_28_29_BASE_IDX 2 6111 #define regCM3_CM_GAMCOR_RAMB_REGION_30_31 0x11c6 6112 #define regCM3_CM_GAMCOR_RAMB_REGION_30_31_BASE_IDX 2 6113 #define regCM3_CM_GAMCOR_RAMB_REGION_32_33 0x11c7 6114 #define regCM3_CM_GAMCOR_RAMB_REGION_32_33_BASE_IDX 2 6115 #define regCM3_CM_BLNDGAM_CONTROL 0x11c8 6116 #define regCM3_CM_BLNDGAM_CONTROL_BASE_IDX 2 6117 #define regCM3_CM_BLNDGAM_LUT_INDEX 0x11c9 6118 #define regCM3_CM_BLNDGAM_LUT_INDEX_BASE_IDX 2 6119 #define regCM3_CM_BLNDGAM_LUT_DATA 0x11ca 6120 #define regCM3_CM_BLNDGAM_LUT_DATA_BASE_IDX 2 6121 #define regCM3_CM_BLNDGAM_LUT_CONTROL 0x11cb 6122 #define regCM3_CM_BLNDGAM_LUT_CONTROL_BASE_IDX 2 6123 #define regCM3_CM_BLNDGAM_RAMA_START_CNTL_B 0x11cc 6124 #define regCM3_CM_BLNDGAM_RAMA_START_CNTL_B_BASE_IDX 2 6125 #define regCM3_CM_BLNDGAM_RAMA_START_CNTL_G 0x11cd 6126 #define regCM3_CM_BLNDGAM_RAMA_START_CNTL_G_BASE_IDX 2 6127 #define regCM3_CM_BLNDGAM_RAMA_START_CNTL_R 0x11ce 6128 #define regCM3_CM_BLNDGAM_RAMA_START_CNTL_R_BASE_IDX 2 6129 #define regCM3_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_B 0x11cf 6130 #define regCM3_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_B_BASE_IDX 2 6131 #define regCM3_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_G 0x11d0 6132 #define regCM3_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_G_BASE_IDX 2 6133 #define regCM3_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_R 0x11d1 6134 #define regCM3_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_R_BASE_IDX 2 6135 #define regCM3_CM_BLNDGAM_RAMA_START_BASE_CNTL_B 0x11d2 6136 #define regCM3_CM_BLNDGAM_RAMA_START_BASE_CNTL_B_BASE_IDX 2 6137 #define regCM3_CM_BLNDGAM_RAMA_START_BASE_CNTL_G 0x11d3 6138 #define regCM3_CM_BLNDGAM_RAMA_START_BASE_CNTL_G_BASE_IDX 2 6139 #define regCM3_CM_BLNDGAM_RAMA_START_BASE_CNTL_R 0x11d4 6140 #define regCM3_CM_BLNDGAM_RAMA_START_BASE_CNTL_R_BASE_IDX 2 6141 #define regCM3_CM_BLNDGAM_RAMA_END_CNTL1_B 0x11d5 6142 #define regCM3_CM_BLNDGAM_RAMA_END_CNTL1_B_BASE_IDX 2 6143 #define regCM3_CM_BLNDGAM_RAMA_END_CNTL2_B 0x11d6 6144 #define regCM3_CM_BLNDGAM_RAMA_END_CNTL2_B_BASE_IDX 2 6145 #define regCM3_CM_BLNDGAM_RAMA_END_CNTL1_G 0x11d7 6146 #define regCM3_CM_BLNDGAM_RAMA_END_CNTL1_G_BASE_IDX 2 6147 #define regCM3_CM_BLNDGAM_RAMA_END_CNTL2_G 0x11d8 6148 #define regCM3_CM_BLNDGAM_RAMA_END_CNTL2_G_BASE_IDX 2 6149 #define regCM3_CM_BLNDGAM_RAMA_END_CNTL1_R 0x11d9 6150 #define regCM3_CM_BLNDGAM_RAMA_END_CNTL1_R_BASE_IDX 2 6151 #define regCM3_CM_BLNDGAM_RAMA_END_CNTL2_R 0x11da 6152 #define regCM3_CM_BLNDGAM_RAMA_END_CNTL2_R_BASE_IDX 2 6153 #define regCM3_CM_BLNDGAM_RAMA_OFFSET_B 0x11db 6154 #define regCM3_CM_BLNDGAM_RAMA_OFFSET_B_BASE_IDX 2 6155 #define regCM3_CM_BLNDGAM_RAMA_OFFSET_G 0x11dc 6156 #define regCM3_CM_BLNDGAM_RAMA_OFFSET_G_BASE_IDX 2 6157 #define regCM3_CM_BLNDGAM_RAMA_OFFSET_R 0x11dd 6158 #define regCM3_CM_BLNDGAM_RAMA_OFFSET_R_BASE_IDX 2 6159 #define regCM3_CM_BLNDGAM_RAMA_REGION_0_1 0x11de 6160 #define regCM3_CM_BLNDGAM_RAMA_REGION_0_1_BASE_IDX 2 6161 #define regCM3_CM_BLNDGAM_RAMA_REGION_2_3 0x11df 6162 #define regCM3_CM_BLNDGAM_RAMA_REGION_2_3_BASE_IDX 2 6163 #define regCM3_CM_BLNDGAM_RAMA_REGION_4_5 0x11e0 6164 #define regCM3_CM_BLNDGAM_RAMA_REGION_4_5_BASE_IDX 2 6165 #define regCM3_CM_BLNDGAM_RAMA_REGION_6_7 0x11e1 6166 #define regCM3_CM_BLNDGAM_RAMA_REGION_6_7_BASE_IDX 2 6167 #define regCM3_CM_BLNDGAM_RAMA_REGION_8_9 0x11e2 6168 #define regCM3_CM_BLNDGAM_RAMA_REGION_8_9_BASE_IDX 2 6169 #define regCM3_CM_BLNDGAM_RAMA_REGION_10_11 0x11e3 6170 #define regCM3_CM_BLNDGAM_RAMA_REGION_10_11_BASE_IDX 2 6171 #define regCM3_CM_BLNDGAM_RAMA_REGION_12_13 0x11e4 6172 #define regCM3_CM_BLNDGAM_RAMA_REGION_12_13_BASE_IDX 2 6173 #define regCM3_CM_BLNDGAM_RAMA_REGION_14_15 0x11e5 6174 #define regCM3_CM_BLNDGAM_RAMA_REGION_14_15_BASE_IDX 2 6175 #define regCM3_CM_BLNDGAM_RAMA_REGION_16_17 0x11e6 6176 #define regCM3_CM_BLNDGAM_RAMA_REGION_16_17_BASE_IDX 2 6177 #define regCM3_CM_BLNDGAM_RAMA_REGION_18_19 0x11e7 6178 #define regCM3_CM_BLNDGAM_RAMA_REGION_18_19_BASE_IDX 2 6179 #define regCM3_CM_BLNDGAM_RAMA_REGION_20_21 0x11e8 6180 #define regCM3_CM_BLNDGAM_RAMA_REGION_20_21_BASE_IDX 2 6181 #define regCM3_CM_BLNDGAM_RAMA_REGION_22_23 0x11e9 6182 #define regCM3_CM_BLNDGAM_RAMA_REGION_22_23_BASE_IDX 2 6183 #define regCM3_CM_BLNDGAM_RAMA_REGION_24_25 0x11ea 6184 #define regCM3_CM_BLNDGAM_RAMA_REGION_24_25_BASE_IDX 2 6185 #define regCM3_CM_BLNDGAM_RAMA_REGION_26_27 0x11eb 6186 #define regCM3_CM_BLNDGAM_RAMA_REGION_26_27_BASE_IDX 2 6187 #define regCM3_CM_BLNDGAM_RAMA_REGION_28_29 0x11ec 6188 #define regCM3_CM_BLNDGAM_RAMA_REGION_28_29_BASE_IDX 2 6189 #define regCM3_CM_BLNDGAM_RAMA_REGION_30_31 0x11ed 6190 #define regCM3_CM_BLNDGAM_RAMA_REGION_30_31_BASE_IDX 2 6191 #define regCM3_CM_BLNDGAM_RAMA_REGION_32_33 0x11ee 6192 #define regCM3_CM_BLNDGAM_RAMA_REGION_32_33_BASE_IDX 2 6193 #define regCM3_CM_BLNDGAM_RAMB_START_CNTL_B 0x11ef 6194 #define regCM3_CM_BLNDGAM_RAMB_START_CNTL_B_BASE_IDX 2 6195 #define regCM3_CM_BLNDGAM_RAMB_START_CNTL_G 0x11f0 6196 #define regCM3_CM_BLNDGAM_RAMB_START_CNTL_G_BASE_IDX 2 6197 #define regCM3_CM_BLNDGAM_RAMB_START_CNTL_R 0x11f1 6198 #define regCM3_CM_BLNDGAM_RAMB_START_CNTL_R_BASE_IDX 2 6199 #define regCM3_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_B 0x11f2 6200 #define regCM3_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_B_BASE_IDX 2 6201 #define regCM3_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_G 0x11f3 6202 #define regCM3_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_G_BASE_IDX 2 6203 #define regCM3_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_R 0x11f4 6204 #define regCM3_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_R_BASE_IDX 2 6205 #define regCM3_CM_BLNDGAM_RAMB_START_BASE_CNTL_B 0x11f5 6206 #define regCM3_CM_BLNDGAM_RAMB_START_BASE_CNTL_B_BASE_IDX 2 6207 #define regCM3_CM_BLNDGAM_RAMB_START_BASE_CNTL_G 0x11f6 6208 #define regCM3_CM_BLNDGAM_RAMB_START_BASE_CNTL_G_BASE_IDX 2 6209 #define regCM3_CM_BLNDGAM_RAMB_START_BASE_CNTL_R 0x11f7 6210 #define regCM3_CM_BLNDGAM_RAMB_START_BASE_CNTL_R_BASE_IDX 2 6211 #define regCM3_CM_BLNDGAM_RAMB_END_CNTL1_B 0x11f8 6212 #define regCM3_CM_BLNDGAM_RAMB_END_CNTL1_B_BASE_IDX 2 6213 #define regCM3_CM_BLNDGAM_RAMB_END_CNTL2_B 0x11f9 6214 #define regCM3_CM_BLNDGAM_RAMB_END_CNTL2_B_BASE_IDX 2 6215 #define regCM3_CM_BLNDGAM_RAMB_END_CNTL1_G 0x11fa 6216 #define regCM3_CM_BLNDGAM_RAMB_END_CNTL1_G_BASE_IDX 2 6217 #define regCM3_CM_BLNDGAM_RAMB_END_CNTL2_G 0x11fb 6218 #define regCM3_CM_BLNDGAM_RAMB_END_CNTL2_G_BASE_IDX 2 6219 #define regCM3_CM_BLNDGAM_RAMB_END_CNTL1_R 0x11fc 6220 #define regCM3_CM_BLNDGAM_RAMB_END_CNTL1_R_BASE_IDX 2 6221 #define regCM3_CM_BLNDGAM_RAMB_END_CNTL2_R 0x11fd 6222 #define regCM3_CM_BLNDGAM_RAMB_END_CNTL2_R_BASE_IDX 2 6223 #define regCM3_CM_BLNDGAM_RAMB_OFFSET_B 0x11fe 6224 #define regCM3_CM_BLNDGAM_RAMB_OFFSET_B_BASE_IDX 2 6225 #define regCM3_CM_BLNDGAM_RAMB_OFFSET_G 0x11ff 6226 #define regCM3_CM_BLNDGAM_RAMB_OFFSET_G_BASE_IDX 2 6227 #define regCM3_CM_BLNDGAM_RAMB_OFFSET_R 0x1200 6228 #define regCM3_CM_BLNDGAM_RAMB_OFFSET_R_BASE_IDX 2 6229 #define regCM3_CM_BLNDGAM_RAMB_REGION_0_1 0x1201 6230 #define regCM3_CM_BLNDGAM_RAMB_REGION_0_1_BASE_IDX 2 6231 #define regCM3_CM_BLNDGAM_RAMB_REGION_2_3 0x1202 6232 #define regCM3_CM_BLNDGAM_RAMB_REGION_2_3_BASE_IDX 2 6233 #define regCM3_CM_BLNDGAM_RAMB_REGION_4_5 0x1203 6234 #define regCM3_CM_BLNDGAM_RAMB_REGION_4_5_BASE_IDX 2 6235 #define regCM3_CM_BLNDGAM_RAMB_REGION_6_7 0x1204 6236 #define regCM3_CM_BLNDGAM_RAMB_REGION_6_7_BASE_IDX 2 6237 #define regCM3_CM_BLNDGAM_RAMB_REGION_8_9 0x1205 6238 #define regCM3_CM_BLNDGAM_RAMB_REGION_8_9_BASE_IDX 2 6239 #define regCM3_CM_BLNDGAM_RAMB_REGION_10_11 0x1206 6240 #define regCM3_CM_BLNDGAM_RAMB_REGION_10_11_BASE_IDX 2 6241 #define regCM3_CM_BLNDGAM_RAMB_REGION_12_13 0x1207 6242 #define regCM3_CM_BLNDGAM_RAMB_REGION_12_13_BASE_IDX 2 6243 #define regCM3_CM_BLNDGAM_RAMB_REGION_14_15 0x1208 6244 #define regCM3_CM_BLNDGAM_RAMB_REGION_14_15_BASE_IDX 2 6245 #define regCM3_CM_BLNDGAM_RAMB_REGION_16_17 0x1209 6246 #define regCM3_CM_BLNDGAM_RAMB_REGION_16_17_BASE_IDX 2 6247 #define regCM3_CM_BLNDGAM_RAMB_REGION_18_19 0x120a 6248 #define regCM3_CM_BLNDGAM_RAMB_REGION_18_19_BASE_IDX 2 6249 #define regCM3_CM_BLNDGAM_RAMB_REGION_20_21 0x120b 6250 #define regCM3_CM_BLNDGAM_RAMB_REGION_20_21_BASE_IDX 2 6251 #define regCM3_CM_BLNDGAM_RAMB_REGION_22_23 0x120c 6252 #define regCM3_CM_BLNDGAM_RAMB_REGION_22_23_BASE_IDX 2 6253 #define regCM3_CM_BLNDGAM_RAMB_REGION_24_25 0x120d 6254 #define regCM3_CM_BLNDGAM_RAMB_REGION_24_25_BASE_IDX 2 6255 #define regCM3_CM_BLNDGAM_RAMB_REGION_26_27 0x120e 6256 #define regCM3_CM_BLNDGAM_RAMB_REGION_26_27_BASE_IDX 2 6257 #define regCM3_CM_BLNDGAM_RAMB_REGION_28_29 0x120f 6258 #define regCM3_CM_BLNDGAM_RAMB_REGION_28_29_BASE_IDX 2 6259 #define regCM3_CM_BLNDGAM_RAMB_REGION_30_31 0x1210 6260 #define regCM3_CM_BLNDGAM_RAMB_REGION_30_31_BASE_IDX 2 6261 #define regCM3_CM_BLNDGAM_RAMB_REGION_32_33 0x1211 6262 #define regCM3_CM_BLNDGAM_RAMB_REGION_32_33_BASE_IDX 2 6263 #define regCM3_CM_HDR_MULT_COEF 0x1212 6264 #define regCM3_CM_HDR_MULT_COEF_BASE_IDX 2 6265 #define regCM3_CM_MEM_PWR_CTRL 0x1213 6266 #define regCM3_CM_MEM_PWR_CTRL_BASE_IDX 2 6267 #define regCM3_CM_MEM_PWR_STATUS 0x1214 6268 #define regCM3_CM_MEM_PWR_STATUS_BASE_IDX 2 6269 #define regCM3_CM_DEALPHA 0x1216 6270 #define regCM3_CM_DEALPHA_BASE_IDX 2 6271 #define regCM3_CM_COEF_FORMAT 0x1217 6272 #define regCM3_CM_COEF_FORMAT_BASE_IDX 2 6273 #define regCM3_CM_SHAPER_CONTROL 0x1218 6274 #define regCM3_CM_SHAPER_CONTROL_BASE_IDX 2 6275 #define regCM3_CM_SHAPER_OFFSET_R 0x1219 6276 #define regCM3_CM_SHAPER_OFFSET_R_BASE_IDX 2 6277 #define regCM3_CM_SHAPER_OFFSET_G 0x121a 6278 #define regCM3_CM_SHAPER_OFFSET_G_BASE_IDX 2 6279 #define regCM3_CM_SHAPER_OFFSET_B 0x121b 6280 #define regCM3_CM_SHAPER_OFFSET_B_BASE_IDX 2 6281 #define regCM3_CM_SHAPER_SCALE_R 0x121c 6282 #define regCM3_CM_SHAPER_SCALE_R_BASE_IDX 2 6283 #define regCM3_CM_SHAPER_SCALE_G_B 0x121d 6284 #define regCM3_CM_SHAPER_SCALE_G_B_BASE_IDX 2 6285 #define regCM3_CM_SHAPER_LUT_INDEX 0x121e 6286 #define regCM3_CM_SHAPER_LUT_INDEX_BASE_IDX 2 6287 #define regCM3_CM_SHAPER_LUT_DATA 0x121f 6288 #define regCM3_CM_SHAPER_LUT_DATA_BASE_IDX 2 6289 #define regCM3_CM_SHAPER_LUT_WRITE_EN_MASK 0x1220 6290 #define regCM3_CM_SHAPER_LUT_WRITE_EN_MASK_BASE_IDX 2 6291 #define regCM3_CM_SHAPER_RAMA_START_CNTL_B 0x1221 6292 #define regCM3_CM_SHAPER_RAMA_START_CNTL_B_BASE_IDX 2 6293 #define regCM3_CM_SHAPER_RAMA_START_CNTL_G 0x1222 6294 #define regCM3_CM_SHAPER_RAMA_START_CNTL_G_BASE_IDX 2 6295 #define regCM3_CM_SHAPER_RAMA_START_CNTL_R 0x1223 6296 #define regCM3_CM_SHAPER_RAMA_START_CNTL_R_BASE_IDX 2 6297 #define regCM3_CM_SHAPER_RAMA_END_CNTL_B 0x1224 6298 #define regCM3_CM_SHAPER_RAMA_END_CNTL_B_BASE_IDX 2 6299 #define regCM3_CM_SHAPER_RAMA_END_CNTL_G 0x1225 6300 #define regCM3_CM_SHAPER_RAMA_END_CNTL_G_BASE_IDX 2 6301 #define regCM3_CM_SHAPER_RAMA_END_CNTL_R 0x1226 6302 #define regCM3_CM_SHAPER_RAMA_END_CNTL_R_BASE_IDX 2 6303 #define regCM3_CM_SHAPER_RAMA_REGION_0_1 0x1227 6304 #define regCM3_CM_SHAPER_RAMA_REGION_0_1_BASE_IDX 2 6305 #define regCM3_CM_SHAPER_RAMA_REGION_2_3 0x1228 6306 #define regCM3_CM_SHAPER_RAMA_REGION_2_3_BASE_IDX 2 6307 #define regCM3_CM_SHAPER_RAMA_REGION_4_5 0x1229 6308 #define regCM3_CM_SHAPER_RAMA_REGION_4_5_BASE_IDX 2 6309 #define regCM3_CM_SHAPER_RAMA_REGION_6_7 0x122a 6310 #define regCM3_CM_SHAPER_RAMA_REGION_6_7_BASE_IDX 2 6311 #define regCM3_CM_SHAPER_RAMA_REGION_8_9 0x122b 6312 #define regCM3_CM_SHAPER_RAMA_REGION_8_9_BASE_IDX 2 6313 #define regCM3_CM_SHAPER_RAMA_REGION_10_11 0x122c 6314 #define regCM3_CM_SHAPER_RAMA_REGION_10_11_BASE_IDX 2 6315 #define regCM3_CM_SHAPER_RAMA_REGION_12_13 0x122d 6316 #define regCM3_CM_SHAPER_RAMA_REGION_12_13_BASE_IDX 2 6317 #define regCM3_CM_SHAPER_RAMA_REGION_14_15 0x122e 6318 #define regCM3_CM_SHAPER_RAMA_REGION_14_15_BASE_IDX 2 6319 #define regCM3_CM_SHAPER_RAMA_REGION_16_17 0x122f 6320 #define regCM3_CM_SHAPER_RAMA_REGION_16_17_BASE_IDX 2 6321 #define regCM3_CM_SHAPER_RAMA_REGION_18_19 0x1230 6322 #define regCM3_CM_SHAPER_RAMA_REGION_18_19_BASE_IDX 2 6323 #define regCM3_CM_SHAPER_RAMA_REGION_20_21 0x1231 6324 #define regCM3_CM_SHAPER_RAMA_REGION_20_21_BASE_IDX 2 6325 #define regCM3_CM_SHAPER_RAMA_REGION_22_23 0x1232 6326 #define regCM3_CM_SHAPER_RAMA_REGION_22_23_BASE_IDX 2 6327 #define regCM3_CM_SHAPER_RAMA_REGION_24_25 0x1233 6328 #define regCM3_CM_SHAPER_RAMA_REGION_24_25_BASE_IDX 2 6329 #define regCM3_CM_SHAPER_RAMA_REGION_26_27 0x1234 6330 #define regCM3_CM_SHAPER_RAMA_REGION_26_27_BASE_IDX 2 6331 #define regCM3_CM_SHAPER_RAMA_REGION_28_29 0x1235 6332 #define regCM3_CM_SHAPER_RAMA_REGION_28_29_BASE_IDX 2 6333 #define regCM3_CM_SHAPER_RAMA_REGION_30_31 0x1236 6334 #define regCM3_CM_SHAPER_RAMA_REGION_30_31_BASE_IDX 2 6335 #define regCM3_CM_SHAPER_RAMA_REGION_32_33 0x1237 6336 #define regCM3_CM_SHAPER_RAMA_REGION_32_33_BASE_IDX 2 6337 #define regCM3_CM_SHAPER_RAMB_START_CNTL_B 0x1238 6338 #define regCM3_CM_SHAPER_RAMB_START_CNTL_B_BASE_IDX 2 6339 #define regCM3_CM_SHAPER_RAMB_START_CNTL_G 0x1239 6340 #define regCM3_CM_SHAPER_RAMB_START_CNTL_G_BASE_IDX 2 6341 #define regCM3_CM_SHAPER_RAMB_START_CNTL_R 0x123a 6342 #define regCM3_CM_SHAPER_RAMB_START_CNTL_R_BASE_IDX 2 6343 #define regCM3_CM_SHAPER_RAMB_END_CNTL_B 0x123b 6344 #define regCM3_CM_SHAPER_RAMB_END_CNTL_B_BASE_IDX 2 6345 #define regCM3_CM_SHAPER_RAMB_END_CNTL_G 0x123c 6346 #define regCM3_CM_SHAPER_RAMB_END_CNTL_G_BASE_IDX 2 6347 #define regCM3_CM_SHAPER_RAMB_END_CNTL_R 0x123d 6348 #define regCM3_CM_SHAPER_RAMB_END_CNTL_R_BASE_IDX 2 6349 #define regCM3_CM_SHAPER_RAMB_REGION_0_1 0x123e 6350 #define regCM3_CM_SHAPER_RAMB_REGION_0_1_BASE_IDX 2 6351 #define regCM3_CM_SHAPER_RAMB_REGION_2_3 0x123f 6352 #define regCM3_CM_SHAPER_RAMB_REGION_2_3_BASE_IDX 2 6353 #define regCM3_CM_SHAPER_RAMB_REGION_4_5 0x1240 6354 #define regCM3_CM_SHAPER_RAMB_REGION_4_5_BASE_IDX 2 6355 #define regCM3_CM_SHAPER_RAMB_REGION_6_7 0x1241 6356 #define regCM3_CM_SHAPER_RAMB_REGION_6_7_BASE_IDX 2 6357 #define regCM3_CM_SHAPER_RAMB_REGION_8_9 0x1242 6358 #define regCM3_CM_SHAPER_RAMB_REGION_8_9_BASE_IDX 2 6359 #define regCM3_CM_SHAPER_RAMB_REGION_10_11 0x1243 6360 #define regCM3_CM_SHAPER_RAMB_REGION_10_11_BASE_IDX 2 6361 #define regCM3_CM_SHAPER_RAMB_REGION_12_13 0x1244 6362 #define regCM3_CM_SHAPER_RAMB_REGION_12_13_BASE_IDX 2 6363 #define regCM3_CM_SHAPER_RAMB_REGION_14_15 0x1245 6364 #define regCM3_CM_SHAPER_RAMB_REGION_14_15_BASE_IDX 2 6365 #define regCM3_CM_SHAPER_RAMB_REGION_16_17 0x1246 6366 #define regCM3_CM_SHAPER_RAMB_REGION_16_17_BASE_IDX 2 6367 #define regCM3_CM_SHAPER_RAMB_REGION_18_19 0x1247 6368 #define regCM3_CM_SHAPER_RAMB_REGION_18_19_BASE_IDX 2 6369 #define regCM3_CM_SHAPER_RAMB_REGION_20_21 0x1248 6370 #define regCM3_CM_SHAPER_RAMB_REGION_20_21_BASE_IDX 2 6371 #define regCM3_CM_SHAPER_RAMB_REGION_22_23 0x1249 6372 #define regCM3_CM_SHAPER_RAMB_REGION_22_23_BASE_IDX 2 6373 #define regCM3_CM_SHAPER_RAMB_REGION_24_25 0x124a 6374 #define regCM3_CM_SHAPER_RAMB_REGION_24_25_BASE_IDX 2 6375 #define regCM3_CM_SHAPER_RAMB_REGION_26_27 0x124b 6376 #define regCM3_CM_SHAPER_RAMB_REGION_26_27_BASE_IDX 2 6377 #define regCM3_CM_SHAPER_RAMB_REGION_28_29 0x124c 6378 #define regCM3_CM_SHAPER_RAMB_REGION_28_29_BASE_IDX 2 6379 #define regCM3_CM_SHAPER_RAMB_REGION_30_31 0x124d 6380 #define regCM3_CM_SHAPER_RAMB_REGION_30_31_BASE_IDX 2 6381 #define regCM3_CM_SHAPER_RAMB_REGION_32_33 0x124e 6382 #define regCM3_CM_SHAPER_RAMB_REGION_32_33_BASE_IDX 2 6383 #define regCM3_CM_MEM_PWR_CTRL2 0x124f 6384 #define regCM3_CM_MEM_PWR_CTRL2_BASE_IDX 2 6385 #define regCM3_CM_MEM_PWR_STATUS2 0x1250 6386 #define regCM3_CM_MEM_PWR_STATUS2_BASE_IDX 2 6387 #define regCM3_CM_3DLUT_MODE 0x1251 6388 #define regCM3_CM_3DLUT_MODE_BASE_IDX 2 6389 #define regCM3_CM_3DLUT_INDEX 0x1252 6390 #define regCM3_CM_3DLUT_INDEX_BASE_IDX 2 6391 #define regCM3_CM_3DLUT_DATA 0x1253 6392 #define regCM3_CM_3DLUT_DATA_BASE_IDX 2 6393 #define regCM3_CM_3DLUT_DATA_30BIT 0x1254 6394 #define regCM3_CM_3DLUT_DATA_30BIT_BASE_IDX 2 6395 #define regCM3_CM_3DLUT_READ_WRITE_CONTROL 0x1255 6396 #define regCM3_CM_3DLUT_READ_WRITE_CONTROL_BASE_IDX 2 6397 #define regCM3_CM_3DLUT_OUT_NORM_FACTOR 0x1256 6398 #define regCM3_CM_3DLUT_OUT_NORM_FACTOR_BASE_IDX 2 6399 #define regCM3_CM_3DLUT_OUT_OFFSET_R 0x1257 6400 #define regCM3_CM_3DLUT_OUT_OFFSET_R_BASE_IDX 2 6401 #define regCM3_CM_3DLUT_OUT_OFFSET_G 0x1258 6402 #define regCM3_CM_3DLUT_OUT_OFFSET_G_BASE_IDX 2 6403 #define regCM3_CM_3DLUT_OUT_OFFSET_B 0x1259 6404 #define regCM3_CM_3DLUT_OUT_OFFSET_B_BASE_IDX 2 6405 #define regCM3_CM_TEST_DEBUG_INDEX 0x125a 6406 #define regCM3_CM_TEST_DEBUG_INDEX_BASE_IDX 2 6407 #define regCM3_CM_TEST_DEBUG_DATA 0x125b 6408 #define regCM3_CM_TEST_DEBUG_DATA_BASE_IDX 2 6409 6410 6411 // addressBlock: dce_dc_dpp3_dispdec_dpp_top_dispdec 6412 // base address: 0x1104 6413 #define regDPP_TOP3_DPP_CONTROL 0x1106 6414 #define regDPP_TOP3_DPP_CONTROL_BASE_IDX 2 6415 #define regDPP_TOP3_DPP_SOFT_RESET 0x1107 6416 #define regDPP_TOP3_DPP_SOFT_RESET_BASE_IDX 2 6417 #define regDPP_TOP3_DPP_CRC_VAL_R_G 0x1108 6418 #define regDPP_TOP3_DPP_CRC_VAL_R_G_BASE_IDX 2 6419 #define regDPP_TOP3_DPP_CRC_VAL_B_A 0x1109 6420 #define regDPP_TOP3_DPP_CRC_VAL_B_A_BASE_IDX 2 6421 #define regDPP_TOP3_DPP_CRC_CTRL 0x110a 6422 #define regDPP_TOP3_DPP_CRC_CTRL_BASE_IDX 2 6423 #define regDPP_TOP3_HOST_READ_CONTROL 0x110b 6424 #define regDPP_TOP3_HOST_READ_CONTROL_BASE_IDX 2 6425 6426 6427 // addressBlock: dce_dc_dpp3_dispdec_dpp_dcperfmon_dc_perfmon_dispdec 6428 // base address: 0x4994 6429 #define regDC_PERFMON14_PERFCOUNTER_CNTL 0x1265 6430 #define regDC_PERFMON14_PERFCOUNTER_CNTL_BASE_IDX 2 6431 #define regDC_PERFMON14_PERFCOUNTER_CNTL2 0x1266 6432 #define regDC_PERFMON14_PERFCOUNTER_CNTL2_BASE_IDX 2 6433 #define regDC_PERFMON14_PERFCOUNTER_STATE 0x1267 6434 #define regDC_PERFMON14_PERFCOUNTER_STATE_BASE_IDX 2 6435 #define regDC_PERFMON14_PERFMON_CNTL 0x1268 6436 #define regDC_PERFMON14_PERFMON_CNTL_BASE_IDX 2 6437 #define regDC_PERFMON14_PERFMON_CNTL2 0x1269 6438 #define regDC_PERFMON14_PERFMON_CNTL2_BASE_IDX 2 6439 #define regDC_PERFMON14_PERFMON_CVALUE_INT_MISC 0x126a 6440 #define regDC_PERFMON14_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 6441 #define regDC_PERFMON14_PERFMON_CVALUE_LOW 0x126b 6442 #define regDC_PERFMON14_PERFMON_CVALUE_LOW_BASE_IDX 2 6443 #define regDC_PERFMON14_PERFMON_HI 0x126c 6444 #define regDC_PERFMON14_PERFMON_HI_BASE_IDX 2 6445 #define regDC_PERFMON14_PERFMON_LOW 0x126d 6446 #define regDC_PERFMON14_PERFMON_LOW_BASE_IDX 2 6447 6448 6449 // addressBlock: dce_dc_mpc_mpcc0_dispdec 6450 // base address: 0x0 6451 #define regMPCC0_MPCC_TOP_SEL 0x0000 6452 #define regMPCC0_MPCC_TOP_SEL_BASE_IDX 3 6453 #define regMPCC0_MPCC_BOT_SEL 0x0001 6454 #define regMPCC0_MPCC_BOT_SEL_BASE_IDX 3 6455 #define regMPCC0_MPCC_OPP_ID 0x0002 6456 #define regMPCC0_MPCC_OPP_ID_BASE_IDX 3 6457 #define regMPCC0_MPCC_CONTROL 0x0003 6458 #define regMPCC0_MPCC_CONTROL_BASE_IDX 3 6459 #define regMPCC0_MPCC_SM_CONTROL 0x0004 6460 #define regMPCC0_MPCC_SM_CONTROL_BASE_IDX 3 6461 #define regMPCC0_MPCC_UPDATE_LOCK_SEL 0x0005 6462 #define regMPCC0_MPCC_UPDATE_LOCK_SEL_BASE_IDX 3 6463 #define regMPCC0_MPCC_TOP_GAIN 0x0006 6464 #define regMPCC0_MPCC_TOP_GAIN_BASE_IDX 3 6465 #define regMPCC0_MPCC_BOT_GAIN_INSIDE 0x0007 6466 #define regMPCC0_MPCC_BOT_GAIN_INSIDE_BASE_IDX 3 6467 #define regMPCC0_MPCC_BOT_GAIN_OUTSIDE 0x0008 6468 #define regMPCC0_MPCC_BOT_GAIN_OUTSIDE_BASE_IDX 3 6469 #define regMPCC0_MPCC_BG_R_CR 0x0009 6470 #define regMPCC0_MPCC_BG_R_CR_BASE_IDX 3 6471 #define regMPCC0_MPCC_BG_G_Y 0x000a 6472 #define regMPCC0_MPCC_BG_G_Y_BASE_IDX 3 6473 #define regMPCC0_MPCC_BG_B_CB 0x000b 6474 #define regMPCC0_MPCC_BG_B_CB_BASE_IDX 3 6475 #define regMPCC0_MPCC_MEM_PWR_CTRL 0x000c 6476 #define regMPCC0_MPCC_MEM_PWR_CTRL_BASE_IDX 3 6477 #define regMPCC0_MPCC_STATUS 0x000d 6478 #define regMPCC0_MPCC_STATUS_BASE_IDX 3 6479 6480 6481 // addressBlock: dce_dc_mpc_mpcc1_dispdec 6482 // base address: 0x80 6483 #define regMPCC1_MPCC_TOP_SEL 0x0020 6484 #define regMPCC1_MPCC_TOP_SEL_BASE_IDX 3 6485 #define regMPCC1_MPCC_BOT_SEL 0x0021 6486 #define regMPCC1_MPCC_BOT_SEL_BASE_IDX 3 6487 #define regMPCC1_MPCC_OPP_ID 0x0022 6488 #define regMPCC1_MPCC_OPP_ID_BASE_IDX 3 6489 #define regMPCC1_MPCC_CONTROL 0x0023 6490 #define regMPCC1_MPCC_CONTROL_BASE_IDX 3 6491 #define regMPCC1_MPCC_SM_CONTROL 0x0024 6492 #define regMPCC1_MPCC_SM_CONTROL_BASE_IDX 3 6493 #define regMPCC1_MPCC_UPDATE_LOCK_SEL 0x0025 6494 #define regMPCC1_MPCC_UPDATE_LOCK_SEL_BASE_IDX 3 6495 #define regMPCC1_MPCC_TOP_GAIN 0x0026 6496 #define regMPCC1_MPCC_TOP_GAIN_BASE_IDX 3 6497 #define regMPCC1_MPCC_BOT_GAIN_INSIDE 0x0027 6498 #define regMPCC1_MPCC_BOT_GAIN_INSIDE_BASE_IDX 3 6499 #define regMPCC1_MPCC_BOT_GAIN_OUTSIDE 0x0028 6500 #define regMPCC1_MPCC_BOT_GAIN_OUTSIDE_BASE_IDX 3 6501 #define regMPCC1_MPCC_BG_R_CR 0x0029 6502 #define regMPCC1_MPCC_BG_R_CR_BASE_IDX 3 6503 #define regMPCC1_MPCC_BG_G_Y 0x002a 6504 #define regMPCC1_MPCC_BG_G_Y_BASE_IDX 3 6505 #define regMPCC1_MPCC_BG_B_CB 0x002b 6506 #define regMPCC1_MPCC_BG_B_CB_BASE_IDX 3 6507 #define regMPCC1_MPCC_MEM_PWR_CTRL 0x002c 6508 #define regMPCC1_MPCC_MEM_PWR_CTRL_BASE_IDX 3 6509 #define regMPCC1_MPCC_STATUS 0x002d 6510 #define regMPCC1_MPCC_STATUS_BASE_IDX 3 6511 6512 6513 // addressBlock: dce_dc_mpc_mpcc2_dispdec 6514 // base address: 0x100 6515 #define regMPCC2_MPCC_TOP_SEL 0x0040 6516 #define regMPCC2_MPCC_TOP_SEL_BASE_IDX 3 6517 #define regMPCC2_MPCC_BOT_SEL 0x0041 6518 #define regMPCC2_MPCC_BOT_SEL_BASE_IDX 3 6519 #define regMPCC2_MPCC_OPP_ID 0x0042 6520 #define regMPCC2_MPCC_OPP_ID_BASE_IDX 3 6521 #define regMPCC2_MPCC_CONTROL 0x0043 6522 #define regMPCC2_MPCC_CONTROL_BASE_IDX 3 6523 #define regMPCC2_MPCC_SM_CONTROL 0x0044 6524 #define regMPCC2_MPCC_SM_CONTROL_BASE_IDX 3 6525 #define regMPCC2_MPCC_UPDATE_LOCK_SEL 0x0045 6526 #define regMPCC2_MPCC_UPDATE_LOCK_SEL_BASE_IDX 3 6527 #define regMPCC2_MPCC_TOP_GAIN 0x0046 6528 #define regMPCC2_MPCC_TOP_GAIN_BASE_IDX 3 6529 #define regMPCC2_MPCC_BOT_GAIN_INSIDE 0x0047 6530 #define regMPCC2_MPCC_BOT_GAIN_INSIDE_BASE_IDX 3 6531 #define regMPCC2_MPCC_BOT_GAIN_OUTSIDE 0x0048 6532 #define regMPCC2_MPCC_BOT_GAIN_OUTSIDE_BASE_IDX 3 6533 #define regMPCC2_MPCC_BG_R_CR 0x0049 6534 #define regMPCC2_MPCC_BG_R_CR_BASE_IDX 3 6535 #define regMPCC2_MPCC_BG_G_Y 0x004a 6536 #define regMPCC2_MPCC_BG_G_Y_BASE_IDX 3 6537 #define regMPCC2_MPCC_BG_B_CB 0x004b 6538 #define regMPCC2_MPCC_BG_B_CB_BASE_IDX 3 6539 #define regMPCC2_MPCC_MEM_PWR_CTRL 0x004c 6540 #define regMPCC2_MPCC_MEM_PWR_CTRL_BASE_IDX 3 6541 #define regMPCC2_MPCC_STATUS 0x004d 6542 #define regMPCC2_MPCC_STATUS_BASE_IDX 3 6543 6544 6545 // addressBlock: dce_dc_mpc_mpcc3_dispdec 6546 // base address: 0x180 6547 #define regMPCC3_MPCC_TOP_SEL 0x0060 6548 #define regMPCC3_MPCC_TOP_SEL_BASE_IDX 3 6549 #define regMPCC3_MPCC_BOT_SEL 0x0061 6550 #define regMPCC3_MPCC_BOT_SEL_BASE_IDX 3 6551 #define regMPCC3_MPCC_OPP_ID 0x0062 6552 #define regMPCC3_MPCC_OPP_ID_BASE_IDX 3 6553 #define regMPCC3_MPCC_CONTROL 0x0063 6554 #define regMPCC3_MPCC_CONTROL_BASE_IDX 3 6555 #define regMPCC3_MPCC_SM_CONTROL 0x0064 6556 #define regMPCC3_MPCC_SM_CONTROL_BASE_IDX 3 6557 #define regMPCC3_MPCC_UPDATE_LOCK_SEL 0x0065 6558 #define regMPCC3_MPCC_UPDATE_LOCK_SEL_BASE_IDX 3 6559 #define regMPCC3_MPCC_TOP_GAIN 0x0066 6560 #define regMPCC3_MPCC_TOP_GAIN_BASE_IDX 3 6561 #define regMPCC3_MPCC_BOT_GAIN_INSIDE 0x0067 6562 #define regMPCC3_MPCC_BOT_GAIN_INSIDE_BASE_IDX 3 6563 #define regMPCC3_MPCC_BOT_GAIN_OUTSIDE 0x0068 6564 #define regMPCC3_MPCC_BOT_GAIN_OUTSIDE_BASE_IDX 3 6565 #define regMPCC3_MPCC_BG_R_CR 0x0069 6566 #define regMPCC3_MPCC_BG_R_CR_BASE_IDX 3 6567 #define regMPCC3_MPCC_BG_G_Y 0x006a 6568 #define regMPCC3_MPCC_BG_G_Y_BASE_IDX 3 6569 #define regMPCC3_MPCC_BG_B_CB 0x006b 6570 #define regMPCC3_MPCC_BG_B_CB_BASE_IDX 3 6571 #define regMPCC3_MPCC_MEM_PWR_CTRL 0x006c 6572 #define regMPCC3_MPCC_MEM_PWR_CTRL_BASE_IDX 3 6573 #define regMPCC3_MPCC_STATUS 0x006d 6574 #define regMPCC3_MPCC_STATUS_BASE_IDX 3 6575 6576 6577 // addressBlock: dce_dc_mpc_mpc_cfg_dispdec 6578 // base address: 0x0 6579 #define regMPC_CLOCK_CONTROL 0x0500 6580 #define regMPC_CLOCK_CONTROL_BASE_IDX 3 6581 #define regMPC_SOFT_RESET 0x0501 6582 #define regMPC_SOFT_RESET_BASE_IDX 3 6583 #define regMPC_CRC_CTRL 0x0502 6584 #define regMPC_CRC_CTRL_BASE_IDX 3 6585 #define regMPC_CRC_SEL_CONTROL 0x0503 6586 #define regMPC_CRC_SEL_CONTROL_BASE_IDX 3 6587 #define regMPC_CRC_RESULT_AR 0x0504 6588 #define regMPC_CRC_RESULT_AR_BASE_IDX 3 6589 #define regMPC_CRC_RESULT_GB 0x0505 6590 #define regMPC_CRC_RESULT_GB_BASE_IDX 3 6591 #define regMPC_CRC_RESULT_C 0x0506 6592 #define regMPC_CRC_RESULT_C_BASE_IDX 3 6593 #define regMPC_PERFMON_EVENT_CTRL 0x0509 6594 #define regMPC_PERFMON_EVENT_CTRL_BASE_IDX 3 6595 #define regMPC_BYPASS_BG_AR 0x050a 6596 #define regMPC_BYPASS_BG_AR_BASE_IDX 3 6597 #define regMPC_BYPASS_BG_GB 0x050b 6598 #define regMPC_BYPASS_BG_GB_BASE_IDX 3 6599 #define regMPC_HOST_READ_CONTROL 0x050c 6600 #define regMPC_HOST_READ_CONTROL_BASE_IDX 3 6601 #define regMPC_DPP_PENDING_STATUS 0x050d 6602 #define regMPC_DPP_PENDING_STATUS_BASE_IDX 3 6603 #define regMPC_PENDING_STATUS_MISC 0x050e 6604 #define regMPC_PENDING_STATUS_MISC_BASE_IDX 3 6605 #define regADR_CFG_CUR_VUPDATE_LOCK_SET0 0x050f 6606 #define regADR_CFG_CUR_VUPDATE_LOCK_SET0_BASE_IDX 3 6607 #define regADR_CFG_VUPDATE_LOCK_SET0 0x0510 6608 #define regADR_CFG_VUPDATE_LOCK_SET0_BASE_IDX 3 6609 #define regADR_VUPDATE_LOCK_SET0 0x0511 6610 #define regADR_VUPDATE_LOCK_SET0_BASE_IDX 3 6611 #define regCFG_VUPDATE_LOCK_SET0 0x0512 6612 #define regCFG_VUPDATE_LOCK_SET0_BASE_IDX 3 6613 #define regCUR_VUPDATE_LOCK_SET0 0x0513 6614 #define regCUR_VUPDATE_LOCK_SET0_BASE_IDX 3 6615 #define regADR_CFG_CUR_VUPDATE_LOCK_SET1 0x0514 6616 #define regADR_CFG_CUR_VUPDATE_LOCK_SET1_BASE_IDX 3 6617 #define regADR_CFG_VUPDATE_LOCK_SET1 0x0515 6618 #define regADR_CFG_VUPDATE_LOCK_SET1_BASE_IDX 3 6619 #define regADR_VUPDATE_LOCK_SET1 0x0516 6620 #define regADR_VUPDATE_LOCK_SET1_BASE_IDX 3 6621 #define regCFG_VUPDATE_LOCK_SET1 0x0517 6622 #define regCFG_VUPDATE_LOCK_SET1_BASE_IDX 3 6623 #define regCUR_VUPDATE_LOCK_SET1 0x0518 6624 #define regCUR_VUPDATE_LOCK_SET1_BASE_IDX 3 6625 #define regADR_CFG_CUR_VUPDATE_LOCK_SET2 0x0519 6626 #define regADR_CFG_CUR_VUPDATE_LOCK_SET2_BASE_IDX 3 6627 #define regADR_CFG_VUPDATE_LOCK_SET2 0x051a 6628 #define regADR_CFG_VUPDATE_LOCK_SET2_BASE_IDX 3 6629 #define regADR_VUPDATE_LOCK_SET2 0x051b 6630 #define regADR_VUPDATE_LOCK_SET2_BASE_IDX 3 6631 #define regCFG_VUPDATE_LOCK_SET2 0x051c 6632 #define regCFG_VUPDATE_LOCK_SET2_BASE_IDX 3 6633 #define regCUR_VUPDATE_LOCK_SET2 0x051d 6634 #define regCUR_VUPDATE_LOCK_SET2_BASE_IDX 3 6635 #define regADR_CFG_CUR_VUPDATE_LOCK_SET3 0x051e 6636 #define regADR_CFG_CUR_VUPDATE_LOCK_SET3_BASE_IDX 3 6637 #define regADR_CFG_VUPDATE_LOCK_SET3 0x051f 6638 #define regADR_CFG_VUPDATE_LOCK_SET3_BASE_IDX 3 6639 #define regADR_VUPDATE_LOCK_SET3 0x0520 6640 #define regADR_VUPDATE_LOCK_SET3_BASE_IDX 3 6641 #define regCFG_VUPDATE_LOCK_SET3 0x0521 6642 #define regCFG_VUPDATE_LOCK_SET3_BASE_IDX 3 6643 #define regCUR_VUPDATE_LOCK_SET3 0x0522 6644 #define regCUR_VUPDATE_LOCK_SET3_BASE_IDX 3 6645 #define regMPC_DWB0_MUX 0x055c 6646 #define regMPC_DWB0_MUX_BASE_IDX 3 6647 6648 6649 // addressBlock: dce_dc_mpc_mpc_dcperfmon_dc_perfmon_dispdec 6650 // base address: 0x1901c 6651 #define regDC_PERFMON15_PERFCOUNTER_CNTL 0x08c7 6652 #define regDC_PERFMON15_PERFCOUNTER_CNTL_BASE_IDX 3 6653 #define regDC_PERFMON15_PERFCOUNTER_CNTL2 0x08c8 6654 #define regDC_PERFMON15_PERFCOUNTER_CNTL2_BASE_IDX 3 6655 #define regDC_PERFMON15_PERFCOUNTER_STATE 0x08c9 6656 #define regDC_PERFMON15_PERFCOUNTER_STATE_BASE_IDX 3 6657 #define regDC_PERFMON15_PERFMON_CNTL 0x08ca 6658 #define regDC_PERFMON15_PERFMON_CNTL_BASE_IDX 3 6659 #define regDC_PERFMON15_PERFMON_CNTL2 0x08cb 6660 #define regDC_PERFMON15_PERFMON_CNTL2_BASE_IDX 3 6661 #define regDC_PERFMON15_PERFMON_CVALUE_INT_MISC 0x08cc 6662 #define regDC_PERFMON15_PERFMON_CVALUE_INT_MISC_BASE_IDX 3 6663 #define regDC_PERFMON15_PERFMON_CVALUE_LOW 0x08cd 6664 #define regDC_PERFMON15_PERFMON_CVALUE_LOW_BASE_IDX 3 6665 #define regDC_PERFMON15_PERFMON_HI 0x08ce 6666 #define regDC_PERFMON15_PERFMON_HI_BASE_IDX 3 6667 #define regDC_PERFMON15_PERFMON_LOW 0x08cf 6668 #define regDC_PERFMON15_PERFMON_LOW_BASE_IDX 3 6669 6670 6671 // addressBlock: dce_dc_mpc_mpcc_ogam0_dispdec 6672 // base address: 0x0 6673 #define regMPCC_OGAM0_MPCC_OGAM_CONTROL 0x0100 6674 #define regMPCC_OGAM0_MPCC_OGAM_CONTROL_BASE_IDX 3 6675 #define regMPCC_OGAM0_MPCC_OGAM_LUT_INDEX 0x0101 6676 #define regMPCC_OGAM0_MPCC_OGAM_LUT_INDEX_BASE_IDX 3 6677 #define regMPCC_OGAM0_MPCC_OGAM_LUT_DATA 0x0102 6678 #define regMPCC_OGAM0_MPCC_OGAM_LUT_DATA_BASE_IDX 3 6679 #define regMPCC_OGAM0_MPCC_OGAM_LUT_CONTROL 0x0103 6680 #define regMPCC_OGAM0_MPCC_OGAM_LUT_CONTROL_BASE_IDX 3 6681 #define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_B 0x0104 6682 #define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_B_BASE_IDX 3 6683 #define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_G 0x0105 6684 #define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_G_BASE_IDX 3 6685 #define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_R 0x0106 6686 #define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_R_BASE_IDX 3 6687 #define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B 0x0107 6688 #define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B_BASE_IDX 3 6689 #define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G 0x0108 6690 #define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G_BASE_IDX 3 6691 #define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R 0x0109 6692 #define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R_BASE_IDX 3 6693 #define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_B 0x010a 6694 #define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_B_BASE_IDX 3 6695 #define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_G 0x010b 6696 #define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_G_BASE_IDX 3 6697 #define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_R 0x010c 6698 #define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_R_BASE_IDX 3 6699 #define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_B 0x010d 6700 #define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_B_BASE_IDX 3 6701 #define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_B 0x010e 6702 #define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_B_BASE_IDX 3 6703 #define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_G 0x010f 6704 #define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_G_BASE_IDX 3 6705 #define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_G 0x0110 6706 #define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_G_BASE_IDX 3 6707 #define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_R 0x0111 6708 #define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_R_BASE_IDX 3 6709 #define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_R 0x0112 6710 #define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_R_BASE_IDX 3 6711 #define regMPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_B 0x0113 6712 #define regMPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_B_BASE_IDX 3 6713 #define regMPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_G 0x0114 6714 #define regMPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_G_BASE_IDX 3 6715 #define regMPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_R 0x0115 6716 #define regMPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_R_BASE_IDX 3 6717 #define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1 0x0116 6718 #define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1_BASE_IDX 3 6719 #define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_2_3 0x0117 6720 #define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_2_3_BASE_IDX 3 6721 #define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_4_5 0x0118 6722 #define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_4_5_BASE_IDX 3 6723 #define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_6_7 0x0119 6724 #define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_6_7_BASE_IDX 3 6725 #define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_8_9 0x011a 6726 #define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_8_9_BASE_IDX 3 6727 #define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_10_11 0x011b 6728 #define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_10_11_BASE_IDX 3 6729 #define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_12_13 0x011c 6730 #define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_12_13_BASE_IDX 3 6731 #define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_14_15 0x011d 6732 #define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_14_15_BASE_IDX 3 6733 #define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_16_17 0x011e 6734 #define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_16_17_BASE_IDX 3 6735 #define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_18_19 0x011f 6736 #define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_18_19_BASE_IDX 3 6737 #define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_20_21 0x0120 6738 #define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_20_21_BASE_IDX 3 6739 #define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_22_23 0x0121 6740 #define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_22_23_BASE_IDX 3 6741 #define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_24_25 0x0122 6742 #define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_24_25_BASE_IDX 3 6743 #define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_26_27 0x0123 6744 #define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_26_27_BASE_IDX 3 6745 #define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_28_29 0x0124 6746 #define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_28_29_BASE_IDX 3 6747 #define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_30_31 0x0125 6748 #define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_30_31_BASE_IDX 3 6749 #define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_32_33 0x0126 6750 #define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_32_33_BASE_IDX 3 6751 #define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_B 0x0127 6752 #define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_B_BASE_IDX 3 6753 #define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_G 0x0128 6754 #define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_G_BASE_IDX 3 6755 #define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_R 0x0129 6756 #define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_R_BASE_IDX 3 6757 #define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B 0x012a 6758 #define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B_BASE_IDX 3 6759 #define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G 0x012b 6760 #define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G_BASE_IDX 3 6761 #define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R 0x012c 6762 #define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R_BASE_IDX 3 6763 #define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_B 0x012d 6764 #define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_B_BASE_IDX 3 6765 #define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_G 0x012e 6766 #define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_G_BASE_IDX 3 6767 #define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_R 0x012f 6768 #define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_R_BASE_IDX 3 6769 #define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_B 0x0130 6770 #define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_B_BASE_IDX 3 6771 #define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_B 0x0131 6772 #define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_B_BASE_IDX 3 6773 #define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_G 0x0132 6774 #define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_G_BASE_IDX 3 6775 #define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_G 0x0133 6776 #define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_G_BASE_IDX 3 6777 #define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_R 0x0134 6778 #define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_R_BASE_IDX 3 6779 #define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_R 0x0135 6780 #define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_R_BASE_IDX 3 6781 #define regMPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_B 0x0136 6782 #define regMPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_B_BASE_IDX 3 6783 #define regMPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_G 0x0137 6784 #define regMPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_G_BASE_IDX 3 6785 #define regMPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_R 0x0138 6786 #define regMPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_R_BASE_IDX 3 6787 #define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1 0x0139 6788 #define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1_BASE_IDX 3 6789 #define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_2_3 0x013a 6790 #define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_2_3_BASE_IDX 3 6791 #define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_4_5 0x013b 6792 #define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_4_5_BASE_IDX 3 6793 #define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_6_7 0x013c 6794 #define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_6_7_BASE_IDX 3 6795 #define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_8_9 0x013d 6796 #define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_8_9_BASE_IDX 3 6797 #define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_10_11 0x013e 6798 #define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_10_11_BASE_IDX 3 6799 #define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_12_13 0x013f 6800 #define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_12_13_BASE_IDX 3 6801 #define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_14_15 0x0140 6802 #define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_14_15_BASE_IDX 3 6803 #define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_16_17 0x0141 6804 #define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_16_17_BASE_IDX 3 6805 #define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_18_19 0x0142 6806 #define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_18_19_BASE_IDX 3 6807 #define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_20_21 0x0143 6808 #define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_20_21_BASE_IDX 3 6809 #define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_22_23 0x0144 6810 #define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_22_23_BASE_IDX 3 6811 #define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_24_25 0x0145 6812 #define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_24_25_BASE_IDX 3 6813 #define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_26_27 0x0146 6814 #define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_26_27_BASE_IDX 3 6815 #define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_28_29 0x0147 6816 #define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_28_29_BASE_IDX 3 6817 #define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_30_31 0x0148 6818 #define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_30_31_BASE_IDX 3 6819 #define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_32_33 0x0149 6820 #define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_32_33_BASE_IDX 3 6821 #define regMPCC_OGAM0_MPCC_GAMUT_REMAP_COEF_FORMAT 0x014a 6822 #define regMPCC_OGAM0_MPCC_GAMUT_REMAP_COEF_FORMAT_BASE_IDX 3 6823 #define regMPCC_OGAM0_MPCC_GAMUT_REMAP_MODE 0x014b 6824 #define regMPCC_OGAM0_MPCC_GAMUT_REMAP_MODE_BASE_IDX 3 6825 #define regMPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_A 0x014c 6826 #define regMPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_A_BASE_IDX 3 6827 #define regMPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_A 0x014d 6828 #define regMPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_A_BASE_IDX 3 6829 #define regMPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_A 0x014e 6830 #define regMPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_A_BASE_IDX 3 6831 #define regMPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_A 0x014f 6832 #define regMPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_A_BASE_IDX 3 6833 #define regMPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_A 0x0150 6834 #define regMPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_A_BASE_IDX 3 6835 #define regMPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_A 0x0151 6836 #define regMPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_A_BASE_IDX 3 6837 #define regMPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_B 0x0152 6838 #define regMPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_B_BASE_IDX 3 6839 #define regMPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_B 0x0153 6840 #define regMPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_B_BASE_IDX 3 6841 #define regMPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_B 0x0154 6842 #define regMPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_B_BASE_IDX 3 6843 #define regMPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_B 0x0155 6844 #define regMPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_B_BASE_IDX 3 6845 #define regMPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_B 0x0156 6846 #define regMPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_B_BASE_IDX 3 6847 #define regMPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_B 0x0157 6848 #define regMPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_B_BASE_IDX 3 6849 6850 6851 // addressBlock: dce_dc_mpc_mpcc_ogam1_dispdec 6852 // base address: 0x200 6853 #define regMPCC_OGAM1_MPCC_OGAM_CONTROL 0x0180 6854 #define regMPCC_OGAM1_MPCC_OGAM_CONTROL_BASE_IDX 3 6855 #define regMPCC_OGAM1_MPCC_OGAM_LUT_INDEX 0x0181 6856 #define regMPCC_OGAM1_MPCC_OGAM_LUT_INDEX_BASE_IDX 3 6857 #define regMPCC_OGAM1_MPCC_OGAM_LUT_DATA 0x0182 6858 #define regMPCC_OGAM1_MPCC_OGAM_LUT_DATA_BASE_IDX 3 6859 #define regMPCC_OGAM1_MPCC_OGAM_LUT_CONTROL 0x0183 6860 #define regMPCC_OGAM1_MPCC_OGAM_LUT_CONTROL_BASE_IDX 3 6861 #define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_B 0x0184 6862 #define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_B_BASE_IDX 3 6863 #define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_G 0x0185 6864 #define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_G_BASE_IDX 3 6865 #define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_R 0x0186 6866 #define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_R_BASE_IDX 3 6867 #define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B 0x0187 6868 #define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B_BASE_IDX 3 6869 #define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G 0x0188 6870 #define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G_BASE_IDX 3 6871 #define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R 0x0189 6872 #define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R_BASE_IDX 3 6873 #define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_B 0x018a 6874 #define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_B_BASE_IDX 3 6875 #define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_G 0x018b 6876 #define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_G_BASE_IDX 3 6877 #define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_R 0x018c 6878 #define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_R_BASE_IDX 3 6879 #define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_B 0x018d 6880 #define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_B_BASE_IDX 3 6881 #define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_B 0x018e 6882 #define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_B_BASE_IDX 3 6883 #define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_G 0x018f 6884 #define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_G_BASE_IDX 3 6885 #define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_G 0x0190 6886 #define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_G_BASE_IDX 3 6887 #define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_R 0x0191 6888 #define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_R_BASE_IDX 3 6889 #define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_R 0x0192 6890 #define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_R_BASE_IDX 3 6891 #define regMPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_B 0x0193 6892 #define regMPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_B_BASE_IDX 3 6893 #define regMPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_G 0x0194 6894 #define regMPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_G_BASE_IDX 3 6895 #define regMPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_R 0x0195 6896 #define regMPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_R_BASE_IDX 3 6897 #define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_0_1 0x0196 6898 #define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_0_1_BASE_IDX 3 6899 #define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_2_3 0x0197 6900 #define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_2_3_BASE_IDX 3 6901 #define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_4_5 0x0198 6902 #define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_4_5_BASE_IDX 3 6903 #define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_6_7 0x0199 6904 #define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_6_7_BASE_IDX 3 6905 #define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_8_9 0x019a 6906 #define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_8_9_BASE_IDX 3 6907 #define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_10_11 0x019b 6908 #define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_10_11_BASE_IDX 3 6909 #define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_12_13 0x019c 6910 #define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_12_13_BASE_IDX 3 6911 #define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_14_15 0x019d 6912 #define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_14_15_BASE_IDX 3 6913 #define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_16_17 0x019e 6914 #define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_16_17_BASE_IDX 3 6915 #define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_18_19 0x019f 6916 #define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_18_19_BASE_IDX 3 6917 #define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_20_21 0x01a0 6918 #define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_20_21_BASE_IDX 3 6919 #define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_22_23 0x01a1 6920 #define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_22_23_BASE_IDX 3 6921 #define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_24_25 0x01a2 6922 #define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_24_25_BASE_IDX 3 6923 #define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_26_27 0x01a3 6924 #define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_26_27_BASE_IDX 3 6925 #define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_28_29 0x01a4 6926 #define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_28_29_BASE_IDX 3 6927 #define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_30_31 0x01a5 6928 #define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_30_31_BASE_IDX 3 6929 #define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_32_33 0x01a6 6930 #define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_32_33_BASE_IDX 3 6931 #define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_B 0x01a7 6932 #define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_B_BASE_IDX 3 6933 #define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_G 0x01a8 6934 #define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_G_BASE_IDX 3 6935 #define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_R 0x01a9 6936 #define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_R_BASE_IDX 3 6937 #define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B 0x01aa 6938 #define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B_BASE_IDX 3 6939 #define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G 0x01ab 6940 #define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G_BASE_IDX 3 6941 #define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R 0x01ac 6942 #define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R_BASE_IDX 3 6943 #define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_B 0x01ad 6944 #define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_B_BASE_IDX 3 6945 #define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_G 0x01ae 6946 #define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_G_BASE_IDX 3 6947 #define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_R 0x01af 6948 #define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_R_BASE_IDX 3 6949 #define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_B 0x01b0 6950 #define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_B_BASE_IDX 3 6951 #define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_B 0x01b1 6952 #define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_B_BASE_IDX 3 6953 #define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_G 0x01b2 6954 #define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_G_BASE_IDX 3 6955 #define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_G 0x01b3 6956 #define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_G_BASE_IDX 3 6957 #define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_R 0x01b4 6958 #define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_R_BASE_IDX 3 6959 #define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_R 0x01b5 6960 #define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_R_BASE_IDX 3 6961 #define regMPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_B 0x01b6 6962 #define regMPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_B_BASE_IDX 3 6963 #define regMPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_G 0x01b7 6964 #define regMPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_G_BASE_IDX 3 6965 #define regMPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_R 0x01b8 6966 #define regMPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_R_BASE_IDX 3 6967 #define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_0_1 0x01b9 6968 #define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_0_1_BASE_IDX 3 6969 #define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_2_3 0x01ba 6970 #define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_2_3_BASE_IDX 3 6971 #define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_4_5 0x01bb 6972 #define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_4_5_BASE_IDX 3 6973 #define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_6_7 0x01bc 6974 #define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_6_7_BASE_IDX 3 6975 #define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_8_9 0x01bd 6976 #define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_8_9_BASE_IDX 3 6977 #define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_10_11 0x01be 6978 #define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_10_11_BASE_IDX 3 6979 #define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_12_13 0x01bf 6980 #define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_12_13_BASE_IDX 3 6981 #define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_14_15 0x01c0 6982 #define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_14_15_BASE_IDX 3 6983 #define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_16_17 0x01c1 6984 #define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_16_17_BASE_IDX 3 6985 #define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_18_19 0x01c2 6986 #define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_18_19_BASE_IDX 3 6987 #define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_20_21 0x01c3 6988 #define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_20_21_BASE_IDX 3 6989 #define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_22_23 0x01c4 6990 #define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_22_23_BASE_IDX 3 6991 #define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_24_25 0x01c5 6992 #define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_24_25_BASE_IDX 3 6993 #define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_26_27 0x01c6 6994 #define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_26_27_BASE_IDX 3 6995 #define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_28_29 0x01c7 6996 #define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_28_29_BASE_IDX 3 6997 #define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_30_31 0x01c8 6998 #define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_30_31_BASE_IDX 3 6999 #define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_32_33 0x01c9 7000 #define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_32_33_BASE_IDX 3 7001 #define regMPCC_OGAM1_MPCC_GAMUT_REMAP_COEF_FORMAT 0x01ca 7002 #define regMPCC_OGAM1_MPCC_GAMUT_REMAP_COEF_FORMAT_BASE_IDX 3 7003 #define regMPCC_OGAM1_MPCC_GAMUT_REMAP_MODE 0x01cb 7004 #define regMPCC_OGAM1_MPCC_GAMUT_REMAP_MODE_BASE_IDX 3 7005 #define regMPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_A 0x01cc 7006 #define regMPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_A_BASE_IDX 3 7007 #define regMPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_A 0x01cd 7008 #define regMPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_A_BASE_IDX 3 7009 #define regMPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_A 0x01ce 7010 #define regMPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_A_BASE_IDX 3 7011 #define regMPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_A 0x01cf 7012 #define regMPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_A_BASE_IDX 3 7013 #define regMPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_A 0x01d0 7014 #define regMPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_A_BASE_IDX 3 7015 #define regMPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_A 0x01d1 7016 #define regMPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_A_BASE_IDX 3 7017 #define regMPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_B 0x01d2 7018 #define regMPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_B_BASE_IDX 3 7019 #define regMPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_B 0x01d3 7020 #define regMPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_B_BASE_IDX 3 7021 #define regMPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_B 0x01d4 7022 #define regMPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_B_BASE_IDX 3 7023 #define regMPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_B 0x01d5 7024 #define regMPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_B_BASE_IDX 3 7025 #define regMPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_B 0x01d6 7026 #define regMPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_B_BASE_IDX 3 7027 #define regMPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_B 0x01d7 7028 #define regMPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_B_BASE_IDX 3 7029 7030 7031 // addressBlock: dce_dc_mpc_mpcc_ogam2_dispdec 7032 // base address: 0x400 7033 #define regMPCC_OGAM2_MPCC_OGAM_CONTROL 0x0200 7034 #define regMPCC_OGAM2_MPCC_OGAM_CONTROL_BASE_IDX 3 7035 #define regMPCC_OGAM2_MPCC_OGAM_LUT_INDEX 0x0201 7036 #define regMPCC_OGAM2_MPCC_OGAM_LUT_INDEX_BASE_IDX 3 7037 #define regMPCC_OGAM2_MPCC_OGAM_LUT_DATA 0x0202 7038 #define regMPCC_OGAM2_MPCC_OGAM_LUT_DATA_BASE_IDX 3 7039 #define regMPCC_OGAM2_MPCC_OGAM_LUT_CONTROL 0x0203 7040 #define regMPCC_OGAM2_MPCC_OGAM_LUT_CONTROL_BASE_IDX 3 7041 #define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_B 0x0204 7042 #define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_B_BASE_IDX 3 7043 #define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_G 0x0205 7044 #define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_G_BASE_IDX 3 7045 #define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_R 0x0206 7046 #define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_R_BASE_IDX 3 7047 #define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B 0x0207 7048 #define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B_BASE_IDX 3 7049 #define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G 0x0208 7050 #define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G_BASE_IDX 3 7051 #define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R 0x0209 7052 #define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R_BASE_IDX 3 7053 #define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_B 0x020a 7054 #define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_B_BASE_IDX 3 7055 #define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_G 0x020b 7056 #define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_G_BASE_IDX 3 7057 #define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_R 0x020c 7058 #define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_R_BASE_IDX 3 7059 #define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_B 0x020d 7060 #define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_B_BASE_IDX 3 7061 #define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_B 0x020e 7062 #define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_B_BASE_IDX 3 7063 #define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_G 0x020f 7064 #define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_G_BASE_IDX 3 7065 #define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_G 0x0210 7066 #define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_G_BASE_IDX 3 7067 #define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_R 0x0211 7068 #define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_R_BASE_IDX 3 7069 #define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_R 0x0212 7070 #define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_R_BASE_IDX 3 7071 #define regMPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_B 0x0213 7072 #define regMPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_B_BASE_IDX 3 7073 #define regMPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_G 0x0214 7074 #define regMPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_G_BASE_IDX 3 7075 #define regMPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_R 0x0215 7076 #define regMPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_R_BASE_IDX 3 7077 #define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_0_1 0x0216 7078 #define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_0_1_BASE_IDX 3 7079 #define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_2_3 0x0217 7080 #define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_2_3_BASE_IDX 3 7081 #define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_4_5 0x0218 7082 #define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_4_5_BASE_IDX 3 7083 #define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_6_7 0x0219 7084 #define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_6_7_BASE_IDX 3 7085 #define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_8_9 0x021a 7086 #define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_8_9_BASE_IDX 3 7087 #define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_10_11 0x021b 7088 #define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_10_11_BASE_IDX 3 7089 #define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_12_13 0x021c 7090 #define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_12_13_BASE_IDX 3 7091 #define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_14_15 0x021d 7092 #define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_14_15_BASE_IDX 3 7093 #define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_16_17 0x021e 7094 #define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_16_17_BASE_IDX 3 7095 #define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_18_19 0x021f 7096 #define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_18_19_BASE_IDX 3 7097 #define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_20_21 0x0220 7098 #define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_20_21_BASE_IDX 3 7099 #define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_22_23 0x0221 7100 #define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_22_23_BASE_IDX 3 7101 #define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_24_25 0x0222 7102 #define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_24_25_BASE_IDX 3 7103 #define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_26_27 0x0223 7104 #define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_26_27_BASE_IDX 3 7105 #define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_28_29 0x0224 7106 #define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_28_29_BASE_IDX 3 7107 #define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_30_31 0x0225 7108 #define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_30_31_BASE_IDX 3 7109 #define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_32_33 0x0226 7110 #define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_32_33_BASE_IDX 3 7111 #define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_B 0x0227 7112 #define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_B_BASE_IDX 3 7113 #define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_G 0x0228 7114 #define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_G_BASE_IDX 3 7115 #define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_R 0x0229 7116 #define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_R_BASE_IDX 3 7117 #define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B 0x022a 7118 #define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B_BASE_IDX 3 7119 #define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G 0x022b 7120 #define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G_BASE_IDX 3 7121 #define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R 0x022c 7122 #define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R_BASE_IDX 3 7123 #define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_B 0x022d 7124 #define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_B_BASE_IDX 3 7125 #define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_G 0x022e 7126 #define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_G_BASE_IDX 3 7127 #define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_R 0x022f 7128 #define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_R_BASE_IDX 3 7129 #define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_B 0x0230 7130 #define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_B_BASE_IDX 3 7131 #define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_B 0x0231 7132 #define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_B_BASE_IDX 3 7133 #define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_G 0x0232 7134 #define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_G_BASE_IDX 3 7135 #define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_G 0x0233 7136 #define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_G_BASE_IDX 3 7137 #define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_R 0x0234 7138 #define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_R_BASE_IDX 3 7139 #define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_R 0x0235 7140 #define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_R_BASE_IDX 3 7141 #define regMPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_B 0x0236 7142 #define regMPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_B_BASE_IDX 3 7143 #define regMPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_G 0x0237 7144 #define regMPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_G_BASE_IDX 3 7145 #define regMPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_R 0x0238 7146 #define regMPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_R_BASE_IDX 3 7147 #define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_0_1 0x0239 7148 #define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_0_1_BASE_IDX 3 7149 #define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_2_3 0x023a 7150 #define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_2_3_BASE_IDX 3 7151 #define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_4_5 0x023b 7152 #define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_4_5_BASE_IDX 3 7153 #define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_6_7 0x023c 7154 #define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_6_7_BASE_IDX 3 7155 #define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_8_9 0x023d 7156 #define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_8_9_BASE_IDX 3 7157 #define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_10_11 0x023e 7158 #define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_10_11_BASE_IDX 3 7159 #define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_12_13 0x023f 7160 #define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_12_13_BASE_IDX 3 7161 #define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_14_15 0x0240 7162 #define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_14_15_BASE_IDX 3 7163 #define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_16_17 0x0241 7164 #define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_16_17_BASE_IDX 3 7165 #define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_18_19 0x0242 7166 #define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_18_19_BASE_IDX 3 7167 #define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_20_21 0x0243 7168 #define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_20_21_BASE_IDX 3 7169 #define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_22_23 0x0244 7170 #define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_22_23_BASE_IDX 3 7171 #define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_24_25 0x0245 7172 #define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_24_25_BASE_IDX 3 7173 #define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_26_27 0x0246 7174 #define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_26_27_BASE_IDX 3 7175 #define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_28_29 0x0247 7176 #define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_28_29_BASE_IDX 3 7177 #define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_30_31 0x0248 7178 #define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_30_31_BASE_IDX 3 7179 #define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_32_33 0x0249 7180 #define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_32_33_BASE_IDX 3 7181 #define regMPCC_OGAM2_MPCC_GAMUT_REMAP_COEF_FORMAT 0x024a 7182 #define regMPCC_OGAM2_MPCC_GAMUT_REMAP_COEF_FORMAT_BASE_IDX 3 7183 #define regMPCC_OGAM2_MPCC_GAMUT_REMAP_MODE 0x024b 7184 #define regMPCC_OGAM2_MPCC_GAMUT_REMAP_MODE_BASE_IDX 3 7185 #define regMPCC_OGAM2_MPC_GAMUT_REMAP_C11_C12_A 0x024c 7186 #define regMPCC_OGAM2_MPC_GAMUT_REMAP_C11_C12_A_BASE_IDX 3 7187 #define regMPCC_OGAM2_MPC_GAMUT_REMAP_C13_C14_A 0x024d 7188 #define regMPCC_OGAM2_MPC_GAMUT_REMAP_C13_C14_A_BASE_IDX 3 7189 #define regMPCC_OGAM2_MPC_GAMUT_REMAP_C21_C22_A 0x024e 7190 #define regMPCC_OGAM2_MPC_GAMUT_REMAP_C21_C22_A_BASE_IDX 3 7191 #define regMPCC_OGAM2_MPC_GAMUT_REMAP_C23_C24_A 0x024f 7192 #define regMPCC_OGAM2_MPC_GAMUT_REMAP_C23_C24_A_BASE_IDX 3 7193 #define regMPCC_OGAM2_MPC_GAMUT_REMAP_C31_C32_A 0x0250 7194 #define regMPCC_OGAM2_MPC_GAMUT_REMAP_C31_C32_A_BASE_IDX 3 7195 #define regMPCC_OGAM2_MPC_GAMUT_REMAP_C33_C34_A 0x0251 7196 #define regMPCC_OGAM2_MPC_GAMUT_REMAP_C33_C34_A_BASE_IDX 3 7197 #define regMPCC_OGAM2_MPC_GAMUT_REMAP_C11_C12_B 0x0252 7198 #define regMPCC_OGAM2_MPC_GAMUT_REMAP_C11_C12_B_BASE_IDX 3 7199 #define regMPCC_OGAM2_MPC_GAMUT_REMAP_C13_C14_B 0x0253 7200 #define regMPCC_OGAM2_MPC_GAMUT_REMAP_C13_C14_B_BASE_IDX 3 7201 #define regMPCC_OGAM2_MPC_GAMUT_REMAP_C21_C22_B 0x0254 7202 #define regMPCC_OGAM2_MPC_GAMUT_REMAP_C21_C22_B_BASE_IDX 3 7203 #define regMPCC_OGAM2_MPC_GAMUT_REMAP_C23_C24_B 0x0255 7204 #define regMPCC_OGAM2_MPC_GAMUT_REMAP_C23_C24_B_BASE_IDX 3 7205 #define regMPCC_OGAM2_MPC_GAMUT_REMAP_C31_C32_B 0x0256 7206 #define regMPCC_OGAM2_MPC_GAMUT_REMAP_C31_C32_B_BASE_IDX 3 7207 #define regMPCC_OGAM2_MPC_GAMUT_REMAP_C33_C34_B 0x0257 7208 #define regMPCC_OGAM2_MPC_GAMUT_REMAP_C33_C34_B_BASE_IDX 3 7209 7210 7211 // addressBlock: dce_dc_mpc_mpcc_ogam3_dispdec 7212 // base address: 0x600 7213 #define regMPCC_OGAM3_MPCC_OGAM_CONTROL 0x0280 7214 #define regMPCC_OGAM3_MPCC_OGAM_CONTROL_BASE_IDX 3 7215 #define regMPCC_OGAM3_MPCC_OGAM_LUT_INDEX 0x0281 7216 #define regMPCC_OGAM3_MPCC_OGAM_LUT_INDEX_BASE_IDX 3 7217 #define regMPCC_OGAM3_MPCC_OGAM_LUT_DATA 0x0282 7218 #define regMPCC_OGAM3_MPCC_OGAM_LUT_DATA_BASE_IDX 3 7219 #define regMPCC_OGAM3_MPCC_OGAM_LUT_CONTROL 0x0283 7220 #define regMPCC_OGAM3_MPCC_OGAM_LUT_CONTROL_BASE_IDX 3 7221 #define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_B 0x0284 7222 #define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_B_BASE_IDX 3 7223 #define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_G 0x0285 7224 #define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_G_BASE_IDX 3 7225 #define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_R 0x0286 7226 #define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_R_BASE_IDX 3 7227 #define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B 0x0287 7228 #define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B_BASE_IDX 3 7229 #define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G 0x0288 7230 #define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G_BASE_IDX 3 7231 #define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R 0x0289 7232 #define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R_BASE_IDX 3 7233 #define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_B 0x028a 7234 #define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_B_BASE_IDX 3 7235 #define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_G 0x028b 7236 #define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_G_BASE_IDX 3 7237 #define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_R 0x028c 7238 #define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_R_BASE_IDX 3 7239 #define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_B 0x028d 7240 #define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_B_BASE_IDX 3 7241 #define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_B 0x028e 7242 #define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_B_BASE_IDX 3 7243 #define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_G 0x028f 7244 #define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_G_BASE_IDX 3 7245 #define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_G 0x0290 7246 #define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_G_BASE_IDX 3 7247 #define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_R 0x0291 7248 #define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_R_BASE_IDX 3 7249 #define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_R 0x0292 7250 #define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_R_BASE_IDX 3 7251 #define regMPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_B 0x0293 7252 #define regMPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_B_BASE_IDX 3 7253 #define regMPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_G 0x0294 7254 #define regMPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_G_BASE_IDX 3 7255 #define regMPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_R 0x0295 7256 #define regMPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_R_BASE_IDX 3 7257 #define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_0_1 0x0296 7258 #define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_0_1_BASE_IDX 3 7259 #define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_2_3 0x0297 7260 #define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_2_3_BASE_IDX 3 7261 #define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_4_5 0x0298 7262 #define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_4_5_BASE_IDX 3 7263 #define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_6_7 0x0299 7264 #define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_6_7_BASE_IDX 3 7265 #define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_8_9 0x029a 7266 #define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_8_9_BASE_IDX 3 7267 #define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_10_11 0x029b 7268 #define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_10_11_BASE_IDX 3 7269 #define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_12_13 0x029c 7270 #define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_12_13_BASE_IDX 3 7271 #define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_14_15 0x029d 7272 #define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_14_15_BASE_IDX 3 7273 #define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_16_17 0x029e 7274 #define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_16_17_BASE_IDX 3 7275 #define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_18_19 0x029f 7276 #define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_18_19_BASE_IDX 3 7277 #define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_20_21 0x02a0 7278 #define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_20_21_BASE_IDX 3 7279 #define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_22_23 0x02a1 7280 #define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_22_23_BASE_IDX 3 7281 #define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_24_25 0x02a2 7282 #define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_24_25_BASE_IDX 3 7283 #define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_26_27 0x02a3 7284 #define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_26_27_BASE_IDX 3 7285 #define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_28_29 0x02a4 7286 #define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_28_29_BASE_IDX 3 7287 #define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_30_31 0x02a5 7288 #define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_30_31_BASE_IDX 3 7289 #define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_32_33 0x02a6 7290 #define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_32_33_BASE_IDX 3 7291 #define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_B 0x02a7 7292 #define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_B_BASE_IDX 3 7293 #define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_G 0x02a8 7294 #define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_G_BASE_IDX 3 7295 #define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_R 0x02a9 7296 #define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_R_BASE_IDX 3 7297 #define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B 0x02aa 7298 #define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B_BASE_IDX 3 7299 #define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G 0x02ab 7300 #define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G_BASE_IDX 3 7301 #define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R 0x02ac 7302 #define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R_BASE_IDX 3 7303 #define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_B 0x02ad 7304 #define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_B_BASE_IDX 3 7305 #define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_G 0x02ae 7306 #define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_G_BASE_IDX 3 7307 #define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_R 0x02af 7308 #define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_R_BASE_IDX 3 7309 #define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_B 0x02b0 7310 #define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_B_BASE_IDX 3 7311 #define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_B 0x02b1 7312 #define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_B_BASE_IDX 3 7313 #define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_G 0x02b2 7314 #define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_G_BASE_IDX 3 7315 #define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_G 0x02b3 7316 #define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_G_BASE_IDX 3 7317 #define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_R 0x02b4 7318 #define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_R_BASE_IDX 3 7319 #define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_R 0x02b5 7320 #define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_R_BASE_IDX 3 7321 #define regMPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_B 0x02b6 7322 #define regMPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_B_BASE_IDX 3 7323 #define regMPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_G 0x02b7 7324 #define regMPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_G_BASE_IDX 3 7325 #define regMPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_R 0x02b8 7326 #define regMPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_R_BASE_IDX 3 7327 #define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_0_1 0x02b9 7328 #define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_0_1_BASE_IDX 3 7329 #define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_2_3 0x02ba 7330 #define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_2_3_BASE_IDX 3 7331 #define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_4_5 0x02bb 7332 #define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_4_5_BASE_IDX 3 7333 #define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_6_7 0x02bc 7334 #define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_6_7_BASE_IDX 3 7335 #define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_8_9 0x02bd 7336 #define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_8_9_BASE_IDX 3 7337 #define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_10_11 0x02be 7338 #define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_10_11_BASE_IDX 3 7339 #define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_12_13 0x02bf 7340 #define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_12_13_BASE_IDX 3 7341 #define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_14_15 0x02c0 7342 #define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_14_15_BASE_IDX 3 7343 #define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_16_17 0x02c1 7344 #define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_16_17_BASE_IDX 3 7345 #define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_18_19 0x02c2 7346 #define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_18_19_BASE_IDX 3 7347 #define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_20_21 0x02c3 7348 #define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_20_21_BASE_IDX 3 7349 #define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_22_23 0x02c4 7350 #define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_22_23_BASE_IDX 3 7351 #define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_24_25 0x02c5 7352 #define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_24_25_BASE_IDX 3 7353 #define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_26_27 0x02c6 7354 #define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_26_27_BASE_IDX 3 7355 #define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_28_29 0x02c7 7356 #define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_28_29_BASE_IDX 3 7357 #define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_30_31 0x02c8 7358 #define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_30_31_BASE_IDX 3 7359 #define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_32_33 0x02c9 7360 #define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_32_33_BASE_IDX 3 7361 #define regMPCC_OGAM3_MPCC_GAMUT_REMAP_COEF_FORMAT 0x02ca 7362 #define regMPCC_OGAM3_MPCC_GAMUT_REMAP_COEF_FORMAT_BASE_IDX 3 7363 #define regMPCC_OGAM3_MPCC_GAMUT_REMAP_MODE 0x02cb 7364 #define regMPCC_OGAM3_MPCC_GAMUT_REMAP_MODE_BASE_IDX 3 7365 #define regMPCC_OGAM3_MPC_GAMUT_REMAP_C11_C12_A 0x02cc 7366 #define regMPCC_OGAM3_MPC_GAMUT_REMAP_C11_C12_A_BASE_IDX 3 7367 #define regMPCC_OGAM3_MPC_GAMUT_REMAP_C13_C14_A 0x02cd 7368 #define regMPCC_OGAM3_MPC_GAMUT_REMAP_C13_C14_A_BASE_IDX 3 7369 #define regMPCC_OGAM3_MPC_GAMUT_REMAP_C21_C22_A 0x02ce 7370 #define regMPCC_OGAM3_MPC_GAMUT_REMAP_C21_C22_A_BASE_IDX 3 7371 #define regMPCC_OGAM3_MPC_GAMUT_REMAP_C23_C24_A 0x02cf 7372 #define regMPCC_OGAM3_MPC_GAMUT_REMAP_C23_C24_A_BASE_IDX 3 7373 #define regMPCC_OGAM3_MPC_GAMUT_REMAP_C31_C32_A 0x02d0 7374 #define regMPCC_OGAM3_MPC_GAMUT_REMAP_C31_C32_A_BASE_IDX 3 7375 #define regMPCC_OGAM3_MPC_GAMUT_REMAP_C33_C34_A 0x02d1 7376 #define regMPCC_OGAM3_MPC_GAMUT_REMAP_C33_C34_A_BASE_IDX 3 7377 #define regMPCC_OGAM3_MPC_GAMUT_REMAP_C11_C12_B 0x02d2 7378 #define regMPCC_OGAM3_MPC_GAMUT_REMAP_C11_C12_B_BASE_IDX 3 7379 #define regMPCC_OGAM3_MPC_GAMUT_REMAP_C13_C14_B 0x02d3 7380 #define regMPCC_OGAM3_MPC_GAMUT_REMAP_C13_C14_B_BASE_IDX 3 7381 #define regMPCC_OGAM3_MPC_GAMUT_REMAP_C21_C22_B 0x02d4 7382 #define regMPCC_OGAM3_MPC_GAMUT_REMAP_C21_C22_B_BASE_IDX 3 7383 #define regMPCC_OGAM3_MPC_GAMUT_REMAP_C23_C24_B 0x02d5 7384 #define regMPCC_OGAM3_MPC_GAMUT_REMAP_C23_C24_B_BASE_IDX 3 7385 #define regMPCC_OGAM3_MPC_GAMUT_REMAP_C31_C32_B 0x02d6 7386 #define regMPCC_OGAM3_MPC_GAMUT_REMAP_C31_C32_B_BASE_IDX 3 7387 #define regMPCC_OGAM3_MPC_GAMUT_REMAP_C33_C34_B 0x02d7 7388 #define regMPCC_OGAM3_MPC_GAMUT_REMAP_C33_C34_B_BASE_IDX 3 7389 7390 7391 // addressBlock: dce_dc_mpc_mpc_ocsc_dispdec 7392 // base address: 0x0 7393 #define regMPC_OUT0_MUX 0x0580 7394 #define regMPC_OUT0_MUX_BASE_IDX 3 7395 #define regMPC_OUT0_DENORM_CONTROL 0x0581 7396 #define regMPC_OUT0_DENORM_CONTROL_BASE_IDX 3 7397 #define regMPC_OUT0_DENORM_CLAMP_G_Y 0x0582 7398 #define regMPC_OUT0_DENORM_CLAMP_G_Y_BASE_IDX 3 7399 #define regMPC_OUT0_DENORM_CLAMP_B_CB 0x0583 7400 #define regMPC_OUT0_DENORM_CLAMP_B_CB_BASE_IDX 3 7401 #define regMPC_OUT1_MUX 0x0584 7402 #define regMPC_OUT1_MUX_BASE_IDX 3 7403 #define regMPC_OUT1_DENORM_CONTROL 0x0585 7404 #define regMPC_OUT1_DENORM_CONTROL_BASE_IDX 3 7405 #define regMPC_OUT1_DENORM_CLAMP_G_Y 0x0586 7406 #define regMPC_OUT1_DENORM_CLAMP_G_Y_BASE_IDX 3 7407 #define regMPC_OUT1_DENORM_CLAMP_B_CB 0x0587 7408 #define regMPC_OUT1_DENORM_CLAMP_B_CB_BASE_IDX 3 7409 #define regMPC_OUT2_MUX 0x0588 7410 #define regMPC_OUT2_MUX_BASE_IDX 3 7411 #define regMPC_OUT2_DENORM_CONTROL 0x0589 7412 #define regMPC_OUT2_DENORM_CONTROL_BASE_IDX 3 7413 #define regMPC_OUT2_DENORM_CLAMP_G_Y 0x058a 7414 #define regMPC_OUT2_DENORM_CLAMP_G_Y_BASE_IDX 3 7415 #define regMPC_OUT2_DENORM_CLAMP_B_CB 0x058b 7416 #define regMPC_OUT2_DENORM_CLAMP_B_CB_BASE_IDX 3 7417 #define regMPC_OUT3_MUX 0x058c 7418 #define regMPC_OUT3_MUX_BASE_IDX 3 7419 #define regMPC_OUT3_DENORM_CONTROL 0x058d 7420 #define regMPC_OUT3_DENORM_CONTROL_BASE_IDX 3 7421 #define regMPC_OUT3_DENORM_CLAMP_G_Y 0x058e 7422 #define regMPC_OUT3_DENORM_CLAMP_G_Y_BASE_IDX 3 7423 #define regMPC_OUT3_DENORM_CLAMP_B_CB 0x058f 7424 #define regMPC_OUT3_DENORM_CLAMP_B_CB_BASE_IDX 3 7425 #define regMPC_OUT_CSC_COEF_FORMAT 0x05a0 7426 #define regMPC_OUT_CSC_COEF_FORMAT_BASE_IDX 3 7427 #define regMPC_OUT0_CSC_MODE 0x05a1 7428 #define regMPC_OUT0_CSC_MODE_BASE_IDX 3 7429 #define regMPC_OUT0_CSC_C11_C12_A 0x05a2 7430 #define regMPC_OUT0_CSC_C11_C12_A_BASE_IDX 3 7431 #define regMPC_OUT0_CSC_C13_C14_A 0x05a3 7432 #define regMPC_OUT0_CSC_C13_C14_A_BASE_IDX 3 7433 #define regMPC_OUT0_CSC_C21_C22_A 0x05a4 7434 #define regMPC_OUT0_CSC_C21_C22_A_BASE_IDX 3 7435 #define regMPC_OUT0_CSC_C23_C24_A 0x05a5 7436 #define regMPC_OUT0_CSC_C23_C24_A_BASE_IDX 3 7437 #define regMPC_OUT0_CSC_C31_C32_A 0x05a6 7438 #define regMPC_OUT0_CSC_C31_C32_A_BASE_IDX 3 7439 #define regMPC_OUT0_CSC_C33_C34_A 0x05a7 7440 #define regMPC_OUT0_CSC_C33_C34_A_BASE_IDX 3 7441 #define regMPC_OUT0_CSC_C11_C12_B 0x05a8 7442 #define regMPC_OUT0_CSC_C11_C12_B_BASE_IDX 3 7443 #define regMPC_OUT0_CSC_C13_C14_B 0x05a9 7444 #define regMPC_OUT0_CSC_C13_C14_B_BASE_IDX 3 7445 #define regMPC_OUT0_CSC_C21_C22_B 0x05aa 7446 #define regMPC_OUT0_CSC_C21_C22_B_BASE_IDX 3 7447 #define regMPC_OUT0_CSC_C23_C24_B 0x05ab 7448 #define regMPC_OUT0_CSC_C23_C24_B_BASE_IDX 3 7449 #define regMPC_OUT0_CSC_C31_C32_B 0x05ac 7450 #define regMPC_OUT0_CSC_C31_C32_B_BASE_IDX 3 7451 #define regMPC_OUT0_CSC_C33_C34_B 0x05ad 7452 #define regMPC_OUT0_CSC_C33_C34_B_BASE_IDX 3 7453 #define regMPC_OUT1_CSC_MODE 0x05ae 7454 #define regMPC_OUT1_CSC_MODE_BASE_IDX 3 7455 #define regMPC_OUT1_CSC_C11_C12_A 0x05af 7456 #define regMPC_OUT1_CSC_C11_C12_A_BASE_IDX 3 7457 #define regMPC_OUT1_CSC_C13_C14_A 0x05b0 7458 #define regMPC_OUT1_CSC_C13_C14_A_BASE_IDX 3 7459 #define regMPC_OUT1_CSC_C21_C22_A 0x05b1 7460 #define regMPC_OUT1_CSC_C21_C22_A_BASE_IDX 3 7461 #define regMPC_OUT1_CSC_C23_C24_A 0x05b2 7462 #define regMPC_OUT1_CSC_C23_C24_A_BASE_IDX 3 7463 #define regMPC_OUT1_CSC_C31_C32_A 0x05b3 7464 #define regMPC_OUT1_CSC_C31_C32_A_BASE_IDX 3 7465 #define regMPC_OUT1_CSC_C33_C34_A 0x05b4 7466 #define regMPC_OUT1_CSC_C33_C34_A_BASE_IDX 3 7467 #define regMPC_OUT1_CSC_C11_C12_B 0x05b5 7468 #define regMPC_OUT1_CSC_C11_C12_B_BASE_IDX 3 7469 #define regMPC_OUT1_CSC_C13_C14_B 0x05b6 7470 #define regMPC_OUT1_CSC_C13_C14_B_BASE_IDX 3 7471 #define regMPC_OUT1_CSC_C21_C22_B 0x05b7 7472 #define regMPC_OUT1_CSC_C21_C22_B_BASE_IDX 3 7473 #define regMPC_OUT1_CSC_C23_C24_B 0x05b8 7474 #define regMPC_OUT1_CSC_C23_C24_B_BASE_IDX 3 7475 #define regMPC_OUT1_CSC_C31_C32_B 0x05b9 7476 #define regMPC_OUT1_CSC_C31_C32_B_BASE_IDX 3 7477 #define regMPC_OUT1_CSC_C33_C34_B 0x05ba 7478 #define regMPC_OUT1_CSC_C33_C34_B_BASE_IDX 3 7479 #define regMPC_OUT2_CSC_MODE 0x05bb 7480 #define regMPC_OUT2_CSC_MODE_BASE_IDX 3 7481 #define regMPC_OUT2_CSC_C11_C12_A 0x05bc 7482 #define regMPC_OUT2_CSC_C11_C12_A_BASE_IDX 3 7483 #define regMPC_OUT2_CSC_C13_C14_A 0x05bd 7484 #define regMPC_OUT2_CSC_C13_C14_A_BASE_IDX 3 7485 #define regMPC_OUT2_CSC_C21_C22_A 0x05be 7486 #define regMPC_OUT2_CSC_C21_C22_A_BASE_IDX 3 7487 #define regMPC_OUT2_CSC_C23_C24_A 0x05bf 7488 #define regMPC_OUT2_CSC_C23_C24_A_BASE_IDX 3 7489 #define regMPC_OUT2_CSC_C31_C32_A 0x05c0 7490 #define regMPC_OUT2_CSC_C31_C32_A_BASE_IDX 3 7491 #define regMPC_OUT2_CSC_C33_C34_A 0x05c1 7492 #define regMPC_OUT2_CSC_C33_C34_A_BASE_IDX 3 7493 #define regMPC_OUT2_CSC_C11_C12_B 0x05c2 7494 #define regMPC_OUT2_CSC_C11_C12_B_BASE_IDX 3 7495 #define regMPC_OUT2_CSC_C13_C14_B 0x05c3 7496 #define regMPC_OUT2_CSC_C13_C14_B_BASE_IDX 3 7497 #define regMPC_OUT2_CSC_C21_C22_B 0x05c4 7498 #define regMPC_OUT2_CSC_C21_C22_B_BASE_IDX 3 7499 #define regMPC_OUT2_CSC_C23_C24_B 0x05c5 7500 #define regMPC_OUT2_CSC_C23_C24_B_BASE_IDX 3 7501 #define regMPC_OUT2_CSC_C31_C32_B 0x05c6 7502 #define regMPC_OUT2_CSC_C31_C32_B_BASE_IDX 3 7503 #define regMPC_OUT2_CSC_C33_C34_B 0x05c7 7504 #define regMPC_OUT2_CSC_C33_C34_B_BASE_IDX 3 7505 #define regMPC_OUT3_CSC_MODE 0x05c8 7506 #define regMPC_OUT3_CSC_MODE_BASE_IDX 3 7507 #define regMPC_OUT3_CSC_C11_C12_A 0x05c9 7508 #define regMPC_OUT3_CSC_C11_C12_A_BASE_IDX 3 7509 #define regMPC_OUT3_CSC_C13_C14_A 0x05ca 7510 #define regMPC_OUT3_CSC_C13_C14_A_BASE_IDX 3 7511 #define regMPC_OUT3_CSC_C21_C22_A 0x05cb 7512 #define regMPC_OUT3_CSC_C21_C22_A_BASE_IDX 3 7513 #define regMPC_OUT3_CSC_C23_C24_A 0x05cc 7514 #define regMPC_OUT3_CSC_C23_C24_A_BASE_IDX 3 7515 #define regMPC_OUT3_CSC_C31_C32_A 0x05cd 7516 #define regMPC_OUT3_CSC_C31_C32_A_BASE_IDX 3 7517 #define regMPC_OUT3_CSC_C33_C34_A 0x05ce 7518 #define regMPC_OUT3_CSC_C33_C34_A_BASE_IDX 3 7519 #define regMPC_OUT3_CSC_C11_C12_B 0x05cf 7520 #define regMPC_OUT3_CSC_C11_C12_B_BASE_IDX 3 7521 #define regMPC_OUT3_CSC_C13_C14_B 0x05d0 7522 #define regMPC_OUT3_CSC_C13_C14_B_BASE_IDX 3 7523 #define regMPC_OUT3_CSC_C21_C22_B 0x05d1 7524 #define regMPC_OUT3_CSC_C21_C22_B_BASE_IDX 3 7525 #define regMPC_OUT3_CSC_C23_C24_B 0x05d2 7526 #define regMPC_OUT3_CSC_C23_C24_B_BASE_IDX 3 7527 #define regMPC_OUT3_CSC_C31_C32_B 0x05d3 7528 #define regMPC_OUT3_CSC_C31_C32_B_BASE_IDX 3 7529 #define regMPC_OUT3_CSC_C33_C34_B 0x05d4 7530 #define regMPC_OUT3_CSC_C33_C34_B_BASE_IDX 3 7531 7532 7533 // addressBlock: dce_dc_mpc_mpc_rmu_dispdec 7534 // base address: 0x0 7535 #define regMPC_RMU_CONTROL 0x0680 7536 #define regMPC_RMU_CONTROL_BASE_IDX 3 7537 #define regMPC_RMU_MEM_PWR_CTRL 0x0681 7538 #define regMPC_RMU_MEM_PWR_CTRL_BASE_IDX 3 7539 #define regMPC_RMU0_SHAPER_CONTROL 0x0682 7540 #define regMPC_RMU0_SHAPER_CONTROL_BASE_IDX 3 7541 #define regMPC_RMU0_SHAPER_OFFSET_R 0x0683 7542 #define regMPC_RMU0_SHAPER_OFFSET_R_BASE_IDX 3 7543 #define regMPC_RMU0_SHAPER_OFFSET_G 0x0684 7544 #define regMPC_RMU0_SHAPER_OFFSET_G_BASE_IDX 3 7545 #define regMPC_RMU0_SHAPER_OFFSET_B 0x0685 7546 #define regMPC_RMU0_SHAPER_OFFSET_B_BASE_IDX 3 7547 #define regMPC_RMU0_SHAPER_SCALE_R 0x0686 7548 #define regMPC_RMU0_SHAPER_SCALE_R_BASE_IDX 3 7549 #define regMPC_RMU0_SHAPER_SCALE_G_B 0x0687 7550 #define regMPC_RMU0_SHAPER_SCALE_G_B_BASE_IDX 3 7551 #define regMPC_RMU0_SHAPER_LUT_INDEX 0x0688 7552 #define regMPC_RMU0_SHAPER_LUT_INDEX_BASE_IDX 3 7553 #define regMPC_RMU0_SHAPER_LUT_DATA 0x0689 7554 #define regMPC_RMU0_SHAPER_LUT_DATA_BASE_IDX 3 7555 #define regMPC_RMU0_SHAPER_LUT_WRITE_EN_MASK 0x068a 7556 #define regMPC_RMU0_SHAPER_LUT_WRITE_EN_MASK_BASE_IDX 3 7557 #define regMPC_RMU0_SHAPER_RAMA_START_CNTL_B 0x068b 7558 #define regMPC_RMU0_SHAPER_RAMA_START_CNTL_B_BASE_IDX 3 7559 #define regMPC_RMU0_SHAPER_RAMA_START_CNTL_G 0x068c 7560 #define regMPC_RMU0_SHAPER_RAMA_START_CNTL_G_BASE_IDX 3 7561 #define regMPC_RMU0_SHAPER_RAMA_START_CNTL_R 0x068d 7562 #define regMPC_RMU0_SHAPER_RAMA_START_CNTL_R_BASE_IDX 3 7563 #define regMPC_RMU0_SHAPER_RAMA_END_CNTL_B 0x068e 7564 #define regMPC_RMU0_SHAPER_RAMA_END_CNTL_B_BASE_IDX 3 7565 #define regMPC_RMU0_SHAPER_RAMA_END_CNTL_G 0x068f 7566 #define regMPC_RMU0_SHAPER_RAMA_END_CNTL_G_BASE_IDX 3 7567 #define regMPC_RMU0_SHAPER_RAMA_END_CNTL_R 0x0690 7568 #define regMPC_RMU0_SHAPER_RAMA_END_CNTL_R_BASE_IDX 3 7569 #define regMPC_RMU0_SHAPER_RAMA_REGION_0_1 0x0691 7570 #define regMPC_RMU0_SHAPER_RAMA_REGION_0_1_BASE_IDX 3 7571 #define regMPC_RMU0_SHAPER_RAMA_REGION_2_3 0x0692 7572 #define regMPC_RMU0_SHAPER_RAMA_REGION_2_3_BASE_IDX 3 7573 #define regMPC_RMU0_SHAPER_RAMA_REGION_4_5 0x0693 7574 #define regMPC_RMU0_SHAPER_RAMA_REGION_4_5_BASE_IDX 3 7575 #define regMPC_RMU0_SHAPER_RAMA_REGION_6_7 0x0694 7576 #define regMPC_RMU0_SHAPER_RAMA_REGION_6_7_BASE_IDX 3 7577 #define regMPC_RMU0_SHAPER_RAMA_REGION_8_9 0x0695 7578 #define regMPC_RMU0_SHAPER_RAMA_REGION_8_9_BASE_IDX 3 7579 #define regMPC_RMU0_SHAPER_RAMA_REGION_10_11 0x0696 7580 #define regMPC_RMU0_SHAPER_RAMA_REGION_10_11_BASE_IDX 3 7581 #define regMPC_RMU0_SHAPER_RAMA_REGION_12_13 0x0697 7582 #define regMPC_RMU0_SHAPER_RAMA_REGION_12_13_BASE_IDX 3 7583 #define regMPC_RMU0_SHAPER_RAMA_REGION_14_15 0x0698 7584 #define regMPC_RMU0_SHAPER_RAMA_REGION_14_15_BASE_IDX 3 7585 #define regMPC_RMU0_SHAPER_RAMA_REGION_16_17 0x0699 7586 #define regMPC_RMU0_SHAPER_RAMA_REGION_16_17_BASE_IDX 3 7587 #define regMPC_RMU0_SHAPER_RAMA_REGION_18_19 0x069a 7588 #define regMPC_RMU0_SHAPER_RAMA_REGION_18_19_BASE_IDX 3 7589 #define regMPC_RMU0_SHAPER_RAMA_REGION_20_21 0x069b 7590 #define regMPC_RMU0_SHAPER_RAMA_REGION_20_21_BASE_IDX 3 7591 #define regMPC_RMU0_SHAPER_RAMA_REGION_22_23 0x069c 7592 #define regMPC_RMU0_SHAPER_RAMA_REGION_22_23_BASE_IDX 3 7593 #define regMPC_RMU0_SHAPER_RAMA_REGION_24_25 0x069d 7594 #define regMPC_RMU0_SHAPER_RAMA_REGION_24_25_BASE_IDX 3 7595 #define regMPC_RMU0_SHAPER_RAMA_REGION_26_27 0x069e 7596 #define regMPC_RMU0_SHAPER_RAMA_REGION_26_27_BASE_IDX 3 7597 #define regMPC_RMU0_SHAPER_RAMA_REGION_28_29 0x069f 7598 #define regMPC_RMU0_SHAPER_RAMA_REGION_28_29_BASE_IDX 3 7599 #define regMPC_RMU0_SHAPER_RAMA_REGION_30_31 0x06a0 7600 #define regMPC_RMU0_SHAPER_RAMA_REGION_30_31_BASE_IDX 3 7601 #define regMPC_RMU0_SHAPER_RAMA_REGION_32_33 0x06a1 7602 #define regMPC_RMU0_SHAPER_RAMA_REGION_32_33_BASE_IDX 3 7603 #define regMPC_RMU0_SHAPER_RAMB_START_CNTL_B 0x06a2 7604 #define regMPC_RMU0_SHAPER_RAMB_START_CNTL_B_BASE_IDX 3 7605 #define regMPC_RMU0_SHAPER_RAMB_START_CNTL_G 0x06a3 7606 #define regMPC_RMU0_SHAPER_RAMB_START_CNTL_G_BASE_IDX 3 7607 #define regMPC_RMU0_SHAPER_RAMB_START_CNTL_R 0x06a4 7608 #define regMPC_RMU0_SHAPER_RAMB_START_CNTL_R_BASE_IDX 3 7609 #define regMPC_RMU0_SHAPER_RAMB_END_CNTL_B 0x06a5 7610 #define regMPC_RMU0_SHAPER_RAMB_END_CNTL_B_BASE_IDX 3 7611 #define regMPC_RMU0_SHAPER_RAMB_END_CNTL_G 0x06a6 7612 #define regMPC_RMU0_SHAPER_RAMB_END_CNTL_G_BASE_IDX 3 7613 #define regMPC_RMU0_SHAPER_RAMB_END_CNTL_R 0x06a7 7614 #define regMPC_RMU0_SHAPER_RAMB_END_CNTL_R_BASE_IDX 3 7615 #define regMPC_RMU0_SHAPER_RAMB_REGION_0_1 0x06a8 7616 #define regMPC_RMU0_SHAPER_RAMB_REGION_0_1_BASE_IDX 3 7617 #define regMPC_RMU0_SHAPER_RAMB_REGION_2_3 0x06a9 7618 #define regMPC_RMU0_SHAPER_RAMB_REGION_2_3_BASE_IDX 3 7619 #define regMPC_RMU0_SHAPER_RAMB_REGION_4_5 0x06aa 7620 #define regMPC_RMU0_SHAPER_RAMB_REGION_4_5_BASE_IDX 3 7621 #define regMPC_RMU0_SHAPER_RAMB_REGION_6_7 0x06ab 7622 #define regMPC_RMU0_SHAPER_RAMB_REGION_6_7_BASE_IDX 3 7623 #define regMPC_RMU0_SHAPER_RAMB_REGION_8_9 0x06ac 7624 #define regMPC_RMU0_SHAPER_RAMB_REGION_8_9_BASE_IDX 3 7625 #define regMPC_RMU0_SHAPER_RAMB_REGION_10_11 0x06ad 7626 #define regMPC_RMU0_SHAPER_RAMB_REGION_10_11_BASE_IDX 3 7627 #define regMPC_RMU0_SHAPER_RAMB_REGION_12_13 0x06ae 7628 #define regMPC_RMU0_SHAPER_RAMB_REGION_12_13_BASE_IDX 3 7629 #define regMPC_RMU0_SHAPER_RAMB_REGION_14_15 0x06af 7630 #define regMPC_RMU0_SHAPER_RAMB_REGION_14_15_BASE_IDX 3 7631 #define regMPC_RMU0_SHAPER_RAMB_REGION_16_17 0x06b0 7632 #define regMPC_RMU0_SHAPER_RAMB_REGION_16_17_BASE_IDX 3 7633 #define regMPC_RMU0_SHAPER_RAMB_REGION_18_19 0x06b1 7634 #define regMPC_RMU0_SHAPER_RAMB_REGION_18_19_BASE_IDX 3 7635 #define regMPC_RMU0_SHAPER_RAMB_REGION_20_21 0x06b2 7636 #define regMPC_RMU0_SHAPER_RAMB_REGION_20_21_BASE_IDX 3 7637 #define regMPC_RMU0_SHAPER_RAMB_REGION_22_23 0x06b3 7638 #define regMPC_RMU0_SHAPER_RAMB_REGION_22_23_BASE_IDX 3 7639 #define regMPC_RMU0_SHAPER_RAMB_REGION_24_25 0x06b4 7640 #define regMPC_RMU0_SHAPER_RAMB_REGION_24_25_BASE_IDX 3 7641 #define regMPC_RMU0_SHAPER_RAMB_REGION_26_27 0x06b5 7642 #define regMPC_RMU0_SHAPER_RAMB_REGION_26_27_BASE_IDX 3 7643 #define regMPC_RMU0_SHAPER_RAMB_REGION_28_29 0x06b6 7644 #define regMPC_RMU0_SHAPER_RAMB_REGION_28_29_BASE_IDX 3 7645 #define regMPC_RMU0_SHAPER_RAMB_REGION_30_31 0x06b7 7646 #define regMPC_RMU0_SHAPER_RAMB_REGION_30_31_BASE_IDX 3 7647 #define regMPC_RMU0_SHAPER_RAMB_REGION_32_33 0x06b8 7648 #define regMPC_RMU0_SHAPER_RAMB_REGION_32_33_BASE_IDX 3 7649 #define regMPC_RMU0_3DLUT_MODE 0x06b9 7650 #define regMPC_RMU0_3DLUT_MODE_BASE_IDX 3 7651 #define regMPC_RMU0_3DLUT_INDEX 0x06ba 7652 #define regMPC_RMU0_3DLUT_INDEX_BASE_IDX 3 7653 #define regMPC_RMU0_3DLUT_DATA 0x06bb 7654 #define regMPC_RMU0_3DLUT_DATA_BASE_IDX 3 7655 #define regMPC_RMU0_3DLUT_DATA_30BIT 0x06bc 7656 #define regMPC_RMU0_3DLUT_DATA_30BIT_BASE_IDX 3 7657 #define regMPC_RMU0_3DLUT_READ_WRITE_CONTROL 0x06bd 7658 #define regMPC_RMU0_3DLUT_READ_WRITE_CONTROL_BASE_IDX 3 7659 #define regMPC_RMU0_3DLUT_OUT_NORM_FACTOR 0x06be 7660 #define regMPC_RMU0_3DLUT_OUT_NORM_FACTOR_BASE_IDX 3 7661 #define regMPC_RMU0_3DLUT_OUT_OFFSET_R 0x06bf 7662 #define regMPC_RMU0_3DLUT_OUT_OFFSET_R_BASE_IDX 3 7663 #define regMPC_RMU0_3DLUT_OUT_OFFSET_G 0x06c0 7664 #define regMPC_RMU0_3DLUT_OUT_OFFSET_G_BASE_IDX 3 7665 #define regMPC_RMU0_3DLUT_OUT_OFFSET_B 0x06c1 7666 #define regMPC_RMU0_3DLUT_OUT_OFFSET_B_BASE_IDX 3 7667 #define regMPC_RMU1_SHAPER_CONTROL 0x06c2 7668 #define regMPC_RMU1_SHAPER_CONTROL_BASE_IDX 3 7669 #define regMPC_RMU1_SHAPER_OFFSET_R 0x06c3 7670 #define regMPC_RMU1_SHAPER_OFFSET_R_BASE_IDX 3 7671 #define regMPC_RMU1_SHAPER_OFFSET_G 0x06c4 7672 #define regMPC_RMU1_SHAPER_OFFSET_G_BASE_IDX 3 7673 #define regMPC_RMU1_SHAPER_OFFSET_B 0x06c5 7674 #define regMPC_RMU1_SHAPER_OFFSET_B_BASE_IDX 3 7675 #define regMPC_RMU1_SHAPER_SCALE_R 0x06c6 7676 #define regMPC_RMU1_SHAPER_SCALE_R_BASE_IDX 3 7677 #define regMPC_RMU1_SHAPER_SCALE_G_B 0x06c7 7678 #define regMPC_RMU1_SHAPER_SCALE_G_B_BASE_IDX 3 7679 #define regMPC_RMU1_SHAPER_LUT_INDEX 0x06c8 7680 #define regMPC_RMU1_SHAPER_LUT_INDEX_BASE_IDX 3 7681 #define regMPC_RMU1_SHAPER_LUT_DATA 0x06c9 7682 #define regMPC_RMU1_SHAPER_LUT_DATA_BASE_IDX 3 7683 #define regMPC_RMU1_SHAPER_LUT_WRITE_EN_MASK 0x06ca 7684 #define regMPC_RMU1_SHAPER_LUT_WRITE_EN_MASK_BASE_IDX 3 7685 #define regMPC_RMU1_SHAPER_RAMA_START_CNTL_B 0x06cb 7686 #define regMPC_RMU1_SHAPER_RAMA_START_CNTL_B_BASE_IDX 3 7687 #define regMPC_RMU1_SHAPER_RAMA_START_CNTL_G 0x06cc 7688 #define regMPC_RMU1_SHAPER_RAMA_START_CNTL_G_BASE_IDX 3 7689 #define regMPC_RMU1_SHAPER_RAMA_START_CNTL_R 0x06cd 7690 #define regMPC_RMU1_SHAPER_RAMA_START_CNTL_R_BASE_IDX 3 7691 #define regMPC_RMU1_SHAPER_RAMA_END_CNTL_B 0x06ce 7692 #define regMPC_RMU1_SHAPER_RAMA_END_CNTL_B_BASE_IDX 3 7693 #define regMPC_RMU1_SHAPER_RAMA_END_CNTL_G 0x06cf 7694 #define regMPC_RMU1_SHAPER_RAMA_END_CNTL_G_BASE_IDX 3 7695 #define regMPC_RMU1_SHAPER_RAMA_END_CNTL_R 0x06d0 7696 #define regMPC_RMU1_SHAPER_RAMA_END_CNTL_R_BASE_IDX 3 7697 #define regMPC_RMU1_SHAPER_RAMA_REGION_0_1 0x06d1 7698 #define regMPC_RMU1_SHAPER_RAMA_REGION_0_1_BASE_IDX 3 7699 #define regMPC_RMU1_SHAPER_RAMA_REGION_2_3 0x06d2 7700 #define regMPC_RMU1_SHAPER_RAMA_REGION_2_3_BASE_IDX 3 7701 #define regMPC_RMU1_SHAPER_RAMA_REGION_4_5 0x06d3 7702 #define regMPC_RMU1_SHAPER_RAMA_REGION_4_5_BASE_IDX 3 7703 #define regMPC_RMU1_SHAPER_RAMA_REGION_6_7 0x06d4 7704 #define regMPC_RMU1_SHAPER_RAMA_REGION_6_7_BASE_IDX 3 7705 #define regMPC_RMU1_SHAPER_RAMA_REGION_8_9 0x06d5 7706 #define regMPC_RMU1_SHAPER_RAMA_REGION_8_9_BASE_IDX 3 7707 #define regMPC_RMU1_SHAPER_RAMA_REGION_10_11 0x06d6 7708 #define regMPC_RMU1_SHAPER_RAMA_REGION_10_11_BASE_IDX 3 7709 #define regMPC_RMU1_SHAPER_RAMA_REGION_12_13 0x06d7 7710 #define regMPC_RMU1_SHAPER_RAMA_REGION_12_13_BASE_IDX 3 7711 #define regMPC_RMU1_SHAPER_RAMA_REGION_14_15 0x06d8 7712 #define regMPC_RMU1_SHAPER_RAMA_REGION_14_15_BASE_IDX 3 7713 #define regMPC_RMU1_SHAPER_RAMA_REGION_16_17 0x06d9 7714 #define regMPC_RMU1_SHAPER_RAMA_REGION_16_17_BASE_IDX 3 7715 #define regMPC_RMU1_SHAPER_RAMA_REGION_18_19 0x06da 7716 #define regMPC_RMU1_SHAPER_RAMA_REGION_18_19_BASE_IDX 3 7717 #define regMPC_RMU1_SHAPER_RAMA_REGION_20_21 0x06db 7718 #define regMPC_RMU1_SHAPER_RAMA_REGION_20_21_BASE_IDX 3 7719 #define regMPC_RMU1_SHAPER_RAMA_REGION_22_23 0x06dc 7720 #define regMPC_RMU1_SHAPER_RAMA_REGION_22_23_BASE_IDX 3 7721 #define regMPC_RMU1_SHAPER_RAMA_REGION_24_25 0x06dd 7722 #define regMPC_RMU1_SHAPER_RAMA_REGION_24_25_BASE_IDX 3 7723 #define regMPC_RMU1_SHAPER_RAMA_REGION_26_27 0x06de 7724 #define regMPC_RMU1_SHAPER_RAMA_REGION_26_27_BASE_IDX 3 7725 #define regMPC_RMU1_SHAPER_RAMA_REGION_28_29 0x06df 7726 #define regMPC_RMU1_SHAPER_RAMA_REGION_28_29_BASE_IDX 3 7727 #define regMPC_RMU1_SHAPER_RAMA_REGION_30_31 0x06e0 7728 #define regMPC_RMU1_SHAPER_RAMA_REGION_30_31_BASE_IDX 3 7729 #define regMPC_RMU1_SHAPER_RAMA_REGION_32_33 0x06e1 7730 #define regMPC_RMU1_SHAPER_RAMA_REGION_32_33_BASE_IDX 3 7731 #define regMPC_RMU1_SHAPER_RAMB_START_CNTL_B 0x06e2 7732 #define regMPC_RMU1_SHAPER_RAMB_START_CNTL_B_BASE_IDX 3 7733 #define regMPC_RMU1_SHAPER_RAMB_START_CNTL_G 0x06e3 7734 #define regMPC_RMU1_SHAPER_RAMB_START_CNTL_G_BASE_IDX 3 7735 #define regMPC_RMU1_SHAPER_RAMB_START_CNTL_R 0x06e4 7736 #define regMPC_RMU1_SHAPER_RAMB_START_CNTL_R_BASE_IDX 3 7737 #define regMPC_RMU1_SHAPER_RAMB_END_CNTL_B 0x06e5 7738 #define regMPC_RMU1_SHAPER_RAMB_END_CNTL_B_BASE_IDX 3 7739 #define regMPC_RMU1_SHAPER_RAMB_END_CNTL_G 0x06e6 7740 #define regMPC_RMU1_SHAPER_RAMB_END_CNTL_G_BASE_IDX 3 7741 #define regMPC_RMU1_SHAPER_RAMB_END_CNTL_R 0x06e7 7742 #define regMPC_RMU1_SHAPER_RAMB_END_CNTL_R_BASE_IDX 3 7743 #define regMPC_RMU1_SHAPER_RAMB_REGION_0_1 0x06e8 7744 #define regMPC_RMU1_SHAPER_RAMB_REGION_0_1_BASE_IDX 3 7745 #define regMPC_RMU1_SHAPER_RAMB_REGION_2_3 0x06e9 7746 #define regMPC_RMU1_SHAPER_RAMB_REGION_2_3_BASE_IDX 3 7747 #define regMPC_RMU1_SHAPER_RAMB_REGION_4_5 0x06ea 7748 #define regMPC_RMU1_SHAPER_RAMB_REGION_4_5_BASE_IDX 3 7749 #define regMPC_RMU1_SHAPER_RAMB_REGION_6_7 0x06eb 7750 #define regMPC_RMU1_SHAPER_RAMB_REGION_6_7_BASE_IDX 3 7751 #define regMPC_RMU1_SHAPER_RAMB_REGION_8_9 0x06ec 7752 #define regMPC_RMU1_SHAPER_RAMB_REGION_8_9_BASE_IDX 3 7753 #define regMPC_RMU1_SHAPER_RAMB_REGION_10_11 0x06ed 7754 #define regMPC_RMU1_SHAPER_RAMB_REGION_10_11_BASE_IDX 3 7755 #define regMPC_RMU1_SHAPER_RAMB_REGION_12_13 0x06ee 7756 #define regMPC_RMU1_SHAPER_RAMB_REGION_12_13_BASE_IDX 3 7757 #define regMPC_RMU1_SHAPER_RAMB_REGION_14_15 0x06ef 7758 #define regMPC_RMU1_SHAPER_RAMB_REGION_14_15_BASE_IDX 3 7759 #define regMPC_RMU1_SHAPER_RAMB_REGION_16_17 0x06f0 7760 #define regMPC_RMU1_SHAPER_RAMB_REGION_16_17_BASE_IDX 3 7761 #define regMPC_RMU1_SHAPER_RAMB_REGION_18_19 0x06f1 7762 #define regMPC_RMU1_SHAPER_RAMB_REGION_18_19_BASE_IDX 3 7763 #define regMPC_RMU1_SHAPER_RAMB_REGION_20_21 0x06f2 7764 #define regMPC_RMU1_SHAPER_RAMB_REGION_20_21_BASE_IDX 3 7765 #define regMPC_RMU1_SHAPER_RAMB_REGION_22_23 0x06f3 7766 #define regMPC_RMU1_SHAPER_RAMB_REGION_22_23_BASE_IDX 3 7767 #define regMPC_RMU1_SHAPER_RAMB_REGION_24_25 0x06f4 7768 #define regMPC_RMU1_SHAPER_RAMB_REGION_24_25_BASE_IDX 3 7769 #define regMPC_RMU1_SHAPER_RAMB_REGION_26_27 0x06f5 7770 #define regMPC_RMU1_SHAPER_RAMB_REGION_26_27_BASE_IDX 3 7771 #define regMPC_RMU1_SHAPER_RAMB_REGION_28_29 0x06f6 7772 #define regMPC_RMU1_SHAPER_RAMB_REGION_28_29_BASE_IDX 3 7773 #define regMPC_RMU1_SHAPER_RAMB_REGION_30_31 0x06f7 7774 #define regMPC_RMU1_SHAPER_RAMB_REGION_30_31_BASE_IDX 3 7775 #define regMPC_RMU1_SHAPER_RAMB_REGION_32_33 0x06f8 7776 #define regMPC_RMU1_SHAPER_RAMB_REGION_32_33_BASE_IDX 3 7777 #define regMPC_RMU1_3DLUT_MODE 0x06f9 7778 #define regMPC_RMU1_3DLUT_MODE_BASE_IDX 3 7779 #define regMPC_RMU1_3DLUT_INDEX 0x06fa 7780 #define regMPC_RMU1_3DLUT_INDEX_BASE_IDX 3 7781 #define regMPC_RMU1_3DLUT_DATA 0x06fb 7782 #define regMPC_RMU1_3DLUT_DATA_BASE_IDX 3 7783 #define regMPC_RMU1_3DLUT_DATA_30BIT 0x06fc 7784 #define regMPC_RMU1_3DLUT_DATA_30BIT_BASE_IDX 3 7785 #define regMPC_RMU1_3DLUT_READ_WRITE_CONTROL 0x06fd 7786 #define regMPC_RMU1_3DLUT_READ_WRITE_CONTROL_BASE_IDX 3 7787 #define regMPC_RMU1_3DLUT_OUT_NORM_FACTOR 0x06fe 7788 #define regMPC_RMU1_3DLUT_OUT_NORM_FACTOR_BASE_IDX 3 7789 #define regMPC_RMU1_3DLUT_OUT_OFFSET_R 0x06ff 7790 #define regMPC_RMU1_3DLUT_OUT_OFFSET_R_BASE_IDX 3 7791 #define regMPC_RMU1_3DLUT_OUT_OFFSET_G 0x0700 7792 #define regMPC_RMU1_3DLUT_OUT_OFFSET_G_BASE_IDX 3 7793 #define regMPC_RMU1_3DLUT_OUT_OFFSET_B 0x0701 7794 #define regMPC_RMU1_3DLUT_OUT_OFFSET_B_BASE_IDX 3 7795 7796 7797 // addressBlock: dce_dc_opp_abm0_dispdec 7798 // base address: 0x0 7799 #define regABM0_BL1_PWM_AMBIENT_LIGHT_LEVEL 0x0e7a 7800 #define regABM0_BL1_PWM_AMBIENT_LIGHT_LEVEL_BASE_IDX 3 7801 #define regABM0_BL1_PWM_USER_LEVEL 0x0e7b 7802 #define regABM0_BL1_PWM_USER_LEVEL_BASE_IDX 3 7803 #define regABM0_BL1_PWM_TARGET_ABM_LEVEL 0x0e7c 7804 #define regABM0_BL1_PWM_TARGET_ABM_LEVEL_BASE_IDX 3 7805 #define regABM0_BL1_PWM_CURRENT_ABM_LEVEL 0x0e7d 7806 #define regABM0_BL1_PWM_CURRENT_ABM_LEVEL_BASE_IDX 3 7807 #define regABM0_BL1_PWM_FINAL_DUTY_CYCLE 0x0e7e 7808 #define regABM0_BL1_PWM_FINAL_DUTY_CYCLE_BASE_IDX 3 7809 #define regABM0_BL1_PWM_MINIMUM_DUTY_CYCLE 0x0e7f 7810 #define regABM0_BL1_PWM_MINIMUM_DUTY_CYCLE_BASE_IDX 3 7811 #define regABM0_BL1_PWM_ABM_CNTL 0x0e80 7812 #define regABM0_BL1_PWM_ABM_CNTL_BASE_IDX 3 7813 #define regABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE 0x0e81 7814 #define regABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE_BASE_IDX 3 7815 #define regABM0_BL1_PWM_GRP2_REG_LOCK 0x0e82 7816 #define regABM0_BL1_PWM_GRP2_REG_LOCK_BASE_IDX 3 7817 #define regABM0_DC_ABM1_CNTL 0x0e83 7818 #define regABM0_DC_ABM1_CNTL_BASE_IDX 3 7819 #define regABM0_DC_ABM1_IPCSC_COEFF_SEL 0x0e84 7820 #define regABM0_DC_ABM1_IPCSC_COEFF_SEL_BASE_IDX 3 7821 #define regABM0_DC_ABM1_ACE_OFFSET_SLOPE_0 0x0e85 7822 #define regABM0_DC_ABM1_ACE_OFFSET_SLOPE_0_BASE_IDX 3 7823 #define regABM0_DC_ABM1_ACE_OFFSET_SLOPE_1 0x0e86 7824 #define regABM0_DC_ABM1_ACE_OFFSET_SLOPE_1_BASE_IDX 3 7825 #define regABM0_DC_ABM1_ACE_OFFSET_SLOPE_2 0x0e87 7826 #define regABM0_DC_ABM1_ACE_OFFSET_SLOPE_2_BASE_IDX 3 7827 #define regABM0_DC_ABM1_ACE_OFFSET_SLOPE_3 0x0e88 7828 #define regABM0_DC_ABM1_ACE_OFFSET_SLOPE_3_BASE_IDX 3 7829 #define regABM0_DC_ABM1_ACE_OFFSET_SLOPE_4 0x0e89 7830 #define regABM0_DC_ABM1_ACE_OFFSET_SLOPE_4_BASE_IDX 3 7831 #define regABM0_DC_ABM1_ACE_THRES_12 0x0e8a 7832 #define regABM0_DC_ABM1_ACE_THRES_12_BASE_IDX 3 7833 #define regABM0_DC_ABM1_ACE_THRES_34 0x0e8b 7834 #define regABM0_DC_ABM1_ACE_THRES_34_BASE_IDX 3 7835 #define regABM0_DC_ABM1_ACE_CNTL_MISC 0x0e8c 7836 #define regABM0_DC_ABM1_ACE_CNTL_MISC_BASE_IDX 3 7837 #define regABM0_DC_ABM1_HGLS_REG_READ_PROGRESS 0x0e8e 7838 #define regABM0_DC_ABM1_HGLS_REG_READ_PROGRESS_BASE_IDX 3 7839 #define regABM0_DC_ABM1_HG_MISC_CTRL 0x0e8f 7840 #define regABM0_DC_ABM1_HG_MISC_CTRL_BASE_IDX 3 7841 #define regABM0_DC_ABM1_LS_SUM_OF_LUMA 0x0e90 7842 #define regABM0_DC_ABM1_LS_SUM_OF_LUMA_BASE_IDX 3 7843 #define regABM0_DC_ABM1_LS_MIN_MAX_LUMA 0x0e91 7844 #define regABM0_DC_ABM1_LS_MIN_MAX_LUMA_BASE_IDX 3 7845 #define regABM0_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA 0x0e92 7846 #define regABM0_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA_BASE_IDX 3 7847 #define regABM0_DC_ABM1_LS_PIXEL_COUNT 0x0e93 7848 #define regABM0_DC_ABM1_LS_PIXEL_COUNT_BASE_IDX 3 7849 #define regABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES 0x0e94 7850 #define regABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES_BASE_IDX 3 7851 #define regABM0_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT 0x0e95 7852 #define regABM0_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT_BASE_IDX 3 7853 #define regABM0_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT 0x0e96 7854 #define regABM0_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT_BASE_IDX 3 7855 #define regABM0_DC_ABM1_HG_SAMPLE_RATE 0x0e97 7856 #define regABM0_DC_ABM1_HG_SAMPLE_RATE_BASE_IDX 3 7857 #define regABM0_DC_ABM1_LS_SAMPLE_RATE 0x0e98 7858 #define regABM0_DC_ABM1_LS_SAMPLE_RATE_BASE_IDX 3 7859 #define regABM0_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG 0x0e99 7860 #define regABM0_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG_BASE_IDX 3 7861 #define regABM0_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX 0x0e9a 7862 #define regABM0_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX_BASE_IDX 3 7863 #define regABM0_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX 0x0e9b 7864 #define regABM0_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX_BASE_IDX 3 7865 #define regABM0_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX 0x0e9c 7866 #define regABM0_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX_BASE_IDX 3 7867 #define regABM0_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX 0x0e9d 7868 #define regABM0_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX_BASE_IDX 3 7869 #define regABM0_DC_ABM1_HG_RESULT_1 0x0e9e 7870 #define regABM0_DC_ABM1_HG_RESULT_1_BASE_IDX 3 7871 #define regABM0_DC_ABM1_HG_RESULT_2 0x0e9f 7872 #define regABM0_DC_ABM1_HG_RESULT_2_BASE_IDX 3 7873 #define regABM0_DC_ABM1_HG_RESULT_3 0x0ea0 7874 #define regABM0_DC_ABM1_HG_RESULT_3_BASE_IDX 3 7875 #define regABM0_DC_ABM1_HG_RESULT_4 0x0ea1 7876 #define regABM0_DC_ABM1_HG_RESULT_4_BASE_IDX 3 7877 #define regABM0_DC_ABM1_HG_RESULT_5 0x0ea2 7878 #define regABM0_DC_ABM1_HG_RESULT_5_BASE_IDX 3 7879 #define regABM0_DC_ABM1_HG_RESULT_6 0x0ea3 7880 #define regABM0_DC_ABM1_HG_RESULT_6_BASE_IDX 3 7881 #define regABM0_DC_ABM1_HG_RESULT_7 0x0ea4 7882 #define regABM0_DC_ABM1_HG_RESULT_7_BASE_IDX 3 7883 #define regABM0_DC_ABM1_HG_RESULT_8 0x0ea5 7884 #define regABM0_DC_ABM1_HG_RESULT_8_BASE_IDX 3 7885 #define regABM0_DC_ABM1_HG_RESULT_9 0x0ea6 7886 #define regABM0_DC_ABM1_HG_RESULT_9_BASE_IDX 3 7887 #define regABM0_DC_ABM1_HG_RESULT_10 0x0ea7 7888 #define regABM0_DC_ABM1_HG_RESULT_10_BASE_IDX 3 7889 #define regABM0_DC_ABM1_HG_RESULT_11 0x0ea8 7890 #define regABM0_DC_ABM1_HG_RESULT_11_BASE_IDX 3 7891 #define regABM0_DC_ABM1_HG_RESULT_12 0x0ea9 7892 #define regABM0_DC_ABM1_HG_RESULT_12_BASE_IDX 3 7893 #define regABM0_DC_ABM1_HG_RESULT_13 0x0eaa 7894 #define regABM0_DC_ABM1_HG_RESULT_13_BASE_IDX 3 7895 #define regABM0_DC_ABM1_HG_RESULT_14 0x0eab 7896 #define regABM0_DC_ABM1_HG_RESULT_14_BASE_IDX 3 7897 #define regABM0_DC_ABM1_HG_RESULT_15 0x0eac 7898 #define regABM0_DC_ABM1_HG_RESULT_15_BASE_IDX 3 7899 #define regABM0_DC_ABM1_HG_RESULT_16 0x0ead 7900 #define regABM0_DC_ABM1_HG_RESULT_16_BASE_IDX 3 7901 #define regABM0_DC_ABM1_HG_RESULT_17 0x0eae 7902 #define regABM0_DC_ABM1_HG_RESULT_17_BASE_IDX 3 7903 #define regABM0_DC_ABM1_HG_RESULT_18 0x0eaf 7904 #define regABM0_DC_ABM1_HG_RESULT_18_BASE_IDX 3 7905 #define regABM0_DC_ABM1_HG_RESULT_19 0x0eb0 7906 #define regABM0_DC_ABM1_HG_RESULT_19_BASE_IDX 3 7907 #define regABM0_DC_ABM1_HG_RESULT_20 0x0eb1 7908 #define regABM0_DC_ABM1_HG_RESULT_20_BASE_IDX 3 7909 #define regABM0_DC_ABM1_HG_RESULT_21 0x0eb2 7910 #define regABM0_DC_ABM1_HG_RESULT_21_BASE_IDX 3 7911 #define regABM0_DC_ABM1_HG_RESULT_22 0x0eb3 7912 #define regABM0_DC_ABM1_HG_RESULT_22_BASE_IDX 3 7913 #define regABM0_DC_ABM1_HG_RESULT_23 0x0eb4 7914 #define regABM0_DC_ABM1_HG_RESULT_23_BASE_IDX 3 7915 #define regABM0_DC_ABM1_HG_RESULT_24 0x0eb5 7916 #define regABM0_DC_ABM1_HG_RESULT_24_BASE_IDX 3 7917 #define regABM0_DC_ABM1_BL_MASTER_LOCK 0x0eb6 7918 #define regABM0_DC_ABM1_BL_MASTER_LOCK_BASE_IDX 3 7919 7920 7921 // addressBlock: dce_dc_opp_abm1_dispdec 7922 // base address: 0x104 7923 #define regABM1_BL1_PWM_AMBIENT_LIGHT_LEVEL 0x0ebb 7924 #define regABM1_BL1_PWM_AMBIENT_LIGHT_LEVEL_BASE_IDX 3 7925 #define regABM1_BL1_PWM_USER_LEVEL 0x0ebc 7926 #define regABM1_BL1_PWM_USER_LEVEL_BASE_IDX 3 7927 #define regABM1_BL1_PWM_TARGET_ABM_LEVEL 0x0ebd 7928 #define regABM1_BL1_PWM_TARGET_ABM_LEVEL_BASE_IDX 3 7929 #define regABM1_BL1_PWM_CURRENT_ABM_LEVEL 0x0ebe 7930 #define regABM1_BL1_PWM_CURRENT_ABM_LEVEL_BASE_IDX 3 7931 #define regABM1_BL1_PWM_FINAL_DUTY_CYCLE 0x0ebf 7932 #define regABM1_BL1_PWM_FINAL_DUTY_CYCLE_BASE_IDX 3 7933 #define regABM1_BL1_PWM_MINIMUM_DUTY_CYCLE 0x0ec0 7934 #define regABM1_BL1_PWM_MINIMUM_DUTY_CYCLE_BASE_IDX 3 7935 #define regABM1_BL1_PWM_ABM_CNTL 0x0ec1 7936 #define regABM1_BL1_PWM_ABM_CNTL_BASE_IDX 3 7937 #define regABM1_BL1_PWM_BL_UPDATE_SAMPLE_RATE 0x0ec2 7938 #define regABM1_BL1_PWM_BL_UPDATE_SAMPLE_RATE_BASE_IDX 3 7939 #define regABM1_BL1_PWM_GRP2_REG_LOCK 0x0ec3 7940 #define regABM1_BL1_PWM_GRP2_REG_LOCK_BASE_IDX 3 7941 #define regABM1_DC_ABM1_CNTL 0x0ec4 7942 #define regABM1_DC_ABM1_CNTL_BASE_IDX 3 7943 #define regABM1_DC_ABM1_IPCSC_COEFF_SEL 0x0ec5 7944 #define regABM1_DC_ABM1_IPCSC_COEFF_SEL_BASE_IDX 3 7945 #define regABM1_DC_ABM1_ACE_OFFSET_SLOPE_0 0x0ec6 7946 #define regABM1_DC_ABM1_ACE_OFFSET_SLOPE_0_BASE_IDX 3 7947 #define regABM1_DC_ABM1_ACE_OFFSET_SLOPE_1 0x0ec7 7948 #define regABM1_DC_ABM1_ACE_OFFSET_SLOPE_1_BASE_IDX 3 7949 #define regABM1_DC_ABM1_ACE_OFFSET_SLOPE_2 0x0ec8 7950 #define regABM1_DC_ABM1_ACE_OFFSET_SLOPE_2_BASE_IDX 3 7951 #define regABM1_DC_ABM1_ACE_OFFSET_SLOPE_3 0x0ec9 7952 #define regABM1_DC_ABM1_ACE_OFFSET_SLOPE_3_BASE_IDX 3 7953 #define regABM1_DC_ABM1_ACE_OFFSET_SLOPE_4 0x0eca 7954 #define regABM1_DC_ABM1_ACE_OFFSET_SLOPE_4_BASE_IDX 3 7955 #define regABM1_DC_ABM1_ACE_THRES_12 0x0ecb 7956 #define regABM1_DC_ABM1_ACE_THRES_12_BASE_IDX 3 7957 #define regABM1_DC_ABM1_ACE_THRES_34 0x0ecc 7958 #define regABM1_DC_ABM1_ACE_THRES_34_BASE_IDX 3 7959 #define regABM1_DC_ABM1_ACE_CNTL_MISC 0x0ecd 7960 #define regABM1_DC_ABM1_ACE_CNTL_MISC_BASE_IDX 3 7961 #define regABM1_DC_ABM1_HGLS_REG_READ_PROGRESS 0x0ecf 7962 #define regABM1_DC_ABM1_HGLS_REG_READ_PROGRESS_BASE_IDX 3 7963 #define regABM1_DC_ABM1_HG_MISC_CTRL 0x0ed0 7964 #define regABM1_DC_ABM1_HG_MISC_CTRL_BASE_IDX 3 7965 #define regABM1_DC_ABM1_LS_SUM_OF_LUMA 0x0ed1 7966 #define regABM1_DC_ABM1_LS_SUM_OF_LUMA_BASE_IDX 3 7967 #define regABM1_DC_ABM1_LS_MIN_MAX_LUMA 0x0ed2 7968 #define regABM1_DC_ABM1_LS_MIN_MAX_LUMA_BASE_IDX 3 7969 #define regABM1_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA 0x0ed3 7970 #define regABM1_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA_BASE_IDX 3 7971 #define regABM1_DC_ABM1_LS_PIXEL_COUNT 0x0ed4 7972 #define regABM1_DC_ABM1_LS_PIXEL_COUNT_BASE_IDX 3 7973 #define regABM1_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES 0x0ed5 7974 #define regABM1_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES_BASE_IDX 3 7975 #define regABM1_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT 0x0ed6 7976 #define regABM1_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT_BASE_IDX 3 7977 #define regABM1_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT 0x0ed7 7978 #define regABM1_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT_BASE_IDX 3 7979 #define regABM1_DC_ABM1_HG_SAMPLE_RATE 0x0ed8 7980 #define regABM1_DC_ABM1_HG_SAMPLE_RATE_BASE_IDX 3 7981 #define regABM1_DC_ABM1_LS_SAMPLE_RATE 0x0ed9 7982 #define regABM1_DC_ABM1_LS_SAMPLE_RATE_BASE_IDX 3 7983 #define regABM1_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG 0x0eda 7984 #define regABM1_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG_BASE_IDX 3 7985 #define regABM1_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX 0x0edb 7986 #define regABM1_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX_BASE_IDX 3 7987 #define regABM1_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX 0x0edc 7988 #define regABM1_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX_BASE_IDX 3 7989 #define regABM1_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX 0x0edd 7990 #define regABM1_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX_BASE_IDX 3 7991 #define regABM1_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX 0x0ede 7992 #define regABM1_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX_BASE_IDX 3 7993 #define regABM1_DC_ABM1_HG_RESULT_1 0x0edf 7994 #define regABM1_DC_ABM1_HG_RESULT_1_BASE_IDX 3 7995 #define regABM1_DC_ABM1_HG_RESULT_2 0x0ee0 7996 #define regABM1_DC_ABM1_HG_RESULT_2_BASE_IDX 3 7997 #define regABM1_DC_ABM1_HG_RESULT_3 0x0ee1 7998 #define regABM1_DC_ABM1_HG_RESULT_3_BASE_IDX 3 7999 #define regABM1_DC_ABM1_HG_RESULT_4 0x0ee2 8000 #define regABM1_DC_ABM1_HG_RESULT_4_BASE_IDX 3 8001 #define regABM1_DC_ABM1_HG_RESULT_5 0x0ee3 8002 #define regABM1_DC_ABM1_HG_RESULT_5_BASE_IDX 3 8003 #define regABM1_DC_ABM1_HG_RESULT_6 0x0ee4 8004 #define regABM1_DC_ABM1_HG_RESULT_6_BASE_IDX 3 8005 #define regABM1_DC_ABM1_HG_RESULT_7 0x0ee5 8006 #define regABM1_DC_ABM1_HG_RESULT_7_BASE_IDX 3 8007 #define regABM1_DC_ABM1_HG_RESULT_8 0x0ee6 8008 #define regABM1_DC_ABM1_HG_RESULT_8_BASE_IDX 3 8009 #define regABM1_DC_ABM1_HG_RESULT_9 0x0ee7 8010 #define regABM1_DC_ABM1_HG_RESULT_9_BASE_IDX 3 8011 #define regABM1_DC_ABM1_HG_RESULT_10 0x0ee8 8012 #define regABM1_DC_ABM1_HG_RESULT_10_BASE_IDX 3 8013 #define regABM1_DC_ABM1_HG_RESULT_11 0x0ee9 8014 #define regABM1_DC_ABM1_HG_RESULT_11_BASE_IDX 3 8015 #define regABM1_DC_ABM1_HG_RESULT_12 0x0eea 8016 #define regABM1_DC_ABM1_HG_RESULT_12_BASE_IDX 3 8017 #define regABM1_DC_ABM1_HG_RESULT_13 0x0eeb 8018 #define regABM1_DC_ABM1_HG_RESULT_13_BASE_IDX 3 8019 #define regABM1_DC_ABM1_HG_RESULT_14 0x0eec 8020 #define regABM1_DC_ABM1_HG_RESULT_14_BASE_IDX 3 8021 #define regABM1_DC_ABM1_HG_RESULT_15 0x0eed 8022 #define regABM1_DC_ABM1_HG_RESULT_15_BASE_IDX 3 8023 #define regABM1_DC_ABM1_HG_RESULT_16 0x0eee 8024 #define regABM1_DC_ABM1_HG_RESULT_16_BASE_IDX 3 8025 #define regABM1_DC_ABM1_HG_RESULT_17 0x0eef 8026 #define regABM1_DC_ABM1_HG_RESULT_17_BASE_IDX 3 8027 #define regABM1_DC_ABM1_HG_RESULT_18 0x0ef0 8028 #define regABM1_DC_ABM1_HG_RESULT_18_BASE_IDX 3 8029 #define regABM1_DC_ABM1_HG_RESULT_19 0x0ef1 8030 #define regABM1_DC_ABM1_HG_RESULT_19_BASE_IDX 3 8031 #define regABM1_DC_ABM1_HG_RESULT_20 0x0ef2 8032 #define regABM1_DC_ABM1_HG_RESULT_20_BASE_IDX 3 8033 #define regABM1_DC_ABM1_HG_RESULT_21 0x0ef3 8034 #define regABM1_DC_ABM1_HG_RESULT_21_BASE_IDX 3 8035 #define regABM1_DC_ABM1_HG_RESULT_22 0x0ef4 8036 #define regABM1_DC_ABM1_HG_RESULT_22_BASE_IDX 3 8037 #define regABM1_DC_ABM1_HG_RESULT_23 0x0ef5 8038 #define regABM1_DC_ABM1_HG_RESULT_23_BASE_IDX 3 8039 #define regABM1_DC_ABM1_HG_RESULT_24 0x0ef6 8040 #define regABM1_DC_ABM1_HG_RESULT_24_BASE_IDX 3 8041 #define regABM1_DC_ABM1_BL_MASTER_LOCK 0x0ef7 8042 #define regABM1_DC_ABM1_BL_MASTER_LOCK_BASE_IDX 3 8043 8044 8045 // addressBlock: dce_dc_opp_abm2_dispdec 8046 // base address: 0x208 8047 #define regABM2_BL1_PWM_AMBIENT_LIGHT_LEVEL 0x0efc 8048 #define regABM2_BL1_PWM_AMBIENT_LIGHT_LEVEL_BASE_IDX 3 8049 #define regABM2_BL1_PWM_USER_LEVEL 0x0efd 8050 #define regABM2_BL1_PWM_USER_LEVEL_BASE_IDX 3 8051 #define regABM2_BL1_PWM_TARGET_ABM_LEVEL 0x0efe 8052 #define regABM2_BL1_PWM_TARGET_ABM_LEVEL_BASE_IDX 3 8053 #define regABM2_BL1_PWM_CURRENT_ABM_LEVEL 0x0eff 8054 #define regABM2_BL1_PWM_CURRENT_ABM_LEVEL_BASE_IDX 3 8055 #define regABM2_BL1_PWM_FINAL_DUTY_CYCLE 0x0f00 8056 #define regABM2_BL1_PWM_FINAL_DUTY_CYCLE_BASE_IDX 3 8057 #define regABM2_BL1_PWM_MINIMUM_DUTY_CYCLE 0x0f01 8058 #define regABM2_BL1_PWM_MINIMUM_DUTY_CYCLE_BASE_IDX 3 8059 #define regABM2_BL1_PWM_ABM_CNTL 0x0f02 8060 #define regABM2_BL1_PWM_ABM_CNTL_BASE_IDX 3 8061 #define regABM2_BL1_PWM_BL_UPDATE_SAMPLE_RATE 0x0f03 8062 #define regABM2_BL1_PWM_BL_UPDATE_SAMPLE_RATE_BASE_IDX 3 8063 #define regABM2_BL1_PWM_GRP2_REG_LOCK 0x0f04 8064 #define regABM2_BL1_PWM_GRP2_REG_LOCK_BASE_IDX 3 8065 #define regABM2_DC_ABM1_CNTL 0x0f05 8066 #define regABM2_DC_ABM1_CNTL_BASE_IDX 3 8067 #define regABM2_DC_ABM1_IPCSC_COEFF_SEL 0x0f06 8068 #define regABM2_DC_ABM1_IPCSC_COEFF_SEL_BASE_IDX 3 8069 #define regABM2_DC_ABM1_ACE_OFFSET_SLOPE_0 0x0f07 8070 #define regABM2_DC_ABM1_ACE_OFFSET_SLOPE_0_BASE_IDX 3 8071 #define regABM2_DC_ABM1_ACE_OFFSET_SLOPE_1 0x0f08 8072 #define regABM2_DC_ABM1_ACE_OFFSET_SLOPE_1_BASE_IDX 3 8073 #define regABM2_DC_ABM1_ACE_OFFSET_SLOPE_2 0x0f09 8074 #define regABM2_DC_ABM1_ACE_OFFSET_SLOPE_2_BASE_IDX 3 8075 #define regABM2_DC_ABM1_ACE_OFFSET_SLOPE_3 0x0f0a 8076 #define regABM2_DC_ABM1_ACE_OFFSET_SLOPE_3_BASE_IDX 3 8077 #define regABM2_DC_ABM1_ACE_OFFSET_SLOPE_4 0x0f0b 8078 #define regABM2_DC_ABM1_ACE_OFFSET_SLOPE_4_BASE_IDX 3 8079 #define regABM2_DC_ABM1_ACE_THRES_12 0x0f0c 8080 #define regABM2_DC_ABM1_ACE_THRES_12_BASE_IDX 3 8081 #define regABM2_DC_ABM1_ACE_THRES_34 0x0f0d 8082 #define regABM2_DC_ABM1_ACE_THRES_34_BASE_IDX 3 8083 #define regABM2_DC_ABM1_ACE_CNTL_MISC 0x0f0e 8084 #define regABM2_DC_ABM1_ACE_CNTL_MISC_BASE_IDX 3 8085 #define regABM2_DC_ABM1_HGLS_REG_READ_PROGRESS 0x0f10 8086 #define regABM2_DC_ABM1_HGLS_REG_READ_PROGRESS_BASE_IDX 3 8087 #define regABM2_DC_ABM1_HG_MISC_CTRL 0x0f11 8088 #define regABM2_DC_ABM1_HG_MISC_CTRL_BASE_IDX 3 8089 #define regABM2_DC_ABM1_LS_SUM_OF_LUMA 0x0f12 8090 #define regABM2_DC_ABM1_LS_SUM_OF_LUMA_BASE_IDX 3 8091 #define regABM2_DC_ABM1_LS_MIN_MAX_LUMA 0x0f13 8092 #define regABM2_DC_ABM1_LS_MIN_MAX_LUMA_BASE_IDX 3 8093 #define regABM2_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA 0x0f14 8094 #define regABM2_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA_BASE_IDX 3 8095 #define regABM2_DC_ABM1_LS_PIXEL_COUNT 0x0f15 8096 #define regABM2_DC_ABM1_LS_PIXEL_COUNT_BASE_IDX 3 8097 #define regABM2_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES 0x0f16 8098 #define regABM2_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES_BASE_IDX 3 8099 #define regABM2_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT 0x0f17 8100 #define regABM2_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT_BASE_IDX 3 8101 #define regABM2_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT 0x0f18 8102 #define regABM2_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT_BASE_IDX 3 8103 #define regABM2_DC_ABM1_HG_SAMPLE_RATE 0x0f19 8104 #define regABM2_DC_ABM1_HG_SAMPLE_RATE_BASE_IDX 3 8105 #define regABM2_DC_ABM1_LS_SAMPLE_RATE 0x0f1a 8106 #define regABM2_DC_ABM1_LS_SAMPLE_RATE_BASE_IDX 3 8107 #define regABM2_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG 0x0f1b 8108 #define regABM2_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG_BASE_IDX 3 8109 #define regABM2_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX 0x0f1c 8110 #define regABM2_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX_BASE_IDX 3 8111 #define regABM2_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX 0x0f1d 8112 #define regABM2_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX_BASE_IDX 3 8113 #define regABM2_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX 0x0f1e 8114 #define regABM2_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX_BASE_IDX 3 8115 #define regABM2_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX 0x0f1f 8116 #define regABM2_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX_BASE_IDX 3 8117 #define regABM2_DC_ABM1_HG_RESULT_1 0x0f20 8118 #define regABM2_DC_ABM1_HG_RESULT_1_BASE_IDX 3 8119 #define regABM2_DC_ABM1_HG_RESULT_2 0x0f21 8120 #define regABM2_DC_ABM1_HG_RESULT_2_BASE_IDX 3 8121 #define regABM2_DC_ABM1_HG_RESULT_3 0x0f22 8122 #define regABM2_DC_ABM1_HG_RESULT_3_BASE_IDX 3 8123 #define regABM2_DC_ABM1_HG_RESULT_4 0x0f23 8124 #define regABM2_DC_ABM1_HG_RESULT_4_BASE_IDX 3 8125 #define regABM2_DC_ABM1_HG_RESULT_5 0x0f24 8126 #define regABM2_DC_ABM1_HG_RESULT_5_BASE_IDX 3 8127 #define regABM2_DC_ABM1_HG_RESULT_6 0x0f25 8128 #define regABM2_DC_ABM1_HG_RESULT_6_BASE_IDX 3 8129 #define regABM2_DC_ABM1_HG_RESULT_7 0x0f26 8130 #define regABM2_DC_ABM1_HG_RESULT_7_BASE_IDX 3 8131 #define regABM2_DC_ABM1_HG_RESULT_8 0x0f27 8132 #define regABM2_DC_ABM1_HG_RESULT_8_BASE_IDX 3 8133 #define regABM2_DC_ABM1_HG_RESULT_9 0x0f28 8134 #define regABM2_DC_ABM1_HG_RESULT_9_BASE_IDX 3 8135 #define regABM2_DC_ABM1_HG_RESULT_10 0x0f29 8136 #define regABM2_DC_ABM1_HG_RESULT_10_BASE_IDX 3 8137 #define regABM2_DC_ABM1_HG_RESULT_11 0x0f2a 8138 #define regABM2_DC_ABM1_HG_RESULT_11_BASE_IDX 3 8139 #define regABM2_DC_ABM1_HG_RESULT_12 0x0f2b 8140 #define regABM2_DC_ABM1_HG_RESULT_12_BASE_IDX 3 8141 #define regABM2_DC_ABM1_HG_RESULT_13 0x0f2c 8142 #define regABM2_DC_ABM1_HG_RESULT_13_BASE_IDX 3 8143 #define regABM2_DC_ABM1_HG_RESULT_14 0x0f2d 8144 #define regABM2_DC_ABM1_HG_RESULT_14_BASE_IDX 3 8145 #define regABM2_DC_ABM1_HG_RESULT_15 0x0f2e 8146 #define regABM2_DC_ABM1_HG_RESULT_15_BASE_IDX 3 8147 #define regABM2_DC_ABM1_HG_RESULT_16 0x0f2f 8148 #define regABM2_DC_ABM1_HG_RESULT_16_BASE_IDX 3 8149 #define regABM2_DC_ABM1_HG_RESULT_17 0x0f30 8150 #define regABM2_DC_ABM1_HG_RESULT_17_BASE_IDX 3 8151 #define regABM2_DC_ABM1_HG_RESULT_18 0x0f31 8152 #define regABM2_DC_ABM1_HG_RESULT_18_BASE_IDX 3 8153 #define regABM2_DC_ABM1_HG_RESULT_19 0x0f32 8154 #define regABM2_DC_ABM1_HG_RESULT_19_BASE_IDX 3 8155 #define regABM2_DC_ABM1_HG_RESULT_20 0x0f33 8156 #define regABM2_DC_ABM1_HG_RESULT_20_BASE_IDX 3 8157 #define regABM2_DC_ABM1_HG_RESULT_21 0x0f34 8158 #define regABM2_DC_ABM1_HG_RESULT_21_BASE_IDX 3 8159 #define regABM2_DC_ABM1_HG_RESULT_22 0x0f35 8160 #define regABM2_DC_ABM1_HG_RESULT_22_BASE_IDX 3 8161 #define regABM2_DC_ABM1_HG_RESULT_23 0x0f36 8162 #define regABM2_DC_ABM1_HG_RESULT_23_BASE_IDX 3 8163 #define regABM2_DC_ABM1_HG_RESULT_24 0x0f37 8164 #define regABM2_DC_ABM1_HG_RESULT_24_BASE_IDX 3 8165 #define regABM2_DC_ABM1_BL_MASTER_LOCK 0x0f38 8166 #define regABM2_DC_ABM1_BL_MASTER_LOCK_BASE_IDX 3 8167 8168 8169 // addressBlock: dce_dc_opp_abm3_dispdec 8170 // base address: 0x30c 8171 #define regABM3_BL1_PWM_AMBIENT_LIGHT_LEVEL 0x0f3d 8172 #define regABM3_BL1_PWM_AMBIENT_LIGHT_LEVEL_BASE_IDX 3 8173 #define regABM3_BL1_PWM_USER_LEVEL 0x0f3e 8174 #define regABM3_BL1_PWM_USER_LEVEL_BASE_IDX 3 8175 #define regABM3_BL1_PWM_TARGET_ABM_LEVEL 0x0f3f 8176 #define regABM3_BL1_PWM_TARGET_ABM_LEVEL_BASE_IDX 3 8177 #define regABM3_BL1_PWM_CURRENT_ABM_LEVEL 0x0f40 8178 #define regABM3_BL1_PWM_CURRENT_ABM_LEVEL_BASE_IDX 3 8179 #define regABM3_BL1_PWM_FINAL_DUTY_CYCLE 0x0f41 8180 #define regABM3_BL1_PWM_FINAL_DUTY_CYCLE_BASE_IDX 3 8181 #define regABM3_BL1_PWM_MINIMUM_DUTY_CYCLE 0x0f42 8182 #define regABM3_BL1_PWM_MINIMUM_DUTY_CYCLE_BASE_IDX 3 8183 #define regABM3_BL1_PWM_ABM_CNTL 0x0f43 8184 #define regABM3_BL1_PWM_ABM_CNTL_BASE_IDX 3 8185 #define regABM3_BL1_PWM_BL_UPDATE_SAMPLE_RATE 0x0f44 8186 #define regABM3_BL1_PWM_BL_UPDATE_SAMPLE_RATE_BASE_IDX 3 8187 #define regABM3_BL1_PWM_GRP2_REG_LOCK 0x0f45 8188 #define regABM3_BL1_PWM_GRP2_REG_LOCK_BASE_IDX 3 8189 #define regABM3_DC_ABM1_CNTL 0x0f46 8190 #define regABM3_DC_ABM1_CNTL_BASE_IDX 3 8191 #define regABM3_DC_ABM1_IPCSC_COEFF_SEL 0x0f47 8192 #define regABM3_DC_ABM1_IPCSC_COEFF_SEL_BASE_IDX 3 8193 #define regABM3_DC_ABM1_ACE_OFFSET_SLOPE_0 0x0f48 8194 #define regABM3_DC_ABM1_ACE_OFFSET_SLOPE_0_BASE_IDX 3 8195 #define regABM3_DC_ABM1_ACE_OFFSET_SLOPE_1 0x0f49 8196 #define regABM3_DC_ABM1_ACE_OFFSET_SLOPE_1_BASE_IDX 3 8197 #define regABM3_DC_ABM1_ACE_OFFSET_SLOPE_2 0x0f4a 8198 #define regABM3_DC_ABM1_ACE_OFFSET_SLOPE_2_BASE_IDX 3 8199 #define regABM3_DC_ABM1_ACE_OFFSET_SLOPE_3 0x0f4b 8200 #define regABM3_DC_ABM1_ACE_OFFSET_SLOPE_3_BASE_IDX 3 8201 #define regABM3_DC_ABM1_ACE_OFFSET_SLOPE_4 0x0f4c 8202 #define regABM3_DC_ABM1_ACE_OFFSET_SLOPE_4_BASE_IDX 3 8203 #define regABM3_DC_ABM1_ACE_THRES_12 0x0f4d 8204 #define regABM3_DC_ABM1_ACE_THRES_12_BASE_IDX 3 8205 #define regABM3_DC_ABM1_ACE_THRES_34 0x0f4e 8206 #define regABM3_DC_ABM1_ACE_THRES_34_BASE_IDX 3 8207 #define regABM3_DC_ABM1_ACE_CNTL_MISC 0x0f4f 8208 #define regABM3_DC_ABM1_ACE_CNTL_MISC_BASE_IDX 3 8209 #define regABM3_DC_ABM1_HGLS_REG_READ_PROGRESS 0x0f51 8210 #define regABM3_DC_ABM1_HGLS_REG_READ_PROGRESS_BASE_IDX 3 8211 #define regABM3_DC_ABM1_HG_MISC_CTRL 0x0f52 8212 #define regABM3_DC_ABM1_HG_MISC_CTRL_BASE_IDX 3 8213 #define regABM3_DC_ABM1_LS_SUM_OF_LUMA 0x0f53 8214 #define regABM3_DC_ABM1_LS_SUM_OF_LUMA_BASE_IDX 3 8215 #define regABM3_DC_ABM1_LS_MIN_MAX_LUMA 0x0f54 8216 #define regABM3_DC_ABM1_LS_MIN_MAX_LUMA_BASE_IDX 3 8217 #define regABM3_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA 0x0f55 8218 #define regABM3_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA_BASE_IDX 3 8219 #define regABM3_DC_ABM1_LS_PIXEL_COUNT 0x0f56 8220 #define regABM3_DC_ABM1_LS_PIXEL_COUNT_BASE_IDX 3 8221 #define regABM3_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES 0x0f57 8222 #define regABM3_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES_BASE_IDX 3 8223 #define regABM3_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT 0x0f58 8224 #define regABM3_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT_BASE_IDX 3 8225 #define regABM3_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT 0x0f59 8226 #define regABM3_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT_BASE_IDX 3 8227 #define regABM3_DC_ABM1_HG_SAMPLE_RATE 0x0f5a 8228 #define regABM3_DC_ABM1_HG_SAMPLE_RATE_BASE_IDX 3 8229 #define regABM3_DC_ABM1_LS_SAMPLE_RATE 0x0f5b 8230 #define regABM3_DC_ABM1_LS_SAMPLE_RATE_BASE_IDX 3 8231 #define regABM3_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG 0x0f5c 8232 #define regABM3_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG_BASE_IDX 3 8233 #define regABM3_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX 0x0f5d 8234 #define regABM3_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX_BASE_IDX 3 8235 #define regABM3_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX 0x0f5e 8236 #define regABM3_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX_BASE_IDX 3 8237 #define regABM3_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX 0x0f5f 8238 #define regABM3_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX_BASE_IDX 3 8239 #define regABM3_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX 0x0f60 8240 #define regABM3_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX_BASE_IDX 3 8241 #define regABM3_DC_ABM1_HG_RESULT_1 0x0f61 8242 #define regABM3_DC_ABM1_HG_RESULT_1_BASE_IDX 3 8243 #define regABM3_DC_ABM1_HG_RESULT_2 0x0f62 8244 #define regABM3_DC_ABM1_HG_RESULT_2_BASE_IDX 3 8245 #define regABM3_DC_ABM1_HG_RESULT_3 0x0f63 8246 #define regABM3_DC_ABM1_HG_RESULT_3_BASE_IDX 3 8247 #define regABM3_DC_ABM1_HG_RESULT_4 0x0f64 8248 #define regABM3_DC_ABM1_HG_RESULT_4_BASE_IDX 3 8249 #define regABM3_DC_ABM1_HG_RESULT_5 0x0f65 8250 #define regABM3_DC_ABM1_HG_RESULT_5_BASE_IDX 3 8251 #define regABM3_DC_ABM1_HG_RESULT_6 0x0f66 8252 #define regABM3_DC_ABM1_HG_RESULT_6_BASE_IDX 3 8253 #define regABM3_DC_ABM1_HG_RESULT_7 0x0f67 8254 #define regABM3_DC_ABM1_HG_RESULT_7_BASE_IDX 3 8255 #define regABM3_DC_ABM1_HG_RESULT_8 0x0f68 8256 #define regABM3_DC_ABM1_HG_RESULT_8_BASE_IDX 3 8257 #define regABM3_DC_ABM1_HG_RESULT_9 0x0f69 8258 #define regABM3_DC_ABM1_HG_RESULT_9_BASE_IDX 3 8259 #define regABM3_DC_ABM1_HG_RESULT_10 0x0f6a 8260 #define regABM3_DC_ABM1_HG_RESULT_10_BASE_IDX 3 8261 #define regABM3_DC_ABM1_HG_RESULT_11 0x0f6b 8262 #define regABM3_DC_ABM1_HG_RESULT_11_BASE_IDX 3 8263 #define regABM3_DC_ABM1_HG_RESULT_12 0x0f6c 8264 #define regABM3_DC_ABM1_HG_RESULT_12_BASE_IDX 3 8265 #define regABM3_DC_ABM1_HG_RESULT_13 0x0f6d 8266 #define regABM3_DC_ABM1_HG_RESULT_13_BASE_IDX 3 8267 #define regABM3_DC_ABM1_HG_RESULT_14 0x0f6e 8268 #define regABM3_DC_ABM1_HG_RESULT_14_BASE_IDX 3 8269 #define regABM3_DC_ABM1_HG_RESULT_15 0x0f6f 8270 #define regABM3_DC_ABM1_HG_RESULT_15_BASE_IDX 3 8271 #define regABM3_DC_ABM1_HG_RESULT_16 0x0f70 8272 #define regABM3_DC_ABM1_HG_RESULT_16_BASE_IDX 3 8273 #define regABM3_DC_ABM1_HG_RESULT_17 0x0f71 8274 #define regABM3_DC_ABM1_HG_RESULT_17_BASE_IDX 3 8275 #define regABM3_DC_ABM1_HG_RESULT_18 0x0f72 8276 #define regABM3_DC_ABM1_HG_RESULT_18_BASE_IDX 3 8277 #define regABM3_DC_ABM1_HG_RESULT_19 0x0f73 8278 #define regABM3_DC_ABM1_HG_RESULT_19_BASE_IDX 3 8279 #define regABM3_DC_ABM1_HG_RESULT_20 0x0f74 8280 #define regABM3_DC_ABM1_HG_RESULT_20_BASE_IDX 3 8281 #define regABM3_DC_ABM1_HG_RESULT_21 0x0f75 8282 #define regABM3_DC_ABM1_HG_RESULT_21_BASE_IDX 3 8283 #define regABM3_DC_ABM1_HG_RESULT_22 0x0f76 8284 #define regABM3_DC_ABM1_HG_RESULT_22_BASE_IDX 3 8285 #define regABM3_DC_ABM1_HG_RESULT_23 0x0f77 8286 #define regABM3_DC_ABM1_HG_RESULT_23_BASE_IDX 3 8287 #define regABM3_DC_ABM1_HG_RESULT_24 0x0f78 8288 #define regABM3_DC_ABM1_HG_RESULT_24_BASE_IDX 3 8289 #define regABM3_DC_ABM1_BL_MASTER_LOCK 0x0f79 8290 #define regABM3_DC_ABM1_BL_MASTER_LOCK_BASE_IDX 3 8291 8292 8293 // addressBlock: dce_dc_opp_dpg0_dispdec 8294 // base address: 0x0 8295 #define regDPG0_DPG_CONTROL 0x1854 8296 #define regDPG0_DPG_CONTROL_BASE_IDX 2 8297 #define regDPG0_DPG_RAMP_CONTROL 0x1855 8298 #define regDPG0_DPG_RAMP_CONTROL_BASE_IDX 2 8299 #define regDPG0_DPG_DIMENSIONS 0x1856 8300 #define regDPG0_DPG_DIMENSIONS_BASE_IDX 2 8301 #define regDPG0_DPG_COLOUR_R_CR 0x1857 8302 #define regDPG0_DPG_COLOUR_R_CR_BASE_IDX 2 8303 #define regDPG0_DPG_COLOUR_G_Y 0x1858 8304 #define regDPG0_DPG_COLOUR_G_Y_BASE_IDX 2 8305 #define regDPG0_DPG_COLOUR_B_CB 0x1859 8306 #define regDPG0_DPG_COLOUR_B_CB_BASE_IDX 2 8307 #define regDPG0_DPG_OFFSET_SEGMENT 0x185a 8308 #define regDPG0_DPG_OFFSET_SEGMENT_BASE_IDX 2 8309 #define regDPG0_DPG_STATUS 0x185b 8310 #define regDPG0_DPG_STATUS_BASE_IDX 2 8311 8312 8313 // addressBlock: dce_dc_opp_fmt0_dispdec 8314 // base address: 0x0 8315 #define regFMT0_FMT_CLAMP_COMPONENT_R 0x183c 8316 #define regFMT0_FMT_CLAMP_COMPONENT_R_BASE_IDX 2 8317 #define regFMT0_FMT_CLAMP_COMPONENT_G 0x183d 8318 #define regFMT0_FMT_CLAMP_COMPONENT_G_BASE_IDX 2 8319 #define regFMT0_FMT_CLAMP_COMPONENT_B 0x183e 8320 #define regFMT0_FMT_CLAMP_COMPONENT_B_BASE_IDX 2 8321 #define regFMT0_FMT_DYNAMIC_EXP_CNTL 0x183f 8322 #define regFMT0_FMT_DYNAMIC_EXP_CNTL_BASE_IDX 2 8323 #define regFMT0_FMT_CONTROL 0x1840 8324 #define regFMT0_FMT_CONTROL_BASE_IDX 2 8325 #define regFMT0_FMT_BIT_DEPTH_CONTROL 0x1841 8326 #define regFMT0_FMT_BIT_DEPTH_CONTROL_BASE_IDX 2 8327 #define regFMT0_FMT_DITHER_RAND_R_SEED 0x1842 8328 #define regFMT0_FMT_DITHER_RAND_R_SEED_BASE_IDX 2 8329 #define regFMT0_FMT_DITHER_RAND_G_SEED 0x1843 8330 #define regFMT0_FMT_DITHER_RAND_G_SEED_BASE_IDX 2 8331 #define regFMT0_FMT_DITHER_RAND_B_SEED 0x1844 8332 #define regFMT0_FMT_DITHER_RAND_B_SEED_BASE_IDX 2 8333 #define regFMT0_FMT_CLAMP_CNTL 0x1845 8334 #define regFMT0_FMT_CLAMP_CNTL_BASE_IDX 2 8335 #define regFMT0_FMT_SIDE_BY_SIDE_STEREO_CONTROL 0x1846 8336 #define regFMT0_FMT_SIDE_BY_SIDE_STEREO_CONTROL_BASE_IDX 2 8337 #define regFMT0_FMT_MAP420_MEMORY_CONTROL 0x1847 8338 #define regFMT0_FMT_MAP420_MEMORY_CONTROL_BASE_IDX 2 8339 #define regFMT0_FMT_422_CONTROL 0x1849 8340 #define regFMT0_FMT_422_CONTROL_BASE_IDX 2 8341 8342 8343 // addressBlock: dce_dc_opp_oppbuf0_dispdec 8344 // base address: 0x0 8345 #define regOPPBUF0_OPPBUF_CONTROL 0x1884 8346 #define regOPPBUF0_OPPBUF_CONTROL_BASE_IDX 2 8347 #define regOPPBUF0_OPPBUF_3D_PARAMETERS_0 0x1885 8348 #define regOPPBUF0_OPPBUF_3D_PARAMETERS_0_BASE_IDX 2 8349 #define regOPPBUF0_OPPBUF_3D_PARAMETERS_1 0x1886 8350 #define regOPPBUF0_OPPBUF_3D_PARAMETERS_1_BASE_IDX 2 8351 #define regOPPBUF0_OPPBUF_CONTROL1 0x1889 8352 #define regOPPBUF0_OPPBUF_CONTROL1_BASE_IDX 2 8353 8354 8355 // addressBlock: dce_dc_opp_opp_pipe0_dispdec 8356 // base address: 0x0 8357 #define regOPP_PIPE0_OPP_PIPE_CONTROL 0x188c 8358 #define regOPP_PIPE0_OPP_PIPE_CONTROL_BASE_IDX 2 8359 8360 8361 // addressBlock: dce_dc_opp_opp_pipe_crc0_dispdec 8362 // base address: 0x0 8363 #define regOPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL 0x1891 8364 #define regOPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL_BASE_IDX 2 8365 #define regOPP_PIPE_CRC0_OPP_PIPE_CRC_MASK 0x1892 8366 #define regOPP_PIPE_CRC0_OPP_PIPE_CRC_MASK_BASE_IDX 2 8367 #define regOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT0 0x1893 8368 #define regOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT0_BASE_IDX 2 8369 #define regOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT1 0x1894 8370 #define regOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT1_BASE_IDX 2 8371 #define regOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT2 0x1895 8372 #define regOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT2_BASE_IDX 2 8373 8374 8375 // addressBlock: dce_dc_opp_dpg1_dispdec 8376 // base address: 0x168 8377 #define regDPG1_DPG_CONTROL 0x18ae 8378 #define regDPG1_DPG_CONTROL_BASE_IDX 2 8379 #define regDPG1_DPG_RAMP_CONTROL 0x18af 8380 #define regDPG1_DPG_RAMP_CONTROL_BASE_IDX 2 8381 #define regDPG1_DPG_DIMENSIONS 0x18b0 8382 #define regDPG1_DPG_DIMENSIONS_BASE_IDX 2 8383 #define regDPG1_DPG_COLOUR_R_CR 0x18b1 8384 #define regDPG1_DPG_COLOUR_R_CR_BASE_IDX 2 8385 #define regDPG1_DPG_COLOUR_G_Y 0x18b2 8386 #define regDPG1_DPG_COLOUR_G_Y_BASE_IDX 2 8387 #define regDPG1_DPG_COLOUR_B_CB 0x18b3 8388 #define regDPG1_DPG_COLOUR_B_CB_BASE_IDX 2 8389 #define regDPG1_DPG_OFFSET_SEGMENT 0x18b4 8390 #define regDPG1_DPG_OFFSET_SEGMENT_BASE_IDX 2 8391 #define regDPG1_DPG_STATUS 0x18b5 8392 #define regDPG1_DPG_STATUS_BASE_IDX 2 8393 8394 8395 // addressBlock: dce_dc_opp_fmt1_dispdec 8396 // base address: 0x168 8397 #define regFMT1_FMT_CLAMP_COMPONENT_R 0x1896 8398 #define regFMT1_FMT_CLAMP_COMPONENT_R_BASE_IDX 2 8399 #define regFMT1_FMT_CLAMP_COMPONENT_G 0x1897 8400 #define regFMT1_FMT_CLAMP_COMPONENT_G_BASE_IDX 2 8401 #define regFMT1_FMT_CLAMP_COMPONENT_B 0x1898 8402 #define regFMT1_FMT_CLAMP_COMPONENT_B_BASE_IDX 2 8403 #define regFMT1_FMT_DYNAMIC_EXP_CNTL 0x1899 8404 #define regFMT1_FMT_DYNAMIC_EXP_CNTL_BASE_IDX 2 8405 #define regFMT1_FMT_CONTROL 0x189a 8406 #define regFMT1_FMT_CONTROL_BASE_IDX 2 8407 #define regFMT1_FMT_BIT_DEPTH_CONTROL 0x189b 8408 #define regFMT1_FMT_BIT_DEPTH_CONTROL_BASE_IDX 2 8409 #define regFMT1_FMT_DITHER_RAND_R_SEED 0x189c 8410 #define regFMT1_FMT_DITHER_RAND_R_SEED_BASE_IDX 2 8411 #define regFMT1_FMT_DITHER_RAND_G_SEED 0x189d 8412 #define regFMT1_FMT_DITHER_RAND_G_SEED_BASE_IDX 2 8413 #define regFMT1_FMT_DITHER_RAND_B_SEED 0x189e 8414 #define regFMT1_FMT_DITHER_RAND_B_SEED_BASE_IDX 2 8415 #define regFMT1_FMT_CLAMP_CNTL 0x189f 8416 #define regFMT1_FMT_CLAMP_CNTL_BASE_IDX 2 8417 #define regFMT1_FMT_SIDE_BY_SIDE_STEREO_CONTROL 0x18a0 8418 #define regFMT1_FMT_SIDE_BY_SIDE_STEREO_CONTROL_BASE_IDX 2 8419 #define regFMT1_FMT_MAP420_MEMORY_CONTROL 0x18a1 8420 #define regFMT1_FMT_MAP420_MEMORY_CONTROL_BASE_IDX 2 8421 #define regFMT1_FMT_422_CONTROL 0x18a3 8422 #define regFMT1_FMT_422_CONTROL_BASE_IDX 2 8423 8424 8425 // addressBlock: dce_dc_opp_oppbuf1_dispdec 8426 // base address: 0x168 8427 #define regOPPBUF1_OPPBUF_CONTROL 0x18de 8428 #define regOPPBUF1_OPPBUF_CONTROL_BASE_IDX 2 8429 #define regOPPBUF1_OPPBUF_3D_PARAMETERS_0 0x18df 8430 #define regOPPBUF1_OPPBUF_3D_PARAMETERS_0_BASE_IDX 2 8431 #define regOPPBUF1_OPPBUF_3D_PARAMETERS_1 0x18e0 8432 #define regOPPBUF1_OPPBUF_3D_PARAMETERS_1_BASE_IDX 2 8433 #define regOPPBUF1_OPPBUF_CONTROL1 0x18e3 8434 #define regOPPBUF1_OPPBUF_CONTROL1_BASE_IDX 2 8435 8436 8437 // addressBlock: dce_dc_opp_opp_pipe1_dispdec 8438 // base address: 0x168 8439 #define regOPP_PIPE1_OPP_PIPE_CONTROL 0x18e6 8440 #define regOPP_PIPE1_OPP_PIPE_CONTROL_BASE_IDX 2 8441 8442 8443 // addressBlock: dce_dc_opp_opp_pipe_crc1_dispdec 8444 // base address: 0x168 8445 #define regOPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL 0x18eb 8446 #define regOPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL_BASE_IDX 2 8447 #define regOPP_PIPE_CRC1_OPP_PIPE_CRC_MASK 0x18ec 8448 #define regOPP_PIPE_CRC1_OPP_PIPE_CRC_MASK_BASE_IDX 2 8449 #define regOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT0 0x18ed 8450 #define regOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT0_BASE_IDX 2 8451 #define regOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT1 0x18ee 8452 #define regOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT1_BASE_IDX 2 8453 #define regOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT2 0x18ef 8454 #define regOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT2_BASE_IDX 2 8455 8456 8457 // addressBlock: dce_dc_opp_dpg2_dispdec 8458 // base address: 0x2d0 8459 #define regDPG2_DPG_CONTROL 0x1908 8460 #define regDPG2_DPG_CONTROL_BASE_IDX 2 8461 #define regDPG2_DPG_RAMP_CONTROL 0x1909 8462 #define regDPG2_DPG_RAMP_CONTROL_BASE_IDX 2 8463 #define regDPG2_DPG_DIMENSIONS 0x190a 8464 #define regDPG2_DPG_DIMENSIONS_BASE_IDX 2 8465 #define regDPG2_DPG_COLOUR_R_CR 0x190b 8466 #define regDPG2_DPG_COLOUR_R_CR_BASE_IDX 2 8467 #define regDPG2_DPG_COLOUR_G_Y 0x190c 8468 #define regDPG2_DPG_COLOUR_G_Y_BASE_IDX 2 8469 #define regDPG2_DPG_COLOUR_B_CB 0x190d 8470 #define regDPG2_DPG_COLOUR_B_CB_BASE_IDX 2 8471 #define regDPG2_DPG_OFFSET_SEGMENT 0x190e 8472 #define regDPG2_DPG_OFFSET_SEGMENT_BASE_IDX 2 8473 #define regDPG2_DPG_STATUS 0x190f 8474 #define regDPG2_DPG_STATUS_BASE_IDX 2 8475 8476 8477 // addressBlock: dce_dc_opp_fmt2_dispdec 8478 // base address: 0x2d0 8479 #define regFMT2_FMT_CLAMP_COMPONENT_R 0x18f0 8480 #define regFMT2_FMT_CLAMP_COMPONENT_R_BASE_IDX 2 8481 #define regFMT2_FMT_CLAMP_COMPONENT_G 0x18f1 8482 #define regFMT2_FMT_CLAMP_COMPONENT_G_BASE_IDX 2 8483 #define regFMT2_FMT_CLAMP_COMPONENT_B 0x18f2 8484 #define regFMT2_FMT_CLAMP_COMPONENT_B_BASE_IDX 2 8485 #define regFMT2_FMT_DYNAMIC_EXP_CNTL 0x18f3 8486 #define regFMT2_FMT_DYNAMIC_EXP_CNTL_BASE_IDX 2 8487 #define regFMT2_FMT_CONTROL 0x18f4 8488 #define regFMT2_FMT_CONTROL_BASE_IDX 2 8489 #define regFMT2_FMT_BIT_DEPTH_CONTROL 0x18f5 8490 #define regFMT2_FMT_BIT_DEPTH_CONTROL_BASE_IDX 2 8491 #define regFMT2_FMT_DITHER_RAND_R_SEED 0x18f6 8492 #define regFMT2_FMT_DITHER_RAND_R_SEED_BASE_IDX 2 8493 #define regFMT2_FMT_DITHER_RAND_G_SEED 0x18f7 8494 #define regFMT2_FMT_DITHER_RAND_G_SEED_BASE_IDX 2 8495 #define regFMT2_FMT_DITHER_RAND_B_SEED 0x18f8 8496 #define regFMT2_FMT_DITHER_RAND_B_SEED_BASE_IDX 2 8497 #define regFMT2_FMT_CLAMP_CNTL 0x18f9 8498 #define regFMT2_FMT_CLAMP_CNTL_BASE_IDX 2 8499 #define regFMT2_FMT_SIDE_BY_SIDE_STEREO_CONTROL 0x18fa 8500 #define regFMT2_FMT_SIDE_BY_SIDE_STEREO_CONTROL_BASE_IDX 2 8501 #define regFMT2_FMT_MAP420_MEMORY_CONTROL 0x18fb 8502 #define regFMT2_FMT_MAP420_MEMORY_CONTROL_BASE_IDX 2 8503 #define regFMT2_FMT_422_CONTROL 0x18fd 8504 #define regFMT2_FMT_422_CONTROL_BASE_IDX 2 8505 8506 8507 // addressBlock: dce_dc_opp_oppbuf2_dispdec 8508 // base address: 0x2d0 8509 #define regOPPBUF2_OPPBUF_CONTROL 0x1938 8510 #define regOPPBUF2_OPPBUF_CONTROL_BASE_IDX 2 8511 #define regOPPBUF2_OPPBUF_3D_PARAMETERS_0 0x1939 8512 #define regOPPBUF2_OPPBUF_3D_PARAMETERS_0_BASE_IDX 2 8513 #define regOPPBUF2_OPPBUF_3D_PARAMETERS_1 0x193a 8514 #define regOPPBUF2_OPPBUF_3D_PARAMETERS_1_BASE_IDX 2 8515 #define regOPPBUF2_OPPBUF_CONTROL1 0x193d 8516 #define regOPPBUF2_OPPBUF_CONTROL1_BASE_IDX 2 8517 8518 8519 // addressBlock: dce_dc_opp_opp_pipe2_dispdec 8520 // base address: 0x2d0 8521 #define regOPP_PIPE2_OPP_PIPE_CONTROL 0x1940 8522 #define regOPP_PIPE2_OPP_PIPE_CONTROL_BASE_IDX 2 8523 8524 8525 // addressBlock: dce_dc_opp_opp_pipe_crc2_dispdec 8526 // base address: 0x2d0 8527 #define regOPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL 0x1945 8528 #define regOPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL_BASE_IDX 2 8529 #define regOPP_PIPE_CRC2_OPP_PIPE_CRC_MASK 0x1946 8530 #define regOPP_PIPE_CRC2_OPP_PIPE_CRC_MASK_BASE_IDX 2 8531 #define regOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT0 0x1947 8532 #define regOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT0_BASE_IDX 2 8533 #define regOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT1 0x1948 8534 #define regOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT1_BASE_IDX 2 8535 #define regOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT2 0x1949 8536 #define regOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT2_BASE_IDX 2 8537 8538 8539 // addressBlock: dce_dc_opp_dpg3_dispdec 8540 // base address: 0x438 8541 #define regDPG3_DPG_CONTROL 0x1962 8542 #define regDPG3_DPG_CONTROL_BASE_IDX 2 8543 #define regDPG3_DPG_RAMP_CONTROL 0x1963 8544 #define regDPG3_DPG_RAMP_CONTROL_BASE_IDX 2 8545 #define regDPG3_DPG_DIMENSIONS 0x1964 8546 #define regDPG3_DPG_DIMENSIONS_BASE_IDX 2 8547 #define regDPG3_DPG_COLOUR_R_CR 0x1965 8548 #define regDPG3_DPG_COLOUR_R_CR_BASE_IDX 2 8549 #define regDPG3_DPG_COLOUR_G_Y 0x1966 8550 #define regDPG3_DPG_COLOUR_G_Y_BASE_IDX 2 8551 #define regDPG3_DPG_COLOUR_B_CB 0x1967 8552 #define regDPG3_DPG_COLOUR_B_CB_BASE_IDX 2 8553 #define regDPG3_DPG_OFFSET_SEGMENT 0x1968 8554 #define regDPG3_DPG_OFFSET_SEGMENT_BASE_IDX 2 8555 #define regDPG3_DPG_STATUS 0x1969 8556 #define regDPG3_DPG_STATUS_BASE_IDX 2 8557 8558 8559 // addressBlock: dce_dc_opp_fmt3_dispdec 8560 // base address: 0x438 8561 #define regFMT3_FMT_CLAMP_COMPONENT_R 0x194a 8562 #define regFMT3_FMT_CLAMP_COMPONENT_R_BASE_IDX 2 8563 #define regFMT3_FMT_CLAMP_COMPONENT_G 0x194b 8564 #define regFMT3_FMT_CLAMP_COMPONENT_G_BASE_IDX 2 8565 #define regFMT3_FMT_CLAMP_COMPONENT_B 0x194c 8566 #define regFMT3_FMT_CLAMP_COMPONENT_B_BASE_IDX 2 8567 #define regFMT3_FMT_DYNAMIC_EXP_CNTL 0x194d 8568 #define regFMT3_FMT_DYNAMIC_EXP_CNTL_BASE_IDX 2 8569 #define regFMT3_FMT_CONTROL 0x194e 8570 #define regFMT3_FMT_CONTROL_BASE_IDX 2 8571 #define regFMT3_FMT_BIT_DEPTH_CONTROL 0x194f 8572 #define regFMT3_FMT_BIT_DEPTH_CONTROL_BASE_IDX 2 8573 #define regFMT3_FMT_DITHER_RAND_R_SEED 0x1950 8574 #define regFMT3_FMT_DITHER_RAND_R_SEED_BASE_IDX 2 8575 #define regFMT3_FMT_DITHER_RAND_G_SEED 0x1951 8576 #define regFMT3_FMT_DITHER_RAND_G_SEED_BASE_IDX 2 8577 #define regFMT3_FMT_DITHER_RAND_B_SEED 0x1952 8578 #define regFMT3_FMT_DITHER_RAND_B_SEED_BASE_IDX 2 8579 #define regFMT3_FMT_CLAMP_CNTL 0x1953 8580 #define regFMT3_FMT_CLAMP_CNTL_BASE_IDX 2 8581 #define regFMT3_FMT_SIDE_BY_SIDE_STEREO_CONTROL 0x1954 8582 #define regFMT3_FMT_SIDE_BY_SIDE_STEREO_CONTROL_BASE_IDX 2 8583 #define regFMT3_FMT_MAP420_MEMORY_CONTROL 0x1955 8584 #define regFMT3_FMT_MAP420_MEMORY_CONTROL_BASE_IDX 2 8585 #define regFMT3_FMT_422_CONTROL 0x1957 8586 #define regFMT3_FMT_422_CONTROL_BASE_IDX 2 8587 8588 8589 // addressBlock: dce_dc_opp_oppbuf3_dispdec 8590 // base address: 0x438 8591 #define regOPPBUF3_OPPBUF_CONTROL 0x1992 8592 #define regOPPBUF3_OPPBUF_CONTROL_BASE_IDX 2 8593 #define regOPPBUF3_OPPBUF_3D_PARAMETERS_0 0x1993 8594 #define regOPPBUF3_OPPBUF_3D_PARAMETERS_0_BASE_IDX 2 8595 #define regOPPBUF3_OPPBUF_3D_PARAMETERS_1 0x1994 8596 #define regOPPBUF3_OPPBUF_3D_PARAMETERS_1_BASE_IDX 2 8597 #define regOPPBUF3_OPPBUF_CONTROL1 0x1997 8598 #define regOPPBUF3_OPPBUF_CONTROL1_BASE_IDX 2 8599 8600 8601 // addressBlock: dce_dc_opp_opp_pipe3_dispdec 8602 // base address: 0x438 8603 #define regOPP_PIPE3_OPP_PIPE_CONTROL 0x199a 8604 #define regOPP_PIPE3_OPP_PIPE_CONTROL_BASE_IDX 2 8605 8606 8607 // addressBlock: dce_dc_opp_opp_pipe_crc3_dispdec 8608 // base address: 0x438 8609 #define regOPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL 0x199f 8610 #define regOPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL_BASE_IDX 2 8611 #define regOPP_PIPE_CRC3_OPP_PIPE_CRC_MASK 0x19a0 8612 #define regOPP_PIPE_CRC3_OPP_PIPE_CRC_MASK_BASE_IDX 2 8613 #define regOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT0 0x19a1 8614 #define regOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT0_BASE_IDX 2 8615 #define regOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT1 0x19a2 8616 #define regOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT1_BASE_IDX 2 8617 #define regOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT2 0x19a3 8618 #define regOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT2_BASE_IDX 2 8619 8620 8621 // addressBlock: dce_dc_opp_dscrm0_dispdec 8622 // base address: 0x0 8623 #define regDSCRM0_DSCRM_DSC_FORWARD_CONFIG 0x1a64 8624 #define regDSCRM0_DSCRM_DSC_FORWARD_CONFIG_BASE_IDX 2 8625 8626 8627 // addressBlock: dce_dc_opp_dscrm1_dispdec 8628 // base address: 0x4 8629 #define regDSCRM1_DSCRM_DSC_FORWARD_CONFIG 0x1a65 8630 #define regDSCRM1_DSCRM_DSC_FORWARD_CONFIG_BASE_IDX 2 8631 8632 8633 // addressBlock: dce_dc_opp_dscrm2_dispdec 8634 // base address: 0x8 8635 #define regDSCRM2_DSCRM_DSC_FORWARD_CONFIG 0x1a66 8636 #define regDSCRM2_DSCRM_DSC_FORWARD_CONFIG_BASE_IDX 2 8637 8638 8639 // addressBlock: dce_dc_opp_opp_top_dispdec 8640 // base address: 0x0 8641 #define regOPP_TOP_CLK_CONTROL 0x1a5e 8642 #define regOPP_TOP_CLK_CONTROL_BASE_IDX 2 8643 #define regOPP_ABM_CONTROL 0x1a60 8644 #define regOPP_ABM_CONTROL_BASE_IDX 2 8645 8646 8647 // addressBlock: dce_dc_opp_opp_dcperfmon_dc_perfmon_dispdec 8648 // base address: 0x6af8 8649 #define regDC_PERFMON16_PERFCOUNTER_CNTL 0x1abe 8650 #define regDC_PERFMON16_PERFCOUNTER_CNTL_BASE_IDX 2 8651 #define regDC_PERFMON16_PERFCOUNTER_CNTL2 0x1abf 8652 #define regDC_PERFMON16_PERFCOUNTER_CNTL2_BASE_IDX 2 8653 #define regDC_PERFMON16_PERFCOUNTER_STATE 0x1ac0 8654 #define regDC_PERFMON16_PERFCOUNTER_STATE_BASE_IDX 2 8655 #define regDC_PERFMON16_PERFMON_CNTL 0x1ac1 8656 #define regDC_PERFMON16_PERFMON_CNTL_BASE_IDX 2 8657 #define regDC_PERFMON16_PERFMON_CNTL2 0x1ac2 8658 #define regDC_PERFMON16_PERFMON_CNTL2_BASE_IDX 2 8659 #define regDC_PERFMON16_PERFMON_CVALUE_INT_MISC 0x1ac3 8660 #define regDC_PERFMON16_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 8661 #define regDC_PERFMON16_PERFMON_CVALUE_LOW 0x1ac4 8662 #define regDC_PERFMON16_PERFMON_CVALUE_LOW_BASE_IDX 2 8663 #define regDC_PERFMON16_PERFMON_HI 0x1ac5 8664 #define regDC_PERFMON16_PERFMON_HI_BASE_IDX 2 8665 #define regDC_PERFMON16_PERFMON_LOW 0x1ac6 8666 #define regDC_PERFMON16_PERFMON_LOW_BASE_IDX 2 8667 8668 8669 // addressBlock: dce_dc_optc_odm0_dispdec 8670 // base address: 0x0 8671 #define regODM0_OPTC_INPUT_GLOBAL_CONTROL 0x1aca 8672 #define regODM0_OPTC_INPUT_GLOBAL_CONTROL_BASE_IDX 2 8673 #define regODM0_OPTC_DATA_SOURCE_SELECT 0x1acb 8674 #define regODM0_OPTC_DATA_SOURCE_SELECT_BASE_IDX 2 8675 #define regODM0_OPTC_DATA_FORMAT_CONTROL 0x1acc 8676 #define regODM0_OPTC_DATA_FORMAT_CONTROL_BASE_IDX 2 8677 #define regODM0_OPTC_BYTES_PER_PIXEL 0x1acd 8678 #define regODM0_OPTC_BYTES_PER_PIXEL_BASE_IDX 2 8679 #define regODM0_OPTC_WIDTH_CONTROL 0x1ace 8680 #define regODM0_OPTC_WIDTH_CONTROL_BASE_IDX 2 8681 #define regODM0_OPTC_INPUT_CLOCK_CONTROL 0x1acf 8682 #define regODM0_OPTC_INPUT_CLOCK_CONTROL_BASE_IDX 2 8683 #define regODM0_OPTC_MEMORY_CONFIG 0x1ad0 8684 #define regODM0_OPTC_MEMORY_CONFIG_BASE_IDX 2 8685 #define regODM0_OPTC_INPUT_SPARE_REGISTER 0x1ad1 8686 #define regODM0_OPTC_INPUT_SPARE_REGISTER_BASE_IDX 2 8687 8688 8689 // addressBlock: dce_dc_optc_odm1_dispdec 8690 // base address: 0x40 8691 #define regODM1_OPTC_INPUT_GLOBAL_CONTROL 0x1ada 8692 #define regODM1_OPTC_INPUT_GLOBAL_CONTROL_BASE_IDX 2 8693 #define regODM1_OPTC_DATA_SOURCE_SELECT 0x1adb 8694 #define regODM1_OPTC_DATA_SOURCE_SELECT_BASE_IDX 2 8695 #define regODM1_OPTC_DATA_FORMAT_CONTROL 0x1adc 8696 #define regODM1_OPTC_DATA_FORMAT_CONTROL_BASE_IDX 2 8697 #define regODM1_OPTC_BYTES_PER_PIXEL 0x1add 8698 #define regODM1_OPTC_BYTES_PER_PIXEL_BASE_IDX 2 8699 #define regODM1_OPTC_WIDTH_CONTROL 0x1ade 8700 #define regODM1_OPTC_WIDTH_CONTROL_BASE_IDX 2 8701 #define regODM1_OPTC_INPUT_CLOCK_CONTROL 0x1adf 8702 #define regODM1_OPTC_INPUT_CLOCK_CONTROL_BASE_IDX 2 8703 #define regODM1_OPTC_MEMORY_CONFIG 0x1ae0 8704 #define regODM1_OPTC_MEMORY_CONFIG_BASE_IDX 2 8705 #define regODM1_OPTC_INPUT_SPARE_REGISTER 0x1ae1 8706 #define regODM1_OPTC_INPUT_SPARE_REGISTER_BASE_IDX 2 8707 8708 8709 // addressBlock: dce_dc_optc_odm2_dispdec 8710 // base address: 0x80 8711 #define regODM2_OPTC_INPUT_GLOBAL_CONTROL 0x1aea 8712 #define regODM2_OPTC_INPUT_GLOBAL_CONTROL_BASE_IDX 2 8713 #define regODM2_OPTC_DATA_SOURCE_SELECT 0x1aeb 8714 #define regODM2_OPTC_DATA_SOURCE_SELECT_BASE_IDX 2 8715 #define regODM2_OPTC_DATA_FORMAT_CONTROL 0x1aec 8716 #define regODM2_OPTC_DATA_FORMAT_CONTROL_BASE_IDX 2 8717 #define regODM2_OPTC_BYTES_PER_PIXEL 0x1aed 8718 #define regODM2_OPTC_BYTES_PER_PIXEL_BASE_IDX 2 8719 #define regODM2_OPTC_WIDTH_CONTROL 0x1aee 8720 #define regODM2_OPTC_WIDTH_CONTROL_BASE_IDX 2 8721 #define regODM2_OPTC_INPUT_CLOCK_CONTROL 0x1aef 8722 #define regODM2_OPTC_INPUT_CLOCK_CONTROL_BASE_IDX 2 8723 #define regODM2_OPTC_MEMORY_CONFIG 0x1af0 8724 #define regODM2_OPTC_MEMORY_CONFIG_BASE_IDX 2 8725 #define regODM2_OPTC_INPUT_SPARE_REGISTER 0x1af1 8726 #define regODM2_OPTC_INPUT_SPARE_REGISTER_BASE_IDX 2 8727 8728 8729 // addressBlock: dce_dc_optc_odm3_dispdec 8730 // base address: 0xc0 8731 #define regODM3_OPTC_INPUT_GLOBAL_CONTROL 0x1afa 8732 #define regODM3_OPTC_INPUT_GLOBAL_CONTROL_BASE_IDX 2 8733 #define regODM3_OPTC_DATA_SOURCE_SELECT 0x1afb 8734 #define regODM3_OPTC_DATA_SOURCE_SELECT_BASE_IDX 2 8735 #define regODM3_OPTC_DATA_FORMAT_CONTROL 0x1afc 8736 #define regODM3_OPTC_DATA_FORMAT_CONTROL_BASE_IDX 2 8737 #define regODM3_OPTC_BYTES_PER_PIXEL 0x1afd 8738 #define regODM3_OPTC_BYTES_PER_PIXEL_BASE_IDX 2 8739 #define regODM3_OPTC_WIDTH_CONTROL 0x1afe 8740 #define regODM3_OPTC_WIDTH_CONTROL_BASE_IDX 2 8741 #define regODM3_OPTC_INPUT_CLOCK_CONTROL 0x1aff 8742 #define regODM3_OPTC_INPUT_CLOCK_CONTROL_BASE_IDX 2 8743 #define regODM3_OPTC_MEMORY_CONFIG 0x1b00 8744 #define regODM3_OPTC_MEMORY_CONFIG_BASE_IDX 2 8745 #define regODM3_OPTC_INPUT_SPARE_REGISTER 0x1b01 8746 #define regODM3_OPTC_INPUT_SPARE_REGISTER_BASE_IDX 2 8747 8748 8749 // addressBlock: dce_dc_optc_otg0_dispdec 8750 // base address: 0x0 8751 #define regOTG0_OTG_H_TOTAL 0x1b2a 8752 #define regOTG0_OTG_H_TOTAL_BASE_IDX 2 8753 #define regOTG0_OTG_H_BLANK_START_END 0x1b2b 8754 #define regOTG0_OTG_H_BLANK_START_END_BASE_IDX 2 8755 #define regOTG0_OTG_H_SYNC_A 0x1b2c 8756 #define regOTG0_OTG_H_SYNC_A_BASE_IDX 2 8757 #define regOTG0_OTG_H_SYNC_A_CNTL 0x1b2d 8758 #define regOTG0_OTG_H_SYNC_A_CNTL_BASE_IDX 2 8759 #define regOTG0_OTG_H_TIMING_CNTL 0x1b2e 8760 #define regOTG0_OTG_H_TIMING_CNTL_BASE_IDX 2 8761 #define regOTG0_OTG_V_TOTAL 0x1b2f 8762 #define regOTG0_OTG_V_TOTAL_BASE_IDX 2 8763 #define regOTG0_OTG_V_TOTAL_MIN 0x1b30 8764 #define regOTG0_OTG_V_TOTAL_MIN_BASE_IDX 2 8765 #define regOTG0_OTG_V_TOTAL_MAX 0x1b31 8766 #define regOTG0_OTG_V_TOTAL_MAX_BASE_IDX 2 8767 #define regOTG0_OTG_V_TOTAL_MID 0x1b32 8768 #define regOTG0_OTG_V_TOTAL_MID_BASE_IDX 2 8769 #define regOTG0_OTG_V_TOTAL_CONTROL 0x1b33 8770 #define regOTG0_OTG_V_TOTAL_CONTROL_BASE_IDX 2 8771 #define regOTG0_OTG_V_TOTAL_INT_STATUS 0x1b34 8772 #define regOTG0_OTG_V_TOTAL_INT_STATUS_BASE_IDX 2 8773 #define regOTG0_OTG_VSYNC_NOM_INT_STATUS 0x1b35 8774 #define regOTG0_OTG_VSYNC_NOM_INT_STATUS_BASE_IDX 2 8775 #define regOTG0_OTG_V_BLANK_START_END 0x1b36 8776 #define regOTG0_OTG_V_BLANK_START_END_BASE_IDX 2 8777 #define regOTG0_OTG_V_SYNC_A 0x1b37 8778 #define regOTG0_OTG_V_SYNC_A_BASE_IDX 2 8779 #define regOTG0_OTG_V_SYNC_A_CNTL 0x1b38 8780 #define regOTG0_OTG_V_SYNC_A_CNTL_BASE_IDX 2 8781 #define regOTG0_OTG_TRIGA_CNTL 0x1b39 8782 #define regOTG0_OTG_TRIGA_CNTL_BASE_IDX 2 8783 #define regOTG0_OTG_TRIGA_MANUAL_TRIG 0x1b3a 8784 #define regOTG0_OTG_TRIGA_MANUAL_TRIG_BASE_IDX 2 8785 #define regOTG0_OTG_TRIGB_CNTL 0x1b3b 8786 #define regOTG0_OTG_TRIGB_CNTL_BASE_IDX 2 8787 #define regOTG0_OTG_TRIGB_MANUAL_TRIG 0x1b3c 8788 #define regOTG0_OTG_TRIGB_MANUAL_TRIG_BASE_IDX 2 8789 #define regOTG0_OTG_FORCE_COUNT_NOW_CNTL 0x1b3d 8790 #define regOTG0_OTG_FORCE_COUNT_NOW_CNTL_BASE_IDX 2 8791 #define regOTG0_OTG_FLOW_CONTROL 0x1b3e 8792 #define regOTG0_OTG_FLOW_CONTROL_BASE_IDX 2 8793 #define regOTG0_OTG_STEREO_FORCE_NEXT_EYE 0x1b3f 8794 #define regOTG0_OTG_STEREO_FORCE_NEXT_EYE_BASE_IDX 2 8795 #define regOTG0_OTG_CONTROL 0x1b41 8796 #define regOTG0_OTG_CONTROL_BASE_IDX 2 8797 #define regOTG0_OTG_INTERLACE_CONTROL 0x1b44 8798 #define regOTG0_OTG_INTERLACE_CONTROL_BASE_IDX 2 8799 #define regOTG0_OTG_INTERLACE_STATUS 0x1b45 8800 #define regOTG0_OTG_INTERLACE_STATUS_BASE_IDX 2 8801 #define regOTG0_OTG_PIXEL_DATA_READBACK0 0x1b47 8802 #define regOTG0_OTG_PIXEL_DATA_READBACK0_BASE_IDX 2 8803 #define regOTG0_OTG_PIXEL_DATA_READBACK1 0x1b48 8804 #define regOTG0_OTG_PIXEL_DATA_READBACK1_BASE_IDX 2 8805 #define regOTG0_OTG_STATUS 0x1b49 8806 #define regOTG0_OTG_STATUS_BASE_IDX 2 8807 #define regOTG0_OTG_STATUS_POSITION 0x1b4a 8808 #define regOTG0_OTG_STATUS_POSITION_BASE_IDX 2 8809 #define regOTG0_OTG_NOM_VERT_POSITION 0x1b4b 8810 #define regOTG0_OTG_NOM_VERT_POSITION_BASE_IDX 2 8811 #define regOTG0_OTG_STATUS_FRAME_COUNT 0x1b4c 8812 #define regOTG0_OTG_STATUS_FRAME_COUNT_BASE_IDX 2 8813 #define regOTG0_OTG_STATUS_VF_COUNT 0x1b4d 8814 #define regOTG0_OTG_STATUS_VF_COUNT_BASE_IDX 2 8815 #define regOTG0_OTG_STATUS_HV_COUNT 0x1b4e 8816 #define regOTG0_OTG_STATUS_HV_COUNT_BASE_IDX 2 8817 #define regOTG0_OTG_COUNT_CONTROL 0x1b4f 8818 #define regOTG0_OTG_COUNT_CONTROL_BASE_IDX 2 8819 #define regOTG0_OTG_COUNT_RESET 0x1b50 8820 #define regOTG0_OTG_COUNT_RESET_BASE_IDX 2 8821 #define regOTG0_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE 0x1b51 8822 #define regOTG0_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX 2 8823 #define regOTG0_OTG_VERT_SYNC_CONTROL 0x1b52 8824 #define regOTG0_OTG_VERT_SYNC_CONTROL_BASE_IDX 2 8825 #define regOTG0_OTG_STEREO_STATUS 0x1b53 8826 #define regOTG0_OTG_STEREO_STATUS_BASE_IDX 2 8827 #define regOTG0_OTG_STEREO_CONTROL 0x1b54 8828 #define regOTG0_OTG_STEREO_CONTROL_BASE_IDX 2 8829 #define regOTG0_OTG_SNAPSHOT_STATUS 0x1b55 8830 #define regOTG0_OTG_SNAPSHOT_STATUS_BASE_IDX 2 8831 #define regOTG0_OTG_SNAPSHOT_CONTROL 0x1b56 8832 #define regOTG0_OTG_SNAPSHOT_CONTROL_BASE_IDX 2 8833 #define regOTG0_OTG_SNAPSHOT_POSITION 0x1b57 8834 #define regOTG0_OTG_SNAPSHOT_POSITION_BASE_IDX 2 8835 #define regOTG0_OTG_SNAPSHOT_FRAME 0x1b58 8836 #define regOTG0_OTG_SNAPSHOT_FRAME_BASE_IDX 2 8837 #define regOTG0_OTG_INTERRUPT_CONTROL 0x1b59 8838 #define regOTG0_OTG_INTERRUPT_CONTROL_BASE_IDX 2 8839 #define regOTG0_OTG_UPDATE_LOCK 0x1b5a 8840 #define regOTG0_OTG_UPDATE_LOCK_BASE_IDX 2 8841 #define regOTG0_OTG_DOUBLE_BUFFER_CONTROL 0x1b5b 8842 #define regOTG0_OTG_DOUBLE_BUFFER_CONTROL_BASE_IDX 2 8843 #define regOTG0_OTG_MASTER_EN 0x1b5c 8844 #define regOTG0_OTG_MASTER_EN_BASE_IDX 2 8845 #define regOTG0_OTG_VERTICAL_INTERRUPT0_POSITION 0x1b62 8846 #define regOTG0_OTG_VERTICAL_INTERRUPT0_POSITION_BASE_IDX 2 8847 #define regOTG0_OTG_VERTICAL_INTERRUPT0_CONTROL 0x1b63 8848 #define regOTG0_OTG_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX 2 8849 #define regOTG0_OTG_VERTICAL_INTERRUPT1_POSITION 0x1b64 8850 #define regOTG0_OTG_VERTICAL_INTERRUPT1_POSITION_BASE_IDX 2 8851 #define regOTG0_OTG_VERTICAL_INTERRUPT1_CONTROL 0x1b65 8852 #define regOTG0_OTG_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX 2 8853 #define regOTG0_OTG_VERTICAL_INTERRUPT2_POSITION 0x1b66 8854 #define regOTG0_OTG_VERTICAL_INTERRUPT2_POSITION_BASE_IDX 2 8855 #define regOTG0_OTG_VERTICAL_INTERRUPT2_CONTROL 0x1b67 8856 #define regOTG0_OTG_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX 2 8857 #define regOTG0_OTG_CRC_CNTL 0x1b68 8858 #define regOTG0_OTG_CRC_CNTL_BASE_IDX 2 8859 #define regOTG0_OTG_CRC_CNTL2 0x1b69 8860 #define regOTG0_OTG_CRC_CNTL2_BASE_IDX 2 8861 #define regOTG0_OTG_CRC0_WINDOWA_X_CONTROL 0x1b6a 8862 #define regOTG0_OTG_CRC0_WINDOWA_X_CONTROL_BASE_IDX 2 8863 #define regOTG0_OTG_CRC0_WINDOWA_Y_CONTROL 0x1b6b 8864 #define regOTG0_OTG_CRC0_WINDOWA_Y_CONTROL_BASE_IDX 2 8865 #define regOTG0_OTG_CRC0_WINDOWB_X_CONTROL 0x1b6c 8866 #define regOTG0_OTG_CRC0_WINDOWB_X_CONTROL_BASE_IDX 2 8867 #define regOTG0_OTG_CRC0_WINDOWB_Y_CONTROL 0x1b6d 8868 #define regOTG0_OTG_CRC0_WINDOWB_Y_CONTROL_BASE_IDX 2 8869 #define regOTG0_OTG_CRC0_DATA_RG 0x1b6e 8870 #define regOTG0_OTG_CRC0_DATA_RG_BASE_IDX 2 8871 #define regOTG0_OTG_CRC0_DATA_B 0x1b6f 8872 #define regOTG0_OTG_CRC0_DATA_B_BASE_IDX 2 8873 #define regOTG0_OTG_CRC1_WINDOWA_X_CONTROL 0x1b70 8874 #define regOTG0_OTG_CRC1_WINDOWA_X_CONTROL_BASE_IDX 2 8875 #define regOTG0_OTG_CRC1_WINDOWA_Y_CONTROL 0x1b71 8876 #define regOTG0_OTG_CRC1_WINDOWA_Y_CONTROL_BASE_IDX 2 8877 #define regOTG0_OTG_CRC1_WINDOWB_X_CONTROL 0x1b72 8878 #define regOTG0_OTG_CRC1_WINDOWB_X_CONTROL_BASE_IDX 2 8879 #define regOTG0_OTG_CRC1_WINDOWB_Y_CONTROL 0x1b73 8880 #define regOTG0_OTG_CRC1_WINDOWB_Y_CONTROL_BASE_IDX 2 8881 #define regOTG0_OTG_CRC1_DATA_RG 0x1b74 8882 #define regOTG0_OTG_CRC1_DATA_RG_BASE_IDX 2 8883 #define regOTG0_OTG_CRC1_DATA_B 0x1b75 8884 #define regOTG0_OTG_CRC1_DATA_B_BASE_IDX 2 8885 #define regOTG0_OTG_CRC2_DATA_RG 0x1b76 8886 #define regOTG0_OTG_CRC2_DATA_RG_BASE_IDX 2 8887 #define regOTG0_OTG_CRC2_DATA_B 0x1b77 8888 #define regOTG0_OTG_CRC2_DATA_B_BASE_IDX 2 8889 #define regOTG0_OTG_CRC3_DATA_RG 0x1b78 8890 #define regOTG0_OTG_CRC3_DATA_RG_BASE_IDX 2 8891 #define regOTG0_OTG_CRC3_DATA_B 0x1b79 8892 #define regOTG0_OTG_CRC3_DATA_B_BASE_IDX 2 8893 #define regOTG0_OTG_CRC_SIG_RED_GREEN_MASK 0x1b7a 8894 #define regOTG0_OTG_CRC_SIG_RED_GREEN_MASK_BASE_IDX 2 8895 #define regOTG0_OTG_CRC_SIG_BLUE_CONTROL_MASK 0x1b7b 8896 #define regOTG0_OTG_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX 2 8897 #define regOTG0_OTG_STATIC_SCREEN_CONTROL 0x1b82 8898 #define regOTG0_OTG_STATIC_SCREEN_CONTROL_BASE_IDX 2 8899 #define regOTG0_OTG_3D_STRUCTURE_CONTROL 0x1b83 8900 #define regOTG0_OTG_3D_STRUCTURE_CONTROL_BASE_IDX 2 8901 #define regOTG0_OTG_GSL_VSYNC_GAP 0x1b84 8902 #define regOTG0_OTG_GSL_VSYNC_GAP_BASE_IDX 2 8903 #define regOTG0_OTG_MASTER_UPDATE_MODE 0x1b85 8904 #define regOTG0_OTG_MASTER_UPDATE_MODE_BASE_IDX 2 8905 #define regOTG0_OTG_CLOCK_CONTROL 0x1b86 8906 #define regOTG0_OTG_CLOCK_CONTROL_BASE_IDX 2 8907 #define regOTG0_OTG_VSTARTUP_PARAM 0x1b87 8908 #define regOTG0_OTG_VSTARTUP_PARAM_BASE_IDX 2 8909 #define regOTG0_OTG_VUPDATE_PARAM 0x1b88 8910 #define regOTG0_OTG_VUPDATE_PARAM_BASE_IDX 2 8911 #define regOTG0_OTG_VREADY_PARAM 0x1b89 8912 #define regOTG0_OTG_VREADY_PARAM_BASE_IDX 2 8913 #define regOTG0_OTG_GLOBAL_SYNC_STATUS 0x1b8a 8914 #define regOTG0_OTG_GLOBAL_SYNC_STATUS_BASE_IDX 2 8915 #define regOTG0_OTG_MASTER_UPDATE_LOCK 0x1b8b 8916 #define regOTG0_OTG_MASTER_UPDATE_LOCK_BASE_IDX 2 8917 #define regOTG0_OTG_GSL_CONTROL 0x1b8c 8918 #define regOTG0_OTG_GSL_CONTROL_BASE_IDX 2 8919 #define regOTG0_OTG_GSL_WINDOW_X 0x1b8d 8920 #define regOTG0_OTG_GSL_WINDOW_X_BASE_IDX 2 8921 #define regOTG0_OTG_GSL_WINDOW_Y 0x1b8e 8922 #define regOTG0_OTG_GSL_WINDOW_Y_BASE_IDX 2 8923 #define regOTG0_OTG_VUPDATE_KEEPOUT 0x1b8f 8924 #define regOTG0_OTG_VUPDATE_KEEPOUT_BASE_IDX 2 8925 #define regOTG0_OTG_GLOBAL_CONTROL0 0x1b90 8926 #define regOTG0_OTG_GLOBAL_CONTROL0_BASE_IDX 2 8927 #define regOTG0_OTG_GLOBAL_CONTROL1 0x1b91 8928 #define regOTG0_OTG_GLOBAL_CONTROL1_BASE_IDX 2 8929 #define regOTG0_OTG_GLOBAL_CONTROL2 0x1b92 8930 #define regOTG0_OTG_GLOBAL_CONTROL2_BASE_IDX 2 8931 #define regOTG0_OTG_GLOBAL_CONTROL3 0x1b93 8932 #define regOTG0_OTG_GLOBAL_CONTROL3_BASE_IDX 2 8933 #define regOTG0_OTG_GLOBAL_CONTROL4 0x1b94 8934 #define regOTG0_OTG_GLOBAL_CONTROL4_BASE_IDX 2 8935 #define regOTG0_OTG_TRIG_MANUAL_CONTROL 0x1b95 8936 #define regOTG0_OTG_TRIG_MANUAL_CONTROL_BASE_IDX 2 8937 #define regOTG0_OTG_MANUAL_FLOW_CONTROL 0x1b96 8938 #define regOTG0_OTG_MANUAL_FLOW_CONTROL_BASE_IDX 2 8939 #define regOTG0_OTG_DRR_TIMING_INT_STATUS 0x1b97 8940 #define regOTG0_OTG_DRR_TIMING_INT_STATUS_BASE_IDX 2 8941 #define regOTG0_OTG_DRR_V_TOTAL_REACH_RANGE 0x1b98 8942 #define regOTG0_OTG_DRR_V_TOTAL_REACH_RANGE_BASE_IDX 2 8943 #define regOTG0_OTG_DRR_V_TOTAL_CHANGE 0x1b99 8944 #define regOTG0_OTG_DRR_V_TOTAL_CHANGE_BASE_IDX 2 8945 #define regOTG0_OTG_DRR_TRIGGER_WINDOW 0x1b9a 8946 #define regOTG0_OTG_DRR_TRIGGER_WINDOW_BASE_IDX 2 8947 #define regOTG0_OTG_DRR_CONTROL 0x1b9b 8948 #define regOTG0_OTG_DRR_CONTROL_BASE_IDX 2 8949 #define regOTG0_OTG_M_CONST_DTO0 0x1b9c 8950 #define regOTG0_OTG_M_CONST_DTO0_BASE_IDX 2 8951 #define regOTG0_OTG_M_CONST_DTO1 0x1b9d 8952 #define regOTG0_OTG_M_CONST_DTO1_BASE_IDX 2 8953 #define regOTG0_OTG_REQUEST_CONTROL 0x1b9e 8954 #define regOTG0_OTG_REQUEST_CONTROL_BASE_IDX 2 8955 #define regOTG0_OTG_DSC_START_POSITION 0x1b9f 8956 #define regOTG0_OTG_DSC_START_POSITION_BASE_IDX 2 8957 #define regOTG0_OTG_PIPE_UPDATE_STATUS 0x1ba0 8958 #define regOTG0_OTG_PIPE_UPDATE_STATUS_BASE_IDX 2 8959 #define regOTG0_OTG_SPARE_REGISTER 0x1ba2 8960 #define regOTG0_OTG_SPARE_REGISTER_BASE_IDX 2 8961 8962 8963 // addressBlock: dce_dc_optc_otg1_dispdec 8964 // base address: 0x200 8965 #define regOTG1_OTG_H_TOTAL 0x1baa 8966 #define regOTG1_OTG_H_TOTAL_BASE_IDX 2 8967 #define regOTG1_OTG_H_BLANK_START_END 0x1bab 8968 #define regOTG1_OTG_H_BLANK_START_END_BASE_IDX 2 8969 #define regOTG1_OTG_H_SYNC_A 0x1bac 8970 #define regOTG1_OTG_H_SYNC_A_BASE_IDX 2 8971 #define regOTG1_OTG_H_SYNC_A_CNTL 0x1bad 8972 #define regOTG1_OTG_H_SYNC_A_CNTL_BASE_IDX 2 8973 #define regOTG1_OTG_H_TIMING_CNTL 0x1bae 8974 #define regOTG1_OTG_H_TIMING_CNTL_BASE_IDX 2 8975 #define regOTG1_OTG_V_TOTAL 0x1baf 8976 #define regOTG1_OTG_V_TOTAL_BASE_IDX 2 8977 #define regOTG1_OTG_V_TOTAL_MIN 0x1bb0 8978 #define regOTG1_OTG_V_TOTAL_MIN_BASE_IDX 2 8979 #define regOTG1_OTG_V_TOTAL_MAX 0x1bb1 8980 #define regOTG1_OTG_V_TOTAL_MAX_BASE_IDX 2 8981 #define regOTG1_OTG_V_TOTAL_MID 0x1bb2 8982 #define regOTG1_OTG_V_TOTAL_MID_BASE_IDX 2 8983 #define regOTG1_OTG_V_TOTAL_CONTROL 0x1bb3 8984 #define regOTG1_OTG_V_TOTAL_CONTROL_BASE_IDX 2 8985 #define regOTG1_OTG_V_TOTAL_INT_STATUS 0x1bb4 8986 #define regOTG1_OTG_V_TOTAL_INT_STATUS_BASE_IDX 2 8987 #define regOTG1_OTG_VSYNC_NOM_INT_STATUS 0x1bb5 8988 #define regOTG1_OTG_VSYNC_NOM_INT_STATUS_BASE_IDX 2 8989 #define regOTG1_OTG_V_BLANK_START_END 0x1bb6 8990 #define regOTG1_OTG_V_BLANK_START_END_BASE_IDX 2 8991 #define regOTG1_OTG_V_SYNC_A 0x1bb7 8992 #define regOTG1_OTG_V_SYNC_A_BASE_IDX 2 8993 #define regOTG1_OTG_V_SYNC_A_CNTL 0x1bb8 8994 #define regOTG1_OTG_V_SYNC_A_CNTL_BASE_IDX 2 8995 #define regOTG1_OTG_TRIGA_CNTL 0x1bb9 8996 #define regOTG1_OTG_TRIGA_CNTL_BASE_IDX 2 8997 #define regOTG1_OTG_TRIGA_MANUAL_TRIG 0x1bba 8998 #define regOTG1_OTG_TRIGA_MANUAL_TRIG_BASE_IDX 2 8999 #define regOTG1_OTG_TRIGB_CNTL 0x1bbb 9000 #define regOTG1_OTG_TRIGB_CNTL_BASE_IDX 2 9001 #define regOTG1_OTG_TRIGB_MANUAL_TRIG 0x1bbc 9002 #define regOTG1_OTG_TRIGB_MANUAL_TRIG_BASE_IDX 2 9003 #define regOTG1_OTG_FORCE_COUNT_NOW_CNTL 0x1bbd 9004 #define regOTG1_OTG_FORCE_COUNT_NOW_CNTL_BASE_IDX 2 9005 #define regOTG1_OTG_FLOW_CONTROL 0x1bbe 9006 #define regOTG1_OTG_FLOW_CONTROL_BASE_IDX 2 9007 #define regOTG1_OTG_STEREO_FORCE_NEXT_EYE 0x1bbf 9008 #define regOTG1_OTG_STEREO_FORCE_NEXT_EYE_BASE_IDX 2 9009 #define regOTG1_OTG_CONTROL 0x1bc1 9010 #define regOTG1_OTG_CONTROL_BASE_IDX 2 9011 #define regOTG1_OTG_INTERLACE_CONTROL 0x1bc4 9012 #define regOTG1_OTG_INTERLACE_CONTROL_BASE_IDX 2 9013 #define regOTG1_OTG_INTERLACE_STATUS 0x1bc5 9014 #define regOTG1_OTG_INTERLACE_STATUS_BASE_IDX 2 9015 #define regOTG1_OTG_PIXEL_DATA_READBACK0 0x1bc7 9016 #define regOTG1_OTG_PIXEL_DATA_READBACK0_BASE_IDX 2 9017 #define regOTG1_OTG_PIXEL_DATA_READBACK1 0x1bc8 9018 #define regOTG1_OTG_PIXEL_DATA_READBACK1_BASE_IDX 2 9019 #define regOTG1_OTG_STATUS 0x1bc9 9020 #define regOTG1_OTG_STATUS_BASE_IDX 2 9021 #define regOTG1_OTG_STATUS_POSITION 0x1bca 9022 #define regOTG1_OTG_STATUS_POSITION_BASE_IDX 2 9023 #define regOTG1_OTG_NOM_VERT_POSITION 0x1bcb 9024 #define regOTG1_OTG_NOM_VERT_POSITION_BASE_IDX 2 9025 #define regOTG1_OTG_STATUS_FRAME_COUNT 0x1bcc 9026 #define regOTG1_OTG_STATUS_FRAME_COUNT_BASE_IDX 2 9027 #define regOTG1_OTG_STATUS_VF_COUNT 0x1bcd 9028 #define regOTG1_OTG_STATUS_VF_COUNT_BASE_IDX 2 9029 #define regOTG1_OTG_STATUS_HV_COUNT 0x1bce 9030 #define regOTG1_OTG_STATUS_HV_COUNT_BASE_IDX 2 9031 #define regOTG1_OTG_COUNT_CONTROL 0x1bcf 9032 #define regOTG1_OTG_COUNT_CONTROL_BASE_IDX 2 9033 #define regOTG1_OTG_COUNT_RESET 0x1bd0 9034 #define regOTG1_OTG_COUNT_RESET_BASE_IDX 2 9035 #define regOTG1_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE 0x1bd1 9036 #define regOTG1_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX 2 9037 #define regOTG1_OTG_VERT_SYNC_CONTROL 0x1bd2 9038 #define regOTG1_OTG_VERT_SYNC_CONTROL_BASE_IDX 2 9039 #define regOTG1_OTG_STEREO_STATUS 0x1bd3 9040 #define regOTG1_OTG_STEREO_STATUS_BASE_IDX 2 9041 #define regOTG1_OTG_STEREO_CONTROL 0x1bd4 9042 #define regOTG1_OTG_STEREO_CONTROL_BASE_IDX 2 9043 #define regOTG1_OTG_SNAPSHOT_STATUS 0x1bd5 9044 #define regOTG1_OTG_SNAPSHOT_STATUS_BASE_IDX 2 9045 #define regOTG1_OTG_SNAPSHOT_CONTROL 0x1bd6 9046 #define regOTG1_OTG_SNAPSHOT_CONTROL_BASE_IDX 2 9047 #define regOTG1_OTG_SNAPSHOT_POSITION 0x1bd7 9048 #define regOTG1_OTG_SNAPSHOT_POSITION_BASE_IDX 2 9049 #define regOTG1_OTG_SNAPSHOT_FRAME 0x1bd8 9050 #define regOTG1_OTG_SNAPSHOT_FRAME_BASE_IDX 2 9051 #define regOTG1_OTG_INTERRUPT_CONTROL 0x1bd9 9052 #define regOTG1_OTG_INTERRUPT_CONTROL_BASE_IDX 2 9053 #define regOTG1_OTG_UPDATE_LOCK 0x1bda 9054 #define regOTG1_OTG_UPDATE_LOCK_BASE_IDX 2 9055 #define regOTG1_OTG_DOUBLE_BUFFER_CONTROL 0x1bdb 9056 #define regOTG1_OTG_DOUBLE_BUFFER_CONTROL_BASE_IDX 2 9057 #define regOTG1_OTG_MASTER_EN 0x1bdc 9058 #define regOTG1_OTG_MASTER_EN_BASE_IDX 2 9059 #define regOTG1_OTG_VERTICAL_INTERRUPT0_POSITION 0x1be2 9060 #define regOTG1_OTG_VERTICAL_INTERRUPT0_POSITION_BASE_IDX 2 9061 #define regOTG1_OTG_VERTICAL_INTERRUPT0_CONTROL 0x1be3 9062 #define regOTG1_OTG_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX 2 9063 #define regOTG1_OTG_VERTICAL_INTERRUPT1_POSITION 0x1be4 9064 #define regOTG1_OTG_VERTICAL_INTERRUPT1_POSITION_BASE_IDX 2 9065 #define regOTG1_OTG_VERTICAL_INTERRUPT1_CONTROL 0x1be5 9066 #define regOTG1_OTG_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX 2 9067 #define regOTG1_OTG_VERTICAL_INTERRUPT2_POSITION 0x1be6 9068 #define regOTG1_OTG_VERTICAL_INTERRUPT2_POSITION_BASE_IDX 2 9069 #define regOTG1_OTG_VERTICAL_INTERRUPT2_CONTROL 0x1be7 9070 #define regOTG1_OTG_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX 2 9071 #define regOTG1_OTG_CRC_CNTL 0x1be8 9072 #define regOTG1_OTG_CRC_CNTL_BASE_IDX 2 9073 #define regOTG1_OTG_CRC_CNTL2 0x1be9 9074 #define regOTG1_OTG_CRC_CNTL2_BASE_IDX 2 9075 #define regOTG1_OTG_CRC0_WINDOWA_X_CONTROL 0x1bea 9076 #define regOTG1_OTG_CRC0_WINDOWA_X_CONTROL_BASE_IDX 2 9077 #define regOTG1_OTG_CRC0_WINDOWA_Y_CONTROL 0x1beb 9078 #define regOTG1_OTG_CRC0_WINDOWA_Y_CONTROL_BASE_IDX 2 9079 #define regOTG1_OTG_CRC0_WINDOWB_X_CONTROL 0x1bec 9080 #define regOTG1_OTG_CRC0_WINDOWB_X_CONTROL_BASE_IDX 2 9081 #define regOTG1_OTG_CRC0_WINDOWB_Y_CONTROL 0x1bed 9082 #define regOTG1_OTG_CRC0_WINDOWB_Y_CONTROL_BASE_IDX 2 9083 #define regOTG1_OTG_CRC0_DATA_RG 0x1bee 9084 #define regOTG1_OTG_CRC0_DATA_RG_BASE_IDX 2 9085 #define regOTG1_OTG_CRC0_DATA_B 0x1bef 9086 #define regOTG1_OTG_CRC0_DATA_B_BASE_IDX 2 9087 #define regOTG1_OTG_CRC1_WINDOWA_X_CONTROL 0x1bf0 9088 #define regOTG1_OTG_CRC1_WINDOWA_X_CONTROL_BASE_IDX 2 9089 #define regOTG1_OTG_CRC1_WINDOWA_Y_CONTROL 0x1bf1 9090 #define regOTG1_OTG_CRC1_WINDOWA_Y_CONTROL_BASE_IDX 2 9091 #define regOTG1_OTG_CRC1_WINDOWB_X_CONTROL 0x1bf2 9092 #define regOTG1_OTG_CRC1_WINDOWB_X_CONTROL_BASE_IDX 2 9093 #define regOTG1_OTG_CRC1_WINDOWB_Y_CONTROL 0x1bf3 9094 #define regOTG1_OTG_CRC1_WINDOWB_Y_CONTROL_BASE_IDX 2 9095 #define regOTG1_OTG_CRC1_DATA_RG 0x1bf4 9096 #define regOTG1_OTG_CRC1_DATA_RG_BASE_IDX 2 9097 #define regOTG1_OTG_CRC1_DATA_B 0x1bf5 9098 #define regOTG1_OTG_CRC1_DATA_B_BASE_IDX 2 9099 #define regOTG1_OTG_CRC2_DATA_RG 0x1bf6 9100 #define regOTG1_OTG_CRC2_DATA_RG_BASE_IDX 2 9101 #define regOTG1_OTG_CRC2_DATA_B 0x1bf7 9102 #define regOTG1_OTG_CRC2_DATA_B_BASE_IDX 2 9103 #define regOTG1_OTG_CRC3_DATA_RG 0x1bf8 9104 #define regOTG1_OTG_CRC3_DATA_RG_BASE_IDX 2 9105 #define regOTG1_OTG_CRC3_DATA_B 0x1bf9 9106 #define regOTG1_OTG_CRC3_DATA_B_BASE_IDX 2 9107 #define regOTG1_OTG_CRC_SIG_RED_GREEN_MASK 0x1bfa 9108 #define regOTG1_OTG_CRC_SIG_RED_GREEN_MASK_BASE_IDX 2 9109 #define regOTG1_OTG_CRC_SIG_BLUE_CONTROL_MASK 0x1bfb 9110 #define regOTG1_OTG_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX 2 9111 #define regOTG1_OTG_STATIC_SCREEN_CONTROL 0x1c02 9112 #define regOTG1_OTG_STATIC_SCREEN_CONTROL_BASE_IDX 2 9113 #define regOTG1_OTG_3D_STRUCTURE_CONTROL 0x1c03 9114 #define regOTG1_OTG_3D_STRUCTURE_CONTROL_BASE_IDX 2 9115 #define regOTG1_OTG_GSL_VSYNC_GAP 0x1c04 9116 #define regOTG1_OTG_GSL_VSYNC_GAP_BASE_IDX 2 9117 #define regOTG1_OTG_MASTER_UPDATE_MODE 0x1c05 9118 #define regOTG1_OTG_MASTER_UPDATE_MODE_BASE_IDX 2 9119 #define regOTG1_OTG_CLOCK_CONTROL 0x1c06 9120 #define regOTG1_OTG_CLOCK_CONTROL_BASE_IDX 2 9121 #define regOTG1_OTG_VSTARTUP_PARAM 0x1c07 9122 #define regOTG1_OTG_VSTARTUP_PARAM_BASE_IDX 2 9123 #define regOTG1_OTG_VUPDATE_PARAM 0x1c08 9124 #define regOTG1_OTG_VUPDATE_PARAM_BASE_IDX 2 9125 #define regOTG1_OTG_VREADY_PARAM 0x1c09 9126 #define regOTG1_OTG_VREADY_PARAM_BASE_IDX 2 9127 #define regOTG1_OTG_GLOBAL_SYNC_STATUS 0x1c0a 9128 #define regOTG1_OTG_GLOBAL_SYNC_STATUS_BASE_IDX 2 9129 #define regOTG1_OTG_MASTER_UPDATE_LOCK 0x1c0b 9130 #define regOTG1_OTG_MASTER_UPDATE_LOCK_BASE_IDX 2 9131 #define regOTG1_OTG_GSL_CONTROL 0x1c0c 9132 #define regOTG1_OTG_GSL_CONTROL_BASE_IDX 2 9133 #define regOTG1_OTG_GSL_WINDOW_X 0x1c0d 9134 #define regOTG1_OTG_GSL_WINDOW_X_BASE_IDX 2 9135 #define regOTG1_OTG_GSL_WINDOW_Y 0x1c0e 9136 #define regOTG1_OTG_GSL_WINDOW_Y_BASE_IDX 2 9137 #define regOTG1_OTG_VUPDATE_KEEPOUT 0x1c0f 9138 #define regOTG1_OTG_VUPDATE_KEEPOUT_BASE_IDX 2 9139 #define regOTG1_OTG_GLOBAL_CONTROL0 0x1c10 9140 #define regOTG1_OTG_GLOBAL_CONTROL0_BASE_IDX 2 9141 #define regOTG1_OTG_GLOBAL_CONTROL1 0x1c11 9142 #define regOTG1_OTG_GLOBAL_CONTROL1_BASE_IDX 2 9143 #define regOTG1_OTG_GLOBAL_CONTROL2 0x1c12 9144 #define regOTG1_OTG_GLOBAL_CONTROL2_BASE_IDX 2 9145 #define regOTG1_OTG_GLOBAL_CONTROL3 0x1c13 9146 #define regOTG1_OTG_GLOBAL_CONTROL3_BASE_IDX 2 9147 #define regOTG1_OTG_GLOBAL_CONTROL4 0x1c14 9148 #define regOTG1_OTG_GLOBAL_CONTROL4_BASE_IDX 2 9149 #define regOTG1_OTG_TRIG_MANUAL_CONTROL 0x1c15 9150 #define regOTG1_OTG_TRIG_MANUAL_CONTROL_BASE_IDX 2 9151 #define regOTG1_OTG_MANUAL_FLOW_CONTROL 0x1c16 9152 #define regOTG1_OTG_MANUAL_FLOW_CONTROL_BASE_IDX 2 9153 #define regOTG1_OTG_DRR_TIMING_INT_STATUS 0x1c17 9154 #define regOTG1_OTG_DRR_TIMING_INT_STATUS_BASE_IDX 2 9155 #define regOTG1_OTG_DRR_V_TOTAL_REACH_RANGE 0x1c18 9156 #define regOTG1_OTG_DRR_V_TOTAL_REACH_RANGE_BASE_IDX 2 9157 #define regOTG1_OTG_DRR_V_TOTAL_CHANGE 0x1c19 9158 #define regOTG1_OTG_DRR_V_TOTAL_CHANGE_BASE_IDX 2 9159 #define regOTG1_OTG_DRR_TRIGGER_WINDOW 0x1c1a 9160 #define regOTG1_OTG_DRR_TRIGGER_WINDOW_BASE_IDX 2 9161 #define regOTG1_OTG_DRR_CONTROL 0x1c1b 9162 #define regOTG1_OTG_DRR_CONTROL_BASE_IDX 2 9163 #define regOTG1_OTG_M_CONST_DTO0 0x1c1c 9164 #define regOTG1_OTG_M_CONST_DTO0_BASE_IDX 2 9165 #define regOTG1_OTG_M_CONST_DTO1 0x1c1d 9166 #define regOTG1_OTG_M_CONST_DTO1_BASE_IDX 2 9167 #define regOTG1_OTG_REQUEST_CONTROL 0x1c1e 9168 #define regOTG1_OTG_REQUEST_CONTROL_BASE_IDX 2 9169 #define regOTG1_OTG_DSC_START_POSITION 0x1c1f 9170 #define regOTG1_OTG_DSC_START_POSITION_BASE_IDX 2 9171 #define regOTG1_OTG_PIPE_UPDATE_STATUS 0x1c20 9172 #define regOTG1_OTG_PIPE_UPDATE_STATUS_BASE_IDX 2 9173 #define regOTG1_OTG_SPARE_REGISTER 0x1c22 9174 #define regOTG1_OTG_SPARE_REGISTER_BASE_IDX 2 9175 9176 9177 // addressBlock: dce_dc_optc_otg2_dispdec 9178 // base address: 0x400 9179 #define regOTG2_OTG_H_TOTAL 0x1c2a 9180 #define regOTG2_OTG_H_TOTAL_BASE_IDX 2 9181 #define regOTG2_OTG_H_BLANK_START_END 0x1c2b 9182 #define regOTG2_OTG_H_BLANK_START_END_BASE_IDX 2 9183 #define regOTG2_OTG_H_SYNC_A 0x1c2c 9184 #define regOTG2_OTG_H_SYNC_A_BASE_IDX 2 9185 #define regOTG2_OTG_H_SYNC_A_CNTL 0x1c2d 9186 #define regOTG2_OTG_H_SYNC_A_CNTL_BASE_IDX 2 9187 #define regOTG2_OTG_H_TIMING_CNTL 0x1c2e 9188 #define regOTG2_OTG_H_TIMING_CNTL_BASE_IDX 2 9189 #define regOTG2_OTG_V_TOTAL 0x1c2f 9190 #define regOTG2_OTG_V_TOTAL_BASE_IDX 2 9191 #define regOTG2_OTG_V_TOTAL_MIN 0x1c30 9192 #define regOTG2_OTG_V_TOTAL_MIN_BASE_IDX 2 9193 #define regOTG2_OTG_V_TOTAL_MAX 0x1c31 9194 #define regOTG2_OTG_V_TOTAL_MAX_BASE_IDX 2 9195 #define regOTG2_OTG_V_TOTAL_MID 0x1c32 9196 #define regOTG2_OTG_V_TOTAL_MID_BASE_IDX 2 9197 #define regOTG2_OTG_V_TOTAL_CONTROL 0x1c33 9198 #define regOTG2_OTG_V_TOTAL_CONTROL_BASE_IDX 2 9199 #define regOTG2_OTG_V_TOTAL_INT_STATUS 0x1c34 9200 #define regOTG2_OTG_V_TOTAL_INT_STATUS_BASE_IDX 2 9201 #define regOTG2_OTG_VSYNC_NOM_INT_STATUS 0x1c35 9202 #define regOTG2_OTG_VSYNC_NOM_INT_STATUS_BASE_IDX 2 9203 #define regOTG2_OTG_V_BLANK_START_END 0x1c36 9204 #define regOTG2_OTG_V_BLANK_START_END_BASE_IDX 2 9205 #define regOTG2_OTG_V_SYNC_A 0x1c37 9206 #define regOTG2_OTG_V_SYNC_A_BASE_IDX 2 9207 #define regOTG2_OTG_V_SYNC_A_CNTL 0x1c38 9208 #define regOTG2_OTG_V_SYNC_A_CNTL_BASE_IDX 2 9209 #define regOTG2_OTG_TRIGA_CNTL 0x1c39 9210 #define regOTG2_OTG_TRIGA_CNTL_BASE_IDX 2 9211 #define regOTG2_OTG_TRIGA_MANUAL_TRIG 0x1c3a 9212 #define regOTG2_OTG_TRIGA_MANUAL_TRIG_BASE_IDX 2 9213 #define regOTG2_OTG_TRIGB_CNTL 0x1c3b 9214 #define regOTG2_OTG_TRIGB_CNTL_BASE_IDX 2 9215 #define regOTG2_OTG_TRIGB_MANUAL_TRIG 0x1c3c 9216 #define regOTG2_OTG_TRIGB_MANUAL_TRIG_BASE_IDX 2 9217 #define regOTG2_OTG_FORCE_COUNT_NOW_CNTL 0x1c3d 9218 #define regOTG2_OTG_FORCE_COUNT_NOW_CNTL_BASE_IDX 2 9219 #define regOTG2_OTG_FLOW_CONTROL 0x1c3e 9220 #define regOTG2_OTG_FLOW_CONTROL_BASE_IDX 2 9221 #define regOTG2_OTG_STEREO_FORCE_NEXT_EYE 0x1c3f 9222 #define regOTG2_OTG_STEREO_FORCE_NEXT_EYE_BASE_IDX 2 9223 #define regOTG2_OTG_CONTROL 0x1c41 9224 #define regOTG2_OTG_CONTROL_BASE_IDX 2 9225 #define regOTG2_OTG_INTERLACE_CONTROL 0x1c44 9226 #define regOTG2_OTG_INTERLACE_CONTROL_BASE_IDX 2 9227 #define regOTG2_OTG_INTERLACE_STATUS 0x1c45 9228 #define regOTG2_OTG_INTERLACE_STATUS_BASE_IDX 2 9229 #define regOTG2_OTG_PIXEL_DATA_READBACK0 0x1c47 9230 #define regOTG2_OTG_PIXEL_DATA_READBACK0_BASE_IDX 2 9231 #define regOTG2_OTG_PIXEL_DATA_READBACK1 0x1c48 9232 #define regOTG2_OTG_PIXEL_DATA_READBACK1_BASE_IDX 2 9233 #define regOTG2_OTG_STATUS 0x1c49 9234 #define regOTG2_OTG_STATUS_BASE_IDX 2 9235 #define regOTG2_OTG_STATUS_POSITION 0x1c4a 9236 #define regOTG2_OTG_STATUS_POSITION_BASE_IDX 2 9237 #define regOTG2_OTG_NOM_VERT_POSITION 0x1c4b 9238 #define regOTG2_OTG_NOM_VERT_POSITION_BASE_IDX 2 9239 #define regOTG2_OTG_STATUS_FRAME_COUNT 0x1c4c 9240 #define regOTG2_OTG_STATUS_FRAME_COUNT_BASE_IDX 2 9241 #define regOTG2_OTG_STATUS_VF_COUNT 0x1c4d 9242 #define regOTG2_OTG_STATUS_VF_COUNT_BASE_IDX 2 9243 #define regOTG2_OTG_STATUS_HV_COUNT 0x1c4e 9244 #define regOTG2_OTG_STATUS_HV_COUNT_BASE_IDX 2 9245 #define regOTG2_OTG_COUNT_CONTROL 0x1c4f 9246 #define regOTG2_OTG_COUNT_CONTROL_BASE_IDX 2 9247 #define regOTG2_OTG_COUNT_RESET 0x1c50 9248 #define regOTG2_OTG_COUNT_RESET_BASE_IDX 2 9249 #define regOTG2_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE 0x1c51 9250 #define regOTG2_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX 2 9251 #define regOTG2_OTG_VERT_SYNC_CONTROL 0x1c52 9252 #define regOTG2_OTG_VERT_SYNC_CONTROL_BASE_IDX 2 9253 #define regOTG2_OTG_STEREO_STATUS 0x1c53 9254 #define regOTG2_OTG_STEREO_STATUS_BASE_IDX 2 9255 #define regOTG2_OTG_STEREO_CONTROL 0x1c54 9256 #define regOTG2_OTG_STEREO_CONTROL_BASE_IDX 2 9257 #define regOTG2_OTG_SNAPSHOT_STATUS 0x1c55 9258 #define regOTG2_OTG_SNAPSHOT_STATUS_BASE_IDX 2 9259 #define regOTG2_OTG_SNAPSHOT_CONTROL 0x1c56 9260 #define regOTG2_OTG_SNAPSHOT_CONTROL_BASE_IDX 2 9261 #define regOTG2_OTG_SNAPSHOT_POSITION 0x1c57 9262 #define regOTG2_OTG_SNAPSHOT_POSITION_BASE_IDX 2 9263 #define regOTG2_OTG_SNAPSHOT_FRAME 0x1c58 9264 #define regOTG2_OTG_SNAPSHOT_FRAME_BASE_IDX 2 9265 #define regOTG2_OTG_INTERRUPT_CONTROL 0x1c59 9266 #define regOTG2_OTG_INTERRUPT_CONTROL_BASE_IDX 2 9267 #define regOTG2_OTG_UPDATE_LOCK 0x1c5a 9268 #define regOTG2_OTG_UPDATE_LOCK_BASE_IDX 2 9269 #define regOTG2_OTG_DOUBLE_BUFFER_CONTROL 0x1c5b 9270 #define regOTG2_OTG_DOUBLE_BUFFER_CONTROL_BASE_IDX 2 9271 #define regOTG2_OTG_MASTER_EN 0x1c5c 9272 #define regOTG2_OTG_MASTER_EN_BASE_IDX 2 9273 #define regOTG2_OTG_VERTICAL_INTERRUPT0_POSITION 0x1c62 9274 #define regOTG2_OTG_VERTICAL_INTERRUPT0_POSITION_BASE_IDX 2 9275 #define regOTG2_OTG_VERTICAL_INTERRUPT0_CONTROL 0x1c63 9276 #define regOTG2_OTG_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX 2 9277 #define regOTG2_OTG_VERTICAL_INTERRUPT1_POSITION 0x1c64 9278 #define regOTG2_OTG_VERTICAL_INTERRUPT1_POSITION_BASE_IDX 2 9279 #define regOTG2_OTG_VERTICAL_INTERRUPT1_CONTROL 0x1c65 9280 #define regOTG2_OTG_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX 2 9281 #define regOTG2_OTG_VERTICAL_INTERRUPT2_POSITION 0x1c66 9282 #define regOTG2_OTG_VERTICAL_INTERRUPT2_POSITION_BASE_IDX 2 9283 #define regOTG2_OTG_VERTICAL_INTERRUPT2_CONTROL 0x1c67 9284 #define regOTG2_OTG_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX 2 9285 #define regOTG2_OTG_CRC_CNTL 0x1c68 9286 #define regOTG2_OTG_CRC_CNTL_BASE_IDX 2 9287 #define regOTG2_OTG_CRC_CNTL2 0x1c69 9288 #define regOTG2_OTG_CRC_CNTL2_BASE_IDX 2 9289 #define regOTG2_OTG_CRC0_WINDOWA_X_CONTROL 0x1c6a 9290 #define regOTG2_OTG_CRC0_WINDOWA_X_CONTROL_BASE_IDX 2 9291 #define regOTG2_OTG_CRC0_WINDOWA_Y_CONTROL 0x1c6b 9292 #define regOTG2_OTG_CRC0_WINDOWA_Y_CONTROL_BASE_IDX 2 9293 #define regOTG2_OTG_CRC0_WINDOWB_X_CONTROL 0x1c6c 9294 #define regOTG2_OTG_CRC0_WINDOWB_X_CONTROL_BASE_IDX 2 9295 #define regOTG2_OTG_CRC0_WINDOWB_Y_CONTROL 0x1c6d 9296 #define regOTG2_OTG_CRC0_WINDOWB_Y_CONTROL_BASE_IDX 2 9297 #define regOTG2_OTG_CRC0_DATA_RG 0x1c6e 9298 #define regOTG2_OTG_CRC0_DATA_RG_BASE_IDX 2 9299 #define regOTG2_OTG_CRC0_DATA_B 0x1c6f 9300 #define regOTG2_OTG_CRC0_DATA_B_BASE_IDX 2 9301 #define regOTG2_OTG_CRC1_WINDOWA_X_CONTROL 0x1c70 9302 #define regOTG2_OTG_CRC1_WINDOWA_X_CONTROL_BASE_IDX 2 9303 #define regOTG2_OTG_CRC1_WINDOWA_Y_CONTROL 0x1c71 9304 #define regOTG2_OTG_CRC1_WINDOWA_Y_CONTROL_BASE_IDX 2 9305 #define regOTG2_OTG_CRC1_WINDOWB_X_CONTROL 0x1c72 9306 #define regOTG2_OTG_CRC1_WINDOWB_X_CONTROL_BASE_IDX 2 9307 #define regOTG2_OTG_CRC1_WINDOWB_Y_CONTROL 0x1c73 9308 #define regOTG2_OTG_CRC1_WINDOWB_Y_CONTROL_BASE_IDX 2 9309 #define regOTG2_OTG_CRC1_DATA_RG 0x1c74 9310 #define regOTG2_OTG_CRC1_DATA_RG_BASE_IDX 2 9311 #define regOTG2_OTG_CRC1_DATA_B 0x1c75 9312 #define regOTG2_OTG_CRC1_DATA_B_BASE_IDX 2 9313 #define regOTG2_OTG_CRC2_DATA_RG 0x1c76 9314 #define regOTG2_OTG_CRC2_DATA_RG_BASE_IDX 2 9315 #define regOTG2_OTG_CRC2_DATA_B 0x1c77 9316 #define regOTG2_OTG_CRC2_DATA_B_BASE_IDX 2 9317 #define regOTG2_OTG_CRC3_DATA_RG 0x1c78 9318 #define regOTG2_OTG_CRC3_DATA_RG_BASE_IDX 2 9319 #define regOTG2_OTG_CRC3_DATA_B 0x1c79 9320 #define regOTG2_OTG_CRC3_DATA_B_BASE_IDX 2 9321 #define regOTG2_OTG_CRC_SIG_RED_GREEN_MASK 0x1c7a 9322 #define regOTG2_OTG_CRC_SIG_RED_GREEN_MASK_BASE_IDX 2 9323 #define regOTG2_OTG_CRC_SIG_BLUE_CONTROL_MASK 0x1c7b 9324 #define regOTG2_OTG_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX 2 9325 #define regOTG2_OTG_STATIC_SCREEN_CONTROL 0x1c82 9326 #define regOTG2_OTG_STATIC_SCREEN_CONTROL_BASE_IDX 2 9327 #define regOTG2_OTG_3D_STRUCTURE_CONTROL 0x1c83 9328 #define regOTG2_OTG_3D_STRUCTURE_CONTROL_BASE_IDX 2 9329 #define regOTG2_OTG_GSL_VSYNC_GAP 0x1c84 9330 #define regOTG2_OTG_GSL_VSYNC_GAP_BASE_IDX 2 9331 #define regOTG2_OTG_MASTER_UPDATE_MODE 0x1c85 9332 #define regOTG2_OTG_MASTER_UPDATE_MODE_BASE_IDX 2 9333 #define regOTG2_OTG_CLOCK_CONTROL 0x1c86 9334 #define regOTG2_OTG_CLOCK_CONTROL_BASE_IDX 2 9335 #define regOTG2_OTG_VSTARTUP_PARAM 0x1c87 9336 #define regOTG2_OTG_VSTARTUP_PARAM_BASE_IDX 2 9337 #define regOTG2_OTG_VUPDATE_PARAM 0x1c88 9338 #define regOTG2_OTG_VUPDATE_PARAM_BASE_IDX 2 9339 #define regOTG2_OTG_VREADY_PARAM 0x1c89 9340 #define regOTG2_OTG_VREADY_PARAM_BASE_IDX 2 9341 #define regOTG2_OTG_GLOBAL_SYNC_STATUS 0x1c8a 9342 #define regOTG2_OTG_GLOBAL_SYNC_STATUS_BASE_IDX 2 9343 #define regOTG2_OTG_MASTER_UPDATE_LOCK 0x1c8b 9344 #define regOTG2_OTG_MASTER_UPDATE_LOCK_BASE_IDX 2 9345 #define regOTG2_OTG_GSL_CONTROL 0x1c8c 9346 #define regOTG2_OTG_GSL_CONTROL_BASE_IDX 2 9347 #define regOTG2_OTG_GSL_WINDOW_X 0x1c8d 9348 #define regOTG2_OTG_GSL_WINDOW_X_BASE_IDX 2 9349 #define regOTG2_OTG_GSL_WINDOW_Y 0x1c8e 9350 #define regOTG2_OTG_GSL_WINDOW_Y_BASE_IDX 2 9351 #define regOTG2_OTG_VUPDATE_KEEPOUT 0x1c8f 9352 #define regOTG2_OTG_VUPDATE_KEEPOUT_BASE_IDX 2 9353 #define regOTG2_OTG_GLOBAL_CONTROL0 0x1c90 9354 #define regOTG2_OTG_GLOBAL_CONTROL0_BASE_IDX 2 9355 #define regOTG2_OTG_GLOBAL_CONTROL1 0x1c91 9356 #define regOTG2_OTG_GLOBAL_CONTROL1_BASE_IDX 2 9357 #define regOTG2_OTG_GLOBAL_CONTROL2 0x1c92 9358 #define regOTG2_OTG_GLOBAL_CONTROL2_BASE_IDX 2 9359 #define regOTG2_OTG_GLOBAL_CONTROL3 0x1c93 9360 #define regOTG2_OTG_GLOBAL_CONTROL3_BASE_IDX 2 9361 #define regOTG2_OTG_GLOBAL_CONTROL4 0x1c94 9362 #define regOTG2_OTG_GLOBAL_CONTROL4_BASE_IDX 2 9363 #define regOTG2_OTG_TRIG_MANUAL_CONTROL 0x1c95 9364 #define regOTG2_OTG_TRIG_MANUAL_CONTROL_BASE_IDX 2 9365 #define regOTG2_OTG_MANUAL_FLOW_CONTROL 0x1c96 9366 #define regOTG2_OTG_MANUAL_FLOW_CONTROL_BASE_IDX 2 9367 #define regOTG2_OTG_DRR_TIMING_INT_STATUS 0x1c97 9368 #define regOTG2_OTG_DRR_TIMING_INT_STATUS_BASE_IDX 2 9369 #define regOTG2_OTG_DRR_V_TOTAL_REACH_RANGE 0x1c98 9370 #define regOTG2_OTG_DRR_V_TOTAL_REACH_RANGE_BASE_IDX 2 9371 #define regOTG2_OTG_DRR_V_TOTAL_CHANGE 0x1c99 9372 #define regOTG2_OTG_DRR_V_TOTAL_CHANGE_BASE_IDX 2 9373 #define regOTG2_OTG_DRR_TRIGGER_WINDOW 0x1c9a 9374 #define regOTG2_OTG_DRR_TRIGGER_WINDOW_BASE_IDX 2 9375 #define regOTG2_OTG_DRR_CONTROL 0x1c9b 9376 #define regOTG2_OTG_DRR_CONTROL_BASE_IDX 2 9377 #define regOTG2_OTG_M_CONST_DTO0 0x1c9c 9378 #define regOTG2_OTG_M_CONST_DTO0_BASE_IDX 2 9379 #define regOTG2_OTG_M_CONST_DTO1 0x1c9d 9380 #define regOTG2_OTG_M_CONST_DTO1_BASE_IDX 2 9381 #define regOTG2_OTG_REQUEST_CONTROL 0x1c9e 9382 #define regOTG2_OTG_REQUEST_CONTROL_BASE_IDX 2 9383 #define regOTG2_OTG_DSC_START_POSITION 0x1c9f 9384 #define regOTG2_OTG_DSC_START_POSITION_BASE_IDX 2 9385 #define regOTG2_OTG_PIPE_UPDATE_STATUS 0x1ca0 9386 #define regOTG2_OTG_PIPE_UPDATE_STATUS_BASE_IDX 2 9387 #define regOTG2_OTG_SPARE_REGISTER 0x1ca2 9388 #define regOTG2_OTG_SPARE_REGISTER_BASE_IDX 2 9389 9390 9391 // addressBlock: dce_dc_optc_otg3_dispdec 9392 // base address: 0x600 9393 #define regOTG3_OTG_H_TOTAL 0x1caa 9394 #define regOTG3_OTG_H_TOTAL_BASE_IDX 2 9395 #define regOTG3_OTG_H_BLANK_START_END 0x1cab 9396 #define regOTG3_OTG_H_BLANK_START_END_BASE_IDX 2 9397 #define regOTG3_OTG_H_SYNC_A 0x1cac 9398 #define regOTG3_OTG_H_SYNC_A_BASE_IDX 2 9399 #define regOTG3_OTG_H_SYNC_A_CNTL 0x1cad 9400 #define regOTG3_OTG_H_SYNC_A_CNTL_BASE_IDX 2 9401 #define regOTG3_OTG_H_TIMING_CNTL 0x1cae 9402 #define regOTG3_OTG_H_TIMING_CNTL_BASE_IDX 2 9403 #define regOTG3_OTG_V_TOTAL 0x1caf 9404 #define regOTG3_OTG_V_TOTAL_BASE_IDX 2 9405 #define regOTG3_OTG_V_TOTAL_MIN 0x1cb0 9406 #define regOTG3_OTG_V_TOTAL_MIN_BASE_IDX 2 9407 #define regOTG3_OTG_V_TOTAL_MAX 0x1cb1 9408 #define regOTG3_OTG_V_TOTAL_MAX_BASE_IDX 2 9409 #define regOTG3_OTG_V_TOTAL_MID 0x1cb2 9410 #define regOTG3_OTG_V_TOTAL_MID_BASE_IDX 2 9411 #define regOTG3_OTG_V_TOTAL_CONTROL 0x1cb3 9412 #define regOTG3_OTG_V_TOTAL_CONTROL_BASE_IDX 2 9413 #define regOTG3_OTG_V_TOTAL_INT_STATUS 0x1cb4 9414 #define regOTG3_OTG_V_TOTAL_INT_STATUS_BASE_IDX 2 9415 #define regOTG3_OTG_VSYNC_NOM_INT_STATUS 0x1cb5 9416 #define regOTG3_OTG_VSYNC_NOM_INT_STATUS_BASE_IDX 2 9417 #define regOTG3_OTG_V_BLANK_START_END 0x1cb6 9418 #define regOTG3_OTG_V_BLANK_START_END_BASE_IDX 2 9419 #define regOTG3_OTG_V_SYNC_A 0x1cb7 9420 #define regOTG3_OTG_V_SYNC_A_BASE_IDX 2 9421 #define regOTG3_OTG_V_SYNC_A_CNTL 0x1cb8 9422 #define regOTG3_OTG_V_SYNC_A_CNTL_BASE_IDX 2 9423 #define regOTG3_OTG_TRIGA_CNTL 0x1cb9 9424 #define regOTG3_OTG_TRIGA_CNTL_BASE_IDX 2 9425 #define regOTG3_OTG_TRIGA_MANUAL_TRIG 0x1cba 9426 #define regOTG3_OTG_TRIGA_MANUAL_TRIG_BASE_IDX 2 9427 #define regOTG3_OTG_TRIGB_CNTL 0x1cbb 9428 #define regOTG3_OTG_TRIGB_CNTL_BASE_IDX 2 9429 #define regOTG3_OTG_TRIGB_MANUAL_TRIG 0x1cbc 9430 #define regOTG3_OTG_TRIGB_MANUAL_TRIG_BASE_IDX 2 9431 #define regOTG3_OTG_FORCE_COUNT_NOW_CNTL 0x1cbd 9432 #define regOTG3_OTG_FORCE_COUNT_NOW_CNTL_BASE_IDX 2 9433 #define regOTG3_OTG_FLOW_CONTROL 0x1cbe 9434 #define regOTG3_OTG_FLOW_CONTROL_BASE_IDX 2 9435 #define regOTG3_OTG_STEREO_FORCE_NEXT_EYE 0x1cbf 9436 #define regOTG3_OTG_STEREO_FORCE_NEXT_EYE_BASE_IDX 2 9437 #define regOTG3_OTG_CONTROL 0x1cc1 9438 #define regOTG3_OTG_CONTROL_BASE_IDX 2 9439 #define regOTG3_OTG_INTERLACE_CONTROL 0x1cc4 9440 #define regOTG3_OTG_INTERLACE_CONTROL_BASE_IDX 2 9441 #define regOTG3_OTG_INTERLACE_STATUS 0x1cc5 9442 #define regOTG3_OTG_INTERLACE_STATUS_BASE_IDX 2 9443 #define regOTG3_OTG_PIXEL_DATA_READBACK0 0x1cc7 9444 #define regOTG3_OTG_PIXEL_DATA_READBACK0_BASE_IDX 2 9445 #define regOTG3_OTG_PIXEL_DATA_READBACK1 0x1cc8 9446 #define regOTG3_OTG_PIXEL_DATA_READBACK1_BASE_IDX 2 9447 #define regOTG3_OTG_STATUS 0x1cc9 9448 #define regOTG3_OTG_STATUS_BASE_IDX 2 9449 #define regOTG3_OTG_STATUS_POSITION 0x1cca 9450 #define regOTG3_OTG_STATUS_POSITION_BASE_IDX 2 9451 #define regOTG3_OTG_NOM_VERT_POSITION 0x1ccb 9452 #define regOTG3_OTG_NOM_VERT_POSITION_BASE_IDX 2 9453 #define regOTG3_OTG_STATUS_FRAME_COUNT 0x1ccc 9454 #define regOTG3_OTG_STATUS_FRAME_COUNT_BASE_IDX 2 9455 #define regOTG3_OTG_STATUS_VF_COUNT 0x1ccd 9456 #define regOTG3_OTG_STATUS_VF_COUNT_BASE_IDX 2 9457 #define regOTG3_OTG_STATUS_HV_COUNT 0x1cce 9458 #define regOTG3_OTG_STATUS_HV_COUNT_BASE_IDX 2 9459 #define regOTG3_OTG_COUNT_CONTROL 0x1ccf 9460 #define regOTG3_OTG_COUNT_CONTROL_BASE_IDX 2 9461 #define regOTG3_OTG_COUNT_RESET 0x1cd0 9462 #define regOTG3_OTG_COUNT_RESET_BASE_IDX 2 9463 #define regOTG3_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE 0x1cd1 9464 #define regOTG3_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX 2 9465 #define regOTG3_OTG_VERT_SYNC_CONTROL 0x1cd2 9466 #define regOTG3_OTG_VERT_SYNC_CONTROL_BASE_IDX 2 9467 #define regOTG3_OTG_STEREO_STATUS 0x1cd3 9468 #define regOTG3_OTG_STEREO_STATUS_BASE_IDX 2 9469 #define regOTG3_OTG_STEREO_CONTROL 0x1cd4 9470 #define regOTG3_OTG_STEREO_CONTROL_BASE_IDX 2 9471 #define regOTG3_OTG_SNAPSHOT_STATUS 0x1cd5 9472 #define regOTG3_OTG_SNAPSHOT_STATUS_BASE_IDX 2 9473 #define regOTG3_OTG_SNAPSHOT_CONTROL 0x1cd6 9474 #define regOTG3_OTG_SNAPSHOT_CONTROL_BASE_IDX 2 9475 #define regOTG3_OTG_SNAPSHOT_POSITION 0x1cd7 9476 #define regOTG3_OTG_SNAPSHOT_POSITION_BASE_IDX 2 9477 #define regOTG3_OTG_SNAPSHOT_FRAME 0x1cd8 9478 #define regOTG3_OTG_SNAPSHOT_FRAME_BASE_IDX 2 9479 #define regOTG3_OTG_INTERRUPT_CONTROL 0x1cd9 9480 #define regOTG3_OTG_INTERRUPT_CONTROL_BASE_IDX 2 9481 #define regOTG3_OTG_UPDATE_LOCK 0x1cda 9482 #define regOTG3_OTG_UPDATE_LOCK_BASE_IDX 2 9483 #define regOTG3_OTG_DOUBLE_BUFFER_CONTROL 0x1cdb 9484 #define regOTG3_OTG_DOUBLE_BUFFER_CONTROL_BASE_IDX 2 9485 #define regOTG3_OTG_MASTER_EN 0x1cdc 9486 #define regOTG3_OTG_MASTER_EN_BASE_IDX 2 9487 #define regOTG3_OTG_VERTICAL_INTERRUPT0_POSITION 0x1ce2 9488 #define regOTG3_OTG_VERTICAL_INTERRUPT0_POSITION_BASE_IDX 2 9489 #define regOTG3_OTG_VERTICAL_INTERRUPT0_CONTROL 0x1ce3 9490 #define regOTG3_OTG_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX 2 9491 #define regOTG3_OTG_VERTICAL_INTERRUPT1_POSITION 0x1ce4 9492 #define regOTG3_OTG_VERTICAL_INTERRUPT1_POSITION_BASE_IDX 2 9493 #define regOTG3_OTG_VERTICAL_INTERRUPT1_CONTROL 0x1ce5 9494 #define regOTG3_OTG_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX 2 9495 #define regOTG3_OTG_VERTICAL_INTERRUPT2_POSITION 0x1ce6 9496 #define regOTG3_OTG_VERTICAL_INTERRUPT2_POSITION_BASE_IDX 2 9497 #define regOTG3_OTG_VERTICAL_INTERRUPT2_CONTROL 0x1ce7 9498 #define regOTG3_OTG_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX 2 9499 #define regOTG3_OTG_CRC_CNTL 0x1ce8 9500 #define regOTG3_OTG_CRC_CNTL_BASE_IDX 2 9501 #define regOTG3_OTG_CRC_CNTL2 0x1ce9 9502 #define regOTG3_OTG_CRC_CNTL2_BASE_IDX 2 9503 #define regOTG3_OTG_CRC0_WINDOWA_X_CONTROL 0x1cea 9504 #define regOTG3_OTG_CRC0_WINDOWA_X_CONTROL_BASE_IDX 2 9505 #define regOTG3_OTG_CRC0_WINDOWA_Y_CONTROL 0x1ceb 9506 #define regOTG3_OTG_CRC0_WINDOWA_Y_CONTROL_BASE_IDX 2 9507 #define regOTG3_OTG_CRC0_WINDOWB_X_CONTROL 0x1cec 9508 #define regOTG3_OTG_CRC0_WINDOWB_X_CONTROL_BASE_IDX 2 9509 #define regOTG3_OTG_CRC0_WINDOWB_Y_CONTROL 0x1ced 9510 #define regOTG3_OTG_CRC0_WINDOWB_Y_CONTROL_BASE_IDX 2 9511 #define regOTG3_OTG_CRC0_DATA_RG 0x1cee 9512 #define regOTG3_OTG_CRC0_DATA_RG_BASE_IDX 2 9513 #define regOTG3_OTG_CRC0_DATA_B 0x1cef 9514 #define regOTG3_OTG_CRC0_DATA_B_BASE_IDX 2 9515 #define regOTG3_OTG_CRC1_WINDOWA_X_CONTROL 0x1cf0 9516 #define regOTG3_OTG_CRC1_WINDOWA_X_CONTROL_BASE_IDX 2 9517 #define regOTG3_OTG_CRC1_WINDOWA_Y_CONTROL 0x1cf1 9518 #define regOTG3_OTG_CRC1_WINDOWA_Y_CONTROL_BASE_IDX 2 9519 #define regOTG3_OTG_CRC1_WINDOWB_X_CONTROL 0x1cf2 9520 #define regOTG3_OTG_CRC1_WINDOWB_X_CONTROL_BASE_IDX 2 9521 #define regOTG3_OTG_CRC1_WINDOWB_Y_CONTROL 0x1cf3 9522 #define regOTG3_OTG_CRC1_WINDOWB_Y_CONTROL_BASE_IDX 2 9523 #define regOTG3_OTG_CRC1_DATA_RG 0x1cf4 9524 #define regOTG3_OTG_CRC1_DATA_RG_BASE_IDX 2 9525 #define regOTG3_OTG_CRC1_DATA_B 0x1cf5 9526 #define regOTG3_OTG_CRC1_DATA_B_BASE_IDX 2 9527 #define regOTG3_OTG_CRC2_DATA_RG 0x1cf6 9528 #define regOTG3_OTG_CRC2_DATA_RG_BASE_IDX 2 9529 #define regOTG3_OTG_CRC2_DATA_B 0x1cf7 9530 #define regOTG3_OTG_CRC2_DATA_B_BASE_IDX 2 9531 #define regOTG3_OTG_CRC3_DATA_RG 0x1cf8 9532 #define regOTG3_OTG_CRC3_DATA_RG_BASE_IDX 2 9533 #define regOTG3_OTG_CRC3_DATA_B 0x1cf9 9534 #define regOTG3_OTG_CRC3_DATA_B_BASE_IDX 2 9535 #define regOTG3_OTG_CRC_SIG_RED_GREEN_MASK 0x1cfa 9536 #define regOTG3_OTG_CRC_SIG_RED_GREEN_MASK_BASE_IDX 2 9537 #define regOTG3_OTG_CRC_SIG_BLUE_CONTROL_MASK 0x1cfb 9538 #define regOTG3_OTG_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX 2 9539 #define regOTG3_OTG_STATIC_SCREEN_CONTROL 0x1d02 9540 #define regOTG3_OTG_STATIC_SCREEN_CONTROL_BASE_IDX 2 9541 #define regOTG3_OTG_3D_STRUCTURE_CONTROL 0x1d03 9542 #define regOTG3_OTG_3D_STRUCTURE_CONTROL_BASE_IDX 2 9543 #define regOTG3_OTG_GSL_VSYNC_GAP 0x1d04 9544 #define regOTG3_OTG_GSL_VSYNC_GAP_BASE_IDX 2 9545 #define regOTG3_OTG_MASTER_UPDATE_MODE 0x1d05 9546 #define regOTG3_OTG_MASTER_UPDATE_MODE_BASE_IDX 2 9547 #define regOTG3_OTG_CLOCK_CONTROL 0x1d06 9548 #define regOTG3_OTG_CLOCK_CONTROL_BASE_IDX 2 9549 #define regOTG3_OTG_VSTARTUP_PARAM 0x1d07 9550 #define regOTG3_OTG_VSTARTUP_PARAM_BASE_IDX 2 9551 #define regOTG3_OTG_VUPDATE_PARAM 0x1d08 9552 #define regOTG3_OTG_VUPDATE_PARAM_BASE_IDX 2 9553 #define regOTG3_OTG_VREADY_PARAM 0x1d09 9554 #define regOTG3_OTG_VREADY_PARAM_BASE_IDX 2 9555 #define regOTG3_OTG_GLOBAL_SYNC_STATUS 0x1d0a 9556 #define regOTG3_OTG_GLOBAL_SYNC_STATUS_BASE_IDX 2 9557 #define regOTG3_OTG_MASTER_UPDATE_LOCK 0x1d0b 9558 #define regOTG3_OTG_MASTER_UPDATE_LOCK_BASE_IDX 2 9559 #define regOTG3_OTG_GSL_CONTROL 0x1d0c 9560 #define regOTG3_OTG_GSL_CONTROL_BASE_IDX 2 9561 #define regOTG3_OTG_GSL_WINDOW_X 0x1d0d 9562 #define regOTG3_OTG_GSL_WINDOW_X_BASE_IDX 2 9563 #define regOTG3_OTG_GSL_WINDOW_Y 0x1d0e 9564 #define regOTG3_OTG_GSL_WINDOW_Y_BASE_IDX 2 9565 #define regOTG3_OTG_VUPDATE_KEEPOUT 0x1d0f 9566 #define regOTG3_OTG_VUPDATE_KEEPOUT_BASE_IDX 2 9567 #define regOTG3_OTG_GLOBAL_CONTROL0 0x1d10 9568 #define regOTG3_OTG_GLOBAL_CONTROL0_BASE_IDX 2 9569 #define regOTG3_OTG_GLOBAL_CONTROL1 0x1d11 9570 #define regOTG3_OTG_GLOBAL_CONTROL1_BASE_IDX 2 9571 #define regOTG3_OTG_GLOBAL_CONTROL2 0x1d12 9572 #define regOTG3_OTG_GLOBAL_CONTROL2_BASE_IDX 2 9573 #define regOTG3_OTG_GLOBAL_CONTROL3 0x1d13 9574 #define regOTG3_OTG_GLOBAL_CONTROL3_BASE_IDX 2 9575 #define regOTG3_OTG_GLOBAL_CONTROL4 0x1d14 9576 #define regOTG3_OTG_GLOBAL_CONTROL4_BASE_IDX 2 9577 #define regOTG3_OTG_TRIG_MANUAL_CONTROL 0x1d15 9578 #define regOTG3_OTG_TRIG_MANUAL_CONTROL_BASE_IDX 2 9579 #define regOTG3_OTG_MANUAL_FLOW_CONTROL 0x1d16 9580 #define regOTG3_OTG_MANUAL_FLOW_CONTROL_BASE_IDX 2 9581 #define regOTG3_OTG_DRR_TIMING_INT_STATUS 0x1d17 9582 #define regOTG3_OTG_DRR_TIMING_INT_STATUS_BASE_IDX 2 9583 #define regOTG3_OTG_DRR_V_TOTAL_REACH_RANGE 0x1d18 9584 #define regOTG3_OTG_DRR_V_TOTAL_REACH_RANGE_BASE_IDX 2 9585 #define regOTG3_OTG_DRR_V_TOTAL_CHANGE 0x1d19 9586 #define regOTG3_OTG_DRR_V_TOTAL_CHANGE_BASE_IDX 2 9587 #define regOTG3_OTG_DRR_TRIGGER_WINDOW 0x1d1a 9588 #define regOTG3_OTG_DRR_TRIGGER_WINDOW_BASE_IDX 2 9589 #define regOTG3_OTG_DRR_CONTROL 0x1d1b 9590 #define regOTG3_OTG_DRR_CONTROL_BASE_IDX 2 9591 #define regOTG3_OTG_M_CONST_DTO0 0x1d1c 9592 #define regOTG3_OTG_M_CONST_DTO0_BASE_IDX 2 9593 #define regOTG3_OTG_M_CONST_DTO1 0x1d1d 9594 #define regOTG3_OTG_M_CONST_DTO1_BASE_IDX 2 9595 #define regOTG3_OTG_REQUEST_CONTROL 0x1d1e 9596 #define regOTG3_OTG_REQUEST_CONTROL_BASE_IDX 2 9597 #define regOTG3_OTG_DSC_START_POSITION 0x1d1f 9598 #define regOTG3_OTG_DSC_START_POSITION_BASE_IDX 2 9599 #define regOTG3_OTG_PIPE_UPDATE_STATUS 0x1d20 9600 #define regOTG3_OTG_PIPE_UPDATE_STATUS_BASE_IDX 2 9601 #define regOTG3_OTG_SPARE_REGISTER 0x1d22 9602 #define regOTG3_OTG_SPARE_REGISTER_BASE_IDX 2 9603 9604 9605 // addressBlock: dce_dc_optc_optc_misc_dispdec 9606 // base address: 0x0 9607 #define regDWB_SOURCE_SELECT 0x1e2a 9608 #define regDWB_SOURCE_SELECT_BASE_IDX 2 9609 #define regGSL_SOURCE_SELECT 0x1e2b 9610 #define regGSL_SOURCE_SELECT_BASE_IDX 2 9611 #define regOPTC_CLOCK_CONTROL 0x1e2c 9612 #define regOPTC_CLOCK_CONTROL_BASE_IDX 2 9613 #define regODM_MEM_PWR_CTRL 0x1e2d 9614 #define regODM_MEM_PWR_CTRL_BASE_IDX 2 9615 #define regODM_MEM_PWR_CTRL3 0x1e2f 9616 #define regODM_MEM_PWR_CTRL3_BASE_IDX 2 9617 #define regODM_MEM_PWR_STATUS 0x1e30 9618 #define regODM_MEM_PWR_STATUS_BASE_IDX 2 9619 #define regOPTC_MISC_SPARE_REGISTER 0x1e31 9620 #define regOPTC_MISC_SPARE_REGISTER_BASE_IDX 2 9621 9622 9623 // addressBlock: dce_dc_optc_optc_dcperfmon_dc_perfmon_dispdec 9624 // base address: 0x79a8 9625 #define regDC_PERFMON17_PERFCOUNTER_CNTL 0x1e6a 9626 #define regDC_PERFMON17_PERFCOUNTER_CNTL_BASE_IDX 2 9627 #define regDC_PERFMON17_PERFCOUNTER_CNTL2 0x1e6b 9628 #define regDC_PERFMON17_PERFCOUNTER_CNTL2_BASE_IDX 2 9629 #define regDC_PERFMON17_PERFCOUNTER_STATE 0x1e6c 9630 #define regDC_PERFMON17_PERFCOUNTER_STATE_BASE_IDX 2 9631 #define regDC_PERFMON17_PERFMON_CNTL 0x1e6d 9632 #define regDC_PERFMON17_PERFMON_CNTL_BASE_IDX 2 9633 #define regDC_PERFMON17_PERFMON_CNTL2 0x1e6e 9634 #define regDC_PERFMON17_PERFMON_CNTL2_BASE_IDX 2 9635 #define regDC_PERFMON17_PERFMON_CVALUE_INT_MISC 0x1e6f 9636 #define regDC_PERFMON17_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 9637 #define regDC_PERFMON17_PERFMON_CVALUE_LOW 0x1e70 9638 #define regDC_PERFMON17_PERFMON_CVALUE_LOW_BASE_IDX 2 9639 #define regDC_PERFMON17_PERFMON_HI 0x1e71 9640 #define regDC_PERFMON17_PERFMON_HI_BASE_IDX 2 9641 #define regDC_PERFMON17_PERFMON_LOW 0x1e72 9642 #define regDC_PERFMON17_PERFMON_LOW_BASE_IDX 2 9643 9644 9645 // addressBlock: dce_dc_dio_hpd0_dispdec 9646 // base address: 0x0 9647 #define regHPD0_DC_HPD_INT_STATUS 0x1f14 9648 #define regHPD0_DC_HPD_INT_STATUS_BASE_IDX 2 9649 #define regHPD0_DC_HPD_INT_CONTROL 0x1f15 9650 #define regHPD0_DC_HPD_INT_CONTROL_BASE_IDX 2 9651 #define regHPD0_DC_HPD_CONTROL 0x1f16 9652 #define regHPD0_DC_HPD_CONTROL_BASE_IDX 2 9653 #define regHPD0_DC_HPD_FAST_TRAIN_CNTL 0x1f17 9654 #define regHPD0_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX 2 9655 #define regHPD0_DC_HPD_TOGGLE_FILT_CNTL 0x1f18 9656 #define regHPD0_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX 2 9657 9658 9659 // addressBlock: dce_dc_dio_hpd1_dispdec 9660 // base address: 0x20 9661 #define regHPD1_DC_HPD_INT_STATUS 0x1f1c 9662 #define regHPD1_DC_HPD_INT_STATUS_BASE_IDX 2 9663 #define regHPD1_DC_HPD_INT_CONTROL 0x1f1d 9664 #define regHPD1_DC_HPD_INT_CONTROL_BASE_IDX 2 9665 #define regHPD1_DC_HPD_CONTROL 0x1f1e 9666 #define regHPD1_DC_HPD_CONTROL_BASE_IDX 2 9667 #define regHPD1_DC_HPD_FAST_TRAIN_CNTL 0x1f1f 9668 #define regHPD1_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX 2 9669 #define regHPD1_DC_HPD_TOGGLE_FILT_CNTL 0x1f20 9670 #define regHPD1_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX 2 9671 9672 9673 // addressBlock: dce_dc_dio_hpd2_dispdec 9674 // base address: 0x40 9675 #define regHPD2_DC_HPD_INT_STATUS 0x1f24 9676 #define regHPD2_DC_HPD_INT_STATUS_BASE_IDX 2 9677 #define regHPD2_DC_HPD_INT_CONTROL 0x1f25 9678 #define regHPD2_DC_HPD_INT_CONTROL_BASE_IDX 2 9679 #define regHPD2_DC_HPD_CONTROL 0x1f26 9680 #define regHPD2_DC_HPD_CONTROL_BASE_IDX 2 9681 #define regHPD2_DC_HPD_FAST_TRAIN_CNTL 0x1f27 9682 #define regHPD2_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX 2 9683 #define regHPD2_DC_HPD_TOGGLE_FILT_CNTL 0x1f28 9684 #define regHPD2_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX 2 9685 9686 9687 // addressBlock: dce_dc_dio_hpd3_dispdec 9688 // base address: 0x60 9689 #define regHPD3_DC_HPD_INT_STATUS 0x1f2c 9690 #define regHPD3_DC_HPD_INT_STATUS_BASE_IDX 2 9691 #define regHPD3_DC_HPD_INT_CONTROL 0x1f2d 9692 #define regHPD3_DC_HPD_INT_CONTROL_BASE_IDX 2 9693 #define regHPD3_DC_HPD_CONTROL 0x1f2e 9694 #define regHPD3_DC_HPD_CONTROL_BASE_IDX 2 9695 #define regHPD3_DC_HPD_FAST_TRAIN_CNTL 0x1f2f 9696 #define regHPD3_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX 2 9697 #define regHPD3_DC_HPD_TOGGLE_FILT_CNTL 0x1f30 9698 #define regHPD3_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX 2 9699 9700 9701 // addressBlock: dce_dc_dio_hpd4_dispdec 9702 // base address: 0x80 9703 #define regHPD4_DC_HPD_INT_STATUS 0x1f34 9704 #define regHPD4_DC_HPD_INT_STATUS_BASE_IDX 2 9705 #define regHPD4_DC_HPD_INT_CONTROL 0x1f35 9706 #define regHPD4_DC_HPD_INT_CONTROL_BASE_IDX 2 9707 #define regHPD4_DC_HPD_CONTROL 0x1f36 9708 #define regHPD4_DC_HPD_CONTROL_BASE_IDX 2 9709 #define regHPD4_DC_HPD_FAST_TRAIN_CNTL 0x1f37 9710 #define regHPD4_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX 2 9711 #define regHPD4_DC_HPD_TOGGLE_FILT_CNTL 0x1f38 9712 #define regHPD4_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX 2 9713 9714 9715 // addressBlock: dce_dc_dio_dp0_dispdec 9716 // base address: 0x0 9717 #define regDP0_DP_LINK_CNTL 0x2108 9718 #define regDP0_DP_LINK_CNTL_BASE_IDX 2 9719 #define regDP0_DP_PIXEL_FORMAT 0x2109 9720 #define regDP0_DP_PIXEL_FORMAT_BASE_IDX 2 9721 #define regDP0_DP_MSA_COLORIMETRY 0x210a 9722 #define regDP0_DP_MSA_COLORIMETRY_BASE_IDX 2 9723 #define regDP0_DP_CONFIG 0x210b 9724 #define regDP0_DP_CONFIG_BASE_IDX 2 9725 #define regDP0_DP_VID_STREAM_CNTL 0x210c 9726 #define regDP0_DP_VID_STREAM_CNTL_BASE_IDX 2 9727 #define regDP0_DP_STEER_FIFO 0x210d 9728 #define regDP0_DP_STEER_FIFO_BASE_IDX 2 9729 #define regDP0_DP_MSA_MISC 0x210e 9730 #define regDP0_DP_MSA_MISC_BASE_IDX 2 9731 #define regDP0_DP_DPHY_INTERNAL_CTRL 0x210f 9732 #define regDP0_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 9733 #define regDP0_DP_VID_TIMING 0x2110 9734 #define regDP0_DP_VID_TIMING_BASE_IDX 2 9735 #define regDP0_DP_VID_N 0x2111 9736 #define regDP0_DP_VID_N_BASE_IDX 2 9737 #define regDP0_DP_VID_M 0x2112 9738 #define regDP0_DP_VID_M_BASE_IDX 2 9739 #define regDP0_DP_LINK_FRAMING_CNTL 0x2113 9740 #define regDP0_DP_LINK_FRAMING_CNTL_BASE_IDX 2 9741 #define regDP0_DP_HBR2_EYE_PATTERN 0x2114 9742 #define regDP0_DP_HBR2_EYE_PATTERN_BASE_IDX 2 9743 #define regDP0_DP_VID_MSA_VBID 0x2115 9744 #define regDP0_DP_VID_MSA_VBID_BASE_IDX 2 9745 #define regDP0_DP_VID_INTERRUPT_CNTL 0x2116 9746 #define regDP0_DP_VID_INTERRUPT_CNTL_BASE_IDX 2 9747 #define regDP0_DP_DPHY_CNTL 0x2117 9748 #define regDP0_DP_DPHY_CNTL_BASE_IDX 2 9749 #define regDP0_DP_DPHY_TRAINING_PATTERN_SEL 0x2118 9750 #define regDP0_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX 2 9751 #define regDP0_DP_DPHY_SYM0 0x2119 9752 #define regDP0_DP_DPHY_SYM0_BASE_IDX 2 9753 #define regDP0_DP_DPHY_SYM1 0x211a 9754 #define regDP0_DP_DPHY_SYM1_BASE_IDX 2 9755 #define regDP0_DP_DPHY_SYM2 0x211b 9756 #define regDP0_DP_DPHY_SYM2_BASE_IDX 2 9757 #define regDP0_DP_DPHY_8B10B_CNTL 0x211c 9758 #define regDP0_DP_DPHY_8B10B_CNTL_BASE_IDX 2 9759 #define regDP0_DP_DPHY_PRBS_CNTL 0x211d 9760 #define regDP0_DP_DPHY_PRBS_CNTL_BASE_IDX 2 9761 #define regDP0_DP_DPHY_SCRAM_CNTL 0x211e 9762 #define regDP0_DP_DPHY_SCRAM_CNTL_BASE_IDX 2 9763 #define regDP0_DP_DPHY_CRC_EN 0x211f 9764 #define regDP0_DP_DPHY_CRC_EN_BASE_IDX 2 9765 #define regDP0_DP_DPHY_CRC_CNTL 0x2120 9766 #define regDP0_DP_DPHY_CRC_CNTL_BASE_IDX 2 9767 #define regDP0_DP_DPHY_CRC_RESULT 0x2121 9768 #define regDP0_DP_DPHY_CRC_RESULT_BASE_IDX 2 9769 #define regDP0_DP_DPHY_CRC_MST_CNTL 0x2122 9770 #define regDP0_DP_DPHY_CRC_MST_CNTL_BASE_IDX 2 9771 #define regDP0_DP_DPHY_CRC_MST_STATUS 0x2123 9772 #define regDP0_DP_DPHY_CRC_MST_STATUS_BASE_IDX 2 9773 #define regDP0_DP_DPHY_FAST_TRAINING 0x2124 9774 #define regDP0_DP_DPHY_FAST_TRAINING_BASE_IDX 2 9775 #define regDP0_DP_DPHY_FAST_TRAINING_STATUS 0x2125 9776 #define regDP0_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX 2 9777 #define regDP0_DP_SEC_CNTL 0x212b 9778 #define regDP0_DP_SEC_CNTL_BASE_IDX 2 9779 #define regDP0_DP_SEC_CNTL1 0x212c 9780 #define regDP0_DP_SEC_CNTL1_BASE_IDX 2 9781 #define regDP0_DP_SEC_FRAMING1 0x212d 9782 #define regDP0_DP_SEC_FRAMING1_BASE_IDX 2 9783 #define regDP0_DP_SEC_FRAMING2 0x212e 9784 #define regDP0_DP_SEC_FRAMING2_BASE_IDX 2 9785 #define regDP0_DP_SEC_FRAMING3 0x212f 9786 #define regDP0_DP_SEC_FRAMING3_BASE_IDX 2 9787 #define regDP0_DP_SEC_FRAMING4 0x2130 9788 #define regDP0_DP_SEC_FRAMING4_BASE_IDX 2 9789 #define regDP0_DP_SEC_AUD_N 0x2131 9790 #define regDP0_DP_SEC_AUD_N_BASE_IDX 2 9791 #define regDP0_DP_SEC_AUD_N_READBACK 0x2132 9792 #define regDP0_DP_SEC_AUD_N_READBACK_BASE_IDX 2 9793 #define regDP0_DP_SEC_AUD_M 0x2133 9794 #define regDP0_DP_SEC_AUD_M_BASE_IDX 2 9795 #define regDP0_DP_SEC_AUD_M_READBACK 0x2134 9796 #define regDP0_DP_SEC_AUD_M_READBACK_BASE_IDX 2 9797 #define regDP0_DP_SEC_TIMESTAMP 0x2135 9798 #define regDP0_DP_SEC_TIMESTAMP_BASE_IDX 2 9799 #define regDP0_DP_SEC_PACKET_CNTL 0x2136 9800 #define regDP0_DP_SEC_PACKET_CNTL_BASE_IDX 2 9801 #define regDP0_DP_MSE_RATE_CNTL 0x2137 9802 #define regDP0_DP_MSE_RATE_CNTL_BASE_IDX 2 9803 #define regDP0_DP_MSE_RATE_UPDATE 0x2139 9804 #define regDP0_DP_MSE_RATE_UPDATE_BASE_IDX 2 9805 #define regDP0_DP_MSE_SAT0 0x213a 9806 #define regDP0_DP_MSE_SAT0_BASE_IDX 2 9807 #define regDP0_DP_MSE_SAT1 0x213b 9808 #define regDP0_DP_MSE_SAT1_BASE_IDX 2 9809 #define regDP0_DP_MSE_SAT2 0x213c 9810 #define regDP0_DP_MSE_SAT2_BASE_IDX 2 9811 #define regDP0_DP_MSE_SAT_UPDATE 0x213d 9812 #define regDP0_DP_MSE_SAT_UPDATE_BASE_IDX 2 9813 #define regDP0_DP_MSE_LINK_TIMING 0x213e 9814 #define regDP0_DP_MSE_LINK_TIMING_BASE_IDX 2 9815 #define regDP0_DP_MSE_MISC_CNTL 0x213f 9816 #define regDP0_DP_MSE_MISC_CNTL_BASE_IDX 2 9817 #define regDP0_DP_DPHY_BS_SR_SWAP_CNTL 0x2144 9818 #define regDP0_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX 2 9819 #define regDP0_DP_DPHY_HBR2_PATTERN_CONTROL 0x2145 9820 #define regDP0_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX 2 9821 #define regDP0_DP_MSE_SAT0_STATUS 0x2147 9822 #define regDP0_DP_MSE_SAT0_STATUS_BASE_IDX 2 9823 #define regDP0_DP_MSE_SAT1_STATUS 0x2148 9824 #define regDP0_DP_MSE_SAT1_STATUS_BASE_IDX 2 9825 #define regDP0_DP_MSE_SAT2_STATUS 0x2149 9826 #define regDP0_DP_MSE_SAT2_STATUS_BASE_IDX 2 9827 #define regDP0_DP_MSA_TIMING_PARAM1 0x214c 9828 #define regDP0_DP_MSA_TIMING_PARAM1_BASE_IDX 2 9829 #define regDP0_DP_MSA_TIMING_PARAM2 0x214d 9830 #define regDP0_DP_MSA_TIMING_PARAM2_BASE_IDX 2 9831 #define regDP0_DP_MSA_TIMING_PARAM3 0x214e 9832 #define regDP0_DP_MSA_TIMING_PARAM3_BASE_IDX 2 9833 #define regDP0_DP_MSA_TIMING_PARAM4 0x214f 9834 #define regDP0_DP_MSA_TIMING_PARAM4_BASE_IDX 2 9835 #define regDP0_DP_MSO_CNTL 0x2150 9836 #define regDP0_DP_MSO_CNTL_BASE_IDX 2 9837 #define regDP0_DP_MSO_CNTL1 0x2151 9838 #define regDP0_DP_MSO_CNTL1_BASE_IDX 2 9839 #define regDP0_DP_DSC_CNTL 0x2152 9840 #define regDP0_DP_DSC_CNTL_BASE_IDX 2 9841 #define regDP0_DP_SEC_CNTL2 0x2153 9842 #define regDP0_DP_SEC_CNTL2_BASE_IDX 2 9843 #define regDP0_DP_SEC_CNTL3 0x2154 9844 #define regDP0_DP_SEC_CNTL3_BASE_IDX 2 9845 #define regDP0_DP_SEC_CNTL4 0x2155 9846 #define regDP0_DP_SEC_CNTL4_BASE_IDX 2 9847 #define regDP0_DP_SEC_CNTL5 0x2156 9848 #define regDP0_DP_SEC_CNTL5_BASE_IDX 2 9849 #define regDP0_DP_SEC_CNTL6 0x2157 9850 #define regDP0_DP_SEC_CNTL6_BASE_IDX 2 9851 #define regDP0_DP_SEC_CNTL7 0x2158 9852 #define regDP0_DP_SEC_CNTL7_BASE_IDX 2 9853 #define regDP0_DP_DB_CNTL 0x2159 9854 #define regDP0_DP_DB_CNTL_BASE_IDX 2 9855 #define regDP0_DP_MSA_VBID_MISC 0x215a 9856 #define regDP0_DP_MSA_VBID_MISC_BASE_IDX 2 9857 #define regDP0_DP_SEC_METADATA_TRANSMISSION 0x215b 9858 #define regDP0_DP_SEC_METADATA_TRANSMISSION_BASE_IDX 2 9859 #define regDP0_DP_DSC_BYTES_PER_PIXEL 0x215c 9860 #define regDP0_DP_DSC_BYTES_PER_PIXEL_BASE_IDX 2 9861 #define regDP0_DP_ALPM_CNTL 0x215d 9862 #define regDP0_DP_ALPM_CNTL_BASE_IDX 2 9863 #define regDP0_DP_GSP8_CNTL 0x215e 9864 #define regDP0_DP_GSP8_CNTL_BASE_IDX 2 9865 #define regDP0_DP_GSP9_CNTL 0x215f 9866 #define regDP0_DP_GSP9_CNTL_BASE_IDX 2 9867 #define regDP0_DP_GSP10_CNTL 0x2160 9868 #define regDP0_DP_GSP10_CNTL_BASE_IDX 2 9869 #define regDP0_DP_GSP11_CNTL 0x2161 9870 #define regDP0_DP_GSP11_CNTL_BASE_IDX 2 9871 #define regDP0_DP_GSP_EN_DB_STATUS 0x2162 9872 #define regDP0_DP_GSP_EN_DB_STATUS_BASE_IDX 2 9873 9874 9875 // addressBlock: dce_dc_dio_dig0_dispdec 9876 // base address: 0x0 9877 #define regDIG0_DIG_FE_CNTL 0x208b 9878 #define regDIG0_DIG_FE_CNTL_BASE_IDX 2 9879 #define regDIG0_DIG_OUTPUT_CRC_CNTL 0x208c 9880 #define regDIG0_DIG_OUTPUT_CRC_CNTL_BASE_IDX 2 9881 #define regDIG0_DIG_OUTPUT_CRC_RESULT 0x208d 9882 #define regDIG0_DIG_OUTPUT_CRC_RESULT_BASE_IDX 2 9883 #define regDIG0_DIG_CLOCK_PATTERN 0x208e 9884 #define regDIG0_DIG_CLOCK_PATTERN_BASE_IDX 2 9885 #define regDIG0_DIG_TEST_PATTERN 0x208f 9886 #define regDIG0_DIG_TEST_PATTERN_BASE_IDX 2 9887 #define regDIG0_DIG_RANDOM_PATTERN_SEED 0x2090 9888 #define regDIG0_DIG_RANDOM_PATTERN_SEED_BASE_IDX 2 9889 #define regDIG0_DIG_FIFO_STATUS 0x2091 9890 #define regDIG0_DIG_FIFO_STATUS_BASE_IDX 2 9891 #define regDIG0_HDMI_METADATA_PACKET_CONTROL 0x2092 9892 #define regDIG0_HDMI_METADATA_PACKET_CONTROL_BASE_IDX 2 9893 #define regDIG0_HDMI_CONTROL 0x2093 9894 #define regDIG0_HDMI_CONTROL_BASE_IDX 2 9895 #define regDIG0_HDMI_STATUS 0x2094 9896 #define regDIG0_HDMI_STATUS_BASE_IDX 2 9897 #define regDIG0_HDMI_AUDIO_PACKET_CONTROL 0x2095 9898 #define regDIG0_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX 2 9899 #define regDIG0_HDMI_ACR_PACKET_CONTROL 0x2096 9900 #define regDIG0_HDMI_ACR_PACKET_CONTROL_BASE_IDX 2 9901 #define regDIG0_HDMI_VBI_PACKET_CONTROL 0x2097 9902 #define regDIG0_HDMI_VBI_PACKET_CONTROL_BASE_IDX 2 9903 #define regDIG0_HDMI_INFOFRAME_CONTROL0 0x2098 9904 #define regDIG0_HDMI_INFOFRAME_CONTROL0_BASE_IDX 2 9905 #define regDIG0_HDMI_INFOFRAME_CONTROL1 0x2099 9906 #define regDIG0_HDMI_INFOFRAME_CONTROL1_BASE_IDX 2 9907 #define regDIG0_HDMI_GENERIC_PACKET_CONTROL0 0x209a 9908 #define regDIG0_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX 2 9909 #define regDIG0_HDMI_GENERIC_PACKET_CONTROL6 0x209b 9910 #define regDIG0_HDMI_GENERIC_PACKET_CONTROL6_BASE_IDX 2 9911 #define regDIG0_HDMI_GENERIC_PACKET_CONTROL5 0x209c 9912 #define regDIG0_HDMI_GENERIC_PACKET_CONTROL5_BASE_IDX 2 9913 #define regDIG0_HDMI_GC 0x209d 9914 #define regDIG0_HDMI_GC_BASE_IDX 2 9915 #define regDIG0_HDMI_GENERIC_PACKET_CONTROL1 0x209e 9916 #define regDIG0_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX 2 9917 #define regDIG0_HDMI_GENERIC_PACKET_CONTROL2 0x209f 9918 #define regDIG0_HDMI_GENERIC_PACKET_CONTROL2_BASE_IDX 2 9919 #define regDIG0_HDMI_GENERIC_PACKET_CONTROL3 0x20a0 9920 #define regDIG0_HDMI_GENERIC_PACKET_CONTROL3_BASE_IDX 2 9921 #define regDIG0_HDMI_GENERIC_PACKET_CONTROL4 0x20a1 9922 #define regDIG0_HDMI_GENERIC_PACKET_CONTROL4_BASE_IDX 2 9923 #define regDIG0_HDMI_GENERIC_PACKET_CONTROL7 0x20a2 9924 #define regDIG0_HDMI_GENERIC_PACKET_CONTROL7_BASE_IDX 2 9925 #define regDIG0_HDMI_GENERIC_PACKET_CONTROL8 0x20a3 9926 #define regDIG0_HDMI_GENERIC_PACKET_CONTROL8_BASE_IDX 2 9927 #define regDIG0_HDMI_GENERIC_PACKET_CONTROL9 0x20a4 9928 #define regDIG0_HDMI_GENERIC_PACKET_CONTROL9_BASE_IDX 2 9929 #define regDIG0_HDMI_GENERIC_PACKET_CONTROL10 0x20a5 9930 #define regDIG0_HDMI_GENERIC_PACKET_CONTROL10_BASE_IDX 2 9931 #define regDIG0_HDMI_DB_CONTROL 0x20a6 9932 #define regDIG0_HDMI_DB_CONTROL_BASE_IDX 2 9933 #define regDIG0_HDMI_ACR_32_0 0x20a7 9934 #define regDIG0_HDMI_ACR_32_0_BASE_IDX 2 9935 #define regDIG0_HDMI_ACR_32_1 0x20a8 9936 #define regDIG0_HDMI_ACR_32_1_BASE_IDX 2 9937 #define regDIG0_HDMI_ACR_44_0 0x20a9 9938 #define regDIG0_HDMI_ACR_44_0_BASE_IDX 2 9939 #define regDIG0_HDMI_ACR_44_1 0x20aa 9940 #define regDIG0_HDMI_ACR_44_1_BASE_IDX 2 9941 #define regDIG0_HDMI_ACR_48_0 0x20ab 9942 #define regDIG0_HDMI_ACR_48_0_BASE_IDX 2 9943 #define regDIG0_HDMI_ACR_48_1 0x20ac 9944 #define regDIG0_HDMI_ACR_48_1_BASE_IDX 2 9945 #define regDIG0_HDMI_ACR_STATUS_0 0x20ad 9946 #define regDIG0_HDMI_ACR_STATUS_0_BASE_IDX 2 9947 #define regDIG0_HDMI_ACR_STATUS_1 0x20ae 9948 #define regDIG0_HDMI_ACR_STATUS_1_BASE_IDX 2 9949 #define regDIG0_AFMT_CNTL 0x20af 9950 #define regDIG0_AFMT_CNTL_BASE_IDX 2 9951 #define regDIG0_DIG_BE_CNTL 0x20b0 9952 #define regDIG0_DIG_BE_CNTL_BASE_IDX 2 9953 #define regDIG0_DIG_BE_EN_CNTL 0x20b1 9954 #define regDIG0_DIG_BE_EN_CNTL_BASE_IDX 2 9955 #define regDIG0_TMDS_CNTL 0x20d7 9956 #define regDIG0_TMDS_CNTL_BASE_IDX 2 9957 #define regDIG0_TMDS_CONTROL_CHAR 0x20d8 9958 #define regDIG0_TMDS_CONTROL_CHAR_BASE_IDX 2 9959 #define regDIG0_TMDS_CONTROL0_FEEDBACK 0x20d9 9960 #define regDIG0_TMDS_CONTROL0_FEEDBACK_BASE_IDX 2 9961 #define regDIG0_TMDS_STEREOSYNC_CTL_SEL 0x20da 9962 #define regDIG0_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX 2 9963 #define regDIG0_TMDS_SYNC_CHAR_PATTERN_0_1 0x20db 9964 #define regDIG0_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX 2 9965 #define regDIG0_TMDS_SYNC_CHAR_PATTERN_2_3 0x20dc 9966 #define regDIG0_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX 2 9967 #define regDIG0_TMDS_CTL_BITS 0x20de 9968 #define regDIG0_TMDS_CTL_BITS_BASE_IDX 2 9969 #define regDIG0_TMDS_DCBALANCER_CONTROL 0x20df 9970 #define regDIG0_TMDS_DCBALANCER_CONTROL_BASE_IDX 2 9971 #define regDIG0_TMDS_SYNC_DCBALANCE_CHAR 0x20e0 9972 #define regDIG0_TMDS_SYNC_DCBALANCE_CHAR_BASE_IDX 2 9973 #define regDIG0_TMDS_CTL0_1_GEN_CNTL 0x20e1 9974 #define regDIG0_TMDS_CTL0_1_GEN_CNTL_BASE_IDX 2 9975 #define regDIG0_TMDS_CTL2_3_GEN_CNTL 0x20e2 9976 #define regDIG0_TMDS_CTL2_3_GEN_CNTL_BASE_IDX 2 9977 #define regDIG0_DIG_VERSION 0x20e4 9978 #define regDIG0_DIG_VERSION_BASE_IDX 2 9979 #define regDIG0_FORCE_DIG_DISABLE 0x20e5 9980 #define regDIG0_FORCE_DIG_DISABLE_BASE_IDX 2 9981 9982 9983 // addressBlock: dce_dc_dio_dp1_dispdec 9984 // base address: 0x400 9985 #define regDP1_DP_LINK_CNTL 0x2208 9986 #define regDP1_DP_LINK_CNTL_BASE_IDX 2 9987 #define regDP1_DP_PIXEL_FORMAT 0x2209 9988 #define regDP1_DP_PIXEL_FORMAT_BASE_IDX 2 9989 #define regDP1_DP_MSA_COLORIMETRY 0x220a 9990 #define regDP1_DP_MSA_COLORIMETRY_BASE_IDX 2 9991 #define regDP1_DP_CONFIG 0x220b 9992 #define regDP1_DP_CONFIG_BASE_IDX 2 9993 #define regDP1_DP_VID_STREAM_CNTL 0x220c 9994 #define regDP1_DP_VID_STREAM_CNTL_BASE_IDX 2 9995 #define regDP1_DP_STEER_FIFO 0x220d 9996 #define regDP1_DP_STEER_FIFO_BASE_IDX 2 9997 #define regDP1_DP_MSA_MISC 0x220e 9998 #define regDP1_DP_MSA_MISC_BASE_IDX 2 9999 #define regDP1_DP_DPHY_INTERNAL_CTRL 0x220f 10000 #define regDP1_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 10001 #define regDP1_DP_VID_TIMING 0x2210 10002 #define regDP1_DP_VID_TIMING_BASE_IDX 2 10003 #define regDP1_DP_VID_N 0x2211 10004 #define regDP1_DP_VID_N_BASE_IDX 2 10005 #define regDP1_DP_VID_M 0x2212 10006 #define regDP1_DP_VID_M_BASE_IDX 2 10007 #define regDP1_DP_LINK_FRAMING_CNTL 0x2213 10008 #define regDP1_DP_LINK_FRAMING_CNTL_BASE_IDX 2 10009 #define regDP1_DP_HBR2_EYE_PATTERN 0x2214 10010 #define regDP1_DP_HBR2_EYE_PATTERN_BASE_IDX 2 10011 #define regDP1_DP_VID_MSA_VBID 0x2215 10012 #define regDP1_DP_VID_MSA_VBID_BASE_IDX 2 10013 #define regDP1_DP_VID_INTERRUPT_CNTL 0x2216 10014 #define regDP1_DP_VID_INTERRUPT_CNTL_BASE_IDX 2 10015 #define regDP1_DP_DPHY_CNTL 0x2217 10016 #define regDP1_DP_DPHY_CNTL_BASE_IDX 2 10017 #define regDP1_DP_DPHY_TRAINING_PATTERN_SEL 0x2218 10018 #define regDP1_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX 2 10019 #define regDP1_DP_DPHY_SYM0 0x2219 10020 #define regDP1_DP_DPHY_SYM0_BASE_IDX 2 10021 #define regDP1_DP_DPHY_SYM1 0x221a 10022 #define regDP1_DP_DPHY_SYM1_BASE_IDX 2 10023 #define regDP1_DP_DPHY_SYM2 0x221b 10024 #define regDP1_DP_DPHY_SYM2_BASE_IDX 2 10025 #define regDP1_DP_DPHY_8B10B_CNTL 0x221c 10026 #define regDP1_DP_DPHY_8B10B_CNTL_BASE_IDX 2 10027 #define regDP1_DP_DPHY_PRBS_CNTL 0x221d 10028 #define regDP1_DP_DPHY_PRBS_CNTL_BASE_IDX 2 10029 #define regDP1_DP_DPHY_SCRAM_CNTL 0x221e 10030 #define regDP1_DP_DPHY_SCRAM_CNTL_BASE_IDX 2 10031 #define regDP1_DP_DPHY_CRC_EN 0x221f 10032 #define regDP1_DP_DPHY_CRC_EN_BASE_IDX 2 10033 #define regDP1_DP_DPHY_CRC_CNTL 0x2220 10034 #define regDP1_DP_DPHY_CRC_CNTL_BASE_IDX 2 10035 #define regDP1_DP_DPHY_CRC_RESULT 0x2221 10036 #define regDP1_DP_DPHY_CRC_RESULT_BASE_IDX 2 10037 #define regDP1_DP_DPHY_CRC_MST_CNTL 0x2222 10038 #define regDP1_DP_DPHY_CRC_MST_CNTL_BASE_IDX 2 10039 #define regDP1_DP_DPHY_CRC_MST_STATUS 0x2223 10040 #define regDP1_DP_DPHY_CRC_MST_STATUS_BASE_IDX 2 10041 #define regDP1_DP_DPHY_FAST_TRAINING 0x2224 10042 #define regDP1_DP_DPHY_FAST_TRAINING_BASE_IDX 2 10043 #define regDP1_DP_DPHY_FAST_TRAINING_STATUS 0x2225 10044 #define regDP1_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX 2 10045 #define regDP1_DP_SEC_CNTL 0x222b 10046 #define regDP1_DP_SEC_CNTL_BASE_IDX 2 10047 #define regDP1_DP_SEC_CNTL1 0x222c 10048 #define regDP1_DP_SEC_CNTL1_BASE_IDX 2 10049 #define regDP1_DP_SEC_FRAMING1 0x222d 10050 #define regDP1_DP_SEC_FRAMING1_BASE_IDX 2 10051 #define regDP1_DP_SEC_FRAMING2 0x222e 10052 #define regDP1_DP_SEC_FRAMING2_BASE_IDX 2 10053 #define regDP1_DP_SEC_FRAMING3 0x222f 10054 #define regDP1_DP_SEC_FRAMING3_BASE_IDX 2 10055 #define regDP1_DP_SEC_FRAMING4 0x2230 10056 #define regDP1_DP_SEC_FRAMING4_BASE_IDX 2 10057 #define regDP1_DP_SEC_AUD_N 0x2231 10058 #define regDP1_DP_SEC_AUD_N_BASE_IDX 2 10059 #define regDP1_DP_SEC_AUD_N_READBACK 0x2232 10060 #define regDP1_DP_SEC_AUD_N_READBACK_BASE_IDX 2 10061 #define regDP1_DP_SEC_AUD_M 0x2233 10062 #define regDP1_DP_SEC_AUD_M_BASE_IDX 2 10063 #define regDP1_DP_SEC_AUD_M_READBACK 0x2234 10064 #define regDP1_DP_SEC_AUD_M_READBACK_BASE_IDX 2 10065 #define regDP1_DP_SEC_TIMESTAMP 0x2235 10066 #define regDP1_DP_SEC_TIMESTAMP_BASE_IDX 2 10067 #define regDP1_DP_SEC_PACKET_CNTL 0x2236 10068 #define regDP1_DP_SEC_PACKET_CNTL_BASE_IDX 2 10069 #define regDP1_DP_MSE_RATE_CNTL 0x2237 10070 #define regDP1_DP_MSE_RATE_CNTL_BASE_IDX 2 10071 #define regDP1_DP_MSE_RATE_UPDATE 0x2239 10072 #define regDP1_DP_MSE_RATE_UPDATE_BASE_IDX 2 10073 #define regDP1_DP_MSE_SAT0 0x223a 10074 #define regDP1_DP_MSE_SAT0_BASE_IDX 2 10075 #define regDP1_DP_MSE_SAT1 0x223b 10076 #define regDP1_DP_MSE_SAT1_BASE_IDX 2 10077 #define regDP1_DP_MSE_SAT2 0x223c 10078 #define regDP1_DP_MSE_SAT2_BASE_IDX 2 10079 #define regDP1_DP_MSE_SAT_UPDATE 0x223d 10080 #define regDP1_DP_MSE_SAT_UPDATE_BASE_IDX 2 10081 #define regDP1_DP_MSE_LINK_TIMING 0x223e 10082 #define regDP1_DP_MSE_LINK_TIMING_BASE_IDX 2 10083 #define regDP1_DP_MSE_MISC_CNTL 0x223f 10084 #define regDP1_DP_MSE_MISC_CNTL_BASE_IDX 2 10085 #define regDP1_DP_DPHY_BS_SR_SWAP_CNTL 0x2244 10086 #define regDP1_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX 2 10087 #define regDP1_DP_DPHY_HBR2_PATTERN_CONTROL 0x2245 10088 #define regDP1_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX 2 10089 #define regDP1_DP_MSE_SAT0_STATUS 0x2247 10090 #define regDP1_DP_MSE_SAT0_STATUS_BASE_IDX 2 10091 #define regDP1_DP_MSE_SAT1_STATUS 0x2248 10092 #define regDP1_DP_MSE_SAT1_STATUS_BASE_IDX 2 10093 #define regDP1_DP_MSE_SAT2_STATUS 0x2249 10094 #define regDP1_DP_MSE_SAT2_STATUS_BASE_IDX 2 10095 #define regDP1_DP_MSA_TIMING_PARAM1 0x224c 10096 #define regDP1_DP_MSA_TIMING_PARAM1_BASE_IDX 2 10097 #define regDP1_DP_MSA_TIMING_PARAM2 0x224d 10098 #define regDP1_DP_MSA_TIMING_PARAM2_BASE_IDX 2 10099 #define regDP1_DP_MSA_TIMING_PARAM3 0x224e 10100 #define regDP1_DP_MSA_TIMING_PARAM3_BASE_IDX 2 10101 #define regDP1_DP_MSA_TIMING_PARAM4 0x224f 10102 #define regDP1_DP_MSA_TIMING_PARAM4_BASE_IDX 2 10103 #define regDP1_DP_MSO_CNTL 0x2250 10104 #define regDP1_DP_MSO_CNTL_BASE_IDX 2 10105 #define regDP1_DP_MSO_CNTL1 0x2251 10106 #define regDP1_DP_MSO_CNTL1_BASE_IDX 2 10107 #define regDP1_DP_DSC_CNTL 0x2252 10108 #define regDP1_DP_DSC_CNTL_BASE_IDX 2 10109 #define regDP1_DP_SEC_CNTL2 0x2253 10110 #define regDP1_DP_SEC_CNTL2_BASE_IDX 2 10111 #define regDP1_DP_SEC_CNTL3 0x2254 10112 #define regDP1_DP_SEC_CNTL3_BASE_IDX 2 10113 #define regDP1_DP_SEC_CNTL4 0x2255 10114 #define regDP1_DP_SEC_CNTL4_BASE_IDX 2 10115 #define regDP1_DP_SEC_CNTL5 0x2256 10116 #define regDP1_DP_SEC_CNTL5_BASE_IDX 2 10117 #define regDP1_DP_SEC_CNTL6 0x2257 10118 #define regDP1_DP_SEC_CNTL6_BASE_IDX 2 10119 #define regDP1_DP_SEC_CNTL7 0x2258 10120 #define regDP1_DP_SEC_CNTL7_BASE_IDX 2 10121 #define regDP1_DP_DB_CNTL 0x2259 10122 #define regDP1_DP_DB_CNTL_BASE_IDX 2 10123 #define regDP1_DP_MSA_VBID_MISC 0x225a 10124 #define regDP1_DP_MSA_VBID_MISC_BASE_IDX 2 10125 #define regDP1_DP_SEC_METADATA_TRANSMISSION 0x225b 10126 #define regDP1_DP_SEC_METADATA_TRANSMISSION_BASE_IDX 2 10127 #define regDP1_DP_DSC_BYTES_PER_PIXEL 0x225c 10128 #define regDP1_DP_DSC_BYTES_PER_PIXEL_BASE_IDX 2 10129 #define regDP1_DP_ALPM_CNTL 0x225d 10130 #define regDP1_DP_ALPM_CNTL_BASE_IDX 2 10131 #define regDP1_DP_GSP8_CNTL 0x225e 10132 #define regDP1_DP_GSP8_CNTL_BASE_IDX 2 10133 #define regDP1_DP_GSP9_CNTL 0x225f 10134 #define regDP1_DP_GSP9_CNTL_BASE_IDX 2 10135 #define regDP1_DP_GSP10_CNTL 0x2260 10136 #define regDP1_DP_GSP10_CNTL_BASE_IDX 2 10137 #define regDP1_DP_GSP11_CNTL 0x2261 10138 #define regDP1_DP_GSP11_CNTL_BASE_IDX 2 10139 #define regDP1_DP_GSP_EN_DB_STATUS 0x2262 10140 #define regDP1_DP_GSP_EN_DB_STATUS_BASE_IDX 2 10141 10142 10143 // addressBlock: dce_dc_dio_dig1_dispdec 10144 // base address: 0x400 10145 #define regDIG1_DIG_FE_CNTL 0x218b 10146 #define regDIG1_DIG_FE_CNTL_BASE_IDX 2 10147 #define regDIG1_DIG_OUTPUT_CRC_CNTL 0x218c 10148 #define regDIG1_DIG_OUTPUT_CRC_CNTL_BASE_IDX 2 10149 #define regDIG1_DIG_OUTPUT_CRC_RESULT 0x218d 10150 #define regDIG1_DIG_OUTPUT_CRC_RESULT_BASE_IDX 2 10151 #define regDIG1_DIG_CLOCK_PATTERN 0x218e 10152 #define regDIG1_DIG_CLOCK_PATTERN_BASE_IDX 2 10153 #define regDIG1_DIG_TEST_PATTERN 0x218f 10154 #define regDIG1_DIG_TEST_PATTERN_BASE_IDX 2 10155 #define regDIG1_DIG_RANDOM_PATTERN_SEED 0x2190 10156 #define regDIG1_DIG_RANDOM_PATTERN_SEED_BASE_IDX 2 10157 #define regDIG1_DIG_FIFO_STATUS 0x2191 10158 #define regDIG1_DIG_FIFO_STATUS_BASE_IDX 2 10159 #define regDIG1_HDMI_METADATA_PACKET_CONTROL 0x2192 10160 #define regDIG1_HDMI_METADATA_PACKET_CONTROL_BASE_IDX 2 10161 #define regDIG1_HDMI_CONTROL 0x2193 10162 #define regDIG1_HDMI_CONTROL_BASE_IDX 2 10163 #define regDIG1_HDMI_STATUS 0x2194 10164 #define regDIG1_HDMI_STATUS_BASE_IDX 2 10165 #define regDIG1_HDMI_AUDIO_PACKET_CONTROL 0x2195 10166 #define regDIG1_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX 2 10167 #define regDIG1_HDMI_ACR_PACKET_CONTROL 0x2196 10168 #define regDIG1_HDMI_ACR_PACKET_CONTROL_BASE_IDX 2 10169 #define regDIG1_HDMI_VBI_PACKET_CONTROL 0x2197 10170 #define regDIG1_HDMI_VBI_PACKET_CONTROL_BASE_IDX 2 10171 #define regDIG1_HDMI_INFOFRAME_CONTROL0 0x2198 10172 #define regDIG1_HDMI_INFOFRAME_CONTROL0_BASE_IDX 2 10173 #define regDIG1_HDMI_INFOFRAME_CONTROL1 0x2199 10174 #define regDIG1_HDMI_INFOFRAME_CONTROL1_BASE_IDX 2 10175 #define regDIG1_HDMI_GENERIC_PACKET_CONTROL0 0x219a 10176 #define regDIG1_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX 2 10177 #define regDIG1_HDMI_GENERIC_PACKET_CONTROL6 0x219b 10178 #define regDIG1_HDMI_GENERIC_PACKET_CONTROL6_BASE_IDX 2 10179 #define regDIG1_HDMI_GENERIC_PACKET_CONTROL5 0x219c 10180 #define regDIG1_HDMI_GENERIC_PACKET_CONTROL5_BASE_IDX 2 10181 #define regDIG1_HDMI_GC 0x219d 10182 #define regDIG1_HDMI_GC_BASE_IDX 2 10183 #define regDIG1_HDMI_GENERIC_PACKET_CONTROL1 0x219e 10184 #define regDIG1_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX 2 10185 #define regDIG1_HDMI_GENERIC_PACKET_CONTROL2 0x219f 10186 #define regDIG1_HDMI_GENERIC_PACKET_CONTROL2_BASE_IDX 2 10187 #define regDIG1_HDMI_GENERIC_PACKET_CONTROL3 0x21a0 10188 #define regDIG1_HDMI_GENERIC_PACKET_CONTROL3_BASE_IDX 2 10189 #define regDIG1_HDMI_GENERIC_PACKET_CONTROL4 0x21a1 10190 #define regDIG1_HDMI_GENERIC_PACKET_CONTROL4_BASE_IDX 2 10191 #define regDIG1_HDMI_GENERIC_PACKET_CONTROL7 0x21a2 10192 #define regDIG1_HDMI_GENERIC_PACKET_CONTROL7_BASE_IDX 2 10193 #define regDIG1_HDMI_GENERIC_PACKET_CONTROL8 0x21a3 10194 #define regDIG1_HDMI_GENERIC_PACKET_CONTROL8_BASE_IDX 2 10195 #define regDIG1_HDMI_GENERIC_PACKET_CONTROL9 0x21a4 10196 #define regDIG1_HDMI_GENERIC_PACKET_CONTROL9_BASE_IDX 2 10197 #define regDIG1_HDMI_GENERIC_PACKET_CONTROL10 0x21a5 10198 #define regDIG1_HDMI_GENERIC_PACKET_CONTROL10_BASE_IDX 2 10199 #define regDIG1_HDMI_DB_CONTROL 0x21a6 10200 #define regDIG1_HDMI_DB_CONTROL_BASE_IDX 2 10201 #define regDIG1_HDMI_ACR_32_0 0x21a7 10202 #define regDIG1_HDMI_ACR_32_0_BASE_IDX 2 10203 #define regDIG1_HDMI_ACR_32_1 0x21a8 10204 #define regDIG1_HDMI_ACR_32_1_BASE_IDX 2 10205 #define regDIG1_HDMI_ACR_44_0 0x21a9 10206 #define regDIG1_HDMI_ACR_44_0_BASE_IDX 2 10207 #define regDIG1_HDMI_ACR_44_1 0x21aa 10208 #define regDIG1_HDMI_ACR_44_1_BASE_IDX 2 10209 #define regDIG1_HDMI_ACR_48_0 0x21ab 10210 #define regDIG1_HDMI_ACR_48_0_BASE_IDX 2 10211 #define regDIG1_HDMI_ACR_48_1 0x21ac 10212 #define regDIG1_HDMI_ACR_48_1_BASE_IDX 2 10213 #define regDIG1_HDMI_ACR_STATUS_0 0x21ad 10214 #define regDIG1_HDMI_ACR_STATUS_0_BASE_IDX 2 10215 #define regDIG1_HDMI_ACR_STATUS_1 0x21ae 10216 #define regDIG1_HDMI_ACR_STATUS_1_BASE_IDX 2 10217 #define regDIG1_AFMT_CNTL 0x21af 10218 #define regDIG1_AFMT_CNTL_BASE_IDX 2 10219 #define regDIG1_DIG_BE_CNTL 0x21b0 10220 #define regDIG1_DIG_BE_CNTL_BASE_IDX 2 10221 #define regDIG1_DIG_BE_EN_CNTL 0x21b1 10222 #define regDIG1_DIG_BE_EN_CNTL_BASE_IDX 2 10223 #define regDIG1_TMDS_CNTL 0x21d7 10224 #define regDIG1_TMDS_CNTL_BASE_IDX 2 10225 #define regDIG1_TMDS_CONTROL_CHAR 0x21d8 10226 #define regDIG1_TMDS_CONTROL_CHAR_BASE_IDX 2 10227 #define regDIG1_TMDS_CONTROL0_FEEDBACK 0x21d9 10228 #define regDIG1_TMDS_CONTROL0_FEEDBACK_BASE_IDX 2 10229 #define regDIG1_TMDS_STEREOSYNC_CTL_SEL 0x21da 10230 #define regDIG1_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX 2 10231 #define regDIG1_TMDS_SYNC_CHAR_PATTERN_0_1 0x21db 10232 #define regDIG1_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX 2 10233 #define regDIG1_TMDS_SYNC_CHAR_PATTERN_2_3 0x21dc 10234 #define regDIG1_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX 2 10235 #define regDIG1_TMDS_CTL_BITS 0x21de 10236 #define regDIG1_TMDS_CTL_BITS_BASE_IDX 2 10237 #define regDIG1_TMDS_DCBALANCER_CONTROL 0x21df 10238 #define regDIG1_TMDS_DCBALANCER_CONTROL_BASE_IDX 2 10239 #define regDIG1_TMDS_SYNC_DCBALANCE_CHAR 0x21e0 10240 #define regDIG1_TMDS_SYNC_DCBALANCE_CHAR_BASE_IDX 2 10241 #define regDIG1_TMDS_CTL0_1_GEN_CNTL 0x21e1 10242 #define regDIG1_TMDS_CTL0_1_GEN_CNTL_BASE_IDX 2 10243 #define regDIG1_TMDS_CTL2_3_GEN_CNTL 0x21e2 10244 #define regDIG1_TMDS_CTL2_3_GEN_CNTL_BASE_IDX 2 10245 #define regDIG1_DIG_VERSION 0x21e4 10246 #define regDIG1_DIG_VERSION_BASE_IDX 2 10247 #define regDIG1_FORCE_DIG_DISABLE 0x21e5 10248 #define regDIG1_FORCE_DIG_DISABLE_BASE_IDX 2 10249 10250 10251 // addressBlock: dce_dc_dio_dp2_dispdec 10252 // base address: 0x800 10253 #define regDP2_DP_LINK_CNTL 0x2308 10254 #define regDP2_DP_LINK_CNTL_BASE_IDX 2 10255 #define regDP2_DP_PIXEL_FORMAT 0x2309 10256 #define regDP2_DP_PIXEL_FORMAT_BASE_IDX 2 10257 #define regDP2_DP_MSA_COLORIMETRY 0x230a 10258 #define regDP2_DP_MSA_COLORIMETRY_BASE_IDX 2 10259 #define regDP2_DP_CONFIG 0x230b 10260 #define regDP2_DP_CONFIG_BASE_IDX 2 10261 #define regDP2_DP_VID_STREAM_CNTL 0x230c 10262 #define regDP2_DP_VID_STREAM_CNTL_BASE_IDX 2 10263 #define regDP2_DP_STEER_FIFO 0x230d 10264 #define regDP2_DP_STEER_FIFO_BASE_IDX 2 10265 #define regDP2_DP_MSA_MISC 0x230e 10266 #define regDP2_DP_MSA_MISC_BASE_IDX 2 10267 #define regDP2_DP_DPHY_INTERNAL_CTRL 0x230f 10268 #define regDP2_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 10269 #define regDP2_DP_VID_TIMING 0x2310 10270 #define regDP2_DP_VID_TIMING_BASE_IDX 2 10271 #define regDP2_DP_VID_N 0x2311 10272 #define regDP2_DP_VID_N_BASE_IDX 2 10273 #define regDP2_DP_VID_M 0x2312 10274 #define regDP2_DP_VID_M_BASE_IDX 2 10275 #define regDP2_DP_LINK_FRAMING_CNTL 0x2313 10276 #define regDP2_DP_LINK_FRAMING_CNTL_BASE_IDX 2 10277 #define regDP2_DP_HBR2_EYE_PATTERN 0x2314 10278 #define regDP2_DP_HBR2_EYE_PATTERN_BASE_IDX 2 10279 #define regDP2_DP_VID_MSA_VBID 0x2315 10280 #define regDP2_DP_VID_MSA_VBID_BASE_IDX 2 10281 #define regDP2_DP_VID_INTERRUPT_CNTL 0x2316 10282 #define regDP2_DP_VID_INTERRUPT_CNTL_BASE_IDX 2 10283 #define regDP2_DP_DPHY_CNTL 0x2317 10284 #define regDP2_DP_DPHY_CNTL_BASE_IDX 2 10285 #define regDP2_DP_DPHY_TRAINING_PATTERN_SEL 0x2318 10286 #define regDP2_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX 2 10287 #define regDP2_DP_DPHY_SYM0 0x2319 10288 #define regDP2_DP_DPHY_SYM0_BASE_IDX 2 10289 #define regDP2_DP_DPHY_SYM1 0x231a 10290 #define regDP2_DP_DPHY_SYM1_BASE_IDX 2 10291 #define regDP2_DP_DPHY_SYM2 0x231b 10292 #define regDP2_DP_DPHY_SYM2_BASE_IDX 2 10293 #define regDP2_DP_DPHY_8B10B_CNTL 0x231c 10294 #define regDP2_DP_DPHY_8B10B_CNTL_BASE_IDX 2 10295 #define regDP2_DP_DPHY_PRBS_CNTL 0x231d 10296 #define regDP2_DP_DPHY_PRBS_CNTL_BASE_IDX 2 10297 #define regDP2_DP_DPHY_SCRAM_CNTL 0x231e 10298 #define regDP2_DP_DPHY_SCRAM_CNTL_BASE_IDX 2 10299 #define regDP2_DP_DPHY_CRC_EN 0x231f 10300 #define regDP2_DP_DPHY_CRC_EN_BASE_IDX 2 10301 #define regDP2_DP_DPHY_CRC_CNTL 0x2320 10302 #define regDP2_DP_DPHY_CRC_CNTL_BASE_IDX 2 10303 #define regDP2_DP_DPHY_CRC_RESULT 0x2321 10304 #define regDP2_DP_DPHY_CRC_RESULT_BASE_IDX 2 10305 #define regDP2_DP_DPHY_CRC_MST_CNTL 0x2322 10306 #define regDP2_DP_DPHY_CRC_MST_CNTL_BASE_IDX 2 10307 #define regDP2_DP_DPHY_CRC_MST_STATUS 0x2323 10308 #define regDP2_DP_DPHY_CRC_MST_STATUS_BASE_IDX 2 10309 #define regDP2_DP_DPHY_FAST_TRAINING 0x2324 10310 #define regDP2_DP_DPHY_FAST_TRAINING_BASE_IDX 2 10311 #define regDP2_DP_DPHY_FAST_TRAINING_STATUS 0x2325 10312 #define regDP2_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX 2 10313 #define regDP2_DP_SEC_CNTL 0x232b 10314 #define regDP2_DP_SEC_CNTL_BASE_IDX 2 10315 #define regDP2_DP_SEC_CNTL1 0x232c 10316 #define regDP2_DP_SEC_CNTL1_BASE_IDX 2 10317 #define regDP2_DP_SEC_FRAMING1 0x232d 10318 #define regDP2_DP_SEC_FRAMING1_BASE_IDX 2 10319 #define regDP2_DP_SEC_FRAMING2 0x232e 10320 #define regDP2_DP_SEC_FRAMING2_BASE_IDX 2 10321 #define regDP2_DP_SEC_FRAMING3 0x232f 10322 #define regDP2_DP_SEC_FRAMING3_BASE_IDX 2 10323 #define regDP2_DP_SEC_FRAMING4 0x2330 10324 #define regDP2_DP_SEC_FRAMING4_BASE_IDX 2 10325 #define regDP2_DP_SEC_AUD_N 0x2331 10326 #define regDP2_DP_SEC_AUD_N_BASE_IDX 2 10327 #define regDP2_DP_SEC_AUD_N_READBACK 0x2332 10328 #define regDP2_DP_SEC_AUD_N_READBACK_BASE_IDX 2 10329 #define regDP2_DP_SEC_AUD_M 0x2333 10330 #define regDP2_DP_SEC_AUD_M_BASE_IDX 2 10331 #define regDP2_DP_SEC_AUD_M_READBACK 0x2334 10332 #define regDP2_DP_SEC_AUD_M_READBACK_BASE_IDX 2 10333 #define regDP2_DP_SEC_TIMESTAMP 0x2335 10334 #define regDP2_DP_SEC_TIMESTAMP_BASE_IDX 2 10335 #define regDP2_DP_SEC_PACKET_CNTL 0x2336 10336 #define regDP2_DP_SEC_PACKET_CNTL_BASE_IDX 2 10337 #define regDP2_DP_MSE_RATE_CNTL 0x2337 10338 #define regDP2_DP_MSE_RATE_CNTL_BASE_IDX 2 10339 #define regDP2_DP_MSE_RATE_UPDATE 0x2339 10340 #define regDP2_DP_MSE_RATE_UPDATE_BASE_IDX 2 10341 #define regDP2_DP_MSE_SAT0 0x233a 10342 #define regDP2_DP_MSE_SAT0_BASE_IDX 2 10343 #define regDP2_DP_MSE_SAT1 0x233b 10344 #define regDP2_DP_MSE_SAT1_BASE_IDX 2 10345 #define regDP2_DP_MSE_SAT2 0x233c 10346 #define regDP2_DP_MSE_SAT2_BASE_IDX 2 10347 #define regDP2_DP_MSE_SAT_UPDATE 0x233d 10348 #define regDP2_DP_MSE_SAT_UPDATE_BASE_IDX 2 10349 #define regDP2_DP_MSE_LINK_TIMING 0x233e 10350 #define regDP2_DP_MSE_LINK_TIMING_BASE_IDX 2 10351 #define regDP2_DP_MSE_MISC_CNTL 0x233f 10352 #define regDP2_DP_MSE_MISC_CNTL_BASE_IDX 2 10353 #define regDP2_DP_DPHY_BS_SR_SWAP_CNTL 0x2344 10354 #define regDP2_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX 2 10355 #define regDP2_DP_DPHY_HBR2_PATTERN_CONTROL 0x2345 10356 #define regDP2_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX 2 10357 #define regDP2_DP_MSE_SAT0_STATUS 0x2347 10358 #define regDP2_DP_MSE_SAT0_STATUS_BASE_IDX 2 10359 #define regDP2_DP_MSE_SAT1_STATUS 0x2348 10360 #define regDP2_DP_MSE_SAT1_STATUS_BASE_IDX 2 10361 #define regDP2_DP_MSE_SAT2_STATUS 0x2349 10362 #define regDP2_DP_MSE_SAT2_STATUS_BASE_IDX 2 10363 #define regDP2_DP_MSA_TIMING_PARAM1 0x234c 10364 #define regDP2_DP_MSA_TIMING_PARAM1_BASE_IDX 2 10365 #define regDP2_DP_MSA_TIMING_PARAM2 0x234d 10366 #define regDP2_DP_MSA_TIMING_PARAM2_BASE_IDX 2 10367 #define regDP2_DP_MSA_TIMING_PARAM3 0x234e 10368 #define regDP2_DP_MSA_TIMING_PARAM3_BASE_IDX 2 10369 #define regDP2_DP_MSA_TIMING_PARAM4 0x234f 10370 #define regDP2_DP_MSA_TIMING_PARAM4_BASE_IDX 2 10371 #define regDP2_DP_MSO_CNTL 0x2350 10372 #define regDP2_DP_MSO_CNTL_BASE_IDX 2 10373 #define regDP2_DP_MSO_CNTL1 0x2351 10374 #define regDP2_DP_MSO_CNTL1_BASE_IDX 2 10375 #define regDP2_DP_DSC_CNTL 0x2352 10376 #define regDP2_DP_DSC_CNTL_BASE_IDX 2 10377 #define regDP2_DP_SEC_CNTL2 0x2353 10378 #define regDP2_DP_SEC_CNTL2_BASE_IDX 2 10379 #define regDP2_DP_SEC_CNTL3 0x2354 10380 #define regDP2_DP_SEC_CNTL3_BASE_IDX 2 10381 #define regDP2_DP_SEC_CNTL4 0x2355 10382 #define regDP2_DP_SEC_CNTL4_BASE_IDX 2 10383 #define regDP2_DP_SEC_CNTL5 0x2356 10384 #define regDP2_DP_SEC_CNTL5_BASE_IDX 2 10385 #define regDP2_DP_SEC_CNTL6 0x2357 10386 #define regDP2_DP_SEC_CNTL6_BASE_IDX 2 10387 #define regDP2_DP_SEC_CNTL7 0x2358 10388 #define regDP2_DP_SEC_CNTL7_BASE_IDX 2 10389 #define regDP2_DP_DB_CNTL 0x2359 10390 #define regDP2_DP_DB_CNTL_BASE_IDX 2 10391 #define regDP2_DP_MSA_VBID_MISC 0x235a 10392 #define regDP2_DP_MSA_VBID_MISC_BASE_IDX 2 10393 #define regDP2_DP_SEC_METADATA_TRANSMISSION 0x235b 10394 #define regDP2_DP_SEC_METADATA_TRANSMISSION_BASE_IDX 2 10395 #define regDP2_DP_DSC_BYTES_PER_PIXEL 0x235c 10396 #define regDP2_DP_DSC_BYTES_PER_PIXEL_BASE_IDX 2 10397 #define regDP2_DP_ALPM_CNTL 0x235d 10398 #define regDP2_DP_ALPM_CNTL_BASE_IDX 2 10399 #define regDP2_DP_GSP8_CNTL 0x235e 10400 #define regDP2_DP_GSP8_CNTL_BASE_IDX 2 10401 #define regDP2_DP_GSP9_CNTL 0x235f 10402 #define regDP2_DP_GSP9_CNTL_BASE_IDX 2 10403 #define regDP2_DP_GSP10_CNTL 0x2360 10404 #define regDP2_DP_GSP10_CNTL_BASE_IDX 2 10405 #define regDP2_DP_GSP11_CNTL 0x2361 10406 #define regDP2_DP_GSP11_CNTL_BASE_IDX 2 10407 #define regDP2_DP_GSP_EN_DB_STATUS 0x2362 10408 #define regDP2_DP_GSP_EN_DB_STATUS_BASE_IDX 2 10409 10410 10411 // addressBlock: dce_dc_dio_dig2_dispdec 10412 // base address: 0x800 10413 #define regDIG2_DIG_FE_CNTL 0x228b 10414 #define regDIG2_DIG_FE_CNTL_BASE_IDX 2 10415 #define regDIG2_DIG_OUTPUT_CRC_CNTL 0x228c 10416 #define regDIG2_DIG_OUTPUT_CRC_CNTL_BASE_IDX 2 10417 #define regDIG2_DIG_OUTPUT_CRC_RESULT 0x228d 10418 #define regDIG2_DIG_OUTPUT_CRC_RESULT_BASE_IDX 2 10419 #define regDIG2_DIG_CLOCK_PATTERN 0x228e 10420 #define regDIG2_DIG_CLOCK_PATTERN_BASE_IDX 2 10421 #define regDIG2_DIG_TEST_PATTERN 0x228f 10422 #define regDIG2_DIG_TEST_PATTERN_BASE_IDX 2 10423 #define regDIG2_DIG_RANDOM_PATTERN_SEED 0x2290 10424 #define regDIG2_DIG_RANDOM_PATTERN_SEED_BASE_IDX 2 10425 #define regDIG2_DIG_FIFO_STATUS 0x2291 10426 #define regDIG2_DIG_FIFO_STATUS_BASE_IDX 2 10427 #define regDIG2_HDMI_METADATA_PACKET_CONTROL 0x2292 10428 #define regDIG2_HDMI_METADATA_PACKET_CONTROL_BASE_IDX 2 10429 #define regDIG2_HDMI_CONTROL 0x2293 10430 #define regDIG2_HDMI_CONTROL_BASE_IDX 2 10431 #define regDIG2_HDMI_STATUS 0x2294 10432 #define regDIG2_HDMI_STATUS_BASE_IDX 2 10433 #define regDIG2_HDMI_AUDIO_PACKET_CONTROL 0x2295 10434 #define regDIG2_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX 2 10435 #define regDIG2_HDMI_ACR_PACKET_CONTROL 0x2296 10436 #define regDIG2_HDMI_ACR_PACKET_CONTROL_BASE_IDX 2 10437 #define regDIG2_HDMI_VBI_PACKET_CONTROL 0x2297 10438 #define regDIG2_HDMI_VBI_PACKET_CONTROL_BASE_IDX 2 10439 #define regDIG2_HDMI_INFOFRAME_CONTROL0 0x2298 10440 #define regDIG2_HDMI_INFOFRAME_CONTROL0_BASE_IDX 2 10441 #define regDIG2_HDMI_INFOFRAME_CONTROL1 0x2299 10442 #define regDIG2_HDMI_INFOFRAME_CONTROL1_BASE_IDX 2 10443 #define regDIG2_HDMI_GENERIC_PACKET_CONTROL0 0x229a 10444 #define regDIG2_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX 2 10445 #define regDIG2_HDMI_GENERIC_PACKET_CONTROL6 0x229b 10446 #define regDIG2_HDMI_GENERIC_PACKET_CONTROL6_BASE_IDX 2 10447 #define regDIG2_HDMI_GENERIC_PACKET_CONTROL5 0x229c 10448 #define regDIG2_HDMI_GENERIC_PACKET_CONTROL5_BASE_IDX 2 10449 #define regDIG2_HDMI_GC 0x229d 10450 #define regDIG2_HDMI_GC_BASE_IDX 2 10451 #define regDIG2_HDMI_GENERIC_PACKET_CONTROL1 0x229e 10452 #define regDIG2_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX 2 10453 #define regDIG2_HDMI_GENERIC_PACKET_CONTROL2 0x229f 10454 #define regDIG2_HDMI_GENERIC_PACKET_CONTROL2_BASE_IDX 2 10455 #define regDIG2_HDMI_GENERIC_PACKET_CONTROL3 0x22a0 10456 #define regDIG2_HDMI_GENERIC_PACKET_CONTROL3_BASE_IDX 2 10457 #define regDIG2_HDMI_GENERIC_PACKET_CONTROL4 0x22a1 10458 #define regDIG2_HDMI_GENERIC_PACKET_CONTROL4_BASE_IDX 2 10459 #define regDIG2_HDMI_GENERIC_PACKET_CONTROL7 0x22a2 10460 #define regDIG2_HDMI_GENERIC_PACKET_CONTROL7_BASE_IDX 2 10461 #define regDIG2_HDMI_GENERIC_PACKET_CONTROL8 0x22a3 10462 #define regDIG2_HDMI_GENERIC_PACKET_CONTROL8_BASE_IDX 2 10463 #define regDIG2_HDMI_GENERIC_PACKET_CONTROL9 0x22a4 10464 #define regDIG2_HDMI_GENERIC_PACKET_CONTROL9_BASE_IDX 2 10465 #define regDIG2_HDMI_GENERIC_PACKET_CONTROL10 0x22a5 10466 #define regDIG2_HDMI_GENERIC_PACKET_CONTROL10_BASE_IDX 2 10467 #define regDIG2_HDMI_DB_CONTROL 0x22a6 10468 #define regDIG2_HDMI_DB_CONTROL_BASE_IDX 2 10469 #define regDIG2_HDMI_ACR_32_0 0x22a7 10470 #define regDIG2_HDMI_ACR_32_0_BASE_IDX 2 10471 #define regDIG2_HDMI_ACR_32_1 0x22a8 10472 #define regDIG2_HDMI_ACR_32_1_BASE_IDX 2 10473 #define regDIG2_HDMI_ACR_44_0 0x22a9 10474 #define regDIG2_HDMI_ACR_44_0_BASE_IDX 2 10475 #define regDIG2_HDMI_ACR_44_1 0x22aa 10476 #define regDIG2_HDMI_ACR_44_1_BASE_IDX 2 10477 #define regDIG2_HDMI_ACR_48_0 0x22ab 10478 #define regDIG2_HDMI_ACR_48_0_BASE_IDX 2 10479 #define regDIG2_HDMI_ACR_48_1 0x22ac 10480 #define regDIG2_HDMI_ACR_48_1_BASE_IDX 2 10481 #define regDIG2_HDMI_ACR_STATUS_0 0x22ad 10482 #define regDIG2_HDMI_ACR_STATUS_0_BASE_IDX 2 10483 #define regDIG2_HDMI_ACR_STATUS_1 0x22ae 10484 #define regDIG2_HDMI_ACR_STATUS_1_BASE_IDX 2 10485 #define regDIG2_AFMT_CNTL 0x22af 10486 #define regDIG2_AFMT_CNTL_BASE_IDX 2 10487 #define regDIG2_DIG_BE_CNTL 0x22b0 10488 #define regDIG2_DIG_BE_CNTL_BASE_IDX 2 10489 #define regDIG2_DIG_BE_EN_CNTL 0x22b1 10490 #define regDIG2_DIG_BE_EN_CNTL_BASE_IDX 2 10491 #define regDIG2_TMDS_CNTL 0x22d7 10492 #define regDIG2_TMDS_CNTL_BASE_IDX 2 10493 #define regDIG2_TMDS_CONTROL_CHAR 0x22d8 10494 #define regDIG2_TMDS_CONTROL_CHAR_BASE_IDX 2 10495 #define regDIG2_TMDS_CONTROL0_FEEDBACK 0x22d9 10496 #define regDIG2_TMDS_CONTROL0_FEEDBACK_BASE_IDX 2 10497 #define regDIG2_TMDS_STEREOSYNC_CTL_SEL 0x22da 10498 #define regDIG2_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX 2 10499 #define regDIG2_TMDS_SYNC_CHAR_PATTERN_0_1 0x22db 10500 #define regDIG2_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX 2 10501 #define regDIG2_TMDS_SYNC_CHAR_PATTERN_2_3 0x22dc 10502 #define regDIG2_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX 2 10503 #define regDIG2_TMDS_CTL_BITS 0x22de 10504 #define regDIG2_TMDS_CTL_BITS_BASE_IDX 2 10505 #define regDIG2_TMDS_DCBALANCER_CONTROL 0x22df 10506 #define regDIG2_TMDS_DCBALANCER_CONTROL_BASE_IDX 2 10507 #define regDIG2_TMDS_SYNC_DCBALANCE_CHAR 0x22e0 10508 #define regDIG2_TMDS_SYNC_DCBALANCE_CHAR_BASE_IDX 2 10509 #define regDIG2_TMDS_CTL0_1_GEN_CNTL 0x22e1 10510 #define regDIG2_TMDS_CTL0_1_GEN_CNTL_BASE_IDX 2 10511 #define regDIG2_TMDS_CTL2_3_GEN_CNTL 0x22e2 10512 #define regDIG2_TMDS_CTL2_3_GEN_CNTL_BASE_IDX 2 10513 #define regDIG2_DIG_VERSION 0x22e4 10514 #define regDIG2_DIG_VERSION_BASE_IDX 2 10515 #define regDIG2_FORCE_DIG_DISABLE 0x22e5 10516 #define regDIG2_FORCE_DIG_DISABLE_BASE_IDX 2 10517 10518 10519 // addressBlock: dce_dc_dio_dp3_dispdec 10520 // base address: 0xc00 10521 #define regDP3_DP_LINK_CNTL 0x2408 10522 #define regDP3_DP_LINK_CNTL_BASE_IDX 2 10523 #define regDP3_DP_PIXEL_FORMAT 0x2409 10524 #define regDP3_DP_PIXEL_FORMAT_BASE_IDX 2 10525 #define regDP3_DP_MSA_COLORIMETRY 0x240a 10526 #define regDP3_DP_MSA_COLORIMETRY_BASE_IDX 2 10527 #define regDP3_DP_CONFIG 0x240b 10528 #define regDP3_DP_CONFIG_BASE_IDX 2 10529 #define regDP3_DP_VID_STREAM_CNTL 0x240c 10530 #define regDP3_DP_VID_STREAM_CNTL_BASE_IDX 2 10531 #define regDP3_DP_STEER_FIFO 0x240d 10532 #define regDP3_DP_STEER_FIFO_BASE_IDX 2 10533 #define regDP3_DP_MSA_MISC 0x240e 10534 #define regDP3_DP_MSA_MISC_BASE_IDX 2 10535 #define regDP3_DP_DPHY_INTERNAL_CTRL 0x240f 10536 #define regDP3_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 10537 #define regDP3_DP_VID_TIMING 0x2410 10538 #define regDP3_DP_VID_TIMING_BASE_IDX 2 10539 #define regDP3_DP_VID_N 0x2411 10540 #define regDP3_DP_VID_N_BASE_IDX 2 10541 #define regDP3_DP_VID_M 0x2412 10542 #define regDP3_DP_VID_M_BASE_IDX 2 10543 #define regDP3_DP_LINK_FRAMING_CNTL 0x2413 10544 #define regDP3_DP_LINK_FRAMING_CNTL_BASE_IDX 2 10545 #define regDP3_DP_HBR2_EYE_PATTERN 0x2414 10546 #define regDP3_DP_HBR2_EYE_PATTERN_BASE_IDX 2 10547 #define regDP3_DP_VID_MSA_VBID 0x2415 10548 #define regDP3_DP_VID_MSA_VBID_BASE_IDX 2 10549 #define regDP3_DP_VID_INTERRUPT_CNTL 0x2416 10550 #define regDP3_DP_VID_INTERRUPT_CNTL_BASE_IDX 2 10551 #define regDP3_DP_DPHY_CNTL 0x2417 10552 #define regDP3_DP_DPHY_CNTL_BASE_IDX 2 10553 #define regDP3_DP_DPHY_TRAINING_PATTERN_SEL 0x2418 10554 #define regDP3_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX 2 10555 #define regDP3_DP_DPHY_SYM0 0x2419 10556 #define regDP3_DP_DPHY_SYM0_BASE_IDX 2 10557 #define regDP3_DP_DPHY_SYM1 0x241a 10558 #define regDP3_DP_DPHY_SYM1_BASE_IDX 2 10559 #define regDP3_DP_DPHY_SYM2 0x241b 10560 #define regDP3_DP_DPHY_SYM2_BASE_IDX 2 10561 #define regDP3_DP_DPHY_8B10B_CNTL 0x241c 10562 #define regDP3_DP_DPHY_8B10B_CNTL_BASE_IDX 2 10563 #define regDP3_DP_DPHY_PRBS_CNTL 0x241d 10564 #define regDP3_DP_DPHY_PRBS_CNTL_BASE_IDX 2 10565 #define regDP3_DP_DPHY_SCRAM_CNTL 0x241e 10566 #define regDP3_DP_DPHY_SCRAM_CNTL_BASE_IDX 2 10567 #define regDP3_DP_DPHY_CRC_EN 0x241f 10568 #define regDP3_DP_DPHY_CRC_EN_BASE_IDX 2 10569 #define regDP3_DP_DPHY_CRC_CNTL 0x2420 10570 #define regDP3_DP_DPHY_CRC_CNTL_BASE_IDX 2 10571 #define regDP3_DP_DPHY_CRC_RESULT 0x2421 10572 #define regDP3_DP_DPHY_CRC_RESULT_BASE_IDX 2 10573 #define regDP3_DP_DPHY_CRC_MST_CNTL 0x2422 10574 #define regDP3_DP_DPHY_CRC_MST_CNTL_BASE_IDX 2 10575 #define regDP3_DP_DPHY_CRC_MST_STATUS 0x2423 10576 #define regDP3_DP_DPHY_CRC_MST_STATUS_BASE_IDX 2 10577 #define regDP3_DP_DPHY_FAST_TRAINING 0x2424 10578 #define regDP3_DP_DPHY_FAST_TRAINING_BASE_IDX 2 10579 #define regDP3_DP_DPHY_FAST_TRAINING_STATUS 0x2425 10580 #define regDP3_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX 2 10581 #define regDP3_DP_SEC_CNTL 0x242b 10582 #define regDP3_DP_SEC_CNTL_BASE_IDX 2 10583 #define regDP3_DP_SEC_CNTL1 0x242c 10584 #define regDP3_DP_SEC_CNTL1_BASE_IDX 2 10585 #define regDP3_DP_SEC_FRAMING1 0x242d 10586 #define regDP3_DP_SEC_FRAMING1_BASE_IDX 2 10587 #define regDP3_DP_SEC_FRAMING2 0x242e 10588 #define regDP3_DP_SEC_FRAMING2_BASE_IDX 2 10589 #define regDP3_DP_SEC_FRAMING3 0x242f 10590 #define regDP3_DP_SEC_FRAMING3_BASE_IDX 2 10591 #define regDP3_DP_SEC_FRAMING4 0x2430 10592 #define regDP3_DP_SEC_FRAMING4_BASE_IDX 2 10593 #define regDP3_DP_SEC_AUD_N 0x2431 10594 #define regDP3_DP_SEC_AUD_N_BASE_IDX 2 10595 #define regDP3_DP_SEC_AUD_N_READBACK 0x2432 10596 #define regDP3_DP_SEC_AUD_N_READBACK_BASE_IDX 2 10597 #define regDP3_DP_SEC_AUD_M 0x2433 10598 #define regDP3_DP_SEC_AUD_M_BASE_IDX 2 10599 #define regDP3_DP_SEC_AUD_M_READBACK 0x2434 10600 #define regDP3_DP_SEC_AUD_M_READBACK_BASE_IDX 2 10601 #define regDP3_DP_SEC_TIMESTAMP 0x2435 10602 #define regDP3_DP_SEC_TIMESTAMP_BASE_IDX 2 10603 #define regDP3_DP_SEC_PACKET_CNTL 0x2436 10604 #define regDP3_DP_SEC_PACKET_CNTL_BASE_IDX 2 10605 #define regDP3_DP_MSE_RATE_CNTL 0x2437 10606 #define regDP3_DP_MSE_RATE_CNTL_BASE_IDX 2 10607 #define regDP3_DP_MSE_RATE_UPDATE 0x2439 10608 #define regDP3_DP_MSE_RATE_UPDATE_BASE_IDX 2 10609 #define regDP3_DP_MSE_SAT0 0x243a 10610 #define regDP3_DP_MSE_SAT0_BASE_IDX 2 10611 #define regDP3_DP_MSE_SAT1 0x243b 10612 #define regDP3_DP_MSE_SAT1_BASE_IDX 2 10613 #define regDP3_DP_MSE_SAT2 0x243c 10614 #define regDP3_DP_MSE_SAT2_BASE_IDX 2 10615 #define regDP3_DP_MSE_SAT_UPDATE 0x243d 10616 #define regDP3_DP_MSE_SAT_UPDATE_BASE_IDX 2 10617 #define regDP3_DP_MSE_LINK_TIMING 0x243e 10618 #define regDP3_DP_MSE_LINK_TIMING_BASE_IDX 2 10619 #define regDP3_DP_MSE_MISC_CNTL 0x243f 10620 #define regDP3_DP_MSE_MISC_CNTL_BASE_IDX 2 10621 #define regDP3_DP_DPHY_BS_SR_SWAP_CNTL 0x2444 10622 #define regDP3_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX 2 10623 #define regDP3_DP_DPHY_HBR2_PATTERN_CONTROL 0x2445 10624 #define regDP3_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX 2 10625 #define regDP3_DP_MSE_SAT0_STATUS 0x2447 10626 #define regDP3_DP_MSE_SAT0_STATUS_BASE_IDX 2 10627 #define regDP3_DP_MSE_SAT1_STATUS 0x2448 10628 #define regDP3_DP_MSE_SAT1_STATUS_BASE_IDX 2 10629 #define regDP3_DP_MSE_SAT2_STATUS 0x2449 10630 #define regDP3_DP_MSE_SAT2_STATUS_BASE_IDX 2 10631 #define regDP3_DP_MSA_TIMING_PARAM1 0x244c 10632 #define regDP3_DP_MSA_TIMING_PARAM1_BASE_IDX 2 10633 #define regDP3_DP_MSA_TIMING_PARAM2 0x244d 10634 #define regDP3_DP_MSA_TIMING_PARAM2_BASE_IDX 2 10635 #define regDP3_DP_MSA_TIMING_PARAM3 0x244e 10636 #define regDP3_DP_MSA_TIMING_PARAM3_BASE_IDX 2 10637 #define regDP3_DP_MSA_TIMING_PARAM4 0x244f 10638 #define regDP3_DP_MSA_TIMING_PARAM4_BASE_IDX 2 10639 #define regDP3_DP_MSO_CNTL 0x2450 10640 #define regDP3_DP_MSO_CNTL_BASE_IDX 2 10641 #define regDP3_DP_MSO_CNTL1 0x2451 10642 #define regDP3_DP_MSO_CNTL1_BASE_IDX 2 10643 #define regDP3_DP_DSC_CNTL 0x2452 10644 #define regDP3_DP_DSC_CNTL_BASE_IDX 2 10645 #define regDP3_DP_SEC_CNTL2 0x2453 10646 #define regDP3_DP_SEC_CNTL2_BASE_IDX 2 10647 #define regDP3_DP_SEC_CNTL3 0x2454 10648 #define regDP3_DP_SEC_CNTL3_BASE_IDX 2 10649 #define regDP3_DP_SEC_CNTL4 0x2455 10650 #define regDP3_DP_SEC_CNTL4_BASE_IDX 2 10651 #define regDP3_DP_SEC_CNTL5 0x2456 10652 #define regDP3_DP_SEC_CNTL5_BASE_IDX 2 10653 #define regDP3_DP_SEC_CNTL6 0x2457 10654 #define regDP3_DP_SEC_CNTL6_BASE_IDX 2 10655 #define regDP3_DP_SEC_CNTL7 0x2458 10656 #define regDP3_DP_SEC_CNTL7_BASE_IDX 2 10657 #define regDP3_DP_DB_CNTL 0x2459 10658 #define regDP3_DP_DB_CNTL_BASE_IDX 2 10659 #define regDP3_DP_MSA_VBID_MISC 0x245a 10660 #define regDP3_DP_MSA_VBID_MISC_BASE_IDX 2 10661 #define regDP3_DP_SEC_METADATA_TRANSMISSION 0x245b 10662 #define regDP3_DP_SEC_METADATA_TRANSMISSION_BASE_IDX 2 10663 #define regDP3_DP_DSC_BYTES_PER_PIXEL 0x245c 10664 #define regDP3_DP_DSC_BYTES_PER_PIXEL_BASE_IDX 2 10665 #define regDP3_DP_ALPM_CNTL 0x245d 10666 #define regDP3_DP_ALPM_CNTL_BASE_IDX 2 10667 #define regDP3_DP_GSP8_CNTL 0x245e 10668 #define regDP3_DP_GSP8_CNTL_BASE_IDX 2 10669 #define regDP3_DP_GSP9_CNTL 0x245f 10670 #define regDP3_DP_GSP9_CNTL_BASE_IDX 2 10671 #define regDP3_DP_GSP10_CNTL 0x2460 10672 #define regDP3_DP_GSP10_CNTL_BASE_IDX 2 10673 #define regDP3_DP_GSP11_CNTL 0x2461 10674 #define regDP3_DP_GSP11_CNTL_BASE_IDX 2 10675 #define regDP3_DP_GSP_EN_DB_STATUS 0x2462 10676 #define regDP3_DP_GSP_EN_DB_STATUS_BASE_IDX 2 10677 10678 10679 // addressBlock: dce_dc_dio_dig3_dispdec 10680 // base address: 0xc00 10681 #define regDIG3_DIG_FE_CNTL 0x238b 10682 #define regDIG3_DIG_FE_CNTL_BASE_IDX 2 10683 #define regDIG3_DIG_OUTPUT_CRC_CNTL 0x238c 10684 #define regDIG3_DIG_OUTPUT_CRC_CNTL_BASE_IDX 2 10685 #define regDIG3_DIG_OUTPUT_CRC_RESULT 0x238d 10686 #define regDIG3_DIG_OUTPUT_CRC_RESULT_BASE_IDX 2 10687 #define regDIG3_DIG_CLOCK_PATTERN 0x238e 10688 #define regDIG3_DIG_CLOCK_PATTERN_BASE_IDX 2 10689 #define regDIG3_DIG_TEST_PATTERN 0x238f 10690 #define regDIG3_DIG_TEST_PATTERN_BASE_IDX 2 10691 #define regDIG3_DIG_RANDOM_PATTERN_SEED 0x2390 10692 #define regDIG3_DIG_RANDOM_PATTERN_SEED_BASE_IDX 2 10693 #define regDIG3_DIG_FIFO_STATUS 0x2391 10694 #define regDIG3_DIG_FIFO_STATUS_BASE_IDX 2 10695 #define regDIG3_HDMI_METADATA_PACKET_CONTROL 0x2392 10696 #define regDIG3_HDMI_METADATA_PACKET_CONTROL_BASE_IDX 2 10697 #define regDIG3_HDMI_CONTROL 0x2393 10698 #define regDIG3_HDMI_CONTROL_BASE_IDX 2 10699 #define regDIG3_HDMI_STATUS 0x2394 10700 #define regDIG3_HDMI_STATUS_BASE_IDX 2 10701 #define regDIG3_HDMI_AUDIO_PACKET_CONTROL 0x2395 10702 #define regDIG3_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX 2 10703 #define regDIG3_HDMI_ACR_PACKET_CONTROL 0x2396 10704 #define regDIG3_HDMI_ACR_PACKET_CONTROL_BASE_IDX 2 10705 #define regDIG3_HDMI_VBI_PACKET_CONTROL 0x2397 10706 #define regDIG3_HDMI_VBI_PACKET_CONTROL_BASE_IDX 2 10707 #define regDIG3_HDMI_INFOFRAME_CONTROL0 0x2398 10708 #define regDIG3_HDMI_INFOFRAME_CONTROL0_BASE_IDX 2 10709 #define regDIG3_HDMI_INFOFRAME_CONTROL1 0x2399 10710 #define regDIG3_HDMI_INFOFRAME_CONTROL1_BASE_IDX 2 10711 #define regDIG3_HDMI_GENERIC_PACKET_CONTROL0 0x239a 10712 #define regDIG3_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX 2 10713 #define regDIG3_HDMI_GENERIC_PACKET_CONTROL6 0x239b 10714 #define regDIG3_HDMI_GENERIC_PACKET_CONTROL6_BASE_IDX 2 10715 #define regDIG3_HDMI_GENERIC_PACKET_CONTROL5 0x239c 10716 #define regDIG3_HDMI_GENERIC_PACKET_CONTROL5_BASE_IDX 2 10717 #define regDIG3_HDMI_GC 0x239d 10718 #define regDIG3_HDMI_GC_BASE_IDX 2 10719 #define regDIG3_HDMI_GENERIC_PACKET_CONTROL1 0x239e 10720 #define regDIG3_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX 2 10721 #define regDIG3_HDMI_GENERIC_PACKET_CONTROL2 0x239f 10722 #define regDIG3_HDMI_GENERIC_PACKET_CONTROL2_BASE_IDX 2 10723 #define regDIG3_HDMI_GENERIC_PACKET_CONTROL3 0x23a0 10724 #define regDIG3_HDMI_GENERIC_PACKET_CONTROL3_BASE_IDX 2 10725 #define regDIG3_HDMI_GENERIC_PACKET_CONTROL4 0x23a1 10726 #define regDIG3_HDMI_GENERIC_PACKET_CONTROL4_BASE_IDX 2 10727 #define regDIG3_HDMI_GENERIC_PACKET_CONTROL7 0x23a2 10728 #define regDIG3_HDMI_GENERIC_PACKET_CONTROL7_BASE_IDX 2 10729 #define regDIG3_HDMI_GENERIC_PACKET_CONTROL8 0x23a3 10730 #define regDIG3_HDMI_GENERIC_PACKET_CONTROL8_BASE_IDX 2 10731 #define regDIG3_HDMI_GENERIC_PACKET_CONTROL9 0x23a4 10732 #define regDIG3_HDMI_GENERIC_PACKET_CONTROL9_BASE_IDX 2 10733 #define regDIG3_HDMI_GENERIC_PACKET_CONTROL10 0x23a5 10734 #define regDIG3_HDMI_GENERIC_PACKET_CONTROL10_BASE_IDX 2 10735 #define regDIG3_HDMI_DB_CONTROL 0x23a6 10736 #define regDIG3_HDMI_DB_CONTROL_BASE_IDX 2 10737 #define regDIG3_HDMI_ACR_32_0 0x23a7 10738 #define regDIG3_HDMI_ACR_32_0_BASE_IDX 2 10739 #define regDIG3_HDMI_ACR_32_1 0x23a8 10740 #define regDIG3_HDMI_ACR_32_1_BASE_IDX 2 10741 #define regDIG3_HDMI_ACR_44_0 0x23a9 10742 #define regDIG3_HDMI_ACR_44_0_BASE_IDX 2 10743 #define regDIG3_HDMI_ACR_44_1 0x23aa 10744 #define regDIG3_HDMI_ACR_44_1_BASE_IDX 2 10745 #define regDIG3_HDMI_ACR_48_0 0x23ab 10746 #define regDIG3_HDMI_ACR_48_0_BASE_IDX 2 10747 #define regDIG3_HDMI_ACR_48_1 0x23ac 10748 #define regDIG3_HDMI_ACR_48_1_BASE_IDX 2 10749 #define regDIG3_HDMI_ACR_STATUS_0 0x23ad 10750 #define regDIG3_HDMI_ACR_STATUS_0_BASE_IDX 2 10751 #define regDIG3_HDMI_ACR_STATUS_1 0x23ae 10752 #define regDIG3_HDMI_ACR_STATUS_1_BASE_IDX 2 10753 #define regDIG3_AFMT_CNTL 0x23af 10754 #define regDIG3_AFMT_CNTL_BASE_IDX 2 10755 #define regDIG3_DIG_BE_CNTL 0x23b0 10756 #define regDIG3_DIG_BE_CNTL_BASE_IDX 2 10757 #define regDIG3_DIG_BE_EN_CNTL 0x23b1 10758 #define regDIG3_DIG_BE_EN_CNTL_BASE_IDX 2 10759 #define regDIG3_TMDS_CNTL 0x23d7 10760 #define regDIG3_TMDS_CNTL_BASE_IDX 2 10761 #define regDIG3_TMDS_CONTROL_CHAR 0x23d8 10762 #define regDIG3_TMDS_CONTROL_CHAR_BASE_IDX 2 10763 #define regDIG3_TMDS_CONTROL0_FEEDBACK 0x23d9 10764 #define regDIG3_TMDS_CONTROL0_FEEDBACK_BASE_IDX 2 10765 #define regDIG3_TMDS_STEREOSYNC_CTL_SEL 0x23da 10766 #define regDIG3_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX 2 10767 #define regDIG3_TMDS_SYNC_CHAR_PATTERN_0_1 0x23db 10768 #define regDIG3_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX 2 10769 #define regDIG3_TMDS_SYNC_CHAR_PATTERN_2_3 0x23dc 10770 #define regDIG3_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX 2 10771 #define regDIG3_TMDS_CTL_BITS 0x23de 10772 #define regDIG3_TMDS_CTL_BITS_BASE_IDX 2 10773 #define regDIG3_TMDS_DCBALANCER_CONTROL 0x23df 10774 #define regDIG3_TMDS_DCBALANCER_CONTROL_BASE_IDX 2 10775 #define regDIG3_TMDS_SYNC_DCBALANCE_CHAR 0x23e0 10776 #define regDIG3_TMDS_SYNC_DCBALANCE_CHAR_BASE_IDX 2 10777 #define regDIG3_TMDS_CTL0_1_GEN_CNTL 0x23e1 10778 #define regDIG3_TMDS_CTL0_1_GEN_CNTL_BASE_IDX 2 10779 #define regDIG3_TMDS_CTL2_3_GEN_CNTL 0x23e2 10780 #define regDIG3_TMDS_CTL2_3_GEN_CNTL_BASE_IDX 2 10781 #define regDIG3_DIG_VERSION 0x23e4 10782 #define regDIG3_DIG_VERSION_BASE_IDX 2 10783 #define regDIG3_FORCE_DIG_DISABLE 0x23e5 10784 #define regDIG3_FORCE_DIG_DISABLE_BASE_IDX 2 10785 10786 10787 // addressBlock: dce_dc_dio_dp4_dispdec 10788 // base address: 0x1000 10789 #define regDP4_DP_LINK_CNTL 0x2508 10790 #define regDP4_DP_LINK_CNTL_BASE_IDX 2 10791 #define regDP4_DP_PIXEL_FORMAT 0x2509 10792 #define regDP4_DP_PIXEL_FORMAT_BASE_IDX 2 10793 #define regDP4_DP_MSA_COLORIMETRY 0x250a 10794 #define regDP4_DP_MSA_COLORIMETRY_BASE_IDX 2 10795 #define regDP4_DP_CONFIG 0x250b 10796 #define regDP4_DP_CONFIG_BASE_IDX 2 10797 #define regDP4_DP_VID_STREAM_CNTL 0x250c 10798 #define regDP4_DP_VID_STREAM_CNTL_BASE_IDX 2 10799 #define regDP4_DP_STEER_FIFO 0x250d 10800 #define regDP4_DP_STEER_FIFO_BASE_IDX 2 10801 #define regDP4_DP_MSA_MISC 0x250e 10802 #define regDP4_DP_MSA_MISC_BASE_IDX 2 10803 #define regDP4_DP_DPHY_INTERNAL_CTRL 0x250f 10804 #define regDP4_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 10805 #define regDP4_DP_VID_TIMING 0x2510 10806 #define regDP4_DP_VID_TIMING_BASE_IDX 2 10807 #define regDP4_DP_VID_N 0x2511 10808 #define regDP4_DP_VID_N_BASE_IDX 2 10809 #define regDP4_DP_VID_M 0x2512 10810 #define regDP4_DP_VID_M_BASE_IDX 2 10811 #define regDP4_DP_LINK_FRAMING_CNTL 0x2513 10812 #define regDP4_DP_LINK_FRAMING_CNTL_BASE_IDX 2 10813 #define regDP4_DP_HBR2_EYE_PATTERN 0x2514 10814 #define regDP4_DP_HBR2_EYE_PATTERN_BASE_IDX 2 10815 #define regDP4_DP_VID_MSA_VBID 0x2515 10816 #define regDP4_DP_VID_MSA_VBID_BASE_IDX 2 10817 #define regDP4_DP_VID_INTERRUPT_CNTL 0x2516 10818 #define regDP4_DP_VID_INTERRUPT_CNTL_BASE_IDX 2 10819 #define regDP4_DP_DPHY_CNTL 0x2517 10820 #define regDP4_DP_DPHY_CNTL_BASE_IDX 2 10821 #define regDP4_DP_DPHY_TRAINING_PATTERN_SEL 0x2518 10822 #define regDP4_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX 2 10823 #define regDP4_DP_DPHY_SYM0 0x2519 10824 #define regDP4_DP_DPHY_SYM0_BASE_IDX 2 10825 #define regDP4_DP_DPHY_SYM1 0x251a 10826 #define regDP4_DP_DPHY_SYM1_BASE_IDX 2 10827 #define regDP4_DP_DPHY_SYM2 0x251b 10828 #define regDP4_DP_DPHY_SYM2_BASE_IDX 2 10829 #define regDP4_DP_DPHY_8B10B_CNTL 0x251c 10830 #define regDP4_DP_DPHY_8B10B_CNTL_BASE_IDX 2 10831 #define regDP4_DP_DPHY_PRBS_CNTL 0x251d 10832 #define regDP4_DP_DPHY_PRBS_CNTL_BASE_IDX 2 10833 #define regDP4_DP_DPHY_SCRAM_CNTL 0x251e 10834 #define regDP4_DP_DPHY_SCRAM_CNTL_BASE_IDX 2 10835 #define regDP4_DP_DPHY_CRC_EN 0x251f 10836 #define regDP4_DP_DPHY_CRC_EN_BASE_IDX 2 10837 #define regDP4_DP_DPHY_CRC_CNTL 0x2520 10838 #define regDP4_DP_DPHY_CRC_CNTL_BASE_IDX 2 10839 #define regDP4_DP_DPHY_CRC_RESULT 0x2521 10840 #define regDP4_DP_DPHY_CRC_RESULT_BASE_IDX 2 10841 #define regDP4_DP_DPHY_CRC_MST_CNTL 0x2522 10842 #define regDP4_DP_DPHY_CRC_MST_CNTL_BASE_IDX 2 10843 #define regDP4_DP_DPHY_CRC_MST_STATUS 0x2523 10844 #define regDP4_DP_DPHY_CRC_MST_STATUS_BASE_IDX 2 10845 #define regDP4_DP_DPHY_FAST_TRAINING 0x2524 10846 #define regDP4_DP_DPHY_FAST_TRAINING_BASE_IDX 2 10847 #define regDP4_DP_DPHY_FAST_TRAINING_STATUS 0x2525 10848 #define regDP4_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX 2 10849 #define regDP4_DP_SEC_CNTL 0x252b 10850 #define regDP4_DP_SEC_CNTL_BASE_IDX 2 10851 #define regDP4_DP_SEC_CNTL1 0x252c 10852 #define regDP4_DP_SEC_CNTL1_BASE_IDX 2 10853 #define regDP4_DP_SEC_FRAMING1 0x252d 10854 #define regDP4_DP_SEC_FRAMING1_BASE_IDX 2 10855 #define regDP4_DP_SEC_FRAMING2 0x252e 10856 #define regDP4_DP_SEC_FRAMING2_BASE_IDX 2 10857 #define regDP4_DP_SEC_FRAMING3 0x252f 10858 #define regDP4_DP_SEC_FRAMING3_BASE_IDX 2 10859 #define regDP4_DP_SEC_FRAMING4 0x2530 10860 #define regDP4_DP_SEC_FRAMING4_BASE_IDX 2 10861 #define regDP4_DP_SEC_AUD_N 0x2531 10862 #define regDP4_DP_SEC_AUD_N_BASE_IDX 2 10863 #define regDP4_DP_SEC_AUD_N_READBACK 0x2532 10864 #define regDP4_DP_SEC_AUD_N_READBACK_BASE_IDX 2 10865 #define regDP4_DP_SEC_AUD_M 0x2533 10866 #define regDP4_DP_SEC_AUD_M_BASE_IDX 2 10867 #define regDP4_DP_SEC_AUD_M_READBACK 0x2534 10868 #define regDP4_DP_SEC_AUD_M_READBACK_BASE_IDX 2 10869 #define regDP4_DP_SEC_TIMESTAMP 0x2535 10870 #define regDP4_DP_SEC_TIMESTAMP_BASE_IDX 2 10871 #define regDP4_DP_SEC_PACKET_CNTL 0x2536 10872 #define regDP4_DP_SEC_PACKET_CNTL_BASE_IDX 2 10873 #define regDP4_DP_MSE_RATE_CNTL 0x2537 10874 #define regDP4_DP_MSE_RATE_CNTL_BASE_IDX 2 10875 #define regDP4_DP_MSE_RATE_UPDATE 0x2539 10876 #define regDP4_DP_MSE_RATE_UPDATE_BASE_IDX 2 10877 #define regDP4_DP_MSE_SAT0 0x253a 10878 #define regDP4_DP_MSE_SAT0_BASE_IDX 2 10879 #define regDP4_DP_MSE_SAT1 0x253b 10880 #define regDP4_DP_MSE_SAT1_BASE_IDX 2 10881 #define regDP4_DP_MSE_SAT2 0x253c 10882 #define regDP4_DP_MSE_SAT2_BASE_IDX 2 10883 #define regDP4_DP_MSE_SAT_UPDATE 0x253d 10884 #define regDP4_DP_MSE_SAT_UPDATE_BASE_IDX 2 10885 #define regDP4_DP_MSE_LINK_TIMING 0x253e 10886 #define regDP4_DP_MSE_LINK_TIMING_BASE_IDX 2 10887 #define regDP4_DP_MSE_MISC_CNTL 0x253f 10888 #define regDP4_DP_MSE_MISC_CNTL_BASE_IDX 2 10889 #define regDP4_DP_DPHY_BS_SR_SWAP_CNTL 0x2544 10890 #define regDP4_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX 2 10891 #define regDP4_DP_DPHY_HBR2_PATTERN_CONTROL 0x2545 10892 #define regDP4_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX 2 10893 #define regDP4_DP_MSE_SAT0_STATUS 0x2547 10894 #define regDP4_DP_MSE_SAT0_STATUS_BASE_IDX 2 10895 #define regDP4_DP_MSE_SAT1_STATUS 0x2548 10896 #define regDP4_DP_MSE_SAT1_STATUS_BASE_IDX 2 10897 #define regDP4_DP_MSE_SAT2_STATUS 0x2549 10898 #define regDP4_DP_MSE_SAT2_STATUS_BASE_IDX 2 10899 #define regDP4_DP_MSA_TIMING_PARAM1 0x254c 10900 #define regDP4_DP_MSA_TIMING_PARAM1_BASE_IDX 2 10901 #define regDP4_DP_MSA_TIMING_PARAM2 0x254d 10902 #define regDP4_DP_MSA_TIMING_PARAM2_BASE_IDX 2 10903 #define regDP4_DP_MSA_TIMING_PARAM3 0x254e 10904 #define regDP4_DP_MSA_TIMING_PARAM3_BASE_IDX 2 10905 #define regDP4_DP_MSA_TIMING_PARAM4 0x254f 10906 #define regDP4_DP_MSA_TIMING_PARAM4_BASE_IDX 2 10907 #define regDP4_DP_MSO_CNTL 0x2550 10908 #define regDP4_DP_MSO_CNTL_BASE_IDX 2 10909 #define regDP4_DP_MSO_CNTL1 0x2551 10910 #define regDP4_DP_MSO_CNTL1_BASE_IDX 2 10911 #define regDP4_DP_DSC_CNTL 0x2552 10912 #define regDP4_DP_DSC_CNTL_BASE_IDX 2 10913 #define regDP4_DP_SEC_CNTL2 0x2553 10914 #define regDP4_DP_SEC_CNTL2_BASE_IDX 2 10915 #define regDP4_DP_SEC_CNTL3 0x2554 10916 #define regDP4_DP_SEC_CNTL3_BASE_IDX 2 10917 #define regDP4_DP_SEC_CNTL4 0x2555 10918 #define regDP4_DP_SEC_CNTL4_BASE_IDX 2 10919 #define regDP4_DP_SEC_CNTL5 0x2556 10920 #define regDP4_DP_SEC_CNTL5_BASE_IDX 2 10921 #define regDP4_DP_SEC_CNTL6 0x2557 10922 #define regDP4_DP_SEC_CNTL6_BASE_IDX 2 10923 #define regDP4_DP_SEC_CNTL7 0x2558 10924 #define regDP4_DP_SEC_CNTL7_BASE_IDX 2 10925 #define regDP4_DP_DB_CNTL 0x2559 10926 #define regDP4_DP_DB_CNTL_BASE_IDX 2 10927 #define regDP4_DP_MSA_VBID_MISC 0x255a 10928 #define regDP4_DP_MSA_VBID_MISC_BASE_IDX 2 10929 #define regDP4_DP_SEC_METADATA_TRANSMISSION 0x255b 10930 #define regDP4_DP_SEC_METADATA_TRANSMISSION_BASE_IDX 2 10931 #define regDP4_DP_DSC_BYTES_PER_PIXEL 0x255c 10932 #define regDP4_DP_DSC_BYTES_PER_PIXEL_BASE_IDX 2 10933 #define regDP4_DP_ALPM_CNTL 0x255d 10934 #define regDP4_DP_ALPM_CNTL_BASE_IDX 2 10935 #define regDP4_DP_GSP8_CNTL 0x255e 10936 #define regDP4_DP_GSP8_CNTL_BASE_IDX 2 10937 #define regDP4_DP_GSP9_CNTL 0x255f 10938 #define regDP4_DP_GSP9_CNTL_BASE_IDX 2 10939 #define regDP4_DP_GSP10_CNTL 0x2560 10940 #define regDP4_DP_GSP10_CNTL_BASE_IDX 2 10941 #define regDP4_DP_GSP11_CNTL 0x2561 10942 #define regDP4_DP_GSP11_CNTL_BASE_IDX 2 10943 #define regDP4_DP_GSP_EN_DB_STATUS 0x2562 10944 #define regDP4_DP_GSP_EN_DB_STATUS_BASE_IDX 2 10945 10946 10947 // addressBlock: dce_dc_dio_dig4_dispdec 10948 // base address: 0x1000 10949 #define regDIG4_DIG_FE_CNTL 0x248b 10950 #define regDIG4_DIG_FE_CNTL_BASE_IDX 2 10951 #define regDIG4_DIG_OUTPUT_CRC_CNTL 0x248c 10952 #define regDIG4_DIG_OUTPUT_CRC_CNTL_BASE_IDX 2 10953 #define regDIG4_DIG_OUTPUT_CRC_RESULT 0x248d 10954 #define regDIG4_DIG_OUTPUT_CRC_RESULT_BASE_IDX 2 10955 #define regDIG4_DIG_CLOCK_PATTERN 0x248e 10956 #define regDIG4_DIG_CLOCK_PATTERN_BASE_IDX 2 10957 #define regDIG4_DIG_TEST_PATTERN 0x248f 10958 #define regDIG4_DIG_TEST_PATTERN_BASE_IDX 2 10959 #define regDIG4_DIG_RANDOM_PATTERN_SEED 0x2490 10960 #define regDIG4_DIG_RANDOM_PATTERN_SEED_BASE_IDX 2 10961 #define regDIG4_DIG_FIFO_STATUS 0x2491 10962 #define regDIG4_DIG_FIFO_STATUS_BASE_IDX 2 10963 #define regDIG4_HDMI_METADATA_PACKET_CONTROL 0x2492 10964 #define regDIG4_HDMI_METADATA_PACKET_CONTROL_BASE_IDX 2 10965 #define regDIG4_HDMI_CONTROL 0x2493 10966 #define regDIG4_HDMI_CONTROL_BASE_IDX 2 10967 #define regDIG4_HDMI_STATUS 0x2494 10968 #define regDIG4_HDMI_STATUS_BASE_IDX 2 10969 #define regDIG4_HDMI_AUDIO_PACKET_CONTROL 0x2495 10970 #define regDIG4_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX 2 10971 #define regDIG4_HDMI_ACR_PACKET_CONTROL 0x2496 10972 #define regDIG4_HDMI_ACR_PACKET_CONTROL_BASE_IDX 2 10973 #define regDIG4_HDMI_VBI_PACKET_CONTROL 0x2497 10974 #define regDIG4_HDMI_VBI_PACKET_CONTROL_BASE_IDX 2 10975 #define regDIG4_HDMI_INFOFRAME_CONTROL0 0x2498 10976 #define regDIG4_HDMI_INFOFRAME_CONTROL0_BASE_IDX 2 10977 #define regDIG4_HDMI_INFOFRAME_CONTROL1 0x2499 10978 #define regDIG4_HDMI_INFOFRAME_CONTROL1_BASE_IDX 2 10979 #define regDIG4_HDMI_GENERIC_PACKET_CONTROL0 0x249a 10980 #define regDIG4_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX 2 10981 #define regDIG4_HDMI_GENERIC_PACKET_CONTROL6 0x249b 10982 #define regDIG4_HDMI_GENERIC_PACKET_CONTROL6_BASE_IDX 2 10983 #define regDIG4_HDMI_GENERIC_PACKET_CONTROL5 0x249c 10984 #define regDIG4_HDMI_GENERIC_PACKET_CONTROL5_BASE_IDX 2 10985 #define regDIG4_HDMI_GC 0x249d 10986 #define regDIG4_HDMI_GC_BASE_IDX 2 10987 #define regDIG4_HDMI_GENERIC_PACKET_CONTROL1 0x249e 10988 #define regDIG4_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX 2 10989 #define regDIG4_HDMI_GENERIC_PACKET_CONTROL2 0x249f 10990 #define regDIG4_HDMI_GENERIC_PACKET_CONTROL2_BASE_IDX 2 10991 #define regDIG4_HDMI_GENERIC_PACKET_CONTROL3 0x24a0 10992 #define regDIG4_HDMI_GENERIC_PACKET_CONTROL3_BASE_IDX 2 10993 #define regDIG4_HDMI_GENERIC_PACKET_CONTROL4 0x24a1 10994 #define regDIG4_HDMI_GENERIC_PACKET_CONTROL4_BASE_IDX 2 10995 #define regDIG4_HDMI_GENERIC_PACKET_CONTROL7 0x24a2 10996 #define regDIG4_HDMI_GENERIC_PACKET_CONTROL7_BASE_IDX 2 10997 #define regDIG4_HDMI_GENERIC_PACKET_CONTROL8 0x24a3 10998 #define regDIG4_HDMI_GENERIC_PACKET_CONTROL8_BASE_IDX 2 10999 #define regDIG4_HDMI_GENERIC_PACKET_CONTROL9 0x24a4 11000 #define regDIG4_HDMI_GENERIC_PACKET_CONTROL9_BASE_IDX 2 11001 #define regDIG4_HDMI_GENERIC_PACKET_CONTROL10 0x24a5 11002 #define regDIG4_HDMI_GENERIC_PACKET_CONTROL10_BASE_IDX 2 11003 #define regDIG4_HDMI_DB_CONTROL 0x24a6 11004 #define regDIG4_HDMI_DB_CONTROL_BASE_IDX 2 11005 #define regDIG4_HDMI_ACR_32_0 0x24a7 11006 #define regDIG4_HDMI_ACR_32_0_BASE_IDX 2 11007 #define regDIG4_HDMI_ACR_32_1 0x24a8 11008 #define regDIG4_HDMI_ACR_32_1_BASE_IDX 2 11009 #define regDIG4_HDMI_ACR_44_0 0x24a9 11010 #define regDIG4_HDMI_ACR_44_0_BASE_IDX 2 11011 #define regDIG4_HDMI_ACR_44_1 0x24aa 11012 #define regDIG4_HDMI_ACR_44_1_BASE_IDX 2 11013 #define regDIG4_HDMI_ACR_48_0 0x24ab 11014 #define regDIG4_HDMI_ACR_48_0_BASE_IDX 2 11015 #define regDIG4_HDMI_ACR_48_1 0x24ac 11016 #define regDIG4_HDMI_ACR_48_1_BASE_IDX 2 11017 #define regDIG4_HDMI_ACR_STATUS_0 0x24ad 11018 #define regDIG4_HDMI_ACR_STATUS_0_BASE_IDX 2 11019 #define regDIG4_HDMI_ACR_STATUS_1 0x24ae 11020 #define regDIG4_HDMI_ACR_STATUS_1_BASE_IDX 2 11021 #define regDIG4_AFMT_CNTL 0x24af 11022 #define regDIG4_AFMT_CNTL_BASE_IDX 2 11023 #define regDIG4_DIG_BE_CNTL 0x24b0 11024 #define regDIG4_DIG_BE_CNTL_BASE_IDX 2 11025 #define regDIG4_DIG_BE_EN_CNTL 0x24b1 11026 #define regDIG4_DIG_BE_EN_CNTL_BASE_IDX 2 11027 #define regDIG4_TMDS_CNTL 0x24d7 11028 #define regDIG4_TMDS_CNTL_BASE_IDX 2 11029 #define regDIG4_TMDS_CONTROL_CHAR 0x24d8 11030 #define regDIG4_TMDS_CONTROL_CHAR_BASE_IDX 2 11031 #define regDIG4_TMDS_CONTROL0_FEEDBACK 0x24d9 11032 #define regDIG4_TMDS_CONTROL0_FEEDBACK_BASE_IDX 2 11033 #define regDIG4_TMDS_STEREOSYNC_CTL_SEL 0x24da 11034 #define regDIG4_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX 2 11035 #define regDIG4_TMDS_SYNC_CHAR_PATTERN_0_1 0x24db 11036 #define regDIG4_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX 2 11037 #define regDIG4_TMDS_SYNC_CHAR_PATTERN_2_3 0x24dc 11038 #define regDIG4_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX 2 11039 #define regDIG4_TMDS_CTL_BITS 0x24de 11040 #define regDIG4_TMDS_CTL_BITS_BASE_IDX 2 11041 #define regDIG4_TMDS_DCBALANCER_CONTROL 0x24df 11042 #define regDIG4_TMDS_DCBALANCER_CONTROL_BASE_IDX 2 11043 #define regDIG4_TMDS_SYNC_DCBALANCE_CHAR 0x24e0 11044 #define regDIG4_TMDS_SYNC_DCBALANCE_CHAR_BASE_IDX 2 11045 #define regDIG4_TMDS_CTL0_1_GEN_CNTL 0x24e1 11046 #define regDIG4_TMDS_CTL0_1_GEN_CNTL_BASE_IDX 2 11047 #define regDIG4_TMDS_CTL2_3_GEN_CNTL 0x24e2 11048 #define regDIG4_TMDS_CTL2_3_GEN_CNTL_BASE_IDX 2 11049 #define regDIG4_DIG_VERSION 0x24e4 11050 #define regDIG4_DIG_VERSION_BASE_IDX 2 11051 #define regDIG4_FORCE_DIG_DISABLE 0x24e5 11052 #define regDIG4_FORCE_DIG_DISABLE_BASE_IDX 2 11053 11054 11055 // addressBlock: dce_dc_dio_dig0_afmt_afmt_dispdec 11056 // base address: 0x154cc 11057 #define regAFMT0_AFMT_VBI_PACKET_CONTROL 0x2074 11058 #define regAFMT0_AFMT_VBI_PACKET_CONTROL_BASE_IDX 2 11059 #define regAFMT0_AFMT_AUDIO_PACKET_CONTROL2 0x2075 11060 #define regAFMT0_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX 2 11061 #define regAFMT0_AFMT_AUDIO_INFO0 0x2076 11062 #define regAFMT0_AFMT_AUDIO_INFO0_BASE_IDX 2 11063 #define regAFMT0_AFMT_AUDIO_INFO1 0x2077 11064 #define regAFMT0_AFMT_AUDIO_INFO1_BASE_IDX 2 11065 #define regAFMT0_AFMT_60958_0 0x2078 11066 #define regAFMT0_AFMT_60958_0_BASE_IDX 2 11067 #define regAFMT0_AFMT_60958_1 0x2079 11068 #define regAFMT0_AFMT_60958_1_BASE_IDX 2 11069 #define regAFMT0_AFMT_AUDIO_CRC_CONTROL 0x207a 11070 #define regAFMT0_AFMT_AUDIO_CRC_CONTROL_BASE_IDX 2 11071 #define regAFMT0_AFMT_RAMP_CONTROL0 0x207b 11072 #define regAFMT0_AFMT_RAMP_CONTROL0_BASE_IDX 2 11073 #define regAFMT0_AFMT_RAMP_CONTROL1 0x207c 11074 #define regAFMT0_AFMT_RAMP_CONTROL1_BASE_IDX 2 11075 #define regAFMT0_AFMT_RAMP_CONTROL2 0x207d 11076 #define regAFMT0_AFMT_RAMP_CONTROL2_BASE_IDX 2 11077 #define regAFMT0_AFMT_RAMP_CONTROL3 0x207e 11078 #define regAFMT0_AFMT_RAMP_CONTROL3_BASE_IDX 2 11079 #define regAFMT0_AFMT_60958_2 0x207f 11080 #define regAFMT0_AFMT_60958_2_BASE_IDX 2 11081 #define regAFMT0_AFMT_AUDIO_CRC_RESULT 0x2080 11082 #define regAFMT0_AFMT_AUDIO_CRC_RESULT_BASE_IDX 2 11083 #define regAFMT0_AFMT_STATUS 0x2081 11084 #define regAFMT0_AFMT_STATUS_BASE_IDX 2 11085 #define regAFMT0_AFMT_AUDIO_PACKET_CONTROL 0x2082 11086 #define regAFMT0_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX 2 11087 #define regAFMT0_AFMT_INFOFRAME_CONTROL0 0x2083 11088 #define regAFMT0_AFMT_INFOFRAME_CONTROL0_BASE_IDX 2 11089 #define regAFMT0_AFMT_INTERRUPT_STATUS 0x2084 11090 #define regAFMT0_AFMT_INTERRUPT_STATUS_BASE_IDX 2 11091 #define regAFMT0_AFMT_AUDIO_SRC_CONTROL 0x2085 11092 #define regAFMT0_AFMT_AUDIO_SRC_CONTROL_BASE_IDX 2 11093 #define regAFMT0_AFMT_MEM_PWR 0x2087 11094 #define regAFMT0_AFMT_MEM_PWR_BASE_IDX 2 11095 11096 11097 // addressBlock: dce_dc_dio_dig1_afmt_afmt_dispdec 11098 // base address: 0x158cc 11099 #define regAFMT1_AFMT_VBI_PACKET_CONTROL 0x2174 11100 #define regAFMT1_AFMT_VBI_PACKET_CONTROL_BASE_IDX 2 11101 #define regAFMT1_AFMT_AUDIO_PACKET_CONTROL2 0x2175 11102 #define regAFMT1_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX 2 11103 #define regAFMT1_AFMT_AUDIO_INFO0 0x2176 11104 #define regAFMT1_AFMT_AUDIO_INFO0_BASE_IDX 2 11105 #define regAFMT1_AFMT_AUDIO_INFO1 0x2177 11106 #define regAFMT1_AFMT_AUDIO_INFO1_BASE_IDX 2 11107 #define regAFMT1_AFMT_60958_0 0x2178 11108 #define regAFMT1_AFMT_60958_0_BASE_IDX 2 11109 #define regAFMT1_AFMT_60958_1 0x2179 11110 #define regAFMT1_AFMT_60958_1_BASE_IDX 2 11111 #define regAFMT1_AFMT_AUDIO_CRC_CONTROL 0x217a 11112 #define regAFMT1_AFMT_AUDIO_CRC_CONTROL_BASE_IDX 2 11113 #define regAFMT1_AFMT_RAMP_CONTROL0 0x217b 11114 #define regAFMT1_AFMT_RAMP_CONTROL0_BASE_IDX 2 11115 #define regAFMT1_AFMT_RAMP_CONTROL1 0x217c 11116 #define regAFMT1_AFMT_RAMP_CONTROL1_BASE_IDX 2 11117 #define regAFMT1_AFMT_RAMP_CONTROL2 0x217d 11118 #define regAFMT1_AFMT_RAMP_CONTROL2_BASE_IDX 2 11119 #define regAFMT1_AFMT_RAMP_CONTROL3 0x217e 11120 #define regAFMT1_AFMT_RAMP_CONTROL3_BASE_IDX 2 11121 #define regAFMT1_AFMT_60958_2 0x217f 11122 #define regAFMT1_AFMT_60958_2_BASE_IDX 2 11123 #define regAFMT1_AFMT_AUDIO_CRC_RESULT 0x2180 11124 #define regAFMT1_AFMT_AUDIO_CRC_RESULT_BASE_IDX 2 11125 #define regAFMT1_AFMT_STATUS 0x2181 11126 #define regAFMT1_AFMT_STATUS_BASE_IDX 2 11127 #define regAFMT1_AFMT_AUDIO_PACKET_CONTROL 0x2182 11128 #define regAFMT1_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX 2 11129 #define regAFMT1_AFMT_INFOFRAME_CONTROL0 0x2183 11130 #define regAFMT1_AFMT_INFOFRAME_CONTROL0_BASE_IDX 2 11131 #define regAFMT1_AFMT_INTERRUPT_STATUS 0x2184 11132 #define regAFMT1_AFMT_INTERRUPT_STATUS_BASE_IDX 2 11133 #define regAFMT1_AFMT_AUDIO_SRC_CONTROL 0x2185 11134 #define regAFMT1_AFMT_AUDIO_SRC_CONTROL_BASE_IDX 2 11135 #define regAFMT1_AFMT_MEM_PWR 0x2187 11136 #define regAFMT1_AFMT_MEM_PWR_BASE_IDX 2 11137 11138 11139 // addressBlock: dce_dc_dio_dig2_afmt_afmt_dispdec 11140 // base address: 0x15ccc 11141 #define regAFMT2_AFMT_VBI_PACKET_CONTROL 0x2274 11142 #define regAFMT2_AFMT_VBI_PACKET_CONTROL_BASE_IDX 2 11143 #define regAFMT2_AFMT_AUDIO_PACKET_CONTROL2 0x2275 11144 #define regAFMT2_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX 2 11145 #define regAFMT2_AFMT_AUDIO_INFO0 0x2276 11146 #define regAFMT2_AFMT_AUDIO_INFO0_BASE_IDX 2 11147 #define regAFMT2_AFMT_AUDIO_INFO1 0x2277 11148 #define regAFMT2_AFMT_AUDIO_INFO1_BASE_IDX 2 11149 #define regAFMT2_AFMT_60958_0 0x2278 11150 #define regAFMT2_AFMT_60958_0_BASE_IDX 2 11151 #define regAFMT2_AFMT_60958_1 0x2279 11152 #define regAFMT2_AFMT_60958_1_BASE_IDX 2 11153 #define regAFMT2_AFMT_AUDIO_CRC_CONTROL 0x227a 11154 #define regAFMT2_AFMT_AUDIO_CRC_CONTROL_BASE_IDX 2 11155 #define regAFMT2_AFMT_RAMP_CONTROL0 0x227b 11156 #define regAFMT2_AFMT_RAMP_CONTROL0_BASE_IDX 2 11157 #define regAFMT2_AFMT_RAMP_CONTROL1 0x227c 11158 #define regAFMT2_AFMT_RAMP_CONTROL1_BASE_IDX 2 11159 #define regAFMT2_AFMT_RAMP_CONTROL2 0x227d 11160 #define regAFMT2_AFMT_RAMP_CONTROL2_BASE_IDX 2 11161 #define regAFMT2_AFMT_RAMP_CONTROL3 0x227e 11162 #define regAFMT2_AFMT_RAMP_CONTROL3_BASE_IDX 2 11163 #define regAFMT2_AFMT_60958_2 0x227f 11164 #define regAFMT2_AFMT_60958_2_BASE_IDX 2 11165 #define regAFMT2_AFMT_AUDIO_CRC_RESULT 0x2280 11166 #define regAFMT2_AFMT_AUDIO_CRC_RESULT_BASE_IDX 2 11167 #define regAFMT2_AFMT_STATUS 0x2281 11168 #define regAFMT2_AFMT_STATUS_BASE_IDX 2 11169 #define regAFMT2_AFMT_AUDIO_PACKET_CONTROL 0x2282 11170 #define regAFMT2_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX 2 11171 #define regAFMT2_AFMT_INFOFRAME_CONTROL0 0x2283 11172 #define regAFMT2_AFMT_INFOFRAME_CONTROL0_BASE_IDX 2 11173 #define regAFMT2_AFMT_INTERRUPT_STATUS 0x2284 11174 #define regAFMT2_AFMT_INTERRUPT_STATUS_BASE_IDX 2 11175 #define regAFMT2_AFMT_AUDIO_SRC_CONTROL 0x2285 11176 #define regAFMT2_AFMT_AUDIO_SRC_CONTROL_BASE_IDX 2 11177 #define regAFMT2_AFMT_MEM_PWR 0x2287 11178 #define regAFMT2_AFMT_MEM_PWR_BASE_IDX 2 11179 11180 11181 // addressBlock: dce_dc_dio_dig3_afmt_afmt_dispdec 11182 // base address: 0x160cc 11183 #define regAFMT3_AFMT_VBI_PACKET_CONTROL 0x2374 11184 #define regAFMT3_AFMT_VBI_PACKET_CONTROL_BASE_IDX 2 11185 #define regAFMT3_AFMT_AUDIO_PACKET_CONTROL2 0x2375 11186 #define regAFMT3_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX 2 11187 #define regAFMT3_AFMT_AUDIO_INFO0 0x2376 11188 #define regAFMT3_AFMT_AUDIO_INFO0_BASE_IDX 2 11189 #define regAFMT3_AFMT_AUDIO_INFO1 0x2377 11190 #define regAFMT3_AFMT_AUDIO_INFO1_BASE_IDX 2 11191 #define regAFMT3_AFMT_60958_0 0x2378 11192 #define regAFMT3_AFMT_60958_0_BASE_IDX 2 11193 #define regAFMT3_AFMT_60958_1 0x2379 11194 #define regAFMT3_AFMT_60958_1_BASE_IDX 2 11195 #define regAFMT3_AFMT_AUDIO_CRC_CONTROL 0x237a 11196 #define regAFMT3_AFMT_AUDIO_CRC_CONTROL_BASE_IDX 2 11197 #define regAFMT3_AFMT_RAMP_CONTROL0 0x237b 11198 #define regAFMT3_AFMT_RAMP_CONTROL0_BASE_IDX 2 11199 #define regAFMT3_AFMT_RAMP_CONTROL1 0x237c 11200 #define regAFMT3_AFMT_RAMP_CONTROL1_BASE_IDX 2 11201 #define regAFMT3_AFMT_RAMP_CONTROL2 0x237d 11202 #define regAFMT3_AFMT_RAMP_CONTROL2_BASE_IDX 2 11203 #define regAFMT3_AFMT_RAMP_CONTROL3 0x237e 11204 #define regAFMT3_AFMT_RAMP_CONTROL3_BASE_IDX 2 11205 #define regAFMT3_AFMT_60958_2 0x237f 11206 #define regAFMT3_AFMT_60958_2_BASE_IDX 2 11207 #define regAFMT3_AFMT_AUDIO_CRC_RESULT 0x2380 11208 #define regAFMT3_AFMT_AUDIO_CRC_RESULT_BASE_IDX 2 11209 #define regAFMT3_AFMT_STATUS 0x2381 11210 #define regAFMT3_AFMT_STATUS_BASE_IDX 2 11211 #define regAFMT3_AFMT_AUDIO_PACKET_CONTROL 0x2382 11212 #define regAFMT3_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX 2 11213 #define regAFMT3_AFMT_INFOFRAME_CONTROL0 0x2383 11214 #define regAFMT3_AFMT_INFOFRAME_CONTROL0_BASE_IDX 2 11215 #define regAFMT3_AFMT_INTERRUPT_STATUS 0x2384 11216 #define regAFMT3_AFMT_INTERRUPT_STATUS_BASE_IDX 2 11217 #define regAFMT3_AFMT_AUDIO_SRC_CONTROL 0x2385 11218 #define regAFMT3_AFMT_AUDIO_SRC_CONTROL_BASE_IDX 2 11219 #define regAFMT3_AFMT_MEM_PWR 0x2387 11220 #define regAFMT3_AFMT_MEM_PWR_BASE_IDX 2 11221 11222 11223 // addressBlock: dce_dc_dio_dig4_afmt_afmt_dispdec 11224 // base address: 0x164cc 11225 #define regAFMT4_AFMT_VBI_PACKET_CONTROL 0x2474 11226 #define regAFMT4_AFMT_VBI_PACKET_CONTROL_BASE_IDX 2 11227 #define regAFMT4_AFMT_AUDIO_PACKET_CONTROL2 0x2475 11228 #define regAFMT4_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX 2 11229 #define regAFMT4_AFMT_AUDIO_INFO0 0x2476 11230 #define regAFMT4_AFMT_AUDIO_INFO0_BASE_IDX 2 11231 #define regAFMT4_AFMT_AUDIO_INFO1 0x2477 11232 #define regAFMT4_AFMT_AUDIO_INFO1_BASE_IDX 2 11233 #define regAFMT4_AFMT_60958_0 0x2478 11234 #define regAFMT4_AFMT_60958_0_BASE_IDX 2 11235 #define regAFMT4_AFMT_60958_1 0x2479 11236 #define regAFMT4_AFMT_60958_1_BASE_IDX 2 11237 #define regAFMT4_AFMT_AUDIO_CRC_CONTROL 0x247a 11238 #define regAFMT4_AFMT_AUDIO_CRC_CONTROL_BASE_IDX 2 11239 #define regAFMT4_AFMT_RAMP_CONTROL0 0x247b 11240 #define regAFMT4_AFMT_RAMP_CONTROL0_BASE_IDX 2 11241 #define regAFMT4_AFMT_RAMP_CONTROL1 0x247c 11242 #define regAFMT4_AFMT_RAMP_CONTROL1_BASE_IDX 2 11243 #define regAFMT4_AFMT_RAMP_CONTROL2 0x247d 11244 #define regAFMT4_AFMT_RAMP_CONTROL2_BASE_IDX 2 11245 #define regAFMT4_AFMT_RAMP_CONTROL3 0x247e 11246 #define regAFMT4_AFMT_RAMP_CONTROL3_BASE_IDX 2 11247 #define regAFMT4_AFMT_60958_2 0x247f 11248 #define regAFMT4_AFMT_60958_2_BASE_IDX 2 11249 #define regAFMT4_AFMT_AUDIO_CRC_RESULT 0x2480 11250 #define regAFMT4_AFMT_AUDIO_CRC_RESULT_BASE_IDX 2 11251 #define regAFMT4_AFMT_STATUS 0x2481 11252 #define regAFMT4_AFMT_STATUS_BASE_IDX 2 11253 #define regAFMT4_AFMT_AUDIO_PACKET_CONTROL 0x2482 11254 #define regAFMT4_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX 2 11255 #define regAFMT4_AFMT_INFOFRAME_CONTROL0 0x2483 11256 #define regAFMT4_AFMT_INFOFRAME_CONTROL0_BASE_IDX 2 11257 #define regAFMT4_AFMT_INTERRUPT_STATUS 0x2484 11258 #define regAFMT4_AFMT_INTERRUPT_STATUS_BASE_IDX 2 11259 #define regAFMT4_AFMT_AUDIO_SRC_CONTROL 0x2485 11260 #define regAFMT4_AFMT_AUDIO_SRC_CONTROL_BASE_IDX 2 11261 #define regAFMT4_AFMT_MEM_PWR 0x2487 11262 #define regAFMT4_AFMT_MEM_PWR_BASE_IDX 2 11263 11264 11265 // addressBlock: dce_dc_dio_dig0_dme_dme_dispdec 11266 // base address: 0x15524 11267 #define regDME0_DME_CONTROL 0x2089 11268 #define regDME0_DME_CONTROL_BASE_IDX 2 11269 #define regDME0_DME_MEMORY_CONTROL 0x208a 11270 #define regDME0_DME_MEMORY_CONTROL_BASE_IDX 2 11271 11272 11273 // addressBlock: dce_dc_dio_dig0_vpg_vpg_dispdec 11274 // base address: 0x154a0 11275 #define regVPG0_VPG_GENERIC_PACKET_ACCESS_CTRL 0x2068 11276 #define regVPG0_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX 2 11277 #define regVPG0_VPG_GENERIC_PACKET_DATA 0x2069 11278 #define regVPG0_VPG_GENERIC_PACKET_DATA_BASE_IDX 2 11279 #define regVPG0_VPG_GSP_FRAME_UPDATE_CTRL 0x206a 11280 #define regVPG0_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX 2 11281 #define regVPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL 0x206b 11282 #define regVPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX 2 11283 #define regVPG0_VPG_GENERIC_STATUS 0x206c 11284 #define regVPG0_VPG_GENERIC_STATUS_BASE_IDX 2 11285 #define regVPG0_VPG_MEM_PWR 0x206d 11286 #define regVPG0_VPG_MEM_PWR_BASE_IDX 2 11287 #define regVPG0_VPG_ISRC1_2_ACCESS_CTRL 0x206e 11288 #define regVPG0_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX 2 11289 #define regVPG0_VPG_ISRC1_2_DATA 0x206f 11290 #define regVPG0_VPG_ISRC1_2_DATA_BASE_IDX 2 11291 #define regVPG0_VPG_MPEG_INFO0 0x2070 11292 #define regVPG0_VPG_MPEG_INFO0_BASE_IDX 2 11293 #define regVPG0_VPG_MPEG_INFO1 0x2071 11294 #define regVPG0_VPG_MPEG_INFO1_BASE_IDX 2 11295 11296 11297 // addressBlock: dce_dc_dio_dig1_dme_dme_dispdec 11298 // base address: 0x15924 11299 #define regDME1_DME_CONTROL 0x2189 11300 #define regDME1_DME_CONTROL_BASE_IDX 2 11301 #define regDME1_DME_MEMORY_CONTROL 0x218a 11302 #define regDME1_DME_MEMORY_CONTROL_BASE_IDX 2 11303 11304 11305 // addressBlock: dce_dc_dio_dig1_vpg_vpg_dispdec 11306 // base address: 0x158a0 11307 #define regVPG1_VPG_GENERIC_PACKET_ACCESS_CTRL 0x2168 11308 #define regVPG1_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX 2 11309 #define regVPG1_VPG_GENERIC_PACKET_DATA 0x2169 11310 #define regVPG1_VPG_GENERIC_PACKET_DATA_BASE_IDX 2 11311 #define regVPG1_VPG_GSP_FRAME_UPDATE_CTRL 0x216a 11312 #define regVPG1_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX 2 11313 #define regVPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL 0x216b 11314 #define regVPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX 2 11315 #define regVPG1_VPG_GENERIC_STATUS 0x216c 11316 #define regVPG1_VPG_GENERIC_STATUS_BASE_IDX 2 11317 #define regVPG1_VPG_MEM_PWR 0x216d 11318 #define regVPG1_VPG_MEM_PWR_BASE_IDX 2 11319 #define regVPG1_VPG_ISRC1_2_ACCESS_CTRL 0x216e 11320 #define regVPG1_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX 2 11321 #define regVPG1_VPG_ISRC1_2_DATA 0x216f 11322 #define regVPG1_VPG_ISRC1_2_DATA_BASE_IDX 2 11323 #define regVPG1_VPG_MPEG_INFO0 0x2170 11324 #define regVPG1_VPG_MPEG_INFO0_BASE_IDX 2 11325 #define regVPG1_VPG_MPEG_INFO1 0x2171 11326 #define regVPG1_VPG_MPEG_INFO1_BASE_IDX 2 11327 11328 11329 // addressBlock: dce_dc_dio_dig2_dme_dme_dispdec 11330 // base address: 0x15d24 11331 #define regDME2_DME_CONTROL 0x2289 11332 #define regDME2_DME_CONTROL_BASE_IDX 2 11333 #define regDME2_DME_MEMORY_CONTROL 0x228a 11334 #define regDME2_DME_MEMORY_CONTROL_BASE_IDX 2 11335 11336 11337 // addressBlock: dce_dc_dio_dig2_vpg_vpg_dispdec 11338 // base address: 0x15ca0 11339 #define regVPG2_VPG_GENERIC_PACKET_ACCESS_CTRL 0x2268 11340 #define regVPG2_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX 2 11341 #define regVPG2_VPG_GENERIC_PACKET_DATA 0x2269 11342 #define regVPG2_VPG_GENERIC_PACKET_DATA_BASE_IDX 2 11343 #define regVPG2_VPG_GSP_FRAME_UPDATE_CTRL 0x226a 11344 #define regVPG2_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX 2 11345 #define regVPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL 0x226b 11346 #define regVPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX 2 11347 #define regVPG2_VPG_GENERIC_STATUS 0x226c 11348 #define regVPG2_VPG_GENERIC_STATUS_BASE_IDX 2 11349 #define regVPG2_VPG_MEM_PWR 0x226d 11350 #define regVPG2_VPG_MEM_PWR_BASE_IDX 2 11351 #define regVPG2_VPG_ISRC1_2_ACCESS_CTRL 0x226e 11352 #define regVPG2_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX 2 11353 #define regVPG2_VPG_ISRC1_2_DATA 0x226f 11354 #define regVPG2_VPG_ISRC1_2_DATA_BASE_IDX 2 11355 #define regVPG2_VPG_MPEG_INFO0 0x2270 11356 #define regVPG2_VPG_MPEG_INFO0_BASE_IDX 2 11357 #define regVPG2_VPG_MPEG_INFO1 0x2271 11358 #define regVPG2_VPG_MPEG_INFO1_BASE_IDX 2 11359 11360 11361 // addressBlock: dce_dc_dio_dig3_dme_dme_dispdec 11362 // base address: 0x16124 11363 #define regDME3_DME_CONTROL 0x2389 11364 #define regDME3_DME_CONTROL_BASE_IDX 2 11365 #define regDME3_DME_MEMORY_CONTROL 0x238a 11366 #define regDME3_DME_MEMORY_CONTROL_BASE_IDX 2 11367 11368 11369 // addressBlock: dce_dc_dio_dig3_vpg_vpg_dispdec 11370 // base address: 0x160a0 11371 #define regVPG3_VPG_GENERIC_PACKET_ACCESS_CTRL 0x2368 11372 #define regVPG3_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX 2 11373 #define regVPG3_VPG_GENERIC_PACKET_DATA 0x2369 11374 #define regVPG3_VPG_GENERIC_PACKET_DATA_BASE_IDX 2 11375 #define regVPG3_VPG_GSP_FRAME_UPDATE_CTRL 0x236a 11376 #define regVPG3_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX 2 11377 #define regVPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL 0x236b 11378 #define regVPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX 2 11379 #define regVPG3_VPG_GENERIC_STATUS 0x236c 11380 #define regVPG3_VPG_GENERIC_STATUS_BASE_IDX 2 11381 #define regVPG3_VPG_MEM_PWR 0x236d 11382 #define regVPG3_VPG_MEM_PWR_BASE_IDX 2 11383 #define regVPG3_VPG_ISRC1_2_ACCESS_CTRL 0x236e 11384 #define regVPG3_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX 2 11385 #define regVPG3_VPG_ISRC1_2_DATA 0x236f 11386 #define regVPG3_VPG_ISRC1_2_DATA_BASE_IDX 2 11387 #define regVPG3_VPG_MPEG_INFO0 0x2370 11388 #define regVPG3_VPG_MPEG_INFO0_BASE_IDX 2 11389 #define regVPG3_VPG_MPEG_INFO1 0x2371 11390 #define regVPG3_VPG_MPEG_INFO1_BASE_IDX 2 11391 11392 11393 // addressBlock: dce_dc_dio_dig4_dme_dme_dispdec 11394 // base address: 0x16524 11395 #define regDME4_DME_CONTROL 0x2489 11396 #define regDME4_DME_CONTROL_BASE_IDX 2 11397 #define regDME4_DME_MEMORY_CONTROL 0x248a 11398 #define regDME4_DME_MEMORY_CONTROL_BASE_IDX 2 11399 11400 11401 // addressBlock: dce_dc_dio_dig4_vpg_vpg_dispdec 11402 // base address: 0x164a0 11403 #define regVPG4_VPG_GENERIC_PACKET_ACCESS_CTRL 0x2468 11404 #define regVPG4_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX 2 11405 #define regVPG4_VPG_GENERIC_PACKET_DATA 0x2469 11406 #define regVPG4_VPG_GENERIC_PACKET_DATA_BASE_IDX 2 11407 #define regVPG4_VPG_GSP_FRAME_UPDATE_CTRL 0x246a 11408 #define regVPG4_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX 2 11409 #define regVPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL 0x246b 11410 #define regVPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX 2 11411 #define regVPG4_VPG_GENERIC_STATUS 0x246c 11412 #define regVPG4_VPG_GENERIC_STATUS_BASE_IDX 2 11413 #define regVPG4_VPG_MEM_PWR 0x246d 11414 #define regVPG4_VPG_MEM_PWR_BASE_IDX 2 11415 #define regVPG4_VPG_ISRC1_2_ACCESS_CTRL 0x246e 11416 #define regVPG4_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX 2 11417 #define regVPG4_VPG_ISRC1_2_DATA 0x246f 11418 #define regVPG4_VPG_ISRC1_2_DATA_BASE_IDX 2 11419 #define regVPG4_VPG_MPEG_INFO0 0x2470 11420 #define regVPG4_VPG_MPEG_INFO0_BASE_IDX 2 11421 #define regVPG4_VPG_MPEG_INFO1 0x2471 11422 #define regVPG4_VPG_MPEG_INFO1_BASE_IDX 2 11423 11424 11425 // addressBlock: dce_dc_dio_dp_aux0_dispdec 11426 // base address: 0x0 11427 #define regDP_AUX0_AUX_CONTROL 0x1f50 11428 #define regDP_AUX0_AUX_CONTROL_BASE_IDX 2 11429 #define regDP_AUX0_AUX_SW_CONTROL 0x1f51 11430 #define regDP_AUX0_AUX_SW_CONTROL_BASE_IDX 2 11431 #define regDP_AUX0_AUX_ARB_CONTROL 0x1f52 11432 #define regDP_AUX0_AUX_ARB_CONTROL_BASE_IDX 2 11433 #define regDP_AUX0_AUX_INTERRUPT_CONTROL 0x1f53 11434 #define regDP_AUX0_AUX_INTERRUPT_CONTROL_BASE_IDX 2 11435 #define regDP_AUX0_AUX_SW_STATUS 0x1f54 11436 #define regDP_AUX0_AUX_SW_STATUS_BASE_IDX 2 11437 #define regDP_AUX0_AUX_LS_STATUS 0x1f55 11438 #define regDP_AUX0_AUX_LS_STATUS_BASE_IDX 2 11439 #define regDP_AUX0_AUX_SW_DATA 0x1f56 11440 #define regDP_AUX0_AUX_SW_DATA_BASE_IDX 2 11441 #define regDP_AUX0_AUX_LS_DATA 0x1f57 11442 #define regDP_AUX0_AUX_LS_DATA_BASE_IDX 2 11443 #define regDP_AUX0_AUX_DPHY_TX_REF_CONTROL 0x1f58 11444 #define regDP_AUX0_AUX_DPHY_TX_REF_CONTROL_BASE_IDX 2 11445 #define regDP_AUX0_AUX_DPHY_TX_CONTROL 0x1f59 11446 #define regDP_AUX0_AUX_DPHY_TX_CONTROL_BASE_IDX 2 11447 #define regDP_AUX0_AUX_DPHY_RX_CONTROL0 0x1f5a 11448 #define regDP_AUX0_AUX_DPHY_RX_CONTROL0_BASE_IDX 2 11449 #define regDP_AUX0_AUX_DPHY_RX_CONTROL1 0x1f5b 11450 #define regDP_AUX0_AUX_DPHY_RX_CONTROL1_BASE_IDX 2 11451 #define regDP_AUX0_AUX_DPHY_TX_STATUS 0x1f5c 11452 #define regDP_AUX0_AUX_DPHY_TX_STATUS_BASE_IDX 2 11453 #define regDP_AUX0_AUX_DPHY_RX_STATUS 0x1f5d 11454 #define regDP_AUX0_AUX_DPHY_RX_STATUS_BASE_IDX 2 11455 #define regDP_AUX0_AUX_GTC_SYNC_CONTROL 0x1f5e 11456 #define regDP_AUX0_AUX_GTC_SYNC_CONTROL_BASE_IDX 2 11457 #define regDP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL 0x1f5f 11458 #define regDP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL_BASE_IDX 2 11459 #define regDP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS 0x1f60 11460 #define regDP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS_BASE_IDX 2 11461 #define regDP_AUX0_AUX_GTC_SYNC_STATUS 0x1f61 11462 #define regDP_AUX0_AUX_GTC_SYNC_STATUS_BASE_IDX 2 11463 #define regDP_AUX0_AUX_PHY_WAKE_CNTL 0x1f66 11464 #define regDP_AUX0_AUX_PHY_WAKE_CNTL_BASE_IDX 2 11465 11466 11467 // addressBlock: dce_dc_dio_dp_aux1_dispdec 11468 // base address: 0x70 11469 #define regDP_AUX1_AUX_CONTROL 0x1f6c 11470 #define regDP_AUX1_AUX_CONTROL_BASE_IDX 2 11471 #define regDP_AUX1_AUX_SW_CONTROL 0x1f6d 11472 #define regDP_AUX1_AUX_SW_CONTROL_BASE_IDX 2 11473 #define regDP_AUX1_AUX_ARB_CONTROL 0x1f6e 11474 #define regDP_AUX1_AUX_ARB_CONTROL_BASE_IDX 2 11475 #define regDP_AUX1_AUX_INTERRUPT_CONTROL 0x1f6f 11476 #define regDP_AUX1_AUX_INTERRUPT_CONTROL_BASE_IDX 2 11477 #define regDP_AUX1_AUX_SW_STATUS 0x1f70 11478 #define regDP_AUX1_AUX_SW_STATUS_BASE_IDX 2 11479 #define regDP_AUX1_AUX_LS_STATUS 0x1f71 11480 #define regDP_AUX1_AUX_LS_STATUS_BASE_IDX 2 11481 #define regDP_AUX1_AUX_SW_DATA 0x1f72 11482 #define regDP_AUX1_AUX_SW_DATA_BASE_IDX 2 11483 #define regDP_AUX1_AUX_LS_DATA 0x1f73 11484 #define regDP_AUX1_AUX_LS_DATA_BASE_IDX 2 11485 #define regDP_AUX1_AUX_DPHY_TX_REF_CONTROL 0x1f74 11486 #define regDP_AUX1_AUX_DPHY_TX_REF_CONTROL_BASE_IDX 2 11487 #define regDP_AUX1_AUX_DPHY_TX_CONTROL 0x1f75 11488 #define regDP_AUX1_AUX_DPHY_TX_CONTROL_BASE_IDX 2 11489 #define regDP_AUX1_AUX_DPHY_RX_CONTROL0 0x1f76 11490 #define regDP_AUX1_AUX_DPHY_RX_CONTROL0_BASE_IDX 2 11491 #define regDP_AUX1_AUX_DPHY_RX_CONTROL1 0x1f77 11492 #define regDP_AUX1_AUX_DPHY_RX_CONTROL1_BASE_IDX 2 11493 #define regDP_AUX1_AUX_DPHY_TX_STATUS 0x1f78 11494 #define regDP_AUX1_AUX_DPHY_TX_STATUS_BASE_IDX 2 11495 #define regDP_AUX1_AUX_DPHY_RX_STATUS 0x1f79 11496 #define regDP_AUX1_AUX_DPHY_RX_STATUS_BASE_IDX 2 11497 #define regDP_AUX1_AUX_GTC_SYNC_CONTROL 0x1f7a 11498 #define regDP_AUX1_AUX_GTC_SYNC_CONTROL_BASE_IDX 2 11499 #define regDP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL 0x1f7b 11500 #define regDP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL_BASE_IDX 2 11501 #define regDP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS 0x1f7c 11502 #define regDP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS_BASE_IDX 2 11503 #define regDP_AUX1_AUX_GTC_SYNC_STATUS 0x1f7d 11504 #define regDP_AUX1_AUX_GTC_SYNC_STATUS_BASE_IDX 2 11505 #define regDP_AUX1_AUX_PHY_WAKE_CNTL 0x1f82 11506 #define regDP_AUX1_AUX_PHY_WAKE_CNTL_BASE_IDX 2 11507 11508 11509 // addressBlock: dce_dc_dio_dp_aux2_dispdec 11510 // base address: 0xe0 11511 #define regDP_AUX2_AUX_CONTROL 0x1f88 11512 #define regDP_AUX2_AUX_CONTROL_BASE_IDX 2 11513 #define regDP_AUX2_AUX_SW_CONTROL 0x1f89 11514 #define regDP_AUX2_AUX_SW_CONTROL_BASE_IDX 2 11515 #define regDP_AUX2_AUX_ARB_CONTROL 0x1f8a 11516 #define regDP_AUX2_AUX_ARB_CONTROL_BASE_IDX 2 11517 #define regDP_AUX2_AUX_INTERRUPT_CONTROL 0x1f8b 11518 #define regDP_AUX2_AUX_INTERRUPT_CONTROL_BASE_IDX 2 11519 #define regDP_AUX2_AUX_SW_STATUS 0x1f8c 11520 #define regDP_AUX2_AUX_SW_STATUS_BASE_IDX 2 11521 #define regDP_AUX2_AUX_LS_STATUS 0x1f8d 11522 #define regDP_AUX2_AUX_LS_STATUS_BASE_IDX 2 11523 #define regDP_AUX2_AUX_SW_DATA 0x1f8e 11524 #define regDP_AUX2_AUX_SW_DATA_BASE_IDX 2 11525 #define regDP_AUX2_AUX_LS_DATA 0x1f8f 11526 #define regDP_AUX2_AUX_LS_DATA_BASE_IDX 2 11527 #define regDP_AUX2_AUX_DPHY_TX_REF_CONTROL 0x1f90 11528 #define regDP_AUX2_AUX_DPHY_TX_REF_CONTROL_BASE_IDX 2 11529 #define regDP_AUX2_AUX_DPHY_TX_CONTROL 0x1f91 11530 #define regDP_AUX2_AUX_DPHY_TX_CONTROL_BASE_IDX 2 11531 #define regDP_AUX2_AUX_DPHY_RX_CONTROL0 0x1f92 11532 #define regDP_AUX2_AUX_DPHY_RX_CONTROL0_BASE_IDX 2 11533 #define regDP_AUX2_AUX_DPHY_RX_CONTROL1 0x1f93 11534 #define regDP_AUX2_AUX_DPHY_RX_CONTROL1_BASE_IDX 2 11535 #define regDP_AUX2_AUX_DPHY_TX_STATUS 0x1f94 11536 #define regDP_AUX2_AUX_DPHY_TX_STATUS_BASE_IDX 2 11537 #define regDP_AUX2_AUX_DPHY_RX_STATUS 0x1f95 11538 #define regDP_AUX2_AUX_DPHY_RX_STATUS_BASE_IDX 2 11539 #define regDP_AUX2_AUX_GTC_SYNC_CONTROL 0x1f96 11540 #define regDP_AUX2_AUX_GTC_SYNC_CONTROL_BASE_IDX 2 11541 #define regDP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL 0x1f97 11542 #define regDP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL_BASE_IDX 2 11543 #define regDP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS 0x1f98 11544 #define regDP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS_BASE_IDX 2 11545 #define regDP_AUX2_AUX_GTC_SYNC_STATUS 0x1f99 11546 #define regDP_AUX2_AUX_GTC_SYNC_STATUS_BASE_IDX 2 11547 #define regDP_AUX2_AUX_PHY_WAKE_CNTL 0x1f9e 11548 #define regDP_AUX2_AUX_PHY_WAKE_CNTL_BASE_IDX 2 11549 11550 11551 // addressBlock: dce_dc_dio_dp_aux3_dispdec 11552 // base address: 0x150 11553 #define regDP_AUX3_AUX_CONTROL 0x1fa4 11554 #define regDP_AUX3_AUX_CONTROL_BASE_IDX 2 11555 #define regDP_AUX3_AUX_SW_CONTROL 0x1fa5 11556 #define regDP_AUX3_AUX_SW_CONTROL_BASE_IDX 2 11557 #define regDP_AUX3_AUX_ARB_CONTROL 0x1fa6 11558 #define regDP_AUX3_AUX_ARB_CONTROL_BASE_IDX 2 11559 #define regDP_AUX3_AUX_INTERRUPT_CONTROL 0x1fa7 11560 #define regDP_AUX3_AUX_INTERRUPT_CONTROL_BASE_IDX 2 11561 #define regDP_AUX3_AUX_SW_STATUS 0x1fa8 11562 #define regDP_AUX3_AUX_SW_STATUS_BASE_IDX 2 11563 #define regDP_AUX3_AUX_LS_STATUS 0x1fa9 11564 #define regDP_AUX3_AUX_LS_STATUS_BASE_IDX 2 11565 #define regDP_AUX3_AUX_SW_DATA 0x1faa 11566 #define regDP_AUX3_AUX_SW_DATA_BASE_IDX 2 11567 #define regDP_AUX3_AUX_LS_DATA 0x1fab 11568 #define regDP_AUX3_AUX_LS_DATA_BASE_IDX 2 11569 #define regDP_AUX3_AUX_DPHY_TX_REF_CONTROL 0x1fac 11570 #define regDP_AUX3_AUX_DPHY_TX_REF_CONTROL_BASE_IDX 2 11571 #define regDP_AUX3_AUX_DPHY_TX_CONTROL 0x1fad 11572 #define regDP_AUX3_AUX_DPHY_TX_CONTROL_BASE_IDX 2 11573 #define regDP_AUX3_AUX_DPHY_RX_CONTROL0 0x1fae 11574 #define regDP_AUX3_AUX_DPHY_RX_CONTROL0_BASE_IDX 2 11575 #define regDP_AUX3_AUX_DPHY_RX_CONTROL1 0x1faf 11576 #define regDP_AUX3_AUX_DPHY_RX_CONTROL1_BASE_IDX 2 11577 #define regDP_AUX3_AUX_DPHY_TX_STATUS 0x1fb0 11578 #define regDP_AUX3_AUX_DPHY_TX_STATUS_BASE_IDX 2 11579 #define regDP_AUX3_AUX_DPHY_RX_STATUS 0x1fb1 11580 #define regDP_AUX3_AUX_DPHY_RX_STATUS_BASE_IDX 2 11581 #define regDP_AUX3_AUX_GTC_SYNC_CONTROL 0x1fb2 11582 #define regDP_AUX3_AUX_GTC_SYNC_CONTROL_BASE_IDX 2 11583 #define regDP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL 0x1fb3 11584 #define regDP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL_BASE_IDX 2 11585 #define regDP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS 0x1fb4 11586 #define regDP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS_BASE_IDX 2 11587 #define regDP_AUX3_AUX_GTC_SYNC_STATUS 0x1fb5 11588 #define regDP_AUX3_AUX_GTC_SYNC_STATUS_BASE_IDX 2 11589 #define regDP_AUX3_AUX_PHY_WAKE_CNTL 0x1fba 11590 #define regDP_AUX3_AUX_PHY_WAKE_CNTL_BASE_IDX 2 11591 11592 11593 // addressBlock: dce_dc_dio_dp_aux4_dispdec 11594 // base address: 0x1c0 11595 #define regDP_AUX4_AUX_CONTROL 0x1fc0 11596 #define regDP_AUX4_AUX_CONTROL_BASE_IDX 2 11597 #define regDP_AUX4_AUX_SW_CONTROL 0x1fc1 11598 #define regDP_AUX4_AUX_SW_CONTROL_BASE_IDX 2 11599 #define regDP_AUX4_AUX_ARB_CONTROL 0x1fc2 11600 #define regDP_AUX4_AUX_ARB_CONTROL_BASE_IDX 2 11601 #define regDP_AUX4_AUX_INTERRUPT_CONTROL 0x1fc3 11602 #define regDP_AUX4_AUX_INTERRUPT_CONTROL_BASE_IDX 2 11603 #define regDP_AUX4_AUX_SW_STATUS 0x1fc4 11604 #define regDP_AUX4_AUX_SW_STATUS_BASE_IDX 2 11605 #define regDP_AUX4_AUX_LS_STATUS 0x1fc5 11606 #define regDP_AUX4_AUX_LS_STATUS_BASE_IDX 2 11607 #define regDP_AUX4_AUX_SW_DATA 0x1fc6 11608 #define regDP_AUX4_AUX_SW_DATA_BASE_IDX 2 11609 #define regDP_AUX4_AUX_LS_DATA 0x1fc7 11610 #define regDP_AUX4_AUX_LS_DATA_BASE_IDX 2 11611 #define regDP_AUX4_AUX_DPHY_TX_REF_CONTROL 0x1fc8 11612 #define regDP_AUX4_AUX_DPHY_TX_REF_CONTROL_BASE_IDX 2 11613 #define regDP_AUX4_AUX_DPHY_TX_CONTROL 0x1fc9 11614 #define regDP_AUX4_AUX_DPHY_TX_CONTROL_BASE_IDX 2 11615 #define regDP_AUX4_AUX_DPHY_RX_CONTROL0 0x1fca 11616 #define regDP_AUX4_AUX_DPHY_RX_CONTROL0_BASE_IDX 2 11617 #define regDP_AUX4_AUX_DPHY_RX_CONTROL1 0x1fcb 11618 #define regDP_AUX4_AUX_DPHY_RX_CONTROL1_BASE_IDX 2 11619 #define regDP_AUX4_AUX_DPHY_TX_STATUS 0x1fcc 11620 #define regDP_AUX4_AUX_DPHY_TX_STATUS_BASE_IDX 2 11621 #define regDP_AUX4_AUX_DPHY_RX_STATUS 0x1fcd 11622 #define regDP_AUX4_AUX_DPHY_RX_STATUS_BASE_IDX 2 11623 #define regDP_AUX4_AUX_GTC_SYNC_CONTROL 0x1fce 11624 #define regDP_AUX4_AUX_GTC_SYNC_CONTROL_BASE_IDX 2 11625 #define regDP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL 0x1fcf 11626 #define regDP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL_BASE_IDX 2 11627 #define regDP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS 0x1fd0 11628 #define regDP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS_BASE_IDX 2 11629 #define regDP_AUX4_AUX_GTC_SYNC_STATUS 0x1fd1 11630 #define regDP_AUX4_AUX_GTC_SYNC_STATUS_BASE_IDX 2 11631 #define regDP_AUX4_AUX_PHY_WAKE_CNTL 0x1fd6 11632 #define regDP_AUX4_AUX_PHY_WAKE_CNTL_BASE_IDX 2 11633 11634 11635 // addressBlock: dce_dc_dio_dout_i2c_dispdec 11636 // base address: 0x0 11637 #define regDC_I2C_CONTROL 0x1e98 11638 #define regDC_I2C_CONTROL_BASE_IDX 2 11639 #define regDC_I2C_ARBITRATION 0x1e99 11640 #define regDC_I2C_ARBITRATION_BASE_IDX 2 11641 #define regDC_I2C_INTERRUPT_CONTROL 0x1e9a 11642 #define regDC_I2C_INTERRUPT_CONTROL_BASE_IDX 2 11643 #define regDC_I2C_SW_STATUS 0x1e9b 11644 #define regDC_I2C_SW_STATUS_BASE_IDX 2 11645 #define regDC_I2C_DDC1_HW_STATUS 0x1e9c 11646 #define regDC_I2C_DDC1_HW_STATUS_BASE_IDX 2 11647 #define regDC_I2C_DDC2_HW_STATUS 0x1e9d 11648 #define regDC_I2C_DDC2_HW_STATUS_BASE_IDX 2 11649 #define regDC_I2C_DDC3_HW_STATUS 0x1e9e 11650 #define regDC_I2C_DDC3_HW_STATUS_BASE_IDX 2 11651 #define regDC_I2C_DDC4_HW_STATUS 0x1e9f 11652 #define regDC_I2C_DDC4_HW_STATUS_BASE_IDX 2 11653 #define regDC_I2C_DDC5_HW_STATUS 0x1ea0 11654 #define regDC_I2C_DDC5_HW_STATUS_BASE_IDX 2 11655 #define regDC_I2C_DDC1_SPEED 0x1ea2 11656 #define regDC_I2C_DDC1_SPEED_BASE_IDX 2 11657 #define regDC_I2C_DDC1_SETUP 0x1ea3 11658 #define regDC_I2C_DDC1_SETUP_BASE_IDX 2 11659 #define regDC_I2C_DDC2_SPEED 0x1ea4 11660 #define regDC_I2C_DDC2_SPEED_BASE_IDX 2 11661 #define regDC_I2C_DDC2_SETUP 0x1ea5 11662 #define regDC_I2C_DDC2_SETUP_BASE_IDX 2 11663 #define regDC_I2C_DDC3_SPEED 0x1ea6 11664 #define regDC_I2C_DDC3_SPEED_BASE_IDX 2 11665 #define regDC_I2C_DDC3_SETUP 0x1ea7 11666 #define regDC_I2C_DDC3_SETUP_BASE_IDX 2 11667 #define regDC_I2C_DDC4_SPEED 0x1ea8 11668 #define regDC_I2C_DDC4_SPEED_BASE_IDX 2 11669 #define regDC_I2C_DDC4_SETUP 0x1ea9 11670 #define regDC_I2C_DDC4_SETUP_BASE_IDX 2 11671 #define regDC_I2C_DDC5_SPEED 0x1eaa 11672 #define regDC_I2C_DDC5_SPEED_BASE_IDX 2 11673 #define regDC_I2C_DDC5_SETUP 0x1eab 11674 #define regDC_I2C_DDC5_SETUP_BASE_IDX 2 11675 #define regDC_I2C_TRANSACTION0 0x1eae 11676 #define regDC_I2C_TRANSACTION0_BASE_IDX 2 11677 #define regDC_I2C_TRANSACTION1 0x1eaf 11678 #define regDC_I2C_TRANSACTION1_BASE_IDX 2 11679 #define regDC_I2C_TRANSACTION2 0x1eb0 11680 #define regDC_I2C_TRANSACTION2_BASE_IDX 2 11681 #define regDC_I2C_TRANSACTION3 0x1eb1 11682 #define regDC_I2C_TRANSACTION3_BASE_IDX 2 11683 #define regDC_I2C_DATA 0x1eb2 11684 #define regDC_I2C_DATA_BASE_IDX 2 11685 #define regDC_I2C_EDID_DETECT_CTRL 0x1eb6 11686 #define regDC_I2C_EDID_DETECT_CTRL_BASE_IDX 2 11687 #define regDC_I2C_READ_REQUEST_INTERRUPT 0x1eb7 11688 #define regDC_I2C_READ_REQUEST_INTERRUPT_BASE_IDX 2 11689 11690 11691 // addressBlock: dce_dc_dio_dio_misc_dispdec 11692 // base address: 0x0 11693 #define regDIO_SCRATCH0 0x1eca 11694 #define regDIO_SCRATCH0_BASE_IDX 2 11695 #define regDIO_SCRATCH1 0x1ecb 11696 #define regDIO_SCRATCH1_BASE_IDX 2 11697 #define regDIO_SCRATCH2 0x1ecc 11698 #define regDIO_SCRATCH2_BASE_IDX 2 11699 #define regDIO_SCRATCH3 0x1ecd 11700 #define regDIO_SCRATCH3_BASE_IDX 2 11701 #define regDIO_SCRATCH4 0x1ece 11702 #define regDIO_SCRATCH4_BASE_IDX 2 11703 #define regDIO_SCRATCH5 0x1ecf 11704 #define regDIO_SCRATCH5_BASE_IDX 2 11705 #define regDIO_SCRATCH6 0x1ed0 11706 #define regDIO_SCRATCH6_BASE_IDX 2 11707 #define regDIO_SCRATCH7 0x1ed1 11708 #define regDIO_SCRATCH7_BASE_IDX 2 11709 #define regDIO_MEM_PWR_STATUS 0x1edd 11710 #define regDIO_MEM_PWR_STATUS_BASE_IDX 2 11711 #define regDIO_MEM_PWR_CTRL 0x1ede 11712 #define regDIO_MEM_PWR_CTRL_BASE_IDX 2 11713 #define regDIO_MEM_PWR_CTRL2 0x1edf 11714 #define regDIO_MEM_PWR_CTRL2_BASE_IDX 2 11715 #define regDIO_CLK_CNTL 0x1ee0 11716 #define regDIO_CLK_CNTL_BASE_IDX 2 11717 #define regDIO_POWER_MANAGEMENT_CNTL 0x1ee4 11718 #define regDIO_POWER_MANAGEMENT_CNTL_BASE_IDX 2 11719 #define regDIG_SOFT_RESET 0x1eee 11720 #define regDIG_SOFT_RESET_BASE_IDX 2 11721 #define regDIO_CLK_CNTL2 0x1ef2 11722 #define regDIO_CLK_CNTL2_BASE_IDX 2 11723 #define regDIO_CLK_CNTL3 0x1ef3 11724 #define regDIO_CLK_CNTL3_BASE_IDX 2 11725 #define regDIO_HDMI_RXSTATUS_TIMER_CONTROL 0x1eff 11726 #define regDIO_HDMI_RXSTATUS_TIMER_CONTROL_BASE_IDX 2 11727 #define regDIO_GENERIC_INTERRUPT_MESSAGE 0x1f02 11728 #define regDIO_GENERIC_INTERRUPT_MESSAGE_BASE_IDX 2 11729 #define regDIO_GENERIC_INTERRUPT_CLEAR 0x1f03 11730 #define regDIO_GENERIC_INTERRUPT_CLEAR_BASE_IDX 2 11731 #define regDIO_LINKA_CNTL 0x1f04 11732 #define regDIO_LINKA_CNTL_BASE_IDX 2 11733 #define regDIO_LINKB_CNTL 0x1f05 11734 #define regDIO_LINKB_CNTL_BASE_IDX 2 11735 #define regDIO_LINKC_CNTL 0x1f06 11736 #define regDIO_LINKC_CNTL_BASE_IDX 2 11737 #define regDIO_LINKD_CNTL 0x1f07 11738 #define regDIO_LINKD_CNTL_BASE_IDX 2 11739 #define regDIO_LINKE_CNTL 0x1f08 11740 #define regDIO_LINKE_CNTL_BASE_IDX 2 11741 #define regDIO_LINKF_CNTL 0x1f09 11742 #define regDIO_LINKF_CNTL_BASE_IDX 2 11743 11744 11745 // addressBlock: dce_dc_dio_dio_dcperfmon_dc_perfmon_dispdec 11746 // base address: 0x7d10 11747 #define regDC_PERFMON18_PERFCOUNTER_CNTL 0x1f44 11748 #define regDC_PERFMON18_PERFCOUNTER_CNTL_BASE_IDX 2 11749 #define regDC_PERFMON18_PERFCOUNTER_CNTL2 0x1f45 11750 #define regDC_PERFMON18_PERFCOUNTER_CNTL2_BASE_IDX 2 11751 #define regDC_PERFMON18_PERFCOUNTER_STATE 0x1f46 11752 #define regDC_PERFMON18_PERFCOUNTER_STATE_BASE_IDX 2 11753 #define regDC_PERFMON18_PERFMON_CNTL 0x1f47 11754 #define regDC_PERFMON18_PERFMON_CNTL_BASE_IDX 2 11755 #define regDC_PERFMON18_PERFMON_CNTL2 0x1f48 11756 #define regDC_PERFMON18_PERFMON_CNTL2_BASE_IDX 2 11757 #define regDC_PERFMON18_PERFMON_CVALUE_INT_MISC 0x1f49 11758 #define regDC_PERFMON18_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 11759 #define regDC_PERFMON18_PERFMON_CVALUE_LOW 0x1f4a 11760 #define regDC_PERFMON18_PERFMON_CVALUE_LOW_BASE_IDX 2 11761 #define regDC_PERFMON18_PERFMON_HI 0x1f4b 11762 #define regDC_PERFMON18_PERFMON_HI_BASE_IDX 2 11763 #define regDC_PERFMON18_PERFMON_LOW 0x1f4c 11764 #define regDC_PERFMON18_PERFMON_LOW_BASE_IDX 2 11765 11766 11767 // addressBlock: dce_dc_dcio_dcio_dispdec 11768 // base address: 0x0 11769 #define regDC_GENERICA 0x2868 11770 #define regDC_GENERICA_BASE_IDX 2 11771 #define regDC_GENERICB 0x2869 11772 #define regDC_GENERICB_BASE_IDX 2 11773 #define regDCIO_CLOCK_CNTL 0x286a 11774 #define regDCIO_CLOCK_CNTL_BASE_IDX 2 11775 #define regDC_REF_CLK_CNTL 0x286b 11776 #define regDC_REF_CLK_CNTL_BASE_IDX 2 11777 #define regUNIPHYA_LINK_CNTL 0x286d 11778 #define regUNIPHYA_LINK_CNTL_BASE_IDX 2 11779 #define regUNIPHYA_CHANNEL_XBAR_CNTL 0x286e 11780 #define regUNIPHYA_CHANNEL_XBAR_CNTL_BASE_IDX 2 11781 #define regUNIPHYB_LINK_CNTL 0x286f 11782 #define regUNIPHYB_LINK_CNTL_BASE_IDX 2 11783 #define regUNIPHYB_CHANNEL_XBAR_CNTL 0x2870 11784 #define regUNIPHYB_CHANNEL_XBAR_CNTL_BASE_IDX 2 11785 #define regUNIPHYC_LINK_CNTL 0x2871 11786 #define regUNIPHYC_LINK_CNTL_BASE_IDX 2 11787 #define regUNIPHYC_CHANNEL_XBAR_CNTL 0x2872 11788 #define regUNIPHYC_CHANNEL_XBAR_CNTL_BASE_IDX 2 11789 #define regUNIPHYD_LINK_CNTL 0x2873 11790 #define regUNIPHYD_LINK_CNTL_BASE_IDX 2 11791 #define regUNIPHYD_CHANNEL_XBAR_CNTL 0x2874 11792 #define regUNIPHYD_CHANNEL_XBAR_CNTL_BASE_IDX 2 11793 #define regUNIPHYE_LINK_CNTL 0x2875 11794 #define regUNIPHYE_LINK_CNTL_BASE_IDX 2 11795 #define regUNIPHYE_CHANNEL_XBAR_CNTL 0x2876 11796 #define regUNIPHYE_CHANNEL_XBAR_CNTL_BASE_IDX 2 11797 #define regDCIO_WRCMD_DELAY 0x287e 11798 #define regDCIO_WRCMD_DELAY_BASE_IDX 2 11799 #define regDC_PINSTRAPS 0x2880 11800 #define regDC_PINSTRAPS_BASE_IDX 2 11801 #define regINTERCEPT_STATE 0x2884 11802 #define regINTERCEPT_STATE_BASE_IDX 2 11803 #define regDCIO_BL_PWM_FRAME_START_DISP_SEL 0x288b 11804 #define regDCIO_BL_PWM_FRAME_START_DISP_SEL_BASE_IDX 2 11805 #define regDCIO_GSL_GENLK_PAD_CNTL 0x288c 11806 #define regDCIO_GSL_GENLK_PAD_CNTL_BASE_IDX 2 11807 #define regDCIO_GSL_SWAPLOCK_PAD_CNTL 0x288d 11808 #define regDCIO_GSL_SWAPLOCK_PAD_CNTL_BASE_IDX 2 11809 #define regDCIO_SOFT_RESET 0x289e 11810 #define regDCIO_SOFT_RESET_BASE_IDX 2 11811 11812 11813 // addressBlock: dce_dc_dcio_dcio_chip_dispdec 11814 // base address: 0x0 11815 #define regDC_GPIO_GENERIC_MASK 0x28c8 11816 #define regDC_GPIO_GENERIC_MASK_BASE_IDX 2 11817 #define regDC_GPIO_GENERIC_A 0x28c9 11818 #define regDC_GPIO_GENERIC_A_BASE_IDX 2 11819 #define regDC_GPIO_GENERIC_EN 0x28ca 11820 #define regDC_GPIO_GENERIC_EN_BASE_IDX 2 11821 #define regDC_GPIO_GENERIC_Y 0x28cb 11822 #define regDC_GPIO_GENERIC_Y_BASE_IDX 2 11823 #define regDC_GPIO_DDC1_MASK 0x28d0 11824 #define regDC_GPIO_DDC1_MASK_BASE_IDX 2 11825 #define regDC_GPIO_DDC1_A 0x28d1 11826 #define regDC_GPIO_DDC1_A_BASE_IDX 2 11827 #define regDC_GPIO_DDC1_EN 0x28d2 11828 #define regDC_GPIO_DDC1_EN_BASE_IDX 2 11829 #define regDC_GPIO_DDC1_Y 0x28d3 11830 #define regDC_GPIO_DDC1_Y_BASE_IDX 2 11831 #define regDC_GPIO_DDC2_MASK 0x28d4 11832 #define regDC_GPIO_DDC2_MASK_BASE_IDX 2 11833 #define regDC_GPIO_DDC2_A 0x28d5 11834 #define regDC_GPIO_DDC2_A_BASE_IDX 2 11835 #define regDC_GPIO_DDC2_EN 0x28d6 11836 #define regDC_GPIO_DDC2_EN_BASE_IDX 2 11837 #define regDC_GPIO_DDC2_Y 0x28d7 11838 #define regDC_GPIO_DDC2_Y_BASE_IDX 2 11839 #define regDC_GPIO_DDC3_MASK 0x28d8 11840 #define regDC_GPIO_DDC3_MASK_BASE_IDX 2 11841 #define regDC_GPIO_DDC3_A 0x28d9 11842 #define regDC_GPIO_DDC3_A_BASE_IDX 2 11843 #define regDC_GPIO_DDC3_EN 0x28da 11844 #define regDC_GPIO_DDC3_EN_BASE_IDX 2 11845 #define regDC_GPIO_DDC3_Y 0x28db 11846 #define regDC_GPIO_DDC3_Y_BASE_IDX 2 11847 #define regDC_GPIO_DDC4_MASK 0x28dc 11848 #define regDC_GPIO_DDC4_MASK_BASE_IDX 2 11849 #define regDC_GPIO_DDC4_A 0x28dd 11850 #define regDC_GPIO_DDC4_A_BASE_IDX 2 11851 #define regDC_GPIO_DDC4_EN 0x28de 11852 #define regDC_GPIO_DDC4_EN_BASE_IDX 2 11853 #define regDC_GPIO_DDC4_Y 0x28df 11854 #define regDC_GPIO_DDC4_Y_BASE_IDX 2 11855 #define regDC_GPIO_DDC5_MASK 0x28e0 11856 #define regDC_GPIO_DDC5_MASK_BASE_IDX 2 11857 #define regDC_GPIO_DDC5_A 0x28e1 11858 #define regDC_GPIO_DDC5_A_BASE_IDX 2 11859 #define regDC_GPIO_DDC5_EN 0x28e2 11860 #define regDC_GPIO_DDC5_EN_BASE_IDX 2 11861 #define regDC_GPIO_DDC5_Y 0x28e3 11862 #define regDC_GPIO_DDC5_Y_BASE_IDX 2 11863 #define regDC_GPIO_DDCVGA_MASK 0x28e8 11864 #define regDC_GPIO_DDCVGA_MASK_BASE_IDX 2 11865 #define regDC_GPIO_DDCVGA_A 0x28e9 11866 #define regDC_GPIO_DDCVGA_A_BASE_IDX 2 11867 #define regDC_GPIO_DDCVGA_EN 0x28ea 11868 #define regDC_GPIO_DDCVGA_EN_BASE_IDX 2 11869 #define regDC_GPIO_DDCVGA_Y 0x28eb 11870 #define regDC_GPIO_DDCVGA_Y_BASE_IDX 2 11871 #define regDC_GPIO_GENLK_MASK 0x28f0 11872 #define regDC_GPIO_GENLK_MASK_BASE_IDX 2 11873 #define regDC_GPIO_GENLK_A 0x28f1 11874 #define regDC_GPIO_GENLK_A_BASE_IDX 2 11875 #define regDC_GPIO_GENLK_EN 0x28f2 11876 #define regDC_GPIO_GENLK_EN_BASE_IDX 2 11877 #define regDC_GPIO_GENLK_Y 0x28f3 11878 #define regDC_GPIO_GENLK_Y_BASE_IDX 2 11879 #define regDC_GPIO_HPD_MASK 0x28f4 11880 #define regDC_GPIO_HPD_MASK_BASE_IDX 2 11881 #define regDC_GPIO_HPD_A 0x28f5 11882 #define regDC_GPIO_HPD_A_BASE_IDX 2 11883 #define regDC_GPIO_HPD_EN 0x28f6 11884 #define regDC_GPIO_HPD_EN_BASE_IDX 2 11885 #define regDC_GPIO_HPD_Y 0x28f7 11886 #define regDC_GPIO_HPD_Y_BASE_IDX 2 11887 #define regDC_GPIO_PWRSEQ0_EN 0x28fa 11888 #define regDC_GPIO_PWRSEQ0_EN_BASE_IDX 2 11889 #define regDC_GPIO_PAD_STRENGTH_1 0x28fc 11890 #define regDC_GPIO_PAD_STRENGTH_1_BASE_IDX 2 11891 #define regDC_GPIO_PAD_STRENGTH_2 0x28fd 11892 #define regDC_GPIO_PAD_STRENGTH_2_BASE_IDX 2 11893 #define regPHY_AUX_CNTL 0x28ff 11894 #define regPHY_AUX_CNTL_BASE_IDX 2 11895 #define regDC_GPIO_PWRSEQ1_EN 0x2902 11896 #define regDC_GPIO_PWRSEQ1_EN_BASE_IDX 2 11897 #define regDC_GPIO_TX12_EN 0x2915 11898 #define regDC_GPIO_TX12_EN_BASE_IDX 2 11899 #define regDC_GPIO_AUX_CTRL_0 0x2916 11900 #define regDC_GPIO_AUX_CTRL_0_BASE_IDX 2 11901 #define regDC_GPIO_AUX_CTRL_1 0x2917 11902 #define regDC_GPIO_AUX_CTRL_1_BASE_IDX 2 11903 #define regDC_GPIO_AUX_CTRL_2 0x2918 11904 #define regDC_GPIO_AUX_CTRL_2_BASE_IDX 2 11905 #define regDC_GPIO_RXEN 0x2919 11906 #define regDC_GPIO_RXEN_BASE_IDX 2 11907 #define regDC_GPIO_PULLUPEN 0x291a 11908 #define regDC_GPIO_PULLUPEN_BASE_IDX 2 11909 #define regDC_GPIO_AUX_CTRL_3 0x291b 11910 #define regDC_GPIO_AUX_CTRL_3_BASE_IDX 2 11911 #define regDC_GPIO_AUX_CTRL_4 0x291c 11912 #define regDC_GPIO_AUX_CTRL_4_BASE_IDX 2 11913 #define regDC_GPIO_AUX_CTRL_5 0x291d 11914 #define regDC_GPIO_AUX_CTRL_5_BASE_IDX 2 11915 #define regAUXI2C_PAD_ALL_PWR_OK 0x291e 11916 #define regAUXI2C_PAD_ALL_PWR_OK_BASE_IDX 2 11917 11918 11919 // addressBlock: dce_dc_dcio_dcio_uniphy1_dispdec 11920 // base address: 0x360 11921 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED0 0x2a00 11922 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED0_BASE_IDX 2 11923 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED1 0x2a01 11924 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED1_BASE_IDX 2 11925 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED2 0x2a02 11926 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED2_BASE_IDX 2 11927 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED3 0x2a03 11928 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED3_BASE_IDX 2 11929 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED4 0x2a04 11930 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED4_BASE_IDX 2 11931 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED5 0x2a05 11932 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED5_BASE_IDX 2 11933 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED6 0x2a06 11934 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED6_BASE_IDX 2 11935 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED7 0x2a07 11936 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED7_BASE_IDX 2 11937 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED8 0x2a08 11938 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED8_BASE_IDX 2 11939 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED9 0x2a09 11940 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED9_BASE_IDX 2 11941 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED10 0x2a0a 11942 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED10_BASE_IDX 2 11943 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED11 0x2a0b 11944 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED11_BASE_IDX 2 11945 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED12 0x2a0c 11946 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED12_BASE_IDX 2 11947 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED13 0x2a0d 11948 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED13_BASE_IDX 2 11949 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED14 0x2a0e 11950 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED14_BASE_IDX 2 11951 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED15 0x2a0f 11952 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED15_BASE_IDX 2 11953 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED16 0x2a10 11954 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED16_BASE_IDX 2 11955 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED17 0x2a11 11956 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED17_BASE_IDX 2 11957 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED18 0x2a12 11958 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED18_BASE_IDX 2 11959 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED19 0x2a13 11960 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED19_BASE_IDX 2 11961 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED20 0x2a14 11962 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED20_BASE_IDX 2 11963 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED21 0x2a15 11964 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED21_BASE_IDX 2 11965 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED22 0x2a16 11966 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED22_BASE_IDX 2 11967 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED23 0x2a17 11968 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED23_BASE_IDX 2 11969 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED24 0x2a18 11970 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED24_BASE_IDX 2 11971 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED25 0x2a19 11972 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED25_BASE_IDX 2 11973 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED26 0x2a1a 11974 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED26_BASE_IDX 2 11975 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED27 0x2a1b 11976 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED27_BASE_IDX 2 11977 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED28 0x2a1c 11978 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED28_BASE_IDX 2 11979 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED29 0x2a1d 11980 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED29_BASE_IDX 2 11981 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED30 0x2a1e 11982 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED30_BASE_IDX 2 11983 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED31 0x2a1f 11984 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED31_BASE_IDX 2 11985 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED32 0x2a20 11986 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED32_BASE_IDX 2 11987 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED33 0x2a21 11988 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED33_BASE_IDX 2 11989 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED34 0x2a22 11990 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED34_BASE_IDX 2 11991 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED35 0x2a23 11992 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED35_BASE_IDX 2 11993 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED36 0x2a24 11994 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED36_BASE_IDX 2 11995 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED37 0x2a25 11996 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED37_BASE_IDX 2 11997 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED38 0x2a26 11998 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED38_BASE_IDX 2 11999 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED39 0x2a27 12000 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED39_BASE_IDX 2 12001 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED40 0x2a28 12002 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED40_BASE_IDX 2 12003 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED41 0x2a29 12004 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED41_BASE_IDX 2 12005 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED42 0x2a2a 12006 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED42_BASE_IDX 2 12007 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED43 0x2a2b 12008 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED43_BASE_IDX 2 12009 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED44 0x2a2c 12010 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED44_BASE_IDX 2 12011 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED45 0x2a2d 12012 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED45_BASE_IDX 2 12013 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED46 0x2a2e 12014 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED46_BASE_IDX 2 12015 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED47 0x2a2f 12016 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED47_BASE_IDX 2 12017 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED48 0x2a30 12018 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED48_BASE_IDX 2 12019 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED49 0x2a31 12020 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED49_BASE_IDX 2 12021 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED50 0x2a32 12022 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED50_BASE_IDX 2 12023 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED51 0x2a33 12024 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED51_BASE_IDX 2 12025 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED52 0x2a34 12026 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED52_BASE_IDX 2 12027 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED53 0x2a35 12028 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED53_BASE_IDX 2 12029 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED54 0x2a36 12030 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED54_BASE_IDX 2 12031 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED55 0x2a37 12032 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED55_BASE_IDX 2 12033 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED56 0x2a38 12034 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED56_BASE_IDX 2 12035 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED57 0x2a39 12036 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED57_BASE_IDX 2 12037 12038 12039 // addressBlock: dce_dc_dcio_dcio_uniphy2_dispdec 12040 // base address: 0x6c0 12041 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED0 0x2ad8 12042 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED0_BASE_IDX 2 12043 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED1 0x2ad9 12044 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED1_BASE_IDX 2 12045 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED2 0x2ada 12046 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED2_BASE_IDX 2 12047 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED3 0x2adb 12048 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED3_BASE_IDX 2 12049 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED4 0x2adc 12050 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED4_BASE_IDX 2 12051 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED5 0x2add 12052 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED5_BASE_IDX 2 12053 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED6 0x2ade 12054 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED6_BASE_IDX 2 12055 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED7 0x2adf 12056 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED7_BASE_IDX 2 12057 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED8 0x2ae0 12058 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED8_BASE_IDX 2 12059 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED9 0x2ae1 12060 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED9_BASE_IDX 2 12061 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED10 0x2ae2 12062 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED10_BASE_IDX 2 12063 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED11 0x2ae3 12064 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED11_BASE_IDX 2 12065 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED12 0x2ae4 12066 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED12_BASE_IDX 2 12067 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED13 0x2ae5 12068 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED13_BASE_IDX 2 12069 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED14 0x2ae6 12070 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED14_BASE_IDX 2 12071 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED15 0x2ae7 12072 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED15_BASE_IDX 2 12073 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED16 0x2ae8 12074 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED16_BASE_IDX 2 12075 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED17 0x2ae9 12076 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED17_BASE_IDX 2 12077 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED18 0x2aea 12078 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED18_BASE_IDX 2 12079 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED19 0x2aeb 12080 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED19_BASE_IDX 2 12081 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED20 0x2aec 12082 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED20_BASE_IDX 2 12083 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED21 0x2aed 12084 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED21_BASE_IDX 2 12085 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED22 0x2aee 12086 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED22_BASE_IDX 2 12087 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED23 0x2aef 12088 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED23_BASE_IDX 2 12089 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED24 0x2af0 12090 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED24_BASE_IDX 2 12091 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED25 0x2af1 12092 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED25_BASE_IDX 2 12093 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED26 0x2af2 12094 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED26_BASE_IDX 2 12095 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED27 0x2af3 12096 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED27_BASE_IDX 2 12097 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED28 0x2af4 12098 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED28_BASE_IDX 2 12099 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED29 0x2af5 12100 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED29_BASE_IDX 2 12101 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED30 0x2af6 12102 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED30_BASE_IDX 2 12103 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED31 0x2af7 12104 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED31_BASE_IDX 2 12105 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED32 0x2af8 12106 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED32_BASE_IDX 2 12107 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED33 0x2af9 12108 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED33_BASE_IDX 2 12109 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED34 0x2afa 12110 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED34_BASE_IDX 2 12111 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED35 0x2afb 12112 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED35_BASE_IDX 2 12113 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED36 0x2afc 12114 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED36_BASE_IDX 2 12115 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED37 0x2afd 12116 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED37_BASE_IDX 2 12117 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED38 0x2afe 12118 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED38_BASE_IDX 2 12119 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED39 0x2aff 12120 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED39_BASE_IDX 2 12121 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED40 0x2b00 12122 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED40_BASE_IDX 2 12123 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED41 0x2b01 12124 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED41_BASE_IDX 2 12125 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED42 0x2b02 12126 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED42_BASE_IDX 2 12127 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED43 0x2b03 12128 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED43_BASE_IDX 2 12129 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED44 0x2b04 12130 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED44_BASE_IDX 2 12131 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED45 0x2b05 12132 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED45_BASE_IDX 2 12133 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED46 0x2b06 12134 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED46_BASE_IDX 2 12135 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED47 0x2b07 12136 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED47_BASE_IDX 2 12137 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED48 0x2b08 12138 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED48_BASE_IDX 2 12139 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED49 0x2b09 12140 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED49_BASE_IDX 2 12141 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED50 0x2b0a 12142 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED50_BASE_IDX 2 12143 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED51 0x2b0b 12144 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED51_BASE_IDX 2 12145 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED52 0x2b0c 12146 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED52_BASE_IDX 2 12147 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED53 0x2b0d 12148 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED53_BASE_IDX 2 12149 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED54 0x2b0e 12150 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED54_BASE_IDX 2 12151 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED55 0x2b0f 12152 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED55_BASE_IDX 2 12153 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED56 0x2b10 12154 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED56_BASE_IDX 2 12155 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED57 0x2b11 12156 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED57_BASE_IDX 2 12157 12158 12159 // addressBlock: dce_dc_dcio_dcio_uniphy3_dispdec 12160 // base address: 0xa20 12161 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED0 0x2bb0 12162 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED0_BASE_IDX 2 12163 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED1 0x2bb1 12164 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED1_BASE_IDX 2 12165 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED2 0x2bb2 12166 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED2_BASE_IDX 2 12167 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED3 0x2bb3 12168 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED3_BASE_IDX 2 12169 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED4 0x2bb4 12170 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED4_BASE_IDX 2 12171 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED5 0x2bb5 12172 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED5_BASE_IDX 2 12173 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED6 0x2bb6 12174 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED6_BASE_IDX 2 12175 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED7 0x2bb7 12176 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED7_BASE_IDX 2 12177 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED8 0x2bb8 12178 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED8_BASE_IDX 2 12179 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED9 0x2bb9 12180 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED9_BASE_IDX 2 12181 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED10 0x2bba 12182 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED10_BASE_IDX 2 12183 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED11 0x2bbb 12184 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED11_BASE_IDX 2 12185 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED12 0x2bbc 12186 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED12_BASE_IDX 2 12187 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED13 0x2bbd 12188 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED13_BASE_IDX 2 12189 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED14 0x2bbe 12190 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED14_BASE_IDX 2 12191 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED15 0x2bbf 12192 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED15_BASE_IDX 2 12193 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED16 0x2bc0 12194 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED16_BASE_IDX 2 12195 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED17 0x2bc1 12196 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED17_BASE_IDX 2 12197 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED18 0x2bc2 12198 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED18_BASE_IDX 2 12199 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED19 0x2bc3 12200 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED19_BASE_IDX 2 12201 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED20 0x2bc4 12202 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED20_BASE_IDX 2 12203 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED21 0x2bc5 12204 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED21_BASE_IDX 2 12205 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED22 0x2bc6 12206 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED22_BASE_IDX 2 12207 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED23 0x2bc7 12208 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED23_BASE_IDX 2 12209 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED24 0x2bc8 12210 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED24_BASE_IDX 2 12211 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED25 0x2bc9 12212 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED25_BASE_IDX 2 12213 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED26 0x2bca 12214 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED26_BASE_IDX 2 12215 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED27 0x2bcb 12216 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED27_BASE_IDX 2 12217 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED28 0x2bcc 12218 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED28_BASE_IDX 2 12219 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED29 0x2bcd 12220 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED29_BASE_IDX 2 12221 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED30 0x2bce 12222 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED30_BASE_IDX 2 12223 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED31 0x2bcf 12224 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED31_BASE_IDX 2 12225 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED32 0x2bd0 12226 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED32_BASE_IDX 2 12227 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED33 0x2bd1 12228 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED33_BASE_IDX 2 12229 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED34 0x2bd2 12230 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED34_BASE_IDX 2 12231 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED35 0x2bd3 12232 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED35_BASE_IDX 2 12233 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED36 0x2bd4 12234 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED36_BASE_IDX 2 12235 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED37 0x2bd5 12236 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED37_BASE_IDX 2 12237 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED38 0x2bd6 12238 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED38_BASE_IDX 2 12239 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED39 0x2bd7 12240 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED39_BASE_IDX 2 12241 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED40 0x2bd8 12242 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED40_BASE_IDX 2 12243 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED41 0x2bd9 12244 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED41_BASE_IDX 2 12245 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED42 0x2bda 12246 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED42_BASE_IDX 2 12247 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED43 0x2bdb 12248 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED43_BASE_IDX 2 12249 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED44 0x2bdc 12250 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED44_BASE_IDX 2 12251 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED45 0x2bdd 12252 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED45_BASE_IDX 2 12253 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED46 0x2bde 12254 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED46_BASE_IDX 2 12255 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED47 0x2bdf 12256 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED47_BASE_IDX 2 12257 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED48 0x2be0 12258 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED48_BASE_IDX 2 12259 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED49 0x2be1 12260 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED49_BASE_IDX 2 12261 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED50 0x2be2 12262 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED50_BASE_IDX 2 12263 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED51 0x2be3 12264 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED51_BASE_IDX 2 12265 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED52 0x2be4 12266 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED52_BASE_IDX 2 12267 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED53 0x2be5 12268 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED53_BASE_IDX 2 12269 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED54 0x2be6 12270 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED54_BASE_IDX 2 12271 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED55 0x2be7 12272 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED55_BASE_IDX 2 12273 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED56 0x2be8 12274 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED56_BASE_IDX 2 12275 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED57 0x2be9 12276 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED57_BASE_IDX 2 12277 12278 12279 // addressBlock: dce_dc_dcio_dcio_uniphy4_dispdec 12280 // base address: 0xd80 12281 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED0 0x2c88 12282 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED0_BASE_IDX 2 12283 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED1 0x2c89 12284 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED1_BASE_IDX 2 12285 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED2 0x2c8a 12286 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED2_BASE_IDX 2 12287 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED3 0x2c8b 12288 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED3_BASE_IDX 2 12289 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED4 0x2c8c 12290 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED4_BASE_IDX 2 12291 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED5 0x2c8d 12292 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED5_BASE_IDX 2 12293 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED6 0x2c8e 12294 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED6_BASE_IDX 2 12295 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED7 0x2c8f 12296 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED7_BASE_IDX 2 12297 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED8 0x2c90 12298 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED8_BASE_IDX 2 12299 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED9 0x2c91 12300 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED9_BASE_IDX 2 12301 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED10 0x2c92 12302 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED10_BASE_IDX 2 12303 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED11 0x2c93 12304 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED11_BASE_IDX 2 12305 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED12 0x2c94 12306 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED12_BASE_IDX 2 12307 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED13 0x2c95 12308 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED13_BASE_IDX 2 12309 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED14 0x2c96 12310 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED14_BASE_IDX 2 12311 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED15 0x2c97 12312 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED15_BASE_IDX 2 12313 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED16 0x2c98 12314 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED16_BASE_IDX 2 12315 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED17 0x2c99 12316 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED17_BASE_IDX 2 12317 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED18 0x2c9a 12318 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED18_BASE_IDX 2 12319 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED19 0x2c9b 12320 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED19_BASE_IDX 2 12321 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED20 0x2c9c 12322 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED20_BASE_IDX 2 12323 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED21 0x2c9d 12324 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED21_BASE_IDX 2 12325 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED22 0x2c9e 12326 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED22_BASE_IDX 2 12327 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED23 0x2c9f 12328 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED23_BASE_IDX 2 12329 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED24 0x2ca0 12330 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED24_BASE_IDX 2 12331 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED25 0x2ca1 12332 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED25_BASE_IDX 2 12333 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED26 0x2ca2 12334 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED26_BASE_IDX 2 12335 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED27 0x2ca3 12336 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED27_BASE_IDX 2 12337 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED28 0x2ca4 12338 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED28_BASE_IDX 2 12339 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED29 0x2ca5 12340 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED29_BASE_IDX 2 12341 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED30 0x2ca6 12342 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED30_BASE_IDX 2 12343 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED31 0x2ca7 12344 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED31_BASE_IDX 2 12345 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED32 0x2ca8 12346 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED32_BASE_IDX 2 12347 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED33 0x2ca9 12348 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED33_BASE_IDX 2 12349 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED34 0x2caa 12350 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED34_BASE_IDX 2 12351 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED35 0x2cab 12352 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED35_BASE_IDX 2 12353 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED36 0x2cac 12354 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED36_BASE_IDX 2 12355 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED37 0x2cad 12356 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED37_BASE_IDX 2 12357 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED38 0x2cae 12358 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED38_BASE_IDX 2 12359 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED39 0x2caf 12360 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED39_BASE_IDX 2 12361 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED40 0x2cb0 12362 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED40_BASE_IDX 2 12363 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED41 0x2cb1 12364 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED41_BASE_IDX 2 12365 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED42 0x2cb2 12366 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED42_BASE_IDX 2 12367 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED43 0x2cb3 12368 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED43_BASE_IDX 2 12369 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED44 0x2cb4 12370 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED44_BASE_IDX 2 12371 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED45 0x2cb5 12372 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED45_BASE_IDX 2 12373 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED46 0x2cb6 12374 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED46_BASE_IDX 2 12375 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED47 0x2cb7 12376 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED47_BASE_IDX 2 12377 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED48 0x2cb8 12378 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED48_BASE_IDX 2 12379 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED49 0x2cb9 12380 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED49_BASE_IDX 2 12381 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED50 0x2cba 12382 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED50_BASE_IDX 2 12383 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED51 0x2cbb 12384 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED51_BASE_IDX 2 12385 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED52 0x2cbc 12386 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED52_BASE_IDX 2 12387 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED53 0x2cbd 12388 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED53_BASE_IDX 2 12389 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED54 0x2cbe 12390 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED54_BASE_IDX 2 12391 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED55 0x2cbf 12392 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED55_BASE_IDX 2 12393 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED56 0x2cc0 12394 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED56_BASE_IDX 2 12395 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED57 0x2cc1 12396 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED57_BASE_IDX 2 12397 12398 12399 // addressBlock: dce_dc_pwrseq0_dispdec_pwrseq_dispdec 12400 // base address: 0x0 12401 #define regPWRSEQ0_DC_GPIO_PWRSEQ_EN 0x2f10 12402 #define regPWRSEQ0_DC_GPIO_PWRSEQ_EN_BASE_IDX 2 12403 #define regPWRSEQ0_DC_GPIO_PWRSEQ_CTRL 0x2f11 12404 #define regPWRSEQ0_DC_GPIO_PWRSEQ_CTRL_BASE_IDX 2 12405 #define regPWRSEQ0_DC_GPIO_PWRSEQ_MASK 0x2f12 12406 #define regPWRSEQ0_DC_GPIO_PWRSEQ_MASK_BASE_IDX 2 12407 #define regPWRSEQ0_DC_GPIO_PWRSEQ_A_Y 0x2f13 12408 #define regPWRSEQ0_DC_GPIO_PWRSEQ_A_Y_BASE_IDX 2 12409 #define regPWRSEQ0_PANEL_PWRSEQ_CNTL 0x2f14 12410 #define regPWRSEQ0_PANEL_PWRSEQ_CNTL_BASE_IDX 2 12411 #define regPWRSEQ0_PANEL_PWRSEQ_STATE 0x2f15 12412 #define regPWRSEQ0_PANEL_PWRSEQ_STATE_BASE_IDX 2 12413 #define regPWRSEQ0_PANEL_PWRSEQ_DELAY1 0x2f16 12414 #define regPWRSEQ0_PANEL_PWRSEQ_DELAY1_BASE_IDX 2 12415 #define regPWRSEQ0_PANEL_PWRSEQ_DELAY2 0x2f17 12416 #define regPWRSEQ0_PANEL_PWRSEQ_DELAY2_BASE_IDX 2 12417 #define regPWRSEQ0_PANEL_PWRSEQ_REF_DIV1 0x2f18 12418 #define regPWRSEQ0_PANEL_PWRSEQ_REF_DIV1_BASE_IDX 2 12419 #define regPWRSEQ0_BL_PWM_CNTL 0x2f19 12420 #define regPWRSEQ0_BL_PWM_CNTL_BASE_IDX 2 12421 #define regPWRSEQ0_BL_PWM_CNTL2 0x2f1a 12422 #define regPWRSEQ0_BL_PWM_CNTL2_BASE_IDX 2 12423 #define regPWRSEQ0_BL_PWM_PERIOD_CNTL 0x2f1b 12424 #define regPWRSEQ0_BL_PWM_PERIOD_CNTL_BASE_IDX 2 12425 #define regPWRSEQ0_BL_PWM_GRP1_REG_LOCK 0x2f1c 12426 #define regPWRSEQ0_BL_PWM_GRP1_REG_LOCK_BASE_IDX 2 12427 #define regPWRSEQ0_PANEL_PWRSEQ_REF_DIV2 0x2f1d 12428 #define regPWRSEQ0_PANEL_PWRSEQ_REF_DIV2_BASE_IDX 2 12429 #define regPWRSEQ0_PWRSEQ_SPARE 0x2f21 12430 #define regPWRSEQ0_PWRSEQ_SPARE_BASE_IDX 2 12431 12432 12433 // addressBlock: dce_dc_pwrseq1_dispdec_pwrseq_dispdec 12434 // base address: 0x1b0 12435 #define regPWRSEQ1_DC_GPIO_PWRSEQ_EN 0x2f7c 12436 #define regPWRSEQ1_DC_GPIO_PWRSEQ_EN_BASE_IDX 2 12437 #define regPWRSEQ1_DC_GPIO_PWRSEQ_CTRL 0x2f7d 12438 #define regPWRSEQ1_DC_GPIO_PWRSEQ_CTRL_BASE_IDX 2 12439 #define regPWRSEQ1_DC_GPIO_PWRSEQ_MASK 0x2f7e 12440 #define regPWRSEQ1_DC_GPIO_PWRSEQ_MASK_BASE_IDX 2 12441 #define regPWRSEQ1_DC_GPIO_PWRSEQ_A_Y 0x2f7f 12442 #define regPWRSEQ1_DC_GPIO_PWRSEQ_A_Y_BASE_IDX 2 12443 #define regPWRSEQ1_PANEL_PWRSEQ_CNTL 0x2f80 12444 #define regPWRSEQ1_PANEL_PWRSEQ_CNTL_BASE_IDX 2 12445 #define regPWRSEQ1_PANEL_PWRSEQ_STATE 0x2f81 12446 #define regPWRSEQ1_PANEL_PWRSEQ_STATE_BASE_IDX 2 12447 #define regPWRSEQ1_PANEL_PWRSEQ_DELAY1 0x2f82 12448 #define regPWRSEQ1_PANEL_PWRSEQ_DELAY1_BASE_IDX 2 12449 #define regPWRSEQ1_PANEL_PWRSEQ_DELAY2 0x2f83 12450 #define regPWRSEQ1_PANEL_PWRSEQ_DELAY2_BASE_IDX 2 12451 #define regPWRSEQ1_PANEL_PWRSEQ_REF_DIV1 0x2f84 12452 #define regPWRSEQ1_PANEL_PWRSEQ_REF_DIV1_BASE_IDX 2 12453 #define regPWRSEQ1_BL_PWM_CNTL 0x2f85 12454 #define regPWRSEQ1_BL_PWM_CNTL_BASE_IDX 2 12455 #define regPWRSEQ1_BL_PWM_CNTL2 0x2f86 12456 #define regPWRSEQ1_BL_PWM_CNTL2_BASE_IDX 2 12457 #define regPWRSEQ1_BL_PWM_PERIOD_CNTL 0x2f87 12458 #define regPWRSEQ1_BL_PWM_PERIOD_CNTL_BASE_IDX 2 12459 #define regPWRSEQ1_BL_PWM_GRP1_REG_LOCK 0x2f88 12460 #define regPWRSEQ1_BL_PWM_GRP1_REG_LOCK_BASE_IDX 2 12461 #define regPWRSEQ1_PANEL_PWRSEQ_REF_DIV2 0x2f89 12462 #define regPWRSEQ1_PANEL_PWRSEQ_REF_DIV2_BASE_IDX 2 12463 #define regPWRSEQ1_PWRSEQ_SPARE 0x2f8d 12464 #define regPWRSEQ1_PWRSEQ_SPARE_BASE_IDX 2 12465 12466 12467 // addressBlock: dce_dc_dsc0_dispdec_dscc_dispdec 12468 // base address: 0x0 12469 #define regDSCC0_DSCC_CONFIG0 0x300a 12470 #define regDSCC0_DSCC_CONFIG0_BASE_IDX 2 12471 #define regDSCC0_DSCC_CONFIG1 0x300b 12472 #define regDSCC0_DSCC_CONFIG1_BASE_IDX 2 12473 #define regDSCC0_DSCC_STATUS 0x300c 12474 #define regDSCC0_DSCC_STATUS_BASE_IDX 2 12475 #define regDSCC0_DSCC_INTERRUPT_CONTROL_STATUS 0x300d 12476 #define regDSCC0_DSCC_INTERRUPT_CONTROL_STATUS_BASE_IDX 2 12477 #define regDSCC0_DSCC_PPS_CONFIG0 0x300e 12478 #define regDSCC0_DSCC_PPS_CONFIG0_BASE_IDX 2 12479 #define regDSCC0_DSCC_PPS_CONFIG1 0x300f 12480 #define regDSCC0_DSCC_PPS_CONFIG1_BASE_IDX 2 12481 #define regDSCC0_DSCC_PPS_CONFIG2 0x3010 12482 #define regDSCC0_DSCC_PPS_CONFIG2_BASE_IDX 2 12483 #define regDSCC0_DSCC_PPS_CONFIG3 0x3011 12484 #define regDSCC0_DSCC_PPS_CONFIG3_BASE_IDX 2 12485 #define regDSCC0_DSCC_PPS_CONFIG4 0x3012 12486 #define regDSCC0_DSCC_PPS_CONFIG4_BASE_IDX 2 12487 #define regDSCC0_DSCC_PPS_CONFIG5 0x3013 12488 #define regDSCC0_DSCC_PPS_CONFIG5_BASE_IDX 2 12489 #define regDSCC0_DSCC_PPS_CONFIG6 0x3014 12490 #define regDSCC0_DSCC_PPS_CONFIG6_BASE_IDX 2 12491 #define regDSCC0_DSCC_PPS_CONFIG7 0x3015 12492 #define regDSCC0_DSCC_PPS_CONFIG7_BASE_IDX 2 12493 #define regDSCC0_DSCC_PPS_CONFIG8 0x3016 12494 #define regDSCC0_DSCC_PPS_CONFIG8_BASE_IDX 2 12495 #define regDSCC0_DSCC_PPS_CONFIG9 0x3017 12496 #define regDSCC0_DSCC_PPS_CONFIG9_BASE_IDX 2 12497 #define regDSCC0_DSCC_PPS_CONFIG10 0x3018 12498 #define regDSCC0_DSCC_PPS_CONFIG10_BASE_IDX 2 12499 #define regDSCC0_DSCC_PPS_CONFIG11 0x3019 12500 #define regDSCC0_DSCC_PPS_CONFIG11_BASE_IDX 2 12501 #define regDSCC0_DSCC_PPS_CONFIG12 0x301a 12502 #define regDSCC0_DSCC_PPS_CONFIG12_BASE_IDX 2 12503 #define regDSCC0_DSCC_PPS_CONFIG13 0x301b 12504 #define regDSCC0_DSCC_PPS_CONFIG13_BASE_IDX 2 12505 #define regDSCC0_DSCC_PPS_CONFIG14 0x301c 12506 #define regDSCC0_DSCC_PPS_CONFIG14_BASE_IDX 2 12507 #define regDSCC0_DSCC_PPS_CONFIG15 0x301d 12508 #define regDSCC0_DSCC_PPS_CONFIG15_BASE_IDX 2 12509 #define regDSCC0_DSCC_PPS_CONFIG16 0x301e 12510 #define regDSCC0_DSCC_PPS_CONFIG16_BASE_IDX 2 12511 #define regDSCC0_DSCC_PPS_CONFIG17 0x301f 12512 #define regDSCC0_DSCC_PPS_CONFIG17_BASE_IDX 2 12513 #define regDSCC0_DSCC_PPS_CONFIG18 0x3020 12514 #define regDSCC0_DSCC_PPS_CONFIG18_BASE_IDX 2 12515 #define regDSCC0_DSCC_PPS_CONFIG19 0x3021 12516 #define regDSCC0_DSCC_PPS_CONFIG19_BASE_IDX 2 12517 #define regDSCC0_DSCC_PPS_CONFIG20 0x3022 12518 #define regDSCC0_DSCC_PPS_CONFIG20_BASE_IDX 2 12519 #define regDSCC0_DSCC_PPS_CONFIG21 0x3023 12520 #define regDSCC0_DSCC_PPS_CONFIG21_BASE_IDX 2 12521 #define regDSCC0_DSCC_PPS_CONFIG22 0x3024 12522 #define regDSCC0_DSCC_PPS_CONFIG22_BASE_IDX 2 12523 #define regDSCC0_DSCC_MEM_POWER_CONTROL 0x3025 12524 #define regDSCC0_DSCC_MEM_POWER_CONTROL_BASE_IDX 2 12525 #define regDSCC0_DSCC_R_Y_SQUARED_ERROR_LOWER 0x3026 12526 #define regDSCC0_DSCC_R_Y_SQUARED_ERROR_LOWER_BASE_IDX 2 12527 #define regDSCC0_DSCC_R_Y_SQUARED_ERROR_UPPER 0x3027 12528 #define regDSCC0_DSCC_R_Y_SQUARED_ERROR_UPPER_BASE_IDX 2 12529 #define regDSCC0_DSCC_G_CB_SQUARED_ERROR_LOWER 0x3028 12530 #define regDSCC0_DSCC_G_CB_SQUARED_ERROR_LOWER_BASE_IDX 2 12531 #define regDSCC0_DSCC_G_CB_SQUARED_ERROR_UPPER 0x3029 12532 #define regDSCC0_DSCC_G_CB_SQUARED_ERROR_UPPER_BASE_IDX 2 12533 #define regDSCC0_DSCC_B_CR_SQUARED_ERROR_LOWER 0x302a 12534 #define regDSCC0_DSCC_B_CR_SQUARED_ERROR_LOWER_BASE_IDX 2 12535 #define regDSCC0_DSCC_B_CR_SQUARED_ERROR_UPPER 0x302b 12536 #define regDSCC0_DSCC_B_CR_SQUARED_ERROR_UPPER_BASE_IDX 2 12537 #define regDSCC0_DSCC_MAX_ABS_ERROR0 0x302c 12538 #define regDSCC0_DSCC_MAX_ABS_ERROR0_BASE_IDX 2 12539 #define regDSCC0_DSCC_MAX_ABS_ERROR1 0x302d 12540 #define regDSCC0_DSCC_MAX_ABS_ERROR1_BASE_IDX 2 12541 #define regDSCC0_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL 0x302e 12542 #define regDSCC0_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX 2 12543 #define regDSCC0_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL 0x302f 12544 #define regDSCC0_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX 2 12545 #define regDSCC0_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL 0x3030 12546 #define regDSCC0_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX 2 12547 #define regDSCC0_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL 0x3031 12548 #define regDSCC0_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX 2 12549 #define regDSCC0_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL 0x3032 12550 #define regDSCC0_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX 2 12551 #define regDSCC0_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL 0x3033 12552 #define regDSCC0_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX 2 12553 #define regDSCC0_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL 0x3034 12554 #define regDSCC0_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX 2 12555 #define regDSCC0_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL 0x3035 12556 #define regDSCC0_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX 2 12557 #define regDSCC0_DSCC_TEST_DEBUG_BUS_ROTATE 0x303a 12558 #define regDSCC0_DSCC_TEST_DEBUG_BUS_ROTATE_BASE_IDX 2 12559 12560 12561 // addressBlock: dce_dc_dsc0_dispdec_dsccif_dispdec 12562 // base address: 0x0 12563 #define regDSCCIF0_DSCCIF_CONFIG0 0x3005 12564 #define regDSCCIF0_DSCCIF_CONFIG0_BASE_IDX 2 12565 #define regDSCCIF0_DSCCIF_CONFIG1 0x3006 12566 #define regDSCCIF0_DSCCIF_CONFIG1_BASE_IDX 2 12567 12568 12569 // addressBlock: dce_dc_dsc0_dispdec_dsc_top_dispdec 12570 // base address: 0x0 12571 #define regDSC_TOP0_DSC_TOP_CONTROL 0x3000 12572 #define regDSC_TOP0_DSC_TOP_CONTROL_BASE_IDX 2 12573 #define regDSC_TOP0_DSC_DEBUG_CONTROL 0x3001 12574 #define regDSC_TOP0_DSC_DEBUG_CONTROL_BASE_IDX 2 12575 12576 12577 // addressBlock: dce_dc_dsc0_dispdec_dsc_dcperfmon_dc_perfmon_dispdec 12578 // base address: 0xc140 12579 #define regDC_PERFMON19_PERFCOUNTER_CNTL 0x3050 12580 #define regDC_PERFMON19_PERFCOUNTER_CNTL_BASE_IDX 2 12581 #define regDC_PERFMON19_PERFCOUNTER_CNTL2 0x3051 12582 #define regDC_PERFMON19_PERFCOUNTER_CNTL2_BASE_IDX 2 12583 #define regDC_PERFMON19_PERFCOUNTER_STATE 0x3052 12584 #define regDC_PERFMON19_PERFCOUNTER_STATE_BASE_IDX 2 12585 #define regDC_PERFMON19_PERFMON_CNTL 0x3053 12586 #define regDC_PERFMON19_PERFMON_CNTL_BASE_IDX 2 12587 #define regDC_PERFMON19_PERFMON_CNTL2 0x3054 12588 #define regDC_PERFMON19_PERFMON_CNTL2_BASE_IDX 2 12589 #define regDC_PERFMON19_PERFMON_CVALUE_INT_MISC 0x3055 12590 #define regDC_PERFMON19_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 12591 #define regDC_PERFMON19_PERFMON_CVALUE_LOW 0x3056 12592 #define regDC_PERFMON19_PERFMON_CVALUE_LOW_BASE_IDX 2 12593 #define regDC_PERFMON19_PERFMON_HI 0x3057 12594 #define regDC_PERFMON19_PERFMON_HI_BASE_IDX 2 12595 #define regDC_PERFMON19_PERFMON_LOW 0x3058 12596 #define regDC_PERFMON19_PERFMON_LOW_BASE_IDX 2 12597 12598 12599 // addressBlock: dce_dc_dsc1_dispdec_dscc_dispdec 12600 // base address: 0x170 12601 #define regDSCC1_DSCC_CONFIG0 0x3066 12602 #define regDSCC1_DSCC_CONFIG0_BASE_IDX 2 12603 #define regDSCC1_DSCC_CONFIG1 0x3067 12604 #define regDSCC1_DSCC_CONFIG1_BASE_IDX 2 12605 #define regDSCC1_DSCC_STATUS 0x3068 12606 #define regDSCC1_DSCC_STATUS_BASE_IDX 2 12607 #define regDSCC1_DSCC_INTERRUPT_CONTROL_STATUS 0x3069 12608 #define regDSCC1_DSCC_INTERRUPT_CONTROL_STATUS_BASE_IDX 2 12609 #define regDSCC1_DSCC_PPS_CONFIG0 0x306a 12610 #define regDSCC1_DSCC_PPS_CONFIG0_BASE_IDX 2 12611 #define regDSCC1_DSCC_PPS_CONFIG1 0x306b 12612 #define regDSCC1_DSCC_PPS_CONFIG1_BASE_IDX 2 12613 #define regDSCC1_DSCC_PPS_CONFIG2 0x306c 12614 #define regDSCC1_DSCC_PPS_CONFIG2_BASE_IDX 2 12615 #define regDSCC1_DSCC_PPS_CONFIG3 0x306d 12616 #define regDSCC1_DSCC_PPS_CONFIG3_BASE_IDX 2 12617 #define regDSCC1_DSCC_PPS_CONFIG4 0x306e 12618 #define regDSCC1_DSCC_PPS_CONFIG4_BASE_IDX 2 12619 #define regDSCC1_DSCC_PPS_CONFIG5 0x306f 12620 #define regDSCC1_DSCC_PPS_CONFIG5_BASE_IDX 2 12621 #define regDSCC1_DSCC_PPS_CONFIG6 0x3070 12622 #define regDSCC1_DSCC_PPS_CONFIG6_BASE_IDX 2 12623 #define regDSCC1_DSCC_PPS_CONFIG7 0x3071 12624 #define regDSCC1_DSCC_PPS_CONFIG7_BASE_IDX 2 12625 #define regDSCC1_DSCC_PPS_CONFIG8 0x3072 12626 #define regDSCC1_DSCC_PPS_CONFIG8_BASE_IDX 2 12627 #define regDSCC1_DSCC_PPS_CONFIG9 0x3073 12628 #define regDSCC1_DSCC_PPS_CONFIG9_BASE_IDX 2 12629 #define regDSCC1_DSCC_PPS_CONFIG10 0x3074 12630 #define regDSCC1_DSCC_PPS_CONFIG10_BASE_IDX 2 12631 #define regDSCC1_DSCC_PPS_CONFIG11 0x3075 12632 #define regDSCC1_DSCC_PPS_CONFIG11_BASE_IDX 2 12633 #define regDSCC1_DSCC_PPS_CONFIG12 0x3076 12634 #define regDSCC1_DSCC_PPS_CONFIG12_BASE_IDX 2 12635 #define regDSCC1_DSCC_PPS_CONFIG13 0x3077 12636 #define regDSCC1_DSCC_PPS_CONFIG13_BASE_IDX 2 12637 #define regDSCC1_DSCC_PPS_CONFIG14 0x3078 12638 #define regDSCC1_DSCC_PPS_CONFIG14_BASE_IDX 2 12639 #define regDSCC1_DSCC_PPS_CONFIG15 0x3079 12640 #define regDSCC1_DSCC_PPS_CONFIG15_BASE_IDX 2 12641 #define regDSCC1_DSCC_PPS_CONFIG16 0x307a 12642 #define regDSCC1_DSCC_PPS_CONFIG16_BASE_IDX 2 12643 #define regDSCC1_DSCC_PPS_CONFIG17 0x307b 12644 #define regDSCC1_DSCC_PPS_CONFIG17_BASE_IDX 2 12645 #define regDSCC1_DSCC_PPS_CONFIG18 0x307c 12646 #define regDSCC1_DSCC_PPS_CONFIG18_BASE_IDX 2 12647 #define regDSCC1_DSCC_PPS_CONFIG19 0x307d 12648 #define regDSCC1_DSCC_PPS_CONFIG19_BASE_IDX 2 12649 #define regDSCC1_DSCC_PPS_CONFIG20 0x307e 12650 #define regDSCC1_DSCC_PPS_CONFIG20_BASE_IDX 2 12651 #define regDSCC1_DSCC_PPS_CONFIG21 0x307f 12652 #define regDSCC1_DSCC_PPS_CONFIG21_BASE_IDX 2 12653 #define regDSCC1_DSCC_PPS_CONFIG22 0x3080 12654 #define regDSCC1_DSCC_PPS_CONFIG22_BASE_IDX 2 12655 #define regDSCC1_DSCC_MEM_POWER_CONTROL 0x3081 12656 #define regDSCC1_DSCC_MEM_POWER_CONTROL_BASE_IDX 2 12657 #define regDSCC1_DSCC_R_Y_SQUARED_ERROR_LOWER 0x3082 12658 #define regDSCC1_DSCC_R_Y_SQUARED_ERROR_LOWER_BASE_IDX 2 12659 #define regDSCC1_DSCC_R_Y_SQUARED_ERROR_UPPER 0x3083 12660 #define regDSCC1_DSCC_R_Y_SQUARED_ERROR_UPPER_BASE_IDX 2 12661 #define regDSCC1_DSCC_G_CB_SQUARED_ERROR_LOWER 0x3084 12662 #define regDSCC1_DSCC_G_CB_SQUARED_ERROR_LOWER_BASE_IDX 2 12663 #define regDSCC1_DSCC_G_CB_SQUARED_ERROR_UPPER 0x3085 12664 #define regDSCC1_DSCC_G_CB_SQUARED_ERROR_UPPER_BASE_IDX 2 12665 #define regDSCC1_DSCC_B_CR_SQUARED_ERROR_LOWER 0x3086 12666 #define regDSCC1_DSCC_B_CR_SQUARED_ERROR_LOWER_BASE_IDX 2 12667 #define regDSCC1_DSCC_B_CR_SQUARED_ERROR_UPPER 0x3087 12668 #define regDSCC1_DSCC_B_CR_SQUARED_ERROR_UPPER_BASE_IDX 2 12669 #define regDSCC1_DSCC_MAX_ABS_ERROR0 0x3088 12670 #define regDSCC1_DSCC_MAX_ABS_ERROR0_BASE_IDX 2 12671 #define regDSCC1_DSCC_MAX_ABS_ERROR1 0x3089 12672 #define regDSCC1_DSCC_MAX_ABS_ERROR1_BASE_IDX 2 12673 #define regDSCC1_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL 0x308a 12674 #define regDSCC1_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX 2 12675 #define regDSCC1_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL 0x308b 12676 #define regDSCC1_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX 2 12677 #define regDSCC1_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL 0x308c 12678 #define regDSCC1_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX 2 12679 #define regDSCC1_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL 0x308d 12680 #define regDSCC1_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX 2 12681 #define regDSCC1_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL 0x308e 12682 #define regDSCC1_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX 2 12683 #define regDSCC1_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL 0x308f 12684 #define regDSCC1_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX 2 12685 #define regDSCC1_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL 0x3090 12686 #define regDSCC1_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX 2 12687 #define regDSCC1_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL 0x3091 12688 #define regDSCC1_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX 2 12689 #define regDSCC1_DSCC_TEST_DEBUG_BUS_ROTATE 0x3096 12690 #define regDSCC1_DSCC_TEST_DEBUG_BUS_ROTATE_BASE_IDX 2 12691 12692 12693 // addressBlock: dce_dc_dsc1_dispdec_dsccif_dispdec 12694 // base address: 0x170 12695 #define regDSCCIF1_DSCCIF_CONFIG0 0x3061 12696 #define regDSCCIF1_DSCCIF_CONFIG0_BASE_IDX 2 12697 #define regDSCCIF1_DSCCIF_CONFIG1 0x3062 12698 #define regDSCCIF1_DSCCIF_CONFIG1_BASE_IDX 2 12699 12700 12701 // addressBlock: dce_dc_dsc1_dispdec_dsc_top_dispdec 12702 // base address: 0x170 12703 #define regDSC_TOP1_DSC_TOP_CONTROL 0x305c 12704 #define regDSC_TOP1_DSC_TOP_CONTROL_BASE_IDX 2 12705 #define regDSC_TOP1_DSC_DEBUG_CONTROL 0x305d 12706 #define regDSC_TOP1_DSC_DEBUG_CONTROL_BASE_IDX 2 12707 12708 12709 // addressBlock: dce_dc_dsc1_dispdec_dsc_dcperfmon_dc_perfmon_dispdec 12710 // base address: 0xc2b0 12711 #define regDC_PERFMON20_PERFCOUNTER_CNTL 0x30ac 12712 #define regDC_PERFMON20_PERFCOUNTER_CNTL_BASE_IDX 2 12713 #define regDC_PERFMON20_PERFCOUNTER_CNTL2 0x30ad 12714 #define regDC_PERFMON20_PERFCOUNTER_CNTL2_BASE_IDX 2 12715 #define regDC_PERFMON20_PERFCOUNTER_STATE 0x30ae 12716 #define regDC_PERFMON20_PERFCOUNTER_STATE_BASE_IDX 2 12717 #define regDC_PERFMON20_PERFMON_CNTL 0x30af 12718 #define regDC_PERFMON20_PERFMON_CNTL_BASE_IDX 2 12719 #define regDC_PERFMON20_PERFMON_CNTL2 0x30b0 12720 #define regDC_PERFMON20_PERFMON_CNTL2_BASE_IDX 2 12721 #define regDC_PERFMON20_PERFMON_CVALUE_INT_MISC 0x30b1 12722 #define regDC_PERFMON20_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 12723 #define regDC_PERFMON20_PERFMON_CVALUE_LOW 0x30b2 12724 #define regDC_PERFMON20_PERFMON_CVALUE_LOW_BASE_IDX 2 12725 #define regDC_PERFMON20_PERFMON_HI 0x30b3 12726 #define regDC_PERFMON20_PERFMON_HI_BASE_IDX 2 12727 #define regDC_PERFMON20_PERFMON_LOW 0x30b4 12728 #define regDC_PERFMON20_PERFMON_LOW_BASE_IDX 2 12729 12730 12731 // addressBlock: dce_dc_dsc2_dispdec_dscc_dispdec 12732 // base address: 0x2e0 12733 #define regDSCC2_DSCC_CONFIG0 0x30c2 12734 #define regDSCC2_DSCC_CONFIG0_BASE_IDX 2 12735 #define regDSCC2_DSCC_CONFIG1 0x30c3 12736 #define regDSCC2_DSCC_CONFIG1_BASE_IDX 2 12737 #define regDSCC2_DSCC_STATUS 0x30c4 12738 #define regDSCC2_DSCC_STATUS_BASE_IDX 2 12739 #define regDSCC2_DSCC_INTERRUPT_CONTROL_STATUS 0x30c5 12740 #define regDSCC2_DSCC_INTERRUPT_CONTROL_STATUS_BASE_IDX 2 12741 #define regDSCC2_DSCC_PPS_CONFIG0 0x30c6 12742 #define regDSCC2_DSCC_PPS_CONFIG0_BASE_IDX 2 12743 #define regDSCC2_DSCC_PPS_CONFIG1 0x30c7 12744 #define regDSCC2_DSCC_PPS_CONFIG1_BASE_IDX 2 12745 #define regDSCC2_DSCC_PPS_CONFIG2 0x30c8 12746 #define regDSCC2_DSCC_PPS_CONFIG2_BASE_IDX 2 12747 #define regDSCC2_DSCC_PPS_CONFIG3 0x30c9 12748 #define regDSCC2_DSCC_PPS_CONFIG3_BASE_IDX 2 12749 #define regDSCC2_DSCC_PPS_CONFIG4 0x30ca 12750 #define regDSCC2_DSCC_PPS_CONFIG4_BASE_IDX 2 12751 #define regDSCC2_DSCC_PPS_CONFIG5 0x30cb 12752 #define regDSCC2_DSCC_PPS_CONFIG5_BASE_IDX 2 12753 #define regDSCC2_DSCC_PPS_CONFIG6 0x30cc 12754 #define regDSCC2_DSCC_PPS_CONFIG6_BASE_IDX 2 12755 #define regDSCC2_DSCC_PPS_CONFIG7 0x30cd 12756 #define regDSCC2_DSCC_PPS_CONFIG7_BASE_IDX 2 12757 #define regDSCC2_DSCC_PPS_CONFIG8 0x30ce 12758 #define regDSCC2_DSCC_PPS_CONFIG8_BASE_IDX 2 12759 #define regDSCC2_DSCC_PPS_CONFIG9 0x30cf 12760 #define regDSCC2_DSCC_PPS_CONFIG9_BASE_IDX 2 12761 #define regDSCC2_DSCC_PPS_CONFIG10 0x30d0 12762 #define regDSCC2_DSCC_PPS_CONFIG10_BASE_IDX 2 12763 #define regDSCC2_DSCC_PPS_CONFIG11 0x30d1 12764 #define regDSCC2_DSCC_PPS_CONFIG11_BASE_IDX 2 12765 #define regDSCC2_DSCC_PPS_CONFIG12 0x30d2 12766 #define regDSCC2_DSCC_PPS_CONFIG12_BASE_IDX 2 12767 #define regDSCC2_DSCC_PPS_CONFIG13 0x30d3 12768 #define regDSCC2_DSCC_PPS_CONFIG13_BASE_IDX 2 12769 #define regDSCC2_DSCC_PPS_CONFIG14 0x30d4 12770 #define regDSCC2_DSCC_PPS_CONFIG14_BASE_IDX 2 12771 #define regDSCC2_DSCC_PPS_CONFIG15 0x30d5 12772 #define regDSCC2_DSCC_PPS_CONFIG15_BASE_IDX 2 12773 #define regDSCC2_DSCC_PPS_CONFIG16 0x30d6 12774 #define regDSCC2_DSCC_PPS_CONFIG16_BASE_IDX 2 12775 #define regDSCC2_DSCC_PPS_CONFIG17 0x30d7 12776 #define regDSCC2_DSCC_PPS_CONFIG17_BASE_IDX 2 12777 #define regDSCC2_DSCC_PPS_CONFIG18 0x30d8 12778 #define regDSCC2_DSCC_PPS_CONFIG18_BASE_IDX 2 12779 #define regDSCC2_DSCC_PPS_CONFIG19 0x30d9 12780 #define regDSCC2_DSCC_PPS_CONFIG19_BASE_IDX 2 12781 #define regDSCC2_DSCC_PPS_CONFIG20 0x30da 12782 #define regDSCC2_DSCC_PPS_CONFIG20_BASE_IDX 2 12783 #define regDSCC2_DSCC_PPS_CONFIG21 0x30db 12784 #define regDSCC2_DSCC_PPS_CONFIG21_BASE_IDX 2 12785 #define regDSCC2_DSCC_PPS_CONFIG22 0x30dc 12786 #define regDSCC2_DSCC_PPS_CONFIG22_BASE_IDX 2 12787 #define regDSCC2_DSCC_MEM_POWER_CONTROL 0x30dd 12788 #define regDSCC2_DSCC_MEM_POWER_CONTROL_BASE_IDX 2 12789 #define regDSCC2_DSCC_R_Y_SQUARED_ERROR_LOWER 0x30de 12790 #define regDSCC2_DSCC_R_Y_SQUARED_ERROR_LOWER_BASE_IDX 2 12791 #define regDSCC2_DSCC_R_Y_SQUARED_ERROR_UPPER 0x30df 12792 #define regDSCC2_DSCC_R_Y_SQUARED_ERROR_UPPER_BASE_IDX 2 12793 #define regDSCC2_DSCC_G_CB_SQUARED_ERROR_LOWER 0x30e0 12794 #define regDSCC2_DSCC_G_CB_SQUARED_ERROR_LOWER_BASE_IDX 2 12795 #define regDSCC2_DSCC_G_CB_SQUARED_ERROR_UPPER 0x30e1 12796 #define regDSCC2_DSCC_G_CB_SQUARED_ERROR_UPPER_BASE_IDX 2 12797 #define regDSCC2_DSCC_B_CR_SQUARED_ERROR_LOWER 0x30e2 12798 #define regDSCC2_DSCC_B_CR_SQUARED_ERROR_LOWER_BASE_IDX 2 12799 #define regDSCC2_DSCC_B_CR_SQUARED_ERROR_UPPER 0x30e3 12800 #define regDSCC2_DSCC_B_CR_SQUARED_ERROR_UPPER_BASE_IDX 2 12801 #define regDSCC2_DSCC_MAX_ABS_ERROR0 0x30e4 12802 #define regDSCC2_DSCC_MAX_ABS_ERROR0_BASE_IDX 2 12803 #define regDSCC2_DSCC_MAX_ABS_ERROR1 0x30e5 12804 #define regDSCC2_DSCC_MAX_ABS_ERROR1_BASE_IDX 2 12805 #define regDSCC2_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL 0x30e6 12806 #define regDSCC2_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX 2 12807 #define regDSCC2_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL 0x30e7 12808 #define regDSCC2_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX 2 12809 #define regDSCC2_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL 0x30e8 12810 #define regDSCC2_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX 2 12811 #define regDSCC2_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL 0x30e9 12812 #define regDSCC2_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX 2 12813 #define regDSCC2_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL 0x30ea 12814 #define regDSCC2_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX 2 12815 #define regDSCC2_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL 0x30eb 12816 #define regDSCC2_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX 2 12817 #define regDSCC2_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL 0x30ec 12818 #define regDSCC2_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX 2 12819 #define regDSCC2_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL 0x30ed 12820 #define regDSCC2_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX 2 12821 #define regDSCC2_DSCC_TEST_DEBUG_BUS_ROTATE 0x30f2 12822 #define regDSCC2_DSCC_TEST_DEBUG_BUS_ROTATE_BASE_IDX 2 12823 12824 12825 // addressBlock: dce_dc_dsc2_dispdec_dsccif_dispdec 12826 // base address: 0x2e0 12827 #define regDSCCIF2_DSCCIF_CONFIG0 0x30bd 12828 #define regDSCCIF2_DSCCIF_CONFIG0_BASE_IDX 2 12829 #define regDSCCIF2_DSCCIF_CONFIG1 0x30be 12830 #define regDSCCIF2_DSCCIF_CONFIG1_BASE_IDX 2 12831 12832 12833 // addressBlock: dce_dc_dsc2_dispdec_dsc_top_dispdec 12834 // base address: 0x2e0 12835 #define regDSC_TOP2_DSC_TOP_CONTROL 0x30b8 12836 #define regDSC_TOP2_DSC_TOP_CONTROL_BASE_IDX 2 12837 #define regDSC_TOP2_DSC_DEBUG_CONTROL 0x30b9 12838 #define regDSC_TOP2_DSC_DEBUG_CONTROL_BASE_IDX 2 12839 12840 12841 // addressBlock: dce_dc_dsc2_dispdec_dsc_dcperfmon_dc_perfmon_dispdec 12842 // base address: 0xc420 12843 #define regDC_PERFMON21_PERFCOUNTER_CNTL 0x3108 12844 #define regDC_PERFMON21_PERFCOUNTER_CNTL_BASE_IDX 2 12845 #define regDC_PERFMON21_PERFCOUNTER_CNTL2 0x3109 12846 #define regDC_PERFMON21_PERFCOUNTER_CNTL2_BASE_IDX 2 12847 #define regDC_PERFMON21_PERFCOUNTER_STATE 0x310a 12848 #define regDC_PERFMON21_PERFCOUNTER_STATE_BASE_IDX 2 12849 #define regDC_PERFMON21_PERFMON_CNTL 0x310b 12850 #define regDC_PERFMON21_PERFMON_CNTL_BASE_IDX 2 12851 #define regDC_PERFMON21_PERFMON_CNTL2 0x310c 12852 #define regDC_PERFMON21_PERFMON_CNTL2_BASE_IDX 2 12853 #define regDC_PERFMON21_PERFMON_CVALUE_INT_MISC 0x310d 12854 #define regDC_PERFMON21_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 12855 #define regDC_PERFMON21_PERFMON_CVALUE_LOW 0x310e 12856 #define regDC_PERFMON21_PERFMON_CVALUE_LOW_BASE_IDX 2 12857 #define regDC_PERFMON21_PERFMON_HI 0x310f 12858 #define regDC_PERFMON21_PERFMON_HI_BASE_IDX 2 12859 #define regDC_PERFMON21_PERFMON_LOW 0x3110 12860 #define regDC_PERFMON21_PERFMON_LOW_BASE_IDX 2 12861 12862 12863 // addressBlock: dce_dc_hpo_hpo_top_dispdec 12864 // base address: 0x2790c 12865 #define regHPO_TOP_CLOCK_CONTROL 0x0e43 12866 #define regHPO_TOP_CLOCK_CONTROL_BASE_IDX 3 12867 #define regHPO_TOP_HW_CONTROL 0x0e4a 12868 #define regHPO_TOP_HW_CONTROL_BASE_IDX 3 12869 12870 12871 // addressBlock: dce_dc_hpo_dp_stream_mapper_dispdec 12872 // base address: 0x27958 12873 #define regDP_STREAM_MAPPER_CONTROL0 0x0e56 12874 #define regDP_STREAM_MAPPER_CONTROL0_BASE_IDX 3 12875 #define regDP_STREAM_MAPPER_CONTROL1 0x0e57 12876 #define regDP_STREAM_MAPPER_CONTROL1_BASE_IDX 3 12877 #define regDP_STREAM_MAPPER_CONTROL2 0x0e58 12878 #define regDP_STREAM_MAPPER_CONTROL2_BASE_IDX 3 12879 #define regDP_STREAM_MAPPER_CONTROL3 0x0e59 12880 #define regDP_STREAM_MAPPER_CONTROL3_BASE_IDX 3 12881 12882 12883 // addressBlock: dce_dc_hpo_hpo_dcperfmon_dc_perfmon_dispdec 12884 // base address: 0x1a698 12885 #define regDC_PERFMON22_PERFCOUNTER_CNTL 0x0e66 12886 #define regDC_PERFMON22_PERFCOUNTER_CNTL_BASE_IDX 3 12887 #define regDC_PERFMON22_PERFCOUNTER_CNTL2 0x0e67 12888 #define regDC_PERFMON22_PERFCOUNTER_CNTL2_BASE_IDX 3 12889 #define regDC_PERFMON22_PERFCOUNTER_STATE 0x0e68 12890 #define regDC_PERFMON22_PERFCOUNTER_STATE_BASE_IDX 3 12891 #define regDC_PERFMON22_PERFMON_CNTL 0x0e69 12892 #define regDC_PERFMON22_PERFMON_CNTL_BASE_IDX 3 12893 #define regDC_PERFMON22_PERFMON_CNTL2 0x0e6a 12894 #define regDC_PERFMON22_PERFMON_CNTL2_BASE_IDX 3 12895 #define regDC_PERFMON22_PERFMON_CVALUE_INT_MISC 0x0e6b 12896 #define regDC_PERFMON22_PERFMON_CVALUE_INT_MISC_BASE_IDX 3 12897 #define regDC_PERFMON22_PERFMON_CVALUE_LOW 0x0e6c 12898 #define regDC_PERFMON22_PERFMON_CVALUE_LOW_BASE_IDX 3 12899 #define regDC_PERFMON22_PERFMON_HI 0x0e6d 12900 #define regDC_PERFMON22_PERFMON_HI_BASE_IDX 3 12901 #define regDC_PERFMON22_PERFMON_LOW 0x0e6e 12902 #define regDC_PERFMON22_PERFMON_LOW_BASE_IDX 3 12903 12904 12905 // addressBlock: dce_dc_hpo_hdmi_stream_enc0_afmt_afmt_dispdec 12906 // base address: 0x2646c 12907 #define regAFMT5_AFMT_VBI_PACKET_CONTROL 0x091c 12908 #define regAFMT5_AFMT_VBI_PACKET_CONTROL_BASE_IDX 3 12909 #define regAFMT5_AFMT_AUDIO_PACKET_CONTROL2 0x091d 12910 #define regAFMT5_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX 3 12911 #define regAFMT5_AFMT_AUDIO_INFO0 0x091e 12912 #define regAFMT5_AFMT_AUDIO_INFO0_BASE_IDX 3 12913 #define regAFMT5_AFMT_AUDIO_INFO1 0x091f 12914 #define regAFMT5_AFMT_AUDIO_INFO1_BASE_IDX 3 12915 #define regAFMT5_AFMT_60958_0 0x0920 12916 #define regAFMT5_AFMT_60958_0_BASE_IDX 3 12917 #define regAFMT5_AFMT_60958_1 0x0921 12918 #define regAFMT5_AFMT_60958_1_BASE_IDX 3 12919 #define regAFMT5_AFMT_AUDIO_CRC_CONTROL 0x0922 12920 #define regAFMT5_AFMT_AUDIO_CRC_CONTROL_BASE_IDX 3 12921 #define regAFMT5_AFMT_RAMP_CONTROL0 0x0923 12922 #define regAFMT5_AFMT_RAMP_CONTROL0_BASE_IDX 3 12923 #define regAFMT5_AFMT_RAMP_CONTROL1 0x0924 12924 #define regAFMT5_AFMT_RAMP_CONTROL1_BASE_IDX 3 12925 #define regAFMT5_AFMT_RAMP_CONTROL2 0x0925 12926 #define regAFMT5_AFMT_RAMP_CONTROL2_BASE_IDX 3 12927 #define regAFMT5_AFMT_RAMP_CONTROL3 0x0926 12928 #define regAFMT5_AFMT_RAMP_CONTROL3_BASE_IDX 3 12929 #define regAFMT5_AFMT_60958_2 0x0927 12930 #define regAFMT5_AFMT_60958_2_BASE_IDX 3 12931 #define regAFMT5_AFMT_AUDIO_CRC_RESULT 0x0928 12932 #define regAFMT5_AFMT_AUDIO_CRC_RESULT_BASE_IDX 3 12933 #define regAFMT5_AFMT_STATUS 0x0929 12934 #define regAFMT5_AFMT_STATUS_BASE_IDX 3 12935 #define regAFMT5_AFMT_AUDIO_PACKET_CONTROL 0x092a 12936 #define regAFMT5_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX 3 12937 #define regAFMT5_AFMT_INFOFRAME_CONTROL0 0x092b 12938 #define regAFMT5_AFMT_INFOFRAME_CONTROL0_BASE_IDX 3 12939 #define regAFMT5_AFMT_INTERRUPT_STATUS 0x092c 12940 #define regAFMT5_AFMT_INTERRUPT_STATUS_BASE_IDX 3 12941 #define regAFMT5_AFMT_AUDIO_SRC_CONTROL 0x092d 12942 #define regAFMT5_AFMT_AUDIO_SRC_CONTROL_BASE_IDX 3 12943 #define regAFMT5_AFMT_MEM_PWR 0x092f 12944 #define regAFMT5_AFMT_MEM_PWR_BASE_IDX 3 12945 12946 12947 // addressBlock: dce_dc_hpo_hdmi_stream_enc0_dme_dme_dispdec 12948 // base address: 0x264f0 12949 #define regDME5_DME_CONTROL 0x093c 12950 #define regDME5_DME_CONTROL_BASE_IDX 3 12951 #define regDME5_DME_MEMORY_CONTROL 0x093d 12952 #define regDME5_DME_MEMORY_CONTROL_BASE_IDX 3 12953 12954 12955 // addressBlock: dce_dc_hpo_hdmi_stream_enc0_vpg_vpg_dispdec 12956 // base address: 0x264c4 12957 #define regVPG5_VPG_GENERIC_PACKET_ACCESS_CTRL 0x0931 12958 #define regVPG5_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX 3 12959 #define regVPG5_VPG_GENERIC_PACKET_DATA 0x0932 12960 #define regVPG5_VPG_GENERIC_PACKET_DATA_BASE_IDX 3 12961 #define regVPG5_VPG_GSP_FRAME_UPDATE_CTRL 0x0933 12962 #define regVPG5_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX 3 12963 #define regVPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL 0x0934 12964 #define regVPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX 3 12965 #define regVPG5_VPG_GENERIC_STATUS 0x0935 12966 #define regVPG5_VPG_GENERIC_STATUS_BASE_IDX 3 12967 #define regVPG5_VPG_MEM_PWR 0x0936 12968 #define regVPG5_VPG_MEM_PWR_BASE_IDX 3 12969 #define regVPG5_VPG_ISRC1_2_ACCESS_CTRL 0x0937 12970 #define regVPG5_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX 3 12971 #define regVPG5_VPG_ISRC1_2_DATA 0x0938 12972 #define regVPG5_VPG_ISRC1_2_DATA_BASE_IDX 3 12973 #define regVPG5_VPG_MPEG_INFO0 0x0939 12974 #define regVPG5_VPG_MPEG_INFO0_BASE_IDX 3 12975 #define regVPG5_VPG_MPEG_INFO1 0x093a 12976 #define regVPG5_VPG_MPEG_INFO1_BASE_IDX 3 12977 12978 12979 // addressBlock: dce_dc_hpo_dp_stream_enc0_dispdec 12980 // base address: 0x1ab8c 12981 #define regDP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_CONTROL 0x3623 12982 #define regDP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_CONTROL_BASE_IDX 2 12983 #define regDP_STREAM_ENC0_DP_STREAM_ENC_INPUT_MUX_CONTROL 0x3624 12984 #define regDP_STREAM_ENC0_DP_STREAM_ENC_INPUT_MUX_CONTROL_BASE_IDX 2 12985 #define regDP_STREAM_ENC0_DP_STREAM_ENC_AUDIO_CONTROL 0x3625 12986 #define regDP_STREAM_ENC0_DP_STREAM_ENC_AUDIO_CONTROL_BASE_IDX 2 12987 #define regDP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0 0x3626 12988 #define regDP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0_BASE_IDX 2 12989 #define regDP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1 0x3627 12990 #define regDP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1_BASE_IDX 2 12991 #define regDP_STREAM_ENC0_DP_STREAM_ENC_SPARE 0x3628 12992 #define regDP_STREAM_ENC0_DP_STREAM_ENC_SPARE_BASE_IDX 2 12993 12994 12995 // addressBlock: dce_dc_hpo_dp_stream_enc0_apg_apg_dispdec 12996 // base address: 0x1abc0 12997 #define regAPG0_APG_CONTROL 0x3630 12998 #define regAPG0_APG_CONTROL_BASE_IDX 2 12999 #define regAPG0_APG_CONTROL2 0x3631 13000 #define regAPG0_APG_CONTROL2_BASE_IDX 2 13001 #define regAPG0_APG_DBG_GEN_CONTROL 0x3632 13002 #define regAPG0_APG_DBG_GEN_CONTROL_BASE_IDX 2 13003 #define regAPG0_APG_PACKET_CONTROL 0x3633 13004 #define regAPG0_APG_PACKET_CONTROL_BASE_IDX 2 13005 #define regAPG0_APG_AUDIO_CRC_CONTROL 0x363a 13006 #define regAPG0_APG_AUDIO_CRC_CONTROL_BASE_IDX 2 13007 #define regAPG0_APG_AUDIO_CRC_CONTROL2 0x363b 13008 #define regAPG0_APG_AUDIO_CRC_CONTROL2_BASE_IDX 2 13009 #define regAPG0_APG_AUDIO_CRC_RESULT 0x363c 13010 #define regAPG0_APG_AUDIO_CRC_RESULT_BASE_IDX 2 13011 #define regAPG0_APG_STATUS 0x3641 13012 #define regAPG0_APG_STATUS_BASE_IDX 2 13013 #define regAPG0_APG_STATUS2 0x3642 13014 #define regAPG0_APG_STATUS2_BASE_IDX 2 13015 #define regAPG0_APG_MEM_PWR 0x3644 13016 #define regAPG0_APG_MEM_PWR_BASE_IDX 2 13017 #define regAPG0_APG_SPARE 0x3646 13018 #define regAPG0_APG_SPARE_BASE_IDX 2 13019 13020 13021 // addressBlock: dce_dc_hpo_dp_stream_enc0_dme_dme_dispdec 13022 // base address: 0x1ac38 13023 #define regDME6_DME_CONTROL 0x364e 13024 #define regDME6_DME_CONTROL_BASE_IDX 2 13025 #define regDME6_DME_MEMORY_CONTROL 0x364f 13026 #define regDME6_DME_MEMORY_CONTROL_BASE_IDX 2 13027 13028 13029 // addressBlock: dce_dc_hpo_dp_stream_enc0_vpg_vpg_dispdec 13030 // base address: 0x1ac44 13031 #define regVPG6_VPG_GENERIC_PACKET_ACCESS_CTRL 0x3651 13032 #define regVPG6_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX 2 13033 #define regVPG6_VPG_GENERIC_PACKET_DATA 0x3652 13034 #define regVPG6_VPG_GENERIC_PACKET_DATA_BASE_IDX 2 13035 #define regVPG6_VPG_GSP_FRAME_UPDATE_CTRL 0x3653 13036 #define regVPG6_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX 2 13037 #define regVPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL 0x3654 13038 #define regVPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX 2 13039 #define regVPG6_VPG_GENERIC_STATUS 0x3655 13040 #define regVPG6_VPG_GENERIC_STATUS_BASE_IDX 2 13041 #define regVPG6_VPG_MEM_PWR 0x3656 13042 #define regVPG6_VPG_MEM_PWR_BASE_IDX 2 13043 #define regVPG6_VPG_ISRC1_2_ACCESS_CTRL 0x3657 13044 #define regVPG6_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX 2 13045 #define regVPG6_VPG_ISRC1_2_DATA 0x3658 13046 #define regVPG6_VPG_ISRC1_2_DATA_BASE_IDX 2 13047 #define regVPG6_VPG_MPEG_INFO0 0x3659 13048 #define regVPG6_VPG_MPEG_INFO0_BASE_IDX 2 13049 #define regVPG6_VPG_MPEG_INFO1 0x365a 13050 #define regVPG6_VPG_MPEG_INFO1_BASE_IDX 2 13051 13052 13053 // addressBlock: dce_dc_hpo_dp_sym32_enc0_dispdec 13054 // base address: 0x1ac74 13055 #define regDP_SYM32_ENC0_DP_SYM32_ENC_CONTROL 0x365d 13056 #define regDP_SYM32_ENC0_DP_SYM32_ENC_CONTROL_BASE_IDX 2 13057 #define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_FIFO_CONTROL 0x365e 13058 #define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_FIFO_CONTROL_BASE_IDX 2 13059 #define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL 0x365f 13060 #define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL_BASE_IDX 2 13061 #define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL 0x3660 13062 #define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL_BASE_IDX 2 13063 #define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_PIXEL_FORMAT 0x3661 13064 #define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_PIXEL_FORMAT_BASE_IDX 2 13065 #define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA0 0x3662 13066 #define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA0_BASE_IDX 2 13067 #define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA1 0x3663 13068 #define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA1_BASE_IDX 2 13069 #define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA2 0x3664 13070 #define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA2_BASE_IDX 2 13071 #define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA3 0x3665 13072 #define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA3_BASE_IDX 2 13073 #define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA4 0x3666 13074 #define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA4_BASE_IDX 2 13075 #define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA5 0x3667 13076 #define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA5_BASE_IDX 2 13077 #define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA6 0x3668 13078 #define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA6_BASE_IDX 2 13079 #define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA7 0x3669 13080 #define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA7_BASE_IDX 2 13081 #define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA8 0x366a 13082 #define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA8_BASE_IDX 2 13083 #define regDP_SYM32_ENC0_DP_SYM32_ENC_HBLANK_CONTROL 0x366b 13084 #define regDP_SYM32_ENC0_DP_SYM32_ENC_HBLANK_CONTROL_BASE_IDX 2 13085 #define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0 0x366c 13086 #define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0_BASE_IDX 2 13087 #define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1 0x366d 13088 #define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1_BASE_IDX 2 13089 #define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2 0x366e 13090 #define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2_BASE_IDX 2 13091 #define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3 0x366f 13092 #define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3_BASE_IDX 2 13093 #define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4 0x3670 13094 #define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4_BASE_IDX 2 13095 #define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5 0x3671 13096 #define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5_BASE_IDX 2 13097 #define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6 0x3672 13098 #define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6_BASE_IDX 2 13099 #define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7 0x3673 13100 #define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7_BASE_IDX 2 13101 #define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8 0x3674 13102 #define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8_BASE_IDX 2 13103 #define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9 0x3675 13104 #define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9_BASE_IDX 2 13105 #define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10 0x3676 13106 #define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10_BASE_IDX 2 13107 #define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11 0x3677 13108 #define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11_BASE_IDX 2 13109 #define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12 0x3678 13110 #define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12_BASE_IDX 2 13111 #define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13 0x3679 13112 #define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13_BASE_IDX 2 13113 #define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14 0x367a 13114 #define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14_BASE_IDX 2 13115 #define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_CONTROL 0x367b 13116 #define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_CONTROL_BASE_IDX 2 13117 #define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0 0x367c 13118 #define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0_BASE_IDX 2 13119 #define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL1 0x367d 13120 #define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL1_BASE_IDX 2 13121 #define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL 0x367e 13122 #define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL_BASE_IDX 2 13123 #define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA_CONTROL 0x3683 13124 #define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA_CONTROL_BASE_IDX 2 13125 #define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_VBID_CONTROL 0x3684 13126 #define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_VBID_CONTROL_BASE_IDX 2 13127 #define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_STREAM_CONTROL 0x3685 13128 #define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_STREAM_CONTROL_BASE_IDX 2 13129 #define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL 0x3686 13130 #define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL_BASE_IDX 2 13131 #define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_CONTROL 0x3687 13132 #define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_CONTROL_BASE_IDX 2 13133 #define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_RESULT0 0x3688 13134 #define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_RESULT0_BASE_IDX 2 13135 #define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_RESULT1 0x3689 13136 #define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_RESULT1_BASE_IDX 2 13137 #define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_STATUS 0x368a 13138 #define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_STATUS_BASE_IDX 2 13139 #define regDP_SYM32_ENC0_DP_SYM32_ENC_MEM_POWER_CONTROL 0x368b 13140 #define regDP_SYM32_ENC0_DP_SYM32_ENC_MEM_POWER_CONTROL_BASE_IDX 2 13141 #define regDP_SYM32_ENC0_DP_SYM32_ENC_SPARE 0x368c 13142 #define regDP_SYM32_ENC0_DP_SYM32_ENC_SPARE_BASE_IDX 2 13143 13144 13145 // addressBlock: dce_dc_hpo_dp_stream_enc1_dispdec 13146 // base address: 0x1aedc 13147 #define regDP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_CONTROL 0x36f7 13148 #define regDP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_CONTROL_BASE_IDX 2 13149 #define regDP_STREAM_ENC1_DP_STREAM_ENC_INPUT_MUX_CONTROL 0x36f8 13150 #define regDP_STREAM_ENC1_DP_STREAM_ENC_INPUT_MUX_CONTROL_BASE_IDX 2 13151 #define regDP_STREAM_ENC1_DP_STREAM_ENC_AUDIO_CONTROL 0x36f9 13152 #define regDP_STREAM_ENC1_DP_STREAM_ENC_AUDIO_CONTROL_BASE_IDX 2 13153 #define regDP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0 0x36fa 13154 #define regDP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0_BASE_IDX 2 13155 #define regDP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1 0x36fb 13156 #define regDP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1_BASE_IDX 2 13157 #define regDP_STREAM_ENC1_DP_STREAM_ENC_SPARE 0x36fc 13158 #define regDP_STREAM_ENC1_DP_STREAM_ENC_SPARE_BASE_IDX 2 13159 13160 13161 // addressBlock: dce_dc_hpo_dp_stream_enc1_apg_apg_dispdec 13162 // base address: 0x1af10 13163 #define regAPG1_APG_CONTROL 0x3704 13164 #define regAPG1_APG_CONTROL_BASE_IDX 2 13165 #define regAPG1_APG_CONTROL2 0x3705 13166 #define regAPG1_APG_CONTROL2_BASE_IDX 2 13167 #define regAPG1_APG_DBG_GEN_CONTROL 0x3706 13168 #define regAPG1_APG_DBG_GEN_CONTROL_BASE_IDX 2 13169 #define regAPG1_APG_PACKET_CONTROL 0x3707 13170 #define regAPG1_APG_PACKET_CONTROL_BASE_IDX 2 13171 #define regAPG1_APG_AUDIO_CRC_CONTROL 0x370e 13172 #define regAPG1_APG_AUDIO_CRC_CONTROL_BASE_IDX 2 13173 #define regAPG1_APG_AUDIO_CRC_CONTROL2 0x370f 13174 #define regAPG1_APG_AUDIO_CRC_CONTROL2_BASE_IDX 2 13175 #define regAPG1_APG_AUDIO_CRC_RESULT 0x3710 13176 #define regAPG1_APG_AUDIO_CRC_RESULT_BASE_IDX 2 13177 #define regAPG1_APG_STATUS 0x3715 13178 #define regAPG1_APG_STATUS_BASE_IDX 2 13179 #define regAPG1_APG_STATUS2 0x3716 13180 #define regAPG1_APG_STATUS2_BASE_IDX 2 13181 #define regAPG1_APG_MEM_PWR 0x3718 13182 #define regAPG1_APG_MEM_PWR_BASE_IDX 2 13183 #define regAPG1_APG_SPARE 0x371a 13184 #define regAPG1_APG_SPARE_BASE_IDX 2 13185 13186 13187 // addressBlock: dce_dc_hpo_dp_stream_enc1_dme_dme_dispdec 13188 // base address: 0x1af88 13189 #define regDME7_DME_CONTROL 0x3722 13190 #define regDME7_DME_CONTROL_BASE_IDX 2 13191 #define regDME7_DME_MEMORY_CONTROL 0x3723 13192 #define regDME7_DME_MEMORY_CONTROL_BASE_IDX 2 13193 13194 13195 // addressBlock: dce_dc_hpo_dp_stream_enc1_vpg_vpg_dispdec 13196 // base address: 0x1af94 13197 #define regVPG7_VPG_GENERIC_PACKET_ACCESS_CTRL 0x3725 13198 #define regVPG7_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX 2 13199 #define regVPG7_VPG_GENERIC_PACKET_DATA 0x3726 13200 #define regVPG7_VPG_GENERIC_PACKET_DATA_BASE_IDX 2 13201 #define regVPG7_VPG_GSP_FRAME_UPDATE_CTRL 0x3727 13202 #define regVPG7_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX 2 13203 #define regVPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL 0x3728 13204 #define regVPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX 2 13205 #define regVPG7_VPG_GENERIC_STATUS 0x3729 13206 #define regVPG7_VPG_GENERIC_STATUS_BASE_IDX 2 13207 #define regVPG7_VPG_MEM_PWR 0x372a 13208 #define regVPG7_VPG_MEM_PWR_BASE_IDX 2 13209 #define regVPG7_VPG_ISRC1_2_ACCESS_CTRL 0x372b 13210 #define regVPG7_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX 2 13211 #define regVPG7_VPG_ISRC1_2_DATA 0x372c 13212 #define regVPG7_VPG_ISRC1_2_DATA_BASE_IDX 2 13213 #define regVPG7_VPG_MPEG_INFO0 0x372d 13214 #define regVPG7_VPG_MPEG_INFO0_BASE_IDX 2 13215 #define regVPG7_VPG_MPEG_INFO1 0x372e 13216 #define regVPG7_VPG_MPEG_INFO1_BASE_IDX 2 13217 13218 13219 // addressBlock: dce_dc_hpo_dp_sym32_enc1_dispdec 13220 // base address: 0x1afc4 13221 #define regDP_SYM32_ENC1_DP_SYM32_ENC_CONTROL 0x3731 13222 #define regDP_SYM32_ENC1_DP_SYM32_ENC_CONTROL_BASE_IDX 2 13223 #define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_FIFO_CONTROL 0x3732 13224 #define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_FIFO_CONTROL_BASE_IDX 2 13225 #define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL 0x3733 13226 #define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL_BASE_IDX 2 13227 #define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL 0x3734 13228 #define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL_BASE_IDX 2 13229 #define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_PIXEL_FORMAT 0x3735 13230 #define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_PIXEL_FORMAT_BASE_IDX 2 13231 #define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA0 0x3736 13232 #define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA0_BASE_IDX 2 13233 #define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA1 0x3737 13234 #define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA1_BASE_IDX 2 13235 #define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA2 0x3738 13236 #define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA2_BASE_IDX 2 13237 #define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA3 0x3739 13238 #define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA3_BASE_IDX 2 13239 #define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA4 0x373a 13240 #define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA4_BASE_IDX 2 13241 #define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA5 0x373b 13242 #define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA5_BASE_IDX 2 13243 #define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA6 0x373c 13244 #define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA6_BASE_IDX 2 13245 #define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA7 0x373d 13246 #define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA7_BASE_IDX 2 13247 #define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA8 0x373e 13248 #define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA8_BASE_IDX 2 13249 #define regDP_SYM32_ENC1_DP_SYM32_ENC_HBLANK_CONTROL 0x373f 13250 #define regDP_SYM32_ENC1_DP_SYM32_ENC_HBLANK_CONTROL_BASE_IDX 2 13251 #define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0 0x3740 13252 #define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0_BASE_IDX 2 13253 #define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1 0x3741 13254 #define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1_BASE_IDX 2 13255 #define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2 0x3742 13256 #define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2_BASE_IDX 2 13257 #define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3 0x3743 13258 #define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3_BASE_IDX 2 13259 #define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4 0x3744 13260 #define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4_BASE_IDX 2 13261 #define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5 0x3745 13262 #define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5_BASE_IDX 2 13263 #define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6 0x3746 13264 #define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6_BASE_IDX 2 13265 #define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7 0x3747 13266 #define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7_BASE_IDX 2 13267 #define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8 0x3748 13268 #define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8_BASE_IDX 2 13269 #define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9 0x3749 13270 #define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9_BASE_IDX 2 13271 #define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10 0x374a 13272 #define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10_BASE_IDX 2 13273 #define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11 0x374b 13274 #define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11_BASE_IDX 2 13275 #define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12 0x374c 13276 #define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12_BASE_IDX 2 13277 #define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13 0x374d 13278 #define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13_BASE_IDX 2 13279 #define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14 0x374e 13280 #define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14_BASE_IDX 2 13281 #define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_CONTROL 0x374f 13282 #define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_CONTROL_BASE_IDX 2 13283 #define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL0 0x3750 13284 #define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL0_BASE_IDX 2 13285 #define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL1 0x3751 13286 #define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL1_BASE_IDX 2 13287 #define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL 0x3752 13288 #define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL_BASE_IDX 2 13289 #define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA_CONTROL 0x3757 13290 #define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA_CONTROL_BASE_IDX 2 13291 #define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_VBID_CONTROL 0x3758 13292 #define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_VBID_CONTROL_BASE_IDX 2 13293 #define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_STREAM_CONTROL 0x3759 13294 #define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_STREAM_CONTROL_BASE_IDX 2 13295 #define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL 0x375a 13296 #define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL_BASE_IDX 2 13297 #define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_CONTROL 0x375b 13298 #define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_CONTROL_BASE_IDX 2 13299 #define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_RESULT0 0x375c 13300 #define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_RESULT0_BASE_IDX 2 13301 #define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_RESULT1 0x375d 13302 #define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_RESULT1_BASE_IDX 2 13303 #define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_STATUS 0x375e 13304 #define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_STATUS_BASE_IDX 2 13305 #define regDP_SYM32_ENC1_DP_SYM32_ENC_MEM_POWER_CONTROL 0x375f 13306 #define regDP_SYM32_ENC1_DP_SYM32_ENC_MEM_POWER_CONTROL_BASE_IDX 2 13307 #define regDP_SYM32_ENC1_DP_SYM32_ENC_SPARE 0x3760 13308 #define regDP_SYM32_ENC1_DP_SYM32_ENC_SPARE_BASE_IDX 2 13309 13310 13311 // addressBlock: dce_dc_hpo_dp_stream_enc2_dispdec 13312 // base address: 0x1b22c 13313 #define regDP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_CONTROL 0x37cb 13314 #define regDP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_CONTROL_BASE_IDX 2 13315 #define regDP_STREAM_ENC2_DP_STREAM_ENC_INPUT_MUX_CONTROL 0x37cc 13316 #define regDP_STREAM_ENC2_DP_STREAM_ENC_INPUT_MUX_CONTROL_BASE_IDX 2 13317 #define regDP_STREAM_ENC2_DP_STREAM_ENC_AUDIO_CONTROL 0x37cd 13318 #define regDP_STREAM_ENC2_DP_STREAM_ENC_AUDIO_CONTROL_BASE_IDX 2 13319 #define regDP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0 0x37ce 13320 #define regDP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0_BASE_IDX 2 13321 #define regDP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1 0x37cf 13322 #define regDP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1_BASE_IDX 2 13323 #define regDP_STREAM_ENC2_DP_STREAM_ENC_SPARE 0x37d0 13324 #define regDP_STREAM_ENC2_DP_STREAM_ENC_SPARE_BASE_IDX 2 13325 13326 13327 // addressBlock: dce_dc_hpo_dp_stream_enc2_apg_apg_dispdec 13328 // base address: 0x1b260 13329 #define regAPG2_APG_CONTROL 0x37d8 13330 #define regAPG2_APG_CONTROL_BASE_IDX 2 13331 #define regAPG2_APG_CONTROL2 0x37d9 13332 #define regAPG2_APG_CONTROL2_BASE_IDX 2 13333 #define regAPG2_APG_DBG_GEN_CONTROL 0x37da 13334 #define regAPG2_APG_DBG_GEN_CONTROL_BASE_IDX 2 13335 #define regAPG2_APG_PACKET_CONTROL 0x37db 13336 #define regAPG2_APG_PACKET_CONTROL_BASE_IDX 2 13337 #define regAPG2_APG_AUDIO_CRC_CONTROL 0x37e2 13338 #define regAPG2_APG_AUDIO_CRC_CONTROL_BASE_IDX 2 13339 #define regAPG2_APG_AUDIO_CRC_CONTROL2 0x37e3 13340 #define regAPG2_APG_AUDIO_CRC_CONTROL2_BASE_IDX 2 13341 #define regAPG2_APG_AUDIO_CRC_RESULT 0x37e4 13342 #define regAPG2_APG_AUDIO_CRC_RESULT_BASE_IDX 2 13343 #define regAPG2_APG_STATUS 0x37e9 13344 #define regAPG2_APG_STATUS_BASE_IDX 2 13345 #define regAPG2_APG_STATUS2 0x37ea 13346 #define regAPG2_APG_STATUS2_BASE_IDX 2 13347 #define regAPG2_APG_MEM_PWR 0x37ec 13348 #define regAPG2_APG_MEM_PWR_BASE_IDX 2 13349 #define regAPG2_APG_SPARE 0x37ee 13350 #define regAPG2_APG_SPARE_BASE_IDX 2 13351 13352 13353 // addressBlock: dce_dc_hpo_dp_stream_enc2_dme_dme_dispdec 13354 // base address: 0x1b2d8 13355 #define regDME8_DME_CONTROL 0x37f6 13356 #define regDME8_DME_CONTROL_BASE_IDX 2 13357 #define regDME8_DME_MEMORY_CONTROL 0x37f7 13358 #define regDME8_DME_MEMORY_CONTROL_BASE_IDX 2 13359 13360 13361 // addressBlock: dce_dc_hpo_dp_stream_enc2_vpg_vpg_dispdec 13362 // base address: 0x1b2e4 13363 #define regVPG8_VPG_GENERIC_PACKET_ACCESS_CTRL 0x37f9 13364 #define regVPG8_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX 2 13365 #define regVPG8_VPG_GENERIC_PACKET_DATA 0x37fa 13366 #define regVPG8_VPG_GENERIC_PACKET_DATA_BASE_IDX 2 13367 #define regVPG8_VPG_GSP_FRAME_UPDATE_CTRL 0x37fb 13368 #define regVPG8_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX 2 13369 #define regVPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL 0x37fc 13370 #define regVPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX 2 13371 #define regVPG8_VPG_GENERIC_STATUS 0x37fd 13372 #define regVPG8_VPG_GENERIC_STATUS_BASE_IDX 2 13373 #define regVPG8_VPG_MEM_PWR 0x37fe 13374 #define regVPG8_VPG_MEM_PWR_BASE_IDX 2 13375 #define regVPG8_VPG_ISRC1_2_ACCESS_CTRL 0x37ff 13376 #define regVPG8_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX 2 13377 #define regVPG8_VPG_ISRC1_2_DATA 0x3800 13378 #define regVPG8_VPG_ISRC1_2_DATA_BASE_IDX 2 13379 #define regVPG8_VPG_MPEG_INFO0 0x3801 13380 #define regVPG8_VPG_MPEG_INFO0_BASE_IDX 2 13381 #define regVPG8_VPG_MPEG_INFO1 0x3802 13382 #define regVPG8_VPG_MPEG_INFO1_BASE_IDX 2 13383 13384 13385 // addressBlock: dce_dc_hpo_dp_sym32_enc2_dispdec 13386 // base address: 0x1b314 13387 #define regDP_SYM32_ENC2_DP_SYM32_ENC_CONTROL 0x3805 13388 #define regDP_SYM32_ENC2_DP_SYM32_ENC_CONTROL_BASE_IDX 2 13389 #define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_FIFO_CONTROL 0x3806 13390 #define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_FIFO_CONTROL_BASE_IDX 2 13391 #define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL 0x3807 13392 #define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL_BASE_IDX 2 13393 #define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL 0x3808 13394 #define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL_BASE_IDX 2 13395 #define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_PIXEL_FORMAT 0x3809 13396 #define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_PIXEL_FORMAT_BASE_IDX 2 13397 #define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA0 0x380a 13398 #define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA0_BASE_IDX 2 13399 #define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA1 0x380b 13400 #define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA1_BASE_IDX 2 13401 #define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA2 0x380c 13402 #define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA2_BASE_IDX 2 13403 #define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA3 0x380d 13404 #define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA3_BASE_IDX 2 13405 #define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA4 0x380e 13406 #define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA4_BASE_IDX 2 13407 #define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA5 0x380f 13408 #define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA5_BASE_IDX 2 13409 #define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA6 0x3810 13410 #define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA6_BASE_IDX 2 13411 #define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA7 0x3811 13412 #define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA7_BASE_IDX 2 13413 #define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA8 0x3812 13414 #define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA8_BASE_IDX 2 13415 #define regDP_SYM32_ENC2_DP_SYM32_ENC_HBLANK_CONTROL 0x3813 13416 #define regDP_SYM32_ENC2_DP_SYM32_ENC_HBLANK_CONTROL_BASE_IDX 2 13417 #define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0 0x3814 13418 #define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0_BASE_IDX 2 13419 #define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1 0x3815 13420 #define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1_BASE_IDX 2 13421 #define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2 0x3816 13422 #define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2_BASE_IDX 2 13423 #define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3 0x3817 13424 #define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3_BASE_IDX 2 13425 #define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4 0x3818 13426 #define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4_BASE_IDX 2 13427 #define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5 0x3819 13428 #define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5_BASE_IDX 2 13429 #define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6 0x381a 13430 #define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6_BASE_IDX 2 13431 #define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7 0x381b 13432 #define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7_BASE_IDX 2 13433 #define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8 0x381c 13434 #define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8_BASE_IDX 2 13435 #define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9 0x381d 13436 #define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9_BASE_IDX 2 13437 #define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10 0x381e 13438 #define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10_BASE_IDX 2 13439 #define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11 0x381f 13440 #define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11_BASE_IDX 2 13441 #define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12 0x3820 13442 #define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12_BASE_IDX 2 13443 #define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13 0x3821 13444 #define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13_BASE_IDX 2 13445 #define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14 0x3822 13446 #define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14_BASE_IDX 2 13447 #define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_CONTROL 0x3823 13448 #define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_CONTROL_BASE_IDX 2 13449 #define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL0 0x3824 13450 #define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL0_BASE_IDX 2 13451 #define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL1 0x3825 13452 #define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL1_BASE_IDX 2 13453 #define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL 0x3826 13454 #define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL_BASE_IDX 2 13455 #define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA_CONTROL 0x382b 13456 #define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA_CONTROL_BASE_IDX 2 13457 #define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_VBID_CONTROL 0x382c 13458 #define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_VBID_CONTROL_BASE_IDX 2 13459 #define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_STREAM_CONTROL 0x382d 13460 #define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_STREAM_CONTROL_BASE_IDX 2 13461 #define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL 0x382e 13462 #define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL_BASE_IDX 2 13463 #define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_CONTROL 0x382f 13464 #define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_CONTROL_BASE_IDX 2 13465 #define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_RESULT0 0x3830 13466 #define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_RESULT0_BASE_IDX 2 13467 #define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_RESULT1 0x3831 13468 #define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_RESULT1_BASE_IDX 2 13469 #define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_STATUS 0x3832 13470 #define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_STATUS_BASE_IDX 2 13471 #define regDP_SYM32_ENC2_DP_SYM32_ENC_MEM_POWER_CONTROL 0x3833 13472 #define regDP_SYM32_ENC2_DP_SYM32_ENC_MEM_POWER_CONTROL_BASE_IDX 2 13473 #define regDP_SYM32_ENC2_DP_SYM32_ENC_SPARE 0x3834 13474 #define regDP_SYM32_ENC2_DP_SYM32_ENC_SPARE_BASE_IDX 2 13475 13476 13477 // addressBlock: dce_dc_hpo_dp_stream_enc3_dispdec 13478 // base address: 0x1b57c 13479 #define regDP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_CONTROL 0x389f 13480 #define regDP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_CONTROL_BASE_IDX 2 13481 #define regDP_STREAM_ENC3_DP_STREAM_ENC_INPUT_MUX_CONTROL 0x38a0 13482 #define regDP_STREAM_ENC3_DP_STREAM_ENC_INPUT_MUX_CONTROL_BASE_IDX 2 13483 #define regDP_STREAM_ENC3_DP_STREAM_ENC_AUDIO_CONTROL 0x38a1 13484 #define regDP_STREAM_ENC3_DP_STREAM_ENC_AUDIO_CONTROL_BASE_IDX 2 13485 #define regDP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0 0x38a2 13486 #define regDP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0_BASE_IDX 2 13487 #define regDP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1 0x38a3 13488 #define regDP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1_BASE_IDX 2 13489 #define regDP_STREAM_ENC3_DP_STREAM_ENC_SPARE 0x38a4 13490 #define regDP_STREAM_ENC3_DP_STREAM_ENC_SPARE_BASE_IDX 2 13491 13492 13493 // addressBlock: dce_dc_hpo_dp_stream_enc3_apg_apg_dispdec 13494 // base address: 0x1b5b0 13495 #define regAPG3_APG_CONTROL 0x38ac 13496 #define regAPG3_APG_CONTROL_BASE_IDX 2 13497 #define regAPG3_APG_CONTROL2 0x38ad 13498 #define regAPG3_APG_CONTROL2_BASE_IDX 2 13499 #define regAPG3_APG_DBG_GEN_CONTROL 0x38ae 13500 #define regAPG3_APG_DBG_GEN_CONTROL_BASE_IDX 2 13501 #define regAPG3_APG_PACKET_CONTROL 0x38af 13502 #define regAPG3_APG_PACKET_CONTROL_BASE_IDX 2 13503 #define regAPG3_APG_AUDIO_CRC_CONTROL 0x38b6 13504 #define regAPG3_APG_AUDIO_CRC_CONTROL_BASE_IDX 2 13505 #define regAPG3_APG_AUDIO_CRC_CONTROL2 0x38b7 13506 #define regAPG3_APG_AUDIO_CRC_CONTROL2_BASE_IDX 2 13507 #define regAPG3_APG_AUDIO_CRC_RESULT 0x38b8 13508 #define regAPG3_APG_AUDIO_CRC_RESULT_BASE_IDX 2 13509 #define regAPG3_APG_STATUS 0x38bd 13510 #define regAPG3_APG_STATUS_BASE_IDX 2 13511 #define regAPG3_APG_STATUS2 0x38be 13512 #define regAPG3_APG_STATUS2_BASE_IDX 2 13513 #define regAPG3_APG_MEM_PWR 0x38c0 13514 #define regAPG3_APG_MEM_PWR_BASE_IDX 2 13515 #define regAPG3_APG_SPARE 0x38c2 13516 #define regAPG3_APG_SPARE_BASE_IDX 2 13517 13518 13519 // addressBlock: dce_dc_hpo_dp_stream_enc3_dme_dme_dispdec 13520 // base address: 0x1b628 13521 #define regDME9_DME_CONTROL 0x38ca 13522 #define regDME9_DME_CONTROL_BASE_IDX 2 13523 #define regDME9_DME_MEMORY_CONTROL 0x38cb 13524 #define regDME9_DME_MEMORY_CONTROL_BASE_IDX 2 13525 13526 13527 // addressBlock: dce_dc_hpo_dp_stream_enc3_vpg_vpg_dispdec 13528 // base address: 0x1b634 13529 #define regVPG9_VPG_GENERIC_PACKET_ACCESS_CTRL 0x38cd 13530 #define regVPG9_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX 2 13531 #define regVPG9_VPG_GENERIC_PACKET_DATA 0x38ce 13532 #define regVPG9_VPG_GENERIC_PACKET_DATA_BASE_IDX 2 13533 #define regVPG9_VPG_GSP_FRAME_UPDATE_CTRL 0x38cf 13534 #define regVPG9_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX 2 13535 #define regVPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL 0x38d0 13536 #define regVPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX 2 13537 #define regVPG9_VPG_GENERIC_STATUS 0x38d1 13538 #define regVPG9_VPG_GENERIC_STATUS_BASE_IDX 2 13539 #define regVPG9_VPG_MEM_PWR 0x38d2 13540 #define regVPG9_VPG_MEM_PWR_BASE_IDX 2 13541 #define regVPG9_VPG_ISRC1_2_ACCESS_CTRL 0x38d3 13542 #define regVPG9_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX 2 13543 #define regVPG9_VPG_ISRC1_2_DATA 0x38d4 13544 #define regVPG9_VPG_ISRC1_2_DATA_BASE_IDX 2 13545 #define regVPG9_VPG_MPEG_INFO0 0x38d5 13546 #define regVPG9_VPG_MPEG_INFO0_BASE_IDX 2 13547 #define regVPG9_VPG_MPEG_INFO1 0x38d6 13548 #define regVPG9_VPG_MPEG_INFO1_BASE_IDX 2 13549 13550 13551 // addressBlock: dce_dc_hpo_dp_sym32_enc3_dispdec 13552 // base address: 0x1b664 13553 #define regDP_SYM32_ENC3_DP_SYM32_ENC_CONTROL 0x38d9 13554 #define regDP_SYM32_ENC3_DP_SYM32_ENC_CONTROL_BASE_IDX 2 13555 #define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_FIFO_CONTROL 0x38da 13556 #define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_FIFO_CONTROL_BASE_IDX 2 13557 #define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL 0x38db 13558 #define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL_BASE_IDX 2 13559 #define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL 0x38dc 13560 #define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL_BASE_IDX 2 13561 #define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_PIXEL_FORMAT 0x38dd 13562 #define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_PIXEL_FORMAT_BASE_IDX 2 13563 #define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA0 0x38de 13564 #define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA0_BASE_IDX 2 13565 #define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA1 0x38df 13566 #define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA1_BASE_IDX 2 13567 #define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA2 0x38e0 13568 #define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA2_BASE_IDX 2 13569 #define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA3 0x38e1 13570 #define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA3_BASE_IDX 2 13571 #define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA4 0x38e2 13572 #define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA4_BASE_IDX 2 13573 #define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA5 0x38e3 13574 #define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA5_BASE_IDX 2 13575 #define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA6 0x38e4 13576 #define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA6_BASE_IDX 2 13577 #define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA7 0x38e5 13578 #define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA7_BASE_IDX 2 13579 #define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA8 0x38e6 13580 #define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA8_BASE_IDX 2 13581 #define regDP_SYM32_ENC3_DP_SYM32_ENC_HBLANK_CONTROL 0x38e7 13582 #define regDP_SYM32_ENC3_DP_SYM32_ENC_HBLANK_CONTROL_BASE_IDX 2 13583 #define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0 0x38e8 13584 #define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0_BASE_IDX 2 13585 #define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1 0x38e9 13586 #define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1_BASE_IDX 2 13587 #define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2 0x38ea 13588 #define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2_BASE_IDX 2 13589 #define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3 0x38eb 13590 #define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3_BASE_IDX 2 13591 #define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4 0x38ec 13592 #define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4_BASE_IDX 2 13593 #define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5 0x38ed 13594 #define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5_BASE_IDX 2 13595 #define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6 0x38ee 13596 #define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6_BASE_IDX 2 13597 #define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7 0x38ef 13598 #define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7_BASE_IDX 2 13599 #define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8 0x38f0 13600 #define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8_BASE_IDX 2 13601 #define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9 0x38f1 13602 #define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9_BASE_IDX 2 13603 #define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10 0x38f2 13604 #define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10_BASE_IDX 2 13605 #define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11 0x38f3 13606 #define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11_BASE_IDX 2 13607 #define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12 0x38f4 13608 #define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12_BASE_IDX 2 13609 #define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13 0x38f5 13610 #define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13_BASE_IDX 2 13611 #define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14 0x38f6 13612 #define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14_BASE_IDX 2 13613 #define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_CONTROL 0x38f7 13614 #define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_CONTROL_BASE_IDX 2 13615 #define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL0 0x38f8 13616 #define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL0_BASE_IDX 2 13617 #define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL1 0x38f9 13618 #define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL1_BASE_IDX 2 13619 #define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL 0x38fa 13620 #define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL_BASE_IDX 2 13621 #define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA_CONTROL 0x38ff 13622 #define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA_CONTROL_BASE_IDX 2 13623 #define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_VBID_CONTROL 0x3900 13624 #define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_VBID_CONTROL_BASE_IDX 2 13625 #define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_STREAM_CONTROL 0x3901 13626 #define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_STREAM_CONTROL_BASE_IDX 2 13627 #define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL 0x3902 13628 #define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL_BASE_IDX 2 13629 #define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_CONTROL 0x3903 13630 #define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_CONTROL_BASE_IDX 2 13631 #define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_RESULT0 0x3904 13632 #define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_RESULT0_BASE_IDX 2 13633 #define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_RESULT1 0x3905 13634 #define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_RESULT1_BASE_IDX 2 13635 #define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_STATUS 0x3906 13636 #define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_STATUS_BASE_IDX 2 13637 #define regDP_SYM32_ENC3_DP_SYM32_ENC_MEM_POWER_CONTROL 0x3907 13638 #define regDP_SYM32_ENC3_DP_SYM32_ENC_MEM_POWER_CONTROL_BASE_IDX 2 13639 #define regDP_SYM32_ENC3_DP_SYM32_ENC_SPARE 0x3908 13640 #define regDP_SYM32_ENC3_DP_SYM32_ENC_SPARE_BASE_IDX 2 13641 13642 13643 // addressBlock: dce_dc_hpo_dp_link_enc0_dispdec 13644 // base address: 0x1ad5c 13645 #define regDP_LINK_ENC0_DP_LINK_ENC_CLOCK_CONTROL 0x3697 13646 #define regDP_LINK_ENC0_DP_LINK_ENC_CLOCK_CONTROL_BASE_IDX 2 13647 #define regDP_LINK_ENC0_DP_LINK_ENC_SPARE 0x3698 13648 #define regDP_LINK_ENC0_DP_LINK_ENC_SPARE_BASE_IDX 2 13649 13650 13651 // addressBlock: dce_dc_hpo_dp_dphy_sym320_dispdec 13652 // base address: 0x1ae00 13653 #define regDP_DPHY_SYM320_DP_DPHY_SYM32_CONTROL 0x36c0 13654 #define regDP_DPHY_SYM320_DP_DPHY_SYM32_CONTROL_BASE_IDX 2 13655 #define regDP_DPHY_SYM320_DP_DPHY_SYM32_STATUS 0x36c1 13656 #define regDP_DPHY_SYM320_DP_DPHY_SYM32_STATUS_BASE_IDX 2 13657 #define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_UPDATE 0x36c4 13658 #define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_UPDATE_BASE_IDX 2 13659 #define regDP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL0 0x36c5 13660 #define regDP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL0_BASE_IDX 2 13661 #define regDP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL1 0x36c6 13662 #define regDP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL1_BASE_IDX 2 13663 #define regDP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL2 0x36c7 13664 #define regDP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL2_BASE_IDX 2 13665 #define regDP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL3 0x36c8 13666 #define regDP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL3_BASE_IDX 2 13667 #define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC0 0x36cb 13668 #define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC0_BASE_IDX 2 13669 #define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC1 0x36cc 13670 #define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC1_BASE_IDX 2 13671 #define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC2 0x36cd 13672 #define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC2_BASE_IDX 2 13673 #define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC3 0x36ce 13674 #define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC3_BASE_IDX 2 13675 #define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS0 0x36d1 13676 #define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS0_BASE_IDX 2 13677 #define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS1 0x36d2 13678 #define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS1_BASE_IDX 2 13679 #define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS2 0x36d3 13680 #define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS2_BASE_IDX 2 13681 #define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS3 0x36d4 13682 #define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS3_BASE_IDX 2 13683 #define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG 0x36d7 13684 #define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG_BASE_IDX 2 13685 #define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED0 0x36d8 13686 #define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED0_BASE_IDX 2 13687 #define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED1 0x36d9 13688 #define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED1_BASE_IDX 2 13689 #define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED2 0x36da 13690 #define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED2_BASE_IDX 2 13691 #define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED3 0x36db 13692 #define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED3_BASE_IDX 2 13693 #define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_SQ_PULSE 0x36dc 13694 #define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_SQ_PULSE_BASE_IDX 2 13695 #define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM0 0x36dd 13696 #define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM0_BASE_IDX 2 13697 #define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM1 0x36de 13698 #define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM1_BASE_IDX 2 13699 #define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM2 0x36df 13700 #define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM2_BASE_IDX 2 13701 #define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM3 0x36e0 13702 #define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM3_BASE_IDX 2 13703 #define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM4 0x36e1 13704 #define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM4_BASE_IDX 2 13705 #define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM5 0x36e2 13706 #define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM5_BASE_IDX 2 13707 #define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM6 0x36e3 13708 #define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM6_BASE_IDX 2 13709 #define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM7 0x36e4 13710 #define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM7_BASE_IDX 2 13711 #define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM8 0x36e5 13712 #define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM8_BASE_IDX 2 13713 #define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM9 0x36e6 13714 #define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM9_BASE_IDX 2 13715 #define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM10 0x36e7 13716 #define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM10_BASE_IDX 2 13717 #define regDP_DPHY_SYM320_DP_DPHY_SYM32_ERROR_STATUS 0x36e8 13718 #define regDP_DPHY_SYM320_DP_DPHY_SYM32_ERROR_STATUS_BASE_IDX 2 13719 #define regDP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_OVERRIDE 0x36ea 13720 #define regDP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_OVERRIDE_BASE_IDX 2 13721 #define regDP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG0 0x36eb 13722 #define regDP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG0_BASE_IDX 2 13723 #define regDP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG1 0x36ec 13724 #define regDP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG1_BASE_IDX 2 13725 #define regDP_DPHY_SYM320_DP_DPHY_SYM32_CRC_STATUS 0x36ed 13726 #define regDP_DPHY_SYM320_DP_DPHY_SYM32_CRC_STATUS_BASE_IDX 2 13727 #define regDP_DPHY_SYM320_DP_DPHY_SYM32_CRC_COUNT 0x36ee 13728 #define regDP_DPHY_SYM320_DP_DPHY_SYM32_CRC_COUNT_BASE_IDX 2 13729 13730 13731 // addressBlock: dce_dc_hpo_dp_link_enc1_dispdec 13732 // base address: 0x1b0ac 13733 #define regDP_LINK_ENC1_DP_LINK_ENC_CLOCK_CONTROL 0x376b 13734 #define regDP_LINK_ENC1_DP_LINK_ENC_CLOCK_CONTROL_BASE_IDX 2 13735 #define regDP_LINK_ENC1_DP_LINK_ENC_SPARE 0x376c 13736 #define regDP_LINK_ENC1_DP_LINK_ENC_SPARE_BASE_IDX 2 13737 13738 13739 // addressBlock: dce_dc_hpo_dp_dphy_sym321_dispdec 13740 // base address: 0x1b150 13741 #define regDP_DPHY_SYM321_DP_DPHY_SYM32_CONTROL 0x3794 13742 #define regDP_DPHY_SYM321_DP_DPHY_SYM32_CONTROL_BASE_IDX 2 13743 #define regDP_DPHY_SYM321_DP_DPHY_SYM32_STATUS 0x3795 13744 #define regDP_DPHY_SYM321_DP_DPHY_SYM32_STATUS_BASE_IDX 2 13745 #define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_UPDATE 0x3798 13746 #define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_UPDATE_BASE_IDX 2 13747 #define regDP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL0 0x3799 13748 #define regDP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL0_BASE_IDX 2 13749 #define regDP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL1 0x379a 13750 #define regDP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL1_BASE_IDX 2 13751 #define regDP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL2 0x379b 13752 #define regDP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL2_BASE_IDX 2 13753 #define regDP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL3 0x379c 13754 #define regDP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL3_BASE_IDX 2 13755 #define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC0 0x379f 13756 #define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC0_BASE_IDX 2 13757 #define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC1 0x37a0 13758 #define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC1_BASE_IDX 2 13759 #define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC2 0x37a1 13760 #define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC2_BASE_IDX 2 13761 #define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC3 0x37a2 13762 #define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC3_BASE_IDX 2 13763 #define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS0 0x37a5 13764 #define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS0_BASE_IDX 2 13765 #define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS1 0x37a6 13766 #define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS1_BASE_IDX 2 13767 #define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS2 0x37a7 13768 #define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS2_BASE_IDX 2 13769 #define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS3 0x37a8 13770 #define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS3_BASE_IDX 2 13771 #define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CONFIG 0x37ab 13772 #define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CONFIG_BASE_IDX 2 13773 #define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED0 0x37ac 13774 #define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED0_BASE_IDX 2 13775 #define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED1 0x37ad 13776 #define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED1_BASE_IDX 2 13777 #define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED2 0x37ae 13778 #define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED2_BASE_IDX 2 13779 #define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED3 0x37af 13780 #define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED3_BASE_IDX 2 13781 #define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_SQ_PULSE 0x37b0 13782 #define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_SQ_PULSE_BASE_IDX 2 13783 #define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM0 0x37b1 13784 #define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM0_BASE_IDX 2 13785 #define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM1 0x37b2 13786 #define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM1_BASE_IDX 2 13787 #define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM2 0x37b3 13788 #define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM2_BASE_IDX 2 13789 #define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM3 0x37b4 13790 #define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM3_BASE_IDX 2 13791 #define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM4 0x37b5 13792 #define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM4_BASE_IDX 2 13793 #define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM5 0x37b6 13794 #define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM5_BASE_IDX 2 13795 #define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM6 0x37b7 13796 #define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM6_BASE_IDX 2 13797 #define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM7 0x37b8 13798 #define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM7_BASE_IDX 2 13799 #define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM8 0x37b9 13800 #define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM8_BASE_IDX 2 13801 #define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM9 0x37ba 13802 #define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM9_BASE_IDX 2 13803 #define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM10 0x37bb 13804 #define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM10_BASE_IDX 2 13805 #define regDP_DPHY_SYM321_DP_DPHY_SYM32_ERROR_STATUS 0x37bc 13806 #define regDP_DPHY_SYM321_DP_DPHY_SYM32_ERROR_STATUS_BASE_IDX 2 13807 #define regDP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_OVERRIDE 0x37be 13808 #define regDP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_OVERRIDE_BASE_IDX 2 13809 #define regDP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG0 0x37bf 13810 #define regDP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG0_BASE_IDX 2 13811 #define regDP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG1 0x37c0 13812 #define regDP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG1_BASE_IDX 2 13813 #define regDP_DPHY_SYM321_DP_DPHY_SYM32_CRC_STATUS 0x37c1 13814 #define regDP_DPHY_SYM321_DP_DPHY_SYM32_CRC_STATUS_BASE_IDX 2 13815 #define regDP_DPHY_SYM321_DP_DPHY_SYM32_CRC_COUNT 0x37c2 13816 #define regDP_DPHY_SYM321_DP_DPHY_SYM32_CRC_COUNT_BASE_IDX 2 13817 13818 13819 // addressBlock: dce_dc_dchvm_hvm_dispdec 13820 // base address: 0x0 13821 #define regDCHVM_CTRL0 0x3603 13822 #define regDCHVM_CTRL0_BASE_IDX 2 13823 #define regDCHVM_CTRL1 0x3604 13824 #define regDCHVM_CTRL1_BASE_IDX 2 13825 #define regDCHVM_CLK_CTRL 0x3605 13826 #define regDCHVM_CLK_CTRL_BASE_IDX 2 13827 #define regDCHVM_MEM_CTRL 0x3606 13828 #define regDCHVM_MEM_CTRL_BASE_IDX 2 13829 #define regDCHVM_RIOMMU_CTRL0 0x3607 13830 #define regDCHVM_RIOMMU_CTRL0_BASE_IDX 2 13831 #define regDCHVM_RIOMMU_STAT0 0x3608 13832 #define regDCHVM_RIOMMU_STAT0_BASE_IDX 2 13833 13834 // addressBlock: vga_vgaseqind 13835 // base address: 0x0 13836 #define ixSEQ00 0x0000 13837 #define ixSEQ01 0x0001 13838 #define ixSEQ02 0x0002 13839 #define ixSEQ03 0x0003 13840 #define ixSEQ04 0x0004 13841 13842 13843 // addressBlock: vga_vgacrtind 13844 // base address: 0x0 13845 #define ixCRT00 0x0000 13846 #define ixCRT01 0x0001 13847 #define ixCRT02 0x0002 13848 #define ixCRT03 0x0003 13849 #define ixCRT04 0x0004 13850 #define ixCRT05 0x0005 13851 #define ixCRT06 0x0006 13852 #define ixCRT07 0x0007 13853 #define ixCRT08 0x0008 13854 #define ixCRT09 0x0009 13855 #define ixCRT0A 0x000a 13856 #define ixCRT0B 0x000b 13857 #define ixCRT0C 0x000c 13858 #define ixCRT0D 0x000d 13859 #define ixCRT0E 0x000e 13860 #define ixCRT0F 0x000f 13861 #define ixCRT10 0x0010 13862 #define ixCRT11 0x0011 13863 #define ixCRT12 0x0012 13864 #define ixCRT13 0x0013 13865 #define ixCRT14 0x0014 13866 #define ixCRT15 0x0015 13867 #define ixCRT16 0x0016 13868 #define ixCRT17 0x0017 13869 #define ixCRT18 0x0018 13870 #define ixCRT1E 0x001e 13871 #define ixCRT1F 0x001f 13872 #define ixCRT22 0x0022 13873 13874 13875 // addressBlock: vga_vgagrphind 13876 // base address: 0x0 13877 #define ixGRA00 0x0000 13878 #define ixGRA01 0x0001 13879 #define ixGRA02 0x0002 13880 #define ixGRA03 0x0003 13881 #define ixGRA04 0x0004 13882 #define ixGRA05 0x0005 13883 #define ixGRA06 0x0006 13884 #define ixGRA07 0x0007 13885 #define ixGRA08 0x0008 13886 13887 13888 // addressBlock: vga_vgaattrind 13889 // base address: 0x0 13890 #define ixATTR00 0x0000 13891 #define ixATTR01 0x0001 13892 #define ixATTR02 0x0002 13893 #define ixATTR03 0x0003 13894 #define ixATTR04 0x0004 13895 #define ixATTR05 0x0005 13896 #define ixATTR06 0x0006 13897 #define ixATTR07 0x0007 13898 #define ixATTR08 0x0008 13899 #define ixATTR09 0x0009 13900 #define ixATTR0A 0x000a 13901 #define ixATTR0B 0x000b 13902 #define ixATTR0C 0x000c 13903 #define ixATTR0D 0x000d 13904 #define ixATTR0E 0x000e 13905 #define ixATTR0F 0x000f 13906 #define ixATTR10 0x0010 13907 #define ixATTR11 0x0011 13908 #define ixATTR12 0x0012 13909 #define ixATTR13 0x0013 13910 #define ixATTR14 0x0014 13911 13912 13913 // addressBlock: azendpoint_f2codecind 13914 // base address: 0x0 13915 #define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x2200 13916 #define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x2706 13917 #define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x270d 13918 #define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_2 0x270e 13919 #define ixAZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL 0x2724 13920 #define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3 0x273e 13921 #define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x2770 13922 #define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x2771 13923 #define ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x2f09 13924 #define ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x2f0a 13925 #define ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x2f0b 13926 #define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY 0x3702 13927 #define ixAZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x3707 13928 #define ixAZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x3708 13929 #define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x3709 13930 #define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x371c 13931 #define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2 0x371d 13932 #define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3 0x371e 13933 #define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4 0x371f 13934 #define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION 0x3770 13935 #define ixAZALIA_F2_CODEC_PIN_CONTROL_CHANNEL_ALLOCATION 0x3771 13936 #define ixAZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO 0x3772 13937 #define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR 0x3776 13938 #define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_DATA 0x3776 13939 #define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE 0x3777 13940 #define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE 0x3778 13941 #define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE 0x3779 13942 #define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE 0x377a 13943 #define ixAZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC 0x377b 13944 #define ixAZALIA_F2_CODEC_PIN_CONTROL_HBR 0x377c 13945 #define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_INDEX 0x3780 13946 #define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_DATA 0x3781 13947 #define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE 0x3785 13948 #define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE 0x3786 13949 #define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE 0x3787 13950 #define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE 0x3788 13951 #define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x3789 13952 #define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x378a 13953 #define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x378b 13954 #define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x378c 13955 #define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x378d 13956 #define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x378e 13957 #define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x378f 13958 #define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x3790 13959 #define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x3791 13960 #define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x3792 13961 #define ixAZALIA_F2_CODEC_PIN_ASSOCIATION_INFO 0x3793 13962 #define ixAZALIA_F2_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x3797 13963 #define ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x3798 13964 #define ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB 0x3799 13965 #define ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x379a 13966 #define ixAZALIA_F2_CODEC_PIN_CONTROL_CODING_TYPE 0x379b 13967 #define ixAZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x379c 13968 #define ixAZALIA_F2_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x379d 13969 #define ixAZALIA_F2_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x379e 13970 #define ixAZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x3f09 13971 #define ixAZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES 0x3f0c 13972 #define ixAZALIA_F2_CODEC_PIN_PARAMETER_CONNECTION_LIST_LENGTH 0x3f0e 13973 13974 13975 // addressBlock: azendpoint_descriptorind 13976 // base address: 0x0 13977 #define ixAUDIO_DESCRIPTOR0 0x0001 13978 #define ixAUDIO_DESCRIPTOR1 0x0002 13979 #define ixAUDIO_DESCRIPTOR2 0x0003 13980 #define ixAUDIO_DESCRIPTOR3 0x0004 13981 #define ixAUDIO_DESCRIPTOR4 0x0005 13982 #define ixAUDIO_DESCRIPTOR5 0x0006 13983 #define ixAUDIO_DESCRIPTOR6 0x0007 13984 #define ixAUDIO_DESCRIPTOR7 0x0008 13985 #define ixAUDIO_DESCRIPTOR8 0x0009 13986 #define ixAUDIO_DESCRIPTOR9 0x000a 13987 #define ixAUDIO_DESCRIPTOR10 0x000b 13988 #define ixAUDIO_DESCRIPTOR11 0x000c 13989 #define ixAUDIO_DESCRIPTOR12 0x000d 13990 #define ixAUDIO_DESCRIPTOR13 0x000e 13991 13992 13993 // addressBlock: azendpoint_sinkinfoind 13994 // base address: 0x0 13995 #define ixAZALIA_F2_CODEC_PIN_CONTROL_MANUFACTURER_ID 0x0000 13996 #define ixAZALIA_F2_CODEC_PIN_CONTROL_PRODUCT_ID 0x0001 13997 #define ixAZALIA_F2_CODEC_PIN_CONTROL_SINK_DESCRIPTION_LEN 0x0002 13998 #define ixAZALIA_F2_CODEC_PIN_CONTROL_PORTID0 0x0003 13999 #define ixAZALIA_F2_CODEC_PIN_CONTROL_PORTID1 0x0004 14000 #define ixSINK_DESCRIPTION0 0x0005 14001 #define ixSINK_DESCRIPTION1 0x0006 14002 #define ixSINK_DESCRIPTION2 0x0007 14003 #define ixSINK_DESCRIPTION3 0x0008 14004 #define ixSINK_DESCRIPTION4 0x0009 14005 #define ixSINK_DESCRIPTION5 0x000a 14006 #define ixSINK_DESCRIPTION6 0x000b 14007 #define ixSINK_DESCRIPTION7 0x000c 14008 #define ixSINK_DESCRIPTION8 0x000d 14009 #define ixSINK_DESCRIPTION9 0x000e 14010 #define ixSINK_DESCRIPTION10 0x000f 14011 #define ixSINK_DESCRIPTION11 0x0010 14012 #define ixSINK_DESCRIPTION12 0x0011 14013 #define ixSINK_DESCRIPTION13 0x0012 14014 #define ixSINK_DESCRIPTION14 0x0013 14015 #define ixSINK_DESCRIPTION15 0x0014 14016 #define ixSINK_DESCRIPTION16 0x0015 14017 #define ixSINK_DESCRIPTION17 0x0016 14018 14019 14020 // addressBlock: azf0controller_azinputcrc0resultind 14021 // base address: 0x0 14022 #define ixAZALIA_INPUT_CRC0_CHANNEL0 0x0000 14023 #define ixAZALIA_INPUT_CRC0_CHANNEL1 0x0001 14024 #define ixAZALIA_INPUT_CRC0_CHANNEL2 0x0002 14025 #define ixAZALIA_INPUT_CRC0_CHANNEL3 0x0003 14026 #define ixAZALIA_INPUT_CRC0_CHANNEL4 0x0004 14027 #define ixAZALIA_INPUT_CRC0_CHANNEL5 0x0005 14028 #define ixAZALIA_INPUT_CRC0_CHANNEL6 0x0006 14029 #define ixAZALIA_INPUT_CRC0_CHANNEL7 0x0007 14030 14031 14032 // addressBlock: azf0controller_azinputcrc1resultind 14033 // base address: 0x0 14034 #define ixAZALIA_INPUT_CRC1_CHANNEL0 0x0000 14035 #define ixAZALIA_INPUT_CRC1_CHANNEL1 0x0001 14036 #define ixAZALIA_INPUT_CRC1_CHANNEL2 0x0002 14037 #define ixAZALIA_INPUT_CRC1_CHANNEL3 0x0003 14038 #define ixAZALIA_INPUT_CRC1_CHANNEL4 0x0004 14039 #define ixAZALIA_INPUT_CRC1_CHANNEL5 0x0005 14040 #define ixAZALIA_INPUT_CRC1_CHANNEL6 0x0006 14041 #define ixAZALIA_INPUT_CRC1_CHANNEL7 0x0007 14042 14043 14044 // addressBlock: azf0controller_azcrc0resultind 14045 // base address: 0x0 14046 #define ixAZALIA_CRC0_CHANNEL0 0x0000 14047 #define ixAZALIA_CRC0_CHANNEL1 0x0001 14048 #define ixAZALIA_CRC0_CHANNEL2 0x0002 14049 #define ixAZALIA_CRC0_CHANNEL3 0x0003 14050 #define ixAZALIA_CRC0_CHANNEL4 0x0004 14051 #define ixAZALIA_CRC0_CHANNEL5 0x0005 14052 #define ixAZALIA_CRC0_CHANNEL6 0x0006 14053 #define ixAZALIA_CRC0_CHANNEL7 0x0007 14054 14055 14056 // addressBlock: azf0controller_azcrc1resultind 14057 // base address: 0x0 14058 #define ixAZALIA_CRC1_CHANNEL0 0x0000 14059 #define ixAZALIA_CRC1_CHANNEL1 0x0001 14060 #define ixAZALIA_CRC1_CHANNEL2 0x0002 14061 #define ixAZALIA_CRC1_CHANNEL3 0x0003 14062 #define ixAZALIA_CRC1_CHANNEL4 0x0004 14063 #define ixAZALIA_CRC1_CHANNEL5 0x0005 14064 #define ixAZALIA_CRC1_CHANNEL6 0x0006 14065 #define ixAZALIA_CRC1_CHANNEL7 0x0007 14066 14067 14068 // addressBlock: azinputendpoint_f2codecind 14069 // base address: 0x0 14070 #define ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x6200 14071 #define ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x6706 14072 #define ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x670d 14073 #define ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x6f09 14074 #define ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x6f0a 14075 #define ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x6f0b 14076 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x7707 14077 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x7708 14078 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_PIN_SENSE 0x7709 14079 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x771c 14080 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2 0x771d 14081 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3 0x771e 14082 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4 0x771f 14083 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x7771 14084 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE 0x7777 14085 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE 0x7778 14086 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE 0x7779 14087 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE 0x777a 14088 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_HBR 0x777c 14089 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE 0x7785 14090 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE 0x7786 14091 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE 0x7787 14092 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE 0x7788 14093 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x7798 14094 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB 0x7799 14095 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x779a 14096 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x779b 14097 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x779c 14098 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_L 0x779d 14099 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_H 0x779e 14100 #define ixAZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x7f09 14101 #define ixAZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x7f0c 14102 14103 14104 // addressBlock: azroot_f2codecind 14105 // base address: 0x0 14106 #define ixAZALIA_F2_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID 0x0f00 14107 #define ixAZALIA_F2_CODEC_ROOT_PARAMETER_REVISION_ID 0x0f02 14108 #define ixAZALIA_F2_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT 0x0f04 14109 #define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE 0x1705 14110 #define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID 0x1720 14111 #define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_2 0x1721 14112 #define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_3 0x1722 14113 #define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_4 0x1723 14114 #define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION 0x1770 14115 #define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESET 0x17ff 14116 #define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT 0x1f04 14117 #define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_GROUP_TYPE 0x1f05 14118 #define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES 0x1f0a 14119 #define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS 0x1f0b 14120 #define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES 0x1f0f 14121 14122 14123 // addressBlock: azf0stream0_streamind 14124 // base address: 0x0 14125 #define ixAZF0STREAM0_AZALIA_FIFO_SIZE_CONTROL 0x0000 14126 #define ixAZF0STREAM0_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 14127 #define ixAZF0STREAM0_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 14128 #define ixAZF0STREAM0_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 14129 #define ixAZF0STREAM0_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 14130 14131 14132 // addressBlock: azf0stream1_streamind 14133 // base address: 0x0 14134 #define ixAZF0STREAM1_AZALIA_FIFO_SIZE_CONTROL 0x0000 14135 #define ixAZF0STREAM1_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 14136 #define ixAZF0STREAM1_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 14137 #define ixAZF0STREAM1_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 14138 #define ixAZF0STREAM1_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 14139 14140 14141 // addressBlock: azf0stream2_streamind 14142 // base address: 0x0 14143 #define ixAZF0STREAM2_AZALIA_FIFO_SIZE_CONTROL 0x0000 14144 #define ixAZF0STREAM2_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 14145 #define ixAZF0STREAM2_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 14146 #define ixAZF0STREAM2_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 14147 #define ixAZF0STREAM2_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 14148 14149 14150 // addressBlock: azf0stream3_streamind 14151 // base address: 0x0 14152 #define ixAZF0STREAM3_AZALIA_FIFO_SIZE_CONTROL 0x0000 14153 #define ixAZF0STREAM3_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 14154 #define ixAZF0STREAM3_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 14155 #define ixAZF0STREAM3_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 14156 #define ixAZF0STREAM3_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 14157 14158 14159 // addressBlock: azf0stream4_streamind 14160 // base address: 0x0 14161 #define ixAZF0STREAM4_AZALIA_FIFO_SIZE_CONTROL 0x0000 14162 #define ixAZF0STREAM4_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 14163 #define ixAZF0STREAM4_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 14164 #define ixAZF0STREAM4_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 14165 #define ixAZF0STREAM4_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 14166 14167 14168 // addressBlock: azf0stream5_streamind 14169 // base address: 0x0 14170 #define ixAZF0STREAM5_AZALIA_FIFO_SIZE_CONTROL 0x0000 14171 #define ixAZF0STREAM5_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 14172 #define ixAZF0STREAM5_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 14173 #define ixAZF0STREAM5_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 14174 #define ixAZF0STREAM5_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 14175 14176 14177 // addressBlock: azf0stream6_streamind 14178 // base address: 0x0 14179 #define ixAZF0STREAM6_AZALIA_FIFO_SIZE_CONTROL 0x0000 14180 #define ixAZF0STREAM6_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 14181 #define ixAZF0STREAM6_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 14182 #define ixAZF0STREAM6_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 14183 #define ixAZF0STREAM6_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 14184 14185 14186 // addressBlock: azf0stream7_streamind 14187 // base address: 0x0 14188 #define ixAZF0STREAM7_AZALIA_FIFO_SIZE_CONTROL 0x0000 14189 #define ixAZF0STREAM7_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 14190 #define ixAZF0STREAM7_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 14191 #define ixAZF0STREAM7_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 14192 #define ixAZF0STREAM7_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 14193 14194 14195 // addressBlock: azf0stream8_streamind 14196 // base address: 0x0 14197 #define ixAZF0STREAM8_AZALIA_FIFO_SIZE_CONTROL 0x0000 14198 #define ixAZF0STREAM8_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 14199 #define ixAZF0STREAM8_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 14200 #define ixAZF0STREAM8_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 14201 #define ixAZF0STREAM8_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 14202 14203 14204 // addressBlock: azf0stream9_streamind 14205 // base address: 0x0 14206 #define ixAZF0STREAM9_AZALIA_FIFO_SIZE_CONTROL 0x0000 14207 #define ixAZF0STREAM9_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 14208 #define ixAZF0STREAM9_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 14209 #define ixAZF0STREAM9_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 14210 #define ixAZF0STREAM9_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 14211 14212 14213 // addressBlock: azf0stream10_streamind 14214 // base address: 0x0 14215 #define ixAZF0STREAM10_AZALIA_FIFO_SIZE_CONTROL 0x0000 14216 #define ixAZF0STREAM10_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 14217 #define ixAZF0STREAM10_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 14218 #define ixAZF0STREAM10_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 14219 #define ixAZF0STREAM10_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 14220 14221 14222 // addressBlock: azf0stream11_streamind 14223 // base address: 0x0 14224 #define ixAZF0STREAM11_AZALIA_FIFO_SIZE_CONTROL 0x0000 14225 #define ixAZF0STREAM11_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 14226 #define ixAZF0STREAM11_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 14227 #define ixAZF0STREAM11_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 14228 #define ixAZF0STREAM11_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 14229 14230 14231 // addressBlock: azf0stream12_streamind 14232 // base address: 0x0 14233 #define ixAZF0STREAM12_AZALIA_FIFO_SIZE_CONTROL 0x0000 14234 #define ixAZF0STREAM12_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 14235 #define ixAZF0STREAM12_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 14236 #define ixAZF0STREAM12_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 14237 #define ixAZF0STREAM12_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 14238 14239 14240 // addressBlock: azf0stream13_streamind 14241 // base address: 0x0 14242 #define ixAZF0STREAM13_AZALIA_FIFO_SIZE_CONTROL 0x0000 14243 #define ixAZF0STREAM13_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 14244 #define ixAZF0STREAM13_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 14245 #define ixAZF0STREAM13_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 14246 #define ixAZF0STREAM13_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 14247 14248 14249 // addressBlock: azf0stream14_streamind 14250 // base address: 0x0 14251 #define ixAZF0STREAM14_AZALIA_FIFO_SIZE_CONTROL 0x0000 14252 #define ixAZF0STREAM14_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 14253 #define ixAZF0STREAM14_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 14254 #define ixAZF0STREAM14_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 14255 #define ixAZF0STREAM14_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 14256 14257 14258 // addressBlock: azf0stream15_streamind 14259 // base address: 0x0 14260 #define ixAZF0STREAM15_AZALIA_FIFO_SIZE_CONTROL 0x0000 14261 #define ixAZF0STREAM15_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 14262 #define ixAZF0STREAM15_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 14263 #define ixAZF0STREAM15_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 14264 #define ixAZF0STREAM15_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 14265 14266 14267 // addressBlock: azf0endpoint0_endpointind 14268 // base address: 0x0 14269 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 14270 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 14271 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 14272 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 14273 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 14274 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 14275 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007 14276 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008 14277 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x0009 14278 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0x000c 14279 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0x000d 14280 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0x000e 14281 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 14282 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021 14283 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 14284 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023 14285 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024 14286 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025 14287 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028 14288 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029 14289 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a 14290 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b 14291 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c 14292 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d 14293 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e 14294 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f 14295 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030 14296 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031 14297 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032 14298 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033 14299 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034 14300 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035 14301 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 14302 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037 14303 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038 14304 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a 14305 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b 14306 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c 14307 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d 14308 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e 14309 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f 14310 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040 14311 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041 14312 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042 14313 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 14314 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 14315 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 14316 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057 14317 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058 14318 #define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059 14319 #define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a 14320 #define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b 14321 #define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c 14322 #define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d 14323 #define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e 14324 #define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f 14325 #define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060 14326 #define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061 14327 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062 14328 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063 14329 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 14330 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065 14331 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 14332 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067 14333 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068 14334 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069 14335 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a 14336 #define ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b 14337 #define ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c 14338 #define ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d 14339 #define ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e 14340 14341 14342 // addressBlock: azf0endpoint1_endpointind 14343 // base address: 0x0 14344 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 14345 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 14346 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 14347 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 14348 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 14349 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 14350 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007 14351 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008 14352 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x0009 14353 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0x000c 14354 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0x000d 14355 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0x000e 14356 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 14357 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021 14358 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 14359 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023 14360 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024 14361 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025 14362 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028 14363 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029 14364 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a 14365 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b 14366 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c 14367 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d 14368 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e 14369 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f 14370 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030 14371 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031 14372 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032 14373 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033 14374 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034 14375 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035 14376 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 14377 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037 14378 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038 14379 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a 14380 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b 14381 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c 14382 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d 14383 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e 14384 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f 14385 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040 14386 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041 14387 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042 14388 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 14389 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 14390 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 14391 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057 14392 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058 14393 #define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059 14394 #define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a 14395 #define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b 14396 #define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c 14397 #define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d 14398 #define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e 14399 #define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f 14400 #define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060 14401 #define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061 14402 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062 14403 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063 14404 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 14405 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065 14406 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 14407 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067 14408 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068 14409 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069 14410 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a 14411 #define ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b 14412 #define ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c 14413 #define ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d 14414 #define ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e 14415 14416 14417 // addressBlock: azf0endpoint2_endpointind 14418 // base address: 0x0 14419 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 14420 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 14421 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 14422 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 14423 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 14424 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 14425 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007 14426 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008 14427 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x0009 14428 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0x000c 14429 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0x000d 14430 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0x000e 14431 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 14432 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021 14433 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 14434 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023 14435 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024 14436 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025 14437 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028 14438 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029 14439 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a 14440 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b 14441 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c 14442 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d 14443 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e 14444 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f 14445 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030 14446 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031 14447 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032 14448 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033 14449 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034 14450 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035 14451 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 14452 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037 14453 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038 14454 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a 14455 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b 14456 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c 14457 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d 14458 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e 14459 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f 14460 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040 14461 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041 14462 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042 14463 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 14464 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 14465 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 14466 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057 14467 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058 14468 #define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059 14469 #define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a 14470 #define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b 14471 #define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c 14472 #define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d 14473 #define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e 14474 #define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f 14475 #define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060 14476 #define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061 14477 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062 14478 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063 14479 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 14480 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065 14481 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 14482 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067 14483 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068 14484 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069 14485 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a 14486 #define ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b 14487 #define ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c 14488 #define ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d 14489 #define ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e 14490 14491 14492 // addressBlock: azf0endpoint3_endpointind 14493 // base address: 0x0 14494 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 14495 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 14496 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 14497 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 14498 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 14499 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 14500 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007 14501 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008 14502 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x0009 14503 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0x000c 14504 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0x000d 14505 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0x000e 14506 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 14507 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021 14508 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 14509 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023 14510 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024 14511 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025 14512 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028 14513 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029 14514 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a 14515 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b 14516 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c 14517 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d 14518 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e 14519 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f 14520 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030 14521 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031 14522 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032 14523 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033 14524 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034 14525 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035 14526 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 14527 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037 14528 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038 14529 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a 14530 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b 14531 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c 14532 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d 14533 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e 14534 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f 14535 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040 14536 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041 14537 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042 14538 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 14539 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 14540 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 14541 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057 14542 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058 14543 #define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059 14544 #define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a 14545 #define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b 14546 #define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c 14547 #define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d 14548 #define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e 14549 #define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f 14550 #define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060 14551 #define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061 14552 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062 14553 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063 14554 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 14555 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065 14556 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 14557 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067 14558 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068 14559 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069 14560 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a 14561 #define ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b 14562 #define ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c 14563 #define ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d 14564 #define ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e 14565 14566 14567 // addressBlock: azf0endpoint4_endpointind 14568 // base address: 0x0 14569 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 14570 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 14571 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 14572 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 14573 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 14574 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 14575 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007 14576 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008 14577 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x0009 14578 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0x000c 14579 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0x000d 14580 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0x000e 14581 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 14582 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021 14583 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 14584 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023 14585 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024 14586 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025 14587 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028 14588 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029 14589 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a 14590 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b 14591 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c 14592 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d 14593 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e 14594 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f 14595 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030 14596 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031 14597 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032 14598 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033 14599 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034 14600 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035 14601 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 14602 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037 14603 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038 14604 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a 14605 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b 14606 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c 14607 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d 14608 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e 14609 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f 14610 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040 14611 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041 14612 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042 14613 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 14614 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 14615 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 14616 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057 14617 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058 14618 #define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059 14619 #define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a 14620 #define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b 14621 #define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c 14622 #define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d 14623 #define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e 14624 #define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f 14625 #define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060 14626 #define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061 14627 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062 14628 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063 14629 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 14630 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065 14631 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 14632 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067 14633 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068 14634 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069 14635 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a 14636 #define ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b 14637 #define ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c 14638 #define ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d 14639 #define ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e 14640 14641 14642 // addressBlock: azf0endpoint5_endpointind 14643 // base address: 0x0 14644 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 14645 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 14646 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 14647 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 14648 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 14649 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 14650 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007 14651 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008 14652 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x0009 14653 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0x000c 14654 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0x000d 14655 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0x000e 14656 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 14657 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021 14658 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 14659 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023 14660 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024 14661 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025 14662 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028 14663 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029 14664 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a 14665 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b 14666 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c 14667 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d 14668 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e 14669 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f 14670 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030 14671 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031 14672 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032 14673 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033 14674 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034 14675 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035 14676 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 14677 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037 14678 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038 14679 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a 14680 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b 14681 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c 14682 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d 14683 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e 14684 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f 14685 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040 14686 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041 14687 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042 14688 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 14689 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 14690 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 14691 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057 14692 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058 14693 #define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059 14694 #define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a 14695 #define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b 14696 #define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c 14697 #define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d 14698 #define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e 14699 #define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f 14700 #define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060 14701 #define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061 14702 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062 14703 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063 14704 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 14705 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065 14706 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 14707 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067 14708 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068 14709 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069 14710 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a 14711 #define ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b 14712 #define ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c 14713 #define ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d 14714 #define ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e 14715 14716 14717 // addressBlock: azf0endpoint6_endpointind 14718 // base address: 0x0 14719 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 14720 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 14721 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 14722 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 14723 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 14724 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 14725 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007 14726 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008 14727 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x0009 14728 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0x000c 14729 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0x000d 14730 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0x000e 14731 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 14732 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021 14733 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 14734 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023 14735 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024 14736 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025 14737 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028 14738 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029 14739 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a 14740 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b 14741 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c 14742 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d 14743 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e 14744 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f 14745 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030 14746 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031 14747 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032 14748 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033 14749 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034 14750 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035 14751 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 14752 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037 14753 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038 14754 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a 14755 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b 14756 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c 14757 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d 14758 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e 14759 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f 14760 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040 14761 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041 14762 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042 14763 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 14764 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 14765 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 14766 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057 14767 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058 14768 #define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059 14769 #define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a 14770 #define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b 14771 #define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c 14772 #define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d 14773 #define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e 14774 #define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f 14775 #define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060 14776 #define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061 14777 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062 14778 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063 14779 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 14780 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065 14781 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 14782 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067 14783 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068 14784 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069 14785 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a 14786 #define ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b 14787 #define ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c 14788 #define ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d 14789 #define ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e 14790 14791 14792 // addressBlock: azf0endpoint7_endpointind 14793 // base address: 0x0 14794 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 14795 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 14796 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 14797 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 14798 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 14799 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 14800 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007 14801 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008 14802 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x0009 14803 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0x000c 14804 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0x000d 14805 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0x000e 14806 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 14807 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021 14808 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 14809 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023 14810 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024 14811 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025 14812 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028 14813 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029 14814 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a 14815 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b 14816 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c 14817 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d 14818 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e 14819 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f 14820 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030 14821 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031 14822 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032 14823 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033 14824 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034 14825 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035 14826 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 14827 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037 14828 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038 14829 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a 14830 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b 14831 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c 14832 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d 14833 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e 14834 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f 14835 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040 14836 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041 14837 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042 14838 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 14839 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 14840 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 14841 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057 14842 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058 14843 #define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059 14844 #define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a 14845 #define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b 14846 #define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c 14847 #define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d 14848 #define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e 14849 #define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f 14850 #define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060 14851 #define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061 14852 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062 14853 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063 14854 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 14855 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065 14856 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 14857 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067 14858 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068 14859 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069 14860 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a 14861 #define ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b 14862 #define ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c 14863 #define ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d 14864 #define ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e 14865 14866 14867 // addressBlock: azf0inputendpoint0_inputendpointind 14868 // base address: 0x0 14869 #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 14870 #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 14871 #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 14872 #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 14873 #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 14874 #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 14875 #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 14876 #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021 14877 #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 14878 #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023 14879 #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024 14880 #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 14881 #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037 14882 #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038 14883 #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053 14884 #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 14885 #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 14886 #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 14887 #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 14888 #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065 14889 #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 14890 #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067 14891 #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068 14892 14893 14894 // addressBlock: azf0inputendpoint1_inputendpointind 14895 // base address: 0x0 14896 #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 14897 #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 14898 #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 14899 #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 14900 #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 14901 #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 14902 #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 14903 #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021 14904 #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 14905 #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023 14906 #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024 14907 #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 14908 #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037 14909 #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038 14910 #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053 14911 #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 14912 #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 14913 #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 14914 #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 14915 #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065 14916 #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 14917 #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067 14918 #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068 14919 14920 14921 // addressBlock: azf0inputendpoint2_inputendpointind 14922 // base address: 0x0 14923 #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 14924 #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 14925 #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 14926 #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 14927 #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 14928 #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 14929 #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 14930 #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021 14931 #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 14932 #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023 14933 #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024 14934 #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 14935 #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037 14936 #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038 14937 #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053 14938 #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 14939 #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 14940 #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 14941 #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 14942 #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065 14943 #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 14944 #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067 14945 #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068 14946 14947 14948 // addressBlock: azf0inputendpoint3_inputendpointind 14949 // base address: 0x0 14950 #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 14951 #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 14952 #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 14953 #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 14954 #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 14955 #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 14956 #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 14957 #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021 14958 #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 14959 #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023 14960 #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024 14961 #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 14962 #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037 14963 #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038 14964 #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053 14965 #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 14966 #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 14967 #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 14968 #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 14969 #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065 14970 #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 14971 #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067 14972 #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068 14973 14974 14975 // addressBlock: azf0inputendpoint4_inputendpointind 14976 // base address: 0x0 14977 #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 14978 #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 14979 #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 14980 #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 14981 #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 14982 #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 14983 #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 14984 #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021 14985 #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 14986 #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023 14987 #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024 14988 #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 14989 #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037 14990 #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038 14991 #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053 14992 #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 14993 #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 14994 #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 14995 #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 14996 #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065 14997 #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 14998 #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067 14999 #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068 15000 15001 15002 // addressBlock: azf0inputendpoint5_inputendpointind 15003 // base address: 0x0 15004 #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 15005 #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 15006 #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 15007 #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 15008 #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 15009 #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 15010 #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 15011 #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021 15012 #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 15013 #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023 15014 #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024 15015 #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 15016 #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037 15017 #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038 15018 #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053 15019 #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 15020 #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 15021 #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 15022 #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 15023 #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065 15024 #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 15025 #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067 15026 #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068 15027 15028 15029 // addressBlock: azf0inputendpoint6_inputendpointind 15030 // base address: 0x0 15031 #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 15032 #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 15033 #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 15034 #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 15035 #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 15036 #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 15037 #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 15038 #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021 15039 #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 15040 #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023 15041 #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024 15042 #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 15043 #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037 15044 #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038 15045 #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053 15046 #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 15047 #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 15048 #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 15049 #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 15050 #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065 15051 #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 15052 #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067 15053 #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068 15054 15055 15056 // addressBlock: azf0inputendpoint7_inputendpointind 15057 // base address: 0x0 15058 #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 15059 #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 15060 #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 15061 #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 15062 #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 15063 #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 15064 #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 15065 #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021 15066 #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 15067 #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023 15068 #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024 15069 #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 15070 #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037 15071 #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038 15072 #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053 15073 #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 15074 #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 15075 #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 15076 #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 15077 #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065 15078 #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 15079 #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067 15080 #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068 15081 15082 15083 #endif 15084