1 /*
2  * Copyright (C) 2020  Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included
12  * in all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
15  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
18  * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
19  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
20  */
21 #ifndef _dcn_3_0_2_OFFSET_HEADER
22 #define _dcn_3_0_2_OFFSET_HEADER
23 
24 
25 
26 // addressBlock: dce_dc_mmhubbub_vga_dispdec
27 // base address: 0x0
28 #define mmVGA_MEM_WRITE_PAGE_ADDR                                                                      0x0000
29 #define mmVGA_MEM_WRITE_PAGE_ADDR_BASE_IDX                                                             0
30 #define mmVGA_MEM_READ_PAGE_ADDR                                                                       0x0001
31 #define mmVGA_MEM_READ_PAGE_ADDR_BASE_IDX                                                              0
32 #define mmVGA_RENDER_CONTROL                                                                           0x0000
33 #define mmVGA_RENDER_CONTROL_BASE_IDX                                                                  1
34 #define mmVGA_SEQUENCER_RESET_CONTROL                                                                  0x0001
35 #define mmVGA_SEQUENCER_RESET_CONTROL_BASE_IDX                                                         1
36 #define mmVGA_MODE_CONTROL                                                                             0x0002
37 #define mmVGA_MODE_CONTROL_BASE_IDX                                                                    1
38 #define mmVGA_SURFACE_PITCH_SELECT                                                                     0x0003
39 #define mmVGA_SURFACE_PITCH_SELECT_BASE_IDX                                                            1
40 #define mmVGA_MEMORY_BASE_ADDRESS                                                                      0x0004
41 #define mmVGA_MEMORY_BASE_ADDRESS_BASE_IDX                                                             1
42 #define mmVGA_DISPBUF1_SURFACE_ADDR                                                                    0x0006
43 #define mmVGA_DISPBUF1_SURFACE_ADDR_BASE_IDX                                                           1
44 #define mmVGA_DISPBUF2_SURFACE_ADDR                                                                    0x0008
45 #define mmVGA_DISPBUF2_SURFACE_ADDR_BASE_IDX                                                           1
46 #define mmVGA_MEMORY_BASE_ADDRESS_HIGH                                                                 0x0009
47 #define mmVGA_MEMORY_BASE_ADDRESS_HIGH_BASE_IDX                                                        1
48 #define mmVGA_HDP_CONTROL                                                                              0x000a
49 #define mmVGA_HDP_CONTROL_BASE_IDX                                                                     1
50 #define mmVGA_CACHE_CONTROL                                                                            0x000b
51 #define mmVGA_CACHE_CONTROL_BASE_IDX                                                                   1
52 #define mmD1VGA_CONTROL                                                                                0x000c
53 #define mmD1VGA_CONTROL_BASE_IDX                                                                       1
54 #define mmD2VGA_CONTROL                                                                                0x000e
55 #define mmD2VGA_CONTROL_BASE_IDX                                                                       1
56 #define mmVGA_STATUS                                                                                   0x0010
57 #define mmVGA_STATUS_BASE_IDX                                                                          1
58 #define mmVGA_INTERRUPT_CONTROL                                                                        0x0011
59 #define mmVGA_INTERRUPT_CONTROL_BASE_IDX                                                               1
60 #define mmVGA_STATUS_CLEAR                                                                             0x0012
61 #define mmVGA_STATUS_CLEAR_BASE_IDX                                                                    1
62 #define mmVGA_INTERRUPT_STATUS                                                                         0x0013
63 #define mmVGA_INTERRUPT_STATUS_BASE_IDX                                                                1
64 #define mmVGA_MAIN_CONTROL                                                                             0x0014
65 #define mmVGA_MAIN_CONTROL_BASE_IDX                                                                    1
66 #define mmVGA_TEST_CONTROL                                                                             0x0015
67 #define mmVGA_TEST_CONTROL_BASE_IDX                                                                    1
68 #define mmVGA_QOS_CTRL                                                                                 0x0018
69 #define mmVGA_QOS_CTRL_BASE_IDX                                                                        1
70 #define mmCRTC8_IDX                                                                                    0x002d
71 #define mmCRTC8_IDX_BASE_IDX                                                                           1
72 #define mmCRTC8_DATA                                                                                   0x002d
73 #define mmCRTC8_DATA_BASE_IDX                                                                          1
74 #define mmGENFC_WT                                                                                     0x002e
75 #define mmGENFC_WT_BASE_IDX                                                                            1
76 #define mmGENS1                                                                                        0x002e
77 #define mmGENS1_BASE_IDX                                                                               1
78 #define mmATTRDW                                                                                       0x0030
79 #define mmATTRDW_BASE_IDX                                                                              1
80 #define mmATTRX                                                                                        0x0030
81 #define mmATTRX_BASE_IDX                                                                               1
82 #define mmATTRDR                                                                                       0x0030
83 #define mmATTRDR_BASE_IDX                                                                              1
84 #define mmGENMO_WT                                                                                     0x0030
85 #define mmGENMO_WT_BASE_IDX                                                                            1
86 #define mmGENS0                                                                                        0x0030
87 #define mmGENS0_BASE_IDX                                                                               1
88 #define mmGENENB                                                                                       0x0030
89 #define mmGENENB_BASE_IDX                                                                              1
90 #define mmSEQ8_IDX                                                                                     0x0031
91 #define mmSEQ8_IDX_BASE_IDX                                                                            1
92 #define mmSEQ8_DATA                                                                                    0x0031
93 #define mmSEQ8_DATA_BASE_IDX                                                                           1
94 #define mmDAC_MASK                                                                                     0x0031
95 #define mmDAC_MASK_BASE_IDX                                                                            1
96 #define mmDAC_R_INDEX                                                                                  0x0031
97 #define mmDAC_R_INDEX_BASE_IDX                                                                         1
98 #define mmDAC_W_INDEX                                                                                  0x0032
99 #define mmDAC_W_INDEX_BASE_IDX                                                                         1
100 #define mmDAC_DATA                                                                                     0x0032
101 #define mmDAC_DATA_BASE_IDX                                                                            1
102 #define mmGENFC_RD                                                                                     0x0032
103 #define mmGENFC_RD_BASE_IDX                                                                            1
104 #define mmGENMO_RD                                                                                     0x0033
105 #define mmGENMO_RD_BASE_IDX                                                                            1
106 #define mmGRPH8_IDX                                                                                    0x0033
107 #define mmGRPH8_IDX_BASE_IDX                                                                           1
108 #define mmGRPH8_DATA                                                                                   0x0033
109 #define mmGRPH8_DATA_BASE_IDX                                                                          1
110 #define mmCRTC8_IDX_1                                                                                  0x0035
111 #define mmCRTC8_IDX_1_BASE_IDX                                                                         1
112 #define mmCRTC8_DATA_1                                                                                 0x0035
113 #define mmCRTC8_DATA_1_BASE_IDX                                                                        1
114 #define mmGENFC_WT_1                                                                                   0x0036
115 #define mmGENFC_WT_1_BASE_IDX                                                                          1
116 #define mmGENS1_1                                                                                      0x0036
117 #define mmGENS1_1_BASE_IDX                                                                             1
118 #define mmD3VGA_CONTROL                                                                                0x0038
119 #define mmD3VGA_CONTROL_BASE_IDX                                                                       1
120 #define mmD4VGA_CONTROL                                                                                0x0039
121 #define mmD4VGA_CONTROL_BASE_IDX                                                                       1
122 #define mmD5VGA_CONTROL                                                                                0x003a
123 #define mmD5VGA_CONTROL_BASE_IDX                                                                       1
124 #define mmD6VGA_CONTROL                                                                                0x003b
125 #define mmD6VGA_CONTROL_BASE_IDX                                                                       1
126 #define mmVGA_SOURCE_SELECT                                                                            0x003c
127 #define mmVGA_SOURCE_SELECT_BASE_IDX                                                                   1
128 
129 
130 // addressBlock: dce_dc_dccg_dccg_dispdec
131 // base address: 0x0
132 #define mmPHYPLLA_PIXCLK_RESYNC_CNTL                                                                   0x0040
133 #define mmPHYPLLA_PIXCLK_RESYNC_CNTL_BASE_IDX                                                          1
134 #define mmPHYPLLB_PIXCLK_RESYNC_CNTL                                                                   0x0041
135 #define mmPHYPLLB_PIXCLK_RESYNC_CNTL_BASE_IDX                                                          1
136 #define mmPHYPLLC_PIXCLK_RESYNC_CNTL                                                                   0x0042
137 #define mmPHYPLLC_PIXCLK_RESYNC_CNTL_BASE_IDX                                                          1
138 #define mmPHYPLLD_PIXCLK_RESYNC_CNTL                                                                   0x0043
139 #define mmPHYPLLD_PIXCLK_RESYNC_CNTL_BASE_IDX                                                          1
140 #define mmDP_DTO_DBUF_EN                                                                               0x0044
141 #define mmDP_DTO_DBUF_EN_BASE_IDX                                                                      1
142 #define mmDSCCLK3_DTO_PARAM                                                                            0x0045
143 #define mmDSCCLK3_DTO_PARAM_BASE_IDX                                                                   1
144 #define mmDSCCLK4_DTO_PARAM                                                                            0x0046
145 #define mmDSCCLK4_DTO_PARAM_BASE_IDX                                                                   1
146 #define mmDPREFCLK_CGTT_BLK_CTRL_REG                                                                   0x0048
147 #define mmDPREFCLK_CGTT_BLK_CTRL_REG_BASE_IDX                                                          1
148 #define mmREFCLK_CNTL                                                                                  0x0049
149 #define mmREFCLK_CNTL_BASE_IDX                                                                         1
150 #define mmREFCLK_CGTT_BLK_CTRL_REG                                                                     0x004b
151 #define mmREFCLK_CGTT_BLK_CTRL_REG_BASE_IDX                                                            1
152 #define mmPHYPLLE_PIXCLK_RESYNC_CNTL                                                                   0x004c
153 #define mmPHYPLLE_PIXCLK_RESYNC_CNTL_BASE_IDX                                                          1
154 #define mmDCCG_PERFMON_CNTL2                                                                           0x004e
155 #define mmDCCG_PERFMON_CNTL2_BASE_IDX                                                                  1
156 #define mmDCCG_DS_DTO_INCR                                                                             0x0053
157 #define mmDCCG_DS_DTO_INCR_BASE_IDX                                                                    1
158 #define mmDCCG_DS_DTO_MODULO                                                                           0x0054
159 #define mmDCCG_DS_DTO_MODULO_BASE_IDX                                                                  1
160 #define mmDCCG_DS_CNTL                                                                                 0x0055
161 #define mmDCCG_DS_CNTL_BASE_IDX                                                                        1
162 #define mmDCCG_DS_HW_CAL_INTERVAL                                                                      0x0056
163 #define mmDCCG_DS_HW_CAL_INTERVAL_BASE_IDX                                                             1
164 #define mmDPREFCLK_CNTL                                                                                0x0058
165 #define mmDPREFCLK_CNTL_BASE_IDX                                                                       1
166 #define mmDCE_VERSION                                                                                  0x005e
167 #define mmDCE_VERSION_BASE_IDX                                                                         1
168 #define mmDCCG_GTC_CNTL                                                                                0x0060
169 #define mmDCCG_GTC_CNTL_BASE_IDX                                                                       1
170 #define mmDCCG_GTC_DTO_INCR                                                                            0x0061
171 #define mmDCCG_GTC_DTO_INCR_BASE_IDX                                                                   1
172 #define mmDCCG_GTC_DTO_MODULO                                                                          0x0062
173 #define mmDCCG_GTC_DTO_MODULO_BASE_IDX                                                                 1
174 #define mmDCCG_GTC_CURRENT                                                                             0x0063
175 #define mmDCCG_GTC_CURRENT_BASE_IDX                                                                    1
176 #define mmDSCCLK0_DTO_PARAM                                                                            0x006c
177 #define mmDSCCLK0_DTO_PARAM_BASE_IDX                                                                   1
178 #define mmDSCCLK1_DTO_PARAM                                                                            0x006d
179 #define mmDSCCLK1_DTO_PARAM_BASE_IDX                                                                   1
180 #define mmDSCCLK2_DTO_PARAM                                                                            0x006e
181 #define mmDSCCLK2_DTO_PARAM_BASE_IDX                                                                   1
182 #define mmMILLISECOND_TIME_BASE_DIV                                                                    0x0070
183 #define mmMILLISECOND_TIME_BASE_DIV_BASE_IDX                                                           1
184 #define mmDISPCLK_FREQ_CHANGE_CNTL                                                                     0x0071
185 #define mmDISPCLK_FREQ_CHANGE_CNTL_BASE_IDX                                                            1
186 #define mmDC_MEM_GLOBAL_PWR_REQ_CNTL                                                                   0x0072
187 #define mmDC_MEM_GLOBAL_PWR_REQ_CNTL_BASE_IDX                                                          1
188 #define mmDCCG_PERFMON_CNTL                                                                            0x0073
189 #define mmDCCG_PERFMON_CNTL_BASE_IDX                                                                   1
190 #define mmDCCG_GATE_DISABLE_CNTL                                                                       0x0074
191 #define mmDCCG_GATE_DISABLE_CNTL_BASE_IDX                                                              1
192 #define mmDISPCLK_CGTT_BLK_CTRL_REG                                                                    0x0075
193 #define mmDISPCLK_CGTT_BLK_CTRL_REG_BASE_IDX                                                           1
194 #define mmSOCCLK_CGTT_BLK_CTRL_REG                                                                     0x0076
195 #define mmSOCCLK_CGTT_BLK_CTRL_REG_BASE_IDX                                                            1
196 #define mmDCCG_CAC_STATUS                                                                              0x0077
197 #define mmDCCG_CAC_STATUS_BASE_IDX                                                                     1
198 #define mmMICROSECOND_TIME_BASE_DIV                                                                    0x007b
199 #define mmMICROSECOND_TIME_BASE_DIV_BASE_IDX                                                           1
200 #define mmDCCG_GATE_DISABLE_CNTL2                                                                      0x007c
201 #define mmDCCG_GATE_DISABLE_CNTL2_BASE_IDX                                                             1
202 #define mmSYMCLK_CGTT_BLK_CTRL_REG                                                                     0x007d
203 #define mmSYMCLK_CGTT_BLK_CTRL_REG_BASE_IDX                                                            1
204 #define mmDCCG_DISP_CNTL_REG                                                                           0x007f
205 #define mmDCCG_DISP_CNTL_REG_BASE_IDX                                                                  1
206 #define mmOTG0_PIXEL_RATE_CNTL                                                                         0x0080
207 #define mmOTG0_PIXEL_RATE_CNTL_BASE_IDX                                                                1
208 #define mmDP_DTO0_PHASE                                                                                0x0081
209 #define mmDP_DTO0_PHASE_BASE_IDX                                                                       1
210 #define mmDP_DTO0_MODULO                                                                               0x0082
211 #define mmDP_DTO0_MODULO_BASE_IDX                                                                      1
212 #define mmOTG0_PHYPLL_PIXEL_RATE_CNTL                                                                  0x0083
213 #define mmOTG0_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX                                                         1
214 #define mmOTG1_PIXEL_RATE_CNTL                                                                         0x0084
215 #define mmOTG1_PIXEL_RATE_CNTL_BASE_IDX                                                                1
216 #define mmDP_DTO1_PHASE                                                                                0x0085
217 #define mmDP_DTO1_PHASE_BASE_IDX                                                                       1
218 #define mmDP_DTO1_MODULO                                                                               0x0086
219 #define mmDP_DTO1_MODULO_BASE_IDX                                                                      1
220 #define mmOTG1_PHYPLL_PIXEL_RATE_CNTL                                                                  0x0087
221 #define mmOTG1_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX                                                         1
222 #define mmOTG2_PIXEL_RATE_CNTL                                                                         0x0088
223 #define mmOTG2_PIXEL_RATE_CNTL_BASE_IDX                                                                1
224 #define mmDP_DTO2_PHASE                                                                                0x0089
225 #define mmDP_DTO2_PHASE_BASE_IDX                                                                       1
226 #define mmDP_DTO2_MODULO                                                                               0x008a
227 #define mmDP_DTO2_MODULO_BASE_IDX                                                                      1
228 #define mmOTG2_PHYPLL_PIXEL_RATE_CNTL                                                                  0x008b
229 #define mmOTG2_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX                                                         1
230 #define mmOTG3_PIXEL_RATE_CNTL                                                                         0x008c
231 #define mmOTG3_PIXEL_RATE_CNTL_BASE_IDX                                                                1
232 #define mmDP_DTO3_PHASE                                                                                0x008d
233 #define mmDP_DTO3_PHASE_BASE_IDX                                                                       1
234 #define mmDP_DTO3_MODULO                                                                               0x008e
235 #define mmDP_DTO3_MODULO_BASE_IDX                                                                      1
236 #define mmOTG3_PHYPLL_PIXEL_RATE_CNTL                                                                  0x008f
237 #define mmOTG3_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX                                                         1
238 #define mmOTG4_PIXEL_RATE_CNTL                                                                         0x0090
239 #define mmOTG4_PIXEL_RATE_CNTL_BASE_IDX                                                                1
240 #define mmDP_DTO4_PHASE                                                                                0x0091
241 #define mmDP_DTO4_PHASE_BASE_IDX                                                                       1
242 #define mmDP_DTO4_MODULO                                                                               0x0092
243 #define mmDP_DTO4_MODULO_BASE_IDX                                                                      1
244 #define mmOTG4_PHYPLL_PIXEL_RATE_CNTL                                                                  0x0093
245 #define mmOTG4_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX                                                         1
246 #define mmDPPCLK_CGTT_BLK_CTRL_REG                                                                     0x0098
247 #define mmDPPCLK_CGTT_BLK_CTRL_REG_BASE_IDX                                                            1
248 #define mmDPPCLK0_DTO_PARAM                                                                            0x0099
249 #define mmDPPCLK0_DTO_PARAM_BASE_IDX                                                                   1
250 #define mmDPPCLK1_DTO_PARAM                                                                            0x009a
251 #define mmDPPCLK1_DTO_PARAM_BASE_IDX                                                                   1
252 #define mmDPPCLK2_DTO_PARAM                                                                            0x009b
253 #define mmDPPCLK2_DTO_PARAM_BASE_IDX                                                                   1
254 #define mmDPPCLK3_DTO_PARAM                                                                            0x009c
255 #define mmDPPCLK3_DTO_PARAM_BASE_IDX                                                                   1
256 #define mmDPPCLK4_DTO_PARAM                                                                            0x009d
257 #define mmDPPCLK4_DTO_PARAM_BASE_IDX                                                                   1
258 #define mmDCCG_CAC_STATUS2                                                                             0x009f
259 #define mmDCCG_CAC_STATUS2_BASE_IDX                                                                    1
260 #define mmSYMCLKA_CLOCK_ENABLE                                                                         0x00a0
261 #define mmSYMCLKA_CLOCK_ENABLE_BASE_IDX                                                                1
262 #define mmSYMCLKB_CLOCK_ENABLE                                                                         0x00a1
263 #define mmSYMCLKB_CLOCK_ENABLE_BASE_IDX                                                                1
264 #define mmSYMCLKC_CLOCK_ENABLE                                                                         0x00a2
265 #define mmSYMCLKC_CLOCK_ENABLE_BASE_IDX                                                                1
266 #define mmSYMCLKD_CLOCK_ENABLE                                                                         0x00a3
267 #define mmSYMCLKD_CLOCK_ENABLE_BASE_IDX                                                                1
268 #define mmSYMCLKE_CLOCK_ENABLE                                                                         0x00a4
269 #define mmSYMCLKE_CLOCK_ENABLE_BASE_IDX                                                                1
270 #define mmDCCG_SOFT_RESET                                                                              0x00a6
271 #define mmDCCG_SOFT_RESET_BASE_IDX                                                                     1
272 #define mmDSCCLK_DTO_CTRL                                                                              0x00a7
273 #define mmDSCCLK_DTO_CTRL_BASE_IDX                                                                     1
274 #define mmDCCG_AUDIO_DTO_SOURCE                                                                        0x00ab
275 #define mmDCCG_AUDIO_DTO_SOURCE_BASE_IDX                                                               1
276 #define mmDCCG_AUDIO_DTO0_PHASE                                                                        0x00ac
277 #define mmDCCG_AUDIO_DTO0_PHASE_BASE_IDX                                                               1
278 #define mmDCCG_AUDIO_DTO0_MODULE                                                                       0x00ad
279 #define mmDCCG_AUDIO_DTO0_MODULE_BASE_IDX                                                              1
280 #define mmDCCG_AUDIO_DTO1_PHASE                                                                        0x00ae
281 #define mmDCCG_AUDIO_DTO1_PHASE_BASE_IDX                                                               1
282 #define mmDCCG_AUDIO_DTO1_MODULE                                                                       0x00af
283 #define mmDCCG_AUDIO_DTO1_MODULE_BASE_IDX                                                              1
284 #define mmDCCG_VSYNC_OTG0_LATCH_VALUE                                                                  0x00b0
285 #define mmDCCG_VSYNC_OTG0_LATCH_VALUE_BASE_IDX                                                         1
286 #define mmDCCG_VSYNC_OTG1_LATCH_VALUE                                                                  0x00b1
287 #define mmDCCG_VSYNC_OTG1_LATCH_VALUE_BASE_IDX                                                         1
288 #define mmDCCG_VSYNC_OTG2_LATCH_VALUE                                                                  0x00b2
289 #define mmDCCG_VSYNC_OTG2_LATCH_VALUE_BASE_IDX                                                         1
290 #define mmDCCG_VSYNC_OTG3_LATCH_VALUE                                                                  0x00b3
291 #define mmDCCG_VSYNC_OTG3_LATCH_VALUE_BASE_IDX                                                         1
292 #define mmDCCG_VSYNC_OTG4_LATCH_VALUE                                                                  0x00b4
293 #define mmDCCG_VSYNC_OTG4_LATCH_VALUE_BASE_IDX                                                         1
294 #define mmDCCG_VSYNC_OTG5_LATCH_VALUE                                                                  0x00b5
295 #define mmDCCG_VSYNC_OTG5_LATCH_VALUE_BASE_IDX                                                         1
296 #define mmDPPCLK_DTO_CTRL                                                                              0x00b6
297 #define mmDPPCLK_DTO_CTRL_BASE_IDX                                                                     1
298 #define mmDCCG_VSYNC_CNT_CTRL                                                                          0x00b8
299 #define mmDCCG_VSYNC_CNT_CTRL_BASE_IDX                                                                 1
300 #define mmDCCG_VSYNC_CNT_INT_CTRL                                                                      0x00b9
301 #define mmDCCG_VSYNC_CNT_INT_CTRL_BASE_IDX                                                             1
302 #define mmFORCE_SYMCLK_DISABLE                                                                         0x00ba
303 #define mmFORCE_SYMCLK_DISABLE_BASE_IDX                                                                1
304 #define mmPHYASYMCLK_CLOCK_CNTL                                                                        0x0052
305 #define mmPHYASYMCLK_CLOCK_CNTL_BASE_IDX                                                               2
306 #define mmPHYBSYMCLK_CLOCK_CNTL                                                                        0x0053
307 #define mmPHYBSYMCLK_CLOCK_CNTL_BASE_IDX                                                               2
308 #define mmPHYCSYMCLK_CLOCK_CNTL                                                                        0x0054
309 #define mmPHYCSYMCLK_CLOCK_CNTL_BASE_IDX                                                               2
310 #define mmPHYDSYMCLK_CLOCK_CNTL                                                                        0x0055
311 #define mmPHYDSYMCLK_CLOCK_CNTL_BASE_IDX                                                               2
312 #define mmPHYESYMCLK_CLOCK_CNTL                                                                        0x0056
313 #define mmPHYESYMCLK_CLOCK_CNTL_BASE_IDX                                                               2
314 
315 
316 // addressBlock: dce_dc_dccg_dccg_dfs_dispdec
317 // base address: 0x0
318 #define mmDENTIST_DISPCLK_CNTL                                                                         0x0064
319 #define mmDENTIST_DISPCLK_CNTL_BASE_IDX                                                                1
320 
321 
322 // addressBlock: dce_dc_dccg_dccg_dcperfmon0_dc_perfmon_dispdec
323 // base address: 0x0
324 #define mmDC_PERFMON0_PERFCOUNTER_CNTL                                                                 0x0000
325 #define mmDC_PERFMON0_PERFCOUNTER_CNTL_BASE_IDX                                                        2
326 #define mmDC_PERFMON0_PERFCOUNTER_CNTL2                                                                0x0001
327 #define mmDC_PERFMON0_PERFCOUNTER_CNTL2_BASE_IDX                                                       2
328 #define mmDC_PERFMON0_PERFCOUNTER_STATE                                                                0x0002
329 #define mmDC_PERFMON0_PERFCOUNTER_STATE_BASE_IDX                                                       2
330 #define mmDC_PERFMON0_PERFMON_CNTL                                                                     0x0003
331 #define mmDC_PERFMON0_PERFMON_CNTL_BASE_IDX                                                            2
332 #define mmDC_PERFMON0_PERFMON_CNTL2                                                                    0x0004
333 #define mmDC_PERFMON0_PERFMON_CNTL2_BASE_IDX                                                           2
334 #define mmDC_PERFMON0_PERFMON_CVALUE_INT_MISC                                                          0x0005
335 #define mmDC_PERFMON0_PERFMON_CVALUE_INT_MISC_BASE_IDX                                                 2
336 #define mmDC_PERFMON0_PERFMON_CVALUE_LOW                                                               0x0006
337 #define mmDC_PERFMON0_PERFMON_CVALUE_LOW_BASE_IDX                                                      2
338 #define mmDC_PERFMON0_PERFMON_HI                                                                       0x0007
339 #define mmDC_PERFMON0_PERFMON_HI_BASE_IDX                                                              2
340 #define mmDC_PERFMON0_PERFMON_LOW                                                                      0x0008
341 #define mmDC_PERFMON0_PERFMON_LOW_BASE_IDX                                                             2
342 
343 
344 // addressBlock: dce_dc_dccg_dccg_dcperfmon1_dc_perfmon_dispdec
345 // base address: 0x30
346 #define mmDC_PERFMON1_PERFCOUNTER_CNTL                                                                 0x000c
347 #define mmDC_PERFMON1_PERFCOUNTER_CNTL_BASE_IDX                                                        2
348 #define mmDC_PERFMON1_PERFCOUNTER_CNTL2                                                                0x000d
349 #define mmDC_PERFMON1_PERFCOUNTER_CNTL2_BASE_IDX                                                       2
350 #define mmDC_PERFMON1_PERFCOUNTER_STATE                                                                0x000e
351 #define mmDC_PERFMON1_PERFCOUNTER_STATE_BASE_IDX                                                       2
352 #define mmDC_PERFMON1_PERFMON_CNTL                                                                     0x000f
353 #define mmDC_PERFMON1_PERFMON_CNTL_BASE_IDX                                                            2
354 #define mmDC_PERFMON1_PERFMON_CNTL2                                                                    0x0010
355 #define mmDC_PERFMON1_PERFMON_CNTL2_BASE_IDX                                                           2
356 #define mmDC_PERFMON1_PERFMON_CVALUE_INT_MISC                                                          0x0011
357 #define mmDC_PERFMON1_PERFMON_CVALUE_INT_MISC_BASE_IDX                                                 2
358 #define mmDC_PERFMON1_PERFMON_CVALUE_LOW                                                               0x0012
359 #define mmDC_PERFMON1_PERFMON_CVALUE_LOW_BASE_IDX                                                      2
360 #define mmDC_PERFMON1_PERFMON_HI                                                                       0x0013
361 #define mmDC_PERFMON1_PERFMON_HI_BASE_IDX                                                              2
362 #define mmDC_PERFMON1_PERFMON_LOW                                                                      0x0014
363 #define mmDC_PERFMON1_PERFMON_LOW_BASE_IDX                                                             2
364 
365 
366 // addressBlock: dce_dc_dmu_dc_pg_dispdec
367 // base address: 0x0
368 #define mmDOMAIN0_PG_CONFIG                                                                            0x0080
369 #define mmDOMAIN0_PG_CONFIG_BASE_IDX                                                                   2
370 #define mmDOMAIN0_PG_STATUS                                                                            0x0081
371 #define mmDOMAIN0_PG_STATUS_BASE_IDX                                                                   2
372 #define mmDOMAIN1_PG_CONFIG                                                                            0x0082
373 #define mmDOMAIN1_PG_CONFIG_BASE_IDX                                                                   2
374 #define mmDOMAIN1_PG_STATUS                                                                            0x0083
375 #define mmDOMAIN1_PG_STATUS_BASE_IDX                                                                   2
376 #define mmDOMAIN2_PG_CONFIG                                                                            0x0084
377 #define mmDOMAIN2_PG_CONFIG_BASE_IDX                                                                   2
378 #define mmDOMAIN2_PG_STATUS                                                                            0x0085
379 #define mmDOMAIN2_PG_STATUS_BASE_IDX                                                                   2
380 #define mmDOMAIN3_PG_CONFIG                                                                            0x0086
381 #define mmDOMAIN3_PG_CONFIG_BASE_IDX                                                                   2
382 #define mmDOMAIN3_PG_STATUS                                                                            0x0087
383 #define mmDOMAIN3_PG_STATUS_BASE_IDX                                                                   2
384 #define mmDOMAIN4_PG_CONFIG                                                                            0x0088
385 #define mmDOMAIN4_PG_CONFIG_BASE_IDX                                                                   2
386 #define mmDOMAIN4_PG_STATUS                                                                            0x0089
387 #define mmDOMAIN4_PG_STATUS_BASE_IDX                                                                   2
388 #define mmDOMAIN5_PG_CONFIG                                                                            0x008a
389 #define mmDOMAIN5_PG_CONFIG_BASE_IDX                                                                   2
390 #define mmDOMAIN5_PG_STATUS                                                                            0x008b
391 #define mmDOMAIN5_PG_STATUS_BASE_IDX                                                                   2
392 #define mmDOMAIN6_PG_CONFIG                                                                            0x008c
393 #define mmDOMAIN6_PG_CONFIG_BASE_IDX                                                                   2
394 #define mmDOMAIN6_PG_STATUS                                                                            0x008d
395 #define mmDOMAIN6_PG_STATUS_BASE_IDX                                                                   2
396 #define mmDOMAIN7_PG_CONFIG                                                                            0x008e
397 #define mmDOMAIN7_PG_CONFIG_BASE_IDX                                                                   2
398 #define mmDOMAIN7_PG_STATUS                                                                            0x008f
399 #define mmDOMAIN7_PG_STATUS_BASE_IDX                                                                   2
400 #define mmDOMAIN8_PG_CONFIG                                                                            0x0090
401 #define mmDOMAIN8_PG_CONFIG_BASE_IDX                                                                   2
402 #define mmDOMAIN8_PG_STATUS                                                                            0x0091
403 #define mmDOMAIN8_PG_STATUS_BASE_IDX                                                                   2
404 #define mmDOMAIN9_PG_CONFIG                                                                            0x0092
405 #define mmDOMAIN9_PG_CONFIG_BASE_IDX                                                                   2
406 #define mmDOMAIN9_PG_STATUS                                                                            0x0093
407 #define mmDOMAIN9_PG_STATUS_BASE_IDX                                                                   2
408 #define mmDOMAIN16_PG_CONFIG                                                                           0x00a1
409 #define mmDOMAIN16_PG_CONFIG_BASE_IDX                                                                  2
410 #define mmDOMAIN16_PG_STATUS                                                                           0x00a2
411 #define mmDOMAIN16_PG_STATUS_BASE_IDX                                                                  2
412 #define mmDOMAIN17_PG_CONFIG                                                                           0x00a3
413 #define mmDOMAIN17_PG_CONFIG_BASE_IDX                                                                  2
414 #define mmDOMAIN17_PG_STATUS                                                                           0x00a4
415 #define mmDOMAIN17_PG_STATUS_BASE_IDX                                                                  2
416 #define mmDOMAIN18_PG_CONFIG                                                                           0x00a5
417 #define mmDOMAIN18_PG_CONFIG_BASE_IDX                                                                  2
418 #define mmDOMAIN18_PG_STATUS                                                                           0x00a6
419 #define mmDOMAIN18_PG_STATUS_BASE_IDX                                                                  2
420 #define mmDOMAIN19_PG_CONFIG                                                                           0x00a7
421 #define mmDOMAIN19_PG_CONFIG_BASE_IDX                                                                  2
422 #define mmDOMAIN19_PG_STATUS                                                                           0x00a8
423 #define mmDOMAIN19_PG_STATUS_BASE_IDX                                                                  2
424 #define mmDOMAIN20_PG_CONFIG                                                                           0x00a9
425 #define mmDOMAIN20_PG_CONFIG_BASE_IDX                                                                  2
426 #define mmDOMAIN20_PG_STATUS                                                                           0x00aa
427 #define mmDOMAIN20_PG_STATUS_BASE_IDX                                                                  2
428 #define mmDCPG_INTERRUPT_STATUS                                                                        0x00ad
429 #define mmDCPG_INTERRUPT_STATUS_BASE_IDX                                                               2
430 #define mmDCPG_INTERRUPT_STATUS_2                                                                      0x00ae
431 #define mmDCPG_INTERRUPT_STATUS_2_BASE_IDX                                                             2
432 #define mmDCPG_INTERRUPT_CONTROL_1                                                                     0x00af
433 #define mmDCPG_INTERRUPT_CONTROL_1_BASE_IDX                                                            2
434 #define mmDCPG_INTERRUPT_CONTROL_2                                                                     0x00b0
435 #define mmDCPG_INTERRUPT_CONTROL_2_BASE_IDX                                                            2
436 #define mmDCPG_INTERRUPT_CONTROL_3                                                                     0x00b1
437 #define mmDCPG_INTERRUPT_CONTROL_3_BASE_IDX                                                            2
438 #define mmDC_IP_REQUEST_CNTL                                                                           0x00b2
439 #define mmDC_IP_REQUEST_CNTL_BASE_IDX                                                                  2
440 
441 
442 // addressBlock: dce_dc_dmu_dmu_dcperfmon_dc_perfmon_dispdec
443 // base address: 0x2f8
444 #define mmDC_PERFMON2_PERFCOUNTER_CNTL                                                                 0x00be
445 #define mmDC_PERFMON2_PERFCOUNTER_CNTL_BASE_IDX                                                        2
446 #define mmDC_PERFMON2_PERFCOUNTER_CNTL2                                                                0x00bf
447 #define mmDC_PERFMON2_PERFCOUNTER_CNTL2_BASE_IDX                                                       2
448 #define mmDC_PERFMON2_PERFCOUNTER_STATE                                                                0x00c0
449 #define mmDC_PERFMON2_PERFCOUNTER_STATE_BASE_IDX                                                       2
450 #define mmDC_PERFMON2_PERFMON_CNTL                                                                     0x00c1
451 #define mmDC_PERFMON2_PERFMON_CNTL_BASE_IDX                                                            2
452 #define mmDC_PERFMON2_PERFMON_CNTL2                                                                    0x00c2
453 #define mmDC_PERFMON2_PERFMON_CNTL2_BASE_IDX                                                           2
454 #define mmDC_PERFMON2_PERFMON_CVALUE_INT_MISC                                                          0x00c3
455 #define mmDC_PERFMON2_PERFMON_CVALUE_INT_MISC_BASE_IDX                                                 2
456 #define mmDC_PERFMON2_PERFMON_CVALUE_LOW                                                               0x00c4
457 #define mmDC_PERFMON2_PERFMON_CVALUE_LOW_BASE_IDX                                                      2
458 #define mmDC_PERFMON2_PERFMON_HI                                                                       0x00c5
459 #define mmDC_PERFMON2_PERFMON_HI_BASE_IDX                                                              2
460 #define mmDC_PERFMON2_PERFMON_LOW                                                                      0x00c6
461 #define mmDC_PERFMON2_PERFMON_LOW_BASE_IDX                                                             2
462 
463 
464 // addressBlock: dce_dc_dmu_dmu_misc_dispdec
465 // base address: 0x0
466 #define mmCC_DC_PIPE_DIS                                                                               0x00ca
467 #define mmCC_DC_PIPE_DIS_BASE_IDX                                                                      2
468 #define mmDMU_CLK_CNTL                                                                                 0x00cb
469 #define mmDMU_CLK_CNTL_BASE_IDX                                                                        2
470 #define mmDMU_MEM_PWR_CNTL                                                                             0x00cc
471 #define mmDMU_MEM_PWR_CNTL_BASE_IDX                                                                    2
472 #define mmDMCU_SMU_INTERRUPT_CNTL                                                                      0x00cd
473 #define mmDMCU_SMU_INTERRUPT_CNTL_BASE_IDX                                                             2
474 #define mmSMU_INTERRUPT_CONTROL                                                                        0x00ce
475 #define mmSMU_INTERRUPT_CONTROL_BASE_IDX                                                               2
476 #define mmDMU_MISC_ALLOW_DS_FORCE                                                                      0x00d6
477 #define mmDMU_MISC_ALLOW_DS_FORCE_BASE_IDX                                                             2
478 
479 
480 // addressBlock: dce_dc_dmu_dmcu_dispdec
481 // base address: 0x0
482 #define mmDMCU_CTRL                                                                                    0x00da
483 #define mmDMCU_CTRL_BASE_IDX                                                                           2
484 #define mmDMCU_STATUS                                                                                  0x00db
485 #define mmDMCU_STATUS_BASE_IDX                                                                         2
486 #define mmDMCU_PC_START_ADDR                                                                           0x00dc
487 #define mmDMCU_PC_START_ADDR_BASE_IDX                                                                  2
488 #define mmDMCU_FW_START_ADDR                                                                           0x00dd
489 #define mmDMCU_FW_START_ADDR_BASE_IDX                                                                  2
490 #define mmDMCU_FW_END_ADDR                                                                             0x00de
491 #define mmDMCU_FW_END_ADDR_BASE_IDX                                                                    2
492 #define mmDMCU_FW_ISR_START_ADDR                                                                       0x00df
493 #define mmDMCU_FW_ISR_START_ADDR_BASE_IDX                                                              2
494 #define mmDMCU_FW_CS_HI                                                                                0x00e0
495 #define mmDMCU_FW_CS_HI_BASE_IDX                                                                       2
496 #define mmDMCU_FW_CS_LO                                                                                0x00e1
497 #define mmDMCU_FW_CS_LO_BASE_IDX                                                                       2
498 #define mmDMCU_RAM_ACCESS_CTRL                                                                         0x00e2
499 #define mmDMCU_RAM_ACCESS_CTRL_BASE_IDX                                                                2
500 #define mmDMCU_ERAM_WR_CTRL                                                                            0x00e3
501 #define mmDMCU_ERAM_WR_CTRL_BASE_IDX                                                                   2
502 #define mmDMCU_ERAM_WR_DATA                                                                            0x00e4
503 #define mmDMCU_ERAM_WR_DATA_BASE_IDX                                                                   2
504 #define mmDMCU_ERAM_RD_CTRL                                                                            0x00e5
505 #define mmDMCU_ERAM_RD_CTRL_BASE_IDX                                                                   2
506 #define mmDMCU_ERAM_RD_DATA                                                                            0x00e6
507 #define mmDMCU_ERAM_RD_DATA_BASE_IDX                                                                   2
508 #define mmDMCU_IRAM_WR_CTRL                                                                            0x00e7
509 #define mmDMCU_IRAM_WR_CTRL_BASE_IDX                                                                   2
510 #define mmDMCU_IRAM_WR_DATA                                                                            0x00e8
511 #define mmDMCU_IRAM_WR_DATA_BASE_IDX                                                                   2
512 #define mmDMCU_IRAM_RD_CTRL                                                                            0x00e9
513 #define mmDMCU_IRAM_RD_CTRL_BASE_IDX                                                                   2
514 #define mmDMCU_IRAM_RD_DATA                                                                            0x00ea
515 #define mmDMCU_IRAM_RD_DATA_BASE_IDX                                                                   2
516 #define mmDMCU_EVENT_TRIGGER                                                                           0x00eb
517 #define mmDMCU_EVENT_TRIGGER_BASE_IDX                                                                  2
518 #define mmDMCU_UC_INTERNAL_INT_STATUS                                                                  0x00ec
519 #define mmDMCU_UC_INTERNAL_INT_STATUS_BASE_IDX                                                         2
520 #define mmDMCU_SS_INTERRUPT_CNTL_STATUS                                                                0x00ed
521 #define mmDMCU_SS_INTERRUPT_CNTL_STATUS_BASE_IDX                                                       2
522 #define mmDMCU_INTERRUPT_STATUS                                                                        0x00ee
523 #define mmDMCU_INTERRUPT_STATUS_BASE_IDX                                                               2
524 #define mmDMCU_INTERRUPT_STATUS_1                                                                      0x00ef
525 #define mmDMCU_INTERRUPT_STATUS_1_BASE_IDX                                                             2
526 #define mmDMCU_INTERRUPT_TO_HOST_EN_MASK                                                               0x00f0
527 #define mmDMCU_INTERRUPT_TO_HOST_EN_MASK_BASE_IDX                                                      2
528 #define mmDMCU_INTERRUPT_TO_UC_EN_MASK                                                                 0x00f1
529 #define mmDMCU_INTERRUPT_TO_UC_EN_MASK_BASE_IDX                                                        2
530 #define mmDMCU_INTERRUPT_TO_UC_EN_MASK_1                                                               0x00f2
531 #define mmDMCU_INTERRUPT_TO_UC_EN_MASK_1_BASE_IDX                                                      2
532 #define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL                                                            0x00f3
533 #define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_BASE_IDX                                                   2
534 #define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1                                                          0x00f4
535 #define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1_BASE_IDX                                                 2
536 #define mmDC_DMCU_SCRATCH                                                                              0x00f5
537 #define mmDC_DMCU_SCRATCH_BASE_IDX                                                                     2
538 #define mmDMCU_INT_CNT                                                                                 0x00f6
539 #define mmDMCU_INT_CNT_BASE_IDX                                                                        2
540 #define mmDMCU_FW_CHECKSUM_SMPL_BYTE_POS                                                               0x00f7
541 #define mmDMCU_FW_CHECKSUM_SMPL_BYTE_POS_BASE_IDX                                                      2
542 #define mmDMCU_UC_CLK_GATING_CNTL                                                                      0x00f8
543 #define mmDMCU_UC_CLK_GATING_CNTL_BASE_IDX                                                             2
544 #define mmMASTER_COMM_DATA_REG1                                                                        0x00f9
545 #define mmMASTER_COMM_DATA_REG1_BASE_IDX                                                               2
546 #define mmMASTER_COMM_DATA_REG2                                                                        0x00fa
547 #define mmMASTER_COMM_DATA_REG2_BASE_IDX                                                               2
548 #define mmMASTER_COMM_DATA_REG3                                                                        0x00fb
549 #define mmMASTER_COMM_DATA_REG3_BASE_IDX                                                               2
550 #define mmMASTER_COMM_CMD_REG                                                                          0x00fc
551 #define mmMASTER_COMM_CMD_REG_BASE_IDX                                                                 2
552 #define mmMASTER_COMM_CNTL_REG                                                                         0x00fd
553 #define mmMASTER_COMM_CNTL_REG_BASE_IDX                                                                2
554 #define mmSLAVE_COMM_DATA_REG1                                                                         0x00fe
555 #define mmSLAVE_COMM_DATA_REG1_BASE_IDX                                                                2
556 #define mmSLAVE_COMM_DATA_REG2                                                                         0x00ff
557 #define mmSLAVE_COMM_DATA_REG2_BASE_IDX                                                                2
558 #define mmSLAVE_COMM_DATA_REG3                                                                         0x0100
559 #define mmSLAVE_COMM_DATA_REG3_BASE_IDX                                                                2
560 #define mmSLAVE_COMM_CMD_REG                                                                           0x0101
561 #define mmSLAVE_COMM_CMD_REG_BASE_IDX                                                                  2
562 #define mmSLAVE_COMM_CNTL_REG                                                                          0x0102
563 #define mmSLAVE_COMM_CNTL_REG_BASE_IDX                                                                 2
564 #define mmDMCU_PERFMON_INTERRUPT_STATUS1                                                               0x0105
565 #define mmDMCU_PERFMON_INTERRUPT_STATUS1_BASE_IDX                                                      2
566 #define mmDMCU_PERFMON_INTERRUPT_STATUS2                                                               0x0106
567 #define mmDMCU_PERFMON_INTERRUPT_STATUS2_BASE_IDX                                                      2
568 #define mmDMCU_PERFMON_INTERRUPT_STATUS3                                                               0x0107
569 #define mmDMCU_PERFMON_INTERRUPT_STATUS3_BASE_IDX                                                      2
570 #define mmDMCU_PERFMON_INTERRUPT_STATUS4                                                               0x0108
571 #define mmDMCU_PERFMON_INTERRUPT_STATUS4_BASE_IDX                                                      2
572 #define mmDMCU_PERFMON_INTERRUPT_STATUS5                                                               0x0109
573 #define mmDMCU_PERFMON_INTERRUPT_STATUS5_BASE_IDX                                                      2
574 #define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1                                                        0x010a
575 #define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1_BASE_IDX                                               2
576 #define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2                                                        0x010b
577 #define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2_BASE_IDX                                               2
578 #define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3                                                        0x010c
579 #define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3_BASE_IDX                                               2
580 #define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4                                                        0x010d
581 #define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4_BASE_IDX                                               2
582 #define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5                                                        0x010e
583 #define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5_BASE_IDX                                               2
584 #define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1                                                   0x010f
585 #define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1_BASE_IDX                                          2
586 #define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2                                                   0x0110
587 #define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2_BASE_IDX                                          2
588 #define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3                                                   0x0111
589 #define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3_BASE_IDX                                          2
590 #define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4                                                   0x0112
591 #define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4_BASE_IDX                                          2
592 #define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5                                                   0x0113
593 #define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5_BASE_IDX                                          2
594 #define mmDMCU_DPRX_INTERRUPT_STATUS1                                                                  0x0114
595 #define mmDMCU_DPRX_INTERRUPT_STATUS1_BASE_IDX                                                         2
596 #define mmDMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1                                                           0x0115
597 #define mmDMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1_BASE_IDX                                                  2
598 #define mmDMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1                                                      0x0116
599 #define mmDMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1_BASE_IDX                                             2
600 #define mmDMCU_INTERRUPT_STATUS_CONTINUE                                                               0x0119
601 #define mmDMCU_INTERRUPT_STATUS_CONTINUE_BASE_IDX                                                      2
602 #define mmDMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE                                                        0x011a
603 #define mmDMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE_BASE_IDX                                               2
604 #define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE                                                   0x011b
605 #define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE_BASE_IDX                                          2
606 #define mmDMCU_INT_CNT_CONTINUE                                                                        0x011c
607 #define mmDMCU_INT_CNT_CONTINUE_BASE_IDX                                                               2
608 #define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2                                                      0x011d
609 #define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2_BASE_IDX                                             2
610 #define mmDMCU_INTERRUPT_STATUS_2                                                                      0x011e
611 #define mmDMCU_INTERRUPT_STATUS_2_BASE_IDX                                                             2
612 #define mmDMCU_INTERRUPT_TO_UC_EN_MASK_2                                                               0x011f
613 #define mmDMCU_INTERRUPT_TO_UC_EN_MASK_2_BASE_IDX                                                      2
614 #define mmDMCU_INT_CNT_CONT2                                                                           0x0120
615 #define mmDMCU_INT_CNT_CONT2_BASE_IDX                                                                  2
616 #define mmDMCU_INT_CNT_CONT3                                                                           0x0121
617 #define mmDMCU_INT_CNT_CONT3_BASE_IDX                                                                  2
618 #define mmDMCU_INT_CNT_CONT4                                                                           0x0122
619 #define mmDMCU_INT_CNT_CONT4_BASE_IDX                                                                  2
620 
621 
622 // addressBlock: dce_dc_dmu_ihc_dispdec
623 // base address: 0x0
624 #define mmDC_GPU_TIMER_START_POSITION_V_UPDATE                                                         0x0126
625 #define mmDC_GPU_TIMER_START_POSITION_V_UPDATE_BASE_IDX                                                2
626 #define mmDC_GPU_TIMER_START_POSITION_VSTARTUP                                                         0x0127
627 #define mmDC_GPU_TIMER_START_POSITION_VSTARTUP_BASE_IDX                                                2
628 #define mmDC_GPU_TIMER_READ                                                                            0x0128
629 #define mmDC_GPU_TIMER_READ_BASE_IDX                                                                   2
630 #define mmDC_GPU_TIMER_READ_CNTL                                                                       0x0129
631 #define mmDC_GPU_TIMER_READ_CNTL_BASE_IDX                                                              2
632 #define mmDISP_INTERRUPT_STATUS                                                                        0x012a
633 #define mmDISP_INTERRUPT_STATUS_BASE_IDX                                                               2
634 #define mmDISP_INTERRUPT_STATUS_CONTINUE                                                               0x012b
635 #define mmDISP_INTERRUPT_STATUS_CONTINUE_BASE_IDX                                                      2
636 #define mmDISP_INTERRUPT_STATUS_CONTINUE2                                                              0x012c
637 #define mmDISP_INTERRUPT_STATUS_CONTINUE2_BASE_IDX                                                     2
638 #define mmDISP_INTERRUPT_STATUS_CONTINUE3                                                              0x012d
639 #define mmDISP_INTERRUPT_STATUS_CONTINUE3_BASE_IDX                                                     2
640 #define mmDISP_INTERRUPT_STATUS_CONTINUE4                                                              0x012e
641 #define mmDISP_INTERRUPT_STATUS_CONTINUE4_BASE_IDX                                                     2
642 #define mmDISP_INTERRUPT_STATUS_CONTINUE5                                                              0x012f
643 #define mmDISP_INTERRUPT_STATUS_CONTINUE5_BASE_IDX                                                     2
644 #define mmDISP_INTERRUPT_STATUS_CONTINUE6                                                              0x0130
645 #define mmDISP_INTERRUPT_STATUS_CONTINUE6_BASE_IDX                                                     2
646 #define mmDISP_INTERRUPT_STATUS_CONTINUE7                                                              0x0131
647 #define mmDISP_INTERRUPT_STATUS_CONTINUE7_BASE_IDX                                                     2
648 #define mmDISP_INTERRUPT_STATUS_CONTINUE8                                                              0x0132
649 #define mmDISP_INTERRUPT_STATUS_CONTINUE8_BASE_IDX                                                     2
650 #define mmDISP_INTERRUPT_STATUS_CONTINUE9                                                              0x0133
651 #define mmDISP_INTERRUPT_STATUS_CONTINUE9_BASE_IDX                                                     2
652 #define mmDISP_INTERRUPT_STATUS_CONTINUE10                                                             0x0134
653 #define mmDISP_INTERRUPT_STATUS_CONTINUE10_BASE_IDX                                                    2
654 #define mmDISP_INTERRUPT_STATUS_CONTINUE11                                                             0x0135
655 #define mmDISP_INTERRUPT_STATUS_CONTINUE11_BASE_IDX                                                    2
656 #define mmDISP_INTERRUPT_STATUS_CONTINUE12                                                             0x0136
657 #define mmDISP_INTERRUPT_STATUS_CONTINUE12_BASE_IDX                                                    2
658 #define mmDISP_INTERRUPT_STATUS_CONTINUE13                                                             0x0137
659 #define mmDISP_INTERRUPT_STATUS_CONTINUE13_BASE_IDX                                                    2
660 #define mmDISP_INTERRUPT_STATUS_CONTINUE14                                                             0x0138
661 #define mmDISP_INTERRUPT_STATUS_CONTINUE14_BASE_IDX                                                    2
662 #define mmDISP_INTERRUPT_STATUS_CONTINUE15                                                             0x0139
663 #define mmDISP_INTERRUPT_STATUS_CONTINUE15_BASE_IDX                                                    2
664 #define mmDISP_INTERRUPT_STATUS_CONTINUE16                                                             0x013a
665 #define mmDISP_INTERRUPT_STATUS_CONTINUE16_BASE_IDX                                                    2
666 #define mmDISP_INTERRUPT_STATUS_CONTINUE17                                                             0x013b
667 #define mmDISP_INTERRUPT_STATUS_CONTINUE17_BASE_IDX                                                    2
668 #define mmDISP_INTERRUPT_STATUS_CONTINUE18                                                             0x013c
669 #define mmDISP_INTERRUPT_STATUS_CONTINUE18_BASE_IDX                                                    2
670 #define mmDISP_INTERRUPT_STATUS_CONTINUE19                                                             0x013d
671 #define mmDISP_INTERRUPT_STATUS_CONTINUE19_BASE_IDX                                                    2
672 #define mmDISP_INTERRUPT_STATUS_CONTINUE20                                                             0x013e
673 #define mmDISP_INTERRUPT_STATUS_CONTINUE20_BASE_IDX                                                    2
674 #define mmDISP_INTERRUPT_STATUS_CONTINUE21                                                             0x013f
675 #define mmDISP_INTERRUPT_STATUS_CONTINUE21_BASE_IDX                                                    2
676 #define mmDISP_INTERRUPT_STATUS_CONTINUE22                                                             0x0140
677 #define mmDISP_INTERRUPT_STATUS_CONTINUE22_BASE_IDX                                                    2
678 #define mmDC_GPU_TIMER_START_POSITION_VREADY                                                           0x0141
679 #define mmDC_GPU_TIMER_START_POSITION_VREADY_BASE_IDX                                                  2
680 #define mmDC_GPU_TIMER_START_POSITION_FLIP                                                             0x0142
681 #define mmDC_GPU_TIMER_START_POSITION_FLIP_BASE_IDX                                                    2
682 #define mmDC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK                                                 0x0143
683 #define mmDC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK_BASE_IDX                                        2
684 #define mmDC_GPU_TIMER_START_POSITION_FLIP_AWAY                                                        0x0144
685 #define mmDC_GPU_TIMER_START_POSITION_FLIP_AWAY_BASE_IDX                                               2
686 #define mmDISP_INTERRUPT_STATUS_CONTINUE23                                                             0x0145
687 #define mmDISP_INTERRUPT_STATUS_CONTINUE23_BASE_IDX                                                    2
688 #define mmDISP_INTERRUPT_STATUS_CONTINUE24                                                             0x0146
689 #define mmDISP_INTERRUPT_STATUS_CONTINUE24_BASE_IDX                                                    2
690 #define mmDISP_INTERRUPT_STATUS_CONTINUE25                                                             0x0147
691 #define mmDISP_INTERRUPT_STATUS_CONTINUE25_BASE_IDX                                                    2
692 #define mmDCCG_INTERRUPT_DEST                                                                          0x0148
693 #define mmDCCG_INTERRUPT_DEST_BASE_IDX                                                                 2
694 #define mmDMU_INTERRUPT_DEST                                                                           0x0149
695 #define mmDMU_INTERRUPT_DEST_BASE_IDX                                                                  2
696 #define mmDMU_INTERRUPT_DEST2                                                                          0x014a
697 #define mmDMU_INTERRUPT_DEST2_BASE_IDX                                                                 2
698 #define mmDCPG_INTERRUPT_DEST                                                                          0x014b
699 #define mmDCPG_INTERRUPT_DEST_BASE_IDX                                                                 2
700 #define mmDCPG_INTERRUPT_DEST2                                                                         0x014c
701 #define mmDCPG_INTERRUPT_DEST2_BASE_IDX                                                                2
702 #define mmMMHUBBUB_INTERRUPT_DEST                                                                      0x014d
703 #define mmMMHUBBUB_INTERRUPT_DEST_BASE_IDX                                                             2
704 #define mmWB_INTERRUPT_DEST                                                                            0x014e
705 #define mmWB_INTERRUPT_DEST_BASE_IDX                                                                   2
706 #define mmDCHUB_INTERRUPT_DEST                                                                         0x014f
707 #define mmDCHUB_INTERRUPT_DEST_BASE_IDX                                                                2
708 #define mmDCHUB_PERFCOUNTER_INTERRUPT_DEST                                                             0x0150
709 #define mmDCHUB_PERFCOUNTER_INTERRUPT_DEST_BASE_IDX                                                    2
710 #define mmDCHUB_INTERRUPT_DEST2                                                                        0x0151
711 #define mmDCHUB_INTERRUPT_DEST2_BASE_IDX                                                               2
712 #define mmDPP_PERFCOUNTER_INTERRUPT_DEST                                                               0x0152
713 #define mmDPP_PERFCOUNTER_INTERRUPT_DEST_BASE_IDX                                                      2
714 #define mmMPC_INTERRUPT_DEST                                                                           0x0153
715 #define mmMPC_INTERRUPT_DEST_BASE_IDX                                                                  2
716 #define mmOPP_INTERRUPT_DEST                                                                           0x0154
717 #define mmOPP_INTERRUPT_DEST_BASE_IDX                                                                  2
718 #define mmOPTC_INTERRUPT_DEST                                                                          0x0155
719 #define mmOPTC_INTERRUPT_DEST_BASE_IDX                                                                 2
720 #define mmOTG0_INTERRUPT_DEST                                                                          0x0156
721 #define mmOTG0_INTERRUPT_DEST_BASE_IDX                                                                 2
722 #define mmOTG1_INTERRUPT_DEST                                                                          0x0157
723 #define mmOTG1_INTERRUPT_DEST_BASE_IDX                                                                 2
724 #define mmOTG2_INTERRUPT_DEST                                                                          0x0158
725 #define mmOTG2_INTERRUPT_DEST_BASE_IDX                                                                 2
726 #define mmOTG3_INTERRUPT_DEST                                                                          0x0159
727 #define mmOTG3_INTERRUPT_DEST_BASE_IDX                                                                 2
728 #define mmOTG4_INTERRUPT_DEST                                                                          0x015a
729 #define mmOTG4_INTERRUPT_DEST_BASE_IDX                                                                 2
730 #define mmOTG5_INTERRUPT_DEST                                                                          0x015b
731 #define mmOTG5_INTERRUPT_DEST_BASE_IDX                                                                 2
732 #define mmDIG_INTERRUPT_DEST                                                                           0x015c
733 #define mmDIG_INTERRUPT_DEST_BASE_IDX                                                                  2
734 #define mmI2C_DDC_HPD_INTERRUPT_DEST                                                                   0x015d
735 #define mmI2C_DDC_HPD_INTERRUPT_DEST_BASE_IDX                                                          2
736 #define mmDIO_INTERRUPT_DEST                                                                           0x015f
737 #define mmDIO_INTERRUPT_DEST_BASE_IDX                                                                  2
738 #define mmDCIO_INTERRUPT_DEST                                                                          0x0160
739 #define mmDCIO_INTERRUPT_DEST_BASE_IDX                                                                 2
740 #define mmHPD_INTERRUPT_DEST                                                                           0x0161
741 #define mmHPD_INTERRUPT_DEST_BASE_IDX                                                                  2
742 #define mmAZ_INTERRUPT_DEST                                                                            0x0162
743 #define mmAZ_INTERRUPT_DEST_BASE_IDX                                                                   2
744 #define mmAUX_INTERRUPT_DEST                                                                           0x0163
745 #define mmAUX_INTERRUPT_DEST_BASE_IDX                                                                  2
746 #define mmDSC_INTERRUPT_DEST                                                                           0x0164
747 #define mmDSC_INTERRUPT_DEST_BASE_IDX                                                                  2
748 
749 
750 // addressBlock: dce_dc_dmu_fgsec_dispdec
751 // base address: 0x0
752 #define mmDMCUB_RBBMIF_SEC_CNTL                                                                        0x017a
753 #define mmDMCUB_RBBMIF_SEC_CNTL_BASE_IDX                                                               2
754 
755 
756 // addressBlock: dce_dc_dmu_rbbmif_dispdec
757 // base address: 0x0
758 #define mmRBBMIF_TIMEOUT                                                                               0x017f
759 #define mmRBBMIF_TIMEOUT_BASE_IDX                                                                      2
760 #define mmRBBMIF_STATUS                                                                                0x0180
761 #define mmRBBMIF_STATUS_BASE_IDX                                                                       2
762 #define mmRBBMIF_STATUS_2                                                                              0x0181
763 #define mmRBBMIF_STATUS_2_BASE_IDX                                                                     2
764 #define mmRBBMIF_INT_STATUS                                                                            0x0182
765 #define mmRBBMIF_INT_STATUS_BASE_IDX                                                                   2
766 #define mmRBBMIF_TIMEOUT_DIS                                                                           0x0183
767 #define mmRBBMIF_TIMEOUT_DIS_BASE_IDX                                                                  2
768 #define mmRBBMIF_TIMEOUT_DIS_2                                                                         0x0184
769 #define mmRBBMIF_TIMEOUT_DIS_2_BASE_IDX                                                                2
770 #define mmRBBMIF_STATUS_FLAG                                                                           0x0185
771 #define mmRBBMIF_STATUS_FLAG_BASE_IDX                                                                  2
772 
773 
774 // addressBlock: dce_dc_dmu_dmcub_dispdec
775 // base address: 0x0
776 #define mmDMCUB_REGION0_OFFSET                                                                         0x018e
777 #define mmDMCUB_REGION0_OFFSET_BASE_IDX                                                                2
778 #define mmDMCUB_REGION0_OFFSET_HIGH                                                                    0x018f
779 #define mmDMCUB_REGION0_OFFSET_HIGH_BASE_IDX                                                           2
780 #define mmDMCUB_REGION1_OFFSET                                                                         0x0190
781 #define mmDMCUB_REGION1_OFFSET_BASE_IDX                                                                2
782 #define mmDMCUB_REGION1_OFFSET_HIGH                                                                    0x0191
783 #define mmDMCUB_REGION1_OFFSET_HIGH_BASE_IDX                                                           2
784 #define mmDMCUB_REGION2_OFFSET                                                                         0x0192
785 #define mmDMCUB_REGION2_OFFSET_BASE_IDX                                                                2
786 #define mmDMCUB_REGION2_OFFSET_HIGH                                                                    0x0193
787 #define mmDMCUB_REGION2_OFFSET_HIGH_BASE_IDX                                                           2
788 #define mmDMCUB_REGION4_OFFSET                                                                         0x0196
789 #define mmDMCUB_REGION4_OFFSET_BASE_IDX                                                                2
790 #define mmDMCUB_REGION4_OFFSET_HIGH                                                                    0x0197
791 #define mmDMCUB_REGION4_OFFSET_HIGH_BASE_IDX                                                           2
792 #define mmDMCUB_REGION5_OFFSET                                                                         0x0198
793 #define mmDMCUB_REGION5_OFFSET_BASE_IDX                                                                2
794 #define mmDMCUB_REGION5_OFFSET_HIGH                                                                    0x0199
795 #define mmDMCUB_REGION5_OFFSET_HIGH_BASE_IDX                                                           2
796 #define mmDMCUB_REGION6_OFFSET                                                                         0x019a
797 #define mmDMCUB_REGION6_OFFSET_BASE_IDX                                                                2
798 #define mmDMCUB_REGION6_OFFSET_HIGH                                                                    0x019b
799 #define mmDMCUB_REGION6_OFFSET_HIGH_BASE_IDX                                                           2
800 #define mmDMCUB_REGION7_OFFSET                                                                         0x019c
801 #define mmDMCUB_REGION7_OFFSET_BASE_IDX                                                                2
802 #define mmDMCUB_REGION7_OFFSET_HIGH                                                                    0x019d
803 #define mmDMCUB_REGION7_OFFSET_HIGH_BASE_IDX                                                           2
804 #define mmDMCUB_REGION0_TOP_ADDRESS                                                                    0x019e
805 #define mmDMCUB_REGION0_TOP_ADDRESS_BASE_IDX                                                           2
806 #define mmDMCUB_REGION1_TOP_ADDRESS                                                                    0x019f
807 #define mmDMCUB_REGION1_TOP_ADDRESS_BASE_IDX                                                           2
808 #define mmDMCUB_REGION2_TOP_ADDRESS                                                                    0x01a0
809 #define mmDMCUB_REGION2_TOP_ADDRESS_BASE_IDX                                                           2
810 #define mmDMCUB_REGION4_TOP_ADDRESS                                                                    0x01a1
811 #define mmDMCUB_REGION4_TOP_ADDRESS_BASE_IDX                                                           2
812 #define mmDMCUB_REGION5_TOP_ADDRESS                                                                    0x01a2
813 #define mmDMCUB_REGION5_TOP_ADDRESS_BASE_IDX                                                           2
814 #define mmDMCUB_REGION6_TOP_ADDRESS                                                                    0x01a3
815 #define mmDMCUB_REGION6_TOP_ADDRESS_BASE_IDX                                                           2
816 #define mmDMCUB_REGION7_TOP_ADDRESS                                                                    0x01a4
817 #define mmDMCUB_REGION7_TOP_ADDRESS_BASE_IDX                                                           2
818 #define mmDMCUB_REGION3_CW0_BASE_ADDRESS                                                               0x01a5
819 #define mmDMCUB_REGION3_CW0_BASE_ADDRESS_BASE_IDX                                                      2
820 #define mmDMCUB_REGION3_CW1_BASE_ADDRESS                                                               0x01a6
821 #define mmDMCUB_REGION3_CW1_BASE_ADDRESS_BASE_IDX                                                      2
822 #define mmDMCUB_REGION3_CW2_BASE_ADDRESS                                                               0x01a7
823 #define mmDMCUB_REGION3_CW2_BASE_ADDRESS_BASE_IDX                                                      2
824 #define mmDMCUB_REGION3_CW3_BASE_ADDRESS                                                               0x01a8
825 #define mmDMCUB_REGION3_CW3_BASE_ADDRESS_BASE_IDX                                                      2
826 #define mmDMCUB_REGION3_CW4_BASE_ADDRESS                                                               0x01a9
827 #define mmDMCUB_REGION3_CW4_BASE_ADDRESS_BASE_IDX                                                      2
828 #define mmDMCUB_REGION3_CW5_BASE_ADDRESS                                                               0x01aa
829 #define mmDMCUB_REGION3_CW5_BASE_ADDRESS_BASE_IDX                                                      2
830 #define mmDMCUB_REGION3_CW6_BASE_ADDRESS                                                               0x01ab
831 #define mmDMCUB_REGION3_CW6_BASE_ADDRESS_BASE_IDX                                                      2
832 #define mmDMCUB_REGION3_CW7_BASE_ADDRESS                                                               0x01ac
833 #define mmDMCUB_REGION3_CW7_BASE_ADDRESS_BASE_IDX                                                      2
834 #define mmDMCUB_REGION3_CW0_TOP_ADDRESS                                                                0x01ad
835 #define mmDMCUB_REGION3_CW0_TOP_ADDRESS_BASE_IDX                                                       2
836 #define mmDMCUB_REGION3_CW1_TOP_ADDRESS                                                                0x01ae
837 #define mmDMCUB_REGION3_CW1_TOP_ADDRESS_BASE_IDX                                                       2
838 #define mmDMCUB_REGION3_CW2_TOP_ADDRESS                                                                0x01af
839 #define mmDMCUB_REGION3_CW2_TOP_ADDRESS_BASE_IDX                                                       2
840 #define mmDMCUB_REGION3_CW3_TOP_ADDRESS                                                                0x01b0
841 #define mmDMCUB_REGION3_CW3_TOP_ADDRESS_BASE_IDX                                                       2
842 #define mmDMCUB_REGION3_CW4_TOP_ADDRESS                                                                0x01b1
843 #define mmDMCUB_REGION3_CW4_TOP_ADDRESS_BASE_IDX                                                       2
844 #define mmDMCUB_REGION3_CW5_TOP_ADDRESS                                                                0x01b2
845 #define mmDMCUB_REGION3_CW5_TOP_ADDRESS_BASE_IDX                                                       2
846 #define mmDMCUB_REGION3_CW6_TOP_ADDRESS                                                                0x01b3
847 #define mmDMCUB_REGION3_CW6_TOP_ADDRESS_BASE_IDX                                                       2
848 #define mmDMCUB_REGION3_CW7_TOP_ADDRESS                                                                0x01b4
849 #define mmDMCUB_REGION3_CW7_TOP_ADDRESS_BASE_IDX                                                       2
850 #define mmDMCUB_REGION3_CW0_OFFSET                                                                     0x01b5
851 #define mmDMCUB_REGION3_CW0_OFFSET_BASE_IDX                                                            2
852 #define mmDMCUB_REGION3_CW0_OFFSET_HIGH                                                                0x01b6
853 #define mmDMCUB_REGION3_CW0_OFFSET_HIGH_BASE_IDX                                                       2
854 #define mmDMCUB_REGION3_CW1_OFFSET                                                                     0x01b7
855 #define mmDMCUB_REGION3_CW1_OFFSET_BASE_IDX                                                            2
856 #define mmDMCUB_REGION3_CW1_OFFSET_HIGH                                                                0x01b8
857 #define mmDMCUB_REGION3_CW1_OFFSET_HIGH_BASE_IDX                                                       2
858 #define mmDMCUB_REGION3_CW2_OFFSET                                                                     0x01b9
859 #define mmDMCUB_REGION3_CW2_OFFSET_BASE_IDX                                                            2
860 #define mmDMCUB_REGION3_CW2_OFFSET_HIGH                                                                0x01ba
861 #define mmDMCUB_REGION3_CW2_OFFSET_HIGH_BASE_IDX                                                       2
862 #define mmDMCUB_REGION3_CW3_OFFSET                                                                     0x01bb
863 #define mmDMCUB_REGION3_CW3_OFFSET_BASE_IDX                                                            2
864 #define mmDMCUB_REGION3_CW3_OFFSET_HIGH                                                                0x01bc
865 #define mmDMCUB_REGION3_CW3_OFFSET_HIGH_BASE_IDX                                                       2
866 #define mmDMCUB_REGION3_CW4_OFFSET                                                                     0x01bd
867 #define mmDMCUB_REGION3_CW4_OFFSET_BASE_IDX                                                            2
868 #define mmDMCUB_REGION3_CW4_OFFSET_HIGH                                                                0x01be
869 #define mmDMCUB_REGION3_CW4_OFFSET_HIGH_BASE_IDX                                                       2
870 #define mmDMCUB_REGION3_CW5_OFFSET                                                                     0x01bf
871 #define mmDMCUB_REGION3_CW5_OFFSET_BASE_IDX                                                            2
872 #define mmDMCUB_REGION3_CW5_OFFSET_HIGH                                                                0x01c0
873 #define mmDMCUB_REGION3_CW5_OFFSET_HIGH_BASE_IDX                                                       2
874 #define mmDMCUB_REGION3_CW6_OFFSET                                                                     0x01c1
875 #define mmDMCUB_REGION3_CW6_OFFSET_BASE_IDX                                                            2
876 #define mmDMCUB_REGION3_CW6_OFFSET_HIGH                                                                0x01c2
877 #define mmDMCUB_REGION3_CW6_OFFSET_HIGH_BASE_IDX                                                       2
878 #define mmDMCUB_REGION3_CW7_OFFSET                                                                     0x01c3
879 #define mmDMCUB_REGION3_CW7_OFFSET_BASE_IDX                                                            2
880 #define mmDMCUB_REGION3_CW7_OFFSET_HIGH                                                                0x01c4
881 #define mmDMCUB_REGION3_CW7_OFFSET_HIGH_BASE_IDX                                                       2
882 #define mmDMCUB_INTERRUPT_ENABLE                                                                       0x01c5
883 #define mmDMCUB_INTERRUPT_ENABLE_BASE_IDX                                                              2
884 #define mmDMCUB_INTERRUPT_ACK                                                                          0x01c6
885 #define mmDMCUB_INTERRUPT_ACK_BASE_IDX                                                                 2
886 #define mmDMCUB_INTERRUPT_STATUS                                                                       0x01c7
887 #define mmDMCUB_INTERRUPT_STATUS_BASE_IDX                                                              2
888 #define mmDMCUB_INTERRUPT_TYPE                                                                         0x01c8
889 #define mmDMCUB_INTERRUPT_TYPE_BASE_IDX                                                                2
890 #define mmDMCUB_EXT_INTERRUPT_STATUS                                                                   0x01c9
891 #define mmDMCUB_EXT_INTERRUPT_STATUS_BASE_IDX                                                          2
892 #define mmDMCUB_EXT_INTERRUPT_CTXID                                                                    0x01ca
893 #define mmDMCUB_EXT_INTERRUPT_CTXID_BASE_IDX                                                           2
894 #define mmDMCUB_EXT_INTERRUPT_ACK                                                                      0x01cb
895 #define mmDMCUB_EXT_INTERRUPT_ACK_BASE_IDX                                                             2
896 #define mmDMCUB_INST_FETCH_FAULT_ADDR                                                                  0x01cc
897 #define mmDMCUB_INST_FETCH_FAULT_ADDR_BASE_IDX                                                         2
898 #define mmDMCUB_DATA_WRITE_FAULT_ADDR                                                                  0x01cd
899 #define mmDMCUB_DATA_WRITE_FAULT_ADDR_BASE_IDX                                                         2
900 #define mmDMCUB_SEC_CNTL                                                                               0x01ce
901 #define mmDMCUB_SEC_CNTL_BASE_IDX                                                                      2
902 #define mmDMCUB_MEM_CNTL                                                                               0x01cf
903 #define mmDMCUB_MEM_CNTL_BASE_IDX                                                                      2
904 #define mmDMCUB_INBOX0_BASE_ADDRESS                                                                    0x01d0
905 #define mmDMCUB_INBOX0_BASE_ADDRESS_BASE_IDX                                                           2
906 #define mmDMCUB_INBOX0_SIZE                                                                            0x01d1
907 #define mmDMCUB_INBOX0_SIZE_BASE_IDX                                                                   2
908 #define mmDMCUB_INBOX0_WPTR                                                                            0x01d2
909 #define mmDMCUB_INBOX0_WPTR_BASE_IDX                                                                   2
910 #define mmDMCUB_INBOX0_RPTR                                                                            0x01d3
911 #define mmDMCUB_INBOX0_RPTR_BASE_IDX                                                                   2
912 #define mmDMCUB_INBOX1_BASE_ADDRESS                                                                    0x01d4
913 #define mmDMCUB_INBOX1_BASE_ADDRESS_BASE_IDX                                                           2
914 #define mmDMCUB_INBOX1_SIZE                                                                            0x01d5
915 #define mmDMCUB_INBOX1_SIZE_BASE_IDX                                                                   2
916 #define mmDMCUB_INBOX1_WPTR                                                                            0x01d6
917 #define mmDMCUB_INBOX1_WPTR_BASE_IDX                                                                   2
918 #define mmDMCUB_INBOX1_RPTR                                                                            0x01d7
919 #define mmDMCUB_INBOX1_RPTR_BASE_IDX                                                                   2
920 #define mmDMCUB_OUTBOX0_BASE_ADDRESS                                                                   0x01d8
921 #define mmDMCUB_OUTBOX0_BASE_ADDRESS_BASE_IDX                                                          2
922 #define mmDMCUB_OUTBOX0_SIZE                                                                           0x01d9
923 #define mmDMCUB_OUTBOX0_SIZE_BASE_IDX                                                                  2
924 #define mmDMCUB_OUTBOX0_WPTR                                                                           0x01da
925 #define mmDMCUB_OUTBOX0_WPTR_BASE_IDX                                                                  2
926 #define mmDMCUB_OUTBOX0_RPTR                                                                           0x01db
927 #define mmDMCUB_OUTBOX0_RPTR_BASE_IDX                                                                  2
928 #define mmDMCUB_OUTBOX1_BASE_ADDRESS                                                                   0x01dc
929 #define mmDMCUB_OUTBOX1_BASE_ADDRESS_BASE_IDX                                                          2
930 #define mmDMCUB_OUTBOX1_SIZE                                                                           0x01dd
931 #define mmDMCUB_OUTBOX1_SIZE_BASE_IDX                                                                  2
932 #define mmDMCUB_OUTBOX1_WPTR                                                                           0x01de
933 #define mmDMCUB_OUTBOX1_WPTR_BASE_IDX                                                                  2
934 #define mmDMCUB_OUTBOX1_RPTR                                                                           0x01df
935 #define mmDMCUB_OUTBOX1_RPTR_BASE_IDX                                                                  2
936 #define mmDMCUB_TIMER_TRIGGER0                                                                         0x01e0
937 #define mmDMCUB_TIMER_TRIGGER0_BASE_IDX                                                                2
938 #define mmDMCUB_TIMER_TRIGGER1                                                                         0x01e1
939 #define mmDMCUB_TIMER_TRIGGER1_BASE_IDX                                                                2
940 #define mmDMCUB_TIMER_WINDOW                                                                           0x01e2
941 #define mmDMCUB_TIMER_WINDOW_BASE_IDX                                                                  2
942 #define mmDMCUB_SCRATCH0                                                                               0x01e3
943 #define mmDMCUB_SCRATCH0_BASE_IDX                                                                      2
944 #define mmDMCUB_SCRATCH1                                                                               0x01e4
945 #define mmDMCUB_SCRATCH1_BASE_IDX                                                                      2
946 #define mmDMCUB_SCRATCH2                                                                               0x01e5
947 #define mmDMCUB_SCRATCH2_BASE_IDX                                                                      2
948 #define mmDMCUB_SCRATCH3                                                                               0x01e6
949 #define mmDMCUB_SCRATCH3_BASE_IDX                                                                      2
950 #define mmDMCUB_SCRATCH4                                                                               0x01e7
951 #define mmDMCUB_SCRATCH4_BASE_IDX                                                                      2
952 #define mmDMCUB_SCRATCH5                                                                               0x01e8
953 #define mmDMCUB_SCRATCH5_BASE_IDX                                                                      2
954 #define mmDMCUB_SCRATCH6                                                                               0x01e9
955 #define mmDMCUB_SCRATCH6_BASE_IDX                                                                      2
956 #define mmDMCUB_SCRATCH7                                                                               0x01ea
957 #define mmDMCUB_SCRATCH7_BASE_IDX                                                                      2
958 #define mmDMCUB_SCRATCH8                                                                               0x01eb
959 #define mmDMCUB_SCRATCH8_BASE_IDX                                                                      2
960 #define mmDMCUB_SCRATCH9                                                                               0x01ec
961 #define mmDMCUB_SCRATCH9_BASE_IDX                                                                      2
962 #define mmDMCUB_SCRATCH10                                                                              0x01ed
963 #define mmDMCUB_SCRATCH10_BASE_IDX                                                                     2
964 #define mmDMCUB_SCRATCH11                                                                              0x01ee
965 #define mmDMCUB_SCRATCH11_BASE_IDX                                                                     2
966 #define mmDMCUB_SCRATCH12                                                                              0x01ef
967 #define mmDMCUB_SCRATCH12_BASE_IDX                                                                     2
968 #define mmDMCUB_SCRATCH13                                                                              0x01f0
969 #define mmDMCUB_SCRATCH13_BASE_IDX                                                                     2
970 #define mmDMCUB_SCRATCH14                                                                              0x01f1
971 #define mmDMCUB_SCRATCH14_BASE_IDX                                                                     2
972 #define mmDMCUB_SCRATCH15                                                                              0x01f2
973 #define mmDMCUB_SCRATCH15_BASE_IDX                                                                     2
974 #define mmDMCUB_CNTL                                                                                   0x01f6
975 #define mmDMCUB_CNTL_BASE_IDX                                                                          2
976 #define mmDMCUB_GPINT_DATAIN0                                                                          0x01f7
977 #define mmDMCUB_GPINT_DATAIN0_BASE_IDX                                                                 2
978 #define mmDMCUB_GPINT_DATAIN1                                                                          0x01f8
979 #define mmDMCUB_GPINT_DATAIN1_BASE_IDX                                                                 2
980 #define mmDMCUB_GPINT_DATAOUT                                                                          0x01f9
981 #define mmDMCUB_GPINT_DATAOUT_BASE_IDX                                                                 2
982 #define mmDMCUB_UNDEFINED_ADDRESS_FAULT_ADDR                                                           0x01fa
983 #define mmDMCUB_UNDEFINED_ADDRESS_FAULT_ADDR_BASE_IDX                                                  2
984 #define mmDMCUB_LS_WAKE_INT_ENABLE                                                                     0x01fb
985 #define mmDMCUB_LS_WAKE_INT_ENABLE_BASE_IDX                                                            2
986 #define mmDMCUB_MEM_PWR_CNTL                                                                           0x01fc
987 #define mmDMCUB_MEM_PWR_CNTL_BASE_IDX                                                                  2
988 #define mmDMCUB_TIMER_CURRENT                                                                          0x01fd
989 #define mmDMCUB_TIMER_CURRENT_BASE_IDX                                                                 2
990 #define mmDMCUB_PROC_ID                                                                                0x01ff
991 #define mmDMCUB_PROC_ID_BASE_IDX                                                                       2
992 
993 
994 // addressBlock: dce_dc_mmhubbub_mcif_wb0_dispdec
995 // base address: 0x0
996 #define mmMCIF_WB_BUFMGR_SW_CONTROL                                                                    0x0272
997 #define mmMCIF_WB_BUFMGR_SW_CONTROL_BASE_IDX                                                           2
998 #define mmMCIF_WB_BUFMGR_STATUS                                                                        0x0274
999 #define mmMCIF_WB_BUFMGR_STATUS_BASE_IDX                                                               2
1000 #define mmMCIF_WB_BUF_PITCH                                                                            0x0275
1001 #define mmMCIF_WB_BUF_PITCH_BASE_IDX                                                                   2
1002 #define mmMCIF_WB_BUF_1_STATUS                                                                         0x0276
1003 #define mmMCIF_WB_BUF_1_STATUS_BASE_IDX                                                                2
1004 #define mmMCIF_WB_BUF_1_STATUS2                                                                        0x0277
1005 #define mmMCIF_WB_BUF_1_STATUS2_BASE_IDX                                                               2
1006 #define mmMCIF_WB_BUF_2_STATUS                                                                         0x0278
1007 #define mmMCIF_WB_BUF_2_STATUS_BASE_IDX                                                                2
1008 #define mmMCIF_WB_BUF_2_STATUS2                                                                        0x0279
1009 #define mmMCIF_WB_BUF_2_STATUS2_BASE_IDX                                                               2
1010 #define mmMCIF_WB_BUF_3_STATUS                                                                         0x027a
1011 #define mmMCIF_WB_BUF_3_STATUS_BASE_IDX                                                                2
1012 #define mmMCIF_WB_BUF_3_STATUS2                                                                        0x027b
1013 #define mmMCIF_WB_BUF_3_STATUS2_BASE_IDX                                                               2
1014 #define mmMCIF_WB_BUF_4_STATUS                                                                         0x027c
1015 #define mmMCIF_WB_BUF_4_STATUS_BASE_IDX                                                                2
1016 #define mmMCIF_WB_BUF_4_STATUS2                                                                        0x027d
1017 #define mmMCIF_WB_BUF_4_STATUS2_BASE_IDX                                                               2
1018 #define mmMCIF_WB_ARBITRATION_CONTROL                                                                  0x027e
1019 #define mmMCIF_WB_ARBITRATION_CONTROL_BASE_IDX                                                         2
1020 #define mmMCIF_WB_SCLK_CHANGE                                                                          0x027f
1021 #define mmMCIF_WB_SCLK_CHANGE_BASE_IDX                                                                 2
1022 #define mmMCIF_WB_BUF_1_ADDR_Y                                                                         0x0282
1023 #define mmMCIF_WB_BUF_1_ADDR_Y_BASE_IDX                                                                2
1024 #define mmMCIF_WB_BUF_1_ADDR_C                                                                         0x0284
1025 #define mmMCIF_WB_BUF_1_ADDR_C_BASE_IDX                                                                2
1026 #define mmMCIF_WB_BUF_2_ADDR_Y                                                                         0x0286
1027 #define mmMCIF_WB_BUF_2_ADDR_Y_BASE_IDX                                                                2
1028 #define mmMCIF_WB_BUF_2_ADDR_C                                                                         0x0288
1029 #define mmMCIF_WB_BUF_2_ADDR_C_BASE_IDX                                                                2
1030 #define mmMCIF_WB_BUF_3_ADDR_Y                                                                         0x028a
1031 #define mmMCIF_WB_BUF_3_ADDR_Y_BASE_IDX                                                                2
1032 #define mmMCIF_WB_BUF_3_ADDR_C                                                                         0x028c
1033 #define mmMCIF_WB_BUF_3_ADDR_C_BASE_IDX                                                                2
1034 #define mmMCIF_WB_BUF_4_ADDR_Y                                                                         0x028e
1035 #define mmMCIF_WB_BUF_4_ADDR_Y_BASE_IDX                                                                2
1036 #define mmMCIF_WB_BUF_4_ADDR_C                                                                         0x0290
1037 #define mmMCIF_WB_BUF_4_ADDR_C_BASE_IDX                                                                2
1038 #define mmMCIF_WB_BUFMGR_VCE_CONTROL                                                                   0x0292
1039 #define mmMCIF_WB_BUFMGR_VCE_CONTROL_BASE_IDX                                                          2
1040 #define mmMCIF_WB_NB_PSTATE_CONTROL                                                                    0x0293
1041 #define mmMCIF_WB_NB_PSTATE_CONTROL_BASE_IDX                                                           2
1042 #define mmMCIF_WB_CLOCK_GATER_CONTROL                                                                  0x0294
1043 #define mmMCIF_WB_CLOCK_GATER_CONTROL_BASE_IDX                                                         2
1044 #define mmMCIF_WB_SELF_REFRESH_CONTROL                                                                 0x0296
1045 #define mmMCIF_WB_SELF_REFRESH_CONTROL_BASE_IDX                                                        2
1046 #define mmMULTI_LEVEL_QOS_CTRL                                                                         0x0297
1047 #define mmMULTI_LEVEL_QOS_CTRL_BASE_IDX                                                                2
1048 #define mmMCIF_WB_BUF_LUMA_SIZE                                                                        0x0299
1049 #define mmMCIF_WB_BUF_LUMA_SIZE_BASE_IDX                                                               2
1050 #define mmMCIF_WB_BUF_CHROMA_SIZE                                                                      0x029a
1051 #define mmMCIF_WB_BUF_CHROMA_SIZE_BASE_IDX                                                             2
1052 #define mmMCIF_WB_BUF_1_ADDR_Y_HIGH                                                                    0x029b
1053 #define mmMCIF_WB_BUF_1_ADDR_Y_HIGH_BASE_IDX                                                           2
1054 #define mmMCIF_WB_BUF_1_ADDR_C_HIGH                                                                    0x029c
1055 #define mmMCIF_WB_BUF_1_ADDR_C_HIGH_BASE_IDX                                                           2
1056 #define mmMCIF_WB_BUF_2_ADDR_Y_HIGH                                                                    0x029d
1057 #define mmMCIF_WB_BUF_2_ADDR_Y_HIGH_BASE_IDX                                                           2
1058 #define mmMCIF_WB_BUF_2_ADDR_C_HIGH                                                                    0x029e
1059 #define mmMCIF_WB_BUF_2_ADDR_C_HIGH_BASE_IDX                                                           2
1060 #define mmMCIF_WB_BUF_3_ADDR_Y_HIGH                                                                    0x029f
1061 #define mmMCIF_WB_BUF_3_ADDR_Y_HIGH_BASE_IDX                                                           2
1062 #define mmMCIF_WB_BUF_3_ADDR_C_HIGH                                                                    0x02a0
1063 #define mmMCIF_WB_BUF_3_ADDR_C_HIGH_BASE_IDX                                                           2
1064 #define mmMCIF_WB_BUF_4_ADDR_Y_HIGH                                                                    0x02a1
1065 #define mmMCIF_WB_BUF_4_ADDR_Y_HIGH_BASE_IDX                                                           2
1066 #define mmMCIF_WB_BUF_4_ADDR_C_HIGH                                                                    0x02a2
1067 #define mmMCIF_WB_BUF_4_ADDR_C_HIGH_BASE_IDX                                                           2
1068 #define mmMCIF_WB_BUF_1_RESOLUTION                                                                     0x02a3
1069 #define mmMCIF_WB_BUF_1_RESOLUTION_BASE_IDX                                                            2
1070 #define mmMCIF_WB_BUF_2_RESOLUTION                                                                     0x02a4
1071 #define mmMCIF_WB_BUF_2_RESOLUTION_BASE_IDX                                                            2
1072 #define mmMCIF_WB_BUF_3_RESOLUTION                                                                     0x02a5
1073 #define mmMCIF_WB_BUF_3_RESOLUTION_BASE_IDX                                                            2
1074 #define mmMCIF_WB_BUF_4_RESOLUTION                                                                     0x02a6
1075 #define mmMCIF_WB_BUF_4_RESOLUTION_BASE_IDX                                                            2
1076 #define mmMCIF_WB_DRAM_SPEED_CHANGE_DURATION_VBI                                                       0x02a7
1077 #define mmMCIF_WB_DRAM_SPEED_CHANGE_DURATION_VBI_BASE_IDX                                              2
1078 #define mmMCIF_WB_VMID_CONTROL                                                                         0x02a8
1079 #define mmMCIF_WB_VMID_CONTROL_BASE_IDX                                                                2
1080 #define mmMCIF_WB_MIN_TTO                                                                              0x02a9
1081 #define mmMCIF_WB_MIN_TTO_BASE_IDX                                                                     2
1082 
1083 
1084 // addressBlock: dce_dc_mmhubbub_mmhubbub_dispdec
1085 // base address: 0x0
1086 #define mmMCIF_WB_NB_PSTATE_LATENCY_WATERMARK                                                          0x02aa
1087 #define mmMCIF_WB_NB_PSTATE_LATENCY_WATERMARK_BASE_IDX                                                 2
1088 #define mmMCIF_WB_WATERMARK                                                                            0x02ab
1089 #define mmMCIF_WB_WATERMARK_BASE_IDX                                                                   2
1090 #define mmMMHUBBUB_WARMUP_CONFIG                                                                       0x02ac
1091 #define mmMMHUBBUB_WARMUP_CONFIG_BASE_IDX                                                              2
1092 #define mmMMHUBBUB_WARMUP_CONTROL_STATUS                                                               0x02ad
1093 #define mmMMHUBBUB_WARMUP_CONTROL_STATUS_BASE_IDX                                                      2
1094 #define mmMMHUBBUB_WARMUP_BASE_ADDR_LOW                                                                0x02ae
1095 #define mmMMHUBBUB_WARMUP_BASE_ADDR_LOW_BASE_IDX                                                       2
1096 #define mmMMHUBBUB_WARMUP_BASE_ADDR_HIGH                                                               0x02af
1097 #define mmMMHUBBUB_WARMUP_BASE_ADDR_HIGH_BASE_IDX                                                      2
1098 #define mmMMHUBBUB_WARMUP_ADDR_REGION                                                                  0x02b0
1099 #define mmMMHUBBUB_WARMUP_ADDR_REGION_BASE_IDX                                                         2
1100 #define mmMMHUBBUB_MIN_TTO                                                                             0x02b1
1101 #define mmMMHUBBUB_MIN_TTO_BASE_IDX                                                                    2
1102 #define mmWBIF_SMU_WM_CONTROL                                                                          0x0333
1103 #define mmWBIF_SMU_WM_CONTROL_BASE_IDX                                                                 2
1104 #define mmWBIF0_MISC_CTRL                                                                              0x0334
1105 #define mmWBIF0_MISC_CTRL_BASE_IDX                                                                     2
1106 #define mmWBIF0_PHASE0_OUTSTANDING_COUNTER                                                             0x0335
1107 #define mmWBIF0_PHASE0_OUTSTANDING_COUNTER_BASE_IDX                                                    2
1108 #define mmWBIF0_PHASE1_OUTSTANDING_COUNTER                                                             0x0336
1109 #define mmWBIF0_PHASE1_OUTSTANDING_COUNTER_BASE_IDX                                                    2
1110 #define mmVGA_SRC_SPLIT_CNTL                                                                           0x033d
1111 #define mmVGA_SRC_SPLIT_CNTL_BASE_IDX                                                                  2
1112 #define mmMMHUBBUB_MEM_PWR_STATUS                                                                      0x033e
1113 #define mmMMHUBBUB_MEM_PWR_STATUS_BASE_IDX                                                             2
1114 #define mmMMHUBBUB_MEM_PWR_CNTL                                                                        0x033f
1115 #define mmMMHUBBUB_MEM_PWR_CNTL_BASE_IDX                                                               2
1116 #define mmMMHUBBUB_CLOCK_CNTL                                                                          0x0340
1117 #define mmMMHUBBUB_CLOCK_CNTL_BASE_IDX                                                                 2
1118 #define mmMMHUBBUB_SOFT_RESET                                                                          0x0341
1119 #define mmMMHUBBUB_SOFT_RESET_BASE_IDX                                                                 2
1120 #define mmDMU_IF_ERR_STATUS                                                                            0x0345
1121 #define mmDMU_IF_ERR_STATUS_BASE_IDX                                                                   2
1122 #define mmMMHUBBUB_CLIENT_UNIT_ID                                                                      0x0346
1123 #define mmMMHUBBUB_CLIENT_UNIT_ID_BASE_IDX                                                             2
1124 #define mmMMHUBBUB_WARMUP_VMID_CONTROL                                                                 0x0348
1125 #define mmMMHUBBUB_WARMUP_VMID_CONTROL_BASE_IDX                                                        2
1126 
1127 
1128 // addressBlock: dce_dc_mmhubbub_vgaif_dispdec
1129 // base address: 0x0
1130 #define mmMCIF_CONTROL                                                                                 0x034a
1131 #define mmMCIF_CONTROL_BASE_IDX                                                                        2
1132 #define mmMCIF_WRITE_COMBINE_CONTROL                                                                   0x034b
1133 #define mmMCIF_WRITE_COMBINE_CONTROL_BASE_IDX                                                          2
1134 #define mmMCIF_PHASE0_OUTSTANDING_COUNTER                                                              0x034e
1135 #define mmMCIF_PHASE0_OUTSTANDING_COUNTER_BASE_IDX                                                     2
1136 #define mmMCIF_PHASE1_OUTSTANDING_COUNTER                                                              0x034f
1137 #define mmMCIF_PHASE1_OUTSTANDING_COUNTER_BASE_IDX                                                     2
1138 #define mmMCIF_PHASE2_OUTSTANDING_COUNTER                                                              0x0350
1139 #define mmMCIF_PHASE2_OUTSTANDING_COUNTER_BASE_IDX                                                     2
1140 
1141 
1142 // addressBlock: dce_dc_mmhubbub_mmhubbub_dcperfmon_dc_perfmon_dispdec
1143 // base address: 0xd48
1144 #define mmDC_PERFMON3_PERFCOUNTER_CNTL                                                                 0x0352
1145 #define mmDC_PERFMON3_PERFCOUNTER_CNTL_BASE_IDX                                                        2
1146 #define mmDC_PERFMON3_PERFCOUNTER_CNTL2                                                                0x0353
1147 #define mmDC_PERFMON3_PERFCOUNTER_CNTL2_BASE_IDX                                                       2
1148 #define mmDC_PERFMON3_PERFCOUNTER_STATE                                                                0x0354
1149 #define mmDC_PERFMON3_PERFCOUNTER_STATE_BASE_IDX                                                       2
1150 #define mmDC_PERFMON3_PERFMON_CNTL                                                                     0x0355
1151 #define mmDC_PERFMON3_PERFMON_CNTL_BASE_IDX                                                            2
1152 #define mmDC_PERFMON3_PERFMON_CNTL2                                                                    0x0356
1153 #define mmDC_PERFMON3_PERFMON_CNTL2_BASE_IDX                                                           2
1154 #define mmDC_PERFMON3_PERFMON_CVALUE_INT_MISC                                                          0x0357
1155 #define mmDC_PERFMON3_PERFMON_CVALUE_INT_MISC_BASE_IDX                                                 2
1156 #define mmDC_PERFMON3_PERFMON_CVALUE_LOW                                                               0x0358
1157 #define mmDC_PERFMON3_PERFMON_CVALUE_LOW_BASE_IDX                                                      2
1158 #define mmDC_PERFMON3_PERFMON_HI                                                                       0x0359
1159 #define mmDC_PERFMON3_PERFMON_HI_BASE_IDX                                                              2
1160 #define mmDC_PERFMON3_PERFMON_LOW                                                                      0x035a
1161 #define mmDC_PERFMON3_PERFMON_LOW_BASE_IDX                                                             2
1162 
1163 
1164 // addressBlock: dce_dc_hda_azf0stream0_dispdec
1165 // base address: 0x0
1166 #define mmAZF0STREAM0_AZALIA_STREAM_INDEX                                                              0x035e
1167 #define mmAZF0STREAM0_AZALIA_STREAM_INDEX_BASE_IDX                                                     2
1168 #define mmAZF0STREAM0_AZALIA_STREAM_DATA                                                               0x035f
1169 #define mmAZF0STREAM0_AZALIA_STREAM_DATA_BASE_IDX                                                      2
1170 
1171 
1172 // addressBlock: dce_dc_hda_azf0stream1_dispdec
1173 // base address: 0x8
1174 #define mmAZF0STREAM1_AZALIA_STREAM_INDEX                                                              0x0360
1175 #define mmAZF0STREAM1_AZALIA_STREAM_INDEX_BASE_IDX                                                     2
1176 #define mmAZF0STREAM1_AZALIA_STREAM_DATA                                                               0x0361
1177 #define mmAZF0STREAM1_AZALIA_STREAM_DATA_BASE_IDX                                                      2
1178 
1179 
1180 // addressBlock: dce_dc_hda_azf0stream2_dispdec
1181 // base address: 0x10
1182 #define mmAZF0STREAM2_AZALIA_STREAM_INDEX                                                              0x0362
1183 #define mmAZF0STREAM2_AZALIA_STREAM_INDEX_BASE_IDX                                                     2
1184 #define mmAZF0STREAM2_AZALIA_STREAM_DATA                                                               0x0363
1185 #define mmAZF0STREAM2_AZALIA_STREAM_DATA_BASE_IDX                                                      2
1186 
1187 
1188 // addressBlock: dce_dc_hda_azf0stream3_dispdec
1189 // base address: 0x18
1190 #define mmAZF0STREAM3_AZALIA_STREAM_INDEX                                                              0x0364
1191 #define mmAZF0STREAM3_AZALIA_STREAM_INDEX_BASE_IDX                                                     2
1192 #define mmAZF0STREAM3_AZALIA_STREAM_DATA                                                               0x0365
1193 #define mmAZF0STREAM3_AZALIA_STREAM_DATA_BASE_IDX                                                      2
1194 
1195 
1196 // addressBlock: dce_dc_hda_azf0stream4_dispdec
1197 // base address: 0x20
1198 #define mmAZF0STREAM4_AZALIA_STREAM_INDEX                                                              0x0366
1199 #define mmAZF0STREAM4_AZALIA_STREAM_INDEX_BASE_IDX                                                     2
1200 #define mmAZF0STREAM4_AZALIA_STREAM_DATA                                                               0x0367
1201 #define mmAZF0STREAM4_AZALIA_STREAM_DATA_BASE_IDX                                                      2
1202 
1203 
1204 // addressBlock: dce_dc_hda_azf0stream5_dispdec
1205 // base address: 0x28
1206 #define mmAZF0STREAM5_AZALIA_STREAM_INDEX                                                              0x0368
1207 #define mmAZF0STREAM5_AZALIA_STREAM_INDEX_BASE_IDX                                                     2
1208 #define mmAZF0STREAM5_AZALIA_STREAM_DATA                                                               0x0369
1209 #define mmAZF0STREAM5_AZALIA_STREAM_DATA_BASE_IDX                                                      2
1210 
1211 
1212 // addressBlock: dce_dc_hda_azf0stream6_dispdec
1213 // base address: 0x30
1214 #define mmAZF0STREAM6_AZALIA_STREAM_INDEX                                                              0x036a
1215 #define mmAZF0STREAM6_AZALIA_STREAM_INDEX_BASE_IDX                                                     2
1216 #define mmAZF0STREAM6_AZALIA_STREAM_DATA                                                               0x036b
1217 #define mmAZF0STREAM6_AZALIA_STREAM_DATA_BASE_IDX                                                      2
1218 
1219 
1220 // addressBlock: dce_dc_hda_azf0stream7_dispdec
1221 // base address: 0x38
1222 #define mmAZF0STREAM7_AZALIA_STREAM_INDEX                                                              0x036c
1223 #define mmAZF0STREAM7_AZALIA_STREAM_INDEX_BASE_IDX                                                     2
1224 #define mmAZF0STREAM7_AZALIA_STREAM_DATA                                                               0x036d
1225 #define mmAZF0STREAM7_AZALIA_STREAM_DATA_BASE_IDX                                                      2
1226 
1227 
1228 // addressBlock: dce_dc_hda_az_misc_dispdec
1229 // base address: 0x0
1230 #define mmAZ_CLOCK_CNTL                                                                                0x0372
1231 #define mmAZ_CLOCK_CNTL_BASE_IDX                                                                       2
1232 
1233 
1234 // addressBlock: dce_dc_hda_az_dcperfmon_dc_perfmon_dispdec
1235 // base address: 0xde8
1236 #define mmDC_PERFMON4_PERFCOUNTER_CNTL                                                                 0x037a
1237 #define mmDC_PERFMON4_PERFCOUNTER_CNTL_BASE_IDX                                                        2
1238 #define mmDC_PERFMON4_PERFCOUNTER_CNTL2                                                                0x037b
1239 #define mmDC_PERFMON4_PERFCOUNTER_CNTL2_BASE_IDX                                                       2
1240 #define mmDC_PERFMON4_PERFCOUNTER_STATE                                                                0x037c
1241 #define mmDC_PERFMON4_PERFCOUNTER_STATE_BASE_IDX                                                       2
1242 #define mmDC_PERFMON4_PERFMON_CNTL                                                                     0x037d
1243 #define mmDC_PERFMON4_PERFMON_CNTL_BASE_IDX                                                            2
1244 #define mmDC_PERFMON4_PERFMON_CNTL2                                                                    0x037e
1245 #define mmDC_PERFMON4_PERFMON_CNTL2_BASE_IDX                                                           2
1246 #define mmDC_PERFMON4_PERFMON_CVALUE_INT_MISC                                                          0x037f
1247 #define mmDC_PERFMON4_PERFMON_CVALUE_INT_MISC_BASE_IDX                                                 2
1248 #define mmDC_PERFMON4_PERFMON_CVALUE_LOW                                                               0x0380
1249 #define mmDC_PERFMON4_PERFMON_CVALUE_LOW_BASE_IDX                                                      2
1250 #define mmDC_PERFMON4_PERFMON_HI                                                                       0x0381
1251 #define mmDC_PERFMON4_PERFMON_HI_BASE_IDX                                                              2
1252 #define mmDC_PERFMON4_PERFMON_LOW                                                                      0x0382
1253 #define mmDC_PERFMON4_PERFMON_LOW_BASE_IDX                                                             2
1254 
1255 
1256 // addressBlock: dce_dc_hda_azf0endpoint0_dispdec
1257 // base address: 0x0
1258 #define mmAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX                                                 0x0386
1259 #define mmAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX                                        2
1260 #define mmAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA                                                  0x0387
1261 #define mmAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX                                         2
1262 
1263 
1264 // addressBlock: dce_dc_hda_azf0endpoint1_dispdec
1265 // base address: 0x18
1266 #define mmAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_INDEX                                                 0x038c
1267 #define mmAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX                                        2
1268 #define mmAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_DATA                                                  0x038d
1269 #define mmAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX                                         2
1270 
1271 
1272 // addressBlock: dce_dc_hda_azf0endpoint2_dispdec
1273 // base address: 0x30
1274 #define mmAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_INDEX                                                 0x0392
1275 #define mmAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX                                        2
1276 #define mmAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_DATA                                                  0x0393
1277 #define mmAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX                                         2
1278 
1279 
1280 // addressBlock: dce_dc_hda_azf0endpoint3_dispdec
1281 // base address: 0x48
1282 #define mmAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_INDEX                                                 0x0398
1283 #define mmAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX                                        2
1284 #define mmAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_DATA                                                  0x0399
1285 #define mmAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX                                         2
1286 
1287 
1288 // addressBlock: dce_dc_hda_azf0endpoint4_dispdec
1289 // base address: 0x60
1290 #define mmAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_INDEX                                                 0x039e
1291 #define mmAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX                                        2
1292 #define mmAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_DATA                                                  0x039f
1293 #define mmAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX                                         2
1294 
1295 
1296 // addressBlock: dce_dc_hda_azf0endpoint5_dispdec
1297 // base address: 0x78
1298 #define mmAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_INDEX                                                 0x03a4
1299 #define mmAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX                                        2
1300 #define mmAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_DATA                                                  0x03a5
1301 #define mmAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX                                         2
1302 
1303 
1304 // addressBlock: dce_dc_hda_azf0endpoint6_dispdec
1305 // base address: 0x90
1306 #define mmAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_INDEX                                                 0x03aa
1307 #define mmAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX                                        2
1308 #define mmAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_DATA                                                  0x03ab
1309 #define mmAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX                                         2
1310 
1311 
1312 // addressBlock: dce_dc_hda_azf0endpoint7_dispdec
1313 // base address: 0xa8
1314 #define mmAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_INDEX                                                 0x03b0
1315 #define mmAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX                                        2
1316 #define mmAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_DATA                                                  0x03b1
1317 #define mmAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX                                         2
1318 
1319 
1320 // addressBlock: dce_dc_hda_azf0controller_dispdec
1321 // base address: 0x0
1322 #define mmAZALIA_CONTROLLER_CLOCK_GATING                                                               0x03c2
1323 #define mmAZALIA_CONTROLLER_CLOCK_GATING_BASE_IDX                                                      2
1324 #define mmAZALIA_AUDIO_DTO                                                                             0x03c3
1325 #define mmAZALIA_AUDIO_DTO_BASE_IDX                                                                    2
1326 #define mmAZALIA_AUDIO_DTO_CONTROL                                                                     0x03c4
1327 #define mmAZALIA_AUDIO_DTO_CONTROL_BASE_IDX                                                            2
1328 #define mmAZALIA_SOCCLK_CONTROL                                                                        0x03c5
1329 #define mmAZALIA_SOCCLK_CONTROL_BASE_IDX                                                               2
1330 #define mmAZALIA_UNDERFLOW_FILLER_SAMPLE                                                               0x03c6
1331 #define mmAZALIA_UNDERFLOW_FILLER_SAMPLE_BASE_IDX                                                      2
1332 #define mmAZALIA_DATA_DMA_CONTROL                                                                      0x03c7
1333 #define mmAZALIA_DATA_DMA_CONTROL_BASE_IDX                                                             2
1334 #define mmAZALIA_BDL_DMA_CONTROL                                                                       0x03c8
1335 #define mmAZALIA_BDL_DMA_CONTROL_BASE_IDX                                                              2
1336 #define mmAZALIA_RIRB_AND_DP_CONTROL                                                                   0x03c9
1337 #define mmAZALIA_RIRB_AND_DP_CONTROL_BASE_IDX                                                          2
1338 #define mmAZALIA_CORB_DMA_CONTROL                                                                      0x03ca
1339 #define mmAZALIA_CORB_DMA_CONTROL_BASE_IDX                                                             2
1340 #define mmAZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER                                                 0x03d1
1341 #define mmAZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER_BASE_IDX                                        2
1342 #define mmAZALIA_CYCLIC_BUFFER_SYNC                                                                    0x03d2
1343 #define mmAZALIA_CYCLIC_BUFFER_SYNC_BASE_IDX                                                           2
1344 #define mmAZALIA_GLOBAL_CAPABILITIES                                                                   0x03d3
1345 #define mmAZALIA_GLOBAL_CAPABILITIES_BASE_IDX                                                          2
1346 #define mmAZALIA_OUTPUT_PAYLOAD_CAPABILITY                                                             0x03d4
1347 #define mmAZALIA_OUTPUT_PAYLOAD_CAPABILITY_BASE_IDX                                                    2
1348 #define mmAZALIA_OUTPUT_STREAM_ARBITER_CONTROL                                                         0x03d5
1349 #define mmAZALIA_OUTPUT_STREAM_ARBITER_CONTROL_BASE_IDX                                                2
1350 #define mmAZALIA_INPUT_PAYLOAD_CAPABILITY                                                              0x03d6
1351 #define mmAZALIA_INPUT_PAYLOAD_CAPABILITY_BASE_IDX                                                     2
1352 #define mmAZALIA_INPUT_CRC0_CONTROL0                                                                   0x03d9
1353 #define mmAZALIA_INPUT_CRC0_CONTROL0_BASE_IDX                                                          2
1354 #define mmAZALIA_INPUT_CRC0_CONTROL1                                                                   0x03da
1355 #define mmAZALIA_INPUT_CRC0_CONTROL1_BASE_IDX                                                          2
1356 #define mmAZALIA_INPUT_CRC0_CONTROL2                                                                   0x03db
1357 #define mmAZALIA_INPUT_CRC0_CONTROL2_BASE_IDX                                                          2
1358 #define mmAZALIA_INPUT_CRC0_CONTROL3                                                                   0x03dc
1359 #define mmAZALIA_INPUT_CRC0_CONTROL3_BASE_IDX                                                          2
1360 #define mmAZALIA_INPUT_CRC0_RESULT                                                                     0x03dd
1361 #define mmAZALIA_INPUT_CRC0_RESULT_BASE_IDX                                                            2
1362 #define mmAZALIA_INPUT_CRC1_CONTROL0                                                                   0x03de
1363 #define mmAZALIA_INPUT_CRC1_CONTROL0_BASE_IDX                                                          2
1364 #define mmAZALIA_INPUT_CRC1_CONTROL1                                                                   0x03df
1365 #define mmAZALIA_INPUT_CRC1_CONTROL1_BASE_IDX                                                          2
1366 #define mmAZALIA_INPUT_CRC1_CONTROL2                                                                   0x03e0
1367 #define mmAZALIA_INPUT_CRC1_CONTROL2_BASE_IDX                                                          2
1368 #define mmAZALIA_INPUT_CRC1_CONTROL3                                                                   0x03e1
1369 #define mmAZALIA_INPUT_CRC1_CONTROL3_BASE_IDX                                                          2
1370 #define mmAZALIA_INPUT_CRC1_RESULT                                                                     0x03e2
1371 #define mmAZALIA_INPUT_CRC1_RESULT_BASE_IDX                                                            2
1372 #define mmAZALIA_CRC0_CONTROL0                                                                         0x03e3
1373 #define mmAZALIA_CRC0_CONTROL0_BASE_IDX                                                                2
1374 #define mmAZALIA_CRC0_CONTROL1                                                                         0x03e4
1375 #define mmAZALIA_CRC0_CONTROL1_BASE_IDX                                                                2
1376 #define mmAZALIA_CRC0_CONTROL2                                                                         0x03e5
1377 #define mmAZALIA_CRC0_CONTROL2_BASE_IDX                                                                2
1378 #define mmAZALIA_CRC0_CONTROL3                                                                         0x03e6
1379 #define mmAZALIA_CRC0_CONTROL3_BASE_IDX                                                                2
1380 #define mmAZALIA_CRC0_RESULT                                                                           0x03e7
1381 #define mmAZALIA_CRC0_RESULT_BASE_IDX                                                                  2
1382 #define mmAZALIA_CRC1_CONTROL0                                                                         0x03e8
1383 #define mmAZALIA_CRC1_CONTROL0_BASE_IDX                                                                2
1384 #define mmAZALIA_CRC1_CONTROL1                                                                         0x03e9
1385 #define mmAZALIA_CRC1_CONTROL1_BASE_IDX                                                                2
1386 #define mmAZALIA_CRC1_CONTROL2                                                                         0x03ea
1387 #define mmAZALIA_CRC1_CONTROL2_BASE_IDX                                                                2
1388 #define mmAZALIA_CRC1_CONTROL3                                                                         0x03eb
1389 #define mmAZALIA_CRC1_CONTROL3_BASE_IDX                                                                2
1390 #define mmAZALIA_CRC1_RESULT                                                                           0x03ec
1391 #define mmAZALIA_CRC1_RESULT_BASE_IDX                                                                  2
1392 #define mmAZALIA_MEM_PWR_CTRL                                                                          0x03ee
1393 #define mmAZALIA_MEM_PWR_CTRL_BASE_IDX                                                                 2
1394 #define mmAZALIA_MEM_PWR_STATUS                                                                        0x03ef
1395 #define mmAZALIA_MEM_PWR_STATUS_BASE_IDX                                                               2
1396 
1397 
1398 // addressBlock: dce_dc_hda_azf0root_dispdec
1399 // base address: 0x0
1400 #define mmAZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID                                          0x0406
1401 #define mmAZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID_BASE_IDX                                 2
1402 #define mmAZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID                                                   0x0407
1403 #define mmAZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID_BASE_IDX                                          2
1404 #define mmAZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL                                                        0x0408
1405 #define mmAZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL_BASE_IDX                                               2
1406 #define mmAZALIA_F0_CODEC_RESYNC_FIFO_CONTROL                                                          0x0409
1407 #define mmAZALIA_F0_CODEC_RESYNC_FIFO_CONTROL_BASE_IDX                                                 2
1408 #define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE                                                0x040a
1409 #define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE_BASE_IDX                                       2
1410 #define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES                                      0x040b
1411 #define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES_BASE_IDX                             2
1412 #define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS                                            0x040c
1413 #define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS_BASE_IDX                                   2
1414 #define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES                                              0x040d
1415 #define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES_BASE_IDX                                     2
1416 #define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE                                                 0x040e
1417 #define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE_BASE_IDX                                        2
1418 #define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESET                                                       0x040f
1419 #define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESET_BASE_IDX                                              2
1420 #define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID                                       0x0410
1421 #define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_BASE_IDX                              2
1422 #define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION                                   0x0411
1423 #define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION_BASE_IDX                          2
1424 #define mmCC_RCU_DC_AUDIO_PORT_CONNECTIVITY                                                            0x0412
1425 #define mmCC_RCU_DC_AUDIO_PORT_CONNECTIVITY_BASE_IDX                                                   2
1426 #define mmCC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY                                                      0x0413
1427 #define mmCC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_BASE_IDX                                             2
1428 #define mmAZALIA_F0_GTC_GROUP_OFFSET0                                                                  0x0415
1429 #define mmAZALIA_F0_GTC_GROUP_OFFSET0_BASE_IDX                                                         2
1430 #define mmAZALIA_F0_GTC_GROUP_OFFSET1                                                                  0x0416
1431 #define mmAZALIA_F0_GTC_GROUP_OFFSET1_BASE_IDX                                                         2
1432 #define mmAZALIA_F0_GTC_GROUP_OFFSET2                                                                  0x0417
1433 #define mmAZALIA_F0_GTC_GROUP_OFFSET2_BASE_IDX                                                         2
1434 #define mmAZALIA_F0_GTC_GROUP_OFFSET3                                                                  0x0418
1435 #define mmAZALIA_F0_GTC_GROUP_OFFSET3_BASE_IDX                                                         2
1436 #define mmAZALIA_F0_GTC_GROUP_OFFSET4                                                                  0x0419
1437 #define mmAZALIA_F0_GTC_GROUP_OFFSET4_BASE_IDX                                                         2
1438 #define mmAZALIA_F0_GTC_GROUP_OFFSET5                                                                  0x041a
1439 #define mmAZALIA_F0_GTC_GROUP_OFFSET5_BASE_IDX                                                         2
1440 #define mmAZALIA_F0_GTC_GROUP_OFFSET6                                                                  0x041b
1441 #define mmAZALIA_F0_GTC_GROUP_OFFSET6_BASE_IDX                                                         2
1442 #define mmREG_DC_AUDIO_PORT_CONNECTIVITY                                                               0x041c
1443 #define mmREG_DC_AUDIO_PORT_CONNECTIVITY_BASE_IDX                                                      2
1444 #define mmREG_DC_AUDIO_INPUT_PORT_CONNECTIVITY                                                         0x041d
1445 #define mmREG_DC_AUDIO_INPUT_PORT_CONNECTIVITY_BASE_IDX                                                2
1446 
1447 
1448 // addressBlock: dce_dc_hda_azf0stream8_dispdec
1449 // base address: 0x320
1450 #define mmAZF0STREAM8_AZALIA_STREAM_INDEX                                                              0x0426
1451 #define mmAZF0STREAM8_AZALIA_STREAM_INDEX_BASE_IDX                                                     2
1452 #define mmAZF0STREAM8_AZALIA_STREAM_DATA                                                               0x0427
1453 #define mmAZF0STREAM8_AZALIA_STREAM_DATA_BASE_IDX                                                      2
1454 
1455 
1456 // addressBlock: dce_dc_hda_azf0stream9_dispdec
1457 // base address: 0x328
1458 #define mmAZF0STREAM9_AZALIA_STREAM_INDEX                                                              0x0428
1459 #define mmAZF0STREAM9_AZALIA_STREAM_INDEX_BASE_IDX                                                     2
1460 #define mmAZF0STREAM9_AZALIA_STREAM_DATA                                                               0x0429
1461 #define mmAZF0STREAM9_AZALIA_STREAM_DATA_BASE_IDX                                                      2
1462 
1463 
1464 // addressBlock: dce_dc_hda_azf0stream10_dispdec
1465 // base address: 0x330
1466 #define mmAZF0STREAM10_AZALIA_STREAM_INDEX                                                             0x042a
1467 #define mmAZF0STREAM10_AZALIA_STREAM_INDEX_BASE_IDX                                                    2
1468 #define mmAZF0STREAM10_AZALIA_STREAM_DATA                                                              0x042b
1469 #define mmAZF0STREAM10_AZALIA_STREAM_DATA_BASE_IDX                                                     2
1470 
1471 
1472 // addressBlock: dce_dc_hda_azf0stream11_dispdec
1473 // base address: 0x338
1474 #define mmAZF0STREAM11_AZALIA_STREAM_INDEX                                                             0x042c
1475 #define mmAZF0STREAM11_AZALIA_STREAM_INDEX_BASE_IDX                                                    2
1476 #define mmAZF0STREAM11_AZALIA_STREAM_DATA                                                              0x042d
1477 #define mmAZF0STREAM11_AZALIA_STREAM_DATA_BASE_IDX                                                     2
1478 
1479 
1480 // addressBlock: dce_dc_hda_azf0stream12_dispdec
1481 // base address: 0x340
1482 #define mmAZF0STREAM12_AZALIA_STREAM_INDEX                                                             0x042e
1483 #define mmAZF0STREAM12_AZALIA_STREAM_INDEX_BASE_IDX                                                    2
1484 #define mmAZF0STREAM12_AZALIA_STREAM_DATA                                                              0x042f
1485 #define mmAZF0STREAM12_AZALIA_STREAM_DATA_BASE_IDX                                                     2
1486 
1487 
1488 // addressBlock: dce_dc_hda_azf0stream13_dispdec
1489 // base address: 0x348
1490 #define mmAZF0STREAM13_AZALIA_STREAM_INDEX                                                             0x0430
1491 #define mmAZF0STREAM13_AZALIA_STREAM_INDEX_BASE_IDX                                                    2
1492 #define mmAZF0STREAM13_AZALIA_STREAM_DATA                                                              0x0431
1493 #define mmAZF0STREAM13_AZALIA_STREAM_DATA_BASE_IDX                                                     2
1494 
1495 
1496 // addressBlock: dce_dc_hda_azf0stream14_dispdec
1497 // base address: 0x350
1498 #define mmAZF0STREAM14_AZALIA_STREAM_INDEX                                                             0x0432
1499 #define mmAZF0STREAM14_AZALIA_STREAM_INDEX_BASE_IDX                                                    2
1500 #define mmAZF0STREAM14_AZALIA_STREAM_DATA                                                              0x0433
1501 #define mmAZF0STREAM14_AZALIA_STREAM_DATA_BASE_IDX                                                     2
1502 
1503 
1504 // addressBlock: dce_dc_hda_azf0stream15_dispdec
1505 // base address: 0x358
1506 #define mmAZF0STREAM15_AZALIA_STREAM_INDEX                                                             0x0434
1507 #define mmAZF0STREAM15_AZALIA_STREAM_INDEX_BASE_IDX                                                    2
1508 #define mmAZF0STREAM15_AZALIA_STREAM_DATA                                                              0x0435
1509 #define mmAZF0STREAM15_AZALIA_STREAM_DATA_BASE_IDX                                                     2
1510 
1511 
1512 // addressBlock: dce_dc_hda_azf0inputendpoint0_dispdec
1513 // base address: 0x0
1514 #define mmAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX                                      0x043a
1515 #define mmAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX                             2
1516 #define mmAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA                                       0x043b
1517 #define mmAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX                              2
1518 
1519 
1520 // addressBlock: dce_dc_hda_azf0inputendpoint1_dispdec
1521 // base address: 0x10
1522 #define mmAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX                                      0x043e
1523 #define mmAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX                             2
1524 #define mmAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA                                       0x043f
1525 #define mmAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX                              2
1526 
1527 
1528 // addressBlock: dce_dc_hda_azf0inputendpoint2_dispdec
1529 // base address: 0x20
1530 #define mmAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX                                      0x0442
1531 #define mmAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX                             2
1532 #define mmAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA                                       0x0443
1533 #define mmAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX                              2
1534 
1535 
1536 // addressBlock: dce_dc_hda_azf0inputendpoint3_dispdec
1537 // base address: 0x30
1538 #define mmAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX                                      0x0446
1539 #define mmAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX                             2
1540 #define mmAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA                                       0x0447
1541 #define mmAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX                              2
1542 
1543 
1544 // addressBlock: dce_dc_hda_azf0inputendpoint4_dispdec
1545 // base address: 0x40
1546 #define mmAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX                                      0x044a
1547 #define mmAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX                             2
1548 #define mmAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA                                       0x044b
1549 #define mmAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX                              2
1550 
1551 
1552 // addressBlock: dce_dc_hda_azf0inputendpoint5_dispdec
1553 // base address: 0x50
1554 #define mmAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX                                      0x044e
1555 #define mmAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX                             2
1556 #define mmAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA                                       0x044f
1557 #define mmAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX                              2
1558 
1559 
1560 // addressBlock: dce_dc_hda_azf0inputendpoint6_dispdec
1561 // base address: 0x60
1562 #define mmAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX                                      0x0452
1563 #define mmAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX                             2
1564 #define mmAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA                                       0x0453
1565 #define mmAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX                              2
1566 
1567 
1568 // addressBlock: dce_dc_hda_azf0inputendpoint7_dispdec
1569 // base address: 0x70
1570 #define mmAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX                                      0x0456
1571 #define mmAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX                             2
1572 #define mmAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA                                       0x0457
1573 #define mmAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX                              2
1574 
1575 
1576 // addressBlock: dce_dc_dchubbub_hubbub_sdpif_dispdec
1577 // base address: 0x0
1578 #define mmDCHUBBUB_SDPIF_CFG0                                                                          0x048f
1579 #define mmDCHUBBUB_SDPIF_CFG0_BASE_IDX                                                                 2
1580 #define mmVM_REQUEST_PHYSICAL                                                                          0x0490
1581 #define mmVM_REQUEST_PHYSICAL_BASE_IDX                                                                 2
1582 #define mmDCHUBBUB_FORCE_IO_STATUS_0                                                                   0x0491
1583 #define mmDCHUBBUB_FORCE_IO_STATUS_0_BASE_IDX                                                          2
1584 #define mmDCHUBBUB_FORCE_IO_STATUS_1                                                                   0x0492
1585 #define mmDCHUBBUB_FORCE_IO_STATUS_1_BASE_IDX                                                          2
1586 #define mmDCN_VM_FB_LOCATION_BASE                                                                      0x0493
1587 #define mmDCN_VM_FB_LOCATION_BASE_BASE_IDX                                                             2
1588 #define mmDCN_VM_FB_LOCATION_TOP                                                                       0x0494
1589 #define mmDCN_VM_FB_LOCATION_TOP_BASE_IDX                                                              2
1590 #define mmDCN_VM_FB_OFFSET                                                                             0x0495
1591 #define mmDCN_VM_FB_OFFSET_BASE_IDX                                                                    2
1592 #define mmDCN_VM_AGP_BOT                                                                               0x0496
1593 #define mmDCN_VM_AGP_BOT_BASE_IDX                                                                      2
1594 #define mmDCN_VM_AGP_TOP                                                                               0x0497
1595 #define mmDCN_VM_AGP_TOP_BASE_IDX                                                                      2
1596 #define mmDCN_VM_AGP_BASE                                                                              0x0498
1597 #define mmDCN_VM_AGP_BASE_BASE_IDX                                                                     2
1598 #define mmDCN_VM_LOCAL_HBM_ADDRESS_START                                                               0x0499
1599 #define mmDCN_VM_LOCAL_HBM_ADDRESS_START_BASE_IDX                                                      2
1600 #define mmDCN_VM_LOCAL_HBM_ADDRESS_END                                                                 0x049a
1601 #define mmDCN_VM_LOCAL_HBM_ADDRESS_END_BASE_IDX                                                        2
1602 #define mmDCN_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL                                                           0x049b
1603 #define mmDCN_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL_BASE_IDX                                                  2
1604 #define mmDCHUBBUB_SDPIF_MEM_PWR_CTRL                                                                  0x04ba
1605 #define mmDCHUBBUB_SDPIF_MEM_PWR_CTRL_BASE_IDX                                                         2
1606 #define mmDCHUBBUB_SDPIF_MEM_PWR_STATUS                                                                0x04bb
1607 #define mmDCHUBBUB_SDPIF_MEM_PWR_STATUS_BASE_IDX                                                       2
1608 #define mmDCHUBBUB_SDPIF_CFG1                                                                          0x04bf
1609 #define mmDCHUBBUB_SDPIF_CFG1_BASE_IDX                                                                 2
1610 #define mmDCHUBBUB_SDPIF_CFG2                                                                          0x04c0
1611 #define mmDCHUBBUB_SDPIF_CFG2_BASE_IDX                                                                 2
1612 
1613 
1614 // addressBlock: dce_dc_dchubbub_hubbub_ret_path_dispdec
1615 // base address: 0x0
1616 #define mmDCHUBBUB_RET_PATH_DCC_CFG                                                                    0x04cf
1617 #define mmDCHUBBUB_RET_PATH_DCC_CFG_BASE_IDX                                                           2
1618 #define mmDCHUBBUB_RET_PATH_DCC_CFG0_0                                                                 0x04d0
1619 #define mmDCHUBBUB_RET_PATH_DCC_CFG0_0_BASE_IDX                                                        2
1620 #define mmDCHUBBUB_RET_PATH_DCC_CFG0_1                                                                 0x04d1
1621 #define mmDCHUBBUB_RET_PATH_DCC_CFG0_1_BASE_IDX                                                        2
1622 #define mmDCHUBBUB_RET_PATH_DCC_CFG1_0                                                                 0x04d2
1623 #define mmDCHUBBUB_RET_PATH_DCC_CFG1_0_BASE_IDX                                                        2
1624 #define mmDCHUBBUB_RET_PATH_DCC_CFG1_1                                                                 0x04d3
1625 #define mmDCHUBBUB_RET_PATH_DCC_CFG1_1_BASE_IDX                                                        2
1626 #define mmDCHUBBUB_RET_PATH_DCC_CFG2_0                                                                 0x04d4
1627 #define mmDCHUBBUB_RET_PATH_DCC_CFG2_0_BASE_IDX                                                        2
1628 #define mmDCHUBBUB_RET_PATH_DCC_CFG2_1                                                                 0x04d5
1629 #define mmDCHUBBUB_RET_PATH_DCC_CFG2_1_BASE_IDX                                                        2
1630 #define mmDCHUBBUB_RET_PATH_DCC_CFG3_0                                                                 0x04d6
1631 #define mmDCHUBBUB_RET_PATH_DCC_CFG3_0_BASE_IDX                                                        2
1632 #define mmDCHUBBUB_RET_PATH_DCC_CFG3_1                                                                 0x04d7
1633 #define mmDCHUBBUB_RET_PATH_DCC_CFG3_1_BASE_IDX                                                        2
1634 #define mmDCHUBBUB_RET_PATH_DCC_CFG4_0                                                                 0x04d8
1635 #define mmDCHUBBUB_RET_PATH_DCC_CFG4_0_BASE_IDX                                                        2
1636 #define mmDCHUBBUB_RET_PATH_DCC_CFG4_1                                                                 0x04d9
1637 #define mmDCHUBBUB_RET_PATH_DCC_CFG4_1_BASE_IDX                                                        2
1638 #define mmDCHUBBUB_RET_PATH_DCC_CFG5_0                                                                 0x04da
1639 #define mmDCHUBBUB_RET_PATH_DCC_CFG5_0_BASE_IDX                                                        2
1640 #define mmDCHUBBUB_RET_PATH_DCC_CFG5_1                                                                 0x04db
1641 #define mmDCHUBBUB_RET_PATH_DCC_CFG5_1_BASE_IDX                                                        2
1642 #define mmDCHUBBUB_RET_PATH_DCC_CFG6_0                                                                 0x04dc
1643 #define mmDCHUBBUB_RET_PATH_DCC_CFG6_0_BASE_IDX                                                        2
1644 #define mmDCHUBBUB_RET_PATH_DCC_CFG6_1                                                                 0x04dd
1645 #define mmDCHUBBUB_RET_PATH_DCC_CFG6_1_BASE_IDX                                                        2
1646 #define mmDCHUBBUB_RET_PATH_DCC_CFG7_0                                                                 0x04de
1647 #define mmDCHUBBUB_RET_PATH_DCC_CFG7_0_BASE_IDX                                                        2
1648 #define mmDCHUBBUB_RET_PATH_DCC_CFG7_1                                                                 0x04df
1649 #define mmDCHUBBUB_RET_PATH_DCC_CFG7_1_BASE_IDX                                                        2
1650 #define mmDCHUBBUB_RET_PATH_DCC_CFG8_0                                                                 0x04e0
1651 #define mmDCHUBBUB_RET_PATH_DCC_CFG8_0_BASE_IDX                                                        2
1652 #define mmDCHUBBUB_RET_PATH_DCC_CFG8_1                                                                 0x04e1
1653 #define mmDCHUBBUB_RET_PATH_DCC_CFG8_1_BASE_IDX                                                        2
1654 #define mmDCHUBBUB_RET_PATH_DCC_CFG9_0                                                                 0x04e2
1655 #define mmDCHUBBUB_RET_PATH_DCC_CFG9_0_BASE_IDX                                                        2
1656 #define mmDCHUBBUB_RET_PATH_DCC_CFG9_1                                                                 0x04e3
1657 #define mmDCHUBBUB_RET_PATH_DCC_CFG9_1_BASE_IDX                                                        2
1658 #define mmDCHUBBUB_RET_PATH_MEM_PWR_CTRL                                                               0x04ef
1659 #define mmDCHUBBUB_RET_PATH_MEM_PWR_CTRL_BASE_IDX                                                      2
1660 #define mmDCHUBBUB_RET_PATH_MEM_PWR_STATUS                                                             0x04f0
1661 #define mmDCHUBBUB_RET_PATH_MEM_PWR_STATUS_BASE_IDX                                                    2
1662 #define mmDCHUBBUB_CRC_CTRL                                                                            0x04f1
1663 #define mmDCHUBBUB_CRC_CTRL_BASE_IDX                                                                   2
1664 #define mmDCHUBBUB_CRC0_VAL_R_G                                                                        0x04f2
1665 #define mmDCHUBBUB_CRC0_VAL_R_G_BASE_IDX                                                               2
1666 #define mmDCHUBBUB_CRC0_VAL_B_A                                                                        0x04f3
1667 #define mmDCHUBBUB_CRC0_VAL_B_A_BASE_IDX                                                               2
1668 #define mmDCHUBBUB_CRC1_VAL_R_G                                                                        0x04f4
1669 #define mmDCHUBBUB_CRC1_VAL_R_G_BASE_IDX                                                               2
1670 #define mmDCHUBBUB_CRC1_VAL_B_A                                                                        0x04f5
1671 #define mmDCHUBBUB_CRC1_VAL_B_A_BASE_IDX                                                               2
1672 
1673 
1674 // addressBlock: dce_dc_dchubbub_hubbub_dispdec
1675 // base address: 0x0
1676 #define mmDCHUBBUB_ARB_DF_REQ_OUTSTAND                                                                 0x0505
1677 #define mmDCHUBBUB_ARB_DF_REQ_OUTSTAND_BASE_IDX                                                        2
1678 #define mmDCHUBBUB_ARB_SAT_LEVEL                                                                       0x0506
1679 #define mmDCHUBBUB_ARB_SAT_LEVEL_BASE_IDX                                                              2
1680 #define mmDCHUBBUB_ARB_QOS_FORCE                                                                       0x0507
1681 #define mmDCHUBBUB_ARB_QOS_FORCE_BASE_IDX                                                              2
1682 #define mmDCHUBBUB_ARB_DRAM_STATE_CNTL                                                                 0x0508
1683 #define mmDCHUBBUB_ARB_DRAM_STATE_CNTL_BASE_IDX                                                        2
1684 #define mmDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A                                                        0x0509
1685 #define mmDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A_BASE_IDX                                               2
1686 #define mmDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A                                                     0x050a
1687 #define mmDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A_BASE_IDX                                            2
1688 #define mmDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A                                                      0x050b
1689 #define mmDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A_BASE_IDX                                             2
1690 #define mmDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A                                                       0x050c
1691 #define mmDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A_BASE_IDX                                              2
1692 #define mmDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A                                               0x050d
1693 #define mmDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A_BASE_IDX                                      2
1694 #define mmDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B                                                        0x050e
1695 #define mmDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B_BASE_IDX                                               2
1696 #define mmDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B                                                     0x050f
1697 #define mmDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B_BASE_IDX                                            2
1698 #define mmDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B                                                      0x0510
1699 #define mmDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B_BASE_IDX                                             2
1700 #define mmDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B                                                       0x0511
1701 #define mmDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B_BASE_IDX                                              2
1702 #define mmDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B                                               0x0512
1703 #define mmDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B_BASE_IDX                                      2
1704 #define mmDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C                                                        0x0513
1705 #define mmDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C_BASE_IDX                                               2
1706 #define mmDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C                                                     0x0514
1707 #define mmDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C_BASE_IDX                                            2
1708 #define mmDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C                                                      0x0515
1709 #define mmDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C_BASE_IDX                                             2
1710 #define mmDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C                                                       0x0516
1711 #define mmDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C_BASE_IDX                                              2
1712 #define mmDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C                                               0x0517
1713 #define mmDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C_BASE_IDX                                      2
1714 #define mmDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D                                                        0x0518
1715 #define mmDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D_BASE_IDX                                               2
1716 #define mmDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D                                                     0x0519
1717 #define mmDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D_BASE_IDX                                            2
1718 #define mmDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D                                                      0x051a
1719 #define mmDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D_BASE_IDX                                             2
1720 #define mmDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D                                                       0x051b
1721 #define mmDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D_BASE_IDX                                              2
1722 #define mmDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D                                               0x051c
1723 #define mmDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D_BASE_IDX                                      2
1724 #define mmDCHUBBUB_ARB_WATERMARK_CHANGE_CNTL                                                           0x051d
1725 #define mmDCHUBBUB_ARB_WATERMARK_CHANGE_CNTL_BASE_IDX                                                  2
1726 #define mmDCHUBBUB_ARB_TIMEOUT_ENABLE                                                                  0x051e
1727 #define mmDCHUBBUB_ARB_TIMEOUT_ENABLE_BASE_IDX                                                         2
1728 #define mmDCHUBBUB_GLOBAL_TIMER_CNTL                                                                   0x051f
1729 #define mmDCHUBBUB_GLOBAL_TIMER_CNTL_BASE_IDX                                                          2
1730 #define mmSURFACE_CHECK0_ADDRESS_LSB                                                                   0x0520
1731 #define mmSURFACE_CHECK0_ADDRESS_LSB_BASE_IDX                                                          2
1732 #define mmSURFACE_CHECK0_ADDRESS_MSB                                                                   0x0521
1733 #define mmSURFACE_CHECK0_ADDRESS_MSB_BASE_IDX                                                          2
1734 #define mmSURFACE_CHECK1_ADDRESS_LSB                                                                   0x0522
1735 #define mmSURFACE_CHECK1_ADDRESS_LSB_BASE_IDX                                                          2
1736 #define mmSURFACE_CHECK1_ADDRESS_MSB                                                                   0x0523
1737 #define mmSURFACE_CHECK1_ADDRESS_MSB_BASE_IDX                                                          2
1738 #define mmSURFACE_CHECK2_ADDRESS_LSB                                                                   0x0524
1739 #define mmSURFACE_CHECK2_ADDRESS_LSB_BASE_IDX                                                          2
1740 #define mmSURFACE_CHECK2_ADDRESS_MSB                                                                   0x0525
1741 #define mmSURFACE_CHECK2_ADDRESS_MSB_BASE_IDX                                                          2
1742 #define mmSURFACE_CHECK3_ADDRESS_LSB                                                                   0x0526
1743 #define mmSURFACE_CHECK3_ADDRESS_LSB_BASE_IDX                                                          2
1744 #define mmSURFACE_CHECK3_ADDRESS_MSB                                                                   0x0527
1745 #define mmSURFACE_CHECK3_ADDRESS_MSB_BASE_IDX                                                          2
1746 #define mmVTG0_CONTROL                                                                                 0x0528
1747 #define mmVTG0_CONTROL_BASE_IDX                                                                        2
1748 #define mmVTG1_CONTROL                                                                                 0x0529
1749 #define mmVTG1_CONTROL_BASE_IDX                                                                        2
1750 #define mmVTG2_CONTROL                                                                                 0x052a
1751 #define mmVTG2_CONTROL_BASE_IDX                                                                        2
1752 #define mmVTG3_CONTROL                                                                                 0x052b
1753 #define mmVTG3_CONTROL_BASE_IDX                                                                        2
1754 #define mmVTG4_CONTROL                                                                                 0x052c
1755 #define mmVTG4_CONTROL_BASE_IDX                                                                        2
1756 #define mmDCHUBBUB_SOFT_RESET                                                                          0x052e
1757 #define mmDCHUBBUB_SOFT_RESET_BASE_IDX                                                                 2
1758 #define mmDCHUBBUB_CLOCK_CNTL                                                                          0x052f
1759 #define mmDCHUBBUB_CLOCK_CNTL_BASE_IDX                                                                 2
1760 #define mmDCFCLK_CNTL                                                                                  0x0530
1761 #define mmDCFCLK_CNTL_BASE_IDX                                                                         2
1762 #define mmDCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL                                                        0x0531
1763 #define mmDCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL_BASE_IDX                                               2
1764 #define mmDCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2                                                       0x0532
1765 #define mmDCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2_BASE_IDX                                              2
1766 #define mmDCHUBBUB_VLINE_SNAPSHOT                                                                      0x0533
1767 #define mmDCHUBBUB_VLINE_SNAPSHOT_BASE_IDX                                                             2
1768 #define mmDCHUBBUB_CTRL_STATUS                                                                         0x0534
1769 #define mmDCHUBBUB_CTRL_STATUS_BASE_IDX                                                                2
1770 #define mmDCHUBBUB_TIMEOUT_DETECTION_CTRL1                                                             0x053a
1771 #define mmDCHUBBUB_TIMEOUT_DETECTION_CTRL1_BASE_IDX                                                    2
1772 #define mmDCHUBBUB_TIMEOUT_DETECTION_CTRL2                                                             0x053b
1773 #define mmDCHUBBUB_TIMEOUT_DETECTION_CTRL2_BASE_IDX                                                    2
1774 #define mmDCHUBBUB_TIMEOUT_INTERRUPT_STATUS                                                            0x053c
1775 #define mmDCHUBBUB_TIMEOUT_INTERRUPT_STATUS_BASE_IDX                                                   2
1776 #define mmDCHUBBUB_TEST_DEBUG_INDEX                                                                    0x053d
1777 #define mmDCHUBBUB_TEST_DEBUG_INDEX_BASE_IDX                                                           2
1778 #define mmDCHUBBUB_TEST_DEBUG_DATA                                                                     0x053e
1779 #define mmDCHUBBUB_TEST_DEBUG_DATA_BASE_IDX                                                            2
1780 #define mmDCHUBBUB_ARB_FRAC_URG_BW_NOM_A                                                               0x053f
1781 #define mmDCHUBBUB_ARB_FRAC_URG_BW_NOM_A_BASE_IDX                                                      2
1782 #define mmDCHUBBUB_ARB_FRAC_URG_BW_FLIP_A                                                              0x0540
1783 #define mmDCHUBBUB_ARB_FRAC_URG_BW_FLIP_A_BASE_IDX                                                     2
1784 #define mmDCHUBBUB_ARB_FRAC_URG_BW_NOM_B                                                               0x0541
1785 #define mmDCHUBBUB_ARB_FRAC_URG_BW_NOM_B_BASE_IDX                                                      2
1786 #define mmDCHUBBUB_ARB_FRAC_URG_BW_FLIP_B                                                              0x0542
1787 #define mmDCHUBBUB_ARB_FRAC_URG_BW_FLIP_B_BASE_IDX                                                     2
1788 #define mmDCHUBBUB_ARB_FRAC_URG_BW_NOM_C                                                               0x0543
1789 #define mmDCHUBBUB_ARB_FRAC_URG_BW_NOM_C_BASE_IDX                                                      2
1790 #define mmDCHUBBUB_ARB_FRAC_URG_BW_FLIP_C                                                              0x0544
1791 #define mmDCHUBBUB_ARB_FRAC_URG_BW_FLIP_C_BASE_IDX                                                     2
1792 #define mmDCHUBBUB_ARB_FRAC_URG_BW_NOM_D                                                               0x0545
1793 #define mmDCHUBBUB_ARB_FRAC_URG_BW_NOM_D_BASE_IDX                                                      2
1794 #define mmDCHUBBUB_ARB_FRAC_URG_BW_FLIP_D                                                              0x0546
1795 #define mmDCHUBBUB_ARB_FRAC_URG_BW_FLIP_D_BASE_IDX                                                     2
1796 #define mmFMON_CTRL                                                                                    0x0548
1797 #define mmFMON_CTRL_BASE_IDX                                                                           2
1798 #define mmFMON_CTRL_1                                                                                  0x0548
1799 #define mmFMON_CTRL_1_BASE_IDX                                                                         2
1800 
1801 
1802 // addressBlock: dce_dc_dchubbub_dchubbub_dcperfmon_dc_perfmon_dispdec
1803 // base address: 0x1534
1804 #define mmDC_PERFMON5_PERFCOUNTER_CNTL                                                                 0x054d
1805 #define mmDC_PERFMON5_PERFCOUNTER_CNTL_BASE_IDX                                                        2
1806 #define mmDC_PERFMON5_PERFCOUNTER_CNTL2                                                                0x054e
1807 #define mmDC_PERFMON5_PERFCOUNTER_CNTL2_BASE_IDX                                                       2
1808 #define mmDC_PERFMON5_PERFCOUNTER_STATE                                                                0x054f
1809 #define mmDC_PERFMON5_PERFCOUNTER_STATE_BASE_IDX                                                       2
1810 #define mmDC_PERFMON5_PERFMON_CNTL                                                                     0x0550
1811 #define mmDC_PERFMON5_PERFMON_CNTL_BASE_IDX                                                            2
1812 #define mmDC_PERFMON5_PERFMON_CNTL2                                                                    0x0551
1813 #define mmDC_PERFMON5_PERFMON_CNTL2_BASE_IDX                                                           2
1814 #define mmDC_PERFMON5_PERFMON_CVALUE_INT_MISC                                                          0x0552
1815 #define mmDC_PERFMON5_PERFMON_CVALUE_INT_MISC_BASE_IDX                                                 2
1816 #define mmDC_PERFMON5_PERFMON_CVALUE_LOW                                                               0x0553
1817 #define mmDC_PERFMON5_PERFMON_CVALUE_LOW_BASE_IDX                                                      2
1818 #define mmDC_PERFMON5_PERFMON_HI                                                                       0x0554
1819 #define mmDC_PERFMON5_PERFMON_HI_BASE_IDX                                                              2
1820 #define mmDC_PERFMON5_PERFMON_LOW                                                                      0x0555
1821 #define mmDC_PERFMON5_PERFMON_LOW_BASE_IDX                                                             2
1822 
1823 
1824 // addressBlock: dce_dc_dchubbub_hubbub_vmrq_if_dispdec
1825 // base address: 0x0
1826 #define mmDCN_VM_CONTEXT0_CNTL                                                                         0x0559
1827 #define mmDCN_VM_CONTEXT0_CNTL_BASE_IDX                                                                2
1828 #define mmDCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32                                                    0x055a
1829 #define mmDCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                           2
1830 #define mmDCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32                                                    0x055b
1831 #define mmDCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                           2
1832 #define mmDCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32                                                   0x055c
1833 #define mmDCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                          2
1834 #define mmDCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32                                                   0x055d
1835 #define mmDCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                          2
1836 #define mmDCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32                                                     0x055e
1837 #define mmDCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                            2
1838 #define mmDCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32                                                     0x055f
1839 #define mmDCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                            2
1840 #define mmDCN_VM_CONTEXT1_CNTL                                                                         0x0560
1841 #define mmDCN_VM_CONTEXT1_CNTL_BASE_IDX                                                                2
1842 #define mmDCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32                                                    0x0561
1843 #define mmDCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                           2
1844 #define mmDCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32                                                    0x0562
1845 #define mmDCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                           2
1846 #define mmDCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32                                                   0x0563
1847 #define mmDCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                          2
1848 #define mmDCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32                                                   0x0564
1849 #define mmDCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                          2
1850 #define mmDCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32                                                     0x0565
1851 #define mmDCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                            2
1852 #define mmDCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32                                                     0x0566
1853 #define mmDCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                            2
1854 #define mmDCN_VM_CONTEXT2_CNTL                                                                         0x0567
1855 #define mmDCN_VM_CONTEXT2_CNTL_BASE_IDX                                                                2
1856 #define mmDCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32                                                    0x0568
1857 #define mmDCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                           2
1858 #define mmDCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32                                                    0x0569
1859 #define mmDCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                           2
1860 #define mmDCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32                                                   0x056a
1861 #define mmDCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                          2
1862 #define mmDCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32                                                   0x056b
1863 #define mmDCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                          2
1864 #define mmDCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32                                                     0x056c
1865 #define mmDCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                            2
1866 #define mmDCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32                                                     0x056d
1867 #define mmDCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                            2
1868 #define mmDCN_VM_CONTEXT3_CNTL                                                                         0x056e
1869 #define mmDCN_VM_CONTEXT3_CNTL_BASE_IDX                                                                2
1870 #define mmDCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32                                                    0x056f
1871 #define mmDCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                           2
1872 #define mmDCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32                                                    0x0570
1873 #define mmDCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                           2
1874 #define mmDCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32                                                   0x0571
1875 #define mmDCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                          2
1876 #define mmDCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32                                                   0x0572
1877 #define mmDCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                          2
1878 #define mmDCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32                                                     0x0573
1879 #define mmDCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                            2
1880 #define mmDCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32                                                     0x0574
1881 #define mmDCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                            2
1882 #define mmDCN_VM_CONTEXT4_CNTL                                                                         0x0575
1883 #define mmDCN_VM_CONTEXT4_CNTL_BASE_IDX                                                                2
1884 #define mmDCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32                                                    0x0576
1885 #define mmDCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                           2
1886 #define mmDCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32                                                    0x0577
1887 #define mmDCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                           2
1888 #define mmDCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32                                                   0x0578
1889 #define mmDCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                          2
1890 #define mmDCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32                                                   0x0579
1891 #define mmDCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                          2
1892 #define mmDCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32                                                     0x057a
1893 #define mmDCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                            2
1894 #define mmDCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32                                                     0x057b
1895 #define mmDCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                            2
1896 #define mmDCN_VM_CONTEXT5_CNTL                                                                         0x057c
1897 #define mmDCN_VM_CONTEXT5_CNTL_BASE_IDX                                                                2
1898 #define mmDCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32                                                    0x057d
1899 #define mmDCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                           2
1900 #define mmDCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32                                                    0x057e
1901 #define mmDCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                           2
1902 #define mmDCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32                                                   0x057f
1903 #define mmDCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                          2
1904 #define mmDCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32                                                   0x0580
1905 #define mmDCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                          2
1906 #define mmDCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32                                                     0x0581
1907 #define mmDCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                            2
1908 #define mmDCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32                                                     0x0582
1909 #define mmDCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                            2
1910 #define mmDCN_VM_CONTEXT6_CNTL                                                                         0x0583
1911 #define mmDCN_VM_CONTEXT6_CNTL_BASE_IDX                                                                2
1912 #define mmDCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32                                                    0x0584
1913 #define mmDCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                           2
1914 #define mmDCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32                                                    0x0585
1915 #define mmDCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                           2
1916 #define mmDCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32                                                   0x0586
1917 #define mmDCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                          2
1918 #define mmDCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32                                                   0x0587
1919 #define mmDCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                          2
1920 #define mmDCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32                                                     0x0588
1921 #define mmDCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                            2
1922 #define mmDCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32                                                     0x0589
1923 #define mmDCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                            2
1924 #define mmDCN_VM_CONTEXT7_CNTL                                                                         0x058a
1925 #define mmDCN_VM_CONTEXT7_CNTL_BASE_IDX                                                                2
1926 #define mmDCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32                                                    0x058b
1927 #define mmDCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                           2
1928 #define mmDCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32                                                    0x058c
1929 #define mmDCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                           2
1930 #define mmDCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32                                                   0x058d
1931 #define mmDCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                          2
1932 #define mmDCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32                                                   0x058e
1933 #define mmDCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                          2
1934 #define mmDCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32                                                     0x058f
1935 #define mmDCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                            2
1936 #define mmDCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32                                                     0x0590
1937 #define mmDCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                            2
1938 #define mmDCN_VM_CONTEXT8_CNTL                                                                         0x0591
1939 #define mmDCN_VM_CONTEXT8_CNTL_BASE_IDX                                                                2
1940 #define mmDCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32                                                    0x0592
1941 #define mmDCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                           2
1942 #define mmDCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32                                                    0x0593
1943 #define mmDCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                           2
1944 #define mmDCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32                                                   0x0594
1945 #define mmDCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                          2
1946 #define mmDCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32                                                   0x0595
1947 #define mmDCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                          2
1948 #define mmDCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32                                                     0x0596
1949 #define mmDCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                            2
1950 #define mmDCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32                                                     0x0597
1951 #define mmDCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                            2
1952 #define mmDCN_VM_CONTEXT9_CNTL                                                                         0x0598
1953 #define mmDCN_VM_CONTEXT9_CNTL_BASE_IDX                                                                2
1954 #define mmDCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32                                                    0x0599
1955 #define mmDCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                           2
1956 #define mmDCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32                                                    0x059a
1957 #define mmDCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                           2
1958 #define mmDCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32                                                   0x059b
1959 #define mmDCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                          2
1960 #define mmDCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32                                                   0x059c
1961 #define mmDCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                          2
1962 #define mmDCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32                                                     0x059d
1963 #define mmDCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                            2
1964 #define mmDCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32                                                     0x059e
1965 #define mmDCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                            2
1966 #define mmDCN_VM_CONTEXT10_CNTL                                                                        0x059f
1967 #define mmDCN_VM_CONTEXT10_CNTL_BASE_IDX                                                               2
1968 #define mmDCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32                                                   0x05a0
1969 #define mmDCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                          2
1970 #define mmDCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32                                                   0x05a1
1971 #define mmDCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                          2
1972 #define mmDCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32                                                  0x05a2
1973 #define mmDCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                         2
1974 #define mmDCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32                                                  0x05a3
1975 #define mmDCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                         2
1976 #define mmDCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32                                                    0x05a4
1977 #define mmDCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                           2
1978 #define mmDCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32                                                    0x05a5
1979 #define mmDCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                           2
1980 #define mmDCN_VM_CONTEXT11_CNTL                                                                        0x05a6
1981 #define mmDCN_VM_CONTEXT11_CNTL_BASE_IDX                                                               2
1982 #define mmDCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32                                                   0x05a7
1983 #define mmDCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                          2
1984 #define mmDCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32                                                   0x05a8
1985 #define mmDCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                          2
1986 #define mmDCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32                                                  0x05a9
1987 #define mmDCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                         2
1988 #define mmDCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32                                                  0x05aa
1989 #define mmDCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                         2
1990 #define mmDCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32                                                    0x05ab
1991 #define mmDCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                           2
1992 #define mmDCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32                                                    0x05ac
1993 #define mmDCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                           2
1994 #define mmDCN_VM_CONTEXT12_CNTL                                                                        0x05ad
1995 #define mmDCN_VM_CONTEXT12_CNTL_BASE_IDX                                                               2
1996 #define mmDCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32                                                   0x05ae
1997 #define mmDCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                          2
1998 #define mmDCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32                                                   0x05af
1999 #define mmDCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                          2
2000 #define mmDCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32                                                  0x05b0
2001 #define mmDCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                         2
2002 #define mmDCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32                                                  0x05b1
2003 #define mmDCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                         2
2004 #define mmDCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32                                                    0x05b2
2005 #define mmDCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                           2
2006 #define mmDCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32                                                    0x05b3
2007 #define mmDCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                           2
2008 #define mmDCN_VM_CONTEXT13_CNTL                                                                        0x05b4
2009 #define mmDCN_VM_CONTEXT13_CNTL_BASE_IDX                                                               2
2010 #define mmDCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32                                                   0x05b5
2011 #define mmDCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                          2
2012 #define mmDCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32                                                   0x05b6
2013 #define mmDCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                          2
2014 #define mmDCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32                                                  0x05b7
2015 #define mmDCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                         2
2016 #define mmDCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32                                                  0x05b8
2017 #define mmDCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                         2
2018 #define mmDCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32                                                    0x05b9
2019 #define mmDCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                           2
2020 #define mmDCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32                                                    0x05ba
2021 #define mmDCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                           2
2022 #define mmDCN_VM_CONTEXT14_CNTL                                                                        0x05bb
2023 #define mmDCN_VM_CONTEXT14_CNTL_BASE_IDX                                                               2
2024 #define mmDCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32                                                   0x05bc
2025 #define mmDCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                          2
2026 #define mmDCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32                                                   0x05bd
2027 #define mmDCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                          2
2028 #define mmDCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32                                                  0x05be
2029 #define mmDCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                         2
2030 #define mmDCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32                                                  0x05bf
2031 #define mmDCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                         2
2032 #define mmDCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32                                                    0x05c0
2033 #define mmDCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                           2
2034 #define mmDCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32                                                    0x05c1
2035 #define mmDCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                           2
2036 #define mmDCN_VM_CONTEXT15_CNTL                                                                        0x05c2
2037 #define mmDCN_VM_CONTEXT15_CNTL_BASE_IDX                                                               2
2038 #define mmDCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32                                                   0x05c3
2039 #define mmDCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                          2
2040 #define mmDCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32                                                   0x05c4
2041 #define mmDCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                          2
2042 #define mmDCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32                                                  0x05c5
2043 #define mmDCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                         2
2044 #define mmDCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32                                                  0x05c6
2045 #define mmDCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                         2
2046 #define mmDCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32                                                    0x05c7
2047 #define mmDCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                           2
2048 #define mmDCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32                                                    0x05c8
2049 #define mmDCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                           2
2050 #define mmDCN_VM_DEFAULT_ADDR_MSB                                                                      0x05c9
2051 #define mmDCN_VM_DEFAULT_ADDR_MSB_BASE_IDX                                                             2
2052 #define mmDCN_VM_DEFAULT_ADDR_LSB                                                                      0x05ca
2053 #define mmDCN_VM_DEFAULT_ADDR_LSB_BASE_IDX                                                             2
2054 #define mmDCN_VM_FAULT_CNTL                                                                            0x05cb
2055 #define mmDCN_VM_FAULT_CNTL_BASE_IDX                                                                   2
2056 #define mmDCN_VM_FAULT_STATUS                                                                          0x05cc
2057 #define mmDCN_VM_FAULT_STATUS_BASE_IDX                                                                 2
2058 #define mmDCN_VM_FAULT_ADDR_MSB                                                                        0x05cd
2059 #define mmDCN_VM_FAULT_ADDR_MSB_BASE_IDX                                                               2
2060 #define mmDCN_VM_FAULT_ADDR_LSB                                                                        0x05ce
2061 #define mmDCN_VM_FAULT_ADDR_LSB_BASE_IDX                                                               2
2062 
2063 
2064 // addressBlock: dce_dc_dcbubp0_dispdec_hubp_dispdec
2065 // base address: 0x0
2066 #define mmHUBP0_DCSURF_SURFACE_CONFIG                                                                  0x05e5
2067 #define mmHUBP0_DCSURF_SURFACE_CONFIG_BASE_IDX                                                         2
2068 #define mmHUBP0_DCSURF_ADDR_CONFIG                                                                     0x05e6
2069 #define mmHUBP0_DCSURF_ADDR_CONFIG_BASE_IDX                                                            2
2070 #define mmHUBP0_DCSURF_TILING_CONFIG                                                                   0x05e7
2071 #define mmHUBP0_DCSURF_TILING_CONFIG_BASE_IDX                                                          2
2072 #define mmHUBP0_DCSURF_PRI_VIEWPORT_START                                                              0x05e9
2073 #define mmHUBP0_DCSURF_PRI_VIEWPORT_START_BASE_IDX                                                     2
2074 #define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION                                                          0x05ea
2075 #define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX                                                 2
2076 #define mmHUBP0_DCSURF_PRI_VIEWPORT_START_C                                                            0x05eb
2077 #define mmHUBP0_DCSURF_PRI_VIEWPORT_START_C_BASE_IDX                                                   2
2078 #define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C                                                        0x05ec
2079 #define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C_BASE_IDX                                               2
2080 #define mmHUBP0_DCSURF_SEC_VIEWPORT_START                                                              0x05ed
2081 #define mmHUBP0_DCSURF_SEC_VIEWPORT_START_BASE_IDX                                                     2
2082 #define mmHUBP0_DCSURF_SEC_VIEWPORT_DIMENSION                                                          0x05ee
2083 #define mmHUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_BASE_IDX                                                 2
2084 #define mmHUBP0_DCSURF_SEC_VIEWPORT_START_C                                                            0x05ef
2085 #define mmHUBP0_DCSURF_SEC_VIEWPORT_START_C_BASE_IDX                                                   2
2086 #define mmHUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_C                                                        0x05f0
2087 #define mmHUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_C_BASE_IDX                                               2
2088 #define mmHUBP0_DCHUBP_REQ_SIZE_CONFIG                                                                 0x05f1
2089 #define mmHUBP0_DCHUBP_REQ_SIZE_CONFIG_BASE_IDX                                                        2
2090 #define mmHUBP0_DCHUBP_REQ_SIZE_CONFIG_C                                                               0x05f2
2091 #define mmHUBP0_DCHUBP_REQ_SIZE_CONFIG_C_BASE_IDX                                                      2
2092 #define mmHUBP0_DCHUBP_CNTL                                                                            0x05f3
2093 #define mmHUBP0_DCHUBP_CNTL_BASE_IDX                                                                   2
2094 #define mmHUBP0_HUBP_CLK_CNTL                                                                          0x05f4
2095 #define mmHUBP0_HUBP_CLK_CNTL_BASE_IDX                                                                 2
2096 #define mmHUBP0_DCHUBP_VMPG_CONFIG                                                                     0x05f5
2097 #define mmHUBP0_DCHUBP_VMPG_CONFIG_BASE_IDX                                                            2
2098 #define mmHUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK                                                           0x05fb
2099 #define mmHUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK_BASE_IDX                                                  2
2100 #define mmHUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK                                                           0x05fc
2101 #define mmHUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK_BASE_IDX                                                  2
2102 #define mmHUBP0_HUBPREQ_DEBUG_DB                                                                       0x05f6
2103 #define mmHUBP0_HUBPREQ_DEBUG_DB_BASE_IDX                                                              2
2104 #define mmHUBP0_HUBPREQ_DEBUG                                                                          0x05f7
2105 #define mmHUBP0_HUBPREQ_DEBUG_BASE_IDX                                                                 2
2106 
2107 
2108 // addressBlock: dce_dc_dcbubp0_dispdec_hubpreq_dispdec
2109 // base address: 0x0
2110 #define mmHUBPREQ0_DCSURF_SURFACE_PITCH                                                                0x0607
2111 #define mmHUBPREQ0_DCSURF_SURFACE_PITCH_BASE_IDX                                                       2
2112 #define mmHUBPREQ0_DCSURF_SURFACE_PITCH_C                                                              0x0608
2113 #define mmHUBPREQ0_DCSURF_SURFACE_PITCH_C_BASE_IDX                                                     2
2114 #define mmHUBPREQ0_VMID_SETTINGS_0                                                                     0x0609
2115 #define mmHUBPREQ0_VMID_SETTINGS_0_BASE_IDX                                                            2
2116 #define mmHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS                                                      0x060a
2117 #define mmHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_BASE_IDX                                             2
2118 #define mmHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH                                                 0x060b
2119 #define mmHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX                                        2
2120 #define mmHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_C                                                    0x060c
2121 #define mmHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_C_BASE_IDX                                           2
2122 #define mmHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C                                               0x060d
2123 #define mmHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX                                      2
2124 #define mmHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS                                                    0x060e
2125 #define mmHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_BASE_IDX                                           2
2126 #define mmHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH                                               0x060f
2127 #define mmHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX                                      2
2128 #define mmHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_C                                                  0x0610
2129 #define mmHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_C_BASE_IDX                                         2
2130 #define mmHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C                                             0x0611
2131 #define mmHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX                                    2
2132 #define mmHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS                                                 0x0612
2133 #define mmHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_BASE_IDX                                        2
2134 #define mmHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH                                            0x0613
2135 #define mmHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX                                   2
2136 #define mmHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C                                               0x0614
2137 #define mmHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C_BASE_IDX                                      2
2138 #define mmHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C                                          0x0615
2139 #define mmHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX                                 2
2140 #define mmHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS                                               0x0616
2141 #define mmHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_BASE_IDX                                      2
2142 #define mmHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH                                          0x0617
2143 #define mmHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX                                 2
2144 #define mmHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C                                             0x0618
2145 #define mmHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C_BASE_IDX                                    2
2146 #define mmHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C                                        0x0619
2147 #define mmHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX                               2
2148 #define mmHUBPREQ0_DCSURF_SURFACE_CONTROL                                                              0x061a
2149 #define mmHUBPREQ0_DCSURF_SURFACE_CONTROL_BASE_IDX                                                     2
2150 #define mmHUBPREQ0_DCSURF_FLIP_CONTROL                                                                 0x061b
2151 #define mmHUBPREQ0_DCSURF_FLIP_CONTROL_BASE_IDX                                                        2
2152 #define mmHUBPREQ0_DCSURF_FLIP_CONTROL2                                                                0x061c
2153 #define mmHUBPREQ0_DCSURF_FLIP_CONTROL2_BASE_IDX                                                       2
2154 #define mmHUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT                                                       0x0620
2155 #define mmHUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT_BASE_IDX                                              2
2156 #define mmHUBPREQ0_DCSURF_SURFACE_INUSE                                                                0x0621
2157 #define mmHUBPREQ0_DCSURF_SURFACE_INUSE_BASE_IDX                                                       2
2158 #define mmHUBPREQ0_DCSURF_SURFACE_INUSE_HIGH                                                           0x0622
2159 #define mmHUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_BASE_IDX                                                  2
2160 #define mmHUBPREQ0_DCSURF_SURFACE_INUSE_C                                                              0x0623
2161 #define mmHUBPREQ0_DCSURF_SURFACE_INUSE_C_BASE_IDX                                                     2
2162 #define mmHUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_C                                                         0x0624
2163 #define mmHUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_C_BASE_IDX                                                2
2164 #define mmHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE                                                       0x0625
2165 #define mmHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_BASE_IDX                                              2
2166 #define mmHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH                                                  0x0626
2167 #define mmHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_BASE_IDX                                         2
2168 #define mmHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_C                                                     0x0627
2169 #define mmHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_C_BASE_IDX                                            2
2170 #define mmHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C                                                0x0628
2171 #define mmHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C_BASE_IDX                                       2
2172 #define mmHUBPREQ0_DCN_EXPANSION_MODE                                                                  0x0629
2173 #define mmHUBPREQ0_DCN_EXPANSION_MODE_BASE_IDX                                                         2
2174 #define mmHUBPREQ0_DCN_TTU_QOS_WM                                                                      0x062a
2175 #define mmHUBPREQ0_DCN_TTU_QOS_WM_BASE_IDX                                                             2
2176 #define mmHUBPREQ0_DCN_GLOBAL_TTU_CNTL                                                                 0x062b
2177 #define mmHUBPREQ0_DCN_GLOBAL_TTU_CNTL_BASE_IDX                                                        2
2178 #define mmHUBPREQ0_DCN_SURF0_TTU_CNTL0                                                                 0x062c
2179 #define mmHUBPREQ0_DCN_SURF0_TTU_CNTL0_BASE_IDX                                                        2
2180 #define mmHUBPREQ0_DCN_SURF0_TTU_CNTL1                                                                 0x062d
2181 #define mmHUBPREQ0_DCN_SURF0_TTU_CNTL1_BASE_IDX                                                        2
2182 #define mmHUBPREQ0_DCN_SURF1_TTU_CNTL0                                                                 0x062e
2183 #define mmHUBPREQ0_DCN_SURF1_TTU_CNTL0_BASE_IDX                                                        2
2184 #define mmHUBPREQ0_DCN_SURF1_TTU_CNTL1                                                                 0x062f
2185 #define mmHUBPREQ0_DCN_SURF1_TTU_CNTL1_BASE_IDX                                                        2
2186 #define mmHUBPREQ0_DCN_CUR0_TTU_CNTL0                                                                  0x0630
2187 #define mmHUBPREQ0_DCN_CUR0_TTU_CNTL0_BASE_IDX                                                         2
2188 #define mmHUBPREQ0_DCN_CUR0_TTU_CNTL1                                                                  0x0631
2189 #define mmHUBPREQ0_DCN_CUR0_TTU_CNTL1_BASE_IDX                                                         2
2190 #define mmHUBPREQ0_DCN_CUR1_TTU_CNTL0                                                                  0x0632
2191 #define mmHUBPREQ0_DCN_CUR1_TTU_CNTL0_BASE_IDX                                                         2
2192 #define mmHUBPREQ0_DCN_CUR1_TTU_CNTL1                                                                  0x0633
2193 #define mmHUBPREQ0_DCN_CUR1_TTU_CNTL1_BASE_IDX                                                         2
2194 #define mmHUBPREQ0_DCN_DMDATA_VM_CNTL                                                                  0x0634
2195 #define mmHUBPREQ0_DCN_DMDATA_VM_CNTL_BASE_IDX                                                         2
2196 #define mmHUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR                                                     0x0635
2197 #define mmHUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_BASE_IDX                                            2
2198 #define mmHUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR                                                    0x0636
2199 #define mmHUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_BASE_IDX                                           2
2200 #define mmHUBPREQ0_DCN_VM_MX_L1_TLB_CNTL                                                               0x0643
2201 #define mmHUBPREQ0_DCN_VM_MX_L1_TLB_CNTL_BASE_IDX                                                      2
2202 #define mmHUBPREQ0_BLANK_OFFSET_0                                                                      0x0644
2203 #define mmHUBPREQ0_BLANK_OFFSET_0_BASE_IDX                                                             2
2204 #define mmHUBPREQ0_BLANK_OFFSET_1                                                                      0x0645
2205 #define mmHUBPREQ0_BLANK_OFFSET_1_BASE_IDX                                                             2
2206 #define mmHUBPREQ0_DST_DIMENSIONS                                                                      0x0646
2207 #define mmHUBPREQ0_DST_DIMENSIONS_BASE_IDX                                                             2
2208 #define mmHUBPREQ0_DST_AFTER_SCALER                                                                    0x0647
2209 #define mmHUBPREQ0_DST_AFTER_SCALER_BASE_IDX                                                           2
2210 #define mmHUBPREQ0_PREFETCH_SETTINGS                                                                   0x0648
2211 #define mmHUBPREQ0_PREFETCH_SETTINGS_BASE_IDX                                                          2
2212 #define mmHUBPREQ0_PREFETCH_SETTINGS_C                                                                 0x0649
2213 #define mmHUBPREQ0_PREFETCH_SETTINGS_C_BASE_IDX                                                        2
2214 #define mmHUBPREQ0_VBLANK_PARAMETERS_0                                                                 0x064a
2215 #define mmHUBPREQ0_VBLANK_PARAMETERS_0_BASE_IDX                                                        2
2216 #define mmHUBPREQ0_VBLANK_PARAMETERS_1                                                                 0x064b
2217 #define mmHUBPREQ0_VBLANK_PARAMETERS_1_BASE_IDX                                                        2
2218 #define mmHUBPREQ0_VBLANK_PARAMETERS_2                                                                 0x064c
2219 #define mmHUBPREQ0_VBLANK_PARAMETERS_2_BASE_IDX                                                        2
2220 #define mmHUBPREQ0_VBLANK_PARAMETERS_3                                                                 0x064d
2221 #define mmHUBPREQ0_VBLANK_PARAMETERS_3_BASE_IDX                                                        2
2222 #define mmHUBPREQ0_VBLANK_PARAMETERS_4                                                                 0x064e
2223 #define mmHUBPREQ0_VBLANK_PARAMETERS_4_BASE_IDX                                                        2
2224 #define mmHUBPREQ0_FLIP_PARAMETERS_0                                                                   0x064f
2225 #define mmHUBPREQ0_FLIP_PARAMETERS_0_BASE_IDX                                                          2
2226 #define mmHUBPREQ0_FLIP_PARAMETERS_1                                                                   0x0650
2227 #define mmHUBPREQ0_FLIP_PARAMETERS_1_BASE_IDX                                                          2
2228 #define mmHUBPREQ0_FLIP_PARAMETERS_2                                                                   0x0651
2229 #define mmHUBPREQ0_FLIP_PARAMETERS_2_BASE_IDX                                                          2
2230 #define mmHUBPREQ0_NOM_PARAMETERS_0                                                                    0x0652
2231 #define mmHUBPREQ0_NOM_PARAMETERS_0_BASE_IDX                                                           2
2232 #define mmHUBPREQ0_NOM_PARAMETERS_1                                                                    0x0653
2233 #define mmHUBPREQ0_NOM_PARAMETERS_1_BASE_IDX                                                           2
2234 #define mmHUBPREQ0_NOM_PARAMETERS_2                                                                    0x0654
2235 #define mmHUBPREQ0_NOM_PARAMETERS_2_BASE_IDX                                                           2
2236 #define mmHUBPREQ0_NOM_PARAMETERS_3                                                                    0x0655
2237 #define mmHUBPREQ0_NOM_PARAMETERS_3_BASE_IDX                                                           2
2238 #define mmHUBPREQ0_NOM_PARAMETERS_4                                                                    0x0656
2239 #define mmHUBPREQ0_NOM_PARAMETERS_4_BASE_IDX                                                           2
2240 #define mmHUBPREQ0_NOM_PARAMETERS_5                                                                    0x0657
2241 #define mmHUBPREQ0_NOM_PARAMETERS_5_BASE_IDX                                                           2
2242 #define mmHUBPREQ0_NOM_PARAMETERS_6                                                                    0x0658
2243 #define mmHUBPREQ0_NOM_PARAMETERS_6_BASE_IDX                                                           2
2244 #define mmHUBPREQ0_NOM_PARAMETERS_7                                                                    0x0659
2245 #define mmHUBPREQ0_NOM_PARAMETERS_7_BASE_IDX                                                           2
2246 #define mmHUBPREQ0_PER_LINE_DELIVERY_PRE                                                               0x065a
2247 #define mmHUBPREQ0_PER_LINE_DELIVERY_PRE_BASE_IDX                                                      2
2248 #define mmHUBPREQ0_PER_LINE_DELIVERY                                                                   0x065b
2249 #define mmHUBPREQ0_PER_LINE_DELIVERY_BASE_IDX                                                          2
2250 #define mmHUBPREQ0_CURSOR_SETTINGS                                                                     0x065c
2251 #define mmHUBPREQ0_CURSOR_SETTINGS_BASE_IDX                                                            2
2252 #define mmHUBPREQ0_REF_FREQ_TO_PIX_FREQ                                                                0x065d
2253 #define mmHUBPREQ0_REF_FREQ_TO_PIX_FREQ_BASE_IDX                                                       2
2254 #define mmHUBPREQ0_DST_Y_DELTA_DRQ_LIMIT                                                               0x065e
2255 #define mmHUBPREQ0_DST_Y_DELTA_DRQ_LIMIT_BASE_IDX                                                      2
2256 #define mmHUBPREQ0_HUBPREQ_MEM_PWR_CTRL                                                                0x065f
2257 #define mmHUBPREQ0_HUBPREQ_MEM_PWR_CTRL_BASE_IDX                                                       2
2258 #define mmHUBPREQ0_HUBPREQ_MEM_PWR_STATUS                                                              0x0660
2259 #define mmHUBPREQ0_HUBPREQ_MEM_PWR_STATUS_BASE_IDX                                                     2
2260 #define mmHUBPREQ0_VBLANK_PARAMETERS_5                                                                 0x0663
2261 #define mmHUBPREQ0_VBLANK_PARAMETERS_5_BASE_IDX                                                        2
2262 #define mmHUBPREQ0_VBLANK_PARAMETERS_6                                                                 0x0664
2263 #define mmHUBPREQ0_VBLANK_PARAMETERS_6_BASE_IDX                                                        2
2264 #define mmHUBPREQ0_FLIP_PARAMETERS_3                                                                   0x0665
2265 #define mmHUBPREQ0_FLIP_PARAMETERS_3_BASE_IDX                                                          2
2266 #define mmHUBPREQ0_FLIP_PARAMETERS_4                                                                   0x0666
2267 #define mmHUBPREQ0_FLIP_PARAMETERS_4_BASE_IDX                                                          2
2268 #define mmHUBPREQ0_FLIP_PARAMETERS_5                                                                   0x0667
2269 #define mmHUBPREQ0_FLIP_PARAMETERS_5_BASE_IDX                                                          2
2270 #define mmHUBPREQ0_FLIP_PARAMETERS_6                                                                   0x0668
2271 #define mmHUBPREQ0_FLIP_PARAMETERS_6_BASE_IDX                                                          2
2272 
2273 
2274 // addressBlock: dce_dc_dcbubp0_dispdec_hubpret_dispdec
2275 // base address: 0x0
2276 #define mmHUBPRET0_HUBPRET_CONTROL                                                                     0x066c
2277 #define mmHUBPRET0_HUBPRET_CONTROL_BASE_IDX                                                            2
2278 #define mmHUBPRET0_HUBPRET_MEM_PWR_CTRL                                                                0x066d
2279 #define mmHUBPRET0_HUBPRET_MEM_PWR_CTRL_BASE_IDX                                                       2
2280 #define mmHUBPRET0_HUBPRET_MEM_PWR_STATUS                                                              0x066e
2281 #define mmHUBPRET0_HUBPRET_MEM_PWR_STATUS_BASE_IDX                                                     2
2282 #define mmHUBPRET0_HUBPRET_READ_LINE_CTRL0                                                             0x066f
2283 #define mmHUBPRET0_HUBPRET_READ_LINE_CTRL0_BASE_IDX                                                    2
2284 #define mmHUBPRET0_HUBPRET_READ_LINE_CTRL1                                                             0x0670
2285 #define mmHUBPRET0_HUBPRET_READ_LINE_CTRL1_BASE_IDX                                                    2
2286 #define mmHUBPRET0_HUBPRET_READ_LINE0                                                                  0x0671
2287 #define mmHUBPRET0_HUBPRET_READ_LINE0_BASE_IDX                                                         2
2288 #define mmHUBPRET0_HUBPRET_READ_LINE1                                                                  0x0672
2289 #define mmHUBPRET0_HUBPRET_READ_LINE1_BASE_IDX                                                         2
2290 #define mmHUBPRET0_HUBPRET_INTERRUPT                                                                   0x0673
2291 #define mmHUBPRET0_HUBPRET_INTERRUPT_BASE_IDX                                                          2
2292 #define mmHUBPRET0_HUBPRET_READ_LINE_VALUE                                                             0x0674
2293 #define mmHUBPRET0_HUBPRET_READ_LINE_VALUE_BASE_IDX                                                    2
2294 #define mmHUBPRET0_HUBPRET_READ_LINE_STATUS                                                            0x0675
2295 #define mmHUBPRET0_HUBPRET_READ_LINE_STATUS_BASE_IDX                                                   2
2296 
2297 
2298 // addressBlock: dce_dc_dcbubp0_dispdec_cursor0_dispdec
2299 // base address: 0x0
2300 #define mmCURSOR0_0_CURSOR_CONTROL                                                                     0x0678
2301 #define mmCURSOR0_0_CURSOR_CONTROL_BASE_IDX                                                            2
2302 #define mmCURSOR0_0_CURSOR_SURFACE_ADDRESS                                                             0x0679
2303 #define mmCURSOR0_0_CURSOR_SURFACE_ADDRESS_BASE_IDX                                                    2
2304 #define mmCURSOR0_0_CURSOR_SURFACE_ADDRESS_HIGH                                                        0x067a
2305 #define mmCURSOR0_0_CURSOR_SURFACE_ADDRESS_HIGH_BASE_IDX                                               2
2306 #define mmCURSOR0_0_CURSOR_SIZE                                                                        0x067b
2307 #define mmCURSOR0_0_CURSOR_SIZE_BASE_IDX                                                               2
2308 #define mmCURSOR0_0_CURSOR_POSITION                                                                    0x067c
2309 #define mmCURSOR0_0_CURSOR_POSITION_BASE_IDX                                                           2
2310 #define mmCURSOR0_0_CURSOR_HOT_SPOT                                                                    0x067d
2311 #define mmCURSOR0_0_CURSOR_HOT_SPOT_BASE_IDX                                                           2
2312 #define mmCURSOR0_0_CURSOR_STEREO_CONTROL                                                              0x067e
2313 #define mmCURSOR0_0_CURSOR_STEREO_CONTROL_BASE_IDX                                                     2
2314 #define mmCURSOR0_0_CURSOR_DST_OFFSET                                                                  0x067f
2315 #define mmCURSOR0_0_CURSOR_DST_OFFSET_BASE_IDX                                                         2
2316 #define mmCURSOR0_0_CURSOR_MEM_PWR_CTRL                                                                0x0680
2317 #define mmCURSOR0_0_CURSOR_MEM_PWR_CTRL_BASE_IDX                                                       2
2318 #define mmCURSOR0_0_CURSOR_MEM_PWR_STATUS                                                              0x0681
2319 #define mmCURSOR0_0_CURSOR_MEM_PWR_STATUS_BASE_IDX                                                     2
2320 #define mmCURSOR0_0_DMDATA_ADDRESS_HIGH                                                                0x0682
2321 #define mmCURSOR0_0_DMDATA_ADDRESS_HIGH_BASE_IDX                                                       2
2322 #define mmCURSOR0_0_DMDATA_ADDRESS_LOW                                                                 0x0683
2323 #define mmCURSOR0_0_DMDATA_ADDRESS_LOW_BASE_IDX                                                        2
2324 #define mmCURSOR0_0_DMDATA_CNTL                                                                        0x0684
2325 #define mmCURSOR0_0_DMDATA_CNTL_BASE_IDX                                                               2
2326 #define mmCURSOR0_0_DMDATA_QOS_CNTL                                                                    0x0685
2327 #define mmCURSOR0_0_DMDATA_QOS_CNTL_BASE_IDX                                                           2
2328 #define mmCURSOR0_0_DMDATA_STATUS                                                                      0x0686
2329 #define mmCURSOR0_0_DMDATA_STATUS_BASE_IDX                                                             2
2330 #define mmCURSOR0_0_DMDATA_SW_CNTL                                                                     0x0687
2331 #define mmCURSOR0_0_DMDATA_SW_CNTL_BASE_IDX                                                            2
2332 #define mmCURSOR0_0_DMDATA_SW_DATA                                                                     0x0688
2333 #define mmCURSOR0_0_DMDATA_SW_DATA_BASE_IDX                                                            2
2334 
2335 
2336 // addressBlock: dce_dc_dcbubp0_dispdec_hubp_dcperfmon_dc_perfmon_dispdec
2337 // base address: 0x1a74
2338 #define mmDC_PERFMON6_PERFCOUNTER_CNTL                                                                 0x069d
2339 #define mmDC_PERFMON6_PERFCOUNTER_CNTL_BASE_IDX                                                        2
2340 #define mmDC_PERFMON6_PERFCOUNTER_CNTL2                                                                0x069e
2341 #define mmDC_PERFMON6_PERFCOUNTER_CNTL2_BASE_IDX                                                       2
2342 #define mmDC_PERFMON6_PERFCOUNTER_STATE                                                                0x069f
2343 #define mmDC_PERFMON6_PERFCOUNTER_STATE_BASE_IDX                                                       2
2344 #define mmDC_PERFMON6_PERFMON_CNTL                                                                     0x06a0
2345 #define mmDC_PERFMON6_PERFMON_CNTL_BASE_IDX                                                            2
2346 #define mmDC_PERFMON6_PERFMON_CNTL2                                                                    0x06a1
2347 #define mmDC_PERFMON6_PERFMON_CNTL2_BASE_IDX                                                           2
2348 #define mmDC_PERFMON6_PERFMON_CVALUE_INT_MISC                                                          0x06a2
2349 #define mmDC_PERFMON6_PERFMON_CVALUE_INT_MISC_BASE_IDX                                                 2
2350 #define mmDC_PERFMON6_PERFMON_CVALUE_LOW                                                               0x06a3
2351 #define mmDC_PERFMON6_PERFMON_CVALUE_LOW_BASE_IDX                                                      2
2352 #define mmDC_PERFMON6_PERFMON_HI                                                                       0x06a4
2353 #define mmDC_PERFMON6_PERFMON_HI_BASE_IDX                                                              2
2354 #define mmDC_PERFMON6_PERFMON_LOW                                                                      0x06a5
2355 #define mmDC_PERFMON6_PERFMON_LOW_BASE_IDX                                                             2
2356 
2357 
2358 // addressBlock: dce_dc_dcbubp1_dispdec_hubp_dispdec
2359 // base address: 0x370
2360 #define mmHUBP1_DCSURF_SURFACE_CONFIG                                                                  0x06c1
2361 #define mmHUBP1_DCSURF_SURFACE_CONFIG_BASE_IDX                                                         2
2362 #define mmHUBP1_DCSURF_ADDR_CONFIG                                                                     0x06c2
2363 #define mmHUBP1_DCSURF_ADDR_CONFIG_BASE_IDX                                                            2
2364 #define mmHUBP1_DCSURF_TILING_CONFIG                                                                   0x06c3
2365 #define mmHUBP1_DCSURF_TILING_CONFIG_BASE_IDX                                                          2
2366 #define mmHUBP1_DCSURF_PRI_VIEWPORT_START                                                              0x06c5
2367 #define mmHUBP1_DCSURF_PRI_VIEWPORT_START_BASE_IDX                                                     2
2368 #define mmHUBP1_DCSURF_PRI_VIEWPORT_DIMENSION                                                          0x06c6
2369 #define mmHUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX                                                 2
2370 #define mmHUBP1_DCSURF_PRI_VIEWPORT_START_C                                                            0x06c7
2371 #define mmHUBP1_DCSURF_PRI_VIEWPORT_START_C_BASE_IDX                                                   2
2372 #define mmHUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_C                                                        0x06c8
2373 #define mmHUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_C_BASE_IDX                                               2
2374 #define mmHUBP1_DCSURF_SEC_VIEWPORT_START                                                              0x06c9
2375 #define mmHUBP1_DCSURF_SEC_VIEWPORT_START_BASE_IDX                                                     2
2376 #define mmHUBP1_DCSURF_SEC_VIEWPORT_DIMENSION                                                          0x06ca
2377 #define mmHUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_BASE_IDX                                                 2
2378 #define mmHUBP1_DCSURF_SEC_VIEWPORT_START_C                                                            0x06cb
2379 #define mmHUBP1_DCSURF_SEC_VIEWPORT_START_C_BASE_IDX                                                   2
2380 #define mmHUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_C                                                        0x06cc
2381 #define mmHUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_C_BASE_IDX                                               2
2382 #define mmHUBP1_DCHUBP_REQ_SIZE_CONFIG                                                                 0x06cd
2383 #define mmHUBP1_DCHUBP_REQ_SIZE_CONFIG_BASE_IDX                                                        2
2384 #define mmHUBP1_DCHUBP_REQ_SIZE_CONFIG_C                                                               0x06ce
2385 #define mmHUBP1_DCHUBP_REQ_SIZE_CONFIG_C_BASE_IDX                                                      2
2386 #define mmHUBP1_DCHUBP_CNTL                                                                            0x06cf
2387 #define mmHUBP1_DCHUBP_CNTL_BASE_IDX                                                                   2
2388 #define mmHUBP1_HUBP_CLK_CNTL                                                                          0x06d0
2389 #define mmHUBP1_HUBP_CLK_CNTL_BASE_IDX                                                                 2
2390 #define mmHUBP1_DCHUBP_VMPG_CONFIG                                                                     0x06d1
2391 #define mmHUBP1_DCHUBP_VMPG_CONFIG_BASE_IDX                                                            2
2392 #define mmHUBP1_HUBPREQ_DEBUG_DB                                                                       0x06d2
2393 #define mmHUBP1_HUBPREQ_DEBUG_DB_BASE_IDX                                                              2
2394 #define mmHUBP1_HUBPREQ_DEBUG                                                                          0x06d3
2395 #define mmHUBP1_HUBPREQ_DEBUG_BASE_IDX                                                                 2
2396 #define mmHUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK                                                           0x06d7
2397 #define mmHUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK_BASE_IDX                                                  2
2398 #define mmHUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK                                                           0x06d8
2399 #define mmHUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK_BASE_IDX                                                  2
2400 
2401 
2402 // addressBlock: dce_dc_dcbubp1_dispdec_hubpreq_dispdec
2403 // base address: 0x370
2404 #define mmHUBPREQ1_DCSURF_SURFACE_PITCH                                                                0x06e3
2405 #define mmHUBPREQ1_DCSURF_SURFACE_PITCH_BASE_IDX                                                       2
2406 #define mmHUBPREQ1_DCSURF_SURFACE_PITCH_C                                                              0x06e4
2407 #define mmHUBPREQ1_DCSURF_SURFACE_PITCH_C_BASE_IDX                                                     2
2408 #define mmHUBPREQ1_VMID_SETTINGS_0                                                                     0x06e5
2409 #define mmHUBPREQ1_VMID_SETTINGS_0_BASE_IDX                                                            2
2410 #define mmHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS                                                      0x06e6
2411 #define mmHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_BASE_IDX                                             2
2412 #define mmHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH                                                 0x06e7
2413 #define mmHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX                                        2
2414 #define mmHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_C                                                    0x06e8
2415 #define mmHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_C_BASE_IDX                                           2
2416 #define mmHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C                                               0x06e9
2417 #define mmHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX                                      2
2418 #define mmHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS                                                    0x06ea
2419 #define mmHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_BASE_IDX                                           2
2420 #define mmHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH                                               0x06eb
2421 #define mmHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX                                      2
2422 #define mmHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_C                                                  0x06ec
2423 #define mmHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_C_BASE_IDX                                         2
2424 #define mmHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C                                             0x06ed
2425 #define mmHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX                                    2
2426 #define mmHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS                                                 0x06ee
2427 #define mmHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_BASE_IDX                                        2
2428 #define mmHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH                                            0x06ef
2429 #define mmHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX                                   2
2430 #define mmHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C                                               0x06f0
2431 #define mmHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C_BASE_IDX                                      2
2432 #define mmHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C                                          0x06f1
2433 #define mmHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX                                 2
2434 #define mmHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS                                               0x06f2
2435 #define mmHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_BASE_IDX                                      2
2436 #define mmHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH                                          0x06f3
2437 #define mmHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX                                 2
2438 #define mmHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C                                             0x06f4
2439 #define mmHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C_BASE_IDX                                    2
2440 #define mmHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C                                        0x06f5
2441 #define mmHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX                               2
2442 #define mmHUBPREQ1_DCSURF_SURFACE_CONTROL                                                              0x06f6
2443 #define mmHUBPREQ1_DCSURF_SURFACE_CONTROL_BASE_IDX                                                     2
2444 #define mmHUBPREQ1_DCSURF_FLIP_CONTROL                                                                 0x06f7
2445 #define mmHUBPREQ1_DCSURF_FLIP_CONTROL_BASE_IDX                                                        2
2446 #define mmHUBPREQ1_DCSURF_FLIP_CONTROL2                                                                0x06f8
2447 #define mmHUBPREQ1_DCSURF_FLIP_CONTROL2_BASE_IDX                                                       2
2448 #define mmHUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT                                                       0x06fc
2449 #define mmHUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT_BASE_IDX                                              2
2450 #define mmHUBPREQ1_DCSURF_SURFACE_INUSE                                                                0x06fd
2451 #define mmHUBPREQ1_DCSURF_SURFACE_INUSE_BASE_IDX                                                       2
2452 #define mmHUBPREQ1_DCSURF_SURFACE_INUSE_HIGH                                                           0x06fe
2453 #define mmHUBPREQ1_DCSURF_SURFACE_INUSE_HIGH_BASE_IDX                                                  2
2454 #define mmHUBPREQ1_DCSURF_SURFACE_INUSE_C                                                              0x06ff
2455 #define mmHUBPREQ1_DCSURF_SURFACE_INUSE_C_BASE_IDX                                                     2
2456 #define mmHUBPREQ1_DCSURF_SURFACE_INUSE_HIGH_C                                                         0x0700
2457 #define mmHUBPREQ1_DCSURF_SURFACE_INUSE_HIGH_C_BASE_IDX                                                2
2458 #define mmHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE                                                       0x0701
2459 #define mmHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_BASE_IDX                                              2
2460 #define mmHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH                                                  0x0702
2461 #define mmHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_BASE_IDX                                         2
2462 #define mmHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_C                                                     0x0703
2463 #define mmHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_C_BASE_IDX                                            2
2464 #define mmHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C                                                0x0704
2465 #define mmHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C_BASE_IDX                                       2
2466 #define mmHUBPREQ1_DCN_EXPANSION_MODE                                                                  0x0705
2467 #define mmHUBPREQ1_DCN_EXPANSION_MODE_BASE_IDX                                                         2
2468 #define mmHUBPREQ1_DCN_TTU_QOS_WM                                                                      0x0706
2469 #define mmHUBPREQ1_DCN_TTU_QOS_WM_BASE_IDX                                                             2
2470 #define mmHUBPREQ1_DCN_GLOBAL_TTU_CNTL                                                                 0x0707
2471 #define mmHUBPREQ1_DCN_GLOBAL_TTU_CNTL_BASE_IDX                                                        2
2472 #define mmHUBPREQ1_DCN_SURF0_TTU_CNTL0                                                                 0x0708
2473 #define mmHUBPREQ1_DCN_SURF0_TTU_CNTL0_BASE_IDX                                                        2
2474 #define mmHUBPREQ1_DCN_SURF0_TTU_CNTL1                                                                 0x0709
2475 #define mmHUBPREQ1_DCN_SURF0_TTU_CNTL1_BASE_IDX                                                        2
2476 #define mmHUBPREQ1_DCN_SURF1_TTU_CNTL0                                                                 0x070a
2477 #define mmHUBPREQ1_DCN_SURF1_TTU_CNTL0_BASE_IDX                                                        2
2478 #define mmHUBPREQ1_DCN_SURF1_TTU_CNTL1                                                                 0x070b
2479 #define mmHUBPREQ1_DCN_SURF1_TTU_CNTL1_BASE_IDX                                                        2
2480 #define mmHUBPREQ1_DCN_CUR0_TTU_CNTL0                                                                  0x070c
2481 #define mmHUBPREQ1_DCN_CUR0_TTU_CNTL0_BASE_IDX                                                         2
2482 #define mmHUBPREQ1_DCN_CUR0_TTU_CNTL1                                                                  0x070d
2483 #define mmHUBPREQ1_DCN_CUR0_TTU_CNTL1_BASE_IDX                                                         2
2484 #define mmHUBPREQ1_DCN_CUR1_TTU_CNTL0                                                                  0x070e
2485 #define mmHUBPREQ1_DCN_CUR1_TTU_CNTL0_BASE_IDX                                                         2
2486 #define mmHUBPREQ1_DCN_CUR1_TTU_CNTL1                                                                  0x070f
2487 #define mmHUBPREQ1_DCN_CUR1_TTU_CNTL1_BASE_IDX                                                         2
2488 #define mmHUBPREQ1_DCN_DMDATA_VM_CNTL                                                                  0x0710
2489 #define mmHUBPREQ1_DCN_DMDATA_VM_CNTL_BASE_IDX                                                         2
2490 #define mmHUBPREQ1_DCN_VM_SYSTEM_APERTURE_LOW_ADDR                                                     0x0711
2491 #define mmHUBPREQ1_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_BASE_IDX                                            2
2492 #define mmHUBPREQ1_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR                                                    0x0712
2493 #define mmHUBPREQ1_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_BASE_IDX                                           2
2494 #define mmHUBPREQ1_DCN_VM_MX_L1_TLB_CNTL                                                               0x071f
2495 #define mmHUBPREQ1_DCN_VM_MX_L1_TLB_CNTL_BASE_IDX                                                      2
2496 #define mmHUBPREQ1_BLANK_OFFSET_0                                                                      0x0720
2497 #define mmHUBPREQ1_BLANK_OFFSET_0_BASE_IDX                                                             2
2498 #define mmHUBPREQ1_BLANK_OFFSET_1                                                                      0x0721
2499 #define mmHUBPREQ1_BLANK_OFFSET_1_BASE_IDX                                                             2
2500 #define mmHUBPREQ1_DST_DIMENSIONS                                                                      0x0722
2501 #define mmHUBPREQ1_DST_DIMENSIONS_BASE_IDX                                                             2
2502 #define mmHUBPREQ1_DST_AFTER_SCALER                                                                    0x0723
2503 #define mmHUBPREQ1_DST_AFTER_SCALER_BASE_IDX                                                           2
2504 #define mmHUBPREQ1_PREFETCH_SETTINGS                                                                   0x0724
2505 #define mmHUBPREQ1_PREFETCH_SETTINGS_BASE_IDX                                                          2
2506 #define mmHUBPREQ1_PREFETCH_SETTINGS_C                                                                 0x0725
2507 #define mmHUBPREQ1_PREFETCH_SETTINGS_C_BASE_IDX                                                        2
2508 #define mmHUBPREQ1_VBLANK_PARAMETERS_0                                                                 0x0726
2509 #define mmHUBPREQ1_VBLANK_PARAMETERS_0_BASE_IDX                                                        2
2510 #define mmHUBPREQ1_VBLANK_PARAMETERS_1                                                                 0x0727
2511 #define mmHUBPREQ1_VBLANK_PARAMETERS_1_BASE_IDX                                                        2
2512 #define mmHUBPREQ1_VBLANK_PARAMETERS_2                                                                 0x0728
2513 #define mmHUBPREQ1_VBLANK_PARAMETERS_2_BASE_IDX                                                        2
2514 #define mmHUBPREQ1_VBLANK_PARAMETERS_3                                                                 0x0729
2515 #define mmHUBPREQ1_VBLANK_PARAMETERS_3_BASE_IDX                                                        2
2516 #define mmHUBPREQ1_VBLANK_PARAMETERS_4                                                                 0x072a
2517 #define mmHUBPREQ1_VBLANK_PARAMETERS_4_BASE_IDX                                                        2
2518 #define mmHUBPREQ1_FLIP_PARAMETERS_0                                                                   0x072b
2519 #define mmHUBPREQ1_FLIP_PARAMETERS_0_BASE_IDX                                                          2
2520 #define mmHUBPREQ1_FLIP_PARAMETERS_1                                                                   0x072c
2521 #define mmHUBPREQ1_FLIP_PARAMETERS_1_BASE_IDX                                                          2
2522 #define mmHUBPREQ1_FLIP_PARAMETERS_2                                                                   0x072d
2523 #define mmHUBPREQ1_FLIP_PARAMETERS_2_BASE_IDX                                                          2
2524 #define mmHUBPREQ1_NOM_PARAMETERS_0                                                                    0x072e
2525 #define mmHUBPREQ1_NOM_PARAMETERS_0_BASE_IDX                                                           2
2526 #define mmHUBPREQ1_NOM_PARAMETERS_1                                                                    0x072f
2527 #define mmHUBPREQ1_NOM_PARAMETERS_1_BASE_IDX                                                           2
2528 #define mmHUBPREQ1_NOM_PARAMETERS_2                                                                    0x0730
2529 #define mmHUBPREQ1_NOM_PARAMETERS_2_BASE_IDX                                                           2
2530 #define mmHUBPREQ1_NOM_PARAMETERS_3                                                                    0x0731
2531 #define mmHUBPREQ1_NOM_PARAMETERS_3_BASE_IDX                                                           2
2532 #define mmHUBPREQ1_NOM_PARAMETERS_4                                                                    0x0732
2533 #define mmHUBPREQ1_NOM_PARAMETERS_4_BASE_IDX                                                           2
2534 #define mmHUBPREQ1_NOM_PARAMETERS_5                                                                    0x0733
2535 #define mmHUBPREQ1_NOM_PARAMETERS_5_BASE_IDX                                                           2
2536 #define mmHUBPREQ1_NOM_PARAMETERS_6                                                                    0x0734
2537 #define mmHUBPREQ1_NOM_PARAMETERS_6_BASE_IDX                                                           2
2538 #define mmHUBPREQ1_NOM_PARAMETERS_7                                                                    0x0735
2539 #define mmHUBPREQ1_NOM_PARAMETERS_7_BASE_IDX                                                           2
2540 #define mmHUBPREQ1_PER_LINE_DELIVERY_PRE                                                               0x0736
2541 #define mmHUBPREQ1_PER_LINE_DELIVERY_PRE_BASE_IDX                                                      2
2542 #define mmHUBPREQ1_PER_LINE_DELIVERY                                                                   0x0737
2543 #define mmHUBPREQ1_PER_LINE_DELIVERY_BASE_IDX                                                          2
2544 #define mmHUBPREQ1_CURSOR_SETTINGS                                                                     0x0738
2545 #define mmHUBPREQ1_CURSOR_SETTINGS_BASE_IDX                                                            2
2546 #define mmHUBPREQ1_REF_FREQ_TO_PIX_FREQ                                                                0x0739
2547 #define mmHUBPREQ1_REF_FREQ_TO_PIX_FREQ_BASE_IDX                                                       2
2548 #define mmHUBPREQ1_DST_Y_DELTA_DRQ_LIMIT                                                               0x073a
2549 #define mmHUBPREQ1_DST_Y_DELTA_DRQ_LIMIT_BASE_IDX                                                      2
2550 #define mmHUBPREQ1_HUBPREQ_MEM_PWR_CTRL                                                                0x073b
2551 #define mmHUBPREQ1_HUBPREQ_MEM_PWR_CTRL_BASE_IDX                                                       2
2552 #define mmHUBPREQ1_HUBPREQ_MEM_PWR_STATUS                                                              0x073c
2553 #define mmHUBPREQ1_HUBPREQ_MEM_PWR_STATUS_BASE_IDX                                                     2
2554 #define mmHUBPREQ1_VBLANK_PARAMETERS_5                                                                 0x073f
2555 #define mmHUBPREQ1_VBLANK_PARAMETERS_5_BASE_IDX                                                        2
2556 #define mmHUBPREQ1_VBLANK_PARAMETERS_6                                                                 0x0740
2557 #define mmHUBPREQ1_VBLANK_PARAMETERS_6_BASE_IDX                                                        2
2558 #define mmHUBPREQ1_FLIP_PARAMETERS_3                                                                   0x0741
2559 #define mmHUBPREQ1_FLIP_PARAMETERS_3_BASE_IDX                                                          2
2560 #define mmHUBPREQ1_FLIP_PARAMETERS_4                                                                   0x0742
2561 #define mmHUBPREQ1_FLIP_PARAMETERS_4_BASE_IDX                                                          2
2562 #define mmHUBPREQ1_FLIP_PARAMETERS_5                                                                   0x0743
2563 #define mmHUBPREQ1_FLIP_PARAMETERS_5_BASE_IDX                                                          2
2564 #define mmHUBPREQ1_FLIP_PARAMETERS_6                                                                   0x0744
2565 #define mmHUBPREQ1_FLIP_PARAMETERS_6_BASE_IDX                                                          2
2566 
2567 
2568 // addressBlock: dce_dc_dcbubp1_dispdec_hubpret_dispdec
2569 // base address: 0x370
2570 #define mmHUBPRET1_HUBPRET_CONTROL                                                                     0x0748
2571 #define mmHUBPRET1_HUBPRET_CONTROL_BASE_IDX                                                            2
2572 #define mmHUBPRET1_HUBPRET_MEM_PWR_CTRL                                                                0x0749
2573 #define mmHUBPRET1_HUBPRET_MEM_PWR_CTRL_BASE_IDX                                                       2
2574 #define mmHUBPRET1_HUBPRET_MEM_PWR_STATUS                                                              0x074a
2575 #define mmHUBPRET1_HUBPRET_MEM_PWR_STATUS_BASE_IDX                                                     2
2576 #define mmHUBPRET1_HUBPRET_READ_LINE_CTRL0                                                             0x074b
2577 #define mmHUBPRET1_HUBPRET_READ_LINE_CTRL0_BASE_IDX                                                    2
2578 #define mmHUBPRET1_HUBPRET_READ_LINE_CTRL1                                                             0x074c
2579 #define mmHUBPRET1_HUBPRET_READ_LINE_CTRL1_BASE_IDX                                                    2
2580 #define mmHUBPRET1_HUBPRET_READ_LINE0                                                                  0x074d
2581 #define mmHUBPRET1_HUBPRET_READ_LINE0_BASE_IDX                                                         2
2582 #define mmHUBPRET1_HUBPRET_READ_LINE1                                                                  0x074e
2583 #define mmHUBPRET1_HUBPRET_READ_LINE1_BASE_IDX                                                         2
2584 #define mmHUBPRET1_HUBPRET_INTERRUPT                                                                   0x074f
2585 #define mmHUBPRET1_HUBPRET_INTERRUPT_BASE_IDX                                                          2
2586 #define mmHUBPRET1_HUBPRET_READ_LINE_VALUE                                                             0x0750
2587 #define mmHUBPRET1_HUBPRET_READ_LINE_VALUE_BASE_IDX                                                    2
2588 #define mmHUBPRET1_HUBPRET_READ_LINE_STATUS                                                            0x0751
2589 #define mmHUBPRET1_HUBPRET_READ_LINE_STATUS_BASE_IDX                                                   2
2590 
2591 
2592 // addressBlock: dce_dc_dcbubp1_dispdec_cursor0_dispdec
2593 // base address: 0x370
2594 #define mmCURSOR0_1_CURSOR_CONTROL                                                                     0x0754
2595 #define mmCURSOR0_1_CURSOR_CONTROL_BASE_IDX                                                            2
2596 #define mmCURSOR0_1_CURSOR_SURFACE_ADDRESS                                                             0x0755
2597 #define mmCURSOR0_1_CURSOR_SURFACE_ADDRESS_BASE_IDX                                                    2
2598 #define mmCURSOR0_1_CURSOR_SURFACE_ADDRESS_HIGH                                                        0x0756
2599 #define mmCURSOR0_1_CURSOR_SURFACE_ADDRESS_HIGH_BASE_IDX                                               2
2600 #define mmCURSOR0_1_CURSOR_SIZE                                                                        0x0757
2601 #define mmCURSOR0_1_CURSOR_SIZE_BASE_IDX                                                               2
2602 #define mmCURSOR0_1_CURSOR_POSITION                                                                    0x0758
2603 #define mmCURSOR0_1_CURSOR_POSITION_BASE_IDX                                                           2
2604 #define mmCURSOR0_1_CURSOR_HOT_SPOT                                                                    0x0759
2605 #define mmCURSOR0_1_CURSOR_HOT_SPOT_BASE_IDX                                                           2
2606 #define mmCURSOR0_1_CURSOR_STEREO_CONTROL                                                              0x075a
2607 #define mmCURSOR0_1_CURSOR_STEREO_CONTROL_BASE_IDX                                                     2
2608 #define mmCURSOR0_1_CURSOR_DST_OFFSET                                                                  0x075b
2609 #define mmCURSOR0_1_CURSOR_DST_OFFSET_BASE_IDX                                                         2
2610 #define mmCURSOR0_1_CURSOR_MEM_PWR_CTRL                                                                0x075c
2611 #define mmCURSOR0_1_CURSOR_MEM_PWR_CTRL_BASE_IDX                                                       2
2612 #define mmCURSOR0_1_CURSOR_MEM_PWR_STATUS                                                              0x075d
2613 #define mmCURSOR0_1_CURSOR_MEM_PWR_STATUS_BASE_IDX                                                     2
2614 #define mmCURSOR0_1_DMDATA_ADDRESS_HIGH                                                                0x075e
2615 #define mmCURSOR0_1_DMDATA_ADDRESS_HIGH_BASE_IDX                                                       2
2616 #define mmCURSOR0_1_DMDATA_ADDRESS_LOW                                                                 0x075f
2617 #define mmCURSOR0_1_DMDATA_ADDRESS_LOW_BASE_IDX                                                        2
2618 #define mmCURSOR0_1_DMDATA_CNTL                                                                        0x0760
2619 #define mmCURSOR0_1_DMDATA_CNTL_BASE_IDX                                                               2
2620 #define mmCURSOR0_1_DMDATA_QOS_CNTL                                                                    0x0761
2621 #define mmCURSOR0_1_DMDATA_QOS_CNTL_BASE_IDX                                                           2
2622 #define mmCURSOR0_1_DMDATA_STATUS                                                                      0x0762
2623 #define mmCURSOR0_1_DMDATA_STATUS_BASE_IDX                                                             2
2624 #define mmCURSOR0_1_DMDATA_SW_CNTL                                                                     0x0763
2625 #define mmCURSOR0_1_DMDATA_SW_CNTL_BASE_IDX                                                            2
2626 #define mmCURSOR0_1_DMDATA_SW_DATA                                                                     0x0764
2627 #define mmCURSOR0_1_DMDATA_SW_DATA_BASE_IDX                                                            2
2628 
2629 
2630 // addressBlock: dce_dc_dcbubp1_dispdec_hubp_dcperfmon_dc_perfmon_dispdec
2631 // base address: 0x1de4
2632 #define mmDC_PERFMON7_PERFCOUNTER_CNTL                                                                 0x0779
2633 #define mmDC_PERFMON7_PERFCOUNTER_CNTL_BASE_IDX                                                        2
2634 #define mmDC_PERFMON7_PERFCOUNTER_CNTL2                                                                0x077a
2635 #define mmDC_PERFMON7_PERFCOUNTER_CNTL2_BASE_IDX                                                       2
2636 #define mmDC_PERFMON7_PERFCOUNTER_STATE                                                                0x077b
2637 #define mmDC_PERFMON7_PERFCOUNTER_STATE_BASE_IDX                                                       2
2638 #define mmDC_PERFMON7_PERFMON_CNTL                                                                     0x077c
2639 #define mmDC_PERFMON7_PERFMON_CNTL_BASE_IDX                                                            2
2640 #define mmDC_PERFMON7_PERFMON_CNTL2                                                                    0x077d
2641 #define mmDC_PERFMON7_PERFMON_CNTL2_BASE_IDX                                                           2
2642 #define mmDC_PERFMON7_PERFMON_CVALUE_INT_MISC                                                          0x077e
2643 #define mmDC_PERFMON7_PERFMON_CVALUE_INT_MISC_BASE_IDX                                                 2
2644 #define mmDC_PERFMON7_PERFMON_CVALUE_LOW                                                               0x077f
2645 #define mmDC_PERFMON7_PERFMON_CVALUE_LOW_BASE_IDX                                                      2
2646 #define mmDC_PERFMON7_PERFMON_HI                                                                       0x0780
2647 #define mmDC_PERFMON7_PERFMON_HI_BASE_IDX                                                              2
2648 #define mmDC_PERFMON7_PERFMON_LOW                                                                      0x0781
2649 #define mmDC_PERFMON7_PERFMON_LOW_BASE_IDX                                                             2
2650 
2651 
2652 // addressBlock: dce_dc_dcbubp2_dispdec_hubp_dispdec
2653 // base address: 0x6e0
2654 #define mmHUBP2_DCSURF_SURFACE_CONFIG                                                                  0x079d
2655 #define mmHUBP2_DCSURF_SURFACE_CONFIG_BASE_IDX                                                         2
2656 #define mmHUBP2_DCSURF_ADDR_CONFIG                                                                     0x079e
2657 #define mmHUBP2_DCSURF_ADDR_CONFIG_BASE_IDX                                                            2
2658 #define mmHUBP2_DCSURF_TILING_CONFIG                                                                   0x079f
2659 #define mmHUBP2_DCSURF_TILING_CONFIG_BASE_IDX                                                          2
2660 #define mmHUBP2_DCSURF_PRI_VIEWPORT_START                                                              0x07a1
2661 #define mmHUBP2_DCSURF_PRI_VIEWPORT_START_BASE_IDX                                                     2
2662 #define mmHUBP2_DCSURF_PRI_VIEWPORT_DIMENSION                                                          0x07a2
2663 #define mmHUBP2_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX                                                 2
2664 #define mmHUBP2_DCSURF_PRI_VIEWPORT_START_C                                                            0x07a3
2665 #define mmHUBP2_DCSURF_PRI_VIEWPORT_START_C_BASE_IDX                                                   2
2666 #define mmHUBP2_DCSURF_PRI_VIEWPORT_DIMENSION_C                                                        0x07a4
2667 #define mmHUBP2_DCSURF_PRI_VIEWPORT_DIMENSION_C_BASE_IDX                                               2
2668 #define mmHUBP2_DCSURF_SEC_VIEWPORT_START                                                              0x07a5
2669 #define mmHUBP2_DCSURF_SEC_VIEWPORT_START_BASE_IDX                                                     2
2670 #define mmHUBP2_DCSURF_SEC_VIEWPORT_DIMENSION                                                          0x07a6
2671 #define mmHUBP2_DCSURF_SEC_VIEWPORT_DIMENSION_BASE_IDX                                                 2
2672 #define mmHUBP2_DCSURF_SEC_VIEWPORT_START_C                                                            0x07a7
2673 #define mmHUBP2_DCSURF_SEC_VIEWPORT_START_C_BASE_IDX                                                   2
2674 #define mmHUBP2_DCSURF_SEC_VIEWPORT_DIMENSION_C                                                        0x07a8
2675 #define mmHUBP2_DCSURF_SEC_VIEWPORT_DIMENSION_C_BASE_IDX                                               2
2676 #define mmHUBP2_DCHUBP_REQ_SIZE_CONFIG                                                                 0x07a9
2677 #define mmHUBP2_DCHUBP_REQ_SIZE_CONFIG_BASE_IDX                                                        2
2678 #define mmHUBP2_DCHUBP_REQ_SIZE_CONFIG_C                                                               0x07aa
2679 #define mmHUBP2_DCHUBP_REQ_SIZE_CONFIG_C_BASE_IDX                                                      2
2680 #define mmHUBP2_DCHUBP_CNTL                                                                            0x07ab
2681 #define mmHUBP2_DCHUBP_CNTL_BASE_IDX                                                                   2
2682 #define mmHUBP2_HUBP_CLK_CNTL                                                                          0x07ac
2683 #define mmHUBP2_HUBP_CLK_CNTL_BASE_IDX                                                                 2
2684 #define mmHUBP2_DCHUBP_VMPG_CONFIG                                                                     0x07ad
2685 #define mmHUBP2_DCHUBP_VMPG_CONFIG_BASE_IDX                                                            2
2686 #define mmHUBP2_HUBPREQ_DEBUG_DB                                                                       0x07ae
2687 #define mmHUBP2_HUBPREQ_DEBUG_DB_BASE_IDX                                                              2
2688 #define mmHUBP2_HUBPREQ_DEBUG                                                                          0x07af
2689 #define mmHUBP2_HUBPREQ_DEBUG_BASE_IDX                                                                 2
2690 #define mmHUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK                                                           0x07b3
2691 #define mmHUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK_BASE_IDX                                                  2
2692 #define mmHUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK                                                           0x07b4
2693 #define mmHUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK_BASE_IDX                                                  2
2694 
2695 
2696 // addressBlock: dce_dc_dcbubp2_dispdec_hubpreq_dispdec
2697 // base address: 0x6e0
2698 #define mmHUBPREQ2_DCSURF_SURFACE_PITCH                                                                0x07bf
2699 #define mmHUBPREQ2_DCSURF_SURFACE_PITCH_BASE_IDX                                                       2
2700 #define mmHUBPREQ2_DCSURF_SURFACE_PITCH_C                                                              0x07c0
2701 #define mmHUBPREQ2_DCSURF_SURFACE_PITCH_C_BASE_IDX                                                     2
2702 #define mmHUBPREQ2_VMID_SETTINGS_0                                                                     0x07c1
2703 #define mmHUBPREQ2_VMID_SETTINGS_0_BASE_IDX                                                            2
2704 #define mmHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS                                                      0x07c2
2705 #define mmHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_BASE_IDX                                             2
2706 #define mmHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH                                                 0x07c3
2707 #define mmHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX                                        2
2708 #define mmHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_C                                                    0x07c4
2709 #define mmHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_C_BASE_IDX                                           2
2710 #define mmHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C                                               0x07c5
2711 #define mmHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX                                      2
2712 #define mmHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS                                                    0x07c6
2713 #define mmHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_BASE_IDX                                           2
2714 #define mmHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH                                               0x07c7
2715 #define mmHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX                                      2
2716 #define mmHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_C                                                  0x07c8
2717 #define mmHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_C_BASE_IDX                                         2
2718 #define mmHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C                                             0x07c9
2719 #define mmHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX                                    2
2720 #define mmHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS                                                 0x07ca
2721 #define mmHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_BASE_IDX                                        2
2722 #define mmHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH                                            0x07cb
2723 #define mmHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX                                   2
2724 #define mmHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C                                               0x07cc
2725 #define mmHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C_BASE_IDX                                      2
2726 #define mmHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C                                          0x07cd
2727 #define mmHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX                                 2
2728 #define mmHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS                                               0x07ce
2729 #define mmHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_BASE_IDX                                      2
2730 #define mmHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH                                          0x07cf
2731 #define mmHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX                                 2
2732 #define mmHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C                                             0x07d0
2733 #define mmHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C_BASE_IDX                                    2
2734 #define mmHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C                                        0x07d1
2735 #define mmHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX                               2
2736 #define mmHUBPREQ2_DCSURF_SURFACE_CONTROL                                                              0x07d2
2737 #define mmHUBPREQ2_DCSURF_SURFACE_CONTROL_BASE_IDX                                                     2
2738 #define mmHUBPREQ2_DCSURF_FLIP_CONTROL                                                                 0x07d3
2739 #define mmHUBPREQ2_DCSURF_FLIP_CONTROL_BASE_IDX                                                        2
2740 #define mmHUBPREQ2_DCSURF_FLIP_CONTROL2                                                                0x07d4
2741 #define mmHUBPREQ2_DCSURF_FLIP_CONTROL2_BASE_IDX                                                       2
2742 #define mmHUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT                                                       0x07d8
2743 #define mmHUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT_BASE_IDX                                              2
2744 #define mmHUBPREQ2_DCSURF_SURFACE_INUSE                                                                0x07d9
2745 #define mmHUBPREQ2_DCSURF_SURFACE_INUSE_BASE_IDX                                                       2
2746 #define mmHUBPREQ2_DCSURF_SURFACE_INUSE_HIGH                                                           0x07da
2747 #define mmHUBPREQ2_DCSURF_SURFACE_INUSE_HIGH_BASE_IDX                                                  2
2748 #define mmHUBPREQ2_DCSURF_SURFACE_INUSE_C                                                              0x07db
2749 #define mmHUBPREQ2_DCSURF_SURFACE_INUSE_C_BASE_IDX                                                     2
2750 #define mmHUBPREQ2_DCSURF_SURFACE_INUSE_HIGH_C                                                         0x07dc
2751 #define mmHUBPREQ2_DCSURF_SURFACE_INUSE_HIGH_C_BASE_IDX                                                2
2752 #define mmHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE                                                       0x07dd
2753 #define mmHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_BASE_IDX                                              2
2754 #define mmHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH                                                  0x07de
2755 #define mmHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_BASE_IDX                                         2
2756 #define mmHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_C                                                     0x07df
2757 #define mmHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_C_BASE_IDX                                            2
2758 #define mmHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C                                                0x07e0
2759 #define mmHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C_BASE_IDX                                       2
2760 #define mmHUBPREQ2_DCN_EXPANSION_MODE                                                                  0x07e1
2761 #define mmHUBPREQ2_DCN_EXPANSION_MODE_BASE_IDX                                                         2
2762 #define mmHUBPREQ2_DCN_TTU_QOS_WM                                                                      0x07e2
2763 #define mmHUBPREQ2_DCN_TTU_QOS_WM_BASE_IDX                                                             2
2764 #define mmHUBPREQ2_DCN_GLOBAL_TTU_CNTL                                                                 0x07e3
2765 #define mmHUBPREQ2_DCN_GLOBAL_TTU_CNTL_BASE_IDX                                                        2
2766 #define mmHUBPREQ2_DCN_SURF0_TTU_CNTL0                                                                 0x07e4
2767 #define mmHUBPREQ2_DCN_SURF0_TTU_CNTL0_BASE_IDX                                                        2
2768 #define mmHUBPREQ2_DCN_SURF0_TTU_CNTL1                                                                 0x07e5
2769 #define mmHUBPREQ2_DCN_SURF0_TTU_CNTL1_BASE_IDX                                                        2
2770 #define mmHUBPREQ2_DCN_SURF1_TTU_CNTL0                                                                 0x07e6
2771 #define mmHUBPREQ2_DCN_SURF1_TTU_CNTL0_BASE_IDX                                                        2
2772 #define mmHUBPREQ2_DCN_SURF1_TTU_CNTL1                                                                 0x07e7
2773 #define mmHUBPREQ2_DCN_SURF1_TTU_CNTL1_BASE_IDX                                                        2
2774 #define mmHUBPREQ2_DCN_CUR0_TTU_CNTL0                                                                  0x07e8
2775 #define mmHUBPREQ2_DCN_CUR0_TTU_CNTL0_BASE_IDX                                                         2
2776 #define mmHUBPREQ2_DCN_CUR0_TTU_CNTL1                                                                  0x07e9
2777 #define mmHUBPREQ2_DCN_CUR0_TTU_CNTL1_BASE_IDX                                                         2
2778 #define mmHUBPREQ2_DCN_CUR1_TTU_CNTL0                                                                  0x07ea
2779 #define mmHUBPREQ2_DCN_CUR1_TTU_CNTL0_BASE_IDX                                                         2
2780 #define mmHUBPREQ2_DCN_CUR1_TTU_CNTL1                                                                  0x07eb
2781 #define mmHUBPREQ2_DCN_CUR1_TTU_CNTL1_BASE_IDX                                                         2
2782 #define mmHUBPREQ2_DCN_DMDATA_VM_CNTL                                                                  0x07ec
2783 #define mmHUBPREQ2_DCN_DMDATA_VM_CNTL_BASE_IDX                                                         2
2784 #define mmHUBPREQ2_DCN_VM_SYSTEM_APERTURE_LOW_ADDR                                                     0x07ed
2785 #define mmHUBPREQ2_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_BASE_IDX                                            2
2786 #define mmHUBPREQ2_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR                                                    0x07ee
2787 #define mmHUBPREQ2_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_BASE_IDX                                           2
2788 #define mmHUBPREQ2_DCN_VM_MX_L1_TLB_CNTL                                                               0x07fb
2789 #define mmHUBPREQ2_DCN_VM_MX_L1_TLB_CNTL_BASE_IDX                                                      2
2790 #define mmHUBPREQ2_BLANK_OFFSET_0                                                                      0x07fc
2791 #define mmHUBPREQ2_BLANK_OFFSET_0_BASE_IDX                                                             2
2792 #define mmHUBPREQ2_BLANK_OFFSET_1                                                                      0x07fd
2793 #define mmHUBPREQ2_BLANK_OFFSET_1_BASE_IDX                                                             2
2794 #define mmHUBPREQ2_DST_DIMENSIONS                                                                      0x07fe
2795 #define mmHUBPREQ2_DST_DIMENSIONS_BASE_IDX                                                             2
2796 #define mmHUBPREQ2_DST_AFTER_SCALER                                                                    0x07ff
2797 #define mmHUBPREQ2_DST_AFTER_SCALER_BASE_IDX                                                           2
2798 #define mmHUBPREQ2_PREFETCH_SETTINGS                                                                   0x0800
2799 #define mmHUBPREQ2_PREFETCH_SETTINGS_BASE_IDX                                                          2
2800 #define mmHUBPREQ2_PREFETCH_SETTINGS_C                                                                 0x0801
2801 #define mmHUBPREQ2_PREFETCH_SETTINGS_C_BASE_IDX                                                        2
2802 #define mmHUBPREQ2_VBLANK_PARAMETERS_0                                                                 0x0802
2803 #define mmHUBPREQ2_VBLANK_PARAMETERS_0_BASE_IDX                                                        2
2804 #define mmHUBPREQ2_VBLANK_PARAMETERS_1                                                                 0x0803
2805 #define mmHUBPREQ2_VBLANK_PARAMETERS_1_BASE_IDX                                                        2
2806 #define mmHUBPREQ2_VBLANK_PARAMETERS_2                                                                 0x0804
2807 #define mmHUBPREQ2_VBLANK_PARAMETERS_2_BASE_IDX                                                        2
2808 #define mmHUBPREQ2_VBLANK_PARAMETERS_3                                                                 0x0805
2809 #define mmHUBPREQ2_VBLANK_PARAMETERS_3_BASE_IDX                                                        2
2810 #define mmHUBPREQ2_VBLANK_PARAMETERS_4                                                                 0x0806
2811 #define mmHUBPREQ2_VBLANK_PARAMETERS_4_BASE_IDX                                                        2
2812 #define mmHUBPREQ2_FLIP_PARAMETERS_0                                                                   0x0807
2813 #define mmHUBPREQ2_FLIP_PARAMETERS_0_BASE_IDX                                                          2
2814 #define mmHUBPREQ2_FLIP_PARAMETERS_1                                                                   0x0808
2815 #define mmHUBPREQ2_FLIP_PARAMETERS_1_BASE_IDX                                                          2
2816 #define mmHUBPREQ2_FLIP_PARAMETERS_2                                                                   0x0809
2817 #define mmHUBPREQ2_FLIP_PARAMETERS_2_BASE_IDX                                                          2
2818 #define mmHUBPREQ2_NOM_PARAMETERS_0                                                                    0x080a
2819 #define mmHUBPREQ2_NOM_PARAMETERS_0_BASE_IDX                                                           2
2820 #define mmHUBPREQ2_NOM_PARAMETERS_1                                                                    0x080b
2821 #define mmHUBPREQ2_NOM_PARAMETERS_1_BASE_IDX                                                           2
2822 #define mmHUBPREQ2_NOM_PARAMETERS_2                                                                    0x080c
2823 #define mmHUBPREQ2_NOM_PARAMETERS_2_BASE_IDX                                                           2
2824 #define mmHUBPREQ2_NOM_PARAMETERS_3                                                                    0x080d
2825 #define mmHUBPREQ2_NOM_PARAMETERS_3_BASE_IDX                                                           2
2826 #define mmHUBPREQ2_NOM_PARAMETERS_4                                                                    0x080e
2827 #define mmHUBPREQ2_NOM_PARAMETERS_4_BASE_IDX                                                           2
2828 #define mmHUBPREQ2_NOM_PARAMETERS_5                                                                    0x080f
2829 #define mmHUBPREQ2_NOM_PARAMETERS_5_BASE_IDX                                                           2
2830 #define mmHUBPREQ2_NOM_PARAMETERS_6                                                                    0x0810
2831 #define mmHUBPREQ2_NOM_PARAMETERS_6_BASE_IDX                                                           2
2832 #define mmHUBPREQ2_NOM_PARAMETERS_7                                                                    0x0811
2833 #define mmHUBPREQ2_NOM_PARAMETERS_7_BASE_IDX                                                           2
2834 #define mmHUBPREQ2_PER_LINE_DELIVERY_PRE                                                               0x0812
2835 #define mmHUBPREQ2_PER_LINE_DELIVERY_PRE_BASE_IDX                                                      2
2836 #define mmHUBPREQ2_PER_LINE_DELIVERY                                                                   0x0813
2837 #define mmHUBPREQ2_PER_LINE_DELIVERY_BASE_IDX                                                          2
2838 #define mmHUBPREQ2_CURSOR_SETTINGS                                                                     0x0814
2839 #define mmHUBPREQ2_CURSOR_SETTINGS_BASE_IDX                                                            2
2840 #define mmHUBPREQ2_REF_FREQ_TO_PIX_FREQ                                                                0x0815
2841 #define mmHUBPREQ2_REF_FREQ_TO_PIX_FREQ_BASE_IDX                                                       2
2842 #define mmHUBPREQ2_DST_Y_DELTA_DRQ_LIMIT                                                               0x0816
2843 #define mmHUBPREQ2_DST_Y_DELTA_DRQ_LIMIT_BASE_IDX                                                      2
2844 #define mmHUBPREQ2_HUBPREQ_MEM_PWR_CTRL                                                                0x0817
2845 #define mmHUBPREQ2_HUBPREQ_MEM_PWR_CTRL_BASE_IDX                                                       2
2846 #define mmHUBPREQ2_HUBPREQ_MEM_PWR_STATUS                                                              0x0818
2847 #define mmHUBPREQ2_HUBPREQ_MEM_PWR_STATUS_BASE_IDX                                                     2
2848 #define mmHUBPREQ2_VBLANK_PARAMETERS_5                                                                 0x081b
2849 #define mmHUBPREQ2_VBLANK_PARAMETERS_5_BASE_IDX                                                        2
2850 #define mmHUBPREQ2_VBLANK_PARAMETERS_6                                                                 0x081c
2851 #define mmHUBPREQ2_VBLANK_PARAMETERS_6_BASE_IDX                                                        2
2852 #define mmHUBPREQ2_FLIP_PARAMETERS_3                                                                   0x081d
2853 #define mmHUBPREQ2_FLIP_PARAMETERS_3_BASE_IDX                                                          2
2854 #define mmHUBPREQ2_FLIP_PARAMETERS_4                                                                   0x081e
2855 #define mmHUBPREQ2_FLIP_PARAMETERS_4_BASE_IDX                                                          2
2856 #define mmHUBPREQ2_FLIP_PARAMETERS_5                                                                   0x081f
2857 #define mmHUBPREQ2_FLIP_PARAMETERS_5_BASE_IDX                                                          2
2858 #define mmHUBPREQ2_FLIP_PARAMETERS_6                                                                   0x0820
2859 #define mmHUBPREQ2_FLIP_PARAMETERS_6_BASE_IDX                                                          2
2860 
2861 
2862 // addressBlock: dce_dc_dcbubp2_dispdec_hubpret_dispdec
2863 // base address: 0x6e0
2864 #define mmHUBPRET2_HUBPRET_CONTROL                                                                     0x0824
2865 #define mmHUBPRET2_HUBPRET_CONTROL_BASE_IDX                                                            2
2866 #define mmHUBPRET2_HUBPRET_MEM_PWR_CTRL                                                                0x0825
2867 #define mmHUBPRET2_HUBPRET_MEM_PWR_CTRL_BASE_IDX                                                       2
2868 #define mmHUBPRET2_HUBPRET_MEM_PWR_STATUS                                                              0x0826
2869 #define mmHUBPRET2_HUBPRET_MEM_PWR_STATUS_BASE_IDX                                                     2
2870 #define mmHUBPRET2_HUBPRET_READ_LINE_CTRL0                                                             0x0827
2871 #define mmHUBPRET2_HUBPRET_READ_LINE_CTRL0_BASE_IDX                                                    2
2872 #define mmHUBPRET2_HUBPRET_READ_LINE_CTRL1                                                             0x0828
2873 #define mmHUBPRET2_HUBPRET_READ_LINE_CTRL1_BASE_IDX                                                    2
2874 #define mmHUBPRET2_HUBPRET_READ_LINE0                                                                  0x0829
2875 #define mmHUBPRET2_HUBPRET_READ_LINE0_BASE_IDX                                                         2
2876 #define mmHUBPRET2_HUBPRET_READ_LINE1                                                                  0x082a
2877 #define mmHUBPRET2_HUBPRET_READ_LINE1_BASE_IDX                                                         2
2878 #define mmHUBPRET2_HUBPRET_INTERRUPT                                                                   0x082b
2879 #define mmHUBPRET2_HUBPRET_INTERRUPT_BASE_IDX                                                          2
2880 #define mmHUBPRET2_HUBPRET_READ_LINE_VALUE                                                             0x082c
2881 #define mmHUBPRET2_HUBPRET_READ_LINE_VALUE_BASE_IDX                                                    2
2882 #define mmHUBPRET2_HUBPRET_READ_LINE_STATUS                                                            0x082d
2883 #define mmHUBPRET2_HUBPRET_READ_LINE_STATUS_BASE_IDX                                                   2
2884 
2885 
2886 // addressBlock: dce_dc_dcbubp2_dispdec_cursor0_dispdec
2887 // base address: 0x6e0
2888 #define mmCURSOR0_2_CURSOR_CONTROL                                                                     0x0830
2889 #define mmCURSOR0_2_CURSOR_CONTROL_BASE_IDX                                                            2
2890 #define mmCURSOR0_2_CURSOR_SURFACE_ADDRESS                                                             0x0831
2891 #define mmCURSOR0_2_CURSOR_SURFACE_ADDRESS_BASE_IDX                                                    2
2892 #define mmCURSOR0_2_CURSOR_SURFACE_ADDRESS_HIGH                                                        0x0832
2893 #define mmCURSOR0_2_CURSOR_SURFACE_ADDRESS_HIGH_BASE_IDX                                               2
2894 #define mmCURSOR0_2_CURSOR_SIZE                                                                        0x0833
2895 #define mmCURSOR0_2_CURSOR_SIZE_BASE_IDX                                                               2
2896 #define mmCURSOR0_2_CURSOR_POSITION                                                                    0x0834
2897 #define mmCURSOR0_2_CURSOR_POSITION_BASE_IDX                                                           2
2898 #define mmCURSOR0_2_CURSOR_HOT_SPOT                                                                    0x0835
2899 #define mmCURSOR0_2_CURSOR_HOT_SPOT_BASE_IDX                                                           2
2900 #define mmCURSOR0_2_CURSOR_STEREO_CONTROL                                                              0x0836
2901 #define mmCURSOR0_2_CURSOR_STEREO_CONTROL_BASE_IDX                                                     2
2902 #define mmCURSOR0_2_CURSOR_DST_OFFSET                                                                  0x0837
2903 #define mmCURSOR0_2_CURSOR_DST_OFFSET_BASE_IDX                                                         2
2904 #define mmCURSOR0_2_CURSOR_MEM_PWR_CTRL                                                                0x0838
2905 #define mmCURSOR0_2_CURSOR_MEM_PWR_CTRL_BASE_IDX                                                       2
2906 #define mmCURSOR0_2_CURSOR_MEM_PWR_STATUS                                                              0x0839
2907 #define mmCURSOR0_2_CURSOR_MEM_PWR_STATUS_BASE_IDX                                                     2
2908 #define mmCURSOR0_2_DMDATA_ADDRESS_HIGH                                                                0x083a
2909 #define mmCURSOR0_2_DMDATA_ADDRESS_HIGH_BASE_IDX                                                       2
2910 #define mmCURSOR0_2_DMDATA_ADDRESS_LOW                                                                 0x083b
2911 #define mmCURSOR0_2_DMDATA_ADDRESS_LOW_BASE_IDX                                                        2
2912 #define mmCURSOR0_2_DMDATA_CNTL                                                                        0x083c
2913 #define mmCURSOR0_2_DMDATA_CNTL_BASE_IDX                                                               2
2914 #define mmCURSOR0_2_DMDATA_QOS_CNTL                                                                    0x083d
2915 #define mmCURSOR0_2_DMDATA_QOS_CNTL_BASE_IDX                                                           2
2916 #define mmCURSOR0_2_DMDATA_STATUS                                                                      0x083e
2917 #define mmCURSOR0_2_DMDATA_STATUS_BASE_IDX                                                             2
2918 #define mmCURSOR0_2_DMDATA_SW_CNTL                                                                     0x083f
2919 #define mmCURSOR0_2_DMDATA_SW_CNTL_BASE_IDX                                                            2
2920 #define mmCURSOR0_2_DMDATA_SW_DATA                                                                     0x0840
2921 #define mmCURSOR0_2_DMDATA_SW_DATA_BASE_IDX                                                            2
2922 
2923 
2924 // addressBlock: dce_dc_dcbubp2_dispdec_hubp_dcperfmon_dc_perfmon_dispdec
2925 // base address: 0x2154
2926 #define mmDC_PERFMON8_PERFCOUNTER_CNTL                                                                 0x0855
2927 #define mmDC_PERFMON8_PERFCOUNTER_CNTL_BASE_IDX                                                        2
2928 #define mmDC_PERFMON8_PERFCOUNTER_CNTL2                                                                0x0856
2929 #define mmDC_PERFMON8_PERFCOUNTER_CNTL2_BASE_IDX                                                       2
2930 #define mmDC_PERFMON8_PERFCOUNTER_STATE                                                                0x0857
2931 #define mmDC_PERFMON8_PERFCOUNTER_STATE_BASE_IDX                                                       2
2932 #define mmDC_PERFMON8_PERFMON_CNTL                                                                     0x0858
2933 #define mmDC_PERFMON8_PERFMON_CNTL_BASE_IDX                                                            2
2934 #define mmDC_PERFMON8_PERFMON_CNTL2                                                                    0x0859
2935 #define mmDC_PERFMON8_PERFMON_CNTL2_BASE_IDX                                                           2
2936 #define mmDC_PERFMON8_PERFMON_CVALUE_INT_MISC                                                          0x085a
2937 #define mmDC_PERFMON8_PERFMON_CVALUE_INT_MISC_BASE_IDX                                                 2
2938 #define mmDC_PERFMON8_PERFMON_CVALUE_LOW                                                               0x085b
2939 #define mmDC_PERFMON8_PERFMON_CVALUE_LOW_BASE_IDX                                                      2
2940 #define mmDC_PERFMON8_PERFMON_HI                                                                       0x085c
2941 #define mmDC_PERFMON8_PERFMON_HI_BASE_IDX                                                              2
2942 #define mmDC_PERFMON8_PERFMON_LOW                                                                      0x085d
2943 #define mmDC_PERFMON8_PERFMON_LOW_BASE_IDX                                                             2
2944 
2945 
2946 // addressBlock: dce_dc_dcbubp3_dispdec_hubp_dispdec
2947 // base address: 0xa50
2948 #define mmHUBP3_DCSURF_SURFACE_CONFIG                                                                  0x0879
2949 #define mmHUBP3_DCSURF_SURFACE_CONFIG_BASE_IDX                                                         2
2950 #define mmHUBP3_DCSURF_ADDR_CONFIG                                                                     0x087a
2951 #define mmHUBP3_DCSURF_ADDR_CONFIG_BASE_IDX                                                            2
2952 #define mmHUBP3_DCSURF_TILING_CONFIG                                                                   0x087b
2953 #define mmHUBP3_DCSURF_TILING_CONFIG_BASE_IDX                                                          2
2954 #define mmHUBP3_DCSURF_PRI_VIEWPORT_START                                                              0x087d
2955 #define mmHUBP3_DCSURF_PRI_VIEWPORT_START_BASE_IDX                                                     2
2956 #define mmHUBP3_DCSURF_PRI_VIEWPORT_DIMENSION                                                          0x087e
2957 #define mmHUBP3_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX                                                 2
2958 #define mmHUBP3_DCSURF_PRI_VIEWPORT_START_C                                                            0x087f
2959 #define mmHUBP3_DCSURF_PRI_VIEWPORT_START_C_BASE_IDX                                                   2
2960 #define mmHUBP3_DCSURF_PRI_VIEWPORT_DIMENSION_C                                                        0x0880
2961 #define mmHUBP3_DCSURF_PRI_VIEWPORT_DIMENSION_C_BASE_IDX                                               2
2962 #define mmHUBP3_DCSURF_SEC_VIEWPORT_START                                                              0x0881
2963 #define mmHUBP3_DCSURF_SEC_VIEWPORT_START_BASE_IDX                                                     2
2964 #define mmHUBP3_DCSURF_SEC_VIEWPORT_DIMENSION                                                          0x0882
2965 #define mmHUBP3_DCSURF_SEC_VIEWPORT_DIMENSION_BASE_IDX                                                 2
2966 #define mmHUBP3_DCSURF_SEC_VIEWPORT_START_C                                                            0x0883
2967 #define mmHUBP3_DCSURF_SEC_VIEWPORT_START_C_BASE_IDX                                                   2
2968 #define mmHUBP3_DCSURF_SEC_VIEWPORT_DIMENSION_C                                                        0x0884
2969 #define mmHUBP3_DCSURF_SEC_VIEWPORT_DIMENSION_C_BASE_IDX                                               2
2970 #define mmHUBP3_DCHUBP_REQ_SIZE_CONFIG                                                                 0x0885
2971 #define mmHUBP3_DCHUBP_REQ_SIZE_CONFIG_BASE_IDX                                                        2
2972 #define mmHUBP3_DCHUBP_REQ_SIZE_CONFIG_C                                                               0x0886
2973 #define mmHUBP3_DCHUBP_REQ_SIZE_CONFIG_C_BASE_IDX                                                      2
2974 #define mmHUBP3_DCHUBP_CNTL                                                                            0x0887
2975 #define mmHUBP3_DCHUBP_CNTL_BASE_IDX                                                                   2
2976 #define mmHUBP3_HUBP_CLK_CNTL                                                                          0x0888
2977 #define mmHUBP3_HUBP_CLK_CNTL_BASE_IDX                                                                 2
2978 #define mmHUBP3_DCHUBP_VMPG_CONFIG                                                                     0x0889
2979 #define mmHUBP3_DCHUBP_VMPG_CONFIG_BASE_IDX                                                            2
2980 #define mmHUBP3_HUBPREQ_DEBUG_DB                                                                       0x088a
2981 #define mmHUBP3_HUBPREQ_DEBUG_DB_BASE_IDX                                                              2
2982 #define mmHUBP3_HUBPREQ_DEBUG                                                                          0x088b
2983 #define mmHUBP3_HUBPREQ_DEBUG_BASE_IDX                                                                 2
2984 #define mmHUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK                                                           0x088f
2985 #define mmHUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK_BASE_IDX                                                  2
2986 #define mmHUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK                                                           0x0890
2987 #define mmHUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK_BASE_IDX                                                  2
2988 
2989 
2990 // addressBlock: dce_dc_dcbubp3_dispdec_hubpreq_dispdec
2991 // base address: 0xa50
2992 #define mmHUBPREQ3_DCSURF_SURFACE_PITCH                                                                0x089b
2993 #define mmHUBPREQ3_DCSURF_SURFACE_PITCH_BASE_IDX                                                       2
2994 #define mmHUBPREQ3_DCSURF_SURFACE_PITCH_C                                                              0x089c
2995 #define mmHUBPREQ3_DCSURF_SURFACE_PITCH_C_BASE_IDX                                                     2
2996 #define mmHUBPREQ3_VMID_SETTINGS_0                                                                     0x089d
2997 #define mmHUBPREQ3_VMID_SETTINGS_0_BASE_IDX                                                            2
2998 #define mmHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS                                                      0x089e
2999 #define mmHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_BASE_IDX                                             2
3000 #define mmHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH                                                 0x089f
3001 #define mmHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX                                        2
3002 #define mmHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_C                                                    0x08a0
3003 #define mmHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_C_BASE_IDX                                           2
3004 #define mmHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C                                               0x08a1
3005 #define mmHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX                                      2
3006 #define mmHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS                                                    0x08a2
3007 #define mmHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_BASE_IDX                                           2
3008 #define mmHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH                                               0x08a3
3009 #define mmHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX                                      2
3010 #define mmHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_C                                                  0x08a4
3011 #define mmHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_C_BASE_IDX                                         2
3012 #define mmHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C                                             0x08a5
3013 #define mmHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX                                    2
3014 #define mmHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS                                                 0x08a6
3015 #define mmHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_BASE_IDX                                        2
3016 #define mmHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH                                            0x08a7
3017 #define mmHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX                                   2
3018 #define mmHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C                                               0x08a8
3019 #define mmHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C_BASE_IDX                                      2
3020 #define mmHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C                                          0x08a9
3021 #define mmHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX                                 2
3022 #define mmHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS                                               0x08aa
3023 #define mmHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_BASE_IDX                                      2
3024 #define mmHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH                                          0x08ab
3025 #define mmHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX                                 2
3026 #define mmHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C                                             0x08ac
3027 #define mmHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C_BASE_IDX                                    2
3028 #define mmHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C                                        0x08ad
3029 #define mmHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX                               2
3030 #define mmHUBPREQ3_DCSURF_SURFACE_CONTROL                                                              0x08ae
3031 #define mmHUBPREQ3_DCSURF_SURFACE_CONTROL_BASE_IDX                                                     2
3032 #define mmHUBPREQ3_DCSURF_FLIP_CONTROL                                                                 0x08af
3033 #define mmHUBPREQ3_DCSURF_FLIP_CONTROL_BASE_IDX                                                        2
3034 #define mmHUBPREQ3_DCSURF_FLIP_CONTROL2                                                                0x08b0
3035 #define mmHUBPREQ3_DCSURF_FLIP_CONTROL2_BASE_IDX                                                       2
3036 #define mmHUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT                                                       0x08b4
3037 #define mmHUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT_BASE_IDX                                              2
3038 #define mmHUBPREQ3_DCSURF_SURFACE_INUSE                                                                0x08b5
3039 #define mmHUBPREQ3_DCSURF_SURFACE_INUSE_BASE_IDX                                                       2
3040 #define mmHUBPREQ3_DCSURF_SURFACE_INUSE_HIGH                                                           0x08b6
3041 #define mmHUBPREQ3_DCSURF_SURFACE_INUSE_HIGH_BASE_IDX                                                  2
3042 #define mmHUBPREQ3_DCSURF_SURFACE_INUSE_C                                                              0x08b7
3043 #define mmHUBPREQ3_DCSURF_SURFACE_INUSE_C_BASE_IDX                                                     2
3044 #define mmHUBPREQ3_DCSURF_SURFACE_INUSE_HIGH_C                                                         0x08b8
3045 #define mmHUBPREQ3_DCSURF_SURFACE_INUSE_HIGH_C_BASE_IDX                                                2
3046 #define mmHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE                                                       0x08b9
3047 #define mmHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_BASE_IDX                                              2
3048 #define mmHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH                                                  0x08ba
3049 #define mmHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_BASE_IDX                                         2
3050 #define mmHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_C                                                     0x08bb
3051 #define mmHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_C_BASE_IDX                                            2
3052 #define mmHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C                                                0x08bc
3053 #define mmHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C_BASE_IDX                                       2
3054 #define mmHUBPREQ3_DCN_EXPANSION_MODE                                                                  0x08bd
3055 #define mmHUBPREQ3_DCN_EXPANSION_MODE_BASE_IDX                                                         2
3056 #define mmHUBPREQ3_DCN_TTU_QOS_WM                                                                      0x08be
3057 #define mmHUBPREQ3_DCN_TTU_QOS_WM_BASE_IDX                                                             2
3058 #define mmHUBPREQ3_DCN_GLOBAL_TTU_CNTL                                                                 0x08bf
3059 #define mmHUBPREQ3_DCN_GLOBAL_TTU_CNTL_BASE_IDX                                                        2
3060 #define mmHUBPREQ3_DCN_SURF0_TTU_CNTL0                                                                 0x08c0
3061 #define mmHUBPREQ3_DCN_SURF0_TTU_CNTL0_BASE_IDX                                                        2
3062 #define mmHUBPREQ3_DCN_SURF0_TTU_CNTL1                                                                 0x08c1
3063 #define mmHUBPREQ3_DCN_SURF0_TTU_CNTL1_BASE_IDX                                                        2
3064 #define mmHUBPREQ3_DCN_SURF1_TTU_CNTL0                                                                 0x08c2
3065 #define mmHUBPREQ3_DCN_SURF1_TTU_CNTL0_BASE_IDX                                                        2
3066 #define mmHUBPREQ3_DCN_SURF1_TTU_CNTL1                                                                 0x08c3
3067 #define mmHUBPREQ3_DCN_SURF1_TTU_CNTL1_BASE_IDX                                                        2
3068 #define mmHUBPREQ3_DCN_CUR0_TTU_CNTL0                                                                  0x08c4
3069 #define mmHUBPREQ3_DCN_CUR0_TTU_CNTL0_BASE_IDX                                                         2
3070 #define mmHUBPREQ3_DCN_CUR0_TTU_CNTL1                                                                  0x08c5
3071 #define mmHUBPREQ3_DCN_CUR0_TTU_CNTL1_BASE_IDX                                                         2
3072 #define mmHUBPREQ3_DCN_CUR1_TTU_CNTL0                                                                  0x08c6
3073 #define mmHUBPREQ3_DCN_CUR1_TTU_CNTL0_BASE_IDX                                                         2
3074 #define mmHUBPREQ3_DCN_CUR1_TTU_CNTL1                                                                  0x08c7
3075 #define mmHUBPREQ3_DCN_CUR1_TTU_CNTL1_BASE_IDX                                                         2
3076 #define mmHUBPREQ3_DCN_DMDATA_VM_CNTL                                                                  0x08c8
3077 #define mmHUBPREQ3_DCN_DMDATA_VM_CNTL_BASE_IDX                                                         2
3078 #define mmHUBPREQ3_DCN_VM_SYSTEM_APERTURE_LOW_ADDR                                                     0x08c9
3079 #define mmHUBPREQ3_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_BASE_IDX                                            2
3080 #define mmHUBPREQ3_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR                                                    0x08ca
3081 #define mmHUBPREQ3_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_BASE_IDX                                           2
3082 #define mmHUBPREQ3_DCN_VM_MX_L1_TLB_CNTL                                                               0x08d7
3083 #define mmHUBPREQ3_DCN_VM_MX_L1_TLB_CNTL_BASE_IDX                                                      2
3084 #define mmHUBPREQ3_BLANK_OFFSET_0                                                                      0x08d8
3085 #define mmHUBPREQ3_BLANK_OFFSET_0_BASE_IDX                                                             2
3086 #define mmHUBPREQ3_BLANK_OFFSET_1                                                                      0x08d9
3087 #define mmHUBPREQ3_BLANK_OFFSET_1_BASE_IDX                                                             2
3088 #define mmHUBPREQ3_DST_DIMENSIONS                                                                      0x08da
3089 #define mmHUBPREQ3_DST_DIMENSIONS_BASE_IDX                                                             2
3090 #define mmHUBPREQ3_DST_AFTER_SCALER                                                                    0x08db
3091 #define mmHUBPREQ3_DST_AFTER_SCALER_BASE_IDX                                                           2
3092 #define mmHUBPREQ3_PREFETCH_SETTINGS                                                                   0x08dc
3093 #define mmHUBPREQ3_PREFETCH_SETTINGS_BASE_IDX                                                          2
3094 #define mmHUBPREQ3_PREFETCH_SETTINGS_C                                                                 0x08dd
3095 #define mmHUBPREQ3_PREFETCH_SETTINGS_C_BASE_IDX                                                        2
3096 #define mmHUBPREQ3_VBLANK_PARAMETERS_0                                                                 0x08de
3097 #define mmHUBPREQ3_VBLANK_PARAMETERS_0_BASE_IDX                                                        2
3098 #define mmHUBPREQ3_VBLANK_PARAMETERS_1                                                                 0x08df
3099 #define mmHUBPREQ3_VBLANK_PARAMETERS_1_BASE_IDX                                                        2
3100 #define mmHUBPREQ3_VBLANK_PARAMETERS_2                                                                 0x08e0
3101 #define mmHUBPREQ3_VBLANK_PARAMETERS_2_BASE_IDX                                                        2
3102 #define mmHUBPREQ3_VBLANK_PARAMETERS_3                                                                 0x08e1
3103 #define mmHUBPREQ3_VBLANK_PARAMETERS_3_BASE_IDX                                                        2
3104 #define mmHUBPREQ3_VBLANK_PARAMETERS_4                                                                 0x08e2
3105 #define mmHUBPREQ3_VBLANK_PARAMETERS_4_BASE_IDX                                                        2
3106 #define mmHUBPREQ3_FLIP_PARAMETERS_0                                                                   0x08e3
3107 #define mmHUBPREQ3_FLIP_PARAMETERS_0_BASE_IDX                                                          2
3108 #define mmHUBPREQ3_FLIP_PARAMETERS_1                                                                   0x08e4
3109 #define mmHUBPREQ3_FLIP_PARAMETERS_1_BASE_IDX                                                          2
3110 #define mmHUBPREQ3_FLIP_PARAMETERS_2                                                                   0x08e5
3111 #define mmHUBPREQ3_FLIP_PARAMETERS_2_BASE_IDX                                                          2
3112 #define mmHUBPREQ3_NOM_PARAMETERS_0                                                                    0x08e6
3113 #define mmHUBPREQ3_NOM_PARAMETERS_0_BASE_IDX                                                           2
3114 #define mmHUBPREQ3_NOM_PARAMETERS_1                                                                    0x08e7
3115 #define mmHUBPREQ3_NOM_PARAMETERS_1_BASE_IDX                                                           2
3116 #define mmHUBPREQ3_NOM_PARAMETERS_2                                                                    0x08e8
3117 #define mmHUBPREQ3_NOM_PARAMETERS_2_BASE_IDX                                                           2
3118 #define mmHUBPREQ3_NOM_PARAMETERS_3                                                                    0x08e9
3119 #define mmHUBPREQ3_NOM_PARAMETERS_3_BASE_IDX                                                           2
3120 #define mmHUBPREQ3_NOM_PARAMETERS_4                                                                    0x08ea
3121 #define mmHUBPREQ3_NOM_PARAMETERS_4_BASE_IDX                                                           2
3122 #define mmHUBPREQ3_NOM_PARAMETERS_5                                                                    0x08eb
3123 #define mmHUBPREQ3_NOM_PARAMETERS_5_BASE_IDX                                                           2
3124 #define mmHUBPREQ3_NOM_PARAMETERS_6                                                                    0x08ec
3125 #define mmHUBPREQ3_NOM_PARAMETERS_6_BASE_IDX                                                           2
3126 #define mmHUBPREQ3_NOM_PARAMETERS_7                                                                    0x08ed
3127 #define mmHUBPREQ3_NOM_PARAMETERS_7_BASE_IDX                                                           2
3128 #define mmHUBPREQ3_PER_LINE_DELIVERY_PRE                                                               0x08ee
3129 #define mmHUBPREQ3_PER_LINE_DELIVERY_PRE_BASE_IDX                                                      2
3130 #define mmHUBPREQ3_PER_LINE_DELIVERY                                                                   0x08ef
3131 #define mmHUBPREQ3_PER_LINE_DELIVERY_BASE_IDX                                                          2
3132 #define mmHUBPREQ3_CURSOR_SETTINGS                                                                     0x08f0
3133 #define mmHUBPREQ3_CURSOR_SETTINGS_BASE_IDX                                                            2
3134 #define mmHUBPREQ3_REF_FREQ_TO_PIX_FREQ                                                                0x08f1
3135 #define mmHUBPREQ3_REF_FREQ_TO_PIX_FREQ_BASE_IDX                                                       2
3136 #define mmHUBPREQ3_DST_Y_DELTA_DRQ_LIMIT                                                               0x08f2
3137 #define mmHUBPREQ3_DST_Y_DELTA_DRQ_LIMIT_BASE_IDX                                                      2
3138 #define mmHUBPREQ3_HUBPREQ_MEM_PWR_CTRL                                                                0x08f3
3139 #define mmHUBPREQ3_HUBPREQ_MEM_PWR_CTRL_BASE_IDX                                                       2
3140 #define mmHUBPREQ3_HUBPREQ_MEM_PWR_STATUS                                                              0x08f4
3141 #define mmHUBPREQ3_HUBPREQ_MEM_PWR_STATUS_BASE_IDX                                                     2
3142 #define mmHUBPREQ3_VBLANK_PARAMETERS_5                                                                 0x08f7
3143 #define mmHUBPREQ3_VBLANK_PARAMETERS_5_BASE_IDX                                                        2
3144 #define mmHUBPREQ3_VBLANK_PARAMETERS_6                                                                 0x08f8
3145 #define mmHUBPREQ3_VBLANK_PARAMETERS_6_BASE_IDX                                                        2
3146 #define mmHUBPREQ3_FLIP_PARAMETERS_3                                                                   0x08f9
3147 #define mmHUBPREQ3_FLIP_PARAMETERS_3_BASE_IDX                                                          2
3148 #define mmHUBPREQ3_FLIP_PARAMETERS_4                                                                   0x08fa
3149 #define mmHUBPREQ3_FLIP_PARAMETERS_4_BASE_IDX                                                          2
3150 #define mmHUBPREQ3_FLIP_PARAMETERS_5                                                                   0x08fb
3151 #define mmHUBPREQ3_FLIP_PARAMETERS_5_BASE_IDX                                                          2
3152 #define mmHUBPREQ3_FLIP_PARAMETERS_6                                                                   0x08fc
3153 #define mmHUBPREQ3_FLIP_PARAMETERS_6_BASE_IDX                                                          2
3154 
3155 
3156 // addressBlock: dce_dc_dcbubp3_dispdec_hubpret_dispdec
3157 // base address: 0xa50
3158 #define mmHUBPRET3_HUBPRET_CONTROL                                                                     0x0900
3159 #define mmHUBPRET3_HUBPRET_CONTROL_BASE_IDX                                                            2
3160 #define mmHUBPRET3_HUBPRET_MEM_PWR_CTRL                                                                0x0901
3161 #define mmHUBPRET3_HUBPRET_MEM_PWR_CTRL_BASE_IDX                                                       2
3162 #define mmHUBPRET3_HUBPRET_MEM_PWR_STATUS                                                              0x0902
3163 #define mmHUBPRET3_HUBPRET_MEM_PWR_STATUS_BASE_IDX                                                     2
3164 #define mmHUBPRET3_HUBPRET_READ_LINE_CTRL0                                                             0x0903
3165 #define mmHUBPRET3_HUBPRET_READ_LINE_CTRL0_BASE_IDX                                                    2
3166 #define mmHUBPRET3_HUBPRET_READ_LINE_CTRL1                                                             0x0904
3167 #define mmHUBPRET3_HUBPRET_READ_LINE_CTRL1_BASE_IDX                                                    2
3168 #define mmHUBPRET3_HUBPRET_READ_LINE0                                                                  0x0905
3169 #define mmHUBPRET3_HUBPRET_READ_LINE0_BASE_IDX                                                         2
3170 #define mmHUBPRET3_HUBPRET_READ_LINE1                                                                  0x0906
3171 #define mmHUBPRET3_HUBPRET_READ_LINE1_BASE_IDX                                                         2
3172 #define mmHUBPRET3_HUBPRET_INTERRUPT                                                                   0x0907
3173 #define mmHUBPRET3_HUBPRET_INTERRUPT_BASE_IDX                                                          2
3174 #define mmHUBPRET3_HUBPRET_READ_LINE_VALUE                                                             0x0908
3175 #define mmHUBPRET3_HUBPRET_READ_LINE_VALUE_BASE_IDX                                                    2
3176 #define mmHUBPRET3_HUBPRET_READ_LINE_STATUS                                                            0x0909
3177 #define mmHUBPRET3_HUBPRET_READ_LINE_STATUS_BASE_IDX                                                   2
3178 
3179 
3180 // addressBlock: dce_dc_dcbubp3_dispdec_cursor0_dispdec
3181 // base address: 0xa50
3182 #define mmCURSOR0_3_CURSOR_CONTROL                                                                     0x090c
3183 #define mmCURSOR0_3_CURSOR_CONTROL_BASE_IDX                                                            2
3184 #define mmCURSOR0_3_CURSOR_SURFACE_ADDRESS                                                             0x090d
3185 #define mmCURSOR0_3_CURSOR_SURFACE_ADDRESS_BASE_IDX                                                    2
3186 #define mmCURSOR0_3_CURSOR_SURFACE_ADDRESS_HIGH                                                        0x090e
3187 #define mmCURSOR0_3_CURSOR_SURFACE_ADDRESS_HIGH_BASE_IDX                                               2
3188 #define mmCURSOR0_3_CURSOR_SIZE                                                                        0x090f
3189 #define mmCURSOR0_3_CURSOR_SIZE_BASE_IDX                                                               2
3190 #define mmCURSOR0_3_CURSOR_POSITION                                                                    0x0910
3191 #define mmCURSOR0_3_CURSOR_POSITION_BASE_IDX                                                           2
3192 #define mmCURSOR0_3_CURSOR_HOT_SPOT                                                                    0x0911
3193 #define mmCURSOR0_3_CURSOR_HOT_SPOT_BASE_IDX                                                           2
3194 #define mmCURSOR0_3_CURSOR_STEREO_CONTROL                                                              0x0912
3195 #define mmCURSOR0_3_CURSOR_STEREO_CONTROL_BASE_IDX                                                     2
3196 #define mmCURSOR0_3_CURSOR_DST_OFFSET                                                                  0x0913
3197 #define mmCURSOR0_3_CURSOR_DST_OFFSET_BASE_IDX                                                         2
3198 #define mmCURSOR0_3_CURSOR_MEM_PWR_CTRL                                                                0x0914
3199 #define mmCURSOR0_3_CURSOR_MEM_PWR_CTRL_BASE_IDX                                                       2
3200 #define mmCURSOR0_3_CURSOR_MEM_PWR_STATUS                                                              0x0915
3201 #define mmCURSOR0_3_CURSOR_MEM_PWR_STATUS_BASE_IDX                                                     2
3202 #define mmCURSOR0_3_DMDATA_ADDRESS_HIGH                                                                0x0916
3203 #define mmCURSOR0_3_DMDATA_ADDRESS_HIGH_BASE_IDX                                                       2
3204 #define mmCURSOR0_3_DMDATA_ADDRESS_LOW                                                                 0x0917
3205 #define mmCURSOR0_3_DMDATA_ADDRESS_LOW_BASE_IDX                                                        2
3206 #define mmCURSOR0_3_DMDATA_CNTL                                                                        0x0918
3207 #define mmCURSOR0_3_DMDATA_CNTL_BASE_IDX                                                               2
3208 #define mmCURSOR0_3_DMDATA_QOS_CNTL                                                                    0x0919
3209 #define mmCURSOR0_3_DMDATA_QOS_CNTL_BASE_IDX                                                           2
3210 #define mmCURSOR0_3_DMDATA_STATUS                                                                      0x091a
3211 #define mmCURSOR0_3_DMDATA_STATUS_BASE_IDX                                                             2
3212 #define mmCURSOR0_3_DMDATA_SW_CNTL                                                                     0x091b
3213 #define mmCURSOR0_3_DMDATA_SW_CNTL_BASE_IDX                                                            2
3214 #define mmCURSOR0_3_DMDATA_SW_DATA                                                                     0x091c
3215 #define mmCURSOR0_3_DMDATA_SW_DATA_BASE_IDX                                                            2
3216 
3217 
3218 // addressBlock: dce_dc_dcbubp3_dispdec_hubp_dcperfmon_dc_perfmon_dispdec
3219 // base address: 0x24c4
3220 #define mmDC_PERFMON9_PERFCOUNTER_CNTL                                                                 0x0931
3221 #define mmDC_PERFMON9_PERFCOUNTER_CNTL_BASE_IDX                                                        2
3222 #define mmDC_PERFMON9_PERFCOUNTER_CNTL2                                                                0x0932
3223 #define mmDC_PERFMON9_PERFCOUNTER_CNTL2_BASE_IDX                                                       2
3224 #define mmDC_PERFMON9_PERFCOUNTER_STATE                                                                0x0933
3225 #define mmDC_PERFMON9_PERFCOUNTER_STATE_BASE_IDX                                                       2
3226 #define mmDC_PERFMON9_PERFMON_CNTL                                                                     0x0934
3227 #define mmDC_PERFMON9_PERFMON_CNTL_BASE_IDX                                                            2
3228 #define mmDC_PERFMON9_PERFMON_CNTL2                                                                    0x0935
3229 #define mmDC_PERFMON9_PERFMON_CNTL2_BASE_IDX                                                           2
3230 #define mmDC_PERFMON9_PERFMON_CVALUE_INT_MISC                                                          0x0936
3231 #define mmDC_PERFMON9_PERFMON_CVALUE_INT_MISC_BASE_IDX                                                 2
3232 #define mmDC_PERFMON9_PERFMON_CVALUE_LOW                                                               0x0937
3233 #define mmDC_PERFMON9_PERFMON_CVALUE_LOW_BASE_IDX                                                      2
3234 #define mmDC_PERFMON9_PERFMON_HI                                                                       0x0938
3235 #define mmDC_PERFMON9_PERFMON_HI_BASE_IDX                                                              2
3236 #define mmDC_PERFMON9_PERFMON_LOW                                                                      0x0939
3237 #define mmDC_PERFMON9_PERFMON_LOW_BASE_IDX                                                             2
3238 
3239 
3240 // addressBlock: dce_dc_dcbubp4_dispdec_hubp_dispdec
3241 // base address: 0xdc0
3242 #define mmHUBP4_DCSURF_SURFACE_CONFIG                                                                  0x0955
3243 #define mmHUBP4_DCSURF_SURFACE_CONFIG_BASE_IDX                                                         2
3244 #define mmHUBP4_DCSURF_ADDR_CONFIG                                                                     0x0956
3245 #define mmHUBP4_DCSURF_ADDR_CONFIG_BASE_IDX                                                            2
3246 #define mmHUBP4_DCSURF_TILING_CONFIG                                                                   0x0957
3247 #define mmHUBP4_DCSURF_TILING_CONFIG_BASE_IDX                                                          2
3248 #define mmHUBP4_DCSURF_PRI_VIEWPORT_START                                                              0x0959
3249 #define mmHUBP4_DCSURF_PRI_VIEWPORT_START_BASE_IDX                                                     2
3250 #define mmHUBP4_DCSURF_PRI_VIEWPORT_DIMENSION                                                          0x095a
3251 #define mmHUBP4_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX                                                 2
3252 #define mmHUBP4_DCSURF_PRI_VIEWPORT_START_C                                                            0x095b
3253 #define mmHUBP4_DCSURF_PRI_VIEWPORT_START_C_BASE_IDX                                                   2
3254 #define mmHUBP4_DCSURF_PRI_VIEWPORT_DIMENSION_C                                                        0x095c
3255 #define mmHUBP4_DCSURF_PRI_VIEWPORT_DIMENSION_C_BASE_IDX                                               2
3256 #define mmHUBP4_DCSURF_SEC_VIEWPORT_START                                                              0x095d
3257 #define mmHUBP4_DCSURF_SEC_VIEWPORT_START_BASE_IDX                                                     2
3258 #define mmHUBP4_DCSURF_SEC_VIEWPORT_DIMENSION                                                          0x095e
3259 #define mmHUBP4_DCSURF_SEC_VIEWPORT_DIMENSION_BASE_IDX                                                 2
3260 #define mmHUBP4_DCSURF_SEC_VIEWPORT_START_C                                                            0x095f
3261 #define mmHUBP4_DCSURF_SEC_VIEWPORT_START_C_BASE_IDX                                                   2
3262 #define mmHUBP4_DCSURF_SEC_VIEWPORT_DIMENSION_C                                                        0x0960
3263 #define mmHUBP4_DCSURF_SEC_VIEWPORT_DIMENSION_C_BASE_IDX                                               2
3264 #define mmHUBP4_DCHUBP_REQ_SIZE_CONFIG                                                                 0x0961
3265 #define mmHUBP4_DCHUBP_REQ_SIZE_CONFIG_BASE_IDX                                                        2
3266 #define mmHUBP4_DCHUBP_REQ_SIZE_CONFIG_C                                                               0x0962
3267 #define mmHUBP4_DCHUBP_REQ_SIZE_CONFIG_C_BASE_IDX                                                      2
3268 #define mmHUBP4_DCHUBP_CNTL                                                                            0x0963
3269 #define mmHUBP4_DCHUBP_CNTL_BASE_IDX                                                                   2
3270 #define mmHUBP4_HUBP_CLK_CNTL                                                                          0x0964
3271 #define mmHUBP4_HUBP_CLK_CNTL_BASE_IDX                                                                 2
3272 #define mmHUBP4_DCHUBP_VMPG_CONFIG                                                                     0x0965
3273 #define mmHUBP4_DCHUBP_VMPG_CONFIG_BASE_IDX                                                            2
3274 #define mmHUBP4_HUBPREQ_DEBUG_DB                                                                       0x0966
3275 #define mmHUBP4_HUBPREQ_DEBUG_DB_BASE_IDX                                                              2
3276 #define mmHUBP4_HUBPREQ_DEBUG                                                                          0x0967
3277 #define mmHUBP4_HUBPREQ_DEBUG_BASE_IDX                                                                 2
3278 #define mmHUBP4_HUBP_MEASURE_WIN_CTRL_DCFCLK                                                           0x096b
3279 #define mmHUBP4_HUBP_MEASURE_WIN_CTRL_DCFCLK_BASE_IDX                                                  2
3280 #define mmHUBP4_HUBP_MEASURE_WIN_CTRL_DPPCLK                                                           0x096c
3281 #define mmHUBP4_HUBP_MEASURE_WIN_CTRL_DPPCLK_BASE_IDX                                                  2
3282 
3283 
3284 // addressBlock: dce_dc_dcbubp4_dispdec_hubpreq_dispdec
3285 // base address: 0xdc0
3286 #define mmHUBPREQ4_DCSURF_SURFACE_PITCH                                                                0x0977
3287 #define mmHUBPREQ4_DCSURF_SURFACE_PITCH_BASE_IDX                                                       2
3288 #define mmHUBPREQ4_DCSURF_SURFACE_PITCH_C                                                              0x0978
3289 #define mmHUBPREQ4_DCSURF_SURFACE_PITCH_C_BASE_IDX                                                     2
3290 #define mmHUBPREQ4_VMID_SETTINGS_0                                                                     0x0979
3291 #define mmHUBPREQ4_VMID_SETTINGS_0_BASE_IDX                                                            2
3292 #define mmHUBPREQ4_DCSURF_PRIMARY_SURFACE_ADDRESS                                                      0x097a
3293 #define mmHUBPREQ4_DCSURF_PRIMARY_SURFACE_ADDRESS_BASE_IDX                                             2
3294 #define mmHUBPREQ4_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH                                                 0x097b
3295 #define mmHUBPREQ4_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX                                        2
3296 #define mmHUBPREQ4_DCSURF_PRIMARY_SURFACE_ADDRESS_C                                                    0x097c
3297 #define mmHUBPREQ4_DCSURF_PRIMARY_SURFACE_ADDRESS_C_BASE_IDX                                           2
3298 #define mmHUBPREQ4_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C                                               0x097d
3299 #define mmHUBPREQ4_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX                                      2
3300 #define mmHUBPREQ4_DCSURF_SECONDARY_SURFACE_ADDRESS                                                    0x097e
3301 #define mmHUBPREQ4_DCSURF_SECONDARY_SURFACE_ADDRESS_BASE_IDX                                           2
3302 #define mmHUBPREQ4_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH                                               0x097f
3303 #define mmHUBPREQ4_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX                                      2
3304 #define mmHUBPREQ4_DCSURF_SECONDARY_SURFACE_ADDRESS_C                                                  0x0980
3305 #define mmHUBPREQ4_DCSURF_SECONDARY_SURFACE_ADDRESS_C_BASE_IDX                                         2
3306 #define mmHUBPREQ4_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C                                             0x0981
3307 #define mmHUBPREQ4_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX                                    2
3308 #define mmHUBPREQ4_DCSURF_PRIMARY_META_SURFACE_ADDRESS                                                 0x0982
3309 #define mmHUBPREQ4_DCSURF_PRIMARY_META_SURFACE_ADDRESS_BASE_IDX                                        2
3310 #define mmHUBPREQ4_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH                                            0x0983
3311 #define mmHUBPREQ4_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX                                   2
3312 #define mmHUBPREQ4_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C                                               0x0984
3313 #define mmHUBPREQ4_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C_BASE_IDX                                      2
3314 #define mmHUBPREQ4_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C                                          0x0985
3315 #define mmHUBPREQ4_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX                                 2
3316 #define mmHUBPREQ4_DCSURF_SECONDARY_META_SURFACE_ADDRESS                                               0x0986
3317 #define mmHUBPREQ4_DCSURF_SECONDARY_META_SURFACE_ADDRESS_BASE_IDX                                      2
3318 #define mmHUBPREQ4_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH                                          0x0987
3319 #define mmHUBPREQ4_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX                                 2
3320 #define mmHUBPREQ4_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C                                             0x0988
3321 #define mmHUBPREQ4_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C_BASE_IDX                                    2
3322 #define mmHUBPREQ4_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C                                        0x0989
3323 #define mmHUBPREQ4_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX                               2
3324 #define mmHUBPREQ4_DCSURF_SURFACE_CONTROL                                                              0x098a
3325 #define mmHUBPREQ4_DCSURF_SURFACE_CONTROL_BASE_IDX                                                     2
3326 #define mmHUBPREQ4_DCSURF_FLIP_CONTROL                                                                 0x098b
3327 #define mmHUBPREQ4_DCSURF_FLIP_CONTROL_BASE_IDX                                                        2
3328 #define mmHUBPREQ4_DCSURF_FLIP_CONTROL2                                                                0x098c
3329 #define mmHUBPREQ4_DCSURF_FLIP_CONTROL2_BASE_IDX                                                       2
3330 #define mmHUBPREQ4_DCSURF_SURFACE_FLIP_INTERRUPT                                                       0x0990
3331 #define mmHUBPREQ4_DCSURF_SURFACE_FLIP_INTERRUPT_BASE_IDX                                              2
3332 #define mmHUBPREQ4_DCSURF_SURFACE_INUSE                                                                0x0991
3333 #define mmHUBPREQ4_DCSURF_SURFACE_INUSE_BASE_IDX                                                       2
3334 #define mmHUBPREQ4_DCSURF_SURFACE_INUSE_HIGH                                                           0x0992
3335 #define mmHUBPREQ4_DCSURF_SURFACE_INUSE_HIGH_BASE_IDX                                                  2
3336 #define mmHUBPREQ4_DCSURF_SURFACE_INUSE_C                                                              0x0993
3337 #define mmHUBPREQ4_DCSURF_SURFACE_INUSE_C_BASE_IDX                                                     2
3338 #define mmHUBPREQ4_DCSURF_SURFACE_INUSE_HIGH_C                                                         0x0994
3339 #define mmHUBPREQ4_DCSURF_SURFACE_INUSE_HIGH_C_BASE_IDX                                                2
3340 #define mmHUBPREQ4_DCSURF_SURFACE_EARLIEST_INUSE                                                       0x0995
3341 #define mmHUBPREQ4_DCSURF_SURFACE_EARLIEST_INUSE_BASE_IDX                                              2
3342 #define mmHUBPREQ4_DCSURF_SURFACE_EARLIEST_INUSE_HIGH                                                  0x0996
3343 #define mmHUBPREQ4_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_BASE_IDX                                         2
3344 #define mmHUBPREQ4_DCSURF_SURFACE_EARLIEST_INUSE_C                                                     0x0997
3345 #define mmHUBPREQ4_DCSURF_SURFACE_EARLIEST_INUSE_C_BASE_IDX                                            2
3346 #define mmHUBPREQ4_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C                                                0x0998
3347 #define mmHUBPREQ4_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C_BASE_IDX                                       2
3348 #define mmHUBPREQ4_DCN_EXPANSION_MODE                                                                  0x0999
3349 #define mmHUBPREQ4_DCN_EXPANSION_MODE_BASE_IDX                                                         2
3350 #define mmHUBPREQ4_DCN_TTU_QOS_WM                                                                      0x099a
3351 #define mmHUBPREQ4_DCN_TTU_QOS_WM_BASE_IDX                                                             2
3352 #define mmHUBPREQ4_DCN_GLOBAL_TTU_CNTL                                                                 0x099b
3353 #define mmHUBPREQ4_DCN_GLOBAL_TTU_CNTL_BASE_IDX                                                        2
3354 #define mmHUBPREQ4_DCN_SURF0_TTU_CNTL0                                                                 0x099c
3355 #define mmHUBPREQ4_DCN_SURF0_TTU_CNTL0_BASE_IDX                                                        2
3356 #define mmHUBPREQ4_DCN_SURF0_TTU_CNTL1                                                                 0x099d
3357 #define mmHUBPREQ4_DCN_SURF0_TTU_CNTL1_BASE_IDX                                                        2
3358 #define mmHUBPREQ4_DCN_SURF1_TTU_CNTL0                                                                 0x099e
3359 #define mmHUBPREQ4_DCN_SURF1_TTU_CNTL0_BASE_IDX                                                        2
3360 #define mmHUBPREQ4_DCN_SURF1_TTU_CNTL1                                                                 0x099f
3361 #define mmHUBPREQ4_DCN_SURF1_TTU_CNTL1_BASE_IDX                                                        2
3362 #define mmHUBPREQ4_DCN_CUR0_TTU_CNTL0                                                                  0x09a0
3363 #define mmHUBPREQ4_DCN_CUR0_TTU_CNTL0_BASE_IDX                                                         2
3364 #define mmHUBPREQ4_DCN_CUR0_TTU_CNTL1                                                                  0x09a1
3365 #define mmHUBPREQ4_DCN_CUR0_TTU_CNTL1_BASE_IDX                                                         2
3366 #define mmHUBPREQ4_DCN_CUR1_TTU_CNTL0                                                                  0x09a2
3367 #define mmHUBPREQ4_DCN_CUR1_TTU_CNTL0_BASE_IDX                                                         2
3368 #define mmHUBPREQ4_DCN_CUR1_TTU_CNTL1                                                                  0x09a3
3369 #define mmHUBPREQ4_DCN_CUR1_TTU_CNTL1_BASE_IDX                                                         2
3370 #define mmHUBPREQ4_DCN_DMDATA_VM_CNTL                                                                  0x09a4
3371 #define mmHUBPREQ4_DCN_DMDATA_VM_CNTL_BASE_IDX                                                         2
3372 #define mmHUBPREQ4_DCN_VM_SYSTEM_APERTURE_LOW_ADDR                                                     0x09a5
3373 #define mmHUBPREQ4_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_BASE_IDX                                            2
3374 #define mmHUBPREQ4_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR                                                    0x09a6
3375 #define mmHUBPREQ4_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_BASE_IDX                                           2
3376 #define mmHUBPREQ4_DCN_VM_MX_L1_TLB_CNTL                                                               0x09b3
3377 #define mmHUBPREQ4_DCN_VM_MX_L1_TLB_CNTL_BASE_IDX                                                      2
3378 #define mmHUBPREQ4_BLANK_OFFSET_0                                                                      0x09b4
3379 #define mmHUBPREQ4_BLANK_OFFSET_0_BASE_IDX                                                             2
3380 #define mmHUBPREQ4_BLANK_OFFSET_1                                                                      0x09b5
3381 #define mmHUBPREQ4_BLANK_OFFSET_1_BASE_IDX                                                             2
3382 #define mmHUBPREQ4_DST_DIMENSIONS                                                                      0x09b6
3383 #define mmHUBPREQ4_DST_DIMENSIONS_BASE_IDX                                                             2
3384 #define mmHUBPREQ4_DST_AFTER_SCALER                                                                    0x09b7
3385 #define mmHUBPREQ4_DST_AFTER_SCALER_BASE_IDX                                                           2
3386 #define mmHUBPREQ4_PREFETCH_SETTINGS                                                                   0x09b8
3387 #define mmHUBPREQ4_PREFETCH_SETTINGS_BASE_IDX                                                          2
3388 #define mmHUBPREQ4_PREFETCH_SETTINGS_C                                                                 0x09b9
3389 #define mmHUBPREQ4_PREFETCH_SETTINGS_C_BASE_IDX                                                        2
3390 #define mmHUBPREQ4_VBLANK_PARAMETERS_0                                                                 0x09ba
3391 #define mmHUBPREQ4_VBLANK_PARAMETERS_0_BASE_IDX                                                        2
3392 #define mmHUBPREQ4_VBLANK_PARAMETERS_1                                                                 0x09bb
3393 #define mmHUBPREQ4_VBLANK_PARAMETERS_1_BASE_IDX                                                        2
3394 #define mmHUBPREQ4_VBLANK_PARAMETERS_2                                                                 0x09bc
3395 #define mmHUBPREQ4_VBLANK_PARAMETERS_2_BASE_IDX                                                        2
3396 #define mmHUBPREQ4_VBLANK_PARAMETERS_3                                                                 0x09bd
3397 #define mmHUBPREQ4_VBLANK_PARAMETERS_3_BASE_IDX                                                        2
3398 #define mmHUBPREQ4_VBLANK_PARAMETERS_4                                                                 0x09be
3399 #define mmHUBPREQ4_VBLANK_PARAMETERS_4_BASE_IDX                                                        2
3400 #define mmHUBPREQ4_FLIP_PARAMETERS_0                                                                   0x09bf
3401 #define mmHUBPREQ4_FLIP_PARAMETERS_0_BASE_IDX                                                          2
3402 #define mmHUBPREQ4_FLIP_PARAMETERS_1                                                                   0x09c0
3403 #define mmHUBPREQ4_FLIP_PARAMETERS_1_BASE_IDX                                                          2
3404 #define mmHUBPREQ4_FLIP_PARAMETERS_2                                                                   0x09c1
3405 #define mmHUBPREQ4_FLIP_PARAMETERS_2_BASE_IDX                                                          2
3406 #define mmHUBPREQ4_NOM_PARAMETERS_0                                                                    0x09c2
3407 #define mmHUBPREQ4_NOM_PARAMETERS_0_BASE_IDX                                                           2
3408 #define mmHUBPREQ4_NOM_PARAMETERS_1                                                                    0x09c3
3409 #define mmHUBPREQ4_NOM_PARAMETERS_1_BASE_IDX                                                           2
3410 #define mmHUBPREQ4_NOM_PARAMETERS_2                                                                    0x09c4
3411 #define mmHUBPREQ4_NOM_PARAMETERS_2_BASE_IDX                                                           2
3412 #define mmHUBPREQ4_NOM_PARAMETERS_3                                                                    0x09c5
3413 #define mmHUBPREQ4_NOM_PARAMETERS_3_BASE_IDX                                                           2
3414 #define mmHUBPREQ4_NOM_PARAMETERS_4                                                                    0x09c6
3415 #define mmHUBPREQ4_NOM_PARAMETERS_4_BASE_IDX                                                           2
3416 #define mmHUBPREQ4_NOM_PARAMETERS_5                                                                    0x09c7
3417 #define mmHUBPREQ4_NOM_PARAMETERS_5_BASE_IDX                                                           2
3418 #define mmHUBPREQ4_NOM_PARAMETERS_6                                                                    0x09c8
3419 #define mmHUBPREQ4_NOM_PARAMETERS_6_BASE_IDX                                                           2
3420 #define mmHUBPREQ4_NOM_PARAMETERS_7                                                                    0x09c9
3421 #define mmHUBPREQ4_NOM_PARAMETERS_7_BASE_IDX                                                           2
3422 #define mmHUBPREQ4_PER_LINE_DELIVERY_PRE                                                               0x09ca
3423 #define mmHUBPREQ4_PER_LINE_DELIVERY_PRE_BASE_IDX                                                      2
3424 #define mmHUBPREQ4_PER_LINE_DELIVERY                                                                   0x09cb
3425 #define mmHUBPREQ4_PER_LINE_DELIVERY_BASE_IDX                                                          2
3426 #define mmHUBPREQ4_CURSOR_SETTINGS                                                                     0x09cc
3427 #define mmHUBPREQ4_CURSOR_SETTINGS_BASE_IDX                                                            2
3428 #define mmHUBPREQ4_REF_FREQ_TO_PIX_FREQ                                                                0x09cd
3429 #define mmHUBPREQ4_REF_FREQ_TO_PIX_FREQ_BASE_IDX                                                       2
3430 #define mmHUBPREQ4_DST_Y_DELTA_DRQ_LIMIT                                                               0x09ce
3431 #define mmHUBPREQ4_DST_Y_DELTA_DRQ_LIMIT_BASE_IDX                                                      2
3432 #define mmHUBPREQ4_HUBPREQ_MEM_PWR_CTRL                                                                0x09cf
3433 #define mmHUBPREQ4_HUBPREQ_MEM_PWR_CTRL_BASE_IDX                                                       2
3434 #define mmHUBPREQ4_HUBPREQ_MEM_PWR_STATUS                                                              0x09d0
3435 #define mmHUBPREQ4_HUBPREQ_MEM_PWR_STATUS_BASE_IDX                                                     2
3436 #define mmHUBPREQ4_VBLANK_PARAMETERS_5                                                                 0x09d3
3437 #define mmHUBPREQ4_VBLANK_PARAMETERS_5_BASE_IDX                                                        2
3438 #define mmHUBPREQ4_VBLANK_PARAMETERS_6                                                                 0x09d4
3439 #define mmHUBPREQ4_VBLANK_PARAMETERS_6_BASE_IDX                                                        2
3440 #define mmHUBPREQ4_FLIP_PARAMETERS_3                                                                   0x09d5
3441 #define mmHUBPREQ4_FLIP_PARAMETERS_3_BASE_IDX                                                          2
3442 #define mmHUBPREQ4_FLIP_PARAMETERS_4                                                                   0x09d6
3443 #define mmHUBPREQ4_FLIP_PARAMETERS_4_BASE_IDX                                                          2
3444 #define mmHUBPREQ4_FLIP_PARAMETERS_5                                                                   0x09d7
3445 #define mmHUBPREQ4_FLIP_PARAMETERS_5_BASE_IDX                                                          2
3446 #define mmHUBPREQ4_FLIP_PARAMETERS_6                                                                   0x09d8
3447 #define mmHUBPREQ4_FLIP_PARAMETERS_6_BASE_IDX                                                          2
3448 
3449 
3450 // addressBlock: dce_dc_dcbubp4_dispdec_hubpret_dispdec
3451 // base address: 0xdc0
3452 #define mmHUBPRET4_HUBPRET_CONTROL                                                                     0x09dc
3453 #define mmHUBPRET4_HUBPRET_CONTROL_BASE_IDX                                                            2
3454 #define mmHUBPRET4_HUBPRET_MEM_PWR_CTRL                                                                0x09dd
3455 #define mmHUBPRET4_HUBPRET_MEM_PWR_CTRL_BASE_IDX                                                       2
3456 #define mmHUBPRET4_HUBPRET_MEM_PWR_STATUS                                                              0x09de
3457 #define mmHUBPRET4_HUBPRET_MEM_PWR_STATUS_BASE_IDX                                                     2
3458 #define mmHUBPRET4_HUBPRET_READ_LINE_CTRL0                                                             0x09df
3459 #define mmHUBPRET4_HUBPRET_READ_LINE_CTRL0_BASE_IDX                                                    2
3460 #define mmHUBPRET4_HUBPRET_READ_LINE_CTRL1                                                             0x09e0
3461 #define mmHUBPRET4_HUBPRET_READ_LINE_CTRL1_BASE_IDX                                                    2
3462 #define mmHUBPRET4_HUBPRET_READ_LINE0                                                                  0x09e1
3463 #define mmHUBPRET4_HUBPRET_READ_LINE0_BASE_IDX                                                         2
3464 #define mmHUBPRET4_HUBPRET_READ_LINE1                                                                  0x09e2
3465 #define mmHUBPRET4_HUBPRET_READ_LINE1_BASE_IDX                                                         2
3466 #define mmHUBPRET4_HUBPRET_INTERRUPT                                                                   0x09e3
3467 #define mmHUBPRET4_HUBPRET_INTERRUPT_BASE_IDX                                                          2
3468 #define mmHUBPRET4_HUBPRET_READ_LINE_VALUE                                                             0x09e4
3469 #define mmHUBPRET4_HUBPRET_READ_LINE_VALUE_BASE_IDX                                                    2
3470 #define mmHUBPRET4_HUBPRET_READ_LINE_STATUS                                                            0x09e5
3471 #define mmHUBPRET4_HUBPRET_READ_LINE_STATUS_BASE_IDX                                                   2
3472 
3473 
3474 // addressBlock: dce_dc_dcbubp4_dispdec_cursor0_dispdec
3475 // base address: 0xdc0
3476 #define mmCURSOR0_4_CURSOR_CONTROL                                                                     0x09e8
3477 #define mmCURSOR0_4_CURSOR_CONTROL_BASE_IDX                                                            2
3478 #define mmCURSOR0_4_CURSOR_SURFACE_ADDRESS                                                             0x09e9
3479 #define mmCURSOR0_4_CURSOR_SURFACE_ADDRESS_BASE_IDX                                                    2
3480 #define mmCURSOR0_4_CURSOR_SURFACE_ADDRESS_HIGH                                                        0x09ea
3481 #define mmCURSOR0_4_CURSOR_SURFACE_ADDRESS_HIGH_BASE_IDX                                               2
3482 #define mmCURSOR0_4_CURSOR_SIZE                                                                        0x09eb
3483 #define mmCURSOR0_4_CURSOR_SIZE_BASE_IDX                                                               2
3484 #define mmCURSOR0_4_CURSOR_POSITION                                                                    0x09ec
3485 #define mmCURSOR0_4_CURSOR_POSITION_BASE_IDX                                                           2
3486 #define mmCURSOR0_4_CURSOR_HOT_SPOT                                                                    0x09ed
3487 #define mmCURSOR0_4_CURSOR_HOT_SPOT_BASE_IDX                                                           2
3488 #define mmCURSOR0_4_CURSOR_STEREO_CONTROL                                                              0x09ee
3489 #define mmCURSOR0_4_CURSOR_STEREO_CONTROL_BASE_IDX                                                     2
3490 #define mmCURSOR0_4_CURSOR_DST_OFFSET                                                                  0x09ef
3491 #define mmCURSOR0_4_CURSOR_DST_OFFSET_BASE_IDX                                                         2
3492 #define mmCURSOR0_4_CURSOR_MEM_PWR_CTRL                                                                0x09f0
3493 #define mmCURSOR0_4_CURSOR_MEM_PWR_CTRL_BASE_IDX                                                       2
3494 #define mmCURSOR0_4_CURSOR_MEM_PWR_STATUS                                                              0x09f1
3495 #define mmCURSOR0_4_CURSOR_MEM_PWR_STATUS_BASE_IDX                                                     2
3496 #define mmCURSOR0_4_DMDATA_ADDRESS_HIGH                                                                0x09f2
3497 #define mmCURSOR0_4_DMDATA_ADDRESS_HIGH_BASE_IDX                                                       2
3498 #define mmCURSOR0_4_DMDATA_ADDRESS_LOW                                                                 0x09f3
3499 #define mmCURSOR0_4_DMDATA_ADDRESS_LOW_BASE_IDX                                                        2
3500 #define mmCURSOR0_4_DMDATA_CNTL                                                                        0x09f4
3501 #define mmCURSOR0_4_DMDATA_CNTL_BASE_IDX                                                               2
3502 #define mmCURSOR0_4_DMDATA_QOS_CNTL                                                                    0x09f5
3503 #define mmCURSOR0_4_DMDATA_QOS_CNTL_BASE_IDX                                                           2
3504 #define mmCURSOR0_4_DMDATA_STATUS                                                                      0x09f6
3505 #define mmCURSOR0_4_DMDATA_STATUS_BASE_IDX                                                             2
3506 #define mmCURSOR0_4_DMDATA_SW_CNTL                                                                     0x09f7
3507 #define mmCURSOR0_4_DMDATA_SW_CNTL_BASE_IDX                                                            2
3508 #define mmCURSOR0_4_DMDATA_SW_DATA                                                                     0x09f8
3509 #define mmCURSOR0_4_DMDATA_SW_DATA_BASE_IDX                                                            2
3510 
3511 
3512 // addressBlock: dce_dc_dcbubp4_dispdec_hubp_dcperfmon_dc_perfmon_dispdec
3513 // base address: 0x2834
3514 #define mmDC_PERFMON10_PERFCOUNTER_CNTL                                                                0x0a0d
3515 #define mmDC_PERFMON10_PERFCOUNTER_CNTL_BASE_IDX                                                       2
3516 #define mmDC_PERFMON10_PERFCOUNTER_CNTL2                                                               0x0a0e
3517 #define mmDC_PERFMON10_PERFCOUNTER_CNTL2_BASE_IDX                                                      2
3518 #define mmDC_PERFMON10_PERFCOUNTER_STATE                                                               0x0a0f
3519 #define mmDC_PERFMON10_PERFCOUNTER_STATE_BASE_IDX                                                      2
3520 #define mmDC_PERFMON10_PERFMON_CNTL                                                                    0x0a10
3521 #define mmDC_PERFMON10_PERFMON_CNTL_BASE_IDX                                                           2
3522 #define mmDC_PERFMON10_PERFMON_CNTL2                                                                   0x0a11
3523 #define mmDC_PERFMON10_PERFMON_CNTL2_BASE_IDX                                                          2
3524 #define mmDC_PERFMON10_PERFMON_CVALUE_INT_MISC                                                         0x0a12
3525 #define mmDC_PERFMON10_PERFMON_CVALUE_INT_MISC_BASE_IDX                                                2
3526 #define mmDC_PERFMON10_PERFMON_CVALUE_LOW                                                              0x0a13
3527 #define mmDC_PERFMON10_PERFMON_CVALUE_LOW_BASE_IDX                                                     2
3528 #define mmDC_PERFMON10_PERFMON_HI                                                                      0x0a14
3529 #define mmDC_PERFMON10_PERFMON_HI_BASE_IDX                                                             2
3530 #define mmDC_PERFMON10_PERFMON_LOW                                                                     0x0a15
3531 #define mmDC_PERFMON10_PERFMON_LOW_BASE_IDX                                                            2
3532 
3533 
3534 // addressBlock: dce_dc_dcbubp5_dispdec_hubp_dispdec
3535 // base address: 0x1130
3536 #define mmHUBP5_DCSURF_SURFACE_CONFIG                                                                  0x0a31
3537 #define mmHUBP5_DCSURF_SURFACE_CONFIG_BASE_IDX                                                         2
3538 #define mmHUBP5_DCSURF_ADDR_CONFIG                                                                     0x0a32
3539 #define mmHUBP5_DCSURF_ADDR_CONFIG_BASE_IDX                                                            2
3540 #define mmHUBP5_DCSURF_TILING_CONFIG                                                                   0x0a33
3541 #define mmHUBP5_DCSURF_TILING_CONFIG_BASE_IDX                                                          2
3542 #define mmHUBP5_DCSURF_PRI_VIEWPORT_START                                                              0x0a35
3543 #define mmHUBP5_DCSURF_PRI_VIEWPORT_START_BASE_IDX                                                     2
3544 #define mmHUBP5_DCSURF_PRI_VIEWPORT_DIMENSION                                                          0x0a36
3545 #define mmHUBP5_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX                                                 2
3546 #define mmHUBP5_DCSURF_PRI_VIEWPORT_START_C                                                            0x0a37
3547 #define mmHUBP5_DCSURF_PRI_VIEWPORT_START_C_BASE_IDX                                                   2
3548 #define mmHUBP5_DCSURF_PRI_VIEWPORT_DIMENSION_C                                                        0x0a38
3549 #define mmHUBP5_DCSURF_PRI_VIEWPORT_DIMENSION_C_BASE_IDX                                               2
3550 #define mmHUBP5_DCSURF_SEC_VIEWPORT_START                                                              0x0a39
3551 #define mmHUBP5_DCSURF_SEC_VIEWPORT_START_BASE_IDX                                                     2
3552 #define mmHUBP5_DCSURF_SEC_VIEWPORT_DIMENSION                                                          0x0a3a
3553 #define mmHUBP5_DCSURF_SEC_VIEWPORT_DIMENSION_BASE_IDX                                                 2
3554 #define mmHUBP5_DCSURF_SEC_VIEWPORT_START_C                                                            0x0a3b
3555 #define mmHUBP5_DCSURF_SEC_VIEWPORT_START_C_BASE_IDX                                                   2
3556 #define mmHUBP5_DCSURF_SEC_VIEWPORT_DIMENSION_C                                                        0x0a3c
3557 #define mmHUBP5_DCSURF_SEC_VIEWPORT_DIMENSION_C_BASE_IDX                                               2
3558 #define mmHUBP5_DCHUBP_REQ_SIZE_CONFIG                                                                 0x0a3d
3559 #define mmHUBP5_DCHUBP_REQ_SIZE_CONFIG_BASE_IDX                                                        2
3560 #define mmHUBP5_DCHUBP_REQ_SIZE_CONFIG_C                                                               0x0a3e
3561 #define mmHUBP5_DCHUBP_REQ_SIZE_CONFIG_C_BASE_IDX                                                      2
3562 #define mmHUBP5_DCHUBP_CNTL                                                                            0x0a3f
3563 #define mmHUBP5_DCHUBP_CNTL_BASE_IDX                                                                   2
3564 #define mmHUBP5_HUBP_CLK_CNTL                                                                          0x0a40
3565 #define mmHUBP5_HUBP_CLK_CNTL_BASE_IDX                                                                 2
3566 #define mmHUBP5_DCHUBP_VMPG_CONFIG                                                                     0x0a41
3567 #define mmHUBP5_DCHUBP_VMPG_CONFIG_BASE_IDX                                                            2
3568 #define mmHUBP5_HUBPREQ_DEBUG_DB                                                                       0x0a42
3569 #define mmHUBP5_HUBPREQ_DEBUG_DB_BASE_IDX                                                              2
3570 #define mmHUBP5_HUBPREQ_DEBUG                                                                          0x0a43
3571 #define mmHUBP5_HUBPREQ_DEBUG_BASE_IDX                                                                 2
3572 #define mmHUBP5_HUBP_MEASURE_WIN_CTRL_DCFCLK                                                           0x0a47
3573 #define mmHUBP5_HUBP_MEASURE_WIN_CTRL_DCFCLK_BASE_IDX                                                  2
3574 #define mmHUBP5_HUBP_MEASURE_WIN_CTRL_DPPCLK                                                           0x0a48
3575 #define mmHUBP5_HUBP_MEASURE_WIN_CTRL_DPPCLK_BASE_IDX                                                  2
3576 
3577 
3578 // addressBlock: dce_dc_dcbubp5_dispdec_hubpreq_dispdec
3579 // base address: 0x1130
3580 #define mmHUBPREQ5_DCSURF_SURFACE_PITCH                                                                0x0a53
3581 #define mmHUBPREQ5_DCSURF_SURFACE_PITCH_BASE_IDX                                                       2
3582 #define mmHUBPREQ5_DCSURF_SURFACE_PITCH_C                                                              0x0a54
3583 #define mmHUBPREQ5_DCSURF_SURFACE_PITCH_C_BASE_IDX                                                     2
3584 #define mmHUBPREQ5_VMID_SETTINGS_0                                                                     0x0a55
3585 #define mmHUBPREQ5_VMID_SETTINGS_0_BASE_IDX                                                            2
3586 #define mmHUBPREQ5_DCSURF_PRIMARY_SURFACE_ADDRESS                                                      0x0a56
3587 #define mmHUBPREQ5_DCSURF_PRIMARY_SURFACE_ADDRESS_BASE_IDX                                             2
3588 #define mmHUBPREQ5_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH                                                 0x0a57
3589 #define mmHUBPREQ5_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX                                        2
3590 #define mmHUBPREQ5_DCSURF_PRIMARY_SURFACE_ADDRESS_C                                                    0x0a58
3591 #define mmHUBPREQ5_DCSURF_PRIMARY_SURFACE_ADDRESS_C_BASE_IDX                                           2
3592 #define mmHUBPREQ5_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C                                               0x0a59
3593 #define mmHUBPREQ5_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX                                      2
3594 #define mmHUBPREQ5_DCSURF_SECONDARY_SURFACE_ADDRESS                                                    0x0a5a
3595 #define mmHUBPREQ5_DCSURF_SECONDARY_SURFACE_ADDRESS_BASE_IDX                                           2
3596 #define mmHUBPREQ5_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH                                               0x0a5b
3597 #define mmHUBPREQ5_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX                                      2
3598 #define mmHUBPREQ5_DCSURF_SECONDARY_SURFACE_ADDRESS_C                                                  0x0a5c
3599 #define mmHUBPREQ5_DCSURF_SECONDARY_SURFACE_ADDRESS_C_BASE_IDX                                         2
3600 #define mmHUBPREQ5_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C                                             0x0a5d
3601 #define mmHUBPREQ5_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX                                    2
3602 #define mmHUBPREQ5_DCSURF_PRIMARY_META_SURFACE_ADDRESS                                                 0x0a5e
3603 #define mmHUBPREQ5_DCSURF_PRIMARY_META_SURFACE_ADDRESS_BASE_IDX                                        2
3604 #define mmHUBPREQ5_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH                                            0x0a5f
3605 #define mmHUBPREQ5_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX                                   2
3606 #define mmHUBPREQ5_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C                                               0x0a60
3607 #define mmHUBPREQ5_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C_BASE_IDX                                      2
3608 #define mmHUBPREQ5_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C                                          0x0a61
3609 #define mmHUBPREQ5_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX                                 2
3610 #define mmHUBPREQ5_DCSURF_SECONDARY_META_SURFACE_ADDRESS                                               0x0a62
3611 #define mmHUBPREQ5_DCSURF_SECONDARY_META_SURFACE_ADDRESS_BASE_IDX                                      2
3612 #define mmHUBPREQ5_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH                                          0x0a63
3613 #define mmHUBPREQ5_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX                                 2
3614 #define mmHUBPREQ5_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C                                             0x0a64
3615 #define mmHUBPREQ5_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C_BASE_IDX                                    2
3616 #define mmHUBPREQ5_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C                                        0x0a65
3617 #define mmHUBPREQ5_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX                               2
3618 #define mmHUBPREQ5_DCSURF_SURFACE_CONTROL                                                              0x0a66
3619 #define mmHUBPREQ5_DCSURF_SURFACE_CONTROL_BASE_IDX                                                     2
3620 #define mmHUBPREQ5_DCSURF_FLIP_CONTROL                                                                 0x0a67
3621 #define mmHUBPREQ5_DCSURF_FLIP_CONTROL_BASE_IDX                                                        2
3622 #define mmHUBPREQ5_DCSURF_FLIP_CONTROL2                                                                0x0a68
3623 #define mmHUBPREQ5_DCSURF_FLIP_CONTROL2_BASE_IDX                                                       2
3624 #define mmHUBPREQ5_DCSURF_SURFACE_FLIP_INTERRUPT                                                       0x0a6c
3625 #define mmHUBPREQ5_DCSURF_SURFACE_FLIP_INTERRUPT_BASE_IDX                                              2
3626 #define mmHUBPREQ5_DCSURF_SURFACE_INUSE                                                                0x0a6d
3627 #define mmHUBPREQ5_DCSURF_SURFACE_INUSE_BASE_IDX                                                       2
3628 #define mmHUBPREQ5_DCSURF_SURFACE_INUSE_HIGH                                                           0x0a6e
3629 #define mmHUBPREQ5_DCSURF_SURFACE_INUSE_HIGH_BASE_IDX                                                  2
3630 #define mmHUBPREQ5_DCSURF_SURFACE_INUSE_C                                                              0x0a6f
3631 #define mmHUBPREQ5_DCSURF_SURFACE_INUSE_C_BASE_IDX                                                     2
3632 #define mmHUBPREQ5_DCSURF_SURFACE_INUSE_HIGH_C                                                         0x0a70
3633 #define mmHUBPREQ5_DCSURF_SURFACE_INUSE_HIGH_C_BASE_IDX                                                2
3634 #define mmHUBPREQ5_DCSURF_SURFACE_EARLIEST_INUSE                                                       0x0a71
3635 #define mmHUBPREQ5_DCSURF_SURFACE_EARLIEST_INUSE_BASE_IDX                                              2
3636 #define mmHUBPREQ5_DCSURF_SURFACE_EARLIEST_INUSE_HIGH                                                  0x0a72
3637 #define mmHUBPREQ5_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_BASE_IDX                                         2
3638 #define mmHUBPREQ5_DCSURF_SURFACE_EARLIEST_INUSE_C                                                     0x0a73
3639 #define mmHUBPREQ5_DCSURF_SURFACE_EARLIEST_INUSE_C_BASE_IDX                                            2
3640 #define mmHUBPREQ5_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C                                                0x0a74
3641 #define mmHUBPREQ5_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C_BASE_IDX                                       2
3642 #define mmHUBPREQ5_DCN_EXPANSION_MODE                                                                  0x0a75
3643 #define mmHUBPREQ5_DCN_EXPANSION_MODE_BASE_IDX                                                         2
3644 #define mmHUBPREQ5_DCN_TTU_QOS_WM                                                                      0x0a76
3645 #define mmHUBPREQ5_DCN_TTU_QOS_WM_BASE_IDX                                                             2
3646 #define mmHUBPREQ5_DCN_GLOBAL_TTU_CNTL                                                                 0x0a77
3647 #define mmHUBPREQ5_DCN_GLOBAL_TTU_CNTL_BASE_IDX                                                        2
3648 #define mmHUBPREQ5_DCN_SURF0_TTU_CNTL0                                                                 0x0a78
3649 #define mmHUBPREQ5_DCN_SURF0_TTU_CNTL0_BASE_IDX                                                        2
3650 #define mmHUBPREQ5_DCN_SURF0_TTU_CNTL1                                                                 0x0a79
3651 #define mmHUBPREQ5_DCN_SURF0_TTU_CNTL1_BASE_IDX                                                        2
3652 #define mmHUBPREQ5_DCN_SURF1_TTU_CNTL0                                                                 0x0a7a
3653 #define mmHUBPREQ5_DCN_SURF1_TTU_CNTL0_BASE_IDX                                                        2
3654 #define mmHUBPREQ5_DCN_SURF1_TTU_CNTL1                                                                 0x0a7b
3655 #define mmHUBPREQ5_DCN_SURF1_TTU_CNTL1_BASE_IDX                                                        2
3656 #define mmHUBPREQ5_DCN_CUR0_TTU_CNTL0                                                                  0x0a7c
3657 #define mmHUBPREQ5_DCN_CUR0_TTU_CNTL0_BASE_IDX                                                         2
3658 #define mmHUBPREQ5_DCN_CUR0_TTU_CNTL1                                                                  0x0a7d
3659 #define mmHUBPREQ5_DCN_CUR0_TTU_CNTL1_BASE_IDX                                                         2
3660 #define mmHUBPREQ5_DCN_CUR1_TTU_CNTL0                                                                  0x0a7e
3661 #define mmHUBPREQ5_DCN_CUR1_TTU_CNTL0_BASE_IDX                                                         2
3662 #define mmHUBPREQ5_DCN_CUR1_TTU_CNTL1                                                                  0x0a7f
3663 #define mmHUBPREQ5_DCN_CUR1_TTU_CNTL1_BASE_IDX                                                         2
3664 #define mmHUBPREQ5_DCN_DMDATA_VM_CNTL                                                                  0x0a80
3665 #define mmHUBPREQ5_DCN_DMDATA_VM_CNTL_BASE_IDX                                                         2
3666 #define mmHUBPREQ5_DCN_VM_SYSTEM_APERTURE_LOW_ADDR                                                     0x0a81
3667 #define mmHUBPREQ5_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_BASE_IDX                                            2
3668 #define mmHUBPREQ5_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR                                                    0x0a82
3669 #define mmHUBPREQ5_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_BASE_IDX                                           2
3670 #define mmHUBPREQ5_DCN_VM_MX_L1_TLB_CNTL                                                               0x0a8f
3671 #define mmHUBPREQ5_DCN_VM_MX_L1_TLB_CNTL_BASE_IDX                                                      2
3672 #define mmHUBPREQ5_BLANK_OFFSET_0                                                                      0x0a90
3673 #define mmHUBPREQ5_BLANK_OFFSET_0_BASE_IDX                                                             2
3674 #define mmHUBPREQ5_BLANK_OFFSET_1                                                                      0x0a91
3675 #define mmHUBPREQ5_BLANK_OFFSET_1_BASE_IDX                                                             2
3676 #define mmHUBPREQ5_DST_DIMENSIONS                                                                      0x0a92
3677 #define mmHUBPREQ5_DST_DIMENSIONS_BASE_IDX                                                             2
3678 #define mmHUBPREQ5_DST_AFTER_SCALER                                                                    0x0a93
3679 #define mmHUBPREQ5_DST_AFTER_SCALER_BASE_IDX                                                           2
3680 #define mmHUBPREQ5_PREFETCH_SETTINGS                                                                   0x0a94
3681 #define mmHUBPREQ5_PREFETCH_SETTINGS_BASE_IDX                                                          2
3682 #define mmHUBPREQ5_PREFETCH_SETTINGS_C                                                                 0x0a95
3683 #define mmHUBPREQ5_PREFETCH_SETTINGS_C_BASE_IDX                                                        2
3684 #define mmHUBPREQ5_VBLANK_PARAMETERS_0                                                                 0x0a96
3685 #define mmHUBPREQ5_VBLANK_PARAMETERS_0_BASE_IDX                                                        2
3686 #define mmHUBPREQ5_VBLANK_PARAMETERS_1                                                                 0x0a97
3687 #define mmHUBPREQ5_VBLANK_PARAMETERS_1_BASE_IDX                                                        2
3688 #define mmHUBPREQ5_VBLANK_PARAMETERS_2                                                                 0x0a98
3689 #define mmHUBPREQ5_VBLANK_PARAMETERS_2_BASE_IDX                                                        2
3690 #define mmHUBPREQ5_VBLANK_PARAMETERS_3                                                                 0x0a99
3691 #define mmHUBPREQ5_VBLANK_PARAMETERS_3_BASE_IDX                                                        2
3692 #define mmHUBPREQ5_VBLANK_PARAMETERS_4                                                                 0x0a9a
3693 #define mmHUBPREQ5_VBLANK_PARAMETERS_4_BASE_IDX                                                        2
3694 #define mmHUBPREQ5_FLIP_PARAMETERS_0                                                                   0x0a9b
3695 #define mmHUBPREQ5_FLIP_PARAMETERS_0_BASE_IDX                                                          2
3696 #define mmHUBPREQ5_FLIP_PARAMETERS_1                                                                   0x0a9c
3697 #define mmHUBPREQ5_FLIP_PARAMETERS_1_BASE_IDX                                                          2
3698 #define mmHUBPREQ5_FLIP_PARAMETERS_2                                                                   0x0a9d
3699 #define mmHUBPREQ5_FLIP_PARAMETERS_2_BASE_IDX                                                          2
3700 #define mmHUBPREQ5_NOM_PARAMETERS_0                                                                    0x0a9e
3701 #define mmHUBPREQ5_NOM_PARAMETERS_0_BASE_IDX                                                           2
3702 #define mmHUBPREQ5_NOM_PARAMETERS_1                                                                    0x0a9f
3703 #define mmHUBPREQ5_NOM_PARAMETERS_1_BASE_IDX                                                           2
3704 #define mmHUBPREQ5_NOM_PARAMETERS_2                                                                    0x0aa0
3705 #define mmHUBPREQ5_NOM_PARAMETERS_2_BASE_IDX                                                           2
3706 #define mmHUBPREQ5_NOM_PARAMETERS_3                                                                    0x0aa1
3707 #define mmHUBPREQ5_NOM_PARAMETERS_3_BASE_IDX                                                           2
3708 #define mmHUBPREQ5_NOM_PARAMETERS_4                                                                    0x0aa2
3709 #define mmHUBPREQ5_NOM_PARAMETERS_4_BASE_IDX                                                           2
3710 #define mmHUBPREQ5_NOM_PARAMETERS_5                                                                    0x0aa3
3711 #define mmHUBPREQ5_NOM_PARAMETERS_5_BASE_IDX                                                           2
3712 #define mmHUBPREQ5_NOM_PARAMETERS_6                                                                    0x0aa4
3713 #define mmHUBPREQ5_NOM_PARAMETERS_6_BASE_IDX                                                           2
3714 #define mmHUBPREQ5_NOM_PARAMETERS_7                                                                    0x0aa5
3715 #define mmHUBPREQ5_NOM_PARAMETERS_7_BASE_IDX                                                           2
3716 #define mmHUBPREQ5_PER_LINE_DELIVERY_PRE                                                               0x0aa6
3717 #define mmHUBPREQ5_PER_LINE_DELIVERY_PRE_BASE_IDX                                                      2
3718 #define mmHUBPREQ5_PER_LINE_DELIVERY                                                                   0x0aa7
3719 #define mmHUBPREQ5_PER_LINE_DELIVERY_BASE_IDX                                                          2
3720 #define mmHUBPREQ5_CURSOR_SETTINGS                                                                     0x0aa8
3721 #define mmHUBPREQ5_CURSOR_SETTINGS_BASE_IDX                                                            2
3722 #define mmHUBPREQ5_REF_FREQ_TO_PIX_FREQ                                                                0x0aa9
3723 #define mmHUBPREQ5_REF_FREQ_TO_PIX_FREQ_BASE_IDX                                                       2
3724 #define mmHUBPREQ5_DST_Y_DELTA_DRQ_LIMIT                                                               0x0aaa
3725 #define mmHUBPREQ5_DST_Y_DELTA_DRQ_LIMIT_BASE_IDX                                                      2
3726 #define mmHUBPREQ5_HUBPREQ_MEM_PWR_CTRL                                                                0x0aab
3727 #define mmHUBPREQ5_HUBPREQ_MEM_PWR_CTRL_BASE_IDX                                                       2
3728 #define mmHUBPREQ5_HUBPREQ_MEM_PWR_STATUS                                                              0x0aac
3729 #define mmHUBPREQ5_HUBPREQ_MEM_PWR_STATUS_BASE_IDX                                                     2
3730 #define mmHUBPREQ5_VBLANK_PARAMETERS_5                                                                 0x0aaf
3731 #define mmHUBPREQ5_VBLANK_PARAMETERS_5_BASE_IDX                                                        2
3732 #define mmHUBPREQ5_VBLANK_PARAMETERS_6                                                                 0x0ab0
3733 #define mmHUBPREQ5_VBLANK_PARAMETERS_6_BASE_IDX                                                        2
3734 #define mmHUBPREQ5_FLIP_PARAMETERS_3                                                                   0x0ab1
3735 #define mmHUBPREQ5_FLIP_PARAMETERS_3_BASE_IDX                                                          2
3736 #define mmHUBPREQ5_FLIP_PARAMETERS_4                                                                   0x0ab2
3737 #define mmHUBPREQ5_FLIP_PARAMETERS_4_BASE_IDX                                                          2
3738 #define mmHUBPREQ5_FLIP_PARAMETERS_5                                                                   0x0ab3
3739 #define mmHUBPREQ5_FLIP_PARAMETERS_5_BASE_IDX                                                          2
3740 #define mmHUBPREQ5_FLIP_PARAMETERS_6                                                                   0x0ab4
3741 #define mmHUBPREQ5_FLIP_PARAMETERS_6_BASE_IDX                                                          2
3742 
3743 
3744 // addressBlock: dce_dc_dcbubp5_dispdec_hubpret_dispdec
3745 // base address: 0x1130
3746 #define mmHUBPRET5_HUBPRET_CONTROL                                                                     0x0ab8
3747 #define mmHUBPRET5_HUBPRET_CONTROL_BASE_IDX                                                            2
3748 #define mmHUBPRET5_HUBPRET_MEM_PWR_CTRL                                                                0x0ab9
3749 #define mmHUBPRET5_HUBPRET_MEM_PWR_CTRL_BASE_IDX                                                       2
3750 #define mmHUBPRET5_HUBPRET_MEM_PWR_STATUS                                                              0x0aba
3751 #define mmHUBPRET5_HUBPRET_MEM_PWR_STATUS_BASE_IDX                                                     2
3752 #define mmHUBPRET5_HUBPRET_READ_LINE_CTRL0                                                             0x0abb
3753 #define mmHUBPRET5_HUBPRET_READ_LINE_CTRL0_BASE_IDX                                                    2
3754 #define mmHUBPRET5_HUBPRET_READ_LINE_CTRL1                                                             0x0abc
3755 #define mmHUBPRET5_HUBPRET_READ_LINE_CTRL1_BASE_IDX                                                    2
3756 #define mmHUBPRET5_HUBPRET_READ_LINE0                                                                  0x0abd
3757 #define mmHUBPRET5_HUBPRET_READ_LINE0_BASE_IDX                                                         2
3758 #define mmHUBPRET5_HUBPRET_READ_LINE1                                                                  0x0abe
3759 #define mmHUBPRET5_HUBPRET_READ_LINE1_BASE_IDX                                                         2
3760 #define mmHUBPRET5_HUBPRET_INTERRUPT                                                                   0x0abf
3761 #define mmHUBPRET5_HUBPRET_INTERRUPT_BASE_IDX                                                          2
3762 #define mmHUBPRET5_HUBPRET_READ_LINE_VALUE                                                             0x0ac0
3763 #define mmHUBPRET5_HUBPRET_READ_LINE_VALUE_BASE_IDX                                                    2
3764 #define mmHUBPRET5_HUBPRET_READ_LINE_STATUS                                                            0x0ac1
3765 #define mmHUBPRET5_HUBPRET_READ_LINE_STATUS_BASE_IDX                                                   2
3766 
3767 
3768 // addressBlock: dce_dc_dcbubp5_dispdec_cursor0_dispdec
3769 // base address: 0x1130
3770 #define mmCURSOR0_5_CURSOR_CONTROL                                                                     0x0ac4
3771 #define mmCURSOR0_5_CURSOR_CONTROL_BASE_IDX                                                            2
3772 #define mmCURSOR0_5_CURSOR_SURFACE_ADDRESS                                                             0x0ac5
3773 #define mmCURSOR0_5_CURSOR_SURFACE_ADDRESS_BASE_IDX                                                    2
3774 #define mmCURSOR0_5_CURSOR_SURFACE_ADDRESS_HIGH                                                        0x0ac6
3775 #define mmCURSOR0_5_CURSOR_SURFACE_ADDRESS_HIGH_BASE_IDX                                               2
3776 #define mmCURSOR0_5_CURSOR_SIZE                                                                        0x0ac7
3777 #define mmCURSOR0_5_CURSOR_SIZE_BASE_IDX                                                               2
3778 #define mmCURSOR0_5_CURSOR_POSITION                                                                    0x0ac8
3779 #define mmCURSOR0_5_CURSOR_POSITION_BASE_IDX                                                           2
3780 #define mmCURSOR0_5_CURSOR_HOT_SPOT                                                                    0x0ac9
3781 #define mmCURSOR0_5_CURSOR_HOT_SPOT_BASE_IDX                                                           2
3782 #define mmCURSOR0_5_CURSOR_STEREO_CONTROL                                                              0x0aca
3783 #define mmCURSOR0_5_CURSOR_STEREO_CONTROL_BASE_IDX                                                     2
3784 #define mmCURSOR0_5_CURSOR_DST_OFFSET                                                                  0x0acb
3785 #define mmCURSOR0_5_CURSOR_DST_OFFSET_BASE_IDX                                                         2
3786 #define mmCURSOR0_5_CURSOR_MEM_PWR_CTRL                                                                0x0acc
3787 #define mmCURSOR0_5_CURSOR_MEM_PWR_CTRL_BASE_IDX                                                       2
3788 #define mmCURSOR0_5_CURSOR_MEM_PWR_STATUS                                                              0x0acd
3789 #define mmCURSOR0_5_CURSOR_MEM_PWR_STATUS_BASE_IDX                                                     2
3790 #define mmCURSOR0_5_DMDATA_ADDRESS_HIGH                                                                0x0ace
3791 #define mmCURSOR0_5_DMDATA_ADDRESS_HIGH_BASE_IDX                                                       2
3792 #define mmCURSOR0_5_DMDATA_ADDRESS_LOW                                                                 0x0acf
3793 #define mmCURSOR0_5_DMDATA_ADDRESS_LOW_BASE_IDX                                                        2
3794 #define mmCURSOR0_5_DMDATA_CNTL                                                                        0x0ad0
3795 #define mmCURSOR0_5_DMDATA_CNTL_BASE_IDX                                                               2
3796 #define mmCURSOR0_5_DMDATA_QOS_CNTL                                                                    0x0ad1
3797 #define mmCURSOR0_5_DMDATA_QOS_CNTL_BASE_IDX                                                           2
3798 #define mmCURSOR0_5_DMDATA_STATUS                                                                      0x0ad2
3799 #define mmCURSOR0_5_DMDATA_STATUS_BASE_IDX                                                             2
3800 #define mmCURSOR0_5_DMDATA_SW_CNTL                                                                     0x0ad3
3801 #define mmCURSOR0_5_DMDATA_SW_CNTL_BASE_IDX                                                            2
3802 #define mmCURSOR0_5_DMDATA_SW_DATA                                                                     0x0ad4
3803 #define mmCURSOR0_5_DMDATA_SW_DATA_BASE_IDX                                                            2
3804 
3805 // addressBlock: dce_dc_dpp0_dispdec_dpp_top_dispdec
3806 // base address: 0x0
3807 #define mmDPP_TOP0_DPP_CONTROL                                                                         0x0cc5
3808 #define mmDPP_TOP0_DPP_CONTROL_BASE_IDX                                                                2
3809 #define mmDPP_TOP0_DPP_SOFT_RESET                                                                      0x0cc6
3810 #define mmDPP_TOP0_DPP_SOFT_RESET_BASE_IDX                                                             2
3811 #define mmDPP_TOP0_DPP_CRC_VAL_R_G                                                                     0x0cc7
3812 #define mmDPP_TOP0_DPP_CRC_VAL_R_G_BASE_IDX                                                            2
3813 #define mmDPP_TOP0_DPP_CRC_VAL_B_A                                                                     0x0cc8
3814 #define mmDPP_TOP0_DPP_CRC_VAL_B_A_BASE_IDX                                                            2
3815 #define mmDPP_TOP0_DPP_CRC_CTRL                                                                        0x0cc9
3816 #define mmDPP_TOP0_DPP_CRC_CTRL_BASE_IDX                                                               2
3817 #define mmDPP_TOP0_HOST_READ_CONTROL                                                                   0x0cca
3818 #define mmDPP_TOP0_HOST_READ_CONTROL_BASE_IDX                                                          2
3819 
3820 
3821 // addressBlock: dce_dc_dpp0_dispdec_cnvc_cfg_dispdec
3822 // base address: 0x0
3823 #define mmCNVC_CFG0_CNVC_SURFACE_PIXEL_FORMAT                                                          0x0ccf
3824 #define mmCNVC_CFG0_CNVC_SURFACE_PIXEL_FORMAT_BASE_IDX                                                 2
3825 #define mmCNVC_CFG0_FORMAT_CONTROL                                                                     0x0cd0
3826 #define mmCNVC_CFG0_FORMAT_CONTROL_BASE_IDX                                                            2
3827 #define mmCNVC_CFG0_FCNV_FP_BIAS_R                                                                     0x0cd1
3828 #define mmCNVC_CFG0_FCNV_FP_BIAS_R_BASE_IDX                                                            2
3829 #define mmCNVC_CFG0_FCNV_FP_BIAS_G                                                                     0x0cd2
3830 #define mmCNVC_CFG0_FCNV_FP_BIAS_G_BASE_IDX                                                            2
3831 #define mmCNVC_CFG0_FCNV_FP_BIAS_B                                                                     0x0cd3
3832 #define mmCNVC_CFG0_FCNV_FP_BIAS_B_BASE_IDX                                                            2
3833 #define mmCNVC_CFG0_FCNV_FP_SCALE_R                                                                    0x0cd4
3834 #define mmCNVC_CFG0_FCNV_FP_SCALE_R_BASE_IDX                                                           2
3835 #define mmCNVC_CFG0_FCNV_FP_SCALE_G                                                                    0x0cd5
3836 #define mmCNVC_CFG0_FCNV_FP_SCALE_G_BASE_IDX                                                           2
3837 #define mmCNVC_CFG0_FCNV_FP_SCALE_B                                                                    0x0cd6
3838 #define mmCNVC_CFG0_FCNV_FP_SCALE_B_BASE_IDX                                                           2
3839 #define mmCNVC_CFG0_COLOR_KEYER_CONTROL                                                                0x0cd7
3840 #define mmCNVC_CFG0_COLOR_KEYER_CONTROL_BASE_IDX                                                       2
3841 #define mmCNVC_CFG0_COLOR_KEYER_ALPHA                                                                  0x0cd8
3842 #define mmCNVC_CFG0_COLOR_KEYER_ALPHA_BASE_IDX                                                         2
3843 #define mmCNVC_CFG0_COLOR_KEYER_RED                                                                    0x0cd9
3844 #define mmCNVC_CFG0_COLOR_KEYER_RED_BASE_IDX                                                           2
3845 #define mmCNVC_CFG0_COLOR_KEYER_GREEN                                                                  0x0cda
3846 #define mmCNVC_CFG0_COLOR_KEYER_GREEN_BASE_IDX                                                         2
3847 #define mmCNVC_CFG0_COLOR_KEYER_BLUE                                                                   0x0cdb
3848 #define mmCNVC_CFG0_COLOR_KEYER_BLUE_BASE_IDX                                                          2
3849 #define mmCNVC_CFG0_ALPHA_2BIT_LUT                                                                     0x0cdd
3850 #define mmCNVC_CFG0_ALPHA_2BIT_LUT_BASE_IDX                                                            2
3851 #define mmCNVC_CFG0_PRE_DEALPHA                                                                        0x0cde
3852 #define mmCNVC_CFG0_PRE_DEALPHA_BASE_IDX                                                               2
3853 #define mmCNVC_CFG0_PRE_CSC_MODE                                                                       0x0cdf
3854 #define mmCNVC_CFG0_PRE_CSC_MODE_BASE_IDX                                                              2
3855 #define mmCNVC_CFG0_PRE_CSC_C11_C12                                                                    0x0ce0
3856 #define mmCNVC_CFG0_PRE_CSC_C11_C12_BASE_IDX                                                           2
3857 #define mmCNVC_CFG0_PRE_CSC_C13_C14                                                                    0x0ce1
3858 #define mmCNVC_CFG0_PRE_CSC_C13_C14_BASE_IDX                                                           2
3859 #define mmCNVC_CFG0_PRE_CSC_C21_C22                                                                    0x0ce2
3860 #define mmCNVC_CFG0_PRE_CSC_C21_C22_BASE_IDX                                                           2
3861 #define mmCNVC_CFG0_PRE_CSC_C23_C24                                                                    0x0ce3
3862 #define mmCNVC_CFG0_PRE_CSC_C23_C24_BASE_IDX                                                           2
3863 #define mmCNVC_CFG0_PRE_CSC_C31_C32                                                                    0x0ce4
3864 #define mmCNVC_CFG0_PRE_CSC_C31_C32_BASE_IDX                                                           2
3865 #define mmCNVC_CFG0_PRE_CSC_C33_C34                                                                    0x0ce5
3866 #define mmCNVC_CFG0_PRE_CSC_C33_C34_BASE_IDX                                                           2
3867 #define mmCNVC_CFG0_PRE_CSC_B_C11_C12                                                                  0x0ce6
3868 #define mmCNVC_CFG0_PRE_CSC_B_C11_C12_BASE_IDX                                                         2
3869 #define mmCNVC_CFG0_PRE_CSC_B_C13_C14                                                                  0x0ce7
3870 #define mmCNVC_CFG0_PRE_CSC_B_C13_C14_BASE_IDX                                                         2
3871 #define mmCNVC_CFG0_PRE_CSC_B_C21_C22                                                                  0x0ce8
3872 #define mmCNVC_CFG0_PRE_CSC_B_C21_C22_BASE_IDX                                                         2
3873 #define mmCNVC_CFG0_PRE_CSC_B_C23_C24                                                                  0x0ce9
3874 #define mmCNVC_CFG0_PRE_CSC_B_C23_C24_BASE_IDX                                                         2
3875 #define mmCNVC_CFG0_PRE_CSC_B_C31_C32                                                                  0x0cea
3876 #define mmCNVC_CFG0_PRE_CSC_B_C31_C32_BASE_IDX                                                         2
3877 #define mmCNVC_CFG0_PRE_CSC_B_C33_C34                                                                  0x0ceb
3878 #define mmCNVC_CFG0_PRE_CSC_B_C33_C34_BASE_IDX                                                         2
3879 #define mmCNVC_CFG0_CNVC_COEF_FORMAT                                                                   0x0cec
3880 #define mmCNVC_CFG0_CNVC_COEF_FORMAT_BASE_IDX                                                          2
3881 #define mmCNVC_CFG0_PRE_DEGAM                                                                          0x0ced
3882 #define mmCNVC_CFG0_PRE_DEGAM_BASE_IDX                                                                 2
3883 #define mmCNVC_CFG0_PRE_REALPHA                                                                        0x0cee
3884 #define mmCNVC_CFG0_PRE_REALPHA_BASE_IDX                                                               2
3885 
3886 
3887 // addressBlock: dce_dc_dpp0_dispdec_cnvc_cur_dispdec
3888 // base address: 0x0
3889 #define mmCNVC_CUR0_CURSOR0_CONTROL                                                                    0x0cf1
3890 #define mmCNVC_CUR0_CURSOR0_CONTROL_BASE_IDX                                                           2
3891 #define mmCNVC_CUR0_CURSOR0_COLOR0                                                                     0x0cf2
3892 #define mmCNVC_CUR0_CURSOR0_COLOR0_BASE_IDX                                                            2
3893 #define mmCNVC_CUR0_CURSOR0_COLOR1                                                                     0x0cf3
3894 #define mmCNVC_CUR0_CURSOR0_COLOR1_BASE_IDX                                                            2
3895 #define mmCNVC_CUR0_CURSOR0_FP_SCALE_BIAS                                                              0x0cf4
3896 #define mmCNVC_CUR0_CURSOR0_FP_SCALE_BIAS_BASE_IDX                                                     2
3897 
3898 
3899 // addressBlock: dce_dc_dpp0_dispdec_dscl_dispdec
3900 // base address: 0x0
3901 #define mmDSCL0_SCL_COEF_RAM_TAP_SELECT                                                                0x0cf9
3902 #define mmDSCL0_SCL_COEF_RAM_TAP_SELECT_BASE_IDX                                                       2
3903 #define mmDSCL0_SCL_COEF_RAM_TAP_DATA                                                                  0x0cfa
3904 #define mmDSCL0_SCL_COEF_RAM_TAP_DATA_BASE_IDX                                                         2
3905 #define mmDSCL0_SCL_MODE                                                                               0x0cfb
3906 #define mmDSCL0_SCL_MODE_BASE_IDX                                                                      2
3907 #define mmDSCL0_SCL_TAP_CONTROL                                                                        0x0cfc
3908 #define mmDSCL0_SCL_TAP_CONTROL_BASE_IDX                                                               2
3909 #define mmDSCL0_DSCL_CONTROL                                                                           0x0cfd
3910 #define mmDSCL0_DSCL_CONTROL_BASE_IDX                                                                  2
3911 #define mmDSCL0_DSCL_2TAP_CONTROL                                                                      0x0cfe
3912 #define mmDSCL0_DSCL_2TAP_CONTROL_BASE_IDX                                                             2
3913 #define mmDSCL0_SCL_MANUAL_REPLICATE_CONTROL                                                           0x0cff
3914 #define mmDSCL0_SCL_MANUAL_REPLICATE_CONTROL_BASE_IDX                                                  2
3915 #define mmDSCL0_SCL_HORZ_FILTER_SCALE_RATIO                                                            0x0d00
3916 #define mmDSCL0_SCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX                                                   2
3917 #define mmDSCL0_SCL_HORZ_FILTER_INIT                                                                   0x0d01
3918 #define mmDSCL0_SCL_HORZ_FILTER_INIT_BASE_IDX                                                          2
3919 #define mmDSCL0_SCL_HORZ_FILTER_SCALE_RATIO_C                                                          0x0d02
3920 #define mmDSCL0_SCL_HORZ_FILTER_SCALE_RATIO_C_BASE_IDX                                                 2
3921 #define mmDSCL0_SCL_HORZ_FILTER_INIT_C                                                                 0x0d03
3922 #define mmDSCL0_SCL_HORZ_FILTER_INIT_C_BASE_IDX                                                        2
3923 #define mmDSCL0_SCL_VERT_FILTER_SCALE_RATIO                                                            0x0d04
3924 #define mmDSCL0_SCL_VERT_FILTER_SCALE_RATIO_BASE_IDX                                                   2
3925 #define mmDSCL0_SCL_VERT_FILTER_INIT                                                                   0x0d05
3926 #define mmDSCL0_SCL_VERT_FILTER_INIT_BASE_IDX                                                          2
3927 #define mmDSCL0_SCL_VERT_FILTER_INIT_BOT                                                               0x0d06
3928 #define mmDSCL0_SCL_VERT_FILTER_INIT_BOT_BASE_IDX                                                      2
3929 #define mmDSCL0_SCL_VERT_FILTER_SCALE_RATIO_C                                                          0x0d07
3930 #define mmDSCL0_SCL_VERT_FILTER_SCALE_RATIO_C_BASE_IDX                                                 2
3931 #define mmDSCL0_SCL_VERT_FILTER_INIT_C                                                                 0x0d08
3932 #define mmDSCL0_SCL_VERT_FILTER_INIT_C_BASE_IDX                                                        2
3933 #define mmDSCL0_SCL_VERT_FILTER_INIT_BOT_C                                                             0x0d09
3934 #define mmDSCL0_SCL_VERT_FILTER_INIT_BOT_C_BASE_IDX                                                    2
3935 #define mmDSCL0_SCL_BLACK_COLOR                                                                        0x0d0a
3936 #define mmDSCL0_SCL_BLACK_COLOR_BASE_IDX                                                               2
3937 #define mmDSCL0_DSCL_UPDATE                                                                            0x0d0b
3938 #define mmDSCL0_DSCL_UPDATE_BASE_IDX                                                                   2
3939 #define mmDSCL0_DSCL_AUTOCAL                                                                           0x0d0c
3940 #define mmDSCL0_DSCL_AUTOCAL_BASE_IDX                                                                  2
3941 #define mmDSCL0_DSCL_EXT_OVERSCAN_LEFT_RIGHT                                                           0x0d0d
3942 #define mmDSCL0_DSCL_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX                                                  2
3943 #define mmDSCL0_DSCL_EXT_OVERSCAN_TOP_BOTTOM                                                           0x0d0e
3944 #define mmDSCL0_DSCL_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX                                                  2
3945 #define mmDSCL0_OTG_H_BLANK                                                                            0x0d0f
3946 #define mmDSCL0_OTG_H_BLANK_BASE_IDX                                                                   2
3947 #define mmDSCL0_OTG_V_BLANK                                                                            0x0d10
3948 #define mmDSCL0_OTG_V_BLANK_BASE_IDX                                                                   2
3949 #define mmDSCL0_RECOUT_START                                                                           0x0d11
3950 #define mmDSCL0_RECOUT_START_BASE_IDX                                                                  2
3951 #define mmDSCL0_RECOUT_SIZE                                                                            0x0d12
3952 #define mmDSCL0_RECOUT_SIZE_BASE_IDX                                                                   2
3953 #define mmDSCL0_MPC_SIZE                                                                               0x0d13
3954 #define mmDSCL0_MPC_SIZE_BASE_IDX                                                                      2
3955 #define mmDSCL0_LB_DATA_FORMAT                                                                         0x0d14
3956 #define mmDSCL0_LB_DATA_FORMAT_BASE_IDX                                                                2
3957 #define mmDSCL0_LB_MEMORY_CTRL                                                                         0x0d15
3958 #define mmDSCL0_LB_MEMORY_CTRL_BASE_IDX                                                                2
3959 #define mmDSCL0_LB_V_COUNTER                                                                           0x0d16
3960 #define mmDSCL0_LB_V_COUNTER_BASE_IDX                                                                  2
3961 #define mmDSCL0_DSCL_MEM_PWR_CTRL                                                                      0x0d17
3962 #define mmDSCL0_DSCL_MEM_PWR_CTRL_BASE_IDX                                                             2
3963 #define mmDSCL0_DSCL_MEM_PWR_STATUS                                                                    0x0d18
3964 #define mmDSCL0_DSCL_MEM_PWR_STATUS_BASE_IDX                                                           2
3965 #define mmDSCL0_OBUF_CONTROL                                                                           0x0d19
3966 #define mmDSCL0_OBUF_CONTROL_BASE_IDX                                                                  2
3967 #define mmDSCL0_OBUF_MEM_PWR_CTRL                                                                      0x0d1a
3968 #define mmDSCL0_OBUF_MEM_PWR_CTRL_BASE_IDX                                                             2
3969 
3970 
3971 // addressBlock: dce_dc_dpp0_dispdec_cm_dispdec
3972 // base address: 0x0
3973 #define mmCM0_CM_CONTROL                                                                               0x0d20
3974 #define mmCM0_CM_CONTROL_BASE_IDX                                                                      2
3975 #define mmCM0_CM_POST_CSC_CONTROL                                                                      0x0d21
3976 #define mmCM0_CM_POST_CSC_CONTROL_BASE_IDX                                                             2
3977 #define mmCM0_CM_POST_CSC_C11_C12                                                                      0x0d22
3978 #define mmCM0_CM_POST_CSC_C11_C12_BASE_IDX                                                             2
3979 #define mmCM0_CM_POST_CSC_C13_C14                                                                      0x0d23
3980 #define mmCM0_CM_POST_CSC_C13_C14_BASE_IDX                                                             2
3981 #define mmCM0_CM_POST_CSC_C21_C22                                                                      0x0d24
3982 #define mmCM0_CM_POST_CSC_C21_C22_BASE_IDX                                                             2
3983 #define mmCM0_CM_POST_CSC_C23_C24                                                                      0x0d25
3984 #define mmCM0_CM_POST_CSC_C23_C24_BASE_IDX                                                             2
3985 #define mmCM0_CM_POST_CSC_C31_C32                                                                      0x0d26
3986 #define mmCM0_CM_POST_CSC_C31_C32_BASE_IDX                                                             2
3987 #define mmCM0_CM_POST_CSC_C33_C34                                                                      0x0d27
3988 #define mmCM0_CM_POST_CSC_C33_C34_BASE_IDX                                                             2
3989 #define mmCM0_CM_POST_CSC_B_C11_C12                                                                    0x0d28
3990 #define mmCM0_CM_POST_CSC_B_C11_C12_BASE_IDX                                                           2
3991 #define mmCM0_CM_POST_CSC_B_C13_C14                                                                    0x0d29
3992 #define mmCM0_CM_POST_CSC_B_C13_C14_BASE_IDX                                                           2
3993 #define mmCM0_CM_POST_CSC_B_C21_C22                                                                    0x0d2a
3994 #define mmCM0_CM_POST_CSC_B_C21_C22_BASE_IDX                                                           2
3995 #define mmCM0_CM_POST_CSC_B_C23_C24                                                                    0x0d2b
3996 #define mmCM0_CM_POST_CSC_B_C23_C24_BASE_IDX                                                           2
3997 #define mmCM0_CM_POST_CSC_B_C31_C32                                                                    0x0d2c
3998 #define mmCM0_CM_POST_CSC_B_C31_C32_BASE_IDX                                                           2
3999 #define mmCM0_CM_POST_CSC_B_C33_C34                                                                    0x0d2d
4000 #define mmCM0_CM_POST_CSC_B_C33_C34_BASE_IDX                                                           2
4001 #define mmCM0_CM_GAMUT_REMAP_CONTROL                                                                   0x0d2e
4002 #define mmCM0_CM_GAMUT_REMAP_CONTROL_BASE_IDX                                                          2
4003 #define mmCM0_CM_GAMUT_REMAP_C11_C12                                                                   0x0d2f
4004 #define mmCM0_CM_GAMUT_REMAP_C11_C12_BASE_IDX                                                          2
4005 #define mmCM0_CM_GAMUT_REMAP_C13_C14                                                                   0x0d30
4006 #define mmCM0_CM_GAMUT_REMAP_C13_C14_BASE_IDX                                                          2
4007 #define mmCM0_CM_GAMUT_REMAP_C21_C22                                                                   0x0d31
4008 #define mmCM0_CM_GAMUT_REMAP_C21_C22_BASE_IDX                                                          2
4009 #define mmCM0_CM_GAMUT_REMAP_C23_C24                                                                   0x0d32
4010 #define mmCM0_CM_GAMUT_REMAP_C23_C24_BASE_IDX                                                          2
4011 #define mmCM0_CM_GAMUT_REMAP_C31_C32                                                                   0x0d33
4012 #define mmCM0_CM_GAMUT_REMAP_C31_C32_BASE_IDX                                                          2
4013 #define mmCM0_CM_GAMUT_REMAP_C33_C34                                                                   0x0d34
4014 #define mmCM0_CM_GAMUT_REMAP_C33_C34_BASE_IDX                                                          2
4015 #define mmCM0_CM_GAMUT_REMAP_B_C11_C12                                                                 0x0d35
4016 #define mmCM0_CM_GAMUT_REMAP_B_C11_C12_BASE_IDX                                                        2
4017 #define mmCM0_CM_GAMUT_REMAP_B_C13_C14                                                                 0x0d36
4018 #define mmCM0_CM_GAMUT_REMAP_B_C13_C14_BASE_IDX                                                        2
4019 #define mmCM0_CM_GAMUT_REMAP_B_C21_C22                                                                 0x0d37
4020 #define mmCM0_CM_GAMUT_REMAP_B_C21_C22_BASE_IDX                                                        2
4021 #define mmCM0_CM_GAMUT_REMAP_B_C23_C24                                                                 0x0d38
4022 #define mmCM0_CM_GAMUT_REMAP_B_C23_C24_BASE_IDX                                                        2
4023 #define mmCM0_CM_GAMUT_REMAP_B_C31_C32                                                                 0x0d39
4024 #define mmCM0_CM_GAMUT_REMAP_B_C31_C32_BASE_IDX                                                        2
4025 #define mmCM0_CM_GAMUT_REMAP_B_C33_C34                                                                 0x0d3a
4026 #define mmCM0_CM_GAMUT_REMAP_B_C33_C34_BASE_IDX                                                        2
4027 #define mmCM0_CM_BIAS_CR_R                                                                             0x0d3b
4028 #define mmCM0_CM_BIAS_CR_R_BASE_IDX                                                                    2
4029 #define mmCM0_CM_BIAS_Y_G_CB_B                                                                         0x0d3c
4030 #define mmCM0_CM_BIAS_Y_G_CB_B_BASE_IDX                                                                2
4031 #define mmCM0_CM_GAMCOR_CONTROL                                                                        0x0d3d
4032 #define mmCM0_CM_GAMCOR_CONTROL_BASE_IDX                                                               2
4033 #define mmCM0_CM_GAMCOR_LUT_INDEX                                                                      0x0d3e
4034 #define mmCM0_CM_GAMCOR_LUT_INDEX_BASE_IDX                                                             2
4035 #define mmCM0_CM_GAMCOR_LUT_DATA                                                                       0x0d3f
4036 #define mmCM0_CM_GAMCOR_LUT_DATA_BASE_IDX                                                              2
4037 #define mmCM0_CM_GAMCOR_LUT_CONTROL                                                                    0x0d40
4038 #define mmCM0_CM_GAMCOR_LUT_CONTROL_BASE_IDX                                                           2
4039 #define mmCM0_CM_GAMCOR_RAMA_START_CNTL_B                                                              0x0d41
4040 #define mmCM0_CM_GAMCOR_RAMA_START_CNTL_B_BASE_IDX                                                     2
4041 #define mmCM0_CM_GAMCOR_RAMA_START_CNTL_G                                                              0x0d42
4042 #define mmCM0_CM_GAMCOR_RAMA_START_CNTL_G_BASE_IDX                                                     2
4043 #define mmCM0_CM_GAMCOR_RAMA_START_CNTL_R                                                              0x0d43
4044 #define mmCM0_CM_GAMCOR_RAMA_START_CNTL_R_BASE_IDX                                                     2
4045 #define mmCM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B                                                        0x0d44
4046 #define mmCM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B_BASE_IDX                                               2
4047 #define mmCM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G                                                        0x0d45
4048 #define mmCM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G_BASE_IDX                                               2
4049 #define mmCM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R                                                        0x0d46
4050 #define mmCM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R_BASE_IDX                                               2
4051 #define mmCM0_CM_GAMCOR_RAMA_START_BASE_CNTL_B                                                         0x0d47
4052 #define mmCM0_CM_GAMCOR_RAMA_START_BASE_CNTL_B_BASE_IDX                                                2
4053 #define mmCM0_CM_GAMCOR_RAMA_START_BASE_CNTL_G                                                         0x0d48
4054 #define mmCM0_CM_GAMCOR_RAMA_START_BASE_CNTL_G_BASE_IDX                                                2
4055 #define mmCM0_CM_GAMCOR_RAMA_START_BASE_CNTL_R                                                         0x0d49
4056 #define mmCM0_CM_GAMCOR_RAMA_START_BASE_CNTL_R_BASE_IDX                                                2
4057 #define mmCM0_CM_GAMCOR_RAMA_END_CNTL1_B                                                               0x0d4a
4058 #define mmCM0_CM_GAMCOR_RAMA_END_CNTL1_B_BASE_IDX                                                      2
4059 #define mmCM0_CM_GAMCOR_RAMA_END_CNTL2_B                                                               0x0d4b
4060 #define mmCM0_CM_GAMCOR_RAMA_END_CNTL2_B_BASE_IDX                                                      2
4061 #define mmCM0_CM_GAMCOR_RAMA_END_CNTL1_G                                                               0x0d4c
4062 #define mmCM0_CM_GAMCOR_RAMA_END_CNTL1_G_BASE_IDX                                                      2
4063 #define mmCM0_CM_GAMCOR_RAMA_END_CNTL2_G                                                               0x0d4d
4064 #define mmCM0_CM_GAMCOR_RAMA_END_CNTL2_G_BASE_IDX                                                      2
4065 #define mmCM0_CM_GAMCOR_RAMA_END_CNTL1_R                                                               0x0d4e
4066 #define mmCM0_CM_GAMCOR_RAMA_END_CNTL1_R_BASE_IDX                                                      2
4067 #define mmCM0_CM_GAMCOR_RAMA_END_CNTL2_R                                                               0x0d4f
4068 #define mmCM0_CM_GAMCOR_RAMA_END_CNTL2_R_BASE_IDX                                                      2
4069 #define mmCM0_CM_GAMCOR_RAMA_OFFSET_B                                                                  0x0d50
4070 #define mmCM0_CM_GAMCOR_RAMA_OFFSET_B_BASE_IDX                                                         2
4071 #define mmCM0_CM_GAMCOR_RAMA_OFFSET_G                                                                  0x0d51
4072 #define mmCM0_CM_GAMCOR_RAMA_OFFSET_G_BASE_IDX                                                         2
4073 #define mmCM0_CM_GAMCOR_RAMA_OFFSET_R                                                                  0x0d52
4074 #define mmCM0_CM_GAMCOR_RAMA_OFFSET_R_BASE_IDX                                                         2
4075 #define mmCM0_CM_GAMCOR_RAMA_REGION_0_1                                                                0x0d53
4076 #define mmCM0_CM_GAMCOR_RAMA_REGION_0_1_BASE_IDX                                                       2
4077 #define mmCM0_CM_GAMCOR_RAMA_REGION_2_3                                                                0x0d54
4078 #define mmCM0_CM_GAMCOR_RAMA_REGION_2_3_BASE_IDX                                                       2
4079 #define mmCM0_CM_GAMCOR_RAMA_REGION_4_5                                                                0x0d55
4080 #define mmCM0_CM_GAMCOR_RAMA_REGION_4_5_BASE_IDX                                                       2
4081 #define mmCM0_CM_GAMCOR_RAMA_REGION_6_7                                                                0x0d56
4082 #define mmCM0_CM_GAMCOR_RAMA_REGION_6_7_BASE_IDX                                                       2
4083 #define mmCM0_CM_GAMCOR_RAMA_REGION_8_9                                                                0x0d57
4084 #define mmCM0_CM_GAMCOR_RAMA_REGION_8_9_BASE_IDX                                                       2
4085 #define mmCM0_CM_GAMCOR_RAMA_REGION_10_11                                                              0x0d58
4086 #define mmCM0_CM_GAMCOR_RAMA_REGION_10_11_BASE_IDX                                                     2
4087 #define mmCM0_CM_GAMCOR_RAMA_REGION_12_13                                                              0x0d59
4088 #define mmCM0_CM_GAMCOR_RAMA_REGION_12_13_BASE_IDX                                                     2
4089 #define mmCM0_CM_GAMCOR_RAMA_REGION_14_15                                                              0x0d5a
4090 #define mmCM0_CM_GAMCOR_RAMA_REGION_14_15_BASE_IDX                                                     2
4091 #define mmCM0_CM_GAMCOR_RAMA_REGION_16_17                                                              0x0d5b
4092 #define mmCM0_CM_GAMCOR_RAMA_REGION_16_17_BASE_IDX                                                     2
4093 #define mmCM0_CM_GAMCOR_RAMA_REGION_18_19                                                              0x0d5c
4094 #define mmCM0_CM_GAMCOR_RAMA_REGION_18_19_BASE_IDX                                                     2
4095 #define mmCM0_CM_GAMCOR_RAMA_REGION_20_21                                                              0x0d5d
4096 #define mmCM0_CM_GAMCOR_RAMA_REGION_20_21_BASE_IDX                                                     2
4097 #define mmCM0_CM_GAMCOR_RAMA_REGION_22_23                                                              0x0d5e
4098 #define mmCM0_CM_GAMCOR_RAMA_REGION_22_23_BASE_IDX                                                     2
4099 #define mmCM0_CM_GAMCOR_RAMA_REGION_24_25                                                              0x0d5f
4100 #define mmCM0_CM_GAMCOR_RAMA_REGION_24_25_BASE_IDX                                                     2
4101 #define mmCM0_CM_GAMCOR_RAMA_REGION_26_27                                                              0x0d60
4102 #define mmCM0_CM_GAMCOR_RAMA_REGION_26_27_BASE_IDX                                                     2
4103 #define mmCM0_CM_GAMCOR_RAMA_REGION_28_29                                                              0x0d61
4104 #define mmCM0_CM_GAMCOR_RAMA_REGION_28_29_BASE_IDX                                                     2
4105 #define mmCM0_CM_GAMCOR_RAMA_REGION_30_31                                                              0x0d62
4106 #define mmCM0_CM_GAMCOR_RAMA_REGION_30_31_BASE_IDX                                                     2
4107 #define mmCM0_CM_GAMCOR_RAMA_REGION_32_33                                                              0x0d63
4108 #define mmCM0_CM_GAMCOR_RAMA_REGION_32_33_BASE_IDX                                                     2
4109 #define mmCM0_CM_GAMCOR_RAMB_START_CNTL_B                                                              0x0d64
4110 #define mmCM0_CM_GAMCOR_RAMB_START_CNTL_B_BASE_IDX                                                     2
4111 #define mmCM0_CM_GAMCOR_RAMB_START_CNTL_G                                                              0x0d65
4112 #define mmCM0_CM_GAMCOR_RAMB_START_CNTL_G_BASE_IDX                                                     2
4113 #define mmCM0_CM_GAMCOR_RAMB_START_CNTL_R                                                              0x0d66
4114 #define mmCM0_CM_GAMCOR_RAMB_START_CNTL_R_BASE_IDX                                                     2
4115 #define mmCM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B                                                        0x0d67
4116 #define mmCM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B_BASE_IDX                                               2
4117 #define mmCM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G                                                        0x0d68
4118 #define mmCM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G_BASE_IDX                                               2
4119 #define mmCM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R                                                        0x0d69
4120 #define mmCM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R_BASE_IDX                                               2
4121 #define mmCM0_CM_GAMCOR_RAMB_START_BASE_CNTL_B                                                         0x0d6a
4122 #define mmCM0_CM_GAMCOR_RAMB_START_BASE_CNTL_B_BASE_IDX                                                2
4123 #define mmCM0_CM_GAMCOR_RAMB_START_BASE_CNTL_G                                                         0x0d6b
4124 #define mmCM0_CM_GAMCOR_RAMB_START_BASE_CNTL_G_BASE_IDX                                                2
4125 #define mmCM0_CM_GAMCOR_RAMB_START_BASE_CNTL_R                                                         0x0d6c
4126 #define mmCM0_CM_GAMCOR_RAMB_START_BASE_CNTL_R_BASE_IDX                                                2
4127 #define mmCM0_CM_GAMCOR_RAMB_END_CNTL1_B                                                               0x0d6d
4128 #define mmCM0_CM_GAMCOR_RAMB_END_CNTL1_B_BASE_IDX                                                      2
4129 #define mmCM0_CM_GAMCOR_RAMB_END_CNTL2_B                                                               0x0d6e
4130 #define mmCM0_CM_GAMCOR_RAMB_END_CNTL2_B_BASE_IDX                                                      2
4131 #define mmCM0_CM_GAMCOR_RAMB_END_CNTL1_G                                                               0x0d6f
4132 #define mmCM0_CM_GAMCOR_RAMB_END_CNTL1_G_BASE_IDX                                                      2
4133 #define mmCM0_CM_GAMCOR_RAMB_END_CNTL2_G                                                               0x0d70
4134 #define mmCM0_CM_GAMCOR_RAMB_END_CNTL2_G_BASE_IDX                                                      2
4135 #define mmCM0_CM_GAMCOR_RAMB_END_CNTL1_R                                                               0x0d71
4136 #define mmCM0_CM_GAMCOR_RAMB_END_CNTL1_R_BASE_IDX                                                      2
4137 #define mmCM0_CM_GAMCOR_RAMB_END_CNTL2_R                                                               0x0d72
4138 #define mmCM0_CM_GAMCOR_RAMB_END_CNTL2_R_BASE_IDX                                                      2
4139 #define mmCM0_CM_GAMCOR_RAMB_OFFSET_B                                                                  0x0d73
4140 #define mmCM0_CM_GAMCOR_RAMB_OFFSET_B_BASE_IDX                                                         2
4141 #define mmCM0_CM_GAMCOR_RAMB_OFFSET_G                                                                  0x0d74
4142 #define mmCM0_CM_GAMCOR_RAMB_OFFSET_G_BASE_IDX                                                         2
4143 #define mmCM0_CM_GAMCOR_RAMB_OFFSET_R                                                                  0x0d75
4144 #define mmCM0_CM_GAMCOR_RAMB_OFFSET_R_BASE_IDX                                                         2
4145 #define mmCM0_CM_GAMCOR_RAMB_REGION_0_1                                                                0x0d76
4146 #define mmCM0_CM_GAMCOR_RAMB_REGION_0_1_BASE_IDX                                                       2
4147 #define mmCM0_CM_GAMCOR_RAMB_REGION_2_3                                                                0x0d77
4148 #define mmCM0_CM_GAMCOR_RAMB_REGION_2_3_BASE_IDX                                                       2
4149 #define mmCM0_CM_GAMCOR_RAMB_REGION_4_5                                                                0x0d78
4150 #define mmCM0_CM_GAMCOR_RAMB_REGION_4_5_BASE_IDX                                                       2
4151 #define mmCM0_CM_GAMCOR_RAMB_REGION_6_7                                                                0x0d79
4152 #define mmCM0_CM_GAMCOR_RAMB_REGION_6_7_BASE_IDX                                                       2
4153 #define mmCM0_CM_GAMCOR_RAMB_REGION_8_9                                                                0x0d7a
4154 #define mmCM0_CM_GAMCOR_RAMB_REGION_8_9_BASE_IDX                                                       2
4155 #define mmCM0_CM_GAMCOR_RAMB_REGION_10_11                                                              0x0d7b
4156 #define mmCM0_CM_GAMCOR_RAMB_REGION_10_11_BASE_IDX                                                     2
4157 #define mmCM0_CM_GAMCOR_RAMB_REGION_12_13                                                              0x0d7c
4158 #define mmCM0_CM_GAMCOR_RAMB_REGION_12_13_BASE_IDX                                                     2
4159 #define mmCM0_CM_GAMCOR_RAMB_REGION_14_15                                                              0x0d7d
4160 #define mmCM0_CM_GAMCOR_RAMB_REGION_14_15_BASE_IDX                                                     2
4161 #define mmCM0_CM_GAMCOR_RAMB_REGION_16_17                                                              0x0d7e
4162 #define mmCM0_CM_GAMCOR_RAMB_REGION_16_17_BASE_IDX                                                     2
4163 #define mmCM0_CM_GAMCOR_RAMB_REGION_18_19                                                              0x0d7f
4164 #define mmCM0_CM_GAMCOR_RAMB_REGION_18_19_BASE_IDX                                                     2
4165 #define mmCM0_CM_GAMCOR_RAMB_REGION_20_21                                                              0x0d80
4166 #define mmCM0_CM_GAMCOR_RAMB_REGION_20_21_BASE_IDX                                                     2
4167 #define mmCM0_CM_GAMCOR_RAMB_REGION_22_23                                                              0x0d81
4168 #define mmCM0_CM_GAMCOR_RAMB_REGION_22_23_BASE_IDX                                                     2
4169 #define mmCM0_CM_GAMCOR_RAMB_REGION_24_25                                                              0x0d82
4170 #define mmCM0_CM_GAMCOR_RAMB_REGION_24_25_BASE_IDX                                                     2
4171 #define mmCM0_CM_GAMCOR_RAMB_REGION_26_27                                                              0x0d83
4172 #define mmCM0_CM_GAMCOR_RAMB_REGION_26_27_BASE_IDX                                                     2
4173 #define mmCM0_CM_GAMCOR_RAMB_REGION_28_29                                                              0x0d84
4174 #define mmCM0_CM_GAMCOR_RAMB_REGION_28_29_BASE_IDX                                                     2
4175 #define mmCM0_CM_GAMCOR_RAMB_REGION_30_31                                                              0x0d85
4176 #define mmCM0_CM_GAMCOR_RAMB_REGION_30_31_BASE_IDX                                                     2
4177 #define mmCM0_CM_GAMCOR_RAMB_REGION_32_33                                                              0x0d86
4178 #define mmCM0_CM_GAMCOR_RAMB_REGION_32_33_BASE_IDX                                                     2
4179 #define mmCM0_CM_BLNDGAM_CONTROL                                                                       0x0d87
4180 #define mmCM0_CM_BLNDGAM_CONTROL_BASE_IDX                                                              2
4181 #define mmCM0_CM_BLNDGAM_LUT_INDEX                                                                     0x0d88
4182 #define mmCM0_CM_BLNDGAM_LUT_INDEX_BASE_IDX                                                            2
4183 #define mmCM0_CM_BLNDGAM_LUT_DATA                                                                      0x0d89
4184 #define mmCM0_CM_BLNDGAM_LUT_DATA_BASE_IDX                                                             2
4185 #define mmCM0_CM_BLNDGAM_LUT_CONTROL                                                                   0x0d8a
4186 #define mmCM0_CM_BLNDGAM_LUT_CONTROL_BASE_IDX                                                          2
4187 #define mmCM0_CM_BLNDGAM_RAMA_START_CNTL_B                                                             0x0d8b
4188 #define mmCM0_CM_BLNDGAM_RAMA_START_CNTL_B_BASE_IDX                                                    2
4189 #define mmCM0_CM_BLNDGAM_RAMA_START_CNTL_G                                                             0x0d8c
4190 #define mmCM0_CM_BLNDGAM_RAMA_START_CNTL_G_BASE_IDX                                                    2
4191 #define mmCM0_CM_BLNDGAM_RAMA_START_CNTL_R                                                             0x0d8d
4192 #define mmCM0_CM_BLNDGAM_RAMA_START_CNTL_R_BASE_IDX                                                    2
4193 #define mmCM0_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_B                                                       0x0d8e
4194 #define mmCM0_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_B_BASE_IDX                                              2
4195 #define mmCM0_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_G                                                       0x0d8f
4196 #define mmCM0_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_G_BASE_IDX                                              2
4197 #define mmCM0_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_R                                                       0x0d90
4198 #define mmCM0_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_R_BASE_IDX                                              2
4199 #define mmCM0_CM_BLNDGAM_RAMA_START_BASE_CNTL_B                                                        0x0d91
4200 #define mmCM0_CM_BLNDGAM_RAMA_START_BASE_CNTL_B_BASE_IDX                                               2
4201 #define mmCM0_CM_BLNDGAM_RAMA_START_BASE_CNTL_G                                                        0x0d92
4202 #define mmCM0_CM_BLNDGAM_RAMA_START_BASE_CNTL_G_BASE_IDX                                               2
4203 #define mmCM0_CM_BLNDGAM_RAMA_START_BASE_CNTL_R                                                        0x0d93
4204 #define mmCM0_CM_BLNDGAM_RAMA_START_BASE_CNTL_R_BASE_IDX                                               2
4205 #define mmCM0_CM_BLNDGAM_RAMA_END_CNTL1_B                                                              0x0d94
4206 #define mmCM0_CM_BLNDGAM_RAMA_END_CNTL1_B_BASE_IDX                                                     2
4207 #define mmCM0_CM_BLNDGAM_RAMA_END_CNTL2_B                                                              0x0d95
4208 #define mmCM0_CM_BLNDGAM_RAMA_END_CNTL2_B_BASE_IDX                                                     2
4209 #define mmCM0_CM_BLNDGAM_RAMA_END_CNTL1_G                                                              0x0d96
4210 #define mmCM0_CM_BLNDGAM_RAMA_END_CNTL1_G_BASE_IDX                                                     2
4211 #define mmCM0_CM_BLNDGAM_RAMA_END_CNTL2_G                                                              0x0d97
4212 #define mmCM0_CM_BLNDGAM_RAMA_END_CNTL2_G_BASE_IDX                                                     2
4213 #define mmCM0_CM_BLNDGAM_RAMA_END_CNTL1_R                                                              0x0d98
4214 #define mmCM0_CM_BLNDGAM_RAMA_END_CNTL1_R_BASE_IDX                                                     2
4215 #define mmCM0_CM_BLNDGAM_RAMA_END_CNTL2_R                                                              0x0d99
4216 #define mmCM0_CM_BLNDGAM_RAMA_END_CNTL2_R_BASE_IDX                                                     2
4217 #define mmCM0_CM_BLNDGAM_RAMA_OFFSET_B                                                                 0x0d9a
4218 #define mmCM0_CM_BLNDGAM_RAMA_OFFSET_B_BASE_IDX                                                        2
4219 #define mmCM0_CM_BLNDGAM_RAMA_OFFSET_G                                                                 0x0d9b
4220 #define mmCM0_CM_BLNDGAM_RAMA_OFFSET_G_BASE_IDX                                                        2
4221 #define mmCM0_CM_BLNDGAM_RAMA_OFFSET_R                                                                 0x0d9c
4222 #define mmCM0_CM_BLNDGAM_RAMA_OFFSET_R_BASE_IDX                                                        2
4223 #define mmCM0_CM_BLNDGAM_RAMA_REGION_0_1                                                               0x0d9d
4224 #define mmCM0_CM_BLNDGAM_RAMA_REGION_0_1_BASE_IDX                                                      2
4225 #define mmCM0_CM_BLNDGAM_RAMA_REGION_2_3                                                               0x0d9e
4226 #define mmCM0_CM_BLNDGAM_RAMA_REGION_2_3_BASE_IDX                                                      2
4227 #define mmCM0_CM_BLNDGAM_RAMA_REGION_4_5                                                               0x0d9f
4228 #define mmCM0_CM_BLNDGAM_RAMA_REGION_4_5_BASE_IDX                                                      2
4229 #define mmCM0_CM_BLNDGAM_RAMA_REGION_6_7                                                               0x0da0
4230 #define mmCM0_CM_BLNDGAM_RAMA_REGION_6_7_BASE_IDX                                                      2
4231 #define mmCM0_CM_BLNDGAM_RAMA_REGION_8_9                                                               0x0da1
4232 #define mmCM0_CM_BLNDGAM_RAMA_REGION_8_9_BASE_IDX                                                      2
4233 #define mmCM0_CM_BLNDGAM_RAMA_REGION_10_11                                                             0x0da2
4234 #define mmCM0_CM_BLNDGAM_RAMA_REGION_10_11_BASE_IDX                                                    2
4235 #define mmCM0_CM_BLNDGAM_RAMA_REGION_12_13                                                             0x0da3
4236 #define mmCM0_CM_BLNDGAM_RAMA_REGION_12_13_BASE_IDX                                                    2
4237 #define mmCM0_CM_BLNDGAM_RAMA_REGION_14_15                                                             0x0da4
4238 #define mmCM0_CM_BLNDGAM_RAMA_REGION_14_15_BASE_IDX                                                    2
4239 #define mmCM0_CM_BLNDGAM_RAMA_REGION_16_17                                                             0x0da5
4240 #define mmCM0_CM_BLNDGAM_RAMA_REGION_16_17_BASE_IDX                                                    2
4241 #define mmCM0_CM_BLNDGAM_RAMA_REGION_18_19                                                             0x0da6
4242 #define mmCM0_CM_BLNDGAM_RAMA_REGION_18_19_BASE_IDX                                                    2
4243 #define mmCM0_CM_BLNDGAM_RAMA_REGION_20_21                                                             0x0da7
4244 #define mmCM0_CM_BLNDGAM_RAMA_REGION_20_21_BASE_IDX                                                    2
4245 #define mmCM0_CM_BLNDGAM_RAMA_REGION_22_23                                                             0x0da8
4246 #define mmCM0_CM_BLNDGAM_RAMA_REGION_22_23_BASE_IDX                                                    2
4247 #define mmCM0_CM_BLNDGAM_RAMA_REGION_24_25                                                             0x0da9
4248 #define mmCM0_CM_BLNDGAM_RAMA_REGION_24_25_BASE_IDX                                                    2
4249 #define mmCM0_CM_BLNDGAM_RAMA_REGION_26_27                                                             0x0daa
4250 #define mmCM0_CM_BLNDGAM_RAMA_REGION_26_27_BASE_IDX                                                    2
4251 #define mmCM0_CM_BLNDGAM_RAMA_REGION_28_29                                                             0x0dab
4252 #define mmCM0_CM_BLNDGAM_RAMA_REGION_28_29_BASE_IDX                                                    2
4253 #define mmCM0_CM_BLNDGAM_RAMA_REGION_30_31                                                             0x0dac
4254 #define mmCM0_CM_BLNDGAM_RAMA_REGION_30_31_BASE_IDX                                                    2
4255 #define mmCM0_CM_BLNDGAM_RAMA_REGION_32_33                                                             0x0dad
4256 #define mmCM0_CM_BLNDGAM_RAMA_REGION_32_33_BASE_IDX                                                    2
4257 #define mmCM0_CM_BLNDGAM_RAMB_START_CNTL_B                                                             0x0dae
4258 #define mmCM0_CM_BLNDGAM_RAMB_START_CNTL_B_BASE_IDX                                                    2
4259 #define mmCM0_CM_BLNDGAM_RAMB_START_CNTL_G                                                             0x0daf
4260 #define mmCM0_CM_BLNDGAM_RAMB_START_CNTL_G_BASE_IDX                                                    2
4261 #define mmCM0_CM_BLNDGAM_RAMB_START_CNTL_R                                                             0x0db0
4262 #define mmCM0_CM_BLNDGAM_RAMB_START_CNTL_R_BASE_IDX                                                    2
4263 #define mmCM0_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_B                                                       0x0db1
4264 #define mmCM0_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_B_BASE_IDX                                              2
4265 #define mmCM0_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_G                                                       0x0db2
4266 #define mmCM0_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_G_BASE_IDX                                              2
4267 #define mmCM0_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_R                                                       0x0db3
4268 #define mmCM0_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_R_BASE_IDX                                              2
4269 #define mmCM0_CM_BLNDGAM_RAMB_START_BASE_CNTL_B                                                        0x0db4
4270 #define mmCM0_CM_BLNDGAM_RAMB_START_BASE_CNTL_B_BASE_IDX                                               2
4271 #define mmCM0_CM_BLNDGAM_RAMB_START_BASE_CNTL_G                                                        0x0db5
4272 #define mmCM0_CM_BLNDGAM_RAMB_START_BASE_CNTL_G_BASE_IDX                                               2
4273 #define mmCM0_CM_BLNDGAM_RAMB_START_BASE_CNTL_R                                                        0x0db6
4274 #define mmCM0_CM_BLNDGAM_RAMB_START_BASE_CNTL_R_BASE_IDX                                               2
4275 #define mmCM0_CM_BLNDGAM_RAMB_END_CNTL1_B                                                              0x0db7
4276 #define mmCM0_CM_BLNDGAM_RAMB_END_CNTL1_B_BASE_IDX                                                     2
4277 #define mmCM0_CM_BLNDGAM_RAMB_END_CNTL2_B                                                              0x0db8
4278 #define mmCM0_CM_BLNDGAM_RAMB_END_CNTL2_B_BASE_IDX                                                     2
4279 #define mmCM0_CM_BLNDGAM_RAMB_END_CNTL1_G                                                              0x0db9
4280 #define mmCM0_CM_BLNDGAM_RAMB_END_CNTL1_G_BASE_IDX                                                     2
4281 #define mmCM0_CM_BLNDGAM_RAMB_END_CNTL2_G                                                              0x0dba
4282 #define mmCM0_CM_BLNDGAM_RAMB_END_CNTL2_G_BASE_IDX                                                     2
4283 #define mmCM0_CM_BLNDGAM_RAMB_END_CNTL1_R                                                              0x0dbb
4284 #define mmCM0_CM_BLNDGAM_RAMB_END_CNTL1_R_BASE_IDX                                                     2
4285 #define mmCM0_CM_BLNDGAM_RAMB_END_CNTL2_R                                                              0x0dbc
4286 #define mmCM0_CM_BLNDGAM_RAMB_END_CNTL2_R_BASE_IDX                                                     2
4287 #define mmCM0_CM_BLNDGAM_RAMB_OFFSET_B                                                                 0x0dbd
4288 #define mmCM0_CM_BLNDGAM_RAMB_OFFSET_B_BASE_IDX                                                        2
4289 #define mmCM0_CM_BLNDGAM_RAMB_OFFSET_G                                                                 0x0dbe
4290 #define mmCM0_CM_BLNDGAM_RAMB_OFFSET_G_BASE_IDX                                                        2
4291 #define mmCM0_CM_BLNDGAM_RAMB_OFFSET_R                                                                 0x0dbf
4292 #define mmCM0_CM_BLNDGAM_RAMB_OFFSET_R_BASE_IDX                                                        2
4293 #define mmCM0_CM_BLNDGAM_RAMB_REGION_0_1                                                               0x0dc0
4294 #define mmCM0_CM_BLNDGAM_RAMB_REGION_0_1_BASE_IDX                                                      2
4295 #define mmCM0_CM_BLNDGAM_RAMB_REGION_2_3                                                               0x0dc1
4296 #define mmCM0_CM_BLNDGAM_RAMB_REGION_2_3_BASE_IDX                                                      2
4297 #define mmCM0_CM_BLNDGAM_RAMB_REGION_4_5                                                               0x0dc2
4298 #define mmCM0_CM_BLNDGAM_RAMB_REGION_4_5_BASE_IDX                                                      2
4299 #define mmCM0_CM_BLNDGAM_RAMB_REGION_6_7                                                               0x0dc3
4300 #define mmCM0_CM_BLNDGAM_RAMB_REGION_6_7_BASE_IDX                                                      2
4301 #define mmCM0_CM_BLNDGAM_RAMB_REGION_8_9                                                               0x0dc4
4302 #define mmCM0_CM_BLNDGAM_RAMB_REGION_8_9_BASE_IDX                                                      2
4303 #define mmCM0_CM_BLNDGAM_RAMB_REGION_10_11                                                             0x0dc5
4304 #define mmCM0_CM_BLNDGAM_RAMB_REGION_10_11_BASE_IDX                                                    2
4305 #define mmCM0_CM_BLNDGAM_RAMB_REGION_12_13                                                             0x0dc6
4306 #define mmCM0_CM_BLNDGAM_RAMB_REGION_12_13_BASE_IDX                                                    2
4307 #define mmCM0_CM_BLNDGAM_RAMB_REGION_14_15                                                             0x0dc7
4308 #define mmCM0_CM_BLNDGAM_RAMB_REGION_14_15_BASE_IDX                                                    2
4309 #define mmCM0_CM_BLNDGAM_RAMB_REGION_16_17                                                             0x0dc8
4310 #define mmCM0_CM_BLNDGAM_RAMB_REGION_16_17_BASE_IDX                                                    2
4311 #define mmCM0_CM_BLNDGAM_RAMB_REGION_18_19                                                             0x0dc9
4312 #define mmCM0_CM_BLNDGAM_RAMB_REGION_18_19_BASE_IDX                                                    2
4313 #define mmCM0_CM_BLNDGAM_RAMB_REGION_20_21                                                             0x0dca
4314 #define mmCM0_CM_BLNDGAM_RAMB_REGION_20_21_BASE_IDX                                                    2
4315 #define mmCM0_CM_BLNDGAM_RAMB_REGION_22_23                                                             0x0dcb
4316 #define mmCM0_CM_BLNDGAM_RAMB_REGION_22_23_BASE_IDX                                                    2
4317 #define mmCM0_CM_BLNDGAM_RAMB_REGION_24_25                                                             0x0dcc
4318 #define mmCM0_CM_BLNDGAM_RAMB_REGION_24_25_BASE_IDX                                                    2
4319 #define mmCM0_CM_BLNDGAM_RAMB_REGION_26_27                                                             0x0dcd
4320 #define mmCM0_CM_BLNDGAM_RAMB_REGION_26_27_BASE_IDX                                                    2
4321 #define mmCM0_CM_BLNDGAM_RAMB_REGION_28_29                                                             0x0dce
4322 #define mmCM0_CM_BLNDGAM_RAMB_REGION_28_29_BASE_IDX                                                    2
4323 #define mmCM0_CM_BLNDGAM_RAMB_REGION_30_31                                                             0x0dcf
4324 #define mmCM0_CM_BLNDGAM_RAMB_REGION_30_31_BASE_IDX                                                    2
4325 #define mmCM0_CM_BLNDGAM_RAMB_REGION_32_33                                                             0x0dd0
4326 #define mmCM0_CM_BLNDGAM_RAMB_REGION_32_33_BASE_IDX                                                    2
4327 #define mmCM0_CM_HDR_MULT_COEF                                                                         0x0dd1
4328 #define mmCM0_CM_HDR_MULT_COEF_BASE_IDX                                                                2
4329 #define mmCM0_CM_MEM_PWR_CTRL                                                                          0x0dd2
4330 #define mmCM0_CM_MEM_PWR_CTRL_BASE_IDX                                                                 2
4331 #define mmCM0_CM_MEM_PWR_STATUS                                                                        0x0dd3
4332 #define mmCM0_CM_MEM_PWR_STATUS_BASE_IDX                                                               2
4333 #define mmCM0_CM_DEALPHA                                                                               0x0dd5
4334 #define mmCM0_CM_DEALPHA_BASE_IDX                                                                      2
4335 #define mmCM0_CM_COEF_FORMAT                                                                           0x0dd6
4336 #define mmCM0_CM_COEF_FORMAT_BASE_IDX                                                                  2
4337 #define mmCM0_CM_SHAPER_CONTROL                                                                        0x0dd7
4338 #define mmCM0_CM_SHAPER_CONTROL_BASE_IDX                                                               2
4339 #define mmCM0_CM_SHAPER_OFFSET_R                                                                       0x0dd8
4340 #define mmCM0_CM_SHAPER_OFFSET_R_BASE_IDX                                                              2
4341 #define mmCM0_CM_SHAPER_OFFSET_G                                                                       0x0dd9
4342 #define mmCM0_CM_SHAPER_OFFSET_G_BASE_IDX                                                              2
4343 #define mmCM0_CM_SHAPER_OFFSET_B                                                                       0x0dda
4344 #define mmCM0_CM_SHAPER_OFFSET_B_BASE_IDX                                                              2
4345 #define mmCM0_CM_SHAPER_SCALE_R                                                                        0x0ddb
4346 #define mmCM0_CM_SHAPER_SCALE_R_BASE_IDX                                                               2
4347 #define mmCM0_CM_SHAPER_SCALE_G_B                                                                      0x0ddc
4348 #define mmCM0_CM_SHAPER_SCALE_G_B_BASE_IDX                                                             2
4349 #define mmCM0_CM_SHAPER_LUT_INDEX                                                                      0x0ddd
4350 #define mmCM0_CM_SHAPER_LUT_INDEX_BASE_IDX                                                             2
4351 #define mmCM0_CM_SHAPER_LUT_DATA                                                                       0x0dde
4352 #define mmCM0_CM_SHAPER_LUT_DATA_BASE_IDX                                                              2
4353 #define mmCM0_CM_SHAPER_LUT_WRITE_EN_MASK                                                              0x0ddf
4354 #define mmCM0_CM_SHAPER_LUT_WRITE_EN_MASK_BASE_IDX                                                     2
4355 #define mmCM0_CM_SHAPER_RAMA_START_CNTL_B                                                              0x0de0
4356 #define mmCM0_CM_SHAPER_RAMA_START_CNTL_B_BASE_IDX                                                     2
4357 #define mmCM0_CM_SHAPER_RAMA_START_CNTL_G                                                              0x0de1
4358 #define mmCM0_CM_SHAPER_RAMA_START_CNTL_G_BASE_IDX                                                     2
4359 #define mmCM0_CM_SHAPER_RAMA_START_CNTL_R                                                              0x0de2
4360 #define mmCM0_CM_SHAPER_RAMA_START_CNTL_R_BASE_IDX                                                     2
4361 #define mmCM0_CM_SHAPER_RAMA_END_CNTL_B                                                                0x0de3
4362 #define mmCM0_CM_SHAPER_RAMA_END_CNTL_B_BASE_IDX                                                       2
4363 #define mmCM0_CM_SHAPER_RAMA_END_CNTL_G                                                                0x0de4
4364 #define mmCM0_CM_SHAPER_RAMA_END_CNTL_G_BASE_IDX                                                       2
4365 #define mmCM0_CM_SHAPER_RAMA_END_CNTL_R                                                                0x0de5
4366 #define mmCM0_CM_SHAPER_RAMA_END_CNTL_R_BASE_IDX                                                       2
4367 #define mmCM0_CM_SHAPER_RAMA_REGION_0_1                                                                0x0de6
4368 #define mmCM0_CM_SHAPER_RAMA_REGION_0_1_BASE_IDX                                                       2
4369 #define mmCM0_CM_SHAPER_RAMA_REGION_2_3                                                                0x0de7
4370 #define mmCM0_CM_SHAPER_RAMA_REGION_2_3_BASE_IDX                                                       2
4371 #define mmCM0_CM_SHAPER_RAMA_REGION_4_5                                                                0x0de8
4372 #define mmCM0_CM_SHAPER_RAMA_REGION_4_5_BASE_IDX                                                       2
4373 #define mmCM0_CM_SHAPER_RAMA_REGION_6_7                                                                0x0de9
4374 #define mmCM0_CM_SHAPER_RAMA_REGION_6_7_BASE_IDX                                                       2
4375 #define mmCM0_CM_SHAPER_RAMA_REGION_8_9                                                                0x0dea
4376 #define mmCM0_CM_SHAPER_RAMA_REGION_8_9_BASE_IDX                                                       2
4377 #define mmCM0_CM_SHAPER_RAMA_REGION_10_11                                                              0x0deb
4378 #define mmCM0_CM_SHAPER_RAMA_REGION_10_11_BASE_IDX                                                     2
4379 #define mmCM0_CM_SHAPER_RAMA_REGION_12_13                                                              0x0dec
4380 #define mmCM0_CM_SHAPER_RAMA_REGION_12_13_BASE_IDX                                                     2
4381 #define mmCM0_CM_SHAPER_RAMA_REGION_14_15                                                              0x0ded
4382 #define mmCM0_CM_SHAPER_RAMA_REGION_14_15_BASE_IDX                                                     2
4383 #define mmCM0_CM_SHAPER_RAMA_REGION_16_17                                                              0x0dee
4384 #define mmCM0_CM_SHAPER_RAMA_REGION_16_17_BASE_IDX                                                     2
4385 #define mmCM0_CM_SHAPER_RAMA_REGION_18_19                                                              0x0def
4386 #define mmCM0_CM_SHAPER_RAMA_REGION_18_19_BASE_IDX                                                     2
4387 #define mmCM0_CM_SHAPER_RAMA_REGION_20_21                                                              0x0df0
4388 #define mmCM0_CM_SHAPER_RAMA_REGION_20_21_BASE_IDX                                                     2
4389 #define mmCM0_CM_SHAPER_RAMA_REGION_22_23                                                              0x0df1
4390 #define mmCM0_CM_SHAPER_RAMA_REGION_22_23_BASE_IDX                                                     2
4391 #define mmCM0_CM_SHAPER_RAMA_REGION_24_25                                                              0x0df2
4392 #define mmCM0_CM_SHAPER_RAMA_REGION_24_25_BASE_IDX                                                     2
4393 #define mmCM0_CM_SHAPER_RAMA_REGION_26_27                                                              0x0df3
4394 #define mmCM0_CM_SHAPER_RAMA_REGION_26_27_BASE_IDX                                                     2
4395 #define mmCM0_CM_SHAPER_RAMA_REGION_28_29                                                              0x0df4
4396 #define mmCM0_CM_SHAPER_RAMA_REGION_28_29_BASE_IDX                                                     2
4397 #define mmCM0_CM_SHAPER_RAMA_REGION_30_31                                                              0x0df5
4398 #define mmCM0_CM_SHAPER_RAMA_REGION_30_31_BASE_IDX                                                     2
4399 #define mmCM0_CM_SHAPER_RAMA_REGION_32_33                                                              0x0df6
4400 #define mmCM0_CM_SHAPER_RAMA_REGION_32_33_BASE_IDX                                                     2
4401 #define mmCM0_CM_SHAPER_RAMB_START_CNTL_B                                                              0x0df7
4402 #define mmCM0_CM_SHAPER_RAMB_START_CNTL_B_BASE_IDX                                                     2
4403 #define mmCM0_CM_SHAPER_RAMB_START_CNTL_G                                                              0x0df8
4404 #define mmCM0_CM_SHAPER_RAMB_START_CNTL_G_BASE_IDX                                                     2
4405 #define mmCM0_CM_SHAPER_RAMB_START_CNTL_R                                                              0x0df9
4406 #define mmCM0_CM_SHAPER_RAMB_START_CNTL_R_BASE_IDX                                                     2
4407 #define mmCM0_CM_SHAPER_RAMB_END_CNTL_B                                                                0x0dfa
4408 #define mmCM0_CM_SHAPER_RAMB_END_CNTL_B_BASE_IDX                                                       2
4409 #define mmCM0_CM_SHAPER_RAMB_END_CNTL_G                                                                0x0dfb
4410 #define mmCM0_CM_SHAPER_RAMB_END_CNTL_G_BASE_IDX                                                       2
4411 #define mmCM0_CM_SHAPER_RAMB_END_CNTL_R                                                                0x0dfc
4412 #define mmCM0_CM_SHAPER_RAMB_END_CNTL_R_BASE_IDX                                                       2
4413 #define mmCM0_CM_SHAPER_RAMB_REGION_0_1                                                                0x0dfd
4414 #define mmCM0_CM_SHAPER_RAMB_REGION_0_1_BASE_IDX                                                       2
4415 #define mmCM0_CM_SHAPER_RAMB_REGION_2_3                                                                0x0dfe
4416 #define mmCM0_CM_SHAPER_RAMB_REGION_2_3_BASE_IDX                                                       2
4417 #define mmCM0_CM_SHAPER_RAMB_REGION_4_5                                                                0x0dff
4418 #define mmCM0_CM_SHAPER_RAMB_REGION_4_5_BASE_IDX                                                       2
4419 #define mmCM0_CM_SHAPER_RAMB_REGION_6_7                                                                0x0e00
4420 #define mmCM0_CM_SHAPER_RAMB_REGION_6_7_BASE_IDX                                                       2
4421 #define mmCM0_CM_SHAPER_RAMB_REGION_8_9                                                                0x0e01
4422 #define mmCM0_CM_SHAPER_RAMB_REGION_8_9_BASE_IDX                                                       2
4423 #define mmCM0_CM_SHAPER_RAMB_REGION_10_11                                                              0x0e02
4424 #define mmCM0_CM_SHAPER_RAMB_REGION_10_11_BASE_IDX                                                     2
4425 #define mmCM0_CM_SHAPER_RAMB_REGION_12_13                                                              0x0e03
4426 #define mmCM0_CM_SHAPER_RAMB_REGION_12_13_BASE_IDX                                                     2
4427 #define mmCM0_CM_SHAPER_RAMB_REGION_14_15                                                              0x0e04
4428 #define mmCM0_CM_SHAPER_RAMB_REGION_14_15_BASE_IDX                                                     2
4429 #define mmCM0_CM_SHAPER_RAMB_REGION_16_17                                                              0x0e05
4430 #define mmCM0_CM_SHAPER_RAMB_REGION_16_17_BASE_IDX                                                     2
4431 #define mmCM0_CM_SHAPER_RAMB_REGION_18_19                                                              0x0e06
4432 #define mmCM0_CM_SHAPER_RAMB_REGION_18_19_BASE_IDX                                                     2
4433 #define mmCM0_CM_SHAPER_RAMB_REGION_20_21                                                              0x0e07
4434 #define mmCM0_CM_SHAPER_RAMB_REGION_20_21_BASE_IDX                                                     2
4435 #define mmCM0_CM_SHAPER_RAMB_REGION_22_23                                                              0x0e08
4436 #define mmCM0_CM_SHAPER_RAMB_REGION_22_23_BASE_IDX                                                     2
4437 #define mmCM0_CM_SHAPER_RAMB_REGION_24_25                                                              0x0e09
4438 #define mmCM0_CM_SHAPER_RAMB_REGION_24_25_BASE_IDX                                                     2
4439 #define mmCM0_CM_SHAPER_RAMB_REGION_26_27                                                              0x0e0a
4440 #define mmCM0_CM_SHAPER_RAMB_REGION_26_27_BASE_IDX                                                     2
4441 #define mmCM0_CM_SHAPER_RAMB_REGION_28_29                                                              0x0e0b
4442 #define mmCM0_CM_SHAPER_RAMB_REGION_28_29_BASE_IDX                                                     2
4443 #define mmCM0_CM_SHAPER_RAMB_REGION_30_31                                                              0x0e0c
4444 #define mmCM0_CM_SHAPER_RAMB_REGION_30_31_BASE_IDX                                                     2
4445 #define mmCM0_CM_SHAPER_RAMB_REGION_32_33                                                              0x0e0d
4446 #define mmCM0_CM_SHAPER_RAMB_REGION_32_33_BASE_IDX                                                     2
4447 #define mmCM0_CM_MEM_PWR_CTRL2                                                                         0x0e0e
4448 #define mmCM0_CM_MEM_PWR_CTRL2_BASE_IDX                                                                2
4449 #define mmCM0_CM_MEM_PWR_STATUS2                                                                       0x0e0f
4450 #define mmCM0_CM_MEM_PWR_STATUS2_BASE_IDX                                                              2
4451 #define mmCM0_CM_3DLUT_MODE                                                                            0x0e10
4452 #define mmCM0_CM_3DLUT_MODE_BASE_IDX                                                                   2
4453 #define mmCM0_CM_3DLUT_INDEX                                                                           0x0e11
4454 #define mmCM0_CM_3DLUT_INDEX_BASE_IDX                                                                  2
4455 #define mmCM0_CM_3DLUT_DATA                                                                            0x0e12
4456 #define mmCM0_CM_3DLUT_DATA_BASE_IDX                                                                   2
4457 #define mmCM0_CM_3DLUT_DATA_30BIT                                                                      0x0e13
4458 #define mmCM0_CM_3DLUT_DATA_30BIT_BASE_IDX                                                             2
4459 #define mmCM0_CM_3DLUT_READ_WRITE_CONTROL                                                              0x0e14
4460 #define mmCM0_CM_3DLUT_READ_WRITE_CONTROL_BASE_IDX                                                     2
4461 #define mmCM0_CM_3DLUT_OUT_NORM_FACTOR                                                                 0x0e15
4462 #define mmCM0_CM_3DLUT_OUT_NORM_FACTOR_BASE_IDX                                                        2
4463 #define mmCM0_CM_3DLUT_OUT_OFFSET_R                                                                    0x0e16
4464 #define mmCM0_CM_3DLUT_OUT_OFFSET_R_BASE_IDX                                                           2
4465 #define mmCM0_CM_3DLUT_OUT_OFFSET_G                                                                    0x0e17
4466 #define mmCM0_CM_3DLUT_OUT_OFFSET_G_BASE_IDX                                                           2
4467 #define mmCM0_CM_3DLUT_OUT_OFFSET_B                                                                    0x0e18
4468 #define mmCM0_CM_3DLUT_OUT_OFFSET_B_BASE_IDX                                                           2
4469 
4470 
4471 // addressBlock: dce_dc_dpp0_dispdec_dpp_dcperfmon_dc_perfmon_dispdec
4472 // base address: 0x3890
4473 #define mmDC_PERFMON11_PERFCOUNTER_CNTL                                                                0x0e24
4474 #define mmDC_PERFMON11_PERFCOUNTER_CNTL_BASE_IDX                                                       2
4475 #define mmDC_PERFMON11_PERFCOUNTER_CNTL2                                                               0x0e25
4476 #define mmDC_PERFMON11_PERFCOUNTER_CNTL2_BASE_IDX                                                      2
4477 #define mmDC_PERFMON11_PERFCOUNTER_STATE                                                               0x0e26
4478 #define mmDC_PERFMON11_PERFCOUNTER_STATE_BASE_IDX                                                      2
4479 #define mmDC_PERFMON11_PERFMON_CNTL                                                                    0x0e27
4480 #define mmDC_PERFMON11_PERFMON_CNTL_BASE_IDX                                                           2
4481 #define mmDC_PERFMON11_PERFMON_CNTL2                                                                   0x0e28
4482 #define mmDC_PERFMON11_PERFMON_CNTL2_BASE_IDX                                                          2
4483 #define mmDC_PERFMON11_PERFMON_CVALUE_INT_MISC                                                         0x0e29
4484 #define mmDC_PERFMON11_PERFMON_CVALUE_INT_MISC_BASE_IDX                                                2
4485 #define mmDC_PERFMON11_PERFMON_CVALUE_LOW                                                              0x0e2a
4486 #define mmDC_PERFMON11_PERFMON_CVALUE_LOW_BASE_IDX                                                     2
4487 #define mmDC_PERFMON11_PERFMON_HI                                                                      0x0e2b
4488 #define mmDC_PERFMON11_PERFMON_HI_BASE_IDX                                                             2
4489 #define mmDC_PERFMON11_PERFMON_LOW                                                                     0x0e2c
4490 #define mmDC_PERFMON11_PERFMON_LOW_BASE_IDX                                                            2
4491 
4492 
4493 // addressBlock: dce_dc_dpp1_dispdec_dpp_top_dispdec
4494 // base address: 0x5ac
4495 #define mmDPP_TOP1_DPP_CONTROL                                                                         0x0e30
4496 #define mmDPP_TOP1_DPP_CONTROL_BASE_IDX                                                                2
4497 #define mmDPP_TOP1_DPP_SOFT_RESET                                                                      0x0e31
4498 #define mmDPP_TOP1_DPP_SOFT_RESET_BASE_IDX                                                             2
4499 #define mmDPP_TOP1_DPP_CRC_VAL_R_G                                                                     0x0e32
4500 #define mmDPP_TOP1_DPP_CRC_VAL_R_G_BASE_IDX                                                            2
4501 #define mmDPP_TOP1_DPP_CRC_VAL_B_A                                                                     0x0e33
4502 #define mmDPP_TOP1_DPP_CRC_VAL_B_A_BASE_IDX                                                            2
4503 #define mmDPP_TOP1_DPP_CRC_CTRL                                                                        0x0e34
4504 #define mmDPP_TOP1_DPP_CRC_CTRL_BASE_IDX                                                               2
4505 #define mmDPP_TOP1_HOST_READ_CONTROL                                                                   0x0e35
4506 #define mmDPP_TOP1_HOST_READ_CONTROL_BASE_IDX                                                          2
4507 
4508 
4509 // addressBlock: dce_dc_dpp1_dispdec_cnvc_cfg_dispdec
4510 // base address: 0x5ac
4511 #define mmCNVC_CFG1_CNVC_SURFACE_PIXEL_FORMAT                                                          0x0e3a
4512 #define mmCNVC_CFG1_CNVC_SURFACE_PIXEL_FORMAT_BASE_IDX                                                 2
4513 #define mmCNVC_CFG1_FORMAT_CONTROL                                                                     0x0e3b
4514 #define mmCNVC_CFG1_FORMAT_CONTROL_BASE_IDX                                                            2
4515 #define mmCNVC_CFG1_FCNV_FP_BIAS_R                                                                     0x0e3c
4516 #define mmCNVC_CFG1_FCNV_FP_BIAS_R_BASE_IDX                                                            2
4517 #define mmCNVC_CFG1_FCNV_FP_BIAS_G                                                                     0x0e3d
4518 #define mmCNVC_CFG1_FCNV_FP_BIAS_G_BASE_IDX                                                            2
4519 #define mmCNVC_CFG1_FCNV_FP_BIAS_B                                                                     0x0e3e
4520 #define mmCNVC_CFG1_FCNV_FP_BIAS_B_BASE_IDX                                                            2
4521 #define mmCNVC_CFG1_FCNV_FP_SCALE_R                                                                    0x0e3f
4522 #define mmCNVC_CFG1_FCNV_FP_SCALE_R_BASE_IDX                                                           2
4523 #define mmCNVC_CFG1_FCNV_FP_SCALE_G                                                                    0x0e40
4524 #define mmCNVC_CFG1_FCNV_FP_SCALE_G_BASE_IDX                                                           2
4525 #define mmCNVC_CFG1_FCNV_FP_SCALE_B                                                                    0x0e41
4526 #define mmCNVC_CFG1_FCNV_FP_SCALE_B_BASE_IDX                                                           2
4527 #define mmCNVC_CFG1_COLOR_KEYER_CONTROL                                                                0x0e42
4528 #define mmCNVC_CFG1_COLOR_KEYER_CONTROL_BASE_IDX                                                       2
4529 #define mmCNVC_CFG1_COLOR_KEYER_ALPHA                                                                  0x0e43
4530 #define mmCNVC_CFG1_COLOR_KEYER_ALPHA_BASE_IDX                                                         2
4531 #define mmCNVC_CFG1_COLOR_KEYER_RED                                                                    0x0e44
4532 #define mmCNVC_CFG1_COLOR_KEYER_RED_BASE_IDX                                                           2
4533 #define mmCNVC_CFG1_COLOR_KEYER_GREEN                                                                  0x0e45
4534 #define mmCNVC_CFG1_COLOR_KEYER_GREEN_BASE_IDX                                                         2
4535 #define mmCNVC_CFG1_COLOR_KEYER_BLUE                                                                   0x0e46
4536 #define mmCNVC_CFG1_COLOR_KEYER_BLUE_BASE_IDX                                                          2
4537 #define mmCNVC_CFG1_ALPHA_2BIT_LUT                                                                     0x0e48
4538 #define mmCNVC_CFG1_ALPHA_2BIT_LUT_BASE_IDX                                                            2
4539 #define mmCNVC_CFG1_PRE_DEALPHA                                                                        0x0e49
4540 #define mmCNVC_CFG1_PRE_DEALPHA_BASE_IDX                                                               2
4541 #define mmCNVC_CFG1_PRE_CSC_MODE                                                                       0x0e4a
4542 #define mmCNVC_CFG1_PRE_CSC_MODE_BASE_IDX                                                              2
4543 #define mmCNVC_CFG1_PRE_CSC_C11_C12                                                                    0x0e4b
4544 #define mmCNVC_CFG1_PRE_CSC_C11_C12_BASE_IDX                                                           2
4545 #define mmCNVC_CFG1_PRE_CSC_C13_C14                                                                    0x0e4c
4546 #define mmCNVC_CFG1_PRE_CSC_C13_C14_BASE_IDX                                                           2
4547 #define mmCNVC_CFG1_PRE_CSC_C21_C22                                                                    0x0e4d
4548 #define mmCNVC_CFG1_PRE_CSC_C21_C22_BASE_IDX                                                           2
4549 #define mmCNVC_CFG1_PRE_CSC_C23_C24                                                                    0x0e4e
4550 #define mmCNVC_CFG1_PRE_CSC_C23_C24_BASE_IDX                                                           2
4551 #define mmCNVC_CFG1_PRE_CSC_C31_C32                                                                    0x0e4f
4552 #define mmCNVC_CFG1_PRE_CSC_C31_C32_BASE_IDX                                                           2
4553 #define mmCNVC_CFG1_PRE_CSC_C33_C34                                                                    0x0e50
4554 #define mmCNVC_CFG1_PRE_CSC_C33_C34_BASE_IDX                                                           2
4555 #define mmCNVC_CFG1_PRE_CSC_B_C11_C12                                                                  0x0e51
4556 #define mmCNVC_CFG1_PRE_CSC_B_C11_C12_BASE_IDX                                                         2
4557 #define mmCNVC_CFG1_PRE_CSC_B_C13_C14                                                                  0x0e52
4558 #define mmCNVC_CFG1_PRE_CSC_B_C13_C14_BASE_IDX                                                         2
4559 #define mmCNVC_CFG1_PRE_CSC_B_C21_C22                                                                  0x0e53
4560 #define mmCNVC_CFG1_PRE_CSC_B_C21_C22_BASE_IDX                                                         2
4561 #define mmCNVC_CFG1_PRE_CSC_B_C23_C24                                                                  0x0e54
4562 #define mmCNVC_CFG1_PRE_CSC_B_C23_C24_BASE_IDX                                                         2
4563 #define mmCNVC_CFG1_PRE_CSC_B_C31_C32                                                                  0x0e55
4564 #define mmCNVC_CFG1_PRE_CSC_B_C31_C32_BASE_IDX                                                         2
4565 #define mmCNVC_CFG1_PRE_CSC_B_C33_C34                                                                  0x0e56
4566 #define mmCNVC_CFG1_PRE_CSC_B_C33_C34_BASE_IDX                                                         2
4567 #define mmCNVC_CFG1_CNVC_COEF_FORMAT                                                                   0x0e57
4568 #define mmCNVC_CFG1_CNVC_COEF_FORMAT_BASE_IDX                                                          2
4569 #define mmCNVC_CFG1_PRE_DEGAM                                                                          0x0e58
4570 #define mmCNVC_CFG1_PRE_DEGAM_BASE_IDX                                                                 2
4571 #define mmCNVC_CFG1_PRE_REALPHA                                                                        0x0e59
4572 #define mmCNVC_CFG1_PRE_REALPHA_BASE_IDX                                                               2
4573 
4574 
4575 // addressBlock: dce_dc_dpp1_dispdec_cnvc_cur_dispdec
4576 // base address: 0x5ac
4577 #define mmCNVC_CUR1_CURSOR0_CONTROL                                                                    0x0e5c
4578 #define mmCNVC_CUR1_CURSOR0_CONTROL_BASE_IDX                                                           2
4579 #define mmCNVC_CUR1_CURSOR0_COLOR0                                                                     0x0e5d
4580 #define mmCNVC_CUR1_CURSOR0_COLOR0_BASE_IDX                                                            2
4581 #define mmCNVC_CUR1_CURSOR0_COLOR1                                                                     0x0e5e
4582 #define mmCNVC_CUR1_CURSOR0_COLOR1_BASE_IDX                                                            2
4583 #define mmCNVC_CUR1_CURSOR0_FP_SCALE_BIAS                                                              0x0e5f
4584 #define mmCNVC_CUR1_CURSOR0_FP_SCALE_BIAS_BASE_IDX                                                     2
4585 
4586 
4587 // addressBlock: dce_dc_dpp1_dispdec_dscl_dispdec
4588 // base address: 0x5ac
4589 #define mmDSCL1_SCL_COEF_RAM_TAP_SELECT                                                                0x0e64
4590 #define mmDSCL1_SCL_COEF_RAM_TAP_SELECT_BASE_IDX                                                       2
4591 #define mmDSCL1_SCL_COEF_RAM_TAP_DATA                                                                  0x0e65
4592 #define mmDSCL1_SCL_COEF_RAM_TAP_DATA_BASE_IDX                                                         2
4593 #define mmDSCL1_SCL_MODE                                                                               0x0e66
4594 #define mmDSCL1_SCL_MODE_BASE_IDX                                                                      2
4595 #define mmDSCL1_SCL_TAP_CONTROL                                                                        0x0e67
4596 #define mmDSCL1_SCL_TAP_CONTROL_BASE_IDX                                                               2
4597 #define mmDSCL1_DSCL_CONTROL                                                                           0x0e68
4598 #define mmDSCL1_DSCL_CONTROL_BASE_IDX                                                                  2
4599 #define mmDSCL1_DSCL_2TAP_CONTROL                                                                      0x0e69
4600 #define mmDSCL1_DSCL_2TAP_CONTROL_BASE_IDX                                                             2
4601 #define mmDSCL1_SCL_MANUAL_REPLICATE_CONTROL                                                           0x0e6a
4602 #define mmDSCL1_SCL_MANUAL_REPLICATE_CONTROL_BASE_IDX                                                  2
4603 #define mmDSCL1_SCL_HORZ_FILTER_SCALE_RATIO                                                            0x0e6b
4604 #define mmDSCL1_SCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX                                                   2
4605 #define mmDSCL1_SCL_HORZ_FILTER_INIT                                                                   0x0e6c
4606 #define mmDSCL1_SCL_HORZ_FILTER_INIT_BASE_IDX                                                          2
4607 #define mmDSCL1_SCL_HORZ_FILTER_SCALE_RATIO_C                                                          0x0e6d
4608 #define mmDSCL1_SCL_HORZ_FILTER_SCALE_RATIO_C_BASE_IDX                                                 2
4609 #define mmDSCL1_SCL_HORZ_FILTER_INIT_C                                                                 0x0e6e
4610 #define mmDSCL1_SCL_HORZ_FILTER_INIT_C_BASE_IDX                                                        2
4611 #define mmDSCL1_SCL_VERT_FILTER_SCALE_RATIO                                                            0x0e6f
4612 #define mmDSCL1_SCL_VERT_FILTER_SCALE_RATIO_BASE_IDX                                                   2
4613 #define mmDSCL1_SCL_VERT_FILTER_INIT                                                                   0x0e70
4614 #define mmDSCL1_SCL_VERT_FILTER_INIT_BASE_IDX                                                          2
4615 #define mmDSCL1_SCL_VERT_FILTER_INIT_BOT                                                               0x0e71
4616 #define mmDSCL1_SCL_VERT_FILTER_INIT_BOT_BASE_IDX                                                      2
4617 #define mmDSCL1_SCL_VERT_FILTER_SCALE_RATIO_C                                                          0x0e72
4618 #define mmDSCL1_SCL_VERT_FILTER_SCALE_RATIO_C_BASE_IDX                                                 2
4619 #define mmDSCL1_SCL_VERT_FILTER_INIT_C                                                                 0x0e73
4620 #define mmDSCL1_SCL_VERT_FILTER_INIT_C_BASE_IDX                                                        2
4621 #define mmDSCL1_SCL_VERT_FILTER_INIT_BOT_C                                                             0x0e74
4622 #define mmDSCL1_SCL_VERT_FILTER_INIT_BOT_C_BASE_IDX                                                    2
4623 #define mmDSCL1_SCL_BLACK_COLOR                                                                        0x0e75
4624 #define mmDSCL1_SCL_BLACK_COLOR_BASE_IDX                                                               2
4625 #define mmDSCL1_DSCL_UPDATE                                                                            0x0e76
4626 #define mmDSCL1_DSCL_UPDATE_BASE_IDX                                                                   2
4627 #define mmDSCL1_DSCL_AUTOCAL                                                                           0x0e77
4628 #define mmDSCL1_DSCL_AUTOCAL_BASE_IDX                                                                  2
4629 #define mmDSCL1_DSCL_EXT_OVERSCAN_LEFT_RIGHT                                                           0x0e78
4630 #define mmDSCL1_DSCL_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX                                                  2
4631 #define mmDSCL1_DSCL_EXT_OVERSCAN_TOP_BOTTOM                                                           0x0e79
4632 #define mmDSCL1_DSCL_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX                                                  2
4633 #define mmDSCL1_OTG_H_BLANK                                                                            0x0e7a
4634 #define mmDSCL1_OTG_H_BLANK_BASE_IDX                                                                   2
4635 #define mmDSCL1_OTG_V_BLANK                                                                            0x0e7b
4636 #define mmDSCL1_OTG_V_BLANK_BASE_IDX                                                                   2
4637 #define mmDSCL1_RECOUT_START                                                                           0x0e7c
4638 #define mmDSCL1_RECOUT_START_BASE_IDX                                                                  2
4639 #define mmDSCL1_RECOUT_SIZE                                                                            0x0e7d
4640 #define mmDSCL1_RECOUT_SIZE_BASE_IDX                                                                   2
4641 #define mmDSCL1_MPC_SIZE                                                                               0x0e7e
4642 #define mmDSCL1_MPC_SIZE_BASE_IDX                                                                      2
4643 #define mmDSCL1_LB_DATA_FORMAT                                                                         0x0e7f
4644 #define mmDSCL1_LB_DATA_FORMAT_BASE_IDX                                                                2
4645 #define mmDSCL1_LB_MEMORY_CTRL                                                                         0x0e80
4646 #define mmDSCL1_LB_MEMORY_CTRL_BASE_IDX                                                                2
4647 #define mmDSCL1_LB_V_COUNTER                                                                           0x0e81
4648 #define mmDSCL1_LB_V_COUNTER_BASE_IDX                                                                  2
4649 #define mmDSCL1_DSCL_MEM_PWR_CTRL                                                                      0x0e82
4650 #define mmDSCL1_DSCL_MEM_PWR_CTRL_BASE_IDX                                                             2
4651 #define mmDSCL1_DSCL_MEM_PWR_STATUS                                                                    0x0e83
4652 #define mmDSCL1_DSCL_MEM_PWR_STATUS_BASE_IDX                                                           2
4653 #define mmDSCL1_OBUF_CONTROL                                                                           0x0e84
4654 #define mmDSCL1_OBUF_CONTROL_BASE_IDX                                                                  2
4655 #define mmDSCL1_OBUF_MEM_PWR_CTRL                                                                      0x0e85
4656 #define mmDSCL1_OBUF_MEM_PWR_CTRL_BASE_IDX                                                             2
4657 
4658 
4659 // addressBlock: dce_dc_dpp1_dispdec_cm_dispdec
4660 // base address: 0x5ac
4661 #define mmCM1_CM_CONTROL                                                                               0x0e8b
4662 #define mmCM1_CM_CONTROL_BASE_IDX                                                                      2
4663 #define mmCM1_CM_POST_CSC_CONTROL                                                                      0x0e8c
4664 #define mmCM1_CM_POST_CSC_CONTROL_BASE_IDX                                                             2
4665 #define mmCM1_CM_POST_CSC_C11_C12                                                                      0x0e8d
4666 #define mmCM1_CM_POST_CSC_C11_C12_BASE_IDX                                                             2
4667 #define mmCM1_CM_POST_CSC_C13_C14                                                                      0x0e8e
4668 #define mmCM1_CM_POST_CSC_C13_C14_BASE_IDX                                                             2
4669 #define mmCM1_CM_POST_CSC_C21_C22                                                                      0x0e8f
4670 #define mmCM1_CM_POST_CSC_C21_C22_BASE_IDX                                                             2
4671 #define mmCM1_CM_POST_CSC_C23_C24                                                                      0x0e90
4672 #define mmCM1_CM_POST_CSC_C23_C24_BASE_IDX                                                             2
4673 #define mmCM1_CM_POST_CSC_C31_C32                                                                      0x0e91
4674 #define mmCM1_CM_POST_CSC_C31_C32_BASE_IDX                                                             2
4675 #define mmCM1_CM_POST_CSC_C33_C34                                                                      0x0e92
4676 #define mmCM1_CM_POST_CSC_C33_C34_BASE_IDX                                                             2
4677 #define mmCM1_CM_POST_CSC_B_C11_C12                                                                    0x0e93
4678 #define mmCM1_CM_POST_CSC_B_C11_C12_BASE_IDX                                                           2
4679 #define mmCM1_CM_POST_CSC_B_C13_C14                                                                    0x0e94
4680 #define mmCM1_CM_POST_CSC_B_C13_C14_BASE_IDX                                                           2
4681 #define mmCM1_CM_POST_CSC_B_C21_C22                                                                    0x0e95
4682 #define mmCM1_CM_POST_CSC_B_C21_C22_BASE_IDX                                                           2
4683 #define mmCM1_CM_POST_CSC_B_C23_C24                                                                    0x0e96
4684 #define mmCM1_CM_POST_CSC_B_C23_C24_BASE_IDX                                                           2
4685 #define mmCM1_CM_POST_CSC_B_C31_C32                                                                    0x0e97
4686 #define mmCM1_CM_POST_CSC_B_C31_C32_BASE_IDX                                                           2
4687 #define mmCM1_CM_POST_CSC_B_C33_C34                                                                    0x0e98
4688 #define mmCM1_CM_POST_CSC_B_C33_C34_BASE_IDX                                                           2
4689 #define mmCM1_CM_GAMUT_REMAP_CONTROL                                                                   0x0e99
4690 #define mmCM1_CM_GAMUT_REMAP_CONTROL_BASE_IDX                                                          2
4691 #define mmCM1_CM_GAMUT_REMAP_C11_C12                                                                   0x0e9a
4692 #define mmCM1_CM_GAMUT_REMAP_C11_C12_BASE_IDX                                                          2
4693 #define mmCM1_CM_GAMUT_REMAP_C13_C14                                                                   0x0e9b
4694 #define mmCM1_CM_GAMUT_REMAP_C13_C14_BASE_IDX                                                          2
4695 #define mmCM1_CM_GAMUT_REMAP_C21_C22                                                                   0x0e9c
4696 #define mmCM1_CM_GAMUT_REMAP_C21_C22_BASE_IDX                                                          2
4697 #define mmCM1_CM_GAMUT_REMAP_C23_C24                                                                   0x0e9d
4698 #define mmCM1_CM_GAMUT_REMAP_C23_C24_BASE_IDX                                                          2
4699 #define mmCM1_CM_GAMUT_REMAP_C31_C32                                                                   0x0e9e
4700 #define mmCM1_CM_GAMUT_REMAP_C31_C32_BASE_IDX                                                          2
4701 #define mmCM1_CM_GAMUT_REMAP_C33_C34                                                                   0x0e9f
4702 #define mmCM1_CM_GAMUT_REMAP_C33_C34_BASE_IDX                                                          2
4703 #define mmCM1_CM_GAMUT_REMAP_B_C11_C12                                                                 0x0ea0
4704 #define mmCM1_CM_GAMUT_REMAP_B_C11_C12_BASE_IDX                                                        2
4705 #define mmCM1_CM_GAMUT_REMAP_B_C13_C14                                                                 0x0ea1
4706 #define mmCM1_CM_GAMUT_REMAP_B_C13_C14_BASE_IDX                                                        2
4707 #define mmCM1_CM_GAMUT_REMAP_B_C21_C22                                                                 0x0ea2
4708 #define mmCM1_CM_GAMUT_REMAP_B_C21_C22_BASE_IDX                                                        2
4709 #define mmCM1_CM_GAMUT_REMAP_B_C23_C24                                                                 0x0ea3
4710 #define mmCM1_CM_GAMUT_REMAP_B_C23_C24_BASE_IDX                                                        2
4711 #define mmCM1_CM_GAMUT_REMAP_B_C31_C32                                                                 0x0ea4
4712 #define mmCM1_CM_GAMUT_REMAP_B_C31_C32_BASE_IDX                                                        2
4713 #define mmCM1_CM_GAMUT_REMAP_B_C33_C34                                                                 0x0ea5
4714 #define mmCM1_CM_GAMUT_REMAP_B_C33_C34_BASE_IDX                                                        2
4715 #define mmCM1_CM_BIAS_CR_R                                                                             0x0ea6
4716 #define mmCM1_CM_BIAS_CR_R_BASE_IDX                                                                    2
4717 #define mmCM1_CM_BIAS_Y_G_CB_B                                                                         0x0ea7
4718 #define mmCM1_CM_BIAS_Y_G_CB_B_BASE_IDX                                                                2
4719 #define mmCM1_CM_GAMCOR_CONTROL                                                                        0x0ea8
4720 #define mmCM1_CM_GAMCOR_CONTROL_BASE_IDX                                                               2
4721 #define mmCM1_CM_GAMCOR_LUT_INDEX                                                                      0x0ea9
4722 #define mmCM1_CM_GAMCOR_LUT_INDEX_BASE_IDX                                                             2
4723 #define mmCM1_CM_GAMCOR_LUT_DATA                                                                       0x0eaa
4724 #define mmCM1_CM_GAMCOR_LUT_DATA_BASE_IDX                                                              2
4725 #define mmCM1_CM_GAMCOR_LUT_CONTROL                                                                    0x0eab
4726 #define mmCM1_CM_GAMCOR_LUT_CONTROL_BASE_IDX                                                           2
4727 #define mmCM1_CM_GAMCOR_RAMA_START_CNTL_B                                                              0x0eac
4728 #define mmCM1_CM_GAMCOR_RAMA_START_CNTL_B_BASE_IDX                                                     2
4729 #define mmCM1_CM_GAMCOR_RAMA_START_CNTL_G                                                              0x0ead
4730 #define mmCM1_CM_GAMCOR_RAMA_START_CNTL_G_BASE_IDX                                                     2
4731 #define mmCM1_CM_GAMCOR_RAMA_START_CNTL_R                                                              0x0eae
4732 #define mmCM1_CM_GAMCOR_RAMA_START_CNTL_R_BASE_IDX                                                     2
4733 #define mmCM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B                                                        0x0eaf
4734 #define mmCM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B_BASE_IDX                                               2
4735 #define mmCM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G                                                        0x0eb0
4736 #define mmCM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G_BASE_IDX                                               2
4737 #define mmCM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R                                                        0x0eb1
4738 #define mmCM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R_BASE_IDX                                               2
4739 #define mmCM1_CM_GAMCOR_RAMA_START_BASE_CNTL_B                                                         0x0eb2
4740 #define mmCM1_CM_GAMCOR_RAMA_START_BASE_CNTL_B_BASE_IDX                                                2
4741 #define mmCM1_CM_GAMCOR_RAMA_START_BASE_CNTL_G                                                         0x0eb3
4742 #define mmCM1_CM_GAMCOR_RAMA_START_BASE_CNTL_G_BASE_IDX                                                2
4743 #define mmCM1_CM_GAMCOR_RAMA_START_BASE_CNTL_R                                                         0x0eb4
4744 #define mmCM1_CM_GAMCOR_RAMA_START_BASE_CNTL_R_BASE_IDX                                                2
4745 #define mmCM1_CM_GAMCOR_RAMA_END_CNTL1_B                                                               0x0eb5
4746 #define mmCM1_CM_GAMCOR_RAMA_END_CNTL1_B_BASE_IDX                                                      2
4747 #define mmCM1_CM_GAMCOR_RAMA_END_CNTL2_B                                                               0x0eb6
4748 #define mmCM1_CM_GAMCOR_RAMA_END_CNTL2_B_BASE_IDX                                                      2
4749 #define mmCM1_CM_GAMCOR_RAMA_END_CNTL1_G                                                               0x0eb7
4750 #define mmCM1_CM_GAMCOR_RAMA_END_CNTL1_G_BASE_IDX                                                      2
4751 #define mmCM1_CM_GAMCOR_RAMA_END_CNTL2_G                                                               0x0eb8
4752 #define mmCM1_CM_GAMCOR_RAMA_END_CNTL2_G_BASE_IDX                                                      2
4753 #define mmCM1_CM_GAMCOR_RAMA_END_CNTL1_R                                                               0x0eb9
4754 #define mmCM1_CM_GAMCOR_RAMA_END_CNTL1_R_BASE_IDX                                                      2
4755 #define mmCM1_CM_GAMCOR_RAMA_END_CNTL2_R                                                               0x0eba
4756 #define mmCM1_CM_GAMCOR_RAMA_END_CNTL2_R_BASE_IDX                                                      2
4757 #define mmCM1_CM_GAMCOR_RAMA_OFFSET_B                                                                  0x0ebb
4758 #define mmCM1_CM_GAMCOR_RAMA_OFFSET_B_BASE_IDX                                                         2
4759 #define mmCM1_CM_GAMCOR_RAMA_OFFSET_G                                                                  0x0ebc
4760 #define mmCM1_CM_GAMCOR_RAMA_OFFSET_G_BASE_IDX                                                         2
4761 #define mmCM1_CM_GAMCOR_RAMA_OFFSET_R                                                                  0x0ebd
4762 #define mmCM1_CM_GAMCOR_RAMA_OFFSET_R_BASE_IDX                                                         2
4763 #define mmCM1_CM_GAMCOR_RAMA_REGION_0_1                                                                0x0ebe
4764 #define mmCM1_CM_GAMCOR_RAMA_REGION_0_1_BASE_IDX                                                       2
4765 #define mmCM1_CM_GAMCOR_RAMA_REGION_2_3                                                                0x0ebf
4766 #define mmCM1_CM_GAMCOR_RAMA_REGION_2_3_BASE_IDX                                                       2
4767 #define mmCM1_CM_GAMCOR_RAMA_REGION_4_5                                                                0x0ec0
4768 #define mmCM1_CM_GAMCOR_RAMA_REGION_4_5_BASE_IDX                                                       2
4769 #define mmCM1_CM_GAMCOR_RAMA_REGION_6_7                                                                0x0ec1
4770 #define mmCM1_CM_GAMCOR_RAMA_REGION_6_7_BASE_IDX                                                       2
4771 #define mmCM1_CM_GAMCOR_RAMA_REGION_8_9                                                                0x0ec2
4772 #define mmCM1_CM_GAMCOR_RAMA_REGION_8_9_BASE_IDX                                                       2
4773 #define mmCM1_CM_GAMCOR_RAMA_REGION_10_11                                                              0x0ec3
4774 #define mmCM1_CM_GAMCOR_RAMA_REGION_10_11_BASE_IDX                                                     2
4775 #define mmCM1_CM_GAMCOR_RAMA_REGION_12_13                                                              0x0ec4
4776 #define mmCM1_CM_GAMCOR_RAMA_REGION_12_13_BASE_IDX                                                     2
4777 #define mmCM1_CM_GAMCOR_RAMA_REGION_14_15                                                              0x0ec5
4778 #define mmCM1_CM_GAMCOR_RAMA_REGION_14_15_BASE_IDX                                                     2
4779 #define mmCM1_CM_GAMCOR_RAMA_REGION_16_17                                                              0x0ec6
4780 #define mmCM1_CM_GAMCOR_RAMA_REGION_16_17_BASE_IDX                                                     2
4781 #define mmCM1_CM_GAMCOR_RAMA_REGION_18_19                                                              0x0ec7
4782 #define mmCM1_CM_GAMCOR_RAMA_REGION_18_19_BASE_IDX                                                     2
4783 #define mmCM1_CM_GAMCOR_RAMA_REGION_20_21                                                              0x0ec8
4784 #define mmCM1_CM_GAMCOR_RAMA_REGION_20_21_BASE_IDX                                                     2
4785 #define mmCM1_CM_GAMCOR_RAMA_REGION_22_23                                                              0x0ec9
4786 #define mmCM1_CM_GAMCOR_RAMA_REGION_22_23_BASE_IDX                                                     2
4787 #define mmCM1_CM_GAMCOR_RAMA_REGION_24_25                                                              0x0eca
4788 #define mmCM1_CM_GAMCOR_RAMA_REGION_24_25_BASE_IDX                                                     2
4789 #define mmCM1_CM_GAMCOR_RAMA_REGION_26_27                                                              0x0ecb
4790 #define mmCM1_CM_GAMCOR_RAMA_REGION_26_27_BASE_IDX                                                     2
4791 #define mmCM1_CM_GAMCOR_RAMA_REGION_28_29                                                              0x0ecc
4792 #define mmCM1_CM_GAMCOR_RAMA_REGION_28_29_BASE_IDX                                                     2
4793 #define mmCM1_CM_GAMCOR_RAMA_REGION_30_31                                                              0x0ecd
4794 #define mmCM1_CM_GAMCOR_RAMA_REGION_30_31_BASE_IDX                                                     2
4795 #define mmCM1_CM_GAMCOR_RAMA_REGION_32_33                                                              0x0ece
4796 #define mmCM1_CM_GAMCOR_RAMA_REGION_32_33_BASE_IDX                                                     2
4797 #define mmCM1_CM_GAMCOR_RAMB_START_CNTL_B                                                              0x0ecf
4798 #define mmCM1_CM_GAMCOR_RAMB_START_CNTL_B_BASE_IDX                                                     2
4799 #define mmCM1_CM_GAMCOR_RAMB_START_CNTL_G                                                              0x0ed0
4800 #define mmCM1_CM_GAMCOR_RAMB_START_CNTL_G_BASE_IDX                                                     2
4801 #define mmCM1_CM_GAMCOR_RAMB_START_CNTL_R                                                              0x0ed1
4802 #define mmCM1_CM_GAMCOR_RAMB_START_CNTL_R_BASE_IDX                                                     2
4803 #define mmCM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B                                                        0x0ed2
4804 #define mmCM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B_BASE_IDX                                               2
4805 #define mmCM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G                                                        0x0ed3
4806 #define mmCM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G_BASE_IDX                                               2
4807 #define mmCM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R                                                        0x0ed4
4808 #define mmCM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R_BASE_IDX                                               2
4809 #define mmCM1_CM_GAMCOR_RAMB_START_BASE_CNTL_B                                                         0x0ed5
4810 #define mmCM1_CM_GAMCOR_RAMB_START_BASE_CNTL_B_BASE_IDX                                                2
4811 #define mmCM1_CM_GAMCOR_RAMB_START_BASE_CNTL_G                                                         0x0ed6
4812 #define mmCM1_CM_GAMCOR_RAMB_START_BASE_CNTL_G_BASE_IDX                                                2
4813 #define mmCM1_CM_GAMCOR_RAMB_START_BASE_CNTL_R                                                         0x0ed7
4814 #define mmCM1_CM_GAMCOR_RAMB_START_BASE_CNTL_R_BASE_IDX                                                2
4815 #define mmCM1_CM_GAMCOR_RAMB_END_CNTL1_B                                                               0x0ed8
4816 #define mmCM1_CM_GAMCOR_RAMB_END_CNTL1_B_BASE_IDX                                                      2
4817 #define mmCM1_CM_GAMCOR_RAMB_END_CNTL2_B                                                               0x0ed9
4818 #define mmCM1_CM_GAMCOR_RAMB_END_CNTL2_B_BASE_IDX                                                      2
4819 #define mmCM1_CM_GAMCOR_RAMB_END_CNTL1_G                                                               0x0eda
4820 #define mmCM1_CM_GAMCOR_RAMB_END_CNTL1_G_BASE_IDX                                                      2
4821 #define mmCM1_CM_GAMCOR_RAMB_END_CNTL2_G                                                               0x0edb
4822 #define mmCM1_CM_GAMCOR_RAMB_END_CNTL2_G_BASE_IDX                                                      2
4823 #define mmCM1_CM_GAMCOR_RAMB_END_CNTL1_R                                                               0x0edc
4824 #define mmCM1_CM_GAMCOR_RAMB_END_CNTL1_R_BASE_IDX                                                      2
4825 #define mmCM1_CM_GAMCOR_RAMB_END_CNTL2_R                                                               0x0edd
4826 #define mmCM1_CM_GAMCOR_RAMB_END_CNTL2_R_BASE_IDX                                                      2
4827 #define mmCM1_CM_GAMCOR_RAMB_OFFSET_B                                                                  0x0ede
4828 #define mmCM1_CM_GAMCOR_RAMB_OFFSET_B_BASE_IDX                                                         2
4829 #define mmCM1_CM_GAMCOR_RAMB_OFFSET_G                                                                  0x0edf
4830 #define mmCM1_CM_GAMCOR_RAMB_OFFSET_G_BASE_IDX                                                         2
4831 #define mmCM1_CM_GAMCOR_RAMB_OFFSET_R                                                                  0x0ee0
4832 #define mmCM1_CM_GAMCOR_RAMB_OFFSET_R_BASE_IDX                                                         2
4833 #define mmCM1_CM_GAMCOR_RAMB_REGION_0_1                                                                0x0ee1
4834 #define mmCM1_CM_GAMCOR_RAMB_REGION_0_1_BASE_IDX                                                       2
4835 #define mmCM1_CM_GAMCOR_RAMB_REGION_2_3                                                                0x0ee2
4836 #define mmCM1_CM_GAMCOR_RAMB_REGION_2_3_BASE_IDX                                                       2
4837 #define mmCM1_CM_GAMCOR_RAMB_REGION_4_5                                                                0x0ee3
4838 #define mmCM1_CM_GAMCOR_RAMB_REGION_4_5_BASE_IDX                                                       2
4839 #define mmCM1_CM_GAMCOR_RAMB_REGION_6_7                                                                0x0ee4
4840 #define mmCM1_CM_GAMCOR_RAMB_REGION_6_7_BASE_IDX                                                       2
4841 #define mmCM1_CM_GAMCOR_RAMB_REGION_8_9                                                                0x0ee5
4842 #define mmCM1_CM_GAMCOR_RAMB_REGION_8_9_BASE_IDX                                                       2
4843 #define mmCM1_CM_GAMCOR_RAMB_REGION_10_11                                                              0x0ee6
4844 #define mmCM1_CM_GAMCOR_RAMB_REGION_10_11_BASE_IDX                                                     2
4845 #define mmCM1_CM_GAMCOR_RAMB_REGION_12_13                                                              0x0ee7
4846 #define mmCM1_CM_GAMCOR_RAMB_REGION_12_13_BASE_IDX                                                     2
4847 #define mmCM1_CM_GAMCOR_RAMB_REGION_14_15                                                              0x0ee8
4848 #define mmCM1_CM_GAMCOR_RAMB_REGION_14_15_BASE_IDX                                                     2
4849 #define mmCM1_CM_GAMCOR_RAMB_REGION_16_17                                                              0x0ee9
4850 #define mmCM1_CM_GAMCOR_RAMB_REGION_16_17_BASE_IDX                                                     2
4851 #define mmCM1_CM_GAMCOR_RAMB_REGION_18_19                                                              0x0eea
4852 #define mmCM1_CM_GAMCOR_RAMB_REGION_18_19_BASE_IDX                                                     2
4853 #define mmCM1_CM_GAMCOR_RAMB_REGION_20_21                                                              0x0eeb
4854 #define mmCM1_CM_GAMCOR_RAMB_REGION_20_21_BASE_IDX                                                     2
4855 #define mmCM1_CM_GAMCOR_RAMB_REGION_22_23                                                              0x0eec
4856 #define mmCM1_CM_GAMCOR_RAMB_REGION_22_23_BASE_IDX                                                     2
4857 #define mmCM1_CM_GAMCOR_RAMB_REGION_24_25                                                              0x0eed
4858 #define mmCM1_CM_GAMCOR_RAMB_REGION_24_25_BASE_IDX                                                     2
4859 #define mmCM1_CM_GAMCOR_RAMB_REGION_26_27                                                              0x0eee
4860 #define mmCM1_CM_GAMCOR_RAMB_REGION_26_27_BASE_IDX                                                     2
4861 #define mmCM1_CM_GAMCOR_RAMB_REGION_28_29                                                              0x0eef
4862 #define mmCM1_CM_GAMCOR_RAMB_REGION_28_29_BASE_IDX                                                     2
4863 #define mmCM1_CM_GAMCOR_RAMB_REGION_30_31                                                              0x0ef0
4864 #define mmCM1_CM_GAMCOR_RAMB_REGION_30_31_BASE_IDX                                                     2
4865 #define mmCM1_CM_GAMCOR_RAMB_REGION_32_33                                                              0x0ef1
4866 #define mmCM1_CM_GAMCOR_RAMB_REGION_32_33_BASE_IDX                                                     2
4867 #define mmCM1_CM_BLNDGAM_CONTROL                                                                       0x0ef2
4868 #define mmCM1_CM_BLNDGAM_CONTROL_BASE_IDX                                                              2
4869 #define mmCM1_CM_BLNDGAM_LUT_INDEX                                                                     0x0ef3
4870 #define mmCM1_CM_BLNDGAM_LUT_INDEX_BASE_IDX                                                            2
4871 #define mmCM1_CM_BLNDGAM_LUT_DATA                                                                      0x0ef4
4872 #define mmCM1_CM_BLNDGAM_LUT_DATA_BASE_IDX                                                             2
4873 #define mmCM1_CM_BLNDGAM_LUT_CONTROL                                                                   0x0ef5
4874 #define mmCM1_CM_BLNDGAM_LUT_CONTROL_BASE_IDX                                                          2
4875 #define mmCM1_CM_BLNDGAM_RAMA_START_CNTL_B                                                             0x0ef6
4876 #define mmCM1_CM_BLNDGAM_RAMA_START_CNTL_B_BASE_IDX                                                    2
4877 #define mmCM1_CM_BLNDGAM_RAMA_START_CNTL_G                                                             0x0ef7
4878 #define mmCM1_CM_BLNDGAM_RAMA_START_CNTL_G_BASE_IDX                                                    2
4879 #define mmCM1_CM_BLNDGAM_RAMA_START_CNTL_R                                                             0x0ef8
4880 #define mmCM1_CM_BLNDGAM_RAMA_START_CNTL_R_BASE_IDX                                                    2
4881 #define mmCM1_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_B                                                       0x0ef9
4882 #define mmCM1_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_B_BASE_IDX                                              2
4883 #define mmCM1_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_G                                                       0x0efa
4884 #define mmCM1_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_G_BASE_IDX                                              2
4885 #define mmCM1_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_R                                                       0x0efb
4886 #define mmCM1_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_R_BASE_IDX                                              2
4887 #define mmCM1_CM_BLNDGAM_RAMA_START_BASE_CNTL_B                                                        0x0efc
4888 #define mmCM1_CM_BLNDGAM_RAMA_START_BASE_CNTL_B_BASE_IDX                                               2
4889 #define mmCM1_CM_BLNDGAM_RAMA_START_BASE_CNTL_G                                                        0x0efd
4890 #define mmCM1_CM_BLNDGAM_RAMA_START_BASE_CNTL_G_BASE_IDX                                               2
4891 #define mmCM1_CM_BLNDGAM_RAMA_START_BASE_CNTL_R                                                        0x0efe
4892 #define mmCM1_CM_BLNDGAM_RAMA_START_BASE_CNTL_R_BASE_IDX                                               2
4893 #define mmCM1_CM_BLNDGAM_RAMA_END_CNTL1_B                                                              0x0eff
4894 #define mmCM1_CM_BLNDGAM_RAMA_END_CNTL1_B_BASE_IDX                                                     2
4895 #define mmCM1_CM_BLNDGAM_RAMA_END_CNTL2_B                                                              0x0f00
4896 #define mmCM1_CM_BLNDGAM_RAMA_END_CNTL2_B_BASE_IDX                                                     2
4897 #define mmCM1_CM_BLNDGAM_RAMA_END_CNTL1_G                                                              0x0f01
4898 #define mmCM1_CM_BLNDGAM_RAMA_END_CNTL1_G_BASE_IDX                                                     2
4899 #define mmCM1_CM_BLNDGAM_RAMA_END_CNTL2_G                                                              0x0f02
4900 #define mmCM1_CM_BLNDGAM_RAMA_END_CNTL2_G_BASE_IDX                                                     2
4901 #define mmCM1_CM_BLNDGAM_RAMA_END_CNTL1_R                                                              0x0f03
4902 #define mmCM1_CM_BLNDGAM_RAMA_END_CNTL1_R_BASE_IDX                                                     2
4903 #define mmCM1_CM_BLNDGAM_RAMA_END_CNTL2_R                                                              0x0f04
4904 #define mmCM1_CM_BLNDGAM_RAMA_END_CNTL2_R_BASE_IDX                                                     2
4905 #define mmCM1_CM_BLNDGAM_RAMA_OFFSET_B                                                                 0x0f05
4906 #define mmCM1_CM_BLNDGAM_RAMA_OFFSET_B_BASE_IDX                                                        2
4907 #define mmCM1_CM_BLNDGAM_RAMA_OFFSET_G                                                                 0x0f06
4908 #define mmCM1_CM_BLNDGAM_RAMA_OFFSET_G_BASE_IDX                                                        2
4909 #define mmCM1_CM_BLNDGAM_RAMA_OFFSET_R                                                                 0x0f07
4910 #define mmCM1_CM_BLNDGAM_RAMA_OFFSET_R_BASE_IDX                                                        2
4911 #define mmCM1_CM_BLNDGAM_RAMA_REGION_0_1                                                               0x0f08
4912 #define mmCM1_CM_BLNDGAM_RAMA_REGION_0_1_BASE_IDX                                                      2
4913 #define mmCM1_CM_BLNDGAM_RAMA_REGION_2_3                                                               0x0f09
4914 #define mmCM1_CM_BLNDGAM_RAMA_REGION_2_3_BASE_IDX                                                      2
4915 #define mmCM1_CM_BLNDGAM_RAMA_REGION_4_5                                                               0x0f0a
4916 #define mmCM1_CM_BLNDGAM_RAMA_REGION_4_5_BASE_IDX                                                      2
4917 #define mmCM1_CM_BLNDGAM_RAMA_REGION_6_7                                                               0x0f0b
4918 #define mmCM1_CM_BLNDGAM_RAMA_REGION_6_7_BASE_IDX                                                      2
4919 #define mmCM1_CM_BLNDGAM_RAMA_REGION_8_9                                                               0x0f0c
4920 #define mmCM1_CM_BLNDGAM_RAMA_REGION_8_9_BASE_IDX                                                      2
4921 #define mmCM1_CM_BLNDGAM_RAMA_REGION_10_11                                                             0x0f0d
4922 #define mmCM1_CM_BLNDGAM_RAMA_REGION_10_11_BASE_IDX                                                    2
4923 #define mmCM1_CM_BLNDGAM_RAMA_REGION_12_13                                                             0x0f0e
4924 #define mmCM1_CM_BLNDGAM_RAMA_REGION_12_13_BASE_IDX                                                    2
4925 #define mmCM1_CM_BLNDGAM_RAMA_REGION_14_15                                                             0x0f0f
4926 #define mmCM1_CM_BLNDGAM_RAMA_REGION_14_15_BASE_IDX                                                    2
4927 #define mmCM1_CM_BLNDGAM_RAMA_REGION_16_17                                                             0x0f10
4928 #define mmCM1_CM_BLNDGAM_RAMA_REGION_16_17_BASE_IDX                                                    2
4929 #define mmCM1_CM_BLNDGAM_RAMA_REGION_18_19                                                             0x0f11
4930 #define mmCM1_CM_BLNDGAM_RAMA_REGION_18_19_BASE_IDX                                                    2
4931 #define mmCM1_CM_BLNDGAM_RAMA_REGION_20_21                                                             0x0f12
4932 #define mmCM1_CM_BLNDGAM_RAMA_REGION_20_21_BASE_IDX                                                    2
4933 #define mmCM1_CM_BLNDGAM_RAMA_REGION_22_23                                                             0x0f13
4934 #define mmCM1_CM_BLNDGAM_RAMA_REGION_22_23_BASE_IDX                                                    2
4935 #define mmCM1_CM_BLNDGAM_RAMA_REGION_24_25                                                             0x0f14
4936 #define mmCM1_CM_BLNDGAM_RAMA_REGION_24_25_BASE_IDX                                                    2
4937 #define mmCM1_CM_BLNDGAM_RAMA_REGION_26_27                                                             0x0f15
4938 #define mmCM1_CM_BLNDGAM_RAMA_REGION_26_27_BASE_IDX                                                    2
4939 #define mmCM1_CM_BLNDGAM_RAMA_REGION_28_29                                                             0x0f16
4940 #define mmCM1_CM_BLNDGAM_RAMA_REGION_28_29_BASE_IDX                                                    2
4941 #define mmCM1_CM_BLNDGAM_RAMA_REGION_30_31                                                             0x0f17
4942 #define mmCM1_CM_BLNDGAM_RAMA_REGION_30_31_BASE_IDX                                                    2
4943 #define mmCM1_CM_BLNDGAM_RAMA_REGION_32_33                                                             0x0f18
4944 #define mmCM1_CM_BLNDGAM_RAMA_REGION_32_33_BASE_IDX                                                    2
4945 #define mmCM1_CM_BLNDGAM_RAMB_START_CNTL_B                                                             0x0f19
4946 #define mmCM1_CM_BLNDGAM_RAMB_START_CNTL_B_BASE_IDX                                                    2
4947 #define mmCM1_CM_BLNDGAM_RAMB_START_CNTL_G                                                             0x0f1a
4948 #define mmCM1_CM_BLNDGAM_RAMB_START_CNTL_G_BASE_IDX                                                    2
4949 #define mmCM1_CM_BLNDGAM_RAMB_START_CNTL_R                                                             0x0f1b
4950 #define mmCM1_CM_BLNDGAM_RAMB_START_CNTL_R_BASE_IDX                                                    2
4951 #define mmCM1_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_B                                                       0x0f1c
4952 #define mmCM1_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_B_BASE_IDX                                              2
4953 #define mmCM1_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_G                                                       0x0f1d
4954 #define mmCM1_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_G_BASE_IDX                                              2
4955 #define mmCM1_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_R                                                       0x0f1e
4956 #define mmCM1_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_R_BASE_IDX                                              2
4957 #define mmCM1_CM_BLNDGAM_RAMB_START_BASE_CNTL_B                                                        0x0f1f
4958 #define mmCM1_CM_BLNDGAM_RAMB_START_BASE_CNTL_B_BASE_IDX                                               2
4959 #define mmCM1_CM_BLNDGAM_RAMB_START_BASE_CNTL_G                                                        0x0f20
4960 #define mmCM1_CM_BLNDGAM_RAMB_START_BASE_CNTL_G_BASE_IDX                                               2
4961 #define mmCM1_CM_BLNDGAM_RAMB_START_BASE_CNTL_R                                                        0x0f21
4962 #define mmCM1_CM_BLNDGAM_RAMB_START_BASE_CNTL_R_BASE_IDX                                               2
4963 #define mmCM1_CM_BLNDGAM_RAMB_END_CNTL1_B                                                              0x0f22
4964 #define mmCM1_CM_BLNDGAM_RAMB_END_CNTL1_B_BASE_IDX                                                     2
4965 #define mmCM1_CM_BLNDGAM_RAMB_END_CNTL2_B                                                              0x0f23
4966 #define mmCM1_CM_BLNDGAM_RAMB_END_CNTL2_B_BASE_IDX                                                     2
4967 #define mmCM1_CM_BLNDGAM_RAMB_END_CNTL1_G                                                              0x0f24
4968 #define mmCM1_CM_BLNDGAM_RAMB_END_CNTL1_G_BASE_IDX                                                     2
4969 #define mmCM1_CM_BLNDGAM_RAMB_END_CNTL2_G                                                              0x0f25
4970 #define mmCM1_CM_BLNDGAM_RAMB_END_CNTL2_G_BASE_IDX                                                     2
4971 #define mmCM1_CM_BLNDGAM_RAMB_END_CNTL1_R                                                              0x0f26
4972 #define mmCM1_CM_BLNDGAM_RAMB_END_CNTL1_R_BASE_IDX                                                     2
4973 #define mmCM1_CM_BLNDGAM_RAMB_END_CNTL2_R                                                              0x0f27
4974 #define mmCM1_CM_BLNDGAM_RAMB_END_CNTL2_R_BASE_IDX                                                     2
4975 #define mmCM1_CM_BLNDGAM_RAMB_OFFSET_B                                                                 0x0f28
4976 #define mmCM1_CM_BLNDGAM_RAMB_OFFSET_B_BASE_IDX                                                        2
4977 #define mmCM1_CM_BLNDGAM_RAMB_OFFSET_G                                                                 0x0f29
4978 #define mmCM1_CM_BLNDGAM_RAMB_OFFSET_G_BASE_IDX                                                        2
4979 #define mmCM1_CM_BLNDGAM_RAMB_OFFSET_R                                                                 0x0f2a
4980 #define mmCM1_CM_BLNDGAM_RAMB_OFFSET_R_BASE_IDX                                                        2
4981 #define mmCM1_CM_BLNDGAM_RAMB_REGION_0_1                                                               0x0f2b
4982 #define mmCM1_CM_BLNDGAM_RAMB_REGION_0_1_BASE_IDX                                                      2
4983 #define mmCM1_CM_BLNDGAM_RAMB_REGION_2_3                                                               0x0f2c
4984 #define mmCM1_CM_BLNDGAM_RAMB_REGION_2_3_BASE_IDX                                                      2
4985 #define mmCM1_CM_BLNDGAM_RAMB_REGION_4_5                                                               0x0f2d
4986 #define mmCM1_CM_BLNDGAM_RAMB_REGION_4_5_BASE_IDX                                                      2
4987 #define mmCM1_CM_BLNDGAM_RAMB_REGION_6_7                                                               0x0f2e
4988 #define mmCM1_CM_BLNDGAM_RAMB_REGION_6_7_BASE_IDX                                                      2
4989 #define mmCM1_CM_BLNDGAM_RAMB_REGION_8_9                                                               0x0f2f
4990 #define mmCM1_CM_BLNDGAM_RAMB_REGION_8_9_BASE_IDX                                                      2
4991 #define mmCM1_CM_BLNDGAM_RAMB_REGION_10_11                                                             0x0f30
4992 #define mmCM1_CM_BLNDGAM_RAMB_REGION_10_11_BASE_IDX                                                    2
4993 #define mmCM1_CM_BLNDGAM_RAMB_REGION_12_13                                                             0x0f31
4994 #define mmCM1_CM_BLNDGAM_RAMB_REGION_12_13_BASE_IDX                                                    2
4995 #define mmCM1_CM_BLNDGAM_RAMB_REGION_14_15                                                             0x0f32
4996 #define mmCM1_CM_BLNDGAM_RAMB_REGION_14_15_BASE_IDX                                                    2
4997 #define mmCM1_CM_BLNDGAM_RAMB_REGION_16_17                                                             0x0f33
4998 #define mmCM1_CM_BLNDGAM_RAMB_REGION_16_17_BASE_IDX                                                    2
4999 #define mmCM1_CM_BLNDGAM_RAMB_REGION_18_19                                                             0x0f34
5000 #define mmCM1_CM_BLNDGAM_RAMB_REGION_18_19_BASE_IDX                                                    2
5001 #define mmCM1_CM_BLNDGAM_RAMB_REGION_20_21                                                             0x0f35
5002 #define mmCM1_CM_BLNDGAM_RAMB_REGION_20_21_BASE_IDX                                                    2
5003 #define mmCM1_CM_BLNDGAM_RAMB_REGION_22_23                                                             0x0f36
5004 #define mmCM1_CM_BLNDGAM_RAMB_REGION_22_23_BASE_IDX                                                    2
5005 #define mmCM1_CM_BLNDGAM_RAMB_REGION_24_25                                                             0x0f37
5006 #define mmCM1_CM_BLNDGAM_RAMB_REGION_24_25_BASE_IDX                                                    2
5007 #define mmCM1_CM_BLNDGAM_RAMB_REGION_26_27                                                             0x0f38
5008 #define mmCM1_CM_BLNDGAM_RAMB_REGION_26_27_BASE_IDX                                                    2
5009 #define mmCM1_CM_BLNDGAM_RAMB_REGION_28_29                                                             0x0f39
5010 #define mmCM1_CM_BLNDGAM_RAMB_REGION_28_29_BASE_IDX                                                    2
5011 #define mmCM1_CM_BLNDGAM_RAMB_REGION_30_31                                                             0x0f3a
5012 #define mmCM1_CM_BLNDGAM_RAMB_REGION_30_31_BASE_IDX                                                    2
5013 #define mmCM1_CM_BLNDGAM_RAMB_REGION_32_33                                                             0x0f3b
5014 #define mmCM1_CM_BLNDGAM_RAMB_REGION_32_33_BASE_IDX                                                    2
5015 #define mmCM1_CM_HDR_MULT_COEF                                                                         0x0f3c
5016 #define mmCM1_CM_HDR_MULT_COEF_BASE_IDX                                                                2
5017 #define mmCM1_CM_MEM_PWR_CTRL                                                                          0x0f3d
5018 #define mmCM1_CM_MEM_PWR_CTRL_BASE_IDX                                                                 2
5019 #define mmCM1_CM_MEM_PWR_STATUS                                                                        0x0f3e
5020 #define mmCM1_CM_MEM_PWR_STATUS_BASE_IDX                                                               2
5021 #define mmCM1_CM_DEALPHA                                                                               0x0f40
5022 #define mmCM1_CM_DEALPHA_BASE_IDX                                                                      2
5023 #define mmCM1_CM_COEF_FORMAT                                                                           0x0f41
5024 #define mmCM1_CM_COEF_FORMAT_BASE_IDX                                                                  2
5025 #define mmCM1_CM_SHAPER_CONTROL                                                                        0x0f42
5026 #define mmCM1_CM_SHAPER_CONTROL_BASE_IDX                                                               2
5027 #define mmCM1_CM_SHAPER_OFFSET_R                                                                       0x0f43
5028 #define mmCM1_CM_SHAPER_OFFSET_R_BASE_IDX                                                              2
5029 #define mmCM1_CM_SHAPER_OFFSET_G                                                                       0x0f44
5030 #define mmCM1_CM_SHAPER_OFFSET_G_BASE_IDX                                                              2
5031 #define mmCM1_CM_SHAPER_OFFSET_B                                                                       0x0f45
5032 #define mmCM1_CM_SHAPER_OFFSET_B_BASE_IDX                                                              2
5033 #define mmCM1_CM_SHAPER_SCALE_R                                                                        0x0f46
5034 #define mmCM1_CM_SHAPER_SCALE_R_BASE_IDX                                                               2
5035 #define mmCM1_CM_SHAPER_SCALE_G_B                                                                      0x0f47
5036 #define mmCM1_CM_SHAPER_SCALE_G_B_BASE_IDX                                                             2
5037 #define mmCM1_CM_SHAPER_LUT_INDEX                                                                      0x0f48
5038 #define mmCM1_CM_SHAPER_LUT_INDEX_BASE_IDX                                                             2
5039 #define mmCM1_CM_SHAPER_LUT_DATA                                                                       0x0f49
5040 #define mmCM1_CM_SHAPER_LUT_DATA_BASE_IDX                                                              2
5041 #define mmCM1_CM_SHAPER_LUT_WRITE_EN_MASK                                                              0x0f4a
5042 #define mmCM1_CM_SHAPER_LUT_WRITE_EN_MASK_BASE_IDX                                                     2
5043 #define mmCM1_CM_SHAPER_RAMA_START_CNTL_B                                                              0x0f4b
5044 #define mmCM1_CM_SHAPER_RAMA_START_CNTL_B_BASE_IDX                                                     2
5045 #define mmCM1_CM_SHAPER_RAMA_START_CNTL_G                                                              0x0f4c
5046 #define mmCM1_CM_SHAPER_RAMA_START_CNTL_G_BASE_IDX                                                     2
5047 #define mmCM1_CM_SHAPER_RAMA_START_CNTL_R                                                              0x0f4d
5048 #define mmCM1_CM_SHAPER_RAMA_START_CNTL_R_BASE_IDX                                                     2
5049 #define mmCM1_CM_SHAPER_RAMA_END_CNTL_B                                                                0x0f4e
5050 #define mmCM1_CM_SHAPER_RAMA_END_CNTL_B_BASE_IDX                                                       2
5051 #define mmCM1_CM_SHAPER_RAMA_END_CNTL_G                                                                0x0f4f
5052 #define mmCM1_CM_SHAPER_RAMA_END_CNTL_G_BASE_IDX                                                       2
5053 #define mmCM1_CM_SHAPER_RAMA_END_CNTL_R                                                                0x0f50
5054 #define mmCM1_CM_SHAPER_RAMA_END_CNTL_R_BASE_IDX                                                       2
5055 #define mmCM1_CM_SHAPER_RAMA_REGION_0_1                                                                0x0f51
5056 #define mmCM1_CM_SHAPER_RAMA_REGION_0_1_BASE_IDX                                                       2
5057 #define mmCM1_CM_SHAPER_RAMA_REGION_2_3                                                                0x0f52
5058 #define mmCM1_CM_SHAPER_RAMA_REGION_2_3_BASE_IDX                                                       2
5059 #define mmCM1_CM_SHAPER_RAMA_REGION_4_5                                                                0x0f53
5060 #define mmCM1_CM_SHAPER_RAMA_REGION_4_5_BASE_IDX                                                       2
5061 #define mmCM1_CM_SHAPER_RAMA_REGION_6_7                                                                0x0f54
5062 #define mmCM1_CM_SHAPER_RAMA_REGION_6_7_BASE_IDX                                                       2
5063 #define mmCM1_CM_SHAPER_RAMA_REGION_8_9                                                                0x0f55
5064 #define mmCM1_CM_SHAPER_RAMA_REGION_8_9_BASE_IDX                                                       2
5065 #define mmCM1_CM_SHAPER_RAMA_REGION_10_11                                                              0x0f56
5066 #define mmCM1_CM_SHAPER_RAMA_REGION_10_11_BASE_IDX                                                     2
5067 #define mmCM1_CM_SHAPER_RAMA_REGION_12_13                                                              0x0f57
5068 #define mmCM1_CM_SHAPER_RAMA_REGION_12_13_BASE_IDX                                                     2
5069 #define mmCM1_CM_SHAPER_RAMA_REGION_14_15                                                              0x0f58
5070 #define mmCM1_CM_SHAPER_RAMA_REGION_14_15_BASE_IDX                                                     2
5071 #define mmCM1_CM_SHAPER_RAMA_REGION_16_17                                                              0x0f59
5072 #define mmCM1_CM_SHAPER_RAMA_REGION_16_17_BASE_IDX                                                     2
5073 #define mmCM1_CM_SHAPER_RAMA_REGION_18_19                                                              0x0f5a
5074 #define mmCM1_CM_SHAPER_RAMA_REGION_18_19_BASE_IDX                                                     2
5075 #define mmCM1_CM_SHAPER_RAMA_REGION_20_21                                                              0x0f5b
5076 #define mmCM1_CM_SHAPER_RAMA_REGION_20_21_BASE_IDX                                                     2
5077 #define mmCM1_CM_SHAPER_RAMA_REGION_22_23                                                              0x0f5c
5078 #define mmCM1_CM_SHAPER_RAMA_REGION_22_23_BASE_IDX                                                     2
5079 #define mmCM1_CM_SHAPER_RAMA_REGION_24_25                                                              0x0f5d
5080 #define mmCM1_CM_SHAPER_RAMA_REGION_24_25_BASE_IDX                                                     2
5081 #define mmCM1_CM_SHAPER_RAMA_REGION_26_27                                                              0x0f5e
5082 #define mmCM1_CM_SHAPER_RAMA_REGION_26_27_BASE_IDX                                                     2
5083 #define mmCM1_CM_SHAPER_RAMA_REGION_28_29                                                              0x0f5f
5084 #define mmCM1_CM_SHAPER_RAMA_REGION_28_29_BASE_IDX                                                     2
5085 #define mmCM1_CM_SHAPER_RAMA_REGION_30_31                                                              0x0f60
5086 #define mmCM1_CM_SHAPER_RAMA_REGION_30_31_BASE_IDX                                                     2
5087 #define mmCM1_CM_SHAPER_RAMA_REGION_32_33                                                              0x0f61
5088 #define mmCM1_CM_SHAPER_RAMA_REGION_32_33_BASE_IDX                                                     2
5089 #define mmCM1_CM_SHAPER_RAMB_START_CNTL_B                                                              0x0f62
5090 #define mmCM1_CM_SHAPER_RAMB_START_CNTL_B_BASE_IDX                                                     2
5091 #define mmCM1_CM_SHAPER_RAMB_START_CNTL_G                                                              0x0f63
5092 #define mmCM1_CM_SHAPER_RAMB_START_CNTL_G_BASE_IDX                                                     2
5093 #define mmCM1_CM_SHAPER_RAMB_START_CNTL_R                                                              0x0f64
5094 #define mmCM1_CM_SHAPER_RAMB_START_CNTL_R_BASE_IDX                                                     2
5095 #define mmCM1_CM_SHAPER_RAMB_END_CNTL_B                                                                0x0f65
5096 #define mmCM1_CM_SHAPER_RAMB_END_CNTL_B_BASE_IDX                                                       2
5097 #define mmCM1_CM_SHAPER_RAMB_END_CNTL_G                                                                0x0f66
5098 #define mmCM1_CM_SHAPER_RAMB_END_CNTL_G_BASE_IDX                                                       2
5099 #define mmCM1_CM_SHAPER_RAMB_END_CNTL_R                                                                0x0f67
5100 #define mmCM1_CM_SHAPER_RAMB_END_CNTL_R_BASE_IDX                                                       2
5101 #define mmCM1_CM_SHAPER_RAMB_REGION_0_1                                                                0x0f68
5102 #define mmCM1_CM_SHAPER_RAMB_REGION_0_1_BASE_IDX                                                       2
5103 #define mmCM1_CM_SHAPER_RAMB_REGION_2_3                                                                0x0f69
5104 #define mmCM1_CM_SHAPER_RAMB_REGION_2_3_BASE_IDX                                                       2
5105 #define mmCM1_CM_SHAPER_RAMB_REGION_4_5                                                                0x0f6a
5106 #define mmCM1_CM_SHAPER_RAMB_REGION_4_5_BASE_IDX                                                       2
5107 #define mmCM1_CM_SHAPER_RAMB_REGION_6_7                                                                0x0f6b
5108 #define mmCM1_CM_SHAPER_RAMB_REGION_6_7_BASE_IDX                                                       2
5109 #define mmCM1_CM_SHAPER_RAMB_REGION_8_9                                                                0x0f6c
5110 #define mmCM1_CM_SHAPER_RAMB_REGION_8_9_BASE_IDX                                                       2
5111 #define mmCM1_CM_SHAPER_RAMB_REGION_10_11                                                              0x0f6d
5112 #define mmCM1_CM_SHAPER_RAMB_REGION_10_11_BASE_IDX                                                     2
5113 #define mmCM1_CM_SHAPER_RAMB_REGION_12_13                                                              0x0f6e
5114 #define mmCM1_CM_SHAPER_RAMB_REGION_12_13_BASE_IDX                                                     2
5115 #define mmCM1_CM_SHAPER_RAMB_REGION_14_15                                                              0x0f6f
5116 #define mmCM1_CM_SHAPER_RAMB_REGION_14_15_BASE_IDX                                                     2
5117 #define mmCM1_CM_SHAPER_RAMB_REGION_16_17                                                              0x0f70
5118 #define mmCM1_CM_SHAPER_RAMB_REGION_16_17_BASE_IDX                                                     2
5119 #define mmCM1_CM_SHAPER_RAMB_REGION_18_19                                                              0x0f71
5120 #define mmCM1_CM_SHAPER_RAMB_REGION_18_19_BASE_IDX                                                     2
5121 #define mmCM1_CM_SHAPER_RAMB_REGION_20_21                                                              0x0f72
5122 #define mmCM1_CM_SHAPER_RAMB_REGION_20_21_BASE_IDX                                                     2
5123 #define mmCM1_CM_SHAPER_RAMB_REGION_22_23                                                              0x0f73
5124 #define mmCM1_CM_SHAPER_RAMB_REGION_22_23_BASE_IDX                                                     2
5125 #define mmCM1_CM_SHAPER_RAMB_REGION_24_25                                                              0x0f74
5126 #define mmCM1_CM_SHAPER_RAMB_REGION_24_25_BASE_IDX                                                     2
5127 #define mmCM1_CM_SHAPER_RAMB_REGION_26_27                                                              0x0f75
5128 #define mmCM1_CM_SHAPER_RAMB_REGION_26_27_BASE_IDX                                                     2
5129 #define mmCM1_CM_SHAPER_RAMB_REGION_28_29                                                              0x0f76
5130 #define mmCM1_CM_SHAPER_RAMB_REGION_28_29_BASE_IDX                                                     2
5131 #define mmCM1_CM_SHAPER_RAMB_REGION_30_31                                                              0x0f77
5132 #define mmCM1_CM_SHAPER_RAMB_REGION_30_31_BASE_IDX                                                     2
5133 #define mmCM1_CM_SHAPER_RAMB_REGION_32_33                                                              0x0f78
5134 #define mmCM1_CM_SHAPER_RAMB_REGION_32_33_BASE_IDX                                                     2
5135 #define mmCM1_CM_MEM_PWR_CTRL2                                                                         0x0f79
5136 #define mmCM1_CM_MEM_PWR_CTRL2_BASE_IDX                                                                2
5137 #define mmCM1_CM_MEM_PWR_STATUS2                                                                       0x0f7a
5138 #define mmCM1_CM_MEM_PWR_STATUS2_BASE_IDX                                                              2
5139 #define mmCM1_CM_3DLUT_MODE                                                                            0x0f7b
5140 #define mmCM1_CM_3DLUT_MODE_BASE_IDX                                                                   2
5141 #define mmCM1_CM_3DLUT_INDEX                                                                           0x0f7c
5142 #define mmCM1_CM_3DLUT_INDEX_BASE_IDX                                                                  2
5143 #define mmCM1_CM_3DLUT_DATA                                                                            0x0f7d
5144 #define mmCM1_CM_3DLUT_DATA_BASE_IDX                                                                   2
5145 #define mmCM1_CM_3DLUT_DATA_30BIT                                                                      0x0f7e
5146 #define mmCM1_CM_3DLUT_DATA_30BIT_BASE_IDX                                                             2
5147 #define mmCM1_CM_3DLUT_READ_WRITE_CONTROL                                                              0x0f7f
5148 #define mmCM1_CM_3DLUT_READ_WRITE_CONTROL_BASE_IDX                                                     2
5149 #define mmCM1_CM_3DLUT_OUT_NORM_FACTOR                                                                 0x0f80
5150 #define mmCM1_CM_3DLUT_OUT_NORM_FACTOR_BASE_IDX                                                        2
5151 #define mmCM1_CM_3DLUT_OUT_OFFSET_R                                                                    0x0f81
5152 #define mmCM1_CM_3DLUT_OUT_OFFSET_R_BASE_IDX                                                           2
5153 #define mmCM1_CM_3DLUT_OUT_OFFSET_G                                                                    0x0f82
5154 #define mmCM1_CM_3DLUT_OUT_OFFSET_G_BASE_IDX                                                           2
5155 #define mmCM1_CM_3DLUT_OUT_OFFSET_B                                                                    0x0f83
5156 #define mmCM1_CM_3DLUT_OUT_OFFSET_B_BASE_IDX                                                           2
5157 
5158 
5159 // addressBlock: dce_dc_dpp1_dispdec_dpp_dcperfmon_dc_perfmon_dispdec
5160 // base address: 0x3e3c
5161 #define mmDC_PERFMON12_PERFCOUNTER_CNTL                                                                0x0f8f
5162 #define mmDC_PERFMON12_PERFCOUNTER_CNTL_BASE_IDX                                                       2
5163 #define mmDC_PERFMON12_PERFCOUNTER_CNTL2                                                               0x0f90
5164 #define mmDC_PERFMON12_PERFCOUNTER_CNTL2_BASE_IDX                                                      2
5165 #define mmDC_PERFMON12_PERFCOUNTER_STATE                                                               0x0f91
5166 #define mmDC_PERFMON12_PERFCOUNTER_STATE_BASE_IDX                                                      2
5167 #define mmDC_PERFMON12_PERFMON_CNTL                                                                    0x0f92
5168 #define mmDC_PERFMON12_PERFMON_CNTL_BASE_IDX                                                           2
5169 #define mmDC_PERFMON12_PERFMON_CNTL2                                                                   0x0f93
5170 #define mmDC_PERFMON12_PERFMON_CNTL2_BASE_IDX                                                          2
5171 #define mmDC_PERFMON12_PERFMON_CVALUE_INT_MISC                                                         0x0f94
5172 #define mmDC_PERFMON12_PERFMON_CVALUE_INT_MISC_BASE_IDX                                                2
5173 #define mmDC_PERFMON12_PERFMON_CVALUE_LOW                                                              0x0f95
5174 #define mmDC_PERFMON12_PERFMON_CVALUE_LOW_BASE_IDX                                                     2
5175 #define mmDC_PERFMON12_PERFMON_HI                                                                      0x0f96
5176 #define mmDC_PERFMON12_PERFMON_HI_BASE_IDX                                                             2
5177 #define mmDC_PERFMON12_PERFMON_LOW                                                                     0x0f97
5178 #define mmDC_PERFMON12_PERFMON_LOW_BASE_IDX                                                            2
5179 
5180 
5181 // addressBlock: dce_dc_dpp2_dispdec_dpp_top_dispdec
5182 // base address: 0xb58
5183 #define mmDPP_TOP2_DPP_CONTROL                                                                         0x0f9b
5184 #define mmDPP_TOP2_DPP_CONTROL_BASE_IDX                                                                2
5185 #define mmDPP_TOP2_DPP_SOFT_RESET                                                                      0x0f9c
5186 #define mmDPP_TOP2_DPP_SOFT_RESET_BASE_IDX                                                             2
5187 #define mmDPP_TOP2_DPP_CRC_VAL_R_G                                                                     0x0f9d
5188 #define mmDPP_TOP2_DPP_CRC_VAL_R_G_BASE_IDX                                                            2
5189 #define mmDPP_TOP2_DPP_CRC_VAL_B_A                                                                     0x0f9e
5190 #define mmDPP_TOP2_DPP_CRC_VAL_B_A_BASE_IDX                                                            2
5191 #define mmDPP_TOP2_DPP_CRC_CTRL                                                                        0x0f9f
5192 #define mmDPP_TOP2_DPP_CRC_CTRL_BASE_IDX                                                               2
5193 #define mmDPP_TOP2_HOST_READ_CONTROL                                                                   0x0fa0
5194 #define mmDPP_TOP2_HOST_READ_CONTROL_BASE_IDX                                                          2
5195 
5196 
5197 // addressBlock: dce_dc_dpp2_dispdec_cnvc_cfg_dispdec
5198 // base address: 0xb58
5199 #define mmCNVC_CFG2_CNVC_SURFACE_PIXEL_FORMAT                                                          0x0fa5
5200 #define mmCNVC_CFG2_CNVC_SURFACE_PIXEL_FORMAT_BASE_IDX                                                 2
5201 #define mmCNVC_CFG2_FORMAT_CONTROL                                                                     0x0fa6
5202 #define mmCNVC_CFG2_FORMAT_CONTROL_BASE_IDX                                                            2
5203 #define mmCNVC_CFG2_FCNV_FP_BIAS_R                                                                     0x0fa7
5204 #define mmCNVC_CFG2_FCNV_FP_BIAS_R_BASE_IDX                                                            2
5205 #define mmCNVC_CFG2_FCNV_FP_BIAS_G                                                                     0x0fa8
5206 #define mmCNVC_CFG2_FCNV_FP_BIAS_G_BASE_IDX                                                            2
5207 #define mmCNVC_CFG2_FCNV_FP_BIAS_B                                                                     0x0fa9
5208 #define mmCNVC_CFG2_FCNV_FP_BIAS_B_BASE_IDX                                                            2
5209 #define mmCNVC_CFG2_FCNV_FP_SCALE_R                                                                    0x0faa
5210 #define mmCNVC_CFG2_FCNV_FP_SCALE_R_BASE_IDX                                                           2
5211 #define mmCNVC_CFG2_FCNV_FP_SCALE_G                                                                    0x0fab
5212 #define mmCNVC_CFG2_FCNV_FP_SCALE_G_BASE_IDX                                                           2
5213 #define mmCNVC_CFG2_FCNV_FP_SCALE_B                                                                    0x0fac
5214 #define mmCNVC_CFG2_FCNV_FP_SCALE_B_BASE_IDX                                                           2
5215 #define mmCNVC_CFG2_COLOR_KEYER_CONTROL                                                                0x0fad
5216 #define mmCNVC_CFG2_COLOR_KEYER_CONTROL_BASE_IDX                                                       2
5217 #define mmCNVC_CFG2_COLOR_KEYER_ALPHA                                                                  0x0fae
5218 #define mmCNVC_CFG2_COLOR_KEYER_ALPHA_BASE_IDX                                                         2
5219 #define mmCNVC_CFG2_COLOR_KEYER_RED                                                                    0x0faf
5220 #define mmCNVC_CFG2_COLOR_KEYER_RED_BASE_IDX                                                           2
5221 #define mmCNVC_CFG2_COLOR_KEYER_GREEN                                                                  0x0fb0
5222 #define mmCNVC_CFG2_COLOR_KEYER_GREEN_BASE_IDX                                                         2
5223 #define mmCNVC_CFG2_COLOR_KEYER_BLUE                                                                   0x0fb1
5224 #define mmCNVC_CFG2_COLOR_KEYER_BLUE_BASE_IDX                                                          2
5225 #define mmCNVC_CFG2_ALPHA_2BIT_LUT                                                                     0x0fb3
5226 #define mmCNVC_CFG2_ALPHA_2BIT_LUT_BASE_IDX                                                            2
5227 #define mmCNVC_CFG2_PRE_DEALPHA                                                                        0x0fb4
5228 #define mmCNVC_CFG2_PRE_DEALPHA_BASE_IDX                                                               2
5229 #define mmCNVC_CFG2_PRE_CSC_MODE                                                                       0x0fb5
5230 #define mmCNVC_CFG2_PRE_CSC_MODE_BASE_IDX                                                              2
5231 #define mmCNVC_CFG2_PRE_CSC_C11_C12                                                                    0x0fb6
5232 #define mmCNVC_CFG2_PRE_CSC_C11_C12_BASE_IDX                                                           2
5233 #define mmCNVC_CFG2_PRE_CSC_C13_C14                                                                    0x0fb7
5234 #define mmCNVC_CFG2_PRE_CSC_C13_C14_BASE_IDX                                                           2
5235 #define mmCNVC_CFG2_PRE_CSC_C21_C22                                                                    0x0fb8
5236 #define mmCNVC_CFG2_PRE_CSC_C21_C22_BASE_IDX                                                           2
5237 #define mmCNVC_CFG2_PRE_CSC_C23_C24                                                                    0x0fb9
5238 #define mmCNVC_CFG2_PRE_CSC_C23_C24_BASE_IDX                                                           2
5239 #define mmCNVC_CFG2_PRE_CSC_C31_C32                                                                    0x0fba
5240 #define mmCNVC_CFG2_PRE_CSC_C31_C32_BASE_IDX                                                           2
5241 #define mmCNVC_CFG2_PRE_CSC_C33_C34                                                                    0x0fbb
5242 #define mmCNVC_CFG2_PRE_CSC_C33_C34_BASE_IDX                                                           2
5243 #define mmCNVC_CFG2_PRE_CSC_B_C11_C12                                                                  0x0fbc
5244 #define mmCNVC_CFG2_PRE_CSC_B_C11_C12_BASE_IDX                                                         2
5245 #define mmCNVC_CFG2_PRE_CSC_B_C13_C14                                                                  0x0fbd
5246 #define mmCNVC_CFG2_PRE_CSC_B_C13_C14_BASE_IDX                                                         2
5247 #define mmCNVC_CFG2_PRE_CSC_B_C21_C22                                                                  0x0fbe
5248 #define mmCNVC_CFG2_PRE_CSC_B_C21_C22_BASE_IDX                                                         2
5249 #define mmCNVC_CFG2_PRE_CSC_B_C23_C24                                                                  0x0fbf
5250 #define mmCNVC_CFG2_PRE_CSC_B_C23_C24_BASE_IDX                                                         2
5251 #define mmCNVC_CFG2_PRE_CSC_B_C31_C32                                                                  0x0fc0
5252 #define mmCNVC_CFG2_PRE_CSC_B_C31_C32_BASE_IDX                                                         2
5253 #define mmCNVC_CFG2_PRE_CSC_B_C33_C34                                                                  0x0fc1
5254 #define mmCNVC_CFG2_PRE_CSC_B_C33_C34_BASE_IDX                                                         2
5255 #define mmCNVC_CFG2_CNVC_COEF_FORMAT                                                                   0x0fc2
5256 #define mmCNVC_CFG2_CNVC_COEF_FORMAT_BASE_IDX                                                          2
5257 #define mmCNVC_CFG2_PRE_DEGAM                                                                          0x0fc3
5258 #define mmCNVC_CFG2_PRE_DEGAM_BASE_IDX                                                                 2
5259 #define mmCNVC_CFG2_PRE_REALPHA                                                                        0x0fc4
5260 #define mmCNVC_CFG2_PRE_REALPHA_BASE_IDX                                                               2
5261 
5262 
5263 // addressBlock: dce_dc_dpp2_dispdec_cnvc_cur_dispdec
5264 // base address: 0xb58
5265 #define mmCNVC_CUR2_CURSOR0_CONTROL                                                                    0x0fc7
5266 #define mmCNVC_CUR2_CURSOR0_CONTROL_BASE_IDX                                                           2
5267 #define mmCNVC_CUR2_CURSOR0_COLOR0                                                                     0x0fc8
5268 #define mmCNVC_CUR2_CURSOR0_COLOR0_BASE_IDX                                                            2
5269 #define mmCNVC_CUR2_CURSOR0_COLOR1                                                                     0x0fc9
5270 #define mmCNVC_CUR2_CURSOR0_COLOR1_BASE_IDX                                                            2
5271 #define mmCNVC_CUR2_CURSOR0_FP_SCALE_BIAS                                                              0x0fca
5272 #define mmCNVC_CUR2_CURSOR0_FP_SCALE_BIAS_BASE_IDX                                                     2
5273 
5274 // addressBlock: dce_dc_dpp2_dispdec_dscl_dispdec
5275 // base address: 0xb58
5276 #define mmDSCL2_SCL_COEF_RAM_TAP_SELECT                                                                0x0fcf
5277 #define mmDSCL2_SCL_COEF_RAM_TAP_SELECT_BASE_IDX                                                       2
5278 #define mmDSCL2_SCL_COEF_RAM_TAP_DATA                                                                  0x0fd0
5279 #define mmDSCL2_SCL_COEF_RAM_TAP_DATA_BASE_IDX                                                         2
5280 #define mmDSCL2_SCL_MODE                                                                               0x0fd1
5281 #define mmDSCL2_SCL_MODE_BASE_IDX                                                                      2
5282 #define mmDSCL2_SCL_TAP_CONTROL                                                                        0x0fd2
5283 #define mmDSCL2_SCL_TAP_CONTROL_BASE_IDX                                                               2
5284 #define mmDSCL2_DSCL_CONTROL                                                                           0x0fd3
5285 #define mmDSCL2_DSCL_CONTROL_BASE_IDX                                                                  2
5286 #define mmDSCL2_DSCL_2TAP_CONTROL                                                                      0x0fd4
5287 #define mmDSCL2_DSCL_2TAP_CONTROL_BASE_IDX                                                             2
5288 #define mmDSCL2_SCL_MANUAL_REPLICATE_CONTROL                                                           0x0fd5
5289 #define mmDSCL2_SCL_MANUAL_REPLICATE_CONTROL_BASE_IDX                                                  2
5290 #define mmDSCL2_SCL_HORZ_FILTER_SCALE_RATIO                                                            0x0fd6
5291 #define mmDSCL2_SCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX                                                   2
5292 #define mmDSCL2_SCL_HORZ_FILTER_INIT                                                                   0x0fd7
5293 #define mmDSCL2_SCL_HORZ_FILTER_INIT_BASE_IDX                                                          2
5294 #define mmDSCL2_SCL_HORZ_FILTER_SCALE_RATIO_C                                                          0x0fd8
5295 #define mmDSCL2_SCL_HORZ_FILTER_SCALE_RATIO_C_BASE_IDX                                                 2
5296 #define mmDSCL2_SCL_HORZ_FILTER_INIT_C                                                                 0x0fd9
5297 #define mmDSCL2_SCL_HORZ_FILTER_INIT_C_BASE_IDX                                                        2
5298 #define mmDSCL2_SCL_VERT_FILTER_SCALE_RATIO                                                            0x0fda
5299 #define mmDSCL2_SCL_VERT_FILTER_SCALE_RATIO_BASE_IDX                                                   2
5300 #define mmDSCL2_SCL_VERT_FILTER_INIT                                                                   0x0fdb
5301 #define mmDSCL2_SCL_VERT_FILTER_INIT_BASE_IDX                                                          2
5302 #define mmDSCL2_SCL_VERT_FILTER_INIT_BOT                                                               0x0fdc
5303 #define mmDSCL2_SCL_VERT_FILTER_INIT_BOT_BASE_IDX                                                      2
5304 #define mmDSCL2_SCL_VERT_FILTER_SCALE_RATIO_C                                                          0x0fdd
5305 #define mmDSCL2_SCL_VERT_FILTER_SCALE_RATIO_C_BASE_IDX                                                 2
5306 #define mmDSCL2_SCL_VERT_FILTER_INIT_C                                                                 0x0fde
5307 #define mmDSCL2_SCL_VERT_FILTER_INIT_C_BASE_IDX                                                        2
5308 #define mmDSCL2_SCL_VERT_FILTER_INIT_BOT_C                                                             0x0fdf
5309 #define mmDSCL2_SCL_VERT_FILTER_INIT_BOT_C_BASE_IDX                                                    2
5310 #define mmDSCL2_SCL_BLACK_COLOR                                                                        0x0fe0
5311 #define mmDSCL2_SCL_BLACK_COLOR_BASE_IDX                                                               2
5312 #define mmDSCL2_DSCL_UPDATE                                                                            0x0fe1
5313 #define mmDSCL2_DSCL_UPDATE_BASE_IDX                                                                   2
5314 #define mmDSCL2_DSCL_AUTOCAL                                                                           0x0fe2
5315 #define mmDSCL2_DSCL_AUTOCAL_BASE_IDX                                                                  2
5316 #define mmDSCL2_DSCL_EXT_OVERSCAN_LEFT_RIGHT                                                           0x0fe3
5317 #define mmDSCL2_DSCL_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX                                                  2
5318 #define mmDSCL2_DSCL_EXT_OVERSCAN_TOP_BOTTOM                                                           0x0fe4
5319 #define mmDSCL2_DSCL_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX                                                  2
5320 #define mmDSCL2_OTG_H_BLANK                                                                            0x0fe5
5321 #define mmDSCL2_OTG_H_BLANK_BASE_IDX                                                                   2
5322 #define mmDSCL2_OTG_V_BLANK                                                                            0x0fe6
5323 #define mmDSCL2_OTG_V_BLANK_BASE_IDX                                                                   2
5324 #define mmDSCL2_RECOUT_START                                                                           0x0fe7
5325 #define mmDSCL2_RECOUT_START_BASE_IDX                                                                  2
5326 #define mmDSCL2_RECOUT_SIZE                                                                            0x0fe8
5327 #define mmDSCL2_RECOUT_SIZE_BASE_IDX                                                                   2
5328 #define mmDSCL2_MPC_SIZE                                                                               0x0fe9
5329 #define mmDSCL2_MPC_SIZE_BASE_IDX                                                                      2
5330 #define mmDSCL2_LB_DATA_FORMAT                                                                         0x0fea
5331 #define mmDSCL2_LB_DATA_FORMAT_BASE_IDX                                                                2
5332 #define mmDSCL2_LB_MEMORY_CTRL                                                                         0x0feb
5333 #define mmDSCL2_LB_MEMORY_CTRL_BASE_IDX                                                                2
5334 #define mmDSCL2_LB_V_COUNTER                                                                           0x0fec
5335 #define mmDSCL2_LB_V_COUNTER_BASE_IDX                                                                  2
5336 #define mmDSCL2_DSCL_MEM_PWR_CTRL                                                                      0x0fed
5337 #define mmDSCL2_DSCL_MEM_PWR_CTRL_BASE_IDX                                                             2
5338 #define mmDSCL2_DSCL_MEM_PWR_STATUS                                                                    0x0fee
5339 #define mmDSCL2_DSCL_MEM_PWR_STATUS_BASE_IDX                                                           2
5340 #define mmDSCL2_OBUF_CONTROL                                                                           0x0fef
5341 #define mmDSCL2_OBUF_CONTROL_BASE_IDX                                                                  2
5342 #define mmDSCL2_OBUF_MEM_PWR_CTRL                                                                      0x0ff0
5343 #define mmDSCL2_OBUF_MEM_PWR_CTRL_BASE_IDX                                                             2
5344 
5345 
5346 // addressBlock: dce_dc_dpp2_dispdec_cm_dispdec
5347 // base address: 0xb58
5348 #define mmCM2_CM_CONTROL                                                                               0x0ff6
5349 #define mmCM2_CM_CONTROL_BASE_IDX                                                                      2
5350 #define mmCM2_CM_POST_CSC_CONTROL                                                                      0x0ff7
5351 #define mmCM2_CM_POST_CSC_CONTROL_BASE_IDX                                                             2
5352 #define mmCM2_CM_POST_CSC_C11_C12                                                                      0x0ff8
5353 #define mmCM2_CM_POST_CSC_C11_C12_BASE_IDX                                                             2
5354 #define mmCM2_CM_POST_CSC_C13_C14                                                                      0x0ff9
5355 #define mmCM2_CM_POST_CSC_C13_C14_BASE_IDX                                                             2
5356 #define mmCM2_CM_POST_CSC_C21_C22                                                                      0x0ffa
5357 #define mmCM2_CM_POST_CSC_C21_C22_BASE_IDX                                                             2
5358 #define mmCM2_CM_POST_CSC_C23_C24                                                                      0x0ffb
5359 #define mmCM2_CM_POST_CSC_C23_C24_BASE_IDX                                                             2
5360 #define mmCM2_CM_POST_CSC_C31_C32                                                                      0x0ffc
5361 #define mmCM2_CM_POST_CSC_C31_C32_BASE_IDX                                                             2
5362 #define mmCM2_CM_POST_CSC_C33_C34                                                                      0x0ffd
5363 #define mmCM2_CM_POST_CSC_C33_C34_BASE_IDX                                                             2
5364 #define mmCM2_CM_POST_CSC_B_C11_C12                                                                    0x0ffe
5365 #define mmCM2_CM_POST_CSC_B_C11_C12_BASE_IDX                                                           2
5366 #define mmCM2_CM_POST_CSC_B_C13_C14                                                                    0x0fff
5367 #define mmCM2_CM_POST_CSC_B_C13_C14_BASE_IDX                                                           2
5368 #define mmCM2_CM_POST_CSC_B_C21_C22                                                                    0x1000
5369 #define mmCM2_CM_POST_CSC_B_C21_C22_BASE_IDX                                                           2
5370 #define mmCM2_CM_POST_CSC_B_C23_C24                                                                    0x1001
5371 #define mmCM2_CM_POST_CSC_B_C23_C24_BASE_IDX                                                           2
5372 #define mmCM2_CM_POST_CSC_B_C31_C32                                                                    0x1002
5373 #define mmCM2_CM_POST_CSC_B_C31_C32_BASE_IDX                                                           2
5374 #define mmCM2_CM_POST_CSC_B_C33_C34                                                                    0x1003
5375 #define mmCM2_CM_POST_CSC_B_C33_C34_BASE_IDX                                                           2
5376 #define mmCM2_CM_GAMUT_REMAP_CONTROL                                                                   0x1004
5377 #define mmCM2_CM_GAMUT_REMAP_CONTROL_BASE_IDX                                                          2
5378 #define mmCM2_CM_GAMUT_REMAP_C11_C12                                                                   0x1005
5379 #define mmCM2_CM_GAMUT_REMAP_C11_C12_BASE_IDX                                                          2
5380 #define mmCM2_CM_GAMUT_REMAP_C13_C14                                                                   0x1006
5381 #define mmCM2_CM_GAMUT_REMAP_C13_C14_BASE_IDX                                                          2
5382 #define mmCM2_CM_GAMUT_REMAP_C21_C22                                                                   0x1007
5383 #define mmCM2_CM_GAMUT_REMAP_C21_C22_BASE_IDX                                                          2
5384 #define mmCM2_CM_GAMUT_REMAP_C23_C24                                                                   0x1008
5385 #define mmCM2_CM_GAMUT_REMAP_C23_C24_BASE_IDX                                                          2
5386 #define mmCM2_CM_GAMUT_REMAP_C31_C32                                                                   0x1009
5387 #define mmCM2_CM_GAMUT_REMAP_C31_C32_BASE_IDX                                                          2
5388 #define mmCM2_CM_GAMUT_REMAP_C33_C34                                                                   0x100a
5389 #define mmCM2_CM_GAMUT_REMAP_C33_C34_BASE_IDX                                                          2
5390 #define mmCM2_CM_GAMUT_REMAP_B_C11_C12                                                                 0x100b
5391 #define mmCM2_CM_GAMUT_REMAP_B_C11_C12_BASE_IDX                                                        2
5392 #define mmCM2_CM_GAMUT_REMAP_B_C13_C14                                                                 0x100c
5393 #define mmCM2_CM_GAMUT_REMAP_B_C13_C14_BASE_IDX                                                        2
5394 #define mmCM2_CM_GAMUT_REMAP_B_C21_C22                                                                 0x100d
5395 #define mmCM2_CM_GAMUT_REMAP_B_C21_C22_BASE_IDX                                                        2
5396 #define mmCM2_CM_GAMUT_REMAP_B_C23_C24                                                                 0x100e
5397 #define mmCM2_CM_GAMUT_REMAP_B_C23_C24_BASE_IDX                                                        2
5398 #define mmCM2_CM_GAMUT_REMAP_B_C31_C32                                                                 0x100f
5399 #define mmCM2_CM_GAMUT_REMAP_B_C31_C32_BASE_IDX                                                        2
5400 #define mmCM2_CM_GAMUT_REMAP_B_C33_C34                                                                 0x1010
5401 #define mmCM2_CM_GAMUT_REMAP_B_C33_C34_BASE_IDX                                                        2
5402 #define mmCM2_CM_BIAS_CR_R                                                                             0x1011
5403 #define mmCM2_CM_BIAS_CR_R_BASE_IDX                                                                    2
5404 #define mmCM2_CM_BIAS_Y_G_CB_B                                                                         0x1012
5405 #define mmCM2_CM_BIAS_Y_G_CB_B_BASE_IDX                                                                2
5406 #define mmCM2_CM_GAMCOR_CONTROL                                                                        0x1013
5407 #define mmCM2_CM_GAMCOR_CONTROL_BASE_IDX                                                               2
5408 #define mmCM2_CM_GAMCOR_LUT_INDEX                                                                      0x1014
5409 #define mmCM2_CM_GAMCOR_LUT_INDEX_BASE_IDX                                                             2
5410 #define mmCM2_CM_GAMCOR_LUT_DATA                                                                       0x1015
5411 #define mmCM2_CM_GAMCOR_LUT_DATA_BASE_IDX                                                              2
5412 #define mmCM2_CM_GAMCOR_LUT_CONTROL                                                                    0x1016
5413 #define mmCM2_CM_GAMCOR_LUT_CONTROL_BASE_IDX                                                           2
5414 #define mmCM2_CM_GAMCOR_RAMA_START_CNTL_B                                                              0x1017
5415 #define mmCM2_CM_GAMCOR_RAMA_START_CNTL_B_BASE_IDX                                                     2
5416 #define mmCM2_CM_GAMCOR_RAMA_START_CNTL_G                                                              0x1018
5417 #define mmCM2_CM_GAMCOR_RAMA_START_CNTL_G_BASE_IDX                                                     2
5418 #define mmCM2_CM_GAMCOR_RAMA_START_CNTL_R                                                              0x1019
5419 #define mmCM2_CM_GAMCOR_RAMA_START_CNTL_R_BASE_IDX                                                     2
5420 #define mmCM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B                                                        0x101a
5421 #define mmCM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B_BASE_IDX                                               2
5422 #define mmCM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G                                                        0x101b
5423 #define mmCM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G_BASE_IDX                                               2
5424 #define mmCM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R                                                        0x101c
5425 #define mmCM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R_BASE_IDX                                               2
5426 #define mmCM2_CM_GAMCOR_RAMA_START_BASE_CNTL_B                                                         0x101d
5427 #define mmCM2_CM_GAMCOR_RAMA_START_BASE_CNTL_B_BASE_IDX                                                2
5428 #define mmCM2_CM_GAMCOR_RAMA_START_BASE_CNTL_G                                                         0x101e
5429 #define mmCM2_CM_GAMCOR_RAMA_START_BASE_CNTL_G_BASE_IDX                                                2
5430 #define mmCM2_CM_GAMCOR_RAMA_START_BASE_CNTL_R                                                         0x101f
5431 #define mmCM2_CM_GAMCOR_RAMA_START_BASE_CNTL_R_BASE_IDX                                                2
5432 #define mmCM2_CM_GAMCOR_RAMA_END_CNTL1_B                                                               0x1020
5433 #define mmCM2_CM_GAMCOR_RAMA_END_CNTL1_B_BASE_IDX                                                      2
5434 #define mmCM2_CM_GAMCOR_RAMA_END_CNTL2_B                                                               0x1021
5435 #define mmCM2_CM_GAMCOR_RAMA_END_CNTL2_B_BASE_IDX                                                      2
5436 #define mmCM2_CM_GAMCOR_RAMA_END_CNTL1_G                                                               0x1022
5437 #define mmCM2_CM_GAMCOR_RAMA_END_CNTL1_G_BASE_IDX                                                      2
5438 #define mmCM2_CM_GAMCOR_RAMA_END_CNTL2_G                                                               0x1023
5439 #define mmCM2_CM_GAMCOR_RAMA_END_CNTL2_G_BASE_IDX                                                      2
5440 #define mmCM2_CM_GAMCOR_RAMA_END_CNTL1_R                                                               0x1024
5441 #define mmCM2_CM_GAMCOR_RAMA_END_CNTL1_R_BASE_IDX                                                      2
5442 #define mmCM2_CM_GAMCOR_RAMA_END_CNTL2_R                                                               0x1025
5443 #define mmCM2_CM_GAMCOR_RAMA_END_CNTL2_R_BASE_IDX                                                      2
5444 #define mmCM2_CM_GAMCOR_RAMA_OFFSET_B                                                                  0x1026
5445 #define mmCM2_CM_GAMCOR_RAMA_OFFSET_B_BASE_IDX                                                         2
5446 #define mmCM2_CM_GAMCOR_RAMA_OFFSET_G                                                                  0x1027
5447 #define mmCM2_CM_GAMCOR_RAMA_OFFSET_G_BASE_IDX                                                         2
5448 #define mmCM2_CM_GAMCOR_RAMA_OFFSET_R                                                                  0x1028
5449 #define mmCM2_CM_GAMCOR_RAMA_OFFSET_R_BASE_IDX                                                         2
5450 #define mmCM2_CM_GAMCOR_RAMA_REGION_0_1                                                                0x1029
5451 #define mmCM2_CM_GAMCOR_RAMA_REGION_0_1_BASE_IDX                                                       2
5452 #define mmCM2_CM_GAMCOR_RAMA_REGION_2_3                                                                0x102a
5453 #define mmCM2_CM_GAMCOR_RAMA_REGION_2_3_BASE_IDX                                                       2
5454 #define mmCM2_CM_GAMCOR_RAMA_REGION_4_5                                                                0x102b
5455 #define mmCM2_CM_GAMCOR_RAMA_REGION_4_5_BASE_IDX                                                       2
5456 #define mmCM2_CM_GAMCOR_RAMA_REGION_6_7                                                                0x102c
5457 #define mmCM2_CM_GAMCOR_RAMA_REGION_6_7_BASE_IDX                                                       2
5458 #define mmCM2_CM_GAMCOR_RAMA_REGION_8_9                                                                0x102d
5459 #define mmCM2_CM_GAMCOR_RAMA_REGION_8_9_BASE_IDX                                                       2
5460 #define mmCM2_CM_GAMCOR_RAMA_REGION_10_11                                                              0x102e
5461 #define mmCM2_CM_GAMCOR_RAMA_REGION_10_11_BASE_IDX                                                     2
5462 #define mmCM2_CM_GAMCOR_RAMA_REGION_12_13                                                              0x102f
5463 #define mmCM2_CM_GAMCOR_RAMA_REGION_12_13_BASE_IDX                                                     2
5464 #define mmCM2_CM_GAMCOR_RAMA_REGION_14_15                                                              0x1030
5465 #define mmCM2_CM_GAMCOR_RAMA_REGION_14_15_BASE_IDX                                                     2
5466 #define mmCM2_CM_GAMCOR_RAMA_REGION_16_17                                                              0x1031
5467 #define mmCM2_CM_GAMCOR_RAMA_REGION_16_17_BASE_IDX                                                     2
5468 #define mmCM2_CM_GAMCOR_RAMA_REGION_18_19                                                              0x1032
5469 #define mmCM2_CM_GAMCOR_RAMA_REGION_18_19_BASE_IDX                                                     2
5470 #define mmCM2_CM_GAMCOR_RAMA_REGION_20_21                                                              0x1033
5471 #define mmCM2_CM_GAMCOR_RAMA_REGION_20_21_BASE_IDX                                                     2
5472 #define mmCM2_CM_GAMCOR_RAMA_REGION_22_23                                                              0x1034
5473 #define mmCM2_CM_GAMCOR_RAMA_REGION_22_23_BASE_IDX                                                     2
5474 #define mmCM2_CM_GAMCOR_RAMA_REGION_24_25                                                              0x1035
5475 #define mmCM2_CM_GAMCOR_RAMA_REGION_24_25_BASE_IDX                                                     2
5476 #define mmCM2_CM_GAMCOR_RAMA_REGION_26_27                                                              0x1036
5477 #define mmCM2_CM_GAMCOR_RAMA_REGION_26_27_BASE_IDX                                                     2
5478 #define mmCM2_CM_GAMCOR_RAMA_REGION_28_29                                                              0x1037
5479 #define mmCM2_CM_GAMCOR_RAMA_REGION_28_29_BASE_IDX                                                     2
5480 #define mmCM2_CM_GAMCOR_RAMA_REGION_30_31                                                              0x1038
5481 #define mmCM2_CM_GAMCOR_RAMA_REGION_30_31_BASE_IDX                                                     2
5482 #define mmCM2_CM_GAMCOR_RAMA_REGION_32_33                                                              0x1039
5483 #define mmCM2_CM_GAMCOR_RAMA_REGION_32_33_BASE_IDX                                                     2
5484 #define mmCM2_CM_GAMCOR_RAMB_START_CNTL_B                                                              0x103a
5485 #define mmCM2_CM_GAMCOR_RAMB_START_CNTL_B_BASE_IDX                                                     2
5486 #define mmCM2_CM_GAMCOR_RAMB_START_CNTL_G                                                              0x103b
5487 #define mmCM2_CM_GAMCOR_RAMB_START_CNTL_G_BASE_IDX                                                     2
5488 #define mmCM2_CM_GAMCOR_RAMB_START_CNTL_R                                                              0x103c
5489 #define mmCM2_CM_GAMCOR_RAMB_START_CNTL_R_BASE_IDX                                                     2
5490 #define mmCM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B                                                        0x103d
5491 #define mmCM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B_BASE_IDX                                               2
5492 #define mmCM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G                                                        0x103e
5493 #define mmCM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G_BASE_IDX                                               2
5494 #define mmCM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R                                                        0x103f
5495 #define mmCM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R_BASE_IDX                                               2
5496 #define mmCM2_CM_GAMCOR_RAMB_START_BASE_CNTL_B                                                         0x1040
5497 #define mmCM2_CM_GAMCOR_RAMB_START_BASE_CNTL_B_BASE_IDX                                                2
5498 #define mmCM2_CM_GAMCOR_RAMB_START_BASE_CNTL_G                                                         0x1041
5499 #define mmCM2_CM_GAMCOR_RAMB_START_BASE_CNTL_G_BASE_IDX                                                2
5500 #define mmCM2_CM_GAMCOR_RAMB_START_BASE_CNTL_R                                                         0x1042
5501 #define mmCM2_CM_GAMCOR_RAMB_START_BASE_CNTL_R_BASE_IDX                                                2
5502 #define mmCM2_CM_GAMCOR_RAMB_END_CNTL1_B                                                               0x1043
5503 #define mmCM2_CM_GAMCOR_RAMB_END_CNTL1_B_BASE_IDX                                                      2
5504 #define mmCM2_CM_GAMCOR_RAMB_END_CNTL2_B                                                               0x1044
5505 #define mmCM2_CM_GAMCOR_RAMB_END_CNTL2_B_BASE_IDX                                                      2
5506 #define mmCM2_CM_GAMCOR_RAMB_END_CNTL1_G                                                               0x1045
5507 #define mmCM2_CM_GAMCOR_RAMB_END_CNTL1_G_BASE_IDX                                                      2
5508 #define mmCM2_CM_GAMCOR_RAMB_END_CNTL2_G                                                               0x1046
5509 #define mmCM2_CM_GAMCOR_RAMB_END_CNTL2_G_BASE_IDX                                                      2
5510 #define mmCM2_CM_GAMCOR_RAMB_END_CNTL1_R                                                               0x1047
5511 #define mmCM2_CM_GAMCOR_RAMB_END_CNTL1_R_BASE_IDX                                                      2
5512 #define mmCM2_CM_GAMCOR_RAMB_END_CNTL2_R                                                               0x1048
5513 #define mmCM2_CM_GAMCOR_RAMB_END_CNTL2_R_BASE_IDX                                                      2
5514 #define mmCM2_CM_GAMCOR_RAMB_OFFSET_B                                                                  0x1049
5515 #define mmCM2_CM_GAMCOR_RAMB_OFFSET_B_BASE_IDX                                                         2
5516 #define mmCM2_CM_GAMCOR_RAMB_OFFSET_G                                                                  0x104a
5517 #define mmCM2_CM_GAMCOR_RAMB_OFFSET_G_BASE_IDX                                                         2
5518 #define mmCM2_CM_GAMCOR_RAMB_OFFSET_R                                                                  0x104b
5519 #define mmCM2_CM_GAMCOR_RAMB_OFFSET_R_BASE_IDX                                                         2
5520 #define mmCM2_CM_GAMCOR_RAMB_REGION_0_1                                                                0x104c
5521 #define mmCM2_CM_GAMCOR_RAMB_REGION_0_1_BASE_IDX                                                       2
5522 #define mmCM2_CM_GAMCOR_RAMB_REGION_2_3                                                                0x104d
5523 #define mmCM2_CM_GAMCOR_RAMB_REGION_2_3_BASE_IDX                                                       2
5524 #define mmCM2_CM_GAMCOR_RAMB_REGION_4_5                                                                0x104e
5525 #define mmCM2_CM_GAMCOR_RAMB_REGION_4_5_BASE_IDX                                                       2
5526 #define mmCM2_CM_GAMCOR_RAMB_REGION_6_7                                                                0x104f
5527 #define mmCM2_CM_GAMCOR_RAMB_REGION_6_7_BASE_IDX                                                       2
5528 #define mmCM2_CM_GAMCOR_RAMB_REGION_8_9                                                                0x1050
5529 #define mmCM2_CM_GAMCOR_RAMB_REGION_8_9_BASE_IDX                                                       2
5530 #define mmCM2_CM_GAMCOR_RAMB_REGION_10_11                                                              0x1051
5531 #define mmCM2_CM_GAMCOR_RAMB_REGION_10_11_BASE_IDX                                                     2
5532 #define mmCM2_CM_GAMCOR_RAMB_REGION_12_13                                                              0x1052
5533 #define mmCM2_CM_GAMCOR_RAMB_REGION_12_13_BASE_IDX                                                     2
5534 #define mmCM2_CM_GAMCOR_RAMB_REGION_14_15                                                              0x1053
5535 #define mmCM2_CM_GAMCOR_RAMB_REGION_14_15_BASE_IDX                                                     2
5536 #define mmCM2_CM_GAMCOR_RAMB_REGION_16_17                                                              0x1054
5537 #define mmCM2_CM_GAMCOR_RAMB_REGION_16_17_BASE_IDX                                                     2
5538 #define mmCM2_CM_GAMCOR_RAMB_REGION_18_19                                                              0x1055
5539 #define mmCM2_CM_GAMCOR_RAMB_REGION_18_19_BASE_IDX                                                     2
5540 #define mmCM2_CM_GAMCOR_RAMB_REGION_20_21                                                              0x1056
5541 #define mmCM2_CM_GAMCOR_RAMB_REGION_20_21_BASE_IDX                                                     2
5542 #define mmCM2_CM_GAMCOR_RAMB_REGION_22_23                                                              0x1057
5543 #define mmCM2_CM_GAMCOR_RAMB_REGION_22_23_BASE_IDX                                                     2
5544 #define mmCM2_CM_GAMCOR_RAMB_REGION_24_25                                                              0x1058
5545 #define mmCM2_CM_GAMCOR_RAMB_REGION_24_25_BASE_IDX                                                     2
5546 #define mmCM2_CM_GAMCOR_RAMB_REGION_26_27                                                              0x1059
5547 #define mmCM2_CM_GAMCOR_RAMB_REGION_26_27_BASE_IDX                                                     2
5548 #define mmCM2_CM_GAMCOR_RAMB_REGION_28_29                                                              0x105a
5549 #define mmCM2_CM_GAMCOR_RAMB_REGION_28_29_BASE_IDX                                                     2
5550 #define mmCM2_CM_GAMCOR_RAMB_REGION_30_31                                                              0x105b
5551 #define mmCM2_CM_GAMCOR_RAMB_REGION_30_31_BASE_IDX                                                     2
5552 #define mmCM2_CM_GAMCOR_RAMB_REGION_32_33                                                              0x105c
5553 #define mmCM2_CM_GAMCOR_RAMB_REGION_32_33_BASE_IDX                                                     2
5554 #define mmCM2_CM_BLNDGAM_CONTROL                                                                       0x105d
5555 #define mmCM2_CM_BLNDGAM_CONTROL_BASE_IDX                                                              2
5556 #define mmCM2_CM_BLNDGAM_LUT_INDEX                                                                     0x105e
5557 #define mmCM2_CM_BLNDGAM_LUT_INDEX_BASE_IDX                                                            2
5558 #define mmCM2_CM_BLNDGAM_LUT_DATA                                                                      0x105f
5559 #define mmCM2_CM_BLNDGAM_LUT_DATA_BASE_IDX                                                             2
5560 #define mmCM2_CM_BLNDGAM_LUT_CONTROL                                                                   0x1060
5561 #define mmCM2_CM_BLNDGAM_LUT_CONTROL_BASE_IDX                                                          2
5562 #define mmCM2_CM_BLNDGAM_RAMA_START_CNTL_B                                                             0x1061
5563 #define mmCM2_CM_BLNDGAM_RAMA_START_CNTL_B_BASE_IDX                                                    2
5564 #define mmCM2_CM_BLNDGAM_RAMA_START_CNTL_G                                                             0x1062
5565 #define mmCM2_CM_BLNDGAM_RAMA_START_CNTL_G_BASE_IDX                                                    2
5566 #define mmCM2_CM_BLNDGAM_RAMA_START_CNTL_R                                                             0x1063
5567 #define mmCM2_CM_BLNDGAM_RAMA_START_CNTL_R_BASE_IDX                                                    2
5568 #define mmCM2_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_B                                                       0x1064
5569 #define mmCM2_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_B_BASE_IDX                                              2
5570 #define mmCM2_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_G                                                       0x1065
5571 #define mmCM2_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_G_BASE_IDX                                              2
5572 #define mmCM2_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_R                                                       0x1066
5573 #define mmCM2_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_R_BASE_IDX                                              2
5574 #define mmCM2_CM_BLNDGAM_RAMA_START_BASE_CNTL_B                                                        0x1067
5575 #define mmCM2_CM_BLNDGAM_RAMA_START_BASE_CNTL_B_BASE_IDX                                               2
5576 #define mmCM2_CM_BLNDGAM_RAMA_START_BASE_CNTL_G                                                        0x1068
5577 #define mmCM2_CM_BLNDGAM_RAMA_START_BASE_CNTL_G_BASE_IDX                                               2
5578 #define mmCM2_CM_BLNDGAM_RAMA_START_BASE_CNTL_R                                                        0x1069
5579 #define mmCM2_CM_BLNDGAM_RAMA_START_BASE_CNTL_R_BASE_IDX                                               2
5580 #define mmCM2_CM_BLNDGAM_RAMA_END_CNTL1_B                                                              0x106a
5581 #define mmCM2_CM_BLNDGAM_RAMA_END_CNTL1_B_BASE_IDX                                                     2
5582 #define mmCM2_CM_BLNDGAM_RAMA_END_CNTL2_B                                                              0x106b
5583 #define mmCM2_CM_BLNDGAM_RAMA_END_CNTL2_B_BASE_IDX                                                     2
5584 #define mmCM2_CM_BLNDGAM_RAMA_END_CNTL1_G                                                              0x106c
5585 #define mmCM2_CM_BLNDGAM_RAMA_END_CNTL1_G_BASE_IDX                                                     2
5586 #define mmCM2_CM_BLNDGAM_RAMA_END_CNTL2_G                                                              0x106d
5587 #define mmCM2_CM_BLNDGAM_RAMA_END_CNTL2_G_BASE_IDX                                                     2
5588 #define mmCM2_CM_BLNDGAM_RAMA_END_CNTL1_R                                                              0x106e
5589 #define mmCM2_CM_BLNDGAM_RAMA_END_CNTL1_R_BASE_IDX                                                     2
5590 #define mmCM2_CM_BLNDGAM_RAMA_END_CNTL2_R                                                              0x106f
5591 #define mmCM2_CM_BLNDGAM_RAMA_END_CNTL2_R_BASE_IDX                                                     2
5592 #define mmCM2_CM_BLNDGAM_RAMA_OFFSET_B                                                                 0x1070
5593 #define mmCM2_CM_BLNDGAM_RAMA_OFFSET_B_BASE_IDX                                                        2
5594 #define mmCM2_CM_BLNDGAM_RAMA_OFFSET_G                                                                 0x1071
5595 #define mmCM2_CM_BLNDGAM_RAMA_OFFSET_G_BASE_IDX                                                        2
5596 #define mmCM2_CM_BLNDGAM_RAMA_OFFSET_R                                                                 0x1072
5597 #define mmCM2_CM_BLNDGAM_RAMA_OFFSET_R_BASE_IDX                                                        2
5598 #define mmCM2_CM_BLNDGAM_RAMA_REGION_0_1                                                               0x1073
5599 #define mmCM2_CM_BLNDGAM_RAMA_REGION_0_1_BASE_IDX                                                      2
5600 #define mmCM2_CM_BLNDGAM_RAMA_REGION_2_3                                                               0x1074
5601 #define mmCM2_CM_BLNDGAM_RAMA_REGION_2_3_BASE_IDX                                                      2
5602 #define mmCM2_CM_BLNDGAM_RAMA_REGION_4_5                                                               0x1075
5603 #define mmCM2_CM_BLNDGAM_RAMA_REGION_4_5_BASE_IDX                                                      2
5604 #define mmCM2_CM_BLNDGAM_RAMA_REGION_6_7                                                               0x1076
5605 #define mmCM2_CM_BLNDGAM_RAMA_REGION_6_7_BASE_IDX                                                      2
5606 #define mmCM2_CM_BLNDGAM_RAMA_REGION_8_9                                                               0x1077
5607 #define mmCM2_CM_BLNDGAM_RAMA_REGION_8_9_BASE_IDX                                                      2
5608 #define mmCM2_CM_BLNDGAM_RAMA_REGION_10_11                                                             0x1078
5609 #define mmCM2_CM_BLNDGAM_RAMA_REGION_10_11_BASE_IDX                                                    2
5610 #define mmCM2_CM_BLNDGAM_RAMA_REGION_12_13                                                             0x1079
5611 #define mmCM2_CM_BLNDGAM_RAMA_REGION_12_13_BASE_IDX                                                    2
5612 #define mmCM2_CM_BLNDGAM_RAMA_REGION_14_15                                                             0x107a
5613 #define mmCM2_CM_BLNDGAM_RAMA_REGION_14_15_BASE_IDX                                                    2
5614 #define mmCM2_CM_BLNDGAM_RAMA_REGION_16_17                                                             0x107b
5615 #define mmCM2_CM_BLNDGAM_RAMA_REGION_16_17_BASE_IDX                                                    2
5616 #define mmCM2_CM_BLNDGAM_RAMA_REGION_18_19                                                             0x107c
5617 #define mmCM2_CM_BLNDGAM_RAMA_REGION_18_19_BASE_IDX                                                    2
5618 #define mmCM2_CM_BLNDGAM_RAMA_REGION_20_21                                                             0x107d
5619 #define mmCM2_CM_BLNDGAM_RAMA_REGION_20_21_BASE_IDX                                                    2
5620 #define mmCM2_CM_BLNDGAM_RAMA_REGION_22_23                                                             0x107e
5621 #define mmCM2_CM_BLNDGAM_RAMA_REGION_22_23_BASE_IDX                                                    2
5622 #define mmCM2_CM_BLNDGAM_RAMA_REGION_24_25                                                             0x107f
5623 #define mmCM2_CM_BLNDGAM_RAMA_REGION_24_25_BASE_IDX                                                    2
5624 #define mmCM2_CM_BLNDGAM_RAMA_REGION_26_27                                                             0x1080
5625 #define mmCM2_CM_BLNDGAM_RAMA_REGION_26_27_BASE_IDX                                                    2
5626 #define mmCM2_CM_BLNDGAM_RAMA_REGION_28_29                                                             0x1081
5627 #define mmCM2_CM_BLNDGAM_RAMA_REGION_28_29_BASE_IDX                                                    2
5628 #define mmCM2_CM_BLNDGAM_RAMA_REGION_30_31                                                             0x1082
5629 #define mmCM2_CM_BLNDGAM_RAMA_REGION_30_31_BASE_IDX                                                    2
5630 #define mmCM2_CM_BLNDGAM_RAMA_REGION_32_33                                                             0x1083
5631 #define mmCM2_CM_BLNDGAM_RAMA_REGION_32_33_BASE_IDX                                                    2
5632 #define mmCM2_CM_BLNDGAM_RAMB_START_CNTL_B                                                             0x1084
5633 #define mmCM2_CM_BLNDGAM_RAMB_START_CNTL_B_BASE_IDX                                                    2
5634 #define mmCM2_CM_BLNDGAM_RAMB_START_CNTL_G                                                             0x1085
5635 #define mmCM2_CM_BLNDGAM_RAMB_START_CNTL_G_BASE_IDX                                                    2
5636 #define mmCM2_CM_BLNDGAM_RAMB_START_CNTL_R                                                             0x1086
5637 #define mmCM2_CM_BLNDGAM_RAMB_START_CNTL_R_BASE_IDX                                                    2
5638 #define mmCM2_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_B                                                       0x1087
5639 #define mmCM2_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_B_BASE_IDX                                              2
5640 #define mmCM2_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_G                                                       0x1088
5641 #define mmCM2_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_G_BASE_IDX                                              2
5642 #define mmCM2_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_R                                                       0x1089
5643 #define mmCM2_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_R_BASE_IDX                                              2
5644 #define mmCM2_CM_BLNDGAM_RAMB_START_BASE_CNTL_B                                                        0x108a
5645 #define mmCM2_CM_BLNDGAM_RAMB_START_BASE_CNTL_B_BASE_IDX                                               2
5646 #define mmCM2_CM_BLNDGAM_RAMB_START_BASE_CNTL_G                                                        0x108b
5647 #define mmCM2_CM_BLNDGAM_RAMB_START_BASE_CNTL_G_BASE_IDX                                               2
5648 #define mmCM2_CM_BLNDGAM_RAMB_START_BASE_CNTL_R                                                        0x108c
5649 #define mmCM2_CM_BLNDGAM_RAMB_START_BASE_CNTL_R_BASE_IDX                                               2
5650 #define mmCM2_CM_BLNDGAM_RAMB_END_CNTL1_B                                                              0x108d
5651 #define mmCM2_CM_BLNDGAM_RAMB_END_CNTL1_B_BASE_IDX                                                     2
5652 #define mmCM2_CM_BLNDGAM_RAMB_END_CNTL2_B                                                              0x108e
5653 #define mmCM2_CM_BLNDGAM_RAMB_END_CNTL2_B_BASE_IDX                                                     2
5654 #define mmCM2_CM_BLNDGAM_RAMB_END_CNTL1_G                                                              0x108f
5655 #define mmCM2_CM_BLNDGAM_RAMB_END_CNTL1_G_BASE_IDX                                                     2
5656 #define mmCM2_CM_BLNDGAM_RAMB_END_CNTL2_G                                                              0x1090
5657 #define mmCM2_CM_BLNDGAM_RAMB_END_CNTL2_G_BASE_IDX                                                     2
5658 #define mmCM2_CM_BLNDGAM_RAMB_END_CNTL1_R                                                              0x1091
5659 #define mmCM2_CM_BLNDGAM_RAMB_END_CNTL1_R_BASE_IDX                                                     2
5660 #define mmCM2_CM_BLNDGAM_RAMB_END_CNTL2_R                                                              0x1092
5661 #define mmCM2_CM_BLNDGAM_RAMB_END_CNTL2_R_BASE_IDX                                                     2
5662 #define mmCM2_CM_BLNDGAM_RAMB_OFFSET_B                                                                 0x1093
5663 #define mmCM2_CM_BLNDGAM_RAMB_OFFSET_B_BASE_IDX                                                        2
5664 #define mmCM2_CM_BLNDGAM_RAMB_OFFSET_G                                                                 0x1094
5665 #define mmCM2_CM_BLNDGAM_RAMB_OFFSET_G_BASE_IDX                                                        2
5666 #define mmCM2_CM_BLNDGAM_RAMB_OFFSET_R                                                                 0x1095
5667 #define mmCM2_CM_BLNDGAM_RAMB_OFFSET_R_BASE_IDX                                                        2
5668 #define mmCM2_CM_BLNDGAM_RAMB_REGION_0_1                                                               0x1096
5669 #define mmCM2_CM_BLNDGAM_RAMB_REGION_0_1_BASE_IDX                                                      2
5670 #define mmCM2_CM_BLNDGAM_RAMB_REGION_2_3                                                               0x1097
5671 #define mmCM2_CM_BLNDGAM_RAMB_REGION_2_3_BASE_IDX                                                      2
5672 #define mmCM2_CM_BLNDGAM_RAMB_REGION_4_5                                                               0x1098
5673 #define mmCM2_CM_BLNDGAM_RAMB_REGION_4_5_BASE_IDX                                                      2
5674 #define mmCM2_CM_BLNDGAM_RAMB_REGION_6_7                                                               0x1099
5675 #define mmCM2_CM_BLNDGAM_RAMB_REGION_6_7_BASE_IDX                                                      2
5676 #define mmCM2_CM_BLNDGAM_RAMB_REGION_8_9                                                               0x109a
5677 #define mmCM2_CM_BLNDGAM_RAMB_REGION_8_9_BASE_IDX                                                      2
5678 #define mmCM2_CM_BLNDGAM_RAMB_REGION_10_11                                                             0x109b
5679 #define mmCM2_CM_BLNDGAM_RAMB_REGION_10_11_BASE_IDX                                                    2
5680 #define mmCM2_CM_BLNDGAM_RAMB_REGION_12_13                                                             0x109c
5681 #define mmCM2_CM_BLNDGAM_RAMB_REGION_12_13_BASE_IDX                                                    2
5682 #define mmCM2_CM_BLNDGAM_RAMB_REGION_14_15                                                             0x109d
5683 #define mmCM2_CM_BLNDGAM_RAMB_REGION_14_15_BASE_IDX                                                    2
5684 #define mmCM2_CM_BLNDGAM_RAMB_REGION_16_17                                                             0x109e
5685 #define mmCM2_CM_BLNDGAM_RAMB_REGION_16_17_BASE_IDX                                                    2
5686 #define mmCM2_CM_BLNDGAM_RAMB_REGION_18_19                                                             0x109f
5687 #define mmCM2_CM_BLNDGAM_RAMB_REGION_18_19_BASE_IDX                                                    2
5688 #define mmCM2_CM_BLNDGAM_RAMB_REGION_20_21                                                             0x10a0
5689 #define mmCM2_CM_BLNDGAM_RAMB_REGION_20_21_BASE_IDX                                                    2
5690 #define mmCM2_CM_BLNDGAM_RAMB_REGION_22_23                                                             0x10a1
5691 #define mmCM2_CM_BLNDGAM_RAMB_REGION_22_23_BASE_IDX                                                    2
5692 #define mmCM2_CM_BLNDGAM_RAMB_REGION_24_25                                                             0x10a2
5693 #define mmCM2_CM_BLNDGAM_RAMB_REGION_24_25_BASE_IDX                                                    2
5694 #define mmCM2_CM_BLNDGAM_RAMB_REGION_26_27                                                             0x10a3
5695 #define mmCM2_CM_BLNDGAM_RAMB_REGION_26_27_BASE_IDX                                                    2
5696 #define mmCM2_CM_BLNDGAM_RAMB_REGION_28_29                                                             0x10a4
5697 #define mmCM2_CM_BLNDGAM_RAMB_REGION_28_29_BASE_IDX                                                    2
5698 #define mmCM2_CM_BLNDGAM_RAMB_REGION_30_31                                                             0x10a5
5699 #define mmCM2_CM_BLNDGAM_RAMB_REGION_30_31_BASE_IDX                                                    2
5700 #define mmCM2_CM_BLNDGAM_RAMB_REGION_32_33                                                             0x10a6
5701 #define mmCM2_CM_BLNDGAM_RAMB_REGION_32_33_BASE_IDX                                                    2
5702 #define mmCM2_CM_HDR_MULT_COEF                                                                         0x10a7
5703 #define mmCM2_CM_HDR_MULT_COEF_BASE_IDX                                                                2
5704 #define mmCM2_CM_MEM_PWR_CTRL                                                                          0x10a8
5705 #define mmCM2_CM_MEM_PWR_CTRL_BASE_IDX                                                                 2
5706 #define mmCM2_CM_MEM_PWR_STATUS                                                                        0x10a9
5707 #define mmCM2_CM_MEM_PWR_STATUS_BASE_IDX                                                               2
5708 #define mmCM2_CM_DEALPHA                                                                               0x10ab
5709 #define mmCM2_CM_DEALPHA_BASE_IDX                                                                      2
5710 #define mmCM2_CM_COEF_FORMAT                                                                           0x10ac
5711 #define mmCM2_CM_COEF_FORMAT_BASE_IDX                                                                  2
5712 #define mmCM2_CM_SHAPER_CONTROL                                                                        0x10ad
5713 #define mmCM2_CM_SHAPER_CONTROL_BASE_IDX                                                               2
5714 #define mmCM2_CM_SHAPER_OFFSET_R                                                                       0x10ae
5715 #define mmCM2_CM_SHAPER_OFFSET_R_BASE_IDX                                                              2
5716 #define mmCM2_CM_SHAPER_OFFSET_G                                                                       0x10af
5717 #define mmCM2_CM_SHAPER_OFFSET_G_BASE_IDX                                                              2
5718 #define mmCM2_CM_SHAPER_OFFSET_B                                                                       0x10b0
5719 #define mmCM2_CM_SHAPER_OFFSET_B_BASE_IDX                                                              2
5720 #define mmCM2_CM_SHAPER_SCALE_R                                                                        0x10b1
5721 #define mmCM2_CM_SHAPER_SCALE_R_BASE_IDX                                                               2
5722 #define mmCM2_CM_SHAPER_SCALE_G_B                                                                      0x10b2
5723 #define mmCM2_CM_SHAPER_SCALE_G_B_BASE_IDX                                                             2
5724 #define mmCM2_CM_SHAPER_LUT_INDEX                                                                      0x10b3
5725 #define mmCM2_CM_SHAPER_LUT_INDEX_BASE_IDX                                                             2
5726 #define mmCM2_CM_SHAPER_LUT_DATA                                                                       0x10b4
5727 #define mmCM2_CM_SHAPER_LUT_DATA_BASE_IDX                                                              2
5728 #define mmCM2_CM_SHAPER_LUT_WRITE_EN_MASK                                                              0x10b5
5729 #define mmCM2_CM_SHAPER_LUT_WRITE_EN_MASK_BASE_IDX                                                     2
5730 #define mmCM2_CM_SHAPER_RAMA_START_CNTL_B                                                              0x10b6
5731 #define mmCM2_CM_SHAPER_RAMA_START_CNTL_B_BASE_IDX                                                     2
5732 #define mmCM2_CM_SHAPER_RAMA_START_CNTL_G                                                              0x10b7
5733 #define mmCM2_CM_SHAPER_RAMA_START_CNTL_G_BASE_IDX                                                     2
5734 #define mmCM2_CM_SHAPER_RAMA_START_CNTL_R                                                              0x10b8
5735 #define mmCM2_CM_SHAPER_RAMA_START_CNTL_R_BASE_IDX                                                     2
5736 #define mmCM2_CM_SHAPER_RAMA_END_CNTL_B                                                                0x10b9
5737 #define mmCM2_CM_SHAPER_RAMA_END_CNTL_B_BASE_IDX                                                       2
5738 #define mmCM2_CM_SHAPER_RAMA_END_CNTL_G                                                                0x10ba
5739 #define mmCM2_CM_SHAPER_RAMA_END_CNTL_G_BASE_IDX                                                       2
5740 #define mmCM2_CM_SHAPER_RAMA_END_CNTL_R                                                                0x10bb
5741 #define mmCM2_CM_SHAPER_RAMA_END_CNTL_R_BASE_IDX                                                       2
5742 #define mmCM2_CM_SHAPER_RAMA_REGION_0_1                                                                0x10bc
5743 #define mmCM2_CM_SHAPER_RAMA_REGION_0_1_BASE_IDX                                                       2
5744 #define mmCM2_CM_SHAPER_RAMA_REGION_2_3                                                                0x10bd
5745 #define mmCM2_CM_SHAPER_RAMA_REGION_2_3_BASE_IDX                                                       2
5746 #define mmCM2_CM_SHAPER_RAMA_REGION_4_5                                                                0x10be
5747 #define mmCM2_CM_SHAPER_RAMA_REGION_4_5_BASE_IDX                                                       2
5748 #define mmCM2_CM_SHAPER_RAMA_REGION_6_7                                                                0x10bf
5749 #define mmCM2_CM_SHAPER_RAMA_REGION_6_7_BASE_IDX                                                       2
5750 #define mmCM2_CM_SHAPER_RAMA_REGION_8_9                                                                0x10c0
5751 #define mmCM2_CM_SHAPER_RAMA_REGION_8_9_BASE_IDX                                                       2
5752 #define mmCM2_CM_SHAPER_RAMA_REGION_10_11                                                              0x10c1
5753 #define mmCM2_CM_SHAPER_RAMA_REGION_10_11_BASE_IDX                                                     2
5754 #define mmCM2_CM_SHAPER_RAMA_REGION_12_13                                                              0x10c2
5755 #define mmCM2_CM_SHAPER_RAMA_REGION_12_13_BASE_IDX                                                     2
5756 #define mmCM2_CM_SHAPER_RAMA_REGION_14_15                                                              0x10c3
5757 #define mmCM2_CM_SHAPER_RAMA_REGION_14_15_BASE_IDX                                                     2
5758 #define mmCM2_CM_SHAPER_RAMA_REGION_16_17                                                              0x10c4
5759 #define mmCM2_CM_SHAPER_RAMA_REGION_16_17_BASE_IDX                                                     2
5760 #define mmCM2_CM_SHAPER_RAMA_REGION_18_19                                                              0x10c5
5761 #define mmCM2_CM_SHAPER_RAMA_REGION_18_19_BASE_IDX                                                     2
5762 #define mmCM2_CM_SHAPER_RAMA_REGION_20_21                                                              0x10c6
5763 #define mmCM2_CM_SHAPER_RAMA_REGION_20_21_BASE_IDX                                                     2
5764 #define mmCM2_CM_SHAPER_RAMA_REGION_22_23                                                              0x10c7
5765 #define mmCM2_CM_SHAPER_RAMA_REGION_22_23_BASE_IDX                                                     2
5766 #define mmCM2_CM_SHAPER_RAMA_REGION_24_25                                                              0x10c8
5767 #define mmCM2_CM_SHAPER_RAMA_REGION_24_25_BASE_IDX                                                     2
5768 #define mmCM2_CM_SHAPER_RAMA_REGION_26_27                                                              0x10c9
5769 #define mmCM2_CM_SHAPER_RAMA_REGION_26_27_BASE_IDX                                                     2
5770 #define mmCM2_CM_SHAPER_RAMA_REGION_28_29                                                              0x10ca
5771 #define mmCM2_CM_SHAPER_RAMA_REGION_28_29_BASE_IDX                                                     2
5772 #define mmCM2_CM_SHAPER_RAMA_REGION_30_31                                                              0x10cb
5773 #define mmCM2_CM_SHAPER_RAMA_REGION_30_31_BASE_IDX                                                     2
5774 #define mmCM2_CM_SHAPER_RAMA_REGION_32_33                                                              0x10cc
5775 #define mmCM2_CM_SHAPER_RAMA_REGION_32_33_BASE_IDX                                                     2
5776 #define mmCM2_CM_SHAPER_RAMB_START_CNTL_B                                                              0x10cd
5777 #define mmCM2_CM_SHAPER_RAMB_START_CNTL_B_BASE_IDX                                                     2
5778 #define mmCM2_CM_SHAPER_RAMB_START_CNTL_G                                                              0x10ce
5779 #define mmCM2_CM_SHAPER_RAMB_START_CNTL_G_BASE_IDX                                                     2
5780 #define mmCM2_CM_SHAPER_RAMB_START_CNTL_R                                                              0x10cf
5781 #define mmCM2_CM_SHAPER_RAMB_START_CNTL_R_BASE_IDX                                                     2
5782 #define mmCM2_CM_SHAPER_RAMB_END_CNTL_B                                                                0x10d0
5783 #define mmCM2_CM_SHAPER_RAMB_END_CNTL_B_BASE_IDX                                                       2
5784 #define mmCM2_CM_SHAPER_RAMB_END_CNTL_G                                                                0x10d1
5785 #define mmCM2_CM_SHAPER_RAMB_END_CNTL_G_BASE_IDX                                                       2
5786 #define mmCM2_CM_SHAPER_RAMB_END_CNTL_R                                                                0x10d2
5787 #define mmCM2_CM_SHAPER_RAMB_END_CNTL_R_BASE_IDX                                                       2
5788 #define mmCM2_CM_SHAPER_RAMB_REGION_0_1                                                                0x10d3
5789 #define mmCM2_CM_SHAPER_RAMB_REGION_0_1_BASE_IDX                                                       2
5790 #define mmCM2_CM_SHAPER_RAMB_REGION_2_3                                                                0x10d4
5791 #define mmCM2_CM_SHAPER_RAMB_REGION_2_3_BASE_IDX                                                       2
5792 #define mmCM2_CM_SHAPER_RAMB_REGION_4_5                                                                0x10d5
5793 #define mmCM2_CM_SHAPER_RAMB_REGION_4_5_BASE_IDX                                                       2
5794 #define mmCM2_CM_SHAPER_RAMB_REGION_6_7                                                                0x10d6
5795 #define mmCM2_CM_SHAPER_RAMB_REGION_6_7_BASE_IDX                                                       2
5796 #define mmCM2_CM_SHAPER_RAMB_REGION_8_9                                                                0x10d7
5797 #define mmCM2_CM_SHAPER_RAMB_REGION_8_9_BASE_IDX                                                       2
5798 #define mmCM2_CM_SHAPER_RAMB_REGION_10_11                                                              0x10d8
5799 #define mmCM2_CM_SHAPER_RAMB_REGION_10_11_BASE_IDX                                                     2
5800 #define mmCM2_CM_SHAPER_RAMB_REGION_12_13                                                              0x10d9
5801 #define mmCM2_CM_SHAPER_RAMB_REGION_12_13_BASE_IDX                                                     2
5802 #define mmCM2_CM_SHAPER_RAMB_REGION_14_15                                                              0x10da
5803 #define mmCM2_CM_SHAPER_RAMB_REGION_14_15_BASE_IDX                                                     2
5804 #define mmCM2_CM_SHAPER_RAMB_REGION_16_17                                                              0x10db
5805 #define mmCM2_CM_SHAPER_RAMB_REGION_16_17_BASE_IDX                                                     2
5806 #define mmCM2_CM_SHAPER_RAMB_REGION_18_19                                                              0x10dc
5807 #define mmCM2_CM_SHAPER_RAMB_REGION_18_19_BASE_IDX                                                     2
5808 #define mmCM2_CM_SHAPER_RAMB_REGION_20_21                                                              0x10dd
5809 #define mmCM2_CM_SHAPER_RAMB_REGION_20_21_BASE_IDX                                                     2
5810 #define mmCM2_CM_SHAPER_RAMB_REGION_22_23                                                              0x10de
5811 #define mmCM2_CM_SHAPER_RAMB_REGION_22_23_BASE_IDX                                                     2
5812 #define mmCM2_CM_SHAPER_RAMB_REGION_24_25                                                              0x10df
5813 #define mmCM2_CM_SHAPER_RAMB_REGION_24_25_BASE_IDX                                                     2
5814 #define mmCM2_CM_SHAPER_RAMB_REGION_26_27                                                              0x10e0
5815 #define mmCM2_CM_SHAPER_RAMB_REGION_26_27_BASE_IDX                                                     2
5816 #define mmCM2_CM_SHAPER_RAMB_REGION_28_29                                                              0x10e1
5817 #define mmCM2_CM_SHAPER_RAMB_REGION_28_29_BASE_IDX                                                     2
5818 #define mmCM2_CM_SHAPER_RAMB_REGION_30_31                                                              0x10e2
5819 #define mmCM2_CM_SHAPER_RAMB_REGION_30_31_BASE_IDX                                                     2
5820 #define mmCM2_CM_SHAPER_RAMB_REGION_32_33                                                              0x10e3
5821 #define mmCM2_CM_SHAPER_RAMB_REGION_32_33_BASE_IDX                                                     2
5822 #define mmCM2_CM_MEM_PWR_CTRL2                                                                         0x10e4
5823 #define mmCM2_CM_MEM_PWR_CTRL2_BASE_IDX                                                                2
5824 #define mmCM2_CM_MEM_PWR_STATUS2                                                                       0x10e5
5825 #define mmCM2_CM_MEM_PWR_STATUS2_BASE_IDX                                                              2
5826 #define mmCM2_CM_3DLUT_MODE                                                                            0x10e6
5827 #define mmCM2_CM_3DLUT_MODE_BASE_IDX                                                                   2
5828 #define mmCM2_CM_3DLUT_INDEX                                                                           0x10e7
5829 #define mmCM2_CM_3DLUT_INDEX_BASE_IDX                                                                  2
5830 #define mmCM2_CM_3DLUT_DATA                                                                            0x10e8
5831 #define mmCM2_CM_3DLUT_DATA_BASE_IDX                                                                   2
5832 #define mmCM2_CM_3DLUT_DATA_30BIT                                                                      0x10e9
5833 #define mmCM2_CM_3DLUT_DATA_30BIT_BASE_IDX                                                             2
5834 #define mmCM2_CM_3DLUT_READ_WRITE_CONTROL                                                              0x10ea
5835 #define mmCM2_CM_3DLUT_READ_WRITE_CONTROL_BASE_IDX                                                     2
5836 #define mmCM2_CM_3DLUT_OUT_NORM_FACTOR                                                                 0x10eb
5837 #define mmCM2_CM_3DLUT_OUT_NORM_FACTOR_BASE_IDX                                                        2
5838 #define mmCM2_CM_3DLUT_OUT_OFFSET_R                                                                    0x10ec
5839 #define mmCM2_CM_3DLUT_OUT_OFFSET_R_BASE_IDX                                                           2
5840 #define mmCM2_CM_3DLUT_OUT_OFFSET_G                                                                    0x10ed
5841 #define mmCM2_CM_3DLUT_OUT_OFFSET_G_BASE_IDX                                                           2
5842 #define mmCM2_CM_3DLUT_OUT_OFFSET_B                                                                    0x10ee
5843 #define mmCM2_CM_3DLUT_OUT_OFFSET_B_BASE_IDX                                                           2
5844 
5845 
5846 // addressBlock: dce_dc_dpp2_dispdec_dpp_dcperfmon_dc_perfmon_dispdec
5847 // base address: 0x43e8
5848 #define mmDC_PERFMON13_PERFCOUNTER_CNTL                                                                0x10fa
5849 #define mmDC_PERFMON13_PERFCOUNTER_CNTL_BASE_IDX                                                       2
5850 #define mmDC_PERFMON13_PERFCOUNTER_CNTL2                                                               0x10fb
5851 #define mmDC_PERFMON13_PERFCOUNTER_CNTL2_BASE_IDX                                                      2
5852 #define mmDC_PERFMON13_PERFCOUNTER_STATE                                                               0x10fc
5853 #define mmDC_PERFMON13_PERFCOUNTER_STATE_BASE_IDX                                                      2
5854 #define mmDC_PERFMON13_PERFMON_CNTL                                                                    0x10fd
5855 #define mmDC_PERFMON13_PERFMON_CNTL_BASE_IDX                                                           2
5856 #define mmDC_PERFMON13_PERFMON_CNTL2                                                                   0x10fe
5857 #define mmDC_PERFMON13_PERFMON_CNTL2_BASE_IDX                                                          2
5858 #define mmDC_PERFMON13_PERFMON_CVALUE_INT_MISC                                                         0x10ff
5859 #define mmDC_PERFMON13_PERFMON_CVALUE_INT_MISC_BASE_IDX                                                2
5860 #define mmDC_PERFMON13_PERFMON_CVALUE_LOW                                                              0x1100
5861 #define mmDC_PERFMON13_PERFMON_CVALUE_LOW_BASE_IDX                                                     2
5862 #define mmDC_PERFMON13_PERFMON_HI                                                                      0x1101
5863 #define mmDC_PERFMON13_PERFMON_HI_BASE_IDX                                                             2
5864 #define mmDC_PERFMON13_PERFMON_LOW                                                                     0x1102
5865 #define mmDC_PERFMON13_PERFMON_LOW_BASE_IDX                                                            2
5866 
5867 
5868 // addressBlock: dce_dc_dpp3_dispdec_dpp_top_dispdec
5869 // base address: 0x1104
5870 #define mmDPP_TOP3_DPP_CONTROL                                                                         0x1106
5871 #define mmDPP_TOP3_DPP_CONTROL_BASE_IDX                                                                2
5872 #define mmDPP_TOP3_DPP_SOFT_RESET                                                                      0x1107
5873 #define mmDPP_TOP3_DPP_SOFT_RESET_BASE_IDX                                                             2
5874 #define mmDPP_TOP3_DPP_CRC_VAL_R_G                                                                     0x1108
5875 #define mmDPP_TOP3_DPP_CRC_VAL_R_G_BASE_IDX                                                            2
5876 #define mmDPP_TOP3_DPP_CRC_VAL_B_A                                                                     0x1109
5877 #define mmDPP_TOP3_DPP_CRC_VAL_B_A_BASE_IDX                                                            2
5878 #define mmDPP_TOP3_DPP_CRC_CTRL                                                                        0x110a
5879 #define mmDPP_TOP3_DPP_CRC_CTRL_BASE_IDX                                                               2
5880 #define mmDPP_TOP3_HOST_READ_CONTROL                                                                   0x110b
5881 #define mmDPP_TOP3_HOST_READ_CONTROL_BASE_IDX                                                          2
5882 
5883 
5884 // addressBlock: dce_dc_dpp3_dispdec_cnvc_cfg_dispdec
5885 // base address: 0x1104
5886 #define mmCNVC_CFG3_CNVC_SURFACE_PIXEL_FORMAT                                                          0x1110
5887 #define mmCNVC_CFG3_CNVC_SURFACE_PIXEL_FORMAT_BASE_IDX                                                 2
5888 #define mmCNVC_CFG3_FORMAT_CONTROL                                                                     0x1111
5889 #define mmCNVC_CFG3_FORMAT_CONTROL_BASE_IDX                                                            2
5890 #define mmCNVC_CFG3_FCNV_FP_BIAS_R                                                                     0x1112
5891 #define mmCNVC_CFG3_FCNV_FP_BIAS_R_BASE_IDX                                                            2
5892 #define mmCNVC_CFG3_FCNV_FP_BIAS_G                                                                     0x1113
5893 #define mmCNVC_CFG3_FCNV_FP_BIAS_G_BASE_IDX                                                            2
5894 #define mmCNVC_CFG3_FCNV_FP_BIAS_B                                                                     0x1114
5895 #define mmCNVC_CFG3_FCNV_FP_BIAS_B_BASE_IDX                                                            2
5896 #define mmCNVC_CFG3_FCNV_FP_SCALE_R                                                                    0x1115
5897 #define mmCNVC_CFG3_FCNV_FP_SCALE_R_BASE_IDX                                                           2
5898 #define mmCNVC_CFG3_FCNV_FP_SCALE_G                                                                    0x1116
5899 #define mmCNVC_CFG3_FCNV_FP_SCALE_G_BASE_IDX                                                           2
5900 #define mmCNVC_CFG3_FCNV_FP_SCALE_B                                                                    0x1117
5901 #define mmCNVC_CFG3_FCNV_FP_SCALE_B_BASE_IDX                                                           2
5902 #define mmCNVC_CFG3_COLOR_KEYER_CONTROL                                                                0x1118
5903 #define mmCNVC_CFG3_COLOR_KEYER_CONTROL_BASE_IDX                                                       2
5904 #define mmCNVC_CFG3_COLOR_KEYER_ALPHA                                                                  0x1119
5905 #define mmCNVC_CFG3_COLOR_KEYER_ALPHA_BASE_IDX                                                         2
5906 #define mmCNVC_CFG3_COLOR_KEYER_RED                                                                    0x111a
5907 #define mmCNVC_CFG3_COLOR_KEYER_RED_BASE_IDX                                                           2
5908 #define mmCNVC_CFG3_COLOR_KEYER_GREEN                                                                  0x111b
5909 #define mmCNVC_CFG3_COLOR_KEYER_GREEN_BASE_IDX                                                         2
5910 #define mmCNVC_CFG3_COLOR_KEYER_BLUE                                                                   0x111c
5911 #define mmCNVC_CFG3_COLOR_KEYER_BLUE_BASE_IDX                                                          2
5912 #define mmCNVC_CFG3_ALPHA_2BIT_LUT                                                                     0x111e
5913 #define mmCNVC_CFG3_ALPHA_2BIT_LUT_BASE_IDX                                                            2
5914 #define mmCNVC_CFG3_PRE_DEALPHA                                                                        0x111f
5915 #define mmCNVC_CFG3_PRE_DEALPHA_BASE_IDX                                                               2
5916 #define mmCNVC_CFG3_PRE_CSC_MODE                                                                       0x1120
5917 #define mmCNVC_CFG3_PRE_CSC_MODE_BASE_IDX                                                              2
5918 #define mmCNVC_CFG3_PRE_CSC_C11_C12                                                                    0x1121
5919 #define mmCNVC_CFG3_PRE_CSC_C11_C12_BASE_IDX                                                           2
5920 #define mmCNVC_CFG3_PRE_CSC_C13_C14                                                                    0x1122
5921 #define mmCNVC_CFG3_PRE_CSC_C13_C14_BASE_IDX                                                           2
5922 #define mmCNVC_CFG3_PRE_CSC_C21_C22                                                                    0x1123
5923 #define mmCNVC_CFG3_PRE_CSC_C21_C22_BASE_IDX                                                           2
5924 #define mmCNVC_CFG3_PRE_CSC_C23_C24                                                                    0x1124
5925 #define mmCNVC_CFG3_PRE_CSC_C23_C24_BASE_IDX                                                           2
5926 #define mmCNVC_CFG3_PRE_CSC_C31_C32                                                                    0x1125
5927 #define mmCNVC_CFG3_PRE_CSC_C31_C32_BASE_IDX                                                           2
5928 #define mmCNVC_CFG3_PRE_CSC_C33_C34                                                                    0x1126
5929 #define mmCNVC_CFG3_PRE_CSC_C33_C34_BASE_IDX                                                           2
5930 #define mmCNVC_CFG3_PRE_CSC_B_C11_C12                                                                  0x1127
5931 #define mmCNVC_CFG3_PRE_CSC_B_C11_C12_BASE_IDX                                                         2
5932 #define mmCNVC_CFG3_PRE_CSC_B_C13_C14                                                                  0x1128
5933 #define mmCNVC_CFG3_PRE_CSC_B_C13_C14_BASE_IDX                                                         2
5934 #define mmCNVC_CFG3_PRE_CSC_B_C21_C22                                                                  0x1129
5935 #define mmCNVC_CFG3_PRE_CSC_B_C21_C22_BASE_IDX                                                         2
5936 #define mmCNVC_CFG3_PRE_CSC_B_C23_C24                                                                  0x112a
5937 #define mmCNVC_CFG3_PRE_CSC_B_C23_C24_BASE_IDX                                                         2
5938 #define mmCNVC_CFG3_PRE_CSC_B_C31_C32                                                                  0x112b
5939 #define mmCNVC_CFG3_PRE_CSC_B_C31_C32_BASE_IDX                                                         2
5940 #define mmCNVC_CFG3_PRE_CSC_B_C33_C34                                                                  0x112c
5941 #define mmCNVC_CFG3_PRE_CSC_B_C33_C34_BASE_IDX                                                         2
5942 #define mmCNVC_CFG3_CNVC_COEF_FORMAT                                                                   0x112d
5943 #define mmCNVC_CFG3_CNVC_COEF_FORMAT_BASE_IDX                                                          2
5944 #define mmCNVC_CFG3_PRE_DEGAM                                                                          0x112e
5945 #define mmCNVC_CFG3_PRE_DEGAM_BASE_IDX                                                                 2
5946 #define mmCNVC_CFG3_PRE_REALPHA                                                                        0x112f
5947 #define mmCNVC_CFG3_PRE_REALPHA_BASE_IDX                                                               2
5948 
5949 
5950 // addressBlock: dce_dc_dpp3_dispdec_cnvc_cur_dispdec
5951 // base address: 0x1104
5952 #define mmCNVC_CUR3_CURSOR0_CONTROL                                                                    0x1132
5953 #define mmCNVC_CUR3_CURSOR0_CONTROL_BASE_IDX                                                           2
5954 #define mmCNVC_CUR3_CURSOR0_COLOR0                                                                     0x1133
5955 #define mmCNVC_CUR3_CURSOR0_COLOR0_BASE_IDX                                                            2
5956 #define mmCNVC_CUR3_CURSOR0_COLOR1                                                                     0x1134
5957 #define mmCNVC_CUR3_CURSOR0_COLOR1_BASE_IDX                                                            2
5958 #define mmCNVC_CUR3_CURSOR0_FP_SCALE_BIAS                                                              0x1135
5959 #define mmCNVC_CUR3_CURSOR0_FP_SCALE_BIAS_BASE_IDX                                                     2
5960 
5961 
5962 // addressBlock: dce_dc_dpp3_dispdec_dscl_dispdec
5963 // base address: 0x1104
5964 #define mmDSCL3_SCL_COEF_RAM_TAP_SELECT                                                                0x113a
5965 #define mmDSCL3_SCL_COEF_RAM_TAP_SELECT_BASE_IDX                                                       2
5966 #define mmDSCL3_SCL_COEF_RAM_TAP_DATA                                                                  0x113b
5967 #define mmDSCL3_SCL_COEF_RAM_TAP_DATA_BASE_IDX                                                         2
5968 #define mmDSCL3_SCL_MODE                                                                               0x113c
5969 #define mmDSCL3_SCL_MODE_BASE_IDX                                                                      2
5970 #define mmDSCL3_SCL_TAP_CONTROL                                                                        0x113d
5971 #define mmDSCL3_SCL_TAP_CONTROL_BASE_IDX                                                               2
5972 #define mmDSCL3_DSCL_CONTROL                                                                           0x113e
5973 #define mmDSCL3_DSCL_CONTROL_BASE_IDX                                                                  2
5974 #define mmDSCL3_DSCL_2TAP_CONTROL                                                                      0x113f
5975 #define mmDSCL3_DSCL_2TAP_CONTROL_BASE_IDX                                                             2
5976 #define mmDSCL3_SCL_MANUAL_REPLICATE_CONTROL                                                           0x1140
5977 #define mmDSCL3_SCL_MANUAL_REPLICATE_CONTROL_BASE_IDX                                                  2
5978 #define mmDSCL3_SCL_HORZ_FILTER_SCALE_RATIO                                                            0x1141
5979 #define mmDSCL3_SCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX                                                   2
5980 #define mmDSCL3_SCL_HORZ_FILTER_INIT                                                                   0x1142
5981 #define mmDSCL3_SCL_HORZ_FILTER_INIT_BASE_IDX                                                          2
5982 #define mmDSCL3_SCL_HORZ_FILTER_SCALE_RATIO_C                                                          0x1143
5983 #define mmDSCL3_SCL_HORZ_FILTER_SCALE_RATIO_C_BASE_IDX                                                 2
5984 #define mmDSCL3_SCL_HORZ_FILTER_INIT_C                                                                 0x1144
5985 #define mmDSCL3_SCL_HORZ_FILTER_INIT_C_BASE_IDX                                                        2
5986 #define mmDSCL3_SCL_VERT_FILTER_SCALE_RATIO                                                            0x1145
5987 #define mmDSCL3_SCL_VERT_FILTER_SCALE_RATIO_BASE_IDX                                                   2
5988 #define mmDSCL3_SCL_VERT_FILTER_INIT                                                                   0x1146
5989 #define mmDSCL3_SCL_VERT_FILTER_INIT_BASE_IDX                                                          2
5990 #define mmDSCL3_SCL_VERT_FILTER_INIT_BOT                                                               0x1147
5991 #define mmDSCL3_SCL_VERT_FILTER_INIT_BOT_BASE_IDX                                                      2
5992 #define mmDSCL3_SCL_VERT_FILTER_SCALE_RATIO_C                                                          0x1148
5993 #define mmDSCL3_SCL_VERT_FILTER_SCALE_RATIO_C_BASE_IDX                                                 2
5994 #define mmDSCL3_SCL_VERT_FILTER_INIT_C                                                                 0x1149
5995 #define mmDSCL3_SCL_VERT_FILTER_INIT_C_BASE_IDX                                                        2
5996 #define mmDSCL3_SCL_VERT_FILTER_INIT_BOT_C                                                             0x114a
5997 #define mmDSCL3_SCL_VERT_FILTER_INIT_BOT_C_BASE_IDX                                                    2
5998 #define mmDSCL3_SCL_BLACK_COLOR                                                                        0x114b
5999 #define mmDSCL3_SCL_BLACK_COLOR_BASE_IDX                                                               2
6000 #define mmDSCL3_DSCL_UPDATE                                                                            0x114c
6001 #define mmDSCL3_DSCL_UPDATE_BASE_IDX                                                                   2
6002 #define mmDSCL3_DSCL_AUTOCAL                                                                           0x114d
6003 #define mmDSCL3_DSCL_AUTOCAL_BASE_IDX                                                                  2
6004 #define mmDSCL3_DSCL_EXT_OVERSCAN_LEFT_RIGHT                                                           0x114e
6005 #define mmDSCL3_DSCL_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX                                                  2
6006 #define mmDSCL3_DSCL_EXT_OVERSCAN_TOP_BOTTOM                                                           0x114f
6007 #define mmDSCL3_DSCL_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX                                                  2
6008 #define mmDSCL3_OTG_H_BLANK                                                                            0x1150
6009 #define mmDSCL3_OTG_H_BLANK_BASE_IDX                                                                   2
6010 #define mmDSCL3_OTG_V_BLANK                                                                            0x1151
6011 #define mmDSCL3_OTG_V_BLANK_BASE_IDX                                                                   2
6012 #define mmDSCL3_RECOUT_START                                                                           0x1152
6013 #define mmDSCL3_RECOUT_START_BASE_IDX                                                                  2
6014 #define mmDSCL3_RECOUT_SIZE                                                                            0x1153
6015 #define mmDSCL3_RECOUT_SIZE_BASE_IDX                                                                   2
6016 #define mmDSCL3_MPC_SIZE                                                                               0x1154
6017 #define mmDSCL3_MPC_SIZE_BASE_IDX                                                                      2
6018 #define mmDSCL3_LB_DATA_FORMAT                                                                         0x1155
6019 #define mmDSCL3_LB_DATA_FORMAT_BASE_IDX                                                                2
6020 #define mmDSCL3_LB_MEMORY_CTRL                                                                         0x1156
6021 #define mmDSCL3_LB_MEMORY_CTRL_BASE_IDX                                                                2
6022 #define mmDSCL3_LB_V_COUNTER                                                                           0x1157
6023 #define mmDSCL3_LB_V_COUNTER_BASE_IDX                                                                  2
6024 #define mmDSCL3_DSCL_MEM_PWR_CTRL                                                                      0x1158
6025 #define mmDSCL3_DSCL_MEM_PWR_CTRL_BASE_IDX                                                             2
6026 #define mmDSCL3_DSCL_MEM_PWR_STATUS                                                                    0x1159
6027 #define mmDSCL3_DSCL_MEM_PWR_STATUS_BASE_IDX                                                           2
6028 #define mmDSCL3_OBUF_CONTROL                                                                           0x115a
6029 #define mmDSCL3_OBUF_CONTROL_BASE_IDX                                                                  2
6030 #define mmDSCL3_OBUF_MEM_PWR_CTRL                                                                      0x115b
6031 #define mmDSCL3_OBUF_MEM_PWR_CTRL_BASE_IDX                                                             2
6032 
6033 
6034 // addressBlock: dce_dc_dpp3_dispdec_cm_dispdec
6035 // base address: 0x1104
6036 #define mmCM3_CM_CONTROL                                                                               0x1161
6037 #define mmCM3_CM_CONTROL_BASE_IDX                                                                      2
6038 #define mmCM3_CM_POST_CSC_CONTROL                                                                      0x1162
6039 #define mmCM3_CM_POST_CSC_CONTROL_BASE_IDX                                                             2
6040 #define mmCM3_CM_POST_CSC_C11_C12                                                                      0x1163
6041 #define mmCM3_CM_POST_CSC_C11_C12_BASE_IDX                                                             2
6042 #define mmCM3_CM_POST_CSC_C13_C14                                                                      0x1164
6043 #define mmCM3_CM_POST_CSC_C13_C14_BASE_IDX                                                             2
6044 #define mmCM3_CM_POST_CSC_C21_C22                                                                      0x1165
6045 #define mmCM3_CM_POST_CSC_C21_C22_BASE_IDX                                                             2
6046 #define mmCM3_CM_POST_CSC_C23_C24                                                                      0x1166
6047 #define mmCM3_CM_POST_CSC_C23_C24_BASE_IDX                                                             2
6048 #define mmCM3_CM_POST_CSC_C31_C32                                                                      0x1167
6049 #define mmCM3_CM_POST_CSC_C31_C32_BASE_IDX                                                             2
6050 #define mmCM3_CM_POST_CSC_C33_C34                                                                      0x1168
6051 #define mmCM3_CM_POST_CSC_C33_C34_BASE_IDX                                                             2
6052 #define mmCM3_CM_POST_CSC_B_C11_C12                                                                    0x1169
6053 #define mmCM3_CM_POST_CSC_B_C11_C12_BASE_IDX                                                           2
6054 #define mmCM3_CM_POST_CSC_B_C13_C14                                                                    0x116a
6055 #define mmCM3_CM_POST_CSC_B_C13_C14_BASE_IDX                                                           2
6056 #define mmCM3_CM_POST_CSC_B_C21_C22                                                                    0x116b
6057 #define mmCM3_CM_POST_CSC_B_C21_C22_BASE_IDX                                                           2
6058 #define mmCM3_CM_POST_CSC_B_C23_C24                                                                    0x116c
6059 #define mmCM3_CM_POST_CSC_B_C23_C24_BASE_IDX                                                           2
6060 #define mmCM3_CM_POST_CSC_B_C31_C32                                                                    0x116d
6061 #define mmCM3_CM_POST_CSC_B_C31_C32_BASE_IDX                                                           2
6062 #define mmCM3_CM_POST_CSC_B_C33_C34                                                                    0x116e
6063 #define mmCM3_CM_POST_CSC_B_C33_C34_BASE_IDX                                                           2
6064 #define mmCM3_CM_GAMUT_REMAP_CONTROL                                                                   0x116f
6065 #define mmCM3_CM_GAMUT_REMAP_CONTROL_BASE_IDX                                                          2
6066 #define mmCM3_CM_GAMUT_REMAP_C11_C12                                                                   0x1170
6067 #define mmCM3_CM_GAMUT_REMAP_C11_C12_BASE_IDX                                                          2
6068 #define mmCM3_CM_GAMUT_REMAP_C13_C14                                                                   0x1171
6069 #define mmCM3_CM_GAMUT_REMAP_C13_C14_BASE_IDX                                                          2
6070 #define mmCM3_CM_GAMUT_REMAP_C21_C22                                                                   0x1172
6071 #define mmCM3_CM_GAMUT_REMAP_C21_C22_BASE_IDX                                                          2
6072 #define mmCM3_CM_GAMUT_REMAP_C23_C24                                                                   0x1173
6073 #define mmCM3_CM_GAMUT_REMAP_C23_C24_BASE_IDX                                                          2
6074 #define mmCM3_CM_GAMUT_REMAP_C31_C32                                                                   0x1174
6075 #define mmCM3_CM_GAMUT_REMAP_C31_C32_BASE_IDX                                                          2
6076 #define mmCM3_CM_GAMUT_REMAP_C33_C34                                                                   0x1175
6077 #define mmCM3_CM_GAMUT_REMAP_C33_C34_BASE_IDX                                                          2
6078 #define mmCM3_CM_GAMUT_REMAP_B_C11_C12                                                                 0x1176
6079 #define mmCM3_CM_GAMUT_REMAP_B_C11_C12_BASE_IDX                                                        2
6080 #define mmCM3_CM_GAMUT_REMAP_B_C13_C14                                                                 0x1177
6081 #define mmCM3_CM_GAMUT_REMAP_B_C13_C14_BASE_IDX                                                        2
6082 #define mmCM3_CM_GAMUT_REMAP_B_C21_C22                                                                 0x1178
6083 #define mmCM3_CM_GAMUT_REMAP_B_C21_C22_BASE_IDX                                                        2
6084 #define mmCM3_CM_GAMUT_REMAP_B_C23_C24                                                                 0x1179
6085 #define mmCM3_CM_GAMUT_REMAP_B_C23_C24_BASE_IDX                                                        2
6086 #define mmCM3_CM_GAMUT_REMAP_B_C31_C32                                                                 0x117a
6087 #define mmCM3_CM_GAMUT_REMAP_B_C31_C32_BASE_IDX                                                        2
6088 #define mmCM3_CM_GAMUT_REMAP_B_C33_C34                                                                 0x117b
6089 #define mmCM3_CM_GAMUT_REMAP_B_C33_C34_BASE_IDX                                                        2
6090 #define mmCM3_CM_BIAS_CR_R                                                                             0x117c
6091 #define mmCM3_CM_BIAS_CR_R_BASE_IDX                                                                    2
6092 #define mmCM3_CM_BIAS_Y_G_CB_B                                                                         0x117d
6093 #define mmCM3_CM_BIAS_Y_G_CB_B_BASE_IDX                                                                2
6094 #define mmCM3_CM_GAMCOR_CONTROL                                                                        0x117e
6095 #define mmCM3_CM_GAMCOR_CONTROL_BASE_IDX                                                               2
6096 #define mmCM3_CM_GAMCOR_LUT_INDEX                                                                      0x117f
6097 #define mmCM3_CM_GAMCOR_LUT_INDEX_BASE_IDX                                                             2
6098 #define mmCM3_CM_GAMCOR_LUT_DATA                                                                       0x1180
6099 #define mmCM3_CM_GAMCOR_LUT_DATA_BASE_IDX                                                              2
6100 #define mmCM3_CM_GAMCOR_LUT_CONTROL                                                                    0x1181
6101 #define mmCM3_CM_GAMCOR_LUT_CONTROL_BASE_IDX                                                           2
6102 #define mmCM3_CM_GAMCOR_RAMA_START_CNTL_B                                                              0x1182
6103 #define mmCM3_CM_GAMCOR_RAMA_START_CNTL_B_BASE_IDX                                                     2
6104 #define mmCM3_CM_GAMCOR_RAMA_START_CNTL_G                                                              0x1183
6105 #define mmCM3_CM_GAMCOR_RAMA_START_CNTL_G_BASE_IDX                                                     2
6106 #define mmCM3_CM_GAMCOR_RAMA_START_CNTL_R                                                              0x1184
6107 #define mmCM3_CM_GAMCOR_RAMA_START_CNTL_R_BASE_IDX                                                     2
6108 #define mmCM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B                                                        0x1185
6109 #define mmCM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B_BASE_IDX                                               2
6110 #define mmCM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G                                                        0x1186
6111 #define mmCM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G_BASE_IDX                                               2
6112 #define mmCM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R                                                        0x1187
6113 #define mmCM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R_BASE_IDX                                               2
6114 #define mmCM3_CM_GAMCOR_RAMA_START_BASE_CNTL_B                                                         0x1188
6115 #define mmCM3_CM_GAMCOR_RAMA_START_BASE_CNTL_B_BASE_IDX                                                2
6116 #define mmCM3_CM_GAMCOR_RAMA_START_BASE_CNTL_G                                                         0x1189
6117 #define mmCM3_CM_GAMCOR_RAMA_START_BASE_CNTL_G_BASE_IDX                                                2
6118 #define mmCM3_CM_GAMCOR_RAMA_START_BASE_CNTL_R                                                         0x118a
6119 #define mmCM3_CM_GAMCOR_RAMA_START_BASE_CNTL_R_BASE_IDX                                                2
6120 #define mmCM3_CM_GAMCOR_RAMA_END_CNTL1_B                                                               0x118b
6121 #define mmCM3_CM_GAMCOR_RAMA_END_CNTL1_B_BASE_IDX                                                      2
6122 #define mmCM3_CM_GAMCOR_RAMA_END_CNTL2_B                                                               0x118c
6123 #define mmCM3_CM_GAMCOR_RAMA_END_CNTL2_B_BASE_IDX                                                      2
6124 #define mmCM3_CM_GAMCOR_RAMA_END_CNTL1_G                                                               0x118d
6125 #define mmCM3_CM_GAMCOR_RAMA_END_CNTL1_G_BASE_IDX                                                      2
6126 #define mmCM3_CM_GAMCOR_RAMA_END_CNTL2_G                                                               0x118e
6127 #define mmCM3_CM_GAMCOR_RAMA_END_CNTL2_G_BASE_IDX                                                      2
6128 #define mmCM3_CM_GAMCOR_RAMA_END_CNTL1_R                                                               0x118f
6129 #define mmCM3_CM_GAMCOR_RAMA_END_CNTL1_R_BASE_IDX                                                      2
6130 #define mmCM3_CM_GAMCOR_RAMA_END_CNTL2_R                                                               0x1190
6131 #define mmCM3_CM_GAMCOR_RAMA_END_CNTL2_R_BASE_IDX                                                      2
6132 #define mmCM3_CM_GAMCOR_RAMA_OFFSET_B                                                                  0x1191
6133 #define mmCM3_CM_GAMCOR_RAMA_OFFSET_B_BASE_IDX                                                         2
6134 #define mmCM3_CM_GAMCOR_RAMA_OFFSET_G                                                                  0x1192
6135 #define mmCM3_CM_GAMCOR_RAMA_OFFSET_G_BASE_IDX                                                         2
6136 #define mmCM3_CM_GAMCOR_RAMA_OFFSET_R                                                                  0x1193
6137 #define mmCM3_CM_GAMCOR_RAMA_OFFSET_R_BASE_IDX                                                         2
6138 #define mmCM3_CM_GAMCOR_RAMA_REGION_0_1                                                                0x1194
6139 #define mmCM3_CM_GAMCOR_RAMA_REGION_0_1_BASE_IDX                                                       2
6140 #define mmCM3_CM_GAMCOR_RAMA_REGION_2_3                                                                0x1195
6141 #define mmCM3_CM_GAMCOR_RAMA_REGION_2_3_BASE_IDX                                                       2
6142 #define mmCM3_CM_GAMCOR_RAMA_REGION_4_5                                                                0x1196
6143 #define mmCM3_CM_GAMCOR_RAMA_REGION_4_5_BASE_IDX                                                       2
6144 #define mmCM3_CM_GAMCOR_RAMA_REGION_6_7                                                                0x1197
6145 #define mmCM3_CM_GAMCOR_RAMA_REGION_6_7_BASE_IDX                                                       2
6146 #define mmCM3_CM_GAMCOR_RAMA_REGION_8_9                                                                0x1198
6147 #define mmCM3_CM_GAMCOR_RAMA_REGION_8_9_BASE_IDX                                                       2
6148 #define mmCM3_CM_GAMCOR_RAMA_REGION_10_11                                                              0x1199
6149 #define mmCM3_CM_GAMCOR_RAMA_REGION_10_11_BASE_IDX                                                     2
6150 #define mmCM3_CM_GAMCOR_RAMA_REGION_12_13                                                              0x119a
6151 #define mmCM3_CM_GAMCOR_RAMA_REGION_12_13_BASE_IDX                                                     2
6152 #define mmCM3_CM_GAMCOR_RAMA_REGION_14_15                                                              0x119b
6153 #define mmCM3_CM_GAMCOR_RAMA_REGION_14_15_BASE_IDX                                                     2
6154 #define mmCM3_CM_GAMCOR_RAMA_REGION_16_17                                                              0x119c
6155 #define mmCM3_CM_GAMCOR_RAMA_REGION_16_17_BASE_IDX                                                     2
6156 #define mmCM3_CM_GAMCOR_RAMA_REGION_18_19                                                              0x119d
6157 #define mmCM3_CM_GAMCOR_RAMA_REGION_18_19_BASE_IDX                                                     2
6158 #define mmCM3_CM_GAMCOR_RAMA_REGION_20_21                                                              0x119e
6159 #define mmCM3_CM_GAMCOR_RAMA_REGION_20_21_BASE_IDX                                                     2
6160 #define mmCM3_CM_GAMCOR_RAMA_REGION_22_23                                                              0x119f
6161 #define mmCM3_CM_GAMCOR_RAMA_REGION_22_23_BASE_IDX                                                     2
6162 #define mmCM3_CM_GAMCOR_RAMA_REGION_24_25                                                              0x11a0
6163 #define mmCM3_CM_GAMCOR_RAMA_REGION_24_25_BASE_IDX                                                     2
6164 #define mmCM3_CM_GAMCOR_RAMA_REGION_26_27                                                              0x11a1
6165 #define mmCM3_CM_GAMCOR_RAMA_REGION_26_27_BASE_IDX                                                     2
6166 #define mmCM3_CM_GAMCOR_RAMA_REGION_28_29                                                              0x11a2
6167 #define mmCM3_CM_GAMCOR_RAMA_REGION_28_29_BASE_IDX                                                     2
6168 #define mmCM3_CM_GAMCOR_RAMA_REGION_30_31                                                              0x11a3
6169 #define mmCM3_CM_GAMCOR_RAMA_REGION_30_31_BASE_IDX                                                     2
6170 #define mmCM3_CM_GAMCOR_RAMA_REGION_32_33                                                              0x11a4
6171 #define mmCM3_CM_GAMCOR_RAMA_REGION_32_33_BASE_IDX                                                     2
6172 #define mmCM3_CM_GAMCOR_RAMB_START_CNTL_B                                                              0x11a5
6173 #define mmCM3_CM_GAMCOR_RAMB_START_CNTL_B_BASE_IDX                                                     2
6174 #define mmCM3_CM_GAMCOR_RAMB_START_CNTL_G                                                              0x11a6
6175 #define mmCM3_CM_GAMCOR_RAMB_START_CNTL_G_BASE_IDX                                                     2
6176 #define mmCM3_CM_GAMCOR_RAMB_START_CNTL_R                                                              0x11a7
6177 #define mmCM3_CM_GAMCOR_RAMB_START_CNTL_R_BASE_IDX                                                     2
6178 #define mmCM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B                                                        0x11a8
6179 #define mmCM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B_BASE_IDX                                               2
6180 #define mmCM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G                                                        0x11a9
6181 #define mmCM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G_BASE_IDX                                               2
6182 #define mmCM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R                                                        0x11aa
6183 #define mmCM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R_BASE_IDX                                               2
6184 #define mmCM3_CM_GAMCOR_RAMB_START_BASE_CNTL_B                                                         0x11ab
6185 #define mmCM3_CM_GAMCOR_RAMB_START_BASE_CNTL_B_BASE_IDX                                                2
6186 #define mmCM3_CM_GAMCOR_RAMB_START_BASE_CNTL_G                                                         0x11ac
6187 #define mmCM3_CM_GAMCOR_RAMB_START_BASE_CNTL_G_BASE_IDX                                                2
6188 #define mmCM3_CM_GAMCOR_RAMB_START_BASE_CNTL_R                                                         0x11ad
6189 #define mmCM3_CM_GAMCOR_RAMB_START_BASE_CNTL_R_BASE_IDX                                                2
6190 #define mmCM3_CM_GAMCOR_RAMB_END_CNTL1_B                                                               0x11ae
6191 #define mmCM3_CM_GAMCOR_RAMB_END_CNTL1_B_BASE_IDX                                                      2
6192 #define mmCM3_CM_GAMCOR_RAMB_END_CNTL2_B                                                               0x11af
6193 #define mmCM3_CM_GAMCOR_RAMB_END_CNTL2_B_BASE_IDX                                                      2
6194 #define mmCM3_CM_GAMCOR_RAMB_END_CNTL1_G                                                               0x11b0
6195 #define mmCM3_CM_GAMCOR_RAMB_END_CNTL1_G_BASE_IDX                                                      2
6196 #define mmCM3_CM_GAMCOR_RAMB_END_CNTL2_G                                                               0x11b1
6197 #define mmCM3_CM_GAMCOR_RAMB_END_CNTL2_G_BASE_IDX                                                      2
6198 #define mmCM3_CM_GAMCOR_RAMB_END_CNTL1_R                                                               0x11b2
6199 #define mmCM3_CM_GAMCOR_RAMB_END_CNTL1_R_BASE_IDX                                                      2
6200 #define mmCM3_CM_GAMCOR_RAMB_END_CNTL2_R                                                               0x11b3
6201 #define mmCM3_CM_GAMCOR_RAMB_END_CNTL2_R_BASE_IDX                                                      2
6202 #define mmCM3_CM_GAMCOR_RAMB_OFFSET_B                                                                  0x11b4
6203 #define mmCM3_CM_GAMCOR_RAMB_OFFSET_B_BASE_IDX                                                         2
6204 #define mmCM3_CM_GAMCOR_RAMB_OFFSET_G                                                                  0x11b5
6205 #define mmCM3_CM_GAMCOR_RAMB_OFFSET_G_BASE_IDX                                                         2
6206 #define mmCM3_CM_GAMCOR_RAMB_OFFSET_R                                                                  0x11b6
6207 #define mmCM3_CM_GAMCOR_RAMB_OFFSET_R_BASE_IDX                                                         2
6208 #define mmCM3_CM_GAMCOR_RAMB_REGION_0_1                                                                0x11b7
6209 #define mmCM3_CM_GAMCOR_RAMB_REGION_0_1_BASE_IDX                                                       2
6210 #define mmCM3_CM_GAMCOR_RAMB_REGION_2_3                                                                0x11b8
6211 #define mmCM3_CM_GAMCOR_RAMB_REGION_2_3_BASE_IDX                                                       2
6212 #define mmCM3_CM_GAMCOR_RAMB_REGION_4_5                                                                0x11b9
6213 #define mmCM3_CM_GAMCOR_RAMB_REGION_4_5_BASE_IDX                                                       2
6214 #define mmCM3_CM_GAMCOR_RAMB_REGION_6_7                                                                0x11ba
6215 #define mmCM3_CM_GAMCOR_RAMB_REGION_6_7_BASE_IDX                                                       2
6216 #define mmCM3_CM_GAMCOR_RAMB_REGION_8_9                                                                0x11bb
6217 #define mmCM3_CM_GAMCOR_RAMB_REGION_8_9_BASE_IDX                                                       2
6218 #define mmCM3_CM_GAMCOR_RAMB_REGION_10_11                                                              0x11bc
6219 #define mmCM3_CM_GAMCOR_RAMB_REGION_10_11_BASE_IDX                                                     2
6220 #define mmCM3_CM_GAMCOR_RAMB_REGION_12_13                                                              0x11bd
6221 #define mmCM3_CM_GAMCOR_RAMB_REGION_12_13_BASE_IDX                                                     2
6222 #define mmCM3_CM_GAMCOR_RAMB_REGION_14_15                                                              0x11be
6223 #define mmCM3_CM_GAMCOR_RAMB_REGION_14_15_BASE_IDX                                                     2
6224 #define mmCM3_CM_GAMCOR_RAMB_REGION_16_17                                                              0x11bf
6225 #define mmCM3_CM_GAMCOR_RAMB_REGION_16_17_BASE_IDX                                                     2
6226 #define mmCM3_CM_GAMCOR_RAMB_REGION_18_19                                                              0x11c0
6227 #define mmCM3_CM_GAMCOR_RAMB_REGION_18_19_BASE_IDX                                                     2
6228 #define mmCM3_CM_GAMCOR_RAMB_REGION_20_21                                                              0x11c1
6229 #define mmCM3_CM_GAMCOR_RAMB_REGION_20_21_BASE_IDX                                                     2
6230 #define mmCM3_CM_GAMCOR_RAMB_REGION_22_23                                                              0x11c2
6231 #define mmCM3_CM_GAMCOR_RAMB_REGION_22_23_BASE_IDX                                                     2
6232 #define mmCM3_CM_GAMCOR_RAMB_REGION_24_25                                                              0x11c3
6233 #define mmCM3_CM_GAMCOR_RAMB_REGION_24_25_BASE_IDX                                                     2
6234 #define mmCM3_CM_GAMCOR_RAMB_REGION_26_27                                                              0x11c4
6235 #define mmCM3_CM_GAMCOR_RAMB_REGION_26_27_BASE_IDX                                                     2
6236 #define mmCM3_CM_GAMCOR_RAMB_REGION_28_29                                                              0x11c5
6237 #define mmCM3_CM_GAMCOR_RAMB_REGION_28_29_BASE_IDX                                                     2
6238 #define mmCM3_CM_GAMCOR_RAMB_REGION_30_31                                                              0x11c6
6239 #define mmCM3_CM_GAMCOR_RAMB_REGION_30_31_BASE_IDX                                                     2
6240 #define mmCM3_CM_GAMCOR_RAMB_REGION_32_33                                                              0x11c7
6241 #define mmCM3_CM_GAMCOR_RAMB_REGION_32_33_BASE_IDX                                                     2
6242 #define mmCM3_CM_BLNDGAM_CONTROL                                                                       0x11c8
6243 #define mmCM3_CM_BLNDGAM_CONTROL_BASE_IDX                                                              2
6244 #define mmCM3_CM_BLNDGAM_LUT_INDEX                                                                     0x11c9
6245 #define mmCM3_CM_BLNDGAM_LUT_INDEX_BASE_IDX                                                            2
6246 #define mmCM3_CM_BLNDGAM_LUT_DATA                                                                      0x11ca
6247 #define mmCM3_CM_BLNDGAM_LUT_DATA_BASE_IDX                                                             2
6248 #define mmCM3_CM_BLNDGAM_LUT_CONTROL                                                                   0x11cb
6249 #define mmCM3_CM_BLNDGAM_LUT_CONTROL_BASE_IDX                                                          2
6250 #define mmCM3_CM_BLNDGAM_RAMA_START_CNTL_B                                                             0x11cc
6251 #define mmCM3_CM_BLNDGAM_RAMA_START_CNTL_B_BASE_IDX                                                    2
6252 #define mmCM3_CM_BLNDGAM_RAMA_START_CNTL_G                                                             0x11cd
6253 #define mmCM3_CM_BLNDGAM_RAMA_START_CNTL_G_BASE_IDX                                                    2
6254 #define mmCM3_CM_BLNDGAM_RAMA_START_CNTL_R                                                             0x11ce
6255 #define mmCM3_CM_BLNDGAM_RAMA_START_CNTL_R_BASE_IDX                                                    2
6256 #define mmCM3_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_B                                                       0x11cf
6257 #define mmCM3_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_B_BASE_IDX                                              2
6258 #define mmCM3_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_G                                                       0x11d0
6259 #define mmCM3_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_G_BASE_IDX                                              2
6260 #define mmCM3_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_R                                                       0x11d1
6261 #define mmCM3_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_R_BASE_IDX                                              2
6262 #define mmCM3_CM_BLNDGAM_RAMA_START_BASE_CNTL_B                                                        0x11d2
6263 #define mmCM3_CM_BLNDGAM_RAMA_START_BASE_CNTL_B_BASE_IDX                                               2
6264 #define mmCM3_CM_BLNDGAM_RAMA_START_BASE_CNTL_G                                                        0x11d3
6265 #define mmCM3_CM_BLNDGAM_RAMA_START_BASE_CNTL_G_BASE_IDX                                               2
6266 #define mmCM3_CM_BLNDGAM_RAMA_START_BASE_CNTL_R                                                        0x11d4
6267 #define mmCM3_CM_BLNDGAM_RAMA_START_BASE_CNTL_R_BASE_IDX                                               2
6268 #define mmCM3_CM_BLNDGAM_RAMA_END_CNTL1_B                                                              0x11d5
6269 #define mmCM3_CM_BLNDGAM_RAMA_END_CNTL1_B_BASE_IDX                                                     2
6270 #define mmCM3_CM_BLNDGAM_RAMA_END_CNTL2_B                                                              0x11d6
6271 #define mmCM3_CM_BLNDGAM_RAMA_END_CNTL2_B_BASE_IDX                                                     2
6272 #define mmCM3_CM_BLNDGAM_RAMA_END_CNTL1_G                                                              0x11d7
6273 #define mmCM3_CM_BLNDGAM_RAMA_END_CNTL1_G_BASE_IDX                                                     2
6274 #define mmCM3_CM_BLNDGAM_RAMA_END_CNTL2_G                                                              0x11d8
6275 #define mmCM3_CM_BLNDGAM_RAMA_END_CNTL2_G_BASE_IDX                                                     2
6276 #define mmCM3_CM_BLNDGAM_RAMA_END_CNTL1_R                                                              0x11d9
6277 #define mmCM3_CM_BLNDGAM_RAMA_END_CNTL1_R_BASE_IDX                                                     2
6278 #define mmCM3_CM_BLNDGAM_RAMA_END_CNTL2_R                                                              0x11da
6279 #define mmCM3_CM_BLNDGAM_RAMA_END_CNTL2_R_BASE_IDX                                                     2
6280 #define mmCM3_CM_BLNDGAM_RAMA_OFFSET_B                                                                 0x11db
6281 #define mmCM3_CM_BLNDGAM_RAMA_OFFSET_B_BASE_IDX                                                        2
6282 #define mmCM3_CM_BLNDGAM_RAMA_OFFSET_G                                                                 0x11dc
6283 #define mmCM3_CM_BLNDGAM_RAMA_OFFSET_G_BASE_IDX                                                        2
6284 #define mmCM3_CM_BLNDGAM_RAMA_OFFSET_R                                                                 0x11dd
6285 #define mmCM3_CM_BLNDGAM_RAMA_OFFSET_R_BASE_IDX                                                        2
6286 #define mmCM3_CM_BLNDGAM_RAMA_REGION_0_1                                                               0x11de
6287 #define mmCM3_CM_BLNDGAM_RAMA_REGION_0_1_BASE_IDX                                                      2
6288 #define mmCM3_CM_BLNDGAM_RAMA_REGION_2_3                                                               0x11df
6289 #define mmCM3_CM_BLNDGAM_RAMA_REGION_2_3_BASE_IDX                                                      2
6290 #define mmCM3_CM_BLNDGAM_RAMA_REGION_4_5                                                               0x11e0
6291 #define mmCM3_CM_BLNDGAM_RAMA_REGION_4_5_BASE_IDX                                                      2
6292 #define mmCM3_CM_BLNDGAM_RAMA_REGION_6_7                                                               0x11e1
6293 #define mmCM3_CM_BLNDGAM_RAMA_REGION_6_7_BASE_IDX                                                      2
6294 #define mmCM3_CM_BLNDGAM_RAMA_REGION_8_9                                                               0x11e2
6295 #define mmCM3_CM_BLNDGAM_RAMA_REGION_8_9_BASE_IDX                                                      2
6296 #define mmCM3_CM_BLNDGAM_RAMA_REGION_10_11                                                             0x11e3
6297 #define mmCM3_CM_BLNDGAM_RAMA_REGION_10_11_BASE_IDX                                                    2
6298 #define mmCM3_CM_BLNDGAM_RAMA_REGION_12_13                                                             0x11e4
6299 #define mmCM3_CM_BLNDGAM_RAMA_REGION_12_13_BASE_IDX                                                    2
6300 #define mmCM3_CM_BLNDGAM_RAMA_REGION_14_15                                                             0x11e5
6301 #define mmCM3_CM_BLNDGAM_RAMA_REGION_14_15_BASE_IDX                                                    2
6302 #define mmCM3_CM_BLNDGAM_RAMA_REGION_16_17                                                             0x11e6
6303 #define mmCM3_CM_BLNDGAM_RAMA_REGION_16_17_BASE_IDX                                                    2
6304 #define mmCM3_CM_BLNDGAM_RAMA_REGION_18_19                                                             0x11e7
6305 #define mmCM3_CM_BLNDGAM_RAMA_REGION_18_19_BASE_IDX                                                    2
6306 #define mmCM3_CM_BLNDGAM_RAMA_REGION_20_21                                                             0x11e8
6307 #define mmCM3_CM_BLNDGAM_RAMA_REGION_20_21_BASE_IDX                                                    2
6308 #define mmCM3_CM_BLNDGAM_RAMA_REGION_22_23                                                             0x11e9
6309 #define mmCM3_CM_BLNDGAM_RAMA_REGION_22_23_BASE_IDX                                                    2
6310 #define mmCM3_CM_BLNDGAM_RAMA_REGION_24_25                                                             0x11ea
6311 #define mmCM3_CM_BLNDGAM_RAMA_REGION_24_25_BASE_IDX                                                    2
6312 #define mmCM3_CM_BLNDGAM_RAMA_REGION_26_27                                                             0x11eb
6313 #define mmCM3_CM_BLNDGAM_RAMA_REGION_26_27_BASE_IDX                                                    2
6314 #define mmCM3_CM_BLNDGAM_RAMA_REGION_28_29                                                             0x11ec
6315 #define mmCM3_CM_BLNDGAM_RAMA_REGION_28_29_BASE_IDX                                                    2
6316 #define mmCM3_CM_BLNDGAM_RAMA_REGION_30_31                                                             0x11ed
6317 #define mmCM3_CM_BLNDGAM_RAMA_REGION_30_31_BASE_IDX                                                    2
6318 #define mmCM3_CM_BLNDGAM_RAMA_REGION_32_33                                                             0x11ee
6319 #define mmCM3_CM_BLNDGAM_RAMA_REGION_32_33_BASE_IDX                                                    2
6320 #define mmCM3_CM_BLNDGAM_RAMB_START_CNTL_B                                                             0x11ef
6321 #define mmCM3_CM_BLNDGAM_RAMB_START_CNTL_B_BASE_IDX                                                    2
6322 #define mmCM3_CM_BLNDGAM_RAMB_START_CNTL_G                                                             0x11f0
6323 #define mmCM3_CM_BLNDGAM_RAMB_START_CNTL_G_BASE_IDX                                                    2
6324 #define mmCM3_CM_BLNDGAM_RAMB_START_CNTL_R                                                             0x11f1
6325 #define mmCM3_CM_BLNDGAM_RAMB_START_CNTL_R_BASE_IDX                                                    2
6326 #define mmCM3_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_B                                                       0x11f2
6327 #define mmCM3_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_B_BASE_IDX                                              2
6328 #define mmCM3_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_G                                                       0x11f3
6329 #define mmCM3_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_G_BASE_IDX                                              2
6330 #define mmCM3_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_R                                                       0x11f4
6331 #define mmCM3_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_R_BASE_IDX                                              2
6332 #define mmCM3_CM_BLNDGAM_RAMB_START_BASE_CNTL_B                                                        0x11f5
6333 #define mmCM3_CM_BLNDGAM_RAMB_START_BASE_CNTL_B_BASE_IDX                                               2
6334 #define mmCM3_CM_BLNDGAM_RAMB_START_BASE_CNTL_G                                                        0x11f6
6335 #define mmCM3_CM_BLNDGAM_RAMB_START_BASE_CNTL_G_BASE_IDX                                               2
6336 #define mmCM3_CM_BLNDGAM_RAMB_START_BASE_CNTL_R                                                        0x11f7
6337 #define mmCM3_CM_BLNDGAM_RAMB_START_BASE_CNTL_R_BASE_IDX                                               2
6338 #define mmCM3_CM_BLNDGAM_RAMB_END_CNTL1_B                                                              0x11f8
6339 #define mmCM3_CM_BLNDGAM_RAMB_END_CNTL1_B_BASE_IDX                                                     2
6340 #define mmCM3_CM_BLNDGAM_RAMB_END_CNTL2_B                                                              0x11f9
6341 #define mmCM3_CM_BLNDGAM_RAMB_END_CNTL2_B_BASE_IDX                                                     2
6342 #define mmCM3_CM_BLNDGAM_RAMB_END_CNTL1_G                                                              0x11fa
6343 #define mmCM3_CM_BLNDGAM_RAMB_END_CNTL1_G_BASE_IDX                                                     2
6344 #define mmCM3_CM_BLNDGAM_RAMB_END_CNTL2_G                                                              0x11fb
6345 #define mmCM3_CM_BLNDGAM_RAMB_END_CNTL2_G_BASE_IDX                                                     2
6346 #define mmCM3_CM_BLNDGAM_RAMB_END_CNTL1_R                                                              0x11fc
6347 #define mmCM3_CM_BLNDGAM_RAMB_END_CNTL1_R_BASE_IDX                                                     2
6348 #define mmCM3_CM_BLNDGAM_RAMB_END_CNTL2_R                                                              0x11fd
6349 #define mmCM3_CM_BLNDGAM_RAMB_END_CNTL2_R_BASE_IDX                                                     2
6350 #define mmCM3_CM_BLNDGAM_RAMB_OFFSET_B                                                                 0x11fe
6351 #define mmCM3_CM_BLNDGAM_RAMB_OFFSET_B_BASE_IDX                                                        2
6352 #define mmCM3_CM_BLNDGAM_RAMB_OFFSET_G                                                                 0x11ff
6353 #define mmCM3_CM_BLNDGAM_RAMB_OFFSET_G_BASE_IDX                                                        2
6354 #define mmCM3_CM_BLNDGAM_RAMB_OFFSET_R                                                                 0x1200
6355 #define mmCM3_CM_BLNDGAM_RAMB_OFFSET_R_BASE_IDX                                                        2
6356 #define mmCM3_CM_BLNDGAM_RAMB_REGION_0_1                                                               0x1201
6357 #define mmCM3_CM_BLNDGAM_RAMB_REGION_0_1_BASE_IDX                                                      2
6358 #define mmCM3_CM_BLNDGAM_RAMB_REGION_2_3                                                               0x1202
6359 #define mmCM3_CM_BLNDGAM_RAMB_REGION_2_3_BASE_IDX                                                      2
6360 #define mmCM3_CM_BLNDGAM_RAMB_REGION_4_5                                                               0x1203
6361 #define mmCM3_CM_BLNDGAM_RAMB_REGION_4_5_BASE_IDX                                                      2
6362 #define mmCM3_CM_BLNDGAM_RAMB_REGION_6_7                                                               0x1204
6363 #define mmCM3_CM_BLNDGAM_RAMB_REGION_6_7_BASE_IDX                                                      2
6364 #define mmCM3_CM_BLNDGAM_RAMB_REGION_8_9                                                               0x1205
6365 #define mmCM3_CM_BLNDGAM_RAMB_REGION_8_9_BASE_IDX                                                      2
6366 #define mmCM3_CM_BLNDGAM_RAMB_REGION_10_11                                                             0x1206
6367 #define mmCM3_CM_BLNDGAM_RAMB_REGION_10_11_BASE_IDX                                                    2
6368 #define mmCM3_CM_BLNDGAM_RAMB_REGION_12_13                                                             0x1207
6369 #define mmCM3_CM_BLNDGAM_RAMB_REGION_12_13_BASE_IDX                                                    2
6370 #define mmCM3_CM_BLNDGAM_RAMB_REGION_14_15                                                             0x1208
6371 #define mmCM3_CM_BLNDGAM_RAMB_REGION_14_15_BASE_IDX                                                    2
6372 #define mmCM3_CM_BLNDGAM_RAMB_REGION_16_17                                                             0x1209
6373 #define mmCM3_CM_BLNDGAM_RAMB_REGION_16_17_BASE_IDX                                                    2
6374 #define mmCM3_CM_BLNDGAM_RAMB_REGION_18_19                                                             0x120a
6375 #define mmCM3_CM_BLNDGAM_RAMB_REGION_18_19_BASE_IDX                                                    2
6376 #define mmCM3_CM_BLNDGAM_RAMB_REGION_20_21                                                             0x120b
6377 #define mmCM3_CM_BLNDGAM_RAMB_REGION_20_21_BASE_IDX                                                    2
6378 #define mmCM3_CM_BLNDGAM_RAMB_REGION_22_23                                                             0x120c
6379 #define mmCM3_CM_BLNDGAM_RAMB_REGION_22_23_BASE_IDX                                                    2
6380 #define mmCM3_CM_BLNDGAM_RAMB_REGION_24_25                                                             0x120d
6381 #define mmCM3_CM_BLNDGAM_RAMB_REGION_24_25_BASE_IDX                                                    2
6382 #define mmCM3_CM_BLNDGAM_RAMB_REGION_26_27                                                             0x120e
6383 #define mmCM3_CM_BLNDGAM_RAMB_REGION_26_27_BASE_IDX                                                    2
6384 #define mmCM3_CM_BLNDGAM_RAMB_REGION_28_29                                                             0x120f
6385 #define mmCM3_CM_BLNDGAM_RAMB_REGION_28_29_BASE_IDX                                                    2
6386 #define mmCM3_CM_BLNDGAM_RAMB_REGION_30_31                                                             0x1210
6387 #define mmCM3_CM_BLNDGAM_RAMB_REGION_30_31_BASE_IDX                                                    2
6388 #define mmCM3_CM_BLNDGAM_RAMB_REGION_32_33                                                             0x1211
6389 #define mmCM3_CM_BLNDGAM_RAMB_REGION_32_33_BASE_IDX                                                    2
6390 #define mmCM3_CM_HDR_MULT_COEF                                                                         0x1212
6391 #define mmCM3_CM_HDR_MULT_COEF_BASE_IDX                                                                2
6392 #define mmCM3_CM_MEM_PWR_CTRL                                                                          0x1213
6393 #define mmCM3_CM_MEM_PWR_CTRL_BASE_IDX                                                                 2
6394 #define mmCM3_CM_MEM_PWR_STATUS                                                                        0x1214
6395 #define mmCM3_CM_MEM_PWR_STATUS_BASE_IDX                                                               2
6396 #define mmCM3_CM_DEALPHA                                                                               0x1216
6397 #define mmCM3_CM_DEALPHA_BASE_IDX                                                                      2
6398 #define mmCM3_CM_COEF_FORMAT                                                                           0x1217
6399 #define mmCM3_CM_COEF_FORMAT_BASE_IDX                                                                  2
6400 #define mmCM3_CM_SHAPER_CONTROL                                                                        0x1218
6401 #define mmCM3_CM_SHAPER_CONTROL_BASE_IDX                                                               2
6402 #define mmCM3_CM_SHAPER_OFFSET_R                                                                       0x1219
6403 #define mmCM3_CM_SHAPER_OFFSET_R_BASE_IDX                                                              2
6404 #define mmCM3_CM_SHAPER_OFFSET_G                                                                       0x121a
6405 #define mmCM3_CM_SHAPER_OFFSET_G_BASE_IDX                                                              2
6406 #define mmCM3_CM_SHAPER_OFFSET_B                                                                       0x121b
6407 #define mmCM3_CM_SHAPER_OFFSET_B_BASE_IDX                                                              2
6408 #define mmCM3_CM_SHAPER_SCALE_R                                                                        0x121c
6409 #define mmCM3_CM_SHAPER_SCALE_R_BASE_IDX                                                               2
6410 #define mmCM3_CM_SHAPER_SCALE_G_B                                                                      0x121d
6411 #define mmCM3_CM_SHAPER_SCALE_G_B_BASE_IDX                                                             2
6412 #define mmCM3_CM_SHAPER_LUT_INDEX                                                                      0x121e
6413 #define mmCM3_CM_SHAPER_LUT_INDEX_BASE_IDX                                                             2
6414 #define mmCM3_CM_SHAPER_LUT_DATA                                                                       0x121f
6415 #define mmCM3_CM_SHAPER_LUT_DATA_BASE_IDX                                                              2
6416 #define mmCM3_CM_SHAPER_LUT_WRITE_EN_MASK                                                              0x1220
6417 #define mmCM3_CM_SHAPER_LUT_WRITE_EN_MASK_BASE_IDX                                                     2
6418 #define mmCM3_CM_SHAPER_RAMA_START_CNTL_B                                                              0x1221
6419 #define mmCM3_CM_SHAPER_RAMA_START_CNTL_B_BASE_IDX                                                     2
6420 #define mmCM3_CM_SHAPER_RAMA_START_CNTL_G                                                              0x1222
6421 #define mmCM3_CM_SHAPER_RAMA_START_CNTL_G_BASE_IDX                                                     2
6422 #define mmCM3_CM_SHAPER_RAMA_START_CNTL_R                                                              0x1223
6423 #define mmCM3_CM_SHAPER_RAMA_START_CNTL_R_BASE_IDX                                                     2
6424 #define mmCM3_CM_SHAPER_RAMA_END_CNTL_B                                                                0x1224
6425 #define mmCM3_CM_SHAPER_RAMA_END_CNTL_B_BASE_IDX                                                       2
6426 #define mmCM3_CM_SHAPER_RAMA_END_CNTL_G                                                                0x1225
6427 #define mmCM3_CM_SHAPER_RAMA_END_CNTL_G_BASE_IDX                                                       2
6428 #define mmCM3_CM_SHAPER_RAMA_END_CNTL_R                                                                0x1226
6429 #define mmCM3_CM_SHAPER_RAMA_END_CNTL_R_BASE_IDX                                                       2
6430 #define mmCM3_CM_SHAPER_RAMA_REGION_0_1                                                                0x1227
6431 #define mmCM3_CM_SHAPER_RAMA_REGION_0_1_BASE_IDX                                                       2
6432 #define mmCM3_CM_SHAPER_RAMA_REGION_2_3                                                                0x1228
6433 #define mmCM3_CM_SHAPER_RAMA_REGION_2_3_BASE_IDX                                                       2
6434 #define mmCM3_CM_SHAPER_RAMA_REGION_4_5                                                                0x1229
6435 #define mmCM3_CM_SHAPER_RAMA_REGION_4_5_BASE_IDX                                                       2
6436 #define mmCM3_CM_SHAPER_RAMA_REGION_6_7                                                                0x122a
6437 #define mmCM3_CM_SHAPER_RAMA_REGION_6_7_BASE_IDX                                                       2
6438 #define mmCM3_CM_SHAPER_RAMA_REGION_8_9                                                                0x122b
6439 #define mmCM3_CM_SHAPER_RAMA_REGION_8_9_BASE_IDX                                                       2
6440 #define mmCM3_CM_SHAPER_RAMA_REGION_10_11                                                              0x122c
6441 #define mmCM3_CM_SHAPER_RAMA_REGION_10_11_BASE_IDX                                                     2
6442 #define mmCM3_CM_SHAPER_RAMA_REGION_12_13                                                              0x122d
6443 #define mmCM3_CM_SHAPER_RAMA_REGION_12_13_BASE_IDX                                                     2
6444 #define mmCM3_CM_SHAPER_RAMA_REGION_14_15                                                              0x122e
6445 #define mmCM3_CM_SHAPER_RAMA_REGION_14_15_BASE_IDX                                                     2
6446 #define mmCM3_CM_SHAPER_RAMA_REGION_16_17                                                              0x122f
6447 #define mmCM3_CM_SHAPER_RAMA_REGION_16_17_BASE_IDX                                                     2
6448 #define mmCM3_CM_SHAPER_RAMA_REGION_18_19                                                              0x1230
6449 #define mmCM3_CM_SHAPER_RAMA_REGION_18_19_BASE_IDX                                                     2
6450 #define mmCM3_CM_SHAPER_RAMA_REGION_20_21                                                              0x1231
6451 #define mmCM3_CM_SHAPER_RAMA_REGION_20_21_BASE_IDX                                                     2
6452 #define mmCM3_CM_SHAPER_RAMA_REGION_22_23                                                              0x1232
6453 #define mmCM3_CM_SHAPER_RAMA_REGION_22_23_BASE_IDX                                                     2
6454 #define mmCM3_CM_SHAPER_RAMA_REGION_24_25                                                              0x1233
6455 #define mmCM3_CM_SHAPER_RAMA_REGION_24_25_BASE_IDX                                                     2
6456 #define mmCM3_CM_SHAPER_RAMA_REGION_26_27                                                              0x1234
6457 #define mmCM3_CM_SHAPER_RAMA_REGION_26_27_BASE_IDX                                                     2
6458 #define mmCM3_CM_SHAPER_RAMA_REGION_28_29                                                              0x1235
6459 #define mmCM3_CM_SHAPER_RAMA_REGION_28_29_BASE_IDX                                                     2
6460 #define mmCM3_CM_SHAPER_RAMA_REGION_30_31                                                              0x1236
6461 #define mmCM3_CM_SHAPER_RAMA_REGION_30_31_BASE_IDX                                                     2
6462 #define mmCM3_CM_SHAPER_RAMA_REGION_32_33                                                              0x1237
6463 #define mmCM3_CM_SHAPER_RAMA_REGION_32_33_BASE_IDX                                                     2
6464 #define mmCM3_CM_SHAPER_RAMB_START_CNTL_B                                                              0x1238
6465 #define mmCM3_CM_SHAPER_RAMB_START_CNTL_B_BASE_IDX                                                     2
6466 #define mmCM3_CM_SHAPER_RAMB_START_CNTL_G                                                              0x1239
6467 #define mmCM3_CM_SHAPER_RAMB_START_CNTL_G_BASE_IDX                                                     2
6468 #define mmCM3_CM_SHAPER_RAMB_START_CNTL_R                                                              0x123a
6469 #define mmCM3_CM_SHAPER_RAMB_START_CNTL_R_BASE_IDX                                                     2
6470 #define mmCM3_CM_SHAPER_RAMB_END_CNTL_B                                                                0x123b
6471 #define mmCM3_CM_SHAPER_RAMB_END_CNTL_B_BASE_IDX                                                       2
6472 #define mmCM3_CM_SHAPER_RAMB_END_CNTL_G                                                                0x123c
6473 #define mmCM3_CM_SHAPER_RAMB_END_CNTL_G_BASE_IDX                                                       2
6474 #define mmCM3_CM_SHAPER_RAMB_END_CNTL_R                                                                0x123d
6475 #define mmCM3_CM_SHAPER_RAMB_END_CNTL_R_BASE_IDX                                                       2
6476 #define mmCM3_CM_SHAPER_RAMB_REGION_0_1                                                                0x123e
6477 #define mmCM3_CM_SHAPER_RAMB_REGION_0_1_BASE_IDX                                                       2
6478 #define mmCM3_CM_SHAPER_RAMB_REGION_2_3                                                                0x123f
6479 #define mmCM3_CM_SHAPER_RAMB_REGION_2_3_BASE_IDX                                                       2
6480 #define mmCM3_CM_SHAPER_RAMB_REGION_4_5                                                                0x1240
6481 #define mmCM3_CM_SHAPER_RAMB_REGION_4_5_BASE_IDX                                                       2
6482 #define mmCM3_CM_SHAPER_RAMB_REGION_6_7                                                                0x1241
6483 #define mmCM3_CM_SHAPER_RAMB_REGION_6_7_BASE_IDX                                                       2
6484 #define mmCM3_CM_SHAPER_RAMB_REGION_8_9                                                                0x1242
6485 #define mmCM3_CM_SHAPER_RAMB_REGION_8_9_BASE_IDX                                                       2
6486 #define mmCM3_CM_SHAPER_RAMB_REGION_10_11                                                              0x1243
6487 #define mmCM3_CM_SHAPER_RAMB_REGION_10_11_BASE_IDX                                                     2
6488 #define mmCM3_CM_SHAPER_RAMB_REGION_12_13                                                              0x1244
6489 #define mmCM3_CM_SHAPER_RAMB_REGION_12_13_BASE_IDX                                                     2
6490 #define mmCM3_CM_SHAPER_RAMB_REGION_14_15                                                              0x1245
6491 #define mmCM3_CM_SHAPER_RAMB_REGION_14_15_BASE_IDX                                                     2
6492 #define mmCM3_CM_SHAPER_RAMB_REGION_16_17                                                              0x1246
6493 #define mmCM3_CM_SHAPER_RAMB_REGION_16_17_BASE_IDX                                                     2
6494 #define mmCM3_CM_SHAPER_RAMB_REGION_18_19                                                              0x1247
6495 #define mmCM3_CM_SHAPER_RAMB_REGION_18_19_BASE_IDX                                                     2
6496 #define mmCM3_CM_SHAPER_RAMB_REGION_20_21                                                              0x1248
6497 #define mmCM3_CM_SHAPER_RAMB_REGION_20_21_BASE_IDX                                                     2
6498 #define mmCM3_CM_SHAPER_RAMB_REGION_22_23                                                              0x1249
6499 #define mmCM3_CM_SHAPER_RAMB_REGION_22_23_BASE_IDX                                                     2
6500 #define mmCM3_CM_SHAPER_RAMB_REGION_24_25                                                              0x124a
6501 #define mmCM3_CM_SHAPER_RAMB_REGION_24_25_BASE_IDX                                                     2
6502 #define mmCM3_CM_SHAPER_RAMB_REGION_26_27                                                              0x124b
6503 #define mmCM3_CM_SHAPER_RAMB_REGION_26_27_BASE_IDX                                                     2
6504 #define mmCM3_CM_SHAPER_RAMB_REGION_28_29                                                              0x124c
6505 #define mmCM3_CM_SHAPER_RAMB_REGION_28_29_BASE_IDX                                                     2
6506 #define mmCM3_CM_SHAPER_RAMB_REGION_30_31                                                              0x124d
6507 #define mmCM3_CM_SHAPER_RAMB_REGION_30_31_BASE_IDX                                                     2
6508 #define mmCM3_CM_SHAPER_RAMB_REGION_32_33                                                              0x124e
6509 #define mmCM3_CM_SHAPER_RAMB_REGION_32_33_BASE_IDX                                                     2
6510 #define mmCM3_CM_MEM_PWR_CTRL2                                                                         0x124f
6511 #define mmCM3_CM_MEM_PWR_CTRL2_BASE_IDX                                                                2
6512 #define mmCM3_CM_MEM_PWR_STATUS2                                                                       0x1250
6513 #define mmCM3_CM_MEM_PWR_STATUS2_BASE_IDX                                                              2
6514 #define mmCM3_CM_3DLUT_MODE                                                                            0x1251
6515 #define mmCM3_CM_3DLUT_MODE_BASE_IDX                                                                   2
6516 #define mmCM3_CM_3DLUT_INDEX                                                                           0x1252
6517 #define mmCM3_CM_3DLUT_INDEX_BASE_IDX                                                                  2
6518 #define mmCM3_CM_3DLUT_DATA                                                                            0x1253
6519 #define mmCM3_CM_3DLUT_DATA_BASE_IDX                                                                   2
6520 #define mmCM3_CM_3DLUT_DATA_30BIT                                                                      0x1254
6521 #define mmCM3_CM_3DLUT_DATA_30BIT_BASE_IDX                                                             2
6522 #define mmCM3_CM_3DLUT_READ_WRITE_CONTROL                                                              0x1255
6523 #define mmCM3_CM_3DLUT_READ_WRITE_CONTROL_BASE_IDX                                                     2
6524 #define mmCM3_CM_3DLUT_OUT_NORM_FACTOR                                                                 0x1256
6525 #define mmCM3_CM_3DLUT_OUT_NORM_FACTOR_BASE_IDX                                                        2
6526 #define mmCM3_CM_3DLUT_OUT_OFFSET_R                                                                    0x1257
6527 #define mmCM3_CM_3DLUT_OUT_OFFSET_R_BASE_IDX                                                           2
6528 #define mmCM3_CM_3DLUT_OUT_OFFSET_G                                                                    0x1258
6529 #define mmCM3_CM_3DLUT_OUT_OFFSET_G_BASE_IDX                                                           2
6530 #define mmCM3_CM_3DLUT_OUT_OFFSET_B                                                                    0x1259
6531 #define mmCM3_CM_3DLUT_OUT_OFFSET_B_BASE_IDX                                                           2
6532 
6533 
6534 // addressBlock: dce_dc_dpp3_dispdec_dpp_dcperfmon_dc_perfmon_dispdec
6535 // base address: 0x4994
6536 #define mmDC_PERFMON14_PERFCOUNTER_CNTL                                                                0x1265
6537 #define mmDC_PERFMON14_PERFCOUNTER_CNTL_BASE_IDX                                                       2
6538 #define mmDC_PERFMON14_PERFCOUNTER_CNTL2                                                               0x1266
6539 #define mmDC_PERFMON14_PERFCOUNTER_CNTL2_BASE_IDX                                                      2
6540 #define mmDC_PERFMON14_PERFCOUNTER_STATE                                                               0x1267
6541 #define mmDC_PERFMON14_PERFCOUNTER_STATE_BASE_IDX                                                      2
6542 #define mmDC_PERFMON14_PERFMON_CNTL                                                                    0x1268
6543 #define mmDC_PERFMON14_PERFMON_CNTL_BASE_IDX                                                           2
6544 #define mmDC_PERFMON14_PERFMON_CNTL2                                                                   0x1269
6545 #define mmDC_PERFMON14_PERFMON_CNTL2_BASE_IDX                                                          2
6546 #define mmDC_PERFMON14_PERFMON_CVALUE_INT_MISC                                                         0x126a
6547 #define mmDC_PERFMON14_PERFMON_CVALUE_INT_MISC_BASE_IDX                                                2
6548 #define mmDC_PERFMON14_PERFMON_CVALUE_LOW                                                              0x126b
6549 #define mmDC_PERFMON14_PERFMON_CVALUE_LOW_BASE_IDX                                                     2
6550 #define mmDC_PERFMON14_PERFMON_HI                                                                      0x126c
6551 #define mmDC_PERFMON14_PERFMON_HI_BASE_IDX                                                             2
6552 #define mmDC_PERFMON14_PERFMON_LOW                                                                     0x126d
6553 #define mmDC_PERFMON14_PERFMON_LOW_BASE_IDX                                                            2
6554 
6555 
6556 // addressBlock: dce_dc_dpp4_dispdec_dpp_top_dispdec
6557 // base address: 0x16b0
6558 #define mmDPP_TOP4_DPP_CONTROL                                                                         0x1271
6559 #define mmDPP_TOP4_DPP_CONTROL_BASE_IDX                                                                2
6560 #define mmDPP_TOP4_DPP_SOFT_RESET                                                                      0x1272
6561 #define mmDPP_TOP4_DPP_SOFT_RESET_BASE_IDX                                                             2
6562 #define mmDPP_TOP4_DPP_CRC_VAL_R_G                                                                     0x1273
6563 #define mmDPP_TOP4_DPP_CRC_VAL_R_G_BASE_IDX                                                            2
6564 #define mmDPP_TOP4_DPP_CRC_VAL_B_A                                                                     0x1274
6565 #define mmDPP_TOP4_DPP_CRC_VAL_B_A_BASE_IDX                                                            2
6566 #define mmDPP_TOP4_DPP_CRC_CTRL                                                                        0x1275
6567 #define mmDPP_TOP4_DPP_CRC_CTRL_BASE_IDX                                                               2
6568 #define mmDPP_TOP4_HOST_READ_CONTROL                                                                   0x1276
6569 #define mmDPP_TOP4_HOST_READ_CONTROL_BASE_IDX                                                          2
6570 
6571 
6572 // addressBlock: dce_dc_dpp4_dispdec_cnvc_cfg_dispdec
6573 // base address: 0x16b0
6574 #define mmCNVC_CFG4_CNVC_SURFACE_PIXEL_FORMAT                                                          0x127b
6575 #define mmCNVC_CFG4_CNVC_SURFACE_PIXEL_FORMAT_BASE_IDX                                                 2
6576 #define mmCNVC_CFG4_FORMAT_CONTROL                                                                     0x127c
6577 #define mmCNVC_CFG4_FORMAT_CONTROL_BASE_IDX                                                            2
6578 #define mmCNVC_CFG4_FCNV_FP_BIAS_R                                                                     0x127d
6579 #define mmCNVC_CFG4_FCNV_FP_BIAS_R_BASE_IDX                                                            2
6580 #define mmCNVC_CFG4_FCNV_FP_BIAS_G                                                                     0x127e
6581 #define mmCNVC_CFG4_FCNV_FP_BIAS_G_BASE_IDX                                                            2
6582 #define mmCNVC_CFG4_FCNV_FP_BIAS_B                                                                     0x127f
6583 #define mmCNVC_CFG4_FCNV_FP_BIAS_B_BASE_IDX                                                            2
6584 #define mmCNVC_CFG4_FCNV_FP_SCALE_R                                                                    0x1280
6585 #define mmCNVC_CFG4_FCNV_FP_SCALE_R_BASE_IDX                                                           2
6586 #define mmCNVC_CFG4_FCNV_FP_SCALE_G                                                                    0x1281
6587 #define mmCNVC_CFG4_FCNV_FP_SCALE_G_BASE_IDX                                                           2
6588 #define mmCNVC_CFG4_FCNV_FP_SCALE_B                                                                    0x1282
6589 #define mmCNVC_CFG4_FCNV_FP_SCALE_B_BASE_IDX                                                           2
6590 #define mmCNVC_CFG4_COLOR_KEYER_CONTROL                                                                0x1283
6591 #define mmCNVC_CFG4_COLOR_KEYER_CONTROL_BASE_IDX                                                       2
6592 #define mmCNVC_CFG4_COLOR_KEYER_ALPHA                                                                  0x1284
6593 #define mmCNVC_CFG4_COLOR_KEYER_ALPHA_BASE_IDX                                                         2
6594 #define mmCNVC_CFG4_COLOR_KEYER_RED                                                                    0x1285
6595 #define mmCNVC_CFG4_COLOR_KEYER_RED_BASE_IDX                                                           2
6596 #define mmCNVC_CFG4_COLOR_KEYER_GREEN                                                                  0x1286
6597 #define mmCNVC_CFG4_COLOR_KEYER_GREEN_BASE_IDX                                                         2
6598 #define mmCNVC_CFG4_COLOR_KEYER_BLUE                                                                   0x1287
6599 #define mmCNVC_CFG4_COLOR_KEYER_BLUE_BASE_IDX                                                          2
6600 #define mmCNVC_CFG4_ALPHA_2BIT_LUT                                                                     0x1289
6601 #define mmCNVC_CFG4_ALPHA_2BIT_LUT_BASE_IDX                                                            2
6602 #define mmCNVC_CFG4_PRE_DEALPHA                                                                        0x128a
6603 #define mmCNVC_CFG4_PRE_DEALPHA_BASE_IDX                                                               2
6604 #define mmCNVC_CFG4_PRE_CSC_MODE                                                                       0x128b
6605 #define mmCNVC_CFG4_PRE_CSC_MODE_BASE_IDX                                                              2
6606 #define mmCNVC_CFG4_PRE_CSC_C11_C12                                                                    0x128c
6607 #define mmCNVC_CFG4_PRE_CSC_C11_C12_BASE_IDX                                                           2
6608 #define mmCNVC_CFG4_PRE_CSC_C13_C14                                                                    0x128d
6609 #define mmCNVC_CFG4_PRE_CSC_C13_C14_BASE_IDX                                                           2
6610 #define mmCNVC_CFG4_PRE_CSC_C21_C22                                                                    0x128e
6611 #define mmCNVC_CFG4_PRE_CSC_C21_C22_BASE_IDX                                                           2
6612 #define mmCNVC_CFG4_PRE_CSC_C23_C24                                                                    0x128f
6613 #define mmCNVC_CFG4_PRE_CSC_C23_C24_BASE_IDX                                                           2
6614 #define mmCNVC_CFG4_PRE_CSC_C31_C32                                                                    0x1290
6615 #define mmCNVC_CFG4_PRE_CSC_C31_C32_BASE_IDX                                                           2
6616 #define mmCNVC_CFG4_PRE_CSC_C33_C34                                                                    0x1291
6617 #define mmCNVC_CFG4_PRE_CSC_C33_C34_BASE_IDX                                                           2
6618 #define mmCNVC_CFG4_PRE_CSC_B_C11_C12                                                                  0x1292
6619 #define mmCNVC_CFG4_PRE_CSC_B_C11_C12_BASE_IDX                                                         2
6620 #define mmCNVC_CFG4_PRE_CSC_B_C13_C14                                                                  0x1293
6621 #define mmCNVC_CFG4_PRE_CSC_B_C13_C14_BASE_IDX                                                         2
6622 #define mmCNVC_CFG4_PRE_CSC_B_C21_C22                                                                  0x1294
6623 #define mmCNVC_CFG4_PRE_CSC_B_C21_C22_BASE_IDX                                                         2
6624 #define mmCNVC_CFG4_PRE_CSC_B_C23_C24                                                                  0x1295
6625 #define mmCNVC_CFG4_PRE_CSC_B_C23_C24_BASE_IDX                                                         2
6626 #define mmCNVC_CFG4_PRE_CSC_B_C31_C32                                                                  0x1296
6627 #define mmCNVC_CFG4_PRE_CSC_B_C31_C32_BASE_IDX                                                         2
6628 #define mmCNVC_CFG4_PRE_CSC_B_C33_C34                                                                  0x1297
6629 #define mmCNVC_CFG4_PRE_CSC_B_C33_C34_BASE_IDX                                                         2
6630 #define mmCNVC_CFG4_CNVC_COEF_FORMAT                                                                   0x1298
6631 #define mmCNVC_CFG4_CNVC_COEF_FORMAT_BASE_IDX                                                          2
6632 #define mmCNVC_CFG4_PRE_DEGAM                                                                          0x1299
6633 #define mmCNVC_CFG4_PRE_DEGAM_BASE_IDX                                                                 2
6634 #define mmCNVC_CFG4_PRE_REALPHA                                                                        0x129a
6635 #define mmCNVC_CFG4_PRE_REALPHA_BASE_IDX                                                               2
6636 
6637 
6638 // addressBlock: dce_dc_dpp4_dispdec_cnvc_cur_dispdec
6639 // base address: 0x16b0
6640 #define mmCNVC_CUR4_CURSOR0_CONTROL                                                                    0x129d
6641 #define mmCNVC_CUR4_CURSOR0_CONTROL_BASE_IDX                                                           2
6642 #define mmCNVC_CUR4_CURSOR0_COLOR0                                                                     0x129e
6643 #define mmCNVC_CUR4_CURSOR0_COLOR0_BASE_IDX                                                            2
6644 #define mmCNVC_CUR4_CURSOR0_COLOR1                                                                     0x129f
6645 #define mmCNVC_CUR4_CURSOR0_COLOR1_BASE_IDX                                                            2
6646 #define mmCNVC_CUR4_CURSOR0_FP_SCALE_BIAS                                                              0x12a0
6647 #define mmCNVC_CUR4_CURSOR0_FP_SCALE_BIAS_BASE_IDX                                                     2
6648 
6649 
6650 // addressBlock: dce_dc_dpp4_dispdec_dscl_dispdec
6651 // base address: 0x16b0
6652 #define mmDSCL4_SCL_COEF_RAM_TAP_SELECT                                                                0x12a5
6653 #define mmDSCL4_SCL_COEF_RAM_TAP_SELECT_BASE_IDX                                                       2
6654 #define mmDSCL4_SCL_COEF_RAM_TAP_DATA                                                                  0x12a6
6655 #define mmDSCL4_SCL_COEF_RAM_TAP_DATA_BASE_IDX                                                         2
6656 #define mmDSCL4_SCL_MODE                                                                               0x12a7
6657 #define mmDSCL4_SCL_MODE_BASE_IDX                                                                      2
6658 #define mmDSCL4_SCL_TAP_CONTROL                                                                        0x12a8
6659 #define mmDSCL4_SCL_TAP_CONTROL_BASE_IDX                                                               2
6660 #define mmDSCL4_DSCL_CONTROL                                                                           0x12a9
6661 #define mmDSCL4_DSCL_CONTROL_BASE_IDX                                                                  2
6662 #define mmDSCL4_DSCL_2TAP_CONTROL                                                                      0x12aa
6663 #define mmDSCL4_DSCL_2TAP_CONTROL_BASE_IDX                                                             2
6664 #define mmDSCL4_SCL_MANUAL_REPLICATE_CONTROL                                                           0x12ab
6665 #define mmDSCL4_SCL_MANUAL_REPLICATE_CONTROL_BASE_IDX                                                  2
6666 #define mmDSCL4_SCL_HORZ_FILTER_SCALE_RATIO                                                            0x12ac
6667 #define mmDSCL4_SCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX                                                   2
6668 #define mmDSCL4_SCL_HORZ_FILTER_INIT                                                                   0x12ad
6669 #define mmDSCL4_SCL_HORZ_FILTER_INIT_BASE_IDX                                                          2
6670 #define mmDSCL4_SCL_HORZ_FILTER_SCALE_RATIO_C                                                          0x12ae
6671 #define mmDSCL4_SCL_HORZ_FILTER_SCALE_RATIO_C_BASE_IDX                                                 2
6672 #define mmDSCL4_SCL_HORZ_FILTER_INIT_C                                                                 0x12af
6673 #define mmDSCL4_SCL_HORZ_FILTER_INIT_C_BASE_IDX                                                        2
6674 #define mmDSCL4_SCL_VERT_FILTER_SCALE_RATIO                                                            0x12b0
6675 #define mmDSCL4_SCL_VERT_FILTER_SCALE_RATIO_BASE_IDX                                                   2
6676 #define mmDSCL4_SCL_VERT_FILTER_INIT                                                                   0x12b1
6677 #define mmDSCL4_SCL_VERT_FILTER_INIT_BASE_IDX                                                          2
6678 #define mmDSCL4_SCL_VERT_FILTER_INIT_BOT                                                               0x12b2
6679 #define mmDSCL4_SCL_VERT_FILTER_INIT_BOT_BASE_IDX                                                      2
6680 #define mmDSCL4_SCL_VERT_FILTER_SCALE_RATIO_C                                                          0x12b3
6681 #define mmDSCL4_SCL_VERT_FILTER_SCALE_RATIO_C_BASE_IDX                                                 2
6682 #define mmDSCL4_SCL_VERT_FILTER_INIT_C                                                                 0x12b4
6683 #define mmDSCL4_SCL_VERT_FILTER_INIT_C_BASE_IDX                                                        2
6684 #define mmDSCL4_SCL_VERT_FILTER_INIT_BOT_C                                                             0x12b5
6685 #define mmDSCL4_SCL_VERT_FILTER_INIT_BOT_C_BASE_IDX                                                    2
6686 #define mmDSCL4_SCL_BLACK_COLOR                                                                        0x12b6
6687 #define mmDSCL4_SCL_BLACK_COLOR_BASE_IDX                                                               2
6688 #define mmDSCL4_DSCL_UPDATE                                                                            0x12b7
6689 #define mmDSCL4_DSCL_UPDATE_BASE_IDX                                                                   2
6690 #define mmDSCL4_DSCL_AUTOCAL                                                                           0x12b8
6691 #define mmDSCL4_DSCL_AUTOCAL_BASE_IDX                                                                  2
6692 #define mmDSCL4_DSCL_EXT_OVERSCAN_LEFT_RIGHT                                                           0x12b9
6693 #define mmDSCL4_DSCL_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX                                                  2
6694 #define mmDSCL4_DSCL_EXT_OVERSCAN_TOP_BOTTOM                                                           0x12ba
6695 #define mmDSCL4_DSCL_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX                                                  2
6696 #define mmDSCL4_OTG_H_BLANK                                                                            0x12bb
6697 #define mmDSCL4_OTG_H_BLANK_BASE_IDX                                                                   2
6698 #define mmDSCL4_OTG_V_BLANK                                                                            0x12bc
6699 #define mmDSCL4_OTG_V_BLANK_BASE_IDX                                                                   2
6700 #define mmDSCL4_RECOUT_START                                                                           0x12bd
6701 #define mmDSCL4_RECOUT_START_BASE_IDX                                                                  2
6702 #define mmDSCL4_RECOUT_SIZE                                                                            0x12be
6703 #define mmDSCL4_RECOUT_SIZE_BASE_IDX                                                                   2
6704 #define mmDSCL4_MPC_SIZE                                                                               0x12bf
6705 #define mmDSCL4_MPC_SIZE_BASE_IDX                                                                      2
6706 #define mmDSCL4_LB_DATA_FORMAT                                                                         0x12c0
6707 #define mmDSCL4_LB_DATA_FORMAT_BASE_IDX                                                                2
6708 #define mmDSCL4_LB_MEMORY_CTRL                                                                         0x12c1
6709 #define mmDSCL4_LB_MEMORY_CTRL_BASE_IDX                                                                2
6710 #define mmDSCL4_LB_V_COUNTER                                                                           0x12c2
6711 #define mmDSCL4_LB_V_COUNTER_BASE_IDX                                                                  2
6712 #define mmDSCL4_DSCL_MEM_PWR_CTRL                                                                      0x12c3
6713 #define mmDSCL4_DSCL_MEM_PWR_CTRL_BASE_IDX                                                             2
6714 #define mmDSCL4_DSCL_MEM_PWR_STATUS                                                                    0x12c4
6715 #define mmDSCL4_DSCL_MEM_PWR_STATUS_BASE_IDX                                                           2
6716 #define mmDSCL4_OBUF_CONTROL                                                                           0x12c5
6717 #define mmDSCL4_OBUF_CONTROL_BASE_IDX                                                                  2
6718 #define mmDSCL4_OBUF_MEM_PWR_CTRL                                                                      0x12c6
6719 #define mmDSCL4_OBUF_MEM_PWR_CTRL_BASE_IDX                                                             2
6720 
6721 
6722 // addressBlock: dce_dc_dpp4_dispdec_cm_dispdec
6723 // base address: 0x16b0
6724 #define mmCM4_CM_CONTROL                                                                               0x12cc
6725 #define mmCM4_CM_CONTROL_BASE_IDX                                                                      2
6726 #define mmCM4_CM_POST_CSC_CONTROL                                                                      0x12cd
6727 #define mmCM4_CM_POST_CSC_CONTROL_BASE_IDX                                                             2
6728 #define mmCM4_CM_POST_CSC_C11_C12                                                                      0x12ce
6729 #define mmCM4_CM_POST_CSC_C11_C12_BASE_IDX                                                             2
6730 #define mmCM4_CM_POST_CSC_C13_C14                                                                      0x12cf
6731 #define mmCM4_CM_POST_CSC_C13_C14_BASE_IDX                                                             2
6732 #define mmCM4_CM_POST_CSC_C21_C22                                                                      0x12d0
6733 #define mmCM4_CM_POST_CSC_C21_C22_BASE_IDX                                                             2
6734 #define mmCM4_CM_POST_CSC_C23_C24                                                                      0x12d1
6735 #define mmCM4_CM_POST_CSC_C23_C24_BASE_IDX                                                             2
6736 #define mmCM4_CM_POST_CSC_C31_C32                                                                      0x12d2
6737 #define mmCM4_CM_POST_CSC_C31_C32_BASE_IDX                                                             2
6738 #define mmCM4_CM_POST_CSC_C33_C34                                                                      0x12d3
6739 #define mmCM4_CM_POST_CSC_C33_C34_BASE_IDX                                                             2
6740 #define mmCM4_CM_POST_CSC_B_C11_C12                                                                    0x12d4
6741 #define mmCM4_CM_POST_CSC_B_C11_C12_BASE_IDX                                                           2
6742 #define mmCM4_CM_POST_CSC_B_C13_C14                                                                    0x12d5
6743 #define mmCM4_CM_POST_CSC_B_C13_C14_BASE_IDX                                                           2
6744 #define mmCM4_CM_POST_CSC_B_C21_C22                                                                    0x12d6
6745 #define mmCM4_CM_POST_CSC_B_C21_C22_BASE_IDX                                                           2
6746 #define mmCM4_CM_POST_CSC_B_C23_C24                                                                    0x12d7
6747 #define mmCM4_CM_POST_CSC_B_C23_C24_BASE_IDX                                                           2
6748 #define mmCM4_CM_POST_CSC_B_C31_C32                                                                    0x12d8
6749 #define mmCM4_CM_POST_CSC_B_C31_C32_BASE_IDX                                                           2
6750 #define mmCM4_CM_POST_CSC_B_C33_C34                                                                    0x12d9
6751 #define mmCM4_CM_POST_CSC_B_C33_C34_BASE_IDX                                                           2
6752 #define mmCM4_CM_GAMUT_REMAP_CONTROL                                                                   0x12da
6753 #define mmCM4_CM_GAMUT_REMAP_CONTROL_BASE_IDX                                                          2
6754 #define mmCM4_CM_GAMUT_REMAP_C11_C12                                                                   0x12db
6755 #define mmCM4_CM_GAMUT_REMAP_C11_C12_BASE_IDX                                                          2
6756 #define mmCM4_CM_GAMUT_REMAP_C13_C14                                                                   0x12dc
6757 #define mmCM4_CM_GAMUT_REMAP_C13_C14_BASE_IDX                                                          2
6758 #define mmCM4_CM_GAMUT_REMAP_C21_C22                                                                   0x12dd
6759 #define mmCM4_CM_GAMUT_REMAP_C21_C22_BASE_IDX                                                          2
6760 #define mmCM4_CM_GAMUT_REMAP_C23_C24                                                                   0x12de
6761 #define mmCM4_CM_GAMUT_REMAP_C23_C24_BASE_IDX                                                          2
6762 #define mmCM4_CM_GAMUT_REMAP_C31_C32                                                                   0x12df
6763 #define mmCM4_CM_GAMUT_REMAP_C31_C32_BASE_IDX                                                          2
6764 #define mmCM4_CM_GAMUT_REMAP_C33_C34                                                                   0x12e0
6765 #define mmCM4_CM_GAMUT_REMAP_C33_C34_BASE_IDX                                                          2
6766 #define mmCM4_CM_GAMUT_REMAP_B_C11_C12                                                                 0x12e1
6767 #define mmCM4_CM_GAMUT_REMAP_B_C11_C12_BASE_IDX                                                        2
6768 #define mmCM4_CM_GAMUT_REMAP_B_C13_C14                                                                 0x12e2
6769 #define mmCM4_CM_GAMUT_REMAP_B_C13_C14_BASE_IDX                                                        2
6770 #define mmCM4_CM_GAMUT_REMAP_B_C21_C22                                                                 0x12e3
6771 #define mmCM4_CM_GAMUT_REMAP_B_C21_C22_BASE_IDX                                                        2
6772 #define mmCM4_CM_GAMUT_REMAP_B_C23_C24                                                                 0x12e4
6773 #define mmCM4_CM_GAMUT_REMAP_B_C23_C24_BASE_IDX                                                        2
6774 #define mmCM4_CM_GAMUT_REMAP_B_C31_C32                                                                 0x12e5
6775 #define mmCM4_CM_GAMUT_REMAP_B_C31_C32_BASE_IDX                                                        2
6776 #define mmCM4_CM_GAMUT_REMAP_B_C33_C34                                                                 0x12e6
6777 #define mmCM4_CM_GAMUT_REMAP_B_C33_C34_BASE_IDX                                                        2
6778 #define mmCM4_CM_BIAS_CR_R                                                                             0x12e7
6779 #define mmCM4_CM_BIAS_CR_R_BASE_IDX                                                                    2
6780 #define mmCM4_CM_BIAS_Y_G_CB_B                                                                         0x12e8
6781 #define mmCM4_CM_BIAS_Y_G_CB_B_BASE_IDX                                                                2
6782 #define mmCM4_CM_GAMCOR_CONTROL                                                                        0x12e9
6783 #define mmCM4_CM_GAMCOR_CONTROL_BASE_IDX                                                               2
6784 #define mmCM4_CM_GAMCOR_LUT_INDEX                                                                      0x12ea
6785 #define mmCM4_CM_GAMCOR_LUT_INDEX_BASE_IDX                                                             2
6786 #define mmCM4_CM_GAMCOR_LUT_DATA                                                                       0x12eb
6787 #define mmCM4_CM_GAMCOR_LUT_DATA_BASE_IDX                                                              2
6788 #define mmCM4_CM_GAMCOR_LUT_CONTROL                                                                    0x12ec
6789 #define mmCM4_CM_GAMCOR_LUT_CONTROL_BASE_IDX                                                           2
6790 #define mmCM4_CM_GAMCOR_RAMA_START_CNTL_B                                                              0x12ed
6791 #define mmCM4_CM_GAMCOR_RAMA_START_CNTL_B_BASE_IDX                                                     2
6792 #define mmCM4_CM_GAMCOR_RAMA_START_CNTL_G                                                              0x12ee
6793 #define mmCM4_CM_GAMCOR_RAMA_START_CNTL_G_BASE_IDX                                                     2
6794 #define mmCM4_CM_GAMCOR_RAMA_START_CNTL_R                                                              0x12ef
6795 #define mmCM4_CM_GAMCOR_RAMA_START_CNTL_R_BASE_IDX                                                     2
6796 #define mmCM4_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B                                                        0x12f0
6797 #define mmCM4_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B_BASE_IDX                                               2
6798 #define mmCM4_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G                                                        0x12f1
6799 #define mmCM4_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G_BASE_IDX                                               2
6800 #define mmCM4_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R                                                        0x12f2
6801 #define mmCM4_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R_BASE_IDX                                               2
6802 #define mmCM4_CM_GAMCOR_RAMA_START_BASE_CNTL_B                                                         0x12f3
6803 #define mmCM4_CM_GAMCOR_RAMA_START_BASE_CNTL_B_BASE_IDX                                                2
6804 #define mmCM4_CM_GAMCOR_RAMA_START_BASE_CNTL_G                                                         0x12f4
6805 #define mmCM4_CM_GAMCOR_RAMA_START_BASE_CNTL_G_BASE_IDX                                                2
6806 #define mmCM4_CM_GAMCOR_RAMA_START_BASE_CNTL_R                                                         0x12f5
6807 #define mmCM4_CM_GAMCOR_RAMA_START_BASE_CNTL_R_BASE_IDX                                                2
6808 #define mmCM4_CM_GAMCOR_RAMA_END_CNTL1_B                                                               0x12f6
6809 #define mmCM4_CM_GAMCOR_RAMA_END_CNTL1_B_BASE_IDX                                                      2
6810 #define mmCM4_CM_GAMCOR_RAMA_END_CNTL2_B                                                               0x12f7
6811 #define mmCM4_CM_GAMCOR_RAMA_END_CNTL2_B_BASE_IDX                                                      2
6812 #define mmCM4_CM_GAMCOR_RAMA_END_CNTL1_G                                                               0x12f8
6813 #define mmCM4_CM_GAMCOR_RAMA_END_CNTL1_G_BASE_IDX                                                      2
6814 #define mmCM4_CM_GAMCOR_RAMA_END_CNTL2_G                                                               0x12f9
6815 #define mmCM4_CM_GAMCOR_RAMA_END_CNTL2_G_BASE_IDX                                                      2
6816 #define mmCM4_CM_GAMCOR_RAMA_END_CNTL1_R                                                               0x12fa
6817 #define mmCM4_CM_GAMCOR_RAMA_END_CNTL1_R_BASE_IDX                                                      2
6818 #define mmCM4_CM_GAMCOR_RAMA_END_CNTL2_R                                                               0x12fb
6819 #define mmCM4_CM_GAMCOR_RAMA_END_CNTL2_R_BASE_IDX                                                      2
6820 #define mmCM4_CM_GAMCOR_RAMA_OFFSET_B                                                                  0x12fc
6821 #define mmCM4_CM_GAMCOR_RAMA_OFFSET_B_BASE_IDX                                                         2
6822 #define mmCM4_CM_GAMCOR_RAMA_OFFSET_G                                                                  0x12fd
6823 #define mmCM4_CM_GAMCOR_RAMA_OFFSET_G_BASE_IDX                                                         2
6824 #define mmCM4_CM_GAMCOR_RAMA_OFFSET_R                                                                  0x12fe
6825 #define mmCM4_CM_GAMCOR_RAMA_OFFSET_R_BASE_IDX                                                         2
6826 #define mmCM4_CM_GAMCOR_RAMA_REGION_0_1                                                                0x12ff
6827 #define mmCM4_CM_GAMCOR_RAMA_REGION_0_1_BASE_IDX                                                       2
6828 #define mmCM4_CM_GAMCOR_RAMA_REGION_2_3                                                                0x1300
6829 #define mmCM4_CM_GAMCOR_RAMA_REGION_2_3_BASE_IDX                                                       2
6830 #define mmCM4_CM_GAMCOR_RAMA_REGION_4_5                                                                0x1301
6831 #define mmCM4_CM_GAMCOR_RAMA_REGION_4_5_BASE_IDX                                                       2
6832 #define mmCM4_CM_GAMCOR_RAMA_REGION_6_7                                                                0x1302
6833 #define mmCM4_CM_GAMCOR_RAMA_REGION_6_7_BASE_IDX                                                       2
6834 #define mmCM4_CM_GAMCOR_RAMA_REGION_8_9                                                                0x1303
6835 #define mmCM4_CM_GAMCOR_RAMA_REGION_8_9_BASE_IDX                                                       2
6836 #define mmCM4_CM_GAMCOR_RAMA_REGION_10_11                                                              0x1304
6837 #define mmCM4_CM_GAMCOR_RAMA_REGION_10_11_BASE_IDX                                                     2
6838 #define mmCM4_CM_GAMCOR_RAMA_REGION_12_13                                                              0x1305
6839 #define mmCM4_CM_GAMCOR_RAMA_REGION_12_13_BASE_IDX                                                     2
6840 #define mmCM4_CM_GAMCOR_RAMA_REGION_14_15                                                              0x1306
6841 #define mmCM4_CM_GAMCOR_RAMA_REGION_14_15_BASE_IDX                                                     2
6842 #define mmCM4_CM_GAMCOR_RAMA_REGION_16_17                                                              0x1307
6843 #define mmCM4_CM_GAMCOR_RAMA_REGION_16_17_BASE_IDX                                                     2
6844 #define mmCM4_CM_GAMCOR_RAMA_REGION_18_19                                                              0x1308
6845 #define mmCM4_CM_GAMCOR_RAMA_REGION_18_19_BASE_IDX                                                     2
6846 #define mmCM4_CM_GAMCOR_RAMA_REGION_20_21                                                              0x1309
6847 #define mmCM4_CM_GAMCOR_RAMA_REGION_20_21_BASE_IDX                                                     2
6848 #define mmCM4_CM_GAMCOR_RAMA_REGION_22_23                                                              0x130a
6849 #define mmCM4_CM_GAMCOR_RAMA_REGION_22_23_BASE_IDX                                                     2
6850 #define mmCM4_CM_GAMCOR_RAMA_REGION_24_25                                                              0x130b
6851 #define mmCM4_CM_GAMCOR_RAMA_REGION_24_25_BASE_IDX                                                     2
6852 #define mmCM4_CM_GAMCOR_RAMA_REGION_26_27                                                              0x130c
6853 #define mmCM4_CM_GAMCOR_RAMA_REGION_26_27_BASE_IDX                                                     2
6854 #define mmCM4_CM_GAMCOR_RAMA_REGION_28_29                                                              0x130d
6855 #define mmCM4_CM_GAMCOR_RAMA_REGION_28_29_BASE_IDX                                                     2
6856 #define mmCM4_CM_GAMCOR_RAMA_REGION_30_31                                                              0x130e
6857 #define mmCM4_CM_GAMCOR_RAMA_REGION_30_31_BASE_IDX                                                     2
6858 #define mmCM4_CM_GAMCOR_RAMA_REGION_32_33                                                              0x130f
6859 #define mmCM4_CM_GAMCOR_RAMA_REGION_32_33_BASE_IDX                                                     2
6860 #define mmCM4_CM_GAMCOR_RAMB_START_CNTL_B                                                              0x1310
6861 #define mmCM4_CM_GAMCOR_RAMB_START_CNTL_B_BASE_IDX                                                     2
6862 #define mmCM4_CM_GAMCOR_RAMB_START_CNTL_G                                                              0x1311
6863 #define mmCM4_CM_GAMCOR_RAMB_START_CNTL_G_BASE_IDX                                                     2
6864 #define mmCM4_CM_GAMCOR_RAMB_START_CNTL_R                                                              0x1312
6865 #define mmCM4_CM_GAMCOR_RAMB_START_CNTL_R_BASE_IDX                                                     2
6866 #define mmCM4_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B                                                        0x1313
6867 #define mmCM4_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B_BASE_IDX                                               2
6868 #define mmCM4_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G                                                        0x1314
6869 #define mmCM4_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G_BASE_IDX                                               2
6870 #define mmCM4_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R                                                        0x1315
6871 #define mmCM4_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R_BASE_IDX                                               2
6872 #define mmCM4_CM_GAMCOR_RAMB_START_BASE_CNTL_B                                                         0x1316
6873 #define mmCM4_CM_GAMCOR_RAMB_START_BASE_CNTL_B_BASE_IDX                                                2
6874 #define mmCM4_CM_GAMCOR_RAMB_START_BASE_CNTL_G                                                         0x1317
6875 #define mmCM4_CM_GAMCOR_RAMB_START_BASE_CNTL_G_BASE_IDX                                                2
6876 #define mmCM4_CM_GAMCOR_RAMB_START_BASE_CNTL_R                                                         0x1318
6877 #define mmCM4_CM_GAMCOR_RAMB_START_BASE_CNTL_R_BASE_IDX                                                2
6878 #define mmCM4_CM_GAMCOR_RAMB_END_CNTL1_B                                                               0x1319
6879 #define mmCM4_CM_GAMCOR_RAMB_END_CNTL1_B_BASE_IDX                                                      2
6880 #define mmCM4_CM_GAMCOR_RAMB_END_CNTL2_B                                                               0x131a
6881 #define mmCM4_CM_GAMCOR_RAMB_END_CNTL2_B_BASE_IDX                                                      2
6882 #define mmCM4_CM_GAMCOR_RAMB_END_CNTL1_G                                                               0x131b
6883 #define mmCM4_CM_GAMCOR_RAMB_END_CNTL1_G_BASE_IDX                                                      2
6884 #define mmCM4_CM_GAMCOR_RAMB_END_CNTL2_G                                                               0x131c
6885 #define mmCM4_CM_GAMCOR_RAMB_END_CNTL2_G_BASE_IDX                                                      2
6886 #define mmCM4_CM_GAMCOR_RAMB_END_CNTL1_R                                                               0x131d
6887 #define mmCM4_CM_GAMCOR_RAMB_END_CNTL1_R_BASE_IDX                                                      2
6888 #define mmCM4_CM_GAMCOR_RAMB_END_CNTL2_R                                                               0x131e
6889 #define mmCM4_CM_GAMCOR_RAMB_END_CNTL2_R_BASE_IDX                                                      2
6890 #define mmCM4_CM_GAMCOR_RAMB_OFFSET_B                                                                  0x131f
6891 #define mmCM4_CM_GAMCOR_RAMB_OFFSET_B_BASE_IDX                                                         2
6892 #define mmCM4_CM_GAMCOR_RAMB_OFFSET_G                                                                  0x1320
6893 #define mmCM4_CM_GAMCOR_RAMB_OFFSET_G_BASE_IDX                                                         2
6894 #define mmCM4_CM_GAMCOR_RAMB_OFFSET_R                                                                  0x1321
6895 #define mmCM4_CM_GAMCOR_RAMB_OFFSET_R_BASE_IDX                                                         2
6896 #define mmCM4_CM_GAMCOR_RAMB_REGION_0_1                                                                0x1322
6897 #define mmCM4_CM_GAMCOR_RAMB_REGION_0_1_BASE_IDX                                                       2
6898 #define mmCM4_CM_GAMCOR_RAMB_REGION_2_3                                                                0x1323
6899 #define mmCM4_CM_GAMCOR_RAMB_REGION_2_3_BASE_IDX                                                       2
6900 #define mmCM4_CM_GAMCOR_RAMB_REGION_4_5                                                                0x1324
6901 #define mmCM4_CM_GAMCOR_RAMB_REGION_4_5_BASE_IDX                                                       2
6902 #define mmCM4_CM_GAMCOR_RAMB_REGION_6_7                                                                0x1325
6903 #define mmCM4_CM_GAMCOR_RAMB_REGION_6_7_BASE_IDX                                                       2
6904 #define mmCM4_CM_GAMCOR_RAMB_REGION_8_9                                                                0x1326
6905 #define mmCM4_CM_GAMCOR_RAMB_REGION_8_9_BASE_IDX                                                       2
6906 #define mmCM4_CM_GAMCOR_RAMB_REGION_10_11                                                              0x1327
6907 #define mmCM4_CM_GAMCOR_RAMB_REGION_10_11_BASE_IDX                                                     2
6908 #define mmCM4_CM_GAMCOR_RAMB_REGION_12_13                                                              0x1328
6909 #define mmCM4_CM_GAMCOR_RAMB_REGION_12_13_BASE_IDX                                                     2
6910 #define mmCM4_CM_GAMCOR_RAMB_REGION_14_15                                                              0x1329
6911 #define mmCM4_CM_GAMCOR_RAMB_REGION_14_15_BASE_IDX                                                     2
6912 #define mmCM4_CM_GAMCOR_RAMB_REGION_16_17                                                              0x132a
6913 #define mmCM4_CM_GAMCOR_RAMB_REGION_16_17_BASE_IDX                                                     2
6914 #define mmCM4_CM_GAMCOR_RAMB_REGION_18_19                                                              0x132b
6915 #define mmCM4_CM_GAMCOR_RAMB_REGION_18_19_BASE_IDX                                                     2
6916 #define mmCM4_CM_GAMCOR_RAMB_REGION_20_21                                                              0x132c
6917 #define mmCM4_CM_GAMCOR_RAMB_REGION_20_21_BASE_IDX                                                     2
6918 #define mmCM4_CM_GAMCOR_RAMB_REGION_22_23                                                              0x132d
6919 #define mmCM4_CM_GAMCOR_RAMB_REGION_22_23_BASE_IDX                                                     2
6920 #define mmCM4_CM_GAMCOR_RAMB_REGION_24_25                                                              0x132e
6921 #define mmCM4_CM_GAMCOR_RAMB_REGION_24_25_BASE_IDX                                                     2
6922 #define mmCM4_CM_GAMCOR_RAMB_REGION_26_27                                                              0x132f
6923 #define mmCM4_CM_GAMCOR_RAMB_REGION_26_27_BASE_IDX                                                     2
6924 #define mmCM4_CM_GAMCOR_RAMB_REGION_28_29                                                              0x1330
6925 #define mmCM4_CM_GAMCOR_RAMB_REGION_28_29_BASE_IDX                                                     2
6926 #define mmCM4_CM_GAMCOR_RAMB_REGION_30_31                                                              0x1331
6927 #define mmCM4_CM_GAMCOR_RAMB_REGION_30_31_BASE_IDX                                                     2
6928 #define mmCM4_CM_GAMCOR_RAMB_REGION_32_33                                                              0x1332
6929 #define mmCM4_CM_GAMCOR_RAMB_REGION_32_33_BASE_IDX                                                     2
6930 #define mmCM4_CM_BLNDGAM_CONTROL                                                                       0x1333
6931 #define mmCM4_CM_BLNDGAM_CONTROL_BASE_IDX                                                              2
6932 #define mmCM4_CM_BLNDGAM_LUT_INDEX                                                                     0x1334
6933 #define mmCM4_CM_BLNDGAM_LUT_INDEX_BASE_IDX                                                            2
6934 #define mmCM4_CM_BLNDGAM_LUT_DATA                                                                      0x1335
6935 #define mmCM4_CM_BLNDGAM_LUT_DATA_BASE_IDX                                                             2
6936 #define mmCM4_CM_BLNDGAM_LUT_CONTROL                                                                   0x1336
6937 #define mmCM4_CM_BLNDGAM_LUT_CONTROL_BASE_IDX                                                          2
6938 #define mmCM4_CM_BLNDGAM_RAMA_START_CNTL_B                                                             0x1337
6939 #define mmCM4_CM_BLNDGAM_RAMA_START_CNTL_B_BASE_IDX                                                    2
6940 #define mmCM4_CM_BLNDGAM_RAMA_START_CNTL_G                                                             0x1338
6941 #define mmCM4_CM_BLNDGAM_RAMA_START_CNTL_G_BASE_IDX                                                    2
6942 #define mmCM4_CM_BLNDGAM_RAMA_START_CNTL_R                                                             0x1339
6943 #define mmCM4_CM_BLNDGAM_RAMA_START_CNTL_R_BASE_IDX                                                    2
6944 #define mmCM4_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_B                                                       0x133a
6945 #define mmCM4_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_B_BASE_IDX                                              2
6946 #define mmCM4_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_G                                                       0x133b
6947 #define mmCM4_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_G_BASE_IDX                                              2
6948 #define mmCM4_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_R                                                       0x133c
6949 #define mmCM4_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_R_BASE_IDX                                              2
6950 #define mmCM4_CM_BLNDGAM_RAMA_START_BASE_CNTL_B                                                        0x133d
6951 #define mmCM4_CM_BLNDGAM_RAMA_START_BASE_CNTL_B_BASE_IDX                                               2
6952 #define mmCM4_CM_BLNDGAM_RAMA_START_BASE_CNTL_G                                                        0x133e
6953 #define mmCM4_CM_BLNDGAM_RAMA_START_BASE_CNTL_G_BASE_IDX                                               2
6954 #define mmCM4_CM_BLNDGAM_RAMA_START_BASE_CNTL_R                                                        0x133f
6955 #define mmCM4_CM_BLNDGAM_RAMA_START_BASE_CNTL_R_BASE_IDX                                               2
6956 #define mmCM4_CM_BLNDGAM_RAMA_END_CNTL1_B                                                              0x1340
6957 #define mmCM4_CM_BLNDGAM_RAMA_END_CNTL1_B_BASE_IDX                                                     2
6958 #define mmCM4_CM_BLNDGAM_RAMA_END_CNTL2_B                                                              0x1341
6959 #define mmCM4_CM_BLNDGAM_RAMA_END_CNTL2_B_BASE_IDX                                                     2
6960 #define mmCM4_CM_BLNDGAM_RAMA_END_CNTL1_G                                                              0x1342
6961 #define mmCM4_CM_BLNDGAM_RAMA_END_CNTL1_G_BASE_IDX                                                     2
6962 #define mmCM4_CM_BLNDGAM_RAMA_END_CNTL2_G                                                              0x1343
6963 #define mmCM4_CM_BLNDGAM_RAMA_END_CNTL2_G_BASE_IDX                                                     2
6964 #define mmCM4_CM_BLNDGAM_RAMA_END_CNTL1_R                                                              0x1344
6965 #define mmCM4_CM_BLNDGAM_RAMA_END_CNTL1_R_BASE_IDX                                                     2
6966 #define mmCM4_CM_BLNDGAM_RAMA_END_CNTL2_R                                                              0x1345
6967 #define mmCM4_CM_BLNDGAM_RAMA_END_CNTL2_R_BASE_IDX                                                     2
6968 #define mmCM4_CM_BLNDGAM_RAMA_OFFSET_B                                                                 0x1346
6969 #define mmCM4_CM_BLNDGAM_RAMA_OFFSET_B_BASE_IDX                                                        2
6970 #define mmCM4_CM_BLNDGAM_RAMA_OFFSET_G                                                                 0x1347
6971 #define mmCM4_CM_BLNDGAM_RAMA_OFFSET_G_BASE_IDX                                                        2
6972 #define mmCM4_CM_BLNDGAM_RAMA_OFFSET_R                                                                 0x1348
6973 #define mmCM4_CM_BLNDGAM_RAMA_OFFSET_R_BASE_IDX                                                        2
6974 #define mmCM4_CM_BLNDGAM_RAMA_REGION_0_1                                                               0x1349
6975 #define mmCM4_CM_BLNDGAM_RAMA_REGION_0_1_BASE_IDX                                                      2
6976 #define mmCM4_CM_BLNDGAM_RAMA_REGION_2_3                                                               0x134a
6977 #define mmCM4_CM_BLNDGAM_RAMA_REGION_2_3_BASE_IDX                                                      2
6978 #define mmCM4_CM_BLNDGAM_RAMA_REGION_4_5                                                               0x134b
6979 #define mmCM4_CM_BLNDGAM_RAMA_REGION_4_5_BASE_IDX                                                      2
6980 #define mmCM4_CM_BLNDGAM_RAMA_REGION_6_7                                                               0x134c
6981 #define mmCM4_CM_BLNDGAM_RAMA_REGION_6_7_BASE_IDX                                                      2
6982 #define mmCM4_CM_BLNDGAM_RAMA_REGION_8_9                                                               0x134d
6983 #define mmCM4_CM_BLNDGAM_RAMA_REGION_8_9_BASE_IDX                                                      2
6984 #define mmCM4_CM_BLNDGAM_RAMA_REGION_10_11                                                             0x134e
6985 #define mmCM4_CM_BLNDGAM_RAMA_REGION_10_11_BASE_IDX                                                    2
6986 #define mmCM4_CM_BLNDGAM_RAMA_REGION_12_13                                                             0x134f
6987 #define mmCM4_CM_BLNDGAM_RAMA_REGION_12_13_BASE_IDX                                                    2
6988 #define mmCM4_CM_BLNDGAM_RAMA_REGION_14_15                                                             0x1350
6989 #define mmCM4_CM_BLNDGAM_RAMA_REGION_14_15_BASE_IDX                                                    2
6990 #define mmCM4_CM_BLNDGAM_RAMA_REGION_16_17                                                             0x1351
6991 #define mmCM4_CM_BLNDGAM_RAMA_REGION_16_17_BASE_IDX                                                    2
6992 #define mmCM4_CM_BLNDGAM_RAMA_REGION_18_19                                                             0x1352
6993 #define mmCM4_CM_BLNDGAM_RAMA_REGION_18_19_BASE_IDX                                                    2
6994 #define mmCM4_CM_BLNDGAM_RAMA_REGION_20_21                                                             0x1353
6995 #define mmCM4_CM_BLNDGAM_RAMA_REGION_20_21_BASE_IDX                                                    2
6996 #define mmCM4_CM_BLNDGAM_RAMA_REGION_22_23                                                             0x1354
6997 #define mmCM4_CM_BLNDGAM_RAMA_REGION_22_23_BASE_IDX                                                    2
6998 #define mmCM4_CM_BLNDGAM_RAMA_REGION_24_25                                                             0x1355
6999 #define mmCM4_CM_BLNDGAM_RAMA_REGION_24_25_BASE_IDX                                                    2
7000 #define mmCM4_CM_BLNDGAM_RAMA_REGION_26_27                                                             0x1356
7001 #define mmCM4_CM_BLNDGAM_RAMA_REGION_26_27_BASE_IDX                                                    2
7002 #define mmCM4_CM_BLNDGAM_RAMA_REGION_28_29                                                             0x1357
7003 #define mmCM4_CM_BLNDGAM_RAMA_REGION_28_29_BASE_IDX                                                    2
7004 #define mmCM4_CM_BLNDGAM_RAMA_REGION_30_31                                                             0x1358
7005 #define mmCM4_CM_BLNDGAM_RAMA_REGION_30_31_BASE_IDX                                                    2
7006 #define mmCM4_CM_BLNDGAM_RAMA_REGION_32_33                                                             0x1359
7007 #define mmCM4_CM_BLNDGAM_RAMA_REGION_32_33_BASE_IDX                                                    2
7008 #define mmCM4_CM_BLNDGAM_RAMB_START_CNTL_B                                                             0x135a
7009 #define mmCM4_CM_BLNDGAM_RAMB_START_CNTL_B_BASE_IDX                                                    2
7010 #define mmCM4_CM_BLNDGAM_RAMB_START_CNTL_G                                                             0x135b
7011 #define mmCM4_CM_BLNDGAM_RAMB_START_CNTL_G_BASE_IDX                                                    2
7012 #define mmCM4_CM_BLNDGAM_RAMB_START_CNTL_R                                                             0x135c
7013 #define mmCM4_CM_BLNDGAM_RAMB_START_CNTL_R_BASE_IDX                                                    2
7014 #define mmCM4_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_B                                                       0x135d
7015 #define mmCM4_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_B_BASE_IDX                                              2
7016 #define mmCM4_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_G                                                       0x135e
7017 #define mmCM4_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_G_BASE_IDX                                              2
7018 #define mmCM4_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_R                                                       0x135f
7019 #define mmCM4_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_R_BASE_IDX                                              2
7020 #define mmCM4_CM_BLNDGAM_RAMB_START_BASE_CNTL_B                                                        0x1360
7021 #define mmCM4_CM_BLNDGAM_RAMB_START_BASE_CNTL_B_BASE_IDX                                               2
7022 #define mmCM4_CM_BLNDGAM_RAMB_START_BASE_CNTL_G                                                        0x1361
7023 #define mmCM4_CM_BLNDGAM_RAMB_START_BASE_CNTL_G_BASE_IDX                                               2
7024 #define mmCM4_CM_BLNDGAM_RAMB_START_BASE_CNTL_R                                                        0x1362
7025 #define mmCM4_CM_BLNDGAM_RAMB_START_BASE_CNTL_R_BASE_IDX                                               2
7026 #define mmCM4_CM_BLNDGAM_RAMB_END_CNTL1_B                                                              0x1363
7027 #define mmCM4_CM_BLNDGAM_RAMB_END_CNTL1_B_BASE_IDX                                                     2
7028 #define mmCM4_CM_BLNDGAM_RAMB_END_CNTL2_B                                                              0x1364
7029 #define mmCM4_CM_BLNDGAM_RAMB_END_CNTL2_B_BASE_IDX                                                     2
7030 #define mmCM4_CM_BLNDGAM_RAMB_END_CNTL1_G                                                              0x1365
7031 #define mmCM4_CM_BLNDGAM_RAMB_END_CNTL1_G_BASE_IDX                                                     2
7032 #define mmCM4_CM_BLNDGAM_RAMB_END_CNTL2_G                                                              0x1366
7033 #define mmCM4_CM_BLNDGAM_RAMB_END_CNTL2_G_BASE_IDX                                                     2
7034 #define mmCM4_CM_BLNDGAM_RAMB_END_CNTL1_R                                                              0x1367
7035 #define mmCM4_CM_BLNDGAM_RAMB_END_CNTL1_R_BASE_IDX                                                     2
7036 #define mmCM4_CM_BLNDGAM_RAMB_END_CNTL2_R                                                              0x1368
7037 #define mmCM4_CM_BLNDGAM_RAMB_END_CNTL2_R_BASE_IDX                                                     2
7038 #define mmCM4_CM_BLNDGAM_RAMB_OFFSET_B                                                                 0x1369
7039 #define mmCM4_CM_BLNDGAM_RAMB_OFFSET_B_BASE_IDX                                                        2
7040 #define mmCM4_CM_BLNDGAM_RAMB_OFFSET_G                                                                 0x136a
7041 #define mmCM4_CM_BLNDGAM_RAMB_OFFSET_G_BASE_IDX                                                        2
7042 #define mmCM4_CM_BLNDGAM_RAMB_OFFSET_R                                                                 0x136b
7043 #define mmCM4_CM_BLNDGAM_RAMB_OFFSET_R_BASE_IDX                                                        2
7044 #define mmCM4_CM_BLNDGAM_RAMB_REGION_0_1                                                               0x136c
7045 #define mmCM4_CM_BLNDGAM_RAMB_REGION_0_1_BASE_IDX                                                      2
7046 #define mmCM4_CM_BLNDGAM_RAMB_REGION_2_3                                                               0x136d
7047 #define mmCM4_CM_BLNDGAM_RAMB_REGION_2_3_BASE_IDX                                                      2
7048 #define mmCM4_CM_BLNDGAM_RAMB_REGION_4_5                                                               0x136e
7049 #define mmCM4_CM_BLNDGAM_RAMB_REGION_4_5_BASE_IDX                                                      2
7050 #define mmCM4_CM_BLNDGAM_RAMB_REGION_6_7                                                               0x136f
7051 #define mmCM4_CM_BLNDGAM_RAMB_REGION_6_7_BASE_IDX                                                      2
7052 #define mmCM4_CM_BLNDGAM_RAMB_REGION_8_9                                                               0x1370
7053 #define mmCM4_CM_BLNDGAM_RAMB_REGION_8_9_BASE_IDX                                                      2
7054 #define mmCM4_CM_BLNDGAM_RAMB_REGION_10_11                                                             0x1371
7055 #define mmCM4_CM_BLNDGAM_RAMB_REGION_10_11_BASE_IDX                                                    2
7056 #define mmCM4_CM_BLNDGAM_RAMB_REGION_12_13                                                             0x1372
7057 #define mmCM4_CM_BLNDGAM_RAMB_REGION_12_13_BASE_IDX                                                    2
7058 #define mmCM4_CM_BLNDGAM_RAMB_REGION_14_15                                                             0x1373
7059 #define mmCM4_CM_BLNDGAM_RAMB_REGION_14_15_BASE_IDX                                                    2
7060 #define mmCM4_CM_BLNDGAM_RAMB_REGION_16_17                                                             0x1374
7061 #define mmCM4_CM_BLNDGAM_RAMB_REGION_16_17_BASE_IDX                                                    2
7062 #define mmCM4_CM_BLNDGAM_RAMB_REGION_18_19                                                             0x1375
7063 #define mmCM4_CM_BLNDGAM_RAMB_REGION_18_19_BASE_IDX                                                    2
7064 #define mmCM4_CM_BLNDGAM_RAMB_REGION_20_21                                                             0x1376
7065 #define mmCM4_CM_BLNDGAM_RAMB_REGION_20_21_BASE_IDX                                                    2
7066 #define mmCM4_CM_BLNDGAM_RAMB_REGION_22_23                                                             0x1377
7067 #define mmCM4_CM_BLNDGAM_RAMB_REGION_22_23_BASE_IDX                                                    2
7068 #define mmCM4_CM_BLNDGAM_RAMB_REGION_24_25                                                             0x1378
7069 #define mmCM4_CM_BLNDGAM_RAMB_REGION_24_25_BASE_IDX                                                    2
7070 #define mmCM4_CM_BLNDGAM_RAMB_REGION_26_27                                                             0x1379
7071 #define mmCM4_CM_BLNDGAM_RAMB_REGION_26_27_BASE_IDX                                                    2
7072 #define mmCM4_CM_BLNDGAM_RAMB_REGION_28_29                                                             0x137a
7073 #define mmCM4_CM_BLNDGAM_RAMB_REGION_28_29_BASE_IDX                                                    2
7074 #define mmCM4_CM_BLNDGAM_RAMB_REGION_30_31                                                             0x137b
7075 #define mmCM4_CM_BLNDGAM_RAMB_REGION_30_31_BASE_IDX                                                    2
7076 #define mmCM4_CM_BLNDGAM_RAMB_REGION_32_33                                                             0x137c
7077 #define mmCM4_CM_BLNDGAM_RAMB_REGION_32_33_BASE_IDX                                                    2
7078 #define mmCM4_CM_HDR_MULT_COEF                                                                         0x137d
7079 #define mmCM4_CM_HDR_MULT_COEF_BASE_IDX                                                                2
7080 #define mmCM4_CM_MEM_PWR_CTRL                                                                          0x137e
7081 #define mmCM4_CM_MEM_PWR_CTRL_BASE_IDX                                                                 2
7082 #define mmCM4_CM_MEM_PWR_STATUS                                                                        0x137f
7083 #define mmCM4_CM_MEM_PWR_STATUS_BASE_IDX                                                               2
7084 #define mmCM4_CM_DEALPHA                                                                               0x1381
7085 #define mmCM4_CM_DEALPHA_BASE_IDX                                                                      2
7086 #define mmCM4_CM_COEF_FORMAT                                                                           0x1382
7087 #define mmCM4_CM_COEF_FORMAT_BASE_IDX                                                                  2
7088 #define mmCM4_CM_SHAPER_CONTROL                                                                        0x1383
7089 #define mmCM4_CM_SHAPER_CONTROL_BASE_IDX                                                               2
7090 #define mmCM4_CM_SHAPER_OFFSET_R                                                                       0x1384
7091 #define mmCM4_CM_SHAPER_OFFSET_R_BASE_IDX                                                              2
7092 #define mmCM4_CM_SHAPER_OFFSET_G                                                                       0x1385
7093 #define mmCM4_CM_SHAPER_OFFSET_G_BASE_IDX                                                              2
7094 #define mmCM4_CM_SHAPER_OFFSET_B                                                                       0x1386
7095 #define mmCM4_CM_SHAPER_OFFSET_B_BASE_IDX                                                              2
7096 #define mmCM4_CM_SHAPER_SCALE_R                                                                        0x1387
7097 #define mmCM4_CM_SHAPER_SCALE_R_BASE_IDX                                                               2
7098 #define mmCM4_CM_SHAPER_SCALE_G_B                                                                      0x1388
7099 #define mmCM4_CM_SHAPER_SCALE_G_B_BASE_IDX                                                             2
7100 #define mmCM4_CM_SHAPER_LUT_INDEX                                                                      0x1389
7101 #define mmCM4_CM_SHAPER_LUT_INDEX_BASE_IDX                                                             2
7102 #define mmCM4_CM_SHAPER_LUT_DATA                                                                       0x138a
7103 #define mmCM4_CM_SHAPER_LUT_DATA_BASE_IDX                                                              2
7104 #define mmCM4_CM_SHAPER_LUT_WRITE_EN_MASK                                                              0x138b
7105 #define mmCM4_CM_SHAPER_LUT_WRITE_EN_MASK_BASE_IDX                                                     2
7106 #define mmCM4_CM_SHAPER_RAMA_START_CNTL_B                                                              0x138c
7107 #define mmCM4_CM_SHAPER_RAMA_START_CNTL_B_BASE_IDX                                                     2
7108 #define mmCM4_CM_SHAPER_RAMA_START_CNTL_G                                                              0x138d
7109 #define mmCM4_CM_SHAPER_RAMA_START_CNTL_G_BASE_IDX                                                     2
7110 #define mmCM4_CM_SHAPER_RAMA_START_CNTL_R                                                              0x138e
7111 #define mmCM4_CM_SHAPER_RAMA_START_CNTL_R_BASE_IDX                                                     2
7112 #define mmCM4_CM_SHAPER_RAMA_END_CNTL_B                                                                0x138f
7113 #define mmCM4_CM_SHAPER_RAMA_END_CNTL_B_BASE_IDX                                                       2
7114 #define mmCM4_CM_SHAPER_RAMA_END_CNTL_G                                                                0x1390
7115 #define mmCM4_CM_SHAPER_RAMA_END_CNTL_G_BASE_IDX                                                       2
7116 #define mmCM4_CM_SHAPER_RAMA_END_CNTL_R                                                                0x1391
7117 #define mmCM4_CM_SHAPER_RAMA_END_CNTL_R_BASE_IDX                                                       2
7118 #define mmCM4_CM_SHAPER_RAMA_REGION_0_1                                                                0x1392
7119 #define mmCM4_CM_SHAPER_RAMA_REGION_0_1_BASE_IDX                                                       2
7120 #define mmCM4_CM_SHAPER_RAMA_REGION_2_3                                                                0x1393
7121 #define mmCM4_CM_SHAPER_RAMA_REGION_2_3_BASE_IDX                                                       2
7122 #define mmCM4_CM_SHAPER_RAMA_REGION_4_5                                                                0x1394
7123 #define mmCM4_CM_SHAPER_RAMA_REGION_4_5_BASE_IDX                                                       2
7124 #define mmCM4_CM_SHAPER_RAMA_REGION_6_7                                                                0x1395
7125 #define mmCM4_CM_SHAPER_RAMA_REGION_6_7_BASE_IDX                                                       2
7126 #define mmCM4_CM_SHAPER_RAMA_REGION_8_9                                                                0x1396
7127 #define mmCM4_CM_SHAPER_RAMA_REGION_8_9_BASE_IDX                                                       2
7128 #define mmCM4_CM_SHAPER_RAMA_REGION_10_11                                                              0x1397
7129 #define mmCM4_CM_SHAPER_RAMA_REGION_10_11_BASE_IDX                                                     2
7130 #define mmCM4_CM_SHAPER_RAMA_REGION_12_13                                                              0x1398
7131 #define mmCM4_CM_SHAPER_RAMA_REGION_12_13_BASE_IDX                                                     2
7132 #define mmCM4_CM_SHAPER_RAMA_REGION_14_15                                                              0x1399
7133 #define mmCM4_CM_SHAPER_RAMA_REGION_14_15_BASE_IDX                                                     2
7134 #define mmCM4_CM_SHAPER_RAMA_REGION_16_17                                                              0x139a
7135 #define mmCM4_CM_SHAPER_RAMA_REGION_16_17_BASE_IDX                                                     2
7136 #define mmCM4_CM_SHAPER_RAMA_REGION_18_19                                                              0x139b
7137 #define mmCM4_CM_SHAPER_RAMA_REGION_18_19_BASE_IDX                                                     2
7138 #define mmCM4_CM_SHAPER_RAMA_REGION_20_21                                                              0x139c
7139 #define mmCM4_CM_SHAPER_RAMA_REGION_20_21_BASE_IDX                                                     2
7140 #define mmCM4_CM_SHAPER_RAMA_REGION_22_23                                                              0x139d
7141 #define mmCM4_CM_SHAPER_RAMA_REGION_22_23_BASE_IDX                                                     2
7142 #define mmCM4_CM_SHAPER_RAMA_REGION_24_25                                                              0x139e
7143 #define mmCM4_CM_SHAPER_RAMA_REGION_24_25_BASE_IDX                                                     2
7144 #define mmCM4_CM_SHAPER_RAMA_REGION_26_27                                                              0x139f
7145 #define mmCM4_CM_SHAPER_RAMA_REGION_26_27_BASE_IDX                                                     2
7146 #define mmCM4_CM_SHAPER_RAMA_REGION_28_29                                                              0x13a0
7147 #define mmCM4_CM_SHAPER_RAMA_REGION_28_29_BASE_IDX                                                     2
7148 #define mmCM4_CM_SHAPER_RAMA_REGION_30_31                                                              0x13a1
7149 #define mmCM4_CM_SHAPER_RAMA_REGION_30_31_BASE_IDX                                                     2
7150 #define mmCM4_CM_SHAPER_RAMA_REGION_32_33                                                              0x13a2
7151 #define mmCM4_CM_SHAPER_RAMA_REGION_32_33_BASE_IDX                                                     2
7152 #define mmCM4_CM_SHAPER_RAMB_START_CNTL_B                                                              0x13a3
7153 #define mmCM4_CM_SHAPER_RAMB_START_CNTL_B_BASE_IDX                                                     2
7154 #define mmCM4_CM_SHAPER_RAMB_START_CNTL_G                                                              0x13a4
7155 #define mmCM4_CM_SHAPER_RAMB_START_CNTL_G_BASE_IDX                                                     2
7156 #define mmCM4_CM_SHAPER_RAMB_START_CNTL_R                                                              0x13a5
7157 #define mmCM4_CM_SHAPER_RAMB_START_CNTL_R_BASE_IDX                                                     2
7158 #define mmCM4_CM_SHAPER_RAMB_END_CNTL_B                                                                0x13a6
7159 #define mmCM4_CM_SHAPER_RAMB_END_CNTL_B_BASE_IDX                                                       2
7160 #define mmCM4_CM_SHAPER_RAMB_END_CNTL_G                                                                0x13a7
7161 #define mmCM4_CM_SHAPER_RAMB_END_CNTL_G_BASE_IDX                                                       2
7162 #define mmCM4_CM_SHAPER_RAMB_END_CNTL_R                                                                0x13a8
7163 #define mmCM4_CM_SHAPER_RAMB_END_CNTL_R_BASE_IDX                                                       2
7164 #define mmCM4_CM_SHAPER_RAMB_REGION_0_1                                                                0x13a9
7165 #define mmCM4_CM_SHAPER_RAMB_REGION_0_1_BASE_IDX                                                       2
7166 #define mmCM4_CM_SHAPER_RAMB_REGION_2_3                                                                0x13aa
7167 #define mmCM4_CM_SHAPER_RAMB_REGION_2_3_BASE_IDX                                                       2
7168 #define mmCM4_CM_SHAPER_RAMB_REGION_4_5                                                                0x13ab
7169 #define mmCM4_CM_SHAPER_RAMB_REGION_4_5_BASE_IDX                                                       2
7170 #define mmCM4_CM_SHAPER_RAMB_REGION_6_7                                                                0x13ac
7171 #define mmCM4_CM_SHAPER_RAMB_REGION_6_7_BASE_IDX                                                       2
7172 #define mmCM4_CM_SHAPER_RAMB_REGION_8_9                                                                0x13ad
7173 #define mmCM4_CM_SHAPER_RAMB_REGION_8_9_BASE_IDX                                                       2
7174 #define mmCM4_CM_SHAPER_RAMB_REGION_10_11                                                              0x13ae
7175 #define mmCM4_CM_SHAPER_RAMB_REGION_10_11_BASE_IDX                                                     2
7176 #define mmCM4_CM_SHAPER_RAMB_REGION_12_13                                                              0x13af
7177 #define mmCM4_CM_SHAPER_RAMB_REGION_12_13_BASE_IDX                                                     2
7178 #define mmCM4_CM_SHAPER_RAMB_REGION_14_15                                                              0x13b0
7179 #define mmCM4_CM_SHAPER_RAMB_REGION_14_15_BASE_IDX                                                     2
7180 #define mmCM4_CM_SHAPER_RAMB_REGION_16_17                                                              0x13b1
7181 #define mmCM4_CM_SHAPER_RAMB_REGION_16_17_BASE_IDX                                                     2
7182 #define mmCM4_CM_SHAPER_RAMB_REGION_18_19                                                              0x13b2
7183 #define mmCM4_CM_SHAPER_RAMB_REGION_18_19_BASE_IDX                                                     2
7184 #define mmCM4_CM_SHAPER_RAMB_REGION_20_21                                                              0x13b3
7185 #define mmCM4_CM_SHAPER_RAMB_REGION_20_21_BASE_IDX                                                     2
7186 #define mmCM4_CM_SHAPER_RAMB_REGION_22_23                                                              0x13b4
7187 #define mmCM4_CM_SHAPER_RAMB_REGION_22_23_BASE_IDX                                                     2
7188 #define mmCM4_CM_SHAPER_RAMB_REGION_24_25                                                              0x13b5
7189 #define mmCM4_CM_SHAPER_RAMB_REGION_24_25_BASE_IDX                                                     2
7190 #define mmCM4_CM_SHAPER_RAMB_REGION_26_27                                                              0x13b6
7191 #define mmCM4_CM_SHAPER_RAMB_REGION_26_27_BASE_IDX                                                     2
7192 #define mmCM4_CM_SHAPER_RAMB_REGION_28_29                                                              0x13b7
7193 #define mmCM4_CM_SHAPER_RAMB_REGION_28_29_BASE_IDX                                                     2
7194 #define mmCM4_CM_SHAPER_RAMB_REGION_30_31                                                              0x13b8
7195 #define mmCM4_CM_SHAPER_RAMB_REGION_30_31_BASE_IDX                                                     2
7196 #define mmCM4_CM_SHAPER_RAMB_REGION_32_33                                                              0x13b9
7197 #define mmCM4_CM_SHAPER_RAMB_REGION_32_33_BASE_IDX                                                     2
7198 #define mmCM4_CM_MEM_PWR_CTRL2                                                                         0x13ba
7199 #define mmCM4_CM_MEM_PWR_CTRL2_BASE_IDX                                                                2
7200 #define mmCM4_CM_MEM_PWR_STATUS2                                                                       0x13bb
7201 #define mmCM4_CM_MEM_PWR_STATUS2_BASE_IDX                                                              2
7202 #define mmCM4_CM_3DLUT_MODE                                                                            0x13bc
7203 #define mmCM4_CM_3DLUT_MODE_BASE_IDX                                                                   2
7204 #define mmCM4_CM_3DLUT_INDEX                                                                           0x13bd
7205 #define mmCM4_CM_3DLUT_INDEX_BASE_IDX                                                                  2
7206 #define mmCM4_CM_3DLUT_DATA                                                                            0x13be
7207 #define mmCM4_CM_3DLUT_DATA_BASE_IDX                                                                   2
7208 #define mmCM4_CM_3DLUT_DATA_30BIT                                                                      0x13bf
7209 #define mmCM4_CM_3DLUT_DATA_30BIT_BASE_IDX                                                             2
7210 #define mmCM4_CM_3DLUT_READ_WRITE_CONTROL                                                              0x13c0
7211 #define mmCM4_CM_3DLUT_READ_WRITE_CONTROL_BASE_IDX                                                     2
7212 #define mmCM4_CM_3DLUT_OUT_NORM_FACTOR                                                                 0x13c1
7213 #define mmCM4_CM_3DLUT_OUT_NORM_FACTOR_BASE_IDX                                                        2
7214 #define mmCM4_CM_3DLUT_OUT_OFFSET_R                                                                    0x13c2
7215 #define mmCM4_CM_3DLUT_OUT_OFFSET_R_BASE_IDX                                                           2
7216 #define mmCM4_CM_3DLUT_OUT_OFFSET_G                                                                    0x13c3
7217 #define mmCM4_CM_3DLUT_OUT_OFFSET_G_BASE_IDX                                                           2
7218 #define mmCM4_CM_3DLUT_OUT_OFFSET_B                                                                    0x13c4
7219 #define mmCM4_CM_3DLUT_OUT_OFFSET_B_BASE_IDX                                                           2
7220 
7221 
7222 // addressBlock: dce_dc_dpp4_dispdec_dpp_dcperfmon_dc_perfmon_dispdec
7223 // base address: 0x4f40
7224 #define mmDC_PERFMON15_PERFCOUNTER_CNTL                                                                0x13d0
7225 #define mmDC_PERFMON15_PERFCOUNTER_CNTL_BASE_IDX                                                       2
7226 #define mmDC_PERFMON15_PERFCOUNTER_CNTL2                                                               0x13d1
7227 #define mmDC_PERFMON15_PERFCOUNTER_CNTL2_BASE_IDX                                                      2
7228 #define mmDC_PERFMON15_PERFCOUNTER_STATE                                                               0x13d2
7229 #define mmDC_PERFMON15_PERFCOUNTER_STATE_BASE_IDX                                                      2
7230 #define mmDC_PERFMON15_PERFMON_CNTL                                                                    0x13d3
7231 #define mmDC_PERFMON15_PERFMON_CNTL_BASE_IDX                                                           2
7232 #define mmDC_PERFMON15_PERFMON_CNTL2                                                                   0x13d4
7233 #define mmDC_PERFMON15_PERFMON_CNTL2_BASE_IDX                                                          2
7234 #define mmDC_PERFMON15_PERFMON_CVALUE_INT_MISC                                                         0x13d5
7235 #define mmDC_PERFMON15_PERFMON_CVALUE_INT_MISC_BASE_IDX                                                2
7236 #define mmDC_PERFMON15_PERFMON_CVALUE_LOW                                                              0x13d6
7237 #define mmDC_PERFMON15_PERFMON_CVALUE_LOW_BASE_IDX                                                     2
7238 #define mmDC_PERFMON15_PERFMON_HI                                                                      0x13d7
7239 #define mmDC_PERFMON15_PERFMON_HI_BASE_IDX                                                             2
7240 #define mmDC_PERFMON15_PERFMON_LOW                                                                     0x13d8
7241 #define mmDC_PERFMON15_PERFMON_LOW_BASE_IDX                                                            2
7242 
7243 
7244 // addressBlock: dce_dc_opp_fmt0_dispdec
7245 // base address: 0x0
7246 #define mmFMT0_FMT_CLAMP_COMPONENT_R                                                                   0x183c
7247 #define mmFMT0_FMT_CLAMP_COMPONENT_R_BASE_IDX                                                          2
7248 #define mmFMT0_FMT_CLAMP_COMPONENT_G                                                                   0x183d
7249 #define mmFMT0_FMT_CLAMP_COMPONENT_G_BASE_IDX                                                          2
7250 #define mmFMT0_FMT_CLAMP_COMPONENT_B                                                                   0x183e
7251 #define mmFMT0_FMT_CLAMP_COMPONENT_B_BASE_IDX                                                          2
7252 #define mmFMT0_FMT_DYNAMIC_EXP_CNTL                                                                    0x183f
7253 #define mmFMT0_FMT_DYNAMIC_EXP_CNTL_BASE_IDX                                                           2
7254 #define mmFMT0_FMT_CONTROL                                                                             0x1840
7255 #define mmFMT0_FMT_CONTROL_BASE_IDX                                                                    2
7256 #define mmFMT0_FMT_BIT_DEPTH_CONTROL                                                                   0x1841
7257 #define mmFMT0_FMT_BIT_DEPTH_CONTROL_BASE_IDX                                                          2
7258 #define mmFMT0_FMT_DITHER_RAND_R_SEED                                                                  0x1842
7259 #define mmFMT0_FMT_DITHER_RAND_R_SEED_BASE_IDX                                                         2
7260 #define mmFMT0_FMT_DITHER_RAND_G_SEED                                                                  0x1843
7261 #define mmFMT0_FMT_DITHER_RAND_G_SEED_BASE_IDX                                                         2
7262 #define mmFMT0_FMT_DITHER_RAND_B_SEED                                                                  0x1844
7263 #define mmFMT0_FMT_DITHER_RAND_B_SEED_BASE_IDX                                                         2
7264 #define mmFMT0_FMT_CLAMP_CNTL                                                                          0x1845
7265 #define mmFMT0_FMT_CLAMP_CNTL_BASE_IDX                                                                 2
7266 #define mmFMT0_FMT_SIDE_BY_SIDE_STEREO_CONTROL                                                         0x1846
7267 #define mmFMT0_FMT_SIDE_BY_SIDE_STEREO_CONTROL_BASE_IDX                                                2
7268 #define mmFMT0_FMT_MAP420_MEMORY_CONTROL                                                               0x1847
7269 #define mmFMT0_FMT_MAP420_MEMORY_CONTROL_BASE_IDX                                                      2
7270 #define mmFMT0_FMT_422_CONTROL                                                                         0x1849
7271 #define mmFMT0_FMT_422_CONTROL_BASE_IDX                                                                2
7272 
7273 
7274 // addressBlock: dce_dc_opp_dpg0_dispdec
7275 // base address: 0x0
7276 #define mmDPG0_DPG_CONTROL                                                                             0x1854
7277 #define mmDPG0_DPG_CONTROL_BASE_IDX                                                                    2
7278 #define mmDPG0_DPG_RAMP_CONTROL                                                                        0x1855
7279 #define mmDPG0_DPG_RAMP_CONTROL_BASE_IDX                                                               2
7280 #define mmDPG0_DPG_DIMENSIONS                                                                          0x1856
7281 #define mmDPG0_DPG_DIMENSIONS_BASE_IDX                                                                 2
7282 #define mmDPG0_DPG_COLOUR_R_CR                                                                         0x1857
7283 #define mmDPG0_DPG_COLOUR_R_CR_BASE_IDX                                                                2
7284 #define mmDPG0_DPG_COLOUR_G_Y                                                                          0x1858
7285 #define mmDPG0_DPG_COLOUR_G_Y_BASE_IDX                                                                 2
7286 #define mmDPG0_DPG_COLOUR_B_CB                                                                         0x1859
7287 #define mmDPG0_DPG_COLOUR_B_CB_BASE_IDX                                                                2
7288 #define mmDPG0_DPG_OFFSET_SEGMENT                                                                      0x185a
7289 #define mmDPG0_DPG_OFFSET_SEGMENT_BASE_IDX                                                             2
7290 #define mmDPG0_DPG_STATUS                                                                              0x185b
7291 #define mmDPG0_DPG_STATUS_BASE_IDX                                                                     2
7292 
7293 
7294 // addressBlock: dce_dc_opp_oppbuf0_dispdec
7295 // base address: 0x0
7296 #define mmOPPBUF0_OPPBUF_CONTROL                                                                       0x1884
7297 #define mmOPPBUF0_OPPBUF_CONTROL_BASE_IDX                                                              2
7298 #define mmOPPBUF0_OPPBUF_3D_PARAMETERS_0                                                               0x1885
7299 #define mmOPPBUF0_OPPBUF_3D_PARAMETERS_0_BASE_IDX                                                      2
7300 #define mmOPPBUF0_OPPBUF_3D_PARAMETERS_1                                                               0x1886
7301 #define mmOPPBUF0_OPPBUF_3D_PARAMETERS_1_BASE_IDX                                                      2
7302 #define mmOPPBUF0_OPPBUF_CONTROL1                                                                      0x1889
7303 #define mmOPPBUF0_OPPBUF_CONTROL1_BASE_IDX                                                             2
7304 
7305 
7306 // addressBlock: dce_dc_opp_opp_pipe0_dispdec
7307 // base address: 0x0
7308 #define mmOPP_PIPE0_OPP_PIPE_CONTROL                                                                   0x188c
7309 #define mmOPP_PIPE0_OPP_PIPE_CONTROL_BASE_IDX                                                          2
7310 
7311 
7312 // addressBlock: dce_dc_opp_opp_pipe_crc0_dispdec
7313 // base address: 0x0
7314 #define mmOPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL                                                           0x1891
7315 #define mmOPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL_BASE_IDX                                                  2
7316 #define mmOPP_PIPE_CRC0_OPP_PIPE_CRC_MASK                                                              0x1892
7317 #define mmOPP_PIPE_CRC0_OPP_PIPE_CRC_MASK_BASE_IDX                                                     2
7318 #define mmOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT0                                                           0x1893
7319 #define mmOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT0_BASE_IDX                                                  2
7320 #define mmOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT1                                                           0x1894
7321 #define mmOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT1_BASE_IDX                                                  2
7322 #define mmOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT2                                                           0x1895
7323 #define mmOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT2_BASE_IDX                                                  2
7324 
7325 
7326 // addressBlock: dce_dc_opp_fmt1_dispdec
7327 // base address: 0x168
7328 #define mmFMT1_FMT_CLAMP_COMPONENT_R                                                                   0x1896
7329 #define mmFMT1_FMT_CLAMP_COMPONENT_R_BASE_IDX                                                          2
7330 #define mmFMT1_FMT_CLAMP_COMPONENT_G                                                                   0x1897
7331 #define mmFMT1_FMT_CLAMP_COMPONENT_G_BASE_IDX                                                          2
7332 #define mmFMT1_FMT_CLAMP_COMPONENT_B                                                                   0x1898
7333 #define mmFMT1_FMT_CLAMP_COMPONENT_B_BASE_IDX                                                          2
7334 #define mmFMT1_FMT_DYNAMIC_EXP_CNTL                                                                    0x1899
7335 #define mmFMT1_FMT_DYNAMIC_EXP_CNTL_BASE_IDX                                                           2
7336 #define mmFMT1_FMT_CONTROL                                                                             0x189a
7337 #define mmFMT1_FMT_CONTROL_BASE_IDX                                                                    2
7338 #define mmFMT1_FMT_BIT_DEPTH_CONTROL                                                                   0x189b
7339 #define mmFMT1_FMT_BIT_DEPTH_CONTROL_BASE_IDX                                                          2
7340 #define mmFMT1_FMT_DITHER_RAND_R_SEED                                                                  0x189c
7341 #define mmFMT1_FMT_DITHER_RAND_R_SEED_BASE_IDX                                                         2
7342 #define mmFMT1_FMT_DITHER_RAND_G_SEED                                                                  0x189d
7343 #define mmFMT1_FMT_DITHER_RAND_G_SEED_BASE_IDX                                                         2
7344 #define mmFMT1_FMT_DITHER_RAND_B_SEED                                                                  0x189e
7345 #define mmFMT1_FMT_DITHER_RAND_B_SEED_BASE_IDX                                                         2
7346 #define mmFMT1_FMT_CLAMP_CNTL                                                                          0x189f
7347 #define mmFMT1_FMT_CLAMP_CNTL_BASE_IDX                                                                 2
7348 #define mmFMT1_FMT_SIDE_BY_SIDE_STEREO_CONTROL                                                         0x18a0
7349 #define mmFMT1_FMT_SIDE_BY_SIDE_STEREO_CONTROL_BASE_IDX                                                2
7350 #define mmFMT1_FMT_MAP420_MEMORY_CONTROL                                                               0x18a1
7351 #define mmFMT1_FMT_MAP420_MEMORY_CONTROL_BASE_IDX                                                      2
7352 #define mmFMT1_FMT_422_CONTROL                                                                         0x18a3
7353 #define mmFMT1_FMT_422_CONTROL_BASE_IDX                                                                2
7354 
7355 
7356 // addressBlock: dce_dc_opp_dpg1_dispdec
7357 // base address: 0x168
7358 #define mmDPG1_DPG_CONTROL                                                                             0x18ae
7359 #define mmDPG1_DPG_CONTROL_BASE_IDX                                                                    2
7360 #define mmDPG1_DPG_RAMP_CONTROL                                                                        0x18af
7361 #define mmDPG1_DPG_RAMP_CONTROL_BASE_IDX                                                               2
7362 #define mmDPG1_DPG_DIMENSIONS                                                                          0x18b0
7363 #define mmDPG1_DPG_DIMENSIONS_BASE_IDX                                                                 2
7364 #define mmDPG1_DPG_COLOUR_R_CR                                                                         0x18b1
7365 #define mmDPG1_DPG_COLOUR_R_CR_BASE_IDX                                                                2
7366 #define mmDPG1_DPG_COLOUR_G_Y                                                                          0x18b2
7367 #define mmDPG1_DPG_COLOUR_G_Y_BASE_IDX                                                                 2
7368 #define mmDPG1_DPG_COLOUR_B_CB                                                                         0x18b3
7369 #define mmDPG1_DPG_COLOUR_B_CB_BASE_IDX                                                                2
7370 #define mmDPG1_DPG_OFFSET_SEGMENT                                                                      0x18b4
7371 #define mmDPG1_DPG_OFFSET_SEGMENT_BASE_IDX                                                             2
7372 #define mmDPG1_DPG_STATUS                                                                              0x18b5
7373 #define mmDPG1_DPG_STATUS_BASE_IDX                                                                     2
7374 
7375 
7376 // addressBlock: dce_dc_opp_oppbuf1_dispdec
7377 // base address: 0x168
7378 #define mmOPPBUF1_OPPBUF_CONTROL                                                                       0x18de
7379 #define mmOPPBUF1_OPPBUF_CONTROL_BASE_IDX                                                              2
7380 #define mmOPPBUF1_OPPBUF_3D_PARAMETERS_0                                                               0x18df
7381 #define mmOPPBUF1_OPPBUF_3D_PARAMETERS_0_BASE_IDX                                                      2
7382 #define mmOPPBUF1_OPPBUF_3D_PARAMETERS_1                                                               0x18e0
7383 #define mmOPPBUF1_OPPBUF_3D_PARAMETERS_1_BASE_IDX                                                      2
7384 #define mmOPPBUF1_OPPBUF_CONTROL1                                                                      0x18e3
7385 #define mmOPPBUF1_OPPBUF_CONTROL1_BASE_IDX                                                             2
7386 
7387 
7388 // addressBlock: dce_dc_opp_opp_pipe1_dispdec
7389 // base address: 0x168
7390 #define mmOPP_PIPE1_OPP_PIPE_CONTROL                                                                   0x18e6
7391 #define mmOPP_PIPE1_OPP_PIPE_CONTROL_BASE_IDX                                                          2
7392 
7393 
7394 // addressBlock: dce_dc_opp_opp_pipe_crc1_dispdec
7395 // base address: 0x168
7396 #define mmOPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL                                                           0x18eb
7397 #define mmOPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL_BASE_IDX                                                  2
7398 #define mmOPP_PIPE_CRC1_OPP_PIPE_CRC_MASK                                                              0x18ec
7399 #define mmOPP_PIPE_CRC1_OPP_PIPE_CRC_MASK_BASE_IDX                                                     2
7400 #define mmOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT0                                                           0x18ed
7401 #define mmOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT0_BASE_IDX                                                  2
7402 #define mmOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT1                                                           0x18ee
7403 #define mmOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT1_BASE_IDX                                                  2
7404 #define mmOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT2                                                           0x18ef
7405 #define mmOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT2_BASE_IDX                                                  2
7406 
7407 
7408 // addressBlock: dce_dc_opp_fmt2_dispdec
7409 // base address: 0x2d0
7410 #define mmFMT2_FMT_CLAMP_COMPONENT_R                                                                   0x18f0
7411 #define mmFMT2_FMT_CLAMP_COMPONENT_R_BASE_IDX                                                          2
7412 #define mmFMT2_FMT_CLAMP_COMPONENT_G                                                                   0x18f1
7413 #define mmFMT2_FMT_CLAMP_COMPONENT_G_BASE_IDX                                                          2
7414 #define mmFMT2_FMT_CLAMP_COMPONENT_B                                                                   0x18f2
7415 #define mmFMT2_FMT_CLAMP_COMPONENT_B_BASE_IDX                                                          2
7416 #define mmFMT2_FMT_DYNAMIC_EXP_CNTL                                                                    0x18f3
7417 #define mmFMT2_FMT_DYNAMIC_EXP_CNTL_BASE_IDX                                                           2
7418 #define mmFMT2_FMT_CONTROL                                                                             0x18f4
7419 #define mmFMT2_FMT_CONTROL_BASE_IDX                                                                    2
7420 #define mmFMT2_FMT_BIT_DEPTH_CONTROL                                                                   0x18f5
7421 #define mmFMT2_FMT_BIT_DEPTH_CONTROL_BASE_IDX                                                          2
7422 #define mmFMT2_FMT_DITHER_RAND_R_SEED                                                                  0x18f6
7423 #define mmFMT2_FMT_DITHER_RAND_R_SEED_BASE_IDX                                                         2
7424 #define mmFMT2_FMT_DITHER_RAND_G_SEED                                                                  0x18f7
7425 #define mmFMT2_FMT_DITHER_RAND_G_SEED_BASE_IDX                                                         2
7426 #define mmFMT2_FMT_DITHER_RAND_B_SEED                                                                  0x18f8
7427 #define mmFMT2_FMT_DITHER_RAND_B_SEED_BASE_IDX                                                         2
7428 #define mmFMT2_FMT_CLAMP_CNTL                                                                          0x18f9
7429 #define mmFMT2_FMT_CLAMP_CNTL_BASE_IDX                                                                 2
7430 #define mmFMT2_FMT_SIDE_BY_SIDE_STEREO_CONTROL                                                         0x18fa
7431 #define mmFMT2_FMT_SIDE_BY_SIDE_STEREO_CONTROL_BASE_IDX                                                2
7432 #define mmFMT2_FMT_MAP420_MEMORY_CONTROL                                                               0x18fb
7433 #define mmFMT2_FMT_MAP420_MEMORY_CONTROL_BASE_IDX                                                      2
7434 #define mmFMT2_FMT_422_CONTROL                                                                         0x18fd
7435 #define mmFMT2_FMT_422_CONTROL_BASE_IDX                                                                2
7436 
7437 
7438 // addressBlock: dce_dc_opp_dpg2_dispdec
7439 // base address: 0x2d0
7440 #define mmDPG2_DPG_CONTROL                                                                             0x1908
7441 #define mmDPG2_DPG_CONTROL_BASE_IDX                                                                    2
7442 #define mmDPG2_DPG_RAMP_CONTROL                                                                        0x1909
7443 #define mmDPG2_DPG_RAMP_CONTROL_BASE_IDX                                                               2
7444 #define mmDPG2_DPG_DIMENSIONS                                                                          0x190a
7445 #define mmDPG2_DPG_DIMENSIONS_BASE_IDX                                                                 2
7446 #define mmDPG2_DPG_COLOUR_R_CR                                                                         0x190b
7447 #define mmDPG2_DPG_COLOUR_R_CR_BASE_IDX                                                                2
7448 #define mmDPG2_DPG_COLOUR_G_Y                                                                          0x190c
7449 #define mmDPG2_DPG_COLOUR_G_Y_BASE_IDX                                                                 2
7450 #define mmDPG2_DPG_COLOUR_B_CB                                                                         0x190d
7451 #define mmDPG2_DPG_COLOUR_B_CB_BASE_IDX                                                                2
7452 #define mmDPG2_DPG_OFFSET_SEGMENT                                                                      0x190e
7453 #define mmDPG2_DPG_OFFSET_SEGMENT_BASE_IDX                                                             2
7454 #define mmDPG2_DPG_STATUS                                                                              0x190f
7455 #define mmDPG2_DPG_STATUS_BASE_IDX                                                                     2
7456 
7457 
7458 // addressBlock: dce_dc_opp_oppbuf2_dispdec
7459 // base address: 0x2d0
7460 #define mmOPPBUF2_OPPBUF_CONTROL                                                                       0x1938
7461 #define mmOPPBUF2_OPPBUF_CONTROL_BASE_IDX                                                              2
7462 #define mmOPPBUF2_OPPBUF_3D_PARAMETERS_0                                                               0x1939
7463 #define mmOPPBUF2_OPPBUF_3D_PARAMETERS_0_BASE_IDX                                                      2
7464 #define mmOPPBUF2_OPPBUF_3D_PARAMETERS_1                                                               0x193a
7465 #define mmOPPBUF2_OPPBUF_3D_PARAMETERS_1_BASE_IDX                                                      2
7466 #define mmOPPBUF2_OPPBUF_CONTROL1                                                                      0x193d
7467 #define mmOPPBUF2_OPPBUF_CONTROL1_BASE_IDX                                                             2
7468 
7469 
7470 // addressBlock: dce_dc_opp_opp_pipe2_dispdec
7471 // base address: 0x2d0
7472 #define mmOPP_PIPE2_OPP_PIPE_CONTROL                                                                   0x1940
7473 #define mmOPP_PIPE2_OPP_PIPE_CONTROL_BASE_IDX                                                          2
7474 
7475 
7476 // addressBlock: dce_dc_opp_opp_pipe_crc2_dispdec
7477 // base address: 0x2d0
7478 #define mmOPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL                                                           0x1945
7479 #define mmOPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL_BASE_IDX                                                  2
7480 #define mmOPP_PIPE_CRC2_OPP_PIPE_CRC_MASK                                                              0x1946
7481 #define mmOPP_PIPE_CRC2_OPP_PIPE_CRC_MASK_BASE_IDX                                                     2
7482 #define mmOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT0                                                           0x1947
7483 #define mmOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT0_BASE_IDX                                                  2
7484 #define mmOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT1                                                           0x1948
7485 #define mmOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT1_BASE_IDX                                                  2
7486 #define mmOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT2                                                           0x1949
7487 #define mmOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT2_BASE_IDX                                                  2
7488 
7489 
7490 // addressBlock: dce_dc_opp_fmt3_dispdec
7491 // base address: 0x438
7492 #define mmFMT3_FMT_CLAMP_COMPONENT_R                                                                   0x194a
7493 #define mmFMT3_FMT_CLAMP_COMPONENT_R_BASE_IDX                                                          2
7494 #define mmFMT3_FMT_CLAMP_COMPONENT_G                                                                   0x194b
7495 #define mmFMT3_FMT_CLAMP_COMPONENT_G_BASE_IDX                                                          2
7496 #define mmFMT3_FMT_CLAMP_COMPONENT_B                                                                   0x194c
7497 #define mmFMT3_FMT_CLAMP_COMPONENT_B_BASE_IDX                                                          2
7498 #define mmFMT3_FMT_DYNAMIC_EXP_CNTL                                                                    0x194d
7499 #define mmFMT3_FMT_DYNAMIC_EXP_CNTL_BASE_IDX                                                           2
7500 #define mmFMT3_FMT_CONTROL                                                                             0x194e
7501 #define mmFMT3_FMT_CONTROL_BASE_IDX                                                                    2
7502 #define mmFMT3_FMT_BIT_DEPTH_CONTROL                                                                   0x194f
7503 #define mmFMT3_FMT_BIT_DEPTH_CONTROL_BASE_IDX                                                          2
7504 #define mmFMT3_FMT_DITHER_RAND_R_SEED                                                                  0x1950
7505 #define mmFMT3_FMT_DITHER_RAND_R_SEED_BASE_IDX                                                         2
7506 #define mmFMT3_FMT_DITHER_RAND_G_SEED                                                                  0x1951
7507 #define mmFMT3_FMT_DITHER_RAND_G_SEED_BASE_IDX                                                         2
7508 #define mmFMT3_FMT_DITHER_RAND_B_SEED                                                                  0x1952
7509 #define mmFMT3_FMT_DITHER_RAND_B_SEED_BASE_IDX                                                         2
7510 #define mmFMT3_FMT_CLAMP_CNTL                                                                          0x1953
7511 #define mmFMT3_FMT_CLAMP_CNTL_BASE_IDX                                                                 2
7512 #define mmFMT3_FMT_SIDE_BY_SIDE_STEREO_CONTROL                                                         0x1954
7513 #define mmFMT3_FMT_SIDE_BY_SIDE_STEREO_CONTROL_BASE_IDX                                                2
7514 #define mmFMT3_FMT_MAP420_MEMORY_CONTROL                                                               0x1955
7515 #define mmFMT3_FMT_MAP420_MEMORY_CONTROL_BASE_IDX                                                      2
7516 #define mmFMT3_FMT_422_CONTROL                                                                         0x1957
7517 #define mmFMT3_FMT_422_CONTROL_BASE_IDX                                                                2
7518 
7519 
7520 // addressBlock: dce_dc_opp_dpg3_dispdec
7521 // base address: 0x438
7522 #define mmDPG3_DPG_CONTROL                                                                             0x1962
7523 #define mmDPG3_DPG_CONTROL_BASE_IDX                                                                    2
7524 #define mmDPG3_DPG_RAMP_CONTROL                                                                        0x1963
7525 #define mmDPG3_DPG_RAMP_CONTROL_BASE_IDX                                                               2
7526 #define mmDPG3_DPG_DIMENSIONS                                                                          0x1964
7527 #define mmDPG3_DPG_DIMENSIONS_BASE_IDX                                                                 2
7528 #define mmDPG3_DPG_COLOUR_R_CR                                                                         0x1965
7529 #define mmDPG3_DPG_COLOUR_R_CR_BASE_IDX                                                                2
7530 #define mmDPG3_DPG_COLOUR_G_Y                                                                          0x1966
7531 #define mmDPG3_DPG_COLOUR_G_Y_BASE_IDX                                                                 2
7532 #define mmDPG3_DPG_COLOUR_B_CB                                                                         0x1967
7533 #define mmDPG3_DPG_COLOUR_B_CB_BASE_IDX                                                                2
7534 #define mmDPG3_DPG_OFFSET_SEGMENT                                                                      0x1968
7535 #define mmDPG3_DPG_OFFSET_SEGMENT_BASE_IDX                                                             2
7536 #define mmDPG3_DPG_STATUS                                                                              0x1969
7537 #define mmDPG3_DPG_STATUS_BASE_IDX                                                                     2
7538 
7539 
7540 // addressBlock: dce_dc_opp_oppbuf3_dispdec
7541 // base address: 0x438
7542 #define mmOPPBUF3_OPPBUF_CONTROL                                                                       0x1992
7543 #define mmOPPBUF3_OPPBUF_CONTROL_BASE_IDX                                                              2
7544 #define mmOPPBUF3_OPPBUF_3D_PARAMETERS_0                                                               0x1993
7545 #define mmOPPBUF3_OPPBUF_3D_PARAMETERS_0_BASE_IDX                                                      2
7546 #define mmOPPBUF3_OPPBUF_3D_PARAMETERS_1                                                               0x1994
7547 #define mmOPPBUF3_OPPBUF_3D_PARAMETERS_1_BASE_IDX                                                      2
7548 #define mmOPPBUF3_OPPBUF_CONTROL1                                                                      0x1997
7549 #define mmOPPBUF3_OPPBUF_CONTROL1_BASE_IDX                                                             2
7550 
7551 
7552 // addressBlock: dce_dc_opp_opp_pipe3_dispdec
7553 // base address: 0x438
7554 #define mmOPP_PIPE3_OPP_PIPE_CONTROL                                                                   0x199a
7555 #define mmOPP_PIPE3_OPP_PIPE_CONTROL_BASE_IDX                                                          2
7556 
7557 // addressBlock: dce_dc_opp_opp_pipe_crc3_dispdec
7558 // base address: 0x438
7559 #define mmOPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL                                                           0x199f
7560 #define mmOPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL_BASE_IDX                                                  2
7561 #define mmOPP_PIPE_CRC3_OPP_PIPE_CRC_MASK                                                              0x19a0
7562 #define mmOPP_PIPE_CRC3_OPP_PIPE_CRC_MASK_BASE_IDX                                                     2
7563 #define mmOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT0                                                           0x19a1
7564 #define mmOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT0_BASE_IDX                                                  2
7565 #define mmOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT1                                                           0x19a2
7566 #define mmOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT1_BASE_IDX                                                  2
7567 #define mmOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT2                                                           0x19a3
7568 #define mmOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT2_BASE_IDX                                                  2
7569 
7570 
7571 // addressBlock: dce_dc_opp_fmt4_dispdec
7572 // base address: 0x5a0
7573 #define mmFMT4_FMT_CLAMP_COMPONENT_R                                                                   0x19a4
7574 #define mmFMT4_FMT_CLAMP_COMPONENT_R_BASE_IDX                                                          2
7575 #define mmFMT4_FMT_CLAMP_COMPONENT_G                                                                   0x19a5
7576 #define mmFMT4_FMT_CLAMP_COMPONENT_G_BASE_IDX                                                          2
7577 #define mmFMT4_FMT_CLAMP_COMPONENT_B                                                                   0x19a6
7578 #define mmFMT4_FMT_CLAMP_COMPONENT_B_BASE_IDX                                                          2
7579 #define mmFMT4_FMT_DYNAMIC_EXP_CNTL                                                                    0x19a7
7580 #define mmFMT4_FMT_DYNAMIC_EXP_CNTL_BASE_IDX                                                           2
7581 #define mmFMT4_FMT_CONTROL                                                                             0x19a8
7582 #define mmFMT4_FMT_CONTROL_BASE_IDX                                                                    2
7583 #define mmFMT4_FMT_BIT_DEPTH_CONTROL                                                                   0x19a9
7584 #define mmFMT4_FMT_BIT_DEPTH_CONTROL_BASE_IDX                                                          2
7585 #define mmFMT4_FMT_DITHER_RAND_R_SEED                                                                  0x19aa
7586 #define mmFMT4_FMT_DITHER_RAND_R_SEED_BASE_IDX                                                         2
7587 #define mmFMT4_FMT_DITHER_RAND_G_SEED                                                                  0x19ab
7588 #define mmFMT4_FMT_DITHER_RAND_G_SEED_BASE_IDX                                                         2
7589 #define mmFMT4_FMT_DITHER_RAND_B_SEED                                                                  0x19ac
7590 #define mmFMT4_FMT_DITHER_RAND_B_SEED_BASE_IDX                                                         2
7591 #define mmFMT4_FMT_CLAMP_CNTL                                                                          0x19ad
7592 #define mmFMT4_FMT_CLAMP_CNTL_BASE_IDX                                                                 2
7593 #define mmFMT4_FMT_SIDE_BY_SIDE_STEREO_CONTROL                                                         0x19ae
7594 #define mmFMT4_FMT_SIDE_BY_SIDE_STEREO_CONTROL_BASE_IDX                                                2
7595 #define mmFMT4_FMT_MAP420_MEMORY_CONTROL                                                               0x19af
7596 #define mmFMT4_FMT_MAP420_MEMORY_CONTROL_BASE_IDX                                                      2
7597 #define mmFMT4_FMT_422_CONTROL                                                                         0x19b1
7598 #define mmFMT4_FMT_422_CONTROL_BASE_IDX                                                                2
7599 
7600 
7601 // addressBlock: dce_dc_opp_dpg4_dispdec
7602 // base address: 0x5a0
7603 #define mmDPG4_DPG_CONTROL                                                                             0x19bc
7604 #define mmDPG4_DPG_CONTROL_BASE_IDX                                                                    2
7605 #define mmDPG4_DPG_RAMP_CONTROL                                                                        0x19bd
7606 #define mmDPG4_DPG_RAMP_CONTROL_BASE_IDX                                                               2
7607 #define mmDPG4_DPG_DIMENSIONS                                                                          0x19be
7608 #define mmDPG4_DPG_DIMENSIONS_BASE_IDX                                                                 2
7609 #define mmDPG4_DPG_COLOUR_R_CR                                                                         0x19bf
7610 #define mmDPG4_DPG_COLOUR_R_CR_BASE_IDX                                                                2
7611 #define mmDPG4_DPG_COLOUR_G_Y                                                                          0x19c0
7612 #define mmDPG4_DPG_COLOUR_G_Y_BASE_IDX                                                                 2
7613 #define mmDPG4_DPG_COLOUR_B_CB                                                                         0x19c1
7614 #define mmDPG4_DPG_COLOUR_B_CB_BASE_IDX                                                                2
7615 #define mmDPG4_DPG_OFFSET_SEGMENT                                                                      0x19c2
7616 #define mmDPG4_DPG_OFFSET_SEGMENT_BASE_IDX                                                             2
7617 #define mmDPG4_DPG_STATUS                                                                              0x19c3
7618 #define mmDPG4_DPG_STATUS_BASE_IDX                                                                     2
7619 
7620 
7621 // addressBlock: dce_dc_opp_oppbuf4_dispdec
7622 // base address: 0x5a0
7623 #define mmOPPBUF4_OPPBUF_CONTROL                                                                       0x19ec
7624 #define mmOPPBUF4_OPPBUF_CONTROL_BASE_IDX                                                              2
7625 #define mmOPPBUF4_OPPBUF_3D_PARAMETERS_0                                                               0x19ed
7626 #define mmOPPBUF4_OPPBUF_3D_PARAMETERS_0_BASE_IDX                                                      2
7627 #define mmOPPBUF4_OPPBUF_3D_PARAMETERS_1                                                               0x19ee
7628 #define mmOPPBUF4_OPPBUF_3D_PARAMETERS_1_BASE_IDX                                                      2
7629 #define mmOPPBUF4_OPPBUF_CONTROL1                                                                      0x19f1
7630 #define mmOPPBUF4_OPPBUF_CONTROL1_BASE_IDX                                                             2
7631 
7632 
7633 // addressBlock: dce_dc_opp_opp_pipe4_dispdec
7634 // base address: 0x5a0
7635 #define mmOPP_PIPE4_OPP_PIPE_CONTROL                                                                   0x19f4
7636 #define mmOPP_PIPE4_OPP_PIPE_CONTROL_BASE_IDX                                                          2
7637 
7638 
7639 // addressBlock: dce_dc_opp_opp_pipe_crc4_dispdec
7640 // base address: 0x5a0
7641 #define mmOPP_PIPE_CRC4_OPP_PIPE_CRC_CONTROL                                                           0x19f9
7642 #define mmOPP_PIPE_CRC4_OPP_PIPE_CRC_CONTROL_BASE_IDX                                                  2
7643 #define mmOPP_PIPE_CRC4_OPP_PIPE_CRC_MASK                                                              0x19fa
7644 #define mmOPP_PIPE_CRC4_OPP_PIPE_CRC_MASK_BASE_IDX                                                     2
7645 #define mmOPP_PIPE_CRC4_OPP_PIPE_CRC_RESULT0                                                           0x19fb
7646 #define mmOPP_PIPE_CRC4_OPP_PIPE_CRC_RESULT0_BASE_IDX                                                  2
7647 #define mmOPP_PIPE_CRC4_OPP_PIPE_CRC_RESULT1                                                           0x19fc
7648 #define mmOPP_PIPE_CRC4_OPP_PIPE_CRC_RESULT1_BASE_IDX                                                  2
7649 #define mmOPP_PIPE_CRC4_OPP_PIPE_CRC_RESULT2                                                           0x19fd
7650 #define mmOPP_PIPE_CRC4_OPP_PIPE_CRC_RESULT2_BASE_IDX                                                  2
7651 
7652 
7653 // addressBlock: dce_dc_opp_opp_top_dispdec
7654 // base address: 0x0
7655 #define mmOPP_TOP_CLK_CONTROL                                                                          0x1a5e
7656 #define mmOPP_TOP_CLK_CONTROL_BASE_IDX                                                                 2
7657 #define mmOPP_ABM_CONTROL                                                                              0x1a60
7658 #define mmOPP_ABM_CONTROL_BASE_IDX                                                                     2
7659 
7660 
7661 // addressBlock: dce_dc_opp_dscrm0_dispdec
7662 // base address: 0x0
7663 #define mmDSCRM0_DSCRM_DSC_FORWARD_CONFIG                                                              0x1a64
7664 #define mmDSCRM0_DSCRM_DSC_FORWARD_CONFIG_BASE_IDX                                                     2
7665 
7666 
7667 // addressBlock: dce_dc_opp_dscrm1_dispdec
7668 // base address: 0x4
7669 #define mmDSCRM1_DSCRM_DSC_FORWARD_CONFIG                                                              0x1a65
7670 #define mmDSCRM1_DSCRM_DSC_FORWARD_CONFIG_BASE_IDX                                                     2
7671 
7672 
7673 // addressBlock: dce_dc_opp_dscrm2_dispdec
7674 // base address: 0x8
7675 #define mmDSCRM2_DSCRM_DSC_FORWARD_CONFIG                                                              0x1a66
7676 #define mmDSCRM2_DSCRM_DSC_FORWARD_CONFIG_BASE_IDX                                                     2
7677 
7678 
7679 // addressBlock: dce_dc_opp_dscrm3_dispdec
7680 // base address: 0xc
7681 #define mmDSCRM3_DSCRM_DSC_FORWARD_CONFIG                                                              0x1a67
7682 #define mmDSCRM3_DSCRM_DSC_FORWARD_CONFIG_BASE_IDX                                                     2
7683 
7684 
7685 // addressBlock: dce_dc_opp_dscrm4_dispdec
7686 // base address: 0x10
7687 #define mmDSCRM4_DSCRM_DSC_FORWARD_CONFIG                                                              0x1a68
7688 #define mmDSCRM4_DSCRM_DSC_FORWARD_CONFIG_BASE_IDX                                                     2
7689 
7690 
7691 // addressBlock: dce_dc_opp_opp_dcperfmon_dc_perfmon_dispdec
7692 // base address: 0x6af8
7693 #define mmDC_PERFMON16_PERFCOUNTER_CNTL                                                                0x1abe
7694 #define mmDC_PERFMON16_PERFCOUNTER_CNTL_BASE_IDX                                                       2
7695 #define mmDC_PERFMON16_PERFCOUNTER_CNTL2                                                               0x1abf
7696 #define mmDC_PERFMON16_PERFCOUNTER_CNTL2_BASE_IDX                                                      2
7697 #define mmDC_PERFMON16_PERFCOUNTER_STATE                                                               0x1ac0
7698 #define mmDC_PERFMON16_PERFCOUNTER_STATE_BASE_IDX                                                      2
7699 #define mmDC_PERFMON16_PERFMON_CNTL                                                                    0x1ac1
7700 #define mmDC_PERFMON16_PERFMON_CNTL_BASE_IDX                                                           2
7701 #define mmDC_PERFMON16_PERFMON_CNTL2                                                                   0x1ac2
7702 #define mmDC_PERFMON16_PERFMON_CNTL2_BASE_IDX                                                          2
7703 #define mmDC_PERFMON16_PERFMON_CVALUE_INT_MISC                                                         0x1ac3
7704 #define mmDC_PERFMON16_PERFMON_CVALUE_INT_MISC_BASE_IDX                                                2
7705 #define mmDC_PERFMON16_PERFMON_CVALUE_LOW                                                              0x1ac4
7706 #define mmDC_PERFMON16_PERFMON_CVALUE_LOW_BASE_IDX                                                     2
7707 #define mmDC_PERFMON16_PERFMON_HI                                                                      0x1ac5
7708 #define mmDC_PERFMON16_PERFMON_HI_BASE_IDX                                                             2
7709 #define mmDC_PERFMON16_PERFMON_LOW                                                                     0x1ac6
7710 #define mmDC_PERFMON16_PERFMON_LOW_BASE_IDX                                                            2
7711 
7712 
7713 // addressBlock: dce_dc_optc_odm0_dispdec
7714 // base address: 0x0
7715 #define mmODM0_OPTC_INPUT_GLOBAL_CONTROL                                                               0x1aca
7716 #define mmODM0_OPTC_INPUT_GLOBAL_CONTROL_BASE_IDX                                                      2
7717 #define mmODM0_OPTC_DATA_SOURCE_SELECT                                                                 0x1acb
7718 #define mmODM0_OPTC_DATA_SOURCE_SELECT_BASE_IDX                                                        2
7719 #define mmODM0_OPTC_DATA_FORMAT_CONTROL                                                                0x1acc
7720 #define mmODM0_OPTC_DATA_FORMAT_CONTROL_BASE_IDX                                                       2
7721 #define mmODM0_OPTC_BYTES_PER_PIXEL                                                                    0x1acd
7722 #define mmODM0_OPTC_BYTES_PER_PIXEL_BASE_IDX                                                           2
7723 #define mmODM0_OPTC_WIDTH_CONTROL                                                                      0x1ace
7724 #define mmODM0_OPTC_WIDTH_CONTROL_BASE_IDX                                                             2
7725 #define mmODM0_OPTC_INPUT_CLOCK_CONTROL                                                                0x1acf
7726 #define mmODM0_OPTC_INPUT_CLOCK_CONTROL_BASE_IDX                                                       2
7727 #define mmODM0_OPTC_MEMORY_CONFIG                                                                      0x1ad0
7728 #define mmODM0_OPTC_MEMORY_CONFIG_BASE_IDX                                                             2
7729 #define mmODM0_OPTC_INPUT_SPARE_REGISTER                                                               0x1ad1
7730 #define mmODM0_OPTC_INPUT_SPARE_REGISTER_BASE_IDX                                                      2
7731 
7732 
7733 // addressBlock: dce_dc_optc_odm1_dispdec
7734 // base address: 0x40
7735 #define mmODM1_OPTC_INPUT_GLOBAL_CONTROL                                                               0x1ada
7736 #define mmODM1_OPTC_INPUT_GLOBAL_CONTROL_BASE_IDX                                                      2
7737 #define mmODM1_OPTC_DATA_SOURCE_SELECT                                                                 0x1adb
7738 #define mmODM1_OPTC_DATA_SOURCE_SELECT_BASE_IDX                                                        2
7739 #define mmODM1_OPTC_DATA_FORMAT_CONTROL                                                                0x1adc
7740 #define mmODM1_OPTC_DATA_FORMAT_CONTROL_BASE_IDX                                                       2
7741 #define mmODM1_OPTC_BYTES_PER_PIXEL                                                                    0x1add
7742 #define mmODM1_OPTC_BYTES_PER_PIXEL_BASE_IDX                                                           2
7743 #define mmODM1_OPTC_WIDTH_CONTROL                                                                      0x1ade
7744 #define mmODM1_OPTC_WIDTH_CONTROL_BASE_IDX                                                             2
7745 #define mmODM1_OPTC_INPUT_CLOCK_CONTROL                                                                0x1adf
7746 #define mmODM1_OPTC_INPUT_CLOCK_CONTROL_BASE_IDX                                                       2
7747 #define mmODM1_OPTC_MEMORY_CONFIG                                                                      0x1ae0
7748 #define mmODM1_OPTC_MEMORY_CONFIG_BASE_IDX                                                             2
7749 #define mmODM1_OPTC_INPUT_SPARE_REGISTER                                                               0x1ae1
7750 #define mmODM1_OPTC_INPUT_SPARE_REGISTER_BASE_IDX                                                      2
7751 
7752 
7753 // addressBlock: dce_dc_optc_odm2_dispdec
7754 // base address: 0x80
7755 #define mmODM2_OPTC_INPUT_GLOBAL_CONTROL                                                               0x1aea
7756 #define mmODM2_OPTC_INPUT_GLOBAL_CONTROL_BASE_IDX                                                      2
7757 #define mmODM2_OPTC_DATA_SOURCE_SELECT                                                                 0x1aeb
7758 #define mmODM2_OPTC_DATA_SOURCE_SELECT_BASE_IDX                                                        2
7759 #define mmODM2_OPTC_DATA_FORMAT_CONTROL                                                                0x1aec
7760 #define mmODM2_OPTC_DATA_FORMAT_CONTROL_BASE_IDX                                                       2
7761 #define mmODM2_OPTC_BYTES_PER_PIXEL                                                                    0x1aed
7762 #define mmODM2_OPTC_BYTES_PER_PIXEL_BASE_IDX                                                           2
7763 #define mmODM2_OPTC_WIDTH_CONTROL                                                                      0x1aee
7764 #define mmODM2_OPTC_WIDTH_CONTROL_BASE_IDX                                                             2
7765 #define mmODM2_OPTC_INPUT_CLOCK_CONTROL                                                                0x1aef
7766 #define mmODM2_OPTC_INPUT_CLOCK_CONTROL_BASE_IDX                                                       2
7767 #define mmODM2_OPTC_MEMORY_CONFIG                                                                      0x1af0
7768 #define mmODM2_OPTC_MEMORY_CONFIG_BASE_IDX                                                             2
7769 #define mmODM2_OPTC_INPUT_SPARE_REGISTER                                                               0x1af1
7770 #define mmODM2_OPTC_INPUT_SPARE_REGISTER_BASE_IDX                                                      2
7771 
7772 
7773 // addressBlock: dce_dc_optc_odm3_dispdec
7774 // base address: 0xc0
7775 #define mmODM3_OPTC_INPUT_GLOBAL_CONTROL                                                               0x1afa
7776 #define mmODM3_OPTC_INPUT_GLOBAL_CONTROL_BASE_IDX                                                      2
7777 #define mmODM3_OPTC_DATA_SOURCE_SELECT                                                                 0x1afb
7778 #define mmODM3_OPTC_DATA_SOURCE_SELECT_BASE_IDX                                                        2
7779 #define mmODM3_OPTC_DATA_FORMAT_CONTROL                                                                0x1afc
7780 #define mmODM3_OPTC_DATA_FORMAT_CONTROL_BASE_IDX                                                       2
7781 #define mmODM3_OPTC_BYTES_PER_PIXEL                                                                    0x1afd
7782 #define mmODM3_OPTC_BYTES_PER_PIXEL_BASE_IDX                                                           2
7783 #define mmODM3_OPTC_WIDTH_CONTROL                                                                      0x1afe
7784 #define mmODM3_OPTC_WIDTH_CONTROL_BASE_IDX                                                             2
7785 #define mmODM3_OPTC_INPUT_CLOCK_CONTROL                                                                0x1aff
7786 #define mmODM3_OPTC_INPUT_CLOCK_CONTROL_BASE_IDX                                                       2
7787 #define mmODM3_OPTC_MEMORY_CONFIG                                                                      0x1b00
7788 #define mmODM3_OPTC_MEMORY_CONFIG_BASE_IDX                                                             2
7789 #define mmODM3_OPTC_INPUT_SPARE_REGISTER                                                               0x1b01
7790 #define mmODM3_OPTC_INPUT_SPARE_REGISTER_BASE_IDX                                                      2
7791 
7792 
7793 // addressBlock: dce_dc_optc_odm4_dispdec
7794 // base address: 0x100
7795 #define mmODM4_OPTC_INPUT_GLOBAL_CONTROL                                                               0x1b0a
7796 #define mmODM4_OPTC_INPUT_GLOBAL_CONTROL_BASE_IDX                                                      2
7797 #define mmODM4_OPTC_DATA_SOURCE_SELECT                                                                 0x1b0b
7798 #define mmODM4_OPTC_DATA_SOURCE_SELECT_BASE_IDX                                                        2
7799 #define mmODM4_OPTC_DATA_FORMAT_CONTROL                                                                0x1b0c
7800 #define mmODM4_OPTC_DATA_FORMAT_CONTROL_BASE_IDX                                                       2
7801 #define mmODM4_OPTC_BYTES_PER_PIXEL                                                                    0x1b0d
7802 #define mmODM4_OPTC_BYTES_PER_PIXEL_BASE_IDX                                                           2
7803 #define mmODM4_OPTC_WIDTH_CONTROL                                                                      0x1b0e
7804 #define mmODM4_OPTC_WIDTH_CONTROL_BASE_IDX                                                             2
7805 #define mmODM4_OPTC_INPUT_CLOCK_CONTROL                                                                0x1b0f
7806 #define mmODM4_OPTC_INPUT_CLOCK_CONTROL_BASE_IDX                                                       2
7807 #define mmODM4_OPTC_MEMORY_CONFIG                                                                      0x1b10
7808 #define mmODM4_OPTC_MEMORY_CONFIG_BASE_IDX                                                             2
7809 #define mmODM4_OPTC_INPUT_SPARE_REGISTER                                                               0x1b11
7810 #define mmODM4_OPTC_INPUT_SPARE_REGISTER_BASE_IDX                                                      2
7811 
7812 
7813 // addressBlock: dce_dc_optc_otg0_dispdec
7814 // base address: 0x0
7815 #define mmOTG0_OTG_H_TOTAL                                                                             0x1b2a
7816 #define mmOTG0_OTG_H_TOTAL_BASE_IDX                                                                    2
7817 #define mmOTG0_OTG_H_BLANK_START_END                                                                   0x1b2b
7818 #define mmOTG0_OTG_H_BLANK_START_END_BASE_IDX                                                          2
7819 #define mmOTG0_OTG_H_SYNC_A                                                                            0x1b2c
7820 #define mmOTG0_OTG_H_SYNC_A_BASE_IDX                                                                   2
7821 #define mmOTG0_OTG_H_SYNC_A_CNTL                                                                       0x1b2d
7822 #define mmOTG0_OTG_H_SYNC_A_CNTL_BASE_IDX                                                              2
7823 #define mmOTG0_OTG_H_TIMING_CNTL                                                                       0x1b2e
7824 #define mmOTG0_OTG_H_TIMING_CNTL_BASE_IDX                                                              2
7825 #define mmOTG0_OTG_V_TOTAL                                                                             0x1b2f
7826 #define mmOTG0_OTG_V_TOTAL_BASE_IDX                                                                    2
7827 #define mmOTG0_OTG_V_TOTAL_MIN                                                                         0x1b30
7828 #define mmOTG0_OTG_V_TOTAL_MIN_BASE_IDX                                                                2
7829 #define mmOTG0_OTG_V_TOTAL_MAX                                                                         0x1b31
7830 #define mmOTG0_OTG_V_TOTAL_MAX_BASE_IDX                                                                2
7831 #define mmOTG0_OTG_V_TOTAL_MID                                                                         0x1b32
7832 #define mmOTG0_OTG_V_TOTAL_MID_BASE_IDX                                                                2
7833 #define mmOTG0_OTG_V_TOTAL_CONTROL                                                                     0x1b33
7834 #define mmOTG0_OTG_V_TOTAL_CONTROL_BASE_IDX                                                            2
7835 #define mmOTG0_OTG_V_TOTAL_INT_STATUS                                                                  0x1b34
7836 #define mmOTG0_OTG_V_TOTAL_INT_STATUS_BASE_IDX                                                         2
7837 #define mmOTG0_OTG_VSYNC_NOM_INT_STATUS                                                                0x1b35
7838 #define mmOTG0_OTG_VSYNC_NOM_INT_STATUS_BASE_IDX                                                       2
7839 #define mmOTG0_OTG_V_BLANK_START_END                                                                   0x1b36
7840 #define mmOTG0_OTG_V_BLANK_START_END_BASE_IDX                                                          2
7841 #define mmOTG0_OTG_V_SYNC_A                                                                            0x1b37
7842 #define mmOTG0_OTG_V_SYNC_A_BASE_IDX                                                                   2
7843 #define mmOTG0_OTG_V_SYNC_A_CNTL                                                                       0x1b38
7844 #define mmOTG0_OTG_V_SYNC_A_CNTL_BASE_IDX                                                              2
7845 #define mmOTG0_OTG_TRIGA_CNTL                                                                          0x1b39
7846 #define mmOTG0_OTG_TRIGA_CNTL_BASE_IDX                                                                 2
7847 #define mmOTG0_OTG_TRIGA_MANUAL_TRIG                                                                   0x1b3a
7848 #define mmOTG0_OTG_TRIGA_MANUAL_TRIG_BASE_IDX                                                          2
7849 #define mmOTG0_OTG_TRIGB_CNTL                                                                          0x1b3b
7850 #define mmOTG0_OTG_TRIGB_CNTL_BASE_IDX                                                                 2
7851 #define mmOTG0_OTG_TRIGB_MANUAL_TRIG                                                                   0x1b3c
7852 #define mmOTG0_OTG_TRIGB_MANUAL_TRIG_BASE_IDX                                                          2
7853 #define mmOTG0_OTG_FORCE_COUNT_NOW_CNTL                                                                0x1b3d
7854 #define mmOTG0_OTG_FORCE_COUNT_NOW_CNTL_BASE_IDX                                                       2
7855 #define mmOTG0_OTG_FLOW_CONTROL                                                                        0x1b3e
7856 #define mmOTG0_OTG_FLOW_CONTROL_BASE_IDX                                                               2
7857 #define mmOTG0_OTG_STEREO_FORCE_NEXT_EYE                                                               0x1b3f
7858 #define mmOTG0_OTG_STEREO_FORCE_NEXT_EYE_BASE_IDX                                                      2
7859 #define mmOTG0_OTG_CONTROL                                                                             0x1b41
7860 #define mmOTG0_OTG_CONTROL_BASE_IDX                                                                    2
7861 #define mmOTG0_OTG_INTERLACE_CONTROL                                                                   0x1b44
7862 #define mmOTG0_OTG_INTERLACE_CONTROL_BASE_IDX                                                          2
7863 #define mmOTG0_OTG_INTERLACE_STATUS                                                                    0x1b45
7864 #define mmOTG0_OTG_INTERLACE_STATUS_BASE_IDX                                                           2
7865 #define mmOTG0_OTG_PIXEL_DATA_READBACK0                                                                0x1b47
7866 #define mmOTG0_OTG_PIXEL_DATA_READBACK0_BASE_IDX                                                       2
7867 #define mmOTG0_OTG_PIXEL_DATA_READBACK1                                                                0x1b48
7868 #define mmOTG0_OTG_PIXEL_DATA_READBACK1_BASE_IDX                                                       2
7869 #define mmOTG0_OTG_STATUS                                                                              0x1b49
7870 #define mmOTG0_OTG_STATUS_BASE_IDX                                                                     2
7871 #define mmOTG0_OTG_STATUS_POSITION                                                                     0x1b4a
7872 #define mmOTG0_OTG_STATUS_POSITION_BASE_IDX                                                            2
7873 #define mmOTG0_OTG_NOM_VERT_POSITION                                                                   0x1b4b
7874 #define mmOTG0_OTG_NOM_VERT_POSITION_BASE_IDX                                                          2
7875 #define mmOTG0_OTG_STATUS_FRAME_COUNT                                                                  0x1b4c
7876 #define mmOTG0_OTG_STATUS_FRAME_COUNT_BASE_IDX                                                         2
7877 #define mmOTG0_OTG_STATUS_VF_COUNT                                                                     0x1b4d
7878 #define mmOTG0_OTG_STATUS_VF_COUNT_BASE_IDX                                                            2
7879 #define mmOTG0_OTG_STATUS_HV_COUNT                                                                     0x1b4e
7880 #define mmOTG0_OTG_STATUS_HV_COUNT_BASE_IDX                                                            2
7881 #define mmOTG0_OTG_COUNT_CONTROL                                                                       0x1b4f
7882 #define mmOTG0_OTG_COUNT_CONTROL_BASE_IDX                                                              2
7883 #define mmOTG0_OTG_COUNT_RESET                                                                         0x1b50
7884 #define mmOTG0_OTG_COUNT_RESET_BASE_IDX                                                                2
7885 #define mmOTG0_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE                                                        0x1b51
7886 #define mmOTG0_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX                                               2
7887 #define mmOTG0_OTG_VERT_SYNC_CONTROL                                                                   0x1b52
7888 #define mmOTG0_OTG_VERT_SYNC_CONTROL_BASE_IDX                                                          2
7889 #define mmOTG0_OTG_STEREO_STATUS                                                                       0x1b53
7890 #define mmOTG0_OTG_STEREO_STATUS_BASE_IDX                                                              2
7891 #define mmOTG0_OTG_STEREO_CONTROL                                                                      0x1b54
7892 #define mmOTG0_OTG_STEREO_CONTROL_BASE_IDX                                                             2
7893 #define mmOTG0_OTG_SNAPSHOT_STATUS                                                                     0x1b55
7894 #define mmOTG0_OTG_SNAPSHOT_STATUS_BASE_IDX                                                            2
7895 #define mmOTG0_OTG_SNAPSHOT_CONTROL                                                                    0x1b56
7896 #define mmOTG0_OTG_SNAPSHOT_CONTROL_BASE_IDX                                                           2
7897 #define mmOTG0_OTG_SNAPSHOT_POSITION                                                                   0x1b57
7898 #define mmOTG0_OTG_SNAPSHOT_POSITION_BASE_IDX                                                          2
7899 #define mmOTG0_OTG_SNAPSHOT_FRAME                                                                      0x1b58
7900 #define mmOTG0_OTG_SNAPSHOT_FRAME_BASE_IDX                                                             2
7901 #define mmOTG0_OTG_INTERRUPT_CONTROL                                                                   0x1b59
7902 #define mmOTG0_OTG_INTERRUPT_CONTROL_BASE_IDX                                                          2
7903 #define mmOTG0_OTG_UPDATE_LOCK                                                                         0x1b5a
7904 #define mmOTG0_OTG_UPDATE_LOCK_BASE_IDX                                                                2
7905 #define mmOTG0_OTG_DOUBLE_BUFFER_CONTROL                                                               0x1b5b
7906 #define mmOTG0_OTG_DOUBLE_BUFFER_CONTROL_BASE_IDX                                                      2
7907 #define mmOTG0_OTG_MASTER_EN                                                                           0x1b5c
7908 #define mmOTG0_OTG_MASTER_EN_BASE_IDX                                                                  2
7909 #define mmOTG0_OTG_BLANK_DATA_COLOR                                                                    0x1b5e
7910 #define mmOTG0_OTG_BLANK_DATA_COLOR_BASE_IDX                                                           2
7911 #define mmOTG0_OTG_BLANK_DATA_COLOR_EXT                                                                0x1b5f
7912 #define mmOTG0_OTG_BLANK_DATA_COLOR_EXT_BASE_IDX                                                       2
7913 #define mmOTG0_OTG_VERTICAL_INTERRUPT0_POSITION                                                        0x1b62
7914 #define mmOTG0_OTG_VERTICAL_INTERRUPT0_POSITION_BASE_IDX                                               2
7915 #define mmOTG0_OTG_VERTICAL_INTERRUPT0_CONTROL                                                         0x1b63
7916 #define mmOTG0_OTG_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX                                                2
7917 #define mmOTG0_OTG_VERTICAL_INTERRUPT1_POSITION                                                        0x1b64
7918 #define mmOTG0_OTG_VERTICAL_INTERRUPT1_POSITION_BASE_IDX                                               2
7919 #define mmOTG0_OTG_VERTICAL_INTERRUPT1_CONTROL                                                         0x1b65
7920 #define mmOTG0_OTG_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX                                                2
7921 #define mmOTG0_OTG_VERTICAL_INTERRUPT2_POSITION                                                        0x1b66
7922 #define mmOTG0_OTG_VERTICAL_INTERRUPT2_POSITION_BASE_IDX                                               2
7923 #define mmOTG0_OTG_VERTICAL_INTERRUPT2_CONTROL                                                         0x1b67
7924 #define mmOTG0_OTG_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX                                                2
7925 #define mmOTG0_OTG_CRC_CNTL                                                                            0x1b68
7926 #define mmOTG0_OTG_CRC_CNTL_BASE_IDX                                                                   2
7927 #define mmOTG0_OTG_CRC_CNTL2                                                                           0x1b69
7928 #define mmOTG0_OTG_CRC_CNTL2_BASE_IDX                                                                  2
7929 #define mmOTG0_OTG_CRC0_WINDOWA_X_CONTROL                                                              0x1b6a
7930 #define mmOTG0_OTG_CRC0_WINDOWA_X_CONTROL_BASE_IDX                                                     2
7931 #define mmOTG0_OTG_CRC0_WINDOWA_Y_CONTROL                                                              0x1b6b
7932 #define mmOTG0_OTG_CRC0_WINDOWA_Y_CONTROL_BASE_IDX                                                     2
7933 #define mmOTG0_OTG_CRC0_WINDOWB_X_CONTROL                                                              0x1b6c
7934 #define mmOTG0_OTG_CRC0_WINDOWB_X_CONTROL_BASE_IDX                                                     2
7935 #define mmOTG0_OTG_CRC0_WINDOWB_Y_CONTROL                                                              0x1b6d
7936 #define mmOTG0_OTG_CRC0_WINDOWB_Y_CONTROL_BASE_IDX                                                     2
7937 #define mmOTG0_OTG_CRC0_DATA_RG                                                                        0x1b6e
7938 #define mmOTG0_OTG_CRC0_DATA_RG_BASE_IDX                                                               2
7939 #define mmOTG0_OTG_CRC0_DATA_B                                                                         0x1b6f
7940 #define mmOTG0_OTG_CRC0_DATA_B_BASE_IDX                                                                2
7941 #define mmOTG0_OTG_CRC1_WINDOWA_X_CONTROL                                                              0x1b70
7942 #define mmOTG0_OTG_CRC1_WINDOWA_X_CONTROL_BASE_IDX                                                     2
7943 #define mmOTG0_OTG_CRC1_WINDOWA_Y_CONTROL                                                              0x1b71
7944 #define mmOTG0_OTG_CRC1_WINDOWA_Y_CONTROL_BASE_IDX                                                     2
7945 #define mmOTG0_OTG_CRC1_WINDOWB_X_CONTROL                                                              0x1b72
7946 #define mmOTG0_OTG_CRC1_WINDOWB_X_CONTROL_BASE_IDX                                                     2
7947 #define mmOTG0_OTG_CRC1_WINDOWB_Y_CONTROL                                                              0x1b73
7948 #define mmOTG0_OTG_CRC1_WINDOWB_Y_CONTROL_BASE_IDX                                                     2
7949 #define mmOTG0_OTG_CRC1_DATA_RG                                                                        0x1b74
7950 #define mmOTG0_OTG_CRC1_DATA_RG_BASE_IDX                                                               2
7951 #define mmOTG0_OTG_CRC1_DATA_B                                                                         0x1b75
7952 #define mmOTG0_OTG_CRC1_DATA_B_BASE_IDX                                                                2
7953 #define mmOTG0_OTG_CRC2_DATA_RG                                                                        0x1b76
7954 #define mmOTG0_OTG_CRC2_DATA_RG_BASE_IDX                                                               2
7955 #define mmOTG0_OTG_CRC2_DATA_B                                                                         0x1b77
7956 #define mmOTG0_OTG_CRC2_DATA_B_BASE_IDX                                                                2
7957 #define mmOTG0_OTG_CRC3_DATA_RG                                                                        0x1b78
7958 #define mmOTG0_OTG_CRC3_DATA_RG_BASE_IDX                                                               2
7959 #define mmOTG0_OTG_CRC3_DATA_B                                                                         0x1b79
7960 #define mmOTG0_OTG_CRC3_DATA_B_BASE_IDX                                                                2
7961 #define mmOTG0_OTG_CRC_SIG_RED_GREEN_MASK                                                              0x1b7a
7962 #define mmOTG0_OTG_CRC_SIG_RED_GREEN_MASK_BASE_IDX                                                     2
7963 #define mmOTG0_OTG_CRC_SIG_BLUE_CONTROL_MASK                                                           0x1b7b
7964 #define mmOTG0_OTG_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX                                                  2
7965 #define mmOTG0_OTG_STATIC_SCREEN_CONTROL                                                               0x1b82
7966 #define mmOTG0_OTG_STATIC_SCREEN_CONTROL_BASE_IDX                                                      2
7967 #define mmOTG0_OTG_3D_STRUCTURE_CONTROL                                                                0x1b83
7968 #define mmOTG0_OTG_3D_STRUCTURE_CONTROL_BASE_IDX                                                       2
7969 #define mmOTG0_OTG_GSL_VSYNC_GAP                                                                       0x1b84
7970 #define mmOTG0_OTG_GSL_VSYNC_GAP_BASE_IDX                                                              2
7971 #define mmOTG0_OTG_MASTER_UPDATE_MODE                                                                  0x1b85
7972 #define mmOTG0_OTG_MASTER_UPDATE_MODE_BASE_IDX                                                         2
7973 #define mmOTG0_OTG_CLOCK_CONTROL                                                                       0x1b86
7974 #define mmOTG0_OTG_CLOCK_CONTROL_BASE_IDX                                                              2
7975 #define mmOTG0_OTG_VSTARTUP_PARAM                                                                      0x1b87
7976 #define mmOTG0_OTG_VSTARTUP_PARAM_BASE_IDX                                                             2
7977 #define mmOTG0_OTG_VUPDATE_PARAM                                                                       0x1b88
7978 #define mmOTG0_OTG_VUPDATE_PARAM_BASE_IDX                                                              2
7979 #define mmOTG0_OTG_VREADY_PARAM                                                                        0x1b89
7980 #define mmOTG0_OTG_VREADY_PARAM_BASE_IDX                                                               2
7981 #define mmOTG0_OTG_GLOBAL_SYNC_STATUS                                                                  0x1b8a
7982 #define mmOTG0_OTG_GLOBAL_SYNC_STATUS_BASE_IDX                                                         2
7983 #define mmOTG0_OTG_MASTER_UPDATE_LOCK                                                                  0x1b8b
7984 #define mmOTG0_OTG_MASTER_UPDATE_LOCK_BASE_IDX                                                         2
7985 #define mmOTG0_OTG_GSL_CONTROL                                                                         0x1b8c
7986 #define mmOTG0_OTG_GSL_CONTROL_BASE_IDX                                                                2
7987 #define mmOTG0_OTG_GSL_WINDOW_X                                                                        0x1b8d
7988 #define mmOTG0_OTG_GSL_WINDOW_X_BASE_IDX                                                               2
7989 #define mmOTG0_OTG_GSL_WINDOW_Y                                                                        0x1b8e
7990 #define mmOTG0_OTG_GSL_WINDOW_Y_BASE_IDX                                                               2
7991 #define mmOTG0_OTG_VUPDATE_KEEPOUT                                                                     0x1b8f
7992 #define mmOTG0_OTG_VUPDATE_KEEPOUT_BASE_IDX                                                            2
7993 #define mmOTG0_OTG_GLOBAL_CONTROL0                                                                     0x1b90
7994 #define mmOTG0_OTG_GLOBAL_CONTROL0_BASE_IDX                                                            2
7995 #define mmOTG0_OTG_GLOBAL_CONTROL1                                                                     0x1b91
7996 #define mmOTG0_OTG_GLOBAL_CONTROL1_BASE_IDX                                                            2
7997 #define mmOTG0_OTG_GLOBAL_CONTROL2                                                                     0x1b92
7998 #define mmOTG0_OTG_GLOBAL_CONTROL2_BASE_IDX                                                            2
7999 #define mmOTG0_OTG_GLOBAL_CONTROL3                                                                     0x1b93
8000 #define mmOTG0_OTG_GLOBAL_CONTROL3_BASE_IDX                                                            2
8001 #define mmOTG0_OTG_GLOBAL_CONTROL4                                                                     0x1b94
8002 #define mmOTG0_OTG_GLOBAL_CONTROL4_BASE_IDX                                                            2
8003 #define mmOTG0_OTG_TRIG_MANUAL_CONTROL                                                                 0x1b95
8004 #define mmOTG0_OTG_TRIG_MANUAL_CONTROL_BASE_IDX                                                        2
8005 #define mmOTG0_OTG_MANUAL_FLOW_CONTROL                                                                 0x1b96
8006 #define mmOTG0_OTG_MANUAL_FLOW_CONTROL_BASE_IDX                                                        2
8007 #define mmOTG0_OTG_DRR_TIMING_INT_STATUS                                                               0x1b97
8008 #define mmOTG0_OTG_DRR_TIMING_INT_STATUS_BASE_IDX                                                      2
8009 #define mmOTG0_OTG_DRR_V_TOTAL_REACH_RANGE                                                             0x1b98
8010 #define mmOTG0_OTG_DRR_V_TOTAL_REACH_RANGE_BASE_IDX                                                    2
8011 #define mmOTG0_OTG_DRR_V_TOTAL_CHANGE                                                                  0x1b99
8012 #define mmOTG0_OTG_DRR_V_TOTAL_CHANGE_BASE_IDX                                                         2
8013 #define mmOTG0_OTG_DRR_TRIGGER_WINDOW                                                                  0x1b9a
8014 #define mmOTG0_OTG_DRR_TRIGGER_WINDOW_BASE_IDX                                                         2
8015 #define mmOTG0_OTG_DRR_CONTROL                                                                         0x1b9b
8016 #define mmOTG0_OTG_DRR_CONTROL_BASE_IDX                                                                2
8017 #define mmOTG0_OTG_M_CONST_DTO0                                                                        0x1b9c
8018 #define mmOTG0_OTG_M_CONST_DTO0_BASE_IDX                                                               2
8019 #define mmOTG0_OTG_M_CONST_DTO1                                                                        0x1b9d
8020 #define mmOTG0_OTG_M_CONST_DTO1_BASE_IDX                                                               2
8021 #define mmOTG0_OTG_REQUEST_CONTROL                                                                     0x1b9e
8022 #define mmOTG0_OTG_REQUEST_CONTROL_BASE_IDX                                                            2
8023 #define mmOTG0_OTG_DSC_START_POSITION                                                                  0x1b9f
8024 #define mmOTG0_OTG_DSC_START_POSITION_BASE_IDX                                                         2
8025 #define mmOTG0_OTG_PIPE_UPDATE_STATUS                                                                  0x1ba0
8026 #define mmOTG0_OTG_PIPE_UPDATE_STATUS_BASE_IDX                                                         2
8027 #define mmOTG0_OTG_SPARE_REGISTER                                                                      0x1ba2
8028 #define mmOTG0_OTG_SPARE_REGISTER_BASE_IDX                                                             2
8029 
8030 
8031 // addressBlock: dce_dc_optc_otg1_dispdec
8032 // base address: 0x200
8033 #define mmOTG1_OTG_H_TOTAL                                                                             0x1baa
8034 #define mmOTG1_OTG_H_TOTAL_BASE_IDX                                                                    2
8035 #define mmOTG1_OTG_H_BLANK_START_END                                                                   0x1bab
8036 #define mmOTG1_OTG_H_BLANK_START_END_BASE_IDX                                                          2
8037 #define mmOTG1_OTG_H_SYNC_A                                                                            0x1bac
8038 #define mmOTG1_OTG_H_SYNC_A_BASE_IDX                                                                   2
8039 #define mmOTG1_OTG_H_SYNC_A_CNTL                                                                       0x1bad
8040 #define mmOTG1_OTG_H_SYNC_A_CNTL_BASE_IDX                                                              2
8041 #define mmOTG1_OTG_H_TIMING_CNTL                                                                       0x1bae
8042 #define mmOTG1_OTG_H_TIMING_CNTL_BASE_IDX                                                              2
8043 #define mmOTG1_OTG_V_TOTAL                                                                             0x1baf
8044 #define mmOTG1_OTG_V_TOTAL_BASE_IDX                                                                    2
8045 #define mmOTG1_OTG_V_TOTAL_MIN                                                                         0x1bb0
8046 #define mmOTG1_OTG_V_TOTAL_MIN_BASE_IDX                                                                2
8047 #define mmOTG1_OTG_V_TOTAL_MAX                                                                         0x1bb1
8048 #define mmOTG1_OTG_V_TOTAL_MAX_BASE_IDX                                                                2
8049 #define mmOTG1_OTG_V_TOTAL_MID                                                                         0x1bb2
8050 #define mmOTG1_OTG_V_TOTAL_MID_BASE_IDX                                                                2
8051 #define mmOTG1_OTG_V_TOTAL_CONTROL                                                                     0x1bb3
8052 #define mmOTG1_OTG_V_TOTAL_CONTROL_BASE_IDX                                                            2
8053 #define mmOTG1_OTG_V_TOTAL_INT_STATUS                                                                  0x1bb4
8054 #define mmOTG1_OTG_V_TOTAL_INT_STATUS_BASE_IDX                                                         2
8055 #define mmOTG1_OTG_VSYNC_NOM_INT_STATUS                                                                0x1bb5
8056 #define mmOTG1_OTG_VSYNC_NOM_INT_STATUS_BASE_IDX                                                       2
8057 #define mmOTG1_OTG_V_BLANK_START_END                                                                   0x1bb6
8058 #define mmOTG1_OTG_V_BLANK_START_END_BASE_IDX                                                          2
8059 #define mmOTG1_OTG_V_SYNC_A                                                                            0x1bb7
8060 #define mmOTG1_OTG_V_SYNC_A_BASE_IDX                                                                   2
8061 #define mmOTG1_OTG_V_SYNC_A_CNTL                                                                       0x1bb8
8062 #define mmOTG1_OTG_V_SYNC_A_CNTL_BASE_IDX                                                              2
8063 #define mmOTG1_OTG_TRIGA_CNTL                                                                          0x1bb9
8064 #define mmOTG1_OTG_TRIGA_CNTL_BASE_IDX                                                                 2
8065 #define mmOTG1_OTG_TRIGA_MANUAL_TRIG                                                                   0x1bba
8066 #define mmOTG1_OTG_TRIGA_MANUAL_TRIG_BASE_IDX                                                          2
8067 #define mmOTG1_OTG_TRIGB_CNTL                                                                          0x1bbb
8068 #define mmOTG1_OTG_TRIGB_CNTL_BASE_IDX                                                                 2
8069 #define mmOTG1_OTG_TRIGB_MANUAL_TRIG                                                                   0x1bbc
8070 #define mmOTG1_OTG_TRIGB_MANUAL_TRIG_BASE_IDX                                                          2
8071 #define mmOTG1_OTG_FORCE_COUNT_NOW_CNTL                                                                0x1bbd
8072 #define mmOTG1_OTG_FORCE_COUNT_NOW_CNTL_BASE_IDX                                                       2
8073 #define mmOTG1_OTG_FLOW_CONTROL                                                                        0x1bbe
8074 #define mmOTG1_OTG_FLOW_CONTROL_BASE_IDX                                                               2
8075 #define mmOTG1_OTG_STEREO_FORCE_NEXT_EYE                                                               0x1bbf
8076 #define mmOTG1_OTG_STEREO_FORCE_NEXT_EYE_BASE_IDX                                                      2
8077 #define mmOTG1_OTG_CONTROL                                                                             0x1bc1
8078 #define mmOTG1_OTG_CONTROL_BASE_IDX                                                                    2
8079 #define mmOTG1_OTG_INTERLACE_CONTROL                                                                   0x1bc4
8080 #define mmOTG1_OTG_INTERLACE_CONTROL_BASE_IDX                                                          2
8081 #define mmOTG1_OTG_INTERLACE_STATUS                                                                    0x1bc5
8082 #define mmOTG1_OTG_INTERLACE_STATUS_BASE_IDX                                                           2
8083 #define mmOTG1_OTG_PIXEL_DATA_READBACK0                                                                0x1bc7
8084 #define mmOTG1_OTG_PIXEL_DATA_READBACK0_BASE_IDX                                                       2
8085 #define mmOTG1_OTG_PIXEL_DATA_READBACK1                                                                0x1bc8
8086 #define mmOTG1_OTG_PIXEL_DATA_READBACK1_BASE_IDX                                                       2
8087 #define mmOTG1_OTG_STATUS                                                                              0x1bc9
8088 #define mmOTG1_OTG_STATUS_BASE_IDX                                                                     2
8089 #define mmOTG1_OTG_STATUS_POSITION                                                                     0x1bca
8090 #define mmOTG1_OTG_STATUS_POSITION_BASE_IDX                                                            2
8091 #define mmOTG1_OTG_NOM_VERT_POSITION                                                                   0x1bcb
8092 #define mmOTG1_OTG_NOM_VERT_POSITION_BASE_IDX                                                          2
8093 #define mmOTG1_OTG_STATUS_FRAME_COUNT                                                                  0x1bcc
8094 #define mmOTG1_OTG_STATUS_FRAME_COUNT_BASE_IDX                                                         2
8095 #define mmOTG1_OTG_STATUS_VF_COUNT                                                                     0x1bcd
8096 #define mmOTG1_OTG_STATUS_VF_COUNT_BASE_IDX                                                            2
8097 #define mmOTG1_OTG_STATUS_HV_COUNT                                                                     0x1bce
8098 #define mmOTG1_OTG_STATUS_HV_COUNT_BASE_IDX                                                            2
8099 #define mmOTG1_OTG_COUNT_CONTROL                                                                       0x1bcf
8100 #define mmOTG1_OTG_COUNT_CONTROL_BASE_IDX                                                              2
8101 #define mmOTG1_OTG_COUNT_RESET                                                                         0x1bd0
8102 #define mmOTG1_OTG_COUNT_RESET_BASE_IDX                                                                2
8103 #define mmOTG1_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE                                                        0x1bd1
8104 #define mmOTG1_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX                                               2
8105 #define mmOTG1_OTG_VERT_SYNC_CONTROL                                                                   0x1bd2
8106 #define mmOTG1_OTG_VERT_SYNC_CONTROL_BASE_IDX                                                          2
8107 #define mmOTG1_OTG_STEREO_STATUS                                                                       0x1bd3
8108 #define mmOTG1_OTG_STEREO_STATUS_BASE_IDX                                                              2
8109 #define mmOTG1_OTG_STEREO_CONTROL                                                                      0x1bd4
8110 #define mmOTG1_OTG_STEREO_CONTROL_BASE_IDX                                                             2
8111 #define mmOTG1_OTG_SNAPSHOT_STATUS                                                                     0x1bd5
8112 #define mmOTG1_OTG_SNAPSHOT_STATUS_BASE_IDX                                                            2
8113 #define mmOTG1_OTG_SNAPSHOT_CONTROL                                                                    0x1bd6
8114 #define mmOTG1_OTG_SNAPSHOT_CONTROL_BASE_IDX                                                           2
8115 #define mmOTG1_OTG_SNAPSHOT_POSITION                                                                   0x1bd7
8116 #define mmOTG1_OTG_SNAPSHOT_POSITION_BASE_IDX                                                          2
8117 #define mmOTG1_OTG_SNAPSHOT_FRAME                                                                      0x1bd8
8118 #define mmOTG1_OTG_SNAPSHOT_FRAME_BASE_IDX                                                             2
8119 #define mmOTG1_OTG_INTERRUPT_CONTROL                                                                   0x1bd9
8120 #define mmOTG1_OTG_INTERRUPT_CONTROL_BASE_IDX                                                          2
8121 #define mmOTG1_OTG_UPDATE_LOCK                                                                         0x1bda
8122 #define mmOTG1_OTG_UPDATE_LOCK_BASE_IDX                                                                2
8123 #define mmOTG1_OTG_DOUBLE_BUFFER_CONTROL                                                               0x1bdb
8124 #define mmOTG1_OTG_DOUBLE_BUFFER_CONTROL_BASE_IDX                                                      2
8125 #define mmOTG1_OTG_MASTER_EN                                                                           0x1bdc
8126 #define mmOTG1_OTG_MASTER_EN_BASE_IDX                                                                  2
8127 #define mmOTG1_OTG_BLANK_DATA_COLOR                                                                    0x1bde
8128 #define mmOTG1_OTG_BLANK_DATA_COLOR_BASE_IDX                                                           2
8129 #define mmOTG1_OTG_BLANK_DATA_COLOR_EXT                                                                0x1bdf
8130 #define mmOTG1_OTG_BLANK_DATA_COLOR_EXT_BASE_IDX                                                       2
8131 #define mmOTG1_OTG_VERTICAL_INTERRUPT0_POSITION                                                        0x1be2
8132 #define mmOTG1_OTG_VERTICAL_INTERRUPT0_POSITION_BASE_IDX                                               2
8133 #define mmOTG1_OTG_VERTICAL_INTERRUPT0_CONTROL                                                         0x1be3
8134 #define mmOTG1_OTG_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX                                                2
8135 #define mmOTG1_OTG_VERTICAL_INTERRUPT1_POSITION                                                        0x1be4
8136 #define mmOTG1_OTG_VERTICAL_INTERRUPT1_POSITION_BASE_IDX                                               2
8137 #define mmOTG1_OTG_VERTICAL_INTERRUPT1_CONTROL                                                         0x1be5
8138 #define mmOTG1_OTG_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX                                                2
8139 #define mmOTG1_OTG_VERTICAL_INTERRUPT2_POSITION                                                        0x1be6
8140 #define mmOTG1_OTG_VERTICAL_INTERRUPT2_POSITION_BASE_IDX                                               2
8141 #define mmOTG1_OTG_VERTICAL_INTERRUPT2_CONTROL                                                         0x1be7
8142 #define mmOTG1_OTG_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX                                                2
8143 #define mmOTG1_OTG_CRC_CNTL                                                                            0x1be8
8144 #define mmOTG1_OTG_CRC_CNTL_BASE_IDX                                                                   2
8145 #define mmOTG1_OTG_CRC_CNTL2                                                                           0x1be9
8146 #define mmOTG1_OTG_CRC_CNTL2_BASE_IDX                                                                  2
8147 #define mmOTG1_OTG_CRC0_WINDOWA_X_CONTROL                                                              0x1bea
8148 #define mmOTG1_OTG_CRC0_WINDOWA_X_CONTROL_BASE_IDX                                                     2
8149 #define mmOTG1_OTG_CRC0_WINDOWA_Y_CONTROL                                                              0x1beb
8150 #define mmOTG1_OTG_CRC0_WINDOWA_Y_CONTROL_BASE_IDX                                                     2
8151 #define mmOTG1_OTG_CRC0_WINDOWB_X_CONTROL                                                              0x1bec
8152 #define mmOTG1_OTG_CRC0_WINDOWB_X_CONTROL_BASE_IDX                                                     2
8153 #define mmOTG1_OTG_CRC0_WINDOWB_Y_CONTROL                                                              0x1bed
8154 #define mmOTG1_OTG_CRC0_WINDOWB_Y_CONTROL_BASE_IDX                                                     2
8155 #define mmOTG1_OTG_CRC0_DATA_RG                                                                        0x1bee
8156 #define mmOTG1_OTG_CRC0_DATA_RG_BASE_IDX                                                               2
8157 #define mmOTG1_OTG_CRC0_DATA_B                                                                         0x1bef
8158 #define mmOTG1_OTG_CRC0_DATA_B_BASE_IDX                                                                2
8159 #define mmOTG1_OTG_CRC1_WINDOWA_X_CONTROL                                                              0x1bf0
8160 #define mmOTG1_OTG_CRC1_WINDOWA_X_CONTROL_BASE_IDX                                                     2
8161 #define mmOTG1_OTG_CRC1_WINDOWA_Y_CONTROL                                                              0x1bf1
8162 #define mmOTG1_OTG_CRC1_WINDOWA_Y_CONTROL_BASE_IDX                                                     2
8163 #define mmOTG1_OTG_CRC1_WINDOWB_X_CONTROL                                                              0x1bf2
8164 #define mmOTG1_OTG_CRC1_WINDOWB_X_CONTROL_BASE_IDX                                                     2
8165 #define mmOTG1_OTG_CRC1_WINDOWB_Y_CONTROL                                                              0x1bf3
8166 #define mmOTG1_OTG_CRC1_WINDOWB_Y_CONTROL_BASE_IDX                                                     2
8167 #define mmOTG1_OTG_CRC1_DATA_RG                                                                        0x1bf4
8168 #define mmOTG1_OTG_CRC1_DATA_RG_BASE_IDX                                                               2
8169 #define mmOTG1_OTG_CRC1_DATA_B                                                                         0x1bf5
8170 #define mmOTG1_OTG_CRC1_DATA_B_BASE_IDX                                                                2
8171 #define mmOTG1_OTG_CRC2_DATA_RG                                                                        0x1bf6
8172 #define mmOTG1_OTG_CRC2_DATA_RG_BASE_IDX                                                               2
8173 #define mmOTG1_OTG_CRC2_DATA_B                                                                         0x1bf7
8174 #define mmOTG1_OTG_CRC2_DATA_B_BASE_IDX                                                                2
8175 #define mmOTG1_OTG_CRC3_DATA_RG                                                                        0x1bf8
8176 #define mmOTG1_OTG_CRC3_DATA_RG_BASE_IDX                                                               2
8177 #define mmOTG1_OTG_CRC3_DATA_B                                                                         0x1bf9
8178 #define mmOTG1_OTG_CRC3_DATA_B_BASE_IDX                                                                2
8179 #define mmOTG1_OTG_CRC_SIG_RED_GREEN_MASK                                                              0x1bfa
8180 #define mmOTG1_OTG_CRC_SIG_RED_GREEN_MASK_BASE_IDX                                                     2
8181 #define mmOTG1_OTG_CRC_SIG_BLUE_CONTROL_MASK                                                           0x1bfb
8182 #define mmOTG1_OTG_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX                                                  2
8183 #define mmOTG1_OTG_STATIC_SCREEN_CONTROL                                                               0x1c02
8184 #define mmOTG1_OTG_STATIC_SCREEN_CONTROL_BASE_IDX                                                      2
8185 #define mmOTG1_OTG_3D_STRUCTURE_CONTROL                                                                0x1c03
8186 #define mmOTG1_OTG_3D_STRUCTURE_CONTROL_BASE_IDX                                                       2
8187 #define mmOTG1_OTG_GSL_VSYNC_GAP                                                                       0x1c04
8188 #define mmOTG1_OTG_GSL_VSYNC_GAP_BASE_IDX                                                              2
8189 #define mmOTG1_OTG_MASTER_UPDATE_MODE                                                                  0x1c05
8190 #define mmOTG1_OTG_MASTER_UPDATE_MODE_BASE_IDX                                                         2
8191 #define mmOTG1_OTG_CLOCK_CONTROL                                                                       0x1c06
8192 #define mmOTG1_OTG_CLOCK_CONTROL_BASE_IDX                                                              2
8193 #define mmOTG1_OTG_VSTARTUP_PARAM                                                                      0x1c07
8194 #define mmOTG1_OTG_VSTARTUP_PARAM_BASE_IDX                                                             2
8195 #define mmOTG1_OTG_VUPDATE_PARAM                                                                       0x1c08
8196 #define mmOTG1_OTG_VUPDATE_PARAM_BASE_IDX                                                              2
8197 #define mmOTG1_OTG_VREADY_PARAM                                                                        0x1c09
8198 #define mmOTG1_OTG_VREADY_PARAM_BASE_IDX                                                               2
8199 #define mmOTG1_OTG_GLOBAL_SYNC_STATUS                                                                  0x1c0a
8200 #define mmOTG1_OTG_GLOBAL_SYNC_STATUS_BASE_IDX                                                         2
8201 #define mmOTG1_OTG_MASTER_UPDATE_LOCK                                                                  0x1c0b
8202 #define mmOTG1_OTG_MASTER_UPDATE_LOCK_BASE_IDX                                                         2
8203 #define mmOTG1_OTG_GSL_CONTROL                                                                         0x1c0c
8204 #define mmOTG1_OTG_GSL_CONTROL_BASE_IDX                                                                2
8205 #define mmOTG1_OTG_GSL_WINDOW_X                                                                        0x1c0d
8206 #define mmOTG1_OTG_GSL_WINDOW_X_BASE_IDX                                                               2
8207 #define mmOTG1_OTG_GSL_WINDOW_Y                                                                        0x1c0e
8208 #define mmOTG1_OTG_GSL_WINDOW_Y_BASE_IDX                                                               2
8209 #define mmOTG1_OTG_VUPDATE_KEEPOUT                                                                     0x1c0f
8210 #define mmOTG1_OTG_VUPDATE_KEEPOUT_BASE_IDX                                                            2
8211 #define mmOTG1_OTG_GLOBAL_CONTROL0                                                                     0x1c10
8212 #define mmOTG1_OTG_GLOBAL_CONTROL0_BASE_IDX                                                            2
8213 #define mmOTG1_OTG_GLOBAL_CONTROL1                                                                     0x1c11
8214 #define mmOTG1_OTG_GLOBAL_CONTROL1_BASE_IDX                                                            2
8215 #define mmOTG1_OTG_GLOBAL_CONTROL2                                                                     0x1c12
8216 #define mmOTG1_OTG_GLOBAL_CONTROL2_BASE_IDX                                                            2
8217 #define mmOTG1_OTG_GLOBAL_CONTROL3                                                                     0x1c13
8218 #define mmOTG1_OTG_GLOBAL_CONTROL3_BASE_IDX                                                            2
8219 #define mmOTG1_OTG_GLOBAL_CONTROL4                                                                     0x1c14
8220 #define mmOTG1_OTG_GLOBAL_CONTROL4_BASE_IDX                                                            2
8221 #define mmOTG1_OTG_TRIG_MANUAL_CONTROL                                                                 0x1c15
8222 #define mmOTG1_OTG_TRIG_MANUAL_CONTROL_BASE_IDX                                                        2
8223 #define mmOTG1_OTG_MANUAL_FLOW_CONTROL                                                                 0x1c16
8224 #define mmOTG1_OTG_MANUAL_FLOW_CONTROL_BASE_IDX                                                        2
8225 #define mmOTG1_OTG_DRR_TIMING_INT_STATUS                                                               0x1c17
8226 #define mmOTG1_OTG_DRR_TIMING_INT_STATUS_BASE_IDX                                                      2
8227 #define mmOTG1_OTG_DRR_V_TOTAL_REACH_RANGE                                                             0x1c18
8228 #define mmOTG1_OTG_DRR_V_TOTAL_REACH_RANGE_BASE_IDX                                                    2
8229 #define mmOTG1_OTG_DRR_V_TOTAL_CHANGE                                                                  0x1c19
8230 #define mmOTG1_OTG_DRR_V_TOTAL_CHANGE_BASE_IDX                                                         2
8231 #define mmOTG1_OTG_DRR_TRIGGER_WINDOW                                                                  0x1c1a
8232 #define mmOTG1_OTG_DRR_TRIGGER_WINDOW_BASE_IDX                                                         2
8233 #define mmOTG1_OTG_DRR_CONTROL                                                                         0x1c1b
8234 #define mmOTG1_OTG_DRR_CONTROL_BASE_IDX                                                                2
8235 #define mmOTG1_OTG_M_CONST_DTO0                                                                        0x1c1c
8236 #define mmOTG1_OTG_M_CONST_DTO0_BASE_IDX                                                               2
8237 #define mmOTG1_OTG_M_CONST_DTO1                                                                        0x1c1d
8238 #define mmOTG1_OTG_M_CONST_DTO1_BASE_IDX                                                               2
8239 #define mmOTG1_OTG_REQUEST_CONTROL                                                                     0x1c1e
8240 #define mmOTG1_OTG_REQUEST_CONTROL_BASE_IDX                                                            2
8241 #define mmOTG1_OTG_DSC_START_POSITION                                                                  0x1c1f
8242 #define mmOTG1_OTG_DSC_START_POSITION_BASE_IDX                                                         2
8243 #define mmOTG1_OTG_PIPE_UPDATE_STATUS                                                                  0x1c20
8244 #define mmOTG1_OTG_PIPE_UPDATE_STATUS_BASE_IDX                                                         2
8245 #define mmOTG1_OTG_SPARE_REGISTER                                                                      0x1c22
8246 #define mmOTG1_OTG_SPARE_REGISTER_BASE_IDX                                                             2
8247 
8248 
8249 // addressBlock: dce_dc_optc_otg2_dispdec
8250 // base address: 0x400
8251 #define mmOTG2_OTG_H_TOTAL                                                                             0x1c2a
8252 #define mmOTG2_OTG_H_TOTAL_BASE_IDX                                                                    2
8253 #define mmOTG2_OTG_H_BLANK_START_END                                                                   0x1c2b
8254 #define mmOTG2_OTG_H_BLANK_START_END_BASE_IDX                                                          2
8255 #define mmOTG2_OTG_H_SYNC_A                                                                            0x1c2c
8256 #define mmOTG2_OTG_H_SYNC_A_BASE_IDX                                                                   2
8257 #define mmOTG2_OTG_H_SYNC_A_CNTL                                                                       0x1c2d
8258 #define mmOTG2_OTG_H_SYNC_A_CNTL_BASE_IDX                                                              2
8259 #define mmOTG2_OTG_H_TIMING_CNTL                                                                       0x1c2e
8260 #define mmOTG2_OTG_H_TIMING_CNTL_BASE_IDX                                                              2
8261 #define mmOTG2_OTG_V_TOTAL                                                                             0x1c2f
8262 #define mmOTG2_OTG_V_TOTAL_BASE_IDX                                                                    2
8263 #define mmOTG2_OTG_V_TOTAL_MIN                                                                         0x1c30
8264 #define mmOTG2_OTG_V_TOTAL_MIN_BASE_IDX                                                                2
8265 #define mmOTG2_OTG_V_TOTAL_MAX                                                                         0x1c31
8266 #define mmOTG2_OTG_V_TOTAL_MAX_BASE_IDX                                                                2
8267 #define mmOTG2_OTG_V_TOTAL_MID                                                                         0x1c32
8268 #define mmOTG2_OTG_V_TOTAL_MID_BASE_IDX                                                                2
8269 #define mmOTG2_OTG_V_TOTAL_CONTROL                                                                     0x1c33
8270 #define mmOTG2_OTG_V_TOTAL_CONTROL_BASE_IDX                                                            2
8271 #define mmOTG2_OTG_V_TOTAL_INT_STATUS                                                                  0x1c34
8272 #define mmOTG2_OTG_V_TOTAL_INT_STATUS_BASE_IDX                                                         2
8273 #define mmOTG2_OTG_VSYNC_NOM_INT_STATUS                                                                0x1c35
8274 #define mmOTG2_OTG_VSYNC_NOM_INT_STATUS_BASE_IDX                                                       2
8275 #define mmOTG2_OTG_V_BLANK_START_END                                                                   0x1c36
8276 #define mmOTG2_OTG_V_BLANK_START_END_BASE_IDX                                                          2
8277 #define mmOTG2_OTG_V_SYNC_A                                                                            0x1c37
8278 #define mmOTG2_OTG_V_SYNC_A_BASE_IDX                                                                   2
8279 #define mmOTG2_OTG_V_SYNC_A_CNTL                                                                       0x1c38
8280 #define mmOTG2_OTG_V_SYNC_A_CNTL_BASE_IDX                                                              2
8281 #define mmOTG2_OTG_TRIGA_CNTL                                                                          0x1c39
8282 #define mmOTG2_OTG_TRIGA_CNTL_BASE_IDX                                                                 2
8283 #define mmOTG2_OTG_TRIGA_MANUAL_TRIG                                                                   0x1c3a
8284 #define mmOTG2_OTG_TRIGA_MANUAL_TRIG_BASE_IDX                                                          2
8285 #define mmOTG2_OTG_TRIGB_CNTL                                                                          0x1c3b
8286 #define mmOTG2_OTG_TRIGB_CNTL_BASE_IDX                                                                 2
8287 #define mmOTG2_OTG_TRIGB_MANUAL_TRIG                                                                   0x1c3c
8288 #define mmOTG2_OTG_TRIGB_MANUAL_TRIG_BASE_IDX                                                          2
8289 #define mmOTG2_OTG_FORCE_COUNT_NOW_CNTL                                                                0x1c3d
8290 #define mmOTG2_OTG_FORCE_COUNT_NOW_CNTL_BASE_IDX                                                       2
8291 #define mmOTG2_OTG_FLOW_CONTROL                                                                        0x1c3e
8292 #define mmOTG2_OTG_FLOW_CONTROL_BASE_IDX                                                               2
8293 #define mmOTG2_OTG_STEREO_FORCE_NEXT_EYE                                                               0x1c3f
8294 #define mmOTG2_OTG_STEREO_FORCE_NEXT_EYE_BASE_IDX                                                      2
8295 #define mmOTG2_OTG_CONTROL                                                                             0x1c41
8296 #define mmOTG2_OTG_CONTROL_BASE_IDX                                                                    2
8297 #define mmOTG2_OTG_INTERLACE_CONTROL                                                                   0x1c44
8298 #define mmOTG2_OTG_INTERLACE_CONTROL_BASE_IDX                                                          2
8299 #define mmOTG2_OTG_INTERLACE_STATUS                                                                    0x1c45
8300 #define mmOTG2_OTG_INTERLACE_STATUS_BASE_IDX                                                           2
8301 #define mmOTG2_OTG_PIXEL_DATA_READBACK0                                                                0x1c47
8302 #define mmOTG2_OTG_PIXEL_DATA_READBACK0_BASE_IDX                                                       2
8303 #define mmOTG2_OTG_PIXEL_DATA_READBACK1                                                                0x1c48
8304 #define mmOTG2_OTG_PIXEL_DATA_READBACK1_BASE_IDX                                                       2
8305 #define mmOTG2_OTG_STATUS                                                                              0x1c49
8306 #define mmOTG2_OTG_STATUS_BASE_IDX                                                                     2
8307 #define mmOTG2_OTG_STATUS_POSITION                                                                     0x1c4a
8308 #define mmOTG2_OTG_STATUS_POSITION_BASE_IDX                                                            2
8309 #define mmOTG2_OTG_NOM_VERT_POSITION                                                                   0x1c4b
8310 #define mmOTG2_OTG_NOM_VERT_POSITION_BASE_IDX                                                          2
8311 #define mmOTG2_OTG_STATUS_FRAME_COUNT                                                                  0x1c4c
8312 #define mmOTG2_OTG_STATUS_FRAME_COUNT_BASE_IDX                                                         2
8313 #define mmOTG2_OTG_STATUS_VF_COUNT                                                                     0x1c4d
8314 #define mmOTG2_OTG_STATUS_VF_COUNT_BASE_IDX                                                            2
8315 #define mmOTG2_OTG_STATUS_HV_COUNT                                                                     0x1c4e
8316 #define mmOTG2_OTG_STATUS_HV_COUNT_BASE_IDX                                                            2
8317 #define mmOTG2_OTG_COUNT_CONTROL                                                                       0x1c4f
8318 #define mmOTG2_OTG_COUNT_CONTROL_BASE_IDX                                                              2
8319 #define mmOTG2_OTG_COUNT_RESET                                                                         0x1c50
8320 #define mmOTG2_OTG_COUNT_RESET_BASE_IDX                                                                2
8321 #define mmOTG2_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE                                                        0x1c51
8322 #define mmOTG2_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX                                               2
8323 #define mmOTG2_OTG_VERT_SYNC_CONTROL                                                                   0x1c52
8324 #define mmOTG2_OTG_VERT_SYNC_CONTROL_BASE_IDX                                                          2
8325 #define mmOTG2_OTG_STEREO_STATUS                                                                       0x1c53
8326 #define mmOTG2_OTG_STEREO_STATUS_BASE_IDX                                                              2
8327 #define mmOTG2_OTG_STEREO_CONTROL                                                                      0x1c54
8328 #define mmOTG2_OTG_STEREO_CONTROL_BASE_IDX                                                             2
8329 #define mmOTG2_OTG_SNAPSHOT_STATUS                                                                     0x1c55
8330 #define mmOTG2_OTG_SNAPSHOT_STATUS_BASE_IDX                                                            2
8331 #define mmOTG2_OTG_SNAPSHOT_CONTROL                                                                    0x1c56
8332 #define mmOTG2_OTG_SNAPSHOT_CONTROL_BASE_IDX                                                           2
8333 #define mmOTG2_OTG_SNAPSHOT_POSITION                                                                   0x1c57
8334 #define mmOTG2_OTG_SNAPSHOT_POSITION_BASE_IDX                                                          2
8335 #define mmOTG2_OTG_SNAPSHOT_FRAME                                                                      0x1c58
8336 #define mmOTG2_OTG_SNAPSHOT_FRAME_BASE_IDX                                                             2
8337 #define mmOTG2_OTG_INTERRUPT_CONTROL                                                                   0x1c59
8338 #define mmOTG2_OTG_INTERRUPT_CONTROL_BASE_IDX                                                          2
8339 #define mmOTG2_OTG_UPDATE_LOCK                                                                         0x1c5a
8340 #define mmOTG2_OTG_UPDATE_LOCK_BASE_IDX                                                                2
8341 #define mmOTG2_OTG_DOUBLE_BUFFER_CONTROL                                                               0x1c5b
8342 #define mmOTG2_OTG_DOUBLE_BUFFER_CONTROL_BASE_IDX                                                      2
8343 #define mmOTG2_OTG_MASTER_EN                                                                           0x1c5c
8344 #define mmOTG2_OTG_MASTER_EN_BASE_IDX                                                                  2
8345 #define mmOTG2_OTG_BLANK_DATA_COLOR                                                                    0x1c5e
8346 #define mmOTG2_OTG_BLANK_DATA_COLOR_BASE_IDX                                                           2
8347 #define mmOTG2_OTG_BLANK_DATA_COLOR_EXT                                                                0x1c5f
8348 #define mmOTG2_OTG_BLANK_DATA_COLOR_EXT_BASE_IDX                                                       2
8349 #define mmOTG2_OTG_VERTICAL_INTERRUPT0_POSITION                                                        0x1c62
8350 #define mmOTG2_OTG_VERTICAL_INTERRUPT0_POSITION_BASE_IDX                                               2
8351 #define mmOTG2_OTG_VERTICAL_INTERRUPT0_CONTROL                                                         0x1c63
8352 #define mmOTG2_OTG_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX                                                2
8353 #define mmOTG2_OTG_VERTICAL_INTERRUPT1_POSITION                                                        0x1c64
8354 #define mmOTG2_OTG_VERTICAL_INTERRUPT1_POSITION_BASE_IDX                                               2
8355 #define mmOTG2_OTG_VERTICAL_INTERRUPT1_CONTROL                                                         0x1c65
8356 #define mmOTG2_OTG_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX                                                2
8357 #define mmOTG2_OTG_VERTICAL_INTERRUPT2_POSITION                                                        0x1c66
8358 #define mmOTG2_OTG_VERTICAL_INTERRUPT2_POSITION_BASE_IDX                                               2
8359 #define mmOTG2_OTG_VERTICAL_INTERRUPT2_CONTROL                                                         0x1c67
8360 #define mmOTG2_OTG_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX                                                2
8361 #define mmOTG2_OTG_CRC_CNTL                                                                            0x1c68
8362 #define mmOTG2_OTG_CRC_CNTL_BASE_IDX                                                                   2
8363 #define mmOTG2_OTG_CRC_CNTL2                                                                           0x1c69
8364 #define mmOTG2_OTG_CRC_CNTL2_BASE_IDX                                                                  2
8365 #define mmOTG2_OTG_CRC0_WINDOWA_X_CONTROL                                                              0x1c6a
8366 #define mmOTG2_OTG_CRC0_WINDOWA_X_CONTROL_BASE_IDX                                                     2
8367 #define mmOTG2_OTG_CRC0_WINDOWA_Y_CONTROL                                                              0x1c6b
8368 #define mmOTG2_OTG_CRC0_WINDOWA_Y_CONTROL_BASE_IDX                                                     2
8369 #define mmOTG2_OTG_CRC0_WINDOWB_X_CONTROL                                                              0x1c6c
8370 #define mmOTG2_OTG_CRC0_WINDOWB_X_CONTROL_BASE_IDX                                                     2
8371 #define mmOTG2_OTG_CRC0_WINDOWB_Y_CONTROL                                                              0x1c6d
8372 #define mmOTG2_OTG_CRC0_WINDOWB_Y_CONTROL_BASE_IDX                                                     2
8373 #define mmOTG2_OTG_CRC0_DATA_RG                                                                        0x1c6e
8374 #define mmOTG2_OTG_CRC0_DATA_RG_BASE_IDX                                                               2
8375 #define mmOTG2_OTG_CRC0_DATA_B                                                                         0x1c6f
8376 #define mmOTG2_OTG_CRC0_DATA_B_BASE_IDX                                                                2
8377 #define mmOTG2_OTG_CRC1_WINDOWA_X_CONTROL                                                              0x1c70
8378 #define mmOTG2_OTG_CRC1_WINDOWA_X_CONTROL_BASE_IDX                                                     2
8379 #define mmOTG2_OTG_CRC1_WINDOWA_Y_CONTROL                                                              0x1c71
8380 #define mmOTG2_OTG_CRC1_WINDOWA_Y_CONTROL_BASE_IDX                                                     2
8381 #define mmOTG2_OTG_CRC1_WINDOWB_X_CONTROL                                                              0x1c72
8382 #define mmOTG2_OTG_CRC1_WINDOWB_X_CONTROL_BASE_IDX                                                     2
8383 #define mmOTG2_OTG_CRC1_WINDOWB_Y_CONTROL                                                              0x1c73
8384 #define mmOTG2_OTG_CRC1_WINDOWB_Y_CONTROL_BASE_IDX                                                     2
8385 #define mmOTG2_OTG_CRC1_DATA_RG                                                                        0x1c74
8386 #define mmOTG2_OTG_CRC1_DATA_RG_BASE_IDX                                                               2
8387 #define mmOTG2_OTG_CRC1_DATA_B                                                                         0x1c75
8388 #define mmOTG2_OTG_CRC1_DATA_B_BASE_IDX                                                                2
8389 #define mmOTG2_OTG_CRC2_DATA_RG                                                                        0x1c76
8390 #define mmOTG2_OTG_CRC2_DATA_RG_BASE_IDX                                                               2
8391 #define mmOTG2_OTG_CRC2_DATA_B                                                                         0x1c77
8392 #define mmOTG2_OTG_CRC2_DATA_B_BASE_IDX                                                                2
8393 #define mmOTG2_OTG_CRC3_DATA_RG                                                                        0x1c78
8394 #define mmOTG2_OTG_CRC3_DATA_RG_BASE_IDX                                                               2
8395 #define mmOTG2_OTG_CRC3_DATA_B                                                                         0x1c79
8396 #define mmOTG2_OTG_CRC3_DATA_B_BASE_IDX                                                                2
8397 #define mmOTG2_OTG_CRC_SIG_RED_GREEN_MASK                                                              0x1c7a
8398 #define mmOTG2_OTG_CRC_SIG_RED_GREEN_MASK_BASE_IDX                                                     2
8399 #define mmOTG2_OTG_CRC_SIG_BLUE_CONTROL_MASK                                                           0x1c7b
8400 #define mmOTG2_OTG_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX                                                  2
8401 #define mmOTG2_OTG_STATIC_SCREEN_CONTROL                                                               0x1c82
8402 #define mmOTG2_OTG_STATIC_SCREEN_CONTROL_BASE_IDX                                                      2
8403 #define mmOTG2_OTG_3D_STRUCTURE_CONTROL                                                                0x1c83
8404 #define mmOTG2_OTG_3D_STRUCTURE_CONTROL_BASE_IDX                                                       2
8405 #define mmOTG2_OTG_GSL_VSYNC_GAP                                                                       0x1c84
8406 #define mmOTG2_OTG_GSL_VSYNC_GAP_BASE_IDX                                                              2
8407 #define mmOTG2_OTG_MASTER_UPDATE_MODE                                                                  0x1c85
8408 #define mmOTG2_OTG_MASTER_UPDATE_MODE_BASE_IDX                                                         2
8409 #define mmOTG2_OTG_CLOCK_CONTROL                                                                       0x1c86
8410 #define mmOTG2_OTG_CLOCK_CONTROL_BASE_IDX                                                              2
8411 #define mmOTG2_OTG_VSTARTUP_PARAM                                                                      0x1c87
8412 #define mmOTG2_OTG_VSTARTUP_PARAM_BASE_IDX                                                             2
8413 #define mmOTG2_OTG_VUPDATE_PARAM                                                                       0x1c88
8414 #define mmOTG2_OTG_VUPDATE_PARAM_BASE_IDX                                                              2
8415 #define mmOTG2_OTG_VREADY_PARAM                                                                        0x1c89
8416 #define mmOTG2_OTG_VREADY_PARAM_BASE_IDX                                                               2
8417 #define mmOTG2_OTG_GLOBAL_SYNC_STATUS                                                                  0x1c8a
8418 #define mmOTG2_OTG_GLOBAL_SYNC_STATUS_BASE_IDX                                                         2
8419 #define mmOTG2_OTG_MASTER_UPDATE_LOCK                                                                  0x1c8b
8420 #define mmOTG2_OTG_MASTER_UPDATE_LOCK_BASE_IDX                                                         2
8421 #define mmOTG2_OTG_GSL_CONTROL                                                                         0x1c8c
8422 #define mmOTG2_OTG_GSL_CONTROL_BASE_IDX                                                                2
8423 #define mmOTG2_OTG_GSL_WINDOW_X                                                                        0x1c8d
8424 #define mmOTG2_OTG_GSL_WINDOW_X_BASE_IDX                                                               2
8425 #define mmOTG2_OTG_GSL_WINDOW_Y                                                                        0x1c8e
8426 #define mmOTG2_OTG_GSL_WINDOW_Y_BASE_IDX                                                               2
8427 #define mmOTG2_OTG_VUPDATE_KEEPOUT                                                                     0x1c8f
8428 #define mmOTG2_OTG_VUPDATE_KEEPOUT_BASE_IDX                                                            2
8429 #define mmOTG2_OTG_GLOBAL_CONTROL0                                                                     0x1c90
8430 #define mmOTG2_OTG_GLOBAL_CONTROL0_BASE_IDX                                                            2
8431 #define mmOTG2_OTG_GLOBAL_CONTROL1                                                                     0x1c91
8432 #define mmOTG2_OTG_GLOBAL_CONTROL1_BASE_IDX                                                            2
8433 #define mmOTG2_OTG_GLOBAL_CONTROL2                                                                     0x1c92
8434 #define mmOTG2_OTG_GLOBAL_CONTROL2_BASE_IDX                                                            2
8435 #define mmOTG2_OTG_GLOBAL_CONTROL3                                                                     0x1c93
8436 #define mmOTG2_OTG_GLOBAL_CONTROL3_BASE_IDX                                                            2
8437 #define mmOTG2_OTG_GLOBAL_CONTROL4                                                                     0x1c94
8438 #define mmOTG2_OTG_GLOBAL_CONTROL4_BASE_IDX                                                            2
8439 #define mmOTG2_OTG_TRIG_MANUAL_CONTROL                                                                 0x1c95
8440 #define mmOTG2_OTG_TRIG_MANUAL_CONTROL_BASE_IDX                                                        2
8441 #define mmOTG2_OTG_MANUAL_FLOW_CONTROL                                                                 0x1c96
8442 #define mmOTG2_OTG_MANUAL_FLOW_CONTROL_BASE_IDX                                                        2
8443 #define mmOTG2_OTG_DRR_TIMING_INT_STATUS                                                               0x1c97
8444 #define mmOTG2_OTG_DRR_TIMING_INT_STATUS_BASE_IDX                                                      2
8445 #define mmOTG2_OTG_DRR_V_TOTAL_REACH_RANGE                                                             0x1c98
8446 #define mmOTG2_OTG_DRR_V_TOTAL_REACH_RANGE_BASE_IDX                                                    2
8447 #define mmOTG2_OTG_DRR_V_TOTAL_CHANGE                                                                  0x1c99
8448 #define mmOTG2_OTG_DRR_V_TOTAL_CHANGE_BASE_IDX                                                         2
8449 #define mmOTG2_OTG_DRR_TRIGGER_WINDOW                                                                  0x1c9a
8450 #define mmOTG2_OTG_DRR_TRIGGER_WINDOW_BASE_IDX                                                         2
8451 #define mmOTG2_OTG_DRR_CONTROL                                                                         0x1c9b
8452 #define mmOTG2_OTG_DRR_CONTROL_BASE_IDX                                                                2
8453 #define mmOTG2_OTG_M_CONST_DTO0                                                                        0x1c9c
8454 #define mmOTG2_OTG_M_CONST_DTO0_BASE_IDX                                                               2
8455 #define mmOTG2_OTG_M_CONST_DTO1                                                                        0x1c9d
8456 #define mmOTG2_OTG_M_CONST_DTO1_BASE_IDX                                                               2
8457 #define mmOTG2_OTG_REQUEST_CONTROL                                                                     0x1c9e
8458 #define mmOTG2_OTG_REQUEST_CONTROL_BASE_IDX                                                            2
8459 #define mmOTG2_OTG_DSC_START_POSITION                                                                  0x1c9f
8460 #define mmOTG2_OTG_DSC_START_POSITION_BASE_IDX                                                         2
8461 #define mmOTG2_OTG_PIPE_UPDATE_STATUS                                                                  0x1ca0
8462 #define mmOTG2_OTG_PIPE_UPDATE_STATUS_BASE_IDX                                                         2
8463 #define mmOTG2_OTG_SPARE_REGISTER                                                                      0x1ca2
8464 #define mmOTG2_OTG_SPARE_REGISTER_BASE_IDX                                                             2
8465 
8466 
8467 // addressBlock: dce_dc_optc_otg3_dispdec
8468 // base address: 0x600
8469 #define mmOTG3_OTG_H_TOTAL                                                                             0x1caa
8470 #define mmOTG3_OTG_H_TOTAL_BASE_IDX                                                                    2
8471 #define mmOTG3_OTG_H_BLANK_START_END                                                                   0x1cab
8472 #define mmOTG3_OTG_H_BLANK_START_END_BASE_IDX                                                          2
8473 #define mmOTG3_OTG_H_SYNC_A                                                                            0x1cac
8474 #define mmOTG3_OTG_H_SYNC_A_BASE_IDX                                                                   2
8475 #define mmOTG3_OTG_H_SYNC_A_CNTL                                                                       0x1cad
8476 #define mmOTG3_OTG_H_SYNC_A_CNTL_BASE_IDX                                                              2
8477 #define mmOTG3_OTG_H_TIMING_CNTL                                                                       0x1cae
8478 #define mmOTG3_OTG_H_TIMING_CNTL_BASE_IDX                                                              2
8479 #define mmOTG3_OTG_V_TOTAL                                                                             0x1caf
8480 #define mmOTG3_OTG_V_TOTAL_BASE_IDX                                                                    2
8481 #define mmOTG3_OTG_V_TOTAL_MIN                                                                         0x1cb0
8482 #define mmOTG3_OTG_V_TOTAL_MIN_BASE_IDX                                                                2
8483 #define mmOTG3_OTG_V_TOTAL_MAX                                                                         0x1cb1
8484 #define mmOTG3_OTG_V_TOTAL_MAX_BASE_IDX                                                                2
8485 #define mmOTG3_OTG_V_TOTAL_MID                                                                         0x1cb2
8486 #define mmOTG3_OTG_V_TOTAL_MID_BASE_IDX                                                                2
8487 #define mmOTG3_OTG_V_TOTAL_CONTROL                                                                     0x1cb3
8488 #define mmOTG3_OTG_V_TOTAL_CONTROL_BASE_IDX                                                            2
8489 #define mmOTG3_OTG_V_TOTAL_INT_STATUS                                                                  0x1cb4
8490 #define mmOTG3_OTG_V_TOTAL_INT_STATUS_BASE_IDX                                                         2
8491 #define mmOTG3_OTG_VSYNC_NOM_INT_STATUS                                                                0x1cb5
8492 #define mmOTG3_OTG_VSYNC_NOM_INT_STATUS_BASE_IDX                                                       2
8493 #define mmOTG3_OTG_V_BLANK_START_END                                                                   0x1cb6
8494 #define mmOTG3_OTG_V_BLANK_START_END_BASE_IDX                                                          2
8495 #define mmOTG3_OTG_V_SYNC_A                                                                            0x1cb7
8496 #define mmOTG3_OTG_V_SYNC_A_BASE_IDX                                                                   2
8497 #define mmOTG3_OTG_V_SYNC_A_CNTL                                                                       0x1cb8
8498 #define mmOTG3_OTG_V_SYNC_A_CNTL_BASE_IDX                                                              2
8499 #define mmOTG3_OTG_TRIGA_CNTL                                                                          0x1cb9
8500 #define mmOTG3_OTG_TRIGA_CNTL_BASE_IDX                                                                 2
8501 #define mmOTG3_OTG_TRIGA_MANUAL_TRIG                                                                   0x1cba
8502 #define mmOTG3_OTG_TRIGA_MANUAL_TRIG_BASE_IDX                                                          2
8503 #define mmOTG3_OTG_TRIGB_CNTL                                                                          0x1cbb
8504 #define mmOTG3_OTG_TRIGB_CNTL_BASE_IDX                                                                 2
8505 #define mmOTG3_OTG_TRIGB_MANUAL_TRIG                                                                   0x1cbc
8506 #define mmOTG3_OTG_TRIGB_MANUAL_TRIG_BASE_IDX                                                          2
8507 #define mmOTG3_OTG_FORCE_COUNT_NOW_CNTL                                                                0x1cbd
8508 #define mmOTG3_OTG_FORCE_COUNT_NOW_CNTL_BASE_IDX                                                       2
8509 #define mmOTG3_OTG_FLOW_CONTROL                                                                        0x1cbe
8510 #define mmOTG3_OTG_FLOW_CONTROL_BASE_IDX                                                               2
8511 #define mmOTG3_OTG_STEREO_FORCE_NEXT_EYE                                                               0x1cbf
8512 #define mmOTG3_OTG_STEREO_FORCE_NEXT_EYE_BASE_IDX                                                      2
8513 #define mmOTG3_OTG_CONTROL                                                                             0x1cc1
8514 #define mmOTG3_OTG_CONTROL_BASE_IDX                                                                    2
8515 #define mmOTG3_OTG_INTERLACE_CONTROL                                                                   0x1cc4
8516 #define mmOTG3_OTG_INTERLACE_CONTROL_BASE_IDX                                                          2
8517 #define mmOTG3_OTG_INTERLACE_STATUS                                                                    0x1cc5
8518 #define mmOTG3_OTG_INTERLACE_STATUS_BASE_IDX                                                           2
8519 #define mmOTG3_OTG_PIXEL_DATA_READBACK0                                                                0x1cc7
8520 #define mmOTG3_OTG_PIXEL_DATA_READBACK0_BASE_IDX                                                       2
8521 #define mmOTG3_OTG_PIXEL_DATA_READBACK1                                                                0x1cc8
8522 #define mmOTG3_OTG_PIXEL_DATA_READBACK1_BASE_IDX                                                       2
8523 #define mmOTG3_OTG_STATUS                                                                              0x1cc9
8524 #define mmOTG3_OTG_STATUS_BASE_IDX                                                                     2
8525 #define mmOTG3_OTG_STATUS_POSITION                                                                     0x1cca
8526 #define mmOTG3_OTG_STATUS_POSITION_BASE_IDX                                                            2
8527 #define mmOTG3_OTG_NOM_VERT_POSITION                                                                   0x1ccb
8528 #define mmOTG3_OTG_NOM_VERT_POSITION_BASE_IDX                                                          2
8529 #define mmOTG3_OTG_STATUS_FRAME_COUNT                                                                  0x1ccc
8530 #define mmOTG3_OTG_STATUS_FRAME_COUNT_BASE_IDX                                                         2
8531 #define mmOTG3_OTG_STATUS_VF_COUNT                                                                     0x1ccd
8532 #define mmOTG3_OTG_STATUS_VF_COUNT_BASE_IDX                                                            2
8533 #define mmOTG3_OTG_STATUS_HV_COUNT                                                                     0x1cce
8534 #define mmOTG3_OTG_STATUS_HV_COUNT_BASE_IDX                                                            2
8535 #define mmOTG3_OTG_COUNT_CONTROL                                                                       0x1ccf
8536 #define mmOTG3_OTG_COUNT_CONTROL_BASE_IDX                                                              2
8537 #define mmOTG3_OTG_COUNT_RESET                                                                         0x1cd0
8538 #define mmOTG3_OTG_COUNT_RESET_BASE_IDX                                                                2
8539 #define mmOTG3_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE                                                        0x1cd1
8540 #define mmOTG3_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX                                               2
8541 #define mmOTG3_OTG_VERT_SYNC_CONTROL                                                                   0x1cd2
8542 #define mmOTG3_OTG_VERT_SYNC_CONTROL_BASE_IDX                                                          2
8543 #define mmOTG3_OTG_STEREO_STATUS                                                                       0x1cd3
8544 #define mmOTG3_OTG_STEREO_STATUS_BASE_IDX                                                              2
8545 #define mmOTG3_OTG_STEREO_CONTROL                                                                      0x1cd4
8546 #define mmOTG3_OTG_STEREO_CONTROL_BASE_IDX                                                             2
8547 #define mmOTG3_OTG_SNAPSHOT_STATUS                                                                     0x1cd5
8548 #define mmOTG3_OTG_SNAPSHOT_STATUS_BASE_IDX                                                            2
8549 #define mmOTG3_OTG_SNAPSHOT_CONTROL                                                                    0x1cd6
8550 #define mmOTG3_OTG_SNAPSHOT_CONTROL_BASE_IDX                                                           2
8551 #define mmOTG3_OTG_SNAPSHOT_POSITION                                                                   0x1cd7
8552 #define mmOTG3_OTG_SNAPSHOT_POSITION_BASE_IDX                                                          2
8553 #define mmOTG3_OTG_SNAPSHOT_FRAME                                                                      0x1cd8
8554 #define mmOTG3_OTG_SNAPSHOT_FRAME_BASE_IDX                                                             2
8555 #define mmOTG3_OTG_INTERRUPT_CONTROL                                                                   0x1cd9
8556 #define mmOTG3_OTG_INTERRUPT_CONTROL_BASE_IDX                                                          2
8557 #define mmOTG3_OTG_UPDATE_LOCK                                                                         0x1cda
8558 #define mmOTG3_OTG_UPDATE_LOCK_BASE_IDX                                                                2
8559 #define mmOTG3_OTG_DOUBLE_BUFFER_CONTROL                                                               0x1cdb
8560 #define mmOTG3_OTG_DOUBLE_BUFFER_CONTROL_BASE_IDX                                                      2
8561 #define mmOTG3_OTG_MASTER_EN                                                                           0x1cdc
8562 #define mmOTG3_OTG_MASTER_EN_BASE_IDX                                                                  2
8563 #define mmOTG3_OTG_BLANK_DATA_COLOR                                                                    0x1cde
8564 #define mmOTG3_OTG_BLANK_DATA_COLOR_BASE_IDX                                                           2
8565 #define mmOTG3_OTG_BLANK_DATA_COLOR_EXT                                                                0x1cdf
8566 #define mmOTG3_OTG_BLANK_DATA_COLOR_EXT_BASE_IDX                                                       2
8567 #define mmOTG3_OTG_VERTICAL_INTERRUPT0_POSITION                                                        0x1ce2
8568 #define mmOTG3_OTG_VERTICAL_INTERRUPT0_POSITION_BASE_IDX                                               2
8569 #define mmOTG3_OTG_VERTICAL_INTERRUPT0_CONTROL                                                         0x1ce3
8570 #define mmOTG3_OTG_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX                                                2
8571 #define mmOTG3_OTG_VERTICAL_INTERRUPT1_POSITION                                                        0x1ce4
8572 #define mmOTG3_OTG_VERTICAL_INTERRUPT1_POSITION_BASE_IDX                                               2
8573 #define mmOTG3_OTG_VERTICAL_INTERRUPT1_CONTROL                                                         0x1ce5
8574 #define mmOTG3_OTG_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX                                                2
8575 #define mmOTG3_OTG_VERTICAL_INTERRUPT2_POSITION                                                        0x1ce6
8576 #define mmOTG3_OTG_VERTICAL_INTERRUPT2_POSITION_BASE_IDX                                               2
8577 #define mmOTG3_OTG_VERTICAL_INTERRUPT2_CONTROL                                                         0x1ce7
8578 #define mmOTG3_OTG_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX                                                2
8579 #define mmOTG3_OTG_CRC_CNTL                                                                            0x1ce8
8580 #define mmOTG3_OTG_CRC_CNTL_BASE_IDX                                                                   2
8581 #define mmOTG3_OTG_CRC_CNTL2                                                                           0x1ce9
8582 #define mmOTG3_OTG_CRC_CNTL2_BASE_IDX                                                                  2
8583 #define mmOTG3_OTG_CRC0_WINDOWA_X_CONTROL                                                              0x1cea
8584 #define mmOTG3_OTG_CRC0_WINDOWA_X_CONTROL_BASE_IDX                                                     2
8585 #define mmOTG3_OTG_CRC0_WINDOWA_Y_CONTROL                                                              0x1ceb
8586 #define mmOTG3_OTG_CRC0_WINDOWA_Y_CONTROL_BASE_IDX                                                     2
8587 #define mmOTG3_OTG_CRC0_WINDOWB_X_CONTROL                                                              0x1cec
8588 #define mmOTG3_OTG_CRC0_WINDOWB_X_CONTROL_BASE_IDX                                                     2
8589 #define mmOTG3_OTG_CRC0_WINDOWB_Y_CONTROL                                                              0x1ced
8590 #define mmOTG3_OTG_CRC0_WINDOWB_Y_CONTROL_BASE_IDX                                                     2
8591 #define mmOTG3_OTG_CRC0_DATA_RG                                                                        0x1cee
8592 #define mmOTG3_OTG_CRC0_DATA_RG_BASE_IDX                                                               2
8593 #define mmOTG3_OTG_CRC0_DATA_B                                                                         0x1cef
8594 #define mmOTG3_OTG_CRC0_DATA_B_BASE_IDX                                                                2
8595 #define mmOTG3_OTG_CRC1_WINDOWA_X_CONTROL                                                              0x1cf0
8596 #define mmOTG3_OTG_CRC1_WINDOWA_X_CONTROL_BASE_IDX                                                     2
8597 #define mmOTG3_OTG_CRC1_WINDOWA_Y_CONTROL                                                              0x1cf1
8598 #define mmOTG3_OTG_CRC1_WINDOWA_Y_CONTROL_BASE_IDX                                                     2
8599 #define mmOTG3_OTG_CRC1_WINDOWB_X_CONTROL                                                              0x1cf2
8600 #define mmOTG3_OTG_CRC1_WINDOWB_X_CONTROL_BASE_IDX                                                     2
8601 #define mmOTG3_OTG_CRC1_WINDOWB_Y_CONTROL                                                              0x1cf3
8602 #define mmOTG3_OTG_CRC1_WINDOWB_Y_CONTROL_BASE_IDX                                                     2
8603 #define mmOTG3_OTG_CRC1_DATA_RG                                                                        0x1cf4
8604 #define mmOTG3_OTG_CRC1_DATA_RG_BASE_IDX                                                               2
8605 #define mmOTG3_OTG_CRC1_DATA_B                                                                         0x1cf5
8606 #define mmOTG3_OTG_CRC1_DATA_B_BASE_IDX                                                                2
8607 #define mmOTG3_OTG_CRC2_DATA_RG                                                                        0x1cf6
8608 #define mmOTG3_OTG_CRC2_DATA_RG_BASE_IDX                                                               2
8609 #define mmOTG3_OTG_CRC2_DATA_B                                                                         0x1cf7
8610 #define mmOTG3_OTG_CRC2_DATA_B_BASE_IDX                                                                2
8611 #define mmOTG3_OTG_CRC3_DATA_RG                                                                        0x1cf8
8612 #define mmOTG3_OTG_CRC3_DATA_RG_BASE_IDX                                                               2
8613 #define mmOTG3_OTG_CRC3_DATA_B                                                                         0x1cf9
8614 #define mmOTG3_OTG_CRC3_DATA_B_BASE_IDX                                                                2
8615 #define mmOTG3_OTG_CRC_SIG_RED_GREEN_MASK                                                              0x1cfa
8616 #define mmOTG3_OTG_CRC_SIG_RED_GREEN_MASK_BASE_IDX                                                     2
8617 #define mmOTG3_OTG_CRC_SIG_BLUE_CONTROL_MASK                                                           0x1cfb
8618 #define mmOTG3_OTG_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX                                                  2
8619 #define mmOTG3_OTG_STATIC_SCREEN_CONTROL                                                               0x1d02
8620 #define mmOTG3_OTG_STATIC_SCREEN_CONTROL_BASE_IDX                                                      2
8621 #define mmOTG3_OTG_3D_STRUCTURE_CONTROL                                                                0x1d03
8622 #define mmOTG3_OTG_3D_STRUCTURE_CONTROL_BASE_IDX                                                       2
8623 #define mmOTG3_OTG_GSL_VSYNC_GAP                                                                       0x1d04
8624 #define mmOTG3_OTG_GSL_VSYNC_GAP_BASE_IDX                                                              2
8625 #define mmOTG3_OTG_MASTER_UPDATE_MODE                                                                  0x1d05
8626 #define mmOTG3_OTG_MASTER_UPDATE_MODE_BASE_IDX                                                         2
8627 #define mmOTG3_OTG_CLOCK_CONTROL                                                                       0x1d06
8628 #define mmOTG3_OTG_CLOCK_CONTROL_BASE_IDX                                                              2
8629 #define mmOTG3_OTG_VSTARTUP_PARAM                                                                      0x1d07
8630 #define mmOTG3_OTG_VSTARTUP_PARAM_BASE_IDX                                                             2
8631 #define mmOTG3_OTG_VUPDATE_PARAM                                                                       0x1d08
8632 #define mmOTG3_OTG_VUPDATE_PARAM_BASE_IDX                                                              2
8633 #define mmOTG3_OTG_VREADY_PARAM                                                                        0x1d09
8634 #define mmOTG3_OTG_VREADY_PARAM_BASE_IDX                                                               2
8635 #define mmOTG3_OTG_GLOBAL_SYNC_STATUS                                                                  0x1d0a
8636 #define mmOTG3_OTG_GLOBAL_SYNC_STATUS_BASE_IDX                                                         2
8637 #define mmOTG3_OTG_MASTER_UPDATE_LOCK                                                                  0x1d0b
8638 #define mmOTG3_OTG_MASTER_UPDATE_LOCK_BASE_IDX                                                         2
8639 #define mmOTG3_OTG_GSL_CONTROL                                                                         0x1d0c
8640 #define mmOTG3_OTG_GSL_CONTROL_BASE_IDX                                                                2
8641 #define mmOTG3_OTG_GSL_WINDOW_X                                                                        0x1d0d
8642 #define mmOTG3_OTG_GSL_WINDOW_X_BASE_IDX                                                               2
8643 #define mmOTG3_OTG_GSL_WINDOW_Y                                                                        0x1d0e
8644 #define mmOTG3_OTG_GSL_WINDOW_Y_BASE_IDX                                                               2
8645 #define mmOTG3_OTG_VUPDATE_KEEPOUT                                                                     0x1d0f
8646 #define mmOTG3_OTG_VUPDATE_KEEPOUT_BASE_IDX                                                            2
8647 #define mmOTG3_OTG_GLOBAL_CONTROL0                                                                     0x1d10
8648 #define mmOTG3_OTG_GLOBAL_CONTROL0_BASE_IDX                                                            2
8649 #define mmOTG3_OTG_GLOBAL_CONTROL1                                                                     0x1d11
8650 #define mmOTG3_OTG_GLOBAL_CONTROL1_BASE_IDX                                                            2
8651 #define mmOTG3_OTG_GLOBAL_CONTROL2                                                                     0x1d12
8652 #define mmOTG3_OTG_GLOBAL_CONTROL2_BASE_IDX                                                            2
8653 #define mmOTG3_OTG_GLOBAL_CONTROL3                                                                     0x1d13
8654 #define mmOTG3_OTG_GLOBAL_CONTROL3_BASE_IDX                                                            2
8655 #define mmOTG3_OTG_GLOBAL_CONTROL4                                                                     0x1d14
8656 #define mmOTG3_OTG_GLOBAL_CONTROL4_BASE_IDX                                                            2
8657 #define mmOTG3_OTG_TRIG_MANUAL_CONTROL                                                                 0x1d15
8658 #define mmOTG3_OTG_TRIG_MANUAL_CONTROL_BASE_IDX                                                        2
8659 #define mmOTG3_OTG_MANUAL_FLOW_CONTROL                                                                 0x1d16
8660 #define mmOTG3_OTG_MANUAL_FLOW_CONTROL_BASE_IDX                                                        2
8661 #define mmOTG3_OTG_DRR_TIMING_INT_STATUS                                                               0x1d17
8662 #define mmOTG3_OTG_DRR_TIMING_INT_STATUS_BASE_IDX                                                      2
8663 #define mmOTG3_OTG_DRR_V_TOTAL_REACH_RANGE                                                             0x1d18
8664 #define mmOTG3_OTG_DRR_V_TOTAL_REACH_RANGE_BASE_IDX                                                    2
8665 #define mmOTG3_OTG_DRR_V_TOTAL_CHANGE                                                                  0x1d19
8666 #define mmOTG3_OTG_DRR_V_TOTAL_CHANGE_BASE_IDX                                                         2
8667 #define mmOTG3_OTG_DRR_TRIGGER_WINDOW                                                                  0x1d1a
8668 #define mmOTG3_OTG_DRR_TRIGGER_WINDOW_BASE_IDX                                                         2
8669 #define mmOTG3_OTG_DRR_CONTROL                                                                         0x1d1b
8670 #define mmOTG3_OTG_DRR_CONTROL_BASE_IDX                                                                2
8671 #define mmOTG3_OTG_M_CONST_DTO0                                                                        0x1d1c
8672 #define mmOTG3_OTG_M_CONST_DTO0_BASE_IDX                                                               2
8673 #define mmOTG3_OTG_M_CONST_DTO1                                                                        0x1d1d
8674 #define mmOTG3_OTG_M_CONST_DTO1_BASE_IDX                                                               2
8675 #define mmOTG3_OTG_REQUEST_CONTROL                                                                     0x1d1e
8676 #define mmOTG3_OTG_REQUEST_CONTROL_BASE_IDX                                                            2
8677 #define mmOTG3_OTG_DSC_START_POSITION                                                                  0x1d1f
8678 #define mmOTG3_OTG_DSC_START_POSITION_BASE_IDX                                                         2
8679 #define mmOTG3_OTG_PIPE_UPDATE_STATUS                                                                  0x1d20
8680 #define mmOTG3_OTG_PIPE_UPDATE_STATUS_BASE_IDX                                                         2
8681 #define mmOTG3_OTG_SPARE_REGISTER                                                                      0x1d22
8682 #define mmOTG3_OTG_SPARE_REGISTER_BASE_IDX                                                             2
8683 
8684 
8685 // addressBlock: dce_dc_optc_otg4_dispdec
8686 // base address: 0x800
8687 #define mmOTG4_OTG_H_TOTAL                                                                             0x1d2a
8688 #define mmOTG4_OTG_H_TOTAL_BASE_IDX                                                                    2
8689 #define mmOTG4_OTG_H_BLANK_START_END                                                                   0x1d2b
8690 #define mmOTG4_OTG_H_BLANK_START_END_BASE_IDX                                                          2
8691 #define mmOTG4_OTG_H_SYNC_A                                                                            0x1d2c
8692 #define mmOTG4_OTG_H_SYNC_A_BASE_IDX                                                                   2
8693 #define mmOTG4_OTG_H_SYNC_A_CNTL                                                                       0x1d2d
8694 #define mmOTG4_OTG_H_SYNC_A_CNTL_BASE_IDX                                                              2
8695 #define mmOTG4_OTG_H_TIMING_CNTL                                                                       0x1d2e
8696 #define mmOTG4_OTG_H_TIMING_CNTL_BASE_IDX                                                              2
8697 #define mmOTG4_OTG_V_TOTAL                                                                             0x1d2f
8698 #define mmOTG4_OTG_V_TOTAL_BASE_IDX                                                                    2
8699 #define mmOTG4_OTG_V_TOTAL_MIN                                                                         0x1d30
8700 #define mmOTG4_OTG_V_TOTAL_MIN_BASE_IDX                                                                2
8701 #define mmOTG4_OTG_V_TOTAL_MAX                                                                         0x1d31
8702 #define mmOTG4_OTG_V_TOTAL_MAX_BASE_IDX                                                                2
8703 #define mmOTG4_OTG_V_TOTAL_MID                                                                         0x1d32
8704 #define mmOTG4_OTG_V_TOTAL_MID_BASE_IDX                                                                2
8705 #define mmOTG4_OTG_V_TOTAL_CONTROL                                                                     0x1d33
8706 #define mmOTG4_OTG_V_TOTAL_CONTROL_BASE_IDX                                                            2
8707 #define mmOTG4_OTG_V_TOTAL_INT_STATUS                                                                  0x1d34
8708 #define mmOTG4_OTG_V_TOTAL_INT_STATUS_BASE_IDX                                                         2
8709 #define mmOTG4_OTG_VSYNC_NOM_INT_STATUS                                                                0x1d35
8710 #define mmOTG4_OTG_VSYNC_NOM_INT_STATUS_BASE_IDX                                                       2
8711 #define mmOTG4_OTG_V_BLANK_START_END                                                                   0x1d36
8712 #define mmOTG4_OTG_V_BLANK_START_END_BASE_IDX                                                          2
8713 #define mmOTG4_OTG_V_SYNC_A                                                                            0x1d37
8714 #define mmOTG4_OTG_V_SYNC_A_BASE_IDX                                                                   2
8715 #define mmOTG4_OTG_V_SYNC_A_CNTL                                                                       0x1d38
8716 #define mmOTG4_OTG_V_SYNC_A_CNTL_BASE_IDX                                                              2
8717 #define mmOTG4_OTG_TRIGA_CNTL                                                                          0x1d39
8718 #define mmOTG4_OTG_TRIGA_CNTL_BASE_IDX                                                                 2
8719 #define mmOTG4_OTG_TRIGA_MANUAL_TRIG                                                                   0x1d3a
8720 #define mmOTG4_OTG_TRIGA_MANUAL_TRIG_BASE_IDX                                                          2
8721 #define mmOTG4_OTG_TRIGB_CNTL                                                                          0x1d3b
8722 #define mmOTG4_OTG_TRIGB_CNTL_BASE_IDX                                                                 2
8723 #define mmOTG4_OTG_TRIGB_MANUAL_TRIG                                                                   0x1d3c
8724 #define mmOTG4_OTG_TRIGB_MANUAL_TRIG_BASE_IDX                                                          2
8725 #define mmOTG4_OTG_FORCE_COUNT_NOW_CNTL                                                                0x1d3d
8726 #define mmOTG4_OTG_FORCE_COUNT_NOW_CNTL_BASE_IDX                                                       2
8727 #define mmOTG4_OTG_FLOW_CONTROL                                                                        0x1d3e
8728 #define mmOTG4_OTG_FLOW_CONTROL_BASE_IDX                                                               2
8729 #define mmOTG4_OTG_STEREO_FORCE_NEXT_EYE                                                               0x1d3f
8730 #define mmOTG4_OTG_STEREO_FORCE_NEXT_EYE_BASE_IDX                                                      2
8731 #define mmOTG4_OTG_CONTROL                                                                             0x1d41
8732 #define mmOTG4_OTG_CONTROL_BASE_IDX                                                                    2
8733 #define mmOTG4_OTG_INTERLACE_CONTROL                                                                   0x1d44
8734 #define mmOTG4_OTG_INTERLACE_CONTROL_BASE_IDX                                                          2
8735 #define mmOTG4_OTG_INTERLACE_STATUS                                                                    0x1d45
8736 #define mmOTG4_OTG_INTERLACE_STATUS_BASE_IDX                                                           2
8737 #define mmOTG4_OTG_PIXEL_DATA_READBACK0                                                                0x1d47
8738 #define mmOTG4_OTG_PIXEL_DATA_READBACK0_BASE_IDX                                                       2
8739 #define mmOTG4_OTG_PIXEL_DATA_READBACK1                                                                0x1d48
8740 #define mmOTG4_OTG_PIXEL_DATA_READBACK1_BASE_IDX                                                       2
8741 #define mmOTG4_OTG_STATUS                                                                              0x1d49
8742 #define mmOTG4_OTG_STATUS_BASE_IDX                                                                     2
8743 #define mmOTG4_OTG_STATUS_POSITION                                                                     0x1d4a
8744 #define mmOTG4_OTG_STATUS_POSITION_BASE_IDX                                                            2
8745 #define mmOTG4_OTG_NOM_VERT_POSITION                                                                   0x1d4b
8746 #define mmOTG4_OTG_NOM_VERT_POSITION_BASE_IDX                                                          2
8747 #define mmOTG4_OTG_STATUS_FRAME_COUNT                                                                  0x1d4c
8748 #define mmOTG4_OTG_STATUS_FRAME_COUNT_BASE_IDX                                                         2
8749 #define mmOTG4_OTG_STATUS_VF_COUNT                                                                     0x1d4d
8750 #define mmOTG4_OTG_STATUS_VF_COUNT_BASE_IDX                                                            2
8751 #define mmOTG4_OTG_STATUS_HV_COUNT                                                                     0x1d4e
8752 #define mmOTG4_OTG_STATUS_HV_COUNT_BASE_IDX                                                            2
8753 #define mmOTG4_OTG_COUNT_CONTROL                                                                       0x1d4f
8754 #define mmOTG4_OTG_COUNT_CONTROL_BASE_IDX                                                              2
8755 #define mmOTG4_OTG_COUNT_RESET                                                                         0x1d50
8756 #define mmOTG4_OTG_COUNT_RESET_BASE_IDX                                                                2
8757 #define mmOTG4_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE                                                        0x1d51
8758 #define mmOTG4_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX                                               2
8759 #define mmOTG4_OTG_VERT_SYNC_CONTROL                                                                   0x1d52
8760 #define mmOTG4_OTG_VERT_SYNC_CONTROL_BASE_IDX                                                          2
8761 #define mmOTG4_OTG_STEREO_STATUS                                                                       0x1d53
8762 #define mmOTG4_OTG_STEREO_STATUS_BASE_IDX                                                              2
8763 #define mmOTG4_OTG_STEREO_CONTROL                                                                      0x1d54
8764 #define mmOTG4_OTG_STEREO_CONTROL_BASE_IDX                                                             2
8765 #define mmOTG4_OTG_SNAPSHOT_STATUS                                                                     0x1d55
8766 #define mmOTG4_OTG_SNAPSHOT_STATUS_BASE_IDX                                                            2
8767 #define mmOTG4_OTG_SNAPSHOT_CONTROL                                                                    0x1d56
8768 #define mmOTG4_OTG_SNAPSHOT_CONTROL_BASE_IDX                                                           2
8769 #define mmOTG4_OTG_SNAPSHOT_POSITION                                                                   0x1d57
8770 #define mmOTG4_OTG_SNAPSHOT_POSITION_BASE_IDX                                                          2
8771 #define mmOTG4_OTG_SNAPSHOT_FRAME                                                                      0x1d58
8772 #define mmOTG4_OTG_SNAPSHOT_FRAME_BASE_IDX                                                             2
8773 #define mmOTG4_OTG_INTERRUPT_CONTROL                                                                   0x1d59
8774 #define mmOTG4_OTG_INTERRUPT_CONTROL_BASE_IDX                                                          2
8775 #define mmOTG4_OTG_UPDATE_LOCK                                                                         0x1d5a
8776 #define mmOTG4_OTG_UPDATE_LOCK_BASE_IDX                                                                2
8777 #define mmOTG4_OTG_DOUBLE_BUFFER_CONTROL                                                               0x1d5b
8778 #define mmOTG4_OTG_DOUBLE_BUFFER_CONTROL_BASE_IDX                                                      2
8779 #define mmOTG4_OTG_MASTER_EN                                                                           0x1d5c
8780 #define mmOTG4_OTG_MASTER_EN_BASE_IDX                                                                  2
8781 #define mmOTG4_OTG_BLANK_DATA_COLOR                                                                    0x1d5e
8782 #define mmOTG4_OTG_BLANK_DATA_COLOR_BASE_IDX                                                           2
8783 #define mmOTG4_OTG_BLANK_DATA_COLOR_EXT                                                                0x1d5f
8784 #define mmOTG4_OTG_BLANK_DATA_COLOR_EXT_BASE_IDX                                                       2
8785 #define mmOTG4_OTG_VERTICAL_INTERRUPT0_POSITION                                                        0x1d62
8786 #define mmOTG4_OTG_VERTICAL_INTERRUPT0_POSITION_BASE_IDX                                               2
8787 #define mmOTG4_OTG_VERTICAL_INTERRUPT0_CONTROL                                                         0x1d63
8788 #define mmOTG4_OTG_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX                                                2
8789 #define mmOTG4_OTG_VERTICAL_INTERRUPT1_POSITION                                                        0x1d64
8790 #define mmOTG4_OTG_VERTICAL_INTERRUPT1_POSITION_BASE_IDX                                               2
8791 #define mmOTG4_OTG_VERTICAL_INTERRUPT1_CONTROL                                                         0x1d65
8792 #define mmOTG4_OTG_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX                                                2
8793 #define mmOTG4_OTG_VERTICAL_INTERRUPT2_POSITION                                                        0x1d66
8794 #define mmOTG4_OTG_VERTICAL_INTERRUPT2_POSITION_BASE_IDX                                               2
8795 #define mmOTG4_OTG_VERTICAL_INTERRUPT2_CONTROL                                                         0x1d67
8796 #define mmOTG4_OTG_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX                                                2
8797 #define mmOTG4_OTG_CRC_CNTL                                                                            0x1d68
8798 #define mmOTG4_OTG_CRC_CNTL_BASE_IDX                                                                   2
8799 #define mmOTG4_OTG_CRC_CNTL2                                                                           0x1d69
8800 #define mmOTG4_OTG_CRC_CNTL2_BASE_IDX                                                                  2
8801 #define mmOTG4_OTG_CRC0_WINDOWA_X_CONTROL                                                              0x1d6a
8802 #define mmOTG4_OTG_CRC0_WINDOWA_X_CONTROL_BASE_IDX                                                     2
8803 #define mmOTG4_OTG_CRC0_WINDOWA_Y_CONTROL                                                              0x1d6b
8804 #define mmOTG4_OTG_CRC0_WINDOWA_Y_CONTROL_BASE_IDX                                                     2
8805 #define mmOTG4_OTG_CRC0_WINDOWB_X_CONTROL                                                              0x1d6c
8806 #define mmOTG4_OTG_CRC0_WINDOWB_X_CONTROL_BASE_IDX                                                     2
8807 #define mmOTG4_OTG_CRC0_WINDOWB_Y_CONTROL                                                              0x1d6d
8808 #define mmOTG4_OTG_CRC0_WINDOWB_Y_CONTROL_BASE_IDX                                                     2
8809 #define mmOTG4_OTG_CRC0_DATA_RG                                                                        0x1d6e
8810 #define mmOTG4_OTG_CRC0_DATA_RG_BASE_IDX                                                               2
8811 #define mmOTG4_OTG_CRC0_DATA_B                                                                         0x1d6f
8812 #define mmOTG4_OTG_CRC0_DATA_B_BASE_IDX                                                                2
8813 #define mmOTG4_OTG_CRC1_WINDOWA_X_CONTROL                                                              0x1d70
8814 #define mmOTG4_OTG_CRC1_WINDOWA_X_CONTROL_BASE_IDX                                                     2
8815 #define mmOTG4_OTG_CRC1_WINDOWA_Y_CONTROL                                                              0x1d71
8816 #define mmOTG4_OTG_CRC1_WINDOWA_Y_CONTROL_BASE_IDX                                                     2
8817 #define mmOTG4_OTG_CRC1_WINDOWB_X_CONTROL                                                              0x1d72
8818 #define mmOTG4_OTG_CRC1_WINDOWB_X_CONTROL_BASE_IDX                                                     2
8819 #define mmOTG4_OTG_CRC1_WINDOWB_Y_CONTROL                                                              0x1d73
8820 #define mmOTG4_OTG_CRC1_WINDOWB_Y_CONTROL_BASE_IDX                                                     2
8821 #define mmOTG4_OTG_CRC1_DATA_RG                                                                        0x1d74
8822 #define mmOTG4_OTG_CRC1_DATA_RG_BASE_IDX                                                               2
8823 #define mmOTG4_OTG_CRC1_DATA_B                                                                         0x1d75
8824 #define mmOTG4_OTG_CRC1_DATA_B_BASE_IDX                                                                2
8825 #define mmOTG4_OTG_CRC2_DATA_RG                                                                        0x1d76
8826 #define mmOTG4_OTG_CRC2_DATA_RG_BASE_IDX                                                               2
8827 #define mmOTG4_OTG_CRC2_DATA_B                                                                         0x1d77
8828 #define mmOTG4_OTG_CRC2_DATA_B_BASE_IDX                                                                2
8829 #define mmOTG4_OTG_CRC3_DATA_RG                                                                        0x1d78
8830 #define mmOTG4_OTG_CRC3_DATA_RG_BASE_IDX                                                               2
8831 #define mmOTG4_OTG_CRC3_DATA_B                                                                         0x1d79
8832 #define mmOTG4_OTG_CRC3_DATA_B_BASE_IDX                                                                2
8833 #define mmOTG4_OTG_CRC_SIG_RED_GREEN_MASK                                                              0x1d7a
8834 #define mmOTG4_OTG_CRC_SIG_RED_GREEN_MASK_BASE_IDX                                                     2
8835 #define mmOTG4_OTG_CRC_SIG_BLUE_CONTROL_MASK                                                           0x1d7b
8836 #define mmOTG4_OTG_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX                                                  2
8837 #define mmOTG4_OTG_STATIC_SCREEN_CONTROL                                                               0x1d82
8838 #define mmOTG4_OTG_STATIC_SCREEN_CONTROL_BASE_IDX                                                      2
8839 #define mmOTG4_OTG_3D_STRUCTURE_CONTROL                                                                0x1d83
8840 #define mmOTG4_OTG_3D_STRUCTURE_CONTROL_BASE_IDX                                                       2
8841 #define mmOTG4_OTG_GSL_VSYNC_GAP                                                                       0x1d84
8842 #define mmOTG4_OTG_GSL_VSYNC_GAP_BASE_IDX                                                              2
8843 #define mmOTG4_OTG_MASTER_UPDATE_MODE                                                                  0x1d85
8844 #define mmOTG4_OTG_MASTER_UPDATE_MODE_BASE_IDX                                                         2
8845 #define mmOTG4_OTG_CLOCK_CONTROL                                                                       0x1d86
8846 #define mmOTG4_OTG_CLOCK_CONTROL_BASE_IDX                                                              2
8847 #define mmOTG4_OTG_VSTARTUP_PARAM                                                                      0x1d87
8848 #define mmOTG4_OTG_VSTARTUP_PARAM_BASE_IDX                                                             2
8849 #define mmOTG4_OTG_VUPDATE_PARAM                                                                       0x1d88
8850 #define mmOTG4_OTG_VUPDATE_PARAM_BASE_IDX                                                              2
8851 #define mmOTG4_OTG_VREADY_PARAM                                                                        0x1d89
8852 #define mmOTG4_OTG_VREADY_PARAM_BASE_IDX                                                               2
8853 #define mmOTG4_OTG_GLOBAL_SYNC_STATUS                                                                  0x1d8a
8854 #define mmOTG4_OTG_GLOBAL_SYNC_STATUS_BASE_IDX                                                         2
8855 #define mmOTG4_OTG_MASTER_UPDATE_LOCK                                                                  0x1d8b
8856 #define mmOTG4_OTG_MASTER_UPDATE_LOCK_BASE_IDX                                                         2
8857 #define mmOTG4_OTG_GSL_CONTROL                                                                         0x1d8c
8858 #define mmOTG4_OTG_GSL_CONTROL_BASE_IDX                                                                2
8859 #define mmOTG4_OTG_GSL_WINDOW_X                                                                        0x1d8d
8860 #define mmOTG4_OTG_GSL_WINDOW_X_BASE_IDX                                                               2
8861 #define mmOTG4_OTG_GSL_WINDOW_Y                                                                        0x1d8e
8862 #define mmOTG4_OTG_GSL_WINDOW_Y_BASE_IDX                                                               2
8863 #define mmOTG4_OTG_VUPDATE_KEEPOUT                                                                     0x1d8f
8864 #define mmOTG4_OTG_VUPDATE_KEEPOUT_BASE_IDX                                                            2
8865 #define mmOTG4_OTG_GLOBAL_CONTROL0                                                                     0x1d90
8866 #define mmOTG4_OTG_GLOBAL_CONTROL0_BASE_IDX                                                            2
8867 #define mmOTG4_OTG_GLOBAL_CONTROL1                                                                     0x1d91
8868 #define mmOTG4_OTG_GLOBAL_CONTROL1_BASE_IDX                                                            2
8869 #define mmOTG4_OTG_GLOBAL_CONTROL2                                                                     0x1d92
8870 #define mmOTG4_OTG_GLOBAL_CONTROL2_BASE_IDX                                                            2
8871 #define mmOTG4_OTG_GLOBAL_CONTROL3                                                                     0x1d93
8872 #define mmOTG4_OTG_GLOBAL_CONTROL3_BASE_IDX                                                            2
8873 #define mmOTG4_OTG_GLOBAL_CONTROL4                                                                     0x1d94
8874 #define mmOTG4_OTG_GLOBAL_CONTROL4_BASE_IDX                                                            2
8875 #define mmOTG4_OTG_TRIG_MANUAL_CONTROL                                                                 0x1d95
8876 #define mmOTG4_OTG_TRIG_MANUAL_CONTROL_BASE_IDX                                                        2
8877 #define mmOTG4_OTG_MANUAL_FLOW_CONTROL                                                                 0x1d96
8878 #define mmOTG4_OTG_MANUAL_FLOW_CONTROL_BASE_IDX                                                        2
8879 #define mmOTG4_OTG_DRR_TIMING_INT_STATUS                                                               0x1d97
8880 #define mmOTG4_OTG_DRR_TIMING_INT_STATUS_BASE_IDX                                                      2
8881 #define mmOTG4_OTG_DRR_V_TOTAL_REACH_RANGE                                                             0x1d98
8882 #define mmOTG4_OTG_DRR_V_TOTAL_REACH_RANGE_BASE_IDX                                                    2
8883 #define mmOTG4_OTG_DRR_V_TOTAL_CHANGE                                                                  0x1d99
8884 #define mmOTG4_OTG_DRR_V_TOTAL_CHANGE_BASE_IDX                                                         2
8885 #define mmOTG4_OTG_DRR_TRIGGER_WINDOW                                                                  0x1d9a
8886 #define mmOTG4_OTG_DRR_TRIGGER_WINDOW_BASE_IDX                                                         2
8887 #define mmOTG4_OTG_DRR_CONTROL                                                                         0x1d9b
8888 #define mmOTG4_OTG_DRR_CONTROL_BASE_IDX                                                                2
8889 #define mmOTG4_OTG_M_CONST_DTO0                                                                        0x1d9c
8890 #define mmOTG4_OTG_M_CONST_DTO0_BASE_IDX                                                               2
8891 #define mmOTG4_OTG_M_CONST_DTO1                                                                        0x1d9d
8892 #define mmOTG4_OTG_M_CONST_DTO1_BASE_IDX                                                               2
8893 #define mmOTG4_OTG_REQUEST_CONTROL                                                                     0x1d9e
8894 #define mmOTG4_OTG_REQUEST_CONTROL_BASE_IDX                                                            2
8895 #define mmOTG4_OTG_DSC_START_POSITION                                                                  0x1d9f
8896 #define mmOTG4_OTG_DSC_START_POSITION_BASE_IDX                                                         2
8897 #define mmOTG4_OTG_PIPE_UPDATE_STATUS                                                                  0x1da0
8898 #define mmOTG4_OTG_PIPE_UPDATE_STATUS_BASE_IDX                                                         2
8899 #define mmOTG4_OTG_SPARE_REGISTER                                                                      0x1da2
8900 #define mmOTG4_OTG_SPARE_REGISTER_BASE_IDX                                                             2
8901 
8902 
8903 // addressBlock: dce_dc_optc_optc_misc_dispdec
8904 // base address: 0x0
8905 #define mmDWB_SOURCE_SELECT                                                                            0x1e2a
8906 #define mmDWB_SOURCE_SELECT_BASE_IDX                                                                   2
8907 #define mmGSL_SOURCE_SELECT                                                                            0x1e2b
8908 #define mmGSL_SOURCE_SELECT_BASE_IDX                                                                   2
8909 #define mmOPTC_CLOCK_CONTROL                                                                           0x1e2c
8910 #define mmOPTC_CLOCK_CONTROL_BASE_IDX                                                                  2
8911 #define mmODM_MEM_PWR_CTRL                                                                             0x1e2d
8912 #define mmODM_MEM_PWR_CTRL_BASE_IDX                                                                    2
8913 #define mmODM_MEM_PWR_CTRL2                                                                            0x1e2e
8914 #define mmODM_MEM_PWR_CTRL2_BASE_IDX                                                                   2
8915 #define mmODM_MEM_PWR_CTRL3                                                                            0x1e2f
8916 #define mmODM_MEM_PWR_CTRL3_BASE_IDX                                                                   2
8917 #define mmODM_MEM_PWR_STATUS                                                                           0x1e30
8918 #define mmODM_MEM_PWR_STATUS_BASE_IDX                                                                  2
8919 #define mmOPTC_MISC_SPARE_REGISTER                                                                     0x1e31
8920 #define mmOPTC_MISC_SPARE_REGISTER_BASE_IDX                                                            2
8921 
8922 
8923 // addressBlock: dce_dc_optc_optc_dcperfmon_dc_perfmon_dispdec
8924 // base address: 0x79a8
8925 #define mmDC_PERFMON17_PERFCOUNTER_CNTL                                                                0x1e6a
8926 #define mmDC_PERFMON17_PERFCOUNTER_CNTL_BASE_IDX                                                       2
8927 #define mmDC_PERFMON17_PERFCOUNTER_CNTL2                                                               0x1e6b
8928 #define mmDC_PERFMON17_PERFCOUNTER_CNTL2_BASE_IDX                                                      2
8929 #define mmDC_PERFMON17_PERFCOUNTER_STATE                                                               0x1e6c
8930 #define mmDC_PERFMON17_PERFCOUNTER_STATE_BASE_IDX                                                      2
8931 #define mmDC_PERFMON17_PERFMON_CNTL                                                                    0x1e6d
8932 #define mmDC_PERFMON17_PERFMON_CNTL_BASE_IDX                                                           2
8933 #define mmDC_PERFMON17_PERFMON_CNTL2                                                                   0x1e6e
8934 #define mmDC_PERFMON17_PERFMON_CNTL2_BASE_IDX                                                          2
8935 #define mmDC_PERFMON17_PERFMON_CVALUE_INT_MISC                                                         0x1e6f
8936 #define mmDC_PERFMON17_PERFMON_CVALUE_INT_MISC_BASE_IDX                                                2
8937 #define mmDC_PERFMON17_PERFMON_CVALUE_LOW                                                              0x1e70
8938 #define mmDC_PERFMON17_PERFMON_CVALUE_LOW_BASE_IDX                                                     2
8939 #define mmDC_PERFMON17_PERFMON_HI                                                                      0x1e71
8940 #define mmDC_PERFMON17_PERFMON_HI_BASE_IDX                                                             2
8941 #define mmDC_PERFMON17_PERFMON_LOW                                                                     0x1e72
8942 #define mmDC_PERFMON17_PERFMON_LOW_BASE_IDX                                                            2
8943 
8944 
8945 // addressBlock: dce_dc_dio_dout_i2c_dispdec
8946 // base address: 0x0
8947 #define mmDC_I2C_CONTROL                                                                               0x1e98
8948 #define mmDC_I2C_CONTROL_BASE_IDX                                                                      2
8949 #define mmDC_I2C_ARBITRATION                                                                           0x1e99
8950 #define mmDC_I2C_ARBITRATION_BASE_IDX                                                                  2
8951 #define mmDC_I2C_INTERRUPT_CONTROL                                                                     0x1e9a
8952 #define mmDC_I2C_INTERRUPT_CONTROL_BASE_IDX                                                            2
8953 #define mmDC_I2C_SW_STATUS                                                                             0x1e9b
8954 #define mmDC_I2C_SW_STATUS_BASE_IDX                                                                    2
8955 #define mmDC_I2C_DDC1_HW_STATUS                                                                        0x1e9c
8956 #define mmDC_I2C_DDC1_HW_STATUS_BASE_IDX                                                               2
8957 #define mmDC_I2C_DDC2_HW_STATUS                                                                        0x1e9d
8958 #define mmDC_I2C_DDC2_HW_STATUS_BASE_IDX                                                               2
8959 #define mmDC_I2C_DDC3_HW_STATUS                                                                        0x1e9e
8960 #define mmDC_I2C_DDC3_HW_STATUS_BASE_IDX                                                               2
8961 #define mmDC_I2C_DDC4_HW_STATUS                                                                        0x1e9f
8962 #define mmDC_I2C_DDC4_HW_STATUS_BASE_IDX                                                               2
8963 #define mmDC_I2C_DDC5_HW_STATUS                                                                        0x1ea0
8964 #define mmDC_I2C_DDC5_HW_STATUS_BASE_IDX                                                               2
8965 #define mmDC_I2C_DDC1_SPEED                                                                            0x1ea2
8966 #define mmDC_I2C_DDC1_SPEED_BASE_IDX                                                                   2
8967 #define mmDC_I2C_DDC1_SETUP                                                                            0x1ea3
8968 #define mmDC_I2C_DDC1_SETUP_BASE_IDX                                                                   2
8969 #define mmDC_I2C_DDC2_SPEED                                                                            0x1ea4
8970 #define mmDC_I2C_DDC2_SPEED_BASE_IDX                                                                   2
8971 #define mmDC_I2C_DDC2_SETUP                                                                            0x1ea5
8972 #define mmDC_I2C_DDC2_SETUP_BASE_IDX                                                                   2
8973 #define mmDC_I2C_DDC3_SPEED                                                                            0x1ea6
8974 #define mmDC_I2C_DDC3_SPEED_BASE_IDX                                                                   2
8975 #define mmDC_I2C_DDC3_SETUP                                                                            0x1ea7
8976 #define mmDC_I2C_DDC3_SETUP_BASE_IDX                                                                   2
8977 #define mmDC_I2C_DDC4_SPEED                                                                            0x1ea8
8978 #define mmDC_I2C_DDC4_SPEED_BASE_IDX                                                                   2
8979 #define mmDC_I2C_DDC4_SETUP                                                                            0x1ea9
8980 #define mmDC_I2C_DDC4_SETUP_BASE_IDX                                                                   2
8981 #define mmDC_I2C_DDC5_SPEED                                                                            0x1eaa
8982 #define mmDC_I2C_DDC5_SPEED_BASE_IDX                                                                   2
8983 #define mmDC_I2C_DDC5_SETUP                                                                            0x1eab
8984 #define mmDC_I2C_DDC5_SETUP_BASE_IDX                                                                   2
8985 #define mmDC_I2C_TRANSACTION0                                                                          0x1eae
8986 #define mmDC_I2C_TRANSACTION0_BASE_IDX                                                                 2
8987 #define mmDC_I2C_TRANSACTION1                                                                          0x1eaf
8988 #define mmDC_I2C_TRANSACTION1_BASE_IDX                                                                 2
8989 #define mmDC_I2C_TRANSACTION2                                                                          0x1eb0
8990 #define mmDC_I2C_TRANSACTION2_BASE_IDX                                                                 2
8991 #define mmDC_I2C_TRANSACTION3                                                                          0x1eb1
8992 #define mmDC_I2C_TRANSACTION3_BASE_IDX                                                                 2
8993 #define mmDC_I2C_DATA                                                                                  0x1eb2
8994 #define mmDC_I2C_DATA_BASE_IDX                                                                         2
8995 #define mmDC_I2C_EDID_DETECT_CTRL                                                                      0x1eb6
8996 #define mmDC_I2C_EDID_DETECT_CTRL_BASE_IDX                                                             2
8997 #define mmDC_I2C_READ_REQUEST_INTERRUPT                                                                0x1eb7
8998 #define mmDC_I2C_READ_REQUEST_INTERRUPT_BASE_IDX                                                       2
8999 
9000 
9001 // addressBlock: dce_dc_dio_dio_misc_dispdec
9002 // base address: 0x0
9003 #define mmDIO_SCRATCH0                                                                                 0x1eca
9004 #define mmDIO_SCRATCH0_BASE_IDX                                                                        2
9005 #define mmDIO_SCRATCH1                                                                                 0x1ecb
9006 #define mmDIO_SCRATCH1_BASE_IDX                                                                        2
9007 #define mmDIO_SCRATCH2                                                                                 0x1ecc
9008 #define mmDIO_SCRATCH2_BASE_IDX                                                                        2
9009 #define mmDIO_SCRATCH3                                                                                 0x1ecd
9010 #define mmDIO_SCRATCH3_BASE_IDX                                                                        2
9011 #define mmDIO_SCRATCH4                                                                                 0x1ece
9012 #define mmDIO_SCRATCH4_BASE_IDX                                                                        2
9013 #define mmDIO_SCRATCH5                                                                                 0x1ecf
9014 #define mmDIO_SCRATCH5_BASE_IDX                                                                        2
9015 #define mmDIO_SCRATCH6                                                                                 0x1ed0
9016 #define mmDIO_SCRATCH6_BASE_IDX                                                                        2
9017 #define mmDIO_SCRATCH7                                                                                 0x1ed1
9018 #define mmDIO_SCRATCH7_BASE_IDX                                                                        2
9019 #define mmDIO_MEM_PWR_STATUS                                                                           0x1edd
9020 #define mmDIO_MEM_PWR_STATUS_BASE_IDX                                                                  2
9021 #define mmDIO_MEM_PWR_CTRL                                                                             0x1ede
9022 #define mmDIO_MEM_PWR_CTRL_BASE_IDX                                                                    2
9023 #define mmDIO_MEM_PWR_CTRL2                                                                            0x1edf
9024 #define mmDIO_MEM_PWR_CTRL2_BASE_IDX                                                                   2
9025 #define mmDIO_CLK_CNTL                                                                                 0x1ee0
9026 #define mmDIO_CLK_CNTL_BASE_IDX                                                                        2
9027 #define mmDIO_POWER_MANAGEMENT_CNTL                                                                    0x1ee4
9028 #define mmDIO_POWER_MANAGEMENT_CNTL_BASE_IDX                                                           2
9029 #define mmDIG_SOFT_RESET                                                                               0x1eee
9030 #define mmDIG_SOFT_RESET_BASE_IDX                                                                      2
9031 #define mmDIO_CLK_CNTL2                                                                                0x1ef2
9032 #define mmDIO_CLK_CNTL2_BASE_IDX                                                                       2
9033 #define mmDIO_CLK_CNTL3                                                                                0x1ef3
9034 #define mmDIO_CLK_CNTL3_BASE_IDX                                                                       2
9035 #define mmDIO_HDMI_RXSTATUS_TIMER_CONTROL                                                              0x1eff
9036 #define mmDIO_HDMI_RXSTATUS_TIMER_CONTROL_BASE_IDX                                                     2
9037 #define mmDIO_GENERIC_INTERRUPT_MESSAGE                                                                0x1f02
9038 #define mmDIO_GENERIC_INTERRUPT_MESSAGE_BASE_IDX                                                       2
9039 #define mmDIO_GENERIC_INTERRUPT_CLEAR                                                                  0x1f03
9040 #define mmDIO_GENERIC_INTERRUPT_CLEAR_BASE_IDX                                                         2
9041 
9042 
9043 // addressBlock: dce_dc_dio_hpd0_dispdec
9044 // base address: 0x0
9045 #define mmHPD0_DC_HPD_INT_STATUS                                                                       0x1f14
9046 #define mmHPD0_DC_HPD_INT_STATUS_BASE_IDX                                                              2
9047 #define mmHPD0_DC_HPD_INT_CONTROL                                                                      0x1f15
9048 #define mmHPD0_DC_HPD_INT_CONTROL_BASE_IDX                                                             2
9049 #define mmHPD0_DC_HPD_CONTROL                                                                          0x1f16
9050 #define mmHPD0_DC_HPD_CONTROL_BASE_IDX                                                                 2
9051 #define mmHPD0_DC_HPD_FAST_TRAIN_CNTL                                                                  0x1f17
9052 #define mmHPD0_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX                                                         2
9053 #define mmHPD0_DC_HPD_TOGGLE_FILT_CNTL                                                                 0x1f18
9054 #define mmHPD0_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX                                                        2
9055 
9056 
9057 // addressBlock: dce_dc_dio_hpd1_dispdec
9058 // base address: 0x20
9059 #define mmHPD1_DC_HPD_INT_STATUS                                                                       0x1f1c
9060 #define mmHPD1_DC_HPD_INT_STATUS_BASE_IDX                                                              2
9061 #define mmHPD1_DC_HPD_INT_CONTROL                                                                      0x1f1d
9062 #define mmHPD1_DC_HPD_INT_CONTROL_BASE_IDX                                                             2
9063 #define mmHPD1_DC_HPD_CONTROL                                                                          0x1f1e
9064 #define mmHPD1_DC_HPD_CONTROL_BASE_IDX                                                                 2
9065 #define mmHPD1_DC_HPD_FAST_TRAIN_CNTL                                                                  0x1f1f
9066 #define mmHPD1_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX                                                         2
9067 #define mmHPD1_DC_HPD_TOGGLE_FILT_CNTL                                                                 0x1f20
9068 #define mmHPD1_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX                                                        2
9069 
9070 
9071 // addressBlock: dce_dc_dio_hpd2_dispdec
9072 // base address: 0x40
9073 #define mmHPD2_DC_HPD_INT_STATUS                                                                       0x1f24
9074 #define mmHPD2_DC_HPD_INT_STATUS_BASE_IDX                                                              2
9075 #define mmHPD2_DC_HPD_INT_CONTROL                                                                      0x1f25
9076 #define mmHPD2_DC_HPD_INT_CONTROL_BASE_IDX                                                             2
9077 #define mmHPD2_DC_HPD_CONTROL                                                                          0x1f26
9078 #define mmHPD2_DC_HPD_CONTROL_BASE_IDX                                                                 2
9079 #define mmHPD2_DC_HPD_FAST_TRAIN_CNTL                                                                  0x1f27
9080 #define mmHPD2_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX                                                         2
9081 #define mmHPD2_DC_HPD_TOGGLE_FILT_CNTL                                                                 0x1f28
9082 #define mmHPD2_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX                                                        2
9083 
9084 
9085 // addressBlock: dce_dc_dio_hpd3_dispdec
9086 // base address: 0x60
9087 #define mmHPD3_DC_HPD_INT_STATUS                                                                       0x1f2c
9088 #define mmHPD3_DC_HPD_INT_STATUS_BASE_IDX                                                              2
9089 #define mmHPD3_DC_HPD_INT_CONTROL                                                                      0x1f2d
9090 #define mmHPD3_DC_HPD_INT_CONTROL_BASE_IDX                                                             2
9091 #define mmHPD3_DC_HPD_CONTROL                                                                          0x1f2e
9092 #define mmHPD3_DC_HPD_CONTROL_BASE_IDX                                                                 2
9093 #define mmHPD3_DC_HPD_FAST_TRAIN_CNTL                                                                  0x1f2f
9094 #define mmHPD3_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX                                                         2
9095 #define mmHPD3_DC_HPD_TOGGLE_FILT_CNTL                                                                 0x1f30
9096 #define mmHPD3_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX                                                        2
9097 
9098 
9099 // addressBlock: dce_dc_dio_hpd4_dispdec
9100 // base address: 0x80
9101 #define mmHPD4_DC_HPD_INT_STATUS                                                                       0x1f34
9102 #define mmHPD4_DC_HPD_INT_STATUS_BASE_IDX                                                              2
9103 #define mmHPD4_DC_HPD_INT_CONTROL                                                                      0x1f35
9104 #define mmHPD4_DC_HPD_INT_CONTROL_BASE_IDX                                                             2
9105 #define mmHPD4_DC_HPD_CONTROL                                                                          0x1f36
9106 #define mmHPD4_DC_HPD_CONTROL_BASE_IDX                                                                 2
9107 #define mmHPD4_DC_HPD_FAST_TRAIN_CNTL                                                                  0x1f37
9108 #define mmHPD4_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX                                                         2
9109 #define mmHPD4_DC_HPD_TOGGLE_FILT_CNTL                                                                 0x1f38
9110 #define mmHPD4_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX                                                        2
9111 
9112 
9113 // addressBlock: dce_dc_dio_dio_dcperfmon_dc_perfmon_dispdec
9114 // base address: 0x7d10
9115 #define mmDC_PERFMON18_PERFCOUNTER_CNTL                                                                0x1f44
9116 #define mmDC_PERFMON18_PERFCOUNTER_CNTL_BASE_IDX                                                       2
9117 #define mmDC_PERFMON18_PERFCOUNTER_CNTL2                                                               0x1f45
9118 #define mmDC_PERFMON18_PERFCOUNTER_CNTL2_BASE_IDX                                                      2
9119 #define mmDC_PERFMON18_PERFCOUNTER_STATE                                                               0x1f46
9120 #define mmDC_PERFMON18_PERFCOUNTER_STATE_BASE_IDX                                                      2
9121 #define mmDC_PERFMON18_PERFMON_CNTL                                                                    0x1f47
9122 #define mmDC_PERFMON18_PERFMON_CNTL_BASE_IDX                                                           2
9123 #define mmDC_PERFMON18_PERFMON_CNTL2                                                                   0x1f48
9124 #define mmDC_PERFMON18_PERFMON_CNTL2_BASE_IDX                                                          2
9125 #define mmDC_PERFMON18_PERFMON_CVALUE_INT_MISC                                                         0x1f49
9126 #define mmDC_PERFMON18_PERFMON_CVALUE_INT_MISC_BASE_IDX                                                2
9127 #define mmDC_PERFMON18_PERFMON_CVALUE_LOW                                                              0x1f4a
9128 #define mmDC_PERFMON18_PERFMON_CVALUE_LOW_BASE_IDX                                                     2
9129 #define mmDC_PERFMON18_PERFMON_HI                                                                      0x1f4b
9130 #define mmDC_PERFMON18_PERFMON_HI_BASE_IDX                                                             2
9131 #define mmDC_PERFMON18_PERFMON_LOW                                                                     0x1f4c
9132 #define mmDC_PERFMON18_PERFMON_LOW_BASE_IDX                                                            2
9133 
9134 
9135 // addressBlock: dce_dc_dio_dp_aux0_dispdec
9136 // base address: 0x0
9137 #define mmDP_AUX0_AUX_CONTROL                                                                          0x1f50
9138 #define mmDP_AUX0_AUX_CONTROL_BASE_IDX                                                                 2
9139 #define mmDP_AUX0_AUX_SW_CONTROL                                                                       0x1f51
9140 #define mmDP_AUX0_AUX_SW_CONTROL_BASE_IDX                                                              2
9141 #define mmDP_AUX0_AUX_ARB_CONTROL                                                                      0x1f52
9142 #define mmDP_AUX0_AUX_ARB_CONTROL_BASE_IDX                                                             2
9143 #define mmDP_AUX0_AUX_INTERRUPT_CONTROL                                                                0x1f53
9144 #define mmDP_AUX0_AUX_INTERRUPT_CONTROL_BASE_IDX                                                       2
9145 #define mmDP_AUX0_AUX_SW_STATUS                                                                        0x1f54
9146 #define mmDP_AUX0_AUX_SW_STATUS_BASE_IDX                                                               2
9147 #define mmDP_AUX0_AUX_LS_STATUS                                                                        0x1f55
9148 #define mmDP_AUX0_AUX_LS_STATUS_BASE_IDX                                                               2
9149 #define mmDP_AUX0_AUX_SW_DATA                                                                          0x1f56
9150 #define mmDP_AUX0_AUX_SW_DATA_BASE_IDX                                                                 2
9151 #define mmDP_AUX0_AUX_LS_DATA                                                                          0x1f57
9152 #define mmDP_AUX0_AUX_LS_DATA_BASE_IDX                                                                 2
9153 #define mmDP_AUX0_AUX_DPHY_TX_REF_CONTROL                                                              0x1f58
9154 #define mmDP_AUX0_AUX_DPHY_TX_REF_CONTROL_BASE_IDX                                                     2
9155 #define mmDP_AUX0_AUX_DPHY_TX_CONTROL                                                                  0x1f59
9156 #define mmDP_AUX0_AUX_DPHY_TX_CONTROL_BASE_IDX                                                         2
9157 #define mmDP_AUX0_AUX_DPHY_RX_CONTROL0                                                                 0x1f5a
9158 #define mmDP_AUX0_AUX_DPHY_RX_CONTROL0_BASE_IDX                                                        2
9159 #define mmDP_AUX0_AUX_DPHY_RX_CONTROL1                                                                 0x1f5b
9160 #define mmDP_AUX0_AUX_DPHY_RX_CONTROL1_BASE_IDX                                                        2
9161 #define mmDP_AUX0_AUX_DPHY_TX_STATUS                                                                   0x1f5c
9162 #define mmDP_AUX0_AUX_DPHY_TX_STATUS_BASE_IDX                                                          2
9163 #define mmDP_AUX0_AUX_DPHY_RX_STATUS                                                                   0x1f5d
9164 #define mmDP_AUX0_AUX_DPHY_RX_STATUS_BASE_IDX                                                          2
9165 #define mmDP_AUX0_AUX_GTC_SYNC_CONTROL                                                                 0x1f5e
9166 #define mmDP_AUX0_AUX_GTC_SYNC_CONTROL_BASE_IDX                                                        2
9167 #define mmDP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL                                                           0x1f5f
9168 #define mmDP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL_BASE_IDX                                                  2
9169 #define mmDP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS                                                       0x1f60
9170 #define mmDP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS_BASE_IDX                                              2
9171 #define mmDP_AUX0_AUX_GTC_SYNC_STATUS                                                                  0x1f61
9172 #define mmDP_AUX0_AUX_GTC_SYNC_STATUS_BASE_IDX                                                         2
9173 #define mmDP_AUX0_AUX_PHY_WAKE_CNTL                                                                    0x1f66
9174 #define mmDP_AUX0_AUX_PHY_WAKE_CNTL_BASE_IDX                                                           2
9175 
9176 
9177 // addressBlock: dce_dc_dio_dp_aux1_dispdec
9178 // base address: 0x70
9179 #define mmDP_AUX1_AUX_CONTROL                                                                          0x1f6c
9180 #define mmDP_AUX1_AUX_CONTROL_BASE_IDX                                                                 2
9181 #define mmDP_AUX1_AUX_SW_CONTROL                                                                       0x1f6d
9182 #define mmDP_AUX1_AUX_SW_CONTROL_BASE_IDX                                                              2
9183 #define mmDP_AUX1_AUX_ARB_CONTROL                                                                      0x1f6e
9184 #define mmDP_AUX1_AUX_ARB_CONTROL_BASE_IDX                                                             2
9185 #define mmDP_AUX1_AUX_INTERRUPT_CONTROL                                                                0x1f6f
9186 #define mmDP_AUX1_AUX_INTERRUPT_CONTROL_BASE_IDX                                                       2
9187 #define mmDP_AUX1_AUX_SW_STATUS                                                                        0x1f70
9188 #define mmDP_AUX1_AUX_SW_STATUS_BASE_IDX                                                               2
9189 #define mmDP_AUX1_AUX_LS_STATUS                                                                        0x1f71
9190 #define mmDP_AUX1_AUX_LS_STATUS_BASE_IDX                                                               2
9191 #define mmDP_AUX1_AUX_SW_DATA                                                                          0x1f72
9192 #define mmDP_AUX1_AUX_SW_DATA_BASE_IDX                                                                 2
9193 #define mmDP_AUX1_AUX_LS_DATA                                                                          0x1f73
9194 #define mmDP_AUX1_AUX_LS_DATA_BASE_IDX                                                                 2
9195 #define mmDP_AUX1_AUX_DPHY_TX_REF_CONTROL                                                              0x1f74
9196 #define mmDP_AUX1_AUX_DPHY_TX_REF_CONTROL_BASE_IDX                                                     2
9197 #define mmDP_AUX1_AUX_DPHY_TX_CONTROL                                                                  0x1f75
9198 #define mmDP_AUX1_AUX_DPHY_TX_CONTROL_BASE_IDX                                                         2
9199 #define mmDP_AUX1_AUX_DPHY_RX_CONTROL0                                                                 0x1f76
9200 #define mmDP_AUX1_AUX_DPHY_RX_CONTROL0_BASE_IDX                                                        2
9201 #define mmDP_AUX1_AUX_DPHY_RX_CONTROL1                                                                 0x1f77
9202 #define mmDP_AUX1_AUX_DPHY_RX_CONTROL1_BASE_IDX                                                        2
9203 #define mmDP_AUX1_AUX_DPHY_TX_STATUS                                                                   0x1f78
9204 #define mmDP_AUX1_AUX_DPHY_TX_STATUS_BASE_IDX                                                          2
9205 #define mmDP_AUX1_AUX_DPHY_RX_STATUS                                                                   0x1f79
9206 #define mmDP_AUX1_AUX_DPHY_RX_STATUS_BASE_IDX                                                          2
9207 #define mmDP_AUX1_AUX_GTC_SYNC_CONTROL                                                                 0x1f7a
9208 #define mmDP_AUX1_AUX_GTC_SYNC_CONTROL_BASE_IDX                                                        2
9209 #define mmDP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL                                                           0x1f7b
9210 #define mmDP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL_BASE_IDX                                                  2
9211 #define mmDP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS                                                       0x1f7c
9212 #define mmDP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS_BASE_IDX                                              2
9213 #define mmDP_AUX1_AUX_GTC_SYNC_STATUS                                                                  0x1f7d
9214 #define mmDP_AUX1_AUX_GTC_SYNC_STATUS_BASE_IDX                                                         2
9215 #define mmDP_AUX1_AUX_PHY_WAKE_CNTL                                                                    0x1f82
9216 #define mmDP_AUX1_AUX_PHY_WAKE_CNTL_BASE_IDX                                                           2
9217 
9218 
9219 // addressBlock: dce_dc_dio_dp_aux2_dispdec
9220 // base address: 0xe0
9221 #define mmDP_AUX2_AUX_CONTROL                                                                          0x1f88
9222 #define mmDP_AUX2_AUX_CONTROL_BASE_IDX                                                                 2
9223 #define mmDP_AUX2_AUX_SW_CONTROL                                                                       0x1f89
9224 #define mmDP_AUX2_AUX_SW_CONTROL_BASE_IDX                                                              2
9225 #define mmDP_AUX2_AUX_ARB_CONTROL                                                                      0x1f8a
9226 #define mmDP_AUX2_AUX_ARB_CONTROL_BASE_IDX                                                             2
9227 #define mmDP_AUX2_AUX_INTERRUPT_CONTROL                                                                0x1f8b
9228 #define mmDP_AUX2_AUX_INTERRUPT_CONTROL_BASE_IDX                                                       2
9229 #define mmDP_AUX2_AUX_SW_STATUS                                                                        0x1f8c
9230 #define mmDP_AUX2_AUX_SW_STATUS_BASE_IDX                                                               2
9231 #define mmDP_AUX2_AUX_LS_STATUS                                                                        0x1f8d
9232 #define mmDP_AUX2_AUX_LS_STATUS_BASE_IDX                                                               2
9233 #define mmDP_AUX2_AUX_SW_DATA                                                                          0x1f8e
9234 #define mmDP_AUX2_AUX_SW_DATA_BASE_IDX                                                                 2
9235 #define mmDP_AUX2_AUX_LS_DATA                                                                          0x1f8f
9236 #define mmDP_AUX2_AUX_LS_DATA_BASE_IDX                                                                 2
9237 #define mmDP_AUX2_AUX_DPHY_TX_REF_CONTROL                                                              0x1f90
9238 #define mmDP_AUX2_AUX_DPHY_TX_REF_CONTROL_BASE_IDX                                                     2
9239 #define mmDP_AUX2_AUX_DPHY_TX_CONTROL                                                                  0x1f91
9240 #define mmDP_AUX2_AUX_DPHY_TX_CONTROL_BASE_IDX                                                         2
9241 #define mmDP_AUX2_AUX_DPHY_RX_CONTROL0                                                                 0x1f92
9242 #define mmDP_AUX2_AUX_DPHY_RX_CONTROL0_BASE_IDX                                                        2
9243 #define mmDP_AUX2_AUX_DPHY_RX_CONTROL1                                                                 0x1f93
9244 #define mmDP_AUX2_AUX_DPHY_RX_CONTROL1_BASE_IDX                                                        2
9245 #define mmDP_AUX2_AUX_DPHY_TX_STATUS                                                                   0x1f94
9246 #define mmDP_AUX2_AUX_DPHY_TX_STATUS_BASE_IDX                                                          2
9247 #define mmDP_AUX2_AUX_DPHY_RX_STATUS                                                                   0x1f95
9248 #define mmDP_AUX2_AUX_DPHY_RX_STATUS_BASE_IDX                                                          2
9249 #define mmDP_AUX2_AUX_GTC_SYNC_CONTROL                                                                 0x1f96
9250 #define mmDP_AUX2_AUX_GTC_SYNC_CONTROL_BASE_IDX                                                        2
9251 #define mmDP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL                                                           0x1f97
9252 #define mmDP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL_BASE_IDX                                                  2
9253 #define mmDP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS                                                       0x1f98
9254 #define mmDP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS_BASE_IDX                                              2
9255 #define mmDP_AUX2_AUX_GTC_SYNC_STATUS                                                                  0x1f99
9256 #define mmDP_AUX2_AUX_GTC_SYNC_STATUS_BASE_IDX                                                         2
9257 #define mmDP_AUX2_AUX_PHY_WAKE_CNTL                                                                    0x1f9e
9258 #define mmDP_AUX2_AUX_PHY_WAKE_CNTL_BASE_IDX                                                           2
9259 
9260 
9261 // addressBlock: dce_dc_dio_dp_aux3_dispdec
9262 // base address: 0x150
9263 #define mmDP_AUX3_AUX_CONTROL                                                                          0x1fa4
9264 #define mmDP_AUX3_AUX_CONTROL_BASE_IDX                                                                 2
9265 #define mmDP_AUX3_AUX_SW_CONTROL                                                                       0x1fa5
9266 #define mmDP_AUX3_AUX_SW_CONTROL_BASE_IDX                                                              2
9267 #define mmDP_AUX3_AUX_ARB_CONTROL                                                                      0x1fa6
9268 #define mmDP_AUX3_AUX_ARB_CONTROL_BASE_IDX                                                             2
9269 #define mmDP_AUX3_AUX_INTERRUPT_CONTROL                                                                0x1fa7
9270 #define mmDP_AUX3_AUX_INTERRUPT_CONTROL_BASE_IDX                                                       2
9271 #define mmDP_AUX3_AUX_SW_STATUS                                                                        0x1fa8
9272 #define mmDP_AUX3_AUX_SW_STATUS_BASE_IDX                                                               2
9273 #define mmDP_AUX3_AUX_LS_STATUS                                                                        0x1fa9
9274 #define mmDP_AUX3_AUX_LS_STATUS_BASE_IDX                                                               2
9275 #define mmDP_AUX3_AUX_SW_DATA                                                                          0x1faa
9276 #define mmDP_AUX3_AUX_SW_DATA_BASE_IDX                                                                 2
9277 #define mmDP_AUX3_AUX_LS_DATA                                                                          0x1fab
9278 #define mmDP_AUX3_AUX_LS_DATA_BASE_IDX                                                                 2
9279 #define mmDP_AUX3_AUX_DPHY_TX_REF_CONTROL                                                              0x1fac
9280 #define mmDP_AUX3_AUX_DPHY_TX_REF_CONTROL_BASE_IDX                                                     2
9281 #define mmDP_AUX3_AUX_DPHY_TX_CONTROL                                                                  0x1fad
9282 #define mmDP_AUX3_AUX_DPHY_TX_CONTROL_BASE_IDX                                                         2
9283 #define mmDP_AUX3_AUX_DPHY_RX_CONTROL0                                                                 0x1fae
9284 #define mmDP_AUX3_AUX_DPHY_RX_CONTROL0_BASE_IDX                                                        2
9285 #define mmDP_AUX3_AUX_DPHY_RX_CONTROL1                                                                 0x1faf
9286 #define mmDP_AUX3_AUX_DPHY_RX_CONTROL1_BASE_IDX                                                        2
9287 #define mmDP_AUX3_AUX_DPHY_TX_STATUS                                                                   0x1fb0
9288 #define mmDP_AUX3_AUX_DPHY_TX_STATUS_BASE_IDX                                                          2
9289 #define mmDP_AUX3_AUX_DPHY_RX_STATUS                                                                   0x1fb1
9290 #define mmDP_AUX3_AUX_DPHY_RX_STATUS_BASE_IDX                                                          2
9291 #define mmDP_AUX3_AUX_GTC_SYNC_CONTROL                                                                 0x1fb2
9292 #define mmDP_AUX3_AUX_GTC_SYNC_CONTROL_BASE_IDX                                                        2
9293 #define mmDP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL                                                           0x1fb3
9294 #define mmDP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL_BASE_IDX                                                  2
9295 #define mmDP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS                                                       0x1fb4
9296 #define mmDP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS_BASE_IDX                                              2
9297 #define mmDP_AUX3_AUX_GTC_SYNC_STATUS                                                                  0x1fb5
9298 #define mmDP_AUX3_AUX_GTC_SYNC_STATUS_BASE_IDX                                                         2
9299 #define mmDP_AUX3_AUX_PHY_WAKE_CNTL                                                                    0x1fba
9300 #define mmDP_AUX3_AUX_PHY_WAKE_CNTL_BASE_IDX                                                           2
9301 
9302 
9303 // addressBlock: dce_dc_dio_dp_aux4_dispdec
9304 // base address: 0x1c0
9305 #define mmDP_AUX4_AUX_CONTROL                                                                          0x1fc0
9306 #define mmDP_AUX4_AUX_CONTROL_BASE_IDX                                                                 2
9307 #define mmDP_AUX4_AUX_SW_CONTROL                                                                       0x1fc1
9308 #define mmDP_AUX4_AUX_SW_CONTROL_BASE_IDX                                                              2
9309 #define mmDP_AUX4_AUX_ARB_CONTROL                                                                      0x1fc2
9310 #define mmDP_AUX4_AUX_ARB_CONTROL_BASE_IDX                                                             2
9311 #define mmDP_AUX4_AUX_INTERRUPT_CONTROL                                                                0x1fc3
9312 #define mmDP_AUX4_AUX_INTERRUPT_CONTROL_BASE_IDX                                                       2
9313 #define mmDP_AUX4_AUX_SW_STATUS                                                                        0x1fc4
9314 #define mmDP_AUX4_AUX_SW_STATUS_BASE_IDX                                                               2
9315 #define mmDP_AUX4_AUX_LS_STATUS                                                                        0x1fc5
9316 #define mmDP_AUX4_AUX_LS_STATUS_BASE_IDX                                                               2
9317 #define mmDP_AUX4_AUX_SW_DATA                                                                          0x1fc6
9318 #define mmDP_AUX4_AUX_SW_DATA_BASE_IDX                                                                 2
9319 #define mmDP_AUX4_AUX_LS_DATA                                                                          0x1fc7
9320 #define mmDP_AUX4_AUX_LS_DATA_BASE_IDX                                                                 2
9321 #define mmDP_AUX4_AUX_DPHY_TX_REF_CONTROL                                                              0x1fc8
9322 #define mmDP_AUX4_AUX_DPHY_TX_REF_CONTROL_BASE_IDX                                                     2
9323 #define mmDP_AUX4_AUX_DPHY_TX_CONTROL                                                                  0x1fc9
9324 #define mmDP_AUX4_AUX_DPHY_TX_CONTROL_BASE_IDX                                                         2
9325 #define mmDP_AUX4_AUX_DPHY_RX_CONTROL0                                                                 0x1fca
9326 #define mmDP_AUX4_AUX_DPHY_RX_CONTROL0_BASE_IDX                                                        2
9327 #define mmDP_AUX4_AUX_DPHY_RX_CONTROL1                                                                 0x1fcb
9328 #define mmDP_AUX4_AUX_DPHY_RX_CONTROL1_BASE_IDX                                                        2
9329 #define mmDP_AUX4_AUX_DPHY_TX_STATUS                                                                   0x1fcc
9330 #define mmDP_AUX4_AUX_DPHY_TX_STATUS_BASE_IDX                                                          2
9331 #define mmDP_AUX4_AUX_DPHY_RX_STATUS                                                                   0x1fcd
9332 #define mmDP_AUX4_AUX_DPHY_RX_STATUS_BASE_IDX                                                          2
9333 #define mmDP_AUX4_AUX_GTC_SYNC_CONTROL                                                                 0x1fce
9334 #define mmDP_AUX4_AUX_GTC_SYNC_CONTROL_BASE_IDX                                                        2
9335 #define mmDP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL                                                           0x1fcf
9336 #define mmDP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL_BASE_IDX                                                  2
9337 #define mmDP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS                                                       0x1fd0
9338 #define mmDP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS_BASE_IDX                                              2
9339 #define mmDP_AUX4_AUX_GTC_SYNC_STATUS                                                                  0x1fd1
9340 #define mmDP_AUX4_AUX_GTC_SYNC_STATUS_BASE_IDX                                                         2
9341 #define mmDP_AUX4_AUX_PHY_WAKE_CNTL                                                                    0x1fd6
9342 #define mmDP_AUX4_AUX_PHY_WAKE_CNTL_BASE_IDX                                                           2
9343 
9344 
9345 // addressBlock: dce_dc_dio_dig0_vpg_vpg_dispdec
9346 // base address: 0x154a0
9347 #define mmVPG0_VPG_GENERIC_PACKET_ACCESS_CTRL                                                          0x2068
9348 #define mmVPG0_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX                                                 2
9349 #define mmVPG0_VPG_GENERIC_PACKET_DATA                                                                 0x2069
9350 #define mmVPG0_VPG_GENERIC_PACKET_DATA_BASE_IDX                                                        2
9351 #define mmVPG0_VPG_GSP_FRAME_UPDATE_CTRL                                                               0x206a
9352 #define mmVPG0_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX                                                      2
9353 #define mmVPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL                                                           0x206b
9354 #define mmVPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX                                                  2
9355 #define mmVPG0_VPG_GENERIC_STATUS                                                                      0x206c
9356 #define mmVPG0_VPG_GENERIC_STATUS_BASE_IDX                                                             2
9357 #define mmVPG0_VPG_MEM_PWR                                                                             0x206d
9358 #define mmVPG0_VPG_MEM_PWR_BASE_IDX                                                                    2
9359 #define mmVPG0_VPG_ISRC1_2_ACCESS_CTRL                                                                 0x206e
9360 #define mmVPG0_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX                                                        2
9361 #define mmVPG0_VPG_ISRC1_2_DATA                                                                        0x206f
9362 #define mmVPG0_VPG_ISRC1_2_DATA_BASE_IDX                                                               2
9363 #define mmVPG0_VPG_MPEG_INFO0                                                                          0x2070
9364 #define mmVPG0_VPG_MPEG_INFO0_BASE_IDX                                                                 2
9365 #define mmVPG0_VPG_MPEG_INFO1                                                                          0x2071
9366 #define mmVPG0_VPG_MPEG_INFO1_BASE_IDX                                                                 2
9367 
9368 
9369 // addressBlock: dce_dc_dio_dig0_afmt_afmt_dispdec
9370 // base address: 0x154cc
9371 #define mmAFMT0_AFMT_VBI_PACKET_CONTROL                                                                0x2074
9372 #define mmAFMT0_AFMT_VBI_PACKET_CONTROL_BASE_IDX                                                       2
9373 #define mmAFMT0_AFMT_AUDIO_PACKET_CONTROL2                                                             0x2075
9374 #define mmAFMT0_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX                                                    2
9375 #define mmAFMT0_AFMT_AUDIO_INFO0                                                                       0x2076
9376 #define mmAFMT0_AFMT_AUDIO_INFO0_BASE_IDX                                                              2
9377 #define mmAFMT0_AFMT_AUDIO_INFO1                                                                       0x2077
9378 #define mmAFMT0_AFMT_AUDIO_INFO1_BASE_IDX                                                              2
9379 #define mmAFMT0_AFMT_60958_0                                                                           0x2078
9380 #define mmAFMT0_AFMT_60958_0_BASE_IDX                                                                  2
9381 #define mmAFMT0_AFMT_60958_1                                                                           0x2079
9382 #define mmAFMT0_AFMT_60958_1_BASE_IDX                                                                  2
9383 #define mmAFMT0_AFMT_AUDIO_CRC_CONTROL                                                                 0x207a
9384 #define mmAFMT0_AFMT_AUDIO_CRC_CONTROL_BASE_IDX                                                        2
9385 #define mmAFMT0_AFMT_RAMP_CONTROL0                                                                     0x207b
9386 #define mmAFMT0_AFMT_RAMP_CONTROL0_BASE_IDX                                                            2
9387 #define mmAFMT0_AFMT_RAMP_CONTROL1                                                                     0x207c
9388 #define mmAFMT0_AFMT_RAMP_CONTROL1_BASE_IDX                                                            2
9389 #define mmAFMT0_AFMT_RAMP_CONTROL2                                                                     0x207d
9390 #define mmAFMT0_AFMT_RAMP_CONTROL2_BASE_IDX                                                            2
9391 #define mmAFMT0_AFMT_RAMP_CONTROL3                                                                     0x207e
9392 #define mmAFMT0_AFMT_RAMP_CONTROL3_BASE_IDX                                                            2
9393 #define mmAFMT0_AFMT_60958_2                                                                           0x207f
9394 #define mmAFMT0_AFMT_60958_2_BASE_IDX                                                                  2
9395 #define mmAFMT0_AFMT_AUDIO_CRC_RESULT                                                                  0x2080
9396 #define mmAFMT0_AFMT_AUDIO_CRC_RESULT_BASE_IDX                                                         2
9397 #define mmAFMT0_AFMT_STATUS                                                                            0x2081
9398 #define mmAFMT0_AFMT_STATUS_BASE_IDX                                                                   2
9399 #define mmAFMT0_AFMT_AUDIO_PACKET_CONTROL                                                              0x2082
9400 #define mmAFMT0_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX                                                     2
9401 #define mmAFMT0_AFMT_INFOFRAME_CONTROL0                                                                0x2083
9402 #define mmAFMT0_AFMT_INFOFRAME_CONTROL0_BASE_IDX                                                       2
9403 #define mmAFMT0_AFMT_INTERRUPT_STATUS                                                                  0x2084
9404 #define mmAFMT0_AFMT_INTERRUPT_STATUS_BASE_IDX                                                         2
9405 #define mmAFMT0_AFMT_AUDIO_SRC_CONTROL                                                                 0x2085
9406 #define mmAFMT0_AFMT_AUDIO_SRC_CONTROL_BASE_IDX                                                        2
9407 #define mmAFMT0_AFMT_MEM_PWR                                                                           0x2087
9408 #define mmAFMT0_AFMT_MEM_PWR_BASE_IDX                                                                  2
9409 
9410 
9411 // addressBlock: dce_dc_dio_dig0_dme_dme_dispdec
9412 // base address: 0x15524
9413 #define mmDME0_DME_CONTROL                                                                             0x2089
9414 #define mmDME0_DME_CONTROL_BASE_IDX                                                                    2
9415 #define mmDME0_DME_MEMORY_CONTROL                                                                      0x208a
9416 #define mmDME0_DME_MEMORY_CONTROL_BASE_IDX                                                             2
9417 
9418 
9419 // addressBlock: dce_dc_dio_dig0_dispdec
9420 // base address: 0x0
9421 #define mmDIG0_DIG_FE_CNTL                                                                             0x208b
9422 #define mmDIG0_DIG_FE_CNTL_BASE_IDX                                                                    2
9423 #define mmDIG0_DIG_OUTPUT_CRC_CNTL                                                                     0x208c
9424 #define mmDIG0_DIG_OUTPUT_CRC_CNTL_BASE_IDX                                                            2
9425 #define mmDIG0_DIG_OUTPUT_CRC_RESULT                                                                   0x208d
9426 #define mmDIG0_DIG_OUTPUT_CRC_RESULT_BASE_IDX                                                          2
9427 #define mmDIG0_DIG_CLOCK_PATTERN                                                                       0x208e
9428 #define mmDIG0_DIG_CLOCK_PATTERN_BASE_IDX                                                              2
9429 #define mmDIG0_DIG_TEST_PATTERN                                                                        0x208f
9430 #define mmDIG0_DIG_TEST_PATTERN_BASE_IDX                                                               2
9431 #define mmDIG0_DIG_RANDOM_PATTERN_SEED                                                                 0x2090
9432 #define mmDIG0_DIG_RANDOM_PATTERN_SEED_BASE_IDX                                                        2
9433 #define mmDIG0_DIG_FIFO_STATUS                                                                         0x2091
9434 #define mmDIG0_DIG_FIFO_STATUS_BASE_IDX                                                                2
9435 #define mmDIG0_HDMI_METADATA_PACKET_CONTROL                                                            0x2092
9436 #define mmDIG0_HDMI_METADATA_PACKET_CONTROL_BASE_IDX                                                   2
9437 #define mmDIG0_HDMI_CONTROL                                                                            0x2093
9438 #define mmDIG0_HDMI_CONTROL_BASE_IDX                                                                   2
9439 #define mmDIG0_HDMI_STATUS                                                                             0x2094
9440 #define mmDIG0_HDMI_STATUS_BASE_IDX                                                                    2
9441 #define mmDIG0_HDMI_AUDIO_PACKET_CONTROL                                                               0x2095
9442 #define mmDIG0_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX                                                      2
9443 #define mmDIG0_HDMI_ACR_PACKET_CONTROL                                                                 0x2096
9444 #define mmDIG0_HDMI_ACR_PACKET_CONTROL_BASE_IDX                                                        2
9445 #define mmDIG0_HDMI_VBI_PACKET_CONTROL                                                                 0x2097
9446 #define mmDIG0_HDMI_VBI_PACKET_CONTROL_BASE_IDX                                                        2
9447 #define mmDIG0_HDMI_INFOFRAME_CONTROL0                                                                 0x2098
9448 #define mmDIG0_HDMI_INFOFRAME_CONTROL0_BASE_IDX                                                        2
9449 #define mmDIG0_HDMI_INFOFRAME_CONTROL1                                                                 0x2099
9450 #define mmDIG0_HDMI_INFOFRAME_CONTROL1_BASE_IDX                                                        2
9451 #define mmDIG0_HDMI_GENERIC_PACKET_CONTROL0                                                            0x209a
9452 #define mmDIG0_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX                                                   2
9453 #define mmDIG0_HDMI_GENERIC_PACKET_CONTROL6                                                            0x209b
9454 #define mmDIG0_HDMI_GENERIC_PACKET_CONTROL6_BASE_IDX                                                   2
9455 #define mmDIG0_HDMI_GENERIC_PACKET_CONTROL5                                                            0x209c
9456 #define mmDIG0_HDMI_GENERIC_PACKET_CONTROL5_BASE_IDX                                                   2
9457 #define mmDIG0_HDMI_GC                                                                                 0x209d
9458 #define mmDIG0_HDMI_GC_BASE_IDX                                                                        2
9459 #define mmDIG0_HDMI_GENERIC_PACKET_CONTROL1                                                            0x209e
9460 #define mmDIG0_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX                                                   2
9461 #define mmDIG0_HDMI_GENERIC_PACKET_CONTROL2                                                            0x209f
9462 #define mmDIG0_HDMI_GENERIC_PACKET_CONTROL2_BASE_IDX                                                   2
9463 #define mmDIG0_HDMI_GENERIC_PACKET_CONTROL3                                                            0x20a0
9464 #define mmDIG0_HDMI_GENERIC_PACKET_CONTROL3_BASE_IDX                                                   2
9465 #define mmDIG0_HDMI_GENERIC_PACKET_CONTROL4                                                            0x20a1
9466 #define mmDIG0_HDMI_GENERIC_PACKET_CONTROL4_BASE_IDX                                                   2
9467 #define mmDIG0_HDMI_GENERIC_PACKET_CONTROL7                                                            0x20a2
9468 #define mmDIG0_HDMI_GENERIC_PACKET_CONTROL7_BASE_IDX                                                   2
9469 #define mmDIG0_HDMI_GENERIC_PACKET_CONTROL8                                                            0x20a3
9470 #define mmDIG0_HDMI_GENERIC_PACKET_CONTROL8_BASE_IDX                                                   2
9471 #define mmDIG0_HDMI_GENERIC_PACKET_CONTROL9                                                            0x20a4
9472 #define mmDIG0_HDMI_GENERIC_PACKET_CONTROL9_BASE_IDX                                                   2
9473 #define mmDIG0_HDMI_GENERIC_PACKET_CONTROL10                                                           0x20a5
9474 #define mmDIG0_HDMI_GENERIC_PACKET_CONTROL10_BASE_IDX                                                  2
9475 #define mmDIG0_HDMI_DB_CONTROL                                                                         0x20a6
9476 #define mmDIG0_HDMI_DB_CONTROL_BASE_IDX                                                                2
9477 #define mmDIG0_HDMI_ACR_32_0                                                                           0x20a7
9478 #define mmDIG0_HDMI_ACR_32_0_BASE_IDX                                                                  2
9479 #define mmDIG0_HDMI_ACR_32_1                                                                           0x20a8
9480 #define mmDIG0_HDMI_ACR_32_1_BASE_IDX                                                                  2
9481 #define mmDIG0_HDMI_ACR_44_0                                                                           0x20a9
9482 #define mmDIG0_HDMI_ACR_44_0_BASE_IDX                                                                  2
9483 #define mmDIG0_HDMI_ACR_44_1                                                                           0x20aa
9484 #define mmDIG0_HDMI_ACR_44_1_BASE_IDX                                                                  2
9485 #define mmDIG0_HDMI_ACR_48_0                                                                           0x20ab
9486 #define mmDIG0_HDMI_ACR_48_0_BASE_IDX                                                                  2
9487 #define mmDIG0_HDMI_ACR_48_1                                                                           0x20ac
9488 #define mmDIG0_HDMI_ACR_48_1_BASE_IDX                                                                  2
9489 #define mmDIG0_HDMI_ACR_STATUS_0                                                                       0x20ad
9490 #define mmDIG0_HDMI_ACR_STATUS_0_BASE_IDX                                                              2
9491 #define mmDIG0_HDMI_ACR_STATUS_1                                                                       0x20ae
9492 #define mmDIG0_HDMI_ACR_STATUS_1_BASE_IDX                                                              2
9493 #define mmDIG0_AFMT_CNTL                                                                               0x20af
9494 #define mmDIG0_AFMT_CNTL_BASE_IDX                                                                      2
9495 #define mmDIG0_DIG_BE_CNTL                                                                             0x20b0
9496 #define mmDIG0_DIG_BE_CNTL_BASE_IDX                                                                    2
9497 #define mmDIG0_DIG_BE_EN_CNTL                                                                          0x20b1
9498 #define mmDIG0_DIG_BE_EN_CNTL_BASE_IDX                                                                 2
9499 #define mmDIG0_TMDS_CNTL                                                                               0x20d7
9500 #define mmDIG0_TMDS_CNTL_BASE_IDX                                                                      2
9501 #define mmDIG0_TMDS_CONTROL_CHAR                                                                       0x20d8
9502 #define mmDIG0_TMDS_CONTROL_CHAR_BASE_IDX                                                              2
9503 #define mmDIG0_TMDS_CONTROL0_FEEDBACK                                                                  0x20d9
9504 #define mmDIG0_TMDS_CONTROL0_FEEDBACK_BASE_IDX                                                         2
9505 #define mmDIG0_TMDS_STEREOSYNC_CTL_SEL                                                                 0x20da
9506 #define mmDIG0_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX                                                        2
9507 #define mmDIG0_TMDS_SYNC_CHAR_PATTERN_0_1                                                              0x20db
9508 #define mmDIG0_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX                                                     2
9509 #define mmDIG0_TMDS_SYNC_CHAR_PATTERN_2_3                                                              0x20dc
9510 #define mmDIG0_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX                                                     2
9511 #define mmDIG0_TMDS_CTL_BITS                                                                           0x20de
9512 #define mmDIG0_TMDS_CTL_BITS_BASE_IDX                                                                  2
9513 #define mmDIG0_TMDS_DCBALANCER_CONTROL                                                                 0x20df
9514 #define mmDIG0_TMDS_DCBALANCER_CONTROL_BASE_IDX                                                        2
9515 #define mmDIG0_TMDS_SYNC_DCBALANCE_CHAR                                                                0x20e0
9516 #define mmDIG0_TMDS_SYNC_DCBALANCE_CHAR_BASE_IDX                                                       2
9517 #define mmDIG0_TMDS_CTL0_1_GEN_CNTL                                                                    0x20e1
9518 #define mmDIG0_TMDS_CTL0_1_GEN_CNTL_BASE_IDX                                                           2
9519 #define mmDIG0_TMDS_CTL2_3_GEN_CNTL                                                                    0x20e2
9520 #define mmDIG0_TMDS_CTL2_3_GEN_CNTL_BASE_IDX                                                           2
9521 #define mmDIG0_DIG_VERSION                                                                             0x20e4
9522 #define mmDIG0_DIG_VERSION_BASE_IDX                                                                    2
9523 #define mmDIG0_DIG_LANE_ENABLE                                                                         0x20e5
9524 #define mmDIG0_DIG_LANE_ENABLE_BASE_IDX                                                                2
9525 #define mmDIG0_FORCE_DIG_DISABLE                                                                       0x20e6
9526 #define mmDIG0_FORCE_DIG_DISABLE_BASE_IDX                                                              2
9527 
9528 // addressBlock: dce_dc_dio_dp0_dispdec
9529 // base address: 0x0
9530 #define mmDP0_DP_LINK_CNTL                                                                             0x2108
9531 #define mmDP0_DP_LINK_CNTL_BASE_IDX                                                                    2
9532 #define mmDP0_DP_PIXEL_FORMAT                                                                          0x2109
9533 #define mmDP0_DP_PIXEL_FORMAT_BASE_IDX                                                                 2
9534 #define mmDP0_DP_MSA_COLORIMETRY                                                                       0x210a
9535 #define mmDP0_DP_MSA_COLORIMETRY_BASE_IDX                                                              2
9536 #define mmDP0_DP_CONFIG                                                                                0x210b
9537 #define mmDP0_DP_CONFIG_BASE_IDX                                                                       2
9538 #define mmDP0_DP_VID_STREAM_CNTL                                                                       0x210c
9539 #define mmDP0_DP_VID_STREAM_CNTL_BASE_IDX                                                              2
9540 #define mmDP0_DP_STEER_FIFO                                                                            0x210d
9541 #define mmDP0_DP_STEER_FIFO_BASE_IDX                                                                   2
9542 #define mmDP0_DP_MSA_MISC                                                                              0x210e
9543 #define mmDP0_DP_MSA_MISC_BASE_IDX                                                                     2
9544 #define mmDP0_DP_DPHY_INTERNAL_CTRL                                                                    0x210f
9545 #define mmDP0_DP_DPHY_INTERNAL_CTRL_BASE_IDX                                                           2
9546 #define mmDP0_DP_VID_TIMING                                                                            0x2110
9547 #define mmDP0_DP_VID_TIMING_BASE_IDX                                                                   2
9548 #define mmDP0_DP_VID_N                                                                                 0x2111
9549 #define mmDP0_DP_VID_N_BASE_IDX                                                                        2
9550 #define mmDP0_DP_VID_M                                                                                 0x2112
9551 #define mmDP0_DP_VID_M_BASE_IDX                                                                        2
9552 #define mmDP0_DP_LINK_FRAMING_CNTL                                                                     0x2113
9553 #define mmDP0_DP_LINK_FRAMING_CNTL_BASE_IDX                                                            2
9554 #define mmDP0_DP_HBR2_EYE_PATTERN                                                                      0x2114
9555 #define mmDP0_DP_HBR2_EYE_PATTERN_BASE_IDX                                                             2
9556 #define mmDP0_DP_VID_MSA_VBID                                                                          0x2115
9557 #define mmDP0_DP_VID_MSA_VBID_BASE_IDX                                                                 2
9558 #define mmDP0_DP_VID_INTERRUPT_CNTL                                                                    0x2116
9559 #define mmDP0_DP_VID_INTERRUPT_CNTL_BASE_IDX                                                           2
9560 #define mmDP0_DP_DPHY_CNTL                                                                             0x2117
9561 #define mmDP0_DP_DPHY_CNTL_BASE_IDX                                                                    2
9562 #define mmDP0_DP_DPHY_TRAINING_PATTERN_SEL                                                             0x2118
9563 #define mmDP0_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX                                                    2
9564 #define mmDP0_DP_DPHY_SYM0                                                                             0x2119
9565 #define mmDP0_DP_DPHY_SYM0_BASE_IDX                                                                    2
9566 #define mmDP0_DP_DPHY_SYM1                                                                             0x211a
9567 #define mmDP0_DP_DPHY_SYM1_BASE_IDX                                                                    2
9568 #define mmDP0_DP_DPHY_SYM2                                                                             0x211b
9569 #define mmDP0_DP_DPHY_SYM2_BASE_IDX                                                                    2
9570 #define mmDP0_DP_DPHY_8B10B_CNTL                                                                       0x211c
9571 #define mmDP0_DP_DPHY_8B10B_CNTL_BASE_IDX                                                              2
9572 #define mmDP0_DP_DPHY_PRBS_CNTL                                                                        0x211d
9573 #define mmDP0_DP_DPHY_PRBS_CNTL_BASE_IDX                                                               2
9574 #define mmDP0_DP_DPHY_SCRAM_CNTL                                                                       0x211e
9575 #define mmDP0_DP_DPHY_SCRAM_CNTL_BASE_IDX                                                              2
9576 #define mmDP0_DP_DPHY_CRC_EN                                                                           0x211f
9577 #define mmDP0_DP_DPHY_CRC_EN_BASE_IDX                                                                  2
9578 #define mmDP0_DP_DPHY_CRC_CNTL                                                                         0x2120
9579 #define mmDP0_DP_DPHY_CRC_CNTL_BASE_IDX                                                                2
9580 #define mmDP0_DP_DPHY_CRC_RESULT                                                                       0x2121
9581 #define mmDP0_DP_DPHY_CRC_RESULT_BASE_IDX                                                              2
9582 #define mmDP0_DP_DPHY_CRC_MST_CNTL                                                                     0x2122
9583 #define mmDP0_DP_DPHY_CRC_MST_CNTL_BASE_IDX                                                            2
9584 #define mmDP0_DP_DPHY_CRC_MST_STATUS                                                                   0x2123
9585 #define mmDP0_DP_DPHY_CRC_MST_STATUS_BASE_IDX                                                          2
9586 #define mmDP0_DP_DPHY_FAST_TRAINING                                                                    0x2124
9587 #define mmDP0_DP_DPHY_FAST_TRAINING_BASE_IDX                                                           2
9588 #define mmDP0_DP_DPHY_FAST_TRAINING_STATUS                                                             0x2125
9589 #define mmDP0_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX                                                    2
9590 #define mmDP0_DP_SEC_CNTL                                                                              0x212b
9591 #define mmDP0_DP_SEC_CNTL_BASE_IDX                                                                     2
9592 #define mmDP0_DP_SEC_CNTL1                                                                             0x212c
9593 #define mmDP0_DP_SEC_CNTL1_BASE_IDX                                                                    2
9594 #define mmDP0_DP_SEC_FRAMING1                                                                          0x212d
9595 #define mmDP0_DP_SEC_FRAMING1_BASE_IDX                                                                 2
9596 #define mmDP0_DP_SEC_FRAMING2                                                                          0x212e
9597 #define mmDP0_DP_SEC_FRAMING2_BASE_IDX                                                                 2
9598 #define mmDP0_DP_SEC_FRAMING3                                                                          0x212f
9599 #define mmDP0_DP_SEC_FRAMING3_BASE_IDX                                                                 2
9600 #define mmDP0_DP_SEC_FRAMING4                                                                          0x2130
9601 #define mmDP0_DP_SEC_FRAMING4_BASE_IDX                                                                 2
9602 #define mmDP0_DP_SEC_AUD_N                                                                             0x2131
9603 #define mmDP0_DP_SEC_AUD_N_BASE_IDX                                                                    2
9604 #define mmDP0_DP_SEC_AUD_N_READBACK                                                                    0x2132
9605 #define mmDP0_DP_SEC_AUD_N_READBACK_BASE_IDX                                                           2
9606 #define mmDP0_DP_SEC_AUD_M                                                                             0x2133
9607 #define mmDP0_DP_SEC_AUD_M_BASE_IDX                                                                    2
9608 #define mmDP0_DP_SEC_AUD_M_READBACK                                                                    0x2134
9609 #define mmDP0_DP_SEC_AUD_M_READBACK_BASE_IDX                                                           2
9610 #define mmDP0_DP_SEC_TIMESTAMP                                                                         0x2135
9611 #define mmDP0_DP_SEC_TIMESTAMP_BASE_IDX                                                                2
9612 #define mmDP0_DP_SEC_PACKET_CNTL                                                                       0x2136
9613 #define mmDP0_DP_SEC_PACKET_CNTL_BASE_IDX                                                              2
9614 #define mmDP0_DP_MSE_RATE_CNTL                                                                         0x2137
9615 #define mmDP0_DP_MSE_RATE_CNTL_BASE_IDX                                                                2
9616 #define mmDP0_DP_MSE_RATE_UPDATE                                                                       0x2139
9617 #define mmDP0_DP_MSE_RATE_UPDATE_BASE_IDX                                                              2
9618 #define mmDP0_DP_MSE_SAT0                                                                              0x213a
9619 #define mmDP0_DP_MSE_SAT0_BASE_IDX                                                                     2
9620 #define mmDP0_DP_MSE_SAT1                                                                              0x213b
9621 #define mmDP0_DP_MSE_SAT1_BASE_IDX                                                                     2
9622 #define mmDP0_DP_MSE_SAT2                                                                              0x213c
9623 #define mmDP0_DP_MSE_SAT2_BASE_IDX                                                                     2
9624 #define mmDP0_DP_MSE_SAT_UPDATE                                                                        0x213d
9625 #define mmDP0_DP_MSE_SAT_UPDATE_BASE_IDX                                                               2
9626 #define mmDP0_DP_MSE_LINK_TIMING                                                                       0x213e
9627 #define mmDP0_DP_MSE_LINK_TIMING_BASE_IDX                                                              2
9628 #define mmDP0_DP_MSE_MISC_CNTL                                                                         0x213f
9629 #define mmDP0_DP_MSE_MISC_CNTL_BASE_IDX                                                                2
9630 #define mmDP0_DP_DPHY_BS_SR_SWAP_CNTL                                                                  0x2144
9631 #define mmDP0_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX                                                         2
9632 #define mmDP0_DP_DPHY_HBR2_PATTERN_CONTROL                                                             0x2145
9633 #define mmDP0_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX                                                    2
9634 #define mmDP0_DP_MSE_SAT0_STATUS                                                                       0x2147
9635 #define mmDP0_DP_MSE_SAT0_STATUS_BASE_IDX                                                              2
9636 #define mmDP0_DP_MSE_SAT1_STATUS                                                                       0x2148
9637 #define mmDP0_DP_MSE_SAT1_STATUS_BASE_IDX                                                              2
9638 #define mmDP0_DP_MSE_SAT2_STATUS                                                                       0x2149
9639 #define mmDP0_DP_MSE_SAT2_STATUS_BASE_IDX                                                              2
9640 #define mmDP0_DP_MSA_TIMING_PARAM1                                                                     0x214c
9641 #define mmDP0_DP_MSA_TIMING_PARAM1_BASE_IDX                                                            2
9642 #define mmDP0_DP_MSA_TIMING_PARAM2                                                                     0x214d
9643 #define mmDP0_DP_MSA_TIMING_PARAM2_BASE_IDX                                                            2
9644 #define mmDP0_DP_MSA_TIMING_PARAM3                                                                     0x214e
9645 #define mmDP0_DP_MSA_TIMING_PARAM3_BASE_IDX                                                            2
9646 #define mmDP0_DP_MSA_TIMING_PARAM4                                                                     0x214f
9647 #define mmDP0_DP_MSA_TIMING_PARAM4_BASE_IDX                                                            2
9648 #define mmDP0_DP_MSO_CNTL                                                                              0x2150
9649 #define mmDP0_DP_MSO_CNTL_BASE_IDX                                                                     2
9650 #define mmDP0_DP_MSO_CNTL1                                                                             0x2151
9651 #define mmDP0_DP_MSO_CNTL1_BASE_IDX                                                                    2
9652 #define mmDP0_DP_DSC_CNTL                                                                              0x2152
9653 #define mmDP0_DP_DSC_CNTL_BASE_IDX                                                                     2
9654 #define mmDP0_DP_SEC_CNTL2                                                                             0x2153
9655 #define mmDP0_DP_SEC_CNTL2_BASE_IDX                                                                    2
9656 #define mmDP0_DP_SEC_CNTL3                                                                             0x2154
9657 #define mmDP0_DP_SEC_CNTL3_BASE_IDX                                                                    2
9658 #define mmDP0_DP_SEC_CNTL4                                                                             0x2155
9659 #define mmDP0_DP_SEC_CNTL4_BASE_IDX                                                                    2
9660 #define mmDP0_DP_SEC_CNTL5                                                                             0x2156
9661 #define mmDP0_DP_SEC_CNTL5_BASE_IDX                                                                    2
9662 #define mmDP0_DP_SEC_CNTL6                                                                             0x2157
9663 #define mmDP0_DP_SEC_CNTL6_BASE_IDX                                                                    2
9664 #define mmDP0_DP_SEC_CNTL7                                                                             0x2158
9665 #define mmDP0_DP_SEC_CNTL7_BASE_IDX                                                                    2
9666 #define mmDP0_DP_DB_CNTL                                                                               0x2159
9667 #define mmDP0_DP_DB_CNTL_BASE_IDX                                                                      2
9668 #define mmDP0_DP_MSA_VBID_MISC                                                                         0x215a
9669 #define mmDP0_DP_MSA_VBID_MISC_BASE_IDX                                                                2
9670 #define mmDP0_DP_SEC_METADATA_TRANSMISSION                                                             0x215b
9671 #define mmDP0_DP_SEC_METADATA_TRANSMISSION_BASE_IDX                                                    2
9672 #define mmDP0_DP_DSC_BYTES_PER_PIXEL                                                                   0x215c
9673 #define mmDP0_DP_DSC_BYTES_PER_PIXEL_BASE_IDX                                                          2
9674 #define mmDP0_DP_ALPM_CNTL                                                                             0x215d
9675 #define mmDP0_DP_ALPM_CNTL_BASE_IDX                                                                    2
9676 #define mmDP0_DP_GSP8_CNTL                                                                             0x215e
9677 #define mmDP0_DP_GSP8_CNTL_BASE_IDX                                                                    2
9678 #define mmDP0_DP_GSP9_CNTL                                                                             0x215f
9679 #define mmDP0_DP_GSP9_CNTL_BASE_IDX                                                                    2
9680 #define mmDP0_DP_GSP10_CNTL                                                                            0x2160
9681 #define mmDP0_DP_GSP10_CNTL_BASE_IDX                                                                   2
9682 #define mmDP0_DP_GSP11_CNTL                                                                            0x2161
9683 #define mmDP0_DP_GSP11_CNTL_BASE_IDX                                                                   2
9684 #define mmDP0_DP_GSP_EN_DB_STATUS                                                                      0x2162
9685 #define mmDP0_DP_GSP_EN_DB_STATUS_BASE_IDX                                                             2
9686 
9687 
9688 // addressBlock: dce_dc_dio_dig1_vpg_vpg_dispdec
9689 // base address: 0x158a0
9690 #define mmVPG1_VPG_GENERIC_PACKET_ACCESS_CTRL                                                          0x2168
9691 #define mmVPG1_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX                                                 2
9692 #define mmVPG1_VPG_GENERIC_PACKET_DATA                                                                 0x2169
9693 #define mmVPG1_VPG_GENERIC_PACKET_DATA_BASE_IDX                                                        2
9694 #define mmVPG1_VPG_GSP_FRAME_UPDATE_CTRL                                                               0x216a
9695 #define mmVPG1_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX                                                      2
9696 #define mmVPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL                                                           0x216b
9697 #define mmVPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX                                                  2
9698 #define mmVPG1_VPG_GENERIC_STATUS                                                                      0x216c
9699 #define mmVPG1_VPG_GENERIC_STATUS_BASE_IDX                                                             2
9700 #define mmVPG1_VPG_MEM_PWR                                                                             0x216d
9701 #define mmVPG1_VPG_MEM_PWR_BASE_IDX                                                                    2
9702 #define mmVPG1_VPG_ISRC1_2_ACCESS_CTRL                                                                 0x216e
9703 #define mmVPG1_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX                                                        2
9704 #define mmVPG1_VPG_ISRC1_2_DATA                                                                        0x216f
9705 #define mmVPG1_VPG_ISRC1_2_DATA_BASE_IDX                                                               2
9706 #define mmVPG1_VPG_MPEG_INFO0                                                                          0x2170
9707 #define mmVPG1_VPG_MPEG_INFO0_BASE_IDX                                                                 2
9708 #define mmVPG1_VPG_MPEG_INFO1                                                                          0x2171
9709 #define mmVPG1_VPG_MPEG_INFO1_BASE_IDX                                                                 2
9710 
9711 
9712 // addressBlock: dce_dc_dio_dig1_afmt_afmt_dispdec
9713 // base address: 0x158cc
9714 #define mmAFMT1_AFMT_VBI_PACKET_CONTROL                                                                0x2174
9715 #define mmAFMT1_AFMT_VBI_PACKET_CONTROL_BASE_IDX                                                       2
9716 #define mmAFMT1_AFMT_AUDIO_PACKET_CONTROL2                                                             0x2175
9717 #define mmAFMT1_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX                                                    2
9718 #define mmAFMT1_AFMT_AUDIO_INFO0                                                                       0x2176
9719 #define mmAFMT1_AFMT_AUDIO_INFO0_BASE_IDX                                                              2
9720 #define mmAFMT1_AFMT_AUDIO_INFO1                                                                       0x2177
9721 #define mmAFMT1_AFMT_AUDIO_INFO1_BASE_IDX                                                              2
9722 #define mmAFMT1_AFMT_60958_0                                                                           0x2178
9723 #define mmAFMT1_AFMT_60958_0_BASE_IDX                                                                  2
9724 #define mmAFMT1_AFMT_60958_1                                                                           0x2179
9725 #define mmAFMT1_AFMT_60958_1_BASE_IDX                                                                  2
9726 #define mmAFMT1_AFMT_AUDIO_CRC_CONTROL                                                                 0x217a
9727 #define mmAFMT1_AFMT_AUDIO_CRC_CONTROL_BASE_IDX                                                        2
9728 #define mmAFMT1_AFMT_RAMP_CONTROL0                                                                     0x217b
9729 #define mmAFMT1_AFMT_RAMP_CONTROL0_BASE_IDX                                                            2
9730 #define mmAFMT1_AFMT_RAMP_CONTROL1                                                                     0x217c
9731 #define mmAFMT1_AFMT_RAMP_CONTROL1_BASE_IDX                                                            2
9732 #define mmAFMT1_AFMT_RAMP_CONTROL2                                                                     0x217d
9733 #define mmAFMT1_AFMT_RAMP_CONTROL2_BASE_IDX                                                            2
9734 #define mmAFMT1_AFMT_RAMP_CONTROL3                                                                     0x217e
9735 #define mmAFMT1_AFMT_RAMP_CONTROL3_BASE_IDX                                                            2
9736 #define mmAFMT1_AFMT_60958_2                                                                           0x217f
9737 #define mmAFMT1_AFMT_60958_2_BASE_IDX                                                                  2
9738 #define mmAFMT1_AFMT_AUDIO_CRC_RESULT                                                                  0x2180
9739 #define mmAFMT1_AFMT_AUDIO_CRC_RESULT_BASE_IDX                                                         2
9740 #define mmAFMT1_AFMT_STATUS                                                                            0x2181
9741 #define mmAFMT1_AFMT_STATUS_BASE_IDX                                                                   2
9742 #define mmAFMT1_AFMT_AUDIO_PACKET_CONTROL                                                              0x2182
9743 #define mmAFMT1_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX                                                     2
9744 #define mmAFMT1_AFMT_INFOFRAME_CONTROL0                                                                0x2183
9745 #define mmAFMT1_AFMT_INFOFRAME_CONTROL0_BASE_IDX                                                       2
9746 #define mmAFMT1_AFMT_INTERRUPT_STATUS                                                                  0x2184
9747 #define mmAFMT1_AFMT_INTERRUPT_STATUS_BASE_IDX                                                         2
9748 #define mmAFMT1_AFMT_AUDIO_SRC_CONTROL                                                                 0x2185
9749 #define mmAFMT1_AFMT_AUDIO_SRC_CONTROL_BASE_IDX                                                        2
9750 #define mmAFMT1_AFMT_MEM_PWR                                                                           0x2187
9751 #define mmAFMT1_AFMT_MEM_PWR_BASE_IDX                                                                  2
9752 
9753 
9754 // addressBlock: dce_dc_dio_dig1_dme_dme_dispdec
9755 // base address: 0x15924
9756 #define mmDME1_DME_CONTROL                                                                             0x2189
9757 #define mmDME1_DME_CONTROL_BASE_IDX                                                                    2
9758 #define mmDME1_DME_MEMORY_CONTROL                                                                      0x218a
9759 #define mmDME1_DME_MEMORY_CONTROL_BASE_IDX                                                             2
9760 
9761 
9762 // addressBlock: dce_dc_dio_dig1_dispdec
9763 // base address: 0x400
9764 #define mmDIG1_DIG_FE_CNTL                                                                             0x218b
9765 #define mmDIG1_DIG_FE_CNTL_BASE_IDX                                                                    2
9766 #define mmDIG1_DIG_OUTPUT_CRC_CNTL                                                                     0x218c
9767 #define mmDIG1_DIG_OUTPUT_CRC_CNTL_BASE_IDX                                                            2
9768 #define mmDIG1_DIG_OUTPUT_CRC_RESULT                                                                   0x218d
9769 #define mmDIG1_DIG_OUTPUT_CRC_RESULT_BASE_IDX                                                          2
9770 #define mmDIG1_DIG_CLOCK_PATTERN                                                                       0x218e
9771 #define mmDIG1_DIG_CLOCK_PATTERN_BASE_IDX                                                              2
9772 #define mmDIG1_DIG_TEST_PATTERN                                                                        0x218f
9773 #define mmDIG1_DIG_TEST_PATTERN_BASE_IDX                                                               2
9774 #define mmDIG1_DIG_RANDOM_PATTERN_SEED                                                                 0x2190
9775 #define mmDIG1_DIG_RANDOM_PATTERN_SEED_BASE_IDX                                                        2
9776 #define mmDIG1_DIG_FIFO_STATUS                                                                         0x2191
9777 #define mmDIG1_DIG_FIFO_STATUS_BASE_IDX                                                                2
9778 #define mmDIG1_HDMI_METADATA_PACKET_CONTROL                                                            0x2192
9779 #define mmDIG1_HDMI_METADATA_PACKET_CONTROL_BASE_IDX                                                   2
9780 #define mmDIG1_HDMI_CONTROL                                                                            0x2193
9781 #define mmDIG1_HDMI_CONTROL_BASE_IDX                                                                   2
9782 #define mmDIG1_HDMI_STATUS                                                                             0x2194
9783 #define mmDIG1_HDMI_STATUS_BASE_IDX                                                                    2
9784 #define mmDIG1_HDMI_AUDIO_PACKET_CONTROL                                                               0x2195
9785 #define mmDIG1_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX                                                      2
9786 #define mmDIG1_HDMI_ACR_PACKET_CONTROL                                                                 0x2196
9787 #define mmDIG1_HDMI_ACR_PACKET_CONTROL_BASE_IDX                                                        2
9788 #define mmDIG1_HDMI_VBI_PACKET_CONTROL                                                                 0x2197
9789 #define mmDIG1_HDMI_VBI_PACKET_CONTROL_BASE_IDX                                                        2
9790 #define mmDIG1_HDMI_INFOFRAME_CONTROL0                                                                 0x2198
9791 #define mmDIG1_HDMI_INFOFRAME_CONTROL0_BASE_IDX                                                        2
9792 #define mmDIG1_HDMI_INFOFRAME_CONTROL1                                                                 0x2199
9793 #define mmDIG1_HDMI_INFOFRAME_CONTROL1_BASE_IDX                                                        2
9794 #define mmDIG1_HDMI_GENERIC_PACKET_CONTROL0                                                            0x219a
9795 #define mmDIG1_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX                                                   2
9796 #define mmDIG1_HDMI_GENERIC_PACKET_CONTROL6                                                            0x219b
9797 #define mmDIG1_HDMI_GENERIC_PACKET_CONTROL6_BASE_IDX                                                   2
9798 #define mmDIG1_HDMI_GENERIC_PACKET_CONTROL5                                                            0x219c
9799 #define mmDIG1_HDMI_GENERIC_PACKET_CONTROL5_BASE_IDX                                                   2
9800 #define mmDIG1_HDMI_GC                                                                                 0x219d
9801 #define mmDIG1_HDMI_GC_BASE_IDX                                                                        2
9802 #define mmDIG1_HDMI_GENERIC_PACKET_CONTROL1                                                            0x219e
9803 #define mmDIG1_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX                                                   2
9804 #define mmDIG1_HDMI_GENERIC_PACKET_CONTROL2                                                            0x219f
9805 #define mmDIG1_HDMI_GENERIC_PACKET_CONTROL2_BASE_IDX                                                   2
9806 #define mmDIG1_HDMI_GENERIC_PACKET_CONTROL3                                                            0x21a0
9807 #define mmDIG1_HDMI_GENERIC_PACKET_CONTROL3_BASE_IDX                                                   2
9808 #define mmDIG1_HDMI_GENERIC_PACKET_CONTROL4                                                            0x21a1
9809 #define mmDIG1_HDMI_GENERIC_PACKET_CONTROL4_BASE_IDX                                                   2
9810 #define mmDIG1_HDMI_GENERIC_PACKET_CONTROL7                                                            0x21a2
9811 #define mmDIG1_HDMI_GENERIC_PACKET_CONTROL7_BASE_IDX                                                   2
9812 #define mmDIG1_HDMI_GENERIC_PACKET_CONTROL8                                                            0x21a3
9813 #define mmDIG1_HDMI_GENERIC_PACKET_CONTROL8_BASE_IDX                                                   2
9814 #define mmDIG1_HDMI_GENERIC_PACKET_CONTROL9                                                            0x21a4
9815 #define mmDIG1_HDMI_GENERIC_PACKET_CONTROL9_BASE_IDX                                                   2
9816 #define mmDIG1_HDMI_GENERIC_PACKET_CONTROL10                                                           0x21a5
9817 #define mmDIG1_HDMI_GENERIC_PACKET_CONTROL10_BASE_IDX                                                  2
9818 #define mmDIG1_HDMI_DB_CONTROL                                                                         0x21a6
9819 #define mmDIG1_HDMI_DB_CONTROL_BASE_IDX                                                                2
9820 #define mmDIG1_HDMI_ACR_32_0                                                                           0x21a7
9821 #define mmDIG1_HDMI_ACR_32_0_BASE_IDX                                                                  2
9822 #define mmDIG1_HDMI_ACR_32_1                                                                           0x21a8
9823 #define mmDIG1_HDMI_ACR_32_1_BASE_IDX                                                                  2
9824 #define mmDIG1_HDMI_ACR_44_0                                                                           0x21a9
9825 #define mmDIG1_HDMI_ACR_44_0_BASE_IDX                                                                  2
9826 #define mmDIG1_HDMI_ACR_44_1                                                                           0x21aa
9827 #define mmDIG1_HDMI_ACR_44_1_BASE_IDX                                                                  2
9828 #define mmDIG1_HDMI_ACR_48_0                                                                           0x21ab
9829 #define mmDIG1_HDMI_ACR_48_0_BASE_IDX                                                                  2
9830 #define mmDIG1_HDMI_ACR_48_1                                                                           0x21ac
9831 #define mmDIG1_HDMI_ACR_48_1_BASE_IDX                                                                  2
9832 #define mmDIG1_HDMI_ACR_STATUS_0                                                                       0x21ad
9833 #define mmDIG1_HDMI_ACR_STATUS_0_BASE_IDX                                                              2
9834 #define mmDIG1_HDMI_ACR_STATUS_1                                                                       0x21ae
9835 #define mmDIG1_HDMI_ACR_STATUS_1_BASE_IDX                                                              2
9836 #define mmDIG1_AFMT_CNTL                                                                               0x21af
9837 #define mmDIG1_AFMT_CNTL_BASE_IDX                                                                      2
9838 #define mmDIG1_DIG_BE_CNTL                                                                             0x21b0
9839 #define mmDIG1_DIG_BE_CNTL_BASE_IDX                                                                    2
9840 #define mmDIG1_DIG_BE_EN_CNTL                                                                          0x21b1
9841 #define mmDIG1_DIG_BE_EN_CNTL_BASE_IDX                                                                 2
9842 #define mmDIG1_TMDS_CNTL                                                                               0x21d7
9843 #define mmDIG1_TMDS_CNTL_BASE_IDX                                                                      2
9844 #define mmDIG1_TMDS_CONTROL_CHAR                                                                       0x21d8
9845 #define mmDIG1_TMDS_CONTROL_CHAR_BASE_IDX                                                              2
9846 #define mmDIG1_TMDS_CONTROL0_FEEDBACK                                                                  0x21d9
9847 #define mmDIG1_TMDS_CONTROL0_FEEDBACK_BASE_IDX                                                         2
9848 #define mmDIG1_TMDS_STEREOSYNC_CTL_SEL                                                                 0x21da
9849 #define mmDIG1_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX                                                        2
9850 #define mmDIG1_TMDS_SYNC_CHAR_PATTERN_0_1                                                              0x21db
9851 #define mmDIG1_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX                                                     2
9852 #define mmDIG1_TMDS_SYNC_CHAR_PATTERN_2_3                                                              0x21dc
9853 #define mmDIG1_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX                                                     2
9854 #define mmDIG1_TMDS_CTL_BITS                                                                           0x21de
9855 #define mmDIG1_TMDS_CTL_BITS_BASE_IDX                                                                  2
9856 #define mmDIG1_TMDS_DCBALANCER_CONTROL                                                                 0x21df
9857 #define mmDIG1_TMDS_DCBALANCER_CONTROL_BASE_IDX                                                        2
9858 #define mmDIG1_TMDS_SYNC_DCBALANCE_CHAR                                                                0x21e0
9859 #define mmDIG1_TMDS_SYNC_DCBALANCE_CHAR_BASE_IDX                                                       2
9860 #define mmDIG1_TMDS_CTL0_1_GEN_CNTL                                                                    0x21e1
9861 #define mmDIG1_TMDS_CTL0_1_GEN_CNTL_BASE_IDX                                                           2
9862 #define mmDIG1_TMDS_CTL2_3_GEN_CNTL                                                                    0x21e2
9863 #define mmDIG1_TMDS_CTL2_3_GEN_CNTL_BASE_IDX                                                           2
9864 #define mmDIG1_DIG_VERSION                                                                             0x21e4
9865 #define mmDIG1_DIG_VERSION_BASE_IDX                                                                    2
9866 #define mmDIG1_DIG_LANE_ENABLE                                                                         0x21e5
9867 #define mmDIG1_DIG_LANE_ENABLE_BASE_IDX                                                                2
9868 #define mmDIG1_FORCE_DIG_DISABLE                                                                       0x21e6
9869 #define mmDIG1_FORCE_DIG_DISABLE_BASE_IDX                                                              2
9870 
9871 // addressBlock: dce_dc_dio_dp1_dispdec
9872 // base address: 0x400
9873 #define mmDP1_DP_LINK_CNTL                                                                             0x2208
9874 #define mmDP1_DP_LINK_CNTL_BASE_IDX                                                                    2
9875 #define mmDP1_DP_PIXEL_FORMAT                                                                          0x2209
9876 #define mmDP1_DP_PIXEL_FORMAT_BASE_IDX                                                                 2
9877 #define mmDP1_DP_MSA_COLORIMETRY                                                                       0x220a
9878 #define mmDP1_DP_MSA_COLORIMETRY_BASE_IDX                                                              2
9879 #define mmDP1_DP_CONFIG                                                                                0x220b
9880 #define mmDP1_DP_CONFIG_BASE_IDX                                                                       2
9881 #define mmDP1_DP_VID_STREAM_CNTL                                                                       0x220c
9882 #define mmDP1_DP_VID_STREAM_CNTL_BASE_IDX                                                              2
9883 #define mmDP1_DP_STEER_FIFO                                                                            0x220d
9884 #define mmDP1_DP_STEER_FIFO_BASE_IDX                                                                   2
9885 #define mmDP1_DP_MSA_MISC                                                                              0x220e
9886 #define mmDP1_DP_MSA_MISC_BASE_IDX                                                                     2
9887 #define mmDP1_DP_DPHY_INTERNAL_CTRL                                                                    0x220f
9888 #define mmDP1_DP_DPHY_INTERNAL_CTRL_BASE_IDX                                                           2
9889 #define mmDP1_DP_VID_TIMING                                                                            0x2210
9890 #define mmDP1_DP_VID_TIMING_BASE_IDX                                                                   2
9891 #define mmDP1_DP_VID_N                                                                                 0x2211
9892 #define mmDP1_DP_VID_N_BASE_IDX                                                                        2
9893 #define mmDP1_DP_VID_M                                                                                 0x2212
9894 #define mmDP1_DP_VID_M_BASE_IDX                                                                        2
9895 #define mmDP1_DP_LINK_FRAMING_CNTL                                                                     0x2213
9896 #define mmDP1_DP_LINK_FRAMING_CNTL_BASE_IDX                                                            2
9897 #define mmDP1_DP_HBR2_EYE_PATTERN                                                                      0x2214
9898 #define mmDP1_DP_HBR2_EYE_PATTERN_BASE_IDX                                                             2
9899 #define mmDP1_DP_VID_MSA_VBID                                                                          0x2215
9900 #define mmDP1_DP_VID_MSA_VBID_BASE_IDX                                                                 2
9901 #define mmDP1_DP_VID_INTERRUPT_CNTL                                                                    0x2216
9902 #define mmDP1_DP_VID_INTERRUPT_CNTL_BASE_IDX                                                           2
9903 #define mmDP1_DP_DPHY_CNTL                                                                             0x2217
9904 #define mmDP1_DP_DPHY_CNTL_BASE_IDX                                                                    2
9905 #define mmDP1_DP_DPHY_TRAINING_PATTERN_SEL                                                             0x2218
9906 #define mmDP1_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX                                                    2
9907 #define mmDP1_DP_DPHY_SYM0                                                                             0x2219
9908 #define mmDP1_DP_DPHY_SYM0_BASE_IDX                                                                    2
9909 #define mmDP1_DP_DPHY_SYM1                                                                             0x221a
9910 #define mmDP1_DP_DPHY_SYM1_BASE_IDX                                                                    2
9911 #define mmDP1_DP_DPHY_SYM2                                                                             0x221b
9912 #define mmDP1_DP_DPHY_SYM2_BASE_IDX                                                                    2
9913 #define mmDP1_DP_DPHY_8B10B_CNTL                                                                       0x221c
9914 #define mmDP1_DP_DPHY_8B10B_CNTL_BASE_IDX                                                              2
9915 #define mmDP1_DP_DPHY_PRBS_CNTL                                                                        0x221d
9916 #define mmDP1_DP_DPHY_PRBS_CNTL_BASE_IDX                                                               2
9917 #define mmDP1_DP_DPHY_SCRAM_CNTL                                                                       0x221e
9918 #define mmDP1_DP_DPHY_SCRAM_CNTL_BASE_IDX                                                              2
9919 #define mmDP1_DP_DPHY_CRC_EN                                                                           0x221f
9920 #define mmDP1_DP_DPHY_CRC_EN_BASE_IDX                                                                  2
9921 #define mmDP1_DP_DPHY_CRC_CNTL                                                                         0x2220
9922 #define mmDP1_DP_DPHY_CRC_CNTL_BASE_IDX                                                                2
9923 #define mmDP1_DP_DPHY_CRC_RESULT                                                                       0x2221
9924 #define mmDP1_DP_DPHY_CRC_RESULT_BASE_IDX                                                              2
9925 #define mmDP1_DP_DPHY_CRC_MST_CNTL                                                                     0x2222
9926 #define mmDP1_DP_DPHY_CRC_MST_CNTL_BASE_IDX                                                            2
9927 #define mmDP1_DP_DPHY_CRC_MST_STATUS                                                                   0x2223
9928 #define mmDP1_DP_DPHY_CRC_MST_STATUS_BASE_IDX                                                          2
9929 #define mmDP1_DP_DPHY_FAST_TRAINING                                                                    0x2224
9930 #define mmDP1_DP_DPHY_FAST_TRAINING_BASE_IDX                                                           2
9931 #define mmDP1_DP_DPHY_FAST_TRAINING_STATUS                                                             0x2225
9932 #define mmDP1_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX                                                    2
9933 #define mmDP1_DP_SEC_CNTL                                                                              0x222b
9934 #define mmDP1_DP_SEC_CNTL_BASE_IDX                                                                     2
9935 #define mmDP1_DP_SEC_CNTL1                                                                             0x222c
9936 #define mmDP1_DP_SEC_CNTL1_BASE_IDX                                                                    2
9937 #define mmDP1_DP_SEC_FRAMING1                                                                          0x222d
9938 #define mmDP1_DP_SEC_FRAMING1_BASE_IDX                                                                 2
9939 #define mmDP1_DP_SEC_FRAMING2                                                                          0x222e
9940 #define mmDP1_DP_SEC_FRAMING2_BASE_IDX                                                                 2
9941 #define mmDP1_DP_SEC_FRAMING3                                                                          0x222f
9942 #define mmDP1_DP_SEC_FRAMING3_BASE_IDX                                                                 2
9943 #define mmDP1_DP_SEC_FRAMING4                                                                          0x2230
9944 #define mmDP1_DP_SEC_FRAMING4_BASE_IDX                                                                 2
9945 #define mmDP1_DP_SEC_AUD_N                                                                             0x2231
9946 #define mmDP1_DP_SEC_AUD_N_BASE_IDX                                                                    2
9947 #define mmDP1_DP_SEC_AUD_N_READBACK                                                                    0x2232
9948 #define mmDP1_DP_SEC_AUD_N_READBACK_BASE_IDX                                                           2
9949 #define mmDP1_DP_SEC_AUD_M                                                                             0x2233
9950 #define mmDP1_DP_SEC_AUD_M_BASE_IDX                                                                    2
9951 #define mmDP1_DP_SEC_AUD_M_READBACK                                                                    0x2234
9952 #define mmDP1_DP_SEC_AUD_M_READBACK_BASE_IDX                                                           2
9953 #define mmDP1_DP_SEC_TIMESTAMP                                                                         0x2235
9954 #define mmDP1_DP_SEC_TIMESTAMP_BASE_IDX                                                                2
9955 #define mmDP1_DP_SEC_PACKET_CNTL                                                                       0x2236
9956 #define mmDP1_DP_SEC_PACKET_CNTL_BASE_IDX                                                              2
9957 #define mmDP1_DP_MSE_RATE_CNTL                                                                         0x2237
9958 #define mmDP1_DP_MSE_RATE_CNTL_BASE_IDX                                                                2
9959 #define mmDP1_DP_MSE_RATE_UPDATE                                                                       0x2239
9960 #define mmDP1_DP_MSE_RATE_UPDATE_BASE_IDX                                                              2
9961 #define mmDP1_DP_MSE_SAT0                                                                              0x223a
9962 #define mmDP1_DP_MSE_SAT0_BASE_IDX                                                                     2
9963 #define mmDP1_DP_MSE_SAT1                                                                              0x223b
9964 #define mmDP1_DP_MSE_SAT1_BASE_IDX                                                                     2
9965 #define mmDP1_DP_MSE_SAT2                                                                              0x223c
9966 #define mmDP1_DP_MSE_SAT2_BASE_IDX                                                                     2
9967 #define mmDP1_DP_MSE_SAT_UPDATE                                                                        0x223d
9968 #define mmDP1_DP_MSE_SAT_UPDATE_BASE_IDX                                                               2
9969 #define mmDP1_DP_MSE_LINK_TIMING                                                                       0x223e
9970 #define mmDP1_DP_MSE_LINK_TIMING_BASE_IDX                                                              2
9971 #define mmDP1_DP_MSE_MISC_CNTL                                                                         0x223f
9972 #define mmDP1_DP_MSE_MISC_CNTL_BASE_IDX                                                                2
9973 #define mmDP1_DP_DPHY_BS_SR_SWAP_CNTL                                                                  0x2244
9974 #define mmDP1_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX                                                         2
9975 #define mmDP1_DP_DPHY_HBR2_PATTERN_CONTROL                                                             0x2245
9976 #define mmDP1_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX                                                    2
9977 #define mmDP1_DP_MSE_SAT0_STATUS                                                                       0x2247
9978 #define mmDP1_DP_MSE_SAT0_STATUS_BASE_IDX                                                              2
9979 #define mmDP1_DP_MSE_SAT1_STATUS                                                                       0x2248
9980 #define mmDP1_DP_MSE_SAT1_STATUS_BASE_IDX                                                              2
9981 #define mmDP1_DP_MSE_SAT2_STATUS                                                                       0x2249
9982 #define mmDP1_DP_MSE_SAT2_STATUS_BASE_IDX                                                              2
9983 #define mmDP1_DP_MSA_TIMING_PARAM1                                                                     0x224c
9984 #define mmDP1_DP_MSA_TIMING_PARAM1_BASE_IDX                                                            2
9985 #define mmDP1_DP_MSA_TIMING_PARAM2                                                                     0x224d
9986 #define mmDP1_DP_MSA_TIMING_PARAM2_BASE_IDX                                                            2
9987 #define mmDP1_DP_MSA_TIMING_PARAM3                                                                     0x224e
9988 #define mmDP1_DP_MSA_TIMING_PARAM3_BASE_IDX                                                            2
9989 #define mmDP1_DP_MSA_TIMING_PARAM4                                                                     0x224f
9990 #define mmDP1_DP_MSA_TIMING_PARAM4_BASE_IDX                                                            2
9991 #define mmDP1_DP_MSO_CNTL                                                                              0x2250
9992 #define mmDP1_DP_MSO_CNTL_BASE_IDX                                                                     2
9993 #define mmDP1_DP_MSO_CNTL1                                                                             0x2251
9994 #define mmDP1_DP_MSO_CNTL1_BASE_IDX                                                                    2
9995 #define mmDP1_DP_DSC_CNTL                                                                              0x2252
9996 #define mmDP1_DP_DSC_CNTL_BASE_IDX                                                                     2
9997 #define mmDP1_DP_SEC_CNTL2                                                                             0x2253
9998 #define mmDP1_DP_SEC_CNTL2_BASE_IDX                                                                    2
9999 #define mmDP1_DP_SEC_CNTL3                                                                             0x2254
10000 #define mmDP1_DP_SEC_CNTL3_BASE_IDX                                                                    2
10001 #define mmDP1_DP_SEC_CNTL4                                                                             0x2255
10002 #define mmDP1_DP_SEC_CNTL4_BASE_IDX                                                                    2
10003 #define mmDP1_DP_SEC_CNTL5                                                                             0x2256
10004 #define mmDP1_DP_SEC_CNTL5_BASE_IDX                                                                    2
10005 #define mmDP1_DP_SEC_CNTL6                                                                             0x2257
10006 #define mmDP1_DP_SEC_CNTL6_BASE_IDX                                                                    2
10007 #define mmDP1_DP_SEC_CNTL7                                                                             0x2258
10008 #define mmDP1_DP_SEC_CNTL7_BASE_IDX                                                                    2
10009 #define mmDP1_DP_DB_CNTL                                                                               0x2259
10010 #define mmDP1_DP_DB_CNTL_BASE_IDX                                                                      2
10011 #define mmDP1_DP_MSA_VBID_MISC                                                                         0x225a
10012 #define mmDP1_DP_MSA_VBID_MISC_BASE_IDX                                                                2
10013 #define mmDP1_DP_SEC_METADATA_TRANSMISSION                                                             0x225b
10014 #define mmDP1_DP_SEC_METADATA_TRANSMISSION_BASE_IDX                                                    2
10015 #define mmDP1_DP_DSC_BYTES_PER_PIXEL                                                                   0x225c
10016 #define mmDP1_DP_DSC_BYTES_PER_PIXEL_BASE_IDX                                                          2
10017 #define mmDP1_DP_ALPM_CNTL                                                                             0x225d
10018 #define mmDP1_DP_ALPM_CNTL_BASE_IDX                                                                    2
10019 #define mmDP1_DP_GSP8_CNTL                                                                             0x225e
10020 #define mmDP1_DP_GSP8_CNTL_BASE_IDX                                                                    2
10021 #define mmDP1_DP_GSP9_CNTL                                                                             0x225f
10022 #define mmDP1_DP_GSP9_CNTL_BASE_IDX                                                                    2
10023 #define mmDP1_DP_GSP10_CNTL                                                                            0x2260
10024 #define mmDP1_DP_GSP10_CNTL_BASE_IDX                                                                   2
10025 #define mmDP1_DP_GSP11_CNTL                                                                            0x2261
10026 #define mmDP1_DP_GSP11_CNTL_BASE_IDX                                                                   2
10027 #define mmDP1_DP_GSP_EN_DB_STATUS                                                                      0x2262
10028 #define mmDP1_DP_GSP_EN_DB_STATUS_BASE_IDX                                                             2
10029 
10030 
10031 // addressBlock: dce_dc_dio_dig2_vpg_vpg_dispdec
10032 // base address: 0x15ca0
10033 #define mmVPG2_VPG_GENERIC_PACKET_ACCESS_CTRL                                                          0x2268
10034 #define mmVPG2_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX                                                 2
10035 #define mmVPG2_VPG_GENERIC_PACKET_DATA                                                                 0x2269
10036 #define mmVPG2_VPG_GENERIC_PACKET_DATA_BASE_IDX                                                        2
10037 #define mmVPG2_VPG_GSP_FRAME_UPDATE_CTRL                                                               0x226a
10038 #define mmVPG2_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX                                                      2
10039 #define mmVPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL                                                           0x226b
10040 #define mmVPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX                                                  2
10041 #define mmVPG2_VPG_GENERIC_STATUS                                                                      0x226c
10042 #define mmVPG2_VPG_GENERIC_STATUS_BASE_IDX                                                             2
10043 #define mmVPG2_VPG_MEM_PWR                                                                             0x226d
10044 #define mmVPG2_VPG_MEM_PWR_BASE_IDX                                                                    2
10045 #define mmVPG2_VPG_ISRC1_2_ACCESS_CTRL                                                                 0x226e
10046 #define mmVPG2_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX                                                        2
10047 #define mmVPG2_VPG_ISRC1_2_DATA                                                                        0x226f
10048 #define mmVPG2_VPG_ISRC1_2_DATA_BASE_IDX                                                               2
10049 #define mmVPG2_VPG_MPEG_INFO0                                                                          0x2270
10050 #define mmVPG2_VPG_MPEG_INFO0_BASE_IDX                                                                 2
10051 #define mmVPG2_VPG_MPEG_INFO1                                                                          0x2271
10052 #define mmVPG2_VPG_MPEG_INFO1_BASE_IDX                                                                 2
10053 
10054 
10055 // addressBlock: dce_dc_dio_dig2_afmt_afmt_dispdec
10056 // base address: 0x15ccc
10057 #define mmAFMT2_AFMT_VBI_PACKET_CONTROL                                                                0x2274
10058 #define mmAFMT2_AFMT_VBI_PACKET_CONTROL_BASE_IDX                                                       2
10059 #define mmAFMT2_AFMT_AUDIO_PACKET_CONTROL2                                                             0x2275
10060 #define mmAFMT2_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX                                                    2
10061 #define mmAFMT2_AFMT_AUDIO_INFO0                                                                       0x2276
10062 #define mmAFMT2_AFMT_AUDIO_INFO0_BASE_IDX                                                              2
10063 #define mmAFMT2_AFMT_AUDIO_INFO1                                                                       0x2277
10064 #define mmAFMT2_AFMT_AUDIO_INFO1_BASE_IDX                                                              2
10065 #define mmAFMT2_AFMT_60958_0                                                                           0x2278
10066 #define mmAFMT2_AFMT_60958_0_BASE_IDX                                                                  2
10067 #define mmAFMT2_AFMT_60958_1                                                                           0x2279
10068 #define mmAFMT2_AFMT_60958_1_BASE_IDX                                                                  2
10069 #define mmAFMT2_AFMT_AUDIO_CRC_CONTROL                                                                 0x227a
10070 #define mmAFMT2_AFMT_AUDIO_CRC_CONTROL_BASE_IDX                                                        2
10071 #define mmAFMT2_AFMT_RAMP_CONTROL0                                                                     0x227b
10072 #define mmAFMT2_AFMT_RAMP_CONTROL0_BASE_IDX                                                            2
10073 #define mmAFMT2_AFMT_RAMP_CONTROL1                                                                     0x227c
10074 #define mmAFMT2_AFMT_RAMP_CONTROL1_BASE_IDX                                                            2
10075 #define mmAFMT2_AFMT_RAMP_CONTROL2                                                                     0x227d
10076 #define mmAFMT2_AFMT_RAMP_CONTROL2_BASE_IDX                                                            2
10077 #define mmAFMT2_AFMT_RAMP_CONTROL3                                                                     0x227e
10078 #define mmAFMT2_AFMT_RAMP_CONTROL3_BASE_IDX                                                            2
10079 #define mmAFMT2_AFMT_60958_2                                                                           0x227f
10080 #define mmAFMT2_AFMT_60958_2_BASE_IDX                                                                  2
10081 #define mmAFMT2_AFMT_AUDIO_CRC_RESULT                                                                  0x2280
10082 #define mmAFMT2_AFMT_AUDIO_CRC_RESULT_BASE_IDX                                                         2
10083 #define mmAFMT2_AFMT_STATUS                                                                            0x2281
10084 #define mmAFMT2_AFMT_STATUS_BASE_IDX                                                                   2
10085 #define mmAFMT2_AFMT_AUDIO_PACKET_CONTROL                                                              0x2282
10086 #define mmAFMT2_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX                                                     2
10087 #define mmAFMT2_AFMT_INFOFRAME_CONTROL0                                                                0x2283
10088 #define mmAFMT2_AFMT_INFOFRAME_CONTROL0_BASE_IDX                                                       2
10089 #define mmAFMT2_AFMT_INTERRUPT_STATUS                                                                  0x2284
10090 #define mmAFMT2_AFMT_INTERRUPT_STATUS_BASE_IDX                                                         2
10091 #define mmAFMT2_AFMT_AUDIO_SRC_CONTROL                                                                 0x2285
10092 #define mmAFMT2_AFMT_AUDIO_SRC_CONTROL_BASE_IDX                                                        2
10093 #define mmAFMT2_AFMT_MEM_PWR                                                                           0x2287
10094 #define mmAFMT2_AFMT_MEM_PWR_BASE_IDX                                                                  2
10095 
10096 
10097 // addressBlock: dce_dc_dio_dig2_dme_dme_dispdec
10098 // base address: 0x15d24
10099 #define mmDME2_DME_CONTROL                                                                             0x2289
10100 #define mmDME2_DME_CONTROL_BASE_IDX                                                                    2
10101 #define mmDME2_DME_MEMORY_CONTROL                                                                      0x228a
10102 #define mmDME2_DME_MEMORY_CONTROL_BASE_IDX                                                             2
10103 
10104 
10105 // addressBlock: dce_dc_dio_dig2_dispdec
10106 // base address: 0x800
10107 #define mmDIG2_DIG_FE_CNTL                                                                             0x228b
10108 #define mmDIG2_DIG_FE_CNTL_BASE_IDX                                                                    2
10109 #define mmDIG2_DIG_OUTPUT_CRC_CNTL                                                                     0x228c
10110 #define mmDIG2_DIG_OUTPUT_CRC_CNTL_BASE_IDX                                                            2
10111 #define mmDIG2_DIG_OUTPUT_CRC_RESULT                                                                   0x228d
10112 #define mmDIG2_DIG_OUTPUT_CRC_RESULT_BASE_IDX                                                          2
10113 #define mmDIG2_DIG_CLOCK_PATTERN                                                                       0x228e
10114 #define mmDIG2_DIG_CLOCK_PATTERN_BASE_IDX                                                              2
10115 #define mmDIG2_DIG_TEST_PATTERN                                                                        0x228f
10116 #define mmDIG2_DIG_TEST_PATTERN_BASE_IDX                                                               2
10117 #define mmDIG2_DIG_RANDOM_PATTERN_SEED                                                                 0x2290
10118 #define mmDIG2_DIG_RANDOM_PATTERN_SEED_BASE_IDX                                                        2
10119 #define mmDIG2_DIG_FIFO_STATUS                                                                         0x2291
10120 #define mmDIG2_DIG_FIFO_STATUS_BASE_IDX                                                                2
10121 #define mmDIG2_HDMI_METADATA_PACKET_CONTROL                                                            0x2292
10122 #define mmDIG2_HDMI_METADATA_PACKET_CONTROL_BASE_IDX                                                   2
10123 #define mmDIG2_HDMI_CONTROL                                                                            0x2293
10124 #define mmDIG2_HDMI_CONTROL_BASE_IDX                                                                   2
10125 #define mmDIG2_HDMI_STATUS                                                                             0x2294
10126 #define mmDIG2_HDMI_STATUS_BASE_IDX                                                                    2
10127 #define mmDIG2_HDMI_AUDIO_PACKET_CONTROL                                                               0x2295
10128 #define mmDIG2_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX                                                      2
10129 #define mmDIG2_HDMI_ACR_PACKET_CONTROL                                                                 0x2296
10130 #define mmDIG2_HDMI_ACR_PACKET_CONTROL_BASE_IDX                                                        2
10131 #define mmDIG2_HDMI_VBI_PACKET_CONTROL                                                                 0x2297
10132 #define mmDIG2_HDMI_VBI_PACKET_CONTROL_BASE_IDX                                                        2
10133 #define mmDIG2_HDMI_INFOFRAME_CONTROL0                                                                 0x2298
10134 #define mmDIG2_HDMI_INFOFRAME_CONTROL0_BASE_IDX                                                        2
10135 #define mmDIG2_HDMI_INFOFRAME_CONTROL1                                                                 0x2299
10136 #define mmDIG2_HDMI_INFOFRAME_CONTROL1_BASE_IDX                                                        2
10137 #define mmDIG2_HDMI_GENERIC_PACKET_CONTROL0                                                            0x229a
10138 #define mmDIG2_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX                                                   2
10139 #define mmDIG2_HDMI_GENERIC_PACKET_CONTROL6                                                            0x229b
10140 #define mmDIG2_HDMI_GENERIC_PACKET_CONTROL6_BASE_IDX                                                   2
10141 #define mmDIG2_HDMI_GENERIC_PACKET_CONTROL5                                                            0x229c
10142 #define mmDIG2_HDMI_GENERIC_PACKET_CONTROL5_BASE_IDX                                                   2
10143 #define mmDIG2_HDMI_GC                                                                                 0x229d
10144 #define mmDIG2_HDMI_GC_BASE_IDX                                                                        2
10145 #define mmDIG2_HDMI_GENERIC_PACKET_CONTROL1                                                            0x229e
10146 #define mmDIG2_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX                                                   2
10147 #define mmDIG2_HDMI_GENERIC_PACKET_CONTROL2                                                            0x229f
10148 #define mmDIG2_HDMI_GENERIC_PACKET_CONTROL2_BASE_IDX                                                   2
10149 #define mmDIG2_HDMI_GENERIC_PACKET_CONTROL3                                                            0x22a0
10150 #define mmDIG2_HDMI_GENERIC_PACKET_CONTROL3_BASE_IDX                                                   2
10151 #define mmDIG2_HDMI_GENERIC_PACKET_CONTROL4                                                            0x22a1
10152 #define mmDIG2_HDMI_GENERIC_PACKET_CONTROL4_BASE_IDX                                                   2
10153 #define mmDIG2_HDMI_GENERIC_PACKET_CONTROL7                                                            0x22a2
10154 #define mmDIG2_HDMI_GENERIC_PACKET_CONTROL7_BASE_IDX                                                   2
10155 #define mmDIG2_HDMI_GENERIC_PACKET_CONTROL8                                                            0x22a3
10156 #define mmDIG2_HDMI_GENERIC_PACKET_CONTROL8_BASE_IDX                                                   2
10157 #define mmDIG2_HDMI_GENERIC_PACKET_CONTROL9                                                            0x22a4
10158 #define mmDIG2_HDMI_GENERIC_PACKET_CONTROL9_BASE_IDX                                                   2
10159 #define mmDIG2_HDMI_GENERIC_PACKET_CONTROL10                                                           0x22a5
10160 #define mmDIG2_HDMI_GENERIC_PACKET_CONTROL10_BASE_IDX                                                  2
10161 #define mmDIG2_HDMI_DB_CONTROL                                                                         0x22a6
10162 #define mmDIG2_HDMI_DB_CONTROL_BASE_IDX                                                                2
10163 #define mmDIG2_HDMI_ACR_32_0                                                                           0x22a7
10164 #define mmDIG2_HDMI_ACR_32_0_BASE_IDX                                                                  2
10165 #define mmDIG2_HDMI_ACR_32_1                                                                           0x22a8
10166 #define mmDIG2_HDMI_ACR_32_1_BASE_IDX                                                                  2
10167 #define mmDIG2_HDMI_ACR_44_0                                                                           0x22a9
10168 #define mmDIG2_HDMI_ACR_44_0_BASE_IDX                                                                  2
10169 #define mmDIG2_HDMI_ACR_44_1                                                                           0x22aa
10170 #define mmDIG2_HDMI_ACR_44_1_BASE_IDX                                                                  2
10171 #define mmDIG2_HDMI_ACR_48_0                                                                           0x22ab
10172 #define mmDIG2_HDMI_ACR_48_0_BASE_IDX                                                                  2
10173 #define mmDIG2_HDMI_ACR_48_1                                                                           0x22ac
10174 #define mmDIG2_HDMI_ACR_48_1_BASE_IDX                                                                  2
10175 #define mmDIG2_HDMI_ACR_STATUS_0                                                                       0x22ad
10176 #define mmDIG2_HDMI_ACR_STATUS_0_BASE_IDX                                                              2
10177 #define mmDIG2_HDMI_ACR_STATUS_1                                                                       0x22ae
10178 #define mmDIG2_HDMI_ACR_STATUS_1_BASE_IDX                                                              2
10179 #define mmDIG2_AFMT_CNTL                                                                               0x22af
10180 #define mmDIG2_AFMT_CNTL_BASE_IDX                                                                      2
10181 #define mmDIG2_DIG_BE_CNTL                                                                             0x22b0
10182 #define mmDIG2_DIG_BE_CNTL_BASE_IDX                                                                    2
10183 #define mmDIG2_DIG_BE_EN_CNTL                                                                          0x22b1
10184 #define mmDIG2_DIG_BE_EN_CNTL_BASE_IDX                                                                 2
10185 #define mmDIG2_TMDS_CNTL                                                                               0x22d7
10186 #define mmDIG2_TMDS_CNTL_BASE_IDX                                                                      2
10187 #define mmDIG2_TMDS_CONTROL_CHAR                                                                       0x22d8
10188 #define mmDIG2_TMDS_CONTROL_CHAR_BASE_IDX                                                              2
10189 #define mmDIG2_TMDS_CONTROL0_FEEDBACK                                                                  0x22d9
10190 #define mmDIG2_TMDS_CONTROL0_FEEDBACK_BASE_IDX                                                         2
10191 #define mmDIG2_TMDS_STEREOSYNC_CTL_SEL                                                                 0x22da
10192 #define mmDIG2_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX                                                        2
10193 #define mmDIG2_TMDS_SYNC_CHAR_PATTERN_0_1                                                              0x22db
10194 #define mmDIG2_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX                                                     2
10195 #define mmDIG2_TMDS_SYNC_CHAR_PATTERN_2_3                                                              0x22dc
10196 #define mmDIG2_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX                                                     2
10197 #define mmDIG2_TMDS_CTL_BITS                                                                           0x22de
10198 #define mmDIG2_TMDS_CTL_BITS_BASE_IDX                                                                  2
10199 #define mmDIG2_TMDS_DCBALANCER_CONTROL                                                                 0x22df
10200 #define mmDIG2_TMDS_DCBALANCER_CONTROL_BASE_IDX                                                        2
10201 #define mmDIG2_TMDS_SYNC_DCBALANCE_CHAR                                                                0x22e0
10202 #define mmDIG2_TMDS_SYNC_DCBALANCE_CHAR_BASE_IDX                                                       2
10203 #define mmDIG2_TMDS_CTL0_1_GEN_CNTL                                                                    0x22e1
10204 #define mmDIG2_TMDS_CTL0_1_GEN_CNTL_BASE_IDX                                                           2
10205 #define mmDIG2_TMDS_CTL2_3_GEN_CNTL                                                                    0x22e2
10206 #define mmDIG2_TMDS_CTL2_3_GEN_CNTL_BASE_IDX                                                           2
10207 #define mmDIG2_DIG_VERSION                                                                             0x22e4
10208 #define mmDIG2_DIG_VERSION_BASE_IDX                                                                    2
10209 #define mmDIG2_DIG_LANE_ENABLE                                                                         0x22e5
10210 #define mmDIG2_DIG_LANE_ENABLE_BASE_IDX                                                                2
10211 #define mmDIG2_FORCE_DIG_DISABLE                                                                       0x22e6
10212 #define mmDIG2_FORCE_DIG_DISABLE_BASE_IDX                                                              2
10213 
10214 // addressBlock: dce_dc_dio_dp2_dispdec
10215 // base address: 0x800
10216 #define mmDP2_DP_LINK_CNTL                                                                             0x2308
10217 #define mmDP2_DP_LINK_CNTL_BASE_IDX                                                                    2
10218 #define mmDP2_DP_PIXEL_FORMAT                                                                          0x2309
10219 #define mmDP2_DP_PIXEL_FORMAT_BASE_IDX                                                                 2
10220 #define mmDP2_DP_MSA_COLORIMETRY                                                                       0x230a
10221 #define mmDP2_DP_MSA_COLORIMETRY_BASE_IDX                                                              2
10222 #define mmDP2_DP_CONFIG                                                                                0x230b
10223 #define mmDP2_DP_CONFIG_BASE_IDX                                                                       2
10224 #define mmDP2_DP_VID_STREAM_CNTL                                                                       0x230c
10225 #define mmDP2_DP_VID_STREAM_CNTL_BASE_IDX                                                              2
10226 #define mmDP2_DP_STEER_FIFO                                                                            0x230d
10227 #define mmDP2_DP_STEER_FIFO_BASE_IDX                                                                   2
10228 #define mmDP2_DP_MSA_MISC                                                                              0x230e
10229 #define mmDP2_DP_MSA_MISC_BASE_IDX                                                                     2
10230 #define mmDP2_DP_DPHY_INTERNAL_CTRL                                                                    0x230f
10231 #define mmDP2_DP_DPHY_INTERNAL_CTRL_BASE_IDX                                                           2
10232 #define mmDP2_DP_VID_TIMING                                                                            0x2310
10233 #define mmDP2_DP_VID_TIMING_BASE_IDX                                                                   2
10234 #define mmDP2_DP_VID_N                                                                                 0x2311
10235 #define mmDP2_DP_VID_N_BASE_IDX                                                                        2
10236 #define mmDP2_DP_VID_M                                                                                 0x2312
10237 #define mmDP2_DP_VID_M_BASE_IDX                                                                        2
10238 #define mmDP2_DP_LINK_FRAMING_CNTL                                                                     0x2313
10239 #define mmDP2_DP_LINK_FRAMING_CNTL_BASE_IDX                                                            2
10240 #define mmDP2_DP_HBR2_EYE_PATTERN                                                                      0x2314
10241 #define mmDP2_DP_HBR2_EYE_PATTERN_BASE_IDX                                                             2
10242 #define mmDP2_DP_VID_MSA_VBID                                                                          0x2315
10243 #define mmDP2_DP_VID_MSA_VBID_BASE_IDX                                                                 2
10244 #define mmDP2_DP_VID_INTERRUPT_CNTL                                                                    0x2316
10245 #define mmDP2_DP_VID_INTERRUPT_CNTL_BASE_IDX                                                           2
10246 #define mmDP2_DP_DPHY_CNTL                                                                             0x2317
10247 #define mmDP2_DP_DPHY_CNTL_BASE_IDX                                                                    2
10248 #define mmDP2_DP_DPHY_TRAINING_PATTERN_SEL                                                             0x2318
10249 #define mmDP2_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX                                                    2
10250 #define mmDP2_DP_DPHY_SYM0                                                                             0x2319
10251 #define mmDP2_DP_DPHY_SYM0_BASE_IDX                                                                    2
10252 #define mmDP2_DP_DPHY_SYM1                                                                             0x231a
10253 #define mmDP2_DP_DPHY_SYM1_BASE_IDX                                                                    2
10254 #define mmDP2_DP_DPHY_SYM2                                                                             0x231b
10255 #define mmDP2_DP_DPHY_SYM2_BASE_IDX                                                                    2
10256 #define mmDP2_DP_DPHY_8B10B_CNTL                                                                       0x231c
10257 #define mmDP2_DP_DPHY_8B10B_CNTL_BASE_IDX                                                              2
10258 #define mmDP2_DP_DPHY_PRBS_CNTL                                                                        0x231d
10259 #define mmDP2_DP_DPHY_PRBS_CNTL_BASE_IDX                                                               2
10260 #define mmDP2_DP_DPHY_SCRAM_CNTL                                                                       0x231e
10261 #define mmDP2_DP_DPHY_SCRAM_CNTL_BASE_IDX                                                              2
10262 #define mmDP2_DP_DPHY_CRC_EN                                                                           0x231f
10263 #define mmDP2_DP_DPHY_CRC_EN_BASE_IDX                                                                  2
10264 #define mmDP2_DP_DPHY_CRC_CNTL                                                                         0x2320
10265 #define mmDP2_DP_DPHY_CRC_CNTL_BASE_IDX                                                                2
10266 #define mmDP2_DP_DPHY_CRC_RESULT                                                                       0x2321
10267 #define mmDP2_DP_DPHY_CRC_RESULT_BASE_IDX                                                              2
10268 #define mmDP2_DP_DPHY_CRC_MST_CNTL                                                                     0x2322
10269 #define mmDP2_DP_DPHY_CRC_MST_CNTL_BASE_IDX                                                            2
10270 #define mmDP2_DP_DPHY_CRC_MST_STATUS                                                                   0x2323
10271 #define mmDP2_DP_DPHY_CRC_MST_STATUS_BASE_IDX                                                          2
10272 #define mmDP2_DP_DPHY_FAST_TRAINING                                                                    0x2324
10273 #define mmDP2_DP_DPHY_FAST_TRAINING_BASE_IDX                                                           2
10274 #define mmDP2_DP_DPHY_FAST_TRAINING_STATUS                                                             0x2325
10275 #define mmDP2_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX                                                    2
10276 #define mmDP2_DP_SEC_CNTL                                                                              0x232b
10277 #define mmDP2_DP_SEC_CNTL_BASE_IDX                                                                     2
10278 #define mmDP2_DP_SEC_CNTL1                                                                             0x232c
10279 #define mmDP2_DP_SEC_CNTL1_BASE_IDX                                                                    2
10280 #define mmDP2_DP_SEC_FRAMING1                                                                          0x232d
10281 #define mmDP2_DP_SEC_FRAMING1_BASE_IDX                                                                 2
10282 #define mmDP2_DP_SEC_FRAMING2                                                                          0x232e
10283 #define mmDP2_DP_SEC_FRAMING2_BASE_IDX                                                                 2
10284 #define mmDP2_DP_SEC_FRAMING3                                                                          0x232f
10285 #define mmDP2_DP_SEC_FRAMING3_BASE_IDX                                                                 2
10286 #define mmDP2_DP_SEC_FRAMING4                                                                          0x2330
10287 #define mmDP2_DP_SEC_FRAMING4_BASE_IDX                                                                 2
10288 #define mmDP2_DP_SEC_AUD_N                                                                             0x2331
10289 #define mmDP2_DP_SEC_AUD_N_BASE_IDX                                                                    2
10290 #define mmDP2_DP_SEC_AUD_N_READBACK                                                                    0x2332
10291 #define mmDP2_DP_SEC_AUD_N_READBACK_BASE_IDX                                                           2
10292 #define mmDP2_DP_SEC_AUD_M                                                                             0x2333
10293 #define mmDP2_DP_SEC_AUD_M_BASE_IDX                                                                    2
10294 #define mmDP2_DP_SEC_AUD_M_READBACK                                                                    0x2334
10295 #define mmDP2_DP_SEC_AUD_M_READBACK_BASE_IDX                                                           2
10296 #define mmDP2_DP_SEC_TIMESTAMP                                                                         0x2335
10297 #define mmDP2_DP_SEC_TIMESTAMP_BASE_IDX                                                                2
10298 #define mmDP2_DP_SEC_PACKET_CNTL                                                                       0x2336
10299 #define mmDP2_DP_SEC_PACKET_CNTL_BASE_IDX                                                              2
10300 #define mmDP2_DP_MSE_RATE_CNTL                                                                         0x2337
10301 #define mmDP2_DP_MSE_RATE_CNTL_BASE_IDX                                                                2
10302 #define mmDP2_DP_MSE_RATE_UPDATE                                                                       0x2339
10303 #define mmDP2_DP_MSE_RATE_UPDATE_BASE_IDX                                                              2
10304 #define mmDP2_DP_MSE_SAT0                                                                              0x233a
10305 #define mmDP2_DP_MSE_SAT0_BASE_IDX                                                                     2
10306 #define mmDP2_DP_MSE_SAT1                                                                              0x233b
10307 #define mmDP2_DP_MSE_SAT1_BASE_IDX                                                                     2
10308 #define mmDP2_DP_MSE_SAT2                                                                              0x233c
10309 #define mmDP2_DP_MSE_SAT2_BASE_IDX                                                                     2
10310 #define mmDP2_DP_MSE_SAT_UPDATE                                                                        0x233d
10311 #define mmDP2_DP_MSE_SAT_UPDATE_BASE_IDX                                                               2
10312 #define mmDP2_DP_MSE_LINK_TIMING                                                                       0x233e
10313 #define mmDP2_DP_MSE_LINK_TIMING_BASE_IDX                                                              2
10314 #define mmDP2_DP_MSE_MISC_CNTL                                                                         0x233f
10315 #define mmDP2_DP_MSE_MISC_CNTL_BASE_IDX                                                                2
10316 #define mmDP2_DP_DPHY_BS_SR_SWAP_CNTL                                                                  0x2344
10317 #define mmDP2_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX                                                         2
10318 #define mmDP2_DP_DPHY_HBR2_PATTERN_CONTROL                                                             0x2345
10319 #define mmDP2_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX                                                    2
10320 #define mmDP2_DP_MSE_SAT0_STATUS                                                                       0x2347
10321 #define mmDP2_DP_MSE_SAT0_STATUS_BASE_IDX                                                              2
10322 #define mmDP2_DP_MSE_SAT1_STATUS                                                                       0x2348
10323 #define mmDP2_DP_MSE_SAT1_STATUS_BASE_IDX                                                              2
10324 #define mmDP2_DP_MSE_SAT2_STATUS                                                                       0x2349
10325 #define mmDP2_DP_MSE_SAT2_STATUS_BASE_IDX                                                              2
10326 #define mmDP2_DP_MSA_TIMING_PARAM1                                                                     0x234c
10327 #define mmDP2_DP_MSA_TIMING_PARAM1_BASE_IDX                                                            2
10328 #define mmDP2_DP_MSA_TIMING_PARAM2                                                                     0x234d
10329 #define mmDP2_DP_MSA_TIMING_PARAM2_BASE_IDX                                                            2
10330 #define mmDP2_DP_MSA_TIMING_PARAM3                                                                     0x234e
10331 #define mmDP2_DP_MSA_TIMING_PARAM3_BASE_IDX                                                            2
10332 #define mmDP2_DP_MSA_TIMING_PARAM4                                                                     0x234f
10333 #define mmDP2_DP_MSA_TIMING_PARAM4_BASE_IDX                                                            2
10334 #define mmDP2_DP_MSO_CNTL                                                                              0x2350
10335 #define mmDP2_DP_MSO_CNTL_BASE_IDX                                                                     2
10336 #define mmDP2_DP_MSO_CNTL1                                                                             0x2351
10337 #define mmDP2_DP_MSO_CNTL1_BASE_IDX                                                                    2
10338 #define mmDP2_DP_DSC_CNTL                                                                              0x2352
10339 #define mmDP2_DP_DSC_CNTL_BASE_IDX                                                                     2
10340 #define mmDP2_DP_SEC_CNTL2                                                                             0x2353
10341 #define mmDP2_DP_SEC_CNTL2_BASE_IDX                                                                    2
10342 #define mmDP2_DP_SEC_CNTL3                                                                             0x2354
10343 #define mmDP2_DP_SEC_CNTL3_BASE_IDX                                                                    2
10344 #define mmDP2_DP_SEC_CNTL4                                                                             0x2355
10345 #define mmDP2_DP_SEC_CNTL4_BASE_IDX                                                                    2
10346 #define mmDP2_DP_SEC_CNTL5                                                                             0x2356
10347 #define mmDP2_DP_SEC_CNTL5_BASE_IDX                                                                    2
10348 #define mmDP2_DP_SEC_CNTL6                                                                             0x2357
10349 #define mmDP2_DP_SEC_CNTL6_BASE_IDX                                                                    2
10350 #define mmDP2_DP_SEC_CNTL7                                                                             0x2358
10351 #define mmDP2_DP_SEC_CNTL7_BASE_IDX                                                                    2
10352 #define mmDP2_DP_DB_CNTL                                                                               0x2359
10353 #define mmDP2_DP_DB_CNTL_BASE_IDX                                                                      2
10354 #define mmDP2_DP_MSA_VBID_MISC                                                                         0x235a
10355 #define mmDP2_DP_MSA_VBID_MISC_BASE_IDX                                                                2
10356 #define mmDP2_DP_SEC_METADATA_TRANSMISSION                                                             0x235b
10357 #define mmDP2_DP_SEC_METADATA_TRANSMISSION_BASE_IDX                                                    2
10358 #define mmDP2_DP_DSC_BYTES_PER_PIXEL                                                                   0x235c
10359 #define mmDP2_DP_DSC_BYTES_PER_PIXEL_BASE_IDX                                                          2
10360 #define mmDP2_DP_ALPM_CNTL                                                                             0x235d
10361 #define mmDP2_DP_ALPM_CNTL_BASE_IDX                                                                    2
10362 #define mmDP2_DP_GSP8_CNTL                                                                             0x235e
10363 #define mmDP2_DP_GSP8_CNTL_BASE_IDX                                                                    2
10364 #define mmDP2_DP_GSP9_CNTL                                                                             0x235f
10365 #define mmDP2_DP_GSP9_CNTL_BASE_IDX                                                                    2
10366 #define mmDP2_DP_GSP10_CNTL                                                                            0x2360
10367 #define mmDP2_DP_GSP10_CNTL_BASE_IDX                                                                   2
10368 #define mmDP2_DP_GSP11_CNTL                                                                            0x2361
10369 #define mmDP2_DP_GSP11_CNTL_BASE_IDX                                                                   2
10370 #define mmDP2_DP_GSP_EN_DB_STATUS                                                                      0x2362
10371 #define mmDP2_DP_GSP_EN_DB_STATUS_BASE_IDX                                                             2
10372 
10373 
10374 // addressBlock: dce_dc_dio_dig3_vpg_vpg_dispdec
10375 // base address: 0x160a0
10376 #define mmVPG3_VPG_GENERIC_PACKET_ACCESS_CTRL                                                          0x2368
10377 #define mmVPG3_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX                                                 2
10378 #define mmVPG3_VPG_GENERIC_PACKET_DATA                                                                 0x2369
10379 #define mmVPG3_VPG_GENERIC_PACKET_DATA_BASE_IDX                                                        2
10380 #define mmVPG3_VPG_GSP_FRAME_UPDATE_CTRL                                                               0x236a
10381 #define mmVPG3_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX                                                      2
10382 #define mmVPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL                                                           0x236b
10383 #define mmVPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX                                                  2
10384 #define mmVPG3_VPG_GENERIC_STATUS                                                                      0x236c
10385 #define mmVPG3_VPG_GENERIC_STATUS_BASE_IDX                                                             2
10386 #define mmVPG3_VPG_MEM_PWR                                                                             0x236d
10387 #define mmVPG3_VPG_MEM_PWR_BASE_IDX                                                                    2
10388 #define mmVPG3_VPG_ISRC1_2_ACCESS_CTRL                                                                 0x236e
10389 #define mmVPG3_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX                                                        2
10390 #define mmVPG3_VPG_ISRC1_2_DATA                                                                        0x236f
10391 #define mmVPG3_VPG_ISRC1_2_DATA_BASE_IDX                                                               2
10392 #define mmVPG3_VPG_MPEG_INFO0                                                                          0x2370
10393 #define mmVPG3_VPG_MPEG_INFO0_BASE_IDX                                                                 2
10394 #define mmVPG3_VPG_MPEG_INFO1                                                                          0x2371
10395 #define mmVPG3_VPG_MPEG_INFO1_BASE_IDX                                                                 2
10396 
10397 
10398 // addressBlock: dce_dc_dio_dig3_afmt_afmt_dispdec
10399 // base address: 0x160cc
10400 #define mmAFMT3_AFMT_VBI_PACKET_CONTROL                                                                0x2374
10401 #define mmAFMT3_AFMT_VBI_PACKET_CONTROL_BASE_IDX                                                       2
10402 #define mmAFMT3_AFMT_AUDIO_PACKET_CONTROL2                                                             0x2375
10403 #define mmAFMT3_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX                                                    2
10404 #define mmAFMT3_AFMT_AUDIO_INFO0                                                                       0x2376
10405 #define mmAFMT3_AFMT_AUDIO_INFO0_BASE_IDX                                                              2
10406 #define mmAFMT3_AFMT_AUDIO_INFO1                                                                       0x2377
10407 #define mmAFMT3_AFMT_AUDIO_INFO1_BASE_IDX                                                              2
10408 #define mmAFMT3_AFMT_60958_0                                                                           0x2378
10409 #define mmAFMT3_AFMT_60958_0_BASE_IDX                                                                  2
10410 #define mmAFMT3_AFMT_60958_1                                                                           0x2379
10411 #define mmAFMT3_AFMT_60958_1_BASE_IDX                                                                  2
10412 #define mmAFMT3_AFMT_AUDIO_CRC_CONTROL                                                                 0x237a
10413 #define mmAFMT3_AFMT_AUDIO_CRC_CONTROL_BASE_IDX                                                        2
10414 #define mmAFMT3_AFMT_RAMP_CONTROL0                                                                     0x237b
10415 #define mmAFMT3_AFMT_RAMP_CONTROL0_BASE_IDX                                                            2
10416 #define mmAFMT3_AFMT_RAMP_CONTROL1                                                                     0x237c
10417 #define mmAFMT3_AFMT_RAMP_CONTROL1_BASE_IDX                                                            2
10418 #define mmAFMT3_AFMT_RAMP_CONTROL2                                                                     0x237d
10419 #define mmAFMT3_AFMT_RAMP_CONTROL2_BASE_IDX                                                            2
10420 #define mmAFMT3_AFMT_RAMP_CONTROL3                                                                     0x237e
10421 #define mmAFMT3_AFMT_RAMP_CONTROL3_BASE_IDX                                                            2
10422 #define mmAFMT3_AFMT_60958_2                                                                           0x237f
10423 #define mmAFMT3_AFMT_60958_2_BASE_IDX                                                                  2
10424 #define mmAFMT3_AFMT_AUDIO_CRC_RESULT                                                                  0x2380
10425 #define mmAFMT3_AFMT_AUDIO_CRC_RESULT_BASE_IDX                                                         2
10426 #define mmAFMT3_AFMT_STATUS                                                                            0x2381
10427 #define mmAFMT3_AFMT_STATUS_BASE_IDX                                                                   2
10428 #define mmAFMT3_AFMT_AUDIO_PACKET_CONTROL                                                              0x2382
10429 #define mmAFMT3_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX                                                     2
10430 #define mmAFMT3_AFMT_INFOFRAME_CONTROL0                                                                0x2383
10431 #define mmAFMT3_AFMT_INFOFRAME_CONTROL0_BASE_IDX                                                       2
10432 #define mmAFMT3_AFMT_INTERRUPT_STATUS                                                                  0x2384
10433 #define mmAFMT3_AFMT_INTERRUPT_STATUS_BASE_IDX                                                         2
10434 #define mmAFMT3_AFMT_AUDIO_SRC_CONTROL                                                                 0x2385
10435 #define mmAFMT3_AFMT_AUDIO_SRC_CONTROL_BASE_IDX                                                        2
10436 #define mmAFMT3_AFMT_MEM_PWR                                                                           0x2387
10437 #define mmAFMT3_AFMT_MEM_PWR_BASE_IDX                                                                  2
10438 
10439 
10440 // addressBlock: dce_dc_dio_dig3_dme_dme_dispdec
10441 // base address: 0x16124
10442 #define mmDME3_DME_CONTROL                                                                             0x2389
10443 #define mmDME3_DME_CONTROL_BASE_IDX                                                                    2
10444 #define mmDME3_DME_MEMORY_CONTROL                                                                      0x238a
10445 #define mmDME3_DME_MEMORY_CONTROL_BASE_IDX                                                             2
10446 
10447 
10448 // addressBlock: dce_dc_dio_dig3_dispdec
10449 // base address: 0xc00
10450 #define mmDIG3_DIG_FE_CNTL                                                                             0x238b
10451 #define mmDIG3_DIG_FE_CNTL_BASE_IDX                                                                    2
10452 #define mmDIG3_DIG_OUTPUT_CRC_CNTL                                                                     0x238c
10453 #define mmDIG3_DIG_OUTPUT_CRC_CNTL_BASE_IDX                                                            2
10454 #define mmDIG3_DIG_OUTPUT_CRC_RESULT                                                                   0x238d
10455 #define mmDIG3_DIG_OUTPUT_CRC_RESULT_BASE_IDX                                                          2
10456 #define mmDIG3_DIG_CLOCK_PATTERN                                                                       0x238e
10457 #define mmDIG3_DIG_CLOCK_PATTERN_BASE_IDX                                                              2
10458 #define mmDIG3_DIG_TEST_PATTERN                                                                        0x238f
10459 #define mmDIG3_DIG_TEST_PATTERN_BASE_IDX                                                               2
10460 #define mmDIG3_DIG_RANDOM_PATTERN_SEED                                                                 0x2390
10461 #define mmDIG3_DIG_RANDOM_PATTERN_SEED_BASE_IDX                                                        2
10462 #define mmDIG3_DIG_FIFO_STATUS                                                                         0x2391
10463 #define mmDIG3_DIG_FIFO_STATUS_BASE_IDX                                                                2
10464 #define mmDIG3_HDMI_METADATA_PACKET_CONTROL                                                            0x2392
10465 #define mmDIG3_HDMI_METADATA_PACKET_CONTROL_BASE_IDX                                                   2
10466 #define mmDIG3_HDMI_CONTROL                                                                            0x2393
10467 #define mmDIG3_HDMI_CONTROL_BASE_IDX                                                                   2
10468 #define mmDIG3_HDMI_STATUS                                                                             0x2394
10469 #define mmDIG3_HDMI_STATUS_BASE_IDX                                                                    2
10470 #define mmDIG3_HDMI_AUDIO_PACKET_CONTROL                                                               0x2395
10471 #define mmDIG3_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX                                                      2
10472 #define mmDIG3_HDMI_ACR_PACKET_CONTROL                                                                 0x2396
10473 #define mmDIG3_HDMI_ACR_PACKET_CONTROL_BASE_IDX                                                        2
10474 #define mmDIG3_HDMI_VBI_PACKET_CONTROL                                                                 0x2397
10475 #define mmDIG3_HDMI_VBI_PACKET_CONTROL_BASE_IDX                                                        2
10476 #define mmDIG3_HDMI_INFOFRAME_CONTROL0                                                                 0x2398
10477 #define mmDIG3_HDMI_INFOFRAME_CONTROL0_BASE_IDX                                                        2
10478 #define mmDIG3_HDMI_INFOFRAME_CONTROL1                                                                 0x2399
10479 #define mmDIG3_HDMI_INFOFRAME_CONTROL1_BASE_IDX                                                        2
10480 #define mmDIG3_HDMI_GENERIC_PACKET_CONTROL0                                                            0x239a
10481 #define mmDIG3_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX                                                   2
10482 #define mmDIG3_HDMI_GENERIC_PACKET_CONTROL6                                                            0x239b
10483 #define mmDIG3_HDMI_GENERIC_PACKET_CONTROL6_BASE_IDX                                                   2
10484 #define mmDIG3_HDMI_GENERIC_PACKET_CONTROL5                                                            0x239c
10485 #define mmDIG3_HDMI_GENERIC_PACKET_CONTROL5_BASE_IDX                                                   2
10486 #define mmDIG3_HDMI_GC                                                                                 0x239d
10487 #define mmDIG3_HDMI_GC_BASE_IDX                                                                        2
10488 #define mmDIG3_HDMI_GENERIC_PACKET_CONTROL1                                                            0x239e
10489 #define mmDIG3_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX                                                   2
10490 #define mmDIG3_HDMI_GENERIC_PACKET_CONTROL2                                                            0x239f
10491 #define mmDIG3_HDMI_GENERIC_PACKET_CONTROL2_BASE_IDX                                                   2
10492 #define mmDIG3_HDMI_GENERIC_PACKET_CONTROL3                                                            0x23a0
10493 #define mmDIG3_HDMI_GENERIC_PACKET_CONTROL3_BASE_IDX                                                   2
10494 #define mmDIG3_HDMI_GENERIC_PACKET_CONTROL4                                                            0x23a1
10495 #define mmDIG3_HDMI_GENERIC_PACKET_CONTROL4_BASE_IDX                                                   2
10496 #define mmDIG3_HDMI_GENERIC_PACKET_CONTROL7                                                            0x23a2
10497 #define mmDIG3_HDMI_GENERIC_PACKET_CONTROL7_BASE_IDX                                                   2
10498 #define mmDIG3_HDMI_GENERIC_PACKET_CONTROL8                                                            0x23a3
10499 #define mmDIG3_HDMI_GENERIC_PACKET_CONTROL8_BASE_IDX                                                   2
10500 #define mmDIG3_HDMI_GENERIC_PACKET_CONTROL9                                                            0x23a4
10501 #define mmDIG3_HDMI_GENERIC_PACKET_CONTROL9_BASE_IDX                                                   2
10502 #define mmDIG3_HDMI_GENERIC_PACKET_CONTROL10                                                           0x23a5
10503 #define mmDIG3_HDMI_GENERIC_PACKET_CONTROL10_BASE_IDX                                                  2
10504 #define mmDIG3_HDMI_DB_CONTROL                                                                         0x23a6
10505 #define mmDIG3_HDMI_DB_CONTROL_BASE_IDX                                                                2
10506 #define mmDIG3_HDMI_ACR_32_0                                                                           0x23a7
10507 #define mmDIG3_HDMI_ACR_32_0_BASE_IDX                                                                  2
10508 #define mmDIG3_HDMI_ACR_32_1                                                                           0x23a8
10509 #define mmDIG3_HDMI_ACR_32_1_BASE_IDX                                                                  2
10510 #define mmDIG3_HDMI_ACR_44_0                                                                           0x23a9
10511 #define mmDIG3_HDMI_ACR_44_0_BASE_IDX                                                                  2
10512 #define mmDIG3_HDMI_ACR_44_1                                                                           0x23aa
10513 #define mmDIG3_HDMI_ACR_44_1_BASE_IDX                                                                  2
10514 #define mmDIG3_HDMI_ACR_48_0                                                                           0x23ab
10515 #define mmDIG3_HDMI_ACR_48_0_BASE_IDX                                                                  2
10516 #define mmDIG3_HDMI_ACR_48_1                                                                           0x23ac
10517 #define mmDIG3_HDMI_ACR_48_1_BASE_IDX                                                                  2
10518 #define mmDIG3_HDMI_ACR_STATUS_0                                                                       0x23ad
10519 #define mmDIG3_HDMI_ACR_STATUS_0_BASE_IDX                                                              2
10520 #define mmDIG3_HDMI_ACR_STATUS_1                                                                       0x23ae
10521 #define mmDIG3_HDMI_ACR_STATUS_1_BASE_IDX                                                              2
10522 #define mmDIG3_AFMT_CNTL                                                                               0x23af
10523 #define mmDIG3_AFMT_CNTL_BASE_IDX                                                                      2
10524 #define mmDIG3_DIG_BE_CNTL                                                                             0x23b0
10525 #define mmDIG3_DIG_BE_CNTL_BASE_IDX                                                                    2
10526 #define mmDIG3_DIG_BE_EN_CNTL                                                                          0x23b1
10527 #define mmDIG3_DIG_BE_EN_CNTL_BASE_IDX                                                                 2
10528 #define mmDIG3_TMDS_CNTL                                                                               0x23d7
10529 #define mmDIG3_TMDS_CNTL_BASE_IDX                                                                      2
10530 #define mmDIG3_TMDS_CONTROL_CHAR                                                                       0x23d8
10531 #define mmDIG3_TMDS_CONTROL_CHAR_BASE_IDX                                                              2
10532 #define mmDIG3_TMDS_CONTROL0_FEEDBACK                                                                  0x23d9
10533 #define mmDIG3_TMDS_CONTROL0_FEEDBACK_BASE_IDX                                                         2
10534 #define mmDIG3_TMDS_STEREOSYNC_CTL_SEL                                                                 0x23da
10535 #define mmDIG3_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX                                                        2
10536 #define mmDIG3_TMDS_SYNC_CHAR_PATTERN_0_1                                                              0x23db
10537 #define mmDIG3_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX                                                     2
10538 #define mmDIG3_TMDS_SYNC_CHAR_PATTERN_2_3                                                              0x23dc
10539 #define mmDIG3_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX                                                     2
10540 #define mmDIG3_TMDS_CTL_BITS                                                                           0x23de
10541 #define mmDIG3_TMDS_CTL_BITS_BASE_IDX                                                                  2
10542 #define mmDIG3_TMDS_DCBALANCER_CONTROL                                                                 0x23df
10543 #define mmDIG3_TMDS_DCBALANCER_CONTROL_BASE_IDX                                                        2
10544 #define mmDIG3_TMDS_SYNC_DCBALANCE_CHAR                                                                0x23e0
10545 #define mmDIG3_TMDS_SYNC_DCBALANCE_CHAR_BASE_IDX                                                       2
10546 #define mmDIG3_TMDS_CTL0_1_GEN_CNTL                                                                    0x23e1
10547 #define mmDIG3_TMDS_CTL0_1_GEN_CNTL_BASE_IDX                                                           2
10548 #define mmDIG3_TMDS_CTL2_3_GEN_CNTL                                                                    0x23e2
10549 #define mmDIG3_TMDS_CTL2_3_GEN_CNTL_BASE_IDX                                                           2
10550 #define mmDIG3_DIG_VERSION                                                                             0x23e4
10551 #define mmDIG3_DIG_VERSION_BASE_IDX                                                                    2
10552 #define mmDIG3_DIG_LANE_ENABLE                                                                         0x23e5
10553 #define mmDIG3_DIG_LANE_ENABLE_BASE_IDX                                                                2
10554 #define mmDIG3_FORCE_DIG_DISABLE                                                                       0x23e6
10555 #define mmDIG3_FORCE_DIG_DISABLE_BASE_IDX                                                              2
10556 
10557 
10558 // addressBlock: dce_dc_dio_dp3_dispdec
10559 // base address: 0xc00
10560 #define mmDP3_DP_LINK_CNTL                                                                             0x2408
10561 #define mmDP3_DP_LINK_CNTL_BASE_IDX                                                                    2
10562 #define mmDP3_DP_PIXEL_FORMAT                                                                          0x2409
10563 #define mmDP3_DP_PIXEL_FORMAT_BASE_IDX                                                                 2
10564 #define mmDP3_DP_MSA_COLORIMETRY                                                                       0x240a
10565 #define mmDP3_DP_MSA_COLORIMETRY_BASE_IDX                                                              2
10566 #define mmDP3_DP_CONFIG                                                                                0x240b
10567 #define mmDP3_DP_CONFIG_BASE_IDX                                                                       2
10568 #define mmDP3_DP_VID_STREAM_CNTL                                                                       0x240c
10569 #define mmDP3_DP_VID_STREAM_CNTL_BASE_IDX                                                              2
10570 #define mmDP3_DP_STEER_FIFO                                                                            0x240d
10571 #define mmDP3_DP_STEER_FIFO_BASE_IDX                                                                   2
10572 #define mmDP3_DP_MSA_MISC                                                                              0x240e
10573 #define mmDP3_DP_MSA_MISC_BASE_IDX                                                                     2
10574 #define mmDP3_DP_DPHY_INTERNAL_CTRL                                                                    0x240f
10575 #define mmDP3_DP_DPHY_INTERNAL_CTRL_BASE_IDX                                                           2
10576 #define mmDP3_DP_VID_TIMING                                                                            0x2410
10577 #define mmDP3_DP_VID_TIMING_BASE_IDX                                                                   2
10578 #define mmDP3_DP_VID_N                                                                                 0x2411
10579 #define mmDP3_DP_VID_N_BASE_IDX                                                                        2
10580 #define mmDP3_DP_VID_M                                                                                 0x2412
10581 #define mmDP3_DP_VID_M_BASE_IDX                                                                        2
10582 #define mmDP3_DP_LINK_FRAMING_CNTL                                                                     0x2413
10583 #define mmDP3_DP_LINK_FRAMING_CNTL_BASE_IDX                                                            2
10584 #define mmDP3_DP_HBR2_EYE_PATTERN                                                                      0x2414
10585 #define mmDP3_DP_HBR2_EYE_PATTERN_BASE_IDX                                                             2
10586 #define mmDP3_DP_VID_MSA_VBID                                                                          0x2415
10587 #define mmDP3_DP_VID_MSA_VBID_BASE_IDX                                                                 2
10588 #define mmDP3_DP_VID_INTERRUPT_CNTL                                                                    0x2416
10589 #define mmDP3_DP_VID_INTERRUPT_CNTL_BASE_IDX                                                           2
10590 #define mmDP3_DP_DPHY_CNTL                                                                             0x2417
10591 #define mmDP3_DP_DPHY_CNTL_BASE_IDX                                                                    2
10592 #define mmDP3_DP_DPHY_TRAINING_PATTERN_SEL                                                             0x2418
10593 #define mmDP3_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX                                                    2
10594 #define mmDP3_DP_DPHY_SYM0                                                                             0x2419
10595 #define mmDP3_DP_DPHY_SYM0_BASE_IDX                                                                    2
10596 #define mmDP3_DP_DPHY_SYM1                                                                             0x241a
10597 #define mmDP3_DP_DPHY_SYM1_BASE_IDX                                                                    2
10598 #define mmDP3_DP_DPHY_SYM2                                                                             0x241b
10599 #define mmDP3_DP_DPHY_SYM2_BASE_IDX                                                                    2
10600 #define mmDP3_DP_DPHY_8B10B_CNTL                                                                       0x241c
10601 #define mmDP3_DP_DPHY_8B10B_CNTL_BASE_IDX                                                              2
10602 #define mmDP3_DP_DPHY_PRBS_CNTL                                                                        0x241d
10603 #define mmDP3_DP_DPHY_PRBS_CNTL_BASE_IDX                                                               2
10604 #define mmDP3_DP_DPHY_SCRAM_CNTL                                                                       0x241e
10605 #define mmDP3_DP_DPHY_SCRAM_CNTL_BASE_IDX                                                              2
10606 #define mmDP3_DP_DPHY_CRC_EN                                                                           0x241f
10607 #define mmDP3_DP_DPHY_CRC_EN_BASE_IDX                                                                  2
10608 #define mmDP3_DP_DPHY_CRC_CNTL                                                                         0x2420
10609 #define mmDP3_DP_DPHY_CRC_CNTL_BASE_IDX                                                                2
10610 #define mmDP3_DP_DPHY_CRC_RESULT                                                                       0x2421
10611 #define mmDP3_DP_DPHY_CRC_RESULT_BASE_IDX                                                              2
10612 #define mmDP3_DP_DPHY_CRC_MST_CNTL                                                                     0x2422
10613 #define mmDP3_DP_DPHY_CRC_MST_CNTL_BASE_IDX                                                            2
10614 #define mmDP3_DP_DPHY_CRC_MST_STATUS                                                                   0x2423
10615 #define mmDP3_DP_DPHY_CRC_MST_STATUS_BASE_IDX                                                          2
10616 #define mmDP3_DP_DPHY_FAST_TRAINING                                                                    0x2424
10617 #define mmDP3_DP_DPHY_FAST_TRAINING_BASE_IDX                                                           2
10618 #define mmDP3_DP_DPHY_FAST_TRAINING_STATUS                                                             0x2425
10619 #define mmDP3_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX                                                    2
10620 #define mmDP3_DP_SEC_CNTL                                                                              0x242b
10621 #define mmDP3_DP_SEC_CNTL_BASE_IDX                                                                     2
10622 #define mmDP3_DP_SEC_CNTL1                                                                             0x242c
10623 #define mmDP3_DP_SEC_CNTL1_BASE_IDX                                                                    2
10624 #define mmDP3_DP_SEC_FRAMING1                                                                          0x242d
10625 #define mmDP3_DP_SEC_FRAMING1_BASE_IDX                                                                 2
10626 #define mmDP3_DP_SEC_FRAMING2                                                                          0x242e
10627 #define mmDP3_DP_SEC_FRAMING2_BASE_IDX                                                                 2
10628 #define mmDP3_DP_SEC_FRAMING3                                                                          0x242f
10629 #define mmDP3_DP_SEC_FRAMING3_BASE_IDX                                                                 2
10630 #define mmDP3_DP_SEC_FRAMING4                                                                          0x2430
10631 #define mmDP3_DP_SEC_FRAMING4_BASE_IDX                                                                 2
10632 #define mmDP3_DP_SEC_AUD_N                                                                             0x2431
10633 #define mmDP3_DP_SEC_AUD_N_BASE_IDX                                                                    2
10634 #define mmDP3_DP_SEC_AUD_N_READBACK                                                                    0x2432
10635 #define mmDP3_DP_SEC_AUD_N_READBACK_BASE_IDX                                                           2
10636 #define mmDP3_DP_SEC_AUD_M                                                                             0x2433
10637 #define mmDP3_DP_SEC_AUD_M_BASE_IDX                                                                    2
10638 #define mmDP3_DP_SEC_AUD_M_READBACK                                                                    0x2434
10639 #define mmDP3_DP_SEC_AUD_M_READBACK_BASE_IDX                                                           2
10640 #define mmDP3_DP_SEC_TIMESTAMP                                                                         0x2435
10641 #define mmDP3_DP_SEC_TIMESTAMP_BASE_IDX                                                                2
10642 #define mmDP3_DP_SEC_PACKET_CNTL                                                                       0x2436
10643 #define mmDP3_DP_SEC_PACKET_CNTL_BASE_IDX                                                              2
10644 #define mmDP3_DP_MSE_RATE_CNTL                                                                         0x2437
10645 #define mmDP3_DP_MSE_RATE_CNTL_BASE_IDX                                                                2
10646 #define mmDP3_DP_MSE_RATE_UPDATE                                                                       0x2439
10647 #define mmDP3_DP_MSE_RATE_UPDATE_BASE_IDX                                                              2
10648 #define mmDP3_DP_MSE_SAT0                                                                              0x243a
10649 #define mmDP3_DP_MSE_SAT0_BASE_IDX                                                                     2
10650 #define mmDP3_DP_MSE_SAT1                                                                              0x243b
10651 #define mmDP3_DP_MSE_SAT1_BASE_IDX                                                                     2
10652 #define mmDP3_DP_MSE_SAT2                                                                              0x243c
10653 #define mmDP3_DP_MSE_SAT2_BASE_IDX                                                                     2
10654 #define mmDP3_DP_MSE_SAT_UPDATE                                                                        0x243d
10655 #define mmDP3_DP_MSE_SAT_UPDATE_BASE_IDX                                                               2
10656 #define mmDP3_DP_MSE_LINK_TIMING                                                                       0x243e
10657 #define mmDP3_DP_MSE_LINK_TIMING_BASE_IDX                                                              2
10658 #define mmDP3_DP_MSE_MISC_CNTL                                                                         0x243f
10659 #define mmDP3_DP_MSE_MISC_CNTL_BASE_IDX                                                                2
10660 #define mmDP3_DP_DPHY_BS_SR_SWAP_CNTL                                                                  0x2444
10661 #define mmDP3_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX                                                         2
10662 #define mmDP3_DP_DPHY_HBR2_PATTERN_CONTROL                                                             0x2445
10663 #define mmDP3_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX                                                    2
10664 #define mmDP3_DP_MSE_SAT0_STATUS                                                                       0x2447
10665 #define mmDP3_DP_MSE_SAT0_STATUS_BASE_IDX                                                              2
10666 #define mmDP3_DP_MSE_SAT1_STATUS                                                                       0x2448
10667 #define mmDP3_DP_MSE_SAT1_STATUS_BASE_IDX                                                              2
10668 #define mmDP3_DP_MSE_SAT2_STATUS                                                                       0x2449
10669 #define mmDP3_DP_MSE_SAT2_STATUS_BASE_IDX                                                              2
10670 #define mmDP3_DP_MSA_TIMING_PARAM1                                                                     0x244c
10671 #define mmDP3_DP_MSA_TIMING_PARAM1_BASE_IDX                                                            2
10672 #define mmDP3_DP_MSA_TIMING_PARAM2                                                                     0x244d
10673 #define mmDP3_DP_MSA_TIMING_PARAM2_BASE_IDX                                                            2
10674 #define mmDP3_DP_MSA_TIMING_PARAM3                                                                     0x244e
10675 #define mmDP3_DP_MSA_TIMING_PARAM3_BASE_IDX                                                            2
10676 #define mmDP3_DP_MSA_TIMING_PARAM4                                                                     0x244f
10677 #define mmDP3_DP_MSA_TIMING_PARAM4_BASE_IDX                                                            2
10678 #define mmDP3_DP_MSO_CNTL                                                                              0x2450
10679 #define mmDP3_DP_MSO_CNTL_BASE_IDX                                                                     2
10680 #define mmDP3_DP_MSO_CNTL1                                                                             0x2451
10681 #define mmDP3_DP_MSO_CNTL1_BASE_IDX                                                                    2
10682 #define mmDP3_DP_DSC_CNTL                                                                              0x2452
10683 #define mmDP3_DP_DSC_CNTL_BASE_IDX                                                                     2
10684 #define mmDP3_DP_SEC_CNTL2                                                                             0x2453
10685 #define mmDP3_DP_SEC_CNTL2_BASE_IDX                                                                    2
10686 #define mmDP3_DP_SEC_CNTL3                                                                             0x2454
10687 #define mmDP3_DP_SEC_CNTL3_BASE_IDX                                                                    2
10688 #define mmDP3_DP_SEC_CNTL4                                                                             0x2455
10689 #define mmDP3_DP_SEC_CNTL4_BASE_IDX                                                                    2
10690 #define mmDP3_DP_SEC_CNTL5                                                                             0x2456
10691 #define mmDP3_DP_SEC_CNTL5_BASE_IDX                                                                    2
10692 #define mmDP3_DP_SEC_CNTL6                                                                             0x2457
10693 #define mmDP3_DP_SEC_CNTL6_BASE_IDX                                                                    2
10694 #define mmDP3_DP_SEC_CNTL7                                                                             0x2458
10695 #define mmDP3_DP_SEC_CNTL7_BASE_IDX                                                                    2
10696 #define mmDP3_DP_DB_CNTL                                                                               0x2459
10697 #define mmDP3_DP_DB_CNTL_BASE_IDX                                                                      2
10698 #define mmDP3_DP_MSA_VBID_MISC                                                                         0x245a
10699 #define mmDP3_DP_MSA_VBID_MISC_BASE_IDX                                                                2
10700 #define mmDP3_DP_SEC_METADATA_TRANSMISSION                                                             0x245b
10701 #define mmDP3_DP_SEC_METADATA_TRANSMISSION_BASE_IDX                                                    2
10702 #define mmDP3_DP_DSC_BYTES_PER_PIXEL                                                                   0x245c
10703 #define mmDP3_DP_DSC_BYTES_PER_PIXEL_BASE_IDX                                                          2
10704 #define mmDP3_DP_ALPM_CNTL                                                                             0x245d
10705 #define mmDP3_DP_ALPM_CNTL_BASE_IDX                                                                    2
10706 #define mmDP3_DP_GSP8_CNTL                                                                             0x245e
10707 #define mmDP3_DP_GSP8_CNTL_BASE_IDX                                                                    2
10708 #define mmDP3_DP_GSP9_CNTL                                                                             0x245f
10709 #define mmDP3_DP_GSP9_CNTL_BASE_IDX                                                                    2
10710 #define mmDP3_DP_GSP10_CNTL                                                                            0x2460
10711 #define mmDP3_DP_GSP10_CNTL_BASE_IDX                                                                   2
10712 #define mmDP3_DP_GSP11_CNTL                                                                            0x2461
10713 #define mmDP3_DP_GSP11_CNTL_BASE_IDX                                                                   2
10714 #define mmDP3_DP_GSP_EN_DB_STATUS                                                                      0x2462
10715 #define mmDP3_DP_GSP_EN_DB_STATUS_BASE_IDX                                                             2
10716 
10717 
10718 // addressBlock: dce_dc_dio_dig4_vpg_vpg_dispdec
10719 // base address: 0x164a0
10720 #define mmVPG4_VPG_GENERIC_PACKET_ACCESS_CTRL                                                          0x2468
10721 #define mmVPG4_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX                                                 2
10722 #define mmVPG4_VPG_GENERIC_PACKET_DATA                                                                 0x2469
10723 #define mmVPG4_VPG_GENERIC_PACKET_DATA_BASE_IDX                                                        2
10724 #define mmVPG4_VPG_GSP_FRAME_UPDATE_CTRL                                                               0x246a
10725 #define mmVPG4_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX                                                      2
10726 #define mmVPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL                                                           0x246b
10727 #define mmVPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX                                                  2
10728 #define mmVPG4_VPG_GENERIC_STATUS                                                                      0x246c
10729 #define mmVPG4_VPG_GENERIC_STATUS_BASE_IDX                                                             2
10730 #define mmVPG4_VPG_MEM_PWR                                                                             0x246d
10731 #define mmVPG4_VPG_MEM_PWR_BASE_IDX                                                                    2
10732 #define mmVPG4_VPG_ISRC1_2_ACCESS_CTRL                                                                 0x246e
10733 #define mmVPG4_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX                                                        2
10734 #define mmVPG4_VPG_ISRC1_2_DATA                                                                        0x246f
10735 #define mmVPG4_VPG_ISRC1_2_DATA_BASE_IDX                                                               2
10736 #define mmVPG4_VPG_MPEG_INFO0                                                                          0x2470
10737 #define mmVPG4_VPG_MPEG_INFO0_BASE_IDX                                                                 2
10738 #define mmVPG4_VPG_MPEG_INFO1                                                                          0x2471
10739 #define mmVPG4_VPG_MPEG_INFO1_BASE_IDX                                                                 2
10740 
10741 
10742 // addressBlock: dce_dc_dio_dig4_afmt_afmt_dispdec
10743 #define mmAFMT4_AFMT_VBI_PACKET_CONTROL                                                                0x2474
10744 #define mmAFMT4_AFMT_VBI_PACKET_CONTROL_BASE_IDX                                                       2
10745 #define mmAFMT4_AFMT_AUDIO_PACKET_CONTROL2                                                             0x2475
10746 #define mmAFMT4_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX                                                    2
10747 #define mmAFMT4_AFMT_AUDIO_INFO0                                                                       0x2476
10748 #define mmAFMT4_AFMT_AUDIO_INFO0_BASE_IDX                                                              2
10749 #define mmAFMT4_AFMT_AUDIO_INFO1                                                                       0x2477
10750 #define mmAFMT4_AFMT_AUDIO_INFO1_BASE_IDX                                                              2
10751 #define mmAFMT4_AFMT_60958_0                                                                           0x2478
10752 #define mmAFMT4_AFMT_60958_0_BASE_IDX                                                                  2
10753 #define mmAFMT4_AFMT_60958_1                                                                           0x2479
10754 #define mmAFMT4_AFMT_60958_1_BASE_IDX                                                                  2
10755 #define mmAFMT4_AFMT_AUDIO_CRC_CONTROL                                                                 0x247a
10756 #define mmAFMT4_AFMT_AUDIO_CRC_CONTROL_BASE_IDX                                                        2
10757 #define mmAFMT4_AFMT_RAMP_CONTROL0                                                                     0x247b
10758 #define mmAFMT4_AFMT_RAMP_CONTROL0_BASE_IDX                                                            2
10759 #define mmAFMT4_AFMT_RAMP_CONTROL1                                                                     0x247c
10760 #define mmAFMT4_AFMT_RAMP_CONTROL1_BASE_IDX                                                            2
10761 #define mmAFMT4_AFMT_RAMP_CONTROL2                                                                     0x247d
10762 #define mmAFMT4_AFMT_RAMP_CONTROL2_BASE_IDX                                                            2
10763 #define mmAFMT4_AFMT_RAMP_CONTROL3                                                                     0x247e
10764 #define mmAFMT4_AFMT_RAMP_CONTROL3_BASE_IDX                                                            2
10765 #define mmAFMT4_AFMT_60958_2                                                                           0x247f
10766 #define mmAFMT4_AFMT_60958_2_BASE_IDX                                                                  2
10767 #define mmAFMT4_AFMT_AUDIO_CRC_RESULT                                                                  0x2480
10768 #define mmAFMT4_AFMT_AUDIO_CRC_RESULT_BASE_IDX                                                         2
10769 #define mmAFMT4_AFMT_STATUS                                                                            0x2481
10770 #define mmAFMT4_AFMT_STATUS_BASE_IDX                                                                   2
10771 #define mmAFMT4_AFMT_AUDIO_PACKET_CONTROL                                                              0x2482
10772 #define mmAFMT4_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX                                                     2
10773 #define mmAFMT4_AFMT_INFOFRAME_CONTROL0                                                                0x2483
10774 #define mmAFMT4_AFMT_INFOFRAME_CONTROL0_BASE_IDX                                                       2
10775 #define mmAFMT4_AFMT_INTERRUPT_STATUS                                                                  0x2484
10776 #define mmAFMT4_AFMT_INTERRUPT_STATUS_BASE_IDX                                                         2
10777 #define mmAFMT4_AFMT_AUDIO_SRC_CONTROL                                                                 0x2485
10778 #define mmAFMT4_AFMT_AUDIO_SRC_CONTROL_BASE_IDX                                                        2
10779 #define mmAFMT4_AFMT_MEM_PWR                                                                           0x2487
10780 #define mmAFMT4_AFMT_MEM_PWR_BASE_IDX                                                                  2
10781 
10782 
10783 // addressBlock: dce_dc_dio_dig4_dme_dme_dispdec
10784 // base address: 0x16524
10785 #define mmDME4_DME_CONTROL                                                                             0x2489
10786 #define mmDME4_DME_CONTROL_BASE_IDX                                                                    2
10787 #define mmDME4_DME_MEMORY_CONTROL                                                                      0x248a
10788 #define mmDME4_DME_MEMORY_CONTROL_BASE_IDX                                                             2
10789 
10790 
10791 // addressBlock: dce_dc_dio_dig4_dispdec
10792 // base address: 0x1000
10793 #define mmDIG4_DIG_FE_CNTL                                                                             0x248b
10794 #define mmDIG4_DIG_FE_CNTL_BASE_IDX                                                                    2
10795 #define mmDIG4_DIG_OUTPUT_CRC_CNTL                                                                     0x248c
10796 #define mmDIG4_DIG_OUTPUT_CRC_CNTL_BASE_IDX                                                            2
10797 #define mmDIG4_DIG_OUTPUT_CRC_RESULT                                                                   0x248d
10798 #define mmDIG4_DIG_OUTPUT_CRC_RESULT_BASE_IDX                                                          2
10799 #define mmDIG4_DIG_CLOCK_PATTERN                                                                       0x248e
10800 #define mmDIG4_DIG_CLOCK_PATTERN_BASE_IDX                                                              2
10801 #define mmDIG4_DIG_TEST_PATTERN                                                                        0x248f
10802 #define mmDIG4_DIG_TEST_PATTERN_BASE_IDX                                                               2
10803 #define mmDIG4_DIG_RANDOM_PATTERN_SEED                                                                 0x2490
10804 #define mmDIG4_DIG_RANDOM_PATTERN_SEED_BASE_IDX                                                        2
10805 #define mmDIG4_DIG_FIFO_STATUS                                                                         0x2491
10806 #define mmDIG4_DIG_FIFO_STATUS_BASE_IDX                                                                2
10807 #define mmDIG4_HDMI_METADATA_PACKET_CONTROL                                                            0x2492
10808 #define mmDIG4_HDMI_METADATA_PACKET_CONTROL_BASE_IDX                                                   2
10809 #define mmDIG4_HDMI_CONTROL                                                                            0x2493
10810 #define mmDIG4_HDMI_CONTROL_BASE_IDX                                                                   2
10811 #define mmDIG4_HDMI_STATUS                                                                             0x2494
10812 #define mmDIG4_HDMI_STATUS_BASE_IDX                                                                    2
10813 #define mmDIG4_HDMI_AUDIO_PACKET_CONTROL                                                               0x2495
10814 #define mmDIG4_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX                                                      2
10815 #define mmDIG4_HDMI_ACR_PACKET_CONTROL                                                                 0x2496
10816 #define mmDIG4_HDMI_ACR_PACKET_CONTROL_BASE_IDX                                                        2
10817 #define mmDIG4_HDMI_VBI_PACKET_CONTROL                                                                 0x2497
10818 #define mmDIG4_HDMI_VBI_PACKET_CONTROL_BASE_IDX                                                        2
10819 #define mmDIG4_HDMI_INFOFRAME_CONTROL0                                                                 0x2498
10820 #define mmDIG4_HDMI_INFOFRAME_CONTROL0_BASE_IDX                                                        2
10821 #define mmDIG4_HDMI_INFOFRAME_CONTROL1                                                                 0x2499
10822 #define mmDIG4_HDMI_INFOFRAME_CONTROL1_BASE_IDX                                                        2
10823 #define mmDIG4_HDMI_GENERIC_PACKET_CONTROL0                                                            0x249a
10824 #define mmDIG4_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX                                                   2
10825 #define mmDIG4_HDMI_GENERIC_PACKET_CONTROL6                                                            0x249b
10826 #define mmDIG4_HDMI_GENERIC_PACKET_CONTROL6_BASE_IDX                                                   2
10827 #define mmDIG4_HDMI_GENERIC_PACKET_CONTROL5                                                            0x249c
10828 #define mmDIG4_HDMI_GENERIC_PACKET_CONTROL5_BASE_IDX                                                   2
10829 #define mmDIG4_HDMI_GC                                                                                 0x249d
10830 #define mmDIG4_HDMI_GC_BASE_IDX                                                                        2
10831 #define mmDIG4_HDMI_GENERIC_PACKET_CONTROL1                                                            0x249e
10832 #define mmDIG4_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX                                                   2
10833 #define mmDIG4_HDMI_GENERIC_PACKET_CONTROL2                                                            0x249f
10834 #define mmDIG4_HDMI_GENERIC_PACKET_CONTROL2_BASE_IDX                                                   2
10835 #define mmDIG4_HDMI_GENERIC_PACKET_CONTROL3                                                            0x24a0
10836 #define mmDIG4_HDMI_GENERIC_PACKET_CONTROL3_BASE_IDX                                                   2
10837 #define mmDIG4_HDMI_GENERIC_PACKET_CONTROL4                                                            0x24a1
10838 #define mmDIG4_HDMI_GENERIC_PACKET_CONTROL4_BASE_IDX                                                   2
10839 #define mmDIG4_HDMI_GENERIC_PACKET_CONTROL7                                                            0x24a2
10840 #define mmDIG4_HDMI_GENERIC_PACKET_CONTROL7_BASE_IDX                                                   2
10841 #define mmDIG4_HDMI_GENERIC_PACKET_CONTROL8                                                            0x24a3
10842 #define mmDIG4_HDMI_GENERIC_PACKET_CONTROL8_BASE_IDX                                                   2
10843 #define mmDIG4_HDMI_GENERIC_PACKET_CONTROL9                                                            0x24a4
10844 #define mmDIG4_HDMI_GENERIC_PACKET_CONTROL9_BASE_IDX                                                   2
10845 #define mmDIG4_HDMI_GENERIC_PACKET_CONTROL10                                                           0x24a5
10846 #define mmDIG4_HDMI_GENERIC_PACKET_CONTROL10_BASE_IDX                                                  2
10847 #define mmDIG4_HDMI_DB_CONTROL                                                                         0x24a6
10848 #define mmDIG4_HDMI_DB_CONTROL_BASE_IDX                                                                2
10849 #define mmDIG4_HDMI_ACR_32_0                                                                           0x24a7
10850 #define mmDIG4_HDMI_ACR_32_0_BASE_IDX                                                                  2
10851 #define mmDIG4_HDMI_ACR_32_1                                                                           0x24a8
10852 #define mmDIG4_HDMI_ACR_32_1_BASE_IDX                                                                  2
10853 #define mmDIG4_HDMI_ACR_44_0                                                                           0x24a9
10854 #define mmDIG4_HDMI_ACR_44_0_BASE_IDX                                                                  2
10855 #define mmDIG4_HDMI_ACR_44_1                                                                           0x24aa
10856 #define mmDIG4_HDMI_ACR_44_1_BASE_IDX                                                                  2
10857 #define mmDIG4_HDMI_ACR_48_0                                                                           0x24ab
10858 #define mmDIG4_HDMI_ACR_48_0_BASE_IDX                                                                  2
10859 #define mmDIG4_HDMI_ACR_48_1                                                                           0x24ac
10860 #define mmDIG4_HDMI_ACR_48_1_BASE_IDX                                                                  2
10861 #define mmDIG4_HDMI_ACR_STATUS_0                                                                       0x24ad
10862 #define mmDIG4_HDMI_ACR_STATUS_0_BASE_IDX                                                              2
10863 #define mmDIG4_HDMI_ACR_STATUS_1                                                                       0x24ae
10864 #define mmDIG4_HDMI_ACR_STATUS_1_BASE_IDX                                                              2
10865 #define mmDIG4_AFMT_CNTL                                                                               0x24af
10866 #define mmDIG4_AFMT_CNTL_BASE_IDX                                                                      2
10867 #define mmDIG4_DIG_BE_CNTL                                                                             0x24b0
10868 #define mmDIG4_DIG_BE_CNTL_BASE_IDX                                                                    2
10869 #define mmDIG4_DIG_BE_EN_CNTL                                                                          0x24b1
10870 #define mmDIG4_DIG_BE_EN_CNTL_BASE_IDX                                                                 2
10871 #define mmDIG4_TMDS_CNTL                                                                               0x24d7
10872 #define mmDIG4_TMDS_CNTL_BASE_IDX                                                                      2
10873 #define mmDIG4_TMDS_CONTROL_CHAR                                                                       0x24d8
10874 #define mmDIG4_TMDS_CONTROL_CHAR_BASE_IDX                                                              2
10875 #define mmDIG4_TMDS_CONTROL0_FEEDBACK                                                                  0x24d9
10876 #define mmDIG4_TMDS_CONTROL0_FEEDBACK_BASE_IDX                                                         2
10877 #define mmDIG4_TMDS_STEREOSYNC_CTL_SEL                                                                 0x24da
10878 #define mmDIG4_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX                                                        2
10879 #define mmDIG4_TMDS_SYNC_CHAR_PATTERN_0_1                                                              0x24db
10880 #define mmDIG4_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX                                                     2
10881 #define mmDIG4_TMDS_SYNC_CHAR_PATTERN_2_3                                                              0x24dc
10882 #define mmDIG4_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX                                                     2
10883 #define mmDIG4_TMDS_CTL_BITS                                                                           0x24de
10884 #define mmDIG4_TMDS_CTL_BITS_BASE_IDX                                                                  2
10885 #define mmDIG4_TMDS_DCBALANCER_CONTROL                                                                 0x24df
10886 #define mmDIG4_TMDS_DCBALANCER_CONTROL_BASE_IDX                                                        2
10887 #define mmDIG4_TMDS_SYNC_DCBALANCE_CHAR                                                                0x24e0
10888 #define mmDIG4_TMDS_SYNC_DCBALANCE_CHAR_BASE_IDX                                                       2
10889 #define mmDIG4_TMDS_CTL0_1_GEN_CNTL                                                                    0x24e1
10890 #define mmDIG4_TMDS_CTL0_1_GEN_CNTL_BASE_IDX                                                           2
10891 #define mmDIG4_TMDS_CTL2_3_GEN_CNTL                                                                    0x24e2
10892 #define mmDIG4_TMDS_CTL2_3_GEN_CNTL_BASE_IDX                                                           2
10893 #define mmDIG4_DIG_VERSION                                                                             0x24e4
10894 #define mmDIG4_DIG_VERSION_BASE_IDX                                                                    2
10895 #define mmDIG4_DIG_LANE_ENABLE                                                                         0x24e5
10896 #define mmDIG4_DIG_LANE_ENABLE_BASE_IDX                                                                2
10897 #define mmDIG4_FORCE_DIG_DISABLE                                                                       0x24e6
10898 #define mmDIG4_FORCE_DIG_DISABLE_BASE_IDX                                                              2
10899 
10900 
10901 // addressBlock: dce_dc_dio_dp4_dispdec
10902 // base address: 0x1000
10903 #define mmDP4_DP_LINK_CNTL                                                                             0x2508
10904 #define mmDP4_DP_LINK_CNTL_BASE_IDX                                                                    2
10905 #define mmDP4_DP_PIXEL_FORMAT                                                                          0x2509
10906 #define mmDP4_DP_PIXEL_FORMAT_BASE_IDX                                                                 2
10907 #define mmDP4_DP_MSA_COLORIMETRY                                                                       0x250a
10908 #define mmDP4_DP_MSA_COLORIMETRY_BASE_IDX                                                              2
10909 #define mmDP4_DP_CONFIG                                                                                0x250b
10910 #define mmDP4_DP_CONFIG_BASE_IDX                                                                       2
10911 #define mmDP4_DP_VID_STREAM_CNTL                                                                       0x250c
10912 #define mmDP4_DP_VID_STREAM_CNTL_BASE_IDX                                                              2
10913 #define mmDP4_DP_STEER_FIFO                                                                            0x250d
10914 #define mmDP4_DP_STEER_FIFO_BASE_IDX                                                                   2
10915 #define mmDP4_DP_MSA_MISC                                                                              0x250e
10916 #define mmDP4_DP_MSA_MISC_BASE_IDX                                                                     2
10917 #define mmDP4_DP_DPHY_INTERNAL_CTRL                                                                    0x250f
10918 #define mmDP4_DP_DPHY_INTERNAL_CTRL_BASE_IDX                                                           2
10919 #define mmDP4_DP_VID_TIMING                                                                            0x2510
10920 #define mmDP4_DP_VID_TIMING_BASE_IDX                                                                   2
10921 #define mmDP4_DP_VID_N                                                                                 0x2511
10922 #define mmDP4_DP_VID_N_BASE_IDX                                                                        2
10923 #define mmDP4_DP_VID_M                                                                                 0x2512
10924 #define mmDP4_DP_VID_M_BASE_IDX                                                                        2
10925 #define mmDP4_DP_LINK_FRAMING_CNTL                                                                     0x2513
10926 #define mmDP4_DP_LINK_FRAMING_CNTL_BASE_IDX                                                            2
10927 #define mmDP4_DP_HBR2_EYE_PATTERN                                                                      0x2514
10928 #define mmDP4_DP_HBR2_EYE_PATTERN_BASE_IDX                                                             2
10929 #define mmDP4_DP_VID_MSA_VBID                                                                          0x2515
10930 #define mmDP4_DP_VID_MSA_VBID_BASE_IDX                                                                 2
10931 #define mmDP4_DP_VID_INTERRUPT_CNTL                                                                    0x2516
10932 #define mmDP4_DP_VID_INTERRUPT_CNTL_BASE_IDX                                                           2
10933 #define mmDP4_DP_DPHY_CNTL                                                                             0x2517
10934 #define mmDP4_DP_DPHY_CNTL_BASE_IDX                                                                    2
10935 #define mmDP4_DP_DPHY_TRAINING_PATTERN_SEL                                                             0x2518
10936 #define mmDP4_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX                                                    2
10937 #define mmDP4_DP_DPHY_SYM0                                                                             0x2519
10938 #define mmDP4_DP_DPHY_SYM0_BASE_IDX                                                                    2
10939 #define mmDP4_DP_DPHY_SYM1                                                                             0x251a
10940 #define mmDP4_DP_DPHY_SYM1_BASE_IDX                                                                    2
10941 #define mmDP4_DP_DPHY_SYM2                                                                             0x251b
10942 #define mmDP4_DP_DPHY_SYM2_BASE_IDX                                                                    2
10943 #define mmDP4_DP_DPHY_8B10B_CNTL                                                                       0x251c
10944 #define mmDP4_DP_DPHY_8B10B_CNTL_BASE_IDX                                                              2
10945 #define mmDP4_DP_DPHY_PRBS_CNTL                                                                        0x251d
10946 #define mmDP4_DP_DPHY_PRBS_CNTL_BASE_IDX                                                               2
10947 #define mmDP4_DP_DPHY_SCRAM_CNTL                                                                       0x251e
10948 #define mmDP4_DP_DPHY_SCRAM_CNTL_BASE_IDX                                                              2
10949 #define mmDP4_DP_DPHY_CRC_EN                                                                           0x251f
10950 #define mmDP4_DP_DPHY_CRC_EN_BASE_IDX                                                                  2
10951 #define mmDP4_DP_DPHY_CRC_CNTL                                                                         0x2520
10952 #define mmDP4_DP_DPHY_CRC_CNTL_BASE_IDX                                                                2
10953 #define mmDP4_DP_DPHY_CRC_RESULT                                                                       0x2521
10954 #define mmDP4_DP_DPHY_CRC_RESULT_BASE_IDX                                                              2
10955 #define mmDP4_DP_DPHY_CRC_MST_CNTL                                                                     0x2522
10956 #define mmDP4_DP_DPHY_CRC_MST_CNTL_BASE_IDX                                                            2
10957 #define mmDP4_DP_DPHY_CRC_MST_STATUS                                                                   0x2523
10958 #define mmDP4_DP_DPHY_CRC_MST_STATUS_BASE_IDX                                                          2
10959 #define mmDP4_DP_DPHY_FAST_TRAINING                                                                    0x2524
10960 #define mmDP4_DP_DPHY_FAST_TRAINING_BASE_IDX                                                           2
10961 #define mmDP4_DP_DPHY_FAST_TRAINING_STATUS                                                             0x2525
10962 #define mmDP4_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX                                                    2
10963 #define mmDP4_DP_SEC_CNTL                                                                              0x252b
10964 #define mmDP4_DP_SEC_CNTL_BASE_IDX                                                                     2
10965 #define mmDP4_DP_SEC_CNTL1                                                                             0x252c
10966 #define mmDP4_DP_SEC_CNTL1_BASE_IDX                                                                    2
10967 #define mmDP4_DP_SEC_FRAMING1                                                                          0x252d
10968 #define mmDP4_DP_SEC_FRAMING1_BASE_IDX                                                                 2
10969 #define mmDP4_DP_SEC_FRAMING2                                                                          0x252e
10970 #define mmDP4_DP_SEC_FRAMING2_BASE_IDX                                                                 2
10971 #define mmDP4_DP_SEC_FRAMING3                                                                          0x252f
10972 #define mmDP4_DP_SEC_FRAMING3_BASE_IDX                                                                 2
10973 #define mmDP4_DP_SEC_FRAMING4                                                                          0x2530
10974 #define mmDP4_DP_SEC_FRAMING4_BASE_IDX                                                                 2
10975 #define mmDP4_DP_SEC_AUD_N                                                                             0x2531
10976 #define mmDP4_DP_SEC_AUD_N_BASE_IDX                                                                    2
10977 #define mmDP4_DP_SEC_AUD_N_READBACK                                                                    0x2532
10978 #define mmDP4_DP_SEC_AUD_N_READBACK_BASE_IDX                                                           2
10979 #define mmDP4_DP_SEC_AUD_M                                                                             0x2533
10980 #define mmDP4_DP_SEC_AUD_M_BASE_IDX                                                                    2
10981 #define mmDP4_DP_SEC_AUD_M_READBACK                                                                    0x2534
10982 #define mmDP4_DP_SEC_AUD_M_READBACK_BASE_IDX                                                           2
10983 #define mmDP4_DP_SEC_TIMESTAMP                                                                         0x2535
10984 #define mmDP4_DP_SEC_TIMESTAMP_BASE_IDX                                                                2
10985 #define mmDP4_DP_SEC_PACKET_CNTL                                                                       0x2536
10986 #define mmDP4_DP_SEC_PACKET_CNTL_BASE_IDX                                                              2
10987 #define mmDP4_DP_MSE_RATE_CNTL                                                                         0x2537
10988 #define mmDP4_DP_MSE_RATE_CNTL_BASE_IDX                                                                2
10989 #define mmDP4_DP_MSE_RATE_UPDATE                                                                       0x2539
10990 #define mmDP4_DP_MSE_RATE_UPDATE_BASE_IDX                                                              2
10991 #define mmDP4_DP_MSE_SAT0                                                                              0x253a
10992 #define mmDP4_DP_MSE_SAT0_BASE_IDX                                                                     2
10993 #define mmDP4_DP_MSE_SAT1                                                                              0x253b
10994 #define mmDP4_DP_MSE_SAT1_BASE_IDX                                                                     2
10995 #define mmDP4_DP_MSE_SAT2                                                                              0x253c
10996 #define mmDP4_DP_MSE_SAT2_BASE_IDX                                                                     2
10997 #define mmDP4_DP_MSE_SAT_UPDATE                                                                        0x253d
10998 #define mmDP4_DP_MSE_SAT_UPDATE_BASE_IDX                                                               2
10999 #define mmDP4_DP_MSE_LINK_TIMING                                                                       0x253e
11000 #define mmDP4_DP_MSE_LINK_TIMING_BASE_IDX                                                              2
11001 #define mmDP4_DP_MSE_MISC_CNTL                                                                         0x253f
11002 #define mmDP4_DP_MSE_MISC_CNTL_BASE_IDX                                                                2
11003 #define mmDP4_DP_DPHY_BS_SR_SWAP_CNTL                                                                  0x2544
11004 #define mmDP4_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX                                                         2
11005 #define mmDP4_DP_DPHY_HBR2_PATTERN_CONTROL                                                             0x2545
11006 #define mmDP4_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX                                                    2
11007 #define mmDP4_DP_MSE_SAT0_STATUS                                                                       0x2547
11008 #define mmDP4_DP_MSE_SAT0_STATUS_BASE_IDX                                                              2
11009 #define mmDP4_DP_MSE_SAT1_STATUS                                                                       0x2548
11010 #define mmDP4_DP_MSE_SAT1_STATUS_BASE_IDX                                                              2
11011 #define mmDP4_DP_MSE_SAT2_STATUS                                                                       0x2549
11012 #define mmDP4_DP_MSE_SAT2_STATUS_BASE_IDX                                                              2
11013 #define mmDP4_DP_MSA_TIMING_PARAM1                                                                     0x254c
11014 #define mmDP4_DP_MSA_TIMING_PARAM1_BASE_IDX                                                            2
11015 #define mmDP4_DP_MSA_TIMING_PARAM2                                                                     0x254d
11016 #define mmDP4_DP_MSA_TIMING_PARAM2_BASE_IDX                                                            2
11017 #define mmDP4_DP_MSA_TIMING_PARAM3                                                                     0x254e
11018 #define mmDP4_DP_MSA_TIMING_PARAM3_BASE_IDX                                                            2
11019 #define mmDP4_DP_MSA_TIMING_PARAM4                                                                     0x254f
11020 #define mmDP4_DP_MSA_TIMING_PARAM4_BASE_IDX                                                            2
11021 #define mmDP4_DP_MSO_CNTL                                                                              0x2550
11022 #define mmDP4_DP_MSO_CNTL_BASE_IDX                                                                     2
11023 #define mmDP4_DP_MSO_CNTL1                                                                             0x2551
11024 #define mmDP4_DP_MSO_CNTL1_BASE_IDX                                                                    2
11025 #define mmDP4_DP_DSC_CNTL                                                                              0x2552
11026 #define mmDP4_DP_DSC_CNTL_BASE_IDX                                                                     2
11027 #define mmDP4_DP_SEC_CNTL2                                                                             0x2553
11028 #define mmDP4_DP_SEC_CNTL2_BASE_IDX                                                                    2
11029 #define mmDP4_DP_SEC_CNTL3                                                                             0x2554
11030 #define mmDP4_DP_SEC_CNTL3_BASE_IDX                                                                    2
11031 #define mmDP4_DP_SEC_CNTL4                                                                             0x2555
11032 #define mmDP4_DP_SEC_CNTL4_BASE_IDX                                                                    2
11033 #define mmDP4_DP_SEC_CNTL5                                                                             0x2556
11034 #define mmDP4_DP_SEC_CNTL5_BASE_IDX                                                                    2
11035 #define mmDP4_DP_SEC_CNTL6                                                                             0x2557
11036 #define mmDP4_DP_SEC_CNTL6_BASE_IDX                                                                    2
11037 #define mmDP4_DP_SEC_CNTL7                                                                             0x2558
11038 #define mmDP4_DP_SEC_CNTL7_BASE_IDX                                                                    2
11039 #define mmDP4_DP_DB_CNTL                                                                               0x2559
11040 #define mmDP4_DP_DB_CNTL_BASE_IDX                                                                      2
11041 #define mmDP4_DP_MSA_VBID_MISC                                                                         0x255a
11042 #define mmDP4_DP_MSA_VBID_MISC_BASE_IDX                                                                2
11043 #define mmDP4_DP_SEC_METADATA_TRANSMISSION                                                             0x255b
11044 #define mmDP4_DP_SEC_METADATA_TRANSMISSION_BASE_IDX                                                    2
11045 #define mmDP4_DP_DSC_BYTES_PER_PIXEL                                                                   0x255c
11046 #define mmDP4_DP_DSC_BYTES_PER_PIXEL_BASE_IDX                                                          2
11047 #define mmDP4_DP_ALPM_CNTL                                                                             0x255d
11048 #define mmDP4_DP_ALPM_CNTL_BASE_IDX                                                                    2
11049 #define mmDP4_DP_GSP8_CNTL                                                                             0x255e
11050 #define mmDP4_DP_GSP8_CNTL_BASE_IDX                                                                    2
11051 #define mmDP4_DP_GSP9_CNTL                                                                             0x255f
11052 #define mmDP4_DP_GSP9_CNTL_BASE_IDX                                                                    2
11053 #define mmDP4_DP_GSP10_CNTL                                                                            0x2560
11054 #define mmDP4_DP_GSP10_CNTL_BASE_IDX                                                                   2
11055 #define mmDP4_DP_GSP11_CNTL                                                                            0x2561
11056 #define mmDP4_DP_GSP11_CNTL_BASE_IDX                                                                   2
11057 #define mmDP4_DP_GSP_EN_DB_STATUS                                                                      0x2562
11058 #define mmDP4_DP_GSP_EN_DB_STATUS_BASE_IDX                                                             2
11059 
11060 
11061 // addressBlock: dce_dc_dio_dig5_vpg_vpg_dispdec
11062 // base address: 0x168a0
11063 #define mmVPG5_VPG_GENERIC_PACKET_ACCESS_CTRL                                                          0x2568
11064 #define mmVPG5_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX                                                 2
11065 #define mmVPG5_VPG_GENERIC_PACKET_DATA                                                                 0x2569
11066 #define mmVPG5_VPG_GENERIC_PACKET_DATA_BASE_IDX                                                        2
11067 #define mmVPG5_VPG_GSP_FRAME_UPDATE_CTRL                                                               0x256a
11068 #define mmVPG5_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX                                                      2
11069 #define mmVPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL                                                           0x256b
11070 #define mmVPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX                                                  2
11071 #define mmVPG5_VPG_GENERIC_STATUS                                                                      0x256c
11072 #define mmVPG5_VPG_GENERIC_STATUS_BASE_IDX                                                             2
11073 #define mmVPG5_VPG_MEM_PWR                                                                             0x256d
11074 #define mmVPG5_VPG_MEM_PWR_BASE_IDX                                                                    2
11075 #define mmVPG5_VPG_ISRC1_2_ACCESS_CTRL                                                                 0x256e
11076 #define mmVPG5_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX                                                        2
11077 #define mmVPG5_VPG_ISRC1_2_DATA                                                                        0x256f
11078 #define mmVPG5_VPG_ISRC1_2_DATA_BASE_IDX                                                               2
11079 #define mmVPG5_VPG_MPEG_INFO0                                                                          0x2570
11080 #define mmVPG5_VPG_MPEG_INFO0_BASE_IDX                                                                 2
11081 #define mmVPG5_VPG_MPEG_INFO1                                                                          0x2571
11082 #define mmVPG5_VPG_MPEG_INFO1_BASE_IDX                                                                 2
11083 
11084 
11085 // addressBlock: dce_dc_dio_dig5_afmt_afmt_dispdec
11086 // base address: 0x168cc
11087 #define mmAFMT5_AFMT_VBI_PACKET_CONTROL                                                                0x2574
11088 #define mmAFMT5_AFMT_VBI_PACKET_CONTROL_BASE_IDX                                                       2
11089 #define mmAFMT5_AFMT_AUDIO_PACKET_CONTROL2                                                             0x2575
11090 #define mmAFMT5_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX                                                    2
11091 #define mmAFMT5_AFMT_AUDIO_INFO0                                                                       0x2576
11092 #define mmAFMT5_AFMT_AUDIO_INFO0_BASE_IDX                                                              2
11093 #define mmAFMT5_AFMT_AUDIO_INFO1                                                                       0x2577
11094 #define mmAFMT5_AFMT_AUDIO_INFO1_BASE_IDX                                                              2
11095 #define mmAFMT5_AFMT_60958_0                                                                           0x2578
11096 #define mmAFMT5_AFMT_60958_0_BASE_IDX                                                                  2
11097 #define mmAFMT5_AFMT_60958_1                                                                           0x2579
11098 #define mmAFMT5_AFMT_60958_1_BASE_IDX                                                                  2
11099 #define mmAFMT5_AFMT_AUDIO_CRC_CONTROL                                                                 0x257a
11100 #define mmAFMT5_AFMT_AUDIO_CRC_CONTROL_BASE_IDX                                                        2
11101 #define mmAFMT5_AFMT_RAMP_CONTROL0                                                                     0x257b
11102 #define mmAFMT5_AFMT_RAMP_CONTROL0_BASE_IDX                                                            2
11103 #define mmAFMT5_AFMT_RAMP_CONTROL1                                                                     0x257c
11104 #define mmAFMT5_AFMT_RAMP_CONTROL1_BASE_IDX                                                            2
11105 #define mmAFMT5_AFMT_RAMP_CONTROL2                                                                     0x257d
11106 #define mmAFMT5_AFMT_RAMP_CONTROL2_BASE_IDX                                                            2
11107 #define mmAFMT5_AFMT_RAMP_CONTROL3                                                                     0x257e
11108 #define mmAFMT5_AFMT_RAMP_CONTROL3_BASE_IDX                                                            2
11109 #define mmAFMT5_AFMT_60958_2                                                                           0x257f
11110 #define mmAFMT5_AFMT_60958_2_BASE_IDX                                                                  2
11111 #define mmAFMT5_AFMT_AUDIO_CRC_RESULT                                                                  0x2580
11112 #define mmAFMT5_AFMT_AUDIO_CRC_RESULT_BASE_IDX                                                         2
11113 #define mmAFMT5_AFMT_STATUS                                                                            0x2581
11114 #define mmAFMT5_AFMT_STATUS_BASE_IDX                                                                   2
11115 #define mmAFMT5_AFMT_AUDIO_PACKET_CONTROL                                                              0x2582
11116 #define mmAFMT5_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX                                                     2
11117 #define mmAFMT5_AFMT_INFOFRAME_CONTROL0                                                                0x2583
11118 #define mmAFMT5_AFMT_INFOFRAME_CONTROL0_BASE_IDX                                                       2
11119 #define mmAFMT5_AFMT_INTERRUPT_STATUS                                                                  0x2584
11120 #define mmAFMT5_AFMT_INTERRUPT_STATUS_BASE_IDX                                                         2
11121 #define mmAFMT5_AFMT_AUDIO_SRC_CONTROL                                                                 0x2585
11122 #define mmAFMT5_AFMT_AUDIO_SRC_CONTROL_BASE_IDX                                                        2
11123 #define mmAFMT5_AFMT_MEM_PWR                                                                           0x2587
11124 #define mmAFMT5_AFMT_MEM_PWR_BASE_IDX                                                                  2
11125 
11126 
11127 // addressBlock: dce_dc_dio_dig5_dispdec
11128 // base address: 0x1400
11129 #define mmDIG5_DIG_FE_CNTL                                                                             0x258b
11130 #define mmDIG5_DIG_FE_CNTL_BASE_IDX                                                                    2
11131 #define mmDIG5_DIG_OUTPUT_CRC_CNTL                                                                     0x258c
11132 #define mmDIG5_DIG_OUTPUT_CRC_CNTL_BASE_IDX                                                            2
11133 #define mmDIG5_DIG_OUTPUT_CRC_RESULT                                                                   0x258d
11134 #define mmDIG5_DIG_OUTPUT_CRC_RESULT_BASE_IDX                                                          2
11135 #define mmDIG5_DIG_CLOCK_PATTERN                                                                       0x258e
11136 #define mmDIG5_DIG_CLOCK_PATTERN_BASE_IDX                                                              2
11137 #define mmDIG5_DIG_TEST_PATTERN                                                                        0x258f
11138 #define mmDIG5_DIG_TEST_PATTERN_BASE_IDX                                                               2
11139 #define mmDIG5_DIG_RANDOM_PATTERN_SEED                                                                 0x2590
11140 #define mmDIG5_DIG_RANDOM_PATTERN_SEED_BASE_IDX                                                        2
11141 #define mmDIG5_DIG_FIFO_STATUS                                                                         0x2591
11142 #define mmDIG5_DIG_FIFO_STATUS_BASE_IDX                                                                2
11143 #define mmDIG5_HDMI_METADATA_PACKET_CONTROL                                                            0x2592
11144 #define mmDIG5_HDMI_METADATA_PACKET_CONTROL_BASE_IDX                                                   2
11145 #define mmDIG5_HDMI_CONTROL                                                                            0x2593
11146 #define mmDIG5_HDMI_CONTROL_BASE_IDX                                                                   2
11147 #define mmDIG5_HDMI_STATUS                                                                             0x2594
11148 #define mmDIG5_HDMI_STATUS_BASE_IDX                                                                    2
11149 #define mmDIG5_HDMI_AUDIO_PACKET_CONTROL                                                               0x2595
11150 #define mmDIG5_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX                                                      2
11151 #define mmDIG5_HDMI_ACR_PACKET_CONTROL                                                                 0x2596
11152 #define mmDIG5_HDMI_ACR_PACKET_CONTROL_BASE_IDX                                                        2
11153 #define mmDIG5_HDMI_VBI_PACKET_CONTROL                                                                 0x2597
11154 #define mmDIG5_HDMI_VBI_PACKET_CONTROL_BASE_IDX                                                        2
11155 #define mmDIG5_HDMI_INFOFRAME_CONTROL0                                                                 0x2598
11156 #define mmDIG5_HDMI_INFOFRAME_CONTROL0_BASE_IDX                                                        2
11157 #define mmDIG5_HDMI_INFOFRAME_CONTROL1                                                                 0x2599
11158 #define mmDIG5_HDMI_INFOFRAME_CONTROL1_BASE_IDX                                                        2
11159 #define mmDIG5_HDMI_GENERIC_PACKET_CONTROL0                                                            0x259a
11160 #define mmDIG5_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX                                                   2
11161 #define mmDIG5_HDMI_GENERIC_PACKET_CONTROL6                                                            0x259b
11162 #define mmDIG5_HDMI_GENERIC_PACKET_CONTROL6_BASE_IDX                                                   2
11163 #define mmDIG5_HDMI_GENERIC_PACKET_CONTROL5                                                            0x259c
11164 #define mmDIG5_HDMI_GENERIC_PACKET_CONTROL5_BASE_IDX                                                   2
11165 #define mmDIG5_HDMI_GC                                                                                 0x259d
11166 #define mmDIG5_HDMI_GC_BASE_IDX                                                                        2
11167 #define mmDIG5_HDMI_GENERIC_PACKET_CONTROL1                                                            0x259e
11168 #define mmDIG5_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX                                                   2
11169 #define mmDIG5_HDMI_GENERIC_PACKET_CONTROL2                                                            0x259f
11170 #define mmDIG5_HDMI_GENERIC_PACKET_CONTROL2_BASE_IDX                                                   2
11171 #define mmDIG5_HDMI_GENERIC_PACKET_CONTROL3                                                            0x25a0
11172 #define mmDIG5_HDMI_GENERIC_PACKET_CONTROL3_BASE_IDX                                                   2
11173 #define mmDIG5_HDMI_GENERIC_PACKET_CONTROL4                                                            0x25a1
11174 #define mmDIG5_HDMI_GENERIC_PACKET_CONTROL4_BASE_IDX                                                   2
11175 #define mmDIG5_HDMI_GENERIC_PACKET_CONTROL7                                                            0x25a2
11176 #define mmDIG5_HDMI_GENERIC_PACKET_CONTROL7_BASE_IDX                                                   2
11177 #define mmDIG5_HDMI_GENERIC_PACKET_CONTROL8                                                            0x25a3
11178 #define mmDIG5_HDMI_GENERIC_PACKET_CONTROL8_BASE_IDX                                                   2
11179 #define mmDIG5_HDMI_GENERIC_PACKET_CONTROL9                                                            0x25a4
11180 #define mmDIG5_HDMI_GENERIC_PACKET_CONTROL9_BASE_IDX                                                   2
11181 #define mmDIG5_HDMI_GENERIC_PACKET_CONTROL10                                                           0x25a5
11182 #define mmDIG5_HDMI_GENERIC_PACKET_CONTROL10_BASE_IDX                                                  2
11183 #define mmDIG5_HDMI_DB_CONTROL                                                                         0x25a6
11184 #define mmDIG5_HDMI_DB_CONTROL_BASE_IDX                                                                2
11185 #define mmDIG5_HDMI_ACR_32_0                                                                           0x25a7
11186 #define mmDIG5_HDMI_ACR_32_0_BASE_IDX                                                                  2
11187 #define mmDIG5_HDMI_ACR_32_1                                                                           0x25a8
11188 #define mmDIG5_HDMI_ACR_32_1_BASE_IDX                                                                  2
11189 #define mmDIG5_HDMI_ACR_44_0                                                                           0x25a9
11190 #define mmDIG5_HDMI_ACR_44_0_BASE_IDX                                                                  2
11191 #define mmDIG5_HDMI_ACR_44_1                                                                           0x25aa
11192 #define mmDIG5_HDMI_ACR_44_1_BASE_IDX                                                                  2
11193 #define mmDIG5_HDMI_ACR_48_0                                                                           0x25ab
11194 #define mmDIG5_HDMI_ACR_48_0_BASE_IDX                                                                  2
11195 #define mmDIG5_HDMI_ACR_48_1                                                                           0x25ac
11196 #define mmDIG5_HDMI_ACR_48_1_BASE_IDX                                                                  2
11197 #define mmDIG5_HDMI_ACR_STATUS_0                                                                       0x25ad
11198 #define mmDIG5_HDMI_ACR_STATUS_0_BASE_IDX                                                              2
11199 #define mmDIG5_HDMI_ACR_STATUS_1                                                                       0x25ae
11200 #define mmDIG5_HDMI_ACR_STATUS_1_BASE_IDX                                                              2
11201 #define mmDIG5_AFMT_CNTL                                                                               0x25af
11202 #define mmDIG5_AFMT_CNTL_BASE_IDX                                                                      2
11203 #define mmDIG5_DIG_BE_CNTL                                                                             0x25b0
11204 #define mmDIG5_DIG_BE_CNTL_BASE_IDX                                                                    2
11205 #define mmDIG5_DIG_BE_EN_CNTL                                                                          0x25b1
11206 #define mmDIG5_DIG_BE_EN_CNTL_BASE_IDX                                                                 2
11207 
11208 #define mmDIG5_TMDS_CNTL                                                                               0x25d7
11209 #define mmDIG5_TMDS_CNTL_BASE_IDX                                                                      2
11210 #define mmDIG5_TMDS_CONTROL_CHAR                                                                       0x25d8
11211 #define mmDIG5_TMDS_CONTROL_CHAR_BASE_IDX                                                              2
11212 #define mmDIG5_TMDS_CONTROL0_FEEDBACK                                                                  0x25d9
11213 #define mmDIG5_TMDS_CONTROL0_FEEDBACK_BASE_IDX                                                         2
11214 #define mmDIG5_TMDS_STEREOSYNC_CTL_SEL                                                                 0x25da
11215 #define mmDIG5_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX                                                        2
11216 #define mmDIG5_TMDS_SYNC_CHAR_PATTERN_0_1                                                              0x25db
11217 #define mmDIG5_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX                                                     2
11218 #define mmDIG5_TMDS_SYNC_CHAR_PATTERN_2_3                                                              0x25dc
11219 #define mmDIG5_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX                                                     2
11220 #define mmDIG5_TMDS_CTL_BITS                                                                           0x25de
11221 #define mmDIG5_TMDS_CTL_BITS_BASE_IDX                                                                  2
11222 #define mmDIG5_TMDS_DCBALANCER_CONTROL                                                                 0x25df
11223 #define mmDIG5_TMDS_DCBALANCER_CONTROL_BASE_IDX                                                        2
11224 #define mmDIG5_TMDS_SYNC_DCBALANCE_CHAR                                                                0x25e0
11225 #define mmDIG5_TMDS_SYNC_DCBALANCE_CHAR_BASE_IDX                                                       2
11226 #define mmDIG5_TMDS_CTL0_1_GEN_CNTL                                                                    0x25e1
11227 #define mmDIG5_TMDS_CTL0_1_GEN_CNTL_BASE_IDX                                                           2
11228 #define mmDIG5_TMDS_CTL2_3_GEN_CNTL                                                                    0x25e2
11229 #define mmDIG5_TMDS_CTL2_3_GEN_CNTL_BASE_IDX                                                           2
11230 #define mmDIG5_DIG_VERSION                                                                             0x25e4
11231 #define mmDIG5_DIG_VERSION_BASE_IDX                                                                    2
11232 #define mmDIG5_DIG_LANE_ENABLE                                                                         0x25e5
11233 #define mmDIG5_DIG_LANE_ENABLE_BASE_IDX                                                                2
11234 #define mmDIG5_FORCE_DIG_DISABLE                                                                       0x25e6
11235 #define mmDIG5_FORCE_DIG_DISABLE_BASE_IDX                                                              2
11236 
11237 // addressBlock: dce_dc_dio_dp5_dispdec
11238 // base address: 0x1400
11239 #define mmDP5_DP_LINK_CNTL                                                                             0x2608
11240 #define mmDP5_DP_LINK_CNTL_BASE_IDX                                                                    2
11241 #define mmDP5_DP_PIXEL_FORMAT                                                                          0x2609
11242 #define mmDP5_DP_PIXEL_FORMAT_BASE_IDX                                                                 2
11243 #define mmDP5_DP_MSA_COLORIMETRY                                                                       0x260a
11244 #define mmDP5_DP_MSA_COLORIMETRY_BASE_IDX                                                              2
11245 #define mmDP5_DP_CONFIG                                                                                0x260b
11246 #define mmDP5_DP_CONFIG_BASE_IDX                                                                       2
11247 #define mmDP5_DP_VID_STREAM_CNTL                                                                       0x260c
11248 #define mmDP5_DP_VID_STREAM_CNTL_BASE_IDX                                                              2
11249 #define mmDP5_DP_STEER_FIFO                                                                            0x260d
11250 #define mmDP5_DP_STEER_FIFO_BASE_IDX                                                                   2
11251 #define mmDP5_DP_MSA_MISC                                                                              0x260e
11252 #define mmDP5_DP_MSA_MISC_BASE_IDX                                                                     2
11253 #define mmDP5_DP_DPHY_INTERNAL_CTRL                                                                    0x260f
11254 #define mmDP5_DP_DPHY_INTERNAL_CTRL_BASE_IDX                                                           2
11255 #define mmDP5_DP_VID_TIMING                                                                            0x2610
11256 #define mmDP5_DP_VID_TIMING_BASE_IDX                                                                   2
11257 #define mmDP5_DP_VID_N                                                                                 0x2611
11258 #define mmDP5_DP_VID_N_BASE_IDX                                                                        2
11259 #define mmDP5_DP_VID_M                                                                                 0x2612
11260 #define mmDP5_DP_VID_M_BASE_IDX                                                                        2
11261 #define mmDP5_DP_LINK_FRAMING_CNTL                                                                     0x2613
11262 #define mmDP5_DP_LINK_FRAMING_CNTL_BASE_IDX                                                            2
11263 #define mmDP5_DP_HBR2_EYE_PATTERN                                                                      0x2614
11264 #define mmDP5_DP_HBR2_EYE_PATTERN_BASE_IDX                                                             2
11265 #define mmDP5_DP_VID_MSA_VBID                                                                          0x2615
11266 #define mmDP5_DP_VID_MSA_VBID_BASE_IDX                                                                 2
11267 #define mmDP5_DP_VID_INTERRUPT_CNTL                                                                    0x2616
11268 #define mmDP5_DP_VID_INTERRUPT_CNTL_BASE_IDX                                                           2
11269 #define mmDP5_DP_DPHY_CNTL                                                                             0x2617
11270 #define mmDP5_DP_DPHY_CNTL_BASE_IDX                                                                    2
11271 #define mmDP5_DP_DPHY_TRAINING_PATTERN_SEL                                                             0x2618
11272 #define mmDP5_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX                                                    2
11273 #define mmDP5_DP_DPHY_SYM0                                                                             0x2619
11274 #define mmDP5_DP_DPHY_SYM0_BASE_IDX                                                                    2
11275 #define mmDP5_DP_DPHY_SYM1                                                                             0x261a
11276 #define mmDP5_DP_DPHY_SYM1_BASE_IDX                                                                    2
11277 #define mmDP5_DP_DPHY_SYM2                                                                             0x261b
11278 #define mmDP5_DP_DPHY_SYM2_BASE_IDX                                                                    2
11279 #define mmDP5_DP_DPHY_8B10B_CNTL                                                                       0x261c
11280 #define mmDP5_DP_DPHY_8B10B_CNTL_BASE_IDX                                                              2
11281 #define mmDP5_DP_DPHY_PRBS_CNTL                                                                        0x261d
11282 #define mmDP5_DP_DPHY_PRBS_CNTL_BASE_IDX                                                               2
11283 #define mmDP5_DP_DPHY_SCRAM_CNTL                                                                       0x261e
11284 #define mmDP5_DP_DPHY_SCRAM_CNTL_BASE_IDX                                                              2
11285 #define mmDP5_DP_DPHY_CRC_EN                                                                           0x261f
11286 #define mmDP5_DP_DPHY_CRC_EN_BASE_IDX                                                                  2
11287 #define mmDP5_DP_DPHY_CRC_CNTL                                                                         0x2620
11288 #define mmDP5_DP_DPHY_CRC_CNTL_BASE_IDX                                                                2
11289 #define mmDP5_DP_DPHY_CRC_RESULT                                                                       0x2621
11290 #define mmDP5_DP_DPHY_CRC_RESULT_BASE_IDX                                                              2
11291 #define mmDP5_DP_DPHY_CRC_MST_CNTL                                                                     0x2622
11292 #define mmDP5_DP_DPHY_CRC_MST_CNTL_BASE_IDX                                                            2
11293 #define mmDP5_DP_DPHY_CRC_MST_STATUS                                                                   0x2623
11294 #define mmDP5_DP_DPHY_CRC_MST_STATUS_BASE_IDX                                                          2
11295 #define mmDP5_DP_DPHY_FAST_TRAINING                                                                    0x2624
11296 #define mmDP5_DP_DPHY_FAST_TRAINING_BASE_IDX                                                           2
11297 #define mmDP5_DP_DPHY_FAST_TRAINING_STATUS                                                             0x2625
11298 #define mmDP5_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX                                                    2
11299 #define mmDP5_DP_SEC_CNTL                                                                              0x262b
11300 #define mmDP5_DP_SEC_CNTL_BASE_IDX                                                                     2
11301 #define mmDP5_DP_SEC_CNTL1                                                                             0x262c
11302 #define mmDP5_DP_SEC_CNTL1_BASE_IDX                                                                    2
11303 #define mmDP5_DP_SEC_FRAMING1                                                                          0x262d
11304 #define mmDP5_DP_SEC_FRAMING1_BASE_IDX                                                                 2
11305 #define mmDP5_DP_SEC_FRAMING2                                                                          0x262e
11306 #define mmDP5_DP_SEC_FRAMING2_BASE_IDX                                                                 2
11307 #define mmDP5_DP_SEC_FRAMING3                                                                          0x262f
11308 #define mmDP5_DP_SEC_FRAMING3_BASE_IDX                                                                 2
11309 #define mmDP5_DP_SEC_FRAMING4                                                                          0x2630
11310 #define mmDP5_DP_SEC_FRAMING4_BASE_IDX                                                                 2
11311 #define mmDP5_DP_SEC_AUD_N                                                                             0x2631
11312 #define mmDP5_DP_SEC_AUD_N_BASE_IDX                                                                    2
11313 #define mmDP5_DP_SEC_AUD_N_READBACK                                                                    0x2632
11314 #define mmDP5_DP_SEC_AUD_N_READBACK_BASE_IDX                                                           2
11315 #define mmDP5_DP_SEC_AUD_M                                                                             0x2633
11316 #define mmDP5_DP_SEC_AUD_M_BASE_IDX                                                                    2
11317 #define mmDP5_DP_SEC_AUD_M_READBACK                                                                    0x2634
11318 #define mmDP5_DP_SEC_AUD_M_READBACK_BASE_IDX                                                           2
11319 #define mmDP5_DP_SEC_TIMESTAMP                                                                         0x2635
11320 #define mmDP5_DP_SEC_TIMESTAMP_BASE_IDX                                                                2
11321 #define mmDP5_DP_SEC_PACKET_CNTL                                                                       0x2636
11322 #define mmDP5_DP_SEC_PACKET_CNTL_BASE_IDX                                                              2
11323 #define mmDP5_DP_MSE_RATE_CNTL                                                                         0x2637
11324 #define mmDP5_DP_MSE_RATE_CNTL_BASE_IDX                                                                2
11325 #define mmDP5_DP_MSE_RATE_UPDATE                                                                       0x2639
11326 #define mmDP5_DP_MSE_RATE_UPDATE_BASE_IDX                                                              2
11327 #define mmDP5_DP_MSE_SAT0                                                                              0x263a
11328 #define mmDP5_DP_MSE_SAT0_BASE_IDX                                                                     2
11329 #define mmDP5_DP_MSE_SAT1                                                                              0x263b
11330 #define mmDP5_DP_MSE_SAT1_BASE_IDX                                                                     2
11331 #define mmDP5_DP_MSE_SAT2                                                                              0x263c
11332 #define mmDP5_DP_MSE_SAT2_BASE_IDX                                                                     2
11333 #define mmDP5_DP_MSE_SAT_UPDATE                                                                        0x263d
11334 #define mmDP5_DP_MSE_SAT_UPDATE_BASE_IDX                                                               2
11335 #define mmDP5_DP_MSE_LINK_TIMING                                                                       0x263e
11336 #define mmDP5_DP_MSE_LINK_TIMING_BASE_IDX                                                              2
11337 #define mmDP5_DP_MSE_MISC_CNTL                                                                         0x263f
11338 #define mmDP5_DP_MSE_MISC_CNTL_BASE_IDX                                                                2
11339 #define mmDP5_DP_DPHY_BS_SR_SWAP_CNTL                                                                  0x2644
11340 #define mmDP5_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX                                                         2
11341 #define mmDP5_DP_DPHY_HBR2_PATTERN_CONTROL                                                             0x2645
11342 #define mmDP5_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX                                                    2
11343 #define mmDP5_DP_MSE_SAT0_STATUS                                                                       0x2647
11344 #define mmDP5_DP_MSE_SAT0_STATUS_BASE_IDX                                                              2
11345 #define mmDP5_DP_MSE_SAT1_STATUS                                                                       0x2648
11346 #define mmDP5_DP_MSE_SAT1_STATUS_BASE_IDX                                                              2
11347 #define mmDP5_DP_MSE_SAT2_STATUS                                                                       0x2649
11348 #define mmDP5_DP_MSE_SAT2_STATUS_BASE_IDX                                                              2
11349 #define mmDP5_DP_MSA_TIMING_PARAM1                                                                     0x264c
11350 #define mmDP5_DP_MSA_TIMING_PARAM1_BASE_IDX                                                            2
11351 #define mmDP5_DP_MSA_TIMING_PARAM2                                                                     0x264d
11352 #define mmDP5_DP_MSA_TIMING_PARAM2_BASE_IDX                                                            2
11353 #define mmDP5_DP_MSA_TIMING_PARAM3                                                                     0x264e
11354 #define mmDP5_DP_MSA_TIMING_PARAM3_BASE_IDX                                                            2
11355 #define mmDP5_DP_MSA_TIMING_PARAM4                                                                     0x264f
11356 #define mmDP5_DP_MSA_TIMING_PARAM4_BASE_IDX                                                            2
11357 #define mmDP5_DP_MSO_CNTL                                                                              0x2650
11358 #define mmDP5_DP_MSO_CNTL_BASE_IDX                                                                     2
11359 #define mmDP5_DP_MSO_CNTL1                                                                             0x2651
11360 #define mmDP5_DP_MSO_CNTL1_BASE_IDX                                                                    2
11361 #define mmDP5_DP_DSC_CNTL                                                                              0x2652
11362 #define mmDP5_DP_DSC_CNTL_BASE_IDX                                                                     2
11363 #define mmDP5_DP_SEC_CNTL2                                                                             0x2653
11364 #define mmDP5_DP_SEC_CNTL2_BASE_IDX                                                                    2
11365 #define mmDP5_DP_SEC_CNTL3                                                                             0x2654
11366 #define mmDP5_DP_SEC_CNTL3_BASE_IDX                                                                    2
11367 #define mmDP5_DP_SEC_CNTL4                                                                             0x2655
11368 #define mmDP5_DP_SEC_CNTL4_BASE_IDX                                                                    2
11369 #define mmDP5_DP_SEC_CNTL5                                                                             0x2656
11370 #define mmDP5_DP_SEC_CNTL5_BASE_IDX                                                                    2
11371 #define mmDP5_DP_SEC_CNTL6                                                                             0x2657
11372 #define mmDP5_DP_SEC_CNTL6_BASE_IDX                                                                    2
11373 #define mmDP5_DP_SEC_CNTL7                                                                             0x2658
11374 #define mmDP5_DP_SEC_CNTL7_BASE_IDX                                                                    2
11375 #define mmDP5_DP_DB_CNTL                                                                               0x2659
11376 #define mmDP5_DP_DB_CNTL_BASE_IDX                                                                      2
11377 #define mmDP5_DP_MSA_VBID_MISC                                                                         0x265a
11378 #define mmDP5_DP_MSA_VBID_MISC_BASE_IDX                                                                2
11379 #define mmDP5_DP_SEC_METADATA_TRANSMISSION                                                             0x265b
11380 #define mmDP5_DP_SEC_METADATA_TRANSMISSION_BASE_IDX                                                    2
11381 #define mmDP5_DP_DSC_BYTES_PER_PIXEL                                                                   0x265c
11382 #define mmDP5_DP_DSC_BYTES_PER_PIXEL_BASE_IDX                                                          2
11383 #define mmDP5_DP_ALPM_CNTL                                                                             0x265d
11384 #define mmDP5_DP_ALPM_CNTL_BASE_IDX                                                                    2
11385 #define mmDP5_DP_GSP8_CNTL                                                                             0x265e
11386 #define mmDP5_DP_GSP8_CNTL_BASE_IDX                                                                    2
11387 #define mmDP5_DP_GSP9_CNTL                                                                             0x265f
11388 #define mmDP5_DP_GSP9_CNTL_BASE_IDX                                                                    2
11389 #define mmDP5_DP_GSP10_CNTL                                                                            0x2660
11390 #define mmDP5_DP_GSP10_CNTL_BASE_IDX                                                                   2
11391 #define mmDP5_DP_GSP11_CNTL                                                                            0x2661
11392 #define mmDP5_DP_GSP11_CNTL_BASE_IDX                                                                   2
11393 #define mmDP5_DP_GSP_EN_DB_STATUS                                                                      0x2662
11394 #define mmDP5_DP_GSP_EN_DB_STATUS_BASE_IDX                                                             2
11395 
11396 
11397 // addressBlock: dce_dc_dcio_dcio_dispdec
11398 // base address: 0x0
11399 #define mmDC_GENERICA                                                                                  0x2868
11400 #define mmDC_GENERICA_BASE_IDX                                                                         2
11401 #define mmDC_GENERICB                                                                                  0x2869
11402 #define mmDC_GENERICB_BASE_IDX                                                                         2
11403 #define mmDCIO_CLOCK_CNTL                                                                              0x286a
11404 #define mmDCIO_CLOCK_CNTL_BASE_IDX                                                                     2
11405 #define mmDC_REF_CLK_CNTL                                                                              0x286b
11406 #define mmDC_REF_CLK_CNTL_BASE_IDX                                                                     2
11407 #define mmUNIPHYA_LINK_CNTL                                                                            0x286d
11408 #define mmUNIPHYA_LINK_CNTL_BASE_IDX                                                                   2
11409 #define mmUNIPHYA_CHANNEL_XBAR_CNTL                                                                    0x286e
11410 #define mmUNIPHYA_CHANNEL_XBAR_CNTL_BASE_IDX                                                           2
11411 #define mmUNIPHYB_LINK_CNTL                                                                            0x286f
11412 #define mmUNIPHYB_LINK_CNTL_BASE_IDX                                                                   2
11413 #define mmUNIPHYB_CHANNEL_XBAR_CNTL                                                                    0x2870
11414 #define mmUNIPHYB_CHANNEL_XBAR_CNTL_BASE_IDX                                                           2
11415 #define mmUNIPHYC_LINK_CNTL                                                                            0x2871
11416 #define mmUNIPHYC_LINK_CNTL_BASE_IDX                                                                   2
11417 #define mmUNIPHYC_CHANNEL_XBAR_CNTL                                                                    0x2872
11418 #define mmUNIPHYC_CHANNEL_XBAR_CNTL_BASE_IDX                                                           2
11419 #define mmUNIPHYD_LINK_CNTL                                                                            0x2873
11420 #define mmUNIPHYD_LINK_CNTL_BASE_IDX                                                                   2
11421 #define mmUNIPHYD_CHANNEL_XBAR_CNTL                                                                    0x2874
11422 #define mmUNIPHYD_CHANNEL_XBAR_CNTL_BASE_IDX                                                           2
11423 #define mmUNIPHYE_LINK_CNTL                                                                            0x2875
11424 #define mmUNIPHYE_LINK_CNTL_BASE_IDX                                                                   2
11425 #define mmUNIPHYE_CHANNEL_XBAR_CNTL                                                                    0x2876
11426 #define mmUNIPHYE_CHANNEL_XBAR_CNTL_BASE_IDX                                                           2
11427 #define mmDCIO_WRCMD_DELAY                                                                             0x287e
11428 #define mmDCIO_WRCMD_DELAY_BASE_IDX                                                                    2
11429 #define mmDC_PINSTRAPS                                                                                 0x2880
11430 #define mmDC_PINSTRAPS_BASE_IDX                                                                        2
11431 #define mmLVTMA_PWRSEQ_CNTL                                                                            0x2883
11432 #define mmLVTMA_PWRSEQ_CNTL_BASE_IDX                                                                   2
11433 #define mmLVTMA_PWRSEQ_STATE                                                                           0x2884
11434 #define mmLVTMA_PWRSEQ_STATE_BASE_IDX                                                                  2
11435 #define mmLVTMA_PWRSEQ_REF_DIV                                                                         0x2885
11436 #define mmLVTMA_PWRSEQ_REF_DIV_BASE_IDX                                                                2
11437 #define mmLVTMA_PWRSEQ_DELAY1                                                                          0x2886
11438 #define mmLVTMA_PWRSEQ_DELAY1_BASE_IDX                                                                 2
11439 #define mmLVTMA_PWRSEQ_DELAY2                                                                          0x2887
11440 #define mmLVTMA_PWRSEQ_DELAY2_BASE_IDX                                                                 2
11441 #define mmBL_PWM_CNTL                                                                                  0x2888
11442 #define mmBL_PWM_CNTL_BASE_IDX                                                                         2
11443 #define mmBL_PWM_CNTL2                                                                                 0x2889
11444 #define mmBL_PWM_CNTL2_BASE_IDX                                                                        2
11445 #define mmBL_PWM_PERIOD_CNTL                                                                           0x288a
11446 #define mmBL_PWM_PERIOD_CNTL_BASE_IDX                                                                  2
11447 #define mmBL_PWM_GRP1_REG_LOCK                                                                         0x288b
11448 #define mmBL_PWM_GRP1_REG_LOCK_BASE_IDX                                                                2
11449 #define mmDCIO_GSL_GENLK_PAD_CNTL                                                                      0x288c
11450 #define mmDCIO_GSL_GENLK_PAD_CNTL_BASE_IDX                                                             2
11451 #define mmDCIO_GSL_SWAPLOCK_PAD_CNTL                                                                   0x288d
11452 #define mmDCIO_GSL_SWAPLOCK_PAD_CNTL_BASE_IDX                                                          2
11453 #define mmDCIO_SOFT_RESET                                                                              0x289e
11454 #define mmDCIO_SOFT_RESET_BASE_IDX                                                                     2
11455 
11456 
11457 // addressBlock: dce_dc_dcio_dcio_chip_dispdec
11458 // base address: 0x0
11459 #define mmDC_GPIO_GENERIC_MASK                                                                         0x28c8
11460 #define mmDC_GPIO_GENERIC_MASK_BASE_IDX                                                                2
11461 #define mmDC_GPIO_GENERIC_A                                                                            0x28c9
11462 #define mmDC_GPIO_GENERIC_A_BASE_IDX                                                                   2
11463 #define mmDC_GPIO_GENERIC_EN                                                                           0x28ca
11464 #define mmDC_GPIO_GENERIC_EN_BASE_IDX                                                                  2
11465 #define mmDC_GPIO_GENERIC_Y                                                                            0x28cb
11466 #define mmDC_GPIO_GENERIC_Y_BASE_IDX                                                                   2
11467 #define mmDC_GPIO_DDC1_MASK                                                                            0x28d0
11468 #define mmDC_GPIO_DDC1_MASK_BASE_IDX                                                                   2
11469 #define mmDC_GPIO_DDC1_A                                                                               0x28d1
11470 #define mmDC_GPIO_DDC1_A_BASE_IDX                                                                      2
11471 #define mmDC_GPIO_DDC1_EN                                                                              0x28d2
11472 #define mmDC_GPIO_DDC1_EN_BASE_IDX                                                                     2
11473 #define mmDC_GPIO_DDC1_Y                                                                               0x28d3
11474 #define mmDC_GPIO_DDC1_Y_BASE_IDX                                                                      2
11475 #define mmDC_GPIO_DDC2_MASK                                                                            0x28d4
11476 #define mmDC_GPIO_DDC2_MASK_BASE_IDX                                                                   2
11477 #define mmDC_GPIO_DDC2_A                                                                               0x28d5
11478 #define mmDC_GPIO_DDC2_A_BASE_IDX                                                                      2
11479 #define mmDC_GPIO_DDC2_EN                                                                              0x28d6
11480 #define mmDC_GPIO_DDC2_EN_BASE_IDX                                                                     2
11481 #define mmDC_GPIO_DDC2_Y                                                                               0x28d7
11482 #define mmDC_GPIO_DDC2_Y_BASE_IDX                                                                      2
11483 #define mmDC_GPIO_DDC3_MASK                                                                            0x28d8
11484 #define mmDC_GPIO_DDC3_MASK_BASE_IDX                                                                   2
11485 #define mmDC_GPIO_DDC3_A                                                                               0x28d9
11486 #define mmDC_GPIO_DDC3_A_BASE_IDX                                                                      2
11487 #define mmDC_GPIO_DDC3_EN                                                                              0x28da
11488 #define mmDC_GPIO_DDC3_EN_BASE_IDX                                                                     2
11489 #define mmDC_GPIO_DDC3_Y                                                                               0x28db
11490 #define mmDC_GPIO_DDC3_Y_BASE_IDX                                                                      2
11491 #define mmDC_GPIO_DDC4_MASK                                                                            0x28dc
11492 #define mmDC_GPIO_DDC4_MASK_BASE_IDX                                                                   2
11493 #define mmDC_GPIO_DDC4_A                                                                               0x28dd
11494 #define mmDC_GPIO_DDC4_A_BASE_IDX                                                                      2
11495 #define mmDC_GPIO_DDC4_EN                                                                              0x28de
11496 #define mmDC_GPIO_DDC4_EN_BASE_IDX                                                                     2
11497 #define mmDC_GPIO_DDC4_Y                                                                               0x28df
11498 #define mmDC_GPIO_DDC4_Y_BASE_IDX                                                                      2
11499 #define mmDC_GPIO_DDC5_MASK                                                                            0x28e0
11500 #define mmDC_GPIO_DDC5_MASK_BASE_IDX                                                                   2
11501 #define mmDC_GPIO_DDC5_A                                                                               0x28e1
11502 #define mmDC_GPIO_DDC5_A_BASE_IDX                                                                      2
11503 #define mmDC_GPIO_DDC5_EN                                                                              0x28e2
11504 #define mmDC_GPIO_DDC5_EN_BASE_IDX                                                                     2
11505 #define mmDC_GPIO_DDC5_Y                                                                               0x28e3
11506 #define mmDC_GPIO_DDC5_Y_BASE_IDX                                                                      2
11507 #define mmDC_GPIO_DDCVGA_MASK                                                                          0x28e8
11508 #define mmDC_GPIO_DDCVGA_MASK_BASE_IDX                                                                 2
11509 #define mmDC_GPIO_DDCVGA_A                                                                             0x28e9
11510 #define mmDC_GPIO_DDCVGA_A_BASE_IDX                                                                    2
11511 #define mmDC_GPIO_DDCVGA_EN                                                                            0x28ea
11512 #define mmDC_GPIO_DDCVGA_EN_BASE_IDX                                                                   2
11513 #define mmDC_GPIO_DDCVGA_Y                                                                             0x28eb
11514 #define mmDC_GPIO_DDCVGA_Y_BASE_IDX                                                                    2
11515 #define mmDC_GPIO_GENLK_MASK                                                                           0x28f0
11516 #define mmDC_GPIO_GENLK_MASK_BASE_IDX                                                                  2
11517 #define mmDC_GPIO_GENLK_A                                                                              0x28f1
11518 #define mmDC_GPIO_GENLK_A_BASE_IDX                                                                     2
11519 #define mmDC_GPIO_GENLK_EN                                                                             0x28f2
11520 #define mmDC_GPIO_GENLK_EN_BASE_IDX                                                                    2
11521 #define mmDC_GPIO_GENLK_Y                                                                              0x28f3
11522 #define mmDC_GPIO_GENLK_Y_BASE_IDX                                                                     2
11523 #define mmDC_GPIO_HPD_MASK                                                                             0x28f4
11524 #define mmDC_GPIO_HPD_MASK_BASE_IDX                                                                    2
11525 #define mmDC_GPIO_HPD_A                                                                                0x28f5
11526 #define mmDC_GPIO_HPD_A_BASE_IDX                                                                       2
11527 #define mmDC_GPIO_HPD_EN                                                                               0x28f6
11528 #define mmDC_GPIO_HPD_EN_BASE_IDX                                                                      2
11529 #define mmDC_GPIO_HPD_Y                                                                                0x28f7
11530 #define mmDC_GPIO_HPD_Y_BASE_IDX                                                                       2
11531 #define mmDC_GPIO_PWRSEQ_MASK                                                                          0x28f8
11532 #define mmDC_GPIO_PWRSEQ_MASK_BASE_IDX                                                                 2
11533 #define mmDC_GPIO_PWRSEQ_A                                                                             0x28f9
11534 #define mmDC_GPIO_PWRSEQ_A_BASE_IDX                                                                    2
11535 #define mmDC_GPIO_PWRSEQ_EN                                                                            0x28fa
11536 #define mmDC_GPIO_PWRSEQ_EN_BASE_IDX                                                                   2
11537 #define mmDC_GPIO_PWRSEQ_Y                                                                             0x28fb
11538 #define mmDC_GPIO_PWRSEQ_Y_BASE_IDX                                                                    2
11539 #define mmDC_GPIO_PAD_STRENGTH_1                                                                       0x28fc
11540 #define mmDC_GPIO_PAD_STRENGTH_1_BASE_IDX                                                              2
11541 #define mmDC_GPIO_PAD_STRENGTH_2                                                                       0x28fd
11542 #define mmDC_GPIO_PAD_STRENGTH_2_BASE_IDX                                                              2
11543 #define mmPHY_AUX_CNTL                                                                                 0x28ff
11544 #define mmPHY_AUX_CNTL_BASE_IDX                                                                        2
11545 #define mmDC_GPIO_TX12_EN                                                                              0x2915
11546 #define mmDC_GPIO_TX12_EN_BASE_IDX                                                                     2
11547 #define mmDC_GPIO_AUX_CTRL_0                                                                           0x2916
11548 #define mmDC_GPIO_AUX_CTRL_0_BASE_IDX                                                                  2
11549 #define mmDC_GPIO_AUX_CTRL_1                                                                           0x2917
11550 #define mmDC_GPIO_AUX_CTRL_1_BASE_IDX                                                                  2
11551 #define mmDC_GPIO_AUX_CTRL_2                                                                           0x2918
11552 #define mmDC_GPIO_AUX_CTRL_2_BASE_IDX                                                                  2
11553 #define mmDC_GPIO_RXEN                                                                                 0x2919
11554 #define mmDC_GPIO_RXEN_BASE_IDX                                                                        2
11555 #define mmDC_GPIO_PULLUPEN                                                                             0x291a
11556 #define mmDC_GPIO_PULLUPEN_BASE_IDX                                                                    2
11557 #define mmDC_GPIO_AUX_CTRL_3                                                                           0x291b
11558 #define mmDC_GPIO_AUX_CTRL_3_BASE_IDX                                                                  2
11559 #define mmDC_GPIO_AUX_CTRL_4                                                                           0x291c
11560 #define mmDC_GPIO_AUX_CTRL_4_BASE_IDX                                                                  2
11561 #define mmDC_GPIO_AUX_CTRL_5                                                                           0x291d
11562 #define mmDC_GPIO_AUX_CTRL_5_BASE_IDX                                                                  2
11563 #define mmAUXI2C_PAD_ALL_PWR_OK                                                                        0x291e
11564 #define mmAUXI2C_PAD_ALL_PWR_OK_BASE_IDX                                                               2
11565 
11566 
11567 
11568 // addressBlock: dce_dc_dsc0_dispdec_dsc_top_dispdec
11569 // base address: 0x0
11570 #define mmDSC_TOP0_DSC_TOP_CONTROL                                                                     0x3000
11571 #define mmDSC_TOP0_DSC_TOP_CONTROL_BASE_IDX                                                            2
11572 #define mmDSC_TOP0_DSC_DEBUG_CONTROL                                                                   0x3001
11573 #define mmDSC_TOP0_DSC_DEBUG_CONTROL_BASE_IDX                                                          2
11574 
11575 
11576 // addressBlock: dce_dc_dsc0_dispdec_dsccif_dispdec
11577 // base address: 0x0
11578 #define mmDSCCIF0_DSCCIF_CONFIG0                                                                       0x3005
11579 #define mmDSCCIF0_DSCCIF_CONFIG0_BASE_IDX                                                              2
11580 #define mmDSCCIF0_DSCCIF_CONFIG1                                                                       0x3006
11581 #define mmDSCCIF0_DSCCIF_CONFIG1_BASE_IDX                                                              2
11582 
11583 
11584 // addressBlock: dce_dc_dsc0_dispdec_dscc_dispdec
11585 // base address: 0x0
11586 #define mmDSCC0_DSCC_CONFIG0                                                                           0x300a
11587 #define mmDSCC0_DSCC_CONFIG0_BASE_IDX                                                                  2
11588 #define mmDSCC0_DSCC_CONFIG1                                                                           0x300b
11589 #define mmDSCC0_DSCC_CONFIG1_BASE_IDX                                                                  2
11590 #define mmDSCC0_DSCC_STATUS                                                                            0x300c
11591 #define mmDSCC0_DSCC_STATUS_BASE_IDX                                                                   2
11592 #define mmDSCC0_DSCC_INTERRUPT_CONTROL_STATUS                                                          0x300d
11593 #define mmDSCC0_DSCC_INTERRUPT_CONTROL_STATUS_BASE_IDX                                                 2
11594 #define mmDSCC0_DSCC_PPS_CONFIG0                                                                       0x300e
11595 #define mmDSCC0_DSCC_PPS_CONFIG0_BASE_IDX                                                              2
11596 #define mmDSCC0_DSCC_PPS_CONFIG1                                                                       0x300f
11597 #define mmDSCC0_DSCC_PPS_CONFIG1_BASE_IDX                                                              2
11598 #define mmDSCC0_DSCC_PPS_CONFIG2                                                                       0x3010
11599 #define mmDSCC0_DSCC_PPS_CONFIG2_BASE_IDX                                                              2
11600 #define mmDSCC0_DSCC_PPS_CONFIG3                                                                       0x3011
11601 #define mmDSCC0_DSCC_PPS_CONFIG3_BASE_IDX                                                              2
11602 #define mmDSCC0_DSCC_PPS_CONFIG4                                                                       0x3012
11603 #define mmDSCC0_DSCC_PPS_CONFIG4_BASE_IDX                                                              2
11604 #define mmDSCC0_DSCC_PPS_CONFIG5                                                                       0x3013
11605 #define mmDSCC0_DSCC_PPS_CONFIG5_BASE_IDX                                                              2
11606 #define mmDSCC0_DSCC_PPS_CONFIG6                                                                       0x3014
11607 #define mmDSCC0_DSCC_PPS_CONFIG6_BASE_IDX                                                              2
11608 #define mmDSCC0_DSCC_PPS_CONFIG7                                                                       0x3015
11609 #define mmDSCC0_DSCC_PPS_CONFIG7_BASE_IDX                                                              2
11610 #define mmDSCC0_DSCC_PPS_CONFIG8                                                                       0x3016
11611 #define mmDSCC0_DSCC_PPS_CONFIG8_BASE_IDX                                                              2
11612 #define mmDSCC0_DSCC_PPS_CONFIG9                                                                       0x3017
11613 #define mmDSCC0_DSCC_PPS_CONFIG9_BASE_IDX                                                              2
11614 #define mmDSCC0_DSCC_PPS_CONFIG10                                                                      0x3018
11615 #define mmDSCC0_DSCC_PPS_CONFIG10_BASE_IDX                                                             2
11616 #define mmDSCC0_DSCC_PPS_CONFIG11                                                                      0x3019
11617 #define mmDSCC0_DSCC_PPS_CONFIG11_BASE_IDX                                                             2
11618 #define mmDSCC0_DSCC_PPS_CONFIG12                                                                      0x301a
11619 #define mmDSCC0_DSCC_PPS_CONFIG12_BASE_IDX                                                             2
11620 #define mmDSCC0_DSCC_PPS_CONFIG13                                                                      0x301b
11621 #define mmDSCC0_DSCC_PPS_CONFIG13_BASE_IDX                                                             2
11622 #define mmDSCC0_DSCC_PPS_CONFIG14                                                                      0x301c
11623 #define mmDSCC0_DSCC_PPS_CONFIG14_BASE_IDX                                                             2
11624 #define mmDSCC0_DSCC_PPS_CONFIG15                                                                      0x301d
11625 #define mmDSCC0_DSCC_PPS_CONFIG15_BASE_IDX                                                             2
11626 #define mmDSCC0_DSCC_PPS_CONFIG16                                                                      0x301e
11627 #define mmDSCC0_DSCC_PPS_CONFIG16_BASE_IDX                                                             2
11628 #define mmDSCC0_DSCC_PPS_CONFIG17                                                                      0x301f
11629 #define mmDSCC0_DSCC_PPS_CONFIG17_BASE_IDX                                                             2
11630 #define mmDSCC0_DSCC_PPS_CONFIG18                                                                      0x3020
11631 #define mmDSCC0_DSCC_PPS_CONFIG18_BASE_IDX                                                             2
11632 #define mmDSCC0_DSCC_PPS_CONFIG19                                                                      0x3021
11633 #define mmDSCC0_DSCC_PPS_CONFIG19_BASE_IDX                                                             2
11634 #define mmDSCC0_DSCC_PPS_CONFIG20                                                                      0x3022
11635 #define mmDSCC0_DSCC_PPS_CONFIG20_BASE_IDX                                                             2
11636 #define mmDSCC0_DSCC_PPS_CONFIG21                                                                      0x3023
11637 #define mmDSCC0_DSCC_PPS_CONFIG21_BASE_IDX                                                             2
11638 #define mmDSCC0_DSCC_PPS_CONFIG22                                                                      0x3024
11639 #define mmDSCC0_DSCC_PPS_CONFIG22_BASE_IDX                                                             2
11640 #define mmDSCC0_DSCC_MEM_POWER_CONTROL                                                                 0x3025
11641 #define mmDSCC0_DSCC_MEM_POWER_CONTROL_BASE_IDX                                                        2
11642 #define mmDSCC0_DSCC_R_Y_SQUARED_ERROR_LOWER                                                           0x3026
11643 #define mmDSCC0_DSCC_R_Y_SQUARED_ERROR_LOWER_BASE_IDX                                                  2
11644 #define mmDSCC0_DSCC_R_Y_SQUARED_ERROR_UPPER                                                           0x3027
11645 #define mmDSCC0_DSCC_R_Y_SQUARED_ERROR_UPPER_BASE_IDX                                                  2
11646 #define mmDSCC0_DSCC_G_CB_SQUARED_ERROR_LOWER                                                          0x3028
11647 #define mmDSCC0_DSCC_G_CB_SQUARED_ERROR_LOWER_BASE_IDX                                                 2
11648 #define mmDSCC0_DSCC_G_CB_SQUARED_ERROR_UPPER                                                          0x3029
11649 #define mmDSCC0_DSCC_G_CB_SQUARED_ERROR_UPPER_BASE_IDX                                                 2
11650 #define mmDSCC0_DSCC_B_CR_SQUARED_ERROR_LOWER                                                          0x302a
11651 #define mmDSCC0_DSCC_B_CR_SQUARED_ERROR_LOWER_BASE_IDX                                                 2
11652 #define mmDSCC0_DSCC_B_CR_SQUARED_ERROR_UPPER                                                          0x302b
11653 #define mmDSCC0_DSCC_B_CR_SQUARED_ERROR_UPPER_BASE_IDX                                                 2
11654 #define mmDSCC0_DSCC_MAX_ABS_ERROR0                                                                    0x302c
11655 #define mmDSCC0_DSCC_MAX_ABS_ERROR0_BASE_IDX                                                           2
11656 #define mmDSCC0_DSCC_MAX_ABS_ERROR1                                                                    0x302d
11657 #define mmDSCC0_DSCC_MAX_ABS_ERROR1_BASE_IDX                                                           2
11658 #define mmDSCC0_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL                                                   0x302e
11659 #define mmDSCC0_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX                                          2
11660 #define mmDSCC0_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL                                                   0x302f
11661 #define mmDSCC0_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX                                          2
11662 #define mmDSCC0_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL                                                   0x3030
11663 #define mmDSCC0_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX                                          2
11664 #define mmDSCC0_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL                                                   0x3031
11665 #define mmDSCC0_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX                                          2
11666 #define mmDSCC0_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL                                           0x3032
11667 #define mmDSCC0_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX                                  2
11668 #define mmDSCC0_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL                                           0x3033
11669 #define mmDSCC0_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX                                  2
11670 #define mmDSCC0_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL                                           0x3034
11671 #define mmDSCC0_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX                                  2
11672 #define mmDSCC0_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL                                           0x3035
11673 #define mmDSCC0_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX                                  2
11674 
11675 
11676 // addressBlock: dce_dc_dsc0_dispdec_dsc_dcperfmon_dc_perfmon_dispdec
11677 // base address: 0xc140
11678 #define mmDC_PERFMON19_PERFCOUNTER_CNTL                                                                0x3050
11679 #define mmDC_PERFMON19_PERFCOUNTER_CNTL_BASE_IDX                                                       2
11680 #define mmDC_PERFMON19_PERFCOUNTER_CNTL2                                                               0x3051
11681 #define mmDC_PERFMON19_PERFCOUNTER_CNTL2_BASE_IDX                                                      2
11682 #define mmDC_PERFMON19_PERFCOUNTER_STATE                                                               0x3052
11683 #define mmDC_PERFMON19_PERFCOUNTER_STATE_BASE_IDX                                                      2
11684 #define mmDC_PERFMON19_PERFMON_CNTL                                                                    0x3053
11685 #define mmDC_PERFMON19_PERFMON_CNTL_BASE_IDX                                                           2
11686 #define mmDC_PERFMON19_PERFMON_CNTL2                                                                   0x3054
11687 #define mmDC_PERFMON19_PERFMON_CNTL2_BASE_IDX                                                          2
11688 #define mmDC_PERFMON19_PERFMON_CVALUE_INT_MISC                                                         0x3055
11689 #define mmDC_PERFMON19_PERFMON_CVALUE_INT_MISC_BASE_IDX                                                2
11690 #define mmDC_PERFMON19_PERFMON_CVALUE_LOW                                                              0x3056
11691 #define mmDC_PERFMON19_PERFMON_CVALUE_LOW_BASE_IDX                                                     2
11692 #define mmDC_PERFMON19_PERFMON_HI                                                                      0x3057
11693 #define mmDC_PERFMON19_PERFMON_HI_BASE_IDX                                                             2
11694 #define mmDC_PERFMON19_PERFMON_LOW                                                                     0x3058
11695 #define mmDC_PERFMON19_PERFMON_LOW_BASE_IDX                                                            2
11696 
11697 
11698 // addressBlock: dce_dc_dsc1_dispdec_dsc_top_dispdec
11699 // base address: 0x170
11700 #define mmDSC_TOP1_DSC_TOP_CONTROL                                                                     0x305c
11701 #define mmDSC_TOP1_DSC_TOP_CONTROL_BASE_IDX                                                            2
11702 #define mmDSC_TOP1_DSC_DEBUG_CONTROL                                                                   0x305d
11703 #define mmDSC_TOP1_DSC_DEBUG_CONTROL_BASE_IDX                                                          2
11704 
11705 
11706 // addressBlock: dce_dc_dsc1_dispdec_dsccif_dispdec
11707 // base address: 0x170
11708 #define mmDSCCIF1_DSCCIF_CONFIG0                                                                       0x3061
11709 #define mmDSCCIF1_DSCCIF_CONFIG0_BASE_IDX                                                              2
11710 #define mmDSCCIF1_DSCCIF_CONFIG1                                                                       0x3062
11711 #define mmDSCCIF1_DSCCIF_CONFIG1_BASE_IDX                                                              2
11712 
11713 
11714 // addressBlock: dce_dc_dsc1_dispdec_dscc_dispdec
11715 // base address: 0x170
11716 #define mmDSCC1_DSCC_CONFIG0                                                                           0x3066
11717 #define mmDSCC1_DSCC_CONFIG0_BASE_IDX                                                                  2
11718 #define mmDSCC1_DSCC_CONFIG1                                                                           0x3067
11719 #define mmDSCC1_DSCC_CONFIG1_BASE_IDX                                                                  2
11720 #define mmDSCC1_DSCC_STATUS                                                                            0x3068
11721 #define mmDSCC1_DSCC_STATUS_BASE_IDX                                                                   2
11722 #define mmDSCC1_DSCC_INTERRUPT_CONTROL_STATUS                                                          0x3069
11723 #define mmDSCC1_DSCC_INTERRUPT_CONTROL_STATUS_BASE_IDX                                                 2
11724 #define mmDSCC1_DSCC_PPS_CONFIG0                                                                       0x306a
11725 #define mmDSCC1_DSCC_PPS_CONFIG0_BASE_IDX                                                              2
11726 #define mmDSCC1_DSCC_PPS_CONFIG1                                                                       0x306b
11727 #define mmDSCC1_DSCC_PPS_CONFIG1_BASE_IDX                                                              2
11728 #define mmDSCC1_DSCC_PPS_CONFIG2                                                                       0x306c
11729 #define mmDSCC1_DSCC_PPS_CONFIG2_BASE_IDX                                                              2
11730 #define mmDSCC1_DSCC_PPS_CONFIG3                                                                       0x306d
11731 #define mmDSCC1_DSCC_PPS_CONFIG3_BASE_IDX                                                              2
11732 #define mmDSCC1_DSCC_PPS_CONFIG4                                                                       0x306e
11733 #define mmDSCC1_DSCC_PPS_CONFIG4_BASE_IDX                                                              2
11734 #define mmDSCC1_DSCC_PPS_CONFIG5                                                                       0x306f
11735 #define mmDSCC1_DSCC_PPS_CONFIG5_BASE_IDX                                                              2
11736 #define mmDSCC1_DSCC_PPS_CONFIG6                                                                       0x3070
11737 #define mmDSCC1_DSCC_PPS_CONFIG6_BASE_IDX                                                              2
11738 #define mmDSCC1_DSCC_PPS_CONFIG7                                                                       0x3071
11739 #define mmDSCC1_DSCC_PPS_CONFIG7_BASE_IDX                                                              2
11740 #define mmDSCC1_DSCC_PPS_CONFIG8                                                                       0x3072
11741 #define mmDSCC1_DSCC_PPS_CONFIG8_BASE_IDX                                                              2
11742 #define mmDSCC1_DSCC_PPS_CONFIG9                                                                       0x3073
11743 #define mmDSCC1_DSCC_PPS_CONFIG9_BASE_IDX                                                              2
11744 #define mmDSCC1_DSCC_PPS_CONFIG10                                                                      0x3074
11745 #define mmDSCC1_DSCC_PPS_CONFIG10_BASE_IDX                                                             2
11746 #define mmDSCC1_DSCC_PPS_CONFIG11                                                                      0x3075
11747 #define mmDSCC1_DSCC_PPS_CONFIG11_BASE_IDX                                                             2
11748 #define mmDSCC1_DSCC_PPS_CONFIG12                                                                      0x3076
11749 #define mmDSCC1_DSCC_PPS_CONFIG12_BASE_IDX                                                             2
11750 #define mmDSCC1_DSCC_PPS_CONFIG13                                                                      0x3077
11751 #define mmDSCC1_DSCC_PPS_CONFIG13_BASE_IDX                                                             2
11752 #define mmDSCC1_DSCC_PPS_CONFIG14                                                                      0x3078
11753 #define mmDSCC1_DSCC_PPS_CONFIG14_BASE_IDX                                                             2
11754 #define mmDSCC1_DSCC_PPS_CONFIG15                                                                      0x3079
11755 #define mmDSCC1_DSCC_PPS_CONFIG15_BASE_IDX                                                             2
11756 #define mmDSCC1_DSCC_PPS_CONFIG16                                                                      0x307a
11757 #define mmDSCC1_DSCC_PPS_CONFIG16_BASE_IDX                                                             2
11758 #define mmDSCC1_DSCC_PPS_CONFIG17                                                                      0x307b
11759 #define mmDSCC1_DSCC_PPS_CONFIG17_BASE_IDX                                                             2
11760 #define mmDSCC1_DSCC_PPS_CONFIG18                                                                      0x307c
11761 #define mmDSCC1_DSCC_PPS_CONFIG18_BASE_IDX                                                             2
11762 #define mmDSCC1_DSCC_PPS_CONFIG19                                                                      0x307d
11763 #define mmDSCC1_DSCC_PPS_CONFIG19_BASE_IDX                                                             2
11764 #define mmDSCC1_DSCC_PPS_CONFIG20                                                                      0x307e
11765 #define mmDSCC1_DSCC_PPS_CONFIG20_BASE_IDX                                                             2
11766 #define mmDSCC1_DSCC_PPS_CONFIG21                                                                      0x307f
11767 #define mmDSCC1_DSCC_PPS_CONFIG21_BASE_IDX                                                             2
11768 #define mmDSCC1_DSCC_PPS_CONFIG22                                                                      0x3080
11769 #define mmDSCC1_DSCC_PPS_CONFIG22_BASE_IDX                                                             2
11770 #define mmDSCC1_DSCC_MEM_POWER_CONTROL                                                                 0x3081
11771 #define mmDSCC1_DSCC_MEM_POWER_CONTROL_BASE_IDX                                                        2
11772 #define mmDSCC1_DSCC_R_Y_SQUARED_ERROR_LOWER                                                           0x3082
11773 #define mmDSCC1_DSCC_R_Y_SQUARED_ERROR_LOWER_BASE_IDX                                                  2
11774 #define mmDSCC1_DSCC_R_Y_SQUARED_ERROR_UPPER                                                           0x3083
11775 #define mmDSCC1_DSCC_R_Y_SQUARED_ERROR_UPPER_BASE_IDX                                                  2
11776 #define mmDSCC1_DSCC_G_CB_SQUARED_ERROR_LOWER                                                          0x3084
11777 #define mmDSCC1_DSCC_G_CB_SQUARED_ERROR_LOWER_BASE_IDX                                                 2
11778 #define mmDSCC1_DSCC_G_CB_SQUARED_ERROR_UPPER                                                          0x3085
11779 #define mmDSCC1_DSCC_G_CB_SQUARED_ERROR_UPPER_BASE_IDX                                                 2
11780 #define mmDSCC1_DSCC_B_CR_SQUARED_ERROR_LOWER                                                          0x3086
11781 #define mmDSCC1_DSCC_B_CR_SQUARED_ERROR_LOWER_BASE_IDX                                                 2
11782 #define mmDSCC1_DSCC_B_CR_SQUARED_ERROR_UPPER                                                          0x3087
11783 #define mmDSCC1_DSCC_B_CR_SQUARED_ERROR_UPPER_BASE_IDX                                                 2
11784 #define mmDSCC1_DSCC_MAX_ABS_ERROR0                                                                    0x3088
11785 #define mmDSCC1_DSCC_MAX_ABS_ERROR0_BASE_IDX                                                           2
11786 #define mmDSCC1_DSCC_MAX_ABS_ERROR1                                                                    0x3089
11787 #define mmDSCC1_DSCC_MAX_ABS_ERROR1_BASE_IDX                                                           2
11788 #define mmDSCC1_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL                                                   0x308a
11789 #define mmDSCC1_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX                                          2
11790 #define mmDSCC1_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL                                                   0x308b
11791 #define mmDSCC1_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX                                          2
11792 #define mmDSCC1_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL                                                   0x308c
11793 #define mmDSCC1_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX                                          2
11794 #define mmDSCC1_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL                                                   0x308d
11795 #define mmDSCC1_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX                                          2
11796 #define mmDSCC1_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL                                           0x308e
11797 #define mmDSCC1_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX                                  2
11798 #define mmDSCC1_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL                                           0x308f
11799 #define mmDSCC1_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX                                  2
11800 #define mmDSCC1_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL                                           0x3090
11801 #define mmDSCC1_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX                                  2
11802 #define mmDSCC1_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL                                           0x3091
11803 #define mmDSCC1_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX                                  2
11804 
11805 
11806 // addressBlock: dce_dc_dsc1_dispdec_dsc_dcperfmon_dc_perfmon_dispdec
11807 // base address: 0xc2b0
11808 #define mmDC_PERFMON20_PERFCOUNTER_CNTL                                                                0x30ac
11809 #define mmDC_PERFMON20_PERFCOUNTER_CNTL_BASE_IDX                                                       2
11810 #define mmDC_PERFMON20_PERFCOUNTER_CNTL2                                                               0x30ad
11811 #define mmDC_PERFMON20_PERFCOUNTER_CNTL2_BASE_IDX                                                      2
11812 #define mmDC_PERFMON20_PERFCOUNTER_STATE                                                               0x30ae
11813 #define mmDC_PERFMON20_PERFCOUNTER_STATE_BASE_IDX                                                      2
11814 #define mmDC_PERFMON20_PERFMON_CNTL                                                                    0x30af
11815 #define mmDC_PERFMON20_PERFMON_CNTL_BASE_IDX                                                           2
11816 #define mmDC_PERFMON20_PERFMON_CNTL2                                                                   0x30b0
11817 #define mmDC_PERFMON20_PERFMON_CNTL2_BASE_IDX                                                          2
11818 #define mmDC_PERFMON20_PERFMON_CVALUE_INT_MISC                                                         0x30b1
11819 #define mmDC_PERFMON20_PERFMON_CVALUE_INT_MISC_BASE_IDX                                                2
11820 #define mmDC_PERFMON20_PERFMON_CVALUE_LOW                                                              0x30b2
11821 #define mmDC_PERFMON20_PERFMON_CVALUE_LOW_BASE_IDX                                                     2
11822 #define mmDC_PERFMON20_PERFMON_HI                                                                      0x30b3
11823 #define mmDC_PERFMON20_PERFMON_HI_BASE_IDX                                                             2
11824 #define mmDC_PERFMON20_PERFMON_LOW                                                                     0x30b4
11825 #define mmDC_PERFMON20_PERFMON_LOW_BASE_IDX                                                            2
11826 
11827 
11828 // addressBlock: dce_dc_dsc2_dispdec_dsc_top_dispdec
11829 // base address: 0x2e0
11830 #define mmDSC_TOP2_DSC_TOP_CONTROL                                                                     0x30b8
11831 #define mmDSC_TOP2_DSC_TOP_CONTROL_BASE_IDX                                                            2
11832 #define mmDSC_TOP2_DSC_DEBUG_CONTROL                                                                   0x30b9
11833 #define mmDSC_TOP2_DSC_DEBUG_CONTROL_BASE_IDX                                                          2
11834 
11835 
11836 // addressBlock: dce_dc_dsc2_dispdec_dsccif_dispdec
11837 // base address: 0x2e0
11838 #define mmDSCCIF2_DSCCIF_CONFIG0                                                                       0x30bd
11839 #define mmDSCCIF2_DSCCIF_CONFIG0_BASE_IDX                                                              2
11840 #define mmDSCCIF2_DSCCIF_CONFIG1                                                                       0x30be
11841 #define mmDSCCIF2_DSCCIF_CONFIG1_BASE_IDX                                                              2
11842 
11843 
11844 // addressBlock: dce_dc_dsc2_dispdec_dscc_dispdec
11845 // base address: 0x2e0
11846 #define mmDSCC2_DSCC_CONFIG0                                                                           0x30c2
11847 #define mmDSCC2_DSCC_CONFIG0_BASE_IDX                                                                  2
11848 #define mmDSCC2_DSCC_CONFIG1                                                                           0x30c3
11849 #define mmDSCC2_DSCC_CONFIG1_BASE_IDX                                                                  2
11850 #define mmDSCC2_DSCC_STATUS                                                                            0x30c4
11851 #define mmDSCC2_DSCC_STATUS_BASE_IDX                                                                   2
11852 #define mmDSCC2_DSCC_INTERRUPT_CONTROL_STATUS                                                          0x30c5
11853 #define mmDSCC2_DSCC_INTERRUPT_CONTROL_STATUS_BASE_IDX                                                 2
11854 #define mmDSCC2_DSCC_PPS_CONFIG0                                                                       0x30c6
11855 #define mmDSCC2_DSCC_PPS_CONFIG0_BASE_IDX                                                              2
11856 #define mmDSCC2_DSCC_PPS_CONFIG1                                                                       0x30c7
11857 #define mmDSCC2_DSCC_PPS_CONFIG1_BASE_IDX                                                              2
11858 #define mmDSCC2_DSCC_PPS_CONFIG2                                                                       0x30c8
11859 #define mmDSCC2_DSCC_PPS_CONFIG2_BASE_IDX                                                              2
11860 #define mmDSCC2_DSCC_PPS_CONFIG3                                                                       0x30c9
11861 #define mmDSCC2_DSCC_PPS_CONFIG3_BASE_IDX                                                              2
11862 #define mmDSCC2_DSCC_PPS_CONFIG4                                                                       0x30ca
11863 #define mmDSCC2_DSCC_PPS_CONFIG4_BASE_IDX                                                              2
11864 #define mmDSCC2_DSCC_PPS_CONFIG5                                                                       0x30cb
11865 #define mmDSCC2_DSCC_PPS_CONFIG5_BASE_IDX                                                              2
11866 #define mmDSCC2_DSCC_PPS_CONFIG6                                                                       0x30cc
11867 #define mmDSCC2_DSCC_PPS_CONFIG6_BASE_IDX                                                              2
11868 #define mmDSCC2_DSCC_PPS_CONFIG7                                                                       0x30cd
11869 #define mmDSCC2_DSCC_PPS_CONFIG7_BASE_IDX                                                              2
11870 #define mmDSCC2_DSCC_PPS_CONFIG8                                                                       0x30ce
11871 #define mmDSCC2_DSCC_PPS_CONFIG8_BASE_IDX                                                              2
11872 #define mmDSCC2_DSCC_PPS_CONFIG9                                                                       0x30cf
11873 #define mmDSCC2_DSCC_PPS_CONFIG9_BASE_IDX                                                              2
11874 #define mmDSCC2_DSCC_PPS_CONFIG10                                                                      0x30d0
11875 #define mmDSCC2_DSCC_PPS_CONFIG10_BASE_IDX                                                             2
11876 #define mmDSCC2_DSCC_PPS_CONFIG11                                                                      0x30d1
11877 #define mmDSCC2_DSCC_PPS_CONFIG11_BASE_IDX                                                             2
11878 #define mmDSCC2_DSCC_PPS_CONFIG12                                                                      0x30d2
11879 #define mmDSCC2_DSCC_PPS_CONFIG12_BASE_IDX                                                             2
11880 #define mmDSCC2_DSCC_PPS_CONFIG13                                                                      0x30d3
11881 #define mmDSCC2_DSCC_PPS_CONFIG13_BASE_IDX                                                             2
11882 #define mmDSCC2_DSCC_PPS_CONFIG14                                                                      0x30d4
11883 #define mmDSCC2_DSCC_PPS_CONFIG14_BASE_IDX                                                             2
11884 #define mmDSCC2_DSCC_PPS_CONFIG15                                                                      0x30d5
11885 #define mmDSCC2_DSCC_PPS_CONFIG15_BASE_IDX                                                             2
11886 #define mmDSCC2_DSCC_PPS_CONFIG16                                                                      0x30d6
11887 #define mmDSCC2_DSCC_PPS_CONFIG16_BASE_IDX                                                             2
11888 #define mmDSCC2_DSCC_PPS_CONFIG17                                                                      0x30d7
11889 #define mmDSCC2_DSCC_PPS_CONFIG17_BASE_IDX                                                             2
11890 #define mmDSCC2_DSCC_PPS_CONFIG18                                                                      0x30d8
11891 #define mmDSCC2_DSCC_PPS_CONFIG18_BASE_IDX                                                             2
11892 #define mmDSCC2_DSCC_PPS_CONFIG19                                                                      0x30d9
11893 #define mmDSCC2_DSCC_PPS_CONFIG19_BASE_IDX                                                             2
11894 #define mmDSCC2_DSCC_PPS_CONFIG20                                                                      0x30da
11895 #define mmDSCC2_DSCC_PPS_CONFIG20_BASE_IDX                                                             2
11896 #define mmDSCC2_DSCC_PPS_CONFIG21                                                                      0x30db
11897 #define mmDSCC2_DSCC_PPS_CONFIG21_BASE_IDX                                                             2
11898 #define mmDSCC2_DSCC_PPS_CONFIG22                                                                      0x30dc
11899 #define mmDSCC2_DSCC_PPS_CONFIG22_BASE_IDX                                                             2
11900 #define mmDSCC2_DSCC_MEM_POWER_CONTROL                                                                 0x30dd
11901 #define mmDSCC2_DSCC_MEM_POWER_CONTROL_BASE_IDX                                                        2
11902 #define mmDSCC2_DSCC_R_Y_SQUARED_ERROR_LOWER                                                           0x30de
11903 #define mmDSCC2_DSCC_R_Y_SQUARED_ERROR_LOWER_BASE_IDX                                                  2
11904 #define mmDSCC2_DSCC_R_Y_SQUARED_ERROR_UPPER                                                           0x30df
11905 #define mmDSCC2_DSCC_R_Y_SQUARED_ERROR_UPPER_BASE_IDX                                                  2
11906 #define mmDSCC2_DSCC_G_CB_SQUARED_ERROR_LOWER                                                          0x30e0
11907 #define mmDSCC2_DSCC_G_CB_SQUARED_ERROR_LOWER_BASE_IDX                                                 2
11908 #define mmDSCC2_DSCC_G_CB_SQUARED_ERROR_UPPER                                                          0x30e1
11909 #define mmDSCC2_DSCC_G_CB_SQUARED_ERROR_UPPER_BASE_IDX                                                 2
11910 #define mmDSCC2_DSCC_B_CR_SQUARED_ERROR_LOWER                                                          0x30e2
11911 #define mmDSCC2_DSCC_B_CR_SQUARED_ERROR_LOWER_BASE_IDX                                                 2
11912 #define mmDSCC2_DSCC_B_CR_SQUARED_ERROR_UPPER                                                          0x30e3
11913 #define mmDSCC2_DSCC_B_CR_SQUARED_ERROR_UPPER_BASE_IDX                                                 2
11914 #define mmDSCC2_DSCC_MAX_ABS_ERROR0                                                                    0x30e4
11915 #define mmDSCC2_DSCC_MAX_ABS_ERROR0_BASE_IDX                                                           2
11916 #define mmDSCC2_DSCC_MAX_ABS_ERROR1                                                                    0x30e5
11917 #define mmDSCC2_DSCC_MAX_ABS_ERROR1_BASE_IDX                                                           2
11918 #define mmDSCC2_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL                                                   0x30e6
11919 #define mmDSCC2_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX                                          2
11920 #define mmDSCC2_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL                                                   0x30e7
11921 #define mmDSCC2_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX                                          2
11922 #define mmDSCC2_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL                                                   0x30e8
11923 #define mmDSCC2_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX                                          2
11924 #define mmDSCC2_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL                                                   0x30e9
11925 #define mmDSCC2_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX                                          2
11926 #define mmDSCC2_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL                                           0x30ea
11927 #define mmDSCC2_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX                                  2
11928 #define mmDSCC2_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL                                           0x30eb
11929 #define mmDSCC2_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX                                  2
11930 #define mmDSCC2_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL                                           0x30ec
11931 #define mmDSCC2_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX                                  2
11932 #define mmDSCC2_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL                                           0x30ed
11933 #define mmDSCC2_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX                                  2
11934 
11935 
11936 // addressBlock: dce_dc_dsc2_dispdec_dsc_dcperfmon_dc_perfmon_dispdec
11937 // base address: 0xc420
11938 #define mmDC_PERFMON21_PERFCOUNTER_CNTL                                                                0x3108
11939 #define mmDC_PERFMON21_PERFCOUNTER_CNTL_BASE_IDX                                                       2
11940 #define mmDC_PERFMON21_PERFCOUNTER_CNTL2                                                               0x3109
11941 #define mmDC_PERFMON21_PERFCOUNTER_CNTL2_BASE_IDX                                                      2
11942 #define mmDC_PERFMON21_PERFCOUNTER_STATE                                                               0x310a
11943 #define mmDC_PERFMON21_PERFCOUNTER_STATE_BASE_IDX                                                      2
11944 #define mmDC_PERFMON21_PERFMON_CNTL                                                                    0x310b
11945 #define mmDC_PERFMON21_PERFMON_CNTL_BASE_IDX                                                           2
11946 #define mmDC_PERFMON21_PERFMON_CNTL2                                                                   0x310c
11947 #define mmDC_PERFMON21_PERFMON_CNTL2_BASE_IDX                                                          2
11948 #define mmDC_PERFMON21_PERFMON_CVALUE_INT_MISC                                                         0x310d
11949 #define mmDC_PERFMON21_PERFMON_CVALUE_INT_MISC_BASE_IDX                                                2
11950 #define mmDC_PERFMON21_PERFMON_CVALUE_LOW                                                              0x310e
11951 #define mmDC_PERFMON21_PERFMON_CVALUE_LOW_BASE_IDX                                                     2
11952 #define mmDC_PERFMON21_PERFMON_HI                                                                      0x310f
11953 #define mmDC_PERFMON21_PERFMON_HI_BASE_IDX                                                             2
11954 #define mmDC_PERFMON21_PERFMON_LOW                                                                     0x3110
11955 #define mmDC_PERFMON21_PERFMON_LOW_BASE_IDX                                                            2
11956 
11957 
11958 // addressBlock: dce_dc_dsc3_dispdec_dsc_top_dispdec
11959 // base address: 0x450
11960 #define mmDSC_TOP3_DSC_TOP_CONTROL                                                                     0x3114
11961 #define mmDSC_TOP3_DSC_TOP_CONTROL_BASE_IDX                                                            2
11962 #define mmDSC_TOP3_DSC_DEBUG_CONTROL                                                                   0x3115
11963 #define mmDSC_TOP3_DSC_DEBUG_CONTROL_BASE_IDX                                                          2
11964 
11965 
11966 // addressBlock: dce_dc_dsc3_dispdec_dsccif_dispdec
11967 // base address: 0x450
11968 #define mmDSCCIF3_DSCCIF_CONFIG0                                                                       0x3119
11969 #define mmDSCCIF3_DSCCIF_CONFIG0_BASE_IDX                                                              2
11970 #define mmDSCCIF3_DSCCIF_CONFIG1                                                                       0x311a
11971 #define mmDSCCIF3_DSCCIF_CONFIG1_BASE_IDX                                                              2
11972 
11973 
11974 // addressBlock: dce_dc_dsc3_dispdec_dscc_dispdec
11975 // base address: 0x450
11976 #define mmDSCC3_DSCC_CONFIG0                                                                           0x311e
11977 #define mmDSCC3_DSCC_CONFIG0_BASE_IDX                                                                  2
11978 #define mmDSCC3_DSCC_CONFIG1                                                                           0x311f
11979 #define mmDSCC3_DSCC_CONFIG1_BASE_IDX                                                                  2
11980 #define mmDSCC3_DSCC_STATUS                                                                            0x3120
11981 #define mmDSCC3_DSCC_STATUS_BASE_IDX                                                                   2
11982 #define mmDSCC3_DSCC_INTERRUPT_CONTROL_STATUS                                                          0x3121
11983 #define mmDSCC3_DSCC_INTERRUPT_CONTROL_STATUS_BASE_IDX                                                 2
11984 #define mmDSCC3_DSCC_PPS_CONFIG0                                                                       0x3122
11985 #define mmDSCC3_DSCC_PPS_CONFIG0_BASE_IDX                                                              2
11986 #define mmDSCC3_DSCC_PPS_CONFIG1                                                                       0x3123
11987 #define mmDSCC3_DSCC_PPS_CONFIG1_BASE_IDX                                                              2
11988 #define mmDSCC3_DSCC_PPS_CONFIG2                                                                       0x3124
11989 #define mmDSCC3_DSCC_PPS_CONFIG2_BASE_IDX                                                              2
11990 #define mmDSCC3_DSCC_PPS_CONFIG3                                                                       0x3125
11991 #define mmDSCC3_DSCC_PPS_CONFIG3_BASE_IDX                                                              2
11992 #define mmDSCC3_DSCC_PPS_CONFIG4                                                                       0x3126
11993 #define mmDSCC3_DSCC_PPS_CONFIG4_BASE_IDX                                                              2
11994 #define mmDSCC3_DSCC_PPS_CONFIG5                                                                       0x3127
11995 #define mmDSCC3_DSCC_PPS_CONFIG5_BASE_IDX                                                              2
11996 #define mmDSCC3_DSCC_PPS_CONFIG6                                                                       0x3128
11997 #define mmDSCC3_DSCC_PPS_CONFIG6_BASE_IDX                                                              2
11998 #define mmDSCC3_DSCC_PPS_CONFIG7                                                                       0x3129
11999 #define mmDSCC3_DSCC_PPS_CONFIG7_BASE_IDX                                                              2
12000 #define mmDSCC3_DSCC_PPS_CONFIG8                                                                       0x312a
12001 #define mmDSCC3_DSCC_PPS_CONFIG8_BASE_IDX                                                              2
12002 #define mmDSCC3_DSCC_PPS_CONFIG9                                                                       0x312b
12003 #define mmDSCC3_DSCC_PPS_CONFIG9_BASE_IDX                                                              2
12004 #define mmDSCC3_DSCC_PPS_CONFIG10                                                                      0x312c
12005 #define mmDSCC3_DSCC_PPS_CONFIG10_BASE_IDX                                                             2
12006 #define mmDSCC3_DSCC_PPS_CONFIG11                                                                      0x312d
12007 #define mmDSCC3_DSCC_PPS_CONFIG11_BASE_IDX                                                             2
12008 #define mmDSCC3_DSCC_PPS_CONFIG12                                                                      0x312e
12009 #define mmDSCC3_DSCC_PPS_CONFIG12_BASE_IDX                                                             2
12010 #define mmDSCC3_DSCC_PPS_CONFIG13                                                                      0x312f
12011 #define mmDSCC3_DSCC_PPS_CONFIG13_BASE_IDX                                                             2
12012 #define mmDSCC3_DSCC_PPS_CONFIG14                                                                      0x3130
12013 #define mmDSCC3_DSCC_PPS_CONFIG14_BASE_IDX                                                             2
12014 #define mmDSCC3_DSCC_PPS_CONFIG15                                                                      0x3131
12015 #define mmDSCC3_DSCC_PPS_CONFIG15_BASE_IDX                                                             2
12016 #define mmDSCC3_DSCC_PPS_CONFIG16                                                                      0x3132
12017 #define mmDSCC3_DSCC_PPS_CONFIG16_BASE_IDX                                                             2
12018 #define mmDSCC3_DSCC_PPS_CONFIG17                                                                      0x3133
12019 #define mmDSCC3_DSCC_PPS_CONFIG17_BASE_IDX                                                             2
12020 #define mmDSCC3_DSCC_PPS_CONFIG18                                                                      0x3134
12021 #define mmDSCC3_DSCC_PPS_CONFIG18_BASE_IDX                                                             2
12022 #define mmDSCC3_DSCC_PPS_CONFIG19                                                                      0x3135
12023 #define mmDSCC3_DSCC_PPS_CONFIG19_BASE_IDX                                                             2
12024 #define mmDSCC3_DSCC_PPS_CONFIG20                                                                      0x3136
12025 #define mmDSCC3_DSCC_PPS_CONFIG20_BASE_IDX                                                             2
12026 #define mmDSCC3_DSCC_PPS_CONFIG21                                                                      0x3137
12027 #define mmDSCC3_DSCC_PPS_CONFIG21_BASE_IDX                                                             2
12028 #define mmDSCC3_DSCC_PPS_CONFIG22                                                                      0x3138
12029 #define mmDSCC3_DSCC_PPS_CONFIG22_BASE_IDX                                                             2
12030 #define mmDSCC3_DSCC_MEM_POWER_CONTROL                                                                 0x3139
12031 #define mmDSCC3_DSCC_MEM_POWER_CONTROL_BASE_IDX                                                        2
12032 #define mmDSCC3_DSCC_R_Y_SQUARED_ERROR_LOWER                                                           0x313a
12033 #define mmDSCC3_DSCC_R_Y_SQUARED_ERROR_LOWER_BASE_IDX                                                  2
12034 #define mmDSCC3_DSCC_R_Y_SQUARED_ERROR_UPPER                                                           0x313b
12035 #define mmDSCC3_DSCC_R_Y_SQUARED_ERROR_UPPER_BASE_IDX                                                  2
12036 #define mmDSCC3_DSCC_G_CB_SQUARED_ERROR_LOWER                                                          0x313c
12037 #define mmDSCC3_DSCC_G_CB_SQUARED_ERROR_LOWER_BASE_IDX                                                 2
12038 #define mmDSCC3_DSCC_G_CB_SQUARED_ERROR_UPPER                                                          0x313d
12039 #define mmDSCC3_DSCC_G_CB_SQUARED_ERROR_UPPER_BASE_IDX                                                 2
12040 #define mmDSCC3_DSCC_B_CR_SQUARED_ERROR_LOWER                                                          0x313e
12041 #define mmDSCC3_DSCC_B_CR_SQUARED_ERROR_LOWER_BASE_IDX                                                 2
12042 #define mmDSCC3_DSCC_B_CR_SQUARED_ERROR_UPPER                                                          0x313f
12043 #define mmDSCC3_DSCC_B_CR_SQUARED_ERROR_UPPER_BASE_IDX                                                 2
12044 #define mmDSCC3_DSCC_MAX_ABS_ERROR0                                                                    0x3140
12045 #define mmDSCC3_DSCC_MAX_ABS_ERROR0_BASE_IDX                                                           2
12046 #define mmDSCC3_DSCC_MAX_ABS_ERROR1                                                                    0x3141
12047 #define mmDSCC3_DSCC_MAX_ABS_ERROR1_BASE_IDX                                                           2
12048 #define mmDSCC3_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL                                                   0x3142
12049 #define mmDSCC3_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX                                          2
12050 #define mmDSCC3_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL                                                   0x3143
12051 #define mmDSCC3_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX                                          2
12052 #define mmDSCC3_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL                                                   0x3144
12053 #define mmDSCC3_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX                                          2
12054 #define mmDSCC3_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL                                                   0x3145
12055 #define mmDSCC3_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX                                          2
12056 #define mmDSCC3_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL                                           0x3146
12057 #define mmDSCC3_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX                                  2
12058 #define mmDSCC3_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL                                           0x3147
12059 #define mmDSCC3_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX                                  2
12060 #define mmDSCC3_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL                                           0x3148
12061 #define mmDSCC3_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX                                  2
12062 #define mmDSCC3_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL                                           0x3149
12063 #define mmDSCC3_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX                                  2
12064 
12065 
12066 // addressBlock: dce_dc_dsc3_dispdec_dsc_dcperfmon_dc_perfmon_dispdec
12067 // base address: 0xc590
12068 #define mmDC_PERFMON22_PERFCOUNTER_CNTL                                                                0x3164
12069 #define mmDC_PERFMON22_PERFCOUNTER_CNTL_BASE_IDX                                                       2
12070 #define mmDC_PERFMON22_PERFCOUNTER_CNTL2                                                               0x3165
12071 #define mmDC_PERFMON22_PERFCOUNTER_CNTL2_BASE_IDX                                                      2
12072 #define mmDC_PERFMON22_PERFCOUNTER_STATE                                                               0x3166
12073 #define mmDC_PERFMON22_PERFCOUNTER_STATE_BASE_IDX                                                      2
12074 #define mmDC_PERFMON22_PERFMON_CNTL                                                                    0x3167
12075 #define mmDC_PERFMON22_PERFMON_CNTL_BASE_IDX                                                           2
12076 #define mmDC_PERFMON22_PERFMON_CNTL2                                                                   0x3168
12077 #define mmDC_PERFMON22_PERFMON_CNTL2_BASE_IDX                                                          2
12078 #define mmDC_PERFMON22_PERFMON_CVALUE_INT_MISC                                                         0x3169
12079 #define mmDC_PERFMON22_PERFMON_CVALUE_INT_MISC_BASE_IDX                                                2
12080 #define mmDC_PERFMON22_PERFMON_CVALUE_LOW                                                              0x316a
12081 #define mmDC_PERFMON22_PERFMON_CVALUE_LOW_BASE_IDX                                                     2
12082 #define mmDC_PERFMON22_PERFMON_HI                                                                      0x316b
12083 #define mmDC_PERFMON22_PERFMON_HI_BASE_IDX                                                             2
12084 #define mmDC_PERFMON22_PERFMON_LOW                                                                     0x316c
12085 #define mmDC_PERFMON22_PERFMON_LOW_BASE_IDX                                                            2
12086 
12087 
12088 // addressBlock: dce_dc_dsc4_dispdec_dsc_top_dispdec
12089 // base address: 0x5c0
12090 #define mmDSC_TOP4_DSC_TOP_CONTROL                                                                     0x3170
12091 #define mmDSC_TOP4_DSC_TOP_CONTROL_BASE_IDX                                                            2
12092 #define mmDSC_TOP4_DSC_DEBUG_CONTROL                                                                   0x3171
12093 #define mmDSC_TOP4_DSC_DEBUG_CONTROL_BASE_IDX                                                          2
12094 
12095 
12096 // addressBlock: dce_dc_dsc4_dispdec_dsccif_dispdec
12097 // base address: 0x5c0
12098 #define mmDSCCIF4_DSCCIF_CONFIG0                                                                       0x3175
12099 #define mmDSCCIF4_DSCCIF_CONFIG0_BASE_IDX                                                              2
12100 #define mmDSCCIF4_DSCCIF_CONFIG1                                                                       0x3176
12101 #define mmDSCCIF4_DSCCIF_CONFIG1_BASE_IDX                                                              2
12102 
12103 
12104 // addressBlock: dce_dc_dsc4_dispdec_dscc_dispdec
12105 // base address: 0x5c0
12106 #define mmDSCC4_DSCC_CONFIG0                                                                           0x317a
12107 #define mmDSCC4_DSCC_CONFIG0_BASE_IDX                                                                  2
12108 #define mmDSCC4_DSCC_CONFIG1                                                                           0x317b
12109 #define mmDSCC4_DSCC_CONFIG1_BASE_IDX                                                                  2
12110 #define mmDSCC4_DSCC_STATUS                                                                            0x317c
12111 #define mmDSCC4_DSCC_STATUS_BASE_IDX                                                                   2
12112 #define mmDSCC4_DSCC_INTERRUPT_CONTROL_STATUS                                                          0x317d
12113 #define mmDSCC4_DSCC_INTERRUPT_CONTROL_STATUS_BASE_IDX                                                 2
12114 #define mmDSCC4_DSCC_PPS_CONFIG0                                                                       0x317e
12115 #define mmDSCC4_DSCC_PPS_CONFIG0_BASE_IDX                                                              2
12116 #define mmDSCC4_DSCC_PPS_CONFIG1                                                                       0x317f
12117 #define mmDSCC4_DSCC_PPS_CONFIG1_BASE_IDX                                                              2
12118 #define mmDSCC4_DSCC_PPS_CONFIG2                                                                       0x3180
12119 #define mmDSCC4_DSCC_PPS_CONFIG2_BASE_IDX                                                              2
12120 #define mmDSCC4_DSCC_PPS_CONFIG3                                                                       0x3181
12121 #define mmDSCC4_DSCC_PPS_CONFIG3_BASE_IDX                                                              2
12122 #define mmDSCC4_DSCC_PPS_CONFIG4                                                                       0x3182
12123 #define mmDSCC4_DSCC_PPS_CONFIG4_BASE_IDX                                                              2
12124 #define mmDSCC4_DSCC_PPS_CONFIG5                                                                       0x3183
12125 #define mmDSCC4_DSCC_PPS_CONFIG5_BASE_IDX                                                              2
12126 #define mmDSCC4_DSCC_PPS_CONFIG6                                                                       0x3184
12127 #define mmDSCC4_DSCC_PPS_CONFIG6_BASE_IDX                                                              2
12128 #define mmDSCC4_DSCC_PPS_CONFIG7                                                                       0x3185
12129 #define mmDSCC4_DSCC_PPS_CONFIG7_BASE_IDX                                                              2
12130 #define mmDSCC4_DSCC_PPS_CONFIG8                                                                       0x3186
12131 #define mmDSCC4_DSCC_PPS_CONFIG8_BASE_IDX                                                              2
12132 #define mmDSCC4_DSCC_PPS_CONFIG9                                                                       0x3187
12133 #define mmDSCC4_DSCC_PPS_CONFIG9_BASE_IDX                                                              2
12134 #define mmDSCC4_DSCC_PPS_CONFIG10                                                                      0x3188
12135 #define mmDSCC4_DSCC_PPS_CONFIG10_BASE_IDX                                                             2
12136 #define mmDSCC4_DSCC_PPS_CONFIG11                                                                      0x3189
12137 #define mmDSCC4_DSCC_PPS_CONFIG11_BASE_IDX                                                             2
12138 #define mmDSCC4_DSCC_PPS_CONFIG12                                                                      0x318a
12139 #define mmDSCC4_DSCC_PPS_CONFIG12_BASE_IDX                                                             2
12140 #define mmDSCC4_DSCC_PPS_CONFIG13                                                                      0x318b
12141 #define mmDSCC4_DSCC_PPS_CONFIG13_BASE_IDX                                                             2
12142 #define mmDSCC4_DSCC_PPS_CONFIG14                                                                      0x318c
12143 #define mmDSCC4_DSCC_PPS_CONFIG14_BASE_IDX                                                             2
12144 #define mmDSCC4_DSCC_PPS_CONFIG15                                                                      0x318d
12145 #define mmDSCC4_DSCC_PPS_CONFIG15_BASE_IDX                                                             2
12146 #define mmDSCC4_DSCC_PPS_CONFIG16                                                                      0x318e
12147 #define mmDSCC4_DSCC_PPS_CONFIG16_BASE_IDX                                                             2
12148 #define mmDSCC4_DSCC_PPS_CONFIG17                                                                      0x318f
12149 #define mmDSCC4_DSCC_PPS_CONFIG17_BASE_IDX                                                             2
12150 #define mmDSCC4_DSCC_PPS_CONFIG18                                                                      0x3190
12151 #define mmDSCC4_DSCC_PPS_CONFIG18_BASE_IDX                                                             2
12152 #define mmDSCC4_DSCC_PPS_CONFIG19                                                                      0x3191
12153 #define mmDSCC4_DSCC_PPS_CONFIG19_BASE_IDX                                                             2
12154 #define mmDSCC4_DSCC_PPS_CONFIG20                                                                      0x3192
12155 #define mmDSCC4_DSCC_PPS_CONFIG20_BASE_IDX                                                             2
12156 #define mmDSCC4_DSCC_PPS_CONFIG21                                                                      0x3193
12157 #define mmDSCC4_DSCC_PPS_CONFIG21_BASE_IDX                                                             2
12158 #define mmDSCC4_DSCC_PPS_CONFIG22                                                                      0x3194
12159 #define mmDSCC4_DSCC_PPS_CONFIG22_BASE_IDX                                                             2
12160 #define mmDSCC4_DSCC_MEM_POWER_CONTROL                                                                 0x3195
12161 #define mmDSCC4_DSCC_MEM_POWER_CONTROL_BASE_IDX                                                        2
12162 #define mmDSCC4_DSCC_R_Y_SQUARED_ERROR_LOWER                                                           0x3196
12163 #define mmDSCC4_DSCC_R_Y_SQUARED_ERROR_LOWER_BASE_IDX                                                  2
12164 #define mmDSCC4_DSCC_R_Y_SQUARED_ERROR_UPPER                                                           0x3197
12165 #define mmDSCC4_DSCC_R_Y_SQUARED_ERROR_UPPER_BASE_IDX                                                  2
12166 #define mmDSCC4_DSCC_G_CB_SQUARED_ERROR_LOWER                                                          0x3198
12167 #define mmDSCC4_DSCC_G_CB_SQUARED_ERROR_LOWER_BASE_IDX                                                 2
12168 #define mmDSCC4_DSCC_G_CB_SQUARED_ERROR_UPPER                                                          0x3199
12169 #define mmDSCC4_DSCC_G_CB_SQUARED_ERROR_UPPER_BASE_IDX                                                 2
12170 #define mmDSCC4_DSCC_B_CR_SQUARED_ERROR_LOWER                                                          0x319a
12171 #define mmDSCC4_DSCC_B_CR_SQUARED_ERROR_LOWER_BASE_IDX                                                 2
12172 #define mmDSCC4_DSCC_B_CR_SQUARED_ERROR_UPPER                                                          0x319b
12173 #define mmDSCC4_DSCC_B_CR_SQUARED_ERROR_UPPER_BASE_IDX                                                 2
12174 #define mmDSCC4_DSCC_MAX_ABS_ERROR0                                                                    0x319c
12175 #define mmDSCC4_DSCC_MAX_ABS_ERROR0_BASE_IDX                                                           2
12176 #define mmDSCC4_DSCC_MAX_ABS_ERROR1                                                                    0x319d
12177 #define mmDSCC4_DSCC_MAX_ABS_ERROR1_BASE_IDX                                                           2
12178 #define mmDSCC4_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL                                                   0x319e
12179 #define mmDSCC4_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX                                          2
12180 #define mmDSCC4_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL                                                   0x319f
12181 #define mmDSCC4_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX                                          2
12182 #define mmDSCC4_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL                                                   0x31a0
12183 #define mmDSCC4_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX                                          2
12184 #define mmDSCC4_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL                                                   0x31a1
12185 #define mmDSCC4_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX                                          2
12186 #define mmDSCC4_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL                                           0x31a2
12187 #define mmDSCC4_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX                                  2
12188 #define mmDSCC4_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL                                           0x31a3
12189 #define mmDSCC4_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX                                  2
12190 #define mmDSCC4_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL                                           0x31a4
12191 #define mmDSCC4_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX                                  2
12192 #define mmDSCC4_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL                                           0x31a5
12193 #define mmDSCC4_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX                                  2
12194 
12195 
12196 // addressBlock: dce_dc_dsc4_dispdec_dsc_dcperfmon_dc_perfmon_dispdec
12197 // base address: 0xc700
12198 #define mmDC_PERFMON23_PERFCOUNTER_CNTL                                                                0x31c0
12199 #define mmDC_PERFMON23_PERFCOUNTER_CNTL_BASE_IDX                                                       2
12200 #define mmDC_PERFMON23_PERFCOUNTER_CNTL2                                                               0x31c1
12201 #define mmDC_PERFMON23_PERFCOUNTER_CNTL2_BASE_IDX                                                      2
12202 #define mmDC_PERFMON23_PERFCOUNTER_STATE                                                               0x31c2
12203 #define mmDC_PERFMON23_PERFCOUNTER_STATE_BASE_IDX                                                      2
12204 #define mmDC_PERFMON23_PERFMON_CNTL                                                                    0x31c3
12205 #define mmDC_PERFMON23_PERFMON_CNTL_BASE_IDX                                                           2
12206 #define mmDC_PERFMON23_PERFMON_CNTL2                                                                   0x31c4
12207 #define mmDC_PERFMON23_PERFMON_CNTL2_BASE_IDX                                                          2
12208 #define mmDC_PERFMON23_PERFMON_CVALUE_INT_MISC                                                         0x31c5
12209 #define mmDC_PERFMON23_PERFMON_CVALUE_INT_MISC_BASE_IDX                                                2
12210 #define mmDC_PERFMON23_PERFMON_CVALUE_LOW                                                              0x31c6
12211 #define mmDC_PERFMON23_PERFMON_CVALUE_LOW_BASE_IDX                                                     2
12212 #define mmDC_PERFMON23_PERFMON_HI                                                                      0x31c7
12213 #define mmDC_PERFMON23_PERFMON_HI_BASE_IDX                                                             2
12214 #define mmDC_PERFMON23_PERFMON_LOW                                                                     0x31c8
12215 #define mmDC_PERFMON23_PERFMON_LOW_BASE_IDX                                                            2
12216 
12217 
12218 // addressBlock: dce_dc_wb0_dispdec_dwb_top_dispdec
12219 // base address: 0x0
12220 #define mmDWB_ENABLE_CLK_CTRL                                                                          0x3228
12221 #define mmDWB_ENABLE_CLK_CTRL_BASE_IDX                                                                 2
12222 #define mmDWB_MEM_PWR_CTRL                                                                             0x3229
12223 #define mmDWB_MEM_PWR_CTRL_BASE_IDX                                                                    2
12224 #define mmFC_MODE_CTRL                                                                                 0x322a
12225 #define mmFC_MODE_CTRL_BASE_IDX                                                                        2
12226 #define mmFC_FLOW_CTRL                                                                                 0x322b
12227 #define mmFC_FLOW_CTRL_BASE_IDX                                                                        2
12228 #define mmFC_WINDOW_START                                                                              0x322c
12229 #define mmFC_WINDOW_START_BASE_IDX                                                                     2
12230 #define mmFC_WINDOW_SIZE                                                                               0x322d
12231 #define mmFC_WINDOW_SIZE_BASE_IDX                                                                      2
12232 #define mmFC_SOURCE_SIZE                                                                               0x322e
12233 #define mmFC_SOURCE_SIZE_BASE_IDX                                                                      2
12234 #define mmDWB_UPDATE_CTRL                                                                              0x322f
12235 #define mmDWB_UPDATE_CTRL_BASE_IDX                                                                     2
12236 #define mmDWB_CRC_CTRL                                                                                 0x3230
12237 #define mmDWB_CRC_CTRL_BASE_IDX                                                                        2
12238 #define mmDWB_CRC_MASK_R_G                                                                             0x3231
12239 #define mmDWB_CRC_MASK_R_G_BASE_IDX                                                                    2
12240 #define mmDWB_CRC_MASK_B_A                                                                             0x3232
12241 #define mmDWB_CRC_MASK_B_A_BASE_IDX                                                                    2
12242 #define mmDWB_CRC_VAL_R_G                                                                              0x3233
12243 #define mmDWB_CRC_VAL_R_G_BASE_IDX                                                                     2
12244 #define mmDWB_CRC_VAL_B_A                                                                              0x3234
12245 #define mmDWB_CRC_VAL_B_A_BASE_IDX                                                                     2
12246 #define mmDWB_OUT_CTRL                                                                                 0x3235
12247 #define mmDWB_OUT_CTRL_BASE_IDX                                                                        2
12248 #define mmDWB_MMHUBBUB_BACKPRESSURE_CNT_EN                                                             0x3236
12249 #define mmDWB_MMHUBBUB_BACKPRESSURE_CNT_EN_BASE_IDX                                                    2
12250 #define mmDWB_MMHUBBUB_BACKPRESSURE_CNT                                                                0x3237
12251 #define mmDWB_MMHUBBUB_BACKPRESSURE_CNT_BASE_IDX                                                       2
12252 #define mmDWB_HOST_READ_CONTROL                                                                        0x3238
12253 #define mmDWB_HOST_READ_CONTROL_BASE_IDX                                                               2
12254 #define mmDWB_OVERFLOW_STATUS                                                                          0x3239
12255 #define mmDWB_OVERFLOW_STATUS_BASE_IDX                                                                 2
12256 #define mmDWB_OVERFLOW_COUNTER                                                                         0x323a
12257 #define mmDWB_OVERFLOW_COUNTER_BASE_IDX                                                                2
12258 #define mmDWB_SOFT_RESET                                                                               0x323b
12259 #define mmDWB_SOFT_RESET_BASE_IDX                                                                      2
12260 
12261 
12262 // addressBlock: dce_dc_wb0_dispdec_wb_dcperfmon_dc_perfmon_dispdec
12263 // base address: 0xca20
12264 #define mmDC_PERFMON24_PERFCOUNTER_CNTL                                                                0x3288
12265 #define mmDC_PERFMON24_PERFCOUNTER_CNTL_BASE_IDX                                                       2
12266 #define mmDC_PERFMON24_PERFCOUNTER_CNTL2                                                               0x3289
12267 #define mmDC_PERFMON24_PERFCOUNTER_CNTL2_BASE_IDX                                                      2
12268 #define mmDC_PERFMON24_PERFCOUNTER_STATE                                                               0x328a
12269 #define mmDC_PERFMON24_PERFCOUNTER_STATE_BASE_IDX                                                      2
12270 #define mmDC_PERFMON24_PERFMON_CNTL                                                                    0x328b
12271 #define mmDC_PERFMON24_PERFMON_CNTL_BASE_IDX                                                           2
12272 #define mmDC_PERFMON24_PERFMON_CNTL2                                                                   0x328c
12273 #define mmDC_PERFMON24_PERFMON_CNTL2_BASE_IDX                                                          2
12274 #define mmDC_PERFMON24_PERFMON_CVALUE_INT_MISC                                                         0x328d
12275 #define mmDC_PERFMON24_PERFMON_CVALUE_INT_MISC_BASE_IDX                                                2
12276 #define mmDC_PERFMON24_PERFMON_CVALUE_LOW                                                              0x328e
12277 #define mmDC_PERFMON24_PERFMON_CVALUE_LOW_BASE_IDX                                                     2
12278 #define mmDC_PERFMON24_PERFMON_HI                                                                      0x328f
12279 #define mmDC_PERFMON24_PERFMON_HI_BASE_IDX                                                             2
12280 #define mmDC_PERFMON24_PERFMON_LOW                                                                     0x3290
12281 #define mmDC_PERFMON24_PERFMON_LOW_BASE_IDX                                                            2
12282 
12283 
12284 // addressBlock: dce_dc_wb0_dispdec_dwbcp_dispdec
12285 // base address: 0x0
12286 #define mmDWB_HDR_MULT_COEF                                                                            0x3294
12287 #define mmDWB_HDR_MULT_COEF_BASE_IDX                                                                   2
12288 #define mmDWB_GAMUT_REMAP_MODE                                                                         0x3295
12289 #define mmDWB_GAMUT_REMAP_MODE_BASE_IDX                                                                2
12290 #define mmDWB_GAMUT_REMAP_COEF_FORMAT                                                                  0x3296
12291 #define mmDWB_GAMUT_REMAP_COEF_FORMAT_BASE_IDX                                                         2
12292 #define mmDWB_GAMUT_REMAPA_C11_C12                                                                     0x3297
12293 #define mmDWB_GAMUT_REMAPA_C11_C12_BASE_IDX                                                            2
12294 #define mmDWB_GAMUT_REMAPA_C13_C14                                                                     0x3298
12295 #define mmDWB_GAMUT_REMAPA_C13_C14_BASE_IDX                                                            2
12296 #define mmDWB_GAMUT_REMAPA_C21_C22                                                                     0x3299
12297 #define mmDWB_GAMUT_REMAPA_C21_C22_BASE_IDX                                                            2
12298 #define mmDWB_GAMUT_REMAPA_C23_C24                                                                     0x329a
12299 #define mmDWB_GAMUT_REMAPA_C23_C24_BASE_IDX                                                            2
12300 #define mmDWB_GAMUT_REMAPA_C31_C32                                                                     0x329b
12301 #define mmDWB_GAMUT_REMAPA_C31_C32_BASE_IDX                                                            2
12302 #define mmDWB_GAMUT_REMAPA_C33_C34                                                                     0x329c
12303 #define mmDWB_GAMUT_REMAPA_C33_C34_BASE_IDX                                                            2
12304 #define mmDWB_GAMUT_REMAPB_C11_C12                                                                     0x329d
12305 #define mmDWB_GAMUT_REMAPB_C11_C12_BASE_IDX                                                            2
12306 #define mmDWB_GAMUT_REMAPB_C13_C14                                                                     0x329e
12307 #define mmDWB_GAMUT_REMAPB_C13_C14_BASE_IDX                                                            2
12308 #define mmDWB_GAMUT_REMAPB_C21_C22                                                                     0x329f
12309 #define mmDWB_GAMUT_REMAPB_C21_C22_BASE_IDX                                                            2
12310 #define mmDWB_GAMUT_REMAPB_C23_C24                                                                     0x32a0
12311 #define mmDWB_GAMUT_REMAPB_C23_C24_BASE_IDX                                                            2
12312 #define mmDWB_GAMUT_REMAPB_C31_C32                                                                     0x32a1
12313 #define mmDWB_GAMUT_REMAPB_C31_C32_BASE_IDX                                                            2
12314 #define mmDWB_GAMUT_REMAPB_C33_C34                                                                     0x32a2
12315 #define mmDWB_GAMUT_REMAPB_C33_C34_BASE_IDX                                                            2
12316 #define mmDWB_OGAM_CONTROL                                                                             0x32a3
12317 #define mmDWB_OGAM_CONTROL_BASE_IDX                                                                    2
12318 #define mmDWB_OGAM_LUT_INDEX                                                                           0x32a4
12319 #define mmDWB_OGAM_LUT_INDEX_BASE_IDX                                                                  2
12320 #define mmDWB_OGAM_LUT_DATA                                                                            0x32a5
12321 #define mmDWB_OGAM_LUT_DATA_BASE_IDX                                                                   2
12322 #define mmDWB_OGAM_LUT_CONTROL                                                                         0x32a6
12323 #define mmDWB_OGAM_LUT_CONTROL_BASE_IDX                                                                2
12324 #define mmDWB_OGAM_RAMA_START_CNTL_B                                                                   0x32a7
12325 #define mmDWB_OGAM_RAMA_START_CNTL_B_BASE_IDX                                                          2
12326 #define mmDWB_OGAM_RAMA_START_CNTL_G                                                                   0x32a8
12327 #define mmDWB_OGAM_RAMA_START_CNTL_G_BASE_IDX                                                          2
12328 #define mmDWB_OGAM_RAMA_START_CNTL_R                                                                   0x32a9
12329 #define mmDWB_OGAM_RAMA_START_CNTL_R_BASE_IDX                                                          2
12330 #define mmDWB_OGAM_RAMA_START_BASE_CNTL_B                                                              0x32aa
12331 #define mmDWB_OGAM_RAMA_START_BASE_CNTL_B_BASE_IDX                                                     2
12332 #define mmDWB_OGAM_RAMA_START_SLOPE_CNTL_B                                                             0x32ab
12333 #define mmDWB_OGAM_RAMA_START_SLOPE_CNTL_B_BASE_IDX                                                    2
12334 #define mmDWB_OGAM_RAMA_START_BASE_CNTL_G                                                              0x32ac
12335 #define mmDWB_OGAM_RAMA_START_BASE_CNTL_G_BASE_IDX                                                     2
12336 #define mmDWB_OGAM_RAMA_START_SLOPE_CNTL_G                                                             0x32ad
12337 #define mmDWB_OGAM_RAMA_START_SLOPE_CNTL_G_BASE_IDX                                                    2
12338 #define mmDWB_OGAM_RAMA_START_BASE_CNTL_R                                                              0x32ae
12339 #define mmDWB_OGAM_RAMA_START_BASE_CNTL_R_BASE_IDX                                                     2
12340 #define mmDWB_OGAM_RAMA_START_SLOPE_CNTL_R                                                             0x32af
12341 #define mmDWB_OGAM_RAMA_START_SLOPE_CNTL_R_BASE_IDX                                                    2
12342 #define mmDWB_OGAM_RAMA_END_CNTL1_B                                                                    0x32b0
12343 #define mmDWB_OGAM_RAMA_END_CNTL1_B_BASE_IDX                                                           2
12344 #define mmDWB_OGAM_RAMA_END_CNTL2_B                                                                    0x32b1
12345 #define mmDWB_OGAM_RAMA_END_CNTL2_B_BASE_IDX                                                           2
12346 #define mmDWB_OGAM_RAMA_END_CNTL1_G                                                                    0x32b2
12347 #define mmDWB_OGAM_RAMA_END_CNTL1_G_BASE_IDX                                                           2
12348 #define mmDWB_OGAM_RAMA_END_CNTL2_G                                                                    0x32b3
12349 #define mmDWB_OGAM_RAMA_END_CNTL2_G_BASE_IDX                                                           2
12350 #define mmDWB_OGAM_RAMA_END_CNTL1_R                                                                    0x32b4
12351 #define mmDWB_OGAM_RAMA_END_CNTL1_R_BASE_IDX                                                           2
12352 #define mmDWB_OGAM_RAMA_END_CNTL2_R                                                                    0x32b5
12353 #define mmDWB_OGAM_RAMA_END_CNTL2_R_BASE_IDX                                                           2
12354 #define mmDWB_OGAM_RAMA_OFFSET_B                                                                       0x32b6
12355 #define mmDWB_OGAM_RAMA_OFFSET_B_BASE_IDX                                                              2
12356 #define mmDWB_OGAM_RAMA_OFFSET_G                                                                       0x32b7
12357 #define mmDWB_OGAM_RAMA_OFFSET_G_BASE_IDX                                                              2
12358 #define mmDWB_OGAM_RAMA_OFFSET_R                                                                       0x32b8
12359 #define mmDWB_OGAM_RAMA_OFFSET_R_BASE_IDX                                                              2
12360 #define mmDWB_OGAM_RAMA_REGION_0_1                                                                     0x32b9
12361 #define mmDWB_OGAM_RAMA_REGION_0_1_BASE_IDX                                                            2
12362 #define mmDWB_OGAM_RAMA_REGION_2_3                                                                     0x32ba
12363 #define mmDWB_OGAM_RAMA_REGION_2_3_BASE_IDX                                                            2
12364 #define mmDWB_OGAM_RAMA_REGION_4_5                                                                     0x32bb
12365 #define mmDWB_OGAM_RAMA_REGION_4_5_BASE_IDX                                                            2
12366 #define mmDWB_OGAM_RAMA_REGION_6_7                                                                     0x32bc
12367 #define mmDWB_OGAM_RAMA_REGION_6_7_BASE_IDX                                                            2
12368 #define mmDWB_OGAM_RAMA_REGION_8_9                                                                     0x32bd
12369 #define mmDWB_OGAM_RAMA_REGION_8_9_BASE_IDX                                                            2
12370 #define mmDWB_OGAM_RAMA_REGION_10_11                                                                   0x32be
12371 #define mmDWB_OGAM_RAMA_REGION_10_11_BASE_IDX                                                          2
12372 #define mmDWB_OGAM_RAMA_REGION_12_13                                                                   0x32bf
12373 #define mmDWB_OGAM_RAMA_REGION_12_13_BASE_IDX                                                          2
12374 #define mmDWB_OGAM_RAMA_REGION_14_15                                                                   0x32c0
12375 #define mmDWB_OGAM_RAMA_REGION_14_15_BASE_IDX                                                          2
12376 #define mmDWB_OGAM_RAMA_REGION_16_17                                                                   0x32c1
12377 #define mmDWB_OGAM_RAMA_REGION_16_17_BASE_IDX                                                          2
12378 #define mmDWB_OGAM_RAMA_REGION_18_19                                                                   0x32c2
12379 #define mmDWB_OGAM_RAMA_REGION_18_19_BASE_IDX                                                          2
12380 #define mmDWB_OGAM_RAMA_REGION_20_21                                                                   0x32c3
12381 #define mmDWB_OGAM_RAMA_REGION_20_21_BASE_IDX                                                          2
12382 #define mmDWB_OGAM_RAMA_REGION_22_23                                                                   0x32c4
12383 #define mmDWB_OGAM_RAMA_REGION_22_23_BASE_IDX                                                          2
12384 #define mmDWB_OGAM_RAMA_REGION_24_25                                                                   0x32c5
12385 #define mmDWB_OGAM_RAMA_REGION_24_25_BASE_IDX                                                          2
12386 #define mmDWB_OGAM_RAMA_REGION_26_27                                                                   0x32c6
12387 #define mmDWB_OGAM_RAMA_REGION_26_27_BASE_IDX                                                          2
12388 #define mmDWB_OGAM_RAMA_REGION_28_29                                                                   0x32c7
12389 #define mmDWB_OGAM_RAMA_REGION_28_29_BASE_IDX                                                          2
12390 #define mmDWB_OGAM_RAMA_REGION_30_31                                                                   0x32c8
12391 #define mmDWB_OGAM_RAMA_REGION_30_31_BASE_IDX                                                          2
12392 #define mmDWB_OGAM_RAMA_REGION_32_33                                                                   0x32c9
12393 #define mmDWB_OGAM_RAMA_REGION_32_33_BASE_IDX                                                          2
12394 #define mmDWB_OGAM_RAMB_START_CNTL_B                                                                   0x32ca
12395 #define mmDWB_OGAM_RAMB_START_CNTL_B_BASE_IDX                                                          2
12396 #define mmDWB_OGAM_RAMB_START_CNTL_G                                                                   0x32cb
12397 #define mmDWB_OGAM_RAMB_START_CNTL_G_BASE_IDX                                                          2
12398 #define mmDWB_OGAM_RAMB_START_CNTL_R                                                                   0x32cc
12399 #define mmDWB_OGAM_RAMB_START_CNTL_R_BASE_IDX                                                          2
12400 #define mmDWB_OGAM_RAMB_START_BASE_CNTL_B                                                              0x32cd
12401 #define mmDWB_OGAM_RAMB_START_BASE_CNTL_B_BASE_IDX                                                     2
12402 #define mmDWB_OGAM_RAMB_START_SLOPE_CNTL_B                                                             0x32ce
12403 #define mmDWB_OGAM_RAMB_START_SLOPE_CNTL_B_BASE_IDX                                                    2
12404 #define mmDWB_OGAM_RAMB_START_BASE_CNTL_G                                                              0x32cf
12405 #define mmDWB_OGAM_RAMB_START_BASE_CNTL_G_BASE_IDX                                                     2
12406 #define mmDWB_OGAM_RAMB_START_SLOPE_CNTL_G                                                             0x32d0
12407 #define mmDWB_OGAM_RAMB_START_SLOPE_CNTL_G_BASE_IDX                                                    2
12408 #define mmDWB_OGAM_RAMB_START_BASE_CNTL_R                                                              0x32d1
12409 #define mmDWB_OGAM_RAMB_START_BASE_CNTL_R_BASE_IDX                                                     2
12410 #define mmDWB_OGAM_RAMB_START_SLOPE_CNTL_R                                                             0x32d2
12411 #define mmDWB_OGAM_RAMB_START_SLOPE_CNTL_R_BASE_IDX                                                    2
12412 #define mmDWB_OGAM_RAMB_END_CNTL1_B                                                                    0x32d3
12413 #define mmDWB_OGAM_RAMB_END_CNTL1_B_BASE_IDX                                                           2
12414 #define mmDWB_OGAM_RAMB_END_CNTL2_B                                                                    0x32d4
12415 #define mmDWB_OGAM_RAMB_END_CNTL2_B_BASE_IDX                                                           2
12416 #define mmDWB_OGAM_RAMB_END_CNTL1_G                                                                    0x32d5
12417 #define mmDWB_OGAM_RAMB_END_CNTL1_G_BASE_IDX                                                           2
12418 #define mmDWB_OGAM_RAMB_END_CNTL2_G                                                                    0x32d6
12419 #define mmDWB_OGAM_RAMB_END_CNTL2_G_BASE_IDX                                                           2
12420 #define mmDWB_OGAM_RAMB_END_CNTL1_R                                                                    0x32d7
12421 #define mmDWB_OGAM_RAMB_END_CNTL1_R_BASE_IDX                                                           2
12422 #define mmDWB_OGAM_RAMB_END_CNTL2_R                                                                    0x32d8
12423 #define mmDWB_OGAM_RAMB_END_CNTL2_R_BASE_IDX                                                           2
12424 #define mmDWB_OGAM_RAMB_OFFSET_B                                                                       0x32d9
12425 #define mmDWB_OGAM_RAMB_OFFSET_B_BASE_IDX                                                              2
12426 #define mmDWB_OGAM_RAMB_OFFSET_G                                                                       0x32da
12427 #define mmDWB_OGAM_RAMB_OFFSET_G_BASE_IDX                                                              2
12428 #define mmDWB_OGAM_RAMB_OFFSET_R                                                                       0x32db
12429 #define mmDWB_OGAM_RAMB_OFFSET_R_BASE_IDX                                                              2
12430 #define mmDWB_OGAM_RAMB_REGION_0_1                                                                     0x32dc
12431 #define mmDWB_OGAM_RAMB_REGION_0_1_BASE_IDX                                                            2
12432 #define mmDWB_OGAM_RAMB_REGION_2_3                                                                     0x32dd
12433 #define mmDWB_OGAM_RAMB_REGION_2_3_BASE_IDX                                                            2
12434 #define mmDWB_OGAM_RAMB_REGION_4_5                                                                     0x32de
12435 #define mmDWB_OGAM_RAMB_REGION_4_5_BASE_IDX                                                            2
12436 #define mmDWB_OGAM_RAMB_REGION_6_7                                                                     0x32df
12437 #define mmDWB_OGAM_RAMB_REGION_6_7_BASE_IDX                                                            2
12438 #define mmDWB_OGAM_RAMB_REGION_8_9                                                                     0x32e0
12439 #define mmDWB_OGAM_RAMB_REGION_8_9_BASE_IDX                                                            2
12440 #define mmDWB_OGAM_RAMB_REGION_10_11                                                                   0x32e1
12441 #define mmDWB_OGAM_RAMB_REGION_10_11_BASE_IDX                                                          2
12442 #define mmDWB_OGAM_RAMB_REGION_12_13                                                                   0x32e2
12443 #define mmDWB_OGAM_RAMB_REGION_12_13_BASE_IDX                                                          2
12444 #define mmDWB_OGAM_RAMB_REGION_14_15                                                                   0x32e3
12445 #define mmDWB_OGAM_RAMB_REGION_14_15_BASE_IDX                                                          2
12446 #define mmDWB_OGAM_RAMB_REGION_16_17                                                                   0x32e4
12447 #define mmDWB_OGAM_RAMB_REGION_16_17_BASE_IDX                                                          2
12448 #define mmDWB_OGAM_RAMB_REGION_18_19                                                                   0x32e5
12449 #define mmDWB_OGAM_RAMB_REGION_18_19_BASE_IDX                                                          2
12450 #define mmDWB_OGAM_RAMB_REGION_20_21                                                                   0x32e6
12451 #define mmDWB_OGAM_RAMB_REGION_20_21_BASE_IDX                                                          2
12452 #define mmDWB_OGAM_RAMB_REGION_22_23                                                                   0x32e7
12453 #define mmDWB_OGAM_RAMB_REGION_22_23_BASE_IDX                                                          2
12454 #define mmDWB_OGAM_RAMB_REGION_24_25                                                                   0x32e8
12455 #define mmDWB_OGAM_RAMB_REGION_24_25_BASE_IDX                                                          2
12456 #define mmDWB_OGAM_RAMB_REGION_26_27                                                                   0x32e9
12457 #define mmDWB_OGAM_RAMB_REGION_26_27_BASE_IDX                                                          2
12458 #define mmDWB_OGAM_RAMB_REGION_28_29                                                                   0x32ea
12459 #define mmDWB_OGAM_RAMB_REGION_28_29_BASE_IDX                                                          2
12460 #define mmDWB_OGAM_RAMB_REGION_30_31                                                                   0x32eb
12461 #define mmDWB_OGAM_RAMB_REGION_30_31_BASE_IDX                                                          2
12462 #define mmDWB_OGAM_RAMB_REGION_32_33                                                                   0x32ec
12463 #define mmDWB_OGAM_RAMB_REGION_32_33_BASE_IDX                                                          2
12464 
12465 
12466 // addressBlock: dce_dc_mpc_mpcc0_dispdec
12467 // base address: 0x0
12468 #define mmMPCC0_MPCC_TOP_SEL                                                                           0x0000
12469 #define mmMPCC0_MPCC_TOP_SEL_BASE_IDX                                                                  3
12470 #define mmMPCC0_MPCC_BOT_SEL                                                                           0x0001
12471 #define mmMPCC0_MPCC_BOT_SEL_BASE_IDX                                                                  3
12472 #define mmMPCC0_MPCC_OPP_ID                                                                            0x0002
12473 #define mmMPCC0_MPCC_OPP_ID_BASE_IDX                                                                   3
12474 #define mmMPCC0_MPCC_CONTROL                                                                           0x0003
12475 #define mmMPCC0_MPCC_CONTROL_BASE_IDX                                                                  3
12476 #define mmMPCC0_MPCC_SM_CONTROL                                                                        0x0004
12477 #define mmMPCC0_MPCC_SM_CONTROL_BASE_IDX                                                               3
12478 #define mmMPCC0_MPCC_UPDATE_LOCK_SEL                                                                   0x0005
12479 #define mmMPCC0_MPCC_UPDATE_LOCK_SEL_BASE_IDX                                                          3
12480 #define mmMPCC0_MPCC_TOP_GAIN                                                                          0x0006
12481 #define mmMPCC0_MPCC_TOP_GAIN_BASE_IDX                                                                 3
12482 #define mmMPCC0_MPCC_BOT_GAIN_INSIDE                                                                   0x0007
12483 #define mmMPCC0_MPCC_BOT_GAIN_INSIDE_BASE_IDX                                                          3
12484 #define mmMPCC0_MPCC_BOT_GAIN_OUTSIDE                                                                  0x0008
12485 #define mmMPCC0_MPCC_BOT_GAIN_OUTSIDE_BASE_IDX                                                         3
12486 #define mmMPCC0_MPCC_BG_R_CR                                                                           0x0009
12487 #define mmMPCC0_MPCC_BG_R_CR_BASE_IDX                                                                  3
12488 #define mmMPCC0_MPCC_BG_G_Y                                                                            0x000a
12489 #define mmMPCC0_MPCC_BG_G_Y_BASE_IDX                                                                   3
12490 #define mmMPCC0_MPCC_BG_B_CB                                                                           0x000b
12491 #define mmMPCC0_MPCC_BG_B_CB_BASE_IDX                                                                  3
12492 #define mmMPCC0_MPCC_MEM_PWR_CTRL                                                                      0x000c
12493 #define mmMPCC0_MPCC_MEM_PWR_CTRL_BASE_IDX                                                             3
12494 #define mmMPCC0_MPCC_STATUS                                                                            0x000d
12495 #define mmMPCC0_MPCC_STATUS_BASE_IDX                                                                   3
12496 
12497 
12498 // addressBlock: dce_dc_mpc_mpcc1_dispdec
12499 // base address: 0x80
12500 #define mmMPCC1_MPCC_TOP_SEL                                                                           0x0020
12501 #define mmMPCC1_MPCC_TOP_SEL_BASE_IDX                                                                  3
12502 #define mmMPCC1_MPCC_BOT_SEL                                                                           0x0021
12503 #define mmMPCC1_MPCC_BOT_SEL_BASE_IDX                                                                  3
12504 #define mmMPCC1_MPCC_OPP_ID                                                                            0x0022
12505 #define mmMPCC1_MPCC_OPP_ID_BASE_IDX                                                                   3
12506 #define mmMPCC1_MPCC_CONTROL                                                                           0x0023
12507 #define mmMPCC1_MPCC_CONTROL_BASE_IDX                                                                  3
12508 #define mmMPCC1_MPCC_SM_CONTROL                                                                        0x0024
12509 #define mmMPCC1_MPCC_SM_CONTROL_BASE_IDX                                                               3
12510 #define mmMPCC1_MPCC_UPDATE_LOCK_SEL                                                                   0x0025
12511 #define mmMPCC1_MPCC_UPDATE_LOCK_SEL_BASE_IDX                                                          3
12512 #define mmMPCC1_MPCC_TOP_GAIN                                                                          0x0026
12513 #define mmMPCC1_MPCC_TOP_GAIN_BASE_IDX                                                                 3
12514 #define mmMPCC1_MPCC_BOT_GAIN_INSIDE                                                                   0x0027
12515 #define mmMPCC1_MPCC_BOT_GAIN_INSIDE_BASE_IDX                                                          3
12516 #define mmMPCC1_MPCC_BOT_GAIN_OUTSIDE                                                                  0x0028
12517 #define mmMPCC1_MPCC_BOT_GAIN_OUTSIDE_BASE_IDX                                                         3
12518 #define mmMPCC1_MPCC_BG_R_CR                                                                           0x0029
12519 #define mmMPCC1_MPCC_BG_R_CR_BASE_IDX                                                                  3
12520 #define mmMPCC1_MPCC_BG_G_Y                                                                            0x002a
12521 #define mmMPCC1_MPCC_BG_G_Y_BASE_IDX                                                                   3
12522 #define mmMPCC1_MPCC_BG_B_CB                                                                           0x002b
12523 #define mmMPCC1_MPCC_BG_B_CB_BASE_IDX                                                                  3
12524 #define mmMPCC1_MPCC_MEM_PWR_CTRL                                                                      0x002c
12525 #define mmMPCC1_MPCC_MEM_PWR_CTRL_BASE_IDX                                                             3
12526 #define mmMPCC1_MPCC_STATUS                                                                            0x002d
12527 #define mmMPCC1_MPCC_STATUS_BASE_IDX                                                                   3
12528 
12529 
12530 // addressBlock: dce_dc_mpc_mpcc2_dispdec
12531 // base address: 0x100
12532 #define mmMPCC2_MPCC_TOP_SEL                                                                           0x0040
12533 #define mmMPCC2_MPCC_TOP_SEL_BASE_IDX                                                                  3
12534 #define mmMPCC2_MPCC_BOT_SEL                                                                           0x0041
12535 #define mmMPCC2_MPCC_BOT_SEL_BASE_IDX                                                                  3
12536 #define mmMPCC2_MPCC_OPP_ID                                                                            0x0042
12537 #define mmMPCC2_MPCC_OPP_ID_BASE_IDX                                                                   3
12538 #define mmMPCC2_MPCC_CONTROL                                                                           0x0043
12539 #define mmMPCC2_MPCC_CONTROL_BASE_IDX                                                                  3
12540 #define mmMPCC2_MPCC_SM_CONTROL                                                                        0x0044
12541 #define mmMPCC2_MPCC_SM_CONTROL_BASE_IDX                                                               3
12542 #define mmMPCC2_MPCC_UPDATE_LOCK_SEL                                                                   0x0045
12543 #define mmMPCC2_MPCC_UPDATE_LOCK_SEL_BASE_IDX                                                          3
12544 #define mmMPCC2_MPCC_TOP_GAIN                                                                          0x0046
12545 #define mmMPCC2_MPCC_TOP_GAIN_BASE_IDX                                                                 3
12546 #define mmMPCC2_MPCC_BOT_GAIN_INSIDE                                                                   0x0047
12547 #define mmMPCC2_MPCC_BOT_GAIN_INSIDE_BASE_IDX                                                          3
12548 #define mmMPCC2_MPCC_BOT_GAIN_OUTSIDE                                                                  0x0048
12549 #define mmMPCC2_MPCC_BOT_GAIN_OUTSIDE_BASE_IDX                                                         3
12550 #define mmMPCC2_MPCC_BG_R_CR                                                                           0x0049
12551 #define mmMPCC2_MPCC_BG_R_CR_BASE_IDX                                                                  3
12552 #define mmMPCC2_MPCC_BG_G_Y                                                                            0x004a
12553 #define mmMPCC2_MPCC_BG_G_Y_BASE_IDX                                                                   3
12554 #define mmMPCC2_MPCC_BG_B_CB                                                                           0x004b
12555 #define mmMPCC2_MPCC_BG_B_CB_BASE_IDX                                                                  3
12556 #define mmMPCC2_MPCC_MEM_PWR_CTRL                                                                      0x004c
12557 #define mmMPCC2_MPCC_MEM_PWR_CTRL_BASE_IDX                                                             3
12558 #define mmMPCC2_MPCC_STATUS                                                                            0x004d
12559 #define mmMPCC2_MPCC_STATUS_BASE_IDX                                                                   3
12560 
12561 
12562 // addressBlock: dce_dc_mpc_mpcc3_dispdec
12563 // base address: 0x180
12564 #define mmMPCC3_MPCC_TOP_SEL                                                                           0x0060
12565 #define mmMPCC3_MPCC_TOP_SEL_BASE_IDX                                                                  3
12566 #define mmMPCC3_MPCC_BOT_SEL                                                                           0x0061
12567 #define mmMPCC3_MPCC_BOT_SEL_BASE_IDX                                                                  3
12568 #define mmMPCC3_MPCC_OPP_ID                                                                            0x0062
12569 #define mmMPCC3_MPCC_OPP_ID_BASE_IDX                                                                   3
12570 #define mmMPCC3_MPCC_CONTROL                                                                           0x0063
12571 #define mmMPCC3_MPCC_CONTROL_BASE_IDX                                                                  3
12572 #define mmMPCC3_MPCC_SM_CONTROL                                                                        0x0064
12573 #define mmMPCC3_MPCC_SM_CONTROL_BASE_IDX                                                               3
12574 #define mmMPCC3_MPCC_UPDATE_LOCK_SEL                                                                   0x0065
12575 #define mmMPCC3_MPCC_UPDATE_LOCK_SEL_BASE_IDX                                                          3
12576 #define mmMPCC3_MPCC_TOP_GAIN                                                                          0x0066
12577 #define mmMPCC3_MPCC_TOP_GAIN_BASE_IDX                                                                 3
12578 #define mmMPCC3_MPCC_BOT_GAIN_INSIDE                                                                   0x0067
12579 #define mmMPCC3_MPCC_BOT_GAIN_INSIDE_BASE_IDX                                                          3
12580 #define mmMPCC3_MPCC_BOT_GAIN_OUTSIDE                                                                  0x0068
12581 #define mmMPCC3_MPCC_BOT_GAIN_OUTSIDE_BASE_IDX                                                         3
12582 #define mmMPCC3_MPCC_BG_R_CR                                                                           0x0069
12583 #define mmMPCC3_MPCC_BG_R_CR_BASE_IDX                                                                  3
12584 #define mmMPCC3_MPCC_BG_G_Y                                                                            0x006a
12585 #define mmMPCC3_MPCC_BG_G_Y_BASE_IDX                                                                   3
12586 #define mmMPCC3_MPCC_BG_B_CB                                                                           0x006b
12587 #define mmMPCC3_MPCC_BG_B_CB_BASE_IDX                                                                  3
12588 #define mmMPCC3_MPCC_MEM_PWR_CTRL                                                                      0x006c
12589 #define mmMPCC3_MPCC_MEM_PWR_CTRL_BASE_IDX                                                             3
12590 #define mmMPCC3_MPCC_STATUS                                                                            0x006d
12591 #define mmMPCC3_MPCC_STATUS_BASE_IDX                                                                   3
12592 
12593 
12594 // addressBlock: dce_dc_mpc_mpcc4_dispdec
12595 // base address: 0x200
12596 #define mmMPCC4_MPCC_TOP_SEL                                                                           0x0080
12597 #define mmMPCC4_MPCC_TOP_SEL_BASE_IDX                                                                  3
12598 #define mmMPCC4_MPCC_BOT_SEL                                                                           0x0081
12599 #define mmMPCC4_MPCC_BOT_SEL_BASE_IDX                                                                  3
12600 #define mmMPCC4_MPCC_OPP_ID                                                                            0x0082
12601 #define mmMPCC4_MPCC_OPP_ID_BASE_IDX                                                                   3
12602 #define mmMPCC4_MPCC_CONTROL                                                                           0x0083
12603 #define mmMPCC4_MPCC_CONTROL_BASE_IDX                                                                  3
12604 #define mmMPCC4_MPCC_SM_CONTROL                                                                        0x0084
12605 #define mmMPCC4_MPCC_SM_CONTROL_BASE_IDX                                                               3
12606 #define mmMPCC4_MPCC_UPDATE_LOCK_SEL                                                                   0x0085
12607 #define mmMPCC4_MPCC_UPDATE_LOCK_SEL_BASE_IDX                                                          3
12608 #define mmMPCC4_MPCC_TOP_GAIN                                                                          0x0086
12609 #define mmMPCC4_MPCC_TOP_GAIN_BASE_IDX                                                                 3
12610 #define mmMPCC4_MPCC_BOT_GAIN_INSIDE                                                                   0x0087
12611 #define mmMPCC4_MPCC_BOT_GAIN_INSIDE_BASE_IDX                                                          3
12612 #define mmMPCC4_MPCC_BOT_GAIN_OUTSIDE                                                                  0x0088
12613 #define mmMPCC4_MPCC_BOT_GAIN_OUTSIDE_BASE_IDX                                                         3
12614 #define mmMPCC4_MPCC_BG_R_CR                                                                           0x0089
12615 #define mmMPCC4_MPCC_BG_R_CR_BASE_IDX                                                                  3
12616 #define mmMPCC4_MPCC_BG_G_Y                                                                            0x008a
12617 #define mmMPCC4_MPCC_BG_G_Y_BASE_IDX                                                                   3
12618 #define mmMPCC4_MPCC_BG_B_CB                                                                           0x008b
12619 #define mmMPCC4_MPCC_BG_B_CB_BASE_IDX                                                                  3
12620 #define mmMPCC4_MPCC_MEM_PWR_CTRL                                                                      0x008c
12621 #define mmMPCC4_MPCC_MEM_PWR_CTRL_BASE_IDX                                                             3
12622 #define mmMPCC4_MPCC_STATUS                                                                            0x008d
12623 #define mmMPCC4_MPCC_STATUS_BASE_IDX                                                                   3
12624 
12625 
12626 // addressBlock: dce_dc_mpc_mpcc_ogam0_dispdec
12627 // base address: 0x0
12628 #define mmMPCC_OGAM0_MPCC_OGAM_CONTROL                                                                 0x0100
12629 #define mmMPCC_OGAM0_MPCC_OGAM_CONTROL_BASE_IDX                                                        3
12630 #define mmMPCC_OGAM0_MPCC_OGAM_LUT_INDEX                                                               0x0101
12631 #define mmMPCC_OGAM0_MPCC_OGAM_LUT_INDEX_BASE_IDX                                                      3
12632 #define mmMPCC_OGAM0_MPCC_OGAM_LUT_DATA                                                                0x0102
12633 #define mmMPCC_OGAM0_MPCC_OGAM_LUT_DATA_BASE_IDX                                                       3
12634 #define mmMPCC_OGAM0_MPCC_OGAM_LUT_CONTROL                                                             0x0103
12635 #define mmMPCC_OGAM0_MPCC_OGAM_LUT_CONTROL_BASE_IDX                                                    3
12636 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_B                                                       0x0104
12637 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_B_BASE_IDX                                              3
12638 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_G                                                       0x0105
12639 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_G_BASE_IDX                                              3
12640 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_R                                                       0x0106
12641 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_R_BASE_IDX                                              3
12642 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B                                                 0x0107
12643 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B_BASE_IDX                                        3
12644 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G                                                 0x0108
12645 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G_BASE_IDX                                        3
12646 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R                                                 0x0109
12647 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R_BASE_IDX                                        3
12648 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_B                                                  0x010a
12649 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_B_BASE_IDX                                         3
12650 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_G                                                  0x010b
12651 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_G_BASE_IDX                                         3
12652 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_R                                                  0x010c
12653 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_R_BASE_IDX                                         3
12654 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_B                                                        0x010d
12655 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_B_BASE_IDX                                               3
12656 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_B                                                        0x010e
12657 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_B_BASE_IDX                                               3
12658 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_G                                                        0x010f
12659 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_G_BASE_IDX                                               3
12660 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_G                                                        0x0110
12661 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_G_BASE_IDX                                               3
12662 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_R                                                        0x0111
12663 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_R_BASE_IDX                                               3
12664 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_R                                                        0x0112
12665 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_R_BASE_IDX                                               3
12666 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_B                                                           0x0113
12667 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_B_BASE_IDX                                                  3
12668 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_G                                                           0x0114
12669 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_G_BASE_IDX                                                  3
12670 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_R                                                           0x0115
12671 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_R_BASE_IDX                                                  3
12672 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1                                                         0x0116
12673 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1_BASE_IDX                                                3
12674 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_2_3                                                         0x0117
12675 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_2_3_BASE_IDX                                                3
12676 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_4_5                                                         0x0118
12677 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_4_5_BASE_IDX                                                3
12678 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_6_7                                                         0x0119
12679 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_6_7_BASE_IDX                                                3
12680 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_8_9                                                         0x011a
12681 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_8_9_BASE_IDX                                                3
12682 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_10_11                                                       0x011b
12683 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_10_11_BASE_IDX                                              3
12684 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_12_13                                                       0x011c
12685 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_12_13_BASE_IDX                                              3
12686 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_14_15                                                       0x011d
12687 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_14_15_BASE_IDX                                              3
12688 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_16_17                                                       0x011e
12689 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_16_17_BASE_IDX                                              3
12690 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_18_19                                                       0x011f
12691 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_18_19_BASE_IDX                                              3
12692 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_20_21                                                       0x0120
12693 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_20_21_BASE_IDX                                              3
12694 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_22_23                                                       0x0121
12695 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_22_23_BASE_IDX                                              3
12696 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_24_25                                                       0x0122
12697 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_24_25_BASE_IDX                                              3
12698 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_26_27                                                       0x0123
12699 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_26_27_BASE_IDX                                              3
12700 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_28_29                                                       0x0124
12701 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_28_29_BASE_IDX                                              3
12702 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_30_31                                                       0x0125
12703 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_30_31_BASE_IDX                                              3
12704 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_32_33                                                       0x0126
12705 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_32_33_BASE_IDX                                              3
12706 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_B                                                       0x0127
12707 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_B_BASE_IDX                                              3
12708 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_G                                                       0x0128
12709 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_G_BASE_IDX                                              3
12710 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_R                                                       0x0129
12711 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_R_BASE_IDX                                              3
12712 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B                                                 0x012a
12713 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B_BASE_IDX                                        3
12714 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G                                                 0x012b
12715 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G_BASE_IDX                                        3
12716 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R                                                 0x012c
12717 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R_BASE_IDX                                        3
12718 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_B                                                  0x012d
12719 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_B_BASE_IDX                                         3
12720 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_G                                                  0x012e
12721 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_G_BASE_IDX                                         3
12722 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_R                                                  0x012f
12723 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_R_BASE_IDX                                         3
12724 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_B                                                        0x0130
12725 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_B_BASE_IDX                                               3
12726 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_B                                                        0x0131
12727 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_B_BASE_IDX                                               3
12728 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_G                                                        0x0132
12729 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_G_BASE_IDX                                               3
12730 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_G                                                        0x0133
12731 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_G_BASE_IDX                                               3
12732 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_R                                                        0x0134
12733 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_R_BASE_IDX                                               3
12734 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_R                                                        0x0135
12735 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_R_BASE_IDX                                               3
12736 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_B                                                           0x0136
12737 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_B_BASE_IDX                                                  3
12738 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_G                                                           0x0137
12739 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_G_BASE_IDX                                                  3
12740 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_R                                                           0x0138
12741 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_R_BASE_IDX                                                  3
12742 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1                                                         0x0139
12743 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1_BASE_IDX                                                3
12744 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_2_3                                                         0x013a
12745 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_2_3_BASE_IDX                                                3
12746 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_4_5                                                         0x013b
12747 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_4_5_BASE_IDX                                                3
12748 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_6_7                                                         0x013c
12749 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_6_7_BASE_IDX                                                3
12750 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_8_9                                                         0x013d
12751 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_8_9_BASE_IDX                                                3
12752 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_10_11                                                       0x013e
12753 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_10_11_BASE_IDX                                              3
12754 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_12_13                                                       0x013f
12755 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_12_13_BASE_IDX                                              3
12756 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_14_15                                                       0x0140
12757 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_14_15_BASE_IDX                                              3
12758 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_16_17                                                       0x0141
12759 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_16_17_BASE_IDX                                              3
12760 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_18_19                                                       0x0142
12761 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_18_19_BASE_IDX                                              3
12762 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_20_21                                                       0x0143
12763 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_20_21_BASE_IDX                                              3
12764 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_22_23                                                       0x0144
12765 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_22_23_BASE_IDX                                              3
12766 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_24_25                                                       0x0145
12767 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_24_25_BASE_IDX                                              3
12768 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_26_27                                                       0x0146
12769 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_26_27_BASE_IDX                                              3
12770 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_28_29                                                       0x0147
12771 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_28_29_BASE_IDX                                              3
12772 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_30_31                                                       0x0148
12773 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_30_31_BASE_IDX                                              3
12774 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_32_33                                                       0x0149
12775 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_32_33_BASE_IDX                                              3
12776 #define mmMPCC_OGAM0_MPCC_GAMUT_REMAP_COEF_FORMAT                                                      0x014a
12777 #define mmMPCC_OGAM0_MPCC_GAMUT_REMAP_COEF_FORMAT_BASE_IDX                                             3
12778 #define mmMPCC_OGAM0_MPCC_GAMUT_REMAP_MODE                                                             0x014b
12779 #define mmMPCC_OGAM0_MPCC_GAMUT_REMAP_MODE_BASE_IDX                                                    3
12780 #define mmMPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_A                                                         0x014c
12781 #define mmMPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_A_BASE_IDX                                                3
12782 #define mmMPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_A                                                         0x014d
12783 #define mmMPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_A_BASE_IDX                                                3
12784 #define mmMPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_A                                                         0x014e
12785 #define mmMPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_A_BASE_IDX                                                3
12786 #define mmMPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_A                                                         0x014f
12787 #define mmMPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_A_BASE_IDX                                                3
12788 #define mmMPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_A                                                         0x0150
12789 #define mmMPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_A_BASE_IDX                                                3
12790 #define mmMPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_A                                                         0x0151
12791 #define mmMPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_A_BASE_IDX                                                3
12792 #define mmMPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_B                                                         0x0152
12793 #define mmMPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_B_BASE_IDX                                                3
12794 #define mmMPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_B                                                         0x0153
12795 #define mmMPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_B_BASE_IDX                                                3
12796 #define mmMPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_B                                                         0x0154
12797 #define mmMPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_B_BASE_IDX                                                3
12798 #define mmMPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_B                                                         0x0155
12799 #define mmMPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_B_BASE_IDX                                                3
12800 #define mmMPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_B                                                         0x0156
12801 #define mmMPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_B_BASE_IDX                                                3
12802 #define mmMPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_B                                                         0x0157
12803 #define mmMPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_B_BASE_IDX                                                3
12804 
12805 
12806 // addressBlock: dce_dc_mpc_mpcc_ogam1_dispdec
12807 // base address: 0x200
12808 #define mmMPCC_OGAM1_MPCC_OGAM_CONTROL                                                                 0x0180
12809 #define mmMPCC_OGAM1_MPCC_OGAM_CONTROL_BASE_IDX                                                        3
12810 #define mmMPCC_OGAM1_MPCC_OGAM_LUT_INDEX                                                               0x0181
12811 #define mmMPCC_OGAM1_MPCC_OGAM_LUT_INDEX_BASE_IDX                                                      3
12812 #define mmMPCC_OGAM1_MPCC_OGAM_LUT_DATA                                                                0x0182
12813 #define mmMPCC_OGAM1_MPCC_OGAM_LUT_DATA_BASE_IDX                                                       3
12814 #define mmMPCC_OGAM1_MPCC_OGAM_LUT_CONTROL                                                             0x0183
12815 #define mmMPCC_OGAM1_MPCC_OGAM_LUT_CONTROL_BASE_IDX                                                    3
12816 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_B                                                       0x0184
12817 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_B_BASE_IDX                                              3
12818 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_G                                                       0x0185
12819 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_G_BASE_IDX                                              3
12820 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_R                                                       0x0186
12821 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_R_BASE_IDX                                              3
12822 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B                                                 0x0187
12823 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B_BASE_IDX                                        3
12824 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G                                                 0x0188
12825 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G_BASE_IDX                                        3
12826 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R                                                 0x0189
12827 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R_BASE_IDX                                        3
12828 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_B                                                  0x018a
12829 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_B_BASE_IDX                                         3
12830 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_G                                                  0x018b
12831 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_G_BASE_IDX                                         3
12832 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_R                                                  0x018c
12833 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_R_BASE_IDX                                         3
12834 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_B                                                        0x018d
12835 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_B_BASE_IDX                                               3
12836 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_B                                                        0x018e
12837 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_B_BASE_IDX                                               3
12838 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_G                                                        0x018f
12839 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_G_BASE_IDX                                               3
12840 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_G                                                        0x0190
12841 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_G_BASE_IDX                                               3
12842 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_R                                                        0x0191
12843 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_R_BASE_IDX                                               3
12844 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_R                                                        0x0192
12845 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_R_BASE_IDX                                               3
12846 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_B                                                           0x0193
12847 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_B_BASE_IDX                                                  3
12848 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_G                                                           0x0194
12849 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_G_BASE_IDX                                                  3
12850 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_R                                                           0x0195
12851 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_R_BASE_IDX                                                  3
12852 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_0_1                                                         0x0196
12853 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_0_1_BASE_IDX                                                3
12854 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_2_3                                                         0x0197
12855 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_2_3_BASE_IDX                                                3
12856 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_4_5                                                         0x0198
12857 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_4_5_BASE_IDX                                                3
12858 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_6_7                                                         0x0199
12859 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_6_7_BASE_IDX                                                3
12860 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_8_9                                                         0x019a
12861 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_8_9_BASE_IDX                                                3
12862 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_10_11                                                       0x019b
12863 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_10_11_BASE_IDX                                              3
12864 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_12_13                                                       0x019c
12865 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_12_13_BASE_IDX                                              3
12866 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_14_15                                                       0x019d
12867 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_14_15_BASE_IDX                                              3
12868 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_16_17                                                       0x019e
12869 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_16_17_BASE_IDX                                              3
12870 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_18_19                                                       0x019f
12871 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_18_19_BASE_IDX                                              3
12872 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_20_21                                                       0x01a0
12873 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_20_21_BASE_IDX                                              3
12874 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_22_23                                                       0x01a1
12875 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_22_23_BASE_IDX                                              3
12876 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_24_25                                                       0x01a2
12877 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_24_25_BASE_IDX                                              3
12878 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_26_27                                                       0x01a3
12879 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_26_27_BASE_IDX                                              3
12880 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_28_29                                                       0x01a4
12881 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_28_29_BASE_IDX                                              3
12882 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_30_31                                                       0x01a5
12883 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_30_31_BASE_IDX                                              3
12884 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_32_33                                                       0x01a6
12885 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_32_33_BASE_IDX                                              3
12886 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_B                                                       0x01a7
12887 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_B_BASE_IDX                                              3
12888 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_G                                                       0x01a8
12889 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_G_BASE_IDX                                              3
12890 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_R                                                       0x01a9
12891 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_R_BASE_IDX                                              3
12892 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B                                                 0x01aa
12893 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B_BASE_IDX                                        3
12894 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G                                                 0x01ab
12895 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G_BASE_IDX                                        3
12896 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R                                                 0x01ac
12897 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R_BASE_IDX                                        3
12898 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_B                                                  0x01ad
12899 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_B_BASE_IDX                                         3
12900 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_G                                                  0x01ae
12901 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_G_BASE_IDX                                         3
12902 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_R                                                  0x01af
12903 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_R_BASE_IDX                                         3
12904 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_B                                                        0x01b0
12905 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_B_BASE_IDX                                               3
12906 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_B                                                        0x01b1
12907 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_B_BASE_IDX                                               3
12908 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_G                                                        0x01b2
12909 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_G_BASE_IDX                                               3
12910 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_G                                                        0x01b3
12911 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_G_BASE_IDX                                               3
12912 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_R                                                        0x01b4
12913 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_R_BASE_IDX                                               3
12914 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_R                                                        0x01b5
12915 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_R_BASE_IDX                                               3
12916 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_B                                                           0x01b6
12917 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_B_BASE_IDX                                                  3
12918 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_G                                                           0x01b7
12919 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_G_BASE_IDX                                                  3
12920 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_R                                                           0x01b8
12921 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_R_BASE_IDX                                                  3
12922 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_0_1                                                         0x01b9
12923 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_0_1_BASE_IDX                                                3
12924 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_2_3                                                         0x01ba
12925 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_2_3_BASE_IDX                                                3
12926 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_4_5                                                         0x01bb
12927 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_4_5_BASE_IDX                                                3
12928 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_6_7                                                         0x01bc
12929 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_6_7_BASE_IDX                                                3
12930 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_8_9                                                         0x01bd
12931 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_8_9_BASE_IDX                                                3
12932 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_10_11                                                       0x01be
12933 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_10_11_BASE_IDX                                              3
12934 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_12_13                                                       0x01bf
12935 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_12_13_BASE_IDX                                              3
12936 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_14_15                                                       0x01c0
12937 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_14_15_BASE_IDX                                              3
12938 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_16_17                                                       0x01c1
12939 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_16_17_BASE_IDX                                              3
12940 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_18_19                                                       0x01c2
12941 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_18_19_BASE_IDX                                              3
12942 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_20_21                                                       0x01c3
12943 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_20_21_BASE_IDX                                              3
12944 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_22_23                                                       0x01c4
12945 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_22_23_BASE_IDX                                              3
12946 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_24_25                                                       0x01c5
12947 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_24_25_BASE_IDX                                              3
12948 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_26_27                                                       0x01c6
12949 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_26_27_BASE_IDX                                              3
12950 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_28_29                                                       0x01c7
12951 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_28_29_BASE_IDX                                              3
12952 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_30_31                                                       0x01c8
12953 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_30_31_BASE_IDX                                              3
12954 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_32_33                                                       0x01c9
12955 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_32_33_BASE_IDX                                              3
12956 #define mmMPCC_OGAM1_MPCC_GAMUT_REMAP_COEF_FORMAT                                                      0x01ca
12957 #define mmMPCC_OGAM1_MPCC_GAMUT_REMAP_COEF_FORMAT_BASE_IDX                                             3
12958 #define mmMPCC_OGAM1_MPCC_GAMUT_REMAP_MODE                                                             0x01cb
12959 #define mmMPCC_OGAM1_MPCC_GAMUT_REMAP_MODE_BASE_IDX                                                    3
12960 #define mmMPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_A                                                         0x01cc
12961 #define mmMPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_A_BASE_IDX                                                3
12962 #define mmMPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_A                                                         0x01cd
12963 #define mmMPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_A_BASE_IDX                                                3
12964 #define mmMPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_A                                                         0x01ce
12965 #define mmMPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_A_BASE_IDX                                                3
12966 #define mmMPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_A                                                         0x01cf
12967 #define mmMPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_A_BASE_IDX                                                3
12968 #define mmMPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_A                                                         0x01d0
12969 #define mmMPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_A_BASE_IDX                                                3
12970 #define mmMPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_A                                                         0x01d1
12971 #define mmMPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_A_BASE_IDX                                                3
12972 #define mmMPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_B                                                         0x01d2
12973 #define mmMPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_B_BASE_IDX                                                3
12974 #define mmMPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_B                                                         0x01d3
12975 #define mmMPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_B_BASE_IDX                                                3
12976 #define mmMPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_B                                                         0x01d4
12977 #define mmMPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_B_BASE_IDX                                                3
12978 #define mmMPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_B                                                         0x01d5
12979 #define mmMPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_B_BASE_IDX                                                3
12980 #define mmMPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_B                                                         0x01d6
12981 #define mmMPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_B_BASE_IDX                                                3
12982 #define mmMPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_B                                                         0x01d7
12983 #define mmMPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_B_BASE_IDX                                                3
12984 
12985 
12986 // addressBlock: dce_dc_mpc_mpcc_ogam2_dispdec
12987 // base address: 0x400
12988 #define mmMPCC_OGAM2_MPCC_OGAM_CONTROL                                                                 0x0200
12989 #define mmMPCC_OGAM2_MPCC_OGAM_CONTROL_BASE_IDX                                                        3
12990 #define mmMPCC_OGAM2_MPCC_OGAM_LUT_INDEX                                                               0x0201
12991 #define mmMPCC_OGAM2_MPCC_OGAM_LUT_INDEX_BASE_IDX                                                      3
12992 #define mmMPCC_OGAM2_MPCC_OGAM_LUT_DATA                                                                0x0202
12993 #define mmMPCC_OGAM2_MPCC_OGAM_LUT_DATA_BASE_IDX                                                       3
12994 #define mmMPCC_OGAM2_MPCC_OGAM_LUT_CONTROL                                                             0x0203
12995 #define mmMPCC_OGAM2_MPCC_OGAM_LUT_CONTROL_BASE_IDX                                                    3
12996 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_B                                                       0x0204
12997 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_B_BASE_IDX                                              3
12998 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_G                                                       0x0205
12999 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_G_BASE_IDX                                              3
13000 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_R                                                       0x0206
13001 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_R_BASE_IDX                                              3
13002 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B                                                 0x0207
13003 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B_BASE_IDX                                        3
13004 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G                                                 0x0208
13005 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G_BASE_IDX                                        3
13006 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R                                                 0x0209
13007 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R_BASE_IDX                                        3
13008 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_B                                                  0x020a
13009 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_B_BASE_IDX                                         3
13010 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_G                                                  0x020b
13011 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_G_BASE_IDX                                         3
13012 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_R                                                  0x020c
13013 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_R_BASE_IDX                                         3
13014 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_B                                                        0x020d
13015 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_B_BASE_IDX                                               3
13016 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_B                                                        0x020e
13017 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_B_BASE_IDX                                               3
13018 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_G                                                        0x020f
13019 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_G_BASE_IDX                                               3
13020 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_G                                                        0x0210
13021 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_G_BASE_IDX                                               3
13022 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_R                                                        0x0211
13023 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_R_BASE_IDX                                               3
13024 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_R                                                        0x0212
13025 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_R_BASE_IDX                                               3
13026 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_B                                                           0x0213
13027 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_B_BASE_IDX                                                  3
13028 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_G                                                           0x0214
13029 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_G_BASE_IDX                                                  3
13030 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_R                                                           0x0215
13031 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_R_BASE_IDX                                                  3
13032 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_0_1                                                         0x0216
13033 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_0_1_BASE_IDX                                                3
13034 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_2_3                                                         0x0217
13035 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_2_3_BASE_IDX                                                3
13036 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_4_5                                                         0x0218
13037 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_4_5_BASE_IDX                                                3
13038 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_6_7                                                         0x0219
13039 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_6_7_BASE_IDX                                                3
13040 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_8_9                                                         0x021a
13041 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_8_9_BASE_IDX                                                3
13042 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_10_11                                                       0x021b
13043 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_10_11_BASE_IDX                                              3
13044 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_12_13                                                       0x021c
13045 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_12_13_BASE_IDX                                              3
13046 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_14_15                                                       0x021d
13047 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_14_15_BASE_IDX                                              3
13048 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_16_17                                                       0x021e
13049 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_16_17_BASE_IDX                                              3
13050 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_18_19                                                       0x021f
13051 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_18_19_BASE_IDX                                              3
13052 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_20_21                                                       0x0220
13053 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_20_21_BASE_IDX                                              3
13054 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_22_23                                                       0x0221
13055 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_22_23_BASE_IDX                                              3
13056 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_24_25                                                       0x0222
13057 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_24_25_BASE_IDX                                              3
13058 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_26_27                                                       0x0223
13059 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_26_27_BASE_IDX                                              3
13060 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_28_29                                                       0x0224
13061 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_28_29_BASE_IDX                                              3
13062 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_30_31                                                       0x0225
13063 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_30_31_BASE_IDX                                              3
13064 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_32_33                                                       0x0226
13065 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_32_33_BASE_IDX                                              3
13066 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_B                                                       0x0227
13067 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_B_BASE_IDX                                              3
13068 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_G                                                       0x0228
13069 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_G_BASE_IDX                                              3
13070 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_R                                                       0x0229
13071 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_R_BASE_IDX                                              3
13072 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B                                                 0x022a
13073 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B_BASE_IDX                                        3
13074 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G                                                 0x022b
13075 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G_BASE_IDX                                        3
13076 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R                                                 0x022c
13077 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R_BASE_IDX                                        3
13078 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_B                                                  0x022d
13079 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_B_BASE_IDX                                         3
13080 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_G                                                  0x022e
13081 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_G_BASE_IDX                                         3
13082 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_R                                                  0x022f
13083 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_R_BASE_IDX                                         3
13084 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_B                                                        0x0230
13085 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_B_BASE_IDX                                               3
13086 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_B                                                        0x0231
13087 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_B_BASE_IDX                                               3
13088 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_G                                                        0x0232
13089 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_G_BASE_IDX                                               3
13090 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_G                                                        0x0233
13091 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_G_BASE_IDX                                               3
13092 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_R                                                        0x0234
13093 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_R_BASE_IDX                                               3
13094 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_R                                                        0x0235
13095 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_R_BASE_IDX                                               3
13096 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_B                                                           0x0236
13097 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_B_BASE_IDX                                                  3
13098 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_G                                                           0x0237
13099 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_G_BASE_IDX                                                  3
13100 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_R                                                           0x0238
13101 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_R_BASE_IDX                                                  3
13102 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_0_1                                                         0x0239
13103 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_0_1_BASE_IDX                                                3
13104 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_2_3                                                         0x023a
13105 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_2_3_BASE_IDX                                                3
13106 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_4_5                                                         0x023b
13107 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_4_5_BASE_IDX                                                3
13108 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_6_7                                                         0x023c
13109 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_6_7_BASE_IDX                                                3
13110 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_8_9                                                         0x023d
13111 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_8_9_BASE_IDX                                                3
13112 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_10_11                                                       0x023e
13113 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_10_11_BASE_IDX                                              3
13114 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_12_13                                                       0x023f
13115 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_12_13_BASE_IDX                                              3
13116 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_14_15                                                       0x0240
13117 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_14_15_BASE_IDX                                              3
13118 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_16_17                                                       0x0241
13119 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_16_17_BASE_IDX                                              3
13120 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_18_19                                                       0x0242
13121 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_18_19_BASE_IDX                                              3
13122 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_20_21                                                       0x0243
13123 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_20_21_BASE_IDX                                              3
13124 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_22_23                                                       0x0244
13125 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_22_23_BASE_IDX                                              3
13126 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_24_25                                                       0x0245
13127 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_24_25_BASE_IDX                                              3
13128 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_26_27                                                       0x0246
13129 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_26_27_BASE_IDX                                              3
13130 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_28_29                                                       0x0247
13131 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_28_29_BASE_IDX                                              3
13132 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_30_31                                                       0x0248
13133 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_30_31_BASE_IDX                                              3
13134 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_32_33                                                       0x0249
13135 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_32_33_BASE_IDX                                              3
13136 #define mmMPCC_OGAM2_MPCC_GAMUT_REMAP_COEF_FORMAT                                                      0x024a
13137 #define mmMPCC_OGAM2_MPCC_GAMUT_REMAP_COEF_FORMAT_BASE_IDX                                             3
13138 #define mmMPCC_OGAM2_MPCC_GAMUT_REMAP_MODE                                                             0x024b
13139 #define mmMPCC_OGAM2_MPCC_GAMUT_REMAP_MODE_BASE_IDX                                                    3
13140 #define mmMPCC_OGAM2_MPC_GAMUT_REMAP_C11_C12_A                                                         0x024c
13141 #define mmMPCC_OGAM2_MPC_GAMUT_REMAP_C11_C12_A_BASE_IDX                                                3
13142 #define mmMPCC_OGAM2_MPC_GAMUT_REMAP_C13_C14_A                                                         0x024d
13143 #define mmMPCC_OGAM2_MPC_GAMUT_REMAP_C13_C14_A_BASE_IDX                                                3
13144 #define mmMPCC_OGAM2_MPC_GAMUT_REMAP_C21_C22_A                                                         0x024e
13145 #define mmMPCC_OGAM2_MPC_GAMUT_REMAP_C21_C22_A_BASE_IDX                                                3
13146 #define mmMPCC_OGAM2_MPC_GAMUT_REMAP_C23_C24_A                                                         0x024f
13147 #define mmMPCC_OGAM2_MPC_GAMUT_REMAP_C23_C24_A_BASE_IDX                                                3
13148 #define mmMPCC_OGAM2_MPC_GAMUT_REMAP_C31_C32_A                                                         0x0250
13149 #define mmMPCC_OGAM2_MPC_GAMUT_REMAP_C31_C32_A_BASE_IDX                                                3
13150 #define mmMPCC_OGAM2_MPC_GAMUT_REMAP_C33_C34_A                                                         0x0251
13151 #define mmMPCC_OGAM2_MPC_GAMUT_REMAP_C33_C34_A_BASE_IDX                                                3
13152 #define mmMPCC_OGAM2_MPC_GAMUT_REMAP_C11_C12_B                                                         0x0252
13153 #define mmMPCC_OGAM2_MPC_GAMUT_REMAP_C11_C12_B_BASE_IDX                                                3
13154 #define mmMPCC_OGAM2_MPC_GAMUT_REMAP_C13_C14_B                                                         0x0253
13155 #define mmMPCC_OGAM2_MPC_GAMUT_REMAP_C13_C14_B_BASE_IDX                                                3
13156 #define mmMPCC_OGAM2_MPC_GAMUT_REMAP_C21_C22_B                                                         0x0254
13157 #define mmMPCC_OGAM2_MPC_GAMUT_REMAP_C21_C22_B_BASE_IDX                                                3
13158 #define mmMPCC_OGAM2_MPC_GAMUT_REMAP_C23_C24_B                                                         0x0255
13159 #define mmMPCC_OGAM2_MPC_GAMUT_REMAP_C23_C24_B_BASE_IDX                                                3
13160 #define mmMPCC_OGAM2_MPC_GAMUT_REMAP_C31_C32_B                                                         0x0256
13161 #define mmMPCC_OGAM2_MPC_GAMUT_REMAP_C31_C32_B_BASE_IDX                                                3
13162 #define mmMPCC_OGAM2_MPC_GAMUT_REMAP_C33_C34_B                                                         0x0257
13163 #define mmMPCC_OGAM2_MPC_GAMUT_REMAP_C33_C34_B_BASE_IDX                                                3
13164 
13165 
13166 // addressBlock: dce_dc_mpc_mpcc_ogam3_dispdec
13167 // base address: 0x600
13168 #define mmMPCC_OGAM3_MPCC_OGAM_CONTROL                                                                 0x0280
13169 #define mmMPCC_OGAM3_MPCC_OGAM_CONTROL_BASE_IDX                                                        3
13170 #define mmMPCC_OGAM3_MPCC_OGAM_LUT_INDEX                                                               0x0281
13171 #define mmMPCC_OGAM3_MPCC_OGAM_LUT_INDEX_BASE_IDX                                                      3
13172 #define mmMPCC_OGAM3_MPCC_OGAM_LUT_DATA                                                                0x0282
13173 #define mmMPCC_OGAM3_MPCC_OGAM_LUT_DATA_BASE_IDX                                                       3
13174 #define mmMPCC_OGAM3_MPCC_OGAM_LUT_CONTROL                                                             0x0283
13175 #define mmMPCC_OGAM3_MPCC_OGAM_LUT_CONTROL_BASE_IDX                                                    3
13176 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_B                                                       0x0284
13177 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_B_BASE_IDX                                              3
13178 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_G                                                       0x0285
13179 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_G_BASE_IDX                                              3
13180 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_R                                                       0x0286
13181 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_R_BASE_IDX                                              3
13182 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B                                                 0x0287
13183 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B_BASE_IDX                                        3
13184 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G                                                 0x0288
13185 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G_BASE_IDX                                        3
13186 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R                                                 0x0289
13187 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R_BASE_IDX                                        3
13188 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_B                                                  0x028a
13189 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_B_BASE_IDX                                         3
13190 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_G                                                  0x028b
13191 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_G_BASE_IDX                                         3
13192 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_R                                                  0x028c
13193 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_R_BASE_IDX                                         3
13194 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_B                                                        0x028d
13195 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_B_BASE_IDX                                               3
13196 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_B                                                        0x028e
13197 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_B_BASE_IDX                                               3
13198 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_G                                                        0x028f
13199 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_G_BASE_IDX                                               3
13200 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_G                                                        0x0290
13201 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_G_BASE_IDX                                               3
13202 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_R                                                        0x0291
13203 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_R_BASE_IDX                                               3
13204 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_R                                                        0x0292
13205 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_R_BASE_IDX                                               3
13206 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_B                                                           0x0293
13207 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_B_BASE_IDX                                                  3
13208 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_G                                                           0x0294
13209 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_G_BASE_IDX                                                  3
13210 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_R                                                           0x0295
13211 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_R_BASE_IDX                                                  3
13212 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_0_1                                                         0x0296
13213 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_0_1_BASE_IDX                                                3
13214 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_2_3                                                         0x0297
13215 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_2_3_BASE_IDX                                                3
13216 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_4_5                                                         0x0298
13217 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_4_5_BASE_IDX                                                3
13218 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_6_7                                                         0x0299
13219 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_6_7_BASE_IDX                                                3
13220 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_8_9                                                         0x029a
13221 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_8_9_BASE_IDX                                                3
13222 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_10_11                                                       0x029b
13223 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_10_11_BASE_IDX                                              3
13224 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_12_13                                                       0x029c
13225 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_12_13_BASE_IDX                                              3
13226 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_14_15                                                       0x029d
13227 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_14_15_BASE_IDX                                              3
13228 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_16_17                                                       0x029e
13229 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_16_17_BASE_IDX                                              3
13230 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_18_19                                                       0x029f
13231 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_18_19_BASE_IDX                                              3
13232 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_20_21                                                       0x02a0
13233 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_20_21_BASE_IDX                                              3
13234 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_22_23                                                       0x02a1
13235 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_22_23_BASE_IDX                                              3
13236 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_24_25                                                       0x02a2
13237 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_24_25_BASE_IDX                                              3
13238 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_26_27                                                       0x02a3
13239 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_26_27_BASE_IDX                                              3
13240 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_28_29                                                       0x02a4
13241 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_28_29_BASE_IDX                                              3
13242 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_30_31                                                       0x02a5
13243 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_30_31_BASE_IDX                                              3
13244 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_32_33                                                       0x02a6
13245 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_32_33_BASE_IDX                                              3
13246 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_B                                                       0x02a7
13247 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_B_BASE_IDX                                              3
13248 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_G                                                       0x02a8
13249 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_G_BASE_IDX                                              3
13250 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_R                                                       0x02a9
13251 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_R_BASE_IDX                                              3
13252 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B                                                 0x02aa
13253 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B_BASE_IDX                                        3
13254 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G                                                 0x02ab
13255 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G_BASE_IDX                                        3
13256 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R                                                 0x02ac
13257 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R_BASE_IDX                                        3
13258 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_B                                                  0x02ad
13259 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_B_BASE_IDX                                         3
13260 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_G                                                  0x02ae
13261 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_G_BASE_IDX                                         3
13262 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_R                                                  0x02af
13263 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_R_BASE_IDX                                         3
13264 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_B                                                        0x02b0
13265 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_B_BASE_IDX                                               3
13266 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_B                                                        0x02b1
13267 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_B_BASE_IDX                                               3
13268 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_G                                                        0x02b2
13269 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_G_BASE_IDX                                               3
13270 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_G                                                        0x02b3
13271 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_G_BASE_IDX                                               3
13272 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_R                                                        0x02b4
13273 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_R_BASE_IDX                                               3
13274 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_R                                                        0x02b5
13275 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_R_BASE_IDX                                               3
13276 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_B                                                           0x02b6
13277 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_B_BASE_IDX                                                  3
13278 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_G                                                           0x02b7
13279 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_G_BASE_IDX                                                  3
13280 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_R                                                           0x02b8
13281 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_R_BASE_IDX                                                  3
13282 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_0_1                                                         0x02b9
13283 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_0_1_BASE_IDX                                                3
13284 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_2_3                                                         0x02ba
13285 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_2_3_BASE_IDX                                                3
13286 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_4_5                                                         0x02bb
13287 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_4_5_BASE_IDX                                                3
13288 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_6_7                                                         0x02bc
13289 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_6_7_BASE_IDX                                                3
13290 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_8_9                                                         0x02bd
13291 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_8_9_BASE_IDX                                                3
13292 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_10_11                                                       0x02be
13293 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_10_11_BASE_IDX                                              3
13294 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_12_13                                                       0x02bf
13295 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_12_13_BASE_IDX                                              3
13296 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_14_15                                                       0x02c0
13297 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_14_15_BASE_IDX                                              3
13298 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_16_17                                                       0x02c1
13299 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_16_17_BASE_IDX                                              3
13300 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_18_19                                                       0x02c2
13301 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_18_19_BASE_IDX                                              3
13302 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_20_21                                                       0x02c3
13303 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_20_21_BASE_IDX                                              3
13304 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_22_23                                                       0x02c4
13305 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_22_23_BASE_IDX                                              3
13306 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_24_25                                                       0x02c5
13307 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_24_25_BASE_IDX                                              3
13308 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_26_27                                                       0x02c6
13309 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_26_27_BASE_IDX                                              3
13310 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_28_29                                                       0x02c7
13311 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_28_29_BASE_IDX                                              3
13312 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_30_31                                                       0x02c8
13313 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_30_31_BASE_IDX                                              3
13314 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_32_33                                                       0x02c9
13315 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_32_33_BASE_IDX                                              3
13316 #define mmMPCC_OGAM3_MPCC_GAMUT_REMAP_COEF_FORMAT                                                      0x02ca
13317 #define mmMPCC_OGAM3_MPCC_GAMUT_REMAP_COEF_FORMAT_BASE_IDX                                             3
13318 #define mmMPCC_OGAM3_MPCC_GAMUT_REMAP_MODE                                                             0x02cb
13319 #define mmMPCC_OGAM3_MPCC_GAMUT_REMAP_MODE_BASE_IDX                                                    3
13320 #define mmMPCC_OGAM3_MPC_GAMUT_REMAP_C11_C12_A                                                         0x02cc
13321 #define mmMPCC_OGAM3_MPC_GAMUT_REMAP_C11_C12_A_BASE_IDX                                                3
13322 #define mmMPCC_OGAM3_MPC_GAMUT_REMAP_C13_C14_A                                                         0x02cd
13323 #define mmMPCC_OGAM3_MPC_GAMUT_REMAP_C13_C14_A_BASE_IDX                                                3
13324 #define mmMPCC_OGAM3_MPC_GAMUT_REMAP_C21_C22_A                                                         0x02ce
13325 #define mmMPCC_OGAM3_MPC_GAMUT_REMAP_C21_C22_A_BASE_IDX                                                3
13326 #define mmMPCC_OGAM3_MPC_GAMUT_REMAP_C23_C24_A                                                         0x02cf
13327 #define mmMPCC_OGAM3_MPC_GAMUT_REMAP_C23_C24_A_BASE_IDX                                                3
13328 #define mmMPCC_OGAM3_MPC_GAMUT_REMAP_C31_C32_A                                                         0x02d0
13329 #define mmMPCC_OGAM3_MPC_GAMUT_REMAP_C31_C32_A_BASE_IDX                                                3
13330 #define mmMPCC_OGAM3_MPC_GAMUT_REMAP_C33_C34_A                                                         0x02d1
13331 #define mmMPCC_OGAM3_MPC_GAMUT_REMAP_C33_C34_A_BASE_IDX                                                3
13332 #define mmMPCC_OGAM3_MPC_GAMUT_REMAP_C11_C12_B                                                         0x02d2
13333 #define mmMPCC_OGAM3_MPC_GAMUT_REMAP_C11_C12_B_BASE_IDX                                                3
13334 #define mmMPCC_OGAM3_MPC_GAMUT_REMAP_C13_C14_B                                                         0x02d3
13335 #define mmMPCC_OGAM3_MPC_GAMUT_REMAP_C13_C14_B_BASE_IDX                                                3
13336 #define mmMPCC_OGAM3_MPC_GAMUT_REMAP_C21_C22_B                                                         0x02d4
13337 #define mmMPCC_OGAM3_MPC_GAMUT_REMAP_C21_C22_B_BASE_IDX                                                3
13338 #define mmMPCC_OGAM3_MPC_GAMUT_REMAP_C23_C24_B                                                         0x02d5
13339 #define mmMPCC_OGAM3_MPC_GAMUT_REMAP_C23_C24_B_BASE_IDX                                                3
13340 #define mmMPCC_OGAM3_MPC_GAMUT_REMAP_C31_C32_B                                                         0x02d6
13341 #define mmMPCC_OGAM3_MPC_GAMUT_REMAP_C31_C32_B_BASE_IDX                                                3
13342 #define mmMPCC_OGAM3_MPC_GAMUT_REMAP_C33_C34_B                                                         0x02d7
13343 #define mmMPCC_OGAM3_MPC_GAMUT_REMAP_C33_C34_B_BASE_IDX                                                3
13344 
13345 
13346 // addressBlock: dce_dc_mpc_mpcc_ogam4_dispdec
13347 // base address: 0x800
13348 #define mmMPCC_OGAM4_MPCC_OGAM_CONTROL                                                                 0x0300
13349 #define mmMPCC_OGAM4_MPCC_OGAM_CONTROL_BASE_IDX                                                        3
13350 #define mmMPCC_OGAM4_MPCC_OGAM_LUT_INDEX                                                               0x0301
13351 #define mmMPCC_OGAM4_MPCC_OGAM_LUT_INDEX_BASE_IDX                                                      3
13352 #define mmMPCC_OGAM4_MPCC_OGAM_LUT_DATA                                                                0x0302
13353 #define mmMPCC_OGAM4_MPCC_OGAM_LUT_DATA_BASE_IDX                                                       3
13354 #define mmMPCC_OGAM4_MPCC_OGAM_LUT_CONTROL                                                             0x0303
13355 #define mmMPCC_OGAM4_MPCC_OGAM_LUT_CONTROL_BASE_IDX                                                    3
13356 #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_START_CNTL_B                                                       0x0304
13357 #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_START_CNTL_B_BASE_IDX                                              3
13358 #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_START_CNTL_G                                                       0x0305
13359 #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_START_CNTL_G_BASE_IDX                                              3
13360 #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_START_CNTL_R                                                       0x0306
13361 #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_START_CNTL_R_BASE_IDX                                              3
13362 #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B                                                 0x0307
13363 #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B_BASE_IDX                                        3
13364 #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G                                                 0x0308
13365 #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G_BASE_IDX                                        3
13366 #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R                                                 0x0309
13367 #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R_BASE_IDX                                        3
13368 #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_START_BASE_CNTL_B                                                  0x030a
13369 #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_START_BASE_CNTL_B_BASE_IDX                                         3
13370 #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_START_BASE_CNTL_G                                                  0x030b
13371 #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_START_BASE_CNTL_G_BASE_IDX                                         3
13372 #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_START_BASE_CNTL_R                                                  0x030c
13373 #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_START_BASE_CNTL_R_BASE_IDX                                         3
13374 #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL1_B                                                        0x030d
13375 #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL1_B_BASE_IDX                                               3
13376 #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL2_B                                                        0x030e
13377 #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL2_B_BASE_IDX                                               3
13378 #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL1_G                                                        0x030f
13379 #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL1_G_BASE_IDX                                               3
13380 #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL2_G                                                        0x0310
13381 #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL2_G_BASE_IDX                                               3
13382 #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL1_R                                                        0x0311
13383 #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL1_R_BASE_IDX                                               3
13384 #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL2_R                                                        0x0312
13385 #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL2_R_BASE_IDX                                               3
13386 #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_OFFSET_B                                                           0x0313
13387 #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_OFFSET_B_BASE_IDX                                                  3
13388 #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_OFFSET_G                                                           0x0314
13389 #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_OFFSET_G_BASE_IDX                                                  3
13390 #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_OFFSET_R                                                           0x0315
13391 #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_OFFSET_R_BASE_IDX                                                  3
13392 #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_0_1                                                         0x0316
13393 #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_0_1_BASE_IDX                                                3
13394 #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_2_3                                                         0x0317
13395 #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_2_3_BASE_IDX                                                3
13396 #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_4_5                                                         0x0318
13397 #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_4_5_BASE_IDX                                                3
13398 #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_6_7                                                         0x0319
13399 #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_6_7_BASE_IDX                                                3
13400 #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_8_9                                                         0x031a
13401 #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_8_9_BASE_IDX                                                3
13402 #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_10_11                                                       0x031b
13403 #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_10_11_BASE_IDX                                              3
13404 #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_12_13                                                       0x031c
13405 #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_12_13_BASE_IDX                                              3
13406 #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_14_15                                                       0x031d
13407 #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_14_15_BASE_IDX                                              3
13408 #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_16_17                                                       0x031e
13409 #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_16_17_BASE_IDX                                              3
13410 #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_18_19                                                       0x031f
13411 #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_18_19_BASE_IDX                                              3
13412 #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_20_21                                                       0x0320
13413 #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_20_21_BASE_IDX                                              3
13414 #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_22_23                                                       0x0321
13415 #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_22_23_BASE_IDX                                              3
13416 #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_24_25                                                       0x0322
13417 #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_24_25_BASE_IDX                                              3
13418 #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_26_27                                                       0x0323
13419 #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_26_27_BASE_IDX                                              3
13420 #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_28_29                                                       0x0324
13421 #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_28_29_BASE_IDX                                              3
13422 #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_30_31                                                       0x0325
13423 #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_30_31_BASE_IDX                                              3
13424 #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_32_33                                                       0x0326
13425 #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_32_33_BASE_IDX                                              3
13426 #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_START_CNTL_B                                                       0x0327
13427 #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_START_CNTL_B_BASE_IDX                                              3
13428 #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_START_CNTL_G                                                       0x0328
13429 #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_START_CNTL_G_BASE_IDX                                              3
13430 #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_START_CNTL_R                                                       0x0329
13431 #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_START_CNTL_R_BASE_IDX                                              3
13432 #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B                                                 0x032a
13433 #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B_BASE_IDX                                        3
13434 #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G                                                 0x032b
13435 #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G_BASE_IDX                                        3
13436 #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R                                                 0x032c
13437 #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R_BASE_IDX                                        3
13438 #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_START_BASE_CNTL_B                                                  0x032d
13439 #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_START_BASE_CNTL_B_BASE_IDX                                         3
13440 #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_START_BASE_CNTL_G                                                  0x032e
13441 #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_START_BASE_CNTL_G_BASE_IDX                                         3
13442 #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_START_BASE_CNTL_R                                                  0x032f
13443 #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_START_BASE_CNTL_R_BASE_IDX                                         3
13444 #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL1_B                                                        0x0330
13445 #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL1_B_BASE_IDX                                               3
13446 #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL2_B                                                        0x0331
13447 #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL2_B_BASE_IDX                                               3
13448 #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL1_G                                                        0x0332
13449 #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL1_G_BASE_IDX                                               3
13450 #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL2_G                                                        0x0333
13451 #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL2_G_BASE_IDX                                               3
13452 #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL1_R                                                        0x0334
13453 #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL1_R_BASE_IDX                                               3
13454 #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL2_R                                                        0x0335
13455 #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL2_R_BASE_IDX                                               3
13456 #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_OFFSET_B                                                           0x0336
13457 #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_OFFSET_B_BASE_IDX                                                  3
13458 #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_OFFSET_G                                                           0x0337
13459 #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_OFFSET_G_BASE_IDX                                                  3
13460 #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_OFFSET_R                                                           0x0338
13461 #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_OFFSET_R_BASE_IDX                                                  3
13462 #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_0_1                                                         0x0339
13463 #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_0_1_BASE_IDX                                                3
13464 #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_2_3                                                         0x033a
13465 #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_2_3_BASE_IDX                                                3
13466 #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_4_5                                                         0x033b
13467 #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_4_5_BASE_IDX                                                3
13468 #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_6_7                                                         0x033c
13469 #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_6_7_BASE_IDX                                                3
13470 #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_8_9                                                         0x033d
13471 #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_8_9_BASE_IDX                                                3
13472 #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_10_11                                                       0x033e
13473 #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_10_11_BASE_IDX                                              3
13474 #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_12_13                                                       0x033f
13475 #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_12_13_BASE_IDX                                              3
13476 #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_14_15                                                       0x0340
13477 #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_14_15_BASE_IDX                                              3
13478 #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_16_17                                                       0x0341
13479 #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_16_17_BASE_IDX                                              3
13480 #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_18_19                                                       0x0342
13481 #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_18_19_BASE_IDX                                              3
13482 #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_20_21                                                       0x0343
13483 #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_20_21_BASE_IDX                                              3
13484 #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_22_23                                                       0x0344
13485 #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_22_23_BASE_IDX                                              3
13486 #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_24_25                                                       0x0345
13487 #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_24_25_BASE_IDX                                              3
13488 #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_26_27                                                       0x0346
13489 #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_26_27_BASE_IDX                                              3
13490 #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_28_29                                                       0x0347
13491 #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_28_29_BASE_IDX                                              3
13492 #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_30_31                                                       0x0348
13493 #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_30_31_BASE_IDX                                              3
13494 #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_32_33                                                       0x0349
13495 #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_32_33_BASE_IDX                                              3
13496 #define mmMPCC_OGAM4_MPCC_GAMUT_REMAP_COEF_FORMAT                                                      0x034a
13497 #define mmMPCC_OGAM4_MPCC_GAMUT_REMAP_COEF_FORMAT_BASE_IDX                                             3
13498 #define mmMPCC_OGAM4_MPCC_GAMUT_REMAP_MODE                                                             0x034b
13499 #define mmMPCC_OGAM4_MPCC_GAMUT_REMAP_MODE_BASE_IDX                                                    3
13500 #define mmMPCC_OGAM4_MPC_GAMUT_REMAP_C11_C12_A                                                         0x034c
13501 #define mmMPCC_OGAM4_MPC_GAMUT_REMAP_C11_C12_A_BASE_IDX                                                3
13502 #define mmMPCC_OGAM4_MPC_GAMUT_REMAP_C13_C14_A                                                         0x034d
13503 #define mmMPCC_OGAM4_MPC_GAMUT_REMAP_C13_C14_A_BASE_IDX                                                3
13504 #define mmMPCC_OGAM4_MPC_GAMUT_REMAP_C21_C22_A                                                         0x034e
13505 #define mmMPCC_OGAM4_MPC_GAMUT_REMAP_C21_C22_A_BASE_IDX                                                3
13506 #define mmMPCC_OGAM4_MPC_GAMUT_REMAP_C23_C24_A                                                         0x034f
13507 #define mmMPCC_OGAM4_MPC_GAMUT_REMAP_C23_C24_A_BASE_IDX                                                3
13508 #define mmMPCC_OGAM4_MPC_GAMUT_REMAP_C31_C32_A                                                         0x0350
13509 #define mmMPCC_OGAM4_MPC_GAMUT_REMAP_C31_C32_A_BASE_IDX                                                3
13510 #define mmMPCC_OGAM4_MPC_GAMUT_REMAP_C33_C34_A                                                         0x0351
13511 #define mmMPCC_OGAM4_MPC_GAMUT_REMAP_C33_C34_A_BASE_IDX                                                3
13512 #define mmMPCC_OGAM4_MPC_GAMUT_REMAP_C11_C12_B                                                         0x0352
13513 #define mmMPCC_OGAM4_MPC_GAMUT_REMAP_C11_C12_B_BASE_IDX                                                3
13514 #define mmMPCC_OGAM4_MPC_GAMUT_REMAP_C13_C14_B                                                         0x0353
13515 #define mmMPCC_OGAM4_MPC_GAMUT_REMAP_C13_C14_B_BASE_IDX                                                3
13516 #define mmMPCC_OGAM4_MPC_GAMUT_REMAP_C21_C22_B                                                         0x0354
13517 #define mmMPCC_OGAM4_MPC_GAMUT_REMAP_C21_C22_B_BASE_IDX                                                3
13518 #define mmMPCC_OGAM4_MPC_GAMUT_REMAP_C23_C24_B                                                         0x0355
13519 #define mmMPCC_OGAM4_MPC_GAMUT_REMAP_C23_C24_B_BASE_IDX                                                3
13520 #define mmMPCC_OGAM4_MPC_GAMUT_REMAP_C31_C32_B                                                         0x0356
13521 #define mmMPCC_OGAM4_MPC_GAMUT_REMAP_C31_C32_B_BASE_IDX                                                3
13522 #define mmMPCC_OGAM4_MPC_GAMUT_REMAP_C33_C34_B                                                         0x0357
13523 #define mmMPCC_OGAM4_MPC_GAMUT_REMAP_C33_C34_B_BASE_IDX                                                3
13524 
13525 
13526 // addressBlock: dce_dc_mpc_mpc_cfg_dispdec
13527 // base address: 0x0
13528 #define mmMPC_CLOCK_CONTROL                                                                            0x0500
13529 #define mmMPC_CLOCK_CONTROL_BASE_IDX                                                                   3
13530 #define mmMPC_SOFT_RESET                                                                               0x0501
13531 #define mmMPC_SOFT_RESET_BASE_IDX                                                                      3
13532 #define mmMPC_CRC_CTRL                                                                                 0x0502
13533 #define mmMPC_CRC_CTRL_BASE_IDX                                                                        3
13534 #define mmMPC_CRC_SEL_CONTROL                                                                          0x0503
13535 #define mmMPC_CRC_SEL_CONTROL_BASE_IDX                                                                 3
13536 #define mmMPC_CRC_RESULT_AR                                                                            0x0504
13537 #define mmMPC_CRC_RESULT_AR_BASE_IDX                                                                   3
13538 #define mmMPC_CRC_RESULT_GB                                                                            0x0505
13539 #define mmMPC_CRC_RESULT_GB_BASE_IDX                                                                   3
13540 #define mmMPC_CRC_RESULT_C                                                                             0x0506
13541 #define mmMPC_CRC_RESULT_C_BASE_IDX                                                                    3
13542 #define mmMPC_PERFMON_EVENT_CTRL                                                                       0x0509
13543 #define mmMPC_PERFMON_EVENT_CTRL_BASE_IDX                                                              3
13544 #define mmMPC_BYPASS_BG_AR                                                                             0x050a
13545 #define mmMPC_BYPASS_BG_AR_BASE_IDX                                                                    3
13546 #define mmMPC_BYPASS_BG_GB                                                                             0x050b
13547 #define mmMPC_BYPASS_BG_GB_BASE_IDX                                                                    3
13548 #define mmMPC_HOST_READ_CONTROL                                                                        0x050c
13549 #define mmMPC_HOST_READ_CONTROL_BASE_IDX                                                               3
13550 #define mmMPC_DPP_PENDING_STATUS                                                                       0x050d
13551 #define mmMPC_DPP_PENDING_STATUS_BASE_IDX                                                              3
13552 #define mmMPC_PENDING_STATUS_MISC                                                                      0x050e
13553 #define mmMPC_PENDING_STATUS_MISC_BASE_IDX                                                             3
13554 #define mmADR_CFG_CUR_VUPDATE_LOCK_SET0                                                                0x050f
13555 #define mmADR_CFG_CUR_VUPDATE_LOCK_SET0_BASE_IDX                                                       3
13556 #define mmADR_CFG_VUPDATE_LOCK_SET0                                                                    0x0510
13557 #define mmADR_CFG_VUPDATE_LOCK_SET0_BASE_IDX                                                           3
13558 #define mmADR_VUPDATE_LOCK_SET0                                                                        0x0511
13559 #define mmADR_VUPDATE_LOCK_SET0_BASE_IDX                                                               3
13560 #define mmCFG_VUPDATE_LOCK_SET0                                                                        0x0512
13561 #define mmCFG_VUPDATE_LOCK_SET0_BASE_IDX                                                               3
13562 #define mmCUR_VUPDATE_LOCK_SET0                                                                        0x0513
13563 #define mmCUR_VUPDATE_LOCK_SET0_BASE_IDX                                                               3
13564 #define mmADR_CFG_CUR_VUPDATE_LOCK_SET1                                                                0x0514
13565 #define mmADR_CFG_CUR_VUPDATE_LOCK_SET1_BASE_IDX                                                       3
13566 #define mmADR_CFG_VUPDATE_LOCK_SET1                                                                    0x0515
13567 #define mmADR_CFG_VUPDATE_LOCK_SET1_BASE_IDX                                                           3
13568 #define mmADR_VUPDATE_LOCK_SET1                                                                        0x0516
13569 #define mmADR_VUPDATE_LOCK_SET1_BASE_IDX                                                               3
13570 #define mmCFG_VUPDATE_LOCK_SET1                                                                        0x0517
13571 #define mmCFG_VUPDATE_LOCK_SET1_BASE_IDX                                                               3
13572 #define mmCUR_VUPDATE_LOCK_SET1                                                                        0x0518
13573 #define mmCUR_VUPDATE_LOCK_SET1_BASE_IDX                                                               3
13574 #define mmADR_CFG_CUR_VUPDATE_LOCK_SET2                                                                0x0519
13575 #define mmADR_CFG_CUR_VUPDATE_LOCK_SET2_BASE_IDX                                                       3
13576 #define mmADR_CFG_VUPDATE_LOCK_SET2                                                                    0x051a
13577 #define mmADR_CFG_VUPDATE_LOCK_SET2_BASE_IDX                                                           3
13578 #define mmADR_VUPDATE_LOCK_SET2                                                                        0x051b
13579 #define mmADR_VUPDATE_LOCK_SET2_BASE_IDX                                                               3
13580 #define mmCFG_VUPDATE_LOCK_SET2                                                                        0x051c
13581 #define mmCFG_VUPDATE_LOCK_SET2_BASE_IDX                                                               3
13582 #define mmCUR_VUPDATE_LOCK_SET2                                                                        0x051d
13583 #define mmCUR_VUPDATE_LOCK_SET2_BASE_IDX                                                               3
13584 #define mmADR_CFG_CUR_VUPDATE_LOCK_SET3                                                                0x051e
13585 #define mmADR_CFG_CUR_VUPDATE_LOCK_SET3_BASE_IDX                                                       3
13586 #define mmADR_CFG_VUPDATE_LOCK_SET3                                                                    0x051f
13587 #define mmADR_CFG_VUPDATE_LOCK_SET3_BASE_IDX                                                           3
13588 #define mmADR_VUPDATE_LOCK_SET3                                                                        0x0520
13589 #define mmADR_VUPDATE_LOCK_SET3_BASE_IDX                                                               3
13590 #define mmCFG_VUPDATE_LOCK_SET3                                                                        0x0521
13591 #define mmCFG_VUPDATE_LOCK_SET3_BASE_IDX                                                               3
13592 #define mmCUR_VUPDATE_LOCK_SET3                                                                        0x0522
13593 #define mmCUR_VUPDATE_LOCK_SET3_BASE_IDX                                                               3
13594 #define mmADR_CFG_CUR_VUPDATE_LOCK_SET4                                                                0x0523
13595 #define mmADR_CFG_CUR_VUPDATE_LOCK_SET4_BASE_IDX                                                       3
13596 #define mmADR_CFG_VUPDATE_LOCK_SET4                                                                    0x0524
13597 #define mmADR_CFG_VUPDATE_LOCK_SET4_BASE_IDX                                                           3
13598 #define mmADR_VUPDATE_LOCK_SET4                                                                        0x0525
13599 #define mmADR_VUPDATE_LOCK_SET4_BASE_IDX                                                               3
13600 #define mmCFG_VUPDATE_LOCK_SET4                                                                        0x0526
13601 #define mmCFG_VUPDATE_LOCK_SET4_BASE_IDX                                                               3
13602 #define mmCUR_VUPDATE_LOCK_SET4                                                                        0x0527
13603 #define mmCUR_VUPDATE_LOCK_SET4_BASE_IDX                                                               3
13604 #define mmMPC_DWB0_MUX                                                                                 0x055c
13605 #define mmMPC_DWB0_MUX_BASE_IDX                                                                        3
13606 
13607 
13608 // addressBlock: dce_dc_mpc_mpc_ocsc_dispdec
13609 // base address: 0x0
13610 #define mmMPC_OUT0_MUX                                                                                 0x0580
13611 #define mmMPC_OUT0_MUX_BASE_IDX                                                                        3
13612 #define mmMPC_OUT0_DENORM_CONTROL                                                                      0x0581
13613 #define mmMPC_OUT0_DENORM_CONTROL_BASE_IDX                                                             3
13614 #define mmMPC_OUT0_DENORM_CLAMP_G_Y                                                                    0x0582
13615 #define mmMPC_OUT0_DENORM_CLAMP_G_Y_BASE_IDX                                                           3
13616 #define mmMPC_OUT0_DENORM_CLAMP_B_CB                                                                   0x0583
13617 #define mmMPC_OUT0_DENORM_CLAMP_B_CB_BASE_IDX                                                          3
13618 #define mmMPC_OUT1_MUX                                                                                 0x0584
13619 #define mmMPC_OUT1_MUX_BASE_IDX                                                                        3
13620 #define mmMPC_OUT1_DENORM_CONTROL                                                                      0x0585
13621 #define mmMPC_OUT1_DENORM_CONTROL_BASE_IDX                                                             3
13622 #define mmMPC_OUT1_DENORM_CLAMP_G_Y                                                                    0x0586
13623 #define mmMPC_OUT1_DENORM_CLAMP_G_Y_BASE_IDX                                                           3
13624 #define mmMPC_OUT1_DENORM_CLAMP_B_CB                                                                   0x0587
13625 #define mmMPC_OUT1_DENORM_CLAMP_B_CB_BASE_IDX                                                          3
13626 #define mmMPC_OUT2_MUX                                                                                 0x0588
13627 #define mmMPC_OUT2_MUX_BASE_IDX                                                                        3
13628 #define mmMPC_OUT2_DENORM_CONTROL                                                                      0x0589
13629 #define mmMPC_OUT2_DENORM_CONTROL_BASE_IDX                                                             3
13630 #define mmMPC_OUT2_DENORM_CLAMP_G_Y                                                                    0x058a
13631 #define mmMPC_OUT2_DENORM_CLAMP_G_Y_BASE_IDX                                                           3
13632 #define mmMPC_OUT2_DENORM_CLAMP_B_CB                                                                   0x058b
13633 #define mmMPC_OUT2_DENORM_CLAMP_B_CB_BASE_IDX                                                          3
13634 #define mmMPC_OUT3_MUX                                                                                 0x058c
13635 #define mmMPC_OUT3_MUX_BASE_IDX                                                                        3
13636 #define mmMPC_OUT3_DENORM_CONTROL                                                                      0x058d
13637 #define mmMPC_OUT3_DENORM_CONTROL_BASE_IDX                                                             3
13638 #define mmMPC_OUT3_DENORM_CLAMP_G_Y                                                                    0x058e
13639 #define mmMPC_OUT3_DENORM_CLAMP_G_Y_BASE_IDX                                                           3
13640 #define mmMPC_OUT3_DENORM_CLAMP_B_CB                                                                   0x058f
13641 #define mmMPC_OUT3_DENORM_CLAMP_B_CB_BASE_IDX                                                          3
13642 #define mmMPC_OUT4_MUX                                                                                 0x0590
13643 #define mmMPC_OUT4_MUX_BASE_IDX                                                                        3
13644 #define mmMPC_OUT4_DENORM_CONTROL                                                                      0x0591
13645 #define mmMPC_OUT4_DENORM_CONTROL_BASE_IDX                                                             3
13646 #define mmMPC_OUT4_DENORM_CLAMP_G_Y                                                                    0x0592
13647 #define mmMPC_OUT4_DENORM_CLAMP_G_Y_BASE_IDX                                                           3
13648 #define mmMPC_OUT4_DENORM_CLAMP_B_CB                                                                   0x0593
13649 #define mmMPC_OUT4_DENORM_CLAMP_B_CB_BASE_IDX                                                          3
13650 #define mmMPC_OUT_CSC_COEF_FORMAT                                                                      0x0594
13651 #define mmMPC_OUT_CSC_COEF_FORMAT_BASE_IDX                                                             3
13652 #define mmMPC_OUT0_CSC_MODE                                                                            0x0595
13653 #define mmMPC_OUT0_CSC_MODE_BASE_IDX                                                                   3
13654 #define mmMPC_OUT0_CSC_C11_C12_A                                                                       0x0596
13655 #define mmMPC_OUT0_CSC_C11_C12_A_BASE_IDX                                                              3
13656 #define mmMPC_OUT0_CSC_C13_C14_A                                                                       0x0597
13657 #define mmMPC_OUT0_CSC_C13_C14_A_BASE_IDX                                                              3
13658 #define mmMPC_OUT0_CSC_C21_C22_A                                                                       0x0598
13659 #define mmMPC_OUT0_CSC_C21_C22_A_BASE_IDX                                                              3
13660 #define mmMPC_OUT0_CSC_C23_C24_A                                                                       0x0599
13661 #define mmMPC_OUT0_CSC_C23_C24_A_BASE_IDX                                                              3
13662 #define mmMPC_OUT0_CSC_C31_C32_A                                                                       0x059a
13663 #define mmMPC_OUT0_CSC_C31_C32_A_BASE_IDX                                                              3
13664 #define mmMPC_OUT0_CSC_C33_C34_A                                                                       0x059b
13665 #define mmMPC_OUT0_CSC_C33_C34_A_BASE_IDX                                                              3
13666 #define mmMPC_OUT0_CSC_C11_C12_B                                                                       0x059c
13667 #define mmMPC_OUT0_CSC_C11_C12_B_BASE_IDX                                                              3
13668 #define mmMPC_OUT0_CSC_C13_C14_B                                                                       0x059d
13669 #define mmMPC_OUT0_CSC_C13_C14_B_BASE_IDX                                                              3
13670 #define mmMPC_OUT0_CSC_C21_C22_B                                                                       0x059e
13671 #define mmMPC_OUT0_CSC_C21_C22_B_BASE_IDX                                                              3
13672 #define mmMPC_OUT0_CSC_C23_C24_B                                                                       0x059f
13673 #define mmMPC_OUT0_CSC_C23_C24_B_BASE_IDX                                                              3
13674 #define mmMPC_OUT0_CSC_C31_C32_B                                                                       0x05a0
13675 #define mmMPC_OUT0_CSC_C31_C32_B_BASE_IDX                                                              3
13676 #define mmMPC_OUT0_CSC_C33_C34_B                                                                       0x05a1
13677 #define mmMPC_OUT0_CSC_C33_C34_B_BASE_IDX                                                              3
13678 #define mmMPC_OUT1_CSC_MODE                                                                            0x05a2
13679 #define mmMPC_OUT1_CSC_MODE_BASE_IDX                                                                   3
13680 #define mmMPC_OUT1_CSC_C11_C12_A                                                                       0x05a3
13681 #define mmMPC_OUT1_CSC_C11_C12_A_BASE_IDX                                                              3
13682 #define mmMPC_OUT1_CSC_C13_C14_A                                                                       0x05a4
13683 #define mmMPC_OUT1_CSC_C13_C14_A_BASE_IDX                                                              3
13684 #define mmMPC_OUT1_CSC_C21_C22_A                                                                       0x05a5
13685 #define mmMPC_OUT1_CSC_C21_C22_A_BASE_IDX                                                              3
13686 #define mmMPC_OUT1_CSC_C23_C24_A                                                                       0x05a6
13687 #define mmMPC_OUT1_CSC_C23_C24_A_BASE_IDX                                                              3
13688 #define mmMPC_OUT1_CSC_C31_C32_A                                                                       0x05a7
13689 #define mmMPC_OUT1_CSC_C31_C32_A_BASE_IDX                                                              3
13690 #define mmMPC_OUT1_CSC_C33_C34_A                                                                       0x05a8
13691 #define mmMPC_OUT1_CSC_C33_C34_A_BASE_IDX                                                              3
13692 #define mmMPC_OUT1_CSC_C11_C12_B                                                                       0x05a9
13693 #define mmMPC_OUT1_CSC_C11_C12_B_BASE_IDX                                                              3
13694 #define mmMPC_OUT1_CSC_C13_C14_B                                                                       0x05aa
13695 #define mmMPC_OUT1_CSC_C13_C14_B_BASE_IDX                                                              3
13696 #define mmMPC_OUT1_CSC_C21_C22_B                                                                       0x05ab
13697 #define mmMPC_OUT1_CSC_C21_C22_B_BASE_IDX                                                              3
13698 #define mmMPC_OUT1_CSC_C23_C24_B                                                                       0x05ac
13699 #define mmMPC_OUT1_CSC_C23_C24_B_BASE_IDX                                                              3
13700 #define mmMPC_OUT1_CSC_C31_C32_B                                                                       0x05ad
13701 #define mmMPC_OUT1_CSC_C31_C32_B_BASE_IDX                                                              3
13702 #define mmMPC_OUT1_CSC_C33_C34_B                                                                       0x05ae
13703 #define mmMPC_OUT1_CSC_C33_C34_B_BASE_IDX                                                              3
13704 #define mmMPC_OUT2_CSC_MODE                                                                            0x05af
13705 #define mmMPC_OUT2_CSC_MODE_BASE_IDX                                                                   3
13706 #define mmMPC_OUT2_CSC_C11_C12_A                                                                       0x05b0
13707 #define mmMPC_OUT2_CSC_C11_C12_A_BASE_IDX                                                              3
13708 #define mmMPC_OUT2_CSC_C13_C14_A                                                                       0x05b1
13709 #define mmMPC_OUT2_CSC_C13_C14_A_BASE_IDX                                                              3
13710 #define mmMPC_OUT2_CSC_C21_C22_A                                                                       0x05b2
13711 #define mmMPC_OUT2_CSC_C21_C22_A_BASE_IDX                                                              3
13712 #define mmMPC_OUT2_CSC_C23_C24_A                                                                       0x05b3
13713 #define mmMPC_OUT2_CSC_C23_C24_A_BASE_IDX                                                              3
13714 #define mmMPC_OUT2_CSC_C31_C32_A                                                                       0x05b4
13715 #define mmMPC_OUT2_CSC_C31_C32_A_BASE_IDX                                                              3
13716 #define mmMPC_OUT2_CSC_C33_C34_A                                                                       0x05b5
13717 #define mmMPC_OUT2_CSC_C33_C34_A_BASE_IDX                                                              3
13718 #define mmMPC_OUT2_CSC_C11_C12_B                                                                       0x05b6
13719 #define mmMPC_OUT2_CSC_C11_C12_B_BASE_IDX                                                              3
13720 #define mmMPC_OUT2_CSC_C13_C14_B                                                                       0x05b7
13721 #define mmMPC_OUT2_CSC_C13_C14_B_BASE_IDX                                                              3
13722 #define mmMPC_OUT2_CSC_C21_C22_B                                                                       0x05b8
13723 #define mmMPC_OUT2_CSC_C21_C22_B_BASE_IDX                                                              3
13724 #define mmMPC_OUT2_CSC_C23_C24_B                                                                       0x05b9
13725 #define mmMPC_OUT2_CSC_C23_C24_B_BASE_IDX                                                              3
13726 #define mmMPC_OUT2_CSC_C31_C32_B                                                                       0x05ba
13727 #define mmMPC_OUT2_CSC_C31_C32_B_BASE_IDX                                                              3
13728 #define mmMPC_OUT2_CSC_C33_C34_B                                                                       0x05bb
13729 #define mmMPC_OUT2_CSC_C33_C34_B_BASE_IDX                                                              3
13730 #define mmMPC_OUT3_CSC_MODE                                                                            0x05bc
13731 #define mmMPC_OUT3_CSC_MODE_BASE_IDX                                                                   3
13732 #define mmMPC_OUT3_CSC_C11_C12_A                                                                       0x05bd
13733 #define mmMPC_OUT3_CSC_C11_C12_A_BASE_IDX                                                              3
13734 #define mmMPC_OUT3_CSC_C13_C14_A                                                                       0x05be
13735 #define mmMPC_OUT3_CSC_C13_C14_A_BASE_IDX                                                              3
13736 #define mmMPC_OUT3_CSC_C21_C22_A                                                                       0x05bf
13737 #define mmMPC_OUT3_CSC_C21_C22_A_BASE_IDX                                                              3
13738 #define mmMPC_OUT3_CSC_C23_C24_A                                                                       0x05c0
13739 #define mmMPC_OUT3_CSC_C23_C24_A_BASE_IDX                                                              3
13740 #define mmMPC_OUT3_CSC_C31_C32_A                                                                       0x05c1
13741 #define mmMPC_OUT3_CSC_C31_C32_A_BASE_IDX                                                              3
13742 #define mmMPC_OUT3_CSC_C33_C34_A                                                                       0x05c2
13743 #define mmMPC_OUT3_CSC_C33_C34_A_BASE_IDX                                                              3
13744 #define mmMPC_OUT3_CSC_C11_C12_B                                                                       0x05c3
13745 #define mmMPC_OUT3_CSC_C11_C12_B_BASE_IDX                                                              3
13746 #define mmMPC_OUT3_CSC_C13_C14_B                                                                       0x05c4
13747 #define mmMPC_OUT3_CSC_C13_C14_B_BASE_IDX                                                              3
13748 #define mmMPC_OUT3_CSC_C21_C22_B                                                                       0x05c5
13749 #define mmMPC_OUT3_CSC_C21_C22_B_BASE_IDX                                                              3
13750 #define mmMPC_OUT3_CSC_C23_C24_B                                                                       0x05c6
13751 #define mmMPC_OUT3_CSC_C23_C24_B_BASE_IDX                                                              3
13752 #define mmMPC_OUT3_CSC_C31_C32_B                                                                       0x05c7
13753 #define mmMPC_OUT3_CSC_C31_C32_B_BASE_IDX                                                              3
13754 #define mmMPC_OUT3_CSC_C33_C34_B                                                                       0x05c8
13755 #define mmMPC_OUT3_CSC_C33_C34_B_BASE_IDX                                                              3
13756 #define mmMPC_OUT4_CSC_MODE                                                                            0x05c9
13757 #define mmMPC_OUT4_CSC_MODE_BASE_IDX                                                                   3
13758 #define mmMPC_OUT4_CSC_C11_C12_A                                                                       0x05ca
13759 #define mmMPC_OUT4_CSC_C11_C12_A_BASE_IDX                                                              3
13760 #define mmMPC_OUT4_CSC_C13_C14_A                                                                       0x05cb
13761 #define mmMPC_OUT4_CSC_C13_C14_A_BASE_IDX                                                              3
13762 #define mmMPC_OUT4_CSC_C21_C22_A                                                                       0x05cc
13763 #define mmMPC_OUT4_CSC_C21_C22_A_BASE_IDX                                                              3
13764 #define mmMPC_OUT4_CSC_C23_C24_A                                                                       0x05cd
13765 #define mmMPC_OUT4_CSC_C23_C24_A_BASE_IDX                                                              3
13766 #define mmMPC_OUT4_CSC_C31_C32_A                                                                       0x05ce
13767 #define mmMPC_OUT4_CSC_C31_C32_A_BASE_IDX                                                              3
13768 #define mmMPC_OUT4_CSC_C33_C34_A                                                                       0x05cf
13769 #define mmMPC_OUT4_CSC_C33_C34_A_BASE_IDX                                                              3
13770 #define mmMPC_OUT4_CSC_C11_C12_B                                                                       0x05d0
13771 #define mmMPC_OUT4_CSC_C11_C12_B_BASE_IDX                                                              3
13772 #define mmMPC_OUT4_CSC_C13_C14_B                                                                       0x05d1
13773 #define mmMPC_OUT4_CSC_C13_C14_B_BASE_IDX                                                              3
13774 #define mmMPC_OUT4_CSC_C21_C22_B                                                                       0x05d2
13775 #define mmMPC_OUT4_CSC_C21_C22_B_BASE_IDX                                                              3
13776 #define mmMPC_OUT4_CSC_C23_C24_B                                                                       0x05d3
13777 #define mmMPC_OUT4_CSC_C23_C24_B_BASE_IDX                                                              3
13778 #define mmMPC_OUT4_CSC_C31_C32_B                                                                       0x05d4
13779 #define mmMPC_OUT4_CSC_C31_C32_B_BASE_IDX                                                              3
13780 #define mmMPC_OUT4_CSC_C33_C34_B                                                                       0x05d5
13781 #define mmMPC_OUT4_CSC_C33_C34_B_BASE_IDX                                                              3
13782 
13783 
13784 // addressBlock: dce_dc_mpc_mpc_rmu_dispdec
13785 // base address: 0x0
13786 #define mmMPC_RMU_CONTROL                                                                              0x0680
13787 #define mmMPC_RMU_CONTROL_BASE_IDX                                                                     3
13788 #define mmMPC_RMU_MEM_PWR_CTRL                                                                         0x0681
13789 #define mmMPC_RMU_MEM_PWR_CTRL_BASE_IDX                                                                3
13790 #define mmMPC_RMU0_SHAPER_CONTROL                                                                      0x0682
13791 #define mmMPC_RMU0_SHAPER_CONTROL_BASE_IDX                                                             3
13792 #define mmMPC_RMU0_SHAPER_OFFSET_R                                                                     0x0683
13793 #define mmMPC_RMU0_SHAPER_OFFSET_R_BASE_IDX                                                            3
13794 #define mmMPC_RMU0_SHAPER_OFFSET_G                                                                     0x0684
13795 #define mmMPC_RMU0_SHAPER_OFFSET_G_BASE_IDX                                                            3
13796 #define mmMPC_RMU0_SHAPER_OFFSET_B                                                                     0x0685
13797 #define mmMPC_RMU0_SHAPER_OFFSET_B_BASE_IDX                                                            3
13798 #define mmMPC_RMU0_SHAPER_SCALE_R                                                                      0x0686
13799 #define mmMPC_RMU0_SHAPER_SCALE_R_BASE_IDX                                                             3
13800 #define mmMPC_RMU0_SHAPER_SCALE_G_B                                                                    0x0687
13801 #define mmMPC_RMU0_SHAPER_SCALE_G_B_BASE_IDX                                                           3
13802 #define mmMPC_RMU0_SHAPER_LUT_INDEX                                                                    0x0688
13803 #define mmMPC_RMU0_SHAPER_LUT_INDEX_BASE_IDX                                                           3
13804 #define mmMPC_RMU0_SHAPER_LUT_DATA                                                                     0x0689
13805 #define mmMPC_RMU0_SHAPER_LUT_DATA_BASE_IDX                                                            3
13806 #define mmMPC_RMU0_SHAPER_LUT_WRITE_EN_MASK                                                            0x068a
13807 #define mmMPC_RMU0_SHAPER_LUT_WRITE_EN_MASK_BASE_IDX                                                   3
13808 #define mmMPC_RMU0_SHAPER_RAMA_START_CNTL_B                                                            0x068b
13809 #define mmMPC_RMU0_SHAPER_RAMA_START_CNTL_B_BASE_IDX                                                   3
13810 #define mmMPC_RMU0_SHAPER_RAMA_START_CNTL_G                                                            0x068c
13811 #define mmMPC_RMU0_SHAPER_RAMA_START_CNTL_G_BASE_IDX                                                   3
13812 #define mmMPC_RMU0_SHAPER_RAMA_START_CNTL_R                                                            0x068d
13813 #define mmMPC_RMU0_SHAPER_RAMA_START_CNTL_R_BASE_IDX                                                   3
13814 #define mmMPC_RMU0_SHAPER_RAMA_END_CNTL_B                                                              0x068e
13815 #define mmMPC_RMU0_SHAPER_RAMA_END_CNTL_B_BASE_IDX                                                     3
13816 #define mmMPC_RMU0_SHAPER_RAMA_END_CNTL_G                                                              0x068f
13817 #define mmMPC_RMU0_SHAPER_RAMA_END_CNTL_G_BASE_IDX                                                     3
13818 #define mmMPC_RMU0_SHAPER_RAMA_END_CNTL_R                                                              0x0690
13819 #define mmMPC_RMU0_SHAPER_RAMA_END_CNTL_R_BASE_IDX                                                     3
13820 #define mmMPC_RMU0_SHAPER_RAMA_REGION_0_1                                                              0x0691
13821 #define mmMPC_RMU0_SHAPER_RAMA_REGION_0_1_BASE_IDX                                                     3
13822 #define mmMPC_RMU0_SHAPER_RAMA_REGION_2_3                                                              0x0692
13823 #define mmMPC_RMU0_SHAPER_RAMA_REGION_2_3_BASE_IDX                                                     3
13824 #define mmMPC_RMU0_SHAPER_RAMA_REGION_4_5                                                              0x0693
13825 #define mmMPC_RMU0_SHAPER_RAMA_REGION_4_5_BASE_IDX                                                     3
13826 #define mmMPC_RMU0_SHAPER_RAMA_REGION_6_7                                                              0x0694
13827 #define mmMPC_RMU0_SHAPER_RAMA_REGION_6_7_BASE_IDX                                                     3
13828 #define mmMPC_RMU0_SHAPER_RAMA_REGION_8_9                                                              0x0695
13829 #define mmMPC_RMU0_SHAPER_RAMA_REGION_8_9_BASE_IDX                                                     3
13830 #define mmMPC_RMU0_SHAPER_RAMA_REGION_10_11                                                            0x0696
13831 #define mmMPC_RMU0_SHAPER_RAMA_REGION_10_11_BASE_IDX                                                   3
13832 #define mmMPC_RMU0_SHAPER_RAMA_REGION_12_13                                                            0x0697
13833 #define mmMPC_RMU0_SHAPER_RAMA_REGION_12_13_BASE_IDX                                                   3
13834 #define mmMPC_RMU0_SHAPER_RAMA_REGION_14_15                                                            0x0698
13835 #define mmMPC_RMU0_SHAPER_RAMA_REGION_14_15_BASE_IDX                                                   3
13836 #define mmMPC_RMU0_SHAPER_RAMA_REGION_16_17                                                            0x0699
13837 #define mmMPC_RMU0_SHAPER_RAMA_REGION_16_17_BASE_IDX                                                   3
13838 #define mmMPC_RMU0_SHAPER_RAMA_REGION_18_19                                                            0x069a
13839 #define mmMPC_RMU0_SHAPER_RAMA_REGION_18_19_BASE_IDX                                                   3
13840 #define mmMPC_RMU0_SHAPER_RAMA_REGION_20_21                                                            0x069b
13841 #define mmMPC_RMU0_SHAPER_RAMA_REGION_20_21_BASE_IDX                                                   3
13842 #define mmMPC_RMU0_SHAPER_RAMA_REGION_22_23                                                            0x069c
13843 #define mmMPC_RMU0_SHAPER_RAMA_REGION_22_23_BASE_IDX                                                   3
13844 #define mmMPC_RMU0_SHAPER_RAMA_REGION_24_25                                                            0x069d
13845 #define mmMPC_RMU0_SHAPER_RAMA_REGION_24_25_BASE_IDX                                                   3
13846 #define mmMPC_RMU0_SHAPER_RAMA_REGION_26_27                                                            0x069e
13847 #define mmMPC_RMU0_SHAPER_RAMA_REGION_26_27_BASE_IDX                                                   3
13848 #define mmMPC_RMU0_SHAPER_RAMA_REGION_28_29                                                            0x069f
13849 #define mmMPC_RMU0_SHAPER_RAMA_REGION_28_29_BASE_IDX                                                   3
13850 #define mmMPC_RMU0_SHAPER_RAMA_REGION_30_31                                                            0x06a0
13851 #define mmMPC_RMU0_SHAPER_RAMA_REGION_30_31_BASE_IDX                                                   3
13852 #define mmMPC_RMU0_SHAPER_RAMA_REGION_32_33                                                            0x06a1
13853 #define mmMPC_RMU0_SHAPER_RAMA_REGION_32_33_BASE_IDX                                                   3
13854 #define mmMPC_RMU0_SHAPER_RAMB_START_CNTL_B                                                            0x06a2
13855 #define mmMPC_RMU0_SHAPER_RAMB_START_CNTL_B_BASE_IDX                                                   3
13856 #define mmMPC_RMU0_SHAPER_RAMB_START_CNTL_G                                                            0x06a3
13857 #define mmMPC_RMU0_SHAPER_RAMB_START_CNTL_G_BASE_IDX                                                   3
13858 #define mmMPC_RMU0_SHAPER_RAMB_START_CNTL_R                                                            0x06a4
13859 #define mmMPC_RMU0_SHAPER_RAMB_START_CNTL_R_BASE_IDX                                                   3
13860 #define mmMPC_RMU0_SHAPER_RAMB_END_CNTL_B                                                              0x06a5
13861 #define mmMPC_RMU0_SHAPER_RAMB_END_CNTL_B_BASE_IDX                                                     3
13862 #define mmMPC_RMU0_SHAPER_RAMB_END_CNTL_G                                                              0x06a6
13863 #define mmMPC_RMU0_SHAPER_RAMB_END_CNTL_G_BASE_IDX                                                     3
13864 #define mmMPC_RMU0_SHAPER_RAMB_END_CNTL_R                                                              0x06a7
13865 #define mmMPC_RMU0_SHAPER_RAMB_END_CNTL_R_BASE_IDX                                                     3
13866 #define mmMPC_RMU0_SHAPER_RAMB_REGION_0_1                                                              0x06a8
13867 #define mmMPC_RMU0_SHAPER_RAMB_REGION_0_1_BASE_IDX                                                     3
13868 #define mmMPC_RMU0_SHAPER_RAMB_REGION_2_3                                                              0x06a9
13869 #define mmMPC_RMU0_SHAPER_RAMB_REGION_2_3_BASE_IDX                                                     3
13870 #define mmMPC_RMU0_SHAPER_RAMB_REGION_4_5                                                              0x06aa
13871 #define mmMPC_RMU0_SHAPER_RAMB_REGION_4_5_BASE_IDX                                                     3
13872 #define mmMPC_RMU0_SHAPER_RAMB_REGION_6_7                                                              0x06ab
13873 #define mmMPC_RMU0_SHAPER_RAMB_REGION_6_7_BASE_IDX                                                     3
13874 #define mmMPC_RMU0_SHAPER_RAMB_REGION_8_9                                                              0x06ac
13875 #define mmMPC_RMU0_SHAPER_RAMB_REGION_8_9_BASE_IDX                                                     3
13876 #define mmMPC_RMU0_SHAPER_RAMB_REGION_10_11                                                            0x06ad
13877 #define mmMPC_RMU0_SHAPER_RAMB_REGION_10_11_BASE_IDX                                                   3
13878 #define mmMPC_RMU0_SHAPER_RAMB_REGION_12_13                                                            0x06ae
13879 #define mmMPC_RMU0_SHAPER_RAMB_REGION_12_13_BASE_IDX                                                   3
13880 #define mmMPC_RMU0_SHAPER_RAMB_REGION_14_15                                                            0x06af
13881 #define mmMPC_RMU0_SHAPER_RAMB_REGION_14_15_BASE_IDX                                                   3
13882 #define mmMPC_RMU0_SHAPER_RAMB_REGION_16_17                                                            0x06b0
13883 #define mmMPC_RMU0_SHAPER_RAMB_REGION_16_17_BASE_IDX                                                   3
13884 #define mmMPC_RMU0_SHAPER_RAMB_REGION_18_19                                                            0x06b1
13885 #define mmMPC_RMU0_SHAPER_RAMB_REGION_18_19_BASE_IDX                                                   3
13886 #define mmMPC_RMU0_SHAPER_RAMB_REGION_20_21                                                            0x06b2
13887 #define mmMPC_RMU0_SHAPER_RAMB_REGION_20_21_BASE_IDX                                                   3
13888 #define mmMPC_RMU0_SHAPER_RAMB_REGION_22_23                                                            0x06b3
13889 #define mmMPC_RMU0_SHAPER_RAMB_REGION_22_23_BASE_IDX                                                   3
13890 #define mmMPC_RMU0_SHAPER_RAMB_REGION_24_25                                                            0x06b4
13891 #define mmMPC_RMU0_SHAPER_RAMB_REGION_24_25_BASE_IDX                                                   3
13892 #define mmMPC_RMU0_SHAPER_RAMB_REGION_26_27                                                            0x06b5
13893 #define mmMPC_RMU0_SHAPER_RAMB_REGION_26_27_BASE_IDX                                                   3
13894 #define mmMPC_RMU0_SHAPER_RAMB_REGION_28_29                                                            0x06b6
13895 #define mmMPC_RMU0_SHAPER_RAMB_REGION_28_29_BASE_IDX                                                   3
13896 #define mmMPC_RMU0_SHAPER_RAMB_REGION_30_31                                                            0x06b7
13897 #define mmMPC_RMU0_SHAPER_RAMB_REGION_30_31_BASE_IDX                                                   3
13898 #define mmMPC_RMU0_SHAPER_RAMB_REGION_32_33                                                            0x06b8
13899 #define mmMPC_RMU0_SHAPER_RAMB_REGION_32_33_BASE_IDX                                                   3
13900 #define mmMPC_RMU0_3DLUT_MODE                                                                          0x06b9
13901 #define mmMPC_RMU0_3DLUT_MODE_BASE_IDX                                                                 3
13902 #define mmMPC_RMU0_3DLUT_INDEX                                                                         0x06ba
13903 #define mmMPC_RMU0_3DLUT_INDEX_BASE_IDX                                                                3
13904 #define mmMPC_RMU0_3DLUT_DATA                                                                          0x06bb
13905 #define mmMPC_RMU0_3DLUT_DATA_BASE_IDX                                                                 3
13906 #define mmMPC_RMU0_3DLUT_DATA_30BIT                                                                    0x06bc
13907 #define mmMPC_RMU0_3DLUT_DATA_30BIT_BASE_IDX                                                           3
13908 #define mmMPC_RMU0_3DLUT_READ_WRITE_CONTROL                                                            0x06bd
13909 #define mmMPC_RMU0_3DLUT_READ_WRITE_CONTROL_BASE_IDX                                                   3
13910 #define mmMPC_RMU0_3DLUT_OUT_NORM_FACTOR                                                               0x06be
13911 #define mmMPC_RMU0_3DLUT_OUT_NORM_FACTOR_BASE_IDX                                                      3
13912 #define mmMPC_RMU0_3DLUT_OUT_OFFSET_R                                                                  0x06bf
13913 #define mmMPC_RMU0_3DLUT_OUT_OFFSET_R_BASE_IDX                                                         3
13914 #define mmMPC_RMU0_3DLUT_OUT_OFFSET_G                                                                  0x06c0
13915 #define mmMPC_RMU0_3DLUT_OUT_OFFSET_G_BASE_IDX                                                         3
13916 #define mmMPC_RMU0_3DLUT_OUT_OFFSET_B                                                                  0x06c1
13917 #define mmMPC_RMU0_3DLUT_OUT_OFFSET_B_BASE_IDX                                                         3
13918 #define mmMPC_RMU1_SHAPER_CONTROL                                                                      0x06c2
13919 #define mmMPC_RMU1_SHAPER_CONTROL_BASE_IDX                                                             3
13920 #define mmMPC_RMU1_SHAPER_OFFSET_R                                                                     0x06c3
13921 #define mmMPC_RMU1_SHAPER_OFFSET_R_BASE_IDX                                                            3
13922 #define mmMPC_RMU1_SHAPER_OFFSET_G                                                                     0x06c4
13923 #define mmMPC_RMU1_SHAPER_OFFSET_G_BASE_IDX                                                            3
13924 #define mmMPC_RMU1_SHAPER_OFFSET_B                                                                     0x06c5
13925 #define mmMPC_RMU1_SHAPER_OFFSET_B_BASE_IDX                                                            3
13926 #define mmMPC_RMU1_SHAPER_SCALE_R                                                                      0x06c6
13927 #define mmMPC_RMU1_SHAPER_SCALE_R_BASE_IDX                                                             3
13928 #define mmMPC_RMU1_SHAPER_SCALE_G_B                                                                    0x06c7
13929 #define mmMPC_RMU1_SHAPER_SCALE_G_B_BASE_IDX                                                           3
13930 #define mmMPC_RMU1_SHAPER_LUT_INDEX                                                                    0x06c8
13931 #define mmMPC_RMU1_SHAPER_LUT_INDEX_BASE_IDX                                                           3
13932 #define mmMPC_RMU1_SHAPER_LUT_DATA                                                                     0x06c9
13933 #define mmMPC_RMU1_SHAPER_LUT_DATA_BASE_IDX                                                            3
13934 #define mmMPC_RMU1_SHAPER_LUT_WRITE_EN_MASK                                                            0x06ca
13935 #define mmMPC_RMU1_SHAPER_LUT_WRITE_EN_MASK_BASE_IDX                                                   3
13936 #define mmMPC_RMU1_SHAPER_RAMA_START_CNTL_B                                                            0x06cb
13937 #define mmMPC_RMU1_SHAPER_RAMA_START_CNTL_B_BASE_IDX                                                   3
13938 #define mmMPC_RMU1_SHAPER_RAMA_START_CNTL_G                                                            0x06cc
13939 #define mmMPC_RMU1_SHAPER_RAMA_START_CNTL_G_BASE_IDX                                                   3
13940 #define mmMPC_RMU1_SHAPER_RAMA_START_CNTL_R                                                            0x06cd
13941 #define mmMPC_RMU1_SHAPER_RAMA_START_CNTL_R_BASE_IDX                                                   3
13942 #define mmMPC_RMU1_SHAPER_RAMA_END_CNTL_B                                                              0x06ce
13943 #define mmMPC_RMU1_SHAPER_RAMA_END_CNTL_B_BASE_IDX                                                     3
13944 #define mmMPC_RMU1_SHAPER_RAMA_END_CNTL_G                                                              0x06cf
13945 #define mmMPC_RMU1_SHAPER_RAMA_END_CNTL_G_BASE_IDX                                                     3
13946 #define mmMPC_RMU1_SHAPER_RAMA_END_CNTL_R                                                              0x06d0
13947 #define mmMPC_RMU1_SHAPER_RAMA_END_CNTL_R_BASE_IDX                                                     3
13948 #define mmMPC_RMU1_SHAPER_RAMA_REGION_0_1                                                              0x06d1
13949 #define mmMPC_RMU1_SHAPER_RAMA_REGION_0_1_BASE_IDX                                                     3
13950 #define mmMPC_RMU1_SHAPER_RAMA_REGION_2_3                                                              0x06d2
13951 #define mmMPC_RMU1_SHAPER_RAMA_REGION_2_3_BASE_IDX                                                     3
13952 #define mmMPC_RMU1_SHAPER_RAMA_REGION_4_5                                                              0x06d3
13953 #define mmMPC_RMU1_SHAPER_RAMA_REGION_4_5_BASE_IDX                                                     3
13954 #define mmMPC_RMU1_SHAPER_RAMA_REGION_6_7                                                              0x06d4
13955 #define mmMPC_RMU1_SHAPER_RAMA_REGION_6_7_BASE_IDX                                                     3
13956 #define mmMPC_RMU1_SHAPER_RAMA_REGION_8_9                                                              0x06d5
13957 #define mmMPC_RMU1_SHAPER_RAMA_REGION_8_9_BASE_IDX                                                     3
13958 #define mmMPC_RMU1_SHAPER_RAMA_REGION_10_11                                                            0x06d6
13959 #define mmMPC_RMU1_SHAPER_RAMA_REGION_10_11_BASE_IDX                                                   3
13960 #define mmMPC_RMU1_SHAPER_RAMA_REGION_12_13                                                            0x06d7
13961 #define mmMPC_RMU1_SHAPER_RAMA_REGION_12_13_BASE_IDX                                                   3
13962 #define mmMPC_RMU1_SHAPER_RAMA_REGION_14_15                                                            0x06d8
13963 #define mmMPC_RMU1_SHAPER_RAMA_REGION_14_15_BASE_IDX                                                   3
13964 #define mmMPC_RMU1_SHAPER_RAMA_REGION_16_17                                                            0x06d9
13965 #define mmMPC_RMU1_SHAPER_RAMA_REGION_16_17_BASE_IDX                                                   3
13966 #define mmMPC_RMU1_SHAPER_RAMA_REGION_18_19                                                            0x06da
13967 #define mmMPC_RMU1_SHAPER_RAMA_REGION_18_19_BASE_IDX                                                   3
13968 #define mmMPC_RMU1_SHAPER_RAMA_REGION_20_21                                                            0x06db
13969 #define mmMPC_RMU1_SHAPER_RAMA_REGION_20_21_BASE_IDX                                                   3
13970 #define mmMPC_RMU1_SHAPER_RAMA_REGION_22_23                                                            0x06dc
13971 #define mmMPC_RMU1_SHAPER_RAMA_REGION_22_23_BASE_IDX                                                   3
13972 #define mmMPC_RMU1_SHAPER_RAMA_REGION_24_25                                                            0x06dd
13973 #define mmMPC_RMU1_SHAPER_RAMA_REGION_24_25_BASE_IDX                                                   3
13974 #define mmMPC_RMU1_SHAPER_RAMA_REGION_26_27                                                            0x06de
13975 #define mmMPC_RMU1_SHAPER_RAMA_REGION_26_27_BASE_IDX                                                   3
13976 #define mmMPC_RMU1_SHAPER_RAMA_REGION_28_29                                                            0x06df
13977 #define mmMPC_RMU1_SHAPER_RAMA_REGION_28_29_BASE_IDX                                                   3
13978 #define mmMPC_RMU1_SHAPER_RAMA_REGION_30_31                                                            0x06e0
13979 #define mmMPC_RMU1_SHAPER_RAMA_REGION_30_31_BASE_IDX                                                   3
13980 #define mmMPC_RMU1_SHAPER_RAMA_REGION_32_33                                                            0x06e1
13981 #define mmMPC_RMU1_SHAPER_RAMA_REGION_32_33_BASE_IDX                                                   3
13982 #define mmMPC_RMU1_SHAPER_RAMB_START_CNTL_B                                                            0x06e2
13983 #define mmMPC_RMU1_SHAPER_RAMB_START_CNTL_B_BASE_IDX                                                   3
13984 #define mmMPC_RMU1_SHAPER_RAMB_START_CNTL_G                                                            0x06e3
13985 #define mmMPC_RMU1_SHAPER_RAMB_START_CNTL_G_BASE_IDX                                                   3
13986 #define mmMPC_RMU1_SHAPER_RAMB_START_CNTL_R                                                            0x06e4
13987 #define mmMPC_RMU1_SHAPER_RAMB_START_CNTL_R_BASE_IDX                                                   3
13988 #define mmMPC_RMU1_SHAPER_RAMB_END_CNTL_B                                                              0x06e5
13989 #define mmMPC_RMU1_SHAPER_RAMB_END_CNTL_B_BASE_IDX                                                     3
13990 #define mmMPC_RMU1_SHAPER_RAMB_END_CNTL_G                                                              0x06e6
13991 #define mmMPC_RMU1_SHAPER_RAMB_END_CNTL_G_BASE_IDX                                                     3
13992 #define mmMPC_RMU1_SHAPER_RAMB_END_CNTL_R                                                              0x06e7
13993 #define mmMPC_RMU1_SHAPER_RAMB_END_CNTL_R_BASE_IDX                                                     3
13994 #define mmMPC_RMU1_SHAPER_RAMB_REGION_0_1                                                              0x06e8
13995 #define mmMPC_RMU1_SHAPER_RAMB_REGION_0_1_BASE_IDX                                                     3
13996 #define mmMPC_RMU1_SHAPER_RAMB_REGION_2_3                                                              0x06e9
13997 #define mmMPC_RMU1_SHAPER_RAMB_REGION_2_3_BASE_IDX                                                     3
13998 #define mmMPC_RMU1_SHAPER_RAMB_REGION_4_5                                                              0x06ea
13999 #define mmMPC_RMU1_SHAPER_RAMB_REGION_4_5_BASE_IDX                                                     3
14000 #define mmMPC_RMU1_SHAPER_RAMB_REGION_6_7                                                              0x06eb
14001 #define mmMPC_RMU1_SHAPER_RAMB_REGION_6_7_BASE_IDX                                                     3
14002 #define mmMPC_RMU1_SHAPER_RAMB_REGION_8_9                                                              0x06ec
14003 #define mmMPC_RMU1_SHAPER_RAMB_REGION_8_9_BASE_IDX                                                     3
14004 #define mmMPC_RMU1_SHAPER_RAMB_REGION_10_11                                                            0x06ed
14005 #define mmMPC_RMU1_SHAPER_RAMB_REGION_10_11_BASE_IDX                                                   3
14006 #define mmMPC_RMU1_SHAPER_RAMB_REGION_12_13                                                            0x06ee
14007 #define mmMPC_RMU1_SHAPER_RAMB_REGION_12_13_BASE_IDX                                                   3
14008 #define mmMPC_RMU1_SHAPER_RAMB_REGION_14_15                                                            0x06ef
14009 #define mmMPC_RMU1_SHAPER_RAMB_REGION_14_15_BASE_IDX                                                   3
14010 #define mmMPC_RMU1_SHAPER_RAMB_REGION_16_17                                                            0x06f0
14011 #define mmMPC_RMU1_SHAPER_RAMB_REGION_16_17_BASE_IDX                                                   3
14012 #define mmMPC_RMU1_SHAPER_RAMB_REGION_18_19                                                            0x06f1
14013 #define mmMPC_RMU1_SHAPER_RAMB_REGION_18_19_BASE_IDX                                                   3
14014 #define mmMPC_RMU1_SHAPER_RAMB_REGION_20_21                                                            0x06f2
14015 #define mmMPC_RMU1_SHAPER_RAMB_REGION_20_21_BASE_IDX                                                   3
14016 #define mmMPC_RMU1_SHAPER_RAMB_REGION_22_23                                                            0x06f3
14017 #define mmMPC_RMU1_SHAPER_RAMB_REGION_22_23_BASE_IDX                                                   3
14018 #define mmMPC_RMU1_SHAPER_RAMB_REGION_24_25                                                            0x06f4
14019 #define mmMPC_RMU1_SHAPER_RAMB_REGION_24_25_BASE_IDX                                                   3
14020 #define mmMPC_RMU1_SHAPER_RAMB_REGION_26_27                                                            0x06f5
14021 #define mmMPC_RMU1_SHAPER_RAMB_REGION_26_27_BASE_IDX                                                   3
14022 #define mmMPC_RMU1_SHAPER_RAMB_REGION_28_29                                                            0x06f6
14023 #define mmMPC_RMU1_SHAPER_RAMB_REGION_28_29_BASE_IDX                                                   3
14024 #define mmMPC_RMU1_SHAPER_RAMB_REGION_30_31                                                            0x06f7
14025 #define mmMPC_RMU1_SHAPER_RAMB_REGION_30_31_BASE_IDX                                                   3
14026 #define mmMPC_RMU1_SHAPER_RAMB_REGION_32_33                                                            0x06f8
14027 #define mmMPC_RMU1_SHAPER_RAMB_REGION_32_33_BASE_IDX                                                   3
14028 #define mmMPC_RMU1_3DLUT_MODE                                                                          0x06f9
14029 #define mmMPC_RMU1_3DLUT_MODE_BASE_IDX                                                                 3
14030 #define mmMPC_RMU1_3DLUT_INDEX                                                                         0x06fa
14031 #define mmMPC_RMU1_3DLUT_INDEX_BASE_IDX                                                                3
14032 #define mmMPC_RMU1_3DLUT_DATA                                                                          0x06fb
14033 #define mmMPC_RMU1_3DLUT_DATA_BASE_IDX                                                                 3
14034 #define mmMPC_RMU1_3DLUT_DATA_30BIT                                                                    0x06fc
14035 #define mmMPC_RMU1_3DLUT_DATA_30BIT_BASE_IDX                                                           3
14036 #define mmMPC_RMU1_3DLUT_READ_WRITE_CONTROL                                                            0x06fd
14037 #define mmMPC_RMU1_3DLUT_READ_WRITE_CONTROL_BASE_IDX                                                   3
14038 #define mmMPC_RMU1_3DLUT_OUT_NORM_FACTOR                                                               0x06fe
14039 #define mmMPC_RMU1_3DLUT_OUT_NORM_FACTOR_BASE_IDX                                                      3
14040 #define mmMPC_RMU1_3DLUT_OUT_OFFSET_R                                                                  0x06ff
14041 #define mmMPC_RMU1_3DLUT_OUT_OFFSET_R_BASE_IDX                                                         3
14042 #define mmMPC_RMU1_3DLUT_OUT_OFFSET_G                                                                  0x0700
14043 #define mmMPC_RMU1_3DLUT_OUT_OFFSET_G_BASE_IDX                                                         3
14044 #define mmMPC_RMU1_3DLUT_OUT_OFFSET_B                                                                  0x0701
14045 #define mmMPC_RMU1_3DLUT_OUT_OFFSET_B_BASE_IDX                                                         3
14046 #define mmMPC_RMU2_SHAPER_CONTROL                                                                      0x0702
14047 #define mmMPC_RMU2_SHAPER_CONTROL_BASE_IDX                                                             3
14048 #define mmMPC_RMU2_SHAPER_OFFSET_R                                                                     0x0703
14049 #define mmMPC_RMU2_SHAPER_OFFSET_R_BASE_IDX                                                            3
14050 #define mmMPC_RMU2_SHAPER_OFFSET_G                                                                     0x0704
14051 #define mmMPC_RMU2_SHAPER_OFFSET_G_BASE_IDX                                                            3
14052 #define mmMPC_RMU2_SHAPER_OFFSET_B                                                                     0x0705
14053 #define mmMPC_RMU2_SHAPER_OFFSET_B_BASE_IDX                                                            3
14054 #define mmMPC_RMU2_SHAPER_SCALE_R                                                                      0x0706
14055 #define mmMPC_RMU2_SHAPER_SCALE_R_BASE_IDX                                                             3
14056 #define mmMPC_RMU2_SHAPER_SCALE_G_B                                                                    0x0707
14057 #define mmMPC_RMU2_SHAPER_SCALE_G_B_BASE_IDX                                                           3
14058 #define mmMPC_RMU2_SHAPER_LUT_INDEX                                                                    0x0708
14059 #define mmMPC_RMU2_SHAPER_LUT_INDEX_BASE_IDX                                                           3
14060 #define mmMPC_RMU2_SHAPER_LUT_DATA                                                                     0x0709
14061 #define mmMPC_RMU2_SHAPER_LUT_DATA_BASE_IDX                                                            3
14062 #define mmMPC_RMU2_SHAPER_LUT_WRITE_EN_MASK                                                            0x070a
14063 #define mmMPC_RMU2_SHAPER_LUT_WRITE_EN_MASK_BASE_IDX                                                   3
14064 #define mmMPC_RMU2_SHAPER_RAMA_START_CNTL_B                                                            0x070b
14065 #define mmMPC_RMU2_SHAPER_RAMA_START_CNTL_B_BASE_IDX                                                   3
14066 #define mmMPC_RMU2_SHAPER_RAMA_START_CNTL_G                                                            0x070c
14067 #define mmMPC_RMU2_SHAPER_RAMA_START_CNTL_G_BASE_IDX                                                   3
14068 #define mmMPC_RMU2_SHAPER_RAMA_START_CNTL_R                                                            0x070d
14069 #define mmMPC_RMU2_SHAPER_RAMA_START_CNTL_R_BASE_IDX                                                   3
14070 #define mmMPC_RMU2_SHAPER_RAMA_END_CNTL_B                                                              0x070e
14071 #define mmMPC_RMU2_SHAPER_RAMA_END_CNTL_B_BASE_IDX                                                     3
14072 #define mmMPC_RMU2_SHAPER_RAMA_END_CNTL_G                                                              0x070f
14073 #define mmMPC_RMU2_SHAPER_RAMA_END_CNTL_G_BASE_IDX                                                     3
14074 #define mmMPC_RMU2_SHAPER_RAMA_END_CNTL_R                                                              0x0710
14075 #define mmMPC_RMU2_SHAPER_RAMA_END_CNTL_R_BASE_IDX                                                     3
14076 #define mmMPC_RMU2_SHAPER_RAMA_REGION_0_1                                                              0x0711
14077 #define mmMPC_RMU2_SHAPER_RAMA_REGION_0_1_BASE_IDX                                                     3
14078 #define mmMPC_RMU2_SHAPER_RAMA_REGION_2_3                                                              0x0712
14079 #define mmMPC_RMU2_SHAPER_RAMA_REGION_2_3_BASE_IDX                                                     3
14080 #define mmMPC_RMU2_SHAPER_RAMA_REGION_4_5                                                              0x0713
14081 #define mmMPC_RMU2_SHAPER_RAMA_REGION_4_5_BASE_IDX                                                     3
14082 #define mmMPC_RMU2_SHAPER_RAMA_REGION_6_7                                                              0x0714
14083 #define mmMPC_RMU2_SHAPER_RAMA_REGION_6_7_BASE_IDX                                                     3
14084 #define mmMPC_RMU2_SHAPER_RAMA_REGION_8_9                                                              0x0715
14085 #define mmMPC_RMU2_SHAPER_RAMA_REGION_8_9_BASE_IDX                                                     3
14086 #define mmMPC_RMU2_SHAPER_RAMA_REGION_10_11                                                            0x0716
14087 #define mmMPC_RMU2_SHAPER_RAMA_REGION_10_11_BASE_IDX                                                   3
14088 #define mmMPC_RMU2_SHAPER_RAMA_REGION_12_13                                                            0x0717
14089 #define mmMPC_RMU2_SHAPER_RAMA_REGION_12_13_BASE_IDX                                                   3
14090 #define mmMPC_RMU2_SHAPER_RAMA_REGION_14_15                                                            0x0718
14091 #define mmMPC_RMU2_SHAPER_RAMA_REGION_14_15_BASE_IDX                                                   3
14092 #define mmMPC_RMU2_SHAPER_RAMA_REGION_16_17                                                            0x0719
14093 #define mmMPC_RMU2_SHAPER_RAMA_REGION_16_17_BASE_IDX                                                   3
14094 #define mmMPC_RMU2_SHAPER_RAMA_REGION_18_19                                                            0x071a
14095 #define mmMPC_RMU2_SHAPER_RAMA_REGION_18_19_BASE_IDX                                                   3
14096 #define mmMPC_RMU2_SHAPER_RAMA_REGION_20_21                                                            0x071b
14097 #define mmMPC_RMU2_SHAPER_RAMA_REGION_20_21_BASE_IDX                                                   3
14098 #define mmMPC_RMU2_SHAPER_RAMA_REGION_22_23                                                            0x071c
14099 #define mmMPC_RMU2_SHAPER_RAMA_REGION_22_23_BASE_IDX                                                   3
14100 #define mmMPC_RMU2_SHAPER_RAMA_REGION_24_25                                                            0x071d
14101 #define mmMPC_RMU2_SHAPER_RAMA_REGION_24_25_BASE_IDX                                                   3
14102 #define mmMPC_RMU2_SHAPER_RAMA_REGION_26_27                                                            0x071e
14103 #define mmMPC_RMU2_SHAPER_RAMA_REGION_26_27_BASE_IDX                                                   3
14104 #define mmMPC_RMU2_SHAPER_RAMA_REGION_28_29                                                            0x071f
14105 #define mmMPC_RMU2_SHAPER_RAMA_REGION_28_29_BASE_IDX                                                   3
14106 #define mmMPC_RMU2_SHAPER_RAMA_REGION_30_31                                                            0x0720
14107 #define mmMPC_RMU2_SHAPER_RAMA_REGION_30_31_BASE_IDX                                                   3
14108 #define mmMPC_RMU2_SHAPER_RAMA_REGION_32_33                                                            0x0721
14109 #define mmMPC_RMU2_SHAPER_RAMA_REGION_32_33_BASE_IDX                                                   3
14110 #define mmMPC_RMU2_SHAPER_RAMB_START_CNTL_B                                                            0x0722
14111 #define mmMPC_RMU2_SHAPER_RAMB_START_CNTL_B_BASE_IDX                                                   3
14112 #define mmMPC_RMU2_SHAPER_RAMB_START_CNTL_G                                                            0x0723
14113 #define mmMPC_RMU2_SHAPER_RAMB_START_CNTL_G_BASE_IDX                                                   3
14114 #define mmMPC_RMU2_SHAPER_RAMB_START_CNTL_R                                                            0x0724
14115 #define mmMPC_RMU2_SHAPER_RAMB_START_CNTL_R_BASE_IDX                                                   3
14116 #define mmMPC_RMU2_SHAPER_RAMB_END_CNTL_B                                                              0x0725
14117 #define mmMPC_RMU2_SHAPER_RAMB_END_CNTL_B_BASE_IDX                                                     3
14118 #define mmMPC_RMU2_SHAPER_RAMB_END_CNTL_G                                                              0x0726
14119 #define mmMPC_RMU2_SHAPER_RAMB_END_CNTL_G_BASE_IDX                                                     3
14120 #define mmMPC_RMU2_SHAPER_RAMB_END_CNTL_R                                                              0x0727
14121 #define mmMPC_RMU2_SHAPER_RAMB_END_CNTL_R_BASE_IDX                                                     3
14122 #define mmMPC_RMU2_SHAPER_RAMB_REGION_0_1                                                              0x0728
14123 #define mmMPC_RMU2_SHAPER_RAMB_REGION_0_1_BASE_IDX                                                     3
14124 #define mmMPC_RMU2_SHAPER_RAMB_REGION_2_3                                                              0x0729
14125 #define mmMPC_RMU2_SHAPER_RAMB_REGION_2_3_BASE_IDX                                                     3
14126 #define mmMPC_RMU2_SHAPER_RAMB_REGION_4_5                                                              0x072a
14127 #define mmMPC_RMU2_SHAPER_RAMB_REGION_4_5_BASE_IDX                                                     3
14128 #define mmMPC_RMU2_SHAPER_RAMB_REGION_6_7                                                              0x072b
14129 #define mmMPC_RMU2_SHAPER_RAMB_REGION_6_7_BASE_IDX                                                     3
14130 #define mmMPC_RMU2_SHAPER_RAMB_REGION_8_9                                                              0x072c
14131 #define mmMPC_RMU2_SHAPER_RAMB_REGION_8_9_BASE_IDX                                                     3
14132 #define mmMPC_RMU2_SHAPER_RAMB_REGION_10_11                                                            0x072d
14133 #define mmMPC_RMU2_SHAPER_RAMB_REGION_10_11_BASE_IDX                                                   3
14134 #define mmMPC_RMU2_SHAPER_RAMB_REGION_12_13                                                            0x072e
14135 #define mmMPC_RMU2_SHAPER_RAMB_REGION_12_13_BASE_IDX                                                   3
14136 #define mmMPC_RMU2_SHAPER_RAMB_REGION_14_15                                                            0x072f
14137 #define mmMPC_RMU2_SHAPER_RAMB_REGION_14_15_BASE_IDX                                                   3
14138 #define mmMPC_RMU2_SHAPER_RAMB_REGION_16_17                                                            0x0730
14139 #define mmMPC_RMU2_SHAPER_RAMB_REGION_16_17_BASE_IDX                                                   3
14140 #define mmMPC_RMU2_SHAPER_RAMB_REGION_18_19                                                            0x0731
14141 #define mmMPC_RMU2_SHAPER_RAMB_REGION_18_19_BASE_IDX                                                   3
14142 #define mmMPC_RMU2_SHAPER_RAMB_REGION_20_21                                                            0x0732
14143 #define mmMPC_RMU2_SHAPER_RAMB_REGION_20_21_BASE_IDX                                                   3
14144 #define mmMPC_RMU2_SHAPER_RAMB_REGION_22_23                                                            0x0733
14145 #define mmMPC_RMU2_SHAPER_RAMB_REGION_22_23_BASE_IDX                                                   3
14146 #define mmMPC_RMU2_SHAPER_RAMB_REGION_24_25                                                            0x0734
14147 #define mmMPC_RMU2_SHAPER_RAMB_REGION_24_25_BASE_IDX                                                   3
14148 #define mmMPC_RMU2_SHAPER_RAMB_REGION_26_27                                                            0x0735
14149 #define mmMPC_RMU2_SHAPER_RAMB_REGION_26_27_BASE_IDX                                                   3
14150 #define mmMPC_RMU2_SHAPER_RAMB_REGION_28_29                                                            0x0736
14151 #define mmMPC_RMU2_SHAPER_RAMB_REGION_28_29_BASE_IDX                                                   3
14152 #define mmMPC_RMU2_SHAPER_RAMB_REGION_30_31                                                            0x0737
14153 #define mmMPC_RMU2_SHAPER_RAMB_REGION_30_31_BASE_IDX                                                   3
14154 #define mmMPC_RMU2_SHAPER_RAMB_REGION_32_33                                                            0x0738
14155 #define mmMPC_RMU2_SHAPER_RAMB_REGION_32_33_BASE_IDX                                                   3
14156 #define mmMPC_RMU2_3DLUT_MODE                                                                          0x0739
14157 #define mmMPC_RMU2_3DLUT_MODE_BASE_IDX                                                                 3
14158 #define mmMPC_RMU2_3DLUT_INDEX                                                                         0x073a
14159 #define mmMPC_RMU2_3DLUT_INDEX_BASE_IDX                                                                3
14160 #define mmMPC_RMU2_3DLUT_DATA                                                                          0x073b
14161 #define mmMPC_RMU2_3DLUT_DATA_BASE_IDX                                                                 3
14162 #define mmMPC_RMU2_3DLUT_DATA_30BIT                                                                    0x073c
14163 #define mmMPC_RMU2_3DLUT_DATA_30BIT_BASE_IDX                                                           3
14164 #define mmMPC_RMU2_3DLUT_READ_WRITE_CONTROL                                                            0x073d
14165 #define mmMPC_RMU2_3DLUT_READ_WRITE_CONTROL_BASE_IDX                                                   3
14166 #define mmMPC_RMU2_3DLUT_OUT_NORM_FACTOR                                                               0x073e
14167 #define mmMPC_RMU2_3DLUT_OUT_NORM_FACTOR_BASE_IDX                                                      3
14168 #define mmMPC_RMU2_3DLUT_OUT_OFFSET_R                                                                  0x073f
14169 #define mmMPC_RMU2_3DLUT_OUT_OFFSET_R_BASE_IDX                                                         3
14170 #define mmMPC_RMU2_3DLUT_OUT_OFFSET_G                                                                  0x0740
14171 #define mmMPC_RMU2_3DLUT_OUT_OFFSET_G_BASE_IDX                                                         3
14172 #define mmMPC_RMU2_3DLUT_OUT_OFFSET_B                                                                  0x0741
14173 #define mmMPC_RMU2_3DLUT_OUT_OFFSET_B_BASE_IDX                                                         3
14174 
14175 
14176 // addressBlock: dce_dc_mpc_mpc_dcperfmon_dc_perfmon_dispdec
14177 // base address: 0x1901c
14178 #define mmDC_PERFMON25_PERFCOUNTER_CNTL                                                                0x08c7
14179 #define mmDC_PERFMON25_PERFCOUNTER_CNTL_BASE_IDX                                                       3
14180 #define mmDC_PERFMON25_PERFCOUNTER_CNTL2                                                               0x08c8
14181 #define mmDC_PERFMON25_PERFCOUNTER_CNTL2_BASE_IDX                                                      3
14182 #define mmDC_PERFMON25_PERFCOUNTER_STATE                                                               0x08c9
14183 #define mmDC_PERFMON25_PERFCOUNTER_STATE_BASE_IDX                                                      3
14184 #define mmDC_PERFMON25_PERFMON_CNTL                                                                    0x08ca
14185 #define mmDC_PERFMON25_PERFMON_CNTL_BASE_IDX                                                           3
14186 #define mmDC_PERFMON25_PERFMON_CNTL2                                                                   0x08cb
14187 #define mmDC_PERFMON25_PERFMON_CNTL2_BASE_IDX                                                          3
14188 #define mmDC_PERFMON25_PERFMON_CVALUE_INT_MISC                                                         0x08cc
14189 #define mmDC_PERFMON25_PERFMON_CVALUE_INT_MISC_BASE_IDX                                                3
14190 #define mmDC_PERFMON25_PERFMON_CVALUE_LOW                                                              0x08cd
14191 #define mmDC_PERFMON25_PERFMON_CVALUE_LOW_BASE_IDX                                                     3
14192 #define mmDC_PERFMON25_PERFMON_HI                                                                      0x08ce
14193 #define mmDC_PERFMON25_PERFMON_HI_BASE_IDX                                                             3
14194 #define mmDC_PERFMON25_PERFMON_LOW                                                                     0x08cf
14195 #define mmDC_PERFMON25_PERFMON_LOW_BASE_IDX                                                            3
14196 // base address: 0x264f0
14197 #define mmDME5_DME_CONTROL                                                                             0x093c
14198 #define mmDME5_DME_CONTROL_BASE_IDX                                                                    3
14199 #define mmDME5_DME_MEMORY_CONTROL                                                                      0x093d
14200 #define mmDME5_DME_MEMORY_CONTROL_BASE_IDX                                                             3
14201 
14202 
14203 // addressBlock: dce_dc_hpo_hdmi_stream_enc0_hdcp2_hdcp2_dispdec
14204 // base address: 0x264f8
14205 
14206 
14207 
14208 
14209 // base address: 0x1a698
14210 #define mmDC_PERFMON26_PERFCOUNTER_CNTL                                                                0x0e66
14211 #define mmDC_PERFMON26_PERFCOUNTER_CNTL_BASE_IDX                                                       3
14212 #define mmDC_PERFMON26_PERFCOUNTER_CNTL2                                                               0x0e67
14213 #define mmDC_PERFMON26_PERFCOUNTER_CNTL2_BASE_IDX                                                      3
14214 #define mmDC_PERFMON26_PERFCOUNTER_STATE                                                               0x0e68
14215 #define mmDC_PERFMON26_PERFCOUNTER_STATE_BASE_IDX                                                      3
14216 #define mmDC_PERFMON26_PERFMON_CNTL                                                                    0x0e69
14217 #define mmDC_PERFMON26_PERFMON_CNTL_BASE_IDX                                                           3
14218 #define mmDC_PERFMON26_PERFMON_CNTL2                                                                   0x0e6a
14219 #define mmDC_PERFMON26_PERFMON_CNTL2_BASE_IDX                                                          3
14220 #define mmDC_PERFMON26_PERFMON_CVALUE_INT_MISC                                                         0x0e6b
14221 #define mmDC_PERFMON26_PERFMON_CVALUE_INT_MISC_BASE_IDX                                                3
14222 #define mmDC_PERFMON26_PERFMON_CVALUE_LOW                                                              0x0e6c
14223 #define mmDC_PERFMON26_PERFMON_CVALUE_LOW_BASE_IDX                                                     3
14224 #define mmDC_PERFMON26_PERFMON_HI                                                                      0x0e6d
14225 #define mmDC_PERFMON26_PERFMON_HI_BASE_IDX                                                             3
14226 #define mmDC_PERFMON26_PERFMON_LOW                                                                     0x0e6e
14227 #define mmDC_PERFMON26_PERFMON_LOW_BASE_IDX                                                            3
14228 
14229 
14230 // addressBlock: dce_dc_opp_abm0_dispdec
14231 // base address: 0x0
14232 #define mmABM0_BL1_PWM_AMBIENT_LIGHT_LEVEL                                                             0x0e7a
14233 #define mmABM0_BL1_PWM_AMBIENT_LIGHT_LEVEL_BASE_IDX                                                    3
14234 #define mmABM0_BL1_PWM_USER_LEVEL                                                                      0x0e7b
14235 #define mmABM0_BL1_PWM_USER_LEVEL_BASE_IDX                                                             3
14236 #define mmABM0_BL1_PWM_TARGET_ABM_LEVEL                                                                0x0e7c
14237 #define mmABM0_BL1_PWM_TARGET_ABM_LEVEL_BASE_IDX                                                       3
14238 #define mmABM0_BL1_PWM_CURRENT_ABM_LEVEL                                                               0x0e7d
14239 #define mmABM0_BL1_PWM_CURRENT_ABM_LEVEL_BASE_IDX                                                      3
14240 #define mmABM0_BL1_PWM_FINAL_DUTY_CYCLE                                                                0x0e7e
14241 #define mmABM0_BL1_PWM_FINAL_DUTY_CYCLE_BASE_IDX                                                       3
14242 #define mmABM0_BL1_PWM_MINIMUM_DUTY_CYCLE                                                              0x0e7f
14243 #define mmABM0_BL1_PWM_MINIMUM_DUTY_CYCLE_BASE_IDX                                                     3
14244 #define mmABM0_BL1_PWM_ABM_CNTL                                                                        0x0e80
14245 #define mmABM0_BL1_PWM_ABM_CNTL_BASE_IDX                                                               3
14246 #define mmABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE                                                           0x0e81
14247 #define mmABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE_BASE_IDX                                                  3
14248 #define mmABM0_BL1_PWM_GRP2_REG_LOCK                                                                   0x0e82
14249 #define mmABM0_BL1_PWM_GRP2_REG_LOCK_BASE_IDX                                                          3
14250 #define mmABM0_DC_ABM1_CNTL                                                                            0x0e83
14251 #define mmABM0_DC_ABM1_CNTL_BASE_IDX                                                                   3
14252 #define mmABM0_DC_ABM1_IPCSC_COEFF_SEL                                                                 0x0e84
14253 #define mmABM0_DC_ABM1_IPCSC_COEFF_SEL_BASE_IDX                                                        3
14254 #define mmABM0_DC_ABM1_ACE_OFFSET_SLOPE_0                                                              0x0e85
14255 #define mmABM0_DC_ABM1_ACE_OFFSET_SLOPE_0_BASE_IDX                                                     3
14256 #define mmABM0_DC_ABM1_ACE_OFFSET_SLOPE_1                                                              0x0e86
14257 #define mmABM0_DC_ABM1_ACE_OFFSET_SLOPE_1_BASE_IDX                                                     3
14258 #define mmABM0_DC_ABM1_ACE_OFFSET_SLOPE_2                                                              0x0e87
14259 #define mmABM0_DC_ABM1_ACE_OFFSET_SLOPE_2_BASE_IDX                                                     3
14260 #define mmABM0_DC_ABM1_ACE_OFFSET_SLOPE_3                                                              0x0e88
14261 #define mmABM0_DC_ABM1_ACE_OFFSET_SLOPE_3_BASE_IDX                                                     3
14262 #define mmABM0_DC_ABM1_ACE_OFFSET_SLOPE_4                                                              0x0e89
14263 #define mmABM0_DC_ABM1_ACE_OFFSET_SLOPE_4_BASE_IDX                                                     3
14264 #define mmABM0_DC_ABM1_ACE_THRES_12                                                                    0x0e8a
14265 #define mmABM0_DC_ABM1_ACE_THRES_12_BASE_IDX                                                           3
14266 #define mmABM0_DC_ABM1_ACE_THRES_34                                                                    0x0e8b
14267 #define mmABM0_DC_ABM1_ACE_THRES_34_BASE_IDX                                                           3
14268 #define mmABM0_DC_ABM1_ACE_CNTL_MISC                                                                   0x0e8c
14269 #define mmABM0_DC_ABM1_ACE_CNTL_MISC_BASE_IDX                                                          3
14270 #define mmABM0_DC_ABM1_HGLS_REG_READ_PROGRESS                                                          0x0e8e
14271 #define mmABM0_DC_ABM1_HGLS_REG_READ_PROGRESS_BASE_IDX                                                 3
14272 #define mmABM0_DC_ABM1_HG_MISC_CTRL                                                                    0x0e8f
14273 #define mmABM0_DC_ABM1_HG_MISC_CTRL_BASE_IDX                                                           3
14274 #define mmABM0_DC_ABM1_LS_SUM_OF_LUMA                                                                  0x0e90
14275 #define mmABM0_DC_ABM1_LS_SUM_OF_LUMA_BASE_IDX                                                         3
14276 #define mmABM0_DC_ABM1_LS_MIN_MAX_LUMA                                                                 0x0e91
14277 #define mmABM0_DC_ABM1_LS_MIN_MAX_LUMA_BASE_IDX                                                        3
14278 #define mmABM0_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA                                                        0x0e92
14279 #define mmABM0_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA_BASE_IDX                                               3
14280 #define mmABM0_DC_ABM1_LS_PIXEL_COUNT                                                                  0x0e93
14281 #define mmABM0_DC_ABM1_LS_PIXEL_COUNT_BASE_IDX                                                         3
14282 #define mmABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES                                                    0x0e94
14283 #define mmABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES_BASE_IDX                                           3
14284 #define mmABM0_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT                                                        0x0e95
14285 #define mmABM0_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT_BASE_IDX                                               3
14286 #define mmABM0_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT                                                        0x0e96
14287 #define mmABM0_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT_BASE_IDX                                               3
14288 #define mmABM0_DC_ABM1_HG_SAMPLE_RATE                                                                  0x0e97
14289 #define mmABM0_DC_ABM1_HG_SAMPLE_RATE_BASE_IDX                                                         3
14290 #define mmABM0_DC_ABM1_LS_SAMPLE_RATE                                                                  0x0e98
14291 #define mmABM0_DC_ABM1_LS_SAMPLE_RATE_BASE_IDX                                                         3
14292 #define mmABM0_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG                                                          0x0e99
14293 #define mmABM0_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG_BASE_IDX                                                 3
14294 #define mmABM0_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX                                                          0x0e9a
14295 #define mmABM0_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX_BASE_IDX                                                 3
14296 #define mmABM0_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX                                                         0x0e9b
14297 #define mmABM0_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX_BASE_IDX                                                3
14298 #define mmABM0_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX                                                        0x0e9c
14299 #define mmABM0_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX_BASE_IDX                                               3
14300 #define mmABM0_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX                                                        0x0e9d
14301 #define mmABM0_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX_BASE_IDX                                               3
14302 #define mmABM0_DC_ABM1_HG_RESULT_1                                                                     0x0e9e
14303 #define mmABM0_DC_ABM1_HG_RESULT_1_BASE_IDX                                                            3
14304 #define mmABM0_DC_ABM1_HG_RESULT_2                                                                     0x0e9f
14305 #define mmABM0_DC_ABM1_HG_RESULT_2_BASE_IDX                                                            3
14306 #define mmABM0_DC_ABM1_HG_RESULT_3                                                                     0x0ea0
14307 #define mmABM0_DC_ABM1_HG_RESULT_3_BASE_IDX                                                            3
14308 #define mmABM0_DC_ABM1_HG_RESULT_4                                                                     0x0ea1
14309 #define mmABM0_DC_ABM1_HG_RESULT_4_BASE_IDX                                                            3
14310 #define mmABM0_DC_ABM1_HG_RESULT_5                                                                     0x0ea2
14311 #define mmABM0_DC_ABM1_HG_RESULT_5_BASE_IDX                                                            3
14312 #define mmABM0_DC_ABM1_HG_RESULT_6                                                                     0x0ea3
14313 #define mmABM0_DC_ABM1_HG_RESULT_6_BASE_IDX                                                            3
14314 #define mmABM0_DC_ABM1_HG_RESULT_7                                                                     0x0ea4
14315 #define mmABM0_DC_ABM1_HG_RESULT_7_BASE_IDX                                                            3
14316 #define mmABM0_DC_ABM1_HG_RESULT_8                                                                     0x0ea5
14317 #define mmABM0_DC_ABM1_HG_RESULT_8_BASE_IDX                                                            3
14318 #define mmABM0_DC_ABM1_HG_RESULT_9                                                                     0x0ea6
14319 #define mmABM0_DC_ABM1_HG_RESULT_9_BASE_IDX                                                            3
14320 #define mmABM0_DC_ABM1_HG_RESULT_10                                                                    0x0ea7
14321 #define mmABM0_DC_ABM1_HG_RESULT_10_BASE_IDX                                                           3
14322 #define mmABM0_DC_ABM1_HG_RESULT_11                                                                    0x0ea8
14323 #define mmABM0_DC_ABM1_HG_RESULT_11_BASE_IDX                                                           3
14324 #define mmABM0_DC_ABM1_HG_RESULT_12                                                                    0x0ea9
14325 #define mmABM0_DC_ABM1_HG_RESULT_12_BASE_IDX                                                           3
14326 #define mmABM0_DC_ABM1_HG_RESULT_13                                                                    0x0eaa
14327 #define mmABM0_DC_ABM1_HG_RESULT_13_BASE_IDX                                                           3
14328 #define mmABM0_DC_ABM1_HG_RESULT_14                                                                    0x0eab
14329 #define mmABM0_DC_ABM1_HG_RESULT_14_BASE_IDX                                                           3
14330 #define mmABM0_DC_ABM1_HG_RESULT_15                                                                    0x0eac
14331 #define mmABM0_DC_ABM1_HG_RESULT_15_BASE_IDX                                                           3
14332 #define mmABM0_DC_ABM1_HG_RESULT_16                                                                    0x0ead
14333 #define mmABM0_DC_ABM1_HG_RESULT_16_BASE_IDX                                                           3
14334 #define mmABM0_DC_ABM1_HG_RESULT_17                                                                    0x0eae
14335 #define mmABM0_DC_ABM1_HG_RESULT_17_BASE_IDX                                                           3
14336 #define mmABM0_DC_ABM1_HG_RESULT_18                                                                    0x0eaf
14337 #define mmABM0_DC_ABM1_HG_RESULT_18_BASE_IDX                                                           3
14338 #define mmABM0_DC_ABM1_HG_RESULT_19                                                                    0x0eb0
14339 #define mmABM0_DC_ABM1_HG_RESULT_19_BASE_IDX                                                           3
14340 #define mmABM0_DC_ABM1_HG_RESULT_20                                                                    0x0eb1
14341 #define mmABM0_DC_ABM1_HG_RESULT_20_BASE_IDX                                                           3
14342 #define mmABM0_DC_ABM1_HG_RESULT_21                                                                    0x0eb2
14343 #define mmABM0_DC_ABM1_HG_RESULT_21_BASE_IDX                                                           3
14344 #define mmABM0_DC_ABM1_HG_RESULT_22                                                                    0x0eb3
14345 #define mmABM0_DC_ABM1_HG_RESULT_22_BASE_IDX                                                           3
14346 #define mmABM0_DC_ABM1_HG_RESULT_23                                                                    0x0eb4
14347 #define mmABM0_DC_ABM1_HG_RESULT_23_BASE_IDX                                                           3
14348 #define mmABM0_DC_ABM1_HG_RESULT_24                                                                    0x0eb5
14349 #define mmABM0_DC_ABM1_HG_RESULT_24_BASE_IDX                                                           3
14350 #define mmABM0_DC_ABM1_BL_MASTER_LOCK                                                                  0x0eb6
14351 #define mmABM0_DC_ABM1_BL_MASTER_LOCK_BASE_IDX                                                         3
14352 
14353 
14354 // addressBlock: dce_dc_opp_abm1_dispdec
14355 // base address: 0x104
14356 #define mmABM1_BL1_PWM_AMBIENT_LIGHT_LEVEL                                                             0x0ebb
14357 #define mmABM1_BL1_PWM_AMBIENT_LIGHT_LEVEL_BASE_IDX                                                    3
14358 #define mmABM1_BL1_PWM_USER_LEVEL                                                                      0x0ebc
14359 #define mmABM1_BL1_PWM_USER_LEVEL_BASE_IDX                                                             3
14360 #define mmABM1_BL1_PWM_TARGET_ABM_LEVEL                                                                0x0ebd
14361 #define mmABM1_BL1_PWM_TARGET_ABM_LEVEL_BASE_IDX                                                       3
14362 #define mmABM1_BL1_PWM_CURRENT_ABM_LEVEL                                                               0x0ebe
14363 #define mmABM1_BL1_PWM_CURRENT_ABM_LEVEL_BASE_IDX                                                      3
14364 #define mmABM1_BL1_PWM_FINAL_DUTY_CYCLE                                                                0x0ebf
14365 #define mmABM1_BL1_PWM_FINAL_DUTY_CYCLE_BASE_IDX                                                       3
14366 #define mmABM1_BL1_PWM_MINIMUM_DUTY_CYCLE                                                              0x0ec0
14367 #define mmABM1_BL1_PWM_MINIMUM_DUTY_CYCLE_BASE_IDX                                                     3
14368 #define mmABM1_BL1_PWM_ABM_CNTL                                                                        0x0ec1
14369 #define mmABM1_BL1_PWM_ABM_CNTL_BASE_IDX                                                               3
14370 #define mmABM1_BL1_PWM_BL_UPDATE_SAMPLE_RATE                                                           0x0ec2
14371 #define mmABM1_BL1_PWM_BL_UPDATE_SAMPLE_RATE_BASE_IDX                                                  3
14372 #define mmABM1_BL1_PWM_GRP2_REG_LOCK                                                                   0x0ec3
14373 #define mmABM1_BL1_PWM_GRP2_REG_LOCK_BASE_IDX                                                          3
14374 #define mmABM1_DC_ABM1_CNTL                                                                            0x0ec4
14375 #define mmABM1_DC_ABM1_CNTL_BASE_IDX                                                                   3
14376 #define mmABM1_DC_ABM1_IPCSC_COEFF_SEL                                                                 0x0ec5
14377 #define mmABM1_DC_ABM1_IPCSC_COEFF_SEL_BASE_IDX                                                        3
14378 #define mmABM1_DC_ABM1_ACE_OFFSET_SLOPE_0                                                              0x0ec6
14379 #define mmABM1_DC_ABM1_ACE_OFFSET_SLOPE_0_BASE_IDX                                                     3
14380 #define mmABM1_DC_ABM1_ACE_OFFSET_SLOPE_1                                                              0x0ec7
14381 #define mmABM1_DC_ABM1_ACE_OFFSET_SLOPE_1_BASE_IDX                                                     3
14382 #define mmABM1_DC_ABM1_ACE_OFFSET_SLOPE_2                                                              0x0ec8
14383 #define mmABM1_DC_ABM1_ACE_OFFSET_SLOPE_2_BASE_IDX                                                     3
14384 #define mmABM1_DC_ABM1_ACE_OFFSET_SLOPE_3                                                              0x0ec9
14385 #define mmABM1_DC_ABM1_ACE_OFFSET_SLOPE_3_BASE_IDX                                                     3
14386 #define mmABM1_DC_ABM1_ACE_OFFSET_SLOPE_4                                                              0x0eca
14387 #define mmABM1_DC_ABM1_ACE_OFFSET_SLOPE_4_BASE_IDX                                                     3
14388 #define mmABM1_DC_ABM1_ACE_THRES_12                                                                    0x0ecb
14389 #define mmABM1_DC_ABM1_ACE_THRES_12_BASE_IDX                                                           3
14390 #define mmABM1_DC_ABM1_ACE_THRES_34                                                                    0x0ecc
14391 #define mmABM1_DC_ABM1_ACE_THRES_34_BASE_IDX                                                           3
14392 #define mmABM1_DC_ABM1_ACE_CNTL_MISC                                                                   0x0ecd
14393 #define mmABM1_DC_ABM1_ACE_CNTL_MISC_BASE_IDX                                                          3
14394 #define mmABM1_DC_ABM1_HGLS_REG_READ_PROGRESS                                                          0x0ecf
14395 #define mmABM1_DC_ABM1_HGLS_REG_READ_PROGRESS_BASE_IDX                                                 3
14396 #define mmABM1_DC_ABM1_HG_MISC_CTRL                                                                    0x0ed0
14397 #define mmABM1_DC_ABM1_HG_MISC_CTRL_BASE_IDX                                                           3
14398 #define mmABM1_DC_ABM1_LS_SUM_OF_LUMA                                                                  0x0ed1
14399 #define mmABM1_DC_ABM1_LS_SUM_OF_LUMA_BASE_IDX                                                         3
14400 #define mmABM1_DC_ABM1_LS_MIN_MAX_LUMA                                                                 0x0ed2
14401 #define mmABM1_DC_ABM1_LS_MIN_MAX_LUMA_BASE_IDX                                                        3
14402 #define mmABM1_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA                                                        0x0ed3
14403 #define mmABM1_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA_BASE_IDX                                               3
14404 #define mmABM1_DC_ABM1_LS_PIXEL_COUNT                                                                  0x0ed4
14405 #define mmABM1_DC_ABM1_LS_PIXEL_COUNT_BASE_IDX                                                         3
14406 #define mmABM1_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES                                                    0x0ed5
14407 #define mmABM1_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES_BASE_IDX                                           3
14408 #define mmABM1_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT                                                        0x0ed6
14409 #define mmABM1_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT_BASE_IDX                                               3
14410 #define mmABM1_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT                                                        0x0ed7
14411 #define mmABM1_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT_BASE_IDX                                               3
14412 #define mmABM1_DC_ABM1_HG_SAMPLE_RATE                                                                  0x0ed8
14413 #define mmABM1_DC_ABM1_HG_SAMPLE_RATE_BASE_IDX                                                         3
14414 #define mmABM1_DC_ABM1_LS_SAMPLE_RATE                                                                  0x0ed9
14415 #define mmABM1_DC_ABM1_LS_SAMPLE_RATE_BASE_IDX                                                         3
14416 #define mmABM1_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG                                                          0x0eda
14417 #define mmABM1_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG_BASE_IDX                                                 3
14418 #define mmABM1_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX                                                          0x0edb
14419 #define mmABM1_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX_BASE_IDX                                                 3
14420 #define mmABM1_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX                                                         0x0edc
14421 #define mmABM1_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX_BASE_IDX                                                3
14422 #define mmABM1_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX                                                        0x0edd
14423 #define mmABM1_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX_BASE_IDX                                               3
14424 #define mmABM1_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX                                                        0x0ede
14425 #define mmABM1_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX_BASE_IDX                                               3
14426 #define mmABM1_DC_ABM1_HG_RESULT_1                                                                     0x0edf
14427 #define mmABM1_DC_ABM1_HG_RESULT_1_BASE_IDX                                                            3
14428 #define mmABM1_DC_ABM1_HG_RESULT_2                                                                     0x0ee0
14429 #define mmABM1_DC_ABM1_HG_RESULT_2_BASE_IDX                                                            3
14430 #define mmABM1_DC_ABM1_HG_RESULT_3                                                                     0x0ee1
14431 #define mmABM1_DC_ABM1_HG_RESULT_3_BASE_IDX                                                            3
14432 #define mmABM1_DC_ABM1_HG_RESULT_4                                                                     0x0ee2
14433 #define mmABM1_DC_ABM1_HG_RESULT_4_BASE_IDX                                                            3
14434 #define mmABM1_DC_ABM1_HG_RESULT_5                                                                     0x0ee3
14435 #define mmABM1_DC_ABM1_HG_RESULT_5_BASE_IDX                                                            3
14436 #define mmABM1_DC_ABM1_HG_RESULT_6                                                                     0x0ee4
14437 #define mmABM1_DC_ABM1_HG_RESULT_6_BASE_IDX                                                            3
14438 #define mmABM1_DC_ABM1_HG_RESULT_7                                                                     0x0ee5
14439 #define mmABM1_DC_ABM1_HG_RESULT_7_BASE_IDX                                                            3
14440 #define mmABM1_DC_ABM1_HG_RESULT_8                                                                     0x0ee6
14441 #define mmABM1_DC_ABM1_HG_RESULT_8_BASE_IDX                                                            3
14442 #define mmABM1_DC_ABM1_HG_RESULT_9                                                                     0x0ee7
14443 #define mmABM1_DC_ABM1_HG_RESULT_9_BASE_IDX                                                            3
14444 #define mmABM1_DC_ABM1_HG_RESULT_10                                                                    0x0ee8
14445 #define mmABM1_DC_ABM1_HG_RESULT_10_BASE_IDX                                                           3
14446 #define mmABM1_DC_ABM1_HG_RESULT_11                                                                    0x0ee9
14447 #define mmABM1_DC_ABM1_HG_RESULT_11_BASE_IDX                                                           3
14448 #define mmABM1_DC_ABM1_HG_RESULT_12                                                                    0x0eea
14449 #define mmABM1_DC_ABM1_HG_RESULT_12_BASE_IDX                                                           3
14450 #define mmABM1_DC_ABM1_HG_RESULT_13                                                                    0x0eeb
14451 #define mmABM1_DC_ABM1_HG_RESULT_13_BASE_IDX                                                           3
14452 #define mmABM1_DC_ABM1_HG_RESULT_14                                                                    0x0eec
14453 #define mmABM1_DC_ABM1_HG_RESULT_14_BASE_IDX                                                           3
14454 #define mmABM1_DC_ABM1_HG_RESULT_15                                                                    0x0eed
14455 #define mmABM1_DC_ABM1_HG_RESULT_15_BASE_IDX                                                           3
14456 #define mmABM1_DC_ABM1_HG_RESULT_16                                                                    0x0eee
14457 #define mmABM1_DC_ABM1_HG_RESULT_16_BASE_IDX                                                           3
14458 #define mmABM1_DC_ABM1_HG_RESULT_17                                                                    0x0eef
14459 #define mmABM1_DC_ABM1_HG_RESULT_17_BASE_IDX                                                           3
14460 #define mmABM1_DC_ABM1_HG_RESULT_18                                                                    0x0ef0
14461 #define mmABM1_DC_ABM1_HG_RESULT_18_BASE_IDX                                                           3
14462 #define mmABM1_DC_ABM1_HG_RESULT_19                                                                    0x0ef1
14463 #define mmABM1_DC_ABM1_HG_RESULT_19_BASE_IDX                                                           3
14464 #define mmABM1_DC_ABM1_HG_RESULT_20                                                                    0x0ef2
14465 #define mmABM1_DC_ABM1_HG_RESULT_20_BASE_IDX                                                           3
14466 #define mmABM1_DC_ABM1_HG_RESULT_21                                                                    0x0ef3
14467 #define mmABM1_DC_ABM1_HG_RESULT_21_BASE_IDX                                                           3
14468 #define mmABM1_DC_ABM1_HG_RESULT_22                                                                    0x0ef4
14469 #define mmABM1_DC_ABM1_HG_RESULT_22_BASE_IDX                                                           3
14470 #define mmABM1_DC_ABM1_HG_RESULT_23                                                                    0x0ef5
14471 #define mmABM1_DC_ABM1_HG_RESULT_23_BASE_IDX                                                           3
14472 #define mmABM1_DC_ABM1_HG_RESULT_24                                                                    0x0ef6
14473 #define mmABM1_DC_ABM1_HG_RESULT_24_BASE_IDX                                                           3
14474 #define mmABM1_DC_ABM1_BL_MASTER_LOCK                                                                  0x0ef7
14475 #define mmABM1_DC_ABM1_BL_MASTER_LOCK_BASE_IDX                                                         3
14476 
14477 
14478 // addressBlock: dce_dc_opp_abm2_dispdec
14479 // base address: 0x208
14480 #define mmABM2_BL1_PWM_AMBIENT_LIGHT_LEVEL                                                             0x0efc
14481 #define mmABM2_BL1_PWM_AMBIENT_LIGHT_LEVEL_BASE_IDX                                                    3
14482 #define mmABM2_BL1_PWM_USER_LEVEL                                                                      0x0efd
14483 #define mmABM2_BL1_PWM_USER_LEVEL_BASE_IDX                                                             3
14484 #define mmABM2_BL1_PWM_TARGET_ABM_LEVEL                                                                0x0efe
14485 #define mmABM2_BL1_PWM_TARGET_ABM_LEVEL_BASE_IDX                                                       3
14486 #define mmABM2_BL1_PWM_CURRENT_ABM_LEVEL                                                               0x0eff
14487 #define mmABM2_BL1_PWM_CURRENT_ABM_LEVEL_BASE_IDX                                                      3
14488 #define mmABM2_BL1_PWM_FINAL_DUTY_CYCLE                                                                0x0f00
14489 #define mmABM2_BL1_PWM_FINAL_DUTY_CYCLE_BASE_IDX                                                       3
14490 #define mmABM2_BL1_PWM_MINIMUM_DUTY_CYCLE                                                              0x0f01
14491 #define mmABM2_BL1_PWM_MINIMUM_DUTY_CYCLE_BASE_IDX                                                     3
14492 #define mmABM2_BL1_PWM_ABM_CNTL                                                                        0x0f02
14493 #define mmABM2_BL1_PWM_ABM_CNTL_BASE_IDX                                                               3
14494 #define mmABM2_BL1_PWM_BL_UPDATE_SAMPLE_RATE                                                           0x0f03
14495 #define mmABM2_BL1_PWM_BL_UPDATE_SAMPLE_RATE_BASE_IDX                                                  3
14496 #define mmABM2_BL1_PWM_GRP2_REG_LOCK                                                                   0x0f04
14497 #define mmABM2_BL1_PWM_GRP2_REG_LOCK_BASE_IDX                                                          3
14498 #define mmABM2_DC_ABM1_CNTL                                                                            0x0f05
14499 #define mmABM2_DC_ABM1_CNTL_BASE_IDX                                                                   3
14500 #define mmABM2_DC_ABM1_IPCSC_COEFF_SEL                                                                 0x0f06
14501 #define mmABM2_DC_ABM1_IPCSC_COEFF_SEL_BASE_IDX                                                        3
14502 #define mmABM2_DC_ABM1_ACE_OFFSET_SLOPE_0                                                              0x0f07
14503 #define mmABM2_DC_ABM1_ACE_OFFSET_SLOPE_0_BASE_IDX                                                     3
14504 #define mmABM2_DC_ABM1_ACE_OFFSET_SLOPE_1                                                              0x0f08
14505 #define mmABM2_DC_ABM1_ACE_OFFSET_SLOPE_1_BASE_IDX                                                     3
14506 #define mmABM2_DC_ABM1_ACE_OFFSET_SLOPE_2                                                              0x0f09
14507 #define mmABM2_DC_ABM1_ACE_OFFSET_SLOPE_2_BASE_IDX                                                     3
14508 #define mmABM2_DC_ABM1_ACE_OFFSET_SLOPE_3                                                              0x0f0a
14509 #define mmABM2_DC_ABM1_ACE_OFFSET_SLOPE_3_BASE_IDX                                                     3
14510 #define mmABM2_DC_ABM1_ACE_OFFSET_SLOPE_4                                                              0x0f0b
14511 #define mmABM2_DC_ABM1_ACE_OFFSET_SLOPE_4_BASE_IDX                                                     3
14512 #define mmABM2_DC_ABM1_ACE_THRES_12                                                                    0x0f0c
14513 #define mmABM2_DC_ABM1_ACE_THRES_12_BASE_IDX                                                           3
14514 #define mmABM2_DC_ABM1_ACE_THRES_34                                                                    0x0f0d
14515 #define mmABM2_DC_ABM1_ACE_THRES_34_BASE_IDX                                                           3
14516 #define mmABM2_DC_ABM1_ACE_CNTL_MISC                                                                   0x0f0e
14517 #define mmABM2_DC_ABM1_ACE_CNTL_MISC_BASE_IDX                                                          3
14518 #define mmABM2_DC_ABM1_HGLS_REG_READ_PROGRESS                                                          0x0f10
14519 #define mmABM2_DC_ABM1_HGLS_REG_READ_PROGRESS_BASE_IDX                                                 3
14520 #define mmABM2_DC_ABM1_HG_MISC_CTRL                                                                    0x0f11
14521 #define mmABM2_DC_ABM1_HG_MISC_CTRL_BASE_IDX                                                           3
14522 #define mmABM2_DC_ABM1_LS_SUM_OF_LUMA                                                                  0x0f12
14523 #define mmABM2_DC_ABM1_LS_SUM_OF_LUMA_BASE_IDX                                                         3
14524 #define mmABM2_DC_ABM1_LS_MIN_MAX_LUMA                                                                 0x0f13
14525 #define mmABM2_DC_ABM1_LS_MIN_MAX_LUMA_BASE_IDX                                                        3
14526 #define mmABM2_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA                                                        0x0f14
14527 #define mmABM2_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA_BASE_IDX                                               3
14528 #define mmABM2_DC_ABM1_LS_PIXEL_COUNT                                                                  0x0f15
14529 #define mmABM2_DC_ABM1_LS_PIXEL_COUNT_BASE_IDX                                                         3
14530 #define mmABM2_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES                                                    0x0f16
14531 #define mmABM2_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES_BASE_IDX                                           3
14532 #define mmABM2_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT                                                        0x0f17
14533 #define mmABM2_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT_BASE_IDX                                               3
14534 #define mmABM2_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT                                                        0x0f18
14535 #define mmABM2_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT_BASE_IDX                                               3
14536 #define mmABM2_DC_ABM1_HG_SAMPLE_RATE                                                                  0x0f19
14537 #define mmABM2_DC_ABM1_HG_SAMPLE_RATE_BASE_IDX                                                         3
14538 #define mmABM2_DC_ABM1_LS_SAMPLE_RATE                                                                  0x0f1a
14539 #define mmABM2_DC_ABM1_LS_SAMPLE_RATE_BASE_IDX                                                         3
14540 #define mmABM2_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG                                                          0x0f1b
14541 #define mmABM2_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG_BASE_IDX                                                 3
14542 #define mmABM2_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX                                                          0x0f1c
14543 #define mmABM2_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX_BASE_IDX                                                 3
14544 #define mmABM2_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX                                                         0x0f1d
14545 #define mmABM2_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX_BASE_IDX                                                3
14546 #define mmABM2_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX                                                        0x0f1e
14547 #define mmABM2_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX_BASE_IDX                                               3
14548 #define mmABM2_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX                                                        0x0f1f
14549 #define mmABM2_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX_BASE_IDX                                               3
14550 #define mmABM2_DC_ABM1_HG_RESULT_1                                                                     0x0f20
14551 #define mmABM2_DC_ABM1_HG_RESULT_1_BASE_IDX                                                            3
14552 #define mmABM2_DC_ABM1_HG_RESULT_2                                                                     0x0f21
14553 #define mmABM2_DC_ABM1_HG_RESULT_2_BASE_IDX                                                            3
14554 #define mmABM2_DC_ABM1_HG_RESULT_3                                                                     0x0f22
14555 #define mmABM2_DC_ABM1_HG_RESULT_3_BASE_IDX                                                            3
14556 #define mmABM2_DC_ABM1_HG_RESULT_4                                                                     0x0f23
14557 #define mmABM2_DC_ABM1_HG_RESULT_4_BASE_IDX                                                            3
14558 #define mmABM2_DC_ABM1_HG_RESULT_5                                                                     0x0f24
14559 #define mmABM2_DC_ABM1_HG_RESULT_5_BASE_IDX                                                            3
14560 #define mmABM2_DC_ABM1_HG_RESULT_6                                                                     0x0f25
14561 #define mmABM2_DC_ABM1_HG_RESULT_6_BASE_IDX                                                            3
14562 #define mmABM2_DC_ABM1_HG_RESULT_7                                                                     0x0f26
14563 #define mmABM2_DC_ABM1_HG_RESULT_7_BASE_IDX                                                            3
14564 #define mmABM2_DC_ABM1_HG_RESULT_8                                                                     0x0f27
14565 #define mmABM2_DC_ABM1_HG_RESULT_8_BASE_IDX                                                            3
14566 #define mmABM2_DC_ABM1_HG_RESULT_9                                                                     0x0f28
14567 #define mmABM2_DC_ABM1_HG_RESULT_9_BASE_IDX                                                            3
14568 #define mmABM2_DC_ABM1_HG_RESULT_10                                                                    0x0f29
14569 #define mmABM2_DC_ABM1_HG_RESULT_10_BASE_IDX                                                           3
14570 #define mmABM2_DC_ABM1_HG_RESULT_11                                                                    0x0f2a
14571 #define mmABM2_DC_ABM1_HG_RESULT_11_BASE_IDX                                                           3
14572 #define mmABM2_DC_ABM1_HG_RESULT_12                                                                    0x0f2b
14573 #define mmABM2_DC_ABM1_HG_RESULT_12_BASE_IDX                                                           3
14574 #define mmABM2_DC_ABM1_HG_RESULT_13                                                                    0x0f2c
14575 #define mmABM2_DC_ABM1_HG_RESULT_13_BASE_IDX                                                           3
14576 #define mmABM2_DC_ABM1_HG_RESULT_14                                                                    0x0f2d
14577 #define mmABM2_DC_ABM1_HG_RESULT_14_BASE_IDX                                                           3
14578 #define mmABM2_DC_ABM1_HG_RESULT_15                                                                    0x0f2e
14579 #define mmABM2_DC_ABM1_HG_RESULT_15_BASE_IDX                                                           3
14580 #define mmABM2_DC_ABM1_HG_RESULT_16                                                                    0x0f2f
14581 #define mmABM2_DC_ABM1_HG_RESULT_16_BASE_IDX                                                           3
14582 #define mmABM2_DC_ABM1_HG_RESULT_17                                                                    0x0f30
14583 #define mmABM2_DC_ABM1_HG_RESULT_17_BASE_IDX                                                           3
14584 #define mmABM2_DC_ABM1_HG_RESULT_18                                                                    0x0f31
14585 #define mmABM2_DC_ABM1_HG_RESULT_18_BASE_IDX                                                           3
14586 #define mmABM2_DC_ABM1_HG_RESULT_19                                                                    0x0f32
14587 #define mmABM2_DC_ABM1_HG_RESULT_19_BASE_IDX                                                           3
14588 #define mmABM2_DC_ABM1_HG_RESULT_20                                                                    0x0f33
14589 #define mmABM2_DC_ABM1_HG_RESULT_20_BASE_IDX                                                           3
14590 #define mmABM2_DC_ABM1_HG_RESULT_21                                                                    0x0f34
14591 #define mmABM2_DC_ABM1_HG_RESULT_21_BASE_IDX                                                           3
14592 #define mmABM2_DC_ABM1_HG_RESULT_22                                                                    0x0f35
14593 #define mmABM2_DC_ABM1_HG_RESULT_22_BASE_IDX                                                           3
14594 #define mmABM2_DC_ABM1_HG_RESULT_23                                                                    0x0f36
14595 #define mmABM2_DC_ABM1_HG_RESULT_23_BASE_IDX                                                           3
14596 #define mmABM2_DC_ABM1_HG_RESULT_24                                                                    0x0f37
14597 #define mmABM2_DC_ABM1_HG_RESULT_24_BASE_IDX                                                           3
14598 #define mmABM2_DC_ABM1_BL_MASTER_LOCK                                                                  0x0f38
14599 #define mmABM2_DC_ABM1_BL_MASTER_LOCK_BASE_IDX                                                         3
14600 
14601 
14602 // addressBlock: dce_dc_opp_abm3_dispdec
14603 // base address: 0x30c
14604 #define mmABM3_BL1_PWM_AMBIENT_LIGHT_LEVEL                                                             0x0f3d
14605 #define mmABM3_BL1_PWM_AMBIENT_LIGHT_LEVEL_BASE_IDX                                                    3
14606 #define mmABM3_BL1_PWM_USER_LEVEL                                                                      0x0f3e
14607 #define mmABM3_BL1_PWM_USER_LEVEL_BASE_IDX                                                             3
14608 #define mmABM3_BL1_PWM_TARGET_ABM_LEVEL                                                                0x0f3f
14609 #define mmABM3_BL1_PWM_TARGET_ABM_LEVEL_BASE_IDX                                                       3
14610 #define mmABM3_BL1_PWM_CURRENT_ABM_LEVEL                                                               0x0f40
14611 #define mmABM3_BL1_PWM_CURRENT_ABM_LEVEL_BASE_IDX                                                      3
14612 #define mmABM3_BL1_PWM_FINAL_DUTY_CYCLE                                                                0x0f41
14613 #define mmABM3_BL1_PWM_FINAL_DUTY_CYCLE_BASE_IDX                                                       3
14614 #define mmABM3_BL1_PWM_MINIMUM_DUTY_CYCLE                                                              0x0f42
14615 #define mmABM3_BL1_PWM_MINIMUM_DUTY_CYCLE_BASE_IDX                                                     3
14616 #define mmABM3_BL1_PWM_ABM_CNTL                                                                        0x0f43
14617 #define mmABM3_BL1_PWM_ABM_CNTL_BASE_IDX                                                               3
14618 #define mmABM3_BL1_PWM_BL_UPDATE_SAMPLE_RATE                                                           0x0f44
14619 #define mmABM3_BL1_PWM_BL_UPDATE_SAMPLE_RATE_BASE_IDX                                                  3
14620 #define mmABM3_BL1_PWM_GRP2_REG_LOCK                                                                   0x0f45
14621 #define mmABM3_BL1_PWM_GRP2_REG_LOCK_BASE_IDX                                                          3
14622 #define mmABM3_DC_ABM1_CNTL                                                                            0x0f46
14623 #define mmABM3_DC_ABM1_CNTL_BASE_IDX                                                                   3
14624 #define mmABM3_DC_ABM1_IPCSC_COEFF_SEL                                                                 0x0f47
14625 #define mmABM3_DC_ABM1_IPCSC_COEFF_SEL_BASE_IDX                                                        3
14626 #define mmABM3_DC_ABM1_ACE_OFFSET_SLOPE_0                                                              0x0f48
14627 #define mmABM3_DC_ABM1_ACE_OFFSET_SLOPE_0_BASE_IDX                                                     3
14628 #define mmABM3_DC_ABM1_ACE_OFFSET_SLOPE_1                                                              0x0f49
14629 #define mmABM3_DC_ABM1_ACE_OFFSET_SLOPE_1_BASE_IDX                                                     3
14630 #define mmABM3_DC_ABM1_ACE_OFFSET_SLOPE_2                                                              0x0f4a
14631 #define mmABM3_DC_ABM1_ACE_OFFSET_SLOPE_2_BASE_IDX                                                     3
14632 #define mmABM3_DC_ABM1_ACE_OFFSET_SLOPE_3                                                              0x0f4b
14633 #define mmABM3_DC_ABM1_ACE_OFFSET_SLOPE_3_BASE_IDX                                                     3
14634 #define mmABM3_DC_ABM1_ACE_OFFSET_SLOPE_4                                                              0x0f4c
14635 #define mmABM3_DC_ABM1_ACE_OFFSET_SLOPE_4_BASE_IDX                                                     3
14636 #define mmABM3_DC_ABM1_ACE_THRES_12                                                                    0x0f4d
14637 #define mmABM3_DC_ABM1_ACE_THRES_12_BASE_IDX                                                           3
14638 #define mmABM3_DC_ABM1_ACE_THRES_34                                                                    0x0f4e
14639 #define mmABM3_DC_ABM1_ACE_THRES_34_BASE_IDX                                                           3
14640 #define mmABM3_DC_ABM1_ACE_CNTL_MISC                                                                   0x0f4f
14641 #define mmABM3_DC_ABM1_ACE_CNTL_MISC_BASE_IDX                                                          3
14642 #define mmABM3_DC_ABM1_HGLS_REG_READ_PROGRESS                                                          0x0f51
14643 #define mmABM3_DC_ABM1_HGLS_REG_READ_PROGRESS_BASE_IDX                                                 3
14644 #define mmABM3_DC_ABM1_HG_MISC_CTRL                                                                    0x0f52
14645 #define mmABM3_DC_ABM1_HG_MISC_CTRL_BASE_IDX                                                           3
14646 #define mmABM3_DC_ABM1_LS_SUM_OF_LUMA                                                                  0x0f53
14647 #define mmABM3_DC_ABM1_LS_SUM_OF_LUMA_BASE_IDX                                                         3
14648 #define mmABM3_DC_ABM1_LS_MIN_MAX_LUMA                                                                 0x0f54
14649 #define mmABM3_DC_ABM1_LS_MIN_MAX_LUMA_BASE_IDX                                                        3
14650 #define mmABM3_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA                                                        0x0f55
14651 #define mmABM3_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA_BASE_IDX                                               3
14652 #define mmABM3_DC_ABM1_LS_PIXEL_COUNT                                                                  0x0f56
14653 #define mmABM3_DC_ABM1_LS_PIXEL_COUNT_BASE_IDX                                                         3
14654 #define mmABM3_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES                                                    0x0f57
14655 #define mmABM3_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES_BASE_IDX                                           3
14656 #define mmABM3_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT                                                        0x0f58
14657 #define mmABM3_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT_BASE_IDX                                               3
14658 #define mmABM3_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT                                                        0x0f59
14659 #define mmABM3_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT_BASE_IDX                                               3
14660 #define mmABM3_DC_ABM1_HG_SAMPLE_RATE                                                                  0x0f5a
14661 #define mmABM3_DC_ABM1_HG_SAMPLE_RATE_BASE_IDX                                                         3
14662 #define mmABM3_DC_ABM1_LS_SAMPLE_RATE                                                                  0x0f5b
14663 #define mmABM3_DC_ABM1_LS_SAMPLE_RATE_BASE_IDX                                                         3
14664 #define mmABM3_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG                                                          0x0f5c
14665 #define mmABM3_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG_BASE_IDX                                                 3
14666 #define mmABM3_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX                                                          0x0f5d
14667 #define mmABM3_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX_BASE_IDX                                                 3
14668 #define mmABM3_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX                                                         0x0f5e
14669 #define mmABM3_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX_BASE_IDX                                                3
14670 #define mmABM3_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX                                                        0x0f5f
14671 #define mmABM3_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX_BASE_IDX                                               3
14672 #define mmABM3_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX                                                        0x0f60
14673 #define mmABM3_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX_BASE_IDX                                               3
14674 #define mmABM3_DC_ABM1_HG_RESULT_1                                                                     0x0f61
14675 #define mmABM3_DC_ABM1_HG_RESULT_1_BASE_IDX                                                            3
14676 #define mmABM3_DC_ABM1_HG_RESULT_2                                                                     0x0f62
14677 #define mmABM3_DC_ABM1_HG_RESULT_2_BASE_IDX                                                            3
14678 #define mmABM3_DC_ABM1_HG_RESULT_3                                                                     0x0f63
14679 #define mmABM3_DC_ABM1_HG_RESULT_3_BASE_IDX                                                            3
14680 #define mmABM3_DC_ABM1_HG_RESULT_4                                                                     0x0f64
14681 #define mmABM3_DC_ABM1_HG_RESULT_4_BASE_IDX                                                            3
14682 #define mmABM3_DC_ABM1_HG_RESULT_5                                                                     0x0f65
14683 #define mmABM3_DC_ABM1_HG_RESULT_5_BASE_IDX                                                            3
14684 #define mmABM3_DC_ABM1_HG_RESULT_6                                                                     0x0f66
14685 #define mmABM3_DC_ABM1_HG_RESULT_6_BASE_IDX                                                            3
14686 #define mmABM3_DC_ABM1_HG_RESULT_7                                                                     0x0f67
14687 #define mmABM3_DC_ABM1_HG_RESULT_7_BASE_IDX                                                            3
14688 #define mmABM3_DC_ABM1_HG_RESULT_8                                                                     0x0f68
14689 #define mmABM3_DC_ABM1_HG_RESULT_8_BASE_IDX                                                            3
14690 #define mmABM3_DC_ABM1_HG_RESULT_9                                                                     0x0f69
14691 #define mmABM3_DC_ABM1_HG_RESULT_9_BASE_IDX                                                            3
14692 #define mmABM3_DC_ABM1_HG_RESULT_10                                                                    0x0f6a
14693 #define mmABM3_DC_ABM1_HG_RESULT_10_BASE_IDX                                                           3
14694 #define mmABM3_DC_ABM1_HG_RESULT_11                                                                    0x0f6b
14695 #define mmABM3_DC_ABM1_HG_RESULT_11_BASE_IDX                                                           3
14696 #define mmABM3_DC_ABM1_HG_RESULT_12                                                                    0x0f6c
14697 #define mmABM3_DC_ABM1_HG_RESULT_12_BASE_IDX                                                           3
14698 #define mmABM3_DC_ABM1_HG_RESULT_13                                                                    0x0f6d
14699 #define mmABM3_DC_ABM1_HG_RESULT_13_BASE_IDX                                                           3
14700 #define mmABM3_DC_ABM1_HG_RESULT_14                                                                    0x0f6e
14701 #define mmABM3_DC_ABM1_HG_RESULT_14_BASE_IDX                                                           3
14702 #define mmABM3_DC_ABM1_HG_RESULT_15                                                                    0x0f6f
14703 #define mmABM3_DC_ABM1_HG_RESULT_15_BASE_IDX                                                           3
14704 #define mmABM3_DC_ABM1_HG_RESULT_16                                                                    0x0f70
14705 #define mmABM3_DC_ABM1_HG_RESULT_16_BASE_IDX                                                           3
14706 #define mmABM3_DC_ABM1_HG_RESULT_17                                                                    0x0f71
14707 #define mmABM3_DC_ABM1_HG_RESULT_17_BASE_IDX                                                           3
14708 #define mmABM3_DC_ABM1_HG_RESULT_18                                                                    0x0f72
14709 #define mmABM3_DC_ABM1_HG_RESULT_18_BASE_IDX                                                           3
14710 #define mmABM3_DC_ABM1_HG_RESULT_19                                                                    0x0f73
14711 #define mmABM3_DC_ABM1_HG_RESULT_19_BASE_IDX                                                           3
14712 #define mmABM3_DC_ABM1_HG_RESULT_20                                                                    0x0f74
14713 #define mmABM3_DC_ABM1_HG_RESULT_20_BASE_IDX                                                           3
14714 #define mmABM3_DC_ABM1_HG_RESULT_21                                                                    0x0f75
14715 #define mmABM3_DC_ABM1_HG_RESULT_21_BASE_IDX                                                           3
14716 #define mmABM3_DC_ABM1_HG_RESULT_22                                                                    0x0f76
14717 #define mmABM3_DC_ABM1_HG_RESULT_22_BASE_IDX                                                           3
14718 #define mmABM3_DC_ABM1_HG_RESULT_23                                                                    0x0f77
14719 #define mmABM3_DC_ABM1_HG_RESULT_23_BASE_IDX                                                           3
14720 #define mmABM3_DC_ABM1_HG_RESULT_24                                                                    0x0f78
14721 #define mmABM3_DC_ABM1_HG_RESULT_24_BASE_IDX                                                           3
14722 #define mmABM3_DC_ABM1_BL_MASTER_LOCK                                                                  0x0f79
14723 #define mmABM3_DC_ABM1_BL_MASTER_LOCK_BASE_IDX                                                         3
14724 
14725 
14726 // addressBlock: dce_dc_opp_abm4_dispdec
14727 // base address: 0x410
14728 #define mmABM4_BL1_PWM_AMBIENT_LIGHT_LEVEL                                                             0x0f7e
14729 #define mmABM4_BL1_PWM_AMBIENT_LIGHT_LEVEL_BASE_IDX                                                    3
14730 #define mmABM4_BL1_PWM_USER_LEVEL                                                                      0x0f7f
14731 #define mmABM4_BL1_PWM_USER_LEVEL_BASE_IDX                                                             3
14732 #define mmABM4_BL1_PWM_TARGET_ABM_LEVEL                                                                0x0f80
14733 #define mmABM4_BL1_PWM_TARGET_ABM_LEVEL_BASE_IDX                                                       3
14734 #define mmABM4_BL1_PWM_CURRENT_ABM_LEVEL                                                               0x0f81
14735 #define mmABM4_BL1_PWM_CURRENT_ABM_LEVEL_BASE_IDX                                                      3
14736 #define mmABM4_BL1_PWM_FINAL_DUTY_CYCLE                                                                0x0f82
14737 #define mmABM4_BL1_PWM_FINAL_DUTY_CYCLE_BASE_IDX                                                       3
14738 #define mmABM4_BL1_PWM_MINIMUM_DUTY_CYCLE                                                              0x0f83
14739 #define mmABM4_BL1_PWM_MINIMUM_DUTY_CYCLE_BASE_IDX                                                     3
14740 #define mmABM4_BL1_PWM_ABM_CNTL                                                                        0x0f84
14741 #define mmABM4_BL1_PWM_ABM_CNTL_BASE_IDX                                                               3
14742 #define mmABM4_BL1_PWM_BL_UPDATE_SAMPLE_RATE                                                           0x0f85
14743 #define mmABM4_BL1_PWM_BL_UPDATE_SAMPLE_RATE_BASE_IDX                                                  3
14744 #define mmABM4_BL1_PWM_GRP2_REG_LOCK                                                                   0x0f86
14745 #define mmABM4_BL1_PWM_GRP2_REG_LOCK_BASE_IDX                                                          3
14746 #define mmABM4_DC_ABM1_CNTL                                                                            0x0f87
14747 #define mmABM4_DC_ABM1_CNTL_BASE_IDX                                                                   3
14748 #define mmABM4_DC_ABM1_IPCSC_COEFF_SEL                                                                 0x0f88
14749 #define mmABM4_DC_ABM1_IPCSC_COEFF_SEL_BASE_IDX                                                        3
14750 #define mmABM4_DC_ABM1_ACE_OFFSET_SLOPE_0                                                              0x0f89
14751 #define mmABM4_DC_ABM1_ACE_OFFSET_SLOPE_0_BASE_IDX                                                     3
14752 #define mmABM4_DC_ABM1_ACE_OFFSET_SLOPE_1                                                              0x0f8a
14753 #define mmABM4_DC_ABM1_ACE_OFFSET_SLOPE_1_BASE_IDX                                                     3
14754 #define mmABM4_DC_ABM1_ACE_OFFSET_SLOPE_2                                                              0x0f8b
14755 #define mmABM4_DC_ABM1_ACE_OFFSET_SLOPE_2_BASE_IDX                                                     3
14756 #define mmABM4_DC_ABM1_ACE_OFFSET_SLOPE_3                                                              0x0f8c
14757 #define mmABM4_DC_ABM1_ACE_OFFSET_SLOPE_3_BASE_IDX                                                     3
14758 #define mmABM4_DC_ABM1_ACE_OFFSET_SLOPE_4                                                              0x0f8d
14759 #define mmABM4_DC_ABM1_ACE_OFFSET_SLOPE_4_BASE_IDX                                                     3
14760 #define mmABM4_DC_ABM1_ACE_THRES_12                                                                    0x0f8e
14761 #define mmABM4_DC_ABM1_ACE_THRES_12_BASE_IDX                                                           3
14762 #define mmABM4_DC_ABM1_ACE_THRES_34                                                                    0x0f8f
14763 #define mmABM4_DC_ABM1_ACE_THRES_34_BASE_IDX                                                           3
14764 #define mmABM4_DC_ABM1_ACE_CNTL_MISC                                                                   0x0f90
14765 #define mmABM4_DC_ABM1_ACE_CNTL_MISC_BASE_IDX                                                          3
14766 #define mmABM4_DC_ABM1_HGLS_REG_READ_PROGRESS                                                          0x0f92
14767 #define mmABM4_DC_ABM1_HGLS_REG_READ_PROGRESS_BASE_IDX                                                 3
14768 #define mmABM4_DC_ABM1_HG_MISC_CTRL                                                                    0x0f93
14769 #define mmABM4_DC_ABM1_HG_MISC_CTRL_BASE_IDX                                                           3
14770 #define mmABM4_DC_ABM1_LS_SUM_OF_LUMA                                                                  0x0f94
14771 #define mmABM4_DC_ABM1_LS_SUM_OF_LUMA_BASE_IDX                                                         3
14772 #define mmABM4_DC_ABM1_LS_MIN_MAX_LUMA                                                                 0x0f95
14773 #define mmABM4_DC_ABM1_LS_MIN_MAX_LUMA_BASE_IDX                                                        3
14774 #define mmABM4_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA                                                        0x0f96
14775 #define mmABM4_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA_BASE_IDX                                               3
14776 #define mmABM4_DC_ABM1_LS_PIXEL_COUNT                                                                  0x0f97
14777 #define mmABM4_DC_ABM1_LS_PIXEL_COUNT_BASE_IDX                                                         3
14778 #define mmABM4_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES                                                    0x0f98
14779 #define mmABM4_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES_BASE_IDX                                           3
14780 #define mmABM4_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT                                                        0x0f99
14781 #define mmABM4_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT_BASE_IDX                                               3
14782 #define mmABM4_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT                                                        0x0f9a
14783 #define mmABM4_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT_BASE_IDX                                               3
14784 #define mmABM4_DC_ABM1_HG_SAMPLE_RATE                                                                  0x0f9b
14785 #define mmABM4_DC_ABM1_HG_SAMPLE_RATE_BASE_IDX                                                         3
14786 #define mmABM4_DC_ABM1_LS_SAMPLE_RATE                                                                  0x0f9c
14787 #define mmABM4_DC_ABM1_LS_SAMPLE_RATE_BASE_IDX                                                         3
14788 #define mmABM4_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG                                                          0x0f9d
14789 #define mmABM4_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG_BASE_IDX                                                 3
14790 #define mmABM4_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX                                                          0x0f9e
14791 #define mmABM4_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX_BASE_IDX                                                 3
14792 #define mmABM4_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX                                                         0x0f9f
14793 #define mmABM4_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX_BASE_IDX                                                3
14794 #define mmABM4_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX                                                        0x0fa0
14795 #define mmABM4_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX_BASE_IDX                                               3
14796 #define mmABM4_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX                                                        0x0fa1
14797 #define mmABM4_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX_BASE_IDX                                               3
14798 #define mmABM4_DC_ABM1_HG_RESULT_1                                                                     0x0fa2
14799 #define mmABM4_DC_ABM1_HG_RESULT_1_BASE_IDX                                                            3
14800 #define mmABM4_DC_ABM1_HG_RESULT_2                                                                     0x0fa3
14801 #define mmABM4_DC_ABM1_HG_RESULT_2_BASE_IDX                                                            3
14802 #define mmABM4_DC_ABM1_HG_RESULT_3                                                                     0x0fa4
14803 #define mmABM4_DC_ABM1_HG_RESULT_3_BASE_IDX                                                            3
14804 #define mmABM4_DC_ABM1_HG_RESULT_4                                                                     0x0fa5
14805 #define mmABM4_DC_ABM1_HG_RESULT_4_BASE_IDX                                                            3
14806 #define mmABM4_DC_ABM1_HG_RESULT_5                                                                     0x0fa6
14807 #define mmABM4_DC_ABM1_HG_RESULT_5_BASE_IDX                                                            3
14808 #define mmABM4_DC_ABM1_HG_RESULT_6                                                                     0x0fa7
14809 #define mmABM4_DC_ABM1_HG_RESULT_6_BASE_IDX                                                            3
14810 #define mmABM4_DC_ABM1_HG_RESULT_7                                                                     0x0fa8
14811 #define mmABM4_DC_ABM1_HG_RESULT_7_BASE_IDX                                                            3
14812 #define mmABM4_DC_ABM1_HG_RESULT_8                                                                     0x0fa9
14813 #define mmABM4_DC_ABM1_HG_RESULT_8_BASE_IDX                                                            3
14814 #define mmABM4_DC_ABM1_HG_RESULT_9                                                                     0x0faa
14815 #define mmABM4_DC_ABM1_HG_RESULT_9_BASE_IDX                                                            3
14816 #define mmABM4_DC_ABM1_HG_RESULT_10                                                                    0x0fab
14817 #define mmABM4_DC_ABM1_HG_RESULT_10_BASE_IDX                                                           3
14818 #define mmABM4_DC_ABM1_HG_RESULT_11                                                                    0x0fac
14819 #define mmABM4_DC_ABM1_HG_RESULT_11_BASE_IDX                                                           3
14820 #define mmABM4_DC_ABM1_HG_RESULT_12                                                                    0x0fad
14821 #define mmABM4_DC_ABM1_HG_RESULT_12_BASE_IDX                                                           3
14822 #define mmABM4_DC_ABM1_HG_RESULT_13                                                                    0x0fae
14823 #define mmABM4_DC_ABM1_HG_RESULT_13_BASE_IDX                                                           3
14824 #define mmABM4_DC_ABM1_HG_RESULT_14                                                                    0x0faf
14825 #define mmABM4_DC_ABM1_HG_RESULT_14_BASE_IDX                                                           3
14826 #define mmABM4_DC_ABM1_HG_RESULT_15                                                                    0x0fb0
14827 #define mmABM4_DC_ABM1_HG_RESULT_15_BASE_IDX                                                           3
14828 #define mmABM4_DC_ABM1_HG_RESULT_16                                                                    0x0fb1
14829 #define mmABM4_DC_ABM1_HG_RESULT_16_BASE_IDX                                                           3
14830 #define mmABM4_DC_ABM1_HG_RESULT_17                                                                    0x0fb2
14831 #define mmABM4_DC_ABM1_HG_RESULT_17_BASE_IDX                                                           3
14832 #define mmABM4_DC_ABM1_HG_RESULT_18                                                                    0x0fb3
14833 #define mmABM4_DC_ABM1_HG_RESULT_18_BASE_IDX                                                           3
14834 #define mmABM4_DC_ABM1_HG_RESULT_19                                                                    0x0fb4
14835 #define mmABM4_DC_ABM1_HG_RESULT_19_BASE_IDX                                                           3
14836 #define mmABM4_DC_ABM1_HG_RESULT_20                                                                    0x0fb5
14837 #define mmABM4_DC_ABM1_HG_RESULT_20_BASE_IDX                                                           3
14838 #define mmABM4_DC_ABM1_HG_RESULT_21                                                                    0x0fb6
14839 #define mmABM4_DC_ABM1_HG_RESULT_21_BASE_IDX                                                           3
14840 #define mmABM4_DC_ABM1_HG_RESULT_22                                                                    0x0fb7
14841 #define mmABM4_DC_ABM1_HG_RESULT_22_BASE_IDX                                                           3
14842 #define mmABM4_DC_ABM1_HG_RESULT_23                                                                    0x0fb8
14843 #define mmABM4_DC_ABM1_HG_RESULT_23_BASE_IDX                                                           3
14844 #define mmABM4_DC_ABM1_HG_RESULT_24                                                                    0x0fb9
14845 #define mmABM4_DC_ABM1_HG_RESULT_24_BASE_IDX                                                           3
14846 #define mmABM4_DC_ABM1_BL_MASTER_LOCK                                                                  0x0fba
14847 #define mmABM4_DC_ABM1_BL_MASTER_LOCK_BASE_IDX                                                         3
14848 
14849 
14850 // addressBlock: dce_dc_hda_azcontroller_azdec
14851 // base address: 0x0
14852 #define mmCORB_WRITE_POINTER                                                                           0x0000
14853 #define mmCORB_WRITE_POINTER_BASE_IDX                                                                  0
14854 #define mmCORB_READ_POINTER                                                                            0x0000
14855 #define mmCORB_READ_POINTER_BASE_IDX                                                                   0
14856 #define mmCORB_CONTROL                                                                                 0x0001
14857 #define mmCORB_CONTROL_BASE_IDX                                                                        0
14858 #define mmCORB_STATUS                                                                                  0x0001
14859 #define mmCORB_STATUS_BASE_IDX                                                                         0
14860 #define mmCORB_SIZE                                                                                    0x0001
14861 #define mmCORB_SIZE_BASE_IDX                                                                           0
14862 #define mmRIRB_LOWER_BASE_ADDRESS                                                                      0x0002
14863 #define mmRIRB_LOWER_BASE_ADDRESS_BASE_IDX                                                             0
14864 #define mmRIRB_UPPER_BASE_ADDRESS                                                                      0x0003
14865 #define mmRIRB_UPPER_BASE_ADDRESS_BASE_IDX                                                             0
14866 #define mmRIRB_WRITE_POINTER                                                                           0x0004
14867 #define mmRIRB_WRITE_POINTER_BASE_IDX                                                                  0
14868 #define mmRESPONSE_INTERRUPT_COUNT                                                                     0x0004
14869 #define mmRESPONSE_INTERRUPT_COUNT_BASE_IDX                                                            0
14870 #define mmRIRB_CONTROL                                                                                 0x0005
14871 #define mmRIRB_CONTROL_BASE_IDX                                                                        0
14872 #define mmRIRB_STATUS                                                                                  0x0005
14873 #define mmRIRB_STATUS_BASE_IDX                                                                         0
14874 #define mmRIRB_SIZE                                                                                    0x0005
14875 #define mmRIRB_SIZE_BASE_IDX                                                                           0
14876 #define mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE                                                           0x0006
14877 #define mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE_BASE_IDX                                                  0
14878 #define mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA                                                      0x0006
14879 #define mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA_BASE_IDX                                             0
14880 #define mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX                                                     0x0006
14881 #define mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX_BASE_IDX                                            0
14882 #define mmIMMEDIATE_RESPONSE_INPUT_INTERFACE                                                           0x0007
14883 #define mmIMMEDIATE_RESPONSE_INPUT_INTERFACE_BASE_IDX                                                  0
14884 #define mmIMMEDIATE_COMMAND_STATUS                                                                     0x0008
14885 #define mmIMMEDIATE_COMMAND_STATUS_BASE_IDX                                                            0
14886 #define mmDMA_POSITION_LOWER_BASE_ADDRESS                                                              0x000a
14887 #define mmDMA_POSITION_LOWER_BASE_ADDRESS_BASE_IDX                                                     0
14888 #define mmDMA_POSITION_UPPER_BASE_ADDRESS                                                              0x000b
14889 #define mmDMA_POSITION_UPPER_BASE_ADDRESS_BASE_IDX                                                     0
14890 #define mmWALL_CLOCK_COUNTER_ALIAS                                                                     0x074c
14891 #define mmWALL_CLOCK_COUNTER_ALIAS_BASE_IDX                                                            1
14892 
14893 
14894 // addressBlock: dce_dc_hda_azendpoint_azdec
14895 // base address: 0x0
14896 #define mmAZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA                                           0x0006
14897 #define mmAZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA_BASE_IDX                                  0
14898 #define mmAZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX                                          0x0006
14899 #define mmAZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX_BASE_IDX                                 0
14900 
14901 
14902 // addressBlock: dce_dc_hda_azinputendpoint_azdec
14903 // base address: 0x0
14904 #define mmAZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA                                            0x0006
14905 #define mmAZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA_BASE_IDX                                   0
14906 #define mmAZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX                                           0x0006
14907 #define mmAZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX_BASE_IDX                                  0
14908 
14909 
14910 
14911 // addressBlock: vga_vgaseqind
14912 // base address: 0x0
14913 #define ixSEQ00                                                                                        0x0000
14914 #define ixSEQ01                                                                                        0x0001
14915 #define ixSEQ02                                                                                        0x0002
14916 #define ixSEQ03                                                                                        0x0003
14917 #define ixSEQ04                                                                                        0x0004
14918 
14919 
14920 // addressBlock: vga_vgacrtind
14921 // base address: 0x0
14922 #define ixCRT00                                                                                        0x0000
14923 #define ixCRT01                                                                                        0x0001
14924 #define ixCRT02                                                                                        0x0002
14925 #define ixCRT03                                                                                        0x0003
14926 #define ixCRT04                                                                                        0x0004
14927 #define ixCRT05                                                                                        0x0005
14928 #define ixCRT06                                                                                        0x0006
14929 #define ixCRT07                                                                                        0x0007
14930 #define ixCRT08                                                                                        0x0008
14931 #define ixCRT09                                                                                        0x0009
14932 #define ixCRT0A                                                                                        0x000a
14933 #define ixCRT0B                                                                                        0x000b
14934 #define ixCRT0C                                                                                        0x000c
14935 #define ixCRT0D                                                                                        0x000d
14936 #define ixCRT0E                                                                                        0x000e
14937 #define ixCRT0F                                                                                        0x000f
14938 #define ixCRT10                                                                                        0x0010
14939 #define ixCRT11                                                                                        0x0011
14940 #define ixCRT12                                                                                        0x0012
14941 #define ixCRT13                                                                                        0x0013
14942 #define ixCRT14                                                                                        0x0014
14943 #define ixCRT15                                                                                        0x0015
14944 #define ixCRT16                                                                                        0x0016
14945 #define ixCRT17                                                                                        0x0017
14946 #define ixCRT18                                                                                        0x0018
14947 #define ixCRT1E                                                                                        0x001e
14948 #define ixCRT1F                                                                                        0x001f
14949 #define ixCRT22                                                                                        0x0022
14950 
14951 
14952 // addressBlock: vga_vgagrphind
14953 // base address: 0x0
14954 #define ixGRA00                                                                                        0x0000
14955 #define ixGRA01                                                                                        0x0001
14956 #define ixGRA02                                                                                        0x0002
14957 #define ixGRA03                                                                                        0x0003
14958 #define ixGRA04                                                                                        0x0004
14959 #define ixGRA05                                                                                        0x0005
14960 #define ixGRA06                                                                                        0x0006
14961 #define ixGRA07                                                                                        0x0007
14962 #define ixGRA08                                                                                        0x0008
14963 
14964 
14965 // addressBlock: vga_vgaattrind
14966 // base address: 0x0
14967 #define ixATTR00                                                                                       0x0000
14968 #define ixATTR01                                                                                       0x0001
14969 #define ixATTR02                                                                                       0x0002
14970 #define ixATTR03                                                                                       0x0003
14971 #define ixATTR04                                                                                       0x0004
14972 #define ixATTR05                                                                                       0x0005
14973 #define ixATTR06                                                                                       0x0006
14974 #define ixATTR07                                                                                       0x0007
14975 #define ixATTR08                                                                                       0x0008
14976 #define ixATTR09                                                                                       0x0009
14977 #define ixATTR0A                                                                                       0x000a
14978 #define ixATTR0B                                                                                       0x000b
14979 #define ixATTR0C                                                                                       0x000c
14980 #define ixATTR0D                                                                                       0x000d
14981 #define ixATTR0E                                                                                       0x000e
14982 #define ixATTR0F                                                                                       0x000f
14983 #define ixATTR10                                                                                       0x0010
14984 #define ixATTR11                                                                                       0x0011
14985 #define ixATTR12                                                                                       0x0012
14986 #define ixATTR13                                                                                       0x0013
14987 #define ixATTR14                                                                                       0x0014
14988 
14989 
14990 // addressBlock: azendpoint_f2codecind
14991 // base address: 0x0
14992 #define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT                                           0x2200
14993 #define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID                                          0x2706
14994 #define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER                                          0x270d
14995 #define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_2                                        0x270e
14996 #define ixAZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL                                                     0x2724
14997 #define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3                                        0x273e
14998 #define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_RAMP_RATE                                                  0x2770
14999 #define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING                                              0x2771
15000 #define ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES                                0x2f09
15001 #define ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES                                     0x2f0a
15002 #define ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS                                           0x2f0b
15003 #define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY                                   0x3702
15004 #define ixAZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL                                                   0x3707
15005 #define ixAZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE                                             0x3708
15006 #define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE                                               0x3709
15007 #define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT                                   0x371c
15008 #define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2                                 0x371d
15009 #define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3                                 0x371e
15010 #define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4                                 0x371f
15011 #define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION                                      0x3770
15012 #define ixAZALIA_F2_CODEC_PIN_CONTROL_CHANNEL_ALLOCATION                                               0x3771
15013 #define ixAZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO                                                    0x3772
15014 #define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR                                                 0x3776
15015 #define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_DATA                                            0x3776
15016 #define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE                                            0x3777
15017 #define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE                                            0x3778
15018 #define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE                                            0x3779
15019 #define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE                                            0x377a
15020 #define ixAZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC                                                          0x377b
15021 #define ixAZALIA_F2_CODEC_PIN_CONTROL_HBR                                                              0x377c
15022 #define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_INDEX                                            0x3780
15023 #define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_DATA                                             0x3781
15024 #define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE                                             0x3785
15025 #define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE                                             0x3786
15026 #define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE                                             0x3787
15027 #define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE                                             0x3788
15028 #define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE                                                0x3789
15029 #define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0                                                    0x378a
15030 #define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1                                                    0x378b
15031 #define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2                                                    0x378c
15032 #define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3                                                    0x378d
15033 #define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4                                                    0x378e
15034 #define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5                                                    0x378f
15035 #define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6                                                    0x3790
15036 #define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7                                                    0x3791
15037 #define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8                                                    0x3792
15038 #define ixAZALIA_F2_CODEC_PIN_ASSOCIATION_INFO                                                         0x3793
15039 #define ixAZALIA_F2_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS                                            0x3797
15040 #define ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                                            0x3798
15041 #define ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB                                                             0x3799
15042 #define ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                                              0x379a
15043 #define ixAZALIA_F2_CODEC_PIN_CONTROL_CODING_TYPE                                                      0x379b
15044 #define ixAZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED                                                   0x379c
15045 #define ixAZALIA_F2_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION                                  0x379d
15046 #define ixAZALIA_F2_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE                                                 0x379e
15047 #define ixAZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES                                      0x3f09
15048 #define ixAZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES                                                   0x3f0c
15049 #define ixAZALIA_F2_CODEC_PIN_PARAMETER_CONNECTION_LIST_LENGTH                                         0x3f0e
15050 
15051 
15052 // addressBlock: azendpoint_descriptorind
15053 // base address: 0x0
15054 #define ixAUDIO_DESCRIPTOR0                                                                            0x0001
15055 #define ixAUDIO_DESCRIPTOR1                                                                            0x0002
15056 #define ixAUDIO_DESCRIPTOR2                                                                            0x0003
15057 #define ixAUDIO_DESCRIPTOR3                                                                            0x0004
15058 #define ixAUDIO_DESCRIPTOR4                                                                            0x0005
15059 #define ixAUDIO_DESCRIPTOR5                                                                            0x0006
15060 #define ixAUDIO_DESCRIPTOR6                                                                            0x0007
15061 #define ixAUDIO_DESCRIPTOR7                                                                            0x0008
15062 #define ixAUDIO_DESCRIPTOR8                                                                            0x0009
15063 #define ixAUDIO_DESCRIPTOR9                                                                            0x000a
15064 #define ixAUDIO_DESCRIPTOR10                                                                           0x000b
15065 #define ixAUDIO_DESCRIPTOR11                                                                           0x000c
15066 #define ixAUDIO_DESCRIPTOR12                                                                           0x000d
15067 #define ixAUDIO_DESCRIPTOR13                                                                           0x000e
15068 
15069 
15070 // addressBlock: azendpoint_sinkinfoind
15071 // base address: 0x0
15072 #define ixAZALIA_F2_CODEC_PIN_CONTROL_MANUFACTURER_ID                                                  0x0000
15073 #define ixAZALIA_F2_CODEC_PIN_CONTROL_PRODUCT_ID                                                       0x0001
15074 #define ixAZALIA_F2_CODEC_PIN_CONTROL_SINK_DESCRIPTION_LEN                                             0x0002
15075 #define ixAZALIA_F2_CODEC_PIN_CONTROL_PORTID0                                                          0x0003
15076 #define ixAZALIA_F2_CODEC_PIN_CONTROL_PORTID1                                                          0x0004
15077 #define ixSINK_DESCRIPTION0                                                                            0x0005
15078 #define ixSINK_DESCRIPTION1                                                                            0x0006
15079 #define ixSINK_DESCRIPTION2                                                                            0x0007
15080 #define ixSINK_DESCRIPTION3                                                                            0x0008
15081 #define ixSINK_DESCRIPTION4                                                                            0x0009
15082 #define ixSINK_DESCRIPTION5                                                                            0x000a
15083 #define ixSINK_DESCRIPTION6                                                                            0x000b
15084 #define ixSINK_DESCRIPTION7                                                                            0x000c
15085 #define ixSINK_DESCRIPTION8                                                                            0x000d
15086 #define ixSINK_DESCRIPTION9                                                                            0x000e
15087 #define ixSINK_DESCRIPTION10                                                                           0x000f
15088 #define ixSINK_DESCRIPTION11                                                                           0x0010
15089 #define ixSINK_DESCRIPTION12                                                                           0x0011
15090 #define ixSINK_DESCRIPTION13                                                                           0x0012
15091 #define ixSINK_DESCRIPTION14                                                                           0x0013
15092 #define ixSINK_DESCRIPTION15                                                                           0x0014
15093 #define ixSINK_DESCRIPTION16                                                                           0x0015
15094 #define ixSINK_DESCRIPTION17                                                                           0x0016
15095 
15096 
15097 // addressBlock: azf0controller_azinputcrc0resultind
15098 // base address: 0x0
15099 #define ixAZALIA_INPUT_CRC0_CHANNEL0                                                                   0x0000
15100 #define ixAZALIA_INPUT_CRC0_CHANNEL1                                                                   0x0001
15101 #define ixAZALIA_INPUT_CRC0_CHANNEL2                                                                   0x0002
15102 #define ixAZALIA_INPUT_CRC0_CHANNEL3                                                                   0x0003
15103 #define ixAZALIA_INPUT_CRC0_CHANNEL4                                                                   0x0004
15104 #define ixAZALIA_INPUT_CRC0_CHANNEL5                                                                   0x0005
15105 #define ixAZALIA_INPUT_CRC0_CHANNEL6                                                                   0x0006
15106 #define ixAZALIA_INPUT_CRC0_CHANNEL7                                                                   0x0007
15107 
15108 
15109 // addressBlock: azf0controller_azinputcrc1resultind
15110 // base address: 0x0
15111 #define ixAZALIA_INPUT_CRC1_CHANNEL0                                                                   0x0000
15112 #define ixAZALIA_INPUT_CRC1_CHANNEL1                                                                   0x0001
15113 #define ixAZALIA_INPUT_CRC1_CHANNEL2                                                                   0x0002
15114 #define ixAZALIA_INPUT_CRC1_CHANNEL3                                                                   0x0003
15115 #define ixAZALIA_INPUT_CRC1_CHANNEL4                                                                   0x0004
15116 #define ixAZALIA_INPUT_CRC1_CHANNEL5                                                                   0x0005
15117 #define ixAZALIA_INPUT_CRC1_CHANNEL6                                                                   0x0006
15118 #define ixAZALIA_INPUT_CRC1_CHANNEL7                                                                   0x0007
15119 
15120 
15121 // addressBlock: azf0controller_azcrc0resultind
15122 // base address: 0x0
15123 #define ixAZALIA_CRC0_CHANNEL0                                                                         0x0000
15124 #define ixAZALIA_CRC0_CHANNEL1                                                                         0x0001
15125 #define ixAZALIA_CRC0_CHANNEL2                                                                         0x0002
15126 #define ixAZALIA_CRC0_CHANNEL3                                                                         0x0003
15127 #define ixAZALIA_CRC0_CHANNEL4                                                                         0x0004
15128 #define ixAZALIA_CRC0_CHANNEL5                                                                         0x0005
15129 #define ixAZALIA_CRC0_CHANNEL6                                                                         0x0006
15130 #define ixAZALIA_CRC0_CHANNEL7                                                                         0x0007
15131 
15132 
15133 // addressBlock: azf0controller_azcrc1resultind
15134 // base address: 0x0
15135 #define ixAZALIA_CRC1_CHANNEL0                                                                         0x0000
15136 #define ixAZALIA_CRC1_CHANNEL1                                                                         0x0001
15137 #define ixAZALIA_CRC1_CHANNEL2                                                                         0x0002
15138 #define ixAZALIA_CRC1_CHANNEL3                                                                         0x0003
15139 #define ixAZALIA_CRC1_CHANNEL4                                                                         0x0004
15140 #define ixAZALIA_CRC1_CHANNEL5                                                                         0x0005
15141 #define ixAZALIA_CRC1_CHANNEL6                                                                         0x0006
15142 #define ixAZALIA_CRC1_CHANNEL7                                                                         0x0007
15143 
15144 
15145 // addressBlock: azinputendpoint_f2codecind
15146 // base address: 0x0
15147 #define ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT                                     0x6200
15148 #define ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID                                    0x6706
15149 #define ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER                                    0x670d
15150 #define ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES                          0x6f09
15151 #define ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES                               0x6f0a
15152 #define ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS                                     0x6f0b
15153 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL                                             0x7707
15154 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE                                       0x7708
15155 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_PIN_SENSE                                         0x7709
15156 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT                             0x771c
15157 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2                           0x771d
15158 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3                           0x771e
15159 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4                           0x771f
15160 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION                                         0x7771
15161 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE                                       0x7777
15162 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE                                       0x7778
15163 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE                                       0x7779
15164 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE                                       0x777a
15165 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_HBR                                                        0x777c
15166 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE                                       0x7785
15167 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE                                       0x7786
15168 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE                                       0x7787
15169 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE                                       0x7788
15170 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                                      0x7798
15171 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB                                                       0x7799
15172 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                                        0x779a
15173 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL                                       0x779b
15174 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME                                                  0x779c
15175 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_L                                           0x779d
15176 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_H                                           0x779e
15177 #define ixAZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES                                0x7f09
15178 #define ixAZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES                                             0x7f0c
15179 
15180 
15181 // addressBlock: azroot_f2codecind
15182 // base address: 0x0
15183 #define ixAZALIA_F2_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID                                          0x0f00
15184 #define ixAZALIA_F2_CODEC_ROOT_PARAMETER_REVISION_ID                                                   0x0f02
15185 #define ixAZALIA_F2_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT                                        0x0f04
15186 #define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE                                                 0x1705
15187 #define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID                                       0x1720
15188 #define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_2                                     0x1721
15189 #define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_3                                     0x1722
15190 #define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_4                                     0x1723
15191 #define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION                                   0x1770
15192 #define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESET                                                       0x17ff
15193 #define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT                                    0x1f04
15194 #define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_GROUP_TYPE                                                0x1f05
15195 #define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES                                      0x1f0a
15196 #define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS                                            0x1f0b
15197 #define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES                                              0x1f0f
15198 
15199 
15200 // addressBlock: azf0stream0_streamind
15201 // base address: 0x0
15202 #define ixAZF0STREAM0_AZALIA_FIFO_SIZE_CONTROL                                                         0x0000
15203 #define ixAZF0STREAM0_AZALIA_LATENCY_COUNTER_CONTROL                                                   0x0001
15204 #define ixAZF0STREAM0_AZALIA_WORSTCASE_LATENCY_COUNT                                                   0x0002
15205 #define ixAZF0STREAM0_AZALIA_CUMULATIVE_LATENCY_COUNT                                                  0x0003
15206 #define ixAZF0STREAM0_AZALIA_CUMULATIVE_REQUEST_COUNT                                                  0x0004
15207 
15208 
15209 // addressBlock: azf0stream1_streamind
15210 // base address: 0x0
15211 #define ixAZF0STREAM1_AZALIA_FIFO_SIZE_CONTROL                                                         0x0000
15212 #define ixAZF0STREAM1_AZALIA_LATENCY_COUNTER_CONTROL                                                   0x0001
15213 #define ixAZF0STREAM1_AZALIA_WORSTCASE_LATENCY_COUNT                                                   0x0002
15214 #define ixAZF0STREAM1_AZALIA_CUMULATIVE_LATENCY_COUNT                                                  0x0003
15215 #define ixAZF0STREAM1_AZALIA_CUMULATIVE_REQUEST_COUNT                                                  0x0004
15216 
15217 
15218 // addressBlock: azf0stream2_streamind
15219 // base address: 0x0
15220 #define ixAZF0STREAM2_AZALIA_FIFO_SIZE_CONTROL                                                         0x0000
15221 #define ixAZF0STREAM2_AZALIA_LATENCY_COUNTER_CONTROL                                                   0x0001
15222 #define ixAZF0STREAM2_AZALIA_WORSTCASE_LATENCY_COUNT                                                   0x0002
15223 #define ixAZF0STREAM2_AZALIA_CUMULATIVE_LATENCY_COUNT                                                  0x0003
15224 #define ixAZF0STREAM2_AZALIA_CUMULATIVE_REQUEST_COUNT                                                  0x0004
15225 
15226 
15227 // addressBlock: azf0stream3_streamind
15228 // base address: 0x0
15229 #define ixAZF0STREAM3_AZALIA_FIFO_SIZE_CONTROL                                                         0x0000
15230 #define ixAZF0STREAM3_AZALIA_LATENCY_COUNTER_CONTROL                                                   0x0001
15231 #define ixAZF0STREAM3_AZALIA_WORSTCASE_LATENCY_COUNT                                                   0x0002
15232 #define ixAZF0STREAM3_AZALIA_CUMULATIVE_LATENCY_COUNT                                                  0x0003
15233 #define ixAZF0STREAM3_AZALIA_CUMULATIVE_REQUEST_COUNT                                                  0x0004
15234 
15235 
15236 // addressBlock: azf0stream4_streamind
15237 // base address: 0x0
15238 #define ixAZF0STREAM4_AZALIA_FIFO_SIZE_CONTROL                                                         0x0000
15239 #define ixAZF0STREAM4_AZALIA_LATENCY_COUNTER_CONTROL                                                   0x0001
15240 #define ixAZF0STREAM4_AZALIA_WORSTCASE_LATENCY_COUNT                                                   0x0002
15241 #define ixAZF0STREAM4_AZALIA_CUMULATIVE_LATENCY_COUNT                                                  0x0003
15242 #define ixAZF0STREAM4_AZALIA_CUMULATIVE_REQUEST_COUNT                                                  0x0004
15243 
15244 
15245 // addressBlock: azf0stream5_streamind
15246 // base address: 0x0
15247 #define ixAZF0STREAM5_AZALIA_FIFO_SIZE_CONTROL                                                         0x0000
15248 #define ixAZF0STREAM5_AZALIA_LATENCY_COUNTER_CONTROL                                                   0x0001
15249 #define ixAZF0STREAM5_AZALIA_WORSTCASE_LATENCY_COUNT                                                   0x0002
15250 #define ixAZF0STREAM5_AZALIA_CUMULATIVE_LATENCY_COUNT                                                  0x0003
15251 #define ixAZF0STREAM5_AZALIA_CUMULATIVE_REQUEST_COUNT                                                  0x0004
15252 
15253 
15254 // addressBlock: azf0stream6_streamind
15255 // base address: 0x0
15256 #define ixAZF0STREAM6_AZALIA_FIFO_SIZE_CONTROL                                                         0x0000
15257 #define ixAZF0STREAM6_AZALIA_LATENCY_COUNTER_CONTROL                                                   0x0001
15258 #define ixAZF0STREAM6_AZALIA_WORSTCASE_LATENCY_COUNT                                                   0x0002
15259 #define ixAZF0STREAM6_AZALIA_CUMULATIVE_LATENCY_COUNT                                                  0x0003
15260 #define ixAZF0STREAM6_AZALIA_CUMULATIVE_REQUEST_COUNT                                                  0x0004
15261 
15262 
15263 // addressBlock: azf0stream7_streamind
15264 // base address: 0x0
15265 #define ixAZF0STREAM7_AZALIA_FIFO_SIZE_CONTROL                                                         0x0000
15266 #define ixAZF0STREAM7_AZALIA_LATENCY_COUNTER_CONTROL                                                   0x0001
15267 #define ixAZF0STREAM7_AZALIA_WORSTCASE_LATENCY_COUNT                                                   0x0002
15268 #define ixAZF0STREAM7_AZALIA_CUMULATIVE_LATENCY_COUNT                                                  0x0003
15269 #define ixAZF0STREAM7_AZALIA_CUMULATIVE_REQUEST_COUNT                                                  0x0004
15270 
15271 
15272 // addressBlock: azf0stream8_streamind
15273 // base address: 0x0
15274 #define ixAZF0STREAM8_AZALIA_FIFO_SIZE_CONTROL                                                         0x0000
15275 #define ixAZF0STREAM8_AZALIA_LATENCY_COUNTER_CONTROL                                                   0x0001
15276 #define ixAZF0STREAM8_AZALIA_WORSTCASE_LATENCY_COUNT                                                   0x0002
15277 #define ixAZF0STREAM8_AZALIA_CUMULATIVE_LATENCY_COUNT                                                  0x0003
15278 #define ixAZF0STREAM8_AZALIA_CUMULATIVE_REQUEST_COUNT                                                  0x0004
15279 
15280 
15281 // addressBlock: azf0stream9_streamind
15282 // base address: 0x0
15283 #define ixAZF0STREAM9_AZALIA_FIFO_SIZE_CONTROL                                                         0x0000
15284 #define ixAZF0STREAM9_AZALIA_LATENCY_COUNTER_CONTROL                                                   0x0001
15285 #define ixAZF0STREAM9_AZALIA_WORSTCASE_LATENCY_COUNT                                                   0x0002
15286 #define ixAZF0STREAM9_AZALIA_CUMULATIVE_LATENCY_COUNT                                                  0x0003
15287 #define ixAZF0STREAM9_AZALIA_CUMULATIVE_REQUEST_COUNT                                                  0x0004
15288 
15289 
15290 // addressBlock: azf0stream10_streamind
15291 // base address: 0x0
15292 #define ixAZF0STREAM10_AZALIA_FIFO_SIZE_CONTROL                                                        0x0000
15293 #define ixAZF0STREAM10_AZALIA_LATENCY_COUNTER_CONTROL                                                  0x0001
15294 #define ixAZF0STREAM10_AZALIA_WORSTCASE_LATENCY_COUNT                                                  0x0002
15295 #define ixAZF0STREAM10_AZALIA_CUMULATIVE_LATENCY_COUNT                                                 0x0003
15296 #define ixAZF0STREAM10_AZALIA_CUMULATIVE_REQUEST_COUNT                                                 0x0004
15297 
15298 
15299 // addressBlock: azf0stream11_streamind
15300 // base address: 0x0
15301 #define ixAZF0STREAM11_AZALIA_FIFO_SIZE_CONTROL                                                        0x0000
15302 #define ixAZF0STREAM11_AZALIA_LATENCY_COUNTER_CONTROL                                                  0x0001
15303 #define ixAZF0STREAM11_AZALIA_WORSTCASE_LATENCY_COUNT                                                  0x0002
15304 #define ixAZF0STREAM11_AZALIA_CUMULATIVE_LATENCY_COUNT                                                 0x0003
15305 #define ixAZF0STREAM11_AZALIA_CUMULATIVE_REQUEST_COUNT                                                 0x0004
15306 
15307 
15308 // addressBlock: azf0stream12_streamind
15309 // base address: 0x0
15310 #define ixAZF0STREAM12_AZALIA_FIFO_SIZE_CONTROL                                                        0x0000
15311 #define ixAZF0STREAM12_AZALIA_LATENCY_COUNTER_CONTROL                                                  0x0001
15312 #define ixAZF0STREAM12_AZALIA_WORSTCASE_LATENCY_COUNT                                                  0x0002
15313 #define ixAZF0STREAM12_AZALIA_CUMULATIVE_LATENCY_COUNT                                                 0x0003
15314 #define ixAZF0STREAM12_AZALIA_CUMULATIVE_REQUEST_COUNT                                                 0x0004
15315 
15316 
15317 // addressBlock: azf0stream13_streamind
15318 // base address: 0x0
15319 #define ixAZF0STREAM13_AZALIA_FIFO_SIZE_CONTROL                                                        0x0000
15320 #define ixAZF0STREAM13_AZALIA_LATENCY_COUNTER_CONTROL                                                  0x0001
15321 #define ixAZF0STREAM13_AZALIA_WORSTCASE_LATENCY_COUNT                                                  0x0002
15322 #define ixAZF0STREAM13_AZALIA_CUMULATIVE_LATENCY_COUNT                                                 0x0003
15323 #define ixAZF0STREAM13_AZALIA_CUMULATIVE_REQUEST_COUNT                                                 0x0004
15324 
15325 
15326 // addressBlock: azf0stream14_streamind
15327 // base address: 0x0
15328 #define ixAZF0STREAM14_AZALIA_FIFO_SIZE_CONTROL                                                        0x0000
15329 #define ixAZF0STREAM14_AZALIA_LATENCY_COUNTER_CONTROL                                                  0x0001
15330 #define ixAZF0STREAM14_AZALIA_WORSTCASE_LATENCY_COUNT                                                  0x0002
15331 #define ixAZF0STREAM14_AZALIA_CUMULATIVE_LATENCY_COUNT                                                 0x0003
15332 #define ixAZF0STREAM14_AZALIA_CUMULATIVE_REQUEST_COUNT                                                 0x0004
15333 
15334 
15335 // addressBlock: azf0stream15_streamind
15336 // base address: 0x0
15337 #define ixAZF0STREAM15_AZALIA_FIFO_SIZE_CONTROL                                                        0x0000
15338 #define ixAZF0STREAM15_AZALIA_LATENCY_COUNTER_CONTROL                                                  0x0001
15339 #define ixAZF0STREAM15_AZALIA_WORSTCASE_LATENCY_COUNT                                                  0x0002
15340 #define ixAZF0STREAM15_AZALIA_CUMULATIVE_LATENCY_COUNT                                                 0x0003
15341 #define ixAZF0STREAM15_AZALIA_CUMULATIVE_REQUEST_COUNT                                                 0x0004
15342 
15343 
15344 // addressBlock: azf0endpoint0_endpointind
15345 // base address: 0x0
15346 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES                  0x0001
15347 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT                             0x0002
15348 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID                            0x0003
15349 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER                            0x0004
15350 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS                             0x0005
15351 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES                       0x0006
15352 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL                                       0x0007
15353 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE                                    0x0008
15354 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING                                0x0009
15355 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA                                    0x000c
15356 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN                                0x000d
15357 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX                                0x000e
15358 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES                        0x0020
15359 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES                                     0x0021
15360 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE                               0x0022
15361 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE                                 0x0023
15362 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL                                     0x0024
15363 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER                                    0x0025
15364 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0                                  0x0028
15365 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1                                  0x0029
15366 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2                                  0x002a
15367 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3                                  0x002b
15368 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4                                  0x002c
15369 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5                                  0x002d
15370 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6                                  0x002e
15371 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7                                  0x002f
15372 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8                                  0x0030
15373 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9                                  0x0031
15374 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10                                 0x0032
15375 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11                                 0x0033
15376 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12                                 0x0034
15377 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13                                 0x0035
15378 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE                                0x0036
15379 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC                                   0x0037
15380 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR                                       0x0038
15381 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0                                         0x003a
15382 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1                                         0x003b
15383 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2                                         0x003c
15384 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3                                         0x003d
15385 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4                                         0x003e
15386 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5                                         0x003f
15387 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6                                         0x0040
15388 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7                                         0x0041
15389 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8                                         0x0042
15390 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL                                   0x0054
15391 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE                         0x0055
15392 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT                     0x0056
15393 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2                               0x0057
15394 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE                                  0x0058
15395 #define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0                                      0x0059
15396 #define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1                                      0x005a
15397 #define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2                                      0x005b
15398 #define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3                                      0x005c
15399 #define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4                                      0x005d
15400 #define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5                                      0x005e
15401 #define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6                                      0x005f
15402 #define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7                                      0x0060
15403 #define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8                                      0x0061
15404 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO                                           0x0062
15405 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS                              0x0063
15406 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                              0x0064
15407 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB                                               0x0065
15408 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                                0x0066
15409 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE                                        0x0067
15410 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED                                     0x0068
15411 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION                    0x0069
15412 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE                                   0x006a
15413 #define ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLE_STATUS                                                  0x006b
15414 #define ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLED_INT_STATUS                                             0x006c
15415 #define ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_DISABLED_INT_STATUS                                            0x006d
15416 #define ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS                                      0x006e
15417 
15418 
15419 // addressBlock: azf0endpoint1_endpointind
15420 // base address: 0x0
15421 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES                  0x0001
15422 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT                             0x0002
15423 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID                            0x0003
15424 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER                            0x0004
15425 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS                             0x0005
15426 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES                       0x0006
15427 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL                                       0x0007
15428 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE                                    0x0008
15429 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING                                0x0009
15430 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA                                    0x000c
15431 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN                                0x000d
15432 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX                                0x000e
15433 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES                        0x0020
15434 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES                                     0x0021
15435 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE                               0x0022
15436 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE                                 0x0023
15437 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL                                     0x0024
15438 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER                                    0x0025
15439 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0                                  0x0028
15440 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1                                  0x0029
15441 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2                                  0x002a
15442 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3                                  0x002b
15443 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4                                  0x002c
15444 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5                                  0x002d
15445 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6                                  0x002e
15446 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7                                  0x002f
15447 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8                                  0x0030
15448 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9                                  0x0031
15449 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10                                 0x0032
15450 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11                                 0x0033
15451 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12                                 0x0034
15452 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13                                 0x0035
15453 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE                                0x0036
15454 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC                                   0x0037
15455 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR                                       0x0038
15456 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0                                         0x003a
15457 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1                                         0x003b
15458 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2                                         0x003c
15459 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3                                         0x003d
15460 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4                                         0x003e
15461 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5                                         0x003f
15462 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6                                         0x0040
15463 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7                                         0x0041
15464 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8                                         0x0042
15465 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL                                   0x0054
15466 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE                         0x0055
15467 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT                     0x0056
15468 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2                               0x0057
15469 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE                                  0x0058
15470 #define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0                                      0x0059
15471 #define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1                                      0x005a
15472 #define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2                                      0x005b
15473 #define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3                                      0x005c
15474 #define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4                                      0x005d
15475 #define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5                                      0x005e
15476 #define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6                                      0x005f
15477 #define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7                                      0x0060
15478 #define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8                                      0x0061
15479 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO                                           0x0062
15480 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS                              0x0063
15481 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                              0x0064
15482 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB                                               0x0065
15483 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                                0x0066
15484 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE                                        0x0067
15485 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED                                     0x0068
15486 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION                    0x0069
15487 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE                                   0x006a
15488 #define ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLE_STATUS                                                  0x006b
15489 #define ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLED_INT_STATUS                                             0x006c
15490 #define ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_DISABLED_INT_STATUS                                            0x006d
15491 #define ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS                                      0x006e
15492 
15493 
15494 // addressBlock: azf0endpoint2_endpointind
15495 // base address: 0x0
15496 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES                  0x0001
15497 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT                             0x0002
15498 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID                            0x0003
15499 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER                            0x0004
15500 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS                             0x0005
15501 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES                       0x0006
15502 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL                                       0x0007
15503 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE                                    0x0008
15504 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING                                0x0009
15505 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA                                    0x000c
15506 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN                                0x000d
15507 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX                                0x000e
15508 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES                        0x0020
15509 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES                                     0x0021
15510 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE                               0x0022
15511 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE                                 0x0023
15512 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL                                     0x0024
15513 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER                                    0x0025
15514 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0                                  0x0028
15515 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1                                  0x0029
15516 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2                                  0x002a
15517 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3                                  0x002b
15518 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4                                  0x002c
15519 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5                                  0x002d
15520 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6                                  0x002e
15521 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7                                  0x002f
15522 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8                                  0x0030
15523 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9                                  0x0031
15524 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10                                 0x0032
15525 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11                                 0x0033
15526 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12                                 0x0034
15527 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13                                 0x0035
15528 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE                                0x0036
15529 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC                                   0x0037
15530 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR                                       0x0038
15531 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0                                         0x003a
15532 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1                                         0x003b
15533 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2                                         0x003c
15534 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3                                         0x003d
15535 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4                                         0x003e
15536 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5                                         0x003f
15537 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6                                         0x0040
15538 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7                                         0x0041
15539 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8                                         0x0042
15540 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL                                   0x0054
15541 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE                         0x0055
15542 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT                     0x0056
15543 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2                               0x0057
15544 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE                                  0x0058
15545 #define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0                                      0x0059
15546 #define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1                                      0x005a
15547 #define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2                                      0x005b
15548 #define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3                                      0x005c
15549 #define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4                                      0x005d
15550 #define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5                                      0x005e
15551 #define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6                                      0x005f
15552 #define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7                                      0x0060
15553 #define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8                                      0x0061
15554 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO                                           0x0062
15555 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS                              0x0063
15556 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                              0x0064
15557 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB                                               0x0065
15558 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                                0x0066
15559 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE                                        0x0067
15560 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED                                     0x0068
15561 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION                    0x0069
15562 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE                                   0x006a
15563 #define ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLE_STATUS                                                  0x006b
15564 #define ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLED_INT_STATUS                                             0x006c
15565 #define ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_DISABLED_INT_STATUS                                            0x006d
15566 #define ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS                                      0x006e
15567 
15568 
15569 // addressBlock: azf0endpoint3_endpointind
15570 // base address: 0x0
15571 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES                  0x0001
15572 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT                             0x0002
15573 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID                            0x0003
15574 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER                            0x0004
15575 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS                             0x0005
15576 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES                       0x0006
15577 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL                                       0x0007
15578 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE                                    0x0008
15579 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING                                0x0009
15580 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA                                    0x000c
15581 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN                                0x000d
15582 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX                                0x000e
15583 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES                        0x0020
15584 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES                                     0x0021
15585 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE                               0x0022
15586 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE                                 0x0023
15587 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL                                     0x0024
15588 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER                                    0x0025
15589 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0                                  0x0028
15590 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1                                  0x0029
15591 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2                                  0x002a
15592 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3                                  0x002b
15593 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4                                  0x002c
15594 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5                                  0x002d
15595 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6                                  0x002e
15596 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7                                  0x002f
15597 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8                                  0x0030
15598 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9                                  0x0031
15599 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10                                 0x0032
15600 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11                                 0x0033
15601 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12                                 0x0034
15602 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13                                 0x0035
15603 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE                                0x0036
15604 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC                                   0x0037
15605 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR                                       0x0038
15606 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0                                         0x003a
15607 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1                                         0x003b
15608 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2                                         0x003c
15609 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3                                         0x003d
15610 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4                                         0x003e
15611 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5                                         0x003f
15612 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6                                         0x0040
15613 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7                                         0x0041
15614 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8                                         0x0042
15615 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL                                   0x0054
15616 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE                         0x0055
15617 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT                     0x0056
15618 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2                               0x0057
15619 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE                                  0x0058
15620 #define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0                                      0x0059
15621 #define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1                                      0x005a
15622 #define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2                                      0x005b
15623 #define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3                                      0x005c
15624 #define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4                                      0x005d
15625 #define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5                                      0x005e
15626 #define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6                                      0x005f
15627 #define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7                                      0x0060
15628 #define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8                                      0x0061
15629 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO                                           0x0062
15630 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS                              0x0063
15631 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                              0x0064
15632 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB                                               0x0065
15633 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                                0x0066
15634 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE                                        0x0067
15635 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED                                     0x0068
15636 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION                    0x0069
15637 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE                                   0x006a
15638 #define ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLE_STATUS                                                  0x006b
15639 #define ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLED_INT_STATUS                                             0x006c
15640 #define ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_DISABLED_INT_STATUS                                            0x006d
15641 #define ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS                                      0x006e
15642 
15643 
15644 // addressBlock: azf0endpoint4_endpointind
15645 // base address: 0x0
15646 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES                  0x0001
15647 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT                             0x0002
15648 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID                            0x0003
15649 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER                            0x0004
15650 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS                             0x0005
15651 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES                       0x0006
15652 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL                                       0x0007
15653 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE                                    0x0008
15654 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING                                0x0009
15655 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA                                    0x000c
15656 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN                                0x000d
15657 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX                                0x000e
15658 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES                        0x0020
15659 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES                                     0x0021
15660 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE                               0x0022
15661 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE                                 0x0023
15662 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL                                     0x0024
15663 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER                                    0x0025
15664 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0                                  0x0028
15665 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1                                  0x0029
15666 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2                                  0x002a
15667 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3                                  0x002b
15668 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4                                  0x002c
15669 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5                                  0x002d
15670 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6                                  0x002e
15671 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7                                  0x002f
15672 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8                                  0x0030
15673 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9                                  0x0031
15674 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10                                 0x0032
15675 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11                                 0x0033
15676 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12                                 0x0034
15677 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13                                 0x0035
15678 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE                                0x0036
15679 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC                                   0x0037
15680 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR                                       0x0038
15681 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0                                         0x003a
15682 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1                                         0x003b
15683 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2                                         0x003c
15684 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3                                         0x003d
15685 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4                                         0x003e
15686 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5                                         0x003f
15687 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6                                         0x0040
15688 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7                                         0x0041
15689 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8                                         0x0042
15690 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL                                   0x0054
15691 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE                         0x0055
15692 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT                     0x0056
15693 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2                               0x0057
15694 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE                                  0x0058
15695 #define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0                                      0x0059
15696 #define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1                                      0x005a
15697 #define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2                                      0x005b
15698 #define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3                                      0x005c
15699 #define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4                                      0x005d
15700 #define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5                                      0x005e
15701 #define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6                                      0x005f
15702 #define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7                                      0x0060
15703 #define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8                                      0x0061
15704 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO                                           0x0062
15705 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS                              0x0063
15706 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                              0x0064
15707 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB                                               0x0065
15708 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                                0x0066
15709 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE                                        0x0067
15710 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED                                     0x0068
15711 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION                    0x0069
15712 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE                                   0x006a
15713 #define ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLE_STATUS                                                  0x006b
15714 #define ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLED_INT_STATUS                                             0x006c
15715 #define ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_DISABLED_INT_STATUS                                            0x006d
15716 #define ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS                                      0x006e
15717 
15718 
15719 // addressBlock: azf0endpoint5_endpointind
15720 // base address: 0x0
15721 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES                  0x0001
15722 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT                             0x0002
15723 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID                            0x0003
15724 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER                            0x0004
15725 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS                             0x0005
15726 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES                       0x0006
15727 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL                                       0x0007
15728 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE                                    0x0008
15729 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING                                0x0009
15730 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA                                    0x000c
15731 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN                                0x000d
15732 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX                                0x000e
15733 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES                        0x0020
15734 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES                                     0x0021
15735 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE                               0x0022
15736 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE                                 0x0023
15737 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL                                     0x0024
15738 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER                                    0x0025
15739 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0                                  0x0028
15740 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1                                  0x0029
15741 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2                                  0x002a
15742 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3                                  0x002b
15743 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4                                  0x002c
15744 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5                                  0x002d
15745 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6                                  0x002e
15746 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7                                  0x002f
15747 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8                                  0x0030
15748 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9                                  0x0031
15749 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10                                 0x0032
15750 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11                                 0x0033
15751 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12                                 0x0034
15752 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13                                 0x0035
15753 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE                                0x0036
15754 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC                                   0x0037
15755 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR                                       0x0038
15756 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0                                         0x003a
15757 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1                                         0x003b
15758 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2                                         0x003c
15759 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3                                         0x003d
15760 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4                                         0x003e
15761 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5                                         0x003f
15762 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6                                         0x0040
15763 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7                                         0x0041
15764 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8                                         0x0042
15765 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL                                   0x0054
15766 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE                         0x0055
15767 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT                     0x0056
15768 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2                               0x0057
15769 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE                                  0x0058
15770 #define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0                                      0x0059
15771 #define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1                                      0x005a
15772 #define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2                                      0x005b
15773 #define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3                                      0x005c
15774 #define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4                                      0x005d
15775 #define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5                                      0x005e
15776 #define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6                                      0x005f
15777 #define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7                                      0x0060
15778 #define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8                                      0x0061
15779 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO                                           0x0062
15780 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS                              0x0063
15781 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                              0x0064
15782 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB                                               0x0065
15783 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                                0x0066
15784 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE                                        0x0067
15785 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED                                     0x0068
15786 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION                    0x0069
15787 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE                                   0x006a
15788 #define ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLE_STATUS                                                  0x006b
15789 #define ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLED_INT_STATUS                                             0x006c
15790 #define ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_DISABLED_INT_STATUS                                            0x006d
15791 #define ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS                                      0x006e
15792 
15793 
15794 // addressBlock: azf0endpoint6_endpointind
15795 // base address: 0x0
15796 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES                  0x0001
15797 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT                             0x0002
15798 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID                            0x0003
15799 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER                            0x0004
15800 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS                             0x0005
15801 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES                       0x0006
15802 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL                                       0x0007
15803 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE                                    0x0008
15804 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING                                0x0009
15805 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA                                    0x000c
15806 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN                                0x000d
15807 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX                                0x000e
15808 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES                        0x0020
15809 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES                                     0x0021
15810 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE                               0x0022
15811 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE                                 0x0023
15812 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL                                     0x0024
15813 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER                                    0x0025
15814 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0                                  0x0028
15815 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1                                  0x0029
15816 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2                                  0x002a
15817 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3                                  0x002b
15818 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4                                  0x002c
15819 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5                                  0x002d
15820 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6                                  0x002e
15821 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7                                  0x002f
15822 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8                                  0x0030
15823 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9                                  0x0031
15824 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10                                 0x0032
15825 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11                                 0x0033
15826 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12                                 0x0034
15827 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13                                 0x0035
15828 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE                                0x0036
15829 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC                                   0x0037
15830 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR                                       0x0038
15831 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0                                         0x003a
15832 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1                                         0x003b
15833 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2                                         0x003c
15834 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3                                         0x003d
15835 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4                                         0x003e
15836 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5                                         0x003f
15837 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6                                         0x0040
15838 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7                                         0x0041
15839 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8                                         0x0042
15840 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL                                   0x0054
15841 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE                         0x0055
15842 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT                     0x0056
15843 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2                               0x0057
15844 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE                                  0x0058
15845 #define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0                                      0x0059
15846 #define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1                                      0x005a
15847 #define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2                                      0x005b
15848 #define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3                                      0x005c
15849 #define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4                                      0x005d
15850 #define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5                                      0x005e
15851 #define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6                                      0x005f
15852 #define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7                                      0x0060
15853 #define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8                                      0x0061
15854 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO                                           0x0062
15855 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS                              0x0063
15856 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                              0x0064
15857 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB                                               0x0065
15858 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                                0x0066
15859 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE                                        0x0067
15860 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED                                     0x0068
15861 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION                    0x0069
15862 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE                                   0x006a
15863 #define ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLE_STATUS                                                  0x006b
15864 #define ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLED_INT_STATUS                                             0x006c
15865 #define ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_DISABLED_INT_STATUS                                            0x006d
15866 #define ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS                                      0x006e
15867 
15868 
15869 // addressBlock: azf0endpoint7_endpointind
15870 // base address: 0x0
15871 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES                  0x0001
15872 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT                             0x0002
15873 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID                            0x0003
15874 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER                            0x0004
15875 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS                             0x0005
15876 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES                       0x0006
15877 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL                                       0x0007
15878 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE                                    0x0008
15879 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING                                0x0009
15880 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA                                    0x000c
15881 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN                                0x000d
15882 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX                                0x000e
15883 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES                        0x0020
15884 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES                                     0x0021
15885 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE                               0x0022
15886 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE                                 0x0023
15887 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL                                     0x0024
15888 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER                                    0x0025
15889 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0                                  0x0028
15890 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1                                  0x0029
15891 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2                                  0x002a
15892 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3                                  0x002b
15893 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4                                  0x002c
15894 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5                                  0x002d
15895 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6                                  0x002e
15896 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7                                  0x002f
15897 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8                                  0x0030
15898 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9                                  0x0031
15899 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10                                 0x0032
15900 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11                                 0x0033
15901 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12                                 0x0034
15902 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13                                 0x0035
15903 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE                                0x0036
15904 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC                                   0x0037
15905 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR                                       0x0038
15906 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0                                         0x003a
15907 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1                                         0x003b
15908 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2                                         0x003c
15909 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3                                         0x003d
15910 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4                                         0x003e
15911 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5                                         0x003f
15912 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6                                         0x0040
15913 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7                                         0x0041
15914 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8                                         0x0042
15915 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL                                   0x0054
15916 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE                         0x0055
15917 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT                     0x0056
15918 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2                               0x0057
15919 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE                                  0x0058
15920 #define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0                                      0x0059
15921 #define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1                                      0x005a
15922 #define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2                                      0x005b
15923 #define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3                                      0x005c
15924 #define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4                                      0x005d
15925 #define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5                                      0x005e
15926 #define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6                                      0x005f
15927 #define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7                                      0x0060
15928 #define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8                                      0x0061
15929 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO                                           0x0062
15930 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS                              0x0063
15931 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                              0x0064
15932 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB                                               0x0065
15933 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                                0x0066
15934 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE                                        0x0067
15935 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED                                     0x0068
15936 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION                    0x0069
15937 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE                                   0x006a
15938 #define ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLE_STATUS                                                  0x006b
15939 #define ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLED_INT_STATUS                                             0x006c
15940 #define ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_DISABLED_INT_STATUS                                            0x006d
15941 #define ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS                                      0x006e
15942 
15943 
15944 // addressBlock: azf0inputendpoint0_inputendpointind
15945 // base address: 0x0
15946 #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES       0x0001
15947 #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT                  0x0002
15948 #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID                 0x0003
15949 #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER                 0x0004
15950 #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS                  0x0005
15951 #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES            0x0006
15952 #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES             0x0020
15953 #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES                          0x0021
15954 #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE                    0x0022
15955 #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE                0x0023
15956 #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL                          0x0024
15957 #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE                     0x0036
15958 #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2                    0x0037
15959 #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR                            0x0038
15960 #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION                      0x0053
15961 #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL                        0x0054
15962 #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE              0x0055
15963 #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT          0x0056
15964 #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                   0x0064
15965 #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB                                    0x0065
15966 #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                     0x0066
15967 #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL                    0x0067
15968 #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME                               0x0068
15969 
15970 
15971 // addressBlock: azf0inputendpoint1_inputendpointind
15972 // base address: 0x0
15973 #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES       0x0001
15974 #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT                  0x0002
15975 #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID                 0x0003
15976 #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER                 0x0004
15977 #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS                  0x0005
15978 #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES            0x0006
15979 #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES             0x0020
15980 #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES                          0x0021
15981 #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE                    0x0022
15982 #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE                0x0023
15983 #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL                          0x0024
15984 #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE                     0x0036
15985 #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2                    0x0037
15986 #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR                            0x0038
15987 #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION                      0x0053
15988 #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL                        0x0054
15989 #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE              0x0055
15990 #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT          0x0056
15991 #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                   0x0064
15992 #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB                                    0x0065
15993 #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                     0x0066
15994 #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL                    0x0067
15995 #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME                               0x0068
15996 
15997 
15998 // addressBlock: azf0inputendpoint2_inputendpointind
15999 // base address: 0x0
16000 #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES       0x0001
16001 #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT                  0x0002
16002 #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID                 0x0003
16003 #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER                 0x0004
16004 #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS                  0x0005
16005 #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES            0x0006
16006 #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES             0x0020
16007 #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES                          0x0021
16008 #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE                    0x0022
16009 #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE                0x0023
16010 #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL                          0x0024
16011 #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE                     0x0036
16012 #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2                    0x0037
16013 #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR                            0x0038
16014 #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION                      0x0053
16015 #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL                        0x0054
16016 #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE              0x0055
16017 #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT          0x0056
16018 #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                   0x0064
16019 #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB                                    0x0065
16020 #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                     0x0066
16021 #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL                    0x0067
16022 #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME                               0x0068
16023 
16024 
16025 // addressBlock: azf0inputendpoint3_inputendpointind
16026 // base address: 0x0
16027 #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES       0x0001
16028 #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT                  0x0002
16029 #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID                 0x0003
16030 #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER                 0x0004
16031 #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS                  0x0005
16032 #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES            0x0006
16033 #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES             0x0020
16034 #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES                          0x0021
16035 #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE                    0x0022
16036 #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE                0x0023
16037 #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL                          0x0024
16038 #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE                     0x0036
16039 #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2                    0x0037
16040 #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR                            0x0038
16041 #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION                      0x0053
16042 #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL                        0x0054
16043 #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE              0x0055
16044 #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT          0x0056
16045 #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                   0x0064
16046 #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB                                    0x0065
16047 #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                     0x0066
16048 #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL                    0x0067
16049 #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME                               0x0068
16050 
16051 
16052 // addressBlock: azf0inputendpoint4_inputendpointind
16053 // base address: 0x0
16054 #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES       0x0001
16055 #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT                  0x0002
16056 #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID                 0x0003
16057 #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER                 0x0004
16058 #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS                  0x0005
16059 #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES            0x0006
16060 #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES             0x0020
16061 #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES                          0x0021
16062 #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE                    0x0022
16063 #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE                0x0023
16064 #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL                          0x0024
16065 #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE                     0x0036
16066 #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2                    0x0037
16067 #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR                            0x0038
16068 #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION                      0x0053
16069 #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL                        0x0054
16070 #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE              0x0055
16071 #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT          0x0056
16072 #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                   0x0064
16073 #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB                                    0x0065
16074 #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                     0x0066
16075 #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL                    0x0067
16076 #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME                               0x0068
16077 
16078 
16079 // addressBlock: azf0inputendpoint5_inputendpointind
16080 // base address: 0x0
16081 #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES       0x0001
16082 #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT                  0x0002
16083 #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID                 0x0003
16084 #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER                 0x0004
16085 #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS                  0x0005
16086 #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES            0x0006
16087 #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES             0x0020
16088 #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES                          0x0021
16089 #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE                    0x0022
16090 #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE                0x0023
16091 #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL                          0x0024
16092 #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE                     0x0036
16093 #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2                    0x0037
16094 #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR                            0x0038
16095 #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION                      0x0053
16096 #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL                        0x0054
16097 #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE              0x0055
16098 #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT          0x0056
16099 #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                   0x0064
16100 #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB                                    0x0065
16101 #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                     0x0066
16102 #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL                    0x0067
16103 #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME                               0x0068
16104 
16105 
16106 // addressBlock: azf0inputendpoint6_inputendpointind
16107 // base address: 0x0
16108 #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES       0x0001
16109 #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT                  0x0002
16110 #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID                 0x0003
16111 #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER                 0x0004
16112 #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS                  0x0005
16113 #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES            0x0006
16114 #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES             0x0020
16115 #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES                          0x0021
16116 #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE                    0x0022
16117 #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE                0x0023
16118 #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL                          0x0024
16119 #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE                     0x0036
16120 #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2                    0x0037
16121 #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR                            0x0038
16122 #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION                      0x0053
16123 #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL                        0x0054
16124 #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE              0x0055
16125 #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT          0x0056
16126 #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                   0x0064
16127 #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB                                    0x0065
16128 #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                     0x0066
16129 #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL                    0x0067
16130 #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME                               0x0068
16131 
16132 
16133 // addressBlock: azf0inputendpoint7_inputendpointind
16134 // base address: 0x0
16135 #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES       0x0001
16136 #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT                  0x0002
16137 #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID                 0x0003
16138 #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER                 0x0004
16139 #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS                  0x0005
16140 #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES            0x0006
16141 #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES             0x0020
16142 #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES                          0x0021
16143 #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE                    0x0022
16144 #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE                0x0023
16145 #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL                          0x0024
16146 #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE                     0x0036
16147 #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2                    0x0037
16148 #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR                            0x0038
16149 #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION                      0x0053
16150 #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL                        0x0054
16151 #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE              0x0055
16152 #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT          0x0056
16153 #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                   0x0064
16154 #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB                                    0x0065
16155 #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                     0x0066
16156 #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL                    0x0067
16157 #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME                               0x0068
16158 
16159 #endif
16160