1de2bdb3dSTom St Denis /* 2de2bdb3dSTom St Denis * 3de2bdb3dSTom St Denis * Copyright (C) 2016 Advanced Micro Devices, Inc. 4de2bdb3dSTom St Denis * 5de2bdb3dSTom St Denis * Permission is hereby granted, free of charge, to any person obtaining a 6de2bdb3dSTom St Denis * copy of this software and associated documentation files (the "Software"), 7de2bdb3dSTom St Denis * to deal in the Software without restriction, including without limitation 8de2bdb3dSTom St Denis * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9de2bdb3dSTom St Denis * and/or sell copies of the Software, and to permit persons to whom the 10de2bdb3dSTom St Denis * Software is furnished to do so, subject to the following conditions: 11de2bdb3dSTom St Denis * 12de2bdb3dSTom St Denis * The above copyright notice and this permission notice shall be included 13de2bdb3dSTom St Denis * in all copies or substantial portions of the Software. 14de2bdb3dSTom St Denis * 15de2bdb3dSTom St Denis * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 16de2bdb3dSTom St Denis * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17de2bdb3dSTom St Denis * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18de2bdb3dSTom St Denis * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN 19de2bdb3dSTom St Denis * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 20de2bdb3dSTom St Denis * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 21de2bdb3dSTom St Denis */ 22de2bdb3dSTom St Denis 23de2bdb3dSTom St Denis #ifndef DCE_6_0_SH_MASK_H 24de2bdb3dSTom St Denis #define DCE_6_0_SH_MASK_H 25de2bdb3dSTom St Denis 26de2bdb3dSTom St Denis #define ABM_TEST_DEBUG_DATA__ABM_TEST_DEBUG_DATA_MASK 0xffffffffL 27de2bdb3dSTom St Denis #define ABM_TEST_DEBUG_DATA__ABM_TEST_DEBUG_DATA__SHIFT 0x00000000 28de2bdb3dSTom St Denis #define ABM_TEST_DEBUG_INDEX__ABM_TEST_DEBUG_INDEX_MASK 0x000000ffL 29de2bdb3dSTom St Denis #define ABM_TEST_DEBUG_INDEX__ABM_TEST_DEBUG_INDEX__SHIFT 0x00000000 30de2bdb3dSTom St Denis #define ABM_TEST_DEBUG_INDEX__ABM_TEST_DEBUG_WRITE_EN_MASK 0x00000100L 31de2bdb3dSTom St Denis #define ABM_TEST_DEBUG_INDEX__ABM_TEST_DEBUG_WRITE_EN__SHIFT 0x00000008 32de2bdb3dSTom St Denis #define AFMT_60958_0__AFMT_60958_CS_A_MASK 0x00000001L 33de2bdb3dSTom St Denis #define AFMT_60958_0__AFMT_60958_CS_A__SHIFT 0x00000000 34de2bdb3dSTom St Denis #define AFMT_60958_0__AFMT_60958_CS_B_MASK 0x00000002L 35de2bdb3dSTom St Denis #define AFMT_60958_0__AFMT_60958_CS_B__SHIFT 0x00000001 36de2bdb3dSTom St Denis #define AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE_MASK 0x0000ff00L 37de2bdb3dSTom St Denis #define AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE__SHIFT 0x00000008 38de2bdb3dSTom St Denis #define AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L_MASK 0x00f00000L 39de2bdb3dSTom St Denis #define AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L__SHIFT 0x00000014 40de2bdb3dSTom St Denis #define AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY_MASK 0x30000000L 41de2bdb3dSTom St Denis #define AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY__SHIFT 0x0000001c 42de2bdb3dSTom St Denis #define AFMT_60958_0__AFMT_60958_CS_C_MASK 0x00000004L 43de2bdb3dSTom St Denis #define AFMT_60958_0__AFMT_60958_CS_C__SHIFT 0x00000002 44de2bdb3dSTom St Denis #define AFMT_60958_0__AFMT_60958_CS_D_MASK 0x00000038L 45de2bdb3dSTom St Denis #define AFMT_60958_0__AFMT_60958_CS_D__SHIFT 0x00000003 46de2bdb3dSTom St Denis #define AFMT_60958_0__AFMT_60958_CS_MODE_MASK 0x000000c0L 47de2bdb3dSTom St Denis #define AFMT_60958_0__AFMT_60958_CS_MODE__SHIFT 0x00000006 48de2bdb3dSTom St Denis #define AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY_MASK 0x0f000000L 49de2bdb3dSTom St Denis #define AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY__SHIFT 0x00000018 50de2bdb3dSTom St Denis #define AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER_MASK 0x000f0000L 51de2bdb3dSTom St Denis #define AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER__SHIFT 0x00000010 52de2bdb3dSTom St Denis #define AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R_MASK 0x00f00000L 53de2bdb3dSTom St Denis #define AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R__SHIFT 0x00000014 54de2bdb3dSTom St Denis #define AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK 0x000000f0L 55de2bdb3dSTom St Denis #define AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT 0x00000004 56de2bdb3dSTom St Denis #define AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH_MASK 0x0000000fL 57de2bdb3dSTom St Denis #define AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH__SHIFT 0x00000000 58de2bdb3dSTom St Denis #define AFMT_60958_1__AFMT_60958_VALID_L_MASK 0x00010000L 59de2bdb3dSTom St Denis #define AFMT_60958_1__AFMT_60958_VALID_L__SHIFT 0x00000010 60de2bdb3dSTom St Denis #define AFMT_60958_1__AFMT_60958_VALID_R_MASK 0x00040000L 61de2bdb3dSTom St Denis #define AFMT_60958_1__AFMT_60958_VALID_R__SHIFT 0x00000012 62de2bdb3dSTom St Denis #define AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2_MASK 0x0000000fL 63de2bdb3dSTom St Denis #define AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2__SHIFT 0x00000000 64de2bdb3dSTom St Denis #define AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3_MASK 0x000000f0L 65de2bdb3dSTom St Denis #define AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3__SHIFT 0x00000004 66de2bdb3dSTom St Denis #define AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4_MASK 0x00000f00L 67de2bdb3dSTom St Denis #define AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4__SHIFT 0x00000008 68de2bdb3dSTom St Denis #define AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5_MASK 0x0000f000L 69de2bdb3dSTom St Denis #define AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5__SHIFT 0x0000000c 70de2bdb3dSTom St Denis #define AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6_MASK 0x000f0000L 71de2bdb3dSTom St Denis #define AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6__SHIFT 0x00000010 72de2bdb3dSTom St Denis #define AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7_MASK 0x00f00000L 73de2bdb3dSTom St Denis #define AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7__SHIFT 0x00000014 74de2bdb3dSTom St Denis #define AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL_MASK 0x0000f000L 75de2bdb3dSTom St Denis #define AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL__SHIFT 0x0000000c 76de2bdb3dSTom St Denis #define AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT_MASK 0x00000010L 77de2bdb3dSTom St Denis #define AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT__SHIFT 0x00000004 78de2bdb3dSTom St Denis #define AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT_MASK 0xffff0000L 79de2bdb3dSTom St Denis #define AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT__SHIFT 0x00000010 80de2bdb3dSTom St Denis #define AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN_MASK 0x00000001L 81de2bdb3dSTom St Denis #define AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN__SHIFT 0x00000000 82de2bdb3dSTom St Denis #define AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE_MASK 0x00000100L 83de2bdb3dSTom St Denis #define AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE__SHIFT 0x00000008 84de2bdb3dSTom St Denis #define AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE_MASK 0x00000001L 85de2bdb3dSTom St Denis #define AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE__SHIFT 0x00000000 86de2bdb3dSTom St Denis #define AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_MASK 0xffffff00L 87de2bdb3dSTom St Denis #define AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC__SHIFT 0x00000008 88de2bdb3dSTom St Denis #define AFMT_AUDIO_DBG_DTO_CNTL__AFMT_AUDIO_DTO_DBG_BASE_MASK 0x00000100L 89de2bdb3dSTom St Denis #define AFMT_AUDIO_DBG_DTO_CNTL__AFMT_AUDIO_DTO_DBG_BASE__SHIFT 0x00000008 90de2bdb3dSTom St Denis #define AFMT_AUDIO_DBG_DTO_CNTL__AFMT_AUDIO_DTO_DBG_DIV_MASK 0x00070000L 91de2bdb3dSTom St Denis #define AFMT_AUDIO_DBG_DTO_CNTL__AFMT_AUDIO_DTO_DBG_DIV__SHIFT 0x00000010 92de2bdb3dSTom St Denis #define AFMT_AUDIO_DBG_DTO_CNTL__AFMT_AUDIO_DTO_DBG_MULTI_MASK 0x00007000L 93de2bdb3dSTom St Denis #define AFMT_AUDIO_DBG_DTO_CNTL__AFMT_AUDIO_DTO_DBG_MULTI__SHIFT 0x0000000c 94de2bdb3dSTom St Denis #define AFMT_AUDIO_DBG_DTO_CNTL__AFMT_AUDIO_DTO_FS_DIV_SEL_MASK 0x00000007L 95de2bdb3dSTom St Denis #define AFMT_AUDIO_DBG_DTO_CNTL__AFMT_AUDIO_DTO_FS_DIV_SEL__SHIFT 0x00000000 96de2bdb3dSTom St Denis #define AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC_MASK 0x00000700L 97de2bdb3dSTom St Denis #define AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC__SHIFT 0x00000008 98de2bdb3dSTom St Denis #define AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_MASK 0x000000ffL 99de2bdb3dSTom St Denis #define AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET_MASK 0x00ff0000L 100de2bdb3dSTom St Denis #define AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET__SHIFT 0x00000010 101de2bdb3dSTom St Denis #define AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM__SHIFT 0x00000000 102de2bdb3dSTom St Denis #define AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT_MASK 0x00007800L 103de2bdb3dSTom St Denis #define AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT__SHIFT 0x0000000b 104de2bdb3dSTom St Denis #define AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT_MASK 0x1f000000L 105de2bdb3dSTom St Denis #define AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT__SHIFT 0x00000018 106de2bdb3dSTom St Denis #define AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA_MASK 0x000000ffL 107de2bdb3dSTom St Denis #define AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA__SHIFT 0x00000000 108de2bdb3dSTom St Denis #define AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH_MASK 0x00008000L 109de2bdb3dSTom St Denis #define AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH__SHIFT 0x0000000f 110de2bdb3dSTom St Denis #define AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL_MASK 0x00030000L 111de2bdb3dSTom St Denis #define AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL__SHIFT 0x00000010 112de2bdb3dSTom St Denis #define AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV_MASK 0x00007800L 113de2bdb3dSTom St Denis #define AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV__SHIFT 0x0000000b 114de2bdb3dSTom St Denis #define AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD_MASK 0x10000000L 115de2bdb3dSTom St Denis #define AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD__SHIFT 0x0000001c 116de2bdb3dSTom St Denis #define AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE_MASK 0x0000ff00L 117de2bdb3dSTom St Denis #define AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE__SHIFT 0x00000008 118de2bdb3dSTom St Denis #define AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD_MASK 0x00000001L 119de2bdb3dSTom St Denis #define AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD__SHIFT 0x00000000 120de2bdb3dSTom St Denis #define AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT_MASK 0x00000002L 121de2bdb3dSTom St Denis #define AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT__SHIFT 0x00000001 122de2bdb3dSTom St Denis #define AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID_MASK 0x00ff0000L 123de2bdb3dSTom St Denis #define AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID__SHIFT 0x00000010 124de2bdb3dSTom St Denis #define AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD_MASK 0x01000000L 125de2bdb3dSTom St Denis #define AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD__SHIFT 0x00000018 126de2bdb3dSTom St Denis #define AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE_MASK 0x04000000L 127de2bdb3dSTom St Denis #define AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE__SHIFT 0x0000001a 128de2bdb3dSTom St Denis #define AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP_MASK 0x01000000L 129de2bdb3dSTom St Denis #define AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP__SHIFT 0x00000018 130de2bdb3dSTom St Denis #define AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK_MASK 0x00800000L 131de2bdb3dSTom St Denis #define AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK__SHIFT 0x00000017 132de2bdb3dSTom St Denis #define AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_MASK 0x00000001L 133de2bdb3dSTom St Denis #define AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND__SHIFT 0x00000000 134de2bdb3dSTom St Denis #define AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN_MASK 0x00001000L 135de2bdb3dSTom St Denis #define AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN__SHIFT 0x0000000c 136de2bdb3dSTom St Denis #define AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE_MASK 0x00004000L 137de2bdb3dSTom St Denis #define AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE__SHIFT 0x0000000e 138de2bdb3dSTom St Denis #define AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK_MASK 0x40000000L 139de2bdb3dSTom St Denis #define AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK__SHIFT 0x0000001e 140de2bdb3dSTom St Denis #define AFMT_AUDIO_PACKET_CONTROL__AFMT_BLANK_TEST_DATA_ON_ENC_ENB_MASK 0x80000000L 141de2bdb3dSTom St Denis #define AFMT_AUDIO_PACKET_CONTROL__AFMT_BLANK_TEST_DATA_ON_ENC_ENB__SHIFT 0x0000001f 142de2bdb3dSTom St Denis #define AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS_MASK 0x00000800L 143de2bdb3dSTom St Denis #define AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS__SHIFT 0x0000000b 144de2bdb3dSTom St Denis #define AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT_MASK 0x00000007L 145de2bdb3dSTom St Denis #define AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT__SHIFT 0x00000000 146de2bdb3dSTom St Denis #define AFMT_AVI_INFO0__AFMT_AVI_INFO_A_MASK 0x00001000L 147de2bdb3dSTom St Denis #define AFMT_AVI_INFO0__AFMT_AVI_INFO_A__SHIFT 0x0000000c 148de2bdb3dSTom St Denis #define AFMT_AVI_INFO0__AFMT_AVI_INFO_B_MASK 0x00000c00L 149de2bdb3dSTom St Denis #define AFMT_AVI_INFO0__AFMT_AVI_INFO_B__SHIFT 0x0000000a 150de2bdb3dSTom St Denis #define AFMT_AVI_INFO0__AFMT_AVI_INFO_CHECKSUM_MASK 0x000000ffL 151de2bdb3dSTom St Denis #define AFMT_AVI_INFO0__AFMT_AVI_INFO_CHECKSUM__SHIFT 0x00000000 152de2bdb3dSTom St Denis #define AFMT_AVI_INFO0__AFMT_AVI_INFO_C_MASK 0x00c00000L 153de2bdb3dSTom St Denis #define AFMT_AVI_INFO0__AFMT_AVI_INFO_C__SHIFT 0x00000016 154de2bdb3dSTom St Denis #define AFMT_AVI_INFO0__AFMT_AVI_INFO_EC_MASK 0x70000000L 155de2bdb3dSTom St Denis #define AFMT_AVI_INFO0__AFMT_AVI_INFO_EC__SHIFT 0x0000001c 156de2bdb3dSTom St Denis #define AFMT_AVI_INFO0__AFMT_AVI_INFO_ITC_MASK 0x80000000L 157de2bdb3dSTom St Denis #define AFMT_AVI_INFO0__AFMT_AVI_INFO_ITC__SHIFT 0x0000001f 158de2bdb3dSTom St Denis #define AFMT_AVI_INFO0__AFMT_AVI_INFO_M_MASK 0x00300000L 159de2bdb3dSTom St Denis #define AFMT_AVI_INFO0__AFMT_AVI_INFO_M__SHIFT 0x00000014 160de2bdb3dSTom St Denis #define AFMT_AVI_INFO0__AFMT_AVI_INFO_PB1_RSVD_MASK 0x00008000L 161de2bdb3dSTom St Denis #define AFMT_AVI_INFO0__AFMT_AVI_INFO_PB1_RSVD__SHIFT 0x0000000f 162de2bdb3dSTom St Denis #define AFMT_AVI_INFO0__AFMT_AVI_INFO_Q_MASK 0x0c000000L 163de2bdb3dSTom St Denis #define AFMT_AVI_INFO0__AFMT_AVI_INFO_Q__SHIFT 0x0000001a 164de2bdb3dSTom St Denis #define AFMT_AVI_INFO0__AFMT_AVI_INFO_R_MASK 0x000f0000L 165de2bdb3dSTom St Denis #define AFMT_AVI_INFO0__AFMT_AVI_INFO_R__SHIFT 0x00000010 166de2bdb3dSTom St Denis #define AFMT_AVI_INFO0__AFMT_AVI_INFO_SC_MASK 0x03000000L 167de2bdb3dSTom St Denis #define AFMT_AVI_INFO0__AFMT_AVI_INFO_SC__SHIFT 0x00000018 168de2bdb3dSTom St Denis #define AFMT_AVI_INFO0__AFMT_AVI_INFO_S_MASK 0x00000300L 169de2bdb3dSTom St Denis #define AFMT_AVI_INFO0__AFMT_AVI_INFO_S__SHIFT 0x00000008 170de2bdb3dSTom St Denis #define AFMT_AVI_INFO0__AFMT_AVI_INFO_Y_MASK 0x00006000L 171de2bdb3dSTom St Denis #define AFMT_AVI_INFO0__AFMT_AVI_INFO_Y__SHIFT 0x0000000d 172de2bdb3dSTom St Denis #define AFMT_AVI_INFO1__AFMT_AVI_INFO_CN_MASK 0x00003000L 173de2bdb3dSTom St Denis #define AFMT_AVI_INFO1__AFMT_AVI_INFO_CN__SHIFT 0x0000000c 174de2bdb3dSTom St Denis #define AFMT_AVI_INFO1__AFMT_AVI_INFO_PB4_RSVD_MASK 0x00000080L 175de2bdb3dSTom St Denis #define AFMT_AVI_INFO1__AFMT_AVI_INFO_PB4_RSVD__SHIFT 0x00000007 176de2bdb3dSTom St Denis #define AFMT_AVI_INFO1__AFMT_AVI_INFO_PR_MASK 0x00000f00L 177de2bdb3dSTom St Denis #define AFMT_AVI_INFO1__AFMT_AVI_INFO_PR__SHIFT 0x00000008 178de2bdb3dSTom St Denis #define AFMT_AVI_INFO1__AFMT_AVI_INFO_TOP_MASK 0xffff0000L 179de2bdb3dSTom St Denis #define AFMT_AVI_INFO1__AFMT_AVI_INFO_TOP__SHIFT 0x00000010 180de2bdb3dSTom St Denis #define AFMT_AVI_INFO1__AFMT_AVI_INFO_VIC_MASK 0x0000007fL 181de2bdb3dSTom St Denis #define AFMT_AVI_INFO1__AFMT_AVI_INFO_VIC__SHIFT 0x00000000 182de2bdb3dSTom St Denis #define AFMT_AVI_INFO1__AFMT_AVI_INFO_YQ_MASK 0x0000c000L 183de2bdb3dSTom St Denis #define AFMT_AVI_INFO1__AFMT_AVI_INFO_YQ__SHIFT 0x0000000e 184de2bdb3dSTom St Denis #define AFMT_AVI_INFO2__AFMT_AVI_INFO_BOTTOM_MASK 0x0000ffffL 185de2bdb3dSTom St Denis #define AFMT_AVI_INFO2__AFMT_AVI_INFO_BOTTOM__SHIFT 0x00000000 186de2bdb3dSTom St Denis #define AFMT_AVI_INFO2__AFMT_AVI_INFO_LEFT_MASK 0xffff0000L 187de2bdb3dSTom St Denis #define AFMT_AVI_INFO2__AFMT_AVI_INFO_LEFT__SHIFT 0x00000010 188de2bdb3dSTom St Denis #define AFMT_AVI_INFO3__AFMT_AVI_INFO_RIGHT_MASK 0x0000ffffL 189de2bdb3dSTom St Denis #define AFMT_AVI_INFO3__AFMT_AVI_INFO_RIGHT__SHIFT 0x00000000 190de2bdb3dSTom St Denis #define AFMT_AVI_INFO3__AFMT_AVI_INFO_VERSION_MASK 0xff000000L 191de2bdb3dSTom St Denis #define AFMT_AVI_INFO3__AFMT_AVI_INFO_VERSION__SHIFT 0x00000018 192de2bdb3dSTom St Denis #define AFMT_GENERIC_0__AFMT_GENERIC_BYTE0_MASK 0x000000ffL 193de2bdb3dSTom St Denis #define AFMT_GENERIC_0__AFMT_GENERIC_BYTE0__SHIFT 0x00000000 194de2bdb3dSTom St Denis #define AFMT_GENERIC_0__AFMT_GENERIC_BYTE1_MASK 0x0000ff00L 195de2bdb3dSTom St Denis #define AFMT_GENERIC_0__AFMT_GENERIC_BYTE1__SHIFT 0x00000008 196de2bdb3dSTom St Denis #define AFMT_GENERIC_0__AFMT_GENERIC_BYTE2_MASK 0x00ff0000L 197de2bdb3dSTom St Denis #define AFMT_GENERIC_0__AFMT_GENERIC_BYTE2__SHIFT 0x00000010 198de2bdb3dSTom St Denis #define AFMT_GENERIC_0__AFMT_GENERIC_BYTE3_MASK 0xff000000L 199de2bdb3dSTom St Denis #define AFMT_GENERIC_0__AFMT_GENERIC_BYTE3__SHIFT 0x00000018 200de2bdb3dSTom St Denis #define AFMT_GENERIC_1__AFMT_GENERIC_BYTE4_MASK 0x000000ffL 201de2bdb3dSTom St Denis #define AFMT_GENERIC_1__AFMT_GENERIC_BYTE4__SHIFT 0x00000000 202de2bdb3dSTom St Denis #define AFMT_GENERIC_1__AFMT_GENERIC_BYTE5_MASK 0x0000ff00L 203de2bdb3dSTom St Denis #define AFMT_GENERIC_1__AFMT_GENERIC_BYTE5__SHIFT 0x00000008 204de2bdb3dSTom St Denis #define AFMT_GENERIC_1__AFMT_GENERIC_BYTE6_MASK 0x00ff0000L 205de2bdb3dSTom St Denis #define AFMT_GENERIC_1__AFMT_GENERIC_BYTE6__SHIFT 0x00000010 206de2bdb3dSTom St Denis #define AFMT_GENERIC_1__AFMT_GENERIC_BYTE7_MASK 0xff000000L 207de2bdb3dSTom St Denis #define AFMT_GENERIC_1__AFMT_GENERIC_BYTE7__SHIFT 0x00000018 208de2bdb3dSTom St Denis #define AFMT_GENERIC_2__AFMT_GENERIC_BYTE10_MASK 0x00ff0000L 209de2bdb3dSTom St Denis #define AFMT_GENERIC_2__AFMT_GENERIC_BYTE10__SHIFT 0x00000010 210de2bdb3dSTom St Denis #define AFMT_GENERIC_2__AFMT_GENERIC_BYTE11_MASK 0xff000000L 211de2bdb3dSTom St Denis #define AFMT_GENERIC_2__AFMT_GENERIC_BYTE11__SHIFT 0x00000018 212de2bdb3dSTom St Denis #define AFMT_GENERIC_2__AFMT_GENERIC_BYTE8_MASK 0x000000ffL 213de2bdb3dSTom St Denis #define AFMT_GENERIC_2__AFMT_GENERIC_BYTE8__SHIFT 0x00000000 214de2bdb3dSTom St Denis #define AFMT_GENERIC_2__AFMT_GENERIC_BYTE9_MASK 0x0000ff00L 215de2bdb3dSTom St Denis #define AFMT_GENERIC_2__AFMT_GENERIC_BYTE9__SHIFT 0x00000008 216de2bdb3dSTom St Denis #define AFMT_GENERIC_3__AFMT_GENERIC_BYTE12_MASK 0x000000ffL 217de2bdb3dSTom St Denis #define AFMT_GENERIC_3__AFMT_GENERIC_BYTE12__SHIFT 0x00000000 218de2bdb3dSTom St Denis #define AFMT_GENERIC_3__AFMT_GENERIC_BYTE13_MASK 0x0000ff00L 219de2bdb3dSTom St Denis #define AFMT_GENERIC_3__AFMT_GENERIC_BYTE13__SHIFT 0x00000008 220de2bdb3dSTom St Denis #define AFMT_GENERIC_3__AFMT_GENERIC_BYTE14_MASK 0x00ff0000L 221de2bdb3dSTom St Denis #define AFMT_GENERIC_3__AFMT_GENERIC_BYTE14__SHIFT 0x00000010 222de2bdb3dSTom St Denis #define AFMT_GENERIC_3__AFMT_GENERIC_BYTE15_MASK 0xff000000L 223de2bdb3dSTom St Denis #define AFMT_GENERIC_3__AFMT_GENERIC_BYTE15__SHIFT 0x00000018 224de2bdb3dSTom St Denis #define AFMT_GENERIC_4__AFMT_GENERIC_BYTE16_MASK 0x000000ffL 225de2bdb3dSTom St Denis #define AFMT_GENERIC_4__AFMT_GENERIC_BYTE16__SHIFT 0x00000000 226de2bdb3dSTom St Denis #define AFMT_GENERIC_4__AFMT_GENERIC_BYTE17_MASK 0x0000ff00L 227de2bdb3dSTom St Denis #define AFMT_GENERIC_4__AFMT_GENERIC_BYTE17__SHIFT 0x00000008 228de2bdb3dSTom St Denis #define AFMT_GENERIC_4__AFMT_GENERIC_BYTE18_MASK 0x00ff0000L 229de2bdb3dSTom St Denis #define AFMT_GENERIC_4__AFMT_GENERIC_BYTE18__SHIFT 0x00000010 230de2bdb3dSTom St Denis #define AFMT_GENERIC_4__AFMT_GENERIC_BYTE19_MASK 0xff000000L 231de2bdb3dSTom St Denis #define AFMT_GENERIC_4__AFMT_GENERIC_BYTE19__SHIFT 0x00000018 232de2bdb3dSTom St Denis #define AFMT_GENERIC_5__AFMT_GENERIC_BYTE20_MASK 0x000000ffL 233de2bdb3dSTom St Denis #define AFMT_GENERIC_5__AFMT_GENERIC_BYTE20__SHIFT 0x00000000 234de2bdb3dSTom St Denis #define AFMT_GENERIC_5__AFMT_GENERIC_BYTE21_MASK 0x0000ff00L 235de2bdb3dSTom St Denis #define AFMT_GENERIC_5__AFMT_GENERIC_BYTE21__SHIFT 0x00000008 236de2bdb3dSTom St Denis #define AFMT_GENERIC_5__AFMT_GENERIC_BYTE22_MASK 0x00ff0000L 237de2bdb3dSTom St Denis #define AFMT_GENERIC_5__AFMT_GENERIC_BYTE22__SHIFT 0x00000010 238de2bdb3dSTom St Denis #define AFMT_GENERIC_5__AFMT_GENERIC_BYTE23_MASK 0xff000000L 239de2bdb3dSTom St Denis #define AFMT_GENERIC_5__AFMT_GENERIC_BYTE23__SHIFT 0x00000018 240de2bdb3dSTom St Denis #define AFMT_GENERIC_6__AFMT_GENERIC_BYTE24_MASK 0x000000ffL 241de2bdb3dSTom St Denis #define AFMT_GENERIC_6__AFMT_GENERIC_BYTE24__SHIFT 0x00000000 242de2bdb3dSTom St Denis #define AFMT_GENERIC_6__AFMT_GENERIC_BYTE25_MASK 0x0000ff00L 243de2bdb3dSTom St Denis #define AFMT_GENERIC_6__AFMT_GENERIC_BYTE25__SHIFT 0x00000008 244de2bdb3dSTom St Denis #define AFMT_GENERIC_6__AFMT_GENERIC_BYTE26_MASK 0x00ff0000L 245de2bdb3dSTom St Denis #define AFMT_GENERIC_6__AFMT_GENERIC_BYTE26__SHIFT 0x00000010 246de2bdb3dSTom St Denis #define AFMT_GENERIC_6__AFMT_GENERIC_BYTE27_MASK 0xff000000L 247de2bdb3dSTom St Denis #define AFMT_GENERIC_6__AFMT_GENERIC_BYTE27__SHIFT 0x00000018 248de2bdb3dSTom St Denis #define AFMT_GENERIC_7__AFMT_GENERIC_BYTE28_MASK 0x000000ffL 249de2bdb3dSTom St Denis #define AFMT_GENERIC_7__AFMT_GENERIC_BYTE28__SHIFT 0x00000000 250de2bdb3dSTom St Denis #define AFMT_GENERIC_7__AFMT_GENERIC_BYTE29_MASK 0x0000ff00L 251de2bdb3dSTom St Denis #define AFMT_GENERIC_7__AFMT_GENERIC_BYTE29__SHIFT 0x00000008 252de2bdb3dSTom St Denis #define AFMT_GENERIC_7__AFMT_GENERIC_BYTE30_MASK 0x00ff0000L 253de2bdb3dSTom St Denis #define AFMT_GENERIC_7__AFMT_GENERIC_BYTE30__SHIFT 0x00000010 254de2bdb3dSTom St Denis #define AFMT_GENERIC_7__AFMT_GENERIC_BYTE31_MASK 0xff000000L 255de2bdb3dSTom St Denis #define AFMT_GENERIC_7__AFMT_GENERIC_BYTE31__SHIFT 0x00000018 256de2bdb3dSTom St Denis #define AFMT_GENERIC_HDR__AFMT_GENERIC_HB0_MASK 0x000000ffL 257de2bdb3dSTom St Denis #define AFMT_GENERIC_HDR__AFMT_GENERIC_HB0__SHIFT 0x00000000 258de2bdb3dSTom St Denis #define AFMT_GENERIC_HDR__AFMT_GENERIC_HB1_MASK 0x0000ff00L 259de2bdb3dSTom St Denis #define AFMT_GENERIC_HDR__AFMT_GENERIC_HB1__SHIFT 0x00000008 260de2bdb3dSTom St Denis #define AFMT_GENERIC_HDR__AFMT_GENERIC_HB2_MASK 0x00ff0000L 261de2bdb3dSTom St Denis #define AFMT_GENERIC_HDR__AFMT_GENERIC_HB2__SHIFT 0x00000010 262de2bdb3dSTom St Denis #define AFMT_GENERIC_HDR__AFMT_GENERIC_HB3_MASK 0xff000000L 263de2bdb3dSTom St Denis #define AFMT_GENERIC_HDR__AFMT_GENERIC_HB3__SHIFT 0x00000018 264de2bdb3dSTom St Denis #define AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE_MASK 0x00000040L 265de2bdb3dSTom St Denis #define AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE__SHIFT 0x00000006 266de2bdb3dSTom St Denis #define AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE_MASK 0x00000080L 267de2bdb3dSTom St Denis #define AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE__SHIFT 0x00000007 268de2bdb3dSTom St Denis #define AFMT_INFOFRAME_CONTROL0__AFMT_MPEG_INFO_UPDATE_MASK 0x00000400L 269de2bdb3dSTom St Denis #define AFMT_INFOFRAME_CONTROL0__AFMT_MPEG_INFO_UPDATE__SHIFT 0x0000000a 270de2bdb3dSTom St Denis #define AFMT_ISRC1_0__AFMT_ISRC_CONTINUE_MASK 0x00000040L 271de2bdb3dSTom St Denis #define AFMT_ISRC1_0__AFMT_ISRC_CONTINUE__SHIFT 0x00000006 272de2bdb3dSTom St Denis #define AFMT_ISRC1_0__AFMT_ISRC_STATUS_MASK 0x00000007L 273de2bdb3dSTom St Denis #define AFMT_ISRC1_0__AFMT_ISRC_STATUS__SHIFT 0x00000000 274de2bdb3dSTom St Denis #define AFMT_ISRC1_0__AFMT_ISRC_VALID_MASK 0x00000080L 275de2bdb3dSTom St Denis #define AFMT_ISRC1_0__AFMT_ISRC_VALID__SHIFT 0x00000007 276de2bdb3dSTom St Denis #define AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC0_MASK 0x000000ffL 277de2bdb3dSTom St Denis #define AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC0__SHIFT 0x00000000 278de2bdb3dSTom St Denis #define AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC1_MASK 0x0000ff00L 279de2bdb3dSTom St Denis #define AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC1__SHIFT 0x00000008 280de2bdb3dSTom St Denis #define AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC2_MASK 0x00ff0000L 281de2bdb3dSTom St Denis #define AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC2__SHIFT 0x00000010 282de2bdb3dSTom St Denis #define AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC3_MASK 0xff000000L 283de2bdb3dSTom St Denis #define AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC3__SHIFT 0x00000018 284de2bdb3dSTom St Denis #define AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC4_MASK 0x000000ffL 285de2bdb3dSTom St Denis #define AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC4__SHIFT 0x00000000 286de2bdb3dSTom St Denis #define AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC5_MASK 0x0000ff00L 287de2bdb3dSTom St Denis #define AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC5__SHIFT 0x00000008 288de2bdb3dSTom St Denis #define AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC6_MASK 0x00ff0000L 289de2bdb3dSTom St Denis #define AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC6__SHIFT 0x00000010 290de2bdb3dSTom St Denis #define AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC7_MASK 0xff000000L 291de2bdb3dSTom St Denis #define AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC7__SHIFT 0x00000018 292de2bdb3dSTom St Denis #define AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC10_MASK 0x00ff0000L 293de2bdb3dSTom St Denis #define AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC10__SHIFT 0x00000010 294de2bdb3dSTom St Denis #define AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC11_MASK 0xff000000L 295de2bdb3dSTom St Denis #define AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC11__SHIFT 0x00000018 296de2bdb3dSTom St Denis #define AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC8_MASK 0x000000ffL 297de2bdb3dSTom St Denis #define AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC8__SHIFT 0x00000000 298de2bdb3dSTom St Denis #define AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC9_MASK 0x0000ff00L 299de2bdb3dSTom St Denis #define AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC9__SHIFT 0x00000008 300de2bdb3dSTom St Denis #define AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC12_MASK 0x000000ffL 301de2bdb3dSTom St Denis #define AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC12__SHIFT 0x00000000 302de2bdb3dSTom St Denis #define AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC13_MASK 0x0000ff00L 303de2bdb3dSTom St Denis #define AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC13__SHIFT 0x00000008 304de2bdb3dSTom St Denis #define AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC14_MASK 0x00ff0000L 305de2bdb3dSTom St Denis #define AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC14__SHIFT 0x00000010 306de2bdb3dSTom St Denis #define AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC15_MASK 0xff000000L 307de2bdb3dSTom St Denis #define AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC15__SHIFT 0x00000018 308de2bdb3dSTom St Denis #define AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC16_MASK 0x000000ffL 309de2bdb3dSTom St Denis #define AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC16__SHIFT 0x00000000 310de2bdb3dSTom St Denis #define AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC17_MASK 0x0000ff00L 311de2bdb3dSTom St Denis #define AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC17__SHIFT 0x00000008 312de2bdb3dSTom St Denis #define AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC18_MASK 0x00ff0000L 313de2bdb3dSTom St Denis #define AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC18__SHIFT 0x00000010 314de2bdb3dSTom St Denis #define AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC19_MASK 0xff000000L 315de2bdb3dSTom St Denis #define AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC19__SHIFT 0x00000018 316de2bdb3dSTom St Denis #define AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC20_MASK 0x000000ffL 317de2bdb3dSTom St Denis #define AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC20__SHIFT 0x00000000 318de2bdb3dSTom St Denis #define AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC21_MASK 0x0000ff00L 319de2bdb3dSTom St Denis #define AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC21__SHIFT 0x00000008 320de2bdb3dSTom St Denis #define AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC22_MASK 0x00ff0000L 321de2bdb3dSTom St Denis #define AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC22__SHIFT 0x00000010 322de2bdb3dSTom St Denis #define AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC23_MASK 0xff000000L 323de2bdb3dSTom St Denis #define AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC23__SHIFT 0x00000018 324de2bdb3dSTom St Denis #define AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC24_MASK 0x000000ffL 325de2bdb3dSTom St Denis #define AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC24__SHIFT 0x00000000 326de2bdb3dSTom St Denis #define AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC25_MASK 0x0000ff00L 327de2bdb3dSTom St Denis #define AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC25__SHIFT 0x00000008 328de2bdb3dSTom St Denis #define AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC26_MASK 0x00ff0000L 329de2bdb3dSTom St Denis #define AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC26__SHIFT 0x00000010 330de2bdb3dSTom St Denis #define AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC27_MASK 0xff000000L 331de2bdb3dSTom St Denis #define AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC27__SHIFT 0x00000018 332de2bdb3dSTom St Denis #define AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC28_MASK 0x000000ffL 333de2bdb3dSTom St Denis #define AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC28__SHIFT 0x00000000 334de2bdb3dSTom St Denis #define AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC29_MASK 0x0000ff00L 335de2bdb3dSTom St Denis #define AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC29__SHIFT 0x00000008 336de2bdb3dSTom St Denis #define AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC30_MASK 0x00ff0000L 337de2bdb3dSTom St Denis #define AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC30__SHIFT 0x00000010 338de2bdb3dSTom St Denis #define AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC31_MASK 0xff000000L 339de2bdb3dSTom St Denis #define AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC31__SHIFT 0x00000018 340de2bdb3dSTom St Denis #define AFMT_MPEG_INFO0__AFMT_MPEG_INFO_CHECKSUM_MASK 0x000000ffL 341de2bdb3dSTom St Denis #define AFMT_MPEG_INFO0__AFMT_MPEG_INFO_CHECKSUM__SHIFT 0x00000000 342de2bdb3dSTom St Denis #define AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB0_MASK 0x0000ff00L 343de2bdb3dSTom St Denis #define AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB0__SHIFT 0x00000008 344de2bdb3dSTom St Denis #define AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB1_MASK 0x00ff0000L 345de2bdb3dSTom St Denis #define AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB1__SHIFT 0x00000010 346de2bdb3dSTom St Denis #define AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB2_MASK 0xff000000L 347de2bdb3dSTom St Denis #define AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB2__SHIFT 0x00000018 348de2bdb3dSTom St Denis #define AFMT_MPEG_INFO1__AFMT_MPEG_INFO_FR_MASK 0x00001000L 349de2bdb3dSTom St Denis #define AFMT_MPEG_INFO1__AFMT_MPEG_INFO_FR__SHIFT 0x0000000c 350de2bdb3dSTom St Denis #define AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MB3_MASK 0x000000ffL 351de2bdb3dSTom St Denis #define AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MB3__SHIFT 0x00000000 352de2bdb3dSTom St Denis #define AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MF_MASK 0x00000300L 353de2bdb3dSTom St Denis #define AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MF__SHIFT 0x00000008 354de2bdb3dSTom St Denis #define AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN_MASK 0x80000000L 355de2bdb3dSTom St Denis #define AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN__SHIFT 0x0000001f 356de2bdb3dSTom St Denis #define AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT_MASK 0x00ffffffL 357de2bdb3dSTom St Denis #define AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT__SHIFT 0x00000000 358de2bdb3dSTom St Denis #define AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE_MASK 0xff000000L 359de2bdb3dSTom St Denis #define AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE__SHIFT 0x00000018 360de2bdb3dSTom St Denis #define AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT_MASK 0x00ffffffL 361de2bdb3dSTom St Denis #define AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT__SHIFT 0x00000000 362de2bdb3dSTom St Denis #define AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT_MASK 0x00ffffffL 363de2bdb3dSTom St Denis #define AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT__SHIFT 0x00000000 364de2bdb3dSTom St Denis #define AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT_MASK 0x00ffffffL 365de2bdb3dSTom St Denis #define AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT__SHIFT 0x00000000 366de2bdb3dSTom St Denis #define AFMT_STATUS__AFMT_AUDIO_ENABLE_MASK 0x00000010L 367de2bdb3dSTom St Denis #define AFMT_STATUS__AFMT_AUDIO_ENABLE__SHIFT 0x00000004 368de2bdb3dSTom St Denis #define AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW_MASK 0x01000000L 369de2bdb3dSTom St Denis #define AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW__SHIFT 0x00000018 370de2bdb3dSTom St Denis #define AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG_MASK 0x40000000L 371de2bdb3dSTom St Denis #define AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG__SHIFT 0x0000001e 372de2bdb3dSTom St Denis #define AFMT_STATUS__AFMT_AZ_HBR_ENABLE_MASK 0x00000100L 373de2bdb3dSTom St Denis #define AFMT_STATUS__AFMT_AZ_HBR_ENABLE__SHIFT 0x00000008 374de2bdb3dSTom St Denis #define AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC0_UPDATE_MASK 0x00000004L 375de2bdb3dSTom St Denis #define AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC0_UPDATE__SHIFT 0x00000002 376de2bdb3dSTom St Denis #define AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC2_UPDATE_MASK 0x00000008L 377de2bdb3dSTom St Denis #define AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC2_UPDATE__SHIFT 0x00000003 378de2bdb3dSTom St Denis #define AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_INDEX_MASK 0xc0000000L 379de2bdb3dSTom St Denis #define AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_INDEX__SHIFT 0x0000001e 380de2bdb3dSTom St Denis #define ATTR00__ATTR_PAL_MASK 0x0000003fL 381de2bdb3dSTom St Denis #define ATTR00__ATTR_PAL__SHIFT 0x00000000 382de2bdb3dSTom St Denis #define ATTR01__ATTR_PAL_MASK 0x0000003fL 383de2bdb3dSTom St Denis #define ATTR01__ATTR_PAL__SHIFT 0x00000000 384de2bdb3dSTom St Denis #define ATTR02__ATTR_PAL_MASK 0x0000003fL 385de2bdb3dSTom St Denis #define ATTR02__ATTR_PAL__SHIFT 0x00000000 386de2bdb3dSTom St Denis #define ATTR03__ATTR_PAL_MASK 0x0000003fL 387de2bdb3dSTom St Denis #define ATTR03__ATTR_PAL__SHIFT 0x00000000 388de2bdb3dSTom St Denis #define ATTR04__ATTR_PAL_MASK 0x0000003fL 389de2bdb3dSTom St Denis #define ATTR04__ATTR_PAL__SHIFT 0x00000000 390de2bdb3dSTom St Denis #define ATTR05__ATTR_PAL_MASK 0x0000003fL 391de2bdb3dSTom St Denis #define ATTR05__ATTR_PAL__SHIFT 0x00000000 392de2bdb3dSTom St Denis #define ATTR06__ATTR_PAL_MASK 0x0000003fL 393de2bdb3dSTom St Denis #define ATTR06__ATTR_PAL__SHIFT 0x00000000 394de2bdb3dSTom St Denis #define ATTR07__ATTR_PAL_MASK 0x0000003fL 395de2bdb3dSTom St Denis #define ATTR07__ATTR_PAL__SHIFT 0x00000000 396de2bdb3dSTom St Denis #define ATTR08__ATTR_PAL_MASK 0x0000003fL 397de2bdb3dSTom St Denis #define ATTR08__ATTR_PAL__SHIFT 0x00000000 398de2bdb3dSTom St Denis #define ATTR09__ATTR_PAL_MASK 0x0000003fL 399de2bdb3dSTom St Denis #define ATTR09__ATTR_PAL__SHIFT 0x00000000 400de2bdb3dSTom St Denis #define ATTR0A__ATTR_PAL_MASK 0x0000003fL 401de2bdb3dSTom St Denis #define ATTR0A__ATTR_PAL__SHIFT 0x00000000 402de2bdb3dSTom St Denis #define ATTR0B__ATTR_PAL_MASK 0x0000003fL 403de2bdb3dSTom St Denis #define ATTR0B__ATTR_PAL__SHIFT 0x00000000 404de2bdb3dSTom St Denis #define ATTR0C__ATTR_PAL_MASK 0x0000003fL 405de2bdb3dSTom St Denis #define ATTR0C__ATTR_PAL__SHIFT 0x00000000 406de2bdb3dSTom St Denis #define ATTR0D__ATTR_PAL_MASK 0x0000003fL 407de2bdb3dSTom St Denis #define ATTR0D__ATTR_PAL__SHIFT 0x00000000 408de2bdb3dSTom St Denis #define ATTR0E__ATTR_PAL_MASK 0x0000003fL 409de2bdb3dSTom St Denis #define ATTR0E__ATTR_PAL__SHIFT 0x00000000 410de2bdb3dSTom St Denis #define ATTR0F__ATTR_PAL_MASK 0x0000003fL 411de2bdb3dSTom St Denis #define ATTR0F__ATTR_PAL__SHIFT 0x00000000 412de2bdb3dSTom St Denis #define ATTR10__ATTR_BLINK_EN_MASK 0x00000008L 413de2bdb3dSTom St Denis #define ATTR10__ATTR_BLINK_EN__SHIFT 0x00000003 414de2bdb3dSTom St Denis #define ATTR10__ATTR_CSEL_EN_MASK 0x00000080L 415de2bdb3dSTom St Denis #define ATTR10__ATTR_CSEL_EN__SHIFT 0x00000007 416de2bdb3dSTom St Denis #define ATTR10__ATTR_GRPH_MODE_MASK 0x00000001L 417de2bdb3dSTom St Denis #define ATTR10__ATTR_GRPH_MODE__SHIFT 0x00000000 418de2bdb3dSTom St Denis #define ATTR10__ATTR_LGRPH_EN_MASK 0x00000004L 419de2bdb3dSTom St Denis #define ATTR10__ATTR_LGRPH_EN__SHIFT 0x00000002 420de2bdb3dSTom St Denis #define ATTR10__ATTR_MONO_EN_MASK 0x00000002L 421de2bdb3dSTom St Denis #define ATTR10__ATTR_MONO_EN__SHIFT 0x00000001 422de2bdb3dSTom St Denis #define ATTR10__ATTR_PANTOPONLY_MASK 0x00000020L 423de2bdb3dSTom St Denis #define ATTR10__ATTR_PANTOPONLY__SHIFT 0x00000005 424de2bdb3dSTom St Denis #define ATTR10__ATTR_PCLKBY2_MASK 0x00000040L 425de2bdb3dSTom St Denis #define ATTR10__ATTR_PCLKBY2__SHIFT 0x00000006 426de2bdb3dSTom St Denis #define ATTR11__ATTR_OVSC_MASK 0x000000ffL 427de2bdb3dSTom St Denis #define ATTR11__ATTR_OVSC__SHIFT 0x00000000 428de2bdb3dSTom St Denis #define ATTR12__ATTR_MAP_EN_MASK 0x0000000fL 429de2bdb3dSTom St Denis #define ATTR12__ATTR_MAP_EN__SHIFT 0x00000000 430de2bdb3dSTom St Denis #define ATTR12__ATTR_VSMUX_MASK 0x00000030L 431de2bdb3dSTom St Denis #define ATTR12__ATTR_VSMUX__SHIFT 0x00000004 432de2bdb3dSTom St Denis #define ATTR13__ATTR_PPAN_MASK 0x0000000fL 433de2bdb3dSTom St Denis #define ATTR13__ATTR_PPAN__SHIFT 0x00000000 434de2bdb3dSTom St Denis #define ATTR14__ATTR_CSEL1_MASK 0x00000003L 435de2bdb3dSTom St Denis #define ATTR14__ATTR_CSEL1__SHIFT 0x00000000 436de2bdb3dSTom St Denis #define ATTR14__ATTR_CSEL2_MASK 0x0000000cL 437de2bdb3dSTom St Denis #define ATTR14__ATTR_CSEL2__SHIFT 0x00000002 438de2bdb3dSTom St Denis #define ATTRDR__ATTR_DATA_MASK 0x000000ffL 439de2bdb3dSTom St Denis #define ATTRDR__ATTR_DATA__SHIFT 0x00000000 440de2bdb3dSTom St Denis #define ATTRDW__ATTR_DATA_MASK 0x000000ffL 441de2bdb3dSTom St Denis #define ATTRDW__ATTR_DATA__SHIFT 0x00000000 442de2bdb3dSTom St Denis #define ATTRX__ATTR_IDX_MASK 0x0000001fL 443de2bdb3dSTom St Denis #define ATTRX__ATTR_IDX__SHIFT 0x00000000 444de2bdb3dSTom St Denis #define ATTRX__ATTR_PAL_RW_ENB_MASK 0x00000020L 445de2bdb3dSTom St Denis #define ATTRX__ATTR_PAL_RW_ENB__SHIFT 0x00000005 446de2bdb3dSTom St Denis #define AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2_MASK 0x00ff0000L 447de2bdb3dSTom St Denis #define AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT 0x00000010 448de2bdb3dSTom St Denis #define AUDIO_DESCRIPTOR0__MAX_CHANNELS_MASK 0x00000007L 449de2bdb3dSTom St Denis #define AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT 0x00000000 450de2bdb3dSTom St Denis #define AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_MASK 0x0000ff00L 451de2bdb3dSTom St Denis #define AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT 0x00000008 452de2bdb3dSTom St Denis #define AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000L 453de2bdb3dSTom St Denis #define AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x00000018 454de2bdb3dSTom St Denis #define AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2_MASK 0x00ff0000L 455de2bdb3dSTom St Denis #define AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2__SHIFT 0x00000010 456de2bdb3dSTom St Denis #define AUDIO_DESCRIPTOR10__MAX_CHANNELS_MASK 0x00000007L 457de2bdb3dSTom St Denis #define AUDIO_DESCRIPTOR10__MAX_CHANNELS__SHIFT 0x00000000 458de2bdb3dSTom St Denis #define AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_MASK 0x0000ff00L 459de2bdb3dSTom St Denis #define AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES__SHIFT 0x00000008 460de2bdb3dSTom St Denis #define AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000L 461de2bdb3dSTom St Denis #define AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x00000018 462de2bdb3dSTom St Denis #define AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2_MASK 0x00ff0000L 463de2bdb3dSTom St Denis #define AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2__SHIFT 0x00000010 464de2bdb3dSTom St Denis #define AUDIO_DESCRIPTOR11__MAX_CHANNELS_MASK 0x00000007L 465de2bdb3dSTom St Denis #define AUDIO_DESCRIPTOR11__MAX_CHANNELS__SHIFT 0x00000000 466de2bdb3dSTom St Denis #define AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_MASK 0x0000ff00L 467de2bdb3dSTom St Denis #define AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES__SHIFT 0x00000008 468de2bdb3dSTom St Denis #define AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000L 469de2bdb3dSTom St Denis #define AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x00000018 470de2bdb3dSTom St Denis #define AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2_MASK 0x00ff0000L 471de2bdb3dSTom St Denis #define AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2__SHIFT 0x00000010 472de2bdb3dSTom St Denis #define AUDIO_DESCRIPTOR12__MAX_CHANNELS_MASK 0x00000007L 473de2bdb3dSTom St Denis #define AUDIO_DESCRIPTOR12__MAX_CHANNELS__SHIFT 0x00000000 474de2bdb3dSTom St Denis #define AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_MASK 0x0000ff00L 475de2bdb3dSTom St Denis #define AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES__SHIFT 0x00000008 476de2bdb3dSTom St Denis #define AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000L 477de2bdb3dSTom St Denis #define AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x00000018 478de2bdb3dSTom St Denis #define AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2_MASK 0x00ff0000L 479de2bdb3dSTom St Denis #define AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2__SHIFT 0x00000010 480de2bdb3dSTom St Denis #define AUDIO_DESCRIPTOR13__MAX_CHANNELS_MASK 0x00000007L 481de2bdb3dSTom St Denis #define AUDIO_DESCRIPTOR13__MAX_CHANNELS__SHIFT 0x00000000 482de2bdb3dSTom St Denis #define AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_MASK 0x0000ff00L 483de2bdb3dSTom St Denis #define AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES__SHIFT 0x00000008 484de2bdb3dSTom St Denis #define AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000L 485de2bdb3dSTom St Denis #define AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x00000018 486de2bdb3dSTom St Denis #define AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2_MASK 0x00ff0000L 487de2bdb3dSTom St Denis #define AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2__SHIFT 0x00000010 488de2bdb3dSTom St Denis #define AUDIO_DESCRIPTOR1__MAX_CHANNELS_MASK 0x00000007L 489de2bdb3dSTom St Denis #define AUDIO_DESCRIPTOR1__MAX_CHANNELS__SHIFT 0x00000000 490de2bdb3dSTom St Denis #define AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_MASK 0x0000ff00L 491de2bdb3dSTom St Denis #define AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES__SHIFT 0x00000008 492de2bdb3dSTom St Denis #define AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000L 493de2bdb3dSTom St Denis #define AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x00000018 494de2bdb3dSTom St Denis #define AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2_MASK 0x00ff0000L 495de2bdb3dSTom St Denis #define AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2__SHIFT 0x00000010 496de2bdb3dSTom St Denis #define AUDIO_DESCRIPTOR2__MAX_CHANNELS_MASK 0x00000007L 497de2bdb3dSTom St Denis #define AUDIO_DESCRIPTOR2__MAX_CHANNELS__SHIFT 0x00000000 498de2bdb3dSTom St Denis #define AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_MASK 0x0000ff00L 499de2bdb3dSTom St Denis #define AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES__SHIFT 0x00000008 500de2bdb3dSTom St Denis #define AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000L 501de2bdb3dSTom St Denis #define AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x00000018 502de2bdb3dSTom St Denis #define AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2_MASK 0x00ff0000L 503de2bdb3dSTom St Denis #define AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2__SHIFT 0x00000010 504de2bdb3dSTom St Denis #define AUDIO_DESCRIPTOR3__MAX_CHANNELS_MASK 0x00000007L 505de2bdb3dSTom St Denis #define AUDIO_DESCRIPTOR3__MAX_CHANNELS__SHIFT 0x00000000 506de2bdb3dSTom St Denis #define AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_MASK 0x0000ff00L 507de2bdb3dSTom St Denis #define AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES__SHIFT 0x00000008 508de2bdb3dSTom St Denis #define AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000L 509de2bdb3dSTom St Denis #define AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x00000018 510de2bdb3dSTom St Denis #define AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2_MASK 0x00ff0000L 511de2bdb3dSTom St Denis #define AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2__SHIFT 0x00000010 512de2bdb3dSTom St Denis #define AUDIO_DESCRIPTOR4__MAX_CHANNELS_MASK 0x00000007L 513de2bdb3dSTom St Denis #define AUDIO_DESCRIPTOR4__MAX_CHANNELS__SHIFT 0x00000000 514de2bdb3dSTom St Denis #define AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_MASK 0x0000ff00L 515de2bdb3dSTom St Denis #define AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES__SHIFT 0x00000008 516de2bdb3dSTom St Denis #define AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000L 517de2bdb3dSTom St Denis #define AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x00000018 518de2bdb3dSTom St Denis #define AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2_MASK 0x00ff0000L 519de2bdb3dSTom St Denis #define AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2__SHIFT 0x00000010 520de2bdb3dSTom St Denis #define AUDIO_DESCRIPTOR5__MAX_CHANNELS_MASK 0x00000007L 521de2bdb3dSTom St Denis #define AUDIO_DESCRIPTOR5__MAX_CHANNELS__SHIFT 0x00000000 522de2bdb3dSTom St Denis #define AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_MASK 0x0000ff00L 523de2bdb3dSTom St Denis #define AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES__SHIFT 0x00000008 524de2bdb3dSTom St Denis #define AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000L 525de2bdb3dSTom St Denis #define AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x00000018 526de2bdb3dSTom St Denis #define AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2_MASK 0x00ff0000L 527de2bdb3dSTom St Denis #define AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2__SHIFT 0x00000010 528de2bdb3dSTom St Denis #define AUDIO_DESCRIPTOR6__MAX_CHANNELS_MASK 0x00000007L 529de2bdb3dSTom St Denis #define AUDIO_DESCRIPTOR6__MAX_CHANNELS__SHIFT 0x00000000 530de2bdb3dSTom St Denis #define AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_MASK 0x0000ff00L 531de2bdb3dSTom St Denis #define AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES__SHIFT 0x00000008 532de2bdb3dSTom St Denis #define AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000L 533de2bdb3dSTom St Denis #define AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x00000018 534de2bdb3dSTom St Denis #define AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2_MASK 0x00ff0000L 535de2bdb3dSTom St Denis #define AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2__SHIFT 0x00000010 536de2bdb3dSTom St Denis #define AUDIO_DESCRIPTOR7__MAX_CHANNELS_MASK 0x00000007L 537de2bdb3dSTom St Denis #define AUDIO_DESCRIPTOR7__MAX_CHANNELS__SHIFT 0x00000000 538de2bdb3dSTom St Denis #define AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_MASK 0x0000ff00L 539de2bdb3dSTom St Denis #define AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES__SHIFT 0x00000008 540de2bdb3dSTom St Denis #define AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000L 541de2bdb3dSTom St Denis #define AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x00000018 542de2bdb3dSTom St Denis #define AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2_MASK 0x00ff0000L 543de2bdb3dSTom St Denis #define AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2__SHIFT 0x00000010 544de2bdb3dSTom St Denis #define AUDIO_DESCRIPTOR8__MAX_CHANNELS_MASK 0x00000007L 545de2bdb3dSTom St Denis #define AUDIO_DESCRIPTOR8__MAX_CHANNELS__SHIFT 0x00000000 546de2bdb3dSTom St Denis #define AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_MASK 0x0000ff00L 547de2bdb3dSTom St Denis #define AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES__SHIFT 0x00000008 548de2bdb3dSTom St Denis #define AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000L 549de2bdb3dSTom St Denis #define AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x00000018 550de2bdb3dSTom St Denis #define AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2_MASK 0x00ff0000L 551de2bdb3dSTom St Denis #define AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2__SHIFT 0x00000010 552de2bdb3dSTom St Denis #define AUDIO_DESCRIPTOR9__MAX_CHANNELS_MASK 0x00000007L 553de2bdb3dSTom St Denis #define AUDIO_DESCRIPTOR9__MAX_CHANNELS__SHIFT 0x00000000 554de2bdb3dSTom St Denis #define AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_MASK 0x0000ff00L 555de2bdb3dSTom St Denis #define AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES__SHIFT 0x00000008 556de2bdb3dSTom St Denis #define AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000L 557de2bdb3dSTom St Denis #define AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x00000018 558de2bdb3dSTom St Denis #define AUX_ARB_CONTROL__AUX_ARB_PRIORITY_MASK 0x00000003L 559de2bdb3dSTom St Denis #define AUX_ARB_CONTROL__AUX_ARB_PRIORITY__SHIFT 0x00000000 560de2bdb3dSTom St Denis #define AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG_MASK 0x02000000L 561de2bdb3dSTom St Denis #define AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG__SHIFT 0x00000019 562de2bdb3dSTom St Denis #define AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ_MASK 0x01000000L 563de2bdb3dSTom St Denis #define AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ__SHIFT 0x00000018 564de2bdb3dSTom St Denis #define AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ_MASK 0x01000000L 565de2bdb3dSTom St Denis #define AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ__SHIFT 0x00000018 566de2bdb3dSTom St Denis #define AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO_MASK 0x00000400L 567de2bdb3dSTom St Denis #define AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO__SHIFT 0x0000000a 568de2bdb3dSTom St Denis #define AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO_MASK 0x00000100L 569de2bdb3dSTom St Denis #define AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO__SHIFT 0x00000008 570de2bdb3dSTom St Denis #define AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS_MASK 0x0000000cL 571de2bdb3dSTom St Denis #define AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS__SHIFT 0x00000002 572de2bdb3dSTom St Denis #define AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG_MASK 0x00020000L 573de2bdb3dSTom St Denis #define AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG__SHIFT 0x00000011 574de2bdb3dSTom St Denis #define AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ_MASK 0x00010000L 575de2bdb3dSTom St Denis #define AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ__SHIFT 0x00000010 576de2bdb3dSTom St Denis #define AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ_MASK 0x00010000L 577de2bdb3dSTom St Denis #define AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ__SHIFT 0x00000010 578de2bdb3dSTom St Denis #define AUX_CONTROL__AUX_DEGLITCH_EN_MASK 0x20000000L 579de2bdb3dSTom St Denis #define AUX_CONTROL__AUX_DEGLITCH_EN__SHIFT 0x0000001d 580de2bdb3dSTom St Denis #define AUX_CONTROL__AUX_EN_MASK 0x00000001L 581de2bdb3dSTom St Denis #define AUX_CONTROL__AUX_EN__SHIFT 0x00000000 582de2bdb3dSTom St Denis #define AUX_CONTROL__AUX_HPD_SEL_MASK 0x00700000L 583de2bdb3dSTom St Denis #define AUX_CONTROL__AUX_HPD_SEL__SHIFT 0x00000014 584de2bdb3dSTom St Denis #define AUX_CONTROL__AUX_IGNORE_HPD_DISCON_MASK 0x00010000L 585de2bdb3dSTom St Denis #define AUX_CONTROL__AUX_IGNORE_HPD_DISCON__SHIFT 0x00000010 586de2bdb3dSTom St Denis #define AUX_CONTROL__AUX_IMPCAL_REQ_EN_MASK 0x01000000L 587de2bdb3dSTom St Denis #define AUX_CONTROL__AUX_IMPCAL_REQ_EN__SHIFT 0x00000018 588de2bdb3dSTom St Denis #define AUX_CONTROL__AUX_LS_READ_EN_MASK 0x00000100L 589de2bdb3dSTom St Denis #define AUX_CONTROL__AUX_LS_READ_EN__SHIFT 0x00000008 590de2bdb3dSTom St Denis #define AUX_CONTROL__AUX_LS_UPDATE_DISABLE_MASK 0x00001000L 591de2bdb3dSTom St Denis #define AUX_CONTROL__AUX_LS_UPDATE_DISABLE__SHIFT 0x0000000c 592de2bdb3dSTom St Denis #define AUX_CONTROL__AUX_MODE_DET_EN_MASK 0x00040000L 593de2bdb3dSTom St Denis #define AUX_CONTROL__AUX_MODE_DET_EN__SHIFT 0x00000012 594de2bdb3dSTom St Denis #define AUX_CONTROL__AUX_TEST_MODE_MASK 0x10000000L 595de2bdb3dSTom St Denis #define AUX_CONTROL__AUX_TEST_MODE__SHIFT 0x0000001c 596de2bdb3dSTom St Denis #define AUX_CONTROL__SPARE_0_MASK 0x40000000L 597de2bdb3dSTom St Denis #define AUX_CONTROL__SPARE_0__SHIFT 0x0000001e 598de2bdb3dSTom St Denis #define AUX_CONTROL__SPARE_1_MASK 0x80000000L 599de2bdb3dSTom St Denis #define AUX_CONTROL__SPARE_1__SHIFT 0x0000001f 600de2bdb3dSTom St Denis #define AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT_MASK 0x00020000L 601de2bdb3dSTom St Denis #define AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT__SHIFT 0x00000011 602de2bdb3dSTom St Denis #define AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START_MASK 0x00040000L 603de2bdb3dSTom St Denis #define AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START__SHIFT 0x00000012 604de2bdb3dSTom St Denis #define AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP_MASK 0x00080000L 605de2bdb3dSTom St Denis #define AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP__SHIFT 0x00000013 606de2bdb3dSTom St Denis #define AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD_MASK 0x70000000L 607de2bdb3dSTom St Denis #define AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD__SHIFT 0x0000001c 608de2bdb3dSTom St Denis #define AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN_MASK 0x00003000L 609de2bdb3dSTom St Denis #define AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN__SHIFT 0x0000000c 610de2bdb3dSTom St Denis #define AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN_MASK 0x00300000L 611de2bdb3dSTom St Denis #define AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN__SHIFT 0x00000014 612de2bdb3dSTom St Denis #define AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW_MASK 0x00000700L 613de2bdb3dSTom St Denis #define AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW__SHIFT 0x00000008 614de2bdb3dSTom St Denis #define AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW_MASK 0x00000070L 615de2bdb3dSTom St Denis #define AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW__SHIFT 0x00000004 616de2bdb3dSTom St Denis #define AUX_DPHY_RX_CONTROL0__AUX_RX_TIMEOUT_LEN_MASK 0x07000000L 617de2bdb3dSTom St Denis #define AUX_DPHY_RX_CONTROL0__AUX_RX_TIMEOUT_LEN__SHIFT 0x00000018 618de2bdb3dSTom St Denis #define AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN_MASK 0x00010000L 619de2bdb3dSTom St Denis #define AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN__SHIFT 0x00000010 620de2bdb3dSTom St Denis #define AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP_MASK 0x000000ffL 621de2bdb3dSTom St Denis #define AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP__SHIFT 0x00000000 622de2bdb3dSTom St Denis #define AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT_MASK 0x001f0000L 623de2bdb3dSTom St Denis #define AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT__SHIFT 0x00000010 624de2bdb3dSTom St Denis #define AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_MASK 0x3fe00000L 625de2bdb3dSTom St Denis #define AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD__SHIFT 0x00000015 626de2bdb3dSTom St Denis #define AUX_DPHY_RX_STATUS__AUX_RX_STATE_MASK 0x00000007L 627de2bdb3dSTom St Denis #define AUX_DPHY_RX_STATUS__AUX_RX_STATE__SHIFT 0x00000000 628de2bdb3dSTom St Denis #define AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT_MASK 0x00001f00L 629de2bdb3dSTom St Denis #define AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT__SHIFT 0x00000008 630de2bdb3dSTom St Denis #define AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MASK 0x00000007L 631de2bdb3dSTom St Denis #define AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN__SHIFT 0x00000000 632de2bdb3dSTom St Denis #define AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS_MASK 0x00003f00L 633de2bdb3dSTom St Denis #define AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS__SHIFT 0x00000008 634de2bdb3dSTom St Denis #define AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE_MASK 0x00000030L 635de2bdb3dSTom St Denis #define AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE__SHIFT 0x00000004 636de2bdb3dSTom St Denis #define AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV_MASK 0x01ff0000L 637de2bdb3dSTom St Denis #define AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV__SHIFT 0x00000010 638de2bdb3dSTom St Denis #define AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL_MASK 0x00000001L 639de2bdb3dSTom St Denis #define AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL__SHIFT 0x00000000 640de2bdb3dSTom St Denis #define AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE_MASK 0x00000001L 641de2bdb3dSTom St Denis #define AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE__SHIFT 0x00000000 642de2bdb3dSTom St Denis #define AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD_MASK 0x01ff0000L 643de2bdb3dSTom St Denis #define AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD__SHIFT 0x00000010 644de2bdb3dSTom St Denis #define AUX_DPHY_TX_STATUS__AUX_TX_STATE_MASK 0x00000070L 645de2bdb3dSTom St Denis #define AUX_DPHY_TX_STATUS__AUX_TX_STATE__SHIFT 0x00000004 646de2bdb3dSTom St Denis #define AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_EN_MASK 0x00000001L 647de2bdb3dSTom St Denis #define AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_EN__SHIFT 0x00000000 648de2bdb3dSTom St Denis #define AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK_MASK 0x00000020L 649de2bdb3dSTom St Denis #define AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK__SHIFT 0x00000005 650de2bdb3dSTom St Denis #define AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT_MASK 0x00000010L 651de2bdb3dSTom St Denis #define AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT__SHIFT 0x00000004 652de2bdb3dSTom St Denis #define AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK_MASK 0x00000040L 653de2bdb3dSTom St Denis #define AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK__SHIFT 0x00000006 654de2bdb3dSTom St Denis #define AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK_MASK 0x00000002L 655de2bdb3dSTom St Denis #define AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK__SHIFT 0x00000001 656de2bdb3dSTom St Denis #define AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT_MASK 0x00000001L 657de2bdb3dSTom St Denis #define AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT__SHIFT 0x00000000 658de2bdb3dSTom St Denis #define AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK_MASK 0x00000004L 659de2bdb3dSTom St Denis #define AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK__SHIFT 0x00000002 660de2bdb3dSTom St Denis #define AUX_LS_DATA__AUX_LS_DATA_MASK 0x0000ff00L 661de2bdb3dSTom St Denis #define AUX_LS_DATA__AUX_LS_DATA__SHIFT 0x00000008 662de2bdb3dSTom St Denis #define AUX_LS_DATA__AUX_LS_INDEX_MASK 0x001f0000L 663de2bdb3dSTom St Denis #define AUX_LS_DATA__AUX_LS_INDEX__SHIFT 0x00000010 664de2bdb3dSTom St Denis #define AUX_LS_STATUS__AUX_LS_CP_IRQ_MASK 0x20000000L 665de2bdb3dSTom St Denis #define AUX_LS_STATUS__AUX_LS_CP_IRQ__SHIFT 0x0000001d 666de2bdb3dSTom St Denis #define AUX_LS_STATUS__AUX_LS_DONE_MASK 0x00000001L 667de2bdb3dSTom St Denis #define AUX_LS_STATUS__AUX_LS_DONE__SHIFT 0x00000000 668de2bdb3dSTom St Denis #define AUX_LS_STATUS__AUX_LS_HPD_DISCON_MASK 0x00000200L 669de2bdb3dSTom St Denis #define AUX_LS_STATUS__AUX_LS_HPD_DISCON__SHIFT 0x00000009 670de2bdb3dSTom St Denis #define AUX_LS_STATUS__AUX_LS_NON_AUX_MODE_MASK 0x00000800L 671de2bdb3dSTom St Denis #define AUX_LS_STATUS__AUX_LS_NON_AUX_MODE__SHIFT 0x0000000b 672de2bdb3dSTom St Denis #define AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT_MASK 0x1f000000L 673de2bdb3dSTom St Denis #define AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT__SHIFT 0x00000018 674de2bdb3dSTom St Denis #define AUX_LS_STATUS__AUX_LS_REQ_MASK 0x00000002L 675de2bdb3dSTom St Denis #define AUX_LS_STATUS__AUX_LS_REQ__SHIFT 0x00000001 676de2bdb3dSTom St Denis #define AUX_LS_STATUS__AUX_LS_RX_INVALID_START_MASK 0x00080000L 677de2bdb3dSTom St Denis #define AUX_LS_STATUS__AUX_LS_RX_INVALID_START__SHIFT 0x00000013 678de2bdb3dSTom St Denis #define AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP_MASK 0x00004000L 679de2bdb3dSTom St Denis #define AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP__SHIFT 0x0000000e 680de2bdb3dSTom St Denis #define AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL_MASK 0x00001000L 681de2bdb3dSTom St Denis #define AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL__SHIFT 0x0000000c 682de2bdb3dSTom St Denis #define AUX_LS_STATUS__AUX_LS_RX_OVERFLOW_MASK 0x00000100L 683de2bdb3dSTom St Denis #define AUX_LS_STATUS__AUX_LS_RX_OVERFLOW__SHIFT 0x00000008 684de2bdb3dSTom St Denis #define AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE_MASK 0x00000400L 685de2bdb3dSTom St Denis #define AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE__SHIFT 0x0000000a 686de2bdb3dSTom St Denis #define AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H_MASK 0x00400000L 687de2bdb3dSTom St Denis #define AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H__SHIFT 0x00000016 688de2bdb3dSTom St Denis #define AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L_MASK 0x00800000L 689de2bdb3dSTom St Denis #define AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L__SHIFT 0x00000017 690de2bdb3dSTom St Denis #define AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET_MASK 0x00100000L 691de2bdb3dSTom St Denis #define AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET__SHIFT 0x00000014 692de2bdb3dSTom St Denis #define AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H_MASK 0x00040000L 693de2bdb3dSTom St Denis #define AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H__SHIFT 0x00000012 694de2bdb3dSTom St Denis #define AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L_MASK 0x00020000L 695de2bdb3dSTom St Denis #define AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L__SHIFT 0x00000011 696de2bdb3dSTom St Denis #define AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_MASK 0x00000080L 697de2bdb3dSTom St Denis #define AUX_LS_STATUS__AUX_LS_RX_TIMEOUT__SHIFT 0x00000007 698de2bdb3dSTom St Denis #define AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE_MASK 0x00000070L 699de2bdb3dSTom St Denis #define AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE__SHIFT 0x00000004 700de2bdb3dSTom St Denis #define AUX_LS_STATUS__AUX_LS_UPDATED_ACK_MASK 0x80000000L 701de2bdb3dSTom St Denis #define AUX_LS_STATUS__AUX_LS_UPDATED_ACK__SHIFT 0x0000001f 702de2bdb3dSTom St Denis #define AUX_LS_STATUS__AUX_LS_UPDATED_MASK 0x40000000L 703de2bdb3dSTom St Denis #define AUX_LS_STATUS__AUX_LS_UPDATED__SHIFT 0x0000001e 704de2bdb3dSTom St Denis #define AUXN_IMPCAL__AUXN_CALOUT_ERROR_AK_MASK 0x00000400L 705de2bdb3dSTom St Denis #define AUXN_IMPCAL__AUXN_CALOUT_ERROR_AK__SHIFT 0x0000000a 706de2bdb3dSTom St Denis #define AUXN_IMPCAL__AUXN_CALOUT_ERROR_MASK 0x00000200L 707de2bdb3dSTom St Denis #define AUXN_IMPCAL__AUXN_CALOUT_ERROR__SHIFT 0x00000009 708de2bdb3dSTom St Denis #define AUXN_IMPCAL__AUXN_IMPCAL_CALOUT_MASK 0x00000100L 709de2bdb3dSTom St Denis #define AUXN_IMPCAL__AUXN_IMPCAL_CALOUT__SHIFT 0x00000008 710de2bdb3dSTom St Denis #define AUXN_IMPCAL__AUXN_IMPCAL_ENABLE_MASK 0x00000001L 711de2bdb3dSTom St Denis #define AUXN_IMPCAL__AUXN_IMPCAL_ENABLE__SHIFT 0x00000000 712de2bdb3dSTom St Denis #define AUXN_IMPCAL__AUXN_IMPCAL_OVERRIDE_ENABLE_MASK 0x10000000L 713de2bdb3dSTom St Denis #define AUXN_IMPCAL__AUXN_IMPCAL_OVERRIDE_ENABLE__SHIFT 0x0000001c 714de2bdb3dSTom St Denis #define AUXN_IMPCAL__AUXN_IMPCAL_OVERRIDE_MASK 0x0f000000L 715de2bdb3dSTom St Denis #define AUXN_IMPCAL__AUXN_IMPCAL_OVERRIDE__SHIFT 0x00000018 716de2bdb3dSTom St Denis #define AUXN_IMPCAL__AUXN_IMPCAL_STEP_DELAY_MASK 0x00f00000L 717de2bdb3dSTom St Denis #define AUXN_IMPCAL__AUXN_IMPCAL_STEP_DELAY__SHIFT 0x00000014 718de2bdb3dSTom St Denis #define AUXN_IMPCAL__AUXN_IMPCAL_VALUE_MASK 0x000f0000L 719de2bdb3dSTom St Denis #define AUXN_IMPCAL__AUXN_IMPCAL_VALUE__SHIFT 0x00000010 720de2bdb3dSTom St Denis #define AUXP_IMPCAL__AUXP_CALOUT_ERROR_AK_MASK 0x00000400L 721de2bdb3dSTom St Denis #define AUXP_IMPCAL__AUXP_CALOUT_ERROR_AK__SHIFT 0x0000000a 722de2bdb3dSTom St Denis #define AUXP_IMPCAL__AUXP_CALOUT_ERROR_MASK 0x00000200L 723de2bdb3dSTom St Denis #define AUXP_IMPCAL__AUXP_CALOUT_ERROR__SHIFT 0x00000009 724de2bdb3dSTom St Denis #define AUXP_IMPCAL__AUXP_IMPCAL_CALOUT_MASK 0x00000100L 725de2bdb3dSTom St Denis #define AUXP_IMPCAL__AUXP_IMPCAL_CALOUT__SHIFT 0x00000008 726de2bdb3dSTom St Denis #define AUXP_IMPCAL__AUXP_IMPCAL_ENABLE_MASK 0x00000001L 727de2bdb3dSTom St Denis #define AUXP_IMPCAL__AUXP_IMPCAL_ENABLE__SHIFT 0x00000000 728de2bdb3dSTom St Denis #define AUXP_IMPCAL__AUXP_IMPCAL_OVERRIDE_ENABLE_MASK 0x10000000L 729de2bdb3dSTom St Denis #define AUXP_IMPCAL__AUXP_IMPCAL_OVERRIDE_ENABLE__SHIFT 0x0000001c 730de2bdb3dSTom St Denis #define AUXP_IMPCAL__AUXP_IMPCAL_OVERRIDE_MASK 0x0f000000L 731de2bdb3dSTom St Denis #define AUXP_IMPCAL__AUXP_IMPCAL_OVERRIDE__SHIFT 0x00000018 732de2bdb3dSTom St Denis #define AUXP_IMPCAL__AUXP_IMPCAL_STEP_DELAY_MASK 0x00f00000L 733de2bdb3dSTom St Denis #define AUXP_IMPCAL__AUXP_IMPCAL_STEP_DELAY__SHIFT 0x00000014 734de2bdb3dSTom St Denis #define AUXP_IMPCAL__AUXP_IMPCAL_VALUE_MASK 0x000f0000L 735de2bdb3dSTom St Denis #define AUXP_IMPCAL__AUXP_IMPCAL_VALUE__SHIFT 0x00000010 736de2bdb3dSTom St Denis #define AUX_SW_CONTROL__AUX_LS_READ_TRIG_MASK 0x00000004L 737de2bdb3dSTom St Denis #define AUX_SW_CONTROL__AUX_LS_READ_TRIG__SHIFT 0x00000002 738de2bdb3dSTom St Denis #define AUX_SW_CONTROL__AUX_SW_GO_MASK 0x00000001L 739de2bdb3dSTom St Denis #define AUX_SW_CONTROL__AUX_SW_GO__SHIFT 0x00000000 740de2bdb3dSTom St Denis #define AUX_SW_CONTROL__AUX_SW_START_DELAY_MASK 0x000000f0L 741de2bdb3dSTom St Denis #define AUX_SW_CONTROL__AUX_SW_START_DELAY__SHIFT 0x00000004 742de2bdb3dSTom St Denis #define AUX_SW_CONTROL__AUX_SW_WR_BYTES_MASK 0x001f0000L 743de2bdb3dSTom St Denis #define AUX_SW_CONTROL__AUX_SW_WR_BYTES__SHIFT 0x00000010 744de2bdb3dSTom St Denis #define AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE_MASK 0x80000000L 745de2bdb3dSTom St Denis #define AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE__SHIFT 0x0000001f 746de2bdb3dSTom St Denis #define AUX_SW_DATA__AUX_SW_DATA_MASK 0x0000ff00L 747de2bdb3dSTom St Denis #define AUX_SW_DATA__AUX_SW_DATA_RW_MASK 0x00000001L 748de2bdb3dSTom St Denis #define AUX_SW_DATA__AUX_SW_DATA_RW__SHIFT 0x00000000 749de2bdb3dSTom St Denis #define AUX_SW_DATA__AUX_SW_DATA__SHIFT 0x00000008 750de2bdb3dSTom St Denis #define AUX_SW_DATA__AUX_SW_INDEX_MASK 0x001f0000L 751de2bdb3dSTom St Denis #define AUX_SW_DATA__AUX_SW_INDEX__SHIFT 0x00000010 752de2bdb3dSTom St Denis #define AUX_SW_STATUS__AUX_ARB_STATUS_MASK 0xc0000000L 753de2bdb3dSTom St Denis #define AUX_SW_STATUS__AUX_ARB_STATUS__SHIFT 0x0000001e 754de2bdb3dSTom St Denis #define AUX_SW_STATUS__AUX_SW_DONE_MASK 0x00000001L 755de2bdb3dSTom St Denis #define AUX_SW_STATUS__AUX_SW_DONE__SHIFT 0x00000000 756de2bdb3dSTom St Denis #define AUX_SW_STATUS__AUX_SW_HPD_DISCON_MASK 0x00000200L 757de2bdb3dSTom St Denis #define AUX_SW_STATUS__AUX_SW_HPD_DISCON__SHIFT 0x00000009 758de2bdb3dSTom St Denis #define AUX_SW_STATUS__AUX_SW_NON_AUX_MODE_MASK 0x00000800L 759de2bdb3dSTom St Denis #define AUX_SW_STATUS__AUX_SW_NON_AUX_MODE__SHIFT 0x0000000b 760de2bdb3dSTom St Denis #define AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT_MASK 0x1f000000L 761de2bdb3dSTom St Denis #define AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT__SHIFT 0x00000018 762de2bdb3dSTom St Denis #define AUX_SW_STATUS__AUX_SW_REQ_MASK 0x00000002L 763de2bdb3dSTom St Denis #define AUX_SW_STATUS__AUX_SW_REQ__SHIFT 0x00000001 764de2bdb3dSTom St Denis #define AUX_SW_STATUS__AUX_SW_RX_INVALID_START_MASK 0x00080000L 765de2bdb3dSTom St Denis #define AUX_SW_STATUS__AUX_SW_RX_INVALID_START__SHIFT 0x00000013 766de2bdb3dSTom St Denis #define AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP_MASK 0x00004000L 767de2bdb3dSTom St Denis #define AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP__SHIFT 0x0000000e 768de2bdb3dSTom St Denis #define AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL_MASK 0x00001000L 769de2bdb3dSTom St Denis #define AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL__SHIFT 0x0000000c 770de2bdb3dSTom St Denis #define AUX_SW_STATUS__AUX_SW_RX_OVERFLOW_MASK 0x00000100L 771de2bdb3dSTom St Denis #define AUX_SW_STATUS__AUX_SW_RX_OVERFLOW__SHIFT 0x00000008 772de2bdb3dSTom St Denis #define AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE_MASK 0x00000400L 773de2bdb3dSTom St Denis #define AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE__SHIFT 0x0000000a 774de2bdb3dSTom St Denis #define AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H_MASK 0x00400000L 775de2bdb3dSTom St Denis #define AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H__SHIFT 0x00000016 776de2bdb3dSTom St Denis #define AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L_MASK 0x00800000L 777de2bdb3dSTom St Denis #define AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L__SHIFT 0x00000017 778de2bdb3dSTom St Denis #define AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET_MASK 0x00100000L 779de2bdb3dSTom St Denis #define AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET__SHIFT 0x00000014 780de2bdb3dSTom St Denis #define AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H_MASK 0x00040000L 781de2bdb3dSTom St Denis #define AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H__SHIFT 0x00000012 782de2bdb3dSTom St Denis #define AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L_MASK 0x00020000L 783de2bdb3dSTom St Denis #define AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L__SHIFT 0x00000011 784de2bdb3dSTom St Denis #define AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_MASK 0x00000080L 785de2bdb3dSTom St Denis #define AUX_SW_STATUS__AUX_SW_RX_TIMEOUT__SHIFT 0x00000007 786de2bdb3dSTom St Denis #define AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE_MASK 0x00000070L 787de2bdb3dSTom St Denis #define AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE__SHIFT 0x00000004 788de2bdb3dSTom St Denis #define AZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER__APPLICATION_POSITION_IN_CYCLIC_BUFFER_MASK 0xffffffffL 789de2bdb3dSTom St Denis #define AZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER__APPLICATION_POSITION_IN_CYCLIC_BUFFER__SHIFT 0x00000000 790de2bdb3dSTom St Denis #define AZALIA_AUDIO_DTO__AZALIA_AUDIO_DTO_MODULE_MASK 0xffff0000L 791de2bdb3dSTom St Denis #define AZALIA_AUDIO_DTO__AZALIA_AUDIO_DTO_MODULE__SHIFT 0x00000010 792de2bdb3dSTom St Denis #define AZALIA_AUDIO_DTO__AZALIA_AUDIO_DTO_PHASE_MASK 0x0000ffffL 793de2bdb3dSTom St Denis #define AZALIA_AUDIO_DTO__AZALIA_AUDIO_DTO_PHASE__SHIFT 0x00000000 794de2bdb3dSTom St Denis #define AZALIA_AUDIO_DTO_CONTROL__AZALIA_AUDIO_FORCE_DTO_MASK 0x00000300L 795de2bdb3dSTom St Denis #define AZALIA_AUDIO_DTO_CONTROL__AZALIA_AUDIO_FORCE_DTO__SHIFT 0x00000008 796de2bdb3dSTom St Denis #define AZALIA_BDL_DMA_CONTROL__BDL_DMA_ISOCHRONOUS_MASK 0x00000030L 797de2bdb3dSTom St Denis #define AZALIA_BDL_DMA_CONTROL__BDL_DMA_ISOCHRONOUS__SHIFT 0x00000004 798de2bdb3dSTom St Denis #define AZALIA_BDL_DMA_CONTROL__BDL_DMA_NON_SNOOP_MASK 0x00000003L 799de2bdb3dSTom St Denis #define AZALIA_BDL_DMA_CONTROL__BDL_DMA_NON_SNOOP__SHIFT 0x00000000 800de2bdb3dSTom St Denis #define AZALIA_CONTROLLER_DEBUG__CONTROLLER_DEBUG_MASK 0xffffffffL 801de2bdb3dSTom St Denis #define AZALIA_CONTROLLER_DEBUG__CONTROLLER_DEBUG__SHIFT 0x00000000 802de2bdb3dSTom St Denis #define AZALIA_CORB_DMA_CONTROL__CORB_DMA_ISOCHRONOUS_MASK 0x00000010L 803de2bdb3dSTom St Denis #define AZALIA_CORB_DMA_CONTROL__CORB_DMA_ISOCHRONOUS__SHIFT 0x00000004 804de2bdb3dSTom St Denis #define AZALIA_CORB_DMA_CONTROL__CORB_DMA_NON_SNOOP_MASK 0x00000001L 805de2bdb3dSTom St Denis #define AZALIA_CORB_DMA_CONTROL__CORB_DMA_NON_SNOOP__SHIFT 0x00000000 806de2bdb3dSTom St Denis #define AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK 0xffffffffL 807de2bdb3dSTom St Denis #define AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT 0x00000000 808de2bdb3dSTom St Denis #define AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK 0xffffffffL 809de2bdb3dSTom St Denis #define AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT 0x00000000 810de2bdb3dSTom St Denis #define AZALIA_CYCLIC_BUFFER_SYNC__CYCLIC_BUFFER_SYNC_ENABLE_MASK 0x00000001L 811de2bdb3dSTom St Denis #define AZALIA_CYCLIC_BUFFER_SYNC__CYCLIC_BUFFER_SYNC_ENABLE__SHIFT 0x00000000 812de2bdb3dSTom St Denis #define AZALIA_DATA_DMA_CONTROL__AZALIA_IOC_GENERATION_METHOD_MASK 0x00010000L 813de2bdb3dSTom St Denis #define AZALIA_DATA_DMA_CONTROL__AZALIA_IOC_GENERATION_METHOD__SHIFT 0x00000010 814de2bdb3dSTom St Denis #define AZALIA_DATA_DMA_CONTROL__AZALIA_UNDERFLOW_CONTROL_MASK 0x00020000L 815de2bdb3dSTom St Denis #define AZALIA_DATA_DMA_CONTROL__AZALIA_UNDERFLOW_CONTROL__SHIFT 0x00000011 816de2bdb3dSTom St Denis #define AZALIA_DATA_DMA_CONTROL__DATA_DMA_ISOCHRONOUS_MASK 0x00000030L 817de2bdb3dSTom St Denis #define AZALIA_DATA_DMA_CONTROL__DATA_DMA_ISOCHRONOUS__SHIFT 0x00000004 818de2bdb3dSTom St Denis #define AZALIA_DATA_DMA_CONTROL__DATA_DMA_NON_SNOOP_MASK 0x00000003L 819de2bdb3dSTom St Denis #define AZALIA_DATA_DMA_CONTROL__DATA_DMA_NON_SNOOP__SHIFT 0x00000000 820de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL__COMPRESSED_CHANNEL_COUNT_MASK 0x00000070L 821de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL__COMPRESSED_CHANNEL_COUNT__SHIFT 0x00000004 822de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL__HBR_CHANNEL_COUNT_MASK 0x00000007L 823de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL__HBR_CHANNEL_COUNT__SHIFT 0x00000000 824de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0x0000000fL 825de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x00000000 826de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0x000000f0L 827de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x00000004 828de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x00000070L 829de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x00000004 830de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0x0000000fL 831de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x00000000 832de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x00000700L 833de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x00000008 834de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x00003800L 835de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0x0000000b 836de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x00004000L 837de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0x0000000e 838de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x00008000L 839de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0x0000000f 840de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x00007f00L 841de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x00000008 842de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x00000010L 843de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x00000004 844de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x00000001L 845de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x00000000 846de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x00800000L 847de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x00000017 848de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x00000080L 849de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x00000007 850de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x00000020L 851de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x00000005 852de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x00000008L 853de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x00000003 854de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x00000040L 855de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x00000006 856de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x00000004L 857de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x00000002 858de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x00000002L 859de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x00000001 860de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE_MASK 0x00000001L 861de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE__SHIFT 0x00000000 862de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE_MASK 0x000000ffL 863de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE__SHIFT 0x00000000 864de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L 865de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x00000003 866de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L 867de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x00000000 868de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000f0000L 869de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x00000010 870de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L 871de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x00000008 872de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L 873de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x00000009 874de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x00000010L 875de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x00000004 876de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L 877de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x00000001 878de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L 879de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0x0000000b 880de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L 881de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x00000002 882de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L 883de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0x0000000a 884de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L 885de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x00000006 886de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L 887de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x00000005 888de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00f00000L 889de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x00000014 890de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L 891de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x00000007 892de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xffffffffL 893de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x00000000 894de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001f0000L 895de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x00000010 896de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000fffL 897de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x00000000 898de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_CONVERTER_PIN_DEBUG__AZALIA_DEBUG__SHIFT 0x00000000 899de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY_MASK 0x00700000L 900de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY__SHIFT 0x00000014 901de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL_MASK 0x00000003L 902de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL__SHIFT 0x00000000 903de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_DEBUG__CODEC_DEBUG_MASK 0xffffffffL 904de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_DEBUG__CODEC_DEBUG__SHIFT 0x00000000 905de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA_MASK 0xffffffffL 906de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA__SHIFT 0x00000000 907de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX_MASK 0x000000ffL 908de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX__SHIFT 0x00000000 9094caca706SXiaojie Yuan #define AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_WRITE_EN_MASK 0x00000100L 9104caca706SXiaojie Yuan #define AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_WRITE_EN__SHIFT 0x00000008 911de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION__CONVERTER_SYNCHRONIZATION_MASK 0x0000003fL 912de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION__CONVERTER_SYNCHRONIZATION__SHIFT 0x00000000 913de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__CLKSTOPOK_MASK 0x00000200L 914de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__CLKSTOPOK__SHIFT 0x00000009 915de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_ACT_MASK 0x000000f0L 916de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_ACT__SHIFT 0x00000004 917de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SET_MASK 0x0000000fL 918de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SET__SHIFT 0x00000000 919de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SETTINGS_RESET_MASK 0x00000400L 920de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SETTINGS_RESET__SHIFT 0x0000000a 921de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESET__CODEC_RESET_MASK 0x00000001L 922de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESET__CODEC_RESET__SHIFT 0x00000000 923de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE0_MASK 0x000000ffL 924de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE0__SHIFT 0x00000000 925de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE1_MASK 0x0000ff00L 926de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE1__SHIFT 0x00000008 927de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE2_MASK 0x00ff0000L 928de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE2__SHIFT 0x00000010 929de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE3_MASK 0xff000000L 930de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE3__SHIFT 0x00000018 931de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__AZALIA_CODEC_FUNCTION_PARAMETER_GROUP_TYPE_MASK 0xffffffffL 932de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__AZALIA_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__SHIFT 0x00000000 933de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__AZALIA_CODEC_FUNCTION_PARAMETER_POWER_STATES_MASK 0x3fffffffL 934de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__AZALIA_CODEC_FUNCTION_PARAMETER_POWER_STATES__SHIFT 0x00000000 935de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__CLKSTOP_MASK 0x40000000L 936de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__CLKSTOP__SHIFT 0x0000001e 937de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__EPSS_MASK 0x80000000L 938de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__EPSS__SHIFT 0x0000001f 939de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__AZALIA_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS_MASK 0xffffffffL 940de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__AZALIA_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__SHIFT 0x00000000 941de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001f0000L 942de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x00000010 943de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000fffL 944de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x00000000 945de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO_MASK 0xffffffffL 946de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO__SHIFT 0x00000000 947de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2_MASK 0x00ff0000L 948de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT 0x00000010 949de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS_MASK 0x00000007L 950de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT 0x00000000 951de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_MASK 0x0000ff00L 952de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT 0x00000008 953de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000L 954de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x00000018 955de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2_MASK 0x00ff0000L 956de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2__SHIFT 0x00000010 957de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS_MASK 0x00000007L 958de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS__SHIFT 0x00000000 959de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_MASK 0x0000ff00L 960de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES__SHIFT 0x00000008 961de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2_MASK 0x00ff0000L 962de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2__SHIFT 0x00000010 963de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS_MASK 0x00000007L 964de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS__SHIFT 0x00000000 965de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_MASK 0x0000ff00L 966de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES__SHIFT 0x00000008 967de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2_MASK 0x00ff0000L 968de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2__SHIFT 0x00000010 969de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS_MASK 0x00000007L 970de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS__SHIFT 0x00000000 971de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_MASK 0x0000ff00L 972de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES__SHIFT 0x00000008 973de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2_MASK 0x00ff0000L 974de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2__SHIFT 0x00000010 975de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS_MASK 0x00000007L 976de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS__SHIFT 0x00000000 977de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_MASK 0x0000ff00L 978de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES__SHIFT 0x00000008 979de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2_MASK 0x00ff0000L 980de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2__SHIFT 0x00000010 981de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS_MASK 0x00000007L 982de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS__SHIFT 0x00000000 983de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_MASK 0x0000ff00L 984de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES__SHIFT 0x00000008 985de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2_MASK 0x00ff0000L 986de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2__SHIFT 0x00000010 987de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS_MASK 0x00000007L 988de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS__SHIFT 0x00000000 989de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_MASK 0x0000ff00L 990de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES__SHIFT 0x00000008 991de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2_MASK 0x00ff0000L 992de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2__SHIFT 0x00000010 993de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS_MASK 0x00000007L 994de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS__SHIFT 0x00000000 995de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_MASK 0x0000ff00L 996de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES__SHIFT 0x00000008 997de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2_MASK 0x00ff0000L 998de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2__SHIFT 0x00000010 999de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS_MASK 0x00000007L 1000de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS__SHIFT 0x00000000 1001de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_MASK 0x0000ff00L 1002de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES__SHIFT 0x00000008 1003de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2_MASK 0x00ff0000L 1004de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2__SHIFT 0x00000010 1005de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS_MASK 0x00000007L 1006de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS__SHIFT 0x00000000 1007de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_MASK 0x0000ff00L 1008de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES__SHIFT 0x00000008 1009de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2_MASK 0x00ff0000L 1010de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2__SHIFT 0x00000010 1011de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS_MASK 0x00000007L 1012de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS__SHIFT 0x00000000 1013de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_MASK 0x0000ff00L 1014de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES__SHIFT 0x00000008 1015de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2_MASK 0x00ff0000L 1016de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2__SHIFT 0x00000010 1017de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS_MASK 0x00000007L 1018de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS__SHIFT 0x00000000 1019de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_MASK 0x0000ff00L 1020de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES__SHIFT 0x00000008 1021de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2_MASK 0x00ff0000L 1022de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2__SHIFT 0x00000010 1023de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS_MASK 0x00000007L 1024de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS__SHIFT 0x00000000 1025de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_MASK 0x0000ff00L 1026de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES__SHIFT 0x00000008 1027de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2_MASK 0x00ff0000L 1028de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2__SHIFT 0x00000010 1029de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS_MASK 0x00000007L 1030de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS__SHIFT 0x00000000 1031de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_MASK 0x0000ff00L 1032de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES__SHIFT 0x00000008 1033de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION_MASK 0x0000ff00L 1034de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION__SHIFT 0x00000008 1035de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT_MASK 0x80000000L 1036de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT__SHIFT 0x0000001f 1037de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION_MASK 0x00020000L 1038de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION__SHIFT 0x00000011 1039de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO_MASK 0x00fc0000L 1040de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO__SHIFT 0x00000012 1041de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION_MASK 0x00010000L 1042de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION__SHIFT 0x00000010 1043de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT_MASK 0x78000000L 1044de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT__SHIFT 0x0000001b 1045de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION_MASK 0x0000007fL 1046de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION__SHIFT 0x00000000 1047de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK 0x80000000L 1048de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT 0x0000001f 1049de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID_MASK 0x000000f0L 1050de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID__SHIFT 0x00000004 1051de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE_MASK 0x00000001L 1052de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE__SHIFT 0x00000000 1053de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE_MASK 0x00000002L 1054de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE__SHIFT 0x00000001 1055de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID_MASK 0x0000f000L 1056de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID__SHIFT 0x0000000c 1057de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE_MASK 0x00000100L 1058de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE__SHIFT 0x00000008 1059de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE_MASK 0x00000200L 1060de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE__SHIFT 0x00000009 1061de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK 0x00f00000L 1062de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT 0x00000014 1063de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK 0x00010000L 1064de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT 0x00000010 1065de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK 0x00020000L 1066de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT 0x00000011 1067de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK 0xf0000000L 1068de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x0000001c 1069de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK 0x01000000L 1070de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT 0x00000018 1071de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK 0x02000000L 1072de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT 0x00000019 1073de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID_MASK 0x000000f0L 1074de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID__SHIFT 0x00000004 1075de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE_MASK 0x00000001L 1076de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE__SHIFT 0x00000000 1077de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE_MASK 0x00000002L 1078de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE__SHIFT 0x00000001 1079de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID_MASK 0x0000f000L 1080de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID__SHIFT 0x0000000c 1081de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE_MASK 0x00000100L 1082de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE__SHIFT 0x00000008 1083de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE_MASK 0x00000200L 1084de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE__SHIFT 0x00000009 1085de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID_MASK 0x00f00000L 1086de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID__SHIFT 0x00000014 1087de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE_MASK 0x00010000L 1088de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE__SHIFT 0x00000010 1089de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE_MASK 0x00020000L 1090de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE__SHIFT 0x00000011 1091de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID_MASK 0xf0000000L 1092de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID__SHIFT 0x0000001c 1093de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE_MASK 0x01000000L 1094de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE__SHIFT 0x00000018 1095de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE_MASK 0x02000000L 1096de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE__SHIFT 0x00000019 1097de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE_MASK 0x00000001L 1098de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE__SHIFT 0x00000000 1099de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0x0000f000L 1100de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0x0000000c 1101de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0x000f0000L 1102de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x00000010 1103de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0x000000f0L 1104de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x00000004 1105de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0x00f00000L 1106de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x00000014 1107de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3f000000L 1108de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x00000018 1109de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0x00000f00L 1110de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x00000008 1111de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xc0000000L 1112de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x0000001e 1113de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0x0000000fL 1114de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x00000000 1115de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK 0x00000001L 1116de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT 0x00000000 1117de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK 0x00000010L 1118de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT 0x00000004 1119de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC_MASK 0x0000ff00L 1120de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT 0x00000008 1121de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC_MASK 0x000000ffL 1122de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT 0x00000000 1123de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7fffffffL 1124de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x00000000 1125de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID_MASK 0x0000ffffL 1126de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID__SHIFT 0x00000000 1127de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID_MASK 0xffff0000L 1128de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID__SHIFT 0x00000010 1129de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN_MASK 0x000000ffL 1130de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN__SHIFT 0x00000000 1131de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0_MASK 0xffffffffL 1132de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0__SHIFT 0x00000000 1133de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1_MASK 0xffffffffL 1134de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1__SHIFT 0x00000000 1135de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0_MASK 0x000000ffL 1136de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0__SHIFT 0x00000000 1137de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1_MASK 0x0000ff00L 1138de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1__SHIFT 0x00000008 1139de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2_MASK 0x00ff0000L 1140de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2__SHIFT 0x00000010 1141de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3_MASK 0xff000000L 1142de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3__SHIFT 0x00000018 1143de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4_MASK 0x000000ffL 1144de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4__SHIFT 0x00000000 1145de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5_MASK 0x0000ff00L 1146de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5__SHIFT 0x00000008 1147de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6_MASK 0x00ff0000L 1148de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6__SHIFT 0x00000010 1149de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7_MASK 0xff000000L 1150de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7__SHIFT 0x00000018 1151de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10_MASK 0x00ff0000L 1152de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10__SHIFT 0x00000010 1153de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11_MASK 0xff000000L 1154de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11__SHIFT 0x00000018 1155de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8_MASK 0x000000ffL 1156de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8__SHIFT 0x00000000 1157de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9_MASK 0x0000ff00L 1158de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9__SHIFT 0x00000008 1159de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12_MASK 0x000000ffL 1160de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12__SHIFT 0x00000000 1161de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13_MASK 0x0000ff00L 1162de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13__SHIFT 0x00000008 1163de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14_MASK 0x00ff0000L 1164de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14__SHIFT 0x00000010 1165de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15_MASK 0xff000000L 1166de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15__SHIFT 0x00000018 1167de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16_MASK 0x000000ffL 1168de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16__SHIFT 0x00000000 1169de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17_MASK 0x0000ff00L 1170de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17__SHIFT 0x00000008 1171de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x00000080L 1172de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x00000007 1173de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK 0x10000000L 1174de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT 0x0000001c 1175de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK 0x03ffffffL 1176de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT 0x00000000 1177de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x0000003fL 1178de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x00000000 1179de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE_MASK 0x00000040L 1180de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE__SHIFT 0x00000006 1181de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L 1182de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x00000003 1183de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L 1184de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x00000000 1185de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000f0000L 1186de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x00000010 1187de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L 1188de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x00000008 1189de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L 1190de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x00000009 1191de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L 1192de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x00000001 1193de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L 1194de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0x0000000b 1195de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L 1196de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x00000002 1197de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L 1198de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0x0000000a 1199de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L 1200de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x00000006 1201de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L 1202de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x00000005 1203de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00f00000L 1204de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x00000014 1205de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L 1206de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x00000007 1207de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x00000040L 1208de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x00000006 1209de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x01000000L 1210de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x00000018 1211de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x00010000L 1212de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x00000010 1213de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x00000080L 1214de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x00000007 1215de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x00000008L 1216de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x00000003 1217de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x00000001L 1218de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x00000000 1219de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x00000020L 1220de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x00000005 1221de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x00000004L 1222de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x00000002 1223de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x00000010L 1224de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x00000004 1225de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x00000002L 1226de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x00000001 1227de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0x0000ff00L 1228de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x00000008 1229de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_RESYNC_FIFO_CONTROL__RESYNC_FIFO_STARTUP_KEEPOUT_WINDOW_MASK 0x0000003fL 1230de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_RESYNC_FIFO_CONTROL__RESYNC_FIFO_STARTUP_KEEPOUT_WINDOW__SHIFT 0x00000000 1231de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID__AZALIA_CODEC_ROOT_PARAMETER_REVISION_ID_MASK 0xffffffffL 1232de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID__AZALIA_CODEC_ROOT_PARAMETER_REVISION_ID__SHIFT 0x00000000 1233de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__AZALIA_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID_MASK 0xffffffffL 1234de2bdb3dSTom St Denis #define AZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__AZALIA_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__SHIFT 0x00000000 1235de2bdb3dSTom St Denis #define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE_MASK 0x00000003L 1236de2bdb3dSTom St Denis #define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE__SHIFT 0x00000000 1237de2bdb3dSTom St Denis #define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER_MASK 0x0000003cL 1238de2bdb3dSTom St Denis #define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER__SHIFT 0x00000002 1239de2bdb3dSTom St Denis #define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_MASK 0x00000003L 1240de2bdb3dSTom St Denis #define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN_MASK 0x00000004L 1241de2bdb3dSTom St Denis #define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN__SHIFT 0x00000002 1242de2bdb3dSTom St Denis #define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY__SHIFT 0x00000000 1243de2bdb3dSTom St Denis #define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_MASK 0x00000078L 1244de2bdb3dSTom St Denis #define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN_MASK 0x00000080L 1245de2bdb3dSTom St Denis #define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN__SHIFT 0x00000007 1246de2bdb3dSTom St Denis #define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH__SHIFT 0x00000003 1247de2bdb3dSTom St Denis #define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_MASK 0x0000003fL 1248de2bdb3dSTom St Denis #define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x00000040L 1249de2bdb3dSTom St Denis #define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x00000006 1250de2bdb3dSTom St Denis #define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY__SHIFT 0x00000000 1251de2bdb3dSTom St Denis #define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK 0x0000000fL 1252de2bdb3dSTom St Denis #define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x00000010L 1253de2bdb3dSTom St Denis #define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x00000004 1254de2bdb3dSTom St Denis #define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT 0x00000000 1255de2bdb3dSTom St Denis #define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_MASK 0x00000060L 1256de2bdb3dSTom St Denis #define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A__SHIFT 0x00000005 1257de2bdb3dSTom St Denis #define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID_MASK 0x00000080L 1258de2bdb3dSTom St Denis #define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID__SHIFT 0x00000007 1259de2bdb3dSTom St Denis #define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO_MASK 0x00000010L 1260de2bdb3dSTom St Denis #define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO__SHIFT 0x00000004 1261de2bdb3dSTom St Denis #define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF_MASK 0x0000000fL 1262de2bdb3dSTom St Denis #define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF__SHIFT 0x00000000 1263de2bdb3dSTom St Denis #define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L_MASK 0x0000000fL 1264de2bdb3dSTom St Denis #define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L__SHIFT 0x00000000 1265de2bdb3dSTom St Denis #define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R_MASK 0x000000f0L 1266de2bdb3dSTom St Denis #define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R__SHIFT 0x00000004 1267de2bdb3dSTom St Denis #define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2_MASK 0x0000000fL 1268de2bdb3dSTom St Denis #define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2__SHIFT 0x00000000 1269de2bdb3dSTom St Denis #define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3_MASK 0x000000f0L 1270de2bdb3dSTom St Denis #define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3__SHIFT 0x00000004 1271de2bdb3dSTom St Denis #define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4_MASK 0x0000000fL 1272de2bdb3dSTom St Denis #define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4__SHIFT 0x00000000 1273de2bdb3dSTom St Denis #define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5_MASK 0x000000f0L 1274de2bdb3dSTom St Denis #define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5__SHIFT 0x00000004 1275de2bdb3dSTom St Denis #define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6_MASK 0x0000000fL 1276de2bdb3dSTom St Denis #define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6__SHIFT 0x00000000 1277de2bdb3dSTom St Denis #define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7_MASK 0x000000f0L 1278de2bdb3dSTom St Denis #define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7__SHIFT 0x00000004 1279de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0x0000000fL 1280de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x00000000 1281de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0x000000f0L 1282de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x00000004 1283de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x00000070L 1284de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x00000004 1285de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0x0000000fL 1286de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x00000000 1287de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x00000700L 1288de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x00000008 1289de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x00003800L 1290de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0x0000000b 1291de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x00004000L 1292de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0x0000000e 1293de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x00008000L 1294de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_R_MASK 0x00008000L 1295de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_R__SHIFT 0x0000000f 1296de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0x0000000f 1297de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_2__CC_MASK 0x0000007fL 1298de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_2__CC__SHIFT 0x00000000 1299de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3__KEEPALIVE_MASK 0x00000080L 1300de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3__KEEPALIVE__SHIFT 0x00000007 1301de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x00007f00L 1302de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x00000008 1303de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x00000010L 1304de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x00000004 1305de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x00000001L 1306de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x00000000 1307de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x00800000L 1308de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x00000017 1309de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x00000080L 1310de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x00000007 1311de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x00000020L 1312de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x00000005 1313de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x00000008L 1314de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x00000003 1315de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x00000040L 1316de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x00000006 1317de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x00000004L 1318de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x00000002 1319de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x00000002L 1320de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x00000001 1321de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE_MASK 0x000000ffL 1322de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE__SHIFT 0x00000000 1323de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L 1324de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x00000003 1325de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L 1326de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x00000000 1327de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000f0000L 1328de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x00000010 1329de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L 1330de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x00000008 1331de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L 1332de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x00000009 1333de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x00000010L 1334de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x00000004 1335de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L 1336de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x00000001 1337de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L 1338de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0x0000000b 1339de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L 1340de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x00000002 1341de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L 1342de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0x0000000a 1343de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L 1344de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x00000006 1345de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L 1346de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x00000005 1347de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00f00000L 1348de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x00000014 1349de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L 1350de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x00000007 1351de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xffffffffL 1352de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x00000000 1353de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001f0000L 1354de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x00000010 1355de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000fffL 1356de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x00000000 1357de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY_MASK 0x00700000L 1358de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY__SHIFT 0x00000014 1359de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL_MASK 0x00000003L 1360de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL__SHIFT 0x00000000 1361de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION__CONVERTER_SYNCHRONIZATION_MASK 0x0000003fL 1362de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION__CONVERTER_SYNCHRONIZATION__SHIFT 0x00000000 1363de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__CLKSTOPOK_MASK 0x00000200L 1364de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__CLKSTOPOK__SHIFT 0x00000009 1365de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_ACT_MASK 0x000000f0L 1366de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_ACT__SHIFT 0x00000004 1367de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SET_MASK 0x0000000fL 1368de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SET__SHIFT 0x00000000 1369de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SETTINGS_RESET_MASK 0x00000400L 1370de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SETTINGS_RESET__SHIFT 0x0000000a 1371de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET__CODEC_RESET_MASK 0x00000001L 1372de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET__CODEC_RESET__SHIFT 0x00000000 1373de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_2__SUBSYSTEM_ID_BYTE1_MASK 0x000000ffL 1374de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_2__SUBSYSTEM_ID_BYTE1__SHIFT 0x00000000 1375de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_3__SUBSYSTEM_ID_BYTE2_MASK 0x000000ffL 1376de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_3__SUBSYSTEM_ID_BYTE2__SHIFT 0x00000000 1377de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_4__SUBSYSTEM_ID_BYTE3_MASK 0x000000ffL 1378de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_4__SUBSYSTEM_ID_BYTE3__SHIFT 0x00000000 1379de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE0_MASK 0x000000ffL 1380de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE0__SHIFT 0x00000000 1381de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE1_MASK 0x0000ff00L 1382de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE1__SHIFT 0x00000008 1383de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE2_MASK 0x00ff0000L 1384de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE2__SHIFT 0x00000010 1385de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE3_MASK 0xff000000L 1386de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE3__SHIFT 0x00000018 1387de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__AZALIA_CODEC_FUNCTION_PARAMETER_GROUP_TYPE_MASK 0xffffffffL 1388de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__AZALIA_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__SHIFT 0x00000000 1389de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__AZALIA_CODEC_FUNCTION_PARAMETER_POWER_STATES_MASK 0x3fffffffL 1390de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__AZALIA_CODEC_FUNCTION_PARAMETER_POWER_STATES__SHIFT 0x00000000 1391de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__CLKSTOP_MASK 0x40000000L 1392de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__CLKSTOP__SHIFT 0x0000001e 1393de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__EPSS_MASK 0x80000000L 1394de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__EPSS__SHIFT 0x0000001f 1395de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__AZALIA_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS_MASK 0xffffffffL 1396de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__AZALIA_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__SHIFT 0x00000000 1397de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT__AZALIA_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT_MASK 0xffffffffL 1398de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT__AZALIA_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT__SHIFT 0x00000000 1399de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001f0000L 1400de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x00000010 1401de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000fffL 1402de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x00000000 1403de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO_MASK 0xffffffffL 1404de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO__SHIFT 0x00000000 1405de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_DATA__DESCRIPTOR_MASK 0xffffffffL 1406de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_DATA__DESCRIPTOR__SHIFT 0x00000000 1407de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__DESCRIPTOR_BYTE_2_MASK 0x00ff0000L 1408de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__DESCRIPTOR_BYTE_2__SHIFT 0x00000010 1409de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__FORMAT_CODE_MASK 0x00000078L 1410de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__FORMAT_CODE__SHIFT 0x00000003 1411de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__MAX_CHANNELS_MASK 0x00000007L 1412de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__MAX_CHANNELS__SHIFT 0x00000000 1413de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__SUPPORTED_FREQUENCIES_MASK 0x0000ff00L 1414de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__SUPPORTED_FREQUENCIES__SHIFT 0x00000008 1415de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000L 1416de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x00000018 1417de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_DATA__SINK_DATA_MASK 0xffffffffL 1418de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_DATA__SINK_DATA__SHIFT 0x00000000 1419de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_INDEX__SINK_INFO_INDEX_MASK 0x000000ffL 1420de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_INDEX__SINK_INFO_INDEX__SHIFT 0x00000000 1421de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK 0x000000ffL 1422de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT 0x00000000 1423de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO__DOWN_MIX_INHIBIT_MASK 0x00000080L 1424de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO__DOWN_MIX_INHIBIT__SHIFT 0x00000007 1425de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO__LEVEL_SHIFT_MASK 0x00000078L 1426de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO__LEVEL_SHIFT__SHIFT 0x00000003 1427de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_PIN_CONTROL_HBR__HBR_CAPABLE_MASK 0x00000001L 1428de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_PIN_CONTROL_HBR__HBR_CAPABLE__SHIFT 0x00000000 1429de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_PIN_CONTROL_HBR__HBR_ENABLE_MASK 0x00000010L 1430de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_PIN_CONTROL_HBR__HBR_ENABLE__SHIFT 0x00000004 1431de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC__AUDIO_LIPSYNC_MASK 0x0000ff00L 1432de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC__AUDIO_LIPSYNC__SHIFT 0x00000008 1433de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC__VIDEO_LIPSYNC_MASK 0x000000ffL 1434de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC__VIDEO_LIPSYNC__SHIFT 0x00000000 1435de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_PIN_CONTROL_MANUFACTURER_ID__MANUFACTURER_ID_MASK 0x0000ffffL 1436de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_PIN_CONTROL_MANUFACTURER_ID__MANUFACTURER_ID__SHIFT 0x00000000 1437de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE__MULTICHANNEL01_CHANNEL_ID_MASK 0x000000f0L 1438de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE__MULTICHANNEL01_CHANNEL_ID__SHIFT 0x00000004 1439de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE__MULTICHANNEL01_ENABLE_MASK 0x00000001L 1440de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE__MULTICHANNEL01_ENABLE__SHIFT 0x00000000 1441de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE__MULTICHANNEL01_MUTE_MASK 0x00000002L 1442de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE__MULTICHANNEL01_MUTE__SHIFT 0x00000001 1443de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK 0x000000f0L 1444de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT 0x00000004 1445de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_ENABLE_MASK 0x00000001L 1446de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_ENABLE__SHIFT 0x00000000 1447de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_MUTE_MASK 0x00000002L 1448de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_MUTE__SHIFT 0x00000001 1449de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE__MULTICHANNEL23_CHANNEL_ID_MASK 0x000000f0L 1450de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE__MULTICHANNEL23_CHANNEL_ID__SHIFT 0x00000004 1451de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE__MULTICHANNEL23_ENABLE_MASK 0x00000001L 1452de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE__MULTICHANNEL23_ENABLE__SHIFT 0x00000000 1453de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE__MULTICHANNEL23_MUTE_MASK 0x00000002L 1454de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE__MULTICHANNEL23_MUTE__SHIFT 0x00000001 1455de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK 0x000000f0L 1456de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT 0x00000004 1457de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_ENABLE_MASK 0x00000001L 1458de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_ENABLE__SHIFT 0x00000000 1459de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_MUTE_MASK 0x00000002L 1460de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_MUTE__SHIFT 0x00000001 1461de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE__MULTICHANNEL45_CHANNEL_ID_MASK 0x000000f0L 1462de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE__MULTICHANNEL45_CHANNEL_ID__SHIFT 0x00000004 1463de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE__MULTICHANNEL45_ENABLE_MASK 0x00000001L 1464de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE__MULTICHANNEL45_ENABLE__SHIFT 0x00000000 1465de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE__MULTICHANNEL45_MUTE_MASK 0x00000002L 1466de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE__MULTICHANNEL45_MUTE__SHIFT 0x00000001 1467de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_CHANNEL_ID_MASK 0x000000f0L 1468de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_CHANNEL_ID__SHIFT 0x00000004 1469de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_ENABLE_MASK 0x00000001L 1470de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_ENABLE__SHIFT 0x00000000 1471de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_MUTE_MASK 0x00000002L 1472de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_MUTE__SHIFT 0x00000001 1473de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE__MULTICHANNEL67_CHANNEL_ID_MASK 0x000000f0L 1474de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE__MULTICHANNEL67_CHANNEL_ID__SHIFT 0x00000004 1475de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE__MULTICHANNEL67_ENABLE_MASK 0x00000001L 1476de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE__MULTICHANNEL67_ENABLE__SHIFT 0x00000000 1477de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE__MULTICHANNEL67_MUTE_MASK 0x00000002L 1478de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE__MULTICHANNEL67_MUTE__SHIFT 0x00000001 1479de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_CHANNEL_ID_MASK 0x000000f0L 1480de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x00000004 1481de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_ENABLE_MASK 0x00000001L 1482de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_ENABLE__SHIFT 0x00000000 1483de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_MUTE_MASK 0x00000002L 1484de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_MUTE__SHIFT 0x00000001 1485de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE_MASK 0x00000001L 1486de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE__SHIFT 0x00000000 1487de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_PIN_CONTROL_PORTID0__PORTID_MASK 0xffffffffL 1488de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_PIN_CONTROL_PORTID0__PORTID__SHIFT 0x00000000 1489de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_PIN_CONTROL_PORTID1__PORTID_MASK 0xffffffffL 1490de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_PIN_CONTROL_PORTID1__PORTID__SHIFT 0x00000000 1491de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_PIN_CONTROL_PRODUCT_ID__PRODUCT_ID_MASK 0x0000ffffL 1492de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_PIN_CONTROL_PRODUCT_ID__PRODUCT_ID__SHIFT 0x00000000 1493de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__COLOR_MASK 0x000000f0L 1494de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__COLOR__SHIFT 0x00000004 1495de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__MISC_MASK 0x0000000fL 1496de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__MISC__SHIFT 0x00000000 1497de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__CONNECTION_TYPE_MASK 0x0000000fL 1498de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__CONNECTION_TYPE__SHIFT 0x00000000 1499de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__DEFAULT_DEVICE_MASK 0x000000f0L 1500de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__DEFAULT_DEVICE__SHIFT 0x00000004 1501de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__LOCATION_MASK 0x0000003fL 1502de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__LOCATION__SHIFT 0x00000000 1503de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__PORT_CONNECTIVITY_MASK 0x000000c0L 1504de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__PORT_CONNECTIVITY__SHIFT 0x00000006 1505de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0x0000f000L 1506de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0x0000000c 1507de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0x000f0000L 1508de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x00000010 1509de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0x000000f0L 1510de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x00000004 1511de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0x00f00000L 1512de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x00000014 1513de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3f000000L 1514de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x00000018 1515de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0x00000f00L 1516de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x00000008 1517de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xc0000000L 1518de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x0000001e 1519de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0x0000000fL 1520de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x00000000 1521de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY__CONNECTION_LIST_ENTRY_MASK 0xffffffffL 1522de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY__CONNECTION_LIST_ENTRY__SHIFT 0x00000000 1523de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7fffffffL 1524de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x00000000 1525de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__PRESENCE_DETECT_MASK 0x80000000L 1526de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__PRESENCE_DETECT__SHIFT 0x0000001f 1527de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__DP_CONNECTION_MASK 0x00000200L 1528de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__DP_CONNECTION__SHIFT 0x00000009 1529de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__EXTRA_CONNECTION_INFO_MASK 0x0000fc00L 1530de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__EXTRA_CONNECTION_INFO__SHIFT 0x0000000a 1531de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__HDMI_CONNECTION_MASK 0x00000100L 1532de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__HDMI_CONNECTION__SHIFT 0x00000008 1533de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__SPEAKER_ALLOCATION_MASK 0x0000007fL 1534de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__SPEAKER_ALLOCATION__SHIFT 0x00000000 1535de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_PIN_CONTROL_SINK_DESCRIPTION_LEN__SINK_DESCRIPTION_LEN_MASK 0x000000ffL 1536de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_PIN_CONTROL_SINK_DESCRIPTION_LEN__SINK_DESCRIPTION_LEN__SHIFT 0x00000000 1537de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x00000080L 1538de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x00000007 1539de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x0000003fL 1540de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x00000000 1541de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE_MASK 0x00000040L 1542de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE__SHIFT 0x00000006 1543de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L 1544de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x00000003 1545de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L 1546de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x00000000 1547de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000f0000L 1548de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x00000010 1549de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L 1550de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x00000008 1551de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L 1552de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x00000009 1553de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L 1554de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x00000001 1555de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L 1556de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0x0000000b 1557de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L 1558de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x00000002 1559de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L 1560de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0x0000000a 1561de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L 1562de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x00000006 1563de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L 1564de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x00000005 1565de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00f00000L 1566de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x00000014 1567de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L 1568de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x00000007 1569de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x00000040L 1570de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x00000006 1571de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x01000000L 1572de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x00000018 1573de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x00010000L 1574de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x00000010 1575de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x00000080L 1576de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x00000007 1577de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x00000008L 1578de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x00000003 1579de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x00000001L 1580de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x00000000 1581de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x00000020L 1582de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x00000005 1583de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x00000004L 1584de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x00000002 1585de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x00000010L 1586de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x00000004 1587de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x00000002L 1588de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x00000001 1589de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0x0000ff00L 1590de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x00000008 1591de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_PIN_PARAMETER_CONNECTION_LIST_LENGTH__CONNECTION_LIST_LENGTH_MASK 0xffffffffL 1592de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_PIN_PARAMETER_CONNECTION_LIST_LENGTH__CONNECTION_LIST_LENGTH__SHIFT 0x00000000 1593de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_ROOT_PARAMETER_REVISION_ID__AZALIA_CODEC_ROOT_PARAMETER_REVISION_ID_MASK 0xffffffffL 1594de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_ROOT_PARAMETER_REVISION_ID__AZALIA_CODEC_ROOT_PARAMETER_REVISION_ID__SHIFT 0x00000000 1595de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT__AZALIA_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT_MASK 0xffffffffL 1596de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT__AZALIA_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT__SHIFT 0x00000000 1597de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__AZALIA_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID_MASK 0xffffffffL 1598de2bdb3dSTom St Denis #define AZALIA_F2_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__AZALIA_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__SHIFT 0x00000000 1599de2bdb3dSTom St Denis #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE_MASK 0x00000003L 1600de2bdb3dSTom St Denis #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE__SHIFT 0x00000000 1601de2bdb3dSTom St Denis #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER_MASK 0x0000003cL 1602de2bdb3dSTom St Denis #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER__SHIFT 0x00000002 1603de2bdb3dSTom St Denis #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_MASK 0x00000003L 1604de2bdb3dSTom St Denis #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN_MASK 0x00000004L 1605de2bdb3dSTom St Denis #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN__SHIFT 0x00000002 1606de2bdb3dSTom St Denis #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY__SHIFT 0x00000000 1607de2bdb3dSTom St Denis #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_MASK 0x00000078L 1608de2bdb3dSTom St Denis #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN_MASK 0x00000080L 1609de2bdb3dSTom St Denis #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN__SHIFT 0x00000007 1610de2bdb3dSTom St Denis #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH__SHIFT 0x00000003 1611de2bdb3dSTom St Denis #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_MASK 0x0000003fL 1612de2bdb3dSTom St Denis #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x00000040L 1613de2bdb3dSTom St Denis #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x00000006 1614de2bdb3dSTom St Denis #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY__SHIFT 0x00000000 1615de2bdb3dSTom St Denis #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK 0x0000000fL 1616de2bdb3dSTom St Denis #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x00000010L 1617de2bdb3dSTom St Denis #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x00000004 1618de2bdb3dSTom St Denis #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT 0x00000000 1619de2bdb3dSTom St Denis #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_MASK 0x00000060L 1620de2bdb3dSTom St Denis #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A__SHIFT 0x00000005 1621de2bdb3dSTom St Denis #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID_MASK 0x00000080L 1622de2bdb3dSTom St Denis #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID__SHIFT 0x00000007 1623de2bdb3dSTom St Denis #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO_MASK 0x00000010L 1624de2bdb3dSTom St Denis #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO__SHIFT 0x00000004 1625de2bdb3dSTom St Denis #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF_MASK 0x0000000fL 1626de2bdb3dSTom St Denis #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF__SHIFT 0x00000000 1627de2bdb3dSTom St Denis #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L_MASK 0x0000000fL 1628de2bdb3dSTom St Denis #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L__SHIFT 0x00000000 1629de2bdb3dSTom St Denis #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R_MASK 0x000000f0L 1630de2bdb3dSTom St Denis #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R__SHIFT 0x00000004 1631de2bdb3dSTom St Denis #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2_MASK 0x0000000fL 1632de2bdb3dSTom St Denis #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2__SHIFT 0x00000000 1633de2bdb3dSTom St Denis #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3_MASK 0x000000f0L 1634de2bdb3dSTom St Denis #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3__SHIFT 0x00000004 1635de2bdb3dSTom St Denis #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4_MASK 0x0000000fL 1636de2bdb3dSTom St Denis #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4__SHIFT 0x00000000 1637de2bdb3dSTom St Denis #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5_MASK 0x000000f0L 1638de2bdb3dSTom St Denis #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5__SHIFT 0x00000004 1639de2bdb3dSTom St Denis #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6_MASK 0x0000000fL 1640de2bdb3dSTom St Denis #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6__SHIFT 0x00000000 1641de2bdb3dSTom St Denis #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7_MASK 0x000000f0L 1642de2bdb3dSTom St Denis #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7__SHIFT 0x00000004 1643de2bdb3dSTom St Denis #define AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK 0x00007f00L 1644de2bdb3dSTom St Denis #define AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT 0x00000008 1645de2bdb3dSTom St Denis #define AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK 0x00ff0000L 1646de2bdb3dSTom St Denis #define AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT 0x00000010 1647de2bdb3dSTom St Denis #define AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK 0x0000007fL 1648de2bdb3dSTom St Denis #define AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT 0x00000000 1649de2bdb3dSTom St Denis #define AZALIA_GLOBAL_CAPABILITIES__NUMBER_OF_SERIAL_DATA_OUTPUT_SIGNALS_MASK 0x00000006L 1650de2bdb3dSTom St Denis #define AZALIA_GLOBAL_CAPABILITIES__NUMBER_OF_SERIAL_DATA_OUTPUT_SIGNALS__SHIFT 0x00000001 1651de2bdb3dSTom St Denis #define AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK 0x00000001L 1652de2bdb3dSTom St Denis #define AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT 0x00000000 1653de2bdb3dSTom St Denis #define AZALIA_OUTPUT_PAYLOAD_CAPABILITY__OUTPUT_PAYLOAD_CAPABILITY_MASK 0x0000ffffL 1654de2bdb3dSTom St Denis #define AZALIA_OUTPUT_PAYLOAD_CAPABILITY__OUTPUT_PAYLOAD_CAPABILITY__SHIFT 0x00000000 1655de2bdb3dSTom St Denis #define AZALIA_OUTPUT_PAYLOAD_CAPABILITY__OUTSTRMPAY_MASK 0xffff0000L 1656de2bdb3dSTom St Denis #define AZALIA_OUTPUT_PAYLOAD_CAPABILITY__OUTSTRMPAY__SHIFT 0x00000010 1657de2bdb3dSTom St Denis #define AZALIA_OUTPUT_STREAM_ARBITER_CONTROL__LATENCY_HIDING_LEVEL_MASK 0x000000ffL 1658de2bdb3dSTom St Denis #define AZALIA_OUTPUT_STREAM_ARBITER_CONTROL__LATENCY_HIDING_LEVEL__SHIFT 0x00000000 1659de2bdb3dSTom St Denis #define AZALIA_OUTPUT_STREAM_ARBITER_CONTROL__SYS_MEM_ACTIVE_ENABLE_MASK 0x00000100L 1660de2bdb3dSTom St Denis #define AZALIA_OUTPUT_STREAM_ARBITER_CONTROL__SYS_MEM_ACTIVE_ENABLE__SHIFT 0x00000008 1661de2bdb3dSTom St Denis #define AZALIA_RIRB_AND_DP_CONTROL__DP_DMA_NON_SNOOP_MASK 0x00000010L 1662de2bdb3dSTom St Denis #define AZALIA_RIRB_AND_DP_CONTROL__DP_DMA_NON_SNOOP__SHIFT 0x00000004 1663de2bdb3dSTom St Denis #define AZALIA_RIRB_AND_DP_CONTROL__RIRB_NON_SNOOP_MASK 0x00000001L 1664de2bdb3dSTom St Denis #define AZALIA_RIRB_AND_DP_CONTROL__RIRB_NON_SNOOP__SHIFT 0x00000000 1665de2bdb3dSTom St Denis #define AZALIA_SCLK_CONTROL__AUDIO_SCLK_CONTROL_MASK 0x00000030L 1666de2bdb3dSTom St Denis #define AZALIA_SCLK_CONTROL__AUDIO_SCLK_CONTROL__SHIFT 0x00000004 1667de2bdb3dSTom St Denis #define AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK 0xffffffffL 1668de2bdb3dSTom St Denis #define AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT 0x00000000 1669de2bdb3dSTom St Denis #define AZALIA_STREAM_DEBUG__STREAM_DEBUG_DATA_MASK 0xffffffffL 1670de2bdb3dSTom St Denis #define AZALIA_STREAM_DEBUG__STREAM_DEBUG_DATA__SHIFT 0x00000000 1671de2bdb3dSTom St Denis #define AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK 0x000000ffL 1672de2bdb3dSTom St Denis #define AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT 0x00000000 1673de2bdb3dSTom St Denis #define AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK 0x00000100L 1674de2bdb3dSTom St Denis #define AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT 0x00000008 1675de2bdb3dSTom St Denis #define AZALIA_UNDERFLOW_FILLER_SAMPLE__AZALIA_UNDERFLOW_FILLER_SAMPLE_MASK 0xffffffffL 1676de2bdb3dSTom St Denis #define AZALIA_UNDERFLOW_FILLER_SAMPLE__AZALIA_UNDERFLOW_FILLER_SAMPLE__SHIFT 0x00000000 1677de2bdb3dSTom St Denis #define AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK 0xffffffffL 1678de2bdb3dSTom St Denis #define AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT 0x00000000 1679de2bdb3dSTom St Denis #define AZ_TEST_DEBUG_DATA__AZ_TEST_DEBUG_DATA_MASK 0xffffffffL 1680de2bdb3dSTom St Denis #define AZ_TEST_DEBUG_DATA__AZ_TEST_DEBUG_DATA__SHIFT 0x00000000 1681de2bdb3dSTom St Denis #define AZ_TEST_DEBUG_INDEX__AZ_TEST_DEBUG_INDEX_MASK 0x000000ffL 1682de2bdb3dSTom St Denis #define AZ_TEST_DEBUG_INDEX__AZ_TEST_DEBUG_INDEX__SHIFT 0x00000000 1683de2bdb3dSTom St Denis #define AZ_TEST_DEBUG_INDEX__AZ_TEST_DEBUG_WRITE_EN_MASK 0x00000100L 1684de2bdb3dSTom St Denis #define AZ_TEST_DEBUG_INDEX__AZ_TEST_DEBUG_WRITE_EN__SHIFT 0x00000008 1685de2bdb3dSTom St Denis #define BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_CALC_FINAL_DUTY_CYCLE_EN_MASK 0x00000008L 1686de2bdb3dSTom St Denis #define BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_CALC_FINAL_DUTY_CYCLE_EN__SHIFT 0x00000003 1687de2bdb3dSTom St Denis #define BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_LEVEL_EN_MASK 0x00000004L 1688de2bdb3dSTom St Denis #define BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_LEVEL_EN__SHIFT 0x00000002 1689de2bdb3dSTom St Denis #define BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_STEP_SIZE_MASK 0xffff0000L 1690de2bdb3dSTom St Denis #define BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_STEP_SIZE__SHIFT 0x00000010 1691de2bdb3dSTom St Denis #define BL1_PWM_ABM_CNTL__BL1_PWM_USE_ABM_EN_MASK 0x00000001L 1692de2bdb3dSTom St Denis #define BL1_PWM_ABM_CNTL__BL1_PWM_USE_ABM_EN__SHIFT 0x00000000 1693de2bdb3dSTom St Denis #define BL1_PWM_ABM_CNTL__BL1_PWM_USE_AMBIENT_LEVEL_EN_MASK 0x00000002L 1694de2bdb3dSTom St Denis #define BL1_PWM_ABM_CNTL__BL1_PWM_USE_AMBIENT_LEVEL_EN__SHIFT 0x00000001 1695de2bdb3dSTom St Denis #define BL1_PWM_AMBIENT_LIGHT_LEVEL__BL1_PWM_AMBIENT_LIGHT_LEVEL_MASK 0x0001ffffL 1696de2bdb3dSTom St Denis #define BL1_PWM_AMBIENT_LIGHT_LEVEL__BL1_PWM_AMBIENT_LIGHT_LEVEL__SHIFT 0x00000000 1697de2bdb3dSTom St Denis #define BL1_PWM_BL_UPDATE_SAMPLE_RATE__ABM1_HGLS_REG_LOCK_MASK 0x80000000L 1698de2bdb3dSTom St Denis #define BL1_PWM_BL_UPDATE_SAMPLE_RATE__ABM1_HGLS_REG_LOCK__SHIFT 0x0000001f 1699de2bdb3dSTom St Denis #define BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET_MASK 0x00ff0000L 1700de2bdb3dSTom St Denis #define BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET__SHIFT 0x00000010 1701de2bdb3dSTom St Denis #define BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_RESET_SAMPLE_RATE_FRAME_COUNTER_MASK 0x00000002L 1702de2bdb3dSTom St Denis #define BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_RESET_SAMPLE_RATE_FRAME_COUNTER__SHIFT 0x00000001 1703de2bdb3dSTom St Denis #define BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_COUNT_EN_MASK 0x00000001L 1704de2bdb3dSTom St Denis #define BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_COUNT_EN__SHIFT 0x00000000 1705de2bdb3dSTom St Denis #define BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_FRAME_COUNT_MASK 0x0000ff00L 1706de2bdb3dSTom St Denis #define BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_FRAME_COUNT__SHIFT 0x00000008 1707de2bdb3dSTom St Denis #define BL1_PWM_CURRENT_ABM_LEVEL__BL1_PWM_CURRENT_ABM_LEVEL_MASK 0x0001ffffL 1708de2bdb3dSTom St Denis #define BL1_PWM_CURRENT_ABM_LEVEL__BL1_PWM_CURRENT_ABM_LEVEL__SHIFT 0x00000000 1709de2bdb3dSTom St Denis #define BL1_PWM_FINAL_DUTY_CYCLE__BL1_PWM_FINAL_DUTY_CYCLE_MASK 0x0001ffffL 1710de2bdb3dSTom St Denis #define BL1_PWM_FINAL_DUTY_CYCLE__BL1_PWM_FINAL_DUTY_CYCLE__SHIFT 0x00000000 1711de2bdb3dSTom St Denis #define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_FRAME_START_DISP_SEL_MASK 0x000e0000L 1712de2bdb3dSTom St Denis #define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_FRAME_START_DISP_SEL__SHIFT 0x00000011 1713de2bdb3dSTom St Denis #define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_IGNORE_MASTER_LOCK_EN_MASK 0x80000000L 1714de2bdb3dSTom St Denis #define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_IGNORE_MASTER_LOCK_EN__SHIFT 0x0000001f 1715de2bdb3dSTom St Denis #define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_READBACK_DB_REG_VALUE_EN_MASK 0x01000000L 1716de2bdb3dSTom St Denis #define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_READBACK_DB_REG_VALUE_EN__SHIFT 0x00000018 1717de2bdb3dSTom St Denis #define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_LOCK_MASK 0x00000001L 1718de2bdb3dSTom St Denis #define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_LOCK__SHIFT 0x00000000 1719de2bdb3dSTom St Denis #define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_UPDATE_PENDING_MASK 0x00000100L 1720de2bdb3dSTom St Denis #define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_UPDATE_PENDING__SHIFT 0x00000008 1721de2bdb3dSTom St Denis #define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_UPDATE_AT_FRAME_START_MASK 0x00010000L 1722de2bdb3dSTom St Denis #define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_UPDATE_AT_FRAME_START__SHIFT 0x00000010 1723de2bdb3dSTom St Denis #define BL1_PWM_MINIMUM_DUTY_CYCLE__BL1_PWM_MINIMUM_DUTY_CYCLE_MASK 0x0001ffffL 1724de2bdb3dSTom St Denis #define BL1_PWM_MINIMUM_DUTY_CYCLE__BL1_PWM_MINIMUM_DUTY_CYCLE__SHIFT 0x00000000 1725de2bdb3dSTom St Denis #define BL1_PWM_TARGET_ABM_LEVEL__BL1_PWM_TARGET_ABM_LEVEL_MASK 0x0001ffffL 1726de2bdb3dSTom St Denis #define BL1_PWM_TARGET_ABM_LEVEL__BL1_PWM_TARGET_ABM_LEVEL__SHIFT 0x00000000 1727de2bdb3dSTom St Denis #define BL1_PWM_USER_LEVEL__BL1_PWM_USER_LEVEL_MASK 0x0001ffffL 1728de2bdb3dSTom St Denis #define BL1_PWM_USER_LEVEL__BL1_PWM_USER_LEVEL__SHIFT 0x00000000 1729de2bdb3dSTom St Denis #define BL_PWM_CNTL2__BL_PWM_OVERRIDE_BL_OUT_ENABLE_MASK 0x40000000L 1730de2bdb3dSTom St Denis #define BL_PWM_CNTL2__BL_PWM_OVERRIDE_BL_OUT_ENABLE__SHIFT 0x0000001e 1731de2bdb3dSTom St Denis #define BL_PWM_CNTL2__BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN_MASK 0x80000000L 1732de2bdb3dSTom St Denis #define BL_PWM_CNTL2__BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN__SHIFT 0x0000001f 1733de2bdb3dSTom St Denis #define BL_PWM_CNTL2__BL_PWM_POST_FRAME_START_DELAY_BEFORE_UPDATE_MASK 0x0000ffffL 1734de2bdb3dSTom St Denis #define BL_PWM_CNTL2__BL_PWM_POST_FRAME_START_DELAY_BEFORE_UPDATE__SHIFT 0x00000000 1735de2bdb3dSTom St Denis #define BL_PWM_CNTL2__DBG_BL_PWM_INPUT_REFCLK_SELECT_MASK 0x30000000L 1736de2bdb3dSTom St Denis #define BL_PWM_CNTL2__DBG_BL_PWM_INPUT_REFCLK_SELECT__SHIFT 0x0000001c 1737de2bdb3dSTom St Denis #define BL_PWM_CNTL__BL_ACTIVE_INT_FRAC_CNT_MASK 0x0000ffffL 1738de2bdb3dSTom St Denis #define BL_PWM_CNTL__BL_ACTIVE_INT_FRAC_CNT__SHIFT 0x00000000 1739de2bdb3dSTom St Denis #define BL_PWM_CNTL__BL_PWM_EN_MASK 0x80000000L 1740de2bdb3dSTom St Denis #define BL_PWM_CNTL__BL_PWM_EN__SHIFT 0x0000001f 1741de2bdb3dSTom St Denis #define BL_PWM_CNTL__BL_PWM_FRACTIONAL_EN_MASK 0x40000000L 1742de2bdb3dSTom St Denis #define BL_PWM_CNTL__BL_PWM_FRACTIONAL_EN__SHIFT 0x0000001e 1743de2bdb3dSTom St Denis #define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_FRAME_START_DISP_SEL_MASK 0x000e0000L 1744de2bdb3dSTom St Denis #define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_FRAME_START_DISP_SEL__SHIFT 0x00000011 1745de2bdb3dSTom St Denis #define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN_MASK 0x80000000L 1746de2bdb3dSTom St Denis #define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN__SHIFT 0x0000001f 1747de2bdb3dSTom St Denis #define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN_MASK 0x01000000L 1748de2bdb3dSTom St Denis #define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN__SHIFT 0x00000018 1749de2bdb3dSTom St Denis #define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_REG_LOCK_MASK 0x00000001L 1750de2bdb3dSTom St Denis #define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_REG_LOCK__SHIFT 0x00000000 1751de2bdb3dSTom St Denis #define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_REG_UPDATE_PENDING_MASK 0x00000100L 1752de2bdb3dSTom St Denis #define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_REG_UPDATE_PENDING__SHIFT 0x00000008 1753de2bdb3dSTom St Denis #define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_UPDATE_AT_FRAME_START_MASK 0x00010000L 1754de2bdb3dSTom St Denis #define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_UPDATE_AT_FRAME_START__SHIFT 0x00000010 1755de2bdb3dSTom St Denis #define BL_PWM_PERIOD_CNTL__BL_PWM_PERIOD_BITCNT_MASK 0x000f0000L 1756de2bdb3dSTom St Denis #define BL_PWM_PERIOD_CNTL__BL_PWM_PERIOD_BITCNT__SHIFT 0x00000010 1757de2bdb3dSTom St Denis #define BL_PWM_PERIOD_CNTL__BL_PWM_PERIOD_MASK 0x0000ffffL 1758de2bdb3dSTom St Denis #define BL_PWM_PERIOD_CNTL__BL_PWM_PERIOD__SHIFT 0x00000000 1759de2bdb3dSTom St Denis #define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_COMPLETE_MASK 0x10000000L 1760de2bdb3dSTom St Denis #define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_COMPLETE__SHIFT 0x0000001c 1761de2bdb3dSTom St Denis #define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_DACADJ_EN_MASK 0x00000004L 1762de2bdb3dSTom St Denis #define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_DACADJ_EN__SHIFT 0x00000002 1763de2bdb3dSTom St Denis #define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_EN_MASK 0x00000002L 1764de2bdb3dSTom St Denis #define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_EN__SHIFT 0x00000001 1765de2bdb3dSTom St Denis #define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_INITB_MASK 0x00000001L 1766de2bdb3dSTom St Denis #define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_INITB__SHIFT 0x00000000 1767de2bdb3dSTom St Denis #define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_MASK_MASK 0x00700000L 1768de2bdb3dSTom St Denis #define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_MASK__SHIFT 0x00000014 1769de2bdb3dSTom St Denis #define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_WAIT_ADJUST_MASK 0x00003ff0L 1770de2bdb3dSTom St Denis #define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_WAIT_ADJUST__SHIFT 0x00000004 1771de2bdb3dSTom St Denis #define BPHYC_DAC_MACRO_CNTL__BPHYC_DAC_ANALOG_MONITOR_MASK 0x0f000000L 1772de2bdb3dSTom St Denis #define BPHYC_DAC_MACRO_CNTL__BPHYC_DAC_ANALOG_MONITOR__SHIFT 0x00000018 1773de2bdb3dSTom St Denis #define BPHYC_DAC_MACRO_CNTL__BPHYC_DAC_BANDGAP_ADJUSTMENT_MASK 0x003f0000L 1774de2bdb3dSTom St Denis #define BPHYC_DAC_MACRO_CNTL__BPHYC_DAC_BANDGAP_ADJUSTMENT__SHIFT 0x00000010 1775de2bdb3dSTom St Denis #define BPHYC_DAC_MACRO_CNTL__BPHYC_DAC_COREMON_MASK 0x10000000L 1776de2bdb3dSTom St Denis #define BPHYC_DAC_MACRO_CNTL__BPHYC_DAC_COREMON__SHIFT 0x0000001c 1777de2bdb3dSTom St Denis #define BPHYC_DAC_MACRO_CNTL__BPHYC_DAC_WHITE_FINE_CONTROL_MASK 0x00003f00L 1778de2bdb3dSTom St Denis #define BPHYC_DAC_MACRO_CNTL__BPHYC_DAC_WHITE_FINE_CONTROL__SHIFT 0x00000008 1779de2bdb3dSTom St Denis #define BPHYC_DAC_MACRO_CNTL__BPHYC_DAC_WHITE_LEVEL_MASK 0x00000003L 1780de2bdb3dSTom St Denis #define BPHYC_DAC_MACRO_CNTL__BPHYC_DAC_WHITE_LEVEL__SHIFT 0x00000000 1781de2bdb3dSTom St Denis #define CC_DC_PIPE_DIS__DC_PIPE_DIS_MASK 0x0000007eL 1782de2bdb3dSTom St Denis #define CC_DC_PIPE_DIS__DC_PIPE_DIS__SHIFT 0x00000001 1783de2bdb3dSTom St Denis #define CC_RCU_DC_AUDIO_PORT_CONNECTIVITY__PORT_CONNECTIVITY_MASK 0x00000007L 1784de2bdb3dSTom St Denis #define CC_RCU_DC_AUDIO_PORT_CONNECTIVITY__PORT_CONNECTIVITY_OVERRIDE_ENABLE_MASK 0x00000010L 1785de2bdb3dSTom St Denis #define CC_RCU_DC_AUDIO_PORT_CONNECTIVITY__PORT_CONNECTIVITY_OVERRIDE_ENABLE__SHIFT 0x00000004 1786de2bdb3dSTom St Denis #define CC_RCU_DC_AUDIO_PORT_CONNECTIVITY__PORT_CONNECTIVITY__SHIFT 0x00000000 1787de2bdb3dSTom St Denis #define COMM_MATRIXA_TRANS_C11_C12__COMM_MATRIXA_TRANS_C11_MASK 0x0000ffffL 1788de2bdb3dSTom St Denis #define COMM_MATRIXA_TRANS_C11_C12__COMM_MATRIXA_TRANS_C11__SHIFT 0x00000000 1789de2bdb3dSTom St Denis #define COMM_MATRIXA_TRANS_C11_C12__COMM_MATRIXA_TRANS_C12_MASK 0xffff0000L 1790de2bdb3dSTom St Denis #define COMM_MATRIXA_TRANS_C11_C12__COMM_MATRIXA_TRANS_C12__SHIFT 0x00000010 1791de2bdb3dSTom St Denis #define COMM_MATRIXA_TRANS_C13_C14__COMM_MATRIXA_TRANS_C13_MASK 0x0000ffffL 1792de2bdb3dSTom St Denis #define COMM_MATRIXA_TRANS_C13_C14__COMM_MATRIXA_TRANS_C13__SHIFT 0x00000000 1793de2bdb3dSTom St Denis #define COMM_MATRIXA_TRANS_C13_C14__COMM_MATRIXA_TRANS_C14_MASK 0xffff0000L 1794de2bdb3dSTom St Denis #define COMM_MATRIXA_TRANS_C13_C14__COMM_MATRIXA_TRANS_C14__SHIFT 0x00000010 1795de2bdb3dSTom St Denis #define COMM_MATRIXA_TRANS_C21_C22__COMM_MATRIXA_TRANS_C21_MASK 0x0000ffffL 1796de2bdb3dSTom St Denis #define COMM_MATRIXA_TRANS_C21_C22__COMM_MATRIXA_TRANS_C21__SHIFT 0x00000000 1797de2bdb3dSTom St Denis #define COMM_MATRIXA_TRANS_C21_C22__COMM_MATRIXA_TRANS_C22_MASK 0xffff0000L 1798de2bdb3dSTom St Denis #define COMM_MATRIXA_TRANS_C21_C22__COMM_MATRIXA_TRANS_C22__SHIFT 0x00000010 1799de2bdb3dSTom St Denis #define COMM_MATRIXA_TRANS_C23_C24__COMM_MATRIXA_TRANS_C23_MASK 0x0000ffffL 1800de2bdb3dSTom St Denis #define COMM_MATRIXA_TRANS_C23_C24__COMM_MATRIXA_TRANS_C23__SHIFT 0x00000000 1801de2bdb3dSTom St Denis #define COMM_MATRIXA_TRANS_C23_C24__COMM_MATRIXA_TRANS_C24_MASK 0xffff0000L 1802de2bdb3dSTom St Denis #define COMM_MATRIXA_TRANS_C23_C24__COMM_MATRIXA_TRANS_C24__SHIFT 0x00000010 1803de2bdb3dSTom St Denis #define COMM_MATRIXA_TRANS_C31_C32__COMM_MATRIXA_TRANS_C31_MASK 0x0000ffffL 1804de2bdb3dSTom St Denis #define COMM_MATRIXA_TRANS_C31_C32__COMM_MATRIXA_TRANS_C31__SHIFT 0x00000000 1805de2bdb3dSTom St Denis #define COMM_MATRIXA_TRANS_C31_C32__COMM_MATRIXA_TRANS_C32_MASK 0xffff0000L 1806de2bdb3dSTom St Denis #define COMM_MATRIXA_TRANS_C31_C32__COMM_MATRIXA_TRANS_C32__SHIFT 0x00000010 1807de2bdb3dSTom St Denis #define COMM_MATRIXA_TRANS_C33_C34__COMM_MATRIXA_TRANS_C33_MASK 0x0000ffffL 1808de2bdb3dSTom St Denis #define COMM_MATRIXA_TRANS_C33_C34__COMM_MATRIXA_TRANS_C33__SHIFT 0x00000000 1809de2bdb3dSTom St Denis #define COMM_MATRIXA_TRANS_C33_C34__COMM_MATRIXA_TRANS_C34_MASK 0xffff0000L 1810de2bdb3dSTom St Denis #define COMM_MATRIXA_TRANS_C33_C34__COMM_MATRIXA_TRANS_C34__SHIFT 0x00000010 1811de2bdb3dSTom St Denis #define COMM_MATRIXB_TRANS_C11_C12__COMM_MATRIXB_TRANS_C11_MASK 0x0000ffffL 1812de2bdb3dSTom St Denis #define COMM_MATRIXB_TRANS_C11_C12__COMM_MATRIXB_TRANS_C11__SHIFT 0x00000000 1813de2bdb3dSTom St Denis #define COMM_MATRIXB_TRANS_C11_C12__COMM_MATRIXB_TRANS_C12_MASK 0xffff0000L 1814de2bdb3dSTom St Denis #define COMM_MATRIXB_TRANS_C11_C12__COMM_MATRIXB_TRANS_C12__SHIFT 0x00000010 1815de2bdb3dSTom St Denis #define COMM_MATRIXB_TRANS_C13_C14__COMM_MATRIXB_TRANS_C13_MASK 0x0000ffffL 1816de2bdb3dSTom St Denis #define COMM_MATRIXB_TRANS_C13_C14__COMM_MATRIXB_TRANS_C13__SHIFT 0x00000000 1817de2bdb3dSTom St Denis #define COMM_MATRIXB_TRANS_C13_C14__COMM_MATRIXB_TRANS_C14_MASK 0xffff0000L 1818de2bdb3dSTom St Denis #define COMM_MATRIXB_TRANS_C13_C14__COMM_MATRIXB_TRANS_C14__SHIFT 0x00000010 1819de2bdb3dSTom St Denis #define COMM_MATRIXB_TRANS_C21_C22__COMM_MATRIXB_TRANS_C21_MASK 0x0000ffffL 1820de2bdb3dSTom St Denis #define COMM_MATRIXB_TRANS_C21_C22__COMM_MATRIXB_TRANS_C21__SHIFT 0x00000000 1821de2bdb3dSTom St Denis #define COMM_MATRIXB_TRANS_C21_C22__COMM_MATRIXB_TRANS_C22_MASK 0xffff0000L 1822de2bdb3dSTom St Denis #define COMM_MATRIXB_TRANS_C21_C22__COMM_MATRIXB_TRANS_C22__SHIFT 0x00000010 1823de2bdb3dSTom St Denis #define COMM_MATRIXB_TRANS_C23_C24__COMM_MATRIXB_TRANS_C23_MASK 0x0000ffffL 1824de2bdb3dSTom St Denis #define COMM_MATRIXB_TRANS_C23_C24__COMM_MATRIXB_TRANS_C23__SHIFT 0x00000000 1825de2bdb3dSTom St Denis #define COMM_MATRIXB_TRANS_C23_C24__COMM_MATRIXB_TRANS_C24_MASK 0xffff0000L 1826de2bdb3dSTom St Denis #define COMM_MATRIXB_TRANS_C23_C24__COMM_MATRIXB_TRANS_C24__SHIFT 0x00000010 1827de2bdb3dSTom St Denis #define COMM_MATRIXB_TRANS_C31_C32__COMM_MATRIXB_TRANS_C31_MASK 0x0000ffffL 1828de2bdb3dSTom St Denis #define COMM_MATRIXB_TRANS_C31_C32__COMM_MATRIXB_TRANS_C31__SHIFT 0x00000000 1829de2bdb3dSTom St Denis #define COMM_MATRIXB_TRANS_C31_C32__COMM_MATRIXB_TRANS_C32_MASK 0xffff0000L 1830de2bdb3dSTom St Denis #define COMM_MATRIXB_TRANS_C31_C32__COMM_MATRIXB_TRANS_C32__SHIFT 0x00000010 1831de2bdb3dSTom St Denis #define COMM_MATRIXB_TRANS_C33_C34__COMM_MATRIXB_TRANS_C33_MASK 0x0000ffffL 1832de2bdb3dSTom St Denis #define COMM_MATRIXB_TRANS_C33_C34__COMM_MATRIXB_TRANS_C33__SHIFT 0x00000000 1833de2bdb3dSTom St Denis #define COMM_MATRIXB_TRANS_C33_C34__COMM_MATRIXB_TRANS_C34_MASK 0xffff0000L 1834de2bdb3dSTom St Denis #define COMM_MATRIXB_TRANS_C33_C34__COMM_MATRIXB_TRANS_C34__SHIFT 0x00000010 1835de2bdb3dSTom St Denis #define CRT00__H_TOTAL_MASK 0x000000ffL 1836de2bdb3dSTom St Denis #define CRT00__H_TOTAL__SHIFT 0x00000000 1837de2bdb3dSTom St Denis #define CRT01__H_DISP_END_MASK 0x000000ffL 1838de2bdb3dSTom St Denis #define CRT01__H_DISP_END__SHIFT 0x00000000 1839de2bdb3dSTom St Denis #define CRT02__H_BLANK_START_MASK 0x000000ffL 1840de2bdb3dSTom St Denis #define CRT02__H_BLANK_START__SHIFT 0x00000000 1841de2bdb3dSTom St Denis #define CRT03__CR10CR11_R_DIS_B_MASK 0x00000080L 1842de2bdb3dSTom St Denis #define CRT03__CR10CR11_R_DIS_B__SHIFT 0x00000007 1843de2bdb3dSTom St Denis #define CRT03__H_BLANK_END_MASK 0x0000001fL 1844de2bdb3dSTom St Denis #define CRT03__H_BLANK_END__SHIFT 0x00000000 1845de2bdb3dSTom St Denis #define CRT03__H_DE_SKEW_MASK 0x00000060L 1846de2bdb3dSTom St Denis #define CRT03__H_DE_SKEW__SHIFT 0x00000005 1847de2bdb3dSTom St Denis #define CRT04__H_SYNC_START_MASK 0x000000ffL 1848de2bdb3dSTom St Denis #define CRT04__H_SYNC_START__SHIFT 0x00000000 1849de2bdb3dSTom St Denis #define CRT05__H_BLANK_END_B5_MASK 0x00000080L 1850de2bdb3dSTom St Denis #define CRT05__H_BLANK_END_B5__SHIFT 0x00000007 1851de2bdb3dSTom St Denis #define CRT05__H_SYNC_END_MASK 0x0000001fL 1852de2bdb3dSTom St Denis #define CRT05__H_SYNC_END__SHIFT 0x00000000 1853de2bdb3dSTom St Denis #define CRT05__H_SYNC_SKEW_MASK 0x00000060L 1854de2bdb3dSTom St Denis #define CRT05__H_SYNC_SKEW__SHIFT 0x00000005 1855de2bdb3dSTom St Denis #define CRT06__V_TOTAL_MASK 0x000000ffL 1856de2bdb3dSTom St Denis #define CRT06__V_TOTAL__SHIFT 0x00000000 1857de2bdb3dSTom St Denis #define CRT07__LINE_CMP_B8_MASK 0x00000010L 1858de2bdb3dSTom St Denis #define CRT07__LINE_CMP_B8__SHIFT 0x00000004 1859de2bdb3dSTom St Denis #define CRT07__V_BLANK_START_B8_MASK 0x00000008L 1860de2bdb3dSTom St Denis #define CRT07__V_BLANK_START_B8__SHIFT 0x00000003 1861de2bdb3dSTom St Denis #define CRT07__V_DISP_END_B8_MASK 0x00000002L 1862de2bdb3dSTom St Denis #define CRT07__V_DISP_END_B8__SHIFT 0x00000001 1863de2bdb3dSTom St Denis #define CRT07__V_DISP_END_B9_MASK 0x00000040L 1864de2bdb3dSTom St Denis #define CRT07__V_DISP_END_B9__SHIFT 0x00000006 1865de2bdb3dSTom St Denis #define CRT07__V_SYNC_START_B8_MASK 0x00000004L 1866de2bdb3dSTom St Denis #define CRT07__V_SYNC_START_B8__SHIFT 0x00000002 1867de2bdb3dSTom St Denis #define CRT07__V_SYNC_START_B9_MASK 0x00000080L 1868de2bdb3dSTom St Denis #define CRT07__V_SYNC_START_B9__SHIFT 0x00000007 1869de2bdb3dSTom St Denis #define CRT07__V_TOTAL_B8_MASK 0x00000001L 1870de2bdb3dSTom St Denis #define CRT07__V_TOTAL_B8__SHIFT 0x00000000 1871de2bdb3dSTom St Denis #define CRT07__V_TOTAL_B9_MASK 0x00000020L 1872de2bdb3dSTom St Denis #define CRT07__V_TOTAL_B9__SHIFT 0x00000005 1873de2bdb3dSTom St Denis #define CRT08__BYTE_PAN_MASK 0x00000060L 1874de2bdb3dSTom St Denis #define CRT08__BYTE_PAN__SHIFT 0x00000005 1875de2bdb3dSTom St Denis #define CRT08__ROW_SCAN_START_MASK 0x0000001fL 1876de2bdb3dSTom St Denis #define CRT08__ROW_SCAN_START__SHIFT 0x00000000 1877de2bdb3dSTom St Denis #define CRT09__DOUBLE_CHAR_HEIGHT_MASK 0x00000080L 1878de2bdb3dSTom St Denis #define CRT09__DOUBLE_CHAR_HEIGHT__SHIFT 0x00000007 1879de2bdb3dSTom St Denis #define CRT09__LINE_CMP_B9_MASK 0x00000040L 1880de2bdb3dSTom St Denis #define CRT09__LINE_CMP_B9__SHIFT 0x00000006 1881de2bdb3dSTom St Denis #define CRT09__MAX_ROW_SCAN_MASK 0x0000001fL 1882de2bdb3dSTom St Denis #define CRT09__MAX_ROW_SCAN__SHIFT 0x00000000 1883de2bdb3dSTom St Denis #define CRT09__V_BLANK_START_B9_MASK 0x00000020L 1884de2bdb3dSTom St Denis #define CRT09__V_BLANK_START_B9__SHIFT 0x00000005 1885de2bdb3dSTom St Denis #define CRT0A__CURSOR_DISABLE_MASK 0x00000020L 1886de2bdb3dSTom St Denis #define CRT0A__CURSOR_DISABLE__SHIFT 0x00000005 1887de2bdb3dSTom St Denis #define CRT0A__CURSOR_START_MASK 0x0000001fL 1888de2bdb3dSTom St Denis #define CRT0A__CURSOR_START__SHIFT 0x00000000 1889de2bdb3dSTom St Denis #define CRT0B__CURSOR_END_MASK 0x0000001fL 1890de2bdb3dSTom St Denis #define CRT0B__CURSOR_END__SHIFT 0x00000000 1891de2bdb3dSTom St Denis #define CRT0B__CURSOR_SKEW_MASK 0x00000060L 1892de2bdb3dSTom St Denis #define CRT0B__CURSOR_SKEW__SHIFT 0x00000005 1893de2bdb3dSTom St Denis #define CRT0C__DISP_START_MASK 0x000000ffL 1894de2bdb3dSTom St Denis #define CRT0C__DISP_START__SHIFT 0x00000000 1895de2bdb3dSTom St Denis #define CRT0D__DISP_START_MASK 0x000000ffL 1896de2bdb3dSTom St Denis #define CRT0D__DISP_START__SHIFT 0x00000000 1897de2bdb3dSTom St Denis #define CRT0E__CURSOR_LOC_HI_MASK 0x000000ffL 1898de2bdb3dSTom St Denis #define CRT0E__CURSOR_LOC_HI__SHIFT 0x00000000 1899de2bdb3dSTom St Denis #define CRT0F__CURSOR_LOC_LO_MASK 0x000000ffL 1900de2bdb3dSTom St Denis #define CRT0F__CURSOR_LOC_LO__SHIFT 0x00000000 1901de2bdb3dSTom St Denis #define CRT10__V_SYNC_START_MASK 0x000000ffL 1902de2bdb3dSTom St Denis #define CRT10__V_SYNC_START__SHIFT 0x00000000 1903de2bdb3dSTom St Denis #define CRT11__C0T7_WR_ONLY_MASK 0x00000080L 1904de2bdb3dSTom St Denis #define CRT11__C0T7_WR_ONLY__SHIFT 0x00000007 1905de2bdb3dSTom St Denis #define CRT11__SEL5_REFRESH_CYC_MASK 0x00000040L 1906de2bdb3dSTom St Denis #define CRT11__SEL5_REFRESH_CYC__SHIFT 0x00000006 1907de2bdb3dSTom St Denis #define CRT11__V_INTR_CLR_MASK 0x00000010L 1908de2bdb3dSTom St Denis #define CRT11__V_INTR_CLR__SHIFT 0x00000004 1909de2bdb3dSTom St Denis #define CRT11__V_INTR_EN_MASK 0x00000020L 1910de2bdb3dSTom St Denis #define CRT11__V_INTR_EN__SHIFT 0x00000005 1911de2bdb3dSTom St Denis #define CRT11__V_SYNC_END_MASK 0x0000000fL 1912de2bdb3dSTom St Denis #define CRT11__V_SYNC_END__SHIFT 0x00000000 1913de2bdb3dSTom St Denis #define CRT12__V_DISP_END_MASK 0x000000ffL 1914de2bdb3dSTom St Denis #define CRT12__V_DISP_END__SHIFT 0x00000000 1915de2bdb3dSTom St Denis #define CRT13__DISP_PITCH_MASK 0x000000ffL 1916de2bdb3dSTom St Denis #define CRT13__DISP_PITCH__SHIFT 0x00000000 1917de2bdb3dSTom St Denis #define CRT14__ADDR_CNT_BY4_MASK 0x00000020L 1918de2bdb3dSTom St Denis #define CRT14__ADDR_CNT_BY4__SHIFT 0x00000005 1919de2bdb3dSTom St Denis #define CRT14__DOUBLE_WORD_MASK 0x00000040L 1920de2bdb3dSTom St Denis #define CRT14__DOUBLE_WORD__SHIFT 0x00000006 1921de2bdb3dSTom St Denis #define CRT14__UNDRLN_LOC_MASK 0x0000001fL 1922de2bdb3dSTom St Denis #define CRT14__UNDRLN_LOC__SHIFT 0x00000000 1923de2bdb3dSTom St Denis #define CRT15__V_BLANK_START_MASK 0x000000ffL 1924de2bdb3dSTom St Denis #define CRT15__V_BLANK_START__SHIFT 0x00000000 1925de2bdb3dSTom St Denis #define CRT16__V_BLANK_END_MASK 0x000000ffL 1926de2bdb3dSTom St Denis #define CRT16__V_BLANK_END__SHIFT 0x00000000 1927de2bdb3dSTom St Denis #define CRT17__ADDR_CNT_BY2_MASK 0x00000008L 1928de2bdb3dSTom St Denis #define CRT17__ADDR_CNT_BY2__SHIFT 0x00000003 1929de2bdb3dSTom St Denis #define CRT17__BYTE_MODE_MASK 0x00000040L 1930de2bdb3dSTom St Denis #define CRT17__BYTE_MODE__SHIFT 0x00000006 1931de2bdb3dSTom St Denis #define CRT17__CRTC_SYNC_EN_MASK 0x00000080L 1932de2bdb3dSTom St Denis #define CRT17__CRTC_SYNC_EN__SHIFT 0x00000007 1933de2bdb3dSTom St Denis #define CRT17__RA0_AS_A13B_MASK 0x00000001L 1934de2bdb3dSTom St Denis #define CRT17__RA0_AS_A13B__SHIFT 0x00000000 1935de2bdb3dSTom St Denis #define CRT17__RA1_AS_A14B_MASK 0x00000002L 1936de2bdb3dSTom St Denis #define CRT17__RA1_AS_A14B__SHIFT 0x00000001 1937de2bdb3dSTom St Denis #define CRT17__VCOUNT_BY2_MASK 0x00000004L 1938de2bdb3dSTom St Denis #define CRT17__VCOUNT_BY2__SHIFT 0x00000002 1939de2bdb3dSTom St Denis #define CRT17__WRAP_A15TOA0_MASK 0x00000020L 1940de2bdb3dSTom St Denis #define CRT17__WRAP_A15TOA0__SHIFT 0x00000005 1941de2bdb3dSTom St Denis #define CRT18__LINE_CMP_MASK 0x000000ffL 1942de2bdb3dSTom St Denis #define CRT18__LINE_CMP__SHIFT 0x00000000 1943de2bdb3dSTom St Denis #define CRT1E__GRPH_DEC_RD1_MASK 0x00000002L 1944de2bdb3dSTom St Denis #define CRT1E__GRPH_DEC_RD1__SHIFT 0x00000001 1945de2bdb3dSTom St Denis #define CRT1F__GRPH_DEC_RD0_MASK 0x000000ffL 1946de2bdb3dSTom St Denis #define CRT1F__GRPH_DEC_RD0__SHIFT 0x00000000 1947de2bdb3dSTom St Denis #define CRT22__GRPH_LATCH_DATA_MASK 0x000000ffL 1948de2bdb3dSTom St Denis #define CRT22__GRPH_LATCH_DATA__SHIFT 0x00000000 1949de2bdb3dSTom St Denis #define CRTC0_PIXEL_RATE_CNTL__CRTC0_ADD_PIXEL_MASK 0x00000100L 1950de2bdb3dSTom St Denis #define CRTC0_PIXEL_RATE_CNTL__CRTC0_ADD_PIXEL__SHIFT 0x00000008 1951de2bdb3dSTom St Denis #define CRTC0_PIXEL_RATE_CNTL__CRTC0_DISPOUT_ERROR_COUNT_MASK 0x0fff0000L 1952de2bdb3dSTom St Denis #define CRTC0_PIXEL_RATE_CNTL__CRTC0_DISPOUT_ERROR_COUNT__SHIFT 0x00000010 1953de2bdb3dSTom St Denis #define CRTC0_PIXEL_RATE_CNTL__CRTC0_DISPOUT_FIFO_ERROR_MASK 0x0000c000L 1954de2bdb3dSTom St Denis #define CRTC0_PIXEL_RATE_CNTL__CRTC0_DISPOUT_FIFO_ERROR__SHIFT 0x0000000e 1955de2bdb3dSTom St Denis #define CRTC0_PIXEL_RATE_CNTL__CRTC0_DROP_PIXEL_MASK 0x00000200L 1956de2bdb3dSTom St Denis #define CRTC0_PIXEL_RATE_CNTL__CRTC0_DROP_PIXEL__SHIFT 0x00000009 1957de2bdb3dSTom St Denis #define CRTC0_PIXEL_RATE_CNTL__CRTC0_PIXEL_RATE_SOURCE_MASK 0x00000003L 1958de2bdb3dSTom St Denis #define CRTC0_PIXEL_RATE_CNTL__CRTC0_PIXEL_RATE_SOURCE__SHIFT 0x00000000 1959de2bdb3dSTom St Denis #define CRTC0_PIXEL_RATE_CNTL__DP_DTO0_ENABLE_MASK 0x00000010L 1960de2bdb3dSTom St Denis #define CRTC0_PIXEL_RATE_CNTL__DP_DTO0_ENABLE__SHIFT 0x00000004 1961de2bdb3dSTom St Denis #define CRTC1_PIXEL_RATE_CNTL__CRTC1_ADD_PIXEL_MASK 0x00000100L 1962de2bdb3dSTom St Denis #define CRTC1_PIXEL_RATE_CNTL__CRTC1_ADD_PIXEL__SHIFT 0x00000008 1963de2bdb3dSTom St Denis #define CRTC1_PIXEL_RATE_CNTL__CRTC1_DISPOUT_ERROR_COUNT_MASK 0x0fff0000L 1964de2bdb3dSTom St Denis #define CRTC1_PIXEL_RATE_CNTL__CRTC1_DISPOUT_ERROR_COUNT__SHIFT 0x00000010 1965de2bdb3dSTom St Denis #define CRTC1_PIXEL_RATE_CNTL__CRTC1_DISPOUT_FIFO_ERROR_MASK 0x0000c000L 1966de2bdb3dSTom St Denis #define CRTC1_PIXEL_RATE_CNTL__CRTC1_DISPOUT_FIFO_ERROR__SHIFT 0x0000000e 1967de2bdb3dSTom St Denis #define CRTC1_PIXEL_RATE_CNTL__CRTC1_DROP_PIXEL_MASK 0x00000200L 1968de2bdb3dSTom St Denis #define CRTC1_PIXEL_RATE_CNTL__CRTC1_DROP_PIXEL__SHIFT 0x00000009 1969de2bdb3dSTom St Denis #define CRTC1_PIXEL_RATE_CNTL__CRTC1_PIXEL_RATE_SOURCE_MASK 0x00000003L 1970de2bdb3dSTom St Denis #define CRTC1_PIXEL_RATE_CNTL__CRTC1_PIXEL_RATE_SOURCE__SHIFT 0x00000000 1971de2bdb3dSTom St Denis #define CRTC1_PIXEL_RATE_CNTL__DP_DTO1_ENABLE_MASK 0x00000010L 1972de2bdb3dSTom St Denis #define CRTC1_PIXEL_RATE_CNTL__DP_DTO1_ENABLE__SHIFT 0x00000004 1973de2bdb3dSTom St Denis #define CRTC2_PIXEL_RATE_CNTL__CRTC2_ADD_PIXEL_MASK 0x00000100L 1974de2bdb3dSTom St Denis #define CRTC2_PIXEL_RATE_CNTL__CRTC2_ADD_PIXEL__SHIFT 0x00000008 1975de2bdb3dSTom St Denis #define CRTC2_PIXEL_RATE_CNTL__CRTC2_DISPOUT_ERROR_COUNT_MASK 0x0fff0000L 1976de2bdb3dSTom St Denis #define CRTC2_PIXEL_RATE_CNTL__CRTC2_DISPOUT_ERROR_COUNT__SHIFT 0x00000010 1977de2bdb3dSTom St Denis #define CRTC2_PIXEL_RATE_CNTL__CRTC2_DISPOUT_FIFO_ERROR_MASK 0x0000c000L 1978de2bdb3dSTom St Denis #define CRTC2_PIXEL_RATE_CNTL__CRTC2_DISPOUT_FIFO_ERROR__SHIFT 0x0000000e 1979de2bdb3dSTom St Denis #define CRTC2_PIXEL_RATE_CNTL__CRTC2_DROP_PIXEL_MASK 0x00000200L 1980de2bdb3dSTom St Denis #define CRTC2_PIXEL_RATE_CNTL__CRTC2_DROP_PIXEL__SHIFT 0x00000009 1981de2bdb3dSTom St Denis #define CRTC2_PIXEL_RATE_CNTL__CRTC2_PIXEL_RATE_SOURCE_MASK 0x00000003L 1982de2bdb3dSTom St Denis #define CRTC2_PIXEL_RATE_CNTL__CRTC2_PIXEL_RATE_SOURCE__SHIFT 0x00000000 1983de2bdb3dSTom St Denis #define CRTC2_PIXEL_RATE_CNTL__DP_DTO2_ENABLE_MASK 0x00000010L 1984de2bdb3dSTom St Denis #define CRTC2_PIXEL_RATE_CNTL__DP_DTO2_ENABLE__SHIFT 0x00000004 1985de2bdb3dSTom St Denis #define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_EN_DB_MASK 0x00000010L 1986de2bdb3dSTom St Denis #define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_EN_DB__SHIFT 0x00000004 1987de2bdb3dSTom St Denis #define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_EN_MASK 0x00000001L 1988de2bdb3dSTom St Denis #define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_EN__SHIFT 0x00000000 1989de2bdb3dSTom St Denis #define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT_MASK 0x000c0000L 1990de2bdb3dSTom St Denis #define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT_RESET_MASK 0x00010000L 1991de2bdb3dSTom St Denis #define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT_RESET_PENDING_MASK 0x00020000L 1992de2bdb3dSTom St Denis #define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT_RESET_PENDING__SHIFT 0x00000011 1993de2bdb3dSTom St Denis #define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT_RESET__SHIFT 0x00000010 1994de2bdb3dSTom St Denis #define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT__SHIFT 0x00000012 1995de2bdb3dSTom St Denis #define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_STEREO_SEL_OVR_MASK 0x00001000L 1996de2bdb3dSTom St Denis #define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_STEREO_SEL_OVR__SHIFT 0x0000000c 1997de2bdb3dSTom St Denis #define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_V_UPDATE_MODE_MASK 0x00000300L 1998de2bdb3dSTom St Denis #define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_V_UPDATE_MODE__SHIFT 0x00000008 1999de2bdb3dSTom St Denis #define CRTC3_PIXEL_RATE_CNTL__CRTC3_ADD_PIXEL_MASK 0x00000100L 2000de2bdb3dSTom St Denis #define CRTC3_PIXEL_RATE_CNTL__CRTC3_ADD_PIXEL__SHIFT 0x00000008 2001de2bdb3dSTom St Denis #define CRTC3_PIXEL_RATE_CNTL__CRTC3_DISPOUT_ERROR_COUNT_MASK 0x0fff0000L 2002de2bdb3dSTom St Denis #define CRTC3_PIXEL_RATE_CNTL__CRTC3_DISPOUT_ERROR_COUNT__SHIFT 0x00000010 2003de2bdb3dSTom St Denis #define CRTC3_PIXEL_RATE_CNTL__CRTC3_DISPOUT_FIFO_ERROR_MASK 0x0000c000L 2004de2bdb3dSTom St Denis #define CRTC3_PIXEL_RATE_CNTL__CRTC3_DISPOUT_FIFO_ERROR__SHIFT 0x0000000e 2005de2bdb3dSTom St Denis #define CRTC3_PIXEL_RATE_CNTL__CRTC3_DROP_PIXEL_MASK 0x00000200L 2006de2bdb3dSTom St Denis #define CRTC3_PIXEL_RATE_CNTL__CRTC3_DROP_PIXEL__SHIFT 0x00000009 2007de2bdb3dSTom St Denis #define CRTC3_PIXEL_RATE_CNTL__CRTC3_PIXEL_RATE_SOURCE_MASK 0x00000003L 2008de2bdb3dSTom St Denis #define CRTC3_PIXEL_RATE_CNTL__CRTC3_PIXEL_RATE_SOURCE__SHIFT 0x00000000 2009de2bdb3dSTom St Denis #define CRTC3_PIXEL_RATE_CNTL__DP_DTO3_ENABLE_MASK 0x00000010L 2010de2bdb3dSTom St Denis #define CRTC3_PIXEL_RATE_CNTL__DP_DTO3_ENABLE__SHIFT 0x00000004 2011de2bdb3dSTom St Denis #define CRTC4_PIXEL_RATE_CNTL__CRTC4_ADD_PIXEL_MASK 0x00000100L 2012de2bdb3dSTom St Denis #define CRTC4_PIXEL_RATE_CNTL__CRTC4_ADD_PIXEL__SHIFT 0x00000008 2013de2bdb3dSTom St Denis #define CRTC4_PIXEL_RATE_CNTL__CRTC4_DISPOUT_ERROR_COUNT_MASK 0x0fff0000L 2014de2bdb3dSTom St Denis #define CRTC4_PIXEL_RATE_CNTL__CRTC4_DISPOUT_ERROR_COUNT__SHIFT 0x00000010 2015de2bdb3dSTom St Denis #define CRTC4_PIXEL_RATE_CNTL__CRTC4_DISPOUT_FIFO_ERROR_MASK 0x0000c000L 2016de2bdb3dSTom St Denis #define CRTC4_PIXEL_RATE_CNTL__CRTC4_DISPOUT_FIFO_ERROR__SHIFT 0x0000000e 2017de2bdb3dSTom St Denis #define CRTC4_PIXEL_RATE_CNTL__CRTC4_DROP_PIXEL_MASK 0x00000200L 2018de2bdb3dSTom St Denis #define CRTC4_PIXEL_RATE_CNTL__CRTC4_DROP_PIXEL__SHIFT 0x00000009 2019de2bdb3dSTom St Denis #define CRTC4_PIXEL_RATE_CNTL__CRTC4_PIXEL_RATE_SOURCE_MASK 0x00000003L 2020de2bdb3dSTom St Denis #define CRTC4_PIXEL_RATE_CNTL__CRTC4_PIXEL_RATE_SOURCE__SHIFT 0x00000000 2021de2bdb3dSTom St Denis #define CRTC4_PIXEL_RATE_CNTL__DP_DTO4_ENABLE_MASK 0x00000010L 2022de2bdb3dSTom St Denis #define CRTC4_PIXEL_RATE_CNTL__DP_DTO4_ENABLE__SHIFT 0x00000004 2023de2bdb3dSTom St Denis #define CRTC5_PIXEL_RATE_CNTL__CRTC5_ADD_PIXEL_MASK 0x00000100L 2024de2bdb3dSTom St Denis #define CRTC5_PIXEL_RATE_CNTL__CRTC5_ADD_PIXEL__SHIFT 0x00000008 2025de2bdb3dSTom St Denis #define CRTC5_PIXEL_RATE_CNTL__CRTC5_DISPOUT_ERROR_COUNT_MASK 0x0fff0000L 2026de2bdb3dSTom St Denis #define CRTC5_PIXEL_RATE_CNTL__CRTC5_DISPOUT_ERROR_COUNT__SHIFT 0x00000010 2027de2bdb3dSTom St Denis #define CRTC5_PIXEL_RATE_CNTL__CRTC5_DISPOUT_FIFO_ERROR_MASK 0x0000c000L 2028de2bdb3dSTom St Denis #define CRTC5_PIXEL_RATE_CNTL__CRTC5_DISPOUT_FIFO_ERROR__SHIFT 0x0000000e 2029de2bdb3dSTom St Denis #define CRTC5_PIXEL_RATE_CNTL__CRTC5_DROP_PIXEL_MASK 0x00000200L 2030de2bdb3dSTom St Denis #define CRTC5_PIXEL_RATE_CNTL__CRTC5_DROP_PIXEL__SHIFT 0x00000009 2031de2bdb3dSTom St Denis #define CRTC5_PIXEL_RATE_CNTL__CRTC5_PIXEL_RATE_SOURCE_MASK 0x00000003L 2032de2bdb3dSTom St Denis #define CRTC5_PIXEL_RATE_CNTL__CRTC5_PIXEL_RATE_SOURCE__SHIFT 0x00000000 2033de2bdb3dSTom St Denis #define CRTC5_PIXEL_RATE_CNTL__DP_DTO5_ENABLE_MASK 0x00000010L 2034de2bdb3dSTom St Denis #define CRTC5_PIXEL_RATE_CNTL__DP_DTO5_ENABLE__SHIFT 0x00000004 2035de2bdb3dSTom St Denis #define CRTC8_DATA__VCRTC_DATA_MASK 0x000000ffL 2036de2bdb3dSTom St Denis #define CRTC8_DATA__VCRTC_DATA__SHIFT 0x00000000 2037de2bdb3dSTom St Denis #define CRTC8_IDX__VCRTC_IDX_MASK 0x0000003fL 2038de2bdb3dSTom St Denis #define CRTC8_IDX__VCRTC_IDX__SHIFT 0x00000000 2039de2bdb3dSTom St Denis #define CRTC_ALLOW_STOP_OFF_V_CNT__CRTC_ALLOW_STOP_OFF_V_CNT_MASK 0x000000ffL 2040de2bdb3dSTom St Denis #define CRTC_ALLOW_STOP_OFF_V_CNT__CRTC_ALLOW_STOP_OFF_V_CNT__SHIFT 0x00000000 2041de2bdb3dSTom St Denis #define CRTC_ALLOW_STOP_OFF_V_CNT__CRTC_DISABLE_ALLOW_STOP_OFF_V_CNT_MASK 0x00010000L 2042de2bdb3dSTom St Denis #define CRTC_ALLOW_STOP_OFF_V_CNT__CRTC_DISABLE_ALLOW_STOP_OFF_V_CNT__SHIFT 0x00000010 2043de2bdb3dSTom St Denis #define CRTC_BLACK_COLOR__CRTC_BLACK_COLOR_B_CB_MASK 0x000003ffL 2044de2bdb3dSTom St Denis #define CRTC_BLACK_COLOR__CRTC_BLACK_COLOR_B_CB__SHIFT 0x00000000 2045de2bdb3dSTom St Denis #define CRTC_BLACK_COLOR__CRTC_BLACK_COLOR_G_Y_MASK 0x000ffc00L 2046de2bdb3dSTom St Denis #define CRTC_BLACK_COLOR__CRTC_BLACK_COLOR_G_Y__SHIFT 0x0000000a 2047de2bdb3dSTom St Denis #define CRTC_BLACK_COLOR__CRTC_BLACK_COLOR_R_CR_MASK 0x3ff00000L 2048de2bdb3dSTom St Denis #define CRTC_BLACK_COLOR__CRTC_BLACK_COLOR_R_CR__SHIFT 0x00000014 2049de2bdb3dSTom St Denis #define CRTC_BLANK_CONTROL__CRTC_BLANK_DATA_EN_MASK 0x00000100L 2050de2bdb3dSTom St Denis #define CRTC_BLANK_CONTROL__CRTC_BLANK_DATA_EN__SHIFT 0x00000008 2051de2bdb3dSTom St Denis #define CRTC_BLANK_CONTROL__CRTC_BLANK_DE_MODE_MASK 0x00010000L 2052de2bdb3dSTom St Denis #define CRTC_BLANK_CONTROL__CRTC_BLANK_DE_MODE__SHIFT 0x00000010 2053de2bdb3dSTom St Denis #define CRTC_BLANK_CONTROL__CRTC_CURRENT_BLANK_STATE_MASK 0x00000001L 2054de2bdb3dSTom St Denis #define CRTC_BLANK_CONTROL__CRTC_CURRENT_BLANK_STATE__SHIFT 0x00000000 2055de2bdb3dSTom St Denis #define CRTC_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_BLUE_CB_MASK 0x000003ffL 2056de2bdb3dSTom St Denis #define CRTC_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_BLUE_CB__SHIFT 0x00000000 2057de2bdb3dSTom St Denis #define CRTC_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_GREEN_Y_MASK 0x000ffc00L 2058de2bdb3dSTom St Denis #define CRTC_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_GREEN_Y__SHIFT 0x0000000a 2059de2bdb3dSTom St Denis #define CRTC_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_RED_CR_MASK 0x3ff00000L 2060de2bdb3dSTom St Denis #define CRTC_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_RED_CR__SHIFT 0x00000014 2061de2bdb3dSTom St Denis #define CRTC_CONTROL__CRTC_CURRENT_MASTER_EN_STATE_MASK 0x00010000L 2062de2bdb3dSTom St Denis #define CRTC_CONTROL__CRTC_CURRENT_MASTER_EN_STATE__SHIFT 0x00000010 2063de2bdb3dSTom St Denis #define CRTC_CONTROL__CRTC_DISABLE_POINT_CNTL_MASK 0x00000300L 2064de2bdb3dSTom St Denis #define CRTC_CONTROL__CRTC_DISABLE_POINT_CNTL__SHIFT 0x00000008 2065de2bdb3dSTom St Denis #define CRTC_CONTROL__CRTC_DISP_READ_REQUEST_DISABLE_MASK 0x01000000L 2066de2bdb3dSTom St Denis #define CRTC_CONTROL__CRTC_DISP_READ_REQUEST_DISABLE__SHIFT 0x00000018 2067de2bdb3dSTom St Denis #define CRTC_CONTROL__CRTC_FIELD_NUMBER_CNTL_MASK 0x00002000L 2068de2bdb3dSTom St Denis #define CRTC_CONTROL__CRTC_FIELD_NUMBER_CNTL__SHIFT 0x0000000d 2069de2bdb3dSTom St Denis #define CRTC_CONTROL__CRTC_HBLANK_EARLY_CONTROL_MASK 0x00700000L 2070de2bdb3dSTom St Denis #define CRTC_CONTROL__CRTC_HBLANK_EARLY_CONTROL__SHIFT 0x00000014 2071de2bdb3dSTom St Denis #define CRTC_CONTROL__CRTC_MASTER_EN_MASK 0x00000001L 2072de2bdb3dSTom St Denis #define CRTC_CONTROL__CRTC_MASTER_EN__SHIFT 0x00000000 2073de2bdb3dSTom St Denis #define CRTC_CONTROL__CRTC_SOF_PULL_EN_MASK 0x20000000L 2074de2bdb3dSTom St Denis #define CRTC_CONTROL__CRTC_SOF_PULL_EN__SHIFT 0x0000001d 2075de2bdb3dSTom St Denis #define CRTC_CONTROL__CRTC_START_POINT_CNTL_MASK 0x00001000L 2076de2bdb3dSTom St Denis #define CRTC_CONTROL__CRTC_START_POINT_CNTL__SHIFT 0x0000000c 2077de2bdb3dSTom St Denis #define CRTC_CONTROL__CRTC_SYNC_RESET_SEL_MASK 0x00000010L 2078de2bdb3dSTom St Denis #define CRTC_CONTROL__CRTC_SYNC_RESET_SEL__SHIFT 0x00000004 20796863660dSAlex Deucher #define CRTC_CONTROL__CRTC_PREFETCH_EN_MASK 0x10000000L 20806863660dSAlex Deucher #define CRTC_CONTROL__CRTC_PREFETCH_EN__SHIFT 0x0000001c 2081de2bdb3dSTom St Denis #define CRTC_COUNT_CONTROL__CRTC_HORZ_COUNT_BY2_EN_MASK 0x00000001L 2082de2bdb3dSTom St Denis #define CRTC_COUNT_CONTROL__CRTC_HORZ_COUNT_BY2_EN__SHIFT 0x00000000 2083de2bdb3dSTom St Denis #define CRTC_COUNT_CONTROL__CRTC_HORZ_REPETITION_COUNT_MASK 0x0000001eL 2084de2bdb3dSTom St Denis #define CRTC_COUNT_CONTROL__CRTC_HORZ_REPETITION_COUNT__SHIFT 0x00000001 2085de2bdb3dSTom St Denis #define CRTC_COUNT_RESET__CRTC_RESET_FRAME_COUNT_MASK 0x00000001L 2086de2bdb3dSTom St Denis #define CRTC_COUNT_RESET__CRTC_RESET_FRAME_COUNT__SHIFT 0x00000000 2087de2bdb3dSTom St Denis #define CRTC_DCFE_CLOCK_CONTROL__CRTC_DCFE_CLOCK_ENABLE_MASK 0x80000000L 2088de2bdb3dSTom St Denis #define CRTC_DCFE_CLOCK_CONTROL__CRTC_DCFE_CLOCK_ENABLE__SHIFT 0x0000001f 2089de2bdb3dSTom St Denis #define CRTC_DCFE_CLOCK_CONTROL__CRTC_DCFE_TEST_CLK_SEL_MASK 0x1f000000L 2090de2bdb3dSTom St Denis #define CRTC_DCFE_CLOCK_CONTROL__CRTC_DCFE_TEST_CLK_SEL__SHIFT 0x00000018 2091de2bdb3dSTom St Denis #define CRTC_DCFE_CLOCK_CONTROL__CRTC_DISPCLK_G_DCP_GATE_DISABLE_MASK 0x00000100L 2092de2bdb3dSTom St Denis #define CRTC_DCFE_CLOCK_CONTROL__CRTC_DISPCLK_G_DCP_GATE_DISABLE__SHIFT 0x00000008 2093de2bdb3dSTom St Denis #define CRTC_DCFE_CLOCK_CONTROL__CRTC_DISPCLK_G_SCL_GATE_DISABLE_MASK 0x00001000L 2094de2bdb3dSTom St Denis #define CRTC_DCFE_CLOCK_CONTROL__CRTC_DISPCLK_G_SCL_GATE_DISABLE__SHIFT 0x0000000c 2095de2bdb3dSTom St Denis #define CRTC_DCFE_CLOCK_CONTROL__CRTC_DISPCLK_R_DCFE_GATE_DISABLE_MASK 0x00000010L 2096de2bdb3dSTom St Denis #define CRTC_DCFE_CLOCK_CONTROL__CRTC_DISPCLK_R_DCFE_GATE_DISABLE__SHIFT 0x00000004 2097de2bdb3dSTom St Denis #define CRTC_DOUBLE_BUFFER_CONTROL__CRTC_BLANK_DATA_DOUBLE_BUFFER_EN_MASK 0x00010000L 2098de2bdb3dSTom St Denis #define CRTC_DOUBLE_BUFFER_CONTROL__CRTC_BLANK_DATA_DOUBLE_BUFFER_EN__SHIFT 0x00000010 2099de2bdb3dSTom St Denis #define CRTC_DOUBLE_BUFFER_CONTROL__CRTC_UPDATE_INSTANTLY_MASK 0x00000100L 2100de2bdb3dSTom St Denis #define CRTC_DOUBLE_BUFFER_CONTROL__CRTC_UPDATE_INSTANTLY__SHIFT 0x00000008 2101de2bdb3dSTom St Denis #define CRTC_DOUBLE_BUFFER_CONTROL__CRTC_UPDATE_PENDING_MASK 0x00000001L 2102de2bdb3dSTom St Denis #define CRTC_DOUBLE_BUFFER_CONTROL__CRTC_UPDATE_PENDING__SHIFT 0x00000000 2103de2bdb3dSTom St Denis #define CRTC_DTMTEST_CNTL__CRTC_DTMTEST_CLK_DIV_MASK 0x0000001eL 2104de2bdb3dSTom St Denis #define CRTC_DTMTEST_CNTL__CRTC_DTMTEST_CLK_DIV__SHIFT 0x00000001 2105de2bdb3dSTom St Denis #define CRTC_DTMTEST_CNTL__CRTC_DTMTEST_CRTC_EN_MASK 0x00000001L 2106de2bdb3dSTom St Denis #define CRTC_DTMTEST_CNTL__CRTC_DTMTEST_CRTC_EN__SHIFT 0x00000000 2107de2bdb3dSTom St Denis #define CRTC_DTMTEST_STATUS_POSITION__CRTC_DTMTEST_HORZ_COUNT_MASK 0x1fff0000L 2108de2bdb3dSTom St Denis #define CRTC_DTMTEST_STATUS_POSITION__CRTC_DTMTEST_HORZ_COUNT__SHIFT 0x00000010 2109de2bdb3dSTom St Denis #define CRTC_DTMTEST_STATUS_POSITION__CRTC_DTMTEST_VERT_COUNT_MASK 0x00001fffL 2110de2bdb3dSTom St Denis #define CRTC_DTMTEST_STATUS_POSITION__CRTC_DTMTEST_VERT_COUNT__SHIFT 0x00000000 2111de2bdb3dSTom St Denis #define CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_GRANULARITY_MASK 0x00010000L 2112de2bdb3dSTom St Denis #define CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_GRANULARITY__SHIFT 0x00000010 2113de2bdb3dSTom St Denis #define CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_INPUT_STATUS_MASK 0x01000000L 2114de2bdb3dSTom St Denis #define CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_INPUT_STATUS__SHIFT 0x00000018 2115de2bdb3dSTom St Denis #define CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_POLARITY_MASK 0x00000100L 2116de2bdb3dSTom St Denis #define CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_POLARITY__SHIFT 0x00000008 2117de2bdb3dSTom St Denis #define CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_SOURCE_SELECT_MASK 0x0000001fL 2118de2bdb3dSTom St Denis #define CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_SOURCE_SELECT__SHIFT 0x00000000 2119de2bdb3dSTom St Denis #define CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_CHECK_MASK 0x00000010L 2120de2bdb3dSTom St Denis #define CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_CHECK__SHIFT 0x00000004 2121de2bdb3dSTom St Denis #define CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_CLEAR_MASK 0x01000000L 2122de2bdb3dSTom St Denis #define CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_CLEAR__SHIFT 0x00000018 2123de2bdb3dSTom St Denis #define CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_MODE_MASK 0x00000003L 2124de2bdb3dSTom St Denis #define CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_MODE__SHIFT 0x00000000 2125de2bdb3dSTom St Denis #define CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_OCCURRED_MASK 0x00010000L 2126de2bdb3dSTom St Denis #define CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_OCCURRED__SHIFT 0x00000010 2127de2bdb3dSTom St Denis #define CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_TRIG_SEL_MASK 0x00000100L 2128de2bdb3dSTom St Denis #define CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_TRIG_SEL__SHIFT 0x00000008 2129de2bdb3dSTom St Denis #define CRTC_GSL_CONTROL__CRTC_GSL_CHECK_ALL_FIELDS_MASK 0x10000000L 2130de2bdb3dSTom St Denis #define CRTC_GSL_CONTROL__CRTC_GSL_CHECK_ALL_FIELDS__SHIFT 0x0000001c 2131de2bdb3dSTom St Denis #define CRTC_GSL_CONTROL__CRTC_GSL_CHECK_LINE_NUM_MASK 0x00001fffL 2132de2bdb3dSTom St Denis #define CRTC_GSL_CONTROL__CRTC_GSL_CHECK_LINE_NUM__SHIFT 0x00000000 2133de2bdb3dSTom St Denis #define CRTC_GSL_CONTROL__CRTC_GSL_FORCE_DELAY_MASK 0x001f0000L 2134de2bdb3dSTom St Denis #define CRTC_GSL_CONTROL__CRTC_GSL_FORCE_DELAY__SHIFT 0x00000010 2135de2bdb3dSTom St Denis #define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_CLEAR_MASK 0x00080000L 2136de2bdb3dSTom St Denis #define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_CLEAR__SHIFT 0x00000013 2137de2bdb3dSTom St Denis #define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_DELAY_MASK 0x0000ff00L 2138de2bdb3dSTom St Denis #define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_DELAY__SHIFT 0x00000008 2139de2bdb3dSTom St Denis #define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_LIMIT_MASK 0x000000ffL 2140de2bdb3dSTom St Denis #define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_LIMIT__SHIFT 0x00000000 2141de2bdb3dSTom St Denis #define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_MASK 0xff000000L 2142de2bdb3dSTom St Denis #define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_MASTER_FASTER_MASK 0x00800000L 2143de2bdb3dSTom St Denis #define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_MASTER_FASTER__SHIFT 0x00000017 2144de2bdb3dSTom St Denis #define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_MODE_MASK 0x00060000L 2145de2bdb3dSTom St Denis #define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_MODE__SHIFT 0x00000011 2146de2bdb3dSTom St Denis #define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_OCCURRED_MASK 0x00100000L 2147de2bdb3dSTom St Denis #define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_OCCURRED__SHIFT 0x00000014 2148de2bdb3dSTom St Denis #define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP__SHIFT 0x00000018 2149de2bdb3dSTom St Denis #define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_SOURCE_SEL_MASK 0x00010000L 2150de2bdb3dSTom St Denis #define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_SOURCE_SEL__SHIFT 0x00000010 2151de2bdb3dSTom St Denis #define CRTC_GSL_WINDOW__CRTC_GSL_WINDOW_END_MASK 0x1fff0000L 2152de2bdb3dSTom St Denis #define CRTC_GSL_WINDOW__CRTC_GSL_WINDOW_END__SHIFT 0x00000010 2153de2bdb3dSTom St Denis #define CRTC_GSL_WINDOW__CRTC_GSL_WINDOW_START_MASK 0x00001fffL 2154de2bdb3dSTom St Denis #define CRTC_GSL_WINDOW__CRTC_GSL_WINDOW_START__SHIFT 0x00000000 2155de2bdb3dSTom St Denis #define CRTC_H_BLANK_EARLY_NUM__CRTC_H_BLANK_EARLY_NUM_DIS_MASK 0x00010000L 2156de2bdb3dSTom St Denis #define CRTC_H_BLANK_EARLY_NUM__CRTC_H_BLANK_EARLY_NUM_DIS__SHIFT 0x00000010 2157de2bdb3dSTom St Denis #define CRTC_H_BLANK_EARLY_NUM__CRTC_H_BLANK_EARLY_NUM_MASK 0x000003ffL 2158de2bdb3dSTom St Denis #define CRTC_H_BLANK_EARLY_NUM__CRTC_H_BLANK_EARLY_NUM__SHIFT 0x00000000 2159de2bdb3dSTom St Denis #define CRTC_H_BLANK_START_END__CRTC_H_BLANK_END_MASK 0x1fff0000L 2160de2bdb3dSTom St Denis #define CRTC_H_BLANK_START_END__CRTC_H_BLANK_END__SHIFT 0x00000010 2161de2bdb3dSTom St Denis #define CRTC_H_BLANK_START_END__CRTC_H_BLANK_START_MASK 0x00001fffL 2162de2bdb3dSTom St Denis #define CRTC_H_BLANK_START_END__CRTC_H_BLANK_START__SHIFT 0x00000000 2163de2bdb3dSTom St Denis #define CRTC_H_SYNC_A_CNTL__CRTC_COMP_SYNC_A_EN_MASK 0x00010000L 2164de2bdb3dSTom St Denis #define CRTC_H_SYNC_A_CNTL__CRTC_COMP_SYNC_A_EN__SHIFT 0x00000010 2165de2bdb3dSTom St Denis #define CRTC_H_SYNC_A_CNTL__CRTC_H_SYNC_A_CUTOFF_MASK 0x00020000L 2166de2bdb3dSTom St Denis #define CRTC_H_SYNC_A_CNTL__CRTC_H_SYNC_A_CUTOFF__SHIFT 0x00000011 2167de2bdb3dSTom St Denis #define CRTC_H_SYNC_A_CNTL__CRTC_H_SYNC_A_POL_MASK 0x00000001L 2168de2bdb3dSTom St Denis #define CRTC_H_SYNC_A_CNTL__CRTC_H_SYNC_A_POL__SHIFT 0x00000000 2169de2bdb3dSTom St Denis #define CRTC_H_SYNC_A__CRTC_H_SYNC_A_END_MASK 0x1fff0000L 2170de2bdb3dSTom St Denis #define CRTC_H_SYNC_A__CRTC_H_SYNC_A_END__SHIFT 0x00000010 2171de2bdb3dSTom St Denis #define CRTC_H_SYNC_A__CRTC_H_SYNC_A_START_MASK 0x00001fffL 2172de2bdb3dSTom St Denis #define CRTC_H_SYNC_A__CRTC_H_SYNC_A_START__SHIFT 0x00000000 2173de2bdb3dSTom St Denis #define CRTC_H_SYNC_B_CNTL__CRTC_COMP_SYNC_B_EN_MASK 0x00010000L 2174de2bdb3dSTom St Denis #define CRTC_H_SYNC_B_CNTL__CRTC_COMP_SYNC_B_EN__SHIFT 0x00000010 2175de2bdb3dSTom St Denis #define CRTC_H_SYNC_B_CNTL__CRTC_H_SYNC_B_CUTOFF_MASK 0x00020000L 2176de2bdb3dSTom St Denis #define CRTC_H_SYNC_B_CNTL__CRTC_H_SYNC_B_CUTOFF__SHIFT 0x00000011 2177de2bdb3dSTom St Denis #define CRTC_H_SYNC_B_CNTL__CRTC_H_SYNC_B_POL_MASK 0x00000001L 2178de2bdb3dSTom St Denis #define CRTC_H_SYNC_B_CNTL__CRTC_H_SYNC_B_POL__SHIFT 0x00000000 2179de2bdb3dSTom St Denis #define CRTC_H_SYNC_B__CRTC_H_SYNC_B_END_MASK 0x1fff0000L 2180de2bdb3dSTom St Denis #define CRTC_H_SYNC_B__CRTC_H_SYNC_B_END__SHIFT 0x00000010 2181de2bdb3dSTom St Denis #define CRTC_H_SYNC_B__CRTC_H_SYNC_B_START_MASK 0x00001fffL 2182de2bdb3dSTom St Denis #define CRTC_H_SYNC_B__CRTC_H_SYNC_B_START__SHIFT 0x00000000 2183de2bdb3dSTom St Denis #define CRTC_H_TOTAL__CRTC_H_TOTAL_MASK 0x00001fffL 2184de2bdb3dSTom St Denis #define CRTC_H_TOTAL__CRTC_H_TOTAL__SHIFT 0x00000000 2185de2bdb3dSTom St Denis #define CRTC_INTERLACE_CONTROL__CRTC_INTERLACE_ENABLE_MASK 0x00000001L 2186de2bdb3dSTom St Denis #define CRTC_INTERLACE_CONTROL__CRTC_INTERLACE_ENABLE__SHIFT 0x00000000 2187de2bdb3dSTom St Denis #define CRTC_INTERLACE_CONTROL__CRTC_INTERLACE_FORCE_NEXT_FIELD_MASK 0x00030000L 2188de2bdb3dSTom St Denis #define CRTC_INTERLACE_CONTROL__CRTC_INTERLACE_FORCE_NEXT_FIELD__SHIFT 0x00000010 2189de2bdb3dSTom St Denis #define CRTC_INTERLACE_STATUS__CRTC_INTERLACE_CURRENT_FIELD_MASK 0x00000001L 2190de2bdb3dSTom St Denis #define CRTC_INTERLACE_STATUS__CRTC_INTERLACE_CURRENT_FIELD__SHIFT 0x00000000 2191de2bdb3dSTom St Denis #define CRTC_INTERLACE_STATUS__CRTC_INTERLACE_NEXT_FIELD_MASK 0x00000002L 2192de2bdb3dSTom St Denis #define CRTC_INTERLACE_STATUS__CRTC_INTERLACE_NEXT_FIELD__SHIFT 0x00000001 2193de2bdb3dSTom St Denis #define CRTC_INTERRUPT_CONTROL__CRTC_FORCE_COUNT_NOW_INT_MSK_MASK 0x00000100L 2194de2bdb3dSTom St Denis #define CRTC_INTERRUPT_CONTROL__CRTC_FORCE_COUNT_NOW_INT_MSK__SHIFT 0x00000008 2195de2bdb3dSTom St Denis #define CRTC_INTERRUPT_CONTROL__CRTC_FORCE_COUNT_NOW_INT_TYPE_MASK 0x00000200L 2196de2bdb3dSTom St Denis #define CRTC_INTERRUPT_CONTROL__CRTC_FORCE_COUNT_NOW_INT_TYPE__SHIFT 0x00000009 2197de2bdb3dSTom St Denis #define CRTC_INTERRUPT_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_INT_MSK_MASK 0x00010000L 2198de2bdb3dSTom St Denis #define CRTC_INTERRUPT_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_INT_MSK__SHIFT 0x00000010 2199de2bdb3dSTom St Denis #define CRTC_INTERRUPT_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_INT_TYPE_MASK 0x00020000L 2200de2bdb3dSTom St Denis #define CRTC_INTERRUPT_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_INT_TYPE__SHIFT 0x00000011 2201de2bdb3dSTom St Denis #define CRTC_INTERRUPT_CONTROL__CRTC_GSL_VSYNC_GAP_INT_MSK_MASK 0x40000000L 2202de2bdb3dSTom St Denis #define CRTC_INTERRUPT_CONTROL__CRTC_GSL_VSYNC_GAP_INT_MSK__SHIFT 0x0000001e 2203de2bdb3dSTom St Denis #define CRTC_INTERRUPT_CONTROL__CRTC_GSL_VSYNC_GAP_INT_TYPE_MASK 0x80000000L 2204de2bdb3dSTom St Denis #define CRTC_INTERRUPT_CONTROL__CRTC_GSL_VSYNC_GAP_INT_TYPE__SHIFT 0x0000001f 2205de2bdb3dSTom St Denis #define CRTC_INTERRUPT_CONTROL__CRTC_SNAPSHOT_INT_MSK_MASK 0x00000001L 2206de2bdb3dSTom St Denis #define CRTC_INTERRUPT_CONTROL__CRTC_SNAPSHOT_INT_MSK__SHIFT 0x00000000 2207de2bdb3dSTom St Denis #define CRTC_INTERRUPT_CONTROL__CRTC_SNAPSHOT_INT_TYPE_MASK 0x00000002L 2208de2bdb3dSTom St Denis #define CRTC_INTERRUPT_CONTROL__CRTC_SNAPSHOT_INT_TYPE__SHIFT 0x00000001 2209de2bdb3dSTom St Denis #define CRTC_INTERRUPT_CONTROL__CRTC_TRIGA_INT_MSK_MASK 0x01000000L 2210de2bdb3dSTom St Denis #define CRTC_INTERRUPT_CONTROL__CRTC_TRIGA_INT_MSK__SHIFT 0x00000018 2211de2bdb3dSTom St Denis #define CRTC_INTERRUPT_CONTROL__CRTC_TRIGA_INT_TYPE_MASK 0x04000000L 2212de2bdb3dSTom St Denis #define CRTC_INTERRUPT_CONTROL__CRTC_TRIGA_INT_TYPE__SHIFT 0x0000001a 2213de2bdb3dSTom St Denis #define CRTC_INTERRUPT_CONTROL__CRTC_TRIGB_INT_MSK_MASK 0x02000000L 2214de2bdb3dSTom St Denis #define CRTC_INTERRUPT_CONTROL__CRTC_TRIGB_INT_MSK__SHIFT 0x00000019 2215de2bdb3dSTom St Denis #define CRTC_INTERRUPT_CONTROL__CRTC_TRIGB_INT_TYPE_MASK 0x08000000L 2216de2bdb3dSTom St Denis #define CRTC_INTERRUPT_CONTROL__CRTC_TRIGB_INT_TYPE__SHIFT 0x0000001b 2217de2bdb3dSTom St Denis #define CRTC_INTERRUPT_CONTROL__CRTC_VSYNC_NOM_INT_MSK_MASK 0x10000000L 2218de2bdb3dSTom St Denis #define CRTC_INTERRUPT_CONTROL__CRTC_VSYNC_NOM_INT_MSK__SHIFT 0x0000001c 2219de2bdb3dSTom St Denis #define CRTC_INTERRUPT_CONTROL__CRTC_VSYNC_NOM_INT_TYPE_MASK 0x20000000L 2220de2bdb3dSTom St Denis #define CRTC_INTERRUPT_CONTROL__CRTC_VSYNC_NOM_INT_TYPE__SHIFT 0x0000001d 2221de2bdb3dSTom St Denis #define CRTC_INTERRUPT_CONTROL__CRTC_V_UPDATE_INT_MSK_MASK 0x00000010L 2222de2bdb3dSTom St Denis #define CRTC_INTERRUPT_CONTROL__CRTC_V_UPDATE_INT_MSK__SHIFT 0x00000004 2223de2bdb3dSTom St Denis #define CRTC_INTERRUPT_CONTROL__CRTC_V_UPDATE_INT_TYPE_MASK 0x00000020L 2224de2bdb3dSTom St Denis #define CRTC_INTERRUPT_CONTROL__CRTC_V_UPDATE_INT_TYPE__SHIFT 0x00000005 2225de2bdb3dSTom St Denis #define CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE__CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_MASK 0x00000001L 2226de2bdb3dSTom St Denis #define CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE__CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE__SHIFT 0x00000000 2227de2bdb3dSTom St Denis #define CRTC_MASTER_EN__CRTC_MASTER_EN_MASK 0x00000001L 2228de2bdb3dSTom St Denis #define CRTC_MASTER_EN__CRTC_MASTER_EN__SHIFT 0x00000000 2229de2bdb3dSTom St Denis #define CRTC_MVP_INBAND_CNTL_INSERT__CRTC_MVP_INBAND_CNTL_CHAR_INSERT_MASK 0xffffff00L 2230de2bdb3dSTom St Denis #define CRTC_MVP_INBAND_CNTL_INSERT__CRTC_MVP_INBAND_CNTL_CHAR_INSERT__SHIFT 0x00000008 2231de2bdb3dSTom St Denis #define CRTC_MVP_INBAND_CNTL_INSERT__CRTC_MVP_INBAND_OUT_MODE_MASK 0x00000003L 2232de2bdb3dSTom St Denis #define CRTC_MVP_INBAND_CNTL_INSERT__CRTC_MVP_INBAND_OUT_MODE__SHIFT 0x00000000 2233de2bdb3dSTom St Denis #define CRTC_MVP_INBAND_CNTL_INSERT_TIMER__CRTC_MVP_INBAND_CNTL_CHAR_INSERT_TIMER_MASK 0x000000ffL 2234de2bdb3dSTom St Denis #define CRTC_MVP_INBAND_CNTL_INSERT_TIMER__CRTC_MVP_INBAND_CNTL_CHAR_INSERT_TIMER__SHIFT 0x00000000 2235de2bdb3dSTom St Denis #define CRTC_MVP_STATUS__CRTC_AFR_HSYNC_SWITCH_DONE_CLEAR_MASK 0x00100000L 2236de2bdb3dSTom St Denis #define CRTC_MVP_STATUS__CRTC_AFR_HSYNC_SWITCH_DONE_CLEAR__SHIFT 0x00000014 2237de2bdb3dSTom St Denis #define CRTC_MVP_STATUS__CRTC_AFR_HSYNC_SWITCH_DONE_OCCURRED_MASK 0x00000010L 2238de2bdb3dSTom St Denis #define CRTC_MVP_STATUS__CRTC_AFR_HSYNC_SWITCH_DONE_OCCURRED__SHIFT 0x00000004 2239de2bdb3dSTom St Denis #define CRTC_MVP_STATUS__CRTC_FLIP_NOW_CLEAR_MASK 0x00010000L 2240de2bdb3dSTom St Denis #define CRTC_MVP_STATUS__CRTC_FLIP_NOW_CLEAR__SHIFT 0x00000010 2241de2bdb3dSTom St Denis #define CRTC_MVP_STATUS__CRTC_FLIP_NOW_OCCURRED_MASK 0x00000001L 2242de2bdb3dSTom St Denis #define CRTC_MVP_STATUS__CRTC_FLIP_NOW_OCCURRED__SHIFT 0x00000000 2243de2bdb3dSTom St Denis #define CRTC_NOM_VERT_POSITION__CRTC_VERT_COUNT_NOM_MASK 0x00001fffL 2244de2bdb3dSTom St Denis #define CRTC_NOM_VERT_POSITION__CRTC_VERT_COUNT_NOM__SHIFT 0x00000000 2245de2bdb3dSTom St Denis #define CRTC_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_BLUE_MASK 0x000003ffL 2246de2bdb3dSTom St Denis #define CRTC_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_BLUE__SHIFT 0x00000000 2247de2bdb3dSTom St Denis #define CRTC_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_GREEN_MASK 0x000ffc00L 2248de2bdb3dSTom St Denis #define CRTC_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_GREEN__SHIFT 0x0000000a 2249de2bdb3dSTom St Denis #define CRTC_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_RED_MASK 0x3ff00000L 2250de2bdb3dSTom St Denis #define CRTC_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_RED__SHIFT 0x00000014 2251de2bdb3dSTom St Denis #define CRTC_SNAPSHOT_CONTROL__CRTC_AUTO_SNAPSHOT_TRIG_SEL_MASK 0x00000003L 2252de2bdb3dSTom St Denis #define CRTC_SNAPSHOT_CONTROL__CRTC_AUTO_SNAPSHOT_TRIG_SEL__SHIFT 0x00000000 2253de2bdb3dSTom St Denis #define CRTC_SNAPSHOT_FRAME__CRTC_SNAPSHOT_FRAME_COUNT_MASK 0x00ffffffL 2254de2bdb3dSTom St Denis #define CRTC_SNAPSHOT_FRAME__CRTC_SNAPSHOT_FRAME_COUNT__SHIFT 0x00000000 2255de2bdb3dSTom St Denis #define CRTC_SNAPSHOT_POSITION__CRTC_SNAPSHOT_HORZ_COUNT_MASK 0x1fff0000L 2256de2bdb3dSTom St Denis #define CRTC_SNAPSHOT_POSITION__CRTC_SNAPSHOT_HORZ_COUNT__SHIFT 0x00000010 2257de2bdb3dSTom St Denis #define CRTC_SNAPSHOT_POSITION__CRTC_SNAPSHOT_VERT_COUNT_MASK 0x00001fffL 2258de2bdb3dSTom St Denis #define CRTC_SNAPSHOT_POSITION__CRTC_SNAPSHOT_VERT_COUNT__SHIFT 0x00000000 2259de2bdb3dSTom St Denis #define CRTC_SNAPSHOT_STATUS__CRTC_SNAPSHOT_CLEAR_MASK 0x00000002L 2260de2bdb3dSTom St Denis #define CRTC_SNAPSHOT_STATUS__CRTC_SNAPSHOT_CLEAR__SHIFT 0x00000001 2261de2bdb3dSTom St Denis #define CRTC_SNAPSHOT_STATUS__CRTC_SNAPSHOT_MANUAL_TRIGGER_MASK 0x00000004L 2262de2bdb3dSTom St Denis #define CRTC_SNAPSHOT_STATUS__CRTC_SNAPSHOT_MANUAL_TRIGGER__SHIFT 0x00000002 2263de2bdb3dSTom St Denis #define CRTC_SNAPSHOT_STATUS__CRTC_SNAPSHOT_OCCURRED_MASK 0x00000001L 2264de2bdb3dSTom St Denis #define CRTC_SNAPSHOT_STATUS__CRTC_SNAPSHOT_OCCURRED__SHIFT 0x00000000 2265de2bdb3dSTom St Denis #define CRTC_START_LINE_CONTROL__CRTC_ADVANCED_START_LINE_POSITION_MASK 0x000f0000L 2266de2bdb3dSTom St Denis #define CRTC_START_LINE_CONTROL__CRTC_ADVANCED_START_LINE_POSITION__SHIFT 0x00000010 2267de2bdb3dSTom St Denis #define CRTC_START_LINE_CONTROL__CRTC_INTERLACE_START_LINE_EARLY_MASK 0x00000100L 2268de2bdb3dSTom St Denis #define CRTC_START_LINE_CONTROL__CRTC_INTERLACE_START_LINE_EARLY__SHIFT 0x00000008 2269de2bdb3dSTom St Denis #define CRTC_START_LINE_CONTROL__CRTC_PROGRESSIVE_START_LINE_EARLY_MASK 0x00000001L 2270de2bdb3dSTom St Denis #define CRTC_START_LINE_CONTROL__CRTC_PROGRESSIVE_START_LINE_EARLY__SHIFT 0x00000000 2271de2bdb3dSTom St Denis #define CRTC_STATUS__CRTC_H_ACTIVE_DISP_MASK 0x00020000L 2272de2bdb3dSTom St Denis #define CRTC_STATUS__CRTC_H_ACTIVE_DISP__SHIFT 0x00000011 2273de2bdb3dSTom St Denis #define CRTC_STATUS__CRTC_H_BLANK_MASK 0x00010000L 2274de2bdb3dSTom St Denis #define CRTC_STATUS__CRTC_H_BLANK__SHIFT 0x00000010 2275de2bdb3dSTom St Denis #define CRTC_STATUS__CRTC_H_SYNC_A_MASK 0x00040000L 2276de2bdb3dSTom St Denis #define CRTC_STATUS__CRTC_H_SYNC_A__SHIFT 0x00000012 2277de2bdb3dSTom St Denis #define CRTC_STATUS__CRTC_V_ACTIVE_DISP_MASK 0x00000002L 2278de2bdb3dSTom St Denis #define CRTC_STATUS__CRTC_V_ACTIVE_DISP__SHIFT 0x00000001 2279de2bdb3dSTom St Denis #define CRTC_STATUS__CRTC_V_BLANK_3D_STRUCTURE_MASK 0x00000020L 2280de2bdb3dSTom St Denis #define CRTC_STATUS__CRTC_V_BLANK_3D_STRUCTURE__SHIFT 0x00000005 2281de2bdb3dSTom St Denis #define CRTC_STATUS__CRTC_V_BLANK_MASK 0x00000001L 2282de2bdb3dSTom St Denis #define CRTC_STATUS__CRTC_V_BLANK__SHIFT 0x00000000 2283de2bdb3dSTom St Denis #define CRTC_STATUS__CRTC_V_START_LINE_MASK 0x00000010L 2284de2bdb3dSTom St Denis #define CRTC_STATUS__CRTC_V_START_LINE__SHIFT 0x00000004 2285de2bdb3dSTom St Denis #define CRTC_STATUS__CRTC_V_SYNC_A_MASK 0x00000004L 2286de2bdb3dSTom St Denis #define CRTC_STATUS__CRTC_V_SYNC_A__SHIFT 0x00000002 2287de2bdb3dSTom St Denis #define CRTC_STATUS__CRTC_V_UPDATE_MASK 0x00000008L 2288de2bdb3dSTom St Denis #define CRTC_STATUS__CRTC_V_UPDATE__SHIFT 0x00000003 2289de2bdb3dSTom St Denis #define CRTC_STATUS_FRAME_COUNT__CRTC_FRAME_COUNT_MASK 0x00ffffffL 2290de2bdb3dSTom St Denis #define CRTC_STATUS_FRAME_COUNT__CRTC_FRAME_COUNT__SHIFT 0x00000000 2291de2bdb3dSTom St Denis #define CRTC_STATUS_HV_COUNT__CRTC_HV_COUNT_MASK 0x1fffffffL 2292de2bdb3dSTom St Denis #define CRTC_STATUS_HV_COUNT__CRTC_HV_COUNT__SHIFT 0x00000000 2293de2bdb3dSTom St Denis #define CRTC_STATUS_POSITION__CRTC_HORZ_COUNT_MASK 0x1fff0000L 2294de2bdb3dSTom St Denis #define CRTC_STATUS_POSITION__CRTC_HORZ_COUNT__SHIFT 0x00000010 2295de2bdb3dSTom St Denis #define CRTC_STATUS_POSITION__CRTC_VERT_COUNT_MASK 0x00001fffL 2296de2bdb3dSTom St Denis #define CRTC_STATUS_POSITION__CRTC_VERT_COUNT__SHIFT 0x00000000 2297de2bdb3dSTom St Denis #define CRTC_STATUS_VF_COUNT__CRTC_VF_COUNT_MASK 0x1fffffffL 2298de2bdb3dSTom St Denis #define CRTC_STATUS_VF_COUNT__CRTC_VF_COUNT__SHIFT 0x00000000 2299de2bdb3dSTom St Denis #define CRTC_STEREO_CONTROL__CRTC_STEREO_EN_MASK 0x01000000L 2300de2bdb3dSTom St Denis #define CRTC_STEREO_CONTROL__CRTC_STEREO_EN__SHIFT 0x00000018 2301de2bdb3dSTom St Denis #define CRTC_STEREO_CONTROL__CRTC_STEREO_SYNC_OUTPUT_LINE_NUM_MASK 0x00001fffL 2302de2bdb3dSTom St Denis #define CRTC_STEREO_CONTROL__CRTC_STEREO_SYNC_OUTPUT_LINE_NUM__SHIFT 0x00000000 2303de2bdb3dSTom St Denis #define CRTC_STEREO_CONTROL__CRTC_STEREO_SYNC_OUTPUT_POLARITY_MASK 0x00008000L 2304de2bdb3dSTom St Denis #define CRTC_STEREO_CONTROL__CRTC_STEREO_SYNC_OUTPUT_POLARITY__SHIFT 0x0000000f 2305de2bdb3dSTom St Denis #define CRTC_STEREO_CONTROL__CRTC_STEREO_SYNC_SELECT_POLARITY_MASK 0x00010000L 2306de2bdb3dSTom St Denis #define CRTC_STEREO_CONTROL__CRTC_STEREO_SYNC_SELECT_POLARITY__SHIFT 0x00000010 2307de2bdb3dSTom St Denis #define CRTC_STEREO_FORCE_NEXT_EYE__CRTC_STEREO_FORCE_NEXT_EYE_MASK 0x00000003L 2308de2bdb3dSTom St Denis #define CRTC_STEREO_FORCE_NEXT_EYE__CRTC_STEREO_FORCE_NEXT_EYE__SHIFT 0x00000000 2309de2bdb3dSTom St Denis #define CRTC_STEREO_STATUS__CRTC_STEREO_CURRENT_EYE_MASK 0x00000001L 2310de2bdb3dSTom St Denis #define CRTC_STEREO_STATUS__CRTC_STEREO_CURRENT_EYE__SHIFT 0x00000000 2311de2bdb3dSTom St Denis #define CRTC_STEREO_STATUS__CRTC_STEREO_FORCE_NEXT_EYE_PENDING_MASK 0x03000000L 2312de2bdb3dSTom St Denis #define CRTC_STEREO_STATUS__CRTC_STEREO_FORCE_NEXT_EYE_PENDING__SHIFT 0x00000018 2313de2bdb3dSTom St Denis #define CRTC_STEREO_STATUS__CRTC_STEREO_SYNC_OUTPUT_MASK 0x00000100L 2314de2bdb3dSTom St Denis #define CRTC_STEREO_STATUS__CRTC_STEREO_SYNC_OUTPUT__SHIFT 0x00000008 2315de2bdb3dSTom St Denis #define CRTC_STEREO_STATUS__CRTC_STEREO_SYNC_SELECT_MASK 0x00010000L 2316de2bdb3dSTom St Denis #define CRTC_STEREO_STATUS__CRTC_STEREO_SYNC_SELECT__SHIFT 0x00000010 2317de2bdb3dSTom St Denis #define CRTC_TEST_DEBUG_DATA__CRTC_TEST_DEBUG_DATA_MASK 0xffffffffL 2318de2bdb3dSTom St Denis #define CRTC_TEST_DEBUG_DATA__CRTC_TEST_DEBUG_DATA__SHIFT 0x00000000 2319de2bdb3dSTom St Denis #define CRTC_TEST_DEBUG_INDEX__CRTC_TEST_DEBUG_INDEX_MASK 0x000000ffL 2320de2bdb3dSTom St Denis #define CRTC_TEST_DEBUG_INDEX__CRTC_TEST_DEBUG_INDEX__SHIFT 0x00000000 2321de2bdb3dSTom St Denis #define CRTC_TEST_DEBUG_INDEX__CRTC_TEST_DEBUG_WRITE_EN_MASK 0x00000100L 2322de2bdb3dSTom St Denis #define CRTC_TEST_DEBUG_INDEX__CRTC_TEST_DEBUG_WRITE_EN__SHIFT 0x00000008 2323de2bdb3dSTom St Denis #define CRTC_TEST_PATTERN_COLOR__CRTC_TEST_PATTERN_DATA_MASK 0x0000ffffL 2324de2bdb3dSTom St Denis #define CRTC_TEST_PATTERN_COLOR__CRTC_TEST_PATTERN_DATA__SHIFT 0x00000000 2325de2bdb3dSTom St Denis #define CRTC_TEST_PATTERN_COLOR__CRTC_TEST_PATTERN_MASK_MASK 0x003f0000L 2326de2bdb3dSTom St Denis #define CRTC_TEST_PATTERN_COLOR__CRTC_TEST_PATTERN_MASK__SHIFT 0x00000010 2327de2bdb3dSTom St Denis #define CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_COLOR_FORMAT_MASK 0xff000000L 2328de2bdb3dSTom St Denis #define CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_COLOR_FORMAT__SHIFT 0x00000018 2329de2bdb3dSTom St Denis #define CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_DYNAMIC_RANGE_MASK 0x00010000L 2330de2bdb3dSTom St Denis #define CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_DYNAMIC_RANGE__SHIFT 0x00000010 2331de2bdb3dSTom St Denis #define CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_EN_MASK 0x00000001L 2332de2bdb3dSTom St Denis #define CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_EN__SHIFT 0x00000000 2333de2bdb3dSTom St Denis #define CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_MODE_MASK 0x00000700L 2334de2bdb3dSTom St Denis #define CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_MODE__SHIFT 0x00000008 2335de2bdb3dSTom St Denis #define CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_HRES_MASK 0x0000f000L 2336de2bdb3dSTom St Denis #define CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_HRES__SHIFT 0x0000000c 2337de2bdb3dSTom St Denis #define CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_INC0_MASK 0x0000000fL 2338de2bdb3dSTom St Denis #define CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_INC0__SHIFT 0x00000000 2339de2bdb3dSTom St Denis #define CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_INC1_MASK 0x000000f0L 2340de2bdb3dSTom St Denis #define CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_INC1__SHIFT 0x00000004 2341de2bdb3dSTom St Denis #define CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_RAMP0_OFFSET_MASK 0xffff0000L 2342de2bdb3dSTom St Denis #define CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_RAMP0_OFFSET__SHIFT 0x00000010 2343de2bdb3dSTom St Denis #define CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_VRES_MASK 0x00000f00L 2344de2bdb3dSTom St Denis #define CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_VRES__SHIFT 0x00000008 2345de2bdb3dSTom St Denis #define CRTC_TRIGA_CNTL__CRTC_TRIGA_CLEAR_MASK 0x80000000L 2346de2bdb3dSTom St Denis #define CRTC_TRIGA_CNTL__CRTC_TRIGA_CLEAR__SHIFT 0x0000001f 2347de2bdb3dSTom St Denis #define CRTC_TRIGA_CNTL__CRTC_TRIGA_DELAY_MASK 0x1f000000L 2348de2bdb3dSTom St Denis #define CRTC_TRIGA_CNTL__CRTC_TRIGA_DELAY__SHIFT 0x00000018 2349de2bdb3dSTom St Denis #define CRTC_TRIGA_CNTL__CRTC_TRIGA_FALLING_EDGE_DETECT_CNTL_MASK 0x00030000L 2350de2bdb3dSTom St Denis #define CRTC_TRIGA_CNTL__CRTC_TRIGA_FALLING_EDGE_DETECT_CNTL__SHIFT 0x00000010 2351de2bdb3dSTom St Denis #define CRTC_TRIGA_CNTL__CRTC_TRIGA_FREQUENCY_SELECT_MASK 0x00300000L 2352de2bdb3dSTom St Denis #define CRTC_TRIGA_CNTL__CRTC_TRIGA_FREQUENCY_SELECT__SHIFT 0x00000014 2353de2bdb3dSTom St Denis #define CRTC_TRIGA_CNTL__CRTC_TRIGA_INPUT_STATUS_MASK 0x00000200L 2354de2bdb3dSTom St Denis #define CRTC_TRIGA_CNTL__CRTC_TRIGA_INPUT_STATUS__SHIFT 0x00000009 2355de2bdb3dSTom St Denis #define CRTC_TRIGA_CNTL__CRTC_TRIGA_OCCURRED_MASK 0x00000800L 2356de2bdb3dSTom St Denis #define CRTC_TRIGA_CNTL__CRTC_TRIGA_OCCURRED__SHIFT 0x0000000b 2357de2bdb3dSTom St Denis #define CRTC_TRIGA_CNTL__CRTC_TRIGA_POLARITY_SELECT_MASK 0x000000e0L 2358de2bdb3dSTom St Denis #define CRTC_TRIGA_CNTL__CRTC_TRIGA_POLARITY_SELECT__SHIFT 0x00000005 2359de2bdb3dSTom St Denis #define CRTC_TRIGA_CNTL__CRTC_TRIGA_POLARITY_STATUS_MASK 0x00000400L 2360de2bdb3dSTom St Denis #define CRTC_TRIGA_CNTL__CRTC_TRIGA_POLARITY_STATUS__SHIFT 0x0000000a 2361de2bdb3dSTom St Denis #define CRTC_TRIGA_CNTL__CRTC_TRIGA_RESYNC_BYPASS_EN_MASK 0x00000100L 2362de2bdb3dSTom St Denis #define CRTC_TRIGA_CNTL__CRTC_TRIGA_RESYNC_BYPASS_EN__SHIFT 0x00000008 2363de2bdb3dSTom St Denis #define CRTC_TRIGA_CNTL__CRTC_TRIGA_RISING_EDGE_DETECT_CNTL_MASK 0x00003000L 2364de2bdb3dSTom St Denis #define CRTC_TRIGA_CNTL__CRTC_TRIGA_RISING_EDGE_DETECT_CNTL__SHIFT 0x0000000c 2365de2bdb3dSTom St Denis #define CRTC_TRIGA_CNTL__CRTC_TRIGA_SOURCE_SELECT_MASK 0x0000001fL 2366de2bdb3dSTom St Denis #define CRTC_TRIGA_CNTL__CRTC_TRIGA_SOURCE_SELECT__SHIFT 0x00000000 2367de2bdb3dSTom St Denis #define CRTC_TRIGA_MANUAL_TRIG__CRTC_TRIGA_MANUAL_TRIG_MASK 0x00000001L 2368de2bdb3dSTom St Denis #define CRTC_TRIGA_MANUAL_TRIG__CRTC_TRIGA_MANUAL_TRIG__SHIFT 0x00000000 2369de2bdb3dSTom St Denis #define CRTC_TRIGB_CNTL__CRTC_TRIGB_CLEAR_MASK 0x80000000L 2370de2bdb3dSTom St Denis #define CRTC_TRIGB_CNTL__CRTC_TRIGB_CLEAR__SHIFT 0x0000001f 2371de2bdb3dSTom St Denis #define CRTC_TRIGB_CNTL__CRTC_TRIGB_DELAY_MASK 0x1f000000L 2372de2bdb3dSTom St Denis #define CRTC_TRIGB_CNTL__CRTC_TRIGB_DELAY__SHIFT 0x00000018 2373de2bdb3dSTom St Denis #define CRTC_TRIGB_CNTL__CRTC_TRIGB_FALLING_EDGE_DETECT_CNTL_MASK 0x00030000L 2374de2bdb3dSTom St Denis #define CRTC_TRIGB_CNTL__CRTC_TRIGB_FALLING_EDGE_DETECT_CNTL__SHIFT 0x00000010 2375de2bdb3dSTom St Denis #define CRTC_TRIGB_CNTL__CRTC_TRIGB_FREQUENCY_SELECT_MASK 0x00300000L 2376de2bdb3dSTom St Denis #define CRTC_TRIGB_CNTL__CRTC_TRIGB_FREQUENCY_SELECT__SHIFT 0x00000014 2377de2bdb3dSTom St Denis #define CRTC_TRIGB_CNTL__CRTC_TRIGB_INPUT_STATUS_MASK 0x00000200L 2378de2bdb3dSTom St Denis #define CRTC_TRIGB_CNTL__CRTC_TRIGB_INPUT_STATUS__SHIFT 0x00000009 2379de2bdb3dSTom St Denis #define CRTC_TRIGB_CNTL__CRTC_TRIGB_OCCURRED_MASK 0x00000800L 2380de2bdb3dSTom St Denis #define CRTC_TRIGB_CNTL__CRTC_TRIGB_OCCURRED__SHIFT 0x0000000b 2381de2bdb3dSTom St Denis #define CRTC_TRIGB_CNTL__CRTC_TRIGB_POLARITY_SELECT_MASK 0x000000e0L 2382de2bdb3dSTom St Denis #define CRTC_TRIGB_CNTL__CRTC_TRIGB_POLARITY_SELECT__SHIFT 0x00000005 2383de2bdb3dSTom St Denis #define CRTC_TRIGB_CNTL__CRTC_TRIGB_POLARITY_STATUS_MASK 0x00000400L 2384de2bdb3dSTom St Denis #define CRTC_TRIGB_CNTL__CRTC_TRIGB_POLARITY_STATUS__SHIFT 0x0000000a 2385de2bdb3dSTom St Denis #define CRTC_TRIGB_CNTL__CRTC_TRIGB_RESYNC_BYPASS_EN_MASK 0x00000100L 2386de2bdb3dSTom St Denis #define CRTC_TRIGB_CNTL__CRTC_TRIGB_RESYNC_BYPASS_EN__SHIFT 0x00000008 2387de2bdb3dSTom St Denis #define CRTC_TRIGB_CNTL__CRTC_TRIGB_RISING_EDGE_DETECT_CNTL_MASK 0x00003000L 2388de2bdb3dSTom St Denis #define CRTC_TRIGB_CNTL__CRTC_TRIGB_RISING_EDGE_DETECT_CNTL__SHIFT 0x0000000c 2389de2bdb3dSTom St Denis #define CRTC_TRIGB_CNTL__CRTC_TRIGB_SOURCE_SELECT_MASK 0x0000001fL 2390de2bdb3dSTom St Denis #define CRTC_TRIGB_CNTL__CRTC_TRIGB_SOURCE_SELECT__SHIFT 0x00000000 2391de2bdb3dSTom St Denis #define CRTC_TRIGB_MANUAL_TRIG__CRTC_TRIGB_MANUAL_TRIG_MASK 0x00000001L 2392de2bdb3dSTom St Denis #define CRTC_TRIGB_MANUAL_TRIG__CRTC_TRIGB_MANUAL_TRIG__SHIFT 0x00000000 2393de2bdb3dSTom St Denis #define CRTC_UPDATE_LOCK__CRTC_UPDATE_LOCK_MASK 0x00000001L 2394de2bdb3dSTom St Denis #define CRTC_UPDATE_LOCK__CRTC_UPDATE_LOCK__SHIFT 0x00000000 2395de2bdb3dSTom St Denis #define CRTC_VBI_END__CRTC_VBI_H_END_MASK 0x1fff0000L 2396de2bdb3dSTom St Denis #define CRTC_VBI_END__CRTC_VBI_H_END__SHIFT 0x00000010 2397de2bdb3dSTom St Denis #define CRTC_VBI_END__CRTC_VBI_V_END_MASK 0x00001fffL 2398de2bdb3dSTom St Denis #define CRTC_VBI_END__CRTC_VBI_V_END__SHIFT 0x00000000 2399de2bdb3dSTom St Denis #define CRTC_V_BLANK_START_END__CRTC_V_BLANK_END_MASK 0x1fff0000L 2400de2bdb3dSTom St Denis #define CRTC_V_BLANK_START_END__CRTC_V_BLANK_END__SHIFT 0x00000010 2401de2bdb3dSTom St Denis #define CRTC_V_BLANK_START_END__CRTC_V_BLANK_START_MASK 0x00001fffL 2402de2bdb3dSTom St Denis #define CRTC_V_BLANK_START_END__CRTC_V_BLANK_START__SHIFT 0x00000000 2403de2bdb3dSTom St Denis #define CRTC_VERT_SYNC_CONTROL__CRTC_AUTO_FORCE_VSYNC_MODE_MASK 0x00030000L 2404de2bdb3dSTom St Denis #define CRTC_VERT_SYNC_CONTROL__CRTC_AUTO_FORCE_VSYNC_MODE__SHIFT 0x00000010 2405de2bdb3dSTom St Denis #define CRTC_VERT_SYNC_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_CLEAR_MASK 0x00000100L 2406de2bdb3dSTom St Denis #define CRTC_VERT_SYNC_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_CLEAR__SHIFT 0x00000008 2407de2bdb3dSTom St Denis #define CRTC_VERT_SYNC_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_OCCURRED_MASK 0x00000001L 2408de2bdb3dSTom St Denis #define CRTC_VERT_SYNC_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_OCCURRED__SHIFT 0x00000000 2409de2bdb3dSTom St Denis #define CRTC_VGA_PARAMETER_CAPTURE_MODE__CRTC_VGA_PARAMETER_CAPTURE_MODE_MASK 0x00000001L 2410de2bdb3dSTom St Denis #define CRTC_VGA_PARAMETER_CAPTURE_MODE__CRTC_VGA_PARAMETER_CAPTURE_MODE__SHIFT 0x00000000 2411de2bdb3dSTom St Denis #define CRTC_V_SYNC_A_CNTL__CRTC_V_SYNC_A_POL_MASK 0x00000001L 2412de2bdb3dSTom St Denis #define CRTC_V_SYNC_A_CNTL__CRTC_V_SYNC_A_POL__SHIFT 0x00000000 2413de2bdb3dSTom St Denis #define CRTC_V_SYNC_A__CRTC_V_SYNC_A_END_MASK 0x1fff0000L 2414de2bdb3dSTom St Denis #define CRTC_V_SYNC_A__CRTC_V_SYNC_A_END__SHIFT 0x00000010 2415de2bdb3dSTom St Denis #define CRTC_V_SYNC_A__CRTC_V_SYNC_A_START_MASK 0x00001fffL 2416de2bdb3dSTom St Denis #define CRTC_V_SYNC_A__CRTC_V_SYNC_A_START__SHIFT 0x00000000 2417de2bdb3dSTom St Denis #define CRTC_V_SYNC_B_CNTL__CRTC_V_SYNC_B_POL_MASK 0x00000001L 2418de2bdb3dSTom St Denis #define CRTC_V_SYNC_B_CNTL__CRTC_V_SYNC_B_POL__SHIFT 0x00000000 2419de2bdb3dSTom St Denis #define CRTC_V_SYNC_B__CRTC_V_SYNC_B_END_MASK 0x1fff0000L 2420de2bdb3dSTom St Denis #define CRTC_V_SYNC_B__CRTC_V_SYNC_B_END__SHIFT 0x00000010 2421de2bdb3dSTom St Denis #define CRTC_V_SYNC_B__CRTC_V_SYNC_B_START_MASK 0x00001fffL 2422de2bdb3dSTom St Denis #define CRTC_V_SYNC_B__CRTC_V_SYNC_B_START__SHIFT 0x00000000 2423de2bdb3dSTom St Denis #define CRTC_VSYNC_NOM_INT_STATUS__CRTC_VSYNC_NOM_INT_CLEAR_MASK 0x00000010L 2424de2bdb3dSTom St Denis #define CRTC_VSYNC_NOM_INT_STATUS__CRTC_VSYNC_NOM_INT_CLEAR__SHIFT 0x00000004 2425de2bdb3dSTom St Denis #define CRTC_VSYNC_NOM_INT_STATUS__CRTC_VSYNC_NOM_MASK 0x00000001L 2426de2bdb3dSTom St Denis #define CRTC_VSYNC_NOM_INT_STATUS__CRTC_VSYNC_NOM__SHIFT 0x00000000 2427de2bdb3dSTom St Denis #define CRTC_V_TOTAL_CONTROL__CRTC_FORCE_LOCK_ON_EVENT_MASK 0x00000100L 2428de2bdb3dSTom St Denis #define CRTC_V_TOTAL_CONTROL__CRTC_FORCE_LOCK_ON_EVENT__SHIFT 0x00000008 2429de2bdb3dSTom St Denis #define CRTC_V_TOTAL_CONTROL__CRTC_FORCE_LOCK_TO_MASTER_VSYNC_MASK 0x00001000L 2430de2bdb3dSTom St Denis #define CRTC_V_TOTAL_CONTROL__CRTC_FORCE_LOCK_TO_MASTER_VSYNC__SHIFT 0x0000000c 2431de2bdb3dSTom St Denis #define CRTC_V_TOTAL_CONTROL__CRTC_SET_V_TOTAL_MIN_MASK_MASK 0xffff0000L 2432de2bdb3dSTom St Denis #define CRTC_V_TOTAL_CONTROL__CRTC_SET_V_TOTAL_MIN_MASK__SHIFT 0x00000010 2433de2bdb3dSTom St Denis #define CRTC_V_TOTAL_CONTROL__CRTC_V_TOTAL_MAX_SEL_MASK 0x00000010L 2434de2bdb3dSTom St Denis #define CRTC_V_TOTAL_CONTROL__CRTC_V_TOTAL_MAX_SEL__SHIFT 0x00000004 2435de2bdb3dSTom St Denis #define CRTC_V_TOTAL_CONTROL__CRTC_V_TOTAL_MIN_SEL_MASK 0x00000001L 2436de2bdb3dSTom St Denis #define CRTC_V_TOTAL_CONTROL__CRTC_V_TOTAL_MIN_SEL__SHIFT 0x00000000 2437de2bdb3dSTom St Denis #define CRTC_V_TOTAL__CRTC_V_TOTAL_MASK 0x00001fffL 2438de2bdb3dSTom St Denis #define CRTC_V_TOTAL__CRTC_V_TOTAL__SHIFT 0x00000000 2439de2bdb3dSTom St Denis #define CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK_MASK 0x00000100L 2440de2bdb3dSTom St Denis #define CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK__SHIFT 0x00000008 2441de2bdb3dSTom St Denis #define CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK 0x00000010L 2442de2bdb3dSTom St Denis #define CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT 0x00000004 2443de2bdb3dSTom St Denis #define CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_MASK 0x00000001L 2444de2bdb3dSTom St Denis #define CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_MSK_MASK 0x00001000L 2445de2bdb3dSTom St Denis #define CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_MSK__SHIFT 0x0000000c 2446de2bdb3dSTom St Denis #define CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED__SHIFT 0x00000000 2447de2bdb3dSTom St Denis #define CRTC_V_TOTAL_MAX__CRTC_ALLOW_VBLANK_EXTENSION_FOR_MC_TRAINING_MASK 0x00010000L 2448de2bdb3dSTom St Denis #define CRTC_V_TOTAL_MAX__CRTC_ALLOW_VBLANK_EXTENSION_FOR_MC_TRAINING__SHIFT 0x00000010 2449de2bdb3dSTom St Denis #define CRTC_V_TOTAL_MAX__CRTC_V_TOTAL_MAX_MASK 0x00001fffL 2450de2bdb3dSTom St Denis #define CRTC_V_TOTAL_MAX__CRTC_V_TOTAL_MAX__SHIFT 0x00000000 2451de2bdb3dSTom St Denis #define CRTC_V_TOTAL_MIN__CRTC_V_TOTAL_MIN_MASK 0x00001fffL 2452de2bdb3dSTom St Denis #define CRTC_V_TOTAL_MIN__CRTC_V_TOTAL_MIN__SHIFT 0x00000000 2453de2bdb3dSTom St Denis #define CRTC_V_UPDATE_INT_STATUS__CRTC_V_UPDATE_INT_CLEAR_MASK 0x00000100L 2454de2bdb3dSTom St Denis #define CRTC_V_UPDATE_INT_STATUS__CRTC_V_UPDATE_INT_CLEAR__SHIFT 0x00000008 2455de2bdb3dSTom St Denis #define CRTC_V_UPDATE_INT_STATUS__CRTC_V_UPDATE_INT_OCCURRED_MASK 0x00000001L 2456de2bdb3dSTom St Denis #define CRTC_V_UPDATE_INT_STATUS__CRTC_V_UPDATE_INT_OCCURRED__SHIFT 0x00000000 2457de2bdb3dSTom St Denis #define CUR_COLOR1__CUR_COLOR1_BLUE_MASK 0x000000ffL 2458de2bdb3dSTom St Denis #define CUR_COLOR1__CUR_COLOR1_BLUE__SHIFT 0x00000000 2459de2bdb3dSTom St Denis #define CUR_COLOR1__CUR_COLOR1_GREEN_MASK 0x0000ff00L 2460de2bdb3dSTom St Denis #define CUR_COLOR1__CUR_COLOR1_GREEN__SHIFT 0x00000008 2461de2bdb3dSTom St Denis #define CUR_COLOR1__CUR_COLOR1_RED_MASK 0x00ff0000L 2462de2bdb3dSTom St Denis #define CUR_COLOR1__CUR_COLOR1_RED__SHIFT 0x00000010 2463de2bdb3dSTom St Denis #define CUR_COLOR2__CUR_COLOR2_BLUE_MASK 0x000000ffL 2464de2bdb3dSTom St Denis #define CUR_COLOR2__CUR_COLOR2_BLUE__SHIFT 0x00000000 2465de2bdb3dSTom St Denis #define CUR_COLOR2__CUR_COLOR2_GREEN_MASK 0x0000ff00L 2466de2bdb3dSTom St Denis #define CUR_COLOR2__CUR_COLOR2_GREEN__SHIFT 0x00000008 2467de2bdb3dSTom St Denis #define CUR_COLOR2__CUR_COLOR2_RED_MASK 0x00ff0000L 2468de2bdb3dSTom St Denis #define CUR_COLOR2__CUR_COLOR2_RED__SHIFT 0x00000010 2469de2bdb3dSTom St Denis #define CUR_CONTROL__CUR_INV_TRANS_CLAMP_MASK 0x00000010L 2470de2bdb3dSTom St Denis #define CUR_CONTROL__CUR_INV_TRANS_CLAMP__SHIFT 0x00000004 2471de2bdb3dSTom St Denis #define CUR_CONTROL__CURSOR_2X_MAGNIFY_MASK 0x00010000L 2472de2bdb3dSTom St Denis #define CUR_CONTROL__CURSOR_2X_MAGNIFY__SHIFT 0x00000010 2473de2bdb3dSTom St Denis #define CUR_CONTROL__CURSOR_EN_MASK 0x00000001L 2474de2bdb3dSTom St Denis #define CUR_CONTROL__CURSOR_EN__SHIFT 0x00000000 2475de2bdb3dSTom St Denis #define CUR_CONTROL__CURSOR_FORCE_MC_ON_MASK 0x00100000L 2476de2bdb3dSTom St Denis #define CUR_CONTROL__CURSOR_FORCE_MC_ON__SHIFT 0x00000014 2477de2bdb3dSTom St Denis #define CUR_CONTROL__CURSOR_MODE_MASK 0x00000300L 2478de2bdb3dSTom St Denis #define CUR_CONTROL__CURSOR_MODE__SHIFT 0x00000008 2479de2bdb3dSTom St Denis #define CUR_CONTROL__CURSOR_URGENT_CONTROL_MASK 0x07000000L 2480de2bdb3dSTom St Denis #define CUR_CONTROL__CURSOR_URGENT_CONTROL__SHIFT 0x00000018 2481de2bdb3dSTom St Denis #define CUR_HOT_SPOT__CURSOR_HOT_SPOT_X_MASK 0x003f0000L 2482de2bdb3dSTom St Denis #define CUR_HOT_SPOT__CURSOR_HOT_SPOT_X__SHIFT 0x00000010 2483de2bdb3dSTom St Denis #define CUR_HOT_SPOT__CURSOR_HOT_SPOT_Y_MASK 0x0000003fL 2484de2bdb3dSTom St Denis #define CUR_HOT_SPOT__CURSOR_HOT_SPOT_Y__SHIFT 0x00000000 2485de2bdb3dSTom St Denis #define CUR_POSITION__CURSOR_X_POSITION_MASK 0x3fff0000L 2486de2bdb3dSTom St Denis #define CUR_POSITION__CURSOR_X_POSITION__SHIFT 0x00000010 2487de2bdb3dSTom St Denis #define CUR_POSITION__CURSOR_Y_POSITION_MASK 0x00003fffL 2488de2bdb3dSTom St Denis #define CUR_POSITION__CURSOR_Y_POSITION__SHIFT 0x00000000 2489de2bdb3dSTom St Denis #define CUR_REQUEST_FILTER_CNTL__CUR_REQUEST_FILTER_DIS_MASK 0x00000001L 2490de2bdb3dSTom St Denis #define CUR_REQUEST_FILTER_CNTL__CUR_REQUEST_FILTER_DIS__SHIFT 0x00000000 2491de2bdb3dSTom St Denis #define CUR_SIZE__CURSOR_HEIGHT_MASK 0x0000003fL 2492de2bdb3dSTom St Denis #define CUR_SIZE__CURSOR_HEIGHT__SHIFT 0x00000000 2493de2bdb3dSTom St Denis #define CUR_SIZE__CURSOR_WIDTH_MASK 0x003f0000L 2494de2bdb3dSTom St Denis #define CUR_SIZE__CURSOR_WIDTH__SHIFT 0x00000010 2495de2bdb3dSTom St Denis #define CUR_SURFACE_ADDRESS__CURSOR_SURFACE_ADDRESS_MASK 0xffffffffL 2496de2bdb3dSTom St Denis #define CUR_SURFACE_ADDRESS__CURSOR_SURFACE_ADDRESS__SHIFT 0x00000000 2497de2bdb3dSTom St Denis #define CUR_SURFACE_ADDRESS_HIGH__CURSOR_SURFACE_ADDRESS_HIGH_MASK 0x000000ffL 2498de2bdb3dSTom St Denis #define CUR_SURFACE_ADDRESS_HIGH__CURSOR_SURFACE_ADDRESS_HIGH__SHIFT 0x00000000 2499de2bdb3dSTom St Denis #define CUR_UPDATE__CURSOR_DISABLE_MULTIPLE_UPDATE_MASK 0x01000000L 2500de2bdb3dSTom St Denis #define CUR_UPDATE__CURSOR_DISABLE_MULTIPLE_UPDATE__SHIFT 0x00000018 2501de2bdb3dSTom St Denis #define CUR_UPDATE__CURSOR_UPDATE_LOCK_MASK 0x00010000L 2502de2bdb3dSTom St Denis #define CUR_UPDATE__CURSOR_UPDATE_LOCK__SHIFT 0x00000010 2503de2bdb3dSTom St Denis #define CUR_UPDATE__CURSOR_UPDATE_PENDING_MASK 0x00000001L 2504de2bdb3dSTom St Denis #define CUR_UPDATE__CURSOR_UPDATE_PENDING__SHIFT 0x00000000 2505de2bdb3dSTom St Denis #define CUR_UPDATE__CURSOR_UPDATE_TAKEN_MASK 0x00000002L 2506de2bdb3dSTom St Denis #define CUR_UPDATE__CURSOR_UPDATE_TAKEN__SHIFT 0x00000001 2507de2bdb3dSTom St Denis #define D1VGA_CONTROL__D1VGA_MODE_ENABLE_MASK 0x00000001L 2508de2bdb3dSTom St Denis #define D1VGA_CONTROL__D1VGA_MODE_ENABLE__SHIFT 0x00000000 2509de2bdb3dSTom St Denis #define D1VGA_CONTROL__D1VGA_OVERSCAN_COLOR_EN_MASK 0x00010000L 2510de2bdb3dSTom St Denis #define D1VGA_CONTROL__D1VGA_OVERSCAN_COLOR_EN__SHIFT 0x00000010 2511de2bdb3dSTom St Denis #define D1VGA_CONTROL__D1VGA_ROTATE_MASK 0x03000000L 2512de2bdb3dSTom St Denis #define D1VGA_CONTROL__D1VGA_ROTATE__SHIFT 0x00000018 2513de2bdb3dSTom St Denis #define D1VGA_CONTROL__D1VGA_SYNC_POLARITY_SELECT_MASK 0x00000200L 2514de2bdb3dSTom St Denis #define D1VGA_CONTROL__D1VGA_SYNC_POLARITY_SELECT__SHIFT 0x00000009 2515de2bdb3dSTom St Denis #define D1VGA_CONTROL__D1VGA_TIMING_SELECT_MASK 0x00000100L 2516de2bdb3dSTom St Denis #define D1VGA_CONTROL__D1VGA_TIMING_SELECT__SHIFT 0x00000008 2517de2bdb3dSTom St Denis #define D2VGA_CONTROL__D2VGA_MODE_ENABLE_MASK 0x00000001L 2518de2bdb3dSTom St Denis #define D2VGA_CONTROL__D2VGA_MODE_ENABLE__SHIFT 0x00000000 2519de2bdb3dSTom St Denis #define D2VGA_CONTROL__D2VGA_OVERSCAN_COLOR_EN_MASK 0x00010000L 2520de2bdb3dSTom St Denis #define D2VGA_CONTROL__D2VGA_OVERSCAN_COLOR_EN__SHIFT 0x00000010 2521de2bdb3dSTom St Denis #define D2VGA_CONTROL__D2VGA_ROTATE_MASK 0x03000000L 2522de2bdb3dSTom St Denis #define D2VGA_CONTROL__D2VGA_ROTATE__SHIFT 0x00000018 2523de2bdb3dSTom St Denis #define D2VGA_CONTROL__D2VGA_SYNC_POLARITY_SELECT_MASK 0x00000200L 2524de2bdb3dSTom St Denis #define D2VGA_CONTROL__D2VGA_SYNC_POLARITY_SELECT__SHIFT 0x00000009 2525de2bdb3dSTom St Denis #define D2VGA_CONTROL__D2VGA_TIMING_SELECT_MASK 0x00000100L 2526de2bdb3dSTom St Denis #define D2VGA_CONTROL__D2VGA_TIMING_SELECT__SHIFT 0x00000008 2527de2bdb3dSTom St Denis #define D3VGA_CONTROL__D3VGA_MODE_ENABLE_MASK 0x00000001L 2528de2bdb3dSTom St Denis #define D3VGA_CONTROL__D3VGA_MODE_ENABLE__SHIFT 0x00000000 2529de2bdb3dSTom St Denis #define D3VGA_CONTROL__D3VGA_OVERSCAN_COLOR_EN_MASK 0x00010000L 2530de2bdb3dSTom St Denis #define D3VGA_CONTROL__D3VGA_OVERSCAN_COLOR_EN__SHIFT 0x00000010 2531de2bdb3dSTom St Denis #define D3VGA_CONTROL__D3VGA_ROTATE_MASK 0x03000000L 2532de2bdb3dSTom St Denis #define D3VGA_CONTROL__D3VGA_ROTATE__SHIFT 0x00000018 2533de2bdb3dSTom St Denis #define D3VGA_CONTROL__D3VGA_SYNC_POLARITY_SELECT_MASK 0x00000200L 2534de2bdb3dSTom St Denis #define D3VGA_CONTROL__D3VGA_SYNC_POLARITY_SELECT__SHIFT 0x00000009 2535de2bdb3dSTom St Denis #define D3VGA_CONTROL__D3VGA_TIMING_SELECT_MASK 0x00000100L 2536de2bdb3dSTom St Denis #define D3VGA_CONTROL__D3VGA_TIMING_SELECT__SHIFT 0x00000008 2537de2bdb3dSTom St Denis #define D4VGA_CONTROL__D4VGA_MODE_ENABLE_MASK 0x00000001L 2538de2bdb3dSTom St Denis #define D4VGA_CONTROL__D4VGA_MODE_ENABLE__SHIFT 0x00000000 2539de2bdb3dSTom St Denis #define D4VGA_CONTROL__D4VGA_OVERSCAN_COLOR_EN_MASK 0x00010000L 2540de2bdb3dSTom St Denis #define D4VGA_CONTROL__D4VGA_OVERSCAN_COLOR_EN__SHIFT 0x00000010 2541de2bdb3dSTom St Denis #define D4VGA_CONTROL__D4VGA_ROTATE_MASK 0x03000000L 2542de2bdb3dSTom St Denis #define D4VGA_CONTROL__D4VGA_ROTATE__SHIFT 0x00000018 2543de2bdb3dSTom St Denis #define D4VGA_CONTROL__D4VGA_SYNC_POLARITY_SELECT_MASK 0x00000200L 2544de2bdb3dSTom St Denis #define D4VGA_CONTROL__D4VGA_SYNC_POLARITY_SELECT__SHIFT 0x00000009 2545de2bdb3dSTom St Denis #define D4VGA_CONTROL__D4VGA_TIMING_SELECT_MASK 0x00000100L 2546de2bdb3dSTom St Denis #define D4VGA_CONTROL__D4VGA_TIMING_SELECT__SHIFT 0x00000008 2547de2bdb3dSTom St Denis #define D5VGA_CONTROL__D5VGA_MODE_ENABLE_MASK 0x00000001L 2548de2bdb3dSTom St Denis #define D5VGA_CONTROL__D5VGA_MODE_ENABLE__SHIFT 0x00000000 2549de2bdb3dSTom St Denis #define D5VGA_CONTROL__D5VGA_OVERSCAN_COLOR_EN_MASK 0x00010000L 2550de2bdb3dSTom St Denis #define D5VGA_CONTROL__D5VGA_OVERSCAN_COLOR_EN__SHIFT 0x00000010 2551de2bdb3dSTom St Denis #define D5VGA_CONTROL__D5VGA_ROTATE_MASK 0x03000000L 2552de2bdb3dSTom St Denis #define D5VGA_CONTROL__D5VGA_ROTATE__SHIFT 0x00000018 2553de2bdb3dSTom St Denis #define D5VGA_CONTROL__D5VGA_SYNC_POLARITY_SELECT_MASK 0x00000200L 2554de2bdb3dSTom St Denis #define D5VGA_CONTROL__D5VGA_SYNC_POLARITY_SELECT__SHIFT 0x00000009 2555de2bdb3dSTom St Denis #define D5VGA_CONTROL__D5VGA_TIMING_SELECT_MASK 0x00000100L 2556de2bdb3dSTom St Denis #define D5VGA_CONTROL__D5VGA_TIMING_SELECT__SHIFT 0x00000008 2557de2bdb3dSTom St Denis #define D6VGA_CONTROL__D6VGA_MODE_ENABLE_MASK 0x00000001L 2558de2bdb3dSTom St Denis #define D6VGA_CONTROL__D6VGA_MODE_ENABLE__SHIFT 0x00000000 2559de2bdb3dSTom St Denis #define D6VGA_CONTROL__D6VGA_OVERSCAN_COLOR_EN_MASK 0x00010000L 2560de2bdb3dSTom St Denis #define D6VGA_CONTROL__D6VGA_OVERSCAN_COLOR_EN__SHIFT 0x00000010 2561de2bdb3dSTom St Denis #define D6VGA_CONTROL__D6VGA_ROTATE_MASK 0x03000000L 2562de2bdb3dSTom St Denis #define D6VGA_CONTROL__D6VGA_ROTATE__SHIFT 0x00000018 2563de2bdb3dSTom St Denis #define D6VGA_CONTROL__D6VGA_SYNC_POLARITY_SELECT_MASK 0x00000200L 2564de2bdb3dSTom St Denis #define D6VGA_CONTROL__D6VGA_SYNC_POLARITY_SELECT__SHIFT 0x00000009 2565de2bdb3dSTom St Denis #define D6VGA_CONTROL__D6VGA_TIMING_SELECT_MASK 0x00000100L 2566de2bdb3dSTom St Denis #define D6VGA_CONTROL__D6VGA_TIMING_SELECT__SHIFT 0x00000008 2567de2bdb3dSTom St Denis #define DAC_AUTODETECT_CONTROL2__DAC_AUTODETECT_POWERUP_COUNTER_MASK 0x000000ffL 2568de2bdb3dSTom St Denis #define DAC_AUTODETECT_CONTROL2__DAC_AUTODETECT_POWERUP_COUNTER__SHIFT 0x00000000 2569de2bdb3dSTom St Denis #define DAC_AUTODETECT_CONTROL2__DAC_AUTODETECT_TESTMODE_MASK 0x00000100L 2570de2bdb3dSTom St Denis #define DAC_AUTODETECT_CONTROL2__DAC_AUTODETECT_TESTMODE__SHIFT 0x00000008 2571de2bdb3dSTom St Denis #define DAC_AUTODETECT_CONTROL3__DAC_AUTODET_COMPARATOR_IN_DELAY_MASK 0x000000ffL 2572de2bdb3dSTom St Denis #define DAC_AUTODETECT_CONTROL3__DAC_AUTODET_COMPARATOR_IN_DELAY__SHIFT 0x00000000 2573de2bdb3dSTom St Denis #define DAC_AUTODETECT_CONTROL3__DAC_AUTODET_COMPARATOR_OUT_DELAY_MASK 0x0000ff00L 2574de2bdb3dSTom St Denis #define DAC_AUTODETECT_CONTROL3__DAC_AUTODET_COMPARATOR_OUT_DELAY__SHIFT 0x00000008 2575de2bdb3dSTom St Denis #define DAC_AUTODETECT_CONTROL__DAC_AUTODETECT_CHECK_MASK_MASK 0x00070000L 2576de2bdb3dSTom St Denis #define DAC_AUTODETECT_CONTROL__DAC_AUTODETECT_CHECK_MASK__SHIFT 0x00000010 2577de2bdb3dSTom St Denis #define DAC_AUTODETECT_CONTROL__DAC_AUTODETECT_FRAME_TIME_COUNTER_MASK 0x0000ff00L 2578de2bdb3dSTom St Denis #define DAC_AUTODETECT_CONTROL__DAC_AUTODETECT_FRAME_TIME_COUNTER__SHIFT 0x00000008 2579de2bdb3dSTom St Denis #define DAC_AUTODETECT_CONTROL__DAC_AUTODETECT_MODE_MASK 0x00000003L 2580de2bdb3dSTom St Denis #define DAC_AUTODETECT_CONTROL__DAC_AUTODETECT_MODE__SHIFT 0x00000000 2581de2bdb3dSTom St Denis #define DAC_AUTODETECT_INT_CONTROL__DAC_AUTODETECT_ACK_MASK 0x00000001L 2582de2bdb3dSTom St Denis #define DAC_AUTODETECT_INT_CONTROL__DAC_AUTODETECT_ACK__SHIFT 0x00000000 2583de2bdb3dSTom St Denis #define DAC_AUTODETECT_INT_CONTROL__DAC_AUTODETECT_INT_ENABLE_MASK 0x00010000L 2584de2bdb3dSTom St Denis #define DAC_AUTODETECT_INT_CONTROL__DAC_AUTODETECT_INT_ENABLE__SHIFT 0x00000010 2585de2bdb3dSTom St Denis #define DAC_AUTODETECT_STATUS__DAC_AUTODETECT_BLUE_SENSE_MASK 0x03000000L 2586de2bdb3dSTom St Denis #define DAC_AUTODETECT_STATUS__DAC_AUTODETECT_BLUE_SENSE__SHIFT 0x00000018 2587de2bdb3dSTom St Denis #define DAC_AUTODETECT_STATUS__DAC_AUTODETECT_CONNECT_MASK 0x00000010L 2588de2bdb3dSTom St Denis #define DAC_AUTODETECT_STATUS__DAC_AUTODETECT_CONNECT__SHIFT 0x00000004 2589de2bdb3dSTom St Denis #define DAC_AUTODETECT_STATUS__DAC_AUTODETECT_GREEN_SENSE_MASK 0x00030000L 2590de2bdb3dSTom St Denis #define DAC_AUTODETECT_STATUS__DAC_AUTODETECT_GREEN_SENSE__SHIFT 0x00000010 2591de2bdb3dSTom St Denis #define DAC_AUTODETECT_STATUS__DAC_AUTODETECT_RED_SENSE_MASK 0x00000300L 2592de2bdb3dSTom St Denis #define DAC_AUTODETECT_STATUS__DAC_AUTODETECT_RED_SENSE__SHIFT 0x00000008 2593de2bdb3dSTom St Denis #define DAC_AUTODETECT_STATUS__DAC_AUTODETECT_STATUS_MASK 0x00000001L 2594de2bdb3dSTom St Denis #define DAC_AUTODETECT_STATUS__DAC_AUTODETECT_STATUS__SHIFT 0x00000000 2595de2bdb3dSTom St Denis #define DAC_CLK_ENABLE__DACA_CLK_ENABLE_MASK 0x00000001L 2596de2bdb3dSTom St Denis #define DAC_CLK_ENABLE__DACA_CLK_ENABLE__SHIFT 0x00000000 2597de2bdb3dSTom St Denis #define DAC_CLK_ENABLE__DACB_CLK_ENABLE_MASK 0x00000010L 2598de2bdb3dSTom St Denis #define DAC_CLK_ENABLE__DACB_CLK_ENABLE__SHIFT 0x00000004 2599de2bdb3dSTom St Denis #define DAC_COMPARATOR_ENABLE__DAC_B_ASYNC_ENABLE_MASK 0x00040000L 2600de2bdb3dSTom St Denis #define DAC_COMPARATOR_ENABLE__DAC_B_ASYNC_ENABLE__SHIFT 0x00000012 2601de2bdb3dSTom St Denis #define DAC_COMPARATOR_ENABLE__DAC_COMP_DDET_REF_EN_MASK 0x00000001L 2602de2bdb3dSTom St Denis #define DAC_COMPARATOR_ENABLE__DAC_COMP_DDET_REF_EN__SHIFT 0x00000000 2603de2bdb3dSTom St Denis #define DAC_COMPARATOR_ENABLE__DAC_COMP_SDET_REF_EN_MASK 0x00000100L 2604de2bdb3dSTom St Denis #define DAC_COMPARATOR_ENABLE__DAC_COMP_SDET_REF_EN__SHIFT 0x00000008 2605de2bdb3dSTom St Denis #define DAC_COMPARATOR_ENABLE__DAC_G_ASYNC_ENABLE_MASK 0x00020000L 2606de2bdb3dSTom St Denis #define DAC_COMPARATOR_ENABLE__DAC_G_ASYNC_ENABLE__SHIFT 0x00000011 2607de2bdb3dSTom St Denis #define DAC_COMPARATOR_ENABLE__DAC_R_ASYNC_ENABLE_MASK 0x00010000L 2608de2bdb3dSTom St Denis #define DAC_COMPARATOR_ENABLE__DAC_R_ASYNC_ENABLE__SHIFT 0x00000010 2609de2bdb3dSTom St Denis #define DAC_COMPARATOR_OUTPUT__DAC_COMPARATOR_OUTPUT_BLUE_MASK 0x00000002L 2610de2bdb3dSTom St Denis #define DAC_COMPARATOR_OUTPUT__DAC_COMPARATOR_OUTPUT_BLUE__SHIFT 0x00000001 2611de2bdb3dSTom St Denis #define DAC_COMPARATOR_OUTPUT__DAC_COMPARATOR_OUTPUT_GREEN_MASK 0x00000004L 2612de2bdb3dSTom St Denis #define DAC_COMPARATOR_OUTPUT__DAC_COMPARATOR_OUTPUT_GREEN__SHIFT 0x00000002 2613de2bdb3dSTom St Denis #define DAC_COMPARATOR_OUTPUT__DAC_COMPARATOR_OUTPUT_MASK 0x00000001L 2614de2bdb3dSTom St Denis #define DAC_COMPARATOR_OUTPUT__DAC_COMPARATOR_OUTPUT_RED_MASK 0x00000008L 2615de2bdb3dSTom St Denis #define DAC_COMPARATOR_OUTPUT__DAC_COMPARATOR_OUTPUT_RED__SHIFT 0x00000003 2616de2bdb3dSTom St Denis #define DAC_COMPARATOR_OUTPUT__DAC_COMPARATOR_OUTPUT__SHIFT 0x00000000 2617de2bdb3dSTom St Denis #define DAC_CONTROL__DAC_DFORCE_EN_MASK 0x00000001L 2618de2bdb3dSTom St Denis #define DAC_CONTROL__DAC_DFORCE_EN__SHIFT 0x00000000 2619de2bdb3dSTom St Denis #define DAC_CONTROL__DAC_TV_ENABLE_MASK 0x00000100L 2620de2bdb3dSTom St Denis #define DAC_CONTROL__DAC_TV_ENABLE__SHIFT 0x00000008 2621de2bdb3dSTom St Denis #define DAC_CONTROL__DAC_ZSCALE_SHIFT_MASK 0x00010000L 2622de2bdb3dSTom St Denis #define DAC_CONTROL__DAC_ZSCALE_SHIFT__SHIFT 0x00000010 2623de2bdb3dSTom St Denis #define DAC_CRC_CONTROL__DAC_CRC_FIELD_MASK 0x00000001L 2624de2bdb3dSTom St Denis #define DAC_CRC_CONTROL__DAC_CRC_FIELD__SHIFT 0x00000000 2625de2bdb3dSTom St Denis #define DAC_CRC_CONTROL__DAC_CRC_ONLY_BLANKb_MASK 0x00000100L 2626de2bdb3dSTom St Denis #define DAC_CRC_CONTROL__DAC_CRC_ONLY_BLANKb__SHIFT 0x00000008 2627de2bdb3dSTom St Denis #define DAC_CRC_EN__DAC_CRC_CONT_EN_MASK 0x00010000L 2628de2bdb3dSTom St Denis #define DAC_CRC_EN__DAC_CRC_CONT_EN__SHIFT 0x00000010 2629de2bdb3dSTom St Denis #define DAC_CRC_EN__DAC_CRC_EN_MASK 0x00000001L 2630de2bdb3dSTom St Denis #define DAC_CRC_EN__DAC_CRC_EN__SHIFT 0x00000000 2631de2bdb3dSTom St Denis #define DAC_CRC_SIG_CONTROL__DAC_CRC_SIG_CONTROL_MASK 0x0000003fL 2632de2bdb3dSTom St Denis #define DAC_CRC_SIG_CONTROL__DAC_CRC_SIG_CONTROL__SHIFT 0x00000000 2633de2bdb3dSTom St Denis #define DAC_CRC_SIG_CONTROL_MASK__DAC_CRC_SIG_CONTROL_MASK_MASK 0x0000003fL 2634de2bdb3dSTom St Denis #define DAC_CRC_SIG_CONTROL_MASK__DAC_CRC_SIG_CONTROL_MASK__SHIFT 0x00000000 2635de2bdb3dSTom St Denis #define DAC_CRC_SIG_RGB__DAC_CRC_SIG_BLUE_MASK 0x000003ffL 2636de2bdb3dSTom St Denis #define DAC_CRC_SIG_RGB__DAC_CRC_SIG_BLUE__SHIFT 0x00000000 2637de2bdb3dSTom St Denis #define DAC_CRC_SIG_RGB__DAC_CRC_SIG_GREEN_MASK 0x000ffc00L 2638de2bdb3dSTom St Denis #define DAC_CRC_SIG_RGB__DAC_CRC_SIG_GREEN__SHIFT 0x0000000a 2639de2bdb3dSTom St Denis #define DAC_CRC_SIG_RGB__DAC_CRC_SIG_RED_MASK 0x3ff00000L 2640de2bdb3dSTom St Denis #define DAC_CRC_SIG_RGB__DAC_CRC_SIG_RED__SHIFT 0x00000014 2641de2bdb3dSTom St Denis #define DAC_CRC_SIG_RGB_MASK__DAC_CRC_SIG_BLUE_MASK_MASK 0x000003ffL 2642de2bdb3dSTom St Denis #define DAC_CRC_SIG_RGB_MASK__DAC_CRC_SIG_BLUE_MASK__SHIFT 0x00000000 2643de2bdb3dSTom St Denis #define DAC_CRC_SIG_RGB_MASK__DAC_CRC_SIG_GREEN_MASK_MASK 0x000ffc00L 2644de2bdb3dSTom St Denis #define DAC_CRC_SIG_RGB_MASK__DAC_CRC_SIG_GREEN_MASK__SHIFT 0x0000000a 2645de2bdb3dSTom St Denis #define DAC_CRC_SIG_RGB_MASK__DAC_CRC_SIG_RED_MASK_MASK 0x3ff00000L 2646de2bdb3dSTom St Denis #define DAC_CRC_SIG_RGB_MASK__DAC_CRC_SIG_RED_MASK__SHIFT 0x00000014 2647de2bdb3dSTom St Denis #define DAC_DATA__DAC_DATA_MASK 0x0000003fL 2648de2bdb3dSTom St Denis #define DAC_DATA__DAC_DATA__SHIFT 0x00000000 2649de2bdb3dSTom St Denis #define DAC_DFT_CONFIG__DAC_DFT_CONFIG_MASK 0xffffffffL 2650de2bdb3dSTom St Denis #define DAC_DFT_CONFIG__DAC_DFT_CONFIG__SHIFT 0x00000000 2651de2bdb3dSTom St Denis #define DAC_ENABLE__DAC_ENABLE_MASK 0x00000001L 2652de2bdb3dSTom St Denis #define DAC_ENABLE__DAC_ENABLE__SHIFT 0x00000000 2653de2bdb3dSTom St Denis #define DAC_ENABLE__DAC_RESYNC_FIFO_ENABLE_MASK 0x00000002L 2654de2bdb3dSTom St Denis #define DAC_ENABLE__DAC_RESYNC_FIFO_ENABLE__SHIFT 0x00000001 2655de2bdb3dSTom St Denis #define DAC_ENABLE__DAC_RESYNC_FIFO_ERROR_ACK_MASK 0x00000020L 2656de2bdb3dSTom St Denis #define DAC_ENABLE__DAC_RESYNC_FIFO_ERROR_ACK__SHIFT 0x00000005 2657de2bdb3dSTom St Denis #define DAC_ENABLE__DAC_RESYNC_FIFO_ERROR_MASK 0x00000010L 2658de2bdb3dSTom St Denis #define DAC_ENABLE__DAC_RESYNC_FIFO_ERROR__SHIFT 0x00000004 2659de2bdb3dSTom St Denis #define DAC_ENABLE__DAC_RESYNC_FIFO_POINTER_SKEW_MASK 0x0000000cL 2660de2bdb3dSTom St Denis #define DAC_ENABLE__DAC_RESYNC_FIFO_POINTER_SKEW__SHIFT 0x00000002 2661de2bdb3dSTom St Denis #define DAC_ENABLE__DAC_RESYNC_FIFO_TVOUT_SIM_MASK 0x00000100L 2662de2bdb3dSTom St Denis #define DAC_ENABLE__DAC_RESYNC_FIFO_TVOUT_SIM__SHIFT 0x00000008 2663de2bdb3dSTom St Denis #define DAC_FIFO_STATUS__DAC_FIFO_CAL_AVERAGE_LEVEL_MASK 0x0000fc00L 2664de2bdb3dSTom St Denis #define DAC_FIFO_STATUS__DAC_FIFO_CAL_AVERAGE_LEVEL__SHIFT 0x0000000a 2665de2bdb3dSTom St Denis #define DAC_FIFO_STATUS__DAC_FIFO_CALIBRATED_MASK 0x20000000L 2666de2bdb3dSTom St Denis #define DAC_FIFO_STATUS__DAC_FIFO_CALIBRATED__SHIFT 0x0000001d 2667de2bdb3dSTom St Denis #define DAC_FIFO_STATUS__DAC_FIFO_FORCE_RECAL_AVERAGE_MASK 0x40000000L 2668de2bdb3dSTom St Denis #define DAC_FIFO_STATUS__DAC_FIFO_FORCE_RECAL_AVERAGE__SHIFT 0x0000001e 2669de2bdb3dSTom St Denis #define DAC_FIFO_STATUS__DAC_FIFO_FORCE_RECOMP_MINMAX_MASK 0x80000000L 2670de2bdb3dSTom St Denis #define DAC_FIFO_STATUS__DAC_FIFO_FORCE_RECOMP_MINMAX__SHIFT 0x0000001f 2671de2bdb3dSTom St Denis #define DAC_FIFO_STATUS__DAC_FIFO_MAXIMUM_LEVEL_MASK 0x000f0000L 2672de2bdb3dSTom St Denis #define DAC_FIFO_STATUS__DAC_FIFO_MAXIMUM_LEVEL__SHIFT 0x00000010 2673de2bdb3dSTom St Denis #define DAC_FIFO_STATUS__DAC_FIFO_MINIMUM_LEVEL_MASK 0x03c00000L 2674de2bdb3dSTom St Denis #define DAC_FIFO_STATUS__DAC_FIFO_MINIMUM_LEVEL__SHIFT 0x00000016 2675de2bdb3dSTom St Denis #define DAC_FIFO_STATUS__DAC_FIFO_OVERWRITE_LEVEL_MASK 0x000000fcL 2676de2bdb3dSTom St Denis #define DAC_FIFO_STATUS__DAC_FIFO_OVERWRITE_LEVEL__SHIFT 0x00000002 2677de2bdb3dSTom St Denis #define DAC_FIFO_STATUS__DAC_FIFO_USE_OVERWRITE_LEVEL_MASK 0x00000002L 2678de2bdb3dSTom St Denis #define DAC_FIFO_STATUS__DAC_FIFO_USE_OVERWRITE_LEVEL__SHIFT 0x00000001 2679de2bdb3dSTom St Denis #define DAC_FORCE_DATA__DAC_FORCE_DATA_MASK 0x000003ffL 2680de2bdb3dSTom St Denis #define DAC_FORCE_DATA__DAC_FORCE_DATA__SHIFT 0x00000000 2681de2bdb3dSTom St Denis #define DAC_FORCE_OUTPUT_CNTL__DAC_FORCE_DATA_EN_MASK 0x00000001L 2682de2bdb3dSTom St Denis #define DAC_FORCE_OUTPUT_CNTL__DAC_FORCE_DATA_EN__SHIFT 0x00000000 2683de2bdb3dSTom St Denis #define DAC_FORCE_OUTPUT_CNTL__DAC_FORCE_DATA_ON_BLANKb_ONLY_MASK 0x01000000L 2684de2bdb3dSTom St Denis #define DAC_FORCE_OUTPUT_CNTL__DAC_FORCE_DATA_ON_BLANKb_ONLY__SHIFT 0x00000018 2685de2bdb3dSTom St Denis #define DAC_FORCE_OUTPUT_CNTL__DAC_FORCE_DATA_SEL_MASK 0x00000700L 2686de2bdb3dSTom St Denis #define DAC_FORCE_OUTPUT_CNTL__DAC_FORCE_DATA_SEL__SHIFT 0x00000008 2687de2bdb3dSTom St Denis #define DAC_MACRO_CNTL_RESERVED0__DAC_MACRO_CNTL_RESERVED_MASK 0xffffffffL 2688de2bdb3dSTom St Denis #define DAC_MACRO_CNTL_RESERVED0__DAC_MACRO_CNTL_RESERVED__SHIFT 0x00000000 2689de2bdb3dSTom St Denis #define DAC_MACRO_CNTL_RESERVED1__DAC_MACRO_CNTL_RESERVED_MASK 0xffffffffL 2690de2bdb3dSTom St Denis #define DAC_MACRO_CNTL_RESERVED1__DAC_MACRO_CNTL_RESERVED__SHIFT 0x00000000 2691de2bdb3dSTom St Denis #define DAC_MACRO_CNTL_RESERVED2__DAC_MACRO_CNTL_RESERVED_MASK 0xffffffffL 2692de2bdb3dSTom St Denis #define DAC_MACRO_CNTL_RESERVED2__DAC_MACRO_CNTL_RESERVED__SHIFT 0x00000000 2693de2bdb3dSTom St Denis #define DAC_MACRO_CNTL_RESERVED3__DAC_MACRO_CNTL_RESERVED_MASK 0xffffffffL 2694de2bdb3dSTom St Denis #define DAC_MACRO_CNTL_RESERVED3__DAC_MACRO_CNTL_RESERVED__SHIFT 0x00000000 2695de2bdb3dSTom St Denis #define DAC_MASK__DAC_MASK_MASK 0x000000ffL 2696de2bdb3dSTom St Denis #define DAC_MASK__DAC_MASK__SHIFT 0x00000000 2697de2bdb3dSTom St Denis #define DAC_POWERDOWN__DAC_POWERDOWN_BLUE_MASK 0x00000100L 2698de2bdb3dSTom St Denis #define DAC_POWERDOWN__DAC_POWERDOWN_BLUE__SHIFT 0x00000008 2699de2bdb3dSTom St Denis #define DAC_POWERDOWN__DAC_POWERDOWN_GREEN_MASK 0x00010000L 2700de2bdb3dSTom St Denis #define DAC_POWERDOWN__DAC_POWERDOWN_GREEN__SHIFT 0x00000010 2701de2bdb3dSTom St Denis #define DAC_POWERDOWN__DAC_POWERDOWN_MASK 0x00000001L 2702de2bdb3dSTom St Denis #define DAC_POWERDOWN__DAC_POWERDOWN_RED_MASK 0x01000000L 2703de2bdb3dSTom St Denis #define DAC_POWERDOWN__DAC_POWERDOWN_RED__SHIFT 0x00000018 2704de2bdb3dSTom St Denis #define DAC_POWERDOWN__DAC_POWERDOWN__SHIFT 0x00000000 2705de2bdb3dSTom St Denis #define DAC_PWR_CNTL__DAC_BG_MODE_MASK 0x00000003L 2706de2bdb3dSTom St Denis #define DAC_PWR_CNTL__DAC_BG_MODE__SHIFT 0x00000000 2707de2bdb3dSTom St Denis #define DAC_PWR_CNTL__DAC_PWRCNTL_MASK 0x00030000L 2708de2bdb3dSTom St Denis #define DAC_PWR_CNTL__DAC_PWRCNTL__SHIFT 0x00000010 2709de2bdb3dSTom St Denis #define DAC_R_INDEX__DAC_R_INDEX_MASK 0x000000ffL 2710de2bdb3dSTom St Denis #define DAC_R_INDEX__DAC_R_INDEX__SHIFT 0x00000000 2711de2bdb3dSTom St Denis #define DAC_SOURCE_SELECT__DAC_SOURCE_SELECT_MASK 0x00000007L 2712de2bdb3dSTom St Denis #define DAC_SOURCE_SELECT__DAC_SOURCE_SELECT__SHIFT 0x00000000 2713de2bdb3dSTom St Denis #define DAC_SOURCE_SELECT__DAC_TV_SELECT_MASK 0x00000008L 2714de2bdb3dSTom St Denis #define DAC_SOURCE_SELECT__DAC_TV_SELECT__SHIFT 0x00000003 2715de2bdb3dSTom St Denis #define DAC_STEREOSYNC_SELECT__DAC_STEREOSYNC_SELECT_MASK 0x00000007L 2716de2bdb3dSTom St Denis #define DAC_STEREOSYNC_SELECT__DAC_STEREOSYNC_SELECT__SHIFT 0x00000000 2717de2bdb3dSTom St Denis #define DAC_SYNC_TRISTATE_CONTROL__DAC_HSYNCA_TRISTATE_MASK 0x00000001L 2718de2bdb3dSTom St Denis #define DAC_SYNC_TRISTATE_CONTROL__DAC_HSYNCA_TRISTATE__SHIFT 0x00000000 2719de2bdb3dSTom St Denis #define DAC_SYNC_TRISTATE_CONTROL__DAC_SYNCA_TRISTATE_MASK 0x00010000L 2720de2bdb3dSTom St Denis #define DAC_SYNC_TRISTATE_CONTROL__DAC_SYNCA_TRISTATE__SHIFT 0x00000010 2721de2bdb3dSTom St Denis #define DAC_SYNC_TRISTATE_CONTROL__DAC_VSYNCA_TRISTATE_MASK 0x00000100L 2722de2bdb3dSTom St Denis #define DAC_SYNC_TRISTATE_CONTROL__DAC_VSYNCA_TRISTATE__SHIFT 0x00000008 2723de2bdb3dSTom St Denis #define DAC_W_INDEX__DAC_W_INDEX_MASK 0x000000ffL 2724de2bdb3dSTom St Denis #define DAC_W_INDEX__DAC_W_INDEX__SHIFT 0x00000000 2725de2bdb3dSTom St Denis #define DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME_CLEAR_MASK 0x00000100L 2726de2bdb3dSTom St Denis #define DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME_CLEAR__SHIFT 0x00000008 2727de2bdb3dSTom St Denis #define DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME_MASK 0x00000001L 2728de2bdb3dSTom St Denis #define DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME__SHIFT 0x00000000 2729de2bdb3dSTom St Denis #define DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_LOCK_MASK 0x80000000L 2730de2bdb3dSTom St Denis #define DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_LOCK__SHIFT 0x0000001f 2731de2bdb3dSTom St Denis #define DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_OFFSET_0_MASK 0x07ff0000L 2732de2bdb3dSTom St Denis #define DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_OFFSET_0__SHIFT 0x00000010 2733de2bdb3dSTom St Denis #define DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_SLOPE_0_MASK 0x00007fffL 2734de2bdb3dSTom St Denis #define DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_SLOPE_0__SHIFT 0x00000000 2735de2bdb3dSTom St Denis #define DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_LOCK_MASK 0x80000000L 2736de2bdb3dSTom St Denis #define DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_LOCK__SHIFT 0x0000001f 2737de2bdb3dSTom St Denis #define DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_OFFSET_1_MASK 0x07ff0000L 2738de2bdb3dSTom St Denis #define DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_OFFSET_1__SHIFT 0x00000010 2739de2bdb3dSTom St Denis #define DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_SLOPE_1_MASK 0x00007fffL 2740de2bdb3dSTom St Denis #define DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_SLOPE_1__SHIFT 0x00000000 2741de2bdb3dSTom St Denis #define DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_LOCK_MASK 0x80000000L 2742de2bdb3dSTom St Denis #define DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_LOCK__SHIFT 0x0000001f 2743de2bdb3dSTom St Denis #define DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_OFFSET_2_MASK 0x07ff0000L 2744de2bdb3dSTom St Denis #define DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_OFFSET_2__SHIFT 0x00000010 2745de2bdb3dSTom St Denis #define DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_SLOPE_2_MASK 0x00007fffL 2746de2bdb3dSTom St Denis #define DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_SLOPE_2__SHIFT 0x00000000 2747de2bdb3dSTom St Denis #define DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_LOCK_MASK 0x80000000L 2748de2bdb3dSTom St Denis #define DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_LOCK__SHIFT 0x0000001f 2749de2bdb3dSTom St Denis #define DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_OFFSET_3_MASK 0x07ff0000L 2750de2bdb3dSTom St Denis #define DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_OFFSET_3__SHIFT 0x00000010 2751de2bdb3dSTom St Denis #define DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_SLOPE_3_MASK 0x00007fffL 2752de2bdb3dSTom St Denis #define DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_SLOPE_3__SHIFT 0x00000000 2753de2bdb3dSTom St Denis #define DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_LOCK_MASK 0x80000000L 2754de2bdb3dSTom St Denis #define DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_LOCK__SHIFT 0x0000001f 2755de2bdb3dSTom St Denis #define DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_OFFSET_4_MASK 0x07ff0000L 2756de2bdb3dSTom St Denis #define DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_OFFSET_4__SHIFT 0x00000010 2757de2bdb3dSTom St Denis #define DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_SLOPE_4_MASK 0x00007fffL 2758de2bdb3dSTom St Denis #define DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_SLOPE_4__SHIFT 0x00000000 2759de2bdb3dSTom St Denis #define DC_ABM1_ACE_THRES_12__ABM1_ACE_LOCK_MASK 0x80000000L 2760de2bdb3dSTom St Denis #define DC_ABM1_ACE_THRES_12__ABM1_ACE_LOCK__SHIFT 0x0000001f 2761de2bdb3dSTom St Denis #define DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_1_MASK 0x000003ffL 2762de2bdb3dSTom St Denis #define DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_1__SHIFT 0x00000000 2763de2bdb3dSTom St Denis #define DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_2_MASK 0x03ff0000L 2764de2bdb3dSTom St Denis #define DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_2__SHIFT 0x00000010 2765de2bdb3dSTom St Denis #define DC_ABM1_ACE_THRES_34__ABM1_ACE_DBUF_REG_UPDATE_PENDING_MASK 0x40000000L 2766de2bdb3dSTom St Denis #define DC_ABM1_ACE_THRES_34__ABM1_ACE_DBUF_REG_UPDATE_PENDING__SHIFT 0x0000001e 2767de2bdb3dSTom St Denis #define DC_ABM1_ACE_THRES_34__ABM1_ACE_IGNORE_MASTER_LOCK_EN_MASK 0x10000000L 2768de2bdb3dSTom St Denis #define DC_ABM1_ACE_THRES_34__ABM1_ACE_IGNORE_MASTER_LOCK_EN__SHIFT 0x0000001c 2769de2bdb3dSTom St Denis #define DC_ABM1_ACE_THRES_34__ABM1_ACE_LOCK_MASK 0x80000000L 2770de2bdb3dSTom St Denis #define DC_ABM1_ACE_THRES_34__ABM1_ACE_LOCK__SHIFT 0x0000001f 2771de2bdb3dSTom St Denis #define DC_ABM1_ACE_THRES_34__ABM1_ACE_READBACK_DB_REG_VALUE_EN_MASK 0x20000000L 2772de2bdb3dSTom St Denis #define DC_ABM1_ACE_THRES_34__ABM1_ACE_READBACK_DB_REG_VALUE_EN__SHIFT 0x0000001d 2773de2bdb3dSTom St Denis #define DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_3_MASK 0x000003ffL 2774de2bdb3dSTom St Denis #define DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_3__SHIFT 0x00000000 2775de2bdb3dSTom St Denis #define DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_4_MASK 0x03ff0000L 2776de2bdb3dSTom St Denis #define DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_4__SHIFT 0x00000010 2777de2bdb3dSTom St Denis #define DC_ABM1_BL_MASTER_LOCK__ABM1_BL_MASTER_LOCK_MASK 0x80000000L 2778de2bdb3dSTom St Denis #define DC_ABM1_BL_MASTER_LOCK__ABM1_BL_MASTER_LOCK__SHIFT 0x0000001f 2779de2bdb3dSTom St Denis #define DC_ABM1_CNTL__ABM1_BLANK_MODE_SUPPORT_ENABLE_MASK 0x80000000L 2780de2bdb3dSTom St Denis #define DC_ABM1_CNTL__ABM1_BLANK_MODE_SUPPORT_ENABLE__SHIFT 0x0000001f 2781de2bdb3dSTom St Denis #define DC_ABM1_CNTL__ABM1_EN_MASK 0x00000001L 2782de2bdb3dSTom St Denis #define DC_ABM1_CNTL__ABM1_EN__SHIFT 0x00000000 2783de2bdb3dSTom St Denis #define DC_ABM1_CNTL__ABM1_SOURCE_SELECT_MASK 0x00000700L 2784de2bdb3dSTom St Denis #define DC_ABM1_CNTL__ABM1_SOURCE_SELECT__SHIFT 0x00000008 2785de2bdb3dSTom St Denis #define DC_ABM1_DEBUG_MISC__ABM1_BL_FORCE_INTERRUPT_MASK 0x00010000L 2786de2bdb3dSTom St Denis #define DC_ABM1_DEBUG_MISC__ABM1_BL_FORCE_INTERRUPT__SHIFT 0x00000010 2787de2bdb3dSTom St Denis #define DC_ABM1_DEBUG_MISC__ABM1_HG_FORCE_INTERRUPT_MASK 0x00000001L 2788de2bdb3dSTom St Denis #define DC_ABM1_DEBUG_MISC__ABM1_HG_FORCE_INTERRUPT__SHIFT 0x00000000 2789de2bdb3dSTom St Denis #define DC_ABM1_DEBUG_MISC__ABM1_LS_FORCE_INTERRUPT_MASK 0x00000100L 2790de2bdb3dSTom St Denis #define DC_ABM1_DEBUG_MISC__ABM1_LS_FORCE_INTERRUPT__SHIFT 0x00000008 2791de2bdb3dSTom St Denis #define DC_ABM1_HG_BIN_1_32_SHIFT_FLAG__ABM1_HG_BIN_1_32_SHIFT_FLAG_MASK 0xffffffffL 2792de2bdb3dSTom St Denis #define DC_ABM1_HG_BIN_1_32_SHIFT_FLAG__ABM1_HG_BIN_1_32_SHIFT_FLAG__SHIFT 0x00000000 2793de2bdb3dSTom St Denis #define DC_ABM1_HG_BIN_17_24_SHIFT_INDEX__ABM1_HG_BIN_17_24_SHIFT_INDEX_MASK 0xffffffffL 2794de2bdb3dSTom St Denis #define DC_ABM1_HG_BIN_17_24_SHIFT_INDEX__ABM1_HG_BIN_17_24_SHIFT_INDEX__SHIFT 0x00000000 2795de2bdb3dSTom St Denis #define DC_ABM1_HG_BIN_1_8_SHIFT_INDEX__ABM1_HG_BIN_1_8_SHIFT_INDEX_MASK 0xffffffffL 2796de2bdb3dSTom St Denis #define DC_ABM1_HG_BIN_1_8_SHIFT_INDEX__ABM1_HG_BIN_1_8_SHIFT_INDEX__SHIFT 0x00000000 2797de2bdb3dSTom St Denis #define DC_ABM1_HG_BIN_25_32_SHIFT_INDEX__ABM1_HG_BIN_25_32_SHIFT_INDEX_MASK 0xffffffffL 2798de2bdb3dSTom St Denis #define DC_ABM1_HG_BIN_25_32_SHIFT_INDEX__ABM1_HG_BIN_25_32_SHIFT_INDEX__SHIFT 0x00000000 2799de2bdb3dSTom St Denis #define DC_ABM1_HG_BIN_9_16_SHIFT_INDEX__ABM1_HG_BIN_9_16_SHIFT_INDEX_MASK 0xffffffffL 2800de2bdb3dSTom St Denis #define DC_ABM1_HG_BIN_9_16_SHIFT_INDEX__ABM1_HG_BIN_9_16_SHIFT_INDEX__SHIFT 0x00000000 2801de2bdb3dSTom St Denis #define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_IN_PROGRESS_MASK 0x00000004L 2802de2bdb3dSTom St Denis #define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_IN_PROGRESS__SHIFT 0x00000002 2803de2bdb3dSTom St Denis #define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME_CLEAR_MASK 0x80000000L 2804de2bdb3dSTom St Denis #define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME_CLEAR__SHIFT 0x0000001f 2805de2bdb3dSTom St Denis #define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME_MASK 0x00000400L 2806de2bdb3dSTom St Denis #define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME__SHIFT 0x0000000a 2807de2bdb3dSTom St Denis #define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_IN_PROGRESS_MASK 0x00000001L 2808de2bdb3dSTom St Denis #define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_IN_PROGRESS__SHIFT 0x00000000 2809de2bdb3dSTom St Denis #define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME_CLEAR_MASK 0x00010000L 2810de2bdb3dSTom St Denis #define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME_CLEAR__SHIFT 0x00000010 2811de2bdb3dSTom St Denis #define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME_MASK 0x00000100L 2812de2bdb3dSTom St Denis #define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME__SHIFT 0x00000008 2813de2bdb3dSTom St Denis #define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_IN_PROGRESS_MASK 0x00000002L 2814de2bdb3dSTom St Denis #define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_IN_PROGRESS__SHIFT 0x00000001 2815de2bdb3dSTom St Denis #define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME_CLEAR_MASK 0x01000000L 2816de2bdb3dSTom St Denis #define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME_CLEAR__SHIFT 0x00000018 2817de2bdb3dSTom St Denis #define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME_MASK 0x00000200L 2818de2bdb3dSTom St Denis #define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME__SHIFT 0x00000009 2819de2bdb3dSTom St Denis #define DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_READBACK_DB_REG_VALUE_EN_MASK 0x00800000L 2820de2bdb3dSTom St Denis #define DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_READBACK_DB_REG_VALUE_EN__SHIFT 0x00000017 2821de2bdb3dSTom St Denis #define DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_FRAME_START_DISP_SEL_MASK 0x07000000L 2822de2bdb3dSTom St Denis #define DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_FRAME_START_DISP_SEL__SHIFT 0x00000018 2823de2bdb3dSTom St Denis #define DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_AT_FRAME_START_MASK 0x10000000L 2824de2bdb3dSTom St Denis #define DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_AT_FRAME_START__SHIFT 0x0000001c 2825de2bdb3dSTom St Denis #define DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_PENDING_MASK 0x40000000L 2826de2bdb3dSTom St Denis #define DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_PENDING__SHIFT 0x0000001e 2827de2bdb3dSTom St Denis #define DC_ABM1_HG_MISC_CTRL__ABM1_HG_BIN_BITWIDTH_SIZE_SEL_MASK 0x00030000L 2828de2bdb3dSTom St Denis #define DC_ABM1_HG_MISC_CTRL__ABM1_HG_BIN_BITWIDTH_SIZE_SEL__SHIFT 0x00000010 2829de2bdb3dSTom St Denis #define DC_ABM1_HG_MISC_CTRL__ABM1_HG_FINE_MODE_BIN_SEL_MASK 0x00001000L 2830de2bdb3dSTom St Denis #define DC_ABM1_HG_MISC_CTRL__ABM1_HG_FINE_MODE_BIN_SEL__SHIFT 0x0000000c 2831de2bdb3dSTom St Denis #define DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_IGNORE_MASTER_LOCK_EN_MASK 0x20000000L 2832de2bdb3dSTom St Denis #define DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_IGNORE_MASTER_LOCK_EN__SHIFT 0x0000001d 2833de2bdb3dSTom St Denis #define DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_REG_LOCK_MASK 0x80000000L 2834de2bdb3dSTom St Denis #define DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_REG_LOCK__SHIFT 0x0000001f 2835de2bdb3dSTom St Denis #define DC_ABM1_HG_MISC_CTRL__ABM1_HG_NUM_OF_BINS_SEL_MASK 0x00000003L 2836de2bdb3dSTom St Denis #define DC_ABM1_HG_MISC_CTRL__ABM1_HG_NUM_OF_BINS_SEL__SHIFT 0x00000000 2837de2bdb3dSTom St Denis #define DC_ABM1_HG_MISC_CTRL__ABM1_HG_VMAX_SEL_MASK 0x00000100L 2838de2bdb3dSTom St Denis #define DC_ABM1_HG_MISC_CTRL__ABM1_HG_VMAX_SEL__SHIFT 0x00000008 2839de2bdb3dSTom St Denis #define DC_ABM1_HG_MISC_CTRL__ABM1_OVR_SCAN_PIXEL_PROCESS_EN_MASK 0x00100000L 2840de2bdb3dSTom St Denis #define DC_ABM1_HG_MISC_CTRL__ABM1_OVR_SCAN_PIXEL_PROCESS_EN__SHIFT 0x00000014 2841de2bdb3dSTom St Denis #define DC_ABM1_HG_RESULT_10__ABM1_HG_RESULT_10_MASK 0xffffffffL 2842de2bdb3dSTom St Denis #define DC_ABM1_HG_RESULT_10__ABM1_HG_RESULT_10__SHIFT 0x00000000 2843de2bdb3dSTom St Denis #define DC_ABM1_HG_RESULT_11__ABM1_HG_RESULT_11_MASK 0xffffffffL 2844de2bdb3dSTom St Denis #define DC_ABM1_HG_RESULT_11__ABM1_HG_RESULT_11__SHIFT 0x00000000 2845de2bdb3dSTom St Denis #define DC_ABM1_HG_RESULT_12__ABM1_HG_RESULT_12_MASK 0xffffffffL 2846de2bdb3dSTom St Denis #define DC_ABM1_HG_RESULT_12__ABM1_HG_RESULT_12__SHIFT 0x00000000 2847de2bdb3dSTom St Denis #define DC_ABM1_HG_RESULT_13__ABM1_HG_RESULT_13_MASK 0xffffffffL 2848de2bdb3dSTom St Denis #define DC_ABM1_HG_RESULT_13__ABM1_HG_RESULT_13__SHIFT 0x00000000 2849de2bdb3dSTom St Denis #define DC_ABM1_HG_RESULT_14__ABM1_HG_RESULT_14_MASK 0xffffffffL 2850de2bdb3dSTom St Denis #define DC_ABM1_HG_RESULT_14__ABM1_HG_RESULT_14__SHIFT 0x00000000 2851de2bdb3dSTom St Denis #define DC_ABM1_HG_RESULT_15__ABM1_HG_RESULT_15_MASK 0xffffffffL 2852de2bdb3dSTom St Denis #define DC_ABM1_HG_RESULT_15__ABM1_HG_RESULT_15__SHIFT 0x00000000 2853de2bdb3dSTom St Denis #define DC_ABM1_HG_RESULT_16__ABM1_HG_RESULT_16_MASK 0xffffffffL 2854de2bdb3dSTom St Denis #define DC_ABM1_HG_RESULT_16__ABM1_HG_RESULT_16__SHIFT 0x00000000 2855de2bdb3dSTom St Denis #define DC_ABM1_HG_RESULT_17__ABM1_HG_RESULT_17_MASK 0xffffffffL 2856de2bdb3dSTom St Denis #define DC_ABM1_HG_RESULT_17__ABM1_HG_RESULT_17__SHIFT 0x00000000 2857de2bdb3dSTom St Denis #define DC_ABM1_HG_RESULT_18__ABM1_HG_RESULT_18_MASK 0xffffffffL 2858de2bdb3dSTom St Denis #define DC_ABM1_HG_RESULT_18__ABM1_HG_RESULT_18__SHIFT 0x00000000 2859de2bdb3dSTom St Denis #define DC_ABM1_HG_RESULT_19__ABM1_HG_RESULT_19_MASK 0xffffffffL 2860de2bdb3dSTom St Denis #define DC_ABM1_HG_RESULT_19__ABM1_HG_RESULT_19__SHIFT 0x00000000 2861de2bdb3dSTom St Denis #define DC_ABM1_HG_RESULT_1__ABM1_HG_RESULT_1_MASK 0xffffffffL 2862de2bdb3dSTom St Denis #define DC_ABM1_HG_RESULT_1__ABM1_HG_RESULT_1__SHIFT 0x00000000 2863de2bdb3dSTom St Denis #define DC_ABM1_HG_RESULT_20__ABM1_HG_RESULT_20_MASK 0xffffffffL 2864de2bdb3dSTom St Denis #define DC_ABM1_HG_RESULT_20__ABM1_HG_RESULT_20__SHIFT 0x00000000 2865de2bdb3dSTom St Denis #define DC_ABM1_HG_RESULT_21__ABM1_HG_RESULT_21_MASK 0xffffffffL 2866de2bdb3dSTom St Denis #define DC_ABM1_HG_RESULT_21__ABM1_HG_RESULT_21__SHIFT 0x00000000 2867de2bdb3dSTom St Denis #define DC_ABM1_HG_RESULT_22__ABM1_HG_RESULT_22_MASK 0xffffffffL 2868de2bdb3dSTom St Denis #define DC_ABM1_HG_RESULT_22__ABM1_HG_RESULT_22__SHIFT 0x00000000 2869de2bdb3dSTom St Denis #define DC_ABM1_HG_RESULT_23__ABM1_HG_RESULT_23_MASK 0xffffffffL 2870de2bdb3dSTom St Denis #define DC_ABM1_HG_RESULT_23__ABM1_HG_RESULT_23__SHIFT 0x00000000 2871de2bdb3dSTom St Denis #define DC_ABM1_HG_RESULT_24__ABM1_HG_RESULT_24_MASK 0xffffffffL 2872de2bdb3dSTom St Denis #define DC_ABM1_HG_RESULT_24__ABM1_HG_RESULT_24__SHIFT 0x00000000 2873de2bdb3dSTom St Denis #define DC_ABM1_HG_RESULT_2__ABM1_HG_RESULT_2_MASK 0xffffffffL 2874de2bdb3dSTom St Denis #define DC_ABM1_HG_RESULT_2__ABM1_HG_RESULT_2__SHIFT 0x00000000 2875de2bdb3dSTom St Denis #define DC_ABM1_HG_RESULT_3__ABM1_HG_RESULT_3_MASK 0xffffffffL 2876de2bdb3dSTom St Denis #define DC_ABM1_HG_RESULT_3__ABM1_HG_RESULT_3__SHIFT 0x00000000 2877de2bdb3dSTom St Denis #define DC_ABM1_HG_RESULT_4__ABM1_HG_RESULT_4_MASK 0xffffffffL 2878de2bdb3dSTom St Denis #define DC_ABM1_HG_RESULT_4__ABM1_HG_RESULT_4__SHIFT 0x00000000 2879de2bdb3dSTom St Denis #define DC_ABM1_HG_RESULT_5__ABM1_HG_RESULT_5_MASK 0xffffffffL 2880de2bdb3dSTom St Denis #define DC_ABM1_HG_RESULT_5__ABM1_HG_RESULT_5__SHIFT 0x00000000 2881de2bdb3dSTom St Denis #define DC_ABM1_HG_RESULT_6__ABM1_HG_RESULT_6_MASK 0xffffffffL 2882de2bdb3dSTom St Denis #define DC_ABM1_HG_RESULT_6__ABM1_HG_RESULT_6__SHIFT 0x00000000 2883de2bdb3dSTom St Denis #define DC_ABM1_HG_RESULT_7__ABM1_HG_RESULT_7_MASK 0xffffffffL 2884de2bdb3dSTom St Denis #define DC_ABM1_HG_RESULT_7__ABM1_HG_RESULT_7__SHIFT 0x00000000 2885de2bdb3dSTom St Denis #define DC_ABM1_HG_RESULT_8__ABM1_HG_RESULT_8_MASK 0xffffffffL 2886de2bdb3dSTom St Denis #define DC_ABM1_HG_RESULT_8__ABM1_HG_RESULT_8__SHIFT 0x00000000 2887de2bdb3dSTom St Denis #define DC_ABM1_HG_RESULT_9__ABM1_HG_RESULT_9_MASK 0xffffffffL 2888de2bdb3dSTom St Denis #define DC_ABM1_HG_RESULT_9__ABM1_HG_RESULT_9__SHIFT 0x00000000 2889de2bdb3dSTom St Denis #define DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET_MASK 0x00ff0000L 2890de2bdb3dSTom St Denis #define DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET__SHIFT 0x00000010 2891de2bdb3dSTom St Denis #define DC_ABM1_HG_SAMPLE_RATE__ABM1_HGLS_REG_LOCK_MASK 0x80000000L 2892de2bdb3dSTom St Denis #define DC_ABM1_HG_SAMPLE_RATE__ABM1_HGLS_REG_LOCK__SHIFT 0x0000001f 2893de2bdb3dSTom St Denis #define DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_RESET_SAMPLE_RATE_FRAME_COUNTER_MASK 0x00000002L 2894de2bdb3dSTom St Denis #define DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_RESET_SAMPLE_RATE_FRAME_COUNTER__SHIFT 0x00000001 2895de2bdb3dSTom St Denis #define DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_COUNT_EN_MASK 0x00000001L 2896de2bdb3dSTom St Denis #define DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_COUNT_EN__SHIFT 0x00000000 2897de2bdb3dSTom St Denis #define DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_FRAME_COUNT_MASK 0x0000ff00L 2898de2bdb3dSTom St Denis #define DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_FRAME_COUNT__SHIFT 0x00000008 2899de2bdb3dSTom St Denis #define DC_ABM1_IPCSC_COEFF_SEL__ABM1_HGLS_REG_LOCK_MASK 0x80000000L 2900de2bdb3dSTom St Denis #define DC_ABM1_IPCSC_COEFF_SEL__ABM1_HGLS_REG_LOCK__SHIFT 0x0000001f 2901de2bdb3dSTom St Denis #define DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_B_MASK 0x0000000fL 2902de2bdb3dSTom St Denis #define DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_B__SHIFT 0x00000000 2903de2bdb3dSTom St Denis #define DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_G_MASK 0x00000f00L 2904de2bdb3dSTom St Denis #define DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_G__SHIFT 0x00000008 2905de2bdb3dSTom St Denis #define DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_R_MASK 0x000f0000L 2906de2bdb3dSTom St Denis #define DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_R__SHIFT 0x00000010 2907de2bdb3dSTom St Denis #define DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MAX_LUMA_MASK 0x03ff0000L 2908de2bdb3dSTom St Denis #define DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MAX_LUMA__SHIFT 0x00000010 2909de2bdb3dSTom St Denis #define DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MIN_LUMA_MASK 0x000003ffL 2910de2bdb3dSTom St Denis #define DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MIN_LUMA__SHIFT 0x00000000 2911de2bdb3dSTom St Denis #define DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT__ABM1_LS_MAX_PIXEL_VALUE_COUNT_MASK 0x00ffffffL 2912de2bdb3dSTom St Denis #define DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT__ABM1_LS_MAX_PIXEL_VALUE_COUNT__SHIFT 0x00000000 2913de2bdb3dSTom St Denis #define DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MAX_LUMA_MASK 0x03ff0000L 2914de2bdb3dSTom St Denis #define DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MAX_LUMA__SHIFT 0x00000010 2915de2bdb3dSTom St Denis #define DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MIN_LUMA_MASK 0x000003ffL 2916de2bdb3dSTom St Denis #define DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MIN_LUMA__SHIFT 0x00000000 2917de2bdb3dSTom St Denis #define DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_HGLS_REG_LOCK_MASK 0x80000000L 2918de2bdb3dSTom St Denis #define DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_HGLS_REG_LOCK__SHIFT 0x0000001f 2919de2bdb3dSTom St Denis #define DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MAX_PIXEL_VALUE_THRES_MASK 0x03ff0000L 2920de2bdb3dSTom St Denis #define DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MAX_PIXEL_VALUE_THRES__SHIFT 0x00000010 2921de2bdb3dSTom St Denis #define DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MIN_PIXEL_VALUE_THRES_MASK 0x000003ffL 2922de2bdb3dSTom St Denis #define DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MIN_PIXEL_VALUE_THRES__SHIFT 0x00000000 2923de2bdb3dSTom St Denis #define DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT__ABM1_LS_MIN_PIXEL_VALUE_COUNT_MASK 0x00ffffffL 2924de2bdb3dSTom St Denis #define DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT__ABM1_LS_MIN_PIXEL_VALUE_COUNT__SHIFT 0x00000000 2925de2bdb3dSTom St Denis #define DC_ABM1_LS_OVR_SCAN_BIN__ABM1_LS_OVR_SCAN_BIN_MASK 0x00ffffffL 2926de2bdb3dSTom St Denis #define DC_ABM1_LS_OVR_SCAN_BIN__ABM1_LS_OVR_SCAN_BIN__SHIFT 0x00000000 2927de2bdb3dSTom St Denis #define DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_PIXEL_COUNT_MASK 0x00ffffffL 2928de2bdb3dSTom St Denis #define DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_PIXEL_COUNT__SHIFT 0x00000000 2929de2bdb3dSTom St Denis #define DC_ABM1_LS_SAMPLE_RATE__ABM1_HGLS_REG_LOCK_MASK 0x80000000L 2930de2bdb3dSTom St Denis #define DC_ABM1_LS_SAMPLE_RATE__ABM1_HGLS_REG_LOCK__SHIFT 0x0000001f 2931de2bdb3dSTom St Denis #define DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET_MASK 0x00ff0000L 2932de2bdb3dSTom St Denis #define DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET__SHIFT 0x00000010 2933de2bdb3dSTom St Denis #define DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_RESET_SAMPLE_RATE_FRAME_COUNTER_MASK 0x00000002L 2934de2bdb3dSTom St Denis #define DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_RESET_SAMPLE_RATE_FRAME_COUNTER__SHIFT 0x00000001 2935de2bdb3dSTom St Denis #define DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_COUNT_EN_MASK 0x00000001L 2936de2bdb3dSTom St Denis #define DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_COUNT_EN__SHIFT 0x00000000 2937de2bdb3dSTom St Denis #define DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_FRAME_COUNT_MASK 0x0000ff00L 2938de2bdb3dSTom St Denis #define DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_FRAME_COUNT__SHIFT 0x00000008 2939de2bdb3dSTom St Denis #define DC_ABM1_LS_SUM_OF_LUMA__ABM1_LS_SUM_OF_LUMA_MASK 0xffffffffL 2940de2bdb3dSTom St Denis #define DC_ABM1_LS_SUM_OF_LUMA__ABM1_LS_SUM_OF_LUMA__SHIFT 0x00000000 2941de2bdb3dSTom St Denis #define DC_ABM1_OVERSCAN_PIXEL_VALUE__ABM1_OVERSCAN_B_PIXEL_VALUE_MASK 0x3ff00000L 2942de2bdb3dSTom St Denis #define DC_ABM1_OVERSCAN_PIXEL_VALUE__ABM1_OVERSCAN_B_PIXEL_VALUE__SHIFT 0x00000014 2943de2bdb3dSTom St Denis #define DC_ABM1_OVERSCAN_PIXEL_VALUE__ABM1_OVERSCAN_G_PIXEL_VALUE_MASK 0x000ffc00L 2944de2bdb3dSTom St Denis #define DC_ABM1_OVERSCAN_PIXEL_VALUE__ABM1_OVERSCAN_G_PIXEL_VALUE__SHIFT 0x0000000a 2945de2bdb3dSTom St Denis #define DC_ABM1_OVERSCAN_PIXEL_VALUE__ABM1_OVERSCAN_R_PIXEL_VALUE_MASK 0x000003ffL 2946de2bdb3dSTom St Denis #define DC_ABM1_OVERSCAN_PIXEL_VALUE__ABM1_OVERSCAN_R_PIXEL_VALUE__SHIFT 0x00000000 2947de2bdb3dSTom St Denis #define DCCG_AUDIO_DTO0_MODULE__DCCG_AUDIO_DTO0_MODULE_MASK 0xffffffffL 2948de2bdb3dSTom St Denis #define DCCG_AUDIO_DTO0_MODULE__DCCG_AUDIO_DTO0_MODULE__SHIFT 0x00000000 2949de2bdb3dSTom St Denis #define DCCG_AUDIO_DTO0_PHASE__DCCG_AUDIO_DTO0_PHASE_MASK 0xffffffffL 2950de2bdb3dSTom St Denis #define DCCG_AUDIO_DTO0_PHASE__DCCG_AUDIO_DTO0_PHASE__SHIFT 0x00000000 2951de2bdb3dSTom St Denis #define DCCG_AUDIO_DTO1_MODULE__DCCG_AUDIO_DTO1_MODULE_MASK 0xffffffffL 2952de2bdb3dSTom St Denis #define DCCG_AUDIO_DTO1_MODULE__DCCG_AUDIO_DTO1_MODULE__SHIFT 0x00000000 2953de2bdb3dSTom St Denis #define DCCG_AUDIO_DTO1_PHASE__DCCG_AUDIO_DTO1_PHASE_MASK 0xffffffffL 2954de2bdb3dSTom St Denis #define DCCG_AUDIO_DTO1_PHASE__DCCG_AUDIO_DTO1_PHASE__SHIFT 0x00000000 2955de2bdb3dSTom St Denis #define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO0_SOURCE_SEL_MASK 0x00000007L 2956de2bdb3dSTom St Denis #define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO0_SOURCE_SEL__SHIFT 0x00000000 2957de2bdb3dSTom St Denis #define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO_SEL_MASK 0x00000010L 2958de2bdb3dSTom St Denis #define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO_SEL__SHIFT 0x00000004 2959de2bdb3dSTom St Denis #define DCCG_CAC_STATUS__CAC_STATUS_RDDATA_MASK 0xffffffffL 2960de2bdb3dSTom St Denis #define DCCG_CAC_STATUS__CAC_STATUS_RDDATA__SHIFT 0x00000000 2961de2bdb3dSTom St Denis #define DCCG_GATE_DISABLE_CNTL__DACACLK_GATE_DISABLE_MASK 0x00000010L 2962de2bdb3dSTom St Denis #define DCCG_GATE_DISABLE_CNTL__DACACLK_GATE_DISABLE__SHIFT 0x00000004 2963de2bdb3dSTom St Denis #define DCCG_GATE_DISABLE_CNTL__DACBCLK_GATE_DISABLE_MASK 0x00000020L 2964de2bdb3dSTom St Denis #define DCCG_GATE_DISABLE_CNTL__DACBCLK_GATE_DISABLE__SHIFT 0x00000005 2965de2bdb3dSTom St Denis #define DCCG_GATE_DISABLE_CNTL__DISPCLK_DCCG_GATE_DISABLE_MASK 0x00000001L 2966de2bdb3dSTom St Denis #define DCCG_GATE_DISABLE_CNTL__DISPCLK_DCCG_GATE_DISABLE__SHIFT 0x00000000 2967de2bdb3dSTom St Denis #define DCCG_GATE_DISABLE_CNTL__DISPCLK_RAMP_DIV_ID_MASK 0x07000000L 2968de2bdb3dSTom St Denis #define DCCG_GATE_DISABLE_CNTL__DISPCLK_RAMP_DIV_ID__SHIFT 0x00000018 2969de2bdb3dSTom St Denis #define DCCG_GATE_DISABLE_CNTL__DISPCLK_R_DCCG_GATE_DISABLE_MASK 0x00000002L 2970de2bdb3dSTom St Denis #define DCCG_GATE_DISABLE_CNTL__DISPCLK_R_DCCG_GATE_DISABLE__SHIFT 0x00000001 2971de2bdb3dSTom St Denis #define DCCG_GATE_DISABLE_CNTL__DISPCLK_R_DCCG_RAMP_DISABLE_MASK 0x00100000L 2972de2bdb3dSTom St Denis #define DCCG_GATE_DISABLE_CNTL__DISPCLK_R_DCCG_RAMP_DISABLE__SHIFT 0x00000014 2973de2bdb3dSTom St Denis #define DCCG_GATE_DISABLE_CNTL__DVOACLK_GATE_DISABLE_MASK 0x00000040L 2974de2bdb3dSTom St Denis #define DCCG_GATE_DISABLE_CNTL__DVOACLK_GATE_DISABLE__SHIFT 0x00000006 2975de2bdb3dSTom St Denis #define DCCG_GATE_DISABLE_CNTL__PCLK_TV_GATE_DISABLE_MASK 0x00010000L 2976de2bdb3dSTom St Denis #define DCCG_GATE_DISABLE_CNTL__PCLK_TV_GATE_DISABLE__SHIFT 0x00000010 2977de2bdb3dSTom St Denis #define DCCG_GATE_DISABLE_CNTL__SCLK_GATE_DISABLE_MASK 0x00000004L 2978de2bdb3dSTom St Denis #define DCCG_GATE_DISABLE_CNTL__SCLK_GATE_DISABLE__SHIFT 0x00000002 2979de2bdb3dSTom St Denis #define DCCG_GATE_DISABLE_CNTL__SCLK_RAMP_DIV_ID_MASK 0x70000000L 2980de2bdb3dSTom St Denis #define DCCG_GATE_DISABLE_CNTL__SCLK_RAMP_DIV_ID__SHIFT 0x0000001c 2981de2bdb3dSTom St Denis #define DCCG_GATE_DISABLE_CNTL__SYMCLKA_GATE_DISABLE_MASK 0x00000100L 2982de2bdb3dSTom St Denis #define DCCG_GATE_DISABLE_CNTL__SYMCLKA_GATE_DISABLE__SHIFT 0x00000008 2983de2bdb3dSTom St Denis #define DCCG_GATE_DISABLE_CNTL__SYMCLKB_GATE_DISABLE_MASK 0x00000200L 2984de2bdb3dSTom St Denis #define DCCG_GATE_DISABLE_CNTL__SYMCLKB_GATE_DISABLE__SHIFT 0x00000009 2985de2bdb3dSTom St Denis #define DCCG_GATE_DISABLE_CNTL__SYMCLKC_GATE_DISABLE_MASK 0x00000400L 2986de2bdb3dSTom St Denis #define DCCG_GATE_DISABLE_CNTL__SYMCLKC_GATE_DISABLE__SHIFT 0x0000000a 2987de2bdb3dSTom St Denis #define DCCG_GATE_DISABLE_CNTL__SYMCLKD_GATE_DISABLE_MASK 0x00000800L 2988de2bdb3dSTom St Denis #define DCCG_GATE_DISABLE_CNTL__SYMCLKD_GATE_DISABLE__SHIFT 0x0000000b 2989de2bdb3dSTom St Denis #define DCCG_GATE_DISABLE_CNTL__SYMCLKE_GATE_DISABLE_MASK 0x00001000L 2990de2bdb3dSTom St Denis #define DCCG_GATE_DISABLE_CNTL__SYMCLKE_GATE_DISABLE__SHIFT 0x0000000c 2991de2bdb3dSTom St Denis #define DCCG_GATE_DISABLE_CNTL__SYMCLKF_GATE_DISABLE_MASK 0x00002000L 2992de2bdb3dSTom St Denis #define DCCG_GATE_DISABLE_CNTL__SYMCLKF_GATE_DISABLE__SHIFT 0x0000000d 2993de2bdb3dSTom St Denis #define DCCG_GTC_CNTL__DCCG_GTC_ENABLE_MASK 0x00000001L 2994de2bdb3dSTom St Denis #define DCCG_GTC_CNTL__DCCG_GTC_ENABLE__SHIFT 0x00000000 2995de2bdb3dSTom St Denis #define DCCG_GTC_CURRENT__DCCG_GTC_CURRENT_MASK 0xffffffffL 2996de2bdb3dSTom St Denis #define DCCG_GTC_CURRENT__DCCG_GTC_CURRENT__SHIFT 0x00000000 2997de2bdb3dSTom St Denis #define DCCG_GTC_DTO_MODULO__DCCG_GTC_DTO_MODULO_MASK 0xffffffffL 2998de2bdb3dSTom St Denis #define DCCG_GTC_DTO_MODULO__DCCG_GTC_DTO_MODULO__SHIFT 0x00000000 2999de2bdb3dSTom St Denis #define DCCG_PERFMON_CNTL__DCCG_PERF_CRTC_SEL_MASK 0x00000700L 3000de2bdb3dSTom St Denis #define DCCG_PERFMON_CNTL__DCCG_PERF_CRTC_SEL__SHIFT 0x00000008 3001de2bdb3dSTom St Denis #define DCCG_PERFMON_CNTL__DCCG_PERF_DISPCLK_ENABLE_MASK 0x00000001L 3002de2bdb3dSTom St Denis #define DCCG_PERFMON_CNTL__DCCG_PERF_DISPCLK_ENABLE__SHIFT 0x00000000 3003de2bdb3dSTom St Denis #define DCCG_PERFMON_CNTL__DCCG_PERF_DPREFCLK_ENABLE_MASK 0x00000002L 3004de2bdb3dSTom St Denis #define DCCG_PERFMON_CNTL__DCCG_PERF_DPREFCLK_ENABLE__SHIFT 0x00000001 3005de2bdb3dSTom St Denis #define DCCG_PERFMON_CNTL__DCCG_PERF_MODE_HSYNC_MASK 0x00000080L 3006de2bdb3dSTom St Denis #define DCCG_PERFMON_CNTL__DCCG_PERF_MODE_HSYNC__SHIFT 0x00000007 3007de2bdb3dSTom St Denis #define DCCG_PERFMON_CNTL__DCCG_PERF_MODE_VSYNC_MASK 0x00000040L 3008de2bdb3dSTom St Denis #define DCCG_PERFMON_CNTL__DCCG_PERF_MODE_VSYNC__SHIFT 0x00000006 3009de2bdb3dSTom St Denis #define DCCG_PERFMON_CNTL__DCCG_PERF_PIXCLK0_ENABLE_MASK 0x00000010L 3010de2bdb3dSTom St Denis #define DCCG_PERFMON_CNTL__DCCG_PERF_PIXCLK0_ENABLE__SHIFT 0x00000004 3011de2bdb3dSTom St Denis #define DCCG_PERFMON_CNTL__DCCG_PERF_PIXCLK1_ENABLE_MASK 0x00000004L 3012de2bdb3dSTom St Denis #define DCCG_PERFMON_CNTL__DCCG_PERF_PIXCLK1_ENABLE__SHIFT 0x00000002 3013de2bdb3dSTom St Denis #define DCCG_PERFMON_CNTL__DCCG_PERF_PIXCLK2_ENABLE_MASK 0x00000008L 3014de2bdb3dSTom St Denis #define DCCG_PERFMON_CNTL__DCCG_PERF_PIXCLK2_ENABLE__SHIFT 0x00000003 3015de2bdb3dSTom St Denis #define DCCG_PERFMON_CNTL__DCCG_PERF_RUN_MASK 0x00000020L 3016de2bdb3dSTom St Denis #define DCCG_PERFMON_CNTL__DCCG_PERF_RUN__SHIFT 0x00000005 3017de2bdb3dSTom St Denis #define DCCG_SOFT_RESET__REFCLK_SOFT_RESET_MASK 0x00000001L 3018de2bdb3dSTom St Denis #define DCCG_SOFT_RESET__REFCLK_SOFT_RESET__SHIFT 0x00000000 3019de2bdb3dSTom St Denis #define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICA_INV_MASK 0x00010000L 3020de2bdb3dSTom St Denis #define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICA_INV__SHIFT 0x00000010 3021de2bdb3dSTom St Denis #define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICA_SEL_MASK 0x000000ffL 3022de2bdb3dSTom St Denis #define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICA_SEL__SHIFT 0x00000000 3023de2bdb3dSTom St Denis #define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICB_INV_MASK 0x01000000L 3024de2bdb3dSTom St Denis #define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICB_INV__SHIFT 0x00000018 3025de2bdb3dSTom St Denis #define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICB_SEL_MASK 0x0000ff00L 3026de2bdb3dSTom St Denis #define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICB_SEL__SHIFT 0x00000008 3027de2bdb3dSTom St Denis #define DCCG_TEST_DEBUG_DATA__DCCG_TEST_DEBUG_DATA_MASK 0xffffffffL 3028de2bdb3dSTom St Denis #define DCCG_TEST_DEBUG_DATA__DCCG_TEST_DEBUG_DATA__SHIFT 0x00000000 3029de2bdb3dSTom St Denis #define DCCG_TEST_DEBUG_INDEX__DCCG_DBG_SEL_MASK 0x00001000L 3030de2bdb3dSTom St Denis #define DCCG_TEST_DEBUG_INDEX__DCCG_DBG_SEL__SHIFT 0x0000000c 3031de2bdb3dSTom St Denis #define DCCG_TEST_DEBUG_INDEX__DCCG_TEST_DEBUG_INDEX_MASK 0x000000ffL 3032de2bdb3dSTom St Denis #define DCCG_TEST_DEBUG_INDEX__DCCG_TEST_DEBUG_INDEX__SHIFT 0x00000000 3033de2bdb3dSTom St Denis #define DCCG_TEST_DEBUG_INDEX__DCCG_TEST_DEBUG_WRITE_EN_MASK 0x00000100L 3034de2bdb3dSTom St Denis #define DCCG_TEST_DEBUG_INDEX__DCCG_TEST_DEBUG_WRITE_EN__SHIFT 0x00000008 3035de2bdb3dSTom St Denis #define DCCG_VPCLK_CNTL__AZ_LIGHT_SLEEP_DIS_MASK 0x00000004L 3036de2bdb3dSTom St Denis #define DCCG_VPCLK_CNTL__AZ_LIGHT_SLEEP_DIS__SHIFT 0x00000002 3037de2bdb3dSTom St Denis #define DCCG_VPCLK_CNTL__AZ_MEM_SHUTDOWN_DIS_MASK 0x04000000L 3038de2bdb3dSTom St Denis #define DCCG_VPCLK_CNTL__AZ_MEM_SHUTDOWN_DIS__SHIFT 0x0000001a 3039de2bdb3dSTom St Denis #define DCCG_VPCLK_CNTL__DCCG_VPCLK_POL_MASK 0x00000001L 3040de2bdb3dSTom St Denis #define DCCG_VPCLK_CNTL__DCCG_VPCLK_POL__SHIFT 0x00000000 3041de2bdb3dSTom St Denis #define DCCG_VPCLK_CNTL__DMCU_LIGHT_SLEEP_DIS_MASK 0x00000008L 3042de2bdb3dSTom St Denis #define DCCG_VPCLK_CNTL__DMCU_LIGHT_SLEEP_DIS__SHIFT 0x00000003 3043de2bdb3dSTom St Denis #define DCCG_VPCLK_CNTL__DMCU_MEM_SHUTDOWN_DIS_MASK 0x00010000L 3044de2bdb3dSTom St Denis #define DCCG_VPCLK_CNTL__DMCU_MEM_SHUTDOWN_DIS__SHIFT 0x00000010 3045de2bdb3dSTom St Denis #define DCCG_VPCLK_CNTL__DMIF0_LIGHT_SLEEP_DIS_MASK 0x00000100L 3046de2bdb3dSTom St Denis #define DCCG_VPCLK_CNTL__DMIF0_LIGHT_SLEEP_DIS__SHIFT 0x00000008 3047de2bdb3dSTom St Denis #define DCCG_VPCLK_CNTL__DMIF0_MEM_SHUTDOWN_DIS_MASK 0x00100000L 3048de2bdb3dSTom St Denis #define DCCG_VPCLK_CNTL__DMIF0_MEM_SHUTDOWN_DIS__SHIFT 0x00000014 3049de2bdb3dSTom St Denis #define DCCG_VPCLK_CNTL__DMIF1_LIGHT_SLEEP_DIS_MASK 0x00000200L 3050de2bdb3dSTom St Denis #define DCCG_VPCLK_CNTL__DMIF1_LIGHT_SLEEP_DIS__SHIFT 0x00000009 3051de2bdb3dSTom St Denis #define DCCG_VPCLK_CNTL__DMIF1_MEM_SHUTDOWN_DIS_MASK 0x00200000L 3052de2bdb3dSTom St Denis #define DCCG_VPCLK_CNTL__DMIF1_MEM_SHUTDOWN_DIS__SHIFT 0x00000015 3053de2bdb3dSTom St Denis #define DCCG_VPCLK_CNTL__DMIF2_LIGHT_SLEEP_DIS_MASK 0x00000400L 3054de2bdb3dSTom St Denis #define DCCG_VPCLK_CNTL__DMIF2_LIGHT_SLEEP_DIS__SHIFT 0x0000000a 3055de2bdb3dSTom St Denis #define DCCG_VPCLK_CNTL__DMIF2_MEM_SHUTDOWN_DIS_MASK 0x00400000L 3056de2bdb3dSTom St Denis #define DCCG_VPCLK_CNTL__DMIF2_MEM_SHUTDOWN_DIS__SHIFT 0x00000016 3057de2bdb3dSTom St Denis #define DCCG_VPCLK_CNTL__DMIF3_LIGHT_SLEEP_DIS_MASK 0x00000800L 3058de2bdb3dSTom St Denis #define DCCG_VPCLK_CNTL__DMIF3_LIGHT_SLEEP_DIS__SHIFT 0x0000000b 3059de2bdb3dSTom St Denis #define DCCG_VPCLK_CNTL__DMIF3_MEM_SHUTDOWN_DIS_MASK 0x00800000L 3060de2bdb3dSTom St Denis #define DCCG_VPCLK_CNTL__DMIF3_MEM_SHUTDOWN_DIS__SHIFT 0x00000017 3061de2bdb3dSTom St Denis #define DCCG_VPCLK_CNTL__DMIF4_LIGHT_SLEEP_DIS_MASK 0x00001000L 3062de2bdb3dSTom St Denis #define DCCG_VPCLK_CNTL__DMIF4_LIGHT_SLEEP_DIS__SHIFT 0x0000000c 3063de2bdb3dSTom St Denis #define DCCG_VPCLK_CNTL__DMIF4_MEM_SHUTDOWN_DIS_MASK 0x01000000L 3064de2bdb3dSTom St Denis #define DCCG_VPCLK_CNTL__DMIF4_MEM_SHUTDOWN_DIS__SHIFT 0x00000018 3065de2bdb3dSTom St Denis #define DCCG_VPCLK_CNTL__DMIF5_LIGHT_SLEEP_DIS_MASK 0x00002000L 3066de2bdb3dSTom St Denis #define DCCG_VPCLK_CNTL__DMIF5_LIGHT_SLEEP_DIS__SHIFT 0x0000000d 3067de2bdb3dSTom St Denis #define DCCG_VPCLK_CNTL__DMIF5_MEM_SHUTDOWN_DIS_MASK 0x02000000L 3068de2bdb3dSTom St Denis #define DCCG_VPCLK_CNTL__DMIF5_MEM_SHUTDOWN_DIS__SHIFT 0x00000019 3069de2bdb3dSTom St Denis #define DCCG_VPCLK_CNTL__DMIF_XLR_LIGHT_SLEEP_MODE_FORCE_MASK 0x00000020L 3070de2bdb3dSTom St Denis #define DCCG_VPCLK_CNTL__DMIF_XLR_LIGHT_SLEEP_MODE_FORCE__SHIFT 0x00000005 3071de2bdb3dSTom St Denis #define DCCG_VPCLK_CNTL__DMIF_XLR_MEM_SHUTDOWN_MODE_FORCE_MASK 0x00040000L 3072de2bdb3dSTom St Denis #define DCCG_VPCLK_CNTL__DMIF_XLR_MEM_SHUTDOWN_MODE_FORCE__SHIFT 0x00000012 3073de2bdb3dSTom St Denis #define DCCG_VPCLK_CNTL__FBC_LIGHT_SLEEP_DIS_MASK 0x00004000L 3074de2bdb3dSTom St Denis #define DCCG_VPCLK_CNTL__FBC_LIGHT_SLEEP_DIS__SHIFT 0x0000000e 3075de2bdb3dSTom St Denis #define DCCG_VPCLK_CNTL__FBC_MEM_SHUTDOWN_DIS_MASK 0x00080000L 3076de2bdb3dSTom St Denis #define DCCG_VPCLK_CNTL__FBC_MEM_SHUTDOWN_DIS__SHIFT 0x00000013 3077de2bdb3dSTom St Denis #define DCCG_VPCLK_CNTL__MCIF_LIGHT_SLEEP_MODE_FORCE_MASK 0x00000010L 3078de2bdb3dSTom St Denis #define DCCG_VPCLK_CNTL__MCIF_LIGHT_SLEEP_MODE_FORCE__SHIFT 0x00000004 3079de2bdb3dSTom St Denis #define DCCG_VPCLK_CNTL__MCIF_MEM_SHUTDOWN_MODE_FORCE_MASK 0x00020000L 3080de2bdb3dSTom St Denis #define DCCG_VPCLK_CNTL__MCIF_MEM_SHUTDOWN_MODE_FORCE__SHIFT 0x00000011 3081de2bdb3dSTom St Denis #define DCCG_VPCLK_CNTL__VGA_LIGHT_SLEEP_MODE_FORCE_MASK 0x00000002L 3082de2bdb3dSTom St Denis #define DCCG_VPCLK_CNTL__VGA_LIGHT_SLEEP_MODE_FORCE__SHIFT 0x00000001 3083de2bdb3dSTom St Denis #define DCCG_VPCLK_CNTL__VIP_LIGHT_SLEEP_DIS_MASK 0x00008000L 3084de2bdb3dSTom St Denis #define DCCG_VPCLK_CNTL__VIP_LIGHT_SLEEP_DIS__SHIFT 0x0000000f 3085de2bdb3dSTom St Denis #define DCDEBUG_BUS_CLK1_SEL__DCDEBUG_BUS_CLK1_SEL_MASK 0xffffffffL 3086de2bdb3dSTom St Denis #define DCDEBUG_BUS_CLK1_SEL__DCDEBUG_BUS_CLK1_SEL__SHIFT 0x00000000 3087de2bdb3dSTom St Denis #define DCDEBUG_BUS_CLK2_SEL__DCDEBUG_BUS_CLK2_SEL_MASK 0xffffffffL 3088de2bdb3dSTom St Denis #define DCDEBUG_BUS_CLK2_SEL__DCDEBUG_BUS_CLK2_SEL__SHIFT 0x00000000 3089de2bdb3dSTom St Denis #define DCDEBUG_BUS_CLK3_SEL__DCDEBUG_BUS_CLK3_SEL_MASK 0xffffffffL 3090de2bdb3dSTom St Denis #define DCDEBUG_BUS_CLK3_SEL__DCDEBUG_BUS_CLK3_SEL__SHIFT 0x00000000 3091de2bdb3dSTom St Denis #define DCDEBUG_BUS_CLK4_SEL__DCDEBUG_BUS_CLK4_SEL_MASK 0xffffffffL 3092de2bdb3dSTom St Denis #define DCDEBUG_BUS_CLK4_SEL__DCDEBUG_BUS_CLK4_SEL__SHIFT 0x00000000 3093de2bdb3dSTom St Denis #define DCDEBUG_OUT_CNTL__DCDEBUG_BLOCK_SEL_MASK 0x0000001fL 3094de2bdb3dSTom St Denis #define DCDEBUG_OUT_CNTL__DCDEBUG_BLOCK_SEL__SHIFT 0x00000000 3095de2bdb3dSTom St Denis #define DCDEBUG_OUT_CNTL__DCDEBUG_OUT_EN_MASK 0x00000020L 3096de2bdb3dSTom St Denis #define DCDEBUG_OUT_CNTL__DCDEBUG_OUT_EN__SHIFT 0x00000005 3097de2bdb3dSTom St Denis #define DCDEBUG_OUT_CNTL__DCDEBUG_OUT_PIN_SEL_MASK 0x00000040L 3098de2bdb3dSTom St Denis #define DCDEBUG_OUT_CNTL__DCDEBUG_OUT_PIN_SEL__SHIFT 0x00000006 3099de2bdb3dSTom St Denis #define DCDEBUG_OUT_CNTL__DCDEBUG_OUT_SEL_MASK 0x00300000L 3100de2bdb3dSTom St Denis #define DCDEBUG_OUT_CNTL__DCDEBUG_OUT_SEL__SHIFT 0x00000014 3101de2bdb3dSTom St Denis #define DCDEBUG_OUT_CNTL__DCDEBUG_OUT_TEST_DATA_EN_MASK 0x00000080L 3102de2bdb3dSTom St Denis #define DCDEBUG_OUT_CNTL__DCDEBUG_OUT_TEST_DATA_EN__SHIFT 0x00000007 3103de2bdb3dSTom St Denis #define DCDEBUG_OUT_CNTL__DCDEBUG_OUT_TEST_DATA_MASK 0x000fff00L 3104de2bdb3dSTom St Denis #define DCDEBUG_OUT_CNTL__DCDEBUG_OUT_TEST_DATA__SHIFT 0x00000008 3105de2bdb3dSTom St Denis #define DCDEBUG_OUT_DATA__DCDEBUG_OUT_DATA_MASK 0xffffffffL 3106de2bdb3dSTom St Denis #define DCDEBUG_OUT_DATA__DCDEBUG_OUT_DATA__SHIFT 0x00000000 3107de2bdb3dSTom St Denis #define DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE1_EN_MASK 0x00001000L 3108de2bdb3dSTom St Denis #define DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE1_EN__SHIFT 0x0000000c 3109de2bdb3dSTom St Denis #define DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE1_PIN_SEL_MASK 0x0000000fL 3110de2bdb3dSTom St Denis #define DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE1_PIN_SEL__SHIFT 0x00000000 3111de2bdb3dSTom St Denis #define DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE1_REGBIT_SEL_MASK 0x000001f0L 3112de2bdb3dSTom St Denis #define DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE1_REGBIT_SEL__SHIFT 0x00000004 3113de2bdb3dSTom St Denis #define DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE2_EN_MASK 0x10000000L 3114de2bdb3dSTom St Denis #define DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE2_EN__SHIFT 0x0000001c 3115de2bdb3dSTom St Denis #define DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE2_PIN_SEL_MASK 0x000f0000L 3116de2bdb3dSTom St Denis #define DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE2_PIN_SEL__SHIFT 0x00000010 3117de2bdb3dSTom St Denis #define DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE2_REGBIT_SEL_MASK 0x01f00000L 3118de2bdb3dSTom St Denis #define DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE2_REGBIT_SEL__SHIFT 0x00000014 3119de2bdb3dSTom St Denis #define DC_DMCU_SCRATCH__DMCU_SCRATCH_MASK 0xffffffffL 3120de2bdb3dSTom St Denis #define DC_DMCU_SCRATCH__DMCU_SCRATCH__SHIFT 0x00000000 3121de2bdb3dSTom St Denis #define DC_DVODATA_CONFIG__DVO_ALTER_MAPPING_EN_MASK 0x00200000L 3122de2bdb3dSTom St Denis #define DC_DVODATA_CONFIG__DVO_ALTER_MAPPING_EN__SHIFT 0x00000015 3123de2bdb3dSTom St Denis #define DC_DVODATA_CONFIG__VIP_ALTER_MAPPING_EN_MASK 0x00100000L 3124de2bdb3dSTom St Denis #define DC_DVODATA_CONFIG__VIP_ALTER_MAPPING_EN__SHIFT 0x00000014 3125de2bdb3dSTom St Denis #define DC_DVODATA_CONFIG__VIP_MUX_EN_MASK 0x00080000L 3126de2bdb3dSTom St Denis #define DC_DVODATA_CONFIG__VIP_MUX_EN__SHIFT 0x00000013 3127de2bdb3dSTom St Denis #define DCFE0_SOFT_RESET__CRTC0_SOFT_RESET_MASK 0x00000010L 3128de2bdb3dSTom St Denis #define DCFE0_SOFT_RESET__CRTC0_SOFT_RESET__SHIFT 0x00000004 3129de2bdb3dSTom St Denis #define DCFE0_SOFT_RESET__DCP0_PIXPIPE_SOFT_RESET_MASK 0x00000001L 3130de2bdb3dSTom St Denis #define DCFE0_SOFT_RESET__DCP0_PIXPIPE_SOFT_RESET__SHIFT 0x00000000 3131de2bdb3dSTom St Denis #define DCFE0_SOFT_RESET__DCP0_REQ_SOFT_RESET_MASK 0x00000002L 3132de2bdb3dSTom St Denis #define DCFE0_SOFT_RESET__DCP0_REQ_SOFT_RESET__SHIFT 0x00000001 3133de2bdb3dSTom St Denis #define DCFE0_SOFT_RESET__SCL0_ALU_SOFT_RESET_MASK 0x00000004L 3134de2bdb3dSTom St Denis #define DCFE0_SOFT_RESET__SCL0_ALU_SOFT_RESET__SHIFT 0x00000002 3135de2bdb3dSTom St Denis #define DCFE0_SOFT_RESET__SCL0_SOFT_RESET_MASK 0x00000008L 3136de2bdb3dSTom St Denis #define DCFE0_SOFT_RESET__SCL0_SOFT_RESET__SHIFT 0x00000003 3137de2bdb3dSTom St Denis #define DCFE1_SOFT_RESET__CRTC1_SOFT_RESET_MASK 0x00000010L 3138de2bdb3dSTom St Denis #define DCFE1_SOFT_RESET__CRTC1_SOFT_RESET__SHIFT 0x00000004 3139de2bdb3dSTom St Denis #define DCFE1_SOFT_RESET__DCP1_PIXPIPE_SOFT_RESET_MASK 0x00000001L 3140de2bdb3dSTom St Denis #define DCFE1_SOFT_RESET__DCP1_PIXPIPE_SOFT_RESET__SHIFT 0x00000000 3141de2bdb3dSTom St Denis #define DCFE1_SOFT_RESET__DCP1_REQ_SOFT_RESET_MASK 0x00000002L 3142de2bdb3dSTom St Denis #define DCFE1_SOFT_RESET__DCP1_REQ_SOFT_RESET__SHIFT 0x00000001 3143de2bdb3dSTom St Denis #define DCFE1_SOFT_RESET__SCL1_ALU_SOFT_RESET_MASK 0x00000004L 3144de2bdb3dSTom St Denis #define DCFE1_SOFT_RESET__SCL1_ALU_SOFT_RESET__SHIFT 0x00000002 3145de2bdb3dSTom St Denis #define DCFE1_SOFT_RESET__SCL1_SOFT_RESET_MASK 0x00000008L 3146de2bdb3dSTom St Denis #define DCFE1_SOFT_RESET__SCL1_SOFT_RESET__SHIFT 0x00000003 3147de2bdb3dSTom St Denis #define DCFE2_SOFT_RESET__CRTC2_SOFT_RESET_MASK 0x00000010L 3148de2bdb3dSTom St Denis #define DCFE2_SOFT_RESET__CRTC2_SOFT_RESET__SHIFT 0x00000004 3149de2bdb3dSTom St Denis #define DCFE2_SOFT_RESET__DCP2_PIXPIPE_SOFT_RESET_MASK 0x00000001L 3150de2bdb3dSTom St Denis #define DCFE2_SOFT_RESET__DCP2_PIXPIPE_SOFT_RESET__SHIFT 0x00000000 3151de2bdb3dSTom St Denis #define DCFE2_SOFT_RESET__DCP2_REQ_SOFT_RESET_MASK 0x00000002L 3152de2bdb3dSTom St Denis #define DCFE2_SOFT_RESET__DCP2_REQ_SOFT_RESET__SHIFT 0x00000001 3153de2bdb3dSTom St Denis #define DCFE2_SOFT_RESET__SCL2_ALU_SOFT_RESET_MASK 0x00000004L 3154de2bdb3dSTom St Denis #define DCFE2_SOFT_RESET__SCL2_ALU_SOFT_RESET__SHIFT 0x00000002 3155de2bdb3dSTom St Denis #define DCFE2_SOFT_RESET__SCL2_SOFT_RESET_MASK 0x00000008L 3156de2bdb3dSTom St Denis #define DCFE2_SOFT_RESET__SCL2_SOFT_RESET__SHIFT 0x00000003 3157de2bdb3dSTom St Denis #define DCFE3_SOFT_RESET__CRTC3_SOFT_RESET_MASK 0x00000010L 3158de2bdb3dSTom St Denis #define DCFE3_SOFT_RESET__CRTC3_SOFT_RESET__SHIFT 0x00000004 3159de2bdb3dSTom St Denis #define DCFE3_SOFT_RESET__DCP3_PIXPIPE_SOFT_RESET_MASK 0x00000001L 3160de2bdb3dSTom St Denis #define DCFE3_SOFT_RESET__DCP3_PIXPIPE_SOFT_RESET__SHIFT 0x00000000 3161de2bdb3dSTom St Denis #define DCFE3_SOFT_RESET__DCP3_REQ_SOFT_RESET_MASK 0x00000002L 3162de2bdb3dSTom St Denis #define DCFE3_SOFT_RESET__DCP3_REQ_SOFT_RESET__SHIFT 0x00000001 3163de2bdb3dSTom St Denis #define DCFE3_SOFT_RESET__SCL3_ALU_SOFT_RESET_MASK 0x00000004L 3164de2bdb3dSTom St Denis #define DCFE3_SOFT_RESET__SCL3_ALU_SOFT_RESET__SHIFT 0x00000002 3165de2bdb3dSTom St Denis #define DCFE3_SOFT_RESET__SCL3_SOFT_RESET_MASK 0x00000008L 3166de2bdb3dSTom St Denis #define DCFE3_SOFT_RESET__SCL3_SOFT_RESET__SHIFT 0x00000003 3167de2bdb3dSTom St Denis #define DCFE4_SOFT_RESET__CRTC4_SOFT_RESET_MASK 0x00000010L 3168de2bdb3dSTom St Denis #define DCFE4_SOFT_RESET__CRTC4_SOFT_RESET__SHIFT 0x00000004 3169de2bdb3dSTom St Denis #define DCFE4_SOFT_RESET__DCP4_PIXPIPE_SOFT_RESET_MASK 0x00000001L 3170de2bdb3dSTom St Denis #define DCFE4_SOFT_RESET__DCP4_PIXPIPE_SOFT_RESET__SHIFT 0x00000000 3171de2bdb3dSTom St Denis #define DCFE4_SOFT_RESET__DCP4_REQ_SOFT_RESET_MASK 0x00000002L 3172de2bdb3dSTom St Denis #define DCFE4_SOFT_RESET__DCP4_REQ_SOFT_RESET__SHIFT 0x00000001 3173de2bdb3dSTom St Denis #define DCFE4_SOFT_RESET__SCL4_ALU_SOFT_RESET_MASK 0x00000004L 3174de2bdb3dSTom St Denis #define DCFE4_SOFT_RESET__SCL4_ALU_SOFT_RESET__SHIFT 0x00000002 3175de2bdb3dSTom St Denis #define DCFE4_SOFT_RESET__SCL4_SOFT_RESET_MASK 0x00000008L 3176de2bdb3dSTom St Denis #define DCFE4_SOFT_RESET__SCL4_SOFT_RESET__SHIFT 0x00000003 3177de2bdb3dSTom St Denis #define DCFE5_SOFT_RESET__CRTC5_SOFT_RESET_MASK 0x00000010L 3178de2bdb3dSTom St Denis #define DCFE5_SOFT_RESET__CRTC5_SOFT_RESET__SHIFT 0x00000004 3179de2bdb3dSTom St Denis #define DCFE5_SOFT_RESET__DCP5_PIXPIPE_SOFT_RESET_MASK 0x00000001L 3180de2bdb3dSTom St Denis #define DCFE5_SOFT_RESET__DCP5_PIXPIPE_SOFT_RESET__SHIFT 0x00000000 3181de2bdb3dSTom St Denis #define DCFE5_SOFT_RESET__DCP5_REQ_SOFT_RESET_MASK 0x00000002L 3182de2bdb3dSTom St Denis #define DCFE5_SOFT_RESET__DCP5_REQ_SOFT_RESET__SHIFT 0x00000001 3183de2bdb3dSTom St Denis #define DCFE5_SOFT_RESET__SCL5_ALU_SOFT_RESET_MASK 0x00000004L 3184de2bdb3dSTom St Denis #define DCFE5_SOFT_RESET__SCL5_ALU_SOFT_RESET__SHIFT 0x00000002 3185de2bdb3dSTom St Denis #define DCFE5_SOFT_RESET__SCL5_SOFT_RESET_MASK 0x00000008L 3186de2bdb3dSTom St Denis #define DCFE5_SOFT_RESET__SCL5_SOFT_RESET__SHIFT 0x00000003 3187de2bdb3dSTom St Denis #define DCFE_DBG_SEL__DCFE_DBG_SEL_MASK 0x0000000fL 3188de2bdb3dSTom St Denis #define DCFE_DBG_SEL__DCFE_DBG_SEL__SHIFT 0x00000000 3189de2bdb3dSTom St Denis #define DCFE_MEM_LIGHT_SLEEP_CNTL__DCP_CURSOR_LIGHT_SLEEP_DIS_MASK 0x00000001L 3190de2bdb3dSTom St Denis #define DCFE_MEM_LIGHT_SLEEP_CNTL__DCP_CURSOR_LIGHT_SLEEP_DIS__SHIFT 0x00000000 3191de2bdb3dSTom St Denis #define DCFE_MEM_LIGHT_SLEEP_CNTL__DCP_CURSOR_MEM_PWR_STATE_MASK 0x00000300L 3192de2bdb3dSTom St Denis #define DCFE_MEM_LIGHT_SLEEP_CNTL__DCP_CURSOR_MEM_PWR_STATE__SHIFT 0x00000008 3193de2bdb3dSTom St Denis #define DCFE_MEM_LIGHT_SLEEP_CNTL__DCP_LUT_LIGHT_SLEEP_DIS_MASK 0x00000004L 3194de2bdb3dSTom St Denis #define DCFE_MEM_LIGHT_SLEEP_CNTL__DCP_LUT_LIGHT_SLEEP_DIS__SHIFT 0x00000002 3195de2bdb3dSTom St Denis #define DCFE_MEM_LIGHT_SLEEP_CNTL__DCP_LUT_MEM_PWR_STATE_MASK 0x00003000L 3196de2bdb3dSTom St Denis #define DCFE_MEM_LIGHT_SLEEP_CNTL__DCP_LUT_MEM_PWR_STATE__SHIFT 0x0000000c 3197de2bdb3dSTom St Denis #define DCFE_MEM_LIGHT_SLEEP_CNTL__LB1_MEM_SHUTDOWN_DIS_MASK 0x20000000L 3198de2bdb3dSTom St Denis #define DCFE_MEM_LIGHT_SLEEP_CNTL__LB1_MEM_SHUTDOWN_DIS__SHIFT 0x0000001d 3199de2bdb3dSTom St Denis #define DCFE_MEM_LIGHT_SLEEP_CNTL__LB2_MEM_SHUTDOWN_DIS_MASK 0x40000000L 3200de2bdb3dSTom St Denis #define DCFE_MEM_LIGHT_SLEEP_CNTL__LB2_MEM_SHUTDOWN_DIS__SHIFT 0x0000001e 3201de2bdb3dSTom St Denis #define DCFE_MEM_LIGHT_SLEEP_CNTL__LB_LIGHT_SLEEP_DIS_MASK 0x00000010L 3202de2bdb3dSTom St Denis #define DCFE_MEM_LIGHT_SLEEP_CNTL__LB_LIGHT_SLEEP_DIS__SHIFT 0x00000004 3203de2bdb3dSTom St Denis #define DCFE_MEM_LIGHT_SLEEP_CNTL__LB_MEM_PWR_STATE_0_MASK 0x00030000L 3204de2bdb3dSTom St Denis #define DCFE_MEM_LIGHT_SLEEP_CNTL__LB_MEM_PWR_STATE_0__SHIFT 0x00000010 3205de2bdb3dSTom St Denis #define DCFE_MEM_LIGHT_SLEEP_CNTL__LB_MEM_PWR_STATE_1_MASK 0x00c00000L 3206de2bdb3dSTom St Denis #define DCFE_MEM_LIGHT_SLEEP_CNTL__LB_MEM_PWR_STATE_1__SHIFT 0x00000016 3207de2bdb3dSTom St Denis #define DCFE_MEM_LIGHT_SLEEP_CNTL__LB_MEM_PWR_STATE_2_MASK 0x03000000L 3208de2bdb3dSTom St Denis #define DCFE_MEM_LIGHT_SLEEP_CNTL__LB_MEM_PWR_STATE_2__SHIFT 0x00000018 3209de2bdb3dSTom St Denis #define DCFE_MEM_LIGHT_SLEEP_CNTL__OVLSCL_LIGHT_SLEEP_DIS_MASK 0x00000008L 3210de2bdb3dSTom St Denis #define DCFE_MEM_LIGHT_SLEEP_CNTL__OVLSCL_LIGHT_SLEEP_DIS__SHIFT 0x00000003 3211de2bdb3dSTom St Denis #define DCFE_MEM_LIGHT_SLEEP_CNTL__OVLSCL_MEM_PWR_STATE_MASK 0x0000c000L 3212de2bdb3dSTom St Denis #define DCFE_MEM_LIGHT_SLEEP_CNTL__OVLSCL_MEM_PWR_STATE__SHIFT 0x0000000e 3213de2bdb3dSTom St Denis #define DCFE_MEM_LIGHT_SLEEP_CNTL__PIPE_MEM_SHUTDOWN_DIS_MASK 0x10000000L 3214de2bdb3dSTom St Denis #define DCFE_MEM_LIGHT_SLEEP_CNTL__PIPE_MEM_SHUTDOWN_DIS__SHIFT 0x0000001c 3215de2bdb3dSTom St Denis #define DCFE_MEM_LIGHT_SLEEP_CNTL__REGAMMA_LUT_LIGHT_SLEEP_DIS_MASK 0x00000040L 3216de2bdb3dSTom St Denis #define DCFE_MEM_LIGHT_SLEEP_CNTL__REGAMMA_LUT_LIGHT_SLEEP_DIS__SHIFT 0x00000006 3217de2bdb3dSTom St Denis #define DCFE_MEM_LIGHT_SLEEP_CNTL__REGAMMA_LUT_MEM_PWR_STATE_MASK 0x00300000L 3218de2bdb3dSTom St Denis #define DCFE_MEM_LIGHT_SLEEP_CNTL__REGAMMA_LUT_MEM_PWR_STATE__SHIFT 0x00000014 3219de2bdb3dSTom St Denis #define DCFE_MEM_LIGHT_SLEEP_CNTL__SCL_LIGHT_SLEEP_DIS_MASK 0x00000020L 3220de2bdb3dSTom St Denis #define DCFE_MEM_LIGHT_SLEEP_CNTL__SCL_LIGHT_SLEEP_DIS__SHIFT 0x00000005 3221de2bdb3dSTom St Denis #define DCFE_MEM_LIGHT_SLEEP_CNTL__SCL_MEM_PWR_STATE_MASK 0x000c0000L 3222de2bdb3dSTom St Denis #define DCFE_MEM_LIGHT_SLEEP_CNTL__SCL_MEM_PWR_STATE__SHIFT 0x00000012 3223de2bdb3dSTom St Denis #define DC_GENERICA__GENERICA_EN_MASK 0x00000001L 3224de2bdb3dSTom St Denis #define DC_GENERICA__GENERICA_EN__SHIFT 0x00000000 3225de2bdb3dSTom St Denis #define DC_GENERICA__GENERICA_SEL_MASK 0x00000f00L 3226de2bdb3dSTom St Denis #define DC_GENERICA__GENERICA_SEL__SHIFT 0x00000008 3227de2bdb3dSTom St Denis #define DC_GENERICA__GENERICA_UNIPHY_FBDIV_CLK_DIV2_SEL_MASK 0x07000000L 3228de2bdb3dSTom St Denis #define DC_GENERICA__GENERICA_UNIPHY_FBDIV_CLK_DIV2_SEL__SHIFT 0x00000018 3229de2bdb3dSTom St Denis #define DC_GENERICA__GENERICA_UNIPHY_FBDIV_CLK_SEL_MASK 0x00070000L 3230de2bdb3dSTom St Denis #define DC_GENERICA__GENERICA_UNIPHY_FBDIV_CLK_SEL__SHIFT 0x00000010 3231de2bdb3dSTom St Denis #define DC_GENERICA__GENERICA_UNIPHY_FBDIV_SSC_CLK_SEL_MASK 0x00700000L 3232de2bdb3dSTom St Denis #define DC_GENERICA__GENERICA_UNIPHY_FBDIV_SSC_CLK_SEL__SHIFT 0x00000014 3233de2bdb3dSTom St Denis #define DC_GENERICA__GENERICA_UNIPHY_REFDIV_CLK_SEL_MASK 0x00007000L 3234de2bdb3dSTom St Denis #define DC_GENERICA__GENERICA_UNIPHY_REFDIV_CLK_SEL__SHIFT 0x0000000c 3235de2bdb3dSTom St Denis #define DC_GENERICB__GENERICB_EN_MASK 0x00000001L 3236de2bdb3dSTom St Denis #define DC_GENERICB__GENERICB_EN__SHIFT 0x00000000 3237de2bdb3dSTom St Denis #define DC_GENERICB__GENERICB_SEL_MASK 0x00000f00L 3238de2bdb3dSTom St Denis #define DC_GENERICB__GENERICB_SEL__SHIFT 0x00000008 3239de2bdb3dSTom St Denis #define DC_GENERICB__GENERICB_UNIPHY_FBDIV_CLK_DIV2_SEL_MASK 0x07000000L 3240de2bdb3dSTom St Denis #define DC_GENERICB__GENERICB_UNIPHY_FBDIV_CLK_DIV2_SEL__SHIFT 0x00000018 3241de2bdb3dSTom St Denis #define DC_GENERICB__GENERICB_UNIPHY_FBDIV_CLK_SEL_MASK 0x00070000L 3242de2bdb3dSTom St Denis #define DC_GENERICB__GENERICB_UNIPHY_FBDIV_CLK_SEL__SHIFT 0x00000010 3243de2bdb3dSTom St Denis #define DC_GENERICB__GENERICB_UNIPHY_FBDIV_SSC_CLK_SEL_MASK 0x00700000L 3244de2bdb3dSTom St Denis #define DC_GENERICB__GENERICB_UNIPHY_FBDIV_SSC_CLK_SEL__SHIFT 0x00000014 3245de2bdb3dSTom St Denis #define DC_GENERICB__GENERICB_UNIPHY_REFDIV_CLK_SEL_MASK 0x00007000L 3246de2bdb3dSTom St Denis #define DC_GENERICB__GENERICB_UNIPHY_REFDIV_CLK_SEL__SHIFT 0x0000000c 3247de2bdb3dSTom St Denis #define DC_GPIO_DDC1_A__DC_GPIO_DDC1CLK_A_MASK 0x00000001L 3248de2bdb3dSTom St Denis #define DC_GPIO_DDC1_A__DC_GPIO_DDC1CLK_A__SHIFT 0x00000000 3249de2bdb3dSTom St Denis #define DC_GPIO_DDC1_A__DC_GPIO_DDC1DATA_A_MASK 0x00000100L 3250de2bdb3dSTom St Denis #define DC_GPIO_DDC1_A__DC_GPIO_DDC1DATA_A__SHIFT 0x00000008 3251de2bdb3dSTom St Denis #define DC_GPIO_DDC1_EN__DC_GPIO_DDC1CLK_EN_MASK 0x00000001L 3252de2bdb3dSTom St Denis #define DC_GPIO_DDC1_EN__DC_GPIO_DDC1CLK_EN__SHIFT 0x00000000 3253de2bdb3dSTom St Denis #define DC_GPIO_DDC1_EN__DC_GPIO_DDC1DATA_EN_MASK 0x00000100L 3254de2bdb3dSTom St Denis #define DC_GPIO_DDC1_EN__DC_GPIO_DDC1DATA_EN__SHIFT 0x00000008 3255de2bdb3dSTom St Denis #define DC_GPIO_DDC1_MASK__ALLOW_HW_DDC1_PD_EN_MASK 0x00400000L 3256de2bdb3dSTom St Denis #define DC_GPIO_DDC1_MASK__ALLOW_HW_DDC1_PD_EN__SHIFT 0x00000016 3257de2bdb3dSTom St Denis #define DC_GPIO_DDC1_MASK__AUX1_POL_MASK 0x00100000L 3258de2bdb3dSTom St Denis #define DC_GPIO_DDC1_MASK__AUX1_POL__SHIFT 0x00000014 3259de2bdb3dSTom St Denis #define DC_GPIO_DDC1_MASK__AUX_PAD1_MODE_MASK 0x00010000L 3260de2bdb3dSTom St Denis #define DC_GPIO_DDC1_MASK__AUX_PAD1_MODE__SHIFT 0x00000010 3261de2bdb3dSTom St Denis #define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_MASK_MASK 0x00000001L 3262de2bdb3dSTom St Denis #define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_MASK__SHIFT 0x00000000 3263de2bdb3dSTom St Denis #define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_PD_EN_MASK 0x00000010L 3264de2bdb3dSTom St Denis #define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_PD_EN__SHIFT 0x00000004 3265de2bdb3dSTom St Denis #define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_RECV_MASK 0x00000040L 3266de2bdb3dSTom St Denis #define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_RECV__SHIFT 0x00000006 3267de2bdb3dSTom St Denis #define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_STR_MASK 0x0f000000L 3268de2bdb3dSTom St Denis #define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_STR__SHIFT 0x00000018 3269de2bdb3dSTom St Denis #define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_MASK_MASK 0x00000100L 3270de2bdb3dSTom St Denis #define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_MASK__SHIFT 0x00000008 3271de2bdb3dSTom St Denis #define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_PD_EN_MASK 0x00001000L 3272de2bdb3dSTom St Denis #define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_PD_EN__SHIFT 0x0000000c 3273de2bdb3dSTom St Denis #define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_RECV_MASK 0x00004000L 3274de2bdb3dSTom St Denis #define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_RECV__SHIFT 0x0000000e 3275de2bdb3dSTom St Denis #define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_STR_MASK 0xf0000000L 3276de2bdb3dSTom St Denis #define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_STR__SHIFT 0x0000001c 3277de2bdb3dSTom St Denis #define DC_GPIO_DDC1_Y__DC_GPIO_DDC1CLK_Y_MASK 0x00000001L 3278de2bdb3dSTom St Denis #define DC_GPIO_DDC1_Y__DC_GPIO_DDC1CLK_Y__SHIFT 0x00000000 3279de2bdb3dSTom St Denis #define DC_GPIO_DDC1_Y__DC_GPIO_DDC1DATA_Y_MASK 0x00000100L 3280de2bdb3dSTom St Denis #define DC_GPIO_DDC1_Y__DC_GPIO_DDC1DATA_Y__SHIFT 0x00000008 3281de2bdb3dSTom St Denis #define DC_GPIO_DDC2_A__DC_GPIO_DDC2CLK_A_MASK 0x00000001L 3282de2bdb3dSTom St Denis #define DC_GPIO_DDC2_A__DC_GPIO_DDC2CLK_A__SHIFT 0x00000000 3283de2bdb3dSTom St Denis #define DC_GPIO_DDC2_A__DC_GPIO_DDC2DATA_A_MASK 0x00000100L 3284de2bdb3dSTom St Denis #define DC_GPIO_DDC2_A__DC_GPIO_DDC2DATA_A__SHIFT 0x00000008 3285de2bdb3dSTom St Denis #define DC_GPIO_DDC2_EN__DC_GPIO_DDC2CLK_EN_MASK 0x00000001L 3286de2bdb3dSTom St Denis #define DC_GPIO_DDC2_EN__DC_GPIO_DDC2CLK_EN__SHIFT 0x00000000 3287de2bdb3dSTom St Denis #define DC_GPIO_DDC2_EN__DC_GPIO_DDC2DATA_EN_MASK 0x00000100L 3288de2bdb3dSTom St Denis #define DC_GPIO_DDC2_EN__DC_GPIO_DDC2DATA_EN__SHIFT 0x00000008 3289de2bdb3dSTom St Denis #define DC_GPIO_DDC2_MASK__ALLOW_HW_DDC2_PD_EN_MASK 0x00400000L 3290de2bdb3dSTom St Denis #define DC_GPIO_DDC2_MASK__ALLOW_HW_DDC2_PD_EN__SHIFT 0x00000016 3291de2bdb3dSTom St Denis #define DC_GPIO_DDC2_MASK__AUX2_POL_MASK 0x00100000L 3292de2bdb3dSTom St Denis #define DC_GPIO_DDC2_MASK__AUX2_POL__SHIFT 0x00000014 3293de2bdb3dSTom St Denis #define DC_GPIO_DDC2_MASK__AUX_PAD2_MODE_MASK 0x00010000L 3294de2bdb3dSTom St Denis #define DC_GPIO_DDC2_MASK__AUX_PAD2_MODE__SHIFT 0x00000010 3295de2bdb3dSTom St Denis #define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_MASK_MASK 0x00000001L 3296de2bdb3dSTom St Denis #define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_MASK__SHIFT 0x00000000 3297de2bdb3dSTom St Denis #define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_PD_EN_MASK 0x00000010L 3298de2bdb3dSTom St Denis #define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_PD_EN__SHIFT 0x00000004 3299de2bdb3dSTom St Denis #define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_RECV_MASK 0x00000040L 3300de2bdb3dSTom St Denis #define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_RECV__SHIFT 0x00000006 3301de2bdb3dSTom St Denis #define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_STR_MASK 0x0f000000L 3302de2bdb3dSTom St Denis #define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_STR__SHIFT 0x00000018 3303de2bdb3dSTom St Denis #define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_MASK_MASK 0x00000100L 3304de2bdb3dSTom St Denis #define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_MASK__SHIFT 0x00000008 3305de2bdb3dSTom St Denis #define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_PD_EN_MASK 0x00001000L 3306de2bdb3dSTom St Denis #define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_PD_EN__SHIFT 0x0000000c 3307de2bdb3dSTom St Denis #define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_RECV_MASK 0x00004000L 3308de2bdb3dSTom St Denis #define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_RECV__SHIFT 0x0000000e 3309de2bdb3dSTom St Denis #define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_STR_MASK 0xf0000000L 3310de2bdb3dSTom St Denis #define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_STR__SHIFT 0x0000001c 3311de2bdb3dSTom St Denis #define DC_GPIO_DDC2_Y__DC_GPIO_DDC2CLK_Y_MASK 0x00000001L 3312de2bdb3dSTom St Denis #define DC_GPIO_DDC2_Y__DC_GPIO_DDC2CLK_Y__SHIFT 0x00000000 3313de2bdb3dSTom St Denis #define DC_GPIO_DDC2_Y__DC_GPIO_DDC2DATA_Y_MASK 0x00000100L 3314de2bdb3dSTom St Denis #define DC_GPIO_DDC2_Y__DC_GPIO_DDC2DATA_Y__SHIFT 0x00000008 3315de2bdb3dSTom St Denis #define DC_GPIO_DDC3_A__DC_GPIO_DDC3CLK_A_MASK 0x00000001L 3316de2bdb3dSTom St Denis #define DC_GPIO_DDC3_A__DC_GPIO_DDC3CLK_A__SHIFT 0x00000000 3317de2bdb3dSTom St Denis #define DC_GPIO_DDC3_A__DC_GPIO_DDC3DATA_A_MASK 0x00000100L 3318de2bdb3dSTom St Denis #define DC_GPIO_DDC3_A__DC_GPIO_DDC3DATA_A__SHIFT 0x00000008 3319de2bdb3dSTom St Denis #define DC_GPIO_DDC3_EN__DC_GPIO_DDC3CLK_EN_MASK 0x00000001L 3320de2bdb3dSTom St Denis #define DC_GPIO_DDC3_EN__DC_GPIO_DDC3CLK_EN__SHIFT 0x00000000 3321de2bdb3dSTom St Denis #define DC_GPIO_DDC3_EN__DC_GPIO_DDC3DATA_EN_MASK 0x00000100L 3322de2bdb3dSTom St Denis #define DC_GPIO_DDC3_EN__DC_GPIO_DDC3DATA_EN__SHIFT 0x00000008 3323de2bdb3dSTom St Denis #define DC_GPIO_DDC3_MASK__ALLOW_HW_DDC3_PD_EN_MASK 0x00400000L 3324de2bdb3dSTom St Denis #define DC_GPIO_DDC3_MASK__ALLOW_HW_DDC3_PD_EN__SHIFT 0x00000016 3325de2bdb3dSTom St Denis #define DC_GPIO_DDC3_MASK__AUX3_POL_MASK 0x00100000L 3326de2bdb3dSTom St Denis #define DC_GPIO_DDC3_MASK__AUX3_POL__SHIFT 0x00000014 3327de2bdb3dSTom St Denis #define DC_GPIO_DDC3_MASK__AUX_PAD3_MODE_MASK 0x00010000L 3328de2bdb3dSTom St Denis #define DC_GPIO_DDC3_MASK__AUX_PAD3_MODE__SHIFT 0x00000010 3329de2bdb3dSTom St Denis #define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_MASK_MASK 0x00000001L 3330de2bdb3dSTom St Denis #define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_MASK__SHIFT 0x00000000 3331de2bdb3dSTom St Denis #define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_PD_EN_MASK 0x00000010L 3332de2bdb3dSTom St Denis #define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_PD_EN__SHIFT 0x00000004 3333de2bdb3dSTom St Denis #define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_RECV_MASK 0x00000040L 3334de2bdb3dSTom St Denis #define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_RECV__SHIFT 0x00000006 3335de2bdb3dSTom St Denis #define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_STR_MASK 0x0f000000L 3336de2bdb3dSTom St Denis #define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_STR__SHIFT 0x00000018 3337de2bdb3dSTom St Denis #define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_MASK_MASK 0x00000100L 3338de2bdb3dSTom St Denis #define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_MASK__SHIFT 0x00000008 3339de2bdb3dSTom St Denis #define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_PD_EN_MASK 0x00001000L 3340de2bdb3dSTom St Denis #define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_PD_EN__SHIFT 0x0000000c 3341de2bdb3dSTom St Denis #define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_RECV_MASK 0x00004000L 3342de2bdb3dSTom St Denis #define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_RECV__SHIFT 0x0000000e 3343de2bdb3dSTom St Denis #define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_STR_MASK 0xf0000000L 3344de2bdb3dSTom St Denis #define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_STR__SHIFT 0x0000001c 3345de2bdb3dSTom St Denis #define DC_GPIO_DDC3_Y__DC_GPIO_DDC3CLK_Y_MASK 0x00000001L 3346de2bdb3dSTom St Denis #define DC_GPIO_DDC3_Y__DC_GPIO_DDC3CLK_Y__SHIFT 0x00000000 3347de2bdb3dSTom St Denis #define DC_GPIO_DDC3_Y__DC_GPIO_DDC3DATA_Y_MASK 0x00000100L 3348de2bdb3dSTom St Denis #define DC_GPIO_DDC3_Y__DC_GPIO_DDC3DATA_Y__SHIFT 0x00000008 3349de2bdb3dSTom St Denis #define DC_GPIO_DDC4_A__DC_GPIO_DDC4CLK_A_MASK 0x00000001L 3350de2bdb3dSTom St Denis #define DC_GPIO_DDC4_A__DC_GPIO_DDC4CLK_A__SHIFT 0x00000000 3351de2bdb3dSTom St Denis #define DC_GPIO_DDC4_A__DC_GPIO_DDC4DATA_A_MASK 0x00000100L 3352de2bdb3dSTom St Denis #define DC_GPIO_DDC4_A__DC_GPIO_DDC4DATA_A__SHIFT 0x00000008 3353de2bdb3dSTom St Denis #define DC_GPIO_DDC4_EN__DC_GPIO_DDC4CLK_EN_MASK 0x00000001L 3354de2bdb3dSTom St Denis #define DC_GPIO_DDC4_EN__DC_GPIO_DDC4CLK_EN__SHIFT 0x00000000 3355de2bdb3dSTom St Denis #define DC_GPIO_DDC4_EN__DC_GPIO_DDC4DATA_EN_MASK 0x00000100L 3356de2bdb3dSTom St Denis #define DC_GPIO_DDC4_EN__DC_GPIO_DDC4DATA_EN__SHIFT 0x00000008 3357de2bdb3dSTom St Denis #define DC_GPIO_DDC4_MASK__ALLOW_HW_DDC4_PD_EN_MASK 0x00400000L 3358de2bdb3dSTom St Denis #define DC_GPIO_DDC4_MASK__ALLOW_HW_DDC4_PD_EN__SHIFT 0x00000016 3359de2bdb3dSTom St Denis #define DC_GPIO_DDC4_MASK__AUX4_POL_MASK 0x00100000L 3360de2bdb3dSTom St Denis #define DC_GPIO_DDC4_MASK__AUX4_POL__SHIFT 0x00000014 3361de2bdb3dSTom St Denis #define DC_GPIO_DDC4_MASK__AUX_PAD4_MODE_MASK 0x00010000L 3362de2bdb3dSTom St Denis #define DC_GPIO_DDC4_MASK__AUX_PAD4_MODE__SHIFT 0x00000010 3363de2bdb3dSTom St Denis #define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_MASK_MASK 0x00000001L 3364de2bdb3dSTom St Denis #define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_MASK__SHIFT 0x00000000 3365de2bdb3dSTom St Denis #define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_PD_EN_MASK 0x00000010L 3366de2bdb3dSTom St Denis #define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_PD_EN__SHIFT 0x00000004 3367de2bdb3dSTom St Denis #define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_RECV_MASK 0x00000040L 3368de2bdb3dSTom St Denis #define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_RECV__SHIFT 0x00000006 3369de2bdb3dSTom St Denis #define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_STR_MASK 0x0f000000L 3370de2bdb3dSTom St Denis #define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_STR__SHIFT 0x00000018 3371de2bdb3dSTom St Denis #define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_MASK_MASK 0x00000100L 3372de2bdb3dSTom St Denis #define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_MASK__SHIFT 0x00000008 3373de2bdb3dSTom St Denis #define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_PD_EN_MASK 0x00001000L 3374de2bdb3dSTom St Denis #define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_PD_EN__SHIFT 0x0000000c 3375de2bdb3dSTom St Denis #define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_RECV_MASK 0x00004000L 3376de2bdb3dSTom St Denis #define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_RECV__SHIFT 0x0000000e 3377de2bdb3dSTom St Denis #define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_STR_MASK 0xf0000000L 3378de2bdb3dSTom St Denis #define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_STR__SHIFT 0x0000001c 3379de2bdb3dSTom St Denis #define DC_GPIO_DDC4_Y__DC_GPIO_DDC4CLK_Y_MASK 0x00000001L 3380de2bdb3dSTom St Denis #define DC_GPIO_DDC4_Y__DC_GPIO_DDC4CLK_Y__SHIFT 0x00000000 3381de2bdb3dSTom St Denis #define DC_GPIO_DDC4_Y__DC_GPIO_DDC4DATA_Y_MASK 0x00000100L 3382de2bdb3dSTom St Denis #define DC_GPIO_DDC4_Y__DC_GPIO_DDC4DATA_Y__SHIFT 0x00000008 3383de2bdb3dSTom St Denis #define DC_GPIO_DDC5_A__DC_GPIO_DDC5CLK_A_MASK 0x00000001L 3384de2bdb3dSTom St Denis #define DC_GPIO_DDC5_A__DC_GPIO_DDC5CLK_A__SHIFT 0x00000000 3385de2bdb3dSTom St Denis #define DC_GPIO_DDC5_A__DC_GPIO_DDC5DATA_A_MASK 0x00000100L 3386de2bdb3dSTom St Denis #define DC_GPIO_DDC5_A__DC_GPIO_DDC5DATA_A__SHIFT 0x00000008 3387de2bdb3dSTom St Denis #define DC_GPIO_DDC5_EN__DC_GPIO_DDC5CLK_EN_MASK 0x00000001L 3388de2bdb3dSTom St Denis #define DC_GPIO_DDC5_EN__DC_GPIO_DDC5CLK_EN__SHIFT 0x00000000 3389de2bdb3dSTom St Denis #define DC_GPIO_DDC5_EN__DC_GPIO_DDC5DATA_EN_MASK 0x00000100L 3390de2bdb3dSTom St Denis #define DC_GPIO_DDC5_EN__DC_GPIO_DDC5DATA_EN__SHIFT 0x00000008 3391de2bdb3dSTom St Denis #define DC_GPIO_DDC5_MASK__ALLOW_HW_DDC5_PD_EN_MASK 0x00400000L 3392de2bdb3dSTom St Denis #define DC_GPIO_DDC5_MASK__ALLOW_HW_DDC5_PD_EN__SHIFT 0x00000016 3393de2bdb3dSTom St Denis #define DC_GPIO_DDC5_MASK__AUX5_POL_MASK 0x00100000L 3394de2bdb3dSTom St Denis #define DC_GPIO_DDC5_MASK__AUX5_POL__SHIFT 0x00000014 3395de2bdb3dSTom St Denis #define DC_GPIO_DDC5_MASK__AUX_PAD5_MODE_MASK 0x00010000L 3396de2bdb3dSTom St Denis #define DC_GPIO_DDC5_MASK__AUX_PAD5_MODE__SHIFT 0x00000010 3397de2bdb3dSTom St Denis #define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_MASK_MASK 0x00000001L 3398de2bdb3dSTom St Denis #define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_MASK__SHIFT 0x00000000 3399de2bdb3dSTom St Denis #define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_PD_EN_MASK 0x00000010L 3400de2bdb3dSTom St Denis #define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_PD_EN__SHIFT 0x00000004 3401de2bdb3dSTom St Denis #define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_RECV_MASK 0x00000040L 3402de2bdb3dSTom St Denis #define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_RECV__SHIFT 0x00000006 3403de2bdb3dSTom St Denis #define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_STR_MASK 0x0f000000L 3404de2bdb3dSTom St Denis #define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_STR__SHIFT 0x00000018 3405de2bdb3dSTom St Denis #define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_MASK_MASK 0x00000100L 3406de2bdb3dSTom St Denis #define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_MASK__SHIFT 0x00000008 3407de2bdb3dSTom St Denis #define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_PD_EN_MASK 0x00001000L 3408de2bdb3dSTom St Denis #define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_PD_EN__SHIFT 0x0000000c 3409de2bdb3dSTom St Denis #define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_RECV_MASK 0x00004000L 3410de2bdb3dSTom St Denis #define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_RECV__SHIFT 0x0000000e 3411de2bdb3dSTom St Denis #define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_STR_MASK 0xf0000000L 3412de2bdb3dSTom St Denis #define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_STR__SHIFT 0x0000001c 3413de2bdb3dSTom St Denis #define DC_GPIO_DDC5_Y__DC_GPIO_DDC5CLK_Y_MASK 0x00000001L 3414de2bdb3dSTom St Denis #define DC_GPIO_DDC5_Y__DC_GPIO_DDC5CLK_Y__SHIFT 0x00000000 3415de2bdb3dSTom St Denis #define DC_GPIO_DDC5_Y__DC_GPIO_DDC5DATA_Y_MASK 0x00000100L 3416de2bdb3dSTom St Denis #define DC_GPIO_DDC5_Y__DC_GPIO_DDC5DATA_Y__SHIFT 0x00000008 3417de2bdb3dSTom St Denis #define DC_GPIO_DDC6_A__DC_GPIO_DDC6CLK_A_MASK 0x00000001L 3418de2bdb3dSTom St Denis #define DC_GPIO_DDC6_A__DC_GPIO_DDC6CLK_A__SHIFT 0x00000000 3419de2bdb3dSTom St Denis #define DC_GPIO_DDC6_A__DC_GPIO_DDC6DATA_A_MASK 0x00000100L 3420de2bdb3dSTom St Denis #define DC_GPIO_DDC6_A__DC_GPIO_DDC6DATA_A__SHIFT 0x00000008 3421de2bdb3dSTom St Denis #define DC_GPIO_DDC6_EN__DC_GPIO_DDC6CLK_EN_MASK 0x00000001L 3422de2bdb3dSTom St Denis #define DC_GPIO_DDC6_EN__DC_GPIO_DDC6CLK_EN__SHIFT 0x00000000 3423de2bdb3dSTom St Denis #define DC_GPIO_DDC6_EN__DC_GPIO_DDC6DATA_EN_MASK 0x00000100L 3424de2bdb3dSTom St Denis #define DC_GPIO_DDC6_EN__DC_GPIO_DDC6DATA_EN__SHIFT 0x00000008 3425de2bdb3dSTom St Denis #define DC_GPIO_DDC6_MASK__ALLOW_HW_DDC6_PD_EN_MASK 0x00400000L 3426de2bdb3dSTom St Denis #define DC_GPIO_DDC6_MASK__ALLOW_HW_DDC6_PD_EN__SHIFT 0x00000016 3427de2bdb3dSTom St Denis #define DC_GPIO_DDC6_MASK__AUX6_POL_MASK 0x00100000L 3428de2bdb3dSTom St Denis #define DC_GPIO_DDC6_MASK__AUX6_POL__SHIFT 0x00000014 3429de2bdb3dSTom St Denis #define DC_GPIO_DDC6_MASK__AUX_PAD6_MODE_MASK 0x00010000L 3430de2bdb3dSTom St Denis #define DC_GPIO_DDC6_MASK__AUX_PAD6_MODE__SHIFT 0x00000010 3431de2bdb3dSTom St Denis #define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6CLK_MASK_MASK 0x00000001L 3432de2bdb3dSTom St Denis #define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6CLK_MASK__SHIFT 0x00000000 3433de2bdb3dSTom St Denis #define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6CLK_PD_EN_MASK 0x00000010L 3434de2bdb3dSTom St Denis #define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6CLK_PD_EN__SHIFT 0x00000004 3435de2bdb3dSTom St Denis #define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6CLK_RECV_MASK 0x00000040L 3436de2bdb3dSTom St Denis #define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6CLK_RECV__SHIFT 0x00000006 3437de2bdb3dSTom St Denis #define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6CLK_STR_MASK 0x0f000000L 3438de2bdb3dSTom St Denis #define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6CLK_STR__SHIFT 0x00000018 3439de2bdb3dSTom St Denis #define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6DATA_MASK_MASK 0x00000100L 3440de2bdb3dSTom St Denis #define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6DATA_MASK__SHIFT 0x00000008 3441de2bdb3dSTom St Denis #define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6DATA_PD_EN_MASK 0x00001000L 3442de2bdb3dSTom St Denis #define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6DATA_PD_EN__SHIFT 0x0000000c 3443de2bdb3dSTom St Denis #define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6DATA_RECV_MASK 0x00004000L 3444de2bdb3dSTom St Denis #define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6DATA_RECV__SHIFT 0x0000000e 3445de2bdb3dSTom St Denis #define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6DATA_STR_MASK 0xf0000000L 3446de2bdb3dSTom St Denis #define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6DATA_STR__SHIFT 0x0000001c 3447de2bdb3dSTom St Denis #define DC_GPIO_DDC6_Y__DC_GPIO_DDC6CLK_Y_MASK 0x00000001L 3448de2bdb3dSTom St Denis #define DC_GPIO_DDC6_Y__DC_GPIO_DDC6CLK_Y__SHIFT 0x00000000 3449de2bdb3dSTom St Denis #define DC_GPIO_DDC6_Y__DC_GPIO_DDC6DATA_Y_MASK 0x00000100L 3450de2bdb3dSTom St Denis #define DC_GPIO_DDC6_Y__DC_GPIO_DDC6DATA_Y__SHIFT 0x00000008 3451de2bdb3dSTom St Denis #define DC_GPIO_DDCVGA_A__DC_GPIO_DDCVGACLK_A_MASK 0x00000001L 3452de2bdb3dSTom St Denis #define DC_GPIO_DDCVGA_A__DC_GPIO_DDCVGACLK_A__SHIFT 0x00000000 3453de2bdb3dSTom St Denis #define DC_GPIO_DDCVGA_A__DC_GPIO_DDCVGADATA_A_MASK 0x00000100L 3454de2bdb3dSTom St Denis #define DC_GPIO_DDCVGA_A__DC_GPIO_DDCVGADATA_A__SHIFT 0x00000008 3455de2bdb3dSTom St Denis #define DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGACLK_EN_MASK 0x00000001L 3456de2bdb3dSTom St Denis #define DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGACLK_EN__SHIFT 0x00000000 3457de2bdb3dSTom St Denis #define DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGADATA_EN_MASK 0x00000100L 3458de2bdb3dSTom St Denis #define DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGADATA_EN__SHIFT 0x00000008 3459de2bdb3dSTom St Denis #define DC_GPIO_DDCVGA_MASK__ALLOW_HW_DDCVGA_PD_EN_MASK 0x00400000L 3460de2bdb3dSTom St Denis #define DC_GPIO_DDCVGA_MASK__ALLOW_HW_DDCVGA_PD_EN__SHIFT 0x00000016 3461de2bdb3dSTom St Denis #define DC_GPIO_DDCVGA_MASK__AUX_PADVGA_MODE_MASK 0x00010000L 3462de2bdb3dSTom St Denis #define DC_GPIO_DDCVGA_MASK__AUX_PADVGA_MODE__SHIFT 0x00000010 3463de2bdb3dSTom St Denis #define DC_GPIO_DDCVGA_MASK__AUXVGA_POL_MASK 0x00100000L 3464de2bdb3dSTom St Denis #define DC_GPIO_DDCVGA_MASK__AUXVGA_POL__SHIFT 0x00000014 3465de2bdb3dSTom St Denis #define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_MASK_MASK 0x00000001L 3466de2bdb3dSTom St Denis #define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_MASK__SHIFT 0x00000000 3467de2bdb3dSTom St Denis #define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_RECV_MASK 0x00000040L 3468de2bdb3dSTom St Denis #define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_RECV__SHIFT 0x00000006 3469de2bdb3dSTom St Denis #define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_STR_MASK 0x0f000000L 3470de2bdb3dSTom St Denis #define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_STR__SHIFT 0x00000018 3471de2bdb3dSTom St Denis #define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_MASK_MASK 0x00000100L 3472de2bdb3dSTom St Denis #define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_MASK__SHIFT 0x00000008 3473de2bdb3dSTom St Denis #define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_PD_EN_MASK 0x00001000L 3474de2bdb3dSTom St Denis #define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_PD_EN__SHIFT 0x0000000c 3475de2bdb3dSTom St Denis #define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_RECV_MASK 0x00004000L 3476de2bdb3dSTom St Denis #define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_RECV__SHIFT 0x0000000e 3477de2bdb3dSTom St Denis #define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_STR_MASK 0xf0000000L 3478de2bdb3dSTom St Denis #define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_STR__SHIFT 0x0000001c 3479de2bdb3dSTom St Denis #define DC_GPIO_DDCVGA_Y__DC_GPIO_DDCVGACLK_Y_MASK 0x00000001L 3480de2bdb3dSTom St Denis #define DC_GPIO_DDCVGA_Y__DC_GPIO_DDCVGACLK_Y__SHIFT 0x00000000 3481de2bdb3dSTom St Denis #define DC_GPIO_DDCVGA_Y__DC_GPIO_DDCVGADATA_Y_MASK 0x00000100L 3482de2bdb3dSTom St Denis #define DC_GPIO_DDCVGA_Y__DC_GPIO_DDCVGADATA_Y__SHIFT 0x00000008 3483de2bdb3dSTom St Denis #define DC_GPIO_DEBUG__DC_GPIO_CHIP_DEBUG_OUT_PIN_SEL_MASK 0x00010000L 3484de2bdb3dSTom St Denis #define DC_GPIO_DEBUG__DC_GPIO_CHIP_DEBUG_OUT_PIN_SEL__SHIFT 0x00000010 3485de2bdb3dSTom St Denis #define DC_GPIO_DEBUG__DC_GPIO_MACRO_DEBUG_MASK 0x00000300L 3486de2bdb3dSTom St Denis #define DC_GPIO_DEBUG__DC_GPIO_MACRO_DEBUG__SHIFT 0x00000008 3487de2bdb3dSTom St Denis #define DC_GPIO_DEBUG__DC_GPIO_VIP_DEBUG_MASK 0x00000001L 3488de2bdb3dSTom St Denis #define DC_GPIO_DEBUG__DC_GPIO_VIP_DEBUG__SHIFT 0x00000000 3489de2bdb3dSTom St Denis #define DC_GPIO_DVODATA_A__DC_GPIO_DVOCLK_A_MASK 0x10000000L 3490de2bdb3dSTom St Denis #define DC_GPIO_DVODATA_A__DC_GPIO_DVOCLK_A__SHIFT 0x0000001c 3491de2bdb3dSTom St Denis #define DC_GPIO_DVODATA_A__DC_GPIO_DVOCNTL_A_MASK 0x07000000L 3492de2bdb3dSTom St Denis #define DC_GPIO_DVODATA_A__DC_GPIO_DVOCNTL_A__SHIFT 0x00000018 3493de2bdb3dSTom St Denis #define DC_GPIO_DVODATA_A__DC_GPIO_DVODATA_A_MASK 0x00ffffffL 3494de2bdb3dSTom St Denis #define DC_GPIO_DVODATA_A__DC_GPIO_DVODATA_A__SHIFT 0x00000000 3495de2bdb3dSTom St Denis #define DC_GPIO_DVODATA_A__DC_GPIO_MVP_DVOCNTL_A_MASK 0xc0000000L 3496de2bdb3dSTom St Denis #define DC_GPIO_DVODATA_A__DC_GPIO_MVP_DVOCNTL_A__SHIFT 0x0000001e 3497de2bdb3dSTom St Denis #define DC_GPIO_DVODATA_EN__DC_GPIO_DVOCLK_EN_MASK 0x10000000L 3498de2bdb3dSTom St Denis #define DC_GPIO_DVODATA_EN__DC_GPIO_DVOCLK_EN__SHIFT 0x0000001c 3499de2bdb3dSTom St Denis #define DC_GPIO_DVODATA_EN__DC_GPIO_DVOCNTL_EN_MASK 0x07000000L 3500de2bdb3dSTom St Denis #define DC_GPIO_DVODATA_EN__DC_GPIO_DVOCNTL_EN__SHIFT 0x00000018 3501de2bdb3dSTom St Denis #define DC_GPIO_DVODATA_EN__DC_GPIO_DVODATA_EN_MASK 0x00ffffffL 3502de2bdb3dSTom St Denis #define DC_GPIO_DVODATA_EN__DC_GPIO_DVODATA_EN__SHIFT 0x00000000 3503de2bdb3dSTom St Denis #define DC_GPIO_DVODATA_EN__DC_GPIO_MVP_DVOCNTL_EN_MASK 0xc0000000L 3504de2bdb3dSTom St Denis #define DC_GPIO_DVODATA_EN__DC_GPIO_MVP_DVOCNTL_EN__SHIFT 0x0000001e 3505de2bdb3dSTom St Denis #define DC_GPIO_DVODATA_MASK__DC_GPIO_DVOCLK_MASK_MASK 0x10000000L 3506de2bdb3dSTom St Denis #define DC_GPIO_DVODATA_MASK__DC_GPIO_DVOCLK_MASK__SHIFT 0x0000001c 3507de2bdb3dSTom St Denis #define DC_GPIO_DVODATA_MASK__DC_GPIO_DVOCNTL_MASK_MASK 0x07000000L 3508de2bdb3dSTom St Denis #define DC_GPIO_DVODATA_MASK__DC_GPIO_DVOCNTL_MASK__SHIFT 0x00000018 3509de2bdb3dSTom St Denis #define DC_GPIO_DVODATA_MASK__DC_GPIO_DVODATA_MASK_MASK 0x00ffffffL 3510de2bdb3dSTom St Denis #define DC_GPIO_DVODATA_MASK__DC_GPIO_DVODATA_MASK__SHIFT 0x00000000 3511de2bdb3dSTom St Denis #define DC_GPIO_DVODATA_MASK__DC_GPIO_MVP_DVOCNTL_MASK_MASK 0xc0000000L 3512de2bdb3dSTom St Denis #define DC_GPIO_DVODATA_MASK__DC_GPIO_MVP_DVOCNTL_MASK__SHIFT 0x0000001e 3513de2bdb3dSTom St Denis #define DC_GPIO_DVODATA_Y__DC_GPIO_DVOCLK_Y_MASK 0x10000000L 3514de2bdb3dSTom St Denis #define DC_GPIO_DVODATA_Y__DC_GPIO_DVOCLK_Y__SHIFT 0x0000001c 3515de2bdb3dSTom St Denis #define DC_GPIO_DVODATA_Y__DC_GPIO_DVOCNTL_Y_MASK 0x07000000L 3516de2bdb3dSTom St Denis #define DC_GPIO_DVODATA_Y__DC_GPIO_DVOCNTL_Y__SHIFT 0x00000018 3517de2bdb3dSTom St Denis #define DC_GPIO_DVODATA_Y__DC_GPIO_DVODATA_Y_MASK 0x00ffffffL 3518de2bdb3dSTom St Denis #define DC_GPIO_DVODATA_Y__DC_GPIO_DVODATA_Y__SHIFT 0x00000000 3519de2bdb3dSTom St Denis #define DC_GPIO_DVODATA_Y__DC_GPIO_MVP_DVOCNTL_Y_MASK 0xc0000000L 3520de2bdb3dSTom St Denis #define DC_GPIO_DVODATA_Y__DC_GPIO_MVP_DVOCNTL_Y__SHIFT 0x0000001e 3521de2bdb3dSTom St Denis #define DC_GPIO_GENERIC_A__DC_GPIO_GENERICA_A_MASK 0x00000001L 3522de2bdb3dSTom St Denis #define DC_GPIO_GENERIC_A__DC_GPIO_GENERICA_A__SHIFT 0x00000000 3523de2bdb3dSTom St Denis #define DC_GPIO_GENERIC_A__DC_GPIO_GENERICB_A_MASK 0x00000100L 3524de2bdb3dSTom St Denis #define DC_GPIO_GENERIC_A__DC_GPIO_GENERICB_A__SHIFT 0x00000008 3525de2bdb3dSTom St Denis #define DC_GPIO_GENERIC_A__DC_GPIO_GENERICC_A_MASK 0x00010000L 3526de2bdb3dSTom St Denis #define DC_GPIO_GENERIC_A__DC_GPIO_GENERICC_A__SHIFT 0x00000010 3527de2bdb3dSTom St Denis #define DC_GPIO_GENERIC_A__DC_GPIO_GENERICD_A_MASK 0x00100000L 3528de2bdb3dSTom St Denis #define DC_GPIO_GENERIC_A__DC_GPIO_GENERICD_A__SHIFT 0x00000014 3529de2bdb3dSTom St Denis #define DC_GPIO_GENERIC_A__DC_GPIO_GENERICE_A_MASK 0x00200000L 3530de2bdb3dSTom St Denis #define DC_GPIO_GENERIC_A__DC_GPIO_GENERICE_A__SHIFT 0x00000015 3531de2bdb3dSTom St Denis #define DC_GPIO_GENERIC_A__DC_GPIO_GENERICF_A_MASK 0x00400000L 3532de2bdb3dSTom St Denis #define DC_GPIO_GENERIC_A__DC_GPIO_GENERICF_A__SHIFT 0x00000016 3533de2bdb3dSTom St Denis #define DC_GPIO_GENERIC_A__DC_GPIO_GENERICG_A_MASK 0x00800000L 3534de2bdb3dSTom St Denis #define DC_GPIO_GENERIC_A__DC_GPIO_GENERICG_A__SHIFT 0x00000017 3535de2bdb3dSTom St Denis #define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICA_EN_MASK 0x00000001L 3536de2bdb3dSTom St Denis #define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICA_EN__SHIFT 0x00000000 3537de2bdb3dSTom St Denis #define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICB_EN_MASK 0x00000100L 3538de2bdb3dSTom St Denis #define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICB_EN__SHIFT 0x00000008 3539de2bdb3dSTom St Denis #define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICC_EN_MASK 0x00010000L 3540de2bdb3dSTom St Denis #define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICC_EN__SHIFT 0x00000010 3541de2bdb3dSTom St Denis #define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICD_EN_MASK 0x00100000L 3542de2bdb3dSTom St Denis #define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICD_EN__SHIFT 0x00000014 3543de2bdb3dSTom St Denis #define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICE_EN_MASK 0x00200000L 3544de2bdb3dSTom St Denis #define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICE_EN__SHIFT 0x00000015 3545de2bdb3dSTom St Denis #define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICF_EN_MASK 0x00400000L 3546de2bdb3dSTom St Denis #define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICF_EN__SHIFT 0x00000016 3547de2bdb3dSTom St Denis #define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICG_EN_MASK 0x00800000L 3548de2bdb3dSTom St Denis #define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICG_EN__SHIFT 0x00000017 3549de2bdb3dSTom St Denis #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_MASK_MASK 0x00000001L 3550de2bdb3dSTom St Denis #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_MASK__SHIFT 0x00000000 3551de2bdb3dSTom St Denis #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_PD_DIS_MASK 0x00000002L 3552de2bdb3dSTom St Denis #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_PD_DIS__SHIFT 0x00000001 3553de2bdb3dSTom St Denis #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_RECV_MASK 0x00000004L 3554de2bdb3dSTom St Denis #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_RECV__SHIFT 0x00000002 3555de2bdb3dSTom St Denis #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_MASK_MASK 0x00000010L 3556de2bdb3dSTom St Denis #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_MASK__SHIFT 0x00000004 3557de2bdb3dSTom St Denis #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_PD_DIS_MASK 0x00000020L 3558de2bdb3dSTom St Denis #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_PD_DIS__SHIFT 0x00000005 3559de2bdb3dSTom St Denis #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_RECV_MASK 0x00000040L 3560de2bdb3dSTom St Denis #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_RECV__SHIFT 0x00000006 3561de2bdb3dSTom St Denis #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_MASK_MASK 0x00000100L 3562de2bdb3dSTom St Denis #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_MASK__SHIFT 0x00000008 3563de2bdb3dSTom St Denis #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_PD_DIS_MASK 0x00000200L 3564de2bdb3dSTom St Denis #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_PD_DIS__SHIFT 0x00000009 3565de2bdb3dSTom St Denis #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_RECV_MASK 0x00000400L 3566de2bdb3dSTom St Denis #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_RECV__SHIFT 0x0000000a 3567de2bdb3dSTom St Denis #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_MASK_MASK 0x00001000L 3568de2bdb3dSTom St Denis #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_MASK__SHIFT 0x0000000c 3569de2bdb3dSTom St Denis #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_PD_DIS_MASK 0x00002000L 3570de2bdb3dSTom St Denis #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_PD_DIS__SHIFT 0x0000000d 3571de2bdb3dSTom St Denis #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_RECV_MASK 0x00004000L 3572de2bdb3dSTom St Denis #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_RECV__SHIFT 0x0000000e 3573de2bdb3dSTom St Denis #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_MASK_MASK 0x00010000L 3574de2bdb3dSTom St Denis #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_MASK__SHIFT 0x00000010 3575de2bdb3dSTom St Denis #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_PD_DIS_MASK 0x00020000L 3576de2bdb3dSTom St Denis #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_PD_DIS__SHIFT 0x00000011 3577de2bdb3dSTom St Denis #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_RECV_MASK 0x00040000L 3578de2bdb3dSTom St Denis #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_RECV__SHIFT 0x00000012 3579de2bdb3dSTom St Denis #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_MASK_MASK 0x00100000L 3580de2bdb3dSTom St Denis #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_MASK__SHIFT 0x00000014 3581de2bdb3dSTom St Denis #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_PD_DIS_MASK 0x00200000L 3582de2bdb3dSTom St Denis #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_PD_DIS__SHIFT 0x00000015 3583de2bdb3dSTom St Denis #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_RECV_MASK 0x00400000L 3584de2bdb3dSTom St Denis #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_RECV__SHIFT 0x00000016 3585de2bdb3dSTom St Denis #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_MASK_MASK 0x01000000L 3586de2bdb3dSTom St Denis #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_MASK__SHIFT 0x00000018 3587de2bdb3dSTom St Denis #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_PD_DIS_MASK 0x02000000L 3588de2bdb3dSTom St Denis #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_PD_DIS__SHIFT 0x00000019 3589de2bdb3dSTom St Denis #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_RECV_MASK 0x04000000L 3590de2bdb3dSTom St Denis #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_RECV__SHIFT 0x0000001a 3591de2bdb3dSTom St Denis #define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICA_Y_MASK 0x00000001L 3592de2bdb3dSTom St Denis #define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICA_Y__SHIFT 0x00000000 3593de2bdb3dSTom St Denis #define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICB_Y_MASK 0x00000100L 3594de2bdb3dSTom St Denis #define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICB_Y__SHIFT 0x00000008 3595de2bdb3dSTom St Denis #define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICC_Y_MASK 0x00010000L 3596de2bdb3dSTom St Denis #define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICC_Y__SHIFT 0x00000010 3597de2bdb3dSTom St Denis #define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICD_Y_MASK 0x00100000L 3598de2bdb3dSTom St Denis #define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICD_Y__SHIFT 0x00000014 3599de2bdb3dSTom St Denis #define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICE_Y_MASK 0x00200000L 3600de2bdb3dSTom St Denis #define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICE_Y__SHIFT 0x00000015 3601de2bdb3dSTom St Denis #define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICF_Y_MASK 0x00400000L 3602de2bdb3dSTom St Denis #define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICF_Y__SHIFT 0x00000016 3603de2bdb3dSTom St Denis #define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICG_Y_MASK 0x00800000L 3604de2bdb3dSTom St Denis #define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICG_Y__SHIFT 0x00000017 3605de2bdb3dSTom St Denis #define DC_GPIO_GENLK_A__DC_GPIO_GENLK_CLK_A_MASK 0x00000001L 3606de2bdb3dSTom St Denis #define DC_GPIO_GENLK_A__DC_GPIO_GENLK_CLK_A__SHIFT 0x00000000 3607de2bdb3dSTom St Denis #define DC_GPIO_GENLK_A__DC_GPIO_GENLK_VSYNC_A_MASK 0x00000100L 3608de2bdb3dSTom St Denis #define DC_GPIO_GENLK_A__DC_GPIO_GENLK_VSYNC_A__SHIFT 0x00000008 3609de2bdb3dSTom St Denis #define DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_A_A_MASK 0x00010000L 3610de2bdb3dSTom St Denis #define DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_A_A__SHIFT 0x00000010 3611de2bdb3dSTom St Denis #define DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_B_A_MASK 0x01000000L 3612de2bdb3dSTom St Denis #define DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_B_A__SHIFT 0x00000018 3613de2bdb3dSTom St Denis #define DC_GPIO_GENLK_EN__DC_GPIO_GENLK_CLK_EN_MASK 0x00000001L 3614de2bdb3dSTom St Denis #define DC_GPIO_GENLK_EN__DC_GPIO_GENLK_CLK_EN__SHIFT 0x00000000 3615de2bdb3dSTom St Denis #define DC_GPIO_GENLK_EN__DC_GPIO_GENLK_VSYNC_EN_MASK 0x00000100L 3616de2bdb3dSTom St Denis #define DC_GPIO_GENLK_EN__DC_GPIO_GENLK_VSYNC_EN__SHIFT 0x00000008 3617de2bdb3dSTom St Denis #define DC_GPIO_GENLK_EN__DC_GPIO_SWAPLOCK_A_EN_MASK 0x00010000L 3618de2bdb3dSTom St Denis #define DC_GPIO_GENLK_EN__DC_GPIO_SWAPLOCK_A_EN__SHIFT 0x00000010 3619de2bdb3dSTom St Denis #define DC_GPIO_GENLK_EN__DC_GPIO_SWAPLOCK_B_EN_MASK 0x01000000L 3620de2bdb3dSTom St Denis #define DC_GPIO_GENLK_EN__DC_GPIO_SWAPLOCK_B_EN__SHIFT 0x00000018 3621de2bdb3dSTom St Denis #define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_MASK_MASK 0x00000001L 3622de2bdb3dSTom St Denis #define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_MASK__SHIFT 0x00000000 3623de2bdb3dSTom St Denis #define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_PD_DIS_MASK 0x00000002L 3624de2bdb3dSTom St Denis #define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_PD_DIS__SHIFT 0x00000001 3625de2bdb3dSTom St Denis #define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_PU_EN_MASK 0x00000008L 3626de2bdb3dSTom St Denis #define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_PU_EN__SHIFT 0x00000003 3627de2bdb3dSTom St Denis #define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_RECV_MASK 0x00000004L 3628de2bdb3dSTom St Denis #define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_RECV__SHIFT 0x00000002 3629de2bdb3dSTom St Denis #define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_MASK_MASK 0x00000100L 3630de2bdb3dSTom St Denis #define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_MASK__SHIFT 0x00000008 3631de2bdb3dSTom St Denis #define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_PD_DIS_MASK 0x00000200L 3632de2bdb3dSTom St Denis #define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_PD_DIS__SHIFT 0x00000009 3633de2bdb3dSTom St Denis #define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_PU_EN_MASK 0x00000800L 3634de2bdb3dSTom St Denis #define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_PU_EN__SHIFT 0x0000000b 3635de2bdb3dSTom St Denis #define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_RECV_MASK 0x00000400L 3636de2bdb3dSTom St Denis #define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_RECV__SHIFT 0x0000000a 3637de2bdb3dSTom St Denis #define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_MASK_MASK 0x00010000L 3638de2bdb3dSTom St Denis #define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_MASK__SHIFT 0x00000010 3639de2bdb3dSTom St Denis #define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_PD_DIS_MASK 0x00020000L 3640de2bdb3dSTom St Denis #define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_PD_DIS__SHIFT 0x00000011 3641de2bdb3dSTom St Denis #define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_PU_EN_MASK 0x00080000L 3642de2bdb3dSTom St Denis #define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_PU_EN__SHIFT 0x00000013 3643de2bdb3dSTom St Denis #define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_RECV_MASK 0x00040000L 3644de2bdb3dSTom St Denis #define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_RECV__SHIFT 0x00000012 3645de2bdb3dSTom St Denis #define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_MASK_MASK 0x01000000L 3646de2bdb3dSTom St Denis #define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_MASK__SHIFT 0x00000018 3647de2bdb3dSTom St Denis #define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_PD_DIS_MASK 0x02000000L 3648de2bdb3dSTom St Denis #define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_PD_DIS__SHIFT 0x00000019 3649de2bdb3dSTom St Denis #define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_PU_EN_MASK 0x08000000L 3650de2bdb3dSTom St Denis #define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_PU_EN__SHIFT 0x0000001b 3651de2bdb3dSTom St Denis #define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_RECV_MASK 0x04000000L 3652de2bdb3dSTom St Denis #define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_RECV__SHIFT 0x0000001a 3653de2bdb3dSTom St Denis #define DC_GPIO_GENLK_Y__DC_GPIO_GENLK_CLK_Y_MASK 0x00000001L 3654de2bdb3dSTom St Denis #define DC_GPIO_GENLK_Y__DC_GPIO_GENLK_CLK_Y__SHIFT 0x00000000 3655de2bdb3dSTom St Denis #define DC_GPIO_GENLK_Y__DC_GPIO_GENLK_VSYNC_Y_MASK 0x00000100L 3656de2bdb3dSTom St Denis #define DC_GPIO_GENLK_Y__DC_GPIO_GENLK_VSYNC_Y__SHIFT 0x00000008 3657de2bdb3dSTom St Denis #define DC_GPIO_GENLK_Y__DC_GPIO_SWAPLOCK_A_Y_MASK 0x00010000L 3658de2bdb3dSTom St Denis #define DC_GPIO_GENLK_Y__DC_GPIO_SWAPLOCK_A_Y__SHIFT 0x00000010 3659de2bdb3dSTom St Denis #define DC_GPIO_GENLK_Y__DC_GPIO_SWAPLOCK_B_Y_MASK 0x01000000L 3660de2bdb3dSTom St Denis #define DC_GPIO_GENLK_Y__DC_GPIO_SWAPLOCK_B_Y__SHIFT 0x00000018 3661de2bdb3dSTom St Denis #define DC_GPIO_HPD_A__DC_GPIO_HPD1_A_MASK 0x00000001L 3662de2bdb3dSTom St Denis #define DC_GPIO_HPD_A__DC_GPIO_HPD1_A__SHIFT 0x00000000 3663de2bdb3dSTom St Denis #define DC_GPIO_HPD_A__DC_GPIO_HPD2_A_MASK 0x00000100L 3664de2bdb3dSTom St Denis #define DC_GPIO_HPD_A__DC_GPIO_HPD2_A__SHIFT 0x00000008 3665de2bdb3dSTom St Denis #define DC_GPIO_HPD_A__DC_GPIO_HPD3_A_MASK 0x00010000L 3666de2bdb3dSTom St Denis #define DC_GPIO_HPD_A__DC_GPIO_HPD3_A__SHIFT 0x00000010 3667de2bdb3dSTom St Denis #define DC_GPIO_HPD_A__DC_GPIO_HPD4_A_MASK 0x01000000L 3668de2bdb3dSTom St Denis #define DC_GPIO_HPD_A__DC_GPIO_HPD4_A__SHIFT 0x00000018 3669de2bdb3dSTom St Denis #define DC_GPIO_HPD_A__DC_GPIO_HPD5_A_MASK 0x04000000L 3670de2bdb3dSTom St Denis #define DC_GPIO_HPD_A__DC_GPIO_HPD5_A__SHIFT 0x0000001a 3671de2bdb3dSTom St Denis #define DC_GPIO_HPD_A__DC_GPIO_HPD6_A_MASK 0x10000000L 3672de2bdb3dSTom St Denis #define DC_GPIO_HPD_A__DC_GPIO_HPD6_A__SHIFT 0x0000001c 3673de2bdb3dSTom St Denis #define DC_GPIO_HPD_EN__DC_GPIO_HPD1_EN_MASK 0x00000001L 3674de2bdb3dSTom St Denis #define DC_GPIO_HPD_EN__DC_GPIO_HPD1_EN__SHIFT 0x00000000 3675de2bdb3dSTom St Denis #define DC_GPIO_HPD_EN__DC_GPIO_HPD2_EN_MASK 0x00000100L 3676de2bdb3dSTom St Denis #define DC_GPIO_HPD_EN__DC_GPIO_HPD2_EN__SHIFT 0x00000008 3677de2bdb3dSTom St Denis #define DC_GPIO_HPD_EN__DC_GPIO_HPD3_EN_MASK 0x00010000L 3678de2bdb3dSTom St Denis #define DC_GPIO_HPD_EN__DC_GPIO_HPD3_EN__SHIFT 0x00000010 3679de2bdb3dSTom St Denis #define DC_GPIO_HPD_EN__DC_GPIO_HPD4_EN_MASK 0x01000000L 3680de2bdb3dSTom St Denis #define DC_GPIO_HPD_EN__DC_GPIO_HPD4_EN__SHIFT 0x00000018 3681de2bdb3dSTom St Denis #define DC_GPIO_HPD_EN__DC_GPIO_HPD5_EN_MASK 0x04000000L 3682de2bdb3dSTom St Denis #define DC_GPIO_HPD_EN__DC_GPIO_HPD5_EN__SHIFT 0x0000001a 3683de2bdb3dSTom St Denis #define DC_GPIO_HPD_EN__DC_GPIO_HPD6_EN_MASK 0x10000000L 3684de2bdb3dSTom St Denis #define DC_GPIO_HPD_EN__DC_GPIO_HPD6_EN__SHIFT 0x0000001c 3685de2bdb3dSTom St Denis #define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_MASK_MASK 0x00000001L 3686de2bdb3dSTom St Denis #define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_MASK__SHIFT 0x00000000 3687de2bdb3dSTom St Denis #define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_PD_DIS_MASK 0x00000010L 3688de2bdb3dSTom St Denis #define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_PD_DIS__SHIFT 0x00000004 3689de2bdb3dSTom St Denis #define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_RECV_MASK 0x00000040L 3690de2bdb3dSTom St Denis #define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_RECV__SHIFT 0x00000006 3691de2bdb3dSTom St Denis #define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_MASK_MASK 0x00000100L 3692de2bdb3dSTom St Denis #define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_MASK__SHIFT 0x00000008 3693de2bdb3dSTom St Denis #define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_PD_DIS_MASK 0x00000200L 3694de2bdb3dSTom St Denis #define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_PD_DIS__SHIFT 0x00000009 3695de2bdb3dSTom St Denis #define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_RECV_MASK 0x00000400L 3696de2bdb3dSTom St Denis #define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_RECV__SHIFT 0x0000000a 3697de2bdb3dSTom St Denis #define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_MASK_MASK 0x00010000L 3698de2bdb3dSTom St Denis #define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_MASK__SHIFT 0x00000010 3699de2bdb3dSTom St Denis #define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_PD_DIS_MASK 0x00020000L 3700de2bdb3dSTom St Denis #define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_PD_DIS__SHIFT 0x00000011 3701de2bdb3dSTom St Denis #define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_RECV_MASK 0x00040000L 3702de2bdb3dSTom St Denis #define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_RECV__SHIFT 0x00000012 3703de2bdb3dSTom St Denis #define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_MASK_MASK 0x00100000L 3704de2bdb3dSTom St Denis #define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_MASK__SHIFT 0x00000014 3705de2bdb3dSTom St Denis #define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_PD_DIS_MASK 0x00200000L 3706de2bdb3dSTom St Denis #define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_PD_DIS__SHIFT 0x00000015 3707de2bdb3dSTom St Denis #define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_RECV_MASK 0x00400000L 3708de2bdb3dSTom St Denis #define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_RECV__SHIFT 0x00000016 3709de2bdb3dSTom St Denis #define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_MASK_MASK 0x01000000L 3710de2bdb3dSTom St Denis #define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_MASK__SHIFT 0x00000018 3711de2bdb3dSTom St Denis #define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_PD_DIS_MASK 0x02000000L 3712de2bdb3dSTom St Denis #define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_PD_DIS__SHIFT 0x00000019 3713de2bdb3dSTom St Denis #define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_RECV_MASK 0x04000000L 3714de2bdb3dSTom St Denis #define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_RECV__SHIFT 0x0000001a 3715de2bdb3dSTom St Denis #define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_MASK_MASK 0x10000000L 3716de2bdb3dSTom St Denis #define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_MASK__SHIFT 0x0000001c 3717de2bdb3dSTom St Denis #define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_PD_DIS_MASK 0x20000000L 3718de2bdb3dSTom St Denis #define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_PD_DIS__SHIFT 0x0000001d 3719de2bdb3dSTom St Denis #define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_RECV_MASK 0x40000000L 3720de2bdb3dSTom St Denis #define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_RECV__SHIFT 0x0000001e 3721de2bdb3dSTom St Denis #define DC_GPIO_HPD_Y__DC_GPIO_HPD1_Y_MASK 0x00000001L 3722de2bdb3dSTom St Denis #define DC_GPIO_HPD_Y__DC_GPIO_HPD1_Y__SHIFT 0x00000000 3723de2bdb3dSTom St Denis #define DC_GPIO_HPD_Y__DC_GPIO_HPD2_Y_MASK 0x00000100L 3724de2bdb3dSTom St Denis #define DC_GPIO_HPD_Y__DC_GPIO_HPD2_Y__SHIFT 0x00000008 3725de2bdb3dSTom St Denis #define DC_GPIO_HPD_Y__DC_GPIO_HPD3_Y_MASK 0x00010000L 3726de2bdb3dSTom St Denis #define DC_GPIO_HPD_Y__DC_GPIO_HPD3_Y__SHIFT 0x00000010 3727de2bdb3dSTom St Denis #define DC_GPIO_HPD_Y__DC_GPIO_HPD4_Y_MASK 0x01000000L 3728de2bdb3dSTom St Denis #define DC_GPIO_HPD_Y__DC_GPIO_HPD4_Y__SHIFT 0x00000018 3729de2bdb3dSTom St Denis #define DC_GPIO_HPD_Y__DC_GPIO_HPD5_Y_MASK 0x04000000L 3730de2bdb3dSTom St Denis #define DC_GPIO_HPD_Y__DC_GPIO_HPD5_Y__SHIFT 0x0000001a 3731de2bdb3dSTom St Denis #define DC_GPIO_HPD_Y__DC_GPIO_HPD6_Y_MASK 0x10000000L 3732de2bdb3dSTom St Denis #define DC_GPIO_HPD_Y__DC_GPIO_HPD6_Y__SHIFT 0x0000001c 3733de2bdb3dSTom St Denis #define DC_GPIO_I2CPAD_A__DC_GPIO_SCL_A_MASK 0x00000001L 3734de2bdb3dSTom St Denis #define DC_GPIO_I2CPAD_A__DC_GPIO_SCL_A__SHIFT 0x00000000 3735de2bdb3dSTom St Denis #define DC_GPIO_I2CPAD_A__DC_GPIO_SDA_A_MASK 0x00000002L 3736de2bdb3dSTom St Denis #define DC_GPIO_I2CPAD_A__DC_GPIO_SDA_A__SHIFT 0x00000001 3737de2bdb3dSTom St Denis #define DC_GPIO_I2CPAD_EN__DC_GPIO_SCL_EN_MASK 0x00000001L 3738de2bdb3dSTom St Denis #define DC_GPIO_I2CPAD_EN__DC_GPIO_SCL_EN__SHIFT 0x00000000 3739de2bdb3dSTom St Denis #define DC_GPIO_I2CPAD_EN__DC_GPIO_SDA_EN_MASK 0x00000002L 3740de2bdb3dSTom St Denis #define DC_GPIO_I2CPAD_EN__DC_GPIO_SDA_EN__SHIFT 0x00000001 3741de2bdb3dSTom St Denis #define DC_GPIO_I2CPAD_MASK__DC_GPIO_SCL_MASK_MASK 0x00000001L 3742de2bdb3dSTom St Denis #define DC_GPIO_I2CPAD_MASK__DC_GPIO_SCL_MASK__SHIFT 0x00000000 3743de2bdb3dSTom St Denis #define DC_GPIO_I2CPAD_MASK__DC_GPIO_SCL_PD_DIS_MASK 0x00000002L 3744de2bdb3dSTom St Denis #define DC_GPIO_I2CPAD_MASK__DC_GPIO_SCL_PD_DIS__SHIFT 0x00000001 3745de2bdb3dSTom St Denis #define DC_GPIO_I2CPAD_MASK__DC_GPIO_SCL_RECV_MASK 0x00000004L 3746de2bdb3dSTom St Denis #define DC_GPIO_I2CPAD_MASK__DC_GPIO_SCL_RECV__SHIFT 0x00000002 3747de2bdb3dSTom St Denis #define DC_GPIO_I2CPAD_MASK__DC_GPIO_SDA_MASK_MASK 0x00000010L 3748de2bdb3dSTom St Denis #define DC_GPIO_I2CPAD_MASK__DC_GPIO_SDA_MASK__SHIFT 0x00000004 3749de2bdb3dSTom St Denis #define DC_GPIO_I2CPAD_MASK__DC_GPIO_SDA_PD_DIS_MASK 0x00000020L 3750de2bdb3dSTom St Denis #define DC_GPIO_I2CPAD_MASK__DC_GPIO_SDA_PD_DIS__SHIFT 0x00000005 3751de2bdb3dSTom St Denis #define DC_GPIO_I2CPAD_MASK__DC_GPIO_SDA_RECV_MASK 0x00000040L 3752de2bdb3dSTom St Denis #define DC_GPIO_I2CPAD_MASK__DC_GPIO_SDA_RECV__SHIFT 0x00000006 3753de2bdb3dSTom St Denis #define DC_GPIO_I2CPAD_STRENGTH__I2C_STRENGTH_SN_MASK 0x0000000fL 3754de2bdb3dSTom St Denis #define DC_GPIO_I2CPAD_STRENGTH__I2C_STRENGTH_SN__SHIFT 0x00000000 3755de2bdb3dSTom St Denis #define DC_GPIO_I2CPAD_STRENGTH__I2C_STRENGTH_SP_MASK 0x000000f0L 3756de2bdb3dSTom St Denis #define DC_GPIO_I2CPAD_STRENGTH__I2C_STRENGTH_SP__SHIFT 0x00000004 3757de2bdb3dSTom St Denis #define DC_GPIO_I2CPAD_Y__DC_GPIO_SCL_Y_MASK 0x00000001L 3758de2bdb3dSTom St Denis #define DC_GPIO_I2CPAD_Y__DC_GPIO_SCL_Y__SHIFT 0x00000000 3759de2bdb3dSTom St Denis #define DC_GPIO_I2CPAD_Y__DC_GPIO_SDA_Y_MASK 0x00000002L 3760de2bdb3dSTom St Denis #define DC_GPIO_I2CPAD_Y__DC_GPIO_SDA_Y__SHIFT 0x00000001 3761de2bdb3dSTom St Denis #define DC_GPIO_PAD_STRENGTH_1__GENLK_STRENGTH_SN_MASK 0x0000000fL 3762de2bdb3dSTom St Denis #define DC_GPIO_PAD_STRENGTH_1__GENLK_STRENGTH_SN__SHIFT 0x00000000 3763de2bdb3dSTom St Denis #define DC_GPIO_PAD_STRENGTH_1__GENLK_STRENGTH_SP_MASK 0x000000f0L 3764de2bdb3dSTom St Denis #define DC_GPIO_PAD_STRENGTH_1__GENLK_STRENGTH_SP__SHIFT 0x00000004 3765de2bdb3dSTom St Denis #define DC_GPIO_PAD_STRENGTH_1__SYNC_STRENGTH_SN_MASK 0x0f000000L 3766de2bdb3dSTom St Denis #define DC_GPIO_PAD_STRENGTH_1__SYNC_STRENGTH_SN__SHIFT 0x00000018 3767de2bdb3dSTom St Denis #define DC_GPIO_PAD_STRENGTH_1__SYNC_STRENGTH_SP_MASK 0xf0000000L 3768de2bdb3dSTom St Denis #define DC_GPIO_PAD_STRENGTH_1__SYNC_STRENGTH_SP__SHIFT 0x0000001c 3769de2bdb3dSTom St Denis #define DC_GPIO_PAD_STRENGTH_2__PWRSEQ_STRENGTH_SN_MASK 0x000f0000L 3770de2bdb3dSTom St Denis #define DC_GPIO_PAD_STRENGTH_2__PWRSEQ_STRENGTH_SN__SHIFT 0x00000010 3771de2bdb3dSTom St Denis #define DC_GPIO_PAD_STRENGTH_2__PWRSEQ_STRENGTH_SP_MASK 0x00f00000L 3772de2bdb3dSTom St Denis #define DC_GPIO_PAD_STRENGTH_2__PWRSEQ_STRENGTH_SP__SHIFT 0x00000014 3773de2bdb3dSTom St Denis #define DC_GPIO_PAD_STRENGTH_2__STRENGTH_SN_MASK 0x0000000fL 3774de2bdb3dSTom St Denis #define DC_GPIO_PAD_STRENGTH_2__STRENGTH_SN__SHIFT 0x00000000 3775de2bdb3dSTom St Denis #define DC_GPIO_PAD_STRENGTH_2__STRENGTH_SP_MASK 0x000000f0L 3776de2bdb3dSTom St Denis #define DC_GPIO_PAD_STRENGTH_2__STRENGTH_SP__SHIFT 0x00000004 3777de2bdb3dSTom St Denis #define DC_GPIO_PWRSEQ_A__DC_GPIO_BLON_A_MASK 0x00000001L 3778de2bdb3dSTom St Denis #define DC_GPIO_PWRSEQ_A__DC_GPIO_BLON_A__SHIFT 0x00000000 3779de2bdb3dSTom St Denis #define DC_GPIO_PWRSEQ_A__DC_GPIO_DIGON_A_MASK 0x00000100L 3780de2bdb3dSTom St Denis #define DC_GPIO_PWRSEQ_A__DC_GPIO_DIGON_A__SHIFT 0x00000008 3781de2bdb3dSTom St Denis #define DC_GPIO_PWRSEQ_A__DC_GPIO_ENA_BL_A_MASK 0x00010000L 3782de2bdb3dSTom St Denis #define DC_GPIO_PWRSEQ_A__DC_GPIO_ENA_BL_A__SHIFT 0x00000010 3783de2bdb3dSTom St Denis #define DC_GPIO_PWRSEQ_EN__DC_GPIO_BLON_EN_MASK 0x00000001L 3784de2bdb3dSTom St Denis #define DC_GPIO_PWRSEQ_EN__DC_GPIO_BLON_EN__SHIFT 0x00000000 3785de2bdb3dSTom St Denis #define DC_GPIO_PWRSEQ_EN__DC_GPIO_DIGON_EN_MASK 0x00000100L 3786de2bdb3dSTom St Denis #define DC_GPIO_PWRSEQ_EN__DC_GPIO_DIGON_EN__SHIFT 0x00000008 3787de2bdb3dSTom St Denis #define DC_GPIO_PWRSEQ_EN__DC_GPIO_ENA_BL_EN_MASK 0x00010000L 3788de2bdb3dSTom St Denis #define DC_GPIO_PWRSEQ_EN__DC_GPIO_ENA_BL_EN__SHIFT 0x00000010 3789de2bdb3dSTom St Denis #define DC_GPIO_PWRSEQ_EN__DC_GPIO_VARY_BL_GENERICA_EN_MASK 0x00000002L 3790de2bdb3dSTom St Denis #define DC_GPIO_PWRSEQ_EN__DC_GPIO_VARY_BL_GENERICA_EN__SHIFT 0x00000001 3791de2bdb3dSTom St Denis #define DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_MASK_MASK 0x00000001L 3792de2bdb3dSTom St Denis #define DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_MASK__SHIFT 0x00000000 3793de2bdb3dSTom St Denis #define DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_PD_DIS_MASK 0x00000010L 3794de2bdb3dSTom St Denis #define DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_PD_DIS__SHIFT 0x00000004 3795de2bdb3dSTom St Denis #define DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_RECV_MASK 0x00000040L 3796de2bdb3dSTom St Denis #define DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_RECV__SHIFT 0x00000006 3797de2bdb3dSTom St Denis #define DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_MASK_MASK 0x00000100L 3798de2bdb3dSTom St Denis #define DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_MASK__SHIFT 0x00000008 3799de2bdb3dSTom St Denis #define DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_PD_DIS_MASK 0x00001000L 3800de2bdb3dSTom St Denis #define DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_PD_DIS__SHIFT 0x0000000c 3801de2bdb3dSTom St Denis #define DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_RECV_MASK 0x00004000L 3802de2bdb3dSTom St Denis #define DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_RECV__SHIFT 0x0000000e 3803de2bdb3dSTom St Denis #define DC_GPIO_PWRSEQ_MASK__DC_GPIO_ENA_BL_MASK_MASK 0x00010000L 3804de2bdb3dSTom St Denis #define DC_GPIO_PWRSEQ_MASK__DC_GPIO_ENA_BL_MASK__SHIFT 0x00000010 3805de2bdb3dSTom St Denis #define DC_GPIO_PWRSEQ_MASK__DC_GPIO_ENA_BL_PD_DIS_MASK 0x00100000L 3806de2bdb3dSTom St Denis #define DC_GPIO_PWRSEQ_MASK__DC_GPIO_ENA_BL_PD_DIS__SHIFT 0x00000014 3807de2bdb3dSTom St Denis #define DC_GPIO_PWRSEQ_MASK__DC_GPIO_ENA_BL_RECV_MASK 0x00400000L 3808de2bdb3dSTom St Denis #define DC_GPIO_PWRSEQ_MASK__DC_GPIO_ENA_BL_RECV__SHIFT 0x00000016 3809de2bdb3dSTom St Denis #define DC_GPIO_PWRSEQ_Y__DC_GPIO_BLON_Y_MASK 0x00000001L 3810de2bdb3dSTom St Denis #define DC_GPIO_PWRSEQ_Y__DC_GPIO_BLON_Y__SHIFT 0x00000000 3811de2bdb3dSTom St Denis #define DC_GPIO_PWRSEQ_Y__DC_GPIO_DIGON_Y_MASK 0x00000100L 3812de2bdb3dSTom St Denis #define DC_GPIO_PWRSEQ_Y__DC_GPIO_DIGON_Y__SHIFT 0x00000008 3813de2bdb3dSTom St Denis #define DC_GPIO_PWRSEQ_Y__DC_GPIO_ENA_BL_Y_MASK 0x00010000L 3814de2bdb3dSTom St Denis #define DC_GPIO_PWRSEQ_Y__DC_GPIO_ENA_BL_Y__SHIFT 0x00000010 3815de2bdb3dSTom St Denis #define DC_GPIO_SYNCA_A__DC_GPIO_HSYNCA_A_MASK 0x00000001L 3816de2bdb3dSTom St Denis #define DC_GPIO_SYNCA_A__DC_GPIO_HSYNCA_A__SHIFT 0x00000000 3817de2bdb3dSTom St Denis #define DC_GPIO_SYNCA_A__DC_GPIO_VSYNCA_A_MASK 0x00000100L 3818de2bdb3dSTom St Denis #define DC_GPIO_SYNCA_A__DC_GPIO_VSYNCA_A__SHIFT 0x00000008 3819de2bdb3dSTom St Denis #define DC_GPIO_SYNCA_EN__DC_GPIO_HSYNCA_EN_MASK 0x00000001L 3820de2bdb3dSTom St Denis #define DC_GPIO_SYNCA_EN__DC_GPIO_HSYNCA_EN__SHIFT 0x00000000 3821de2bdb3dSTom St Denis #define DC_GPIO_SYNCA_EN__DC_GPIO_VSYNCA_EN_MASK 0x00000100L 3822de2bdb3dSTom St Denis #define DC_GPIO_SYNCA_EN__DC_GPIO_VSYNCA_EN__SHIFT 0x00000008 3823de2bdb3dSTom St Denis #define DC_GPIO_SYNCA_MASK__DC_GPIO_HSYNCA_CRTC_HSYNC_MASK_MASK 0x07000000L 3824de2bdb3dSTom St Denis #define DC_GPIO_SYNCA_MASK__DC_GPIO_HSYNCA_CRTC_HSYNC_MASK__SHIFT 0x00000018 3825de2bdb3dSTom St Denis #define DC_GPIO_SYNCA_MASK__DC_GPIO_HSYNCA_MASK_MASK 0x00000001L 3826de2bdb3dSTom St Denis #define DC_GPIO_SYNCA_MASK__DC_GPIO_HSYNCA_MASK__SHIFT 0x00000000 3827de2bdb3dSTom St Denis #define DC_GPIO_SYNCA_MASK__DC_GPIO_HSYNCA_PD_DIS_MASK 0x00000010L 3828de2bdb3dSTom St Denis #define DC_GPIO_SYNCA_MASK__DC_GPIO_HSYNCA_PD_DIS__SHIFT 0x00000004 3829de2bdb3dSTom St Denis #define DC_GPIO_SYNCA_MASK__DC_GPIO_HSYNCA_RECV_MASK 0x00000040L 3830de2bdb3dSTom St Denis #define DC_GPIO_SYNCA_MASK__DC_GPIO_HSYNCA_RECV__SHIFT 0x00000006 3831de2bdb3dSTom St Denis #define DC_GPIO_SYNCA_MASK__DC_GPIO_VSYNCA_CRTC_VSYNC_MASK_MASK 0x70000000L 3832de2bdb3dSTom St Denis #define DC_GPIO_SYNCA_MASK__DC_GPIO_VSYNCA_CRTC_VSYNC_MASK__SHIFT 0x0000001c 3833de2bdb3dSTom St Denis #define DC_GPIO_SYNCA_MASK__DC_GPIO_VSYNCA_MASK_MASK 0x00000100L 3834de2bdb3dSTom St Denis #define DC_GPIO_SYNCA_MASK__DC_GPIO_VSYNCA_MASK__SHIFT 0x00000008 3835de2bdb3dSTom St Denis #define DC_GPIO_SYNCA_MASK__DC_GPIO_VSYNCA_PD_DIS_MASK 0x00001000L 3836de2bdb3dSTom St Denis #define DC_GPIO_SYNCA_MASK__DC_GPIO_VSYNCA_PD_DIS__SHIFT 0x0000000c 3837de2bdb3dSTom St Denis #define DC_GPIO_SYNCA_MASK__DC_GPIO_VSYNCA_RECV_MASK 0x00004000L 3838de2bdb3dSTom St Denis #define DC_GPIO_SYNCA_MASK__DC_GPIO_VSYNCA_RECV__SHIFT 0x0000000e 3839de2bdb3dSTom St Denis #define DC_GPIO_SYNCA_Y__DC_GPIO_HSYNCA_Y_MASK 0x00000001L 3840de2bdb3dSTom St Denis #define DC_GPIO_SYNCA_Y__DC_GPIO_HSYNCA_Y__SHIFT 0x00000000 3841de2bdb3dSTom St Denis #define DC_GPIO_SYNCA_Y__DC_GPIO_VSYNCA_Y_MASK 0x00000100L 3842de2bdb3dSTom St Denis #define DC_GPIO_SYNCA_Y__DC_GPIO_VSYNCA_Y__SHIFT 0x00000008 3843de2bdb3dSTom St Denis #define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_READ_SELECT_MASK 0x0000003fL 3844de2bdb3dSTom St Denis #define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_READ_SELECT__SHIFT 0x00000000 3845de2bdb3dSTom St Denis #define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D1_VSYNC_NOM_MASK 0x00000700L 3846de2bdb3dSTom St Denis #define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D1_VSYNC_NOM__SHIFT 0x00000008 3847de2bdb3dSTom St Denis #define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D2_VSYNC_NOM_MASK 0x00003800L 3848de2bdb3dSTom St Denis #define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D2_VSYNC_NOM__SHIFT 0x0000000b 3849de2bdb3dSTom St Denis #define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D3_VSYNC_NOM_MASK 0x0001c000L 3850de2bdb3dSTom St Denis #define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D3_VSYNC_NOM__SHIFT 0x0000000e 3851de2bdb3dSTom St Denis #define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D4_VSYNC_NOM_MASK 0x000e0000L 3852de2bdb3dSTom St Denis #define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D4_VSYNC_NOM__SHIFT 0x00000011 3853de2bdb3dSTom St Denis #define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D5_VSYNC_NOM_MASK 0x00700000L 3854de2bdb3dSTom St Denis #define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D5_VSYNC_NOM__SHIFT 0x00000014 3855de2bdb3dSTom St Denis #define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D6_VSYNC_NOM_MASK 0x03800000L 3856de2bdb3dSTom St Denis #define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D6_VSYNC_NOM__SHIFT 0x00000017 3857de2bdb3dSTom St Denis #define DC_GPU_TIMER_READ__DC_GPU_TIMER_READ_MASK 0xffffffffL 3858de2bdb3dSTom St Denis #define DC_GPU_TIMER_READ__DC_GPU_TIMER_READ__SHIFT 0x00000000 3859de2bdb3dSTom St Denis #define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D1_P_FLIP_MASK 0x00000007L 3860de2bdb3dSTom St Denis #define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D1_P_FLIP__SHIFT 0x00000000 3861de2bdb3dSTom St Denis #define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D2_P_FLIP_MASK 0x00000070L 3862de2bdb3dSTom St Denis #define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D2_P_FLIP__SHIFT 0x00000004 3863de2bdb3dSTom St Denis #define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D3_P_FLIP_MASK 0x00000700L 3864de2bdb3dSTom St Denis #define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D3_P_FLIP__SHIFT 0x00000008 3865de2bdb3dSTom St Denis #define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D4_P_FLIP_MASK 0x00007000L 3866de2bdb3dSTom St Denis #define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D4_P_FLIP__SHIFT 0x0000000c 3867de2bdb3dSTom St Denis #define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D5_P_FLIP_MASK 0x00070000L 3868de2bdb3dSTom St Denis #define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D5_P_FLIP__SHIFT 0x00000010 3869de2bdb3dSTom St Denis #define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D6_P_FLIP_MASK 0x00700000L 3870de2bdb3dSTom St Denis #define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D6_P_FLIP__SHIFT 0x00000014 3871de2bdb3dSTom St Denis #define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D1_V_UPDATE_MASK 0x00000007L 3872de2bdb3dSTom St Denis #define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D1_V_UPDATE__SHIFT 0x00000000 3873de2bdb3dSTom St Denis #define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D2_V_UPDATE_MASK 0x00000070L 3874de2bdb3dSTom St Denis #define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D2_V_UPDATE__SHIFT 0x00000004 3875de2bdb3dSTom St Denis #define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D3_V_UPDATE_MASK 0x00000700L 3876de2bdb3dSTom St Denis #define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D3_V_UPDATE__SHIFT 0x00000008 3877de2bdb3dSTom St Denis #define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D4_V_UPDATE_MASK 0x00007000L 3878de2bdb3dSTom St Denis #define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D4_V_UPDATE__SHIFT 0x0000000c 3879de2bdb3dSTom St Denis #define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D5_V_UPDATE_MASK 0x00070000L 3880de2bdb3dSTom St Denis #define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D5_V_UPDATE__SHIFT 0x00000010 3881de2bdb3dSTom St Denis #define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D6_V_UPDATE_MASK 0x00700000L 3882de2bdb3dSTom St Denis #define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D6_V_UPDATE__SHIFT 0x00000014 3883de2bdb3dSTom St Denis #define DC_HPD1_CONTROL__DC_HPD1_CONNECTION_TIMER_MASK 0x00001fffL 3884de2bdb3dSTom St Denis #define DC_HPD1_CONTROL__DC_HPD1_CONNECTION_TIMER__SHIFT 0x00000000 3885de2bdb3dSTom St Denis #define DC_HPD1_CONTROL__DC_HPD1_EN_MASK 0x10000000L 3886de2bdb3dSTom St Denis #define DC_HPD1_CONTROL__DC_HPD1_EN__SHIFT 0x0000001c 3887de2bdb3dSTom St Denis #define DC_HPD1_CONTROL__DC_HPD1_RX_INT_TIMER_MASK 0x03ff0000L 3888de2bdb3dSTom St Denis #define DC_HPD1_CONTROL__DC_HPD1_RX_INT_TIMER__SHIFT 0x00000010 3889de2bdb3dSTom St Denis #define DC_HPD1_FAST_TRAIN_CNTL__DC_HPD1_CONNECT_AUX_TX_DELAY_MASK 0x000000ffL 3890de2bdb3dSTom St Denis #define DC_HPD1_FAST_TRAIN_CNTL__DC_HPD1_CONNECT_AUX_TX_DELAY__SHIFT 0x00000000 3891de2bdb3dSTom St Denis #define DC_HPD1_FAST_TRAIN_CNTL__DC_HPD1_CONNECT_AUX_TX_EN_MASK 0x01000000L 3892de2bdb3dSTom St Denis #define DC_HPD1_FAST_TRAIN_CNTL__DC_HPD1_CONNECT_AUX_TX_EN__SHIFT 0x00000018 3893de2bdb3dSTom St Denis #define DC_HPD1_FAST_TRAIN_CNTL__DC_HPD1_CONNECT_FAST_TRAIN_DELAY_MASK 0x000ff000L 3894de2bdb3dSTom St Denis #define DC_HPD1_FAST_TRAIN_CNTL__DC_HPD1_CONNECT_FAST_TRAIN_DELAY__SHIFT 0x0000000c 3895de2bdb3dSTom St Denis #define DC_HPD1_FAST_TRAIN_CNTL__DC_HPD1_CONNECT_FAST_TRAIN_EN_MASK 0x10000000L 3896de2bdb3dSTom St Denis #define DC_HPD1_FAST_TRAIN_CNTL__DC_HPD1_CONNECT_FAST_TRAIN_EN__SHIFT 0x0000001c 3897de2bdb3dSTom St Denis #define DC_HPD1_INT_CONTROL__DC_HPD1_INT_ACK_MASK 0x00000001L 3898de2bdb3dSTom St Denis #define DC_HPD1_INT_CONTROL__DC_HPD1_INT_ACK__SHIFT 0x00000000 3899de2bdb3dSTom St Denis #define DC_HPD1_INT_CONTROL__DC_HPD1_INT_EN_MASK 0x00010000L 3900de2bdb3dSTom St Denis #define DC_HPD1_INT_CONTROL__DC_HPD1_INT_EN__SHIFT 0x00000010 3901de2bdb3dSTom St Denis #define DC_HPD1_INT_CONTROL__DC_HPD1_INT_POLARITY_MASK 0x00000100L 3902de2bdb3dSTom St Denis #define DC_HPD1_INT_CONTROL__DC_HPD1_INT_POLARITY__SHIFT 0x00000008 3903de2bdb3dSTom St Denis #define DC_HPD1_INT_CONTROL__DC_HPD1_RX_INT_ACK_MASK 0x00100000L 3904de2bdb3dSTom St Denis #define DC_HPD1_INT_CONTROL__DC_HPD1_RX_INT_ACK__SHIFT 0x00000014 3905de2bdb3dSTom St Denis #define DC_HPD1_INT_CONTROL__DC_HPD1_RX_INT_EN_MASK 0x01000000L 3906de2bdb3dSTom St Denis #define DC_HPD1_INT_CONTROL__DC_HPD1_RX_INT_EN__SHIFT 0x00000018 3907de2bdb3dSTom St Denis #define DC_HPD1_INT_STATUS__DC_HPD1_INT_STATUS_MASK 0x00000001L 3908de2bdb3dSTom St Denis #define DC_HPD1_INT_STATUS__DC_HPD1_INT_STATUS__SHIFT 0x00000000 3909de2bdb3dSTom St Denis #define DC_HPD1_INT_STATUS__DC_HPD1_RX_INT_STATUS_MASK 0x00000100L 3910de2bdb3dSTom St Denis #define DC_HPD1_INT_STATUS__DC_HPD1_RX_INT_STATUS__SHIFT 0x00000008 3911de2bdb3dSTom St Denis #define DC_HPD1_INT_STATUS__DC_HPD1_SENSE_DELAYED_MASK 0x00000010L 3912de2bdb3dSTom St Denis #define DC_HPD1_INT_STATUS__DC_HPD1_SENSE_DELAYED__SHIFT 0x00000004 3913de2bdb3dSTom St Denis #define DC_HPD1_INT_STATUS__DC_HPD1_SENSE_MASK 0x00000002L 3914de2bdb3dSTom St Denis #define DC_HPD1_INT_STATUS__DC_HPD1_SENSE__SHIFT 0x00000001 3915de2bdb3dSTom St Denis #define DC_HPD1_INT_STATUS__DC_HPD1_TOGGLE_FILT_CON_TIMER_VAL_MASK 0x000ff000L 3916de2bdb3dSTom St Denis #define DC_HPD1_INT_STATUS__DC_HPD1_TOGGLE_FILT_CON_TIMER_VAL__SHIFT 0x0000000c 3917de2bdb3dSTom St Denis #define DC_HPD1_INT_STATUS__DC_HPD1_TOGGLE_FILT_DISCON_TIMER_VAL_MASK 0xff000000L 3918de2bdb3dSTom St Denis #define DC_HPD1_INT_STATUS__DC_HPD1_TOGGLE_FILT_DISCON_TIMER_VAL__SHIFT 0x00000018 3919de2bdb3dSTom St Denis #define DC_HPD1_TOGGLE_FILT_CNTL__DC_HPD1_CONNECT_INT_DELAY_MASK 0x000000ffL 3920de2bdb3dSTom St Denis #define DC_HPD1_TOGGLE_FILT_CNTL__DC_HPD1_CONNECT_INT_DELAY__SHIFT 0x00000000 3921de2bdb3dSTom St Denis #define DC_HPD1_TOGGLE_FILT_CNTL__DC_HPD1_DISCONNECT_INT_DELAY_MASK 0x0ff00000L 3922de2bdb3dSTom St Denis #define DC_HPD1_TOGGLE_FILT_CNTL__DC_HPD1_DISCONNECT_INT_DELAY__SHIFT 0x00000014 3923de2bdb3dSTom St Denis #define DC_HPD2_CONTROL__DC_HPD2_CONNECTION_TIMER_MASK 0x00001fffL 3924de2bdb3dSTom St Denis #define DC_HPD2_CONTROL__DC_HPD2_CONNECTION_TIMER__SHIFT 0x00000000 3925de2bdb3dSTom St Denis #define DC_HPD2_CONTROL__DC_HPD2_EN_MASK 0x10000000L 3926de2bdb3dSTom St Denis #define DC_HPD2_CONTROL__DC_HPD2_EN__SHIFT 0x0000001c 3927de2bdb3dSTom St Denis #define DC_HPD2_CONTROL__DC_HPD2_RX_INT_TIMER_MASK 0x03ff0000L 3928de2bdb3dSTom St Denis #define DC_HPD2_CONTROL__DC_HPD2_RX_INT_TIMER__SHIFT 0x00000010 3929de2bdb3dSTom St Denis #define DC_HPD2_FAST_TRAIN_CNTL__DC_HPD2_CONNECT_AUX_TX_DELAY_MASK 0x000000ffL 3930de2bdb3dSTom St Denis #define DC_HPD2_FAST_TRAIN_CNTL__DC_HPD2_CONNECT_AUX_TX_DELAY__SHIFT 0x00000000 3931de2bdb3dSTom St Denis #define DC_HPD2_FAST_TRAIN_CNTL__DC_HPD2_CONNECT_AUX_TX_EN_MASK 0x01000000L 3932de2bdb3dSTom St Denis #define DC_HPD2_FAST_TRAIN_CNTL__DC_HPD2_CONNECT_AUX_TX_EN__SHIFT 0x00000018 3933de2bdb3dSTom St Denis #define DC_HPD2_FAST_TRAIN_CNTL__DC_HPD2_CONNECT_FAST_TRAIN_DELAY_MASK 0x000ff000L 3934de2bdb3dSTom St Denis #define DC_HPD2_FAST_TRAIN_CNTL__DC_HPD2_CONNECT_FAST_TRAIN_DELAY__SHIFT 0x0000000c 3935de2bdb3dSTom St Denis #define DC_HPD2_FAST_TRAIN_CNTL__DC_HPD2_CONNECT_FAST_TRAIN_EN_MASK 0x10000000L 3936de2bdb3dSTom St Denis #define DC_HPD2_FAST_TRAIN_CNTL__DC_HPD2_CONNECT_FAST_TRAIN_EN__SHIFT 0x0000001c 3937de2bdb3dSTom St Denis #define DC_HPD2_INT_CONTROL__DC_HPD2_INT_ACK_MASK 0x00000001L 3938de2bdb3dSTom St Denis #define DC_HPD2_INT_CONTROL__DC_HPD2_INT_ACK__SHIFT 0x00000000 3939de2bdb3dSTom St Denis #define DC_HPD2_INT_CONTROL__DC_HPD2_INT_EN_MASK 0x00010000L 3940de2bdb3dSTom St Denis #define DC_HPD2_INT_CONTROL__DC_HPD2_INT_EN__SHIFT 0x00000010 3941de2bdb3dSTom St Denis #define DC_HPD2_INT_CONTROL__DC_HPD2_INT_POLARITY_MASK 0x00000100L 3942de2bdb3dSTom St Denis #define DC_HPD2_INT_CONTROL__DC_HPD2_INT_POLARITY__SHIFT 0x00000008 3943de2bdb3dSTom St Denis #define DC_HPD2_INT_CONTROL__DC_HPD2_RX_INT_ACK_MASK 0x00100000L 3944de2bdb3dSTom St Denis #define DC_HPD2_INT_CONTROL__DC_HPD2_RX_INT_ACK__SHIFT 0x00000014 3945de2bdb3dSTom St Denis #define DC_HPD2_INT_CONTROL__DC_HPD2_RX_INT_EN_MASK 0x01000000L 3946de2bdb3dSTom St Denis #define DC_HPD2_INT_CONTROL__DC_HPD2_RX_INT_EN__SHIFT 0x00000018 3947de2bdb3dSTom St Denis #define DC_HPD2_INT_STATUS__DC_HPD2_INT_STATUS_MASK 0x00000001L 3948de2bdb3dSTom St Denis #define DC_HPD2_INT_STATUS__DC_HPD2_INT_STATUS__SHIFT 0x00000000 3949de2bdb3dSTom St Denis #define DC_HPD2_INT_STATUS__DC_HPD2_RX_INT_STATUS_MASK 0x00000100L 3950de2bdb3dSTom St Denis #define DC_HPD2_INT_STATUS__DC_HPD2_RX_INT_STATUS__SHIFT 0x00000008 3951de2bdb3dSTom St Denis #define DC_HPD2_INT_STATUS__DC_HPD2_SENSE_DELAYED_MASK 0x00000010L 3952de2bdb3dSTom St Denis #define DC_HPD2_INT_STATUS__DC_HPD2_SENSE_DELAYED__SHIFT 0x00000004 3953de2bdb3dSTom St Denis #define DC_HPD2_INT_STATUS__DC_HPD2_SENSE_MASK 0x00000002L 3954de2bdb3dSTom St Denis #define DC_HPD2_INT_STATUS__DC_HPD2_SENSE__SHIFT 0x00000001 3955de2bdb3dSTom St Denis #define DC_HPD2_INT_STATUS__DC_HPD2_TOGGLE_FILT_CON_TIMER_VAL_MASK 0x000ff000L 3956de2bdb3dSTom St Denis #define DC_HPD2_INT_STATUS__DC_HPD2_TOGGLE_FILT_CON_TIMER_VAL__SHIFT 0x0000000c 3957de2bdb3dSTom St Denis #define DC_HPD2_INT_STATUS__DC_HPD2_TOGGLE_FILT_DISCON_TIMER_VAL_MASK 0xff000000L 3958de2bdb3dSTom St Denis #define DC_HPD2_INT_STATUS__DC_HPD2_TOGGLE_FILT_DISCON_TIMER_VAL__SHIFT 0x00000018 3959de2bdb3dSTom St Denis #define DC_HPD2_TOGGLE_FILT_CNTL__DC_HPD2_CONNECT_INT_DELAY_MASK 0x000000ffL 3960de2bdb3dSTom St Denis #define DC_HPD2_TOGGLE_FILT_CNTL__DC_HPD2_CONNECT_INT_DELAY__SHIFT 0x00000000 3961de2bdb3dSTom St Denis #define DC_HPD2_TOGGLE_FILT_CNTL__DC_HPD2_DISCONNECT_INT_DELAY_MASK 0x0ff00000L 3962de2bdb3dSTom St Denis #define DC_HPD2_TOGGLE_FILT_CNTL__DC_HPD2_DISCONNECT_INT_DELAY__SHIFT 0x00000014 3963de2bdb3dSTom St Denis #define DC_HPD3_CONTROL__DC_HPD3_CONNECTION_TIMER_MASK 0x00001fffL 3964de2bdb3dSTom St Denis #define DC_HPD3_CONTROL__DC_HPD3_CONNECTION_TIMER__SHIFT 0x00000000 3965de2bdb3dSTom St Denis #define DC_HPD3_CONTROL__DC_HPD3_EN_MASK 0x10000000L 3966de2bdb3dSTom St Denis #define DC_HPD3_CONTROL__DC_HPD3_EN__SHIFT 0x0000001c 3967de2bdb3dSTom St Denis #define DC_HPD3_CONTROL__DC_HPD3_RX_INT_TIMER_MASK 0x03ff0000L 3968de2bdb3dSTom St Denis #define DC_HPD3_CONTROL__DC_HPD3_RX_INT_TIMER__SHIFT 0x00000010 3969de2bdb3dSTom St Denis #define DC_HPD3_FAST_TRAIN_CNTL__DC_HPD3_CONNECT_AUX_TX_DELAY_MASK 0x000000ffL 3970de2bdb3dSTom St Denis #define DC_HPD3_FAST_TRAIN_CNTL__DC_HPD3_CONNECT_AUX_TX_DELAY__SHIFT 0x00000000 3971de2bdb3dSTom St Denis #define DC_HPD3_FAST_TRAIN_CNTL__DC_HPD3_CONNECT_AUX_TX_EN_MASK 0x01000000L 3972de2bdb3dSTom St Denis #define DC_HPD3_FAST_TRAIN_CNTL__DC_HPD3_CONNECT_AUX_TX_EN__SHIFT 0x00000018 3973de2bdb3dSTom St Denis #define DC_HPD3_FAST_TRAIN_CNTL__DC_HPD3_CONNECT_FAST_TRAIN_DELAY_MASK 0x000ff000L 3974de2bdb3dSTom St Denis #define DC_HPD3_FAST_TRAIN_CNTL__DC_HPD3_CONNECT_FAST_TRAIN_DELAY__SHIFT 0x0000000c 3975de2bdb3dSTom St Denis #define DC_HPD3_FAST_TRAIN_CNTL__DC_HPD3_CONNECT_FAST_TRAIN_EN_MASK 0x10000000L 3976de2bdb3dSTom St Denis #define DC_HPD3_FAST_TRAIN_CNTL__DC_HPD3_CONNECT_FAST_TRAIN_EN__SHIFT 0x0000001c 3977de2bdb3dSTom St Denis #define DC_HPD3_INT_CONTROL__DC_HPD3_INT_ACK_MASK 0x00000001L 3978de2bdb3dSTom St Denis #define DC_HPD3_INT_CONTROL__DC_HPD3_INT_ACK__SHIFT 0x00000000 3979de2bdb3dSTom St Denis #define DC_HPD3_INT_CONTROL__DC_HPD3_INT_EN_MASK 0x00010000L 3980de2bdb3dSTom St Denis #define DC_HPD3_INT_CONTROL__DC_HPD3_INT_EN__SHIFT 0x00000010 3981de2bdb3dSTom St Denis #define DC_HPD3_INT_CONTROL__DC_HPD3_INT_POLARITY_MASK 0x00000100L 3982de2bdb3dSTom St Denis #define DC_HPD3_INT_CONTROL__DC_HPD3_INT_POLARITY__SHIFT 0x00000008 3983de2bdb3dSTom St Denis #define DC_HPD3_INT_CONTROL__DC_HPD3_RX_INT_ACK_MASK 0x00100000L 3984de2bdb3dSTom St Denis #define DC_HPD3_INT_CONTROL__DC_HPD3_RX_INT_ACK__SHIFT 0x00000014 3985de2bdb3dSTom St Denis #define DC_HPD3_INT_CONTROL__DC_HPD3_RX_INT_EN_MASK 0x01000000L 3986de2bdb3dSTom St Denis #define DC_HPD3_INT_CONTROL__DC_HPD3_RX_INT_EN__SHIFT 0x00000018 3987de2bdb3dSTom St Denis #define DC_HPD3_INT_STATUS__DC_HPD3_INT_STATUS_MASK 0x00000001L 3988de2bdb3dSTom St Denis #define DC_HPD3_INT_STATUS__DC_HPD3_INT_STATUS__SHIFT 0x00000000 3989de2bdb3dSTom St Denis #define DC_HPD3_INT_STATUS__DC_HPD3_RX_INT_STATUS_MASK 0x00000100L 3990de2bdb3dSTom St Denis #define DC_HPD3_INT_STATUS__DC_HPD3_RX_INT_STATUS__SHIFT 0x00000008 3991de2bdb3dSTom St Denis #define DC_HPD3_INT_STATUS__DC_HPD3_SENSE_DELAYED_MASK 0x00000010L 3992de2bdb3dSTom St Denis #define DC_HPD3_INT_STATUS__DC_HPD3_SENSE_DELAYED__SHIFT 0x00000004 3993de2bdb3dSTom St Denis #define DC_HPD3_INT_STATUS__DC_HPD3_SENSE_MASK 0x00000002L 3994de2bdb3dSTom St Denis #define DC_HPD3_INT_STATUS__DC_HPD3_SENSE__SHIFT 0x00000001 3995de2bdb3dSTom St Denis #define DC_HPD3_INT_STATUS__DC_HPD3_TOGGLE_FILT_CON_TIMER_VAL_MASK 0x000ff000L 3996de2bdb3dSTom St Denis #define DC_HPD3_INT_STATUS__DC_HPD3_TOGGLE_FILT_CON_TIMER_VAL__SHIFT 0x0000000c 3997de2bdb3dSTom St Denis #define DC_HPD3_INT_STATUS__DC_HPD3_TOGGLE_FILT_DISCON_TIMER_VAL_MASK 0xff000000L 3998de2bdb3dSTom St Denis #define DC_HPD3_INT_STATUS__DC_HPD3_TOGGLE_FILT_DISCON_TIMER_VAL__SHIFT 0x00000018 3999de2bdb3dSTom St Denis #define DC_HPD3_TOGGLE_FILT_CNTL__DC_HPD3_CONNECT_INT_DELAY_MASK 0x000000ffL 4000de2bdb3dSTom St Denis #define DC_HPD3_TOGGLE_FILT_CNTL__DC_HPD3_CONNECT_INT_DELAY__SHIFT 0x00000000 4001de2bdb3dSTom St Denis #define DC_HPD3_TOGGLE_FILT_CNTL__DC_HPD3_DISCONNECT_INT_DELAY_MASK 0x0ff00000L 4002de2bdb3dSTom St Denis #define DC_HPD3_TOGGLE_FILT_CNTL__DC_HPD3_DISCONNECT_INT_DELAY__SHIFT 0x00000014 4003de2bdb3dSTom St Denis #define DC_HPD4_CONTROL__DC_HPD4_CONNECTION_TIMER_MASK 0x00001fffL 4004de2bdb3dSTom St Denis #define DC_HPD4_CONTROL__DC_HPD4_CONNECTION_TIMER__SHIFT 0x00000000 4005de2bdb3dSTom St Denis #define DC_HPD4_CONTROL__DC_HPD4_EN_MASK 0x10000000L 4006de2bdb3dSTom St Denis #define DC_HPD4_CONTROL__DC_HPD4_EN__SHIFT 0x0000001c 4007de2bdb3dSTom St Denis #define DC_HPD4_CONTROL__DC_HPD4_RX_INT_TIMER_MASK 0x03ff0000L 4008de2bdb3dSTom St Denis #define DC_HPD4_CONTROL__DC_HPD4_RX_INT_TIMER__SHIFT 0x00000010 4009de2bdb3dSTom St Denis #define DC_HPD4_FAST_TRAIN_CNTL__DC_HPD4_CONNECT_AUX_TX_DELAY_MASK 0x000000ffL 4010de2bdb3dSTom St Denis #define DC_HPD4_FAST_TRAIN_CNTL__DC_HPD4_CONNECT_AUX_TX_DELAY__SHIFT 0x00000000 4011de2bdb3dSTom St Denis #define DC_HPD4_FAST_TRAIN_CNTL__DC_HPD4_CONNECT_AUX_TX_EN_MASK 0x01000000L 4012de2bdb3dSTom St Denis #define DC_HPD4_FAST_TRAIN_CNTL__DC_HPD4_CONNECT_AUX_TX_EN__SHIFT 0x00000018 4013de2bdb3dSTom St Denis #define DC_HPD4_FAST_TRAIN_CNTL__DC_HPD4_CONNECT_FAST_TRAIN_DELAY_MASK 0x000ff000L 4014de2bdb3dSTom St Denis #define DC_HPD4_FAST_TRAIN_CNTL__DC_HPD4_CONNECT_FAST_TRAIN_DELAY__SHIFT 0x0000000c 4015de2bdb3dSTom St Denis #define DC_HPD4_FAST_TRAIN_CNTL__DC_HPD4_CONNECT_FAST_TRAIN_EN_MASK 0x10000000L 4016de2bdb3dSTom St Denis #define DC_HPD4_FAST_TRAIN_CNTL__DC_HPD4_CONNECT_FAST_TRAIN_EN__SHIFT 0x0000001c 4017de2bdb3dSTom St Denis #define DC_HPD4_INT_CONTROL__DC_HPD4_INT_ACK_MASK 0x00000001L 4018de2bdb3dSTom St Denis #define DC_HPD4_INT_CONTROL__DC_HPD4_INT_ACK__SHIFT 0x00000000 4019de2bdb3dSTom St Denis #define DC_HPD4_INT_CONTROL__DC_HPD4_INT_EN_MASK 0x00010000L 4020de2bdb3dSTom St Denis #define DC_HPD4_INT_CONTROL__DC_HPD4_INT_EN__SHIFT 0x00000010 4021de2bdb3dSTom St Denis #define DC_HPD4_INT_CONTROL__DC_HPD4_INT_POLARITY_MASK 0x00000100L 4022de2bdb3dSTom St Denis #define DC_HPD4_INT_CONTROL__DC_HPD4_INT_POLARITY__SHIFT 0x00000008 4023de2bdb3dSTom St Denis #define DC_HPD4_INT_CONTROL__DC_HPD4_RX_INT_ACK_MASK 0x00100000L 4024de2bdb3dSTom St Denis #define DC_HPD4_INT_CONTROL__DC_HPD4_RX_INT_ACK__SHIFT 0x00000014 4025de2bdb3dSTom St Denis #define DC_HPD4_INT_CONTROL__DC_HPD4_RX_INT_EN_MASK 0x01000000L 4026de2bdb3dSTom St Denis #define DC_HPD4_INT_CONTROL__DC_HPD4_RX_INT_EN__SHIFT 0x00000018 4027de2bdb3dSTom St Denis #define DC_HPD4_INT_STATUS__DC_HPD4_INT_STATUS_MASK 0x00000001L 4028de2bdb3dSTom St Denis #define DC_HPD4_INT_STATUS__DC_HPD4_INT_STATUS__SHIFT 0x00000000 4029de2bdb3dSTom St Denis #define DC_HPD4_INT_STATUS__DC_HPD4_RX_INT_STATUS_MASK 0x00000100L 4030de2bdb3dSTom St Denis #define DC_HPD4_INT_STATUS__DC_HPD4_RX_INT_STATUS__SHIFT 0x00000008 4031de2bdb3dSTom St Denis #define DC_HPD4_INT_STATUS__DC_HPD4_SENSE_DELAYED_MASK 0x00000010L 4032de2bdb3dSTom St Denis #define DC_HPD4_INT_STATUS__DC_HPD4_SENSE_DELAYED__SHIFT 0x00000004 4033de2bdb3dSTom St Denis #define DC_HPD4_INT_STATUS__DC_HPD4_SENSE_MASK 0x00000002L 4034de2bdb3dSTom St Denis #define DC_HPD4_INT_STATUS__DC_HPD4_SENSE__SHIFT 0x00000001 4035de2bdb3dSTom St Denis #define DC_HPD4_INT_STATUS__DC_HPD4_TOGGLE_FILT_CON_TIMER_VAL_MASK 0x000ff000L 4036de2bdb3dSTom St Denis #define DC_HPD4_INT_STATUS__DC_HPD4_TOGGLE_FILT_CON_TIMER_VAL__SHIFT 0x0000000c 4037de2bdb3dSTom St Denis #define DC_HPD4_INT_STATUS__DC_HPD4_TOGGLE_FILT_DISCON_TIMER_VAL_MASK 0xff000000L 4038de2bdb3dSTom St Denis #define DC_HPD4_INT_STATUS__DC_HPD4_TOGGLE_FILT_DISCON_TIMER_VAL__SHIFT 0x00000018 4039de2bdb3dSTom St Denis #define DC_HPD4_TOGGLE_FILT_CNTL__DC_HPD4_CONNECT_INT_DELAY_MASK 0x000000ffL 4040de2bdb3dSTom St Denis #define DC_HPD4_TOGGLE_FILT_CNTL__DC_HPD4_CONNECT_INT_DELAY__SHIFT 0x00000000 4041de2bdb3dSTom St Denis #define DC_HPD4_TOGGLE_FILT_CNTL__DC_HPD4_DISCONNECT_INT_DELAY_MASK 0x0ff00000L 4042de2bdb3dSTom St Denis #define DC_HPD4_TOGGLE_FILT_CNTL__DC_HPD4_DISCONNECT_INT_DELAY__SHIFT 0x00000014 4043de2bdb3dSTom St Denis #define DC_HPD5_CONTROL__DC_HPD5_CONNECTION_TIMER_MASK 0x00001fffL 4044de2bdb3dSTom St Denis #define DC_HPD5_CONTROL__DC_HPD5_CONNECTION_TIMER__SHIFT 0x00000000 4045de2bdb3dSTom St Denis #define DC_HPD5_CONTROL__DC_HPD5_EN_MASK 0x10000000L 4046de2bdb3dSTom St Denis #define DC_HPD5_CONTROL__DC_HPD5_EN__SHIFT 0x0000001c 4047de2bdb3dSTom St Denis #define DC_HPD5_CONTROL__DC_HPD5_RX_INT_TIMER_MASK 0x03ff0000L 4048de2bdb3dSTom St Denis #define DC_HPD5_CONTROL__DC_HPD5_RX_INT_TIMER__SHIFT 0x00000010 4049de2bdb3dSTom St Denis #define DC_HPD5_FAST_TRAIN_CNTL__DC_HPD5_CONNECT_AUX_TX_DELAY_MASK 0x000000ffL 4050de2bdb3dSTom St Denis #define DC_HPD5_FAST_TRAIN_CNTL__DC_HPD5_CONNECT_AUX_TX_DELAY__SHIFT 0x00000000 4051de2bdb3dSTom St Denis #define DC_HPD5_FAST_TRAIN_CNTL__DC_HPD5_CONNECT_AUX_TX_EN_MASK 0x01000000L 4052de2bdb3dSTom St Denis #define DC_HPD5_FAST_TRAIN_CNTL__DC_HPD5_CONNECT_AUX_TX_EN__SHIFT 0x00000018 4053de2bdb3dSTom St Denis #define DC_HPD5_FAST_TRAIN_CNTL__DC_HPD5_CONNECT_FAST_TRAIN_DELAY_MASK 0x000ff000L 4054de2bdb3dSTom St Denis #define DC_HPD5_FAST_TRAIN_CNTL__DC_HPD5_CONNECT_FAST_TRAIN_DELAY__SHIFT 0x0000000c 4055de2bdb3dSTom St Denis #define DC_HPD5_FAST_TRAIN_CNTL__DC_HPD5_CONNECT_FAST_TRAIN_EN_MASK 0x10000000L 4056de2bdb3dSTom St Denis #define DC_HPD5_FAST_TRAIN_CNTL__DC_HPD5_CONNECT_FAST_TRAIN_EN__SHIFT 0x0000001c 4057de2bdb3dSTom St Denis #define DC_HPD5_INT_CONTROL__DC_HPD5_INT_ACK_MASK 0x00000001L 4058de2bdb3dSTom St Denis #define DC_HPD5_INT_CONTROL__DC_HPD5_INT_ACK__SHIFT 0x00000000 4059de2bdb3dSTom St Denis #define DC_HPD5_INT_CONTROL__DC_HPD5_INT_EN_MASK 0x00010000L 4060de2bdb3dSTom St Denis #define DC_HPD5_INT_CONTROL__DC_HPD5_INT_EN__SHIFT 0x00000010 4061de2bdb3dSTom St Denis #define DC_HPD5_INT_CONTROL__DC_HPD5_INT_POLARITY_MASK 0x00000100L 4062de2bdb3dSTom St Denis #define DC_HPD5_INT_CONTROL__DC_HPD5_INT_POLARITY__SHIFT 0x00000008 4063de2bdb3dSTom St Denis #define DC_HPD5_INT_CONTROL__DC_HPD5_RX_INT_ACK_MASK 0x00100000L 4064de2bdb3dSTom St Denis #define DC_HPD5_INT_CONTROL__DC_HPD5_RX_INT_ACK__SHIFT 0x00000014 4065de2bdb3dSTom St Denis #define DC_HPD5_INT_CONTROL__DC_HPD5_RX_INT_EN_MASK 0x01000000L 4066de2bdb3dSTom St Denis #define DC_HPD5_INT_CONTROL__DC_HPD5_RX_INT_EN__SHIFT 0x00000018 4067de2bdb3dSTom St Denis #define DC_HPD5_INT_STATUS__DC_HPD5_INT_STATUS_MASK 0x00000001L 4068de2bdb3dSTom St Denis #define DC_HPD5_INT_STATUS__DC_HPD5_INT_STATUS__SHIFT 0x00000000 4069de2bdb3dSTom St Denis #define DC_HPD5_INT_STATUS__DC_HPD5_RX_INT_STATUS_MASK 0x00000100L 4070de2bdb3dSTom St Denis #define DC_HPD5_INT_STATUS__DC_HPD5_RX_INT_STATUS__SHIFT 0x00000008 4071de2bdb3dSTom St Denis #define DC_HPD5_INT_STATUS__DC_HPD5_SENSE_DELAYED_MASK 0x00000010L 4072de2bdb3dSTom St Denis #define DC_HPD5_INT_STATUS__DC_HPD5_SENSE_DELAYED__SHIFT 0x00000004 4073de2bdb3dSTom St Denis #define DC_HPD5_INT_STATUS__DC_HPD5_SENSE_MASK 0x00000002L 4074de2bdb3dSTom St Denis #define DC_HPD5_INT_STATUS__DC_HPD5_SENSE__SHIFT 0x00000001 4075de2bdb3dSTom St Denis #define DC_HPD5_INT_STATUS__DC_HPD5_TOGGLE_FILT_CON_TIMER_VAL_MASK 0x000ff000L 4076de2bdb3dSTom St Denis #define DC_HPD5_INT_STATUS__DC_HPD5_TOGGLE_FILT_CON_TIMER_VAL__SHIFT 0x0000000c 4077de2bdb3dSTom St Denis #define DC_HPD5_INT_STATUS__DC_HPD5_TOGGLE_FILT_DISCON_TIMER_VAL_MASK 0xff000000L 4078de2bdb3dSTom St Denis #define DC_HPD5_INT_STATUS__DC_HPD5_TOGGLE_FILT_DISCON_TIMER_VAL__SHIFT 0x00000018 4079de2bdb3dSTom St Denis #define DC_HPD5_TOGGLE_FILT_CNTL__DC_HPD5_CONNECT_INT_DELAY_MASK 0x000000ffL 4080de2bdb3dSTom St Denis #define DC_HPD5_TOGGLE_FILT_CNTL__DC_HPD5_CONNECT_INT_DELAY__SHIFT 0x00000000 4081de2bdb3dSTom St Denis #define DC_HPD5_TOGGLE_FILT_CNTL__DC_HPD5_DISCONNECT_INT_DELAY_MASK 0x0ff00000L 4082de2bdb3dSTom St Denis #define DC_HPD5_TOGGLE_FILT_CNTL__DC_HPD5_DISCONNECT_INT_DELAY__SHIFT 0x00000014 4083de2bdb3dSTom St Denis #define DC_HPD6_CONTROL__DC_HPD6_CONNECTION_TIMER_MASK 0x00001fffL 4084de2bdb3dSTom St Denis #define DC_HPD6_CONTROL__DC_HPD6_CONNECTION_TIMER__SHIFT 0x00000000 4085de2bdb3dSTom St Denis #define DC_HPD6_CONTROL__DC_HPD6_EN_MASK 0x10000000L 4086de2bdb3dSTom St Denis #define DC_HPD6_CONTROL__DC_HPD6_EN__SHIFT 0x0000001c 4087de2bdb3dSTom St Denis #define DC_HPD6_CONTROL__DC_HPD6_RX_INT_TIMER_MASK 0x03ff0000L 4088de2bdb3dSTom St Denis #define DC_HPD6_CONTROL__DC_HPD6_RX_INT_TIMER__SHIFT 0x00000010 4089de2bdb3dSTom St Denis #define DC_HPD6_FAST_TRAIN_CNTL__DC_HPD6_CONNECT_AUX_TX_DELAY_MASK 0x000000ffL 4090de2bdb3dSTom St Denis #define DC_HPD6_FAST_TRAIN_CNTL__DC_HPD6_CONNECT_AUX_TX_DELAY__SHIFT 0x00000000 4091de2bdb3dSTom St Denis #define DC_HPD6_FAST_TRAIN_CNTL__DC_HPD6_CONNECT_AUX_TX_EN_MASK 0x01000000L 4092de2bdb3dSTom St Denis #define DC_HPD6_FAST_TRAIN_CNTL__DC_HPD6_CONNECT_AUX_TX_EN__SHIFT 0x00000018 4093de2bdb3dSTom St Denis #define DC_HPD6_FAST_TRAIN_CNTL__DC_HPD6_CONNECT_FAST_TRAIN_DELAY_MASK 0x000ff000L 4094de2bdb3dSTom St Denis #define DC_HPD6_FAST_TRAIN_CNTL__DC_HPD6_CONNECT_FAST_TRAIN_DELAY__SHIFT 0x0000000c 4095de2bdb3dSTom St Denis #define DC_HPD6_FAST_TRAIN_CNTL__DC_HPD6_CONNECT_FAST_TRAIN_EN_MASK 0x10000000L 4096de2bdb3dSTom St Denis #define DC_HPD6_FAST_TRAIN_CNTL__DC_HPD6_CONNECT_FAST_TRAIN_EN__SHIFT 0x0000001c 4097de2bdb3dSTom St Denis #define DC_HPD6_INT_CONTROL__DC_HPD6_INT_ACK_MASK 0x00000001L 4098de2bdb3dSTom St Denis #define DC_HPD6_INT_CONTROL__DC_HPD6_INT_ACK__SHIFT 0x00000000 4099de2bdb3dSTom St Denis #define DC_HPD6_INT_CONTROL__DC_HPD6_INT_EN_MASK 0x00010000L 4100de2bdb3dSTom St Denis #define DC_HPD6_INT_CONTROL__DC_HPD6_INT_EN__SHIFT 0x00000010 4101de2bdb3dSTom St Denis #define DC_HPD6_INT_CONTROL__DC_HPD6_INT_POLARITY_MASK 0x00000100L 4102de2bdb3dSTom St Denis #define DC_HPD6_INT_CONTROL__DC_HPD6_INT_POLARITY__SHIFT 0x00000008 4103de2bdb3dSTom St Denis #define DC_HPD6_INT_CONTROL__DC_HPD6_RX_INT_ACK_MASK 0x00100000L 4104de2bdb3dSTom St Denis #define DC_HPD6_INT_CONTROL__DC_HPD6_RX_INT_ACK__SHIFT 0x00000014 4105de2bdb3dSTom St Denis #define DC_HPD6_INT_CONTROL__DC_HPD6_RX_INT_EN_MASK 0x01000000L 4106de2bdb3dSTom St Denis #define DC_HPD6_INT_CONTROL__DC_HPD6_RX_INT_EN__SHIFT 0x00000018 4107de2bdb3dSTom St Denis #define DC_HPD6_INT_STATUS__DC_HPD6_INT_STATUS_MASK 0x00000001L 4108de2bdb3dSTom St Denis #define DC_HPD6_INT_STATUS__DC_HPD6_INT_STATUS__SHIFT 0x00000000 4109de2bdb3dSTom St Denis #define DC_HPD6_INT_STATUS__DC_HPD6_RX_INT_STATUS_MASK 0x00000100L 4110de2bdb3dSTom St Denis #define DC_HPD6_INT_STATUS__DC_HPD6_RX_INT_STATUS__SHIFT 0x00000008 4111de2bdb3dSTom St Denis #define DC_HPD6_INT_STATUS__DC_HPD6_SENSE_DELAYED_MASK 0x00000010L 4112de2bdb3dSTom St Denis #define DC_HPD6_INT_STATUS__DC_HPD6_SENSE_DELAYED__SHIFT 0x00000004 4113de2bdb3dSTom St Denis #define DC_HPD6_INT_STATUS__DC_HPD6_SENSE_MASK 0x00000002L 4114de2bdb3dSTom St Denis #define DC_HPD6_INT_STATUS__DC_HPD6_SENSE__SHIFT 0x00000001 4115de2bdb3dSTom St Denis #define DC_HPD6_INT_STATUS__DC_HPD6_TOGGLE_FILT_CON_TIMER_VAL_MASK 0x000ff000L 4116de2bdb3dSTom St Denis #define DC_HPD6_INT_STATUS__DC_HPD6_TOGGLE_FILT_CON_TIMER_VAL__SHIFT 0x0000000c 4117de2bdb3dSTom St Denis #define DC_HPD6_INT_STATUS__DC_HPD6_TOGGLE_FILT_DISCON_TIMER_VAL_MASK 0xff000000L 4118de2bdb3dSTom St Denis #define DC_HPD6_INT_STATUS__DC_HPD6_TOGGLE_FILT_DISCON_TIMER_VAL__SHIFT 0x00000018 4119de2bdb3dSTom St Denis #define DC_HPD6_TOGGLE_FILT_CNTL__DC_HPD6_CONNECT_INT_DELAY_MASK 0x000000ffL 4120de2bdb3dSTom St Denis #define DC_HPD6_TOGGLE_FILT_CNTL__DC_HPD6_CONNECT_INT_DELAY__SHIFT 0x00000000 4121de2bdb3dSTom St Denis #define DC_HPD6_TOGGLE_FILT_CNTL__DC_HPD6_DISCONNECT_INT_DELAY_MASK 0x0ff00000L 4122de2bdb3dSTom St Denis #define DC_HPD6_TOGGLE_FILT_CNTL__DC_HPD6_DISCONNECT_INT_DELAY__SHIFT 0x00000014 4123de2bdb3dSTom St Denis #define DC_I2C_ARBITRATION__DC_I2C_ABORT_HW_XFER_MASK 0x00000100L 4124de2bdb3dSTom St Denis #define DC_I2C_ARBITRATION__DC_I2C_ABORT_HW_XFER__SHIFT 0x00000008 4125de2bdb3dSTom St Denis #define DC_I2C_ARBITRATION__DC_I2C_ABORT_SW_XFER_MASK 0x00001000L 4126de2bdb3dSTom St Denis #define DC_I2C_ARBITRATION__DC_I2C_ABORT_SW_XFER__SHIFT 0x0000000c 4127de2bdb3dSTom St Denis #define DC_I2C_ARBITRATION__DC_I2C_DMCU_DONE_USING_I2C_REG_MASK 0x02000000L 4128de2bdb3dSTom St Denis #define DC_I2C_ARBITRATION__DC_I2C_DMCU_DONE_USING_I2C_REG__SHIFT 0x00000019 4129de2bdb3dSTom St Denis #define DC_I2C_ARBITRATION__DC_I2C_DMCU_USE_I2C_REG_REQ_MASK 0x01000000L 4130de2bdb3dSTom St Denis #define DC_I2C_ARBITRATION__DC_I2C_DMCU_USE_I2C_REG_REQ__SHIFT 0x00000018 4131de2bdb3dSTom St Denis #define DC_I2C_ARBITRATION__DC_I2C_NO_QUEUED_SW_GO_MASK 0x00000010L 4132de2bdb3dSTom St Denis #define DC_I2C_ARBITRATION__DC_I2C_NO_QUEUED_SW_GO__SHIFT 0x00000004 4133de2bdb3dSTom St Denis #define DC_I2C_ARBITRATION__DC_I2C_REG_RW_CNTL_STATUS_MASK 0x0000000cL 4134de2bdb3dSTom St Denis #define DC_I2C_ARBITRATION__DC_I2C_REG_RW_CNTL_STATUS__SHIFT 0x00000002 4135de2bdb3dSTom St Denis #define DC_I2C_ARBITRATION__DC_I2C_SW_DONE_USING_I2C_REG_MASK 0x00200000L 4136de2bdb3dSTom St Denis #define DC_I2C_ARBITRATION__DC_I2C_SW_DONE_USING_I2C_REG__SHIFT 0x00000015 4137de2bdb3dSTom St Denis #define DC_I2C_ARBITRATION__DC_I2C_SW_PRIORITY_MASK 0x00000003L 4138de2bdb3dSTom St Denis #define DC_I2C_ARBITRATION__DC_I2C_SW_PRIORITY__SHIFT 0x00000000 4139de2bdb3dSTom St Denis #define DC_I2C_ARBITRATION__DC_I2C_SW_USE_I2C_REG_REQ_MASK 0x00100000L 4140de2bdb3dSTom St Denis #define DC_I2C_ARBITRATION__DC_I2C_SW_USE_I2C_REG_REQ__SHIFT 0x00000014 4141de2bdb3dSTom St Denis #define DC_I2C_CONTROL__DC_I2C_DBG_REF_SEL_MASK 0x80000000L 4142de2bdb3dSTom St Denis #define DC_I2C_CONTROL__DC_I2C_DBG_REF_SEL__SHIFT 0x0000001f 4143de2bdb3dSTom St Denis #define DC_I2C_CONTROL__DC_I2C_DDC_SELECT_MASK 0x00000700L 4144de2bdb3dSTom St Denis #define DC_I2C_CONTROL__DC_I2C_DDC_SELECT__SHIFT 0x00000008 4145de2bdb3dSTom St Denis #define DC_I2C_CONTROL__DC_I2C_GO_MASK 0x00000001L 4146de2bdb3dSTom St Denis #define DC_I2C_CONTROL__DC_I2C_GO__SHIFT 0x00000000 4147de2bdb3dSTom St Denis #define DC_I2C_CONTROL__DC_I2C_SEND_RESET_MASK 0x00000004L 4148de2bdb3dSTom St Denis #define DC_I2C_CONTROL__DC_I2C_SEND_RESET__SHIFT 0x00000002 4149de2bdb3dSTom St Denis #define DC_I2C_CONTROL__DC_I2C_SOFT_RESET_MASK 0x00000002L 4150de2bdb3dSTom St Denis #define DC_I2C_CONTROL__DC_I2C_SOFT_RESET__SHIFT 0x00000001 4151de2bdb3dSTom St Denis #define DC_I2C_CONTROL__DC_I2C_SW_STATUS_RESET_MASK 0x00000008L 4152de2bdb3dSTom St Denis #define DC_I2C_CONTROL__DC_I2C_SW_STATUS_RESET__SHIFT 0x00000003 4153de2bdb3dSTom St Denis #define DC_I2C_CONTROL__DC_I2C_TRANSACTION_COUNT_MASK 0x00300000L 4154de2bdb3dSTom St Denis #define DC_I2C_CONTROL__DC_I2C_TRANSACTION_COUNT__SHIFT 0x00000014 4155de2bdb3dSTom St Denis #define DC_I2C_DATA__DC_I2C_DATA_MASK 0x0000ff00L 4156de2bdb3dSTom St Denis #define DC_I2C_DATA__DC_I2C_DATA_RW_MASK 0x00000001L 4157de2bdb3dSTom St Denis #define DC_I2C_DATA__DC_I2C_DATA_RW__SHIFT 0x00000000 4158de2bdb3dSTom St Denis #define DC_I2C_DATA__DC_I2C_DATA__SHIFT 0x00000008 4159de2bdb3dSTom St Denis #define DC_I2C_DATA__DC_I2C_INDEX_MASK 0x00ff0000L 4160de2bdb3dSTom St Denis #define DC_I2C_DATA__DC_I2C_INDEX__SHIFT 0x00000010 4161de2bdb3dSTom St Denis #define DC_I2C_DATA__DC_I2C_INDEX_WRITE_MASK 0x80000000L 4162de2bdb3dSTom St Denis #define DC_I2C_DATA__DC_I2C_INDEX_WRITE__SHIFT 0x0000001f 4163de2bdb3dSTom St Denis #define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_EDID_DETECT_NUM_VALID_TRIES_MASK 0x0f000000L 4164de2bdb3dSTom St Denis #define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_EDID_DETECT_NUM_VALID_TRIES__SHIFT 0x00000018 4165de2bdb3dSTom St Denis #define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_EDID_DETECT_STATE_MASK 0x70000000L 4166de2bdb3dSTom St Denis #define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_EDID_DETECT_STATE__SHIFT 0x0000001c 4167de2bdb3dSTom St Denis #define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_EDID_DETECT_STATUS_MASK 0x00100000L 4168de2bdb3dSTom St Denis #define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_EDID_DETECT_STATUS__SHIFT 0x00000014 4169de2bdb3dSTom St Denis #define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_DONE_MASK 0x00000008L 4170de2bdb3dSTom St Denis #define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_DONE__SHIFT 0x00000003 4171de2bdb3dSTom St Denis #define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_REQ_MASK 0x00010000L 4172de2bdb3dSTom St Denis #define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_REQ__SHIFT 0x00000010 4173de2bdb3dSTom St Denis #define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_STATUS_MASK 0x00000003L 4174de2bdb3dSTom St Denis #define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_STATUS__SHIFT 0x00000000 4175de2bdb3dSTom St Denis #define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_URG_MASK 0x00020000L 4176de2bdb3dSTom St Denis #define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_URG__SHIFT 0x00000011 4177de2bdb3dSTom St Denis #define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_CLK_DRIVE_EN_MASK 0x00000080L 4178de2bdb3dSTom St Denis #define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_CLK_DRIVE_EN__SHIFT 0x00000007 4179de2bdb3dSTom St Denis #define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_DATA_DRIVE_EN_MASK 0x00000001L 4180de2bdb3dSTom St Denis #define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_DATA_DRIVE_EN__SHIFT 0x00000000 4181de2bdb3dSTom St Denis #define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_DATA_DRIVE_SEL_MASK 0x00000002L 4182de2bdb3dSTom St Denis #define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_DATA_DRIVE_SEL__SHIFT 0x00000001 4183de2bdb3dSTom St Denis #define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_EDID_DETECT_ENABLE_MASK 0x00000010L 4184de2bdb3dSTom St Denis #define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_EDID_DETECT_ENABLE__SHIFT 0x00000004 4185de2bdb3dSTom St Denis #define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_EDID_DETECT_MODE_MASK 0x00000020L 4186de2bdb3dSTom St Denis #define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_EDID_DETECT_MODE__SHIFT 0x00000005 4187de2bdb3dSTom St Denis #define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_ENABLE_MASK 0x00000040L 4188de2bdb3dSTom St Denis #define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_ENABLE__SHIFT 0x00000006 4189de2bdb3dSTom St Denis #define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_INTRA_BYTE_DELAY_MASK 0x0000ff00L 4190de2bdb3dSTom St Denis #define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_INTRA_BYTE_DELAY__SHIFT 0x00000008 4191de2bdb3dSTom St Denis #define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_INTRA_TRANSACTION_DELAY_MASK 0x00ff0000L 4192de2bdb3dSTom St Denis #define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_INTRA_TRANSACTION_DELAY__SHIFT 0x00000010 4193de2bdb3dSTom St Denis #define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_TIME_LIMIT_MASK 0xff000000L 4194de2bdb3dSTom St Denis #define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_TIME_LIMIT__SHIFT 0x00000018 4195de2bdb3dSTom St Denis #define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_DISABLE_FILTER_DURING_STALL_MASK 0x00000010L 4196de2bdb3dSTom St Denis #define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_DISABLE_FILTER_DURING_STALL__SHIFT 0x00000004 4197de2bdb3dSTom St Denis #define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_PRESCALE_MASK 0xffff0000L 4198de2bdb3dSTom St Denis #define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_PRESCALE__SHIFT 0x00000010 4199de2bdb3dSTom St Denis #define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_THRESHOLD_MASK 0x00000003L 4200de2bdb3dSTom St Denis #define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_THRESHOLD__SHIFT 0x00000000 4201de2bdb3dSTom St Denis #define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_EDID_DETECT_NUM_VALID_TRIES_MASK 0x0f000000L 4202de2bdb3dSTom St Denis #define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_EDID_DETECT_NUM_VALID_TRIES__SHIFT 0x00000018 4203de2bdb3dSTom St Denis #define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_EDID_DETECT_STATE_MASK 0x70000000L 4204de2bdb3dSTom St Denis #define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_EDID_DETECT_STATE__SHIFT 0x0000001c 4205de2bdb3dSTom St Denis #define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_EDID_DETECT_STATUS_MASK 0x00100000L 4206de2bdb3dSTom St Denis #define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_EDID_DETECT_STATUS__SHIFT 0x00000014 4207de2bdb3dSTom St Denis #define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_DONE_MASK 0x00000008L 4208de2bdb3dSTom St Denis #define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_DONE__SHIFT 0x00000003 4209de2bdb3dSTom St Denis #define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_REQ_MASK 0x00010000L 4210de2bdb3dSTom St Denis #define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_REQ__SHIFT 0x00000010 4211de2bdb3dSTom St Denis #define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_STATUS_MASK 0x00000003L 4212de2bdb3dSTom St Denis #define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_STATUS__SHIFT 0x00000000 4213de2bdb3dSTom St Denis #define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_URG_MASK 0x00020000L 4214de2bdb3dSTom St Denis #define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_URG__SHIFT 0x00000011 4215de2bdb3dSTom St Denis #define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_CLK_DRIVE_EN_MASK 0x00000080L 4216de2bdb3dSTom St Denis #define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_CLK_DRIVE_EN__SHIFT 0x00000007 4217de2bdb3dSTom St Denis #define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_DATA_DRIVE_EN_MASK 0x00000001L 4218de2bdb3dSTom St Denis #define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_DATA_DRIVE_EN__SHIFT 0x00000000 4219de2bdb3dSTom St Denis #define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_DATA_DRIVE_SEL_MASK 0x00000002L 4220de2bdb3dSTom St Denis #define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_DATA_DRIVE_SEL__SHIFT 0x00000001 4221de2bdb3dSTom St Denis #define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_EDID_DETECT_ENABLE_MASK 0x00000010L 4222de2bdb3dSTom St Denis #define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_EDID_DETECT_ENABLE__SHIFT 0x00000004 4223de2bdb3dSTom St Denis #define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_EDID_DETECT_MODE_MASK 0x00000020L 4224de2bdb3dSTom St Denis #define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_EDID_DETECT_MODE__SHIFT 0x00000005 4225de2bdb3dSTom St Denis #define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_ENABLE_MASK 0x00000040L 4226de2bdb3dSTom St Denis #define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_ENABLE__SHIFT 0x00000006 4227de2bdb3dSTom St Denis #define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_INTRA_BYTE_DELAY_MASK 0x0000ff00L 4228de2bdb3dSTom St Denis #define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_INTRA_BYTE_DELAY__SHIFT 0x00000008 4229de2bdb3dSTom St Denis #define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_INTRA_TRANSACTION_DELAY_MASK 0x00ff0000L 4230de2bdb3dSTom St Denis #define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_INTRA_TRANSACTION_DELAY__SHIFT 0x00000010 4231de2bdb3dSTom St Denis #define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_TIME_LIMIT_MASK 0xff000000L 4232de2bdb3dSTom St Denis #define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_TIME_LIMIT__SHIFT 0x00000018 4233de2bdb3dSTom St Denis #define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_DISABLE_FILTER_DURING_STALL_MASK 0x00000010L 4234de2bdb3dSTom St Denis #define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_DISABLE_FILTER_DURING_STALL__SHIFT 0x00000004 4235de2bdb3dSTom St Denis #define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_PRESCALE_MASK 0xffff0000L 4236de2bdb3dSTom St Denis #define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_PRESCALE__SHIFT 0x00000010 4237de2bdb3dSTom St Denis #define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_THRESHOLD_MASK 0x00000003L 4238de2bdb3dSTom St Denis #define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_THRESHOLD__SHIFT 0x00000000 4239de2bdb3dSTom St Denis #define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_EDID_DETECT_NUM_VALID_TRIES_MASK 0x0f000000L 4240de2bdb3dSTom St Denis #define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_EDID_DETECT_NUM_VALID_TRIES__SHIFT 0x00000018 4241de2bdb3dSTom St Denis #define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_EDID_DETECT_STATE_MASK 0x70000000L 4242de2bdb3dSTom St Denis #define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_EDID_DETECT_STATE__SHIFT 0x0000001c 4243de2bdb3dSTom St Denis #define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_EDID_DETECT_STATUS_MASK 0x00100000L 4244de2bdb3dSTom St Denis #define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_EDID_DETECT_STATUS__SHIFT 0x00000014 4245de2bdb3dSTom St Denis #define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_DONE_MASK 0x00000008L 4246de2bdb3dSTom St Denis #define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_DONE__SHIFT 0x00000003 4247de2bdb3dSTom St Denis #define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_REQ_MASK 0x00010000L 4248de2bdb3dSTom St Denis #define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_REQ__SHIFT 0x00000010 4249de2bdb3dSTom St Denis #define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_STATUS_MASK 0x00000003L 4250de2bdb3dSTom St Denis #define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_STATUS__SHIFT 0x00000000 4251de2bdb3dSTom St Denis #define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_URG_MASK 0x00020000L 4252de2bdb3dSTom St Denis #define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_URG__SHIFT 0x00000011 4253de2bdb3dSTom St Denis #define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_CLK_DRIVE_EN_MASK 0x00000080L 4254de2bdb3dSTom St Denis #define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_CLK_DRIVE_EN__SHIFT 0x00000007 4255de2bdb3dSTom St Denis #define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_DATA_DRIVE_EN_MASK 0x00000001L 4256de2bdb3dSTom St Denis #define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_DATA_DRIVE_EN__SHIFT 0x00000000 4257de2bdb3dSTom St Denis #define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_DATA_DRIVE_SEL_MASK 0x00000002L 4258de2bdb3dSTom St Denis #define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_DATA_DRIVE_SEL__SHIFT 0x00000001 4259de2bdb3dSTom St Denis #define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_EDID_DETECT_ENABLE_MASK 0x00000010L 4260de2bdb3dSTom St Denis #define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_EDID_DETECT_ENABLE__SHIFT 0x00000004 4261de2bdb3dSTom St Denis #define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_EDID_DETECT_MODE_MASK 0x00000020L 4262de2bdb3dSTom St Denis #define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_EDID_DETECT_MODE__SHIFT 0x00000005 4263de2bdb3dSTom St Denis #define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_ENABLE_MASK 0x00000040L 4264de2bdb3dSTom St Denis #define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_ENABLE__SHIFT 0x00000006 4265de2bdb3dSTom St Denis #define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_INTRA_BYTE_DELAY_MASK 0x0000ff00L 4266de2bdb3dSTom St Denis #define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_INTRA_BYTE_DELAY__SHIFT 0x00000008 4267de2bdb3dSTom St Denis #define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_INTRA_TRANSACTION_DELAY_MASK 0x00ff0000L 4268de2bdb3dSTom St Denis #define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_INTRA_TRANSACTION_DELAY__SHIFT 0x00000010 4269de2bdb3dSTom St Denis #define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_TIME_LIMIT_MASK 0xff000000L 4270de2bdb3dSTom St Denis #define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_TIME_LIMIT__SHIFT 0x00000018 4271de2bdb3dSTom St Denis #define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_DISABLE_FILTER_DURING_STALL_MASK 0x00000010L 4272de2bdb3dSTom St Denis #define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_DISABLE_FILTER_DURING_STALL__SHIFT 0x00000004 4273de2bdb3dSTom St Denis #define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_PRESCALE_MASK 0xffff0000L 4274de2bdb3dSTom St Denis #define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_PRESCALE__SHIFT 0x00000010 4275de2bdb3dSTom St Denis #define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_THRESHOLD_MASK 0x00000003L 4276de2bdb3dSTom St Denis #define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_THRESHOLD__SHIFT 0x00000000 4277de2bdb3dSTom St Denis #define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_EDID_DETECT_NUM_VALID_TRIES_MASK 0x0f000000L 4278de2bdb3dSTom St Denis #define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_EDID_DETECT_NUM_VALID_TRIES__SHIFT 0x00000018 4279de2bdb3dSTom St Denis #define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_EDID_DETECT_STATE_MASK 0x70000000L 4280de2bdb3dSTom St Denis #define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_EDID_DETECT_STATE__SHIFT 0x0000001c 4281de2bdb3dSTom St Denis #define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_EDID_DETECT_STATUS_MASK 0x00100000L 4282de2bdb3dSTom St Denis #define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_EDID_DETECT_STATUS__SHIFT 0x00000014 4283de2bdb3dSTom St Denis #define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_DONE_MASK 0x00000008L 4284de2bdb3dSTom St Denis #define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_DONE__SHIFT 0x00000003 4285de2bdb3dSTom St Denis #define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_REQ_MASK 0x00010000L 4286de2bdb3dSTom St Denis #define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_REQ__SHIFT 0x00000010 4287de2bdb3dSTom St Denis #define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_STATUS_MASK 0x00000003L 4288de2bdb3dSTom St Denis #define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_STATUS__SHIFT 0x00000000 4289de2bdb3dSTom St Denis #define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_URG_MASK 0x00020000L 4290de2bdb3dSTom St Denis #define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_URG__SHIFT 0x00000011 4291de2bdb3dSTom St Denis #define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_CLK_DRIVE_EN_MASK 0x00000080L 4292de2bdb3dSTom St Denis #define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_CLK_DRIVE_EN__SHIFT 0x00000007 4293de2bdb3dSTom St Denis #define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_DATA_DRIVE_EN_MASK 0x00000001L 4294de2bdb3dSTom St Denis #define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_DATA_DRIVE_EN__SHIFT 0x00000000 4295de2bdb3dSTom St Denis #define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_DATA_DRIVE_SEL_MASK 0x00000002L 4296de2bdb3dSTom St Denis #define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_DATA_DRIVE_SEL__SHIFT 0x00000001 4297de2bdb3dSTom St Denis #define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_EDID_DETECT_ENABLE_MASK 0x00000010L 4298de2bdb3dSTom St Denis #define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_EDID_DETECT_ENABLE__SHIFT 0x00000004 4299de2bdb3dSTom St Denis #define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_EDID_DETECT_MODE_MASK 0x00000020L 4300de2bdb3dSTom St Denis #define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_EDID_DETECT_MODE__SHIFT 0x00000005 4301de2bdb3dSTom St Denis #define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_ENABLE_MASK 0x00000040L 4302de2bdb3dSTom St Denis #define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_ENABLE__SHIFT 0x00000006 4303de2bdb3dSTom St Denis #define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_INTRA_BYTE_DELAY_MASK 0x0000ff00L 4304de2bdb3dSTom St Denis #define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_INTRA_BYTE_DELAY__SHIFT 0x00000008 4305de2bdb3dSTom St Denis #define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_INTRA_TRANSACTION_DELAY_MASK 0x00ff0000L 4306de2bdb3dSTom St Denis #define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_INTRA_TRANSACTION_DELAY__SHIFT 0x00000010 4307de2bdb3dSTom St Denis #define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_TIME_LIMIT_MASK 0xff000000L 4308de2bdb3dSTom St Denis #define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_TIME_LIMIT__SHIFT 0x00000018 4309de2bdb3dSTom St Denis #define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_DISABLE_FILTER_DURING_STALL_MASK 0x00000010L 4310de2bdb3dSTom St Denis #define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_DISABLE_FILTER_DURING_STALL__SHIFT 0x00000004 4311de2bdb3dSTom St Denis #define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_PRESCALE_MASK 0xffff0000L 4312de2bdb3dSTom St Denis #define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_PRESCALE__SHIFT 0x00000010 4313de2bdb3dSTom St Denis #define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_THRESHOLD_MASK 0x00000003L 4314de2bdb3dSTom St Denis #define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_THRESHOLD__SHIFT 0x00000000 4315de2bdb3dSTom St Denis #define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_EDID_DETECT_NUM_VALID_TRIES_MASK 0x0f000000L 4316de2bdb3dSTom St Denis #define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_EDID_DETECT_NUM_VALID_TRIES__SHIFT 0x00000018 4317de2bdb3dSTom St Denis #define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_EDID_DETECT_STATE_MASK 0x70000000L 4318de2bdb3dSTom St Denis #define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_EDID_DETECT_STATE__SHIFT 0x0000001c 4319de2bdb3dSTom St Denis #define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_EDID_DETECT_STATUS_MASK 0x00100000L 4320de2bdb3dSTom St Denis #define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_EDID_DETECT_STATUS__SHIFT 0x00000014 4321de2bdb3dSTom St Denis #define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_DONE_MASK 0x00000008L 4322de2bdb3dSTom St Denis #define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_DONE__SHIFT 0x00000003 4323de2bdb3dSTom St Denis #define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_REQ_MASK 0x00010000L 4324de2bdb3dSTom St Denis #define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_REQ__SHIFT 0x00000010 4325de2bdb3dSTom St Denis #define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_STATUS_MASK 0x00000003L 4326de2bdb3dSTom St Denis #define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_STATUS__SHIFT 0x00000000 4327de2bdb3dSTom St Denis #define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_URG_MASK 0x00020000L 4328de2bdb3dSTom St Denis #define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_URG__SHIFT 0x00000011 4329de2bdb3dSTom St Denis #define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_CLK_DRIVE_EN_MASK 0x00000080L 4330de2bdb3dSTom St Denis #define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_CLK_DRIVE_EN__SHIFT 0x00000007 4331de2bdb3dSTom St Denis #define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_DATA_DRIVE_EN_MASK 0x00000001L 4332de2bdb3dSTom St Denis #define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_DATA_DRIVE_EN__SHIFT 0x00000000 4333de2bdb3dSTom St Denis #define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_DATA_DRIVE_SEL_MASK 0x00000002L 4334de2bdb3dSTom St Denis #define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_DATA_DRIVE_SEL__SHIFT 0x00000001 4335de2bdb3dSTom St Denis #define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_EDID_DETECT_ENABLE_MASK 0x00000010L 4336de2bdb3dSTom St Denis #define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_EDID_DETECT_ENABLE__SHIFT 0x00000004 4337de2bdb3dSTom St Denis #define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_EDID_DETECT_MODE_MASK 0x00000020L 4338de2bdb3dSTom St Denis #define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_EDID_DETECT_MODE__SHIFT 0x00000005 4339de2bdb3dSTom St Denis #define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_ENABLE_MASK 0x00000040L 4340de2bdb3dSTom St Denis #define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_ENABLE__SHIFT 0x00000006 4341de2bdb3dSTom St Denis #define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_INTRA_BYTE_DELAY_MASK 0x0000ff00L 4342de2bdb3dSTom St Denis #define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_INTRA_BYTE_DELAY__SHIFT 0x00000008 4343de2bdb3dSTom St Denis #define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_INTRA_TRANSACTION_DELAY_MASK 0x00ff0000L 4344de2bdb3dSTom St Denis #define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_INTRA_TRANSACTION_DELAY__SHIFT 0x00000010 4345de2bdb3dSTom St Denis #define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_TIME_LIMIT_MASK 0xff000000L 4346de2bdb3dSTom St Denis #define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_TIME_LIMIT__SHIFT 0x00000018 4347de2bdb3dSTom St Denis #define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_DISABLE_FILTER_DURING_STALL_MASK 0x00000010L 4348de2bdb3dSTom St Denis #define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_DISABLE_FILTER_DURING_STALL__SHIFT 0x00000004 4349de2bdb3dSTom St Denis #define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_PRESCALE_MASK 0xffff0000L 4350de2bdb3dSTom St Denis #define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_PRESCALE__SHIFT 0x00000010 4351de2bdb3dSTom St Denis #define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_THRESHOLD_MASK 0x00000003L 4352de2bdb3dSTom St Denis #define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_THRESHOLD__SHIFT 0x00000000 4353de2bdb3dSTom St Denis #define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_EDID_DETECT_NUM_VALID_TRIES_MASK 0x0f000000L 4354de2bdb3dSTom St Denis #define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_EDID_DETECT_NUM_VALID_TRIES__SHIFT 0x00000018 4355de2bdb3dSTom St Denis #define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_EDID_DETECT_STATE_MASK 0x70000000L 4356de2bdb3dSTom St Denis #define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_EDID_DETECT_STATE__SHIFT 0x0000001c 4357de2bdb3dSTom St Denis #define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_EDID_DETECT_STATUS_MASK 0x00100000L 4358de2bdb3dSTom St Denis #define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_EDID_DETECT_STATUS__SHIFT 0x00000014 4359de2bdb3dSTom St Denis #define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_HW_DONE_MASK 0x00000008L 4360de2bdb3dSTom St Denis #define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_HW_DONE__SHIFT 0x00000003 4361de2bdb3dSTom St Denis #define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_HW_REQ_MASK 0x00010000L 4362de2bdb3dSTom St Denis #define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_HW_REQ__SHIFT 0x00000010 4363de2bdb3dSTom St Denis #define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_HW_STATUS_MASK 0x00000003L 4364de2bdb3dSTom St Denis #define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_HW_STATUS__SHIFT 0x00000000 4365de2bdb3dSTom St Denis #define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_HW_URG_MASK 0x00020000L 4366de2bdb3dSTom St Denis #define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_HW_URG__SHIFT 0x00000011 4367de2bdb3dSTom St Denis #define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_CLK_DRIVE_EN_MASK 0x00000080L 4368de2bdb3dSTom St Denis #define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_CLK_DRIVE_EN__SHIFT 0x00000007 4369de2bdb3dSTom St Denis #define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_DATA_DRIVE_EN_MASK 0x00000001L 4370de2bdb3dSTom St Denis #define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_DATA_DRIVE_EN__SHIFT 0x00000000 4371de2bdb3dSTom St Denis #define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_DATA_DRIVE_SEL_MASK 0x00000002L 4372de2bdb3dSTom St Denis #define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_DATA_DRIVE_SEL__SHIFT 0x00000001 4373de2bdb3dSTom St Denis #define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_EDID_DETECT_ENABLE_MASK 0x00000010L 4374de2bdb3dSTom St Denis #define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_EDID_DETECT_ENABLE__SHIFT 0x00000004 4375de2bdb3dSTom St Denis #define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_EDID_DETECT_MODE_MASK 0x00000020L 4376de2bdb3dSTom St Denis #define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_EDID_DETECT_MODE__SHIFT 0x00000005 4377de2bdb3dSTom St Denis #define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_ENABLE_MASK 0x00000040L 4378de2bdb3dSTom St Denis #define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_ENABLE__SHIFT 0x00000006 4379de2bdb3dSTom St Denis #define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_INTRA_BYTE_DELAY_MASK 0x0000ff00L 4380de2bdb3dSTom St Denis #define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_INTRA_BYTE_DELAY__SHIFT 0x00000008 4381de2bdb3dSTom St Denis #define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_INTRA_TRANSACTION_DELAY_MASK 0x00ff0000L 4382de2bdb3dSTom St Denis #define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_INTRA_TRANSACTION_DELAY__SHIFT 0x00000010 4383de2bdb3dSTom St Denis #define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_TIME_LIMIT_MASK 0xff000000L 4384de2bdb3dSTom St Denis #define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_TIME_LIMIT__SHIFT 0x00000018 4385de2bdb3dSTom St Denis #define DC_I2C_DDC6_SPEED__DC_I2C_DDC6_DISABLE_FILTER_DURING_STALL_MASK 0x00000010L 4386de2bdb3dSTom St Denis #define DC_I2C_DDC6_SPEED__DC_I2C_DDC6_DISABLE_FILTER_DURING_STALL__SHIFT 0x00000004 4387de2bdb3dSTom St Denis #define DC_I2C_DDC6_SPEED__DC_I2C_DDC6_PRESCALE_MASK 0xffff0000L 4388de2bdb3dSTom St Denis #define DC_I2C_DDC6_SPEED__DC_I2C_DDC6_PRESCALE__SHIFT 0x00000010 4389de2bdb3dSTom St Denis #define DC_I2C_DDC6_SPEED__DC_I2C_DDC6_THRESHOLD_MASK 0x00000003L 4390de2bdb3dSTom St Denis #define DC_I2C_DDC6_SPEED__DC_I2C_DDC6_THRESHOLD__SHIFT 0x00000000 4391de2bdb3dSTom St Denis #define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_EDID_DETECT_NUM_VALID_TRIES_MASK 0x0f000000L 4392de2bdb3dSTom St Denis #define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_EDID_DETECT_NUM_VALID_TRIES__SHIFT 0x00000018 4393de2bdb3dSTom St Denis #define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_EDID_DETECT_STATE_MASK 0x70000000L 4394de2bdb3dSTom St Denis #define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_EDID_DETECT_STATE__SHIFT 0x0000001c 4395de2bdb3dSTom St Denis #define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_EDID_DETECT_STATUS_MASK 0x00100000L 4396de2bdb3dSTom St Denis #define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_EDID_DETECT_STATUS__SHIFT 0x00000014 4397de2bdb3dSTom St Denis #define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_HW_DONE_MASK 0x00000008L 4398de2bdb3dSTom St Denis #define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_HW_DONE__SHIFT 0x00000003 4399de2bdb3dSTom St Denis #define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_HW_REQ_MASK 0x00010000L 4400de2bdb3dSTom St Denis #define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_HW_REQ__SHIFT 0x00000010 4401de2bdb3dSTom St Denis #define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_HW_STATUS_MASK 0x00000003L 4402de2bdb3dSTom St Denis #define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_HW_STATUS__SHIFT 0x00000000 4403de2bdb3dSTom St Denis #define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_HW_URG_MASK 0x00020000L 4404de2bdb3dSTom St Denis #define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_HW_URG__SHIFT 0x00000011 4405de2bdb3dSTom St Denis #define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_CLK_DRIVE_EN_MASK 0x00000080L 4406de2bdb3dSTom St Denis #define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_CLK_DRIVE_EN__SHIFT 0x00000007 4407de2bdb3dSTom St Denis #define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_DATA_DRIVE_EN_MASK 0x00000001L 4408de2bdb3dSTom St Denis #define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_DATA_DRIVE_EN__SHIFT 0x00000000 4409de2bdb3dSTom St Denis #define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_DATA_DRIVE_SEL_MASK 0x00000002L 4410de2bdb3dSTom St Denis #define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_DATA_DRIVE_SEL__SHIFT 0x00000001 4411de2bdb3dSTom St Denis #define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_EDID_DETECT_ENABLE_MASK 0x00000010L 4412de2bdb3dSTom St Denis #define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_EDID_DETECT_ENABLE__SHIFT 0x00000004 4413de2bdb3dSTom St Denis #define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_EDID_DETECT_MODE_MASK 0x00000020L 4414de2bdb3dSTom St Denis #define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_EDID_DETECT_MODE__SHIFT 0x00000005 4415de2bdb3dSTom St Denis #define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_ENABLE_MASK 0x00000040L 4416de2bdb3dSTom St Denis #define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_ENABLE__SHIFT 0x00000006 4417de2bdb3dSTom St Denis #define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_INTRA_BYTE_DELAY_MASK 0x0000ff00L 4418de2bdb3dSTom St Denis #define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_INTRA_BYTE_DELAY__SHIFT 0x00000008 4419de2bdb3dSTom St Denis #define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_INTRA_TRANSACTION_DELAY_MASK 0x00ff0000L 4420de2bdb3dSTom St Denis #define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_INTRA_TRANSACTION_DELAY__SHIFT 0x00000010 4421de2bdb3dSTom St Denis #define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_TIME_LIMIT_MASK 0xff000000L 4422de2bdb3dSTom St Denis #define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_TIME_LIMIT__SHIFT 0x00000018 4423de2bdb3dSTom St Denis #define DC_I2C_DDCVGA_SPEED__DC_I2C_DDCVGA_DISABLE_FILTER_DURING_STALL_MASK 0x00000010L 4424de2bdb3dSTom St Denis #define DC_I2C_DDCVGA_SPEED__DC_I2C_DDCVGA_DISABLE_FILTER_DURING_STALL__SHIFT 0x00000004 4425de2bdb3dSTom St Denis #define DC_I2C_DDCVGA_SPEED__DC_I2C_DDCVGA_PRESCALE_MASK 0xffff0000L 4426de2bdb3dSTom St Denis #define DC_I2C_DDCVGA_SPEED__DC_I2C_DDCVGA_PRESCALE__SHIFT 0x00000010 4427de2bdb3dSTom St Denis #define DC_I2C_DDCVGA_SPEED__DC_I2C_DDCVGA_THRESHOLD_MASK 0x00000003L 4428de2bdb3dSTom St Denis #define DC_I2C_DDCVGA_SPEED__DC_I2C_DDCVGA_THRESHOLD__SHIFT 0x00000000 4429de2bdb3dSTom St Denis #define DC_I2C_EDID_DETECT_CTRL__DC_I2C_EDID_DETECT_NUM_TRIES_UNTIL_VALID_MASK 0x00f00000L 4430de2bdb3dSTom St Denis #define DC_I2C_EDID_DETECT_CTRL__DC_I2C_EDID_DETECT_NUM_TRIES_UNTIL_VALID__SHIFT 0x00000014 4431de2bdb3dSTom St Denis #define DC_I2C_EDID_DETECT_CTRL__DC_I2C_EDID_DETECT_SEND_RESET_MASK 0x10000000L 4432de2bdb3dSTom St Denis #define DC_I2C_EDID_DETECT_CTRL__DC_I2C_EDID_DETECT_SEND_RESET__SHIFT 0x0000001c 4433de2bdb3dSTom St Denis #define DC_I2C_EDID_DETECT_CTRL__DC_I2C_EDID_DETECT_WAIT_TIME_MASK 0x0000ffffL 4434de2bdb3dSTom St Denis #define DC_I2C_EDID_DETECT_CTRL__DC_I2C_EDID_DETECT_WAIT_TIME__SHIFT 0x00000000 4435de2bdb3dSTom St Denis #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_ACK_MASK 0x00000020L 4436de2bdb3dSTom St Denis #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_ACK__SHIFT 0x00000005 4437de2bdb3dSTom St Denis #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_INT_MASK 0x00000010L 4438de2bdb3dSTom St Denis #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_INT__SHIFT 0x00000004 4439de2bdb3dSTom St Denis #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_MASK_MASK 0x00000040L 4440de2bdb3dSTom St Denis #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_MASK__SHIFT 0x00000006 4441de2bdb3dSTom St Denis #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_ACK_MASK 0x00000200L 4442de2bdb3dSTom St Denis #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_ACK__SHIFT 0x00000009 4443de2bdb3dSTom St Denis #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_INT_MASK 0x00000100L 4444de2bdb3dSTom St Denis #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_INT__SHIFT 0x00000008 4445de2bdb3dSTom St Denis #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_MASK_MASK 0x00000400L 4446de2bdb3dSTom St Denis #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_MASK__SHIFT 0x0000000a 4447de2bdb3dSTom St Denis #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_ACK_MASK 0x00002000L 4448de2bdb3dSTom St Denis #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_ACK__SHIFT 0x0000000d 4449de2bdb3dSTom St Denis #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_INT_MASK 0x00001000L 4450de2bdb3dSTom St Denis #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_INT__SHIFT 0x0000000c 4451de2bdb3dSTom St Denis #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_MASK_MASK 0x00004000L 4452de2bdb3dSTom St Denis #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_MASK__SHIFT 0x0000000e 4453de2bdb3dSTom St Denis #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_ACK_MASK 0x00020000L 4454de2bdb3dSTom St Denis #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_ACK__SHIFT 0x00000011 4455de2bdb3dSTom St Denis #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_INT_MASK 0x00010000L 4456de2bdb3dSTom St Denis #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_INT__SHIFT 0x00000010 4457de2bdb3dSTom St Denis #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_MASK_MASK 0x00040000L 4458de2bdb3dSTom St Denis #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_MASK__SHIFT 0x00000012 4459de2bdb3dSTom St Denis #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_ACK_MASK 0x00200000L 4460de2bdb3dSTom St Denis #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_ACK__SHIFT 0x00000015 4461de2bdb3dSTom St Denis #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_INT_MASK 0x00100000L 4462de2bdb3dSTom St Denis #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_INT__SHIFT 0x00000014 4463de2bdb3dSTom St Denis #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_MASK_MASK 0x00400000L 4464de2bdb3dSTom St Denis #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_MASK__SHIFT 0x00000016 4465de2bdb3dSTom St Denis #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_ACK_MASK 0x02000000L 4466de2bdb3dSTom St Denis #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_ACK__SHIFT 0x00000019 4467de2bdb3dSTom St Denis #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_INT_MASK 0x01000000L 4468de2bdb3dSTom St Denis #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_INT__SHIFT 0x00000018 4469de2bdb3dSTom St Denis #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_MASK_MASK 0x04000000L 4470de2bdb3dSTom St Denis #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_MASK__SHIFT 0x0000001a 4471de2bdb3dSTom St Denis #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDCVGA_HW_DONE_ACK_MASK 0x10000000L 4472de2bdb3dSTom St Denis #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDCVGA_HW_DONE_ACK__SHIFT 0x0000001c 4473de2bdb3dSTom St Denis #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDCVGA_HW_DONE_INT_MASK 0x08000000L 4474de2bdb3dSTom St Denis #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDCVGA_HW_DONE_INT__SHIFT 0x0000001b 4475de2bdb3dSTom St Denis #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDCVGA_HW_DONE_MASK_MASK 0x20000000L 4476de2bdb3dSTom St Denis #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDCVGA_HW_DONE_MASK__SHIFT 0x0000001d 4477de2bdb3dSTom St Denis #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_ACK_MASK 0x00000002L 4478de2bdb3dSTom St Denis #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_ACK__SHIFT 0x00000001 4479de2bdb3dSTom St Denis #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_INT_MASK 0x00000001L 4480de2bdb3dSTom St Denis #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_INT__SHIFT 0x00000000 4481de2bdb3dSTom St Denis #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_MASK_MASK 0x00000004L 4482de2bdb3dSTom St Denis #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_MASK__SHIFT 0x00000002 4483de2bdb3dSTom St Denis #define DC_I2C_SW_STATUS__DC_I2C_SW_ABORTED_MASK 0x00000010L 4484de2bdb3dSTom St Denis #define DC_I2C_SW_STATUS__DC_I2C_SW_ABORTED__SHIFT 0x00000004 4485de2bdb3dSTom St Denis #define DC_I2C_SW_STATUS__DC_I2C_SW_BUFFER_OVERFLOW_MASK 0x00000080L 4486de2bdb3dSTom St Denis #define DC_I2C_SW_STATUS__DC_I2C_SW_BUFFER_OVERFLOW__SHIFT 0x00000007 4487de2bdb3dSTom St Denis #define DC_I2C_SW_STATUS__DC_I2C_SW_DONE_MASK 0x00000004L 4488de2bdb3dSTom St Denis #define DC_I2C_SW_STATUS__DC_I2C_SW_DONE__SHIFT 0x00000002 4489de2bdb3dSTom St Denis #define DC_I2C_SW_STATUS__DC_I2C_SW_INTERRUPTED_MASK 0x00000040L 4490de2bdb3dSTom St Denis #define DC_I2C_SW_STATUS__DC_I2C_SW_INTERRUPTED__SHIFT 0x00000006 4491de2bdb3dSTom St Denis #define DC_I2C_SW_STATUS__DC_I2C_SW_NACK0_MASK 0x00001000L 4492de2bdb3dSTom St Denis #define DC_I2C_SW_STATUS__DC_I2C_SW_NACK0__SHIFT 0x0000000c 4493de2bdb3dSTom St Denis #define DC_I2C_SW_STATUS__DC_I2C_SW_NACK1_MASK 0x00002000L 4494de2bdb3dSTom St Denis #define DC_I2C_SW_STATUS__DC_I2C_SW_NACK1__SHIFT 0x0000000d 4495de2bdb3dSTom St Denis #define DC_I2C_SW_STATUS__DC_I2C_SW_NACK2_MASK 0x00004000L 4496de2bdb3dSTom St Denis #define DC_I2C_SW_STATUS__DC_I2C_SW_NACK2__SHIFT 0x0000000e 4497de2bdb3dSTom St Denis #define DC_I2C_SW_STATUS__DC_I2C_SW_NACK3_MASK 0x00008000L 4498de2bdb3dSTom St Denis #define DC_I2C_SW_STATUS__DC_I2C_SW_NACK3__SHIFT 0x0000000f 4499de2bdb3dSTom St Denis #define DC_I2C_SW_STATUS__DC_I2C_SW_REQ_MASK 0x00040000L 4500de2bdb3dSTom St Denis #define DC_I2C_SW_STATUS__DC_I2C_SW_REQ__SHIFT 0x00000012 4501de2bdb3dSTom St Denis #define DC_I2C_SW_STATUS__DC_I2C_SW_STATUS_MASK 0x00000003L 4502de2bdb3dSTom St Denis #define DC_I2C_SW_STATUS__DC_I2C_SW_STATUS__SHIFT 0x00000000 4503de2bdb3dSTom St Denis #define DC_I2C_SW_STATUS__DC_I2C_SW_STOPPED_ON_NACK_MASK 0x00000100L 4504de2bdb3dSTom St Denis #define DC_I2C_SW_STATUS__DC_I2C_SW_STOPPED_ON_NACK__SHIFT 0x00000008 4505de2bdb3dSTom St Denis #define DC_I2C_SW_STATUS__DC_I2C_SW_TIMEOUT_MASK 0x00000020L 4506de2bdb3dSTom St Denis #define DC_I2C_SW_STATUS__DC_I2C_SW_TIMEOUT__SHIFT 0x00000005 4507de2bdb3dSTom St Denis #define DC_I2C_TRANSACTION0__DC_I2C_COUNT0_MASK 0x00ff0000L 4508de2bdb3dSTom St Denis #define DC_I2C_TRANSACTION0__DC_I2C_COUNT0__SHIFT 0x00000010 4509de2bdb3dSTom St Denis #define DC_I2C_TRANSACTION0__DC_I2C_RW0_MASK 0x00000001L 4510de2bdb3dSTom St Denis #define DC_I2C_TRANSACTION0__DC_I2C_RW0__SHIFT 0x00000000 4511de2bdb3dSTom St Denis #define DC_I2C_TRANSACTION0__DC_I2C_START0_MASK 0x00001000L 4512de2bdb3dSTom St Denis #define DC_I2C_TRANSACTION0__DC_I2C_START0__SHIFT 0x0000000c 4513de2bdb3dSTom St Denis #define DC_I2C_TRANSACTION0__DC_I2C_STOP0_MASK 0x00002000L 4514de2bdb3dSTom St Denis #define DC_I2C_TRANSACTION0__DC_I2C_STOP0__SHIFT 0x0000000d 4515de2bdb3dSTom St Denis #define DC_I2C_TRANSACTION0__DC_I2C_STOP_ON_NACK0_MASK 0x00000100L 4516de2bdb3dSTom St Denis #define DC_I2C_TRANSACTION0__DC_I2C_STOP_ON_NACK0__SHIFT 0x00000008 4517de2bdb3dSTom St Denis #define DC_I2C_TRANSACTION1__DC_I2C_COUNT1_MASK 0x00ff0000L 4518de2bdb3dSTom St Denis #define DC_I2C_TRANSACTION1__DC_I2C_COUNT1__SHIFT 0x00000010 4519de2bdb3dSTom St Denis #define DC_I2C_TRANSACTION1__DC_I2C_RW1_MASK 0x00000001L 4520de2bdb3dSTom St Denis #define DC_I2C_TRANSACTION1__DC_I2C_RW1__SHIFT 0x00000000 4521de2bdb3dSTom St Denis #define DC_I2C_TRANSACTION1__DC_I2C_START1_MASK 0x00001000L 4522de2bdb3dSTom St Denis #define DC_I2C_TRANSACTION1__DC_I2C_START1__SHIFT 0x0000000c 4523de2bdb3dSTom St Denis #define DC_I2C_TRANSACTION1__DC_I2C_STOP1_MASK 0x00002000L 4524de2bdb3dSTom St Denis #define DC_I2C_TRANSACTION1__DC_I2C_STOP1__SHIFT 0x0000000d 4525de2bdb3dSTom St Denis #define DC_I2C_TRANSACTION1__DC_I2C_STOP_ON_NACK1_MASK 0x00000100L 4526de2bdb3dSTom St Denis #define DC_I2C_TRANSACTION1__DC_I2C_STOP_ON_NACK1__SHIFT 0x00000008 4527de2bdb3dSTom St Denis #define DC_I2C_TRANSACTION2__DC_I2C_COUNT2_MASK 0x00ff0000L 4528de2bdb3dSTom St Denis #define DC_I2C_TRANSACTION2__DC_I2C_COUNT2__SHIFT 0x00000010 4529de2bdb3dSTom St Denis #define DC_I2C_TRANSACTION2__DC_I2C_RW2_MASK 0x00000001L 4530de2bdb3dSTom St Denis #define DC_I2C_TRANSACTION2__DC_I2C_RW2__SHIFT 0x00000000 4531de2bdb3dSTom St Denis #define DC_I2C_TRANSACTION2__DC_I2C_START2_MASK 0x00001000L 4532de2bdb3dSTom St Denis #define DC_I2C_TRANSACTION2__DC_I2C_START2__SHIFT 0x0000000c 4533de2bdb3dSTom St Denis #define DC_I2C_TRANSACTION2__DC_I2C_STOP2_MASK 0x00002000L 4534de2bdb3dSTom St Denis #define DC_I2C_TRANSACTION2__DC_I2C_STOP2__SHIFT 0x0000000d 4535de2bdb3dSTom St Denis #define DC_I2C_TRANSACTION2__DC_I2C_STOP_ON_NACK2_MASK 0x00000100L 4536de2bdb3dSTom St Denis #define DC_I2C_TRANSACTION2__DC_I2C_STOP_ON_NACK2__SHIFT 0x00000008 4537de2bdb3dSTom St Denis #define DC_I2C_TRANSACTION3__DC_I2C_COUNT3_MASK 0x00ff0000L 4538de2bdb3dSTom St Denis #define DC_I2C_TRANSACTION3__DC_I2C_COUNT3__SHIFT 0x00000010 4539de2bdb3dSTom St Denis #define DC_I2C_TRANSACTION3__DC_I2C_RW3_MASK 0x00000001L 4540de2bdb3dSTom St Denis #define DC_I2C_TRANSACTION3__DC_I2C_RW3__SHIFT 0x00000000 4541de2bdb3dSTom St Denis #define DC_I2C_TRANSACTION3__DC_I2C_START3_MASK 0x00001000L 4542de2bdb3dSTom St Denis #define DC_I2C_TRANSACTION3__DC_I2C_START3__SHIFT 0x0000000c 4543de2bdb3dSTom St Denis #define DC_I2C_TRANSACTION3__DC_I2C_STOP3_MASK 0x00002000L 4544de2bdb3dSTom St Denis #define DC_I2C_TRANSACTION3__DC_I2C_STOP3__SHIFT 0x0000000d 4545de2bdb3dSTom St Denis #define DC_I2C_TRANSACTION3__DC_I2C_STOP_ON_NACK3_MASK 0x00000100L 4546de2bdb3dSTom St Denis #define DC_I2C_TRANSACTION3__DC_I2C_STOP_ON_NACK3__SHIFT 0x00000008 4547de2bdb3dSTom St Denis #define DCI_CLK_CNTL__DCI_PG_TEST_CLK_SEL_MASK 0xf8000000L 4548de2bdb3dSTom St Denis #define DCI_CLK_CNTL__DCI_PG_TEST_CLK_SEL__SHIFT 0x0000001b 4549de2bdb3dSTom St Denis #define DCI_CLK_CNTL__DCI_TEST_CLK_SEL_MASK 0x0000001fL 4550de2bdb3dSTom St Denis #define DCI_CLK_CNTL__DCI_TEST_CLK_SEL__SHIFT 0x00000000 4551de2bdb3dSTom St Denis #define DCI_CLK_CNTL__DISPCLK_G_DMCU_GATE_DIS_MASK 0x00008000L 4552de2bdb3dSTom St Denis #define DCI_CLK_CNTL__DISPCLK_G_DMCU_GATE_DIS__SHIFT 0x0000000f 4553de2bdb3dSTom St Denis #define DCI_CLK_CNTL__DISPCLK_G_DMIF0_GATE_DIS_MASK 0x00010000L 4554de2bdb3dSTom St Denis #define DCI_CLK_CNTL__DISPCLK_G_DMIF0_GATE_DIS__SHIFT 0x00000010 4555de2bdb3dSTom St Denis #define DCI_CLK_CNTL__DISPCLK_G_DMIF1_GATE_DIS_MASK 0x00020000L 4556de2bdb3dSTom St Denis #define DCI_CLK_CNTL__DISPCLK_G_DMIF1_GATE_DIS__SHIFT 0x00000011 4557de2bdb3dSTom St Denis #define DCI_CLK_CNTL__DISPCLK_G_DMIF2_GATE_DIS_MASK 0x00040000L 4558de2bdb3dSTom St Denis #define DCI_CLK_CNTL__DISPCLK_G_DMIF2_GATE_DIS__SHIFT 0x00000012 4559de2bdb3dSTom St Denis #define DCI_CLK_CNTL__DISPCLK_G_DMIF3_GATE_DIS_MASK 0x00080000L 4560de2bdb3dSTom St Denis #define DCI_CLK_CNTL__DISPCLK_G_DMIF3_GATE_DIS__SHIFT 0x00000013 4561de2bdb3dSTom St Denis #define DCI_CLK_CNTL__DISPCLK_G_DMIF4_GATE_DIS_MASK 0x00100000L 4562de2bdb3dSTom St Denis #define DCI_CLK_CNTL__DISPCLK_G_DMIF4_GATE_DIS__SHIFT 0x00000014 4563de2bdb3dSTom St Denis #define DCI_CLK_CNTL__DISPCLK_G_DMIF5_GATE_DIS_MASK 0x00200000L 4564de2bdb3dSTom St Denis #define DCI_CLK_CNTL__DISPCLK_G_DMIF5_GATE_DIS__SHIFT 0x00000015 4565de2bdb3dSTom St Denis #define DCI_CLK_CNTL__DISPCLK_G_FBC_GATE_DIS_MASK 0x00000200L 4566de2bdb3dSTom St Denis #define DCI_CLK_CNTL__DISPCLK_G_FBC_GATE_DIS__SHIFT 0x00000009 4567de2bdb3dSTom St Denis #define DCI_CLK_CNTL__DISPCLK_G_VGA_GATE_DIS_MASK 0x00000800L 4568de2bdb3dSTom St Denis #define DCI_CLK_CNTL__DISPCLK_G_VGA_GATE_DIS__SHIFT 0x0000000b 4569de2bdb3dSTom St Denis #define DCI_CLK_CNTL__DISPCLK_G_VIP_GATE_DIS_MASK 0x00002000L 4570de2bdb3dSTom St Denis #define DCI_CLK_CNTL__DISPCLK_G_VIP_GATE_DIS__SHIFT 0x0000000d 4571de2bdb3dSTom St Denis #define DCI_CLK_CNTL__DISPCLK_M_GATE_DIS_MASK 0x00000040L 4572de2bdb3dSTom St Denis #define DCI_CLK_CNTL__DISPCLK_M_GATE_DIS__SHIFT 0x00000006 4573de2bdb3dSTom St Denis #define DCI_CLK_CNTL__DISPCLK_R_DCI_GATE_DIS_MASK 0x00000020L 4574de2bdb3dSTom St Denis #define DCI_CLK_CNTL__DISPCLK_R_DCI_GATE_DIS__SHIFT 0x00000005 4575de2bdb3dSTom St Denis #define DCI_CLK_CNTL__DISPCLK_R_DMCU_GATE_DIS_MASK 0x00004000L 4576de2bdb3dSTom St Denis #define DCI_CLK_CNTL__DISPCLK_R_DMCU_GATE_DIS__SHIFT 0x0000000e 4577de2bdb3dSTom St Denis #define DCI_CLK_CNTL__DISPCLK_R_VGA_GATE_DIS_MASK 0x00000400L 4578de2bdb3dSTom St Denis #define DCI_CLK_CNTL__DISPCLK_R_VGA_GATE_DIS__SHIFT 0x0000000a 4579de2bdb3dSTom St Denis #define DCI_CLK_CNTL__DISPCLK_R_VIP_GATE_DIS_MASK 0x00001000L 4580de2bdb3dSTom St Denis #define DCI_CLK_CNTL__DISPCLK_R_VIP_GATE_DIS__SHIFT 0x0000000c 4581de2bdb3dSTom St Denis #define DCI_CLK_CNTL__SCLK_G_DMIF_GATE_DIS_MASK 0x00400000L 4582de2bdb3dSTom St Denis #define DCI_CLK_CNTL__SCLK_G_DMIF_GATE_DIS__SHIFT 0x00000016 4583de2bdb3dSTom St Denis #define DCI_CLK_CNTL__SCLK_G_DMIFTRK_GATE_DIS_MASK 0x00800000L 4584de2bdb3dSTom St Denis #define DCI_CLK_CNTL__SCLK_G_DMIFTRK_GATE_DIS__SHIFT 0x00000017 4585de2bdb3dSTom St Denis #define DCI_CLK_CNTL__SCLK_R_AZ_GATE_DIS_MASK 0x00000100L 4586de2bdb3dSTom St Denis #define DCI_CLK_CNTL__SCLK_R_AZ_GATE_DIS__SHIFT 0x00000008 4587de2bdb3dSTom St Denis #define DCI_DEBUG_CONFIG__DCI_DBG_SEL_MASK 0x0000000fL 4588de2bdb3dSTom St Denis #define DCI_DEBUG_CONFIG__DCI_DBG_SEL__SHIFT 0x00000000 4589de2bdb3dSTom St Denis #define DCI_MEM_PWR_CNTL__DMIF0_ASYNC_LIGHT_SLEEP_DIS_MASK 0x00000001L 4590de2bdb3dSTom St Denis #define DCI_MEM_PWR_CNTL__DMIF0_ASYNC_LIGHT_SLEEP_DIS__SHIFT 0x00000000 4591de2bdb3dSTom St Denis #define DCI_MEM_PWR_CNTL__DMIF0_ASYNC_MEM_PWR_STATE_MASK 0x00003000L 4592de2bdb3dSTom St Denis #define DCI_MEM_PWR_CNTL__DMIF0_ASYNC_MEM_PWR_STATE__SHIFT 0x0000000c 4593de2bdb3dSTom St Denis #define DCI_MEM_PWR_CNTL__DMIF0_ASYNC_MEM_SHUTDOWN_DIS_MASK 0x00000040L 4594de2bdb3dSTom St Denis #define DCI_MEM_PWR_CNTL__DMIF0_ASYNC_MEM_SHUTDOWN_DIS__SHIFT 0x00000006 4595de2bdb3dSTom St Denis #define DCI_MEM_PWR_CNTL__DMIF1_ASYNC_LIGHT_SLEEP_DIS_MASK 0x00000002L 4596de2bdb3dSTom St Denis #define DCI_MEM_PWR_CNTL__DMIF1_ASYNC_LIGHT_SLEEP_DIS__SHIFT 0x00000001 4597de2bdb3dSTom St Denis #define DCI_MEM_PWR_CNTL__DMIF1_ASYNC_MEM_PWR_STATE_MASK 0x0000c000L 4598de2bdb3dSTom St Denis #define DCI_MEM_PWR_CNTL__DMIF1_ASYNC_MEM_PWR_STATE__SHIFT 0x0000000e 4599de2bdb3dSTom St Denis #define DCI_MEM_PWR_CNTL__DMIF1_ASYNC_MEM_SHUTDOWN_DIS_MASK 0x00000080L 4600de2bdb3dSTom St Denis #define DCI_MEM_PWR_CNTL__DMIF1_ASYNC_MEM_SHUTDOWN_DIS__SHIFT 0x00000007 4601de2bdb3dSTom St Denis #define DCI_MEM_PWR_CNTL__DMIF2_ASYNC_LIGHT_SLEEP_DIS_MASK 0x00000004L 4602de2bdb3dSTom St Denis #define DCI_MEM_PWR_CNTL__DMIF2_ASYNC_LIGHT_SLEEP_DIS__SHIFT 0x00000002 4603de2bdb3dSTom St Denis #define DCI_MEM_PWR_CNTL__DMIF2_ASYNC_MEM_PWR_STATE_MASK 0x00030000L 4604de2bdb3dSTom St Denis #define DCI_MEM_PWR_CNTL__DMIF2_ASYNC_MEM_PWR_STATE__SHIFT 0x00000010 4605de2bdb3dSTom St Denis #define DCI_MEM_PWR_CNTL__DMIF2_ASYNC_MEM_SHUTDOWN_DIS_MASK 0x00000100L 4606de2bdb3dSTom St Denis #define DCI_MEM_PWR_CNTL__DMIF2_ASYNC_MEM_SHUTDOWN_DIS__SHIFT 0x00000008 4607de2bdb3dSTom St Denis #define DCI_MEM_PWR_CNTL__DMIF3_ASYNC_LIGHT_SLEEP_DIS_MASK 0x00000008L 4608de2bdb3dSTom St Denis #define DCI_MEM_PWR_CNTL__DMIF3_ASYNC_LIGHT_SLEEP_DIS__SHIFT 0x00000003 4609de2bdb3dSTom St Denis #define DCI_MEM_PWR_CNTL__DMIF3_ASYNC_MEM_PWR_STATE_MASK 0x000c0000L 4610de2bdb3dSTom St Denis #define DCI_MEM_PWR_CNTL__DMIF3_ASYNC_MEM_PWR_STATE__SHIFT 0x00000012 4611de2bdb3dSTom St Denis #define DCI_MEM_PWR_CNTL__DMIF3_ASYNC_MEM_SHUTDOWN_DIS_MASK 0x00000200L 4612de2bdb3dSTom St Denis #define DCI_MEM_PWR_CNTL__DMIF3_ASYNC_MEM_SHUTDOWN_DIS__SHIFT 0x00000009 4613de2bdb3dSTom St Denis #define DCI_MEM_PWR_CNTL__DMIF4_ASYNC_LIGHT_SLEEP_DIS_MASK 0x00000010L 4614de2bdb3dSTom St Denis #define DCI_MEM_PWR_CNTL__DMIF4_ASYNC_LIGHT_SLEEP_DIS__SHIFT 0x00000004 4615de2bdb3dSTom St Denis #define DCI_MEM_PWR_CNTL__DMIF4_ASYNC_MEM_PWR_STATE_MASK 0x00300000L 4616de2bdb3dSTom St Denis #define DCI_MEM_PWR_CNTL__DMIF4_ASYNC_MEM_PWR_STATE__SHIFT 0x00000014 4617de2bdb3dSTom St Denis #define DCI_MEM_PWR_CNTL__DMIF4_ASYNC_MEM_SHUTDOWN_DIS_MASK 0x00000400L 4618de2bdb3dSTom St Denis #define DCI_MEM_PWR_CNTL__DMIF4_ASYNC_MEM_SHUTDOWN_DIS__SHIFT 0x0000000a 4619de2bdb3dSTom St Denis #define DCI_MEM_PWR_CNTL__DMIF5_ASYNC_LIGHT_SLEEP_DIS_MASK 0x00000020L 4620de2bdb3dSTom St Denis #define DCI_MEM_PWR_CNTL__DMIF5_ASYNC_LIGHT_SLEEP_DIS__SHIFT 0x00000005 4621de2bdb3dSTom St Denis #define DCI_MEM_PWR_CNTL__DMIF5_ASYNC_MEM_PWR_STATE_MASK 0x00c00000L 4622de2bdb3dSTom St Denis #define DCI_MEM_PWR_CNTL__DMIF5_ASYNC_MEM_PWR_STATE__SHIFT 0x00000016 4623de2bdb3dSTom St Denis #define DCI_MEM_PWR_CNTL__DMIF5_ASYNC_MEM_SHUTDOWN_DIS_MASK 0x00000800L 4624de2bdb3dSTom St Denis #define DCI_MEM_PWR_CNTL__DMIF5_ASYNC_MEM_SHUTDOWN_DIS__SHIFT 0x0000000b 4625de2bdb3dSTom St Denis #define DCI_MEM_PWR_STATE2__DMCU_ERAM1_PWR_STATE_MASK 0x00000003L 4626de2bdb3dSTom St Denis #define DCI_MEM_PWR_STATE2__DMCU_ERAM1_PWR_STATE__SHIFT 0x00000000 4627de2bdb3dSTom St Denis #define DCI_MEM_PWR_STATE2__DMCU_ERAM2_PWR_STATE_MASK 0x0000000cL 4628de2bdb3dSTom St Denis #define DCI_MEM_PWR_STATE2__DMCU_ERAM2_PWR_STATE__SHIFT 0x00000002 4629de2bdb3dSTom St Denis #define DCI_MEM_PWR_STATE2__DMCU_ERAM3_PWR_STATE_MASK 0x00000030L 4630de2bdb3dSTom St Denis #define DCI_MEM_PWR_STATE2__DMCU_ERAM3_PWR_STATE__SHIFT 0x00000004 4631de2bdb3dSTom St Denis #define DCI_MEM_PWR_STATE__AZ_MEM_PWR_STATE_MASK 0x00c00000L 4632de2bdb3dSTom St Denis #define DCI_MEM_PWR_STATE__AZ_MEM_PWR_STATE__SHIFT 0x00000016 4633de2bdb3dSTom St Denis #define DCI_MEM_PWR_STATE__DMCU_IRAM_PWR_STATE_MASK 0x30000000L 4634de2bdb3dSTom St Denis #define DCI_MEM_PWR_STATE__DMCU_IRAM_PWR_STATE__SHIFT 0x0000001c 4635de2bdb3dSTom St Denis #define DCI_MEM_PWR_STATE__DMCU_MEM_PWR_STATE_MASK 0x00000003L 4636de2bdb3dSTom St Denis #define DCI_MEM_PWR_STATE__DMCU_MEM_PWR_STATE__SHIFT 0x00000000 4637de2bdb3dSTom St Denis #define DCI_MEM_PWR_STATE__DMIF0_MEM_PWR_STATE_MASK 0x0000000cL 4638de2bdb3dSTom St Denis #define DCI_MEM_PWR_STATE__DMIF0_MEM_PWR_STATE__SHIFT 0x00000002 4639de2bdb3dSTom St Denis #define DCI_MEM_PWR_STATE__DMIF1_MEM_PWR_STATE_MASK 0x00000030L 4640de2bdb3dSTom St Denis #define DCI_MEM_PWR_STATE__DMIF1_MEM_PWR_STATE__SHIFT 0x00000004 4641de2bdb3dSTom St Denis #define DCI_MEM_PWR_STATE__DMIF2_MEM_PWR_STATE_MASK 0x000000c0L 4642de2bdb3dSTom St Denis #define DCI_MEM_PWR_STATE__DMIF2_MEM_PWR_STATE__SHIFT 0x00000006 4643de2bdb3dSTom St Denis #define DCI_MEM_PWR_STATE__DMIF3_MEM_PWR_STATE_MASK 0x00000300L 4644de2bdb3dSTom St Denis #define DCI_MEM_PWR_STATE__DMIF3_MEM_PWR_STATE__SHIFT 0x00000008 4645de2bdb3dSTom St Denis #define DCI_MEM_PWR_STATE__DMIF4_MEM_PWR_STATE_MASK 0x00000c00L 4646de2bdb3dSTom St Denis #define DCI_MEM_PWR_STATE__DMIF4_MEM_PWR_STATE__SHIFT 0x0000000a 4647de2bdb3dSTom St Denis #define DCI_MEM_PWR_STATE__DMIF5_MEM_PWR_STATE_MASK 0x00003000L 4648de2bdb3dSTom St Denis #define DCI_MEM_PWR_STATE__DMIF5_MEM_PWR_STATE__SHIFT 0x0000000c 4649de2bdb3dSTom St Denis #define DCI_MEM_PWR_STATE__DMIF_XLR_MEM1_PWR_STATE_MASK 0x0c000000L 4650de2bdb3dSTom St Denis #define DCI_MEM_PWR_STATE__DMIF_XLR_MEM1_PWR_STATE__SHIFT 0x0000001a 4651de2bdb3dSTom St Denis #define DCI_MEM_PWR_STATE__DMIF_XLR_MEM_PWR_STATE_MASK 0x03000000L 4652de2bdb3dSTom St Denis #define DCI_MEM_PWR_STATE__DMIF_XLR_MEM_PWR_STATE__SHIFT 0x00000018 4653de2bdb3dSTom St Denis #define DCI_MEM_PWR_STATE__FBC_MEM_PWR_STATE_MASK 0x00030000L 4654de2bdb3dSTom St Denis #define DCI_MEM_PWR_STATE__FBC_MEM_PWR_STATE__SHIFT 0x00000010 4655de2bdb3dSTom St Denis #define DCI_MEM_PWR_STATE__MCIF_MEM_PWR_STATE_MASK 0x000c0000L 4656de2bdb3dSTom St Denis #define DCI_MEM_PWR_STATE__MCIF_MEM_PWR_STATE__SHIFT 0x00000012 4657de2bdb3dSTom St Denis #define DCI_MEM_PWR_STATE__VGA_MEM_PWR_STATE_MASK 0x0000c000L 4658de2bdb3dSTom St Denis #define DCI_MEM_PWR_STATE__VGA_MEM_PWR_STATE__SHIFT 0x0000000e 4659de2bdb3dSTom St Denis #define DCI_MEM_PWR_STATE__VIP_MEM_PWR_STATE_MASK 0x00300000L 4660de2bdb3dSTom St Denis #define DCI_MEM_PWR_STATE__VIP_MEM_PWR_STATE__SHIFT 0x00000014 4661de2bdb3dSTom St Denis #define DCIO_DEBUG10__DCIO_DIGC_DEBUG_MASK 0xffffffffL 4662de2bdb3dSTom St Denis #define DCIO_DEBUG10__DCIO_DIGC_DEBUG__SHIFT 0x00000000 4663de2bdb3dSTom St Denis #define DCIO_DEBUG11__DCIO_DIGD_DEBUG_MASK 0xffffffffL 4664de2bdb3dSTom St Denis #define DCIO_DEBUG11__DCIO_DIGD_DEBUG__SHIFT 0x00000000 4665de2bdb3dSTom St Denis #define DCIO_DEBUG12__DCIO_DIGE_DEBUG_MASK 0xffffffffL 4666de2bdb3dSTom St Denis #define DCIO_DEBUG12__DCIO_DIGE_DEBUG__SHIFT 0x00000000 4667de2bdb3dSTom St Denis #define DCIO_DEBUG13__DCIO_DIGF_DEBUG_MASK 0xffffffffL 4668de2bdb3dSTom St Denis #define DCIO_DEBUG13__DCIO_DIGF_DEBUG__SHIFT 0x00000000 4669de2bdb3dSTom St Denis #define DCIO_DEBUG1__DOUT_DCIO_DVO_CLK_TRISTATE_MASK 0x00040000L 4670de2bdb3dSTom St Denis #define DCIO_DEBUG1__DOUT_DCIO_DVO_CLK_TRISTATE__SHIFT 0x00000012 4671de2bdb3dSTom St Denis #define DCIO_DEBUG1__DOUT_DCIO_DVOCNTL1_A0_MASK 0x00008000L 4672de2bdb3dSTom St Denis #define DCIO_DEBUG1__DOUT_DCIO_DVOCNTL1_A0_PREMUX_MASK 0x00004000L 4673de2bdb3dSTom St Denis #define DCIO_DEBUG1__DOUT_DCIO_DVOCNTL1_A0_PREMUX__SHIFT 0x0000000e 4674de2bdb3dSTom St Denis #define DCIO_DEBUG1__DOUT_DCIO_DVOCNTL1_A0_REG_MASK 0x00002000L 4675de2bdb3dSTom St Denis #define DCIO_DEBUG1__DOUT_DCIO_DVOCNTL1_A0_REG__SHIFT 0x0000000d 4676de2bdb3dSTom St Denis #define DCIO_DEBUG1__DOUT_DCIO_DVOCNTL1_A0__SHIFT 0x0000000f 4677de2bdb3dSTom St Denis #define DCIO_DEBUG1__DOUT_DCIO_DVOCNTL1_EN_MASK 0x00100000L 4678de2bdb3dSTom St Denis #define DCIO_DEBUG1__DOUT_DCIO_DVOCNTL1_EN_PREMUX_MASK 0x00080000L 4679de2bdb3dSTom St Denis #define DCIO_DEBUG1__DOUT_DCIO_DVOCNTL1_EN_PREMUX__SHIFT 0x00000013 4680de2bdb3dSTom St Denis #define DCIO_DEBUG1__DOUT_DCIO_DVOCNTL1_EN_REG_MASK 0x00010000L 4681de2bdb3dSTom St Denis #define DCIO_DEBUG1__DOUT_DCIO_DVOCNTL1_EN_REG__SHIFT 0x00000010 4682de2bdb3dSTom St Denis #define DCIO_DEBUG1__DOUT_DCIO_DVOCNTL1_EN__SHIFT 0x00000014 4683de2bdb3dSTom St Denis #define DCIO_DEBUG1__DOUT_DCIO_DVOCNTL1_MASK_REG_MASK 0x00400000L 4684de2bdb3dSTom St Denis #define DCIO_DEBUG1__DOUT_DCIO_DVOCNTL1_MASK_REG__SHIFT 0x00000016 4685de2bdb3dSTom St Denis #define DCIO_DEBUG1__DOUT_DCIO_DVOCNTL1_MUX_MASK 0x00200000L 4686de2bdb3dSTom St Denis #define DCIO_DEBUG1__DOUT_DCIO_DVOCNTL1_MUX__SHIFT 0x00000015 4687de2bdb3dSTom St Denis #define DCIO_DEBUG1__DOUT_DCIO_DVOCNTL1_SEL0_MASK 0x08000000L 4688de2bdb3dSTom St Denis #define DCIO_DEBUG1__DOUT_DCIO_DVOCNTL1_SEL0_PREMUX_MASK 0x04000000L 4689de2bdb3dSTom St Denis #define DCIO_DEBUG1__DOUT_DCIO_DVOCNTL1_SEL0_PREMUX__SHIFT 0x0000001a 4690de2bdb3dSTom St Denis #define DCIO_DEBUG1__DOUT_DCIO_DVOCNTL1_SEL0__SHIFT 0x0000001b 4691de2bdb3dSTom St Denis #define DCIO_DEBUG1__DOUT_DCIO_DVO_ENABLE_MASK 0x00800000L 4692de2bdb3dSTom St Denis #define DCIO_DEBUG1__DOUT_DCIO_DVO_ENABLE__SHIFT 0x00000017 4693de2bdb3dSTom St Denis #define DCIO_DEBUG1__DOUT_DCIO_DVO_HSYNC_TRISTATE_MASK 0x00020000L 4694de2bdb3dSTom St Denis #define DCIO_DEBUG1__DOUT_DCIO_DVO_HSYNC_TRISTATE__SHIFT 0x00000011 4695de2bdb3dSTom St Denis #define DCIO_DEBUG1__DOUT_DCIO_DVO_RATE_SEL_MASK 0x02000000L 4696de2bdb3dSTom St Denis #define DCIO_DEBUG1__DOUT_DCIO_DVO_RATE_SEL__SHIFT 0x00000019 4697de2bdb3dSTom St Denis #define DCIO_DEBUG1__DOUT_DCIO_DVO_VSYNC_TRISTATE_MASK 0x01000000L 4698de2bdb3dSTom St Denis #define DCIO_DEBUG1__DOUT_DCIO_DVO_VSYNC_TRISTATE__SHIFT 0x00000018 4699de2bdb3dSTom St Denis #define DCIO_DEBUG1__DOUT_DCIO_MVP_DVOCLK_C_MASK 0x00001000L 4700de2bdb3dSTom St Denis #define DCIO_DEBUG1__DOUT_DCIO_MVP_DVOCLK_C__SHIFT 0x0000000c 4701de2bdb3dSTom St Denis #define DCIO_DEBUG1__DOUT_DCIO_MVP_DVOCNTL_A0_MASK 0x000000c0L 4702de2bdb3dSTom St Denis #define DCIO_DEBUG1__DOUT_DCIO_MVP_DVOCNTL_A0_REG_MASK 0x00000003L 4703de2bdb3dSTom St Denis #define DCIO_DEBUG1__DOUT_DCIO_MVP_DVOCNTL_A0_REG__SHIFT 0x00000000 4704de2bdb3dSTom St Denis #define DCIO_DEBUG1__DOUT_DCIO_MVP_DVOCNTL_A0__SHIFT 0x00000006 4705de2bdb3dSTom St Denis #define DCIO_DEBUG1__DOUT_DCIO_MVP_DVOCNTL_EN_MASK 0x00000c00L 4706de2bdb3dSTom St Denis #define DCIO_DEBUG1__DOUT_DCIO_MVP_DVOCNTL_EN_REG_MASK 0x00000030L 4707de2bdb3dSTom St Denis #define DCIO_DEBUG1__DOUT_DCIO_MVP_DVOCNTL_EN_REG__SHIFT 0x00000004 4708de2bdb3dSTom St Denis #define DCIO_DEBUG1__DOUT_DCIO_MVP_DVOCNTL_EN__SHIFT 0x0000000a 4709de2bdb3dSTom St Denis #define DCIO_DEBUG1__DOUT_DCIO_MVP_DVOCNTL_MASK_REG_MASK 0x0000000cL 4710de2bdb3dSTom St Denis #define DCIO_DEBUG1__DOUT_DCIO_MVP_DVOCNTL_MASK_REG__SHIFT 0x00000002 4711de2bdb3dSTom St Denis #define DCIO_DEBUG1__DOUT_DCIO_MVP_DVOCNTL_SEL0_MASK 0x00000300L 4712de2bdb3dSTom St Denis #define DCIO_DEBUG1__DOUT_DCIO_MVP_DVOCNTL_SEL0__SHIFT 0x00000008 4713de2bdb3dSTom St Denis #define DCIO_DEBUG2__DCIO_DEBUG2_MASK 0xffffffffL 4714de2bdb3dSTom St Denis #define DCIO_DEBUG2__DCIO_DEBUG2__SHIFT 0x00000000 4715de2bdb3dSTom St Denis #define DCIO_DEBUG3__DCIO_DEBUG3_MASK 0xffffffffL 4716de2bdb3dSTom St Denis #define DCIO_DEBUG3__DCIO_DEBUG3__SHIFT 0x00000000 4717de2bdb3dSTom St Denis #define DCIO_DEBUG4__DCIO_DEBUG4_MASK 0xffffffffL 4718de2bdb3dSTom St Denis #define DCIO_DEBUG4__DCIO_DEBUG4__SHIFT 0x00000000 4719de2bdb3dSTom St Denis #define DCIO_DEBUG5__DCIO_DEBUG5_MASK 0xffffffffL 4720de2bdb3dSTom St Denis #define DCIO_DEBUG5__DCIO_DEBUG5__SHIFT 0x00000000 4721de2bdb3dSTom St Denis #define DCIO_DEBUG6__DCIO_DEBUG6_MASK 0xffffffffL 4722de2bdb3dSTom St Denis #define DCIO_DEBUG6__DCIO_DEBUG6__SHIFT 0x00000000 4723de2bdb3dSTom St Denis #define DCIO_DEBUG7__DCIO_DEBUG7_MASK 0xffffffffL 4724de2bdb3dSTom St Denis #define DCIO_DEBUG7__DCIO_DEBUG7__SHIFT 0x00000000 4725de2bdb3dSTom St Denis #define DCIO_DEBUG8__DCIO_DEBUG8_MASK 0xffffffffL 4726de2bdb3dSTom St Denis #define DCIO_DEBUG8__DCIO_DEBUG8__SHIFT 0x00000000 4727de2bdb3dSTom St Denis #define DCIO_DEBUG9__DCIO_DEBUG9_MASK 0xffffffffL 4728de2bdb3dSTom St Denis #define DCIO_DEBUG9__DCIO_DEBUG9__SHIFT 0x00000000 4729de2bdb3dSTom St Denis #define DCIO_DEBUGA__DCIO_DEBUGA_MASK 0xffffffffL 4730de2bdb3dSTom St Denis #define DCIO_DEBUGA__DCIO_DEBUGA__SHIFT 0x00000000 4731de2bdb3dSTom St Denis #define DCIO_DEBUGB__DCIO_DEBUGB_MASK 0xffffffffL 4732de2bdb3dSTom St Denis #define DCIO_DEBUGB__DCIO_DEBUGB__SHIFT 0x00000000 4733de2bdb3dSTom St Denis #define DCIO_DEBUGC__DCIO_DEBUGC_MASK 0xffffffffL 4734de2bdb3dSTom St Denis #define DCIO_DEBUGC__DCIO_DEBUGC__SHIFT 0x00000000 4735de2bdb3dSTom St Denis #define DCIO_DEBUG__DCIO_DEBUG_MASK 0xffffffffL 4736de2bdb3dSTom St Denis #define DCIO_DEBUG__DCIO_DEBUG__SHIFT 0x00000000 4737de2bdb3dSTom St Denis #define DCIO_DEBUGD__DCIO_DEBUGD_MASK 0xffffffffL 4738de2bdb3dSTom St Denis #define DCIO_DEBUGD__DCIO_DEBUGD__SHIFT 0x00000000 4739de2bdb3dSTom St Denis #define DCIO_DEBUGE__DCIO_DIGA_DEBUG_MASK 0xffffffffL 4740de2bdb3dSTom St Denis #define DCIO_DEBUGE__DCIO_DIGA_DEBUG__SHIFT 0x00000000 4741de2bdb3dSTom St Denis #define DCIO_DEBUGF__DCIO_DIGB_DEBUG_MASK 0xffffffffL 4742de2bdb3dSTom St Denis #define DCIO_DEBUGF__DCIO_DIGB_DEBUG__SHIFT 0x00000000 4743de2bdb3dSTom St Denis #define DCIO_DEBUG_ID__DCIO_DEBUG_ID_MASK 0xffffffffL 4744de2bdb3dSTom St Denis #define DCIO_DEBUG_ID__DCIO_DEBUG_ID__SHIFT 0x00000000 4745de2bdb3dSTom St Denis #define DCIO_GSL0_CNTL__DCIO_GSL0_GLOBAL_UNLOCK_SEL_MASK 0x00070000L 4746de2bdb3dSTom St Denis #define DCIO_GSL0_CNTL__DCIO_GSL0_GLOBAL_UNLOCK_SEL__SHIFT 0x00000010 4747de2bdb3dSTom St Denis #define DCIO_GSL0_CNTL__DCIO_GSL0_TIMING_SYNC_SEL_MASK 0x00000700L 4748de2bdb3dSTom St Denis #define DCIO_GSL0_CNTL__DCIO_GSL0_TIMING_SYNC_SEL__SHIFT 0x00000008 4749de2bdb3dSTom St Denis #define DCIO_GSL0_CNTL__DCIO_GSL0_VSYNC_SEL_MASK 0x00000007L 4750de2bdb3dSTom St Denis #define DCIO_GSL0_CNTL__DCIO_GSL0_VSYNC_SEL__SHIFT 0x00000000 4751de2bdb3dSTom St Denis #define DCIO_GSL1_CNTL__DCIO_GSL1_GLOBAL_UNLOCK_SEL_MASK 0x00070000L 4752de2bdb3dSTom St Denis #define DCIO_GSL1_CNTL__DCIO_GSL1_GLOBAL_UNLOCK_SEL__SHIFT 0x00000010 4753de2bdb3dSTom St Denis #define DCIO_GSL1_CNTL__DCIO_GSL1_TIMING_SYNC_SEL_MASK 0x00000700L 4754de2bdb3dSTom St Denis #define DCIO_GSL1_CNTL__DCIO_GSL1_TIMING_SYNC_SEL__SHIFT 0x00000008 4755de2bdb3dSTom St Denis #define DCIO_GSL1_CNTL__DCIO_GSL1_VSYNC_SEL_MASK 0x00000007L 4756de2bdb3dSTom St Denis #define DCIO_GSL1_CNTL__DCIO_GSL1_VSYNC_SEL__SHIFT 0x00000000 4757de2bdb3dSTom St Denis #define DCIO_GSL2_CNTL__DCIO_GSL2_GLOBAL_UNLOCK_SEL_MASK 0x00070000L 4758de2bdb3dSTom St Denis #define DCIO_GSL2_CNTL__DCIO_GSL2_GLOBAL_UNLOCK_SEL__SHIFT 0x00000010 4759de2bdb3dSTom St Denis #define DCIO_GSL2_CNTL__DCIO_GSL2_TIMING_SYNC_SEL_MASK 0x00000700L 4760de2bdb3dSTom St Denis #define DCIO_GSL2_CNTL__DCIO_GSL2_TIMING_SYNC_SEL__SHIFT 0x00000008 4761de2bdb3dSTom St Denis #define DCIO_GSL2_CNTL__DCIO_GSL2_VSYNC_SEL_MASK 0x00000007L 4762de2bdb3dSTom St Denis #define DCIO_GSL2_CNTL__DCIO_GSL2_VSYNC_SEL__SHIFT 0x00000000 4763de2bdb3dSTom St Denis #define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_CLK_GSL_FLIP_LOCK_SEL_MASK 0x00000030L 4764de2bdb3dSTom St Denis #define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_CLK_GSL_FLIP_LOCK_SEL__SHIFT 0x00000004 4765de2bdb3dSTom St Denis #define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_CLK_GSL_MASK_MASK 0x00000300L 4766de2bdb3dSTom St Denis #define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_CLK_GSL_MASK__SHIFT 0x00000008 4767de2bdb3dSTom St Denis #define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_CLK_GSL_TIMING_SYNC_SEL_MASK 0x00000003L 4768de2bdb3dSTom St Denis #define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_CLK_GSL_TIMING_SYNC_SEL__SHIFT 0x00000000 4769de2bdb3dSTom St Denis #define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_VSYNC_GSL_FLIP_LOCK_SEL_MASK 0x00300000L 4770de2bdb3dSTom St Denis #define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_VSYNC_GSL_FLIP_LOCK_SEL__SHIFT 0x00000014 4771de2bdb3dSTom St Denis #define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_VSYNC_GSL_MASK_MASK 0x03000000L 4772de2bdb3dSTom St Denis #define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_VSYNC_GSL_MASK__SHIFT 0x00000018 4773de2bdb3dSTom St Denis #define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_VSYNC_GSL_TIMING_SYNC_SEL_MASK 0x00030000L 4774de2bdb3dSTom St Denis #define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_VSYNC_GSL_TIMING_SYNC_SEL__SHIFT 0x00000010 4775de2bdb3dSTom St Denis #define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_A_GSL_FLIP_LOCK_SEL_MASK 0x00000030L 4776de2bdb3dSTom St Denis #define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_A_GSL_FLIP_LOCK_SEL__SHIFT 0x00000004 4777de2bdb3dSTom St Denis #define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_A_GSL_MASK_MASK 0x00000300L 4778de2bdb3dSTom St Denis #define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_A_GSL_MASK__SHIFT 0x00000008 4779de2bdb3dSTom St Denis #define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_A_GSL_TIMING_SYNC_SEL_MASK 0x00000003L 4780de2bdb3dSTom St Denis #define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_A_GSL_TIMING_SYNC_SEL__SHIFT 0x00000000 4781de2bdb3dSTom St Denis #define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_B_GSL_FLIP_LOCK_SEL_MASK 0x00300000L 4782de2bdb3dSTom St Denis #define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_B_GSL_FLIP_LOCK_SEL__SHIFT 0x00000014 4783de2bdb3dSTom St Denis #define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_B_GSL_MASK_MASK 0x03000000L 4784de2bdb3dSTom St Denis #define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_B_GSL_MASK__SHIFT 0x00000018 4785de2bdb3dSTom St Denis #define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_B_GSL_TIMING_SYNC_SEL_MASK 0x00030000L 4786de2bdb3dSTom St Denis #define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_B_GSL_TIMING_SYNC_SEL__SHIFT 0x00000010 4787de2bdb3dSTom St Denis #define DCIO_IMPCAL_CNTL_AB__CALR_CNTL_OVERRIDE_MASK 0x0000000fL 4788de2bdb3dSTom St Denis #define DCIO_IMPCAL_CNTL_AB__CALR_CNTL_OVERRIDE__SHIFT 0x00000000 4789de2bdb3dSTom St Denis #define DCIO_IMPCAL_CNTL_AB__IMPCAL_ARB_STATE_MASK 0x00007000L 4790de2bdb3dSTom St Denis #define DCIO_IMPCAL_CNTL_AB__IMPCAL_ARB_STATE__SHIFT 0x0000000c 4791de2bdb3dSTom St Denis #define DCIO_IMPCAL_CNTL_AB__IMPCAL_SOFT_RESET_MASK 0x00000020L 4792de2bdb3dSTom St Denis #define DCIO_IMPCAL_CNTL_AB__IMPCAL_SOFT_RESET__SHIFT 0x00000005 4793de2bdb3dSTom St Denis #define DCIO_IMPCAL_CNTL_AB__IMPCAL_STATUS_MASK 0x00000300L 4794de2bdb3dSTom St Denis #define DCIO_IMPCAL_CNTL_AB__IMPCAL_STATUS__SHIFT 0x00000008 4795de2bdb3dSTom St Denis #define DCIO_IMPCAL_CNTL_CD__CALR_CNTL_OVERRIDE_MASK 0x0000000fL 4796de2bdb3dSTom St Denis #define DCIO_IMPCAL_CNTL_CD__CALR_CNTL_OVERRIDE__SHIFT 0x00000000 4797de2bdb3dSTom St Denis #define DCIO_IMPCAL_CNTL_CD__IMPCAL_ARB_STATE_MASK 0x00007000L 4798de2bdb3dSTom St Denis #define DCIO_IMPCAL_CNTL_CD__IMPCAL_ARB_STATE__SHIFT 0x0000000c 4799de2bdb3dSTom St Denis #define DCIO_IMPCAL_CNTL_CD__IMPCAL_SOFT_RESET_MASK 0x00000020L 4800de2bdb3dSTom St Denis #define DCIO_IMPCAL_CNTL_CD__IMPCAL_SOFT_RESET__SHIFT 0x00000005 4801de2bdb3dSTom St Denis #define DCIO_IMPCAL_CNTL_CD__IMPCAL_STATUS_MASK 0x00000300L 4802de2bdb3dSTom St Denis #define DCIO_IMPCAL_CNTL_CD__IMPCAL_STATUS__SHIFT 0x00000008 4803de2bdb3dSTom St Denis #define DCIO_IMPCAL_CNTL_EF__CALR_CNTL_OVERRIDE_MASK 0x0000000fL 4804de2bdb3dSTom St Denis #define DCIO_IMPCAL_CNTL_EF__CALR_CNTL_OVERRIDE__SHIFT 0x00000000 4805de2bdb3dSTom St Denis #define DCIO_IMPCAL_CNTL_EF__IMPCAL_ARB_STATE_MASK 0x00007000L 4806de2bdb3dSTom St Denis #define DCIO_IMPCAL_CNTL_EF__IMPCAL_ARB_STATE__SHIFT 0x0000000c 4807de2bdb3dSTom St Denis #define DCIO_IMPCAL_CNTL_EF__IMPCAL_SOFT_RESET_MASK 0x00000020L 4808de2bdb3dSTom St Denis #define DCIO_IMPCAL_CNTL_EF__IMPCAL_SOFT_RESET__SHIFT 0x00000005 4809de2bdb3dSTom St Denis #define DCIO_IMPCAL_CNTL_EF__IMPCAL_STATUS_MASK 0x00000300L 4810de2bdb3dSTom St Denis #define DCIO_IMPCAL_CNTL_EF__IMPCAL_STATUS__SHIFT 0x00000008 4811de2bdb3dSTom St Denis #define DCIO_TEST_DEBUG_DATA__DCIO_TEST_DEBUG_DATA_MASK 0xffffffffL 4812de2bdb3dSTom St Denis #define DCIO_TEST_DEBUG_DATA__DCIO_TEST_DEBUG_DATA__SHIFT 0x00000000 4813de2bdb3dSTom St Denis #define DCIO_TEST_DEBUG_INDEX__DCIO_TEST_DEBUG_INDEX_MASK 0x000000ffL 4814de2bdb3dSTom St Denis #define DCIO_TEST_DEBUG_INDEX__DCIO_TEST_DEBUG_INDEX__SHIFT 0x00000000 4815de2bdb3dSTom St Denis #define DCIO_TEST_DEBUG_INDEX__DCIO_TEST_DEBUG_WRITE_EN_MASK 0x00000100L 4816de2bdb3dSTom St Denis #define DCIO_TEST_DEBUG_INDEX__DCIO_TEST_DEBUG_WRITE_EN__SHIFT 0x00000008 4817de2bdb3dSTom St Denis #define DCI_SOFT_RESET__DMIF0_SOFT_RESET_MASK 0x00000010L 4818de2bdb3dSTom St Denis #define DCI_SOFT_RESET__DMIF0_SOFT_RESET__SHIFT 0x00000004 4819de2bdb3dSTom St Denis #define DCI_SOFT_RESET__DMIF1_SOFT_RESET_MASK 0x00000020L 4820de2bdb3dSTom St Denis #define DCI_SOFT_RESET__DMIF1_SOFT_RESET__SHIFT 0x00000005 4821de2bdb3dSTom St Denis #define DCI_SOFT_RESET__DMIF2_SOFT_RESET_MASK 0x00000040L 4822de2bdb3dSTom St Denis #define DCI_SOFT_RESET__DMIF2_SOFT_RESET__SHIFT 0x00000006 4823de2bdb3dSTom St Denis #define DCI_SOFT_RESET__DMIF3_SOFT_RESET_MASK 0x00000080L 4824de2bdb3dSTom St Denis #define DCI_SOFT_RESET__DMIF3_SOFT_RESET__SHIFT 0x00000007 4825de2bdb3dSTom St Denis #define DCI_SOFT_RESET__DMIF4_SOFT_RESET_MASK 0x00000100L 4826de2bdb3dSTom St Denis #define DCI_SOFT_RESET__DMIF4_SOFT_RESET__SHIFT 0x00000008 4827de2bdb3dSTom St Denis #define DCI_SOFT_RESET__DMIF5_SOFT_RESET_MASK 0x00000200L 4828de2bdb3dSTom St Denis #define DCI_SOFT_RESET__DMIF5_SOFT_RESET__SHIFT 0x00000009 4829de2bdb3dSTom St Denis #define DCI_SOFT_RESET__DMIFARB_SOFT_RESET_MASK 0x00001000L 4830de2bdb3dSTom St Denis #define DCI_SOFT_RESET__DMIFARB_SOFT_RESET__SHIFT 0x0000000c 4831de2bdb3dSTom St Denis #define DCI_SOFT_RESET__FBC_SOFT_RESET_MASK 0x00000008L 4832de2bdb3dSTom St Denis #define DCI_SOFT_RESET__FBC_SOFT_RESET__SHIFT 0x00000003 4833de2bdb3dSTom St Denis #define DCI_SOFT_RESET__MCIF_SOFT_RESET_MASK 0x00000004L 4834de2bdb3dSTom St Denis #define DCI_SOFT_RESET__MCIF_SOFT_RESET__SHIFT 0x00000002 4835de2bdb3dSTom St Denis #define DCI_SOFT_RESET__VGA_SOFT_RESET_MASK 0x00000001L 4836de2bdb3dSTom St Denis #define DCI_SOFT_RESET__VGA_SOFT_RESET__SHIFT 0x00000000 4837de2bdb3dSTom St Denis #define DCI_SOFT_RESET__VIP_SOFT_RESET_MASK 0x00000002L 4838de2bdb3dSTom St Denis #define DCI_SOFT_RESET__VIP_SOFT_RESET__SHIFT 0x00000001 4839de2bdb3dSTom St Denis #define DCI_TEST_DEBUG_DATA__DCI_TEST_DEBUG_DATA_MASK 0xffffffffL 4840de2bdb3dSTom St Denis #define DCI_TEST_DEBUG_DATA__DCI_TEST_DEBUG_DATA__SHIFT 0x00000000 4841de2bdb3dSTom St Denis #define DCI_TEST_DEBUG_INDEX__DCI_TEST_DEBUG_INDEX_MASK 0x000000ffL 4842de2bdb3dSTom St Denis #define DCI_TEST_DEBUG_INDEX__DCI_TEST_DEBUG_INDEX__SHIFT 0x00000000 4843de2bdb3dSTom St Denis #define DCI_TEST_DEBUG_INDEX__DCI_TEST_DEBUG_WRITE_EN_MASK 0x00000100L 4844de2bdb3dSTom St Denis #define DCI_TEST_DEBUG_INDEX__DCI_TEST_DEBUG_WRITE_EN__SHIFT 0x00000008 4845de2bdb3dSTom St Denis #define DC_LUT_30_COLOR__DC_LUT_COLOR_10_BLUE_MASK 0x000003ffL 4846de2bdb3dSTom St Denis #define DC_LUT_30_COLOR__DC_LUT_COLOR_10_BLUE__SHIFT 0x00000000 4847de2bdb3dSTom St Denis #define DC_LUT_30_COLOR__DC_LUT_COLOR_10_GREEN_MASK 0x000ffc00L 4848de2bdb3dSTom St Denis #define DC_LUT_30_COLOR__DC_LUT_COLOR_10_GREEN__SHIFT 0x0000000a 4849de2bdb3dSTom St Denis #define DC_LUT_30_COLOR__DC_LUT_COLOR_10_RED_MASK 0x3ff00000L 4850de2bdb3dSTom St Denis #define DC_LUT_30_COLOR__DC_LUT_COLOR_10_RED__SHIFT 0x00000014 4851de2bdb3dSTom St Denis #define DC_LUT_AUTOFILL__DC_LUT_AUTOFILL_DONE_MASK 0x00000002L 4852de2bdb3dSTom St Denis #define DC_LUT_AUTOFILL__DC_LUT_AUTOFILL_DONE__SHIFT 0x00000001 4853de2bdb3dSTom St Denis #define DC_LUT_AUTOFILL__DC_LUT_AUTOFILL_MASK 0x00000001L 4854de2bdb3dSTom St Denis #define DC_LUT_AUTOFILL__DC_LUT_AUTOFILL__SHIFT 0x00000000 4855de2bdb3dSTom St Denis #define DC_LUT_BLACK_OFFSET_BLUE__DC_LUT_BLACK_OFFSET_BLUE_MASK 0x0000ffffL 4856de2bdb3dSTom St Denis #define DC_LUT_BLACK_OFFSET_BLUE__DC_LUT_BLACK_OFFSET_BLUE__SHIFT 0x00000000 4857de2bdb3dSTom St Denis #define DC_LUT_BLACK_OFFSET_GREEN__DC_LUT_BLACK_OFFSET_GREEN_MASK 0x0000ffffL 4858de2bdb3dSTom St Denis #define DC_LUT_BLACK_OFFSET_GREEN__DC_LUT_BLACK_OFFSET_GREEN__SHIFT 0x00000000 4859de2bdb3dSTom St Denis #define DC_LUT_BLACK_OFFSET_RED__DC_LUT_BLACK_OFFSET_RED_MASK 0x0000ffffL 4860de2bdb3dSTom St Denis #define DC_LUT_BLACK_OFFSET_RED__DC_LUT_BLACK_OFFSET_RED__SHIFT 0x00000000 4861de2bdb3dSTom St Denis #define DC_LUT_CONTROL__DC_LUT_DATA_B_FLOAT_POINT_EN_MASK 0x00000020L 4862de2bdb3dSTom St Denis #define DC_LUT_CONTROL__DC_LUT_DATA_B_FLOAT_POINT_EN__SHIFT 0x00000005 4863de2bdb3dSTom St Denis #define DC_LUT_CONTROL__DC_LUT_DATA_B_FORMAT_MASK 0x000000c0L 4864de2bdb3dSTom St Denis #define DC_LUT_CONTROL__DC_LUT_DATA_B_FORMAT__SHIFT 0x00000006 4865de2bdb3dSTom St Denis #define DC_LUT_CONTROL__DC_LUT_DATA_B_SIGNED_EN_MASK 0x00000010L 4866de2bdb3dSTom St Denis #define DC_LUT_CONTROL__DC_LUT_DATA_B_SIGNED_EN__SHIFT 0x00000004 4867de2bdb3dSTom St Denis #define DC_LUT_CONTROL__DC_LUT_DATA_G_FLOAT_POINT_EN_MASK 0x00002000L 4868de2bdb3dSTom St Denis #define DC_LUT_CONTROL__DC_LUT_DATA_G_FLOAT_POINT_EN__SHIFT 0x0000000d 4869de2bdb3dSTom St Denis #define DC_LUT_CONTROL__DC_LUT_DATA_G_FORMAT_MASK 0x0000c000L 4870de2bdb3dSTom St Denis #define DC_LUT_CONTROL__DC_LUT_DATA_G_FORMAT__SHIFT 0x0000000e 4871de2bdb3dSTom St Denis #define DC_LUT_CONTROL__DC_LUT_DATA_G_SIGNED_EN_MASK 0x00001000L 4872de2bdb3dSTom St Denis #define DC_LUT_CONTROL__DC_LUT_DATA_G_SIGNED_EN__SHIFT 0x0000000c 4873de2bdb3dSTom St Denis #define DC_LUT_CONTROL__DC_LUT_DATA_R_FLOAT_POINT_EN_MASK 0x00200000L 4874de2bdb3dSTom St Denis #define DC_LUT_CONTROL__DC_LUT_DATA_R_FLOAT_POINT_EN__SHIFT 0x00000015 4875de2bdb3dSTom St Denis #define DC_LUT_CONTROL__DC_LUT_DATA_R_FORMAT_MASK 0x00c00000L 4876de2bdb3dSTom St Denis #define DC_LUT_CONTROL__DC_LUT_DATA_R_FORMAT__SHIFT 0x00000016 4877de2bdb3dSTom St Denis #define DC_LUT_CONTROL__DC_LUT_DATA_R_SIGNED_EN_MASK 0x00100000L 4878de2bdb3dSTom St Denis #define DC_LUT_CONTROL__DC_LUT_DATA_R_SIGNED_EN__SHIFT 0x00000014 4879de2bdb3dSTom St Denis #define DC_LUT_CONTROL__DC_LUT_INC_B_MASK 0x0000000fL 4880de2bdb3dSTom St Denis #define DC_LUT_CONTROL__DC_LUT_INC_B__SHIFT 0x00000000 4881de2bdb3dSTom St Denis #define DC_LUT_CONTROL__DC_LUT_INC_G_MASK 0x00000f00L 4882de2bdb3dSTom St Denis #define DC_LUT_CONTROL__DC_LUT_INC_G__SHIFT 0x00000008 4883de2bdb3dSTom St Denis #define DC_LUT_CONTROL__DC_LUT_INC_R_MASK 0x000f0000L 4884de2bdb3dSTom St Denis #define DC_LUT_CONTROL__DC_LUT_INC_R__SHIFT 0x00000010 4885de2bdb3dSTom St Denis #define DC_LUT_PWL_DATA__DC_LUT_BASE_MASK 0x0000ffffL 4886de2bdb3dSTom St Denis #define DC_LUT_PWL_DATA__DC_LUT_BASE__SHIFT 0x00000000 4887de2bdb3dSTom St Denis #define DC_LUT_PWL_DATA__DC_LUT_DELTA_MASK 0xffff0000L 4888de2bdb3dSTom St Denis #define DC_LUT_PWL_DATA__DC_LUT_DELTA__SHIFT 0x00000010 4889de2bdb3dSTom St Denis #define DC_LUT_RW_INDEX__DC_LUT_RW_INDEX_MASK 0x000000ffL 4890de2bdb3dSTom St Denis #define DC_LUT_RW_INDEX__DC_LUT_RW_INDEX__SHIFT 0x00000000 4891de2bdb3dSTom St Denis #define DC_LUT_RW_MODE__DC_LUT_RW_MODE_MASK 0x00000001L 4892de2bdb3dSTom St Denis #define DC_LUT_RW_MODE__DC_LUT_RW_MODE__SHIFT 0x00000000 4893de2bdb3dSTom St Denis #define DC_LUT_SEQ_COLOR__DC_LUT_SEQ_COLOR_MASK 0x0000ffffL 4894de2bdb3dSTom St Denis #define DC_LUT_SEQ_COLOR__DC_LUT_SEQ_COLOR__SHIFT 0x00000000 4895de2bdb3dSTom St Denis #define DC_LUT_VGA_ACCESS_ENABLE__DC_LUT_VGA_ACCESS_ENABLE_MASK 0x00000001L 4896de2bdb3dSTom St Denis #define DC_LUT_VGA_ACCESS_ENABLE__DC_LUT_VGA_ACCESS_ENABLE__SHIFT 0x00000000 4897de2bdb3dSTom St Denis #define DC_LUT_WHITE_OFFSET_BLUE__DC_LUT_WHITE_OFFSET_BLUE_MASK 0x0000ffffL 4898de2bdb3dSTom St Denis #define DC_LUT_WHITE_OFFSET_BLUE__DC_LUT_WHITE_OFFSET_BLUE__SHIFT 0x00000000 4899de2bdb3dSTom St Denis #define DC_LUT_WHITE_OFFSET_GREEN__DC_LUT_WHITE_OFFSET_GREEN_MASK 0x0000ffffL 4900de2bdb3dSTom St Denis #define DC_LUT_WHITE_OFFSET_GREEN__DC_LUT_WHITE_OFFSET_GREEN__SHIFT 0x00000000 4901de2bdb3dSTom St Denis #define DC_LUT_WHITE_OFFSET_RED__DC_LUT_WHITE_OFFSET_RED_MASK 0x0000ffffL 4902de2bdb3dSTom St Denis #define DC_LUT_WHITE_OFFSET_RED__DC_LUT_WHITE_OFFSET_RED__SHIFT 0x00000000 4903de2bdb3dSTom St Denis #define DC_LUT_WRITE_EN_MASK__DC_LUT_WRITE_EN_MASK_MASK 0x00000007L 4904de2bdb3dSTom St Denis #define DC_LUT_WRITE_EN_MASK__DC_LUT_WRITE_EN_MASK__SHIFT 0x00000000 4905de2bdb3dSTom St Denis #define DC_MVP_LB_CONTROL__DC_MVP_SPARE_FLOPS_MASK 0x80000000L 4906de2bdb3dSTom St Denis #define DC_MVP_LB_CONTROL__DC_MVP_SPARE_FLOPS__SHIFT 0x0000001f 4907de2bdb3dSTom St Denis #define DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_IN_CAP_MASK 0x10000000L 4908de2bdb3dSTom St Denis #define DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_IN_CAP__SHIFT 0x0000001c 4909de2bdb3dSTom St Denis #define DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_OUT_FORCE_ONE_MASK 0x00001000L 4910de2bdb3dSTom St Denis #define DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_OUT_FORCE_ONE__SHIFT 0x0000000c 4911de2bdb3dSTom St Denis #define DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_OUT_FORCE_ZERO_MASK 0x00010000L 4912de2bdb3dSTom St Denis #define DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_OUT_FORCE_ZERO__SHIFT 0x00000010 4913de2bdb3dSTom St Denis #define DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_OUT_SEL_MASK 0x00000100L 4914de2bdb3dSTom St Denis #define DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_OUT_SEL__SHIFT 0x00000008 4915de2bdb3dSTom St Denis #define DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_STATUS_MASK 0x00100000L 4916de2bdb3dSTom St Denis #define DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_STATUS__SHIFT 0x00000014 4917de2bdb3dSTom St Denis #define DC_MVP_LB_CONTROL__MVP_SWAP_LOCK_IN_MODE_MASK 0x00000003L 4918de2bdb3dSTom St Denis #define DC_MVP_LB_CONTROL__MVP_SWAP_LOCK_IN_MODE__SHIFT 0x00000000 4919de2bdb3dSTom St Denis #define DCO_CLK_CNTL__DCO_TEST_CLK_SEL_MASK 0x0000001fL 4920de2bdb3dSTom St Denis #define DCO_CLK_CNTL__DCO_TEST_CLK_SEL__SHIFT 0x00000000 4921de2bdb3dSTom St Denis #define DCO_CLK_CNTL__DISPCLK_G_ABM_GATE_DIS_MASK 0x00000040L 4922de2bdb3dSTom St Denis #define DCO_CLK_CNTL__DISPCLK_G_ABM_GATE_DIS__SHIFT 0x00000006 4923de2bdb3dSTom St Denis #define DCO_CLK_CNTL__DISPCLK_G_DACA_GATE_DIS_MASK 0x00000100L 4924de2bdb3dSTom St Denis #define DCO_CLK_CNTL__DISPCLK_G_DACA_GATE_DIS__SHIFT 0x00000008 4925de2bdb3dSTom St Denis #define DCO_CLK_CNTL__DISPCLK_G_DACB_GATE_DIS_MASK 0x00000200L 4926de2bdb3dSTom St Denis #define DCO_CLK_CNTL__DISPCLK_G_DACB_GATE_DIS__SHIFT 0x00000009 4927de2bdb3dSTom St Denis #define DCO_CLK_CNTL__DISPCLK_G_DIGA_GATE_DIS_MASK 0x01000000L 4928de2bdb3dSTom St Denis #define DCO_CLK_CNTL__DISPCLK_G_DIGA_GATE_DIS__SHIFT 0x00000018 4929de2bdb3dSTom St Denis #define DCO_CLK_CNTL__DISPCLK_G_DIGB_GATE_DIS_MASK 0x02000000L 4930de2bdb3dSTom St Denis #define DCO_CLK_CNTL__DISPCLK_G_DIGB_GATE_DIS__SHIFT 0x00000019 4931de2bdb3dSTom St Denis #define DCO_CLK_CNTL__DISPCLK_G_DIGC_GATE_DIS_MASK 0x04000000L 4932de2bdb3dSTom St Denis #define DCO_CLK_CNTL__DISPCLK_G_DIGC_GATE_DIS__SHIFT 0x0000001a 4933de2bdb3dSTom St Denis #define DCO_CLK_CNTL__DISPCLK_G_DIGD_GATE_DIS_MASK 0x08000000L 4934de2bdb3dSTom St Denis #define DCO_CLK_CNTL__DISPCLK_G_DIGD_GATE_DIS__SHIFT 0x0000001b 4935de2bdb3dSTom St Denis #define DCO_CLK_CNTL__DISPCLK_G_DIGE_GATE_DIS_MASK 0x10000000L 4936de2bdb3dSTom St Denis #define DCO_CLK_CNTL__DISPCLK_G_DIGE_GATE_DIS__SHIFT 0x0000001c 4937de2bdb3dSTom St Denis #define DCO_CLK_CNTL__DISPCLK_G_DIGF_GATE_DIS_MASK 0x20000000L 4938de2bdb3dSTom St Denis #define DCO_CLK_CNTL__DISPCLK_G_DIGF_GATE_DIS__SHIFT 0x0000001d 4939de2bdb3dSTom St Denis #define DCO_CLK_CNTL__DISPCLK_G_DVO_GATE_DIS_MASK 0x00000080L 4940de2bdb3dSTom St Denis #define DCO_CLK_CNTL__DISPCLK_G_DVO_GATE_DIS__SHIFT 0x00000007 4941de2bdb3dSTom St Denis #define DCO_CLK_CNTL__DISPCLK_G_FMT0_GATE_DIS_MASK 0x00010000L 4942de2bdb3dSTom St Denis #define DCO_CLK_CNTL__DISPCLK_G_FMT0_GATE_DIS__SHIFT 0x00000010 4943de2bdb3dSTom St Denis #define DCO_CLK_CNTL__DISPCLK_G_FMT1_GATE_DIS_MASK 0x00020000L 4944de2bdb3dSTom St Denis #define DCO_CLK_CNTL__DISPCLK_G_FMT1_GATE_DIS__SHIFT 0x00000011 4945de2bdb3dSTom St Denis #define DCO_CLK_CNTL__DISPCLK_G_FMT2_GATE_DIS_MASK 0x00040000L 4946de2bdb3dSTom St Denis #define DCO_CLK_CNTL__DISPCLK_G_FMT2_GATE_DIS__SHIFT 0x00000012 4947de2bdb3dSTom St Denis #define DCO_CLK_CNTL__DISPCLK_G_FMT3_GATE_DIS_MASK 0x00080000L 4948de2bdb3dSTom St Denis #define DCO_CLK_CNTL__DISPCLK_G_FMT3_GATE_DIS__SHIFT 0x00000013 4949de2bdb3dSTom St Denis #define DCO_CLK_CNTL__DISPCLK_G_FMT4_GATE_DIS_MASK 0x00100000L 4950de2bdb3dSTom St Denis #define DCO_CLK_CNTL__DISPCLK_G_FMT4_GATE_DIS__SHIFT 0x00000014 4951de2bdb3dSTom St Denis #define DCO_CLK_CNTL__DISPCLK_G_FMT5_GATE_DIS_MASK 0x00200000L 4952de2bdb3dSTom St Denis #define DCO_CLK_CNTL__DISPCLK_G_FMT5_GATE_DIS__SHIFT 0x00000015 4953de2bdb3dSTom St Denis #define DCO_CLK_CNTL__DISPCLK_R_ABM_GATE_DIS_MASK 0x00001000L 4954de2bdb3dSTom St Denis #define DCO_CLK_CNTL__DISPCLK_R_ABM_GATE_DIS__SHIFT 0x0000000c 4955de2bdb3dSTom St Denis #define DCO_CLK_CNTL__DISPCLK_R_DCO_GATE_DIS_MASK 0x00000020L 4956de2bdb3dSTom St Denis #define DCO_CLK_CNTL__DISPCLK_R_DCO_GATE_DIS__SHIFT 0x00000005 4957de2bdb3dSTom St Denis #define DCO_CLK_RAMP_CNTL__DISPCLK_G_ABM_RAMP_DIS_MASK 0x00000040L 4958de2bdb3dSTom St Denis #define DCO_CLK_RAMP_CNTL__DISPCLK_G_ABM_RAMP_DIS__SHIFT 0x00000006 4959de2bdb3dSTom St Denis #define DCO_CLK_RAMP_CNTL__DISPCLK_G_DACA_RAMP_DIS_MASK 0x00000100L 4960de2bdb3dSTom St Denis #define DCO_CLK_RAMP_CNTL__DISPCLK_G_DACA_RAMP_DIS__SHIFT 0x00000008 4961de2bdb3dSTom St Denis #define DCO_CLK_RAMP_CNTL__DISPCLK_G_DACB_RAMP_DIS_MASK 0x00000200L 4962de2bdb3dSTom St Denis #define DCO_CLK_RAMP_CNTL__DISPCLK_G_DACB_RAMP_DIS__SHIFT 0x00000009 4963de2bdb3dSTom St Denis #define DCO_CLK_RAMP_CNTL__DISPCLK_G_DIGA_RAMP_DIS_MASK 0x01000000L 4964de2bdb3dSTom St Denis #define DCO_CLK_RAMP_CNTL__DISPCLK_G_DIGA_RAMP_DIS__SHIFT 0x00000018 4965de2bdb3dSTom St Denis #define DCO_CLK_RAMP_CNTL__DISPCLK_G_DIGB_RAMP_DIS_MASK 0x02000000L 4966de2bdb3dSTom St Denis #define DCO_CLK_RAMP_CNTL__DISPCLK_G_DIGB_RAMP_DIS__SHIFT 0x00000019 4967de2bdb3dSTom St Denis #define DCO_CLK_RAMP_CNTL__DISPCLK_G_DIGC_RAMP_DIS_MASK 0x04000000L 4968de2bdb3dSTom St Denis #define DCO_CLK_RAMP_CNTL__DISPCLK_G_DIGC_RAMP_DIS__SHIFT 0x0000001a 4969de2bdb3dSTom St Denis #define DCO_CLK_RAMP_CNTL__DISPCLK_G_DIGD_RAMP_DIS_MASK 0x08000000L 4970de2bdb3dSTom St Denis #define DCO_CLK_RAMP_CNTL__DISPCLK_G_DIGD_RAMP_DIS__SHIFT 0x0000001b 4971de2bdb3dSTom St Denis #define DCO_CLK_RAMP_CNTL__DISPCLK_G_DIGE_RAMP_DIS_MASK 0x10000000L 4972de2bdb3dSTom St Denis #define DCO_CLK_RAMP_CNTL__DISPCLK_G_DIGE_RAMP_DIS__SHIFT 0x0000001c 4973de2bdb3dSTom St Denis #define DCO_CLK_RAMP_CNTL__DISPCLK_G_DIGF_RAMP_DIS_MASK 0x20000000L 4974de2bdb3dSTom St Denis #define DCO_CLK_RAMP_CNTL__DISPCLK_G_DIGF_RAMP_DIS__SHIFT 0x0000001d 4975de2bdb3dSTom St Denis #define DCO_CLK_RAMP_CNTL__DISPCLK_G_DVO_RAMP_DIS_MASK 0x00000080L 4976de2bdb3dSTom St Denis #define DCO_CLK_RAMP_CNTL__DISPCLK_G_DVO_RAMP_DIS__SHIFT 0x00000007 4977de2bdb3dSTom St Denis #define DCO_CLK_RAMP_CNTL__DISPCLK_G_FMT0_RAMP_DIS_MASK 0x00010000L 4978de2bdb3dSTom St Denis #define DCO_CLK_RAMP_CNTL__DISPCLK_G_FMT0_RAMP_DIS__SHIFT 0x00000010 4979de2bdb3dSTom St Denis #define DCO_CLK_RAMP_CNTL__DISPCLK_G_FMT1_RAMP_DIS_MASK 0x00020000L 4980de2bdb3dSTom St Denis #define DCO_CLK_RAMP_CNTL__DISPCLK_G_FMT1_RAMP_DIS__SHIFT 0x00000011 4981de2bdb3dSTom St Denis #define DCO_CLK_RAMP_CNTL__DISPCLK_G_FMT2_RAMP_DIS_MASK 0x00040000L 4982de2bdb3dSTom St Denis #define DCO_CLK_RAMP_CNTL__DISPCLK_G_FMT2_RAMP_DIS__SHIFT 0x00000012 4983de2bdb3dSTom St Denis #define DCO_CLK_RAMP_CNTL__DISPCLK_G_FMT3_RAMP_DIS_MASK 0x00080000L 4984de2bdb3dSTom St Denis #define DCO_CLK_RAMP_CNTL__DISPCLK_G_FMT3_RAMP_DIS__SHIFT 0x00000013 4985de2bdb3dSTom St Denis #define DCO_CLK_RAMP_CNTL__DISPCLK_G_FMT4_RAMP_DIS_MASK 0x00100000L 4986de2bdb3dSTom St Denis #define DCO_CLK_RAMP_CNTL__DISPCLK_G_FMT4_RAMP_DIS__SHIFT 0x00000014 4987de2bdb3dSTom St Denis #define DCO_CLK_RAMP_CNTL__DISPCLK_G_FMT5_RAMP_DIS_MASK 0x00200000L 4988de2bdb3dSTom St Denis #define DCO_CLK_RAMP_CNTL__DISPCLK_G_FMT5_RAMP_DIS__SHIFT 0x00000015 4989de2bdb3dSTom St Denis #define DCO_CLK_RAMP_CNTL__DISPCLK_R_ABM_RAMP_DIS_MASK 0x00001000L 4990de2bdb3dSTom St Denis #define DCO_CLK_RAMP_CNTL__DISPCLK_R_ABM_RAMP_DIS__SHIFT 0x0000000c 4991de2bdb3dSTom St Denis #define DCO_CLK_RAMP_CNTL__DISPCLK_R_DCO_RAMP_DIS_MASK 0x00000020L 4992de2bdb3dSTom St Denis #define DCO_CLK_RAMP_CNTL__DISPCLK_R_DCO_RAMP_DIS__SHIFT 0x00000005 4993de2bdb3dSTom St Denis #define DCO_LIGHT_SLEEP_DIS__DPA_LIGHT_SLEEP_DIS_MASK 0x00000008L 4994de2bdb3dSTom St Denis #define DCO_LIGHT_SLEEP_DIS__DPA_LIGHT_SLEEP_DIS__SHIFT 0x00000003 4995de2bdb3dSTom St Denis #define DCO_LIGHT_SLEEP_DIS__DPA_MEM_SHUTDOWN_DIS_MASK 0x00020000L 4996de2bdb3dSTom St Denis #define DCO_LIGHT_SLEEP_DIS__DPA_MEM_SHUTDOWN_DIS__SHIFT 0x00000011 4997de2bdb3dSTom St Denis #define DCO_LIGHT_SLEEP_DIS__DPB_LIGHT_SLEEP_DIS_MASK 0x00000010L 4998de2bdb3dSTom St Denis #define DCO_LIGHT_SLEEP_DIS__DPB_LIGHT_SLEEP_DIS__SHIFT 0x00000004 4999de2bdb3dSTom St Denis #define DCO_LIGHT_SLEEP_DIS__DPB_MEM_SHUTDOWN_DIS_MASK 0x00040000L 5000de2bdb3dSTom St Denis #define DCO_LIGHT_SLEEP_DIS__DPB_MEM_SHUTDOWN_DIS__SHIFT 0x00000012 5001de2bdb3dSTom St Denis #define DCO_LIGHT_SLEEP_DIS__DPC_LIGHT_SLEEP_DIS_MASK 0x00000020L 5002de2bdb3dSTom St Denis #define DCO_LIGHT_SLEEP_DIS__DPC_LIGHT_SLEEP_DIS__SHIFT 0x00000005 5003de2bdb3dSTom St Denis #define DCO_LIGHT_SLEEP_DIS__DPC_MEM_SHUTDOWN_DIS_MASK 0x00080000L 5004de2bdb3dSTom St Denis #define DCO_LIGHT_SLEEP_DIS__DPC_MEM_SHUTDOWN_DIS__SHIFT 0x00000013 5005de2bdb3dSTom St Denis #define DCO_LIGHT_SLEEP_DIS__DPD_LIGHT_SLEEP_DIS_MASK 0x00000040L 5006de2bdb3dSTom St Denis #define DCO_LIGHT_SLEEP_DIS__DPD_LIGHT_SLEEP_DIS__SHIFT 0x00000006 5007de2bdb3dSTom St Denis #define DCO_LIGHT_SLEEP_DIS__DPD_MEM_SHUTDOWN_DIS_MASK 0x00100000L 5008de2bdb3dSTom St Denis #define DCO_LIGHT_SLEEP_DIS__DPD_MEM_SHUTDOWN_DIS__SHIFT 0x00000014 5009de2bdb3dSTom St Denis #define DCO_LIGHT_SLEEP_DIS__DPE_LIGHT_SLEEP_DIS_MASK 0x00000080L 5010de2bdb3dSTom St Denis #define DCO_LIGHT_SLEEP_DIS__DPE_LIGHT_SLEEP_DIS__SHIFT 0x00000007 5011de2bdb3dSTom St Denis #define DCO_LIGHT_SLEEP_DIS__DPE_MEM_SHUTDOWN_DIS_MASK 0x00200000L 5012de2bdb3dSTom St Denis #define DCO_LIGHT_SLEEP_DIS__DPE_MEM_SHUTDOWN_DIS__SHIFT 0x00000015 5013de2bdb3dSTom St Denis #define DCO_LIGHT_SLEEP_DIS__DPF_LIGHT_SLEEP_DIS_MASK 0x00000100L 5014de2bdb3dSTom St Denis #define DCO_LIGHT_SLEEP_DIS__DPF_LIGHT_SLEEP_DIS__SHIFT 0x00000008 5015de2bdb3dSTom St Denis #define DCO_LIGHT_SLEEP_DIS__DPF_MEM_SHUTDOWN_DIS_MASK 0x00400000L 5016de2bdb3dSTom St Denis #define DCO_LIGHT_SLEEP_DIS__DPF_MEM_SHUTDOWN_DIS__SHIFT 0x00000016 5017de2bdb3dSTom St Denis #define DCO_LIGHT_SLEEP_DIS__HDMI0_LIGHT_SLEEP_DIS_MASK 0x00000200L 5018de2bdb3dSTom St Denis #define DCO_LIGHT_SLEEP_DIS__HDMI0_LIGHT_SLEEP_DIS__SHIFT 0x00000009 5019de2bdb3dSTom St Denis #define DCO_LIGHT_SLEEP_DIS__HDMI1_LIGHT_SLEEP_DIS_MASK 0x00000400L 5020de2bdb3dSTom St Denis #define DCO_LIGHT_SLEEP_DIS__HDMI1_LIGHT_SLEEP_DIS__SHIFT 0x0000000a 5021de2bdb3dSTom St Denis #define DCO_LIGHT_SLEEP_DIS__HDMI2_LIGHT_SLEEP_DIS_MASK 0x00000800L 5022de2bdb3dSTom St Denis #define DCO_LIGHT_SLEEP_DIS__HDMI2_LIGHT_SLEEP_DIS__SHIFT 0x0000000b 5023de2bdb3dSTom St Denis #define DCO_LIGHT_SLEEP_DIS__HDMI3_LIGHT_SLEEP_DIS_MASK 0x00001000L 5024de2bdb3dSTom St Denis #define DCO_LIGHT_SLEEP_DIS__HDMI3_LIGHT_SLEEP_DIS__SHIFT 0x0000000c 5025de2bdb3dSTom St Denis #define DCO_LIGHT_SLEEP_DIS__HDMI4_LIGHT_SLEEP_DIS_MASK 0x00002000L 5026de2bdb3dSTom St Denis #define DCO_LIGHT_SLEEP_DIS__HDMI4_LIGHT_SLEEP_DIS__SHIFT 0x0000000d 5027de2bdb3dSTom St Denis #define DCO_LIGHT_SLEEP_DIS__HDMI5_LIGHT_SLEEP_DIS_MASK 0x00004000L 5028de2bdb3dSTom St Denis #define DCO_LIGHT_SLEEP_DIS__HDMI5_LIGHT_SLEEP_DIS__SHIFT 0x0000000e 5029de2bdb3dSTom St Denis #define DCO_LIGHT_SLEEP_DIS__I2C_LIGHT_SLEEP_FORCE_MASK 0x00000002L 5030de2bdb3dSTom St Denis #define DCO_LIGHT_SLEEP_DIS__I2C_LIGHT_SLEEP_FORCE__SHIFT 0x00000001 5031de2bdb3dSTom St Denis #define DCO_LIGHT_SLEEP_DIS__MVP_LIGHT_SLEEP_DIS_MASK 0x00000004L 5032de2bdb3dSTom St Denis #define DCO_LIGHT_SLEEP_DIS__MVP_LIGHT_SLEEP_DIS__SHIFT 0x00000002 5033de2bdb3dSTom St Denis #define DCO_LIGHT_SLEEP_DIS__MVP_MEM_SHUTDOWN_DIS_MASK 0x00010000L 5034de2bdb3dSTom St Denis #define DCO_LIGHT_SLEEP_DIS__MVP_MEM_SHUTDOWN_DIS__SHIFT 0x00000010 5035de2bdb3dSTom St Denis #define DCO_LIGHT_SLEEP_DIS__TVOUT_LIGHT_SLEEP_DIS_MASK 0x00000001L 5036de2bdb3dSTom St Denis #define DCO_LIGHT_SLEEP_DIS__TVOUT_LIGHT_SLEEP_DIS__SHIFT 0x00000000 5037de2bdb3dSTom St Denis #define DCO_MEM_POWER_STATE__DPA_MEM_PWR_STATE_MASK 0x000000c0L 5038de2bdb3dSTom St Denis #define DCO_MEM_POWER_STATE__DPA_MEM_PWR_STATE__SHIFT 0x00000006 5039de2bdb3dSTom St Denis #define DCO_MEM_POWER_STATE__DPB_MEM_PWR_STATE_MASK 0x00000300L 5040de2bdb3dSTom St Denis #define DCO_MEM_POWER_STATE__DPB_MEM_PWR_STATE__SHIFT 0x00000008 5041de2bdb3dSTom St Denis #define DCO_MEM_POWER_STATE__DPC_MEM_PWR_STATE_MASK 0x00000c00L 5042de2bdb3dSTom St Denis #define DCO_MEM_POWER_STATE__DPC_MEM_PWR_STATE__SHIFT 0x0000000a 5043de2bdb3dSTom St Denis #define DCO_MEM_POWER_STATE__DPD_MEM_PWR_STATE_MASK 0x00003000L 5044de2bdb3dSTom St Denis #define DCO_MEM_POWER_STATE__DPD_MEM_PWR_STATE__SHIFT 0x0000000c 5045de2bdb3dSTom St Denis #define DCO_MEM_POWER_STATE__DPE_MEM_PWR_STATE_MASK 0x0000c000L 5046de2bdb3dSTom St Denis #define DCO_MEM_POWER_STATE__DPE_MEM_PWR_STATE__SHIFT 0x0000000e 5047de2bdb3dSTom St Denis #define DCO_MEM_POWER_STATE__DPF_MEM_PWR_STATE_MASK 0x00030000L 5048de2bdb3dSTom St Denis #define DCO_MEM_POWER_STATE__DPF_MEM_PWR_STATE__SHIFT 0x00000010 5049de2bdb3dSTom St Denis #define DCO_MEM_POWER_STATE__HDMI0_MEM_PWR_STATE_MASK 0x000c0000L 5050de2bdb3dSTom St Denis #define DCO_MEM_POWER_STATE__HDMI0_MEM_PWR_STATE__SHIFT 0x00000012 5051de2bdb3dSTom St Denis #define DCO_MEM_POWER_STATE__HDMI1_MEM_PWR_STATE_MASK 0x00300000L 5052de2bdb3dSTom St Denis #define DCO_MEM_POWER_STATE__HDMI1_MEM_PWR_STATE__SHIFT 0x00000014 5053de2bdb3dSTom St Denis #define DCO_MEM_POWER_STATE__HDMI2_MEM_PWR_STATE_MASK 0x00c00000L 5054de2bdb3dSTom St Denis #define DCO_MEM_POWER_STATE__HDMI2_MEM_PWR_STATE__SHIFT 0x00000016 5055de2bdb3dSTom St Denis #define DCO_MEM_POWER_STATE__HDMI3_MEM_PWR_STATE_MASK 0x03000000L 5056de2bdb3dSTom St Denis #define DCO_MEM_POWER_STATE__HDMI3_MEM_PWR_STATE__SHIFT 0x00000018 5057de2bdb3dSTom St Denis #define DCO_MEM_POWER_STATE__HDMI4_MEM_PWR_STATE_MASK 0x0c000000L 5058de2bdb3dSTom St Denis #define DCO_MEM_POWER_STATE__HDMI4_MEM_PWR_STATE__SHIFT 0x0000001a 5059de2bdb3dSTom St Denis #define DCO_MEM_POWER_STATE__HDMI5_MEM_PWR_STATE_MASK 0x30000000L 5060de2bdb3dSTom St Denis #define DCO_MEM_POWER_STATE__HDMI5_MEM_PWR_STATE__SHIFT 0x0000001c 5061de2bdb3dSTom St Denis #define DCO_MEM_POWER_STATE__I2C_MEM_PWR_STATE_MASK 0x0000000cL 5062de2bdb3dSTom St Denis #define DCO_MEM_POWER_STATE__I2C_MEM_PWR_STATE__SHIFT 0x00000002 5063de2bdb3dSTom St Denis #define DCO_MEM_POWER_STATE__MVP_MEM_PWR_STATE_MASK 0x00000030L 5064de2bdb3dSTom St Denis #define DCO_MEM_POWER_STATE__MVP_MEM_PWR_STATE__SHIFT 0x00000004 5065de2bdb3dSTom St Denis #define DCO_MEM_POWER_STATE__TVOUT_MEM_PWR_STATE_MASK 0x00000003L 5066de2bdb3dSTom St Denis #define DCO_MEM_POWER_STATE__TVOUT_MEM_PWR_STATE__SHIFT 0x00000000 5067de2bdb3dSTom St Denis #define DCO_SOFT_RESET__ABM_SOFT_RESET_MASK 0x02000000L 5068de2bdb3dSTom St Denis #define DCO_SOFT_RESET__ABM_SOFT_RESET__SHIFT 0x00000019 5069de2bdb3dSTom St Denis #define DCO_SOFT_RESET__DACA_CFG_IF_SOFT_RESET_MASK 0x20000000L 5070de2bdb3dSTom St Denis #define DCO_SOFT_RESET__DACA_CFG_IF_SOFT_RESET__SHIFT 0x0000001d 5071de2bdb3dSTom St Denis #define DCO_SOFT_RESET__DACA_SOFT_RESET_MASK 0x00000001L 5072de2bdb3dSTom St Denis #define DCO_SOFT_RESET__DACA_SOFT_RESET__SHIFT 0x00000000 5073de2bdb3dSTom St Denis #define DCO_SOFT_RESET__DACB_SOFT_RESET_MASK 0x00000002L 5074de2bdb3dSTom St Denis #define DCO_SOFT_RESET__DACB_SOFT_RESET__SHIFT 0x00000001 5075de2bdb3dSTom St Denis #define DCO_SOFT_RESET__DVO_ENABLE_RST_MASK 0x00000008L 5076de2bdb3dSTom St Denis #define DCO_SOFT_RESET__DVO_ENABLE_RST__SHIFT 0x00000003 5077de2bdb3dSTom St Denis #define DCO_SOFT_RESET__DVO_SOFT_RESET_MASK 0x08000000L 5078de2bdb3dSTom St Denis #define DCO_SOFT_RESET__DVO_SOFT_RESET__SHIFT 0x0000001b 5079de2bdb3dSTom St Denis #define DCO_SOFT_RESET__FMT0_SOFT_RESET_MASK 0x00010000L 5080de2bdb3dSTom St Denis #define DCO_SOFT_RESET__FMT0_SOFT_RESET__SHIFT 0x00000010 5081de2bdb3dSTom St Denis #define DCO_SOFT_RESET__FMT1_SOFT_RESET_MASK 0x00020000L 5082de2bdb3dSTom St Denis #define DCO_SOFT_RESET__FMT1_SOFT_RESET__SHIFT 0x00000011 5083de2bdb3dSTom St Denis #define DCO_SOFT_RESET__FMT2_SOFT_RESET_MASK 0x00040000L 5084de2bdb3dSTom St Denis #define DCO_SOFT_RESET__FMT2_SOFT_RESET__SHIFT 0x00000012 5085de2bdb3dSTom St Denis #define DCO_SOFT_RESET__FMT3_SOFT_RESET_MASK 0x00080000L 5086de2bdb3dSTom St Denis #define DCO_SOFT_RESET__FMT3_SOFT_RESET__SHIFT 0x00000013 5087de2bdb3dSTom St Denis #define DCO_SOFT_RESET__FMT4_SOFT_RESET_MASK 0x00100000L 5088de2bdb3dSTom St Denis #define DCO_SOFT_RESET__FMT4_SOFT_RESET__SHIFT 0x00000014 5089de2bdb3dSTom St Denis #define DCO_SOFT_RESET__FMT5_SOFT_RESET_MASK 0x00200000L 5090de2bdb3dSTom St Denis #define DCO_SOFT_RESET__FMT5_SOFT_RESET__SHIFT 0x00000015 5091de2bdb3dSTom St Denis #define DCO_SOFT_RESET__MVP_SOFT_RESET_MASK 0x01000000L 5092de2bdb3dSTom St Denis #define DCO_SOFT_RESET__MVP_SOFT_RESET__SHIFT 0x00000018 5093de2bdb3dSTom St Denis #define DCO_SOFT_RESET__SOFT_RESET_DVO_MASK 0x00000004L 5094de2bdb3dSTom St Denis #define DCO_SOFT_RESET__SOFT_RESET_DVO__SHIFT 0x00000002 5095de2bdb3dSTom St Denis #define DCO_SOFT_RESET__SRBM_SOFT_RESET_ENABLE_MASK 0x10000000L 5096de2bdb3dSTom St Denis #define DCO_SOFT_RESET__SRBM_SOFT_RESET_ENABLE__SHIFT 0x0000001c 5097de2bdb3dSTom St Denis #define DCO_SOFT_RESET__TVOUT_SOFT_RESET_MASK 0x04000000L 5098de2bdb3dSTom St Denis #define DCO_SOFT_RESET__TVOUT_SOFT_RESET__SHIFT 0x0000001a 5099de2bdb3dSTom St Denis #define DC_PAD_EXTERN_SIG__DC_PAD_EXTERN_SIG_SEL_MASK 0x0000000fL 5100de2bdb3dSTom St Denis #define DC_PAD_EXTERN_SIG__DC_PAD_EXTERN_SIG_SEL__SHIFT 0x00000000 5101de2bdb3dSTom St Denis #define DC_PAD_EXTERN_SIG__MVP_PIXEL_SRC_STATUS_MASK 0x00000030L 5102de2bdb3dSTom St Denis #define DC_PAD_EXTERN_SIG__MVP_PIXEL_SRC_STATUS__SHIFT 0x00000004 5103de2bdb3dSTom St Denis #define DCP_CRC_CONTROL__DCP_CRC_ENABLE_MASK 0x00000001L 5104de2bdb3dSTom St Denis #define DCP_CRC_CONTROL__DCP_CRC_ENABLE__SHIFT 0x00000000 5105de2bdb3dSTom St Denis #define DCP_CRC_CONTROL__DCP_CRC_LINE_SEL_MASK 0x00000300L 5106de2bdb3dSTom St Denis #define DCP_CRC_CONTROL__DCP_CRC_LINE_SEL__SHIFT 0x00000008 5107de2bdb3dSTom St Denis #define DCP_CRC_CONTROL__DCP_CRC_SOURCE_SEL_MASK 0x0000001cL 5108de2bdb3dSTom St Denis #define DCP_CRC_CONTROL__DCP_CRC_SOURCE_SEL__SHIFT 0x00000002 5109de2bdb3dSTom St Denis #define DCP_CRC_CURRENT__DCP_CRC_CURRENT_MASK 0xffffffffL 5110de2bdb3dSTom St Denis #define DCP_CRC_CURRENT__DCP_CRC_CURRENT__SHIFT 0x00000000 5111de2bdb3dSTom St Denis #define DCP_CRC_LAST__DCP_CRC_LAST_MASK 0xffffffffL 5112de2bdb3dSTom St Denis #define DCP_CRC_LAST__DCP_CRC_LAST__SHIFT 0x00000000 5113de2bdb3dSTom St Denis #define DCP_CRC_MASK__DCP_CRC_MASK_MASK 0xffffffffL 5114de2bdb3dSTom St Denis #define DCP_CRC_MASK__DCP_CRC_MASK__SHIFT 0x00000000 5115de2bdb3dSTom St Denis #define DCP_DEBUG2__DCP_DEBUG2_MASK 0xffffffffL 5116de2bdb3dSTom St Denis #define DCP_DEBUG2__DCP_DEBUG2__SHIFT 0x00000000 5117de2bdb3dSTom St Denis #define DCP_DEBUG__DCP_DEBUG_MASK 0xffffffffL 5118de2bdb3dSTom St Denis #define DCP_DEBUG__DCP_DEBUG__SHIFT 0x00000000 5119de2bdb3dSTom St Denis #define DCP_FP_CONVERTED_FIELD__DCP_FP_CONVERTED_FIELD_DATA_MASK 0x0003ffffL 5120de2bdb3dSTom St Denis #define DCP_FP_CONVERTED_FIELD__DCP_FP_CONVERTED_FIELD_DATA__SHIFT 0x00000000 5121de2bdb3dSTom St Denis #define DCP_FP_CONVERTED_FIELD__DCP_FP_CONVERTED_FIELD_INDEX_MASK 0x07f00000L 5122de2bdb3dSTom St Denis #define DCP_FP_CONVERTED_FIELD__DCP_FP_CONVERTED_FIELD_INDEX__SHIFT 0x00000014 5123de2bdb3dSTom St Denis #define DC_PGCNTL_STATUS_REG__DCPG_ECO_DEBUG_MASK 0xffff0000L 5124de2bdb3dSTom St Denis #define DC_PGCNTL_STATUS_REG__DCPG_ECO_DEBUG__SHIFT 0x00000010 5125de2bdb3dSTom St Denis #define DC_PGCNTL_STATUS_REG__IPREQ_IGNORE_STATUS_MASK 0x00000004L 5126de2bdb3dSTom St Denis #define DC_PGCNTL_STATUS_REG__IPREQ_IGNORE_STATUS__SHIFT 0x00000002 5127de2bdb3dSTom St Denis #define DC_PGCNTL_STATUS_REG__SWREQ_RWOP_BUSY_MASK 0x00000001L 5128de2bdb3dSTom St Denis #define DC_PGCNTL_STATUS_REG__SWREQ_RWOP_BUSY__SHIFT 0x00000000 5129de2bdb3dSTom St Denis #define DC_PGCNTL_STATUS_REG__SWREQ_RWOP_FORCE_MASK 0x00000002L 5130de2bdb3dSTom St Denis #define DC_PGCNTL_STATUS_REG__SWREQ_RWOP_FORCE__SHIFT 0x00000001 5131de2bdb3dSTom St Denis #define DC_PGFSM_CONFIG_REG__PGFSM_CONFIG_REG_MASK 0xffffffffL 5132de2bdb3dSTom St Denis #define DC_PGFSM_CONFIG_REG__PGFSM_CONFIG_REG__SHIFT 0x00000000 5133de2bdb3dSTom St Denis #define DC_PGFSM_WRITE_REG__PGFSM_WRITE_REG_MASK 0xffffffffL 5134de2bdb3dSTom St Denis #define DC_PGFSM_WRITE_REG__PGFSM_WRITE_REG__SHIFT 0x00000000 5135de2bdb3dSTom St Denis #define DCP_GSL_CONTROL__DCP_GSL0_EN_MASK 0x00000001L 5136de2bdb3dSTom St Denis #define DCP_GSL_CONTROL__DCP_GSL0_EN__SHIFT 0x00000000 5137de2bdb3dSTom St Denis #define DCP_GSL_CONTROL__DCP_GSL1_EN_MASK 0x00000002L 5138de2bdb3dSTom St Denis #define DCP_GSL_CONTROL__DCP_GSL1_EN__SHIFT 0x00000001 5139de2bdb3dSTom St Denis #define DCP_GSL_CONTROL__DCP_GSL2_EN_MASK 0x00000004L 5140de2bdb3dSTom St Denis #define DCP_GSL_CONTROL__DCP_GSL2_EN__SHIFT 0x00000002 5141de2bdb3dSTom St Denis #define DCP_GSL_CONTROL__DCP_GSL_DELAY_SURFACE_UPDATE_PENDING_MASK 0x08000000L 5142de2bdb3dSTom St Denis #define DCP_GSL_CONTROL__DCP_GSL_DELAY_SURFACE_UPDATE_PENDING__SHIFT 0x0000001b 5143de2bdb3dSTom St Denis #define DCP_GSL_CONTROL__DCP_GSL_HSYNC_FLIP_CHECK_DELAY_MASK 0xf0000000L 5144de2bdb3dSTom St Denis #define DCP_GSL_CONTROL__DCP_GSL_HSYNC_FLIP_CHECK_DELAY__SHIFT 0x0000001c 5145de2bdb3dSTom St Denis #define DCP_GSL_CONTROL__DCP_GSL_HSYNC_FLIP_FORCE_DELAY_MASK 0x0000f000L 5146de2bdb3dSTom St Denis #define DCP_GSL_CONTROL__DCP_GSL_HSYNC_FLIP_FORCE_DELAY__SHIFT 0x0000000c 5147de2bdb3dSTom St Denis #define DCP_GSL_CONTROL__DCP_GSL_MASTER_EN_MASK 0x00010000L 5148de2bdb3dSTom St Denis #define DCP_GSL_CONTROL__DCP_GSL_MASTER_EN__SHIFT 0x00000010 5149de2bdb3dSTom St Denis #define DCP_GSL_CONTROL__DCP_GSL_MODE_MASK 0x00000300L 5150de2bdb3dSTom St Denis #define DCP_GSL_CONTROL__DCP_GSL_MODE__SHIFT 0x00000008 5151de2bdb3dSTom St Denis #define DCP_GSL_CONTROL__DCP_GSL_SYNC_SOURCE_MASK 0x03000000L 5152de2bdb3dSTom St Denis #define DCP_GSL_CONTROL__DCP_GSL_SYNC_SOURCE__SHIFT 0x00000018 5153de2bdb3dSTom St Denis #define DCPG_TEST_DEBUG_DATA__DCPG_TEST_DEBUG_DATA_MASK 0xffffffffL 5154de2bdb3dSTom St Denis #define DCPG_TEST_DEBUG_DATA__DCPG_TEST_DEBUG_DATA__SHIFT 0x00000000 5155de2bdb3dSTom St Denis #define DCPG_TEST_DEBUG_INDEX__DCPG_TEST_DEBUG_INDEX_MASK 0x000000ffL 5156de2bdb3dSTom St Denis #define DCPG_TEST_DEBUG_INDEX__DCPG_TEST_DEBUG_INDEX__SHIFT 0x00000000 5157de2bdb3dSTom St Denis #define DCPG_TEST_DEBUG_INDEX__DCPG_TEST_DEBUG_WRITE_EN_MASK 0x00000100L 5158de2bdb3dSTom St Denis #define DCPG_TEST_DEBUG_INDEX__DCPG_TEST_DEBUG_WRITE_EN__SHIFT 0x00000008 5159de2bdb3dSTom St Denis #define DC_PINSTRAPS__DC_PINSTRAPS_AUDIO_MASK 0x0000c000L 5160de2bdb3dSTom St Denis #define DC_PINSTRAPS__DC_PINSTRAPS_AUDIO__SHIFT 0x0000000e 5161de2bdb3dSTom St Denis #define DC_PINSTRAPS__DC_PINSTRAPS_BIF_CEC_DIS_MASK 0x00000400L 5162de2bdb3dSTom St Denis #define DC_PINSTRAPS__DC_PINSTRAPS_BIF_CEC_DIS__SHIFT 0x0000000a 5163de2bdb3dSTom St Denis #define DC_PINSTRAPS__DC_PINSTRAPS_CCBYPASS_MASK 0x00010000L 5164de2bdb3dSTom St Denis #define DC_PINSTRAPS__DC_PINSTRAPS_CCBYPASS__SHIFT 0x00000010 5165de2bdb3dSTom St Denis #define DC_PINSTRAPS__DC_PINSTRAPS_SMS_EN_HARD_MASK 0x00002000L 5166de2bdb3dSTom St Denis #define DC_PINSTRAPS__DC_PINSTRAPS_SMS_EN_HARD__SHIFT 0x0000000d 5167de2bdb3dSTom St Denis #define DC_PINSTRAPS__DC_PINSTRAPS_VIP_DEVICE_MASK 0x00000800L 5168de2bdb3dSTom St Denis #define DC_PINSTRAPS__DC_PINSTRAPS_VIP_DEVICE__SHIFT 0x0000000b 5169de2bdb3dSTom St Denis #define DCP_LB_DATA_GAP_BETWEEN_CHUNK__DCP_LB_GAP_BETWEEN_CHUNK_20BPP_MASK 0x0000000fL 5170de2bdb3dSTom St Denis #define DCP_LB_DATA_GAP_BETWEEN_CHUNK__DCP_LB_GAP_BETWEEN_CHUNK_20BPP__SHIFT 0x00000000 5171de2bdb3dSTom St Denis #define DCP_LB_DATA_GAP_BETWEEN_CHUNK__DCP_LB_GAP_BETWEEN_CHUNK_30BPP_MASK 0x000000f0L 5172de2bdb3dSTom St Denis #define DCP_LB_DATA_GAP_BETWEEN_CHUNK__DCP_LB_GAP_BETWEEN_CHUNK_30BPP__SHIFT 0x00000004 5173de2bdb3dSTom St Denis #define DCP_RANDOM_SEEDS__DCP_RAND_B_SEED_MASK 0x00ff0000L 5174de2bdb3dSTom St Denis #define DCP_RANDOM_SEEDS__DCP_RAND_B_SEED__SHIFT 0x00000010 5175de2bdb3dSTom St Denis #define DCP_RANDOM_SEEDS__DCP_RAND_G_SEED_MASK 0x0000ff00L 5176de2bdb3dSTom St Denis #define DCP_RANDOM_SEEDS__DCP_RAND_G_SEED__SHIFT 0x00000008 5177de2bdb3dSTom St Denis #define DCP_RANDOM_SEEDS__DCP_RAND_R_SEED_MASK 0x000000ffL 5178de2bdb3dSTom St Denis #define DCP_RANDOM_SEEDS__DCP_RAND_R_SEED__SHIFT 0x00000000 5179de2bdb3dSTom St Denis #define DCP_SPATIAL_DITHER_CNTL__DCP_FRAME_RANDOM_ENABLE_MASK 0x00000100L 5180de2bdb3dSTom St Denis #define DCP_SPATIAL_DITHER_CNTL__DCP_FRAME_RANDOM_ENABLE__SHIFT 0x00000008 5181de2bdb3dSTom St Denis #define DCP_SPATIAL_DITHER_CNTL__DCP_HIGHPASS_RANDOM_ENABLE_MASK 0x00000400L 5182de2bdb3dSTom St Denis #define DCP_SPATIAL_DITHER_CNTL__DCP_HIGHPASS_RANDOM_ENABLE__SHIFT 0x0000000a 5183de2bdb3dSTom St Denis #define DCP_SPATIAL_DITHER_CNTL__DCP_RGB_RANDOM_ENABLE_MASK 0x00000200L 5184de2bdb3dSTom St Denis #define DCP_SPATIAL_DITHER_CNTL__DCP_RGB_RANDOM_ENABLE__SHIFT 0x00000009 5185de2bdb3dSTom St Denis #define DCP_SPATIAL_DITHER_CNTL__DCP_SPATIAL_DITHER_DEPTH_MASK 0x00000040L 5186de2bdb3dSTom St Denis #define DCP_SPATIAL_DITHER_CNTL__DCP_SPATIAL_DITHER_DEPTH__SHIFT 0x00000006 5187de2bdb3dSTom St Denis #define DCP_SPATIAL_DITHER_CNTL__DCP_SPATIAL_DITHER_EN_MASK 0x00000001L 5188de2bdb3dSTom St Denis #define DCP_SPATIAL_DITHER_CNTL__DCP_SPATIAL_DITHER_EN__SHIFT 0x00000000 5189de2bdb3dSTom St Denis #define DCP_SPATIAL_DITHER_CNTL__DCP_SPATIAL_DITHER_MODE_MASK 0x00000030L 5190de2bdb3dSTom St Denis #define DCP_SPATIAL_DITHER_CNTL__DCP_SPATIAL_DITHER_MODE__SHIFT 0x00000004 5191de2bdb3dSTom St Denis #define DCP_TEST_DEBUG_DATA__DCP_TEST_DEBUG_DATA_MASK 0xffffffffL 5192de2bdb3dSTom St Denis #define DCP_TEST_DEBUG_DATA__DCP_TEST_DEBUG_DATA__SHIFT 0x00000000 5193de2bdb3dSTom St Denis #define DCP_TEST_DEBUG_INDEX__DCP_TEST_DEBUG_INDEX_MASK 0x000000ffL 5194de2bdb3dSTom St Denis #define DCP_TEST_DEBUG_INDEX__DCP_TEST_DEBUG_INDEX__SHIFT 0x00000000 5195de2bdb3dSTom St Denis #define DCP_TEST_DEBUG_INDEX__DCP_TEST_DEBUG_WRITE_EN_MASK 0x00000100L 5196de2bdb3dSTom St Denis #define DCP_TEST_DEBUG_INDEX__DCP_TEST_DEBUG_WRITE_EN__SHIFT 0x00000008 5197de2bdb3dSTom St Denis #define DC_RBBMIF_RDWR_CNTL1__DC_RBBMIF_CLIENT0_RDWR_DELAY_MASK 0x00000007L 5198de2bdb3dSTom St Denis #define DC_RBBMIF_RDWR_CNTL1__DC_RBBMIF_CLIENT0_RDWR_DELAY__SHIFT 0x00000000 5199de2bdb3dSTom St Denis #define DC_RBBMIF_RDWR_CNTL1__DC_RBBMIF_CLIENT0_RDWR_TIMEOUT_DIS_MASK 0x00000008L 5200de2bdb3dSTom St Denis #define DC_RBBMIF_RDWR_CNTL1__DC_RBBMIF_CLIENT0_RDWR_TIMEOUT_DIS__SHIFT 0x00000003 5201de2bdb3dSTom St Denis #define DC_RBBMIF_RDWR_CNTL1__DC_RBBMIF_CLIENT1_RDWR_DELAY_MASK 0x00000070L 5202de2bdb3dSTom St Denis #define DC_RBBMIF_RDWR_CNTL1__DC_RBBMIF_CLIENT1_RDWR_DELAY__SHIFT 0x00000004 5203de2bdb3dSTom St Denis #define DC_RBBMIF_RDWR_CNTL1__DC_RBBMIF_CLIENT1_RDWR_TIMEOUT_DIS_MASK 0x00000080L 5204de2bdb3dSTom St Denis #define DC_RBBMIF_RDWR_CNTL1__DC_RBBMIF_CLIENT1_RDWR_TIMEOUT_DIS__SHIFT 0x00000007 5205de2bdb3dSTom St Denis #define DC_RBBMIF_RDWR_CNTL1__DC_RBBMIF_CLIENT2_RDWR_DELAY_MASK 0x00000700L 5206de2bdb3dSTom St Denis #define DC_RBBMIF_RDWR_CNTL1__DC_RBBMIF_CLIENT2_RDWR_DELAY__SHIFT 0x00000008 5207de2bdb3dSTom St Denis #define DC_RBBMIF_RDWR_CNTL1__DC_RBBMIF_CLIENT2_RDWR_TIMEOUT_DIS_MASK 0x00000800L 5208de2bdb3dSTom St Denis #define DC_RBBMIF_RDWR_CNTL1__DC_RBBMIF_CLIENT2_RDWR_TIMEOUT_DIS__SHIFT 0x0000000b 5209de2bdb3dSTom St Denis #define DC_RBBMIF_RDWR_CNTL1__DC_RBBMIF_CLIENT3_RDWR_DELAY_MASK 0x00007000L 5210de2bdb3dSTom St Denis #define DC_RBBMIF_RDWR_CNTL1__DC_RBBMIF_CLIENT3_RDWR_DELAY__SHIFT 0x0000000c 5211de2bdb3dSTom St Denis #define DC_RBBMIF_RDWR_CNTL1__DC_RBBMIF_CLIENT3_RDWR_TIMEOUT_DIS_MASK 0x00008000L 5212de2bdb3dSTom St Denis #define DC_RBBMIF_RDWR_CNTL1__DC_RBBMIF_CLIENT3_RDWR_TIMEOUT_DIS__SHIFT 0x0000000f 5213de2bdb3dSTom St Denis #define DC_RBBMIF_RDWR_CNTL1__DC_RBBMIF_CLIENT4_RDWR_DELAY_MASK 0x00070000L 5214de2bdb3dSTom St Denis #define DC_RBBMIF_RDWR_CNTL1__DC_RBBMIF_CLIENT4_RDWR_DELAY__SHIFT 0x00000010 5215de2bdb3dSTom St Denis #define DC_RBBMIF_RDWR_CNTL1__DC_RBBMIF_CLIENT4_RDWR_TIMEOUT_DIS_MASK 0x00080000L 5216de2bdb3dSTom St Denis #define DC_RBBMIF_RDWR_CNTL1__DC_RBBMIF_CLIENT4_RDWR_TIMEOUT_DIS__SHIFT 0x00000013 5217de2bdb3dSTom St Denis #define DC_RBBMIF_RDWR_CNTL2__DC_RBBMIF_CLIENT8_RDWR_DELAY_MASK 0x00000007L 5218de2bdb3dSTom St Denis #define DC_RBBMIF_RDWR_CNTL2__DC_RBBMIF_CLIENT8_RDWR_DELAY__SHIFT 0x00000000 5219de2bdb3dSTom St Denis #define DC_RBBMIF_RDWR_CNTL2__DC_RBBMIF_CLIENT8_RDWR_TIMEOUT_DIS_MASK 0x00000008L 5220de2bdb3dSTom St Denis #define DC_RBBMIF_RDWR_CNTL2__DC_RBBMIF_CLIENT8_RDWR_TIMEOUT_DIS__SHIFT 0x00000003 5221de2bdb3dSTom St Denis #define DC_RBBMIF_RDWR_CNTL2__DC_RBBMIF_CLIENT9_RDWR_DELAY_MASK 0x00000070L 5222de2bdb3dSTom St Denis #define DC_RBBMIF_RDWR_CNTL2__DC_RBBMIF_CLIENT9_RDWR_DELAY__SHIFT 0x00000004 5223de2bdb3dSTom St Denis #define DC_RBBMIF_RDWR_CNTL2__DC_RBBMIF_CLIENT9_RDWR_TIMEOUT_DIS_MASK 0x00000080L 5224de2bdb3dSTom St Denis #define DC_RBBMIF_RDWR_CNTL2__DC_RBBMIF_CLIENT9_RDWR_TIMEOUT_DIS__SHIFT 0x00000007 5225de2bdb3dSTom St Denis #define DC_REF_CLK_CNTL__GENLK_CLK_OUTPUT_SEL_MASK 0x00000300L 5226de2bdb3dSTom St Denis #define DC_REF_CLK_CNTL__GENLK_CLK_OUTPUT_SEL__SHIFT 0x00000008 5227de2bdb3dSTom St Denis #define DC_REF_CLK_CNTL__HSYNCA_OUTPUT_SEL_MASK 0x00000003L 5228de2bdb3dSTom St Denis #define DC_REF_CLK_CNTL__HSYNCA_OUTPUT_SEL__SHIFT 0x00000000 5229de2bdb3dSTom St Denis #define DC_XDMA_INTERFACE_CNTL__DC_FLIP_PENDING_TO_DCP_MASK 0x00400000L 5230de2bdb3dSTom St Denis #define DC_XDMA_INTERFACE_CNTL__DC_FLIP_PENDING_TO_DCP__SHIFT 0x00000016 5231de2bdb3dSTom St Denis #define DC_XDMA_INTERFACE_CNTL__DC_XDMA_FLIP_PENDING_MASK 0x00010000L 5232de2bdb3dSTom St Denis #define DC_XDMA_INTERFACE_CNTL__DC_XDMA_FLIP_PENDING__SHIFT 0x00000010 5233de2bdb3dSTom St Denis #define DC_XDMA_INTERFACE_CNTL__XDMA_M_FLIP_PENDING_TO_DCP_MASK 0x00100000L 5234de2bdb3dSTom St Denis #define DC_XDMA_INTERFACE_CNTL__XDMA_M_FLIP_PENDING_TO_DCP__SHIFT 0x00000014 5235de2bdb3dSTom St Denis #define DC_XDMA_INTERFACE_CNTL__XDMA_PIPE_ENABLE_MASK 0x0000003fL 5236de2bdb3dSTom St Denis #define DC_XDMA_INTERFACE_CNTL__XDMA_PIPE_ENABLE__SHIFT 0x00000000 5237de2bdb3dSTom St Denis #define DC_XDMA_INTERFACE_CNTL__XDMA_PIPE_SEL_MASK 0x00000700L 5238de2bdb3dSTom St Denis #define DC_XDMA_INTERFACE_CNTL__XDMA_PIPE_SEL__SHIFT 0x00000008 5239de2bdb3dSTom St Denis #define DC_XDMA_INTERFACE_CNTL__XDMA_S_FLIP_PENDING_TO_DCP_MASK 0x00200000L 5240de2bdb3dSTom St Denis #define DC_XDMA_INTERFACE_CNTL__XDMA_S_FLIP_PENDING_TO_DCP__SHIFT 0x00000015 5241de2bdb3dSTom St Denis #define DEGAMMA_CONTROL__CURSOR_DEGAMMA_MODE_MASK 0x00003000L 5242de2bdb3dSTom St Denis #define DEGAMMA_CONTROL__CURSOR_DEGAMMA_MODE__SHIFT 0x0000000c 5243de2bdb3dSTom St Denis #define DEGAMMA_CONTROL__GRPH_DEGAMMA_MODE_MASK 0x00000003L 5244de2bdb3dSTom St Denis #define DEGAMMA_CONTROL__GRPH_DEGAMMA_MODE__SHIFT 0x00000000 5245de2bdb3dSTom St Denis #define DEGAMMA_CONTROL__OVL_DEGAMMA_MODE_MASK 0x00000030L 5246de2bdb3dSTom St Denis #define DEGAMMA_CONTROL__OVL_DEGAMMA_MODE__SHIFT 0x00000004 5247de2bdb3dSTom St Denis #define DENORM_CONTROL__DENORM_MODE_MASK 0x00000007L 5248de2bdb3dSTom St Denis #define DENORM_CONTROL__DENORM_MODE__SHIFT 0x00000000 5249de2bdb3dSTom St Denis #define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHG_DONE_MASK 0x00080000L 5250de2bdb3dSTom St Denis #define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHG_DONE__SHIFT 0x00000013 5251de2bdb3dSTom St Denis #define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHG_MODE_MASK 0x00018000L 5252de2bdb3dSTom St Denis #define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHG_MODE__SHIFT 0x0000000f 5253de2bdb3dSTom St Denis #define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHGTOG_MASK 0x00020000L 5254de2bdb3dSTom St Denis #define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHGTOG__SHIFT 0x00000011 5255de2bdb3dSTom St Denis #define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_DONETOG_MASK 0x00040000L 5256de2bdb3dSTom St Denis #define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_DONETOG__SHIFT 0x00000012 5257de2bdb3dSTom St Denis #define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_RDIVIDER_MASK 0x00007f00L 5258de2bdb3dSTom St Denis #define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_RDIVIDER__SHIFT 0x00000008 5259de2bdb3dSTom St Denis #define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_WDIVIDER_MASK 0x0000007fL 5260de2bdb3dSTom St Denis #define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_WDIVIDER__SHIFT 0x00000000 5261de2bdb3dSTom St Denis #define DENTIST_DISPCLK_CNTL__DENTIST_DPREFCLK_CHG_DONE_MASK 0x00100000L 5262de2bdb3dSTom St Denis #define DENTIST_DISPCLK_CNTL__DENTIST_DPREFCLK_CHG_DONE__SHIFT 0x00000014 5263de2bdb3dSTom St Denis #define DENTIST_DISPCLK_CNTL__DENTIST_DPREFCLK_CHGTOG_MASK 0x00200000L 5264de2bdb3dSTom St Denis #define DENTIST_DISPCLK_CNTL__DENTIST_DPREFCLK_CHGTOG__SHIFT 0x00000015 5265de2bdb3dSTom St Denis #define DENTIST_DISPCLK_CNTL__DENTIST_DPREFCLK_DONETOG_MASK 0x00400000L 5266de2bdb3dSTom St Denis #define DENTIST_DISPCLK_CNTL__DENTIST_DPREFCLK_DONETOG__SHIFT 0x00000016 5267de2bdb3dSTom St Denis #define DENTIST_DISPCLK_CNTL__DENTIST_DPREFCLK_WDIVIDER_MASK 0x7f000000L 5268de2bdb3dSTom St Denis #define DENTIST_DISPCLK_CNTL__DENTIST_DPREFCLK_WDIVIDER__SHIFT 0x00000018 5269de2bdb3dSTom St Denis #define DIG_BE_CNTL__DIG_FE_SOURCE_SELECT_MASK 0x00003f00L 5270de2bdb3dSTom St Denis #define DIG_BE_CNTL__DIG_FE_SOURCE_SELECT__SHIFT 0x00000008 5271de2bdb3dSTom St Denis #define DIG_BE_CNTL__DIG_HPD_SELECT_MASK 0x70000000L 5272de2bdb3dSTom St Denis #define DIG_BE_CNTL__DIG_HPD_SELECT__SHIFT 0x0000001c 5273de2bdb3dSTom St Denis #define DIG_BE_CNTL__DIG_MODE_MASK 0x00070000L 5274de2bdb3dSTom St Denis #define DIG_BE_CNTL__DIG_MODE__SHIFT 0x00000010 5275de2bdb3dSTom St Denis #define DIG_BE_EN_CNTL__DIG_ENABLE_MASK 0x00000001L 5276de2bdb3dSTom St Denis #define DIG_BE_EN_CNTL__DIG_ENABLE__SHIFT 0x00000000 5277de2bdb3dSTom St Denis #define DIG_BE_EN_CNTL__DIG_SYMCLK_BE_ON_MASK 0x00000100L 5278de2bdb3dSTom St Denis #define DIG_BE_EN_CNTL__DIG_SYMCLK_BE_ON__SHIFT 0x00000008 5279de2bdb3dSTom St Denis #define DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN_MASK 0x000003ffL 5280de2bdb3dSTom St Denis #define DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN__SHIFT 0x00000000 5281de2bdb3dSTom St Denis #define DIG_DISPCLK_SWITCH_CNTL__DIG_DISPCLK_SWITCH_POINT_MASK 0x00000001L 5282de2bdb3dSTom St Denis #define DIG_DISPCLK_SWITCH_CNTL__DIG_DISPCLK_SWITCH_POINT__SHIFT 0x00000000 5283de2bdb3dSTom St Denis #define DIG_DISPCLK_SWITCH_STATUS__DIG_DISPCLK_SWITCH_ALLOWED_INT_ACK_MASK 0x00000100L 5284de2bdb3dSTom St Denis #define DIG_DISPCLK_SWITCH_STATUS__DIG_DISPCLK_SWITCH_ALLOWED_INT_ACK__SHIFT 0x00000008 5285de2bdb3dSTom St Denis #define DIG_DISPCLK_SWITCH_STATUS__DIG_DISPCLK_SWITCH_ALLOWED_INT_MASK 0x00000010L 5286de2bdb3dSTom St Denis #define DIG_DISPCLK_SWITCH_STATUS__DIG_DISPCLK_SWITCH_ALLOWED_INT_MASK_MASK 0x00001000L 5287de2bdb3dSTom St Denis #define DIG_DISPCLK_SWITCH_STATUS__DIG_DISPCLK_SWITCH_ALLOWED_INT_MASK__SHIFT 0x0000000c 5288de2bdb3dSTom St Denis #define DIG_DISPCLK_SWITCH_STATUS__DIG_DISPCLK_SWITCH_ALLOWED_INT__SHIFT 0x00000004 5289de2bdb3dSTom St Denis #define DIG_DISPCLK_SWITCH_STATUS__DIG_DISPCLK_SWITCH_ALLOWED_MASK 0x00000001L 5290de2bdb3dSTom St Denis #define DIG_DISPCLK_SWITCH_STATUS__DIG_DISPCLK_SWITCH_ALLOWED__SHIFT 0x00000000 5291de2bdb3dSTom St Denis #define DIG_FE_CNTL__DIG_DUAL_LINK_ENABLE_MASK 0x00010000L 5292de2bdb3dSTom St Denis #define DIG_FE_CNTL__DIG_DUAL_LINK_ENABLE__SHIFT 0x00000010 5293de2bdb3dSTom St Denis #define DIG_FE_CNTL__DIG_RB_SWITCH_EN_MASK 0x00100000L 5294de2bdb3dSTom St Denis #define DIG_FE_CNTL__DIG_RB_SWITCH_EN__SHIFT 0x00000014 5295de2bdb3dSTom St Denis #define DIG_FE_CNTL__DIG_SOURCE_SELECT_MASK 0x00000007L 5296de2bdb3dSTom St Denis #define DIG_FE_CNTL__DIG_SOURCE_SELECT__SHIFT 0x00000000 5297de2bdb3dSTom St Denis #define DIG_FE_CNTL__DIG_START_MASK 0x00000400L 5298de2bdb3dSTom St Denis #define DIG_FE_CNTL__DIG_START__SHIFT 0x0000000a 5299de2bdb3dSTom St Denis #define DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN_MASK 0x00000100L 5300de2bdb3dSTom St Denis #define DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN__SHIFT 0x00000008 5301de2bdb3dSTom St Denis #define DIG_FE_CNTL__DIG_STEREOSYNC_SELECT_MASK 0x00000070L 5302de2bdb3dSTom St Denis #define DIG_FE_CNTL__DIG_STEREOSYNC_SELECT__SHIFT 0x00000004 5303de2bdb3dSTom St Denis #define DIG_FE_CNTL__DIG_SWAP_MASK 0x00040000L 5304de2bdb3dSTom St Denis #define DIG_FE_CNTL__DIG_SWAP__SHIFT 0x00000012 5305de2bdb3dSTom St Denis #define DIG_FE_CNTL__DIG_SYMCLK_FE_ON_MASK 0x01000000L 5306de2bdb3dSTom St Denis #define DIG_FE_CNTL__DIG_SYMCLK_FE_ON__SHIFT 0x00000018 5307de2bdb3dSTom St Denis #define DIG_FIFO_STATUS__DIG_FIFO_CAL_AVERAGE_LEVEL_MASK 0x0000fc00L 5308de2bdb3dSTom St Denis #define DIG_FIFO_STATUS__DIG_FIFO_CAL_AVERAGE_LEVEL__SHIFT 0x0000000a 5309de2bdb3dSTom St Denis #define DIG_FIFO_STATUS__DIG_FIFO_CALIBRATED_MASK 0x20000000L 5310de2bdb3dSTom St Denis #define DIG_FIFO_STATUS__DIG_FIFO_CALIBRATED__SHIFT 0x0000001d 5311de2bdb3dSTom St Denis #define DIG_FIFO_STATUS__DIG_FIFO_ERROR_ACK_MASK 0x00000100L 5312de2bdb3dSTom St Denis #define DIG_FIFO_STATUS__DIG_FIFO_ERROR_ACK__SHIFT 0x00000008 5313de2bdb3dSTom St Denis #define DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECAL_AVERAGE_MASK 0x40000000L 5314de2bdb3dSTom St Denis #define DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECAL_AVERAGE__SHIFT 0x0000001e 5315de2bdb3dSTom St Denis #define DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECOMP_MINMAX_MASK 0x80000000L 5316de2bdb3dSTom St Denis #define DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECOMP_MINMAX__SHIFT 0x0000001f 5317de2bdb3dSTom St Denis #define DIG_FIFO_STATUS__DIG_FIFO_LEVEL_ERROR_MASK 0x00000001L 5318de2bdb3dSTom St Denis #define DIG_FIFO_STATUS__DIG_FIFO_LEVEL_ERROR__SHIFT 0x00000000 5319de2bdb3dSTom St Denis #define DIG_FIFO_STATUS__DIG_FIFO_MAXIMUM_LEVEL_MASK 0x001f0000L 5320de2bdb3dSTom St Denis #define DIG_FIFO_STATUS__DIG_FIFO_MAXIMUM_LEVEL__SHIFT 0x00000010 5321de2bdb3dSTom St Denis #define DIG_FIFO_STATUS__DIG_FIFO_MINIMUM_LEVEL_MASK 0x03c00000L 5322de2bdb3dSTom St Denis #define DIG_FIFO_STATUS__DIG_FIFO_MINIMUM_LEVEL__SHIFT 0x00000016 5323de2bdb3dSTom St Denis #define DIG_FIFO_STATUS__DIG_FIFO_OVERWRITE_LEVEL_MASK 0x000000fcL 5324de2bdb3dSTom St Denis #define DIG_FIFO_STATUS__DIG_FIFO_OVERWRITE_LEVEL__SHIFT 0x00000002 5325de2bdb3dSTom St Denis #define DIG_FIFO_STATUS__DIG_FIFO_USE_OVERWRITE_LEVEL_MASK 0x00000002L 5326de2bdb3dSTom St Denis #define DIG_FIFO_STATUS__DIG_FIFO_USE_OVERWRITE_LEVEL__SHIFT 0x00000001 5327de2bdb3dSTom St Denis #define DIG_LANE_ENABLE__DIG_CLK_EN_MASK 0x00000100L 5328de2bdb3dSTom St Denis #define DIG_LANE_ENABLE__DIG_CLK_EN__SHIFT 0x00000008 5329de2bdb3dSTom St Denis #define DIG_LANE_ENABLE__DIG_LANE0EN_MASK 0x00000001L 5330de2bdb3dSTom St Denis #define DIG_LANE_ENABLE__DIG_LANE0EN__SHIFT 0x00000000 5331de2bdb3dSTom St Denis #define DIG_LANE_ENABLE__DIG_LANE1EN_MASK 0x00000002L 5332de2bdb3dSTom St Denis #define DIG_LANE_ENABLE__DIG_LANE1EN__SHIFT 0x00000001 5333de2bdb3dSTom St Denis #define DIG_LANE_ENABLE__DIG_LANE2EN_MASK 0x00000004L 5334de2bdb3dSTom St Denis #define DIG_LANE_ENABLE__DIG_LANE2EN__SHIFT 0x00000002 5335de2bdb3dSTom St Denis #define DIG_LANE_ENABLE__DIG_LANE3EN_MASK 0x00000008L 5336de2bdb3dSTom St Denis #define DIG_LANE_ENABLE__DIG_LANE3EN__SHIFT 0x00000003 5337de2bdb3dSTom St Denis #define DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL_MASK 0x00000300L 5338de2bdb3dSTom St Denis #define DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL__SHIFT 0x00000008 5339de2bdb3dSTom St Denis #define DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN_MASK 0x00000001L 5340de2bdb3dSTom St Denis #define DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN__SHIFT 0x00000000 5341de2bdb3dSTom St Denis #define DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL_MASK 0x00000010L 5342de2bdb3dSTom St Denis #define DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL__SHIFT 0x00000004 5343de2bdb3dSTom St Denis #define DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT_MASK 0x3fffffffL 5344de2bdb3dSTom St Denis #define DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT__SHIFT 0x00000000 5345de2bdb3dSTom St Denis #define DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED_MASK 0x00ffffffL 5346de2bdb3dSTom St Denis #define DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED__SHIFT 0x00000000 5347de2bdb3dSTom St Denis #define DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY_MASK 0x01000000L 5348de2bdb3dSTom St Denis #define DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY__SHIFT 0x00000018 5349de2bdb3dSTom St Denis #define DIG_SOFT_RESET__DIGA_BE_SOFT_RESET_MASK 0x00000002L 5350de2bdb3dSTom St Denis #define DIG_SOFT_RESET__DIGA_BE_SOFT_RESET__SHIFT 0x00000001 5351de2bdb3dSTom St Denis #define DIG_SOFT_RESET__DIGA_FE_SOFT_RESET_MASK 0x00000001L 5352de2bdb3dSTom St Denis #define DIG_SOFT_RESET__DIGA_FE_SOFT_RESET__SHIFT 0x00000000 5353de2bdb3dSTom St Denis #define DIG_SOFT_RESET__DIGB_BE_SOFT_RESET_MASK 0x00000020L 5354de2bdb3dSTom St Denis #define DIG_SOFT_RESET__DIGB_BE_SOFT_RESET__SHIFT 0x00000005 5355de2bdb3dSTom St Denis #define DIG_SOFT_RESET__DIGB_FE_SOFT_RESET_MASK 0x00000010L 5356de2bdb3dSTom St Denis #define DIG_SOFT_RESET__DIGB_FE_SOFT_RESET__SHIFT 0x00000004 5357de2bdb3dSTom St Denis #define DIG_SOFT_RESET__DIGC_BE_SOFT_RESET_MASK 0x00000200L 5358de2bdb3dSTom St Denis #define DIG_SOFT_RESET__DIGC_BE_SOFT_RESET__SHIFT 0x00000009 5359de2bdb3dSTom St Denis #define DIG_SOFT_RESET__DIGC_FE_SOFT_RESET_MASK 0x00000100L 5360de2bdb3dSTom St Denis #define DIG_SOFT_RESET__DIGC_FE_SOFT_RESET__SHIFT 0x00000008 5361de2bdb3dSTom St Denis #define DIG_SOFT_RESET__DIGD_BE_SOFT_RESET_MASK 0x00002000L 5362de2bdb3dSTom St Denis #define DIG_SOFT_RESET__DIGD_BE_SOFT_RESET__SHIFT 0x0000000d 5363de2bdb3dSTom St Denis #define DIG_SOFT_RESET__DIGD_FE_SOFT_RESET_MASK 0x00001000L 5364de2bdb3dSTom St Denis #define DIG_SOFT_RESET__DIGD_FE_SOFT_RESET__SHIFT 0x0000000c 5365de2bdb3dSTom St Denis #define DIG_SOFT_RESET__DIGE_BE_SOFT_RESET_MASK 0x00020000L 5366de2bdb3dSTom St Denis #define DIG_SOFT_RESET__DIGE_BE_SOFT_RESET__SHIFT 0x00000011 5367de2bdb3dSTom St Denis #define DIG_SOFT_RESET__DIGE_FE_SOFT_RESET_MASK 0x00010000L 5368de2bdb3dSTom St Denis #define DIG_SOFT_RESET__DIGE_FE_SOFT_RESET__SHIFT 0x00000010 5369de2bdb3dSTom St Denis #define DIG_SOFT_RESET__DIGF_BE_SOFT_RESET_MASK 0x00200000L 5370de2bdb3dSTom St Denis #define DIG_SOFT_RESET__DIGF_BE_SOFT_RESET__SHIFT 0x00000015 5371de2bdb3dSTom St Denis #define DIG_SOFT_RESET__DIGF_FE_SOFT_RESET_MASK 0x00100000L 5372de2bdb3dSTom St Denis #define DIG_SOFT_RESET__DIGF_FE_SOFT_RESET__SHIFT 0x00000014 5373de2bdb3dSTom St Denis #define DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL_MASK 0x00000002L 5374de2bdb3dSTom St Denis #define DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL__SHIFT 0x00000001 5375de2bdb3dSTom St Denis #define DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN_MASK 0x00000010L 5376de2bdb3dSTom St Denis #define DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN__SHIFT 0x00000004 5377de2bdb3dSTom St Denis #define DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET_MASK 0x00000020L 5378de2bdb3dSTom St Denis #define DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET__SHIFT 0x00000005 5379de2bdb3dSTom St Denis #define DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN_MASK 0x03ff0000L 5380de2bdb3dSTom St Denis #define DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN__SHIFT 0x00000010 5381de2bdb3dSTom St Denis #define DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN_MASK 0x00000040L 5382de2bdb3dSTom St Denis #define DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN__SHIFT 0x00000006 5383de2bdb3dSTom St Denis #define DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN_MASK 0x00000001L 5384de2bdb3dSTom St Denis #define DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN__SHIFT 0x00000000 5385de2bdb3dSTom St Denis #define DIG_TEST_PATTERN__LVDS_EYE_PATTERN_MASK 0x00000100L 5386de2bdb3dSTom St Denis #define DIG_TEST_PATTERN__LVDS_EYE_PATTERN__SHIFT 0x00000008 5387de2bdb3dSTom St Denis #define DIG_TEST_PATTERN__LVDS_TEST_CLOCK_DATA_MASK 0x00000004L 5388de2bdb3dSTom St Denis #define DIG_TEST_PATTERN__LVDS_TEST_CLOCK_DATA__SHIFT 0x00000002 5389de2bdb3dSTom St Denis #define DISPCLK_CGTT_BLK_CTRL_REG__DISPCLK_TURN_OFF_DELAY_MASK 0x00000ff0L 5390de2bdb3dSTom St Denis #define DISPCLK_CGTT_BLK_CTRL_REG__DISPCLK_TURN_OFF_DELAY__SHIFT 0x00000004 5391de2bdb3dSTom St Denis #define DISPCLK_CGTT_BLK_CTRL_REG__DISPCLK_TURN_ON_DELAY_MASK 0x0000000fL 5392de2bdb3dSTom St Denis #define DISPCLK_CGTT_BLK_CTRL_REG__DISPCLK_TURN_ON_DELAY__SHIFT 0x00000000 5393de2bdb3dSTom St Denis #define DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_OVR_EN_MASK 0x40000000L 5394de2bdb3dSTom St Denis #define DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_OVR_EN__SHIFT 0x0000001e 5395de2bdb3dSTom St Denis #define DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_RESET_MASK 0x10000000L 5396de2bdb3dSTom St Denis #define DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_RESET__SHIFT 0x0000001c 5397de2bdb3dSTom St Denis #define DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_STATE_MASK 0x20000000L 5398de2bdb3dSTom St Denis #define DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_STATE__SHIFT 0x0000001d 5399de2bdb3dSTom St Denis #define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_CHG_FWD_CORR_DISABLE_MASK 0x80000000L 5400de2bdb3dSTom St Denis #define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_CHG_FWD_CORR_DISABLE__SHIFT 0x0000001f 5401de2bdb3dSTom St Denis #define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_FREQ_RAMP_DONE_MASK 0x00100000L 5402de2bdb3dSTom St Denis #define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_FREQ_RAMP_DONE__SHIFT 0x00000014 5403de2bdb3dSTom St Denis #define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_MAX_ERRDET_CYCLES_MASK 0x0e000000L 5404de2bdb3dSTom St Denis #define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_MAX_ERRDET_CYCLES__SHIFT 0x00000019 5405de2bdb3dSTom St Denis #define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_STEP_DELAY_MASK 0x00003fffL 5406de2bdb3dSTom St Denis #define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_STEP_DELAY__SHIFT 0x00000000 5407de2bdb3dSTom St Denis #define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_STEP_SIZE_MASK 0x000f0000L 5408de2bdb3dSTom St Denis #define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_STEP_SIZE__SHIFT 0x00000010 5409de2bdb3dSTom St Denis #define DISP_INTERRUPT_STATUS__ABM1_BL_UPDATE_INT_MASK 0x40000000L 5410de2bdb3dSTom St Denis #define DISP_INTERRUPT_STATUS__ABM1_BL_UPDATE_INT__SHIFT 0x0000001e 5411de2bdb3dSTom St Denis #define DISP_INTERRUPT_STATUS__ABM1_HG_READY_INT_MASK 0x10000000L 5412de2bdb3dSTom St Denis #define DISP_INTERRUPT_STATUS__ABM1_HG_READY_INT__SHIFT 0x0000001c 5413de2bdb3dSTom St Denis #define DISP_INTERRUPT_STATUS__ABM1_LS_READY_INT_MASK 0x20000000L 5414de2bdb3dSTom St Denis #define DISP_INTERRUPT_STATUS__ABM1_LS_READY_INT__SHIFT 0x0000001d 5415de2bdb3dSTom St Denis #define DISP_INTERRUPT_STATUS__AUX1_LS_DONE_INTERRUPT_MASK 0x00100000L 5416de2bdb3dSTom St Denis #define DISP_INTERRUPT_STATUS__AUX1_LS_DONE_INTERRUPT__SHIFT 0x00000014 5417de2bdb3dSTom St Denis #define DISP_INTERRUPT_STATUS__AUX1_SW_DONE_INTERRUPT_MASK 0x00080000L 5418de2bdb3dSTom St Denis #define DISP_INTERRUPT_STATUS__AUX1_SW_DONE_INTERRUPT__SHIFT 0x00000013 5419de2bdb3dSTom St Denis #define DISP_INTERRUPT_STATUS_CONTINUE2__AUX3_LS_DONE_INTERRUPT_MASK 0x00100000L 5420de2bdb3dSTom St Denis #define DISP_INTERRUPT_STATUS_CONTINUE2__AUX3_LS_DONE_INTERRUPT__SHIFT 0x00000014 5421de2bdb3dSTom St Denis #define DISP_INTERRUPT_STATUS_CONTINUE2__AUX3_SW_DONE_INTERRUPT_MASK 0x00080000L 5422de2bdb3dSTom St Denis #define DISP_INTERRUPT_STATUS_CONTINUE2__AUX3_SW_DONE_INTERRUPT__SHIFT 0x00000013 5423de2bdb3dSTom St Denis #define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_FORCE_COUNT_NOW_INTERRUPT_MASK 0x00000040L 5424de2bdb3dSTom St Denis #define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_FORCE_COUNT_NOW_INTERRUPT__SHIFT 0x00000006 5425de2bdb3dSTom St Denis #define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK 0x00000020L 5426de2bdb3dSTom St Denis #define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT 0x00000005 5427de2bdb3dSTom St Denis #define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK 0x00000400L 5428de2bdb3dSTom St Denis #define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT 0x0000000a 5429de2bdb3dSTom St Denis #define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_SNAPSHOT_INTERRUPT_MASK 0x00000010L 5430de2bdb3dSTom St Denis #define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_SNAPSHOT_INTERRUPT__SHIFT 0x00000004 5431de2bdb3dSTom St Denis #define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_TRIGA_INTERRUPT_MASK 0x00000080L 5432de2bdb3dSTom St Denis #define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_TRIGA_INTERRUPT__SHIFT 0x00000007 5433de2bdb3dSTom St Denis #define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_TRIGB_INTERRUPT_MASK 0x00000100L 5434de2bdb3dSTom St Denis #define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_TRIGB_INTERRUPT__SHIFT 0x00000008 5435de2bdb3dSTom St Denis #define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_VSYNC_NOM_INTERRUPT_MASK 0x00000200L 5436de2bdb3dSTom St Denis #define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_VSYNC_NOM_INTERRUPT__SHIFT 0x00000009 5437de2bdb3dSTom St Denis #define DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_INTERRUPT_MASK 0x00020000L 5438de2bdb3dSTom St Denis #define DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_INTERRUPT__SHIFT 0x00000011 5439de2bdb3dSTom St Denis #define DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_RX_INTERRUPT_MASK 0x00040000L 5440de2bdb3dSTom St Denis #define DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_RX_INTERRUPT__SHIFT 0x00000012 5441de2bdb3dSTom St Denis #define DISP_INTERRUPT_STATUS_CONTINUE2__DIGC_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK 0x00008000L 5442de2bdb3dSTom St Denis #define DISP_INTERRUPT_STATUS_CONTINUE2__DIGC_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT 0x0000000f 5443de2bdb3dSTom St Denis #define DISP_INTERRUPT_STATUS_CONTINUE2__DIGC_DP_VID_STREAM_DISABLE_INTERRUPT_MASK 0x00010000L 5444de2bdb3dSTom St Denis #define DISP_INTERRUPT_STATUS_CONTINUE2__DIGC_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT 0x00000010 5445de2bdb3dSTom St Denis #define DISP_INTERRUPT_STATUS_CONTINUE2__DISP_INTERRUPT_STATUS_CONTINUE3_MASK 0x80000000L 5446de2bdb3dSTom St Denis #define DISP_INTERRUPT_STATUS_CONTINUE2__DISP_INTERRUPT_STATUS_CONTINUE3__SHIFT 0x0000001f 5447de2bdb3dSTom St Denis #define DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VBLANK_INTERRUPT_MASK 0x00000008L 5448de2bdb3dSTom St Denis #define DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VBLANK_INTERRUPT__SHIFT 0x00000003 5449de2bdb3dSTom St Denis #define DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VLINE_INTERRUPT_MASK 0x00000004L 5450de2bdb3dSTom St Denis #define DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VLINE_INTERRUPT__SHIFT 0x00000002 5451de2bdb3dSTom St Denis #define DISP_INTERRUPT_STATUS_CONTINUE2__SCL_DISP3_MODE_CHANGE_INTERRUPT_MASK 0x00000001L 5452de2bdb3dSTom St Denis #define DISP_INTERRUPT_STATUS_CONTINUE2__SCL_DISP3_MODE_CHANGE_INTERRUPT__SHIFT 0x00000000 5453de2bdb3dSTom St Denis #define DISP_INTERRUPT_STATUS_CONTINUE3__AUX4_LS_DONE_INTERRUPT_MASK 0x00100000L 5454de2bdb3dSTom St Denis #define DISP_INTERRUPT_STATUS_CONTINUE3__AUX4_LS_DONE_INTERRUPT__SHIFT 0x00000014 5455de2bdb3dSTom St Denis #define DISP_INTERRUPT_STATUS_CONTINUE3__AUX4_SW_DONE_INTERRUPT_MASK 0x00080000L 5456de2bdb3dSTom St Denis #define DISP_INTERRUPT_STATUS_CONTINUE3__AUX4_SW_DONE_INTERRUPT__SHIFT 0x00000013 5457de2bdb3dSTom St Denis #define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_FORCE_COUNT_NOW_INTERRUPT_MASK 0x00000040L 5458de2bdb3dSTom St Denis #define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_FORCE_COUNT_NOW_INTERRUPT__SHIFT 0x00000006 5459de2bdb3dSTom St Denis #define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK 0x00000020L 5460de2bdb3dSTom St Denis #define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT 0x00000005 5461de2bdb3dSTom St Denis #define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK 0x00000400L 5462de2bdb3dSTom St Denis #define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT 0x0000000a 5463de2bdb3dSTom St Denis #define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_SNAPSHOT_INTERRUPT_MASK 0x00000010L 5464de2bdb3dSTom St Denis #define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_SNAPSHOT_INTERRUPT__SHIFT 0x00000004 5465de2bdb3dSTom St Denis #define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_TRIGA_INTERRUPT_MASK 0x00000080L 5466de2bdb3dSTom St Denis #define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_TRIGA_INTERRUPT__SHIFT 0x00000007 5467de2bdb3dSTom St Denis #define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_TRIGB_INTERRUPT_MASK 0x00000100L 5468de2bdb3dSTom St Denis #define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_TRIGB_INTERRUPT__SHIFT 0x00000008 5469de2bdb3dSTom St Denis #define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_VSYNC_NOM_INTERRUPT_MASK 0x00000200L 5470de2bdb3dSTom St Denis #define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_VSYNC_NOM_INTERRUPT__SHIFT 0x00000009 5471de2bdb3dSTom St Denis #define DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT_MASK 0x00020000L 5472de2bdb3dSTom St Denis #define DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT__SHIFT 0x00000011 5473de2bdb3dSTom St Denis #define DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_RX_INTERRUPT_MASK 0x00040000L 5474de2bdb3dSTom St Denis #define DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_RX_INTERRUPT__SHIFT 0x00000012 5475de2bdb3dSTom St Denis #define DISP_INTERRUPT_STATUS_CONTINUE3__DIGD_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK 0x00008000L 5476de2bdb3dSTom St Denis #define DISP_INTERRUPT_STATUS_CONTINUE3__DIGD_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT 0x0000000f 5477de2bdb3dSTom St Denis #define DISP_INTERRUPT_STATUS_CONTINUE3__DIGD_DP_VID_STREAM_DISABLE_INTERRUPT_MASK 0x00010000L 5478de2bdb3dSTom St Denis #define DISP_INTERRUPT_STATUS_CONTINUE3__DIGD_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT 0x00000010 5479de2bdb3dSTom St Denis #define DISP_INTERRUPT_STATUS_CONTINUE3__DISP_INTERRUPT_STATUS_CONTINUE4_MASK 0x80000000L 5480de2bdb3dSTom St Denis #define DISP_INTERRUPT_STATUS_CONTINUE3__DISP_INTERRUPT_STATUS_CONTINUE4__SHIFT 0x0000001f 5481de2bdb3dSTom St Denis #define DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VBLANK_INTERRUPT_MASK 0x00000008L 5482de2bdb3dSTom St Denis #define DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VBLANK_INTERRUPT__SHIFT 0x00000003 5483de2bdb3dSTom St Denis #define DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VLINE_INTERRUPT_MASK 0x00000004L 5484de2bdb3dSTom St Denis #define DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VLINE_INTERRUPT__SHIFT 0x00000002 5485de2bdb3dSTom St Denis #define DISP_INTERRUPT_STATUS_CONTINUE3__SCL_DISP4_MODE_CHANGE_INTERRUPT_MASK 0x00000001L 5486de2bdb3dSTom St Denis #define DISP_INTERRUPT_STATUS_CONTINUE3__SCL_DISP4_MODE_CHANGE_INTERRUPT__SHIFT 0x00000000 5487de2bdb3dSTom St Denis #define DISP_INTERRUPT_STATUS_CONTINUE4__AUX5_LS_DONE_INTERRUPT_MASK 0x00100000L 5488de2bdb3dSTom St Denis #define DISP_INTERRUPT_STATUS_CONTINUE4__AUX5_LS_DONE_INTERRUPT__SHIFT 0x00000014 5489de2bdb3dSTom St Denis #define DISP_INTERRUPT_STATUS_CONTINUE4__AUX5_SW_DONE_INTERRUPT_MASK 0x00080000L 5490de2bdb3dSTom St Denis #define DISP_INTERRUPT_STATUS_CONTINUE4__AUX5_SW_DONE_INTERRUPT__SHIFT 0x00000013 5491de2bdb3dSTom St Denis #define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_FORCE_COUNT_NOW_INTERRUPT_MASK 0x00000040L 5492de2bdb3dSTom St Denis #define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_FORCE_COUNT_NOW_INTERRUPT__SHIFT 0x00000006 5493de2bdb3dSTom St Denis #define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK 0x00000020L 5494de2bdb3dSTom St Denis #define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT 0x00000005 5495de2bdb3dSTom St Denis #define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK 0x00000400L 5496de2bdb3dSTom St Denis #define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT 0x0000000a 5497de2bdb3dSTom St Denis #define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_SNAPSHOT_INTERRUPT_MASK 0x00000010L 5498de2bdb3dSTom St Denis #define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_SNAPSHOT_INTERRUPT__SHIFT 0x00000004 5499de2bdb3dSTom St Denis #define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_TRIGA_INTERRUPT_MASK 0x00000080L 5500de2bdb3dSTom St Denis #define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_TRIGA_INTERRUPT__SHIFT 0x00000007 5501de2bdb3dSTom St Denis #define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_TRIGB_INTERRUPT_MASK 0x00000100L 5502de2bdb3dSTom St Denis #define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_TRIGB_INTERRUPT__SHIFT 0x00000008 5503de2bdb3dSTom St Denis #define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_VSYNC_NOM_INTERRUPT_MASK 0x00000200L 5504de2bdb3dSTom St Denis #define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_VSYNC_NOM_INTERRUPT__SHIFT 0x00000009 5505de2bdb3dSTom St Denis #define DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_INTERRUPT_MASK 0x00020000L 5506de2bdb3dSTom St Denis #define DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_INTERRUPT__SHIFT 0x00000011 5507de2bdb3dSTom St Denis #define DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_RX_INTERRUPT_MASK 0x00040000L 5508de2bdb3dSTom St Denis #define DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_RX_INTERRUPT__SHIFT 0x00000012 5509de2bdb3dSTom St Denis #define DISP_INTERRUPT_STATUS_CONTINUE4__DIGE_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK 0x00008000L 5510de2bdb3dSTom St Denis #define DISP_INTERRUPT_STATUS_CONTINUE4__DIGE_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT 0x0000000f 5511de2bdb3dSTom St Denis #define DISP_INTERRUPT_STATUS_CONTINUE4__DIGE_DP_VID_STREAM_DISABLE_INTERRUPT_MASK 0x00010000L 5512de2bdb3dSTom St Denis #define DISP_INTERRUPT_STATUS_CONTINUE4__DIGE_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT 0x00000010 5513de2bdb3dSTom St Denis #define DISP_INTERRUPT_STATUS_CONTINUE4__DISP_INTERRUPT_STATUS_CONTINUE5_MASK 0x80000000L 5514de2bdb3dSTom St Denis #define DISP_INTERRUPT_STATUS_CONTINUE4__DISP_INTERRUPT_STATUS_CONTINUE5__SHIFT 0x0000001f 5515de2bdb3dSTom St Denis #define DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VBLANK_INTERRUPT_MASK 0x00000008L 5516de2bdb3dSTom St Denis #define DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VBLANK_INTERRUPT__SHIFT 0x00000003 5517de2bdb3dSTom St Denis #define DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VLINE_INTERRUPT_MASK 0x00000004L 5518de2bdb3dSTom St Denis #define DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VLINE_INTERRUPT__SHIFT 0x00000002 5519de2bdb3dSTom St Denis #define DISP_INTERRUPT_STATUS_CONTINUE4__SCL_DISP5_MODE_CHANGE_INTERRUPT_MASK 0x00000001L 5520de2bdb3dSTom St Denis #define DISP_INTERRUPT_STATUS_CONTINUE4__SCL_DISP5_MODE_CHANGE_INTERRUPT__SHIFT 0x00000000 5521de2bdb3dSTom St Denis #define DISP_INTERRUPT_STATUS_CONTINUE5__AUX6_LS_DONE_INTERRUPT_MASK 0x00100000L 5522de2bdb3dSTom St Denis #define DISP_INTERRUPT_STATUS_CONTINUE5__AUX6_LS_DONE_INTERRUPT__SHIFT 0x00000014 5523de2bdb3dSTom St Denis #define DISP_INTERRUPT_STATUS_CONTINUE5__AUX6_SW_DONE_INTERRUPT_MASK 0x00080000L 5524de2bdb3dSTom St Denis #define DISP_INTERRUPT_STATUS_CONTINUE5__AUX6_SW_DONE_INTERRUPT__SHIFT 0x00000013 5525de2bdb3dSTom St Denis #define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_FORCE_COUNT_NOW_INTERRUPT_MASK 0x00000040L 5526de2bdb3dSTom St Denis #define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_FORCE_COUNT_NOW_INTERRUPT__SHIFT 0x00000006 5527de2bdb3dSTom St Denis #define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK 0x00000020L 5528de2bdb3dSTom St Denis #define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT 0x00000005 5529de2bdb3dSTom St Denis #define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK 0x00000400L 5530de2bdb3dSTom St Denis #define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT 0x0000000a 5531de2bdb3dSTom St Denis #define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_SNAPSHOT_INTERRUPT_MASK 0x00000010L 5532de2bdb3dSTom St Denis #define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_SNAPSHOT_INTERRUPT__SHIFT 0x00000004 5533de2bdb3dSTom St Denis #define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_TRIGA_INTERRUPT_MASK 0x00000080L 5534de2bdb3dSTom St Denis #define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_TRIGA_INTERRUPT__SHIFT 0x00000007 5535de2bdb3dSTom St Denis #define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_TRIGB_INTERRUPT_MASK 0x00000100L 5536de2bdb3dSTom St Denis #define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_TRIGB_INTERRUPT__SHIFT 0x00000008 5537de2bdb3dSTom St Denis #define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_VSYNC_NOM_INTERRUPT_MASK 0x00000200L 5538de2bdb3dSTom St Denis #define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_VSYNC_NOM_INTERRUPT__SHIFT 0x00000009 5539de2bdb3dSTom St Denis #define DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_INTERRUPT_MASK 0x00020000L 5540de2bdb3dSTom St Denis #define DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_INTERRUPT__SHIFT 0x00000011 5541de2bdb3dSTom St Denis #define DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_RX_INTERRUPT_MASK 0x00040000L 5542de2bdb3dSTom St Denis #define DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_RX_INTERRUPT__SHIFT 0x00000012 5543de2bdb3dSTom St Denis #define DISP_INTERRUPT_STATUS_CONTINUE5__DIGF_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK 0x00008000L 5544de2bdb3dSTom St Denis #define DISP_INTERRUPT_STATUS_CONTINUE5__DIGF_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT 0x0000000f 5545de2bdb3dSTom St Denis #define DISP_INTERRUPT_STATUS_CONTINUE5__DIGF_DP_VID_STREAM_DISABLE_INTERRUPT_MASK 0x00010000L 5546de2bdb3dSTom St Denis #define DISP_INTERRUPT_STATUS_CONTINUE5__DIGF_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT 0x00000010 5547de2bdb3dSTom St Denis #define DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VBLANK_INTERRUPT_MASK 0x00000008L 5548de2bdb3dSTom St Denis #define DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VBLANK_INTERRUPT__SHIFT 0x00000003 5549de2bdb3dSTom St Denis #define DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VLINE_INTERRUPT_MASK 0x00000004L 5550de2bdb3dSTom St Denis #define DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VLINE_INTERRUPT__SHIFT 0x00000002 5551de2bdb3dSTom St Denis #define DISP_INTERRUPT_STATUS_CONTINUE5__SCL_DISP6_MODE_CHANGE_INTERRUPT_MASK 0x00000001L 5552de2bdb3dSTom St Denis #define DISP_INTERRUPT_STATUS_CONTINUE5__SCL_DISP6_MODE_CHANGE_INTERRUPT__SHIFT 0x00000000 5553de2bdb3dSTom St Denis #define DISP_INTERRUPT_STATUS_CONTINUE__AUX2_LS_DONE_INTERRUPT_MASK 0x00100000L 5554de2bdb3dSTom St Denis #define DISP_INTERRUPT_STATUS_CONTINUE__AUX2_LS_DONE_INTERRUPT__SHIFT 0x00000014 5555de2bdb3dSTom St Denis #define DISP_INTERRUPT_STATUS_CONTINUE__AUX2_SW_DONE_INTERRUPT_MASK 0x00080000L 5556de2bdb3dSTom St Denis #define DISP_INTERRUPT_STATUS_CONTINUE__AUX2_SW_DONE_INTERRUPT__SHIFT 0x00000013 5557de2bdb3dSTom St Denis #define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_FORCE_COUNT_NOW_INTERRUPT_MASK 0x00000040L 5558de2bdb3dSTom St Denis #define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_FORCE_COUNT_NOW_INTERRUPT__SHIFT 0x00000006 5559de2bdb3dSTom St Denis #define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK 0x00000020L 5560de2bdb3dSTom St Denis #define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT 0x00000005 5561de2bdb3dSTom St Denis #define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK 0x00000400L 5562de2bdb3dSTom St Denis #define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT 0x0000000a 5563de2bdb3dSTom St Denis #define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_SNAPSHOT_INTERRUPT_MASK 0x00000010L 5564de2bdb3dSTom St Denis #define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_SNAPSHOT_INTERRUPT__SHIFT 0x00000004 5565de2bdb3dSTom St Denis #define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_TRIGA_INTERRUPT_MASK 0x00000080L 5566de2bdb3dSTom St Denis #define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_TRIGA_INTERRUPT__SHIFT 0x00000007 5567de2bdb3dSTom St Denis #define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_TRIGB_INTERRUPT_MASK 0x00000100L 5568de2bdb3dSTom St Denis #define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_TRIGB_INTERRUPT__SHIFT 0x00000008 5569de2bdb3dSTom St Denis #define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_VSYNC_NOM_INTERRUPT_MASK 0x00000200L 5570de2bdb3dSTom St Denis #define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_VSYNC_NOM_INTERRUPT__SHIFT 0x00000009 5571de2bdb3dSTom St Denis #define DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_INTERRUPT_MASK 0x00020000L 5572de2bdb3dSTom St Denis #define DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_INTERRUPT__SHIFT 0x00000011 5573de2bdb3dSTom St Denis #define DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_RX_INTERRUPT_MASK 0x00040000L 5574de2bdb3dSTom St Denis #define DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_RX_INTERRUPT__SHIFT 0x00000012 5575de2bdb3dSTom St Denis #define DISP_INTERRUPT_STATUS_CONTINUE__DIGB_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK 0x00008000L 5576de2bdb3dSTom St Denis #define DISP_INTERRUPT_STATUS_CONTINUE__DIGB_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT 0x0000000f 5577de2bdb3dSTom St Denis #define DISP_INTERRUPT_STATUS_CONTINUE__DIGB_DP_VID_STREAM_DISABLE_INTERRUPT_MASK 0x00010000L 5578de2bdb3dSTom St Denis #define DISP_INTERRUPT_STATUS_CONTINUE__DIGB_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT 0x00000010 5579de2bdb3dSTom St Denis #define DISP_INTERRUPT_STATUS_CONTINUE__DISP_INTERRUPT_STATUS_CONTINUE2_MASK 0x80000000L 5580de2bdb3dSTom St Denis #define DISP_INTERRUPT_STATUS_CONTINUE__DISP_INTERRUPT_STATUS_CONTINUE2__SHIFT 0x0000001f 5581de2bdb3dSTom St Denis #define DISP_INTERRUPT_STATUS_CONTINUE__DISP_TIMER_INTERRUPT_MASK 0x01000000L 5582de2bdb3dSTom St Denis #define DISP_INTERRUPT_STATUS_CONTINUE__DISP_TIMER_INTERRUPT__SHIFT 0x00000018 5583de2bdb3dSTom St Denis #define DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VBLANK_INTERRUPT_MASK 0x00000008L 5584de2bdb3dSTom St Denis #define DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VBLANK_INTERRUPT__SHIFT 0x00000003 5585de2bdb3dSTom St Denis #define DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VLINE_INTERRUPT_MASK 0x00000004L 5586de2bdb3dSTom St Denis #define DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VLINE_INTERRUPT__SHIFT 0x00000002 5587de2bdb3dSTom St Denis #define DISP_INTERRUPT_STATUS_CONTINUE__SCL_DISP2_MODE_CHANGE_INTERRUPT_MASK 0x00000001L 5588de2bdb3dSTom St Denis #define DISP_INTERRUPT_STATUS_CONTINUE__SCL_DISP2_MODE_CHANGE_INTERRUPT__SHIFT 0x00000000 5589de2bdb3dSTom St Denis #define DISP_INTERRUPT_STATUS__CRTC1_FORCE_COUNT_NOW_INTERRUPT_MASK 0x00000040L 5590de2bdb3dSTom St Denis #define DISP_INTERRUPT_STATUS__CRTC1_FORCE_COUNT_NOW_INTERRUPT__SHIFT 0x00000006 5591de2bdb3dSTom St Denis #define DISP_INTERRUPT_STATUS__CRTC1_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK 0x00000020L 5592de2bdb3dSTom St Denis #define DISP_INTERRUPT_STATUS__CRTC1_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT 0x00000005 5593de2bdb3dSTom St Denis #define DISP_INTERRUPT_STATUS__CRTC1_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK 0x00000400L 5594de2bdb3dSTom St Denis #define DISP_INTERRUPT_STATUS__CRTC1_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT 0x0000000a 5595de2bdb3dSTom St Denis #define DISP_INTERRUPT_STATUS__CRTC1_SNAPSHOT_INTERRUPT_MASK 0x00000010L 5596de2bdb3dSTom St Denis #define DISP_INTERRUPT_STATUS__CRTC1_SNAPSHOT_INTERRUPT__SHIFT 0x00000004 5597de2bdb3dSTom St Denis #define DISP_INTERRUPT_STATUS__CRTC1_TRIGA_INTERRUPT_MASK 0x00000080L 5598de2bdb3dSTom St Denis #define DISP_INTERRUPT_STATUS__CRTC1_TRIGA_INTERRUPT__SHIFT 0x00000007 5599de2bdb3dSTom St Denis #define DISP_INTERRUPT_STATUS__CRTC1_TRIGB_INTERRUPT_MASK 0x00000100L 5600de2bdb3dSTom St Denis #define DISP_INTERRUPT_STATUS__CRTC1_TRIGB_INTERRUPT__SHIFT 0x00000008 5601de2bdb3dSTom St Denis #define DISP_INTERRUPT_STATUS__CRTC1_VSYNC_NOM_INTERRUPT_MASK 0x00000200L 5602de2bdb3dSTom St Denis #define DISP_INTERRUPT_STATUS__CRTC1_VSYNC_NOM_INTERRUPT__SHIFT 0x00000009 5603de2bdb3dSTom St Denis #define DISP_INTERRUPT_STATUS__DACA_AUTODETECT_INTERRUPT_MASK 0x00400000L 5604de2bdb3dSTom St Denis #define DISP_INTERRUPT_STATUS__DACA_AUTODETECT_INTERRUPT__SHIFT 0x00000016 5605de2bdb3dSTom St Denis #define DISP_INTERRUPT_STATUS__DACB_AUTODETECT_INTERRUPT_MASK 0x00800000L 5606de2bdb3dSTom St Denis #define DISP_INTERRUPT_STATUS__DACB_AUTODETECT_INTERRUPT__SHIFT 0x00000017 5607de2bdb3dSTom St Denis #define DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT_MASK 0x00020000L 5608de2bdb3dSTom St Denis #define DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT__SHIFT 0x00000011 5609de2bdb3dSTom St Denis #define DISP_INTERRUPT_STATUS__DC_HPD1_RX_INTERRUPT_MASK 0x00040000L 5610de2bdb3dSTom St Denis #define DISP_INTERRUPT_STATUS__DC_HPD1_RX_INTERRUPT__SHIFT 0x00000012 5611de2bdb3dSTom St Denis #define DISP_INTERRUPT_STATUS__DC_I2C_HW_DONE_INTERRUPT_MASK 0x02000000L 5612de2bdb3dSTom St Denis #define DISP_INTERRUPT_STATUS__DC_I2C_HW_DONE_INTERRUPT__SHIFT 0x00000019 5613de2bdb3dSTom St Denis #define DISP_INTERRUPT_STATUS__DC_I2C_SW_DONE_INTERRUPT_MASK 0x01000000L 5614de2bdb3dSTom St Denis #define DISP_INTERRUPT_STATUS__DC_I2C_SW_DONE_INTERRUPT__SHIFT 0x00000018 5615de2bdb3dSTom St Denis #define DISP_INTERRUPT_STATUS__DIGA_DISPCLK_SWITCH_ALLOWED_INTERRUPT_MASK 0x00200000L 5616de2bdb3dSTom St Denis #define DISP_INTERRUPT_STATUS__DIGA_DISPCLK_SWITCH_ALLOWED_INTERRUPT__SHIFT 0x00000015 5617de2bdb3dSTom St Denis #define DISP_INTERRUPT_STATUS__DIGA_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK 0x00008000L 5618de2bdb3dSTom St Denis #define DISP_INTERRUPT_STATUS__DIGA_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT 0x0000000f 5619de2bdb3dSTom St Denis #define DISP_INTERRUPT_STATUS__DIGA_DP_VID_STREAM_DISABLE_INTERRUPT_MASK 0x00010000L 5620de2bdb3dSTom St Denis #define DISP_INTERRUPT_STATUS__DIGA_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT 0x00000010 5621de2bdb3dSTom St Denis #define DISP_INTERRUPT_STATUS__DISP_INTERRUPT_STATUS_CONTINUE_MASK 0x80000000L 5622de2bdb3dSTom St Denis #define DISP_INTERRUPT_STATUS__DISP_INTERRUPT_STATUS_CONTINUE__SHIFT 0x0000001f 5623de2bdb3dSTom St Denis #define DISP_INTERRUPT_STATUS__DMCU_SCP_INT_MASK 0x08000000L 5624de2bdb3dSTom St Denis #define DISP_INTERRUPT_STATUS__DMCU_SCP_INT__SHIFT 0x0000001b 5625de2bdb3dSTom St Denis #define DISP_INTERRUPT_STATUS__DMCU_UC_INTERNAL_INT_MASK 0x04000000L 5626de2bdb3dSTom St Denis #define DISP_INTERRUPT_STATUS__DMCU_UC_INTERNAL_INT__SHIFT 0x0000001a 5627de2bdb3dSTom St Denis #define DISP_INTERRUPT_STATUS__LB_D1_VBLANK_INTERRUPT_MASK 0x00000008L 5628de2bdb3dSTom St Denis #define DISP_INTERRUPT_STATUS__LB_D1_VBLANK_INTERRUPT__SHIFT 0x00000003 5629de2bdb3dSTom St Denis #define DISP_INTERRUPT_STATUS__LB_D1_VLINE_INTERRUPT_MASK 0x00000004L 5630de2bdb3dSTom St Denis #define DISP_INTERRUPT_STATUS__LB_D1_VLINE_INTERRUPT__SHIFT 0x00000002 5631de2bdb3dSTom St Denis #define DISP_INTERRUPT_STATUS__SCL_DISP1_MODE_CHANGE_INTERRUPT_MASK 0x00000001L 5632de2bdb3dSTom St Denis #define DISP_INTERRUPT_STATUS__SCL_DISP1_MODE_CHANGE_INTERRUPT__SHIFT 0x00000000 5633de2bdb3dSTom St Denis #define DISPOUT_STEREOSYNC_SEL__GENERICA_STEREOSYNC_SEL_MASK 0x00000007L 5634de2bdb3dSTom St Denis #define DISPOUT_STEREOSYNC_SEL__GENERICA_STEREOSYNC_SEL__SHIFT 0x00000000 5635de2bdb3dSTom St Denis #define DISPOUT_STEREOSYNC_SEL__GENERICB_STEREOSYNC_SEL_MASK 0x00070000L 5636de2bdb3dSTom St Denis #define DISPOUT_STEREOSYNC_SEL__GENERICB_STEREOSYNC_SEL__SHIFT 0x00000010 5637de2bdb3dSTom St Denis #define DISPPLL_BG_CNTL__DISPPLL_BG_ADJ_MASK 0x000000f0L 5638de2bdb3dSTom St Denis #define DISPPLL_BG_CNTL__DISPPLL_BG_ADJ__SHIFT 0x00000004 5639de2bdb3dSTom St Denis #define DISPPLL_BG_CNTL__DISPPLL_BG_PDN_MASK 0x00000001L 5640de2bdb3dSTom St Denis #define DISPPLL_BG_CNTL__DISPPLL_BG_PDN__SHIFT 0x00000000 5641de2bdb3dSTom St Denis #define DISP_TIMER_CONTROL__DISP_TIMER_INT_COUNT_MASK 0x01ffffffL 5642de2bdb3dSTom St Denis #define DISP_TIMER_CONTROL__DISP_TIMER_INT_COUNT__SHIFT 0x00000000 5643de2bdb3dSTom St Denis #define DISP_TIMER_CONTROL__DISP_TIMER_INT_ENABLE_MASK 0x02000000L 5644de2bdb3dSTom St Denis #define DISP_TIMER_CONTROL__DISP_TIMER_INT_ENABLE__SHIFT 0x00000019 5645de2bdb3dSTom St Denis #define DISP_TIMER_CONTROL__DISP_TIMER_INT_MASK 0x40000000L 5646de2bdb3dSTom St Denis #define DISP_TIMER_CONTROL__DISP_TIMER_INT_MSK_MASK 0x08000000L 5647de2bdb3dSTom St Denis #define DISP_TIMER_CONTROL__DISP_TIMER_INT_MSK__SHIFT 0x0000001b 5648de2bdb3dSTom St Denis #define DISP_TIMER_CONTROL__DISP_TIMER_INT_RUNNING_MASK 0x04000000L 5649de2bdb3dSTom St Denis #define DISP_TIMER_CONTROL__DISP_TIMER_INT_RUNNING__SHIFT 0x0000001a 5650de2bdb3dSTom St Denis #define DISP_TIMER_CONTROL__DISP_TIMER_INT__SHIFT 0x0000001e 5651de2bdb3dSTom St Denis #define DISP_TIMER_CONTROL__DISP_TIMER_INT_STAT_AK_MASK 0x20000000L 5652de2bdb3dSTom St Denis #define DISP_TIMER_CONTROL__DISP_TIMER_INT_STAT_AK__SHIFT 0x0000001d 5653de2bdb3dSTom St Denis #define DISP_TIMER_CONTROL__DISP_TIMER_INT_STAT_MASK 0x10000000L 5654de2bdb3dSTom St Denis #define DISP_TIMER_CONTROL__DISP_TIMER_INT_STAT__SHIFT 0x0000001c 5655de2bdb3dSTom St Denis #define DMCU_CTRL__DISABLE_IRQ_TO_UC_MASK 0x00000004L 5656de2bdb3dSTom St Denis #define DMCU_CTRL__DISABLE_IRQ_TO_UC__SHIFT 0x00000002 5657de2bdb3dSTom St Denis #define DMCU_CTRL__DISABLE_XIRQ_TO_UC_MASK 0x00000008L 5658de2bdb3dSTom St Denis #define DMCU_CTRL__DISABLE_XIRQ_TO_UC__SHIFT 0x00000003 5659de2bdb3dSTom St Denis #define DMCU_CTRL__DMCU_ENABLE_MASK 0x00000010L 5660de2bdb3dSTom St Denis #define DMCU_CTRL__DMCU_ENABLE__SHIFT 0x00000004 5661de2bdb3dSTom St Denis #define DMCU_CTRL__IGNORE_PWRMGT_MASK 0x00000002L 5662de2bdb3dSTom St Denis #define DMCU_CTRL__IGNORE_PWRMGT__SHIFT 0x00000001 5663de2bdb3dSTom St Denis #define DMCU_CTRL__RESET_UC_MASK 0x00000001L 5664de2bdb3dSTom St Denis #define DMCU_CTRL__RESET_UC__SHIFT 0x00000000 5665de2bdb3dSTom St Denis #define DMCU_CTRL__UC_REG_RD_TIMEOUT_MASK 0xffc00000L 5666de2bdb3dSTom St Denis #define DMCU_CTRL__UC_REG_RD_TIMEOUT__SHIFT 0x00000016 5667de2bdb3dSTom St Denis #define DMCU_ERAM_RD_CTRL__ERAM_RD_ADDR_MASK 0x0000ffffL 5668de2bdb3dSTom St Denis #define DMCU_ERAM_RD_CTRL__ERAM_RD_ADDR__SHIFT 0x00000000 5669de2bdb3dSTom St Denis #define DMCU_ERAM_RD_CTRL__ERAM_RD_BE_MASK 0x000f0000L 5670de2bdb3dSTom St Denis #define DMCU_ERAM_RD_CTRL__ERAM_RD_BE__SHIFT 0x00000010 5671de2bdb3dSTom St Denis #define DMCU_ERAM_RD_CTRL__ERAM_RD_BYTE_MODE_MASK 0x00100000L 5672de2bdb3dSTom St Denis #define DMCU_ERAM_RD_CTRL__ERAM_RD_BYTE_MODE__SHIFT 0x00000014 5673de2bdb3dSTom St Denis #define DMCU_ERAM_RD_DATA__ERAM_RD_DATA_MASK 0xffffffffL 5674de2bdb3dSTom St Denis #define DMCU_ERAM_RD_DATA__ERAM_RD_DATA__SHIFT 0x00000000 5675de2bdb3dSTom St Denis #define DMCU_ERAM_WR_CTRL__ERAM_WR_ADDR_MASK 0x0000ffffL 5676de2bdb3dSTom St Denis #define DMCU_ERAM_WR_CTRL__ERAM_WR_ADDR__SHIFT 0x00000000 5677de2bdb3dSTom St Denis #define DMCU_ERAM_WR_CTRL__ERAM_WR_BE_MASK 0x000f0000L 5678de2bdb3dSTom St Denis #define DMCU_ERAM_WR_CTRL__ERAM_WR_BE__SHIFT 0x00000010 5679de2bdb3dSTom St Denis #define DMCU_ERAM_WR_CTRL__ERAM_WR_BYTE_MODE_MASK 0x00100000L 5680de2bdb3dSTom St Denis #define DMCU_ERAM_WR_CTRL__ERAM_WR_BYTE_MODE__SHIFT 0x00000014 5681de2bdb3dSTom St Denis #define DMCU_ERAM_WR_DATA__ERAM_WR_DATA_MASK 0xffffffffL 5682de2bdb3dSTom St Denis #define DMCU_ERAM_WR_DATA__ERAM_WR_DATA__SHIFT 0x00000000 5683de2bdb3dSTom St Denis #define DMCU_EVENT_TRIGGER__GEN_SW_INT_TO_UC_MASK 0x00000001L 5684de2bdb3dSTom St Denis #define DMCU_EVENT_TRIGGER__GEN_SW_INT_TO_UC__SHIFT 0x00000000 5685de2bdb3dSTom St Denis #define DMCU_EVENT_TRIGGER__GEN_UC_INTERNAL_INT_TO_HOST_MASK 0x00800000L 5686de2bdb3dSTom St Denis #define DMCU_EVENT_TRIGGER__GEN_UC_INTERNAL_INT_TO_HOST__SHIFT 0x00000017 5687de2bdb3dSTom St Denis #define DMCU_EVENT_TRIGGER__UC_INTERNAL_INT_CODE_MASK 0x007f0000L 5688de2bdb3dSTom St Denis #define DMCU_EVENT_TRIGGER__UC_INTERNAL_INT_CODE__SHIFT 0x00000010 5689de2bdb3dSTom St Denis #define DMCU_FW_CHECKSUM_SMPL_BYTE_POS__DMCU_FW_CHECKSUM_HI_SMPL_BYTE_POS_MASK 0x0000000cL 5690de2bdb3dSTom St Denis #define DMCU_FW_CHECKSUM_SMPL_BYTE_POS__DMCU_FW_CHECKSUM_HI_SMPL_BYTE_POS__SHIFT 0x00000002 5691de2bdb3dSTom St Denis #define DMCU_FW_CHECKSUM_SMPL_BYTE_POS__DMCU_FW_CHECKSUM_LO_SMPL_BYTE_POS_MASK 0x00000003L 5692de2bdb3dSTom St Denis #define DMCU_FW_CHECKSUM_SMPL_BYTE_POS__DMCU_FW_CHECKSUM_LO_SMPL_BYTE_POS__SHIFT 0x00000000 5693de2bdb3dSTom St Denis #define DMCU_FW_CS_HI__FW_CHECKSUM_HI_MASK 0xffffffffL 5694de2bdb3dSTom St Denis #define DMCU_FW_CS_HI__FW_CHECKSUM_HI__SHIFT 0x00000000 5695de2bdb3dSTom St Denis #define DMCU_FW_CS_LO__FW_CHECKSUM_LO_MASK 0xffffffffL 5696de2bdb3dSTom St Denis #define DMCU_FW_CS_LO__FW_CHECKSUM_LO__SHIFT 0x00000000 5697de2bdb3dSTom St Denis #define DMCU_FW_END_ADDR__FW_END_ADDR_LSB_MASK 0x000000ffL 5698de2bdb3dSTom St Denis #define DMCU_FW_END_ADDR__FW_END_ADDR_LSB__SHIFT 0x00000000 5699de2bdb3dSTom St Denis #define DMCU_FW_END_ADDR__FW_END_ADDR_MSB_MASK 0x0000ff00L 5700de2bdb3dSTom St Denis #define DMCU_FW_END_ADDR__FW_END_ADDR_MSB__SHIFT 0x00000008 5701de2bdb3dSTom St Denis #define DMCU_FW_ISR_START_ADDR__FW_ISR_START_ADDR_LSB_MASK 0x000000ffL 5702de2bdb3dSTom St Denis #define DMCU_FW_ISR_START_ADDR__FW_ISR_START_ADDR_LSB__SHIFT 0x00000000 5703de2bdb3dSTom St Denis #define DMCU_FW_ISR_START_ADDR__FW_ISR_START_ADDR_MSB_MASK 0x0000ff00L 5704de2bdb3dSTom St Denis #define DMCU_FW_ISR_START_ADDR__FW_ISR_START_ADDR_MSB__SHIFT 0x00000008 5705de2bdb3dSTom St Denis #define DMCU_FW_START_ADDR__FW_START_ADDR_LSB_MASK 0x000000ffL 5706de2bdb3dSTom St Denis #define DMCU_FW_START_ADDR__FW_START_ADDR_LSB__SHIFT 0x00000000 5707de2bdb3dSTom St Denis #define DMCU_FW_START_ADDR__FW_START_ADDR_MSB_MASK 0x0000ff00L 5708de2bdb3dSTom St Denis #define DMCU_FW_START_ADDR__FW_START_ADDR_MSB__SHIFT 0x00000008 5709de2bdb3dSTom St Denis #define DMCU_INT_CNT__DMCU_ABM1_BL_UPDATE_INT_CNT_MASK 0x00ff0000L 5710de2bdb3dSTom St Denis #define DMCU_INT_CNT__DMCU_ABM1_BL_UPDATE_INT_CNT__SHIFT 0x00000010 5711de2bdb3dSTom St Denis #define DMCU_INT_CNT__DMCU_ABM1_HG_READY_INT_CNT_MASK 0x000000ffL 5712de2bdb3dSTom St Denis #define DMCU_INT_CNT__DMCU_ABM1_HG_READY_INT_CNT__SHIFT 0x00000000 5713de2bdb3dSTom St Denis #define DMCU_INT_CNT__DMCU_ABM1_LS_READY_INT_CNT_MASK 0x0000ff00L 5714de2bdb3dSTom St Denis #define DMCU_INT_CNT__DMCU_ABM1_LS_READY_INT_CNT__SHIFT 0x00000008 5715de2bdb3dSTom St Denis #define DMCU_INTERRUPT_STATUS__ABM1_BL_UPDATE_INT_CLEAR_MASK 0x00000004L 5716de2bdb3dSTom St Denis #define DMCU_INTERRUPT_STATUS__ABM1_BL_UPDATE_INT_CLEAR__SHIFT 0x00000002 5717de2bdb3dSTom St Denis #define DMCU_INTERRUPT_STATUS__ABM1_BL_UPDATE_INT_OCCURRED_MASK 0x00000004L 5718de2bdb3dSTom St Denis #define DMCU_INTERRUPT_STATUS__ABM1_BL_UPDATE_INT_OCCURRED__SHIFT 0x00000002 5719de2bdb3dSTom St Denis #define DMCU_INTERRUPT_STATUS__ABM1_HG_READY_INT_CLEAR_MASK 0x00000001L 5720de2bdb3dSTom St Denis #define DMCU_INTERRUPT_STATUS__ABM1_HG_READY_INT_CLEAR__SHIFT 0x00000000 5721de2bdb3dSTom St Denis #define DMCU_INTERRUPT_STATUS__ABM1_HG_READY_INT_OCCURRED_MASK 0x00000001L 5722de2bdb3dSTom St Denis #define DMCU_INTERRUPT_STATUS__ABM1_HG_READY_INT_OCCURRED__SHIFT 0x00000000 5723de2bdb3dSTom St Denis #define DMCU_INTERRUPT_STATUS__ABM1_LS_READY_INT_CLEAR_MASK 0x00000002L 5724de2bdb3dSTom St Denis #define DMCU_INTERRUPT_STATUS__ABM1_LS_READY_INT_CLEAR__SHIFT 0x00000001 5725de2bdb3dSTom St Denis #define DMCU_INTERRUPT_STATUS__ABM1_LS_READY_INT_OCCURRED_MASK 0x00000002L 5726de2bdb3dSTom St Denis #define DMCU_INTERRUPT_STATUS__ABM1_LS_READY_INT_OCCURRED__SHIFT 0x00000001 5727de2bdb3dSTom St Denis #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE0_POWER_DOWN_INT_CLEAR_MASK 0x00040000L 5728de2bdb3dSTom St Denis #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE0_POWER_DOWN_INT_CLEAR__SHIFT 0x00000012 5729de2bdb3dSTom St Denis #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE0_POWER_DOWN_INT_OCCURRED_MASK 0x00040000L 5730de2bdb3dSTom St Denis #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE0_POWER_DOWN_INT_OCCURRED__SHIFT 0x00000012 5731de2bdb3dSTom St Denis #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE0_POWER_UP_INT_CLEAR_MASK 0x00001000L 5732de2bdb3dSTom St Denis #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE0_POWER_UP_INT_CLEAR__SHIFT 0x0000000c 5733de2bdb3dSTom St Denis #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE0_POWER_UP_INT_OCCURRED_MASK 0x00001000L 5734de2bdb3dSTom St Denis #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE0_POWER_UP_INT_OCCURRED__SHIFT 0x0000000c 5735de2bdb3dSTom St Denis #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE1_POWER_DOWN_INT_CLEAR_MASK 0x00080000L 5736de2bdb3dSTom St Denis #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE1_POWER_DOWN_INT_CLEAR__SHIFT 0x00000013 5737de2bdb3dSTom St Denis #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE1_POWER_DOWN_INT_OCCURRED_MASK 0x00080000L 5738de2bdb3dSTom St Denis #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE1_POWER_DOWN_INT_OCCURRED__SHIFT 0x00000013 5739de2bdb3dSTom St Denis #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE1_POWER_UP_INT_CLEAR_MASK 0x00002000L 5740de2bdb3dSTom St Denis #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE1_POWER_UP_INT_CLEAR__SHIFT 0x0000000d 5741de2bdb3dSTom St Denis #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE1_POWER_UP_INT_OCCURRED_MASK 0x00002000L 5742de2bdb3dSTom St Denis #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE1_POWER_UP_INT_OCCURRED__SHIFT 0x0000000d 5743de2bdb3dSTom St Denis #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE2_POWER_DOWN_INT_CLEAR_MASK 0x00100000L 5744de2bdb3dSTom St Denis #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE2_POWER_DOWN_INT_CLEAR__SHIFT 0x00000014 5745de2bdb3dSTom St Denis #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE2_POWER_DOWN_INT_OCCURRED_MASK 0x00100000L 5746de2bdb3dSTom St Denis #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE2_POWER_DOWN_INT_OCCURRED__SHIFT 0x00000014 5747de2bdb3dSTom St Denis #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE2_POWER_UP_INT_CLEAR_MASK 0x00004000L 5748de2bdb3dSTom St Denis #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE2_POWER_UP_INT_CLEAR__SHIFT 0x0000000e 5749de2bdb3dSTom St Denis #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE2_POWER_UP_INT_OCCURRED_MASK 0x00004000L 5750de2bdb3dSTom St Denis #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE2_POWER_UP_INT_OCCURRED__SHIFT 0x0000000e 5751de2bdb3dSTom St Denis #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE3_POWER_DOWN_INT_CLEAR_MASK 0x00200000L 5752de2bdb3dSTom St Denis #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE3_POWER_DOWN_INT_CLEAR__SHIFT 0x00000015 5753de2bdb3dSTom St Denis #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE3_POWER_DOWN_INT_OCCURRED_MASK 0x00200000L 5754de2bdb3dSTom St Denis #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE3_POWER_DOWN_INT_OCCURRED__SHIFT 0x00000015 5755de2bdb3dSTom St Denis #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE3_POWER_UP_INT_CLEAR_MASK 0x00008000L 5756de2bdb3dSTom St Denis #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE3_POWER_UP_INT_CLEAR__SHIFT 0x0000000f 5757de2bdb3dSTom St Denis #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE3_POWER_UP_INT_OCCURRED_MASK 0x00008000L 5758de2bdb3dSTom St Denis #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE3_POWER_UP_INT_OCCURRED__SHIFT 0x0000000f 5759de2bdb3dSTom St Denis #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE4_POWER_DOWN_INT_CLEAR_MASK 0x00400000L 5760de2bdb3dSTom St Denis #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE4_POWER_DOWN_INT_CLEAR__SHIFT 0x00000016 5761de2bdb3dSTom St Denis #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE4_POWER_DOWN_INT_OCCURRED_MASK 0x00400000L 5762de2bdb3dSTom St Denis #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE4_POWER_DOWN_INT_OCCURRED__SHIFT 0x00000016 5763de2bdb3dSTom St Denis #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE4_POWER_UP_INT_CLEAR_MASK 0x00010000L 5764de2bdb3dSTom St Denis #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE4_POWER_UP_INT_CLEAR__SHIFT 0x00000010 5765de2bdb3dSTom St Denis #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE4_POWER_UP_INT_OCCURRED_MASK 0x00010000L 5766de2bdb3dSTom St Denis #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE4_POWER_UP_INT_OCCURRED__SHIFT 0x00000010 5767de2bdb3dSTom St Denis #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE5_POWER_DOWN_INT_CLEAR_MASK 0x00800000L 5768de2bdb3dSTom St Denis #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE5_POWER_DOWN_INT_CLEAR__SHIFT 0x00000017 5769de2bdb3dSTom St Denis #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE5_POWER_DOWN_INT_OCCURRED_MASK 0x00800000L 5770de2bdb3dSTom St Denis #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE5_POWER_DOWN_INT_OCCURRED__SHIFT 0x00000017 5771de2bdb3dSTom St Denis #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE5_POWER_UP_INT_CLEAR_MASK 0x00020000L 5772de2bdb3dSTom St Denis #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE5_POWER_UP_INT_CLEAR__SHIFT 0x00000011 5773de2bdb3dSTom St Denis #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE5_POWER_UP_INT_OCCURRED_MASK 0x00020000L 5774de2bdb3dSTom St Denis #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE5_POWER_UP_INT_OCCURRED__SHIFT 0x00000011 5775de2bdb3dSTom St Denis #define DMCU_INTERRUPT_STATUS__EXTERNAL_SW_INT_CLEAR_MASK 0x00000100L 5776de2bdb3dSTom St Denis #define DMCU_INTERRUPT_STATUS__EXTERNAL_SW_INT_CLEAR__SHIFT 0x00000008 5777de2bdb3dSTom St Denis #define DMCU_INTERRUPT_STATUS__EXTERNAL_SW_INT_OCCURRED_MASK 0x00000100L 5778de2bdb3dSTom St Denis #define DMCU_INTERRUPT_STATUS__EXTERNAL_SW_INT_OCCURRED__SHIFT 0x00000008 5779de2bdb3dSTom St Denis #define DMCU_INTERRUPT_STATUS__MCP_INT_OCCURRED_MASK 0x00000008L 5780de2bdb3dSTom St Denis #define DMCU_INTERRUPT_STATUS__MCP_INT_OCCURRED__SHIFT 0x00000003 5781de2bdb3dSTom St Denis #define DMCU_INTERRUPT_STATUS__SCP_INT_OCCURRED_MASK 0x00000200L 5782de2bdb3dSTom St Denis #define DMCU_INTERRUPT_STATUS__SCP_INT_OCCURRED__SHIFT 0x00000009 5783de2bdb3dSTom St Denis #define DMCU_INTERRUPT_STATUS__UC_INTERNAL_INT_CLEAR_MASK 0x00000400L 5784de2bdb3dSTom St Denis #define DMCU_INTERRUPT_STATUS__UC_INTERNAL_INT_CLEAR__SHIFT 0x0000000a 5785de2bdb3dSTom St Denis #define DMCU_INTERRUPT_STATUS__UC_INTERNAL_INT_OCCURRED_MASK 0x00000400L 5786de2bdb3dSTom St Denis #define DMCU_INTERRUPT_STATUS__UC_INTERNAL_INT_OCCURRED__SHIFT 0x0000000a 5787de2bdb3dSTom St Denis #define DMCU_INTERRUPT_STATUS__UC_REG_RD_TIMEOUT_INT_CLEAR_MASK 0x00000800L 5788de2bdb3dSTom St Denis #define DMCU_INTERRUPT_STATUS__UC_REG_RD_TIMEOUT_INT_CLEAR__SHIFT 0x0000000b 5789de2bdb3dSTom St Denis #define DMCU_INTERRUPT_STATUS__UC_REG_RD_TIMEOUT_INT_OCCURRED_MASK 0x00000800L 5790de2bdb3dSTom St Denis #define DMCU_INTERRUPT_STATUS__UC_REG_RD_TIMEOUT_INT_OCCURRED__SHIFT 0x0000000b 5791de2bdb3dSTom St Denis #define DMCU_INTERRUPT_STATUS__VBLANK1_INT_CLEAR_MASK 0x01000000L 5792de2bdb3dSTom St Denis #define DMCU_INTERRUPT_STATUS__VBLANK1_INT_CLEAR__SHIFT 0x00000018 5793de2bdb3dSTom St Denis #define DMCU_INTERRUPT_STATUS__VBLANK1_INT_OCCURRED_MASK 0x01000000L 5794de2bdb3dSTom St Denis #define DMCU_INTERRUPT_STATUS__VBLANK1_INT_OCCURRED__SHIFT 0x00000018 5795de2bdb3dSTom St Denis #define DMCU_INTERRUPT_STATUS__VBLANK2_INT_CLEAR_MASK 0x02000000L 5796de2bdb3dSTom St Denis #define DMCU_INTERRUPT_STATUS__VBLANK2_INT_CLEAR__SHIFT 0x00000019 5797de2bdb3dSTom St Denis #define DMCU_INTERRUPT_STATUS__VBLANK2_INT_OCCURRED_MASK 0x02000000L 5798de2bdb3dSTom St Denis #define DMCU_INTERRUPT_STATUS__VBLANK2_INT_OCCURRED__SHIFT 0x00000019 5799de2bdb3dSTom St Denis #define DMCU_INTERRUPT_STATUS__VBLANK3_INT_CLEAR_MASK 0x04000000L 5800de2bdb3dSTom St Denis #define DMCU_INTERRUPT_STATUS__VBLANK3_INT_CLEAR__SHIFT 0x0000001a 5801de2bdb3dSTom St Denis #define DMCU_INTERRUPT_STATUS__VBLANK3_INT_OCCURRED_MASK 0x04000000L 5802de2bdb3dSTom St Denis #define DMCU_INTERRUPT_STATUS__VBLANK3_INT_OCCURRED__SHIFT 0x0000001a 5803de2bdb3dSTom St Denis #define DMCU_INTERRUPT_STATUS__VBLANK4_INT_CLEAR_MASK 0x08000000L 5804de2bdb3dSTom St Denis #define DMCU_INTERRUPT_STATUS__VBLANK4_INT_CLEAR__SHIFT 0x0000001b 5805de2bdb3dSTom St Denis #define DMCU_INTERRUPT_STATUS__VBLANK4_INT_OCCURRED_MASK 0x08000000L 5806de2bdb3dSTom St Denis #define DMCU_INTERRUPT_STATUS__VBLANK4_INT_OCCURRED__SHIFT 0x0000001b 5807de2bdb3dSTom St Denis #define DMCU_INTERRUPT_STATUS__VBLANK5_INT_CLEAR_MASK 0x10000000L 5808de2bdb3dSTom St Denis #define DMCU_INTERRUPT_STATUS__VBLANK5_INT_CLEAR__SHIFT 0x0000001c 5809de2bdb3dSTom St Denis #define DMCU_INTERRUPT_STATUS__VBLANK5_INT_OCCURRED_MASK 0x10000000L 5810de2bdb3dSTom St Denis #define DMCU_INTERRUPT_STATUS__VBLANK5_INT_OCCURRED__SHIFT 0x0000001c 5811de2bdb3dSTom St Denis #define DMCU_INTERRUPT_STATUS__VBLANK6_INT_CLEAR_MASK 0x20000000L 5812de2bdb3dSTom St Denis #define DMCU_INTERRUPT_STATUS__VBLANK6_INT_CLEAR__SHIFT 0x0000001d 5813de2bdb3dSTom St Denis #define DMCU_INTERRUPT_STATUS__VBLANK6_INT_OCCURRED_MASK 0x20000000L 5814de2bdb3dSTom St Denis #define DMCU_INTERRUPT_STATUS__VBLANK6_INT_OCCURRED__SHIFT 0x0000001d 5815de2bdb3dSTom St Denis #define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM1_BL_UPDATE_INT_MASK_MASK 0x00000004L 5816de2bdb3dSTom St Denis #define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM1_BL_UPDATE_INT_MASK__SHIFT 0x00000002 5817de2bdb3dSTom St Denis #define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM1_HG_READY_INT_MASK_MASK 0x00000001L 5818de2bdb3dSTom St Denis #define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM1_HG_READY_INT_MASK__SHIFT 0x00000000 5819de2bdb3dSTom St Denis #define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM1_LS_READY_INT_MASK_MASK 0x00000002L 5820de2bdb3dSTom St Denis #define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM1_LS_READY_INT_MASK__SHIFT 0x00000001 5821de2bdb3dSTom St Denis #define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE0_POWER_DOWN_INT_MASK_MASK 0x00040000L 5822de2bdb3dSTom St Denis #define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE0_POWER_DOWN_INT_MASK__SHIFT 0x00000012 5823de2bdb3dSTom St Denis #define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE0_POWER_UP_INT_MASK_MASK 0x00001000L 5824de2bdb3dSTom St Denis #define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE0_POWER_UP_INT_MASK__SHIFT 0x0000000c 5825de2bdb3dSTom St Denis #define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE1_POWER_DOWN_INT_MASK_MASK 0x00080000L 5826de2bdb3dSTom St Denis #define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE1_POWER_DOWN_INT_MASK__SHIFT 0x00000013 5827de2bdb3dSTom St Denis #define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE1_POWER_UP_INT_MASK_MASK 0x00002000L 5828de2bdb3dSTom St Denis #define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE1_POWER_UP_INT_MASK__SHIFT 0x0000000d 5829de2bdb3dSTom St Denis #define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE2_POWER_DOWN_INT_MASK_MASK 0x00100000L 5830de2bdb3dSTom St Denis #define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE2_POWER_DOWN_INT_MASK__SHIFT 0x00000014 5831de2bdb3dSTom St Denis #define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE2_POWER_UP_INT_MASK_MASK 0x00004000L 5832de2bdb3dSTom St Denis #define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE2_POWER_UP_INT_MASK__SHIFT 0x0000000e 5833de2bdb3dSTom St Denis #define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE3_POWER_DOWN_INT_MASK_MASK 0x00200000L 5834de2bdb3dSTom St Denis #define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE3_POWER_DOWN_INT_MASK__SHIFT 0x00000015 5835de2bdb3dSTom St Denis #define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE3_POWER_UP_INT_MASK_MASK 0x00008000L 5836de2bdb3dSTom St Denis #define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE3_POWER_UP_INT_MASK__SHIFT 0x0000000f 5837de2bdb3dSTom St Denis #define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE4_POWER_DOWN_INT_MASK_MASK 0x00400000L 5838de2bdb3dSTom St Denis #define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE4_POWER_DOWN_INT_MASK__SHIFT 0x00000016 5839de2bdb3dSTom St Denis #define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE4_POWER_UP_INT_MASK_MASK 0x00010000L 5840de2bdb3dSTom St Denis #define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE4_POWER_UP_INT_MASK__SHIFT 0x00000010 5841de2bdb3dSTom St Denis #define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE5_POWER_DOWN_INT_MASK_MASK 0x00800000L 5842de2bdb3dSTom St Denis #define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE5_POWER_DOWN_INT_MASK__SHIFT 0x00000017 5843de2bdb3dSTom St Denis #define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE5_POWER_UP_INT_MASK_MASK 0x00020000L 5844de2bdb3dSTom St Denis #define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE5_POWER_UP_INT_MASK__SHIFT 0x00000011 5845de2bdb3dSTom St Denis #define DMCU_INTERRUPT_TO_HOST_EN_MASK__SCP_INT_MASK_MASK 0x00000200L 5846de2bdb3dSTom St Denis #define DMCU_INTERRUPT_TO_HOST_EN_MASK__SCP_INT_MASK__SHIFT 0x00000009 5847de2bdb3dSTom St Denis #define DMCU_INTERRUPT_TO_HOST_EN_MASK__UC_INTERNAL_INT_MASK_MASK 0x00000400L 5848de2bdb3dSTom St Denis #define DMCU_INTERRUPT_TO_HOST_EN_MASK__UC_INTERNAL_INT_MASK__SHIFT 0x0000000a 5849de2bdb3dSTom St Denis #define DMCU_INTERRUPT_TO_HOST_EN_MASK__UC_REG_RD_TIMEOUT_INT_MASK_MASK 0x00000800L 5850de2bdb3dSTom St Denis #define DMCU_INTERRUPT_TO_HOST_EN_MASK__UC_REG_RD_TIMEOUT_INT_MASK__SHIFT 0x0000000b 5851de2bdb3dSTom St Denis #define DMCU_INTERRUPT_TO_UC_EN_MASK__ABM1_BL_UPDATE_INT_TO_UC_EN_MASK 0x00000004L 5852de2bdb3dSTom St Denis #define DMCU_INTERRUPT_TO_UC_EN_MASK__ABM1_BL_UPDATE_INT_TO_UC_EN__SHIFT 0x00000002 5853de2bdb3dSTom St Denis #define DMCU_INTERRUPT_TO_UC_EN_MASK__ABM1_HG_READY_INT_TO_UC_EN_MASK 0x00000001L 5854de2bdb3dSTom St Denis #define DMCU_INTERRUPT_TO_UC_EN_MASK__ABM1_HG_READY_INT_TO_UC_EN__SHIFT 0x00000000 5855de2bdb3dSTom St Denis #define DMCU_INTERRUPT_TO_UC_EN_MASK__ABM1_LS_READY_INT_TO_UC_EN_MASK 0x00000002L 5856de2bdb3dSTom St Denis #define DMCU_INTERRUPT_TO_UC_EN_MASK__ABM1_LS_READY_INT_TO_UC_EN__SHIFT 0x00000001 5857de2bdb3dSTom St Denis #define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE0_POWER_DOWN_INT_TO_UC_EN_MASK 0x00040000L 5858de2bdb3dSTom St Denis #define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE0_POWER_DOWN_INT_TO_UC_EN__SHIFT 0x00000012 5859de2bdb3dSTom St Denis #define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE0_POWER_UP_INT_TO_UC_EN_MASK 0x00001000L 5860de2bdb3dSTom St Denis #define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE0_POWER_UP_INT_TO_UC_EN__SHIFT 0x0000000c 5861de2bdb3dSTom St Denis #define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE1_POWER_DOWN_INT_TO_UC_EN_MASK 0x00080000L 5862de2bdb3dSTom St Denis #define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE1_POWER_DOWN_INT_TO_UC_EN__SHIFT 0x00000013 5863de2bdb3dSTom St Denis #define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE1_POWER_UP_INT_TO_UC_EN_MASK 0x00002000L 5864de2bdb3dSTom St Denis #define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE1_POWER_UP_INT_TO_UC_EN__SHIFT 0x0000000d 5865de2bdb3dSTom St Denis #define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE2_POWER_DOWN_INT_TO_UC_EN_MASK 0x00100000L 5866de2bdb3dSTom St Denis #define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE2_POWER_DOWN_INT_TO_UC_EN__SHIFT 0x00000014 5867de2bdb3dSTom St Denis #define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE2_POWER_UP_INT_TO_UC_EN_MASK 0x00004000L 5868de2bdb3dSTom St Denis #define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE2_POWER_UP_INT_TO_UC_EN__SHIFT 0x0000000e 5869de2bdb3dSTom St Denis #define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE3_POWER_DOWN_INT_TO_UC_EN_MASK 0x00200000L 5870de2bdb3dSTom St Denis #define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE3_POWER_DOWN_INT_TO_UC_EN__SHIFT 0x00000015 5871de2bdb3dSTom St Denis #define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE3_POWER_UP_INT_TO_UC_EN_MASK 0x00008000L 5872de2bdb3dSTom St Denis #define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE3_POWER_UP_INT_TO_UC_EN__SHIFT 0x0000000f 5873de2bdb3dSTom St Denis #define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE4_POWER_DOWN_INT_TO_UC_EN_MASK 0x00400000L 5874de2bdb3dSTom St Denis #define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE4_POWER_DOWN_INT_TO_UC_EN__SHIFT 0x00000016 5875de2bdb3dSTom St Denis #define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE4_POWER_UP_INT_TO_UC_EN_MASK 0x00010000L 5876de2bdb3dSTom St Denis #define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE4_POWER_UP_INT_TO_UC_EN__SHIFT 0x00000010 5877de2bdb3dSTom St Denis #define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE5_POWER_DOWN_INT_TO_UC_EN_MASK 0x00800000L 5878de2bdb3dSTom St Denis #define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE5_POWER_DOWN_INT_TO_UC_EN__SHIFT 0x00000017 5879de2bdb3dSTom St Denis #define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE5_POWER_UP_INT_TO_UC_EN_MASK 0x00020000L 5880de2bdb3dSTom St Denis #define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE5_POWER_UP_INT_TO_UC_EN__SHIFT 0x00000011 5881de2bdb3dSTom St Denis #define DMCU_INTERRUPT_TO_UC_EN_MASK__EXTERNAL_SW_INT_TO_UC_EN_MASK 0x00000100L 5882de2bdb3dSTom St Denis #define DMCU_INTERRUPT_TO_UC_EN_MASK__EXTERNAL_SW_INT_TO_UC_EN__SHIFT 0x00000008 5883de2bdb3dSTom St Denis #define DMCU_INTERRUPT_TO_UC_EN_MASK__MCP_INT_TO_UC_EN_MASK 0x00000008L 5884de2bdb3dSTom St Denis #define DMCU_INTERRUPT_TO_UC_EN_MASK__MCP_INT_TO_UC_EN__SHIFT 0x00000003 5885de2bdb3dSTom St Denis #define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK1_INT_TO_UC_EN_MASK 0x01000000L 5886de2bdb3dSTom St Denis #define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK1_INT_TO_UC_EN__SHIFT 0x00000018 5887de2bdb3dSTom St Denis #define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK2_INT_TO_UC_EN_MASK 0x02000000L 5888de2bdb3dSTom St Denis #define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK2_INT_TO_UC_EN__SHIFT 0x00000019 5889de2bdb3dSTom St Denis #define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK3_INT_TO_UC_EN_MASK 0x04000000L 5890de2bdb3dSTom St Denis #define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK3_INT_TO_UC_EN__SHIFT 0x0000001a 5891de2bdb3dSTom St Denis #define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK4_INT_TO_UC_EN_MASK 0x08000000L 5892de2bdb3dSTom St Denis #define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK4_INT_TO_UC_EN__SHIFT 0x0000001b 5893de2bdb3dSTom St Denis #define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK5_INT_TO_UC_EN_MASK 0x10000000L 5894de2bdb3dSTom St Denis #define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK5_INT_TO_UC_EN__SHIFT 0x0000001c 5895de2bdb3dSTom St Denis #define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK6_INT_TO_UC_EN_MASK 0x20000000L 5896de2bdb3dSTom St Denis #define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK6_INT_TO_UC_EN__SHIFT 0x0000001d 5897de2bdb3dSTom St Denis #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__ABM1_BL_UPDATE_INT_XIRQ_IRQ_SEL_MASK 0x00000004L 5898de2bdb3dSTom St Denis #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__ABM1_BL_UPDATE_INT_XIRQ_IRQ_SEL__SHIFT 0x00000002 5899de2bdb3dSTom St Denis #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__ABM1_HG_READY_INT_XIRQ_IRQ_SEL_MASK 0x00000001L 5900de2bdb3dSTom St Denis #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__ABM1_HG_READY_INT_XIRQ_IRQ_SEL__SHIFT 0x00000000 5901de2bdb3dSTom St Denis #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__ABM1_LS_READY_INT_XIRQ_IRQ_SEL_MASK 0x00000002L 5902de2bdb3dSTom St Denis #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__ABM1_LS_READY_INT_XIRQ_IRQ_SEL__SHIFT 0x00000001 5903de2bdb3dSTom St Denis #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE0_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK 0x00040000L 5904de2bdb3dSTom St Denis #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE0_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT 0x00000012 5905de2bdb3dSTom St Denis #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE0_POWER_UP_INT_XIRQ_IRQ_SEL_MASK 0x00001000L 5906de2bdb3dSTom St Denis #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE0_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT 0x0000000c 5907de2bdb3dSTom St Denis #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE1_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK 0x00080000L 5908de2bdb3dSTom St Denis #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE1_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT 0x00000013 5909de2bdb3dSTom St Denis #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE1_POWER_UP_INT_XIRQ_IRQ_SEL_MASK 0x00002000L 5910de2bdb3dSTom St Denis #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE1_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT 0x0000000d 5911de2bdb3dSTom St Denis #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE2_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK 0x00100000L 5912de2bdb3dSTom St Denis #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE2_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT 0x00000014 5913de2bdb3dSTom St Denis #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE2_POWER_UP_INT_XIRQ_IRQ_SEL_MASK 0x00004000L 5914de2bdb3dSTom St Denis #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE2_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT 0x0000000e 5915de2bdb3dSTom St Denis #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE3_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK 0x00200000L 5916de2bdb3dSTom St Denis #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE3_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT 0x00000015 5917de2bdb3dSTom St Denis #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE3_POWER_UP_INT_XIRQ_IRQ_SEL_MASK 0x00008000L 5918de2bdb3dSTom St Denis #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE3_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT 0x0000000f 5919de2bdb3dSTom St Denis #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE4_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK 0x00400000L 5920de2bdb3dSTom St Denis #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE4_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT 0x00000016 5921de2bdb3dSTom St Denis #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE4_POWER_UP_INT_XIRQ_IRQ_SEL_MASK 0x00010000L 5922de2bdb3dSTom St Denis #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE4_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT 0x00000010 5923de2bdb3dSTom St Denis #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE5_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK 0x00800000L 5924de2bdb3dSTom St Denis #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE5_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT 0x00000017 5925de2bdb3dSTom St Denis #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE5_POWER_UP_INT_XIRQ_IRQ_SEL_MASK 0x00020000L 5926de2bdb3dSTom St Denis #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE5_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT 0x00000011 5927de2bdb3dSTom St Denis #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__EXTERNAL_SW_INT_XIRQ_IRQ_SEL_MASK 0x00000100L 5928de2bdb3dSTom St Denis #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__EXTERNAL_SW_INT_XIRQ_IRQ_SEL__SHIFT 0x00000008 5929de2bdb3dSTom St Denis #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__MCP_INT_XIRQ_IRQ_SEL_MASK 0x00000008L 5930de2bdb3dSTom St Denis #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__MCP_INT_XIRQ_IRQ_SEL__SHIFT 0x00000003 5931de2bdb3dSTom St Denis #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK1_INT_XIRQ_IRQ_SEL_MASK 0x01000000L 5932de2bdb3dSTom St Denis #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK1_INT_XIRQ_IRQ_SEL__SHIFT 0x00000018 5933de2bdb3dSTom St Denis #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK2_INT_XIRQ_IRQ_SEL_MASK 0x02000000L 5934de2bdb3dSTom St Denis #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK2_INT_XIRQ_IRQ_SEL__SHIFT 0x00000019 5935de2bdb3dSTom St Denis #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK3_INT_XIRQ_IRQ_SEL_MASK 0x04000000L 5936de2bdb3dSTom St Denis #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK3_INT_XIRQ_IRQ_SEL__SHIFT 0x0000001a 5937de2bdb3dSTom St Denis #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK4_INT_XIRQ_IRQ_SEL_MASK 0x08000000L 5938de2bdb3dSTom St Denis #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK4_INT_XIRQ_IRQ_SEL__SHIFT 0x0000001b 5939de2bdb3dSTom St Denis #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK5_INT_XIRQ_IRQ_SEL_MASK 0x10000000L 5940de2bdb3dSTom St Denis #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK5_INT_XIRQ_IRQ_SEL__SHIFT 0x0000001c 5941de2bdb3dSTom St Denis #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK6_INT_XIRQ_IRQ_SEL_MASK 0x20000000L 5942de2bdb3dSTom St Denis #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK6_INT_XIRQ_IRQ_SEL__SHIFT 0x0000001d 5943de2bdb3dSTom St Denis #define DMCU_IRAM_RD_CTRL__IRAM_RD_ADDR_MASK 0x000003ffL 5944de2bdb3dSTom St Denis #define DMCU_IRAM_RD_CTRL__IRAM_RD_ADDR__SHIFT 0x00000000 5945de2bdb3dSTom St Denis #define DMCU_IRAM_RD_DATA__IRAM_RD_DATA_MASK 0x000000ffL 5946de2bdb3dSTom St Denis #define DMCU_IRAM_RD_DATA__IRAM_RD_DATA__SHIFT 0x00000000 5947de2bdb3dSTom St Denis #define DMCU_IRAM_WR_CTRL__IRAM_WR_ADDR_MASK 0x000003ffL 5948de2bdb3dSTom St Denis #define DMCU_IRAM_WR_CTRL__IRAM_WR_ADDR__SHIFT 0x00000000 5949de2bdb3dSTom St Denis #define DMCU_IRAM_WR_DATA__IRAM_WR_DATA_MASK 0x000000ffL 5950de2bdb3dSTom St Denis #define DMCU_IRAM_WR_DATA__IRAM_WR_DATA__SHIFT 0x00000000 5951de2bdb3dSTom St Denis #define DMCU_PC_START_ADDR__PC_START_ADDR_LSB_MASK 0x000000ffL 5952de2bdb3dSTom St Denis #define DMCU_PC_START_ADDR__PC_START_ADDR_LSB__SHIFT 0x00000000 5953de2bdb3dSTom St Denis #define DMCU_PC_START_ADDR__PC_START_ADDR_MSB_MASK 0x0000ff00L 5954de2bdb3dSTom St Denis #define DMCU_PC_START_ADDR__PC_START_ADDR_MSB__SHIFT 0x00000008 5955de2bdb3dSTom St Denis #define DMCU_RAM_ACCESS_CTRL__ERAM_HOST_ACCESS_EN_MASK 0x00000010L 5956de2bdb3dSTom St Denis #define DMCU_RAM_ACCESS_CTRL__ERAM_HOST_ACCESS_EN__SHIFT 0x00000004 5957de2bdb3dSTom St Denis #define DMCU_RAM_ACCESS_CTRL__ERAM_RD_ADDR_AUTO_INC_MASK 0x00000002L 5958de2bdb3dSTom St Denis #define DMCU_RAM_ACCESS_CTRL__ERAM_RD_ADDR_AUTO_INC__SHIFT 0x00000001 5959de2bdb3dSTom St Denis #define DMCU_RAM_ACCESS_CTRL__ERAM_WR_ADDR_AUTO_INC_MASK 0x00000001L 5960de2bdb3dSTom St Denis #define DMCU_RAM_ACCESS_CTRL__ERAM_WR_ADDR_AUTO_INC__SHIFT 0x00000000 5961de2bdb3dSTom St Denis #define DMCU_RAM_ACCESS_CTRL__IRAM_HOST_ACCESS_EN_MASK 0x00000020L 5962de2bdb3dSTom St Denis #define DMCU_RAM_ACCESS_CTRL__IRAM_HOST_ACCESS_EN__SHIFT 0x00000005 5963de2bdb3dSTom St Denis #define DMCU_RAM_ACCESS_CTRL__IRAM_RD_ADDR_AUTO_INC_MASK 0x00000008L 5964de2bdb3dSTom St Denis #define DMCU_RAM_ACCESS_CTRL__IRAM_RD_ADDR_AUTO_INC__SHIFT 0x00000003 5965de2bdb3dSTom St Denis #define DMCU_RAM_ACCESS_CTRL__IRAM_WR_ADDR_AUTO_INC_MASK 0x00000004L 5966de2bdb3dSTom St Denis #define DMCU_RAM_ACCESS_CTRL__IRAM_WR_ADDR_AUTO_INC__SHIFT 0x00000002 5967de2bdb3dSTom St Denis #define DMCU_RAM_ACCESS_CTRL__UC_RST_RELEASE_DELAY_CNT_MASK 0x0000ff00L 5968de2bdb3dSTom St Denis #define DMCU_RAM_ACCESS_CTRL__UC_RST_RELEASE_DELAY_CNT__SHIFT 0x00000008 5969de2bdb3dSTom St Denis #define DMCU_STATUS__UC_IN_RESET_MASK 0x00000001L 5970de2bdb3dSTom St Denis #define DMCU_STATUS__UC_IN_RESET__SHIFT 0x00000000 5971de2bdb3dSTom St Denis #define DMCU_STATUS__UC_IN_STOP_MODE_MASK 0x00000004L 5972de2bdb3dSTom St Denis #define DMCU_STATUS__UC_IN_STOP_MODE__SHIFT 0x00000002 5973de2bdb3dSTom St Denis #define DMCU_STATUS__UC_IN_WAIT_MODE_MASK 0x00000002L 5974de2bdb3dSTom St Denis #define DMCU_STATUS__UC_IN_WAIT_MODE__SHIFT 0x00000001 5975de2bdb3dSTom St Denis #define DMCU_TEST_DEBUG_DATA__DMCU_TEST_DEBUG_DATA_MASK 0xffffffffL 5976de2bdb3dSTom St Denis #define DMCU_TEST_DEBUG_DATA__DMCU_TEST_DEBUG_DATA__SHIFT 0x00000000 5977de2bdb3dSTom St Denis #define DMCU_TEST_DEBUG_INDEX__DMCU_TEST_DEBUG_INDEX_MASK 0x000000ffL 5978de2bdb3dSTom St Denis #define DMCU_TEST_DEBUG_INDEX__DMCU_TEST_DEBUG_INDEX__SHIFT 0x00000000 5979de2bdb3dSTom St Denis #define DMCU_TEST_DEBUG_INDEX__DMCU_TEST_DEBUG_WRITE_EN_MASK 0x00000100L 5980de2bdb3dSTom St Denis #define DMCU_TEST_DEBUG_INDEX__DMCU_TEST_DEBUG_WRITE_EN__SHIFT 0x00000008 5981de2bdb3dSTom St Denis #define DMCU_UC_CLK_GATING_CNTL__UC_ERAM_RD_DELAY_MASK 0x00000700L 5982de2bdb3dSTom St Denis #define DMCU_UC_CLK_GATING_CNTL__UC_ERAM_RD_DELAY__SHIFT 0x00000008 5983de2bdb3dSTom St Denis #define DMCU_UC_CLK_GATING_CNTL__UC_IRAM_RD_DELAY_MASK 0x00000007L 5984de2bdb3dSTom St Denis #define DMCU_UC_CLK_GATING_CNTL__UC_IRAM_RD_DELAY__SHIFT 0x00000000 5985de2bdb3dSTom St Denis #define DMCU_UC_CLK_GATING_CNTL__UC_RBBM_RD_CLK_GATING_EN_MASK 0x00010000L 5986de2bdb3dSTom St Denis #define DMCU_UC_CLK_GATING_CNTL__UC_RBBM_RD_CLK_GATING_EN__SHIFT 0x00000010 5987de2bdb3dSTom St Denis #define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_ILLEGAL_OPCODE_TRAP_MASK 0x00000008L 5988de2bdb3dSTom St Denis #define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_ILLEGAL_OPCODE_TRAP__SHIFT 0x00000003 5989de2bdb3dSTom St Denis #define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_IRQ_N_PIN_MASK 0x00000001L 5990de2bdb3dSTom St Denis #define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_IRQ_N_PIN__SHIFT 0x00000000 5991de2bdb3dSTom St Denis #define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_PULSE_ACCUMULATOR_INPUT_EDGE_MASK 0x00004000L 5992de2bdb3dSTom St Denis #define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_PULSE_ACCUMULATOR_INPUT_EDGE__SHIFT 0x0000000e 5993de2bdb3dSTom St Denis #define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_PULSE_ACCUMULATOR_OVERFLOW_MASK 0x00008000L 5994de2bdb3dSTom St Denis #define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_PULSE_ACCUMULATOR_OVERFLOW__SHIFT 0x0000000f 5995de2bdb3dSTom St Denis #define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_REAL_TIME_INTERRUPT_MASK 0x00000200L 5996de2bdb3dSTom St Denis #define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_REAL_TIME_INTERRUPT__SHIFT 0x00000009 5997de2bdb3dSTom St Denis #define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_SOFTWARE_INTERRUPT_MASK 0x00000004L 5998de2bdb3dSTom St Denis #define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_SOFTWARE_INTERRUPT__SHIFT 0x00000002 5999de2bdb3dSTom St Denis #define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_1_MASK 0x00002000L 6000de2bdb3dSTom St Denis #define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_1__SHIFT 0x0000000d 6001de2bdb3dSTom St Denis #define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_2_MASK 0x00001000L 6002de2bdb3dSTom St Denis #define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_2__SHIFT 0x0000000c 6003de2bdb3dSTom St Denis #define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_3_MASK 0x00000800L 6004de2bdb3dSTom St Denis #define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_3__SHIFT 0x0000000b 6005de2bdb3dSTom St Denis #define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_4_OUTPUT_COMPARE_5_MASK 0x00000400L 6006de2bdb3dSTom St Denis #define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_4_OUTPUT_COMPARE_5__SHIFT 0x0000000a 6007de2bdb3dSTom St Denis #define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_1_MASK 0x00000080L 6008de2bdb3dSTom St Denis #define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_1__SHIFT 0x00000007 6009de2bdb3dSTom St Denis #define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_2_MASK 0x00000040L 6010de2bdb3dSTom St Denis #define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_2__SHIFT 0x00000006 6011de2bdb3dSTom St Denis #define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_3_MASK 0x00000020L 6012de2bdb3dSTom St Denis #define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_3__SHIFT 0x00000005 6013de2bdb3dSTom St Denis #define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_4_MASK 0x00000010L 6014de2bdb3dSTom St Denis #define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_4__SHIFT 0x00000004 6015de2bdb3dSTom St Denis #define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OVERFLOW_MASK 0x00000100L 6016de2bdb3dSTom St Denis #define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OVERFLOW__SHIFT 0x00000008 6017de2bdb3dSTom St Denis #define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_XIRQ_N_PIN_MASK 0x00000002L 6018de2bdb3dSTom St Denis #define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_XIRQ_N_PIN__SHIFT 0x00000001 6019de2bdb3dSTom St Denis #define DMIF_ADDR_CALC__ADDR_CONFIG_PIPE_INTERLEAVE_SIZE_MASK 0x00000070L 6020de2bdb3dSTom St Denis #define DMIF_ADDR_CALC__ADDR_CONFIG_PIPE_INTERLEAVE_SIZE__SHIFT 0x00000004 6021de2bdb3dSTom St Denis #define DMIF_ADDR_CALC__ADDR_CONFIG_ROW_SIZE_MASK 0x30000000L 6022de2bdb3dSTom St Denis #define DMIF_ADDR_CALC__ADDR_CONFIG_ROW_SIZE__SHIFT 0x0000001c 6023de2bdb3dSTom St Denis #define DMIF_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x00000700L 6024de2bdb3dSTom St Denis #define DMIF_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x00000008 6025de2bdb3dSTom St Denis #define DMIF_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000L 6026de2bdb3dSTom St Denis #define DMIF_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x0000001e 6027de2bdb3dSTom St Denis #define DMIF_ADDR_CONFIG__NUM_PIPES_MASK 0x00000007L 6028de2bdb3dSTom St Denis #define DMIF_ADDR_CONFIG__NUM_PIPES__SHIFT 0x00000000 6029de2bdb3dSTom St Denis #define DMIF_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x00003000L 6030de2bdb3dSTom St Denis #define DMIF_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0x0000000c 6031de2bdb3dSTom St Denis #define DMIF_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x00000070L 6032de2bdb3dSTom St Denis #define DMIF_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x00000004 6033de2bdb3dSTom St Denis #define DMIF_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000L 6034de2bdb3dSTom St Denis #define DMIF_ADDR_CONFIG__ROW_SIZE__SHIFT 0x0000001c 6035de2bdb3dSTom St Denis #define DMIF_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x00070000L 6036de2bdb3dSTom St Denis #define DMIF_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x00000010 6037de2bdb3dSTom St Denis #define DMIF_ARBITRATION_CONTROL__DMIF_ARBITRATION_REFERENCE_CLOCK_PERIOD_MASK 0x0000ffffL 6038de2bdb3dSTom St Denis #define DMIF_ARBITRATION_CONTROL__DMIF_ARBITRATION_REFERENCE_CLOCK_PERIOD__SHIFT 0x00000000 6039de2bdb3dSTom St Denis #define DMIF_ARBITRATION_CONTROL__PIPE_SWITCH_EFFICIENCY_WEIGHT_MASK 0xffff0000L 6040de2bdb3dSTom St Denis #define DMIF_ARBITRATION_CONTROL__PIPE_SWITCH_EFFICIENCY_WEIGHT__SHIFT 0x00000010 6041de2bdb3dSTom St Denis #define DMIF_CONTROL__DMIF_BUFF_SIZE_MASK 0x00000003L 6042de2bdb3dSTom St Denis #define DMIF_CONTROL__DMIF_BUFF_SIZE__SHIFT 0x00000000 6043de2bdb3dSTom St Denis #define DMIF_CONTROL__DMIF_CHUNK_BUFF_MARGIN_MASK 0x60000000L 6044de2bdb3dSTom St Denis #define DMIF_CONTROL__DMIF_CHUNK_BUFF_MARGIN__SHIFT 0x0000001d 6045de2bdb3dSTom St Denis #define DMIF_CONTROL__DMIF_DELAY_ARBITRATION_MASK 0x1f000000L 6046de2bdb3dSTom St Denis #define DMIF_CONTROL__DMIF_DELAY_ARBITRATION__SHIFT 0x00000018 6047de2bdb3dSTom St Denis #define DMIF_CONTROL__DMIF_DISABLE_EARLY_RECEIVED_LEVEL_COUNT_MASK 0x00000010L 6048de2bdb3dSTom St Denis #define DMIF_CONTROL__DMIF_DISABLE_EARLY_RECEIVED_LEVEL_COUNT__SHIFT 0x00000004 6049de2bdb3dSTom St Denis #define DMIF_CONTROL__DMIF_FORCE_TOTAL_REQ_BURST_SIZE_MASK 0x0000f000L 6050de2bdb3dSTom St Denis #define DMIF_CONTROL__DMIF_FORCE_TOTAL_REQ_BURST_SIZE__SHIFT 0x0000000c 6051de2bdb3dSTom St Denis #define DMIF_CONTROL__DMIF_GROUP_REQUESTS_IN_CHUNK_MASK 0x00000004L 6052de2bdb3dSTom St Denis #define DMIF_CONTROL__DMIF_GROUP_REQUESTS_IN_CHUNK__SHIFT 0x00000002 6053de2bdb3dSTom St Denis #define DMIF_CONTROL__DMIF_MAX_TOTAL_OUTSTANDING_CHUNK_REQUESTS_MASK 0x003f0000L 6054de2bdb3dSTom St Denis #define DMIF_CONTROL__DMIF_MAX_TOTAL_OUTSTANDING_CHUNK_REQUESTS__SHIFT 0x00000010 6055de2bdb3dSTom St Denis #define DMIF_CONTROL__DMIF_REQ_BURST_SIZE_MASK 0x00000700L 6056de2bdb3dSTom St Denis #define DMIF_CONTROL__DMIF_REQ_BURST_SIZE__SHIFT 0x00000008 6057de2bdb3dSTom St Denis #define DMIF_DEBUG02_CORE0__DB_DATA_MASK 0x0000ffffL 6058de2bdb3dSTom St Denis #define DMIF_DEBUG02_CORE0__DB_DATA__SHIFT 0x00000000 6059de2bdb3dSTom St Denis #define DMIF_DEBUG02_CORE0__MC_RDRET_COUNT_EN_MASK 0x00010000L 6060de2bdb3dSTom St Denis #define DMIF_DEBUG02_CORE0__MC_RDRET_COUNT_EN__SHIFT 0x00000010 6061de2bdb3dSTom St Denis #define DMIF_DEBUG02_CORE0__MC_RDRET_COUNTER_MASK 0x0ffe0000L 6062de2bdb3dSTom St Denis #define DMIF_DEBUG02_CORE0__MC_RDRET_COUNTER__SHIFT 0x00000011 6063de2bdb3dSTom St Denis #define DMIF_DEBUG02_CORE1__DB_DATA_MASK 0x0000ffffL 6064de2bdb3dSTom St Denis #define DMIF_DEBUG02_CORE1__DB_DATA__SHIFT 0x00000000 6065de2bdb3dSTom St Denis #define DMIF_DEBUG02_CORE1__MC_RDRET_COUNT_EN_MASK 0x00010000L 6066de2bdb3dSTom St Denis #define DMIF_DEBUG02_CORE1__MC_RDRET_COUNT_EN__SHIFT 0x00000010 6067de2bdb3dSTom St Denis #define DMIF_DEBUG02_CORE1__MC_RDRET_COUNTER_MASK 0x0ffe0000L 6068de2bdb3dSTom St Denis #define DMIF_DEBUG02_CORE1__MC_RDRET_COUNTER__SHIFT 0x00000011 6069de2bdb3dSTom St Denis #define DMIF_HW_DEBUG__DMIF_HW_DEBUG_MASK 0xffffffffL 6070de2bdb3dSTom St Denis #define DMIF_HW_DEBUG__DMIF_HW_DEBUG__SHIFT 0x00000000 6071de2bdb3dSTom St Denis #define DMIF_STATUS2__DMIF_CHUNK_TRACKER_SCLK_STATUS_MASK 0x00000100L 6072de2bdb3dSTom St Denis #define DMIF_STATUS2__DMIF_CHUNK_TRACKER_SCLK_STATUS__SHIFT 0x00000008 6073de2bdb3dSTom St Denis #define DMIF_STATUS2__DMIF_FBC_TRACKER_SCLK_STATUS_MASK 0x00000200L 6074de2bdb3dSTom St Denis #define DMIF_STATUS2__DMIF_FBC_TRACKER_SCLK_STATUS__SHIFT 0x00000009 6075de2bdb3dSTom St Denis #define DMIF_STATUS2__DMIF_PIPE0_DISPCLK_STATUS_MASK 0x00000001L 6076de2bdb3dSTom St Denis #define DMIF_STATUS2__DMIF_PIPE0_DISPCLK_STATUS__SHIFT 0x00000000 6077de2bdb3dSTom St Denis #define DMIF_STATUS2__DMIF_PIPE1_DISPCLK_STATUS_MASK 0x00000002L 6078de2bdb3dSTom St Denis #define DMIF_STATUS2__DMIF_PIPE1_DISPCLK_STATUS__SHIFT 0x00000001 6079de2bdb3dSTom St Denis #define DMIF_STATUS2__DMIF_PIPE2_DISPCLK_STATUS_MASK 0x00000004L 6080de2bdb3dSTom St Denis #define DMIF_STATUS2__DMIF_PIPE2_DISPCLK_STATUS__SHIFT 0x00000002 6081de2bdb3dSTom St Denis #define DMIF_STATUS2__DMIF_PIPE3_DISPCLK_STATUS_MASK 0x00000008L 6082de2bdb3dSTom St Denis #define DMIF_STATUS2__DMIF_PIPE3_DISPCLK_STATUS__SHIFT 0x00000003 6083de2bdb3dSTom St Denis #define DMIF_STATUS2__DMIF_PIPE4_DISPCLK_STATUS_MASK 0x00000010L 6084de2bdb3dSTom St Denis #define DMIF_STATUS2__DMIF_PIPE4_DISPCLK_STATUS__SHIFT 0x00000004 6085de2bdb3dSTom St Denis #define DMIF_STATUS2__DMIF_PIPE5_DISPCLK_STATUS_MASK 0x00000020L 6086de2bdb3dSTom St Denis #define DMIF_STATUS2__DMIF_PIPE5_DISPCLK_STATUS__SHIFT 0x00000005 6087de2bdb3dSTom St Denis #define DMIF_STATUS__DMIF_CLEAR_MC_SEND_ON_IDLE_MASK 0x00003f00L 6088de2bdb3dSTom St Denis #define DMIF_STATUS__DMIF_CLEAR_MC_SEND_ON_IDLE__SHIFT 0x00000008 6089de2bdb3dSTom St Denis #define DMIF_STATUS__DMIF_MC_LATENCY_COUNTER_ENABLE_MASK 0x00010000L 6090de2bdb3dSTom St Denis #define DMIF_STATUS__DMIF_MC_LATENCY_COUNTER_ENABLE__SHIFT 0x00000010 6091de2bdb3dSTom St Denis #define DMIF_STATUS__DMIF_MC_LATENCY_COUNTER_SOURCE_SELECT_MASK 0x00700000L 6092de2bdb3dSTom St Denis #define DMIF_STATUS__DMIF_MC_LATENCY_COUNTER_SOURCE_SELECT__SHIFT 0x00000014 6093de2bdb3dSTom St Denis #define DMIF_STATUS__DMIF_MC_LATENCY_COUNTER_URGENT_ONLY_MASK 0x00020000L 6094de2bdb3dSTom St Denis #define DMIF_STATUS__DMIF_MC_LATENCY_COUNTER_URGENT_ONLY__SHIFT 0x00000011 6095de2bdb3dSTom St Denis #define DMIF_STATUS__DMIF_MC_SEND_ON_IDLE_MASK 0x0000003fL 6096de2bdb3dSTom St Denis #define DMIF_STATUS__DMIF_MC_SEND_ON_IDLE__SHIFT 0x00000000 6097de2bdb3dSTom St Denis #define DMIF_STATUS__DMIF_PERFORMANCE_COUNTER_SOURCE_SELECT_MASK 0x07000000L 6098de2bdb3dSTom St Denis #define DMIF_STATUS__DMIF_PERFORMANCE_COUNTER_SOURCE_SELECT__SHIFT 0x00000018 6099de2bdb3dSTom St Denis #define DMIF_STATUS__DMIF_UNDERFLOW_MASK 0x10000000L 6100de2bdb3dSTom St Denis #define DMIF_STATUS__DMIF_UNDERFLOW__SHIFT 0x0000001c 6101de2bdb3dSTom St Denis #define DMIF_TEST_DEBUG_DATA__DMIF_TEST_DEBUG_DATA_MASK 0xffffffffL 6102de2bdb3dSTom St Denis #define DMIF_TEST_DEBUG_DATA__DMIF_TEST_DEBUG_DATA__SHIFT 0x00000000 6103de2bdb3dSTom St Denis #define DMIF_TEST_DEBUG_INDEX__DMIF_TEST_DEBUG_INDEX_MASK 0x000000ffL 6104de2bdb3dSTom St Denis #define DMIF_TEST_DEBUG_INDEX__DMIF_TEST_DEBUG_INDEX__SHIFT 0x00000000 6105de2bdb3dSTom St Denis #define DMIF_TEST_DEBUG_INDEX__DMIF_TEST_DEBUG_WRITE_EN_MASK 0x00000100L 6106de2bdb3dSTom St Denis #define DMIF_TEST_DEBUG_INDEX__DMIF_TEST_DEBUG_WRITE_EN__SHIFT 0x00000008 6107de2bdb3dSTom St Denis #define DOUT_DCE_VCE_CONTROL__DC_VCE_AUDIO_STREAM_SELECT_MASK 0x00000070L 6108de2bdb3dSTom St Denis #define DOUT_DCE_VCE_CONTROL__DC_VCE_AUDIO_STREAM_SELECT__SHIFT 0x00000004 6109de2bdb3dSTom St Denis #define DOUT_DCE_VCE_CONTROL__DC_VCE_VIDEO_PIPE_SELECT_MASK 0x00000007L 6110de2bdb3dSTom St Denis #define DOUT_DCE_VCE_CONTROL__DC_VCE_VIDEO_PIPE_SELECT__SHIFT 0x00000000 6111de2bdb3dSTom St Denis #define DOUT_POWER_MANAGEMENT_CNTL__PM_ALL_BUSY_OFF_MASK 0x00000100L 6112de2bdb3dSTom St Denis #define DOUT_POWER_MANAGEMENT_CNTL__PM_ALL_BUSY_OFF__SHIFT 0x00000008 6113de2bdb3dSTom St Denis #define DOUT_POWER_MANAGEMENT_CNTL__PM_ASSERT_RESET_MASK 0x00000001L 6114de2bdb3dSTom St Denis #define DOUT_POWER_MANAGEMENT_CNTL__PM_ASSERT_RESET__SHIFT 0x00000000 6115de2bdb3dSTom St Denis #define DOUT_SCRATCH0__DOUT_SCRATCH0_MASK 0xffffffffL 6116de2bdb3dSTom St Denis #define DOUT_SCRATCH0__DOUT_SCRATCH0__SHIFT 0x00000000 6117de2bdb3dSTom St Denis #define DOUT_SCRATCH1__DOUT_SCRATCH1_MASK 0xffffffffL 6118de2bdb3dSTom St Denis #define DOUT_SCRATCH1__DOUT_SCRATCH1__SHIFT 0x00000000 6119de2bdb3dSTom St Denis #define DOUT_SCRATCH2__DOUT_SCRATCH2_MASK 0xffffffffL 6120de2bdb3dSTom St Denis #define DOUT_SCRATCH2__DOUT_SCRATCH2__SHIFT 0x00000000 6121de2bdb3dSTom St Denis #define DOUT_SCRATCH3__DOUT_SCRATCH3_MASK 0xffffffffL 6122de2bdb3dSTom St Denis #define DOUT_SCRATCH3__DOUT_SCRATCH3__SHIFT 0x00000000 6123de2bdb3dSTom St Denis #define DOUT_SCRATCH4__DOUT_SCRATCH4_MASK 0xffffffffL 6124de2bdb3dSTom St Denis #define DOUT_SCRATCH4__DOUT_SCRATCH4__SHIFT 0x00000000 6125de2bdb3dSTom St Denis #define DOUT_SCRATCH5__DOUT_SCRATCH5_MASK 0xffffffffL 6126de2bdb3dSTom St Denis #define DOUT_SCRATCH5__DOUT_SCRATCH5__SHIFT 0x00000000 6127de2bdb3dSTom St Denis #define DOUT_SCRATCH6__DOUT_SCRATCH6_MASK 0xffffffffL 6128de2bdb3dSTom St Denis #define DOUT_SCRATCH6__DOUT_SCRATCH6__SHIFT 0x00000000 6129de2bdb3dSTom St Denis #define DOUT_SCRATCH7__DOUT_SCRATCH7_MASK 0xffffffffL 6130de2bdb3dSTom St Denis #define DOUT_SCRATCH7__DOUT_SCRATCH7__SHIFT 0x00000000 6131de2bdb3dSTom St Denis #define DOUT_TEST_DEBUG_DATA__DOUT_TEST_DEBUG_DATA_MASK 0xffffffffL 6132de2bdb3dSTom St Denis #define DOUT_TEST_DEBUG_DATA__DOUT_TEST_DEBUG_DATA__SHIFT 0x00000000 6133de2bdb3dSTom St Denis #define DOUT_TEST_DEBUG_INDEX__DOUT_TEST_DEBUG_INDEX_MASK 0x000000ffL 6134de2bdb3dSTom St Denis #define DOUT_TEST_DEBUG_INDEX__DOUT_TEST_DEBUG_INDEX__SHIFT 0x00000000 6135de2bdb3dSTom St Denis #define DOUT_TEST_DEBUG_INDEX__DOUT_TEST_DEBUG_WRITE_EN_MASK 0x00000100L 6136de2bdb3dSTom St Denis #define DOUT_TEST_DEBUG_INDEX__DOUT_TEST_DEBUG_WRITE_EN__SHIFT 0x00000008 6137de2bdb3dSTom St Denis #define DP_AUX1_DEBUG_A__DP_AUX1_DEBUG_A_MASK 0xffffffffL 6138de2bdb3dSTom St Denis #define DP_AUX1_DEBUG_A__DP_AUX1_DEBUG_A__SHIFT 0x00000000 6139de2bdb3dSTom St Denis #define DP_AUX1_DEBUG_B__DP_AUX1_DEBUG_B_MASK 0xffffffffL 6140de2bdb3dSTom St Denis #define DP_AUX1_DEBUG_B__DP_AUX1_DEBUG_B__SHIFT 0x00000000 6141de2bdb3dSTom St Denis #define DP_AUX1_DEBUG_C__DP_AUX1_DEBUG_C_MASK 0xffffffffL 6142de2bdb3dSTom St Denis #define DP_AUX1_DEBUG_C__DP_AUX1_DEBUG_C__SHIFT 0x00000000 6143de2bdb3dSTom St Denis #define DP_AUX1_DEBUG_D__DP_AUX1_DEBUG_D_MASK 0xffffffffL 6144de2bdb3dSTom St Denis #define DP_AUX1_DEBUG_D__DP_AUX1_DEBUG_D__SHIFT 0x00000000 6145de2bdb3dSTom St Denis #define DP_AUX1_DEBUG_E__DP_AUX1_DEBUG_E_MASK 0xffffffffL 6146de2bdb3dSTom St Denis #define DP_AUX1_DEBUG_E__DP_AUX1_DEBUG_E__SHIFT 0x00000000 6147de2bdb3dSTom St Denis #define DP_AUX1_DEBUG_F__DP_AUX1_DEBUG_F_MASK 0xffffffffL 6148de2bdb3dSTom St Denis #define DP_AUX1_DEBUG_F__DP_AUX1_DEBUG_F__SHIFT 0x00000000 6149de2bdb3dSTom St Denis #define DP_AUX1_DEBUG_G__DP_AUX1_DEBUG_G_MASK 0xffffffffL 6150de2bdb3dSTom St Denis #define DP_AUX1_DEBUG_G__DP_AUX1_DEBUG_G__SHIFT 0x00000000 6151de2bdb3dSTom St Denis #define DP_AUX1_DEBUG_H__DP_AUX1_DEBUG_H_MASK 0xffffffffL 6152de2bdb3dSTom St Denis #define DP_AUX1_DEBUG_H__DP_AUX1_DEBUG_H__SHIFT 0x00000000 6153de2bdb3dSTom St Denis #define DP_AUX1_DEBUG_I__DP_AUX1_DEBUG_I_MASK 0xffffffffL 6154de2bdb3dSTom St Denis #define DP_AUX1_DEBUG_I__DP_AUX1_DEBUG_I__SHIFT 0x00000000 6155de2bdb3dSTom St Denis #define DP_AUX2_DEBUG_A__DP_AUX2_DEBUG_A_MASK 0xffffffffL 6156de2bdb3dSTom St Denis #define DP_AUX2_DEBUG_A__DP_AUX2_DEBUG_A__SHIFT 0x00000000 6157de2bdb3dSTom St Denis #define DP_AUX2_DEBUG_B__DP_AUX2_DEBUG_B_MASK 0xffffffffL 6158de2bdb3dSTom St Denis #define DP_AUX2_DEBUG_B__DP_AUX2_DEBUG_B__SHIFT 0x00000000 6159de2bdb3dSTom St Denis #define DP_AUX2_DEBUG_C__DP_AUX2_DEBUG_C_MASK 0xffffffffL 6160de2bdb3dSTom St Denis #define DP_AUX2_DEBUG_C__DP_AUX2_DEBUG_C__SHIFT 0x00000000 6161de2bdb3dSTom St Denis #define DP_AUX2_DEBUG_D__DP_AUX2_DEBUG_D_MASK 0xffffffffL 6162de2bdb3dSTom St Denis #define DP_AUX2_DEBUG_D__DP_AUX2_DEBUG_D__SHIFT 0x00000000 6163de2bdb3dSTom St Denis #define DP_AUX2_DEBUG_E__DP_AUX2_DEBUG_E_MASK 0xffffffffL 6164de2bdb3dSTom St Denis #define DP_AUX2_DEBUG_E__DP_AUX2_DEBUG_E__SHIFT 0x00000000 6165de2bdb3dSTom St Denis #define DP_AUX2_DEBUG_F__DP_AUX2_DEBUG_F_MASK 0xffffffffL 6166de2bdb3dSTom St Denis #define DP_AUX2_DEBUG_F__DP_AUX2_DEBUG_F__SHIFT 0x00000000 6167de2bdb3dSTom St Denis #define DP_AUX2_DEBUG_G__DP_AUX2_DEBUG_G_MASK 0xffffffffL 6168de2bdb3dSTom St Denis #define DP_AUX2_DEBUG_G__DP_AUX2_DEBUG_G__SHIFT 0x00000000 6169de2bdb3dSTom St Denis #define DP_AUX2_DEBUG_H__DP_AUX2_DEBUG_H_MASK 0xffffffffL 6170de2bdb3dSTom St Denis #define DP_AUX2_DEBUG_H__DP_AUX2_DEBUG_H__SHIFT 0x00000000 6171de2bdb3dSTom St Denis #define DP_AUX2_DEBUG_I__DP_AUX2_DEBUG_I_MASK 0xffffffffL 6172de2bdb3dSTom St Denis #define DP_AUX2_DEBUG_I__DP_AUX2_DEBUG_I__SHIFT 0x00000000 6173de2bdb3dSTom St Denis #define DP_AUX3_DEBUG_A__DP_AUX3_DEBUG_A_MASK 0xffffffffL 6174de2bdb3dSTom St Denis #define DP_AUX3_DEBUG_A__DP_AUX3_DEBUG_A__SHIFT 0x00000000 6175de2bdb3dSTom St Denis #define DP_AUX3_DEBUG_B__DP_AUX3_DEBUG_B_MASK 0xffffffffL 6176de2bdb3dSTom St Denis #define DP_AUX3_DEBUG_B__DP_AUX3_DEBUG_B__SHIFT 0x00000000 6177de2bdb3dSTom St Denis #define DP_AUX3_DEBUG_C__DP_AUX3_DEBUG_C_MASK 0xffffffffL 6178de2bdb3dSTom St Denis #define DP_AUX3_DEBUG_C__DP_AUX3_DEBUG_C__SHIFT 0x00000000 6179de2bdb3dSTom St Denis #define DP_AUX3_DEBUG_D__DP_AUX3_DEBUG_D_MASK 0xffffffffL 6180de2bdb3dSTom St Denis #define DP_AUX3_DEBUG_D__DP_AUX3_DEBUG_D__SHIFT 0x00000000 6181de2bdb3dSTom St Denis #define DP_AUX3_DEBUG_E__DP_AUX3_DEBUG_E_MASK 0xffffffffL 6182de2bdb3dSTom St Denis #define DP_AUX3_DEBUG_E__DP_AUX3_DEBUG_E__SHIFT 0x00000000 6183de2bdb3dSTom St Denis #define DP_AUX3_DEBUG_F__DP_AUX3_DEBUG_F_MASK 0xffffffffL 6184de2bdb3dSTom St Denis #define DP_AUX3_DEBUG_F__DP_AUX3_DEBUG_F__SHIFT 0x00000000 6185de2bdb3dSTom St Denis #define DP_AUX3_DEBUG_G__DP_AUX3_DEBUG_G_MASK 0xffffffffL 6186de2bdb3dSTom St Denis #define DP_AUX3_DEBUG_G__DP_AUX3_DEBUG_G__SHIFT 0x00000000 6187de2bdb3dSTom St Denis #define DP_AUX3_DEBUG_H__DP_AUX3_DEBUG_H_MASK 0xffffffffL 6188de2bdb3dSTom St Denis #define DP_AUX3_DEBUG_H__DP_AUX3_DEBUG_H__SHIFT 0x00000000 6189de2bdb3dSTom St Denis #define DP_AUX3_DEBUG_I__DP_AUX3_DEBUG_I_MASK 0xffffffffL 6190de2bdb3dSTom St Denis #define DP_AUX3_DEBUG_I__DP_AUX3_DEBUG_I__SHIFT 0x00000000 6191de2bdb3dSTom St Denis #define DP_AUX4_DEBUG_A__DP_AUX4_DEBUG_A_MASK 0xffffffffL 6192de2bdb3dSTom St Denis #define DP_AUX4_DEBUG_A__DP_AUX4_DEBUG_A__SHIFT 0x00000000 6193de2bdb3dSTom St Denis #define DP_AUX4_DEBUG_B__DP_AUX4_DEBUG_B_MASK 0xffffffffL 6194de2bdb3dSTom St Denis #define DP_AUX4_DEBUG_B__DP_AUX4_DEBUG_B__SHIFT 0x00000000 6195de2bdb3dSTom St Denis #define DP_AUX4_DEBUG_C__DP_AUX4_DEBUG_C_MASK 0xffffffffL 6196de2bdb3dSTom St Denis #define DP_AUX4_DEBUG_C__DP_AUX4_DEBUG_C__SHIFT 0x00000000 6197de2bdb3dSTom St Denis #define DP_AUX4_DEBUG_D__DP_AUX4_DEBUG_D_MASK 0xffffffffL 6198de2bdb3dSTom St Denis #define DP_AUX4_DEBUG_D__DP_AUX4_DEBUG_D__SHIFT 0x00000000 6199de2bdb3dSTom St Denis #define DP_AUX4_DEBUG_E__DP_AUX4_DEBUG_E_MASK 0xffffffffL 6200de2bdb3dSTom St Denis #define DP_AUX4_DEBUG_E__DP_AUX4_DEBUG_E__SHIFT 0x00000000 6201de2bdb3dSTom St Denis #define DP_AUX4_DEBUG_F__DP_AUX4_DEBUG_F_MASK 0xffffffffL 6202de2bdb3dSTom St Denis #define DP_AUX4_DEBUG_F__DP_AUX4_DEBUG_F__SHIFT 0x00000000 6203de2bdb3dSTom St Denis #define DP_AUX4_DEBUG_G__DP_AUX4_DEBUG_G_MASK 0xffffffffL 6204de2bdb3dSTom St Denis #define DP_AUX4_DEBUG_G__DP_AUX4_DEBUG_G__SHIFT 0x00000000 6205de2bdb3dSTom St Denis #define DP_AUX4_DEBUG_H__DP_AUX4_DEBUG_H_MASK 0xffffffffL 6206de2bdb3dSTom St Denis #define DP_AUX4_DEBUG_H__DP_AUX4_DEBUG_H__SHIFT 0x00000000 6207de2bdb3dSTom St Denis #define DP_AUX4_DEBUG_I__DP_AUX4_DEBUG_I_MASK 0xffffffffL 6208de2bdb3dSTom St Denis #define DP_AUX4_DEBUG_I__DP_AUX4_DEBUG_I__SHIFT 0x00000000 6209de2bdb3dSTom St Denis #define DP_AUX5_DEBUG_A__DP_AUX5_DEBUG_A_MASK 0xffffffffL 6210de2bdb3dSTom St Denis #define DP_AUX5_DEBUG_A__DP_AUX5_DEBUG_A__SHIFT 0x00000000 6211de2bdb3dSTom St Denis #define DP_AUX5_DEBUG_B__DP_AUX5_DEBUG_B_MASK 0xffffffffL 6212de2bdb3dSTom St Denis #define DP_AUX5_DEBUG_B__DP_AUX5_DEBUG_B__SHIFT 0x00000000 6213de2bdb3dSTom St Denis #define DP_AUX5_DEBUG_C__DP_AUX5_DEBUG_C_MASK 0xffffffffL 6214de2bdb3dSTom St Denis #define DP_AUX5_DEBUG_C__DP_AUX5_DEBUG_C__SHIFT 0x00000000 6215de2bdb3dSTom St Denis #define DP_AUX5_DEBUG_D__DP_AUX5_DEBUG_D_MASK 0xffffffffL 6216de2bdb3dSTom St Denis #define DP_AUX5_DEBUG_D__DP_AUX5_DEBUG_D__SHIFT 0x00000000 6217de2bdb3dSTom St Denis #define DP_AUX5_DEBUG_E__DP_AUX5_DEBUG_E_MASK 0xffffffffL 6218de2bdb3dSTom St Denis #define DP_AUX5_DEBUG_E__DP_AUX5_DEBUG_E__SHIFT 0x00000000 6219de2bdb3dSTom St Denis #define DP_AUX5_DEBUG_F__DP_AUX5_DEBUG_F_MASK 0xffffffffL 6220de2bdb3dSTom St Denis #define DP_AUX5_DEBUG_F__DP_AUX5_DEBUG_F__SHIFT 0x00000000 6221de2bdb3dSTom St Denis #define DP_AUX5_DEBUG_G__DP_AUX5_DEBUG_G_MASK 0xffffffffL 6222de2bdb3dSTom St Denis #define DP_AUX5_DEBUG_G__DP_AUX5_DEBUG_G__SHIFT 0x00000000 6223de2bdb3dSTom St Denis #define DP_AUX5_DEBUG_H__DP_AUX5_DEBUG_H_MASK 0xffffffffL 6224de2bdb3dSTom St Denis #define DP_AUX5_DEBUG_H__DP_AUX5_DEBUG_H__SHIFT 0x00000000 6225de2bdb3dSTom St Denis #define DP_AUX5_DEBUG_I__DP_AUX5_DEBUG_I_MASK 0xffffffffL 6226de2bdb3dSTom St Denis #define DP_AUX5_DEBUG_I__DP_AUX5_DEBUG_I__SHIFT 0x00000000 6227de2bdb3dSTom St Denis #define DP_AUX6_DEBUG_A__DP_AUX6_DEBUG_A_MASK 0xffffffffL 6228de2bdb3dSTom St Denis #define DP_AUX6_DEBUG_A__DP_AUX6_DEBUG_A__SHIFT 0x00000000 6229de2bdb3dSTom St Denis #define DP_AUX6_DEBUG_B__DP_AUX6_DEBUG_B_MASK 0xffffffffL 6230de2bdb3dSTom St Denis #define DP_AUX6_DEBUG_B__DP_AUX6_DEBUG_B__SHIFT 0x00000000 6231de2bdb3dSTom St Denis #define DP_AUX6_DEBUG_C__DP_AUX6_DEBUG_C_MASK 0xffffffffL 6232de2bdb3dSTom St Denis #define DP_AUX6_DEBUG_C__DP_AUX6_DEBUG_C__SHIFT 0x00000000 6233de2bdb3dSTom St Denis #define DP_AUX6_DEBUG_D__DP_AUX6_DEBUG_D_MASK 0xffffffffL 6234de2bdb3dSTom St Denis #define DP_AUX6_DEBUG_D__DP_AUX6_DEBUG_D__SHIFT 0x00000000 6235de2bdb3dSTom St Denis #define DP_AUX6_DEBUG_E__DP_AUX6_DEBUG_E_MASK 0xffffffffL 6236de2bdb3dSTom St Denis #define DP_AUX6_DEBUG_E__DP_AUX6_DEBUG_E__SHIFT 0x00000000 6237de2bdb3dSTom St Denis #define DP_AUX6_DEBUG_F__DP_AUX6_DEBUG_F_MASK 0xffffffffL 6238de2bdb3dSTom St Denis #define DP_AUX6_DEBUG_F__DP_AUX6_DEBUG_F__SHIFT 0x00000000 6239de2bdb3dSTom St Denis #define DP_AUX6_DEBUG_G__DP_AUX6_DEBUG_G_MASK 0xffffffffL 6240de2bdb3dSTom St Denis #define DP_AUX6_DEBUG_G__DP_AUX6_DEBUG_G__SHIFT 0x00000000 6241de2bdb3dSTom St Denis #define DP_AUX6_DEBUG_H__DP_AUX6_DEBUG_H_MASK 0xffffffffL 6242de2bdb3dSTom St Denis #define DP_AUX6_DEBUG_H__DP_AUX6_DEBUG_H__SHIFT 0x00000000 6243de2bdb3dSTom St Denis #define DP_AUX6_DEBUG_I__DP_AUX6_DEBUG_I_MASK 0xffffffffL 6244de2bdb3dSTom St Denis #define DP_AUX6_DEBUG_I__DP_AUX6_DEBUG_I__SHIFT 0x00000000 6245de2bdb3dSTom St Denis #define DP_CONFIG__DP_UDI_LANES_MASK 0x00000003L 6246de2bdb3dSTom St Denis #define DP_CONFIG__DP_UDI_LANES__SHIFT 0x00000000 6247de2bdb3dSTom St Denis #define DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP_MASK 0x01000000L 6248de2bdb3dSTom St Denis #define DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP__SHIFT 0x00000018 6249de2bdb3dSTom St Denis #define DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP_MASK 0x00010000L 6250de2bdb3dSTom St Denis #define DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP__SHIFT 0x00000010 6251de2bdb3dSTom St Denis #define DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET_MASK 0x00000100L 6252de2bdb3dSTom St Denis #define DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET__SHIFT 0x00000008 6253de2bdb3dSTom St Denis #define DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0_MASK 0x00000001L 6254de2bdb3dSTom St Denis #define DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0__SHIFT 0x00000000 6255de2bdb3dSTom St Denis #define DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1_MASK 0x00000002L 6256de2bdb3dSTom St Denis #define DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1__SHIFT 0x00000001 6257de2bdb3dSTom St Denis #define DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2_MASK 0x00000004L 6258de2bdb3dSTom St Denis #define DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2__SHIFT 0x00000002 6259de2bdb3dSTom St Denis #define DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3_MASK 0x00000008L 6260de2bdb3dSTom St Denis #define DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3__SHIFT 0x00000003 6261de2bdb3dSTom St Denis #define DP_DPHY_CNTL__DPHY_BYPASS_MASK 0x00010000L 6262de2bdb3dSTom St Denis #define DP_DPHY_CNTL__DPHY_BYPASS__SHIFT 0x00000010 6263de2bdb3dSTom St Denis #define DP_DPHY_CNTL__DPHY_SKEW_BYPASS_MASK 0x01000000L 6264de2bdb3dSTom St Denis #define DP_DPHY_CNTL__DPHY_SKEW_BYPASS__SHIFT 0x00000018 6265de2bdb3dSTom St Denis #define DP_DPHY_CRC_CNTL__DPHY_CRC_FIELD_MASK 0x00000001L 6266de2bdb3dSTom St Denis #define DP_DPHY_CRC_CNTL__DPHY_CRC_FIELD__SHIFT 0x00000000 6267de2bdb3dSTom St Denis #define DP_DPHY_CRC_CNTL__DPHY_CRC_MASK_MASK 0x00ff0000L 6268de2bdb3dSTom St Denis #define DP_DPHY_CRC_CNTL__DPHY_CRC_MASK__SHIFT 0x00000010 6269de2bdb3dSTom St Denis #define DP_DPHY_CRC_CNTL__DPHY_CRC_SEL_MASK 0x00000030L 6270de2bdb3dSTom St Denis #define DP_DPHY_CRC_CNTL__DPHY_CRC_SEL__SHIFT 0x00000004 6271de2bdb3dSTom St Denis #define DP_DPHY_CRC_EN__DPHY_CRC_CONT_EN_MASK 0x00000010L 6272de2bdb3dSTom St Denis #define DP_DPHY_CRC_EN__DPHY_CRC_CONT_EN__SHIFT 0x00000004 6273de2bdb3dSTom St Denis #define DP_DPHY_CRC_EN__DPHY_CRC_EN_MASK 0x00000001L 6274de2bdb3dSTom St Denis #define DP_DPHY_CRC_EN__DPHY_CRC_EN__SHIFT 0x00000000 6275de2bdb3dSTom St Denis #define DP_DPHY_CRC_EN__DPHY_CRC_RESULT_VALID_MASK 0x00000100L 6276de2bdb3dSTom St Denis #define DP_DPHY_CRC_EN__DPHY_CRC_RESULT_VALID__SHIFT 0x00000008 6277de2bdb3dSTom St Denis #define DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_FIRST_SLOT_MASK 0x0000003fL 6278de2bdb3dSTom St Denis #define DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_FIRST_SLOT__SHIFT 0x00000000 6279de2bdb3dSTom St Denis #define DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_LAST_SLOT_MASK 0x00003f00L 6280de2bdb3dSTom St Denis #define DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_LAST_SLOT__SHIFT 0x00000008 6281de2bdb3dSTom St Denis #define DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK_MASK 0x00010000L 6282de2bdb3dSTom St Denis #define DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK__SHIFT 0x00000010 6283de2bdb3dSTom St Denis #define DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_MASK 0x00000100L 6284de2bdb3dSTom St Denis #define DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR__SHIFT 0x00000008 6285de2bdb3dSTom St Denis #define DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_LOCK_MASK 0x00000001L 6286de2bdb3dSTom St Denis #define DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_LOCK__SHIFT 0x00000000 6287de2bdb3dSTom St Denis #define DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT1_MASK 0x0000ff00L 6288de2bdb3dSTom St Denis #define DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT1__SHIFT 0x00000008 6289de2bdb3dSTom St Denis #define DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT2_MASK 0x00ff0000L 6290de2bdb3dSTom St Denis #define DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT2__SHIFT 0x00000010 6291de2bdb3dSTom St Denis #define DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT3_MASK 0xff000000L 6292de2bdb3dSTom St Denis #define DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT3__SHIFT 0x00000018 6293de2bdb3dSTom St Denis #define DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT_MASK 0x000000ffL 6294de2bdb3dSTom St Denis #define DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT__SHIFT 0x00000000 6295de2bdb3dSTom St Denis #define DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME_MASK 0x000fff00L 6296de2bdb3dSTom St Denis #define DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME__SHIFT 0x00000008 6297de2bdb3dSTom St Denis #define DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME_MASK 0xfff00000L 6298de2bdb3dSTom St Denis #define DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME__SHIFT 0x00000014 6299de2bdb3dSTom St Denis #define DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN_MASK 0x00000004L 6300de2bdb3dSTom St Denis #define DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN__SHIFT 0x00000002 6301de2bdb3dSTom St Denis #define DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE_MASK 0x00000001L 6302de2bdb3dSTom St Denis #define DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE__SHIFT 0x00000000 6303de2bdb3dSTom St Denis #define DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START_MASK 0x00000002L 6304de2bdb3dSTom St Denis #define DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START__SHIFT 0x00000001 6305de2bdb3dSTom St Denis #define DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK_MASK 0x00001000L 6306de2bdb3dSTom St Denis #define DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK__SHIFT 0x0000000c 6307de2bdb3dSTom St Denis #define DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK_MASK 0x00000100L 6308de2bdb3dSTom St Denis #define DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK__SHIFT 0x00000008 6309de2bdb3dSTom St Denis #define DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED_MASK 0x00000010L 6310de2bdb3dSTom St Denis #define DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED__SHIFT 0x00000004 6311de2bdb3dSTom St Denis #define DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE_MASK 0x00000007L 6312de2bdb3dSTom St Denis #define DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE__SHIFT 0x00000000 6313de2bdb3dSTom St Denis #define DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN_MASK 0x00000001L 6314de2bdb3dSTom St Denis #define DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN__SHIFT 0x00000000 6315de2bdb3dSTom St Denis #define DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED_MASK 0x7fffff00L 6316de2bdb3dSTom St Denis #define DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED__SHIFT 0x00000008 6317de2bdb3dSTom St Denis #define DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL_MASK 0x00000030L 6318de2bdb3dSTom St Denis #define DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL__SHIFT 0x00000004 6319de2bdb3dSTom St Denis #define DP_DPHY_SYM0__DPHY_SYM1_MASK 0x000003ffL 6320de2bdb3dSTom St Denis #define DP_DPHY_SYM0__DPHY_SYM1__SHIFT 0x00000000 6321de2bdb3dSTom St Denis #define DP_DPHY_SYM0__DPHY_SYM2_MASK 0x000ffc00L 6322de2bdb3dSTom St Denis #define DP_DPHY_SYM0__DPHY_SYM2__SHIFT 0x0000000a 6323de2bdb3dSTom St Denis #define DP_DPHY_SYM0__DPHY_SYM3_MASK 0x3ff00000L 6324de2bdb3dSTom St Denis #define DP_DPHY_SYM0__DPHY_SYM3__SHIFT 0x00000014 6325de2bdb3dSTom St Denis #define DP_DPHY_SYM1__DPHY_SYM4_MASK 0x000003ffL 6326de2bdb3dSTom St Denis #define DP_DPHY_SYM1__DPHY_SYM4__SHIFT 0x00000000 6327de2bdb3dSTom St Denis #define DP_DPHY_SYM1__DPHY_SYM5_MASK 0x000ffc00L 6328de2bdb3dSTom St Denis #define DP_DPHY_SYM1__DPHY_SYM5__SHIFT 0x0000000a 6329de2bdb3dSTom St Denis #define DP_DPHY_SYM1__DPHY_SYM6_MASK 0x3ff00000L 6330de2bdb3dSTom St Denis #define DP_DPHY_SYM1__DPHY_SYM6__SHIFT 0x00000014 6331de2bdb3dSTom St Denis #define DP_DPHY_SYM2__DPHY_SYM7_MASK 0x000003ffL 6332de2bdb3dSTom St Denis #define DP_DPHY_SYM2__DPHY_SYM7__SHIFT 0x00000000 6333de2bdb3dSTom St Denis #define DP_DPHY_SYM2__DPHY_SYM8_MASK 0x000ffc00L 6334de2bdb3dSTom St Denis #define DP_DPHY_SYM2__DPHY_SYM8__SHIFT 0x0000000a 6335de2bdb3dSTom St Denis #define DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL_MASK 0x00000003L 6336de2bdb3dSTom St Denis #define DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL__SHIFT 0x00000000 6337de2bdb3dSTom St Denis #define DP_DTO0_MODULO__DP_DTO0_MODULO_MASK 0xffffffffL 6338de2bdb3dSTom St Denis #define DP_DTO0_MODULO__DP_DTO0_MODULO__SHIFT 0x00000000 6339de2bdb3dSTom St Denis #define DP_DTO0_PHASE__DP_DTO0_PHASE_MASK 0xffffffffL 6340de2bdb3dSTom St Denis #define DP_DTO0_PHASE__DP_DTO0_PHASE__SHIFT 0x00000000 6341de2bdb3dSTom St Denis #define DP_DTO1_MODULO__DP_DTO1_MODULO_MASK 0xffffffffL 6342de2bdb3dSTom St Denis #define DP_DTO1_MODULO__DP_DTO1_MODULO__SHIFT 0x00000000 6343de2bdb3dSTom St Denis #define DP_DTO1_PHASE__DP_DTO1_PHASE_MASK 0xffffffffL 6344de2bdb3dSTom St Denis #define DP_DTO1_PHASE__DP_DTO1_PHASE__SHIFT 0x00000000 6345de2bdb3dSTom St Denis #define DP_DTO2_MODULO__DP_DTO2_MODULO_MASK 0xffffffffL 6346de2bdb3dSTom St Denis #define DP_DTO2_MODULO__DP_DTO2_MODULO__SHIFT 0x00000000 6347de2bdb3dSTom St Denis #define DP_DTO2_PHASE__DP_DTO2_PHASE_MASK 0xffffffffL 6348de2bdb3dSTom St Denis #define DP_DTO2_PHASE__DP_DTO2_PHASE__SHIFT 0x00000000 6349de2bdb3dSTom St Denis #define DP_DTO3_MODULO__DP_DTO3_MODULO_MASK 0xffffffffL 6350de2bdb3dSTom St Denis #define DP_DTO3_MODULO__DP_DTO3_MODULO__SHIFT 0x00000000 6351de2bdb3dSTom St Denis #define DP_DTO3_PHASE__DP_DTO3_PHASE_MASK 0xffffffffL 6352de2bdb3dSTom St Denis #define DP_DTO3_PHASE__DP_DTO3_PHASE__SHIFT 0x00000000 6353de2bdb3dSTom St Denis #define DP_DTO4_MODULO__DP_DTO4_MODULO_MASK 0xffffffffL 6354de2bdb3dSTom St Denis #define DP_DTO4_MODULO__DP_DTO4_MODULO__SHIFT 0x00000000 6355de2bdb3dSTom St Denis #define DP_DTO4_PHASE__DP_DTO4_PHASE_MASK 0xffffffffL 6356de2bdb3dSTom St Denis #define DP_DTO4_PHASE__DP_DTO4_PHASE__SHIFT 0x00000000 6357de2bdb3dSTom St Denis #define DP_DTO5_MODULO__DP_DTO5_MODULO_MASK 0xffffffffL 6358de2bdb3dSTom St Denis #define DP_DTO5_MODULO__DP_DTO5_MODULO__SHIFT 0x00000000 6359de2bdb3dSTom St Denis #define DP_DTO5_PHASE__DP_DTO5_PHASE_MASK 0xffffffffL 6360de2bdb3dSTom St Denis #define DP_DTO5_PHASE__DP_DTO5_PHASE__SHIFT 0x00000000 6361de2bdb3dSTom St Denis #define DPG_PIPE_ARBITRATION_CONTROL1__BASE_WEIGHT_MASK 0xffff0000L 6362de2bdb3dSTom St Denis #define DPG_PIPE_ARBITRATION_CONTROL1__BASE_WEIGHT__SHIFT 0x00000010 6363de2bdb3dSTom St Denis #define DPG_PIPE_ARBITRATION_CONTROL1__PIXEL_DURATION_MASK 0x0000ffffL 6364de2bdb3dSTom St Denis #define DPG_PIPE_ARBITRATION_CONTROL1__PIXEL_DURATION__SHIFT 0x00000000 6365de2bdb3dSTom St Denis #define DPG_PIPE_ARBITRATION_CONTROL2__TIME_WEIGHT_MASK 0x0000ffffL 6366de2bdb3dSTom St Denis #define DPG_PIPE_ARBITRATION_CONTROL2__TIME_WEIGHT__SHIFT 0x00000000 6367de2bdb3dSTom St Denis #define DPG_PIPE_ARBITRATION_CONTROL2__URGENCY_WEIGHT_MASK 0xffff0000L 6368de2bdb3dSTom St Denis #define DPG_PIPE_ARBITRATION_CONTROL2__URGENCY_WEIGHT__SHIFT 0x00000010 63696863660dSAlex Deucher #define DPG_PIPE_ARBITRATION_CONTROL3__URGENCY_WATERMARK_MASK_MASK 0x00030000L 63706863660dSAlex Deucher #define DPG_PIPE_ARBITRATION_CONTROL3__URGENCY_WATERMARK_MASK__SHIFT 0x00000010 6371de2bdb3dSTom St Denis #define DPG_PIPE_DPM_CONTROL__DPM_ENABLE_MASK 0x00000001L 6372de2bdb3dSTom St Denis #define DPG_PIPE_DPM_CONTROL__DPM_ENABLE__SHIFT 0x00000000 6373de2bdb3dSTom St Denis #define DPG_PIPE_DPM_CONTROL__MCLK_CHANGE_ENABLE_MASK 0x00000010L 6374de2bdb3dSTom St Denis #define DPG_PIPE_DPM_CONTROL__MCLK_CHANGE_ENABLE__SHIFT 0x00000004 6375de2bdb3dSTom St Denis #define DPG_PIPE_DPM_CONTROL__MCLK_CHANGE_FORCE_ON_MASK 0x00000100L 6376de2bdb3dSTom St Denis #define DPG_PIPE_DPM_CONTROL__MCLK_CHANGE_FORCE_ON__SHIFT 0x00000008 6377de2bdb3dSTom St Denis #define DPG_PIPE_DPM_CONTROL__MCLK_CHANGE_WATERMARK_MASK 0xffff0000L 6378de2bdb3dSTom St Denis #define DPG_PIPE_DPM_CONTROL__MCLK_CHANGE_WATERMARK_MASK_MASK 0x00003000L 6379de2bdb3dSTom St Denis #define DPG_PIPE_DPM_CONTROL__MCLK_CHANGE_WATERMARK_MASK__SHIFT 0x0000000c 6380de2bdb3dSTom St Denis #define DPG_PIPE_DPM_CONTROL__MCLK_CHANGE_WATERMARK__SHIFT 0x00000010 6381de2bdb3dSTom St Denis #define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_ALLOW_FOR_URGENT_MASK 0x00000400L 6382de2bdb3dSTom St Denis #define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_ALLOW_FOR_URGENT__SHIFT 0x0000000a 6383de2bdb3dSTom St Denis #define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_ENABLE_MASK 0x00000001L 6384de2bdb3dSTom St Denis #define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_ENABLE__SHIFT 0x00000000 6385de2bdb3dSTom St Denis #define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_FORCE_ON_MASK 0x00000200L 6386de2bdb3dSTom St Denis #define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_FORCE_ON__SHIFT 0x00000009 6387de2bdb3dSTom St Denis #define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_NOT_SELF_REFRESH_DURING_REQUEST_MASK 0x00000100L 6388de2bdb3dSTom St Denis #define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_NOT_SELF_REFRESH_DURING_REQUEST__SHIFT 0x00000008 6389de2bdb3dSTom St Denis #define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_URGENT_DURING_REQUEST_MASK 0x00000010L 6390de2bdb3dSTom St Denis #define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_URGENT_DURING_REQUEST__SHIFT 0x00000004 63916863660dSAlex Deucher #define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_WATERMARK_MASK_MASK 0x00003000L 63926863660dSAlex Deucher #define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_WATERMARK_MASK__SHIFT 0x0000000c 6393de2bdb3dSTom St Denis #define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_WATERMARK_MASK 0xffff0000L 6394de2bdb3dSTom St Denis #define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_WATERMARK__SHIFT 0x00000010 6395de2bdb3dSTom St Denis #define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_ENABLE_NONLPTCH_MASK 0x00000001L 6396de2bdb3dSTom St Denis #define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_ENABLE_NONLPTCH__SHIFT 0x00000000 6397de2bdb3dSTom St Denis #define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_CURSOR_NONLPTCH_MASK 0x00000010L 6398de2bdb3dSTom St Denis #define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_CURSOR_NONLPTCH__SHIFT 0x00000004 6399de2bdb3dSTom St Denis #define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_FBC_NONLPTCH_MASK 0x00000080L 6400de2bdb3dSTom St Denis #define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_FBC_NONLPTCH__SHIFT 0x00000007 6401de2bdb3dSTom St Denis #define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_ICON_NONLPTCH_MASK 0x00000020L 6402de2bdb3dSTom St Denis #define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_ICON_NONLPTCH__SHIFT 0x00000005 6403de2bdb3dSTom St Denis #define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_VGA_NONLPTCH_MASK 0x00000040L 6404de2bdb3dSTom St Denis #define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_VGA_NONLPTCH__SHIFT 0x00000006 6405de2bdb3dSTom St Denis #define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_SELF_REFRESH_FORCE_ON_NONLPTCH_MASK 0x00000800L 6406de2bdb3dSTom St Denis #define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_SELF_REFRESH_FORCE_ON_NONLPTCH__SHIFT 0x0000000b 6407de2bdb3dSTom St Denis #define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_URGENT_IN_NOT_SELF_REFRESH_NONLPTCH_MASK 0x00000400L 6408de2bdb3dSTom St Denis #define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_URGENT_IN_NOT_SELF_REFRESH_NONLPTCH__SHIFT 0x0000000a 6409de2bdb3dSTom St Denis #define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_WM_HIGH_EXCLUDES_VBLANK_NONLPTCH_MASK 0x00000200L 6410de2bdb3dSTom St Denis #define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_WM_HIGH_EXCLUDES_VBLANK_NONLPTCH__SHIFT 0x00000009 6411de2bdb3dSTom St Denis #define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_WM_HIGH_FORCE_ON_NONLPTCH_MASK 0x00000100L 6412de2bdb3dSTom St Denis #define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_WM_HIGH_FORCE_ON_NONLPTCH__SHIFT 0x00000008 6413de2bdb3dSTom St Denis #define DPG_PIPE_STUTTER_CONTROL__STUTTER_ENABLE_MASK 0x00000001L 6414de2bdb3dSTom St Denis #define DPG_PIPE_STUTTER_CONTROL__STUTTER_ENABLE__SHIFT 0x00000000 64156863660dSAlex Deucher #define DPG_PIPE_STUTTER_CONTROL__STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK_MASK 0x00003000L 64166863660dSAlex Deucher #define DPG_PIPE_STUTTER_CONTROL__STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK__SHIFT 0x0000000c 6417de2bdb3dSTom St Denis #define DPG_PIPE_STUTTER_CONTROL__STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK 0xffff0000L 6418de2bdb3dSTom St Denis #define DPG_PIPE_STUTTER_CONTROL__STUTTER_EXIT_SELF_REFRESH_WATERMARK__SHIFT 0x00000010 6419de2bdb3dSTom St Denis #define DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_CURSOR_MASK 0x00000010L 6420de2bdb3dSTom St Denis #define DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_CURSOR__SHIFT 0x00000004 6421de2bdb3dSTom St Denis #define DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_FBC_MASK 0x00000080L 6422de2bdb3dSTom St Denis #define DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_FBC__SHIFT 0x00000007 6423de2bdb3dSTom St Denis #define DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_ICON_MASK 0x00000020L 6424de2bdb3dSTom St Denis #define DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_ICON__SHIFT 0x00000005 6425de2bdb3dSTom St Denis #define DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_VGA_MASK 0x00000040L 6426de2bdb3dSTom St Denis #define DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_VGA__SHIFT 0x00000006 6427de2bdb3dSTom St Denis #define DPG_PIPE_STUTTER_CONTROL__STUTTER_SELF_REFRESH_FORCE_ON_MASK 0x00000800L 6428de2bdb3dSTom St Denis #define DPG_PIPE_STUTTER_CONTROL__STUTTER_SELF_REFRESH_FORCE_ON__SHIFT 0x0000000b 6429de2bdb3dSTom St Denis #define DPG_PIPE_STUTTER_CONTROL__STUTTER_URGENT_IN_NOT_SELF_REFRESH_MASK 0x00000400L 6430de2bdb3dSTom St Denis #define DPG_PIPE_STUTTER_CONTROL__STUTTER_URGENT_IN_NOT_SELF_REFRESH__SHIFT 0x0000000a 6431de2bdb3dSTom St Denis #define DPG_PIPE_STUTTER_CONTROL__STUTTER_WM_HIGH_EXCLUDES_VBLANK_MASK 0x00000200L 6432de2bdb3dSTom St Denis #define DPG_PIPE_STUTTER_CONTROL__STUTTER_WM_HIGH_EXCLUDES_VBLANK__SHIFT 0x00000009 6433de2bdb3dSTom St Denis #define DPG_PIPE_STUTTER_CONTROL__STUTTER_WM_HIGH_FORCE_ON_MASK 0x00000100L 6434de2bdb3dSTom St Denis #define DPG_PIPE_STUTTER_CONTROL__STUTTER_WM_HIGH_FORCE_ON__SHIFT 0x00000008 6435de2bdb3dSTom St Denis #define DPG_PIPE_URGENCY_CONTROL__URGENCY_HIGH_WATERMARK_MASK 0xffff0000L 6436de2bdb3dSTom St Denis #define DPG_PIPE_URGENCY_CONTROL__URGENCY_HIGH_WATERMARK__SHIFT 0x00000010 6437de2bdb3dSTom St Denis #define DPG_PIPE_URGENCY_CONTROL__URGENCY_LOW_WATERMARK_MASK 0x0000ffffL 6438de2bdb3dSTom St Denis #define DPG_PIPE_URGENCY_CONTROL__URGENCY_LOW_WATERMARK__SHIFT 0x00000000 6439de2bdb3dSTom St Denis #define DPG_TEST_DEBUG_DATA__DPG_TEST_DEBUG_DATA_MASK 0xffffffffL 6440de2bdb3dSTom St Denis #define DPG_TEST_DEBUG_DATA__DPG_TEST_DEBUG_DATA__SHIFT 0x00000000 6441de2bdb3dSTom St Denis #define DPG_TEST_DEBUG_INDEX__DPG_TEST_DEBUG_INDEX_MASK 0x000000ffL 6442de2bdb3dSTom St Denis #define DPG_TEST_DEBUG_INDEX__DPG_TEST_DEBUG_INDEX__SHIFT 0x00000000 6443de2bdb3dSTom St Denis #define DPG_TEST_DEBUG_INDEX__DPG_TEST_DEBUG_WRITE_EN_MASK 0x00000100L 6444de2bdb3dSTom St Denis #define DPG_TEST_DEBUG_INDEX__DPG_TEST_DEBUG_WRITE_EN__SHIFT 0x00000008 6445de2bdb3dSTom St Denis #define DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE_MASK 0x00000001L 6446de2bdb3dSTom St Denis #define DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE__SHIFT 0x00000000 6447de2bdb3dSTom St Denis #define DP_LINK_CNTL__DP_EMBEDDED_PANEL_MODE_MASK 0x00020000L 6448de2bdb3dSTom St Denis #define DP_LINK_CNTL__DP_EMBEDDED_PANEL_MODE__SHIFT 0x00000011 6449de2bdb3dSTom St Denis #define DP_LINK_CNTL__DP_LINK_STATUS_MASK 0x00000100L 6450de2bdb3dSTom St Denis #define DP_LINK_CNTL__DP_LINK_STATUS__SHIFT 0x00000008 6451de2bdb3dSTom St Denis #define DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE_MASK 0x00000010L 6452de2bdb3dSTom St Denis #define DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE__SHIFT 0x00000004 6453de2bdb3dSTom St Denis #define DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL_MASK 0x0003ffffL 6454de2bdb3dSTom St Denis #define DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL__SHIFT 0x00000000 6455de2bdb3dSTom St Denis #define DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE_MASK 0x01000000L 6456de2bdb3dSTom St Denis #define DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE__SHIFT 0x00000018 6457de2bdb3dSTom St Denis #define DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE_MASK 0x10000000L 6458de2bdb3dSTom St Denis #define DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE__SHIFT 0x0000001c 6459de2bdb3dSTom St Denis #define DP_MSA_COLORIMETRY__DP_MSA_MISC0_OVERRIDE_ENABLE_MASK 0x00000100L 6460de2bdb3dSTom St Denis #define DP_MSA_COLORIMETRY__DP_MSA_MISC0_OVERRIDE_ENABLE__SHIFT 0x00000008 6461de2bdb3dSTom St Denis #define DP_MSA_COLORIMETRY__DP_MSA_MISC0_OVERRIDE_MASK 0x000000ffL 6462de2bdb3dSTom St Denis #define DP_MSA_COLORIMETRY__DP_MSA_MISC0_OVERRIDE__SHIFT 0x00000000 6463de2bdb3dSTom St Denis #define DP_MSA_MISC__DP_MSA_MISC1_MASK 0x000000f8L 6464de2bdb3dSTom St Denis #define DP_MSA_MISC__DP_MSA_MISC1__SHIFT 0x00000003 6465de2bdb3dSTom St Denis #define DP_MSA_MISC__DP_MSA_MISC2_MASK 0x0000ff00L 6466de2bdb3dSTom St Denis #define DP_MSA_MISC__DP_MSA_MISC2__SHIFT 0x00000008 6467de2bdb3dSTom St Denis #define DP_MSA_MISC__DP_MSA_MISC3_MASK 0x00ff0000L 6468de2bdb3dSTom St Denis #define DP_MSA_MISC__DP_MSA_MISC3__SHIFT 0x00000010 6469de2bdb3dSTom St Denis #define DP_MSA_MISC__DP_MSA_MISC4_MASK 0xff000000L 6470de2bdb3dSTom St Denis #define DP_MSA_MISC__DP_MSA_MISC4__SHIFT 0x00000018 6471de2bdb3dSTom St Denis #define DP_MSA_V_TIMING_OVERRIDE1__DP_MSA_V_TIMING_OVERRIDE_EN_MASK 0x00000001L 6472de2bdb3dSTom St Denis #define DP_MSA_V_TIMING_OVERRIDE1__DP_MSA_V_TIMING_OVERRIDE_EN__SHIFT 0x00000000 6473de2bdb3dSTom St Denis #define DP_MSA_V_TIMING_OVERRIDE1__DP_MSA_V_TOTAL_OVERRIDE_MASK 0x0001fff0L 6474de2bdb3dSTom St Denis #define DP_MSA_V_TIMING_OVERRIDE1__DP_MSA_V_TOTAL_OVERRIDE__SHIFT 0x00000004 6475de2bdb3dSTom St Denis #define DP_MSA_V_TIMING_OVERRIDE2__DP_MSA_V_BLANK_END_OVERRIDE_MASK 0x1fff0000L 6476de2bdb3dSTom St Denis #define DP_MSA_V_TIMING_OVERRIDE2__DP_MSA_V_BLANK_END_OVERRIDE__SHIFT 0x00000010 6477de2bdb3dSTom St Denis #define DP_MSA_V_TIMING_OVERRIDE2__DP_MSA_V_BLANK_START_OVERRIDE_MASK 0x00001fffL 6478de2bdb3dSTom St Denis #define DP_MSA_V_TIMING_OVERRIDE2__DP_MSA_V_BLANK_START_OVERRIDE__SHIFT 0x00000000 6479de2bdb3dSTom St Denis #define DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME_MASK 0x000003ffL 6480de2bdb3dSTom St Denis #define DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME__SHIFT 0x00000000 6481de2bdb3dSTom St Denis #define DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE_MASK 0x00030000L 6482de2bdb3dSTom St Denis #define DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE__SHIFT 0x00000010 6483de2bdb3dSTom St Denis #define DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE_MASK 0x00000001L 6484de2bdb3dSTom St Denis #define DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE__SHIFT 0x00000000 6485de2bdb3dSTom St Denis #define DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE_MASK 0x00000010L 6486de2bdb3dSTom St Denis #define DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE__SHIFT 0x00000004 6487de2bdb3dSTom St Denis #define DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER_MASK 0x00000100L 6488de2bdb3dSTom St Denis #define DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER__SHIFT 0x00000008 6489de2bdb3dSTom St Denis #define DP_MSE_RATE_CNTL__DP_MSE_RATE_X_MASK 0xfc000000L 6490de2bdb3dSTom St Denis #define DP_MSE_RATE_CNTL__DP_MSE_RATE_X__SHIFT 0x0000001a 6491de2bdb3dSTom St Denis #define DP_MSE_RATE_CNTL__DP_MSE_RATE_Y_MASK 0x03ffffffL 6492de2bdb3dSTom St Denis #define DP_MSE_RATE_CNTL__DP_MSE_RATE_Y__SHIFT 0x00000000 6493de2bdb3dSTom St Denis #define DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING_MASK 0x00000001L 6494de2bdb3dSTom St Denis #define DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING__SHIFT 0x00000000 6495de2bdb3dSTom St Denis #define DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0_MASK 0x00003f00L 6496de2bdb3dSTom St Denis #define DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0__SHIFT 0x00000008 6497de2bdb3dSTom St Denis #define DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1_MASK 0x3f000000L 6498de2bdb3dSTom St Denis #define DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1__SHIFT 0x00000018 6499de2bdb3dSTom St Denis #define DP_MSE_SAT0__DP_MSE_SAT_SRC0_MASK 0x00000007L 6500de2bdb3dSTom St Denis #define DP_MSE_SAT0__DP_MSE_SAT_SRC0__SHIFT 0x00000000 6501de2bdb3dSTom St Denis #define DP_MSE_SAT0__DP_MSE_SAT_SRC1_MASK 0x00070000L 6502de2bdb3dSTom St Denis #define DP_MSE_SAT0__DP_MSE_SAT_SRC1__SHIFT 0x00000010 6503de2bdb3dSTom St Denis #define DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2_MASK 0x00003f00L 6504de2bdb3dSTom St Denis #define DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2__SHIFT 0x00000008 6505de2bdb3dSTom St Denis #define DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3_MASK 0x3f000000L 6506de2bdb3dSTom St Denis #define DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3__SHIFT 0x00000018 6507de2bdb3dSTom St Denis #define DP_MSE_SAT1__DP_MSE_SAT_SRC2_MASK 0x00000007L 6508de2bdb3dSTom St Denis #define DP_MSE_SAT1__DP_MSE_SAT_SRC2__SHIFT 0x00000000 6509de2bdb3dSTom St Denis #define DP_MSE_SAT1__DP_MSE_SAT_SRC3_MASK 0x00070000L 6510de2bdb3dSTom St Denis #define DP_MSE_SAT1__DP_MSE_SAT_SRC3__SHIFT 0x00000010 6511de2bdb3dSTom St Denis #define DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4_MASK 0x00003f00L 6512de2bdb3dSTom St Denis #define DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4__SHIFT 0x00000008 6513de2bdb3dSTom St Denis #define DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5_MASK 0x3f000000L 6514de2bdb3dSTom St Denis #define DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5__SHIFT 0x00000018 6515de2bdb3dSTom St Denis #define DP_MSE_SAT2__DP_MSE_SAT_SRC4_MASK 0x00000007L 6516de2bdb3dSTom St Denis #define DP_MSE_SAT2__DP_MSE_SAT_SRC4__SHIFT 0x00000000 6517de2bdb3dSTom St Denis #define DP_MSE_SAT2__DP_MSE_SAT_SRC5_MASK 0x00070000L 6518de2bdb3dSTom St Denis #define DP_MSE_SAT2__DP_MSE_SAT_SRC5__SHIFT 0x00000010 6519de2bdb3dSTom St Denis #define DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT_MASK 0x00000100L 6520de2bdb3dSTom St Denis #define DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT__SHIFT 0x00000008 6521de2bdb3dSTom St Denis #define DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE_MASK 0x00000003L 6522de2bdb3dSTom St Denis #define DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE__SHIFT 0x00000000 6523de2bdb3dSTom St Denis #define DP_PIXEL_FORMAT__DP_COMPONENT_DEPTH_MASK 0x07000000L 6524de2bdb3dSTom St Denis #define DP_PIXEL_FORMAT__DP_COMPONENT_DEPTH__SHIFT 0x00000018 6525de2bdb3dSTom St Denis #define DP_PIXEL_FORMAT__DP_DYN_RANGE_MASK 0x00000100L 6526de2bdb3dSTom St Denis #define DP_PIXEL_FORMAT__DP_DYN_RANGE__SHIFT 0x00000008 6527de2bdb3dSTom St Denis #define DP_PIXEL_FORMAT__DP_PIXEL_ENCODING_MASK 0x00000003L 6528de2bdb3dSTom St Denis #define DP_PIXEL_FORMAT__DP_PIXEL_ENCODING__SHIFT 0x00000000 6529de2bdb3dSTom St Denis #define DP_PIXEL_FORMAT__DP_YCBCR_RANGE_MASK 0x00010000L 6530de2bdb3dSTom St Denis #define DP_PIXEL_FORMAT__DP_YCBCR_RANGE__SHIFT 0x00000010 6531de2bdb3dSTom St Denis #define DP_SEC_AUD_M__DP_SEC_AUD_M_MASK 0x00ffffffL 6532de2bdb3dSTom St Denis #define DP_SEC_AUD_M__DP_SEC_AUD_M__SHIFT 0x00000000 6533de2bdb3dSTom St Denis #define DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK_MASK 0x00ffffffL 6534de2bdb3dSTom St Denis #define DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK__SHIFT 0x00000000 6535de2bdb3dSTom St Denis #define DP_SEC_AUD_N__DP_SEC_AUD_N_MASK 0x00ffffffL 6536de2bdb3dSTom St Denis #define DP_SEC_AUD_N__DP_SEC_AUD_N__SHIFT 0x00000000 6537de2bdb3dSTom St Denis #define DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK_MASK 0x00ffffffL 6538de2bdb3dSTom St Denis #define DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK__SHIFT 0x00000000 6539de2bdb3dSTom St Denis #define DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE_MASK 0x00000001L 6540de2bdb3dSTom St Denis #define DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE__SHIFT 0x00000000 6541de2bdb3dSTom St Denis #define DP_SEC_CNTL__DP_SEC_ACM_ENABLE_MASK 0x00010000L 6542de2bdb3dSTom St Denis #define DP_SEC_CNTL__DP_SEC_ACM_ENABLE__SHIFT 0x00000010 6543de2bdb3dSTom St Denis #define DP_SEC_CNTL__DP_SEC_AIP_ENABLE_MASK 0x00001000L 6544de2bdb3dSTom St Denis #define DP_SEC_CNTL__DP_SEC_AIP_ENABLE__SHIFT 0x0000000c 6545de2bdb3dSTom St Denis #define DP_SEC_CNTL__DP_SEC_ASP_ENABLE_MASK 0x00000010L 6546de2bdb3dSTom St Denis #define DP_SEC_CNTL__DP_SEC_ASP_ENABLE__SHIFT 0x00000004 6547de2bdb3dSTom St Denis #define DP_SEC_CNTL__DP_SEC_ATP_ENABLE_MASK 0x00000100L 6548de2bdb3dSTom St Denis #define DP_SEC_CNTL__DP_SEC_ATP_ENABLE__SHIFT 0x00000008 6549de2bdb3dSTom St Denis #define DP_SEC_CNTL__DP_SEC_AVI_ENABLE_MASK 0x01000000L 6550de2bdb3dSTom St Denis #define DP_SEC_CNTL__DP_SEC_AVI_ENABLE__SHIFT 0x00000018 6551de2bdb3dSTom St Denis #define DP_SEC_CNTL__DP_SEC_GSP0_ENABLE_MASK 0x00100000L 6552de2bdb3dSTom St Denis #define DP_SEC_CNTL__DP_SEC_GSP0_ENABLE__SHIFT 0x00000014 6553de2bdb3dSTom St Denis #define DP_SEC_CNTL__DP_SEC_GSP1_ENABLE_MASK 0x00200000L 6554de2bdb3dSTom St Denis #define DP_SEC_CNTL__DP_SEC_GSP1_ENABLE__SHIFT 0x00000015 6555de2bdb3dSTom St Denis #define DP_SEC_CNTL__DP_SEC_GSP2_ENABLE_MASK 0x00400000L 6556de2bdb3dSTom St Denis #define DP_SEC_CNTL__DP_SEC_GSP2_ENABLE__SHIFT 0x00000016 6557de2bdb3dSTom St Denis #define DP_SEC_CNTL__DP_SEC_GSP3_ENABLE_MASK 0x00800000L 6558de2bdb3dSTom St Denis #define DP_SEC_CNTL__DP_SEC_GSP3_ENABLE__SHIFT 0x00000017 6559de2bdb3dSTom St Denis #define DP_SEC_CNTL__DP_SEC_MPG_ENABLE_MASK 0x10000000L 6560de2bdb3dSTom St Denis #define DP_SEC_CNTL__DP_SEC_MPG_ENABLE__SHIFT 0x0000001c 6561de2bdb3dSTom St Denis #define DP_SEC_CNTL__DP_SEC_STREAM_ENABLE_MASK 0x00000001L 6562de2bdb3dSTom St Denis #define DP_SEC_CNTL__DP_SEC_STREAM_ENABLE__SHIFT 0x00000000 6563de2bdb3dSTom St Denis #define DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION_MASK 0x00000fffL 6564de2bdb3dSTom St Denis #define DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION__SHIFT 0x00000000 6565de2bdb3dSTom St Denis #define DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH_MASK 0xffff0000L 6566de2bdb3dSTom St Denis #define DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH__SHIFT 0x00000010 6567de2bdb3dSTom St Denis #define DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH_MASK 0xffff0000L 6568de2bdb3dSTom St Denis #define DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH__SHIFT 0x00000010 6569de2bdb3dSTom St Denis #define DP_SEC_FRAMING2__DP_SEC_START_POSITION_MASK 0x0000ffffL 6570de2bdb3dSTom St Denis #define DP_SEC_FRAMING2__DP_SEC_START_POSITION__SHIFT 0x00000000 6571de2bdb3dSTom St Denis #define DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE_MASK 0x00003fffL 6572de2bdb3dSTom St Denis #define DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE__SHIFT 0x00000000 6573de2bdb3dSTom St Denis #define DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH_MASK 0xffff0000L 6574de2bdb3dSTom St Denis #define DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH__SHIFT 0x00000010 6575de2bdb3dSTom St Denis #define DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_MASK 0x10000000L 6576de2bdb3dSTom St Denis #define DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE__SHIFT 0x0000001c 6577de2bdb3dSTom St Denis #define DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS_MASK 0x20000000L 6578de2bdb3dSTom St Denis #define DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS__SHIFT 0x0000001d 6579de2bdb3dSTom St Denis #define DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK_MASK 0x01000000L 6580de2bdb3dSTom St Denis #define DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK__SHIFT 0x00000018 6581de2bdb3dSTom St Denis #define DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS_MASK 0x00100000L 6582de2bdb3dSTom St Denis #define DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS__SHIFT 0x00000014 6583de2bdb3dSTom St Denis #define DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE_MASK 0x00010000L 6584de2bdb3dSTom St Denis #define DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE__SHIFT 0x00000010 6585de2bdb3dSTom St Denis #define DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE_MASK 0x0000000eL 6586de2bdb3dSTom St Denis #define DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE__SHIFT 0x00000001 6587de2bdb3dSTom St Denis #define DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY_MASK 0x00000010L 6588de2bdb3dSTom St Denis #define DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY__SHIFT 0x00000004 6589de2bdb3dSTom St Denis #define DP_SEC_PACKET_CNTL__DP_SEC_VERSION_MASK 0x00003f00L 6590de2bdb3dSTom St Denis #define DP_SEC_PACKET_CNTL__DP_SEC_VERSION__SHIFT 0x00000008 6591de2bdb3dSTom St Denis #define DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE_MASK 0x00000001L 6592de2bdb3dSTom St Denis #define DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE__SHIFT 0x00000000 6593de2bdb3dSTom St Denis #define DP_STEER_FIFO__DP_STEER_FIFO_RESET_MASK 0x00000001L 6594de2bdb3dSTom St Denis #define DP_STEER_FIFO__DP_STEER_FIFO_RESET__SHIFT 0x00000000 6595de2bdb3dSTom St Denis #define DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK_MASK 0x00000040L 6596de2bdb3dSTom St Denis #define DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK__SHIFT 0x00000006 6597de2bdb3dSTom St Denis #define DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG_MASK 0x00000010L 6598de2bdb3dSTom St Denis #define DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG__SHIFT 0x00000004 6599de2bdb3dSTom St Denis #define DP_STEER_FIFO__DP_STEER_OVERFLOW_INT_MASK 0x00000020L 6600de2bdb3dSTom St Denis #define DP_STEER_FIFO__DP_STEER_OVERFLOW_INT__SHIFT 0x00000005 6601de2bdb3dSTom St Denis #define DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK_MASK 0x00000080L 6602de2bdb3dSTom St Denis #define DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK__SHIFT 0x00000007 6603de2bdb3dSTom St Denis #define DP_STEER_FIFO__DP_TU_OVERFLOW_ACK_MASK 0x00001000L 6604de2bdb3dSTom St Denis #define DP_STEER_FIFO__DP_TU_OVERFLOW_ACK__SHIFT 0x0000000c 6605de2bdb3dSTom St Denis #define DP_STEER_FIFO__DP_TU_OVERFLOW_FLAG_MASK 0x00000100L 6606de2bdb3dSTom St Denis #define DP_STEER_FIFO__DP_TU_OVERFLOW_FLAG__SHIFT 0x00000008 6607de2bdb3dSTom St Denis #define DP_TEST_DEBUG_DATA__DP_TEST_DEBUG_DATA_MASK 0xffffffffL 6608de2bdb3dSTom St Denis #define DP_TEST_DEBUG_DATA__DP_TEST_DEBUG_DATA__SHIFT 0x00000000 6609de2bdb3dSTom St Denis #define DP_TEST_DEBUG_INDEX__DP_TEST_DEBUG_INDEX_MASK 0x000000ffL 6610de2bdb3dSTom St Denis #define DP_TEST_DEBUG_INDEX__DP_TEST_DEBUG_INDEX__SHIFT 0x00000000 6611de2bdb3dSTom St Denis #define DP_TEST_DEBUG_INDEX__DP_TEST_DEBUG_WRITE_EN_MASK 0x00000100L 6612de2bdb3dSTom St Denis #define DP_TEST_DEBUG_INDEX__DP_TEST_DEBUG_WRITE_EN__SHIFT 0x00000008 6613de2bdb3dSTom St Denis #define DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK_MASK 0x00000002L 6614de2bdb3dSTom St Denis #define DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK__SHIFT 0x00000001 6615de2bdb3dSTom St Denis #define DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT_MASK 0x00000001L 6616de2bdb3dSTom St Denis #define DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT__SHIFT 0x00000000 6617de2bdb3dSTom St Denis #define DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK_MASK 0x00000004L 6618de2bdb3dSTom St Denis #define DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK__SHIFT 0x00000002 6619de2bdb3dSTom St Denis #define DP_VID_M__DP_VID_M_MASK 0x00ffffffL 6620de2bdb3dSTom St Denis #define DP_VID_M__DP_VID_M__SHIFT 0x00000000 6621de2bdb3dSTom St Denis #define DP_VID_MSA_VBID__DP_VID_MSA_LOCATION_MASK 0x00000fffL 6622de2bdb3dSTom St Denis #define DP_VID_MSA_VBID__DP_VID_MSA_LOCATION__SHIFT 0x00000000 6623de2bdb3dSTom St Denis #define DP_VID_MSA_VBID__DP_VID_MSA_TOP_FIELD_MODE_MASK 0x00010000L 6624de2bdb3dSTom St Denis #define DP_VID_MSA_VBID__DP_VID_MSA_TOP_FIELD_MODE__SHIFT 0x00000010 6625de2bdb3dSTom St Denis #define DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL_MASK 0x01000000L 6626de2bdb3dSTom St Denis #define DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL__SHIFT 0x00000018 6627de2bdb3dSTom St Denis #define DP_VID_N__DP_VID_N_MASK 0x00ffffffL 6628de2bdb3dSTom St Denis #define DP_VID_N__DP_VID_N__SHIFT 0x00000000 6629de2bdb3dSTom St Denis #define DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT_MASK 0x00100000L 6630de2bdb3dSTom St Denis #define DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT__SHIFT 0x00000014 6631de2bdb3dSTom St Denis #define DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER_MASK 0x00000300L 6632de2bdb3dSTom St Denis #define DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER__SHIFT 0x00000008 6633de2bdb3dSTom St Denis #define DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE_MASK 0x00000001L 6634de2bdb3dSTom St Denis #define DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE__SHIFT 0x00000000 6635de2bdb3dSTom St Denis #define DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS_MASK 0x00010000L 6636de2bdb3dSTom St Denis #define DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS__SHIFT 0x00000010 6637de2bdb3dSTom St Denis #define DP_VID_TIMING__DP_VID_M_N_GEN_EN_MASK 0x00000100L 6638de2bdb3dSTom St Denis #define DP_VID_TIMING__DP_VID_M_N_GEN_EN__SHIFT 0x00000008 6639de2bdb3dSTom St Denis #define DP_VID_TIMING__DP_VID_N_DIV_MASK 0xff000000L 6640de2bdb3dSTom St Denis #define DP_VID_TIMING__DP_VID_N_DIV__SHIFT 0x00000018 6641de2bdb3dSTom St Denis #define DP_VID_TIMING__DP_VID_TIMING_MODE_MASK 0x00000001L 6642de2bdb3dSTom St Denis #define DP_VID_TIMING__DP_VID_TIMING_MODE__SHIFT 0x00000000 6643de2bdb3dSTom St Denis #define DVOACLKC_CNTL__DVOACLKC_COARSE_ADJUST_EN_MASK 0x00020000L 6644de2bdb3dSTom St Denis #define DVOACLKC_CNTL__DVOACLKC_COARSE_ADJUST_EN__SHIFT 0x00000011 6645de2bdb3dSTom St Denis #define DVOACLKC_CNTL__DVOACLKC_COARSE_SKEW_CNTL_MASK 0x00001f00L 6646de2bdb3dSTom St Denis #define DVOACLKC_CNTL__DVOACLKC_COARSE_SKEW_CNTL__SHIFT 0x00000008 6647de2bdb3dSTom St Denis #define DVOACLKC_CNTL__DVOACLKC_FINE_ADJUST_EN_MASK 0x00010000L 6648de2bdb3dSTom St Denis #define DVOACLKC_CNTL__DVOACLKC_FINE_ADJUST_EN__SHIFT 0x00000010 6649de2bdb3dSTom St Denis #define DVOACLKC_CNTL__DVOACLKC_FINE_SKEW_CNTL_MASK 0x00000007L 6650de2bdb3dSTom St Denis #define DVOACLKC_CNTL__DVOACLKC_FINE_SKEW_CNTL__SHIFT 0x00000000 6651de2bdb3dSTom St Denis #define DVOACLKC_CNTL__DVOACLKC_IN_PHASE_MASK 0x00040000L 6652de2bdb3dSTom St Denis #define DVOACLKC_CNTL__DVOACLKC_IN_PHASE__SHIFT 0x00000012 6653de2bdb3dSTom St Denis #define DVOACLKC_MVP_CNTL__DVOACLKC_MVP_COARSE_ADJUST_EN_MASK 0x00020000L 6654de2bdb3dSTom St Denis #define DVOACLKC_MVP_CNTL__DVOACLKC_MVP_COARSE_ADJUST_EN__SHIFT 0x00000011 6655de2bdb3dSTom St Denis #define DVOACLKC_MVP_CNTL__DVOACLKC_MVP_COARSE_SKEW_CNTL_MASK 0x00001f00L 6656de2bdb3dSTom St Denis #define DVOACLKC_MVP_CNTL__DVOACLKC_MVP_COARSE_SKEW_CNTL__SHIFT 0x00000008 6657de2bdb3dSTom St Denis #define DVOACLKC_MVP_CNTL__DVOACLKC_MVP_FINE_ADJUST_EN_MASK 0x00010000L 6658de2bdb3dSTom St Denis #define DVOACLKC_MVP_CNTL__DVOACLKC_MVP_FINE_ADJUST_EN__SHIFT 0x00000010 6659de2bdb3dSTom St Denis #define DVOACLKC_MVP_CNTL__DVOACLKC_MVP_FINE_SKEW_CNTL_MASK 0x00000007L 6660de2bdb3dSTom St Denis #define DVOACLKC_MVP_CNTL__DVOACLKC_MVP_FINE_SKEW_CNTL__SHIFT 0x00000000 6661de2bdb3dSTom St Denis #define DVOACLKC_MVP_CNTL__DVOACLKC_MVP_IN_PHASE_MASK 0x00040000L 6662de2bdb3dSTom St Denis #define DVOACLKC_MVP_CNTL__DVOACLKC_MVP_IN_PHASE__SHIFT 0x00000012 6663de2bdb3dSTom St Denis #define DVOACLKC_MVP_CNTL__DVOACLKC_MVP_SKEW_PHASE_OVERRIDE_MASK 0x00100000L 6664de2bdb3dSTom St Denis #define DVOACLKC_MVP_CNTL__DVOACLKC_MVP_SKEW_PHASE_OVERRIDE__SHIFT 0x00000014 6665de2bdb3dSTom St Denis #define DVOACLKC_MVP_CNTL__MVP_CLK_A_SRC_SEL_MASK 0x03000000L 6666de2bdb3dSTom St Denis #define DVOACLKC_MVP_CNTL__MVP_CLK_A_SRC_SEL__SHIFT 0x00000018 6667de2bdb3dSTom St Denis #define DVOACLKC_MVP_CNTL__MVP_CLK_B_SRC_SEL_MASK 0x30000000L 6668de2bdb3dSTom St Denis #define DVOACLKC_MVP_CNTL__MVP_CLK_B_SRC_SEL__SHIFT 0x0000001c 6669de2bdb3dSTom St Denis #define DVOACLKD_CNTL__DVOACLKD_COARSE_ADJUST_EN_MASK 0x00020000L 6670de2bdb3dSTom St Denis #define DVOACLKD_CNTL__DVOACLKD_COARSE_ADJUST_EN__SHIFT 0x00000011 6671de2bdb3dSTom St Denis #define DVOACLKD_CNTL__DVOACLKD_COARSE_SKEW_CNTL_MASK 0x00001f00L 6672de2bdb3dSTom St Denis #define DVOACLKD_CNTL__DVOACLKD_COARSE_SKEW_CNTL__SHIFT 0x00000008 6673de2bdb3dSTom St Denis #define DVOACLKD_CNTL__DVOACLKD_FINE_ADJUST_EN_MASK 0x00010000L 6674de2bdb3dSTom St Denis #define DVOACLKD_CNTL__DVOACLKD_FINE_ADJUST_EN__SHIFT 0x00000010 6675de2bdb3dSTom St Denis #define DVOACLKD_CNTL__DVOACLKD_FINE_SKEW_CNTL_MASK 0x00000007L 6676de2bdb3dSTom St Denis #define DVOACLKD_CNTL__DVOACLKD_FINE_SKEW_CNTL__SHIFT 0x00000000 6677de2bdb3dSTom St Denis #define DVOACLKD_CNTL__DVOACLKD_IN_PHASE_MASK 0x00040000L 6678de2bdb3dSTom St Denis #define DVOACLKD_CNTL__DVOACLKD_IN_PHASE__SHIFT 0x00000012 6679de2bdb3dSTom St Denis #define DVO_CLK_ENABLE__DVO_CLK_ENABLE_MASK 0x00000001L 6680de2bdb3dSTom St Denis #define DVO_CLK_ENABLE__DVO_CLK_ENABLE__SHIFT 0x00000000 6681de2bdb3dSTom St Denis #define DVO_CONTROL__DVO_COLOR_FORMAT_MASK 0x03000000L 6682de2bdb3dSTom St Denis #define DVO_CONTROL__DVO_COLOR_FORMAT__SHIFT 0x00000018 6683de2bdb3dSTom St Denis #define DVO_CONTROL__DVO_CTL3_MASK 0x80000000L 6684de2bdb3dSTom St Denis #define DVO_CONTROL__DVO_CTL3__SHIFT 0x0000001f 6685de2bdb3dSTom St Denis #define DVO_CONTROL__DVO_DUAL_CHANNEL_EN_MASK 0x00000100L 6686de2bdb3dSTom St Denis #define DVO_CONTROL__DVO_DUAL_CHANNEL_EN__SHIFT 0x00000008 6687de2bdb3dSTom St Denis #define DVO_CONTROL__DVO_INVERT_DVOCLK_MASK 0x00040000L 6688de2bdb3dSTom St Denis #define DVO_CONTROL__DVO_INVERT_DVOCLK__SHIFT 0x00000012 6689de2bdb3dSTom St Denis #define DVO_CONTROL__DVO_RATE_SELECT_MASK 0x00000001L 6690de2bdb3dSTom St Denis #define DVO_CONTROL__DVO_RATE_SELECT__SHIFT 0x00000000 6691de2bdb3dSTom St Denis #define DVO_CONTROL__DVO_RESET_FIFO_MASK 0x00010000L 6692de2bdb3dSTom St Denis #define DVO_CONTROL__DVO_RESET_FIFO__SHIFT 0x00000010 6693de2bdb3dSTom St Denis #define DVO_CONTROL__DVO_SDRCLK_SEL_MASK 0x00000002L 6694de2bdb3dSTom St Denis #define DVO_CONTROL__DVO_SDRCLK_SEL__SHIFT 0x00000001 6695de2bdb3dSTom St Denis #define DVO_CONTROL__DVO_SYNC_PHASE_MASK 0x00020000L 6696de2bdb3dSTom St Denis #define DVO_CONTROL__DVO_SYNC_PHASE__SHIFT 0x00000011 6697de2bdb3dSTom St Denis #define DVO_CRC2_SIG_MASK__DVO_CRC2_SIG_MASK_MASK 0x07ffffffL 6698de2bdb3dSTom St Denis #define DVO_CRC2_SIG_MASK__DVO_CRC2_SIG_MASK__SHIFT 0x00000000 6699de2bdb3dSTom St Denis #define DVO_CRC2_SIG_RESULT__DVO_CRC2_SIG_RESULT_MASK 0x07ffffffL 6700de2bdb3dSTom St Denis #define DVO_CRC2_SIG_RESULT__DVO_CRC2_SIG_RESULT__SHIFT 0x00000000 6701de2bdb3dSTom St Denis #define DVO_CRC_EN__DVO_CRC2_EN_MASK 0x00010000L 6702de2bdb3dSTom St Denis #define DVO_CRC_EN__DVO_CRC2_EN__SHIFT 0x00000010 6703de2bdb3dSTom St Denis #define DVO_ENABLE__DVO_ENABLE_MASK 0x00000001L 6704de2bdb3dSTom St Denis #define DVO_ENABLE__DVO_ENABLE__SHIFT 0x00000000 6705de2bdb3dSTom St Denis #define DVO_FIFO_ERROR_STATUS__DVO_FIFO_CAL_AVERAGE_LEVEL_MASK 0x0000fc00L 6706de2bdb3dSTom St Denis #define DVO_FIFO_ERROR_STATUS__DVO_FIFO_CAL_AVERAGE_LEVEL__SHIFT 0x0000000a 6707de2bdb3dSTom St Denis #define DVO_FIFO_ERROR_STATUS__DVO_FIFO_CALIBRATED_MASK 0x20000000L 6708de2bdb3dSTom St Denis #define DVO_FIFO_ERROR_STATUS__DVO_FIFO_CALIBRATED__SHIFT 0x0000001d 6709de2bdb3dSTom St Denis #define DVO_FIFO_ERROR_STATUS__DVO_FIFO_ERROR_ACK_MASK 0x00000100L 6710de2bdb3dSTom St Denis #define DVO_FIFO_ERROR_STATUS__DVO_FIFO_ERROR_ACK__SHIFT 0x00000008 6711de2bdb3dSTom St Denis #define DVO_FIFO_ERROR_STATUS__DVO_FIFO_FORCE_RECAL_AVERAGE_MASK 0x40000000L 6712de2bdb3dSTom St Denis #define DVO_FIFO_ERROR_STATUS__DVO_FIFO_FORCE_RECAL_AVERAGE__SHIFT 0x0000001e 6713de2bdb3dSTom St Denis #define DVO_FIFO_ERROR_STATUS__DVO_FIFO_FORCE_RECOMP_MINMAX_MASK 0x80000000L 6714de2bdb3dSTom St Denis #define DVO_FIFO_ERROR_STATUS__DVO_FIFO_FORCE_RECOMP_MINMAX__SHIFT 0x0000001f 6715de2bdb3dSTom St Denis #define DVO_FIFO_ERROR_STATUS__DVO_FIFO_LEVEL_ERROR_MASK 0x00000001L 6716de2bdb3dSTom St Denis #define DVO_FIFO_ERROR_STATUS__DVO_FIFO_LEVEL_ERROR__SHIFT 0x00000000 6717de2bdb3dSTom St Denis #define DVO_FIFO_ERROR_STATUS__DVO_FIFO_MAXIMUM_LEVEL_MASK 0x000f0000L 6718de2bdb3dSTom St Denis #define DVO_FIFO_ERROR_STATUS__DVO_FIFO_MAXIMUM_LEVEL__SHIFT 0x00000010 6719de2bdb3dSTom St Denis #define DVO_FIFO_ERROR_STATUS__DVO_FIFO_MINIMUM_LEVEL_MASK 0x03c00000L 6720de2bdb3dSTom St Denis #define DVO_FIFO_ERROR_STATUS__DVO_FIFO_MINIMUM_LEVEL__SHIFT 0x00000016 6721de2bdb3dSTom St Denis #define DVO_FIFO_ERROR_STATUS__DVO_FIFO_OVERWRITE_LEVEL_MASK 0x000000fcL 6722de2bdb3dSTom St Denis #define DVO_FIFO_ERROR_STATUS__DVO_FIFO_OVERWRITE_LEVEL__SHIFT 0x00000002 6723de2bdb3dSTom St Denis #define DVO_FIFO_ERROR_STATUS__DVO_FIFO_USE_OVERWRITE_LEVEL_MASK 0x00000002L 6724de2bdb3dSTom St Denis #define DVO_FIFO_ERROR_STATUS__DVO_FIFO_USE_OVERWRITE_LEVEL__SHIFT 0x00000001 6725de2bdb3dSTom St Denis #define DVO_OUTPUT__DVO_CLOCK_MODE_MASK 0x00000100L 6726de2bdb3dSTom St Denis #define DVO_OUTPUT__DVO_CLOCK_MODE__SHIFT 0x00000008 6727de2bdb3dSTom St Denis #define DVO_OUTPUT__DVO_OUTPUT_ENABLE_MODE_MASK 0x00000003L 6728de2bdb3dSTom St Denis #define DVO_OUTPUT__DVO_OUTPUT_ENABLE_MODE__SHIFT 0x00000000 6729de2bdb3dSTom St Denis #define DVO_SKEW_ADJUST__DVO_SKEW_ADJUST_MASK 0xffffffffL 6730de2bdb3dSTom St Denis #define DVO_SKEW_ADJUST__DVO_SKEW_ADJUST__SHIFT 0x00000000 6731de2bdb3dSTom St Denis #define DVO_SOURCE_SELECT__DVO_SOURCE_SELECT_MASK 0x00000007L 6732de2bdb3dSTom St Denis #define DVO_SOURCE_SELECT__DVO_SOURCE_SELECT__SHIFT 0x00000000 6733de2bdb3dSTom St Denis #define DVO_SOURCE_SELECT__DVO_STEREOSYNC_SELECT_MASK 0x00070000L 6734de2bdb3dSTom St Denis #define DVO_SOURCE_SELECT__DVO_STEREOSYNC_SELECT__SHIFT 0x00000010 6735de2bdb3dSTom St Denis #define DVO_STRENGTH_CONTROL__DVOCLK_SN_MASK 0x0000f000L 6736de2bdb3dSTom St Denis #define DVO_STRENGTH_CONTROL__DVOCLK_SN__SHIFT 0x0000000c 6737de2bdb3dSTom St Denis #define DVO_STRENGTH_CONTROL__DVOCLK_SP_MASK 0x00000f00L 6738de2bdb3dSTom St Denis #define DVO_STRENGTH_CONTROL__DVOCLK_SP__SHIFT 0x00000008 6739de2bdb3dSTom St Denis #define DVO_STRENGTH_CONTROL__DVO_LSB_VMODE_MASK 0x10000000L 6740de2bdb3dSTom St Denis #define DVO_STRENGTH_CONTROL__DVO_LSB_VMODE__SHIFT 0x0000001c 6741de2bdb3dSTom St Denis #define DVO_STRENGTH_CONTROL__DVO_MSB_VMODE_MASK 0x20000000L 6742de2bdb3dSTom St Denis #define DVO_STRENGTH_CONTROL__DVO_MSB_VMODE__SHIFT 0x0000001d 6743de2bdb3dSTom St Denis #define DVO_STRENGTH_CONTROL__DVO_SN_MASK 0x000000f0L 6744de2bdb3dSTom St Denis #define DVO_STRENGTH_CONTROL__DVO_SN__SHIFT 0x00000004 6745de2bdb3dSTom St Denis #define DVO_STRENGTH_CONTROL__DVO_SP_MASK 0x0000000fL 6746de2bdb3dSTom St Denis #define DVO_STRENGTH_CONTROL__DVO_SP__SHIFT 0x00000000 6747de2bdb3dSTom St Denis #define DVO_VREF_CONTROL__DVO_VREFCAL_MASK 0x000000f0L 6748de2bdb3dSTom St Denis #define DVO_VREF_CONTROL__DVO_VREFCAL__SHIFT 0x00000004 6749de2bdb3dSTom St Denis #define DVO_VREF_CONTROL__DVO_VREFPON_MASK 0x00000001L 6750de2bdb3dSTom St Denis #define DVO_VREF_CONTROL__DVO_VREFPON__SHIFT 0x00000000 6751de2bdb3dSTom St Denis #define DVO_VREF_CONTROL__DVO_VREFSEL_MASK 0x00000002L 6752de2bdb3dSTom St Denis #define DVO_VREF_CONTROL__DVO_VREFSEL__SHIFT 0x00000001 6753de2bdb3dSTom St Denis #define EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT_MASK 0x0fff0000L 6754de2bdb3dSTom St Denis #define EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT__SHIFT 0x00000010 6755de2bdb3dSTom St Denis #define EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT_MASK 0x00000fffL 6756de2bdb3dSTom St Denis #define EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT__SHIFT 0x00000000 6757de2bdb3dSTom St Denis #define EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM_MASK 0x00000fffL 6758de2bdb3dSTom St Denis #define EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM__SHIFT 0x00000000 6759de2bdb3dSTom St Denis #define EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP_MASK 0x0fff0000L 6760de2bdb3dSTom St Denis #define EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP__SHIFT 0x00000010 6761de2bdb3dSTom St Denis #define FBC_CLIENT_REGION_MASK__FBC_MEMORY_REGION_MASK_MASK 0x000f0000L 6762de2bdb3dSTom St Denis #define FBC_CLIENT_REGION_MASK__FBC_MEMORY_REGION_MASK__SHIFT 0x00000010 6763de2bdb3dSTom St Denis #define FBC_CNTL__FBC_COHERENCY_MODE_MASK 0x00030000L 6764de2bdb3dSTom St Denis #define FBC_CNTL__FBC_COHERENCY_MODE__SHIFT 0x00000010 6765de2bdb3dSTom St Denis #define FBC_CNTL__FBC_EN_MASK 0x80000000L 6766de2bdb3dSTom St Denis #define FBC_CNTL__FBC_EN__SHIFT 0x0000001f 6767de2bdb3dSTom St Denis #define FBC_CNTL__FBC_GRPH_COMP_EN_MASK 0x00000001L 6768de2bdb3dSTom St Denis #define FBC_CNTL__FBC_GRPH_COMP_EN__SHIFT 0x00000000 6769de2bdb3dSTom St Denis #define FBC_CNTL__FBC_SOFT_COMPRESS_EN_MASK 0x02000000L 6770de2bdb3dSTom St Denis #define FBC_CNTL__FBC_SOFT_COMPRESS_EN__SHIFT 0x00000019 6771de2bdb3dSTom St Denis #define FBC_CNTL__FBC_SRC_SEL_MASK 0x0000000eL 6772de2bdb3dSTom St Denis #define FBC_CNTL__FBC_SRC_SEL__SHIFT 0x00000001 6773de2bdb3dSTom St Denis #define FBC_COMP_CNTL__FBC_DEPTH_MONO08_EN_MASK 0x00010000L 6774de2bdb3dSTom St Denis #define FBC_COMP_CNTL__FBC_DEPTH_MONO08_EN__SHIFT 0x00000010 6775de2bdb3dSTom St Denis #define FBC_COMP_CNTL__FBC_DEPTH_MONO16_EN_MASK 0x00020000L 6776de2bdb3dSTom St Denis #define FBC_COMP_CNTL__FBC_DEPTH_MONO16_EN__SHIFT 0x00000011 6777de2bdb3dSTom St Denis #define FBC_COMP_CNTL__FBC_DEPTH_RGB04_EN_MASK 0x00040000L 6778de2bdb3dSTom St Denis #define FBC_COMP_CNTL__FBC_DEPTH_RGB04_EN__SHIFT 0x00000012 6779de2bdb3dSTom St Denis #define FBC_COMP_CNTL__FBC_DEPTH_RGB08_EN_MASK 0x00080000L 6780de2bdb3dSTom St Denis #define FBC_COMP_CNTL__FBC_DEPTH_RGB08_EN__SHIFT 0x00000013 6781de2bdb3dSTom St Denis #define FBC_COMP_CNTL__FBC_DEPTH_RGB16_EN_MASK 0x00100000L 6782de2bdb3dSTom St Denis #define FBC_COMP_CNTL__FBC_DEPTH_RGB16_EN__SHIFT 0x00000014 6783de2bdb3dSTom St Denis #define FBC_COMP_CNTL__FBC_MIN_COMPRESSION_MASK 0x0000000fL 6784de2bdb3dSTom St Denis #define FBC_COMP_CNTL__FBC_MIN_COMPRESSION__SHIFT 0x00000000 6785de2bdb3dSTom St Denis #define FBC_COMP_MODE__FBC_DPCM4_RGB_EN_MASK 0x00000100L 6786de2bdb3dSTom St Denis #define FBC_COMP_MODE__FBC_DPCM4_RGB_EN__SHIFT 0x00000008 6787de2bdb3dSTom St Denis #define FBC_COMP_MODE__FBC_DPCM4_YUV_EN_MASK 0x00000400L 6788de2bdb3dSTom St Denis #define FBC_COMP_MODE__FBC_DPCM4_YUV_EN__SHIFT 0x0000000a 6789de2bdb3dSTom St Denis #define FBC_COMP_MODE__FBC_DPCM8_RGB_EN_MASK 0x00000200L 6790de2bdb3dSTom St Denis #define FBC_COMP_MODE__FBC_DPCM8_RGB_EN__SHIFT 0x00000009 6791de2bdb3dSTom St Denis #define FBC_COMP_MODE__FBC_DPCM8_YUV_EN_MASK 0x00000800L 6792de2bdb3dSTom St Denis #define FBC_COMP_MODE__FBC_DPCM8_YUV_EN__SHIFT 0x0000000b 6793de2bdb3dSTom St Denis #define FBC_COMP_MODE__FBC_IND_EN_MASK 0x00010000L 6794de2bdb3dSTom St Denis #define FBC_COMP_MODE__FBC_IND_EN__SHIFT 0x00000010 6795de2bdb3dSTom St Denis #define FBC_COMP_MODE__FBC_RLE_EN_MASK 0x00000001L 6796de2bdb3dSTom St Denis #define FBC_COMP_MODE__FBC_RLE_EN__SHIFT 0x00000000 6797de2bdb3dSTom St Denis #define FBC_CSM_REGION_OFFSET_01__FBC_CSM_REGION_OFFSET_0_MASK 0x000003ffL 6798de2bdb3dSTom St Denis #define FBC_CSM_REGION_OFFSET_01__FBC_CSM_REGION_OFFSET_0__SHIFT 0x00000000 6799de2bdb3dSTom St Denis #define FBC_CSM_REGION_OFFSET_01__FBC_CSM_REGION_OFFSET_1_MASK 0x03ff0000L 6800de2bdb3dSTom St Denis #define FBC_CSM_REGION_OFFSET_01__FBC_CSM_REGION_OFFSET_1__SHIFT 0x00000010 6801de2bdb3dSTom St Denis #define FBC_CSM_REGION_OFFSET_23__FBC_CSM_REGION_OFFSET_2_MASK 0x000003ffL 6802de2bdb3dSTom St Denis #define FBC_CSM_REGION_OFFSET_23__FBC_CSM_REGION_OFFSET_2__SHIFT 0x00000000 6803de2bdb3dSTom St Denis #define FBC_CSM_REGION_OFFSET_23__FBC_CSM_REGION_OFFSET_3_MASK 0x03ff0000L 6804de2bdb3dSTom St Denis #define FBC_CSM_REGION_OFFSET_23__FBC_CSM_REGION_OFFSET_3__SHIFT 0x00000010 6805de2bdb3dSTom St Denis #define FBC_DEBUG0__FBC_COMP_WAKE_DIS_MASK 0x00010000L 6806de2bdb3dSTom St Denis #define FBC_DEBUG0__FBC_COMP_WAKE_DIS__SHIFT 0x00000010 6807de2bdb3dSTom St Denis #define FBC_DEBUG0__FBC_DEBUG0_MASK 0x00fe0000L 6808de2bdb3dSTom St Denis #define FBC_DEBUG0__FBC_DEBUG0__SHIFT 0x00000011 6809de2bdb3dSTom St Denis #define FBC_DEBUG0__FBC_DEBUG_MUX_MASK 0xff000000L 6810de2bdb3dSTom St Denis #define FBC_DEBUG0__FBC_DEBUG_MUX__SHIFT 0x00000018 6811de2bdb3dSTom St Denis #define FBC_DEBUG0__FBC_PERF_MUX0_MASK 0x000000ffL 6812de2bdb3dSTom St Denis #define FBC_DEBUG0__FBC_PERF_MUX0__SHIFT 0x00000000 6813de2bdb3dSTom St Denis #define FBC_DEBUG0__FBC_PERF_MUX1_MASK 0x0000ff00L 6814de2bdb3dSTom St Denis #define FBC_DEBUG0__FBC_PERF_MUX1__SHIFT 0x00000008 6815de2bdb3dSTom St Denis #define FBC_DEBUG1__FBC_DEBUG1_MASK 0xffffffffL 6816de2bdb3dSTom St Denis #define FBC_DEBUG1__FBC_DEBUG1__SHIFT 0x00000000 6817de2bdb3dSTom St Denis #define FBC_DEBUG2__FBC_DEBUG2_MASK 0xffffffffL 6818de2bdb3dSTom St Denis #define FBC_DEBUG2__FBC_DEBUG2__SHIFT 0x00000000 6819de2bdb3dSTom St Denis #define FBC_DEBUG_COMP__FBC_COMP_ADDRESS_TRANSLATION_ENABLE_MASK 0x00000800L 6820de2bdb3dSTom St Denis #define FBC_DEBUG_COMP__FBC_COMP_ADDRESS_TRANSLATION_ENABLE__SHIFT 0x0000000b 6821de2bdb3dSTom St Denis #define FBC_DEBUG_COMP__FBC_COMP_BUSY_HYSTERESIS_MASK 0x000000f0L 6822de2bdb3dSTom St Denis #define FBC_DEBUG_COMP__FBC_COMP_BUSY_HYSTERESIS__SHIFT 0x00000004 6823de2bdb3dSTom St Denis #define FBC_DEBUG_COMP__FBC_COMP_CLK_CNTL_MASK 0x00000300L 6824de2bdb3dSTom St Denis #define FBC_DEBUG_COMP__FBC_COMP_CLK_CNTL__SHIFT 0x00000008 6825de2bdb3dSTom St Denis #define FBC_DEBUG_COMP__FBC_COMP_PRIVILEGED_ACCESS_ENABLE_MASK 0x00000400L 6826de2bdb3dSTom St Denis #define FBC_DEBUG_COMP__FBC_COMP_PRIVILEGED_ACCESS_ENABLE__SHIFT 0x0000000a 6827de2bdb3dSTom St Denis #define FBC_DEBUG_COMP__FBC_COMP_RSIZE_MASK 0x00000008L 6828de2bdb3dSTom St Denis #define FBC_DEBUG_COMP__FBC_COMP_RSIZE__SHIFT 0x00000003 6829de2bdb3dSTom St Denis #define FBC_DEBUG_COMP__FBC_COMP_SWAP_MASK 0x00000003L 6830de2bdb3dSTom St Denis #define FBC_DEBUG_COMP__FBC_COMP_SWAP__SHIFT 0x00000000 6831de2bdb3dSTom St Denis #define FBC_DEBUG_CSR__FBC_DEBUG_CSR_ADDR_MASK 0x000003ffL 6832de2bdb3dSTom St Denis #define FBC_DEBUG_CSR__FBC_DEBUG_CSR_ADDR__SHIFT 0x00000000 6833de2bdb3dSTom St Denis #define FBC_DEBUG_CSR__FBC_DEBUG_CSR_EN_MASK 0x80000000L 6834de2bdb3dSTom St Denis #define FBC_DEBUG_CSR__FBC_DEBUG_CSR_EN__SHIFT 0x0000001f 6835de2bdb3dSTom St Denis #define FBC_DEBUG_CSR__FBC_DEBUG_CSR_RD_DATA_MASK 0x00020000L 6836de2bdb3dSTom St Denis #define FBC_DEBUG_CSR__FBC_DEBUG_CSR_RD_DATA__SHIFT 0x00000011 6837de2bdb3dSTom St Denis #define FBC_DEBUG_CSR__FBC_DEBUG_CSR_WR_DATA_MASK 0x00010000L 6838de2bdb3dSTom St Denis #define FBC_DEBUG_CSR__FBC_DEBUG_CSR_WR_DATA__SHIFT 0x00000010 6839de2bdb3dSTom St Denis #define FBC_DEBUG_CSR_RDATA__FBC_DEBUG_CSR_RDATA_MASK 0xffffffffL 6840de2bdb3dSTom St Denis #define FBC_DEBUG_CSR_RDATA__FBC_DEBUG_CSR_RDATA__SHIFT 0x00000000 6841de2bdb3dSTom St Denis #define FBC_DEBUG_CSR_RDATA_HI__FBC_DEBUG_CSR_RDATA_HI_MASK 0x000000ffL 6842de2bdb3dSTom St Denis #define FBC_DEBUG_CSR_RDATA_HI__FBC_DEBUG_CSR_RDATA_HI__SHIFT 0x00000000 6843de2bdb3dSTom St Denis #define FBC_DEBUG_CSR_WDATA__FBC_DEBUG_CSR_WDATA_MASK 0xffffffffL 6844de2bdb3dSTom St Denis #define FBC_DEBUG_CSR_WDATA__FBC_DEBUG_CSR_WDATA__SHIFT 0x00000000 6845de2bdb3dSTom St Denis #define FBC_DEBUG_CSR_WDATA_HI__FBC_DEBUG_CSR_WDATA_HI_MASK 0x000000ffL 6846de2bdb3dSTom St Denis #define FBC_DEBUG_CSR_WDATA_HI__FBC_DEBUG_CSR_WDATA_HI__SHIFT 0x00000000 6847de2bdb3dSTom St Denis #define FBC_IDLE_FORCE_CLEAR_MASK__FBC_IDLE_FORCE_CLEAR_MASK_MASK 0xffffffffL 6848de2bdb3dSTom St Denis #define FBC_IDLE_FORCE_CLEAR_MASK__FBC_IDLE_FORCE_CLEAR_MASK__SHIFT 0x00000000 6849de2bdb3dSTom St Denis #define FBC_IDLE_MASK__FBC_IDLE_MASK_MASK 0xffffffffL 6850de2bdb3dSTom St Denis #define FBC_IDLE_MASK__FBC_IDLE_MASK__SHIFT 0x00000000 6851de2bdb3dSTom St Denis #define FBC_IND_LUT0__FBC_IND_LUT0_MASK 0x00ffffffL 6852de2bdb3dSTom St Denis #define FBC_IND_LUT0__FBC_IND_LUT0__SHIFT 0x00000000 6853de2bdb3dSTom St Denis #define FBC_IND_LUT10__FBC_IND_LUT10_MASK 0x00ffffffL 6854de2bdb3dSTom St Denis #define FBC_IND_LUT10__FBC_IND_LUT10__SHIFT 0x00000000 6855de2bdb3dSTom St Denis #define FBC_IND_LUT11__FBC_IND_LUT11_MASK 0x00ffffffL 6856de2bdb3dSTom St Denis #define FBC_IND_LUT11__FBC_IND_LUT11__SHIFT 0x00000000 6857de2bdb3dSTom St Denis #define FBC_IND_LUT12__FBC_IND_LUT12_MASK 0x00ffffffL 6858de2bdb3dSTom St Denis #define FBC_IND_LUT12__FBC_IND_LUT12__SHIFT 0x00000000 6859de2bdb3dSTom St Denis #define FBC_IND_LUT13__FBC_IND_LUT13_MASK 0x00ffffffL 6860de2bdb3dSTom St Denis #define FBC_IND_LUT13__FBC_IND_LUT13__SHIFT 0x00000000 6861de2bdb3dSTom St Denis #define FBC_IND_LUT14__FBC_IND_LUT14_MASK 0x00ffffffL 6862de2bdb3dSTom St Denis #define FBC_IND_LUT14__FBC_IND_LUT14__SHIFT 0x00000000 6863de2bdb3dSTom St Denis #define FBC_IND_LUT15__FBC_IND_LUT15_MASK 0x00ffffffL 6864de2bdb3dSTom St Denis #define FBC_IND_LUT15__FBC_IND_LUT15__SHIFT 0x00000000 6865de2bdb3dSTom St Denis #define FBC_IND_LUT1__FBC_IND_LUT1_MASK 0x00ffffffL 6866de2bdb3dSTom St Denis #define FBC_IND_LUT1__FBC_IND_LUT1__SHIFT 0x00000000 6867de2bdb3dSTom St Denis #define FBC_IND_LUT2__FBC_IND_LUT2_MASK 0x00ffffffL 6868de2bdb3dSTom St Denis #define FBC_IND_LUT2__FBC_IND_LUT2__SHIFT 0x00000000 6869de2bdb3dSTom St Denis #define FBC_IND_LUT3__FBC_IND_LUT3_MASK 0x00ffffffL 6870de2bdb3dSTom St Denis #define FBC_IND_LUT3__FBC_IND_LUT3__SHIFT 0x00000000 6871de2bdb3dSTom St Denis #define FBC_IND_LUT4__FBC_IND_LUT4_MASK 0x00ffffffL 6872de2bdb3dSTom St Denis #define FBC_IND_LUT4__FBC_IND_LUT4__SHIFT 0x00000000 6873de2bdb3dSTom St Denis #define FBC_IND_LUT5__FBC_IND_LUT5_MASK 0x00ffffffL 6874de2bdb3dSTom St Denis #define FBC_IND_LUT5__FBC_IND_LUT5__SHIFT 0x00000000 6875de2bdb3dSTom St Denis #define FBC_IND_LUT6__FBC_IND_LUT6_MASK 0x00ffffffL 6876de2bdb3dSTom St Denis #define FBC_IND_LUT6__FBC_IND_LUT6__SHIFT 0x00000000 6877de2bdb3dSTom St Denis #define FBC_IND_LUT7__FBC_IND_LUT7_MASK 0x00ffffffL 6878de2bdb3dSTom St Denis #define FBC_IND_LUT7__FBC_IND_LUT7__SHIFT 0x00000000 6879de2bdb3dSTom St Denis #define FBC_IND_LUT8__FBC_IND_LUT8_MASK 0x00ffffffL 6880de2bdb3dSTom St Denis #define FBC_IND_LUT8__FBC_IND_LUT8__SHIFT 0x00000000 6881de2bdb3dSTom St Denis #define FBC_IND_LUT9__FBC_IND_LUT9_MASK 0x00ffffffL 6882de2bdb3dSTom St Denis #define FBC_IND_LUT9__FBC_IND_LUT9__SHIFT 0x00000000 6883de2bdb3dSTom St Denis #define FBC_MISC__FBC_DECOMPRESS_ERROR_CLEAR_MASK 0x00010000L 6884de2bdb3dSTom St Denis #define FBC_MISC__FBC_DECOMPRESS_ERROR_CLEAR__SHIFT 0x00000010 6885de2bdb3dSTom St Denis #define FBC_MISC__FBC_DECOMPRESS_ERROR_MASK 0x00000003L 6886de2bdb3dSTom St Denis #define FBC_MISC__FBC_DECOMPRESS_ERROR__SHIFT 0x00000000 6887de2bdb3dSTom St Denis #define FBC_MISC__FBC_DIVIDE_X_MASK 0x00000300L 6888de2bdb3dSTom St Denis #define FBC_MISC__FBC_DIVIDE_X__SHIFT 0x00000008 6889de2bdb3dSTom St Denis #define FBC_MISC__FBC_DIVIDE_Y_MASK 0x00000400L 6890de2bdb3dSTom St Denis #define FBC_MISC__FBC_DIVIDE_Y__SHIFT 0x0000000a 6891de2bdb3dSTom St Denis #define FBC_MISC__FBC_ERROR_PIXEL_MASK 0x000000f0L 6892de2bdb3dSTom St Denis #define FBC_MISC__FBC_ERROR_PIXEL__SHIFT 0x00000004 6893de2bdb3dSTom St Denis #define FBC_MISC__FBC_INVALIDATE_ON_ERROR_MASK 0x00000008L 6894de2bdb3dSTom St Denis #define FBC_MISC__FBC_INVALIDATE_ON_ERROR__SHIFT 0x00000003 6895de2bdb3dSTom St Denis #define FBC_MISC__FBC_RESET_AT_DISABLE_MASK 0x00200000L 6896de2bdb3dSTom St Denis #define FBC_MISC__FBC_RESET_AT_DISABLE__SHIFT 0x00000015 6897de2bdb3dSTom St Denis #define FBC_MISC__FBC_RESET_AT_ENABLE_MASK 0x00100000L 6898de2bdb3dSTom St Denis #define FBC_MISC__FBC_RESET_AT_ENABLE__SHIFT 0x00000014 6899de2bdb3dSTom St Denis #define FBC_MISC__FBC_RSM_UNCOMP_DATA_IMMEDIATELY_MASK 0x00001000L 6900de2bdb3dSTom St Denis #define FBC_MISC__FBC_RSM_UNCOMP_DATA_IMMEDIATELY__SHIFT 0x0000000c 6901de2bdb3dSTom St Denis #define FBC_MISC__FBC_RSM_WRITE_VALUE_MASK 0x00000800L 6902de2bdb3dSTom St Denis #define FBC_MISC__FBC_RSM_WRITE_VALUE__SHIFT 0x0000000b 6903de2bdb3dSTom St Denis #define FBC_MISC__FBC_SLOW_REQ_INTERVAL_MASK 0xf0000000L 6904de2bdb3dSTom St Denis #define FBC_MISC__FBC_SLOW_REQ_INTERVAL__SHIFT 0x0000001c 6905de2bdb3dSTom St Denis #define FBC_MISC__FBC_STOP_ON_ERROR_MASK 0x00000004L 6906de2bdb3dSTom St Denis #define FBC_MISC__FBC_STOP_ON_ERROR__SHIFT 0x00000002 6907de2bdb3dSTom St Denis #define FBC_START_STOP_DELAY__FBC_COMP_START_DELAY_MASK 0x00001f00L 6908de2bdb3dSTom St Denis #define FBC_START_STOP_DELAY__FBC_COMP_START_DELAY__SHIFT 0x00000008 6909de2bdb3dSTom St Denis #define FBC_START_STOP_DELAY__FBC_DECOMP_START_DELAY_MASK 0x0000001fL 6910de2bdb3dSTom St Denis #define FBC_START_STOP_DELAY__FBC_DECOMP_START_DELAY__SHIFT 0x00000000 6911de2bdb3dSTom St Denis #define FBC_START_STOP_DELAY__FBC_DECOMP_STOP_DELAY_MASK 0x00000080L 6912de2bdb3dSTom St Denis #define FBC_START_STOP_DELAY__FBC_DECOMP_STOP_DELAY__SHIFT 0x00000007 6913de2bdb3dSTom St Denis #define FBC_STATUS__FBC_ENABLE_STATUS_MASK 0x00000001L 6914de2bdb3dSTom St Denis #define FBC_STATUS__FBC_ENABLE_STATUS__SHIFT 0x00000000 6915de2bdb3dSTom St Denis #define FBC_TEST_DEBUG_DATA__FBC_TEST_DEBUG_DATA_MASK 0xffffffffL 6916de2bdb3dSTom St Denis #define FBC_TEST_DEBUG_DATA__FBC_TEST_DEBUG_DATA__SHIFT 0x00000000 6917de2bdb3dSTom St Denis #define FBC_TEST_DEBUG_INDEX__FBC_TEST_DEBUG_INDEX_MASK 0x000000ffL 6918de2bdb3dSTom St Denis #define FBC_TEST_DEBUG_INDEX__FBC_TEST_DEBUG_INDEX__SHIFT 0x00000000 6919de2bdb3dSTom St Denis #define FBC_TEST_DEBUG_INDEX__FBC_TEST_DEBUG_WRITE_EN_MASK 0x00000100L 6920de2bdb3dSTom St Denis #define FBC_TEST_DEBUG_INDEX__FBC_TEST_DEBUG_WRITE_EN__SHIFT 0x00000008 6921de2bdb3dSTom St Denis #define FMT_BIT_DEPTH_CONTROL__FMT_25FRC_SEL_MASK 0x0c000000L 6922de2bdb3dSTom St Denis #define FMT_BIT_DEPTH_CONTROL__FMT_25FRC_SEL__SHIFT 0x0000001a 6923de2bdb3dSTom St Denis #define FMT_BIT_DEPTH_CONTROL__FMT_50FRC_SEL_MASK 0x30000000L 6924de2bdb3dSTom St Denis #define FMT_BIT_DEPTH_CONTROL__FMT_50FRC_SEL__SHIFT 0x0000001c 6925de2bdb3dSTom St Denis #define FMT_BIT_DEPTH_CONTROL__FMT_75FRC_SEL_MASK 0xc0000000L 6926de2bdb3dSTom St Denis #define FMT_BIT_DEPTH_CONTROL__FMT_75FRC_SEL__SHIFT 0x0000001e 6927de2bdb3dSTom St Denis #define FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE_MASK 0x00002000L 6928de2bdb3dSTom St Denis #define FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE__SHIFT 0x0000000d 6929de2bdb3dSTom St Denis #define FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE_MASK 0x00008000L 6930de2bdb3dSTom St Denis #define FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE__SHIFT 0x0000000f 6931de2bdb3dSTom St Denis #define FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE_MASK 0x00004000L 6932de2bdb3dSTom St Denis #define FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE__SHIFT 0x0000000e 6933de2bdb3dSTom St Denis #define FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH_MASK 0x00001000L 6934de2bdb3dSTom St Denis #define FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH__SHIFT 0x0000000c 6935de2bdb3dSTom St Denis #define FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN_MASK 0x00000100L 6936de2bdb3dSTom St Denis #define FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN__SHIFT 0x00000008 6937de2bdb3dSTom St Denis #define FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_MODE_MASK 0x00000600L 6938de2bdb3dSTom St Denis #define FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_MODE__SHIFT 0x00000009 6939de2bdb3dSTom St Denis #define FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_DEPTH_MASK 0x00100000L 6940de2bdb3dSTom St Denis #define FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_DEPTH__SHIFT 0x00000014 6941de2bdb3dSTom St Denis #define FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_EN_MASK 0x00010000L 6942de2bdb3dSTom St Denis #define FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_EN__SHIFT 0x00000010 6943de2bdb3dSTom St Denis #define FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_OFFSET_MASK 0x00600000L 6944de2bdb3dSTom St Denis #define FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_OFFSET__SHIFT 0x00000015 6945de2bdb3dSTom St Denis #define FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_RESET_MASK 0x02000000L 6946de2bdb3dSTom St Denis #define FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_RESET__SHIFT 0x00000019 6947de2bdb3dSTom St Denis #define FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_LEVEL_MASK 0x01000000L 6948de2bdb3dSTom St Denis #define FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_LEVEL__SHIFT 0x00000018 6949de2bdb3dSTom St Denis #define FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH_MASK 0x00000010L 6950de2bdb3dSTom St Denis #define FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH__SHIFT 0x00000004 6951de2bdb3dSTom St Denis #define FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN_MASK 0x00000001L 6952de2bdb3dSTom St Denis #define FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN__SHIFT 0x00000000 6953de2bdb3dSTom St Denis #define FMT_CLAMP_CNTL__FMT_CLAMP_COLOR_FORMAT_MASK 0x00070000L 6954de2bdb3dSTom St Denis #define FMT_CLAMP_CNTL__FMT_CLAMP_COLOR_FORMAT__SHIFT 0x00000010 6955de2bdb3dSTom St Denis #define FMT_CLAMP_CNTL__FMT_CLAMP_DATA_EN_MASK 0x00000001L 6956de2bdb3dSTom St Denis #define FMT_CLAMP_CNTL__FMT_CLAMP_DATA_EN__SHIFT 0x00000000 6957de2bdb3dSTom St Denis #define FMT_CONTROL__FMT_PIXEL_ENCODING_MASK 0x00010000L 6958de2bdb3dSTom St Denis #define FMT_CONTROL__FMT_PIXEL_ENCODING__SHIFT 0x00000010 6959de2bdb3dSTom St Denis #define FMT_CONTROL__FMT_STEREOSYNC_OVERRIDE_MASK 0x00000001L 6960de2bdb3dSTom St Denis #define FMT_CONTROL__FMT_STEREOSYNC_OVERRIDE__SHIFT 0x00000000 6961de2bdb3dSTom St Denis #define FMT_CONTROL__FMT_STEREOSYNC_OVR_POL_MASK 0x00000010L 6962de2bdb3dSTom St Denis #define FMT_CONTROL__FMT_STEREOSYNC_OVR_POL__SHIFT 0x00000004 6963de2bdb3dSTom St Denis #define FMT_CRC_CNTL__FMT_CRC_CONT_EN_MASK 0x00000010L 6964de2bdb3dSTom St Denis #define FMT_CRC_CNTL__FMT_CRC_CONT_EN__SHIFT 0x00000004 6965de2bdb3dSTom St Denis #define FMT_CRC_CNTL__FMT_CRC_EN_MASK 0x00000001L 6966de2bdb3dSTom St Denis #define FMT_CRC_CNTL__FMT_CRC_EN__SHIFT 0x00000000 6967de2bdb3dSTom St Denis #define FMT_CRC_CNTL__FMT_CRC_EVEN_ODD_PIX_ENABLE_MASK 0x00100000L 6968de2bdb3dSTom St Denis #define FMT_CRC_CNTL__FMT_CRC_EVEN_ODD_PIX_ENABLE__SHIFT 0x00000014 6969de2bdb3dSTom St Denis #define FMT_CRC_CNTL__FMT_CRC_EVEN_ODD_PIX_SELECT_MASK 0x01000000L 6970de2bdb3dSTom St Denis #define FMT_CRC_CNTL__FMT_CRC_EVEN_ODD_PIX_SELECT__SHIFT 0x00000018 6971de2bdb3dSTom St Denis #define FMT_CRC_CNTL__FMT_CRC_INTERLACE_MODE_MASK 0x00003000L 6972de2bdb3dSTom St Denis #define FMT_CRC_CNTL__FMT_CRC_INTERLACE_MODE__SHIFT 0x0000000c 6973de2bdb3dSTom St Denis #define FMT_CRC_CNTL__FMT_CRC_ONLY_BLANKb_MASK 0x00000100L 6974de2bdb3dSTom St Denis #define FMT_CRC_CNTL__FMT_CRC_ONLY_BLANKb__SHIFT 0x00000008 6975de2bdb3dSTom St Denis #define FMT_CRC_CNTL__FMT_CRC_USE_NEW_AND_REPEATED_PIXELS_MASK 0x00010000L 6976de2bdb3dSTom St Denis #define FMT_CRC_CNTL__FMT_CRC_USE_NEW_AND_REPEATED_PIXELS__SHIFT 0x00000010 6977de2bdb3dSTom St Denis #define FMT_CRC_SIG_BLUE_CONTROL__FMT_CRC_SIG_BLUE_MASK 0x0000ffffL 6978de2bdb3dSTom St Denis #define FMT_CRC_SIG_BLUE_CONTROL__FMT_CRC_SIG_BLUE__SHIFT 0x00000000 6979de2bdb3dSTom St Denis #define FMT_CRC_SIG_BLUE_CONTROL__FMT_CRC_SIG_CONTROL_MASK 0xffff0000L 6980de2bdb3dSTom St Denis #define FMT_CRC_SIG_BLUE_CONTROL__FMT_CRC_SIG_CONTROL__SHIFT 0x00000010 6981de2bdb3dSTom St Denis #define FMT_CRC_SIG_BLUE_CONTROL_MASK__FMT_CRC_SIG_BLUE_MASK_MASK 0x0000ffffL 6982de2bdb3dSTom St Denis #define FMT_CRC_SIG_BLUE_CONTROL_MASK__FMT_CRC_SIG_BLUE_MASK__SHIFT 0x00000000 6983de2bdb3dSTom St Denis #define FMT_CRC_SIG_BLUE_CONTROL_MASK__FMT_CRC_SIG_CONTROL_MASK_MASK 0xffff0000L 6984de2bdb3dSTom St Denis #define FMT_CRC_SIG_BLUE_CONTROL_MASK__FMT_CRC_SIG_CONTROL_MASK__SHIFT 0x00000010 6985de2bdb3dSTom St Denis #define FMT_CRC_SIG_RED_GREEN__FMT_CRC_SIG_GREEN_MASK 0xffff0000L 6986de2bdb3dSTom St Denis #define FMT_CRC_SIG_RED_GREEN__FMT_CRC_SIG_GREEN__SHIFT 0x00000010 6987de2bdb3dSTom St Denis #define FMT_CRC_SIG_RED_GREEN__FMT_CRC_SIG_RED_MASK 0x0000ffffL 6988de2bdb3dSTom St Denis #define FMT_CRC_SIG_RED_GREEN__FMT_CRC_SIG_RED__SHIFT 0x00000000 6989de2bdb3dSTom St Denis #define FMT_CRC_SIG_RED_GREEN_MASK__FMT_CRC_SIG_GREEN_MASK_MASK 0xffff0000L 6990de2bdb3dSTom St Denis #define FMT_CRC_SIG_RED_GREEN_MASK__FMT_CRC_SIG_GREEN_MASK__SHIFT 0x00000010 6991de2bdb3dSTom St Denis #define FMT_CRC_SIG_RED_GREEN_MASK__FMT_CRC_SIG_RED_MASK_MASK 0x0000ffffL 6992de2bdb3dSTom St Denis #define FMT_CRC_SIG_RED_GREEN_MASK__FMT_CRC_SIG_RED_MASK__SHIFT 0x00000000 6993de2bdb3dSTom St Denis #define FMT_DEBUG0__FMT_DEBUG0_MASK 0xffffffffL 6994de2bdb3dSTom St Denis #define FMT_DEBUG0__FMT_DEBUG0__SHIFT 0x00000000 6995de2bdb3dSTom St Denis #define FMT_DEBUG1__FMT_DEBUG1_MASK 0xffffffffL 6996de2bdb3dSTom St Denis #define FMT_DEBUG1__FMT_DEBUG1__SHIFT 0x00000000 6997de2bdb3dSTom St Denis #define FMT_DEBUG2__FMT_DEBUG2_MASK 0xffffffffL 6998de2bdb3dSTom St Denis #define FMT_DEBUG2__FMT_DEBUG2__SHIFT 0x00000000 6999de2bdb3dSTom St Denis #define FMT_DEBUG_CNTL__FMT_DEBUG_COLOR_SELECT_MASK 0x00000003L 7000de2bdb3dSTom St Denis #define FMT_DEBUG_CNTL__FMT_DEBUG_COLOR_SELECT__SHIFT 0x00000000 7001de2bdb3dSTom St Denis #define FMT_DEBUG_ID__FMT_DEBUG_ID_MASK 0xffffffffL 7002de2bdb3dSTom St Denis #define FMT_DEBUG_ID__FMT_DEBUG_ID__SHIFT 0x00000000 7003de2bdb3dSTom St Denis #define FMT_DITHER_RAND_B_SEED__FMT_RAND_B_SEED_MASK 0x000000ffL 7004de2bdb3dSTom St Denis #define FMT_DITHER_RAND_B_SEED__FMT_RAND_B_SEED__SHIFT 0x00000000 7005de2bdb3dSTom St Denis #define FMT_DITHER_RAND_G_SEED__FMT_RAND_G_SEED_MASK 0x000000ffL 7006de2bdb3dSTom St Denis #define FMT_DITHER_RAND_G_SEED__FMT_RAND_G_SEED__SHIFT 0x00000000 7007de2bdb3dSTom St Denis #define FMT_DITHER_RAND_R_SEED__FMT_RAND_R_SEED_MASK 0x000000ffL 7008de2bdb3dSTom St Denis #define FMT_DITHER_RAND_R_SEED__FMT_RAND_R_SEED__SHIFT 0x00000000 7009de2bdb3dSTom St Denis #define FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_EN_MASK 0x00000001L 7010de2bdb3dSTom St Denis #define FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_EN__SHIFT 0x00000000 7011de2bdb3dSTom St Denis #define FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_MODE_MASK 0x00000010L 7012de2bdb3dSTom St Denis #define FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_MODE__SHIFT 0x00000004 7013de2bdb3dSTom St Denis #define FMT_FORCE_DATA_0_1__FMT_FORCE_DATA0_MASK 0x0000ffffL 7014de2bdb3dSTom St Denis #define FMT_FORCE_DATA_0_1__FMT_FORCE_DATA0__SHIFT 0x00000000 7015de2bdb3dSTom St Denis #define FMT_FORCE_DATA_0_1__FMT_FORCE_DATA1_MASK 0xffff0000L 7016de2bdb3dSTom St Denis #define FMT_FORCE_DATA_0_1__FMT_FORCE_DATA1__SHIFT 0x00000010 7017de2bdb3dSTom St Denis #define FMT_FORCE_DATA_2_3__FMT_FORCE_DATA2_MASK 0x0000ffffL 7018de2bdb3dSTom St Denis #define FMT_FORCE_DATA_2_3__FMT_FORCE_DATA2__SHIFT 0x00000000 7019de2bdb3dSTom St Denis #define FMT_FORCE_DATA_2_3__FMT_FORCE_DATA3_MASK 0xffff0000L 7020de2bdb3dSTom St Denis #define FMT_FORCE_DATA_2_3__FMT_FORCE_DATA3__SHIFT 0x00000010 7021de2bdb3dSTom St Denis #define FMT_FORCE_OUTPUT_CNTL__FMT_FORCE_DATA_EN_MASK 0x00000001L 7022de2bdb3dSTom St Denis #define FMT_FORCE_OUTPUT_CNTL__FMT_FORCE_DATA_EN__SHIFT 0x00000000 7023de2bdb3dSTom St Denis #define FMT_FORCE_OUTPUT_CNTL__FMT_FORCE_DATA_ON_BLANKb_ONLY_MASK 0x00010000L 7024de2bdb3dSTom St Denis #define FMT_FORCE_OUTPUT_CNTL__FMT_FORCE_DATA_ON_BLANKb_ONLY__SHIFT 0x00000010 7025de2bdb3dSTom St Denis #define FMT_FORCE_OUTPUT_CNTL__FMT_FORCE_DATA_SEL_COLOR_MASK 0x00000700L 7026de2bdb3dSTom St Denis #define FMT_FORCE_OUTPUT_CNTL__FMT_FORCE_DATA_SEL_COLOR__SHIFT 0x00000008 7027de2bdb3dSTom St Denis #define FMT_FORCE_OUTPUT_CNTL__FMT_FORCE_DATA_SEL_SLOT_MASK 0x0000f000L 7028de2bdb3dSTom St Denis #define FMT_FORCE_OUTPUT_CNTL__FMT_FORCE_DATA_SEL_SLOT__SHIFT 0x0000000c 7029de2bdb3dSTom St Denis #define FMT_TEMPORAL_DITHER_PATTERN_CONTROL__FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_RGB1_BGR0_MASK 0x00000010L 7030de2bdb3dSTom St Denis #define FMT_TEMPORAL_DITHER_PATTERN_CONTROL__FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_RGB1_BGR0__SHIFT 0x00000004 7031de2bdb3dSTom St Denis #define FMT_TEMPORAL_DITHER_PATTERN_CONTROL__FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_SELECT_MASK 0x00000001L 7032de2bdb3dSTom St Denis #define FMT_TEMPORAL_DITHER_PATTERN_CONTROL__FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_SELECT__SHIFT 0x00000000 7033de2bdb3dSTom St Denis #define FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX__FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX_MASK 0xffffffffL 7034de2bdb3dSTom St Denis #define FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX__FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX__SHIFT 0x00000000 7035de2bdb3dSTom St Denis #define FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX__FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX_MASK 0xffffffffL 7036de2bdb3dSTom St Denis #define FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX__FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX__SHIFT 0x00000000 7037de2bdb3dSTom St Denis #define FMT_TEST_DEBUG_DATA__FMT_TEST_DEBUG_DATA_MASK 0xffffffffL 7038de2bdb3dSTom St Denis #define FMT_TEST_DEBUG_DATA__FMT_TEST_DEBUG_DATA__SHIFT 0x00000000 7039de2bdb3dSTom St Denis #define FMT_TEST_DEBUG_INDEX__FMT_TEST_DEBUG_INDEX_MASK 0x000000ffL 7040de2bdb3dSTom St Denis #define FMT_TEST_DEBUG_INDEX__FMT_TEST_DEBUG_INDEX__SHIFT 0x00000000 7041de2bdb3dSTom St Denis #define FMT_TEST_DEBUG_INDEX__FMT_TEST_DEBUG_WRITE_EN_MASK 0x00000100L 7042de2bdb3dSTom St Denis #define FMT_TEST_DEBUG_INDEX__FMT_TEST_DEBUG_WRITE_EN__SHIFT 0x00000008 7043de2bdb3dSTom St Denis #define GAMUT_REMAP_C11_C12__GAMUT_REMAP_C11_MASK 0x0000ffffL 7044de2bdb3dSTom St Denis #define GAMUT_REMAP_C11_C12__GAMUT_REMAP_C11__SHIFT 0x00000000 7045de2bdb3dSTom St Denis #define GAMUT_REMAP_C11_C12__GAMUT_REMAP_C12_MASK 0xffff0000L 7046de2bdb3dSTom St Denis #define GAMUT_REMAP_C11_C12__GAMUT_REMAP_C12__SHIFT 0x00000010 7047de2bdb3dSTom St Denis #define GAMUT_REMAP_C13_C14__GAMUT_REMAP_C13_MASK 0x0000ffffL 7048de2bdb3dSTom St Denis #define GAMUT_REMAP_C13_C14__GAMUT_REMAP_C13__SHIFT 0x00000000 7049de2bdb3dSTom St Denis #define GAMUT_REMAP_C13_C14__GAMUT_REMAP_C14_MASK 0xffff0000L 7050de2bdb3dSTom St Denis #define GAMUT_REMAP_C13_C14__GAMUT_REMAP_C14__SHIFT 0x00000010 7051de2bdb3dSTom St Denis #define GAMUT_REMAP_C21_C22__GAMUT_REMAP_C21_MASK 0x0000ffffL 7052de2bdb3dSTom St Denis #define GAMUT_REMAP_C21_C22__GAMUT_REMAP_C21__SHIFT 0x00000000 7053de2bdb3dSTom St Denis #define GAMUT_REMAP_C21_C22__GAMUT_REMAP_C22_MASK 0xffff0000L 7054de2bdb3dSTom St Denis #define GAMUT_REMAP_C21_C22__GAMUT_REMAP_C22__SHIFT 0x00000010 7055de2bdb3dSTom St Denis #define GAMUT_REMAP_C23_C24__GAMUT_REMAP_C23_MASK 0x0000ffffL 7056de2bdb3dSTom St Denis #define GAMUT_REMAP_C23_C24__GAMUT_REMAP_C23__SHIFT 0x00000000 7057de2bdb3dSTom St Denis #define GAMUT_REMAP_C23_C24__GAMUT_REMAP_C24_MASK 0xffff0000L 7058de2bdb3dSTom St Denis #define GAMUT_REMAP_C23_C24__GAMUT_REMAP_C24__SHIFT 0x00000010 7059de2bdb3dSTom St Denis #define GAMUT_REMAP_C31_C32__GAMUT_REMAP_C31_MASK 0x0000ffffL 7060de2bdb3dSTom St Denis #define GAMUT_REMAP_C31_C32__GAMUT_REMAP_C31__SHIFT 0x00000000 7061de2bdb3dSTom St Denis #define GAMUT_REMAP_C31_C32__GAMUT_REMAP_C32_MASK 0xffff0000L 7062de2bdb3dSTom St Denis #define GAMUT_REMAP_C31_C32__GAMUT_REMAP_C32__SHIFT 0x00000010 7063de2bdb3dSTom St Denis #define GAMUT_REMAP_C33_C34__GAMUT_REMAP_C33_MASK 0x0000ffffL 7064de2bdb3dSTom St Denis #define GAMUT_REMAP_C33_C34__GAMUT_REMAP_C33__SHIFT 0x00000000 7065de2bdb3dSTom St Denis #define GAMUT_REMAP_C33_C34__GAMUT_REMAP_C34_MASK 0xffff0000L 7066de2bdb3dSTom St Denis #define GAMUT_REMAP_C33_C34__GAMUT_REMAP_C34__SHIFT 0x00000010 7067de2bdb3dSTom St Denis #define GAMUT_REMAP_CONTROL__GRPH_GAMUT_REMAP_MODE_MASK 0x00000003L 7068de2bdb3dSTom St Denis #define GAMUT_REMAP_CONTROL__GRPH_GAMUT_REMAP_MODE__SHIFT 0x00000000 7069de2bdb3dSTom St Denis #define GAMUT_REMAP_CONTROL__OVL_GAMUT_REMAP_MODE_MASK 0x00000030L 7070de2bdb3dSTom St Denis #define GAMUT_REMAP_CONTROL__OVL_GAMUT_REMAP_MODE__SHIFT 0x00000004 7071de2bdb3dSTom St Denis #define GENENB__BLK_IO_BASE_MASK 0x000000ffL 7072de2bdb3dSTom St Denis #define GENENB__BLK_IO_BASE__SHIFT 0x00000000 7073de2bdb3dSTom St Denis #define GENERIC_I2C_CONTROL__GENERIC_I2C_DBG_REF_SEL_MASK 0x80000000L 7074de2bdb3dSTom St Denis #define GENERIC_I2C_CONTROL__GENERIC_I2C_DBG_REF_SEL__SHIFT 0x0000001f 7075de2bdb3dSTom St Denis #define GENERIC_I2C_CONTROL__GENERIC_I2C_ENABLE_MASK 0x00000008L 7076de2bdb3dSTom St Denis #define GENERIC_I2C_CONTROL__GENERIC_I2C_ENABLE__SHIFT 0x00000003 7077de2bdb3dSTom St Denis #define GENERIC_I2C_CONTROL__GENERIC_I2C_GO_MASK 0x00000001L 7078de2bdb3dSTom St Denis #define GENERIC_I2C_CONTROL__GENERIC_I2C_GO__SHIFT 0x00000000 7079de2bdb3dSTom St Denis #define GENERIC_I2C_CONTROL__GENERIC_I2C_SEND_RESET_MASK 0x00000004L 7080de2bdb3dSTom St Denis #define GENERIC_I2C_CONTROL__GENERIC_I2C_SEND_RESET__SHIFT 0x00000002 7081de2bdb3dSTom St Denis #define GENERIC_I2C_CONTROL__GENERIC_I2C_SOFT_RESET_MASK 0x00000002L 7082de2bdb3dSTom St Denis #define GENERIC_I2C_CONTROL__GENERIC_I2C_SOFT_RESET__SHIFT 0x00000001 7083de2bdb3dSTom St Denis #define GENERIC_I2C_DATA__GENERIC_I2C_DATA_MASK 0x0000ff00L 7084de2bdb3dSTom St Denis #define GENERIC_I2C_DATA__GENERIC_I2C_DATA_RW_MASK 0x00000001L 7085de2bdb3dSTom St Denis #define GENERIC_I2C_DATA__GENERIC_I2C_DATA_RW__SHIFT 0x00000000 7086de2bdb3dSTom St Denis #define GENERIC_I2C_DATA__GENERIC_I2C_DATA__SHIFT 0x00000008 7087de2bdb3dSTom St Denis #define GENERIC_I2C_DATA__GENERIC_I2C_INDEX_MASK 0x000f0000L 7088de2bdb3dSTom St Denis #define GENERIC_I2C_DATA__GENERIC_I2C_INDEX__SHIFT 0x00000010 7089de2bdb3dSTom St Denis #define GENERIC_I2C_DATA__GENERIC_I2C_INDEX_WRITE_MASK 0x80000000L 7090de2bdb3dSTom St Denis #define GENERIC_I2C_DATA__GENERIC_I2C_INDEX_WRITE__SHIFT 0x0000001f 7091de2bdb3dSTom St Denis #define GENERIC_I2C_INTERRUPT_CONTROL__GENERIC_I2C_DONE_ACK_MASK 0x00000002L 7092de2bdb3dSTom St Denis #define GENERIC_I2C_INTERRUPT_CONTROL__GENERIC_I2C_DONE_ACK__SHIFT 0x00000001 7093de2bdb3dSTom St Denis #define GENERIC_I2C_INTERRUPT_CONTROL__GENERIC_I2C_DONE_INT_MASK 0x00000001L 7094de2bdb3dSTom St Denis #define GENERIC_I2C_INTERRUPT_CONTROL__GENERIC_I2C_DONE_INT__SHIFT 0x00000000 7095de2bdb3dSTom St Denis #define GENERIC_I2C_INTERRUPT_CONTROL__GENERIC_I2C_DONE_MASK_MASK 0x00000004L 7096de2bdb3dSTom St Denis #define GENERIC_I2C_INTERRUPT_CONTROL__GENERIC_I2C_DONE_MASK__SHIFT 0x00000002 7097de2bdb3dSTom St Denis #define GENERIC_I2C_PIN_DEBUG__GENERIC_I2C_SCL_EN_MASK 0x00000004L 7098de2bdb3dSTom St Denis #define GENERIC_I2C_PIN_DEBUG__GENERIC_I2C_SCL_EN__SHIFT 0x00000002 7099de2bdb3dSTom St Denis #define GENERIC_I2C_PIN_DEBUG__GENERIC_I2C_SCL_INPUT_MASK 0x00000002L 7100de2bdb3dSTom St Denis #define GENERIC_I2C_PIN_DEBUG__GENERIC_I2C_SCL_INPUT__SHIFT 0x00000001 7101de2bdb3dSTom St Denis #define GENERIC_I2C_PIN_DEBUG__GENERIC_I2C_SCL_OUTPUT_MASK 0x00000001L 7102de2bdb3dSTom St Denis #define GENERIC_I2C_PIN_DEBUG__GENERIC_I2C_SCL_OUTPUT__SHIFT 0x00000000 7103de2bdb3dSTom St Denis #define GENERIC_I2C_PIN_DEBUG__GENERIC_I2C_SDA_EN_MASK 0x00000040L 7104de2bdb3dSTom St Denis #define GENERIC_I2C_PIN_DEBUG__GENERIC_I2C_SDA_EN__SHIFT 0x00000006 7105de2bdb3dSTom St Denis #define GENERIC_I2C_PIN_DEBUG__GENERIC_I2C_SDA_INPUT_MASK 0x00000020L 7106de2bdb3dSTom St Denis #define GENERIC_I2C_PIN_DEBUG__GENERIC_I2C_SDA_INPUT__SHIFT 0x00000005 7107de2bdb3dSTom St Denis #define GENERIC_I2C_PIN_DEBUG__GENERIC_I2C_SDA_OUTPUT_MASK 0x00000010L 7108de2bdb3dSTom St Denis #define GENERIC_I2C_PIN_DEBUG__GENERIC_I2C_SDA_OUTPUT__SHIFT 0x00000004 7109de2bdb3dSTom St Denis #define GENERIC_I2C_PIN_SELECTION__GENERIC_I2C_SCL_PIN_SEL_MASK 0x0000007fL 7110de2bdb3dSTom St Denis #define GENERIC_I2C_PIN_SELECTION__GENERIC_I2C_SCL_PIN_SEL__SHIFT 0x00000000 7111de2bdb3dSTom St Denis #define GENERIC_I2C_PIN_SELECTION__GENERIC_I2C_SDA_PIN_SEL_MASK 0x00007f00L 7112de2bdb3dSTom St Denis #define GENERIC_I2C_PIN_SELECTION__GENERIC_I2C_SDA_PIN_SEL__SHIFT 0x00000008 7113de2bdb3dSTom St Denis #define GENERIC_I2C_SETUP__GENERIC_I2C_CLK_DRIVE_EN_MASK 0x00000080L 7114de2bdb3dSTom St Denis #define GENERIC_I2C_SETUP__GENERIC_I2C_CLK_DRIVE_EN__SHIFT 0x00000007 7115de2bdb3dSTom St Denis #define GENERIC_I2C_SETUP__GENERIC_I2C_DATA_DRIVE_EN_MASK 0x00000001L 7116de2bdb3dSTom St Denis #define GENERIC_I2C_SETUP__GENERIC_I2C_DATA_DRIVE_EN__SHIFT 0x00000000 7117de2bdb3dSTom St Denis #define GENERIC_I2C_SETUP__GENERIC_I2C_DATA_DRIVE_SEL_MASK 0x00000002L 7118de2bdb3dSTom St Denis #define GENERIC_I2C_SETUP__GENERIC_I2C_DATA_DRIVE_SEL__SHIFT 0x00000001 7119de2bdb3dSTom St Denis #define GENERIC_I2C_SETUP__GENERIC_I2C_INTRA_BYTE_DELAY_MASK 0x0000ff00L 7120de2bdb3dSTom St Denis #define GENERIC_I2C_SETUP__GENERIC_I2C_INTRA_BYTE_DELAY__SHIFT 0x00000008 7121de2bdb3dSTom St Denis #define GENERIC_I2C_SETUP__GENERIC_I2C_TIME_LIMIT_MASK 0xff000000L 7122de2bdb3dSTom St Denis #define GENERIC_I2C_SETUP__GENERIC_I2C_TIME_LIMIT__SHIFT 0x00000018 7123de2bdb3dSTom St Denis #define GENERIC_I2C_SPEED__GENERIC_I2C_DISABLE_FILTER_DURING_STALL_MASK 0x00000010L 7124de2bdb3dSTom St Denis #define GENERIC_I2C_SPEED__GENERIC_I2C_DISABLE_FILTER_DURING_STALL__SHIFT 0x00000004 7125de2bdb3dSTom St Denis #define GENERIC_I2C_SPEED__GENERIC_I2C_PRESCALE_MASK 0xffff0000L 7126de2bdb3dSTom St Denis #define GENERIC_I2C_SPEED__GENERIC_I2C_PRESCALE__SHIFT 0x00000010 7127de2bdb3dSTom St Denis #define GENERIC_I2C_SPEED__GENERIC_I2C_THRESHOLD_MASK 0x00000003L 7128de2bdb3dSTom St Denis #define GENERIC_I2C_SPEED__GENERIC_I2C_THRESHOLD__SHIFT 0x00000000 7129de2bdb3dSTom St Denis #define GENERIC_I2C_STATUS__GENERIC_I2C_ABORTED_MASK 0x00000020L 7130de2bdb3dSTom St Denis #define GENERIC_I2C_STATUS__GENERIC_I2C_ABORTED__SHIFT 0x00000005 7131de2bdb3dSTom St Denis #define GENERIC_I2C_STATUS__GENERIC_I2C_DONE_MASK 0x00000010L 7132de2bdb3dSTom St Denis #define GENERIC_I2C_STATUS__GENERIC_I2C_DONE__SHIFT 0x00000004 7133de2bdb3dSTom St Denis #define GENERIC_I2C_STATUS__GENERIC_I2C_NACK_MASK 0x00000400L 7134de2bdb3dSTom St Denis #define GENERIC_I2C_STATUS__GENERIC_I2C_NACK__SHIFT 0x0000000a 7135de2bdb3dSTom St Denis #define GENERIC_I2C_STATUS__GENERIC_I2C_STATUS_MASK 0x0000000fL 7136de2bdb3dSTom St Denis #define GENERIC_I2C_STATUS__GENERIC_I2C_STATUS__SHIFT 0x00000000 7137de2bdb3dSTom St Denis #define GENERIC_I2C_STATUS__GENERIC_I2C_STOPPED_ON_NACK_MASK 0x00000200L 7138de2bdb3dSTom St Denis #define GENERIC_I2C_STATUS__GENERIC_I2C_STOPPED_ON_NACK__SHIFT 0x00000009 7139de2bdb3dSTom St Denis #define GENERIC_I2C_STATUS__GENERIC_I2C_TIMEOUT_MASK 0x00000040L 7140de2bdb3dSTom St Denis #define GENERIC_I2C_STATUS__GENERIC_I2C_TIMEOUT__SHIFT 0x00000006 7141de2bdb3dSTom St Denis #define GENERIC_I2C_TRANSACTION__GENERIC_I2C_ACK_ON_READ_MASK 0x00000200L 7142de2bdb3dSTom St Denis #define GENERIC_I2C_TRANSACTION__GENERIC_I2C_ACK_ON_READ__SHIFT 0x00000009 7143de2bdb3dSTom St Denis #define GENERIC_I2C_TRANSACTION__GENERIC_I2C_COUNT_MASK 0x000f0000L 7144de2bdb3dSTom St Denis #define GENERIC_I2C_TRANSACTION__GENERIC_I2C_COUNT__SHIFT 0x00000010 7145de2bdb3dSTom St Denis #define GENERIC_I2C_TRANSACTION__GENERIC_I2C_RW_MASK 0x00000001L 7146de2bdb3dSTom St Denis #define GENERIC_I2C_TRANSACTION__GENERIC_I2C_RW__SHIFT 0x00000000 7147de2bdb3dSTom St Denis #define GENERIC_I2C_TRANSACTION__GENERIC_I2C_START_MASK 0x00001000L 7148de2bdb3dSTom St Denis #define GENERIC_I2C_TRANSACTION__GENERIC_I2C_START__SHIFT 0x0000000c 7149de2bdb3dSTom St Denis #define GENERIC_I2C_TRANSACTION__GENERIC_I2C_STOP_MASK 0x00002000L 7150de2bdb3dSTom St Denis #define GENERIC_I2C_TRANSACTION__GENERIC_I2C_STOP_ON_NACK_MASK 0x00000100L 7151de2bdb3dSTom St Denis #define GENERIC_I2C_TRANSACTION__GENERIC_I2C_STOP_ON_NACK__SHIFT 0x00000008 7152de2bdb3dSTom St Denis #define GENERIC_I2C_TRANSACTION__GENERIC_I2C_STOP__SHIFT 0x0000000d 7153de2bdb3dSTom St Denis #define GENFC_RD__VSYNC_SEL_R_MASK 0x00000008L 7154de2bdb3dSTom St Denis #define GENFC_RD__VSYNC_SEL_R__SHIFT 0x00000003 7155de2bdb3dSTom St Denis #define GENFC_WT__VSYNC_SEL_W_MASK 0x00000008L 7156de2bdb3dSTom St Denis #define GENFC_WT__VSYNC_SEL_W__SHIFT 0x00000003 7157de2bdb3dSTom St Denis #define GENMO_RD__GENMO_MONO_ADDRESS_B_MASK 0x00000001L 7158de2bdb3dSTom St Denis #define GENMO_RD__GENMO_MONO_ADDRESS_B__SHIFT 0x00000000 7159de2bdb3dSTom St Denis #define GENMO_RD__ODD_EVEN_MD_PGSEL_MASK 0x00000020L 7160de2bdb3dSTom St Denis #define GENMO_RD__ODD_EVEN_MD_PGSEL__SHIFT 0x00000005 7161de2bdb3dSTom St Denis #define GENMO_RD__VGA_CKSEL_MASK 0x0000000cL 7162de2bdb3dSTom St Denis #define GENMO_RD__VGA_CKSEL__SHIFT 0x00000002 7163de2bdb3dSTom St Denis #define GENMO_RD__VGA_HSYNC_POL_MASK 0x00000040L 7164de2bdb3dSTom St Denis #define GENMO_RD__VGA_HSYNC_POL__SHIFT 0x00000006 7165de2bdb3dSTom St Denis #define GENMO_RD__VGA_RAM_EN_MASK 0x00000002L 7166de2bdb3dSTom St Denis #define GENMO_RD__VGA_RAM_EN__SHIFT 0x00000001 7167de2bdb3dSTom St Denis #define GENMO_RD__VGA_VSYNC_POL_MASK 0x00000080L 7168de2bdb3dSTom St Denis #define GENMO_RD__VGA_VSYNC_POL__SHIFT 0x00000007 7169de2bdb3dSTom St Denis #define GENMO_WT__GENMO_MONO_ADDRESS_B_MASK 0x00000001L 7170de2bdb3dSTom St Denis #define GENMO_WT__GENMO_MONO_ADDRESS_B__SHIFT 0x00000000 7171de2bdb3dSTom St Denis #define GENMO_WT__ODD_EVEN_MD_PGSEL_MASK 0x00000020L 7172de2bdb3dSTom St Denis #define GENMO_WT__ODD_EVEN_MD_PGSEL__SHIFT 0x00000005 7173de2bdb3dSTom St Denis #define GENMO_WT__VGA_CKSEL_MASK 0x0000000cL 7174de2bdb3dSTom St Denis #define GENMO_WT__VGA_CKSEL__SHIFT 0x00000002 7175de2bdb3dSTom St Denis #define GENMO_WT__VGA_HSYNC_POL_MASK 0x00000040L 7176de2bdb3dSTom St Denis #define GENMO_WT__VGA_HSYNC_POL__SHIFT 0x00000006 7177de2bdb3dSTom St Denis #define GENMO_WT__VGA_RAM_EN_MASK 0x00000002L 7178de2bdb3dSTom St Denis #define GENMO_WT__VGA_RAM_EN__SHIFT 0x00000001 7179de2bdb3dSTom St Denis #define GENMO_WT__VGA_VSYNC_POL_MASK 0x00000080L 7180de2bdb3dSTom St Denis #define GENMO_WT__VGA_VSYNC_POL__SHIFT 0x00000007 7181de2bdb3dSTom St Denis #define GENS0__CRT_INTR_MASK 0x00000080L 7182de2bdb3dSTom St Denis #define GENS0__CRT_INTR__SHIFT 0x00000007 7183de2bdb3dSTom St Denis #define GENS0__SENSE_SWITCH_MASK 0x00000010L 7184de2bdb3dSTom St Denis #define GENS0__SENSE_SWITCH__SHIFT 0x00000004 7185de2bdb3dSTom St Denis #define GENS1__NO_DISPLAY_MASK 0x00000001L 7186de2bdb3dSTom St Denis #define GENS1__NO_DISPLAY__SHIFT 0x00000000 7187de2bdb3dSTom St Denis #define GENS1__PIXEL_READ_BACK_MASK 0x00000030L 7188de2bdb3dSTom St Denis #define GENS1__PIXEL_READ_BACK__SHIFT 0x00000004 7189de2bdb3dSTom St Denis #define GENS1__VGA_VSTATUS_MASK 0x00000008L 7190de2bdb3dSTom St Denis #define GENS1__VGA_VSTATUS__SHIFT 0x00000003 7191de2bdb3dSTom St Denis #define GRA00__GRPH_SET_RESET0_MASK 0x00000001L 7192de2bdb3dSTom St Denis #define GRA00__GRPH_SET_RESET0__SHIFT 0x00000000 7193de2bdb3dSTom St Denis #define GRA00__GRPH_SET_RESET1_MASK 0x00000002L 7194de2bdb3dSTom St Denis #define GRA00__GRPH_SET_RESET1__SHIFT 0x00000001 7195de2bdb3dSTom St Denis #define GRA00__GRPH_SET_RESET2_MASK 0x00000004L 7196de2bdb3dSTom St Denis #define GRA00__GRPH_SET_RESET2__SHIFT 0x00000002 7197de2bdb3dSTom St Denis #define GRA00__GRPH_SET_RESET3_MASK 0x00000008L 7198de2bdb3dSTom St Denis #define GRA00__GRPH_SET_RESET3__SHIFT 0x00000003 7199de2bdb3dSTom St Denis #define GRA01__GRPH_SET_RESET_ENA0_MASK 0x00000001L 7200de2bdb3dSTom St Denis #define GRA01__GRPH_SET_RESET_ENA0__SHIFT 0x00000000 7201de2bdb3dSTom St Denis #define GRA01__GRPH_SET_RESET_ENA1_MASK 0x00000002L 7202de2bdb3dSTom St Denis #define GRA01__GRPH_SET_RESET_ENA1__SHIFT 0x00000001 7203de2bdb3dSTom St Denis #define GRA01__GRPH_SET_RESET_ENA2_MASK 0x00000004L 7204de2bdb3dSTom St Denis #define GRA01__GRPH_SET_RESET_ENA2__SHIFT 0x00000002 7205de2bdb3dSTom St Denis #define GRA01__GRPH_SET_RESET_ENA3_MASK 0x00000008L 7206de2bdb3dSTom St Denis #define GRA01__GRPH_SET_RESET_ENA3__SHIFT 0x00000003 7207de2bdb3dSTom St Denis #define GRA02__GRPH_CCOMP_MASK 0x0000000fL 7208de2bdb3dSTom St Denis #define GRA02__GRPH_CCOMP__SHIFT 0x00000000 7209de2bdb3dSTom St Denis #define GRA03__GRPH_FN_SEL_MASK 0x00000018L 7210de2bdb3dSTom St Denis #define GRA03__GRPH_FN_SEL__SHIFT 0x00000003 7211de2bdb3dSTom St Denis #define GRA03__GRPH_ROTATE_MASK 0x00000007L 7212de2bdb3dSTom St Denis #define GRA03__GRPH_ROTATE__SHIFT 0x00000000 7213de2bdb3dSTom St Denis #define GRA04__GRPH_RMAP_MASK 0x00000003L 7214de2bdb3dSTom St Denis #define GRA04__GRPH_RMAP__SHIFT 0x00000000 7215de2bdb3dSTom St Denis #define GRA05__CGA_ODDEVEN_MASK 0x00000010L 7216de2bdb3dSTom St Denis #define GRA05__CGA_ODDEVEN__SHIFT 0x00000004 7217de2bdb3dSTom St Denis #define GRA05__GRPH_OES_MASK 0x00000020L 7218de2bdb3dSTom St Denis #define GRA05__GRPH_OES__SHIFT 0x00000005 7219de2bdb3dSTom St Denis #define GRA05__GRPH_PACK_MASK 0x00000040L 7220de2bdb3dSTom St Denis #define GRA05__GRPH_PACK__SHIFT 0x00000006 7221de2bdb3dSTom St Denis #define GRA05__GRPH_READ1_MASK 0x00000008L 7222de2bdb3dSTom St Denis #define GRA05__GRPH_READ1__SHIFT 0x00000003 7223de2bdb3dSTom St Denis #define GRA05__GRPH_WRITE_MODE_MASK 0x00000003L 7224de2bdb3dSTom St Denis #define GRA05__GRPH_WRITE_MODE__SHIFT 0x00000000 7225de2bdb3dSTom St Denis #define GRA06__GRPH_ADRSEL_MASK 0x0000000cL 7226de2bdb3dSTom St Denis #define GRA06__GRPH_ADRSEL__SHIFT 0x00000002 7227de2bdb3dSTom St Denis #define GRA06__GRPH_GRAPHICS_MASK 0x00000001L 7228de2bdb3dSTom St Denis #define GRA06__GRPH_GRAPHICS__SHIFT 0x00000000 7229de2bdb3dSTom St Denis #define GRA06__GRPH_ODDEVEN_MASK 0x00000002L 7230de2bdb3dSTom St Denis #define GRA06__GRPH_ODDEVEN__SHIFT 0x00000001 7231de2bdb3dSTom St Denis #define GRA07__GRPH_XCARE0_MASK 0x00000001L 7232de2bdb3dSTom St Denis #define GRA07__GRPH_XCARE0__SHIFT 0x00000000 7233de2bdb3dSTom St Denis #define GRA07__GRPH_XCARE1_MASK 0x00000002L 7234de2bdb3dSTom St Denis #define GRA07__GRPH_XCARE1__SHIFT 0x00000001 7235de2bdb3dSTom St Denis #define GRA07__GRPH_XCARE2_MASK 0x00000004L 7236de2bdb3dSTom St Denis #define GRA07__GRPH_XCARE2__SHIFT 0x00000002 7237de2bdb3dSTom St Denis #define GRA07__GRPH_XCARE3_MASK 0x00000008L 7238de2bdb3dSTom St Denis #define GRA07__GRPH_XCARE3__SHIFT 0x00000003 7239de2bdb3dSTom St Denis #define GRA08__GRPH_BMSK_MASK 0x000000ffL 7240de2bdb3dSTom St Denis #define GRA08__GRPH_BMSK__SHIFT 0x00000000 7241de2bdb3dSTom St Denis #define GRPH8_DATA__GRPH_DATA_MASK 0x000000ffL 7242de2bdb3dSTom St Denis #define GRPH8_DATA__GRPH_DATA__SHIFT 0x00000000 7243de2bdb3dSTom St Denis #define GRPH8_IDX__GRPH_IDX_MASK 0x0000000fL 7244de2bdb3dSTom St Denis #define GRPH8_IDX__GRPH_IDX__SHIFT 0x00000000 7245de2bdb3dSTom St Denis #define GRPH_COMPRESS_PITCH__GRPH_COMPRESS_PITCH_MASK 0x0001ffc0L 7246de2bdb3dSTom St Denis #define GRPH_COMPRESS_PITCH__GRPH_COMPRESS_PITCH__SHIFT 0x00000006 7247de2bdb3dSTom St Denis #define GRPH_COMPRESS_SURFACE_ADDRESS__GRPH_COMPRESS_SURFACE_ADDRESS_MASK 0xffffff00L 7248de2bdb3dSTom St Denis #define GRPH_COMPRESS_SURFACE_ADDRESS__GRPH_COMPRESS_SURFACE_ADDRESS__SHIFT 0x00000008 7249de2bdb3dSTom St Denis #define GRPH_COMPRESS_SURFACE_ADDRESS_HIGH__GRPH_COMPRESS_SURFACE_ADDRESS_HIGH_MASK 0x000000ffL 7250de2bdb3dSTom St Denis #define GRPH_COMPRESS_SURFACE_ADDRESS_HIGH__GRPH_COMPRESS_SURFACE_ADDRESS_HIGH__SHIFT 0x00000000 7251de2bdb3dSTom St Denis #define GRPH_CONTROL__GRPH_ADDRESS_TRANSLATION_ENABLE_MASK 0x00010000L 7252de2bdb3dSTom St Denis #define GRPH_CONTROL__GRPH_ADDRESS_TRANSLATION_ENABLE__SHIFT 0x00000010 7253de2bdb3dSTom St Denis #define GRPH_CONTROL__GRPH_ARRAY_MODE_MASK 0x00f00000L 7254de2bdb3dSTom St Denis #define GRPH_CONTROL__GRPH_ARRAY_MODE__SHIFT 0x00000014 7255de2bdb3dSTom St Denis #define GRPH_CONTROL__GRPH_BANK_HEIGHT_MASK 0x00001800L 7256de2bdb3dSTom St Denis #define GRPH_CONTROL__GRPH_BANK_HEIGHT__SHIFT 0x0000000b 7257de2bdb3dSTom St Denis #define GRPH_CONTROL__GRPH_BANK_WIDTH_MASK 0x000000c0L 7258de2bdb3dSTom St Denis #define GRPH_CONTROL__GRPH_BANK_WIDTH__SHIFT 0x00000006 7259de2bdb3dSTom St Denis #define GRPH_CONTROL__GRPH_COLOR_EXPANSION_MODE_MASK 0x80000000L 7260de2bdb3dSTom St Denis #define GRPH_CONTROL__GRPH_COLOR_EXPANSION_MODE__SHIFT 0x0000001f 7261de2bdb3dSTom St Denis #define GRPH_CONTROL__GRPH_DEPTH_MASK 0x00000003L 7262de2bdb3dSTom St Denis #define GRPH_CONTROL__GRPH_DEPTH__SHIFT 0x00000000 7263de2bdb3dSTom St Denis #define GRPH_CONTROL__GRPH_FORMAT_MASK 0x00000700L 7264de2bdb3dSTom St Denis #define GRPH_CONTROL__GRPH_FORMAT__SHIFT 0x00000008 7265de2bdb3dSTom St Denis #define GRPH_CONTROL__GRPH_MACRO_TILE_ASPECT_MASK 0x000c0000L 7266de2bdb3dSTom St Denis #define GRPH_CONTROL__GRPH_MACRO_TILE_ASPECT__SHIFT 0x00000012 72676863660dSAlex Deucher #define GRPH_CONTROL__GRPH_ARRAY_MODE_MASK 0x00f00000L 72686863660dSAlex Deucher #define GRPH_CONTROL__GRPH_ARRAY_MODE__SHIFT 0x00000014 7269de2bdb3dSTom St Denis #define GRPH_CONTROL__GRPH_NUM_BANKS_MASK 0x0000000cL 7270de2bdb3dSTom St Denis #define GRPH_CONTROL__GRPH_NUM_BANKS__SHIFT 0x00000002 7271de2bdb3dSTom St Denis #define GRPH_CONTROL__GRPH_PIPE_CONFIG_MASK 0x1f000000L 7272de2bdb3dSTom St Denis #define GRPH_CONTROL__GRPH_PIPE_CONFIG__SHIFT 0x00000018 7273de2bdb3dSTom St Denis #define GRPH_CONTROL__GRPH_PRIVILEGED_ACCESS_ENABLE_MASK 0x00020000L 7274de2bdb3dSTom St Denis #define GRPH_CONTROL__GRPH_PRIVILEGED_ACCESS_ENABLE__SHIFT 0x00000011 7275de2bdb3dSTom St Denis #define GRPH_CONTROL__GRPH_TILE_SPLIT_MASK 0x0000e000L 7276de2bdb3dSTom St Denis #define GRPH_CONTROL__GRPH_TILE_SPLIT__SHIFT 0x0000000d 7277de2bdb3dSTom St Denis #define GRPH_CONTROL__GRPH_Z_MASK 0x00000030L 7278de2bdb3dSTom St Denis #define GRPH_CONTROL__GRPH_Z__SHIFT 0x00000004 7279de2bdb3dSTom St Denis #define GRPH_DFQ_CONTROL__GRPH_DFQ_MIN_FREE_ENTRIES_MASK 0x00000700L 7280de2bdb3dSTom St Denis #define GRPH_DFQ_CONTROL__GRPH_DFQ_MIN_FREE_ENTRIES__SHIFT 0x00000008 7281de2bdb3dSTom St Denis #define GRPH_DFQ_CONTROL__GRPH_DFQ_RESET_MASK 0x00000001L 7282de2bdb3dSTom St Denis #define GRPH_DFQ_CONTROL__GRPH_DFQ_RESET__SHIFT 0x00000000 7283de2bdb3dSTom St Denis #define GRPH_DFQ_CONTROL__GRPH_DFQ_SIZE_MASK 0x00000070L 7284de2bdb3dSTom St Denis #define GRPH_DFQ_CONTROL__GRPH_DFQ_SIZE__SHIFT 0x00000004 7285de2bdb3dSTom St Denis #define GRPH_DFQ_STATUS__GRPH_DFQ_RESET_ACK_MASK 0x00000200L 7286de2bdb3dSTom St Denis #define GRPH_DFQ_STATUS__GRPH_DFQ_RESET_ACK__SHIFT 0x00000009 7287de2bdb3dSTom St Denis #define GRPH_DFQ_STATUS__GRPH_DFQ_RESET_FLAG_MASK 0x00000100L 7288de2bdb3dSTom St Denis #define GRPH_DFQ_STATUS__GRPH_DFQ_RESET_FLAG__SHIFT 0x00000008 7289de2bdb3dSTom St Denis #define GRPH_DFQ_STATUS__GRPH_PRIMARY_DFQ_NUM_ENTRIES_MASK 0x0000000fL 7290de2bdb3dSTom St Denis #define GRPH_DFQ_STATUS__GRPH_PRIMARY_DFQ_NUM_ENTRIES__SHIFT 0x00000000 7291de2bdb3dSTom St Denis #define GRPH_DFQ_STATUS__GRPH_SECONDARY_DFQ_NUM_ENTRIES_MASK 0x000000f0L 7292de2bdb3dSTom St Denis #define GRPH_DFQ_STATUS__GRPH_SECONDARY_DFQ_NUM_ENTRIES__SHIFT 0x00000004 7293de2bdb3dSTom St Denis #define GRPH_ENABLE__GRPH_ENABLE_MASK 0x00000001L 7294de2bdb3dSTom St Denis #define GRPH_ENABLE__GRPH_ENABLE__SHIFT 0x00000000 7295de2bdb3dSTom St Denis #define GRPH_FLIP_CONTROL__GRPH_SURFACE_UPDATE_H_RETRACE_EN_MASK 0x00000001L 7296de2bdb3dSTom St Denis #define GRPH_FLIP_CONTROL__GRPH_SURFACE_UPDATE_H_RETRACE_EN__SHIFT 0x00000000 7297de2bdb3dSTom St Denis #define GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK 0x00000001L 7298de2bdb3dSTom St Denis #define GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK__SHIFT 0x00000000 7299de2bdb3dSTom St Denis #define GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_TYPE_MASK 0x00000100L 7300de2bdb3dSTom St Denis #define GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_TYPE__SHIFT 0x00000008 7301de2bdb3dSTom St Denis #define GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK 0x00000100L 7302de2bdb3dSTom St Denis #define GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR__SHIFT 0x00000008 7303de2bdb3dSTom St Denis #define GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED_MASK 0x00000001L 7304de2bdb3dSTom St Denis #define GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED__SHIFT 0x00000000 7305de2bdb3dSTom St Denis #define GRPH_LUT_10BIT_BYPASS__GRPH_LUT_10BIT_BYPASS_DBL_BUF_EN_MASK 0x00010000L 7306de2bdb3dSTom St Denis #define GRPH_LUT_10BIT_BYPASS__GRPH_LUT_10BIT_BYPASS_DBL_BUF_EN__SHIFT 0x00000010 7307de2bdb3dSTom St Denis #define GRPH_LUT_10BIT_BYPASS__GRPH_LUT_10BIT_BYPASS_EN_MASK 0x00000100L 7308de2bdb3dSTom St Denis #define GRPH_LUT_10BIT_BYPASS__GRPH_LUT_10BIT_BYPASS_EN__SHIFT 0x00000008 7309de2bdb3dSTom St Denis #define GRPH_PITCH__GRPH_PITCH_MASK 0x00007fffL 7310de2bdb3dSTom St Denis #define GRPH_PITCH__GRPH_PITCH__SHIFT 0x00000000 7311de2bdb3dSTom St Denis #define GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_DFQ_ENABLE_MASK 0x00000001L 7312de2bdb3dSTom St Denis #define GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_DFQ_ENABLE__SHIFT 0x00000000 7313de2bdb3dSTom St Denis #define GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_SURFACE_ADDRESS_MASK 0xffffff00L 7314de2bdb3dSTom St Denis #define GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_SURFACE_ADDRESS__SHIFT 0x00000008 7315de2bdb3dSTom St Denis #define GRPH_PRIMARY_SURFACE_ADDRESS_HIGH__GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_MASK 0x000000ffL 7316de2bdb3dSTom St Denis #define GRPH_PRIMARY_SURFACE_ADDRESS_HIGH__GRPH_PRIMARY_SURFACE_ADDRESS_HIGH__SHIFT 0x00000000 7317de2bdb3dSTom St Denis #define GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_DFQ_ENABLE_MASK 0x00000001L 7318de2bdb3dSTom St Denis #define GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_DFQ_ENABLE__SHIFT 0x00000000 7319de2bdb3dSTom St Denis #define GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_SURFACE_ADDRESS_MASK 0xffffff00L 7320de2bdb3dSTom St Denis #define GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_SURFACE_ADDRESS__SHIFT 0x00000008 7321de2bdb3dSTom St Denis #define GRPH_SECONDARY_SURFACE_ADDRESS_HIGH__GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_MASK 0x000000ffL 7322de2bdb3dSTom St Denis #define GRPH_SECONDARY_SURFACE_ADDRESS_HIGH__GRPH_SECONDARY_SURFACE_ADDRESS_HIGH__SHIFT 0x00000000 7323de2bdb3dSTom St Denis #define GRPH_STEREOSYNC_FLIP__GRPH_PRIMARY_SURFACE_PENDING_MASK 0x00010000L 7324de2bdb3dSTom St Denis #define GRPH_STEREOSYNC_FLIP__GRPH_PRIMARY_SURFACE_PENDING__SHIFT 0x00000010 7325de2bdb3dSTom St Denis #define GRPH_STEREOSYNC_FLIP__GRPH_SECONDARY_SURFACE_PENDING_MASK 0x00020000L 7326de2bdb3dSTom St Denis #define GRPH_STEREOSYNC_FLIP__GRPH_SECONDARY_SURFACE_PENDING__SHIFT 0x00000011 7327de2bdb3dSTom St Denis #define GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_FLIP_EN_MASK 0x00000001L 7328de2bdb3dSTom St Denis #define GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_FLIP_EN__SHIFT 0x00000000 7329de2bdb3dSTom St Denis #define GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_FLIP_MODE_MASK 0x00000300L 7330de2bdb3dSTom St Denis #define GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_FLIP_MODE__SHIFT 0x00000008 7331de2bdb3dSTom St Denis #define GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_SELECT_DISABLE_MASK 0x10000000L 7332de2bdb3dSTom St Denis #define GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_SELECT_DISABLE__SHIFT 0x0000001c 7333de2bdb3dSTom St Denis #define GRPH_SURFACE_ADDRESS_HIGH_INUSE__GRPH_SURFACE_ADDRESS_HIGH_INUSE_MASK 0x000000ffL 7334de2bdb3dSTom St Denis #define GRPH_SURFACE_ADDRESS_HIGH_INUSE__GRPH_SURFACE_ADDRESS_HIGH_INUSE__SHIFT 0x00000000 7335de2bdb3dSTom St Denis #define GRPH_SURFACE_ADDRESS_INUSE__GRPH_SURFACE_ADDRESS_INUSE_MASK 0xffffff00L 7336de2bdb3dSTom St Denis #define GRPH_SURFACE_ADDRESS_INUSE__GRPH_SURFACE_ADDRESS_INUSE__SHIFT 0x00000008 7337de2bdb3dSTom St Denis #define GRPH_SURFACE_OFFSET_X__GRPH_SURFACE_OFFSET_X_MASK 0x00003fffL 7338de2bdb3dSTom St Denis #define GRPH_SURFACE_OFFSET_X__GRPH_SURFACE_OFFSET_X__SHIFT 0x00000000 7339de2bdb3dSTom St Denis #define GRPH_SURFACE_OFFSET_Y__GRPH_SURFACE_OFFSET_Y_MASK 0x00003fffL 7340de2bdb3dSTom St Denis #define GRPH_SURFACE_OFFSET_Y__GRPH_SURFACE_OFFSET_Y__SHIFT 0x00000000 7341de2bdb3dSTom St Denis #define GRPH_SWAP_CNTL__GRPH_ALPHA_CROSSBAR_MASK 0x00000c00L 7342de2bdb3dSTom St Denis #define GRPH_SWAP_CNTL__GRPH_ALPHA_CROSSBAR__SHIFT 0x0000000a 7343de2bdb3dSTom St Denis #define GRPH_SWAP_CNTL__GRPH_BLUE_CROSSBAR_MASK 0x00000300L 7344de2bdb3dSTom St Denis #define GRPH_SWAP_CNTL__GRPH_BLUE_CROSSBAR__SHIFT 0x00000008 7345de2bdb3dSTom St Denis #define GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP_MASK 0x00000003L 7346de2bdb3dSTom St Denis #define GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT 0x00000000 7347de2bdb3dSTom St Denis #define GRPH_SWAP_CNTL__GRPH_GREEN_CROSSBAR_MASK 0x000000c0L 7348de2bdb3dSTom St Denis #define GRPH_SWAP_CNTL__GRPH_GREEN_CROSSBAR__SHIFT 0x00000006 7349de2bdb3dSTom St Denis #define GRPH_SWAP_CNTL__GRPH_RED_CROSSBAR_MASK 0x00000030L 7350de2bdb3dSTom St Denis #define GRPH_SWAP_CNTL__GRPH_RED_CROSSBAR__SHIFT 0x00000004 7351de2bdb3dSTom St Denis #define GRPH_UPDATE__GRPH_MODE_DISABLE_MULTIPLE_UPDATE_MASK 0x01000000L 7352de2bdb3dSTom St Denis #define GRPH_UPDATE__GRPH_MODE_DISABLE_MULTIPLE_UPDATE__SHIFT 0x00000018 7353de2bdb3dSTom St Denis #define GRPH_UPDATE__GRPH_MODE_UPDATE_PENDING_MASK 0x00000001L 7354de2bdb3dSTom St Denis #define GRPH_UPDATE__GRPH_MODE_UPDATE_PENDING__SHIFT 0x00000000 7355de2bdb3dSTom St Denis #define GRPH_UPDATE__GRPH_MODE_UPDATE_TAKEN_MASK 0x00000002L 7356de2bdb3dSTom St Denis #define GRPH_UPDATE__GRPH_MODE_UPDATE_TAKEN__SHIFT 0x00000001 7357de2bdb3dSTom St Denis #define GRPH_UPDATE__GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE_MASK 0x10000000L 7358de2bdb3dSTom St Denis #define GRPH_UPDATE__GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE__SHIFT 0x0000001c 7359de2bdb3dSTom St Denis #define GRPH_UPDATE__GRPH_SURFACE_UPDATE_PENDING_MASK 0x00000004L 7360de2bdb3dSTom St Denis #define GRPH_UPDATE__GRPH_SURFACE_UPDATE_PENDING__SHIFT 0x00000002 7361de2bdb3dSTom St Denis #define GRPH_UPDATE__GRPH_SURFACE_UPDATE_TAKEN_MASK 0x00000008L 7362de2bdb3dSTom St Denis #define GRPH_UPDATE__GRPH_SURFACE_UPDATE_TAKEN__SHIFT 0x00000003 7363de2bdb3dSTom St Denis #define GRPH_UPDATE__GRPH_SURFACE_XDMA_PENDING_ENABLE_MASK 0x00000100L 7364de2bdb3dSTom St Denis #define GRPH_UPDATE__GRPH_SURFACE_XDMA_PENDING_ENABLE__SHIFT 0x00000008 7365de2bdb3dSTom St Denis #define GRPH_UPDATE__GRPH_UPDATE_LOCK_MASK 0x00010000L 7366de2bdb3dSTom St Denis #define GRPH_UPDATE__GRPH_UPDATE_LOCK__SHIFT 0x00000010 7367de2bdb3dSTom St Denis #define GRPH_X_END__GRPH_X_END_MASK 0x00007fffL 7368de2bdb3dSTom St Denis #define GRPH_X_END__GRPH_X_END__SHIFT 0x00000000 7369de2bdb3dSTom St Denis #define GRPH_X_START__GRPH_X_START_MASK 0x00003fffL 7370de2bdb3dSTom St Denis #define GRPH_X_START__GRPH_X_START__SHIFT 0x00000000 7371de2bdb3dSTom St Denis #define GRPH_Y_END__GRPH_Y_END_MASK 0x00007fffL 7372de2bdb3dSTom St Denis #define GRPH_Y_END__GRPH_Y_END__SHIFT 0x00000000 7373de2bdb3dSTom St Denis #define GRPH_Y_START__GRPH_Y_START_MASK 0x00003fffL 7374de2bdb3dSTom St Denis #define GRPH_Y_START__GRPH_Y_START__SHIFT 0x00000000 7375de2bdb3dSTom St Denis #define HDMI_ACR_32_0__HDMI_ACR_CTS_32_MASK 0xfffff000L 7376de2bdb3dSTom St Denis #define HDMI_ACR_32_0__HDMI_ACR_CTS_32__SHIFT 0x0000000c 7377de2bdb3dSTom St Denis #define HDMI_ACR_32_1__HDMI_ACR_N_32_MASK 0x000fffffL 7378de2bdb3dSTom St Denis #define HDMI_ACR_32_1__HDMI_ACR_N_32__SHIFT 0x00000000 7379de2bdb3dSTom St Denis #define HDMI_ACR_44_0__HDMI_ACR_CTS_44_MASK 0xfffff000L 7380de2bdb3dSTom St Denis #define HDMI_ACR_44_0__HDMI_ACR_CTS_44__SHIFT 0x0000000c 7381de2bdb3dSTom St Denis #define HDMI_ACR_44_1__HDMI_ACR_N_44_MASK 0x000fffffL 7382de2bdb3dSTom St Denis #define HDMI_ACR_44_1__HDMI_ACR_N_44__SHIFT 0x00000000 7383de2bdb3dSTom St Denis #define HDMI_ACR_48_0__HDMI_ACR_CTS_48_MASK 0xfffff000L 7384de2bdb3dSTom St Denis #define HDMI_ACR_48_0__HDMI_ACR_CTS_48__SHIFT 0x0000000c 7385de2bdb3dSTom St Denis #define HDMI_ACR_48_1__HDMI_ACR_N_48_MASK 0x000fffffL 7386de2bdb3dSTom St Denis #define HDMI_ACR_48_1__HDMI_ACR_N_48__SHIFT 0x00000000 7387de2bdb3dSTom St Denis #define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY_MASK 0x80000000L 7388de2bdb3dSTom St Denis #define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY__SHIFT 0x0000001f 7389de2bdb3dSTom St Denis #define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_MASK 0x00001000L 7390de2bdb3dSTom St Denis #define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND__SHIFT 0x0000000c 7391de2bdb3dSTom St Denis #define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT_MASK 0x00000002L 7392de2bdb3dSTom St Denis #define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT__SHIFT 0x00000001 7393de2bdb3dSTom St Denis #define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE_MASK 0x00070000L 7394de2bdb3dSTom St Denis #define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE__SHIFT 0x00000010 7395de2bdb3dSTom St Denis #define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT_MASK 0x00000030L 7396de2bdb3dSTom St Denis #define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT__SHIFT 0x00000004 7397de2bdb3dSTom St Denis #define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND_MASK 0x00000001L 7398de2bdb3dSTom St Denis #define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND__SHIFT 0x00000000 7399de2bdb3dSTom St Denis #define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE_MASK 0x00000100L 7400de2bdb3dSTom St Denis #define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE__SHIFT 0x00000008 7401de2bdb3dSTom St Denis #define HDMI_ACR_STATUS_0__HDMI_ACR_CTS_MASK 0xfffff000L 7402de2bdb3dSTom St Denis #define HDMI_ACR_STATUS_0__HDMI_ACR_CTS__SHIFT 0x0000000c 7403de2bdb3dSTom St Denis #define HDMI_ACR_STATUS_1__HDMI_ACR_N_MASK 0x000fffffL 7404de2bdb3dSTom St Denis #define HDMI_ACR_STATUS_1__HDMI_ACR_N__SHIFT 0x00000000 7405de2bdb3dSTom St Denis #define HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN_MASK 0x00000030L 7406de2bdb3dSTom St Denis #define HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN__SHIFT 0x00000004 7407de2bdb3dSTom St Denis #define HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_PACKETS_PER_LINE_MASK 0x001f0000L 7408de2bdb3dSTom St Denis #define HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_PACKETS_PER_LINE__SHIFT 0x00000010 7409de2bdb3dSTom St Denis #define HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_SEND_MAX_PACKETS_MASK 0x00000100L 7410de2bdb3dSTom St Denis #define HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_SEND_MAX_PACKETS__SHIFT 0x00000008 7411de2bdb3dSTom St Denis #define HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH_MASK 0x30000000L 7412de2bdb3dSTom St Denis #define HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH__SHIFT 0x0000001c 7413de2bdb3dSTom St Denis #define HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE_MASK 0x01000000L 7414de2bdb3dSTom St Denis #define HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE__SHIFT 0x00000018 7415de2bdb3dSTom St Denis #define HDMI_CONTROL__HDMI_ERROR_ACK_MASK 0x00000100L 7416de2bdb3dSTom St Denis #define HDMI_CONTROL__HDMI_ERROR_ACK__SHIFT 0x00000008 7417de2bdb3dSTom St Denis #define HDMI_CONTROL__HDMI_ERROR_MASK_MASK 0x00000200L 7418de2bdb3dSTom St Denis #define HDMI_CONTROL__HDMI_ERROR_MASK__SHIFT 0x00000009 7419de2bdb3dSTom St Denis #define HDMI_CONTROL__HDMI_KEEPOUT_MODE_MASK 0x00000001L 7420de2bdb3dSTom St Denis #define HDMI_CONTROL__HDMI_KEEPOUT_MODE__SHIFT 0x00000000 7421de2bdb3dSTom St Denis #define HDMI_CONTROL__HDMI_PACKET_GEN_VERSION_MASK 0x00000010L 7422de2bdb3dSTom St Denis #define HDMI_CONTROL__HDMI_PACKET_GEN_VERSION__SHIFT 0x00000004 7423de2bdb3dSTom St Denis #define HDMI_GC__HDMI_DEFAULT_PHASE_MASK 0x00000010L 7424de2bdb3dSTom St Denis #define HDMI_GC__HDMI_DEFAULT_PHASE__SHIFT 0x00000004 7425de2bdb3dSTom St Denis #define HDMI_GC__HDMI_GC_AVMUTE_CONT_MASK 0x00000004L 7426de2bdb3dSTom St Denis #define HDMI_GC__HDMI_GC_AVMUTE_CONT__SHIFT 0x00000002 7427de2bdb3dSTom St Denis #define HDMI_GC__HDMI_GC_AVMUTE_MASK 0x00000001L 7428de2bdb3dSTom St Denis #define HDMI_GC__HDMI_GC_AVMUTE__SHIFT 0x00000000 7429de2bdb3dSTom St Denis #define HDMI_GC__HDMI_PACKING_PHASE_MASK 0x00000f00L 7430de2bdb3dSTom St Denis #define HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE_MASK 0x00001000L 7431de2bdb3dSTom St Denis #define HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE__SHIFT 0x0000000c 7432de2bdb3dSTom St Denis #define HDMI_GC__HDMI_PACKING_PHASE__SHIFT 0x00000008 7433de2bdb3dSTom St Denis #define HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT_MASK 0x00000002L 7434de2bdb3dSTom St Denis #define HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT__SHIFT 0x00000001 7435de2bdb3dSTom St Denis #define HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_MASK 0x003f0000L 7436de2bdb3dSTom St Denis #define HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE__SHIFT 0x00000010 7437de2bdb3dSTom St Denis #define HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND_MASK 0x00000001L 7438de2bdb3dSTom St Denis #define HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND__SHIFT 0x00000000 7439de2bdb3dSTom St Denis #define HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT_MASK 0x00000020L 7440de2bdb3dSTom St Denis #define HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT__SHIFT 0x00000005 7441de2bdb3dSTom St Denis #define HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_MASK 0x3f000000L 7442de2bdb3dSTom St Denis #define HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE__SHIFT 0x00000018 7443de2bdb3dSTom St Denis #define HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND_MASK 0x00000010L 7444de2bdb3dSTom St Denis #define HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND__SHIFT 0x00000004 7445de2bdb3dSTom St Denis #define HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_CONT_MASK 0x00000002L 7446de2bdb3dSTom St Denis #define HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_CONT__SHIFT 0x00000001 7447de2bdb3dSTom St Denis #define HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_LINE_MASK 0x003f0000L 7448de2bdb3dSTom St Denis #define HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_LINE__SHIFT 0x00000010 7449de2bdb3dSTom St Denis #define HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_SEND_MASK 0x00000001L 7450de2bdb3dSTom St Denis #define HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_SEND__SHIFT 0x00000000 7451de2bdb3dSTom St Denis #define HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_CONT_MASK 0x00000020L 7452de2bdb3dSTom St Denis #define HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_CONT__SHIFT 0x00000005 7453de2bdb3dSTom St Denis #define HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_LINE_MASK 0x3f000000L 7454de2bdb3dSTom St Denis #define HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_LINE__SHIFT 0x00000018 7455de2bdb3dSTom St Denis #define HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_SEND_MASK 0x00000010L 7456de2bdb3dSTom St Denis #define HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_SEND__SHIFT 0x00000004 7457de2bdb3dSTom St Denis #define HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT_MASK 0x00000020L 7458de2bdb3dSTom St Denis #define HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT__SHIFT 0x00000005 7459de2bdb3dSTom St Denis #define HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND_MASK 0x00000010L 7460de2bdb3dSTom St Denis #define HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND__SHIFT 0x00000004 7461de2bdb3dSTom St Denis #define HDMI_INFOFRAME_CONTROL0__HDMI_AVI_INFO_CONT_MASK 0x00000002L 7462de2bdb3dSTom St Denis #define HDMI_INFOFRAME_CONTROL0__HDMI_AVI_INFO_CONT__SHIFT 0x00000001 7463de2bdb3dSTom St Denis #define HDMI_INFOFRAME_CONTROL0__HDMI_AVI_INFO_SEND_MASK 0x00000001L 7464de2bdb3dSTom St Denis #define HDMI_INFOFRAME_CONTROL0__HDMI_AVI_INFO_SEND__SHIFT 0x00000000 7465de2bdb3dSTom St Denis #define HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT_MASK 0x00000200L 7466de2bdb3dSTom St Denis #define HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT__SHIFT 0x00000009 7467de2bdb3dSTom St Denis #define HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND_MASK 0x00000100L 7468de2bdb3dSTom St Denis #define HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND__SHIFT 0x00000008 7469de2bdb3dSTom St Denis #define HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE_MASK 0x00003f00L 7470de2bdb3dSTom St Denis #define HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE__SHIFT 0x00000008 7471de2bdb3dSTom St Denis #define HDMI_INFOFRAME_CONTROL1__HDMI_AVI_INFO_LINE_MASK 0x0000003fL 7472de2bdb3dSTom St Denis #define HDMI_INFOFRAME_CONTROL1__HDMI_AVI_INFO_LINE__SHIFT 0x00000000 7473de2bdb3dSTom St Denis #define HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE_MASK 0x003f0000L 7474de2bdb3dSTom St Denis #define HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE__SHIFT 0x00000010 7475de2bdb3dSTom St Denis #define HDMI_STATUS__HDMI_ACTIVE_AVMUTE_MASK 0x00000001L 7476de2bdb3dSTom St Denis #define HDMI_STATUS__HDMI_ACTIVE_AVMUTE__SHIFT 0x00000000 7477de2bdb3dSTom St Denis #define HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR_MASK 0x00010000L 7478de2bdb3dSTom St Denis #define HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR__SHIFT 0x00000010 7479de2bdb3dSTom St Denis #define HDMI_STATUS__HDMI_ERROR_INT_MASK 0x08000000L 7480de2bdb3dSTom St Denis #define HDMI_STATUS__HDMI_ERROR_INT__SHIFT 0x0000001b 7481de2bdb3dSTom St Denis #define HDMI_STATUS__HDMI_VBI_PACKET_ERROR_MASK 0x00100000L 7482de2bdb3dSTom St Denis #define HDMI_STATUS__HDMI_VBI_PACKET_ERROR__SHIFT 0x00000014 7483de2bdb3dSTom St Denis #define HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT_MASK 0x00000020L 7484de2bdb3dSTom St Denis #define HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT__SHIFT 0x00000005 7485de2bdb3dSTom St Denis #define HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND_MASK 0x00000010L 7486de2bdb3dSTom St Denis #define HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND__SHIFT 0x00000004 7487de2bdb3dSTom St Denis #define HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT_MASK 0x00000200L 7488de2bdb3dSTom St Denis #define HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT__SHIFT 0x00000009 7489*7c50a3e9SAlan Liu #define HDMI_VBI_PACKET_CONTROL__HDMI_ACP_SEND_MASK 0x1000 7490*7c50a3e9SAlan Liu #define HDMI_VBI_PACKET_CONTROL__HDMI_ACP_SEND__SHIFT 0xc 7491de2bdb3dSTom St Denis #define HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE_MASK 0x003f0000L 7492de2bdb3dSTom St Denis #define HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE__SHIFT 0x00000010 7493de2bdb3dSTom St Denis #define HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND_MASK 0x00000100L 7494de2bdb3dSTom St Denis #define HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND__SHIFT 0x00000008 7495de2bdb3dSTom St Denis #define HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND_MASK 0x00000001L 7496de2bdb3dSTom St Denis #define HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND__SHIFT 0x00000000 7497de2bdb3dSTom St Denis #define IDDCCIF02_DBG_DCCIF_C__DBG_DCCIF_C_MASK 0xffffffffL 7498de2bdb3dSTom St Denis #define IDDCCIF02_DBG_DCCIF_C__DBG_DCCIF_C__SHIFT 0x00000000 7499de2bdb3dSTom St Denis #define IDDCCIF04_DBG_DCCIF_E__DBG_DCCIF_E_MASK 0xffffffffL 7500de2bdb3dSTom St Denis #define IDDCCIF04_DBG_DCCIF_E__DBG_DCCIF_E__SHIFT 0x00000000 7501de2bdb3dSTom St Denis #define IDDCCIF05_DBG_DCCIF_F__DBG_DCCIF_F_MASK 0xffffffffL 7502de2bdb3dSTom St Denis #define IDDCCIF05_DBG_DCCIF_F__DBG_DCCIF_F__SHIFT 0x00000000 7503de2bdb3dSTom St Denis #define INPUT_CSC_C11_C12__INPUT_CSC_C11_MASK 0x0000ffffL 7504de2bdb3dSTom St Denis #define INPUT_CSC_C11_C12__INPUT_CSC_C11__SHIFT 0x00000000 7505de2bdb3dSTom St Denis #define INPUT_CSC_C11_C12__INPUT_CSC_C12_MASK 0xffff0000L 7506de2bdb3dSTom St Denis #define INPUT_CSC_C11_C12__INPUT_CSC_C12__SHIFT 0x00000010 7507de2bdb3dSTom St Denis #define INPUT_CSC_C13_C14__INPUT_CSC_C13_MASK 0x0000ffffL 7508de2bdb3dSTom St Denis #define INPUT_CSC_C13_C14__INPUT_CSC_C13__SHIFT 0x00000000 7509de2bdb3dSTom St Denis #define INPUT_CSC_C13_C14__INPUT_CSC_C14_MASK 0xffff0000L 7510de2bdb3dSTom St Denis #define INPUT_CSC_C13_C14__INPUT_CSC_C14__SHIFT 0x00000010 7511de2bdb3dSTom St Denis #define INPUT_CSC_C21_C22__INPUT_CSC_C21_MASK 0x0000ffffL 7512de2bdb3dSTom St Denis #define INPUT_CSC_C21_C22__INPUT_CSC_C21__SHIFT 0x00000000 7513de2bdb3dSTom St Denis #define INPUT_CSC_C21_C22__INPUT_CSC_C22_MASK 0xffff0000L 7514de2bdb3dSTom St Denis #define INPUT_CSC_C21_C22__INPUT_CSC_C22__SHIFT 0x00000010 7515de2bdb3dSTom St Denis #define INPUT_CSC_C23_C24__INPUT_CSC_C23_MASK 0x0000ffffL 7516de2bdb3dSTom St Denis #define INPUT_CSC_C23_C24__INPUT_CSC_C23__SHIFT 0x00000000 7517de2bdb3dSTom St Denis #define INPUT_CSC_C23_C24__INPUT_CSC_C24_MASK 0xffff0000L 7518de2bdb3dSTom St Denis #define INPUT_CSC_C23_C24__INPUT_CSC_C24__SHIFT 0x00000010 7519de2bdb3dSTom St Denis #define INPUT_CSC_C31_C32__INPUT_CSC_C31_MASK 0x0000ffffL 7520de2bdb3dSTom St Denis #define INPUT_CSC_C31_C32__INPUT_CSC_C31__SHIFT 0x00000000 7521de2bdb3dSTom St Denis #define INPUT_CSC_C31_C32__INPUT_CSC_C32_MASK 0xffff0000L 7522de2bdb3dSTom St Denis #define INPUT_CSC_C31_C32__INPUT_CSC_C32__SHIFT 0x00000010 7523de2bdb3dSTom St Denis #define INPUT_CSC_C33_C34__INPUT_CSC_C33_MASK 0x0000ffffL 7524de2bdb3dSTom St Denis #define INPUT_CSC_C33_C34__INPUT_CSC_C33__SHIFT 0x00000000 7525de2bdb3dSTom St Denis #define INPUT_CSC_C33_C34__INPUT_CSC_C34_MASK 0xffff0000L 7526de2bdb3dSTom St Denis #define INPUT_CSC_C33_C34__INPUT_CSC_C34__SHIFT 0x00000010 7527de2bdb3dSTom St Denis #define INPUT_CSC_CONTROL__INPUT_CSC_GRPH_MODE_MASK 0x00000003L 7528de2bdb3dSTom St Denis #define INPUT_CSC_CONTROL__INPUT_CSC_GRPH_MODE__SHIFT 0x00000000 7529de2bdb3dSTom St Denis #define INPUT_CSC_CONTROL__INPUT_CSC_OVL_MODE_MASK 0x00000030L 7530de2bdb3dSTom St Denis #define INPUT_CSC_CONTROL__INPUT_CSC_OVL_MODE__SHIFT 0x00000004 7531de2bdb3dSTom St Denis #define INPUT_GAMMA_CONTROL__GRPH_INPUT_GAMMA_MODE_MASK 0x00000003L 7532de2bdb3dSTom St Denis #define INPUT_GAMMA_CONTROL__GRPH_INPUT_GAMMA_MODE__SHIFT 0x00000000 7533de2bdb3dSTom St Denis #define INPUT_GAMMA_CONTROL__OVL_INPUT_GAMMA_MODE_MASK 0x00000030L 7534de2bdb3dSTom St Denis #define INPUT_GAMMA_CONTROL__OVL_INPUT_GAMMA_MODE__SHIFT 0x00000004 7535de2bdb3dSTom St Denis #define KEY_CONTROL__GRPH_OVL_HALF_BLEND_MASK 0x10000000L 7536de2bdb3dSTom St Denis #define KEY_CONTROL__GRPH_OVL_HALF_BLEND__SHIFT 0x0000001c 7537de2bdb3dSTom St Denis #define KEY_CONTROL__KEY_MODE_MASK 0x00000006L 7538de2bdb3dSTom St Denis #define KEY_CONTROL__KEY_MODE__SHIFT 0x00000001 7539de2bdb3dSTom St Denis #define KEY_CONTROL__KEY_SELECT_MASK 0x00000001L 7540de2bdb3dSTom St Denis #define KEY_CONTROL__KEY_SELECT__SHIFT 0x00000000 7541de2bdb3dSTom St Denis #define KEY_RANGE_ALPHA__KEY_ALPHA_HIGH_MASK 0xffff0000L 7542de2bdb3dSTom St Denis #define KEY_RANGE_ALPHA__KEY_ALPHA_HIGH__SHIFT 0x00000010 7543de2bdb3dSTom St Denis #define KEY_RANGE_ALPHA__KEY_ALPHA_LOW_MASK 0x0000ffffL 7544de2bdb3dSTom St Denis #define KEY_RANGE_ALPHA__KEY_ALPHA_LOW__SHIFT 0x00000000 7545de2bdb3dSTom St Denis #define KEY_RANGE_BLUE__KEY_BLUE_HIGH_MASK 0xffff0000L 7546de2bdb3dSTom St Denis #define KEY_RANGE_BLUE__KEY_BLUE_HIGH__SHIFT 0x00000010 7547de2bdb3dSTom St Denis #define KEY_RANGE_BLUE__KEY_BLUE_LOW_MASK 0x0000ffffL 7548de2bdb3dSTom St Denis #define KEY_RANGE_BLUE__KEY_BLUE_LOW__SHIFT 0x00000000 7549de2bdb3dSTom St Denis #define KEY_RANGE_GREEN__KEY_GREEN_HIGH_MASK 0xffff0000L 7550de2bdb3dSTom St Denis #define KEY_RANGE_GREEN__KEY_GREEN_HIGH__SHIFT 0x00000010 7551de2bdb3dSTom St Denis #define KEY_RANGE_GREEN__KEY_GREEN_LOW_MASK 0x0000ffffL 7552de2bdb3dSTom St Denis #define KEY_RANGE_GREEN__KEY_GREEN_LOW__SHIFT 0x00000000 7553de2bdb3dSTom St Denis #define KEY_RANGE_RED__KEY_RED_HIGH_MASK 0xffff0000L 7554de2bdb3dSTom St Denis #define KEY_RANGE_RED__KEY_RED_HIGH__SHIFT 0x00000010 7555de2bdb3dSTom St Denis #define KEY_RANGE_RED__KEY_RED_LOW_MASK 0x0000ffffL 7556de2bdb3dSTom St Denis #define KEY_RANGE_RED__KEY_RED_LOW__SHIFT 0x00000000 7557de2bdb3dSTom St Denis #define LB_DEBUG2__LB_DEBUG2_MASK 0xffffffffL 7558de2bdb3dSTom St Denis #define LB_DEBUG2__LB_DEBUG2__SHIFT 0x00000000 7559de2bdb3dSTom St Denis #define LB_DEBUG__LB_DEBUG_MASK 0xffffffffL 7560de2bdb3dSTom St Denis #define LB_DEBUG__LB_DEBUG__SHIFT 0x00000000 7561de2bdb3dSTom St Denis #define LB_NO_OUTSTANDING_REQ_STATUS__LB_NO_OUTSTANDING_REQ_STAT_MASK 0x00000001L 7562de2bdb3dSTom St Denis #define LB_NO_OUTSTANDING_REQ_STATUS__LB_NO_OUTSTANDING_REQ_STAT__SHIFT 0x00000000 7563de2bdb3dSTom St Denis #define LB_SYNC_RESET_SEL__LB_SYNC_RESET_SEL2_MASK 0x00000010L 7564de2bdb3dSTom St Denis #define LB_SYNC_RESET_SEL__LB_SYNC_RESET_SEL2__SHIFT 0x00000004 7565de2bdb3dSTom St Denis #define LB_SYNC_RESET_SEL__LB_SYNC_RESET_SEL_MASK 0x00000003L 7566de2bdb3dSTom St Denis #define LB_SYNC_RESET_SEL__LB_SYNC_RESET_SEL__SHIFT 0x00000000 7567de2bdb3dSTom St Denis #define LB_TEST_DEBUG_DATA__LB_TEST_DEBUG_DATA_MASK 0xffffffffL 7568de2bdb3dSTom St Denis #define LB_TEST_DEBUG_DATA__LB_TEST_DEBUG_DATA__SHIFT 0x00000000 7569de2bdb3dSTom St Denis #define LB_TEST_DEBUG_INDEX__LB_TEST_DEBUG_INDEX_MASK 0x000000ffL 7570de2bdb3dSTom St Denis #define LB_TEST_DEBUG_INDEX__LB_TEST_DEBUG_INDEX__SHIFT 0x00000000 7571de2bdb3dSTom St Denis #define LB_TEST_DEBUG_INDEX__LB_TEST_DEBUG_WRITE_EN_MASK 0x00000100L 7572de2bdb3dSTom St Denis #define LB_TEST_DEBUG_INDEX__LB_TEST_DEBUG_WRITE_EN__SHIFT 0x00000008 7573de2bdb3dSTom St Denis #define LIGHT_SLEEP_CNTL__LIGHT_SLEEP_DIS_MASK 0x00000001L 7574de2bdb3dSTom St Denis #define LIGHT_SLEEP_CNTL__LIGHT_SLEEP_DIS__SHIFT 0x00000000 7575de2bdb3dSTom St Denis #define LIGHT_SLEEP_CNTL__MEM_SHUTDOWN_DIS_MASK 0x00000100L 7576de2bdb3dSTom St Denis #define LIGHT_SLEEP_CNTL__MEM_SHUTDOWN_DIS__SHIFT 0x00000008 7577de2bdb3dSTom St Denis #define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_ENABLE_MASK 0x00000001L 7578de2bdb3dSTom St Denis #define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_ENABLE__SHIFT 0x00000000 7579de2bdb3dSTom St Denis #define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_MODE_MASK 0x00000018L 7580de2bdb3dSTom St Denis #define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_MODE__SHIFT 0x00000003 7581de2bdb3dSTom St Denis #define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_NUM_BANKS_MASK 0x00000700L 7582de2bdb3dSTom St Denis #define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_NUM_BANKS__SHIFT 0x00000008 7583de2bdb3dSTom St Denis #define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_NUM_PIPES_MASK 0x000000e0L 7584de2bdb3dSTom St Denis #define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_NUM_PIPES__SHIFT 0x00000005 7585de2bdb3dSTom St Denis #define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_PIPE_INTERLEAVE_SIZE_MASK 0x00000800L 7586de2bdb3dSTom St Denis #define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_PIPE_INTERLEAVE_SIZE__SHIFT 0x0000000b 7587de2bdb3dSTom St Denis #define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_ROW_SIZE_MASK 0x00007000L 7588de2bdb3dSTom St Denis #define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_ROW_SIZE__SHIFT 0x0000000c 7589de2bdb3dSTom St Denis #define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_ROWS_PER_CHAN_MASK 0x0fff0000L 7590de2bdb3dSTom St Denis #define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_ROWS_PER_CHAN__SHIFT 0x00000010 7591de2bdb3dSTom St Denis #define LVDS_DATA_CNTL__LVDS_24BIT_ENABLE_MASK 0x00000001L 7592de2bdb3dSTom St Denis #define LVDS_DATA_CNTL__LVDS_24BIT_ENABLE__SHIFT 0x00000000 7593de2bdb3dSTom St Denis #define LVDS_DATA_CNTL__LVDS_24BIT_FORMAT_MASK 0x00000010L 7594de2bdb3dSTom St Denis #define LVDS_DATA_CNTL__LVDS_24BIT_FORMAT__SHIFT 0x00000004 7595de2bdb3dSTom St Denis #define LVDS_DATA_CNTL__LVDS_2ND_CHAN_DE_MASK 0x00000100L 7596de2bdb3dSTom St Denis #define LVDS_DATA_CNTL__LVDS_2ND_CHAN_DE__SHIFT 0x00000008 7597de2bdb3dSTom St Denis #define LVDS_DATA_CNTL__LVDS_2ND_CHAN_HS_MASK 0x00000400L 7598de2bdb3dSTom St Denis #define LVDS_DATA_CNTL__LVDS_2ND_CHAN_HS__SHIFT 0x0000000a 7599de2bdb3dSTom St Denis #define LVDS_DATA_CNTL__LVDS_2ND_CHAN_VS_MASK 0x00000200L 7600de2bdb3dSTom St Denis #define LVDS_DATA_CNTL__LVDS_2ND_CHAN_VS__SHIFT 0x00000009 7601de2bdb3dSTom St Denis #define LVDS_DATA_CNTL__LVDS_2ND_LINK_CNTL_BITS_MASK 0x00007000L 7602de2bdb3dSTom St Denis #define LVDS_DATA_CNTL__LVDS_2ND_LINK_CNTL_BITS__SHIFT 0x0000000c 7603de2bdb3dSTom St Denis #define LVDS_DATA_CNTL__LVDS_DTMG_POL_MASK 0x00040000L 7604de2bdb3dSTom St Denis #define LVDS_DATA_CNTL__LVDS_DTMG_POL__SHIFT 0x00000012 7605de2bdb3dSTom St Denis #define LVDS_DATA_CNTL__LVDS_FP_POL_MASK 0x00010000L 7606de2bdb3dSTom St Denis #define LVDS_DATA_CNTL__LVDS_FP_POL__SHIFT 0x00000010 7607de2bdb3dSTom St Denis #define LVDS_DATA_CNTL__LVDS_LP_POL_MASK 0x00020000L 7608de2bdb3dSTom St Denis #define LVDS_DATA_CNTL__LVDS_LP_POL__SHIFT 0x00000011 7609de2bdb3dSTom St Denis #define LVTMA_PWRSEQ_CNTL__LVTMA_BLON_MASK 0x01000000L 7610de2bdb3dSTom St Denis #define LVTMA_PWRSEQ_CNTL__LVTMA_BLON_OVRD_MASK 0x02000000L 7611de2bdb3dSTom St Denis #define LVTMA_PWRSEQ_CNTL__LVTMA_BLON_OVRD__SHIFT 0x00000019 7612de2bdb3dSTom St Denis #define LVTMA_PWRSEQ_CNTL__LVTMA_BLON_POL_MASK 0x04000000L 7613de2bdb3dSTom St Denis #define LVTMA_PWRSEQ_CNTL__LVTMA_BLON_POL__SHIFT 0x0000001a 7614de2bdb3dSTom St Denis #define LVTMA_PWRSEQ_CNTL__LVTMA_BLON__SHIFT 0x00000018 7615de2bdb3dSTom St Denis #define LVTMA_PWRSEQ_CNTL__LVTMA_DIGON_MASK 0x00010000L 7616de2bdb3dSTom St Denis #define LVTMA_PWRSEQ_CNTL__LVTMA_DIGON_OVRD_MASK 0x00020000L 7617de2bdb3dSTom St Denis #define LVTMA_PWRSEQ_CNTL__LVTMA_DIGON_OVRD__SHIFT 0x00000011 7618de2bdb3dSTom St Denis #define LVTMA_PWRSEQ_CNTL__LVTMA_DIGON_POL_MASK 0x00040000L 7619de2bdb3dSTom St Denis #define LVTMA_PWRSEQ_CNTL__LVTMA_DIGON_POL__SHIFT 0x00000012 7620de2bdb3dSTom St Denis #define LVTMA_PWRSEQ_CNTL__LVTMA_DIGON__SHIFT 0x00000010 7621de2bdb3dSTom St Denis #define LVTMA_PWRSEQ_CNTL__LVTMA_PWRSEQ_DISABLE_SYNCEN_CONTROL_OF_TX_EN_MASK 0x00000002L 7622de2bdb3dSTom St Denis #define LVTMA_PWRSEQ_CNTL__LVTMA_PWRSEQ_DISABLE_SYNCEN_CONTROL_OF_TX_EN__SHIFT 0x00000001 7623de2bdb3dSTom St Denis #define LVTMA_PWRSEQ_CNTL__LVTMA_PWRSEQ_EN_MASK 0x00000001L 7624de2bdb3dSTom St Denis #define LVTMA_PWRSEQ_CNTL__LVTMA_PWRSEQ_EN__SHIFT 0x00000000 7625de2bdb3dSTom St Denis #define LVTMA_PWRSEQ_CNTL__LVTMA_PWRSEQ_TARGET_STATE_MASK 0x00000010L 7626de2bdb3dSTom St Denis #define LVTMA_PWRSEQ_CNTL__LVTMA_PWRSEQ_TARGET_STATE__SHIFT 0x00000004 7627de2bdb3dSTom St Denis #define LVTMA_PWRSEQ_CNTL__LVTMA_SYNCEN_MASK 0x00000100L 7628de2bdb3dSTom St Denis #define LVTMA_PWRSEQ_CNTL__LVTMA_SYNCEN_OVRD_MASK 0x00000200L 7629de2bdb3dSTom St Denis #define LVTMA_PWRSEQ_CNTL__LVTMA_SYNCEN_OVRD__SHIFT 0x00000009 7630de2bdb3dSTom St Denis #define LVTMA_PWRSEQ_CNTL__LVTMA_SYNCEN_POL_MASK 0x00000400L 7631de2bdb3dSTom St Denis #define LVTMA_PWRSEQ_CNTL__LVTMA_SYNCEN_POL__SHIFT 0x0000000a 7632de2bdb3dSTom St Denis #define LVTMA_PWRSEQ_CNTL__LVTMA_SYNCEN__SHIFT 0x00000008 7633de2bdb3dSTom St Denis #define LVTMA_PWRSEQ_DELAY1__LVTMA_PWRDN_DELAY1_MASK 0x00ff0000L 7634de2bdb3dSTom St Denis #define LVTMA_PWRSEQ_DELAY1__LVTMA_PWRDN_DELAY1__SHIFT 0x00000010 7635de2bdb3dSTom St Denis #define LVTMA_PWRSEQ_DELAY1__LVTMA_PWRDN_DELAY2_MASK 0xff000000L 7636de2bdb3dSTom St Denis #define LVTMA_PWRSEQ_DELAY1__LVTMA_PWRDN_DELAY2__SHIFT 0x00000018 7637de2bdb3dSTom St Denis #define LVTMA_PWRSEQ_DELAY1__LVTMA_PWRUP_DELAY1_MASK 0x000000ffL 7638de2bdb3dSTom St Denis #define LVTMA_PWRSEQ_DELAY1__LVTMA_PWRUP_DELAY1__SHIFT 0x00000000 7639de2bdb3dSTom St Denis #define LVTMA_PWRSEQ_DELAY1__LVTMA_PWRUP_DELAY2_MASK 0x0000ff00L 7640de2bdb3dSTom St Denis #define LVTMA_PWRSEQ_DELAY1__LVTMA_PWRUP_DELAY2__SHIFT 0x00000008 7641de2bdb3dSTom St Denis #define LVTMA_PWRSEQ_DELAY2__LVTMA_PWRDN_DELAY3_MASK 0x00ff0000L 7642de2bdb3dSTom St Denis #define LVTMA_PWRSEQ_DELAY2__LVTMA_PWRDN_DELAY3__SHIFT 0x00000010 7643de2bdb3dSTom St Denis #define LVTMA_PWRSEQ_DELAY2__LVTMA_PWRDN_MIN_LENGTH_MASK 0x000000ffL 7644de2bdb3dSTom St Denis #define LVTMA_PWRSEQ_DELAY2__LVTMA_PWRDN_MIN_LENGTH__SHIFT 0x00000000 7645de2bdb3dSTom St Denis #define LVTMA_PWRSEQ_DELAY2__LVTMA_PWRUP_DELAY3_MASK 0x0000ff00L 7646de2bdb3dSTom St Denis #define LVTMA_PWRSEQ_DELAY2__LVTMA_PWRUP_DELAY3__SHIFT 0x00000008 7647de2bdb3dSTom St Denis #define LVTMA_PWRSEQ_DELAY2__LVTMA_VARY_BL_OVERRIDE_EN_MASK 0x01000000L 7648de2bdb3dSTom St Denis #define LVTMA_PWRSEQ_DELAY2__LVTMA_VARY_BL_OVERRIDE_EN__SHIFT 0x00000018 7649de2bdb3dSTom St Denis #define LVTMA_PWRSEQ_REF_DIV__BL_PWM_REF_DIV_MASK 0xffff0000L 7650de2bdb3dSTom St Denis #define LVTMA_PWRSEQ_REF_DIV__BL_PWM_REF_DIV__SHIFT 0x00000010 7651de2bdb3dSTom St Denis #define LVTMA_PWRSEQ_REF_DIV__LVTMA_PWRSEQ_REF_DIV_MASK 0x00000fffL 7652de2bdb3dSTom St Denis #define LVTMA_PWRSEQ_REF_DIV__LVTMA_PWRSEQ_REF_DIV__SHIFT 0x00000000 7653de2bdb3dSTom St Denis #define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_BLON_MASK 0x00000008L 7654de2bdb3dSTom St Denis #define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_BLON__SHIFT 0x00000003 7655de2bdb3dSTom St Denis #define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_DIGON_MASK 0x00000002L 7656de2bdb3dSTom St Denis #define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_DIGON__SHIFT 0x00000001 7657de2bdb3dSTom St Denis #define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_DONE_MASK 0x00000010L 7658de2bdb3dSTom St Denis #define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_DONE__SHIFT 0x00000004 7659de2bdb3dSTom St Denis #define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_STATE_MASK 0x00000f00L 7660de2bdb3dSTom St Denis #define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_STATE__SHIFT 0x00000008 7661de2bdb3dSTom St Denis #define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_SYNCEN_MASK 0x00000004L 7662de2bdb3dSTom St Denis #define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_SYNCEN__SHIFT 0x00000002 7663de2bdb3dSTom St Denis #define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_TARGET_STATE_R_MASK 0x00000001L 7664de2bdb3dSTom St Denis #define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_TARGET_STATE_R__SHIFT 0x00000000 7665de2bdb3dSTom St Denis #define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE0_MASK 0x000000ffL 7666de2bdb3dSTom St Denis #define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE0__SHIFT 0x00000000 7667de2bdb3dSTom St Denis #define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE1_MASK 0x0000ff00L 7668de2bdb3dSTom St Denis #define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE1__SHIFT 0x00000008 7669de2bdb3dSTom St Denis #define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE2_MASK 0x00ff0000L 7670de2bdb3dSTom St Denis #define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE2__SHIFT 0x00000010 7671de2bdb3dSTom St Denis #define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE3_MASK 0xff000000L 7672de2bdb3dSTom St Denis #define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE3__SHIFT 0x00000018 7673de2bdb3dSTom St Denis #define MASTER_COMM_CNTL_REG__MASTER_COMM_INTERRUPT_MASK 0x00000001L 7674de2bdb3dSTom St Denis #define MASTER_COMM_CNTL_REG__MASTER_COMM_INTERRUPT__SHIFT 0x00000000 7675de2bdb3dSTom St Denis #define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE0_MASK 0x000000ffL 7676de2bdb3dSTom St Denis #define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE0__SHIFT 0x00000000 7677de2bdb3dSTom St Denis #define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE1_MASK 0x0000ff00L 7678de2bdb3dSTom St Denis #define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE1__SHIFT 0x00000008 7679de2bdb3dSTom St Denis #define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE2_MASK 0x00ff0000L 7680de2bdb3dSTom St Denis #define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE2__SHIFT 0x00000010 7681de2bdb3dSTom St Denis #define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE3_MASK 0xff000000L 7682de2bdb3dSTom St Denis #define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE3__SHIFT 0x00000018 7683de2bdb3dSTom St Denis #define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE0_MASK 0x000000ffL 7684de2bdb3dSTom St Denis #define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE0__SHIFT 0x00000000 7685de2bdb3dSTom St Denis #define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE1_MASK 0x0000ff00L 7686de2bdb3dSTom St Denis #define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE1__SHIFT 0x00000008 7687de2bdb3dSTom St Denis #define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE2_MASK 0x00ff0000L 7688de2bdb3dSTom St Denis #define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE2__SHIFT 0x00000010 7689de2bdb3dSTom St Denis #define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE3_MASK 0xff000000L 7690de2bdb3dSTom St Denis #define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE3__SHIFT 0x00000018 7691de2bdb3dSTom St Denis #define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE0_MASK 0x000000ffL 7692de2bdb3dSTom St Denis #define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE0__SHIFT 0x00000000 7693de2bdb3dSTom St Denis #define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE1_MASK 0x0000ff00L 7694de2bdb3dSTom St Denis #define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE1__SHIFT 0x00000008 7695de2bdb3dSTom St Denis #define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE2_MASK 0x00ff0000L 7696de2bdb3dSTom St Denis #define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE2__SHIFT 0x00000010 7697de2bdb3dSTom St Denis #define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE3_MASK 0xff000000L 7698de2bdb3dSTom St Denis #define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE3__SHIFT 0x00000018 7699de2bdb3dSTom St Denis #define MASTER_UPDATE_LOCK__GSL_CONTROL_MASTER_UPDATE_LOCK_MASK 0x00000100L 7700de2bdb3dSTom St Denis #define MASTER_UPDATE_LOCK__GSL_CONTROL_MASTER_UPDATE_LOCK__SHIFT 0x00000008 7701de2bdb3dSTom St Denis #define MASTER_UPDATE_LOCK__MASTER_UPDATE_LOCK_MASK 0x00000001L 7702de2bdb3dSTom St Denis #define MASTER_UPDATE_LOCK__MASTER_UPDATE_LOCK__SHIFT 0x00000000 7703de2bdb3dSTom St Denis #define MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE_MASK 0x00030000L 7704de2bdb3dSTom St Denis #define MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE__SHIFT 0x00000010 7705de2bdb3dSTom St Denis #define MASTER_UPDATE_MODE__MASTER_UPDATE_MODE_MASK 0x00000007L 7706de2bdb3dSTom St Denis #define MASTER_UPDATE_MODE__MASTER_UPDATE_MODE__SHIFT 0x00000000 7707de2bdb3dSTom St Denis #define MC_DC_INTERFACE_NACK_STATUS__DMIF_RDRET_NACK_CLEAR_MASK 0x00000010L 7708de2bdb3dSTom St Denis #define MC_DC_INTERFACE_NACK_STATUS__DMIF_RDRET_NACK_CLEAR__SHIFT 0x00000004 7709de2bdb3dSTom St Denis #define MC_DC_INTERFACE_NACK_STATUS__DMIF_RDRET_NACK_OCCURRED_MASK 0x00000001L 7710de2bdb3dSTom St Denis #define MC_DC_INTERFACE_NACK_STATUS__DMIF_RDRET_NACK_OCCURRED__SHIFT 0x00000000 7711de2bdb3dSTom St Denis #define MC_DC_INTERFACE_NACK_STATUS__MCIF_RDRET_NACK_CLEAR_MASK 0x00100000L 7712de2bdb3dSTom St Denis #define MC_DC_INTERFACE_NACK_STATUS__MCIF_RDRET_NACK_CLEAR__SHIFT 0x00000014 7713de2bdb3dSTom St Denis #define MC_DC_INTERFACE_NACK_STATUS__MCIF_RDRET_NACK_OCCURRED_MASK 0x00010000L 7714de2bdb3dSTom St Denis #define MC_DC_INTERFACE_NACK_STATUS__MCIF_RDRET_NACK_OCCURRED__SHIFT 0x00000010 7715de2bdb3dSTom St Denis #define MC_DC_INTERFACE_NACK_STATUS__MCIF_WRRET_NACK_CLEAR_MASK 0x10000000L 7716de2bdb3dSTom St Denis #define MC_DC_INTERFACE_NACK_STATUS__MCIF_WRRET_NACK_CLEAR__SHIFT 0x0000001c 7717de2bdb3dSTom St Denis #define MC_DC_INTERFACE_NACK_STATUS__MCIF_WRRET_NACK_OCCURRED_MASK 0x01000000L 7718de2bdb3dSTom St Denis #define MC_DC_INTERFACE_NACK_STATUS__MCIF_WRRET_NACK_OCCURRED__SHIFT 0x00000018 7719de2bdb3dSTom St Denis #define MC_DC_INTERFACE_NACK_STATUS__VIP_WRRET_NACK_CLEAR_MASK 0x00001000L 7720de2bdb3dSTom St Denis #define MC_DC_INTERFACE_NACK_STATUS__VIP_WRRET_NACK_CLEAR__SHIFT 0x0000000c 7721de2bdb3dSTom St Denis #define MC_DC_INTERFACE_NACK_STATUS__VIP_WRRET_NACK_OCCURRED_MASK 0x00000100L 7722de2bdb3dSTom St Denis #define MC_DC_INTERFACE_NACK_STATUS__VIP_WRRET_NACK_OCCURRED__SHIFT 0x00000008 7723de2bdb3dSTom St Denis #define MCIF_CONTROL__ADDRESS_TRANSLATION_ENABLE_MASK 0x00000010L 7724de2bdb3dSTom St Denis #define MCIF_CONTROL__ADDRESS_TRANSLATION_ENABLE__SHIFT 0x00000004 7725de2bdb3dSTom St Denis #define MCIF_CONTROL__LOW_READ_URG_LEVEL_MASK 0x00ff0000L 7726de2bdb3dSTom St Denis #define MCIF_CONTROL__LOW_READ_URG_LEVEL__SHIFT 0x00000010 7727de2bdb3dSTom St Denis #define MCIF_CONTROL__MC_CLEAN_DEASSERT_LATENCY_MASK 0x3f000000L 7728de2bdb3dSTom St Denis #define MCIF_CONTROL__MC_CLEAN_DEASSERT_LATENCY__SHIFT 0x00000018 7729de2bdb3dSTom St Denis #define MCIF_CONTROL__MCIF_BUFF_SIZE_MASK 0x00000003L 7730de2bdb3dSTom St Denis #define MCIF_CONTROL__MCIF_BUFF_SIZE__SHIFT 0x00000000 7731de2bdb3dSTom St Denis #define MCIF_CONTROL__MCIF_MC_LATENCY_COUNTER_ENABLE_MASK 0x40000000L 7732de2bdb3dSTom St Denis #define MCIF_CONTROL__MCIF_MC_LATENCY_COUNTER_ENABLE__SHIFT 0x0000001e 7733de2bdb3dSTom St Denis #define MCIF_CONTROL__MCIF_MC_LATENCY_COUNTER_URGENT_ONLY_MASK 0x80000000L 7734de2bdb3dSTom St Denis #define MCIF_CONTROL__MCIF_MC_LATENCY_COUNTER_URGENT_ONLY__SHIFT 0x0000001f 7735de2bdb3dSTom St Denis #define MCIF_CONTROL__MCIF_SLOW_REQ_INTERVAL_MASK 0x0000f000L 7736de2bdb3dSTom St Denis #define MCIF_CONTROL__MCIF_SLOW_REQ_INTERVAL__SHIFT 0x0000000c 7737de2bdb3dSTom St Denis #define MCIF_CONTROL__PRIVILEGED_ACCESS_ENABLE_MASK 0x00000100L 7738de2bdb3dSTom St Denis #define MCIF_CONTROL__PRIVILEGED_ACCESS_ENABLE__SHIFT 0x00000008 7739de2bdb3dSTom St Denis #define MCIF_MEM_CONTROL__MCIFMEM_CACHE_MODE_DIS_MASK 0x00000001L 7740de2bdb3dSTom St Denis #define MCIF_MEM_CONTROL__MCIFMEM_CACHE_MODE_DIS__SHIFT 0x00000000 7741de2bdb3dSTom St Denis #define MCIF_MEM_CONTROL__MCIFMEM_CACHE_MODE_MASK 0x00000030L 7742de2bdb3dSTom St Denis #define MCIF_MEM_CONTROL__MCIFMEM_CACHE_MODE__SHIFT 0x00000004 7743de2bdb3dSTom St Denis #define MCIF_MEM_CONTROL__MCIFMEM_CACHE_PIPE_MASK 0x00070000L 7744de2bdb3dSTom St Denis #define MCIF_MEM_CONTROL__MCIFMEM_CACHE_PIPE__SHIFT 0x00000010 7745de2bdb3dSTom St Denis #define MCIF_MEM_CONTROL__MCIFMEM_CACHE_SIZE_MASK 0x00007f00L 7746de2bdb3dSTom St Denis #define MCIF_MEM_CONTROL__MCIFMEM_CACHE_SIZE__SHIFT 0x00000008 7747de2bdb3dSTom St Denis #define MCIF_MEM_CONTROL__MCIFMEM_CACHE_TYPE_MASK 0x00180000L 7748de2bdb3dSTom St Denis #define MCIF_MEM_CONTROL__MCIFMEM_CACHE_TYPE__SHIFT 0x00000013 7749de2bdb3dSTom St Denis #define MCIF_TEST_DEBUG_DATA__MCIF_TEST_DEBUG_DATA_MASK 0xffffffffL 7750de2bdb3dSTom St Denis #define MCIF_TEST_DEBUG_DATA__MCIF_TEST_DEBUG_DATA__SHIFT 0x00000000 7751de2bdb3dSTom St Denis #define MCIF_TEST_DEBUG_INDEX__MCIF_TEST_DEBUG_INDEX_MASK 0x000000ffL 7752de2bdb3dSTom St Denis #define MCIF_TEST_DEBUG_INDEX__MCIF_TEST_DEBUG_INDEX__SHIFT 0x00000000 7753de2bdb3dSTom St Denis #define MCIF_TEST_DEBUG_INDEX__MCIF_TEST_DEBUG_WRITE_EN_MASK 0x00000100L 7754de2bdb3dSTom St Denis #define MCIF_TEST_DEBUG_INDEX__MCIF_TEST_DEBUG_WRITE_EN__SHIFT 0x00000008 7755de2bdb3dSTom St Denis #define MCIF_VMID__MCIF_WR_VMID_MASK 0x0000000fL 7756de2bdb3dSTom St Denis #define MCIF_VMID__MCIF_WR_VMID__SHIFT 0x00000000 7757de2bdb3dSTom St Denis #define MCIF_VMID__VIP_WR_VMID_MASK 0x000000f0L 7758de2bdb3dSTom St Denis #define MCIF_VMID__VIP_WR_VMID__SHIFT 0x00000004 7759de2bdb3dSTom St Denis #define MCIF_WRITE_COMBINE_CONTROL__MCIF_WRITE_COMBINE_TIMEOUT_MASK 0x000000ffL 7760de2bdb3dSTom St Denis #define MCIF_WRITE_COMBINE_CONTROL__MCIF_WRITE_COMBINE_TIMEOUT__SHIFT 0x00000000 7761de2bdb3dSTom St Denis #define MCIF_WRITE_COMBINE_CONTROL__VIP_WRITE_COMBINE_TIMEOUT_MASK 0x0000ff00L 7762de2bdb3dSTom St Denis #define MCIF_WRITE_COMBINE_CONTROL__VIP_WRITE_COMBINE_TIMEOUT__SHIFT 0x00000008 7763de2bdb3dSTom St Denis #define MICROSECOND_TIME_BASE_DIV__MICROSECOND_TIME_BASE_CLOCK_SOURCE_SEL_MASK 0x00100000L 7764de2bdb3dSTom St Denis #define MICROSECOND_TIME_BASE_DIV__MICROSECOND_TIME_BASE_CLOCK_SOURCE_SEL__SHIFT 0x00000014 7765de2bdb3dSTom St Denis #define MICROSECOND_TIME_BASE_DIV__MICROSECOND_TIME_BASE_DIV_MASK 0x0000007fL 7766de2bdb3dSTom St Denis #define MICROSECOND_TIME_BASE_DIV__MICROSECOND_TIME_BASE_DIV__SHIFT 0x00000000 7767de2bdb3dSTom St Denis #define MICROSECOND_TIME_BASE_DIV__XTAL_REF_CLOCK_SOURCE_SEL_MASK 0x00020000L 7768de2bdb3dSTom St Denis #define MICROSECOND_TIME_BASE_DIV__XTAL_REF_CLOCK_SOURCE_SEL__SHIFT 0x00000011 7769de2bdb3dSTom St Denis #define MICROSECOND_TIME_BASE_DIV__XTAL_REF_DIV_MASK 0x00007f00L 7770de2bdb3dSTom St Denis #define MICROSECOND_TIME_BASE_DIV__XTAL_REF_DIV__SHIFT 0x00000008 7771de2bdb3dSTom St Denis #define MICROSECOND_TIME_BASE_DIV__XTAL_REF_SEL_MASK 0x00010000L 7772de2bdb3dSTom St Denis #define MICROSECOND_TIME_BASE_DIV__XTAL_REF_SEL__SHIFT 0x00000010 7773de2bdb3dSTom St Denis #define MILLISECOND_TIME_BASE_DIV__MILLISECOND_TIME_BASE_CLOCK_SOURCE_SEL_MASK 0x00100000L 7774de2bdb3dSTom St Denis #define MILLISECOND_TIME_BASE_DIV__MILLISECOND_TIME_BASE_CLOCK_SOURCE_SEL__SHIFT 0x00000014 7775de2bdb3dSTom St Denis #define MILLISECOND_TIME_BASE_DIV__MILLISECOND_TIME_BASE_DIV_MASK 0x0001ffffL 7776de2bdb3dSTom St Denis #define MILLISECOND_TIME_BASE_DIV__MILLISECOND_TIME_BASE_DIV__SHIFT 0x00000000 7777de2bdb3dSTom St Denis #define MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_NUM_ENTRIES_MASK 0x0000000fL 7778de2bdb3dSTom St Denis #define MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_NUM_ENTRIES__SHIFT 0x00000000 7779de2bdb3dSTom St Denis #define MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_RESET_ACK_MASK 0x00001000L 7780de2bdb3dSTom St Denis #define MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_RESET_ACK__SHIFT 0x0000000c 7781de2bdb3dSTom St Denis #define MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_RESET_FLAG_MASK 0x00000100L 7782de2bdb3dSTom St Denis #define MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_RESET_FLAG__SHIFT 0x00000008 7783de2bdb3dSTom St Denis #define MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_RESET_MASK 0x00000010L 7784de2bdb3dSTom St Denis #define MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_RESET__SHIFT 0x00000004 7785de2bdb3dSTom St Denis #define MVP_AFR_FLIP_MODE__MVP_AFR_FLIP_MODE_MASK 0x00000003L 7786de2bdb3dSTom St Denis #define MVP_AFR_FLIP_MODE__MVP_AFR_FLIP_MODE__SHIFT 0x00000000 7787de2bdb3dSTom St Denis #define MVP_BLACK_KEYER__MVP_BLACK_KEYER_B_MASK 0x3ff00000L 7788de2bdb3dSTom St Denis #define MVP_BLACK_KEYER__MVP_BLACK_KEYER_B__SHIFT 0x00000014 7789de2bdb3dSTom St Denis #define MVP_BLACK_KEYER__MVP_BLACK_KEYER_G_MASK 0x000ffc00L 7790de2bdb3dSTom St Denis #define MVP_BLACK_KEYER__MVP_BLACK_KEYER_G__SHIFT 0x0000000a 7791de2bdb3dSTom St Denis #define MVP_BLACK_KEYER__MVP_BLACK_KEYER_R_MASK 0x000003ffL 7792de2bdb3dSTom St Denis #define MVP_BLACK_KEYER__MVP_BLACK_KEYER_R__SHIFT 0x00000000 7793de2bdb3dSTom St Denis #define MVP_CONTROL1__MVP_30BPP_EN_MASK 0x10000000L 7794de2bdb3dSTom St Denis #define MVP_CONTROL1__MVP_30BPP_EN__SHIFT 0x0000001c 7795de2bdb3dSTom St Denis #define MVP_CONTROL1__MVP_ARBITRATION_MODE_FOR_AFR_MANUAL_SWITCH_MODE_MASK 0x00000400L 7796de2bdb3dSTom St Denis #define MVP_CONTROL1__MVP_ARBITRATION_MODE_FOR_AFR_MANUAL_SWITCH_MODE__SHIFT 0x0000000a 7797de2bdb3dSTom St Denis #define MVP_CONTROL1__MVP_CHANNEL_CONTROL_MASK 0x00010000L 7798de2bdb3dSTom St Denis #define MVP_CONTROL1__MVP_CHANNEL_CONTROL__SHIFT 0x00000010 7799de2bdb3dSTom St Denis #define MVP_CONTROL1__MVP_DISABLE_MSB_EXPAND_MASK 0x01000000L 7800de2bdb3dSTom St Denis #define MVP_CONTROL1__MVP_DISABLE_MSB_EXPAND__SHIFT 0x00000018 7801de2bdb3dSTom St Denis #define MVP_CONTROL1__MVP_EN_MASK 0x00000001L 7802de2bdb3dSTom St Denis #define MVP_CONTROL1__MVP_EN__SHIFT 0x00000000 7803de2bdb3dSTom St Denis #define MVP_CONTROL1__MVP_GPU_CHAIN_LOCATION_MASK 0x00300000L 7804de2bdb3dSTom St Denis #define MVP_CONTROL1__MVP_GPU_CHAIN_LOCATION__SHIFT 0x00000014 7805de2bdb3dSTom St Denis #define MVP_CONTROL1__MVP_MIXER_MODE_MASK 0x00000070L 7806de2bdb3dSTom St Denis #define MVP_CONTROL1__MVP_MIXER_MODE__SHIFT 0x00000004 7807de2bdb3dSTom St Denis #define MVP_CONTROL1__MVP_MIXER_SLAVE_SEL_DELAY_UNTIL_END_OF_BLANK_MASK 0x00000200L 7808de2bdb3dSTom St Denis #define MVP_CONTROL1__MVP_MIXER_SLAVE_SEL_DELAY_UNTIL_END_OF_BLANK__SHIFT 0x00000009 7809de2bdb3dSTom St Denis #define MVP_CONTROL1__MVP_MIXER_SLAVE_SEL_MASK 0x00000100L 7810de2bdb3dSTom St Denis #define MVP_CONTROL1__MVP_MIXER_SLAVE_SEL__SHIFT 0x00000008 7811de2bdb3dSTom St Denis #define MVP_CONTROL1__MVP_RATE_CONTROL_MASK 0x00001000L 7812de2bdb3dSTom St Denis #define MVP_CONTROL1__MVP_RATE_CONTROL__SHIFT 0x0000000c 7813de2bdb3dSTom St Denis #define MVP_CONTROL1__MVP_TERMINATION_CNTL_A_MASK 0x40000000L 7814de2bdb3dSTom St Denis #define MVP_CONTROL1__MVP_TERMINATION_CNTL_A__SHIFT 0x0000001e 7815de2bdb3dSTom St Denis #define MVP_CONTROL1__MVP_TERMINATION_CNTL_B_MASK 0x80000000L 7816de2bdb3dSTom St Denis #define MVP_CONTROL1__MVP_TERMINATION_CNTL_B__SHIFT 0x0000001f 7817de2bdb3dSTom St Denis #define MVP_CONTROL2__MVP_DVOCNTL_MUX_MASK 0x00010000L 7818de2bdb3dSTom St Denis #define MVP_CONTROL2__MVP_DVOCNTL_MUX__SHIFT 0x00000010 7819de2bdb3dSTom St Denis #define MVP_CONTROL2__MVP_FLOW_CONTROL_OUT_EN_MASK 0x00100000L 7820de2bdb3dSTom St Denis #define MVP_CONTROL2__MVP_FLOW_CONTROL_OUT_EN__SHIFT 0x00000014 7821de2bdb3dSTom St Denis #define MVP_CONTROL2__MVP_MUXA_CLK_SEL_MASK 0x00000100L 7822de2bdb3dSTom St Denis #define MVP_CONTROL2__MVP_MUXA_CLK_SEL__SHIFT 0x00000008 7823de2bdb3dSTom St Denis #define MVP_CONTROL2__MVP_MUXB_CLK_SEL_MASK 0x00001000L 7824de2bdb3dSTom St Denis #define MVP_CONTROL2__MVP_MUXB_CLK_SEL__SHIFT 0x0000000c 7825de2bdb3dSTom St Denis #define MVP_CONTROL2__MVP_MUX_DE_DVOCNTL0_SEL_MASK 0x00000001L 7826de2bdb3dSTom St Denis #define MVP_CONTROL2__MVP_MUX_DE_DVOCNTL0_SEL__SHIFT 0x00000000 7827de2bdb3dSTom St Denis #define MVP_CONTROL2__MVP_MUX_DE_DVOCNTL2_SEL_MASK 0x00000010L 7828de2bdb3dSTom St Denis #define MVP_CONTROL2__MVP_MUX_DE_DVOCNTL2_SEL__SHIFT 0x00000004 7829de2bdb3dSTom St Denis #define MVP_CONTROL2__MVP_SWAP_AB_IN_DC_DDR_MASK 0x10000000L 7830de2bdb3dSTom St Denis #define MVP_CONTROL2__MVP_SWAP_AB_IN_DC_DDR__SHIFT 0x0000001c 7831de2bdb3dSTom St Denis #define MVP_CONTROL2__MVP_SWAP_LOCK_OUT_EN_MASK 0x01000000L 7832de2bdb3dSTom St Denis #define MVP_CONTROL2__MVP_SWAP_LOCK_OUT_EN__SHIFT 0x00000018 7833de2bdb3dSTom St Denis #define MVP_CONTROL3__MVP_DDR_SC_AB_SEL_MASK 0x00000010L 7834de2bdb3dSTom St Denis #define MVP_CONTROL3__MVP_DDR_SC_AB_SEL__SHIFT 0x00000004 7835de2bdb3dSTom St Denis #define MVP_CONTROL3__MVP_DDR_SC_B_START_MODE_MASK 0x00000100L 7836de2bdb3dSTom St Denis #define MVP_CONTROL3__MVP_DDR_SC_B_START_MODE__SHIFT 0x00000008 7837de2bdb3dSTom St Denis #define MVP_CONTROL3__MVP_FLOW_CONTROL_CASCADE_EN_MASK 0x00100000L 7838de2bdb3dSTom St Denis #define MVP_CONTROL3__MVP_FLOW_CONTROL_CASCADE_EN__SHIFT 0x00000014 7839de2bdb3dSTom St Denis #define MVP_CONTROL3__MVP_FLOW_CONTROL_IN_CAP_MASK 0x10000000L 7840de2bdb3dSTom St Denis #define MVP_CONTROL3__MVP_FLOW_CONTROL_IN_CAP__SHIFT 0x0000001c 7841de2bdb3dSTom St Denis #define MVP_CONTROL3__MVP_FLOW_CONTROL_OUT_FORCE_ONE_MASK 0x00001000L 7842de2bdb3dSTom St Denis #define MVP_CONTROL3__MVP_FLOW_CONTROL_OUT_FORCE_ONE__SHIFT 0x0000000c 7843de2bdb3dSTom St Denis #define MVP_CONTROL3__MVP_FLOW_CONTROL_OUT_FORCE_ZERO_MASK 0x00010000L 7844de2bdb3dSTom St Denis #define MVP_CONTROL3__MVP_FLOW_CONTROL_OUT_FORCE_ZERO__SHIFT 0x00000010 7845de2bdb3dSTom St Denis #define MVP_CONTROL3__MVP_RESET_IN_BETWEEN_FRAMES_MASK 0x00000001L 7846de2bdb3dSTom St Denis #define MVP_CONTROL3__MVP_RESET_IN_BETWEEN_FRAMES__SHIFT 0x00000000 7847de2bdb3dSTom St Denis #define MVP_CONTROL3__MVP_SWAP_48BIT_EN_MASK 0x01000000L 7848de2bdb3dSTom St Denis #define MVP_CONTROL3__MVP_SWAP_48BIT_EN__SHIFT 0x00000018 7849de2bdb3dSTom St Denis #define MVP_CRC_CNTL__MVP_CRC_BLUE_MASK_MASK 0x000000ffL 7850de2bdb3dSTom St Denis #define MVP_CRC_CNTL__MVP_CRC_BLUE_MASK__SHIFT 0x00000000 7851de2bdb3dSTom St Denis #define MVP_CRC_CNTL__MVP_CRC_CONT_EN_MASK 0x20000000L 7852de2bdb3dSTom St Denis #define MVP_CRC_CNTL__MVP_CRC_CONT_EN__SHIFT 0x0000001d 7853de2bdb3dSTom St Denis #define MVP_CRC_CNTL__MVP_CRC_EN_MASK 0x10000000L 7854de2bdb3dSTom St Denis #define MVP_CRC_CNTL__MVP_CRC_EN__SHIFT 0x0000001c 7855de2bdb3dSTom St Denis #define MVP_CRC_CNTL__MVP_CRC_GREEN_MASK_MASK 0x0000ff00L 7856de2bdb3dSTom St Denis #define MVP_CRC_CNTL__MVP_CRC_GREEN_MASK__SHIFT 0x00000008 7857de2bdb3dSTom St Denis #define MVP_CRC_CNTL__MVP_CRC_RED_MASK_MASK 0x00ff0000L 7858de2bdb3dSTom St Denis #define MVP_CRC_CNTL__MVP_CRC_RED_MASK__SHIFT 0x00000010 7859de2bdb3dSTom St Denis #define MVP_CRC_CNTL__MVP_DC_DDR_CRC_EVEN_ODD_PIX_SEL_MASK 0x40000000L 7860de2bdb3dSTom St Denis #define MVP_CRC_CNTL__MVP_DC_DDR_CRC_EVEN_ODD_PIX_SEL__SHIFT 0x0000001e 7861de2bdb3dSTom St Denis #define MVP_CRC_RESULT_BLUE_GREEN__MVP_CRC_BLUE_RESULT_MASK 0x0000ffffL 7862de2bdb3dSTom St Denis #define MVP_CRC_RESULT_BLUE_GREEN__MVP_CRC_BLUE_RESULT__SHIFT 0x00000000 7863de2bdb3dSTom St Denis #define MVP_CRC_RESULT_BLUE_GREEN__MVP_CRC_GREEN_RESULT_MASK 0xffff0000L 7864de2bdb3dSTom St Denis #define MVP_CRC_RESULT_BLUE_GREEN__MVP_CRC_GREEN_RESULT__SHIFT 0x00000010 7865de2bdb3dSTom St Denis #define MVP_CRC_RESULT_RED__MVP_CRC_RED_RESULT_MASK 0x0000ffffL 7866de2bdb3dSTom St Denis #define MVP_CRC_RESULT_RED__MVP_CRC_RED_RESULT__SHIFT 0x00000000 7867de2bdb3dSTom St Denis #define MVP_DEBUG_05__IDE0_MVP_GPU_CHAIN_LOCATION_MASK 0x00000006L 7868de2bdb3dSTom St Denis #define MVP_DEBUG_05__IDE0_MVP_GPU_CHAIN_LOCATION__SHIFT 0x00000001 7869de2bdb3dSTom St Denis #define MVP_DEBUG_09__IDE4_CRTC2_MVP_GPU_CHAIN_LOCATION_MASK 0x00000006L 7870de2bdb3dSTom St Denis #define MVP_DEBUG_09__IDE4_CRTC2_MVP_GPU_CHAIN_LOCATION__SHIFT 0x00000001 7871de2bdb3dSTom St Denis #define MVP_DEBUG_12__IDEC_MVP_DATA_A_H_MASK 0x00000001L 7872de2bdb3dSTom St Denis #define MVP_DEBUG_12__IDEC_MVP_DATA_A_H__SHIFT 0x00000000 7873de2bdb3dSTom St Denis #define MVP_DEBUG_12__IDEC_MVP_DATA_A_MASK 0x01fffffeL 7874de2bdb3dSTom St Denis #define MVP_DEBUG_12__IDEC_MVP_DATA_A__SHIFT 0x00000001 7875de2bdb3dSTom St Denis #define MVP_DEBUG_13__IDED_MVP_DATA_B_H_MASK 0x00000001L 7876de2bdb3dSTom St Denis #define MVP_DEBUG_13__IDED_MVP_DATA_B_H__SHIFT 0x00000000 7877de2bdb3dSTom St Denis #define MVP_DEBUG_13__IDED_MVP_DATA_B_MASK 0x01fffffeL 7878de2bdb3dSTom St Denis #define MVP_DEBUG_13__IDED_MVP_DATA_B__SHIFT 0x00000001 7879de2bdb3dSTom St Denis #define MVP_DEBUG_13__IDED_READ_FIFO_ENTRY_DE_B_MASK 0x04000000L 7880de2bdb3dSTom St Denis #define MVP_DEBUG_13__IDED_READ_FIFO_ENTRY_DE_B__SHIFT 0x0000001a 7881de2bdb3dSTom St Denis #define MVP_DEBUG_13__IDED_START_READ_B_MASK 0x02000000L 7882de2bdb3dSTom St Denis #define MVP_DEBUG_13__IDED_START_READ_B__SHIFT 0x00000019 7883de2bdb3dSTom St Denis #define MVP_DEBUG_13__IDED_WRITE_ADD_B_MASK 0x38000000L 7884de2bdb3dSTom St Denis #define MVP_DEBUG_13__IDED_WRITE_ADD_B__SHIFT 0x0000001b 7885de2bdb3dSTom St Denis #define MVP_DEBUG_14__IDEE_CRC_PHASE_MASK 0x00100000L 7886de2bdb3dSTom St Denis #define MVP_DEBUG_14__IDEE_CRC_PHASE__SHIFT 0x00000014 7887de2bdb3dSTom St Denis #define MVP_DEBUG_14__IDEE_CRTC1_CNTL_CAPTURE_START_A_MASK 0x00080000L 7888de2bdb3dSTom St Denis #define MVP_DEBUG_14__IDEE_CRTC1_CNTL_CAPTURE_START_A__SHIFT 0x00000013 7889de2bdb3dSTom St Denis #define MVP_DEBUG_14__IDEE_READ_ADD_MASK 0x00000007L 7890de2bdb3dSTom St Denis #define MVP_DEBUG_14__IDEE_READ_ADD__SHIFT 0x00000000 7891de2bdb3dSTom St Denis #define MVP_DEBUG_14__IDEE_READ_FIFO_DE_B_MASK 0x00020000L 7892de2bdb3dSTom St Denis #define MVP_DEBUG_14__IDEE_READ_FIFO_DE_B__SHIFT 0x00000011 7893de2bdb3dSTom St Denis #define MVP_DEBUG_14__IDEE_READ_FIFO_DE_MASK 0x00010000L 7894de2bdb3dSTom St Denis #define MVP_DEBUG_14__IDEE_READ_FIFO_DE__SHIFT 0x00000010 7895de2bdb3dSTom St Denis #define MVP_DEBUG_14__IDEE_READ_FIFO_ENABLE_MASK 0x00040000L 7896de2bdb3dSTom St Denis #define MVP_DEBUG_14__IDEE_READ_FIFO_ENABLE__SHIFT 0x00000012 7897de2bdb3dSTom St Denis #define MVP_DEBUG_14__IDEE_READ_FIFO_ENTRY_DE_B_MASK 0x00008000L 7898de2bdb3dSTom St Denis #define MVP_DEBUG_14__IDEE_READ_FIFO_ENTRY_DE_B__SHIFT 0x0000000f 7899de2bdb3dSTom St Denis #define MVP_DEBUG_14__IDEE_READ_FIFO_ENTRY_DE_MASK 0x00004000L 7900de2bdb3dSTom St Denis #define MVP_DEBUG_14__IDEE_READ_FIFO_ENTRY_DE__SHIFT 0x0000000e 7901de2bdb3dSTom St Denis #define MVP_DEBUG_14__IDEE_START_INCR_WR_A_MASK 0x00000800L 7902de2bdb3dSTom St Denis #define MVP_DEBUG_14__IDEE_START_INCR_WR_A__SHIFT 0x0000000b 7903de2bdb3dSTom St Denis #define MVP_DEBUG_14__IDEE_START_INCR_WR_B_MASK 0x00001000L 7904de2bdb3dSTom St Denis #define MVP_DEBUG_14__IDEE_START_INCR_WR_B__SHIFT 0x0000000c 7905de2bdb3dSTom St Denis #define MVP_DEBUG_14__IDEE_START_READ_B_MASK 0x00000400L 7906de2bdb3dSTom St Denis #define MVP_DEBUG_14__IDEE_START_READ_B__SHIFT 0x0000000a 7907de2bdb3dSTom St Denis #define MVP_DEBUG_14__IDEE_START_READ_MASK 0x00000200L 7908de2bdb3dSTom St Denis #define MVP_DEBUG_14__IDEE_START_READ__SHIFT 0x00000009 7909de2bdb3dSTom St Denis #define MVP_DEBUG_14__IDEE_WRITE2FIFO_MASK 0x00002000L 7910de2bdb3dSTom St Denis #define MVP_DEBUG_14__IDEE_WRITE2FIFO__SHIFT 0x0000000d 7911de2bdb3dSTom St Denis #define MVP_DEBUG_14__IDEE_WRITE_ADD_A_MASK 0x00000038L 7912de2bdb3dSTom St Denis #define MVP_DEBUG_14__IDEE_WRITE_ADD_A__SHIFT 0x00000003 7913de2bdb3dSTom St Denis #define MVP_DEBUG_14__IDEE_WRITE_ADD_B_MASK 0x000001c0L 7914de2bdb3dSTom St Denis #define MVP_DEBUG_14__IDEE_WRITE_ADD_B__SHIFT 0x00000006 7915de2bdb3dSTom St Denis #define MVP_DEBUG_15__IDEF_MVP_ASYNC_FIFO_WDATA_MASK 0xfffffff0L 7916de2bdb3dSTom St Denis #define MVP_DEBUG_15__IDEF_MVP_ASYNC_FIFO_WDATA__SHIFT 0x00000004 7917de2bdb3dSTom St Denis #define MVP_DEBUG_15__IDEF_MVP_ASYNC_FIFO_WEN_MASK 0x00000001L 7918de2bdb3dSTom St Denis #define MVP_DEBUG_15__IDEF_MVP_ASYNC_FIFO_WEN__SHIFT 0x00000000 7919de2bdb3dSTom St Denis #define MVP_DEBUG_16__IDCC_FLOW_CONTROL_OUT_MASK 0x00000008L 7920de2bdb3dSTom St Denis #define MVP_DEBUG_16__IDCC_FLOW_CONTROL_OUT__SHIFT 0x00000003 7921de2bdb3dSTom St Denis #define MVP_DEBUG_16__IDCC_MVP_ASYNC_FIFO_EXCEED_PAUSE_LEVEL_MASK 0x00000004L 7922de2bdb3dSTom St Denis #define MVP_DEBUG_16__IDCC_MVP_ASYNC_FIFO_EXCEED_PAUSE_LEVEL__SHIFT 0x00000002 7923de2bdb3dSTom St Denis #define MVP_DEBUG_16__IDCC_MVP_ASYNC_FIFO_EXCEED_STOP_LEVEL_MASK 0x00000002L 7924de2bdb3dSTom St Denis #define MVP_DEBUG_16__IDCC_MVP_ASYNC_FIFO_EXCEED_STOP_LEVEL__SHIFT 0x00000001 7925de2bdb3dSTom St Denis #define MVP_DEBUG_16__IDCC_MVP_ASYNC_FIFO_NUM_ENTRIES_MASK 0x00000ff0L 7926de2bdb3dSTom St Denis #define MVP_DEBUG_16__IDCC_MVP_ASYNC_FIFO_NUM_ENTRIES__SHIFT 0x00000004 7927de2bdb3dSTom St Denis #define MVP_DEBUG_16__IDCC_MVP_ASYNC_FIFO_OVERFLOW_MASK 0x00001000L 7928de2bdb3dSTom St Denis #define MVP_DEBUG_16__IDCC_MVP_ASYNC_FIFO_OVERFLOW__SHIFT 0x0000000c 7929de2bdb3dSTom St Denis #define MVP_DEBUG_16__IDCC_MVP_ASYNC_FIFO_READ_MASK 0x00000001L 7930de2bdb3dSTom St Denis #define MVP_DEBUG_16__IDCC_MVP_ASYNC_FIFO_READ__SHIFT 0x00000000 7931de2bdb3dSTom St Denis #define MVP_DEBUG_16__IDCC_MVP_ASYNC_FIFO_UNDERFLOW_MASK 0x00002000L 7932de2bdb3dSTom St Denis #define MVP_DEBUG_16__IDCC_MVP_ASYNC_FIFO_UNDERFLOW__SHIFT 0x0000000d 7933de2bdb3dSTom St Denis #define MVP_DEBUG_16__IDCC_MVP_ASYNC_READ_ADDR_MASK 0x00ff0000L 7934de2bdb3dSTom St Denis #define MVP_DEBUG_16__IDCC_MVP_ASYNC_READ_ADDR__SHIFT 0x00000010 7935de2bdb3dSTom St Denis #define MVP_DEBUG_16__IDCC_MVP_ASYNC_WRITE_ADDR_MASK 0xff000000L 7936de2bdb3dSTom St Denis #define MVP_DEBUG_16__IDCC_MVP_ASYNC_WRITE_ADDR__SHIFT 0x00000018 7937de2bdb3dSTom St Denis #define MVP_DEBUG_17__IDCD_MVP_ASYNC_FIFO_PHASE_MASK 0x00000002L 7938de2bdb3dSTom St Denis #define MVP_DEBUG_17__IDCD_MVP_ASYNC_FIFO_PHASE__SHIFT 0x00000001 7939de2bdb3dSTom St Denis #define MVP_DEBUG_17__IDCD_MVP_ASYNC_FIFO_READ_DATA_MASK 0xfffffffcL 7940de2bdb3dSTom St Denis #define MVP_DEBUG_17__IDCD_MVP_ASYNC_FIFO_READ_DATA__SHIFT 0x00000002 7941de2bdb3dSTom St Denis #define MVP_DEBUG_17__IDCD_MVP_ASYNC_FIFO_READ_MASK 0x00000001L 7942de2bdb3dSTom St Denis #define MVP_DEBUG_17__IDCD_MVP_ASYNC_FIFO_READ__SHIFT 0x00000000 7943de2bdb3dSTom St Denis #define MVP_DEBUG__MVP_DEBUG_BITS_MASK 0xffffff00L 7944de2bdb3dSTom St Denis #define MVP_DEBUG__MVP_DEBUG_BITS__SHIFT 0x00000008 7945de2bdb3dSTom St Denis #define MVP_DEBUG__MVP_DIS_FIX_AFR_AUTO_VSYNC_FLIP_MASK 0x00000020L 7946de2bdb3dSTom St Denis #define MVP_DEBUG__MVP_DIS_FIX_AFR_AUTO_VSYNC_FLIP__SHIFT 0x00000005 7947de2bdb3dSTom St Denis #define MVP_DEBUG__MVP_DIS_FIX_AFR_MANUAL_HSYNC_FLIP_MASK 0x00000010L 7948de2bdb3dSTom St Denis #define MVP_DEBUG__MVP_DIS_FIX_AFR_MANUAL_HSYNC_FLIP__SHIFT 0x00000004 7949de2bdb3dSTom St Denis #define MVP_DEBUG__MVP_DIS_READ_POINTER_RESET_DELAY_MASK 0x00000080L 7950de2bdb3dSTom St Denis #define MVP_DEBUG__MVP_DIS_READ_POINTER_RESET_DELAY__SHIFT 0x00000007 7951de2bdb3dSTom St Denis #define MVP_DEBUG__MVP_EN_FIX_AFR_MANUAL_SWITCH_IN_SFR_MASK 0x00000040L 7952de2bdb3dSTom St Denis #define MVP_DEBUG__MVP_EN_FIX_AFR_MANUAL_SWITCH_IN_SFR__SHIFT 0x00000006 7953de2bdb3dSTom St Denis #define MVP_DEBUG__MVP_FLOW_CONTROL_IN_EN_MASK 0x00000002L 7954de2bdb3dSTom St Denis #define MVP_DEBUG__MVP_FLOW_CONTROL_IN_EN__SHIFT 0x00000001 7955de2bdb3dSTom St Denis #define MVP_DEBUG__MVP_FLOW_CONTROL_IN_SEL_MASK 0x00000008L 7956de2bdb3dSTom St Denis #define MVP_DEBUG__MVP_FLOW_CONTROL_IN_SEL__SHIFT 0x00000003 7957de2bdb3dSTom St Denis #define MVP_DEBUG__MVP_SWAP_LOCK_IN_EN_MASK 0x00000001L 7958de2bdb3dSTom St Denis #define MVP_DEBUG__MVP_SWAP_LOCK_IN_EN__SHIFT 0x00000000 7959de2bdb3dSTom St Denis #define MVP_DEBUG__MVP_SWAP_LOCK_IN_SEL_MASK 0x00000004L 7960de2bdb3dSTom St Denis #define MVP_DEBUG__MVP_SWAP_LOCK_IN_SEL__SHIFT 0x00000002 7961de2bdb3dSTom St Denis #define MVP_FIFO_CONTROL__MVP_PAUSE_SLAVE_CNT_MASK 0x00ff0000L 7962de2bdb3dSTom St Denis #define MVP_FIFO_CONTROL__MVP_PAUSE_SLAVE_CNT__SHIFT 0x00000010 7963de2bdb3dSTom St Denis #define MVP_FIFO_CONTROL__MVP_PAUSE_SLAVE_WM_MASK 0x0000ff00L 7964de2bdb3dSTom St Denis #define MVP_FIFO_CONTROL__MVP_PAUSE_SLAVE_WM__SHIFT 0x00000008 7965de2bdb3dSTom St Denis #define MVP_FIFO_CONTROL__MVP_STOP_SLAVE_WM_MASK 0x000000ffL 7966de2bdb3dSTom St Denis #define MVP_FIFO_CONTROL__MVP_STOP_SLAVE_WM__SHIFT 0x00000000 7967de2bdb3dSTom St Denis #define MVP_FIFO_STATUS__MVP_FIFO_ERROR_INT_STATUS_MASK 0x80000000L 7968de2bdb3dSTom St Denis #define MVP_FIFO_STATUS__MVP_FIFO_ERROR_INT_STATUS__SHIFT 0x0000001f 7969de2bdb3dSTom St Denis #define MVP_FIFO_STATUS__MVP_FIFO_ERROR_MASK_MASK 0x40000000L 7970de2bdb3dSTom St Denis #define MVP_FIFO_STATUS__MVP_FIFO_ERROR_MASK__SHIFT 0x0000001e 7971de2bdb3dSTom St Denis #define MVP_FIFO_STATUS__MVP_FIFO_LEVEL_MASK 0x000000ffL 7972de2bdb3dSTom St Denis #define MVP_FIFO_STATUS__MVP_FIFO_LEVEL__SHIFT 0x00000000 7973de2bdb3dSTom St Denis #define MVP_FIFO_STATUS__MVP_FIFO_OVERFLOW_ACK_MASK 0x00010000L 7974de2bdb3dSTom St Denis #define MVP_FIFO_STATUS__MVP_FIFO_OVERFLOW_ACK__SHIFT 0x00000010 7975de2bdb3dSTom St Denis #define MVP_FIFO_STATUS__MVP_FIFO_OVERFLOW_MASK 0x00000100L 7976de2bdb3dSTom St Denis #define MVP_FIFO_STATUS__MVP_FIFO_OVERFLOW_OCCURRED_MASK 0x00001000L 7977de2bdb3dSTom St Denis #define MVP_FIFO_STATUS__MVP_FIFO_OVERFLOW_OCCURRED__SHIFT 0x0000000c 7978de2bdb3dSTom St Denis #define MVP_FIFO_STATUS__MVP_FIFO_OVERFLOW__SHIFT 0x00000008 7979de2bdb3dSTom St Denis #define MVP_FIFO_STATUS__MVP_FIFO_UNDERFLOW_ACK_MASK 0x10000000L 7980de2bdb3dSTom St Denis #define MVP_FIFO_STATUS__MVP_FIFO_UNDERFLOW_ACK__SHIFT 0x0000001c 7981de2bdb3dSTom St Denis #define MVP_FIFO_STATUS__MVP_FIFO_UNDERFLOW_MASK 0x00100000L 7982de2bdb3dSTom St Denis #define MVP_FIFO_STATUS__MVP_FIFO_UNDERFLOW_OCCURRED_MASK 0x01000000L 7983de2bdb3dSTom St Denis #define MVP_FIFO_STATUS__MVP_FIFO_UNDERFLOW_OCCURRED__SHIFT 0x00000018 7984de2bdb3dSTom St Denis #define MVP_FIFO_STATUS__MVP_FIFO_UNDERFLOW__SHIFT 0x00000014 7985de2bdb3dSTom St Denis #define MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_AUTO_ENABLE_MASK 0x40000000L 7986de2bdb3dSTom St Denis #define MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_AUTO_ENABLE__SHIFT 0x0000001e 7987de2bdb3dSTom St Denis #define MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_LINE_NUM_INSERT_MASK 0x007fff00L 7988de2bdb3dSTom St Denis #define MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_LINE_NUM_INSERT_MODE_MASK 0x00000003L 7989de2bdb3dSTom St Denis #define MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_LINE_NUM_INSERT_MODE__SHIFT 0x00000000 7990de2bdb3dSTom St Denis #define MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_LINE_NUM_INSERT__SHIFT 0x00000008 7991de2bdb3dSTom St Denis #define MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_LINE_NUM_OFFSET_MASK 0x3f000000L 7992de2bdb3dSTom St Denis #define MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_LINE_NUM_OFFSET__SHIFT 0x00000018 7993de2bdb3dSTom St Denis #define MVP_INBAND_CNTL_CAP__MVP_IGNOR_INBAND_CNTL_MASK 0x00000001L 7994de2bdb3dSTom St Denis #define MVP_INBAND_CNTL_CAP__MVP_IGNOR_INBAND_CNTL__SHIFT 0x00000000 7995de2bdb3dSTom St Denis #define MVP_INBAND_CNTL_CAP__MVP_INBAND_CNTL_CHAR_CAP_MASK 0xffffff00L 7996de2bdb3dSTom St Denis #define MVP_INBAND_CNTL_CAP__MVP_INBAND_CNTL_CHAR_CAP__SHIFT 0x00000008 7997de2bdb3dSTom St Denis #define MVP_INBAND_CNTL_CAP__MVP_PASSING_INBAND_CNTL_EN_MASK 0x00000010L 7998de2bdb3dSTom St Denis #define MVP_INBAND_CNTL_CAP__MVP_PASSING_INBAND_CNTL_EN__SHIFT 0x00000004 7999de2bdb3dSTom St Denis #define MVP_RECEIVE_CNT_CNTL1__MVP_SLAVE_DATA_CHK_EN_MASK 0x80000000L 8000de2bdb3dSTom St Denis #define MVP_RECEIVE_CNT_CNTL1__MVP_SLAVE_DATA_CHK_EN__SHIFT 0x0000001f 8001de2bdb3dSTom St Denis #define MVP_RECEIVE_CNT_CNTL1__MVP_SLAVE_LINE_ERROR_CNT_MASK 0x1fff0000L 8002de2bdb3dSTom St Denis #define MVP_RECEIVE_CNT_CNTL1__MVP_SLAVE_LINE_ERROR_CNT__SHIFT 0x00000010 8003de2bdb3dSTom St Denis #define MVP_RECEIVE_CNT_CNTL1__MVP_SLAVE_PIXEL_ERROR_CNT_MASK 0x00001fffL 8004de2bdb3dSTom St Denis #define MVP_RECEIVE_CNT_CNTL1__MVP_SLAVE_PIXEL_ERROR_CNT__SHIFT 0x00000000 8005de2bdb3dSTom St Denis #define MVP_RECEIVE_CNT_CNTL2__MVP_SLAVE_FRAME_ERROR_CNT_MASK 0x00001fffL 8006de2bdb3dSTom St Denis #define MVP_RECEIVE_CNT_CNTL2__MVP_SLAVE_FRAME_ERROR_CNT_RESET_MASK 0x80000000L 8007de2bdb3dSTom St Denis #define MVP_RECEIVE_CNT_CNTL2__MVP_SLAVE_FRAME_ERROR_CNT_RESET__SHIFT 0x0000001f 8008de2bdb3dSTom St Denis #define MVP_RECEIVE_CNT_CNTL2__MVP_SLAVE_FRAME_ERROR_CNT__SHIFT 0x00000000 8009de2bdb3dSTom St Denis #define MVP_SLAVE_STATUS__MVP_SLAVE_LINES_PER_FRAME_RCVED_MASK 0x1fff0000L 8010de2bdb3dSTom St Denis #define MVP_SLAVE_STATUS__MVP_SLAVE_LINES_PER_FRAME_RCVED__SHIFT 0x00000010 8011de2bdb3dSTom St Denis #define MVP_SLAVE_STATUS__MVP_SLAVE_PIXELS_PER_LINE_RCVED_MASK 0x00001fffL 8012de2bdb3dSTom St Denis #define MVP_SLAVE_STATUS__MVP_SLAVE_PIXELS_PER_LINE_RCVED__SHIFT 0x00000000 8013de2bdb3dSTom St Denis #define MVP_TEST_DEBUG_DATA__MVP_TEST_DEBUG_DATA_MASK 0xffffffffL 8014de2bdb3dSTom St Denis #define MVP_TEST_DEBUG_DATA__MVP_TEST_DEBUG_DATA__SHIFT 0x00000000 8015de2bdb3dSTom St Denis #define MVP_TEST_DEBUG_INDEX__MVP_TEST_DEBUG_INDEX_MASK 0x000000ffL 8016de2bdb3dSTom St Denis #define MVP_TEST_DEBUG_INDEX__MVP_TEST_DEBUG_INDEX__SHIFT 0x00000000 8017de2bdb3dSTom St Denis #define MVP_TEST_DEBUG_INDEX__MVP_TEST_DEBUG_WRITE_EN_MASK 0x00000100L 8018de2bdb3dSTom St Denis #define MVP_TEST_DEBUG_INDEX__MVP_TEST_DEBUG_WRITE_EN__SHIFT 0x00000008 8019de2bdb3dSTom St Denis #define OUTPUT_CSC_C11_C12__OUTPUT_CSC_C11_MASK 0x0000ffffL 8020de2bdb3dSTom St Denis #define OUTPUT_CSC_C11_C12__OUTPUT_CSC_C11__SHIFT 0x00000000 8021de2bdb3dSTom St Denis #define OUTPUT_CSC_C11_C12__OUTPUT_CSC_C12_MASK 0xffff0000L 8022de2bdb3dSTom St Denis #define OUTPUT_CSC_C11_C12__OUTPUT_CSC_C12__SHIFT 0x00000010 8023de2bdb3dSTom St Denis #define OUTPUT_CSC_C13_C14__OUTPUT_CSC_C13_MASK 0x0000ffffL 8024de2bdb3dSTom St Denis #define OUTPUT_CSC_C13_C14__OUTPUT_CSC_C13__SHIFT 0x00000000 8025de2bdb3dSTom St Denis #define OUTPUT_CSC_C13_C14__OUTPUT_CSC_C14_MASK 0xffff0000L 8026de2bdb3dSTom St Denis #define OUTPUT_CSC_C13_C14__OUTPUT_CSC_C14__SHIFT 0x00000010 8027de2bdb3dSTom St Denis #define OUTPUT_CSC_C21_C22__OUTPUT_CSC_C21_MASK 0x0000ffffL 8028de2bdb3dSTom St Denis #define OUTPUT_CSC_C21_C22__OUTPUT_CSC_C21__SHIFT 0x00000000 8029de2bdb3dSTom St Denis #define OUTPUT_CSC_C21_C22__OUTPUT_CSC_C22_MASK 0xffff0000L 8030de2bdb3dSTom St Denis #define OUTPUT_CSC_C21_C22__OUTPUT_CSC_C22__SHIFT 0x00000010 8031de2bdb3dSTom St Denis #define OUTPUT_CSC_C23_C24__OUTPUT_CSC_C23_MASK 0x0000ffffL 8032de2bdb3dSTom St Denis #define OUTPUT_CSC_C23_C24__OUTPUT_CSC_C23__SHIFT 0x00000000 8033de2bdb3dSTom St Denis #define OUTPUT_CSC_C23_C24__OUTPUT_CSC_C24_MASK 0xffff0000L 8034de2bdb3dSTom St Denis #define OUTPUT_CSC_C23_C24__OUTPUT_CSC_C24__SHIFT 0x00000010 8035de2bdb3dSTom St Denis #define OUTPUT_CSC_C31_C32__OUTPUT_CSC_C31_MASK 0x0000ffffL 8036de2bdb3dSTom St Denis #define OUTPUT_CSC_C31_C32__OUTPUT_CSC_C31__SHIFT 0x00000000 8037de2bdb3dSTom St Denis #define OUTPUT_CSC_C31_C32__OUTPUT_CSC_C32_MASK 0xffff0000L 8038de2bdb3dSTom St Denis #define OUTPUT_CSC_C31_C32__OUTPUT_CSC_C32__SHIFT 0x00000010 8039de2bdb3dSTom St Denis #define OUTPUT_CSC_C33_C34__OUTPUT_CSC_C33_MASK 0x0000ffffL 8040de2bdb3dSTom St Denis #define OUTPUT_CSC_C33_C34__OUTPUT_CSC_C33__SHIFT 0x00000000 8041de2bdb3dSTom St Denis #define OUTPUT_CSC_C33_C34__OUTPUT_CSC_C34_MASK 0xffff0000L 8042de2bdb3dSTom St Denis #define OUTPUT_CSC_C33_C34__OUTPUT_CSC_C34__SHIFT 0x00000010 8043de2bdb3dSTom St Denis #define OUTPUT_CSC_CONTROL__OUTPUT_CSC_GRPH_MODE_MASK 0x00000007L 8044de2bdb3dSTom St Denis #define OUTPUT_CSC_CONTROL__OUTPUT_CSC_GRPH_MODE__SHIFT 0x00000000 8045de2bdb3dSTom St Denis #define OUTPUT_CSC_CONTROL__OUTPUT_CSC_OVL_MODE_MASK 0x00000070L 8046de2bdb3dSTom St Denis #define OUTPUT_CSC_CONTROL__OUTPUT_CSC_OVL_MODE__SHIFT 0x00000004 8047de2bdb3dSTom St Denis #define OUT_ROUND_CONTROL__OUT_ROUND_TRUNC_MODE_MASK 0x0000000fL 8048de2bdb3dSTom St Denis #define OUT_ROUND_CONTROL__OUT_ROUND_TRUNC_MODE__SHIFT 0x00000000 8049de2bdb3dSTom St Denis #define OVL_CONTROL1__OVL_ADDRESS_TRANSLATION_ENABLE_MASK 0x00010000L 8050de2bdb3dSTom St Denis #define OVL_CONTROL1__OVL_ADDRESS_TRANSLATION_ENABLE__SHIFT 0x00000010 8051de2bdb3dSTom St Denis #define OVL_CONTROL1__OVL_ARRAY_MODE_MASK 0x00f00000L 8052de2bdb3dSTom St Denis #define OVL_CONTROL1__OVL_ARRAY_MODE__SHIFT 0x00000014 8053de2bdb3dSTom St Denis #define OVL_CONTROL1__OVL_BANK_HEIGHT_MASK 0x00001800L 8054de2bdb3dSTom St Denis #define OVL_CONTROL1__OVL_BANK_HEIGHT__SHIFT 0x0000000b 8055de2bdb3dSTom St Denis #define OVL_CONTROL1__OVL_BANK_WIDTH_MASK 0x000000c0L 8056de2bdb3dSTom St Denis #define OVL_CONTROL1__OVL_BANK_WIDTH__SHIFT 0x00000006 8057de2bdb3dSTom St Denis #define OVL_CONTROL1__OVL_COLOR_EXPANSION_MODE_MASK 0x01000000L 8058de2bdb3dSTom St Denis #define OVL_CONTROL1__OVL_COLOR_EXPANSION_MODE__SHIFT 0x00000018 8059de2bdb3dSTom St Denis #define OVL_CONTROL1__OVL_DEPTH_MASK 0x00000003L 8060de2bdb3dSTom St Denis #define OVL_CONTROL1__OVL_DEPTH__SHIFT 0x00000000 8061de2bdb3dSTom St Denis #define OVL_CONTROL1__OVL_FORMAT_MASK 0x00000700L 8062de2bdb3dSTom St Denis #define OVL_CONTROL1__OVL_FORMAT__SHIFT 0x00000008 8063de2bdb3dSTom St Denis #define OVL_CONTROL1__OVL_MACRO_TILE_ASPECT_MASK 0x000c0000L 8064de2bdb3dSTom St Denis #define OVL_CONTROL1__OVL_MACRO_TILE_ASPECT__SHIFT 0x00000012 8065de2bdb3dSTom St Denis #define OVL_CONTROL1__OVL_NUM_BANKS_MASK 0x0000000cL 8066de2bdb3dSTom St Denis #define OVL_CONTROL1__OVL_NUM_BANKS__SHIFT 0x00000002 8067de2bdb3dSTom St Denis #define OVL_CONTROL1__OVL_PIPE_CONFIG_MASK 0x3e000000L 8068de2bdb3dSTom St Denis #define OVL_CONTROL1__OVL_PIPE_CONFIG__SHIFT 0x00000019 8069de2bdb3dSTom St Denis #define OVL_CONTROL1__OVL_PRIVILEGED_ACCESS_ENABLE_MASK 0x00020000L 8070de2bdb3dSTom St Denis #define OVL_CONTROL1__OVL_PRIVILEGED_ACCESS_ENABLE__SHIFT 0x00000011 8071de2bdb3dSTom St Denis #define OVL_CONTROL1__OVL_TILE_SPLIT_MASK 0x0000e000L 8072de2bdb3dSTom St Denis #define OVL_CONTROL1__OVL_TILE_SPLIT__SHIFT 0x0000000d 8073de2bdb3dSTom St Denis #define OVL_CONTROL1__OVL_Z_MASK 0x00000030L 8074de2bdb3dSTom St Denis #define OVL_CONTROL1__OVL_Z__SHIFT 0x00000004 8075de2bdb3dSTom St Denis #define OVL_CONTROL2__OVL_HALF_RESOLUTION_ENABLE_MASK 0x00000001L 8076de2bdb3dSTom St Denis #define OVL_CONTROL2__OVL_HALF_RESOLUTION_ENABLE__SHIFT 0x00000000 8077de2bdb3dSTom St Denis #define OVL_DFQ_CONTROL__OVL_DFQ_MIN_FREE_ENTRIES_MASK 0x00000700L 8078de2bdb3dSTom St Denis #define OVL_DFQ_CONTROL__OVL_DFQ_MIN_FREE_ENTRIES__SHIFT 0x00000008 8079de2bdb3dSTom St Denis #define OVL_DFQ_CONTROL__OVL_DFQ_RESET_MASK 0x00000001L 8080de2bdb3dSTom St Denis #define OVL_DFQ_CONTROL__OVL_DFQ_RESET__SHIFT 0x00000000 8081de2bdb3dSTom St Denis #define OVL_DFQ_CONTROL__OVL_DFQ_SIZE_MASK 0x00000070L 8082de2bdb3dSTom St Denis #define OVL_DFQ_CONTROL__OVL_DFQ_SIZE__SHIFT 0x00000004 8083de2bdb3dSTom St Denis #define OVL_DFQ_STATUS__OVL_DFQ_NUM_ENTRIES_MASK 0x0000000fL 8084de2bdb3dSTom St Denis #define OVL_DFQ_STATUS__OVL_DFQ_NUM_ENTRIES__SHIFT 0x00000000 8085de2bdb3dSTom St Denis #define OVL_DFQ_STATUS__OVL_DFQ_RESET_ACK_MASK 0x00000200L 8086de2bdb3dSTom St Denis #define OVL_DFQ_STATUS__OVL_DFQ_RESET_ACK__SHIFT 0x00000009 8087de2bdb3dSTom St Denis #define OVL_DFQ_STATUS__OVL_DFQ_RESET_FLAG_MASK 0x00000100L 8088de2bdb3dSTom St Denis #define OVL_DFQ_STATUS__OVL_DFQ_RESET_FLAG__SHIFT 0x00000008 8089de2bdb3dSTom St Denis #define OVL_DFQ_STATUS__OVL_SECONDARY_DFQ_NUM_ENTRIES_MASK 0x000000f0L 8090de2bdb3dSTom St Denis #define OVL_DFQ_STATUS__OVL_SECONDARY_DFQ_NUM_ENTRIES__SHIFT 0x00000004 8091de2bdb3dSTom St Denis #define OVL_ENABLE__OVL_ENABLE_MASK 0x00000001L 8092de2bdb3dSTom St Denis #define OVL_ENABLE__OVL_ENABLE__SHIFT 0x00000000 8093de2bdb3dSTom St Denis #define OVL_ENABLE__OVLSCL_EN_MASK 0x00000100L 8094de2bdb3dSTom St Denis #define OVL_ENABLE__OVLSCL_EN__SHIFT 0x00000008 8095de2bdb3dSTom St Denis #define OVL_END__OVL_X_END_MASK 0x7fff0000L 8096de2bdb3dSTom St Denis #define OVL_END__OVL_X_END__SHIFT 0x00000010 8097de2bdb3dSTom St Denis #define OVL_END__OVL_Y_END_MASK 0x00007fffL 8098de2bdb3dSTom St Denis #define OVL_END__OVL_Y_END__SHIFT 0x00000000 8099de2bdb3dSTom St Denis #define OVL_PITCH__OVL_PITCH_MASK 0x00007fffL 8100de2bdb3dSTom St Denis #define OVL_PITCH__OVL_PITCH__SHIFT 0x00000000 8101de2bdb3dSTom St Denis #define OVLSCL_EDGE_PIXEL_CNTL__OVLSCL_BLACK_COLOR_BCB_MASK 0x000003ffL 8102de2bdb3dSTom St Denis #define OVLSCL_EDGE_PIXEL_CNTL__OVLSCL_BLACK_COLOR_BCB__SHIFT 0x00000000 8103de2bdb3dSTom St Denis #define OVLSCL_EDGE_PIXEL_CNTL__OVLSCL_BLACK_COLOR_GY_MASK 0x000ffc00L 8104de2bdb3dSTom St Denis #define OVLSCL_EDGE_PIXEL_CNTL__OVLSCL_BLACK_COLOR_GY__SHIFT 0x0000000a 8105de2bdb3dSTom St Denis #define OVLSCL_EDGE_PIXEL_CNTL__OVLSCL_BLACK_COLOR_RCR_MASK 0x3ff00000L 8106de2bdb3dSTom St Denis #define OVLSCL_EDGE_PIXEL_CNTL__OVLSCL_BLACK_COLOR_RCR__SHIFT 0x00000014 8107de2bdb3dSTom St Denis #define OVLSCL_EDGE_PIXEL_CNTL__OVLSCL_EDGE_PIXEL_SEL_MASK 0x80000000L 8108de2bdb3dSTom St Denis #define OVLSCL_EDGE_PIXEL_CNTL__OVLSCL_EDGE_PIXEL_SEL__SHIFT 0x0000001f 8109de2bdb3dSTom St Denis #define OVL_SECONDARY_SURFACE_ADDRESS_HIGH__OVL_SECONDARY_SURFACE_ADDRESS_HIGH_MASK 0x000000ffL 8110de2bdb3dSTom St Denis #define OVL_SECONDARY_SURFACE_ADDRESS_HIGH__OVL_SECONDARY_SURFACE_ADDRESS_HIGH__SHIFT 0x00000000 8111de2bdb3dSTom St Denis #define OVL_SECONDARY_SURFACE_ADDRESS__OVL_SECONDARY_DFQ_ENABLE_MASK 0x00000001L 8112de2bdb3dSTom St Denis #define OVL_SECONDARY_SURFACE_ADDRESS__OVL_SECONDARY_DFQ_ENABLE__SHIFT 0x00000000 8113de2bdb3dSTom St Denis #define OVL_SECONDARY_SURFACE_ADDRESS__OVL_SECONDARY_SURFACE_ADDRESS_MASK 0xffffff00L 8114de2bdb3dSTom St Denis #define OVL_SECONDARY_SURFACE_ADDRESS__OVL_SECONDARY_SURFACE_ADDRESS__SHIFT 0x00000008 8115de2bdb3dSTom St Denis #define OVL_START__OVL_X_START_MASK 0x3fff0000L 8116de2bdb3dSTom St Denis #define OVL_START__OVL_X_START__SHIFT 0x00000010 8117de2bdb3dSTom St Denis #define OVL_START__OVL_Y_START_MASK 0x00003fffL 8118de2bdb3dSTom St Denis #define OVL_START__OVL_Y_START__SHIFT 0x00000000 8119de2bdb3dSTom St Denis #define OVL_STEREOSYNC_FLIP__OVL_PRIMARY_SURFACE_PENDING_MASK 0x00010000L 8120de2bdb3dSTom St Denis #define OVL_STEREOSYNC_FLIP__OVL_PRIMARY_SURFACE_PENDING__SHIFT 0x00000010 8121de2bdb3dSTom St Denis #define OVL_STEREOSYNC_FLIP__OVL_SECONDARY_SURFACE_PENDING_MASK 0x00020000L 8122de2bdb3dSTom St Denis #define OVL_STEREOSYNC_FLIP__OVL_SECONDARY_SURFACE_PENDING__SHIFT 0x00000011 8123de2bdb3dSTom St Denis #define OVL_STEREOSYNC_FLIP__OVL_STEREOSYNC_FLIP_EN_MASK 0x00000001L 8124de2bdb3dSTom St Denis #define OVL_STEREOSYNC_FLIP__OVL_STEREOSYNC_FLIP_EN__SHIFT 0x00000000 8125de2bdb3dSTom St Denis #define OVL_STEREOSYNC_FLIP__OVL_STEREOSYNC_FLIP_MODE_MASK 0x00000300L 8126de2bdb3dSTom St Denis #define OVL_STEREOSYNC_FLIP__OVL_STEREOSYNC_FLIP_MODE__SHIFT 0x00000008 8127de2bdb3dSTom St Denis #define OVL_STEREOSYNC_FLIP__OVL_STEREOSYNC_SELECT_DISABLE_MASK 0x10000000L 8128de2bdb3dSTom St Denis #define OVL_STEREOSYNC_FLIP__OVL_STEREOSYNC_SELECT_DISABLE__SHIFT 0x0000001c 8129de2bdb3dSTom St Denis #define OVL_SURFACE_ADDRESS_HIGH_INUSE__OVL_SURFACE_ADDRESS_HIGH_INUSE_MASK 0x000000ffL 8130de2bdb3dSTom St Denis #define OVL_SURFACE_ADDRESS_HIGH_INUSE__OVL_SURFACE_ADDRESS_HIGH_INUSE__SHIFT 0x00000000 8131de2bdb3dSTom St Denis #define OVL_SURFACE_ADDRESS_HIGH__OVL_SURFACE_ADDRESS_HIGH_MASK 0x000000ffL 8132de2bdb3dSTom St Denis #define OVL_SURFACE_ADDRESS_HIGH__OVL_SURFACE_ADDRESS_HIGH__SHIFT 0x00000000 8133de2bdb3dSTom St Denis #define OVL_SURFACE_ADDRESS_INUSE__OVL_SURFACE_ADDRESS_INUSE_MASK 0xffffff00L 8134de2bdb3dSTom St Denis #define OVL_SURFACE_ADDRESS_INUSE__OVL_SURFACE_ADDRESS_INUSE__SHIFT 0x00000008 8135de2bdb3dSTom St Denis #define OVL_SURFACE_ADDRESS__OVL_DFQ_ENABLE_MASK 0x00000001L 8136de2bdb3dSTom St Denis #define OVL_SURFACE_ADDRESS__OVL_DFQ_ENABLE__SHIFT 0x00000000 8137de2bdb3dSTom St Denis #define OVL_SURFACE_ADDRESS__OVL_SURFACE_ADDRESS_MASK 0xffffff00L 8138de2bdb3dSTom St Denis #define OVL_SURFACE_ADDRESS__OVL_SURFACE_ADDRESS__SHIFT 0x00000008 8139de2bdb3dSTom St Denis #define OVL_SURFACE_OFFSET_X__OVL_SURFACE_OFFSET_X_MASK 0x00003fffL 8140de2bdb3dSTom St Denis #define OVL_SURFACE_OFFSET_X__OVL_SURFACE_OFFSET_X__SHIFT 0x00000000 8141de2bdb3dSTom St Denis #define OVL_SURFACE_OFFSET_Y__OVL_SURFACE_OFFSET_Y_MASK 0x00003fffL 8142de2bdb3dSTom St Denis #define OVL_SURFACE_OFFSET_Y__OVL_SURFACE_OFFSET_Y__SHIFT 0x00000000 8143de2bdb3dSTom St Denis #define OVL_SWAP_CNTL__OVL_ALPHA_CROSSBAR_MASK 0x00000c00L 8144de2bdb3dSTom St Denis #define OVL_SWAP_CNTL__OVL_ALPHA_CROSSBAR__SHIFT 0x0000000a 8145de2bdb3dSTom St Denis #define OVL_SWAP_CNTL__OVL_BLUE_CROSSBAR_MASK 0x00000300L 8146de2bdb3dSTom St Denis #define OVL_SWAP_CNTL__OVL_BLUE_CROSSBAR__SHIFT 0x00000008 8147de2bdb3dSTom St Denis #define OVL_SWAP_CNTL__OVL_ENDIAN_SWAP_MASK 0x00000003L 8148de2bdb3dSTom St Denis #define OVL_SWAP_CNTL__OVL_ENDIAN_SWAP__SHIFT 0x00000000 8149de2bdb3dSTom St Denis #define OVL_SWAP_CNTL__OVL_GREEN_CROSSBAR_MASK 0x000000c0L 8150de2bdb3dSTom St Denis #define OVL_SWAP_CNTL__OVL_GREEN_CROSSBAR__SHIFT 0x00000006 8151de2bdb3dSTom St Denis #define OVL_SWAP_CNTL__OVL_RED_CROSSBAR_MASK 0x00000030L 8152de2bdb3dSTom St Denis #define OVL_SWAP_CNTL__OVL_RED_CROSSBAR__SHIFT 0x00000004 8153de2bdb3dSTom St Denis #define OVL_UPDATE__OVL_DISABLE_MULTIPLE_UPDATE_MASK 0x01000000L 8154de2bdb3dSTom St Denis #define OVL_UPDATE__OVL_DISABLE_MULTIPLE_UPDATE__SHIFT 0x00000018 8155de2bdb3dSTom St Denis #define OVL_UPDATE__OVL_UPDATE_LOCK_MASK 0x00010000L 8156de2bdb3dSTom St Denis #define OVL_UPDATE__OVL_UPDATE_LOCK__SHIFT 0x00000010 8157de2bdb3dSTom St Denis #define OVL_UPDATE__OVL_UPDATE_PENDING_MASK 0x00000001L 8158de2bdb3dSTom St Denis #define OVL_UPDATE__OVL_UPDATE_PENDING__SHIFT 0x00000000 8159de2bdb3dSTom St Denis #define OVL_UPDATE__OVL_UPDATE_TAKEN_MASK 0x00000002L 8160de2bdb3dSTom St Denis #define OVL_UPDATE__OVL_UPDATE_TAKEN__SHIFT 0x00000001 8161de2bdb3dSTom St Denis #define PHY_AUX_CNTL__AUX_PAD_RXSEL_MASK 0x00010000L 8162de2bdb3dSTom St Denis #define PHY_AUX_CNTL__AUX_PAD_RXSEL__SHIFT 0x00000010 8163de2bdb3dSTom St Denis #define PHY_AUX_CNTL__AUX_PAD_SLEWN_MASK 0x00001000L 8164de2bdb3dSTom St Denis #define PHY_AUX_CNTL__AUX_PAD_SLEWN__SHIFT 0x0000000c 8165de2bdb3dSTom St Denis #define PHY_AUX_CNTL__AUX_PAD_WAKE_MASK 0x00004000L 8166de2bdb3dSTom St Denis #define PHY_AUX_CNTL__AUX_PAD_WAKE__SHIFT 0x0000000e 8167de2bdb3dSTom St Denis #define PIPE0_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT_MASK 0x0000ffffL 8168de2bdb3dSTom St Denis #define PIPE0_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT__SHIFT 0x00000000 8169de2bdb3dSTom St Denis #define PIPE0_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED_MASK 0x00000007L 8170de2bdb3dSTom St Denis #define PIPE0_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED__SHIFT 0x00000000 8171de2bdb3dSTom St Denis #define PIPE0_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED_MASK 0x00000010L 8172de2bdb3dSTom St Denis #define PIPE0_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED__SHIFT 0x00000004 8173de2bdb3dSTom St Denis #define PIPE0_MAX_REQUESTS__MAX_REQUESTS_MASK 0x000003ffL 8174de2bdb3dSTom St Denis #define PIPE0_MAX_REQUESTS__MAX_REQUESTS__SHIFT 0x00000000 8175de2bdb3dSTom St Denis #define PIPE0_PG_CONFIG__PIPE0_POWER_FORCEON_MASK 0x00000001L 8176de2bdb3dSTom St Denis #define PIPE0_PG_CONFIG__PIPE0_POWER_FORCEON__SHIFT 0x00000000 8177de2bdb3dSTom St Denis #define PIPE0_PG_ENABLE__PIPE0_POWER_GATE_MASK 0x00000001L 8178de2bdb3dSTom St Denis #define PIPE0_PG_ENABLE__PIPE0_POWER_GATE__SHIFT 0x00000000 8179de2bdb3dSTom St Denis #define PIPE0_PG_STATUS__PIPE0_DESIRED_PWR_STATE_MASK 0x10000000L 8180de2bdb3dSTom St Denis #define PIPE0_PG_STATUS__PIPE0_DESIRED_PWR_STATE__SHIFT 0x0000001c 8181de2bdb3dSTom St Denis #define PIPE0_PG_STATUS__PIPE0_PGFSM_PWR_STATUS_MASK 0xc0000000L 8182de2bdb3dSTom St Denis #define PIPE0_PG_STATUS__PIPE0_PGFSM_PWR_STATUS__SHIFT 0x0000001e 8183de2bdb3dSTom St Denis #define PIPE0_PG_STATUS__PIPE0_PGFSM_READ_DATA_MASK 0x00ffffffL 8184de2bdb3dSTom St Denis #define PIPE0_PG_STATUS__PIPE0_PGFSM_READ_DATA__SHIFT 0x00000000 8185de2bdb3dSTom St Denis #define PIPE0_PG_STATUS__PIPE0_REQUESTED_PWR_STATE_MASK 0x20000000L 8186de2bdb3dSTom St Denis #define PIPE0_PG_STATUS__PIPE0_REQUESTED_PWR_STATE__SHIFT 0x0000001d 8187de2bdb3dSTom St Denis #define PIPE1_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT_MASK 0x0000ffffL 8188de2bdb3dSTom St Denis #define PIPE1_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT__SHIFT 0x00000000 8189de2bdb3dSTom St Denis #define PIPE1_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED_MASK 0x00000007L 8190de2bdb3dSTom St Denis #define PIPE1_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED__SHIFT 0x00000000 8191de2bdb3dSTom St Denis #define PIPE1_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED_MASK 0x00000010L 8192de2bdb3dSTom St Denis #define PIPE1_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED__SHIFT 0x00000004 8193de2bdb3dSTom St Denis #define PIPE1_MAX_REQUESTS__MAX_REQUESTS_MASK 0x000003ffL 8194de2bdb3dSTom St Denis #define PIPE1_MAX_REQUESTS__MAX_REQUESTS__SHIFT 0x00000000 8195de2bdb3dSTom St Denis #define PIPE1_PG_CONFIG__PIPE1_POWER_FORCEON_MASK 0x00000001L 8196de2bdb3dSTom St Denis #define PIPE1_PG_CONFIG__PIPE1_POWER_FORCEON__SHIFT 0x00000000 8197de2bdb3dSTom St Denis #define PIPE1_PG_ENABLE__PIPE1_POWER_GATE_MASK 0x00000001L 8198de2bdb3dSTom St Denis #define PIPE1_PG_ENABLE__PIPE1_POWER_GATE__SHIFT 0x00000000 8199de2bdb3dSTom St Denis #define PIPE1_PG_STATUS__PIPE1_DESIRED_PWR_STATE_MASK 0x10000000L 8200de2bdb3dSTom St Denis #define PIPE1_PG_STATUS__PIPE1_DESIRED_PWR_STATE__SHIFT 0x0000001c 8201de2bdb3dSTom St Denis #define PIPE1_PG_STATUS__PIPE1_PGFSM_PWR_STATUS_MASK 0xc0000000L 8202de2bdb3dSTom St Denis #define PIPE1_PG_STATUS__PIPE1_PGFSM_PWR_STATUS__SHIFT 0x0000001e 8203de2bdb3dSTom St Denis #define PIPE1_PG_STATUS__PIPE1_PGFSM_READ_DATA_MASK 0x00ffffffL 8204de2bdb3dSTom St Denis #define PIPE1_PG_STATUS__PIPE1_PGFSM_READ_DATA__SHIFT 0x00000000 8205de2bdb3dSTom St Denis #define PIPE1_PG_STATUS__PIPE1_REQUESTED_PWR_STATE_MASK 0x20000000L 8206de2bdb3dSTom St Denis #define PIPE1_PG_STATUS__PIPE1_REQUESTED_PWR_STATE__SHIFT 0x0000001d 8207de2bdb3dSTom St Denis #define PIPE2_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT_MASK 0x0000ffffL 8208de2bdb3dSTom St Denis #define PIPE2_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT__SHIFT 0x00000000 8209de2bdb3dSTom St Denis #define PIPE2_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED_MASK 0x00000007L 8210de2bdb3dSTom St Denis #define PIPE2_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED__SHIFT 0x00000000 8211de2bdb3dSTom St Denis #define PIPE2_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED_MASK 0x00000010L 8212de2bdb3dSTom St Denis #define PIPE2_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED__SHIFT 0x00000004 8213de2bdb3dSTom St Denis #define PIPE2_MAX_REQUESTS__MAX_REQUESTS_MASK 0x000003ffL 8214de2bdb3dSTom St Denis #define PIPE2_MAX_REQUESTS__MAX_REQUESTS__SHIFT 0x00000000 8215de2bdb3dSTom St Denis #define PIPE2_PG_CONFIG__PIPE2_POWER_FORCEON_MASK 0x00000001L 8216de2bdb3dSTom St Denis #define PIPE2_PG_CONFIG__PIPE2_POWER_FORCEON__SHIFT 0x00000000 8217de2bdb3dSTom St Denis #define PIPE2_PG_ENABLE__PIPE2_POWER_GATE_MASK 0x00000001L 8218de2bdb3dSTom St Denis #define PIPE2_PG_ENABLE__PIPE2_POWER_GATE__SHIFT 0x00000000 8219de2bdb3dSTom St Denis #define PIPE2_PG_STATUS__PIPE2_DESIRED_PWR_STATE_MASK 0x10000000L 8220de2bdb3dSTom St Denis #define PIPE2_PG_STATUS__PIPE2_DESIRED_PWR_STATE__SHIFT 0x0000001c 8221de2bdb3dSTom St Denis #define PIPE2_PG_STATUS__PIPE2_PGFSM_PWR_STATUS_MASK 0xc0000000L 8222de2bdb3dSTom St Denis #define PIPE2_PG_STATUS__PIPE2_PGFSM_PWR_STATUS__SHIFT 0x0000001e 8223de2bdb3dSTom St Denis #define PIPE2_PG_STATUS__PIPE2_PGFSM_READ_DATA_MASK 0x00ffffffL 8224de2bdb3dSTom St Denis #define PIPE2_PG_STATUS__PIPE2_PGFSM_READ_DATA__SHIFT 0x00000000 8225de2bdb3dSTom St Denis #define PIPE2_PG_STATUS__PIPE2_REQUESTED_PWR_STATE_MASK 0x20000000L 8226de2bdb3dSTom St Denis #define PIPE2_PG_STATUS__PIPE2_REQUESTED_PWR_STATE__SHIFT 0x0000001d 8227de2bdb3dSTom St Denis #define PIPE3_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT_MASK 0x0000ffffL 8228de2bdb3dSTom St Denis #define PIPE3_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT__SHIFT 0x00000000 8229de2bdb3dSTom St Denis #define PIPE3_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED_MASK 0x00000007L 8230de2bdb3dSTom St Denis #define PIPE3_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED__SHIFT 0x00000000 8231de2bdb3dSTom St Denis #define PIPE3_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED_MASK 0x00000010L 8232de2bdb3dSTom St Denis #define PIPE3_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED__SHIFT 0x00000004 8233de2bdb3dSTom St Denis #define PIPE3_MAX_REQUESTS__MAX_REQUESTS_MASK 0x000003ffL 8234de2bdb3dSTom St Denis #define PIPE3_MAX_REQUESTS__MAX_REQUESTS__SHIFT 0x00000000 8235de2bdb3dSTom St Denis #define PIPE3_PG_CONFIG__PIPE3_POWER_FORCEON_MASK 0x00000001L 8236de2bdb3dSTom St Denis #define PIPE3_PG_CONFIG__PIPE3_POWER_FORCEON__SHIFT 0x00000000 8237de2bdb3dSTom St Denis #define PIPE3_PG_ENABLE__PIPE3_POWER_GATE_MASK 0x00000001L 8238de2bdb3dSTom St Denis #define PIPE3_PG_ENABLE__PIPE3_POWER_GATE__SHIFT 0x00000000 8239de2bdb3dSTom St Denis #define PIPE3_PG_STATUS__PIPE3_DESIRED_PWR_STATE_MASK 0x10000000L 8240de2bdb3dSTom St Denis #define PIPE3_PG_STATUS__PIPE3_DESIRED_PWR_STATE__SHIFT 0x0000001c 8241de2bdb3dSTom St Denis #define PIPE3_PG_STATUS__PIPE3_PGFSM_PWR_STATUS_MASK 0xc0000000L 8242de2bdb3dSTom St Denis #define PIPE3_PG_STATUS__PIPE3_PGFSM_PWR_STATUS__SHIFT 0x0000001e 8243de2bdb3dSTom St Denis #define PIPE3_PG_STATUS__PIPE3_PGFSM_READ_DATA_MASK 0x00ffffffL 8244de2bdb3dSTom St Denis #define PIPE3_PG_STATUS__PIPE3_PGFSM_READ_DATA__SHIFT 0x00000000 8245de2bdb3dSTom St Denis #define PIPE3_PG_STATUS__PIPE3_REQUESTED_PWR_STATE_MASK 0x20000000L 8246de2bdb3dSTom St Denis #define PIPE3_PG_STATUS__PIPE3_REQUESTED_PWR_STATE__SHIFT 0x0000001d 8247de2bdb3dSTom St Denis #define PIPE4_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT_MASK 0x0000ffffL 8248de2bdb3dSTom St Denis #define PIPE4_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT__SHIFT 0x00000000 8249de2bdb3dSTom St Denis #define PIPE4_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED_MASK 0x00000007L 8250de2bdb3dSTom St Denis #define PIPE4_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED__SHIFT 0x00000000 8251de2bdb3dSTom St Denis #define PIPE4_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED_MASK 0x00000010L 8252de2bdb3dSTom St Denis #define PIPE4_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED__SHIFT 0x00000004 8253de2bdb3dSTom St Denis #define PIPE4_MAX_REQUESTS__MAX_REQUESTS_MASK 0x000003ffL 8254de2bdb3dSTom St Denis #define PIPE4_MAX_REQUESTS__MAX_REQUESTS__SHIFT 0x00000000 8255de2bdb3dSTom St Denis #define PIPE4_PG_CONFIG__PIPE4_POWER_FORCEON_MASK 0x00000001L 8256de2bdb3dSTom St Denis #define PIPE4_PG_CONFIG__PIPE4_POWER_FORCEON__SHIFT 0x00000000 8257de2bdb3dSTom St Denis #define PIPE4_PG_ENABLE__PIPE4_POWER_GATE_MASK 0x00000001L 8258de2bdb3dSTom St Denis #define PIPE4_PG_ENABLE__PIPE4_POWER_GATE__SHIFT 0x00000000 8259de2bdb3dSTom St Denis #define PIPE4_PG_STATUS__PIPE4_DESIRED_PWR_STATE_MASK 0x10000000L 8260de2bdb3dSTom St Denis #define PIPE4_PG_STATUS__PIPE4_DESIRED_PWR_STATE__SHIFT 0x0000001c 8261de2bdb3dSTom St Denis #define PIPE4_PG_STATUS__PIPE4_PGFSM_PWR_STATUS_MASK 0xc0000000L 8262de2bdb3dSTom St Denis #define PIPE4_PG_STATUS__PIPE4_PGFSM_PWR_STATUS__SHIFT 0x0000001e 8263de2bdb3dSTom St Denis #define PIPE4_PG_STATUS__PIPE4_PGFSM_READ_DATA_MASK 0x00ffffffL 8264de2bdb3dSTom St Denis #define PIPE4_PG_STATUS__PIPE4_PGFSM_READ_DATA__SHIFT 0x00000000 8265de2bdb3dSTom St Denis #define PIPE4_PG_STATUS__PIPE4_REQUESTED_PWR_STATE_MASK 0x20000000L 8266de2bdb3dSTom St Denis #define PIPE4_PG_STATUS__PIPE4_REQUESTED_PWR_STATE__SHIFT 0x0000001d 8267de2bdb3dSTom St Denis #define PIPE5_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT_MASK 0x0000ffffL 8268de2bdb3dSTom St Denis #define PIPE5_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT__SHIFT 0x00000000 8269de2bdb3dSTom St Denis #define PIPE5_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED_MASK 0x00000007L 8270de2bdb3dSTom St Denis #define PIPE5_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED__SHIFT 0x00000000 8271de2bdb3dSTom St Denis #define PIPE5_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED_MASK 0x00000010L 8272de2bdb3dSTom St Denis #define PIPE5_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED__SHIFT 0x00000004 8273de2bdb3dSTom St Denis #define PIPE5_MAX_REQUESTS__MAX_REQUESTS_MASK 0x000003ffL 8274de2bdb3dSTom St Denis #define PIPE5_MAX_REQUESTS__MAX_REQUESTS__SHIFT 0x00000000 8275de2bdb3dSTom St Denis #define PIPE5_PG_CONFIG__PIPE5_POWER_FORCEON_MASK 0x00000001L 8276de2bdb3dSTom St Denis #define PIPE5_PG_CONFIG__PIPE5_POWER_FORCEON__SHIFT 0x00000000 8277de2bdb3dSTom St Denis #define PIPE5_PG_ENABLE__PIPE5_POWER_GATE_MASK 0x00000001L 8278de2bdb3dSTom St Denis #define PIPE5_PG_ENABLE__PIPE5_POWER_GATE__SHIFT 0x00000000 8279de2bdb3dSTom St Denis #define PIPE5_PG_STATUS__PIPE5_DESIRED_PWR_STATE_MASK 0x10000000L 8280de2bdb3dSTom St Denis #define PIPE5_PG_STATUS__PIPE5_DESIRED_PWR_STATE__SHIFT 0x0000001c 8281de2bdb3dSTom St Denis #define PIPE5_PG_STATUS__PIPE5_PGFSM_PWR_STATUS_MASK 0xc0000000L 8282de2bdb3dSTom St Denis #define PIPE5_PG_STATUS__PIPE5_PGFSM_PWR_STATUS__SHIFT 0x0000001e 8283de2bdb3dSTom St Denis #define PIPE5_PG_STATUS__PIPE5_PGFSM_READ_DATA_MASK 0x00ffffffL 8284de2bdb3dSTom St Denis #define PIPE5_PG_STATUS__PIPE5_PGFSM_READ_DATA__SHIFT 0x00000000 8285de2bdb3dSTom St Denis #define PIPE5_PG_STATUS__PIPE5_REQUESTED_PWR_STATE_MASK 0x20000000L 8286de2bdb3dSTom St Denis #define PIPE5_PG_STATUS__PIPE5_REQUESTED_PWR_STATE__SHIFT 0x0000001d 8287de2bdb3dSTom St Denis #define PIXCLK0_RESYNC_CNTL__DCCG_DEEP_COLOR_CNTL0_MASK 0x00000030L 8288de2bdb3dSTom St Denis #define PIXCLK0_RESYNC_CNTL__DCCG_DEEP_COLOR_CNTL0__SHIFT 0x00000004 8289de2bdb3dSTom St Denis #define PIXCLK0_RESYNC_CNTL__PIXCLK0_RESYNC_ENABLE_MASK 0x00000001L 8290de2bdb3dSTom St Denis #define PIXCLK0_RESYNC_CNTL__PIXCLK0_RESYNC_ENABLE__SHIFT 0x00000000 8291de2bdb3dSTom St Denis #define PIXCLK1_RESYNC_CNTL__DCCG_DEEP_COLOR_CNTL1_MASK 0x00000030L 8292de2bdb3dSTom St Denis #define PIXCLK1_RESYNC_CNTL__DCCG_DEEP_COLOR_CNTL1__SHIFT 0x00000004 8293de2bdb3dSTom St Denis #define PIXCLK1_RESYNC_CNTL__PIXCLK1_RESYNC_ENABLE_MASK 0x00000001L 8294de2bdb3dSTom St Denis #define PIXCLK1_RESYNC_CNTL__PIXCLK1_RESYNC_ENABLE__SHIFT 0x00000000 8295de2bdb3dSTom St Denis #define PIXCLK2_RESYNC_CNTL__DCCG_DEEP_COLOR_CNTL2_MASK 0x00000030L 8296de2bdb3dSTom St Denis #define PIXCLK2_RESYNC_CNTL__DCCG_DEEP_COLOR_CNTL2__SHIFT 0x00000004 8297de2bdb3dSTom St Denis #define PIXCLK2_RESYNC_CNTL__PIXCLK2_RESYNC_ENABLE_MASK 0x00000001L 8298de2bdb3dSTom St Denis #define PIXCLK2_RESYNC_CNTL__PIXCLK2_RESYNC_ENABLE__SHIFT 0x00000000 8299de2bdb3dSTom St Denis #define PLL_ANALOG__PLL_CAL_MODE_MASK 0x0000001fL 8300de2bdb3dSTom St Denis #define PLL_ANALOG__PLL_CAL_MODE__SHIFT 0x00000000 8301de2bdb3dSTom St Denis #define PLL_ANALOG__PLL_CP_MASK 0x00000f00L 8302de2bdb3dSTom St Denis #define PLL_ANALOG__PLL_CP__SHIFT 0x00000008 8303de2bdb3dSTom St Denis #define PLL_ANALOG__PLL_IBIAS_MASK 0xff000000L 8304de2bdb3dSTom St Denis #define PLL_ANALOG__PLL_IBIAS__SHIFT 0x00000018 8305de2bdb3dSTom St Denis #define PLL_ANALOG__PLL_LF_MODE_MASK 0x001ff000L 8306de2bdb3dSTom St Denis #define PLL_ANALOG__PLL_LF_MODE__SHIFT 0x0000000c 8307de2bdb3dSTom St Denis #define PLL_ANALOG__PLL_PFD_PULSE_SEL_MASK 0x00000060L 8308de2bdb3dSTom St Denis #define PLL_ANALOG__PLL_PFD_PULSE_SEL__SHIFT 0x00000005 8309de2bdb3dSTom St Denis #define PLL_CNTL__PLL_ANTIGLITCH_RESETB_MASK 0x00000080L 8310de2bdb3dSTom St Denis #define PLL_CNTL__PLL_ANTIGLITCH_RESETB__SHIFT 0x00000007 8311de2bdb3dSTom St Denis #define PLL_CNTL__PLL_ANTI_GLITCH_RESET_MASK 0x00002000L 8312de2bdb3dSTom St Denis #define PLL_CNTL__PLL_ANTI_GLITCH_RESET__SHIFT 0x0000000d 8313de2bdb3dSTom St Denis #define PLL_CNTL__PLL_BYPASS_CAL_MASK 0x00000004L 8314de2bdb3dSTom St Denis #define PLL_CNTL__PLL_BYPASS_CAL__SHIFT 0x00000002 8315de2bdb3dSTom St Denis #define PLL_CNTL__PLL_CAL_BYPASS_REFDIV_MASK 0x00000400L 8316de2bdb3dSTom St Denis #define PLL_CNTL__PLL_CAL_BYPASS_REFDIV__SHIFT 0x0000000a 8317de2bdb3dSTom St Denis #define PLL_CNTL__PLL_CALIB_DONE_MASK 0x00100000L 8318de2bdb3dSTom St Denis #define PLL_CNTL__PLL_CALIB_DONE__SHIFT 0x00000014 8319de2bdb3dSTom St Denis #define PLL_CNTL__PLL_CALREF_MASK 0x00000300L 8320de2bdb3dSTom St Denis #define PLL_CNTL__PLL_CALREF__SHIFT 0x00000008 8321de2bdb3dSTom St Denis #define PLL_CNTL__PLL_DIG_SPARE_MASK 0xfc000000L 8322de2bdb3dSTom St Denis #define PLL_CNTL__PLL_DIG_SPARE__SHIFT 0x0000001a 8323de2bdb3dSTom St Denis #define PLL_CNTL__PLL_LOCKED_MASK 0x00200000L 8324de2bdb3dSTom St Denis #define PLL_CNTL__PLL_LOCKED__SHIFT 0x00000015 8325de2bdb3dSTom St Denis #define PLL_CNTL__PLL_LOCK_FREQ_SEL_MASK 0x00080000L 8326de2bdb3dSTom St Denis #define PLL_CNTL__PLL_LOCK_FREQ_SEL__SHIFT 0x00000013 8327de2bdb3dSTom St Denis #define PLL_CNTL__PLL_PCIE_REFCLK_SEL_MASK 0x00000040L 8328de2bdb3dSTom St Denis #define PLL_CNTL__PLL_PCIE_REFCLK_SEL__SHIFT 0x00000006 8329de2bdb3dSTom St Denis #define PLL_CNTL__PLL_POST_DIV_SRC_MASK 0x00000008L 8330de2bdb3dSTom St Denis #define PLL_CNTL__PLL_POST_DIV_SRC__SHIFT 0x00000003 8331de2bdb3dSTom St Denis #define PLL_CNTL__PLL_POWER_DOWN_MASK 0x00000002L 8332de2bdb3dSTom St Denis #define PLL_CNTL__PLL_POWER_DOWN__SHIFT 0x00000001 8333de2bdb3dSTom St Denis #define PLL_CNTL__PLL_REFCLK_SEL_MASK 0x00001800L 8334de2bdb3dSTom St Denis #define PLL_CNTL__PLL_REFCLK_SEL__SHIFT 0x0000000b 8335de2bdb3dSTom St Denis #define PLL_CNTL__PLL_REF_DIV_SRC_MASK 0x00070000L 8336de2bdb3dSTom St Denis #define PLL_CNTL__PLL_REF_DIV_SRC__SHIFT 0x00000010 8337de2bdb3dSTom St Denis #define PLL_CNTL__PLL_RESET_MASK 0x00000001L 8338de2bdb3dSTom St Denis #define PLL_CNTL__PLL_RESET__SHIFT 0x00000000 8339de2bdb3dSTom St Denis #define PLL_CNTL__PLL_TIMING_MODE_STATUS_MASK 0x03000000L 8340de2bdb3dSTom St Denis #define PLL_CNTL__PLL_TIMING_MODE_STATUS__SHIFT 0x00000018 8341de2bdb3dSTom St Denis #define PLL_CNTL__PLL_VCOREF_MASK 0x00000030L 8342de2bdb3dSTom St Denis #define PLL_CNTL__PLL_VCOREF__SHIFT 0x00000004 8343de2bdb3dSTom St Denis #define PLL_DEBUG_CNTL__PLL_DEBUG_CLK_SEL_MASK 0x00000f00L 8344de2bdb3dSTom St Denis #define PLL_DEBUG_CNTL__PLL_DEBUG_CLK_SEL__SHIFT 0x00000008 8345de2bdb3dSTom St Denis #define PLL_DEBUG_CNTL__PLL_DEBUG_MUXOUT_SEL_MASK 0x000000f0L 8346de2bdb3dSTom St Denis #define PLL_DEBUG_CNTL__PLL_DEBUG_MUXOUT_SEL__SHIFT 0x00000004 8347de2bdb3dSTom St Denis #define PLL_DEBUG_CNTL__PLL_DEBUG_SIGNALS_ENABLE_MASK 0x00000001L 8348de2bdb3dSTom St Denis #define PLL_DEBUG_CNTL__PLL_DEBUG_SIGNALS_ENABLE__SHIFT 0x00000000 8349de2bdb3dSTom St Denis #define PLL_DISPCLK_CURRENT_DTO_PHASE__PLL_DISPCLK_CURRENT_DTO_PHASE_MASK 0x000001ffL 8350de2bdb3dSTom St Denis #define PLL_DISPCLK_CURRENT_DTO_PHASE__PLL_DISPCLK_CURRENT_DTO_PHASE__SHIFT 0x00000000 8351de2bdb3dSTom St Denis #define PLL_DISPCLK_DTO_CNTL__PLL_DISPCLK_DTO_COMPL_DELAY_MASK 0xff000000L 8352de2bdb3dSTom St Denis #define PLL_DISPCLK_DTO_CNTL__PLL_DISPCLK_DTO_COMPL_DELAY__SHIFT 0x00000018 8353de2bdb3dSTom St Denis #define PLL_DISPCLK_DTO_CNTL__PLL_DISPCLK_DTO_DIS_MASK 0x00010000L 8354de2bdb3dSTom St Denis #define PLL_DISPCLK_DTO_CNTL__PLL_DISPCLK_DTO_DIS__SHIFT 0x00000010 8355de2bdb3dSTom St Denis #define PLL_DISPCLK_DTO_CNTL__PLL_DISPCLK_DTO_PHASE_MASK 0x000001ffL 8356de2bdb3dSTom St Denis #define PLL_DISPCLK_DTO_CNTL__PLL_DISPCLK_DTO_PHASE__SHIFT 0x00000000 8357de2bdb3dSTom St Denis #define PLL_DISPCLK_DTO_CNTL__PLL_DISPCLK_DTO_UPDATE_ACK_MASK 0x00400000L 8358de2bdb3dSTom St Denis #define PLL_DISPCLK_DTO_CNTL__PLL_DISPCLK_DTO_UPDATE_ACK__SHIFT 0x00000016 8359de2bdb3dSTom St Denis #define PLL_DISPCLK_DTO_CNTL__PLL_DISPCLK_DTO_UPDATE_MODE_MASK 0x00060000L 8360de2bdb3dSTom St Denis #define PLL_DISPCLK_DTO_CNTL__PLL_DISPCLK_DTO_UPDATE_MODE__SHIFT 0x00000011 8361de2bdb3dSTom St Denis #define PLL_DISPCLK_DTO_CNTL__PLL_DISPCLK_DTO_UPDATE_PENDING_MASK 0x00100000L 8362de2bdb3dSTom St Denis #define PLL_DISPCLK_DTO_CNTL__PLL_DISPCLK_DTO_UPDATE_PENDING__SHIFT 0x00000014 8363de2bdb3dSTom St Denis #define PLL_DISPCLK_DTO_CNTL__PLL_DISPCLK_DTO_UPDATE_REQ_MASK 0x00200000L 8364de2bdb3dSTom St Denis #define PLL_DISPCLK_DTO_CNTL__PLL_DISPCLK_DTO_UPDATE_REQ__SHIFT 0x00000015 8365de2bdb3dSTom St Denis #define PLL_DS_CNTL__PLL_DS_FRAC_MASK 0x0000ffffL 8366de2bdb3dSTom St Denis #define PLL_DS_CNTL__PLL_DS_FRAC__SHIFT 0x00000000 8367de2bdb3dSTom St Denis #define PLL_DS_CNTL__PLL_DS_MODE_MASK 0x00040000L 8368de2bdb3dSTom St Denis #define PLL_DS_CNTL__PLL_DS_MODE__SHIFT 0x00000012 8369de2bdb3dSTom St Denis #define PLL_DS_CNTL__PLL_DS_ORDER_MASK 0x00030000L 8370de2bdb3dSTom St Denis #define PLL_DS_CNTL__PLL_DS_ORDER__SHIFT 0x00000010 8371de2bdb3dSTom St Denis #define PLL_DS_CNTL__PLL_DS_PRBS_EN_MASK 0x00080000L 8372de2bdb3dSTom St Denis #define PLL_DS_CNTL__PLL_DS_PRBS_EN__SHIFT 0x00000013 8373de2bdb3dSTom St Denis #define PLL_FB_DIV__PLL_FB_DIV_FRACTION_CNTL_MASK 0x00000030L 8374de2bdb3dSTom St Denis #define PLL_FB_DIV__PLL_FB_DIV_FRACTION_CNTL__SHIFT 0x00000004 8375de2bdb3dSTom St Denis #define PLL_FB_DIV__PLL_FB_DIV_FRACTION_MASK 0x0000000fL 8376de2bdb3dSTom St Denis #define PLL_FB_DIV__PLL_FB_DIV_FRACTION__SHIFT 0x00000000 8377de2bdb3dSTom St Denis #define PLL_FB_DIV__PLL_FB_DIV_MASK 0x0fff0000L 8378de2bdb3dSTom St Denis #define PLL_FB_DIV__PLL_FB_DIV__SHIFT 0x00000010 8379de2bdb3dSTom St Denis #define PLL_IDCLK_CNTL__PLL_DIFF_POST_DIV_MASK 0x000f0000L 8380de2bdb3dSTom St Denis #define PLL_IDCLK_CNTL__PLL_DIFF_POST_DIV_RESET_MASK 0x00000100L 8381de2bdb3dSTom St Denis #define PLL_IDCLK_CNTL__PLL_DIFF_POST_DIV_RESET__SHIFT 0x00000008 8382de2bdb3dSTom St Denis #define PLL_IDCLK_CNTL__PLL_DIFF_POST_DIV_SELECT_MASK 0x00001000L 8383de2bdb3dSTom St Denis #define PLL_IDCLK_CNTL__PLL_DIFF_POST_DIV_SELECT__SHIFT 0x0000000c 8384de2bdb3dSTom St Denis #define PLL_IDCLK_CNTL__PLL_DIFF_POST_DIV__SHIFT 0x00000010 8385de2bdb3dSTom St Denis #define PLL_IDCLK_CNTL__PLL_LTDP_IDCLK_DIFF_EN_MASK 0x00000002L 8386de2bdb3dSTom St Denis #define PLL_IDCLK_CNTL__PLL_LTDP_IDCLK_DIFF_EN__SHIFT 0x00000001 8387de2bdb3dSTom St Denis #define PLL_IDCLK_CNTL__PLL_LTDP_IDCLK_EN_MASK 0x00000001L 8388de2bdb3dSTom St Denis #define PLL_IDCLK_CNTL__PLL_LTDP_IDCLK_EN__SHIFT 0x00000000 8389de2bdb3dSTom St Denis #define PLL_IDCLK_CNTL__PLL_TMDP_IDCLK_DIFF_EN_MASK 0x00000008L 8390de2bdb3dSTom St Denis #define PLL_IDCLK_CNTL__PLL_TMDP_IDCLK_DIFF_EN__SHIFT 0x00000003 8391de2bdb3dSTom St Denis #define PLL_IDCLK_CNTL__PLL_TMDP_IDCLK_EN_MASK 0x00000004L 8392de2bdb3dSTom St Denis #define PLL_IDCLK_CNTL__PLL_TMDP_IDCLK_EN__SHIFT 0x00000002 8393de2bdb3dSTom St Denis #define PLL_IDCLK_CNTL__PLL_UNIPHY_IDCLK_DIFF_EN_MASK 0x00000010L 8394de2bdb3dSTom St Denis #define PLL_IDCLK_CNTL__PLL_UNIPHY_IDCLK_DIFF_EN__SHIFT 0x00000004 8395de2bdb3dSTom St Denis #define PLL_POST_DIV__PLL_POST_DIV1P5_DISPCLK_MASK 0x00000080L 8396de2bdb3dSTom St Denis #define PLL_POST_DIV__PLL_POST_DIV1P5_DISPCLK__SHIFT 0x00000007 8397de2bdb3dSTom St Denis #define PLL_POST_DIV__PLL_POST_DIV1P5_DPREFCLK_MASK 0x00008000L 8398de2bdb3dSTom St Denis #define PLL_POST_DIV__PLL_POST_DIV1P5_DPREFCLK__SHIFT 0x0000000f 8399de2bdb3dSTom St Denis #define PLL_POST_DIV__PLL_POST_DIV_DVOCLK_MASK 0x00007f00L 8400de2bdb3dSTom St Denis #define PLL_POST_DIV__PLL_POST_DIV_DVOCLK__SHIFT 0x00000008 8401de2bdb3dSTom St Denis #define PLL_POST_DIV__PLL_POST_DIV_IDCLK_MASK 0x007f0000L 8402de2bdb3dSTom St Denis #define PLL_POST_DIV__PLL_POST_DIV_IDCLK__SHIFT 0x00000010 8403de2bdb3dSTom St Denis #define PLL_POST_DIV__PLL_POST_DIV_PIXCLK_MASK 0x0000007fL 8404de2bdb3dSTom St Denis #define PLL_POST_DIV__PLL_POST_DIV_PIXCLK__SHIFT 0x00000000 8405de2bdb3dSTom St Denis #define PLL_REF_DIV__PLL_CALIBRATION_REF_DIV_MASK 0x0000f000L 8406de2bdb3dSTom St Denis #define PLL_REF_DIV__PLL_CALIBRATION_REF_DIV__SHIFT 0x0000000c 8407de2bdb3dSTom St Denis #define PLL_REF_DIV__PLL_REF_DIV_MASK 0x000003ffL 8408de2bdb3dSTom St Denis #define PLL_REF_DIV__PLL_REF_DIV__SHIFT 0x00000000 8409de2bdb3dSTom St Denis #define PLL_SS_AMOUNT_DSFRAC__PLL_SS_AMOUNT_DSFRAC_MASK 0x0000ffffL 8410de2bdb3dSTom St Denis #define PLL_SS_AMOUNT_DSFRAC__PLL_SS_AMOUNT_DSFRAC__SHIFT 0x00000000 8411de2bdb3dSTom St Denis #define PLL_SS_CNTL__PLL_SS_AMOUNT_FBDIV_MASK 0x000000ffL 8412de2bdb3dSTom St Denis #define PLL_SS_CNTL__PLL_SS_AMOUNT_FBDIV__SHIFT 0x00000000 8413de2bdb3dSTom St Denis #define PLL_SS_CNTL__PLL_SS_AMOUNT_NFRAC_SLIP_MASK 0x00000f00L 8414de2bdb3dSTom St Denis #define PLL_SS_CNTL__PLL_SS_AMOUNT_NFRAC_SLIP__SHIFT 0x00000008 8415de2bdb3dSTom St Denis #define PLL_SS_CNTL__PLL_SS_EN_MASK 0x00001000L 8416de2bdb3dSTom St Denis #define PLL_SS_CNTL__PLL_SS_EN__SHIFT 0x0000000c 8417de2bdb3dSTom St Denis #define PLL_SS_CNTL__PLL_SS_MODE_MASK 0x00002000L 8418de2bdb3dSTom St Denis #define PLL_SS_CNTL__PLL_SS_MODE__SHIFT 0x0000000d 8419de2bdb3dSTom St Denis #define PLL_SS_CNTL__PLL_SS_STEP_SIZE_DSFRAC_MASK 0xffff0000L 8420de2bdb3dSTom St Denis #define PLL_SS_CNTL__PLL_SS_STEP_SIZE_DSFRAC__SHIFT 0x00000010 8421de2bdb3dSTom St Denis #define PLL_UNLOCK_DETECT_CNTL__PLL_UNLOCK_DET_COUNT_MASK 0x00000070L 8422de2bdb3dSTom St Denis #define PLL_UNLOCK_DETECT_CNTL__PLL_UNLOCK_DET_COUNT__SHIFT 0x00000004 8423de2bdb3dSTom St Denis #define PLL_UNLOCK_DETECT_CNTL__PLL_UNLOCK_DETECT_ENABLE_MASK 0x00000001L 8424de2bdb3dSTom St Denis #define PLL_UNLOCK_DETECT_CNTL__PLL_UNLOCK_DETECT_ENABLE__SHIFT 0x00000000 8425de2bdb3dSTom St Denis #define PLL_UNLOCK_DETECT_CNTL__PLL_UNLOCK_DET_RES100_SELECT_MASK 0x00000002L 8426de2bdb3dSTom St Denis #define PLL_UNLOCK_DETECT_CNTL__PLL_UNLOCK_DET_RES100_SELECT__SHIFT 0x00000001 8427de2bdb3dSTom St Denis #define PLL_UNLOCK_DETECT_CNTL__PLL_UNLOCK_STICKY_CLEAR_MASK 0x00000008L 8428de2bdb3dSTom St Denis #define PLL_UNLOCK_DETECT_CNTL__PLL_UNLOCK_STICKY_CLEAR__SHIFT 0x00000003 8429de2bdb3dSTom St Denis #define PLL_UNLOCK_DETECT_CNTL__PLL_UNLOCK_STICKY_STATUS_MASK 0x00000004L 8430de2bdb3dSTom St Denis #define PLL_UNLOCK_DETECT_CNTL__PLL_UNLOCK_STICKY_STATUS__SHIFT 0x00000002 8431de2bdb3dSTom St Denis #define PLL_UPDATE_CNTL__PLL_AUTO_RESET_DISABLE_MASK 0x00010000L 8432de2bdb3dSTom St Denis #define PLL_UPDATE_CNTL__PLL_AUTO_RESET_DISABLE__SHIFT 0x00000010 8433de2bdb3dSTom St Denis #define PLL_UPDATE_CNTL__PLL_UPDATE_PENDING_MASK 0x00000001L 8434de2bdb3dSTom St Denis #define PLL_UPDATE_CNTL__PLL_UPDATE_PENDING__SHIFT 0x00000000 8435de2bdb3dSTom St Denis #define PLL_UPDATE_CNTL__PLL_UPDATE_POINT_MASK 0x00000100L 8436de2bdb3dSTom St Denis #define PLL_UPDATE_CNTL__PLL_UPDATE_POINT__SHIFT 0x00000008 8437de2bdb3dSTom St Denis #define PLL_UPDATE_LOCK__PLL_UPDATE_LOCK_MASK 0x00000001L 8438de2bdb3dSTom St Denis #define PLL_UPDATE_LOCK__PLL_UPDATE_LOCK__SHIFT 0x00000000 8439de2bdb3dSTom St Denis #define PLL_VREG_CNTL__PLL_VREF_SEL_MASK 0x04000000L 8440de2bdb3dSTom St Denis #define PLL_VREG_CNTL__PLL_VREF_SEL__SHIFT 0x0000001a 8441de2bdb3dSTom St Denis #define PLL_VREG_CNTL__PLL_VREG_BIAS_MASK 0xf0000000L 8442de2bdb3dSTom St Denis #define PLL_VREG_CNTL__PLL_VREG_BIAS__SHIFT 0x0000001c 8443de2bdb3dSTom St Denis #define PLL_VREG_CNTL__PLL_VREG_CNTL_MASK 0x000fffffL 8444de2bdb3dSTom St Denis #define PLL_VREG_CNTL__PLL_VREG_CNTL__SHIFT 0x00000000 8445de2bdb3dSTom St Denis #define PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_B_SIGN_MASK 0x00000008L 8446de2bdb3dSTom St Denis #define PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_B_SIGN__SHIFT 0x00000003 8447de2bdb3dSTom St Denis #define PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_BYPASS_MASK 0x00000010L 8448de2bdb3dSTom St Denis #define PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_BYPASS__SHIFT 0x00000004 8449de2bdb3dSTom St Denis #define PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_G_SIGN_MASK 0x00000004L 8450de2bdb3dSTom St Denis #define PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_G_SIGN__SHIFT 0x00000002 8451de2bdb3dSTom St Denis #define PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_R_SIGN_MASK 0x00000002L 8452de2bdb3dSTom St Denis #define PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_R_SIGN__SHIFT 0x00000001 8453de2bdb3dSTom St Denis #define PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_SELECT_MASK 0x00000001L 8454de2bdb3dSTom St Denis #define PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_SELECT__SHIFT 0x00000000 8455de2bdb3dSTom St Denis #define PRESCALE_OVL_CONTROL__OVL_PRESCALE_BYPASS_MASK 0x00000010L 8456de2bdb3dSTom St Denis #define PRESCALE_OVL_CONTROL__OVL_PRESCALE_BYPASS__SHIFT 0x00000004 8457de2bdb3dSTom St Denis #define PRESCALE_OVL_CONTROL__OVL_PRESCALE_CB_SIGN_MASK 0x00000002L 8458de2bdb3dSTom St Denis #define PRESCALE_OVL_CONTROL__OVL_PRESCALE_CB_SIGN__SHIFT 0x00000001 8459de2bdb3dSTom St Denis #define PRESCALE_OVL_CONTROL__OVL_PRESCALE_CR_SIGN_MASK 0x00000008L 8460de2bdb3dSTom St Denis #define PRESCALE_OVL_CONTROL__OVL_PRESCALE_CR_SIGN__SHIFT 0x00000003 8461de2bdb3dSTom St Denis #define PRESCALE_OVL_CONTROL__OVL_PRESCALE_SELECT_MASK 0x00000001L 8462de2bdb3dSTom St Denis #define PRESCALE_OVL_CONTROL__OVL_PRESCALE_SELECT__SHIFT 0x00000000 8463de2bdb3dSTom St Denis #define PRESCALE_OVL_CONTROL__OVL_PRESCALE_Y_SIGN_MASK 0x00000004L 8464de2bdb3dSTom St Denis #define PRESCALE_OVL_CONTROL__OVL_PRESCALE_Y_SIGN__SHIFT 0x00000002 8465de2bdb3dSTom St Denis #define PRESCALE_VALUES_GRPH_B__GRPH_PRESCALE_BIAS_B_MASK 0x0000ffffL 8466de2bdb3dSTom St Denis #define PRESCALE_VALUES_GRPH_B__GRPH_PRESCALE_BIAS_B__SHIFT 0x00000000 8467de2bdb3dSTom St Denis #define PRESCALE_VALUES_GRPH_B__GRPH_PRESCALE_SCALE_B_MASK 0xffff0000L 8468de2bdb3dSTom St Denis #define PRESCALE_VALUES_GRPH_B__GRPH_PRESCALE_SCALE_B__SHIFT 0x00000010 8469de2bdb3dSTom St Denis #define PRESCALE_VALUES_GRPH_G__GRPH_PRESCALE_BIAS_G_MASK 0x0000ffffL 8470de2bdb3dSTom St Denis #define PRESCALE_VALUES_GRPH_G__GRPH_PRESCALE_BIAS_G__SHIFT 0x00000000 8471de2bdb3dSTom St Denis #define PRESCALE_VALUES_GRPH_G__GRPH_PRESCALE_SCALE_G_MASK 0xffff0000L 8472de2bdb3dSTom St Denis #define PRESCALE_VALUES_GRPH_G__GRPH_PRESCALE_SCALE_G__SHIFT 0x00000010 8473de2bdb3dSTom St Denis #define PRESCALE_VALUES_GRPH_R__GRPH_PRESCALE_BIAS_R_MASK 0x0000ffffL 8474de2bdb3dSTom St Denis #define PRESCALE_VALUES_GRPH_R__GRPH_PRESCALE_BIAS_R__SHIFT 0x00000000 8475de2bdb3dSTom St Denis #define PRESCALE_VALUES_GRPH_R__GRPH_PRESCALE_SCALE_R_MASK 0xffff0000L 8476de2bdb3dSTom St Denis #define PRESCALE_VALUES_GRPH_R__GRPH_PRESCALE_SCALE_R__SHIFT 0x00000010 8477de2bdb3dSTom St Denis #define PRESCALE_VALUES_OVL_CB__OVL_PRESCALE_BIAS_CB_MASK 0x0000ffffL 8478de2bdb3dSTom St Denis #define PRESCALE_VALUES_OVL_CB__OVL_PRESCALE_BIAS_CB__SHIFT 0x00000000 8479de2bdb3dSTom St Denis #define PRESCALE_VALUES_OVL_CB__OVL_PRESCALE_SCALE_CB_MASK 0xffff0000L 8480de2bdb3dSTom St Denis #define PRESCALE_VALUES_OVL_CB__OVL_PRESCALE_SCALE_CB__SHIFT 0x00000010 8481de2bdb3dSTom St Denis #define PRESCALE_VALUES_OVL_CR__OVL_PRESCALE_BIAS_CR_MASK 0x0000ffffL 8482de2bdb3dSTom St Denis #define PRESCALE_VALUES_OVL_CR__OVL_PRESCALE_BIAS_CR__SHIFT 0x00000000 8483de2bdb3dSTom St Denis #define PRESCALE_VALUES_OVL_CR__OVL_PRESCALE_SCALE_CR_MASK 0xffff0000L 8484de2bdb3dSTom St Denis #define PRESCALE_VALUES_OVL_CR__OVL_PRESCALE_SCALE_CR__SHIFT 0x00000010 8485de2bdb3dSTom St Denis #define PRESCALE_VALUES_OVL_Y__OVL_PRESCALE_BIAS_Y_MASK 0x0000ffffL 8486de2bdb3dSTom St Denis #define PRESCALE_VALUES_OVL_Y__OVL_PRESCALE_BIAS_Y__SHIFT 0x00000000 8487de2bdb3dSTom St Denis #define PRESCALE_VALUES_OVL_Y__OVL_PRESCALE_SCALE_Y_MASK 0xffff0000L 8488de2bdb3dSTom St Denis #define PRESCALE_VALUES_OVL_Y__OVL_PRESCALE_SCALE_Y__SHIFT 0x00000010 8489de2bdb3dSTom St Denis #define REGAMMA_CNTLA_END_CNTL1__REGAMMA_CNTLA_EXP_REGION_END_MASK 0x0000ffffL 8490de2bdb3dSTom St Denis #define REGAMMA_CNTLA_END_CNTL1__REGAMMA_CNTLA_EXP_REGION_END__SHIFT 0x00000000 8491de2bdb3dSTom St Denis #define REGAMMA_CNTLA_END_CNTL2__REGAMMA_CNTLA_EXP_REGION_END_BASE_MASK 0xffff0000L 8492de2bdb3dSTom St Denis #define REGAMMA_CNTLA_END_CNTL2__REGAMMA_CNTLA_EXP_REGION_END_BASE__SHIFT 0x00000010 8493de2bdb3dSTom St Denis #define REGAMMA_CNTLA_END_CNTL2__REGAMMA_CNTLA_EXP_REGION_END_SLOPE_MASK 0x0000ffffL 8494de2bdb3dSTom St Denis #define REGAMMA_CNTLA_END_CNTL2__REGAMMA_CNTLA_EXP_REGION_END_SLOPE__SHIFT 0x00000000 8495de2bdb3dSTom St Denis #define REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET_MASK 0x000001ffL 8496de2bdb3dSTom St Denis #define REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET__SHIFT 0x00000000 8497de2bdb3dSTom St Denis #define REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L 8498de2bdb3dSTom St Denis #define REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS__SHIFT 0x0000000c 8499de2bdb3dSTom St Denis #define REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET_MASK 0x01ff0000L 8500de2bdb3dSTom St Denis #define REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET__SHIFT 0x00000010 8501de2bdb3dSTom St Denis #define REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L 8502de2bdb3dSTom St Denis #define REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x0000001c 8503de2bdb3dSTom St Denis #define REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION10_LUT_OFFSET_MASK 0x000001ffL 8504de2bdb3dSTom St Denis #define REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION10_LUT_OFFSET__SHIFT 0x00000000 8505de2bdb3dSTom St Denis #define REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L 8506de2bdb3dSTom St Denis #define REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION10_NUM_SEGMENTS__SHIFT 0x0000000c 8507de2bdb3dSTom St Denis #define REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION11_LUT_OFFSET_MASK 0x01ff0000L 8508de2bdb3dSTom St Denis #define REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION11_LUT_OFFSET__SHIFT 0x00000010 8509de2bdb3dSTom St Denis #define REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L 8510de2bdb3dSTom St Denis #define REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x0000001c 8511de2bdb3dSTom St Denis #define REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION12_LUT_OFFSET_MASK 0x000001ffL 8512de2bdb3dSTom St Denis #define REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION12_LUT_OFFSET__SHIFT 0x00000000 8513de2bdb3dSTom St Denis #define REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L 8514de2bdb3dSTom St Denis #define REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION12_NUM_SEGMENTS__SHIFT 0x0000000c 8515de2bdb3dSTom St Denis #define REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION13_LUT_OFFSET_MASK 0x01ff0000L 8516de2bdb3dSTom St Denis #define REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION13_LUT_OFFSET__SHIFT 0x00000010 8517de2bdb3dSTom St Denis #define REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L 8518de2bdb3dSTom St Denis #define REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x0000001c 8519de2bdb3dSTom St Denis #define REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION14_LUT_OFFSET_MASK 0x000001ffL 8520de2bdb3dSTom St Denis #define REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION14_LUT_OFFSET__SHIFT 0x00000000 8521de2bdb3dSTom St Denis #define REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L 8522de2bdb3dSTom St Denis #define REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION14_NUM_SEGMENTS__SHIFT 0x0000000c 8523de2bdb3dSTom St Denis #define REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION15_LUT_OFFSET_MASK 0x01ff0000L 8524de2bdb3dSTom St Denis #define REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION15_LUT_OFFSET__SHIFT 0x00000010 8525de2bdb3dSTom St Denis #define REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L 8526de2bdb3dSTom St Denis #define REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x0000001c 8527de2bdb3dSTom St Denis #define REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION2_LUT_OFFSET_MASK 0x000001ffL 8528de2bdb3dSTom St Denis #define REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION2_LUT_OFFSET__SHIFT 0x00000000 8529de2bdb3dSTom St Denis #define REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L 8530de2bdb3dSTom St Denis #define REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION2_NUM_SEGMENTS__SHIFT 0x0000000c 8531de2bdb3dSTom St Denis #define REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION3_LUT_OFFSET_MASK 0x01ff0000L 8532de2bdb3dSTom St Denis #define REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION3_LUT_OFFSET__SHIFT 0x00000010 8533de2bdb3dSTom St Denis #define REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L 8534de2bdb3dSTom St Denis #define REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x0000001c 8535de2bdb3dSTom St Denis #define REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION4_LUT_OFFSET_MASK 0x000001ffL 8536de2bdb3dSTom St Denis #define REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION4_LUT_OFFSET__SHIFT 0x00000000 8537de2bdb3dSTom St Denis #define REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L 8538de2bdb3dSTom St Denis #define REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION4_NUM_SEGMENTS__SHIFT 0x0000000c 8539de2bdb3dSTom St Denis #define REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION5_LUT_OFFSET_MASK 0x01ff0000L 8540de2bdb3dSTom St Denis #define REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION5_LUT_OFFSET__SHIFT 0x00000010 8541de2bdb3dSTom St Denis #define REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L 8542de2bdb3dSTom St Denis #define REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x0000001c 8543de2bdb3dSTom St Denis #define REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION6_LUT_OFFSET_MASK 0x000001ffL 8544de2bdb3dSTom St Denis #define REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION6_LUT_OFFSET__SHIFT 0x00000000 8545de2bdb3dSTom St Denis #define REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L 8546de2bdb3dSTom St Denis #define REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION6_NUM_SEGMENTS__SHIFT 0x0000000c 8547de2bdb3dSTom St Denis #define REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION7_LUT_OFFSET_MASK 0x01ff0000L 8548de2bdb3dSTom St Denis #define REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION7_LUT_OFFSET__SHIFT 0x00000010 8549de2bdb3dSTom St Denis #define REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L 8550de2bdb3dSTom St Denis #define REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x0000001c 8551de2bdb3dSTom St Denis #define REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION8_LUT_OFFSET_MASK 0x000001ffL 8552de2bdb3dSTom St Denis #define REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION8_LUT_OFFSET__SHIFT 0x00000000 8553de2bdb3dSTom St Denis #define REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L 8554de2bdb3dSTom St Denis #define REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION8_NUM_SEGMENTS__SHIFT 0x0000000c 8555de2bdb3dSTom St Denis #define REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION9_LUT_OFFSET_MASK 0x01ff0000L 8556de2bdb3dSTom St Denis #define REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION9_LUT_OFFSET__SHIFT 0x00000010 8557de2bdb3dSTom St Denis #define REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L 8558de2bdb3dSTom St Denis #define REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x0000001c 8559de2bdb3dSTom St Denis #define REGAMMA_CNTLA_SLOPE_CNTL__REGAMMA_CNTLA_EXP_REGION_LINEAR_SLOPE_MASK 0x0003ffffL 8560de2bdb3dSTom St Denis #define REGAMMA_CNTLA_SLOPE_CNTL__REGAMMA_CNTLA_EXP_REGION_LINEAR_SLOPE__SHIFT 0x00000000 8561de2bdb3dSTom St Denis #define REGAMMA_CNTLA_START_CNTL__REGAMMA_CNTLA_EXP_REGION_START_MASK 0x0003ffffL 8562de2bdb3dSTom St Denis #define REGAMMA_CNTLA_START_CNTL__REGAMMA_CNTLA_EXP_REGION_START_SEGMENT_MASK 0x07f00000L 8563de2bdb3dSTom St Denis #define REGAMMA_CNTLA_START_CNTL__REGAMMA_CNTLA_EXP_REGION_START_SEGMENT__SHIFT 0x00000014 8564de2bdb3dSTom St Denis #define REGAMMA_CNTLA_START_CNTL__REGAMMA_CNTLA_EXP_REGION_START__SHIFT 0x00000000 8565de2bdb3dSTom St Denis #define REGAMMA_CNTLB_END_CNTL1__REGAMMA_CNTLB_EXP_REGION_END_MASK 0x0000ffffL 8566de2bdb3dSTom St Denis #define REGAMMA_CNTLB_END_CNTL1__REGAMMA_CNTLB_EXP_REGION_END__SHIFT 0x00000000 8567de2bdb3dSTom St Denis #define REGAMMA_CNTLB_END_CNTL2__REGAMMA_CNTLB_EXP_REGION_END_BASE_MASK 0xffff0000L 8568de2bdb3dSTom St Denis #define REGAMMA_CNTLB_END_CNTL2__REGAMMA_CNTLB_EXP_REGION_END_BASE__SHIFT 0x00000010 8569de2bdb3dSTom St Denis #define REGAMMA_CNTLB_END_CNTL2__REGAMMA_CNTLB_EXP_REGION_END_SLOPE_MASK 0x0000ffffL 8570de2bdb3dSTom St Denis #define REGAMMA_CNTLB_END_CNTL2__REGAMMA_CNTLB_EXP_REGION_END_SLOPE__SHIFT 0x00000000 8571de2bdb3dSTom St Denis #define REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION0_LUT_OFFSET_MASK 0x000001ffL 8572de2bdb3dSTom St Denis #define REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION0_LUT_OFFSET__SHIFT 0x00000000 8573de2bdb3dSTom St Denis #define REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L 8574de2bdb3dSTom St Denis #define REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION0_NUM_SEGMENTS__SHIFT 0x0000000c 8575de2bdb3dSTom St Denis #define REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION1_LUT_OFFSET_MASK 0x01ff0000L 8576de2bdb3dSTom St Denis #define REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION1_LUT_OFFSET__SHIFT 0x00000010 8577de2bdb3dSTom St Denis #define REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L 8578de2bdb3dSTom St Denis #define REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x0000001c 8579de2bdb3dSTom St Denis #define REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION10_LUT_OFFSET_MASK 0x000001ffL 8580de2bdb3dSTom St Denis #define REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION10_LUT_OFFSET__SHIFT 0x00000000 8581de2bdb3dSTom St Denis #define REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L 8582de2bdb3dSTom St Denis #define REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION10_NUM_SEGMENTS__SHIFT 0x0000000c 8583de2bdb3dSTom St Denis #define REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION11_LUT_OFFSET_MASK 0x01ff0000L 8584de2bdb3dSTom St Denis #define REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION11_LUT_OFFSET__SHIFT 0x00000010 8585de2bdb3dSTom St Denis #define REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L 8586de2bdb3dSTom St Denis #define REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x0000001c 8587de2bdb3dSTom St Denis #define REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION12_LUT_OFFSET_MASK 0x000001ffL 8588de2bdb3dSTom St Denis #define REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION12_LUT_OFFSET__SHIFT 0x00000000 8589de2bdb3dSTom St Denis #define REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L 8590de2bdb3dSTom St Denis #define REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION12_NUM_SEGMENTS__SHIFT 0x0000000c 8591de2bdb3dSTom St Denis #define REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION13_LUT_OFFSET_MASK 0x01ff0000L 8592de2bdb3dSTom St Denis #define REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION13_LUT_OFFSET__SHIFT 0x00000010 8593de2bdb3dSTom St Denis #define REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L 8594de2bdb3dSTom St Denis #define REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x0000001c 8595de2bdb3dSTom St Denis #define REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION14_LUT_OFFSET_MASK 0x000001ffL 8596de2bdb3dSTom St Denis #define REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION14_LUT_OFFSET__SHIFT 0x00000000 8597de2bdb3dSTom St Denis #define REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L 8598de2bdb3dSTom St Denis #define REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION14_NUM_SEGMENTS__SHIFT 0x0000000c 8599de2bdb3dSTom St Denis #define REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION15_LUT_OFFSET_MASK 0x01ff0000L 8600de2bdb3dSTom St Denis #define REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION15_LUT_OFFSET__SHIFT 0x00000010 8601de2bdb3dSTom St Denis #define REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L 8602de2bdb3dSTom St Denis #define REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x0000001c 8603de2bdb3dSTom St Denis #define REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION2_LUT_OFFSET_MASK 0x000001ffL 8604de2bdb3dSTom St Denis #define REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION2_LUT_OFFSET__SHIFT 0x00000000 8605de2bdb3dSTom St Denis #define REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L 8606de2bdb3dSTom St Denis #define REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION2_NUM_SEGMENTS__SHIFT 0x0000000c 8607de2bdb3dSTom St Denis #define REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION3_LUT_OFFSET_MASK 0x01ff0000L 8608de2bdb3dSTom St Denis #define REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION3_LUT_OFFSET__SHIFT 0x00000010 8609de2bdb3dSTom St Denis #define REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L 8610de2bdb3dSTom St Denis #define REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x0000001c 8611de2bdb3dSTom St Denis #define REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION4_LUT_OFFSET_MASK 0x000001ffL 8612de2bdb3dSTom St Denis #define REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION4_LUT_OFFSET__SHIFT 0x00000000 8613de2bdb3dSTom St Denis #define REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L 8614de2bdb3dSTom St Denis #define REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION4_NUM_SEGMENTS__SHIFT 0x0000000c 8615de2bdb3dSTom St Denis #define REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION5_LUT_OFFSET_MASK 0x01ff0000L 8616de2bdb3dSTom St Denis #define REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION5_LUT_OFFSET__SHIFT 0x00000010 8617de2bdb3dSTom St Denis #define REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L 8618de2bdb3dSTom St Denis #define REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x0000001c 8619de2bdb3dSTom St Denis #define REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION6_LUT_OFFSET_MASK 0x000001ffL 8620de2bdb3dSTom St Denis #define REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION6_LUT_OFFSET__SHIFT 0x00000000 8621de2bdb3dSTom St Denis #define REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L 8622de2bdb3dSTom St Denis #define REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION6_NUM_SEGMENTS__SHIFT 0x0000000c 8623de2bdb3dSTom St Denis #define REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION7_LUT_OFFSET_MASK 0x01ff0000L 8624de2bdb3dSTom St Denis #define REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION7_LUT_OFFSET__SHIFT 0x00000010 8625de2bdb3dSTom St Denis #define REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L 8626de2bdb3dSTom St Denis #define REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x0000001c 8627de2bdb3dSTom St Denis #define REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION8_LUT_OFFSET_MASK 0x000001ffL 8628de2bdb3dSTom St Denis #define REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION8_LUT_OFFSET__SHIFT 0x00000000 8629de2bdb3dSTom St Denis #define REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L 8630de2bdb3dSTom St Denis #define REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION8_NUM_SEGMENTS__SHIFT 0x0000000c 8631de2bdb3dSTom St Denis #define REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION9_LUT_OFFSET_MASK 0x01ff0000L 8632de2bdb3dSTom St Denis #define REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION9_LUT_OFFSET__SHIFT 0x00000010 8633de2bdb3dSTom St Denis #define REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L 8634de2bdb3dSTom St Denis #define REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x0000001c 8635de2bdb3dSTom St Denis #define REGAMMA_CNTLB_SLOPE_CNTL__REGAMMA_CNTLB_EXP_REGION_LINEAR_SLOPE_MASK 0x0003ffffL 8636de2bdb3dSTom St Denis #define REGAMMA_CNTLB_SLOPE_CNTL__REGAMMA_CNTLB_EXP_REGION_LINEAR_SLOPE__SHIFT 0x00000000 8637de2bdb3dSTom St Denis #define REGAMMA_CNTLB_START_CNTL__REGAMMA_CNTLB_EXP_REGION_START_MASK 0x0003ffffL 8638de2bdb3dSTom St Denis #define REGAMMA_CNTLB_START_CNTL__REGAMMA_CNTLB_EXP_REGION_START_SEGMENT_MASK 0x07f00000L 8639de2bdb3dSTom St Denis #define REGAMMA_CNTLB_START_CNTL__REGAMMA_CNTLB_EXP_REGION_START_SEGMENT__SHIFT 0x00000014 8640de2bdb3dSTom St Denis #define REGAMMA_CNTLB_START_CNTL__REGAMMA_CNTLB_EXP_REGION_START__SHIFT 0x00000000 8641de2bdb3dSTom St Denis #define REGAMMA_CONTROL__GRPH_REGAMMA_MODE_MASK 0x00000007L 8642de2bdb3dSTom St Denis #define REGAMMA_CONTROL__GRPH_REGAMMA_MODE__SHIFT 0x00000000 8643de2bdb3dSTom St Denis #define REGAMMA_CONTROL__OVL_REGAMMA_MODE_MASK 0x00000070L 8644de2bdb3dSTom St Denis #define REGAMMA_CONTROL__OVL_REGAMMA_MODE__SHIFT 0x00000004 8645de2bdb3dSTom St Denis #define REGAMMA_LUT_DATA__REGAMMA_LUT_DATA_MASK 0x0007ffffL 8646de2bdb3dSTom St Denis #define REGAMMA_LUT_DATA__REGAMMA_LUT_DATA__SHIFT 0x00000000 8647de2bdb3dSTom St Denis #define REGAMMA_LUT_INDEX__REGAMMA_LUT_INDEX_MASK 0x000001ffL 8648de2bdb3dSTom St Denis #define REGAMMA_LUT_INDEX__REGAMMA_LUT_INDEX__SHIFT 0x00000000 8649de2bdb3dSTom St Denis #define REGAMMA_LUT_WRITE_EN_MASK__REGAMMA_LUT_WRITE_EN_MASK_MASK 0x00000007L 8650de2bdb3dSTom St Denis #define REGAMMA_LUT_WRITE_EN_MASK__REGAMMA_LUT_WRITE_EN_MASK__SHIFT 0x00000000 8651de2bdb3dSTom St Denis #define SCL_ALU_CONTROL__SCL_ALU_DISABLE_MASK 0x00000001L 8652de2bdb3dSTom St Denis #define SCL_ALU_CONTROL__SCL_ALU_DISABLE__SHIFT 0x00000000 8653de2bdb3dSTom St Denis #define SCL_BYPASS_CONTROL__SCL_BYPASS_MODE_MASK 0x00000003L 8654de2bdb3dSTom St Denis #define SCL_BYPASS_CONTROL__SCL_BYPASS_MODE__SHIFT 0x00000000 8655de2bdb3dSTom St Denis #define SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_ACK_MASK 0x00000100L 8656de2bdb3dSTom St Denis #define SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_ACK__SHIFT 0x00000008 8657de2bdb3dSTom St Denis #define SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_FLAG_MASK 0x00000001L 8658de2bdb3dSTom St Denis #define SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_FLAG__SHIFT 0x00000000 8659de2bdb3dSTom St Denis #define SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_INT_STATUS_MASK 0x00010000L 8660de2bdb3dSTom St Denis #define SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_INT_STATUS__SHIFT 0x00000010 8661de2bdb3dSTom St Denis #define SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_MASK_MASK 0x00001000L 8662de2bdb3dSTom St Denis #define SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_MASK__SHIFT 0x0000000c 8663de2bdb3dSTom St Denis #define SCL_COEF_RAM_SELECT__SCL_C_RAM_FILTER_TYPE_MASK 0x00030000L 8664de2bdb3dSTom St Denis #define SCL_COEF_RAM_SELECT__SCL_C_RAM_FILTER_TYPE__SHIFT 0x00000010 8665de2bdb3dSTom St Denis #define SCL_COEF_RAM_SELECT__SCL_C_RAM_PHASE_MASK 0x00000f00L 8666de2bdb3dSTom St Denis #define SCL_COEF_RAM_SELECT__SCL_C_RAM_PHASE__SHIFT 0x00000008 8667de2bdb3dSTom St Denis #define SCL_COEF_RAM_SELECT__SCL_C_RAM_TAP_PAIR_IDX_MASK 0x0000000fL 8668de2bdb3dSTom St Denis #define SCL_COEF_RAM_SELECT__SCL_C_RAM_TAP_PAIR_IDX__SHIFT 0x00000000 8669de2bdb3dSTom St Denis #define SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_EVEN_TAP_COEF_EN_MASK 0x00008000L 8670de2bdb3dSTom St Denis #define SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_EVEN_TAP_COEF_EN__SHIFT 0x0000000f 8671de2bdb3dSTom St Denis #define SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_EVEN_TAP_COEF_MASK 0x00003fffL 8672de2bdb3dSTom St Denis #define SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_EVEN_TAP_COEF__SHIFT 0x00000000 8673de2bdb3dSTom St Denis #define SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_ODD_TAP_COEF_EN_MASK 0x80000000L 8674de2bdb3dSTom St Denis #define SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_ODD_TAP_COEF_EN__SHIFT 0x0000001f 8675de2bdb3dSTom St Denis #define SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_ODD_TAP_COEF_MASK 0x3fff0000L 8676de2bdb3dSTom St Denis #define SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_ODD_TAP_COEF__SHIFT 0x00000010 8677de2bdb3dSTom St Denis #define SCL_DEBUG2__SCL_DEBUG2_MASK 0xffffffffL 8678de2bdb3dSTom St Denis #define SCL_DEBUG2__SCL_DEBUG2__SHIFT 0x00000000 8679de2bdb3dSTom St Denis #define SCL_DEBUG__SCL_DEBUG_MASK 0xffffffffL 8680de2bdb3dSTom St Denis #define SCL_DEBUG__SCL_DEBUG__SHIFT 0x00000000 8681de2bdb3dSTom St Denis #define SCL_F_SHARP_CONTROL__SCL_HF_SHARP_EN_MASK 0x00000010L 8682de2bdb3dSTom St Denis #define SCL_F_SHARP_CONTROL__SCL_HF_SHARP_EN__SHIFT 0x00000004 8683de2bdb3dSTom St Denis #define SCL_F_SHARP_CONTROL__SCL_HF_SHARP_SCALE_FACTOR_MASK 0x00000007L 8684de2bdb3dSTom St Denis #define SCL_F_SHARP_CONTROL__SCL_HF_SHARP_SCALE_FACTOR__SHIFT 0x00000000 8685de2bdb3dSTom St Denis #define SCL_F_SHARP_CONTROL__SCL_VF_SHARP_EN_MASK 0x00001000L 8686de2bdb3dSTom St Denis #define SCL_F_SHARP_CONTROL__SCL_VF_SHARP_EN__SHIFT 0x0000000c 8687de2bdb3dSTom St Denis #define SCL_F_SHARP_CONTROL__SCL_VF_SHARP_SCALE_FACTOR_MASK 0x00000700L 8688de2bdb3dSTom St Denis #define SCL_F_SHARP_CONTROL__SCL_VF_SHARP_SCALE_FACTOR__SHIFT 0x00000008 8689de2bdb3dSTom St Denis #define SCL_HORZ_FILTER_CONTROL__SCL_H_FILTER_PICK_NEAREST_MASK 0x00000001L 8690de2bdb3dSTom St Denis #define SCL_HORZ_FILTER_CONTROL__SCL_H_FILTER_PICK_NEAREST__SHIFT 0x00000000 8691de2bdb3dSTom St Denis #define SCL_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO_MASK 0x03ffffffL 8692de2bdb3dSTom St Denis #define SCL_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO__SHIFT 0x00000000 8693de2bdb3dSTom St Denis #define SCLK_CGTT_BLK_CTRL_REG__SCLK_TURN_OFF_DELAY_MASK 0x00000ff0L 8694de2bdb3dSTom St Denis #define SCLK_CGTT_BLK_CTRL_REG__SCLK_TURN_OFF_DELAY__SHIFT 0x00000004 8695de2bdb3dSTom St Denis #define SCLK_CGTT_BLK_CTRL_REG__SCLK_TURN_ON_DELAY_MASK 0x0000000fL 8696de2bdb3dSTom St Denis #define SCLK_CGTT_BLK_CTRL_REG__SCLK_TURN_ON_DELAY__SHIFT 0x00000000 8697de2bdb3dSTom St Denis #define SCL_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR_MASK 0x00000f00L 8698de2bdb3dSTom St Denis #define SCL_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR__SHIFT 0x00000008 8699de2bdb3dSTom St Denis #define SCL_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR_MASK 0x0000000fL 8700de2bdb3dSTom St Denis #define SCL_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR__SHIFT 0x00000000 8701de2bdb3dSTom St Denis #define SCL_MODE_CHANGE_DET1__SCL_ALU_H_SCALE_RATIO_MASK 0x0fffff80L 8702de2bdb3dSTom St Denis #define SCL_MODE_CHANGE_DET1__SCL_ALU_H_SCALE_RATIO__SHIFT 0x00000007 8703de2bdb3dSTom St Denis #define SCL_MODE_CHANGE_DET1__SCL_MODE_CHANGE_ACK_MASK 0x00000010L 8704de2bdb3dSTom St Denis #define SCL_MODE_CHANGE_DET1__SCL_MODE_CHANGE_ACK__SHIFT 0x00000004 8705de2bdb3dSTom St Denis #define SCL_MODE_CHANGE_DET1__SCL_MODE_CHANGE_MASK 0x00000001L 8706de2bdb3dSTom St Denis #define SCL_MODE_CHANGE_DET1__SCL_MODE_CHANGE__SHIFT 0x00000000 8707de2bdb3dSTom St Denis #define SCL_MODE_CHANGE_DET2__SCL_ALU_V_SCALE_RATIO_MASK 0x001fffffL 8708de2bdb3dSTom St Denis #define SCL_MODE_CHANGE_DET2__SCL_ALU_V_SCALE_RATIO__SHIFT 0x00000000 8709de2bdb3dSTom St Denis #define SCL_MODE_CHANGE_DET3__SCL_ALU_SOURCE_HEIGHT_MASK 0x00003fffL 8710de2bdb3dSTom St Denis #define SCL_MODE_CHANGE_DET3__SCL_ALU_SOURCE_HEIGHT__SHIFT 0x00000000 8711de2bdb3dSTom St Denis #define SCL_MODE_CHANGE_DET3__SCL_ALU_SOURCE_WIDTH_MASK 0x3fff0000L 8712de2bdb3dSTom St Denis #define SCL_MODE_CHANGE_DET3__SCL_ALU_SOURCE_WIDTH__SHIFT 0x00000010 8713de2bdb3dSTom St Denis #define SCL_MODE_CHANGE_MASK__SCL_MODE_CHANGE_MASK_MASK 0x00000001L 8714de2bdb3dSTom St Denis #define SCL_MODE_CHANGE_MASK__SCL_MODE_CHANGE_MASK__SHIFT 0x00000000 8715de2bdb3dSTom St Denis #define SCL_TEST_DEBUG_DATA__SCL_TEST_DEBUG_DATA_MASK 0xffffffffL 8716de2bdb3dSTom St Denis #define SCL_TEST_DEBUG_DATA__SCL_TEST_DEBUG_DATA__SHIFT 0x00000000 8717de2bdb3dSTom St Denis #define SCL_TEST_DEBUG_INDEX__SCL_TEST_DEBUG_INDEX_MASK 0x000000ffL 8718de2bdb3dSTom St Denis #define SCL_TEST_DEBUG_INDEX__SCL_TEST_DEBUG_INDEX__SHIFT 0x00000000 8719de2bdb3dSTom St Denis #define SCL_TEST_DEBUG_INDEX__SCL_TEST_DEBUG_WRITE_EN_MASK 0x00000100L 8720de2bdb3dSTom St Denis #define SCL_TEST_DEBUG_INDEX__SCL_TEST_DEBUG_WRITE_EN__SHIFT 0x00000008 8721de2bdb3dSTom St Denis #define SCL_UPDATE__SCL_UPDATE_LOCK_MASK 0x00010000L 8722de2bdb3dSTom St Denis #define SCL_UPDATE__SCL_UPDATE_LOCK__SHIFT 0x00000010 8723de2bdb3dSTom St Denis #define SCL_UPDATE__SCL_UPDATE_PENDING_MASK 0x00000001L 8724de2bdb3dSTom St Denis #define SCL_UPDATE__SCL_UPDATE_PENDING__SHIFT 0x00000000 8725de2bdb3dSTom St Denis #define SCL_UPDATE__SCL_UPDATE_TAKEN_MASK 0x00000100L 8726de2bdb3dSTom St Denis #define SCL_UPDATE__SCL_UPDATE_TAKEN__SHIFT 0x00000008 8727de2bdb3dSTom St Denis #define SCL_VERT_FILTER_CONTROL__SCL_V_FILTER_PICK_NEAREST_MASK 0x00000001L 8728de2bdb3dSTom St Denis #define SCL_VERT_FILTER_CONTROL__SCL_V_FILTER_PICK_NEAREST__SHIFT 0x00000000 8729de2bdb3dSTom St Denis #define SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT_MASK 0x0000ffffL 8730de2bdb3dSTom St Denis #define SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT__SHIFT 0x00000000 8731de2bdb3dSTom St Denis #define SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT_MASK 0x00070000L 8732de2bdb3dSTom St Denis #define SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT__SHIFT 0x00000010 8733de2bdb3dSTom St Denis #define SCL_VERT_FILTER_INIT__SCL_V_INIT_FRAC_MASK 0x0000ffffL 8734de2bdb3dSTom St Denis #define SCL_VERT_FILTER_INIT__SCL_V_INIT_FRAC__SHIFT 0x00000000 8735de2bdb3dSTom St Denis #define SCL_VERT_FILTER_INIT__SCL_V_INIT_INT_MASK 0x00070000L 8736de2bdb3dSTom St Denis #define SCL_VERT_FILTER_INIT__SCL_V_INIT_INT__SHIFT 0x00000010 8737de2bdb3dSTom St Denis #define SCL_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO_MASK 0x03ffffffL 8738de2bdb3dSTom St Denis #define SCL_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO__SHIFT 0x00000000 8739de2bdb3dSTom St Denis #define SEQ00__SEQ_RST0B_MASK 0x00000001L 8740de2bdb3dSTom St Denis #define SEQ00__SEQ_RST0B__SHIFT 0x00000000 8741de2bdb3dSTom St Denis #define SEQ00__SEQ_RST1B_MASK 0x00000002L 8742de2bdb3dSTom St Denis #define SEQ00__SEQ_RST1B__SHIFT 0x00000001 8743de2bdb3dSTom St Denis #define SEQ01__SEQ_DOT8_MASK 0x00000001L 8744de2bdb3dSTom St Denis #define SEQ01__SEQ_DOT8__SHIFT 0x00000000 8745de2bdb3dSTom St Denis #define SEQ01__SEQ_MAXBW_MASK 0x00000020L 8746de2bdb3dSTom St Denis #define SEQ01__SEQ_MAXBW__SHIFT 0x00000005 8747de2bdb3dSTom St Denis #define SEQ01__SEQ_PCLKBY2_MASK 0x00000008L 8748de2bdb3dSTom St Denis #define SEQ01__SEQ_PCLKBY2__SHIFT 0x00000003 8749de2bdb3dSTom St Denis #define SEQ01__SEQ_SHIFT2_MASK 0x00000004L 8750de2bdb3dSTom St Denis #define SEQ01__SEQ_SHIFT2__SHIFT 0x00000002 8751de2bdb3dSTom St Denis #define SEQ01__SEQ_SHIFT4_MASK 0x00000010L 8752de2bdb3dSTom St Denis #define SEQ01__SEQ_SHIFT4__SHIFT 0x00000004 8753de2bdb3dSTom St Denis #define SEQ02__SEQ_MAP0_EN_MASK 0x00000001L 8754de2bdb3dSTom St Denis #define SEQ02__SEQ_MAP0_EN__SHIFT 0x00000000 8755de2bdb3dSTom St Denis #define SEQ02__SEQ_MAP1_EN_MASK 0x00000002L 8756de2bdb3dSTom St Denis #define SEQ02__SEQ_MAP1_EN__SHIFT 0x00000001 8757de2bdb3dSTom St Denis #define SEQ02__SEQ_MAP2_EN_MASK 0x00000004L 8758de2bdb3dSTom St Denis #define SEQ02__SEQ_MAP2_EN__SHIFT 0x00000002 8759de2bdb3dSTom St Denis #define SEQ02__SEQ_MAP3_EN_MASK 0x00000008L 8760de2bdb3dSTom St Denis #define SEQ02__SEQ_MAP3_EN__SHIFT 0x00000003 8761de2bdb3dSTom St Denis #define SEQ03__SEQ_FONT_A0_MASK 0x00000020L 8762de2bdb3dSTom St Denis #define SEQ03__SEQ_FONT_A0__SHIFT 0x00000005 8763de2bdb3dSTom St Denis #define SEQ03__SEQ_FONT_A1_MASK 0x00000004L 8764de2bdb3dSTom St Denis #define SEQ03__SEQ_FONT_A1__SHIFT 0x00000002 8765de2bdb3dSTom St Denis #define SEQ03__SEQ_FONT_A2_MASK 0x00000008L 8766de2bdb3dSTom St Denis #define SEQ03__SEQ_FONT_A2__SHIFT 0x00000003 8767de2bdb3dSTom St Denis #define SEQ03__SEQ_FONT_B0_MASK 0x00000010L 8768de2bdb3dSTom St Denis #define SEQ03__SEQ_FONT_B0__SHIFT 0x00000004 8769de2bdb3dSTom St Denis #define SEQ03__SEQ_FONT_B1_MASK 0x00000001L 8770de2bdb3dSTom St Denis #define SEQ03__SEQ_FONT_B1__SHIFT 0x00000000 8771de2bdb3dSTom St Denis #define SEQ03__SEQ_FONT_B2_MASK 0x00000002L 8772de2bdb3dSTom St Denis #define SEQ03__SEQ_FONT_B2__SHIFT 0x00000001 8773de2bdb3dSTom St Denis #define SEQ04__SEQ_256K_MASK 0x00000002L 8774de2bdb3dSTom St Denis #define SEQ04__SEQ_256K__SHIFT 0x00000001 8775de2bdb3dSTom St Denis #define SEQ04__SEQ_CHAIN_MASK 0x00000008L 8776de2bdb3dSTom St Denis #define SEQ04__SEQ_CHAIN__SHIFT 0x00000003 8777de2bdb3dSTom St Denis #define SEQ04__SEQ_ODDEVEN_MASK 0x00000004L 8778de2bdb3dSTom St Denis #define SEQ04__SEQ_ODDEVEN__SHIFT 0x00000002 8779de2bdb3dSTom St Denis #define SEQ8_DATA__SEQ_DATA_MASK 0x000000ffL 8780de2bdb3dSTom St Denis #define SEQ8_DATA__SEQ_DATA__SHIFT 0x00000000 8781de2bdb3dSTom St Denis #define SEQ8_IDX__SEQ_IDX_MASK 0x00000007L 8782de2bdb3dSTom St Denis #define SEQ8_IDX__SEQ_IDX__SHIFT 0x00000000 8783de2bdb3dSTom St Denis #define SINK_DESCRIPTION0__DESCRIPTION_MASK 0x000000ffL 8784de2bdb3dSTom St Denis #define SINK_DESCRIPTION0__DESCRIPTION__SHIFT 0x00000000 8785de2bdb3dSTom St Denis #define SINK_DESCRIPTION10__DESCRIPTION_MASK 0x000000ffL 8786de2bdb3dSTom St Denis #define SINK_DESCRIPTION10__DESCRIPTION__SHIFT 0x00000000 8787de2bdb3dSTom St Denis #define SINK_DESCRIPTION11__DESCRIPTION_MASK 0x000000ffL 8788de2bdb3dSTom St Denis #define SINK_DESCRIPTION11__DESCRIPTION__SHIFT 0x00000000 8789de2bdb3dSTom St Denis #define SINK_DESCRIPTION12__DESCRIPTION_MASK 0x000000ffL 8790de2bdb3dSTom St Denis #define SINK_DESCRIPTION12__DESCRIPTION__SHIFT 0x00000000 8791de2bdb3dSTom St Denis #define SINK_DESCRIPTION13__DESCRIPTION_MASK 0x000000ffL 8792de2bdb3dSTom St Denis #define SINK_DESCRIPTION13__DESCRIPTION__SHIFT 0x00000000 8793de2bdb3dSTom St Denis #define SINK_DESCRIPTION14__DESCRIPTION_MASK 0x000000ffL 8794de2bdb3dSTom St Denis #define SINK_DESCRIPTION14__DESCRIPTION__SHIFT 0x00000000 8795de2bdb3dSTom St Denis #define SINK_DESCRIPTION15__DESCRIPTION_MASK 0x000000ffL 8796de2bdb3dSTom St Denis #define SINK_DESCRIPTION15__DESCRIPTION__SHIFT 0x00000000 8797de2bdb3dSTom St Denis #define SINK_DESCRIPTION16__DESCRIPTION_MASK 0x000000ffL 8798de2bdb3dSTom St Denis #define SINK_DESCRIPTION16__DESCRIPTION__SHIFT 0x00000000 8799de2bdb3dSTom St Denis #define SINK_DESCRIPTION17__DESCRIPTION_MASK 0x000000ffL 8800de2bdb3dSTom St Denis #define SINK_DESCRIPTION17__DESCRIPTION__SHIFT 0x00000000 8801de2bdb3dSTom St Denis #define SINK_DESCRIPTION1__DESCRIPTION_MASK 0x000000ffL 8802de2bdb3dSTom St Denis #define SINK_DESCRIPTION1__DESCRIPTION__SHIFT 0x00000000 8803de2bdb3dSTom St Denis #define SINK_DESCRIPTION2__DESCRIPTION_MASK 0x000000ffL 8804de2bdb3dSTom St Denis #define SINK_DESCRIPTION2__DESCRIPTION__SHIFT 0x00000000 8805de2bdb3dSTom St Denis #define SINK_DESCRIPTION3__DESCRIPTION_MASK 0x000000ffL 8806de2bdb3dSTom St Denis #define SINK_DESCRIPTION3__DESCRIPTION__SHIFT 0x00000000 8807de2bdb3dSTom St Denis #define SINK_DESCRIPTION4__DESCRIPTION_MASK 0x000000ffL 8808de2bdb3dSTom St Denis #define SINK_DESCRIPTION4__DESCRIPTION__SHIFT 0x00000000 8809de2bdb3dSTom St Denis #define SINK_DESCRIPTION5__DESCRIPTION_MASK 0x000000ffL 8810de2bdb3dSTom St Denis #define SINK_DESCRIPTION5__DESCRIPTION__SHIFT 0x00000000 8811de2bdb3dSTom St Denis #define SINK_DESCRIPTION6__DESCRIPTION_MASK 0x000000ffL 8812de2bdb3dSTom St Denis #define SINK_DESCRIPTION6__DESCRIPTION__SHIFT 0x00000000 8813de2bdb3dSTom St Denis #define SINK_DESCRIPTION7__DESCRIPTION_MASK 0x000000ffL 8814de2bdb3dSTom St Denis #define SINK_DESCRIPTION7__DESCRIPTION__SHIFT 0x00000000 8815de2bdb3dSTom St Denis #define SINK_DESCRIPTION8__DESCRIPTION_MASK 0x000000ffL 8816de2bdb3dSTom St Denis #define SINK_DESCRIPTION8__DESCRIPTION__SHIFT 0x00000000 8817de2bdb3dSTom St Denis #define SINK_DESCRIPTION9__DESCRIPTION_MASK 0x000000ffL 8818de2bdb3dSTom St Denis #define SINK_DESCRIPTION9__DESCRIPTION__SHIFT 0x00000000 8819de2bdb3dSTom St Denis #define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE0_MASK 0x000000ffL 8820de2bdb3dSTom St Denis #define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE0__SHIFT 0x00000000 8821de2bdb3dSTom St Denis #define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE1_MASK 0x0000ff00L 8822de2bdb3dSTom St Denis #define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE1__SHIFT 0x00000008 8823de2bdb3dSTom St Denis #define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE2_MASK 0x00ff0000L 8824de2bdb3dSTom St Denis #define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE2__SHIFT 0x00000010 8825de2bdb3dSTom St Denis #define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE3_MASK 0xff000000L 8826de2bdb3dSTom St Denis #define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE3__SHIFT 0x00000018 8827de2bdb3dSTom St Denis #define SLAVE_COMM_CNTL_REG__COMM_PORT_MSG_TO_HOST_IN_PROGRESS_MASK 0x00000100L 8828de2bdb3dSTom St Denis #define SLAVE_COMM_CNTL_REG__COMM_PORT_MSG_TO_HOST_IN_PROGRESS__SHIFT 0x00000008 8829de2bdb3dSTom St Denis #define SLAVE_COMM_CNTL_REG__SLAVE_COMM_INTERRUPT_MASK 0x00000001L 8830de2bdb3dSTom St Denis #define SLAVE_COMM_CNTL_REG__SLAVE_COMM_INTERRUPT__SHIFT 0x00000000 8831de2bdb3dSTom St Denis #define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE0_MASK 0x000000ffL 8832de2bdb3dSTom St Denis #define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE0__SHIFT 0x00000000 8833de2bdb3dSTom St Denis #define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE1_MASK 0x0000ff00L 8834de2bdb3dSTom St Denis #define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE1__SHIFT 0x00000008 8835de2bdb3dSTom St Denis #define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE2_MASK 0x00ff0000L 8836de2bdb3dSTom St Denis #define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE2__SHIFT 0x00000010 8837de2bdb3dSTom St Denis #define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE3_MASK 0xff000000L 8838de2bdb3dSTom St Denis #define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE3__SHIFT 0x00000018 8839de2bdb3dSTom St Denis #define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE0_MASK 0x000000ffL 8840de2bdb3dSTom St Denis #define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE0__SHIFT 0x00000000 8841de2bdb3dSTom St Denis #define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE1_MASK 0x0000ff00L 8842de2bdb3dSTom St Denis #define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE1__SHIFT 0x00000008 8843de2bdb3dSTom St Denis #define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE2_MASK 0x00ff0000L 8844de2bdb3dSTom St Denis #define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE2__SHIFT 0x00000010 8845de2bdb3dSTom St Denis #define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE3_MASK 0xff000000L 8846de2bdb3dSTom St Denis #define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE3__SHIFT 0x00000018 8847de2bdb3dSTom St Denis #define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE0_MASK 0x000000ffL 8848de2bdb3dSTom St Denis #define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE0__SHIFT 0x00000000 8849de2bdb3dSTom St Denis #define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE1_MASK 0x0000ff00L 8850de2bdb3dSTom St Denis #define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE1__SHIFT 0x00000008 8851de2bdb3dSTom St Denis #define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE2_MASK 0x00ff0000L 8852de2bdb3dSTom St Denis #define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE2__SHIFT 0x00000010 8853de2bdb3dSTom St Denis #define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE3_MASK 0xff000000L 8854de2bdb3dSTom St Denis #define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE3__SHIFT 0x00000018 8855de2bdb3dSTom St Denis #define SYMCLKA_CLOCK_ENABLE__SYMCLKA_CLOCK_ENABLE_MASK 0x00000001L 8856de2bdb3dSTom St Denis #define SYMCLKA_CLOCK_ENABLE__SYMCLKA_CLOCK_ENABLE__SHIFT 0x00000000 8857de2bdb3dSTom St Denis #define SYMCLKA_CLOCK_ENABLE__SYMCLKA_FE_FORCE_EN_MASK 0x00000010L 8858de2bdb3dSTom St Denis #define SYMCLKA_CLOCK_ENABLE__SYMCLKA_FE_FORCE_EN__SHIFT 0x00000004 8859de2bdb3dSTom St Denis #define SYMCLKA_CLOCK_ENABLE__SYMCLKA_FE_FORCE_SRC_MASK 0x00000700L 8860de2bdb3dSTom St Denis #define SYMCLKA_CLOCK_ENABLE__SYMCLKA_FE_FORCE_SRC__SHIFT 0x00000008 8861de2bdb3dSTom St Denis #define SYMCLKB_CLOCK_ENABLE__SYMCLKB_CLOCK_ENABLE_MASK 0x00000001L 8862de2bdb3dSTom St Denis #define SYMCLKB_CLOCK_ENABLE__SYMCLKB_CLOCK_ENABLE__SHIFT 0x00000000 8863de2bdb3dSTom St Denis #define SYMCLKB_CLOCK_ENABLE__SYMCLKB_FE_FORCE_EN_MASK 0x00000010L 8864de2bdb3dSTom St Denis #define SYMCLKB_CLOCK_ENABLE__SYMCLKB_FE_FORCE_EN__SHIFT 0x00000004 8865de2bdb3dSTom St Denis #define SYMCLKB_CLOCK_ENABLE__SYMCLKB_FE_FORCE_SRC_MASK 0x00000700L 8866de2bdb3dSTom St Denis #define SYMCLKB_CLOCK_ENABLE__SYMCLKB_FE_FORCE_SRC__SHIFT 0x00000008 8867de2bdb3dSTom St Denis #define SYMCLKC_CLOCK_ENABLE__SYMCLKC_CLOCK_ENABLE_MASK 0x00000001L 8868de2bdb3dSTom St Denis #define SYMCLKC_CLOCK_ENABLE__SYMCLKC_CLOCK_ENABLE__SHIFT 0x00000000 8869de2bdb3dSTom St Denis #define SYMCLKC_CLOCK_ENABLE__SYMCLKC_FE_FORCE_EN_MASK 0x00000010L 8870de2bdb3dSTom St Denis #define SYMCLKC_CLOCK_ENABLE__SYMCLKC_FE_FORCE_EN__SHIFT 0x00000004 8871de2bdb3dSTom St Denis #define SYMCLKC_CLOCK_ENABLE__SYMCLKC_FE_FORCE_SRC_MASK 0x00000700L 8872de2bdb3dSTom St Denis #define SYMCLKC_CLOCK_ENABLE__SYMCLKC_FE_FORCE_SRC__SHIFT 0x00000008 8873de2bdb3dSTom St Denis #define SYMCLKD_CLOCK_ENABLE__SYMCLKD_CLOCK_ENABLE_MASK 0x00000001L 8874de2bdb3dSTom St Denis #define SYMCLKD_CLOCK_ENABLE__SYMCLKD_CLOCK_ENABLE__SHIFT 0x00000000 8875de2bdb3dSTom St Denis #define SYMCLKD_CLOCK_ENABLE__SYMCLKD_FE_FORCE_EN_MASK 0x00000010L 8876de2bdb3dSTom St Denis #define SYMCLKD_CLOCK_ENABLE__SYMCLKD_FE_FORCE_EN__SHIFT 0x00000004 8877de2bdb3dSTom St Denis #define SYMCLKD_CLOCK_ENABLE__SYMCLKD_FE_FORCE_SRC_MASK 0x00000700L 8878de2bdb3dSTom St Denis #define SYMCLKD_CLOCK_ENABLE__SYMCLKD_FE_FORCE_SRC__SHIFT 0x00000008 8879de2bdb3dSTom St Denis #define SYMCLKE_CLOCK_ENABLE__SYMCLKE_CLOCK_ENABLE_MASK 0x00000001L 8880de2bdb3dSTom St Denis #define SYMCLKE_CLOCK_ENABLE__SYMCLKE_CLOCK_ENABLE__SHIFT 0x00000000 8881de2bdb3dSTom St Denis #define SYMCLKE_CLOCK_ENABLE__SYMCLKE_FE_FORCE_EN_MASK 0x00000010L 8882de2bdb3dSTom St Denis #define SYMCLKE_CLOCK_ENABLE__SYMCLKE_FE_FORCE_EN__SHIFT 0x00000004 8883de2bdb3dSTom St Denis #define SYMCLKE_CLOCK_ENABLE__SYMCLKE_FE_FORCE_SRC_MASK 0x00000700L 8884de2bdb3dSTom St Denis #define SYMCLKE_CLOCK_ENABLE__SYMCLKE_FE_FORCE_SRC__SHIFT 0x00000008 8885de2bdb3dSTom St Denis #define SYMCLKF_CLOCK_ENABLE__SYMCLKF_CLOCK_ENABLE_MASK 0x00000001L 8886de2bdb3dSTom St Denis #define SYMCLKF_CLOCK_ENABLE__SYMCLKF_CLOCK_ENABLE__SHIFT 0x00000000 8887de2bdb3dSTom St Denis #define SYMCLKF_CLOCK_ENABLE__SYMCLKF_FE_FORCE_EN_MASK 0x00000010L 8888de2bdb3dSTom St Denis #define SYMCLKF_CLOCK_ENABLE__SYMCLKF_FE_FORCE_EN__SHIFT 0x00000004 8889de2bdb3dSTom St Denis #define SYMCLKF_CLOCK_ENABLE__SYMCLKF_FE_FORCE_SRC_MASK 0x00000700L 8890de2bdb3dSTom St Denis #define SYMCLKF_CLOCK_ENABLE__SYMCLKF_FE_FORCE_SRC__SHIFT 0x00000008 8891de2bdb3dSTom St Denis #define TMDS_CNTL__TMDS_COLOR_FORMAT_MASK 0x00000300L 8892de2bdb3dSTom St Denis #define TMDS_CNTL__TMDS_COLOR_FORMAT__SHIFT 0x00000008 8893de2bdb3dSTom St Denis #define TMDS_CNTL__TMDS_PIXEL_ENCODING_MASK 0x00000010L 8894de2bdb3dSTom St Denis #define TMDS_CNTL__TMDS_PIXEL_ENCODING__SHIFT 0x00000004 8895de2bdb3dSTom St Denis #define TMDS_CNTL__TMDS_SYNC_PHASE_MASK 0x00000001L 8896de2bdb3dSTom St Denis #define TMDS_CNTL__TMDS_SYNC_PHASE__SHIFT 0x00000000 8897de2bdb3dSTom St Denis #define TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY_MASK 0x00000300L 8898de2bdb3dSTom St Denis #define TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY__SHIFT 0x00000008 8899de2bdb3dSTom St Denis #define TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT_MASK 0x00000003L 8900de2bdb3dSTom St Denis #define TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT__SHIFT 0x00000000 8901de2bdb3dSTom St Denis #define TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN_MASK 0x00000001L 8902de2bdb3dSTom St Denis #define TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN__SHIFT 0x00000000 8903de2bdb3dSTom St Denis #define TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN_MASK 0x00000002L 8904de2bdb3dSTom St Denis #define TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN__SHIFT 0x00000001 8905de2bdb3dSTom St Denis #define TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN_MASK 0x00000004L 8906de2bdb3dSTom St Denis #define TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN__SHIFT 0x00000002 8907de2bdb3dSTom St Denis #define TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN_MASK 0x00000008L 8908de2bdb3dSTom St Denis #define TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN__SHIFT 0x00000003 8909de2bdb3dSTom St Denis #define TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN_MASK 0x80000000L 8910de2bdb3dSTom St Denis #define TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN__SHIFT 0x0000001f 8911de2bdb3dSTom St Denis #define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY_MASK 0x00000070L 8912de2bdb3dSTom St Denis #define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY__SHIFT 0x00000004 8913de2bdb3dSTom St Denis #define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT_MASK 0x00000080L 8914de2bdb3dSTom St Denis #define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT__SHIFT 0x00000007 8915de2bdb3dSTom St Denis #define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION_MASK 0x00000300L 8916de2bdb3dSTom St Denis #define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION__SHIFT 0x00000008 8917de2bdb3dSTom St Denis #define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL_MASK 0x0000000fL 8918de2bdb3dSTom St Denis #define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL__SHIFT 0x00000000 8919de2bdb3dSTom St Denis #define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT_MASK 0x00000800L 8920de2bdb3dSTom St Denis #define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT__SHIFT 0x0000000b 8921de2bdb3dSTom St Denis #define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN_MASK 0x00001000L 8922de2bdb3dSTom St Denis #define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN__SHIFT 0x0000000c 8923de2bdb3dSTom St Denis #define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH_MASK 0x00000400L 8924de2bdb3dSTom St Denis #define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH__SHIFT 0x0000000a 8925de2bdb3dSTom St Denis #define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY_MASK 0x00700000L 8926de2bdb3dSTom St Denis #define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY__SHIFT 0x00000014 8927de2bdb3dSTom St Denis #define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT_MASK 0x00800000L 8928de2bdb3dSTom St Denis #define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT__SHIFT 0x00000017 8929de2bdb3dSTom St Denis #define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION_MASK 0x03000000L 8930de2bdb3dSTom St Denis #define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION__SHIFT 0x00000018 8931de2bdb3dSTom St Denis #define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL_MASK 0x000f0000L 8932de2bdb3dSTom St Denis #define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL__SHIFT 0x00000010 8933de2bdb3dSTom St Denis #define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT_MASK 0x08000000L 8934de2bdb3dSTom St Denis #define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT__SHIFT 0x0000001b 8935de2bdb3dSTom St Denis #define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN_MASK 0x10000000L 8936de2bdb3dSTom St Denis #define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN__SHIFT 0x0000001c 8937de2bdb3dSTom St Denis #define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH_MASK 0x04000000L 8938de2bdb3dSTom St Denis #define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH__SHIFT 0x0000001a 8939de2bdb3dSTom St Denis #define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY_MASK 0x00000070L 8940de2bdb3dSTom St Denis #define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY__SHIFT 0x00000004 8941de2bdb3dSTom St Denis #define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT_MASK 0x00000080L 8942de2bdb3dSTom St Denis #define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT__SHIFT 0x00000007 8943de2bdb3dSTom St Denis #define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION_MASK 0x00000300L 8944de2bdb3dSTom St Denis #define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION__SHIFT 0x00000008 8945de2bdb3dSTom St Denis #define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL_MASK 0x0000000fL 8946de2bdb3dSTom St Denis #define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL__SHIFT 0x00000000 8947de2bdb3dSTom St Denis #define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT_MASK 0x00000800L 8948de2bdb3dSTom St Denis #define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT__SHIFT 0x0000000b 8949de2bdb3dSTom St Denis #define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN_MASK 0x00001000L 8950de2bdb3dSTom St Denis #define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN__SHIFT 0x0000000c 8951de2bdb3dSTom St Denis #define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH_MASK 0x00000400L 8952de2bdb3dSTom St Denis #define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH__SHIFT 0x0000000a 8953de2bdb3dSTom St Denis #define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY_MASK 0x00700000L 8954de2bdb3dSTom St Denis #define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY__SHIFT 0x00000014 8955de2bdb3dSTom St Denis #define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT_MASK 0x00800000L 8956de2bdb3dSTom St Denis #define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT__SHIFT 0x00000017 8957de2bdb3dSTom St Denis #define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION_MASK 0x03000000L 8958de2bdb3dSTom St Denis #define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION__SHIFT 0x00000018 8959de2bdb3dSTom St Denis #define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL_MASK 0x000f0000L 8960de2bdb3dSTom St Denis #define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL__SHIFT 0x00000010 8961de2bdb3dSTom St Denis #define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT_MASK 0x08000000L 8962de2bdb3dSTom St Denis #define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT__SHIFT 0x0000001b 8963de2bdb3dSTom St Denis #define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN_MASK 0x10000000L 8964de2bdb3dSTom St Denis #define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN__SHIFT 0x0000001c 8965de2bdb3dSTom St Denis #define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH_MASK 0x04000000L 8966de2bdb3dSTom St Denis #define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH__SHIFT 0x0000001a 8967de2bdb3dSTom St Denis #define TMDS_CTL_BITS__TMDS_CTL0_MASK 0x00000001L 8968de2bdb3dSTom St Denis #define TMDS_CTL_BITS__TMDS_CTL0__SHIFT 0x00000000 8969de2bdb3dSTom St Denis #define TMDS_CTL_BITS__TMDS_CTL1_MASK 0x00000100L 8970de2bdb3dSTom St Denis #define TMDS_CTL_BITS__TMDS_CTL1__SHIFT 0x00000008 8971de2bdb3dSTom St Denis #define TMDS_CTL_BITS__TMDS_CTL2_MASK 0x00010000L 8972de2bdb3dSTom St Denis #define TMDS_CTL_BITS__TMDS_CTL2__SHIFT 0x00000010 8973de2bdb3dSTom St Denis #define TMDS_CTL_BITS__TMDS_CTL3_MASK 0x01000000L 8974de2bdb3dSTom St Denis #define TMDS_CTL_BITS__TMDS_CTL3__SHIFT 0x00000018 8975de2bdb3dSTom St Denis #define TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN_MASK 0x00000001L 8976de2bdb3dSTom St Denis #define TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN__SHIFT 0x00000000 8977de2bdb3dSTom St Denis #define TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE_MASK 0x01000000L 8978de2bdb3dSTom St Denis #define TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE__SHIFT 0x00000018 8979de2bdb3dSTom St Denis #define TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN_MASK 0x00000100L 8980de2bdb3dSTom St Denis #define TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN__SHIFT 0x00000008 8981de2bdb3dSTom St Denis #define TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN_MASK 0x000f0000L 8982de2bdb3dSTom St Denis #define TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN__SHIFT 0x00000010 8983de2bdb3dSTom St Denis #define TMDS_DCBALANCER_CONTROL__TMDS_SYNC_DCBAL_EN_MASK 0x00000070L 8984de2bdb3dSTom St Denis #define TMDS_DCBALANCER_CONTROL__TMDS_SYNC_DCBAL_EN__SHIFT 0x00000004 8985de2bdb3dSTom St Denis #define TMDS_DEBUG__TMDS_DEBUG_DE_EN_MASK 0x02000000L 8986de2bdb3dSTom St Denis #define TMDS_DEBUG__TMDS_DEBUG_DE_EN__SHIFT 0x00000019 8987de2bdb3dSTom St Denis #define TMDS_DEBUG__TMDS_DEBUG_DE_MASK 0x01000000L 8988de2bdb3dSTom St Denis #define TMDS_DEBUG__TMDS_DEBUG_DE__SHIFT 0x00000018 8989de2bdb3dSTom St Denis #define TMDS_DEBUG__TMDS_DEBUG_EN_MASK 0x00000001L 8990de2bdb3dSTom St Denis #define TMDS_DEBUG__TMDS_DEBUG_EN__SHIFT 0x00000000 8991de2bdb3dSTom St Denis #define TMDS_DEBUG__TMDS_DEBUG_HSYNC_EN_MASK 0x00000200L 8992de2bdb3dSTom St Denis #define TMDS_DEBUG__TMDS_DEBUG_HSYNC_EN__SHIFT 0x00000009 8993de2bdb3dSTom St Denis #define TMDS_DEBUG__TMDS_DEBUG_HSYNC_MASK 0x00000100L 8994de2bdb3dSTom St Denis #define TMDS_DEBUG__TMDS_DEBUG_HSYNC__SHIFT 0x00000008 8995de2bdb3dSTom St Denis #define TMDS_DEBUG__TMDS_DEBUG_VSYNC_EN_MASK 0x00020000L 8996de2bdb3dSTom St Denis #define TMDS_DEBUG__TMDS_DEBUG_VSYNC_EN__SHIFT 0x00000011 8997de2bdb3dSTom St Denis #define TMDS_DEBUG__TMDS_DEBUG_VSYNC_MASK 0x00010000L 8998de2bdb3dSTom St Denis #define TMDS_DEBUG__TMDS_DEBUG_VSYNC__SHIFT 0x00000010 8999de2bdb3dSTom St Denis #define TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL_MASK 0x00000003L 9000de2bdb3dSTom St Denis #define TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL__SHIFT 0x00000000 9001de2bdb3dSTom St Denis #define TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0_MASK 0x000003ffL 9002de2bdb3dSTom St Denis #define TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0__SHIFT 0x00000000 9003de2bdb3dSTom St Denis #define TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1_MASK 0x03ff0000L 9004de2bdb3dSTom St Denis #define TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1__SHIFT 0x00000010 9005de2bdb3dSTom St Denis #define TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2_MASK 0x000003ffL 9006de2bdb3dSTom St Denis #define TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2__SHIFT 0x00000000 9007de2bdb3dSTom St Denis #define TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3_MASK 0x03ff0000L 9008de2bdb3dSTom St Denis #define TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3__SHIFT 0x00000010 9009de2bdb3dSTom St Denis #define UNIPHYAB_TPG_CONTROL__UNIPHYAB_STATIC_TEST_PATTERN_MASK 0x000003ffL 9010de2bdb3dSTom St Denis #define UNIPHYAB_TPG_CONTROL__UNIPHYAB_STATIC_TEST_PATTERN__SHIFT 0x00000000 9011de2bdb3dSTom St Denis #define UNIPHYAB_TPG_CONTROL__UNIPHYAB_TPG_EN_MASK 0x00010000L 9012de2bdb3dSTom St Denis #define UNIPHYAB_TPG_CONTROL__UNIPHYAB_TPG_EN__SHIFT 0x00000010 9013de2bdb3dSTom St Denis #define UNIPHYAB_TPG_CONTROL__UNIPHYAB_TPG_SEL_MASK 0x000e0000L 9014de2bdb3dSTom St Denis #define UNIPHYAB_TPG_CONTROL__UNIPHYAB_TPG_SEL__SHIFT 0x00000011 9015de2bdb3dSTom St Denis #define UNIPHYAB_TPG_SEED__UNIPHYAB_TPG_SEED_MASK 0x007fffffL 9016de2bdb3dSTom St Denis #define UNIPHYAB_TPG_SEED__UNIPHYAB_TPG_SEED__SHIFT 0x00000000 9017de2bdb3dSTom St Denis #define UNIPHY_ANG_BIST_CNTL__UNIPHY_ANG_BIST_ERROR_MASK 0x001f0000L 9018de2bdb3dSTom St Denis #define UNIPHY_ANG_BIST_CNTL__UNIPHY_ANG_BIST_ERROR__SHIFT 0x00000010 9019de2bdb3dSTom St Denis #define UNIPHY_ANG_BIST_CNTL__UNIPHY_ANG_BIST_RESET_MASK 0x00000002L 9020de2bdb3dSTom St Denis #define UNIPHY_ANG_BIST_CNTL__UNIPHY_ANG_BIST_RESET__SHIFT 0x00000001 9021de2bdb3dSTom St Denis #define UNIPHY_ANG_BIST_CNTL__UNIPHY_PRESETB_MASK 0x01000000L 9022de2bdb3dSTom St Denis #define UNIPHY_ANG_BIST_CNTL__UNIPHY_PRESETB__SHIFT 0x00000018 9023de2bdb3dSTom St Denis #define UNIPHY_ANG_BIST_CNTL__UNIPHY_RX_BIAS_MASK 0x00000f00L 9024de2bdb3dSTom St Denis #define UNIPHY_ANG_BIST_CNTL__UNIPHY_RX_BIAS__SHIFT 0x00000008 9025de2bdb3dSTom St Denis #define UNIPHY_ANG_BIST_CNTL__UNIPHY_TEST_RX_EN_MASK 0x00000001L 9026de2bdb3dSTom St Denis #define UNIPHY_ANG_BIST_CNTL__UNIPHY_TEST_RX_EN__SHIFT 0x00000000 9027de2bdb3dSTom St Denis #define UNIPHYCD_TPG_CONTROL__UNIPHYCD_STATIC_TEST_PATTERN_MASK 0x000003ffL 9028de2bdb3dSTom St Denis #define UNIPHYCD_TPG_CONTROL__UNIPHYCD_STATIC_TEST_PATTERN__SHIFT 0x00000000 9029de2bdb3dSTom St Denis #define UNIPHYCD_TPG_CONTROL__UNIPHYCD_TPG_EN_MASK 0x00010000L 9030de2bdb3dSTom St Denis #define UNIPHYCD_TPG_CONTROL__UNIPHYCD_TPG_EN__SHIFT 0x00000010 9031de2bdb3dSTom St Denis #define UNIPHYCD_TPG_CONTROL__UNIPHYCD_TPG_SEL_MASK 0x000e0000L 9032de2bdb3dSTom St Denis #define UNIPHYCD_TPG_CONTROL__UNIPHYCD_TPG_SEL__SHIFT 0x00000011 9033de2bdb3dSTom St Denis #define UNIPHYCD_TPG_SEED__UNIPHYCD_TPG_SEED_MASK 0x007fffffL 9034de2bdb3dSTom St Denis #define UNIPHYCD_TPG_SEED__UNIPHYCD_TPG_SEED__SHIFT 0x00000000 9035de2bdb3dSTom St Denis #define UNIPHY_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE_MASK 0x00000003L 9036de2bdb3dSTom St Denis #define UNIPHY_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE__SHIFT 0x00000000 9037de2bdb3dSTom St Denis #define UNIPHY_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE_MASK 0x00000300L 9038de2bdb3dSTom St Denis #define UNIPHY_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE__SHIFT 0x00000008 9039de2bdb3dSTom St Denis #define UNIPHY_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE_MASK 0x00030000L 9040de2bdb3dSTom St Denis #define UNIPHY_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE__SHIFT 0x00000010 9041de2bdb3dSTom St Denis #define UNIPHY_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE_MASK 0x03000000L 9042de2bdb3dSTom St Denis #define UNIPHY_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE__SHIFT 0x00000018 9043de2bdb3dSTom St Denis #define UNIPHY_DATA_SYNCHRONIZATION__UNIPHY_DSYN_ERROR_MASK 0x00000040L 9044de2bdb3dSTom St Denis #define UNIPHY_DATA_SYNCHRONIZATION__UNIPHY_DSYN_ERROR__SHIFT 0x00000006 9045de2bdb3dSTom St Denis #define UNIPHY_DATA_SYNCHRONIZATION__UNIPHY_DSYN_LEVEL_MASK 0x00000030L 9046de2bdb3dSTom St Denis #define UNIPHY_DATA_SYNCHRONIZATION__UNIPHY_DSYN_LEVEL__SHIFT 0x00000004 9047de2bdb3dSTom St Denis #define UNIPHY_DATA_SYNCHRONIZATION__UNIPHY_DSYNSEL_MASK 0x00000001L 9048de2bdb3dSTom St Denis #define UNIPHY_DATA_SYNCHRONIZATION__UNIPHY_DSYNSEL__SHIFT 0x00000000 9049de2bdb3dSTom St Denis #define UNIPHY_DATA_SYNCHRONIZATION__UNIPHY_DUAL_LINK_PHASE_MASK 0x00010000L 9050de2bdb3dSTom St Denis #define UNIPHY_DATA_SYNCHRONIZATION__UNIPHY_DUAL_LINK_PHASE__SHIFT 0x00000010 9051de2bdb3dSTom St Denis #define UNIPHY_DATA_SYNCHRONIZATION__UNIPHY_LINK_ENABLE_MASK 0x00001000L 9052de2bdb3dSTom St Denis #define UNIPHY_DATA_SYNCHRONIZATION__UNIPHY_LINK_ENABLE__SHIFT 0x0000000c 9053de2bdb3dSTom St Denis #define UNIPHY_DATA_SYNCHRONIZATION__UNIPHY_SOURCE_SELECT_MASK 0x00000100L 9054de2bdb3dSTom St Denis #define UNIPHY_DATA_SYNCHRONIZATION__UNIPHY_SOURCE_SELECT__SHIFT 0x00000008 9055de2bdb3dSTom St Denis #define UNIPHYEF_TPG_CONTROL__UNIPHYEF_STATIC_TEST_PATTERN_MASK 0x000003ffL 9056de2bdb3dSTom St Denis #define UNIPHYEF_TPG_CONTROL__UNIPHYEF_STATIC_TEST_PATTERN__SHIFT 0x00000000 9057de2bdb3dSTom St Denis #define UNIPHYEF_TPG_CONTROL__UNIPHYEF_TPG_EN_MASK 0x00010000L 9058de2bdb3dSTom St Denis #define UNIPHYEF_TPG_CONTROL__UNIPHYEF_TPG_EN__SHIFT 0x00000010 9059de2bdb3dSTom St Denis #define UNIPHYEF_TPG_CONTROL__UNIPHYEF_TPG_SEL_MASK 0x000e0000L 9060de2bdb3dSTom St Denis #define UNIPHYEF_TPG_CONTROL__UNIPHYEF_TPG_SEL__SHIFT 0x00000011 9061de2bdb3dSTom St Denis #define UNIPHYEF_TPG_SEED__UNIPHYEF_TPG_SEED_MASK 0x007fffffL 9062de2bdb3dSTom St Denis #define UNIPHYEF_TPG_SEED__UNIPHYEF_TPG_SEED__SHIFT 0x00000000 9063de2bdb3dSTom St Denis #define UNIPHY_IMPCAL_LINKA__UNIPHY_CALOUT_ERROR_LINKA_AK_MASK 0x00000400L 9064de2bdb3dSTom St Denis #define UNIPHY_IMPCAL_LINKA__UNIPHY_CALOUT_ERROR_LINKA_AK__SHIFT 0x0000000a 9065de2bdb3dSTom St Denis #define UNIPHY_IMPCAL_LINKA__UNIPHY_CALOUT_ERROR_LINKA_MASK 0x00000200L 9066de2bdb3dSTom St Denis #define UNIPHY_IMPCAL_LINKA__UNIPHY_CALOUT_ERROR_LINKA__SHIFT 0x00000009 9067de2bdb3dSTom St Denis #define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_CALOUT_LINKA_MASK 0x00000100L 9068de2bdb3dSTom St Denis #define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_CALOUT_LINKA__SHIFT 0x00000008 9069de2bdb3dSTom St Denis #define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_ENABLE_LINKA_MASK 0x00000001L 9070de2bdb3dSTom St Denis #define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_ENABLE_LINKA__SHIFT 0x00000000 9071de2bdb3dSTom St Denis #define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKA_MASK 0x10000000L 9072de2bdb3dSTom St Denis #define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKA__SHIFT 0x0000001c 9073de2bdb3dSTom St Denis #define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_OVERRIDE_LINKA_MASK 0x0f000000L 9074de2bdb3dSTom St Denis #define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_OVERRIDE_LINKA__SHIFT 0x00000018 9075de2bdb3dSTom St Denis #define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_SEL_LINKA_MASK 0x40000000L 9076de2bdb3dSTom St Denis #define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_SEL_LINKA__SHIFT 0x0000001e 9077de2bdb3dSTom St Denis #define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_STEP_DELAY_LINKA_MASK 0x00f00000L 9078de2bdb3dSTom St Denis #define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_STEP_DELAY_LINKA__SHIFT 0x00000014 9079de2bdb3dSTom St Denis #define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_VALUE_LINKA_MASK 0x000f0000L 9080de2bdb3dSTom St Denis #define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_VALUE_LINKA__SHIFT 0x00000010 9081de2bdb3dSTom St Denis #define UNIPHY_IMPCAL_LINKB__UNIPHY_CALOUT_ERROR_LINKB_AK_MASK 0x00000400L 9082de2bdb3dSTom St Denis #define UNIPHY_IMPCAL_LINKB__UNIPHY_CALOUT_ERROR_LINKB_AK__SHIFT 0x0000000a 9083de2bdb3dSTom St Denis #define UNIPHY_IMPCAL_LINKB__UNIPHY_CALOUT_ERROR_LINKB_MASK 0x00000200L 9084de2bdb3dSTom St Denis #define UNIPHY_IMPCAL_LINKB__UNIPHY_CALOUT_ERROR_LINKB__SHIFT 0x00000009 9085de2bdb3dSTom St Denis #define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_CALOUT_LINKB_MASK 0x00000100L 9086de2bdb3dSTom St Denis #define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_CALOUT_LINKB__SHIFT 0x00000008 9087de2bdb3dSTom St Denis #define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_ENABLE_LINKB_MASK 0x00000001L 9088de2bdb3dSTom St Denis #define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_ENABLE_LINKB__SHIFT 0x00000000 9089de2bdb3dSTom St Denis #define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKB_MASK 0x10000000L 9090de2bdb3dSTom St Denis #define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKB__SHIFT 0x0000001c 9091de2bdb3dSTom St Denis #define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_OVERRIDE_LINKB_MASK 0x0f000000L 9092de2bdb3dSTom St Denis #define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_OVERRIDE_LINKB__SHIFT 0x00000018 9093de2bdb3dSTom St Denis #define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_SEL_LINKB_MASK 0x40000000L 9094de2bdb3dSTom St Denis #define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_SEL_LINKB__SHIFT 0x0000001e 9095de2bdb3dSTom St Denis #define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_STEP_DELAY_LINKB_MASK 0x00f00000L 9096de2bdb3dSTom St Denis #define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_STEP_DELAY_LINKB__SHIFT 0x00000014 9097de2bdb3dSTom St Denis #define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_VALUE_LINKB_MASK 0x000f0000L 9098de2bdb3dSTom St Denis #define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_VALUE_LINKB__SHIFT 0x00000010 9099de2bdb3dSTom St Denis #define UNIPHY_IMPCAL_LINKC__UNIPHY_CALOUT_ERROR_LINKC_AK_MASK 0x00000400L 9100de2bdb3dSTom St Denis #define UNIPHY_IMPCAL_LINKC__UNIPHY_CALOUT_ERROR_LINKC_AK__SHIFT 0x0000000a 9101de2bdb3dSTom St Denis #define UNIPHY_IMPCAL_LINKC__UNIPHY_CALOUT_ERROR_LINKC_MASK 0x00000200L 9102de2bdb3dSTom St Denis #define UNIPHY_IMPCAL_LINKC__UNIPHY_CALOUT_ERROR_LINKC__SHIFT 0x00000009 9103de2bdb3dSTom St Denis #define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_CALOUT_LINKC_MASK 0x00000100L 9104de2bdb3dSTom St Denis #define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_CALOUT_LINKC__SHIFT 0x00000008 9105de2bdb3dSTom St Denis #define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_ENABLE_LINKC_MASK 0x00000001L 9106de2bdb3dSTom St Denis #define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_ENABLE_LINKC__SHIFT 0x00000000 9107de2bdb3dSTom St Denis #define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKC_MASK 0x10000000L 9108de2bdb3dSTom St Denis #define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKC__SHIFT 0x0000001c 9109de2bdb3dSTom St Denis #define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_OVERRIDE_LINKC_MASK 0x0f000000L 9110de2bdb3dSTom St Denis #define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_OVERRIDE_LINKC__SHIFT 0x00000018 9111de2bdb3dSTom St Denis #define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_SEL_LINKC_MASK 0x40000000L 9112de2bdb3dSTom St Denis #define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_SEL_LINKC__SHIFT 0x0000001e 9113de2bdb3dSTom St Denis #define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_STEP_DELAY_LINKC_MASK 0x00f00000L 9114de2bdb3dSTom St Denis #define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_STEP_DELAY_LINKC__SHIFT 0x00000014 9115de2bdb3dSTom St Denis #define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_VALUE_LINKC_MASK 0x000f0000L 9116de2bdb3dSTom St Denis #define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_VALUE_LINKC__SHIFT 0x00000010 9117de2bdb3dSTom St Denis #define UNIPHY_IMPCAL_LINKD__UNIPHY_CALOUT_ERROR_LINKD_AK_MASK 0x00000400L 9118de2bdb3dSTom St Denis #define UNIPHY_IMPCAL_LINKD__UNIPHY_CALOUT_ERROR_LINKD_AK__SHIFT 0x0000000a 9119de2bdb3dSTom St Denis #define UNIPHY_IMPCAL_LINKD__UNIPHY_CALOUT_ERROR_LINKD_MASK 0x00000200L 9120de2bdb3dSTom St Denis #define UNIPHY_IMPCAL_LINKD__UNIPHY_CALOUT_ERROR_LINKD__SHIFT 0x00000009 9121de2bdb3dSTom St Denis #define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_CALOUT_LINKD_MASK 0x00000100L 9122de2bdb3dSTom St Denis #define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_CALOUT_LINKD__SHIFT 0x00000008 9123de2bdb3dSTom St Denis #define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_ENABLE_LINKD_MASK 0x00000001L 9124de2bdb3dSTom St Denis #define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_ENABLE_LINKD__SHIFT 0x00000000 9125de2bdb3dSTom St Denis #define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKD_MASK 0x10000000L 9126de2bdb3dSTom St Denis #define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKD__SHIFT 0x0000001c 9127de2bdb3dSTom St Denis #define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_OVERRIDE_LINKD_MASK 0x0f000000L 9128de2bdb3dSTom St Denis #define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_OVERRIDE_LINKD__SHIFT 0x00000018 9129de2bdb3dSTom St Denis #define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_SEL_LINKD_MASK 0x40000000L 9130de2bdb3dSTom St Denis #define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_SEL_LINKD__SHIFT 0x0000001e 9131de2bdb3dSTom St Denis #define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_STEP_DELAY_LINKD_MASK 0x00f00000L 9132de2bdb3dSTom St Denis #define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_STEP_DELAY_LINKD__SHIFT 0x00000014 9133de2bdb3dSTom St Denis #define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_VALUE_LINKD_MASK 0x000f0000L 9134de2bdb3dSTom St Denis #define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_VALUE_LINKD__SHIFT 0x00000010 9135de2bdb3dSTom St Denis #define UNIPHY_IMPCAL_LINKE__UNIPHY_CALOUT_ERROR_LINKE_AK_MASK 0x00000400L 9136de2bdb3dSTom St Denis #define UNIPHY_IMPCAL_LINKE__UNIPHY_CALOUT_ERROR_LINKE_AK__SHIFT 0x0000000a 9137de2bdb3dSTom St Denis #define UNIPHY_IMPCAL_LINKE__UNIPHY_CALOUT_ERROR_LINKE_MASK 0x00000200L 9138de2bdb3dSTom St Denis #define UNIPHY_IMPCAL_LINKE__UNIPHY_CALOUT_ERROR_LINKE__SHIFT 0x00000009 9139de2bdb3dSTom St Denis #define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_CALOUT_LINKE_MASK 0x00000100L 9140de2bdb3dSTom St Denis #define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_CALOUT_LINKE__SHIFT 0x00000008 9141de2bdb3dSTom St Denis #define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_ENABLE_LINKE_MASK 0x00000001L 9142de2bdb3dSTom St Denis #define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_ENABLE_LINKE__SHIFT 0x00000000 9143de2bdb3dSTom St Denis #define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKE_MASK 0x10000000L 9144de2bdb3dSTom St Denis #define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKE__SHIFT 0x0000001c 9145de2bdb3dSTom St Denis #define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_OVERRIDE_LINKE_MASK 0x0f000000L 9146de2bdb3dSTom St Denis #define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_OVERRIDE_LINKE__SHIFT 0x00000018 9147de2bdb3dSTom St Denis #define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_SEL_LINKE_MASK 0x40000000L 9148de2bdb3dSTom St Denis #define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_SEL_LINKE__SHIFT 0x0000001e 9149de2bdb3dSTom St Denis #define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_STEP_DELAY_LINKE_MASK 0x00f00000L 9150de2bdb3dSTom St Denis #define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_STEP_DELAY_LINKE__SHIFT 0x00000014 9151de2bdb3dSTom St Denis #define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_VALUE_LINKE_MASK 0x000f0000L 9152de2bdb3dSTom St Denis #define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_VALUE_LINKE__SHIFT 0x00000010 9153de2bdb3dSTom St Denis #define UNIPHY_IMPCAL_LINKF__UNIPHY_CALOUT_ERROR_LINKF_AK_MASK 0x00000400L 9154de2bdb3dSTom St Denis #define UNIPHY_IMPCAL_LINKF__UNIPHY_CALOUT_ERROR_LINKF_AK__SHIFT 0x0000000a 9155de2bdb3dSTom St Denis #define UNIPHY_IMPCAL_LINKF__UNIPHY_CALOUT_ERROR_LINKF_MASK 0x00000200L 9156de2bdb3dSTom St Denis #define UNIPHY_IMPCAL_LINKF__UNIPHY_CALOUT_ERROR_LINKF__SHIFT 0x00000009 9157de2bdb3dSTom St Denis #define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_CALOUT_LINKF_MASK 0x00000100L 9158de2bdb3dSTom St Denis #define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_CALOUT_LINKF__SHIFT 0x00000008 9159de2bdb3dSTom St Denis #define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_ENABLE_LINKF_MASK 0x00000001L 9160de2bdb3dSTom St Denis #define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_ENABLE_LINKF__SHIFT 0x00000000 9161de2bdb3dSTom St Denis #define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKF_MASK 0x10000000L 9162de2bdb3dSTom St Denis #define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKF__SHIFT 0x0000001c 9163de2bdb3dSTom St Denis #define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_OVERRIDE_LINKF_MASK 0x0f000000L 9164de2bdb3dSTom St Denis #define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_OVERRIDE_LINKF__SHIFT 0x00000018 9165de2bdb3dSTom St Denis #define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_SEL_LINKF_MASK 0x40000000L 9166de2bdb3dSTom St Denis #define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_SEL_LINKF__SHIFT 0x0000001e 9167de2bdb3dSTom St Denis #define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_STEP_DELAY_LINKF_MASK 0x00f00000L 9168de2bdb3dSTom St Denis #define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_STEP_DELAY_LINKF__SHIFT 0x00000014 9169de2bdb3dSTom St Denis #define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_VALUE_LINKF_MASK 0x000f0000L 9170de2bdb3dSTom St Denis #define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_VALUE_LINKF__SHIFT 0x00000010 9171de2bdb3dSTom St Denis #define UNIPHY_IMPCAL_PERIOD__UNIPHY_IMPCAL_PERIOD_MASK 0xffffffffL 9172de2bdb3dSTom St Denis #define UNIPHY_IMPCAL_PERIOD__UNIPHY_IMPCAL_PERIOD__SHIFT 0x00000000 9173de2bdb3dSTom St Denis #define UNIPHY_IMPCAL_PSW_AB__UNIPHY_IMPCAL_PSW_LINKA_MASK 0x00007fffL 9174de2bdb3dSTom St Denis #define UNIPHY_IMPCAL_PSW_AB__UNIPHY_IMPCAL_PSW_LINKA__SHIFT 0x00000000 9175de2bdb3dSTom St Denis #define UNIPHY_IMPCAL_PSW_AB__UNIPHY_IMPCAL_PSW_LINKB_MASK 0x7fff0000L 9176de2bdb3dSTom St Denis #define UNIPHY_IMPCAL_PSW_AB__UNIPHY_IMPCAL_PSW_LINKB__SHIFT 0x00000010 9177de2bdb3dSTom St Denis #define UNIPHY_IMPCAL_PSW_CD__UNIPHY_IMPCAL_PSW_LINKC_MASK 0x00007fffL 9178de2bdb3dSTom St Denis #define UNIPHY_IMPCAL_PSW_CD__UNIPHY_IMPCAL_PSW_LINKC__SHIFT 0x00000000 9179de2bdb3dSTom St Denis #define UNIPHY_IMPCAL_PSW_CD__UNIPHY_IMPCAL_PSW_LINKD_MASK 0x7fff0000L 9180de2bdb3dSTom St Denis #define UNIPHY_IMPCAL_PSW_CD__UNIPHY_IMPCAL_PSW_LINKD__SHIFT 0x00000010 9181de2bdb3dSTom St Denis #define UNIPHY_IMPCAL_PSW_EF__UNIPHY_IMPCAL_PSW_LINKE_MASK 0x00007fffL 9182de2bdb3dSTom St Denis #define UNIPHY_IMPCAL_PSW_EF__UNIPHY_IMPCAL_PSW_LINKE__SHIFT 0x00000000 9183de2bdb3dSTom St Denis #define UNIPHY_IMPCAL_PSW_EF__UNIPHY_IMPCAL_PSW_LINKF_MASK 0x7fff0000L 9184de2bdb3dSTom St Denis #define UNIPHY_IMPCAL_PSW_EF__UNIPHY_IMPCAL_PSW_LINKF__SHIFT 0x00000010 9185de2bdb3dSTom St Denis #define UNIPHY_LINK_CNTL__UNIPHY_CHANNEL0_INVERT_MASK 0x00001000L 9186de2bdb3dSTom St Denis #define UNIPHY_LINK_CNTL__UNIPHY_CHANNEL0_INVERT__SHIFT 0x0000000c 9187de2bdb3dSTom St Denis #define UNIPHY_LINK_CNTL__UNIPHY_CHANNEL1_INVERT_MASK 0x00002000L 9188de2bdb3dSTom St Denis #define UNIPHY_LINK_CNTL__UNIPHY_CHANNEL1_INVERT__SHIFT 0x0000000d 9189de2bdb3dSTom St Denis #define UNIPHY_LINK_CNTL__UNIPHY_CHANNEL2_INVERT_MASK 0x00004000L 9190de2bdb3dSTom St Denis #define UNIPHY_LINK_CNTL__UNIPHY_CHANNEL2_INVERT__SHIFT 0x0000000e 9191de2bdb3dSTom St Denis #define UNIPHY_LINK_CNTL__UNIPHY_CHANNEL3_INVERT_MASK 0x00008000L 9192de2bdb3dSTom St Denis #define UNIPHY_LINK_CNTL__UNIPHY_CHANNEL3_INVERT__SHIFT 0x0000000f 9193de2bdb3dSTom St Denis #define UNIPHY_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY_MASK 0x00700000L 9194de2bdb3dSTom St Denis #define UNIPHY_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY__SHIFT 0x00000014 9195de2bdb3dSTom St Denis #define UNIPHY_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK_MASK 0x00030000L 9196de2bdb3dSTom St Denis #define UNIPHY_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK__SHIFT 0x00000010 9197de2bdb3dSTom St Denis #define UNIPHY_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_MASK 0x00000700L 9198de2bdb3dSTom St Denis #define UNIPHY_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION__SHIFT 0x00000008 9199de2bdb3dSTom St Denis #define UNIPHY_LINK_CNTL__UNIPHY_PFREQCHG_MASK 0x00000001L 9200de2bdb3dSTom St Denis #define UNIPHY_LINK_CNTL__UNIPHY_PFREQCHG__SHIFT 0x00000000 9201de2bdb3dSTom St Denis #define UNIPHY_LINK_CNTL__UNIPHY_PIXVLD_RESET_MASK 0x00000010L 9202de2bdb3dSTom St Denis #define UNIPHY_LINK_CNTL__UNIPHY_PIXVLD_RESET__SHIFT 0x00000004 9203de2bdb3dSTom St Denis #define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_BW_CNTL_MASK 0x00ff0000L 9204de2bdb3dSTom St Denis #define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_BW_CNTL__SHIFT 0x00000010 9205de2bdb3dSTom St Denis #define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_CLK_EN_MASK 0x00000008L 9206de2bdb3dSTom St Denis #define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_CLK_EN__SHIFT 0x00000003 9207de2bdb3dSTom St Denis #define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_CLKPH_EN_MASK 0x000000f0L 9208de2bdb3dSTom St Denis #define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_CLKPH_EN__SHIFT 0x00000004 9209de2bdb3dSTom St Denis #define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_ENABLE_MASK 0x00000001L 9210de2bdb3dSTom St Denis #define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_ENABLE__SHIFT 0x00000000 9211de2bdb3dSTom St Denis #define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_EXT_RESET_EN_MASK 0x00000004L 9212de2bdb3dSTom St Denis #define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_EXT_RESET_EN__SHIFT 0x00000002 9213de2bdb3dSTom St Denis #define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_LF_CNTL_MASK 0x00007f00L 9214de2bdb3dSTom St Denis #define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_LF_CNTL__SHIFT 0x00000008 9215de2bdb3dSTom St Denis #define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_RESET_MASK 0x00000002L 9216de2bdb3dSTom St Denis #define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_RESET__SHIFT 0x00000001 9217de2bdb3dSTom St Denis #define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_TEST_BYPCLK_EN_MASK 0x02000000L 9218de2bdb3dSTom St Denis #define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_TEST_BYPCLK_EN__SHIFT 0x00000019 9219de2bdb3dSTom St Denis #define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_TEST_BYPCLK_SRC_MASK 0x01000000L 9220de2bdb3dSTom St Denis #define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_TEST_BYPCLK_SRC__SHIFT 0x00000018 9221de2bdb3dSTom St Denis #define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_TEST_VCTL_ADC_EN_MASK 0x04000000L 9222de2bdb3dSTom St Denis #define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_TEST_VCTL_ADC_EN__SHIFT 0x0000001a 9223de2bdb3dSTom St Denis #define UNIPHY_PLL_CONTROL1__UNIPHY_VCO_MODE_MASK 0x30000000L 9224de2bdb3dSTom St Denis #define UNIPHY_PLL_CONTROL1__UNIPHY_VCO_MODE__SHIFT 0x0000001c 9225de2bdb3dSTom St Denis #define UNIPHY_PLL_CONTROL2__UNIPHY_CLKINV_MASK 0x00002000L 9226de2bdb3dSTom St Denis #define UNIPHY_PLL_CONTROL2__UNIPHY_CLKINV__SHIFT 0x0000000d 9227de2bdb3dSTom St Denis #define UNIPHY_PLL_CONTROL2__UNIPHY_DPLLSEL_MASK 0x0000000cL 9228de2bdb3dSTom St Denis #define UNIPHY_PLL_CONTROL2__UNIPHY_DPLLSEL__SHIFT 0x00000002 9229de2bdb3dSTom St Denis #define UNIPHY_PLL_CONTROL2__UNIPHY_IDCLK_EN_MASK 0x00001000L 9230de2bdb3dSTom St Denis #define UNIPHY_PLL_CONTROL2__UNIPHY_IDCLK_EN__SHIFT 0x0000000c 9231de2bdb3dSTom St Denis #define UNIPHY_PLL_CONTROL2__UNIPHY_IDCLK_SEL_MASK 0x00000010L 9232de2bdb3dSTom St Denis #define UNIPHY_PLL_CONTROL2__UNIPHY_IDCLK_SEL__SHIFT 0x00000004 9233de2bdb3dSTom St Denis #define UNIPHY_PLL_CONTROL2__UNIPHY_IPCIE_REFCLK_SEL_MASK 0x00000020L 9234de2bdb3dSTom St Denis #define UNIPHY_PLL_CONTROL2__UNIPHY_IPCIE_REFCLK_SEL__SHIFT 0x00000005 9235de2bdb3dSTom St Denis #define UNIPHY_PLL_CONTROL2__UNIPHY_IXTALIN_SEL_MASK 0x00000040L 9236de2bdb3dSTom St Denis #define UNIPHY_PLL_CONTROL2__UNIPHY_IXTALIN_SEL__SHIFT 0x00000006 9237de2bdb3dSTom St Denis #define UNIPHY_PLL_CONTROL2__UNIPHY_PCIEREF_CLK_EN_MASK 0x00000800L 9238de2bdb3dSTom St Denis #define UNIPHY_PLL_CONTROL2__UNIPHY_PCIEREF_CLK_EN__SHIFT 0x0000000b 9239de2bdb3dSTom St Denis #define UNIPHY_PLL_CONTROL2__UNIPHY_PDIVFRAC_SEL_MASK 0x00100000L 9240de2bdb3dSTom St Denis #define UNIPHY_PLL_CONTROL2__UNIPHY_PDIVFRAC_SEL__SHIFT 0x00000014 9241de2bdb3dSTom St Denis #define UNIPHY_PLL_CONTROL2__UNIPHY_PDIV_SEL_MASK 0xe0000000L 9242de2bdb3dSTom St Denis #define UNIPHY_PLL_CONTROL2__UNIPHY_PDIV_SEL__SHIFT 0x0000001d 9243de2bdb3dSTom St Denis #define UNIPHY_PLL_CONTROL2__UNIPHY_PLL_DISPCLK_MODE_MASK 0x00000003L 9244de2bdb3dSTom St Denis #define UNIPHY_PLL_CONTROL2__UNIPHY_PLL_DISPCLK_MODE__SHIFT 0x00000000 9245de2bdb3dSTom St Denis #define UNIPHY_PLL_CONTROL2__UNIPHY_PLL_REFCLK_SRC_MASK 0x00000700L 9246de2bdb3dSTom St Denis #define UNIPHY_PLL_CONTROL2__UNIPHY_PLL_REFCLK_SRC__SHIFT 0x00000008 9247de2bdb3dSTom St Denis #define UNIPHY_PLL_CONTROL2__UNIPHY_PLL_REFDIV_MASK 0x1f000000L 9248de2bdb3dSTom St Denis #define UNIPHY_PLL_CONTROL2__UNIPHY_PLL_REFDIV__SHIFT 0x00000018 9249de2bdb3dSTom St Denis #define UNIPHY_PLL_CONTROL2__UNIPHY_PLL_TEST_FBDIV_FRAC_BYPASS_MASK 0x00080000L 9250de2bdb3dSTom St Denis #define UNIPHY_PLL_CONTROL2__UNIPHY_PLL_TEST_FBDIV_FRAC_BYPASS__SHIFT 0x00000013 9251de2bdb3dSTom St Denis #define UNIPHY_PLL_CONTROL2__UNIPHY_PLL_VTOI_BIAS_CNTL_MASK 0x00010000L 9252de2bdb3dSTom St Denis #define UNIPHY_PLL_CONTROL2__UNIPHY_PLL_VTOI_BIAS_CNTL__SHIFT 0x00000010 9253de2bdb3dSTom St Denis #define UNIPHY_PLL_FBDIV__UNIPHY_PLL_FBDIV_FRACTION_MASK 0x0000fffcL 9254de2bdb3dSTom St Denis #define UNIPHY_PLL_FBDIV__UNIPHY_PLL_FBDIV_FRACTION__SHIFT 0x00000002 9255de2bdb3dSTom St Denis #define UNIPHY_PLL_FBDIV__UNIPHY_PLL_FBDIV_MASK 0x0fff0000L 9256de2bdb3dSTom St Denis #define UNIPHY_PLL_FBDIV__UNIPHY_PLL_FBDIV__SHIFT 0x00000010 9257de2bdb3dSTom St Denis #define UNIPHY_PLL_SS_CNTL__UNIPHY_PLL_DSMOD_EN_MASK 0x00001000L 9258de2bdb3dSTom St Denis #define UNIPHY_PLL_SS_CNTL__UNIPHY_PLL_DSMOD_EN__SHIFT 0x0000000c 9259de2bdb3dSTom St Denis #define UNIPHY_PLL_SS_CNTL__UNIPHY_PLL_SS_EN_MASK 0x00002000L 9260de2bdb3dSTom St Denis #define UNIPHY_PLL_SS_CNTL__UNIPHY_PLL_SS_EN__SHIFT 0x0000000d 9261de2bdb3dSTom St Denis #define UNIPHY_PLL_SS_CNTL__UNIPHY_PLL_SS_STEP_NUM_MASK 0x00000fffL 9262de2bdb3dSTom St Denis #define UNIPHY_PLL_SS_CNTL__UNIPHY_PLL_SS_STEP_NUM__SHIFT 0x00000000 9263de2bdb3dSTom St Denis #define UNIPHY_PLL_SS_STEP_SIZE__UNIPHY_PLL_SS_STEP_SIZE_MASK 0x03ffffffL 9264de2bdb3dSTom St Denis #define UNIPHY_PLL_SS_STEP_SIZE__UNIPHY_PLL_SS_STEP_SIZE__SHIFT 0x00000000 9265de2bdb3dSTom St Denis #define UNIPHY_POWER_CONTROL__UNIPHY_BGADJ0P45_MASK 0x000f0000L 9266de2bdb3dSTom St Denis #define UNIPHY_POWER_CONTROL__UNIPHY_BGADJ0P45__SHIFT 0x00000010 9267de2bdb3dSTom St Denis #define UNIPHY_POWER_CONTROL__UNIPHY_BGADJ1P00_MASK 0x00000f00L 9268de2bdb3dSTom St Denis #define UNIPHY_POWER_CONTROL__UNIPHY_BGADJ1P00__SHIFT 0x00000008 9269de2bdb3dSTom St Denis #define UNIPHY_POWER_CONTROL__UNIPHY_BGADJ1P25_MASK 0x0000f000L 9270de2bdb3dSTom St Denis #define UNIPHY_POWER_CONTROL__UNIPHY_BGADJ1P25__SHIFT 0x0000000c 9271de2bdb3dSTom St Denis #define UNIPHY_POWER_CONTROL__UNIPHY_BGPDN_MASK 0x00000001L 9272de2bdb3dSTom St Denis #define UNIPHY_POWER_CONTROL__UNIPHY_BGPDN__SHIFT 0x00000000 9273de2bdb3dSTom St Denis #define UNIPHY_POWER_CONTROL__UNIPHY_BIASREF_SEL_MASK 0x00000004L 9274de2bdb3dSTom St Denis #define UNIPHY_POWER_CONTROL__UNIPHY_BIASREF_SEL__SHIFT 0x00000002 9275de2bdb3dSTom St Denis #define UNIPHY_POWER_CONTROL__UNIPHY_RST_LOGIC_MASK 0x00000002L 9276de2bdb3dSTom St Denis #define UNIPHY_POWER_CONTROL__UNIPHY_RST_LOGIC__SHIFT 0x00000001 9277de2bdb3dSTom St Denis #define UNIPHY_REG_TEST_OUTPUT__UNIPHY_DIG_BIST_ERROR_MASK 0x01f00000L 9278de2bdb3dSTom St Denis #define UNIPHY_REG_TEST_OUTPUT__UNIPHY_DIG_BIST_ERROR__SHIFT 0x00000014 9279de2bdb3dSTom St Denis #define UNIPHY_REG_TEST_OUTPUT__UNIPHY_DIG_BIST_RESET_MASK 0x00008000L 9280de2bdb3dSTom St Denis #define UNIPHY_REG_TEST_OUTPUT__UNIPHY_DIG_BIST_RESET__SHIFT 0x0000000f 9281de2bdb3dSTom St Denis #define UNIPHY_REG_TEST_OUTPUT__UNIPHY_DIG_BIST_SEL_MASK 0x00010000L 9282de2bdb3dSTom St Denis #define UNIPHY_REG_TEST_OUTPUT__UNIPHY_DIG_BIST_SEL__SHIFT 0x00000010 9283de2bdb3dSTom St Denis #define UNIPHY_REG_TEST_OUTPUT__UNIPHY_PLL_INTRESET_MASK 0x20000000L 9284de2bdb3dSTom St Denis #define UNIPHY_REG_TEST_OUTPUT__UNIPHY_PLL_INTRESET__SHIFT 0x0000001d 9285de2bdb3dSTom St Denis #define UNIPHY_REG_TEST_OUTPUT__UNIPHY_PLL_TEST_FREQ_LOCK_MASK 0x10000000L 9286de2bdb3dSTom St Denis #define UNIPHY_REG_TEST_OUTPUT__UNIPHY_PLL_TEST_FREQ_LOCK__SHIFT 0x0000001c 9287de2bdb3dSTom St Denis #define UNIPHY_REG_TEST_OUTPUT__UNIPHY_PLL_TEST_VCTL_ADC_MASK 0x0e000000L 9288de2bdb3dSTom St Denis #define UNIPHY_REG_TEST_OUTPUT__UNIPHY_PLL_TEST_VCTL_ADC__SHIFT 0x00000019 9289de2bdb3dSTom St Denis #define UNIPHY_REG_TEST_OUTPUT__UNIPHY_TEST_CNTL_MASK 0x0000001fL 9290de2bdb3dSTom St Denis #define UNIPHY_REG_TEST_OUTPUT__UNIPHY_TEST_CNTL__SHIFT 0x00000000 9291de2bdb3dSTom St Denis #define UNIPHY_REG_TEST_OUTPUT__UNIPHY_TEST_VCTL_EN_MASK 0x00020000L 9292de2bdb3dSTom St Denis #define UNIPHY_REG_TEST_OUTPUT__UNIPHY_TEST_VCTL_EN__SHIFT 0x00000011 9293de2bdb3dSTom St Denis #define UNIPHY_SOFT_RESET__DSYNCA_SOFT_RESET_MASK 0x00000001L 9294de2bdb3dSTom St Denis #define UNIPHY_SOFT_RESET__DSYNCA_SOFT_RESET__SHIFT 0x00000000 9295de2bdb3dSTom St Denis #define UNIPHY_SOFT_RESET__DSYNCB_SOFT_RESET_MASK 0x00000002L 9296de2bdb3dSTom St Denis #define UNIPHY_SOFT_RESET__DSYNCB_SOFT_RESET__SHIFT 0x00000001 9297de2bdb3dSTom St Denis #define UNIPHY_SOFT_RESET__DSYNCC_SOFT_RESET_MASK 0x00000004L 9298de2bdb3dSTom St Denis #define UNIPHY_SOFT_RESET__DSYNCC_SOFT_RESET__SHIFT 0x00000002 9299de2bdb3dSTom St Denis #define UNIPHY_SOFT_RESET__DSYNCD_SOFT_RESET_MASK 0x00000008L 9300de2bdb3dSTom St Denis #define UNIPHY_SOFT_RESET__DSYNCD_SOFT_RESET__SHIFT 0x00000003 9301de2bdb3dSTom St Denis #define UNIPHY_SOFT_RESET__DSYNCE_SOFT_RESET_MASK 0x00000010L 9302de2bdb3dSTom St Denis #define UNIPHY_SOFT_RESET__DSYNCE_SOFT_RESET__SHIFT 0x00000004 9303de2bdb3dSTom St Denis #define UNIPHY_SOFT_RESET__DSYNCF_SOFT_RESET_MASK 0x00000020L 9304de2bdb3dSTom St Denis #define UNIPHY_SOFT_RESET__DSYNCF_SOFT_RESET__SHIFT 0x00000005 9305de2bdb3dSTom St Denis #define UNIPHY_TX_CONTROL1__UNIPHY_PREMPH_STR0_MASK 0x00000007L 9306de2bdb3dSTom St Denis #define UNIPHY_TX_CONTROL1__UNIPHY_PREMPH_STR0__SHIFT 0x00000000 9307de2bdb3dSTom St Denis #define UNIPHY_TX_CONTROL1__UNIPHY_PREMPH_STR1_MASK 0x00000070L 9308de2bdb3dSTom St Denis #define UNIPHY_TX_CONTROL1__UNIPHY_PREMPH_STR1__SHIFT 0x00000004 9309de2bdb3dSTom St Denis #define UNIPHY_TX_CONTROL1__UNIPHY_PREMPH_STR2_MASK 0x00000700L 9310de2bdb3dSTom St Denis #define UNIPHY_TX_CONTROL1__UNIPHY_PREMPH_STR2__SHIFT 0x00000008 9311de2bdb3dSTom St Denis #define UNIPHY_TX_CONTROL1__UNIPHY_PREMPH_STR3_MASK 0x00007000L 9312de2bdb3dSTom St Denis #define UNIPHY_TX_CONTROL1__UNIPHY_PREMPH_STR3__SHIFT 0x0000000c 9313de2bdb3dSTom St Denis #define UNIPHY_TX_CONTROL1__UNIPHY_PREMPH_STR4_MASK 0x00070000L 9314de2bdb3dSTom St Denis #define UNIPHY_TX_CONTROL1__UNIPHY_PREMPH_STR4__SHIFT 0x00000010 9315de2bdb3dSTom St Denis #define UNIPHY_TX_CONTROL1__UNIPHY_TX_VS0_MASK 0x00300000L 9316de2bdb3dSTom St Denis #define UNIPHY_TX_CONTROL1__UNIPHY_TX_VS0__SHIFT 0x00000014 9317de2bdb3dSTom St Denis #define UNIPHY_TX_CONTROL1__UNIPHY_TX_VS1_MASK 0x00c00000L 9318de2bdb3dSTom St Denis #define UNIPHY_TX_CONTROL1__UNIPHY_TX_VS1__SHIFT 0x00000016 9319de2bdb3dSTom St Denis #define UNIPHY_TX_CONTROL1__UNIPHY_TX_VS2_MASK 0x03000000L 9320de2bdb3dSTom St Denis #define UNIPHY_TX_CONTROL1__UNIPHY_TX_VS2__SHIFT 0x00000018 9321de2bdb3dSTom St Denis #define UNIPHY_TX_CONTROL1__UNIPHY_TX_VS3_MASK 0x0c000000L 9322de2bdb3dSTom St Denis #define UNIPHY_TX_CONTROL1__UNIPHY_TX_VS3__SHIFT 0x0000001a 9323de2bdb3dSTom St Denis #define UNIPHY_TX_CONTROL1__UNIPHY_TX_VS4_MASK 0x30000000L 9324de2bdb3dSTom St Denis #define UNIPHY_TX_CONTROL1__UNIPHY_TX_VS4__SHIFT 0x0000001c 9325de2bdb3dSTom St Denis #define UNIPHY_TX_CONTROL2__UNIPHY_PREMPH0_PC_MASK 0x00000003L 9326de2bdb3dSTom St Denis #define UNIPHY_TX_CONTROL2__UNIPHY_PREMPH0_PC__SHIFT 0x00000000 9327de2bdb3dSTom St Denis #define UNIPHY_TX_CONTROL2__UNIPHY_PREMPH1_PC_MASK 0x00000030L 9328de2bdb3dSTom St Denis #define UNIPHY_TX_CONTROL2__UNIPHY_PREMPH1_PC__SHIFT 0x00000004 9329de2bdb3dSTom St Denis #define UNIPHY_TX_CONTROL2__UNIPHY_PREMPH2_PC_MASK 0x00000300L 9330de2bdb3dSTom St Denis #define UNIPHY_TX_CONTROL2__UNIPHY_PREMPH2_PC__SHIFT 0x00000008 9331de2bdb3dSTom St Denis #define UNIPHY_TX_CONTROL2__UNIPHY_PREMPH3_PC_MASK 0x00003000L 9332de2bdb3dSTom St Denis #define UNIPHY_TX_CONTROL2__UNIPHY_PREMPH3_PC__SHIFT 0x0000000c 9333de2bdb3dSTom St Denis #define UNIPHY_TX_CONTROL2__UNIPHY_PREMPH4_PC_MASK 0x00030000L 9334de2bdb3dSTom St Denis #define UNIPHY_TX_CONTROL2__UNIPHY_PREMPH4_PC__SHIFT 0x00000010 9335de2bdb3dSTom St Denis #define UNIPHY_TX_CONTROL2__UNIPHY_PREMPH_SEL_MASK 0x00100000L 9336de2bdb3dSTom St Denis #define UNIPHY_TX_CONTROL2__UNIPHY_PREMPH_SEL__SHIFT 0x00000014 9337de2bdb3dSTom St Denis #define UNIPHY_TX_CONTROL2__UNIPHY_RT0_CPSEL_MASK 0x00600000L 9338de2bdb3dSTom St Denis #define UNIPHY_TX_CONTROL2__UNIPHY_RT0_CPSEL__SHIFT 0x00000015 9339de2bdb3dSTom St Denis #define UNIPHY_TX_CONTROL2__UNIPHY_RT1_CPSEL_MASK 0x01800000L 9340de2bdb3dSTom St Denis #define UNIPHY_TX_CONTROL2__UNIPHY_RT1_CPSEL__SHIFT 0x00000017 9341de2bdb3dSTom St Denis #define UNIPHY_TX_CONTROL2__UNIPHY_RT2_CPSEL_MASK 0x06000000L 9342de2bdb3dSTom St Denis #define UNIPHY_TX_CONTROL2__UNIPHY_RT2_CPSEL__SHIFT 0x00000019 9343de2bdb3dSTom St Denis #define UNIPHY_TX_CONTROL2__UNIPHY_RT3_CPSEL_MASK 0x18000000L 9344de2bdb3dSTom St Denis #define UNIPHY_TX_CONTROL2__UNIPHY_RT3_CPSEL__SHIFT 0x0000001b 9345de2bdb3dSTom St Denis #define UNIPHY_TX_CONTROL2__UNIPHY_RT4_CPSEL_MASK 0x60000000L 9346de2bdb3dSTom St Denis #define UNIPHY_TX_CONTROL2__UNIPHY_RT4_CPSEL__SHIFT 0x0000001d 9347de2bdb3dSTom St Denis #define UNIPHY_TX_CONTROL3__UNIPHY_LVDS_PULLDWN_MASK 0x80000000L 9348de2bdb3dSTom St Denis #define UNIPHY_TX_CONTROL3__UNIPHY_LVDS_PULLDWN__SHIFT 0x0000001f 9349de2bdb3dSTom St Denis #define UNIPHY_TX_CONTROL3__UNIPHY_PESEL0_MASK 0x00100000L 9350de2bdb3dSTom St Denis #define UNIPHY_TX_CONTROL3__UNIPHY_PESEL0__SHIFT 0x00000014 9351de2bdb3dSTom St Denis #define UNIPHY_TX_CONTROL3__UNIPHY_PESEL1_MASK 0x00200000L 9352de2bdb3dSTom St Denis #define UNIPHY_TX_CONTROL3__UNIPHY_PESEL1__SHIFT 0x00000015 9353de2bdb3dSTom St Denis #define UNIPHY_TX_CONTROL3__UNIPHY_PESEL2_MASK 0x00400000L 9354de2bdb3dSTom St Denis #define UNIPHY_TX_CONTROL3__UNIPHY_PESEL2__SHIFT 0x00000016 9355de2bdb3dSTom St Denis #define UNIPHY_TX_CONTROL3__UNIPHY_PESEL3_MASK 0x00800000L 9356de2bdb3dSTom St Denis #define UNIPHY_TX_CONTROL3__UNIPHY_PESEL3__SHIFT 0x00000017 9357de2bdb3dSTom St Denis #define UNIPHY_TX_CONTROL3__UNIPHY_PREMPH_CS_CLK_MASK 0x000000f0L 9358de2bdb3dSTom St Denis #define UNIPHY_TX_CONTROL3__UNIPHY_PREMPH_CS_CLK__SHIFT 0x00000004 9359de2bdb3dSTom St Denis #define UNIPHY_TX_CONTROL3__UNIPHY_PREMPH_CS_DAT_MASK 0x00000f00L 9360de2bdb3dSTom St Denis #define UNIPHY_TX_CONTROL3__UNIPHY_PREMPH_CS_DAT__SHIFT 0x00000008 9361de2bdb3dSTom St Denis #define UNIPHY_TX_CONTROL3__UNIPHY_PREMPH_PW_CLK_MASK 0x00000003L 9362de2bdb3dSTom St Denis #define UNIPHY_TX_CONTROL3__UNIPHY_PREMPH_PW_CLK__SHIFT 0x00000000 9363de2bdb3dSTom St Denis #define UNIPHY_TX_CONTROL3__UNIPHY_PREMPH_PW_DAT_MASK 0x0000000cL 9364de2bdb3dSTom St Denis #define UNIPHY_TX_CONTROL3__UNIPHY_PREMPH_PW_DAT__SHIFT 0x00000002 9365de2bdb3dSTom St Denis #define UNIPHY_TX_CONTROL3__UNIPHY_PREMPH_STR_CLK_MASK 0x00007000L 9366de2bdb3dSTom St Denis #define UNIPHY_TX_CONTROL3__UNIPHY_PREMPH_STR_CLK__SHIFT 0x0000000c 9367de2bdb3dSTom St Denis #define UNIPHY_TX_CONTROL3__UNIPHY_PREMPH_STR_DAT_MASK 0x00070000L 9368de2bdb3dSTom St Denis #define UNIPHY_TX_CONTROL3__UNIPHY_PREMPH_STR_DAT__SHIFT 0x00000010 9369de2bdb3dSTom St Denis #define UNIPHY_TX_CONTROL3__UNIPHY_TX_VS_ADJ_MASK 0x1f000000L 9370de2bdb3dSTom St Denis #define UNIPHY_TX_CONTROL3__UNIPHY_TX_VS_ADJ__SHIFT 0x00000018 9371de2bdb3dSTom St Denis #define UNIPHY_TX_CONTROL4__UNIPHY_TX_NVS_CLK_MASK 0x0000001fL 9372de2bdb3dSTom St Denis #define UNIPHY_TX_CONTROL4__UNIPHY_TX_NVS_CLK__SHIFT 0x00000000 9373de2bdb3dSTom St Denis #define UNIPHY_TX_CONTROL4__UNIPHY_TX_NVS_DAT_MASK 0x000003e0L 9374de2bdb3dSTom St Denis #define UNIPHY_TX_CONTROL4__UNIPHY_TX_NVS_DAT__SHIFT 0x00000005 9375de2bdb3dSTom St Denis #define UNIPHY_TX_CONTROL4__UNIPHY_TX_OP_CLK_MASK 0x07000000L 9376de2bdb3dSTom St Denis #define UNIPHY_TX_CONTROL4__UNIPHY_TX_OP_CLK__SHIFT 0x00000018 9377de2bdb3dSTom St Denis #define UNIPHY_TX_CONTROL4__UNIPHY_TX_OP_DAT_MASK 0x70000000L 9378de2bdb3dSTom St Denis #define UNIPHY_TX_CONTROL4__UNIPHY_TX_OP_DAT__SHIFT 0x0000001c 9379de2bdb3dSTom St Denis #define UNIPHY_TX_CONTROL4__UNIPHY_TX_PVS_CLK_MASK 0x0001f000L 9380de2bdb3dSTom St Denis #define UNIPHY_TX_CONTROL4__UNIPHY_TX_PVS_CLK__SHIFT 0x0000000c 9381de2bdb3dSTom St Denis #define UNIPHY_TX_CONTROL4__UNIPHY_TX_PVS_DAT_MASK 0x003e0000L 9382de2bdb3dSTom St Denis #define UNIPHY_TX_CONTROL4__UNIPHY_TX_PVS_DAT__SHIFT 0x00000011 9383de2bdb3dSTom St Denis #define VGA25_PPLL_ANALOG__VGA25_CAL_MODE_MASK 0x0000001fL 9384de2bdb3dSTom St Denis #define VGA25_PPLL_ANALOG__VGA25_CAL_MODE__SHIFT 0x00000000 9385de2bdb3dSTom St Denis #define VGA25_PPLL_ANALOG__VGA25_PPLL_CP_MASK 0x00000f00L 9386de2bdb3dSTom St Denis #define VGA25_PPLL_ANALOG__VGA25_PPLL_CP__SHIFT 0x00000008 9387de2bdb3dSTom St Denis #define VGA25_PPLL_ANALOG__VGA25_PPLL_IBIAS_MASK 0xff000000L 9388de2bdb3dSTom St Denis #define VGA25_PPLL_ANALOG__VGA25_PPLL_IBIAS__SHIFT 0x00000018 9389de2bdb3dSTom St Denis #define VGA25_PPLL_ANALOG__VGA25_PPLL_LF_MODE_MASK 0x001ff000L 9390de2bdb3dSTom St Denis #define VGA25_PPLL_ANALOG__VGA25_PPLL_LF_MODE__SHIFT 0x0000000c 9391de2bdb3dSTom St Denis #define VGA25_PPLL_ANALOG__VGA25_PPLL_PFD_PULSE_SEL_MASK 0x00000060L 9392de2bdb3dSTom St Denis #define VGA25_PPLL_ANALOG__VGA25_PPLL_PFD_PULSE_SEL__SHIFT 0x00000005 9393de2bdb3dSTom St Denis #define VGA25_PPLL_FB_DIV__VGA25_PPLL_FB_DIV_FRACTION_CNTL_MASK 0x00000030L 9394de2bdb3dSTom St Denis #define VGA25_PPLL_FB_DIV__VGA25_PPLL_FB_DIV_FRACTION_CNTL__SHIFT 0x00000004 9395de2bdb3dSTom St Denis #define VGA25_PPLL_FB_DIV__VGA25_PPLL_FB_DIV_FRACTION_MASK 0x0000000fL 9396de2bdb3dSTom St Denis #define VGA25_PPLL_FB_DIV__VGA25_PPLL_FB_DIV_FRACTION__SHIFT 0x00000000 9397de2bdb3dSTom St Denis #define VGA25_PPLL_FB_DIV__VGA25_PPLL_FB_DIV_MASK 0x07ff0000L 9398de2bdb3dSTom St Denis #define VGA25_PPLL_FB_DIV__VGA25_PPLL_FB_DIV__SHIFT 0x00000010 9399de2bdb3dSTom St Denis #define VGA25_PPLL_POST_DIV__VGA25_PPLL_POST_DIV_DVOCLK_MASK 0x00007f00L 9400de2bdb3dSTom St Denis #define VGA25_PPLL_POST_DIV__VGA25_PPLL_POST_DIV_DVOCLK__SHIFT 0x00000008 9401de2bdb3dSTom St Denis #define VGA25_PPLL_POST_DIV__VGA25_PPLL_POST_DIV_IDCLK_MASK 0x007f0000L 9402de2bdb3dSTom St Denis #define VGA25_PPLL_POST_DIV__VGA25_PPLL_POST_DIV_IDCLK__SHIFT 0x00000010 9403de2bdb3dSTom St Denis #define VGA25_PPLL_POST_DIV__VGA25_PPLL_POST_DIV_PIXCLK_MASK 0x0000007fL 9404de2bdb3dSTom St Denis #define VGA25_PPLL_POST_DIV__VGA25_PPLL_POST_DIV_PIXCLK__SHIFT 0x00000000 9405de2bdb3dSTom St Denis #define VGA25_PPLL_REF_DIV__VGA25_PPLL_REF_DIV_MASK 0x000003ffL 9406de2bdb3dSTom St Denis #define VGA25_PPLL_REF_DIV__VGA25_PPLL_REF_DIV__SHIFT 0x00000000 9407de2bdb3dSTom St Denis #define VGA28_PPLL_ANALOG__VGA28_CAL_MODE_MASK 0x0000001fL 9408de2bdb3dSTom St Denis #define VGA28_PPLL_ANALOG__VGA28_CAL_MODE__SHIFT 0x00000000 9409de2bdb3dSTom St Denis #define VGA28_PPLL_ANALOG__VGA28_PPLL_CP_MASK 0x00000f00L 9410de2bdb3dSTom St Denis #define VGA28_PPLL_ANALOG__VGA28_PPLL_CP__SHIFT 0x00000008 9411de2bdb3dSTom St Denis #define VGA28_PPLL_ANALOG__VGA28_PPLL_IBIAS_MASK 0xff000000L 9412de2bdb3dSTom St Denis #define VGA28_PPLL_ANALOG__VGA28_PPLL_IBIAS__SHIFT 0x00000018 9413de2bdb3dSTom St Denis #define VGA28_PPLL_ANALOG__VGA28_PPLL_LF_MODE_MASK 0x001ff000L 9414de2bdb3dSTom St Denis #define VGA28_PPLL_ANALOG__VGA28_PPLL_LF_MODE__SHIFT 0x0000000c 9415de2bdb3dSTom St Denis #define VGA28_PPLL_ANALOG__VGA28_PPLL_PFD_PULSE_SEL_MASK 0x00000060L 9416de2bdb3dSTom St Denis #define VGA28_PPLL_ANALOG__VGA28_PPLL_PFD_PULSE_SEL__SHIFT 0x00000005 9417de2bdb3dSTom St Denis #define VGA28_PPLL_FB_DIV__VGA28_PPLL_FB_DIV_FRACTION_CNTL_MASK 0x00000030L 9418de2bdb3dSTom St Denis #define VGA28_PPLL_FB_DIV__VGA28_PPLL_FB_DIV_FRACTION_CNTL__SHIFT 0x00000004 9419de2bdb3dSTom St Denis #define VGA28_PPLL_FB_DIV__VGA28_PPLL_FB_DIV_FRACTION_MASK 0x0000000fL 9420de2bdb3dSTom St Denis #define VGA28_PPLL_FB_DIV__VGA28_PPLL_FB_DIV_FRACTION__SHIFT 0x00000000 9421de2bdb3dSTom St Denis #define VGA28_PPLL_FB_DIV__VGA28_PPLL_FB_DIV_MASK 0x07ff0000L 9422de2bdb3dSTom St Denis #define VGA28_PPLL_FB_DIV__VGA28_PPLL_FB_DIV__SHIFT 0x00000010 9423de2bdb3dSTom St Denis #define VGA28_PPLL_POST_DIV__VGA28_PPLL_POST_DIV_DVOCLK_MASK 0x00007f00L 9424de2bdb3dSTom St Denis #define VGA28_PPLL_POST_DIV__VGA28_PPLL_POST_DIV_DVOCLK__SHIFT 0x00000008 9425de2bdb3dSTom St Denis #define VGA28_PPLL_POST_DIV__VGA28_PPLL_POST_DIV_IDCLK_MASK 0x007f0000L 9426de2bdb3dSTom St Denis #define VGA28_PPLL_POST_DIV__VGA28_PPLL_POST_DIV_IDCLK__SHIFT 0x00000010 9427de2bdb3dSTom St Denis #define VGA28_PPLL_POST_DIV__VGA28_PPLL_POST_DIV_PIXCLK_MASK 0x0000007fL 9428de2bdb3dSTom St Denis #define VGA28_PPLL_POST_DIV__VGA28_PPLL_POST_DIV_PIXCLK__SHIFT 0x00000000 9429de2bdb3dSTom St Denis #define VGA28_PPLL_REF_DIV__VGA28_PPLL_REF_DIV_MASK 0x000003ffL 9430de2bdb3dSTom St Denis #define VGA28_PPLL_REF_DIV__VGA28_PPLL_REF_DIV__SHIFT 0x00000000 9431de2bdb3dSTom St Denis #define VGA41_PPLL_ANALOG__VGA41_CAL_MODE_MASK 0x0000001fL 9432de2bdb3dSTom St Denis #define VGA41_PPLL_ANALOG__VGA41_CAL_MODE__SHIFT 0x00000000 9433de2bdb3dSTom St Denis #define VGA41_PPLL_ANALOG__VGA41_PPLL_CP_MASK 0x00000f00L 9434de2bdb3dSTom St Denis #define VGA41_PPLL_ANALOG__VGA41_PPLL_CP__SHIFT 0x00000008 9435de2bdb3dSTom St Denis #define VGA41_PPLL_ANALOG__VGA41_PPLL_IBIAS_MASK 0xff000000L 9436de2bdb3dSTom St Denis #define VGA41_PPLL_ANALOG__VGA41_PPLL_IBIAS__SHIFT 0x00000018 9437de2bdb3dSTom St Denis #define VGA41_PPLL_ANALOG__VGA41_PPLL_LF_MODE_MASK 0x001ff000L 9438de2bdb3dSTom St Denis #define VGA41_PPLL_ANALOG__VGA41_PPLL_LF_MODE__SHIFT 0x0000000c 9439de2bdb3dSTom St Denis #define VGA41_PPLL_ANALOG__VGA41_PPLL_PFD_PULSE_SEL_MASK 0x00000060L 9440de2bdb3dSTom St Denis #define VGA41_PPLL_ANALOG__VGA41_PPLL_PFD_PULSE_SEL__SHIFT 0x00000005 9441de2bdb3dSTom St Denis #define VGA41_PPLL_FB_DIV__VGA41_PPLL_FB_DIV_FRACTION_CNTL_MASK 0x00000030L 9442de2bdb3dSTom St Denis #define VGA41_PPLL_FB_DIV__VGA41_PPLL_FB_DIV_FRACTION_CNTL__SHIFT 0x00000004 9443de2bdb3dSTom St Denis #define VGA41_PPLL_FB_DIV__VGA41_PPLL_FB_DIV_FRACTION_MASK 0x0000000fL 9444de2bdb3dSTom St Denis #define VGA41_PPLL_FB_DIV__VGA41_PPLL_FB_DIV_FRACTION__SHIFT 0x00000000 9445de2bdb3dSTom St Denis #define VGA41_PPLL_FB_DIV__VGA41_PPLL_FB_DIV_MASK 0x07ff0000L 9446de2bdb3dSTom St Denis #define VGA41_PPLL_FB_DIV__VGA41_PPLL_FB_DIV__SHIFT 0x00000010 9447de2bdb3dSTom St Denis #define VGA41_PPLL_POST_DIV__VGA41_PPLL_POST_DIV_DVOCLK_MASK 0x00007f00L 9448de2bdb3dSTom St Denis #define VGA41_PPLL_POST_DIV__VGA41_PPLL_POST_DIV_DVOCLK__SHIFT 0x00000008 9449de2bdb3dSTom St Denis #define VGA41_PPLL_POST_DIV__VGA41_PPLL_POST_DIV_IDCLK_MASK 0x007f0000L 9450de2bdb3dSTom St Denis #define VGA41_PPLL_POST_DIV__VGA41_PPLL_POST_DIV_IDCLK__SHIFT 0x00000010 9451de2bdb3dSTom St Denis #define VGA41_PPLL_POST_DIV__VGA41_PPLL_POST_DIV_PIXCLK_MASK 0x0000007fL 9452de2bdb3dSTom St Denis #define VGA41_PPLL_POST_DIV__VGA41_PPLL_POST_DIV_PIXCLK__SHIFT 0x00000000 9453de2bdb3dSTom St Denis #define VGA41_PPLL_REF_DIV__VGA41_PPLL_REF_DIV_MASK 0x000003ffL 9454de2bdb3dSTom St Denis #define VGA41_PPLL_REF_DIV__VGA41_PPLL_REF_DIV__SHIFT 0x00000000 9455de2bdb3dSTom St Denis #define VGA_CACHE_CONTROL__VGA_DCCIF_W256ONLY_MASK 0x00100000L 9456de2bdb3dSTom St Denis #define VGA_CACHE_CONTROL__VGA_DCCIF_W256ONLY__SHIFT 0x00000014 9457de2bdb3dSTom St Denis #define VGA_CACHE_CONTROL__VGA_DCCIF_WC_TIMEOUT_MASK 0x3f000000L 9458de2bdb3dSTom St Denis #define VGA_CACHE_CONTROL__VGA_DCCIF_WC_TIMEOUT__SHIFT 0x00000018 9459de2bdb3dSTom St Denis #define VGA_CACHE_CONTROL__VGA_READ_BUFFER_INVALIDATE_MASK 0x00010000L 9460de2bdb3dSTom St Denis #define VGA_CACHE_CONTROL__VGA_READ_BUFFER_INVALIDATE__SHIFT 0x00000010 9461de2bdb3dSTom St Denis #define VGA_CACHE_CONTROL__VGA_READ_CACHE_DISABLE_MASK 0x00000100L 9462de2bdb3dSTom St Denis #define VGA_CACHE_CONTROL__VGA_READ_CACHE_DISABLE__SHIFT 0x00000008 9463de2bdb3dSTom St Denis #define VGA_CACHE_CONTROL__VGA_WRITE_THROUGH_CACHE_DIS_MASK 0x00000001L 9464de2bdb3dSTom St Denis #define VGA_CACHE_CONTROL__VGA_WRITE_THROUGH_CACHE_DIS__SHIFT 0x00000000 9465de2bdb3dSTom St Denis #define VGADCC_DBG_DCCIF_C__DBG_DCCIF_C_MASK 0xffffffffL 9466de2bdb3dSTom St Denis #define VGADCC_DBG_DCCIF_C__DBG_DCCIF_C__SHIFT 0x00000000 9467de2bdb3dSTom St Denis #define VGA_DEBUG_READBACK_DATA__VGA_DEBUG_READBACK_DATA_MASK 0xffffffffL 9468de2bdb3dSTom St Denis #define VGA_DEBUG_READBACK_DATA__VGA_DEBUG_READBACK_DATA__SHIFT 0x00000000 9469de2bdb3dSTom St Denis #define VGA_DEBUG_READBACK_INDEX__VGA_DEBUG_READBACK_INDEX_MASK 0x000000ffL 9470de2bdb3dSTom St Denis #define VGA_DEBUG_READBACK_INDEX__VGA_DEBUG_READBACK_INDEX__SHIFT 0x00000000 9471de2bdb3dSTom St Denis #define VGA_DISPBUF1_SURFACE_ADDR__VGA_DISPBUF1_SURFACE_ADDR_MASK 0x01ffffffL 9472de2bdb3dSTom St Denis #define VGA_DISPBUF1_SURFACE_ADDR__VGA_DISPBUF1_SURFACE_ADDR__SHIFT 0x00000000 9473de2bdb3dSTom St Denis #define VGA_DISPBUF2_SURFACE_ADDR__VGA_DISPBUF2_SURFACE_ADDR_MASK 0x01ffffffL 9474de2bdb3dSTom St Denis #define VGA_DISPBUF2_SURFACE_ADDR__VGA_DISPBUF2_SURFACE_ADDR__SHIFT 0x00000000 9475de2bdb3dSTom St Denis #define VGA_HDP_CONTROL__VGA_MEMORY_DISABLE_MASK 0x00000010L 9476de2bdb3dSTom St Denis #define VGA_HDP_CONTROL__VGA_MEMORY_DISABLE__SHIFT 0x00000004 9477de2bdb3dSTom St Denis #define VGA_HDP_CONTROL__VGA_MEM_PAGE_SELECT_EN_MASK 0x00000001L 9478de2bdb3dSTom St Denis #define VGA_HDP_CONTROL__VGA_MEM_PAGE_SELECT_EN__SHIFT 0x00000000 9479de2bdb3dSTom St Denis #define VGA_HDP_CONTROL__VGA_RBBM_LOCK_DISABLE_MASK 0x00000100L 9480de2bdb3dSTom St Denis #define VGA_HDP_CONTROL__VGA_RBBM_LOCK_DISABLE__SHIFT 0x00000008 9481de2bdb3dSTom St Denis #define VGA_HDP_CONTROL__VGA_SOFT_RESET_MASK 0x00010000L 9482de2bdb3dSTom St Denis #define VGA_HDP_CONTROL__VGA_SOFT_RESET__SHIFT 0x00000010 9483de2bdb3dSTom St Denis #define VGA_HDP_CONTROL__VGA_TEST_RESET_CONTROL_MASK 0x01000000L 9484de2bdb3dSTom St Denis #define VGA_HDP_CONTROL__VGA_TEST_RESET_CONTROL__SHIFT 0x00000018 9485de2bdb3dSTom St Denis #define VGA_HW_DEBUG__VGA_HW_DEBUG_MASK 0xffffffffL 9486de2bdb3dSTom St Denis #define VGA_HW_DEBUG__VGA_HW_DEBUG__SHIFT 0x00000000 9487de2bdb3dSTom St Denis #define VGA_INTERRUPT_CONTROL__VGA_DISPLAY_SWITCH_INT_MASK_MASK 0x00010000L 9488de2bdb3dSTom St Denis #define VGA_INTERRUPT_CONTROL__VGA_DISPLAY_SWITCH_INT_MASK__SHIFT 0x00000010 9489de2bdb3dSTom St Denis #define VGA_INTERRUPT_CONTROL__VGA_MEM_ACCESS_INT_MASK_MASK 0x00000001L 9490de2bdb3dSTom St Denis #define VGA_INTERRUPT_CONTROL__VGA_MEM_ACCESS_INT_MASK__SHIFT 0x00000000 9491de2bdb3dSTom St Denis #define VGA_INTERRUPT_CONTROL__VGA_MODE_AUTO_TRIGGER_INT_MASK_MASK 0x01000000L 9492de2bdb3dSTom St Denis #define VGA_INTERRUPT_CONTROL__VGA_MODE_AUTO_TRIGGER_INT_MASK__SHIFT 0x00000018 9493de2bdb3dSTom St Denis #define VGA_INTERRUPT_CONTROL__VGA_REG_ACCESS_INT_MASK_MASK 0x00000100L 9494de2bdb3dSTom St Denis #define VGA_INTERRUPT_CONTROL__VGA_REG_ACCESS_INT_MASK__SHIFT 0x00000008 9495de2bdb3dSTom St Denis #define VGA_INTERRUPT_STATUS__VGA_DISPLAY_SWITCH_INT_STATUS_MASK 0x00000004L 9496de2bdb3dSTom St Denis #define VGA_INTERRUPT_STATUS__VGA_DISPLAY_SWITCH_INT_STATUS__SHIFT 0x00000002 9497de2bdb3dSTom St Denis #define VGA_INTERRUPT_STATUS__VGA_MEM_ACCESS_INT_STATUS_MASK 0x00000001L 9498de2bdb3dSTom St Denis #define VGA_INTERRUPT_STATUS__VGA_MEM_ACCESS_INT_STATUS__SHIFT 0x00000000 9499de2bdb3dSTom St Denis #define VGA_INTERRUPT_STATUS__VGA_MODE_AUTO_TRIGGER_INT_STATUS_MASK 0x00000008L 9500de2bdb3dSTom St Denis #define VGA_INTERRUPT_STATUS__VGA_MODE_AUTO_TRIGGER_INT_STATUS__SHIFT 0x00000003 9501de2bdb3dSTom St Denis #define VGA_INTERRUPT_STATUS__VGA_REG_ACCESS_INT_STATUS_MASK 0x00000002L 9502de2bdb3dSTom St Denis #define VGA_INTERRUPT_STATUS__VGA_REG_ACCESS_INT_STATUS__SHIFT 0x00000001 9503de2bdb3dSTom St Denis #define VGA_MAIN_CONTROL__VGA_CRTC_TIMEOUT_MASK 0x00000003L 9504de2bdb3dSTom St Denis #define VGA_MAIN_CONTROL__VGA_CRTC_TIMEOUT__SHIFT 0x00000000 9505de2bdb3dSTom St Denis #define VGA_MAIN_CONTROL__VGA_EXTERNAL_DAC_SENSE_MASK 0x20000000L 9506de2bdb3dSTom St Denis #define VGA_MAIN_CONTROL__VGA_EXTERNAL_DAC_SENSE__SHIFT 0x0000001d 9507de2bdb3dSTom St Denis #define VGA_MAIN_CONTROL__VGA_MAIN_TEST_VSTATUS_NO_DISPLAY_CRTC_TIMEOUT_MASK 0x80000000L 9508de2bdb3dSTom St Denis #define VGA_MAIN_CONTROL__VGA_MAIN_TEST_VSTATUS_NO_DISPLAY_CRTC_TIMEOUT__SHIFT 0x0000001f 9509de2bdb3dSTom St Denis #define VGA_MAIN_CONTROL__VGA_READBACK_CRT_INTR_SOURCE_SELECT_MASK 0x03000000L 9510de2bdb3dSTom St Denis #define VGA_MAIN_CONTROL__VGA_READBACK_CRT_INTR_SOURCE_SELECT__SHIFT 0x00000018 9511de2bdb3dSTom St Denis #define VGA_MAIN_CONTROL__VGA_READBACK_NO_DISPLAY_SOURCE_SELECT_MASK 0x00030000L 9512de2bdb3dSTom St Denis #define VGA_MAIN_CONTROL__VGA_READBACK_NO_DISPLAY_SOURCE_SELECT__SHIFT 0x00000010 9513de2bdb3dSTom St Denis #define VGA_MAIN_CONTROL__VGA_READBACK_SENSE_SWITCH_SELECT_MASK 0x04000000L 9514de2bdb3dSTom St Denis #define VGA_MAIN_CONTROL__VGA_READBACK_SENSE_SWITCH_SELECT__SHIFT 0x0000001a 9515de2bdb3dSTom St Denis #define VGA_MAIN_CONTROL__VGA_READBACK_VGA_VSTATUS_SOURCE_SELECT_MASK 0x00000300L 9516de2bdb3dSTom St Denis #define VGA_MAIN_CONTROL__VGA_READBACK_VGA_VSTATUS_SOURCE_SELECT__SHIFT 0x00000008 9517de2bdb3dSTom St Denis #define VGA_MAIN_CONTROL__VGA_READ_URGENT_ENABLE_MASK 0x08000000L 9518de2bdb3dSTom St Denis #define VGA_MAIN_CONTROL__VGA_READ_URGENT_ENABLE__SHIFT 0x0000001b 9519de2bdb3dSTom St Denis #define VGA_MAIN_CONTROL__VGA_RENDER_TIMEOUT_COUNT_MASK 0x00000018L 9520de2bdb3dSTom St Denis #define VGA_MAIN_CONTROL__VGA_RENDER_TIMEOUT_COUNT__SHIFT 0x00000003 9521de2bdb3dSTom St Denis #define VGA_MAIN_CONTROL__VGA_VIRTUAL_VERTICAL_RETRACE_DURATION_MASK 0x000000e0L 9522de2bdb3dSTom St Denis #define VGA_MAIN_CONTROL__VGA_VIRTUAL_VERTICAL_RETRACE_DURATION__SHIFT 0x00000005 9523de2bdb3dSTom St Denis #define VGA_MAIN_CONTROL__VGA_WRITES_URGENT_ENABLE_MASK 0x10000000L 9524de2bdb3dSTom St Denis #define VGA_MAIN_CONTROL__VGA_WRITES_URGENT_ENABLE__SHIFT 0x0000001c 9525de2bdb3dSTom St Denis #define VGA_MEMORY_BASE_ADDRESS_HIGH__VGA_MEMORY_BASE_ADDRESS_HIGH_MASK 0x000000ffL 9526de2bdb3dSTom St Denis #define VGA_MEMORY_BASE_ADDRESS_HIGH__VGA_MEMORY_BASE_ADDRESS_HIGH__SHIFT 0x00000000 9527de2bdb3dSTom St Denis #define VGA_MEMORY_BASE_ADDRESS__VGA_MEMORY_BASE_ADDRESS_MASK 0xffffffffL 9528de2bdb3dSTom St Denis #define VGA_MEMORY_BASE_ADDRESS__VGA_MEMORY_BASE_ADDRESS__SHIFT 0x00000000 9529de2bdb3dSTom St Denis #define VGA_MEM_READ_PAGE_ADDR__VGA_MEM_READ_PAGE0_ADDR_MASK 0x000003ffL 9530de2bdb3dSTom St Denis #define VGA_MEM_READ_PAGE_ADDR__VGA_MEM_READ_PAGE0_ADDR__SHIFT 0x00000000 9531de2bdb3dSTom St Denis #define VGA_MEM_READ_PAGE_ADDR__VGA_MEM_READ_PAGE1_ADDR_MASK 0x03ff0000L 9532de2bdb3dSTom St Denis #define VGA_MEM_READ_PAGE_ADDR__VGA_MEM_READ_PAGE1_ADDR__SHIFT 0x00000010 9533de2bdb3dSTom St Denis #define VGA_MEM_WRITE_PAGE_ADDR__VGA_MEM_WRITE_PAGE0_ADDR_MASK 0x000003ffL 9534de2bdb3dSTom St Denis #define VGA_MEM_WRITE_PAGE_ADDR__VGA_MEM_WRITE_PAGE0_ADDR__SHIFT 0x00000000 9535de2bdb3dSTom St Denis #define VGA_MEM_WRITE_PAGE_ADDR__VGA_MEM_WRITE_PAGE1_ADDR_MASK 0x03ff0000L 9536de2bdb3dSTom St Denis #define VGA_MEM_WRITE_PAGE_ADDR__VGA_MEM_WRITE_PAGE1_ADDR__SHIFT 0x00000010 9537de2bdb3dSTom St Denis #define VGA_MODE_CONTROL__VGA_128K_APERTURE_PAGING_MASK 0x00000100L 9538de2bdb3dSTom St Denis #define VGA_MODE_CONTROL__VGA_128K_APERTURE_PAGING__SHIFT 0x00000008 9539de2bdb3dSTom St Denis #define VGA_MODE_CONTROL__VGA_ATI_LINEAR_MASK 0x00000001L 9540de2bdb3dSTom St Denis #define VGA_MODE_CONTROL__VGA_ATI_LINEAR__SHIFT 0x00000000 9541de2bdb3dSTom St Denis #define VGA_MODE_CONTROL__VGA_LUT_PALETTE_UPDATE_MODE_MASK 0x00000030L 9542de2bdb3dSTom St Denis #define VGA_MODE_CONTROL__VGA_LUT_PALETTE_UPDATE_MODE__SHIFT 0x00000004 9543de2bdb3dSTom St Denis #define VGA_MODE_CONTROL__VGA_TEXT_132_COLUMNS_EN_MASK 0x00010000L 9544de2bdb3dSTom St Denis #define VGA_MODE_CONTROL__VGA_TEXT_132_COLUMNS_EN__SHIFT 0x00000010 9545de2bdb3dSTom St Denis #define VGA_RENDER_CONTROL__VGA_BLINK_MODE_MASK 0x00000060L 9546de2bdb3dSTom St Denis #define VGA_RENDER_CONTROL__VGA_BLINK_MODE__SHIFT 0x00000005 9547de2bdb3dSTom St Denis #define VGA_RENDER_CONTROL__VGA_BLINK_RATE_MASK 0x0000001fL 9548de2bdb3dSTom St Denis #define VGA_RENDER_CONTROL__VGA_BLINK_RATE__SHIFT 0x00000000 9549de2bdb3dSTom St Denis #define VGA_RENDER_CONTROL__VGA_CURSOR_BLINK_INVERT_MASK 0x00000080L 9550de2bdb3dSTom St Denis #define VGA_RENDER_CONTROL__VGA_CURSOR_BLINK_INVERT__SHIFT 0x00000007 9551de2bdb3dSTom St Denis #define VGA_RENDER_CONTROL__VGA_EXTD_ADDR_COUNT_ENABLE_MASK 0x00000100L 9552de2bdb3dSTom St Denis #define VGA_RENDER_CONTROL__VGA_EXTD_ADDR_COUNT_ENABLE__SHIFT 0x00000008 9553de2bdb3dSTom St Denis #define VGA_RENDER_CONTROL__VGA_LOCK_8DOT_MASK 0x01000000L 9554de2bdb3dSTom St Denis #define VGA_RENDER_CONTROL__VGA_LOCK_8DOT__SHIFT 0x00000018 9555de2bdb3dSTom St Denis #define VGA_RENDER_CONTROL__VGAREG_LINECMP_COMPATIBILITY_SEL_MASK 0x02000000L 9556de2bdb3dSTom St Denis #define VGA_RENDER_CONTROL__VGAREG_LINECMP_COMPATIBILITY_SEL__SHIFT 0x00000019 9557de2bdb3dSTom St Denis #define VGA_RENDER_CONTROL__VGA_VSTATUS_CNTL_MASK 0x00030000L 9558de2bdb3dSTom St Denis #define VGA_RENDER_CONTROL__VGA_VSTATUS_CNTL__SHIFT 0x00000010 9559de2bdb3dSTom St Denis #define VGA_SEQUENCER_RESET_CONTROL__D1_BLANK_DISPLAY_WHEN_SEQUENCER_RESET_MASK 0x00000001L 9560de2bdb3dSTom St Denis #define VGA_SEQUENCER_RESET_CONTROL__D1_BLANK_DISPLAY_WHEN_SEQUENCER_RESET__SHIFT 0x00000000 9561de2bdb3dSTom St Denis #define VGA_SEQUENCER_RESET_CONTROL__D1_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET_MASK 0x00000100L 9562de2bdb3dSTom St Denis #define VGA_SEQUENCER_RESET_CONTROL__D1_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET__SHIFT 0x00000008 9563de2bdb3dSTom St Denis #define VGA_SEQUENCER_RESET_CONTROL__D2_BLANK_DISPLAY_WHEN_SEQUENCER_RESET_MASK 0x00000002L 9564de2bdb3dSTom St Denis #define VGA_SEQUENCER_RESET_CONTROL__D2_BLANK_DISPLAY_WHEN_SEQUENCER_RESET__SHIFT 0x00000001 9565de2bdb3dSTom St Denis #define VGA_SEQUENCER_RESET_CONTROL__D2_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET_MASK 0x00000200L 9566de2bdb3dSTom St Denis #define VGA_SEQUENCER_RESET_CONTROL__D2_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET__SHIFT 0x00000009 9567de2bdb3dSTom St Denis #define VGA_SEQUENCER_RESET_CONTROL__D3_BLANK_DISPLAY_WHEN_SEQUENCER_RESET_MASK 0x00000004L 9568de2bdb3dSTom St Denis #define VGA_SEQUENCER_RESET_CONTROL__D3_BLANK_DISPLAY_WHEN_SEQUENCER_RESET__SHIFT 0x00000002 9569de2bdb3dSTom St Denis #define VGA_SEQUENCER_RESET_CONTROL__D3_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET_MASK 0x00000400L 9570de2bdb3dSTom St Denis #define VGA_SEQUENCER_RESET_CONTROL__D3_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET__SHIFT 0x0000000a 9571de2bdb3dSTom St Denis #define VGA_SEQUENCER_RESET_CONTROL__D4_BLANK_DISPLAY_WHEN_SEQUENCER_RESET_MASK 0x00000008L 9572de2bdb3dSTom St Denis #define VGA_SEQUENCER_RESET_CONTROL__D4_BLANK_DISPLAY_WHEN_SEQUENCER_RESET__SHIFT 0x00000003 9573de2bdb3dSTom St Denis #define VGA_SEQUENCER_RESET_CONTROL__D4_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET_MASK 0x00000800L 9574de2bdb3dSTom St Denis #define VGA_SEQUENCER_RESET_CONTROL__D4_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET__SHIFT 0x0000000b 9575de2bdb3dSTom St Denis #define VGA_SEQUENCER_RESET_CONTROL__D5_BLANK_DISPLAY_WHEN_SEQUENCER_RESET_MASK 0x00000010L 9576de2bdb3dSTom St Denis #define VGA_SEQUENCER_RESET_CONTROL__D5_BLANK_DISPLAY_WHEN_SEQUENCER_RESET__SHIFT 0x00000004 9577de2bdb3dSTom St Denis #define VGA_SEQUENCER_RESET_CONTROL__D5_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET_MASK 0x00001000L 9578de2bdb3dSTom St Denis #define VGA_SEQUENCER_RESET_CONTROL__D5_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET__SHIFT 0x0000000c 9579de2bdb3dSTom St Denis #define VGA_SEQUENCER_RESET_CONTROL__D6_BLANK_DISPLAY_WHEN_SEQUENCER_RESET_MASK 0x00000020L 9580de2bdb3dSTom St Denis #define VGA_SEQUENCER_RESET_CONTROL__D6_BLANK_DISPLAY_WHEN_SEQUENCER_RESET__SHIFT 0x00000005 9581de2bdb3dSTom St Denis #define VGA_SEQUENCER_RESET_CONTROL__D6_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET_MASK 0x00002000L 9582de2bdb3dSTom St Denis #define VGA_SEQUENCER_RESET_CONTROL__D6_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET__SHIFT 0x0000000d 9583de2bdb3dSTom St Denis #define VGA_SEQUENCER_RESET_CONTROL__VGA_MODE_AUTO_TRIGGER_ENABLE_MASK 0x00010000L 9584de2bdb3dSTom St Denis #define VGA_SEQUENCER_RESET_CONTROL__VGA_MODE_AUTO_TRIGGER_ENABLE__SHIFT 0x00000010 9585de2bdb3dSTom St Denis #define VGA_SEQUENCER_RESET_CONTROL__VGA_MODE_AUTO_TRIGGER_INDEX_SELECT_MASK 0x00fc0000L 9586de2bdb3dSTom St Denis #define VGA_SEQUENCER_RESET_CONTROL__VGA_MODE_AUTO_TRIGGER_INDEX_SELECT__SHIFT 0x00000012 9587de2bdb3dSTom St Denis #define VGA_SEQUENCER_RESET_CONTROL__VGA_MODE_AUTO_TRIGGER_REGISTER_SELECT_MASK 0x00020000L 9588de2bdb3dSTom St Denis #define VGA_SEQUENCER_RESET_CONTROL__VGA_MODE_AUTO_TRIGGER_REGISTER_SELECT__SHIFT 0x00000011 9589de2bdb3dSTom St Denis #define VGA_SOURCE_SELECT__VGA_SOURCE_SEL_A_MASK 0x00000007L 9590de2bdb3dSTom St Denis #define VGA_SOURCE_SELECT__VGA_SOURCE_SEL_A__SHIFT 0x00000000 9591de2bdb3dSTom St Denis #define VGA_SOURCE_SELECT__VGA_SOURCE_SEL_B_MASK 0x00000700L 9592de2bdb3dSTom St Denis #define VGA_SOURCE_SELECT__VGA_SOURCE_SEL_B__SHIFT 0x00000008 9593de2bdb3dSTom St Denis #define VGA_STATUS_CLEAR__VGA_DISPLAY_SWITCH_INT_CLEAR_MASK 0x00010000L 9594de2bdb3dSTom St Denis #define VGA_STATUS_CLEAR__VGA_DISPLAY_SWITCH_INT_CLEAR__SHIFT 0x00000010 9595de2bdb3dSTom St Denis #define VGA_STATUS_CLEAR__VGA_MEM_ACCESS_INT_CLEAR_MASK 0x00000001L 9596de2bdb3dSTom St Denis #define VGA_STATUS_CLEAR__VGA_MEM_ACCESS_INT_CLEAR__SHIFT 0x00000000 9597de2bdb3dSTom St Denis #define VGA_STATUS_CLEAR__VGA_MODE_AUTO_TRIGGER_INT_CLEAR_MASK 0x01000000L 9598de2bdb3dSTom St Denis #define VGA_STATUS_CLEAR__VGA_MODE_AUTO_TRIGGER_INT_CLEAR__SHIFT 0x00000018 9599de2bdb3dSTom St Denis #define VGA_STATUS_CLEAR__VGA_REG_ACCESS_INT_CLEAR_MASK 0x00000100L 9600de2bdb3dSTom St Denis #define VGA_STATUS_CLEAR__VGA_REG_ACCESS_INT_CLEAR__SHIFT 0x00000008 9601de2bdb3dSTom St Denis #define VGA_STATUS__VGA_DISPLAY_SWITCH_STATUS_MASK 0x00000004L 9602de2bdb3dSTom St Denis #define VGA_STATUS__VGA_DISPLAY_SWITCH_STATUS__SHIFT 0x00000002 9603de2bdb3dSTom St Denis #define VGA_STATUS__VGA_MEM_ACCESS_STATUS_MASK 0x00000001L 9604de2bdb3dSTom St Denis #define VGA_STATUS__VGA_MEM_ACCESS_STATUS__SHIFT 0x00000000 9605de2bdb3dSTom St Denis #define VGA_STATUS__VGA_MODE_AUTO_TRIGGER_STATUS_MASK 0x00000008L 9606de2bdb3dSTom St Denis #define VGA_STATUS__VGA_MODE_AUTO_TRIGGER_STATUS__SHIFT 0x00000003 9607de2bdb3dSTom St Denis #define VGA_STATUS__VGA_REG_ACCESS_STATUS_MASK 0x00000002L 9608de2bdb3dSTom St Denis #define VGA_STATUS__VGA_REG_ACCESS_STATUS__SHIFT 0x00000001 9609de2bdb3dSTom St Denis #define VGA_SURFACE_PITCH_SELECT__VGA_SURFACE_HEIGHT_SELECT_MASK 0x00000300L 9610de2bdb3dSTom St Denis #define VGA_SURFACE_PITCH_SELECT__VGA_SURFACE_HEIGHT_SELECT__SHIFT 0x00000008 9611de2bdb3dSTom St Denis #define VGA_SURFACE_PITCH_SELECT__VGA_SURFACE_PITCH_SELECT_MASK 0x00000003L 9612de2bdb3dSTom St Denis #define VGA_SURFACE_PITCH_SELECT__VGA_SURFACE_PITCH_SELECT__SHIFT 0x00000000 9613de2bdb3dSTom St Denis #define VGA_TEST_CONTROL__VGA_TEST_ENABLE_MASK 0x00000001L 9614de2bdb3dSTom St Denis #define VGA_TEST_CONTROL__VGA_TEST_ENABLE__SHIFT 0x00000000 9615de2bdb3dSTom St Denis #define VGA_TEST_CONTROL__VGA_TEST_RENDER_DISPBUF_SELECT_MASK 0x01000000L 9616de2bdb3dSTom St Denis #define VGA_TEST_CONTROL__VGA_TEST_RENDER_DISPBUF_SELECT__SHIFT 0x00000018 9617de2bdb3dSTom St Denis #define VGA_TEST_CONTROL__VGA_TEST_RENDER_DONE_MASK 0x00010000L 9618de2bdb3dSTom St Denis #define VGA_TEST_CONTROL__VGA_TEST_RENDER_DONE__SHIFT 0x00000010 9619de2bdb3dSTom St Denis #define VGA_TEST_CONTROL__VGA_TEST_RENDER_START_MASK 0x00000100L 9620de2bdb3dSTom St Denis #define VGA_TEST_CONTROL__VGA_TEST_RENDER_START__SHIFT 0x00000008 9621de2bdb3dSTom St Denis #define VGA_TEST_DEBUG_DATA__VGA_TEST_DEBUG_DATA_MASK 0xffffffffL 9622de2bdb3dSTom St Denis #define VGA_TEST_DEBUG_DATA__VGA_TEST_DEBUG_DATA__SHIFT 0x00000000 9623de2bdb3dSTom St Denis #define VGA_TEST_DEBUG_INDEX__VGA_TEST_DEBUG_INDEX_MASK 0x000000ffL 9624de2bdb3dSTom St Denis #define VGA_TEST_DEBUG_INDEX__VGA_TEST_DEBUG_INDEX__SHIFT 0x00000000 9625de2bdb3dSTom St Denis #define VGA_TEST_DEBUG_INDEX__VGA_TEST_DEBUG_WRITE_EN_MASK 0x00000100L 9626de2bdb3dSTom St Denis #define VGA_TEST_DEBUG_INDEX__VGA_TEST_DEBUG_WRITE_EN__SHIFT 0x00000008 9627de2bdb3dSTom St Denis #define VIEWPORT_SIZE__VIEWPORT_HEIGHT_MASK 0x00003fffL 9628de2bdb3dSTom St Denis #define VIEWPORT_SIZE__VIEWPORT_HEIGHT__SHIFT 0x00000000 9629de2bdb3dSTom St Denis #define VIEWPORT_SIZE__VIEWPORT_WIDTH_MASK 0x3fff0000L 9630de2bdb3dSTom St Denis #define VIEWPORT_SIZE__VIEWPORT_WIDTH__SHIFT 0x00000010 9631de2bdb3dSTom St Denis #define VIEWPORT_START__VIEWPORT_X_START_MASK 0x3fff0000L 9632de2bdb3dSTom St Denis #define VIEWPORT_START__VIEWPORT_X_START__SHIFT 0x00000010 9633de2bdb3dSTom St Denis #define VIEWPORT_START__VIEWPORT_Y_START_MASK 0x00003fffL 9634de2bdb3dSTom St Denis #define VIEWPORT_START__VIEWPORT_Y_START__SHIFT 0x00000000 9635de2bdb3dSTom St Denis #define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_GATE_DIS_MASK 0x00008000L 9636de2bdb3dSTom St Denis #define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_GATE_DIS__SHIFT 0x0000000f 9637de2bdb3dSTom St Denis #define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_MSTAT_GATE_DIS_MASK 0x00080000L 9638de2bdb3dSTom St Denis #define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_MSTAT_GATE_DIS__SHIFT 0x00000013 9639de2bdb3dSTom St Denis #define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_SDYN_GATE_DIS_MASK 0x00040000L 9640de2bdb3dSTom St Denis #define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_SDYN_GATE_DIS__SHIFT 0x00000012 9641de2bdb3dSTom St Denis #define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_SSTAT_GATE_DIS_MASK 0x00100000L 9642de2bdb3dSTom St Denis #define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_SSTAT_GATE_DIS__SHIFT 0x00000014 9643de2bdb3dSTom St Denis #define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_REG_GATE_DIS_MASK 0x00010000L 9644de2bdb3dSTom St Denis #define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_REG_GATE_DIS__SHIFT 0x00000010 9645de2bdb3dSTom St Denis #define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_TURN_OFF_DELAY_MASK 0x00000ff0L 9646de2bdb3dSTom St Denis #define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_TURN_OFF_DELAY__SHIFT 0x00000004 9647de2bdb3dSTom St Denis #define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_TURN_ON_DELAY_MASK 0x0000000fL 9648de2bdb3dSTom St Denis #define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_TURN_ON_DELAY__SHIFT 0x00000000 9649de2bdb3dSTom St Denis #define XDMA_IF_BIF_STATUS__XDMA_IF_BIF_ERROR_CLEAR_MASK 0x00000100L 9650de2bdb3dSTom St Denis #define XDMA_IF_BIF_STATUS__XDMA_IF_BIF_ERROR_CLEAR__SHIFT 0x00000008 9651de2bdb3dSTom St Denis #define XDMA_IF_BIF_STATUS__XDMA_IF_BIF_ERROR_STATUS_MASK 0x0000000fL 9652de2bdb3dSTom St Denis #define XDMA_IF_BIF_STATUS__XDMA_IF_BIF_ERROR_STATUS__SHIFT 0x00000000 9653de2bdb3dSTom St Denis #define XDMA_INTERRUPT__XDMA_MSTR_MEM_URGENT_ACK_MASK 0x00000400L 9654de2bdb3dSTom St Denis #define XDMA_INTERRUPT__XDMA_MSTR_MEM_URGENT_ACK__SHIFT 0x0000000a 9655de2bdb3dSTom St Denis #define XDMA_INTERRUPT__XDMA_MSTR_MEM_URGENT_MASK_MASK 0x00000200L 9656de2bdb3dSTom St Denis #define XDMA_INTERRUPT__XDMA_MSTR_MEM_URGENT_MASK__SHIFT 0x00000009 9657de2bdb3dSTom St Denis #define XDMA_INTERRUPT__XDMA_MSTR_MEM_URGENT_STAT_MASK 0x00000100L 9658de2bdb3dSTom St Denis #define XDMA_INTERRUPT__XDMA_MSTR_MEM_URGENT_STAT__SHIFT 0x00000008 9659de2bdb3dSTom St Denis #define XDMA_INTERRUPT__XDMA_MSTR_UNDERFLOW_ACK_MASK 0x00004000L 9660de2bdb3dSTom St Denis #define XDMA_INTERRUPT__XDMA_MSTR_UNDERFLOW_ACK__SHIFT 0x0000000e 9661de2bdb3dSTom St Denis #define XDMA_INTERRUPT__XDMA_MSTR_UNDERFLOW_MASK_MASK 0x00002000L 9662de2bdb3dSTom St Denis #define XDMA_INTERRUPT__XDMA_MSTR_UNDERFLOW_MASK__SHIFT 0x0000000d 9663de2bdb3dSTom St Denis #define XDMA_INTERRUPT__XDMA_MSTR_UNDERFLOW_STAT_MASK 0x00001000L 9664de2bdb3dSTom St Denis #define XDMA_INTERRUPT__XDMA_MSTR_UNDERFLOW_STAT__SHIFT 0x0000000c 9665de2bdb3dSTom St Denis #define XDMA_INTERRUPT__XDMA_SLV_READ_URGENT_ACK_MASK 0x00040000L 9666de2bdb3dSTom St Denis #define XDMA_INTERRUPT__XDMA_SLV_READ_URGENT_ACK__SHIFT 0x00000012 9667de2bdb3dSTom St Denis #define XDMA_INTERRUPT__XDMA_SLV_READ_URGENT_MASK_MASK 0x00020000L 9668de2bdb3dSTom St Denis #define XDMA_INTERRUPT__XDMA_SLV_READ_URGENT_MASK__SHIFT 0x00000011 9669de2bdb3dSTom St Denis #define XDMA_INTERRUPT__XDMA_SLV_READ_URGENT_STAT_MASK 0x00010000L 9670de2bdb3dSTom St Denis #define XDMA_INTERRUPT__XDMA_SLV_READ_URGENT_STAT__SHIFT 0x00000010 9671de2bdb3dSTom St Denis #define XDMA_LOCAL_SURFACE_TILING1__XDMA_LOCAL_ARRAY_MODE_MASK 0x0000000fL 9672de2bdb3dSTom St Denis #define XDMA_LOCAL_SURFACE_TILING1__XDMA_LOCAL_ARRAY_MODE__SHIFT 0x00000000 9673de2bdb3dSTom St Denis #define XDMA_LOCAL_SURFACE_TILING1__XDMA_LOCAL_BANK_HEIGHT_MASK 0x00000c00L 9674de2bdb3dSTom St Denis #define XDMA_LOCAL_SURFACE_TILING1__XDMA_LOCAL_BANK_HEIGHT__SHIFT 0x0000000a 9675de2bdb3dSTom St Denis #define XDMA_LOCAL_SURFACE_TILING1__XDMA_LOCAL_BANK_WIDTH_MASK 0x00000300L 9676de2bdb3dSTom St Denis #define XDMA_LOCAL_SURFACE_TILING1__XDMA_LOCAL_BANK_WIDTH__SHIFT 0x00000008 9677de2bdb3dSTom St Denis #define XDMA_LOCAL_SURFACE_TILING1__XDMA_LOCAL_MACRO_TILE_ASPECT_MASK 0x00003000L 9678de2bdb3dSTom St Denis #define XDMA_LOCAL_SURFACE_TILING1__XDMA_LOCAL_MACRO_TILE_ASPECT__SHIFT 0x0000000c 9679de2bdb3dSTom St Denis #define XDMA_LOCAL_SURFACE_TILING1__XDMA_LOCAL_NUM_BANKS_MASK 0x00300000L 9680de2bdb3dSTom St Denis #define XDMA_LOCAL_SURFACE_TILING1__XDMA_LOCAL_NUM_BANKS__SHIFT 0x00000014 9681de2bdb3dSTom St Denis #define XDMA_LOCAL_SURFACE_TILING1__XDMA_LOCAL_TILE_SPLIT_MASK 0x00000070L 9682de2bdb3dSTom St Denis #define XDMA_LOCAL_SURFACE_TILING1__XDMA_LOCAL_TILE_SPLIT__SHIFT 0x00000004 9683de2bdb3dSTom St Denis #define XDMA_LOCAL_SURFACE_TILING2__XDMA_LOCAL_MICRO_TILE_MODE_MASK 0x00c00000L 9684de2bdb3dSTom St Denis #define XDMA_LOCAL_SURFACE_TILING2__XDMA_LOCAL_MICRO_TILE_MODE__SHIFT 0x00000016 9685de2bdb3dSTom St Denis #define XDMA_LOCAL_SURFACE_TILING2__XDMA_LOCAL_PIPE_CONFIG_MASK 0xf8000000L 9686de2bdb3dSTom St Denis #define XDMA_LOCAL_SURFACE_TILING2__XDMA_LOCAL_PIPE_CONFIG__SHIFT 0x0000001b 9687de2bdb3dSTom St Denis #define XDMA_LOCAL_SURFACE_TILING2__XDMA_LOCAL_PIPE_INTERLEAVE_SIZE_MASK 0x00000007L 9688de2bdb3dSTom St Denis #define XDMA_LOCAL_SURFACE_TILING2__XDMA_LOCAL_PIPE_INTERLEAVE_SIZE__SHIFT 0x00000000 9689de2bdb3dSTom St Denis #define XDMA_MC_PCIE_CLIENT_CONFIG__XDMA_MC_PCIE_PRIV_MASK 0x00010000L 9690de2bdb3dSTom St Denis #define XDMA_MC_PCIE_CLIENT_CONFIG__XDMA_MC_PCIE_PRIV__SHIFT 0x00000010 9691de2bdb3dSTom St Denis #define XDMA_MC_PCIE_CLIENT_CONFIG__XDMA_MC_PCIE_SWAP_MASK 0x00000300L 9692de2bdb3dSTom St Denis #define XDMA_MC_PCIE_CLIENT_CONFIG__XDMA_MC_PCIE_SWAP__SHIFT 0x00000008 9693de2bdb3dSTom St Denis #define XDMA_MC_PCIE_CLIENT_CONFIG__XDMA_MC_PCIE_VMID_MASK 0x0000f000L 9694de2bdb3dSTom St Denis #define XDMA_MC_PCIE_CLIENT_CONFIG__XDMA_MC_PCIE_VMID__SHIFT 0x0000000c 9695de2bdb3dSTom St Denis #define XDMA_MEM_POWER_CNTL__XDMA_MEM_LIGHT_SLEEP_DIS_MASK 0x00000001L 9696de2bdb3dSTom St Denis #define XDMA_MEM_POWER_CNTL__XDMA_MEM_LIGHT_SLEEP_DIS__SHIFT 0x00000000 9697de2bdb3dSTom St Denis #define XDMA_MEM_POWER_CNTL__XDMA_MEM_LIGHT_SLEEP_MODE_FORCE_MASK 0x00010000L 9698de2bdb3dSTom St Denis #define XDMA_MEM_POWER_CNTL__XDMA_MEM_LIGHT_SLEEP_MODE_FORCE__SHIFT 0x00000010 9699de2bdb3dSTom St Denis #define XDMA_MEM_POWER_CNTL__XDMA_MEM_POWER_STATE_MASK 0xc0000000L 9700de2bdb3dSTom St Denis #define XDMA_MEM_POWER_CNTL__XDMA_MEM_POWER_STATE__SHIFT 0x0000001e 9701de2bdb3dSTom St Denis #define XDMA_MEM_POWER_CNTL__XDMA_MEM_SHUTDOWN_DIS_MASK 0x00000100L 9702de2bdb3dSTom St Denis #define XDMA_MEM_POWER_CNTL__XDMA_MEM_SHUTDOWN_DIS__SHIFT 0x00000008 9703de2bdb3dSTom St Denis #define XDMA_MEM_POWER_CNTL__XDMA_MEM_SHUTDOWN_MODE_FORCE_MASK 0x01000000L 9704de2bdb3dSTom St Denis #define XDMA_MEM_POWER_CNTL__XDMA_MEM_SHUTDOWN_MODE_FORCE__SHIFT 0x00000018 9705de2bdb3dSTom St Denis #define XDMA_MSTR_CMD_URGENT_CNTL__XDMA_MSTR_CMD_URGENT_LEVEL_MASK 0x00000f00L 9706de2bdb3dSTom St Denis #define XDMA_MSTR_CMD_URGENT_CNTL__XDMA_MSTR_CMD_URGENT_LEVEL__SHIFT 0x00000008 9707de2bdb3dSTom St Denis #define XDMA_MSTR_CNTL__XDMA_MSTR_DEBUG_MODE_MASK 0x00040000L 9708de2bdb3dSTom St Denis #define XDMA_MSTR_CNTL__XDMA_MSTR_DEBUG_MODE__SHIFT 0x00000012 9709de2bdb3dSTom St Denis #define XDMA_MSTR_CNTL__XDMA_MSTR_ENABLE_MASK 0x00010000L 9710de2bdb3dSTom St Denis #define XDMA_MSTR_CNTL__XDMA_MSTR_ENABLE__SHIFT 0x00000010 9711de2bdb3dSTom St Denis #define XDMA_MSTR_CNTL__XDMA_MSTR_MEM_READY_MASK 0x00000200L 9712de2bdb3dSTom St Denis #define XDMA_MSTR_CNTL__XDMA_MSTR_MEM_READY__SHIFT 0x00000009 9713de2bdb3dSTom St Denis #define XDMA_MSTR_CNTL__XDMA_MSTR_SOFT_RESET_MASK 0x00100000L 9714de2bdb3dSTom St Denis #define XDMA_MSTR_CNTL__XDMA_MSTR_SOFT_RESET__SHIFT 0x00000014 9715de2bdb3dSTom St Denis #define XDMA_MSTR_HEIGHT__XDMA_MSTR_ACTIVE_HEIGHT_MASK 0x00003fffL 9716de2bdb3dSTom St Denis #define XDMA_MSTR_HEIGHT__XDMA_MSTR_ACTIVE_HEIGHT__SHIFT 0x00000000 9717de2bdb3dSTom St Denis #define XDMA_MSTR_HEIGHT__XDMA_MSTR_FRAME_HEIGHT_MASK 0x3fff0000L 9718de2bdb3dSTom St Denis #define XDMA_MSTR_HEIGHT__XDMA_MSTR_FRAME_HEIGHT__SHIFT 0x00000010 9719de2bdb3dSTom St Denis #define XDMA_MSTR_LOCAL_SURFACE_BASE_ADDR_HIGH__XDMA_MSTR_LOCAL_SURFACE_BASE_ADDR_HIGH_MASK 0x000000ffL 9720de2bdb3dSTom St Denis #define XDMA_MSTR_LOCAL_SURFACE_BASE_ADDR_HIGH__XDMA_MSTR_LOCAL_SURFACE_BASE_ADDR_HIGH__SHIFT 0x00000000 9721de2bdb3dSTom St Denis #define XDMA_MSTR_LOCAL_SURFACE_BASE_ADDR__XDMA_MSTR_LOCAL_SURFACE_BASE_ADDR_MASK 0xffffffffL 9722de2bdb3dSTom St Denis #define XDMA_MSTR_LOCAL_SURFACE_BASE_ADDR__XDMA_MSTR_LOCAL_SURFACE_BASE_ADDR__SHIFT 0x00000000 9723de2bdb3dSTom St Denis #define XDMA_MSTR_LOCAL_SURFACE_PITCH__XDMA_MSTR_LOCAL_SURFACE_PITCH_MASK 0x00003fffL 9724de2bdb3dSTom St Denis #define XDMA_MSTR_LOCAL_SURFACE_PITCH__XDMA_MSTR_LOCAL_SURFACE_PITCH__SHIFT 0x00000000 9725de2bdb3dSTom St Denis #define XDMA_MSTR_MEM_CLIENT_CONFIG__XDMA_MSTR_MEM_CLIENT_PRIV_MASK 0x00010000L 9726de2bdb3dSTom St Denis #define XDMA_MSTR_MEM_CLIENT_CONFIG__XDMA_MSTR_MEM_CLIENT_PRIV__SHIFT 0x00000010 9727de2bdb3dSTom St Denis #define XDMA_MSTR_MEM_CLIENT_CONFIG__XDMA_MSTR_MEM_CLIENT_SWAP_MASK 0x00000300L 9728de2bdb3dSTom St Denis #define XDMA_MSTR_MEM_CLIENT_CONFIG__XDMA_MSTR_MEM_CLIENT_SWAP__SHIFT 0x00000008 9729de2bdb3dSTom St Denis #define XDMA_MSTR_MEM_CLIENT_CONFIG__XDMA_MSTR_MEM_CLIENT_VMID_MASK 0x0000f000L 9730de2bdb3dSTom St Denis #define XDMA_MSTR_MEM_CLIENT_CONFIG__XDMA_MSTR_MEM_CLIENT_VMID__SHIFT 0x0000000c 9731de2bdb3dSTom St Denis #define XDMA_MSTR_MEM_NACK_STATUS__XDMA_MSTR_MEM_NACK_CLR_MASK 0x00010000L 9732de2bdb3dSTom St Denis #define XDMA_MSTR_MEM_NACK_STATUS__XDMA_MSTR_MEM_NACK_CLR__SHIFT 0x00000010 9733de2bdb3dSTom St Denis #define XDMA_MSTR_MEM_NACK_STATUS__XDMA_MSTR_MEM_NACK_MASK 0x00003000L 9734de2bdb3dSTom St Denis #define XDMA_MSTR_MEM_NACK_STATUS__XDMA_MSTR_MEM_NACK__SHIFT 0x0000000c 9735de2bdb3dSTom St Denis #define XDMA_MSTR_MEM_NACK_STATUS__XDMA_MSTR_MEM_NACK_TAG_MASK 0x000003ffL 9736de2bdb3dSTom St Denis #define XDMA_MSTR_MEM_NACK_STATUS__XDMA_MSTR_MEM_NACK_TAG__SHIFT 0x00000000 9737de2bdb3dSTom St Denis #define XDMA_MSTR_MEM_URGENT_CNTL__XDMA_MSTR_MEM_CLIENT_STALL_MASK 0x00000001L 9738de2bdb3dSTom St Denis #define XDMA_MSTR_MEM_URGENT_CNTL__XDMA_MSTR_MEM_CLIENT_STALL__SHIFT 0x00000000 9739de2bdb3dSTom St Denis #define XDMA_MSTR_MEM_URGENT_CNTL__XDMA_MSTR_MEM_STALL_DELAY_MASK 0x0000f000L 9740de2bdb3dSTom St Denis #define XDMA_MSTR_MEM_URGENT_CNTL__XDMA_MSTR_MEM_STALL_DELAY__SHIFT 0x0000000c 9741de2bdb3dSTom St Denis #define XDMA_MSTR_MEM_URGENT_CNTL__XDMA_MSTR_MEM_URGENT_LEVEL_MASK 0x00000f00L 9742de2bdb3dSTom St Denis #define XDMA_MSTR_MEM_URGENT_CNTL__XDMA_MSTR_MEM_URGENT_LEVEL__SHIFT 0x00000008 9743de2bdb3dSTom St Denis #define XDMA_MSTR_MEM_URGENT_CNTL__XDMA_MSTR_MEM_URGENT_LIMIT_MASK 0x000000f0L 9744de2bdb3dSTom St Denis #define XDMA_MSTR_MEM_URGENT_CNTL__XDMA_MSTR_MEM_URGENT_LIMIT__SHIFT 0x00000004 9745de2bdb3dSTom St Denis #define XDMA_MSTR_MEM_URGENT_CNTL__XDMA_MSTR_MEM_URGENT_TIMER_MASK 0xffff0000L 9746de2bdb3dSTom St Denis #define XDMA_MSTR_MEM_URGENT_CNTL__XDMA_MSTR_MEM_URGENT_TIMER__SHIFT 0x00000010 9747de2bdb3dSTom St Denis #define XDMA_MSTR_PCIE_NACK_STATUS__XDMA_MSTR_PCIE_NACK_CLR_MASK 0x00010000L 9748de2bdb3dSTom St Denis #define XDMA_MSTR_PCIE_NACK_STATUS__XDMA_MSTR_PCIE_NACK_CLR__SHIFT 0x00000010 9749de2bdb3dSTom St Denis #define XDMA_MSTR_PCIE_NACK_STATUS__XDMA_MSTR_PCIE_NACK_MASK 0x00003000L 9750de2bdb3dSTom St Denis #define XDMA_MSTR_PCIE_NACK_STATUS__XDMA_MSTR_PCIE_NACK__SHIFT 0x0000000c 9751de2bdb3dSTom St Denis #define XDMA_MSTR_PCIE_NACK_STATUS__XDMA_MSTR_PCIE_NACK_TAG_MASK 0x000003ffL 9752de2bdb3dSTom St Denis #define XDMA_MSTR_PCIE_NACK_STATUS__XDMA_MSTR_PCIE_NACK_TAG__SHIFT 0x00000000 9753de2bdb3dSTom St Denis #define XDMA_MSTR_READ_COMMAND__XDMA_MSTR_REQUEST_PREFETCH_MASK 0x3fff0000L 9754de2bdb3dSTom St Denis #define XDMA_MSTR_READ_COMMAND__XDMA_MSTR_REQUEST_PREFETCH__SHIFT 0x00000010 9755de2bdb3dSTom St Denis #define XDMA_MSTR_READ_COMMAND__XDMA_MSTR_REQUEST_SIZE_MASK 0x00003fffL 9756de2bdb3dSTom St Denis #define XDMA_MSTR_READ_COMMAND__XDMA_MSTR_REQUEST_SIZE__SHIFT 0x00000000 9757de2bdb3dSTom St Denis #define XDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH__XDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH_MASK 0x000000ffL 9758de2bdb3dSTom St Denis #define XDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH__XDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH__SHIFT 0x00000000 9759de2bdb3dSTom St Denis #define XDMA_MSTR_REMOTE_GPU_ADDRESS__XDMA_MSTR_REMOTE_GPU_ADDRESS_MASK 0xffffffffL 9760de2bdb3dSTom St Denis #define XDMA_MSTR_REMOTE_GPU_ADDRESS__XDMA_MSTR_REMOTE_GPU_ADDRESS__SHIFT 0x00000000 9761de2bdb3dSTom St Denis #define XDMA_MSTR_REMOTE_SURFACE_BASE_HIGH__XDMA_MSTR_REMOTE_SURFACE_BASE_HIGH_MASK 0x000000ffL 9762de2bdb3dSTom St Denis #define XDMA_MSTR_REMOTE_SURFACE_BASE_HIGH__XDMA_MSTR_REMOTE_SURFACE_BASE_HIGH__SHIFT 0x00000000 9763de2bdb3dSTom St Denis #define XDMA_MSTR_REMOTE_SURFACE_BASE__XDMA_MSTR_REMOTE_SURFACE_BASE_MASK 0xffffffffL 9764de2bdb3dSTom St Denis #define XDMA_MSTR_REMOTE_SURFACE_BASE__XDMA_MSTR_REMOTE_SURFACE_BASE__SHIFT 0x00000000 9765de2bdb3dSTom St Denis #define XDMA_MSTR_STATUS__XDMA_MSTR_VCOUNT_CURRENT_MASK 0x00003fffL 9766de2bdb3dSTom St Denis #define XDMA_MSTR_STATUS__XDMA_MSTR_VCOUNT_CURRENT__SHIFT 0x00000000 9767de2bdb3dSTom St Denis #define XDMA_MSTR_STATUS__XDMA_MSTR_WRITE_LINE_CURRENT_MASK 0x3fff0000L 9768de2bdb3dSTom St Denis #define XDMA_MSTR_STATUS__XDMA_MSTR_WRITE_LINE_CURRENT__SHIFT 0x00000010 9769de2bdb3dSTom St Denis #define XDMA_RBBMIF_RDWR_CNTL__XDMA_RBBMIF_RDWR_DELAY_MASK 0x00000007L 9770de2bdb3dSTom St Denis #define XDMA_RBBMIF_RDWR_CNTL__XDMA_RBBMIF_RDWR_DELAY__SHIFT 0x00000000 9771de2bdb3dSTom St Denis #define XDMA_RBBMIF_RDWR_CNTL__XDMA_RBBMIF_RDWR_TIMEOUT_DIS_MASK 0x00000008L 9772de2bdb3dSTom St Denis #define XDMA_RBBMIF_RDWR_CNTL__XDMA_RBBMIF_RDWR_TIMEOUT_DIS__SHIFT 0x00000003 9773de2bdb3dSTom St Denis #define XDMA_RBBMIF_RDWR_CNTL__XDMA_RBBMIF_TIMEOUT_DELAY_MASK 0xffff8000L 9774de2bdb3dSTom St Denis #define XDMA_RBBMIF_RDWR_CNTL__XDMA_RBBMIF_TIMEOUT_DELAY__SHIFT 0x0000000f 9775de2bdb3dSTom St Denis #define XDMA_SLV_CNTL__XDMA_SLV_ACTIVE_MASK 0x00000100L 9776de2bdb3dSTom St Denis #define XDMA_SLV_CNTL__XDMA_SLV_ACTIVE__SHIFT 0x00000008 9777de2bdb3dSTom St Denis #define XDMA_SLV_CNTL__XDMA_SLV_ENABLE_MASK 0x00010000L 9778de2bdb3dSTom St Denis #define XDMA_SLV_CNTL__XDMA_SLV_ENABLE__SHIFT 0x00000010 9779de2bdb3dSTom St Denis #define XDMA_SLV_CNTL__XDMA_SLV_MEM_READY_MASK 0x00000200L 9780de2bdb3dSTom St Denis #define XDMA_SLV_CNTL__XDMA_SLV_MEM_READY__SHIFT 0x00000009 9781de2bdb3dSTom St Denis #define XDMA_SLV_CNTL__XDMA_SLV_READ_LAT_TEST_EN_MASK 0x00080000L 9782de2bdb3dSTom St Denis #define XDMA_SLV_CNTL__XDMA_SLV_READ_LAT_TEST_EN__SHIFT 0x00000013 9783de2bdb3dSTom St Denis #define XDMA_SLV_CNTL__XDMA_SLV_SOFT_RESET_MASK 0x00100000L 9784de2bdb3dSTom St Denis #define XDMA_SLV_CNTL__XDMA_SLV_SOFT_RESET__SHIFT 0x00000014 9785de2bdb3dSTom St Denis #define XDMA_SLV_FLIP_PENDING__XDMA_SLV_FLIP_PENDING_MASK 0x00000001L 9786de2bdb3dSTom St Denis #define XDMA_SLV_FLIP_PENDING__XDMA_SLV_FLIP_PENDING__SHIFT 0x00000000 9787de2bdb3dSTom St Denis #define XDMA_SLV_MEM_CLIENT_CONFIG__XDMA_SLV_MEM_CLIENT_PRIV_MASK 0x00010000L 9788de2bdb3dSTom St Denis #define XDMA_SLV_MEM_CLIENT_CONFIG__XDMA_SLV_MEM_CLIENT_PRIV__SHIFT 0x00000010 9789de2bdb3dSTom St Denis #define XDMA_SLV_MEM_CLIENT_CONFIG__XDMA_SLV_MEM_CLIENT_SWAP_MASK 0x00000300L 9790de2bdb3dSTom St Denis #define XDMA_SLV_MEM_CLIENT_CONFIG__XDMA_SLV_MEM_CLIENT_SWAP__SHIFT 0x00000008 9791de2bdb3dSTom St Denis #define XDMA_SLV_MEM_CLIENT_CONFIG__XDMA_SLV_MEM_CLIENT_VMID_MASK 0x0000f000L 9792de2bdb3dSTom St Denis #define XDMA_SLV_MEM_CLIENT_CONFIG__XDMA_SLV_MEM_CLIENT_VMID__SHIFT 0x0000000c 9793de2bdb3dSTom St Denis #define XDMA_SLV_MEM_NACK_STATUS__XDMA_SLV_MEM_NACK_CLR_MASK 0x80000000L 9794de2bdb3dSTom St Denis #define XDMA_SLV_MEM_NACK_STATUS__XDMA_SLV_MEM_NACK_CLR__SHIFT 0x0000001f 9795de2bdb3dSTom St Denis #define XDMA_SLV_MEM_NACK_STATUS__XDMA_SLV_MEM_NACK_MASK 0x00030000L 9796de2bdb3dSTom St Denis #define XDMA_SLV_MEM_NACK_STATUS__XDMA_SLV_MEM_NACK__SHIFT 0x00000010 9797de2bdb3dSTom St Denis #define XDMA_SLV_MEM_NACK_STATUS__XDMA_SLV_MEM_NACK_TAG_MASK 0x0000ffffL 9798de2bdb3dSTom St Denis #define XDMA_SLV_MEM_NACK_STATUS__XDMA_SLV_MEM_NACK_TAG__SHIFT 0x00000000 9799de2bdb3dSTom St Denis #define XDMA_SLV_PCIE_NACK_STATUS__XDMA_SLV_PCIE_NACK_CLR_MASK 0x00010000L 9800de2bdb3dSTom St Denis #define XDMA_SLV_PCIE_NACK_STATUS__XDMA_SLV_PCIE_NACK_CLR__SHIFT 0x00000010 9801de2bdb3dSTom St Denis #define XDMA_SLV_PCIE_NACK_STATUS__XDMA_SLV_PCIE_NACK_MASK 0x00003000L 9802de2bdb3dSTom St Denis #define XDMA_SLV_PCIE_NACK_STATUS__XDMA_SLV_PCIE_NACK__SHIFT 0x0000000c 9803de2bdb3dSTom St Denis #define XDMA_SLV_PCIE_NACK_STATUS__XDMA_SLV_PCIE_NACK_TAG_MASK 0x000003ffL 9804de2bdb3dSTom St Denis #define XDMA_SLV_PCIE_NACK_STATUS__XDMA_SLV_PCIE_NACK_TAG__SHIFT 0x00000000 9805de2bdb3dSTom St Denis #define XDMA_SLV_READ_LATENCY_AVE__XDMA_SLV_READ_LATENCY_ACC_MASK 0x000fffffL 9806de2bdb3dSTom St Denis #define XDMA_SLV_READ_LATENCY_AVE__XDMA_SLV_READ_LATENCY_ACC__SHIFT 0x00000000 9807de2bdb3dSTom St Denis #define XDMA_SLV_READ_LATENCY_AVE__XDMA_SLV_READ_LATENCY_COUNT_MASK 0xfff00000L 9808de2bdb3dSTom St Denis #define XDMA_SLV_READ_LATENCY_AVE__XDMA_SLV_READ_LATENCY_COUNT__SHIFT 0x00000014 9809de2bdb3dSTom St Denis #define XDMA_SLV_READ_LATENCY_MINMAX__XDMA_SLV_READ_LATENCY_MAX_MASK 0xffff0000L 9810de2bdb3dSTom St Denis #define XDMA_SLV_READ_LATENCY_MINMAX__XDMA_SLV_READ_LATENCY_MAX__SHIFT 0x00000010 9811de2bdb3dSTom St Denis #define XDMA_SLV_READ_LATENCY_MINMAX__XDMA_SLV_READ_LATENCY_MIN_MASK 0x0000ffffL 9812de2bdb3dSTom St Denis #define XDMA_SLV_READ_LATENCY_MINMAX__XDMA_SLV_READ_LATENCY_MIN__SHIFT 0x00000000 9813de2bdb3dSTom St Denis #define XDMA_SLV_READ_LATENCY_TIMER__XDMA_SLV_READ_LATENCY_TIMER_MASK 0x0000ffffL 9814de2bdb3dSTom St Denis #define XDMA_SLV_READ_LATENCY_TIMER__XDMA_SLV_READ_LATENCY_TIMER__SHIFT 0x00000000 9815de2bdb3dSTom St Denis #define XDMA_SLV_READ_URGENT_CNTL__XDMA_SLV_READ_CLIENT_STALL_MASK 0x00000001L 9816de2bdb3dSTom St Denis #define XDMA_SLV_READ_URGENT_CNTL__XDMA_SLV_READ_CLIENT_STALL__SHIFT 0x00000000 9817de2bdb3dSTom St Denis #define XDMA_SLV_READ_URGENT_CNTL__XDMA_SLV_READ_STALL_DELAY_MASK 0x0000f000L 9818de2bdb3dSTom St Denis #define XDMA_SLV_READ_URGENT_CNTL__XDMA_SLV_READ_STALL_DELAY__SHIFT 0x0000000c 9819de2bdb3dSTom St Denis #define XDMA_SLV_READ_URGENT_CNTL__XDMA_SLV_READ_URGENT_LEVEL_MASK 0x00000f00L 9820de2bdb3dSTom St Denis #define XDMA_SLV_READ_URGENT_CNTL__XDMA_SLV_READ_URGENT_LEVEL__SHIFT 0x00000008 9821de2bdb3dSTom St Denis #define XDMA_SLV_READ_URGENT_CNTL__XDMA_SLV_READ_URGENT_LIMIT_MASK 0x000000f0L 9822de2bdb3dSTom St Denis #define XDMA_SLV_READ_URGENT_CNTL__XDMA_SLV_READ_URGENT_LIMIT__SHIFT 0x00000004 9823de2bdb3dSTom St Denis #define XDMA_SLV_READ_URGENT_CNTL__XDMA_SLV_READ_URGENT_TIMER_MASK 0xffff0000L 9824de2bdb3dSTom St Denis #define XDMA_SLV_READ_URGENT_CNTL__XDMA_SLV_READ_URGENT_TIMER__SHIFT 0x00000010 9825de2bdb3dSTom St Denis #define XDMA_SLV_REMOTE_GPU_ADDRESS_HIGH__XDMA_SLV_REMOTE_GPU_ADDRESS_HIGH_MASK 0x000000ffL 9826de2bdb3dSTom St Denis #define XDMA_SLV_REMOTE_GPU_ADDRESS_HIGH__XDMA_SLV_REMOTE_GPU_ADDRESS_HIGH__SHIFT 0x00000000 9827de2bdb3dSTom St Denis #define XDMA_SLV_REMOTE_GPU_ADDRESS__XDMA_SLV_REMOTE_GPU_ADDRESS_MASK 0xffffffffL 9828de2bdb3dSTom St Denis #define XDMA_SLV_REMOTE_GPU_ADDRESS__XDMA_SLV_REMOTE_GPU_ADDRESS__SHIFT 0x00000000 9829de2bdb3dSTom St Denis #define XDMA_SLV_SLS_PITCH__XDMA_SLV_SLS_PITCH_MASK 0x00003fffL 9830de2bdb3dSTom St Denis #define XDMA_SLV_SLS_PITCH__XDMA_SLV_SLS_PITCH__SHIFT 0x00000000 9831de2bdb3dSTom St Denis #define XDMA_SLV_SLS_PITCH__XDMA_SLV_SLS_WIDTH_MASK 0x3fff0000L 9832de2bdb3dSTom St Denis #define XDMA_SLV_SLS_PITCH__XDMA_SLV_SLS_WIDTH__SHIFT 0x00000010 9833de2bdb3dSTom St Denis #define XDMA_SLV_WB_RATE_CNTL__XDMA_SLV_WB_BURST_PERIOD_MASK 0xffff0000L 9834de2bdb3dSTom St Denis #define XDMA_SLV_WB_RATE_CNTL__XDMA_SLV_WB_BURST_PERIOD__SHIFT 0x00000010 9835de2bdb3dSTom St Denis #define XDMA_SLV_WB_RATE_CNTL__XDMA_SLV_WB_BURST_SIZE_MASK 0x000001ffL 9836de2bdb3dSTom St Denis #define XDMA_SLV_WB_RATE_CNTL__XDMA_SLV_WB_BURST_SIZE__SHIFT 0x00000000 9837de2bdb3dSTom St Denis #define XDMA_SLV_WRITE_URGENT_CNTL__XDMA_SLV_WRITE_STALL_DELAY_MASK 0x0000f000L 9838de2bdb3dSTom St Denis #define XDMA_SLV_WRITE_URGENT_CNTL__XDMA_SLV_WRITE_STALL_DELAY__SHIFT 0x0000000c 9839de2bdb3dSTom St Denis #define XDMA_SLV_WRITE_URGENT_CNTL__XDMA_SLV_WRITE_STALL_MASK 0x00000001L 9840de2bdb3dSTom St Denis #define XDMA_SLV_WRITE_URGENT_CNTL__XDMA_SLV_WRITE_STALL__SHIFT 0x00000000 9841de2bdb3dSTom St Denis #define XDMA_SLV_WRITE_URGENT_CNTL__XDMA_SLV_WRITE_URGENT_LEVEL_MASK 0x00000f00L 9842de2bdb3dSTom St Denis #define XDMA_SLV_WRITE_URGENT_CNTL__XDMA_SLV_WRITE_URGENT_LEVEL__SHIFT 0x00000008 9843de2bdb3dSTom St Denis #define XDMA_TEST_DEBUG_DATA__XDMA_TEST_DEBUG_DATA_MASK 0xffffffffL 9844de2bdb3dSTom St Denis #define XDMA_TEST_DEBUG_DATA__XDMA_TEST_DEBUG_DATA__SHIFT 0x00000000 9845de2bdb3dSTom St Denis #define XDMA_TEST_DEBUG_INDEX__XDMA_TEST_DEBUG_INDEX_MASK 0x000000ffL 9846de2bdb3dSTom St Denis #define XDMA_TEST_DEBUG_INDEX__XDMA_TEST_DEBUG_INDEX__SHIFT 0x00000000 9847de2bdb3dSTom St Denis #define XDMA_TEST_DEBUG_INDEX__XDMA_TEST_DEBUG_WRITE_EN_MASK 0x00000100L 9848de2bdb3dSTom St Denis #define XDMA_TEST_DEBUG_INDEX__XDMA_TEST_DEBUG_WRITE_EN__SHIFT 0x00000008 9849de2bdb3dSTom St Denis 98506863660dSAlex Deucher // DATA_FORMAT 98516863660dSAlex Deucher #define DATA_FORMAT__INTERLEAVE_EN_MASK 0x00000001L 98526863660dSAlex Deucher #define DATA_FORMAT__INTERLEAVE_EN__SHIFT 0x00000000 98536863660dSAlex Deucher #define DATA_FORMAT__RESET_REQ_AT_EOL_MASK 0x00000010L 98546863660dSAlex Deucher #define DATA_FORMAT__RESET_REQ_AT_EOL__SHIFT 0x00000004 98556863660dSAlex Deucher #define DATA_FORMAT__PREFETCH_MASK 0x00001000L 98566863660dSAlex Deucher #define DATA_FORMAT__PREFETCH__SHIFT 0x0000000c 98576863660dSAlex Deucher #define DATA_FORMAT__SOF_READ_PT_MASK 0x001f0000L 98586863660dSAlex Deucher #define DATA_FORMAT__SOF_READ_PT__SHIFT 0x00000010 98596863660dSAlex Deucher #define DATA_FORMAT__REQUEST_MODE_MASK 0x03000000L 98606863660dSAlex Deucher #define DATA_FORMAT__REQUEST_MODE__SHIFT 0x00000018 98616863660dSAlex Deucher #define DATA_FORMAT__ALLOW_REQ_MODE_1_2_MASK 0x10000000L 98626863660dSAlex Deucher #define DATA_FORMAT__ALLOW_REQ_MODE_1_2__SHIFT 0x0000001c 98636863660dSAlex Deucher 98646863660dSAlex Deucher 98656863660dSAlex Deucher // DC_LB_MEMORY_SPLIT 98666863660dSAlex Deucher #define DC_LB_MEMORY_SPLIT__LB_NUM_PARTITIONS_MASK 0x000f0000L 98676863660dSAlex Deucher #define DC_LB_MEMORY_SPLIT__LB_NUM_PARTITIONS__SHIFT 0x00000010 98686863660dSAlex Deucher #define DC_LB_MEMORY_SPLIT__DC_LB_MEMORY_CONFIG_MASK 0x00300000L 98696863660dSAlex Deucher #define DC_LB_MEMORY_SPLIT__DC_LB_MEMORY_CONFIG__SHIFT 0x00000014 98706863660dSAlex Deucher 98716863660dSAlex Deucher // DC_LB_MEM_SIZE 98726863660dSAlex Deucher #define DC_LB_MEM_SIZE__DC_LB_MEM_SIZE_MASK 0x000007ffL 98736863660dSAlex Deucher #define DC_LB_MEM_SIZE__DC_LB_MEM_SIZE__SHIFT 0x00000000 98746863660dSAlex Deucher 98756863660dSAlex Deucher // SCL_TAP_CONTROL 98766863660dSAlex Deucher #define SCL_TAP_CONTROL__SCL_V_NUM_OF_TAPS_MASK 0x00000007L 98776863660dSAlex Deucher #define SCL_TAP_CONTROL__SCL_V_NUM_OF_TAPS__SHIFT 0x00000000 98786863660dSAlex Deucher #define SCL_TAP_CONTROL__SCL_H_NUM_OF_TAPS_MASK 0x00000f00L 98796863660dSAlex Deucher #define SCL_TAP_CONTROL__SCL_H_NUM_OF_TAPS__SHIFT 0x00000008 98806863660dSAlex Deucher 98816863660dSAlex Deucher // INT_MASK 98826863660dSAlex Deucher #define INT_MASK__VBLANK_INT_MASK 0x00000001L 98836863660dSAlex Deucher #define INT_MASK__VBLANK_INT__SHIFT 0x00000000 98846863660dSAlex Deucher #define INT_MASK__VLINE_INT_MASK 0x00000010L 98856863660dSAlex Deucher #define INT_MASK__VLINE_INT__SHIFT 0x00000004 98866863660dSAlex Deucher 98876863660dSAlex Deucher // PRIORITY_A_CNT 98886863660dSAlex Deucher #define PRIORITY_A_CNT__PRIORITY_MARK_A_MASK 0x00007fffL 98896863660dSAlex Deucher #define PRIORITY_A_CNT__PRIORITY_MARK_A__SHIFT 0x00000000 98906863660dSAlex Deucher #define PRIORITY_A_CNT__PRIORITY_A_OFF_MASK 0x00010000L 98916863660dSAlex Deucher #define PRIORITY_A_CNT__PRIORITY_A_OFF__SHIFT 0x00000010 98926863660dSAlex Deucher #define PRIORITY_A_CNT__PRIORITY_A_ALWAYS_ON_MASK 0x00100000L 98936863660dSAlex Deucher #define PRIORITY_A_CNT__PRIORITY_A_ALWAYS_ON__SHIFT 0x00000014 98946863660dSAlex Deucher #define PRIORITY_A_CNT__PRIORITY_A_FORCE_MASK_MASK 0x01000000L 98956863660dSAlex Deucher #define PRIORITY_A_CNT__PRIORITY_A_FORCE_MASK__SHIFT 0x00000018 98966863660dSAlex Deucher 98976863660dSAlex Deucher // PRIORITY_B_CNT 98986863660dSAlex Deucher #define PRIORITY_B_CNT__PRIORITY_MARK_B_MASK 0x00007fffL 98996863660dSAlex Deucher #define PRIORITY_B_CNT__PRIORITY_MARK_B__SHIFT 0x00000000 99006863660dSAlex Deucher #define PRIORITY_B_CNT__PRIORITY_B_OFF_MASK 0x00010000L 99016863660dSAlex Deucher #define PRIORITY_B_CNT__PRIORITY_B_OFF__SHIFT 0x00000010 99026863660dSAlex Deucher #define PRIORITY_B_CNT__PRIORITY_B_ALWAYS_ON_MASK 0x00100000L 99036863660dSAlex Deucher #define PRIORITY_B_CNT__PRIORITY_B_ALWAYS_ON__SHIFT 0x00000014 99046863660dSAlex Deucher #define PRIORITY_B_CNT__PRIORITY_B_FORCE_MASK_MASK 0x01000000L 99056863660dSAlex Deucher #define PRIORITY_B_CNT__PRIORITY_B_FORCE_MASK__SHIFT 0x00000018 99066863660dSAlex Deucher 99076863660dSAlex Deucher // VLINE_STATUS 99086863660dSAlex Deucher #define VLINE_STATUS__VLINE_OCCURRED_MASK 0x00000001L 99096863660dSAlex Deucher #define VLINE_STATUS__VLINE_OCCURRED__SHIFT 0x00000000 99106863660dSAlex Deucher #define VLINE_STATUS__VLINE_ACK_MASK 0x00000010L 99116863660dSAlex Deucher #define VLINE_STATUS__VLINE_ACK__SHIFT 0x00000004 99126863660dSAlex Deucher #define VLINE_STATUS__VLINE_STAT_MASK 0x00001000L 99136863660dSAlex Deucher #define VLINE_STATUS__VLINE_STAT__SHIFT 0x0000000c 99146863660dSAlex Deucher #define VLINE_STATUS__VLINE_INTERRUPT_MASK 0x00010000L 99156863660dSAlex Deucher #define VLINE_STATUS__VLINE_INTERRUPT__SHIFT 0x00000010 99166863660dSAlex Deucher #define VLINE_STATUS__VLINE_INTERRUPT_TYPE_MASK 0x00020000L 99176863660dSAlex Deucher #define VLINE_STATUS__VLINE_INTERRUPT_TYPE__SHIFT 0x00000011 99186863660dSAlex Deucher 99196863660dSAlex Deucher // VBLANK_STATUS 99206863660dSAlex Deucher #define VBLANK_STATUS__VBLANK_OCCURRED_MASK 0x00000001L 99216863660dSAlex Deucher #define VBLANK_STATUS__VBLANK_OCCURRED__SHIFT 0x00000000 99226863660dSAlex Deucher #define VBLANK_STATUS__VBLANK_ACK_MASK 0x00000010L 99236863660dSAlex Deucher #define VBLANK_STATUS__VBLANK_ACK__SHIFT 0x00000004 99246863660dSAlex Deucher #define VBLANK_STATUS__VBLANK_STAT_MASK 0x00001000L 99256863660dSAlex Deucher #define VBLANK_STATUS__VBLANK_STAT__SHIFT 0x0000000c 99266863660dSAlex Deucher #define VBLANK_STATUS__VBLANK_INTERRUPT_MASK 0x00010000L 99276863660dSAlex Deucher #define VBLANK_STATUS__VBLANK_INTERRUPT__SHIFT 0x00000010 99286863660dSAlex Deucher #define VBLANK_STATUS__VBLANK_INTERRUPT_TYPE_MASK 0x00020000L 99296863660dSAlex Deucher #define VBLANK_STATUS__VBLANK_INTERRUPT_TYPE__SHIFT 0x00000011 99306863660dSAlex Deucher 99316863660dSAlex Deucher // SCL_HORZ_FILTER_INIT_RGB_LUMA 99326863660dSAlex Deucher #define SCL_HORZ_FILTER_INIT_RGB_LUMA__SCL_H_INIT_FRAC_RGB_Y_MASK 0x0000ffffL 99336863660dSAlex Deucher #define SCL_HORZ_FILTER_INIT_RGB_LUMA__SCL_H_INIT_FRAC_RGB_Y__SHIFT 0x00000000 99346863660dSAlex Deucher #define SCL_HORZ_FILTER_INIT_RGB_LUMA__SCL_H_INIT_INT_RGB_Y_MASK 0x000f0000L 99356863660dSAlex Deucher #define SCL_HORZ_FILTER_INIT_RGB_LUMA__SCL_H_INIT_INT_RGB_Y__SHIFT 0x00000010 99366863660dSAlex Deucher 99376863660dSAlex Deucher // SCL_HORZ_FILTER_INIT_CHROMA 99386863660dSAlex Deucher #define SCL_HORZ_FILTER_INIT_CHROMA__SCL_H_INIT_FRAC_CBCR_MASK 0x0000ffffL 99396863660dSAlex Deucher #define SCL_HORZ_FILTER_INIT_CHROMA__SCL_H_INIT_FRAC_CBCR__SHIFT 0x00000000 99406863660dSAlex Deucher #define SCL_HORZ_FILTER_INIT_CHROMA__SCL_H_INIT_INT_CBCR_MASK 0x00070000L 99416863660dSAlex Deucher #define SCL_HORZ_FILTER_INIT_CHROMA__SCL_H_INIT_INT_CBCR__SHIFT 0x00000010 99426863660dSAlex Deucher 99436863660dSAlex Deucher 9944de2bdb3dSTom St Denis #endif 9945