1*a5b2c10cSHuang Rui /* 2*a5b2c10cSHuang Rui * Copyright (C) 2020 Advanced Micro Devices, Inc. 3*a5b2c10cSHuang Rui * 4*a5b2c10cSHuang Rui * Permission is hereby granted, free of charge, to any person obtaining a 5*a5b2c10cSHuang Rui * copy of this software and associated documentation files (the "Software"), 6*a5b2c10cSHuang Rui * to deal in the Software without restriction, including without limitation 7*a5b2c10cSHuang Rui * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8*a5b2c10cSHuang Rui * and/or sell copies of the Software, and to permit persons to whom the 9*a5b2c10cSHuang Rui * Software is furnished to do so, subject to the following conditions: 10*a5b2c10cSHuang Rui * 11*a5b2c10cSHuang Rui * The above copyright notice and this permission notice shall be included 12*a5b2c10cSHuang Rui * in all copies or substantial portions of the Software. 13*a5b2c10cSHuang Rui * 14*a5b2c10cSHuang Rui * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 15*a5b2c10cSHuang Rui * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16*a5b2c10cSHuang Rui * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17*a5b2c10cSHuang Rui * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN 18*a5b2c10cSHuang Rui * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 19*a5b2c10cSHuang Rui * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 20*a5b2c10cSHuang Rui */ 21*a5b2c10cSHuang Rui #ifndef _clk_11_5_0_SH_MASK_HEADER 22*a5b2c10cSHuang Rui #define _clk_11_5_0_SH_MASK_HEADER 23*a5b2c10cSHuang Rui 24*a5b2c10cSHuang Rui 25*a5b2c10cSHuang Rui // addressBlock: clk_clk1_0_SmuClkDec 26*a5b2c10cSHuang Rui //CLK1_0_CLK1_CLK_PLL_REQ 27*a5b2c10cSHuang Rui #define CLK1_0_CLK1_CLK_PLL_REQ__FbMult_int__SHIFT 0x0 28*a5b2c10cSHuang Rui #define CLK1_0_CLK1_CLK_PLL_REQ__FbMult_frac__SHIFT 0x10 29*a5b2c10cSHuang Rui #define CLK1_0_CLK1_CLK_PLL_REQ__FbMult_int_MASK 0x000001FFL 30*a5b2c10cSHuang Rui #define CLK1_0_CLK1_CLK_PLL_REQ__FbMult_frac_MASK 0xFFFF0000L 31*a5b2c10cSHuang Rui //CLK1_0_CLK1_CLK0_BYPASS_CNTL 32*a5b2c10cSHuang Rui #define CLK1_0_CLK1_CLK0_BYPASS_CNTL__CLK0_BYPASS_SEL__SHIFT 0x0 33*a5b2c10cSHuang Rui #define CLK1_0_CLK1_CLK0_BYPASS_CNTL__CLK0_BYPASS_DIV__SHIFT 0x10 34*a5b2c10cSHuang Rui #define CLK1_0_CLK1_CLK0_BYPASS_CNTL__CLK0_BYPASS_SEL_MASK 0x00000007L 35*a5b2c10cSHuang Rui #define CLK1_0_CLK1_CLK0_BYPASS_CNTL__CLK0_BYPASS_DIV_MASK 0x000F0000L 36*a5b2c10cSHuang Rui //CLK1_0_CLK1_CLK1_BYPASS_CNTL 37*a5b2c10cSHuang Rui #define CLK1_0_CLK1_CLK1_BYPASS_CNTL__CLK1_BYPASS_SEL__SHIFT 0x0 38*a5b2c10cSHuang Rui #define CLK1_0_CLK1_CLK1_BYPASS_CNTL__CLK1_BYPASS_DIV__SHIFT 0x10 39*a5b2c10cSHuang Rui #define CLK1_0_CLK1_CLK1_BYPASS_CNTL__CLK1_BYPASS_SEL_MASK 0x00000007L 40*a5b2c10cSHuang Rui #define CLK1_0_CLK1_CLK1_BYPASS_CNTL__CLK1_BYPASS_DIV_MASK 0x000F0000L 41*a5b2c10cSHuang Rui //CLK1_0_CLK1_CLK2_BYPASS_CNTL 42*a5b2c10cSHuang Rui #define CLK1_0_CLK1_CLK2_BYPASS_CNTL__CLK2_BYPASS_SEL__SHIFT 0x0 43*a5b2c10cSHuang Rui #define CLK1_0_CLK1_CLK2_BYPASS_CNTL__CLK2_BYPASS_DIV__SHIFT 0x10 44*a5b2c10cSHuang Rui #define CLK1_0_CLK1_CLK2_BYPASS_CNTL__CLK2_BYPASS_SEL_MASK 0x00000007L 45*a5b2c10cSHuang Rui #define CLK1_0_CLK1_CLK2_BYPASS_CNTL__CLK2_BYPASS_DIV_MASK 0x000F0000L 46*a5b2c10cSHuang Rui //CLK1_0_CLK1_CLK3_DS_CNTL 47*a5b2c10cSHuang Rui #define CLK1_0_CLK1_CLK3_DS_CNTL__CLK3_DS_DIV_ID__SHIFT 0x0 48*a5b2c10cSHuang Rui #define CLK1_0_CLK1_CLK3_DS_CNTL__CLK3_DS_DIV_ID_MASK 0x00000007L 49*a5b2c10cSHuang Rui //CLK1_0_CLK1_CLK3_ALLOW_DS 50*a5b2c10cSHuang Rui #define CLK1_0_CLK1_CLK3_ALLOW_DS__CLK3_ALLOW_DS__SHIFT 0x0 51*a5b2c10cSHuang Rui #define CLK1_0_CLK1_CLK3_ALLOW_DS__CLK3_ALLOW_DS_MASK 0x00000001L 52*a5b2c10cSHuang Rui //CLK1_0_CLK1_CLK3_BYPASS_CNTL 53*a5b2c10cSHuang Rui #define CLK1_0_CLK1_CLK3_BYPASS_CNTL__CLK3_BYPASS_SEL__SHIFT 0x0 54*a5b2c10cSHuang Rui #define CLK1_0_CLK1_CLK3_BYPASS_CNTL__CLK3_BYPASS_DIV__SHIFT 0x10 55*a5b2c10cSHuang Rui #define CLK1_0_CLK1_CLK3_BYPASS_CNTL__CLK3_BYPASS_SEL_MASK 0x00000007L 56*a5b2c10cSHuang Rui #define CLK1_0_CLK1_CLK3_BYPASS_CNTL__CLK3_BYPASS_DIV_MASK 0x000F0000L 57*a5b2c10cSHuang Rui //CLK1_0_CLK1_CLK0_CURRENT_CNT 58*a5b2c10cSHuang Rui #define CLK1_0_CLK1_CLK0_CURRENT_CNT__CURRENT_COUNT__SHIFT 0x0 59*a5b2c10cSHuang Rui #define CLK1_0_CLK1_CLK0_CURRENT_CNT__CURRENT_COUNT_MASK 0xFFFFFFFFL 60*a5b2c10cSHuang Rui //CLK1_0_CLK1_CLK1_CURRENT_CNT 61*a5b2c10cSHuang Rui #define CLK1_0_CLK1_CLK1_CURRENT_CNT__CURRENT_COUNT__SHIFT 0x0 62*a5b2c10cSHuang Rui #define CLK1_0_CLK1_CLK1_CURRENT_CNT__CURRENT_COUNT_MASK 0xFFFFFFFFL 63*a5b2c10cSHuang Rui //CLK1_0_CLK1_CLK2_CURRENT_CNT 64*a5b2c10cSHuang Rui #define CLK1_0_CLK1_CLK2_CURRENT_CNT__CURRENT_COUNT__SHIFT 0x0 65*a5b2c10cSHuang Rui #define CLK1_0_CLK1_CLK2_CURRENT_CNT__CURRENT_COUNT_MASK 0xFFFFFFFFL 66*a5b2c10cSHuang Rui //CLK1_0_CLK1_CLK3_CURRENT_CNT 67*a5b2c10cSHuang Rui #define CLK1_0_CLK1_CLK3_CURRENT_CNT__CURRENT_COUNT__SHIFT 0x0 68*a5b2c10cSHuang Rui #define CLK1_0_CLK1_CLK3_CURRENT_CNT__CURRENT_COUNT_MASK 0xFFFFFFFFL 69*a5b2c10cSHuang Rui 70*a5b2c10cSHuang Rui #endif 71