1 /* 2 * Copyright (C) 2020 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included 12 * in all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN 18 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 19 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 20 */ 21 #ifndef _clk_11_5_0_OFFSET_HEADER 22 #define _clk_11_5_0_OFFSET_HEADER 23 24 25 // addressBlock: clk_clk1_0_SmuClkDec 26 // base address: 0x5c000 27 #define mmCLK1_0_CLK1_CLK_PLL_REQ 0x0410 28 #define mmCLK1_0_CLK1_CLK_PLL_REQ_BASE_IDX 0 29 #define mmCLK1_0_CLK1_CLK0_BYPASS_CNTL 0x044a 30 #define mmCLK1_0_CLK1_CLK0_BYPASS_CNTL_BASE_IDX 0 31 #define mmCLK1_0_CLK1_CLK1_BYPASS_CNTL 0x0454 32 #define mmCLK1_0_CLK1_CLK1_BYPASS_CNTL_BASE_IDX 0 33 #define mmCLK1_0_CLK1_CLK2_BYPASS_CNTL 0x045e 34 #define mmCLK1_0_CLK1_CLK2_BYPASS_CNTL_BASE_IDX 0 35 #define mmCLK1_0_CLK1_CLK3_DS_CNTL 0x0461 36 #define mmCLK1_0_CLK1_CLK3_DS_CNTL_BASE_IDX 0 37 #define mmCLK1_0_CLK1_CLK3_ALLOW_DS 0x0462 38 #define mmCLK1_0_CLK1_CLK3_ALLOW_DS_BASE_IDX 0 39 #define mmCLK1_0_CLK1_CLK3_BYPASS_CNTL 0x0468 40 #define mmCLK1_0_CLK1_CLK3_BYPASS_CNTL_BASE_IDX 0 41 #define mmCLK1_0_CLK1_CLK0_CURRENT_CNT 0x04a7 42 #define mmCLK1_0_CLK1_CLK0_CURRENT_CNT_BASE_IDX 0 43 #define mmCLK1_0_CLK1_CLK1_CURRENT_CNT 0x04a8 44 #define mmCLK1_0_CLK1_CLK1_CURRENT_CNT_BASE_IDX 0 45 #define mmCLK1_0_CLK1_CLK2_CURRENT_CNT 0x04a9 46 #define mmCLK1_0_CLK1_CLK2_CURRENT_CNT_BASE_IDX 0 47 #define mmCLK1_0_CLK1_CLK3_CURRENT_CNT 0x04aa 48 #define mmCLK1_0_CLK1_CLK3_CURRENT_CNT_BASE_IDX 0 49 50 #endif 51