xref: /openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/clk/clk_10_0_2_sh_mask.h (revision b593bce5)

/*
 * Copyright (C) 2019  Advanced Micro Devices, Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included
 * in all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 */
#ifndef _clk_10_0_2_SH_MASK_HEADER
#define _clk_10_0_2_SH_MASK_HEADER


// addressBlock: clk_clk1_0_SmuClkDec
//CLK1_CLK_PLL_REQ
#define CLK1_CLK_PLL_REQ__FbMult_int__SHIFT                                                                   0x0
#define CLK1_CLK_PLL_REQ__PllSpineDiv__SHIFT                                                                  0xc
#define CLK1_CLK_PLL_REQ__FbMult_frac__SHIFT                                                                  0x10
#define CLK1_CLK_PLL_REQ__FbMult_int_MASK                                                                     0x000001FFL
#define CLK1_CLK_PLL_REQ__PllSpineDiv_MASK                                                                    0x0000F000L
#define CLK1_CLK_PLL_REQ__FbMult_frac_MASK                                                                    0xFFFF0000L
//CLK1_CLK0_BYPASS_CNTL
#define CLK1_CLK0_BYPASS_CNTL__CLK0_BYPASS_SEL__SHIFT                                                         0x0
#define CLK1_CLK0_BYPASS_CNTL__CLK0_BYPASS_DIV__SHIFT                                                         0x10
#define CLK1_CLK0_BYPASS_CNTL__CLK0_BYPASS_SEL_MASK                                                           0x00000007L
#define CLK1_CLK0_BYPASS_CNTL__CLK0_BYPASS_DIV_MASK                                                           0x000F0000L
//CLK1_CLK1_BYPASS_CNTL
#define CLK1_CLK1_BYPASS_CNTL__CLK1_BYPASS_SEL__SHIFT                                                         0x0
#define CLK1_CLK1_BYPASS_CNTL__CLK1_BYPASS_DIV__SHIFT                                                         0x10
#define CLK1_CLK1_BYPASS_CNTL__CLK1_BYPASS_SEL_MASK                                                           0x00000007L
#define CLK1_CLK1_BYPASS_CNTL__CLK1_BYPASS_DIV_MASK                                                           0x000F0000L
//CLK1_CLK2_BYPASS_CNTL
#define CLK1_CLK2_BYPASS_CNTL__CLK2_BYPASS_SEL__SHIFT                                                         0x0
#define CLK1_CLK2_BYPASS_CNTL__CLK2_BYPASS_DIV__SHIFT                                                         0x10
#define CLK1_CLK2_BYPASS_CNTL__CLK2_BYPASS_SEL_MASK                                                           0x00000007L
#define CLK1_CLK2_BYPASS_CNTL__CLK2_BYPASS_DIV_MASK                                                           0x000F0000L
//CLK1_CLK3_DS_CNTL
#define CLK1_CLK3_DS_CNTL__CLK3_DS_DIV_ID__SHIFT                                                              0x0
#define CLK1_CLK3_DS_CNTL__CLK3_DS_DIV_ID_MASK                                                                0x00000007L
//CLK1_CLK3_ALLOW_DS
#define CLK1_CLK3_ALLOW_DS__CLK3_ALLOW_DS__SHIFT                                                              0x0
#define CLK1_CLK3_ALLOW_DS__CLK3_ALLOW_DS_MASK                                                                0x00000001L
//CLK1_CLK3_BYPASS_CNTL
#define CLK1_CLK3_BYPASS_CNTL__CLK3_BYPASS_SEL__SHIFT                                                         0x0
#define CLK1_CLK3_BYPASS_CNTL__CLK3_BYPASS_DIV__SHIFT                                                         0x10
#define CLK1_CLK3_BYPASS_CNTL__CLK3_BYPASS_SEL_MASK                                                           0x00000007L
#define CLK1_CLK3_BYPASS_CNTL__CLK3_BYPASS_DIV_MASK                                                           0x000F0000L
//CLK1_CLK0_CURRENT_CNT
#define CLK1_CLK0_CURRENT_CNT__CURRENT_COUNT__SHIFT                                                           0x0
#define CLK1_CLK0_CURRENT_CNT__CURRENT_COUNT_MASK                                                             0xFFFFFFFFL
//CLK1_CLK1_CURRENT_CNT
#define CLK1_CLK1_CURRENT_CNT__CURRENT_COUNT__SHIFT                                                           0x0
#define CLK1_CLK1_CURRENT_CNT__CURRENT_COUNT_MASK                                                             0xFFFFFFFFL
//CLK1_CLK2_CURRENT_CNT
#define CLK1_CLK2_CURRENT_CNT__CURRENT_COUNT__SHIFT                                                           0x0
#define CLK1_CLK2_CURRENT_CNT__CURRENT_COUNT_MASK                                                             0xFFFFFFFFL
//CLK1_CLK3_CURRENT_CNT
#define CLK1_CLK3_CURRENT_CNT__CURRENT_COUNT__SHIFT                                                           0x0
#define CLK1_CLK3_CURRENT_CNT__CURRENT_COUNT_MASK                                                             0xFFFFFFFFL


#endif