13e5343bdSAlex Deucher /* 23e5343bdSAlex Deucher * BIF_5_1 Register documentation 33e5343bdSAlex Deucher * 43e5343bdSAlex Deucher * Copyright (C) 2014 Advanced Micro Devices, Inc. 53e5343bdSAlex Deucher * 63e5343bdSAlex Deucher * Permission is hereby granted, free of charge, to any person obtaining a 73e5343bdSAlex Deucher * copy of this software and associated documentation files (the "Software"), 83e5343bdSAlex Deucher * to deal in the Software without restriction, including without limitation 93e5343bdSAlex Deucher * the rights to use, copy, modify, merge, publish, distribute, sublicense, 103e5343bdSAlex Deucher * and/or sell copies of the Software, and to permit persons to whom the 113e5343bdSAlex Deucher * Software is furnished to do so, subject to the following conditions: 123e5343bdSAlex Deucher * 133e5343bdSAlex Deucher * The above copyright notice and this permission notice shall be included 143e5343bdSAlex Deucher * in all copies or substantial portions of the Software. 153e5343bdSAlex Deucher * 163e5343bdSAlex Deucher * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 173e5343bdSAlex Deucher * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 183e5343bdSAlex Deucher * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 193e5343bdSAlex Deucher * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN 203e5343bdSAlex Deucher * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 213e5343bdSAlex Deucher * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 223e5343bdSAlex Deucher */ 233e5343bdSAlex Deucher 243e5343bdSAlex Deucher #ifndef BIF_5_1_D_H 253e5343bdSAlex Deucher #define BIF_5_1_D_H 263e5343bdSAlex Deucher 273e5343bdSAlex Deucher #define mmMM_INDEX 0x0 283e5343bdSAlex Deucher #define mmMM_INDEX_HI 0x6 293e5343bdSAlex Deucher #define mmMM_DATA 0x1 303e5343bdSAlex Deucher #define mmBIF_MM_INDACCESS_CNTL 0x1500 313e5343bdSAlex Deucher #define mmBUS_CNTL 0x1508 323e5343bdSAlex Deucher #define mmCONFIG_CNTL 0x1509 333e5343bdSAlex Deucher #define mmCONFIG_MEMSIZE 0x150a 343e5343bdSAlex Deucher #define mmCONFIG_F0_BASE 0x150b 353e5343bdSAlex Deucher #define mmCONFIG_APER_SIZE 0x150c 363e5343bdSAlex Deucher #define mmCONFIG_REG_APER_SIZE 0x150d 373e5343bdSAlex Deucher #define mmBIF_SCRATCH0 0x150e 383e5343bdSAlex Deucher #define mmBIF_SCRATCH1 0x150f 393e5343bdSAlex Deucher #define mmBX_RESET_EN 0x1514 403e5343bdSAlex Deucher #define mmMM_CFGREGS_CNTL 0x1513 413e5343bdSAlex Deucher #define mmHW_DEBUG 0x1515 423e5343bdSAlex Deucher #define mmMASTER_CREDIT_CNTL 0x1516 433e5343bdSAlex Deucher #define mmSLAVE_REQ_CREDIT_CNTL 0x1517 443e5343bdSAlex Deucher #define mmBX_RESET_CNTL 0x1518 453e5343bdSAlex Deucher #define mmINTERRUPT_CNTL 0x151a 463e5343bdSAlex Deucher #define mmINTERRUPT_CNTL2 0x151b 473e5343bdSAlex Deucher #define mmBIF_DEBUG_CNTL 0x151c 483e5343bdSAlex Deucher #define mmBIF_DEBUG_MUX 0x151d 493e5343bdSAlex Deucher #define mmBIF_DEBUG_OUT 0x151e 503e5343bdSAlex Deucher #define mmHDP_REG_COHERENCY_FLUSH_CNTL 0x1528 513e5343bdSAlex Deucher #define mmHDP_MEM_COHERENCY_FLUSH_CNTL 0x1520 523e5343bdSAlex Deucher #define mmCLKREQB_PAD_CNTL 0x1521 533e5343bdSAlex Deucher #define mmSMBDAT_PAD_CNTL 0x1522 543e5343bdSAlex Deucher #define mmSMBCLK_PAD_CNTL 0x1523 553e5343bdSAlex Deucher #define mmBIF_XDMA_LO 0x14c0 563e5343bdSAlex Deucher #define mmBIF_XDMA_HI 0x14c1 573e5343bdSAlex Deucher #define mmBIF_FEATURES_CONTROL_MISC 0x14c2 583e5343bdSAlex Deucher #define mmBIF_DOORBELL_CNTL 0x14c3 593e5343bdSAlex Deucher #define mmBIF_SLVARB_MODE 0x14c4 603e5343bdSAlex Deucher #define mmBIF_FB_EN 0x1524 613e5343bdSAlex Deucher #define mmBIF_BUSNUM_CNTL1 0x1525 623e5343bdSAlex Deucher #define mmBIF_BUSNUM_LIST0 0x1526 633e5343bdSAlex Deucher #define mmBIF_BUSNUM_LIST1 0x1527 643e5343bdSAlex Deucher #define mmBIF_BUSNUM_CNTL2 0x152b 653e5343bdSAlex Deucher #define mmBIF_BUSY_DELAY_CNTR 0x1529 663e5343bdSAlex Deucher #define mmBIF_PERFMON_CNTL 0x152c 673e5343bdSAlex Deucher #define mmBIF_PERFCOUNTER0_RESULT 0x152d 683e5343bdSAlex Deucher #define mmBIF_PERFCOUNTER1_RESULT 0x152e 693e5343bdSAlex Deucher #define mmSLAVE_HANG_PROTECTION_CNTL 0x1536 703e5343bdSAlex Deucher #define mmGPU_HDP_FLUSH_REQ 0x1537 713e5343bdSAlex Deucher #define mmGPU_HDP_FLUSH_DONE 0x1538 723e5343bdSAlex Deucher #define mmSLAVE_HANG_ERROR 0x153b 733e5343bdSAlex Deucher #define mmCAPTURE_HOST_BUSNUM 0x153c 743e5343bdSAlex Deucher #define mmHOST_BUSNUM 0x153d 753e5343bdSAlex Deucher #define mmPEER_REG_RANGE0 0x153e 763e5343bdSAlex Deucher #define mmPEER_REG_RANGE1 0x153f 773e5343bdSAlex Deucher #define mmPEER0_FB_OFFSET_HI 0x14f3 783e5343bdSAlex Deucher #define mmPEER0_FB_OFFSET_LO 0x14f2 793e5343bdSAlex Deucher #define mmPEER1_FB_OFFSET_HI 0x14f1 803e5343bdSAlex Deucher #define mmPEER1_FB_OFFSET_LO 0x14f0 813e5343bdSAlex Deucher #define mmPEER2_FB_OFFSET_HI 0x14ef 823e5343bdSAlex Deucher #define mmPEER2_FB_OFFSET_LO 0x14ee 833e5343bdSAlex Deucher #define mmPEER3_FB_OFFSET_HI 0x14ed 843e5343bdSAlex Deucher #define mmPEER3_FB_OFFSET_LO 0x14ec 853e5343bdSAlex Deucher #define mmDBG_BYPASS_SRBM_ACCESS 0x14eb 863e5343bdSAlex Deucher #define mmSMBUS_BACO_DUMMY 0x14c6 873e5343bdSAlex Deucher #define mmBIF_DEVFUNCNUM_LIST0 0x14e8 883e5343bdSAlex Deucher #define mmBIF_DEVFUNCNUM_LIST1 0x14e7 893e5343bdSAlex Deucher #define mmBACO_CNTL 0x14e5 903e5343bdSAlex Deucher #define mmBF_ANA_ISO_CNTL 0x14c7 913e5343bdSAlex Deucher #define mmMEM_TYPE_CNTL 0x14e4 923e5343bdSAlex Deucher #define mmBIF_BACO_DEBUG 0x14df 933e5343bdSAlex Deucher #define mmBIF_BACO_DEBUG_LATCH 0x14dc 943e5343bdSAlex Deucher #define mmBACO_CNTL_MISC 0x14db 953e5343bdSAlex Deucher #define mmSMU_BIF_VDDGFX_PWR_STATUS 0x14f8 963e5343bdSAlex Deucher #define mmBIF_VDDGFX_GFX0_LOWER 0x1428 973e5343bdSAlex Deucher #define mmBIF_VDDGFX_GFX0_UPPER 0x1429 983e5343bdSAlex Deucher #define mmBIF_VDDGFX_GFX1_LOWER 0x142a 993e5343bdSAlex Deucher #define mmBIF_VDDGFX_GFX1_UPPER 0x142b 1003e5343bdSAlex Deucher #define mmBIF_VDDGFX_GFX2_LOWER 0x142c 1013e5343bdSAlex Deucher #define mmBIF_VDDGFX_GFX2_UPPER 0x142d 1023e5343bdSAlex Deucher #define mmBIF_VDDGFX_GFX3_LOWER 0x142e 1033e5343bdSAlex Deucher #define mmBIF_VDDGFX_GFX3_UPPER 0x142f 1043e5343bdSAlex Deucher #define mmBIF_VDDGFX_GFX4_LOWER 0x1430 1053e5343bdSAlex Deucher #define mmBIF_VDDGFX_GFX4_UPPER 0x1431 1063e5343bdSAlex Deucher #define mmBIF_VDDGFX_GFX5_LOWER 0x1432 1073e5343bdSAlex Deucher #define mmBIF_VDDGFX_GFX5_UPPER 0x1433 1083e5343bdSAlex Deucher #define mmBIF_VDDGFX_RSV1_LOWER 0x1434 1093e5343bdSAlex Deucher #define mmBIF_VDDGFX_RSV1_UPPER 0x1435 1103e5343bdSAlex Deucher #define mmBIF_VDDGFX_RSV2_LOWER 0x1436 1113e5343bdSAlex Deucher #define mmBIF_VDDGFX_RSV2_UPPER 0x1437 1123e5343bdSAlex Deucher #define mmBIF_VDDGFX_RSV3_LOWER 0x1438 1133e5343bdSAlex Deucher #define mmBIF_VDDGFX_RSV3_UPPER 0x1439 1143e5343bdSAlex Deucher #define mmBIF_VDDGFX_RSV4_LOWER 0x143a 1153e5343bdSAlex Deucher #define mmBIF_VDDGFX_RSV4_UPPER 0x143b 1163e5343bdSAlex Deucher #define mmBIF_VDDGFX_FB_CMP 0x143c 1173e5343bdSAlex Deucher #define mmBIF_DOORBELL_GBLAPER1_LOWER 0x14fc 1183e5343bdSAlex Deucher #define mmBIF_DOORBELL_GBLAPER1_UPPER 0x14fd 1193e5343bdSAlex Deucher #define mmBIF_DOORBELL_GBLAPER2_LOWER 0x14fe 1203e5343bdSAlex Deucher #define mmBIF_DOORBELL_GBLAPER2_UPPER 0x14ff 1213e5343bdSAlex Deucher #define mmBIF_SMU_INDEX 0x143d 1223e5343bdSAlex Deucher #define mmBIF_SMU_DATA 0x143e 1233e5343bdSAlex Deucher #define mmIMPCTL_RESET 0x14f5 1243e5343bdSAlex Deucher #define mmGARLIC_FLUSH_CNTL 0x1401 1253e5343bdSAlex Deucher #define mmGARLIC_FLUSH_ADDR_START_0 0x1402 1263e5343bdSAlex Deucher #define mmGARLIC_FLUSH_ADDR_START_1 0x1404 1273e5343bdSAlex Deucher #define mmGARLIC_FLUSH_ADDR_START_2 0x1406 1283e5343bdSAlex Deucher #define mmGARLIC_FLUSH_ADDR_START_3 0x1408 1293e5343bdSAlex Deucher #define mmGARLIC_FLUSH_ADDR_START_4 0x140a 1303e5343bdSAlex Deucher #define mmGARLIC_FLUSH_ADDR_START_5 0x140c 1313e5343bdSAlex Deucher #define mmGARLIC_FLUSH_ADDR_START_6 0x140e 1323e5343bdSAlex Deucher #define mmGARLIC_FLUSH_ADDR_START_7 0x1410 1333e5343bdSAlex Deucher #define mmGARLIC_FLUSH_ADDR_END_0 0x1403 1343e5343bdSAlex Deucher #define mmGARLIC_FLUSH_ADDR_END_1 0x1405 1353e5343bdSAlex Deucher #define mmGARLIC_FLUSH_ADDR_END_2 0x1407 1363e5343bdSAlex Deucher #define mmGARLIC_FLUSH_ADDR_END_3 0x1409 1373e5343bdSAlex Deucher #define mmGARLIC_FLUSH_ADDR_END_4 0x140b 1383e5343bdSAlex Deucher #define mmGARLIC_FLUSH_ADDR_END_5 0x140d 1393e5343bdSAlex Deucher #define mmGARLIC_FLUSH_ADDR_END_6 0x140f 1403e5343bdSAlex Deucher #define mmGARLIC_FLUSH_ADDR_END_7 0x1411 1413e5343bdSAlex Deucher #define mmGARLIC_FLUSH_REQ 0x1412 1423e5343bdSAlex Deucher #define mmGPU_GARLIC_FLUSH_REQ 0x1413 1433e5343bdSAlex Deucher #define mmGPU_GARLIC_FLUSH_DONE 0x1414 1443e5343bdSAlex Deucher #define mmGARLIC_COHE_CP_RB0_WPTR 0x1415 1453e5343bdSAlex Deucher #define mmGARLIC_COHE_CP_RB1_WPTR 0x1416 1463e5343bdSAlex Deucher #define mmGARLIC_COHE_CP_RB2_WPTR 0x1417 1473e5343bdSAlex Deucher #define mmGARLIC_COHE_UVD_RBC_RB_WPTR 0x1418 1483e5343bdSAlex Deucher #define mmGARLIC_COHE_SDMA0_GFX_RB_WPTR 0x1419 1493e5343bdSAlex Deucher #define mmGARLIC_COHE_SDMA1_GFX_RB_WPTR 0x141a 1503e5343bdSAlex Deucher #define mmGARLIC_COHE_CP_DMA_ME_COMMAND 0x141b 1513e5343bdSAlex Deucher #define mmGARLIC_COHE_CP_DMA_PFP_COMMAND 0x141c 1523e5343bdSAlex Deucher #define mmGARLIC_COHE_SAM_SAB_RBI_WPTR 0x141d 1533e5343bdSAlex Deucher #define mmGARLIC_COHE_SAM_SAB_RBO_WPTR 0x141e 1543e5343bdSAlex Deucher #define mmGARLIC_COHE_VCE_OUT_RB_WPTR 0x141f 1553e5343bdSAlex Deucher #define mmGARLIC_COHE_VCE_RB_WPTR2 0x1420 1563e5343bdSAlex Deucher #define mmGARLIC_COHE_VCE_RB_WPTR 0x1421 1573e5343bdSAlex Deucher #define mmGARLIC_COHE_SDMA2_GFX_RB_WPTR 0x1422 1583e5343bdSAlex Deucher #define mmGARLIC_COHE_SDMA3_GFX_RB_WPTR 0x1423 1593e5343bdSAlex Deucher #define mmGARLIC_COHE_CP_DMA_PIO_COMMAND 0x1424 1603e5343bdSAlex Deucher #define mmGARLIC_COHE_GARLIC_FLUSH_REQ 0x1425 1613e5343bdSAlex Deucher #define mmREMAP_HDP_MEM_FLUSH_CNTL 0x1426 1623e5343bdSAlex Deucher #define mmREMAP_HDP_REG_FLUSH_CNTL 0x1427 1633e5343bdSAlex Deucher #define mmBIOS_SCRATCH_0 0x5c9 1643e5343bdSAlex Deucher #define mmBIOS_SCRATCH_1 0x5ca 1653e5343bdSAlex Deucher #define mmBIOS_SCRATCH_2 0x5cb 1663e5343bdSAlex Deucher #define mmBIOS_SCRATCH_3 0x5cc 1673e5343bdSAlex Deucher #define mmBIOS_SCRATCH_4 0x5cd 1683e5343bdSAlex Deucher #define mmBIOS_SCRATCH_5 0x5ce 1693e5343bdSAlex Deucher #define mmBIOS_SCRATCH_6 0x5cf 1703e5343bdSAlex Deucher #define mmBIOS_SCRATCH_7 0x5d0 1713e5343bdSAlex Deucher #define mmBIOS_SCRATCH_8 0x5d1 1723e5343bdSAlex Deucher #define mmBIOS_SCRATCH_9 0x5d2 1733e5343bdSAlex Deucher #define mmBIOS_SCRATCH_10 0x5d3 1743e5343bdSAlex Deucher #define mmBIOS_SCRATCH_11 0x5d4 1753e5343bdSAlex Deucher #define mmBIOS_SCRATCH_12 0x5d5 1763e5343bdSAlex Deucher #define mmBIOS_SCRATCH_13 0x5d6 1773e5343bdSAlex Deucher #define mmBIOS_SCRATCH_14 0x5d7 1783e5343bdSAlex Deucher #define mmBIOS_SCRATCH_15 0x5d8 1793e5343bdSAlex Deucher #define mmBIF_RB_CNTL 0x1530 1803e5343bdSAlex Deucher #define mmBIF_RB_BASE 0x1531 1813e5343bdSAlex Deucher #define mmBIF_RB_RPTR 0x1532 1823e5343bdSAlex Deucher #define mmBIF_RB_WPTR 0x1533 1833e5343bdSAlex Deucher #define mmBIF_RB_WPTR_ADDR_HI 0x1534 1843e5343bdSAlex Deucher #define mmBIF_RB_WPTR_ADDR_LO 0x1535 1853e5343bdSAlex Deucher #define mmVENDOR_ID 0x0 1863e5343bdSAlex Deucher #define mmDEVICE_ID 0x0 1873e5343bdSAlex Deucher #define mmCOMMAND 0x1 1883e5343bdSAlex Deucher #define mmSTATUS 0x1 1893e5343bdSAlex Deucher #define mmREVISION_ID 0x2 1903e5343bdSAlex Deucher #define mmPROG_INTERFACE 0x2 1913e5343bdSAlex Deucher #define mmSUB_CLASS 0x2 1923e5343bdSAlex Deucher #define mmBASE_CLASS 0x2 1933e5343bdSAlex Deucher #define mmCACHE_LINE 0x3 1943e5343bdSAlex Deucher #define mmLATENCY 0x3 1953e5343bdSAlex Deucher #define mmHEADER 0x3 1963e5343bdSAlex Deucher #define mmBIST 0x3 1973e5343bdSAlex Deucher #define mmBASE_ADDR_1 0x4 1983e5343bdSAlex Deucher #define mmBASE_ADDR_2 0x5 1993e5343bdSAlex Deucher #define mmBASE_ADDR_3 0x6 2003e5343bdSAlex Deucher #define mmBASE_ADDR_4 0x7 2013e5343bdSAlex Deucher #define mmBASE_ADDR_5 0x8 2023e5343bdSAlex Deucher #define mmBASE_ADDR_6 0x9 2033e5343bdSAlex Deucher #define mmROM_BASE_ADDR 0xc 2043e5343bdSAlex Deucher #define mmCAP_PTR 0xd 2053e5343bdSAlex Deucher #define mmINTERRUPT_LINE 0xf 2063e5343bdSAlex Deucher #define mmINTERRUPT_PIN 0xf 2073e5343bdSAlex Deucher #define mmADAPTER_ID 0xb 2083e5343bdSAlex Deucher #define mmMIN_GRANT 0xf 2093e5343bdSAlex Deucher #define mmMAX_LATENCY 0xf 2103e5343bdSAlex Deucher #define mmVENDOR_CAP_LIST 0x12 2113e5343bdSAlex Deucher #define mmADAPTER_ID_W 0x13 2123e5343bdSAlex Deucher #define mmPMI_CAP_LIST 0x14 2133e5343bdSAlex Deucher #define mmPMI_CAP 0x14 2143e5343bdSAlex Deucher #define mmPMI_STATUS_CNTL 0x15 2153e5343bdSAlex Deucher #define mmPCIE_CAP_LIST 0x16 2163e5343bdSAlex Deucher #define mmPCIE_CAP 0x16 2173e5343bdSAlex Deucher #define mmDEVICE_CAP 0x17 2183e5343bdSAlex Deucher #define mmDEVICE_CNTL 0x18 2193e5343bdSAlex Deucher #define mmDEVICE_STATUS 0x18 2203e5343bdSAlex Deucher #define mmLINK_CAP 0x19 2213e5343bdSAlex Deucher #define mmLINK_CNTL 0x1a 2223e5343bdSAlex Deucher #define mmLINK_STATUS 0x1a 2233e5343bdSAlex Deucher #define mmDEVICE_CAP2 0x1f 2243e5343bdSAlex Deucher #define mmDEVICE_CNTL2 0x20 2253e5343bdSAlex Deucher #define mmDEVICE_STATUS2 0x20 2263e5343bdSAlex Deucher #define mmLINK_CAP2 0x21 2273e5343bdSAlex Deucher #define mmLINK_CNTL2 0x22 2283e5343bdSAlex Deucher #define mmLINK_STATUS2 0x22 2293e5343bdSAlex Deucher #define mmMSI_CAP_LIST 0x28 2303e5343bdSAlex Deucher #define mmMSI_MSG_CNTL 0x28 2313e5343bdSAlex Deucher #define mmMSI_MSG_ADDR_LO 0x29 2323e5343bdSAlex Deucher #define mmMSI_MSG_ADDR_HI 0x2a 2333e5343bdSAlex Deucher #define mmMSI_MSG_DATA_64 0x2b 2343e5343bdSAlex Deucher #define mmMSI_MSG_DATA 0x2a 2353e5343bdSAlex Deucher #define mmPCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x40 2363e5343bdSAlex Deucher #define mmPCIE_VENDOR_SPECIFIC_HDR 0x41 2373e5343bdSAlex Deucher #define mmPCIE_VENDOR_SPECIFIC1 0x42 2383e5343bdSAlex Deucher #define mmPCIE_VENDOR_SPECIFIC2 0x43 2393e5343bdSAlex Deucher #define mmPCIE_VC_ENH_CAP_LIST 0x44 2403e5343bdSAlex Deucher #define mmPCIE_PORT_VC_CAP_REG1 0x45 2413e5343bdSAlex Deucher #define mmPCIE_PORT_VC_CAP_REG2 0x46 2423e5343bdSAlex Deucher #define mmPCIE_PORT_VC_CNTL 0x47 2433e5343bdSAlex Deucher #define mmPCIE_PORT_VC_STATUS 0x47 2443e5343bdSAlex Deucher #define mmPCIE_VC0_RESOURCE_CAP 0x48 2453e5343bdSAlex Deucher #define mmPCIE_VC0_RESOURCE_CNTL 0x49 2463e5343bdSAlex Deucher #define mmPCIE_VC0_RESOURCE_STATUS 0x4a 2473e5343bdSAlex Deucher #define mmPCIE_VC1_RESOURCE_CAP 0x4b 2483e5343bdSAlex Deucher #define mmPCIE_VC1_RESOURCE_CNTL 0x4c 2493e5343bdSAlex Deucher #define mmPCIE_VC1_RESOURCE_STATUS 0x4d 2503e5343bdSAlex Deucher #define mmPCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 0x50 2513e5343bdSAlex Deucher #define mmPCIE_DEV_SERIAL_NUM_DW1 0x51 2523e5343bdSAlex Deucher #define mmPCIE_DEV_SERIAL_NUM_DW2 0x52 2533e5343bdSAlex Deucher #define mmPCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x54 2543e5343bdSAlex Deucher #define mmPCIE_UNCORR_ERR_STATUS 0x55 2553e5343bdSAlex Deucher #define mmPCIE_UNCORR_ERR_MASK 0x56 2563e5343bdSAlex Deucher #define mmPCIE_UNCORR_ERR_SEVERITY 0x57 2573e5343bdSAlex Deucher #define mmPCIE_CORR_ERR_STATUS 0x58 2583e5343bdSAlex Deucher #define mmPCIE_CORR_ERR_MASK 0x59 2593e5343bdSAlex Deucher #define mmPCIE_ADV_ERR_CAP_CNTL 0x5a 2603e5343bdSAlex Deucher #define mmPCIE_HDR_LOG0 0x5b 2613e5343bdSAlex Deucher #define mmPCIE_HDR_LOG1 0x5c 2623e5343bdSAlex Deucher #define mmPCIE_HDR_LOG2 0x5d 2633e5343bdSAlex Deucher #define mmPCIE_HDR_LOG3 0x5e 2643e5343bdSAlex Deucher #define mmPCIE_TLP_PREFIX_LOG0 0x62 2653e5343bdSAlex Deucher #define mmPCIE_TLP_PREFIX_LOG1 0x63 2663e5343bdSAlex Deucher #define mmPCIE_TLP_PREFIX_LOG2 0x64 2673e5343bdSAlex Deucher #define mmPCIE_TLP_PREFIX_LOG3 0x65 2683e5343bdSAlex Deucher #define mmPCIE_BAR_ENH_CAP_LIST 0x80 2693e5343bdSAlex Deucher #define mmPCIE_BAR1_CAP 0x81 2703e5343bdSAlex Deucher #define mmPCIE_BAR1_CNTL 0x82 2713e5343bdSAlex Deucher #define mmPCIE_BAR2_CAP 0x83 2723e5343bdSAlex Deucher #define mmPCIE_BAR2_CNTL 0x84 2733e5343bdSAlex Deucher #define mmPCIE_BAR3_CAP 0x85 2743e5343bdSAlex Deucher #define mmPCIE_BAR3_CNTL 0x86 2753e5343bdSAlex Deucher #define mmPCIE_BAR4_CAP 0x87 2763e5343bdSAlex Deucher #define mmPCIE_BAR4_CNTL 0x88 2773e5343bdSAlex Deucher #define mmPCIE_BAR5_CAP 0x89 2783e5343bdSAlex Deucher #define mmPCIE_BAR5_CNTL 0x8a 2793e5343bdSAlex Deucher #define mmPCIE_BAR6_CAP 0x8b 2803e5343bdSAlex Deucher #define mmPCIE_BAR6_CNTL 0x8c 2813e5343bdSAlex Deucher #define mmPCIE_PWR_BUDGET_ENH_CAP_LIST 0x90 2823e5343bdSAlex Deucher #define mmPCIE_PWR_BUDGET_DATA_SELECT 0x91 2833e5343bdSAlex Deucher #define mmPCIE_PWR_BUDGET_DATA 0x92 2843e5343bdSAlex Deucher #define mmPCIE_PWR_BUDGET_CAP 0x93 2853e5343bdSAlex Deucher #define mmPCIE_DPA_ENH_CAP_LIST 0x94 2863e5343bdSAlex Deucher #define mmPCIE_DPA_CAP 0x95 2873e5343bdSAlex Deucher #define mmPCIE_DPA_LATENCY_INDICATOR 0x96 2883e5343bdSAlex Deucher #define mmPCIE_DPA_STATUS 0x97 2893e5343bdSAlex Deucher #define mmPCIE_DPA_CNTL 0x97 2903e5343bdSAlex Deucher #define mmPCIE_DPA_SUBSTATE_PWR_ALLOC_0 0x98 2913e5343bdSAlex Deucher #define mmPCIE_DPA_SUBSTATE_PWR_ALLOC_1 0x98 2923e5343bdSAlex Deucher #define mmPCIE_DPA_SUBSTATE_PWR_ALLOC_2 0x98 2933e5343bdSAlex Deucher #define mmPCIE_DPA_SUBSTATE_PWR_ALLOC_3 0x98 2943e5343bdSAlex Deucher #define mmPCIE_DPA_SUBSTATE_PWR_ALLOC_4 0x99 2953e5343bdSAlex Deucher #define mmPCIE_DPA_SUBSTATE_PWR_ALLOC_5 0x99 2963e5343bdSAlex Deucher #define mmPCIE_DPA_SUBSTATE_PWR_ALLOC_6 0x99 2973e5343bdSAlex Deucher #define mmPCIE_DPA_SUBSTATE_PWR_ALLOC_7 0x99 2983e5343bdSAlex Deucher #define mmPCIE_SECONDARY_ENH_CAP_LIST 0x9c 2993e5343bdSAlex Deucher #define mmPCIE_LINK_CNTL3 0x9d 3003e5343bdSAlex Deucher #define mmPCIE_LANE_ERROR_STATUS 0x9e 3013e5343bdSAlex Deucher #define mmPCIE_LANE_0_EQUALIZATION_CNTL 0x9f 3023e5343bdSAlex Deucher #define mmPCIE_LANE_1_EQUALIZATION_CNTL 0x9f 3033e5343bdSAlex Deucher #define mmPCIE_LANE_2_EQUALIZATION_CNTL 0xa0 3043e5343bdSAlex Deucher #define mmPCIE_LANE_3_EQUALIZATION_CNTL 0xa0 3053e5343bdSAlex Deucher #define mmPCIE_LANE_4_EQUALIZATION_CNTL 0xa1 3063e5343bdSAlex Deucher #define mmPCIE_LANE_5_EQUALIZATION_CNTL 0xa1 3073e5343bdSAlex Deucher #define mmPCIE_LANE_6_EQUALIZATION_CNTL 0xa2 3083e5343bdSAlex Deucher #define mmPCIE_LANE_7_EQUALIZATION_CNTL 0xa2 3093e5343bdSAlex Deucher #define mmPCIE_LANE_8_EQUALIZATION_CNTL 0xa3 3103e5343bdSAlex Deucher #define mmPCIE_LANE_9_EQUALIZATION_CNTL 0xa3 3113e5343bdSAlex Deucher #define mmPCIE_LANE_10_EQUALIZATION_CNTL 0xa4 3123e5343bdSAlex Deucher #define mmPCIE_LANE_11_EQUALIZATION_CNTL 0xa4 3133e5343bdSAlex Deucher #define mmPCIE_LANE_12_EQUALIZATION_CNTL 0xa5 3143e5343bdSAlex Deucher #define mmPCIE_LANE_13_EQUALIZATION_CNTL 0xa5 3153e5343bdSAlex Deucher #define mmPCIE_LANE_14_EQUALIZATION_CNTL 0xa6 3163e5343bdSAlex Deucher #define mmPCIE_LANE_15_EQUALIZATION_CNTL 0xa6 3173e5343bdSAlex Deucher #define mmPCIE_ACS_ENH_CAP_LIST 0xa8 3183e5343bdSAlex Deucher #define mmPCIE_ACS_CAP 0xa9 3193e5343bdSAlex Deucher #define mmPCIE_ACS_CNTL 0xa9 3203e5343bdSAlex Deucher #define mmPCIE_ATS_ENH_CAP_LIST 0xac 3213e5343bdSAlex Deucher #define mmPCIE_ATS_CAP 0xad 3223e5343bdSAlex Deucher #define mmPCIE_ATS_CNTL 0xad 3233e5343bdSAlex Deucher #define mmPCIE_PAGE_REQ_ENH_CAP_LIST 0xb0 3243e5343bdSAlex Deucher #define mmPCIE_PAGE_REQ_CNTL 0xb1 3253e5343bdSAlex Deucher #define mmPCIE_PAGE_REQ_STATUS 0xb1 3263e5343bdSAlex Deucher #define mmPCIE_OUTSTAND_PAGE_REQ_CAPACITY 0xb2 3273e5343bdSAlex Deucher #define mmPCIE_OUTSTAND_PAGE_REQ_ALLOC 0xb3 3283e5343bdSAlex Deucher #define mmPCIE_PASID_ENH_CAP_LIST 0xb4 3293e5343bdSAlex Deucher #define mmPCIE_PASID_CAP 0xb5 3303e5343bdSAlex Deucher #define mmPCIE_PASID_CNTL 0xb5 3313e5343bdSAlex Deucher #define mmPCIE_TPH_REQR_ENH_CAP_LIST 0xb8 3323e5343bdSAlex Deucher #define mmPCIE_TPH_REQR_CAP 0xb9 3333e5343bdSAlex Deucher #define mmPCIE_TPH_REQR_CNTL 0xba 3343e5343bdSAlex Deucher #define mmPCIE_MC_ENH_CAP_LIST 0xbc 3353e5343bdSAlex Deucher #define mmPCIE_MC_CAP 0xbd 3363e5343bdSAlex Deucher #define mmPCIE_MC_CNTL 0xbd 3373e5343bdSAlex Deucher #define mmPCIE_MC_ADDR0 0xbe 3383e5343bdSAlex Deucher #define mmPCIE_MC_ADDR1 0xbf 3393e5343bdSAlex Deucher #define mmPCIE_MC_RCV0 0xc0 3403e5343bdSAlex Deucher #define mmPCIE_MC_RCV1 0xc1 3413e5343bdSAlex Deucher #define mmPCIE_MC_BLOCK_ALL0 0xc2 3423e5343bdSAlex Deucher #define mmPCIE_MC_BLOCK_ALL1 0xc3 3433e5343bdSAlex Deucher #define mmPCIE_MC_BLOCK_UNTRANSLATED_0 0xc4 3443e5343bdSAlex Deucher #define mmPCIE_MC_BLOCK_UNTRANSLATED_1 0xc5 3453e5343bdSAlex Deucher #define mmPCIE_LTR_ENH_CAP_LIST 0xc8 3463e5343bdSAlex Deucher #define mmPCIE_LTR_CAP 0xc9 3473e5343bdSAlex Deucher #define ixMM_INDEX_IND 0x1090000 3483e5343bdSAlex Deucher #define ixMM_INDEX_HI_IND 0x1090006 3493e5343bdSAlex Deucher #define ixMM_DATA_IND 0x1090001 3503e5343bdSAlex Deucher #define ixBIF_MM_INDACCESS_CNTL_IND 0x1091500 3513e5343bdSAlex Deucher #define ixBUS_CNTL_IND 0x1091508 3523e5343bdSAlex Deucher #define ixCONFIG_CNTL_IND 0x1091509 3533e5343bdSAlex Deucher #define ixCONFIG_MEMSIZE_IND 0x109150a 3543e5343bdSAlex Deucher #define ixCONFIG_F0_BASE_IND 0x109150b 3553e5343bdSAlex Deucher #define ixCONFIG_APER_SIZE_IND 0x109150c 3563e5343bdSAlex Deucher #define ixCONFIG_REG_APER_SIZE_IND 0x109150d 3573e5343bdSAlex Deucher #define ixBIF_SCRATCH0_IND 0x109150e 3583e5343bdSAlex Deucher #define ixBIF_SCRATCH1_IND 0x109150f 3593e5343bdSAlex Deucher #define ixBX_RESET_EN_IND 0x1091514 3603e5343bdSAlex Deucher #define ixMM_CFGREGS_CNTL_IND 0x1091513 3613e5343bdSAlex Deucher #define ixHW_DEBUG_IND 0x1091515 3623e5343bdSAlex Deucher #define ixMASTER_CREDIT_CNTL_IND 0x1091516 3633e5343bdSAlex Deucher #define ixSLAVE_REQ_CREDIT_CNTL_IND 0x1091517 3643e5343bdSAlex Deucher #define ixBX_RESET_CNTL_IND 0x1091518 3653e5343bdSAlex Deucher #define ixINTERRUPT_CNTL_IND 0x109151a 3663e5343bdSAlex Deucher #define ixINTERRUPT_CNTL2_IND 0x109151b 3673e5343bdSAlex Deucher #define ixBIF_DEBUG_CNTL_IND 0x109151c 3683e5343bdSAlex Deucher #define ixBIF_DEBUG_MUX_IND 0x109151d 3693e5343bdSAlex Deucher #define ixBIF_DEBUG_OUT_IND 0x109151e 3703e5343bdSAlex Deucher #define ixHDP_REG_COHERENCY_FLUSH_CNTL_IND 0x1091528 3713e5343bdSAlex Deucher #define ixHDP_MEM_COHERENCY_FLUSH_CNTL_IND 0x1091520 3723e5343bdSAlex Deucher #define ixCLKREQB_PAD_CNTL_IND 0x1091521 3733e5343bdSAlex Deucher #define ixSMBDAT_PAD_CNTL_IND 0x1091522 3743e5343bdSAlex Deucher #define ixSMBCLK_PAD_CNTL_IND 0x1091523 3753e5343bdSAlex Deucher #define ixBIF_XDMA_LO_IND 0x10914c0 3763e5343bdSAlex Deucher #define ixBIF_XDMA_HI_IND 0x10914c1 3773e5343bdSAlex Deucher #define ixBIF_FEATURES_CONTROL_MISC_IND 0x10914c2 3783e5343bdSAlex Deucher #define ixBIF_DOORBELL_CNTL_IND 0x10914c3 3793e5343bdSAlex Deucher #define ixBIF_SLVARB_MODE_IND 0x10914c4 3803e5343bdSAlex Deucher #define ixBIF_FB_EN_IND 0x1091524 3813e5343bdSAlex Deucher #define ixBIF_BUSNUM_CNTL1_IND 0x1091525 3823e5343bdSAlex Deucher #define ixBIF_BUSNUM_LIST0_IND 0x1091526 3833e5343bdSAlex Deucher #define ixBIF_BUSNUM_LIST1_IND 0x1091527 3843e5343bdSAlex Deucher #define ixBIF_BUSNUM_CNTL2_IND 0x109152b 3853e5343bdSAlex Deucher #define ixBIF_BUSY_DELAY_CNTR_IND 0x1091529 3863e5343bdSAlex Deucher #define ixBIF_PERFMON_CNTL_IND 0x109152c 3873e5343bdSAlex Deucher #define ixBIF_PERFCOUNTER0_RESULT_IND 0x109152d 3883e5343bdSAlex Deucher #define ixBIF_PERFCOUNTER1_RESULT_IND 0x109152e 3893e5343bdSAlex Deucher #define ixSLAVE_HANG_PROTECTION_CNTL_IND 0x1091536 3903e5343bdSAlex Deucher #define ixGPU_HDP_FLUSH_REQ_IND 0x1091537 3913e5343bdSAlex Deucher #define ixGPU_HDP_FLUSH_DONE_IND 0x1091538 3923e5343bdSAlex Deucher #define ixSLAVE_HANG_ERROR_IND 0x109153b 3933e5343bdSAlex Deucher #define ixCAPTURE_HOST_BUSNUM_IND 0x109153c 3943e5343bdSAlex Deucher #define ixHOST_BUSNUM_IND 0x109153d 3953e5343bdSAlex Deucher #define ixPEER_REG_RANGE0_IND 0x109153e 3963e5343bdSAlex Deucher #define ixPEER_REG_RANGE1_IND 0x109153f 3973e5343bdSAlex Deucher #define ixPEER0_FB_OFFSET_HI_IND 0x10914f3 3983e5343bdSAlex Deucher #define ixPEER0_FB_OFFSET_LO_IND 0x10914f2 3993e5343bdSAlex Deucher #define ixPEER1_FB_OFFSET_HI_IND 0x10914f1 4003e5343bdSAlex Deucher #define ixPEER1_FB_OFFSET_LO_IND 0x10914f0 4013e5343bdSAlex Deucher #define ixPEER2_FB_OFFSET_HI_IND 0x10914ef 4023e5343bdSAlex Deucher #define ixPEER2_FB_OFFSET_LO_IND 0x10914ee 4033e5343bdSAlex Deucher #define ixPEER3_FB_OFFSET_HI_IND 0x10914ed 4043e5343bdSAlex Deucher #define ixPEER3_FB_OFFSET_LO_IND 0x10914ec 4053e5343bdSAlex Deucher #define ixDBG_BYPASS_SRBM_ACCESS_IND 0x10914eb 4063e5343bdSAlex Deucher #define ixSMBUS_BACO_DUMMY_IND 0x10914c6 4073e5343bdSAlex Deucher #define ixBIF_DEVFUNCNUM_LIST0_IND 0x10914e8 4083e5343bdSAlex Deucher #define ixBIF_DEVFUNCNUM_LIST1_IND 0x10914e7 4093e5343bdSAlex Deucher #define ixBACO_CNTL_IND 0x10914e5 4103e5343bdSAlex Deucher #define ixBF_ANA_ISO_CNTL_IND 0x10914c7 4113e5343bdSAlex Deucher #define ixMEM_TYPE_CNTL_IND 0x10914e4 4123e5343bdSAlex Deucher #define ixBIF_BACO_DEBUG_IND 0x10914df 4133e5343bdSAlex Deucher #define ixBIF_BACO_DEBUG_LATCH_IND 0x10914dc 4143e5343bdSAlex Deucher #define ixBACO_CNTL_MISC_IND 0x10914db 4153e5343bdSAlex Deucher #define ixSMU_BIF_VDDGFX_PWR_STATUS_IND 0x10914f8 4163e5343bdSAlex Deucher #define ixBIF_VDDGFX_GFX0_LOWER_IND 0x1091428 4173e5343bdSAlex Deucher #define ixBIF_VDDGFX_GFX0_UPPER_IND 0x1091429 4183e5343bdSAlex Deucher #define ixBIF_VDDGFX_GFX1_LOWER_IND 0x109142a 4193e5343bdSAlex Deucher #define ixBIF_VDDGFX_GFX1_UPPER_IND 0x109142b 4203e5343bdSAlex Deucher #define ixBIF_VDDGFX_GFX2_LOWER_IND 0x109142c 4213e5343bdSAlex Deucher #define ixBIF_VDDGFX_GFX2_UPPER_IND 0x109142d 4223e5343bdSAlex Deucher #define ixBIF_VDDGFX_GFX3_LOWER_IND 0x109142e 4233e5343bdSAlex Deucher #define ixBIF_VDDGFX_GFX3_UPPER_IND 0x109142f 4243e5343bdSAlex Deucher #define ixBIF_VDDGFX_GFX4_LOWER_IND 0x1091430 4253e5343bdSAlex Deucher #define ixBIF_VDDGFX_GFX4_UPPER_IND 0x1091431 4263e5343bdSAlex Deucher #define ixBIF_VDDGFX_GFX5_LOWER_IND 0x1091432 4273e5343bdSAlex Deucher #define ixBIF_VDDGFX_GFX5_UPPER_IND 0x1091433 4283e5343bdSAlex Deucher #define ixBIF_VDDGFX_RSV1_LOWER_IND 0x1091434 4293e5343bdSAlex Deucher #define ixBIF_VDDGFX_RSV1_UPPER_IND 0x1091435 4303e5343bdSAlex Deucher #define ixBIF_VDDGFX_RSV2_LOWER_IND 0x1091436 4313e5343bdSAlex Deucher #define ixBIF_VDDGFX_RSV2_UPPER_IND 0x1091437 4323e5343bdSAlex Deucher #define ixBIF_VDDGFX_RSV3_LOWER_IND 0x1091438 4333e5343bdSAlex Deucher #define ixBIF_VDDGFX_RSV3_UPPER_IND 0x1091439 4343e5343bdSAlex Deucher #define ixBIF_VDDGFX_RSV4_LOWER_IND 0x109143a 4353e5343bdSAlex Deucher #define ixBIF_VDDGFX_RSV4_UPPER_IND 0x109143b 4363e5343bdSAlex Deucher #define ixBIF_VDDGFX_FB_CMP_IND 0x109143c 4373e5343bdSAlex Deucher #define ixBIF_DOORBELL_GBLAPER1_LOWER_IND 0x10914fc 4383e5343bdSAlex Deucher #define ixBIF_DOORBELL_GBLAPER1_UPPER_IND 0x10914fd 4393e5343bdSAlex Deucher #define ixBIF_DOORBELL_GBLAPER2_LOWER_IND 0x10914fe 4403e5343bdSAlex Deucher #define ixBIF_DOORBELL_GBLAPER2_UPPER_IND 0x10914ff 4413e5343bdSAlex Deucher #define ixBIF_SMU_INDEX_IND 0x109143d 4423e5343bdSAlex Deucher #define ixBIF_SMU_DATA_IND 0x109143e 4433e5343bdSAlex Deucher #define ixIMPCTL_RESET_IND 0x10914f5 4443e5343bdSAlex Deucher #define ixGARLIC_FLUSH_CNTL_IND 0x1091401 4453e5343bdSAlex Deucher #define ixGARLIC_FLUSH_REQ_IND 0x1091412 4463e5343bdSAlex Deucher #define ixGPU_GARLIC_FLUSH_REQ_IND 0x1091413 4473e5343bdSAlex Deucher #define ixGPU_GARLIC_FLUSH_DONE_IND 0x1091414 4483e5343bdSAlex Deucher #define ixGARLIC_COHE_CP_RB0_WPTR_IND 0x1091415 4493e5343bdSAlex Deucher #define ixGARLIC_COHE_CP_RB1_WPTR_IND 0x1091416 4503e5343bdSAlex Deucher #define ixGARLIC_COHE_CP_RB2_WPTR_IND 0x1091417 4513e5343bdSAlex Deucher #define ixGARLIC_COHE_UVD_RBC_RB_WPTR_IND 0x1091418 4523e5343bdSAlex Deucher #define ixGARLIC_COHE_SDMA0_GFX_RB_WPTR_IND 0x1091419 4533e5343bdSAlex Deucher #define ixGARLIC_COHE_SDMA1_GFX_RB_WPTR_IND 0x109141a 4543e5343bdSAlex Deucher #define ixGARLIC_COHE_CP_DMA_ME_COMMAND_IND 0x109141b 4553e5343bdSAlex Deucher #define ixGARLIC_COHE_CP_DMA_PFP_COMMAND_IND 0x109141c 4563e5343bdSAlex Deucher #define ixGARLIC_COHE_SAM_SAB_RBI_WPTR_IND 0x109141d 4573e5343bdSAlex Deucher #define ixGARLIC_COHE_SAM_SAB_RBO_WPTR_IND 0x109141e 4583e5343bdSAlex Deucher #define ixGARLIC_COHE_VCE_OUT_RB_WPTR_IND 0x109141f 4593e5343bdSAlex Deucher #define ixGARLIC_COHE_VCE_RB_WPTR2_IND 0x1091420 4603e5343bdSAlex Deucher #define ixGARLIC_COHE_VCE_RB_WPTR_IND 0x1091421 4613e5343bdSAlex Deucher #define ixGARLIC_COHE_SDMA2_GFX_RB_WPTR_IND 0x1091422 4623e5343bdSAlex Deucher #define ixGARLIC_COHE_SDMA3_GFX_RB_WPTR_IND 0x1091423 4633e5343bdSAlex Deucher #define ixGARLIC_COHE_CP_DMA_PIO_COMMAND_IND 0x1091424 4643e5343bdSAlex Deucher #define ixGARLIC_COHE_GARLIC_FLUSH_REQ_IND 0x1091425 4653e5343bdSAlex Deucher #define ixREMAP_HDP_MEM_FLUSH_CNTL_IND 0x1091426 4663e5343bdSAlex Deucher #define ixREMAP_HDP_REG_FLUSH_CNTL_IND 0x1091427 4673e5343bdSAlex Deucher #define ixBIOS_SCRATCH_0_IND 0x10905c9 4683e5343bdSAlex Deucher #define ixBIOS_SCRATCH_1_IND 0x10905ca 4693e5343bdSAlex Deucher #define ixBIOS_SCRATCH_2_IND 0x10905cb 4703e5343bdSAlex Deucher #define ixBIOS_SCRATCH_3_IND 0x10905cc 4713e5343bdSAlex Deucher #define ixBIOS_SCRATCH_4_IND 0x10905cd 4723e5343bdSAlex Deucher #define ixBIOS_SCRATCH_5_IND 0x10905ce 4733e5343bdSAlex Deucher #define ixBIOS_SCRATCH_6_IND 0x10905cf 4743e5343bdSAlex Deucher #define ixBIOS_SCRATCH_7_IND 0x10905d0 4753e5343bdSAlex Deucher #define ixBIOS_SCRATCH_8_IND 0x10905d1 4763e5343bdSAlex Deucher #define ixBIOS_SCRATCH_9_IND 0x10905d2 4773e5343bdSAlex Deucher #define ixBIOS_SCRATCH_10_IND 0x10905d3 4783e5343bdSAlex Deucher #define ixBIOS_SCRATCH_11_IND 0x10905d4 4793e5343bdSAlex Deucher #define ixBIOS_SCRATCH_12_IND 0x10905d5 4803e5343bdSAlex Deucher #define ixBIOS_SCRATCH_13_IND 0x10905d6 4813e5343bdSAlex Deucher #define ixBIOS_SCRATCH_14_IND 0x10905d7 4823e5343bdSAlex Deucher #define ixBIOS_SCRATCH_15_IND 0x10905d8 4833e5343bdSAlex Deucher #define ixBIF_RB_CNTL_IND 0x1091530 4843e5343bdSAlex Deucher #define ixBIF_RB_BASE_IND 0x1091531 4853e5343bdSAlex Deucher #define ixBIF_RB_RPTR_IND 0x1091532 4863e5343bdSAlex Deucher #define ixBIF_RB_WPTR_IND 0x1091533 4873e5343bdSAlex Deucher #define ixBIF_RB_WPTR_ADDR_HI_IND 0x1091534 4883e5343bdSAlex Deucher #define ixBIF_RB_WPTR_ADDR_LO_IND 0x1091535 4893e5343bdSAlex Deucher #define mmNB_GBIF_INDEX 0x34 4903e5343bdSAlex Deucher #define mmNB_GBIF_DATA 0x35 4913e5343bdSAlex Deucher #define mmPCIE_INDEX 0xe 4923e5343bdSAlex Deucher #define mmPCIE_DATA 0xf 4933e5343bdSAlex Deucher #define mmPCIE_INDEX_2 0xc 4943e5343bdSAlex Deucher #define mmPCIE_DATA_2 0xd 4953e5343bdSAlex Deucher #define ixPCIE_RESERVED 0x1400000 4963e5343bdSAlex Deucher #define ixPCIE_SCRATCH 0x1400001 4973e5343bdSAlex Deucher #define ixPCIE_HW_DEBUG 0x1400002 4983e5343bdSAlex Deucher #define ixPCIE_RX_NUM_NAK 0x140000e 4993e5343bdSAlex Deucher #define ixPCIE_RX_NUM_NAK_GENERATED 0x140000f 5003e5343bdSAlex Deucher #define ixPCIE_CNTL 0x1400010 5013e5343bdSAlex Deucher #define ixPCIE_CONFIG_CNTL 0x1400011 5023e5343bdSAlex Deucher #define ixPCIE_DEBUG_CNTL 0x1400012 5033e5343bdSAlex Deucher #define ixPCIE_INT_CNTL 0x140001a 5043e5343bdSAlex Deucher #define ixPCIE_INT_STATUS 0x140001b 5053e5343bdSAlex Deucher #define ixPCIE_CNTL2 0x140001c 5063e5343bdSAlex Deucher #define ixPCIE_RX_CNTL2 0x140001d 5073e5343bdSAlex Deucher #define ixPCIE_TX_F0_ATTR_CNTL 0x140001e 5083e5343bdSAlex Deucher #define ixPCIE_TX_F1_F2_ATTR_CNTL 0x140001f 5093e5343bdSAlex Deucher #define ixPCIE_CI_CNTL 0x1400020 5103e5343bdSAlex Deucher #define ixPCIE_BUS_CNTL 0x1400021 5113e5343bdSAlex Deucher #define ixPCIE_LC_STATE6 0x1400022 5123e5343bdSAlex Deucher #define ixPCIE_LC_STATE7 0x1400023 5133e5343bdSAlex Deucher #define ixPCIE_LC_STATE8 0x1400024 5143e5343bdSAlex Deucher #define ixPCIE_LC_STATE9 0x1400025 5153e5343bdSAlex Deucher #define ixPCIE_LC_STATE10 0x1400026 5163e5343bdSAlex Deucher #define ixPCIE_LC_STATE11 0x1400027 5173e5343bdSAlex Deucher #define ixPCIE_LC_STATUS1 0x1400028 5183e5343bdSAlex Deucher #define ixPCIE_LC_STATUS2 0x1400029 5193e5343bdSAlex Deucher #define ixPCIE_WPR_CNTL 0x1400030 5203e5343bdSAlex Deucher #define ixPCIE_RX_LAST_TLP0 0x1400031 5213e5343bdSAlex Deucher #define ixPCIE_RX_LAST_TLP1 0x1400032 5223e5343bdSAlex Deucher #define ixPCIE_RX_LAST_TLP2 0x1400033 5233e5343bdSAlex Deucher #define ixPCIE_RX_LAST_TLP3 0x1400034 5243e5343bdSAlex Deucher #define ixPCIE_TX_LAST_TLP0 0x1400035 5253e5343bdSAlex Deucher #define ixPCIE_TX_LAST_TLP1 0x1400036 5263e5343bdSAlex Deucher #define ixPCIE_TX_LAST_TLP2 0x1400037 5273e5343bdSAlex Deucher #define ixPCIE_TX_LAST_TLP3 0x1400038 5283e5343bdSAlex Deucher #define ixPCIE_I2C_REG_ADDR_EXPAND 0x140003a 5293e5343bdSAlex Deucher #define ixPCIE_I2C_REG_DATA 0x140003b 5303e5343bdSAlex Deucher #define ixPCIE_CFG_CNTL 0x140003c 5313e5343bdSAlex Deucher #define ixPCIE_P_CNTL 0x1400040 5323e5343bdSAlex Deucher #define ixPCIE_P_BUF_STATUS 0x1400041 5333e5343bdSAlex Deucher #define ixPCIE_P_DECODER_STATUS 0x1400042 5343e5343bdSAlex Deucher #define ixPCIE_P_MISC_STATUS 0x1400043 5353e5343bdSAlex Deucher #define ixPCIE_P_RCV_L0S_FTS_DET 0x1400050 5363e5343bdSAlex Deucher #define ixPCIE_OBFF_CNTL 0x1400061 5373e5343bdSAlex Deucher #define ixPCIE_TX_LTR_CNTL 0x1400060 5383e5343bdSAlex Deucher #define ixPCIE_PERF_COUNT_CNTL 0x1400080 5393e5343bdSAlex Deucher #define ixPCIE_PERF_CNTL_TXCLK 0x1400081 5403e5343bdSAlex Deucher #define ixPCIE_PERF_COUNT0_TXCLK 0x1400082 5413e5343bdSAlex Deucher #define ixPCIE_PERF_COUNT1_TXCLK 0x1400083 5423e5343bdSAlex Deucher #define ixPCIE_PERF_CNTL_MST_R_CLK 0x1400084 5433e5343bdSAlex Deucher #define ixPCIE_PERF_COUNT0_MST_R_CLK 0x1400085 5443e5343bdSAlex Deucher #define ixPCIE_PERF_COUNT1_MST_R_CLK 0x1400086 5453e5343bdSAlex Deucher #define ixPCIE_PERF_CNTL_MST_C_CLK 0x1400087 5463e5343bdSAlex Deucher #define ixPCIE_PERF_COUNT0_MST_C_CLK 0x1400088 5473e5343bdSAlex Deucher #define ixPCIE_PERF_COUNT1_MST_C_CLK 0x1400089 5483e5343bdSAlex Deucher #define ixPCIE_PERF_CNTL_SLV_R_CLK 0x140008a 5493e5343bdSAlex Deucher #define ixPCIE_PERF_COUNT0_SLV_R_CLK 0x140008b 5503e5343bdSAlex Deucher #define ixPCIE_PERF_COUNT1_SLV_R_CLK 0x140008c 5513e5343bdSAlex Deucher #define ixPCIE_PERF_CNTL_SLV_S_C_CLK 0x140008d 5523e5343bdSAlex Deucher #define ixPCIE_PERF_COUNT0_SLV_S_C_CLK 0x140008e 5533e5343bdSAlex Deucher #define ixPCIE_PERF_COUNT1_SLV_S_C_CLK 0x140008f 5543e5343bdSAlex Deucher #define ixPCIE_PERF_CNTL_SLV_NS_C_CLK 0x1400090 5553e5343bdSAlex Deucher #define ixPCIE_PERF_COUNT0_SLV_NS_C_CLK 0x1400091 5563e5343bdSAlex Deucher #define ixPCIE_PERF_COUNT1_SLV_NS_C_CLK 0x1400092 5573e5343bdSAlex Deucher #define ixPCIE_PERF_CNTL_EVENT0_PORT_SEL 0x1400093 5583e5343bdSAlex Deucher #define ixPCIE_PERF_CNTL_EVENT1_PORT_SEL 0x1400094 5593e5343bdSAlex Deucher #define ixPCIE_PERF_CNTL_TXCLK2 0x1400095 5603e5343bdSAlex Deucher #define ixPCIE_PERF_COUNT0_TXCLK2 0x1400096 5613e5343bdSAlex Deucher #define ixPCIE_PERF_COUNT1_TXCLK2 0x1400097 5623e5343bdSAlex Deucher #define ixPCIE_STRAP_F0 0x14000b0 5633e5343bdSAlex Deucher #define ixPCIE_STRAP_F1 0x14000b1 5643e5343bdSAlex Deucher #define ixPCIE_STRAP_F2 0x14000b2 5653e5343bdSAlex Deucher #define ixPCIE_STRAP_F3 0x14000b3 5663e5343bdSAlex Deucher #define ixPCIE_STRAP_F4 0x14000b4 5673e5343bdSAlex Deucher #define ixPCIE_STRAP_F5 0x14000b5 5683e5343bdSAlex Deucher #define ixPCIE_STRAP_F6 0x14000b6 5693e5343bdSAlex Deucher #define ixPCIE_STRAP_F7 0x14000b7 5703e5343bdSAlex Deucher #define ixPCIE_STRAP_MISC 0x14000c0 5713e5343bdSAlex Deucher #define ixPCIE_STRAP_MISC2 0x14000c1 5723e5343bdSAlex Deucher #define ixPCIE_STRAP_PI 0x14000c2 5733e5343bdSAlex Deucher #define ixPCIE_STRAP_I2C_BD 0x14000c4 5743e5343bdSAlex Deucher #define ixPCIE_PRBS_CLR 0x14000c8 5753e5343bdSAlex Deucher #define ixPCIE_PRBS_STATUS1 0x14000c9 5763e5343bdSAlex Deucher #define ixPCIE_PRBS_STATUS2 0x14000ca 5773e5343bdSAlex Deucher #define ixPCIE_PRBS_FREERUN 0x14000cb 5783e5343bdSAlex Deucher #define ixPCIE_PRBS_MISC 0x14000cc 5793e5343bdSAlex Deucher #define ixPCIE_PRBS_USER_PATTERN 0x14000cd 5803e5343bdSAlex Deucher #define ixPCIE_PRBS_LO_BITCNT 0x14000ce 5813e5343bdSAlex Deucher #define ixPCIE_PRBS_HI_BITCNT 0x14000cf 5823e5343bdSAlex Deucher #define ixPCIE_PRBS_ERRCNT_0 0x14000d0 5833e5343bdSAlex Deucher #define ixPCIE_PRBS_ERRCNT_1 0x14000d1 5843e5343bdSAlex Deucher #define ixPCIE_PRBS_ERRCNT_2 0x14000d2 5853e5343bdSAlex Deucher #define ixPCIE_PRBS_ERRCNT_3 0x14000d3 5863e5343bdSAlex Deucher #define ixPCIE_PRBS_ERRCNT_4 0x14000d4 5873e5343bdSAlex Deucher #define ixPCIE_PRBS_ERRCNT_5 0x14000d5 5883e5343bdSAlex Deucher #define ixPCIE_PRBS_ERRCNT_6 0x14000d6 5893e5343bdSAlex Deucher #define ixPCIE_PRBS_ERRCNT_7 0x14000d7 5903e5343bdSAlex Deucher #define ixPCIE_PRBS_ERRCNT_8 0x14000d8 5913e5343bdSAlex Deucher #define ixPCIE_PRBS_ERRCNT_9 0x14000d9 5923e5343bdSAlex Deucher #define ixPCIE_PRBS_ERRCNT_10 0x14000da 5933e5343bdSAlex Deucher #define ixPCIE_PRBS_ERRCNT_11 0x14000db 5943e5343bdSAlex Deucher #define ixPCIE_PRBS_ERRCNT_12 0x14000dc 5953e5343bdSAlex Deucher #define ixPCIE_PRBS_ERRCNT_13 0x14000dd 5963e5343bdSAlex Deucher #define ixPCIE_PRBS_ERRCNT_14 0x14000de 5973e5343bdSAlex Deucher #define ixPCIE_PRBS_ERRCNT_15 0x14000df 5983e5343bdSAlex Deucher #define ixPCIE_F0_DPA_CAP 0x14000e0 5993e5343bdSAlex Deucher #define ixPCIE_F0_DPA_LATENCY_INDICATOR 0x14000e4 6003e5343bdSAlex Deucher #define ixPCIE_F0_DPA_CNTL 0x14000e5 6013e5343bdSAlex Deucher #define ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0 0x14000e7 6023e5343bdSAlex Deucher #define ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1 0x14000e8 6033e5343bdSAlex Deucher #define ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2 0x14000e9 6043e5343bdSAlex Deucher #define ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3 0x14000ea 6053e5343bdSAlex Deucher #define ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4 0x14000eb 6063e5343bdSAlex Deucher #define ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5 0x14000ec 6073e5343bdSAlex Deucher #define ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6 0x14000ed 6083e5343bdSAlex Deucher #define ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7 0x14000ee 6093e5343bdSAlex Deucher #define ixPCIEP_RESERVED 0x10010000 6103e5343bdSAlex Deucher #define ixPCIEP_SCRATCH 0x10010001 6113e5343bdSAlex Deucher #define ixPCIEP_HW_DEBUG 0x10010002 6123e5343bdSAlex Deucher #define ixPCIEP_PORT_CNTL 0x10010010 6133e5343bdSAlex Deucher #define ixPCIE_TX_CNTL 0x10010020 6143e5343bdSAlex Deucher #define ixPCIE_TX_REQUESTER_ID 0x10010021 6153e5343bdSAlex Deucher #define ixPCIE_TX_VENDOR_SPECIFIC 0x10010022 6163e5343bdSAlex Deucher #define ixPCIE_TX_REQUEST_NUM_CNTL 0x10010023 6173e5343bdSAlex Deucher #define ixPCIE_TX_SEQ 0x10010024 6183e5343bdSAlex Deucher #define ixPCIE_TX_REPLAY 0x10010025 6193e5343bdSAlex Deucher #define ixPCIE_TX_ACK_LATENCY_LIMIT 0x10010026 6203e5343bdSAlex Deucher #define ixPCIE_TX_CREDITS_ADVT_P 0x10010030 6213e5343bdSAlex Deucher #define ixPCIE_TX_CREDITS_ADVT_NP 0x10010031 6223e5343bdSAlex Deucher #define ixPCIE_TX_CREDITS_ADVT_CPL 0x10010032 6233e5343bdSAlex Deucher #define ixPCIE_TX_CREDITS_INIT_P 0x10010033 6243e5343bdSAlex Deucher #define ixPCIE_TX_CREDITS_INIT_NP 0x10010034 6253e5343bdSAlex Deucher #define ixPCIE_TX_CREDITS_INIT_CPL 0x10010035 6263e5343bdSAlex Deucher #define ixPCIE_TX_CREDITS_STATUS 0x10010036 6273e5343bdSAlex Deucher #define ixPCIE_TX_CREDITS_FCU_THRESHOLD 0x10010037 6283e5343bdSAlex Deucher #define ixPCIE_P_PORT_LANE_STATUS 0x10010050 6293e5343bdSAlex Deucher #define ixPCIE_FC_P 0x10010060 6303e5343bdSAlex Deucher #define ixPCIE_FC_NP 0x10010061 6313e5343bdSAlex Deucher #define ixPCIE_FC_CPL 0x10010062 6323e5343bdSAlex Deucher #define ixPCIE_ERR_CNTL 0x1001006a 6333e5343bdSAlex Deucher #define ixPCIE_RX_CNTL 0x10010070 6343e5343bdSAlex Deucher #define ixPCIE_RX_EXPECTED_SEQNUM 0x10010071 6353e5343bdSAlex Deucher #define ixPCIE_RX_VENDOR_SPECIFIC 0x10010072 6363e5343bdSAlex Deucher #define ixPCIE_RX_CNTL3 0x10010074 6373e5343bdSAlex Deucher #define ixPCIE_RX_CREDITS_ALLOCATED_P 0x10010080 6383e5343bdSAlex Deucher #define ixPCIE_RX_CREDITS_ALLOCATED_NP 0x10010081 6393e5343bdSAlex Deucher #define ixPCIE_RX_CREDITS_ALLOCATED_CPL 0x10010082 6403e5343bdSAlex Deucher #define ixPCIE_LC_CNTL 0x100100a0 6413e5343bdSAlex Deucher #define ixPCIE_LC_CNTL2 0x100100b1 6423e5343bdSAlex Deucher #define ixPCIE_LC_CNTL3 0x100100b5 6433e5343bdSAlex Deucher #define ixPCIE_LC_CNTL4 0x100100b6 6443e5343bdSAlex Deucher #define ixPCIE_LC_CNTL5 0x100100b7 6453e5343bdSAlex Deucher #define ixPCIE_LC_BW_CHANGE_CNTL 0x100100b2 6463e5343bdSAlex Deucher #define ixPCIE_LC_TRAINING_CNTL 0x100100a1 6473e5343bdSAlex Deucher #define ixPCIE_LC_LINK_WIDTH_CNTL 0x100100a2 6483e5343bdSAlex Deucher #define ixPCIE_LC_N_FTS_CNTL 0x100100a3 6493e5343bdSAlex Deucher #define ixPCIE_LC_SPEED_CNTL 0x100100a4 6503e5343bdSAlex Deucher #define ixPCIE_LC_CDR_CNTL 0x100100b3 6513e5343bdSAlex Deucher #define ixPCIE_LC_LANE_CNTL 0x100100b4 6523e5343bdSAlex Deucher #define ixPCIE_LC_FORCE_COEFF 0x100100b8 6533e5343bdSAlex Deucher #define ixPCIE_LC_BEST_EQ_SETTINGS 0x100100b9 6543e5343bdSAlex Deucher #define ixPCIE_LC_FORCE_EQ_REQ_COEFF 0x100100ba 6553e5343bdSAlex Deucher #define ixPCIE_LC_STATE0 0x100100a5 6563e5343bdSAlex Deucher #define ixPCIE_LC_STATE1 0x100100a6 6573e5343bdSAlex Deucher #define ixPCIE_LC_STATE2 0x100100a7 6583e5343bdSAlex Deucher #define ixPCIE_LC_STATE3 0x100100a8 6593e5343bdSAlex Deucher #define ixPCIE_LC_STATE4 0x100100a9 6603e5343bdSAlex Deucher #define ixPCIE_LC_STATE5 0x100100aa 6613e5343bdSAlex Deucher #define ixPCIEP_STRAP_LC 0x100100c0 6623e5343bdSAlex Deucher #define ixPCIEP_STRAP_MISC 0x100100c1 6633e5343bdSAlex Deucher #define ixPCIEP_BCH_ECC_CNTL 0x100100d0 6643e5343bdSAlex Deucher #define mmBIF_RFE_SNOOP_REG 0x27 6653e5343bdSAlex Deucher #define mmBIF_RFE_WARMRST_CNTL 0x1459 6663e5343bdSAlex Deucher #define mmBIF_RFE_SOFTRST_CNTL 0x1441 6673e5343bdSAlex Deucher #define mmBIF_RFE_CLIENT_SOFTRST_TRIGGER 0x1442 6683e5343bdSAlex Deucher #define mmBIF_RFE_MASTER_SOFTRST_TRIGGER 0x1443 6693e5343bdSAlex Deucher #define mmBIF_PWDN_COMMAND 0x1444 6703e5343bdSAlex Deucher #define mmBIF_PWDN_STATUS 0x1445 6713e5343bdSAlex Deucher #define mmBIF_RFE_MST_FBU_CMDSTATUS 0x1446 6723e5343bdSAlex Deucher #define mmBIF_RFE_MST_RWREG_RFEWGBIF_CMDSTATUS 0x1447 6733e5343bdSAlex Deucher #define mmBIF_RFE_MST_BX_CMDSTATUS 0x1448 6743e5343bdSAlex Deucher #define mmBIF_RFE_MST_TMOUT_STATUS 0x144b 6753e5343bdSAlex Deucher #define mmBIF_RFE_MMCFG_CNTL 0x144c 6763e5343bdSAlex Deucher #define ixBIF_CLOCKS_BITS_IND 0x1301489 6773e5343bdSAlex Deucher #define ixBIF_LNCNT_RESET_IND 0x1301488 6783e5343bdSAlex Deucher #define ixLNCNT_CONTROL_IND 0x1301487 6793e5343bdSAlex Deucher #define ixNEW_REFCLKB_TIMER_IND 0x1301485 6803e5343bdSAlex Deucher #define ixNEW_REFCLKB_TIMER_1_IND 0x1301484 6813e5343bdSAlex Deucher #define ixBIF_CLK_PDWN_DELAY_TIMER_IND 0x1301483 6823e5343bdSAlex Deucher #define ixBIF_RESET_EN_IND 0x1301482 6833e5343bdSAlex Deucher #define ixBIF_PIF_TXCLK_SWITCH_TIMER_IND 0x1301481 6843e5343bdSAlex Deucher #define ixBIF_BACO_MSIC_IND 0x1301480 6853e5343bdSAlex Deucher #define ixBIF_RESET_CNTL_IND 0x1301486 6863e5343bdSAlex Deucher #define ixBIF_RFE_CNTL_MISC_IND 0x130148c 6873e5343bdSAlex Deucher #define ixBIF_MEM_PG_CNTL_IND 0x130148a 6883e5343bdSAlex Deucher #define mmNB_GBIF_INDEX 0x34 6893e5343bdSAlex Deucher #define mmNB_GBIF_DATA 0x35 6903e5343bdSAlex Deucher #define mmBIF_CLOCKS_BITS 0x1489 6913e5343bdSAlex Deucher #define mmBIF_LNCNT_RESET 0x1488 6923e5343bdSAlex Deucher #define mmLNCNT_CONTROL 0x1487 6933e5343bdSAlex Deucher #define mmNEW_REFCLKB_TIMER 0x1485 6943e5343bdSAlex Deucher #define mmNEW_REFCLKB_TIMER_1 0x1484 6953e5343bdSAlex Deucher #define mmBIF_CLK_PDWN_DELAY_TIMER 0x1483 6963e5343bdSAlex Deucher #define mmBIF_RESET_EN 0x1482 6973e5343bdSAlex Deucher #define mmBIF_PIF_TXCLK_SWITCH_TIMER 0x1481 6983e5343bdSAlex Deucher #define mmBIF_BACO_MSIC 0x1480 6993e5343bdSAlex Deucher #define mmBIF_RESET_CNTL 0x1486 7003e5343bdSAlex Deucher #define mmBIF_RFE_CNTL_MISC 0x148c 7013e5343bdSAlex Deucher #define mmBIF_MEM_PG_CNTL 0x148a 7023e5343bdSAlex Deucher #define mmC_PCIE_P_INDEX 0x38 7033e5343bdSAlex Deucher #define mmC_PCIE_P_DATA 0x39 7043e5343bdSAlex Deucher #define ixD2F1_PCIE_PORT_INDEX 0x2000038 7053e5343bdSAlex Deucher #define ixD2F1_PCIE_PORT_DATA 0x2000039 7063e5343bdSAlex Deucher #define ixD2F1_PCIEP_RESERVED 0x0 7073e5343bdSAlex Deucher #define ixD2F1_PCIEP_SCRATCH 0x1 7083e5343bdSAlex Deucher #define ixD2F1_PCIEP_HW_DEBUG 0x2 7093e5343bdSAlex Deucher #define ixD2F1_PCIEP_PORT_CNTL 0x10 7103e5343bdSAlex Deucher #define ixD2F1_PCIE_TX_CNTL 0x20 7113e5343bdSAlex Deucher #define ixD2F1_PCIE_TX_REQUESTER_ID 0x21 7123e5343bdSAlex Deucher #define ixD2F1_PCIE_TX_VENDOR_SPECIFIC 0x22 7133e5343bdSAlex Deucher #define ixD2F1_PCIE_TX_REQUEST_NUM_CNTL 0x23 7143e5343bdSAlex Deucher #define ixD2F1_PCIE_TX_SEQ 0x24 7153e5343bdSAlex Deucher #define ixD2F1_PCIE_TX_REPLAY 0x25 7163e5343bdSAlex Deucher #define ixD2F1_PCIE_TX_ACK_LATENCY_LIMIT 0x26 7173e5343bdSAlex Deucher #define ixD2F1_PCIE_TX_CREDITS_ADVT_P 0x30 7183e5343bdSAlex Deucher #define ixD2F1_PCIE_TX_CREDITS_ADVT_NP 0x31 7193e5343bdSAlex Deucher #define ixD2F1_PCIE_TX_CREDITS_ADVT_CPL 0x32 7203e5343bdSAlex Deucher #define ixD2F1_PCIE_TX_CREDITS_INIT_P 0x33 7213e5343bdSAlex Deucher #define ixD2F1_PCIE_TX_CREDITS_INIT_NP 0x34 7223e5343bdSAlex Deucher #define ixD2F1_PCIE_TX_CREDITS_INIT_CPL 0x35 7233e5343bdSAlex Deucher #define ixD2F1_PCIE_TX_CREDITS_STATUS 0x36 7243e5343bdSAlex Deucher #define ixD2F1_PCIE_TX_CREDITS_FCU_THRESHOLD 0x37 7253e5343bdSAlex Deucher #define ixD2F1_PCIE_P_PORT_LANE_STATUS 0x50 7263e5343bdSAlex Deucher #define ixD2F1_PCIE_FC_P 0x60 7273e5343bdSAlex Deucher #define ixD2F1_PCIE_FC_NP 0x61 7283e5343bdSAlex Deucher #define ixD2F1_PCIE_FC_CPL 0x62 7293e5343bdSAlex Deucher #define ixD2F1_PCIE_ERR_CNTL 0x6a 7303e5343bdSAlex Deucher #define ixD2F1_PCIE_RX_CNTL 0x70 7313e5343bdSAlex Deucher #define ixD2F1_PCIE_RX_EXPECTED_SEQNUM 0x71 7323e5343bdSAlex Deucher #define ixD2F1_PCIE_RX_VENDOR_SPECIFIC 0x72 7333e5343bdSAlex Deucher #define ixD2F1_PCIE_RX_CNTL3 0x74 7343e5343bdSAlex Deucher #define ixD2F1_PCIE_RX_CREDITS_ALLOCATED_P 0x80 7353e5343bdSAlex Deucher #define ixD2F1_PCIE_RX_CREDITS_ALLOCATED_NP 0x81 7363e5343bdSAlex Deucher #define ixD2F1_PCIE_RX_CREDITS_ALLOCATED_CPL 0x82 7373e5343bdSAlex Deucher #define ixD2F1_PCIEP_ERROR_INJECT_PHYSICAL 0x83 7383e5343bdSAlex Deucher #define ixD2F1_PCIEP_ERROR_INJECT_TRANSACTION 0x84 7393e5343bdSAlex Deucher #define ixD2F1_PCIE_LC_CNTL 0xa0 7403e5343bdSAlex Deucher #define ixD2F1_PCIE_LC_CNTL2 0xb1 7413e5343bdSAlex Deucher #define ixD2F1_PCIE_LC_CNTL3 0xb5 7423e5343bdSAlex Deucher #define ixD2F1_PCIE_LC_CNTL4 0xb6 7433e5343bdSAlex Deucher #define ixD2F1_PCIE_LC_CNTL5 0xb7 7443e5343bdSAlex Deucher #define ixD2F1_PCIE_LC_CNTL6 0xbb 7453e5343bdSAlex Deucher #define ixD2F1_PCIE_LC_BW_CHANGE_CNTL 0xb2 7463e5343bdSAlex Deucher #define ixD2F1_PCIE_LC_TRAINING_CNTL 0xa1 7473e5343bdSAlex Deucher #define ixD2F1_PCIE_LC_LINK_WIDTH_CNTL 0xa2 7483e5343bdSAlex Deucher #define ixD2F1_PCIE_LC_N_FTS_CNTL 0xa3 7493e5343bdSAlex Deucher #define ixD2F1_PCIE_LC_SPEED_CNTL 0xa4 7503e5343bdSAlex Deucher #define ixD2F1_PCIE_LC_CDR_CNTL 0xb3 7513e5343bdSAlex Deucher #define ixD2F1_PCIE_LC_LANE_CNTL 0xb4 7523e5343bdSAlex Deucher #define ixD2F1_PCIE_LC_FORCE_COEFF 0xb8 7533e5343bdSAlex Deucher #define ixD2F1_PCIE_LC_BEST_EQ_SETTINGS 0xb9 7543e5343bdSAlex Deucher #define ixD2F1_PCIE_LC_FORCE_EQ_REQ_COEFF 0xba 7553e5343bdSAlex Deucher #define ixD2F1_PCIE_LC_STATE0 0xa5 7563e5343bdSAlex Deucher #define ixD2F1_PCIE_LC_STATE1 0xa6 7573e5343bdSAlex Deucher #define ixD2F1_PCIE_LC_STATE2 0xa7 7583e5343bdSAlex Deucher #define ixD2F1_PCIE_LC_STATE3 0xa8 7593e5343bdSAlex Deucher #define ixD2F1_PCIE_LC_STATE4 0xa9 7603e5343bdSAlex Deucher #define ixD2F1_PCIE_LC_STATE5 0xaa 7613e5343bdSAlex Deucher #define ixD2F1_PCIEP_STRAP_LC 0xc0 7623e5343bdSAlex Deucher #define ixD2F1_PCIEP_STRAP_MISC 0xc1 7633e5343bdSAlex Deucher #define ixD2F1_PCIEP_BCH_ECC_CNTL 0xd0 7643e5343bdSAlex Deucher #define ixD2F1_PCIEP_HPGI_PRIVATE 0xd2 7653e5343bdSAlex Deucher #define ixD2F1_PCIEP_HPGI 0xda 7663e5343bdSAlex Deucher #define ixD2F1_VENDOR_ID 0x2000000 7673e5343bdSAlex Deucher #define ixD2F1_DEVICE_ID 0x2000000 7683e5343bdSAlex Deucher #define ixD2F1_COMMAND 0x2000001 7693e5343bdSAlex Deucher #define ixD2F1_STATUS 0x2000001 7703e5343bdSAlex Deucher #define ixD2F1_REVISION_ID 0x2000002 7713e5343bdSAlex Deucher #define ixD2F1_PROG_INTERFACE 0x2000002 7723e5343bdSAlex Deucher #define ixD2F1_SUB_CLASS 0x2000002 7733e5343bdSAlex Deucher #define ixD2F1_BASE_CLASS 0x2000002 7743e5343bdSAlex Deucher #define ixD2F1_CACHE_LINE 0x2000003 7753e5343bdSAlex Deucher #define ixD2F1_LATENCY 0x2000003 7763e5343bdSAlex Deucher #define ixD2F1_HEADER 0x2000003 7773e5343bdSAlex Deucher #define ixD2F1_BIST 0x2000003 7783e5343bdSAlex Deucher #define ixD2F1_SUB_BUS_NUMBER_LATENCY 0x2000006 7793e5343bdSAlex Deucher #define ixD2F1_IO_BASE_LIMIT 0x2000007 7803e5343bdSAlex Deucher #define ixD2F1_SECONDARY_STATUS 0x2000007 7813e5343bdSAlex Deucher #define ixD2F1_MEM_BASE_LIMIT 0x2000008 7823e5343bdSAlex Deucher #define ixD2F1_PREF_BASE_LIMIT 0x2000009 7833e5343bdSAlex Deucher #define ixD2F1_PREF_BASE_UPPER 0x200000a 7843e5343bdSAlex Deucher #define ixD2F1_PREF_LIMIT_UPPER 0x200000b 7853e5343bdSAlex Deucher #define ixD2F1_IO_BASE_LIMIT_HI 0x200000c 7863e5343bdSAlex Deucher #define ixD2F1_IRQ_BRIDGE_CNTL 0x200000f 7873e5343bdSAlex Deucher #define ixD2F1_CAP_PTR 0x200000d 7883e5343bdSAlex Deucher #define ixD2F1_INTERRUPT_LINE 0x200000f 7893e5343bdSAlex Deucher #define ixD2F1_INTERRUPT_PIN 0x200000f 7903e5343bdSAlex Deucher #define ixD2F1_EXT_BRIDGE_CNTL 0x2000010 7913e5343bdSAlex Deucher #define ixD2F1_PMI_CAP_LIST 0x2000014 7923e5343bdSAlex Deucher #define ixD2F1_PMI_CAP 0x2000014 7933e5343bdSAlex Deucher #define ixD2F1_PMI_STATUS_CNTL 0x2000015 7943e5343bdSAlex Deucher #define ixD2F1_PCIE_CAP_LIST 0x2000016 7953e5343bdSAlex Deucher #define ixD2F1_PCIE_CAP 0x2000016 7963e5343bdSAlex Deucher #define ixD2F1_DEVICE_CAP 0x2000017 7973e5343bdSAlex Deucher #define ixD2F1_DEVICE_CNTL 0x2000018 7983e5343bdSAlex Deucher #define ixD2F1_DEVICE_STATUS 0x2000018 7993e5343bdSAlex Deucher #define ixD2F1_LINK_CAP 0x2000019 8003e5343bdSAlex Deucher #define ixD2F1_LINK_CNTL 0x200001a 8013e5343bdSAlex Deucher #define ixD2F1_LINK_STATUS 0x200001a 8023e5343bdSAlex Deucher #define ixD2F1_SLOT_CAP 0x200001b 8033e5343bdSAlex Deucher #define ixD2F1_SLOT_CNTL 0x200001c 8043e5343bdSAlex Deucher #define ixD2F1_SLOT_STATUS 0x200001c 8053e5343bdSAlex Deucher #define ixD2F1_ROOT_CNTL 0x200001d 8063e5343bdSAlex Deucher #define ixD2F1_ROOT_CAP 0x200001d 8073e5343bdSAlex Deucher #define ixD2F1_ROOT_STATUS 0x200001e 8083e5343bdSAlex Deucher #define ixD2F1_DEVICE_CAP2 0x200001f 8093e5343bdSAlex Deucher #define ixD2F1_DEVICE_CNTL2 0x2000020 8103e5343bdSAlex Deucher #define ixD2F1_DEVICE_STATUS2 0x2000020 8113e5343bdSAlex Deucher #define ixD2F1_LINK_CAP2 0x2000021 8123e5343bdSAlex Deucher #define ixD2F1_LINK_CNTL2 0x2000022 8133e5343bdSAlex Deucher #define ixD2F1_LINK_STATUS2 0x2000022 8143e5343bdSAlex Deucher #define ixD2F1_SLOT_CAP2 0x2000023 8153e5343bdSAlex Deucher #define ixD2F1_SLOT_CNTL2 0x2000024 8163e5343bdSAlex Deucher #define ixD2F1_SLOT_STATUS2 0x2000024 8173e5343bdSAlex Deucher #define ixD2F1_MSI_CAP_LIST 0x2000028 8183e5343bdSAlex Deucher #define ixD2F1_MSI_MSG_CNTL 0x2000028 8193e5343bdSAlex Deucher #define ixD2F1_MSI_MSG_ADDR_LO 0x2000029 8203e5343bdSAlex Deucher #define ixD2F1_MSI_MSG_ADDR_HI 0x200002a 8213e5343bdSAlex Deucher #define ixD2F1_MSI_MSG_DATA_64 0x200002b 8223e5343bdSAlex Deucher #define ixD2F1_MSI_MSG_DATA 0x200002a 8233e5343bdSAlex Deucher #define ixD2F1_SSID_CAP_LIST 0x2000030 8243e5343bdSAlex Deucher #define ixD2F1_SSID_CAP 0x2000031 8253e5343bdSAlex Deucher #define ixD2F1_MSI_MAP_CAP_LIST 0x2000032 8263e5343bdSAlex Deucher #define ixD2F1_MSI_MAP_CAP 0x2000032 8273e5343bdSAlex Deucher #define ixD2F1_MSI_MAP_ADDR_LO 0x2000033 8283e5343bdSAlex Deucher #define ixD2F1_MSI_MAP_ADDR_HI 0x2000034 8293e5343bdSAlex Deucher #define ixD2F1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x2000040 8303e5343bdSAlex Deucher #define ixD2F1_PCIE_VENDOR_SPECIFIC_HDR 0x2000041 8313e5343bdSAlex Deucher #define ixD2F1_PCIE_VENDOR_SPECIFIC1 0x2000042 8323e5343bdSAlex Deucher #define ixD2F1_PCIE_VENDOR_SPECIFIC2 0x2000043 8333e5343bdSAlex Deucher #define ixD2F1_PCIE_VC_ENH_CAP_LIST 0x2000044 8343e5343bdSAlex Deucher #define ixD2F1_PCIE_PORT_VC_CAP_REG1 0x2000045 8353e5343bdSAlex Deucher #define ixD2F1_PCIE_PORT_VC_CAP_REG2 0x2000046 8363e5343bdSAlex Deucher #define ixD2F1_PCIE_PORT_VC_CNTL 0x2000047 8373e5343bdSAlex Deucher #define ixD2F1_PCIE_PORT_VC_STATUS 0x2000047 8383e5343bdSAlex Deucher #define ixD2F1_PCIE_VC0_RESOURCE_CAP 0x2000048 8393e5343bdSAlex Deucher #define ixD2F1_PCIE_VC0_RESOURCE_CNTL 0x2000049 8403e5343bdSAlex Deucher #define ixD2F1_PCIE_VC0_RESOURCE_STATUS 0x200004a 8413e5343bdSAlex Deucher #define ixD2F1_PCIE_VC1_RESOURCE_CAP 0x200004b 8423e5343bdSAlex Deucher #define ixD2F1_PCIE_VC1_RESOURCE_CNTL 0x200004c 8433e5343bdSAlex Deucher #define ixD2F1_PCIE_VC1_RESOURCE_STATUS 0x200004d 8443e5343bdSAlex Deucher #define ixD2F1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 0x2000050 8453e5343bdSAlex Deucher #define ixD2F1_PCIE_DEV_SERIAL_NUM_DW1 0x2000051 8463e5343bdSAlex Deucher #define ixD2F1_PCIE_DEV_SERIAL_NUM_DW2 0x2000052 8473e5343bdSAlex Deucher #define ixD2F1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x2000054 8483e5343bdSAlex Deucher #define ixD2F1_PCIE_UNCORR_ERR_STATUS 0x2000055 8493e5343bdSAlex Deucher #define ixD2F1_PCIE_UNCORR_ERR_MASK 0x2000056 8503e5343bdSAlex Deucher #define ixD2F1_PCIE_UNCORR_ERR_SEVERITY 0x2000057 8513e5343bdSAlex Deucher #define ixD2F1_PCIE_CORR_ERR_STATUS 0x2000058 8523e5343bdSAlex Deucher #define ixD2F1_PCIE_CORR_ERR_MASK 0x2000059 8533e5343bdSAlex Deucher #define ixD2F1_PCIE_ADV_ERR_CAP_CNTL 0x200005a 8543e5343bdSAlex Deucher #define ixD2F1_PCIE_HDR_LOG0 0x200005b 8553e5343bdSAlex Deucher #define ixD2F1_PCIE_HDR_LOG1 0x200005c 8563e5343bdSAlex Deucher #define ixD2F1_PCIE_HDR_LOG2 0x200005d 8573e5343bdSAlex Deucher #define ixD2F1_PCIE_HDR_LOG3 0x200005e 8583e5343bdSAlex Deucher #define ixD2F1_PCIE_ROOT_ERR_CMD 0x200005f 8593e5343bdSAlex Deucher #define ixD2F1_PCIE_ROOT_ERR_STATUS 0x2000060 8603e5343bdSAlex Deucher #define ixD2F1_PCIE_ERR_SRC_ID 0x2000061 8613e5343bdSAlex Deucher #define ixD2F1_PCIE_TLP_PREFIX_LOG0 0x2000062 8623e5343bdSAlex Deucher #define ixD2F1_PCIE_TLP_PREFIX_LOG1 0x2000063 8633e5343bdSAlex Deucher #define ixD2F1_PCIE_TLP_PREFIX_LOG2 0x2000064 8643e5343bdSAlex Deucher #define ixD2F1_PCIE_TLP_PREFIX_LOG3 0x2000065 8653e5343bdSAlex Deucher #define ixD2F1_PCIE_SECONDARY_ENH_CAP_LIST 0x200009c 8663e5343bdSAlex Deucher #define ixD2F1_PCIE_LINK_CNTL3 0x200009d 8673e5343bdSAlex Deucher #define ixD2F1_PCIE_LANE_ERROR_STATUS 0x200009e 8683e5343bdSAlex Deucher #define ixD2F1_PCIE_LANE_0_EQUALIZATION_CNTL 0x200009f 8693e5343bdSAlex Deucher #define ixD2F1_PCIE_LANE_1_EQUALIZATION_CNTL 0x200009f 8703e5343bdSAlex Deucher #define ixD2F1_PCIE_LANE_2_EQUALIZATION_CNTL 0x20000a0 8713e5343bdSAlex Deucher #define ixD2F1_PCIE_LANE_3_EQUALIZATION_CNTL 0x20000a0 8723e5343bdSAlex Deucher #define ixD2F1_PCIE_LANE_4_EQUALIZATION_CNTL 0x20000a1 8733e5343bdSAlex Deucher #define ixD2F1_PCIE_LANE_5_EQUALIZATION_CNTL 0x20000a1 8743e5343bdSAlex Deucher #define ixD2F1_PCIE_LANE_6_EQUALIZATION_CNTL 0x20000a2 8753e5343bdSAlex Deucher #define ixD2F1_PCIE_LANE_7_EQUALIZATION_CNTL 0x20000a2 8763e5343bdSAlex Deucher #define ixD2F1_PCIE_LANE_8_EQUALIZATION_CNTL 0x20000a3 8773e5343bdSAlex Deucher #define ixD2F1_PCIE_LANE_9_EQUALIZATION_CNTL 0x20000a3 8783e5343bdSAlex Deucher #define ixD2F1_PCIE_LANE_10_EQUALIZATION_CNTL 0x20000a4 8793e5343bdSAlex Deucher #define ixD2F1_PCIE_LANE_11_EQUALIZATION_CNTL 0x20000a4 8803e5343bdSAlex Deucher #define ixD2F1_PCIE_LANE_12_EQUALIZATION_CNTL 0x20000a5 8813e5343bdSAlex Deucher #define ixD2F1_PCIE_LANE_13_EQUALIZATION_CNTL 0x20000a5 8823e5343bdSAlex Deucher #define ixD2F1_PCIE_LANE_14_EQUALIZATION_CNTL 0x20000a6 8833e5343bdSAlex Deucher #define ixD2F1_PCIE_LANE_15_EQUALIZATION_CNTL 0x20000a6 8843e5343bdSAlex Deucher #define ixD2F1_PCIE_ACS_ENH_CAP_LIST 0x20000a8 8853e5343bdSAlex Deucher #define ixD2F1_PCIE_ACS_CAP 0x20000a9 8863e5343bdSAlex Deucher #define ixD2F1_PCIE_ACS_CNTL 0x20000a9 8873e5343bdSAlex Deucher #define ixD2F1_PCIE_MC_ENH_CAP_LIST 0x20000bc 8883e5343bdSAlex Deucher #define ixD2F1_PCIE_MC_CAP 0x20000bd 8893e5343bdSAlex Deucher #define ixD2F1_PCIE_MC_CNTL 0x20000bd 8903e5343bdSAlex Deucher #define ixD2F1_PCIE_MC_ADDR0 0x20000be 8913e5343bdSAlex Deucher #define ixD2F1_PCIE_MC_ADDR1 0x20000bf 8923e5343bdSAlex Deucher #define ixD2F1_PCIE_MC_RCV0 0x20000c0 8933e5343bdSAlex Deucher #define ixD2F1_PCIE_MC_RCV1 0x20000c1 8943e5343bdSAlex Deucher #define ixD2F1_PCIE_MC_BLOCK_ALL0 0x20000c2 8953e5343bdSAlex Deucher #define ixD2F1_PCIE_MC_BLOCK_ALL1 0x20000c3 8963e5343bdSAlex Deucher #define ixD2F1_PCIE_MC_BLOCK_UNTRANSLATED_0 0x20000c4 8973e5343bdSAlex Deucher #define ixD2F1_PCIE_MC_BLOCK_UNTRANSLATED_1 0x20000c5 8983e5343bdSAlex Deucher #define ixD2F1_PCIE_MC_OVERLAY_BAR0 0x20000c6 8993e5343bdSAlex Deucher #define ixD2F1_PCIE_MC_OVERLAY_BAR1 0x20000c7 9003e5343bdSAlex Deucher #define ixD2F2_PCIE_PORT_INDEX 0x3000038 9013e5343bdSAlex Deucher #define ixD2F2_PCIE_PORT_DATA 0x3000039 9023e5343bdSAlex Deucher #define ixD2F2_PCIEP_RESERVED 0x0 9033e5343bdSAlex Deucher #define ixD2F2_PCIEP_SCRATCH 0x1 9043e5343bdSAlex Deucher #define ixD2F2_PCIEP_HW_DEBUG 0x2 9053e5343bdSAlex Deucher #define ixD2F2_PCIEP_PORT_CNTL 0x10 9063e5343bdSAlex Deucher #define ixD2F2_PCIE_TX_CNTL 0x20 9073e5343bdSAlex Deucher #define ixD2F2_PCIE_TX_REQUESTER_ID 0x21 9083e5343bdSAlex Deucher #define ixD2F2_PCIE_TX_VENDOR_SPECIFIC 0x22 9093e5343bdSAlex Deucher #define ixD2F2_PCIE_TX_REQUEST_NUM_CNTL 0x23 9103e5343bdSAlex Deucher #define ixD2F2_PCIE_TX_SEQ 0x24 9113e5343bdSAlex Deucher #define ixD2F2_PCIE_TX_REPLAY 0x25 9123e5343bdSAlex Deucher #define ixD2F2_PCIE_TX_ACK_LATENCY_LIMIT 0x26 9133e5343bdSAlex Deucher #define ixD2F2_PCIE_TX_CREDITS_ADVT_P 0x30 9143e5343bdSAlex Deucher #define ixD2F2_PCIE_TX_CREDITS_ADVT_NP 0x31 9153e5343bdSAlex Deucher #define ixD2F2_PCIE_TX_CREDITS_ADVT_CPL 0x32 9163e5343bdSAlex Deucher #define ixD2F2_PCIE_TX_CREDITS_INIT_P 0x33 9173e5343bdSAlex Deucher #define ixD2F2_PCIE_TX_CREDITS_INIT_NP 0x34 9183e5343bdSAlex Deucher #define ixD2F2_PCIE_TX_CREDITS_INIT_CPL 0x35 9193e5343bdSAlex Deucher #define ixD2F2_PCIE_TX_CREDITS_STATUS 0x36 9203e5343bdSAlex Deucher #define ixD2F2_PCIE_TX_CREDITS_FCU_THRESHOLD 0x37 9213e5343bdSAlex Deucher #define ixD2F2_PCIE_P_PORT_LANE_STATUS 0x50 9223e5343bdSAlex Deucher #define ixD2F2_PCIE_FC_P 0x60 9233e5343bdSAlex Deucher #define ixD2F2_PCIE_FC_NP 0x61 9243e5343bdSAlex Deucher #define ixD2F2_PCIE_FC_CPL 0x62 9253e5343bdSAlex Deucher #define ixD2F2_PCIE_ERR_CNTL 0x6a 9263e5343bdSAlex Deucher #define ixD2F2_PCIE_RX_CNTL 0x70 9273e5343bdSAlex Deucher #define ixD2F2_PCIE_RX_EXPECTED_SEQNUM 0x71 9283e5343bdSAlex Deucher #define ixD2F2_PCIE_RX_VENDOR_SPECIFIC 0x72 9293e5343bdSAlex Deucher #define ixD2F2_PCIE_RX_CNTL3 0x74 9303e5343bdSAlex Deucher #define ixD2F2_PCIE_RX_CREDITS_ALLOCATED_P 0x80 9313e5343bdSAlex Deucher #define ixD2F2_PCIE_RX_CREDITS_ALLOCATED_NP 0x81 9323e5343bdSAlex Deucher #define ixD2F2_PCIE_RX_CREDITS_ALLOCATED_CPL 0x82 9333e5343bdSAlex Deucher #define ixD2F2_PCIEP_ERROR_INJECT_PHYSICAL 0x83 9343e5343bdSAlex Deucher #define ixD2F2_PCIEP_ERROR_INJECT_TRANSACTION 0x84 9353e5343bdSAlex Deucher #define ixD2F2_PCIE_LC_CNTL 0xa0 9363e5343bdSAlex Deucher #define ixD2F2_PCIE_LC_CNTL2 0xb1 9373e5343bdSAlex Deucher #define ixD2F2_PCIE_LC_CNTL3 0xb5 9383e5343bdSAlex Deucher #define ixD2F2_PCIE_LC_CNTL4 0xb6 9393e5343bdSAlex Deucher #define ixD2F2_PCIE_LC_CNTL5 0xb7 9403e5343bdSAlex Deucher #define ixD2F2_PCIE_LC_CNTL6 0xbb 9413e5343bdSAlex Deucher #define ixD2F2_PCIE_LC_BW_CHANGE_CNTL 0xb2 9423e5343bdSAlex Deucher #define ixD2F2_PCIE_LC_TRAINING_CNTL 0xa1 9433e5343bdSAlex Deucher #define ixD2F2_PCIE_LC_LINK_WIDTH_CNTL 0xa2 9443e5343bdSAlex Deucher #define ixD2F2_PCIE_LC_N_FTS_CNTL 0xa3 9453e5343bdSAlex Deucher #define ixD2F2_PCIE_LC_SPEED_CNTL 0xa4 9463e5343bdSAlex Deucher #define ixD2F2_PCIE_LC_CDR_CNTL 0xb3 9473e5343bdSAlex Deucher #define ixD2F2_PCIE_LC_LANE_CNTL 0xb4 9483e5343bdSAlex Deucher #define ixD2F2_PCIE_LC_FORCE_COEFF 0xb8 9493e5343bdSAlex Deucher #define ixD2F2_PCIE_LC_BEST_EQ_SETTINGS 0xb9 9503e5343bdSAlex Deucher #define ixD2F2_PCIE_LC_FORCE_EQ_REQ_COEFF 0xba 9513e5343bdSAlex Deucher #define ixD2F2_PCIE_LC_STATE0 0xa5 9523e5343bdSAlex Deucher #define ixD2F2_PCIE_LC_STATE1 0xa6 9533e5343bdSAlex Deucher #define ixD2F2_PCIE_LC_STATE2 0xa7 9543e5343bdSAlex Deucher #define ixD2F2_PCIE_LC_STATE3 0xa8 9553e5343bdSAlex Deucher #define ixD2F2_PCIE_LC_STATE4 0xa9 9563e5343bdSAlex Deucher #define ixD2F2_PCIE_LC_STATE5 0xaa 9573e5343bdSAlex Deucher #define ixD2F2_PCIEP_STRAP_LC 0xc0 9583e5343bdSAlex Deucher #define ixD2F2_PCIEP_STRAP_MISC 0xc1 9593e5343bdSAlex Deucher #define ixD2F2_PCIEP_BCH_ECC_CNTL 0xd0 9603e5343bdSAlex Deucher #define ixD2F2_PCIEP_HPGI_PRIVATE 0xd2 9613e5343bdSAlex Deucher #define ixD2F2_PCIEP_HPGI 0xda 9623e5343bdSAlex Deucher #define ixD2F2_VENDOR_ID 0x3000000 9633e5343bdSAlex Deucher #define ixD2F2_DEVICE_ID 0x3000000 9643e5343bdSAlex Deucher #define ixD2F2_COMMAND 0x3000001 9653e5343bdSAlex Deucher #define ixD2F2_STATUS 0x3000001 9663e5343bdSAlex Deucher #define ixD2F2_REVISION_ID 0x3000002 9673e5343bdSAlex Deucher #define ixD2F2_PROG_INTERFACE 0x3000002 9683e5343bdSAlex Deucher #define ixD2F2_SUB_CLASS 0x3000002 9693e5343bdSAlex Deucher #define ixD2F2_BASE_CLASS 0x3000002 9703e5343bdSAlex Deucher #define ixD2F2_CACHE_LINE 0x3000003 9713e5343bdSAlex Deucher #define ixD2F2_LATENCY 0x3000003 9723e5343bdSAlex Deucher #define ixD2F2_HEADER 0x3000003 9733e5343bdSAlex Deucher #define ixD2F2_BIST 0x3000003 9743e5343bdSAlex Deucher #define ixD2F2_SUB_BUS_NUMBER_LATENCY 0x3000006 9753e5343bdSAlex Deucher #define ixD2F2_IO_BASE_LIMIT 0x3000007 9763e5343bdSAlex Deucher #define ixD2F2_SECONDARY_STATUS 0x3000007 9773e5343bdSAlex Deucher #define ixD2F2_MEM_BASE_LIMIT 0x3000008 9783e5343bdSAlex Deucher #define ixD2F2_PREF_BASE_LIMIT 0x3000009 9793e5343bdSAlex Deucher #define ixD2F2_PREF_BASE_UPPER 0x300000a 9803e5343bdSAlex Deucher #define ixD2F2_PREF_LIMIT_UPPER 0x300000b 9813e5343bdSAlex Deucher #define ixD2F2_IO_BASE_LIMIT_HI 0x300000c 9823e5343bdSAlex Deucher #define ixD2F2_IRQ_BRIDGE_CNTL 0x300000f 9833e5343bdSAlex Deucher #define ixD2F2_CAP_PTR 0x300000d 9843e5343bdSAlex Deucher #define ixD2F2_INTERRUPT_LINE 0x300000f 9853e5343bdSAlex Deucher #define ixD2F2_INTERRUPT_PIN 0x300000f 9863e5343bdSAlex Deucher #define ixD2F2_EXT_BRIDGE_CNTL 0x3000010 9873e5343bdSAlex Deucher #define ixD2F2_PMI_CAP_LIST 0x3000014 9883e5343bdSAlex Deucher #define ixD2F2_PMI_CAP 0x3000014 9893e5343bdSAlex Deucher #define ixD2F2_PMI_STATUS_CNTL 0x3000015 9903e5343bdSAlex Deucher #define ixD2F2_PCIE_CAP_LIST 0x3000016 9913e5343bdSAlex Deucher #define ixD2F2_PCIE_CAP 0x3000016 9923e5343bdSAlex Deucher #define ixD2F2_DEVICE_CAP 0x3000017 9933e5343bdSAlex Deucher #define ixD2F2_DEVICE_CNTL 0x3000018 9943e5343bdSAlex Deucher #define ixD2F2_DEVICE_STATUS 0x3000018 9953e5343bdSAlex Deucher #define ixD2F2_LINK_CAP 0x3000019 9963e5343bdSAlex Deucher #define ixD2F2_LINK_CNTL 0x300001a 9973e5343bdSAlex Deucher #define ixD2F2_LINK_STATUS 0x300001a 9983e5343bdSAlex Deucher #define ixD2F2_SLOT_CAP 0x300001b 9993e5343bdSAlex Deucher #define ixD2F2_SLOT_CNTL 0x300001c 10003e5343bdSAlex Deucher #define ixD2F2_SLOT_STATUS 0x300001c 10013e5343bdSAlex Deucher #define ixD2F2_ROOT_CNTL 0x300001d 10023e5343bdSAlex Deucher #define ixD2F2_ROOT_CAP 0x300001d 10033e5343bdSAlex Deucher #define ixD2F2_ROOT_STATUS 0x300001e 10043e5343bdSAlex Deucher #define ixD2F2_DEVICE_CAP2 0x300001f 10053e5343bdSAlex Deucher #define ixD2F2_DEVICE_CNTL2 0x3000020 10063e5343bdSAlex Deucher #define ixD2F2_DEVICE_STATUS2 0x3000020 10073e5343bdSAlex Deucher #define ixD2F2_LINK_CAP2 0x3000021 10083e5343bdSAlex Deucher #define ixD2F2_LINK_CNTL2 0x3000022 10093e5343bdSAlex Deucher #define ixD2F2_LINK_STATUS2 0x3000022 10103e5343bdSAlex Deucher #define ixD2F2_SLOT_CAP2 0x3000023 10113e5343bdSAlex Deucher #define ixD2F2_SLOT_CNTL2 0x3000024 10123e5343bdSAlex Deucher #define ixD2F2_SLOT_STATUS2 0x3000024 10133e5343bdSAlex Deucher #define ixD2F2_MSI_CAP_LIST 0x3000028 10143e5343bdSAlex Deucher #define ixD2F2_MSI_MSG_CNTL 0x3000028 10153e5343bdSAlex Deucher #define ixD2F2_MSI_MSG_ADDR_LO 0x3000029 10163e5343bdSAlex Deucher #define ixD2F2_MSI_MSG_ADDR_HI 0x300002a 10173e5343bdSAlex Deucher #define ixD2F2_MSI_MSG_DATA_64 0x300002b 10183e5343bdSAlex Deucher #define ixD2F2_MSI_MSG_DATA 0x300002a 10193e5343bdSAlex Deucher #define ixD2F2_SSID_CAP_LIST 0x3000030 10203e5343bdSAlex Deucher #define ixD2F2_SSID_CAP 0x3000031 10213e5343bdSAlex Deucher #define ixD2F2_MSI_MAP_CAP_LIST 0x3000032 10223e5343bdSAlex Deucher #define ixD2F2_MSI_MAP_CAP 0x3000032 10233e5343bdSAlex Deucher #define ixD2F2_MSI_MAP_ADDR_LO 0x3000033 10243e5343bdSAlex Deucher #define ixD2F2_MSI_MAP_ADDR_HI 0x3000034 10253e5343bdSAlex Deucher #define ixD2F2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x3000040 10263e5343bdSAlex Deucher #define ixD2F2_PCIE_VENDOR_SPECIFIC_HDR 0x3000041 10273e5343bdSAlex Deucher #define ixD2F2_PCIE_VENDOR_SPECIFIC1 0x3000042 10283e5343bdSAlex Deucher #define ixD2F2_PCIE_VENDOR_SPECIFIC2 0x3000043 10293e5343bdSAlex Deucher #define ixD2F2_PCIE_VC_ENH_CAP_LIST 0x3000044 10303e5343bdSAlex Deucher #define ixD2F2_PCIE_PORT_VC_CAP_REG1 0x3000045 10313e5343bdSAlex Deucher #define ixD2F2_PCIE_PORT_VC_CAP_REG2 0x3000046 10323e5343bdSAlex Deucher #define ixD2F2_PCIE_PORT_VC_CNTL 0x3000047 10333e5343bdSAlex Deucher #define ixD2F2_PCIE_PORT_VC_STATUS 0x3000047 10343e5343bdSAlex Deucher #define ixD2F2_PCIE_VC0_RESOURCE_CAP 0x3000048 10353e5343bdSAlex Deucher #define ixD2F2_PCIE_VC0_RESOURCE_CNTL 0x3000049 10363e5343bdSAlex Deucher #define ixD2F2_PCIE_VC0_RESOURCE_STATUS 0x300004a 10373e5343bdSAlex Deucher #define ixD2F2_PCIE_VC1_RESOURCE_CAP 0x300004b 10383e5343bdSAlex Deucher #define ixD2F2_PCIE_VC1_RESOURCE_CNTL 0x300004c 10393e5343bdSAlex Deucher #define ixD2F2_PCIE_VC1_RESOURCE_STATUS 0x300004d 10403e5343bdSAlex Deucher #define ixD2F2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 0x3000050 10413e5343bdSAlex Deucher #define ixD2F2_PCIE_DEV_SERIAL_NUM_DW1 0x3000051 10423e5343bdSAlex Deucher #define ixD2F2_PCIE_DEV_SERIAL_NUM_DW2 0x3000052 10433e5343bdSAlex Deucher #define ixD2F2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x3000054 10443e5343bdSAlex Deucher #define ixD2F2_PCIE_UNCORR_ERR_STATUS 0x3000055 10453e5343bdSAlex Deucher #define ixD2F2_PCIE_UNCORR_ERR_MASK 0x3000056 10463e5343bdSAlex Deucher #define ixD2F2_PCIE_UNCORR_ERR_SEVERITY 0x3000057 10473e5343bdSAlex Deucher #define ixD2F2_PCIE_CORR_ERR_STATUS 0x3000058 10483e5343bdSAlex Deucher #define ixD2F2_PCIE_CORR_ERR_MASK 0x3000059 10493e5343bdSAlex Deucher #define ixD2F2_PCIE_ADV_ERR_CAP_CNTL 0x300005a 10503e5343bdSAlex Deucher #define ixD2F2_PCIE_HDR_LOG0 0x300005b 10513e5343bdSAlex Deucher #define ixD2F2_PCIE_HDR_LOG1 0x300005c 10523e5343bdSAlex Deucher #define ixD2F2_PCIE_HDR_LOG2 0x300005d 10533e5343bdSAlex Deucher #define ixD2F2_PCIE_HDR_LOG3 0x300005e 10543e5343bdSAlex Deucher #define ixD2F2_PCIE_ROOT_ERR_CMD 0x300005f 10553e5343bdSAlex Deucher #define ixD2F2_PCIE_ROOT_ERR_STATUS 0x3000060 10563e5343bdSAlex Deucher #define ixD2F2_PCIE_ERR_SRC_ID 0x3000061 10573e5343bdSAlex Deucher #define ixD2F2_PCIE_TLP_PREFIX_LOG0 0x3000062 10583e5343bdSAlex Deucher #define ixD2F2_PCIE_TLP_PREFIX_LOG1 0x3000063 10593e5343bdSAlex Deucher #define ixD2F2_PCIE_TLP_PREFIX_LOG2 0x3000064 10603e5343bdSAlex Deucher #define ixD2F2_PCIE_TLP_PREFIX_LOG3 0x3000065 10613e5343bdSAlex Deucher #define ixD2F2_PCIE_SECONDARY_ENH_CAP_LIST 0x300009c 10623e5343bdSAlex Deucher #define ixD2F2_PCIE_LINK_CNTL3 0x300009d 10633e5343bdSAlex Deucher #define ixD2F2_PCIE_LANE_ERROR_STATUS 0x300009e 10643e5343bdSAlex Deucher #define ixD2F2_PCIE_LANE_0_EQUALIZATION_CNTL 0x300009f 10653e5343bdSAlex Deucher #define ixD2F2_PCIE_LANE_1_EQUALIZATION_CNTL 0x300009f 10663e5343bdSAlex Deucher #define ixD2F2_PCIE_LANE_2_EQUALIZATION_CNTL 0x30000a0 10673e5343bdSAlex Deucher #define ixD2F2_PCIE_LANE_3_EQUALIZATION_CNTL 0x30000a0 10683e5343bdSAlex Deucher #define ixD2F2_PCIE_LANE_4_EQUALIZATION_CNTL 0x30000a1 10693e5343bdSAlex Deucher #define ixD2F2_PCIE_LANE_5_EQUALIZATION_CNTL 0x30000a1 10703e5343bdSAlex Deucher #define ixD2F2_PCIE_LANE_6_EQUALIZATION_CNTL 0x30000a2 10713e5343bdSAlex Deucher #define ixD2F2_PCIE_LANE_7_EQUALIZATION_CNTL 0x30000a2 10723e5343bdSAlex Deucher #define ixD2F2_PCIE_LANE_8_EQUALIZATION_CNTL 0x30000a3 10733e5343bdSAlex Deucher #define ixD2F2_PCIE_LANE_9_EQUALIZATION_CNTL 0x30000a3 10743e5343bdSAlex Deucher #define ixD2F2_PCIE_LANE_10_EQUALIZATION_CNTL 0x30000a4 10753e5343bdSAlex Deucher #define ixD2F2_PCIE_LANE_11_EQUALIZATION_CNTL 0x30000a4 10763e5343bdSAlex Deucher #define ixD2F2_PCIE_LANE_12_EQUALIZATION_CNTL 0x30000a5 10773e5343bdSAlex Deucher #define ixD2F2_PCIE_LANE_13_EQUALIZATION_CNTL 0x30000a5 10783e5343bdSAlex Deucher #define ixD2F2_PCIE_LANE_14_EQUALIZATION_CNTL 0x30000a6 10793e5343bdSAlex Deucher #define ixD2F2_PCIE_LANE_15_EQUALIZATION_CNTL 0x30000a6 10803e5343bdSAlex Deucher #define ixD2F2_PCIE_ACS_ENH_CAP_LIST 0x30000a8 10813e5343bdSAlex Deucher #define ixD2F2_PCIE_ACS_CAP 0x30000a9 10823e5343bdSAlex Deucher #define ixD2F2_PCIE_ACS_CNTL 0x30000a9 10833e5343bdSAlex Deucher #define ixD2F2_PCIE_MC_ENH_CAP_LIST 0x30000bc 10843e5343bdSAlex Deucher #define ixD2F2_PCIE_MC_CAP 0x30000bd 10853e5343bdSAlex Deucher #define ixD2F2_PCIE_MC_CNTL 0x30000bd 10863e5343bdSAlex Deucher #define ixD2F2_PCIE_MC_ADDR0 0x30000be 10873e5343bdSAlex Deucher #define ixD2F2_PCIE_MC_ADDR1 0x30000bf 10883e5343bdSAlex Deucher #define ixD2F2_PCIE_MC_RCV0 0x30000c0 10893e5343bdSAlex Deucher #define ixD2F2_PCIE_MC_RCV1 0x30000c1 10903e5343bdSAlex Deucher #define ixD2F2_PCIE_MC_BLOCK_ALL0 0x30000c2 10913e5343bdSAlex Deucher #define ixD2F2_PCIE_MC_BLOCK_ALL1 0x30000c3 10923e5343bdSAlex Deucher #define ixD2F2_PCIE_MC_BLOCK_UNTRANSLATED_0 0x30000c4 10933e5343bdSAlex Deucher #define ixD2F2_PCIE_MC_BLOCK_UNTRANSLATED_1 0x30000c5 10943e5343bdSAlex Deucher #define ixD2F2_PCIE_MC_OVERLAY_BAR0 0x30000c6 10953e5343bdSAlex Deucher #define ixD2F2_PCIE_MC_OVERLAY_BAR1 0x30000c7 10963e5343bdSAlex Deucher #define ixD2F3_PCIE_PORT_INDEX 0x4000038 10973e5343bdSAlex Deucher #define ixD2F3_PCIE_PORT_DATA 0x4000039 10983e5343bdSAlex Deucher #define ixD2F3_PCIEP_RESERVED 0x0 10993e5343bdSAlex Deucher #define ixD2F3_PCIEP_SCRATCH 0x1 11003e5343bdSAlex Deucher #define ixD2F3_PCIEP_HW_DEBUG 0x2 11013e5343bdSAlex Deucher #define ixD2F3_PCIEP_PORT_CNTL 0x10 11023e5343bdSAlex Deucher #define ixD2F3_PCIE_TX_CNTL 0x20 11033e5343bdSAlex Deucher #define ixD2F3_PCIE_TX_REQUESTER_ID 0x21 11043e5343bdSAlex Deucher #define ixD2F3_PCIE_TX_VENDOR_SPECIFIC 0x22 11053e5343bdSAlex Deucher #define ixD2F3_PCIE_TX_REQUEST_NUM_CNTL 0x23 11063e5343bdSAlex Deucher #define ixD2F3_PCIE_TX_SEQ 0x24 11073e5343bdSAlex Deucher #define ixD2F3_PCIE_TX_REPLAY 0x25 11083e5343bdSAlex Deucher #define ixD2F3_PCIE_TX_ACK_LATENCY_LIMIT 0x26 11093e5343bdSAlex Deucher #define ixD2F3_PCIE_TX_CREDITS_ADVT_P 0x30 11103e5343bdSAlex Deucher #define ixD2F3_PCIE_TX_CREDITS_ADVT_NP 0x31 11113e5343bdSAlex Deucher #define ixD2F3_PCIE_TX_CREDITS_ADVT_CPL 0x32 11123e5343bdSAlex Deucher #define ixD2F3_PCIE_TX_CREDITS_INIT_P 0x33 11133e5343bdSAlex Deucher #define ixD2F3_PCIE_TX_CREDITS_INIT_NP 0x34 11143e5343bdSAlex Deucher #define ixD2F3_PCIE_TX_CREDITS_INIT_CPL 0x35 11153e5343bdSAlex Deucher #define ixD2F3_PCIE_TX_CREDITS_STATUS 0x36 11163e5343bdSAlex Deucher #define ixD2F3_PCIE_TX_CREDITS_FCU_THRESHOLD 0x37 11173e5343bdSAlex Deucher #define ixD2F3_PCIE_P_PORT_LANE_STATUS 0x50 11183e5343bdSAlex Deucher #define ixD2F3_PCIE_FC_P 0x60 11193e5343bdSAlex Deucher #define ixD2F3_PCIE_FC_NP 0x61 11203e5343bdSAlex Deucher #define ixD2F3_PCIE_FC_CPL 0x62 11213e5343bdSAlex Deucher #define ixD2F3_PCIE_ERR_CNTL 0x6a 11223e5343bdSAlex Deucher #define ixD2F3_PCIE_RX_CNTL 0x70 11233e5343bdSAlex Deucher #define ixD2F3_PCIE_RX_EXPECTED_SEQNUM 0x71 11243e5343bdSAlex Deucher #define ixD2F3_PCIE_RX_VENDOR_SPECIFIC 0x72 11253e5343bdSAlex Deucher #define ixD2F3_PCIE_RX_CNTL3 0x74 11263e5343bdSAlex Deucher #define ixD2F3_PCIE_RX_CREDITS_ALLOCATED_P 0x80 11273e5343bdSAlex Deucher #define ixD2F3_PCIE_RX_CREDITS_ALLOCATED_NP 0x81 11283e5343bdSAlex Deucher #define ixD2F3_PCIE_RX_CREDITS_ALLOCATED_CPL 0x82 11293e5343bdSAlex Deucher #define ixD2F3_PCIEP_ERROR_INJECT_PHYSICAL 0x83 11303e5343bdSAlex Deucher #define ixD2F3_PCIEP_ERROR_INJECT_TRANSACTION 0x84 11313e5343bdSAlex Deucher #define ixD2F3_PCIE_LC_CNTL 0xa0 11323e5343bdSAlex Deucher #define ixD2F3_PCIE_LC_CNTL2 0xb1 11333e5343bdSAlex Deucher #define ixD2F3_PCIE_LC_CNTL3 0xb5 11343e5343bdSAlex Deucher #define ixD2F3_PCIE_LC_CNTL4 0xb6 11353e5343bdSAlex Deucher #define ixD2F3_PCIE_LC_CNTL5 0xb7 11363e5343bdSAlex Deucher #define ixD2F3_PCIE_LC_CNTL6 0xbb 11373e5343bdSAlex Deucher #define ixD2F3_PCIE_LC_BW_CHANGE_CNTL 0xb2 11383e5343bdSAlex Deucher #define ixD2F3_PCIE_LC_TRAINING_CNTL 0xa1 11393e5343bdSAlex Deucher #define ixD2F3_PCIE_LC_LINK_WIDTH_CNTL 0xa2 11403e5343bdSAlex Deucher #define ixD2F3_PCIE_LC_N_FTS_CNTL 0xa3 11413e5343bdSAlex Deucher #define ixD2F3_PCIE_LC_SPEED_CNTL 0xa4 11423e5343bdSAlex Deucher #define ixD2F3_PCIE_LC_CDR_CNTL 0xb3 11433e5343bdSAlex Deucher #define ixD2F3_PCIE_LC_LANE_CNTL 0xb4 11443e5343bdSAlex Deucher #define ixD2F3_PCIE_LC_FORCE_COEFF 0xb8 11453e5343bdSAlex Deucher #define ixD2F3_PCIE_LC_BEST_EQ_SETTINGS 0xb9 11463e5343bdSAlex Deucher #define ixD2F3_PCIE_LC_FORCE_EQ_REQ_COEFF 0xba 11473e5343bdSAlex Deucher #define ixD2F3_PCIE_LC_STATE0 0xa5 11483e5343bdSAlex Deucher #define ixD2F3_PCIE_LC_STATE1 0xa6 11493e5343bdSAlex Deucher #define ixD2F3_PCIE_LC_STATE2 0xa7 11503e5343bdSAlex Deucher #define ixD2F3_PCIE_LC_STATE3 0xa8 11513e5343bdSAlex Deucher #define ixD2F3_PCIE_LC_STATE4 0xa9 11523e5343bdSAlex Deucher #define ixD2F3_PCIE_LC_STATE5 0xaa 11533e5343bdSAlex Deucher #define ixD2F3_PCIEP_STRAP_LC 0xc0 11543e5343bdSAlex Deucher #define ixD2F3_PCIEP_STRAP_MISC 0xc1 11553e5343bdSAlex Deucher #define ixD2F3_PCIEP_BCH_ECC_CNTL 0xd0 11563e5343bdSAlex Deucher #define ixD2F3_PCIEP_HPGI_PRIVATE 0xd2 11573e5343bdSAlex Deucher #define ixD2F3_PCIEP_HPGI 0xda 11583e5343bdSAlex Deucher #define ixD2F3_VENDOR_ID 0x4000000 11593e5343bdSAlex Deucher #define ixD2F3_DEVICE_ID 0x4000000 11603e5343bdSAlex Deucher #define ixD2F3_COMMAND 0x4000001 11613e5343bdSAlex Deucher #define ixD2F3_STATUS 0x4000001 11623e5343bdSAlex Deucher #define ixD2F3_REVISION_ID 0x4000002 11633e5343bdSAlex Deucher #define ixD2F3_PROG_INTERFACE 0x4000002 11643e5343bdSAlex Deucher #define ixD2F3_SUB_CLASS 0x4000002 11653e5343bdSAlex Deucher #define ixD2F3_BASE_CLASS 0x4000002 11663e5343bdSAlex Deucher #define ixD2F3_CACHE_LINE 0x4000003 11673e5343bdSAlex Deucher #define ixD2F3_LATENCY 0x4000003 11683e5343bdSAlex Deucher #define ixD2F3_HEADER 0x4000003 11693e5343bdSAlex Deucher #define ixD2F3_BIST 0x4000003 11703e5343bdSAlex Deucher #define ixD2F3_SUB_BUS_NUMBER_LATENCY 0x4000006 11713e5343bdSAlex Deucher #define ixD2F3_IO_BASE_LIMIT 0x4000007 11723e5343bdSAlex Deucher #define ixD2F3_SECONDARY_STATUS 0x4000007 11733e5343bdSAlex Deucher #define ixD2F3_MEM_BASE_LIMIT 0x4000008 11743e5343bdSAlex Deucher #define ixD2F3_PREF_BASE_LIMIT 0x4000009 11753e5343bdSAlex Deucher #define ixD2F3_PREF_BASE_UPPER 0x400000a 11763e5343bdSAlex Deucher #define ixD2F3_PREF_LIMIT_UPPER 0x400000b 11773e5343bdSAlex Deucher #define ixD2F3_IO_BASE_LIMIT_HI 0x400000c 11783e5343bdSAlex Deucher #define ixD2F3_IRQ_BRIDGE_CNTL 0x400000f 11793e5343bdSAlex Deucher #define ixD2F3_CAP_PTR 0x400000d 11803e5343bdSAlex Deucher #define ixD2F3_INTERRUPT_LINE 0x400000f 11813e5343bdSAlex Deucher #define ixD2F3_INTERRUPT_PIN 0x400000f 11823e5343bdSAlex Deucher #define ixD2F3_EXT_BRIDGE_CNTL 0x4000010 11833e5343bdSAlex Deucher #define ixD2F3_PMI_CAP_LIST 0x4000014 11843e5343bdSAlex Deucher #define ixD2F3_PMI_CAP 0x4000014 11853e5343bdSAlex Deucher #define ixD2F3_PMI_STATUS_CNTL 0x4000015 11863e5343bdSAlex Deucher #define ixD2F3_PCIE_CAP_LIST 0x4000016 11873e5343bdSAlex Deucher #define ixD2F3_PCIE_CAP 0x4000016 11883e5343bdSAlex Deucher #define ixD2F3_DEVICE_CAP 0x4000017 11893e5343bdSAlex Deucher #define ixD2F3_DEVICE_CNTL 0x4000018 11903e5343bdSAlex Deucher #define ixD2F3_DEVICE_STATUS 0x4000018 11913e5343bdSAlex Deucher #define ixD2F3_LINK_CAP 0x4000019 11923e5343bdSAlex Deucher #define ixD2F3_LINK_CNTL 0x400001a 11933e5343bdSAlex Deucher #define ixD2F3_LINK_STATUS 0x400001a 11943e5343bdSAlex Deucher #define ixD2F3_SLOT_CAP 0x400001b 11953e5343bdSAlex Deucher #define ixD2F3_SLOT_CNTL 0x400001c 11963e5343bdSAlex Deucher #define ixD2F3_SLOT_STATUS 0x400001c 11973e5343bdSAlex Deucher #define ixD2F3_ROOT_CNTL 0x400001d 11983e5343bdSAlex Deucher #define ixD2F3_ROOT_CAP 0x400001d 11993e5343bdSAlex Deucher #define ixD2F3_ROOT_STATUS 0x400001e 12003e5343bdSAlex Deucher #define ixD2F3_DEVICE_CAP2 0x400001f 12013e5343bdSAlex Deucher #define ixD2F3_DEVICE_CNTL2 0x4000020 12023e5343bdSAlex Deucher #define ixD2F3_DEVICE_STATUS2 0x4000020 12033e5343bdSAlex Deucher #define ixD2F3_LINK_CAP2 0x4000021 12043e5343bdSAlex Deucher #define ixD2F3_LINK_CNTL2 0x4000022 12053e5343bdSAlex Deucher #define ixD2F3_LINK_STATUS2 0x4000022 12063e5343bdSAlex Deucher #define ixD2F3_SLOT_CAP2 0x4000023 12073e5343bdSAlex Deucher #define ixD2F3_SLOT_CNTL2 0x4000024 12083e5343bdSAlex Deucher #define ixD2F3_SLOT_STATUS2 0x4000024 12093e5343bdSAlex Deucher #define ixD2F3_MSI_CAP_LIST 0x4000028 12103e5343bdSAlex Deucher #define ixD2F3_MSI_MSG_CNTL 0x4000028 12113e5343bdSAlex Deucher #define ixD2F3_MSI_MSG_ADDR_LO 0x4000029 12123e5343bdSAlex Deucher #define ixD2F3_MSI_MSG_ADDR_HI 0x400002a 12133e5343bdSAlex Deucher #define ixD2F3_MSI_MSG_DATA_64 0x400002b 12143e5343bdSAlex Deucher #define ixD2F3_MSI_MSG_DATA 0x400002a 12153e5343bdSAlex Deucher #define ixD2F3_SSID_CAP_LIST 0x4000030 12163e5343bdSAlex Deucher #define ixD2F3_SSID_CAP 0x4000031 12173e5343bdSAlex Deucher #define ixD2F3_MSI_MAP_CAP_LIST 0x4000032 12183e5343bdSAlex Deucher #define ixD2F3_MSI_MAP_CAP 0x4000032 12193e5343bdSAlex Deucher #define ixD2F3_MSI_MAP_ADDR_LO 0x4000033 12203e5343bdSAlex Deucher #define ixD2F3_MSI_MAP_ADDR_HI 0x4000034 12213e5343bdSAlex Deucher #define ixD2F3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x4000040 12223e5343bdSAlex Deucher #define ixD2F3_PCIE_VENDOR_SPECIFIC_HDR 0x4000041 12233e5343bdSAlex Deucher #define ixD2F3_PCIE_VENDOR_SPECIFIC1 0x4000042 12243e5343bdSAlex Deucher #define ixD2F3_PCIE_VENDOR_SPECIFIC2 0x4000043 12253e5343bdSAlex Deucher #define ixD2F3_PCIE_VC_ENH_CAP_LIST 0x4000044 12263e5343bdSAlex Deucher #define ixD2F3_PCIE_PORT_VC_CAP_REG1 0x4000045 12273e5343bdSAlex Deucher #define ixD2F3_PCIE_PORT_VC_CAP_REG2 0x4000046 12283e5343bdSAlex Deucher #define ixD2F3_PCIE_PORT_VC_CNTL 0x4000047 12293e5343bdSAlex Deucher #define ixD2F3_PCIE_PORT_VC_STATUS 0x4000047 12303e5343bdSAlex Deucher #define ixD2F3_PCIE_VC0_RESOURCE_CAP 0x4000048 12313e5343bdSAlex Deucher #define ixD2F3_PCIE_VC0_RESOURCE_CNTL 0x4000049 12323e5343bdSAlex Deucher #define ixD2F3_PCIE_VC0_RESOURCE_STATUS 0x400004a 12333e5343bdSAlex Deucher #define ixD2F3_PCIE_VC1_RESOURCE_CAP 0x400004b 12343e5343bdSAlex Deucher #define ixD2F3_PCIE_VC1_RESOURCE_CNTL 0x400004c 12353e5343bdSAlex Deucher #define ixD2F3_PCIE_VC1_RESOURCE_STATUS 0x400004d 12363e5343bdSAlex Deucher #define ixD2F3_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 0x4000050 12373e5343bdSAlex Deucher #define ixD2F3_PCIE_DEV_SERIAL_NUM_DW1 0x4000051 12383e5343bdSAlex Deucher #define ixD2F3_PCIE_DEV_SERIAL_NUM_DW2 0x4000052 12393e5343bdSAlex Deucher #define ixD2F3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x4000054 12403e5343bdSAlex Deucher #define ixD2F3_PCIE_UNCORR_ERR_STATUS 0x4000055 12413e5343bdSAlex Deucher #define ixD2F3_PCIE_UNCORR_ERR_MASK 0x4000056 12423e5343bdSAlex Deucher #define ixD2F3_PCIE_UNCORR_ERR_SEVERITY 0x4000057 12433e5343bdSAlex Deucher #define ixD2F3_PCIE_CORR_ERR_STATUS 0x4000058 12443e5343bdSAlex Deucher #define ixD2F3_PCIE_CORR_ERR_MASK 0x4000059 12453e5343bdSAlex Deucher #define ixD2F3_PCIE_ADV_ERR_CAP_CNTL 0x400005a 12463e5343bdSAlex Deucher #define ixD2F3_PCIE_HDR_LOG0 0x400005b 12473e5343bdSAlex Deucher #define ixD2F3_PCIE_HDR_LOG1 0x400005c 12483e5343bdSAlex Deucher #define ixD2F3_PCIE_HDR_LOG2 0x400005d 12493e5343bdSAlex Deucher #define ixD2F3_PCIE_HDR_LOG3 0x400005e 12503e5343bdSAlex Deucher #define ixD2F3_PCIE_ROOT_ERR_CMD 0x400005f 12513e5343bdSAlex Deucher #define ixD2F3_PCIE_ROOT_ERR_STATUS 0x4000060 12523e5343bdSAlex Deucher #define ixD2F3_PCIE_ERR_SRC_ID 0x4000061 12533e5343bdSAlex Deucher #define ixD2F3_PCIE_TLP_PREFIX_LOG0 0x4000062 12543e5343bdSAlex Deucher #define ixD2F3_PCIE_TLP_PREFIX_LOG1 0x4000063 12553e5343bdSAlex Deucher #define ixD2F3_PCIE_TLP_PREFIX_LOG2 0x4000064 12563e5343bdSAlex Deucher #define ixD2F3_PCIE_TLP_PREFIX_LOG3 0x4000065 12573e5343bdSAlex Deucher #define ixD2F3_PCIE_SECONDARY_ENH_CAP_LIST 0x400009c 12583e5343bdSAlex Deucher #define ixD2F3_PCIE_LINK_CNTL3 0x400009d 12593e5343bdSAlex Deucher #define ixD2F3_PCIE_LANE_ERROR_STATUS 0x400009e 12603e5343bdSAlex Deucher #define ixD2F3_PCIE_LANE_0_EQUALIZATION_CNTL 0x400009f 12613e5343bdSAlex Deucher #define ixD2F3_PCIE_LANE_1_EQUALIZATION_CNTL 0x400009f 12623e5343bdSAlex Deucher #define ixD2F3_PCIE_LANE_2_EQUALIZATION_CNTL 0x40000a0 12633e5343bdSAlex Deucher #define ixD2F3_PCIE_LANE_3_EQUALIZATION_CNTL 0x40000a0 12643e5343bdSAlex Deucher #define ixD2F3_PCIE_LANE_4_EQUALIZATION_CNTL 0x40000a1 12653e5343bdSAlex Deucher #define ixD2F3_PCIE_LANE_5_EQUALIZATION_CNTL 0x40000a1 12663e5343bdSAlex Deucher #define ixD2F3_PCIE_LANE_6_EQUALIZATION_CNTL 0x40000a2 12673e5343bdSAlex Deucher #define ixD2F3_PCIE_LANE_7_EQUALIZATION_CNTL 0x40000a2 12683e5343bdSAlex Deucher #define ixD2F3_PCIE_LANE_8_EQUALIZATION_CNTL 0x40000a3 12693e5343bdSAlex Deucher #define ixD2F3_PCIE_LANE_9_EQUALIZATION_CNTL 0x40000a3 12703e5343bdSAlex Deucher #define ixD2F3_PCIE_LANE_10_EQUALIZATION_CNTL 0x40000a4 12713e5343bdSAlex Deucher #define ixD2F3_PCIE_LANE_11_EQUALIZATION_CNTL 0x40000a4 12723e5343bdSAlex Deucher #define ixD2F3_PCIE_LANE_12_EQUALIZATION_CNTL 0x40000a5 12733e5343bdSAlex Deucher #define ixD2F3_PCIE_LANE_13_EQUALIZATION_CNTL 0x40000a5 12743e5343bdSAlex Deucher #define ixD2F3_PCIE_LANE_14_EQUALIZATION_CNTL 0x40000a6 12753e5343bdSAlex Deucher #define ixD2F3_PCIE_LANE_15_EQUALIZATION_CNTL 0x40000a6 12763e5343bdSAlex Deucher #define ixD2F3_PCIE_ACS_ENH_CAP_LIST 0x40000a8 12773e5343bdSAlex Deucher #define ixD2F3_PCIE_ACS_CAP 0x40000a9 12783e5343bdSAlex Deucher #define ixD2F3_PCIE_ACS_CNTL 0x40000a9 12793e5343bdSAlex Deucher #define ixD2F3_PCIE_MC_ENH_CAP_LIST 0x40000bc 12803e5343bdSAlex Deucher #define ixD2F3_PCIE_MC_CAP 0x40000bd 12813e5343bdSAlex Deucher #define ixD2F3_PCIE_MC_CNTL 0x40000bd 12823e5343bdSAlex Deucher #define ixD2F3_PCIE_MC_ADDR0 0x40000be 12833e5343bdSAlex Deucher #define ixD2F3_PCIE_MC_ADDR1 0x40000bf 12843e5343bdSAlex Deucher #define ixD2F3_PCIE_MC_RCV0 0x40000c0 12853e5343bdSAlex Deucher #define ixD2F3_PCIE_MC_RCV1 0x40000c1 12863e5343bdSAlex Deucher #define ixD2F3_PCIE_MC_BLOCK_ALL0 0x40000c2 12873e5343bdSAlex Deucher #define ixD2F3_PCIE_MC_BLOCK_ALL1 0x40000c3 12883e5343bdSAlex Deucher #define ixD2F3_PCIE_MC_BLOCK_UNTRANSLATED_0 0x40000c4 12893e5343bdSAlex Deucher #define ixD2F3_PCIE_MC_BLOCK_UNTRANSLATED_1 0x40000c5 12903e5343bdSAlex Deucher #define ixD2F3_PCIE_MC_OVERLAY_BAR0 0x40000c6 12913e5343bdSAlex Deucher #define ixD2F3_PCIE_MC_OVERLAY_BAR1 0x40000c7 12923e5343bdSAlex Deucher #define ixD2F4_PCIE_PORT_INDEX 0x5000038 12933e5343bdSAlex Deucher #define ixD2F4_PCIE_PORT_DATA 0x5000039 12943e5343bdSAlex Deucher #define ixD2F4_PCIEP_RESERVED 0x0 12953e5343bdSAlex Deucher #define ixD2F4_PCIEP_SCRATCH 0x1 12963e5343bdSAlex Deucher #define ixD2F4_PCIEP_HW_DEBUG 0x2 12973e5343bdSAlex Deucher #define ixD2F4_PCIEP_PORT_CNTL 0x10 12983e5343bdSAlex Deucher #define ixD2F4_PCIE_TX_CNTL 0x20 12993e5343bdSAlex Deucher #define ixD2F4_PCIE_TX_REQUESTER_ID 0x21 13003e5343bdSAlex Deucher #define ixD2F4_PCIE_TX_VENDOR_SPECIFIC 0x22 13013e5343bdSAlex Deucher #define ixD2F4_PCIE_TX_REQUEST_NUM_CNTL 0x23 13023e5343bdSAlex Deucher #define ixD2F4_PCIE_TX_SEQ 0x24 13033e5343bdSAlex Deucher #define ixD2F4_PCIE_TX_REPLAY 0x25 13043e5343bdSAlex Deucher #define ixD2F4_PCIE_TX_ACK_LATENCY_LIMIT 0x26 13053e5343bdSAlex Deucher #define ixD2F4_PCIE_TX_CREDITS_ADVT_P 0x30 13063e5343bdSAlex Deucher #define ixD2F4_PCIE_TX_CREDITS_ADVT_NP 0x31 13073e5343bdSAlex Deucher #define ixD2F4_PCIE_TX_CREDITS_ADVT_CPL 0x32 13083e5343bdSAlex Deucher #define ixD2F4_PCIE_TX_CREDITS_INIT_P 0x33 13093e5343bdSAlex Deucher #define ixD2F4_PCIE_TX_CREDITS_INIT_NP 0x34 13103e5343bdSAlex Deucher #define ixD2F4_PCIE_TX_CREDITS_INIT_CPL 0x35 13113e5343bdSAlex Deucher #define ixD2F4_PCIE_TX_CREDITS_STATUS 0x36 13123e5343bdSAlex Deucher #define ixD2F4_PCIE_TX_CREDITS_FCU_THRESHOLD 0x37 13133e5343bdSAlex Deucher #define ixD2F4_PCIE_P_PORT_LANE_STATUS 0x50 13143e5343bdSAlex Deucher #define ixD2F4_PCIE_FC_P 0x60 13153e5343bdSAlex Deucher #define ixD2F4_PCIE_FC_NP 0x61 13163e5343bdSAlex Deucher #define ixD2F4_PCIE_FC_CPL 0x62 13173e5343bdSAlex Deucher #define ixD2F4_PCIE_ERR_CNTL 0x6a 13183e5343bdSAlex Deucher #define ixD2F4_PCIE_RX_CNTL 0x70 13193e5343bdSAlex Deucher #define ixD2F4_PCIE_RX_EXPECTED_SEQNUM 0x71 13203e5343bdSAlex Deucher #define ixD2F4_PCIE_RX_VENDOR_SPECIFIC 0x72 13213e5343bdSAlex Deucher #define ixD2F4_PCIE_RX_CNTL3 0x74 13223e5343bdSAlex Deucher #define ixD2F4_PCIE_RX_CREDITS_ALLOCATED_P 0x80 13233e5343bdSAlex Deucher #define ixD2F4_PCIE_RX_CREDITS_ALLOCATED_NP 0x81 13243e5343bdSAlex Deucher #define ixD2F4_PCIE_RX_CREDITS_ALLOCATED_CPL 0x82 13253e5343bdSAlex Deucher #define ixD2F4_PCIEP_ERROR_INJECT_PHYSICAL 0x83 13263e5343bdSAlex Deucher #define ixD2F4_PCIEP_ERROR_INJECT_TRANSACTION 0x84 13273e5343bdSAlex Deucher #define ixD2F4_PCIE_LC_CNTL 0xa0 13283e5343bdSAlex Deucher #define ixD2F4_PCIE_LC_CNTL2 0xb1 13293e5343bdSAlex Deucher #define ixD2F4_PCIE_LC_CNTL3 0xb5 13303e5343bdSAlex Deucher #define ixD2F4_PCIE_LC_CNTL4 0xb6 13313e5343bdSAlex Deucher #define ixD2F4_PCIE_LC_CNTL5 0xb7 13323e5343bdSAlex Deucher #define ixD2F4_PCIE_LC_CNTL6 0xbb 13333e5343bdSAlex Deucher #define ixD2F4_PCIE_LC_BW_CHANGE_CNTL 0xb2 13343e5343bdSAlex Deucher #define ixD2F4_PCIE_LC_TRAINING_CNTL 0xa1 13353e5343bdSAlex Deucher #define ixD2F4_PCIE_LC_LINK_WIDTH_CNTL 0xa2 13363e5343bdSAlex Deucher #define ixD2F4_PCIE_LC_N_FTS_CNTL 0xa3 13373e5343bdSAlex Deucher #define ixD2F4_PCIE_LC_SPEED_CNTL 0xa4 13383e5343bdSAlex Deucher #define ixD2F4_PCIE_LC_CDR_CNTL 0xb3 13393e5343bdSAlex Deucher #define ixD2F4_PCIE_LC_LANE_CNTL 0xb4 13403e5343bdSAlex Deucher #define ixD2F4_PCIE_LC_FORCE_COEFF 0xb8 13413e5343bdSAlex Deucher #define ixD2F4_PCIE_LC_BEST_EQ_SETTINGS 0xb9 13423e5343bdSAlex Deucher #define ixD2F4_PCIE_LC_FORCE_EQ_REQ_COEFF 0xba 13433e5343bdSAlex Deucher #define ixD2F4_PCIE_LC_STATE0 0xa5 13443e5343bdSAlex Deucher #define ixD2F4_PCIE_LC_STATE1 0xa6 13453e5343bdSAlex Deucher #define ixD2F4_PCIE_LC_STATE2 0xa7 13463e5343bdSAlex Deucher #define ixD2F4_PCIE_LC_STATE3 0xa8 13473e5343bdSAlex Deucher #define ixD2F4_PCIE_LC_STATE4 0xa9 13483e5343bdSAlex Deucher #define ixD2F4_PCIE_LC_STATE5 0xaa 13493e5343bdSAlex Deucher #define ixD2F4_PCIEP_STRAP_LC 0xc0 13503e5343bdSAlex Deucher #define ixD2F4_PCIEP_STRAP_MISC 0xc1 13513e5343bdSAlex Deucher #define ixD2F4_PCIEP_BCH_ECC_CNTL 0xd0 13523e5343bdSAlex Deucher #define ixD2F4_PCIEP_HPGI_PRIVATE 0xd2 13533e5343bdSAlex Deucher #define ixD2F4_PCIEP_HPGI 0xda 13543e5343bdSAlex Deucher #define ixD2F4_VENDOR_ID 0x5000000 13553e5343bdSAlex Deucher #define ixD2F4_DEVICE_ID 0x5000000 13563e5343bdSAlex Deucher #define ixD2F4_COMMAND 0x5000001 13573e5343bdSAlex Deucher #define ixD2F4_STATUS 0x5000001 13583e5343bdSAlex Deucher #define ixD2F4_REVISION_ID 0x5000002 13593e5343bdSAlex Deucher #define ixD2F4_PROG_INTERFACE 0x5000002 13603e5343bdSAlex Deucher #define ixD2F4_SUB_CLASS 0x5000002 13613e5343bdSAlex Deucher #define ixD2F4_BASE_CLASS 0x5000002 13623e5343bdSAlex Deucher #define ixD2F4_CACHE_LINE 0x5000003 13633e5343bdSAlex Deucher #define ixD2F4_LATENCY 0x5000003 13643e5343bdSAlex Deucher #define ixD2F4_HEADER 0x5000003 13653e5343bdSAlex Deucher #define ixD2F4_BIST 0x5000003 13663e5343bdSAlex Deucher #define ixD2F4_SUB_BUS_NUMBER_LATENCY 0x5000006 13673e5343bdSAlex Deucher #define ixD2F4_IO_BASE_LIMIT 0x5000007 13683e5343bdSAlex Deucher #define ixD2F4_SECONDARY_STATUS 0x5000007 13693e5343bdSAlex Deucher #define ixD2F4_MEM_BASE_LIMIT 0x5000008 13703e5343bdSAlex Deucher #define ixD2F4_PREF_BASE_LIMIT 0x5000009 13713e5343bdSAlex Deucher #define ixD2F4_PREF_BASE_UPPER 0x500000a 13723e5343bdSAlex Deucher #define ixD2F4_PREF_LIMIT_UPPER 0x500000b 13733e5343bdSAlex Deucher #define ixD2F4_IO_BASE_LIMIT_HI 0x500000c 13743e5343bdSAlex Deucher #define ixD2F4_IRQ_BRIDGE_CNTL 0x500000f 13753e5343bdSAlex Deucher #define ixD2F4_CAP_PTR 0x500000d 13763e5343bdSAlex Deucher #define ixD2F4_INTERRUPT_LINE 0x500000f 13773e5343bdSAlex Deucher #define ixD2F4_INTERRUPT_PIN 0x500000f 13783e5343bdSAlex Deucher #define ixD2F4_EXT_BRIDGE_CNTL 0x5000010 13793e5343bdSAlex Deucher #define ixD2F4_PMI_CAP_LIST 0x5000014 13803e5343bdSAlex Deucher #define ixD2F4_PMI_CAP 0x5000014 13813e5343bdSAlex Deucher #define ixD2F4_PMI_STATUS_CNTL 0x5000015 13823e5343bdSAlex Deucher #define ixD2F4_PCIE_CAP_LIST 0x5000016 13833e5343bdSAlex Deucher #define ixD2F4_PCIE_CAP 0x5000016 13843e5343bdSAlex Deucher #define ixD2F4_DEVICE_CAP 0x5000017 13853e5343bdSAlex Deucher #define ixD2F4_DEVICE_CNTL 0x5000018 13863e5343bdSAlex Deucher #define ixD2F4_DEVICE_STATUS 0x5000018 13873e5343bdSAlex Deucher #define ixD2F4_LINK_CAP 0x5000019 13883e5343bdSAlex Deucher #define ixD2F4_LINK_CNTL 0x500001a 13893e5343bdSAlex Deucher #define ixD2F4_LINK_STATUS 0x500001a 13903e5343bdSAlex Deucher #define ixD2F4_SLOT_CAP 0x500001b 13913e5343bdSAlex Deucher #define ixD2F4_SLOT_CNTL 0x500001c 13923e5343bdSAlex Deucher #define ixD2F4_SLOT_STATUS 0x500001c 13933e5343bdSAlex Deucher #define ixD2F4_ROOT_CNTL 0x500001d 13943e5343bdSAlex Deucher #define ixD2F4_ROOT_CAP 0x500001d 13953e5343bdSAlex Deucher #define ixD2F4_ROOT_STATUS 0x500001e 13963e5343bdSAlex Deucher #define ixD2F4_DEVICE_CAP2 0x500001f 13973e5343bdSAlex Deucher #define ixD2F4_DEVICE_CNTL2 0x5000020 13983e5343bdSAlex Deucher #define ixD2F4_DEVICE_STATUS2 0x5000020 13993e5343bdSAlex Deucher #define ixD2F4_LINK_CAP2 0x5000021 14003e5343bdSAlex Deucher #define ixD2F4_LINK_CNTL2 0x5000022 14013e5343bdSAlex Deucher #define ixD2F4_LINK_STATUS2 0x5000022 14023e5343bdSAlex Deucher #define ixD2F4_SLOT_CAP2 0x5000023 14033e5343bdSAlex Deucher #define ixD2F4_SLOT_CNTL2 0x5000024 14043e5343bdSAlex Deucher #define ixD2F4_SLOT_STATUS2 0x5000024 14053e5343bdSAlex Deucher #define ixD2F4_MSI_CAP_LIST 0x5000028 14063e5343bdSAlex Deucher #define ixD2F4_MSI_MSG_CNTL 0x5000028 14073e5343bdSAlex Deucher #define ixD2F4_MSI_MSG_ADDR_LO 0x5000029 14083e5343bdSAlex Deucher #define ixD2F4_MSI_MSG_ADDR_HI 0x500002a 14093e5343bdSAlex Deucher #define ixD2F4_MSI_MSG_DATA_64 0x500002b 14103e5343bdSAlex Deucher #define ixD2F4_MSI_MSG_DATA 0x500002a 14113e5343bdSAlex Deucher #define ixD2F4_SSID_CAP_LIST 0x5000030 14123e5343bdSAlex Deucher #define ixD2F4_SSID_CAP 0x5000031 14133e5343bdSAlex Deucher #define ixD2F4_MSI_MAP_CAP_LIST 0x5000032 14143e5343bdSAlex Deucher #define ixD2F4_MSI_MAP_CAP 0x5000032 14153e5343bdSAlex Deucher #define ixD2F4_MSI_MAP_ADDR_LO 0x5000033 14163e5343bdSAlex Deucher #define ixD2F4_MSI_MAP_ADDR_HI 0x5000034 14173e5343bdSAlex Deucher #define ixD2F4_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x5000040 14183e5343bdSAlex Deucher #define ixD2F4_PCIE_VENDOR_SPECIFIC_HDR 0x5000041 14193e5343bdSAlex Deucher #define ixD2F4_PCIE_VENDOR_SPECIFIC1 0x5000042 14203e5343bdSAlex Deucher #define ixD2F4_PCIE_VENDOR_SPECIFIC2 0x5000043 14213e5343bdSAlex Deucher #define ixD2F4_PCIE_VC_ENH_CAP_LIST 0x5000044 14223e5343bdSAlex Deucher #define ixD2F4_PCIE_PORT_VC_CAP_REG1 0x5000045 14233e5343bdSAlex Deucher #define ixD2F4_PCIE_PORT_VC_CAP_REG2 0x5000046 14243e5343bdSAlex Deucher #define ixD2F4_PCIE_PORT_VC_CNTL 0x5000047 14253e5343bdSAlex Deucher #define ixD2F4_PCIE_PORT_VC_STATUS 0x5000047 14263e5343bdSAlex Deucher #define ixD2F4_PCIE_VC0_RESOURCE_CAP 0x5000048 14273e5343bdSAlex Deucher #define ixD2F4_PCIE_VC0_RESOURCE_CNTL 0x5000049 14283e5343bdSAlex Deucher #define ixD2F4_PCIE_VC0_RESOURCE_STATUS 0x500004a 14293e5343bdSAlex Deucher #define ixD2F4_PCIE_VC1_RESOURCE_CAP 0x500004b 14303e5343bdSAlex Deucher #define ixD2F4_PCIE_VC1_RESOURCE_CNTL 0x500004c 14313e5343bdSAlex Deucher #define ixD2F4_PCIE_VC1_RESOURCE_STATUS 0x500004d 14323e5343bdSAlex Deucher #define ixD2F4_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 0x5000050 14333e5343bdSAlex Deucher #define ixD2F4_PCIE_DEV_SERIAL_NUM_DW1 0x5000051 14343e5343bdSAlex Deucher #define ixD2F4_PCIE_DEV_SERIAL_NUM_DW2 0x5000052 14353e5343bdSAlex Deucher #define ixD2F4_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x5000054 14363e5343bdSAlex Deucher #define ixD2F4_PCIE_UNCORR_ERR_STATUS 0x5000055 14373e5343bdSAlex Deucher #define ixD2F4_PCIE_UNCORR_ERR_MASK 0x5000056 14383e5343bdSAlex Deucher #define ixD2F4_PCIE_UNCORR_ERR_SEVERITY 0x5000057 14393e5343bdSAlex Deucher #define ixD2F4_PCIE_CORR_ERR_STATUS 0x5000058 14403e5343bdSAlex Deucher #define ixD2F4_PCIE_CORR_ERR_MASK 0x5000059 14413e5343bdSAlex Deucher #define ixD2F4_PCIE_ADV_ERR_CAP_CNTL 0x500005a 14423e5343bdSAlex Deucher #define ixD2F4_PCIE_HDR_LOG0 0x500005b 14433e5343bdSAlex Deucher #define ixD2F4_PCIE_HDR_LOG1 0x500005c 14443e5343bdSAlex Deucher #define ixD2F4_PCIE_HDR_LOG2 0x500005d 14453e5343bdSAlex Deucher #define ixD2F4_PCIE_HDR_LOG3 0x500005e 14463e5343bdSAlex Deucher #define ixD2F4_PCIE_ROOT_ERR_CMD 0x500005f 14473e5343bdSAlex Deucher #define ixD2F4_PCIE_ROOT_ERR_STATUS 0x5000060 14483e5343bdSAlex Deucher #define ixD2F4_PCIE_ERR_SRC_ID 0x5000061 14493e5343bdSAlex Deucher #define ixD2F4_PCIE_TLP_PREFIX_LOG0 0x5000062 14503e5343bdSAlex Deucher #define ixD2F4_PCIE_TLP_PREFIX_LOG1 0x5000063 14513e5343bdSAlex Deucher #define ixD2F4_PCIE_TLP_PREFIX_LOG2 0x5000064 14523e5343bdSAlex Deucher #define ixD2F4_PCIE_TLP_PREFIX_LOG3 0x5000065 14533e5343bdSAlex Deucher #define ixD2F4_PCIE_SECONDARY_ENH_CAP_LIST 0x500009c 14543e5343bdSAlex Deucher #define ixD2F4_PCIE_LINK_CNTL3 0x500009d 14553e5343bdSAlex Deucher #define ixD2F4_PCIE_LANE_ERROR_STATUS 0x500009e 14563e5343bdSAlex Deucher #define ixD2F4_PCIE_LANE_0_EQUALIZATION_CNTL 0x500009f 14573e5343bdSAlex Deucher #define ixD2F4_PCIE_LANE_1_EQUALIZATION_CNTL 0x500009f 14583e5343bdSAlex Deucher #define ixD2F4_PCIE_LANE_2_EQUALIZATION_CNTL 0x50000a0 14593e5343bdSAlex Deucher #define ixD2F4_PCIE_LANE_3_EQUALIZATION_CNTL 0x50000a0 14603e5343bdSAlex Deucher #define ixD2F4_PCIE_LANE_4_EQUALIZATION_CNTL 0x50000a1 14613e5343bdSAlex Deucher #define ixD2F4_PCIE_LANE_5_EQUALIZATION_CNTL 0x50000a1 14623e5343bdSAlex Deucher #define ixD2F4_PCIE_LANE_6_EQUALIZATION_CNTL 0x50000a2 14633e5343bdSAlex Deucher #define ixD2F4_PCIE_LANE_7_EQUALIZATION_CNTL 0x50000a2 14643e5343bdSAlex Deucher #define ixD2F4_PCIE_LANE_8_EQUALIZATION_CNTL 0x50000a3 14653e5343bdSAlex Deucher #define ixD2F4_PCIE_LANE_9_EQUALIZATION_CNTL 0x50000a3 14663e5343bdSAlex Deucher #define ixD2F4_PCIE_LANE_10_EQUALIZATION_CNTL 0x50000a4 14673e5343bdSAlex Deucher #define ixD2F4_PCIE_LANE_11_EQUALIZATION_CNTL 0x50000a4 14683e5343bdSAlex Deucher #define ixD2F4_PCIE_LANE_12_EQUALIZATION_CNTL 0x50000a5 14693e5343bdSAlex Deucher #define ixD2F4_PCIE_LANE_13_EQUALIZATION_CNTL 0x50000a5 14703e5343bdSAlex Deucher #define ixD2F4_PCIE_LANE_14_EQUALIZATION_CNTL 0x50000a6 14713e5343bdSAlex Deucher #define ixD2F4_PCIE_LANE_15_EQUALIZATION_CNTL 0x50000a6 14723e5343bdSAlex Deucher #define ixD2F4_PCIE_ACS_ENH_CAP_LIST 0x50000a8 14733e5343bdSAlex Deucher #define ixD2F4_PCIE_ACS_CAP 0x50000a9 14743e5343bdSAlex Deucher #define ixD2F4_PCIE_ACS_CNTL 0x50000a9 14753e5343bdSAlex Deucher #define ixD2F4_PCIE_MC_ENH_CAP_LIST 0x50000bc 14763e5343bdSAlex Deucher #define ixD2F4_PCIE_MC_CAP 0x50000bd 14773e5343bdSAlex Deucher #define ixD2F4_PCIE_MC_CNTL 0x50000bd 14783e5343bdSAlex Deucher #define ixD2F4_PCIE_MC_ADDR0 0x50000be 14793e5343bdSAlex Deucher #define ixD2F4_PCIE_MC_ADDR1 0x50000bf 14803e5343bdSAlex Deucher #define ixD2F4_PCIE_MC_RCV0 0x50000c0 14813e5343bdSAlex Deucher #define ixD2F4_PCIE_MC_RCV1 0x50000c1 14823e5343bdSAlex Deucher #define ixD2F4_PCIE_MC_BLOCK_ALL0 0x50000c2 14833e5343bdSAlex Deucher #define ixD2F4_PCIE_MC_BLOCK_ALL1 0x50000c3 14843e5343bdSAlex Deucher #define ixD2F4_PCIE_MC_BLOCK_UNTRANSLATED_0 0x50000c4 14853e5343bdSAlex Deucher #define ixD2F4_PCIE_MC_BLOCK_UNTRANSLATED_1 0x50000c5 14863e5343bdSAlex Deucher #define ixD2F4_PCIE_MC_OVERLAY_BAR0 0x50000c6 14873e5343bdSAlex Deucher #define ixD2F4_PCIE_MC_OVERLAY_BAR1 0x50000c7 14883e5343bdSAlex Deucher #define ixD2F5_PCIE_PORT_INDEX 0x6000038 14893e5343bdSAlex Deucher #define ixD2F5_PCIE_PORT_DATA 0x6000039 14903e5343bdSAlex Deucher #define ixD2F5_PCIEP_RESERVED 0x0 14913e5343bdSAlex Deucher #define ixD2F5_PCIEP_SCRATCH 0x1 14923e5343bdSAlex Deucher #define ixD2F5_PCIEP_HW_DEBUG 0x2 14933e5343bdSAlex Deucher #define ixD2F5_PCIEP_PORT_CNTL 0x10 14943e5343bdSAlex Deucher #define ixD2F5_PCIE_TX_CNTL 0x20 14953e5343bdSAlex Deucher #define ixD2F5_PCIE_TX_REQUESTER_ID 0x21 14963e5343bdSAlex Deucher #define ixD2F5_PCIE_TX_VENDOR_SPECIFIC 0x22 14973e5343bdSAlex Deucher #define ixD2F5_PCIE_TX_REQUEST_NUM_CNTL 0x23 14983e5343bdSAlex Deucher #define ixD2F5_PCIE_TX_SEQ 0x24 14993e5343bdSAlex Deucher #define ixD2F5_PCIE_TX_REPLAY 0x25 15003e5343bdSAlex Deucher #define ixD2F5_PCIE_TX_ACK_LATENCY_LIMIT 0x26 15013e5343bdSAlex Deucher #define ixD2F5_PCIE_TX_CREDITS_ADVT_P 0x30 15023e5343bdSAlex Deucher #define ixD2F5_PCIE_TX_CREDITS_ADVT_NP 0x31 15033e5343bdSAlex Deucher #define ixD2F5_PCIE_TX_CREDITS_ADVT_CPL 0x32 15043e5343bdSAlex Deucher #define ixD2F5_PCIE_TX_CREDITS_INIT_P 0x33 15053e5343bdSAlex Deucher #define ixD2F5_PCIE_TX_CREDITS_INIT_NP 0x34 15063e5343bdSAlex Deucher #define ixD2F5_PCIE_TX_CREDITS_INIT_CPL 0x35 15073e5343bdSAlex Deucher #define ixD2F5_PCIE_TX_CREDITS_STATUS 0x36 15083e5343bdSAlex Deucher #define ixD2F5_PCIE_TX_CREDITS_FCU_THRESHOLD 0x37 15093e5343bdSAlex Deucher #define ixD2F5_PCIE_P_PORT_LANE_STATUS 0x50 15103e5343bdSAlex Deucher #define ixD2F5_PCIE_FC_P 0x60 15113e5343bdSAlex Deucher #define ixD2F5_PCIE_FC_NP 0x61 15123e5343bdSAlex Deucher #define ixD2F5_PCIE_FC_CPL 0x62 15133e5343bdSAlex Deucher #define ixD2F5_PCIE_ERR_CNTL 0x6a 15143e5343bdSAlex Deucher #define ixD2F5_PCIE_RX_CNTL 0x70 15153e5343bdSAlex Deucher #define ixD2F5_PCIE_RX_EXPECTED_SEQNUM 0x71 15163e5343bdSAlex Deucher #define ixD2F5_PCIE_RX_VENDOR_SPECIFIC 0x72 15173e5343bdSAlex Deucher #define ixD2F5_PCIE_RX_CNTL3 0x74 15183e5343bdSAlex Deucher #define ixD2F5_PCIE_RX_CREDITS_ALLOCATED_P 0x80 15193e5343bdSAlex Deucher #define ixD2F5_PCIE_RX_CREDITS_ALLOCATED_NP 0x81 15203e5343bdSAlex Deucher #define ixD2F5_PCIE_RX_CREDITS_ALLOCATED_CPL 0x82 15213e5343bdSAlex Deucher #define ixD2F5_PCIEP_ERROR_INJECT_PHYSICAL 0x83 15223e5343bdSAlex Deucher #define ixD2F5_PCIEP_ERROR_INJECT_TRANSACTION 0x84 15233e5343bdSAlex Deucher #define ixD2F5_PCIE_LC_CNTL 0xa0 15243e5343bdSAlex Deucher #define ixD2F5_PCIE_LC_CNTL2 0xb1 15253e5343bdSAlex Deucher #define ixD2F5_PCIE_LC_CNTL3 0xb5 15263e5343bdSAlex Deucher #define ixD2F5_PCIE_LC_CNTL4 0xb6 15273e5343bdSAlex Deucher #define ixD2F5_PCIE_LC_CNTL5 0xb7 15283e5343bdSAlex Deucher #define ixD2F5_PCIE_LC_CNTL6 0xbb 15293e5343bdSAlex Deucher #define ixD2F5_PCIE_LC_BW_CHANGE_CNTL 0xb2 15303e5343bdSAlex Deucher #define ixD2F5_PCIE_LC_TRAINING_CNTL 0xa1 15313e5343bdSAlex Deucher #define ixD2F5_PCIE_LC_LINK_WIDTH_CNTL 0xa2 15323e5343bdSAlex Deucher #define ixD2F5_PCIE_LC_N_FTS_CNTL 0xa3 15333e5343bdSAlex Deucher #define ixD2F5_PCIE_LC_SPEED_CNTL 0xa4 15343e5343bdSAlex Deucher #define ixD2F5_PCIE_LC_CDR_CNTL 0xb3 15353e5343bdSAlex Deucher #define ixD2F5_PCIE_LC_LANE_CNTL 0xb4 15363e5343bdSAlex Deucher #define ixD2F5_PCIE_LC_FORCE_COEFF 0xb8 15373e5343bdSAlex Deucher #define ixD2F5_PCIE_LC_BEST_EQ_SETTINGS 0xb9 15383e5343bdSAlex Deucher #define ixD2F5_PCIE_LC_FORCE_EQ_REQ_COEFF 0xba 15393e5343bdSAlex Deucher #define ixD2F5_PCIE_LC_STATE0 0xa5 15403e5343bdSAlex Deucher #define ixD2F5_PCIE_LC_STATE1 0xa6 15413e5343bdSAlex Deucher #define ixD2F5_PCIE_LC_STATE2 0xa7 15423e5343bdSAlex Deucher #define ixD2F5_PCIE_LC_STATE3 0xa8 15433e5343bdSAlex Deucher #define ixD2F5_PCIE_LC_STATE4 0xa9 15443e5343bdSAlex Deucher #define ixD2F5_PCIE_LC_STATE5 0xaa 15453e5343bdSAlex Deucher #define ixD2F5_PCIEP_STRAP_LC 0xc0 15463e5343bdSAlex Deucher #define ixD2F5_PCIEP_STRAP_MISC 0xc1 15473e5343bdSAlex Deucher #define ixD2F5_PCIEP_BCH_ECC_CNTL 0xd0 15483e5343bdSAlex Deucher #define ixD2F5_PCIEP_HPGI_PRIVATE 0xd2 15493e5343bdSAlex Deucher #define ixD2F5_PCIEP_HPGI 0xda 15503e5343bdSAlex Deucher #define ixD2F5_VENDOR_ID 0x6000000 15513e5343bdSAlex Deucher #define ixD2F5_DEVICE_ID 0x6000000 15523e5343bdSAlex Deucher #define ixD2F5_COMMAND 0x6000001 15533e5343bdSAlex Deucher #define ixD2F5_STATUS 0x6000001 15543e5343bdSAlex Deucher #define ixD2F5_REVISION_ID 0x6000002 15553e5343bdSAlex Deucher #define ixD2F5_PROG_INTERFACE 0x6000002 15563e5343bdSAlex Deucher #define ixD2F5_SUB_CLASS 0x6000002 15573e5343bdSAlex Deucher #define ixD2F5_BASE_CLASS 0x6000002 15583e5343bdSAlex Deucher #define ixD2F5_CACHE_LINE 0x6000003 15593e5343bdSAlex Deucher #define ixD2F5_LATENCY 0x6000003 15603e5343bdSAlex Deucher #define ixD2F5_HEADER 0x6000003 15613e5343bdSAlex Deucher #define ixD2F5_BIST 0x6000003 15623e5343bdSAlex Deucher #define ixD2F5_SUB_BUS_NUMBER_LATENCY 0x6000006 15633e5343bdSAlex Deucher #define ixD2F5_IO_BASE_LIMIT 0x6000007 15643e5343bdSAlex Deucher #define ixD2F5_SECONDARY_STATUS 0x6000007 15653e5343bdSAlex Deucher #define ixD2F5_MEM_BASE_LIMIT 0x6000008 15663e5343bdSAlex Deucher #define ixD2F5_PREF_BASE_LIMIT 0x6000009 15673e5343bdSAlex Deucher #define ixD2F5_PREF_BASE_UPPER 0x600000a 15683e5343bdSAlex Deucher #define ixD2F5_PREF_LIMIT_UPPER 0x600000b 15693e5343bdSAlex Deucher #define ixD2F5_IO_BASE_LIMIT_HI 0x600000c 15703e5343bdSAlex Deucher #define ixD2F5_IRQ_BRIDGE_CNTL 0x600000f 15713e5343bdSAlex Deucher #define ixD2F5_CAP_PTR 0x600000d 15723e5343bdSAlex Deucher #define ixD2F5_INTERRUPT_LINE 0x600000f 15733e5343bdSAlex Deucher #define ixD2F5_INTERRUPT_PIN 0x600000f 15743e5343bdSAlex Deucher #define ixD2F5_EXT_BRIDGE_CNTL 0x6000010 15753e5343bdSAlex Deucher #define ixD2F5_PMI_CAP_LIST 0x6000014 15763e5343bdSAlex Deucher #define ixD2F5_PMI_CAP 0x6000014 15773e5343bdSAlex Deucher #define ixD2F5_PMI_STATUS_CNTL 0x6000015 15783e5343bdSAlex Deucher #define ixD2F5_PCIE_CAP_LIST 0x6000016 15793e5343bdSAlex Deucher #define ixD2F5_PCIE_CAP 0x6000016 15803e5343bdSAlex Deucher #define ixD2F5_DEVICE_CAP 0x6000017 15813e5343bdSAlex Deucher #define ixD2F5_DEVICE_CNTL 0x6000018 15823e5343bdSAlex Deucher #define ixD2F5_DEVICE_STATUS 0x6000018 15833e5343bdSAlex Deucher #define ixD2F5_LINK_CAP 0x6000019 15843e5343bdSAlex Deucher #define ixD2F5_LINK_CNTL 0x600001a 15853e5343bdSAlex Deucher #define ixD2F5_LINK_STATUS 0x600001a 15863e5343bdSAlex Deucher #define ixD2F5_SLOT_CAP 0x600001b 15873e5343bdSAlex Deucher #define ixD2F5_SLOT_CNTL 0x600001c 15883e5343bdSAlex Deucher #define ixD2F5_SLOT_STATUS 0x600001c 15893e5343bdSAlex Deucher #define ixD2F5_ROOT_CNTL 0x600001d 15903e5343bdSAlex Deucher #define ixD2F5_ROOT_CAP 0x600001d 15913e5343bdSAlex Deucher #define ixD2F5_ROOT_STATUS 0x600001e 15923e5343bdSAlex Deucher #define ixD2F5_DEVICE_CAP2 0x600001f 15933e5343bdSAlex Deucher #define ixD2F5_DEVICE_CNTL2 0x6000020 15943e5343bdSAlex Deucher #define ixD2F5_DEVICE_STATUS2 0x6000020 15953e5343bdSAlex Deucher #define ixD2F5_LINK_CAP2 0x6000021 15963e5343bdSAlex Deucher #define ixD2F5_LINK_CNTL2 0x6000022 15973e5343bdSAlex Deucher #define ixD2F5_LINK_STATUS2 0x6000022 15983e5343bdSAlex Deucher #define ixD2F5_SLOT_CAP2 0x6000023 15993e5343bdSAlex Deucher #define ixD2F5_SLOT_CNTL2 0x6000024 16003e5343bdSAlex Deucher #define ixD2F5_SLOT_STATUS2 0x6000024 16013e5343bdSAlex Deucher #define ixD2F5_MSI_CAP_LIST 0x6000028 16023e5343bdSAlex Deucher #define ixD2F5_MSI_MSG_CNTL 0x6000028 16033e5343bdSAlex Deucher #define ixD2F5_MSI_MSG_ADDR_LO 0x6000029 16043e5343bdSAlex Deucher #define ixD2F5_MSI_MSG_ADDR_HI 0x600002a 16053e5343bdSAlex Deucher #define ixD2F5_MSI_MSG_DATA_64 0x600002b 16063e5343bdSAlex Deucher #define ixD2F5_MSI_MSG_DATA 0x600002a 16073e5343bdSAlex Deucher #define ixD2F5_SSID_CAP_LIST 0x6000030 16083e5343bdSAlex Deucher #define ixD2F5_SSID_CAP 0x6000031 16093e5343bdSAlex Deucher #define ixD2F5_MSI_MAP_CAP_LIST 0x6000032 16103e5343bdSAlex Deucher #define ixD2F5_MSI_MAP_CAP 0x6000032 16113e5343bdSAlex Deucher #define ixD2F5_MSI_MAP_ADDR_LO 0x6000033 16123e5343bdSAlex Deucher #define ixD2F5_MSI_MAP_ADDR_HI 0x6000034 16133e5343bdSAlex Deucher #define ixD2F5_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x6000040 16143e5343bdSAlex Deucher #define ixD2F5_PCIE_VENDOR_SPECIFIC_HDR 0x6000041 16153e5343bdSAlex Deucher #define ixD2F5_PCIE_VENDOR_SPECIFIC1 0x6000042 16163e5343bdSAlex Deucher #define ixD2F5_PCIE_VENDOR_SPECIFIC2 0x6000043 16173e5343bdSAlex Deucher #define ixD2F5_PCIE_VC_ENH_CAP_LIST 0x6000044 16183e5343bdSAlex Deucher #define ixD2F5_PCIE_PORT_VC_CAP_REG1 0x6000045 16193e5343bdSAlex Deucher #define ixD2F5_PCIE_PORT_VC_CAP_REG2 0x6000046 16203e5343bdSAlex Deucher #define ixD2F5_PCIE_PORT_VC_CNTL 0x6000047 16213e5343bdSAlex Deucher #define ixD2F5_PCIE_PORT_VC_STATUS 0x6000047 16223e5343bdSAlex Deucher #define ixD2F5_PCIE_VC0_RESOURCE_CAP 0x6000048 16233e5343bdSAlex Deucher #define ixD2F5_PCIE_VC0_RESOURCE_CNTL 0x6000049 16243e5343bdSAlex Deucher #define ixD2F5_PCIE_VC0_RESOURCE_STATUS 0x600004a 16253e5343bdSAlex Deucher #define ixD2F5_PCIE_VC1_RESOURCE_CAP 0x600004b 16263e5343bdSAlex Deucher #define ixD2F5_PCIE_VC1_RESOURCE_CNTL 0x600004c 16273e5343bdSAlex Deucher #define ixD2F5_PCIE_VC1_RESOURCE_STATUS 0x600004d 16283e5343bdSAlex Deucher #define ixD2F5_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 0x6000050 16293e5343bdSAlex Deucher #define ixD2F5_PCIE_DEV_SERIAL_NUM_DW1 0x6000051 16303e5343bdSAlex Deucher #define ixD2F5_PCIE_DEV_SERIAL_NUM_DW2 0x6000052 16313e5343bdSAlex Deucher #define ixD2F5_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x6000054 16323e5343bdSAlex Deucher #define ixD2F5_PCIE_UNCORR_ERR_STATUS 0x6000055 16333e5343bdSAlex Deucher #define ixD2F5_PCIE_UNCORR_ERR_MASK 0x6000056 16343e5343bdSAlex Deucher #define ixD2F5_PCIE_UNCORR_ERR_SEVERITY 0x6000057 16353e5343bdSAlex Deucher #define ixD2F5_PCIE_CORR_ERR_STATUS 0x6000058 16363e5343bdSAlex Deucher #define ixD2F5_PCIE_CORR_ERR_MASK 0x6000059 16373e5343bdSAlex Deucher #define ixD2F5_PCIE_ADV_ERR_CAP_CNTL 0x600005a 16383e5343bdSAlex Deucher #define ixD2F5_PCIE_HDR_LOG0 0x600005b 16393e5343bdSAlex Deucher #define ixD2F5_PCIE_HDR_LOG1 0x600005c 16403e5343bdSAlex Deucher #define ixD2F5_PCIE_HDR_LOG2 0x600005d 16413e5343bdSAlex Deucher #define ixD2F5_PCIE_HDR_LOG3 0x600005e 16423e5343bdSAlex Deucher #define ixD2F5_PCIE_ROOT_ERR_CMD 0x600005f 16433e5343bdSAlex Deucher #define ixD2F5_PCIE_ROOT_ERR_STATUS 0x6000060 16443e5343bdSAlex Deucher #define ixD2F5_PCIE_ERR_SRC_ID 0x6000061 16453e5343bdSAlex Deucher #define ixD2F5_PCIE_TLP_PREFIX_LOG0 0x6000062 16463e5343bdSAlex Deucher #define ixD2F5_PCIE_TLP_PREFIX_LOG1 0x6000063 16473e5343bdSAlex Deucher #define ixD2F5_PCIE_TLP_PREFIX_LOG2 0x6000064 16483e5343bdSAlex Deucher #define ixD2F5_PCIE_TLP_PREFIX_LOG3 0x6000065 16493e5343bdSAlex Deucher #define ixD2F5_PCIE_SECONDARY_ENH_CAP_LIST 0x600009c 16503e5343bdSAlex Deucher #define ixD2F5_PCIE_LINK_CNTL3 0x600009d 16513e5343bdSAlex Deucher #define ixD2F5_PCIE_LANE_ERROR_STATUS 0x600009e 16523e5343bdSAlex Deucher #define ixD2F5_PCIE_LANE_0_EQUALIZATION_CNTL 0x600009f 16533e5343bdSAlex Deucher #define ixD2F5_PCIE_LANE_1_EQUALIZATION_CNTL 0x600009f 16543e5343bdSAlex Deucher #define ixD2F5_PCIE_LANE_2_EQUALIZATION_CNTL 0x60000a0 16553e5343bdSAlex Deucher #define ixD2F5_PCIE_LANE_3_EQUALIZATION_CNTL 0x60000a0 16563e5343bdSAlex Deucher #define ixD2F5_PCIE_LANE_4_EQUALIZATION_CNTL 0x60000a1 16573e5343bdSAlex Deucher #define ixD2F5_PCIE_LANE_5_EQUALIZATION_CNTL 0x60000a1 16583e5343bdSAlex Deucher #define ixD2F5_PCIE_LANE_6_EQUALIZATION_CNTL 0x60000a2 16593e5343bdSAlex Deucher #define ixD2F5_PCIE_LANE_7_EQUALIZATION_CNTL 0x60000a2 16603e5343bdSAlex Deucher #define ixD2F5_PCIE_LANE_8_EQUALIZATION_CNTL 0x60000a3 16613e5343bdSAlex Deucher #define ixD2F5_PCIE_LANE_9_EQUALIZATION_CNTL 0x60000a3 16623e5343bdSAlex Deucher #define ixD2F5_PCIE_LANE_10_EQUALIZATION_CNTL 0x60000a4 16633e5343bdSAlex Deucher #define ixD2F5_PCIE_LANE_11_EQUALIZATION_CNTL 0x60000a4 16643e5343bdSAlex Deucher #define ixD2F5_PCIE_LANE_12_EQUALIZATION_CNTL 0x60000a5 16653e5343bdSAlex Deucher #define ixD2F5_PCIE_LANE_13_EQUALIZATION_CNTL 0x60000a5 16663e5343bdSAlex Deucher #define ixD2F5_PCIE_LANE_14_EQUALIZATION_CNTL 0x60000a6 16673e5343bdSAlex Deucher #define ixD2F5_PCIE_LANE_15_EQUALIZATION_CNTL 0x60000a6 16683e5343bdSAlex Deucher #define ixD2F5_PCIE_ACS_ENH_CAP_LIST 0x60000a8 16693e5343bdSAlex Deucher #define ixD2F5_PCIE_ACS_CAP 0x60000a9 16703e5343bdSAlex Deucher #define ixD2F5_PCIE_ACS_CNTL 0x60000a9 16713e5343bdSAlex Deucher #define ixD2F5_PCIE_MC_ENH_CAP_LIST 0x60000bc 16723e5343bdSAlex Deucher #define ixD2F5_PCIE_MC_CAP 0x60000bd 16733e5343bdSAlex Deucher #define ixD2F5_PCIE_MC_CNTL 0x60000bd 16743e5343bdSAlex Deucher #define ixD2F5_PCIE_MC_ADDR0 0x60000be 16753e5343bdSAlex Deucher #define ixD2F5_PCIE_MC_ADDR1 0x60000bf 16763e5343bdSAlex Deucher #define ixD2F5_PCIE_MC_RCV0 0x60000c0 16773e5343bdSAlex Deucher #define ixD2F5_PCIE_MC_RCV1 0x60000c1 16783e5343bdSAlex Deucher #define ixD2F5_PCIE_MC_BLOCK_ALL0 0x60000c2 16793e5343bdSAlex Deucher #define ixD2F5_PCIE_MC_BLOCK_ALL1 0x60000c3 16803e5343bdSAlex Deucher #define ixD2F5_PCIE_MC_BLOCK_UNTRANSLATED_0 0x60000c4 16813e5343bdSAlex Deucher #define ixD2F5_PCIE_MC_BLOCK_UNTRANSLATED_1 0x60000c5 16823e5343bdSAlex Deucher #define ixD2F5_PCIE_MC_OVERLAY_BAR0 0x60000c6 16833e5343bdSAlex Deucher #define ixD2F5_PCIE_MC_OVERLAY_BAR1 0x60000c7 16843e5343bdSAlex Deucher #define ixD3F1_PCIE_PORT_INDEX 0x7000038 16853e5343bdSAlex Deucher #define ixD3F1_PCIE_PORT_DATA 0x7000039 16863e5343bdSAlex Deucher #define ixD3F1_PCIEP_RESERVED 0x0 16873e5343bdSAlex Deucher #define ixD3F1_PCIEP_SCRATCH 0x1 16883e5343bdSAlex Deucher #define ixD3F1_PCIEP_HW_DEBUG 0x2 16893e5343bdSAlex Deucher #define ixD3F1_PCIEP_PORT_CNTL 0x10 16903e5343bdSAlex Deucher #define ixD3F1_PCIE_TX_CNTL 0x20 16913e5343bdSAlex Deucher #define ixD3F1_PCIE_TX_REQUESTER_ID 0x21 16923e5343bdSAlex Deucher #define ixD3F1_PCIE_TX_VENDOR_SPECIFIC 0x22 16933e5343bdSAlex Deucher #define ixD3F1_PCIE_TX_REQUEST_NUM_CNTL 0x23 16943e5343bdSAlex Deucher #define ixD3F1_PCIE_TX_SEQ 0x24 16953e5343bdSAlex Deucher #define ixD3F1_PCIE_TX_REPLAY 0x25 16963e5343bdSAlex Deucher #define ixD3F1_PCIE_TX_ACK_LATENCY_LIMIT 0x26 16973e5343bdSAlex Deucher #define ixD3F1_PCIE_TX_CREDITS_ADVT_P 0x30 16983e5343bdSAlex Deucher #define ixD3F1_PCIE_TX_CREDITS_ADVT_NP 0x31 16993e5343bdSAlex Deucher #define ixD3F1_PCIE_TX_CREDITS_ADVT_CPL 0x32 17003e5343bdSAlex Deucher #define ixD3F1_PCIE_TX_CREDITS_INIT_P 0x33 17013e5343bdSAlex Deucher #define ixD3F1_PCIE_TX_CREDITS_INIT_NP 0x34 17023e5343bdSAlex Deucher #define ixD3F1_PCIE_TX_CREDITS_INIT_CPL 0x35 17033e5343bdSAlex Deucher #define ixD3F1_PCIE_TX_CREDITS_STATUS 0x36 17043e5343bdSAlex Deucher #define ixD3F1_PCIE_TX_CREDITS_FCU_THRESHOLD 0x37 17053e5343bdSAlex Deucher #define ixD3F1_PCIE_P_PORT_LANE_STATUS 0x50 17063e5343bdSAlex Deucher #define ixD3F1_PCIE_FC_P 0x60 17073e5343bdSAlex Deucher #define ixD3F1_PCIE_FC_NP 0x61 17083e5343bdSAlex Deucher #define ixD3F1_PCIE_FC_CPL 0x62 17093e5343bdSAlex Deucher #define ixD3F1_PCIE_ERR_CNTL 0x6a 17103e5343bdSAlex Deucher #define ixD3F1_PCIE_RX_CNTL 0x70 17113e5343bdSAlex Deucher #define ixD3F1_PCIE_RX_EXPECTED_SEQNUM 0x71 17123e5343bdSAlex Deucher #define ixD3F1_PCIE_RX_VENDOR_SPECIFIC 0x72 17133e5343bdSAlex Deucher #define ixD3F1_PCIE_RX_CNTL3 0x74 17143e5343bdSAlex Deucher #define ixD3F1_PCIE_RX_CREDITS_ALLOCATED_P 0x80 17153e5343bdSAlex Deucher #define ixD3F1_PCIE_RX_CREDITS_ALLOCATED_NP 0x81 17163e5343bdSAlex Deucher #define ixD3F1_PCIE_RX_CREDITS_ALLOCATED_CPL 0x82 17173e5343bdSAlex Deucher #define ixD3F1_PCIEP_ERROR_INJECT_PHYSICAL 0x83 17183e5343bdSAlex Deucher #define ixD3F1_PCIEP_ERROR_INJECT_TRANSACTION 0x84 17193e5343bdSAlex Deucher #define ixD3F1_PCIE_LC_CNTL 0xa0 17203e5343bdSAlex Deucher #define ixD3F1_PCIE_LC_CNTL2 0xb1 17213e5343bdSAlex Deucher #define ixD3F1_PCIE_LC_CNTL3 0xb5 17223e5343bdSAlex Deucher #define ixD3F1_PCIE_LC_CNTL4 0xb6 17233e5343bdSAlex Deucher #define ixD3F1_PCIE_LC_CNTL5 0xb7 17243e5343bdSAlex Deucher #define ixD3F1_PCIE_LC_CNTL6 0xbb 17253e5343bdSAlex Deucher #define ixD3F1_PCIE_LC_BW_CHANGE_CNTL 0xb2 17263e5343bdSAlex Deucher #define ixD3F1_PCIE_LC_TRAINING_CNTL 0xa1 17273e5343bdSAlex Deucher #define ixD3F1_PCIE_LC_LINK_WIDTH_CNTL 0xa2 17283e5343bdSAlex Deucher #define ixD3F1_PCIE_LC_N_FTS_CNTL 0xa3 17293e5343bdSAlex Deucher #define ixD3F1_PCIE_LC_SPEED_CNTL 0xa4 17303e5343bdSAlex Deucher #define ixD3F1_PCIE_LC_CDR_CNTL 0xb3 17313e5343bdSAlex Deucher #define ixD3F1_PCIE_LC_LANE_CNTL 0xb4 17323e5343bdSAlex Deucher #define ixD3F1_PCIE_LC_FORCE_COEFF 0xb8 17333e5343bdSAlex Deucher #define ixD3F1_PCIE_LC_BEST_EQ_SETTINGS 0xb9 17343e5343bdSAlex Deucher #define ixD3F1_PCIE_LC_FORCE_EQ_REQ_COEFF 0xba 17353e5343bdSAlex Deucher #define ixD3F1_PCIE_LC_STATE0 0xa5 17363e5343bdSAlex Deucher #define ixD3F1_PCIE_LC_STATE1 0xa6 17373e5343bdSAlex Deucher #define ixD3F1_PCIE_LC_STATE2 0xa7 17383e5343bdSAlex Deucher #define ixD3F1_PCIE_LC_STATE3 0xa8 17393e5343bdSAlex Deucher #define ixD3F1_PCIE_LC_STATE4 0xa9 17403e5343bdSAlex Deucher #define ixD3F1_PCIE_LC_STATE5 0xaa 17413e5343bdSAlex Deucher #define ixD3F1_PCIEP_STRAP_LC 0xc0 17423e5343bdSAlex Deucher #define ixD3F1_PCIEP_STRAP_MISC 0xc1 17433e5343bdSAlex Deucher #define ixD3F1_PCIEP_BCH_ECC_CNTL 0xd0 17443e5343bdSAlex Deucher #define ixD3F1_PCIEP_HPGI_PRIVATE 0xd2 17453e5343bdSAlex Deucher #define ixD3F1_PCIEP_HPGI 0xda 17463e5343bdSAlex Deucher #define ixD3F1_VENDOR_ID 0x7000000 17473e5343bdSAlex Deucher #define ixD3F1_DEVICE_ID 0x7000000 17483e5343bdSAlex Deucher #define ixD3F1_COMMAND 0x7000001 17493e5343bdSAlex Deucher #define ixD3F1_STATUS 0x7000001 17503e5343bdSAlex Deucher #define ixD3F1_REVISION_ID 0x7000002 17513e5343bdSAlex Deucher #define ixD3F1_PROG_INTERFACE 0x7000002 17523e5343bdSAlex Deucher #define ixD3F1_SUB_CLASS 0x7000002 17533e5343bdSAlex Deucher #define ixD3F1_BASE_CLASS 0x7000002 17543e5343bdSAlex Deucher #define ixD3F1_CACHE_LINE 0x7000003 17553e5343bdSAlex Deucher #define ixD3F1_LATENCY 0x7000003 17563e5343bdSAlex Deucher #define ixD3F1_HEADER 0x7000003 17573e5343bdSAlex Deucher #define ixD3F1_BIST 0x7000003 17583e5343bdSAlex Deucher #define ixD3F1_SUB_BUS_NUMBER_LATENCY 0x7000006 17593e5343bdSAlex Deucher #define ixD3F1_IO_BASE_LIMIT 0x7000007 17603e5343bdSAlex Deucher #define ixD3F1_SECONDARY_STATUS 0x7000007 17613e5343bdSAlex Deucher #define ixD3F1_MEM_BASE_LIMIT 0x7000008 17623e5343bdSAlex Deucher #define ixD3F1_PREF_BASE_LIMIT 0x7000009 17633e5343bdSAlex Deucher #define ixD3F1_PREF_BASE_UPPER 0x700000a 17643e5343bdSAlex Deucher #define ixD3F1_PREF_LIMIT_UPPER 0x700000b 17653e5343bdSAlex Deucher #define ixD3F1_IO_BASE_LIMIT_HI 0x700000c 17663e5343bdSAlex Deucher #define ixD3F1_IRQ_BRIDGE_CNTL 0x700000f 17673e5343bdSAlex Deucher #define ixD3F1_CAP_PTR 0x700000d 17683e5343bdSAlex Deucher #define ixD3F1_INTERRUPT_LINE 0x700000f 17693e5343bdSAlex Deucher #define ixD3F1_INTERRUPT_PIN 0x700000f 17703e5343bdSAlex Deucher #define ixD3F1_EXT_BRIDGE_CNTL 0x7000010 17713e5343bdSAlex Deucher #define ixD3F1_PMI_CAP_LIST 0x7000014 17723e5343bdSAlex Deucher #define ixD3F1_PMI_CAP 0x7000014 17733e5343bdSAlex Deucher #define ixD3F1_PMI_STATUS_CNTL 0x7000015 17743e5343bdSAlex Deucher #define ixD3F1_PCIE_CAP_LIST 0x7000016 17753e5343bdSAlex Deucher #define ixD3F1_PCIE_CAP 0x7000016 17763e5343bdSAlex Deucher #define ixD3F1_DEVICE_CAP 0x7000017 17773e5343bdSAlex Deucher #define ixD3F1_DEVICE_CNTL 0x7000018 17783e5343bdSAlex Deucher #define ixD3F1_DEVICE_STATUS 0x7000018 17793e5343bdSAlex Deucher #define ixD3F1_LINK_CAP 0x7000019 17803e5343bdSAlex Deucher #define ixD3F1_LINK_CNTL 0x700001a 17813e5343bdSAlex Deucher #define ixD3F1_LINK_STATUS 0x700001a 17823e5343bdSAlex Deucher #define ixD3F1_SLOT_CAP 0x700001b 17833e5343bdSAlex Deucher #define ixD3F1_SLOT_CNTL 0x700001c 17843e5343bdSAlex Deucher #define ixD3F1_SLOT_STATUS 0x700001c 17853e5343bdSAlex Deucher #define ixD3F1_ROOT_CNTL 0x700001d 17863e5343bdSAlex Deucher #define ixD3F1_ROOT_CAP 0x700001d 17873e5343bdSAlex Deucher #define ixD3F1_ROOT_STATUS 0x700001e 17883e5343bdSAlex Deucher #define ixD3F1_DEVICE_CAP2 0x700001f 17893e5343bdSAlex Deucher #define ixD3F1_DEVICE_CNTL2 0x7000020 17903e5343bdSAlex Deucher #define ixD3F1_DEVICE_STATUS2 0x7000020 17913e5343bdSAlex Deucher #define ixD3F1_LINK_CAP2 0x7000021 17923e5343bdSAlex Deucher #define ixD3F1_LINK_CNTL2 0x7000022 17933e5343bdSAlex Deucher #define ixD3F1_LINK_STATUS2 0x7000022 17943e5343bdSAlex Deucher #define ixD3F1_SLOT_CAP2 0x7000023 17953e5343bdSAlex Deucher #define ixD3F1_SLOT_CNTL2 0x7000024 17963e5343bdSAlex Deucher #define ixD3F1_SLOT_STATUS2 0x7000024 17973e5343bdSAlex Deucher #define ixD3F1_MSI_CAP_LIST 0x7000028 17983e5343bdSAlex Deucher #define ixD3F1_MSI_MSG_CNTL 0x7000028 17993e5343bdSAlex Deucher #define ixD3F1_MSI_MSG_ADDR_LO 0x7000029 18003e5343bdSAlex Deucher #define ixD3F1_MSI_MSG_ADDR_HI 0x700002a 18013e5343bdSAlex Deucher #define ixD3F1_MSI_MSG_DATA_64 0x700002b 18023e5343bdSAlex Deucher #define ixD3F1_MSI_MSG_DATA 0x700002a 18033e5343bdSAlex Deucher #define ixD3F1_SSID_CAP_LIST 0x7000030 18043e5343bdSAlex Deucher #define ixD3F1_SSID_CAP 0x7000031 18053e5343bdSAlex Deucher #define ixD3F1_MSI_MAP_CAP_LIST 0x7000032 18063e5343bdSAlex Deucher #define ixD3F1_MSI_MAP_CAP 0x7000032 18073e5343bdSAlex Deucher #define ixD3F1_MSI_MAP_ADDR_LO 0x7000033 18083e5343bdSAlex Deucher #define ixD3F1_MSI_MAP_ADDR_HI 0x7000034 18093e5343bdSAlex Deucher #define ixD3F1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x7000040 18103e5343bdSAlex Deucher #define ixD3F1_PCIE_VENDOR_SPECIFIC_HDR 0x7000041 18113e5343bdSAlex Deucher #define ixD3F1_PCIE_VENDOR_SPECIFIC1 0x7000042 18123e5343bdSAlex Deucher #define ixD3F1_PCIE_VENDOR_SPECIFIC2 0x7000043 18133e5343bdSAlex Deucher #define ixD3F1_PCIE_VC_ENH_CAP_LIST 0x7000044 18143e5343bdSAlex Deucher #define ixD3F1_PCIE_PORT_VC_CAP_REG1 0x7000045 18153e5343bdSAlex Deucher #define ixD3F1_PCIE_PORT_VC_CAP_REG2 0x7000046 18163e5343bdSAlex Deucher #define ixD3F1_PCIE_PORT_VC_CNTL 0x7000047 18173e5343bdSAlex Deucher #define ixD3F1_PCIE_PORT_VC_STATUS 0x7000047 18183e5343bdSAlex Deucher #define ixD3F1_PCIE_VC0_RESOURCE_CAP 0x7000048 18193e5343bdSAlex Deucher #define ixD3F1_PCIE_VC0_RESOURCE_CNTL 0x7000049 18203e5343bdSAlex Deucher #define ixD3F1_PCIE_VC0_RESOURCE_STATUS 0x700004a 18213e5343bdSAlex Deucher #define ixD3F1_PCIE_VC1_RESOURCE_CAP 0x700004b 18223e5343bdSAlex Deucher #define ixD3F1_PCIE_VC1_RESOURCE_CNTL 0x700004c 18233e5343bdSAlex Deucher #define ixD3F1_PCIE_VC1_RESOURCE_STATUS 0x700004d 18243e5343bdSAlex Deucher #define ixD3F1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 0x7000050 18253e5343bdSAlex Deucher #define ixD3F1_PCIE_DEV_SERIAL_NUM_DW1 0x7000051 18263e5343bdSAlex Deucher #define ixD3F1_PCIE_DEV_SERIAL_NUM_DW2 0x7000052 18273e5343bdSAlex Deucher #define ixD3F1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x7000054 18283e5343bdSAlex Deucher #define ixD3F1_PCIE_UNCORR_ERR_STATUS 0x7000055 18293e5343bdSAlex Deucher #define ixD3F1_PCIE_UNCORR_ERR_MASK 0x7000056 18303e5343bdSAlex Deucher #define ixD3F1_PCIE_UNCORR_ERR_SEVERITY 0x7000057 18313e5343bdSAlex Deucher #define ixD3F1_PCIE_CORR_ERR_STATUS 0x7000058 18323e5343bdSAlex Deucher #define ixD3F1_PCIE_CORR_ERR_MASK 0x7000059 18333e5343bdSAlex Deucher #define ixD3F1_PCIE_ADV_ERR_CAP_CNTL 0x700005a 18343e5343bdSAlex Deucher #define ixD3F1_PCIE_HDR_LOG0 0x700005b 18353e5343bdSAlex Deucher #define ixD3F1_PCIE_HDR_LOG1 0x700005c 18363e5343bdSAlex Deucher #define ixD3F1_PCIE_HDR_LOG2 0x700005d 18373e5343bdSAlex Deucher #define ixD3F1_PCIE_HDR_LOG3 0x700005e 18383e5343bdSAlex Deucher #define ixD3F1_PCIE_ROOT_ERR_CMD 0x700005f 18393e5343bdSAlex Deucher #define ixD3F1_PCIE_ROOT_ERR_STATUS 0x7000060 18403e5343bdSAlex Deucher #define ixD3F1_PCIE_ERR_SRC_ID 0x7000061 18413e5343bdSAlex Deucher #define ixD3F1_PCIE_TLP_PREFIX_LOG0 0x7000062 18423e5343bdSAlex Deucher #define ixD3F1_PCIE_TLP_PREFIX_LOG1 0x7000063 18433e5343bdSAlex Deucher #define ixD3F1_PCIE_TLP_PREFIX_LOG2 0x7000064 18443e5343bdSAlex Deucher #define ixD3F1_PCIE_TLP_PREFIX_LOG3 0x7000065 18453e5343bdSAlex Deucher #define ixD3F1_PCIE_SECONDARY_ENH_CAP_LIST 0x700009c 18463e5343bdSAlex Deucher #define ixD3F1_PCIE_LINK_CNTL3 0x700009d 18473e5343bdSAlex Deucher #define ixD3F1_PCIE_LANE_ERROR_STATUS 0x700009e 18483e5343bdSAlex Deucher #define ixD3F1_PCIE_LANE_0_EQUALIZATION_CNTL 0x700009f 18493e5343bdSAlex Deucher #define ixD3F1_PCIE_LANE_1_EQUALIZATION_CNTL 0x700009f 18503e5343bdSAlex Deucher #define ixD3F1_PCIE_LANE_2_EQUALIZATION_CNTL 0x70000a0 18513e5343bdSAlex Deucher #define ixD3F1_PCIE_LANE_3_EQUALIZATION_CNTL 0x70000a0 18523e5343bdSAlex Deucher #define ixD3F1_PCIE_LANE_4_EQUALIZATION_CNTL 0x70000a1 18533e5343bdSAlex Deucher #define ixD3F1_PCIE_LANE_5_EQUALIZATION_CNTL 0x70000a1 18543e5343bdSAlex Deucher #define ixD3F1_PCIE_LANE_6_EQUALIZATION_CNTL 0x70000a2 18553e5343bdSAlex Deucher #define ixD3F1_PCIE_LANE_7_EQUALIZATION_CNTL 0x70000a2 18563e5343bdSAlex Deucher #define ixD3F1_PCIE_LANE_8_EQUALIZATION_CNTL 0x70000a3 18573e5343bdSAlex Deucher #define ixD3F1_PCIE_LANE_9_EQUALIZATION_CNTL 0x70000a3 18583e5343bdSAlex Deucher #define ixD3F1_PCIE_LANE_10_EQUALIZATION_CNTL 0x70000a4 18593e5343bdSAlex Deucher #define ixD3F1_PCIE_LANE_11_EQUALIZATION_CNTL 0x70000a4 18603e5343bdSAlex Deucher #define ixD3F1_PCIE_LANE_12_EQUALIZATION_CNTL 0x70000a5 18613e5343bdSAlex Deucher #define ixD3F1_PCIE_LANE_13_EQUALIZATION_CNTL 0x70000a5 18623e5343bdSAlex Deucher #define ixD3F1_PCIE_LANE_14_EQUALIZATION_CNTL 0x70000a6 18633e5343bdSAlex Deucher #define ixD3F1_PCIE_LANE_15_EQUALIZATION_CNTL 0x70000a6 18643e5343bdSAlex Deucher #define ixD3F1_PCIE_ACS_ENH_CAP_LIST 0x70000a8 18653e5343bdSAlex Deucher #define ixD3F1_PCIE_ACS_CAP 0x70000a9 18663e5343bdSAlex Deucher #define ixD3F1_PCIE_ACS_CNTL 0x70000a9 18673e5343bdSAlex Deucher #define ixD3F1_PCIE_MC_ENH_CAP_LIST 0x70000bc 18683e5343bdSAlex Deucher #define ixD3F1_PCIE_MC_CAP 0x70000bd 18693e5343bdSAlex Deucher #define ixD3F1_PCIE_MC_CNTL 0x70000bd 18703e5343bdSAlex Deucher #define ixD3F1_PCIE_MC_ADDR0 0x70000be 18713e5343bdSAlex Deucher #define ixD3F1_PCIE_MC_ADDR1 0x70000bf 18723e5343bdSAlex Deucher #define ixD3F1_PCIE_MC_RCV0 0x70000c0 18733e5343bdSAlex Deucher #define ixD3F1_PCIE_MC_RCV1 0x70000c1 18743e5343bdSAlex Deucher #define ixD3F1_PCIE_MC_BLOCK_ALL0 0x70000c2 18753e5343bdSAlex Deucher #define ixD3F1_PCIE_MC_BLOCK_ALL1 0x70000c3 18763e5343bdSAlex Deucher #define ixD3F1_PCIE_MC_BLOCK_UNTRANSLATED_0 0x70000c4 18773e5343bdSAlex Deucher #define ixD3F1_PCIE_MC_BLOCK_UNTRANSLATED_1 0x70000c5 18783e5343bdSAlex Deucher #define ixD3F1_PCIE_MC_OVERLAY_BAR0 0x70000c6 18793e5343bdSAlex Deucher #define ixD3F1_PCIE_MC_OVERLAY_BAR1 0x70000c7 18803e5343bdSAlex Deucher #define ixD3F2_PCIE_PORT_INDEX 0x8000038 18813e5343bdSAlex Deucher #define ixD3F2_PCIE_PORT_DATA 0x8000039 18823e5343bdSAlex Deucher #define ixD3F2_PCIEP_RESERVED 0x0 18833e5343bdSAlex Deucher #define ixD3F2_PCIEP_SCRATCH 0x1 18843e5343bdSAlex Deucher #define ixD3F2_PCIEP_HW_DEBUG 0x2 18853e5343bdSAlex Deucher #define ixD3F2_PCIEP_PORT_CNTL 0x10 18863e5343bdSAlex Deucher #define ixD3F2_PCIE_TX_CNTL 0x20 18873e5343bdSAlex Deucher #define ixD3F2_PCIE_TX_REQUESTER_ID 0x21 18883e5343bdSAlex Deucher #define ixD3F2_PCIE_TX_VENDOR_SPECIFIC 0x22 18893e5343bdSAlex Deucher #define ixD3F2_PCIE_TX_REQUEST_NUM_CNTL 0x23 18903e5343bdSAlex Deucher #define ixD3F2_PCIE_TX_SEQ 0x24 18913e5343bdSAlex Deucher #define ixD3F2_PCIE_TX_REPLAY 0x25 18923e5343bdSAlex Deucher #define ixD3F2_PCIE_TX_ACK_LATENCY_LIMIT 0x26 18933e5343bdSAlex Deucher #define ixD3F2_PCIE_TX_CREDITS_ADVT_P 0x30 18943e5343bdSAlex Deucher #define ixD3F2_PCIE_TX_CREDITS_ADVT_NP 0x31 18953e5343bdSAlex Deucher #define ixD3F2_PCIE_TX_CREDITS_ADVT_CPL 0x32 18963e5343bdSAlex Deucher #define ixD3F2_PCIE_TX_CREDITS_INIT_P 0x33 18973e5343bdSAlex Deucher #define ixD3F2_PCIE_TX_CREDITS_INIT_NP 0x34 18983e5343bdSAlex Deucher #define ixD3F2_PCIE_TX_CREDITS_INIT_CPL 0x35 18993e5343bdSAlex Deucher #define ixD3F2_PCIE_TX_CREDITS_STATUS 0x36 19003e5343bdSAlex Deucher #define ixD3F2_PCIE_TX_CREDITS_FCU_THRESHOLD 0x37 19013e5343bdSAlex Deucher #define ixD3F2_PCIE_P_PORT_LANE_STATUS 0x50 19023e5343bdSAlex Deucher #define ixD3F2_PCIE_FC_P 0x60 19033e5343bdSAlex Deucher #define ixD3F2_PCIE_FC_NP 0x61 19043e5343bdSAlex Deucher #define ixD3F2_PCIE_FC_CPL 0x62 19053e5343bdSAlex Deucher #define ixD3F2_PCIE_ERR_CNTL 0x6a 19063e5343bdSAlex Deucher #define ixD3F2_PCIE_RX_CNTL 0x70 19073e5343bdSAlex Deucher #define ixD3F2_PCIE_RX_EXPECTED_SEQNUM 0x71 19083e5343bdSAlex Deucher #define ixD3F2_PCIE_RX_VENDOR_SPECIFIC 0x72 19093e5343bdSAlex Deucher #define ixD3F2_PCIE_RX_CNTL3 0x74 19103e5343bdSAlex Deucher #define ixD3F2_PCIE_RX_CREDITS_ALLOCATED_P 0x80 19113e5343bdSAlex Deucher #define ixD3F2_PCIE_RX_CREDITS_ALLOCATED_NP 0x81 19123e5343bdSAlex Deucher #define ixD3F2_PCIE_RX_CREDITS_ALLOCATED_CPL 0x82 19133e5343bdSAlex Deucher #define ixD3F2_PCIEP_ERROR_INJECT_PHYSICAL 0x83 19143e5343bdSAlex Deucher #define ixD3F2_PCIEP_ERROR_INJECT_TRANSACTION 0x84 19153e5343bdSAlex Deucher #define ixD3F2_PCIE_LC_CNTL 0xa0 19163e5343bdSAlex Deucher #define ixD3F2_PCIE_LC_CNTL2 0xb1 19173e5343bdSAlex Deucher #define ixD3F2_PCIE_LC_CNTL3 0xb5 19183e5343bdSAlex Deucher #define ixD3F2_PCIE_LC_CNTL4 0xb6 19193e5343bdSAlex Deucher #define ixD3F2_PCIE_LC_CNTL5 0xb7 19203e5343bdSAlex Deucher #define ixD3F2_PCIE_LC_CNTL6 0xbb 19213e5343bdSAlex Deucher #define ixD3F2_PCIE_LC_BW_CHANGE_CNTL 0xb2 19223e5343bdSAlex Deucher #define ixD3F2_PCIE_LC_TRAINING_CNTL 0xa1 19233e5343bdSAlex Deucher #define ixD3F2_PCIE_LC_LINK_WIDTH_CNTL 0xa2 19243e5343bdSAlex Deucher #define ixD3F2_PCIE_LC_N_FTS_CNTL 0xa3 19253e5343bdSAlex Deucher #define ixD3F2_PCIE_LC_SPEED_CNTL 0xa4 19263e5343bdSAlex Deucher #define ixD3F2_PCIE_LC_CDR_CNTL 0xb3 19273e5343bdSAlex Deucher #define ixD3F2_PCIE_LC_LANE_CNTL 0xb4 19283e5343bdSAlex Deucher #define ixD3F2_PCIE_LC_FORCE_COEFF 0xb8 19293e5343bdSAlex Deucher #define ixD3F2_PCIE_LC_BEST_EQ_SETTINGS 0xb9 19303e5343bdSAlex Deucher #define ixD3F2_PCIE_LC_FORCE_EQ_REQ_COEFF 0xba 19313e5343bdSAlex Deucher #define ixD3F2_PCIE_LC_STATE0 0xa5 19323e5343bdSAlex Deucher #define ixD3F2_PCIE_LC_STATE1 0xa6 19333e5343bdSAlex Deucher #define ixD3F2_PCIE_LC_STATE2 0xa7 19343e5343bdSAlex Deucher #define ixD3F2_PCIE_LC_STATE3 0xa8 19353e5343bdSAlex Deucher #define ixD3F2_PCIE_LC_STATE4 0xa9 19363e5343bdSAlex Deucher #define ixD3F2_PCIE_LC_STATE5 0xaa 19373e5343bdSAlex Deucher #define ixD3F2_PCIEP_STRAP_LC 0xc0 19383e5343bdSAlex Deucher #define ixD3F2_PCIEP_STRAP_MISC 0xc1 19393e5343bdSAlex Deucher #define ixD3F2_PCIEP_BCH_ECC_CNTL 0xd0 19403e5343bdSAlex Deucher #define ixD3F2_PCIEP_HPGI_PRIVATE 0xd2 19413e5343bdSAlex Deucher #define ixD3F2_PCIEP_HPGI 0xda 19423e5343bdSAlex Deucher #define ixD3F2_VENDOR_ID 0x8000000 19433e5343bdSAlex Deucher #define ixD3F2_DEVICE_ID 0x8000000 19443e5343bdSAlex Deucher #define ixD3F2_COMMAND 0x8000001 19453e5343bdSAlex Deucher #define ixD3F2_STATUS 0x8000001 19463e5343bdSAlex Deucher #define ixD3F2_REVISION_ID 0x8000002 19473e5343bdSAlex Deucher #define ixD3F2_PROG_INTERFACE 0x8000002 19483e5343bdSAlex Deucher #define ixD3F2_SUB_CLASS 0x8000002 19493e5343bdSAlex Deucher #define ixD3F2_BASE_CLASS 0x8000002 19503e5343bdSAlex Deucher #define ixD3F2_CACHE_LINE 0x8000003 19513e5343bdSAlex Deucher #define ixD3F2_LATENCY 0x8000003 19523e5343bdSAlex Deucher #define ixD3F2_HEADER 0x8000003 19533e5343bdSAlex Deucher #define ixD3F2_BIST 0x8000003 19543e5343bdSAlex Deucher #define ixD3F2_SUB_BUS_NUMBER_LATENCY 0x8000006 19553e5343bdSAlex Deucher #define ixD3F2_IO_BASE_LIMIT 0x8000007 19563e5343bdSAlex Deucher #define ixD3F2_SECONDARY_STATUS 0x8000007 19573e5343bdSAlex Deucher #define ixD3F2_MEM_BASE_LIMIT 0x8000008 19583e5343bdSAlex Deucher #define ixD3F2_PREF_BASE_LIMIT 0x8000009 19593e5343bdSAlex Deucher #define ixD3F2_PREF_BASE_UPPER 0x800000a 19603e5343bdSAlex Deucher #define ixD3F2_PREF_LIMIT_UPPER 0x800000b 19613e5343bdSAlex Deucher #define ixD3F2_IO_BASE_LIMIT_HI 0x800000c 19623e5343bdSAlex Deucher #define ixD3F2_IRQ_BRIDGE_CNTL 0x800000f 19633e5343bdSAlex Deucher #define ixD3F2_CAP_PTR 0x800000d 19643e5343bdSAlex Deucher #define ixD3F2_INTERRUPT_LINE 0x800000f 19653e5343bdSAlex Deucher #define ixD3F2_INTERRUPT_PIN 0x800000f 19663e5343bdSAlex Deucher #define ixD3F2_EXT_BRIDGE_CNTL 0x8000010 19673e5343bdSAlex Deucher #define ixD3F2_PMI_CAP_LIST 0x8000014 19683e5343bdSAlex Deucher #define ixD3F2_PMI_CAP 0x8000014 19693e5343bdSAlex Deucher #define ixD3F2_PMI_STATUS_CNTL 0x8000015 19703e5343bdSAlex Deucher #define ixD3F2_PCIE_CAP_LIST 0x8000016 19713e5343bdSAlex Deucher #define ixD3F2_PCIE_CAP 0x8000016 19723e5343bdSAlex Deucher #define ixD3F2_DEVICE_CAP 0x8000017 19733e5343bdSAlex Deucher #define ixD3F2_DEVICE_CNTL 0x8000018 19743e5343bdSAlex Deucher #define ixD3F2_DEVICE_STATUS 0x8000018 19753e5343bdSAlex Deucher #define ixD3F2_LINK_CAP 0x8000019 19763e5343bdSAlex Deucher #define ixD3F2_LINK_CNTL 0x800001a 19773e5343bdSAlex Deucher #define ixD3F2_LINK_STATUS 0x800001a 19783e5343bdSAlex Deucher #define ixD3F2_SLOT_CAP 0x800001b 19793e5343bdSAlex Deucher #define ixD3F2_SLOT_CNTL 0x800001c 19803e5343bdSAlex Deucher #define ixD3F2_SLOT_STATUS 0x800001c 19813e5343bdSAlex Deucher #define ixD3F2_ROOT_CNTL 0x800001d 19823e5343bdSAlex Deucher #define ixD3F2_ROOT_CAP 0x800001d 19833e5343bdSAlex Deucher #define ixD3F2_ROOT_STATUS 0x800001e 19843e5343bdSAlex Deucher #define ixD3F2_DEVICE_CAP2 0x800001f 19853e5343bdSAlex Deucher #define ixD3F2_DEVICE_CNTL2 0x8000020 19863e5343bdSAlex Deucher #define ixD3F2_DEVICE_STATUS2 0x8000020 19873e5343bdSAlex Deucher #define ixD3F2_LINK_CAP2 0x8000021 19883e5343bdSAlex Deucher #define ixD3F2_LINK_CNTL2 0x8000022 19893e5343bdSAlex Deucher #define ixD3F2_LINK_STATUS2 0x8000022 19903e5343bdSAlex Deucher #define ixD3F2_SLOT_CAP2 0x8000023 19913e5343bdSAlex Deucher #define ixD3F2_SLOT_CNTL2 0x8000024 19923e5343bdSAlex Deucher #define ixD3F2_SLOT_STATUS2 0x8000024 19933e5343bdSAlex Deucher #define ixD3F2_MSI_CAP_LIST 0x8000028 19943e5343bdSAlex Deucher #define ixD3F2_MSI_MSG_CNTL 0x8000028 19953e5343bdSAlex Deucher #define ixD3F2_MSI_MSG_ADDR_LO 0x8000029 19963e5343bdSAlex Deucher #define ixD3F2_MSI_MSG_ADDR_HI 0x800002a 19973e5343bdSAlex Deucher #define ixD3F2_MSI_MSG_DATA_64 0x800002b 19983e5343bdSAlex Deucher #define ixD3F2_MSI_MSG_DATA 0x800002a 19993e5343bdSAlex Deucher #define ixD3F2_SSID_CAP_LIST 0x8000030 20003e5343bdSAlex Deucher #define ixD3F2_SSID_CAP 0x8000031 20013e5343bdSAlex Deucher #define ixD3F2_MSI_MAP_CAP_LIST 0x8000032 20023e5343bdSAlex Deucher #define ixD3F2_MSI_MAP_CAP 0x8000032 20033e5343bdSAlex Deucher #define ixD3F2_MSI_MAP_ADDR_LO 0x8000033 20043e5343bdSAlex Deucher #define ixD3F2_MSI_MAP_ADDR_HI 0x8000034 20053e5343bdSAlex Deucher #define ixD3F2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x8000040 20063e5343bdSAlex Deucher #define ixD3F2_PCIE_VENDOR_SPECIFIC_HDR 0x8000041 20073e5343bdSAlex Deucher #define ixD3F2_PCIE_VENDOR_SPECIFIC1 0x8000042 20083e5343bdSAlex Deucher #define ixD3F2_PCIE_VENDOR_SPECIFIC2 0x8000043 20093e5343bdSAlex Deucher #define ixD3F2_PCIE_VC_ENH_CAP_LIST 0x8000044 20103e5343bdSAlex Deucher #define ixD3F2_PCIE_PORT_VC_CAP_REG1 0x8000045 20113e5343bdSAlex Deucher #define ixD3F2_PCIE_PORT_VC_CAP_REG2 0x8000046 20123e5343bdSAlex Deucher #define ixD3F2_PCIE_PORT_VC_CNTL 0x8000047 20133e5343bdSAlex Deucher #define ixD3F2_PCIE_PORT_VC_STATUS 0x8000047 20143e5343bdSAlex Deucher #define ixD3F2_PCIE_VC0_RESOURCE_CAP 0x8000048 20153e5343bdSAlex Deucher #define ixD3F2_PCIE_VC0_RESOURCE_CNTL 0x8000049 20163e5343bdSAlex Deucher #define ixD3F2_PCIE_VC0_RESOURCE_STATUS 0x800004a 20173e5343bdSAlex Deucher #define ixD3F2_PCIE_VC1_RESOURCE_CAP 0x800004b 20183e5343bdSAlex Deucher #define ixD3F2_PCIE_VC1_RESOURCE_CNTL 0x800004c 20193e5343bdSAlex Deucher #define ixD3F2_PCIE_VC1_RESOURCE_STATUS 0x800004d 20203e5343bdSAlex Deucher #define ixD3F2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 0x8000050 20213e5343bdSAlex Deucher #define ixD3F2_PCIE_DEV_SERIAL_NUM_DW1 0x8000051 20223e5343bdSAlex Deucher #define ixD3F2_PCIE_DEV_SERIAL_NUM_DW2 0x8000052 20233e5343bdSAlex Deucher #define ixD3F2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x8000054 20243e5343bdSAlex Deucher #define ixD3F2_PCIE_UNCORR_ERR_STATUS 0x8000055 20253e5343bdSAlex Deucher #define ixD3F2_PCIE_UNCORR_ERR_MASK 0x8000056 20263e5343bdSAlex Deucher #define ixD3F2_PCIE_UNCORR_ERR_SEVERITY 0x8000057 20273e5343bdSAlex Deucher #define ixD3F2_PCIE_CORR_ERR_STATUS 0x8000058 20283e5343bdSAlex Deucher #define ixD3F2_PCIE_CORR_ERR_MASK 0x8000059 20293e5343bdSAlex Deucher #define ixD3F2_PCIE_ADV_ERR_CAP_CNTL 0x800005a 20303e5343bdSAlex Deucher #define ixD3F2_PCIE_HDR_LOG0 0x800005b 20313e5343bdSAlex Deucher #define ixD3F2_PCIE_HDR_LOG1 0x800005c 20323e5343bdSAlex Deucher #define ixD3F2_PCIE_HDR_LOG2 0x800005d 20333e5343bdSAlex Deucher #define ixD3F2_PCIE_HDR_LOG3 0x800005e 20343e5343bdSAlex Deucher #define ixD3F2_PCIE_ROOT_ERR_CMD 0x800005f 20353e5343bdSAlex Deucher #define ixD3F2_PCIE_ROOT_ERR_STATUS 0x8000060 20363e5343bdSAlex Deucher #define ixD3F2_PCIE_ERR_SRC_ID 0x8000061 20373e5343bdSAlex Deucher #define ixD3F2_PCIE_TLP_PREFIX_LOG0 0x8000062 20383e5343bdSAlex Deucher #define ixD3F2_PCIE_TLP_PREFIX_LOG1 0x8000063 20393e5343bdSAlex Deucher #define ixD3F2_PCIE_TLP_PREFIX_LOG2 0x8000064 20403e5343bdSAlex Deucher #define ixD3F2_PCIE_TLP_PREFIX_LOG3 0x8000065 20413e5343bdSAlex Deucher #define ixD3F2_PCIE_SECONDARY_ENH_CAP_LIST 0x800009c 20423e5343bdSAlex Deucher #define ixD3F2_PCIE_LINK_CNTL3 0x800009d 20433e5343bdSAlex Deucher #define ixD3F2_PCIE_LANE_ERROR_STATUS 0x800009e 20443e5343bdSAlex Deucher #define ixD3F2_PCIE_LANE_0_EQUALIZATION_CNTL 0x800009f 20453e5343bdSAlex Deucher #define ixD3F2_PCIE_LANE_1_EQUALIZATION_CNTL 0x800009f 20463e5343bdSAlex Deucher #define ixD3F2_PCIE_LANE_2_EQUALIZATION_CNTL 0x80000a0 20473e5343bdSAlex Deucher #define ixD3F2_PCIE_LANE_3_EQUALIZATION_CNTL 0x80000a0 20483e5343bdSAlex Deucher #define ixD3F2_PCIE_LANE_4_EQUALIZATION_CNTL 0x80000a1 20493e5343bdSAlex Deucher #define ixD3F2_PCIE_LANE_5_EQUALIZATION_CNTL 0x80000a1 20503e5343bdSAlex Deucher #define ixD3F2_PCIE_LANE_6_EQUALIZATION_CNTL 0x80000a2 20513e5343bdSAlex Deucher #define ixD3F2_PCIE_LANE_7_EQUALIZATION_CNTL 0x80000a2 20523e5343bdSAlex Deucher #define ixD3F2_PCIE_LANE_8_EQUALIZATION_CNTL 0x80000a3 20533e5343bdSAlex Deucher #define ixD3F2_PCIE_LANE_9_EQUALIZATION_CNTL 0x80000a3 20543e5343bdSAlex Deucher #define ixD3F2_PCIE_LANE_10_EQUALIZATION_CNTL 0x80000a4 20553e5343bdSAlex Deucher #define ixD3F2_PCIE_LANE_11_EQUALIZATION_CNTL 0x80000a4 20563e5343bdSAlex Deucher #define ixD3F2_PCIE_LANE_12_EQUALIZATION_CNTL 0x80000a5 20573e5343bdSAlex Deucher #define ixD3F2_PCIE_LANE_13_EQUALIZATION_CNTL 0x80000a5 20583e5343bdSAlex Deucher #define ixD3F2_PCIE_LANE_14_EQUALIZATION_CNTL 0x80000a6 20593e5343bdSAlex Deucher #define ixD3F2_PCIE_LANE_15_EQUALIZATION_CNTL 0x80000a6 20603e5343bdSAlex Deucher #define ixD3F2_PCIE_ACS_ENH_CAP_LIST 0x80000a8 20613e5343bdSAlex Deucher #define ixD3F2_PCIE_ACS_CAP 0x80000a9 20623e5343bdSAlex Deucher #define ixD3F2_PCIE_ACS_CNTL 0x80000a9 20633e5343bdSAlex Deucher #define ixD3F2_PCIE_MC_ENH_CAP_LIST 0x80000bc 20643e5343bdSAlex Deucher #define ixD3F2_PCIE_MC_CAP 0x80000bd 20653e5343bdSAlex Deucher #define ixD3F2_PCIE_MC_CNTL 0x80000bd 20663e5343bdSAlex Deucher #define ixD3F2_PCIE_MC_ADDR0 0x80000be 20673e5343bdSAlex Deucher #define ixD3F2_PCIE_MC_ADDR1 0x80000bf 20683e5343bdSAlex Deucher #define ixD3F2_PCIE_MC_RCV0 0x80000c0 20693e5343bdSAlex Deucher #define ixD3F2_PCIE_MC_RCV1 0x80000c1 20703e5343bdSAlex Deucher #define ixD3F2_PCIE_MC_BLOCK_ALL0 0x80000c2 20713e5343bdSAlex Deucher #define ixD3F2_PCIE_MC_BLOCK_ALL1 0x80000c3 20723e5343bdSAlex Deucher #define ixD3F2_PCIE_MC_BLOCK_UNTRANSLATED_0 0x80000c4 20733e5343bdSAlex Deucher #define ixD3F2_PCIE_MC_BLOCK_UNTRANSLATED_1 0x80000c5 20743e5343bdSAlex Deucher #define ixD3F2_PCIE_MC_OVERLAY_BAR0 0x80000c6 20753e5343bdSAlex Deucher #define ixD3F2_PCIE_MC_OVERLAY_BAR1 0x80000c7 20763e5343bdSAlex Deucher #define ixD3F3_PCIE_PORT_INDEX 0x9000038 20773e5343bdSAlex Deucher #define ixD3F3_PCIE_PORT_DATA 0x9000039 20783e5343bdSAlex Deucher #define ixD3F3_PCIEP_RESERVED 0x0 20793e5343bdSAlex Deucher #define ixD3F3_PCIEP_SCRATCH 0x1 20803e5343bdSAlex Deucher #define ixD3F3_PCIEP_HW_DEBUG 0x2 20813e5343bdSAlex Deucher #define ixD3F3_PCIEP_PORT_CNTL 0x10 20823e5343bdSAlex Deucher #define ixD3F3_PCIE_TX_CNTL 0x20 20833e5343bdSAlex Deucher #define ixD3F3_PCIE_TX_REQUESTER_ID 0x21 20843e5343bdSAlex Deucher #define ixD3F3_PCIE_TX_VENDOR_SPECIFIC 0x22 20853e5343bdSAlex Deucher #define ixD3F3_PCIE_TX_REQUEST_NUM_CNTL 0x23 20863e5343bdSAlex Deucher #define ixD3F3_PCIE_TX_SEQ 0x24 20873e5343bdSAlex Deucher #define ixD3F3_PCIE_TX_REPLAY 0x25 20883e5343bdSAlex Deucher #define ixD3F3_PCIE_TX_ACK_LATENCY_LIMIT 0x26 20893e5343bdSAlex Deucher #define ixD3F3_PCIE_TX_CREDITS_ADVT_P 0x30 20903e5343bdSAlex Deucher #define ixD3F3_PCIE_TX_CREDITS_ADVT_NP 0x31 20913e5343bdSAlex Deucher #define ixD3F3_PCIE_TX_CREDITS_ADVT_CPL 0x32 20923e5343bdSAlex Deucher #define ixD3F3_PCIE_TX_CREDITS_INIT_P 0x33 20933e5343bdSAlex Deucher #define ixD3F3_PCIE_TX_CREDITS_INIT_NP 0x34 20943e5343bdSAlex Deucher #define ixD3F3_PCIE_TX_CREDITS_INIT_CPL 0x35 20953e5343bdSAlex Deucher #define ixD3F3_PCIE_TX_CREDITS_STATUS 0x36 20963e5343bdSAlex Deucher #define ixD3F3_PCIE_TX_CREDITS_FCU_THRESHOLD 0x37 20973e5343bdSAlex Deucher #define ixD3F3_PCIE_P_PORT_LANE_STATUS 0x50 20983e5343bdSAlex Deucher #define ixD3F3_PCIE_FC_P 0x60 20993e5343bdSAlex Deucher #define ixD3F3_PCIE_FC_NP 0x61 21003e5343bdSAlex Deucher #define ixD3F3_PCIE_FC_CPL 0x62 21013e5343bdSAlex Deucher #define ixD3F3_PCIE_ERR_CNTL 0x6a 21023e5343bdSAlex Deucher #define ixD3F3_PCIE_RX_CNTL 0x70 21033e5343bdSAlex Deucher #define ixD3F3_PCIE_RX_EXPECTED_SEQNUM 0x71 21043e5343bdSAlex Deucher #define ixD3F3_PCIE_RX_VENDOR_SPECIFIC 0x72 21053e5343bdSAlex Deucher #define ixD3F3_PCIE_RX_CNTL3 0x74 21063e5343bdSAlex Deucher #define ixD3F3_PCIE_RX_CREDITS_ALLOCATED_P 0x80 21073e5343bdSAlex Deucher #define ixD3F3_PCIE_RX_CREDITS_ALLOCATED_NP 0x81 21083e5343bdSAlex Deucher #define ixD3F3_PCIE_RX_CREDITS_ALLOCATED_CPL 0x82 21093e5343bdSAlex Deucher #define ixD3F3_PCIEP_ERROR_INJECT_PHYSICAL 0x83 21103e5343bdSAlex Deucher #define ixD3F3_PCIEP_ERROR_INJECT_TRANSACTION 0x84 21113e5343bdSAlex Deucher #define ixD3F3_PCIE_LC_CNTL 0xa0 21123e5343bdSAlex Deucher #define ixD3F3_PCIE_LC_CNTL2 0xb1 21133e5343bdSAlex Deucher #define ixD3F3_PCIE_LC_CNTL3 0xb5 21143e5343bdSAlex Deucher #define ixD3F3_PCIE_LC_CNTL4 0xb6 21153e5343bdSAlex Deucher #define ixD3F3_PCIE_LC_CNTL5 0xb7 21163e5343bdSAlex Deucher #define ixD3F3_PCIE_LC_CNTL6 0xbb 21173e5343bdSAlex Deucher #define ixD3F3_PCIE_LC_BW_CHANGE_CNTL 0xb2 21183e5343bdSAlex Deucher #define ixD3F3_PCIE_LC_TRAINING_CNTL 0xa1 21193e5343bdSAlex Deucher #define ixD3F3_PCIE_LC_LINK_WIDTH_CNTL 0xa2 21203e5343bdSAlex Deucher #define ixD3F3_PCIE_LC_N_FTS_CNTL 0xa3 21213e5343bdSAlex Deucher #define ixD3F3_PCIE_LC_SPEED_CNTL 0xa4 21223e5343bdSAlex Deucher #define ixD3F3_PCIE_LC_CDR_CNTL 0xb3 21233e5343bdSAlex Deucher #define ixD3F3_PCIE_LC_LANE_CNTL 0xb4 21243e5343bdSAlex Deucher #define ixD3F3_PCIE_LC_FORCE_COEFF 0xb8 21253e5343bdSAlex Deucher #define ixD3F3_PCIE_LC_BEST_EQ_SETTINGS 0xb9 21263e5343bdSAlex Deucher #define ixD3F3_PCIE_LC_FORCE_EQ_REQ_COEFF 0xba 21273e5343bdSAlex Deucher #define ixD3F3_PCIE_LC_STATE0 0xa5 21283e5343bdSAlex Deucher #define ixD3F3_PCIE_LC_STATE1 0xa6 21293e5343bdSAlex Deucher #define ixD3F3_PCIE_LC_STATE2 0xa7 21303e5343bdSAlex Deucher #define ixD3F3_PCIE_LC_STATE3 0xa8 21313e5343bdSAlex Deucher #define ixD3F3_PCIE_LC_STATE4 0xa9 21323e5343bdSAlex Deucher #define ixD3F3_PCIE_LC_STATE5 0xaa 21333e5343bdSAlex Deucher #define ixD3F3_PCIEP_STRAP_LC 0xc0 21343e5343bdSAlex Deucher #define ixD3F3_PCIEP_STRAP_MISC 0xc1 21353e5343bdSAlex Deucher #define ixD3F3_PCIEP_BCH_ECC_CNTL 0xd0 21363e5343bdSAlex Deucher #define ixD3F3_PCIEP_HPGI_PRIVATE 0xd2 21373e5343bdSAlex Deucher #define ixD3F3_PCIEP_HPGI 0xda 21383e5343bdSAlex Deucher #define ixD3F3_VENDOR_ID 0x9000000 21393e5343bdSAlex Deucher #define ixD3F3_DEVICE_ID 0x9000000 21403e5343bdSAlex Deucher #define ixD3F3_COMMAND 0x9000001 21413e5343bdSAlex Deucher #define ixD3F3_STATUS 0x9000001 21423e5343bdSAlex Deucher #define ixD3F3_REVISION_ID 0x9000002 21433e5343bdSAlex Deucher #define ixD3F3_PROG_INTERFACE 0x9000002 21443e5343bdSAlex Deucher #define ixD3F3_SUB_CLASS 0x9000002 21453e5343bdSAlex Deucher #define ixD3F3_BASE_CLASS 0x9000002 21463e5343bdSAlex Deucher #define ixD3F3_CACHE_LINE 0x9000003 21473e5343bdSAlex Deucher #define ixD3F3_LATENCY 0x9000003 21483e5343bdSAlex Deucher #define ixD3F3_HEADER 0x9000003 21493e5343bdSAlex Deucher #define ixD3F3_BIST 0x9000003 21503e5343bdSAlex Deucher #define ixD3F3_SUB_BUS_NUMBER_LATENCY 0x9000006 21513e5343bdSAlex Deucher #define ixD3F3_IO_BASE_LIMIT 0x9000007 21523e5343bdSAlex Deucher #define ixD3F3_SECONDARY_STATUS 0x9000007 21533e5343bdSAlex Deucher #define ixD3F3_MEM_BASE_LIMIT 0x9000008 21543e5343bdSAlex Deucher #define ixD3F3_PREF_BASE_LIMIT 0x9000009 21553e5343bdSAlex Deucher #define ixD3F3_PREF_BASE_UPPER 0x900000a 21563e5343bdSAlex Deucher #define ixD3F3_PREF_LIMIT_UPPER 0x900000b 21573e5343bdSAlex Deucher #define ixD3F3_IO_BASE_LIMIT_HI 0x900000c 21583e5343bdSAlex Deucher #define ixD3F3_IRQ_BRIDGE_CNTL 0x900000f 21593e5343bdSAlex Deucher #define ixD3F3_CAP_PTR 0x900000d 21603e5343bdSAlex Deucher #define ixD3F3_INTERRUPT_LINE 0x900000f 21613e5343bdSAlex Deucher #define ixD3F3_INTERRUPT_PIN 0x900000f 21623e5343bdSAlex Deucher #define ixD3F3_EXT_BRIDGE_CNTL 0x9000010 21633e5343bdSAlex Deucher #define ixD3F3_PMI_CAP_LIST 0x9000014 21643e5343bdSAlex Deucher #define ixD3F3_PMI_CAP 0x9000014 21653e5343bdSAlex Deucher #define ixD3F3_PMI_STATUS_CNTL 0x9000015 21663e5343bdSAlex Deucher #define ixD3F3_PCIE_CAP_LIST 0x9000016 21673e5343bdSAlex Deucher #define ixD3F3_PCIE_CAP 0x9000016 21683e5343bdSAlex Deucher #define ixD3F3_DEVICE_CAP 0x9000017 21693e5343bdSAlex Deucher #define ixD3F3_DEVICE_CNTL 0x9000018 21703e5343bdSAlex Deucher #define ixD3F3_DEVICE_STATUS 0x9000018 21713e5343bdSAlex Deucher #define ixD3F3_LINK_CAP 0x9000019 21723e5343bdSAlex Deucher #define ixD3F3_LINK_CNTL 0x900001a 21733e5343bdSAlex Deucher #define ixD3F3_LINK_STATUS 0x900001a 21743e5343bdSAlex Deucher #define ixD3F3_SLOT_CAP 0x900001b 21753e5343bdSAlex Deucher #define ixD3F3_SLOT_CNTL 0x900001c 21763e5343bdSAlex Deucher #define ixD3F3_SLOT_STATUS 0x900001c 21773e5343bdSAlex Deucher #define ixD3F3_ROOT_CNTL 0x900001d 21783e5343bdSAlex Deucher #define ixD3F3_ROOT_CAP 0x900001d 21793e5343bdSAlex Deucher #define ixD3F3_ROOT_STATUS 0x900001e 21803e5343bdSAlex Deucher #define ixD3F3_DEVICE_CAP2 0x900001f 21813e5343bdSAlex Deucher #define ixD3F3_DEVICE_CNTL2 0x9000020 21823e5343bdSAlex Deucher #define ixD3F3_DEVICE_STATUS2 0x9000020 21833e5343bdSAlex Deucher #define ixD3F3_LINK_CAP2 0x9000021 21843e5343bdSAlex Deucher #define ixD3F3_LINK_CNTL2 0x9000022 21853e5343bdSAlex Deucher #define ixD3F3_LINK_STATUS2 0x9000022 21863e5343bdSAlex Deucher #define ixD3F3_SLOT_CAP2 0x9000023 21873e5343bdSAlex Deucher #define ixD3F3_SLOT_CNTL2 0x9000024 21883e5343bdSAlex Deucher #define ixD3F3_SLOT_STATUS2 0x9000024 21893e5343bdSAlex Deucher #define ixD3F3_MSI_CAP_LIST 0x9000028 21903e5343bdSAlex Deucher #define ixD3F3_MSI_MSG_CNTL 0x9000028 21913e5343bdSAlex Deucher #define ixD3F3_MSI_MSG_ADDR_LO 0x9000029 21923e5343bdSAlex Deucher #define ixD3F3_MSI_MSG_ADDR_HI 0x900002a 21933e5343bdSAlex Deucher #define ixD3F3_MSI_MSG_DATA_64 0x900002b 21943e5343bdSAlex Deucher #define ixD3F3_MSI_MSG_DATA 0x900002a 21953e5343bdSAlex Deucher #define ixD3F3_SSID_CAP_LIST 0x9000030 21963e5343bdSAlex Deucher #define ixD3F3_SSID_CAP 0x9000031 21973e5343bdSAlex Deucher #define ixD3F3_MSI_MAP_CAP_LIST 0x9000032 21983e5343bdSAlex Deucher #define ixD3F3_MSI_MAP_CAP 0x9000032 21993e5343bdSAlex Deucher #define ixD3F3_MSI_MAP_ADDR_LO 0x9000033 22003e5343bdSAlex Deucher #define ixD3F3_MSI_MAP_ADDR_HI 0x9000034 22013e5343bdSAlex Deucher #define ixD3F3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x9000040 22023e5343bdSAlex Deucher #define ixD3F3_PCIE_VENDOR_SPECIFIC_HDR 0x9000041 22033e5343bdSAlex Deucher #define ixD3F3_PCIE_VENDOR_SPECIFIC1 0x9000042 22043e5343bdSAlex Deucher #define ixD3F3_PCIE_VENDOR_SPECIFIC2 0x9000043 22053e5343bdSAlex Deucher #define ixD3F3_PCIE_VC_ENH_CAP_LIST 0x9000044 22063e5343bdSAlex Deucher #define ixD3F3_PCIE_PORT_VC_CAP_REG1 0x9000045 22073e5343bdSAlex Deucher #define ixD3F3_PCIE_PORT_VC_CAP_REG2 0x9000046 22083e5343bdSAlex Deucher #define ixD3F3_PCIE_PORT_VC_CNTL 0x9000047 22093e5343bdSAlex Deucher #define ixD3F3_PCIE_PORT_VC_STATUS 0x9000047 22103e5343bdSAlex Deucher #define ixD3F3_PCIE_VC0_RESOURCE_CAP 0x9000048 22113e5343bdSAlex Deucher #define ixD3F3_PCIE_VC0_RESOURCE_CNTL 0x9000049 22123e5343bdSAlex Deucher #define ixD3F3_PCIE_VC0_RESOURCE_STATUS 0x900004a 22133e5343bdSAlex Deucher #define ixD3F3_PCIE_VC1_RESOURCE_CAP 0x900004b 22143e5343bdSAlex Deucher #define ixD3F3_PCIE_VC1_RESOURCE_CNTL 0x900004c 22153e5343bdSAlex Deucher #define ixD3F3_PCIE_VC1_RESOURCE_STATUS 0x900004d 22163e5343bdSAlex Deucher #define ixD3F3_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 0x9000050 22173e5343bdSAlex Deucher #define ixD3F3_PCIE_DEV_SERIAL_NUM_DW1 0x9000051 22183e5343bdSAlex Deucher #define ixD3F3_PCIE_DEV_SERIAL_NUM_DW2 0x9000052 22193e5343bdSAlex Deucher #define ixD3F3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x9000054 22203e5343bdSAlex Deucher #define ixD3F3_PCIE_UNCORR_ERR_STATUS 0x9000055 22213e5343bdSAlex Deucher #define ixD3F3_PCIE_UNCORR_ERR_MASK 0x9000056 22223e5343bdSAlex Deucher #define ixD3F3_PCIE_UNCORR_ERR_SEVERITY 0x9000057 22233e5343bdSAlex Deucher #define ixD3F3_PCIE_CORR_ERR_STATUS 0x9000058 22243e5343bdSAlex Deucher #define ixD3F3_PCIE_CORR_ERR_MASK 0x9000059 22253e5343bdSAlex Deucher #define ixD3F3_PCIE_ADV_ERR_CAP_CNTL 0x900005a 22263e5343bdSAlex Deucher #define ixD3F3_PCIE_HDR_LOG0 0x900005b 22273e5343bdSAlex Deucher #define ixD3F3_PCIE_HDR_LOG1 0x900005c 22283e5343bdSAlex Deucher #define ixD3F3_PCIE_HDR_LOG2 0x900005d 22293e5343bdSAlex Deucher #define ixD3F3_PCIE_HDR_LOG3 0x900005e 22303e5343bdSAlex Deucher #define ixD3F3_PCIE_ROOT_ERR_CMD 0x900005f 22313e5343bdSAlex Deucher #define ixD3F3_PCIE_ROOT_ERR_STATUS 0x9000060 22323e5343bdSAlex Deucher #define ixD3F3_PCIE_ERR_SRC_ID 0x9000061 22333e5343bdSAlex Deucher #define ixD3F3_PCIE_TLP_PREFIX_LOG0 0x9000062 22343e5343bdSAlex Deucher #define ixD3F3_PCIE_TLP_PREFIX_LOG1 0x9000063 22353e5343bdSAlex Deucher #define ixD3F3_PCIE_TLP_PREFIX_LOG2 0x9000064 22363e5343bdSAlex Deucher #define ixD3F3_PCIE_TLP_PREFIX_LOG3 0x9000065 22373e5343bdSAlex Deucher #define ixD3F3_PCIE_SECONDARY_ENH_CAP_LIST 0x900009c 22383e5343bdSAlex Deucher #define ixD3F3_PCIE_LINK_CNTL3 0x900009d 22393e5343bdSAlex Deucher #define ixD3F3_PCIE_LANE_ERROR_STATUS 0x900009e 22403e5343bdSAlex Deucher #define ixD3F3_PCIE_LANE_0_EQUALIZATION_CNTL 0x900009f 22413e5343bdSAlex Deucher #define ixD3F3_PCIE_LANE_1_EQUALIZATION_CNTL 0x900009f 22423e5343bdSAlex Deucher #define ixD3F3_PCIE_LANE_2_EQUALIZATION_CNTL 0x90000a0 22433e5343bdSAlex Deucher #define ixD3F3_PCIE_LANE_3_EQUALIZATION_CNTL 0x90000a0 22443e5343bdSAlex Deucher #define ixD3F3_PCIE_LANE_4_EQUALIZATION_CNTL 0x90000a1 22453e5343bdSAlex Deucher #define ixD3F3_PCIE_LANE_5_EQUALIZATION_CNTL 0x90000a1 22463e5343bdSAlex Deucher #define ixD3F3_PCIE_LANE_6_EQUALIZATION_CNTL 0x90000a2 22473e5343bdSAlex Deucher #define ixD3F3_PCIE_LANE_7_EQUALIZATION_CNTL 0x90000a2 22483e5343bdSAlex Deucher #define ixD3F3_PCIE_LANE_8_EQUALIZATION_CNTL 0x90000a3 22493e5343bdSAlex Deucher #define ixD3F3_PCIE_LANE_9_EQUALIZATION_CNTL 0x90000a3 22503e5343bdSAlex Deucher #define ixD3F3_PCIE_LANE_10_EQUALIZATION_CNTL 0x90000a4 22513e5343bdSAlex Deucher #define ixD3F3_PCIE_LANE_11_EQUALIZATION_CNTL 0x90000a4 22523e5343bdSAlex Deucher #define ixD3F3_PCIE_LANE_12_EQUALIZATION_CNTL 0x90000a5 22533e5343bdSAlex Deucher #define ixD3F3_PCIE_LANE_13_EQUALIZATION_CNTL 0x90000a5 22543e5343bdSAlex Deucher #define ixD3F3_PCIE_LANE_14_EQUALIZATION_CNTL 0x90000a6 22553e5343bdSAlex Deucher #define ixD3F3_PCIE_LANE_15_EQUALIZATION_CNTL 0x90000a6 22563e5343bdSAlex Deucher #define ixD3F3_PCIE_ACS_ENH_CAP_LIST 0x90000a8 22573e5343bdSAlex Deucher #define ixD3F3_PCIE_ACS_CAP 0x90000a9 22583e5343bdSAlex Deucher #define ixD3F3_PCIE_ACS_CNTL 0x90000a9 22593e5343bdSAlex Deucher #define ixD3F3_PCIE_MC_ENH_CAP_LIST 0x90000bc 22603e5343bdSAlex Deucher #define ixD3F3_PCIE_MC_CAP 0x90000bd 22613e5343bdSAlex Deucher #define ixD3F3_PCIE_MC_CNTL 0x90000bd 22623e5343bdSAlex Deucher #define ixD3F3_PCIE_MC_ADDR0 0x90000be 22633e5343bdSAlex Deucher #define ixD3F3_PCIE_MC_ADDR1 0x90000bf 22643e5343bdSAlex Deucher #define ixD3F3_PCIE_MC_RCV0 0x90000c0 22653e5343bdSAlex Deucher #define ixD3F3_PCIE_MC_RCV1 0x90000c1 22663e5343bdSAlex Deucher #define ixD3F3_PCIE_MC_BLOCK_ALL0 0x90000c2 22673e5343bdSAlex Deucher #define ixD3F3_PCIE_MC_BLOCK_ALL1 0x90000c3 22683e5343bdSAlex Deucher #define ixD3F3_PCIE_MC_BLOCK_UNTRANSLATED_0 0x90000c4 22693e5343bdSAlex Deucher #define ixD3F3_PCIE_MC_BLOCK_UNTRANSLATED_1 0x90000c5 22703e5343bdSAlex Deucher #define ixD3F3_PCIE_MC_OVERLAY_BAR0 0x90000c6 22713e5343bdSAlex Deucher #define ixD3F3_PCIE_MC_OVERLAY_BAR1 0x90000c7 22723e5343bdSAlex Deucher #define ixD3F4_PCIE_PORT_INDEX 0xa000038 22733e5343bdSAlex Deucher #define ixD3F4_PCIE_PORT_DATA 0xa000039 22743e5343bdSAlex Deucher #define ixD3F4_PCIEP_RESERVED 0x0 22753e5343bdSAlex Deucher #define ixD3F4_PCIEP_SCRATCH 0x1 22763e5343bdSAlex Deucher #define ixD3F4_PCIEP_HW_DEBUG 0x2 22773e5343bdSAlex Deucher #define ixD3F4_PCIEP_PORT_CNTL 0x10 22783e5343bdSAlex Deucher #define ixD3F4_PCIE_TX_CNTL 0x20 22793e5343bdSAlex Deucher #define ixD3F4_PCIE_TX_REQUESTER_ID 0x21 22803e5343bdSAlex Deucher #define ixD3F4_PCIE_TX_VENDOR_SPECIFIC 0x22 22813e5343bdSAlex Deucher #define ixD3F4_PCIE_TX_REQUEST_NUM_CNTL 0x23 22823e5343bdSAlex Deucher #define ixD3F4_PCIE_TX_SEQ 0x24 22833e5343bdSAlex Deucher #define ixD3F4_PCIE_TX_REPLAY 0x25 22843e5343bdSAlex Deucher #define ixD3F4_PCIE_TX_ACK_LATENCY_LIMIT 0x26 22853e5343bdSAlex Deucher #define ixD3F4_PCIE_TX_CREDITS_ADVT_P 0x30 22863e5343bdSAlex Deucher #define ixD3F4_PCIE_TX_CREDITS_ADVT_NP 0x31 22873e5343bdSAlex Deucher #define ixD3F4_PCIE_TX_CREDITS_ADVT_CPL 0x32 22883e5343bdSAlex Deucher #define ixD3F4_PCIE_TX_CREDITS_INIT_P 0x33 22893e5343bdSAlex Deucher #define ixD3F4_PCIE_TX_CREDITS_INIT_NP 0x34 22903e5343bdSAlex Deucher #define ixD3F4_PCIE_TX_CREDITS_INIT_CPL 0x35 22913e5343bdSAlex Deucher #define ixD3F4_PCIE_TX_CREDITS_STATUS 0x36 22923e5343bdSAlex Deucher #define ixD3F4_PCIE_TX_CREDITS_FCU_THRESHOLD 0x37 22933e5343bdSAlex Deucher #define ixD3F4_PCIE_P_PORT_LANE_STATUS 0x50 22943e5343bdSAlex Deucher #define ixD3F4_PCIE_FC_P 0x60 22953e5343bdSAlex Deucher #define ixD3F4_PCIE_FC_NP 0x61 22963e5343bdSAlex Deucher #define ixD3F4_PCIE_FC_CPL 0x62 22973e5343bdSAlex Deucher #define ixD3F4_PCIE_ERR_CNTL 0x6a 22983e5343bdSAlex Deucher #define ixD3F4_PCIE_RX_CNTL 0x70 22993e5343bdSAlex Deucher #define ixD3F4_PCIE_RX_EXPECTED_SEQNUM 0x71 23003e5343bdSAlex Deucher #define ixD3F4_PCIE_RX_VENDOR_SPECIFIC 0x72 23013e5343bdSAlex Deucher #define ixD3F4_PCIE_RX_CNTL3 0x74 23023e5343bdSAlex Deucher #define ixD3F4_PCIE_RX_CREDITS_ALLOCATED_P 0x80 23033e5343bdSAlex Deucher #define ixD3F4_PCIE_RX_CREDITS_ALLOCATED_NP 0x81 23043e5343bdSAlex Deucher #define ixD3F4_PCIE_RX_CREDITS_ALLOCATED_CPL 0x82 23053e5343bdSAlex Deucher #define ixD3F4_PCIEP_ERROR_INJECT_PHYSICAL 0x83 23063e5343bdSAlex Deucher #define ixD3F4_PCIEP_ERROR_INJECT_TRANSACTION 0x84 23073e5343bdSAlex Deucher #define ixD3F4_PCIE_LC_CNTL 0xa0 23083e5343bdSAlex Deucher #define ixD3F4_PCIE_LC_CNTL2 0xb1 23093e5343bdSAlex Deucher #define ixD3F4_PCIE_LC_CNTL3 0xb5 23103e5343bdSAlex Deucher #define ixD3F4_PCIE_LC_CNTL4 0xb6 23113e5343bdSAlex Deucher #define ixD3F4_PCIE_LC_CNTL5 0xb7 23123e5343bdSAlex Deucher #define ixD3F4_PCIE_LC_CNTL6 0xbb 23133e5343bdSAlex Deucher #define ixD3F4_PCIE_LC_BW_CHANGE_CNTL 0xb2 23143e5343bdSAlex Deucher #define ixD3F4_PCIE_LC_TRAINING_CNTL 0xa1 23153e5343bdSAlex Deucher #define ixD3F4_PCIE_LC_LINK_WIDTH_CNTL 0xa2 23163e5343bdSAlex Deucher #define ixD3F4_PCIE_LC_N_FTS_CNTL 0xa3 23173e5343bdSAlex Deucher #define ixD3F4_PCIE_LC_SPEED_CNTL 0xa4 23183e5343bdSAlex Deucher #define ixD3F4_PCIE_LC_CDR_CNTL 0xb3 23193e5343bdSAlex Deucher #define ixD3F4_PCIE_LC_LANE_CNTL 0xb4 23203e5343bdSAlex Deucher #define ixD3F4_PCIE_LC_FORCE_COEFF 0xb8 23213e5343bdSAlex Deucher #define ixD3F4_PCIE_LC_BEST_EQ_SETTINGS 0xb9 23223e5343bdSAlex Deucher #define ixD3F4_PCIE_LC_FORCE_EQ_REQ_COEFF 0xba 23233e5343bdSAlex Deucher #define ixD3F4_PCIE_LC_STATE0 0xa5 23243e5343bdSAlex Deucher #define ixD3F4_PCIE_LC_STATE1 0xa6 23253e5343bdSAlex Deucher #define ixD3F4_PCIE_LC_STATE2 0xa7 23263e5343bdSAlex Deucher #define ixD3F4_PCIE_LC_STATE3 0xa8 23273e5343bdSAlex Deucher #define ixD3F4_PCIE_LC_STATE4 0xa9 23283e5343bdSAlex Deucher #define ixD3F4_PCIE_LC_STATE5 0xaa 23293e5343bdSAlex Deucher #define ixD3F4_PCIEP_STRAP_LC 0xc0 23303e5343bdSAlex Deucher #define ixD3F4_PCIEP_STRAP_MISC 0xc1 23313e5343bdSAlex Deucher #define ixD3F4_PCIEP_BCH_ECC_CNTL 0xd0 23323e5343bdSAlex Deucher #define ixD3F4_PCIEP_HPGI_PRIVATE 0xd2 23333e5343bdSAlex Deucher #define ixD3F4_PCIEP_HPGI 0xda 23343e5343bdSAlex Deucher #define ixD3F4_VENDOR_ID 0xa000000 23353e5343bdSAlex Deucher #define ixD3F4_DEVICE_ID 0xa000000 23363e5343bdSAlex Deucher #define ixD3F4_COMMAND 0xa000001 23373e5343bdSAlex Deucher #define ixD3F4_STATUS 0xa000001 23383e5343bdSAlex Deucher #define ixD3F4_REVISION_ID 0xa000002 23393e5343bdSAlex Deucher #define ixD3F4_PROG_INTERFACE 0xa000002 23403e5343bdSAlex Deucher #define ixD3F4_SUB_CLASS 0xa000002 23413e5343bdSAlex Deucher #define ixD3F4_BASE_CLASS 0xa000002 23423e5343bdSAlex Deucher #define ixD3F4_CACHE_LINE 0xa000003 23433e5343bdSAlex Deucher #define ixD3F4_LATENCY 0xa000003 23443e5343bdSAlex Deucher #define ixD3F4_HEADER 0xa000003 23453e5343bdSAlex Deucher #define ixD3F4_BIST 0xa000003 23463e5343bdSAlex Deucher #define ixD3F4_SUB_BUS_NUMBER_LATENCY 0xa000006 23473e5343bdSAlex Deucher #define ixD3F4_IO_BASE_LIMIT 0xa000007 23483e5343bdSAlex Deucher #define ixD3F4_SECONDARY_STATUS 0xa000007 23493e5343bdSAlex Deucher #define ixD3F4_MEM_BASE_LIMIT 0xa000008 23503e5343bdSAlex Deucher #define ixD3F4_PREF_BASE_LIMIT 0xa000009 23513e5343bdSAlex Deucher #define ixD3F4_PREF_BASE_UPPER 0xa00000a 23523e5343bdSAlex Deucher #define ixD3F4_PREF_LIMIT_UPPER 0xa00000b 23533e5343bdSAlex Deucher #define ixD3F4_IO_BASE_LIMIT_HI 0xa00000c 23543e5343bdSAlex Deucher #define ixD3F4_IRQ_BRIDGE_CNTL 0xa00000f 23553e5343bdSAlex Deucher #define ixD3F4_CAP_PTR 0xa00000d 23563e5343bdSAlex Deucher #define ixD3F4_INTERRUPT_LINE 0xa00000f 23573e5343bdSAlex Deucher #define ixD3F4_INTERRUPT_PIN 0xa00000f 23583e5343bdSAlex Deucher #define ixD3F4_EXT_BRIDGE_CNTL 0xa000010 23593e5343bdSAlex Deucher #define ixD3F4_PMI_CAP_LIST 0xa000014 23603e5343bdSAlex Deucher #define ixD3F4_PMI_CAP 0xa000014 23613e5343bdSAlex Deucher #define ixD3F4_PMI_STATUS_CNTL 0xa000015 23623e5343bdSAlex Deucher #define ixD3F4_PCIE_CAP_LIST 0xa000016 23633e5343bdSAlex Deucher #define ixD3F4_PCIE_CAP 0xa000016 23643e5343bdSAlex Deucher #define ixD3F4_DEVICE_CAP 0xa000017 23653e5343bdSAlex Deucher #define ixD3F4_DEVICE_CNTL 0xa000018 23663e5343bdSAlex Deucher #define ixD3F4_DEVICE_STATUS 0xa000018 23673e5343bdSAlex Deucher #define ixD3F4_LINK_CAP 0xa000019 23683e5343bdSAlex Deucher #define ixD3F4_LINK_CNTL 0xa00001a 23693e5343bdSAlex Deucher #define ixD3F4_LINK_STATUS 0xa00001a 23703e5343bdSAlex Deucher #define ixD3F4_SLOT_CAP 0xa00001b 23713e5343bdSAlex Deucher #define ixD3F4_SLOT_CNTL 0xa00001c 23723e5343bdSAlex Deucher #define ixD3F4_SLOT_STATUS 0xa00001c 23733e5343bdSAlex Deucher #define ixD3F4_ROOT_CNTL 0xa00001d 23743e5343bdSAlex Deucher #define ixD3F4_ROOT_CAP 0xa00001d 23753e5343bdSAlex Deucher #define ixD3F4_ROOT_STATUS 0xa00001e 23763e5343bdSAlex Deucher #define ixD3F4_DEVICE_CAP2 0xa00001f 23773e5343bdSAlex Deucher #define ixD3F4_DEVICE_CNTL2 0xa000020 23783e5343bdSAlex Deucher #define ixD3F4_DEVICE_STATUS2 0xa000020 23793e5343bdSAlex Deucher #define ixD3F4_LINK_CAP2 0xa000021 23803e5343bdSAlex Deucher #define ixD3F4_LINK_CNTL2 0xa000022 23813e5343bdSAlex Deucher #define ixD3F4_LINK_STATUS2 0xa000022 23823e5343bdSAlex Deucher #define ixD3F4_SLOT_CAP2 0xa000023 23833e5343bdSAlex Deucher #define ixD3F4_SLOT_CNTL2 0xa000024 23843e5343bdSAlex Deucher #define ixD3F4_SLOT_STATUS2 0xa000024 23853e5343bdSAlex Deucher #define ixD3F4_MSI_CAP_LIST 0xa000028 23863e5343bdSAlex Deucher #define ixD3F4_MSI_MSG_CNTL 0xa000028 23873e5343bdSAlex Deucher #define ixD3F4_MSI_MSG_ADDR_LO 0xa000029 23883e5343bdSAlex Deucher #define ixD3F4_MSI_MSG_ADDR_HI 0xa00002a 23893e5343bdSAlex Deucher #define ixD3F4_MSI_MSG_DATA_64 0xa00002b 23903e5343bdSAlex Deucher #define ixD3F4_MSI_MSG_DATA 0xa00002a 23913e5343bdSAlex Deucher #define ixD3F4_SSID_CAP_LIST 0xa000030 23923e5343bdSAlex Deucher #define ixD3F4_SSID_CAP 0xa000031 23933e5343bdSAlex Deucher #define ixD3F4_MSI_MAP_CAP_LIST 0xa000032 23943e5343bdSAlex Deucher #define ixD3F4_MSI_MAP_CAP 0xa000032 23953e5343bdSAlex Deucher #define ixD3F4_MSI_MAP_ADDR_LO 0xa000033 23963e5343bdSAlex Deucher #define ixD3F4_MSI_MAP_ADDR_HI 0xa000034 23973e5343bdSAlex Deucher #define ixD3F4_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0xa000040 23983e5343bdSAlex Deucher #define ixD3F4_PCIE_VENDOR_SPECIFIC_HDR 0xa000041 23993e5343bdSAlex Deucher #define ixD3F4_PCIE_VENDOR_SPECIFIC1 0xa000042 24003e5343bdSAlex Deucher #define ixD3F4_PCIE_VENDOR_SPECIFIC2 0xa000043 24013e5343bdSAlex Deucher #define ixD3F4_PCIE_VC_ENH_CAP_LIST 0xa000044 24023e5343bdSAlex Deucher #define ixD3F4_PCIE_PORT_VC_CAP_REG1 0xa000045 24033e5343bdSAlex Deucher #define ixD3F4_PCIE_PORT_VC_CAP_REG2 0xa000046 24043e5343bdSAlex Deucher #define ixD3F4_PCIE_PORT_VC_CNTL 0xa000047 24053e5343bdSAlex Deucher #define ixD3F4_PCIE_PORT_VC_STATUS 0xa000047 24063e5343bdSAlex Deucher #define ixD3F4_PCIE_VC0_RESOURCE_CAP 0xa000048 24073e5343bdSAlex Deucher #define ixD3F4_PCIE_VC0_RESOURCE_CNTL 0xa000049 24083e5343bdSAlex Deucher #define ixD3F4_PCIE_VC0_RESOURCE_STATUS 0xa00004a 24093e5343bdSAlex Deucher #define ixD3F4_PCIE_VC1_RESOURCE_CAP 0xa00004b 24103e5343bdSAlex Deucher #define ixD3F4_PCIE_VC1_RESOURCE_CNTL 0xa00004c 24113e5343bdSAlex Deucher #define ixD3F4_PCIE_VC1_RESOURCE_STATUS 0xa00004d 24123e5343bdSAlex Deucher #define ixD3F4_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 0xa000050 24133e5343bdSAlex Deucher #define ixD3F4_PCIE_DEV_SERIAL_NUM_DW1 0xa000051 24143e5343bdSAlex Deucher #define ixD3F4_PCIE_DEV_SERIAL_NUM_DW2 0xa000052 24153e5343bdSAlex Deucher #define ixD3F4_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0xa000054 24163e5343bdSAlex Deucher #define ixD3F4_PCIE_UNCORR_ERR_STATUS 0xa000055 24173e5343bdSAlex Deucher #define ixD3F4_PCIE_UNCORR_ERR_MASK 0xa000056 24183e5343bdSAlex Deucher #define ixD3F4_PCIE_UNCORR_ERR_SEVERITY 0xa000057 24193e5343bdSAlex Deucher #define ixD3F4_PCIE_CORR_ERR_STATUS 0xa000058 24203e5343bdSAlex Deucher #define ixD3F4_PCIE_CORR_ERR_MASK 0xa000059 24213e5343bdSAlex Deucher #define ixD3F4_PCIE_ADV_ERR_CAP_CNTL 0xa00005a 24223e5343bdSAlex Deucher #define ixD3F4_PCIE_HDR_LOG0 0xa00005b 24233e5343bdSAlex Deucher #define ixD3F4_PCIE_HDR_LOG1 0xa00005c 24243e5343bdSAlex Deucher #define ixD3F4_PCIE_HDR_LOG2 0xa00005d 24253e5343bdSAlex Deucher #define ixD3F4_PCIE_HDR_LOG3 0xa00005e 24263e5343bdSAlex Deucher #define ixD3F4_PCIE_ROOT_ERR_CMD 0xa00005f 24273e5343bdSAlex Deucher #define ixD3F4_PCIE_ROOT_ERR_STATUS 0xa000060 24283e5343bdSAlex Deucher #define ixD3F4_PCIE_ERR_SRC_ID 0xa000061 24293e5343bdSAlex Deucher #define ixD3F4_PCIE_TLP_PREFIX_LOG0 0xa000062 24303e5343bdSAlex Deucher #define ixD3F4_PCIE_TLP_PREFIX_LOG1 0xa000063 24313e5343bdSAlex Deucher #define ixD3F4_PCIE_TLP_PREFIX_LOG2 0xa000064 24323e5343bdSAlex Deucher #define ixD3F4_PCIE_TLP_PREFIX_LOG3 0xa000065 24333e5343bdSAlex Deucher #define ixD3F4_PCIE_SECONDARY_ENH_CAP_LIST 0xa00009c 24343e5343bdSAlex Deucher #define ixD3F4_PCIE_LINK_CNTL3 0xa00009d 24353e5343bdSAlex Deucher #define ixD3F4_PCIE_LANE_ERROR_STATUS 0xa00009e 24363e5343bdSAlex Deucher #define ixD3F4_PCIE_LANE_0_EQUALIZATION_CNTL 0xa00009f 24373e5343bdSAlex Deucher #define ixD3F4_PCIE_LANE_1_EQUALIZATION_CNTL 0xa00009f 24383e5343bdSAlex Deucher #define ixD3F4_PCIE_LANE_2_EQUALIZATION_CNTL 0xa0000a0 24393e5343bdSAlex Deucher #define ixD3F4_PCIE_LANE_3_EQUALIZATION_CNTL 0xa0000a0 24403e5343bdSAlex Deucher #define ixD3F4_PCIE_LANE_4_EQUALIZATION_CNTL 0xa0000a1 24413e5343bdSAlex Deucher #define ixD3F4_PCIE_LANE_5_EQUALIZATION_CNTL 0xa0000a1 24423e5343bdSAlex Deucher #define ixD3F4_PCIE_LANE_6_EQUALIZATION_CNTL 0xa0000a2 24433e5343bdSAlex Deucher #define ixD3F4_PCIE_LANE_7_EQUALIZATION_CNTL 0xa0000a2 24443e5343bdSAlex Deucher #define ixD3F4_PCIE_LANE_8_EQUALIZATION_CNTL 0xa0000a3 24453e5343bdSAlex Deucher #define ixD3F4_PCIE_LANE_9_EQUALIZATION_CNTL 0xa0000a3 24463e5343bdSAlex Deucher #define ixD3F4_PCIE_LANE_10_EQUALIZATION_CNTL 0xa0000a4 24473e5343bdSAlex Deucher #define ixD3F4_PCIE_LANE_11_EQUALIZATION_CNTL 0xa0000a4 24483e5343bdSAlex Deucher #define ixD3F4_PCIE_LANE_12_EQUALIZATION_CNTL 0xa0000a5 24493e5343bdSAlex Deucher #define ixD3F4_PCIE_LANE_13_EQUALIZATION_CNTL 0xa0000a5 24503e5343bdSAlex Deucher #define ixD3F4_PCIE_LANE_14_EQUALIZATION_CNTL 0xa0000a6 24513e5343bdSAlex Deucher #define ixD3F4_PCIE_LANE_15_EQUALIZATION_CNTL 0xa0000a6 24523e5343bdSAlex Deucher #define ixD3F4_PCIE_ACS_ENH_CAP_LIST 0xa0000a8 24533e5343bdSAlex Deucher #define ixD3F4_PCIE_ACS_CAP 0xa0000a9 24543e5343bdSAlex Deucher #define ixD3F4_PCIE_ACS_CNTL 0xa0000a9 24553e5343bdSAlex Deucher #define ixD3F4_PCIE_MC_ENH_CAP_LIST 0xa0000bc 24563e5343bdSAlex Deucher #define ixD3F4_PCIE_MC_CAP 0xa0000bd 24573e5343bdSAlex Deucher #define ixD3F4_PCIE_MC_CNTL 0xa0000bd 24583e5343bdSAlex Deucher #define ixD3F4_PCIE_MC_ADDR0 0xa0000be 24593e5343bdSAlex Deucher #define ixD3F4_PCIE_MC_ADDR1 0xa0000bf 24603e5343bdSAlex Deucher #define ixD3F4_PCIE_MC_RCV0 0xa0000c0 24613e5343bdSAlex Deucher #define ixD3F4_PCIE_MC_RCV1 0xa0000c1 24623e5343bdSAlex Deucher #define ixD3F4_PCIE_MC_BLOCK_ALL0 0xa0000c2 24633e5343bdSAlex Deucher #define ixD3F4_PCIE_MC_BLOCK_ALL1 0xa0000c3 24643e5343bdSAlex Deucher #define ixD3F4_PCIE_MC_BLOCK_UNTRANSLATED_0 0xa0000c4 24653e5343bdSAlex Deucher #define ixD3F4_PCIE_MC_BLOCK_UNTRANSLATED_1 0xa0000c5 24663e5343bdSAlex Deucher #define ixD3F4_PCIE_MC_OVERLAY_BAR0 0xa0000c6 24673e5343bdSAlex Deucher #define ixD3F4_PCIE_MC_OVERLAY_BAR1 0xa0000c7 24683e5343bdSAlex Deucher #define ixD3F5_PCIE_PORT_INDEX 0xb000038 24693e5343bdSAlex Deucher #define ixD3F5_PCIE_PORT_DATA 0xb000039 24703e5343bdSAlex Deucher #define ixD3F5_PCIEP_RESERVED 0x0 24713e5343bdSAlex Deucher #define ixD3F5_PCIEP_SCRATCH 0x1 24723e5343bdSAlex Deucher #define ixD3F5_PCIEP_HW_DEBUG 0x2 24733e5343bdSAlex Deucher #define ixD3F5_PCIEP_PORT_CNTL 0x10 24743e5343bdSAlex Deucher #define ixD3F5_PCIE_TX_CNTL 0x20 24753e5343bdSAlex Deucher #define ixD3F5_PCIE_TX_REQUESTER_ID 0x21 24763e5343bdSAlex Deucher #define ixD3F5_PCIE_TX_VENDOR_SPECIFIC 0x22 24773e5343bdSAlex Deucher #define ixD3F5_PCIE_TX_REQUEST_NUM_CNTL 0x23 24783e5343bdSAlex Deucher #define ixD3F5_PCIE_TX_SEQ 0x24 24793e5343bdSAlex Deucher #define ixD3F5_PCIE_TX_REPLAY 0x25 24803e5343bdSAlex Deucher #define ixD3F5_PCIE_TX_ACK_LATENCY_LIMIT 0x26 24813e5343bdSAlex Deucher #define ixD3F5_PCIE_TX_CREDITS_ADVT_P 0x30 24823e5343bdSAlex Deucher #define ixD3F5_PCIE_TX_CREDITS_ADVT_NP 0x31 24833e5343bdSAlex Deucher #define ixD3F5_PCIE_TX_CREDITS_ADVT_CPL 0x32 24843e5343bdSAlex Deucher #define ixD3F5_PCIE_TX_CREDITS_INIT_P 0x33 24853e5343bdSAlex Deucher #define ixD3F5_PCIE_TX_CREDITS_INIT_NP 0x34 24863e5343bdSAlex Deucher #define ixD3F5_PCIE_TX_CREDITS_INIT_CPL 0x35 24873e5343bdSAlex Deucher #define ixD3F5_PCIE_TX_CREDITS_STATUS 0x36 24883e5343bdSAlex Deucher #define ixD3F5_PCIE_TX_CREDITS_FCU_THRESHOLD 0x37 24893e5343bdSAlex Deucher #define ixD3F5_PCIE_P_PORT_LANE_STATUS 0x50 24903e5343bdSAlex Deucher #define ixD3F5_PCIE_FC_P 0x60 24913e5343bdSAlex Deucher #define ixD3F5_PCIE_FC_NP 0x61 24923e5343bdSAlex Deucher #define ixD3F5_PCIE_FC_CPL 0x62 24933e5343bdSAlex Deucher #define ixD3F5_PCIE_ERR_CNTL 0x6a 24943e5343bdSAlex Deucher #define ixD3F5_PCIE_RX_CNTL 0x70 24953e5343bdSAlex Deucher #define ixD3F5_PCIE_RX_EXPECTED_SEQNUM 0x71 24963e5343bdSAlex Deucher #define ixD3F5_PCIE_RX_VENDOR_SPECIFIC 0x72 24973e5343bdSAlex Deucher #define ixD3F5_PCIE_RX_CNTL3 0x74 24983e5343bdSAlex Deucher #define ixD3F5_PCIE_RX_CREDITS_ALLOCATED_P 0x80 24993e5343bdSAlex Deucher #define ixD3F5_PCIE_RX_CREDITS_ALLOCATED_NP 0x81 25003e5343bdSAlex Deucher #define ixD3F5_PCIE_RX_CREDITS_ALLOCATED_CPL 0x82 25013e5343bdSAlex Deucher #define ixD3F5_PCIEP_ERROR_INJECT_PHYSICAL 0x83 25023e5343bdSAlex Deucher #define ixD3F5_PCIEP_ERROR_INJECT_TRANSACTION 0x84 25033e5343bdSAlex Deucher #define ixD3F5_PCIE_LC_CNTL 0xa0 25043e5343bdSAlex Deucher #define ixD3F5_PCIE_LC_CNTL2 0xb1 25053e5343bdSAlex Deucher #define ixD3F5_PCIE_LC_CNTL3 0xb5 25063e5343bdSAlex Deucher #define ixD3F5_PCIE_LC_CNTL4 0xb6 25073e5343bdSAlex Deucher #define ixD3F5_PCIE_LC_CNTL5 0xb7 25083e5343bdSAlex Deucher #define ixD3F5_PCIE_LC_CNTL6 0xbb 25093e5343bdSAlex Deucher #define ixD3F5_PCIE_LC_BW_CHANGE_CNTL 0xb2 25103e5343bdSAlex Deucher #define ixD3F5_PCIE_LC_TRAINING_CNTL 0xa1 25113e5343bdSAlex Deucher #define ixD3F5_PCIE_LC_LINK_WIDTH_CNTL 0xa2 25123e5343bdSAlex Deucher #define ixD3F5_PCIE_LC_N_FTS_CNTL 0xa3 25133e5343bdSAlex Deucher #define ixD3F5_PCIE_LC_SPEED_CNTL 0xa4 25143e5343bdSAlex Deucher #define ixD3F5_PCIE_LC_CDR_CNTL 0xb3 25153e5343bdSAlex Deucher #define ixD3F5_PCIE_LC_LANE_CNTL 0xb4 25163e5343bdSAlex Deucher #define ixD3F5_PCIE_LC_FORCE_COEFF 0xb8 25173e5343bdSAlex Deucher #define ixD3F5_PCIE_LC_BEST_EQ_SETTINGS 0xb9 25183e5343bdSAlex Deucher #define ixD3F5_PCIE_LC_FORCE_EQ_REQ_COEFF 0xba 25193e5343bdSAlex Deucher #define ixD3F5_PCIE_LC_STATE0 0xa5 25203e5343bdSAlex Deucher #define ixD3F5_PCIE_LC_STATE1 0xa6 25213e5343bdSAlex Deucher #define ixD3F5_PCIE_LC_STATE2 0xa7 25223e5343bdSAlex Deucher #define ixD3F5_PCIE_LC_STATE3 0xa8 25233e5343bdSAlex Deucher #define ixD3F5_PCIE_LC_STATE4 0xa9 25243e5343bdSAlex Deucher #define ixD3F5_PCIE_LC_STATE5 0xaa 25253e5343bdSAlex Deucher #define ixD3F5_PCIEP_STRAP_LC 0xc0 25263e5343bdSAlex Deucher #define ixD3F5_PCIEP_STRAP_MISC 0xc1 25273e5343bdSAlex Deucher #define ixD3F5_PCIEP_BCH_ECC_CNTL 0xd0 25283e5343bdSAlex Deucher #define ixD3F5_PCIEP_HPGI_PRIVATE 0xd2 25293e5343bdSAlex Deucher #define ixD3F5_PCIEP_HPGI 0xda 25303e5343bdSAlex Deucher #define ixD3F5_VENDOR_ID 0xb000000 25313e5343bdSAlex Deucher #define ixD3F5_DEVICE_ID 0xb000000 25323e5343bdSAlex Deucher #define ixD3F5_COMMAND 0xb000001 25333e5343bdSAlex Deucher #define ixD3F5_STATUS 0xb000001 25343e5343bdSAlex Deucher #define ixD3F5_REVISION_ID 0xb000002 25353e5343bdSAlex Deucher #define ixD3F5_PROG_INTERFACE 0xb000002 25363e5343bdSAlex Deucher #define ixD3F5_SUB_CLASS 0xb000002 25373e5343bdSAlex Deucher #define ixD3F5_BASE_CLASS 0xb000002 25383e5343bdSAlex Deucher #define ixD3F5_CACHE_LINE 0xb000003 25393e5343bdSAlex Deucher #define ixD3F5_LATENCY 0xb000003 25403e5343bdSAlex Deucher #define ixD3F5_HEADER 0xb000003 25413e5343bdSAlex Deucher #define ixD3F5_BIST 0xb000003 25423e5343bdSAlex Deucher #define ixD3F5_SUB_BUS_NUMBER_LATENCY 0xb000006 25433e5343bdSAlex Deucher #define ixD3F5_IO_BASE_LIMIT 0xb000007 25443e5343bdSAlex Deucher #define ixD3F5_SECONDARY_STATUS 0xb000007 25453e5343bdSAlex Deucher #define ixD3F5_MEM_BASE_LIMIT 0xb000008 25463e5343bdSAlex Deucher #define ixD3F5_PREF_BASE_LIMIT 0xb000009 25473e5343bdSAlex Deucher #define ixD3F5_PREF_BASE_UPPER 0xb00000a 25483e5343bdSAlex Deucher #define ixD3F5_PREF_LIMIT_UPPER 0xb00000b 25493e5343bdSAlex Deucher #define ixD3F5_IO_BASE_LIMIT_HI 0xb00000c 25503e5343bdSAlex Deucher #define ixD3F5_IRQ_BRIDGE_CNTL 0xb00000f 25513e5343bdSAlex Deucher #define ixD3F5_CAP_PTR 0xb00000d 25523e5343bdSAlex Deucher #define ixD3F5_INTERRUPT_LINE 0xb00000f 25533e5343bdSAlex Deucher #define ixD3F5_INTERRUPT_PIN 0xb00000f 25543e5343bdSAlex Deucher #define ixD3F5_EXT_BRIDGE_CNTL 0xb000010 25553e5343bdSAlex Deucher #define ixD3F5_PMI_CAP_LIST 0xb000014 25563e5343bdSAlex Deucher #define ixD3F5_PMI_CAP 0xb000014 25573e5343bdSAlex Deucher #define ixD3F5_PMI_STATUS_CNTL 0xb000015 25583e5343bdSAlex Deucher #define ixD3F5_PCIE_CAP_LIST 0xb000016 25593e5343bdSAlex Deucher #define ixD3F5_PCIE_CAP 0xb000016 25603e5343bdSAlex Deucher #define ixD3F5_DEVICE_CAP 0xb000017 25613e5343bdSAlex Deucher #define ixD3F5_DEVICE_CNTL 0xb000018 25623e5343bdSAlex Deucher #define ixD3F5_DEVICE_STATUS 0xb000018 25633e5343bdSAlex Deucher #define ixD3F5_LINK_CAP 0xb000019 25643e5343bdSAlex Deucher #define ixD3F5_LINK_CNTL 0xb00001a 25653e5343bdSAlex Deucher #define ixD3F5_LINK_STATUS 0xb00001a 25663e5343bdSAlex Deucher #define ixD3F5_SLOT_CAP 0xb00001b 25673e5343bdSAlex Deucher #define ixD3F5_SLOT_CNTL 0xb00001c 25683e5343bdSAlex Deucher #define ixD3F5_SLOT_STATUS 0xb00001c 25693e5343bdSAlex Deucher #define ixD3F5_ROOT_CNTL 0xb00001d 25703e5343bdSAlex Deucher #define ixD3F5_ROOT_CAP 0xb00001d 25713e5343bdSAlex Deucher #define ixD3F5_ROOT_STATUS 0xb00001e 25723e5343bdSAlex Deucher #define ixD3F5_DEVICE_CAP2 0xb00001f 25733e5343bdSAlex Deucher #define ixD3F5_DEVICE_CNTL2 0xb000020 25743e5343bdSAlex Deucher #define ixD3F5_DEVICE_STATUS2 0xb000020 25753e5343bdSAlex Deucher #define ixD3F5_LINK_CAP2 0xb000021 25763e5343bdSAlex Deucher #define ixD3F5_LINK_CNTL2 0xb000022 25773e5343bdSAlex Deucher #define ixD3F5_LINK_STATUS2 0xb000022 25783e5343bdSAlex Deucher #define ixD3F5_SLOT_CAP2 0xb000023 25793e5343bdSAlex Deucher #define ixD3F5_SLOT_CNTL2 0xb000024 25803e5343bdSAlex Deucher #define ixD3F5_SLOT_STATUS2 0xb000024 25813e5343bdSAlex Deucher #define ixD3F5_MSI_CAP_LIST 0xb000028 25823e5343bdSAlex Deucher #define ixD3F5_MSI_MSG_CNTL 0xb000028 25833e5343bdSAlex Deucher #define ixD3F5_MSI_MSG_ADDR_LO 0xb000029 25843e5343bdSAlex Deucher #define ixD3F5_MSI_MSG_ADDR_HI 0xb00002a 25853e5343bdSAlex Deucher #define ixD3F5_MSI_MSG_DATA_64 0xb00002b 25863e5343bdSAlex Deucher #define ixD3F5_MSI_MSG_DATA 0xb00002a 25873e5343bdSAlex Deucher #define ixD3F5_SSID_CAP_LIST 0xb000030 25883e5343bdSAlex Deucher #define ixD3F5_SSID_CAP 0xb000031 25893e5343bdSAlex Deucher #define ixD3F5_MSI_MAP_CAP_LIST 0xb000032 25903e5343bdSAlex Deucher #define ixD3F5_MSI_MAP_CAP 0xb000032 25913e5343bdSAlex Deucher #define ixD3F5_MSI_MAP_ADDR_LO 0xb000033 25923e5343bdSAlex Deucher #define ixD3F5_MSI_MAP_ADDR_HI 0xb000034 25933e5343bdSAlex Deucher #define ixD3F5_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0xb000040 25943e5343bdSAlex Deucher #define ixD3F5_PCIE_VENDOR_SPECIFIC_HDR 0xb000041 25953e5343bdSAlex Deucher #define ixD3F5_PCIE_VENDOR_SPECIFIC1 0xb000042 25963e5343bdSAlex Deucher #define ixD3F5_PCIE_VENDOR_SPECIFIC2 0xb000043 25973e5343bdSAlex Deucher #define ixD3F5_PCIE_VC_ENH_CAP_LIST 0xb000044 25983e5343bdSAlex Deucher #define ixD3F5_PCIE_PORT_VC_CAP_REG1 0xb000045 25993e5343bdSAlex Deucher #define ixD3F5_PCIE_PORT_VC_CAP_REG2 0xb000046 26003e5343bdSAlex Deucher #define ixD3F5_PCIE_PORT_VC_CNTL 0xb000047 26013e5343bdSAlex Deucher #define ixD3F5_PCIE_PORT_VC_STATUS 0xb000047 26023e5343bdSAlex Deucher #define ixD3F5_PCIE_VC0_RESOURCE_CAP 0xb000048 26033e5343bdSAlex Deucher #define ixD3F5_PCIE_VC0_RESOURCE_CNTL 0xb000049 26043e5343bdSAlex Deucher #define ixD3F5_PCIE_VC0_RESOURCE_STATUS 0xb00004a 26053e5343bdSAlex Deucher #define ixD3F5_PCIE_VC1_RESOURCE_CAP 0xb00004b 26063e5343bdSAlex Deucher #define ixD3F5_PCIE_VC1_RESOURCE_CNTL 0xb00004c 26073e5343bdSAlex Deucher #define ixD3F5_PCIE_VC1_RESOURCE_STATUS 0xb00004d 26083e5343bdSAlex Deucher #define ixD3F5_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 0xb000050 26093e5343bdSAlex Deucher #define ixD3F5_PCIE_DEV_SERIAL_NUM_DW1 0xb000051 26103e5343bdSAlex Deucher #define ixD3F5_PCIE_DEV_SERIAL_NUM_DW2 0xb000052 26113e5343bdSAlex Deucher #define ixD3F5_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0xb000054 26123e5343bdSAlex Deucher #define ixD3F5_PCIE_UNCORR_ERR_STATUS 0xb000055 26133e5343bdSAlex Deucher #define ixD3F5_PCIE_UNCORR_ERR_MASK 0xb000056 26143e5343bdSAlex Deucher #define ixD3F5_PCIE_UNCORR_ERR_SEVERITY 0xb000057 26153e5343bdSAlex Deucher #define ixD3F5_PCIE_CORR_ERR_STATUS 0xb000058 26163e5343bdSAlex Deucher #define ixD3F5_PCIE_CORR_ERR_MASK 0xb000059 26173e5343bdSAlex Deucher #define ixD3F5_PCIE_ADV_ERR_CAP_CNTL 0xb00005a 26183e5343bdSAlex Deucher #define ixD3F5_PCIE_HDR_LOG0 0xb00005b 26193e5343bdSAlex Deucher #define ixD3F5_PCIE_HDR_LOG1 0xb00005c 26203e5343bdSAlex Deucher #define ixD3F5_PCIE_HDR_LOG2 0xb00005d 26213e5343bdSAlex Deucher #define ixD3F5_PCIE_HDR_LOG3 0xb00005e 26223e5343bdSAlex Deucher #define ixD3F5_PCIE_ROOT_ERR_CMD 0xb00005f 26233e5343bdSAlex Deucher #define ixD3F5_PCIE_ROOT_ERR_STATUS 0xb000060 26243e5343bdSAlex Deucher #define ixD3F5_PCIE_ERR_SRC_ID 0xb000061 26253e5343bdSAlex Deucher #define ixD3F5_PCIE_TLP_PREFIX_LOG0 0xb000062 26263e5343bdSAlex Deucher #define ixD3F5_PCIE_TLP_PREFIX_LOG1 0xb000063 26273e5343bdSAlex Deucher #define ixD3F5_PCIE_TLP_PREFIX_LOG2 0xb000064 26283e5343bdSAlex Deucher #define ixD3F5_PCIE_TLP_PREFIX_LOG3 0xb000065 26293e5343bdSAlex Deucher #define ixD3F5_PCIE_SECONDARY_ENH_CAP_LIST 0xb00009c 26303e5343bdSAlex Deucher #define ixD3F5_PCIE_LINK_CNTL3 0xb00009d 26313e5343bdSAlex Deucher #define ixD3F5_PCIE_LANE_ERROR_STATUS 0xb00009e 26323e5343bdSAlex Deucher #define ixD3F5_PCIE_LANE_0_EQUALIZATION_CNTL 0xb00009f 26333e5343bdSAlex Deucher #define ixD3F5_PCIE_LANE_1_EQUALIZATION_CNTL 0xb00009f 26343e5343bdSAlex Deucher #define ixD3F5_PCIE_LANE_2_EQUALIZATION_CNTL 0xb0000a0 26353e5343bdSAlex Deucher #define ixD3F5_PCIE_LANE_3_EQUALIZATION_CNTL 0xb0000a0 26363e5343bdSAlex Deucher #define ixD3F5_PCIE_LANE_4_EQUALIZATION_CNTL 0xb0000a1 26373e5343bdSAlex Deucher #define ixD3F5_PCIE_LANE_5_EQUALIZATION_CNTL 0xb0000a1 26383e5343bdSAlex Deucher #define ixD3F5_PCIE_LANE_6_EQUALIZATION_CNTL 0xb0000a2 26393e5343bdSAlex Deucher #define ixD3F5_PCIE_LANE_7_EQUALIZATION_CNTL 0xb0000a2 26403e5343bdSAlex Deucher #define ixD3F5_PCIE_LANE_8_EQUALIZATION_CNTL 0xb0000a3 26413e5343bdSAlex Deucher #define ixD3F5_PCIE_LANE_9_EQUALIZATION_CNTL 0xb0000a3 26423e5343bdSAlex Deucher #define ixD3F5_PCIE_LANE_10_EQUALIZATION_CNTL 0xb0000a4 26433e5343bdSAlex Deucher #define ixD3F5_PCIE_LANE_11_EQUALIZATION_CNTL 0xb0000a4 26443e5343bdSAlex Deucher #define ixD3F5_PCIE_LANE_12_EQUALIZATION_CNTL 0xb0000a5 26453e5343bdSAlex Deucher #define ixD3F5_PCIE_LANE_13_EQUALIZATION_CNTL 0xb0000a5 26463e5343bdSAlex Deucher #define ixD3F5_PCIE_LANE_14_EQUALIZATION_CNTL 0xb0000a6 26473e5343bdSAlex Deucher #define ixD3F5_PCIE_LANE_15_EQUALIZATION_CNTL 0xb0000a6 26483e5343bdSAlex Deucher #define ixD3F5_PCIE_ACS_ENH_CAP_LIST 0xb0000a8 26493e5343bdSAlex Deucher #define ixD3F5_PCIE_ACS_CAP 0xb0000a9 26503e5343bdSAlex Deucher #define ixD3F5_PCIE_ACS_CNTL 0xb0000a9 26513e5343bdSAlex Deucher #define ixD3F5_PCIE_MC_ENH_CAP_LIST 0xb0000bc 26523e5343bdSAlex Deucher #define ixD3F5_PCIE_MC_CAP 0xb0000bd 26533e5343bdSAlex Deucher #define ixD3F5_PCIE_MC_CNTL 0xb0000bd 26543e5343bdSAlex Deucher #define ixD3F5_PCIE_MC_ADDR0 0xb0000be 26553e5343bdSAlex Deucher #define ixD3F5_PCIE_MC_ADDR1 0xb0000bf 26563e5343bdSAlex Deucher #define ixD3F5_PCIE_MC_RCV0 0xb0000c0 26573e5343bdSAlex Deucher #define ixD3F5_PCIE_MC_RCV1 0xb0000c1 26583e5343bdSAlex Deucher #define ixD3F5_PCIE_MC_BLOCK_ALL0 0xb0000c2 26593e5343bdSAlex Deucher #define ixD3F5_PCIE_MC_BLOCK_ALL1 0xb0000c3 26603e5343bdSAlex Deucher #define ixD3F5_PCIE_MC_BLOCK_UNTRANSLATED_0 0xb0000c4 26613e5343bdSAlex Deucher #define ixD3F5_PCIE_MC_BLOCK_UNTRANSLATED_1 0xb0000c5 26623e5343bdSAlex Deucher #define ixD3F5_PCIE_MC_OVERLAY_BAR0 0xb0000c6 26633e5343bdSAlex Deucher #define ixD3F5_PCIE_MC_OVERLAY_BAR1 0xb0000c7 26643e5343bdSAlex Deucher #define mmC_PCIE_INDEX 0x28 26653e5343bdSAlex Deucher #define mmPCIE_WRAPPER0_C_PCIE_INDEX 0x28 26663e5343bdSAlex Deucher #define mmPCIE_WRAPPER1_C_PCIE_INDEX 0x38 26673e5343bdSAlex Deucher #define mmC_PCIE_DATA 0x29 26683e5343bdSAlex Deucher #define mmPCIE_WRAPPER0_C_PCIE_DATA 0x29 26693e5343bdSAlex Deucher #define mmPCIE_WRAPPER1_C_PCIE_DATA 0x39 26703e5343bdSAlex Deucher #define mmRFE_SNOOP_RST 0x3c 26713e5343bdSAlex Deucher #define ixPSX80_WRP_BIF_STRAP_FEATURE_EN_1 0x1500000 26723e5343bdSAlex Deucher #define ixPSX80_WRP_BIF_STRAP_PI_CNTL 0x1500001 26733e5343bdSAlex Deucher #define ixPSX80_WRP_BIF_STRAP_LINK_SPEED_CORE 0x1500002 26743e5343bdSAlex Deucher #define ixPSX80_WRP_BIF_STRAP_LC_MISC_CORE 0x1500003 26753e5343bdSAlex Deucher #define ixPSX80_WRP_BIF_STRAP_ERROR_IGNORE 0x1500004 26763e5343bdSAlex Deucher #define ixPSX80_WRP_BIF_STRAP_TEST_DFT 0x1500005 26773e5343bdSAlex Deucher #define ixPSX80_WRP_BIF_STRAP_ID 0x1500006 26783e5343bdSAlex Deucher #define ixPSX80_WRP_BIF_STRAP_REV_ID 0x1500007 26793e5343bdSAlex Deucher #define ixPSX80_WRP_BIF_STRAP_I2C_CNTL 0x1500008 26803e5343bdSAlex Deucher #define ixPSX80_WRP_BIF_INT_CNTL 0x1500009 26813e5343bdSAlex Deucher #define ixPSX80_WRP_BIF_STRAP_ACS 0x150000a 26823e5343bdSAlex Deucher #define ixPSX80_WRP_BIF_STRAP_PM 0x150000b 26833e5343bdSAlex Deucher #define ixPSX80_WRP_BIF_STRAP_FEATURE_EN_2 0x150000c 26843e5343bdSAlex Deucher #define ixPSX80_WRP_BIF_SERIAL_NUM 0x1500045 26853e5343bdSAlex Deucher #define ixPSX80_WRP_BIF_SSID 0x1500046 26863e5343bdSAlex Deucher #define ixPSX80_WRP_BIF_LANE_EQUALIZATION_CNTL 0x1500050 26873e5343bdSAlex Deucher #define ixPSX80_WRP_PCIE_LINK_CONFIG 0x1500080 26883e5343bdSAlex Deucher #define ixPSX80_WRP_PCIE_HOLD_TRAINING_A 0x1500800 26893e5343bdSAlex Deucher #define ixPSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_A 0x1500801 26903e5343bdSAlex Deucher #define ixPSX80_WRP_BIF_STRAP_ASPM_A 0x1500802 26913e5343bdSAlex Deucher #define ixPSX80_WRP_BIF_STRAP_LC_MISC_PORT_A 0x1500803 26923e5343bdSAlex Deucher #define ixPSX80_WRP_BIF_STRAP_MISC_PORT_A 0x1500804 26933e5343bdSAlex Deucher #define ixPSX80_WRP_BIF_STRAP_LINK_TRAINING_A 0x1500805 26943e5343bdSAlex Deucher #define ixPSX80_WRP_PCIE_PORT_IS_SB_A 0x1500813 26953e5343bdSAlex Deucher #define ixPSX80_WRP_PCIE_HOLD_TRAINING_B 0x1500900 26963e5343bdSAlex Deucher #define ixPSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_B 0x1500901 26973e5343bdSAlex Deucher #define ixPSX80_WRP_BIF_STRAP_ASPM_B 0x1500902 26983e5343bdSAlex Deucher #define ixPSX80_WRP_BIF_STRAP_LC_MISC_PORT_B 0x1500903 26993e5343bdSAlex Deucher #define ixPSX80_WRP_BIF_STRAP_MISC_PORT_B 0x1500904 27003e5343bdSAlex Deucher #define ixPSX80_WRP_BIF_STRAP_LINK_TRAINING_B 0x1500905 27013e5343bdSAlex Deucher #define ixPSX80_WRP_PCIE_PORT_IS_SB_B 0x1500913 27023e5343bdSAlex Deucher #define ixPSX80_WRP_PCIE_HOLD_TRAINING_C 0x1500a00 27033e5343bdSAlex Deucher #define ixPSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_C 0x1500a01 27043e5343bdSAlex Deucher #define ixPSX80_WRP_BIF_STRAP_ASPM_C 0x1500a02 27053e5343bdSAlex Deucher #define ixPSX80_WRP_BIF_STRAP_LC_MISC_PORT_C 0x1500a03 27063e5343bdSAlex Deucher #define ixPSX80_WRP_BIF_STRAP_MISC_PORT_C 0x1500a04 27073e5343bdSAlex Deucher #define ixPSX80_WRP_BIF_STRAP_LINK_TRAINING_C 0x1500a05 27083e5343bdSAlex Deucher #define ixPSX80_WRP_PCIE_PORT_IS_SB_C 0x1500a13 27093e5343bdSAlex Deucher #define ixPSX80_WRP_PCIE_HOLD_TRAINING_D 0x1500b00 27103e5343bdSAlex Deucher #define ixPSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_D 0x1500b01 27113e5343bdSAlex Deucher #define ixPSX80_WRP_BIF_STRAP_ASPM_D 0x1500b02 27123e5343bdSAlex Deucher #define ixPSX80_WRP_BIF_STRAP_LC_MISC_PORT_D 0x1500b03 27133e5343bdSAlex Deucher #define ixPSX80_WRP_BIF_STRAP_MISC_PORT_D 0x1500b04 27143e5343bdSAlex Deucher #define ixPSX80_WRP_BIF_STRAP_LINK_TRAINING_D 0x1500b05 27153e5343bdSAlex Deucher #define ixPSX80_WRP_PCIE_PORT_IS_SB_D 0x1500b13 27163e5343bdSAlex Deucher #define ixPSX80_WRP_PCIE_HOLD_TRAINING_E 0x1500c00 27173e5343bdSAlex Deucher #define ixPSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_E 0x1500c01 27183e5343bdSAlex Deucher #define ixPSX80_WRP_BIF_STRAP_ASPM_E 0x1500c02 27193e5343bdSAlex Deucher #define ixPSX80_WRP_BIF_STRAP_LC_MISC_PORT_E 0x1500c03 27203e5343bdSAlex Deucher #define ixPSX80_WRP_BIF_STRAP_MISC_PORT_E 0x1500c04 27213e5343bdSAlex Deucher #define ixPSX80_WRP_BIF_STRAP_LINK_TRAINING_E 0x1500c05 27223e5343bdSAlex Deucher #define ixPSX80_WRP_PCIE_PORT_IS_SB_E 0x1500c13 27233e5343bdSAlex Deucher #define ixPSX80_WRP_LNCNT_CONTROL 0x1508030 27243e5343bdSAlex Deucher #define ixPSX80_WRP_CFG_LNC_WINDOW 0x1508031 27253e5343bdSAlex Deucher #define ixPSX80_WRP_LNCNT_QUAN_THRD 0x1508032 27263e5343bdSAlex Deucher #define ixPSX80_WRP_LNCNT_WEIGHT 0x1508033 27273e5343bdSAlex Deucher #define ixPSX80_WRP_LNC_TOTAL_WACC 0x1508034 27283e5343bdSAlex Deucher #define ixPSX80_WRP_LNC_BW_WACC 0x1508035 27293e5343bdSAlex Deucher #define ixPSX80_WRP_LNC_CMN_WACC 0x1508036 27303e5343bdSAlex Deucher #define ixPSX80_WRP_PCIE_EFUSE 0x150fff0 27313e5343bdSAlex Deucher #define ixPSX80_WRP_PCIE_EFUSE2 0x150fff1 27323e5343bdSAlex Deucher #define ixPSX80_WRP_PCIE_EFUSE3 0x150fff2 27333e5343bdSAlex Deucher #define ixPSX80_WRP_PCIE_EFUSE4 0x150fff3 27343e5343bdSAlex Deucher #define ixPSX80_WRP_PCIE_EFUSE5 0x150fff4 27353e5343bdSAlex Deucher #define ixPSX80_WRP_PCIE_EFUSE6 0x150fff5 27363e5343bdSAlex Deucher #define ixPSX80_WRP_PCIE_EFUSE7 0x150fff6 27373e5343bdSAlex Deucher #define ixPSX80_WRP_PCIE_WRAP_SCRATCH1 0x1308001 27383e5343bdSAlex Deucher #define ixPSX80_WRP_PCIE_WRAP_SCRATCH2 0x1308002 27393e5343bdSAlex Deucher #define ixPSX80_WRP_PCIE_WRAP_REG_TARG_MISC 0x1308005 27403e5343bdSAlex Deucher #define ixPSX80_WRP_PCIE_WRAP_DTM_MISC 0x1308006 27413e5343bdSAlex Deucher #define ixPSX80_WRP_PCIE_WRAP_TURNAROUND_DAISYCHAIN 0x1308007 27423e5343bdSAlex Deucher #define ixPSX80_WRP_PCIE_WRAP_MISC 0x1308008 27433e5343bdSAlex Deucher #define ixPSX80_WRP_PCIE_WRAP_PIF_MISC 0x1308009 27443e5343bdSAlex Deucher #define ixPSX80_WRP_PCIE_RXDET_OVERRIDE 0x130800a 27453e5343bdSAlex Deucher #define ixPSX80_WRP_IMPCTL_CNTL_PIF0 0x1308070 27463e5343bdSAlex Deucher #define ixPSX80_WRP_REG_ADAPT_pciecore0_CONTROL 0x1308090 27473e5343bdSAlex Deucher #define ixPSX80_WRP_REG_ADAPT_pwregt_CONTROL 0x1308096 27483e5343bdSAlex Deucher #define ixPSX80_WRP_REG_ADAPT_pwregr_CONTROL 0x1308097 27493e5343bdSAlex Deucher #define ixPSX80_WRP_REG_ADAPT_pif0_CONTROL 0x1308098 27503e5343bdSAlex Deucher #define ixPSX80_WRP_BIOSTIMER_CMD 0x13080f0 27513e5343bdSAlex Deucher #define ixPSX80_WRP_BIOSTIMER_CNTL 0x13080f1 27523e5343bdSAlex Deucher #define ixPSX80_WRP_BIOSTIMER_DEBUG 0x13080f2 27533e5343bdSAlex Deucher #define ixPSX80_WRP_DTM_RX_BP_CNTL 0x130ffe0 27543e5343bdSAlex Deucher #define ixPSX80_WRP_DTM_CNTL 0x130ffe1 27553e5343bdSAlex Deucher #define ixPSX80_WRP_DTM_CNTL_LEGACY 0x130ffe2 27563e5343bdSAlex Deucher #define ixPSX80_WRP_DTM_STI_LCLK_CTRL 0x130ffe3 27573e5343bdSAlex Deucher #define ixPSX80_WRP_DTM_DENTIST_GATE_TIMING_DI_clk10x 0x130ffe4 27583e5343bdSAlex Deucher #define ixPSX80_WRP_DTM_DENTIST_GATE_TIMING_DI_clkGskt 0x130ffe5 27593e5343bdSAlex Deucher #define ixPSX80_WRP_DTM_DENTIST_GATE_TIMING_FI_clk10x 0x130ffe6 27603e5343bdSAlex Deucher #define ixPSX80_WRP_DTM_DENTIST_GATE_TIMING_FI_clkGskt 0x130ffe7 27613e5343bdSAlex Deucher #define ixPSX80_WRP_DELAYLINE_COMMAND 0x130ffd0 27623e5343bdSAlex Deucher #define ixPSX80_WRP_DELAYLINE_STATUS 0x130ffd1 27633e5343bdSAlex Deucher #define ixPSX81_WRP_BIF_STRAP_FEATURE_EN_1 0x1510000 27643e5343bdSAlex Deucher #define ixPSX81_WRP_BIF_STRAP_PI_CNTL 0x1510001 27653e5343bdSAlex Deucher #define ixPSX81_WRP_BIF_STRAP_LINK_SPEED_CORE 0x1510002 27663e5343bdSAlex Deucher #define ixPSX81_WRP_BIF_STRAP_LC_MISC_CORE 0x1510003 27673e5343bdSAlex Deucher #define ixPSX81_WRP_BIF_STRAP_ERROR_IGNORE 0x1510004 27683e5343bdSAlex Deucher #define ixPSX81_WRP_BIF_STRAP_TEST_DFT 0x1510005 27693e5343bdSAlex Deucher #define ixPSX81_WRP_BIF_STRAP_ID 0x1510006 27703e5343bdSAlex Deucher #define ixPSX81_WRP_BIF_STRAP_REV_ID 0x1510007 27713e5343bdSAlex Deucher #define ixPSX81_WRP_BIF_STRAP_I2C_CNTL 0x1510008 27723e5343bdSAlex Deucher #define ixPSX81_WRP_BIF_INT_CNTL 0x1510009 27733e5343bdSAlex Deucher #define ixPSX81_WRP_BIF_STRAP_ACS 0x151000a 27743e5343bdSAlex Deucher #define ixPSX81_WRP_BIF_STRAP_PM 0x151000b 27753e5343bdSAlex Deucher #define ixPSX81_WRP_BIF_STRAP_FEATURE_EN_2 0x151000c 27763e5343bdSAlex Deucher #define ixPSX81_WRP_BIF_SERIAL_NUM 0x1510045 27773e5343bdSAlex Deucher #define ixPSX81_WRP_BIF_SSID 0x1510046 27783e5343bdSAlex Deucher #define ixPSX81_WRP_BIF_LANE_EQUALIZATION_CNTL 0x1510050 27793e5343bdSAlex Deucher #define ixPSX81_WRP_PCIE_LINK_CONFIG 0x1510080 27803e5343bdSAlex Deucher #define ixPSX81_WRP_PCIE_HOLD_TRAINING_A 0x1510800 27813e5343bdSAlex Deucher #define ixPSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_A 0x1510801 27823e5343bdSAlex Deucher #define ixPSX81_WRP_BIF_STRAP_ASPM_A 0x1510802 27833e5343bdSAlex Deucher #define ixPSX81_WRP_BIF_STRAP_LC_MISC_PORT_A 0x1510803 27843e5343bdSAlex Deucher #define ixPSX81_WRP_BIF_STRAP_MISC_PORT_A 0x1510804 27853e5343bdSAlex Deucher #define ixPSX81_WRP_BIF_STRAP_LINK_TRAINING_A 0x1510805 27863e5343bdSAlex Deucher #define ixPSX81_WRP_PCIE_PORT_IS_SB_A 0x1510813 27873e5343bdSAlex Deucher #define ixPSX81_WRP_PCIE_HOLD_TRAINING_B 0x1510900 27883e5343bdSAlex Deucher #define ixPSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_B 0x1510901 27893e5343bdSAlex Deucher #define ixPSX81_WRP_BIF_STRAP_ASPM_B 0x1510902 27903e5343bdSAlex Deucher #define ixPSX81_WRP_BIF_STRAP_LC_MISC_PORT_B 0x1510903 27913e5343bdSAlex Deucher #define ixPSX81_WRP_BIF_STRAP_MISC_PORT_B 0x1510904 27923e5343bdSAlex Deucher #define ixPSX81_WRP_BIF_STRAP_LINK_TRAINING_B 0x1510905 27933e5343bdSAlex Deucher #define ixPSX81_WRP_PCIE_PORT_IS_SB_B 0x1510913 27943e5343bdSAlex Deucher #define ixPSX81_WRP_PCIE_HOLD_TRAINING_C 0x1510a00 27953e5343bdSAlex Deucher #define ixPSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_C 0x1510a01 27963e5343bdSAlex Deucher #define ixPSX81_WRP_BIF_STRAP_ASPM_C 0x1510a02 27973e5343bdSAlex Deucher #define ixPSX81_WRP_BIF_STRAP_LC_MISC_PORT_C 0x1510a03 27983e5343bdSAlex Deucher #define ixPSX81_WRP_BIF_STRAP_MISC_PORT_C 0x1510a04 27993e5343bdSAlex Deucher #define ixPSX81_WRP_BIF_STRAP_LINK_TRAINING_C 0x1510a05 28003e5343bdSAlex Deucher #define ixPSX81_WRP_PCIE_PORT_IS_SB_C 0x1510a13 28013e5343bdSAlex Deucher #define ixPSX81_WRP_PCIE_HOLD_TRAINING_D 0x1510b00 28023e5343bdSAlex Deucher #define ixPSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_D 0x1510b01 28033e5343bdSAlex Deucher #define ixPSX81_WRP_BIF_STRAP_ASPM_D 0x1510b02 28043e5343bdSAlex Deucher #define ixPSX81_WRP_BIF_STRAP_LC_MISC_PORT_D 0x1510b03 28053e5343bdSAlex Deucher #define ixPSX81_WRP_BIF_STRAP_MISC_PORT_D 0x1510b04 28063e5343bdSAlex Deucher #define ixPSX81_WRP_BIF_STRAP_LINK_TRAINING_D 0x1510b05 28073e5343bdSAlex Deucher #define ixPSX81_WRP_PCIE_PORT_IS_SB_D 0x1510b13 28083e5343bdSAlex Deucher #define ixPSX81_WRP_PCIE_HOLD_TRAINING_E 0x1510c00 28093e5343bdSAlex Deucher #define ixPSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_E 0x1510c01 28103e5343bdSAlex Deucher #define ixPSX81_WRP_BIF_STRAP_ASPM_E 0x1510c02 28113e5343bdSAlex Deucher #define ixPSX81_WRP_BIF_STRAP_LC_MISC_PORT_E 0x1510c03 28123e5343bdSAlex Deucher #define ixPSX81_WRP_BIF_STRAP_MISC_PORT_E 0x1510c04 28133e5343bdSAlex Deucher #define ixPSX81_WRP_BIF_STRAP_LINK_TRAINING_E 0x1510c05 28143e5343bdSAlex Deucher #define ixPSX81_WRP_PCIE_PORT_IS_SB_E 0x1510c13 28153e5343bdSAlex Deucher #define ixPSX81_WRP_LNCNT_CONTROL 0x1518030 28163e5343bdSAlex Deucher #define ixPSX81_WRP_CFG_LNC_WINDOW 0x1518031 28173e5343bdSAlex Deucher #define ixPSX81_WRP_LNCNT_QUAN_THRD 0x1518032 28183e5343bdSAlex Deucher #define ixPSX81_WRP_LNCNT_WEIGHT 0x1518033 28193e5343bdSAlex Deucher #define ixPSX81_WRP_LNC_TOTAL_WACC 0x1518034 28203e5343bdSAlex Deucher #define ixPSX81_WRP_LNC_BW_WACC 0x1518035 28213e5343bdSAlex Deucher #define ixPSX81_WRP_LNC_CMN_WACC 0x1518036 28223e5343bdSAlex Deucher #define ixPSX81_WRP_PCIE_EFUSE 0x151fff0 28233e5343bdSAlex Deucher #define ixPSX81_WRP_PCIE_EFUSE2 0x151fff1 28243e5343bdSAlex Deucher #define ixPSX81_WRP_PCIE_EFUSE3 0x151fff2 28253e5343bdSAlex Deucher #define ixPSX81_WRP_PCIE_EFUSE4 0x151fff3 28263e5343bdSAlex Deucher #define ixPSX81_WRP_PCIE_EFUSE5 0x151fff4 28273e5343bdSAlex Deucher #define ixPSX81_WRP_PCIE_EFUSE6 0x151fff5 28283e5343bdSAlex Deucher #define ixPSX81_WRP_PCIE_EFUSE7 0x151fff6 28293e5343bdSAlex Deucher #define ixPSX81_WRP_PCIE_WRAP_SCRATCH1 0x1318001 28303e5343bdSAlex Deucher #define ixPSX81_WRP_PCIE_WRAP_SCRATCH2 0x1318002 28313e5343bdSAlex Deucher #define ixPSX81_WRP_PCIE_WRAP_REG_TARG_MISC 0x1318005 28323e5343bdSAlex Deucher #define ixPSX81_WRP_PCIE_WRAP_DTM_MISC 0x1318006 28333e5343bdSAlex Deucher #define ixPSX81_WRP_PCIE_WRAP_TURNAROUND_DAISYCHAIN 0x1318007 28343e5343bdSAlex Deucher #define ixPSX81_WRP_PCIE_WRAP_MISC 0x1318008 28353e5343bdSAlex Deucher #define ixPSX81_WRP_PCIE_WRAP_PIF_MISC 0x1318009 28363e5343bdSAlex Deucher #define ixPSX81_WRP_PCIE_RXDET_OVERRIDE 0x131800a 28373e5343bdSAlex Deucher #define ixPSX81_WRP_IMPCTL_CNTL_PIF0 0x1318070 28383e5343bdSAlex Deucher #define ixPSX81_WRP_REG_ADAPT_pciecore0_CONTROL 0x1318090 28393e5343bdSAlex Deucher #define ixPSX81_WRP_REG_ADAPT_pwregt_CONTROL 0x1318096 28403e5343bdSAlex Deucher #define ixPSX81_WRP_REG_ADAPT_pwregr_CONTROL 0x1318097 28413e5343bdSAlex Deucher #define ixPSX81_WRP_REG_ADAPT_pif0_CONTROL 0x1318098 28423e5343bdSAlex Deucher #define ixPSX81_WRP_BIOSTIMER_CMD 0x13180f0 28433e5343bdSAlex Deucher #define ixPSX81_WRP_BIOSTIMER_CNTL 0x13180f1 28443e5343bdSAlex Deucher #define ixPSX81_WRP_BIOSTIMER_DEBUG 0x13180f2 28453e5343bdSAlex Deucher #define ixPSX81_WRP_DTM_RX_BP_CNTL 0x131ffe0 28463e5343bdSAlex Deucher #define ixPSX81_WRP_DTM_CNTL 0x131ffe1 28473e5343bdSAlex Deucher #define ixPSX81_WRP_DTM_CNTL_LEGACY 0x131ffe2 28483e5343bdSAlex Deucher #define ixPSX81_WRP_DTM_STI_LCLK_CTRL 0x131ffe3 28493e5343bdSAlex Deucher #define ixPSX81_WRP_DTM_DENTIST_GATE_TIMING_DI_clk10x 0x131ffe4 28503e5343bdSAlex Deucher #define ixPSX81_WRP_DTM_DENTIST_GATE_TIMING_DI_clkGskt 0x131ffe5 28513e5343bdSAlex Deucher #define ixPSX81_WRP_DTM_DENTIST_GATE_TIMING_FI_clk10x 0x131ffe6 28523e5343bdSAlex Deucher #define ixPSX81_WRP_DTM_DENTIST_GATE_TIMING_FI_clkGskt 0x131ffe7 28533e5343bdSAlex Deucher #define ixPSX81_WRP_DELAYLINE_COMMAND 0x131ffd0 28543e5343bdSAlex Deucher #define ixPSX81_WRP_DELAYLINE_STATUS 0x131ffd1 28553e5343bdSAlex Deucher #define ixRFE_WARMRST_CNTL 0x1085164 28563e5343bdSAlex Deucher #define ixRFE_SOFTRST_CNTL 0x1080001 28573e5343bdSAlex Deucher #define ixRFE_IMPRST_CNTL 0x1085160 28583e5343bdSAlex Deucher #define ixRFE_CLIENT_SOFTRST_TRIGGER 0x1080004 28593e5343bdSAlex Deucher #define ixRFE_MASTER_SOFTRST_TRIGGER 0x1080005 28603e5343bdSAlex Deucher #define ixRFE_PWDN_COMMAND 0x1080010 28613e5343bdSAlex Deucher #define ixRFE_PWDN_STATUS 0x1080011 28623e5343bdSAlex Deucher #define ixRFE_MST_PCIEW0_CMDSTATUS 0x1080020 28633e5343bdSAlex Deucher #define ixRFE_MST_PCIEW1_CMDSTATUS 0x1080021 28643e5343bdSAlex Deucher #define ixRFE_MST_RWREG_RFEWRC_CMDSTATUS 0x1080022 28653e5343bdSAlex Deucher #define ixRFE_MST_TMOUT_STATUS 0x108003f 28663e5343bdSAlex Deucher #define ixRFE_IMPARBH_STATUS 0x1085140 28673e5343bdSAlex Deucher #define ixRFE_IMPARBH_CONTROL 0x1080083 28683e5343bdSAlex Deucher #define ixPSX80_BIF_PCIE_RESERVED 0x1400000 28693e5343bdSAlex Deucher #define ixPSX80_BIF_PCIE_SCRATCH 0x1400001 28703e5343bdSAlex Deucher #define ixPSX80_BIF_PCIE_HW_DEBUG 0x1400002 28713e5343bdSAlex Deucher #define ixPSX80_BIF_PCIE_RX_NUM_NAK 0x140000e 28723e5343bdSAlex Deucher #define ixPSX80_BIF_PCIE_RX_NUM_NAK_GENERATED 0x140000f 28733e5343bdSAlex Deucher #define ixPSX80_BIF_PCIE_CNTL 0x1400010 28743e5343bdSAlex Deucher #define ixPSX80_BIF_PCIE_CONFIG_CNTL 0x1400011 28753e5343bdSAlex Deucher #define ixPSX80_BIF_PCIE_DEBUG_CNTL 0x1400012 28763e5343bdSAlex Deucher #define ixPSX80_BIF_PCIE_CNTL2 0x140001c 28773e5343bdSAlex Deucher #define ixPSX80_BIF_PCIE_RX_CNTL2 0x140001d 28783e5343bdSAlex Deucher #define ixPSX80_BIF_PCIE_TX_F0_ATTR_CNTL 0x140001e 28793e5343bdSAlex Deucher #define ixPSX80_BIF_PCIE_CI_CNTL 0x1400020 28803e5343bdSAlex Deucher #define ixPSX80_BIF_PCIE_BUS_CNTL 0x1400021 28813e5343bdSAlex Deucher #define ixPSX80_BIF_PCIE_LC_STATE6 0x1400022 28823e5343bdSAlex Deucher #define ixPSX80_BIF_PCIE_LC_STATE7 0x1400023 28833e5343bdSAlex Deucher #define ixPSX80_BIF_PCIE_LC_STATE8 0x1400024 28843e5343bdSAlex Deucher #define ixPSX80_BIF_PCIE_LC_STATE9 0x1400025 28853e5343bdSAlex Deucher #define ixPSX80_BIF_PCIE_LC_STATE10 0x1400026 28863e5343bdSAlex Deucher #define ixPSX80_BIF_PCIE_LC_STATE11 0x1400027 28873e5343bdSAlex Deucher #define ixPSX80_BIF_PCIE_LC_STATUS1 0x1400028 28883e5343bdSAlex Deucher #define ixPSX80_BIF_PCIE_LC_STATUS2 0x1400029 28893e5343bdSAlex Deucher #define ixPSX80_BIF_PCIE_WPR_CNTL 0x1400030 28903e5343bdSAlex Deucher #define ixPSX80_BIF_PCIE_RX_LAST_TLP0 0x1400031 28913e5343bdSAlex Deucher #define ixPSX80_BIF_PCIE_RX_LAST_TLP1 0x1400032 28923e5343bdSAlex Deucher #define ixPSX80_BIF_PCIE_RX_LAST_TLP2 0x1400033 28933e5343bdSAlex Deucher #define ixPSX80_BIF_PCIE_RX_LAST_TLP3 0x1400034 28943e5343bdSAlex Deucher #define ixPSX80_BIF_PCIE_TX_LAST_TLP0 0x1400035 28953e5343bdSAlex Deucher #define ixPSX80_BIF_PCIE_TX_LAST_TLP1 0x1400036 28963e5343bdSAlex Deucher #define ixPSX80_BIF_PCIE_TX_LAST_TLP2 0x1400037 28973e5343bdSAlex Deucher #define ixPSX80_BIF_PCIE_TX_LAST_TLP3 0x1400038 28983e5343bdSAlex Deucher #define ixPSX80_BIF_PCIE_I2C_REG_ADDR_EXPAND 0x140003a 28993e5343bdSAlex Deucher #define ixPSX80_BIF_PCIE_I2C_REG_DATA 0x140003b 29003e5343bdSAlex Deucher #define ixPSX80_BIF_PCIE_CFG_CNTL 0x140003c 29013e5343bdSAlex Deucher #define ixPSX80_BIF_PCIE_LC_PM_CNTL 0x140003d 29023e5343bdSAlex Deucher #define ixPSX80_BIF_PCIE_P_CNTL 0x1400040 29033e5343bdSAlex Deucher #define ixPSX80_BIF_PCIE_P_BUF_STATUS 0x1400041 29043e5343bdSAlex Deucher #define ixPSX80_BIF_PCIE_P_DECODER_STATUS 0x1400042 29053e5343bdSAlex Deucher #define ixPSX80_BIF_PCIE_P_MISC_STATUS 0x1400043 29063e5343bdSAlex Deucher #define ixPSX80_BIF_PCIE_P_RCV_L0S_FTS_DET 0x1400050 29073e5343bdSAlex Deucher #define ixPSX80_BIF_PCIE_PERF_COUNT_CNTL 0x1400080 29083e5343bdSAlex Deucher #define ixPSX80_BIF_PCIE_PERF_CNTL_TXCLK 0x1400081 29093e5343bdSAlex Deucher #define ixPSX80_BIF_PCIE_PERF_COUNT0_TXCLK 0x1400082 29103e5343bdSAlex Deucher #define ixPSX80_BIF_PCIE_PERF_COUNT1_TXCLK 0x1400083 29113e5343bdSAlex Deucher #define ixPSX80_BIF_PCIE_PERF_CNTL_MST_R_CLK 0x1400084 29123e5343bdSAlex Deucher #define ixPSX80_BIF_PCIE_PERF_COUNT0_MST_R_CLK 0x1400085 29133e5343bdSAlex Deucher #define ixPSX80_BIF_PCIE_PERF_COUNT1_MST_R_CLK 0x1400086 29143e5343bdSAlex Deucher #define ixPSX80_BIF_PCIE_PERF_CNTL_MST_C_CLK 0x1400087 29153e5343bdSAlex Deucher #define ixPSX80_BIF_PCIE_PERF_COUNT0_MST_C_CLK 0x1400088 29163e5343bdSAlex Deucher #define ixPSX80_BIF_PCIE_PERF_COUNT1_MST_C_CLK 0x1400089 29173e5343bdSAlex Deucher #define ixPSX80_BIF_PCIE_PERF_CNTL_SLV_R_CLK 0x140008a 29183e5343bdSAlex Deucher #define ixPSX80_BIF_PCIE_PERF_COUNT0_SLV_R_CLK 0x140008b 29193e5343bdSAlex Deucher #define ixPSX80_BIF_PCIE_PERF_COUNT1_SLV_R_CLK 0x140008c 29203e5343bdSAlex Deucher #define ixPSX80_BIF_PCIE_PERF_CNTL_SLV_S_C_CLK 0x140008d 29213e5343bdSAlex Deucher #define ixPSX80_BIF_PCIE_PERF_COUNT0_SLV_S_C_CLK 0x140008e 29223e5343bdSAlex Deucher #define ixPSX80_BIF_PCIE_PERF_COUNT1_SLV_S_C_CLK 0x140008f 29233e5343bdSAlex Deucher #define ixPSX80_BIF_PCIE_PERF_CNTL_SLV_NS_C_CLK 0x1400090 29243e5343bdSAlex Deucher #define ixPSX80_BIF_PCIE_PERF_COUNT0_SLV_NS_C_CLK 0x1400091 29253e5343bdSAlex Deucher #define ixPSX80_BIF_PCIE_PERF_COUNT1_SLV_NS_C_CLK 0x1400092 29263e5343bdSAlex Deucher #define ixPSX80_BIF_PCIE_PERF_CNTL_EVENT0_PORT_SEL 0x1400093 29273e5343bdSAlex Deucher #define ixPSX80_BIF_PCIE_PERF_CNTL_EVENT1_PORT_SEL 0x1400094 29283e5343bdSAlex Deucher #define ixPSX80_BIF_PCIE_PERF_CNTL_TXCLK2 0x1400095 29293e5343bdSAlex Deucher #define ixPSX80_BIF_PCIE_PERF_COUNT0_TXCLK2 0x1400096 29303e5343bdSAlex Deucher #define ixPSX80_BIF_PCIE_PERF_COUNT1_TXCLK2 0x1400097 29313e5343bdSAlex Deucher #define ixPSX80_BIF_PCIE_STRAP_F0 0x14000b0 29323e5343bdSAlex Deucher #define ixPSX80_BIF_PCIE_STRAP_MISC 0x14000c0 29333e5343bdSAlex Deucher #define ixPSX80_BIF_PCIE_STRAP_MISC2 0x14000c1 29343e5343bdSAlex Deucher #define ixPSX80_BIF_PCIE_STRAP_PI 0x14000c2 29353e5343bdSAlex Deucher #define ixPSX80_BIF_PCIE_STRAP_I2C_BD 0x14000c4 29363e5343bdSAlex Deucher #define ixPSX80_BIF_PCIE_PRBS_CLR 0x14000c8 29373e5343bdSAlex Deucher #define ixPSX80_BIF_PCIE_PRBS_STATUS1 0x14000c9 29383e5343bdSAlex Deucher #define ixPSX80_BIF_PCIE_PRBS_STATUS2 0x14000ca 29393e5343bdSAlex Deucher #define ixPSX80_BIF_PCIE_PRBS_FREERUN 0x14000cb 29403e5343bdSAlex Deucher #define ixPSX80_BIF_PCIE_PRBS_MISC 0x14000cc 29413e5343bdSAlex Deucher #define ixPSX80_BIF_PCIE_PRBS_USER_PATTERN 0x14000cd 29423e5343bdSAlex Deucher #define ixPSX80_BIF_PCIE_PRBS_LO_BITCNT 0x14000ce 29433e5343bdSAlex Deucher #define ixPSX80_BIF_PCIE_PRBS_HI_BITCNT 0x14000cf 29443e5343bdSAlex Deucher #define ixPSX80_BIF_PCIE_PRBS_ERRCNT_0 0x14000d0 29453e5343bdSAlex Deucher #define ixPSX80_BIF_PCIE_PRBS_ERRCNT_1 0x14000d1 29463e5343bdSAlex Deucher #define ixPSX80_BIF_PCIE_PRBS_ERRCNT_2 0x14000d2 29473e5343bdSAlex Deucher #define ixPSX80_BIF_PCIE_PRBS_ERRCNT_3 0x14000d3 29483e5343bdSAlex Deucher #define ixPSX80_BIF_PCIE_PRBS_ERRCNT_4 0x14000d4 29493e5343bdSAlex Deucher #define ixPSX80_BIF_PCIE_PRBS_ERRCNT_5 0x14000d5 29503e5343bdSAlex Deucher #define ixPSX80_BIF_PCIE_PRBS_ERRCNT_6 0x14000d6 29513e5343bdSAlex Deucher #define ixPSX80_BIF_PCIE_PRBS_ERRCNT_7 0x14000d7 29523e5343bdSAlex Deucher #define ixPSX80_BIF_PCIE_PRBS_ERRCNT_8 0x14000d8 29533e5343bdSAlex Deucher #define ixPSX80_BIF_PCIE_PRBS_ERRCNT_9 0x14000d9 29543e5343bdSAlex Deucher #define ixPSX80_BIF_PCIE_PRBS_ERRCNT_10 0x14000da 29553e5343bdSAlex Deucher #define ixPSX80_BIF_PCIE_PRBS_ERRCNT_11 0x14000db 29563e5343bdSAlex Deucher #define ixPSX80_BIF_PCIE_PRBS_ERRCNT_12 0x14000dc 29573e5343bdSAlex Deucher #define ixPSX80_BIF_PCIE_PRBS_ERRCNT_13 0x14000dd 29583e5343bdSAlex Deucher #define ixPSX80_BIF_PCIE_PRBS_ERRCNT_14 0x14000de 29593e5343bdSAlex Deucher #define ixPSX80_BIF_PCIE_PRBS_ERRCNT_15 0x14000df 29603e5343bdSAlex Deucher #define ixPSX80_BIF_SWRST_COMMAND_STATUS 0x1400100 29613e5343bdSAlex Deucher #define ixPSX80_BIF_SWRST_GENERAL_CONTROL 0x1400101 29623e5343bdSAlex Deucher #define ixPSX80_BIF_SWRST_COMMAND_0 0x1400102 29633e5343bdSAlex Deucher #define ixPSX80_BIF_SWRST_COMMAND_1 0x1400103 29643e5343bdSAlex Deucher #define ixPSX80_BIF_SWRST_CONTROL_0 0x1400104 29653e5343bdSAlex Deucher #define ixPSX80_BIF_SWRST_CONTROL_1 0x1400105 29663e5343bdSAlex Deucher #define ixPSX80_BIF_SWRST_CONTROL_2 0x1400106 29673e5343bdSAlex Deucher #define ixPSX80_BIF_SWRST_CONTROL_3 0x1400107 29683e5343bdSAlex Deucher #define ixPSX80_BIF_SWRST_CONTROL_4 0x1400108 29693e5343bdSAlex Deucher #define ixPSX80_BIF_SWRST_CONTROL_5 0x1400109 29703e5343bdSAlex Deucher #define ixPSX80_BIF_SWRST_CONTROL_6 0x140010a 29713e5343bdSAlex Deucher #define ixPSX80_BIF_CPM_CONTROL 0x1400118 29723e5343bdSAlex Deucher #define ixPSX80_BIF_LM_CONTROL 0x1400120 29733e5343bdSAlex Deucher #define ixPSX80_BIF_LM_PCIETXMUX0 0x1400121 29743e5343bdSAlex Deucher #define ixPSX80_BIF_LM_PCIETXMUX1 0x1400122 29753e5343bdSAlex Deucher #define ixPSX80_BIF_LM_PCIETXMUX2 0x1400123 29763e5343bdSAlex Deucher #define ixPSX80_BIF_LM_PCIETXMUX3 0x1400124 29773e5343bdSAlex Deucher #define ixPSX80_BIF_LM_PCIERXMUX0 0x1400125 29783e5343bdSAlex Deucher #define ixPSX80_BIF_LM_PCIERXMUX1 0x1400126 29793e5343bdSAlex Deucher #define ixPSX80_BIF_LM_PCIERXMUX2 0x1400127 29803e5343bdSAlex Deucher #define ixPSX80_BIF_LM_PCIERXMUX3 0x1400128 29813e5343bdSAlex Deucher #define ixPSX80_BIF_LM_LANEENABLE 0x1400129 29823e5343bdSAlex Deucher #define ixPSX80_BIF_LM_PRBSCONTROL 0x140012a 29833e5343bdSAlex Deucher #define ixPSX80_BIF_LM_POWERCONTROL 0x140012b 29843e5343bdSAlex Deucher #define ixPSX80_BIF_LM_POWERCONTROL1 0x140012c 29853e5343bdSAlex Deucher #define ixPSX80_BIF_LM_POWERCONTROL2 0x140012d 29863e5343bdSAlex Deucher #define ixPSX80_BIF_LM_POWERCONTROL3 0x140012e 29873e5343bdSAlex Deucher #define ixPSX80_BIF_LM_POWERCONTROL4 0x140012f 29883e5343bdSAlex Deucher #define ixPSX81_BIF_PCIE_RESERVED 0x1410000 29893e5343bdSAlex Deucher #define ixPSX81_BIF_PCIE_SCRATCH 0x1410001 29903e5343bdSAlex Deucher #define ixPSX81_BIF_PCIE_HW_DEBUG 0x1410002 29913e5343bdSAlex Deucher #define ixPSX81_BIF_PCIE_RX_NUM_NAK 0x141000e 29923e5343bdSAlex Deucher #define ixPSX81_BIF_PCIE_RX_NUM_NAK_GENERATED 0x141000f 29933e5343bdSAlex Deucher #define ixPSX81_BIF_PCIE_CNTL 0x1410010 29943e5343bdSAlex Deucher #define ixPSX81_BIF_PCIE_CONFIG_CNTL 0x1410011 29953e5343bdSAlex Deucher #define ixPSX81_BIF_PCIE_DEBUG_CNTL 0x1410012 29963e5343bdSAlex Deucher #define ixPSX81_BIF_PCIE_CNTL2 0x141001c 29973e5343bdSAlex Deucher #define ixPSX81_BIF_PCIE_RX_CNTL2 0x141001d 29983e5343bdSAlex Deucher #define ixPSX81_BIF_PCIE_TX_F0_ATTR_CNTL 0x141001e 29993e5343bdSAlex Deucher #define ixPSX81_BIF_PCIE_CI_CNTL 0x1410020 30003e5343bdSAlex Deucher #define ixPSX81_BIF_PCIE_BUS_CNTL 0x1410021 30013e5343bdSAlex Deucher #define ixPSX81_BIF_PCIE_LC_STATE6 0x1410022 30023e5343bdSAlex Deucher #define ixPSX81_BIF_PCIE_LC_STATE7 0x1410023 30033e5343bdSAlex Deucher #define ixPSX81_BIF_PCIE_LC_STATE8 0x1410024 30043e5343bdSAlex Deucher #define ixPSX81_BIF_PCIE_LC_STATE9 0x1410025 30053e5343bdSAlex Deucher #define ixPSX81_BIF_PCIE_LC_STATE10 0x1410026 30063e5343bdSAlex Deucher #define ixPSX81_BIF_PCIE_LC_STATE11 0x1410027 30073e5343bdSAlex Deucher #define ixPSX81_BIF_PCIE_LC_STATUS1 0x1410028 30083e5343bdSAlex Deucher #define ixPSX81_BIF_PCIE_LC_STATUS2 0x1410029 30093e5343bdSAlex Deucher #define ixPSX81_BIF_PCIE_WPR_CNTL 0x1410030 30103e5343bdSAlex Deucher #define ixPSX81_BIF_PCIE_RX_LAST_TLP0 0x1410031 30113e5343bdSAlex Deucher #define ixPSX81_BIF_PCIE_RX_LAST_TLP1 0x1410032 30123e5343bdSAlex Deucher #define ixPSX81_BIF_PCIE_RX_LAST_TLP2 0x1410033 30133e5343bdSAlex Deucher #define ixPSX81_BIF_PCIE_RX_LAST_TLP3 0x1410034 30143e5343bdSAlex Deucher #define ixPSX81_BIF_PCIE_TX_LAST_TLP0 0x1410035 30153e5343bdSAlex Deucher #define ixPSX81_BIF_PCIE_TX_LAST_TLP1 0x1410036 30163e5343bdSAlex Deucher #define ixPSX81_BIF_PCIE_TX_LAST_TLP2 0x1410037 30173e5343bdSAlex Deucher #define ixPSX81_BIF_PCIE_TX_LAST_TLP3 0x1410038 30183e5343bdSAlex Deucher #define ixPSX81_BIF_PCIE_I2C_REG_ADDR_EXPAND 0x141003a 30193e5343bdSAlex Deucher #define ixPSX81_BIF_PCIE_I2C_REG_DATA 0x141003b 30203e5343bdSAlex Deucher #define ixPSX81_BIF_PCIE_CFG_CNTL 0x141003c 30213e5343bdSAlex Deucher #define ixPSX81_BIF_PCIE_LC_PM_CNTL 0x141003d 30223e5343bdSAlex Deucher #define ixPSX81_BIF_PCIE_P_CNTL 0x1410040 30233e5343bdSAlex Deucher #define ixPSX81_BIF_PCIE_P_BUF_STATUS 0x1410041 30243e5343bdSAlex Deucher #define ixPSX81_BIF_PCIE_P_DECODER_STATUS 0x1410042 30253e5343bdSAlex Deucher #define ixPSX81_BIF_PCIE_P_MISC_STATUS 0x1410043 30263e5343bdSAlex Deucher #define ixPSX81_BIF_PCIE_P_RCV_L0S_FTS_DET 0x1410050 30273e5343bdSAlex Deucher #define ixPSX81_BIF_PCIE_PERF_COUNT_CNTL 0x1410080 30283e5343bdSAlex Deucher #define ixPSX81_BIF_PCIE_PERF_CNTL_TXCLK 0x1410081 30293e5343bdSAlex Deucher #define ixPSX81_BIF_PCIE_PERF_COUNT0_TXCLK 0x1410082 30303e5343bdSAlex Deucher #define ixPSX81_BIF_PCIE_PERF_COUNT1_TXCLK 0x1410083 30313e5343bdSAlex Deucher #define ixPSX81_BIF_PCIE_PERF_CNTL_MST_R_CLK 0x1410084 30323e5343bdSAlex Deucher #define ixPSX81_BIF_PCIE_PERF_COUNT0_MST_R_CLK 0x1410085 30333e5343bdSAlex Deucher #define ixPSX81_BIF_PCIE_PERF_COUNT1_MST_R_CLK 0x1410086 30343e5343bdSAlex Deucher #define ixPSX81_BIF_PCIE_PERF_CNTL_MST_C_CLK 0x1410087 30353e5343bdSAlex Deucher #define ixPSX81_BIF_PCIE_PERF_COUNT0_MST_C_CLK 0x1410088 30363e5343bdSAlex Deucher #define ixPSX81_BIF_PCIE_PERF_COUNT1_MST_C_CLK 0x1410089 30373e5343bdSAlex Deucher #define ixPSX81_BIF_PCIE_PERF_CNTL_SLV_R_CLK 0x141008a 30383e5343bdSAlex Deucher #define ixPSX81_BIF_PCIE_PERF_COUNT0_SLV_R_CLK 0x141008b 30393e5343bdSAlex Deucher #define ixPSX81_BIF_PCIE_PERF_COUNT1_SLV_R_CLK 0x141008c 30403e5343bdSAlex Deucher #define ixPSX81_BIF_PCIE_PERF_CNTL_SLV_S_C_CLK 0x141008d 30413e5343bdSAlex Deucher #define ixPSX81_BIF_PCIE_PERF_COUNT0_SLV_S_C_CLK 0x141008e 30423e5343bdSAlex Deucher #define ixPSX81_BIF_PCIE_PERF_COUNT1_SLV_S_C_CLK 0x141008f 30433e5343bdSAlex Deucher #define ixPSX81_BIF_PCIE_PERF_CNTL_SLV_NS_C_CLK 0x1410090 30443e5343bdSAlex Deucher #define ixPSX81_BIF_PCIE_PERF_COUNT0_SLV_NS_C_CLK 0x1410091 30453e5343bdSAlex Deucher #define ixPSX81_BIF_PCIE_PERF_COUNT1_SLV_NS_C_CLK 0x1410092 30463e5343bdSAlex Deucher #define ixPSX81_BIF_PCIE_PERF_CNTL_EVENT0_PORT_SEL 0x1410093 30473e5343bdSAlex Deucher #define ixPSX81_BIF_PCIE_PERF_CNTL_EVENT1_PORT_SEL 0x1410094 30483e5343bdSAlex Deucher #define ixPSX81_BIF_PCIE_PERF_CNTL_TXCLK2 0x1410095 30493e5343bdSAlex Deucher #define ixPSX81_BIF_PCIE_PERF_COUNT0_TXCLK2 0x1410096 30503e5343bdSAlex Deucher #define ixPSX81_BIF_PCIE_PERF_COUNT1_TXCLK2 0x1410097 30513e5343bdSAlex Deucher #define ixPSX81_BIF_PCIE_STRAP_F0 0x14100b0 30523e5343bdSAlex Deucher #define ixPSX81_BIF_PCIE_STRAP_MISC 0x14100c0 30533e5343bdSAlex Deucher #define ixPSX81_BIF_PCIE_STRAP_MISC2 0x14100c1 30543e5343bdSAlex Deucher #define ixPSX81_BIF_PCIE_STRAP_PI 0x14100c2 30553e5343bdSAlex Deucher #define ixPSX81_BIF_PCIE_STRAP_I2C_BD 0x14100c4 30563e5343bdSAlex Deucher #define ixPSX81_BIF_PCIE_PRBS_CLR 0x14100c8 30573e5343bdSAlex Deucher #define ixPSX81_BIF_PCIE_PRBS_STATUS1 0x14100c9 30583e5343bdSAlex Deucher #define ixPSX81_BIF_PCIE_PRBS_STATUS2 0x14100ca 30593e5343bdSAlex Deucher #define ixPSX81_BIF_PCIE_PRBS_FREERUN 0x14100cb 30603e5343bdSAlex Deucher #define ixPSX81_BIF_PCIE_PRBS_MISC 0x14100cc 30613e5343bdSAlex Deucher #define ixPSX81_BIF_PCIE_PRBS_USER_PATTERN 0x14100cd 30623e5343bdSAlex Deucher #define ixPSX81_BIF_PCIE_PRBS_LO_BITCNT 0x14100ce 30633e5343bdSAlex Deucher #define ixPSX81_BIF_PCIE_PRBS_HI_BITCNT 0x14100cf 30643e5343bdSAlex Deucher #define ixPSX81_BIF_PCIE_PRBS_ERRCNT_0 0x14100d0 30653e5343bdSAlex Deucher #define ixPSX81_BIF_PCIE_PRBS_ERRCNT_1 0x14100d1 30663e5343bdSAlex Deucher #define ixPSX81_BIF_PCIE_PRBS_ERRCNT_2 0x14100d2 30673e5343bdSAlex Deucher #define ixPSX81_BIF_PCIE_PRBS_ERRCNT_3 0x14100d3 30683e5343bdSAlex Deucher #define ixPSX81_BIF_PCIE_PRBS_ERRCNT_4 0x14100d4 30693e5343bdSAlex Deucher #define ixPSX81_BIF_PCIE_PRBS_ERRCNT_5 0x14100d5 30703e5343bdSAlex Deucher #define ixPSX81_BIF_PCIE_PRBS_ERRCNT_6 0x14100d6 30713e5343bdSAlex Deucher #define ixPSX81_BIF_PCIE_PRBS_ERRCNT_7 0x14100d7 30723e5343bdSAlex Deucher #define ixPSX81_BIF_PCIE_PRBS_ERRCNT_8 0x14100d8 30733e5343bdSAlex Deucher #define ixPSX81_BIF_PCIE_PRBS_ERRCNT_9 0x14100d9 30743e5343bdSAlex Deucher #define ixPSX81_BIF_PCIE_PRBS_ERRCNT_10 0x14100da 30753e5343bdSAlex Deucher #define ixPSX81_BIF_PCIE_PRBS_ERRCNT_11 0x14100db 30763e5343bdSAlex Deucher #define ixPSX81_BIF_PCIE_PRBS_ERRCNT_12 0x14100dc 30773e5343bdSAlex Deucher #define ixPSX81_BIF_PCIE_PRBS_ERRCNT_13 0x14100dd 30783e5343bdSAlex Deucher #define ixPSX81_BIF_PCIE_PRBS_ERRCNT_14 0x14100de 30793e5343bdSAlex Deucher #define ixPSX81_BIF_PCIE_PRBS_ERRCNT_15 0x14100df 30803e5343bdSAlex Deucher #define ixPSX81_BIF_SWRST_COMMAND_STATUS 0x1410100 30813e5343bdSAlex Deucher #define ixPSX81_BIF_SWRST_GENERAL_CONTROL 0x1410101 30823e5343bdSAlex Deucher #define ixPSX81_BIF_SWRST_COMMAND_0 0x1410102 30833e5343bdSAlex Deucher #define ixPSX81_BIF_SWRST_COMMAND_1 0x1410103 30843e5343bdSAlex Deucher #define ixPSX81_BIF_SWRST_CONTROL_0 0x1410104 30853e5343bdSAlex Deucher #define ixPSX81_BIF_SWRST_CONTROL_1 0x1410105 30863e5343bdSAlex Deucher #define ixPSX81_BIF_SWRST_CONTROL_2 0x1410106 30873e5343bdSAlex Deucher #define ixPSX81_BIF_SWRST_CONTROL_3 0x1410107 30883e5343bdSAlex Deucher #define ixPSX81_BIF_SWRST_CONTROL_4 0x1410108 30893e5343bdSAlex Deucher #define ixPSX81_BIF_SWRST_CONTROL_5 0x1410109 30903e5343bdSAlex Deucher #define ixPSX81_BIF_SWRST_CONTROL_6 0x141010a 30913e5343bdSAlex Deucher #define ixPSX81_BIF_CPM_CONTROL 0x1410118 30923e5343bdSAlex Deucher #define ixPSX81_BIF_LM_CONTROL 0x1410120 30933e5343bdSAlex Deucher #define ixPSX81_BIF_LM_PCIETXMUX0 0x1410121 30943e5343bdSAlex Deucher #define ixPSX81_BIF_LM_PCIETXMUX1 0x1410122 30953e5343bdSAlex Deucher #define ixPSX81_BIF_LM_PCIETXMUX2 0x1410123 30963e5343bdSAlex Deucher #define ixPSX81_BIF_LM_PCIETXMUX3 0x1410124 30973e5343bdSAlex Deucher #define ixPSX81_BIF_LM_PCIERXMUX0 0x1410125 30983e5343bdSAlex Deucher #define ixPSX81_BIF_LM_PCIERXMUX1 0x1410126 30993e5343bdSAlex Deucher #define ixPSX81_BIF_LM_PCIERXMUX2 0x1410127 31003e5343bdSAlex Deucher #define ixPSX81_BIF_LM_PCIERXMUX3 0x1410128 31013e5343bdSAlex Deucher #define ixPSX81_BIF_LM_LANEENABLE 0x1410129 31023e5343bdSAlex Deucher #define ixPSX81_BIF_LM_PRBSCONTROL 0x141012a 31033e5343bdSAlex Deucher #define ixPSX81_BIF_LM_POWERCONTROL 0x141012b 31043e5343bdSAlex Deucher #define ixPSX81_BIF_LM_POWERCONTROL1 0x141012c 31053e5343bdSAlex Deucher #define ixPSX81_BIF_LM_POWERCONTROL2 0x141012d 31063e5343bdSAlex Deucher #define ixPSX81_BIF_LM_POWERCONTROL3 0x141012e 31073e5343bdSAlex Deucher #define ixPSX81_BIF_LM_POWERCONTROL4 0x141012f 31083e5343bdSAlex Deucher #define ixPSX80_PHY0_COM_COMMON_FUSE1 0x1206200 31093e5343bdSAlex Deucher #define ixPSX80_PHY0_COM_COMMON_FUSE2 0x1206201 31103e5343bdSAlex Deucher #define ixPSX80_PHY0_COM_COMMON_FUSE3 0x1206202 31113e5343bdSAlex Deucher #define ixPSX80_PHY0_COM_COMMON_ELECIDLE 0x1206204 31123e5343bdSAlex Deucher #define ixPSX80_PHY0_COM_COMMON_DFX 0x1206205 31133e5343bdSAlex Deucher #define ixPSX80_PHY0_COM_COMMON_MAR_DEEMPH_NOM 0x1206206 31143e5343bdSAlex Deucher #define ixPSX80_PHY0_COM_COMMON_SELDEEMPH35 0x1206207 31153e5343bdSAlex Deucher #define ixPSX80_PHY0_COM_COMMON_SELDEEMPH60 0x1206208 31163e5343bdSAlex Deucher #define ixPSX80_PHY0_COM_COMMON_LANE_PWRMGMT 0x1206209 31173e5343bdSAlex Deucher #define ixPSX80_PHY0_COM_COMMON_ADAPTCTL1 0x120620a 31183e5343bdSAlex Deucher #define ixPSX80_PHY0_COM_COMMON_ADAPTCTL2 0x120620b 31193e5343bdSAlex Deucher #define ixPSX80_PHY0_COM_COMMON_ADAPT_CFG_BYP_VAL 0x120620c 31203e5343bdSAlex Deucher #define ixPSX80_PHY0_COM_COMMON_ADAPT_CFG_BYP_VAL1 0x120620d 31213e5343bdSAlex Deucher #define ixPSX80_PHY0_COM_COMMON_ADAPT_DBG_BYP_VAL 0x120620e 31223e5343bdSAlex Deucher #define ixPSX80_PHY0_COM_COMMON_ADAPT_DBG_BYP_VAL1 0x120620f 31233e5343bdSAlex Deucher #define ixPSX80_PHY0_COM_COMMON_ADAPT_DBG1 0x1206210 31243e5343bdSAlex Deucher #define ixPSX80_PHY0_COM_COMMON_LNCNTRL 0x1206211 31253e5343bdSAlex Deucher #define ixPSX80_PHY0_COM_COMMON_TXTESTDEBUG 0x1206212 31263e5343bdSAlex Deucher #define ixPSX80_PHY0_COM_COMMON_RXTESTDEBUG 0x1206213 31273e5343bdSAlex Deucher #define ixPSX80_PHY0_COM_COMMON_CDR_PHCTL 0x1206214 31283e5343bdSAlex Deucher #define ixPSX80_PHY0_COM_COMMON_CDR_FRCTL 0x1206215 31293e5343bdSAlex Deucher #define ixPSX80_PHY0_RX_CMD_BUS_RX_CONTROL_BROADCAST 0x120fe00 31303e5343bdSAlex Deucher #define ixPSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE0 0x1200000 31313e5343bdSAlex Deucher #define ixPSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE1 0x1200100 31323e5343bdSAlex Deucher #define ixPSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE2 0x1200200 31333e5343bdSAlex Deucher #define ixPSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE3 0x1200300 31343e5343bdSAlex Deucher #define ixPSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE4 0x1200400 31353e5343bdSAlex Deucher #define ixPSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE5 0x1200500 31363e5343bdSAlex Deucher #define ixPSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE6 0x1200600 31373e5343bdSAlex Deucher #define ixPSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE7 0x1200700 31383e5343bdSAlex Deucher #define ixPSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_BROADCAST 0x120fe01 31393e5343bdSAlex Deucher #define ixPSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE0 0x1200001 31403e5343bdSAlex Deucher #define ixPSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE1 0x1200101 31413e5343bdSAlex Deucher #define ixPSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE2 0x1200201 31423e5343bdSAlex Deucher #define ixPSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE3 0x1200301 31433e5343bdSAlex Deucher #define ixPSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE4 0x1200401 31443e5343bdSAlex Deucher #define ixPSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE5 0x1200501 31453e5343bdSAlex Deucher #define ixPSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE6 0x1200601 31463e5343bdSAlex Deucher #define ixPSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE7 0x1200701 31473e5343bdSAlex Deucher #define ixPSX80_PHY0_RX_RX_CTL_BROADCAST 0x120fe02 31483e5343bdSAlex Deucher #define ixPSX80_PHY0_RX_RX_CTL_LANE0 0x1200002 31493e5343bdSAlex Deucher #define ixPSX80_PHY0_RX_RX_CTL_LANE1 0x1200102 31503e5343bdSAlex Deucher #define ixPSX80_PHY0_RX_RX_CTL_LANE2 0x1200202 31513e5343bdSAlex Deucher #define ixPSX80_PHY0_RX_RX_CTL_LANE3 0x1200302 31523e5343bdSAlex Deucher #define ixPSX80_PHY0_RX_RX_CTL_LANE4 0x1200402 31533e5343bdSAlex Deucher #define ixPSX80_PHY0_RX_RX_CTL_LANE5 0x1200502 31543e5343bdSAlex Deucher #define ixPSX80_PHY0_RX_RX_CTL_LANE6 0x1200602 31553e5343bdSAlex Deucher #define ixPSX80_PHY0_RX_RX_CTL_LANE7 0x1200702 31563e5343bdSAlex Deucher #define ixPSX80_PHY0_RX_DLL_CTL_BROADCAST 0x120fe03 31573e5343bdSAlex Deucher #define ixPSX80_PHY0_RX_DLL_CTL_LANE0 0x1200003 31583e5343bdSAlex Deucher #define ixPSX80_PHY0_RX_DLL_CTL_LANE1 0x1200103 31593e5343bdSAlex Deucher #define ixPSX80_PHY0_RX_DLL_CTL_LANE2 0x1200203 31603e5343bdSAlex Deucher #define ixPSX80_PHY0_RX_DLL_CTL_LANE3 0x1200303 31613e5343bdSAlex Deucher #define ixPSX80_PHY0_RX_DLL_CTL_LANE4 0x1200403 31623e5343bdSAlex Deucher #define ixPSX80_PHY0_RX_DLL_CTL_LANE5 0x1200503 31633e5343bdSAlex Deucher #define ixPSX80_PHY0_RX_DLL_CTL_LANE6 0x1200603 31643e5343bdSAlex Deucher #define ixPSX80_PHY0_RX_DLL_CTL_LANE7 0x1200703 31653e5343bdSAlex Deucher #define ixPSX80_PHY0_RX_RXTEST_REGS_BROADCAST 0x120fe04 31663e5343bdSAlex Deucher #define ixPSX80_PHY0_RX_RXTEST_REGS_LANE0 0x1200004 31673e5343bdSAlex Deucher #define ixPSX80_PHY0_RX_RXTEST_REGS_LANE1 0x1200104 31683e5343bdSAlex Deucher #define ixPSX80_PHY0_RX_RXTEST_REGS_LANE2 0x1200204 31693e5343bdSAlex Deucher #define ixPSX80_PHY0_RX_RXTEST_REGS_LANE3 0x1200304 31703e5343bdSAlex Deucher #define ixPSX80_PHY0_RX_RXTEST_REGS_LANE4 0x1200404 31713e5343bdSAlex Deucher #define ixPSX80_PHY0_RX_RXTEST_REGS_LANE5 0x1200504 31723e5343bdSAlex Deucher #define ixPSX80_PHY0_RX_RXTEST_REGS_LANE6 0x1200604 31733e5343bdSAlex Deucher #define ixPSX80_PHY0_RX_RXTEST_REGS_LANE7 0x1200704 31743e5343bdSAlex Deucher #define ixPSX80_PHY0_RX_ELECIDLE_DEBUG_BROADCAST 0x120fe05 31753e5343bdSAlex Deucher #define ixPSX80_PHY0_RX_ELECIDLE_DEBUG_LANE0 0x1200005 31763e5343bdSAlex Deucher #define ixPSX80_PHY0_RX_ELECIDLE_DEBUG_LANE1 0x1200105 31773e5343bdSAlex Deucher #define ixPSX80_PHY0_RX_ELECIDLE_DEBUG_LANE2 0x1200205 31783e5343bdSAlex Deucher #define ixPSX80_PHY0_RX_ELECIDLE_DEBUG_LANE3 0x1200305 31793e5343bdSAlex Deucher #define ixPSX80_PHY0_RX_ELECIDLE_DEBUG_LANE4 0x1200405 31803e5343bdSAlex Deucher #define ixPSX80_PHY0_RX_ELECIDLE_DEBUG_LANE5 0x1200505 31813e5343bdSAlex Deucher #define ixPSX80_PHY0_RX_ELECIDLE_DEBUG_LANE6 0x1200605 31823e5343bdSAlex Deucher #define ixPSX80_PHY0_RX_ELECIDLE_DEBUG_LANE7 0x1200705 31833e5343bdSAlex Deucher #define ixPSX80_PHY0_RX_ADAPTCTL_BROADCAST 0x120fe0a 31843e5343bdSAlex Deucher #define ixPSX80_PHY0_RX_ADAPTCTL_LANE0 0x120000a 31853e5343bdSAlex Deucher #define ixPSX80_PHY0_RX_ADAPTCTL_LANE1 0x120010a 31863e5343bdSAlex Deucher #define ixPSX80_PHY0_RX_ADAPTCTL_LANE2 0x120020a 31873e5343bdSAlex Deucher #define ixPSX80_PHY0_RX_ADAPTCTL_LANE3 0x120030a 31883e5343bdSAlex Deucher #define ixPSX80_PHY0_RX_ADAPTCTL_LANE4 0x120040a 31893e5343bdSAlex Deucher #define ixPSX80_PHY0_RX_ADAPTCTL_LANE5 0x120050a 31903e5343bdSAlex Deucher #define ixPSX80_PHY0_RX_ADAPTCTL_LANE6 0x120060a 31913e5343bdSAlex Deucher #define ixPSX80_PHY0_RX_ADAPTCTL_LANE7 0x120070a 31923e5343bdSAlex Deucher #define ixPSX80_PHY0_RX_FOMCALCCTL_BROADCAST 0x120fe0b 31933e5343bdSAlex Deucher #define ixPSX80_PHY0_RX_FOMCALCCTL_LANE0 0x120000b 31943e5343bdSAlex Deucher #define ixPSX80_PHY0_RX_FOMCALCCTL_LANE1 0x120010b 31953e5343bdSAlex Deucher #define ixPSX80_PHY0_RX_FOMCALCCTL_LANE2 0x120020b 31963e5343bdSAlex Deucher #define ixPSX80_PHY0_RX_FOMCALCCTL_LANE3 0x120030b 31973e5343bdSAlex Deucher #define ixPSX80_PHY0_RX_FOMCALCCTL_LANE4 0x120040b 31983e5343bdSAlex Deucher #define ixPSX80_PHY0_RX_FOMCALCCTL_LANE5 0x120050b 31993e5343bdSAlex Deucher #define ixPSX80_PHY0_RX_FOMCALCCTL_LANE6 0x120060b 32003e5343bdSAlex Deucher #define ixPSX80_PHY0_RX_FOMCALCCTL_LANE7 0x120070b 32013e5343bdSAlex Deucher #define ixPSX80_PHY0_RX_ADAPT_CFG_BYP_EN_BROADCAST 0x120fe0c 32023e5343bdSAlex Deucher #define ixPSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE0 0x120000c 32033e5343bdSAlex Deucher #define ixPSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE1 0x120010c 32043e5343bdSAlex Deucher #define ixPSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE2 0x120020c 32053e5343bdSAlex Deucher #define ixPSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE3 0x120030c 32063e5343bdSAlex Deucher #define ixPSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE4 0x120040c 32073e5343bdSAlex Deucher #define ixPSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE5 0x120050c 32083e5343bdSAlex Deucher #define ixPSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE6 0x120060c 32093e5343bdSAlex Deucher #define ixPSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE7 0x120070c 32103e5343bdSAlex Deucher #define ixPSX80_PHY0_RX_DBG_BYP_EN_BROADCAST 0x120fe0d 32113e5343bdSAlex Deucher #define ixPSX80_PHY0_RX_DBG_BYP_EN_LANE0 0x120000d 32123e5343bdSAlex Deucher #define ixPSX80_PHY0_RX_DBG_BYP_EN_LANE1 0x120010d 32133e5343bdSAlex Deucher #define ixPSX80_PHY0_RX_DBG_BYP_EN_LANE2 0x120020d 32143e5343bdSAlex Deucher #define ixPSX80_PHY0_RX_DBG_BYP_EN_LANE3 0x120030d 32153e5343bdSAlex Deucher #define ixPSX80_PHY0_RX_DBG_BYP_EN_LANE4 0x120040d 32163e5343bdSAlex Deucher #define ixPSX80_PHY0_RX_DBG_BYP_EN_LANE5 0x120050d 32173e5343bdSAlex Deucher #define ixPSX80_PHY0_RX_DBG_BYP_EN_LANE6 0x120060d 32183e5343bdSAlex Deucher #define ixPSX80_PHY0_RX_DBG_BYP_EN_LANE7 0x120070d 32193e5343bdSAlex Deucher #define ixPSX80_PHY0_RX_ADAPTDBG1_BROADCAST 0x120fe0e 32203e5343bdSAlex Deucher #define ixPSX80_PHY0_RX_ADAPTDBG1_LANE0 0x120000e 32213e5343bdSAlex Deucher #define ixPSX80_PHY0_RX_ADAPTDBG1_LANE1 0x120010e 32223e5343bdSAlex Deucher #define ixPSX80_PHY0_RX_ADAPTDBG1_LANE2 0x120020e 32233e5343bdSAlex Deucher #define ixPSX80_PHY0_RX_ADAPTDBG1_LANE3 0x120030e 32243e5343bdSAlex Deucher #define ixPSX80_PHY0_RX_ADAPTDBG1_LANE4 0x120040e 32253e5343bdSAlex Deucher #define ixPSX80_PHY0_RX_ADAPTDBG1_LANE5 0x120050e 32263e5343bdSAlex Deucher #define ixPSX80_PHY0_RX_ADAPTDBG1_LANE6 0x120060e 32273e5343bdSAlex Deucher #define ixPSX80_PHY0_RX_ADAPTDBG1_LANE7 0x120070e 32283e5343bdSAlex Deucher #define ixPSX80_PHY0_TX_CMD_BUS_TX_CONTROL_BROADCAST 0x120ff00 32293e5343bdSAlex Deucher #define ixPSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE0 0x1202000 32303e5343bdSAlex Deucher #define ixPSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE1 0x1202100 32313e5343bdSAlex Deucher #define ixPSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE2 0x1202200 32323e5343bdSAlex Deucher #define ixPSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE3 0x1202300 32333e5343bdSAlex Deucher #define ixPSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE4 0x1202400 32343e5343bdSAlex Deucher #define ixPSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE5 0x1202500 32353e5343bdSAlex Deucher #define ixPSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE6 0x1202600 32363e5343bdSAlex Deucher #define ixPSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE7 0x1202700 32373e5343bdSAlex Deucher #define ixPSX80_PHY0_TX_DFX_BROADCAST 0x120ff01 32383e5343bdSAlex Deucher #define ixPSX80_PHY0_TX_DFX_LANE0 0x1202001 32393e5343bdSAlex Deucher #define ixPSX80_PHY0_TX_DFX_LANE1 0x1202101 32403e5343bdSAlex Deucher #define ixPSX80_PHY0_TX_DFX_LANE2 0x1202201 32413e5343bdSAlex Deucher #define ixPSX80_PHY0_TX_DFX_LANE3 0x1202301 32423e5343bdSAlex Deucher #define ixPSX80_PHY0_TX_DFX_LANE4 0x1202401 32433e5343bdSAlex Deucher #define ixPSX80_PHY0_TX_DFX_LANE5 0x1202501 32443e5343bdSAlex Deucher #define ixPSX80_PHY0_TX_DFX_LANE6 0x1202601 32453e5343bdSAlex Deucher #define ixPSX80_PHY0_TX_DFX_LANE7 0x1202701 32463e5343bdSAlex Deucher #define ixPSX80_PHY0_TX_DEEMPH_BROADCAST 0x120ff02 32473e5343bdSAlex Deucher #define ixPSX80_PHY0_TX_DEEMPH_LANE0 0x1202002 32483e5343bdSAlex Deucher #define ixPSX80_PHY0_TX_DEEMPH_LANE1 0x1202102 32493e5343bdSAlex Deucher #define ixPSX80_PHY0_TX_DEEMPH_LANE2 0x1202202 32503e5343bdSAlex Deucher #define ixPSX80_PHY0_TX_DEEMPH_LANE3 0x1202302 32513e5343bdSAlex Deucher #define ixPSX80_PHY0_TX_DEEMPH_LANE4 0x1202402 32523e5343bdSAlex Deucher #define ixPSX80_PHY0_TX_DEEMPH_LANE5 0x1202502 32533e5343bdSAlex Deucher #define ixPSX80_PHY0_TX_DEEMPH_LANE6 0x1202602 32543e5343bdSAlex Deucher #define ixPSX80_PHY0_TX_DEEMPH_LANE7 0x1202702 32553e5343bdSAlex Deucher #define ixPSX80_PHY0_TX_TSTMARGDEEMPH_BROADCAST 0x120ff03 32563e5343bdSAlex Deucher #define ixPSX80_PHY0_TX_TSTMARGDEEMPH_LANE0 0x1202003 32573e5343bdSAlex Deucher #define ixPSX80_PHY0_TX_TSTMARGDEEMPH_LANE1 0x1202103 32583e5343bdSAlex Deucher #define ixPSX80_PHY0_TX_TSTMARGDEEMPH_LANE2 0x1202203 32593e5343bdSAlex Deucher #define ixPSX80_PHY0_TX_TSTMARGDEEMPH_LANE3 0x1202303 32603e5343bdSAlex Deucher #define ixPSX80_PHY0_TX_TSTMARGDEEMPH_LANE4 0x1202403 32613e5343bdSAlex Deucher #define ixPSX80_PHY0_TX_TSTMARGDEEMPH_LANE5 0x1202503 32623e5343bdSAlex Deucher #define ixPSX80_PHY0_TX_TSTMARGDEEMPH_LANE6 0x1202603 32633e5343bdSAlex Deucher #define ixPSX80_PHY0_TX_TSTMARGDEEMPH_LANE7 0x1202703 32643e5343bdSAlex Deucher #define ixPSX80_PHY0_TX_MARGDEEMPHSTATUS_BROADCAST 0x120ff04 32653e5343bdSAlex Deucher #define ixPSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE0 0x1202004 32663e5343bdSAlex Deucher #define ixPSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE1 0x1202104 32673e5343bdSAlex Deucher #define ixPSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE2 0x1202204 32683e5343bdSAlex Deucher #define ixPSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE3 0x1202304 32693e5343bdSAlex Deucher #define ixPSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE4 0x1202404 32703e5343bdSAlex Deucher #define ixPSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE5 0x1202504 32713e5343bdSAlex Deucher #define ixPSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE6 0x1202604 32723e5343bdSAlex Deucher #define ixPSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE7 0x1202704 32733e5343bdSAlex Deucher #define ixPSX80_PHY0_TX_TXCNTRL_BROADCAST 0x120ff06 32743e5343bdSAlex Deucher #define ixPSX80_PHY0_TX_TXCNTRL_LANE0 0x1202006 32753e5343bdSAlex Deucher #define ixPSX80_PHY0_TX_TXCNTRL_LANE1 0x1202106 32763e5343bdSAlex Deucher #define ixPSX80_PHY0_TX_TXCNTRL_LANE2 0x1202206 32773e5343bdSAlex Deucher #define ixPSX80_PHY0_TX_TXCNTRL_LANE3 0x1202306 32783e5343bdSAlex Deucher #define ixPSX80_PHY0_TX_TXCNTRL_LANE4 0x1202406 32793e5343bdSAlex Deucher #define ixPSX80_PHY0_TX_TXCNTRL_LANE5 0x1202506 32803e5343bdSAlex Deucher #define ixPSX80_PHY0_TX_TXCNTRL_LANE6 0x1202606 32813e5343bdSAlex Deucher #define ixPSX80_PHY0_TX_TXCNTRL_LANE7 0x1202706 32823e5343bdSAlex Deucher #define ixPSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_BROADCAST 0x120ff07 32833e5343bdSAlex Deucher #define ixPSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE0 0x1202007 32843e5343bdSAlex Deucher #define ixPSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE1 0x1202107 32853e5343bdSAlex Deucher #define ixPSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE2 0x1202207 32863e5343bdSAlex Deucher #define ixPSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE3 0x1202307 32873e5343bdSAlex Deucher #define ixPSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE4 0x1202407 32883e5343bdSAlex Deucher #define ixPSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE5 0x1202507 32893e5343bdSAlex Deucher #define ixPSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE6 0x1202607 32903e5343bdSAlex Deucher #define ixPSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE7 0x1202707 32913e5343bdSAlex Deucher #define ixPSX80_PHY0_HTPLL_ROPLL_PowerDownEn 0x1204180 32923e5343bdSAlex Deucher #define ixPSX80_PHY0_HTPLL_ROPLL_PciPllControlExt 0x1204101 32933e5343bdSAlex Deucher #define ixPSX80_PHY0_HTPLL_ROPLL_PciPllControl 0x1204102 32943e5343bdSAlex Deucher #define ixPSX80_PHY0_HTPLL_ROPLL_PciPllTestDebug1 0x1204103 32953e5343bdSAlex Deucher #define ixPSX80_PHY0_HTPLL_ROPLL_PciPllTestDebug2 0x1204104 32963e5343bdSAlex Deucher #define ixPSX80_PHY0_HTPLL_ROPLL_PciPllFreqMode 0x1204105 32973e5343bdSAlex Deucher #define ixPSX80_PHY0_HTPLL_ROPLL_PciPllUpdateCtrl 0x1204108 32983e5343bdSAlex Deucher #define ixPSX80_PHY0_HTPLL_ROPLL_PciPllTestDebug3 0x1204109 32993e5343bdSAlex Deucher #define ixPSX80_PHY0_HTPLL_ROPLL_PciFuseProcess 0x120410a 33003e5343bdSAlex Deucher #define ixPSX80_PHY0_HTPLL_ROPLL_PciPllTestDebug4 0x120410b 33013e5343bdSAlex Deucher #define ixPSX80_PHY0_HTPLL_ROPLL_PciPllTestDebug5 0x120410c 33023e5343bdSAlex Deucher #define ixPSX80_PHY0_LCPLL_LCPLL_PowerDownEn 0x1204080 33033e5343bdSAlex Deucher #define ixPSX80_PHY0_LCPLL_LCPLL_PciPllControlExt 0x1204001 33043e5343bdSAlex Deucher #define ixPSX80_PHY0_LCPLL_LCPLL_PciPllControl 0x1204002 33053e5343bdSAlex Deucher #define ixPSX80_PHY0_LCPLL_LCPLL_PciPllTestDebug1 0x1204003 33063e5343bdSAlex Deucher #define ixPSX80_PHY0_LCPLL_LCPLL_PciPllTestDebug2 0x1204004 33073e5343bdSAlex Deucher #define ixPSX80_PHY0_LCPLL_LCPLL_PciPllFreqMode 0x1204005 33083e5343bdSAlex Deucher #define ixPSX80_PHY0_LCPLL_LCPLL_PciLcVcoCtrl 0x1204007 33093e5343bdSAlex Deucher #define ixPSX80_PHY0_LCPLL_LCPLL_PciPllUpdateCtrl 0x1204008 33103e5343bdSAlex Deucher #define ixPSX80_PHY0_LCPLL_LCPLL_PciPllTestDebug3 0x1204009 33113e5343bdSAlex Deucher #define ixPSX80_PHY0_LCPLL_LCPLL_PciPllTestDebug4 0x120400b 33123e5343bdSAlex Deucher #define ixPSX80_PHY0_LCPLL_LCPLL_PciPllTestDebug5 0x120400c 33133e5343bdSAlex Deucher #define ixPSX81_PHY0_COM_COMMON_FUSE1 0x1216200 33143e5343bdSAlex Deucher #define ixPSX81_PHY0_COM_COMMON_FUSE2 0x1216201 33153e5343bdSAlex Deucher #define ixPSX81_PHY0_COM_COMMON_FUSE3 0x1216202 33163e5343bdSAlex Deucher #define ixPSX81_PHY0_COM_COMMON_ELECIDLE 0x1216204 33173e5343bdSAlex Deucher #define ixPSX81_PHY0_COM_COMMON_DFX 0x1216205 33183e5343bdSAlex Deucher #define ixPSX81_PHY0_COM_COMMON_MAR_DEEMPH_NOM 0x1216206 33193e5343bdSAlex Deucher #define ixPSX81_PHY0_COM_COMMON_SELDEEMPH35 0x1216207 33203e5343bdSAlex Deucher #define ixPSX81_PHY0_COM_COMMON_SELDEEMPH60 0x1216208 33213e5343bdSAlex Deucher #define ixPSX81_PHY0_COM_COMMON_LANE_PWRMGMT 0x1216209 33223e5343bdSAlex Deucher #define ixPSX81_PHY0_COM_COMMON_ADAPTCTL1 0x121620a 33233e5343bdSAlex Deucher #define ixPSX81_PHY0_COM_COMMON_ADAPTCTL2 0x121620b 33243e5343bdSAlex Deucher #define ixPSX81_PHY0_COM_COMMON_ADAPT_CFG_BYP_VAL 0x121620c 33253e5343bdSAlex Deucher #define ixPSX81_PHY0_COM_COMMON_ADAPT_CFG_BYP_VAL1 0x121620d 33263e5343bdSAlex Deucher #define ixPSX81_PHY0_COM_COMMON_ADAPT_DBG_BYP_VAL 0x121620e 33273e5343bdSAlex Deucher #define ixPSX81_PHY0_COM_COMMON_ADAPT_DBG_BYP_VAL1 0x121620f 33283e5343bdSAlex Deucher #define ixPSX81_PHY0_COM_COMMON_ADAPT_DBG1 0x1216210 33293e5343bdSAlex Deucher #define ixPSX81_PHY0_COM_COMMON_LNCNTRL 0x1216211 33303e5343bdSAlex Deucher #define ixPSX81_PHY0_COM_COMMON_TXTESTDEBUG 0x1216212 33313e5343bdSAlex Deucher #define ixPSX81_PHY0_COM_COMMON_RXTESTDEBUG 0x1216213 33323e5343bdSAlex Deucher #define ixPSX81_PHY0_COM_COMMON_CDR_PHCTL 0x1216214 33333e5343bdSAlex Deucher #define ixPSX81_PHY0_COM_COMMON_CDR_FRCTL 0x1216215 33343e5343bdSAlex Deucher #define ixPSX81_PHY0_RX_CMD_BUS_RX_CONTROL_BROADCAST 0x121fe00 33353e5343bdSAlex Deucher #define ixPSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE0 0x1210000 33363e5343bdSAlex Deucher #define ixPSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE1 0x1210100 33373e5343bdSAlex Deucher #define ixPSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE2 0x1210200 33383e5343bdSAlex Deucher #define ixPSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE3 0x1210300 33393e5343bdSAlex Deucher #define ixPSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE4 0x1210400 33403e5343bdSAlex Deucher #define ixPSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE5 0x1210500 33413e5343bdSAlex Deucher #define ixPSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE6 0x1210600 33423e5343bdSAlex Deucher #define ixPSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE7 0x1210700 33433e5343bdSAlex Deucher #define ixPSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_BROADCAST 0x121fe01 33443e5343bdSAlex Deucher #define ixPSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE0 0x1210001 33453e5343bdSAlex Deucher #define ixPSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE1 0x1210101 33463e5343bdSAlex Deucher #define ixPSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE2 0x1210201 33473e5343bdSAlex Deucher #define ixPSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE3 0x1210301 33483e5343bdSAlex Deucher #define ixPSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE4 0x1210401 33493e5343bdSAlex Deucher #define ixPSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE5 0x1210501 33503e5343bdSAlex Deucher #define ixPSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE6 0x1210601 33513e5343bdSAlex Deucher #define ixPSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE7 0x1210701 33523e5343bdSAlex Deucher #define ixPSX81_PHY0_RX_RX_CTL_BROADCAST 0x121fe02 33533e5343bdSAlex Deucher #define ixPSX81_PHY0_RX_RX_CTL_LANE0 0x1210002 33543e5343bdSAlex Deucher #define ixPSX81_PHY0_RX_RX_CTL_LANE1 0x1210102 33553e5343bdSAlex Deucher #define ixPSX81_PHY0_RX_RX_CTL_LANE2 0x1210202 33563e5343bdSAlex Deucher #define ixPSX81_PHY0_RX_RX_CTL_LANE3 0x1210302 33573e5343bdSAlex Deucher #define ixPSX81_PHY0_RX_RX_CTL_LANE4 0x1210402 33583e5343bdSAlex Deucher #define ixPSX81_PHY0_RX_RX_CTL_LANE5 0x1210502 33593e5343bdSAlex Deucher #define ixPSX81_PHY0_RX_RX_CTL_LANE6 0x1210602 33603e5343bdSAlex Deucher #define ixPSX81_PHY0_RX_RX_CTL_LANE7 0x1210702 33613e5343bdSAlex Deucher #define ixPSX81_PHY0_RX_DLL_CTL_BROADCAST 0x121fe03 33623e5343bdSAlex Deucher #define ixPSX81_PHY0_RX_DLL_CTL_LANE0 0x1210003 33633e5343bdSAlex Deucher #define ixPSX81_PHY0_RX_DLL_CTL_LANE1 0x1210103 33643e5343bdSAlex Deucher #define ixPSX81_PHY0_RX_DLL_CTL_LANE2 0x1210203 33653e5343bdSAlex Deucher #define ixPSX81_PHY0_RX_DLL_CTL_LANE3 0x1210303 33663e5343bdSAlex Deucher #define ixPSX81_PHY0_RX_DLL_CTL_LANE4 0x1210403 33673e5343bdSAlex Deucher #define ixPSX81_PHY0_RX_DLL_CTL_LANE5 0x1210503 33683e5343bdSAlex Deucher #define ixPSX81_PHY0_RX_DLL_CTL_LANE6 0x1210603 33693e5343bdSAlex Deucher #define ixPSX81_PHY0_RX_DLL_CTL_LANE7 0x1210703 33703e5343bdSAlex Deucher #define ixPSX81_PHY0_RX_RXTEST_REGS_BROADCAST 0x121fe04 33713e5343bdSAlex Deucher #define ixPSX81_PHY0_RX_RXTEST_REGS_LANE0 0x1210004 33723e5343bdSAlex Deucher #define ixPSX81_PHY0_RX_RXTEST_REGS_LANE1 0x1210104 33733e5343bdSAlex Deucher #define ixPSX81_PHY0_RX_RXTEST_REGS_LANE2 0x1210204 33743e5343bdSAlex Deucher #define ixPSX81_PHY0_RX_RXTEST_REGS_LANE3 0x1210304 33753e5343bdSAlex Deucher #define ixPSX81_PHY0_RX_RXTEST_REGS_LANE4 0x1210404 33763e5343bdSAlex Deucher #define ixPSX81_PHY0_RX_RXTEST_REGS_LANE5 0x1210504 33773e5343bdSAlex Deucher #define ixPSX81_PHY0_RX_RXTEST_REGS_LANE6 0x1210604 33783e5343bdSAlex Deucher #define ixPSX81_PHY0_RX_RXTEST_REGS_LANE7 0x1210704 33793e5343bdSAlex Deucher #define ixPSX81_PHY0_RX_ELECIDLE_DEBUG_BROADCAST 0x121fe05 33803e5343bdSAlex Deucher #define ixPSX81_PHY0_RX_ELECIDLE_DEBUG_LANE0 0x1210005 33813e5343bdSAlex Deucher #define ixPSX81_PHY0_RX_ELECIDLE_DEBUG_LANE1 0x1210105 33823e5343bdSAlex Deucher #define ixPSX81_PHY0_RX_ELECIDLE_DEBUG_LANE2 0x1210205 33833e5343bdSAlex Deucher #define ixPSX81_PHY0_RX_ELECIDLE_DEBUG_LANE3 0x1210305 33843e5343bdSAlex Deucher #define ixPSX81_PHY0_RX_ELECIDLE_DEBUG_LANE4 0x1210405 33853e5343bdSAlex Deucher #define ixPSX81_PHY0_RX_ELECIDLE_DEBUG_LANE5 0x1210505 33863e5343bdSAlex Deucher #define ixPSX81_PHY0_RX_ELECIDLE_DEBUG_LANE6 0x1210605 33873e5343bdSAlex Deucher #define ixPSX81_PHY0_RX_ELECIDLE_DEBUG_LANE7 0x1210705 33883e5343bdSAlex Deucher #define ixPSX81_PHY0_RX_ADAPTCTL_BROADCAST 0x121fe0a 33893e5343bdSAlex Deucher #define ixPSX81_PHY0_RX_ADAPTCTL_LANE0 0x121000a 33903e5343bdSAlex Deucher #define ixPSX81_PHY0_RX_ADAPTCTL_LANE1 0x121010a 33913e5343bdSAlex Deucher #define ixPSX81_PHY0_RX_ADAPTCTL_LANE2 0x121020a 33923e5343bdSAlex Deucher #define ixPSX81_PHY0_RX_ADAPTCTL_LANE3 0x121030a 33933e5343bdSAlex Deucher #define ixPSX81_PHY0_RX_ADAPTCTL_LANE4 0x121040a 33943e5343bdSAlex Deucher #define ixPSX81_PHY0_RX_ADAPTCTL_LANE5 0x121050a 33953e5343bdSAlex Deucher #define ixPSX81_PHY0_RX_ADAPTCTL_LANE6 0x121060a 33963e5343bdSAlex Deucher #define ixPSX81_PHY0_RX_ADAPTCTL_LANE7 0x121070a 33973e5343bdSAlex Deucher #define ixPSX81_PHY0_RX_FOMCALCCTL_BROADCAST 0x121fe0b 33983e5343bdSAlex Deucher #define ixPSX81_PHY0_RX_FOMCALCCTL_LANE0 0x121000b 33993e5343bdSAlex Deucher #define ixPSX81_PHY0_RX_FOMCALCCTL_LANE1 0x121010b 34003e5343bdSAlex Deucher #define ixPSX81_PHY0_RX_FOMCALCCTL_LANE2 0x121020b 34013e5343bdSAlex Deucher #define ixPSX81_PHY0_RX_FOMCALCCTL_LANE3 0x121030b 34023e5343bdSAlex Deucher #define ixPSX81_PHY0_RX_FOMCALCCTL_LANE4 0x121040b 34033e5343bdSAlex Deucher #define ixPSX81_PHY0_RX_FOMCALCCTL_LANE5 0x121050b 34043e5343bdSAlex Deucher #define ixPSX81_PHY0_RX_FOMCALCCTL_LANE6 0x121060b 34053e5343bdSAlex Deucher #define ixPSX81_PHY0_RX_FOMCALCCTL_LANE7 0x121070b 34063e5343bdSAlex Deucher #define ixPSX81_PHY0_RX_ADAPT_CFG_BYP_EN_BROADCAST 0x121fe0c 34073e5343bdSAlex Deucher #define ixPSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE0 0x121000c 34083e5343bdSAlex Deucher #define ixPSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE1 0x121010c 34093e5343bdSAlex Deucher #define ixPSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE2 0x121020c 34103e5343bdSAlex Deucher #define ixPSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE3 0x121030c 34113e5343bdSAlex Deucher #define ixPSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE4 0x121040c 34123e5343bdSAlex Deucher #define ixPSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE5 0x121050c 34133e5343bdSAlex Deucher #define ixPSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE6 0x121060c 34143e5343bdSAlex Deucher #define ixPSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE7 0x121070c 34153e5343bdSAlex Deucher #define ixPSX81_PHY0_RX_DBG_BYP_EN_BROADCAST 0x121fe0d 34163e5343bdSAlex Deucher #define ixPSX81_PHY0_RX_DBG_BYP_EN_LANE0 0x121000d 34173e5343bdSAlex Deucher #define ixPSX81_PHY0_RX_DBG_BYP_EN_LANE1 0x121010d 34183e5343bdSAlex Deucher #define ixPSX81_PHY0_RX_DBG_BYP_EN_LANE2 0x121020d 34193e5343bdSAlex Deucher #define ixPSX81_PHY0_RX_DBG_BYP_EN_LANE3 0x121030d 34203e5343bdSAlex Deucher #define ixPSX81_PHY0_RX_DBG_BYP_EN_LANE4 0x121040d 34213e5343bdSAlex Deucher #define ixPSX81_PHY0_RX_DBG_BYP_EN_LANE5 0x121050d 34223e5343bdSAlex Deucher #define ixPSX81_PHY0_RX_DBG_BYP_EN_LANE6 0x121060d 34233e5343bdSAlex Deucher #define ixPSX81_PHY0_RX_DBG_BYP_EN_LANE7 0x121070d 34243e5343bdSAlex Deucher #define ixPSX81_PHY0_RX_ADAPTDBG1_BROADCAST 0x121fe0e 34253e5343bdSAlex Deucher #define ixPSX81_PHY0_RX_ADAPTDBG1_LANE0 0x121000e 34263e5343bdSAlex Deucher #define ixPSX81_PHY0_RX_ADAPTDBG1_LANE1 0x121010e 34273e5343bdSAlex Deucher #define ixPSX81_PHY0_RX_ADAPTDBG1_LANE2 0x121020e 34283e5343bdSAlex Deucher #define ixPSX81_PHY0_RX_ADAPTDBG1_LANE3 0x121030e 34293e5343bdSAlex Deucher #define ixPSX81_PHY0_RX_ADAPTDBG1_LANE4 0x121040e 34303e5343bdSAlex Deucher #define ixPSX81_PHY0_RX_ADAPTDBG1_LANE5 0x121050e 34313e5343bdSAlex Deucher #define ixPSX81_PHY0_RX_ADAPTDBG1_LANE6 0x121060e 34323e5343bdSAlex Deucher #define ixPSX81_PHY0_RX_ADAPTDBG1_LANE7 0x121070e 34333e5343bdSAlex Deucher #define ixPSX81_PHY0_TX_CMD_BUS_TX_CONTROL_BROADCAST 0x121ff00 34343e5343bdSAlex Deucher #define ixPSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE0 0x1212000 34353e5343bdSAlex Deucher #define ixPSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE1 0x1212100 34363e5343bdSAlex Deucher #define ixPSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE2 0x1212200 34373e5343bdSAlex Deucher #define ixPSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE3 0x1212300 34383e5343bdSAlex Deucher #define ixPSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE4 0x1212400 34393e5343bdSAlex Deucher #define ixPSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE5 0x1212500 34403e5343bdSAlex Deucher #define ixPSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE6 0x1212600 34413e5343bdSAlex Deucher #define ixPSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE7 0x1212700 34423e5343bdSAlex Deucher #define ixPSX81_PHY0_TX_DFX_BROADCAST 0x121ff01 34433e5343bdSAlex Deucher #define ixPSX81_PHY0_TX_DFX_LANE0 0x1212001 34443e5343bdSAlex Deucher #define ixPSX81_PHY0_TX_DFX_LANE1 0x1212101 34453e5343bdSAlex Deucher #define ixPSX81_PHY0_TX_DFX_LANE2 0x1212201 34463e5343bdSAlex Deucher #define ixPSX81_PHY0_TX_DFX_LANE3 0x1212301 34473e5343bdSAlex Deucher #define ixPSX81_PHY0_TX_DFX_LANE4 0x1212401 34483e5343bdSAlex Deucher #define ixPSX81_PHY0_TX_DFX_LANE5 0x1212501 34493e5343bdSAlex Deucher #define ixPSX81_PHY0_TX_DFX_LANE6 0x1212601 34503e5343bdSAlex Deucher #define ixPSX81_PHY0_TX_DFX_LANE7 0x1212701 34513e5343bdSAlex Deucher #define ixPSX81_PHY0_TX_DEEMPH_BROADCAST 0x121ff02 34523e5343bdSAlex Deucher #define ixPSX81_PHY0_TX_DEEMPH_LANE0 0x1212002 34533e5343bdSAlex Deucher #define ixPSX81_PHY0_TX_DEEMPH_LANE1 0x1212102 34543e5343bdSAlex Deucher #define ixPSX81_PHY0_TX_DEEMPH_LANE2 0x1212202 34553e5343bdSAlex Deucher #define ixPSX81_PHY0_TX_DEEMPH_LANE3 0x1212302 34563e5343bdSAlex Deucher #define ixPSX81_PHY0_TX_DEEMPH_LANE4 0x1212402 34573e5343bdSAlex Deucher #define ixPSX81_PHY0_TX_DEEMPH_LANE5 0x1212502 34583e5343bdSAlex Deucher #define ixPSX81_PHY0_TX_DEEMPH_LANE6 0x1212602 34593e5343bdSAlex Deucher #define ixPSX81_PHY0_TX_DEEMPH_LANE7 0x1212702 34603e5343bdSAlex Deucher #define ixPSX81_PHY0_TX_TSTMARGDEEMPH_BROADCAST 0x121ff03 34613e5343bdSAlex Deucher #define ixPSX81_PHY0_TX_TSTMARGDEEMPH_LANE0 0x1212003 34623e5343bdSAlex Deucher #define ixPSX81_PHY0_TX_TSTMARGDEEMPH_LANE1 0x1212103 34633e5343bdSAlex Deucher #define ixPSX81_PHY0_TX_TSTMARGDEEMPH_LANE2 0x1212203 34643e5343bdSAlex Deucher #define ixPSX81_PHY0_TX_TSTMARGDEEMPH_LANE3 0x1212303 34653e5343bdSAlex Deucher #define ixPSX81_PHY0_TX_TSTMARGDEEMPH_LANE4 0x1212403 34663e5343bdSAlex Deucher #define ixPSX81_PHY0_TX_TSTMARGDEEMPH_LANE5 0x1212503 34673e5343bdSAlex Deucher #define ixPSX81_PHY0_TX_TSTMARGDEEMPH_LANE6 0x1212603 34683e5343bdSAlex Deucher #define ixPSX81_PHY0_TX_TSTMARGDEEMPH_LANE7 0x1212703 34693e5343bdSAlex Deucher #define ixPSX81_PHY0_TX_MARGDEEMPHSTATUS_BROADCAST 0x121ff04 34703e5343bdSAlex Deucher #define ixPSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE0 0x1212004 34713e5343bdSAlex Deucher #define ixPSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE1 0x1212104 34723e5343bdSAlex Deucher #define ixPSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE2 0x1212204 34733e5343bdSAlex Deucher #define ixPSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE3 0x1212304 34743e5343bdSAlex Deucher #define ixPSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE4 0x1212404 34753e5343bdSAlex Deucher #define ixPSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE5 0x1212504 34763e5343bdSAlex Deucher #define ixPSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE6 0x1212604 34773e5343bdSAlex Deucher #define ixPSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE7 0x1212704 34783e5343bdSAlex Deucher #define ixPSX81_PHY0_TX_TXCNTRL_BROADCAST 0x121ff06 34793e5343bdSAlex Deucher #define ixPSX81_PHY0_TX_TXCNTRL_LANE0 0x1212006 34803e5343bdSAlex Deucher #define ixPSX81_PHY0_TX_TXCNTRL_LANE1 0x1212106 34813e5343bdSAlex Deucher #define ixPSX81_PHY0_TX_TXCNTRL_LANE2 0x1212206 34823e5343bdSAlex Deucher #define ixPSX81_PHY0_TX_TXCNTRL_LANE3 0x1212306 34833e5343bdSAlex Deucher #define ixPSX81_PHY0_TX_TXCNTRL_LANE4 0x1212406 34843e5343bdSAlex Deucher #define ixPSX81_PHY0_TX_TXCNTRL_LANE5 0x1212506 34853e5343bdSAlex Deucher #define ixPSX81_PHY0_TX_TXCNTRL_LANE6 0x1212606 34863e5343bdSAlex Deucher #define ixPSX81_PHY0_TX_TXCNTRL_LANE7 0x1212706 34873e5343bdSAlex Deucher #define ixPSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_BROADCAST 0x121ff07 34883e5343bdSAlex Deucher #define ixPSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE0 0x1212007 34893e5343bdSAlex Deucher #define ixPSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE1 0x1212107 34903e5343bdSAlex Deucher #define ixPSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE2 0x1212207 34913e5343bdSAlex Deucher #define ixPSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE3 0x1212307 34923e5343bdSAlex Deucher #define ixPSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE4 0x1212407 34933e5343bdSAlex Deucher #define ixPSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE5 0x1212507 34943e5343bdSAlex Deucher #define ixPSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE6 0x1212607 34953e5343bdSAlex Deucher #define ixPSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE7 0x1212707 34963e5343bdSAlex Deucher #define ixPSX81_PHY0_HTPLL_ROPLL_PowerDownEn 0x1214180 34973e5343bdSAlex Deucher #define ixPSX81_PHY0_HTPLL_ROPLL_PciPllControlExt 0x1214101 34983e5343bdSAlex Deucher #define ixPSX81_PHY0_HTPLL_ROPLL_PciPllControl 0x1214102 34993e5343bdSAlex Deucher #define ixPSX81_PHY0_HTPLL_ROPLL_PciPllTestDebug1 0x1214103 35003e5343bdSAlex Deucher #define ixPSX81_PHY0_HTPLL_ROPLL_PciPllTestDebug2 0x1214104 35013e5343bdSAlex Deucher #define ixPSX81_PHY0_HTPLL_ROPLL_PciPllFreqMode 0x1214105 35023e5343bdSAlex Deucher #define ixPSX81_PHY0_HTPLL_ROPLL_PciPllUpdateCtrl 0x1214108 35033e5343bdSAlex Deucher #define ixPSX81_PHY0_HTPLL_ROPLL_PciPllTestDebug3 0x1214109 35043e5343bdSAlex Deucher #define ixPSX81_PHY0_HTPLL_ROPLL_PciFuseProcess 0x121410a 35053e5343bdSAlex Deucher #define ixPSX81_PHY0_HTPLL_ROPLL_PciPllTestDebug4 0x121410b 35063e5343bdSAlex Deucher #define ixPSX81_PHY0_HTPLL_ROPLL_PciPllTestDebug5 0x121410c 35073e5343bdSAlex Deucher #define ixPSX81_PHY0_LCPLL_LCPLL_PowerDownEn 0x1214080 35083e5343bdSAlex Deucher #define ixPSX81_PHY0_LCPLL_LCPLL_PciPllControlExt 0x1214001 35093e5343bdSAlex Deucher #define ixPSX81_PHY0_LCPLL_LCPLL_PciPllControl 0x1214002 35103e5343bdSAlex Deucher #define ixPSX81_PHY0_LCPLL_LCPLL_PciPllTestDebug1 0x1214003 35113e5343bdSAlex Deucher #define ixPSX81_PHY0_LCPLL_LCPLL_PciPllTestDebug2 0x1214004 35123e5343bdSAlex Deucher #define ixPSX81_PHY0_LCPLL_LCPLL_PciPllFreqMode 0x1214005 35133e5343bdSAlex Deucher #define ixPSX81_PHY0_LCPLL_LCPLL_PciLcVcoCtrl 0x1214007 35143e5343bdSAlex Deucher #define ixPSX81_PHY0_LCPLL_LCPLL_PciPllUpdateCtrl 0x1214008 35153e5343bdSAlex Deucher #define ixPSX81_PHY0_LCPLL_LCPLL_PciPllTestDebug3 0x1214009 35163e5343bdSAlex Deucher #define ixPSX81_PHY0_LCPLL_LCPLL_PciPllTestDebug4 0x121400b 35173e5343bdSAlex Deucher #define ixPSX81_PHY0_LCPLL_LCPLL_PciPllTestDebug5 0x121400c 35183e5343bdSAlex Deucher #define ixPSX80_PIF0_SCRATCH 0x1100001 35193e5343bdSAlex Deucher #define ixPSX80_PIF0_HW_DEBUG 0x1100002 35203e5343bdSAlex Deucher #define ixPSX80_PIF0_STRAP_0 0x1100003 35213e5343bdSAlex Deucher #define ixPSX80_PIF0_CTRL 0x1100004 35223e5343bdSAlex Deucher #define ixPSX80_PIF0_TX_CTRL 0x1100008 35233e5343bdSAlex Deucher #define ixPSX80_PIF0_TX_CTRL2 0x1100009 35243e5343bdSAlex Deucher #define ixPSX80_PIF0_RX_CTRL 0x110000a 35253e5343bdSAlex Deucher #define ixPSX80_PIF0_RX_CTRL2 0x110000b 35263e5343bdSAlex Deucher #define ixPSX80_PIF0_GLB_OVRD 0x110000c 35273e5343bdSAlex Deucher #define ixPSX80_PIF0_GLB_OVRD2 0x110000d 35283e5343bdSAlex Deucher #define ixPSX80_PIF0_BIF_CMD_STATUS 0x1100010 35293e5343bdSAlex Deucher #define ixPSX80_PIF0_CMD_BUS_CTRL 0x1100011 35303e5343bdSAlex Deucher #define ixPSX80_PIF0_CMD_BUS_GLB_OVRD 0x1100013 35313e5343bdSAlex Deucher #define ixPSX80_PIF0_LANE0_OVRD 0x1100014 35323e5343bdSAlex Deucher #define ixPSX80_PIF0_LANE0_OVRD2 0x1100015 35333e5343bdSAlex Deucher #define ixPSX80_PIF0_LANE1_OVRD 0x1100016 35343e5343bdSAlex Deucher #define ixPSX80_PIF0_LANE1_OVRD2 0x1100017 35353e5343bdSAlex Deucher #define ixPSX80_PIF0_LANE2_OVRD 0x1100018 35363e5343bdSAlex Deucher #define ixPSX80_PIF0_LANE2_OVRD2 0x1100019 35373e5343bdSAlex Deucher #define ixPSX80_PIF0_LANE3_OVRD 0x110001a 35383e5343bdSAlex Deucher #define ixPSX80_PIF0_LANE3_OVRD2 0x110001b 35393e5343bdSAlex Deucher #define ixPSX80_PIF0_LANE4_OVRD 0x110001c 35403e5343bdSAlex Deucher #define ixPSX80_PIF0_LANE4_OVRD2 0x110001d 35413e5343bdSAlex Deucher #define ixPSX80_PIF0_LANE5_OVRD 0x110001e 35423e5343bdSAlex Deucher #define ixPSX80_PIF0_LANE5_OVRD2 0x110001f 35433e5343bdSAlex Deucher #define ixPSX80_PIF0_LANE6_OVRD 0x1100020 35443e5343bdSAlex Deucher #define ixPSX80_PIF0_LANE6_OVRD2 0x1100021 35453e5343bdSAlex Deucher #define ixPSX80_PIF0_LANE7_OVRD 0x1100022 35463e5343bdSAlex Deucher #define ixPSX80_PIF0_LANE7_OVRD2 0x1100023 35473e5343bdSAlex Deucher #define ixPSX81_PIF0_SCRATCH 0x1110001 35483e5343bdSAlex Deucher #define ixPSX81_PIF0_HW_DEBUG 0x1110002 35493e5343bdSAlex Deucher #define ixPSX81_PIF0_STRAP_0 0x1110003 35503e5343bdSAlex Deucher #define ixPSX81_PIF0_CTRL 0x1110004 35513e5343bdSAlex Deucher #define ixPSX81_PIF0_TX_CTRL 0x1110008 35523e5343bdSAlex Deucher #define ixPSX81_PIF0_TX_CTRL2 0x1110009 35533e5343bdSAlex Deucher #define ixPSX81_PIF0_RX_CTRL 0x111000a 35543e5343bdSAlex Deucher #define ixPSX81_PIF0_RX_CTRL2 0x111000b 35553e5343bdSAlex Deucher #define ixPSX81_PIF0_GLB_OVRD 0x111000c 35563e5343bdSAlex Deucher #define ixPSX81_PIF0_GLB_OVRD2 0x111000d 35573e5343bdSAlex Deucher #define ixPSX81_PIF0_BIF_CMD_STATUS 0x1110010 35583e5343bdSAlex Deucher #define ixPSX81_PIF0_CMD_BUS_CTRL 0x1110011 35593e5343bdSAlex Deucher #define ixPSX81_PIF0_CMD_BUS_GLB_OVRD 0x1110013 35603e5343bdSAlex Deucher #define ixPSX81_PIF0_LANE0_OVRD 0x1110014 35613e5343bdSAlex Deucher #define ixPSX81_PIF0_LANE0_OVRD2 0x1110015 35623e5343bdSAlex Deucher #define ixPSX81_PIF0_LANE1_OVRD 0x1110016 35633e5343bdSAlex Deucher #define ixPSX81_PIF0_LANE1_OVRD2 0x1110017 35643e5343bdSAlex Deucher #define ixPSX81_PIF0_LANE2_OVRD 0x1110018 35653e5343bdSAlex Deucher #define ixPSX81_PIF0_LANE2_OVRD2 0x1110019 35663e5343bdSAlex Deucher #define ixPSX81_PIF0_LANE3_OVRD 0x111001a 35673e5343bdSAlex Deucher #define ixPSX81_PIF0_LANE3_OVRD2 0x111001b 35683e5343bdSAlex Deucher #define ixPSX81_PIF0_LANE4_OVRD 0x111001c 35693e5343bdSAlex Deucher #define ixPSX81_PIF0_LANE4_OVRD2 0x111001d 35703e5343bdSAlex Deucher #define ixPSX81_PIF0_LANE5_OVRD 0x111001e 35713e5343bdSAlex Deucher #define ixPSX81_PIF0_LANE5_OVRD2 0x111001f 35723e5343bdSAlex Deucher #define ixPSX81_PIF0_LANE6_OVRD 0x1110020 35733e5343bdSAlex Deucher #define ixPSX81_PIF0_LANE6_OVRD2 0x1110021 35743e5343bdSAlex Deucher #define ixPSX81_PIF0_LANE7_OVRD 0x1110022 35753e5343bdSAlex Deucher #define ixPSX81_PIF0_LANE7_OVRD2 0x1110023 35763e5343bdSAlex Deucher 35773e5343bdSAlex Deucher #endif /* BIF_5_1_D_H */ 3578