1054e4c60SAlex Deucher /* 2054e4c60SAlex Deucher * BIF_4_1 Register documentation 3054e4c60SAlex Deucher * 4054e4c60SAlex Deucher * Copyright (C) 2014 Advanced Micro Devices, Inc. 5054e4c60SAlex Deucher * 6054e4c60SAlex Deucher * Permission is hereby granted, free of charge, to any person obtaining a 7054e4c60SAlex Deucher * copy of this software and associated documentation files (the "Software"), 8054e4c60SAlex Deucher * to deal in the Software without restriction, including without limitation 9054e4c60SAlex Deucher * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10054e4c60SAlex Deucher * and/or sell copies of the Software, and to permit persons to whom the 11054e4c60SAlex Deucher * Software is furnished to do so, subject to the following conditions: 12054e4c60SAlex Deucher * 13054e4c60SAlex Deucher * The above copyright notice and this permission notice shall be included 14054e4c60SAlex Deucher * in all copies or substantial portions of the Software. 15054e4c60SAlex Deucher * 16054e4c60SAlex Deucher * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 17054e4c60SAlex Deucher * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18054e4c60SAlex Deucher * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19054e4c60SAlex Deucher * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN 20054e4c60SAlex Deucher * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 21054e4c60SAlex Deucher * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 22054e4c60SAlex Deucher */ 23054e4c60SAlex Deucher 24054e4c60SAlex Deucher #ifndef BIF_4_1_D_H 25054e4c60SAlex Deucher #define BIF_4_1_D_H 26054e4c60SAlex Deucher 27054e4c60SAlex Deucher #define mmMM_INDEX 0x0 28054e4c60SAlex Deucher #define mmMM_INDEX_HI 0x6 29054e4c60SAlex Deucher #define mmMM_DATA 0x1 30054e4c60SAlex Deucher #define mmBUS_CNTL 0x1508 31054e4c60SAlex Deucher #define mmCONFIG_CNTL 0x1509 32054e4c60SAlex Deucher #define mmCONFIG_MEMSIZE 0x150a 33054e4c60SAlex Deucher #define mmCONFIG_F0_BASE 0x150b 34054e4c60SAlex Deucher #define mmCONFIG_APER_SIZE 0x150c 35054e4c60SAlex Deucher #define mmCONFIG_REG_APER_SIZE 0x150d 36054e4c60SAlex Deucher #define mmBIF_SCRATCH0 0x150e 37054e4c60SAlex Deucher #define mmBIF_SCRATCH1 0x150f 38054e4c60SAlex Deucher #define mmBX_RESET_EN 0x1514 39054e4c60SAlex Deucher #define mmMM_CFGREGS_CNTL 0x1513 40054e4c60SAlex Deucher #define mmHW_DEBUG 0x1515 41054e4c60SAlex Deucher #define mmMASTER_CREDIT_CNTL 0x1516 42054e4c60SAlex Deucher #define mmSLAVE_REQ_CREDIT_CNTL 0x1517 43054e4c60SAlex Deucher #define mmBX_RESET_CNTL 0x1518 44054e4c60SAlex Deucher #define mmINTERRUPT_CNTL 0x151a 45054e4c60SAlex Deucher #define mmINTERRUPT_CNTL2 0x151b 46054e4c60SAlex Deucher #define mmBIF_DEBUG_CNTL 0x151c 47054e4c60SAlex Deucher #define mmBIF_DEBUG_MUX 0x151d 48054e4c60SAlex Deucher #define mmBIF_DEBUG_OUT 0x151e 49054e4c60SAlex Deucher #define mmHDP_REG_COHERENCY_FLUSH_CNTL 0x1528 50054e4c60SAlex Deucher #define mmHDP_MEM_COHERENCY_FLUSH_CNTL 0x1520 51054e4c60SAlex Deucher #define mmCLKREQB_PAD_CNTL 0x1521 52054e4c60SAlex Deucher #define mmSMBUS_SLV_CNTL 0x14fd 53054e4c60SAlex Deucher #define mmSMBUS_SLV_CNTL1 0x14fe 54054e4c60SAlex Deucher #define mmSMBDAT_PAD_CNTL 0x1522 55054e4c60SAlex Deucher #define mmSMBCLK_PAD_CNTL 0x1523 56054e4c60SAlex Deucher #define mmBIF_XDMA_LO 0x14c0 57054e4c60SAlex Deucher #define mmBIF_XDMA_HI 0x14c1 58054e4c60SAlex Deucher #define mmBIF_FEATURES_CONTROL_MISC 0x14c2 59054e4c60SAlex Deucher #define mmBIF_DOORBELL_CNTL 0x14c3 60054e4c60SAlex Deucher #define mmBIF_SLVARB_MODE 0x14c4 61054e4c60SAlex Deucher #define mmBIF_FB_EN 0x1524 62054e4c60SAlex Deucher #define mmBIF_BUSNUM_CNTL1 0x1525 63054e4c60SAlex Deucher #define mmBIF_BUSNUM_LIST0 0x1526 64054e4c60SAlex Deucher #define mmBIF_BUSNUM_LIST1 0x1527 65054e4c60SAlex Deucher #define mmBIF_BUSNUM_CNTL2 0x152b 66054e4c60SAlex Deucher #define mmBIF_BUSY_DELAY_CNTR 0x1529 67054e4c60SAlex Deucher #define mmBIF_PERFMON_CNTL 0x152c 68054e4c60SAlex Deucher #define mmBIF_PERFCOUNTER0_RESULT 0x152d 69054e4c60SAlex Deucher #define mmBIF_PERFCOUNTER1_RESULT 0x152e 70054e4c60SAlex Deucher #define mmSLAVE_HANG_PROTECTION_CNTL 0x1536 71054e4c60SAlex Deucher #define mmGPU_HDP_FLUSH_REQ 0x1537 72054e4c60SAlex Deucher #define mmGPU_HDP_FLUSH_DONE 0x1538 73054e4c60SAlex Deucher #define mmSLAVE_HANG_ERROR 0x153b 74054e4c60SAlex Deucher #define mmCAPTURE_HOST_BUSNUM 0x153c 75054e4c60SAlex Deucher #define mmHOST_BUSNUM 0x153d 76054e4c60SAlex Deucher #define mmPEER_REG_RANGE0 0x153e 77054e4c60SAlex Deucher #define mmPEER_REG_RANGE1 0x153f 78054e4c60SAlex Deucher #define mmPEER0_FB_OFFSET_HI 0x14f3 79054e4c60SAlex Deucher #define mmPEER0_FB_OFFSET_LO 0x14f2 80054e4c60SAlex Deucher #define mmPEER1_FB_OFFSET_HI 0x14f1 81054e4c60SAlex Deucher #define mmPEER1_FB_OFFSET_LO 0x14f0 82054e4c60SAlex Deucher #define mmPEER2_FB_OFFSET_HI 0x14ef 83054e4c60SAlex Deucher #define mmPEER2_FB_OFFSET_LO 0x14ee 84054e4c60SAlex Deucher #define mmPEER3_FB_OFFSET_HI 0x14ed 85054e4c60SAlex Deucher #define mmPEER3_FB_OFFSET_LO 0x14ec 86054e4c60SAlex Deucher #define mmDBG_BYPASS_SRBM_ACCESS 0x14eb 87054e4c60SAlex Deucher #define mmSMBUS_BACO_DUMMY 0x14c6 88054e4c60SAlex Deucher #define mmBIF_DEVFUNCNUM_LIST0 0x14e8 89054e4c60SAlex Deucher #define mmBIF_DEVFUNCNUM_LIST1 0x14e7 90054e4c60SAlex Deucher #define mmBACO_CNTL 0x14e5 91054e4c60SAlex Deucher #define mmBF_ANA_ISO_CNTL 0x14c7 92054e4c60SAlex Deucher #define mmMEM_TYPE_CNTL 0x14e4 93054e4c60SAlex Deucher #define mmBIF_BACO_DEBUG 0x14df 94054e4c60SAlex Deucher #define mmBIF_BACO_DEBUG_LATCH 0x14dc 95054e4c60SAlex Deucher #define mmBACO_CNTL_MISC 0x14db 96054e4c60SAlex Deucher #define mmBIF_SSA_PWR_STATUS 0x14c8 97054e4c60SAlex Deucher #define mmBIF_SSA_GFX0_LOWER 0x14ca 98054e4c60SAlex Deucher #define mmBIF_SSA_GFX0_UPPER 0x14cb 99054e4c60SAlex Deucher #define mmBIF_SSA_GFX1_LOWER 0x14cc 100054e4c60SAlex Deucher #define mmBIF_SSA_GFX1_UPPER 0x14cd 101054e4c60SAlex Deucher #define mmBIF_SSA_GFX2_LOWER 0x14ce 102054e4c60SAlex Deucher #define mmBIF_SSA_GFX2_UPPER 0x14cf 103054e4c60SAlex Deucher #define mmBIF_SSA_GFX3_LOWER 0x14d0 104054e4c60SAlex Deucher #define mmBIF_SSA_GFX3_UPPER 0x14d1 105054e4c60SAlex Deucher #define mmBIF_SSA_DISP_LOWER 0x14d2 106054e4c60SAlex Deucher #define mmBIF_SSA_DISP_UPPER 0x14d3 107054e4c60SAlex Deucher #define mmBIF_SSA_MC_LOWER 0x14d4 108054e4c60SAlex Deucher #define mmBIF_SSA_MC_UPPER 0x14d5 109054e4c60SAlex Deucher #define mmIMPCTL_RESET 0x14f5 110054e4c60SAlex Deucher #define mmGARLIC_FLUSH_CNTL 0x1401 111054e4c60SAlex Deucher #define mmGARLIC_FLUSH_ADDR_START_0 0x1402 112054e4c60SAlex Deucher #define mmGARLIC_FLUSH_ADDR_START_1 0x1404 113054e4c60SAlex Deucher #define mmGARLIC_FLUSH_ADDR_START_2 0x1406 114054e4c60SAlex Deucher #define mmGARLIC_FLUSH_ADDR_START_3 0x1408 115054e4c60SAlex Deucher #define mmGARLIC_FLUSH_ADDR_START_4 0x140a 116054e4c60SAlex Deucher #define mmGARLIC_FLUSH_ADDR_START_5 0x140c 117054e4c60SAlex Deucher #define mmGARLIC_FLUSH_ADDR_START_6 0x140e 118054e4c60SAlex Deucher #define mmGARLIC_FLUSH_ADDR_START_7 0x1410 119054e4c60SAlex Deucher #define mmGARLIC_FLUSH_ADDR_END_0 0x1403 120054e4c60SAlex Deucher #define mmGARLIC_FLUSH_ADDR_END_1 0x1405 121054e4c60SAlex Deucher #define mmGARLIC_FLUSH_ADDR_END_2 0x1407 122054e4c60SAlex Deucher #define mmGARLIC_FLUSH_ADDR_END_3 0x1409 123054e4c60SAlex Deucher #define mmGARLIC_FLUSH_ADDR_END_4 0x140b 124054e4c60SAlex Deucher #define mmGARLIC_FLUSH_ADDR_END_5 0x140d 125054e4c60SAlex Deucher #define mmGARLIC_FLUSH_ADDR_END_6 0x140f 126054e4c60SAlex Deucher #define mmGARLIC_FLUSH_ADDR_END_7 0x1411 127054e4c60SAlex Deucher #define mmGARLIC_FLUSH_REQ 0x1412 128054e4c60SAlex Deucher #define mmGPU_GARLIC_FLUSH_REQ 0x1413 129054e4c60SAlex Deucher #define mmGPU_GARLIC_FLUSH_DONE 0x1414 130054e4c60SAlex Deucher #define mmGARLIC_COHE_CP_RB0_WPTR 0x1415 131054e4c60SAlex Deucher #define mmGARLIC_COHE_CP_RB1_WPTR 0x1416 132054e4c60SAlex Deucher #define mmGARLIC_COHE_CP_RB2_WPTR 0x1417 133054e4c60SAlex Deucher #define mmGARLIC_COHE_UVD_RBC_RB_WPTR 0x1418 134054e4c60SAlex Deucher #define mmGARLIC_COHE_SDMA0_GFX_RB_WPTR 0x1419 135054e4c60SAlex Deucher #define mmGARLIC_COHE_SDMA1_GFX_RB_WPTR 0x141a 136054e4c60SAlex Deucher #define mmGARLIC_COHE_CP_DMA_ME_COMMAND 0x141b 137054e4c60SAlex Deucher #define mmGARLIC_COHE_CP_DMA_PFP_COMMAND 0x141c 138054e4c60SAlex Deucher #define mmGARLIC_COHE_SAM_SAB_RBI_WPTR 0x141d 139054e4c60SAlex Deucher #define mmGARLIC_COHE_SAM_SAB_RBO_WPTR 0x141e 140054e4c60SAlex Deucher #define mmGARLIC_COHE_VCE_OUT_RB_WPTR 0x141f 141054e4c60SAlex Deucher #define mmGARLIC_COHE_VCE_RB_WPTR2 0x1420 142054e4c60SAlex Deucher #define mmGARLIC_COHE_VCE_RB_WPTR 0x1421 143054e4c60SAlex Deucher #define mmBIOS_SCRATCH_0 0x5c9 144054e4c60SAlex Deucher #define mmBIOS_SCRATCH_1 0x5ca 145054e4c60SAlex Deucher #define mmBIOS_SCRATCH_2 0x5cb 146054e4c60SAlex Deucher #define mmBIOS_SCRATCH_3 0x5cc 147054e4c60SAlex Deucher #define mmBIOS_SCRATCH_4 0x5cd 148054e4c60SAlex Deucher #define mmBIOS_SCRATCH_5 0x5ce 149054e4c60SAlex Deucher #define mmBIOS_SCRATCH_6 0x5cf 150054e4c60SAlex Deucher #define mmBIOS_SCRATCH_7 0x5d0 151054e4c60SAlex Deucher #define mmBIOS_SCRATCH_8 0x5d1 152054e4c60SAlex Deucher #define mmBIOS_SCRATCH_9 0x5d2 153054e4c60SAlex Deucher #define mmBIOS_SCRATCH_10 0x5d3 154054e4c60SAlex Deucher #define mmBIOS_SCRATCH_11 0x5d4 155054e4c60SAlex Deucher #define mmBIOS_SCRATCH_12 0x5d5 156054e4c60SAlex Deucher #define mmBIOS_SCRATCH_13 0x5d6 157054e4c60SAlex Deucher #define mmBIOS_SCRATCH_14 0x5d7 158054e4c60SAlex Deucher #define mmBIOS_SCRATCH_15 0x5d8 159054e4c60SAlex Deucher #define mmVENDOR_ID 0x0 160054e4c60SAlex Deucher #define mmDEVICE_ID 0x0 161054e4c60SAlex Deucher #define mmCOMMAND 0x1 162054e4c60SAlex Deucher #define mmSTATUS 0x1 163054e4c60SAlex Deucher #define mmREVISION_ID 0x2 164054e4c60SAlex Deucher #define mmPROG_INTERFACE 0x2 165054e4c60SAlex Deucher #define mmSUB_CLASS 0x2 166054e4c60SAlex Deucher #define mmBASE_CLASS 0x2 167054e4c60SAlex Deucher #define mmCACHE_LINE 0x3 168054e4c60SAlex Deucher #define mmLATENCY 0x3 169054e4c60SAlex Deucher #define mmHEADER 0x3 170054e4c60SAlex Deucher #define mmBIST 0x3 171054e4c60SAlex Deucher #define mmBASE_ADDR_1 0x4 172054e4c60SAlex Deucher #define mmBASE_ADDR_2 0x5 173054e4c60SAlex Deucher #define mmBASE_ADDR_3 0x6 174054e4c60SAlex Deucher #define mmBASE_ADDR_4 0x7 175054e4c60SAlex Deucher #define mmBASE_ADDR_5 0x8 176054e4c60SAlex Deucher #define mmBASE_ADDR_6 0x9 177054e4c60SAlex Deucher #define mmROM_BASE_ADDR 0xc 178054e4c60SAlex Deucher #define mmCAP_PTR 0xd 179054e4c60SAlex Deucher #define mmINTERRUPT_LINE 0xf 180054e4c60SAlex Deucher #define mmINTERRUPT_PIN 0xf 181054e4c60SAlex Deucher #define mmADAPTER_ID 0xb 182054e4c60SAlex Deucher #define mmMIN_GRANT 0xf 183054e4c60SAlex Deucher #define mmMAX_LATENCY 0xf 184054e4c60SAlex Deucher #define mmVENDOR_CAP_LIST 0x12 185054e4c60SAlex Deucher #define mmADAPTER_ID_W 0x13 186054e4c60SAlex Deucher #define mmPMI_CAP_LIST 0x14 187054e4c60SAlex Deucher #define mmPMI_CAP 0x14 188054e4c60SAlex Deucher #define mmPMI_STATUS_CNTL 0x15 189054e4c60SAlex Deucher #define mmPCIE_CAP_LIST 0x16 190054e4c60SAlex Deucher #define mmPCIE_CAP 0x16 191054e4c60SAlex Deucher #define mmDEVICE_CAP 0x17 192054e4c60SAlex Deucher #define mmDEVICE_CNTL 0x18 193054e4c60SAlex Deucher #define mmDEVICE_STATUS 0x18 194054e4c60SAlex Deucher #define mmLINK_CAP 0x19 195054e4c60SAlex Deucher #define mmLINK_CNTL 0x1a 196054e4c60SAlex Deucher #define mmLINK_STATUS 0x1a 197054e4c60SAlex Deucher #define mmDEVICE_CAP2 0x1f 198054e4c60SAlex Deucher #define mmDEVICE_CNTL2 0x20 199054e4c60SAlex Deucher #define mmDEVICE_STATUS2 0x20 200054e4c60SAlex Deucher #define mmLINK_CAP2 0x21 201054e4c60SAlex Deucher #define mmLINK_CNTL2 0x22 202054e4c60SAlex Deucher #define mmLINK_STATUS2 0x22 203054e4c60SAlex Deucher #define mmMSI_CAP_LIST 0x28 204054e4c60SAlex Deucher #define mmMSI_MSG_CNTL 0x28 205054e4c60SAlex Deucher #define mmMSI_MSG_ADDR_LO 0x29 206054e4c60SAlex Deucher #define mmMSI_MSG_ADDR_HI 0x2a 207054e4c60SAlex Deucher #define mmMSI_MSG_DATA_64 0x2b 208054e4c60SAlex Deucher #define mmMSI_MSG_DATA 0x2a 209054e4c60SAlex Deucher #define mmPCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x40 210054e4c60SAlex Deucher #define mmPCIE_VENDOR_SPECIFIC_HDR 0x41 211054e4c60SAlex Deucher #define mmPCIE_VENDOR_SPECIFIC1 0x42 212054e4c60SAlex Deucher #define mmPCIE_VENDOR_SPECIFIC2 0x43 213054e4c60SAlex Deucher #define mmPCIE_VC_ENH_CAP_LIST 0x44 214054e4c60SAlex Deucher #define mmPCIE_PORT_VC_CAP_REG1 0x45 215054e4c60SAlex Deucher #define mmPCIE_PORT_VC_CAP_REG2 0x46 216054e4c60SAlex Deucher #define mmPCIE_PORT_VC_CNTL 0x47 217054e4c60SAlex Deucher #define mmPCIE_PORT_VC_STATUS 0x47 218054e4c60SAlex Deucher #define mmPCIE_VC0_RESOURCE_CAP 0x48 219054e4c60SAlex Deucher #define mmPCIE_VC0_RESOURCE_CNTL 0x49 220054e4c60SAlex Deucher #define mmPCIE_VC0_RESOURCE_STATUS 0x4a 221054e4c60SAlex Deucher #define mmPCIE_VC1_RESOURCE_CAP 0x4b 222054e4c60SAlex Deucher #define mmPCIE_VC1_RESOURCE_CNTL 0x4c 223054e4c60SAlex Deucher #define mmPCIE_VC1_RESOURCE_STATUS 0x4d 224054e4c60SAlex Deucher #define mmPCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 0x50 225054e4c60SAlex Deucher #define mmPCIE_DEV_SERIAL_NUM_DW1 0x51 226054e4c60SAlex Deucher #define mmPCIE_DEV_SERIAL_NUM_DW2 0x52 227054e4c60SAlex Deucher #define mmPCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x54 228054e4c60SAlex Deucher #define mmPCIE_UNCORR_ERR_STATUS 0x55 229054e4c60SAlex Deucher #define mmPCIE_UNCORR_ERR_MASK 0x56 230054e4c60SAlex Deucher #define mmPCIE_UNCORR_ERR_SEVERITY 0x57 231054e4c60SAlex Deucher #define mmPCIE_CORR_ERR_STATUS 0x58 232054e4c60SAlex Deucher #define mmPCIE_CORR_ERR_MASK 0x59 233054e4c60SAlex Deucher #define mmPCIE_ADV_ERR_CAP_CNTL 0x5a 234054e4c60SAlex Deucher #define mmPCIE_HDR_LOG0 0x5b 235054e4c60SAlex Deucher #define mmPCIE_HDR_LOG1 0x5c 236054e4c60SAlex Deucher #define mmPCIE_HDR_LOG2 0x5d 237054e4c60SAlex Deucher #define mmPCIE_HDR_LOG3 0x5e 238054e4c60SAlex Deucher #define mmPCIE_TLP_PREFIX_LOG0 0x62 239054e4c60SAlex Deucher #define mmPCIE_TLP_PREFIX_LOG1 0x63 240054e4c60SAlex Deucher #define mmPCIE_TLP_PREFIX_LOG2 0x64 241054e4c60SAlex Deucher #define mmPCIE_TLP_PREFIX_LOG3 0x65 242054e4c60SAlex Deucher #define mmPCIE_BAR_ENH_CAP_LIST 0x80 243054e4c60SAlex Deucher #define mmPCIE_BAR1_CAP 0x81 244054e4c60SAlex Deucher #define mmPCIE_BAR1_CNTL 0x82 245054e4c60SAlex Deucher #define mmPCIE_BAR2_CAP 0x83 246054e4c60SAlex Deucher #define mmPCIE_BAR2_CNTL 0x84 247054e4c60SAlex Deucher #define mmPCIE_BAR3_CAP 0x85 248054e4c60SAlex Deucher #define mmPCIE_BAR3_CNTL 0x86 249054e4c60SAlex Deucher #define mmPCIE_BAR4_CAP 0x87 250054e4c60SAlex Deucher #define mmPCIE_BAR4_CNTL 0x88 251054e4c60SAlex Deucher #define mmPCIE_BAR5_CAP 0x89 252054e4c60SAlex Deucher #define mmPCIE_BAR5_CNTL 0x8a 253054e4c60SAlex Deucher #define mmPCIE_BAR6_CAP 0x8b 254054e4c60SAlex Deucher #define mmPCIE_BAR6_CNTL 0x8c 255054e4c60SAlex Deucher #define mmPCIE_PWR_BUDGET_ENH_CAP_LIST 0x90 256054e4c60SAlex Deucher #define mmPCIE_PWR_BUDGET_DATA_SELECT 0x91 257054e4c60SAlex Deucher #define mmPCIE_PWR_BUDGET_DATA 0x92 258054e4c60SAlex Deucher #define mmPCIE_PWR_BUDGET_CAP 0x93 259054e4c60SAlex Deucher #define mmPCIE_DPA_ENH_CAP_LIST 0x94 260054e4c60SAlex Deucher #define mmPCIE_DPA_CAP 0x95 261054e4c60SAlex Deucher #define mmPCIE_DPA_LATENCY_INDICATOR 0x96 262054e4c60SAlex Deucher #define mmPCIE_DPA_STATUS 0x97 263054e4c60SAlex Deucher #define mmPCIE_DPA_CNTL 0x97 264054e4c60SAlex Deucher #define mmPCIE_DPA_SUBSTATE_PWR_ALLOC_0 0x98 265054e4c60SAlex Deucher #define mmPCIE_DPA_SUBSTATE_PWR_ALLOC_1 0x98 266054e4c60SAlex Deucher #define mmPCIE_DPA_SUBSTATE_PWR_ALLOC_2 0x98 267054e4c60SAlex Deucher #define mmPCIE_DPA_SUBSTATE_PWR_ALLOC_3 0x98 268054e4c60SAlex Deucher #define mmPCIE_DPA_SUBSTATE_PWR_ALLOC_4 0x99 269054e4c60SAlex Deucher #define mmPCIE_DPA_SUBSTATE_PWR_ALLOC_5 0x99 270054e4c60SAlex Deucher #define mmPCIE_DPA_SUBSTATE_PWR_ALLOC_6 0x99 271054e4c60SAlex Deucher #define mmPCIE_DPA_SUBSTATE_PWR_ALLOC_7 0x99 272054e4c60SAlex Deucher #define mmPCIE_SECONDARY_ENH_CAP_LIST 0x9c 273054e4c60SAlex Deucher #define mmPCIE_LINK_CNTL3 0x9d 274054e4c60SAlex Deucher #define mmPCIE_LANE_ERROR_STATUS 0x9e 275054e4c60SAlex Deucher #define mmPCIE_LANE_0_EQUALIZATION_CNTL 0x9f 276054e4c60SAlex Deucher #define mmPCIE_LANE_1_EQUALIZATION_CNTL 0x9f 277054e4c60SAlex Deucher #define mmPCIE_LANE_2_EQUALIZATION_CNTL 0xa0 278054e4c60SAlex Deucher #define mmPCIE_LANE_3_EQUALIZATION_CNTL 0xa0 279054e4c60SAlex Deucher #define mmPCIE_LANE_4_EQUALIZATION_CNTL 0xa1 280054e4c60SAlex Deucher #define mmPCIE_LANE_5_EQUALIZATION_CNTL 0xa1 281054e4c60SAlex Deucher #define mmPCIE_LANE_6_EQUALIZATION_CNTL 0xa2 282054e4c60SAlex Deucher #define mmPCIE_LANE_7_EQUALIZATION_CNTL 0xa2 283054e4c60SAlex Deucher #define mmPCIE_LANE_8_EQUALIZATION_CNTL 0xa3 284054e4c60SAlex Deucher #define mmPCIE_LANE_9_EQUALIZATION_CNTL 0xa3 285054e4c60SAlex Deucher #define mmPCIE_LANE_10_EQUALIZATION_CNTL 0xa4 286054e4c60SAlex Deucher #define mmPCIE_LANE_11_EQUALIZATION_CNTL 0xa4 287054e4c60SAlex Deucher #define mmPCIE_LANE_12_EQUALIZATION_CNTL 0xa5 288054e4c60SAlex Deucher #define mmPCIE_LANE_13_EQUALIZATION_CNTL 0xa5 289054e4c60SAlex Deucher #define mmPCIE_LANE_14_EQUALIZATION_CNTL 0xa6 290054e4c60SAlex Deucher #define mmPCIE_LANE_15_EQUALIZATION_CNTL 0xa6 291054e4c60SAlex Deucher #define mmPCIE_ACS_ENH_CAP_LIST 0xa8 292054e4c60SAlex Deucher #define mmPCIE_ACS_CAP 0xa9 293054e4c60SAlex Deucher #define mmPCIE_ACS_CNTL 0xa9 294054e4c60SAlex Deucher #define mmPCIE_ATS_ENH_CAP_LIST 0xac 295054e4c60SAlex Deucher #define mmPCIE_ATS_CAP 0xad 296054e4c60SAlex Deucher #define mmPCIE_ATS_CNTL 0xad 297054e4c60SAlex Deucher #define mmPCIE_PAGE_REQ_ENH_CAP_LIST 0xb0 298054e4c60SAlex Deucher #define mmPCIE_PAGE_REQ_CNTL 0xb1 299054e4c60SAlex Deucher #define mmPCIE_PAGE_REQ_STATUS 0xb1 300054e4c60SAlex Deucher #define mmPCIE_OUTSTAND_PAGE_REQ_CAPACITY 0xb2 301054e4c60SAlex Deucher #define mmPCIE_OUTSTAND_PAGE_REQ_ALLOC 0xb3 302054e4c60SAlex Deucher #define mmPCIE_PASID_ENH_CAP_LIST 0xb4 303054e4c60SAlex Deucher #define mmPCIE_PASID_CAP 0xb5 304054e4c60SAlex Deucher #define mmPCIE_PASID_CNTL 0xb5 305054e4c60SAlex Deucher #define mmPCIE_TPH_REQR_ENH_CAP_LIST 0xb8 306054e4c60SAlex Deucher #define mmPCIE_TPH_REQR_CAP 0xb9 307054e4c60SAlex Deucher #define mmPCIE_TPH_REQR_CNTL 0xba 308054e4c60SAlex Deucher #define mmPCIE_MC_ENH_CAP_LIST 0xbc 309054e4c60SAlex Deucher #define mmPCIE_MC_CAP 0xbd 310054e4c60SAlex Deucher #define mmPCIE_MC_CNTL 0xbd 311054e4c60SAlex Deucher #define mmPCIE_MC_ADDR0 0xbe 312054e4c60SAlex Deucher #define mmPCIE_MC_ADDR1 0xbf 313054e4c60SAlex Deucher #define mmPCIE_MC_RCV0 0xc0 314054e4c60SAlex Deucher #define mmPCIE_MC_RCV1 0xc1 315054e4c60SAlex Deucher #define mmPCIE_MC_BLOCK_ALL0 0xc2 316054e4c60SAlex Deucher #define mmPCIE_MC_BLOCK_ALL1 0xc3 317054e4c60SAlex Deucher #define mmPCIE_MC_BLOCK_UNTRANSLATED_0 0xc4 318054e4c60SAlex Deucher #define mmPCIE_MC_BLOCK_UNTRANSLATED_1 0xc5 319054e4c60SAlex Deucher #define mmPCIE_LTR_ENH_CAP_LIST 0xc8 320054e4c60SAlex Deucher #define mmPCIE_LTR_CAP 0xc9 321054e4c60SAlex Deucher #define mmPCIE_INDEX 0xe 322054e4c60SAlex Deucher #define mmPCIE_DATA 0xf 323054e4c60SAlex Deucher #define mmPCIE_INDEX_2 0xc 324054e4c60SAlex Deucher #define mmPCIE_DATA_2 0xd 325054e4c60SAlex Deucher #define ixPCIE_RESERVED 0x1400000 326054e4c60SAlex Deucher #define ixPCIE_SCRATCH 0x1400001 327054e4c60SAlex Deucher #define ixPCIE_HW_DEBUG 0x1400002 328054e4c60SAlex Deucher #define ixPCIE_RX_NUM_NAK 0x140000e 329054e4c60SAlex Deucher #define ixPCIE_RX_NUM_NAK_GENERATED 0x140000f 330054e4c60SAlex Deucher #define ixPCIE_CNTL 0x1400010 331054e4c60SAlex Deucher #define ixPCIE_CONFIG_CNTL 0x1400011 332054e4c60SAlex Deucher #define ixPCIE_DEBUG_CNTL 0x1400012 333054e4c60SAlex Deucher #define ixPCIE_INT_CNTL 0x140001a 334054e4c60SAlex Deucher #define ixPCIE_INT_STATUS 0x140001b 335054e4c60SAlex Deucher #define ixPCIE_CNTL2 0x140001c 336054e4c60SAlex Deucher #define ixPCIE_RX_CNTL2 0x140001d 337054e4c60SAlex Deucher #define ixPCIE_TX_F0_ATTR_CNTL 0x140001e 338054e4c60SAlex Deucher #define ixPCIE_TX_F1_F2_ATTR_CNTL 0x140001f 339054e4c60SAlex Deucher #define ixPCIE_CI_CNTL 0x1400020 340054e4c60SAlex Deucher #define ixPCIE_BUS_CNTL 0x1400021 341054e4c60SAlex Deucher #define ixPCIE_LC_STATE6 0x1400022 342054e4c60SAlex Deucher #define ixPCIE_LC_STATE7 0x1400023 343054e4c60SAlex Deucher #define ixPCIE_LC_STATE8 0x1400024 344054e4c60SAlex Deucher #define ixPCIE_LC_STATE9 0x1400025 345054e4c60SAlex Deucher #define ixPCIE_LC_STATE10 0x1400026 346054e4c60SAlex Deucher #define ixPCIE_LC_STATE11 0x1400027 347054e4c60SAlex Deucher #define ixPCIE_LC_STATUS1 0x1400028 348054e4c60SAlex Deucher #define ixPCIE_LC_STATUS2 0x1400029 349054e4c60SAlex Deucher #define ixPCIE_WPR_CNTL 0x1400030 350054e4c60SAlex Deucher #define ixPCIE_RX_LAST_TLP0 0x1400031 351054e4c60SAlex Deucher #define ixPCIE_RX_LAST_TLP1 0x1400032 352054e4c60SAlex Deucher #define ixPCIE_RX_LAST_TLP2 0x1400033 353054e4c60SAlex Deucher #define ixPCIE_RX_LAST_TLP3 0x1400034 354054e4c60SAlex Deucher #define ixPCIE_TX_LAST_TLP0 0x1400035 355054e4c60SAlex Deucher #define ixPCIE_TX_LAST_TLP1 0x1400036 356054e4c60SAlex Deucher #define ixPCIE_TX_LAST_TLP2 0x1400037 357054e4c60SAlex Deucher #define ixPCIE_TX_LAST_TLP3 0x1400038 358054e4c60SAlex Deucher #define ixPCIE_I2C_REG_ADDR_EXPAND 0x140003a 359054e4c60SAlex Deucher #define ixPCIE_I2C_REG_DATA 0x140003b 360054e4c60SAlex Deucher #define ixPCIE_CFG_CNTL 0x140003c 361054e4c60SAlex Deucher #define ixPCIE_P_CNTL 0x1400040 362054e4c60SAlex Deucher #define ixPCIE_P_BUF_STATUS 0x1400041 363054e4c60SAlex Deucher #define ixPCIE_P_DECODER_STATUS 0x1400042 364054e4c60SAlex Deucher #define ixPCIE_P_MISC_STATUS 0x1400043 365054e4c60SAlex Deucher #define ixPCIE_P_RCV_L0S_FTS_DET 0x1400050 366054e4c60SAlex Deucher #define ixPCIE_OBFF_CNTL 0x1400061 367054e4c60SAlex Deucher #define ixPCIE_TX_LTR_CNTL 0x1400060 368054e4c60SAlex Deucher #define ixPCIE_PERF_COUNT_CNTL 0x1400080 369054e4c60SAlex Deucher #define ixPCIE_PERF_CNTL_TXCLK 0x1400081 370054e4c60SAlex Deucher #define ixPCIE_PERF_COUNT0_TXCLK 0x1400082 371054e4c60SAlex Deucher #define ixPCIE_PERF_COUNT1_TXCLK 0x1400083 372054e4c60SAlex Deucher #define ixPCIE_PERF_CNTL_MST_R_CLK 0x1400084 373054e4c60SAlex Deucher #define ixPCIE_PERF_COUNT0_MST_R_CLK 0x1400085 374054e4c60SAlex Deucher #define ixPCIE_PERF_COUNT1_MST_R_CLK 0x1400086 375054e4c60SAlex Deucher #define ixPCIE_PERF_CNTL_MST_C_CLK 0x1400087 376054e4c60SAlex Deucher #define ixPCIE_PERF_COUNT0_MST_C_CLK 0x1400088 377054e4c60SAlex Deucher #define ixPCIE_PERF_COUNT1_MST_C_CLK 0x1400089 378054e4c60SAlex Deucher #define ixPCIE_PERF_CNTL_SLV_R_CLK 0x140008a 379054e4c60SAlex Deucher #define ixPCIE_PERF_COUNT0_SLV_R_CLK 0x140008b 380054e4c60SAlex Deucher #define ixPCIE_PERF_COUNT1_SLV_R_CLK 0x140008c 381054e4c60SAlex Deucher #define ixPCIE_PERF_CNTL_SLV_S_C_CLK 0x140008d 382054e4c60SAlex Deucher #define ixPCIE_PERF_COUNT0_SLV_S_C_CLK 0x140008e 383054e4c60SAlex Deucher #define ixPCIE_PERF_COUNT1_SLV_S_C_CLK 0x140008f 384054e4c60SAlex Deucher #define ixPCIE_PERF_CNTL_SLV_NS_C_CLK 0x1400090 385054e4c60SAlex Deucher #define ixPCIE_PERF_COUNT0_SLV_NS_C_CLK 0x1400091 386054e4c60SAlex Deucher #define ixPCIE_PERF_COUNT1_SLV_NS_C_CLK 0x1400092 387054e4c60SAlex Deucher #define ixPCIE_PERF_CNTL_EVENT0_PORT_SEL 0x1400093 388054e4c60SAlex Deucher #define ixPCIE_PERF_CNTL_EVENT1_PORT_SEL 0x1400094 389054e4c60SAlex Deucher #define ixPCIE_PERF_CNTL_TXCLK2 0x1400095 390054e4c60SAlex Deucher #define ixPCIE_PERF_COUNT0_TXCLK2 0x1400096 391054e4c60SAlex Deucher #define ixPCIE_PERF_COUNT1_TXCLK2 0x1400097 392054e4c60SAlex Deucher #define ixPCIE_STRAP_F0 0x14000b0 393054e4c60SAlex Deucher #define ixPCIE_STRAP_F1 0x14000b1 394054e4c60SAlex Deucher #define ixPCIE_STRAP_F2 0x14000b2 395054e4c60SAlex Deucher #define ixPCIE_STRAP_F3 0x14000b3 396054e4c60SAlex Deucher #define ixPCIE_STRAP_F4 0x14000b4 397054e4c60SAlex Deucher #define ixPCIE_STRAP_F5 0x14000b5 398054e4c60SAlex Deucher #define ixPCIE_STRAP_F6 0x14000b6 399054e4c60SAlex Deucher #define ixPCIE_STRAP_F7 0x14000b7 400054e4c60SAlex Deucher #define ixPCIE_STRAP_MISC 0x14000c0 401054e4c60SAlex Deucher #define ixPCIE_STRAP_MISC2 0x14000c1 402054e4c60SAlex Deucher #define ixPCIE_STRAP_PI 0x14000c2 403054e4c60SAlex Deucher #define ixPCIE_STRAP_I2C_BD 0x14000c4 404054e4c60SAlex Deucher #define ixPCIE_PRBS_CLR 0x14000c8 405054e4c60SAlex Deucher #define ixPCIE_PRBS_STATUS1 0x14000c9 406054e4c60SAlex Deucher #define ixPCIE_PRBS_STATUS2 0x14000ca 407054e4c60SAlex Deucher #define ixPCIE_PRBS_FREERUN 0x14000cb 408054e4c60SAlex Deucher #define ixPCIE_PRBS_MISC 0x14000cc 409054e4c60SAlex Deucher #define ixPCIE_PRBS_USER_PATTERN 0x14000cd 410054e4c60SAlex Deucher #define ixPCIE_PRBS_LO_BITCNT 0x14000ce 411054e4c60SAlex Deucher #define ixPCIE_PRBS_HI_BITCNT 0x14000cf 412054e4c60SAlex Deucher #define ixPCIE_PRBS_ERRCNT_0 0x14000d0 413054e4c60SAlex Deucher #define ixPCIE_PRBS_ERRCNT_1 0x14000d1 414054e4c60SAlex Deucher #define ixPCIE_PRBS_ERRCNT_2 0x14000d2 415054e4c60SAlex Deucher #define ixPCIE_PRBS_ERRCNT_3 0x14000d3 416054e4c60SAlex Deucher #define ixPCIE_PRBS_ERRCNT_4 0x14000d4 417054e4c60SAlex Deucher #define ixPCIE_PRBS_ERRCNT_5 0x14000d5 418054e4c60SAlex Deucher #define ixPCIE_PRBS_ERRCNT_6 0x14000d6 419054e4c60SAlex Deucher #define ixPCIE_PRBS_ERRCNT_7 0x14000d7 420054e4c60SAlex Deucher #define ixPCIE_PRBS_ERRCNT_8 0x14000d8 421054e4c60SAlex Deucher #define ixPCIE_PRBS_ERRCNT_9 0x14000d9 422054e4c60SAlex Deucher #define ixPCIE_PRBS_ERRCNT_10 0x14000da 423054e4c60SAlex Deucher #define ixPCIE_PRBS_ERRCNT_11 0x14000db 424054e4c60SAlex Deucher #define ixPCIE_PRBS_ERRCNT_12 0x14000dc 425054e4c60SAlex Deucher #define ixPCIE_PRBS_ERRCNT_13 0x14000dd 426054e4c60SAlex Deucher #define ixPCIE_PRBS_ERRCNT_14 0x14000de 427054e4c60SAlex Deucher #define ixPCIE_PRBS_ERRCNT_15 0x14000df 428054e4c60SAlex Deucher #define ixPCIE_F0_DPA_CAP 0x14000e0 429054e4c60SAlex Deucher #define ixPCIE_F0_DPA_LATENCY_INDICATOR 0x14000e4 430054e4c60SAlex Deucher #define ixPCIE_F0_DPA_CNTL 0x14000e5 431054e4c60SAlex Deucher #define ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0 0x14000e7 432054e4c60SAlex Deucher #define ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1 0x14000e8 433054e4c60SAlex Deucher #define ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2 0x14000e9 434054e4c60SAlex Deucher #define ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3 0x14000ea 435054e4c60SAlex Deucher #define ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4 0x14000eb 436054e4c60SAlex Deucher #define ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5 0x14000ec 437054e4c60SAlex Deucher #define ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6 0x14000ed 438054e4c60SAlex Deucher #define ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7 0x14000ee 439054e4c60SAlex Deucher #define ixPCIEP_RESERVED 0x10010000 440054e4c60SAlex Deucher #define ixPCIEP_SCRATCH 0x10010001 441054e4c60SAlex Deucher #define ixPCIEP_HW_DEBUG 0x10010002 442054e4c60SAlex Deucher #define ixPCIEP_PORT_CNTL 0x10010010 443054e4c60SAlex Deucher #define ixPCIE_TX_CNTL 0x10010020 444054e4c60SAlex Deucher #define ixPCIE_TX_REQUESTER_ID 0x10010021 445054e4c60SAlex Deucher #define ixPCIE_TX_VENDOR_SPECIFIC 0x10010022 446054e4c60SAlex Deucher #define ixPCIE_TX_REQUEST_NUM_CNTL 0x10010023 447054e4c60SAlex Deucher #define ixPCIE_TX_SEQ 0x10010024 448054e4c60SAlex Deucher #define ixPCIE_TX_REPLAY 0x10010025 449054e4c60SAlex Deucher #define ixPCIE_TX_ACK_LATENCY_LIMIT 0x10010026 450054e4c60SAlex Deucher #define ixPCIE_TX_CREDITS_ADVT_P 0x10010030 451054e4c60SAlex Deucher #define ixPCIE_TX_CREDITS_ADVT_NP 0x10010031 452054e4c60SAlex Deucher #define ixPCIE_TX_CREDITS_ADVT_CPL 0x10010032 453054e4c60SAlex Deucher #define ixPCIE_TX_CREDITS_INIT_P 0x10010033 454054e4c60SAlex Deucher #define ixPCIE_TX_CREDITS_INIT_NP 0x10010034 455054e4c60SAlex Deucher #define ixPCIE_TX_CREDITS_INIT_CPL 0x10010035 456054e4c60SAlex Deucher #define ixPCIE_TX_CREDITS_STATUS 0x10010036 457054e4c60SAlex Deucher #define ixPCIE_TX_CREDITS_FCU_THRESHOLD 0x10010037 458054e4c60SAlex Deucher #define ixPCIE_P_PORT_LANE_STATUS 0x10010050 459054e4c60SAlex Deucher #define ixPCIE_FC_P 0x10010060 460054e4c60SAlex Deucher #define ixPCIE_FC_NP 0x10010061 461054e4c60SAlex Deucher #define ixPCIE_FC_CPL 0x10010062 462054e4c60SAlex Deucher #define ixPCIE_ERR_CNTL 0x1001006a 463054e4c60SAlex Deucher #define ixPCIE_RX_CNTL 0x10010070 464054e4c60SAlex Deucher #define ixPCIE_RX_EXPECTED_SEQNUM 0x10010071 465054e4c60SAlex Deucher #define ixPCIE_RX_VENDOR_SPECIFIC 0x10010072 466054e4c60SAlex Deucher #define ixPCIE_RX_CNTL3 0x10010074 467054e4c60SAlex Deucher #define ixPCIE_RX_CREDITS_ALLOCATED_P 0x10010080 468054e4c60SAlex Deucher #define ixPCIE_RX_CREDITS_ALLOCATED_NP 0x10010081 469054e4c60SAlex Deucher #define ixPCIE_RX_CREDITS_ALLOCATED_CPL 0x10010082 470054e4c60SAlex Deucher #define ixPCIE_LC_CNTL 0x100100a0 471054e4c60SAlex Deucher #define ixPCIE_LC_CNTL2 0x100100b1 472054e4c60SAlex Deucher #define ixPCIE_LC_CNTL3 0x100100b5 473054e4c60SAlex Deucher #define ixPCIE_LC_CNTL4 0x100100b6 474054e4c60SAlex Deucher #define ixPCIE_LC_CNTL5 0x100100b7 475054e4c60SAlex Deucher #define ixPCIE_LC_BW_CHANGE_CNTL 0x100100b2 476054e4c60SAlex Deucher #define ixPCIE_LC_TRAINING_CNTL 0x100100a1 477054e4c60SAlex Deucher #define ixPCIE_LC_LINK_WIDTH_CNTL 0x100100a2 478054e4c60SAlex Deucher #define ixPCIE_LC_N_FTS_CNTL 0x100100a3 479054e4c60SAlex Deucher #define ixPCIE_LC_SPEED_CNTL 0x100100a4 480054e4c60SAlex Deucher #define ixPCIE_LC_CDR_CNTL 0x100100b3 481054e4c60SAlex Deucher #define ixPCIE_LC_LANE_CNTL 0x100100b4 482054e4c60SAlex Deucher #define ixPCIE_LC_FORCE_COEFF 0x100100b8 483054e4c60SAlex Deucher #define ixPCIE_LC_BEST_EQ_SETTINGS 0x100100b9 484054e4c60SAlex Deucher #define ixPCIE_LC_FORCE_EQ_REQ_COEFF 0x100100ba 485054e4c60SAlex Deucher #define ixPCIE_LC_STATE0 0x100100a5 486054e4c60SAlex Deucher #define ixPCIE_LC_STATE1 0x100100a6 487054e4c60SAlex Deucher #define ixPCIE_LC_STATE2 0x100100a7 488054e4c60SAlex Deucher #define ixPCIE_LC_STATE3 0x100100a8 489054e4c60SAlex Deucher #define ixPCIE_LC_STATE4 0x100100a9 490054e4c60SAlex Deucher #define ixPCIE_LC_STATE5 0x100100aa 491054e4c60SAlex Deucher #define ixPCIEP_STRAP_LC 0x100100c0 492054e4c60SAlex Deucher #define ixPCIEP_STRAP_MISC 0x100100c1 493054e4c60SAlex Deucher #define ixPCIEP_BCH_ECC_CNTL 0x100100d0 494054e4c60SAlex Deucher #define ixPB0_GLB_CTRL_REG0 0x1200004 495054e4c60SAlex Deucher #define ixPB0_GLB_CTRL_REG1 0x1200008 496054e4c60SAlex Deucher #define ixPB0_GLB_CTRL_REG2 0x120000c 497054e4c60SAlex Deucher #define ixPB0_GLB_CTRL_REG3 0x1200010 498054e4c60SAlex Deucher #define ixPB0_GLB_CTRL_REG4 0x1200014 499054e4c60SAlex Deucher #define ixPB0_GLB_CTRL_REG5 0x1200018 500054e4c60SAlex Deucher #define ixPB0_GLB_SCI_STAT_OVRD_REG0 0x120001c 501054e4c60SAlex Deucher #define ixPB0_GLB_SCI_STAT_OVRD_REG1 0x1200020 502054e4c60SAlex Deucher #define ixPB0_GLB_SCI_STAT_OVRD_REG2 0x1200024 503054e4c60SAlex Deucher #define ixPB0_GLB_SCI_STAT_OVRD_REG3 0x1200028 504054e4c60SAlex Deucher #define ixPB0_GLB_SCI_STAT_OVRD_REG4 0x120002c 505054e4c60SAlex Deucher #define ixPB0_GLB_OVRD_REG0 0x1200030 506054e4c60SAlex Deucher #define ixPB0_GLB_OVRD_REG1 0x1200034 507054e4c60SAlex Deucher #define ixPB0_GLB_OVRD_REG2 0x1200038 508054e4c60SAlex Deucher #define ixPB0_HW_DEBUG 0x1202004 509054e4c60SAlex Deucher #define ixPB0_STRAP_GLB_REG0 0x1202020 510054e4c60SAlex Deucher #define ixPB0_STRAP_TX_REG0 0x1202024 511054e4c60SAlex Deucher #define ixPB0_STRAP_RX_REG0 0x1202028 512054e4c60SAlex Deucher #define ixPB0_STRAP_RX_REG1 0x120202c 513054e4c60SAlex Deucher #define ixPB0_STRAP_PLL_REG0 0x1202030 514054e4c60SAlex Deucher #define ixPB0_STRAP_PIN_REG0 0x1202034 515054e4c60SAlex Deucher #define ixPB0_DFT_JIT_INJ_REG0 0x1203000 516054e4c60SAlex Deucher #define ixPB0_DFT_JIT_INJ_REG1 0x1203004 517054e4c60SAlex Deucher #define ixPB0_DFT_JIT_INJ_REG2 0x1203008 518054e4c60SAlex Deucher #define ixPB0_DFT_DEBUG_CTRL_REG0 0x120300c 519054e4c60SAlex Deucher #define ixPB0_DFT_JIT_INJ_STAT_REG0 0x1203010 520054e4c60SAlex Deucher #define ixPB0_PLL_RO_GLB_CTRL_REG0 0x1204000 521054e4c60SAlex Deucher #define ixPB0_PLL_RO_GLB_OVRD_REG0 0x1204010 522054e4c60SAlex Deucher #define ixPB0_PLL_RO0_CTRL_REG0 0x1204440 523054e4c60SAlex Deucher #define ixPB0_PLL_RO0_OVRD_REG0 0x1204450 524054e4c60SAlex Deucher #define ixPB0_PLL_RO0_OVRD_REG1 0x1204454 525054e4c60SAlex Deucher #define ixPB0_PLL_RO0_SCI_STAT_OVRD_REG0 0x1204460 526054e4c60SAlex Deucher #define ixPB0_PLL_RO1_SCI_STAT_OVRD_REG0 0x1204464 527054e4c60SAlex Deucher #define ixPB0_PLL_RO2_SCI_STAT_OVRD_REG0 0x1204468 528054e4c60SAlex Deucher #define ixPB0_PLL_RO3_SCI_STAT_OVRD_REG0 0x120446c 529054e4c60SAlex Deucher #define ixPB0_PLL_LC0_CTRL_REG0 0x1204480 530054e4c60SAlex Deucher #define ixPB0_PLL_LC0_OVRD_REG0 0x1204490 531054e4c60SAlex Deucher #define ixPB0_PLL_LC0_OVRD_REG1 0x1204494 532054e4c60SAlex Deucher #define ixPB0_PLL_LC0_SCI_STAT_OVRD_REG0 0x1204500 533054e4c60SAlex Deucher #define ixPB0_PLL_LC1_SCI_STAT_OVRD_REG0 0x1204504 534054e4c60SAlex Deucher #define ixPB0_PLL_LC2_SCI_STAT_OVRD_REG0 0x1204508 535054e4c60SAlex Deucher #define ixPB0_PLL_LC3_SCI_STAT_OVRD_REG0 0x120450c 536054e4c60SAlex Deucher #define ixPB0_RX_GLB_CTRL_REG0 0x1206000 537054e4c60SAlex Deucher #define ixPB0_RX_GLB_CTRL_REG1 0x1206004 538054e4c60SAlex Deucher #define ixPB0_RX_GLB_CTRL_REG2 0x1206008 539054e4c60SAlex Deucher #define ixPB0_RX_GLB_CTRL_REG3 0x120600c 540054e4c60SAlex Deucher #define ixPB0_RX_GLB_CTRL_REG4 0x1206010 541054e4c60SAlex Deucher #define ixPB0_RX_GLB_CTRL_REG5 0x1206014 542054e4c60SAlex Deucher #define ixPB0_RX_GLB_CTRL_REG6 0x1206018 543054e4c60SAlex Deucher #define ixPB0_RX_GLB_CTRL_REG7 0x120601c 544054e4c60SAlex Deucher #define ixPB0_RX_GLB_CTRL_REG8 0x1206020 545054e4c60SAlex Deucher #define ixPB0_RX_GLB_SCI_STAT_OVRD_REG0 0x1206028 546054e4c60SAlex Deucher #define ixPB0_RX_GLB_OVRD_REG0 0x1206030 547054e4c60SAlex Deucher #define ixPB0_RX_GLB_OVRD_REG1 0x1206034 548054e4c60SAlex Deucher #define ixPB0_RX_LANE0_CTRL_REG0 0x1206440 549054e4c60SAlex Deucher #define ixPB0_RX_LANE0_SCI_STAT_OVRD_REG0 0x1206448 550054e4c60SAlex Deucher #define ixPB0_RX_LANE1_CTRL_REG0 0x1206480 551054e4c60SAlex Deucher #define ixPB0_RX_LANE1_SCI_STAT_OVRD_REG0 0x1206488 552054e4c60SAlex Deucher #define ixPB0_RX_LANE2_CTRL_REG0 0x1206500 553054e4c60SAlex Deucher #define ixPB0_RX_LANE2_SCI_STAT_OVRD_REG0 0x1206508 554054e4c60SAlex Deucher #define ixPB0_RX_LANE3_CTRL_REG0 0x1206600 555054e4c60SAlex Deucher #define ixPB0_RX_LANE3_SCI_STAT_OVRD_REG0 0x1206608 556054e4c60SAlex Deucher #define ixPB0_RX_LANE4_CTRL_REG0 0x1206800 557054e4c60SAlex Deucher #define ixPB0_RX_LANE4_SCI_STAT_OVRD_REG0 0x1206848 558054e4c60SAlex Deucher #define ixPB0_RX_LANE5_CTRL_REG0 0x1206880 559054e4c60SAlex Deucher #define ixPB0_RX_LANE5_SCI_STAT_OVRD_REG0 0x1206888 560054e4c60SAlex Deucher #define ixPB0_RX_LANE6_CTRL_REG0 0x1206900 561054e4c60SAlex Deucher #define ixPB0_RX_LANE6_SCI_STAT_OVRD_REG0 0x1206908 562054e4c60SAlex Deucher #define ixPB0_RX_LANE7_CTRL_REG0 0x1206a00 563054e4c60SAlex Deucher #define ixPB0_RX_LANE7_SCI_STAT_OVRD_REG0 0x1206a08 564054e4c60SAlex Deucher #define ixPB0_RX_LANE8_CTRL_REG0 0x1207440 565054e4c60SAlex Deucher #define ixPB0_RX_LANE8_SCI_STAT_OVRD_REG0 0x1207448 566054e4c60SAlex Deucher #define ixPB0_RX_LANE9_CTRL_REG0 0x1207480 567054e4c60SAlex Deucher #define ixPB0_RX_LANE9_SCI_STAT_OVRD_REG0 0x1207488 568054e4c60SAlex Deucher #define ixPB0_RX_LANE10_CTRL_REG0 0x1207500 569054e4c60SAlex Deucher #define ixPB0_RX_LANE10_SCI_STAT_OVRD_REG0 0x1207508 570054e4c60SAlex Deucher #define ixPB0_RX_LANE11_CTRL_REG0 0x1207600 571054e4c60SAlex Deucher #define ixPB0_RX_LANE11_SCI_STAT_OVRD_REG0 0x1207608 572054e4c60SAlex Deucher #define ixPB0_RX_LANE12_CTRL_REG0 0x1207840 573054e4c60SAlex Deucher #define ixPB0_RX_LANE12_SCI_STAT_OVRD_REG0 0x1207848 574054e4c60SAlex Deucher #define ixPB0_RX_LANE13_CTRL_REG0 0x1207880 575054e4c60SAlex Deucher #define ixPB0_RX_LANE13_SCI_STAT_OVRD_REG0 0x1207888 576054e4c60SAlex Deucher #define ixPB0_RX_LANE14_CTRL_REG0 0x1207900 577054e4c60SAlex Deucher #define ixPB0_RX_LANE14_SCI_STAT_OVRD_REG0 0x1207908 578054e4c60SAlex Deucher #define ixPB0_RX_LANE15_CTRL_REG0 0x1207a00 579054e4c60SAlex Deucher #define ixPB0_RX_LANE15_SCI_STAT_OVRD_REG0 0x1207a08 580054e4c60SAlex Deucher #define ixPB0_TX_GLB_CTRL_REG0 0x1208000 581054e4c60SAlex Deucher #define ixPB0_TX_GLB_LANE_SKEW_CTRL 0x1208004 582054e4c60SAlex Deucher #define ixPB0_TX_GLB_SCI_STAT_OVRD_REG0 0x1208010 583054e4c60SAlex Deucher #define ixPB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0 0x1208014 584054e4c60SAlex Deucher #define ixPB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1 0x1208018 585054e4c60SAlex Deucher #define ixPB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2 0x120801c 586054e4c60SAlex Deucher #define ixPB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3 0x1208020 587054e4c60SAlex Deucher #define ixPB0_TX_GLB_OVRD_REG0 0x1208030 588054e4c60SAlex Deucher #define ixPB0_TX_GLB_OVRD_REG1 0x1208034 589054e4c60SAlex Deucher #define ixPB0_TX_GLB_OVRD_REG2 0x1208038 590054e4c60SAlex Deucher #define ixPB0_TX_GLB_OVRD_REG3 0x120803c 591054e4c60SAlex Deucher #define ixPB0_TX_GLB_OVRD_REG4 0x1208040 592054e4c60SAlex Deucher #define ixPB0_TX_LANE0_CTRL_REG0 0x1208440 593054e4c60SAlex Deucher #define ixPB0_TX_LANE0_OVRD_REG0 0x1208444 594054e4c60SAlex Deucher #define ixPB0_TX_LANE0_SCI_STAT_OVRD_REG0 0x1208448 595054e4c60SAlex Deucher #define ixPB0_TX_LANE1_CTRL_REG0 0x1208480 596054e4c60SAlex Deucher #define ixPB0_TX_LANE1_OVRD_REG0 0x1208484 597054e4c60SAlex Deucher #define ixPB0_TX_LANE1_SCI_STAT_OVRD_REG0 0x1208488 598054e4c60SAlex Deucher #define ixPB0_TX_LANE2_CTRL_REG0 0x1208500 599054e4c60SAlex Deucher #define ixPB0_TX_LANE2_OVRD_REG0 0x1208504 600054e4c60SAlex Deucher #define ixPB0_TX_LANE2_SCI_STAT_OVRD_REG0 0x1208508 601054e4c60SAlex Deucher #define ixPB0_TX_LANE3_CTRL_REG0 0x1208600 602054e4c60SAlex Deucher #define ixPB0_TX_LANE3_OVRD_REG0 0x1208604 603054e4c60SAlex Deucher #define ixPB0_TX_LANE3_SCI_STAT_OVRD_REG0 0x1208608 604054e4c60SAlex Deucher #define ixPB0_TX_LANE4_CTRL_REG0 0x1208840 605054e4c60SAlex Deucher #define ixPB0_TX_LANE4_OVRD_REG0 0x1208844 606054e4c60SAlex Deucher #define ixPB0_TX_LANE4_SCI_STAT_OVRD_REG0 0x1208848 607054e4c60SAlex Deucher #define ixPB0_TX_LANE5_CTRL_REG0 0x1208880 608054e4c60SAlex Deucher #define ixPB0_TX_LANE5_OVRD_REG0 0x1208884 609054e4c60SAlex Deucher #define ixPB0_TX_LANE5_SCI_STAT_OVRD_REG0 0x1208888 610054e4c60SAlex Deucher #define ixPB0_TX_LANE6_CTRL_REG0 0x1208900 611054e4c60SAlex Deucher #define ixPB0_TX_LANE6_OVRD_REG0 0x1208904 612054e4c60SAlex Deucher #define ixPB0_TX_LANE6_SCI_STAT_OVRD_REG0 0x1208908 613054e4c60SAlex Deucher #define ixPB0_TX_LANE7_CTRL_REG0 0x1208a00 614054e4c60SAlex Deucher #define ixPB0_TX_LANE7_OVRD_REG0 0x1208a04 615054e4c60SAlex Deucher #define ixPB0_TX_LANE7_SCI_STAT_OVRD_REG0 0x1208a08 616054e4c60SAlex Deucher #define ixPB0_TX_LANE8_CTRL_REG0 0x1209440 617054e4c60SAlex Deucher #define ixPB0_TX_LANE8_OVRD_REG0 0x1209444 618054e4c60SAlex Deucher #define ixPB0_TX_LANE8_SCI_STAT_OVRD_REG0 0x1209448 619054e4c60SAlex Deucher #define ixPB0_TX_LANE9_CTRL_REG0 0x1209480 620054e4c60SAlex Deucher #define ixPB0_TX_LANE9_OVRD_REG0 0x1209484 621054e4c60SAlex Deucher #define ixPB0_TX_LANE9_SCI_STAT_OVRD_REG0 0x1209488 622054e4c60SAlex Deucher #define ixPB0_TX_LANE10_CTRL_REG0 0x1209500 623054e4c60SAlex Deucher #define ixPB0_TX_LANE10_OVRD_REG0 0x1209504 624054e4c60SAlex Deucher #define ixPB0_TX_LANE10_SCI_STAT_OVRD_REG0 0x1209508 625054e4c60SAlex Deucher #define ixPB0_TX_LANE11_CTRL_REG0 0x1209600 626054e4c60SAlex Deucher #define ixPB0_TX_LANE11_OVRD_REG0 0x1209604 627054e4c60SAlex Deucher #define ixPB0_TX_LANE11_SCI_STAT_OVRD_REG0 0x1209608 628054e4c60SAlex Deucher #define ixPB0_TX_LANE12_CTRL_REG0 0x1209840 629054e4c60SAlex Deucher #define ixPB0_TX_LANE12_OVRD_REG0 0x1209844 630054e4c60SAlex Deucher #define ixPB0_TX_LANE12_SCI_STAT_OVRD_REG0 0x1209848 631054e4c60SAlex Deucher #define ixPB0_TX_LANE13_CTRL_REG0 0x1209880 632054e4c60SAlex Deucher #define ixPB0_TX_LANE13_OVRD_REG0 0x1209884 633054e4c60SAlex Deucher #define ixPB0_TX_LANE13_SCI_STAT_OVRD_REG0 0x1209888 634054e4c60SAlex Deucher #define ixPB0_TX_LANE14_CTRL_REG0 0x1209900 635054e4c60SAlex Deucher #define ixPB0_TX_LANE14_OVRD_REG0 0x1209904 636054e4c60SAlex Deucher #define ixPB0_TX_LANE14_SCI_STAT_OVRD_REG0 0x1209908 637054e4c60SAlex Deucher #define ixPB0_TX_LANE15_CTRL_REG0 0x1209a00 638054e4c60SAlex Deucher #define ixPB0_TX_LANE15_OVRD_REG0 0x1209a04 639054e4c60SAlex Deucher #define ixPB0_TX_LANE15_SCI_STAT_OVRD_REG0 0x1209a08 640054e4c60SAlex Deucher #define ixPB1_GLB_CTRL_REG0 0x2200004 641054e4c60SAlex Deucher #define ixPB1_GLB_CTRL_REG1 0x2200008 642054e4c60SAlex Deucher #define ixPB1_GLB_CTRL_REG2 0x220000c 643054e4c60SAlex Deucher #define ixPB1_GLB_CTRL_REG3 0x2200010 644054e4c60SAlex Deucher #define ixPB1_GLB_CTRL_REG4 0x2200014 645054e4c60SAlex Deucher #define ixPB1_GLB_CTRL_REG5 0x2200018 646054e4c60SAlex Deucher #define ixPB1_GLB_SCI_STAT_OVRD_REG0 0x220001c 647054e4c60SAlex Deucher #define ixPB1_GLB_SCI_STAT_OVRD_REG1 0x2200020 648054e4c60SAlex Deucher #define ixPB1_GLB_SCI_STAT_OVRD_REG2 0x2200024 649054e4c60SAlex Deucher #define ixPB1_GLB_SCI_STAT_OVRD_REG3 0x2200028 650054e4c60SAlex Deucher #define ixPB1_GLB_SCI_STAT_OVRD_REG4 0x220002c 651054e4c60SAlex Deucher #define ixPB1_GLB_OVRD_REG0 0x2200030 652054e4c60SAlex Deucher #define ixPB1_GLB_OVRD_REG1 0x2200034 653054e4c60SAlex Deucher #define ixPB1_GLB_OVRD_REG2 0x2200038 654054e4c60SAlex Deucher #define ixPB1_HW_DEBUG 0x2202004 655054e4c60SAlex Deucher #define ixPB1_STRAP_GLB_REG0 0x2202020 656054e4c60SAlex Deucher #define ixPB1_STRAP_TX_REG0 0x2202024 657054e4c60SAlex Deucher #define ixPB1_STRAP_RX_REG0 0x2202028 658054e4c60SAlex Deucher #define ixPB1_STRAP_RX_REG1 0x220202c 659054e4c60SAlex Deucher #define ixPB1_STRAP_PLL_REG0 0x2202030 660054e4c60SAlex Deucher #define ixPB1_STRAP_PIN_REG0 0x2202034 661054e4c60SAlex Deucher #define ixPB1_DFT_JIT_INJ_REG0 0x2203000 662054e4c60SAlex Deucher #define ixPB1_DFT_JIT_INJ_REG1 0x2203004 663054e4c60SAlex Deucher #define ixPB1_DFT_JIT_INJ_REG2 0x2203008 664054e4c60SAlex Deucher #define ixPB1_DFT_DEBUG_CTRL_REG0 0x220300c 665054e4c60SAlex Deucher #define ixPB1_DFT_JIT_INJ_STAT_REG0 0x2203010 666054e4c60SAlex Deucher #define ixPB1_PLL_RO_GLB_CTRL_REG0 0x2204000 667054e4c60SAlex Deucher #define ixPB1_PLL_RO_GLB_OVRD_REG0 0x2204010 668054e4c60SAlex Deucher #define ixPB1_PLL_RO0_CTRL_REG0 0x2204440 669054e4c60SAlex Deucher #define ixPB1_PLL_RO0_OVRD_REG0 0x2204450 670054e4c60SAlex Deucher #define ixPB1_PLL_RO0_OVRD_REG1 0x2204454 671054e4c60SAlex Deucher #define ixPB1_PLL_RO0_SCI_STAT_OVRD_REG0 0x2204460 672054e4c60SAlex Deucher #define ixPB1_PLL_RO1_SCI_STAT_OVRD_REG0 0x2204464 673054e4c60SAlex Deucher #define ixPB1_PLL_RO2_SCI_STAT_OVRD_REG0 0x2204468 674054e4c60SAlex Deucher #define ixPB1_PLL_RO3_SCI_STAT_OVRD_REG0 0x220446c 675054e4c60SAlex Deucher #define ixPB1_PLL_LC0_CTRL_REG0 0x2204480 676054e4c60SAlex Deucher #define ixPB1_PLL_LC0_OVRD_REG0 0x2204490 677054e4c60SAlex Deucher #define ixPB1_PLL_LC0_OVRD_REG1 0x2204494 678054e4c60SAlex Deucher #define ixPB1_PLL_LC0_SCI_STAT_OVRD_REG0 0x2204500 679054e4c60SAlex Deucher #define ixPB1_PLL_LC1_SCI_STAT_OVRD_REG0 0x2204504 680054e4c60SAlex Deucher #define ixPB1_PLL_LC2_SCI_STAT_OVRD_REG0 0x2204508 681054e4c60SAlex Deucher #define ixPB1_PLL_LC3_SCI_STAT_OVRD_REG0 0x220450c 682054e4c60SAlex Deucher #define ixPB1_RX_GLB_CTRL_REG0 0x2206000 683054e4c60SAlex Deucher #define ixPB1_RX_GLB_CTRL_REG1 0x2206004 684054e4c60SAlex Deucher #define ixPB1_RX_GLB_CTRL_REG2 0x2206008 685054e4c60SAlex Deucher #define ixPB1_RX_GLB_CTRL_REG3 0x220600c 686054e4c60SAlex Deucher #define ixPB1_RX_GLB_CTRL_REG4 0x2206010 687054e4c60SAlex Deucher #define ixPB1_RX_GLB_CTRL_REG5 0x2206014 688054e4c60SAlex Deucher #define ixPB1_RX_GLB_CTRL_REG6 0x2206018 689054e4c60SAlex Deucher #define ixPB1_RX_GLB_CTRL_REG7 0x220601c 690054e4c60SAlex Deucher #define ixPB1_RX_GLB_CTRL_REG8 0x2206020 691054e4c60SAlex Deucher #define ixPB1_RX_GLB_SCI_STAT_OVRD_REG0 0x2206028 692054e4c60SAlex Deucher #define ixPB1_RX_GLB_OVRD_REG0 0x2206030 693054e4c60SAlex Deucher #define ixPB1_RX_GLB_OVRD_REG1 0x2206034 694054e4c60SAlex Deucher #define ixPB1_RX_LANE0_CTRL_REG0 0x2206440 695054e4c60SAlex Deucher #define ixPB1_RX_LANE0_SCI_STAT_OVRD_REG0 0x2206448 696054e4c60SAlex Deucher #define ixPB1_RX_LANE1_CTRL_REG0 0x2206480 697054e4c60SAlex Deucher #define ixPB1_RX_LANE1_SCI_STAT_OVRD_REG0 0x2206488 698054e4c60SAlex Deucher #define ixPB1_RX_LANE2_CTRL_REG0 0x2206500 699054e4c60SAlex Deucher #define ixPB1_RX_LANE2_SCI_STAT_OVRD_REG0 0x2206508 700054e4c60SAlex Deucher #define ixPB1_RX_LANE3_CTRL_REG0 0x2206600 701054e4c60SAlex Deucher #define ixPB1_RX_LANE3_SCI_STAT_OVRD_REG0 0x2206608 702054e4c60SAlex Deucher #define ixPB1_RX_LANE4_CTRL_REG0 0x2206800 703054e4c60SAlex Deucher #define ixPB1_RX_LANE4_SCI_STAT_OVRD_REG0 0x2206848 704054e4c60SAlex Deucher #define ixPB1_RX_LANE5_CTRL_REG0 0x2206880 705054e4c60SAlex Deucher #define ixPB1_RX_LANE5_SCI_STAT_OVRD_REG0 0x2206888 706054e4c60SAlex Deucher #define ixPB1_RX_LANE6_CTRL_REG0 0x2206900 707054e4c60SAlex Deucher #define ixPB1_RX_LANE6_SCI_STAT_OVRD_REG0 0x2206908 708054e4c60SAlex Deucher #define ixPB1_RX_LANE7_CTRL_REG0 0x2206a00 709054e4c60SAlex Deucher #define ixPB1_RX_LANE7_SCI_STAT_OVRD_REG0 0x2206a08 710054e4c60SAlex Deucher #define ixPB1_RX_LANE8_CTRL_REG0 0x2207440 711054e4c60SAlex Deucher #define ixPB1_RX_LANE8_SCI_STAT_OVRD_REG0 0x2207448 712054e4c60SAlex Deucher #define ixPB1_RX_LANE9_CTRL_REG0 0x2207480 713054e4c60SAlex Deucher #define ixPB1_RX_LANE9_SCI_STAT_OVRD_REG0 0x2207488 714054e4c60SAlex Deucher #define ixPB1_RX_LANE10_CTRL_REG0 0x2207500 715054e4c60SAlex Deucher #define ixPB1_RX_LANE10_SCI_STAT_OVRD_REG0 0x2207508 716054e4c60SAlex Deucher #define ixPB1_RX_LANE11_CTRL_REG0 0x2207600 717054e4c60SAlex Deucher #define ixPB1_RX_LANE11_SCI_STAT_OVRD_REG0 0x2207608 718054e4c60SAlex Deucher #define ixPB1_RX_LANE12_CTRL_REG0 0x2207840 719054e4c60SAlex Deucher #define ixPB1_RX_LANE12_SCI_STAT_OVRD_REG0 0x2207848 720054e4c60SAlex Deucher #define ixPB1_RX_LANE13_CTRL_REG0 0x2207880 721054e4c60SAlex Deucher #define ixPB1_RX_LANE13_SCI_STAT_OVRD_REG0 0x2207888 722054e4c60SAlex Deucher #define ixPB1_RX_LANE14_CTRL_REG0 0x2207900 723054e4c60SAlex Deucher #define ixPB1_RX_LANE14_SCI_STAT_OVRD_REG0 0x2207908 724054e4c60SAlex Deucher #define ixPB1_RX_LANE15_CTRL_REG0 0x2207a00 725054e4c60SAlex Deucher #define ixPB1_RX_LANE15_SCI_STAT_OVRD_REG0 0x2207a08 726054e4c60SAlex Deucher #define ixPB1_TX_GLB_CTRL_REG0 0x2208000 727054e4c60SAlex Deucher #define ixPB1_TX_GLB_LANE_SKEW_CTRL 0x2208004 728054e4c60SAlex Deucher #define ixPB1_TX_GLB_SCI_STAT_OVRD_REG0 0x2208010 729054e4c60SAlex Deucher #define ixPB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0 0x2208014 730054e4c60SAlex Deucher #define ixPB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1 0x2208018 731054e4c60SAlex Deucher #define ixPB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2 0x220801c 732054e4c60SAlex Deucher #define ixPB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3 0x2208020 733054e4c60SAlex Deucher #define ixPB1_TX_GLB_OVRD_REG0 0x2208030 734054e4c60SAlex Deucher #define ixPB1_TX_GLB_OVRD_REG1 0x2208034 735054e4c60SAlex Deucher #define ixPB1_TX_GLB_OVRD_REG2 0x2208038 736054e4c60SAlex Deucher #define ixPB1_TX_GLB_OVRD_REG3 0x220803c 737054e4c60SAlex Deucher #define ixPB1_TX_GLB_OVRD_REG4 0x2208040 738054e4c60SAlex Deucher #define ixPB1_TX_LANE0_CTRL_REG0 0x2208440 739054e4c60SAlex Deucher #define ixPB1_TX_LANE0_OVRD_REG0 0x2208444 740054e4c60SAlex Deucher #define ixPB1_TX_LANE0_SCI_STAT_OVRD_REG0 0x2208448 741054e4c60SAlex Deucher #define ixPB1_TX_LANE1_CTRL_REG0 0x2208480 742054e4c60SAlex Deucher #define ixPB1_TX_LANE1_OVRD_REG0 0x2208484 743054e4c60SAlex Deucher #define ixPB1_TX_LANE1_SCI_STAT_OVRD_REG0 0x2208488 744054e4c60SAlex Deucher #define ixPB1_TX_LANE2_CTRL_REG0 0x2208500 745054e4c60SAlex Deucher #define ixPB1_TX_LANE2_OVRD_REG0 0x2208504 746054e4c60SAlex Deucher #define ixPB1_TX_LANE2_SCI_STAT_OVRD_REG0 0x2208508 747054e4c60SAlex Deucher #define ixPB1_TX_LANE3_CTRL_REG0 0x2208600 748054e4c60SAlex Deucher #define ixPB1_TX_LANE3_OVRD_REG0 0x2208604 749054e4c60SAlex Deucher #define ixPB1_TX_LANE3_SCI_STAT_OVRD_REG0 0x2208608 750054e4c60SAlex Deucher #define ixPB1_TX_LANE4_CTRL_REG0 0x2208840 751054e4c60SAlex Deucher #define ixPB1_TX_LANE4_OVRD_REG0 0x2208844 752054e4c60SAlex Deucher #define ixPB1_TX_LANE4_SCI_STAT_OVRD_REG0 0x2208848 753054e4c60SAlex Deucher #define ixPB1_TX_LANE5_CTRL_REG0 0x2208880 754054e4c60SAlex Deucher #define ixPB1_TX_LANE5_OVRD_REG0 0x2208884 755054e4c60SAlex Deucher #define ixPB1_TX_LANE5_SCI_STAT_OVRD_REG0 0x2208888 756054e4c60SAlex Deucher #define ixPB1_TX_LANE6_CTRL_REG0 0x2208900 757054e4c60SAlex Deucher #define ixPB1_TX_LANE6_OVRD_REG0 0x2208904 758054e4c60SAlex Deucher #define ixPB1_TX_LANE6_SCI_STAT_OVRD_REG0 0x2208908 759054e4c60SAlex Deucher #define ixPB1_TX_LANE7_CTRL_REG0 0x2208a00 760054e4c60SAlex Deucher #define ixPB1_TX_LANE7_OVRD_REG0 0x2208a04 761054e4c60SAlex Deucher #define ixPB1_TX_LANE7_SCI_STAT_OVRD_REG0 0x2208a08 762054e4c60SAlex Deucher #define ixPB1_TX_LANE8_CTRL_REG0 0x2209440 763054e4c60SAlex Deucher #define ixPB1_TX_LANE8_OVRD_REG0 0x2209444 764054e4c60SAlex Deucher #define ixPB1_TX_LANE8_SCI_STAT_OVRD_REG0 0x2209448 765054e4c60SAlex Deucher #define ixPB1_TX_LANE9_CTRL_REG0 0x2209480 766054e4c60SAlex Deucher #define ixPB1_TX_LANE9_OVRD_REG0 0x2209484 767054e4c60SAlex Deucher #define ixPB1_TX_LANE9_SCI_STAT_OVRD_REG0 0x2209488 768054e4c60SAlex Deucher #define ixPB1_TX_LANE10_CTRL_REG0 0x2209500 769054e4c60SAlex Deucher #define ixPB1_TX_LANE10_OVRD_REG0 0x2209504 770054e4c60SAlex Deucher #define ixPB1_TX_LANE10_SCI_STAT_OVRD_REG0 0x2209508 771054e4c60SAlex Deucher #define ixPB1_TX_LANE11_CTRL_REG0 0x2209600 772054e4c60SAlex Deucher #define ixPB1_TX_LANE11_OVRD_REG0 0x2209604 773054e4c60SAlex Deucher #define ixPB1_TX_LANE11_SCI_STAT_OVRD_REG0 0x2209608 774054e4c60SAlex Deucher #define ixPB1_TX_LANE12_CTRL_REG0 0x2209840 775054e4c60SAlex Deucher #define ixPB1_TX_LANE12_OVRD_REG0 0x2209844 776054e4c60SAlex Deucher #define ixPB1_TX_LANE12_SCI_STAT_OVRD_REG0 0x2209848 777054e4c60SAlex Deucher #define ixPB1_TX_LANE13_CTRL_REG0 0x2209880 778054e4c60SAlex Deucher #define ixPB1_TX_LANE13_OVRD_REG0 0x2209884 779054e4c60SAlex Deucher #define ixPB1_TX_LANE13_SCI_STAT_OVRD_REG0 0x2209888 780054e4c60SAlex Deucher #define ixPB1_TX_LANE14_CTRL_REG0 0x2209900 781054e4c60SAlex Deucher #define ixPB1_TX_LANE14_OVRD_REG0 0x2209904 782054e4c60SAlex Deucher #define ixPB1_TX_LANE14_SCI_STAT_OVRD_REG0 0x2209908 783054e4c60SAlex Deucher #define ixPB1_TX_LANE15_CTRL_REG0 0x2209a00 784054e4c60SAlex Deucher #define ixPB1_TX_LANE15_OVRD_REG0 0x2209a04 785054e4c60SAlex Deucher #define ixPB1_TX_LANE15_SCI_STAT_OVRD_REG0 0x2209a08 786054e4c60SAlex Deucher #define ixPB0_PIF_SCRATCH 0x1100001 787054e4c60SAlex Deucher #define ixPB0_PIF_HW_DEBUG 0x1100002 788054e4c60SAlex Deucher #define ixPB0_PIF_PRG6 0x1100003 789054e4c60SAlex Deucher #define ixPB0_PIF_PRG7 0x1100004 790054e4c60SAlex Deucher #define ixPB0_PIF_CNTL 0x1100010 791054e4c60SAlex Deucher #define ixPB0_PIF_PAIRING 0x1100011 792054e4c60SAlex Deucher #define ixPB0_PIF_PWRDOWN_0 0x1100012 793054e4c60SAlex Deucher #define ixPB0_PIF_PWRDOWN_1 0x1100013 794054e4c60SAlex Deucher #define ixPB0_PIF_CNTL2 0x1100014 795054e4c60SAlex Deucher #define ixPB0_PIF_TXPHYSTATUS 0x1100015 796054e4c60SAlex Deucher #define ixPB0_PIF_SC_CTL 0x1100016 797054e4c60SAlex Deucher #define ixPB0_PIF_PWRDOWN_2 0x1100017 798054e4c60SAlex Deucher #define ixPB0_PIF_PWRDOWN_3 0x1100018 799054e4c60SAlex Deucher #define ixPB0_PIF_SC_CTL2 0x1100019 800054e4c60SAlex Deucher #define ixPB0_PIF_PRG0 0x110001a 801054e4c60SAlex Deucher #define ixPB0_PIF_PRG1 0x110001b 802054e4c60SAlex Deucher #define ixPB0_PIF_PRG2 0x110001c 803054e4c60SAlex Deucher #define ixPB0_PIF_PRG3 0x110001d 804054e4c60SAlex Deucher #define ixPB0_PIF_PRG4 0x110001e 805054e4c60SAlex Deucher #define ixPB0_PIF_PRG5 0x110001f 806054e4c60SAlex Deucher #define ixPB0_PIF_PDNB_OVERRIDE_0 0x1100020 807054e4c60SAlex Deucher #define ixPB0_PIF_PDNB_OVERRIDE_1 0x1100021 808054e4c60SAlex Deucher #define ixPB0_PIF_PDNB_OVERRIDE_2 0x1100022 809054e4c60SAlex Deucher #define ixPB0_PIF_PDNB_OVERRIDE_3 0x1100023 810054e4c60SAlex Deucher #define ixPB0_PIF_PDNB_OVERRIDE_4 0x1100024 811054e4c60SAlex Deucher #define ixPB0_PIF_PDNB_OVERRIDE_5 0x1100025 812054e4c60SAlex Deucher #define ixPB0_PIF_PDNB_OVERRIDE_6 0x1100026 813054e4c60SAlex Deucher #define ixPB0_PIF_PDNB_OVERRIDE_7 0x1100027 814054e4c60SAlex Deucher #define ixPB0_PIF_SEQ_STATUS_0 0x1100028 815054e4c60SAlex Deucher #define ixPB0_PIF_SEQ_STATUS_1 0x1100029 816054e4c60SAlex Deucher #define ixPB0_PIF_SEQ_STATUS_2 0x110002a 817054e4c60SAlex Deucher #define ixPB0_PIF_SEQ_STATUS_3 0x110002b 818054e4c60SAlex Deucher #define ixPB0_PIF_SEQ_STATUS_4 0x110002c 819054e4c60SAlex Deucher #define ixPB0_PIF_SEQ_STATUS_5 0x110002d 820054e4c60SAlex Deucher #define ixPB0_PIF_SEQ_STATUS_6 0x110002e 821054e4c60SAlex Deucher #define ixPB0_PIF_SEQ_STATUS_7 0x110002f 822054e4c60SAlex Deucher #define ixPB0_PIF_PDNB_OVERRIDE_8 0x1100030 823054e4c60SAlex Deucher #define ixPB0_PIF_PDNB_OVERRIDE_9 0x1100031 824054e4c60SAlex Deucher #define ixPB0_PIF_PDNB_OVERRIDE_10 0x1100032 825054e4c60SAlex Deucher #define ixPB0_PIF_PDNB_OVERRIDE_11 0x1100033 826054e4c60SAlex Deucher #define ixPB0_PIF_PDNB_OVERRIDE_12 0x1100034 827054e4c60SAlex Deucher #define ixPB0_PIF_PDNB_OVERRIDE_13 0x1100035 828054e4c60SAlex Deucher #define ixPB0_PIF_PDNB_OVERRIDE_14 0x1100036 829054e4c60SAlex Deucher #define ixPB0_PIF_PDNB_OVERRIDE_15 0x1100037 830054e4c60SAlex Deucher #define ixPB0_PIF_SEQ_STATUS_8 0x1100038 831054e4c60SAlex Deucher #define ixPB0_PIF_SEQ_STATUS_9 0x1100039 832054e4c60SAlex Deucher #define ixPB0_PIF_SEQ_STATUS_10 0x110003a 833054e4c60SAlex Deucher #define ixPB0_PIF_SEQ_STATUS_11 0x110003b 834054e4c60SAlex Deucher #define ixPB0_PIF_SEQ_STATUS_12 0x110003c 835054e4c60SAlex Deucher #define ixPB0_PIF_SEQ_STATUS_13 0x110003d 836054e4c60SAlex Deucher #define ixPB0_PIF_SEQ_STATUS_14 0x110003e 837054e4c60SAlex Deucher #define ixPB0_PIF_SEQ_STATUS_15 0x110003f 838054e4c60SAlex Deucher #define ixPB1_PIF_SCRATCH 0x2100001 839054e4c60SAlex Deucher #define ixPB1_PIF_HW_DEBUG 0x2100002 840054e4c60SAlex Deucher #define ixPB1_PIF_PRG6 0x2100003 841054e4c60SAlex Deucher #define ixPB1_PIF_PRG7 0x2100004 842054e4c60SAlex Deucher #define ixPB1_PIF_CNTL 0x2100010 843054e4c60SAlex Deucher #define ixPB1_PIF_PAIRING 0x2100011 844054e4c60SAlex Deucher #define ixPB1_PIF_PWRDOWN_0 0x2100012 845054e4c60SAlex Deucher #define ixPB1_PIF_PWRDOWN_1 0x2100013 846054e4c60SAlex Deucher #define ixPB1_PIF_CNTL2 0x2100014 847054e4c60SAlex Deucher #define ixPB1_PIF_TXPHYSTATUS 0x2100015 848054e4c60SAlex Deucher #define ixPB1_PIF_SC_CTL 0x2100016 849054e4c60SAlex Deucher #define ixPB1_PIF_PWRDOWN_2 0x2100017 850054e4c60SAlex Deucher #define ixPB1_PIF_PWRDOWN_3 0x2100018 851054e4c60SAlex Deucher #define ixPB1_PIF_SC_CTL2 0x2100019 852054e4c60SAlex Deucher #define ixPB1_PIF_PRG0 0x210001a 853054e4c60SAlex Deucher #define ixPB1_PIF_PRG1 0x210001b 854054e4c60SAlex Deucher #define ixPB1_PIF_PRG2 0x210001c 855054e4c60SAlex Deucher #define ixPB1_PIF_PRG3 0x210001d 856054e4c60SAlex Deucher #define ixPB1_PIF_PRG4 0x210001e 857054e4c60SAlex Deucher #define ixPB1_PIF_PRG5 0x210001f 858054e4c60SAlex Deucher #define ixPB1_PIF_PDNB_OVERRIDE_0 0x2100020 859054e4c60SAlex Deucher #define ixPB1_PIF_PDNB_OVERRIDE_1 0x2100021 860054e4c60SAlex Deucher #define ixPB1_PIF_PDNB_OVERRIDE_2 0x2100022 861054e4c60SAlex Deucher #define ixPB1_PIF_PDNB_OVERRIDE_3 0x2100023 862054e4c60SAlex Deucher #define ixPB1_PIF_PDNB_OVERRIDE_4 0x2100024 863054e4c60SAlex Deucher #define ixPB1_PIF_PDNB_OVERRIDE_5 0x2100025 864054e4c60SAlex Deucher #define ixPB1_PIF_PDNB_OVERRIDE_6 0x2100026 865054e4c60SAlex Deucher #define ixPB1_PIF_PDNB_OVERRIDE_7 0x2100027 866054e4c60SAlex Deucher #define ixPB1_PIF_SEQ_STATUS_0 0x2100028 867054e4c60SAlex Deucher #define ixPB1_PIF_SEQ_STATUS_1 0x2100029 868054e4c60SAlex Deucher #define ixPB1_PIF_SEQ_STATUS_2 0x210002a 869054e4c60SAlex Deucher #define ixPB1_PIF_SEQ_STATUS_3 0x210002b 870054e4c60SAlex Deucher #define ixPB1_PIF_SEQ_STATUS_4 0x210002c 871054e4c60SAlex Deucher #define ixPB1_PIF_SEQ_STATUS_5 0x210002d 872054e4c60SAlex Deucher #define ixPB1_PIF_SEQ_STATUS_6 0x210002e 873054e4c60SAlex Deucher #define ixPB1_PIF_SEQ_STATUS_7 0x210002f 874054e4c60SAlex Deucher #define ixPB1_PIF_PDNB_OVERRIDE_8 0x2100030 875054e4c60SAlex Deucher #define ixPB1_PIF_PDNB_OVERRIDE_9 0x2100031 876054e4c60SAlex Deucher #define ixPB1_PIF_PDNB_OVERRIDE_10 0x2100032 877054e4c60SAlex Deucher #define ixPB1_PIF_PDNB_OVERRIDE_11 0x2100033 878054e4c60SAlex Deucher #define ixPB1_PIF_PDNB_OVERRIDE_12 0x2100034 879054e4c60SAlex Deucher #define ixPB1_PIF_PDNB_OVERRIDE_13 0x2100035 880054e4c60SAlex Deucher #define ixPB1_PIF_PDNB_OVERRIDE_14 0x2100036 881054e4c60SAlex Deucher #define ixPB1_PIF_PDNB_OVERRIDE_15 0x2100037 882054e4c60SAlex Deucher #define ixPB1_PIF_SEQ_STATUS_8 0x2100038 883054e4c60SAlex Deucher #define ixPB1_PIF_SEQ_STATUS_9 0x2100039 884054e4c60SAlex Deucher #define ixPB1_PIF_SEQ_STATUS_10 0x210003a 885054e4c60SAlex Deucher #define ixPB1_PIF_SEQ_STATUS_11 0x210003b 886054e4c60SAlex Deucher #define ixPB1_PIF_SEQ_STATUS_12 0x210003c 887054e4c60SAlex Deucher #define ixPB1_PIF_SEQ_STATUS_13 0x210003d 888054e4c60SAlex Deucher #define ixPB1_PIF_SEQ_STATUS_14 0x210003e 889054e4c60SAlex Deucher #define ixPB1_PIF_SEQ_STATUS_15 0x210003f 890054e4c60SAlex Deucher #define mmBIF_RFE_SNOOP_REG 0x27 891054e4c60SAlex Deucher #define mmBIF_RFE_WARMRST_CNTL 0x1459 892054e4c60SAlex Deucher #define mmBIF_RFE_SOFTRST_CNTL 0x1441 893054e4c60SAlex Deucher #define mmBIF_RFE_IMPRST_CNTL 0x1458 894054e4c60SAlex Deucher #define mmBIF_RFE_CLIENT_SOFTRST_TRIGGER 0x1442 895054e4c60SAlex Deucher #define mmBIF_RFE_MASTER_SOFTRST_TRIGGER 0x1443 896054e4c60SAlex Deucher #define mmBIF_PWDN_COMMAND 0x1444 897054e4c60SAlex Deucher #define mmBIF_PWDN_STATUS 0x1445 898054e4c60SAlex Deucher #define mmBIF_RFE_MST_BU_CMDSTATUS 0x1446 899054e4c60SAlex Deucher #define mmBIF_RFE_MST_RWREG_RFEWDBIF_CMDSTATUS 0x1447 900054e4c60SAlex Deucher #define mmBIF_RFE_MST_BX_CMDSTATUS 0x1448 901054e4c60SAlex Deucher #define mmBIF_RFE_MST_TMOUT_STATUS 0x144b 902054e4c60SAlex Deucher #define mmBIF_RFE_MMCFG_CNTL 0x144c 903054e4c60SAlex Deucher #define mmBIF_CC_RFE_IMP_OVERRIDECNTL 0x1455 904054e4c60SAlex Deucher #define mmBIF_IMPCTL_SMPLCNTL 0x1450 905054e4c60SAlex Deucher #define mmBIF_IMPCTL_RXCNTL 0x1451 906054e4c60SAlex Deucher #define mmBIF_IMPCTL_TXCNTL_pd 0x1452 907054e4c60SAlex Deucher #define mmBIF_IMPCTL_TXCNTL_pu 0x1453 908054e4c60SAlex Deucher #define mmBIF_IMPCTL_CONTINUOUS_CALIBRATION_PERIOD 0x1454 909054e4c60SAlex Deucher #define mmBIF_CLOCKS_BITS 0x1489 910054e4c60SAlex Deucher #define mmBIF_LNCNT_RESET 0x1488 911054e4c60SAlex Deucher #define mmLNCNT_CONTROL 0x1487 912054e4c60SAlex Deucher #define mmNEW_REFCLKB_TIMER 0x1485 913054e4c60SAlex Deucher #define mmNEW_REFCLKB_TIMER_1 0x1484 914054e4c60SAlex Deucher #define mmBIF_CLK_PDWN_DELAY_TIMER 0x1483 915054e4c60SAlex Deucher #define mmBIF_RESET_EN 0x1482 916054e4c60SAlex Deucher #define mmBIF_PIF_TXCLK_SWITCH_TIMER 0x1481 917054e4c60SAlex Deucher #define mmBIF_BACO_MSIC 0x1480 918054e4c60SAlex Deucher #define mmBIF_RESET_CNTL 0x1486 919054e4c60SAlex Deucher #define mmBIF_RFE_CNTL_MISC 0x148c 920054e4c60SAlex Deucher 921054e4c60SAlex Deucher #endif /* BIF_4_1_D_H */ 922